content
stringlengths 1
1.04M
⌀ |
|---|
/* Using vhdl 2008 comments. */
entity simple08 is
end;
architecture behav of simple08 is
begin
process
begin
assert false report "Test is running" severity note;
wait; -- Indefinite
end process;
end behav;
|
--
-- File Name: CoveragePkg.vhd
-- Design Unit Name: CoveragePkg
-- Revision: STANDARD VERSION
--
-- Maintainer: Jim Lewis email: [email protected]
-- Contributor(s):
-- Jim Lewis SynthWorks
-- Matthias Alles Creonic. Inspired GetMinBinVal, GetMinPoint, GetCov
-- Jerry Kaczynski Aldec. Inspired GetBin function
-- Sebastian Dunst Inspired GetBinName function
-- ... Aldec Worked on VendorCov functional coverage interface
--
-- Package Defines
-- Functional coverage modeling utilities and data structure
--
-- Developed by/for:
-- SynthWorks Design Inc.
-- VHDL Training Classes
-- 11898 SW 128th Ave. Tigard, Or 97223
-- http://www.SynthWorks.com
--
-- Revision History:
-- Date Version Description
-- 02/2022 2022.02 Updated NewID with ParentID, ReportMode, Search, PrintParent.
-- Supports searching for coverage models.
-- 01/2022 2022.01 Added DeallocateBins and TCover
-- Updated AddBins and AddCross s.t. can set AtLeast and Weight to 0
-- GenBin defaults AtLeast and Weight to 0. AddBins and AddCross to 1.
-- 12/2021 2021.12 Added ReadCovYaml
-- 11/2021 2021.11 Updated WriteCovYaml to write CovWeight first.
-- Updated GetCov calculation with PercentCov.
-- 10/2021 2021.10 Added WriteCovYaml to write out coverage as a YAML file
-- 08/2021 2021.08 Removed SetAlertLogID from singleton public interface - set instead by NewID
-- Moved SetName, SetMessage to deprecated
-- Moved AddBins, AddCross, GenBin, and GenCross with weight parameter to deprecated
-- 07/2021 2021.07 Updated for new data structure
-- 07/2020 2020.07 Adjusted NextPointModeType: Changed MIN to MODE_MINIMUM.
-- The preferred MINIMUM will not work in some tools
-- Added GetNext{Index, BinVal, Point}[(Mode => {RANDOM|INCREMENT|MODE_MINIMUM})]
-- Added NextPointModeType = (RANDOM, INCREMENT, MODE_MINIMUM)
-- Added SetNextPointMode[(Mode => {RANDOM|INCREMENT|MODE_MINIMUM})
-- 05/2020 2020.05 Updated LastIndex to also be set during ICover.
-- Updated deallocate to set all variables to their initial value
-- Added GetInc{Index, BinVal, Point}
-- Added GetNext{Index, BinVal, Point}[(Mode => {RANDOM|INCREMENT|MIN})]
-- Added NextPointModeType = (RANDOM, INCREMENT, MODE_MINIMUM)
-- Added SetNextPointMode[(Mode => {RANDOM|INCREMENT|MODE_MINIMUM})
-- Added to_std_logic(integer), to_boolean(integer) + vector forms
-- RandCov{Point|BinVal} is deprecated, renamed to GetRand{Point|BinVal}
-- 01/2020 2020.01 Updated Licenses to Apache
-- 04/2018 2018.04 Updated PercentCov calculation so AtLeast of <= 0 is correct
-- String' Fix for GHDL
-- Removed Deprecated procedure Increment - see TbUtilPkg as it moved there
-- 05/2017 2017.05 Updated WriteBin name printing
-- ClearCov (deprecates SetCovZero)
-- 11/2016 2016.11 Added VendorCovApiPkg and calls to bind it in.
-- 03/2016 2016.03 Added GetBinName(Index) to retrieve a bin's name
-- 01/2016 2016.01 Fixes for pure functions. Added bounds checking on ICover
-- 06/2015 2015.06 AddCross[CovMatrix?Type], Mirroring for WriteBin
-- 01/2015 2015.01 Use AlertLogPkg to count assertions and filter log messages
-- 12/2014 2014.07a Fix memory leak in deallocate. Removed initialied pointers which can lead to leaks.
-- 7/2014 2014.07 Bin Naming (for requirements tracking), WriteBin with Pass/Fail, GenBin[integer_vector]
-- 1/2014 2014.01 Merging of Cov Models, LastIndex
-- 5/2013 2013.05 Release with updated RandomPkg. Minimal changes.
-- 04/2013: 2013.04 Thresholding, CovTarget, Merging off by default,
-- 01/2012: 2.4 Added Merging of bins
-- 01/2012: 2.3 Added Function GetBin from Jerry K. Made write for RangeArrayType visible
-- 12/2011: 2.2b Fixed minor inconsistencies on interface declarations.
-- 11/2011: 2.2a Changed constants ALL_RANGE, ZERO_BIN, and ONE_BIN to have a 1 index
-- 07/2011: 2.2 Added randomization with coverage goals (AtLeast), weight, and percentage thresholds
-- 06/2011: 2.1 Removed signal based coverage modeling
-- 04/2011: 2.0 Added protected type based data structure: CovPType
-- 02/2011: 1.1 Added GetMinCov, GetMaxCov, CountCovHoles, GetCovHole
-- 02/2011: 1.0 Changed CoverBinType to facilitage long term support of cross coverage
-- 09/2010 Release in SynthWorks' VHDL Testbenches and Verification classes
-- 06/2010: 0.1 Initial revision
--
--
-- Development Notes:
-- The coverage procedures are named ICover to avoid conflicts with
-- future language changes which may add cover as a keyword
-- Procedure WriteBin writes each CovBin on a separate line, as such
-- it was inappropriate to overload either textio write or to_string
-- In the notes VHDL-2008 notes refers to
-- composites with unconstrained elements
--
--
-- This file is part of OSVVM.
--
-- Copyright (c) 2010 - 2022 by SynthWorks Design Inc.
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- https://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
--
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.numeric_std.all ;
use ieee.math_real.all ;
use std.textio.all ;
-- comment out following 2 lines with VHDL-2008. Leave in for VHDL-2002
-- library ieee_proposed ; -- remove with VHDL-2008
-- use ieee_proposed.standard_additions.all ; -- remove with VHDL-2008
use work.TextUtilPkg.all ;
use work.TranscriptPkg.all ;
use work.AlertLogPkg.all ;
use work.RandomBasePkg.all ;
use work.RandomProcedurePkg.all ;
use work.RandomPkg.all ;
use work.NamePkg.all ;
use work.NameStorePkg.all ;
use work.MessageListPkg.all ;
use work.OsvvmGlobalPkg.all ;
use work.VendorCovApiPkg.all ;
package CoveragePkg is
type CoverageIDType is record
ID : integer ;
end record CoverageIDType ;
type CoverageIDArrayType is array (integer range <>) of CoverageIDType ;
constant OSVVM_COVERAGE_ALERTLOG_ID : AlertLogIDType := OSVVM_ALERTLOG_ID ;
-- CovPType allocates bins that are multiples of MIN_NUM_BINS
constant MIN_NUM_BINS : integer := 2**7 ; -- power of 2
type RangeType is record
min : integer ;
max : integer ;
end record ;
type RangeArrayType is array (integer range <>) of RangeType ;
constant ALL_RANGE : RangeArrayType := (1=>(Integer'left, Integer'right)) ;
procedure write ( file f : text ; BinVal : RangeArrayType ) ;
procedure write ( variable buf : inout line ; constant BinVal : in RangeArrayType) ;
-- CovBinBaseType.action values.
-- Note that coverage counting depends on these values
constant COV_COUNT : integer := 1 ;
constant COV_IGNORE : integer := 0 ;
constant COV_ILLEGAL : integer := -1 ;
-- -- type OsvvmOptionsType is (OPT_DEFAULT, FALSE, TRUE) ;
-- alias OsvvmOptionsType is work.OsvvmGlobalPkg.OsvvmOptionsType ;
constant COV_OPT_INIT_PARM_DETECT : OsvvmOptionsType := OPT_INIT_PARM_DETECT ;
-- -- For backward compatibility. Don't add to other packages.
-- alias DISABLED is work.OsvvmGlobalPkg.DISABLED [return work.OsvvmGlobalPkg.OsvvmOptionsType ];
-- alias ENABLED is work.OsvvmGlobalPkg.ENABLED [return work.OsvvmGlobalPkg.OsvvmOptionsType ];
-- Deprecated
-- Used for easy manual entry. Order: min, max, action
-- Intentionally did not use a record to allow other input
-- formats in the future with VHDL-2008 unconstrained arrays
-- of unconstrained elements
-- type CovBinManualType is array (natural range <>) of integer_vector(0 to 2) ;
type CovBinBaseType is record
BinVal : RangeArrayType(1 to 1) ;
Action : integer ;
Count : integer ;
AtLeast : integer ;
Weight : integer ;
end record ;
type CovBinType is array (natural range <>) of CovBinBaseType ;
constant ALL_BIN : CovBinType := (0 => ( BinVal => ALL_RANGE, Action => COV_COUNT, Count => 0, AtLeast => 1, Weight => 1 )) ;
constant ALL_COUNT : CovBinType := (0 => ( BinVal => ALL_RANGE, Action => COV_COUNT, Count => 0, AtLeast => 1, Weight => 1 )) ;
constant ALL_ILLEGAL : CovBinType := (0 => ( BinVal => ALL_RANGE, Action => COV_ILLEGAL, Count => 0, AtLeast => 0, Weight => 0 )) ;
constant ALL_IGNORE : CovBinType := (0 => ( BinVal => ALL_RANGE, Action => COV_IGNORE, Count => 0, AtLeast => 0, Weight => 0 )) ;
constant ZERO_BIN : CovBinType := (0 => ( BinVal => (1=>(0,0)), Action => COV_COUNT, Count => 0, AtLeast => 1, Weight => 1 )) ;
constant ONE_BIN : CovBinType := (0 => ( BinVal => (1=>(1,1)), Action => COV_COUNT, Count => 0, AtLeast => 1, Weight => 1 )) ;
constant NULL_BIN : CovBinType(work.RandomBasePkg.NULL_RANGE_TYPE) := (others => ( BinVal => ALL_RANGE, Action => integer'high, Count => 0, AtLeast => integer'high, Weight => integer'high )) ;
type NextPointModeType is (RANDOM, INCREMENT, MODE_MINIMUM) ;
type CountModeType is (COUNT_FIRST, COUNT_ALL) ;
type IllegalModeType is (ILLEGAL_ON, ILLEGAL_FAILURE, ILLEGAL_OFF) ;
-- WeightModeType other than AT_LEAST or REMAIN is deprecated
type WeightModeType is (AT_LEAST, REMAIN, WEIGHT, REMAIN_EXP, REMAIN_SCALED, REMAIN_WEIGHT ) ;
-- In VHDL-2008 CovMatrix?BaseType and CovMatrix?Type will be subsumed
-- by CovBinBaseType and CovBinType with RangeArrayType as an unconstrained array.
type CovMatrix2BaseType is record
BinVal : RangeArrayType(1 to 2) ;
Action : integer ;
Count : integer ;
AtLeast : integer ;
Weight : integer ;
end record ;
type CovMatrix2Type is array (natural range <>) of CovMatrix2BaseType ;
type CovMatrix3BaseType is record
BinVal : RangeArrayType(1 to 3) ;
Action : integer ;
Count : integer ;
AtLeast : integer ;
Weight : integer ;
end record ;
type CovMatrix3Type is array (natural range <>) of CovMatrix3BaseType ;
type CovMatrix4BaseType is record
BinVal : RangeArrayType(1 to 4) ;
Action : integer ;
Count : integer ;
AtLeast : integer ;
Weight : integer ;
end record ;
type CovMatrix4Type is array (natural range <>) of CovMatrix4BaseType ;
type CovMatrix5BaseType is record
BinVal : RangeArrayType(1 to 5) ;
Action : integer ;
Count : integer ;
AtLeast : integer ;
Weight : integer ;
end record ;
type CovMatrix5Type is array (natural range <>) of CovMatrix5BaseType ;
type CovMatrix6BaseType is record
BinVal : RangeArrayType(1 to 6) ;
Action : integer ;
Count : integer ;
AtLeast : integer ;
Weight : integer ;
end record ;
type CovMatrix6Type is array (natural range <>) of CovMatrix6BaseType ;
type CovMatrix7BaseType is record
BinVal : RangeArrayType(1 to 7) ;
Action : integer ;
Count : integer ;
AtLeast : integer ;
Weight : integer ;
end record ;
type CovMatrix7Type is array (natural range <>) of CovMatrix7BaseType ;
type CovMatrix8BaseType is record
BinVal : RangeArrayType(1 to 8) ;
Action : integer ;
Count : integer ;
AtLeast : integer ;
Weight : integer ;
end record ;
type CovMatrix8Type is array (natural range <>) of CovMatrix8BaseType ;
type CovMatrix9BaseType is record
BinVal : RangeArrayType(1 to 9) ;
Action : integer ;
Count : integer ;
AtLeast : integer ;
Weight : integer ;
end record ;
type CovMatrix9Type is array (natural range <>) of CovMatrix9BaseType ;
------------------------------------------------------------ VendorCov
-- VendorCov Conversion for Vendor supported functional coverage modeling
function ToVendorCovBinVal (BinVal : RangeArrayType) return VendorCovRangeArrayType ;
------------------------------------------------------------
function ToMinPoint (A : RangeArrayType) return integer ;
function ToMinPoint (A : RangeArrayType) return integer_vector ;
-- BinVal to Minimum Point
------------------------------------------------------------
procedure ToRandPoint(
-- BinVal to Random Point
-- better as a function, however, inout not supported on functions
------------------------------------------------------------
variable RV : inout RandomPType ;
constant BinVal : in RangeArrayType ;
variable result : out integer
) ;
------------------------------------------------------------
procedure ToRandPoint(
-- BinVal to Random Point
------------------------------------------------------------
variable RV : inout RandomPType ;
constant BinVal : in RangeArrayType ;
variable result : out integer_vector
) ;
------------------------------------------------------------
impure function NewID (
Name : String ;
ParentID : AlertLogIDType := OSVVM_COVERAGE_ALERTLOG_ID ;
ReportMode : AlertLogReportModeType := ENABLED ;
Search : NameSearchType := NAME_AND_PARENT_ELSE_PRIVATE ;
PrintParent : AlertLogPrintParentType := PRINT_NAME_AND_PARENT
) return CoverageIDType ;
------------------------------------------------------------
-- /////////////////////////////////////////
-- Coverage Global Settings Common to All Coverage Models
-- /////////////////////////////////////////
------------------------------------------------------------
procedure FileOpenWriteBin (FileName : string; OpenKind : File_Open_Kind ) ;
procedure FileCloseWriteBin ;
-- procedure WriteToCovFile (variable buf : inout line) ;
procedure PrintToCovFile(S : string) ;
------------------------------------------------------------
procedure SetReportOptions (
------------------------------------------------------------
WritePassFail : OsvvmOptionsType := COV_OPT_INIT_PARM_DETECT ;
WriteBinInfo : OsvvmOptionsType := COV_OPT_INIT_PARM_DETECT ;
WriteCount : OsvvmOptionsType := COV_OPT_INIT_PARM_DETECT ;
WriteAnyIllegal : OsvvmOptionsType := COV_OPT_INIT_PARM_DETECT ;
WritePrefix : string := OSVVM_STRING_INIT_PARM_DETECT ;
PassName : string := OSVVM_STRING_INIT_PARM_DETECT ;
FailName : string := OSVVM_STRING_INIT_PARM_DETECT
) ;
procedure ResetReportOptions ;
------------------------------------------------------------
-- /////////////////////////////////////////
-- Coverage Model Settings
-- /////////////////////////////////////////
------------------------------------------------------------
-- AlertLogID set by NewID
-- procedure SetAlertLogID (ID : CoverageIDType; A : AlertLogIDType) ;
-- procedure SetAlertLogID (ID : CoverageIDType; Name : string ; ParentID : AlertLogIDType := ALERTLOG_BASE_ID ; CreateHierarchy : Boolean := TRUE) ;
impure function GetAlertLogID (ID : CoverageIDType) return AlertLogIDType ;
------------------------------------------------------------
-- Name set by NewID
impure function GetName (ID : CoverageIDType) return String ;
impure function GetCovModelName (ID : CoverageIDType) return String ;
impure function GetNamePlus (ID : CoverageIDType; prefix, suffix : string) return String ;
procedure SetItemBinNames (
ID : CoverageIDType ;
Name1 : String ;
Name2, Name3, Name4, Name5,
Name6, Name7, Name8, Name9, Name10,
Name11, Name12, Name13, Name14, Name15,
Name16, Name17, Name18, Name19, Name20 : string := ""
) ;
alias SetFieldName is SetItemBinNames [CoverageIDType,
string, string, string, string, string, string, string, string, string, string,
string, string, string, string, string, string, string, string, string, string] ;
procedure SetCovTarget (ID : CoverageIDType; Percent : real) ;
impure function GetCovTarget (ID : CoverageIDType) return real ;
procedure SetThresholding (ID : CoverageIDType; A : boolean := TRUE ) ;
procedure SetCovThreshold (ID : CoverageIDType; Percent : real) ;
procedure SetMerging (ID : CoverageIDType; A : boolean := TRUE ) ;
procedure SetCountMode (ID : CoverageIDType; A : CountModeType) ;
procedure SetIllegalMode (ID : CoverageIDType; A : IllegalModeType) ;
procedure SetNextPointMode (ID : CoverageIDType; A : NextPointModeType) ;
--
-- SetWeightMode with a WeightMode other than AT_LEAST or REMAIN is deprecated
-- SetWeightMode with a WeightScale parameter is deprecated
procedure SetWeightMode (ID : CoverageIDType; WeightMode : WeightModeType; WeightScale : real := 1.0) ;
procedure SetCovWeight (ID : CoverageIDType; Weight : integer) ;
impure function GetCovWeight (ID : CoverageIDType) return integer ;
------------------------------------------------------------
-- Seeds are initialized by NewID.
procedure InitSeed (ID : CoverageIDType; S : string; UseNewSeedMethods : boolean := TRUE) ;
impure function InitSeed (ID : CoverageIDType; S : string; UseNewSeedMethods : boolean := TRUE ) return string ;
procedure InitSeed (ID : CoverageIDType; I : integer; UseNewSeedMethods : boolean := TRUE ) ;
------------------------------------------------------------
procedure SetSeed (ID : CoverageIDType; RandomSeedIn : RandomSeedType ) ;
impure function GetSeed (ID : CoverageIDType) return RandomSeedType ;
------------------------------------------------------------
-- /////////////////////////////////////////
-- Item / Cross Bin Creation and Destruction
-- /////////////////////////////////////////
------------------------------------------------------------
procedure SetBinSize (ID : CoverageIDType; NewNumBins : integer) ;
procedure Deallocate (ID : CoverageIDType) ;
procedure DeallocateBins (CoverID : CoverageIDType) ;
------------------------------------------------------------
procedure AddBins (
------------------------------------------------------------
ID : CoverageIDType ;
Name : String ;
AtLeast : integer ;
CovBin : CovBinType
) ;
procedure AddBins (ID : CoverageIDType; Name : String ; CovBin : CovBinType) ;
procedure AddBins (ID : CoverageIDType; AtLeast : integer ; CovBin : CovBinType ) ;
procedure AddBins (ID : CoverageIDType; CovBin : CovBinType ) ;
------------------------------------------------------------
procedure AddCross(
------------------------------------------------------------
ID : CoverageIDType ;
Name : string ;
AtLeast : integer ;
Bin1, Bin2 : CovBinType ;
Bin3, Bin4, Bin5, Bin6, Bin7, Bin8, Bin9, Bin10, Bin11, Bin12, Bin13,
Bin14, Bin15, Bin16, Bin17, Bin18, Bin19, Bin20 : CovBinType := NULL_BIN
) ;
------------------------------------------------------------
procedure AddCross(
------------------------------------------------------------
ID : CoverageIDType ;
Name : string ;
Bin1, Bin2 : CovBinType ;
Bin3, Bin4, Bin5, Bin6, Bin7, Bin8, Bin9, Bin10, Bin11, Bin12, Bin13,
Bin14, Bin15, Bin16, Bin17, Bin18, Bin19, Bin20 : CovBinType := NULL_BIN
) ;
------------------------------------------------------------
procedure AddCross(
------------------------------------------------------------
ID : CoverageIDType ;
AtLeast : integer ;
Bin1, Bin2 : CovBinType ;
Bin3, Bin4, Bin5, Bin6, Bin7, Bin8, Bin9, Bin10, Bin11, Bin12, Bin13,
Bin14, Bin15, Bin16, Bin17, Bin18, Bin19, Bin20 : CovBinType := NULL_BIN
) ;
------------------------------------------------------------
procedure AddCross(
------------------------------------------------------------
ID : CoverageIDType ;
Bin1, Bin2 : CovBinType ;
Bin3, Bin4, Bin5, Bin6, Bin7, Bin8, Bin9, Bin10, Bin11, Bin12, Bin13,
Bin14, Bin15, Bin16, Bin17, Bin18, Bin19, Bin20 : CovBinType := NULL_BIN
) ;
------------------------------------------------------------
-- AddCross for usage with constants created by GenCross
------------------------------------------------------------
procedure AddCross (ID : CoverageIDType; CovBin : CovMatrix2Type ; Name : String := "") ;
procedure AddCross (ID : CoverageIDType; CovBin : CovMatrix3Type ; Name : String := "") ;
procedure AddCross (ID : CoverageIDType; CovBin : CovMatrix4Type ; Name : String := "") ;
procedure AddCross (ID : CoverageIDType; CovBin : CovMatrix5Type ; Name : String := "") ;
procedure AddCross (ID : CoverageIDType; CovBin : CovMatrix6Type ; Name : String := "") ;
procedure AddCross (ID : CoverageIDType; CovBin : CovMatrix7Type ; Name : String := "") ;
procedure AddCross (ID : CoverageIDType; CovBin : CovMatrix8Type ; Name : String := "") ;
procedure AddCross (ID : CoverageIDType; CovBin : CovMatrix9Type ; Name : String := "") ;
------------------------------------------------------------
-- /////////////////////////////////////////
-- Recording and Clearing Coverage
-- /////////////////////////////////////////
------------------------------------------------------------
------------------------------------------------------------
procedure ICoverLast (ID : CoverageIDType) ;
procedure ICover (ID : CoverageIDType; CovPoint : integer_vector) ;
procedure ICover (ID : CoverageIDType; CovPoint : integer) ;
procedure TCover (CoverID : CoverageIDType; A : integer) ;
procedure ClearCov (ID : CoverageIDType) ;
------------------------------------------------------------
-- /////////////////////////////////////////
-- Coverage Information and Statistics
-- /////////////////////////////////////////
------------------------------------------------------------
------------------------------------------------------------
impure function IsCovered (ID : CoverageIDType; PercentCov : real ) return boolean ;
impure function IsCovered (ID : CoverageIDType) return boolean ;
impure function IsInitialized (ID : CoverageIDType) return boolean ;
------------------------------------------------------------
impure function GetItemCount (ID : CoverageIDType) return integer ;
impure function GetCov (ID : CoverageIDType; PercentCov : real ) return real ;
impure function GetCov (ID : CoverageIDType) return real ;
impure function GetTotalCovCount(ID : CoverageIDType; PercentCov : real ) return integer ;
impure function GetTotalCovCount(ID : CoverageIDType) return integer ;
impure function GetTotalCovGoal (ID : CoverageIDType; PercentCov : real ) return integer ;
impure function GetTotalCovGoal (ID : CoverageIDType) return integer ;
------------------------------------------------------------
impure function GetMinCov (ID : CoverageIDType) return real ;
impure function GetMinCount (ID : CoverageIDType) return integer ;
impure function GetMaxCov (ID : CoverageIDType) return real ;
impure function GetMaxCount (ID : CoverageIDType) return integer ;
------------------------------------------------------------
impure function CountCovHoles (ID : CoverageIDType; PercentCov : real ) return integer ;
impure function CountCovHoles (ID : CoverageIDType) return integer ;
------------------------------------------------------------
-- /////////////////////////////////////////
-- Generating Coverage Points, BinValues, and Indices
-- /////////////////////////////////////////
------------------------------------------------------------
-- Return Points
------------------------------------------------------------
-- to be replaced in VHDL-2019 by version that uses RandomSeed as an inout
impure function ToRandPoint (ID : CoverageIDType; BinVal : RangeArrayType ) return integer ;
impure function ToRandPoint (ID : CoverageIDType; BinVal : RangeArrayType ) return integer_vector ;
------------------------------------------------------------
-- Return Points
impure function GetPoint (ID : CoverageIDType; BinIndex : integer ) return integer ;
impure function GetPoint (ID : CoverageIDType; BinIndex : integer ) return integer_vector ;
impure function GetRandPoint (ID : CoverageIDType) return integer ;
impure function GetRandPoint (ID : CoverageIDType; PercentCov : real ) return integer ;
impure function GetRandPoint (ID : CoverageIDType) return integer_vector ;
impure function GetRandPoint (ID : CoverageIDType; PercentCov : real ) return integer_vector ;
impure function GetIncPoint (ID : CoverageIDType) return integer ;
impure function GetIncPoint (ID : CoverageIDType) return integer_vector ;
impure function GetMinPoint (ID : CoverageIDType) return integer ;
impure function GetMinPoint (ID : CoverageIDType) return integer_vector ;
impure function GetMaxPoint (ID : CoverageIDType) return integer ;
impure function GetMaxPoint (ID : CoverageIDType) return integer_vector ;
impure function GetNextPoint (ID : CoverageIDType; Mode : NextPointModeType) return integer ;
impure function GetNextPoint (ID : CoverageIDType; Mode : NextPointModeType) return integer_vector ;
impure function GetNextPoint (ID : CoverageIDType) return integer ;
impure function GetNextPoint (ID : CoverageIDType) return integer_vector ;
------------------------------------------------------------
-- deprecated, see GetRandPoint
impure function RandCovPoint (ID : CoverageIDType) return integer ;
impure function RandCovPoint (ID : CoverageIDType; PercentCov : real ) return integer ;
impure function RandCovPoint (ID : CoverageIDType) return integer_vector ;
impure function RandCovPoint (ID : CoverageIDType; PercentCov : real ) return integer_vector ;
------------------------------------------------------------
-- Return BinVals
impure function GetBinVal (ID : CoverageIDType; BinIndex : integer ) return RangeArrayType ;
impure function GetRandBinVal (ID : CoverageIDType; PercentCov : real ) return RangeArrayType ;
impure function GetRandBinVal (ID : CoverageIDType) return RangeArrayType ;
impure function GetLastBinVal (ID : CoverageIDType) return RangeArrayType ;
impure function GetIncBinVal (ID : CoverageIDType) return RangeArrayType ;
impure function GetMinBinVal (ID : CoverageIDType) return RangeArrayType ;
impure function GetMaxBinVal (ID : CoverageIDType) return RangeArrayType ;
impure function GetNextBinVal (ID : CoverageIDType; Mode : NextPointModeType) return RangeArrayType ;
impure function GetNextBinVal (ID : CoverageIDType) return RangeArrayType ;
impure function GetHoleBinVal (ID : CoverageIDType; ReqHoleNum : integer ; PercentCov : real ) return RangeArrayType ;
impure function GetHoleBinVal (ID : CoverageIDType; PercentCov : real ) return RangeArrayType ;
impure function GetHoleBinVal (ID : CoverageIDType; ReqHoleNum : integer := 1 ) return RangeArrayType ;
-- deprecated RandCovBinVal, see GetRandBinVal
impure function RandCovBinVal (ID : CoverageIDType; PercentCov : real ) return RangeArrayType ;
impure function RandCovBinVal (ID : CoverageIDType) return RangeArrayType ;
-- Return Index Values
------------------------------------------------------------
impure function GetNumBins (ID : CoverageIDType) return integer ;
impure function GetRandIndex (ID : CoverageIDType; CovTargetPercent : real ) return integer ;
impure function GetRandIndex (ID : CoverageIDType) return integer ;
impure function GetLastIndex (ID : CoverageIDType) return integer ;
impure function GetIncIndex (ID : CoverageIDType) return integer ;
impure function GetMinIndex (ID : CoverageIDType) return integer ;
impure function GetMaxIndex (ID : CoverageIDType) return integer ;
impure function GetNextIndex (ID : CoverageIDType; Mode : NextPointModeType) return integer ;
impure function GetNextIndex (ID : CoverageIDType) return integer ;
------------------------------------------------------------
-- /////////////////////////////////////////
-- Accessing Coverage Bin Information
-- /////////////////////////////////////////
------------------------------------------------------------
-- ------------------------------------------------------------
-- Intended as a stand in until we get a more general GetBin
impure function GetBinInfo (ID : CoverageIDType; BinIndex : integer ) return CovBinBaseType ;
-- ------------------------------------------------------------
-- Intended as a stand in until we get a more general GetBin
impure function GetBinValLength (ID : CoverageIDType) return integer ;
-- ------------------------------------------------------------
-- Eventually the multiple GetBin functions will be replaced by a
-- a single GetBin that returns CovBinBaseType with BinVal as an
-- unconstrained element
impure function GetBin (ID : CoverageIDType; BinIndex : integer ) return CovBinBaseType ;
impure function GetBin (ID : CoverageIDType; BinIndex : integer ) return CovMatrix2BaseType ;
impure function GetBin (ID : CoverageIDType; BinIndex : integer ) return CovMatrix3BaseType ;
impure function GetBin (ID : CoverageIDType; BinIndex : integer ) return CovMatrix4BaseType ;
impure function GetBin (ID : CoverageIDType; BinIndex : integer ) return CovMatrix5BaseType ;
impure function GetBin (ID : CoverageIDType; BinIndex : integer ) return CovMatrix6BaseType ;
impure function GetBin (ID : CoverageIDType; BinIndex : integer ) return CovMatrix7BaseType ;
impure function GetBin (ID : CoverageIDType; BinIndex : integer ) return CovMatrix8BaseType ;
impure function GetBin (ID : CoverageIDType; BinIndex : integer ) return CovMatrix9BaseType ;
-- ------------------------------------------------------------
impure function GetBinName (ID : CoverageIDType; BinIndex : integer; DefaultName : string := "" ) return string ;
------------------------------------------------------------
impure function GetErrorCount (ID : CoverageIDType) return integer ;
------------------------------------------------------------
-- /////////////////////////////////////////
-- Printing Coverage Bin Information
-- /////////////////////////////////////////
------------------------------------------------------------
-- To specify the following, see SetReportOptions
-- WritePassFail, WriteBinInfo, WriteCount, WriteAnyIllegal
-- WritePrefix, PassName, FailName
------------------------------------------------------------
procedure WriteBin (ID : CoverageIDType) ;
procedure WriteBin (ID : CoverageIDType; LogLevel : LogType ) ; -- With LogLevel
procedure WriteBin (ID : CoverageIDType; FileName : string; OpenKind : File_Open_Kind := APPEND_MODE) ;
procedure WriteBin (ID : CoverageIDType; LogLevel : LogType; FileName : string; OpenKind : File_Open_Kind := APPEND_MODE) ;
------------------------------------------------------------
procedure WriteCovHoles (ID : CoverageIDType; LogLevel : LogType := ALWAYS ) ;
procedure WriteCovHoles (ID : CoverageIDType; PercentCov : real ) ;
procedure WriteCovHoles (ID : CoverageIDType; LogLevel : LogType; PercentCov : real ) ;
procedure WriteCovHoles (ID : CoverageIDType; FileName : string; OpenKind : File_Open_Kind := APPEND_MODE ) ;
procedure WriteCovHoles (ID : CoverageIDType; LogLevel : LogType; FileName : string; OpenKind : File_Open_Kind := APPEND_MODE ) ;
procedure WriteCovHoles (ID : CoverageIDType; FileName : string; PercentCov : real ; OpenKind : File_Open_Kind := APPEND_MODE ) ;
procedure WriteCovHoles (ID : CoverageIDType; LogLevel : LogType; FileName : string; PercentCov : real ; OpenKind : File_Open_Kind := APPEND_MODE ) ;
------------------------------------------------------------
-- /////////////////////////////////////////
-- Writing Out RAW Coverage Bin Information
-- Note that read supports merging of coverage models
-- /////////////////////////////////////////
------------------------------------------------------------
procedure ReadCovDb (ID : CoverageIDType; FileName : string; Merge : boolean := FALSE) ;
procedure WriteCovDb (ID : CoverageIDType; FileName : string; OpenKind : File_Open_Kind := WRITE_MODE ) ;
-- procedure WriteCovDb (ID : CoverageIDType) ;
-- procedure WriteCovYaml (ID : CoverageIDType; FileName : string; OpenKind : File_Open_Kind := WRITE_MODE ) ;
------------------------------------------------------------
-- /////////////////////////////////////////
-- Operations across all coverage models
-- /////////////////////////////////////////
------------------------------------------------------------
procedure WriteCovYaml (FileName : string := ""; OpenKind : File_Open_Kind := WRITE_MODE) ;
procedure ReadCovYaml (FileName : string := ""; Merge : boolean := FALSE) ;
impure function GotCoverage return boolean ;
impure function GetCov (PercentCov : real ) return real ;
impure function GetCov return real ;
------------------------------------------------------------
-- Experimental. Intended primarily for development.
procedure CompareBins (
------------------------------------------------------------
constant Bin1 : in CoverageIDType ;
constant Bin2 : in CoverageIDType ;
variable Valid : out Boolean
) ;
------------------------------------------------------------
-- Experimental. Intended primarily for development.
procedure CompareBins (
------------------------------------------------------------
constant Bin1 : in CoverageIDType ;
constant Bin2 : in CoverageIDType
) ;
--
-- Support for AddBins and AddCross
--
------------------------------------------------------------
function GenBin(
------------------------------------------------------------
AtLeast : integer ;
Min, Max : integer ;
NumBin : integer
) return CovBinType ;
-- Each item in range in a separate CovBin
function GenBin(Min, Max, NumBin : integer ) return CovBinType ;
function GenBin(Min, Max : integer) return CovBinType ;
function GenBin(A : integer) return CovBinType ;
------------------------------------------------------------
function GenBin(
------------------------------------------------------------
AtLeast : integer ;
A : integer_vector
) return CovBinType ;
function GenBin ( A : integer_vector ) return CovBinType ;
------------------------------------------------------------
function IllegalBin ( Min, Max, NumBin : integer ) return CovBinType ;
------------------------------------------------------------
-- All items in range in a single CovBin
function IllegalBin ( Min, Max : integer ) return CovBinType ;
function IllegalBin ( A : integer ) return CovBinType ;
-- IgnoreBin should never have an AtLeast parameter
------------------------------------------------------------
function IgnoreBin (Min, Max, NumBin : integer) return CovBinType ;
------------------------------------------------------------
function IgnoreBin (Min, Max : integer) return CovBinType ; -- All items in range in a single CovBin
function IgnoreBin (A : integer) return CovBinType ;
-- With VHDL-2008, there will be one GenCross that returns CovBinType
-- and has inputs initialized to NULL_BIN - see AddCross
------------------------------------------------------------
function GenCross( -- 2
-- Cross existing bins
-- Use AddCross for adding values directly to coverage database
-- Use GenCross for constants
------------------------------------------------------------
AtLeast : integer ;
Bin1, Bin2 : CovBinType
) return CovMatrix2Type ;
function GenCross(Bin1, Bin2 : CovBinType) return CovMatrix2Type ;
------------------------------------------------------------
function GenCross( -- 3
------------------------------------------------------------
AtLeast : integer ;
Bin1, Bin2, Bin3 : CovBinType
) return CovMatrix3Type ;
function GenCross( Bin1, Bin2, Bin3 : CovBinType ) return CovMatrix3Type ;
------------------------------------------------------------
function GenCross( -- 4
------------------------------------------------------------
AtLeast : integer ;
Bin1, Bin2, Bin3, Bin4 : CovBinType
) return CovMatrix4Type ;
function GenCross( Bin1, Bin2, Bin3, Bin4 : CovBinType ) return CovMatrix4Type ;
------------------------------------------------------------
function GenCross( -- 5
------------------------------------------------------------
AtLeast : integer ;
Bin1, Bin2, Bin3, Bin4, Bin5 : CovBinType
) return CovMatrix5Type ;
function GenCross( Bin1, Bin2, Bin3, Bin4, Bin5 : CovBinType ) return CovMatrix5Type ;
------------------------------------------------------------
function GenCross( -- 6
------------------------------------------------------------
AtLeast : integer ;
Bin1, Bin2, Bin3, Bin4, Bin5, Bin6 : CovBinType
) return CovMatrix6Type ;
function GenCross( Bin1, Bin2, Bin3, Bin4, Bin5, Bin6 : CovBinType ) return CovMatrix6Type ;
------------------------------------------------------------
function GenCross( -- 7
------------------------------------------------------------
AtLeast : integer ;
Bin1, Bin2, Bin3, Bin4, Bin5, Bin6, Bin7 : CovBinType
) return CovMatrix7Type ;
function GenCross( Bin1, Bin2, Bin3, Bin4, Bin5, Bin6, Bin7 : CovBinType ) return CovMatrix7Type ;
------------------------------------------------------------
function GenCross( -- 8
------------------------------------------------------------
AtLeast : integer ;
Bin1, Bin2, Bin3, Bin4, Bin5, Bin6, Bin7, Bin8 : CovBinType
) return CovMatrix8Type ;
function GenCross( Bin1, Bin2, Bin3, Bin4, Bin5, Bin6, Bin7, Bin8 : CovBinType ) return CovMatrix8Type ;
------------------------------------------------------------
function GenCross( -- 9
------------------------------------------------------------
AtLeast : integer ;
Bin1, Bin2, Bin3, Bin4, Bin5, Bin6, Bin7, Bin8, Bin9 : CovBinType
) return CovMatrix9Type ;
function GenCross( Bin1, Bin2, Bin3, Bin4, Bin5, Bin6, Bin7, Bin8, Bin9 : CovBinType ) return CovMatrix9Type ;
------------------------------------------------------------
-- Utilities. Remove if added to std.standard
function to_integer ( B : boolean ) return integer ;
function to_boolean ( I : integer ) return boolean ;
function to_integer ( SL : std_logic ) return integer ;
function to_std_logic ( I : integer ) return std_logic ;
function to_integer_vector ( BV : boolean_vector ) return integer_vector ;
function to_boolean_vector ( IV : integer_vector ) return boolean_vector ;
function to_integer_vector ( SLV : std_logic_vector ) return integer_vector ;
function to_std_logic_vector ( IV : integer_vector ) return std_logic_vector ;
alias to_slv is to_std_logic_vector[integer_vector return std_logic_vector] ;
------------------------------------------------------------------------------------------
-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX CovPType XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX CovPType XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX CovPType XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
------------------------------------------------------------------------------------------
type CovPType is protected
------------------------------------------------------------
impure function NewID (
Name : String ;
ParentID : AlertLogIDType := OSVVM_COVERAGE_ALERTLOG_ID ;
ReportMode : AlertLogReportModeType := ENABLED ;
Search : NameSearchType := NAME_AND_PARENT_ELSE_PRIVATE ;
PrintParent : AlertLogPrintParentType := PRINT_NAME_AND_PARENT
) return CoverageIDType ;
impure function GetNumIDs return integer ;
------------------------------------------------------------
-- /////////////////////////////////////////
-- Coverage Global Settings Common to All Coverage Models
-- /////////////////////////////////////////
------------------------------------------------------------
procedure FileOpenWriteBin (FileName : string; OpenKind : File_Open_Kind ) ;
procedure FileCloseWriteBin ;
-- procedure WriteToCovFile (variable buf : inout line) ;
procedure PrintToCovFile(S : string) ;
------------------------------------------------------------
procedure SetReportOptions (
------------------------------------------------------------
WritePassFail : OsvvmOptionsType := COV_OPT_INIT_PARM_DETECT ;
WriteBinInfo : OsvvmOptionsType := COV_OPT_INIT_PARM_DETECT ;
WriteCount : OsvvmOptionsType := COV_OPT_INIT_PARM_DETECT ;
WriteAnyIllegal : OsvvmOptionsType := COV_OPT_INIT_PARM_DETECT ;
WritePrefix : string := OSVVM_STRING_INIT_PARM_DETECT ;
PassName : string := OSVVM_STRING_INIT_PARM_DETECT ;
FailName : string := OSVVM_STRING_INIT_PARM_DETECT
) ;
procedure ResetReportOptions ;
------------------------------------------------------------
-- /////////////////////////////////////////
-- Coverage Model Settings
-- /////////////////////////////////////////
------------------------------------------------------------
procedure SetName (ID : CoverageIDType; Name : String) ;
impure function SetName (ID : CoverageIDType; Name : String) return string ;
procedure DeallocateName (ID : CoverageIDType) ;
impure function GetName (ID : CoverageIDType) return String ;
impure function GetCovModelName (ID : CoverageIDType) return String ;
impure function GetNamePlus (ID : CoverageIDType; prefix, suffix : string) return String ;
procedure SetItemBinNames (
ID : CoverageIDType ;
Name1 : String ;
Name2, Name3, Name4, Name5,
Name6, Name7, Name8, Name9, Name10,
Name11, Name12, Name13, Name14, Name15,
Name16, Name17, Name18, Name19, Name20 : string := ""
) ;
------------------------------------------------------------
procedure SetMessage (ID : CoverageIDType; Message : String) ;
procedure DeallocateMessage (ID : CoverageIDType) ;
procedure SetCovTarget (ID : CoverageIDType; Percent : real) ;
impure function GetCovTarget (ID : CoverageIDType) return real ;
procedure SetThresholding (ID : CoverageIDType; A : boolean := TRUE ) ;
procedure SetCovThreshold (ID : CoverageIDType; Percent : real) ;
procedure SetMerging (ID : CoverageIDType; A : boolean := TRUE ) ;
procedure SetCountMode (ID : CoverageIDType; A : CountModeType) ;
procedure SetIllegalMode (ID : CoverageIDType; A : IllegalModeType) ;
procedure SetWeightMode (ID : CoverageIDType; WeightMode : WeightModeType; WeightScale : real := 1.0) ;
procedure SetNextPointMode (ID : CoverageIDType; A : NextPointModeType) ;
procedure SetCovWeight (ID : CoverageIDType; Weight : integer) ;
impure function GetCovWeight (ID : CoverageIDType) return integer ;
------------------------------------------------------------
procedure SetAlertLogID (ID : CoverageIDType; A : AlertLogIDType) ;
procedure SetAlertLogID (ID : CoverageIDType; Name : string ; ParentID : AlertLogIDType := ALERTLOG_BASE_ID ; CreateHierarchy : Boolean := TRUE) ;
impure function GetAlertLogID (ID : CoverageIDType) return AlertLogIDType ;
------------------------------------------------------------
procedure InitSeed (ID : CoverageIDType; S : string; UseNewSeedMethods : boolean := TRUE) ;
impure function InitSeed (ID : CoverageIDType; S : string; UseNewSeedMethods : boolean := TRUE ) return string ;
procedure InitSeed (ID : CoverageIDType; I : integer; UseNewSeedMethods : boolean := TRUE ) ;
------------------------------------------------------------
procedure SetSeed (ID : CoverageIDType; RandomSeedIn : RandomSeedType ) ;
impure function GetSeed (ID : CoverageIDType) return RandomSeedType ;
------------------------------------------------------------
-- /////////////////////////////////////////
-- Item / Cross Bin Creation and Destruction
-- /////////////////////////////////////////
------------------------------------------------------------
procedure SetBinSize (ID : CoverageIDType; NewNumBins : integer) ;
procedure Deallocate (ID : CoverageIDType) ;
procedure DeallocateBins (CoverID : CoverageIDType) ;
------------------------------------------------------------
-- Weight Deprecated
procedure AddBins (
------------------------------------------------------------
ID : CoverageIDType ;
Name : String ;
AtLeast : integer ;
Weight : integer ;
CovBin : CovBinType
) ;
procedure AddBins (ID : CoverageIDType; Name : String ; AtLeast : integer ; CovBin : CovBinType ) ;
procedure AddBins (ID : CoverageIDType; Name : String ; CovBin : CovBinType) ;
procedure AddBins (ID : CoverageIDType; AtLeast : integer ; Weight : integer ; CovBin : CovBinType ) ; -- Weight Deprecated
procedure AddBins (ID : CoverageIDType; AtLeast : integer ; CovBin : CovBinType ) ;
procedure AddBins (ID : CoverageIDType; CovBin : CovBinType ) ;
------------------------------------------------------------
-- Weight Deprecated
procedure AddCross(
------------------------------------------------------------
ID : CoverageIDType ;
Name : string ;
AtLeast : integer ;
Weight : integer ;
Bin1, Bin2 : CovBinType ;
Bin3, Bin4, Bin5, Bin6, Bin7, Bin8, Bin9, Bin10, Bin11, Bin12, Bin13,
Bin14, Bin15, Bin16, Bin17, Bin18, Bin19, Bin20 : CovBinType := NULL_BIN
) ;
------------------------------------------------------------
procedure AddCross(
------------------------------------------------------------
ID : CoverageIDType ;
Name : string ;
AtLeast : integer ;
Bin1, Bin2 : CovBinType ;
Bin3, Bin4, Bin5, Bin6, Bin7, Bin8, Bin9, Bin10, Bin11, Bin12, Bin13,
Bin14, Bin15, Bin16, Bin17, Bin18, Bin19, Bin20 : CovBinType := NULL_BIN
) ;
------------------------------------------------------------
procedure AddCross(
------------------------------------------------------------
ID : CoverageIDType ;
Name : string ;
Bin1, Bin2 : CovBinType ;
Bin3, Bin4, Bin5, Bin6, Bin7, Bin8, Bin9, Bin10, Bin11, Bin12, Bin13,
Bin14, Bin15, Bin16, Bin17, Bin18, Bin19, Bin20 : CovBinType := NULL_BIN
) ;
------------------------------------------------------------
-- Weight Deprecated
procedure AddCross(
------------------------------------------------------------
ID : CoverageIDType ;
AtLeast : integer ;
Weight : integer ;
Bin1, Bin2 : CovBinType ;
Bin3, Bin4, Bin5, Bin6, Bin7, Bin8, Bin9, Bin10, Bin11, Bin12, Bin13,
Bin14, Bin15, Bin16, Bin17, Bin18, Bin19, Bin20 : CovBinType := NULL_BIN
) ;
------------------------------------------------------------
procedure AddCross(
------------------------------------------------------------
ID : CoverageIDType ;
AtLeast : integer ;
Bin1, Bin2 : CovBinType ;
Bin3, Bin4, Bin5, Bin6, Bin7, Bin8, Bin9, Bin10, Bin11, Bin12, Bin13,
Bin14, Bin15, Bin16, Bin17, Bin18, Bin19, Bin20 : CovBinType := NULL_BIN
) ;
------------------------------------------------------------
procedure AddCross(
------------------------------------------------------------
ID : CoverageIDType ;
Bin1, Bin2 : CovBinType ;
Bin3, Bin4, Bin5, Bin6, Bin7, Bin8, Bin9, Bin10, Bin11, Bin12, Bin13,
Bin14, Bin15, Bin16, Bin17, Bin18, Bin19, Bin20 : CovBinType := NULL_BIN
) ;
------------------------------------------------------------
-- AddCross for usage with constants created by GenCross
------------------------------------------------------------
procedure AddCross (ID : CoverageIDType; CovBin : CovMatrix2Type ; Name : String := "") ;
procedure AddCross (ID : CoverageIDType; CovBin : CovMatrix3Type ; Name : String := "") ;
procedure AddCross (ID : CoverageIDType; CovBin : CovMatrix4Type ; Name : String := "") ;
procedure AddCross (ID : CoverageIDType; CovBin : CovMatrix5Type ; Name : String := "") ;
procedure AddCross (ID : CoverageIDType; CovBin : CovMatrix6Type ; Name : String := "") ;
procedure AddCross (ID : CoverageIDType; CovBin : CovMatrix7Type ; Name : String := "") ;
procedure AddCross (ID : CoverageIDType; CovBin : CovMatrix8Type ; Name : String := "") ;
procedure AddCross (ID : CoverageIDType; CovBin : CovMatrix9Type ; Name : String := "") ;
------------------------------------------------------------
-- /////////////////////////////////////////
-- Recording and Clearing Coverage
-- /////////////////////////////////////////
------------------------------------------------------------
------------------------------------------------------------
procedure ICoverLast (ID : CoverageIDType) ;
procedure ICover (ID : CoverageIDType; CovPoint : integer_vector) ;
procedure ICover (ID : CoverageIDType; CovPoint : integer) ;
procedure TCover (CoverID : CoverageIDType; A : integer) ;
procedure ClearCov (ID : CoverageIDType) ;
------------------------------------------------------------
-- /////////////////////////////////////////
-- Coverage Information and Statistics
-- /////////////////////////////////////////
------------------------------------------------------------
------------------------------------------------------------
impure function IsCovered (ID : CoverageIDType; PercentCov : real ) return boolean ;
impure function IsCovered (ID : CoverageIDType) return boolean ;
impure function IsInitialized (ID : CoverageIDType) return boolean ;
------------------------------------------------------------
impure function GetItemCount (ID : CoverageIDType) return integer ;
procedure GetTotalCovCountAndGoal (ID : CoverageIDType; PercentCov : real; TotalCovCount : out integer; TotalCovGoal : out integer ) ;
procedure GetTotalCovCountAndGoal (ID : CoverageIDType; TotalCovCount : out integer; TotalCovGoal : out integer ) ;
impure function GetCov (ID : CoverageIDType; PercentCov : real ) return real ;
impure function GetCov (ID : CoverageIDType) return real ;
impure function GetTotalCovCount(ID : CoverageIDType; PercentCov : real ) return integer ;
impure function GetTotalCovCount(ID : CoverageIDType) return integer ;
impure function GetTotalCovGoal (ID : CoverageIDType; PercentCov : real ) return integer ;
impure function GetTotalCovGoal (ID : CoverageIDType) return integer ;
------------------------------------------------------------
impure function GetMinCov (ID : CoverageIDType) return real ;
impure function GetMinCount (ID : CoverageIDType) return integer ;
impure function GetMaxCov (ID : CoverageIDType) return real ;
impure function GetMaxCount (ID : CoverageIDType) return integer ;
------------------------------------------------------------
impure function CountCovHoles (ID : CoverageIDType; PercentCov : real ) return integer ;
impure function CountCovHoles (ID : CoverageIDType) return integer ;
------------------------------------------------------------
-- /////////////////////////////////////////
-- Generating Coverage Points, BinValues, and Indices
-- /////////////////////////////////////////
------------------------------------------------------------
-- Return Points
------------------------------------------------------------
-- to be replaced in VHDL-2019 by version that uses RandomSeed as an inout
impure function ToRandPoint (ID : CoverageIDType; BinVal : RangeArrayType ) return integer ;
impure function ToRandPoint (ID : CoverageIDType; BinVal : RangeArrayType ) return integer_vector ;
------------------------------------------------------------
-- Return Points
impure function GetPoint (ID : CoverageIDType; BinIndex : integer ) return integer ;
impure function GetPoint (ID : CoverageIDType; BinIndex : integer ) return integer_vector ;
impure function GetRandPoint (ID : CoverageIDType) return integer ;
impure function GetRandPoint (ID : CoverageIDType; PercentCov : real ) return integer ;
impure function GetRandPoint (ID : CoverageIDType) return integer_vector ;
impure function GetRandPoint (ID : CoverageIDType; PercentCov : real ) return integer_vector ;
impure function GetIncPoint (ID : CoverageIDType) return integer ;
impure function GetIncPoint (ID : CoverageIDType) return integer_vector ;
impure function GetMinPoint (ID : CoverageIDType) return integer ;
impure function GetMinPoint (ID : CoverageIDType) return integer_vector ;
impure function GetMaxPoint (ID : CoverageIDType) return integer ;
impure function GetMaxPoint (ID : CoverageIDType) return integer_vector ;
impure function GetNextPoint (ID : CoverageIDType; Mode : NextPointModeType) return integer ;
impure function GetNextPoint (ID : CoverageIDType; Mode : NextPointModeType) return integer_vector ;
impure function GetNextPoint (ID : CoverageIDType) return integer ;
impure function GetNextPoint (ID : CoverageIDType) return integer_vector ;
------------------------------------------------------------
-- deprecated, see GetRandPoint
impure function RandCovPoint (ID : CoverageIDType) return integer ;
impure function RandCovPoint (ID : CoverageIDType; PercentCov : real ) return integer ;
impure function RandCovPoint (ID : CoverageIDType) return integer_vector ;
impure function RandCovPoint (ID : CoverageIDType; PercentCov : real ) return integer_vector ;
------------------------------------------------------------
-- Return BinVals
impure function GetBinVal (ID : CoverageIDType; BinIndex : integer ) return RangeArrayType ;
impure function GetRandBinVal (ID : CoverageIDType; PercentCov : real ) return RangeArrayType ;
impure function GetRandBinVal (ID : CoverageIDType) return RangeArrayType ;
impure function GetLastBinVal (ID : CoverageIDType) return RangeArrayType ;
impure function GetIncBinVal (ID : CoverageIDType) return RangeArrayType ;
impure function GetMinBinVal (ID : CoverageIDType) return RangeArrayType ;
impure function GetMaxBinVal (ID : CoverageIDType) return RangeArrayType ;
impure function GetNextBinVal (ID : CoverageIDType; Mode : NextPointModeType) return RangeArrayType ;
impure function GetNextBinVal (ID : CoverageIDType) return RangeArrayType ;
impure function GetHoleBinVal (ID : CoverageIDType; ReqHoleNum : integer ; PercentCov : real ) return RangeArrayType ;
impure function GetHoleBinVal (ID : CoverageIDType; PercentCov : real ) return RangeArrayType ;
impure function GetHoleBinVal (ID : CoverageIDType; ReqHoleNum : integer := 1 ) return RangeArrayType ;
-- deprecated RandCovBinVal, see GetRandBinVal
impure function RandCovBinVal (ID : CoverageIDType; PercentCov : real ) return RangeArrayType ;
impure function RandCovBinVal (ID : CoverageIDType) return RangeArrayType ;
-- Return Index Values
------------------------------------------------------------
impure function GetNumBins (ID : CoverageIDType) return integer ;
impure function GetRandIndex (ID : CoverageIDType; CovTargetPercent : real ) return integer ;
impure function GetRandIndex (ID : CoverageIDType) return integer ;
impure function GetLastIndex (ID : CoverageIDType) return integer ;
impure function GetIncIndex (ID : CoverageIDType) return integer ;
impure function GetMinIndex (ID : CoverageIDType) return integer ;
impure function GetMaxIndex (ID : CoverageIDType) return integer ;
impure function GetNextIndex (ID : CoverageIDType; Mode : NextPointModeType) return integer ;
impure function GetNextIndex (ID : CoverageIDType) return integer ;
------------------------------------------------------------
-- /////////////////////////////////////////
-- Accessing Coverage Bin Information
-- /////////////////////////////////////////
------------------------------------------------------------
-- ------------------------------------------------------------
-- Intended as a stand in until we get a more general GetBin
impure function GetBinInfo (ID : CoverageIDType; BinIndex : integer ) return CovBinBaseType ;
-- ------------------------------------------------------------
-- Intended as a stand in until we get a more general GetBin
impure function GetBinValLength (ID : CoverageIDType) return integer ;
-- ------------------------------------------------------------
-- Eventually the multiple GetBin functions will be replaced by a
-- a single GetBin that returns CovBinBaseType with BinVal as an
-- unconstrained element
impure function GetBin (ID : CoverageIDType; BinIndex : integer ) return CovBinBaseType ;
impure function GetBin (ID : CoverageIDType; BinIndex : integer ) return CovMatrix2BaseType ;
impure function GetBin (ID : CoverageIDType; BinIndex : integer ) return CovMatrix3BaseType ;
impure function GetBin (ID : CoverageIDType; BinIndex : integer ) return CovMatrix4BaseType ;
impure function GetBin (ID : CoverageIDType; BinIndex : integer ) return CovMatrix5BaseType ;
impure function GetBin (ID : CoverageIDType; BinIndex : integer ) return CovMatrix6BaseType ;
impure function GetBin (ID : CoverageIDType; BinIndex : integer ) return CovMatrix7BaseType ;
impure function GetBin (ID : CoverageIDType; BinIndex : integer ) return CovMatrix8BaseType ;
impure function GetBin (ID : CoverageIDType; BinIndex : integer ) return CovMatrix9BaseType ;
-- ------------------------------------------------------------
impure function GetBinName (ID : CoverageIDType; BinIndex : integer; DefaultName : string := "" ) return string ;
------------------------------------------------------------
impure function GetErrorCount (ID : CoverageIDType) return integer ;
------------------------------------------------------------
-- /////////////////////////////////////////
-- Printing Coverage Bin Information
-- /////////////////////////////////////////
------------------------------------------------------------
-- To specify the following, see SetReportOptions
-- WritePassFail, WriteBinInfo, WriteCount, WriteAnyIllegal
-- WritePrefix, PassName, FailName
------------------------------------------------------------
procedure WriteBin (ID : CoverageIDType) ;
procedure WriteBin (ID : CoverageIDType; LogLevel : LogType ) ; -- With LogLevel
procedure WriteBin (ID : CoverageIDType; FileName : string; OpenKind : File_Open_Kind := APPEND_MODE) ;
procedure WriteBin (ID : CoverageIDType; LogLevel : LogType; FileName : string; OpenKind : File_Open_Kind := APPEND_MODE) ;
------------------------------------------------------------
procedure DumpBin (ID : CoverageIDType; LogLevel : LogType := DEBUG) ;
------------------------------------------------------------
procedure WriteCovHoles (ID : CoverageIDType; LogLevel : LogType := ALWAYS ) ;
procedure WriteCovHoles (ID : CoverageIDType; PercentCov : real ) ;
procedure WriteCovHoles (ID : CoverageIDType; LogLevel : LogType; PercentCov : real ) ;
procedure WriteCovHoles (ID : CoverageIDType; FileName : string; OpenKind : File_Open_Kind := APPEND_MODE ) ;
procedure WriteCovHoles (ID : CoverageIDType; LogLevel : LogType; FileName : string; OpenKind : File_Open_Kind := APPEND_MODE ) ;
procedure WriteCovHoles (ID : CoverageIDType; FileName : string; PercentCov : real ; OpenKind : File_Open_Kind := APPEND_MODE ) ;
procedure WriteCovHoles (ID : CoverageIDType; LogLevel : LogType; FileName : string; PercentCov : real ; OpenKind : File_Open_Kind := APPEND_MODE ) ;
------------------------------------------------------------
-- /////////////////////////////////////////
-- Writing Out RAW Coverage Bin Information
-- Note that read supports merging of coverage models
-- /////////////////////////////////////////
------------------------------------------------------------
procedure ReadCovDb (ID : CoverageIDType; FileName : string; Merge : boolean := FALSE) ;
procedure WriteCovDb (ID : CoverageIDType; FileName : string; OpenKind : File_Open_Kind := WRITE_MODE ) ;
-- procedure WriteCovDb (ID : CoverageIDType) ;
-- procedure WriteCovYaml (ID : CoverageIDType; FileName : string; OpenKind : File_Open_Kind := WRITE_MODE ) ;
procedure WriteCovYaml (FileName : string := ""; Coverage : real ; OpenKind : File_Open_Kind := WRITE_MODE) ;
procedure ReadCovYaml (FileName : string := ""; Merge : boolean := FALSE) ;
impure function GotCoverage return boolean ;
------------------------------------------------------------
-- /////////////////////////////////////////
-- /////////////////////////////////////////
-- Compatibility Methods - Allows CoveragePkg to Work as a PT still
-- /////////////////////////////////////////
-- /////////////////////////////////////////
------------------------------------------------------------
procedure SetName (Name : String) ;
impure function SetName (Name : String) return string ;
procedure DeallocateName ; -- clear name
impure function GetName return String ;
impure function GetCovModelName return String ;
------------------------------------------------------------
procedure SetMessage (Message : String) ;
procedure DeallocateMessage ; -- clear message
procedure SetCovTarget (Percent : real) ; -- 2.5
impure function GetCovTarget return real ; -- 2.5
procedure SetThresholding (A : boolean := TRUE ) ; -- 2.5
procedure SetCovThreshold (Percent : real) ;
procedure SetMerging (A : boolean := TRUE ) ; -- 2.5
procedure SetCountMode (A : CountModeType) ;
procedure SetIllegalMode (A : IllegalModeType) ;
procedure SetWeightMode (A : WeightModeType; Scale : real := 1.0) ;
procedure SetNextPointMode (A : NextPointModeType) ;
------------------------------------------------------------
procedure SetAlertLogID (A : AlertLogIDType) ;
procedure SetAlertLogID (Name : string ; ParentID : AlertLogIDType := ALERTLOG_BASE_ID ; CreateHierarchy : Boolean := TRUE) ;
impure function GetAlertLogID return AlertLogIDType ;
------------------------------------------------------------
procedure InitSeed (S : string ) ;
impure function InitSeed (S : string ) return string ;
procedure InitSeed (I : integer ) ;
------------------------------------------------------------
procedure SetSeed (RandomSeedIn : RandomSeedType ) ;
impure function GetSeed return RandomSeedType ;
------------------------------------------------------------
procedure SetBinSize (NewNumBins : integer) ;
procedure Deallocate ;
------------------------------------------------------------
-- Weight Deprecated
procedure AddBins (
------------------------------------------------------------
Name : String ;
AtLeast : integer ;
Weight : integer ;
CovBin : CovBinType
) ;
procedure AddBins ( Name : String ; AtLeast : integer ; CovBin : CovBinType ) ;
procedure AddBins ( Name : String ; CovBin : CovBinType) ;
procedure AddBins ( AtLeast : integer ; Weight : integer ; CovBin : CovBinType ) ;
procedure AddBins ( AtLeast : integer ; CovBin : CovBinType ) ;
procedure AddBins ( CovBin : CovBinType ) ;
------------------------------------------------------------
procedure AddCross(
------------------------------------------------------------
Name : string ;
AtLeast : integer ;
Weight : integer ;
Bin1, Bin2 : CovBinType ;
Bin3, Bin4, Bin5, Bin6, Bin7, Bin8, Bin9, Bin10, Bin11, Bin12, Bin13,
Bin14, Bin15, Bin16, Bin17, Bin18, Bin19, Bin20 : CovBinType := NULL_BIN
) ;
------------------------------------------------------------
procedure AddCross(
Name : string ;
AtLeast : integer ;
Bin1, Bin2 : CovBinType ;
Bin3, Bin4, Bin5, Bin6, Bin7, Bin8, Bin9, Bin10, Bin11, Bin12, Bin13,
Bin14, Bin15, Bin16, Bin17, Bin18, Bin19, Bin20 : CovBinType := NULL_BIN
) ;
------------------------------------------------------------
procedure AddCross(
Name : string ;
Bin1, Bin2 : CovBinType ;
Bin3, Bin4, Bin5, Bin6, Bin7, Bin8, Bin9, Bin10, Bin11, Bin12, Bin13,
Bin14, Bin15, Bin16, Bin17, Bin18, Bin19, Bin20 : CovBinType := NULL_BIN
) ;
------------------------------------------------------------
procedure AddCross(
AtLeast : integer ;
Weight : integer ;
Bin1, Bin2 : CovBinType ;
Bin3, Bin4, Bin5, Bin6, Bin7, Bin8, Bin9, Bin10, Bin11, Bin12, Bin13,
Bin14, Bin15, Bin16, Bin17, Bin18, Bin19, Bin20 : CovBinType := NULL_BIN
) ;
------------------------------------------------------------
procedure AddCross(
AtLeast : integer ;
Bin1, Bin2 : CovBinType ;
Bin3, Bin4, Bin5, Bin6, Bin7, Bin8, Bin9, Bin10, Bin11, Bin12, Bin13,
Bin14, Bin15, Bin16, Bin17, Bin18, Bin19, Bin20 : CovBinType := NULL_BIN
) ;
------------------------------------------------------------
procedure AddCross(
Bin1, Bin2 : CovBinType ;
Bin3, Bin4, Bin5, Bin6, Bin7, Bin8, Bin9, Bin10, Bin11, Bin12, Bin13,
Bin14, Bin15, Bin16, Bin17, Bin18, Bin19, Bin20 : CovBinType := NULL_BIN
) ;
------------------------------------------------------------
-- AddCross for usage with constants created by GenCross
procedure AddCross (CovBin : CovMatrix2Type ; Name : String := "") ;
procedure AddCross (CovBin : CovMatrix3Type ; Name : String := "") ;
procedure AddCross (CovBin : CovMatrix4Type ; Name : String := "") ;
procedure AddCross (CovBin : CovMatrix5Type ; Name : String := "") ;
procedure AddCross (CovBin : CovMatrix6Type ; Name : String := "") ;
procedure AddCross (CovBin : CovMatrix7Type ; Name : String := "") ;
procedure AddCross (CovBin : CovMatrix8Type ; Name : String := "") ;
procedure AddCross (CovBin : CovMatrix9Type ; Name : String := "") ;
------------------------------------------------------------
-- Recording and Clearing Coverage
procedure ICoverLast ;
procedure ICover( CovPoint : integer) ;
procedure ICover( CovPoint : integer_vector) ;
procedure TCover( A : integer) ;
procedure ClearCov ;
procedure SetCovZero ; -- Deprecated
------------------------------------------------------------
-- Coverage Information and Statistics
impure function IsCovered return boolean ;
impure function IsCovered ( PercentCov : real ) return boolean ;
impure function IsInitialized return boolean ;
------------------------------------------------------------
impure function GetItemCount return integer ;
impure function GetCov ( PercentCov : real ) return real ;
impure function GetCov return real ; -- PercentCov of entire model/all bins
impure function GetTotalCovCount ( PercentCov : real ) return integer ;
impure function GetTotalCovCount return integer ;
impure function GetTotalCovGoal ( PercentCov : real ) return integer ;
impure function GetTotalCovGoal return integer ;
------------------------------------------------------------
impure function GetMinCov return real ; -- PercentCov
impure function GetMinCount return integer ; -- Count
impure function GetMaxCov return real ; -- PercentCov
impure function GetMaxCount return integer ; -- Count
------------------------------------------------------------
impure function CountCovHoles ( PercentCov : real ) return integer ;
impure function CountCovHoles return integer ;
------------------------------------------------------------
-- Return Points
impure function GetPoint ( BinIndex : integer ) return integer ;
impure function GetPoint ( BinIndex : integer ) return integer_vector ;
impure function GetRandPoint return integer ;
impure function GetRandPoint ( PercentCov : real ) return integer ;
impure function GetRandPoint return integer_vector ;
impure function GetRandPoint ( PercentCov : real ) return integer_vector ;
impure function GetIncPoint return integer ;
impure function GetIncPoint return integer_vector ;
impure function GetMinPoint return integer ;
impure function GetMinPoint return integer_vector ;
impure function GetMaxPoint return integer ;
impure function GetMaxPoint return integer_vector ;
impure function GetNextPoint return integer ;
impure function GetNextPoint return integer_vector ;
impure function GetNextPoint(Mode : NextPointModeType) return integer ;
impure function GetNextPoint(Mode : NextPointModeType) return integer_vector ;
-- RandCovPoint is deprecated, renamed to GetRandPoint
impure function RandCovPoint return integer ;
impure function RandCovPoint ( PercentCov : real ) return integer ;
impure function RandCovPoint return integer_vector ;
impure function RandCovPoint ( PercentCov : real ) return integer_vector ;
------------------------------------------------------------
-- Return BinVals
impure function GetBinVal ( BinIndex : integer ) return RangeArrayType ;
impure function GetRandBinVal return RangeArrayType ;
impure function GetRandBinVal ( PercentCov : real ) return RangeArrayType ;
impure function GetLastBinVal return RangeArrayType ;
impure function GetIncBinVal return RangeArrayType ;
impure function GetMinBinVal return RangeArrayType ;
impure function GetMaxBinVal return RangeArrayType ;
impure function GetNextBinVal return RangeArrayType ;
impure function GetNextBinVal(Mode : NextPointModeType) return RangeArrayType ;
impure function GetHoleBinVal ( ReqHoleNum : integer ; PercentCov : real ) return RangeArrayType ;
impure function GetHoleBinVal ( PercentCov : real ) return RangeArrayType ;
impure function GetHoleBinVal ( ReqHoleNum : integer := 1 ) return RangeArrayType ;
-- RandCovBinVal is deprecated, renamed to GetRandBinVal
impure function RandCovBinVal return RangeArrayType ;
impure function RandCovBinVal ( PercentCov : real ) return RangeArrayType ; -- deprecated, see GetRandBinVal
------------------------------------------------------------
-- Return Index
impure function GetNumBins return integer ;
impure function GetRandIndex return integer ;
impure function GetRandIndex ( CovTargetPercent : real ) return integer ;
impure function GetLastIndex return integer ;
impure function GetIncIndex return integer ;
impure function GetMinIndex return integer ;
impure function GetMaxIndex return integer ;
impure function GetNextIndex return integer ;
impure function GetNextIndex(Mode : NextPointModeType) return integer ;
-- GetBin returns an internal value of the coverage data structure
-- The return value may change as the package evolves
-- Use it only for debugging.
-- GetBinInfo is a for development only.
impure function GetBinInfo ( BinIndex : integer ) return CovBinBaseType ;
impure function GetBinValLength return integer ;
impure function GetBin ( BinIndex : integer ) return CovBinBaseType ;
impure function GetBin ( BinIndex : integer ) return CovMatrix2BaseType ;
impure function GetBin ( BinIndex : integer ) return CovMatrix3BaseType ;
impure function GetBin ( BinIndex : integer ) return CovMatrix4BaseType ;
impure function GetBin ( BinIndex : integer ) return CovMatrix5BaseType ;
impure function GetBin ( BinIndex : integer ) return CovMatrix6BaseType ;
impure function GetBin ( BinIndex : integer ) return CovMatrix7BaseType ;
impure function GetBin ( BinIndex : integer ) return CovMatrix8BaseType ;
impure function GetBin ( BinIndex : integer ) return CovMatrix9BaseType ;
impure function GetBinName ( BinIndex : integer; DefaultName : string := "" ) return string ;
impure function GetErrorCount return integer ;
------------------------------------------------------------
procedure WriteBin (
WritePassFail : OsvvmOptionsType := COV_OPT_INIT_PARM_DETECT ;
WriteBinInfo : OsvvmOptionsType := COV_OPT_INIT_PARM_DETECT ;
WriteCount : OsvvmOptionsType := COV_OPT_INIT_PARM_DETECT ;
WriteAnyIllegal : OsvvmOptionsType := COV_OPT_INIT_PARM_DETECT ;
WritePrefix : string := OSVVM_STRING_INIT_PARM_DETECT ;
PassName : string := OSVVM_STRING_INIT_PARM_DETECT ;
FailName : string := OSVVM_STRING_INIT_PARM_DETECT
) ;
------------------------------------------------------------
procedure WriteBin ( -- With LogLevel
LogLevel : LogType ;
WritePassFail : OsvvmOptionsType := COV_OPT_INIT_PARM_DETECT ;
WriteBinInfo : OsvvmOptionsType := COV_OPT_INIT_PARM_DETECT ;
WriteCount : OsvvmOptionsType := COV_OPT_INIT_PARM_DETECT ;
WriteAnyIllegal : OsvvmOptionsType := COV_OPT_INIT_PARM_DETECT ;
WritePrefix : string := OSVVM_STRING_INIT_PARM_DETECT ;
PassName : string := OSVVM_STRING_INIT_PARM_DETECT ;
FailName : string := OSVVM_STRING_INIT_PARM_DETECT
) ;
------------------------------------------------------------
procedure WriteBin (
FileName : string;
OpenKind : File_Open_Kind := APPEND_MODE ;
WritePassFail : OsvvmOptionsType := COV_OPT_INIT_PARM_DETECT ;
WriteBinInfo : OsvvmOptionsType := COV_OPT_INIT_PARM_DETECT ;
WriteCount : OsvvmOptionsType := COV_OPT_INIT_PARM_DETECT ;
WriteAnyIllegal : OsvvmOptionsType := COV_OPT_INIT_PARM_DETECT ;
WritePrefix : string := OSVVM_STRING_INIT_PARM_DETECT ;
PassName : string := OSVVM_STRING_INIT_PARM_DETECT ;
FailName : string := OSVVM_STRING_INIT_PARM_DETECT
) ;
------------------------------------------------------------
procedure WriteBin ( -- With LogLevel
LogLevel : LogType ;
FileName : string;
OpenKind : File_Open_Kind := APPEND_MODE ;
WritePassFail : OsvvmOptionsType := COV_OPT_INIT_PARM_DETECT ;
WriteBinInfo : OsvvmOptionsType := COV_OPT_INIT_PARM_DETECT ;
WriteCount : OsvvmOptionsType := COV_OPT_INIT_PARM_DETECT ;
WriteAnyIllegal : OsvvmOptionsType := COV_OPT_INIT_PARM_DETECT ;
WritePrefix : string := OSVVM_STRING_INIT_PARM_DETECT ;
PassName : string := OSVVM_STRING_INIT_PARM_DETECT ;
FailName : string := OSVVM_STRING_INIT_PARM_DETECT
) ;
procedure DumpBin (LogLevel : LogType := DEBUG) ; -- Development only
procedure WriteCovHoles ( LogLevel : LogType := ALWAYS ) ;
procedure WriteCovHoles ( PercentCov : real ) ;
procedure WriteCovHoles ( LogLevel : LogType; PercentCov : real ) ;
procedure WriteCovHoles ( FileName : string; OpenKind : File_Open_Kind := APPEND_MODE ) ;
procedure WriteCovHoles ( LogLevel : LogType; FileName : string; OpenKind : File_Open_Kind := APPEND_MODE ) ;
procedure WriteCovHoles ( FileName : string; PercentCov : real ; OpenKind : File_Open_Kind := APPEND_MODE ) ;
procedure WriteCovHoles ( LogLevel : LogType; FileName : string; PercentCov : real ; OpenKind : File_Open_Kind := APPEND_MODE ) ;
procedure ReadCovDb (FileName : string; Merge : boolean := FALSE) ;
procedure WriteCovDb (FileName : string; OpenKind : File_Open_Kind := WRITE_MODE ) ;
------------------------------------------------------------
-- Remaining are Deprecated
--
-- Deprecated/Subsumed by versions with PercentCov Parameter (rather than AtLeast value)
impure function RandCovPoint (AtLeast : integer ) return integer ;
impure function RandCovPoint (AtLeast : integer ) return integer_vector ;
impure function RandCovBinVal (AtLeast : integer ) return RangeArrayType ;
impure function RandCovHole (AtLeast : integer ) return RangeArrayType ;
impure function CountCovHoles (AtLeast : integer ) return integer ;
impure function IsCovered (AtLeast : integer ) return boolean ;
impure function GetHoleBinVal (ReqHoleNum : integer ; AtLeast : integer ) return RangeArrayType ;
impure function GetCovHole (ReqHoleNum : integer ; AtLeast : integer ) return RangeArrayType ;
procedure WriteCovHoles (AtLeast : integer ) ;
procedure WriteCovHoles (LogLevel : LogType; AtLeast : integer ) ;
procedure WriteCovHoles (FileName : string; AtLeast : integer; OpenKind : File_Open_Kind := APPEND_MODE ) ;
procedure WriteCovHoles (LogLevel : LogType; FileName : string; AtLeast : integer ; OpenKind : File_Open_Kind := APPEND_MODE ) ;
-- Deprecated. Replaced by SetMessage
procedure SetItemName (ItemNameIn : String) ; -- Replaced by SetMessage
-- Deprecated. Replaced by GetErrorCount
impure function CovBinErrCnt return integer ; -- Replaced by GetErrorCount
-- Deprecated. Replaced by GetRandBinVal/RandCovBinVal
impure function RandCovHole (PercentCov : real) return RangeArrayType ; -- Deprecated
impure function RandCovHole return RangeArrayType ; -- Deprecated
-- Deprecated. Replaced by GetHoleBinVal
impure function GetCovHole (ReqHoleNum : integer ; PercentCov : real ) return RangeArrayType ;
impure function GetCovHole (PercentCov : real ) return RangeArrayType ;
impure function GetCovHole (ReqHoleNum : integer := 1 ) return RangeArrayType ;
-- Deprecated. Replaced by GetMinCount / GetMaxCount
impure function GetMinCov return integer ; -- Replaced by GetMinCount
impure function GetMaxCov return integer ; -- Replaced by GetMaxCount
-- Deprecated. Replaced by AddCross.
procedure AddBins (CovBin : CovMatrix2Type ; Name : String := "") ;
procedure AddBins (CovBin : CovMatrix3Type ; Name : String := "") ;
procedure AddBins (CovBin : CovMatrix4Type ; Name : String := "") ;
procedure AddBins (CovBin : CovMatrix5Type ; Name : String := "") ;
procedure AddBins (CovBin : CovMatrix6Type ; Name : String := "") ;
procedure AddBins (CovBin : CovMatrix7Type ; Name : String := "") ;
procedure AddBins (CovBin : CovMatrix8Type ; Name : String := "") ;
procedure AddBins (CovBin : CovMatrix9Type ; Name : String := "") ;
end protected CovPType ;
------------------------------------------------------------------------------------------
-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX CovPType XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX CovPType XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
------------------------------------------------------------------------------------------
------------------------------------------------------------
-- Experimental. Intended primarily for development.
procedure CompareBins (
------------------------------------------------------------
variable Bin1 : inout CovPType ;
variable Bin2 : inout CovPType ;
variable ErrorCount : inout integer
) ;
------------------------------------------------------------
-- Experimental. Intended primarily for development.
procedure CompareBins (
------------------------------------------------------------
variable Bin1 : inout CovPType ;
variable Bin2 : inout CovPType
) ;
------------------------------------------------------------
-- Deprecated items
-- The following will be removed from the package in the future.
--
------------------------------------------------------------
-- SetName is deprecated, see NewID
procedure SetName (ID : CoverageIDType; Name : String) ;
impure function SetName (ID : CoverageIDType; Name : String) return string ;
procedure DeallocateName (ID : CoverageIDType) ;
------------------------------------------------------------
-- SetMessage is deprecated, see PrintToCovFile
procedure SetMessage (ID : CoverageIDType; Message : String) ;
procedure DeallocateMessage (ID : CoverageIDType) ;
------------------------------------------------------------
-- DumpBin is deprecated
procedure DumpBin (ID : CoverageIDType; LogLevel : LogType := DEBUG) ;
------------------------------------------------------------
-- Weight Deprecated
procedure AddBins (
------------------------------------------------------------
ID : CoverageIDType ;
Name : String ;
AtLeast : integer ;
Weight : integer ;
CovBin : CovBinType
) ;
procedure AddBins (ID : CoverageIDType; AtLeast : integer ; Weight : integer ; CovBin : CovBinType ) ; -- Weight Deprecated
------------------------------------------------------------
-- Weight Deprecated
procedure AddCross(
------------------------------------------------------------
ID : CoverageIDType ;
Name : string ;
AtLeast : integer ;
Weight : integer ;
Bin1, Bin2 : CovBinType ;
Bin3, Bin4, Bin5, Bin6, Bin7, Bin8, Bin9, Bin10, Bin11, Bin12, Bin13,
Bin14, Bin15, Bin16, Bin17, Bin18, Bin19, Bin20 : CovBinType := NULL_BIN
) ;
------------------------------------------------------------
-- Weight Deprecated
procedure AddCross(
------------------------------------------------------------
ID : CoverageIDType ;
AtLeast : integer ;
Weight : integer ;
Bin1, Bin2 : CovBinType ;
Bin3, Bin4, Bin5, Bin6, Bin7, Bin8, Bin9, Bin10, Bin11, Bin12, Bin13,
Bin14, Bin15, Bin16, Bin17, Bin18, Bin19, Bin20 : CovBinType := NULL_BIN
) ;
------------------------------------------------------------
-- Weight Parameter is deprecated
function GenBin(
------------------------------------------------------------
AtLeast : integer ;
Weight : integer ;
Min, Max : integer ;
NumBin : integer
) return CovBinType ;
------------------------------------------------------------
-- Weight Parameter is deprecated
function GenBin(
------------------------------------------------------------
AtLeast : integer ;
Weight : integer ;
A : integer_vector
) return CovBinType ;
------------------------------------------------------------
function GenCross( -- 2
-- Cross existing bins
-- Use AddCross for adding values directly to coverage database
-- Use GenCross for constants
------------------------------------------------------------
AtLeast : integer ;
Weight : integer ;
Bin1, Bin2 : CovBinType
) return CovMatrix2Type ;
------------------------------------------------------------
function GenCross( -- 3
------------------------------------------------------------
AtLeast : integer ;
Weight : integer ;
Bin1, Bin2, Bin3 : CovBinType
) return CovMatrix3Type ;
------------------------------------------------------------
function GenCross( -- 4
------------------------------------------------------------
AtLeast : integer ;
Weight : integer ;
Bin1, Bin2, Bin3, Bin4 : CovBinType
) return CovMatrix4Type ;
------------------------------------------------------------
function GenCross( -- 5
------------------------------------------------------------
AtLeast : integer ;
Weight : integer ;
Bin1, Bin2, Bin3, Bin4, Bin5 : CovBinType
) return CovMatrix5Type ;
------------------------------------------------------------
function GenCross( -- 6
------------------------------------------------------------
AtLeast : integer ;
Weight : integer ;
Bin1, Bin2, Bin3, Bin4, Bin5, Bin6 : CovBinType
) return CovMatrix6Type ;
------------------------------------------------------------
function GenCross( -- 7
------------------------------------------------------------
AtLeast : integer ;
Weight : integer ;
Bin1, Bin2, Bin3, Bin4, Bin5, Bin6, Bin7 : CovBinType
) return CovMatrix7Type ;
------------------------------------------------------------
function GenCross( -- 8
------------------------------------------------------------
AtLeast : integer ;
Weight : integer ;
Bin1, Bin2, Bin3, Bin4, Bin5, Bin6, Bin7, Bin8 : CovBinType
) return CovMatrix8Type ;
------------------------------------------------------------
function GenCross( -- 9
------------------------------------------------------------
AtLeast : integer ;
Weight : integer ;
Bin1, Bin2, Bin3, Bin4, Bin5, Bin6, Bin7, Bin8, Bin9 : CovBinType
) return CovMatrix9Type ;
end package CoveragePkg ;
--- ///////////////////////////////////////////////////////////////////////////
--- ///////////////////////////////////////////////////////////////////////////
--- ///////////////////////////////////////////////////////////////////////////
package body CoveragePkg is
------------------------------------------------------------
-- package local
function ActionToName(Action : integer) return string is
------------------------------------------------------------
begin
case Action is
when 1 => return "COUNT" ;
when 0 => return "IGNORE" ;
when others => return "ILLEGAL" ;
end case ;
end function ActionToName ;
------------------------------------------------------------
function inside (
-- package local
------------------------------------------------------------
CovPoint : integer_vector ;
BinVal : RangeArrayType
) return boolean is
alias iCovPoint : integer_vector(BinVal'range) is CovPoint ;
begin
for i in BinVal'range loop
if not (iCovPoint(i) >= BinVal(i).min and iCovPoint(i) <= BinVal(i).max) then
return FALSE ;
end if ;
end loop ;
return TRUE ;
end function inside ;
------------------------------------------------------------
function inside (
-- package local, used by InsertBin
-- True when BinVal1 is inside BinVal2
------------------------------------------------------------
BinVal1 : RangeArrayType ;
BinVal2 : RangeArrayType
) return boolean is
alias iBinVal2 : RangeArrayType(BinVal1'range) is BinVal2 ;
begin
for i in BinVal1'range loop
if not (BinVal1(i).min >= iBinVal2(i).min and BinVal1(i).max <= iBinVal2(i).max) then
return FALSE ;
end if ;
end loop ;
return TRUE ;
end function inside ;
------------------------------------------------------------
procedure write (
variable buf : inout line ;
CovPoint : integer_vector
) is
-- package local. called by ICover
------------------------------------------------------------
alias iCovPoint : integer_vector(1 to CovPoint'length) is CovPoint ;
begin
write(buf, "(" & integer'image(iCovPoint(1)) ) ;
for i in 2 to iCovPoint'right loop
write(buf, "," & integer'image(iCovPoint(i)) ) ;
end loop ;
swrite(buf, ")") ;
end procedure write ;
------------------------------------------------------------
procedure write ( file f : text ; BinVal : RangeArrayType ) is
-- called by WriteBin and WriteCovHoles
------------------------------------------------------------
begin
for i in BinVal'range loop
if BinVal(i).min = BinVal(i).max then
write(f, "(" & integer'image(BinVal(i).min) & ") " ) ;
elsif (BinVal(i).min = integer'left) and (BinVal(i).max = integer'right) then
write(f, "(ALL) " ) ;
else
write(f, "(" & integer'image(BinVal(i).min) & " to " &
integer'image(BinVal(i).max) & ") " ) ;
end if ;
end loop ;
end procedure write ;
------------------------------------------------------------
procedure write (
-- called by WriteBin and WriteCovHoles
------------------------------------------------------------
variable buf : inout line ;
constant BinVal : in RangeArrayType
) is
------------------------------------------------------------
begin
for i in BinVal'range loop
if BinVal(i).min = BinVal(i).max then
write(buf, "(" & integer'image(BinVal(i).min) & ") " ) ;
elsif (BinVal(i).min = integer'left) and (BinVal(i).max = integer'right) then
swrite(buf, "(ALL) " ) ;
else
write(buf, "(" & integer'image(BinVal(i).min) & " to " &
integer'image(BinVal(i).max) & ") " ) ;
end if ;
end loop ;
end procedure write ;
------------------------------------------------------------
procedure WriteBinVal (
-- package local for now
------------------------------------------------------------
variable buf : inout line ;
constant BinVal : in RangeArrayType
) is
begin
for i in BinVal'range loop
write(buf, BinVal(i).min) ;
write(buf, ' ') ;
write(buf, BinVal(i).max) ;
write(buf, ' ') ;
end loop ;
end procedure WriteBinVal ;
------------------------------------------------------------
-- package local for now
procedure read (
-- if public, also create one that does not use valid flag
------------------------------------------------------------
variable buf : inout line ;
variable BinVal : out RangeArrayType ;
variable Valid : out boolean
) is
variable ReadValid : boolean ;
begin
for i in BinVal'range loop
read(buf, BinVal(i).min, ReadValid) ;
exit when not ReadValid ;
read(buf, BinVal(i).max, ReadValid) ;
exit when not ReadValid ;
end loop ;
Valid := ReadValid ;
end procedure read ;
------------------------------------------------------------
function CalcPercentCov( Count : integer ; AtLeast : integer ) return real is
-- package local, called by MergeBin, InsertBin, ClearCov, ReadCovDbDatabase
------------------------------------------------------------
variable PercentCov : real ;
begin
if AtLeast > 0 then
return real(Count)*100.0/real(AtLeast) ;
elsif AtLeast = 0 then
return 100.0 ;
else
return real'right ;
end if ;
end function CalcPercentCov ;
-- ------------------------------------------------------------
function BinLengths (
-- package local, used by AddCross, GenCross
-- ------------------------------------------------------------
Bin1, Bin2, Bin3, Bin4, Bin5, Bin6, Bin7, Bin8, Bin9, Bin10, Bin11,
Bin12, Bin13, Bin14, Bin15, Bin16, Bin17, Bin18, Bin19, Bin20 : CovBinType := NULL_BIN
) return integer_vector is
variable result : integer_vector(1 to 20) := (others => 0 ) ;
variable i : integer := result'left ;
variable Len : integer ;
begin
loop
case i is
when 1 => Len := Bin1'length ;
when 2 => Len := Bin2'length ;
when 3 => Len := Bin3'length ;
when 4 => Len := Bin4'length ;
when 5 => Len := Bin5'length ;
when 6 => Len := Bin6'length ;
when 7 => Len := Bin7'length ;
when 8 => Len := Bin8'length ;
when 9 => Len := Bin9'length ;
when 10 => Len := Bin10'length ;
when 11 => Len := Bin11'length ;
when 12 => Len := Bin12'length ;
when 13 => Len := Bin13'length ;
when 14 => Len := Bin14'length ;
when 15 => Len := Bin15'length ;
when 16 => Len := Bin16'length ;
when 17 => Len := Bin17'length ;
when 18 => Len := Bin18'length ;
when 19 => Len := Bin19'length ;
when 20 => Len := Bin20'length ;
when others => Len := 0 ;
end case ;
result(i) := Len ;
exit when Len = 0 ;
i := i + 1 ;
exit when i = 21 ;
end loop ;
return result(1 to (i-1)) ;
end function BinLengths ;
-- ------------------------------------------------------------
function CalcNumCrossBins ( BinLens : integer_vector ) return integer is
-- package local, used by AddCross
-- ------------------------------------------------------------
variable result : integer := 1 ;
begin
for i in BinLens'range loop
result := result * BinLens(i) ;
end loop ;
return result ;
end function CalcNumCrossBins ;
-- ------------------------------------------------------------
procedure IncBinIndex (
-- package local, used by AddCross
-- ------------------------------------------------------------
variable BinIndex : inout integer_vector ;
constant BinLens : in integer_vector
) is
alias aBinIndex : integer_vector(1 to BinIndex'length) is BinIndex ;
alias aBinLens : integer_vector(aBinIndex'range) is BinLens ;
begin
-- increment right most one, then if overflow, increment next
-- assumes bins numbered from 1 to N. - assured by ConcatenateBins
for i in aBinIndex'reverse_range loop
aBinIndex(i) := aBinIndex(i) + 1 ;
exit when aBinIndex(i) <= aBinLens(i) ;
aBinIndex(i) := 1 ;
end loop ;
end procedure IncBinIndex ;
-- ------------------------------------------------------------
function ConcatenateBins (
-- package local, used by AddCross and GenCross
-- ------------------------------------------------------------
BinIndex : integer_vector ;
Bin1, Bin2, Bin3, Bin4, Bin5, Bin6, Bin7, Bin8, Bin9, Bin10, Bin11,
Bin12, Bin13, Bin14, Bin15, Bin16, Bin17, Bin18, Bin19, Bin20 : CovBinType := NULL_BIN
) return CovBinType is
alias aBin1 : CovBinType (1 to Bin1'length) is Bin1 ;
alias aBin2 : CovBinType (1 to Bin2'length) is Bin2 ;
alias aBin3 : CovBinType (1 to Bin3'length) is Bin3 ;
alias aBin4 : CovBinType (1 to Bin4'length) is Bin4 ;
alias aBin5 : CovBinType (1 to Bin5'length) is Bin5 ;
alias aBin6 : CovBinType (1 to Bin6'length) is Bin6 ;
alias aBin7 : CovBinType (1 to Bin7'length) is Bin7 ;
alias aBin8 : CovBinType (1 to Bin8'length) is Bin8 ;
alias aBin9 : CovBinType (1 to Bin9'length) is Bin9 ;
alias aBin10 : CovBinType (1 to Bin10'length) is Bin10 ;
alias aBin11 : CovBinType (1 to Bin11'length) is Bin11 ;
alias aBin12 : CovBinType (1 to Bin12'length) is Bin12 ;
alias aBin13 : CovBinType (1 to Bin13'length) is Bin13 ;
alias aBin14 : CovBinType (1 to Bin14'length) is Bin14 ;
alias aBin15 : CovBinType (1 to Bin15'length) is Bin15 ;
alias aBin16 : CovBinType (1 to Bin16'length) is Bin16 ;
alias aBin17 : CovBinType (1 to Bin17'length) is Bin17 ;
alias aBin18 : CovBinType (1 to Bin18'length) is Bin18 ;
alias aBin19 : CovBinType (1 to Bin19'length) is Bin19 ;
alias aBin20 : CovBinType (1 to Bin20'length) is Bin20 ;
alias aBinIndex : integer_vector(1 to BinIndex'length) is BinIndex ;
variable result : CovBinType(aBinIndex'range) ;
begin
for i in aBinIndex'range loop
case i is
when 1 => result(i) := aBin1(aBinIndex(i)) ;
when 2 => result(i) := aBin2(aBinIndex(i)) ;
when 3 => result(i) := aBin3(aBinIndex(i)) ;
when 4 => result(i) := aBin4(aBinIndex(i)) ;
when 5 => result(i) := aBin5(aBinIndex(i)) ;
when 6 => result(i) := aBin6(aBinIndex(i)) ;
when 7 => result(i) := aBin7(aBinIndex(i)) ;
when 8 => result(i) := aBin8(aBinIndex(i)) ;
when 9 => result(i) := aBin9(aBinIndex(i)) ;
when 10 => result(i) := aBin10(aBinIndex(i)) ;
when 11 => result(i) := aBin11(aBinIndex(i)) ;
when 12 => result(i) := aBin12(aBinIndex(i)) ;
when 13 => result(i) := aBin13(aBinIndex(i)) ;
when 14 => result(i) := aBin14(aBinIndex(i)) ;
when 15 => result(i) := aBin15(aBinIndex(i)) ;
when 16 => result(i) := aBin16(aBinIndex(i)) ;
when 17 => result(i) := aBin17(aBinIndex(i)) ;
when 18 => result(i) := aBin18(aBinIndex(i)) ;
when 19 => result(i) := aBin19(aBinIndex(i)) ;
when 20 => result(i) := aBin20(aBinIndex(i)) ;
when others =>
-- pure functions cannot use alert and/or print
report "CoveragePkg.AddCross: More than 20 bins not supported"
severity FAILURE ;
end case ;
end loop ;
return result ;
end function ConcatenateBins ;
------------------------------------------------------------
function MergeState( CrossBins : CovBinType) return integer is
-- package local, Used by AddCross, GenCross
------------------------------------------------------------
variable resultState : integer ;
begin
resultState := COV_COUNT ;
for i in CrossBins'range loop
if CrossBins(i).action = COV_ILLEGAL then
return COV_ILLEGAL ;
end if ;
if CrossBins(i).action = COV_IGNORE then
resultState := COV_IGNORE ;
end if ;
end loop ;
return resultState ;
end function MergeState ;
------------------------------------------------------------
function MergeBinVal( CrossBins : CovBinType) return RangeArrayType is
-- package local, Used by AddCross, GenCross
------------------------------------------------------------
alias aCrossBins : CovBinType(1 to CrossBins'length) is CrossBins ;
variable BinVal : RangeArrayType(aCrossBins'range) ;
begin
for i in aCrossBins'range loop
BinVal(i to i) := aCrossBins(i).BinVal ;
end loop ;
return BinVal ;
end function MergeBinVal ;
------------------------------------------------------------
function MergeAtLeast(
-- package local, Used by AddCross, GenCross
------------------------------------------------------------
Action : in integer ;
AtLeast : in integer ;
CrossBins : in CovBinType
) return integer is
variable Result : integer := AtLeast ;
begin
if Action /= COV_COUNT then
return 0 ;
end if ;
for i in CrossBins'range loop
if CrossBins(i).Action = Action then
Result := maximum (Result, CrossBins(i).AtLeast) ;
end if ;
end loop ;
return result ;
end function MergeAtLeast ;
------------------------------------------------------------
function MergeWeight(
-- package local, Used by AddCross, GenCross
------------------------------------------------------------
Action : in integer ;
Weight : in integer ;
CrossBins : in CovBinType
) return integer is
variable Result : integer := Weight ;
begin
if Action /= COV_COUNT then
return 0 ;
end if ;
for i in CrossBins'range loop
if CrossBins(i).Action = Action then
Result := maximum (Result, CrossBins(i).Weight) ;
end if ;
end loop ;
return result ;
end function MergeWeight ;
------------------------------------------------------------ VendorCov
-- VendorCov Conversion for Vendor supported functional coverage modeling
function ToVendorCovBinVal (BinVal : RangeArrayType) return VendorCovRangeArrayType is
------------------------------------------------------------
variable VendorCovBinVal : VendorCovRangeArrayType(BinVal'range);
begin -- VendorCov
for ArrIdx in BinVal'LEFT to BinVal'RIGHT loop -- VendorCov
VendorCovBinVal(ArrIdx) := (min => BinVal(ArrIdx).min, -- VendorCov
max => BinVal(ArrIdx).max) ; -- VendorCov
end loop; -- VendorCov
return VendorCovBinVal ;
end function ToVendorCovBinVal ;
------------------------------------------------------------
function ToMinPoint (A : RangeArrayType) return integer is
-- Used in testing
------------------------------------------------------------
begin
return A(A'left).min ;
end function ToMinPoint ;
------------------------------------------------------------
function ToMinPoint (A : RangeArrayType) return integer_vector is
-- Used in testing
------------------------------------------------------------
variable result : integer_vector(A'range) ;
begin
for i in A'range loop
result(i) := A(i).min ;
end loop ;
return result ;
end function ToMinPoint ;
------------------------------------------------------------
procedure ToRandPoint(
------------------------------------------------------------
variable RV : inout RandomPType ;
constant BinVal : in RangeArrayType ;
variable result : out integer
) is
begin
result := RV.RandInt(BinVal(BinVal'left).min, BinVal(BinVal'left).max) ;
end procedure ToRandPoint ;
------------------------------------------------------------
procedure ToRandPoint(
------------------------------------------------------------
variable RV : inout RandomPType ;
constant BinVal : in RangeArrayType ;
variable result : out integer_vector
) is
variable VectorVal : integer_vector(BinVal'range) ;
begin
for i in BinVal'range loop
VectorVal(i) := RV.RandInt(BinVal(i).min, BinVal(i).max) ;
end loop ;
result := VectorVal ;
end procedure ToRandPoint ;
------------------------------------------------------------
-- Local. Get first word from a string
function GetWord (Message : string) return string is
------------------------------------------------------------
alias aMessage : string( 1 to Message'length) is Message ;
begin
for i in aMessage'range loop
if aMessage(i) = ' ' or aMessage(i) = HT then
return aMessage(1 to i-1) ;
end if ;
end loop ;
return aMessage ;
end function GetWord ;
------------------------------------------------------------------------------------------
-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX CovPType XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX CovPType XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX CovPType XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
------------------------------------------------------------------------------------------
type CovPType is protected body
constant COV_READ_YAML_ALERT_LEVEL : AlertType := ERROR ;
------------------------------------------------------------
-- Global Settings for Coverage Modeling
-- Local WriteBin and WriteCovHoles formatting settings, defaults determined by CoverageGlobals
variable WritePassFailVar : OsvvmOptionsType := COV_OPT_INIT_PARM_DETECT ;
variable WriteBinInfoVar : OsvvmOptionsType := COV_OPT_INIT_PARM_DETECT ;
variable WriteCountVar : OsvvmOptionsType := COV_OPT_INIT_PARM_DETECT ;
variable WriteAnyIllegalVar : OsvvmOptionsType := COV_OPT_INIT_PARM_DETECT ;
variable WritePrefixVar : NamePType ;
variable PassNameVar : NamePType ;
variable FailNameVar : NamePType ;
file WriteBinFile : text ;
variable WriteBinFileInit : boolean := FALSE ;
--!! variable UsingLocalFile : boolean := FALSE ;
------------------------------------------------------------
-- /////////////////////////////////////////
-- CoverageBin Data Structures
-- /////////////////////////////////////////
type RangeArrayPtrType is access RangeArrayType ;
type CovBinInternalBaseType is record
BinVal : RangeArrayPtrType ;
Action : integer ;
Count : integer ;
AtLeast : integer ;
Weight : integer ;
PercentCov : real ;
Name : line ;
end record CovBinInternalBaseType ;
type CovBinInternalType is array (natural range <>) of CovBinInternalBaseType ;
type CovBinPtrType is access CovBinInternalType ;
type FieldNameArrayType is array (natural range <>) of Line ;
type FieldNameArrayPtrType is access FieldNameArrayType ;
type IntegerVectorPtrType is access integer_vector ;
------------------------------------------------------------
-- /////////////////////////////////////////
-- Coverage Information and Settings Structure
-- /////////////////////////////////////////
type CovStructType is record
-- Coverage Bin Structure
CovBinPtr : CovBinPtrType ;
CovName : line ;
NumBins : integer ;
BinValLength : integer ;
FieldName : FieldNameArrayPtrType ;
CovWeight : integer ; -- Set GetCov for entire model
TCoverCount : integer ;
TCoverValuePtr : IntegerVectorPtrType ;
CovMessage : MessageStructPtrType ;
VendorCovHandle : VendorCovHandleType ;
-- Statistics and History
ItemCount : integer ; -- Count of randomizations
LastIndex : integer ; -- Index of last Stimulus Gen or Coverage Collection
LastStimGenIndex : integer ; -- Index of last stimulus gen
-- Internal Modes and Settings
NextPointMode : NextPointModeType ;
IllegalMode : IllegalModeType ;
IllegalModeLevel : AlertType ;
WeightMode : WeightModeType ;
WeightScale : real ;
ThresholdingEnable : boolean ; -- thresholding disabled by default
CovThreshold : real ;
CovTarget : real ;
MergingEnable : boolean ; -- merging disabled by default
CountMode : CountModeType ;
-- Randomization Variable
RV : RandomSeedType ;
RvSeedInit : boolean ;
AlertLogID : AlertLogIDType ;
end record CovStructType ;
variable COV_STRUCT_INIT : CovStructType :=
(
-- Coverage Bin Structure
CovBinPtr => NULL,
CovName => NULL,
NumBins => 0,
BinValLength => 1,
FieldName => NULL,
CovWeight => 1,
TCoverCount => 0,
TCoverValuePtr => NULL,
CovMessage => NULL,
VendorCovHandle => 0,
-- Statistics and History
ItemCount => 0, -- Count of randomizations
LastIndex => 1, -- Index of last Stimulus Gen or Coverage Collection
LastStimGenIndex => 1, -- Index of last stimulus gen
-- Internal Modes and Settings
NextPointMode => RANDOM,
IllegalMode => ILLEGAL_ON,
IllegalModeLevel => ERROR,
WeightMode => AT_LEAST,
WeightScale => 1.0,
ThresholdingEnable => FALSE, -- thresholding disabled by default
CovThreshold => 45.0,
CovTarget => 100.0,
MergingEnable => FALSE, -- merging disabled by default
CountMode => COUNT_FIRST,
-- Randomization Variable
RV => (1, 7),
RvSeedInit => FALSE,
AlertLogID => OSVVM_COVERAGE_ALERTLOG_ID
) ;
------------------------------------------------------------
-- /////////////////////////////////////////
-- Adjustable Array Data Structure and Creation
-- /////////////////////////////////////////
type ItemArrayType is array (integer range <>) of CovStructType ;
type ItemArrayPtrType is access ItemArrayType ;
variable Template : ItemArrayType(1 to 1) := (1 => COV_STRUCT_INIT) ;
constant COV_STRUCT_ID_DEFAULT : CoverageIDType := (ID => Template'left) ;
variable CovStructPtr : ItemArrayPtrType := new ItemArrayType'(Template) ;
variable NumItems : integer := 0 ;
-- constant MIN_NUM_ITEMS : integer := 4 ; -- Temporarily small for testing
constant MIN_NUM_ITEMS : integer := 32 ; -- Min amount to resize array
variable LocalNameStore : NameStorePType ;
------------------------------------------------------------
-- Package Local
function NormalizeArraySize( NewNumItems, MinNumItems : integer ) return integer is
------------------------------------------------------------
variable NormNumItems : integer := NewNumItems ;
variable ModNumItems : integer := 0;
begin
ModNumItems := NewNumItems mod MinNumItems ;
if ModNumItems > 0 then
NormNumItems := NormNumItems + (MinNumItems - ModNumItems) ;
end if ;
return NormNumItems ;
end function NormalizeArraySize ;
------------------------------------------------------------
-- Package Local
procedure GrowNumberItems (
------------------------------------------------------------
variable ItemArrayPtr : InOut ItemArrayPtrType ;
variable NumItems : InOut integer ;
constant GrowAmount : in integer ;
-- constant NewNumItems : in integer ;
-- constant CurNumItems : in integer ;
constant MinNumItems : in integer
) is
variable oldItemArrayPtr : ItemArrayPtrType ;
variable NewNumItems : integer ;
begin
NewNumItems := NumItems + GrowAmount ;
if ItemArrayPtr = NULL then
ItemArrayPtr := new ItemArrayType(1 to NormalizeArraySize(NewNumItems, MinNumItems)) ;
elsif NewNumItems > ItemArrayPtr'length then
oldItemArrayPtr := ItemArrayPtr ;
ItemArrayPtr := new ItemArrayType(1 to NormalizeArraySize(NewNumItems, MinNumItems)) ;
ItemArrayPtr(1 to NumItems) := oldItemArrayPtr(1 to NumItems) ;
deallocate(oldItemArrayPtr) ;
end if ;
NumItems := NewNumItems ;
end procedure GrowNumberItems ;
------------------------------------------------------------
impure function NewID (
------------------------------------------------------------
Name : String ;
ParentID : AlertLogIDType := OSVVM_COVERAGE_ALERTLOG_ID ;
ReportMode : AlertLogReportModeType := ENABLED ;
Search : NameSearchType := NAME_AND_PARENT_ELSE_PRIVATE ;
PrintParent : AlertLogPrintParentType := PRINT_NAME_AND_PARENT
) return CoverageIDType is
variable NewCoverageID : CoverageIDType ;
variable NameID : integer ;
variable ResolvedSearch : NameSearchType ;
variable ResolvedPrintParent : AlertLogPrintParentType ;
begin
ResolvedSearch := ResolveSearch (ParentID /= OSVVM_COVERAGE_ALERTLOG_ID, Search) ;
ResolvedPrintParent := ResolvePrintParent(ParentID /= OSVVM_COVERAGE_ALERTLOG_ID, PrintParent) ;
NameID := LocalNameStore.find(Name, ParentID, ResolvedSearch) ;
if NameID /= ID_NOT_FOUND.ID then
NewCoverageID := (ID => NameID) ;
SetName(NewCoverageID, Name) ; -- redundant - refactor after diverge. Needed if deallocate
return NewCoverageID ;
else
-- Add New Coverage Model to Structure
GrowNumberItems(CovStructPtr, NumItems, 1, MIN_NUM_ITEMS) ;
CovStructPtr(NumItems) := COV_STRUCT_INIT ;
NewCoverageID := (ID => NumItems) ;
-- Create AlertLogID
CovStructPtr(NumItems).AlertLogID := NewID(Name, ParentID, ReportMode, ResolvedPrintParent, CreateHierarchy => FALSE) ;
-- Add item to NameStore
NameID := LocalNameStore.NewID(Name, ParentID, ResolvedSearch) ;
AlertIfNotEqual(CovStructPtr(NumItems).AlertLogID, NameID, NumItems, "CoveragePkg: Index of LocalNameStore /= CoverageID") ;
InitSeed( NewCoverageID, Name) ;
SetName( NewCoverageID, Name) ; -- redundant - refactor after diverge
return NewCoverageID ;
end if ;
end function NewID ;
------------------------------------------------------------
impure function GetNumIDs return integer is
------------------------------------------------------------
begin
return NumItems ;
end function GetNumIDs ;
------------------------------------------------------------
-- /////////////////////////////////////////
-- Coverage Global Settings Common to All Coverage Models
-- /////////////////////////////////////////
------------------------------------------------------------
procedure FileOpenWriteBin (FileName : string; OpenKind : File_Open_Kind ) is
------------------------------------------------------------
begin
WriteBinFileInit := TRUE ;
file_open( WriteBinFile , FileName , OpenKind );
end procedure FileOpenWriteBin ;
------------------------------------------------------------
procedure FileCloseWriteBin is
------------------------------------------------------------
begin
WriteBinFileInit := FALSE ;
file_close( WriteBinFile) ;
end procedure FileCloseWriteBin ;
------------------------------------------------------------
-- PT Local for now as it uses an access type
procedure WriteToCovFile (variable buf : inout line) is
------------------------------------------------------------
begin
if buf /= NULL then
if WriteBinFileInit then
-- Write to Local WriteBinFile - Deprecated, recommend use TranscriptFile instead
writeline(WriteBinFile, buf) ;
elsif IsTranscriptEnabled then
if IsTranscriptMirrored then
-- Write to TranscriptFile and OUTPUT
tee(TranscriptFile, buf) ;
else
-- Write to TranscriptFile
writeline(TranscriptFile, buf) ;
end if ;
else
-- Default Write to OUTPUT
writeline(OUTPUT, buf) ;
end if ;
end if ;
end procedure WriteToCovFile ;
------------------------------------------------------------
procedure PrintToCovFile(S : string) is
------------------------------------------------------------
variable buf : line ;
begin
write(buf, S) ;
WriteToCovFile(buf) ;
end procedure PrintToCovFile ;
-- ------------------------------------------------------------
-- procedure FileOpen (FileName : string; OpenKind : File_Open_Kind ) is
-- ------------------------------------------------------------
-- begin
-- WriteCovDbFileInit := TRUE ;
-- file_open( WriteCovDbFile , FileName , OpenKind );
-- end procedure FileOpenWriteCovDb ;
--
-- ------------------------------------------------------------
-- procedure FileCloseWriteCovDb is
-- ------------------------------------------------------------
-- begin
-- WriteCovDbFileInit := FALSE ;
-- file_close( WriteCovDbFile );
-- end procedure FileCloseWriteCovDb ;
------------------------------------------------------------
procedure SetReportOptions (
------------------------------------------------------------
WritePassFail : OsvvmOptionsType := COV_OPT_INIT_PARM_DETECT ;
WriteBinInfo : OsvvmOptionsType := COV_OPT_INIT_PARM_DETECT ;
WriteCount : OsvvmOptionsType := COV_OPT_INIT_PARM_DETECT ;
WriteAnyIllegal : OsvvmOptionsType := COV_OPT_INIT_PARM_DETECT ;
WritePrefix : string := OSVVM_STRING_INIT_PARM_DETECT ;
PassName : string := OSVVM_STRING_INIT_PARM_DETECT ;
FailName : string := OSVVM_STRING_INIT_PARM_DETECT
) is
begin
if WritePassFail /= COV_OPT_INIT_PARM_DETECT then
WritePassFailVar := WritePassFail ;
end if ;
if WriteBinInfo /= COV_OPT_INIT_PARM_DETECT then
WriteBinInfoVar := WriteBinInfo ;
end if ;
if WriteCount /= COV_OPT_INIT_PARM_DETECT then
WriteCountVar := WriteCount ;
end if ;
if WriteAnyIllegal /= COV_OPT_INIT_PARM_DETECT then
WriteAnyIllegalVar := WriteAnyIllegal ;
end if ;
if WritePrefix /= OSVVM_STRING_INIT_PARM_DETECT then
WritePrefixVar.Set(WritePrefix) ;
end if ;
if PassName /= OSVVM_STRING_INIT_PARM_DETECT then
PassNameVar.Set(PassName) ;
end if ;
if FailName /= OSVVM_STRING_INIT_PARM_DETECT then
FailNameVar.Set(FailName) ;
end if ;
end procedure SetReportOptions ;
------------------------------------------------------------
procedure ResetReportOptions is
------------------------------------------------------------
begin
-- Globals - for all coverage models
WritePassFailVar := COV_OPT_INIT_PARM_DETECT ;
WriteBinInfoVar := COV_OPT_INIT_PARM_DETECT ;
WriteCountVar := COV_OPT_INIT_PARM_DETECT ;
WriteAnyIllegalVar := COV_OPT_INIT_PARM_DETECT ;
WritePrefixVar.deallocate ;
PassNameVar.deallocate ;
FailNameVar.deallocate ;
end procedure ResetReportOptions ;
------------------------------------------------------------
-- /////////////////////////////////////////
-- Coverage Model Settings
-- /////////////////////////////////////////
------------------------------------------------------------
impure function IsInitialized (ID : CoverageIDType) return boolean is
------------------------------------------------------------
begin
return CovStructPtr(ID.ID).NumBins > 0 ;
end function IsInitialized ;
------------------------------------------------------------
procedure InitSeed (ID : CoverageIDType; S : string; UseNewSeedMethods : boolean := TRUE) is
------------------------------------------------------------
variable ChurnSeed : integer ;
begin
if UseNewSeedMethods then
CovStructPtr(ID.ID).RV := GenRandSeed(S) ;
Uniform(CovStructPtr(ID.ID).RV, ChurnSeed, 0, 1) ;
else
CovStructPtr(ID.ID).RV := OldGenRandSeed(S) ;
end if ;
CovStructPtr(ID.ID).RvSeedInit := TRUE ;
end procedure InitSeed ;
------------------------------------------------------------
impure function InitSeed (ID : CoverageIDType; S : string; UseNewSeedMethods : boolean := TRUE ) return string is
------------------------------------------------------------
begin
InitSeed(ID, S, UseNewSeedMethods) ;
CovStructPtr(ID.ID).RvSeedInit := TRUE ;
return S ;
end function InitSeed ;
------------------------------------------------------------
procedure InitSeed (ID : CoverageIDType; I : integer; UseNewSeedMethods : boolean := TRUE ) is
------------------------------------------------------------
variable ChurnSeed : integer ;
begin
if UseNewSeedMethods then
CovStructPtr(ID.ID).RV := GenRandSeed(I) ;
Uniform(CovStructPtr(ID.ID).RV, ChurnSeed, 0, 1) ;
else
CovStructPtr(ID.ID).RV := OldGenRandSeed(I) ;
end if ;
CovStructPtr(ID.ID).RvSeedInit := TRUE ;
end procedure InitSeed ;
------------------------------------------------------------
procedure SetSeed (ID : CoverageIDType; RandomSeedIn : RandomSeedType ) is
------------------------------------------------------------
begin
CovStructPtr(ID.ID).RV := RandomSeedIn ;
CovStructPtr(ID.ID).RvSeedInit := TRUE ;
end procedure SetSeed ;
------------------------------------------------------------
impure function GetSeed (ID : CoverageIDType) return RandomSeedType is
------------------------------------------------------------
begin
return CovStructPtr(ID.ID).RV ;
end function GetSeed ;
------------------------------------------------------------
procedure SetName (ID : CoverageIDType; Name : String) is
------------------------------------------------------------
begin
if CovStructPtr(ID.ID).CovName /= NULL then
deallocate (CovStructPtr(ID.ID).CovName) ;
end if;
CovStructPtr(ID.ID).CovName := new string'(Name) ;
-- Update if name updated after model created -- VendorCov
if IsInitialized(ID) then -- VendorCov
VendorCovSetName(CovStructPtr(ID.ID).VendorCovHandle, Name) ; -- VendorCov
end if ; -- VendorCov
-- Init seed if not already initialized
if not CovStructPtr(ID.ID).RvSeedInit then
InitSeed(ID, Name) ;
CovStructPtr(ID.ID).RvSeedInit := TRUE ;
end if ;
end procedure SetName ;
------------------------------------------------------------
impure function SetName (ID : CoverageIDType; Name : String) return string is
------------------------------------------------------------
begin
SetName(ID, Name) ; -- call procedure above
return Name ;
end function SetName ;
------------------------------------------------------------
procedure DeallocateName (ID : CoverageIDType) is
------------------------------------------------------------
begin
Deallocate (CovStructPtr(ID.ID).CovName) ;
end procedure DeallocateName ;
------------------------------------------------------------
impure function GetName (ID : CoverageIDType) return String is
------------------------------------------------------------
begin
if CovStructPtr(ID.ID).CovName /= NULL then
return CovStructPtr(ID.ID).CovName.all ;
else
return "!!! CovName is NULL !!!" ;
end if ;
end function GetName ;
------------------------------------------------------------
impure function GetCovModelName (ID : CoverageIDType) return String is
------------------------------------------------------------
begin
if CovStructPtr(ID.ID).CovName /= NULL then
-- return Name if set
return CovStructPtr(ID.ID).CovName.all ;
elsif CovStructPtr(ID.ID).AlertLogID /= OSVVM_COVERAGE_ALERTLOG_ID then
-- otherwise return AlertLogName if it is set
return GetAlertLogName(CovStructPtr(ID.ID).AlertLogID) ;
elsif CovStructPtr(ID.ID).CovMessage /= NULL then
-- otherwise Get the first word of the Message if it is set
return GetWord(CovStructPtr(ID.ID).CovMessage.Name.all) ;
else
return "" ;
end if ;
end function GetCovModelName ;
------------------------------------------------------------
-- Called in calls to AlertLogID to add Name to if set different from AlertLogID name
impure function GetNamePlus(ID : CoverageIDType; prefix, suffix : string) return String is
------------------------------------------------------------
begin
if CovStructPtr(ID.ID).CovName /= NULL and (CovStructPtr(ID.ID).CovName.all /= GetAlertLogName(CovStructPtr(ID.ID).AlertLogID)) then
-- return Name if set
return prefix & CovStructPtr(ID.ID).CovName.all & suffix ;
elsif CovStructPtr(ID.ID).AlertLogID = OSVVM_COVERAGE_ALERTLOG_ID and CovStructPtr(ID.ID).CovMessage /= NULL then
-- If AlertLogID not set, then use Message
return prefix & GetWord(CovStructPtr(ID.ID).CovMessage.Name.all) & suffix ;
else
return "" ;
end if ;
end function GetNamePlus ;
------------------------------------------------------------
-- PT Local
impure function NewNamePtr(Name : string) return Line is
------------------------------------------------------------
begin
if Name /= "" then
return new string'(Name) ;
else
return NULL ;
end if;
end function NewNamePtr ;
-- ------------------------------------------------------------
-- -- pt local
-- procedure CheckBinValLength(ID : CoverageIDType; CurBinValLength : integer ; Caller : string ) is
-- ------------------------------------------------------------
-- begin
-- if CovStructPtr(ID.ID).NumBins = 0 then
-- CovStructPtr(ID.ID).BinValLength := CurBinValLength ; -- number of points in cross
-- else
-- AlertIfNotEqual(CovStructPtr(ID.ID).AlertLogID, CovStructPtr(ID.ID).BinValLength, CurBinValLength, GetNamePlus(ID, prefix => "in ", suffix => ", ") & "CoveragePkg." & Caller & ":" &
-- " Cross coverage bins of different dimensions prohibited", FAILURE) ;
-- end if;
-- end procedure CheckBinValLength ;
------------------------------------------------------------
-- pt local
impure function BinValLengthNotEqual(CoverID : CoverageIDType; CurBinValLength : integer) return boolean is
------------------------------------------------------------
constant ID : integer := CoverID.ID ;
begin
if CovStructPtr(ID).NumBins = 0 then
CovStructPtr(ID).BinValLength := CurBinValLength ;
CovStructPtr(ID).TCoverValuePtr := new integer_vector(1 to CurBinValLength) ;
return FALSE ;
else
return CurBinValLength /= CovStructPtr(ID).BinValLength ;
end if;
end function BinValLengthNotEqual ;
------------------------------------------------------------
procedure SetItemBinNames (
------------------------------------------------------------
ID : CoverageIDType ;
Name1 : String ;
Name2, Name3, Name4, Name5,
Name6, Name7, Name8, Name9, Name10,
Name11, Name12, Name13, Name14, Name15,
Name16, Name17, Name18, Name19, Name20 : string := ""
) is
variable NamePtr : Line ;
variable FieldNameArray : FieldNameArrayType(1 to 20) ;
variable Dimensions : integer := 0 ;
begin
-- Support names for up to a cross of 20
for i in 1 to 20 loop
if CovStructPtr(ID.ID).FieldName /= NULL then
for i in 1 to CovStructPtr(ID.ID).FieldName'length loop
deallocate (CovStructPtr(ID.ID).FieldName(i)) ;
end loop ;
deallocate (CovStructPtr(ID.ID).FieldName) ;
end if;
case i is
when 1 => NamePtr := NewNamePtr(Name1) ;
when 2 => NamePtr := NewNamePtr(Name2) ;
when 3 => NamePtr := NewNamePtr(Name3) ;
when 4 => NamePtr := NewNamePtr(Name4) ;
when 5 => NamePtr := NewNamePtr(Name5) ;
when 6 => NamePtr := NewNamePtr(Name6) ;
when 7 => NamePtr := NewNamePtr(Name7) ;
when 8 => NamePtr := NewNamePtr(Name8) ;
when 9 => NamePtr := NewNamePtr(Name9) ;
when 10 => NamePtr := NewNamePtr(Name10) ;
when 11 => NamePtr := NewNamePtr(Name11) ;
when 12 => NamePtr := NewNamePtr(Name12) ;
when 13 => NamePtr := NewNamePtr(Name13) ;
when 14 => NamePtr := NewNamePtr(Name14) ;
when 15 => NamePtr := NewNamePtr(Name15) ;
when 16 => NamePtr := NewNamePtr(Name16) ;
when 17 => NamePtr := NewNamePtr(Name17) ;
when 18 => NamePtr := NewNamePtr(Name18) ;
when 19 => NamePtr := NewNamePtr(Name19) ;
when 20 => NamePtr := NewNamePtr(Name20) ;
end case ;
exit when NamePtr = NULL ;
FieldNameArray(i) := NamePtr ;
Dimensions := i ;
end loop ;
CovStructPtr(ID.ID).FieldName := new FieldNameArrayType'(FieldNameArray(1 to Dimensions)) ;
-- Check that Dimensions match bin dimensions
if BinValLengthNotEqual(ID, Dimensions) then
Alert(CovStructPtr(ID.ID).AlertLogID, "CoveragePkg.SetItemBinNames: Coverage bins of different dimensions prohibited", FAILURE) ;
end if ;
end procedure SetItemBinNames ;
------------------------------------------------------------
procedure SetMessage (ID : CoverageIDType; Message : String) is
------------------------------------------------------------
begin
SetMessage(CovStructPtr(ID.ID).CovMessage, Message) ;
-- VendorCov update if name updated after model created
if IsInitialized(ID) then -- VendorCov
-- Refine this? If CovName or AlertLogID is set, -- VendorCov
-- it may be set to the same name again. -- VendorCov
VendorCovSetName(CovStructPtr(ID.ID).VendorCovHandle, GetCovModelName(ID)) ; -- VendorCov
end if ; -- VendorCov
if not CovStructPtr(ID.ID).RvSeedInit then -- Init seed if not initialized
InitSeed(ID, Message) ;
CovStructPtr(ID.ID).RvSeedInit := TRUE ;
end if ;
end procedure SetMessage ;
------------------------------------------------------------
procedure DeallocateMessage (ID : CoverageIDType) is
------------------------------------------------------------
begin
DeallocateMessage(CovStructPtr(ID.ID).CovMessage) ;
end procedure DeallocateMessage ;
------------------------------------------------------------
procedure SetThresholding (ID : CoverageIDType; A : boolean := TRUE ) is
------------------------------------------------------------
begin
CovStructPtr(ID.ID).ThresholdingEnable := A ;
end procedure SetThresholding ;
------------------------------------------------------------
procedure SetCovThreshold (ID : CoverageIDType; Percent : real) is
------------------------------------------------------------
begin
CovStructPtr(ID.ID).ThresholdingEnable := TRUE ;
if Percent >= 0.0 then
CovStructPtr(ID.ID).CovThreshold := Percent + 0.0001 ; -- used in less than
else
CovStructPtr(ID.ID).CovThreshold := 0.0001 ; -- used in less than
Alert(CovStructPtr(ID.ID).AlertLogID, GetNamePlus(ID, prefix => "in ", suffix => ", ") & "CoveragePkg.SetCovThreshold:" &
" Invalid Threshold Value " & real'image(Percent), FAILURE) ;
end if ;
end procedure SetCovThreshold ;
------------------------------------------------------------
procedure SetCovTarget (ID : CoverageIDType; Percent : real) is
------------------------------------------------------------
begin
CovStructPtr(ID.ID).CovTarget := Percent ;
end procedure SetCovTarget ;
------------------------------------------------------------
impure function GetCovTarget (ID : CoverageIDType) return real is
------------------------------------------------------------
begin
return CovStructPtr(ID.ID).CovTarget ;
end function GetCovTarget ;
------------------------------------------------------------
procedure SetMerging (ID : CoverageIDType; A : boolean := TRUE ) is
------------------------------------------------------------
begin
CovStructPtr(ID.ID).MergingEnable := A ;
end procedure SetMerging ;
------------------------------------------------------------
procedure SetCountMode (ID : CoverageIDType; A : CountModeType) is
------------------------------------------------------------
begin
CovStructPtr(ID.ID).CountMode := A ;
end procedure SetCountMode ;
------------------------------------------------------------
procedure SetAlertLogID (ID : CoverageIDType; A : AlertLogIDType) is
------------------------------------------------------------
begin
CovStructPtr(ID.ID).AlertLogID := A ;
end procedure SetAlertLogID ;
------------------------------------------------------------
procedure SetAlertLogID(ID : CoverageIDType; Name : string ; ParentID : AlertLogIDType := ALERTLOG_BASE_ID ; CreateHierarchy : Boolean := TRUE) is
------------------------------------------------------------
begin
CovStructPtr(ID.ID).AlertLogID := GetAlertLogID(Name, ParentID, CreateHierarchy) ;
if not CovStructPtr(ID.ID).RvSeedInit then -- Init seed if not initialized
InitSeed(ID, Name) ;
CovStructPtr(ID.ID).RvSeedInit := TRUE ;
end if ;
end procedure SetAlertLogID ;
------------------------------------------------------------
impure function GetAlertLogID(ID : CoverageIDType) return AlertLogIDType is
------------------------------------------------------------
begin
return CovStructPtr(ID.ID).AlertLogID ;
end function GetAlertLogID ;
------------------------------------------------------------
procedure SetNextPointMode (ID : CoverageIDType; A : NextPointModeType) is
------------------------------------------------------------
begin
CovStructPtr(ID.ID).NextPointMode := A ;
end procedure SetNextPointMode ;
------------------------------------------------------------
procedure SetIllegalMode (ID : CoverageIDType; A : IllegalModeType) is
------------------------------------------------------------
begin
CovStructPtr(ID.ID).IllegalMode := A ;
if A = ILLEGAL_FAILURE then
CovStructPtr(ID.ID).IllegalModeLevel := FAILURE ;
else
CovStructPtr(ID.ID).IllegalModeLevel := ERROR ;
end if ;
end procedure SetIllegalMode ;
------------------------------------------------------------
procedure SetWeightMode (ID : CoverageIDType; WeightMode : WeightModeType; WeightScale : real := 1.0) is
------------------------------------------------------------
variable buf : line ;
begin
CovStructPtr(ID.ID).WeightMode := WeightMode ;
CovStructPtr(ID.ID).WeightScale := WeightScale ;
if (WeightMode = REMAIN_EXP) and (WeightScale > 2.0) then
Alert(CovStructPtr(ID.ID).AlertLogID, GetNamePlus(ID, prefix => "in ", suffix => ", ") & "CoveragePkg.SetWeightMode:" &
" WeightScale > 2.0 and large Counts can cause RandCovPoint to fail due to integer values out of range", WARNING) ;
end if ;
if (WeightScale < 1.0) and (WeightMode = REMAIN_WEIGHT or WeightMode = REMAIN_SCALED) then
Alert(CovStructPtr(ID.ID).AlertLogID, GetNamePlus(ID, prefix => "in ", suffix => ", ") & "CoveragePkg.SetWeightMode:" &
" WeightScale must be > 1.0 when WeightMode = REMAIN_WEIGHT or WeightMode = REMAIN_SCALED", FAILURE) ;
CovStructPtr(ID.ID).WeightScale := 1.0 ;
end if;
if WeightScale <= 0.0 then
Alert(CovStructPtr(ID.ID).AlertLogID, GetNamePlus(ID, prefix => "in ", suffix => ", ") & "CoveragePkg.SetWeightMode:" &
" WeightScale must be > 0.0", FAILURE) ;
CovStructPtr(ID.ID).WeightScale := 1.0 ;
end if;
end procedure SetWeightMode ;
------------------------------------------------------------
procedure SetCovWeight (ID : CoverageIDType; Weight : integer) is
------------------------------------------------------------
begin
CovStructPtr(ID.ID).CovWeight := Weight ;
end procedure SetCovWeight ;
------------------------------------------------------------
impure function GetCovWeight (ID : CoverageIDType) return integer is
------------------------------------------------------------
begin
return CovStructPtr(ID.ID).CovWeight ;
end function GetCovWeight ;
------------------------------------------------------------
procedure SetBinSize (ID : CoverageIDType; NewNumBins : integer) is
-- Sets a CovBin to a particular size
-- Use for small bins to save space or large bins to
-- suppress the resize and copy as a CovBin autosizes.
------------------------------------------------------------
variable oldCovBinPtr : CovBinPtrType ;
begin
if CovStructPtr(ID.ID).CovBinPtr = NULL then
CovStructPtr(ID.ID).CovBinPtr := new CovBinInternalType(1 to NewNumBins) ;
elsif NewNumBins > CovStructPtr(ID.ID).CovBinPtr'length then
-- make message bigger
oldCovBinPtr := CovStructPtr(ID.ID).CovBinPtr ;
CovStructPtr(ID.ID).CovBinPtr := new CovBinInternalType(1 to NewNumBins) ;
CovStructPtr(ID.ID).CovBinPtr.all(1 to CovStructPtr(ID.ID).NumBins) := oldCovBinPtr.all(1 to CovStructPtr(ID.ID).NumBins) ;
deallocate(oldCovBinPtr) ;
end if ;
end procedure SetBinSize ;
------------------------------------------------------------
-- pt local
impure function NormalizeNumBins(ID : CoverageIDType; ReqNumBins : integer ) return integer is
variable NormNumBins : integer := MIN_NUM_BINS ;
begin
while NormNumBins < ReqNumBins loop
NormNumBins := NormNumBins + MIN_NUM_BINS ;
end loop ;
return NormNumBins ;
end function NormalizeNumBins ;
------------------------------------------------------------
-- pt local
procedure GrowBins (ID : CoverageIDType; ReqNumBins : integer) is
variable oldCovBinPtr : CovBinPtrType ;
variable NewNumBins : integer ;
begin
NewNumBins := CovStructPtr(ID.ID).NumBins + ReqNumBins ;
if CovStructPtr(ID.ID).CovBinPtr = NULL then
CovStructPtr(ID.ID).CovBinPtr := new CovBinInternalType(1 to NormalizeNumBins(ID, NewNumBins)) ;
elsif NewNumBins > CovStructPtr(ID.ID).CovBinPtr'length then
-- make message bigger
oldCovBinPtr := CovStructPtr(ID.ID).CovBinPtr ;
CovStructPtr(ID.ID).CovBinPtr := new CovBinInternalType(1 to NormalizeNumBins(ID, NewNumBins)) ;
CovStructPtr(ID.ID).CovBinPtr.all(1 to CovStructPtr(ID.ID).NumBins) := oldCovBinPtr.all(1 to CovStructPtr(ID.ID).NumBins) ;
deallocate(oldCovBinPtr) ;
end if ;
end procedure GrowBins ;
------------------------------------------------------------
-- pt local, called by InsertBin
-- Finds index of bin if it is inside an existing bins
procedure FindBinInside(
ID : CoverageIDType ;
BinVal : RangeArrayType ;
Position : out integer ;
FoundInside : out boolean
) is
begin
Position := CovStructPtr(ID.ID).NumBins + 1 ;
FoundInside := FALSE ;
FindLoop : for i in CovStructPtr(ID.ID).NumBins downto 1 loop
-- skip this CovBin if CovPoint is not in it
next FindLoop when not inside(BinVal, CovStructPtr(ID.ID).CovBinPtr(i).BinVal.all) ;
Position := i ;
FoundInside := TRUE ;
exit ;
end loop ;
end procedure FindBinInside ;
------------------------------------------------------------
-- pt local
-- Inserts values into a new bin.
-- Called by InsertBin
procedure InsertNewBin(
ID : CoverageIDType ;
BinVal : RangeArrayType ;
Action : integer ;
Count : integer ;
AtLeast : integer ;
Weight : integer ;
Name : string ;
PercentCov : real
) is
begin
if (not IsInitialized(ID)) then -- VendorCov
if (BinVal'length > 1) then -- Cross Bin -- VendorCov
CovStructPtr(ID.ID).VendorCovHandle := VendorCovCrossCreate(GetCovModelName(ID)) ; -- VendorCov
else -- VendorCov
CovStructPtr(ID.ID).VendorCovHandle := VendorCovPointCreate(GetCovModelName(ID)); -- VendorCov
end if; -- VendorCov
end if; -- VendorCov
VendorCovBinAdd(CovStructPtr(ID.ID).VendorCovHandle, ToVendorCovBinVal(BinVal), Action, AtLeast, Name) ; -- VendorCov
CovStructPtr(ID.ID).NumBins := CovStructPtr(ID.ID).NumBins + 1 ;
CovStructPtr(ID.ID).CovBinPtr.all(CovStructPtr(ID.ID).NumBins).BinVal := new RangeArrayType'(BinVal) ;
CovStructPtr(ID.ID).CovBinPtr.all(CovStructPtr(ID.ID).NumBins).Action := Action ;
CovStructPtr(ID.ID).CovBinPtr.all(CovStructPtr(ID.ID).NumBins).Count := Count ;
CovStructPtr(ID.ID).CovBinPtr.all(CovStructPtr(ID.ID).NumBins).AtLeast := AtLeast ;
CovStructPtr(ID.ID).CovBinPtr.all(CovStructPtr(ID.ID).NumBins).Weight := Weight ;
CovStructPtr(ID.ID).CovBinPtr.all(CovStructPtr(ID.ID).NumBins).Name := new String'(Name) ;
CovStructPtr(ID.ID).CovBinPtr.all(CovStructPtr(ID.ID).NumBins).PercentCov := PercentCov ;
end procedure InsertNewBin ;
------------------------------------------------------------
-- pt local
-- Inserts values into a new bin.
-- Called by InsertBin
procedure MergeBin (
ID : CoverageIDType ;
Position : Natural ;
Count : integer ;
AtLeast : integer ;
Weight : integer
) is
begin
CovStructPtr(ID.ID).CovBinPtr.all(Position).Count := CovStructPtr(ID.ID).CovBinPtr.all(Position).Count + Count ;
CovStructPtr(ID.ID).CovBinPtr.all(Position).AtLeast := CovStructPtr(ID.ID).CovBinPtr.all(Position).AtLeast + AtLeast ;
CovStructPtr(ID.ID).CovBinPtr.all(Position).Weight := CovStructPtr(ID.ID).CovBinPtr.all(Position).Weight + Weight ;
CovStructPtr(ID.ID).CovBinPtr.all(Position).PercentCov := CalcPercentCov(
Count => CovStructPtr(ID.ID).CovBinPtr.all(Position).Count,
AtLeast => CovStructPtr(ID.ID).CovBinPtr.all(Position).AtLeast ) ;
end procedure MergeBin ;
------------------------------------------------------------
-- pt local
-- All insertion comes here
-- Enforces the general insertion use model:
-- Earlier bins supercede later bins - except with COUNT_ALL
-- Add Illegal and Ignore bins first to remove regions of larger count bins
-- Later ignore bins can be used to miss an illegal catch-all
-- Add Illegal bins last as a catch-all to find things that missed other bins
procedure InsertBin(
ID : CoverageIDType ;
BinVal : RangeArrayType ;
Action : integer ;
Count : integer ;
AtLeast : integer ;
Weight : integer ;
Name : string
) is
variable Position : integer ;
variable FoundInside : boolean ;
variable PercentCov : real ;
begin
PercentCov := CalcPercentCov(Count => Count, AtLeast => AtLeast) ;
if not CovStructPtr(ID.ID).MergingEnable then
InsertNewBin(ID, BinVal, Action, Count, AtLeast, Weight, Name, PercentCov) ;
else -- handle merging
-- future optimization, FindBinInside only checks against Ignore and Illegal bins
FindBinInside(ID, BinVal, Position, FoundInside) ;
if not FoundInside then
InsertNewBin(ID, BinVal, Action, Count, AtLeast, Weight, Name, PercentCov) ;
elsif Action = COV_COUNT then
-- when check only ignore and illegal bins, only action is to drop
if CovStructPtr(ID.ID).CovBinPtr.all(Position).Action /= COV_COUNT then
null ; -- drop count bin when it is inside a Illegal or Ignore bin
elsif CovStructPtr(ID.ID).CovBinPtr.all(Position).BinVal.all = BinVal and CovStructPtr(ID.ID).CovBinPtr.all(Position).Name.all = Name then
-- Bins match, so merge the count values
MergeBin (ID, Position, Count, AtLeast, Weight) ;
else
-- Bins overlap, but do not match, insert new bin
InsertNewBin(ID, BinVal, Action, Count, AtLeast, Weight, Name, PercentCov) ;
end if;
elsif Action = COV_IGNORE then
-- when check only ignore and illegal bins, only action is to report error
if CovStructPtr(ID.ID).CovBinPtr.all(Position).Action = COV_COUNT then
InsertNewBin(ID, BinVal, Action, Count, AtLeast, Weight, Name, PercentCov) ;
else
Alert(CovStructPtr(ID.ID).AlertLogID, GetNamePlus(ID, prefix => "in ", suffix => ", ") & "CoveragePkg.InsertBin (AddBins/AddCross):" &
" ignore bin dropped. It is a subset of prior bin", ERROR) ;
end if;
elsif Action = COV_ILLEGAL then
-- when check only ignore and illegal bins, only action is to report error
if CovStructPtr(ID.ID).CovBinPtr.all(Position).Action = COV_COUNT then
InsertNewBin(ID, BinVal, Action, Count, AtLeast, Weight, Name, PercentCov) ;
else
Alert(CovStructPtr(ID.ID).AlertLogID, GetNamePlus(ID, prefix => "in ", suffix => ", ") & "CoveragePkg.InsertBin (AddBins/AddCross):" &
" illegal bin dropped. It is a subset of prior bin", ERROR) ;
end if;
end if ;
end if ; -- merging enabled
end procedure InsertBin ;
------------------------------------------------------------
procedure AddBins (
------------------------------------------------------------
ID : CoverageIDType ;
Name : String ;
AtLeast : integer ;
Weight : integer ;
CovBin : CovBinType
) is
variable vCalcAtLeast : integer ;
variable vCalcWeight : integer ;
begin
if BinValLengthNotEqual(ID, 1) then
Alert(CovStructPtr(ID.ID).AlertLogID, "CoveragePkg.AddBins: Coverage bins of different dimensions prohibited", FAILURE) ;
return ;
end if ;
GrowBins(ID, CovBin'length) ;
for i in CovBin'range loop
if CovBin(i).Action = COV_COUNT then
vCalcAtLeast := maximum(AtLeast, CovBin(i).AtLeast) ;
vCalcWeight := maximum(Weight, CovBin(i).Weight) ;
else
vCalcAtLeast := 0 ;
vCalcWeight := 0 ;
end if ;
InsertBin(
ID => ID,
BinVal => CovBin(i).BinVal,
Action => CovBin(i).Action,
Count => CovBin(i).Count,
AtLeast => vCalcAtLeast,
Weight => vCalcWeight,
Name => Name
) ;
end loop ;
end procedure AddBins ;
------------------------------------------------------------
procedure AddBins (ID : CoverageIDType; Name : String ; AtLeast : integer ; CovBin : CovBinType ) is
------------------------------------------------------------
begin
AddBins(ID, Name, AtLeast, 1, CovBin) ;
end procedure AddBins ;
------------------------------------------------------------
procedure AddBins (ID : CoverageIDType; Name : String ; CovBin : CovBinType) is
------------------------------------------------------------
begin
AddBins(ID, Name, 1, 1, CovBin) ;
end procedure AddBins ;
------------------------------------------------------------
procedure AddBins (ID : CoverageIDType; AtLeast : integer ; Weight : integer ; CovBin : CovBinType ) is
------------------------------------------------------------
begin
AddBins(ID, "", AtLeast, Weight, CovBin) ;
end procedure AddBins ;
------------------------------------------------------------
procedure AddBins (ID : CoverageIDType; AtLeast : integer ; CovBin : CovBinType ) is
------------------------------------------------------------
begin
AddBins(ID, "", AtLeast, 1, CovBin) ;
end procedure AddBins ;
------------------------------------------------------------
procedure AddBins (ID : CoverageIDType; CovBin : CovBinType ) is
------------------------------------------------------------
begin
AddBins(ID, "", 1, 1, CovBin) ;
end procedure AddBins ;
------------------------------------------------------------
procedure AddCross(
------------------------------------------------------------
ID : CoverageIDType ;
Name : string ;
AtLeast : integer ;
Weight : integer ;
Bin1, Bin2 : CovBinType ;
Bin3, Bin4, Bin5, Bin6, Bin7, Bin8, Bin9, Bin10, Bin11, Bin12, Bin13,
Bin14, Bin15, Bin16, Bin17, Bin18, Bin19, Bin20 : CovBinType := NULL_BIN
) is
constant BIN_LENS : integer_vector :=
BinLengths(
Bin1, Bin2, Bin3, Bin4, Bin5, Bin6, Bin7, Bin8, Bin9, Bin10, Bin11,
Bin12, Bin13, Bin14, Bin15, Bin16, Bin17, Bin18, Bin19, Bin20
) ;
constant NUM_NEW_BINS : integer := CalcNumCrossBins(BIN_LENS) ;
variable BinIndex : integer_vector(1 to BIN_LENS'length) := (others => 1) ;
variable CrossBins : CovBinType(BinIndex'range) ;
variable vCalcAction, vCalcCount, vCalcAtLeast, vCalcWeight : integer ;
variable vCalcBinVal : RangeArrayType(BinIndex'range) ;
begin
if BinValLengthNotEqual(ID, BIN_LENS'length) then
Alert(CovStructPtr(ID.ID).AlertLogID, "CoveragePkg.AddCross: Cross coverage bins of different dimensions prohibited", FAILURE) ;
return ;
end if ;
GrowBins(ID, NUM_NEW_BINS) ;
vCalcCount := 0 ;
for MatrixIndex in 1 to NUM_NEW_BINS loop
CrossBins := ConcatenateBins(BinIndex,
Bin1, Bin2, Bin3, Bin4, Bin5, Bin6, Bin7, Bin8, Bin9, Bin10, Bin11,
Bin12, Bin13, Bin14, Bin15, Bin16, Bin17, Bin18, Bin19, Bin20
) ;
vCalcAction := MergeState (CrossBins) ;
vCalcBinVal := MergeBinVal(CrossBins) ;
vCalcAtLeast := MergeAtLeast( vCalcAction, AtLeast, CrossBins) ;
vCalcWeight := MergeWeight ( vCalcAction, Weight, CrossBins) ;
InsertBin(ID, vCalcBinVal, vCalcAction, vCalcCount, vCalcAtLeast, vCalcWeight, Name) ;
IncBinIndex( BinIndex, BIN_LENS) ; -- increment right most one, then if overflow, increment next
end loop ;
end procedure AddCross ;
------------------------------------------------------------
procedure AddCross(
------------------------------------------------------------
ID : CoverageIDType ;
Name : string ;
AtLeast : integer ;
Bin1, Bin2 : CovBinType ;
Bin3, Bin4, Bin5, Bin6, Bin7, Bin8, Bin9, Bin10, Bin11, Bin12, Bin13,
Bin14, Bin15, Bin16, Bin17, Bin18, Bin19, Bin20 : CovBinType := NULL_BIN
) is
begin
AddCross(ID, Name, AtLeast, 1,
Bin1, Bin2, Bin3, Bin4, Bin5, Bin6, Bin7, Bin8, Bin9, Bin10, Bin11,
Bin12, Bin13, Bin14, Bin15, Bin16, Bin17, Bin18, Bin19, Bin20
) ;
end procedure AddCross ;
------------------------------------------------------------
procedure AddCross(
------------------------------------------------------------
ID : CoverageIDType ;
Name : string ;
Bin1, Bin2 : CovBinType ;
Bin3, Bin4, Bin5, Bin6, Bin7, Bin8, Bin9, Bin10, Bin11, Bin12, Bin13,
Bin14, Bin15, Bin16, Bin17, Bin18, Bin19, Bin20 : CovBinType := NULL_BIN
) is
begin
AddCross(ID, Name, 1, 1,
Bin1, Bin2, Bin3, Bin4, Bin5, Bin6, Bin7, Bin8, Bin9, Bin10, Bin11,
Bin12, Bin13, Bin14, Bin15, Bin16, Bin17, Bin18, Bin19, Bin20
) ;
end procedure AddCross ;
------------------------------------------------------------
procedure AddCross(
------------------------------------------------------------
ID : CoverageIDType ;
AtLeast : integer ;
Weight : integer ;
Bin1, Bin2 : CovBinType ;
Bin3, Bin4, Bin5, Bin6, Bin7, Bin8, Bin9, Bin10, Bin11, Bin12, Bin13,
Bin14, Bin15, Bin16, Bin17, Bin18, Bin19, Bin20 : CovBinType := NULL_BIN
) is
begin
AddCross(ID, "", AtLeast, Weight,
Bin1, Bin2, Bin3, Bin4, Bin5, Bin6, Bin7, Bin8, Bin9, Bin10, Bin11,
Bin12, Bin13, Bin14, Bin15, Bin16, Bin17, Bin18, Bin19, Bin20
) ;
end procedure AddCross ;
------------------------------------------------------------
procedure AddCross(
------------------------------------------------------------
ID : CoverageIDType ;
AtLeast : integer ;
Bin1, Bin2 : CovBinType ;
Bin3, Bin4, Bin5, Bin6, Bin7, Bin8, Bin9, Bin10, Bin11, Bin12, Bin13,
Bin14, Bin15, Bin16, Bin17, Bin18, Bin19, Bin20 : CovBinType := NULL_BIN
) is
begin
AddCross(ID, "", AtLeast, 1,
Bin1, Bin2, Bin3, Bin4, Bin5, Bin6, Bin7, Bin8, Bin9, Bin10, Bin11,
Bin12, Bin13, Bin14, Bin15, Bin16, Bin17, Bin18, Bin19, Bin20
) ;
end procedure AddCross ;
------------------------------------------------------------
procedure AddCross(
------------------------------------------------------------
ID : CoverageIDType ;
Bin1, Bin2 : CovBinType ;
Bin3, Bin4, Bin5, Bin6, Bin7, Bin8, Bin9, Bin10, Bin11, Bin12, Bin13,
Bin14, Bin15, Bin16, Bin17, Bin18, Bin19, Bin20 : CovBinType := NULL_BIN
) is
begin
AddCross(ID, "", 1, 1,
Bin1, Bin2, Bin3, Bin4, Bin5, Bin6, Bin7, Bin8, Bin9, Bin10, Bin11,
Bin12, Bin13, Bin14, Bin15, Bin16, Bin17, Bin18, Bin19, Bin20
) ;
end procedure AddCross ;
------------------------------------------------------------
procedure DeallocateBins(CoverID : CoverageIDType) is
------------------------------------------------------------
constant Index : integer := CoverID.ID ;
begin
-- Local for a particular CoverageModel
if CovStructPtr(Index).CovBinPtr /= NULL then
for i in 1 to CovStructPtr(Index).NumBins loop
deallocate(CovStructPtr(Index).CovBinPtr(i).BinVal) ;
deallocate(CovStructPtr(Index).CovBinPtr(i).Name) ;
end loop ;
deallocate(CovStructPtr(Index).CovBinPtr) ;
end if ;
CovStructPtr(Index).NumBins := 0 ;
end procedure DeallocateBins ;
------------------------------------------------------------
procedure Deallocate(ID : CoverageIDType) is
------------------------------------------------------------
constant Index : integer := ID.ID ;
begin
--!!?? These are only done when removing all coverage models.
-- -- Globals - for all coverage models
-- WritePassFailVar := COV_OPT_INIT_PARM_DETECT ;
-- WriteBinInfoVar := COV_OPT_INIT_PARM_DETECT ;
-- WriteCountVar := COV_OPT_INIT_PARM_DETECT ;
-- WriteAnyIllegalVar := COV_OPT_INIT_PARM_DETECT ;
-- WritePrefixVar.deallocate ;
-- PassNameVar.deallocate ;
-- FailNameVar.deallocate ;
DeallocateBins(ID) ;
DeallocateName(ID) ;
DeallocateMessage(ID) ;
-- Restore internal variables to their default values
-- CovStructPtr(Index) := COV_STRUCT_INIT ;
CovStructPtr(Index).BinValLength := 1 ;
CovStructPtr(Index).VendorCovHandle := 0 ;
CovStructPtr(Index).ItemCount := 0 ;
CovStructPtr(Index).LastIndex := 1 ;
CovStructPtr(Index).LastStimGenIndex := 1 ;
-- Changing these is beyond what deallocate should do.
CovStructPtr(Index).NextPointMode := RANDOM ;
CovStructPtr(Index).IllegalMode := ILLEGAL_ON ;
CovStructPtr(Index).IllegalModeLevel := ERROR ;
CovStructPtr(Index).WeightMode := AT_LEAST ;
CovStructPtr(Index).WeightScale := 1.0 ;
CovStructPtr(Index).ThresholdingEnable := FALSE ;
CovStructPtr(Index).CovThreshold := 45.0 ;
CovStructPtr(Index).CovTarget := 100.0 ;
CovStructPtr(Index).MergingEnable := FALSE ;
CovStructPtr(Index).CountMode := COUNT_FIRST ;
-- CovStructPtr(Index).RV := (1, 7) ;
-- CovStructPtr(Index).RvSeedInit := FALSE ;
-- CovStructPtr(Index).AlertLogID := OSVVM_COVERAGE_ALERTLOG_ID ;
end procedure deallocate ;
------------------------------------------------------------
-- Local
procedure ICoverIndex(ID : CoverageIDType; Index : integer ; CovPoint : integer_vector ) is
------------------------------------------------------------
variable buf : line ;
begin
-- Update Count, PercentCov
CovStructPtr(ID.ID).CovBinPtr(Index).Count := CovStructPtr(ID.ID).CovBinPtr(Index).Count + CovStructPtr(ID.ID).CovBinPtr(Index).action ;
VendorCovBinInc(CovStructPtr(ID.ID).VendorCovHandle, Index); -- VendorCov
CovStructPtr(ID.ID).CovBinPtr(Index).PercentCov := CalcPercentCov(
Count => CovStructPtr(ID.ID).CovBinPtr.all(Index).Count,
AtLeast => CovStructPtr(ID.ID).CovBinPtr.all(Index).AtLeast
) ;
if CovStructPtr(ID.ID).CovBinPtr(Index).action = COV_ILLEGAL then
if CovStructPtr(ID.ID).IllegalMode /= ILLEGAL_OFF then
-- if CovPoint = NULL_INTV then
if CovPoint'length = 0 then
alert(CovStructPtr(ID.ID).AlertLogID, GetNamePlus(ID, prefix => "in ", suffix => ", ") & "CoveragePkg.ICoverLast:" &
" Value randomized is in an illegal bin.", CovStructPtr(ID.ID).IllegalModeLevel) ;
else
write(buf, CovPoint) ;
alert(CovStructPtr(ID.ID).AlertLogID, GetNamePlus(ID, prefix => "in ", suffix => ", ") & "CoveragePkg.ICover:" &
" Value " & buf.all & " is in an illegal bin.", CovStructPtr(ID.ID).IllegalModeLevel) ;
deallocate(buf) ;
end if ;
else
IncAlertCount(CovStructPtr(ID.ID).AlertLogID, ERROR) ; -- silent alert.
end if ;
end if ;
end procedure ICoverIndex ;
------------------------------------------------------------
procedure ICoverLast (ID : CoverageIDType) is
------------------------------------------------------------
begin
ICoverIndex(ID, CovStructPtr(ID.ID).LastStimGenIndex, NULL_INTV) ;
end procedure ICoverLast ;
------------------------------------------------------------
procedure ICover(ID : CoverageIDType; CovPoint : integer_vector) is
------------------------------------------------------------
begin
if CovPoint'length /= CovStructPtr(ID.ID).BinValLength then
Alert(CovStructPtr(ID.ID).AlertLogID, GetNamePlus(ID, prefix => "in ", suffix => ", ") & "CoveragePkg." &
" ICover: CovPoint length = " & to_string(CovPoint'length) &
" does not match Coverage Bin dimensions = " & to_string(CovStructPtr(ID.ID).BinValLength), FAILURE) ;
-- Search CovStructPtr(ID.ID).LastStimGenIndex first. Important it is not CovStructPtr(ID.ID).LastIndex seen by ICover below.
-- If find an object in a sentinal bin - only looks in sentinal bin after that point
elsif CovStructPtr(ID.ID).CountMode = COUNT_FIRST and inside(CovPoint, CovStructPtr(ID.ID).CovBinPtr(CovStructPtr(ID.ID).LastStimGenIndex).BinVal.all) then
ICoverIndex(ID, CovStructPtr(ID.ID).LastStimGenIndex, CovPoint) ;
else
CovLoop : for i in 1 to CovStructPtr(ID.ID).NumBins loop
-- skip this CovBin if CovPoint is not in it
next CovLoop when not inside(CovPoint, CovStructPtr(ID.ID).CovBinPtr(i).BinVal.all) ;
-- Mark Covered
CovStructPtr(ID.ID).LastIndex := i ; -- Mark found index
ICoverIndex(ID, i, CovPoint) ;
exit CovLoop when CovStructPtr(ID.ID).CountMode = COUNT_FIRST ; -- only find first one
end loop CovLoop ;
end if ;
end procedure ICover ;
------------------------------------------------------------
procedure ICover (ID : CoverageIDType; CovPoint : integer) is
------------------------------------------------------------
begin
ICover(ID, (1=> CovPoint)) ;
end procedure ICover ;
------------------------------------------------------------
procedure TCover (CoverID : CoverageIDType; A : integer) is
------------------------------------------------------------
constant ID : integer := CoverID.ID ;
begin
CovStructPtr(ID).TCoverCount := CovStructPtr(ID).TCoverCount + 1 ;
CovStructPtr(ID).TCoverValuePtr.all := CovStructPtr(ID).TCoverValuePtr.all(2 to CovStructPtr(ID).BinValLength) & A ;
if (CovStructPtr(ID).TCoverCount >= CovStructPtr(ID).BinValLength) then
ICover(CoverID, CovStructPtr(ID).TCoverValuePtr.all) ;
end if ;
end procedure TCover ;
------------------------------------------------------------
procedure ClearCov (ID : CoverageIDType) is
------------------------------------------------------------
begin
for i in 1 to CovStructPtr(ID.ID).NumBins loop
CovStructPtr(ID.ID).CovBinPtr(i).Count := 0 ;
CovStructPtr(ID.ID).CovBinPtr(i).PercentCov := CalcPercentCov(
Count => CovStructPtr(ID.ID).CovBinPtr.all(i).Count,
AtLeast => CovStructPtr(ID.ID).CovBinPtr.all(i).AtLeast ) ;
end loop ;
end procedure ClearCov ;
------------------------------------------------------------
impure function GetMinCov (ID : CoverageIDType) return real is
------------------------------------------------------------
variable MinCov : real := real'right ; -- big number
begin
CovLoop : for i in 1 to CovStructPtr(ID.ID).NumBins loop
if CovStructPtr(ID.ID).CovBinPtr(i).action = COV_COUNT and CovStructPtr(ID.ID).CovBinPtr(i).PercentCov < MinCov then
MinCov := CovStructPtr(ID.ID).CovBinPtr(i).PercentCov ;
end if ;
end loop CovLoop ;
return MinCov ;
end function GetMinCov ;
------------------------------------------------------------
impure function GetMinCount (ID : CoverageIDType) return integer is
------------------------------------------------------------
variable MinCount : integer := integer'right ; -- big number
begin
CovLoop : for i in 1 to CovStructPtr(ID.ID).NumBins loop
if CovStructPtr(ID.ID).CovBinPtr(i).action = COV_COUNT and CovStructPtr(ID.ID).CovBinPtr(i).Count < MinCount then
MinCount := CovStructPtr(ID.ID).CovBinPtr(i).Count ;
end if ;
end loop CovLoop ;
return MinCount ;
end function GetMinCount ;
------------------------------------------------------------
impure function GetMaxCov (ID : CoverageIDType) return real is
------------------------------------------------------------
variable MaxCov : real := 0.0 ;
begin
CovLoop : for i in 1 to CovStructPtr(ID.ID).NumBins loop
if CovStructPtr(ID.ID).CovBinPtr(i).action = COV_COUNT and CovStructPtr(ID.ID).CovBinPtr(i).PercentCov > MaxCov then
MaxCov := CovStructPtr(ID.ID).CovBinPtr(i).PercentCov ;
end if ;
end loop CovLoop ;
return MaxCov ;
end function GetMaxCov ;
------------------------------------------------------------
impure function GetMaxCount (ID : CoverageIDType) return integer is
------------------------------------------------------------
variable MaxCount : integer := 0 ;
begin
CovLoop : for i in 1 to CovStructPtr(ID.ID).NumBins loop
if CovStructPtr(ID.ID).CovBinPtr(i).action = COV_COUNT and CovStructPtr(ID.ID).CovBinPtr(i).Count > MaxCount then
MaxCount := CovStructPtr(ID.ID).CovBinPtr(i).Count ;
end if ;
end loop CovLoop ;
return MaxCount ;
end function GetMaxCount ;
------------------------------------------------------------
impure function CountCovHoles (ID : CoverageIDType; PercentCov : real ) return integer is
------------------------------------------------------------
variable HoleCount : integer := 0 ;
begin
CovLoop : for i in 1 to CovStructPtr(ID.ID).NumBins loop
if CovStructPtr(ID.ID).CovBinPtr(i).action = COV_COUNT and CovStructPtr(ID.ID).CovBinPtr(i).PercentCov < PercentCov then
HoleCount := HoleCount + 1 ;
end if ;
end loop CovLoop ;
return HoleCount ;
end function CountCovHoles ;
------------------------------------------------------------
impure function CountCovHoles (ID : CoverageIDType) return integer is
------------------------------------------------------------
begin
return CountCovHoles(ID, CovStructPtr(ID.ID).CovTarget) ;
end function CountCovHoles ;
------------------------------------------------------------
impure function IsCovered (ID : CoverageIDType; PercentCov : real ) return boolean is
------------------------------------------------------------
begin
-- AlertIf(CovStructPtr(ID.ID).NumBins < 1, OSVVM_COVERAGE_ALERTLOG_ID, "CoveragePkg.IsCovered: Empty Coverage Model", failure) ;
return CountCovHoles(ID, PercentCov) = 0 ;
end function IsCovered ;
------------------------------------------------------------
impure function IsCovered (ID : CoverageIDType) return boolean is
------------------------------------------------------------
begin
-- AlertIf(CovStructPtr(ID.ID).NumBins < 1, OSVVM_COVERAGE_ALERTLOG_ID, "CoveragePkg.IsCovered: Empty Coverage Model", failure) ;
return CountCovHoles(ID, CovStructPtr(ID.ID).CovTarget) = 0 ;
end function IsCovered ;
------------------------------------------------------------
procedure GetTotalCovCountAndGoal (ID : CoverageIDType; PercentCov : real; TotalCovCount : out integer; TotalCovGoal : out integer ) is
------------------------------------------------------------
variable ScaledCovGoal : integer := 0 ;
begin
TotalCovCount := 0 ;
TotalCovGoal := 0 ;
BinLoop : for i in 1 to CovStructPtr(ID.ID).NumBins loop
if CovStructPtr(ID.ID).CovBinPtr(i).action = COV_COUNT then
ScaledCovGoal := integer(ceil(PercentCov * real(CovStructPtr(ID.ID).CovBinPtr(i).AtLeast)/100.0)) ;
TotalCovGoal := TotalCovGoal + ScaledCovGoal ;
if CovStructPtr(ID.ID).CovBinPtr(i).Count <= ScaledCovGoal then
TotalCovCount := TotalCovCount + CovStructPtr(ID.ID).CovBinPtr(i).Count ;
else
-- do not count the extra values that exceed their cov goal
TotalCovCount := TotalCovCount + ScaledCovGoal ;
end if ;
end if ;
end loop BinLoop ;
end procedure GetTotalCovCountAndGoal ;
------------------------------------------------------------
procedure GetTotalCovCountAndGoal (ID : CoverageIDType; TotalCovCount : out integer; TotalCovGoal : out integer ) is
------------------------------------------------------------
begin
GetTotalCovCountAndGoal(ID, CovStructPtr(ID.ID).CovTarget, TotalCovCount, TotalCovGoal) ;
end procedure GetTotalCovCountAndGoal ;
------------------------------------------------------------
impure function GetCov (ID : CoverageIDType; PercentCov : real ) return real is
------------------------------------------------------------
variable TotalCovCount, TotalCovGoal : integer ;
begin
GetTotalCovCountAndGoal(ID, PercentCov, TotalCovCount, TotalCovGoal) ;
if TotalCovGoal > 0 then
return 100.0 * real(TotalCovCount) / real(TotalCovGoal) ;
else
return 0.0 ;
end if ;
end function GetCov ;
------------------------------------------------------------
impure function GetCov (ID : CoverageIDType) return real is
------------------------------------------------------------
begin
return GetCov(ID, CovStructPtr(ID.ID).CovTarget ) ;
end function GetCov ;
------------------------------------------------------------
impure function GetTotalCovCount (ID : CoverageIDType; PercentCov : real ) return integer is
------------------------------------------------------------
variable TotalCovCount, TotalCovGoal : integer ;
begin
GetTotalCovCountAndGoal(ID, PercentCov, TotalCovCount, TotalCovGoal) ;
return TotalCovCount ;
end function GetTotalCovCount ;
------------------------------------------------------------
impure function GetTotalCovCount (ID : CoverageIDType) return integer is
------------------------------------------------------------
begin
return GetTotalCovCount(ID, CovStructPtr(ID.ID).CovTarget) ;
end function GetTotalCovCount ;
------------------------------------------------------------
impure function GetTotalCovGoal (ID : CoverageIDType; PercentCov : real ) return integer is
------------------------------------------------------------
variable TotalCovCount, TotalCovGoal : integer ;
begin
GetTotalCovCountAndGoal(ID, PercentCov, TotalCovCount, TotalCovGoal) ;
return TotalCovGoal ;
end function GetTotalCovGoal ;
------------------------------------------------------------
impure function GetTotalCovGoal (ID : CoverageIDType) return integer is
------------------------------------------------------------
begin
return GetTotalCovGoal(ID, CovStructPtr(ID.ID).CovTarget) ;
end function GetTotalCovGoal ;
------------------------------------------------------------
impure function GetItemCount (ID : CoverageIDType) return integer is
------------------------------------------------------------
begin
return CovStructPtr(ID.ID).ItemCount ;
end function GetItemCount ;
-- Return Index Values
------------------------------------------------------------
impure function GetNumBins (ID : CoverageIDType) return integer is
------------------------------------------------------------
begin
return CovStructPtr(ID.ID).NumBins ;
end function GetNumBins ;
------------------------------------------------------------
impure function GetLastIndex (ID : CoverageIDType) return integer is
------------------------------------------------------------
begin
return CovStructPtr(ID.ID).LastIndex ;
end function GetLastIndex ;
------------------------------------------------------------
impure function CalcWeight (ID : CoverageIDType; BinIndex : integer ; MaxCovPercent : real ) return integer is
-- pt local
------------------------------------------------------------
begin
case CovStructPtr(ID.ID).WeightMode is
when AT_LEAST => -- AtLeast
return CovStructPtr(ID.ID).CovBinPtr(BinIndex).AtLeast ;
when WEIGHT => -- Weight
return CovStructPtr(ID.ID).CovBinPtr(BinIndex).Weight ;
when REMAIN => -- (Adjust * AtLeast) - Count
--?? simpler integer( Ceil (MaxCovPercent - CovStructPtr(ID.ID).CovBinPtr(BinIndex).PercentCov)) * CovStructPtr(ID.ID).CovBinPtr(BinIndex).AtLeast
return integer( Ceil( MaxCovPercent * real(CovStructPtr(ID.ID).CovBinPtr(BinIndex).AtLeast)/100.0)) -
CovStructPtr(ID.ID).CovBinPtr(BinIndex).Count ;
when REMAIN_EXP => -- Weight * (REMAIN **WeightScale)
-- Experimental may be removed
-- CAUTION: for large numbers and/or WeightScale > 2.0, result can be > 2**31 (max integer value)
-- both Weight and WeightScale default to 1
return CovStructPtr(ID.ID).CovBinPtr(BinIndex).Weight *
integer( Ceil (
( (MaxCovPercent * real(CovStructPtr(ID.ID).CovBinPtr(BinIndex).AtLeast)/100.0) -
real(CovStructPtr(ID.ID).CovBinPtr(BinIndex).Count) ) ** CovStructPtr(ID.ID).WeightScale ) );
when REMAIN_SCALED => -- (WeightScale * Adjust * AtLeast) - Count
-- Experimental may be removed
-- Biases remainder toward AT_LEAST value.
-- WeightScale must be > 1.0
return integer( Ceil( CovStructPtr(ID.ID).WeightScale * MaxCovPercent * real(CovStructPtr(ID.ID).CovBinPtr(BinIndex).AtLeast)/100.0)) -
CovStructPtr(ID.ID).CovBinPtr(BinIndex).Count ;
when REMAIN_WEIGHT => -- Weight * ((WeightScale * Adjust * AtLeast) - Count)
-- Experimental may be removed
-- WeightScale must be > 1.0
return CovStructPtr(ID.ID).CovBinPtr(BinIndex).Weight * (
integer( Ceil( CovStructPtr(ID.ID).WeightScale * MaxCovPercent * real(CovStructPtr(ID.ID).CovBinPtr(BinIndex).AtLeast)/100.0)) -
CovStructPtr(ID.ID).CovBinPtr(BinIndex).Count) ;
end case ;
end function CalcWeight ;
------------------------------------------------------------
impure function GetRandIndex (ID : CoverageIDType; CovTargetPercent : real ) return integer is
------------------------------------------------------------
variable WeightVec : integer_vector(0 to CovStructPtr(ID.ID).NumBins-1) ; -- Prep for change to DistInt
variable MaxCovPercent : real ;
variable MinCovPercent : real ;
variable rInt : integer ;
begin
CovStructPtr(ID.ID).ItemCount := CovStructPtr(ID.ID).ItemCount + 1 ;
MinCovPercent := GetMinCov(ID) ;
if CovStructPtr(ID.ID).ThresholdingEnable then
MaxCovPercent := MinCovPercent + CovStructPtr(ID.ID).CovThreshold ;
if MinCovPercent < CovTargetPercent then
-- Clip at CovTargetPercent until reach CovTargetPercent
MaxCovPercent := minimum(MaxCovPercent, CovTargetPercent);
end if ;
else
if MinCovPercent < CovTargetPercent then
MaxCovPercent := CovTargetPercent ;
else
-- Done, Enable all bins
MaxCovPercent := GetMaxCov(ID) + 1.0 ;
-- MaxCovPercent := real'right ; -- weight scale issues
end if ;
end if ;
CovLoop : for i in 1 to CovStructPtr(ID.ID).NumBins loop
if CovStructPtr(ID.ID).CovBinPtr(i).action = COV_COUNT and CovStructPtr(ID.ID).CovBinPtr(i).PercentCov < MaxCovPercent then
-- Calculate Weight based on CovStructPtr(ID.ID).WeightMode
-- Scale to current percentage goal: MaxCov which can be < or > 100.0
WeightVec(i-1) := CalcWeight(ID, i, MaxCovPercent) ;
else
WeightVec(i-1) := 0 ;
end if ;
end loop CovLoop ;
-- DistInt returns integer range 0 to CovStructPtr(ID.ID).NumBins-1
-- Caution: DistInt can fail when sum(WeightVec) > 2**31
-- See notes in CalcWeight for REMAIN_EXP
-- CovStructPtr(ID.ID).LastStimGenIndex := 1 + RV.DistInt( WeightVec ) ; -- return range 1 to CovStructPtr(ID.ID).NumBins
DistInt(CovStructPtr(ID.ID).RV, rInt, WeightVec) ;
CovStructPtr(ID.ID).LastStimGenIndex := 1 + rInt ; -- return range 1 to CovStructPtr(ID.ID).NumBins
CovStructPtr(ID.ID).LastIndex := CovStructPtr(ID.ID).LastStimGenIndex ;
return CovStructPtr(ID.ID).LastStimGenIndex ;
end function GetRandIndex ;
------------------------------------------------------------
impure function GetRandIndex (ID : CoverageIDType) return integer is
------------------------------------------------------------
begin
return GetRandIndex(ID, CovStructPtr(ID.ID).CovTarget) ;
end function GetRandIndex ;
------------------------------------------------------------
impure function GetIncIndex (ID : CoverageIDType) return integer is
------------------------------------------------------------
variable CurIndex : integer ;
begin
CurIndex := CovStructPtr(ID.ID).LastStimGenIndex ;
CovStructPtr(ID.ID).LastStimGenIndex := (CovStructPtr(ID.ID).LastStimGenIndex mod CovStructPtr(ID.ID).NumBins) + 1 ;
CovStructPtr(ID.ID).LastIndex := CovStructPtr(ID.ID).LastStimGenIndex ;
return CurIndex ;
end function GetIncIndex ;
------------------------------------------------------------
impure function GetMinIndex (ID : CoverageIDType) return integer is
------------------------------------------------------------
variable MinCov : real := real'right ; -- big number
begin
CovLoop : for i in 1 to CovStructPtr(ID.ID).NumBins loop
if CovStructPtr(ID.ID).CovBinPtr(i).action = COV_COUNT and CovStructPtr(ID.ID).CovBinPtr(i).PercentCov < MinCov then
MinCov := CovStructPtr(ID.ID).CovBinPtr(i).PercentCov ;
CovStructPtr(ID.ID).LastStimGenIndex := i ;
end if ;
end loop CovLoop ;
CovStructPtr(ID.ID).LastIndex := CovStructPtr(ID.ID).LastStimGenIndex ;
return CovStructPtr(ID.ID).LastStimGenIndex ;
end function GetMinIndex ;
------------------------------------------------------------
impure function GetMaxIndex (ID : CoverageIDType) return integer is
------------------------------------------------------------
variable MaxCov : real := -1.0 ;
begin
CovLoop : for i in 1 to CovStructPtr(ID.ID).NumBins loop
if CovStructPtr(ID.ID).CovBinPtr(i).action = COV_COUNT and CovStructPtr(ID.ID).CovBinPtr(i).PercentCov > MaxCov then
MaxCov := CovStructPtr(ID.ID).CovBinPtr(i).PercentCov ;
CovStructPtr(ID.ID).LastStimGenIndex := i ;
end if ;
end loop CovLoop ;
CovStructPtr(ID.ID).LastIndex := CovStructPtr(ID.ID).LastStimGenIndex ;
return CovStructPtr(ID.ID).LastStimGenIndex ;
end function GetMaxIndex ;
------------------------------------------------------------
impure function GetNextIndex (ID : CoverageIDType; Mode : NextPointModeType) return integer is
------------------------------------------------------------
begin
case Mode is
when RANDOM => return GetRandIndex(ID) ;
when INCREMENT => return GetIncIndex (ID) ;
when others => return GetMinIndex (ID) ;
end case ;
end function GetNextIndex;
------------------------------------------------------------
impure function GetNextIndex (ID : CoverageIDType) return integer is
------------------------------------------------------------
begin
return GetNextIndex(ID, CovStructPtr(ID.ID).NextPointMode) ;
end function GetNextIndex ;
-- Return BinVals
------------------------------------------------------------
impure function GetBinVal (ID : CoverageIDType; BinIndex : integer ) return RangeArrayType is
------------------------------------------------------------
begin
return CovStructPtr(ID.ID).CovBinPtr( BinIndex ).BinVal.all ;
end function GetBinVal ;
------------------------------------------------------------
impure function GetLastBinVal (ID : CoverageIDType) return RangeArrayType is
------------------------------------------------------------
begin
return CovStructPtr(ID.ID).CovBinPtr( CovStructPtr(ID.ID).LastIndex ).BinVal.all ;
end function GetLastBinVal ;
------------------------------------------------------------
impure function GetRandBinVal (ID : CoverageIDType; PercentCov : real ) return RangeArrayType is
------------------------------------------------------------
begin
return CovStructPtr(ID.ID).CovBinPtr( GetRandIndex(ID, PercentCov) ).BinVal.all ; -- GetBinVal
end function GetRandBinVal ;
------------------------------------------------------------
impure function GetRandBinVal (ID : CoverageIDType) return RangeArrayType is
------------------------------------------------------------
begin
-- use global coverage target
return CovStructPtr(ID.ID).CovBinPtr( GetRandIndex(ID, CovStructPtr(ID.ID).CovTarget ) ).BinVal.all ; -- GetBinVal
end function GetRandBinVal ;
------------------------------------------------------------
impure function GetIncBinVal (ID : CoverageIDType) return RangeArrayType is
------------------------------------------------------------
begin
return GetBinVal(ID, GetIncIndex(ID)) ;
end function GetIncBinVal ;
------------------------------------------------------------
impure function GetMinBinVal (ID : CoverageIDType) return RangeArrayType is
------------------------------------------------------------
begin
-- use global coverage target
return GetBinVal(ID, GetMinIndex(ID) ) ;
end function GetMinBinVal ;
------------------------------------------------------------
impure function GetMaxBinVal (ID : CoverageIDType) return RangeArrayType is
------------------------------------------------------------
begin
-- use global coverage target
return GetBinVal(ID, GetMaxIndex(ID) ) ;
end function GetMaxBinVal ;
------------------------------------------------------------
impure function GetNextBinVal (ID : CoverageIDType; Mode : NextPointModeType) return RangeArrayType is
------------------------------------------------------------
begin
return GetBinVal(ID, GetNextIndex(ID, Mode)) ;
end function GetNextBinVal;
------------------------------------------------------------
impure function GetNextBinVal (ID : CoverageIDType) return RangeArrayType is
------------------------------------------------------------
begin
return GetBinVal(ID, GetNextIndex(ID, CovStructPtr(ID.ID).NextPointMode)) ;
end function GetNextBinVal ;
------------------------------------------------------------
-- deprecated, see GetRandBinVal
impure function RandCovBinVal (ID : CoverageIDType; PercentCov : real ) return RangeArrayType is
------------------------------------------------------------
begin
return CovStructPtr(ID.ID).CovBinPtr( GetRandIndex(ID, PercentCov) ).BinVal.all ; -- GetBinVal
end function RandCovBinVal ;
------------------------------------------------------------
-- deprecated, see GetRandBinVal
impure function RandCovBinVal (ID : CoverageIDType) return RangeArrayType is
------------------------------------------------------------
begin
-- use global coverage target
return CovStructPtr(ID.ID).CovBinPtr( GetRandIndex(ID, CovStructPtr(ID.ID).CovTarget ) ).BinVal.all ; -- GetBinVal
end function RandCovBinVal ;
------------------------------------------------------------
impure function GetHoleBinVal (ID : CoverageIDType; ReqHoleNum : integer ; PercentCov : real ) return RangeArrayType is
------------------------------------------------------------
variable HoleCount : integer := 0 ;
variable buf : line ;
begin
CovLoop : for i in 1 to CovStructPtr(ID.ID).NumBins loop
if CovStructPtr(ID.ID).CovBinPtr(i).action = COV_COUNT and CovStructPtr(ID.ID).CovBinPtr(i).PercentCov < PercentCov then
HoleCount := HoleCount + 1 ;
if HoleCount = ReqHoleNum then
return CovStructPtr(ID.ID).CovBinPtr(i).BinVal.all ;
end if ;
end if ;
end loop CovLoop ;
Alert(CovStructPtr(ID.ID).AlertLogID, GetNamePlus(ID, prefix => "in ", suffix => ", ") & "CoveragePkg.GetHoleBinVal:" &
" did not find a coverage hole. HoleCount = " & integer'image(HoleCount) &
" ReqHoleNum = " & integer'image(ReqHoleNum), ERROR
) ;
return CovStructPtr(ID.ID).CovBinPtr(CovStructPtr(ID.ID).NumBins).BinVal.all ;
end function GetHoleBinVal ;
------------------------------------------------------------
impure function GetHoleBinVal (ID : CoverageIDType; PercentCov : real ) return RangeArrayType is
------------------------------------------------------------
begin
return GetHoleBinVal(ID, 1, PercentCov) ;
end function GetHoleBinVal ;
------------------------------------------------------------
impure function GetHoleBinVal (ID : CoverageIDType; ReqHoleNum : integer := 1 ) return RangeArrayType is
------------------------------------------------------------
begin
return GetHoleBinVal(ID, ReqHoleNum, CovStructPtr(ID.ID).CovTarget) ;
end function GetHoleBinVal ;
-- Return Points
------------------------------------------------------------
impure function ToRandPoint(ID : CoverageIDType; BinVal : RangeArrayType ) return integer is
-- pt local
------------------------------------------------------------
variable rInt : integer ;
begin
-- return RV.RandInt(BinVal(BinVal'left).min, BinVal(BinVal'left).max) ;
RandInt(CovStructPtr(ID.ID).RV, rInt, BinVal(BinVal'left).min, BinVal(BinVal'left).max) ;
return rInt ;
end function ToRandPoint ;
------------------------------------------------------------
impure function ToRandPoint(ID : CoverageIDType; BinVal : RangeArrayType ) return integer_vector is
-- pt local
------------------------------------------------------------
variable CovPoint : integer_vector(BinVal'range) ;
variable normCovPoint : integer_vector(1 to BinVal'length) ;
begin
for i in BinVal'range loop
-- CovPoint(i) := RV.RandInt(BinVal(i).min, BinVal(i).max) ;
Uniform(CovStructPtr(ID.ID).RV, CovPoint(i), BinVal(i).min, BinVal(i).max) ;
end loop ;
normCovPoint := CovPoint ;
return normCovPoint ;
end function ToRandPoint ;
------------------------------------------------------------
impure function GetPoint (ID : CoverageIDType; BinIndex : integer ) return integer is
------------------------------------------------------------
begin
return ToRandPoint(ID, GetBinVal(ID, BinIndex)) ;
end function GetPoint ;
------------------------------------------------------------
impure function GetPoint (ID : CoverageIDType; BinIndex : integer ) return integer_vector is
------------------------------------------------------------
begin
return ToRandPoint(ID, GetBinVal(ID, BinIndex)) ;
end function GetPoint ;
------------------------------------------------------------
impure function GetRandPoint (ID : CoverageIDType) return integer is
------------------------------------------------------------
begin
return ToRandPoint(ID, GetRandBinVal(ID, CovStructPtr(ID.ID).CovTarget)) ;
end function GetRandPoint ;
------------------------------------------------------------
impure function GetRandPoint (ID : CoverageIDType; PercentCov : real ) return integer is
------------------------------------------------------------
begin
return ToRandPoint(ID, GetRandBinVal(ID, PercentCov)) ;
end function GetRandPoint ;
------------------------------------------------------------
impure function GetRandPoint (ID : CoverageIDType) return integer_vector is
------------------------------------------------------------
begin
return ToRandPoint(ID, GetRandBinVal(ID, CovStructPtr(ID.ID).CovTarget)) ;
end function GetRandPoint ;
------------------------------------------------------------
impure function GetRandPoint (ID : CoverageIDType; PercentCov : real ) return integer_vector is
------------------------------------------------------------
begin
return ToRandPoint(ID, GetRandBinVal(ID, PercentCov)) ;
end function GetRandPoint ;
------------------------------------------------------------
impure function GetIncPoint (ID : CoverageIDType) return integer is
------------------------------------------------------------
begin
return GetPoint(ID, GetIncIndex(ID)) ;
end function GetIncPoint ;
------------------------------------------------------------
impure function GetIncPoint (ID : CoverageIDType) return integer_vector is
------------------------------------------------------------
begin
return GetPoint(ID, GetIncIndex(ID)) ;
end function GetIncPoint ;
------------------------------------------------------------
impure function GetMinPoint (ID : CoverageIDType) return integer is
------------------------------------------------------------
begin
return ToRandPoint(ID, GetBinVal(ID, GetMinIndex(ID) )) ;
end function GetMinPoint ;
------------------------------------------------------------
impure function GetMinPoint (ID : CoverageIDType) return integer_vector is
------------------------------------------------------------
begin
return ToRandPoint(ID, GetBinVal(ID, GetMinIndex(ID) )) ;
end function GetMinPoint ;
------------------------------------------------------------
impure function GetMaxPoint (ID : CoverageIDType) return integer is
------------------------------------------------------------
begin
return ToRandPoint(ID, GetBinVal(ID, GetMaxIndex(ID) )) ;
end function GetMaxPoint ;
------------------------------------------------------------
impure function GetMaxPoint (ID : CoverageIDType) return integer_vector is
------------------------------------------------------------
begin
return ToRandPoint(ID, GetBinVal(ID, GetMaxIndex(ID) )) ;
end function GetMaxPoint ;
------------------------------------------------------------
impure function GetNextPoint (ID : CoverageIDType; Mode : NextPointModeType) return integer is
------------------------------------------------------------
begin
return GetPoint(ID, GetNextIndex(ID, Mode)) ;
end function GetNextPoint;
------------------------------------------------------------
impure function GetNextPoint (ID : CoverageIDType; Mode : NextPointModeType) return integer_vector is
------------------------------------------------------------
begin
return GetPoint(ID, GetNextIndex(ID, Mode)) ;
end function GetNextPoint;
------------------------------------------------------------
impure function GetNextPoint (ID : CoverageIDType) return integer is
------------------------------------------------------------
begin
return GetPoint(ID, GetNextIndex(ID, CovStructPtr(ID.ID).NextPointMode)) ;
end function GetNextPoint ;
------------------------------------------------------------
impure function GetNextPoint (ID : CoverageIDType) return integer_vector is
------------------------------------------------------------
begin
return GetPoint(ID, GetNextIndex(ID, CovStructPtr(ID.ID).NextPointMode)) ;
end function GetNextPoint ;
------------------------------------------------------------
-- deprecated, see GetRandPoint
impure function RandCovPoint (ID : CoverageIDType) return integer is
------------------------------------------------------------
begin
return ToRandPoint(ID, GetRandBinVal(ID, CovStructPtr(ID.ID).CovTarget)) ;
end function RandCovPoint ;
------------------------------------------------------------
-- deprecated, see GetRandPoint
impure function RandCovPoint (ID : CoverageIDType; PercentCov : real ) return integer is
------------------------------------------------------------
begin
return ToRandPoint(ID, GetRandBinVal(ID, PercentCov)) ;
end function RandCovPoint ;
------------------------------------------------------------
-- deprecated, see GetRandPoint
impure function RandCovPoint (ID : CoverageIDType) return integer_vector is
------------------------------------------------------------
begin
return ToRandPoint(ID, GetRandBinVal(ID, CovStructPtr(ID.ID).CovTarget)) ;
end function RandCovPoint ;
------------------------------------------------------------
-- deprecated, see GetRandPoint
impure function RandCovPoint (ID : CoverageIDType; PercentCov : real ) return integer_vector is
------------------------------------------------------------
begin
return ToRandPoint(ID, GetRandBinVal(ID, PercentCov)) ;
end function RandCovPoint ;
-- ------------------------------------------------------------
-- Intended as a stand in until we get a more general GetBin
impure function GetBinInfo (ID : CoverageIDType; BinIndex : integer ) return CovBinBaseType is
-- ------------------------------------------------------------
variable result : CovBinBaseType ;
begin
result.BinVal := ALL_RANGE;
result.Action := CovStructPtr(ID.ID).CovBinPtr(BinIndex).Action;
result.Count := CovStructPtr(ID.ID).CovBinPtr(BinIndex).Count;
result.AtLeast := CovStructPtr(ID.ID).CovBinPtr(BinIndex).AtLeast;
result.Weight := CovStructPtr(ID.ID).CovBinPtr(BinIndex).Weight;
return result ;
end function GetBinInfo ;
-- ------------------------------------------------------------
-- Intended as a stand in until we get a more general GetBin
impure function GetBinValLength (ID : CoverageIDType) return integer is
-- ------------------------------------------------------------
begin
return CovStructPtr(ID.ID).BinValLength ;
end function GetBinValLength ;
-- Eventually the multiple GetBin functions will be replaced by a
-- a single GetBin that returns CovBinBaseType with BinVal as an
-- unconstrained element
-- ------------------------------------------------------------
impure function GetBin (ID : CoverageIDType; BinIndex : integer ) return CovBinBaseType is
-- ------------------------------------------------------------
variable result : CovBinBaseType ;
begin
result.BinVal := CovStructPtr(ID.ID).CovBinPtr(BinIndex).BinVal.all;
result.Action := CovStructPtr(ID.ID).CovBinPtr(BinIndex).Action;
result.Count := CovStructPtr(ID.ID).CovBinPtr(BinIndex).Count;
result.AtLeast := CovStructPtr(ID.ID).CovBinPtr(BinIndex).AtLeast;
result.Weight := CovStructPtr(ID.ID).CovBinPtr(BinIndex).Weight;
return result ;
end function GetBin ;
-- ------------------------------------------------------------
impure function GetBin (ID : CoverageIDType; BinIndex : integer ) return CovMatrix2BaseType is
-- ------------------------------------------------------------
variable result : CovMatrix2BaseType ;
begin
result.BinVal := CovStructPtr(ID.ID).CovBinPtr(BinIndex).BinVal.all;
result.Action := CovStructPtr(ID.ID).CovBinPtr(BinIndex).Action;
result.Count := CovStructPtr(ID.ID).CovBinPtr(BinIndex).Count;
result.AtLeast := CovStructPtr(ID.ID).CovBinPtr(BinIndex).AtLeast;
result.Weight := CovStructPtr(ID.ID).CovBinPtr(BinIndex).Weight;
return result ;
end function GetBin ;
-- ------------------------------------------------------------
impure function GetBin (ID : CoverageIDType; BinIndex : integer ) return CovMatrix3BaseType is
-- ------------------------------------------------------------
variable result : CovMatrix3BaseType ;
begin
result.BinVal := CovStructPtr(ID.ID).CovBinPtr(BinIndex).BinVal.all;
result.Action := CovStructPtr(ID.ID).CovBinPtr(BinIndex).Action;
result.Count := CovStructPtr(ID.ID).CovBinPtr(BinIndex).Count;
result.AtLeast := CovStructPtr(ID.ID).CovBinPtr(BinIndex).AtLeast;
result.Weight := CovStructPtr(ID.ID).CovBinPtr(BinIndex).Weight;
return result ;
end function GetBin ;
-- ------------------------------------------------------------
impure function GetBin (ID : CoverageIDType; BinIndex : integer ) return CovMatrix4BaseType is
-- ------------------------------------------------------------
variable result : CovMatrix4BaseType ;
begin
result.BinVal := CovStructPtr(ID.ID).CovBinPtr(BinIndex).BinVal.all;
result.Action := CovStructPtr(ID.ID).CovBinPtr(BinIndex).Action;
result.Count := CovStructPtr(ID.ID).CovBinPtr(BinIndex).Count;
result.AtLeast := CovStructPtr(ID.ID).CovBinPtr(BinIndex).AtLeast;
result.Weight := CovStructPtr(ID.ID).CovBinPtr(BinIndex).Weight;
return result ;
end function GetBin ;
-- ------------------------------------------------------------
impure function GetBin (ID : CoverageIDType; BinIndex : integer ) return CovMatrix5BaseType is
-- ------------------------------------------------------------
variable result : CovMatrix5BaseType ;
begin
result.BinVal := CovStructPtr(ID.ID).CovBinPtr(BinIndex).BinVal.all;
result.Action := CovStructPtr(ID.ID).CovBinPtr(BinIndex).Action;
result.Count := CovStructPtr(ID.ID).CovBinPtr(BinIndex).Count;
result.AtLeast := CovStructPtr(ID.ID).CovBinPtr(BinIndex).AtLeast;
result.Weight := CovStructPtr(ID.ID).CovBinPtr(BinIndex).Weight;
return result ;
end function GetBin ;
-- ------------------------------------------------------------
impure function GetBin (ID : CoverageIDType; BinIndex : integer ) return CovMatrix6BaseType is
-- ------------------------------------------------------------
variable result : CovMatrix6BaseType ;
begin
result.BinVal := CovStructPtr(ID.ID).CovBinPtr(BinIndex).BinVal.all;
result.Action := CovStructPtr(ID.ID).CovBinPtr(BinIndex).Action;
result.Count := CovStructPtr(ID.ID).CovBinPtr(BinIndex).Count;
result.AtLeast := CovStructPtr(ID.ID).CovBinPtr(BinIndex).AtLeast;
result.Weight := CovStructPtr(ID.ID).CovBinPtr(BinIndex).Weight;
return result ;
end function GetBin ;
-- ------------------------------------------------------------
impure function GetBin (ID : CoverageIDType; BinIndex : integer ) return CovMatrix7BaseType is
-- ------------------------------------------------------------
variable result : CovMatrix7BaseType ;
begin
result.BinVal := CovStructPtr(ID.ID).CovBinPtr(BinIndex).BinVal.all;
result.Action := CovStructPtr(ID.ID).CovBinPtr(BinIndex).Action;
result.Count := CovStructPtr(ID.ID).CovBinPtr(BinIndex).Count;
result.AtLeast := CovStructPtr(ID.ID).CovBinPtr(BinIndex).AtLeast;
result.Weight := CovStructPtr(ID.ID).CovBinPtr(BinIndex).Weight;
return result ;
end function GetBin ;
-- ------------------------------------------------------------
impure function GetBin (ID : CoverageIDType; BinIndex : integer ) return CovMatrix8BaseType is
-- ------------------------------------------------------------
variable result : CovMatrix8BaseType ;
begin
result.BinVal := CovStructPtr(ID.ID).CovBinPtr(BinIndex).BinVal.all;
result.Action := CovStructPtr(ID.ID).CovBinPtr(BinIndex).Action;
result.Count := CovStructPtr(ID.ID).CovBinPtr(BinIndex).Count;
result.AtLeast := CovStructPtr(ID.ID).CovBinPtr(BinIndex).AtLeast;
result.Weight := CovStructPtr(ID.ID).CovBinPtr(BinIndex).Weight;
return result ;
end function GetBin ;
-- ------------------------------------------------------------
impure function GetBin (ID : CoverageIDType; BinIndex : integer ) return CovMatrix9BaseType is
-- ------------------------------------------------------------
variable result : CovMatrix9BaseType ;
begin
result.BinVal := CovStructPtr(ID.ID).CovBinPtr(BinIndex).BinVal.all;
result.Action := CovStructPtr(ID.ID).CovBinPtr(BinIndex).Action;
result.Count := CovStructPtr(ID.ID).CovBinPtr(BinIndex).Count;
result.AtLeast := CovStructPtr(ID.ID).CovBinPtr(BinIndex).AtLeast;
result.Weight := CovStructPtr(ID.ID).CovBinPtr(BinIndex).Weight;
return result ;
end function GetBin ;
-- ------------------------------------------------------------
impure function GetBinName (ID : CoverageIDType; BinIndex : integer; DefaultName : string := "" ) return string is
-- ------------------------------------------------------------
begin
if CovStructPtr(ID.ID).CovBinPtr(BinIndex).Name.all /= "" then
return CovStructPtr(ID.ID).CovBinPtr(BinIndex).Name.all ;
else
return DefaultName ;
end if;
end function GetBinName;
------------------------------------------------------------
-- pt local for now -- file formal parameter not allowed with a public method
-- procedure WriteBinName (ID : CoverageIDType; file f : text ; S : string ; Prefix : string := "%% " ) is
procedure WriteBinName (ID : CoverageIDType; variable buf : inout line; S : string ; Prefix : string := "%% " ) is
------------------------------------------------------------
variable Message : MessageStructPtrType ;
variable MessageIndex : integer := 1 ;
-- variable buf : line ;
begin
Message := CovStructPtr(ID.ID).CovMessage ;
if Message = NULL then
write(buf, Prefix & S & GetCovModelName(ID)) ; -- Print name when no message
write(buf, "" & LF) ;
-- writeline(f, buf) ;
else
if CovStructPtr(ID.ID).CovName /= NULL then
-- Print Name if set
write(buf, Prefix & S & CovStructPtr(ID.ID).CovName.all) ;
elsif CovStructPtr(ID.ID).AlertLogID /= OSVVM_COVERAGE_ALERTLOG_ID then
-- otherwise Print AlertLogName if it is set
write(buf, Prefix & S & string'(GetAlertLogName(CovStructPtr(ID.ID).AlertLogID)) ) ;
else
-- otherwise print the first line of the message
write(buf, Prefix & S & Message.Name.all) ;
Message := Message.NextPtr ;
end if ;
write(buf, "" & LF) ;
-- writeline(f, buf) ;
WriteMessage(buf, Message, Prefix) ;
end if ;
end procedure WriteBinName ;
------------------------------------------------------------
-- pt local for now -- file formal parameter not allowed with method
procedure WriteBin (
ID : CoverageIDType ;
variable buf : inout line ;
-- file f : text ;
WritePassFail : OsvvmOptionsType ;
WriteBinInfo : OsvvmOptionsType ;
WriteCount : OsvvmOptionsType ;
WriteAnyIllegal : OsvvmOptionsType ;
WritePrefix : string ;
PassName : string ;
FailName : string ;
UsingLocalFile : boolean := FALSE
) is
------------------------------------------------------------
begin
if CovStructPtr(ID.ID).NumBins < 1 then
if WriteBinFileInit or UsingLocalFile then
swrite(buf, WritePrefix & " " & FailName & " ") ;
swrite(buf, GetNamePlus(ID, prefix => "in ", suffix => ", ") & "CoveragePkg.WriteBin: Coverage model is empty. Nothing to print.") ;
-- writeline(f, buf) ;
end if ;
Alert(CovStructPtr(ID.ID).AlertLogID, GetNamePlus(ID, prefix => "in ", suffix => ", ") & "CoveragePkg.WriteBin:" &
" Coverage model is empty. Nothing to print.", FAILURE) ;
return ;
end if ;
-- Models with Bins
WriteBinName(ID, buf, "WriteBin: ", WritePrefix) ;
for i in 1 to CovStructPtr(ID.ID).NumBins loop -- CovStructPtr(ID.ID).CovBinPtr.all'range
if CovStructPtr(ID.ID).CovBinPtr(i).action = COV_COUNT or
(CovStructPtr(ID.ID).CovBinPtr(i).action = COV_ILLEGAL and IsEnabled(WriteAnyIllegal)) or
CovStructPtr(ID.ID).CovBinPtr(i).count < 0 -- Illegal bin with errors
then
-- WriteBin Info
swrite(buf, WritePrefix) ;
if CovStructPtr(ID.ID).CovBinPtr(i).Name.all /= "" then
swrite(buf, CovStructPtr(ID.ID).CovBinPtr(i).Name.all & " ") ;
end if ;
if IsEnabled(WritePassFail) then
-- For illegal bins, AtLeast = 0 and count is negative.
if CovStructPtr(ID.ID).CovBinPtr(i).count >= CovStructPtr(ID.ID).CovBinPtr(i).AtLeast then
swrite(buf, PassName & ' ') ;
else
swrite(buf, FailName & ' ') ;
end if ;
end if ;
if IsEnabled(WriteBinInfo) then
if CovStructPtr(ID.ID).CovBinPtr(i).action = COV_COUNT then
swrite(buf, "Bin:") ;
else
swrite(buf, "Illegal Bin:") ;
end if;
write(buf, CovStructPtr(ID.ID).CovBinPtr(i).BinVal.all) ;
end if ;
if IsEnabled(WriteCount) then
write(buf, " Count = " & integer'image(abs(CovStructPtr(ID.ID).CovBinPtr(i).count))) ;
write(buf, " AtLeast = " & integer'image(CovStructPtr(ID.ID).CovBinPtr(i).AtLeast)) ;
if CovStructPtr(ID.ID).WeightMode = WEIGHT or CovStructPtr(ID.ID).WeightMode = REMAIN_WEIGHT then
-- Print Weight only when it is used
write(buf, " Weight = " & integer'image(CovStructPtr(ID.ID).CovBinPtr(i).Weight)) ;
end if ;
end if ;
write(buf, "" & LF) ;
-- writeline(f, buf) ;
end if ;
end loop ;
swrite(buf, "") ;
-- writeline(f, buf) ;
end procedure WriteBin ;
------------------------------------------------------------
procedure WriteBin (ID : CoverageIDType) is
------------------------------------------------------------
constant rWritePassFail : OsvvmOptionsType := ResolveCovWritePassFail (WritePassFailVar) ;
constant rWriteBinInfo : OsvvmOptionsType := ResolveCovWriteBinInfo (WriteBinInfoVar ) ;
constant rWriteCount : OsvvmOptionsType := ResolveCovWriteCount (WriteCountVar ) ;
constant rWriteAnyIllegal : OsvvmOptionsType := ResolveCovWriteAnyIllegal(WriteAnyIllegalVar) ;
-- constant rWritePrefix : string := ResolveOsvvmWritePrefix (WritePrefixVar.GetOpt) ;
-- constant rPassName : string := ResolveOsvvmPassName (PassNameVar.GetOpt ) ;
-- constant rFailName : string := ResolveOsvvmFailName (FailNameVar.GetOpt ) ;
variable buf : line ;
begin
WriteBin (
ID => ID,
buf => buf,
WritePassFail => rWritePassFail,
WriteBinInfo => rWriteBinInfo,
WriteCount => rWriteCount,
WriteAnyIllegal => rWriteAnyIllegal,
-- WritePrefix => rWritePrefix,
WritePrefix => ResolveOsvvmWritePrefix (WritePrefixVar.GetOpt),
-- PassName => rPassName,
PassName => ResolveOsvvmPassName (PassNameVar.GetOpt ),
-- FailName => rFailName
FailName => ResolveOsvvmFailName (FailNameVar.GetOpt )
) ;
WriteToCovFile(buf) ;
end procedure WriteBin ;
------------------------------------------------------------
procedure WriteBin (ID : CoverageIDType; LogLevel : LogType ) is
------------------------------------------------------------
begin
if IsLogEnabled(CovStructPtr(ID.ID).AlertLogID, LogLevel) then
WriteBin (
ID => ID
) ;
end if ;
end procedure WriteBin ; -- With LogLevel
------------------------------------------------------------
procedure WriteBin (ID : CoverageIDType; FileName : string; OpenKind : File_Open_Kind := APPEND_MODE) is
------------------------------------------------------------
constant rWritePassFail : OsvvmOptionsType := ResolveCovWritePassFail (WritePassFailVar) ;
constant rWriteBinInfo : OsvvmOptionsType := ResolveCovWriteBinInfo (WriteBinInfoVar ) ;
constant rWriteCount : OsvvmOptionsType := ResolveCovWriteCount (WriteCountVar ) ;
constant rWriteAnyIllegal : OsvvmOptionsType := ResolveCovWriteAnyIllegal (WriteAnyIllegalVar) ;
-- constant rWritePrefix : string := ResolveOsvvmWritePrefix (WritePrefixVar.GetOpt) ;
-- constant rPassName : string := ResolveOsvvmPassName (PassNameVar.GetOpt ) ;
-- constant rFailName : string := ResolveOsvvmFailName (FailNameVar.GetOpt ) ;
file LocalWriteBinFile : text open OpenKind is FileName ;
variable buf : line ;
begin
WriteBin (
ID => ID,
buf => buf,
WritePassFail => rWritePassFail,
WriteBinInfo => rWriteBinInfo,
WriteCount => rWriteCount,
WriteAnyIllegal => rWriteAnyIllegal,
-- WritePrefix => rWritePrefix,
WritePrefix => ResolveOsvvmWritePrefix (WritePrefixVar.GetOpt),
-- PassName => rPassName,
PassName => ResolveOsvvmPassName (PassNameVar.GetOpt ),
-- FailName => rFailName
FailName => ResolveOsvvmFailName (FailNameVar.GetOpt ),
UsingLocalFile => TRUE
);
writeline(LocalWriteBinFile, buf) ;
end procedure WriteBin ;
------------------------------------------------------------
procedure WriteBin ( -- With LogLevel
------------------------------------------------------------
ID : CoverageIDType ;
LogLevel : LogType ;
FileName : string ;
OpenKind : File_Open_Kind := APPEND_MODE
) is
begin
if IsLogEnabled(CovStructPtr(ID.ID).AlertLogID, LogLevel) then
WriteBin (
ID => ID,
FileName => FileName,
OpenKind => OpenKind
) ;
end if ;
end procedure WriteBin ; -- With LogLevel
------------------------------------------------------------
-- Development only
-- pt local for now -- file formal parameter not allowed with method
-- procedure DumpBin (ID : CoverageIDType; file f : text ) is
procedure DumpBin (ID : CoverageIDType; variable buf : inout line ) is
------------------------------------------------------------
-- variable buf : line ;
begin
WriteBinName(ID, buf, "DumpBin: ") ;
-- writeline(f, buf) ;
-- if CovStructPtr(ID.ID).NumBins < 1 then
-- Write(f, "%%FATAL, Coverage Model is empty. Nothing to print." & LF ) ;
-- end if ;
for i in 1 to CovStructPtr(ID.ID).NumBins loop -- CovStructPtr(ID.ID).CovBinPtr.all'range
swrite(buf, "%% ") ;
if CovStructPtr(ID.ID).CovBinPtr(i).Name.all /= "" then
swrite(buf, CovStructPtr(ID.ID).CovBinPtr(i).Name.all & " ") ;
end if ;
swrite(buf, "Bin:") ;
write(buf, CovStructPtr(ID.ID).CovBinPtr(i).BinVal.all) ;
case CovStructPtr(ID.ID).CovBinPtr(i).action is
when COV_COUNT => swrite(buf, " Count = ") ;
when COV_IGNORE => swrite(buf, " Ignore = ") ;
when COV_ILLEGAL => swrite(buf, " Illegal = ") ;
when others => swrite(buf, " BOGUS BOGUS BOGUS = ") ;
end case ;
write(buf, CovStructPtr(ID.ID).CovBinPtr(i).count) ;
write(buf, " AtLeast = " & integer'image(CovStructPtr(ID.ID).CovBinPtr(i).AtLeast)) ;
write(buf, " Weight = " & integer'image(CovStructPtr(ID.ID).CovBinPtr(i).Weight)) ;
write(buf, "" & LF) ;
-- writeline(f, buf) ;
end loop ;
swrite(buf, "") ;
-- writeline(f,buf) ;
end procedure DumpBin ;
------------------------------------------------------------
procedure DumpBin (ID : CoverageIDType; LogLevel : LogType := DEBUG) is
------------------------------------------------------------
variable buf : line ;
begin
if IsLogEnabled(CovStructPtr(ID.ID).AlertLogID, LogLevel) then
DumpBin(ID, buf) ;
WriteToCovFile(buf) ;
end if ;
end procedure DumpBin ;
------------------------------------------------------------
-- pt local
-- procedure WriteCovHoles (ID : CoverageIDType; file f : text; PercentCov : real := 100.0; UsingLocalFile : boolean := FALSE) is
procedure WriteCovHoles (ID : CoverageIDType; variable buf : inout line; PercentCov : real := 100.0; UsingLocalFile : boolean := FALSE) is
------------------------------------------------------------
-- variable buf : line ;
begin
if CovStructPtr(ID.ID).NumBins < 1 then
if WriteBinFileInit or UsingLocalFile then
-- Duplicate Alert in specified file
swrite(buf, "%% Alert FAILURE " & GetNamePlus(ID, prefix => "in ", suffix => ", ") & "CoveragePkg.WriteCovHoles:" &
" coverage model empty. Nothing to print.") ;
-- writeline(f, buf) ;
end if ;
Alert(CovStructPtr(ID.ID).AlertLogID, GetNamePlus(ID, prefix => "in ", suffix => ", ") & "CoveragePkg.WriteCovHoles:" &
" coverage model empty. Nothing to print.", FAILURE) ;
return ;
end if ;
-- Models with Bins
WriteBinName(ID, buf, "WriteCovHoles: ") ;
-- writeline(f, buf) ;
CovLoop : for i in 1 to CovStructPtr(ID.ID).NumBins loop
if CovStructPtr(ID.ID).CovBinPtr(i).action = COV_COUNT and CovStructPtr(ID.ID).CovBinPtr(i).PercentCov < PercentCov then
swrite(buf, "%% ") ;
if CovStructPtr(ID.ID).CovBinPtr(i).Name.all /= "" then
swrite(buf, CovStructPtr(ID.ID).CovBinPtr(i).Name.all & " ") ;
end if ;
swrite(buf, "Bin:") ;
write(buf, CovStructPtr(ID.ID).CovBinPtr(i).BinVal.all) ;
write(buf, " Count = " & integer'image(CovStructPtr(ID.ID).CovBinPtr(i).Count)) ;
write(buf, " AtLeast = " & integer'image(CovStructPtr(ID.ID).CovBinPtr(i).AtLeast)) ;
if CovStructPtr(ID.ID).WeightMode = WEIGHT or CovStructPtr(ID.ID).WeightMode = REMAIN_WEIGHT then
-- Print Weight only when it is used
write(buf, " Weight = " & integer'image(CovStructPtr(ID.ID).CovBinPtr(i).Weight)) ;
end if ;
write(buf, "" & LF) ;
-- writeline(f, buf) ;
end if ;
end loop CovLoop ;
swrite(buf, "") ;
-- writeline(f, buf) ;
end procedure WriteCovHoles ;
------------------------------------------------------------
procedure WriteCovHoles (ID : CoverageIDType; PercentCov : real ) is
------------------------------------------------------------
variable buf : line ;
begin
WriteCovHoles(ID, buf, PercentCov) ;
WriteToCovFile(buf) ;
end procedure WriteCovHoles ;
------------------------------------------------------------
procedure WriteCovHoles (ID : CoverageIDType; LogLevel : LogType := ALWAYS ) is
------------------------------------------------------------
begin
if IsLogEnabled(CovStructPtr(ID.ID).AlertLogID, LogLevel) then
WriteCovHoles(ID, CovStructPtr(ID.ID).CovTarget) ;
end if;
end procedure WriteCovHoles ;
------------------------------------------------------------
procedure WriteCovHoles (ID : CoverageIDType; LogLevel : LogType ; PercentCov : real ) is
------------------------------------------------------------
begin
if IsLogEnabled(CovStructPtr(ID.ID).AlertLogID, LogLevel) then
WriteCovHoles(ID, PercentCov) ;
end if;
end procedure WriteCovHoles ;
------------------------------------------------------------
procedure WriteCovHoles (ID : CoverageIDType; FileName : string; OpenKind : File_Open_Kind := APPEND_MODE ) is
------------------------------------------------------------
file CovHoleFile : text open OpenKind is FileName ;
variable buf : line ;
begin
-- WriteCovHoles(ID, CovHoleFile, CovStructPtr(ID.ID).CovTarget, TRUE) ;
WriteCovHoles(ID, buf, CovStructPtr(ID.ID).CovTarget, TRUE) ;
writeline(CovHoleFile, buf) ;
end procedure WriteCovHoles ;
------------------------------------------------------------
procedure WriteCovHoles (ID : CoverageIDType; LogLevel : LogType ; FileName : string; OpenKind : File_Open_Kind := APPEND_MODE ) is
------------------------------------------------------------
begin
if IsLogEnabled(CovStructPtr(ID.ID).AlertLogID, LogLevel) then
WriteCovHoles(ID, FileName, OpenKind) ;
end if;
end procedure WriteCovHoles ;
------------------------------------------------------------
procedure WriteCovHoles (ID : CoverageIDType; FileName : string; PercentCov : real ; OpenKind : File_Open_Kind := APPEND_MODE ) is
------------------------------------------------------------
file CovHoleFile : text open OpenKind is FileName ;
variable buf : line ;
begin
-- WriteCovHoles(ID, CovHoleFile, PercentCov, TRUE) ;
WriteCovHoles(ID, buf, PercentCov, TRUE) ;
writeline(CovHoleFile, buf) ;
end procedure WriteCovHoles ;
------------------------------------------------------------
procedure WriteCovHoles (ID : CoverageIDType; LogLevel : LogType ; FileName : string; PercentCov : real ; OpenKind : File_Open_Kind := APPEND_MODE ) is
------------------------------------------------------------
begin
if IsLogEnabled(CovStructPtr(ID.ID).AlertLogID, LogLevel) then
WriteCovHoles(ID, FileName, PercentCov, OpenKind) ;
end if;
end procedure WriteCovHoles ;
------------------------------------------------------------
-- pt local
impure function FindExactBin (
-- find an exact match to a bin wrt BinVal, Action, AtLeast, Weight, and Name
------------------------------------------------------------
ID : CoverageIDType ;
Merge : boolean ;
BinVal : RangeArrayType ;
Action : integer ;
AtLeast : integer ;
Weight : integer ;
Name : string
) return integer is
begin
if Merge then
for i in 1 to CovStructPtr(ID.ID).NumBins loop
if (BinVal = CovStructPtr(ID.ID).CovBinPtr(i).BinVal.all) and (Action = CovStructPtr(ID.ID).CovBinPtr(i).Action) and
(AtLeast = CovStructPtr(ID.ID).CovBinPtr(i).AtLeast) and (Weight = CovStructPtr(ID.ID).CovBinPtr(i).Weight) and
(Name = CovStructPtr(ID.ID).CovBinPtr(i).Name.all) then
return i ;
end if;
end loop ;
end if ;
return 0 ;
end function FindExactBin ;
------------------------------------------------------------
-- pt local
procedure read (
------------------------------------------------------------
buf : inout line ;
NamePtr : inout line ;
NameLength : in integer ;
ReadValid : out boolean
) is
variable Name : string(1 to NameLength) ;
begin
if NameLength > 0 then
read(buf, Name, ReadValid) ;
NamePtr := new string'(Name) ;
else
ReadValid := TRUE ;
NamePtr := new string'("") ;
end if ;
end procedure read ;
------------------------------------------------------------
-- pt local
procedure ReadCovVars (ID : CoverageIDType; file CovDbFile : text; Good : out boolean ) is
------------------------------------------------------------
variable buf : line ;
variable Empty : boolean ;
variable MultiLineComment : boolean := FALSE ;
variable ReadValid : boolean ;
variable GoodLoop1 : boolean ;
variable iSeed : RandomSeedType ;
variable iIllegalMode : integer ;
variable iWeightMode : integer ;
variable iWeightScale : real ;
variable iCovThreshold : real ;
variable iCountMode : integer ;
variable iNumberOfMessages : integer ;
variable iThresholdingEnable : boolean ;
variable iCovTarget : real ;
variable iMergingEnable : boolean ;
begin
-- ReadLoop0 : while not EndFile(CovDbFile) loop
ReadLoop0 : loop -- allows emulation of "return when"
-- ReadLine to Get Coverage Model Name, skip blank and comment lines, fails when file empty
exit when AlertIf(CovStructPtr(ID.ID).AlertLogID, EndFile(CovDbFile), GetNamePlus(ID, prefix => "in ", suffix => ", ") &
"CoveragePkg.ReadCovDb: No Coverage Data to read", FAILURE) ;
ReadLine(CovDbFile, buf) ;
EmptyOrCommentLine(buf, Empty, MultiLineComment) ;
next when Empty ;
if buf.all /= "Coverage_Model_Not_Named" then
SetName(ID, buf.all) ;
end if ;
exit ReadLoop0 ;
end loop ReadLoop0 ;
-- ReadLoop1 : while not EndFile(CovDbFile) loop
ReadLoop1 : loop
-- ReadLine to Get Variables, skip blank and comment lines, fails when file empty
exit when AlertIf(CovStructPtr(ID.ID).AlertLogID, EndFile(CovDbFile), GetNamePlus(ID, prefix => "in ", suffix => ", ") &
"CoveragePkg.ReadCovDb: Coverage DB File Incomplete", FAILURE) ;
ReadLine(CovDbFile, buf) ;
EmptyOrCommentLine(buf, Empty, MultiLineComment) ;
next when Empty ;
read(buf, iSeed, ReadValid) ;
exit when AlertIfNot(CovStructPtr(ID.ID).AlertLogID, ReadValid, GetNamePlus(ID, prefix => "in ", suffix => ", ") &
"CoveragePkg.ReadCovDb: Failed while reading Seed", FAILURE) ;
-- RV.SetSeed( iSeed ) ;
CovStructPtr(ID.ID).RV := iSeed ;
CovStructPtr(ID.ID).RvSeedInit := TRUE ;
read(buf, iCovThreshold, ReadValid) ;
exit when AlertIfNot(CovStructPtr(ID.ID).AlertLogID, ReadValid, GetNamePlus(ID, prefix => "in ", suffix => ", ") &
"CoveragePkg.ReadCovDb: Failed while reading CovThreshold", FAILURE) ;
CovStructPtr(ID.ID).CovThreshold := iCovThreshold ;
read(buf, iIllegalMode, ReadValid) ;
exit when AlertIfNot(CovStructPtr(ID.ID).AlertLogID, ReadValid, GetNamePlus(ID, prefix => "in ", suffix => ", ") &
"CoveragePkg.ReadCovDb: Failed while reading IllegalMode", FAILURE) ;
SetIllegalMode(ID, IllegalModeType'val( iIllegalMode )) ;
read(buf, iWeightMode, ReadValid) ;
exit when AlertIfNot(CovStructPtr(ID.ID).AlertLogID, ReadValid, GetNamePlus(ID, prefix => "in ", suffix => ", ") &
"CoveragePkg.ReadCovDb: Failed while reading WeightMode", FAILURE) ;
CovStructPtr(ID.ID).WeightMode := WeightModeType'val( iWeightMode ) ;
read(buf, iWeightScale, ReadValid) ;
exit when AlertIfNot(CovStructPtr(ID.ID).AlertLogID, ReadValid, GetNamePlus(ID, prefix => "in ", suffix => ", ") &
"CoveragePkg.ReadCovDb: Failed while reading WeightScale", FAILURE) ;
CovStructPtr(ID.ID).WeightScale := iWeightScale ;
read(buf, iCountMode, ReadValid) ;
exit when AlertIfNot(CovStructPtr(ID.ID).AlertLogID, ReadValid, GetNamePlus(ID, prefix => "in ", suffix => ", ") &
"CoveragePkg.ReadCovDb: Failed while reading CountMode", FAILURE) ;
CovStructPtr(ID.ID).CountMode := CountModeType'val( iCountMode ) ;
read(buf, iThresholdingEnable, ReadValid) ;
exit when AlertIfNot(CovStructPtr(ID.ID).AlertLogID, ReadValid, GetNamePlus(ID, prefix => "in ", suffix => ", ") &
"CoveragePkg.ReadCovDb: Failed while reading ThresholdingEnable", FAILURE) ;
CovStructPtr(ID.ID).ThresholdingEnable := iThresholdingEnable ;
read(buf, iCovTarget, ReadValid) ;
exit when AlertIfNot(CovStructPtr(ID.ID).AlertLogID, ReadValid, GetNamePlus(ID, prefix => "in ", suffix => ", ") &
"CoveragePkg.ReadCovDb: Failed while reading CovTarget", FAILURE) ;
CovStructPtr(ID.ID).CovTarget := iCovTarget ;
read(buf, iMergingEnable, ReadValid) ;
exit when AlertIfNot(CovStructPtr(ID.ID).AlertLogID, ReadValid, GetNamePlus(ID, prefix => "in ", suffix => ", ") &
"CoveragePkg.ReadCovDb: Failed while reading MergingEnable", FAILURE) ;
CovStructPtr(ID.ID).MergingEnable := iMergingEnable ;
exit ReadLoop1 ;
end loop ReadLoop1 ;
GoodLoop1 := ReadValid ;
-- ReadLoop2 : while not EndFile(CovDbFile) loop
ReadLoop2 : while ReadValid loop
-- ReadLine to Coverage Model Header WriteBin Message, skip blank and comment lines, fails when file empty
exit when AlertIf(CovStructPtr(ID.ID).AlertLogID, EndFile(CovDbFile), GetNamePlus(ID, prefix => "in ", suffix => ", ") &
"CoveragePkg.ReadCovDb: Coverage DB File Incomplete", FAILURE) ;
ReadLine(CovDbFile, buf) ;
EmptyOrCommentLine(buf, Empty, MultiLineComment) ;
next when Empty ;
read(buf, iNumberOfMessages, ReadValid) ;
exit when AlertIfNot(CovStructPtr(ID.ID).AlertLogID, ReadValid, GetNamePlus(ID, prefix => "in ", suffix => ", ") &
"CoveragePkg.ReadCovDb: Failed while reading NumberOfMessages", FAILURE) ;
for i in 1 to iNumberOfMessages loop
exit when AlertIf(CovStructPtr(ID.ID).AlertLogID, EndFile(CovDbFile), GetNamePlus(ID, prefix => "in ", suffix => ", ") &
"CoveragePkg.ReadCovDb: End of File while reading Messages", FAILURE) ;
ReadLine(CovDbFile, buf) ;
SetMessage(ID, buf.all) ;
end loop ;
exit ReadLoop2 ;
end loop ReadLoop2 ;
Good := ReadValid and GoodLoop1 ;
end procedure ReadCovVars ;
------------------------------------------------------------
-- pt local
procedure ReadCovDbInfo (
------------------------------------------------------------
ID : CoverageIDType ;
File CovDbFile : text ;
variable NumRangeItems : out integer ;
variable NumLines : out integer ;
variable Good : out boolean
) is
variable buf : line ;
variable ReadValid : boolean ;
variable Empty : boolean ;
variable MultiLineComment : boolean := FALSE ;
begin
ReadLoop : loop
-- ReadLine to RangeItems NumLines, skip blank and comment lines, fails when file empty
exit when AlertIf(CovStructPtr(ID.ID).AlertLogID, EndFile(CovDbFile), GetNamePlus(ID, prefix => "in ", suffix => ", ") &
"CoveragePkg.ReadCovDb: Coverage DB File Incomplete", FAILURE) ;
ReadLine(CovDbFile, buf) ;
EmptyOrCommentLine(buf, Empty, MultiLineComment) ;
next when Empty ;
read(buf, NumRangeItems, ReadValid) ;
exit when AlertIfNot(CovStructPtr(ID.ID).AlertLogID, ReadValid, GetNamePlus(ID, prefix => "in ", suffix => ", ") &
"CoveragePkg.ReadCovDb: Failed while reading NumRangeItems", FAILURE) ;
read(buf, NumLines, ReadValid) ;
exit when AlertIfNot(CovStructPtr(ID.ID).AlertLogID, ReadValid, GetNamePlus(ID, prefix => "in ", suffix => ", ") &
"CoveragePkg.ReadCovDb: Failed while reading NumLines", FAILURE) ;
exit ;
end loop ReadLoop ;
Good := ReadValid ;
end procedure ReadCovDbInfo ;
------------------------------------------------------------
-- pt local
procedure ReadCovDbDataBase (
------------------------------------------------------------
ID : CoverageIDType ;
File CovDbFile : text ;
constant NumRangeItems : in integer ;
constant NumLines : in integer ;
constant Merge : in boolean ;
variable Good : out boolean
) is
variable buf : line ;
variable Empty : boolean ;
variable MultiLineComment : boolean := FALSE ;
variable ReadValid : boolean ;
-- Format: Action Count min1 max1 min2 max2 ....
variable Action : integer ;
variable Count : integer ;
variable BinVal : RangeArrayType(1 to NumRangeItems) ;
variable index : integer ;
variable AtLeast : integer ;
variable Weight : integer ;
variable PercentCov : real ;
variable NameLength : integer ;
variable SkipBlank : character ;
variable NamePtr : line ;
begin
GrowBins(ID, NumLines) ;
ReadLoop : for i in 1 to NumLines loop
GetValidLineLoop: loop
exit ReadLoop when AlertIf(CovStructPtr(ID.ID).AlertLogID, EndFile(CovDbFile), GetNamePlus(ID, prefix => "in ", suffix => ", ") &
"CoveragePkg.ReadCovDb: Did not read specified number of lines", FAILURE) ;
ReadLine(CovDbFile, buf) ;
EmptyOrCommentLine(buf, Empty, MultiLineComment) ;
next GetValidLineLoop when Empty ; -- replace with EmptyLine(buf)
exit GetValidLineLoop ;
end loop ;
read(buf, Action, ReadValid) ;
exit ReadLoop when AlertIfNot(CovStructPtr(ID.ID).AlertLogID, ReadValid, GetNamePlus(ID, prefix => "in ", suffix => ", ") &
"CoveragePkg.ReadCovDb: Failed while reading Action", FAILURE) ;
read(buf, Count, ReadValid) ;
exit ReadLoop when AlertIfNot(CovStructPtr(ID.ID).AlertLogID, ReadValid, GetNamePlus(ID, prefix => "in ", suffix => ", ") &
"CoveragePkg.ReadCovDb: Failed while reading Count", FAILURE) ;
read(buf, AtLeast, ReadValid) ;
exit ReadLoop when AlertIfNot(CovStructPtr(ID.ID).AlertLogID, ReadValid, GetNamePlus(ID, prefix => "in ", suffix => ", ") &
"CoveragePkg.ReadCovDb: Failed while reading AtLeast", FAILURE) ;
read(buf, Weight, ReadValid) ;
exit ReadLoop when AlertIfNot(CovStructPtr(ID.ID).AlertLogID, ReadValid, GetNamePlus(ID, prefix => "in ", suffix => ", ") &
"CoveragePkg.ReadCovDb: Failed while reading Weight", FAILURE) ;
read(buf, PercentCov, ReadValid) ;
exit ReadLoop when AlertIfNot(CovStructPtr(ID.ID).AlertLogID, ReadValid, GetNamePlus(ID, prefix => "in ", suffix => ", ") &
"CoveragePkg.ReadCovDb: Failed while reading PercentCov", FAILURE) ;
read(buf, BinVal, ReadValid) ;
exit ReadLoop when AlertIfNot(CovStructPtr(ID.ID).AlertLogID, ReadValid, GetNamePlus(ID, prefix => "in ", suffix => ", ") &
"CoveragePkg.ReadCovDb: Failed while reading BinVal", FAILURE) ;
read(buf, NameLength, ReadValid) ;
exit ReadLoop when AlertIfNot(CovStructPtr(ID.ID).AlertLogID, ReadValid, GetNamePlus(ID, prefix => "in ", suffix => ", ") &
"CoveragePkg.ReadCovDb: Failed while reading Bin Name Length", FAILURE) ;
read(buf, SkipBlank, ReadValid) ;
exit ReadLoop when AlertIfNot(CovStructPtr(ID.ID).AlertLogID, ReadValid, GetNamePlus(ID, prefix => "in ", suffix => ", ") &
"CoveragePkg.ReadCovDb: Failed while reading Bin Name Length", FAILURE) ;
read(buf, NamePtr, NameLength, ReadValid) ;
exit ReadLoop when AlertIfNot(CovStructPtr(ID.ID).AlertLogID, ReadValid, GetNamePlus(ID, prefix => "in ", suffix => ", ") &
"CoveragePkg.ReadCovDb: Failed while reading Bin Name", FAILURE) ;
index := FindExactBin(ID, Merge, BinVal, Action, AtLeast, Weight, NamePtr.all) ;
if index > 0 then
-- Bin is an exact match so only merge the count values
CovStructPtr(ID.ID).CovBinPtr(index).Count := CovStructPtr(ID.ID).CovBinPtr(index).Count + Count ;
CovStructPtr(ID.ID).CovBinPtr(index).PercentCov := CalcPercentCov(
Count => CovStructPtr(ID.ID).CovBinPtr.all(index).Count,
AtLeast => CovStructPtr(ID.ID).CovBinPtr.all(index).AtLeast ) ;
else
InsertNewBin(ID, BinVal, Action, Count, AtLeast, Weight, NamePtr.all, PercentCov) ;
end if ;
deallocate(NamePtr) ;
end loop ReadLoop ;
Good := ReadValid ;
end ReadCovDbDataBase ;
------------------------------------------------------------
-- pt local
procedure ReadCovDb (ID : CoverageIDType; File CovDbFile : text; Merge : boolean := FALSE) is
------------------------------------------------------------
-- Format: Action Count min1 max1 min2 max2
-- file CovDbFile : text open READ_MODE is FileName ;
variable NumRangeItems : integer ;
variable NumLines : integer ;
variable ReadValid : boolean ;
begin
if not Merge then
Deallocate(ID) ; -- remove any old bins
end if ;
ReadLoop : loop
-- Read coverage private variables to the file
ReadCovVars(ID, CovDbFile, ReadValid) ;
exit when not ReadValid ;
-- Get Coverage dimensions and number of items in file.
ReadCovDbInfo(ID, CovDbFile, NumRangeItems, NumLines, ReadValid) ;
exit when not ReadValid ;
-- Read the file
ReadCovDbDataBase(ID, CovDbFile, NumRangeItems, NumLines, Merge, ReadValid) ;
exit ;
end loop ReadLoop ;
end ReadCovDb ;
------------------------------------------------------------
procedure ReadCovDb (ID : CoverageIDType; FileName : string; Merge : boolean := FALSE) is
------------------------------------------------------------
-- Format: Action Count min1 max1 min2 max2
file CovDbFile : text open READ_MODE is FileName ;
begin
ReadCovDb(ID, CovDbFile, Merge) ;
end procedure ReadCovDb ;
------------------------------------------------------------
-- pt local
procedure WriteCovDbVars (ID : CoverageIDType; file CovDbFile : text ) is
------------------------------------------------------------
variable buf : line ;
variable CovMessageCount : integer ;
begin
-- write coverage private variables to the file
if CovStructPtr(ID.ID).CovName /= NULL then
swrite(buf, CovStructPtr(ID.ID).CovName.all) ;
else
swrite(buf, "Coverage_Model_Not_Named") ;
end if ;
writeline(CovDbFile, buf) ;
write(buf, CovStructPtr(ID.ID).RV ) ;
write(buf, ' ') ;
write(buf, CovStructPtr(ID.ID).CovThreshold, RIGHT, 0, 5) ;
write(buf, ' ') ;
write(buf, IllegalModeType'pos(CovStructPtr(ID.ID).IllegalMode)) ;
write(buf, ' ') ;
write(buf, WeightModeType'pos(CovStructPtr(ID.ID).WeightMode)) ;
write(buf, ' ') ;
write(buf, CovStructPtr(ID.ID).WeightScale, RIGHT, 0, 6) ;
write(buf, ' ') ;
write(buf, CountModeType'pos(CovStructPtr(ID.ID).CountMode)) ;
write(buf, ' ') ;
write(buf, CovStructPtr(ID.ID).ThresholdingEnable) ; -- boolean
write(buf, ' ') ;
write(buf, CovStructPtr(ID.ID).CovTarget, RIGHT, 0, 6) ; -- Real
write(buf, ' ') ;
write(buf, CovStructPtr(ID.ID).MergingEnable) ; -- boolean
write(buf, ' ') ;
writeline(CovDbFile, buf) ;
GetMessageCount(CovStructPtr(ID.ID).CovMessage, CovMessageCount) ;
write(buf, CovMessageCount ) ;
writeline(CovDbFile, buf) ;
WriteMessage(CovDbFile, CovStructPtr(ID.ID).CovMessage) ;
end procedure WriteCovDbVars ;
------------------------------------------------------------
-- pt local
procedure WriteCovDb (ID : CoverageIDType; file CovDbFile : text ) is
------------------------------------------------------------
-- Format: Action Count min1 max1 min2 max2
variable buf : line ;
begin
-- write Cover variables to the file
WriteCovDbVars(ID, CovDbFile ) ;
-- write NumRangeItems, NumLines
write(buf, CovStructPtr(ID.ID).CovBinPtr(1).BinVal'length) ;
write(buf, ' ') ;
write(buf, CovStructPtr(ID.ID).NumBins) ;
write(buf, ' ') ;
writeline(CovDbFile, buf) ;
-- write coverage to a file
writeloop : for LineCount in 1 to CovStructPtr(ID.ID).NumBins loop
write(buf, CovStructPtr(ID.ID).CovBinPtr(LineCount).Action) ;
write(buf, ' ') ;
write(buf, CovStructPtr(ID.ID).CovBinPtr(LineCount).Count) ;
write(buf, ' ') ;
write(buf, CovStructPtr(ID.ID).CovBinPtr(LineCount).AtLeast) ;
write(buf, ' ') ;
write(buf, CovStructPtr(ID.ID).CovBinPtr(LineCount).Weight) ;
write(buf, ' ') ;
write(buf, CovStructPtr(ID.ID).CovBinPtr(LineCount).PercentCov, RIGHT, 0, 4) ;
write(buf, ' ') ;
WriteBinVal(buf, CovStructPtr(ID.ID).CovBinPtr(LineCount).BinVal.all) ;
write(buf, ' ') ;
write(buf, CovStructPtr(ID.ID).CovBinPtr(LineCount).Name'length) ;
write(buf, ' ') ;
write(buf, CovStructPtr(ID.ID).CovBinPtr(LineCount).Name.all) ;
writeline(CovDbFile, buf) ;
end loop WriteLoop ;
end procedure WriteCovDb ;
------------------------------------------------------------
procedure WriteCovDb (ID : CoverageIDType; FileName : string; OpenKind : File_Open_Kind := WRITE_MODE ) is
------------------------------------------------------------
-- Format: Action Count min1 max1 min2 max2
file CovDbFile : text open OpenKind is FileName ;
begin
if CovStructPtr(ID.ID).NumBins >= 1 then
WriteCovDb(ID, CovDbFile) ;
else
Alert(CovStructPtr(ID.ID).AlertLogID, GetNamePlus(ID, prefix => "in ", suffix => ", ") &
"CoveragePkg.WriteCovDb: no bins defined ", FAILURE) ;
end if ;
file_close(CovDbFile) ;
end procedure WriteCovDb ;
-- ------------------------------------------------------------
-- procedure WriteCovDb (ID : CoverageIDType) is
-- ------------------------------------------------------------
-- begin
-- if WriteCovDbFileInit then
-- WriteCovDb(ID, WriteCovDbFile) ;
-- else
-- report "CoveragePkg: WriteCovDb file not specified" severity failure ;
-- end if ;
-- end procedure WriteCovDb ;
------------------------------------------------------------
-- pt local
procedure WriteCovSettingsYaml (ID : CoverageIDType; variable buf : inout LINE; Prefix : string ) is
------------------------------------------------------------
variable TotalCovCount, TotalCovGoal : integer ;
begin
-- write bins to YAML file
write(buf, Prefix & "Settings: " & LF) ;
write(buf, Prefix & " CovWeight: " & to_string(CovStructPtr(ID.ID).CovWeight) & LF) ;
write(buf, Prefix & " Goal: " & to_string(CovStructPtr(ID.ID).CovTarget, 1) & LF) ;
write(buf, Prefix & " WeightMode: """ & to_upper(to_string(CovStructPtr(ID.ID).WeightMode)) & '"' & LF) ;
write(buf, Prefix & " Seeds: [" & to_string(CovStructPtr(ID.ID).RV, ", ") & "]" & LF) ;
write(buf, Prefix & " CountMode: """ & to_upper(to_string(CovStructPtr(ID.ID).CountMode)) & '"' & LF) ;
write(buf, Prefix & " IllegalMode: """ & to_upper(to_string(CovStructPtr(ID.ID).IllegalMode)) & '"' & LF) ;
write(buf, Prefix & " Threshold: " & to_string(CovStructPtr(ID.ID).CovThreshold, 1) & LF) ;
write(buf, Prefix & " ThresholdEnable: """ & to_upper(to_string(CovStructPtr(ID.ID).ThresholdingEnable)) & '"' & LF) ;
GetTotalCovCountAndGoal (ID, TotalCovCount, TotalCovGoal) ;
write(buf, Prefix & " TotalCovCount: " & to_string(TotalCovCount) & LF) ;
write(buf, Prefix & " TotalCovGoal: " & to_string(TotalCovGoal) & LF) ;
end procedure WriteCovSettingsYaml ;
------------------------------------------------------------
-- pt local
procedure WriteCovFieldNameYaml (ID : CoverageIDType; variable buf : inout LINE; Prefix : string ) is
------------------------------------------------------------
variable Dimensions : integer ;
variable FieldWidth : integer ;
variable FieldName : FieldNameArrayPtrType ;
begin
FieldName := CovStructPtr(ID.ID).FieldName ;
Dimensions := CovStructPtr(ID.ID).BinValLength ;
if FieldName = NULL then
FieldWidth := 0 ;
else
FieldWidth := FieldName'length;
end if;
write(buf, Prefix & " FieldNames: " & LF) ;
for i in 1 to Dimensions loop
if i > FieldWidth then
write(buf, Prefix & " - ""Bin" & to_string(i) & '"' & LF) ;
else
write(buf, Prefix & " - """ & FieldName(i).all & '"' & LF) ;
end if ;
end loop ;
end procedure WriteCovFieldNameYaml ;
------------------------------------------------------------
-- pt local
procedure WriteCovBinInfoYaml (ID : CoverageIDType; variable buf : inout LINE; Prefix : string ) is
------------------------------------------------------------
begin
-- write bins to YAML file
write(buf, Prefix & "BinInfo: " & LF) ;
write(buf, Prefix & " Dimensions: " & to_string(CovStructPtr(ID.ID).BinValLength) & LF) ;
WriteCovFieldNameYaml(ID, buf, Prefix) ;
write(buf, Prefix & " NumBins: " & to_string(CovStructPtr(ID.ID).NumBins) & LF) ;
end procedure WriteCovBinInfoYaml ;
------------------------------------------------------------
procedure WriteBinValYaml (
-- package local for now
------------------------------------------------------------
variable buf : inout line ;
constant BinVal : in RangeArrayType ;
constant Prefix : in string
) is
begin
for i in BinVal'range loop
write(buf, Prefix &
"- {Min: " & to_string(BinVal(i).min) &
", Max: " & to_string(BinVal(i).max) & "}" & LF) ;
end loop ;
end procedure WriteBinValYaml ;
------------------------------------------------------------
-- pt local
procedure WriteCovBinsYaml (ID : CoverageIDType; variable buf : inout LINE; Prefix : string ) is
------------------------------------------------------------
variable Action : integer ;
variable CovBin : CovBinInternalBaseType ;
begin
-- write bins to YAML file
write(buf, Prefix & "Bins: " & LF) ;
writeloop : for EachLine in 1 to CovStructPtr(ID.ID).NumBins loop
CovBin := CovStructPtr(ID.ID).CovBinPtr(EachLine) ;
write(buf, Prefix & " - Name: """ & CovBin.Name.all & '"' & LF) ;
write(buf, Prefix & " Type: """ & ActionToName(CovBin.Action) & '"' & LF ) ;
write(buf, Prefix & " Range: " & LF) ;
WriteBinValYaml(buf, CovBin.BinVal.all, Prefix & " ") ;
write(buf, Prefix & " Count: " & to_string(CovBin.Count) & LF) ;
write(buf, Prefix & " AtLeast: " & to_string(CovBin.AtLeast) & LF) ;
write(buf, Prefix & " PercentCov: " & to_string(CovBin.PercentCov, 4) & LF) ;
end loop writeloop ;
end procedure WriteCovBinsYaml ;
------------------------------------------------------------
-- pt local
procedure WriteCovYaml (ID : CoverageIDType; file CovYamlFile : text; TestCaseName : string ) is
------------------------------------------------------------
variable buf : line ;
constant NAME_PREFIX : string := " " ;
begin
-- If no bins, FAIL and return (if resumed)
if CovStructPtr(ID.ID).NumBins < 1 then
Alert(CovStructPtr(ID.ID).AlertLogID, GetNamePlus(ID, prefix => "in ", suffix => ", ") &
"CoveragePkg.WriteCovYaml: no bins defined ", FAILURE) ;
return ;
end if ;
write(buf, NAME_PREFIX & "- Name: " & '"' & GetName(ID) & '"' & LF) ;
--!! TODO: Add Writing for ParentName, ReportMode, Search, PrintParent
write(buf, NAME_PREFIX & " TestCases: " & LF) ;
write(buf, NAME_PREFIX & " - " & '"' & TestCaseName & '"' & LF) ;
--!! Add code to list out merged tests
write(buf, NAME_PREFIX & " Coverage: " & to_string(GetCov(ID), 2) & LF) ;
WriteCovSettingsYaml(ID, buf, NAME_PREFIX & " ") ;
WriteCovBinInfoYaml (ID, buf, NAME_PREFIX & " ") ;
WriteCovBinsYaml (ID, buf, NAME_PREFIX & " ") ;
writeline(CovYamlFile, buf) ;
end procedure WriteCovYaml ;
-- ------------------------------------------------------------
-- procedure WriteCovYaml (ID : CoverageIDType; FileName : string; OpenKind : File_Open_Kind := WRITE_MODE ) is
-- ------------------------------------------------------------
-- file CovYamlFile : text open OpenKind is FileName ;
-- begin
-- WriteCovYaml(ID, CovYamlFile) ;
-- file_close(CovYamlFile) ;
-- end procedure WriteCovYaml ;
------------------------------------------------------------
procedure WriteCovYaml (FileName : string := ""; Coverage : real ; OpenKind : File_Open_Kind := WRITE_MODE) is
------------------------------------------------------------
constant RESOLVED_FILE_NAME : string := IfElse(FileName = "", REPORTS_DIRECTORY & GetAlertLogName & "_cov.yml", FileName) ;
file CovYamlFile : text open OpenKind is RESOLVED_FILE_NAME ;
variable buf : line ;
begin
swrite(buf, "Version: 1.0" & LF) ;
swrite(buf, "Coverage: " & to_string(Coverage, 2) & LF) ;
swrite(buf, "Models: ") ;
writeline(CovYamlFile, buf) ;
for i in 1 to NumItems loop
if CovStructPtr(i).NumBins >= 1 then
WriteCovYaml(CoverageIDType'(ID => i), CovYamlFile, GetAlertLogName) ;
end if ;
end loop ;
file_close(CovYamlFile) ;
end procedure WriteCovYaml ;
------------------------------------------------------------
-- pt local. Find a specific token potentially split across lines
procedure ReadFindToken (
------------------------------------------------------------
file ReadFile : text ;
constant Token : in string ;
variable buf : inout line ;
variable Found : out boolean
) is
variable Empty, MultiLineComment, ReadValid : boolean ;
variable vToken : string(1 to Token'length) ;
begin
Found := FALSE ;
ReadLoop : loop
if buf = NULL or buf.all'length = 0 then
-- return Good FALSE when file empty
exit ReadLoop when EndFile(ReadFile) ;
-- Get Next Line
ReadLine(ReadFile, buf) ;
end if ;
-- Skip blank and multi-line comment lines
EmptyOrCommentLine(buf, Empty, MultiLineComment) ;
next ReadLoop when Empty;
read(buf, vToken, ReadValid) ;
if not ReadValid then
deallocate(buf) ;
next ReadLoop ;
end if ;
next ReadLoop when vToken /= Token ;
Found := TRUE ;
exit ReadLoop ;
end loop ReadLoop ;
end procedure ReadFindToken ;
------------------------------------------------------------
-- pt local
procedure ReadQuotedString (
------------------------------------------------------------
variable buf : inout line ;
variable Name : inout line
) is
variable char : character ;
variable vString : string(1 to buf'length) ;
variable Index : integer := 1 ;
variable Found, Empty, ReadValid : boolean ;
begin
Found := FALSE ;
if Name /= NULL then
deallocate(Name) ;
end if ;
ReadLoop : loop
SkipWhiteSpace(buf, Empty) ; -- Skips white space at beginning of line
exit ReadLoop when Empty ;
exit ReadLoop when buf.all(buf'left) /= '"' ;
Read(buf, Char, ReadValid) ;
exit ReadLoop when not ReadValid ;
for i in vString'range loop
Read(buf, vString(i), ReadValid) ;
exit ReadLoop when not ReadValid ;
if vString(i) = '"' then
Index := i - 1 ;
Found := TRUE ;
exit ;
end if ;
exit ReadLoop when buf.all'length = 0 ;
end loop ;
end loop ReadLoop ;
if Found then
Name := new string'(vString(1 to Index)) ;
end if ;
end procedure ReadQuotedString ;
------------------------------------------------------------
-- pt local
procedure ReadCovModelNameYaml (
------------------------------------------------------------
variable ID : out CoverageIDType ;
file CovYamlFile : text ;
variable Found : out boolean
) is
variable buf : line ;
variable sName : line ;
begin
Found := FALSE ;
ReadLoop: loop
ReadFindToken (CovYamlFile, "- Name:", buf, Found) ;
exit ReadLoop when not Found ;
-- Get the Name
ReadQuotedString(buf, sName) ;
exit when AlertIf(OSVVM_COV_ALERTLOG_ID, sName = NULL,
"CoveragePkg.ReadCovYaml: Unnamed Coverage Model.", COV_READ_YAML_ALERT_LEVEL);
--!! TODO: Add reading for ParentName, ReportMode, Search, PrintParent
ID := NewID(sName.all, ReportMode => ENABLED, Search => NAME_AND_PARENT, PrintParent => PRINT_NAME_AND_PARENT) ;
deallocate(sName) ;
Found := TRUE ;
exit ;
end loop ReadLoop ;
end procedure ReadCovModelNameYaml ;
------------------------------------------------------------
-- pt local
procedure ReadCovSettingsYaml (
------------------------------------------------------------
constant CovID : in CoverageIDType ;
file CovYamlFile : text ;
variable Found : out boolean
) is
variable buf : line ;
variable Name : line ;
constant ID : integer := CovID.ID ;
constant AlertLogID : AlertLogIDType := CovStructPtr(ID).AlertLogID ;
variable vInteger : integer ;
variable vReal : real ;
variable Seed1, Seed2 : integer ;
variable ReadValid : boolean ;
begin
Found := FALSE ;
ReadLoop: loop
ReadFindToken (CovYamlFile, "Settings:", buf, Found) ;
exit ReadLoop when AlertIf(AlertLogID, not Found,
"CoveragePkg.ReadCovYaml did not find ""Settings:""", COV_READ_YAML_ALERT_LEVEL) ;
-- CovWeight
ReadFindToken (CovYamlFile, "CovWeight:", buf, Found) ;
exit ReadLoop when AlertIf(AlertLogID, not Found,
"CoveragePkg.ReadCovYaml did not find ""Settings:""", COV_READ_YAML_ALERT_LEVEL) ;
Read(buf, vInteger, ReadValid) ;
exit ReadLoop when AlertIf(AlertLogID, not ReadValid,
"CoveragePkg.ReadCovYaml Error while reading CovWeight value.", COV_READ_YAML_ALERT_LEVEL) ;
CovStructPtr(ID).CovWeight := vInteger ;
-- Goal / CovTarget
ReadFindToken (CovYamlFile, "Goal:", buf, Found) ;
exit ReadLoop when AlertIf(AlertLogID, not Found,
"CoveragePkg.ReadCovYaml did not find ""Goal:""", COV_READ_YAML_ALERT_LEVEL) ;
Read(buf, vReal, ReadValid) ;
exit ReadLoop when AlertIf(AlertLogID, not ReadValid,
"CoveragePkg.ReadCovYaml Error while reading CovTarget value.", COV_READ_YAML_ALERT_LEVEL) ;
CovStructPtr(ID).CovTarget := vReal ;
-- WeightMode
ReadFindToken (CovYamlFile, "WeightMode:", buf, Found) ;
exit ReadLoop when AlertIf(AlertLogID, not Found,
"CoveragePkg.ReadCovYaml did not find ""WeightMode:""", COV_READ_YAML_ALERT_LEVEL) ;
ReadQuotedString(buf, Name) ;
exit ReadLoop when AlertIf(AlertLogID, Name = NULL,
"CoveragePkg.ReadCovYaml Error while reading WeightMode value.", COV_READ_YAML_ALERT_LEVEL) ;
if Name.all = "REMAIN" then
CovStructPtr(ID).WeightMode := REMAIN ;
else -- at_least
CovStructPtr(ID).WeightMode := AT_LEAST ;
end if ;
-- Seeds
ReadFindToken (CovYamlFile, "Seeds:", buf, Found) ;
exit ReadLoop when AlertIf(AlertLogID, not Found,
"CoveragePkg.ReadCovYaml did not find ""Seeds:""", COV_READ_YAML_ALERT_LEVEL) ;
-- [
ReadFindToken (CovYamlFile, "[", buf, Found) ;
exit ReadLoop when AlertIf(AlertLogID, not Found,
"CoveragePkg.ReadCovYaml did not find Seeds ""[""", COV_READ_YAML_ALERT_LEVEL) ;
Read(buf, Seed1, ReadValid) ;
exit ReadLoop when AlertIf(AlertLogID, not ReadValid,
"CoveragePkg.ReadCovYaml Error while reading Seed1 value.", COV_READ_YAML_ALERT_LEVEL) ;
-- ,
ReadFindToken (CovYamlFile, ",", buf, Found) ;
exit ReadLoop when AlertIf(AlertLogID, not Found,
"CoveragePkg.ReadCovYaml did not find Seed #2 "",""", COV_READ_YAML_ALERT_LEVEL) ;
Read(buf, Seed2, ReadValid) ;
exit ReadLoop when AlertIf(AlertLogID, not ReadValid,
"CoveragePkg.ReadCovYaml Error while reading Seed2 value.", COV_READ_YAML_ALERT_LEVEL) ;
CovStructPtr(ID).RV := (Seed1, Seed2) ;
-- CountMode
ReadFindToken (CovYamlFile, "CountMode:", buf, Found) ;
exit ReadLoop when AlertIf(AlertLogID, not Found,
"CoveragePkg.ReadCovYaml did not find ""CountMode:""", COV_READ_YAML_ALERT_LEVEL) ;
ReadQuotedString(buf, Name) ;
exit ReadLoop when AlertIf(AlertLogID, Name = NULL,
"CoveragePkg.ReadCovYaml Error while reading CountMode value.", COV_READ_YAML_ALERT_LEVEL) ;
if Name.all = "COUNT_ALL" then
CovStructPtr(ID).CountMode := COUNT_ALL ;
else
CovStructPtr(ID).CountMode := COUNT_FIRST ;
end if ;
-- IllegalMode
ReadFindToken (CovYamlFile, "IllegalMode:", buf, Found) ;
exit ReadLoop when AlertIf(AlertLogID, not Found,
"CoveragePkg.ReadCovYaml did not find ""IllegalMode:""", COV_READ_YAML_ALERT_LEVEL) ;
ReadQuotedString(buf, Name) ;
exit ReadLoop when AlertIf(AlertLogID, Name = NULL,
"CoveragePkg.ReadCovYaml Error while reading IllegalMode value.", COV_READ_YAML_ALERT_LEVEL) ;
if Name.all = "ILLEGAL_OFF" then
CovStructPtr(ID).IllegalMode := ILLEGAL_OFF ;
elsif Name.all = "ILLEGAL_FAILURE" then
CovStructPtr(ID).IllegalMode := ILLEGAL_FAILURE ;
else
CovStructPtr(ID).IllegalMode := ILLEGAL_ON ;
end if ;
-- Threshold
ReadFindToken (CovYamlFile, "Threshold:", buf, Found) ;
exit ReadLoop when AlertIf(AlertLogID, not Found,
"CoveragePkg.ReadCovYaml did not find ""Threshold:""", COV_READ_YAML_ALERT_LEVEL) ;
Read(buf, vReal, ReadValid) ;
exit ReadLoop when AlertIf(AlertLogID, not ReadValid,
"CoveragePkg.ReadCovYaml Error while reading Threshold value.", COV_READ_YAML_ALERT_LEVEL) ;
CovStructPtr(ID).CovThreshold := vReal ;
-- ThresholdEnable
ReadFindToken (CovYamlFile, "ThresholdEnable:", buf, Found) ;
exit ReadLoop when AlertIf(AlertLogID, not Found,
"CoveragePkg.ReadCovYaml did not find ""ThresholdEnable:""", COV_READ_YAML_ALERT_LEVEL) ;
ReadQuotedString(buf, Name) ;
exit ReadLoop when AlertIf(AlertLogID, Name = NULL,
"CoveragePkg.ReadCovYaml Error while reading IllegalMode value.", COV_READ_YAML_ALERT_LEVEL) ;
if Name.all = "TRUE" then
CovStructPtr(ID).ThresholdingEnable := TRUE ;
else
CovStructPtr(ID).ThresholdingEnable := FALSE ;
end if ;
-- TotalCovCount - read and toss
ReadFindToken (CovYamlFile, "TotalCovCount:", buf, Found) ;
exit ReadLoop when AlertIf(AlertLogID, not Found,
"CoveragePkg.ReadCovYaml did not find ""TotalCovCount:""", COV_READ_YAML_ALERT_LEVEL) ;
Read(buf, vInteger, ReadValid) ;
exit ReadLoop when AlertIf(AlertLogID, not ReadValid,
"CoveragePkg.ReadCovYaml Error while reading TotalCovCount value.", COV_READ_YAML_ALERT_LEVEL) ;
-- Value not used
-- TotalCovGoal - read and toss
ReadFindToken (CovYamlFile, "TotalCovGoal:", buf, Found) ;
exit ReadLoop when AlertIf(AlertLogID, not Found,
"CoveragePkg.ReadCovYaml did not find ""TotalCovGoal:""", COV_READ_YAML_ALERT_LEVEL) ;
Read(buf, vInteger, ReadValid) ;
exit ReadLoop when AlertIf(AlertLogID, not ReadValid,
"CoveragePkg.ReadCovYaml Error while reading TotalCovGoal value.", COV_READ_YAML_ALERT_LEVEL) ;
-- End
Found := TRUE ;
exit ReadLoop ;
end loop ReadLoop ;
deallocate(Name) ;
end procedure ReadCovSettingsYaml ;
------------------------------------------------------------
-- pt local
procedure ReadCovBinInfoYaml (
------------------------------------------------------------
constant CovID : in CoverageIDType ;
file CovYamlFile : text ;
variable Dimensions : out integer ;
variable NumBins : out integer ;
variable Found : out boolean
) is
variable buf : line ;
variable FieldNameArray : FieldNameArrayType(1 to 20) ;
constant ID : integer := CovID.ID ;
constant AlertLogID : AlertLogIDType := CovStructPtr(ID).AlertLogID ;
variable ReadValid : boolean ;
variable FoundFieldName : boolean ;
begin
Found := FALSE ;
Dimensions := 0 ;
NumBins := 0 ;
ReadLoop: loop
ReadFindToken (CovYamlFile, "BinInfo:", buf, Found) ;
exit when AlertIf(AlertLogID, not Found,
"CoveragePkg.ReadCovYaml did not find ""BinInfo:""", COV_READ_YAML_ALERT_LEVEL) ;
-- Dimensions
ReadFindToken (CovYamlFile, "Dimensions:", buf, Found) ;
exit when AlertIf(AlertLogID, not Found,
"CoveragePkg.ReadCovYaml did not find ""Dimensions:""", COV_READ_YAML_ALERT_LEVEL) ;
Read(buf, Dimensions, ReadValid) ;
exit when AlertIf(AlertLogID, not ReadValid,
"CoveragePkg.ReadCovYaml Error while reading Dimensions value.", COV_READ_YAML_ALERT_LEVEL) ;
CovStructPtr(ID).BinValLength := Dimensions ;
-- FieldNames
ReadFindToken (CovYamlFile, "FieldNames:", buf, Found) ;
exit when AlertIf(AlertLogID, not Found,
"CoveragePkg.ReadCovYaml did not find ""FieldNames:""", COV_READ_YAML_ALERT_LEVEL) ;
-- FieldNames Values
FoundFieldName := FALSE ;
for i in 1 to Dimensions loop
ReadFindToken (CovYamlFile, "-", buf, Found) ;
exit when AlertIf(AlertLogID, not Found,
"CoveragePkg.ReadCovYaml did not find Field Name deliminter '-'.", COV_READ_YAML_ALERT_LEVEL) ;
ReadQuotedString(buf, FieldNameArray(i)) ;
exit ReadLoop when AlertIf(AlertLogID, FieldNameArray(i) = NULL,
"CoveragePkg.ReadCovYaml Error while reading Field Name value # " & to_string(i), COV_READ_YAML_ALERT_LEVEL) ;
if FieldNameArray(i).all /= ("Bin" & to_string(i)) then
FoundFieldName := TRUE ;
end if ;
end loop ;
if FoundFieldName then
CovStructPtr(ID).FieldName := new FieldNameArrayType'(FieldNameArray(1 to Dimensions)) ;
end if ;
-- NumBins
ReadFindToken (CovYamlFile, "NumBins:", buf, Found) ;
exit when AlertIf(AlertLogID, not Found,
"CoveragePkg.ReadCovYaml did not find ""NumBins:""", COV_READ_YAML_ALERT_LEVEL) ;
Read(buf, NumBins, ReadValid) ;
exit when AlertIf(AlertLogID, not ReadValid,
"CoveragePkg.ReadCovYaml Error while reading NumBins value.", COV_READ_YAML_ALERT_LEVEL) ;
-- End
Found := TRUE ;
exit ;
end loop ReadLoop ;
if not Found or not FoundFieldName then
-- clean up pointers
for i in 1 to Dimensions loop
deallocate(FieldNameArray(i)) ;
end loop ;
end if ;
end procedure ReadCovBinInfoYaml ;
------------------------------------------------------------
-- pt local
procedure ReadCovBinValYaml (
------------------------------------------------------------
file CovYamlFile : text ;
constant AlertLogID : in AlertLogIDType ;
variable BinVal : out RangeArrayType ;
variable Found : out boolean
) is
variable buf : line ;
variable Min, Max : integer ;
variable ReadValid : boolean ;
begin
Found := FALSE ;
ReadLoop: loop
-- Range:
ReadFindToken (CovYamlFile, "Range:", buf, Found) ;
exit when AlertIf(AlertLogID, not Found,
"CoveragePkg.ReadCovYaml did not find ""Range:""", COV_READ_YAML_ALERT_LEVEL) ;
-- RangeArrayType
for i in BinVal'range loop
-- - {Min:
ReadFindToken (CovYamlFile, "- {Min:", buf, Found) ;
exit ReadLoop when AlertIf(AlertLogID, not Found,
"CoveragePkg.ReadCovYaml did not find Bins ""Min:""", COV_READ_YAML_ALERT_LEVEL) ;
Read(buf, Min, ReadValid) ;
exit ReadLoop when AlertIf(AlertLogID, not ReadValid,
"CoveragePkg.ReadCovYaml Error while reading Min value.", COV_READ_YAML_ALERT_LEVEL) ;
-- , Max:
ReadFindToken (CovYamlFile, ", Max:", buf, Found) ;
exit ReadLoop when AlertIf(AlertLogID, not Found,
"CoveragePkg.ReadCovYaml did not find Bins ""Max:""", COV_READ_YAML_ALERT_LEVEL) ;
Read(buf, Max, ReadValid) ;
exit ReadLoop when AlertIf(AlertLogID, not ReadValid,
"CoveragePkg.ReadCovYaml Error while reading Max value.", COV_READ_YAML_ALERT_LEVEL) ;
BinVal(i) := (Min => Min, Max => Max) ;
end loop ;
Found := TRUE ;
exit ReadLoop ;
end loop ;
end procedure ReadCovBinValYaml ;
------------------------------------------------------------
-- pt local
procedure ReadCovOneBinYaml (
------------------------------------------------------------
file CovYamlFile : text ;
constant CovID : in CoverageIDType ;
constant Merge : in boolean ;
constant Dimensions : in integer ;
variable Found : out boolean
) is
variable buf : line ;
variable Name : line ;
constant ID : integer := CovID.ID ;
constant AlertLogID : AlertLogIDType := CovStructPtr(ID).AlertLogID ;
variable NamePtr : line ;
variable Action : integer ;
variable BinVal : RangeArrayType(1 to Dimensions) ;
variable Count : integer ;
variable AtLeast : integer ;
variable Weight : integer ;
variable PercentCov : real ;
variable Index : integer ;
variable ReadValid : boolean ;
begin
Found := FALSE ;
ReadLoop: loop
-- - Name:
ReadFindToken (CovYamlFile, "- Name:", buf, Found) ;
exit when AlertIf(AlertLogID, not Found,
"CoveragePkg.ReadCovYaml did not find Bins ""Name:""", COV_READ_YAML_ALERT_LEVEL) ;
ReadQuotedString(buf, NamePtr) ;
exit ReadLoop when AlertIf(AlertLogID, NamePtr = NULL,
"CoveragePkg.ReadCovYaml Error while reading Name value.", COV_READ_YAML_ALERT_LEVEL) ;
-- Type:
ReadFindToken (CovYamlFile, "Type:", buf, Found) ;
exit when AlertIf(AlertLogID, not Found,
"CoveragePkg.ReadCovYaml did not find ""Type:""", COV_READ_YAML_ALERT_LEVEL) ;
ReadQuotedString(buf, Name) ;
exit ReadLoop when AlertIf(AlertLogID, Name = NULL,
"CoveragePkg.ReadCovYaml Error while reading Type value.", COV_READ_YAML_ALERT_LEVEL) ;
if Name.all = "COUNT" then
Action := 1 ;
elsif Name.all = "IGNORE" then
Action := 0 ;
else -- Illegal
Action := -1 ;
end if ;
deallocate(Name) ;
-- BinVal
ReadCovBinValYaml(CovYamlFile, AlertLogID, BinVal, Found) ;
exit when not Found ;
-- Count:
ReadFindToken (CovYamlFile, "Count:", buf, Found) ;
exit when AlertIf(AlertLogID, not Found,
"CoveragePkg.ReadCovYaml did not find ""Count:""", COV_READ_YAML_ALERT_LEVEL) ;
Read(buf, Count, ReadValid) ;
exit when AlertIf(AlertLogID, not ReadValid,
"CoveragePkg.ReadCovYaml Error while reading Count value.", COV_READ_YAML_ALERT_LEVEL) ;
-- AtLeast:
ReadFindToken (CovYamlFile, "AtLeast:", buf, Found) ;
exit when AlertIf(AlertLogID, not Found,
"CoveragePkg.ReadCovYaml did not find ""AtLeast:""", COV_READ_YAML_ALERT_LEVEL) ;
Read(buf, AtLeast, ReadValid) ;
exit when AlertIf(AlertLogID, not ReadValid,
"CoveragePkg.ReadCovYaml Error while reading AtLeast value.", COV_READ_YAML_ALERT_LEVEL) ;
Weight := AtLeast ;
-- PercentCov:
ReadFindToken (CovYamlFile, "PercentCov:", buf, Found) ;
exit when AlertIf(AlertLogID, not Found,
"CoveragePkg.ReadCovYaml did not find ""PercentCov:""", COV_READ_YAML_ALERT_LEVEL) ;
Read(buf, PercentCov, ReadValid) ;
exit when AlertIf(AlertLogID, not ReadValid,
"CoveragePkg.ReadCovYaml Error while reading PercentCov value.", COV_READ_YAML_ALERT_LEVEL) ;
-- Insert the Bin
Index := FindExactBin(CovID, Merge, BinVal, Action, AtLeast, Weight, NamePtr.all) ;
if Index > 0 then
-- Bin is an exact match so only merge the count values
CovStructPtr(ID).CovBinPtr(Index).Count := CovStructPtr(ID).CovBinPtr(Index).Count + Count ;
CovStructPtr(ID).CovBinPtr(Index).PercentCov := CalcPercentCov(
Count => CovStructPtr(ID).CovBinPtr.all(Index).Count,
AtLeast => CovStructPtr(ID).CovBinPtr.all(Index).AtLeast ) ;
else
InsertNewBin(CovID, BinVal, Action, Count, AtLeast, Weight, NamePtr.all, PercentCov) ;
end if ;
deallocate(NamePtr) ;
-- End
Found := TRUE ;
exit ;
end loop ReadLoop ;
end procedure ReadCovOneBinYaml ;
------------------------------------------------------------
-- pt local
procedure ReadCovBinsYaml (
------------------------------------------------------------
constant CovID : in CoverageIDType ;
file CovYamlFile : text ;
constant Dimensions : in integer ;
constant NumBins : in integer ;
variable Found : out boolean ;
constant Merge : in boolean := FALSE
) is
variable buf : line ;
variable FieldNameArray : FieldNameArrayType(1 to 20) ;
constant ID : integer := CovID.ID ;
constant AlertLogID : AlertLogIDType := CovStructPtr(ID).AlertLogID ;
begin
Found := FALSE ;
ReadLoop: loop
ReadFindToken (CovYamlFile, "Bins:", buf, Found) ;
exit when AlertIf(AlertLogID, not Found,
"CoveragePkg.ReadCovYaml did not find ""Bins:""", COV_READ_YAML_ALERT_LEVEL) ;
GrowBins(CovID, NumBins) ;
for i in 1 to NumBins loop
ReadCovOneBinYaml(CovYamlFile, CovID, Merge, Dimensions, Found) ;
exit ReadLoop when not Found ;
end loop ;
-- End
Found := TRUE ;
exit ;
end loop ReadLoop ;
end procedure ReadCovBinsYaml ;
------------------------------------------------------------
-- pt local
procedure ReadCovModelYaml (
------------------------------------------------------------
file CovYamlFile : text ;
variable Found : out boolean ;
constant Merge : in boolean := FALSE
) is
variable CovID : CoverageIDType ;
variable Dimensions : integer ;
variable NumBins : integer ;
variable FoundModelName : boolean ;
begin
Found := FALSE ;
FoundModelName := FALSE ;
ReadLoop: loop
ReadCovModelNameYaml(CovID, CovYamlFile, Found) ;
exit when not Found ;
FoundModelName := TRUE ;
if not Merge then -- remove any old bins
DeallocateBins(CovID) ;
end if ;
-- Nothing to do with this for now
-- ReadCovTestCasesYaml(CovID, CovYamlFile, Found) ;
-- exit when not Found ;
-- On merge, new settings apply
ReadCovSettingsYaml(CovID, CovYamlFile, Found) ;
exit when not Found ;
-- On merge, new settings apply
ReadCovBinInfoYaml(CovID, CovYamlFile, Dimensions, NumBins, Found) ;
exit when not Found ;
-- On merge, matching bins are merged
ReadCovBinsYaml(CovID, CovYamlFile, Dimensions, NumBins, Found, Merge) ;
exit when not Found ;
-- End
Found := TRUE ;
exit ;
end loop ReadLoop ;
if FoundModelName and not Found then
-- remove partially constructed model
Deallocate(CovID) ;
end if ;
end procedure ReadCovModelYaml ;
-- ------------------------------------------------------------
-- procedure ReadCovYaml (ModelName : string; FileName : string) is
-- ------------------------------------------------------------
-- file CovYamlFile : text open READ_MODE is FileName ;
-- begin
-- ID := NewID("ModelName"
-- ReadCovYaml(ID, CovYamlFile) ;
-- file_close(CovYamlFile) ;
-- end procedure ReadCovYaml ;
------------------------------------------------------------
procedure ReadCovYaml (FileName : string := ""; Merge : boolean := FALSE) is
------------------------------------------------------------
constant RESOLVED_FILE_NAME : string := IfElse(FileName = "", REPORTS_DIRECTORY & GetAlertLogName & "_cov.yml", FileName) ;
file CovYamlFile : text open READ_MODE is RESOLVED_FILE_NAME ;
variable buf : line ;
variable Found : boolean ;
begin
ReadFindToken (CovYamlFile, "Models:", buf, Found) ;
if not Found then
Alert(OSVVM_COV_ALERTLOG_ID,
"No Coverage Models found in " & RESOLVED_FILE_NAME, COV_READ_YAML_ALERT_LEVEL) ;
return ;
end if;
loop
ReadCovModelYaml(CovYamlFile, Found, Merge) ;
exit when not Found ;
end loop ;
file_close(CovYamlFile) ;
end procedure ReadCovYaml ;
------------------------------------------------------------
impure function GotCoverage return boolean is
------------------------------------------------------------
begin
for i in 1 to NumItems loop
if CovStructPtr(i).NumBins >= 1 then
return TRUE ;
end if;
end loop ;
return FALSE ;
end function GotCoverage ;
------------------------------------------------------------
impure function GetErrorCount (ID : CoverageIDType) return integer is
------------------------------------------------------------
variable ErrorCnt : integer := 0 ;
begin
if CovStructPtr(ID.ID).NumBins < 1 then
return 1 ; -- return error if model empty
else
for i in 1 to CovStructPtr(ID.ID).NumBins loop
if CovStructPtr(ID.ID).CovBinPtr(i).count < 0 then -- illegal CovBin
ErrorCnt := ErrorCnt + CovStructPtr(ID.ID).CovBinPtr(i).count ;
end if ;
end loop ;
return - ErrorCnt ;
end if ;
end function GetErrorCount ;
------------------------------------------------------------
-- pt local
-- Adjusted InsertBin
-- Ensures minimum of Count and AtLeast are 1
procedure AdjustedInsertBin (
ID : CoverageIDType ;
BinVal : RangeArrayType ;
Action : integer ;
Count : integer ;
AtLeast : integer ;
Weight : integer ;
Name : string
) is
variable vCalcAtLeast : integer ;
variable vCalcWeight : integer ;
begin
if Action = COV_COUNT then
vCalcAtLeast := maximum(0, AtLeast) ;
vCalcWeight := maximum(0, Weight) ;
else
vCalcAtLeast := 0 ;
vCalcWeight := 0 ;
end if ;
InsertBin(
ID => ID,
BinVal => BinVal,
Action => Action,
Count => Count,
AtLeast => vCalcAtLeast,
Weight => vCalcWeight,
Name => Name
) ;
end procedure AdjustedInsertBin ;
------------------------------------------------------------
-- These support usage of cross coverage constants
-- Also support the older AddCross(GenCross(...)) methodology
-- which has been replaced by AddCross(GenBin, GenBin, ...)
------------------------------------------------------------
procedure AddCross (ID : CoverageIDType; CovBin : CovMatrix2Type ; Name : String := "") is
------------------------------------------------------------
begin
if BinValLengthNotEqual(ID, 2) then
Alert(CovStructPtr(ID.ID).AlertLogID, "CoveragePkg.AddCross: Cross coverage bins of different dimensions prohibited", FAILURE) ;
return ;
end if ;
GrowBins(ID, CovBin'length) ;
for i in CovBin'range loop
InsertBin(ID,
CovBin(i).BinVal, CovBin(i).Action, CovBin(i).Count,
CovBin(i).AtLeast, CovBin(i).Weight, Name
) ;
end loop ;
end procedure AddCross ;
------------------------------------------------------------
procedure AddCross (ID : CoverageIDType; CovBin : CovMatrix3Type ; Name : String := "") is
------------------------------------------------------------
begin
if BinValLengthNotEqual(ID, 3) then
Alert(CovStructPtr(ID.ID).AlertLogID, "CoveragePkg.AddCross: Cross coverage bins of different dimensions prohibited", FAILURE) ;
return ;
end if ;
GrowBins(ID, CovBin'length) ;
for i in CovBin'range loop
AdjustedInsertBin(ID,
CovBin(i).BinVal, CovBin(i).Action, CovBin(i).Count,
CovBin(i).AtLeast, CovBin(i).Weight, Name
) ;
end loop ;
end procedure AddCross ;
------------------------------------------------------------
procedure AddCross (ID : CoverageIDType; CovBin : CovMatrix4Type ; Name : String := "") is
------------------------------------------------------------
begin
if BinValLengthNotEqual(ID, 4) then
Alert(CovStructPtr(ID.ID).AlertLogID, "CoveragePkg.AddCross: Cross coverage bins of different dimensions prohibited", FAILURE) ;
return ;
end if ;
GrowBins(ID, CovBin'length) ;
for i in CovBin'range loop
AdjustedInsertBin(ID,
CovBin(i).BinVal, CovBin(i).Action, CovBin(i).Count,
CovBin(i).AtLeast, CovBin(i).Weight, Name
) ;
end loop ;
end procedure AddCross ;
------------------------------------------------------------
procedure AddCross (ID : CoverageIDType; CovBin : CovMatrix5Type ; Name : String := "") is
------------------------------------------------------------
begin
if BinValLengthNotEqual(ID, 5) then
Alert(CovStructPtr(ID.ID).AlertLogID, "CoveragePkg.AddCross: Cross coverage bins of different dimensions prohibited", FAILURE) ;
return ;
end if ;
GrowBins(ID, CovBin'length) ;
for i in CovBin'range loop
AdjustedInsertBin(ID,
CovBin(i).BinVal, CovBin(i).Action, CovBin(i).Count,
CovBin(i).AtLeast, CovBin(i).Weight, Name
) ;
end loop ;
end procedure AddCross ;
------------------------------------------------------------
procedure AddCross (ID : CoverageIDType; CovBin : CovMatrix6Type ; Name : String := "") is
------------------------------------------------------------
begin
if BinValLengthNotEqual(ID, 6) then
Alert(CovStructPtr(ID.ID).AlertLogID, "CoveragePkg.AddCross: Cross coverage bins of different dimensions prohibited", FAILURE) ;
return ;
end if ;
GrowBins(ID, CovBin'length) ;
for i in CovBin'range loop
AdjustedInsertBin(ID,
CovBin(i).BinVal, CovBin(i).Action, CovBin(i).Count,
CovBin(i).AtLeast, CovBin(i).Weight, Name
) ;
end loop ;
end procedure AddCross ;
------------------------------------------------------------
procedure AddCross (ID : CoverageIDType; CovBin : CovMatrix7Type ; Name : String := "") is
------------------------------------------------------------
begin
if BinValLengthNotEqual(ID, 7) then
Alert(CovStructPtr(ID.ID).AlertLogID, "CoveragePkg.AddCross: Cross coverage bins of different dimensions prohibited", FAILURE) ;
return ;
end if ;
GrowBins(ID, CovBin'length) ;
for i in CovBin'range loop
AdjustedInsertBin(ID,
CovBin(i).BinVal, CovBin(i).Action, CovBin(i).Count,
CovBin(i).AtLeast, CovBin(i).Weight, Name
) ;
end loop ;
end procedure AddCross ;
------------------------------------------------------------
procedure AddCross (ID : CoverageIDType; CovBin : CovMatrix8Type ; Name : String := "") is
------------------------------------------------------------
begin
if BinValLengthNotEqual(ID, 8) then
Alert(CovStructPtr(ID.ID).AlertLogID, "CoveragePkg.AddCross: Cross coverage bins of different dimensions prohibited", FAILURE) ;
return ;
end if ;
GrowBins(ID, CovBin'length) ;
for i in CovBin'range loop
AdjustedInsertBin(ID,
CovBin(i).BinVal, CovBin(i).Action, CovBin(i).Count,
CovBin(i).AtLeast, CovBin(i).Weight, Name
) ;
end loop ;
end procedure AddCross ;
------------------------------------------------------------
procedure AddCross (ID : CoverageIDType; CovBin : CovMatrix9Type ; Name : String := "") is
------------------------------------------------------------
begin
if BinValLengthNotEqual(ID, 9) then
Alert(CovStructPtr(ID.ID).AlertLogID, "CoveragePkg.AddCross: Cross coverage bins of different dimensions prohibited", FAILURE) ;
return ;
end if ;
GrowBins(ID, CovBin'length) ;
for i in CovBin'range loop
AdjustedInsertBin(ID,
CovBin(i).BinVal, CovBin(i).Action, CovBin(i).Count,
CovBin(i).AtLeast, CovBin(i).Weight, Name
) ;
end loop ;
end procedure AddCross ;
--!!!! How to handle this - do not support in main interface
--------------------------------------------------------------
--------------------------------------------------------------
-- Deprecated / Subsumed by versions with PercentCov Parameter
-- Maintained for backward compatibility only and
-- may be removed in the future.
-- ------------------------------------------------------------
------------------------------------------------------------
-- Deprecated. New versions use PercentCov
impure function CountCovHoles (ID : CoverageIDType; AtLeast : integer ) return integer is
------------------------------------------------------------
variable HoleCount : integer := 0 ;
begin
CovLoop : for i in 1 to CovStructPtr(ID.ID).NumBins loop
-- if CovStructPtr(ID.ID).CovBinPtr(i).action = COV_COUNT and CovStructPtr(ID.ID).CovBinPtr(i).Count < minimum(AtLeast, CovStructPtr(ID.ID).CovBinPtr(i).AtLeast) then
if CovStructPtr(ID.ID).CovBinPtr(i).action = COV_COUNT and CovStructPtr(ID.ID).CovBinPtr(i).Count < AtLeast then
HoleCount := HoleCount + 1 ;
end if ;
end loop CovLoop ;
return HoleCount ;
end function CountCovHoles ;
------------------------------------------------------------
-- Deprecated. New versions use PercentCov
impure function IsCovered (ID : CoverageIDType; AtLeast : integer ) return boolean is
------------------------------------------------------------
begin
return CountCovHoles(ID, AtLeast) = 0 ;
end function IsCovered ;
------------------------------------------------------------
impure function CalcWeight (ID : CoverageIDType; BinIndex : integer ; MaxAtLeast : integer ) return integer is
-- pt local
------------------------------------------------------------
begin
case CovStructPtr(ID.ID).WeightMode is
when AT_LEAST =>
return CovStructPtr(ID.ID).CovBinPtr(BinIndex).AtLeast ;
when WEIGHT =>
return CovStructPtr(ID.ID).CovBinPtr(BinIndex).Weight ;
when REMAIN =>
return MaxAtLeast - CovStructPtr(ID.ID).CovBinPtr(BinIndex).Count ;
when REMAIN_SCALED =>
-- Experimental may be removed
return integer( Ceil( CovStructPtr(ID.ID).WeightScale * real(MaxAtLeast))) -
CovStructPtr(ID.ID).CovBinPtr(BinIndex).Count ;
when REMAIN_WEIGHT =>
-- Experimental may be removed
return CovStructPtr(ID.ID).CovBinPtr(BinIndex).Weight * (
integer( Ceil( CovStructPtr(ID.ID).WeightScale * real(MaxAtLeast))) -
CovStructPtr(ID.ID).CovBinPtr(BinIndex).Count ) ;
when others =>
Alert(CovStructPtr(ID.ID).AlertLogID, GetNamePlus(ID, prefix => "in ", suffix => ", ") & "CoveragePkg.CalcWeight:" &
" Selected Weight Mode not supported with deprecated RandCovPoint(AtLeast), see RandCovPoint(PercentCov)", FAILURE) ;
return MaxAtLeast - CovStructPtr(ID.ID).CovBinPtr(BinIndex).Count ;
end case ;
end function CalcWeight ;
------------------------------------------------------------
-- Deprecated. New versions use PercentCov
-- If keep this, need to be able to scale AtLeast Value
impure function GetRandIndex (ID : CoverageIDType; AtLeast : integer ) return integer is
-- pt local
------------------------------------------------------------
variable WeightVec : integer_vector(0 to CovStructPtr(ID.ID).NumBins-1) ; -- Prep for change to DistInt
variable MinCount, AdjAtLeast, MaxAtLeast : integer ;
variable rInt : integer ;
begin
CovStructPtr(ID.ID).ItemCount := CovStructPtr(ID.ID).ItemCount + 1 ;
MinCount := GetMinCount(ID) ;
-- iAtLeast := integer(ceil(CovStructPtr(ID.ID).CovTarget * real(AtLeast)/100.0)) ;
if CovStructPtr(ID.ID).ThresholdingEnable then
AdjAtLeast := MinCount + integer(CovStructPtr(ID.ID).CovThreshold) + 1 ;
if MinCount < AtLeast then
-- Clip at AtLeast until reach AtLeast
AdjAtLeast := minimum(AdjAtLeast, AtLeast) ;
end if ;
else
if MinCount < AtLeast then
AdjAtLeast := AtLeast ; -- Valid
else
-- Done, Enable all bins
-- AdjAtLeast := integer'right ; -- Get All
AdjAtLeast := GetMaxCount(ID) + 1 ; -- Get All
end if ;
end if;
MaxAtLeast := AdjAtLeast ;
CovLoop : for i in 1 to CovStructPtr(ID.ID).NumBins loop
-- if not CovStructPtr(ID.ID).ThresholdingEnable then
-- -- When not thresholding, consider bin Bin.AtLeast
-- -- iBinAtLeast := integer(ceil(CovStructPtr(ID.ID).CovTarget * real(CovStructPtr(ID.ID).CovBinPtr(i).AtLeast)/100.0)) ;
-- MaxAtLeast := maximum(AdjAtLeast, CovStructPtr(ID.ID).CovBinPtr(i).AtLeast) ;
-- end if ;
if CovStructPtr(ID.ID).CovBinPtr(i).action = COV_COUNT and CovStructPtr(ID.ID).CovBinPtr(i).Count < MaxAtLeast then
WeightVec(i-1) := CalcWeight(ID, i, MaxAtLeast ) ; -- CovStructPtr(ID.ID).CovBinPtr(i).Weight ;
else
WeightVec(i-1) := 0 ;
end if ;
end loop CovLoop ;
-- DistInt returns integer range 0 to CovStructPtr(ID.ID).NumBins-1
-- CovStructPtr(ID.ID).LastStimGenIndex := 1 + RV.DistInt( WeightVec ) ; -- return range 1 to CovStructPtr(ID.ID).NumBins
DistInt(CovStructPtr(ID.ID).RV, rInt, WeightVec) ;
CovStructPtr(ID.ID).LastStimGenIndex := 1 + rInt ; -- return range 1 to CovStructPtr(ID.ID).NumBins
CovStructPtr(ID.ID).LastIndex := CovStructPtr(ID.ID).LastStimGenIndex ;
return CovStructPtr(ID.ID).LastStimGenIndex ;
end function GetRandIndex ;
------------------------------------------------------------
-- Deprecated. New versions use PercentCov
impure function RandCovBinVal (ID : CoverageIDType; AtLeast : integer ) return RangeArrayType is
------------------------------------------------------------
begin
return CovStructPtr(ID.ID).CovBinPtr( GetRandIndex(ID, AtLeast) ).BinVal.all ; -- GetBinVal
end function RandCovBinVal ;
-- Maintained for backward compatibility. Repeated until aliases work for methods
------------------------------------------------------------
-- Deprecated+ New versions use PercentCov. Name change.
impure function RandCovHole (ID : CoverageIDType; AtLeast : integer ) return RangeArrayType is
------------------------------------------------------------
begin
return RandCovBinVal(ID, AtLeast) ; -- GetBinVal
end function RandCovHole ;
------------------------------------------------------------
-- Deprecated. New versions use PercentCov
impure function RandCovPoint (ID : CoverageIDType; AtLeast : integer ) return integer is
------------------------------------------------------------
variable BinVal : RangeArrayType(1 to 1) ;
variable rInt : integer ;
begin
BinVal := RandCovBinVal(ID, AtLeast) ;
-- return RV.RandInt(BinVal(1).min, BinVal(1).max) ;
Uniform(CovStructPtr(ID.ID).RV, rInt, BinVal(1).min, BinVal(1).max) ;
return rInt ;
end function RandCovPoint ;
------------------------------------------------------------
impure function RandCovPoint (ID : CoverageIDType; AtLeast : integer ) return integer_vector is
------------------------------------------------------------
begin
return ToRandPoint(ID, RandCovBinVal(ID, AtLeast)) ;
end function RandCovPoint ;
------------------------------------------------------------
-- Deprecated. New versions use PercentCov
impure function GetHoleBinVal (ID : CoverageIDType; ReqHoleNum : integer ; AtLeast : integer ) return RangeArrayType is
------------------------------------------------------------
variable HoleCount : integer := 0 ;
variable buf : line ;
begin
CovLoop : for i in 1 to CovStructPtr(ID.ID).NumBins loop
-- if CovStructPtr(ID.ID).CovBinPtr(i).action = COV_COUNT and CovStructPtr(ID.ID).CovBinPtr(i).Count < minimum(AtLeast, CovStructPtr(ID.ID).CovBinPtr(i).AtLeast) then
if CovStructPtr(ID.ID).CovBinPtr(i).action = COV_COUNT and CovStructPtr(ID.ID).CovBinPtr(i).Count < AtLeast then
HoleCount := HoleCount + 1 ;
if HoleCount = ReqHoleNum then
return CovStructPtr(ID.ID).CovBinPtr(i).BinVal.all ;
end if ;
end if ;
end loop CovLoop ;
Alert(CovStructPtr(ID.ID).AlertLogID, GetNamePlus(ID, prefix => "in ", suffix => ", ") & "CoveragePkg.GetHoleBinVal:" &
" did not find hole. HoleCount = " & integer'image(HoleCount) &
"ReqHoleNum = " & integer'image(ReqHoleNum), ERROR
) ;
return CovStructPtr(ID.ID).CovBinPtr(CovStructPtr(ID.ID).NumBins).BinVal.all ;
end function GetHoleBinVal ;
------------------------------------------------------------
-- Deprecated+. New versions use PercentCov. Name Change.
impure function GetCovHole (ID : CoverageIDType; ReqHoleNum : integer ; AtLeast : integer ) return RangeArrayType is
------------------------------------------------------------
begin
return GetHoleBinVal(ID, ReqHoleNum, AtLeast) ;
end function GetCovHole ;
------------------------------------------------------------
-- pt local
-- Deprecated. New versions use PercentCov.
procedure WriteCovHoles (ID : CoverageIDType; file f : text; AtLeast : integer; UsingLocalFile : boolean := FALSE ) is
------------------------------------------------------------
-- variable minAtLeast : integer ;
variable buf : line ;
begin
WriteBinName(ID, buf, "WriteCovHoles: ") ;
-- writeline(f, buf) ;
if CovStructPtr(ID.ID).NumBins < 1 then
if WriteBinFileInit or UsingLocalFile then
-- Duplicate Alert in specified file
swrite(buf, "%% Alert FAILURE " & GetNamePlus(ID, prefix => "in ", suffix => ", ") & "CoveragePkg.WriteCovHoles:" &
" coverage model is empty. Nothing to print.") ;
writeline(f, buf) ;
end if ;
Alert(CovStructPtr(ID.ID).AlertLogID, GetNamePlus(ID, prefix => "in ", suffix => ", ") & "CoveragePkg.WriteCovHoles:" &
" coverage model is empty. Nothing to print.", FAILURE) ;
end if ;
CovLoop : for i in 1 to CovStructPtr(ID.ID).NumBins loop
-- minAtLeast := minimum(AtLeast,CovStructPtr(ID.ID).CovBinPtr(i).AtLeast) ;
-- if CovStructPtr(ID.ID).CovBinPtr(i).action = COV_COUNT and CovStructPtr(ID.ID).CovBinPtr(i).Count < minAtLeast then
if CovStructPtr(ID.ID).CovBinPtr(i).action = COV_COUNT and CovStructPtr(ID.ID).CovBinPtr(i).Count < AtLeast then
swrite(buf, "%% Bin:") ;
write(buf, CovStructPtr(ID.ID).CovBinPtr(i).BinVal.all) ;
write(buf, " Count = " & integer'image(CovStructPtr(ID.ID).CovBinPtr(i).Count)) ;
write(buf, " AtLeast = " & integer'image(CovStructPtr(ID.ID).CovBinPtr(i).AtLeast)) ;
if CovStructPtr(ID.ID).WeightMode = WEIGHT or CovStructPtr(ID.ID).WeightMode = REMAIN_WEIGHT then
-- Print Weight only when it is used
write(buf, " Weight = " & integer'image(CovStructPtr(ID.ID).CovBinPtr(i).Weight)) ;
end if ;
writeline(f, buf) ;
end if ;
end loop CovLoop ;
swrite(buf, "") ;
writeline(f, buf) ;
end procedure WriteCovHoles ;
------------------------------------------------------------
-- Deprecated. New versions use PercentCov.
procedure WriteCovHoles (ID : CoverageIDType; AtLeast : integer ) is
------------------------------------------------------------
begin
if WriteBinFileInit then
-- Write to Local WriteBinFile - Deprecated, recommend use TranscriptFile instead
WriteCovHoles(ID, WriteBinFile, AtLeast) ;
elsif IsTranscriptEnabled then
-- Write to TranscriptFile
WriteCovHoles(ID, TranscriptFile, AtLeast) ;
if IsTranscriptMirrored then
-- Mirrored to OUTPUT
WriteCovHoles(ID, OUTPUT, AtLeast) ;
end if ;
else
-- Default Write to OUTPUT
WriteCovHoles(ID, OUTPUT, AtLeast) ;
end if;
end procedure WriteCovHoles ;
------------------------------------------------------------
-- Deprecated. New versions use PercentCov.
procedure WriteCovHoles (ID : CoverageIDType; LogLevel : LogType ; AtLeast : integer ) is
------------------------------------------------------------
begin
if IsLogEnabled(CovStructPtr(ID.ID).AlertLogID, LogLevel) then
WriteCovHoles(ID, AtLeast) ;
end if;
end procedure WriteCovHoles ;
------------------------------------------------------------
-- Deprecated. New versions use PercentCov.
procedure WriteCovHoles (ID : CoverageIDType; FileName : string; AtLeast : integer ; OpenKind : File_Open_Kind := APPEND_MODE ) is
------------------------------------------------------------
file CovHoleFile : text open OpenKind is FileName ;
begin
WriteCovHoles(ID, CovHoleFile, AtLeast, TRUE) ;
end procedure WriteCovHoles ;
------------------------------------------------------------
-- Deprecated. New versions use PercentCov.
procedure WriteCovHoles (ID : CoverageIDType; LogLevel : LogType ; FileName : string; AtLeast : integer ; OpenKind : File_Open_Kind := APPEND_MODE ) is
------------------------------------------------------------
begin
if IsLogEnabled(CovStructPtr(ID.ID).AlertLogID, LogLevel) then
WriteCovHoles(ID, FileName, AtLeast, OpenKind) ;
end if;
end procedure WriteCovHoles ;
------------------------------------------------------------
-- /////////////////////////////////////////
-- /////////////////////////////////////////
-- Compatibility Methods - Allows CoveragePkg to Work as a PT still
-- /////////////////////////////////////////
-- /////////////////////////////////////////
------------------------------------------------------------
------------------------------------------------------------
procedure SetAlertLogID (A : AlertLogIDType) is
------------------------------------------------------------
begin
SetAlertLogID(COV_STRUCT_ID_DEFAULT, A) ;
end procedure SetAlertLogID ;
------------------------------------------------------------
procedure SetAlertLogID(Name : string ; ParentID : AlertLogIDType := ALERTLOG_BASE_ID ; CreateHierarchy : Boolean := TRUE) is
------------------------------------------------------------
constant SeedInit : boolean := CovStructPtr(COV_STRUCT_ID_DEFAULT.ID).RvSeedInit ;
begin
SetAlertLogID(COV_STRUCT_ID_DEFAULT, Name, ParentID, CreateHierarchy) ;
if not SeedInit then
InitSeed(COV_STRUCT_ID_DEFAULT, Name, FALSE) ;
end if ;
end procedure SetAlertLogID ;
------------------------------------------------------------
impure function GetAlertLogID return AlertLogIDType is
------------------------------------------------------------
begin
return GetAlertLogID(COV_STRUCT_ID_DEFAULT) ;
end function GetAlertLogID ;
------------------------------------------------------------
procedure SetName (Name : String) is
------------------------------------------------------------
constant SeedInit : boolean := CovStructPtr(COV_STRUCT_ID_DEFAULT.ID).RvSeedInit ;
begin
SetName(COV_STRUCT_ID_DEFAULT, Name) ;
if not SeedInit then
InitSeed(COV_STRUCT_ID_DEFAULT, Name, FALSE) ;
end if ;
end procedure SetName ;
------------------------------------------------------------
impure function SetName (Name : String) return string is
------------------------------------------------------------
begin
SetName(Name) ; -- call procedure above
return Name ;
end function SetName ;
------------------------------------------------------------
impure function GetName return String is
------------------------------------------------------------
begin
return GetName(COV_STRUCT_ID_DEFAULT) ;
end function GetName ;
------------------------------------------------------------
impure function GetCovModelName return String is
------------------------------------------------------------
begin
return GetCovModelName(COV_STRUCT_ID_DEFAULT) ;
end function GetCovModelName ;
------------------------------------------------------------
impure function GetNamePlus(prefix, suffix : string) return String is
------------------------------------------------------------
begin
return GetNamePlus(COV_STRUCT_ID_DEFAULT, prefix, suffix) ;
end function GetNamePlus ;
------------------------------------------------------------
procedure SetMessage (Message : String) is
------------------------------------------------------------
constant SeedInit : boolean := CovStructPtr(COV_STRUCT_ID_DEFAULT.ID).RvSeedInit ;
begin
SetMessage(COV_STRUCT_ID_DEFAULT, Message) ;
if not SeedInit then
InitSeed(COV_STRUCT_ID_DEFAULT, Message, FALSE) ;
end if ;
end procedure SetMessage ;
------------------------------------------------------------
procedure SetNextPointMode (A : NextPointModeType) is
------------------------------------------------------------
begin
SetNextPointMode(COV_STRUCT_ID_DEFAULT, A) ;
end procedure SetNextPointMode ;
------------------------------------------------------------
procedure SetIllegalMode (A : IllegalModeType) is
------------------------------------------------------------
begin
SetIllegalMode(COV_STRUCT_ID_DEFAULT, A) ;
end procedure SetIllegalMode ;
------------------------------------------------------------
procedure SetWeightMode (A : WeightModeType; Scale : real := 1.0) is
------------------------------------------------------------
begin
SetWeightMode(COV_STRUCT_ID_DEFAULT, A, Scale) ;
end procedure SetWeightMode ;
------------------------------------------------------------
procedure DeallocateMessage is
------------------------------------------------------------
begin
DeallocateMessage(COV_STRUCT_ID_DEFAULT) ;
end procedure DeallocateMessage ;
------------------------------------------------------------
procedure DeallocateName is
------------------------------------------------------------
begin
DeallocateName(COV_STRUCT_ID_DEFAULT) ;
end procedure DeallocateName ;
------------------------------------------------------------
procedure SetThresholding (A : boolean := TRUE ) is
------------------------------------------------------------
begin
SetThresholding(COV_STRUCT_ID_DEFAULT, A) ;
end procedure SetThresholding ;
------------------------------------------------------------
procedure SetCovThreshold (Percent : real) is
------------------------------------------------------------
begin
SetCovThreshold(COV_STRUCT_ID_DEFAULT, Percent) ;
end procedure SetCovThreshold ;
------------------------------------------------------------
procedure SetCovTarget (Percent : real) is
------------------------------------------------------------
begin
SetCovTarget(COV_STRUCT_ID_DEFAULT, Percent) ;
end procedure SetCovTarget ;
------------------------------------------------------------
impure function GetCovTarget return real is
------------------------------------------------------------
begin
return GetCovTarget(COV_STRUCT_ID_DEFAULT) ;
end function GetCovTarget ;
------------------------------------------------------------
procedure SetMerging (A : boolean := TRUE ) is
------------------------------------------------------------
begin
SetMerging(COV_STRUCT_ID_DEFAULT, A) ;
end procedure SetMerging ;
------------------------------------------------------------
procedure SetCountMode (A : CountModeType) is
------------------------------------------------------------
begin
SetCountMode(COV_STRUCT_ID_DEFAULT, A) ;
end procedure SetCountMode ;
------------------------------------------------------------
procedure InitSeed (S : string ) is
------------------------------------------------------------
begin
InitSeed(COV_STRUCT_ID_DEFAULT, S, FALSE) ;
end procedure InitSeed ;
------------------------------------------------------------
impure function InitSeed (S : string ) return string is
------------------------------------------------------------
begin
return InitSeed(COV_STRUCT_ID_DEFAULT, S, FALSE) ;
end function InitSeed ;
------------------------------------------------------------
procedure InitSeed (I : integer ) is
------------------------------------------------------------
begin
InitSeed(COV_STRUCT_ID_DEFAULT, I, FALSE) ;
end procedure InitSeed ;
------------------------------------------------------------
procedure SetSeed (RandomSeedIn : RandomSeedType ) is
------------------------------------------------------------
begin
SetSeed(COV_STRUCT_ID_DEFAULT, RandomSeedIn) ;
end procedure SetSeed ;
------------------------------------------------------------
impure function GetSeed return RandomSeedType is
------------------------------------------------------------
begin
return GetSeed(COV_STRUCT_ID_DEFAULT) ;
end function GetSeed ;
------------------------------------------------------------
procedure SetBinSize (NewNumBins : integer) is
-- Sets a CovBin to a particular size
-- Use for small bins to save space or large bins to
-- suppress the resize and copy as a CovBin autosizes.
------------------------------------------------------------
begin
SetBinSize(COV_STRUCT_ID_DEFAULT, NewNumBins) ;
end procedure SetBinSize ;
------------------------------------------------------------
procedure AddBins (
------------------------------------------------------------
Name : String ;
AtLeast : integer ;
Weight : integer ;
CovBin : CovBinType
) is
begin
AddBins(COV_STRUCT_ID_DEFAULT, Name, AtLeast, Weight, CovBin) ;
end procedure AddBins ;
------------------------------------------------------------
procedure AddBins ( Name : String ; AtLeast : integer ; CovBin : CovBinType ) is
------------------------------------------------------------
begin
AddBins(Name, AtLeast, 1, CovBin) ;
end procedure AddBins ;
------------------------------------------------------------
procedure AddBins (Name : String ; CovBin : CovBinType) is
------------------------------------------------------------
begin
AddBins(Name, 1, 1, CovBin) ;
end procedure AddBins ;
------------------------------------------------------------
procedure AddBins ( AtLeast : integer ; Weight : integer ; CovBin : CovBinType ) is
------------------------------------------------------------
begin
AddBins("", AtLeast, Weight, CovBin) ;
end procedure AddBins ;
------------------------------------------------------------
procedure AddBins ( AtLeast : integer ; CovBin : CovBinType ) is
------------------------------------------------------------
begin
AddBins("", AtLeast, 1, CovBin) ;
end procedure AddBins ;
------------------------------------------------------------
procedure AddBins ( CovBin : CovBinType ) is
------------------------------------------------------------
begin
AddBins("", 1, 1, CovBin) ;
end procedure AddBins ;
------------------------------------------------------------
procedure AddCross(
------------------------------------------------------------
Name : string ;
AtLeast : integer ;
Weight : integer ;
Bin1, Bin2 : CovBinType ;
Bin3, Bin4, Bin5, Bin6, Bin7, Bin8, Bin9, Bin10, Bin11, Bin12, Bin13,
Bin14, Bin15, Bin16, Bin17, Bin18, Bin19, Bin20 : CovBinType := NULL_BIN
) is
begin
AddCross(COV_STRUCT_ID_DEFAULT, Name, AtLeast, Weight,
Bin1, Bin2, Bin3, Bin4, Bin5, Bin6, Bin7, Bin8, Bin9, Bin10,
Bin11, Bin12, Bin13, Bin14, Bin15, Bin16, Bin17, Bin18, Bin19, Bin20) ;
end procedure AddCross ;
------------------------------------------------------------
procedure AddCross(
------------------------------------------------------------
Name : string ;
AtLeast : integer ;
Bin1, Bin2 : CovBinType ;
Bin3, Bin4, Bin5, Bin6, Bin7, Bin8, Bin9, Bin10, Bin11, Bin12, Bin13,
Bin14, Bin15, Bin16, Bin17, Bin18, Bin19, Bin20 : CovBinType := NULL_BIN
) is
begin
AddCross(Name, AtLeast, 1,
Bin1, Bin2, Bin3, Bin4, Bin5, Bin6, Bin7, Bin8, Bin9, Bin10, Bin11,
Bin12, Bin13, Bin14, Bin15, Bin16, Bin17, Bin18, Bin19, Bin20
) ;
end procedure AddCross ;
------------------------------------------------------------
procedure AddCross(
------------------------------------------------------------
Name : string ;
Bin1, Bin2 : CovBinType ;
Bin3, Bin4, Bin5, Bin6, Bin7, Bin8, Bin9, Bin10, Bin11, Bin12, Bin13,
Bin14, Bin15, Bin16, Bin17, Bin18, Bin19, Bin20 : CovBinType := NULL_BIN
) is
begin
AddCross(Name, 1, 1,
Bin1, Bin2, Bin3, Bin4, Bin5, Bin6, Bin7, Bin8, Bin9, Bin10, Bin11,
Bin12, Bin13, Bin14, Bin15, Bin16, Bin17, Bin18, Bin19, Bin20
) ;
end procedure AddCross ;
------------------------------------------------------------
procedure AddCross(
------------------------------------------------------------
AtLeast : integer ;
Weight : integer ;
Bin1, Bin2 : CovBinType ;
Bin3, Bin4, Bin5, Bin6, Bin7, Bin8, Bin9, Bin10, Bin11, Bin12, Bin13,
Bin14, Bin15, Bin16, Bin17, Bin18, Bin19, Bin20 : CovBinType := NULL_BIN
) is
begin
AddCross("", AtLeast, Weight,
Bin1, Bin2, Bin3, Bin4, Bin5, Bin6, Bin7, Bin8, Bin9, Bin10, Bin11,
Bin12, Bin13, Bin14, Bin15, Bin16, Bin17, Bin18, Bin19, Bin20
) ;
end procedure AddCross ;
------------------------------------------------------------
procedure AddCross(
------------------------------------------------------------
AtLeast : integer ;
Bin1, Bin2 : CovBinType ;
Bin3, Bin4, Bin5, Bin6, Bin7, Bin8, Bin9, Bin10, Bin11, Bin12, Bin13,
Bin14, Bin15, Bin16, Bin17, Bin18, Bin19, Bin20 : CovBinType := NULL_BIN
) is
begin
AddCross("", AtLeast, 1,
Bin1, Bin2, Bin3, Bin4, Bin5, Bin6, Bin7, Bin8, Bin9, Bin10, Bin11,
Bin12, Bin13, Bin14, Bin15, Bin16, Bin17, Bin18, Bin19, Bin20
) ;
end procedure AddCross ;
------------------------------------------------------------
procedure AddCross(
------------------------------------------------------------
Bin1, Bin2 : CovBinType ;
Bin3, Bin4, Bin5, Bin6, Bin7, Bin8, Bin9, Bin10, Bin11, Bin12, Bin13,
Bin14, Bin15, Bin16, Bin17, Bin18, Bin19, Bin20 : CovBinType := NULL_BIN
) is
begin
AddCross("", 1, 1,
Bin1, Bin2, Bin3, Bin4, Bin5, Bin6, Bin7, Bin8, Bin9, Bin10, Bin11,
Bin12, Bin13, Bin14, Bin15, Bin16, Bin17, Bin18, Bin19, Bin20
) ;
end procedure AddCross ;
------------------------------------------------------------
procedure Deallocate is
------------------------------------------------------------
begin
ResetReportOptions ;
Deallocate(COV_STRUCT_ID_DEFAULT) ;
end procedure deallocate ;
------------------------------------------------------------
procedure ICoverLast is
------------------------------------------------------------
begin
ICoverLast(COV_STRUCT_ID_DEFAULT) ;
end procedure ICoverLast ;
------------------------------------------------------------
procedure ICover ( CovPoint : integer) is
------------------------------------------------------------
begin
ICover(COV_STRUCT_ID_DEFAULT, (1=> CovPoint)) ;
end procedure ICover ;
------------------------------------------------------------
procedure ICover( CovPoint : integer_vector) is
------------------------------------------------------------
begin
ICover(COV_STRUCT_ID_DEFAULT, CovPoint) ;
end procedure ICover ;
------------------------------------------------------------
procedure TCover ( A : integer) is
------------------------------------------------------------
begin
TCover(COV_STRUCT_ID_DEFAULT, A) ;
end procedure TCover ;
------------------------------------------------------------
procedure ClearCov is
------------------------------------------------------------
begin
ClearCov(COV_STRUCT_ID_DEFAULT) ;
end procedure ClearCov ;
------------------------------------------------------------
-- deprecated
procedure SetCovZero is
------------------------------------------------------------
begin
ClearCov(COV_STRUCT_ID_DEFAULT) ;
end procedure SetCovZero ;
------------------------------------------------------------
impure function IsInitialized return boolean is
------------------------------------------------------------
begin
return IsInitialized(COV_STRUCT_ID_DEFAULT) ;
end function IsInitialized ;
------------------------------------------------------------
impure function GetMinCov return real is
------------------------------------------------------------
begin
return GetMinCov(COV_STRUCT_ID_DEFAULT) ;
end function GetMinCov ;
------------------------------------------------------------
impure function GetMinCount return integer is
------------------------------------------------------------
begin
return GetMinCount (COV_STRUCT_ID_DEFAULT);
end function GetMinCount ;
------------------------------------------------------------
impure function GetMaxCov return real is
------------------------------------------------------------
begin
return GetMaxCov(COV_STRUCT_ID_DEFAULT) ;
end function GetMaxCov ;
------------------------------------------------------------
impure function GetMaxCount return integer is
------------------------------------------------------------
begin
return GetMaxCount(COV_STRUCT_ID_DEFAULT);
end function GetMaxCount ;
------------------------------------------------------------
impure function CountCovHoles ( PercentCov : real ) return integer is
------------------------------------------------------------
begin
return CountCovHoles(COV_STRUCT_ID_DEFAULT, PercentCov) ;
end function CountCovHoles ;
------------------------------------------------------------
impure function CountCovHoles return integer is
------------------------------------------------------------
begin
return CountCovHoles(COV_STRUCT_ID_DEFAULT) ;
end function CountCovHoles ;
------------------------------------------------------------
impure function IsCovered ( PercentCov : real ) return boolean is
------------------------------------------------------------
begin
return IsCovered(COV_STRUCT_ID_DEFAULT, PercentCov) ;
end function IsCovered ;
------------------------------------------------------------
impure function IsCovered return boolean is
------------------------------------------------------------
begin
return IsCovered(COV_STRUCT_ID_DEFAULT) ;
end function IsCovered ;
------------------------------------------------------------
impure function GetCov ( PercentCov : real ) return real is
------------------------------------------------------------
begin
return GetCov(COV_STRUCT_ID_DEFAULT, PercentCov) ;
end function GetCov ;
------------------------------------------------------------
impure function GetCov return real is
------------------------------------------------------------
begin
return GetCov(COV_STRUCT_ID_DEFAULT ) ;
end function GetCov ;
------------------------------------------------------------
impure function GetItemCount return integer is
------------------------------------------------------------
begin
return GetItemCount(COV_STRUCT_ID_DEFAULT) ;
end function GetItemCount ;
------------------------------------------------------------
impure function GetTotalCovCount ( PercentCov : real ) return integer is
------------------------------------------------------------
begin
return GetTotalCovCount(COV_STRUCT_ID_DEFAULT, PercentCov) ;
end function GetTotalCovCount ;
------------------------------------------------------------
impure function GetTotalCovCount return integer is
------------------------------------------------------------
begin
return GetTotalCovCount(COV_STRUCT_ID_DEFAULT) ;
end function GetTotalCovCount ;
------------------------------------------------------------
impure function GetTotalCovGoal ( PercentCov : real ) return integer is
------------------------------------------------------------
begin
return GetTotalCovGoal(COV_STRUCT_ID_DEFAULT, PercentCov) ;
end function GetTotalCovGoal ;
------------------------------------------------------------
impure function GetTotalCovGoal return integer is
------------------------------------------------------------
begin
return GetTotalCovGoal(COV_STRUCT_ID_DEFAULT) ;
end function GetTotalCovGoal ;
-- Return Index Values
------------------------------------------------------------
impure function GetNumBins return integer is
------------------------------------------------------------
begin
return GetNumBins(COV_STRUCT_ID_DEFAULT) ;
end function GetNumBins ;
------------------------------------------------------------
impure function GetLastIndex return integer is
------------------------------------------------------------
begin
return GetLastIndex(COV_STRUCT_ID_DEFAULT) ;
end function GetLastIndex ;
------------------------------------------------------------
impure function GetRandIndex ( CovTargetPercent : real ) return integer is
------------------------------------------------------------
begin
return GetRandIndex(COV_STRUCT_ID_DEFAULT, CovTargetPercent) ;
end function GetRandIndex ;
------------------------------------------------------------
impure function GetRandIndex return integer is
------------------------------------------------------------
begin
return GetRandIndex(COV_STRUCT_ID_DEFAULT) ;
end function GetRandIndex ;
------------------------------------------------------------
impure function GetIncIndex return integer is
------------------------------------------------------------
begin
return GetIncIndex(COV_STRUCT_ID_DEFAULT) ;
end function GetIncIndex ;
------------------------------------------------------------
impure function GetMinIndex return integer is
------------------------------------------------------------
begin
return GetMinIndex(COV_STRUCT_ID_DEFAULT) ;
end function GetMinIndex ;
------------------------------------------------------------
impure function GetMaxIndex return integer is
------------------------------------------------------------
begin
return GetMaxIndex(COV_STRUCT_ID_DEFAULT) ;
end function GetMaxIndex ;
------------------------------------------------------------
impure function GetNextIndex (Mode : NextPointModeType) return integer is
------------------------------------------------------------
begin
return GetNextIndex(COV_STRUCT_ID_DEFAULT, Mode) ;
end function GetNextIndex;
------------------------------------------------------------
impure function GetNextIndex return integer is
------------------------------------------------------------
begin
return GetNextIndex(COV_STRUCT_ID_DEFAULT) ;
end function GetNextIndex ;
-- Return BinVals
------------------------------------------------------------
impure function GetBinVal ( BinIndex : integer ) return RangeArrayType is
------------------------------------------------------------
begin
return GetBinVal(COV_STRUCT_ID_DEFAULT, BinIndex ) ;
end function GetBinVal ;
------------------------------------------------------------
impure function GetLastBinVal return RangeArrayType is
------------------------------------------------------------
begin
return GetLastBinVal(COV_STRUCT_ID_DEFAULT) ;
end function GetLastBinVal ;
------------------------------------------------------------
impure function GetRandBinVal ( PercentCov : real ) return RangeArrayType is
------------------------------------------------------------
begin
return GetRandBinVal(COV_STRUCT_ID_DEFAULT, PercentCov) ; -- GetBinVal
end function GetRandBinVal ;
------------------------------------------------------------
impure function GetRandBinVal return RangeArrayType is
------------------------------------------------------------
begin
-- use global coverage target
return GetRandBinVal(COV_STRUCT_ID_DEFAULT) ; -- GetBinVal
end function GetRandBinVal ;
------------------------------------------------------------
impure function GetIncBinVal return RangeArrayType is
------------------------------------------------------------
begin
return GetIncBinVal( COV_STRUCT_ID_DEFAULT ) ;
end function GetIncBinVal ;
------------------------------------------------------------
impure function GetMinBinVal return RangeArrayType is
------------------------------------------------------------
begin
-- use global coverage target
return GetMinBinVal( COV_STRUCT_ID_DEFAULT ) ;
end function GetMinBinVal ;
------------------------------------------------------------
impure function GetMaxBinVal return RangeArrayType is
------------------------------------------------------------
begin
-- use global coverage target
return GetMaxBinVal( COV_STRUCT_ID_DEFAULT ) ;
end function GetMaxBinVal ;
------------------------------------------------------------
impure function GetNextBinVal (Mode : NextPointModeType) return RangeArrayType is
------------------------------------------------------------
begin
return GetNextBinVal (COV_STRUCT_ID_DEFAULT, Mode) ;
end function GetNextBinVal;
------------------------------------------------------------
impure function GetNextBinVal return RangeArrayType is
------------------------------------------------------------
begin
return GetNextBinVal (COV_STRUCT_ID_DEFAULT) ;
end function GetNextBinVal ;
------------------------------------------------------------
-- deprecated, see GetRandBinVal
impure function RandCovBinVal ( PercentCov : real ) return RangeArrayType is
------------------------------------------------------------
begin
return GetRandBinVal(COV_STRUCT_ID_DEFAULT, PercentCov) ; -- GetBinVal
end function RandCovBinVal ;
------------------------------------------------------------
-- deprecated, see GetRandBinVal
impure function RandCovBinVal return RangeArrayType is
------------------------------------------------------------
begin
return GetRandBinVal(COV_STRUCT_ID_DEFAULT) ; -- GetBinVal
end function RandCovBinVal ;
------------------------------------------------------------
impure function GetHoleBinVal ( ReqHoleNum : integer ; PercentCov : real ) return RangeArrayType is
------------------------------------------------------------
begin
return GetHoleBinVal(COV_STRUCT_ID_DEFAULT, ReqHoleNum, PercentCov) ;
end function GetHoleBinVal ;
------------------------------------------------------------
impure function GetHoleBinVal ( PercentCov : real ) return RangeArrayType is
------------------------------------------------------------
begin
return GetHoleBinVal(COV_STRUCT_ID_DEFAULT, 1, PercentCov) ;
end function GetHoleBinVal ;
------------------------------------------------------------
impure function GetHoleBinVal ( ReqHoleNum : integer := 1 ) return RangeArrayType is
------------------------------------------------------------
begin
return GetHoleBinVal(COV_STRUCT_ID_DEFAULT, ReqHoleNum) ;
end function GetHoleBinVal ;
------------------------------------------------------------
impure function GetPoint ( BinIndex : integer ) return integer is
------------------------------------------------------------
begin
return GetPoint(COV_STRUCT_ID_DEFAULT, BinIndex) ;
end function GetPoint ;
------------------------------------------------------------
impure function GetPoint ( BinIndex : integer ) return integer_vector is
------------------------------------------------------------
begin
return GetPoint(COV_STRUCT_ID_DEFAULT, BinIndex) ;
end function GetPoint ;
------------------------------------------------------------
impure function GetRandPoint return integer is
------------------------------------------------------------
begin
return GetRandPoint(COV_STRUCT_ID_DEFAULT) ;
end function GetRandPoint ;
------------------------------------------------------------
impure function GetRandPoint ( PercentCov : real ) return integer is
------------------------------------------------------------
begin
return GetRandPoint(COV_STRUCT_ID_DEFAULT, PercentCov) ;
end function GetRandPoint ;
------------------------------------------------------------
impure function GetRandPoint return integer_vector is
------------------------------------------------------------
begin
return GetRandPoint(COV_STRUCT_ID_DEFAULT) ;
end function GetRandPoint ;
------------------------------------------------------------
impure function GetRandPoint ( PercentCov : real ) return integer_vector is
------------------------------------------------------------
begin
return GetRandPoint(COV_STRUCT_ID_DEFAULT, PercentCov) ;
end function GetRandPoint ;
------------------------------------------------------------
impure function GetIncPoint return integer is
------------------------------------------------------------
begin
return GetIncPoint(COV_STRUCT_ID_DEFAULT) ;
end function GetIncPoint ;
------------------------------------------------------------
impure function GetIncPoint return integer_vector is
------------------------------------------------------------
begin
return GetIncPoint(COV_STRUCT_ID_DEFAULT) ;
end function GetIncPoint ;
------------------------------------------------------------
impure function GetMinPoint return integer is
------------------------------------------------------------
begin
return GetMinPoint(COV_STRUCT_ID_DEFAULT) ;
end function GetMinPoint ;
------------------------------------------------------------
impure function GetMinPoint return integer_vector is
------------------------------------------------------------
begin
return GetMinPoint(COV_STRUCT_ID_DEFAULT) ;
end function GetMinPoint ;
------------------------------------------------------------
impure function GetMaxPoint return integer is
------------------------------------------------------------
begin
return GetMaxPoint(COV_STRUCT_ID_DEFAULT) ;
end function GetMaxPoint ;
------------------------------------------------------------
impure function GetMaxPoint return integer_vector is
------------------------------------------------------------
begin
return GetMaxPoint(COV_STRUCT_ID_DEFAULT) ;
end function GetMaxPoint ;
------------------------------------------------------------
impure function GetNextPoint (Mode : NextPointModeType) return integer is
------------------------------------------------------------
begin
return GetNextPoint(COV_STRUCT_ID_DEFAULT, Mode) ;
end function GetNextPoint;
------------------------------------------------------------
impure function GetNextPoint (Mode : NextPointModeType) return integer_vector is
------------------------------------------------------------
begin
return GetNextPoint(COV_STRUCT_ID_DEFAULT, Mode) ;
end function GetNextPoint;
------------------------------------------------------------
impure function GetNextPoint return integer is
------------------------------------------------------------
begin
return GetNextPoint(COV_STRUCT_ID_DEFAULT) ;
end function GetNextPoint ;
------------------------------------------------------------
impure function GetNextPoint return integer_vector is
------------------------------------------------------------
begin
return GetNextPoint(COV_STRUCT_ID_DEFAULT) ;
end function GetNextPoint ;
------------------------------------------------------------
-- deprecated, see GetRandPoint
impure function RandCovPoint return integer is
------------------------------------------------------------
begin
return GetRandPoint(COV_STRUCT_ID_DEFAULT) ;
end function RandCovPoint ;
------------------------------------------------------------
-- deprecated, see GetRandPoint
impure function RandCovPoint ( PercentCov : real ) return integer is
------------------------------------------------------------
begin
return GetRandPoint(COV_STRUCT_ID_DEFAULT, PercentCov) ;
end function RandCovPoint ;
------------------------------------------------------------
-- deprecated, see GetRandPoint
impure function RandCovPoint return integer_vector is
------------------------------------------------------------
begin
return GetRandPoint(COV_STRUCT_ID_DEFAULT) ;
end function RandCovPoint ;
------------------------------------------------------------
-- deprecated, see GetRandPoint
impure function RandCovPoint ( PercentCov : real ) return integer_vector is
------------------------------------------------------------
begin
return GetRandPoint(COV_STRUCT_ID_DEFAULT, PercentCov) ;
end function RandCovPoint ;
-- ------------------------------------------------------------
-- Intended as a stand in until we get a more general GetBin
impure function GetBinInfo ( BinIndex : integer ) return CovBinBaseType is
-- ------------------------------------------------------------
begin
return GetBinInfo(COV_STRUCT_ID_DEFAULT, BinIndex) ;
end function GetBinInfo ;
-- ------------------------------------------------------------
-- Intended as a stand in until we get a more general GetBin
impure function GetBinValLength return integer is
-- ------------------------------------------------------------
begin
return GetBinValLength(COV_STRUCT_ID_DEFAULT) ;
end function GetBinValLength ;
-- Eventually the multiple GetBin functions will be replaced by a
-- a single GetBin that returns CovBinBaseType with BinVal as an
-- unconstrained element
-- ------------------------------------------------------------
impure function GetBin ( BinIndex : integer ) return CovBinBaseType is
-- ------------------------------------------------------------
begin
return GetBin(COV_STRUCT_ID_DEFAULT, BinIndex) ;
end function GetBin ;
-- ------------------------------------------------------------
impure function GetBin ( BinIndex : integer ) return CovMatrix2BaseType is
-- ------------------------------------------------------------
begin
return GetBin(COV_STRUCT_ID_DEFAULT, BinIndex) ;
end function GetBin ;
-- ------------------------------------------------------------
impure function GetBin ( BinIndex : integer ) return CovMatrix3BaseType is
-- ------------------------------------------------------------
begin
return GetBin(COV_STRUCT_ID_DEFAULT, BinIndex) ;
end function GetBin ;
-- ------------------------------------------------------------
impure function GetBin ( BinIndex : integer ) return CovMatrix4BaseType is
-- ------------------------------------------------------------
begin
return GetBin(COV_STRUCT_ID_DEFAULT, BinIndex) ;
end function GetBin ;
-- ------------------------------------------------------------
impure function GetBin ( BinIndex : integer ) return CovMatrix5BaseType is
-- ------------------------------------------------------------
begin
return GetBin(COV_STRUCT_ID_DEFAULT, BinIndex) ;
end function GetBin ;
-- ------------------------------------------------------------
impure function GetBin ( BinIndex : integer ) return CovMatrix6BaseType is
-- ------------------------------------------------------------
begin
return GetBin(COV_STRUCT_ID_DEFAULT, BinIndex) ;
end function GetBin ;
-- ------------------------------------------------------------
impure function GetBin ( BinIndex : integer ) return CovMatrix7BaseType is
-- ------------------------------------------------------------
begin
return GetBin(COV_STRUCT_ID_DEFAULT, BinIndex) ;
end function GetBin ;
-- ------------------------------------------------------------
impure function GetBin ( BinIndex : integer ) return CovMatrix8BaseType is
-- ------------------------------------------------------------
begin
return GetBin(COV_STRUCT_ID_DEFAULT, BinIndex) ;
end function GetBin ;
-- ------------------------------------------------------------
impure function GetBin ( BinIndex : integer ) return CovMatrix9BaseType is
-- ------------------------------------------------------------
begin
return GetBin(COV_STRUCT_ID_DEFAULT, BinIndex) ;
end function GetBin ;
-- ------------------------------------------------------------
impure function GetBinName ( BinIndex : integer; DefaultName : string := "" ) return string is
-- ------------------------------------------------------------
begin
return GetBinName(COV_STRUCT_ID_DEFAULT, BinIndex, DefaultName) ;
end function GetBinName;
------------------------------------------------------------
procedure WriteBin (
------------------------------------------------------------
WritePassFail : OsvvmOptionsType := COV_OPT_INIT_PARM_DETECT ;
WriteBinInfo : OsvvmOptionsType := COV_OPT_INIT_PARM_DETECT ;
WriteCount : OsvvmOptionsType := COV_OPT_INIT_PARM_DETECT ;
WriteAnyIllegal : OsvvmOptionsType := COV_OPT_INIT_PARM_DETECT ;
WritePrefix : string := OSVVM_STRING_INIT_PARM_DETECT ;
PassName : string := OSVVM_STRING_INIT_PARM_DETECT ;
FailName : string := OSVVM_STRING_INIT_PARM_DETECT
) is
constant rWritePassFail : OsvvmOptionsType := ResolveCovWritePassFail (WritePassFail, WritePassFailVar) ;
constant rWriteBinInfo : OsvvmOptionsType := ResolveCovWriteBinInfo (WriteBinInfo, WriteBinInfoVar ) ;
constant rWriteCount : OsvvmOptionsType := ResolveCovWriteCount (WriteCount, WriteCountVar ) ;
constant rWriteAnyIllegal : OsvvmOptionsType := ResolveCovWriteAnyIllegal(WriteAnyIllegal, WriteAnyIllegalVar) ;
-- constant rWritePrefix : string := ResolveOsvvmWritePrefix (WritePrefix, WritePrefixVar.GetOpt) ;
-- constant rPassName : string := ResolveOsvvmPassName (PassName, PassNameVar.GetOpt ) ;
-- constant rFailName : string := ResolveOsvvmFailName (FailName, FailNameVar.GetOpt ) ;
variable buf, buf2 : line ;
begin
WriteBin (
ID => COV_STRUCT_ID_DEFAULT,
buf => buf,
WritePassFail => rWritePassFail,
WriteBinInfo => rWriteBinInfo,
WriteCount => rWriteCount,
WriteAnyIllegal => rWriteAnyIllegal,
-- WritePrefix => rWritePrefix,
WritePrefix => ResolveOsvvmWritePrefix (WritePrefix, WritePrefixVar.GetOpt),
-- PassName => rPassName,
PassName => ResolveOsvvmPassName (PassName, PassNameVar.GetOpt ),
-- FailName => rFailName
FailName => ResolveOsvvmFailName (FailName, FailNameVar.GetOpt )
) ;
WriteToCovFile(buf) ;
end procedure WriteBin ;
------------------------------------------------------------
-- Deprecated
procedure WriteBin ( -- With LogLevel
------------------------------------------------------------
LogLevel : LogType ;
WritePassFail : OsvvmOptionsType := COV_OPT_INIT_PARM_DETECT ;
WriteBinInfo : OsvvmOptionsType := COV_OPT_INIT_PARM_DETECT ;
WriteCount : OsvvmOptionsType := COV_OPT_INIT_PARM_DETECT ;
WriteAnyIllegal : OsvvmOptionsType := COV_OPT_INIT_PARM_DETECT ;
WritePrefix : string := OSVVM_STRING_INIT_PARM_DETECT ;
PassName : string := OSVVM_STRING_INIT_PARM_DETECT ;
FailName : string := OSVVM_STRING_INIT_PARM_DETECT
) is
begin
if IsLogEnabled(CovStructPtr(COV_STRUCT_ID_DEFAULT.ID).AlertLogID, LogLevel) then
WriteBin (
WritePassFail => WritePassFail,
WriteBinInfo => WriteBinInfo,
WriteCount => WriteCount,
WriteAnyIllegal => WriteAnyIllegal,
WritePrefix => WritePrefix,
PassName => PassName,
FailName => FailName
) ;
end if ;
end procedure WriteBin ; -- With LogLevel
------------------------------------------------------------
procedure WriteBin (
------------------------------------------------------------
FileName : string;
OpenKind : File_Open_Kind := APPEND_MODE ;
WritePassFail : OsvvmOptionsType := COV_OPT_INIT_PARM_DETECT ;
WriteBinInfo : OsvvmOptionsType := COV_OPT_INIT_PARM_DETECT ;
WriteCount : OsvvmOptionsType := COV_OPT_INIT_PARM_DETECT ;
WriteAnyIllegal : OsvvmOptionsType := COV_OPT_INIT_PARM_DETECT ;
WritePrefix : string := OSVVM_STRING_INIT_PARM_DETECT ;
PassName : string := OSVVM_STRING_INIT_PARM_DETECT ;
FailName : string := OSVVM_STRING_INIT_PARM_DETECT
) is
file LocalWriteBinFile : text open OpenKind is FileName ;
constant rWritePassFail : OsvvmOptionsType := ResolveCovWritePassFail (WritePassFail, WritePassFailVar) ;
constant rWriteBinInfo : OsvvmOptionsType := ResolveCovWriteBinInfo (WriteBinInfo, WriteBinInfoVar ) ;
constant rWriteCount : OsvvmOptionsType := ResolveCovWriteCount (WriteCount, WriteCountVar ) ;
constant rWriteAnyIllegal : OsvvmOptionsType := ResolveCovWriteAnyIllegal (WriteAnyIllegal, WriteAnyIllegalVar) ;
-- constant rWritePrefix : string := ResolveOsvvmWritePrefix (WritePrefix, WritePrefixVar.GetOpt) ;
-- constant rPassName : string := ResolveOsvvmPassName (PassName, PassNameVar.GetOpt ) ;
-- constant rFailName : string := ResolveOsvvmFailName (FailName, FailNameVar.GetOpt ) ;
variable buf : line ;
begin
WriteBin (
ID => COV_STRUCT_ID_DEFAULT,
buf => buf,
WritePassFail => rWritePassFail,
WriteBinInfo => rWriteBinInfo,
WriteCount => rWriteCount,
WriteAnyIllegal => rWriteAnyIllegal,
-- WritePrefix => rWritePrefix,
WritePrefix => ResolveOsvvmWritePrefix (WritePrefix, WritePrefixVar.GetOpt),
-- PassName => rPassName,
PassName => ResolveOsvvmPassName (PassName, PassNameVar.GetOpt ),
-- FailName => rFailName
FailName => ResolveOsvvmFailName (FailName, FailNameVar.GetOpt ),
UsingLocalFile => TRUE
);
writeline(LocalWriteBinFile, buf) ;
end procedure WriteBin ;
------------------------------------------------------------
procedure WriteBin ( -- With LogLevel
------------------------------------------------------------
LogLevel : LogType ;
FileName : string;
OpenKind : File_Open_Kind := APPEND_MODE ;
WritePassFail : OsvvmOptionsType := COV_OPT_INIT_PARM_DETECT ;
WriteBinInfo : OsvvmOptionsType := COV_OPT_INIT_PARM_DETECT ;
WriteCount : OsvvmOptionsType := COV_OPT_INIT_PARM_DETECT ;
WriteAnyIllegal : OsvvmOptionsType := COV_OPT_INIT_PARM_DETECT ;
WritePrefix : string := OSVVM_STRING_INIT_PARM_DETECT ;
PassName : string := OSVVM_STRING_INIT_PARM_DETECT ;
FailName : string := OSVVM_STRING_INIT_PARM_DETECT
) is
begin
if IsLogEnabled(CovStructPtr(COV_STRUCT_ID_DEFAULT.ID).AlertLogID, LogLevel) then
WriteBin (
FileName => FileName,
OpenKind => OpenKind,
WritePassFail => WritePassFail,
WriteBinInfo => WriteBinInfo,
WriteCount => WriteCount,
WriteAnyIllegal => WriteAnyIllegal,
WritePrefix => WritePrefix,
PassName => PassName,
FailName => FailName
) ;
end if ;
end procedure WriteBin ; -- With LogLevel
------------------------------------------------------------
procedure DumpBin (LogLevel : LogType := DEBUG) is
------------------------------------------------------------
begin
DumpBin (COV_STRUCT_ID_DEFAULT, LogLevel) ;
end procedure DumpBin ;
------------------------------------------------------------
procedure WriteCovHoles ( PercentCov : real ) is
------------------------------------------------------------
begin
WriteCovHoles(COV_STRUCT_ID_DEFAULT, PercentCov) ;
end procedure WriteCovHoles ;
------------------------------------------------------------
procedure WriteCovHoles ( LogLevel : LogType := ALWAYS ) is
------------------------------------------------------------
begin
WriteCovHoles(COV_STRUCT_ID_DEFAULT, LogLevel) ;
end procedure WriteCovHoles ;
------------------------------------------------------------
procedure WriteCovHoles ( LogLevel : LogType ; PercentCov : real ) is
------------------------------------------------------------
begin
WriteCovHoles(COV_STRUCT_ID_DEFAULT, LogLevel, PercentCov) ;
end procedure WriteCovHoles ;
------------------------------------------------------------
procedure WriteCovHoles ( FileName : string; OpenKind : File_Open_Kind := APPEND_MODE ) is
------------------------------------------------------------
begin
WriteCovHoles(COV_STRUCT_ID_DEFAULT, FileName, OpenKind) ;
end procedure WriteCovHoles ;
------------------------------------------------------------
procedure WriteCovHoles ( LogLevel : LogType ; FileName : string; OpenKind : File_Open_Kind := APPEND_MODE ) is
------------------------------------------------------------
begin
WriteCovHoles(COV_STRUCT_ID_DEFAULT, LogLevel, FileName, OpenKind) ;
end procedure WriteCovHoles ;
------------------------------------------------------------
procedure WriteCovHoles ( FileName : string; PercentCov : real ; OpenKind : File_Open_Kind := APPEND_MODE ) is
------------------------------------------------------------
begin
WriteCovHoles(COV_STRUCT_ID_DEFAULT, FileName, PercentCov, OpenKind) ;
end procedure WriteCovHoles ;
------------------------------------------------------------
procedure WriteCovHoles ( LogLevel : LogType ; FileName : string; PercentCov : real ; OpenKind : File_Open_Kind := APPEND_MODE ) is
------------------------------------------------------------
begin
WriteCovHoles(COV_STRUCT_ID_DEFAULT, LogLevel, FileName, PercentCov, OpenKind) ;
end procedure WriteCovHoles ;
------------------------------------------------------------
procedure ReadCovDb (FileName : string; Merge : boolean := FALSE) is
------------------------------------------------------------
begin
ReadCovDb(COV_STRUCT_ID_DEFAULT, FileName, Merge) ;
end procedure ReadCovDb ;
------------------------------------------------------------
procedure WriteCovDb (FileName : string; OpenKind : File_Open_Kind := WRITE_MODE ) is
------------------------------------------------------------
begin
WriteCovDb (COV_STRUCT_ID_DEFAULT, FileName, OpenKind) ;
end procedure WriteCovDb ;
------------------------------------------------------------
impure function GetErrorCount return integer is
------------------------------------------------------------
begin
return GetErrorCount(COV_STRUCT_ID_DEFAULT) ;
end function GetErrorCount ;
------------------------------------------------------------
-- These support usage of cross coverage constants
-- Also support the older AddCross(GenCross(...)) methodology
-- which has been replaced by AddCross
------------------------------------------------------------
procedure AddCross (CovBin : CovMatrix2Type ; Name : String := "") is
------------------------------------------------------------
begin
AddCross(COV_STRUCT_ID_DEFAULT, CovBin, Name) ;
end procedure AddCross ;
------------------------------------------------------------
procedure AddCross (CovBin : CovMatrix3Type ; Name : String := "") is
------------------------------------------------------------
begin
AddCross(COV_STRUCT_ID_DEFAULT, CovBin, Name) ;
end procedure AddCross ;
------------------------------------------------------------
procedure AddCross (CovBin : CovMatrix4Type ; Name : String := "") is
------------------------------------------------------------
begin
AddCross(COV_STRUCT_ID_DEFAULT, CovBin, Name) ;
end procedure AddCross ;
------------------------------------------------------------
procedure AddCross (CovBin : CovMatrix5Type ; Name : String := "") is
------------------------------------------------------------
begin
AddCross(COV_STRUCT_ID_DEFAULT, CovBin, Name) ;
end procedure AddCross ;
------------------------------------------------------------
procedure AddCross (CovBin : CovMatrix6Type ; Name : String := "") is
------------------------------------------------------------
begin
AddCross(COV_STRUCT_ID_DEFAULT, CovBin, Name) ;
end procedure AddCross ;
------------------------------------------------------------
procedure AddCross (CovBin : CovMatrix7Type ; Name : String := "") is
------------------------------------------------------------
begin
AddCross(COV_STRUCT_ID_DEFAULT, CovBin, Name) ;
end procedure AddCross ;
------------------------------------------------------------
procedure AddCross (CovBin : CovMatrix8Type ; Name : String := "") is
------------------------------------------------------------
begin
AddCross(COV_STRUCT_ID_DEFAULT, CovBin, Name) ;
end procedure AddCross ;
------------------------------------------------------------
procedure AddCross (CovBin : CovMatrix9Type ; Name : String := "") is
------------------------------------------------------------
begin
AddCross(COV_STRUCT_ID_DEFAULT, CovBin, Name) ;
end procedure AddCross ;
-- ------------------------------------------------------------
-- ------------------------------------------------------------
-- Deprecated / Subsumed by versions with PercentCov Parameter
-- Maintained for backward compatibility only and
-- may be removed in the future.
-- ------------------------------------------------------------
------------------------------------------------------------
-- Deprecated. New versions use PercentCov
impure function CountCovHoles ( AtLeast : integer ) return integer is
------------------------------------------------------------
begin
return CountCovHoles (COV_STRUCT_ID_DEFAULT, AtLeast) ;
end function CountCovHoles ;
------------------------------------------------------------
-- Deprecated. New versions use PercentCov
impure function IsCovered ( AtLeast : integer ) return boolean is
------------------------------------------------------------
begin
return IsCovered(COV_STRUCT_ID_DEFAULT, AtLeast) ;
end function IsCovered ;
------------------------------------------------------------
-- Deprecated. New versions use PercentCov
impure function RandCovBinVal (AtLeast : integer ) return RangeArrayType is
------------------------------------------------------------
begin
return RandCovBinVal(COV_STRUCT_ID_DEFAULT, AtLeast) ;
end function RandCovBinVal ;
-- Maintained for backward compatibility. Repeated until aliases work for methods
------------------------------------------------------------
-- Deprecated+ New versions use PercentCov. Name change.
impure function RandCovHole (AtLeast : integer ) return RangeArrayType is
------------------------------------------------------------
begin
return RandCovHole(COV_STRUCT_ID_DEFAULT, AtLeast) ;
end function RandCovHole ;
------------------------------------------------------------
-- Deprecated. New versions use PercentCov
impure function RandCovPoint (AtLeast : integer ) return integer is
------------------------------------------------------------
begin
return RandCovPoint(COV_STRUCT_ID_DEFAULT, AtLeast) ;
end function RandCovPoint ;
------------------------------------------------------------
impure function RandCovPoint (AtLeast : integer ) return integer_vector is
------------------------------------------------------------
begin
return RandCovPoint(COV_STRUCT_ID_DEFAULT, AtLeast) ;
end function RandCovPoint ;
------------------------------------------------------------
-- Deprecated. New versions use PercentCov
impure function GetHoleBinVal ( ReqHoleNum : integer ; AtLeast : integer ) return RangeArrayType is
------------------------------------------------------------
begin
return GetHoleBinVal (COV_STRUCT_ID_DEFAULT, ReqHoleNum, AtLeast) ;
end function GetHoleBinVal ;
------------------------------------------------------------
-- Deprecated+. New versions use PercentCov. Name Change.
impure function GetCovHole ( ReqHoleNum : integer ; AtLeast : integer ) return RangeArrayType is
------------------------------------------------------------
begin
return GetCovHole(COV_STRUCT_ID_DEFAULT, ReqHoleNum, AtLeast) ;
end function GetCovHole ;
------------------------------------------------------------
-- Deprecated. New versions use PercentCov.
procedure WriteCovHoles ( AtLeast : integer ) is
------------------------------------------------------------
begin
WriteCovHoles(COV_STRUCT_ID_DEFAULT, AtLeast) ;
end procedure WriteCovHoles ;
------------------------------------------------------------
-- Deprecated. New versions use PercentCov.
procedure WriteCovHoles ( LogLevel : LogType ; AtLeast : integer ) is
------------------------------------------------------------
begin
WriteCovHoles(COV_STRUCT_ID_DEFAULT, LogLevel, AtLeast) ;
end procedure WriteCovHoles ;
------------------------------------------------------------
-- Deprecated. New versions use PercentCov.
procedure WriteCovHoles ( FileName : string; AtLeast : integer ; OpenKind : File_Open_Kind := APPEND_MODE ) is
------------------------------------------------------------
begin
WriteCovHoles(COV_STRUCT_ID_DEFAULT, FileName, AtLeast, OpenKind) ;
end procedure WriteCovHoles ;
------------------------------------------------------------
-- Deprecated. New versions use PercentCov.
procedure WriteCovHoles ( LogLevel : LogType ; FileName : string; AtLeast : integer ; OpenKind : File_Open_Kind := APPEND_MODE ) is
------------------------------------------------------------
begin
WriteCovHoles(COV_STRUCT_ID_DEFAULT, LogLevel, FileName, AtLeast, OpenKind) ;
end procedure WriteCovHoles ;
--------------------------------------------------------------
--------------------------------------------------------------
-- Deprecated. Due to name changes to promote greater consistency
-- Maintained for backward compatibility - but only for PT version
-- Not available in Data Structure
-- ------------------------------------------------------------
------------------------------------------------------------
impure function CovBinErrCnt return integer is
-- Deprecated. Name changed to ErrorCount for package to package consistency
------------------------------------------------------------
begin
return GetErrorCount(COV_STRUCT_ID_DEFAULT) ;
end function CovBinErrCnt ;
------------------------------------------------------------
-- Deprecated. Same as RandCovBinVal
impure function RandCovHole ( PercentCov : real ) return RangeArrayType is
------------------------------------------------------------
begin
return RandCovBinVal(COV_STRUCT_ID_DEFAULT, PercentCov) ;
end function RandCovHole ;
------------------------------------------------------------
-- Deprecated. Same as RandCovBinVal
impure function RandCovHole return RangeArrayType is
------------------------------------------------------------
begin
return RandCovBinVal(COV_STRUCT_ID_DEFAULT) ;
end function RandCovHole ;
-- GetCovHole replaced by GetHoleBinVal
------------------------------------------------------------
-- Deprecated. Same as GetHoleBinVal
impure function GetCovHole ( ReqHoleNum : integer ; PercentCov : real ) return RangeArrayType is
------------------------------------------------------------
begin
return GetHoleBinVal(COV_STRUCT_ID_DEFAULT, ReqHoleNum, PercentCov) ;
end function GetCovHole ;
------------------------------------------------------------
-- Deprecated. Same as GetHoleBinVal
impure function GetCovHole ( PercentCov : real ) return RangeArrayType is
------------------------------------------------------------
begin
return GetHoleBinVal(COV_STRUCT_ID_DEFAULT, PercentCov) ;
end function GetCovHole ;
------------------------------------------------------------
-- Deprecated. Same as GetHoleBinVal
impure function GetCovHole ( ReqHoleNum : integer := 1 ) return RangeArrayType is
------------------------------------------------------------
begin
return GetHoleBinVal(COV_STRUCT_ID_DEFAULT, ReqHoleNum) ;
end function GetCovHole ;
------------------------------------------------------------
-- Deprecated. Replaced by SetMessage with multi-line support
procedure SetItemName (ItemNameIn : String) is
------------------------------------------------------------
begin
SetMessage(COV_STRUCT_ID_DEFAULT, ItemNameIn) ;
end procedure SetItemName ;
------------------------------------------------------------
-- Deprecated. Same as GetMinCount
impure function GetMinCov return integer is
------------------------------------------------------------
begin
return GetMinCount(COV_STRUCT_ID_DEFAULT) ;
end function GetMinCov ;
------------------------------------------------------------
-- Deprecated. Same as GetMaxCount
impure function GetMaxCov return integer is
------------------------------------------------------------
begin
return GetMaxCount(COV_STRUCT_ID_DEFAULT) ;
end function GetMaxCov ;
------------------------------------------------------------
-- Deprecated. Use AddCross Instead.
procedure AddBins (CovBin : CovMatrix2Type ; Name : String := "") is
------------------------------------------------------------
begin
AddCross(COV_STRUCT_ID_DEFAULT, CovBin, Name) ;
end procedure AddBins ;
------------------------------------------------------------
procedure AddBins (CovBin : CovMatrix3Type ; Name : String := "") is
------------------------------------------------------------
begin
AddCross(COV_STRUCT_ID_DEFAULT, CovBin, Name) ;
end procedure AddBins ;
------------------------------------------------------------
procedure AddBins (CovBin : CovMatrix4Type ; Name : String := "") is
------------------------------------------------------------
begin
AddCross(COV_STRUCT_ID_DEFAULT, CovBin, Name) ;
end procedure AddBins ;
------------------------------------------------------------
procedure AddBins (CovBin : CovMatrix5Type ; Name : String := "") is
------------------------------------------------------------
begin
AddCross(COV_STRUCT_ID_DEFAULT, CovBin, Name) ;
end procedure AddBins ;
------------------------------------------------------------
procedure AddBins (CovBin : CovMatrix6Type ; Name : String := "") is
------------------------------------------------------------
begin
AddCross(COV_STRUCT_ID_DEFAULT, CovBin, Name) ;
end procedure AddBins ;
------------------------------------------------------------
procedure AddBins (CovBin : CovMatrix7Type ; Name : String := "") is
------------------------------------------------------------
begin
AddCross(COV_STRUCT_ID_DEFAULT, CovBin, Name) ;
end procedure AddBins ;
------------------------------------------------------------
procedure AddBins (CovBin : CovMatrix8Type ; Name : String := "") is
------------------------------------------------------------
begin
AddCross(COV_STRUCT_ID_DEFAULT, CovBin, Name) ;
end procedure AddBins ;
------------------------------------------------------------
procedure AddBins (CovBin : CovMatrix9Type ; Name : String := "") is
------------------------------------------------------------
begin
AddCross(COV_STRUCT_ID_DEFAULT, CovBin, Name) ;
end procedure AddBins ;
end protected body CovPType ;
------------------------------------------------------------------------------------------
-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX CovPType XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX CovPType XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
------------------------------------------------------------------------------------------
------------------------------------------------------------
-- /////////////////////////////////////////
-- Singleton Data Structure
-- /////////////////////////////////////////
------------------------------------------------------------
shared variable CoverageStore : CovPType ;
------------------------------------------------------------
impure function NewID (
Name : String ;
ParentID : AlertLogIDType := OSVVM_COVERAGE_ALERTLOG_ID ;
ReportMode : AlertLogReportModeType := ENABLED ;
Search : NameSearchType := NAME_AND_PARENT_ELSE_PRIVATE ;
PrintParent : AlertLogPrintParentType := PRINT_NAME_AND_PARENT
) return CoverageIDType is
begin
return CoverageStore.NewID (Name, ParentID, ReportMode, Search, PrintParent) ;
end function NewID ;
------------------------------------------------------------
-- /////////////////////////////////////////
-- Coverage Global Settings Common to All Coverage Models
-- /////////////////////////////////////////
------------------------------------------------------------
procedure FileOpenWriteBin (FileName : string; OpenKind : File_Open_Kind ) is
begin
CoverageStore.FileOpenWriteBin (FileName, OpenKind) ;
end procedure FileOpenWriteBin ;
procedure FileCloseWriteBin is
begin
CoverageStore.FileCloseWriteBin ;
end procedure FileCloseWriteBin ;
-- procedure WriteToCovFile (variable buf : inout line) is
-- begin
-- CoverageStore.WriteToCovFile (buf) ;
-- end procedure WriteToCovFile ;
procedure PrintToCovFile(S : string) is
begin
CoverageStore.PrintToCovFile (S) ;
end procedure PrintToCovFile ;
------------------------------------------------------------
procedure SetReportOptions (
------------------------------------------------------------
WritePassFail : OsvvmOptionsType := COV_OPT_INIT_PARM_DETECT ;
WriteBinInfo : OsvvmOptionsType := COV_OPT_INIT_PARM_DETECT ;
WriteCount : OsvvmOptionsType := COV_OPT_INIT_PARM_DETECT ;
WriteAnyIllegal : OsvvmOptionsType := COV_OPT_INIT_PARM_DETECT ;
WritePrefix : string := OSVVM_STRING_INIT_PARM_DETECT ;
PassName : string := OSVVM_STRING_INIT_PARM_DETECT ;
FailName : string := OSVVM_STRING_INIT_PARM_DETECT
) is
begin
CoverageStore.SetReportOptions (
WritePassFail, WriteBinInfo, WriteCount, WriteAnyIllegal,
WritePrefix, PassName, FailName
) ;
end procedure SetReportOptions ;
procedure ResetReportOptions is
begin
CoverageStore.ResetReportOptions ;
end procedure ResetReportOptions ;
------------------------------------------------------------
-- /////////////////////////////////////////
-- Coverage Model Settings
-- /////////////////////////////////////////
------------------------------------------------------------
procedure SetName (ID : CoverageIDType; Name : String) is
begin
CoverageStore.SetName (ID, Name) ;
end procedure SetName ;
impure function SetName (ID : CoverageIDType; Name : String) return string is
begin
return CoverageStore.SetName (ID, Name) ;
end function SetName ;
procedure DeallocateName (ID : CoverageIDType) is
begin
CoverageStore.DeallocateName (ID) ;
end procedure DeallocateName ;
impure function GetName (ID : CoverageIDType) return String is
begin
return CoverageStore.GetName(ID => ID) ;
end function GetName ;
impure function GetCovModelName (ID : CoverageIDType) return String is
begin
return CoverageStore.GetCovModelName(ID => ID) ;
end function GetCovModelName ;
impure function GetNamePlus (ID : CoverageIDType; prefix, suffix : string) return String is
begin
return CoverageStore.GetNamePlus (ID, prefix, suffix) ;
end function GetNamePlus ;
procedure SetItemBinNames (
ID : CoverageIDType ;
Name1 : String ;
Name2, Name3, Name4, Name5,
Name6, Name7, Name8, Name9, Name10,
Name11, Name12, Name13, Name14, Name15,
Name16, Name17, Name18, Name19, Name20 : string := ""
) is
begin
CoverageStore.SetItemBinNames (
ID,
Name1, Name2, Name3, Name4, Name5,
Name6, Name7, Name8, Name9, Name10,
Name11, Name12, Name13, Name14, Name15,
Name16, Name17, Name18, Name19, Name20
) ;
end procedure SetItemBinNames ;
------------------------------------------------------------
procedure SetMessage (ID : CoverageIDType; Message : String) is
begin
CoverageStore.SetMessage(ID, Message) ;
end procedure SetMessage ;
procedure DeallocateMessage (ID : CoverageIDType) is
begin
CoverageStore.DeallocateMessage(ID) ;
end procedure DeallocateMessage ;
procedure SetCovTarget (ID : CoverageIDType; Percent : real) is
begin
CoverageStore.SetCovTarget(ID, Percent) ;
end procedure SetCovTarget ;
impure function GetCovTarget (ID : CoverageIDType) return real is
begin
return CoverageStore.GetCovTarget(ID) ;
end function GetCovTarget ;
procedure SetThresholding (ID : CoverageIDType; A : boolean := TRUE ) is
begin
CoverageStore.SetThresholding(ID, A) ;
end procedure SetThresholding ;
procedure SetCovThreshold (ID : CoverageIDType; Percent : real) is
begin
CoverageStore.SetCovThreshold(ID, Percent) ;
end procedure SetCovThreshold ;
procedure SetMerging (ID : CoverageIDType; A : boolean := TRUE ) is
begin
CoverageStore.SetMerging(ID, A) ;
end procedure SetMerging ;
procedure SetCountMode (ID : CoverageIDType; A : CountModeType) is
begin
CoverageStore.SetCountMode(ID, A) ;
end procedure SetCountMode ;
procedure SetIllegalMode (ID : CoverageIDType; A : IllegalModeType) is
begin
CoverageStore.SetIllegalMode(ID, A) ;
end procedure SetIllegalMode ;
procedure SetWeightMode (ID : CoverageIDType; WeightMode : WeightModeType; WeightScale : real := 1.0) is
begin
CoverageStore.SetWeightMode(ID, WeightMode, WeightScale) ;
end procedure SetWeightMode ;
procedure SetCovWeight (ID : CoverageIDType; Weight : integer) is
begin
CoverageStore.SetCovWeight(ID, Weight) ;
end procedure SetCovWeight ;
impure function GetCovWeight (ID : CoverageIDType) return integer is
begin
return CoverageStore.GetCovWeight(ID) ;
end function GetCovWeight ;
procedure SetNextPointMode (ID : CoverageIDType; A : NextPointModeType) is
begin
CoverageStore.SetNextPointMode(ID, A) ;
end procedure SetNextPointMode ;
------------------------------------------------------------
procedure SetAlertLogID (ID : CoverageIDType; A : AlertLogIDType) is
begin
CoverageStore.SetAlertLogID (ID, A) ;
end procedure SetAlertLogID ;
procedure SetAlertLogID (ID : CoverageIDType; Name : string ; ParentID : AlertLogIDType := ALERTLOG_BASE_ID ; CreateHierarchy : Boolean := TRUE) is
begin
CoverageStore.SetAlertLogID (ID, Name, ParentID, CreateHierarchy) ;
end procedure SetAlertLogID ;
impure function GetAlertLogID (ID : CoverageIDType) return AlertLogIDType is
begin
return CoverageStore.GetAlertLogID(ID) ;
end function GetAlertLogID ;
------------------------------------------------------------
procedure InitSeed (ID : CoverageIDType; S : string; UseNewSeedMethods : boolean := TRUE) is
begin
CoverageStore.InitSeed(ID, S, UseNewSeedMethods) ;
end procedure InitSeed ;
impure function InitSeed (ID : CoverageIDType; S : string; UseNewSeedMethods : boolean := TRUE ) return string is
begin
return CoverageStore.InitSeed(ID, S, UseNewSeedMethods) ;
end function InitSeed ;
procedure InitSeed (ID : CoverageIDType; I : integer; UseNewSeedMethods : boolean := TRUE ) is
begin
CoverageStore.InitSeed(ID, I, UseNewSeedMethods) ;
end procedure InitSeed ;
------------------------------------------------------------
procedure SetSeed (ID : CoverageIDType; RandomSeedIn : RandomSeedType ) is
begin
CoverageStore.SetSeed (ID, RandomSeedIn) ;
end procedure SetSeed ;
impure function GetSeed (ID : CoverageIDType) return RandomSeedType is
begin
return CoverageStore.GetSeed (ID => ID) ;
end function GetSeed ;
------------------------------------------------------------
-- /////////////////////////////////////////
-- Item / Cross Bin Creation and Destruction
-- /////////////////////////////////////////
------------------------------------------------------------
procedure SetBinSize (ID : CoverageIDType; NewNumBins : integer) is
begin
CoverageStore.SetBinSize (ID, NewNumBins) ;
end procedure SetBinSize ;
procedure DeallocateBins (CoverID : CoverageIDType) is
begin
CoverageStore.DeallocateBins (CoverID) ;
end procedure DeallocateBins ;
procedure Deallocate (ID : CoverageIDType) is
begin
CoverageStore.Deallocate (ID) ;
end procedure Deallocate ;
------------------------------------------------------------
-- Weight Deprecated
procedure AddBins (
------------------------------------------------------------
ID : CoverageIDType ;
Name : String ;
AtLeast : integer ;
Weight : integer ;
CovBin : CovBinType
) is
begin
CoverageStore.AddBins (ID, Name, AtLeast, Weight, CovBin) ;
end procedure AddBins ;
procedure AddBins (ID : CoverageIDType; Name : String ; AtLeast : integer ; CovBin : CovBinType ) is
begin
CoverageStore.AddBins (ID, Name, AtLeast, CovBin) ;
end procedure AddBins ;
procedure AddBins (ID : CoverageIDType; Name : String ; CovBin : CovBinType) is
begin
CoverageStore.AddBins (ID, Name, CovBin) ;
end procedure AddBins ;
procedure AddBins (ID : CoverageIDType; AtLeast : integer ; Weight : integer ; CovBin : CovBinType ) is
begin
CoverageStore.AddBins (ID, AtLeast, Weight, CovBin) ;
end procedure AddBins ;
procedure AddBins (ID : CoverageIDType; AtLeast : integer ; CovBin : CovBinType ) is
begin
CoverageStore.AddBins (ID, AtLeast, CovBin) ;
end procedure AddBins ;
procedure AddBins (ID : CoverageIDType; CovBin : CovBinType ) is
begin
CoverageStore.AddBins (ID, CovBin) ;
end procedure AddBins ;
------------------------------------------------------------
-- Weight Deprecated
procedure AddCross (
------------------------------------------------------------
ID : CoverageIDType ;
Name : string ;
AtLeast : integer ;
Weight : integer ;
Bin1, Bin2 : CovBinType ;
Bin3, Bin4, Bin5, Bin6, Bin7, Bin8, Bin9, Bin10, Bin11, Bin12, Bin13,
Bin14, Bin15, Bin16, Bin17, Bin18, Bin19, Bin20 : CovBinType := NULL_BIN
) is
begin
CoverageStore.AddCross(ID, Name, AtLeast, Weight, Bin1, Bin2,
Bin3, Bin4, Bin5, Bin6, Bin7, Bin8, Bin9, Bin10, Bin11, Bin12, Bin13,
Bin14, Bin15, Bin16, Bin17, Bin18, Bin19, Bin20
);
end procedure AddCross ;
------------------------------------------------------------
procedure AddCross(
------------------------------------------------------------
ID : CoverageIDType ;
Name : string ;
AtLeast : integer ;
Bin1, Bin2 : CovBinType ;
Bin3, Bin4, Bin5, Bin6, Bin7, Bin8, Bin9, Bin10, Bin11, Bin12, Bin13,
Bin14, Bin15, Bin16, Bin17, Bin18, Bin19, Bin20 : CovBinType := NULL_BIN
) is
begin
CoverageStore.AddCross(ID, Name, AtLeast, Bin1, Bin2,
Bin3, Bin4, Bin5, Bin6, Bin7, Bin8, Bin9, Bin10, Bin11, Bin12, Bin13,
Bin14, Bin15, Bin16, Bin17, Bin18, Bin19, Bin20
);
end procedure AddCross ;
------------------------------------------------------------
procedure AddCross(
------------------------------------------------------------
ID : CoverageIDType ;
Name : string ;
Bin1, Bin2 : CovBinType ;
Bin3, Bin4, Bin5, Bin6, Bin7, Bin8, Bin9, Bin10, Bin11, Bin12, Bin13,
Bin14, Bin15, Bin16, Bin17, Bin18, Bin19, Bin20 : CovBinType := NULL_BIN
) is
begin
CoverageStore.AddCross(ID, Name, Bin1, Bin2,
Bin3, Bin4, Bin5, Bin6, Bin7, Bin8, Bin9, Bin10, Bin11, Bin12, Bin13,
Bin14, Bin15, Bin16, Bin17, Bin18, Bin19, Bin20
);
end procedure AddCross ;
------------------------------------------------------------
-- Weight Deprecated
procedure AddCross(
------------------------------------------------------------
ID : CoverageIDType ;
AtLeast : integer ;
Weight : integer ;
Bin1, Bin2 : CovBinType ;
Bin3, Bin4, Bin5, Bin6, Bin7, Bin8, Bin9, Bin10, Bin11, Bin12, Bin13,
Bin14, Bin15, Bin16, Bin17, Bin18, Bin19, Bin20 : CovBinType := NULL_BIN
) is
begin
CoverageStore.AddCross(ID, AtLeast, Weight, Bin1, Bin2,
Bin3, Bin4, Bin5, Bin6, Bin7, Bin8, Bin9, Bin10, Bin11, Bin12, Bin13,
Bin14, Bin15, Bin16, Bin17, Bin18, Bin19, Bin20
);
end procedure AddCross ;
------------------------------------------------------------
procedure AddCross(
------------------------------------------------------------
ID : CoverageIDType ;
AtLeast : integer ;
Bin1, Bin2 : CovBinType ;
Bin3, Bin4, Bin5, Bin6, Bin7, Bin8, Bin9, Bin10, Bin11, Bin12, Bin13,
Bin14, Bin15, Bin16, Bin17, Bin18, Bin19, Bin20 : CovBinType := NULL_BIN
) is
begin
CoverageStore.AddCross(ID, AtLeast, Bin1, Bin2,
Bin3, Bin4, Bin5, Bin6, Bin7, Bin8, Bin9, Bin10, Bin11, Bin12, Bin13,
Bin14, Bin15, Bin16, Bin17, Bin18, Bin19, Bin20
);
end procedure AddCross ;
------------------------------------------------------------
procedure AddCross(
------------------------------------------------------------
ID : CoverageIDType ;
Bin1, Bin2 : CovBinType ;
Bin3, Bin4, Bin5, Bin6, Bin7, Bin8, Bin9, Bin10, Bin11, Bin12, Bin13,
Bin14, Bin15, Bin16, Bin17, Bin18, Bin19, Bin20 : CovBinType := NULL_BIN
) is
begin
CoverageStore.AddCross(ID, Bin1, Bin2,
Bin3, Bin4, Bin5, Bin6, Bin7, Bin8, Bin9, Bin10, Bin11, Bin12, Bin13,
Bin14, Bin15, Bin16, Bin17, Bin18, Bin19, Bin20
);
end procedure AddCross ;
------------------------------------------------------------
-- AddCross for usage with constants created by GenCross
------------------------------------------------------------
procedure AddCross (ID : CoverageIDType; CovBin : CovMatrix2Type ; Name : String := "") is
begin
CoverageStore.AddCross (ID, CovBin, Name) ;
end procedure AddCross ;
procedure AddCross (ID : CoverageIDType; CovBin : CovMatrix3Type ; Name : String := "") is
begin
CoverageStore.AddCross (ID, CovBin, Name) ;
end procedure AddCross ;
procedure AddCross (ID : CoverageIDType; CovBin : CovMatrix4Type ; Name : String := "") is
begin
CoverageStore.AddCross (ID, CovBin, Name) ;
end procedure AddCross ;
procedure AddCross (ID : CoverageIDType; CovBin : CovMatrix5Type ; Name : String := "") is
begin
CoverageStore.AddCross (ID, CovBin, Name) ;
end procedure AddCross ;
procedure AddCross (ID : CoverageIDType; CovBin : CovMatrix6Type ; Name : String := "") is
begin
CoverageStore.AddCross (ID, CovBin, Name) ;
end procedure AddCross ;
procedure AddCross (ID : CoverageIDType; CovBin : CovMatrix7Type ; Name : String := "") is
begin
CoverageStore.AddCross (ID, CovBin, Name) ;
end procedure AddCross ;
procedure AddCross (ID : CoverageIDType; CovBin : CovMatrix8Type ; Name : String := "") is
begin
CoverageStore.AddCross (ID, CovBin, Name) ;
end procedure AddCross ;
procedure AddCross (ID : CoverageIDType; CovBin : CovMatrix9Type ; Name : String := "") is
begin
CoverageStore.AddCross (ID, CovBin, Name) ;
end procedure AddCross ;
------------------------------------------------------------
-- /////////////////////////////////////////
-- Recording and Clearing Coverage
-- /////////////////////////////////////////
------------------------------------------------------------
------------------------------------------------------------
procedure ICoverLast (ID : CoverageIDType) is
begin
CoverageStore.ICoverLast (ID) ;
end procedure ICoverLast ;
procedure ICover (ID : CoverageIDType; CovPoint : integer_vector) is
begin
CoverageStore.ICover (ID, CovPoint) ;
end procedure ICover ;
procedure ICover (ID : CoverageIDType; CovPoint : integer) is
begin
CoverageStore.ICover (ID, CovPoint) ;
end procedure ICover ;
procedure TCover (CoverID : CoverageIDType; A : integer) is
begin
CoverageStore.TCover (CoverID, A) ;
end procedure TCover ;
procedure ClearCov (ID : CoverageIDType) is
begin
CoverageStore.ClearCov (ID) ;
end procedure ClearCov ;
------------------------------------------------------------
-- /////////////////////////////////////////
-- Coverage Information and Statistics
-- /////////////////////////////////////////
------------------------------------------------------------
------------------------------------------------------------
impure function IsCovered (ID : CoverageIDType; PercentCov : real ) return boolean is
begin
return CoverageStore.IsCovered (ID, PercentCov) ;
end function IsCovered ;
impure function IsCovered (ID : CoverageIDType) return boolean is
begin
return CoverageStore.IsCovered (ID) ;
end function IsCovered ;
impure function IsInitialized (ID : CoverageIDType) return boolean is
begin
return CoverageStore.IsInitialized (ID) ;
end function IsInitialized ;
------------------------------------------------------------
impure function GetItemCount (ID : CoverageIDType) return integer is
begin
return CoverageStore.GetItemCount (ID) ;
end function GetItemCount ;
impure function GetCov (ID : CoverageIDType; PercentCov : real ) return real is
begin
return CoverageStore.GetCov (ID, PercentCov) ;
end function GetCov ;
impure function GetCov (ID : CoverageIDType) return real is
begin
return CoverageStore.GetCov (ID) ;
end function GetCov ;
impure function GetTotalCovCount (ID : CoverageIDType; PercentCov : real ) return integer is
begin
return CoverageStore.GetTotalCovCount (ID, PercentCov) ;
end function GetTotalCovCount ;
impure function GetTotalCovCount (ID : CoverageIDType) return integer is
begin
return CoverageStore.GetTotalCovCount (ID) ;
end function GetTotalCovCount ;
impure function GetTotalCovGoal (ID : CoverageIDType; PercentCov : real ) return integer is
begin
return CoverageStore.GetTotalCovGoal (ID, PercentCov) ;
end function GetTotalCovGoal ;
impure function GetTotalCovGoal (ID : CoverageIDType) return integer is
begin
return CoverageStore.GetTotalCovGoal (ID) ;
end function GetTotalCovGoal ;
------------------------------------------------------------
impure function GetMinCov (ID : CoverageIDType) return real is
begin
return CoverageStore.GetMinCov (ID) ;
end function GetMinCov ;
impure function GetMinCount (ID : CoverageIDType) return integer is
begin
return CoverageStore.GetMinCount (ID) ;
end function GetMinCount ;
impure function GetMaxCov (ID : CoverageIDType) return real is
begin
return CoverageStore.GetMaxCov (ID) ;
end function GetMaxCov ;
impure function GetMaxCount (ID : CoverageIDType) return integer is
begin
return CoverageStore.GetMaxCount (ID) ;
end function GetMaxCount ;
------------------------------------------------------------
impure function CountCovHoles (ID : CoverageIDType; PercentCov : real ) return integer is
begin
return CoverageStore.CountCovHoles (ID, PercentCov) ;
end function CountCovHoles ;
impure function CountCovHoles (ID : CoverageIDType) return integer is
begin
return CoverageStore.CountCovHoles (ID) ;
end function CountCovHoles ;
------------------------------------------------------------
-- /////////////////////////////////////////
-- Generating Coverage Points, BinValues, and Indices
-- /////////////////////////////////////////
------------------------------------------------------------
-- Return Points
------------------------------------------------------------
-- to be replaced in VHDL-2019 by version that uses RandomSeed as an inout
impure function ToRandPoint (ID : CoverageIDType; BinVal : RangeArrayType ) return integer is
begin
return CoverageStore.ToRandPoint (ID, BinVal) ;
end function ToRandPoint ;
impure function ToRandPoint (ID : CoverageIDType; BinVal : RangeArrayType ) return integer_vector is
begin
return CoverageStore.ToRandPoint (ID, BinVal) ;
end function ToRandPoint ;
------------------------------------------------------------
-- Return Points
impure function GetPoint (ID : CoverageIDType; BinIndex : integer ) return integer is
begin
return CoverageStore.GetPoint (ID, BinIndex) ;
end function GetPoint ;
impure function GetPoint (ID : CoverageIDType; BinIndex : integer ) return integer_vector is
begin
return CoverageStore.GetPoint (ID, BinIndex) ;
end function GetPoint ;
impure function GetRandPoint (ID : CoverageIDType) return integer is
begin
return CoverageStore.GetRandPoint (ID) ;
end function GetRandPoint ;
impure function GetRandPoint (ID : CoverageIDType; PercentCov : real ) return integer is
begin
return CoverageStore.GetRandPoint (ID, PercentCov) ;
end function GetRandPoint ;
impure function GetRandPoint (ID : CoverageIDType) return integer_vector is
begin
return CoverageStore.GetRandPoint (ID) ;
end function GetRandPoint ;
impure function GetRandPoint (ID : CoverageIDType; PercentCov : real ) return integer_vector is
begin
return CoverageStore.GetRandPoint (ID, PercentCov) ;
end function GetRandPoint ;
impure function GetIncPoint (ID : CoverageIDType) return integer is
begin
return CoverageStore.GetIncPoint (ID => ID) ;
end function GetIncPoint ;
impure function GetIncPoint (ID : CoverageIDType) return integer_vector is
begin
return CoverageStore.GetIncPoint (ID => ID) ;
end function GetIncPoint ;
impure function GetMinPoint (ID : CoverageIDType) return integer is
begin
return CoverageStore.GetMinPoint (ID => ID) ;
end function GetMinPoint ;
impure function GetMinPoint (ID : CoverageIDType) return integer_vector is
begin
return CoverageStore.GetMinPoint (ID => ID) ;
end function GetMinPoint ;
impure function GetMaxPoint (ID : CoverageIDType) return integer is
begin
return CoverageStore.GetMaxPoint (ID => ID) ;
end function GetMaxPoint ;
impure function GetMaxPoint (ID : CoverageIDType) return integer_vector is
begin
return CoverageStore.GetMaxPoint (ID => ID) ;
end function GetMaxPoint ;
impure function GetNextPoint (ID : CoverageIDType; Mode : NextPointModeType) return integer is
begin
return CoverageStore.GetNextPoint (ID, Mode) ;
end function GetNextPoint ;
impure function GetNextPoint (ID : CoverageIDType; Mode : NextPointModeType) return integer_vector is
begin
return CoverageStore.GetNextPoint (ID, Mode) ;
end function GetNextPoint ;
impure function GetNextPoint (ID : CoverageIDType) return integer is
begin
return CoverageStore.GetNextPoint (ID) ;
end function GetNextPoint ;
impure function GetNextPoint (ID : CoverageIDType) return integer_vector is
begin
return CoverageStore.GetNextPoint (ID) ;
end function GetNextPoint ;
------------------------------------------------------------
-- deprecated, see GetRandPoint
impure function RandCovPoint (ID : CoverageIDType) return integer is
begin
return CoverageStore.RandCovPoint (ID) ;
end function RandCovPoint ;
impure function RandCovPoint (ID : CoverageIDType; PercentCov : real ) return integer is
begin
return CoverageStore.RandCovPoint (ID, PercentCov) ;
end function RandCovPoint ;
impure function RandCovPoint (ID : CoverageIDType) return integer_vector is
begin
return CoverageStore.RandCovPoint (ID) ;
end function RandCovPoint ;
impure function RandCovPoint (ID : CoverageIDType; PercentCov : real ) return integer_vector is
begin
return CoverageStore.RandCovPoint (ID, PercentCov) ;
end function RandCovPoint ;
------------------------------------------------------------
-- Return BinVals
impure function GetBinVal (ID : CoverageIDType; BinIndex : integer ) return RangeArrayType is
begin
return CoverageStore.GetBinVal (ID, BinIndex) ;
end function GetBinVal ;
impure function GetRandBinVal (ID : CoverageIDType; PercentCov : real ) return RangeArrayType is
begin
return CoverageStore.GetRandBinVal (ID, PercentCov) ;
end function GetRandBinVal ;
impure function GetRandBinVal (ID : CoverageIDType) return RangeArrayType is
begin
return CoverageStore.GetRandBinVal (ID => ID) ;
end function GetRandBinVal ;
impure function GetLastBinVal (ID : CoverageIDType) return RangeArrayType is
begin
return CoverageStore.GetLastBinVal (ID => ID) ;
end function GetLastBinVal ;
impure function GetIncBinVal (ID : CoverageIDType) return RangeArrayType is
begin
return CoverageStore.GetIncBinVal (ID => ID) ;
end function GetIncBinVal ;
impure function GetMinBinVal (ID : CoverageIDType) return RangeArrayType is
begin
return CoverageStore.GetMinBinVal (ID => ID) ;
end function GetMinBinVal ;
impure function GetMaxBinVal (ID : CoverageIDType) return RangeArrayType is
begin
return CoverageStore.GetMaxBinVal (ID => ID) ;
end function GetMaxBinVal ;
impure function GetNextBinVal (ID : CoverageIDType; Mode : NextPointModeType) return RangeArrayType is
begin
return CoverageStore.GetNextBinVal (ID, Mode) ;
end function GetNextBinVal ;
impure function GetNextBinVal (ID : CoverageIDType) return RangeArrayType is
begin
return CoverageStore.GetNextBinVal (ID => ID) ;
end function GetNextBinVal ;
impure function GetHoleBinVal (ID : CoverageIDType; ReqHoleNum : integer ; PercentCov : real ) return RangeArrayType is
begin
return CoverageStore.GetHoleBinVal (ID, ReqHoleNum, PercentCov) ;
end function GetHoleBinVal ;
impure function GetHoleBinVal (ID : CoverageIDType; PercentCov : real ) return RangeArrayType is
begin
return CoverageStore.GetHoleBinVal (ID, PercentCov) ;
end function GetHoleBinVal ;
impure function GetHoleBinVal (ID : CoverageIDType; ReqHoleNum : integer := 1 ) return RangeArrayType is
begin
return CoverageStore.GetHoleBinVal (ID, ReqHoleNum) ;
end function GetHoleBinVal ;
-- deprecated RandCovBinVal, see GetRandBinVal
impure function RandCovBinVal (ID : CoverageIDType; PercentCov : real ) return RangeArrayType is
begin
return CoverageStore.RandCovBinVal (ID, PercentCov) ;
end function RandCovBinVal ;
impure function RandCovBinVal (ID : CoverageIDType) return RangeArrayType is
begin
return CoverageStore.RandCovBinVal (ID => ID) ;
end function RandCovBinVal ;
------------------------------------------------------------
-- Return Index Values
impure function GetNumBins (ID : CoverageIDType) return integer is
begin
return CoverageStore.GetNumBins (ID => ID) ;
end function GetNumBins ;
impure function GetRandIndex (ID : CoverageIDType; CovTargetPercent : real ) return integer is
begin
return CoverageStore.GetRandIndex (ID, CovTargetPercent) ;
end function GetRandIndex ;
impure function GetRandIndex (ID : CoverageIDType) return integer is
begin
return CoverageStore.GetRandIndex (ID => ID) ;
end function GetRandIndex ;
impure function GetLastIndex (ID : CoverageIDType) return integer is
begin
return CoverageStore.GetLastIndex (ID => ID) ;
end function GetLastIndex ;
impure function GetIncIndex (ID : CoverageIDType) return integer is
begin
return CoverageStore.GetIncIndex (ID => ID) ;
end function GetIncIndex ;
impure function GetMinIndex (ID : CoverageIDType) return integer is
begin
return CoverageStore.GetMinIndex (ID => ID) ;
end function GetMinIndex ;
impure function GetMaxIndex (ID : CoverageIDType) return integer is
begin
return CoverageStore.GetMaxIndex (ID => ID) ;
end function GetMaxIndex ;
impure function GetNextIndex (ID : CoverageIDType; Mode : NextPointModeType) return integer is
begin
return CoverageStore.GetNextIndex (ID, Mode) ;
end function GetNextIndex;
impure function GetNextIndex (ID : CoverageIDType) return integer is
begin
return CoverageStore.GetNextIndex (ID => ID) ;
end function GetNextIndex ;
------------------------------------------------------------
-- /////////////////////////////////////////
-- Accessing Coverage Bin Information
-- /////////////////////////////////////////
------------------------------------------------------------
-- ------------------------------------------------------------
-- Intended as a stand in until we get a more general GetBin
impure function GetBinInfo (ID : CoverageIDType; BinIndex : integer ) return CovBinBaseType is
begin
return CoverageStore.GetBinInfo(ID, BinIndex) ;
end function GetBinInfo ;
-- ------------------------------------------------------------
-- Intended as a stand in until we get a more general GetBin
impure function GetBinValLength (ID : CoverageIDType) return integer is
begin
return CoverageStore.GetBinValLength(ID => ID);
end function GetBinValLength ;
-- ------------------------------------------------------------
-- Eventually the multiple GetBin functions will be replaced by a
-- a single GetBin that returns CovBinBaseType with BinVal as an
-- unconstrained element
impure function GetBin (ID : CoverageIDType; BinIndex : integer ) return CovBinBaseType is
begin
return CoverageStore.GetBin(ID, BinIndex) ;
end function GetBin ;
impure function GetBin (ID : CoverageIDType; BinIndex : integer ) return CovMatrix2BaseType is
begin
return CoverageStore.GetBin(ID, BinIndex) ;
end function GetBin ;
impure function GetBin (ID : CoverageIDType; BinIndex : integer ) return CovMatrix3BaseType is
begin
return CoverageStore.GetBin(ID, BinIndex) ;
end function GetBin ;
impure function GetBin (ID : CoverageIDType; BinIndex : integer ) return CovMatrix4BaseType is
begin
return CoverageStore.GetBin(ID, BinIndex) ;
end function GetBin ;
impure function GetBin (ID : CoverageIDType; BinIndex : integer ) return CovMatrix5BaseType is
begin
return CoverageStore.GetBin(ID, BinIndex) ;
end function GetBin ;
impure function GetBin (ID : CoverageIDType; BinIndex : integer ) return CovMatrix6BaseType is
begin
return CoverageStore.GetBin(ID, BinIndex) ;
end function GetBin ;
impure function GetBin (ID : CoverageIDType; BinIndex : integer ) return CovMatrix7BaseType is
begin
return CoverageStore.GetBin(ID, BinIndex) ;
end function GetBin ;
impure function GetBin (ID : CoverageIDType; BinIndex : integer ) return CovMatrix8BaseType is
begin
return CoverageStore.GetBin(ID, BinIndex) ;
end function GetBin ;
impure function GetBin (ID : CoverageIDType; BinIndex : integer ) return CovMatrix9BaseType is
begin
return CoverageStore.GetBin(ID, BinIndex) ;
end function GetBin ;
-- ------------------------------------------------------------
impure function GetBinName (ID : CoverageIDType; BinIndex : integer; DefaultName : string := "" ) return string is
begin
return CoverageStore.GetBinName (ID, BinIndex, DefaultName) ;
end function GetBinName ;
------------------------------------------------------------
impure function GetErrorCount (ID : CoverageIDType) return integer is
begin
return CoverageStore.GetErrorCount (ID => ID) ;
end function GetErrorCount ;
------------------------------------------------------------
-- /////////////////////////////////////////
-- Printing Coverage Bin Information
-- /////////////////////////////////////////
------------------------------------------------------------
-- To specify the following, see SetReportOptions
-- WritePassFail, WriteBinInfo, WriteCount, WriteAnyIllegal
-- WritePrefix, PassName, FailName
------------------------------------------------------------
procedure WriteBin (ID : CoverageIDType) is
begin
CoverageStore.WriteBin (ID => ID) ;
end procedure WriteBin ;
procedure WriteBin (ID : CoverageIDType; LogLevel : LogType ) is
begin
CoverageStore.WriteBin (ID, LogLevel) ;
end procedure WriteBin ;
procedure WriteBin (ID : CoverageIDType; FileName : string; OpenKind : File_Open_Kind := APPEND_MODE) is
begin
CoverageStore.WriteBin (ID, FileName, OpenKind) ;
end procedure WriteBin ;
procedure WriteBin (ID : CoverageIDType; LogLevel : LogType; FileName : string; OpenKind : File_Open_Kind := APPEND_MODE) is
begin
CoverageStore.WriteBin (ID, LogLevel, FileName, OpenKind) ;
end procedure WriteBin ;
------------------------------------------------------------
procedure DumpBin (ID : CoverageIDType; LogLevel : LogType := DEBUG) is
begin
CoverageStore.DumpBin (ID, LogLevel) ;
end procedure DumpBin ;
------------------------------------------------------------
procedure WriteCovHoles (ID : CoverageIDType; LogLevel : LogType := ALWAYS ) is
begin
CoverageStore.WriteCovHoles (ID, LogLevel) ;
end procedure WriteCovHoles ;
procedure WriteCovHoles (ID : CoverageIDType; PercentCov : real ) is
begin
CoverageStore.WriteCovHoles (ID, PercentCov) ;
end procedure WriteCovHoles ;
procedure WriteCovHoles (ID : CoverageIDType; LogLevel : LogType; PercentCov : real ) is
begin
CoverageStore.WriteCovHoles (ID, LogLevel, PercentCov) ;
end procedure WriteCovHoles ;
procedure WriteCovHoles (ID : CoverageIDType; FileName : string; OpenKind : File_Open_Kind := APPEND_MODE ) is
begin
CoverageStore.WriteCovHoles (ID, FileName, OpenKind) ;
end procedure WriteCovHoles ;
procedure WriteCovHoles (ID : CoverageIDType; LogLevel : LogType; FileName : string; OpenKind : File_Open_Kind := APPEND_MODE ) is
begin
CoverageStore.WriteCovHoles (ID, LogLevel, FileName, OpenKind) ;
end procedure WriteCovHoles ;
procedure WriteCovHoles (ID : CoverageIDType; FileName : string; PercentCov : real ; OpenKind : File_Open_Kind := APPEND_MODE ) is
begin
CoverageStore.WriteCovHoles (ID, FileName, PercentCov, OpenKind) ;
end procedure WriteCovHoles ;
procedure WriteCovHoles (ID : CoverageIDType; LogLevel : LogType; FileName : string; PercentCov : real ; OpenKind : File_Open_Kind := APPEND_MODE ) is
begin
CoverageStore.WriteCovHoles (ID, LogLevel, FileName, PercentCov, OpenKind) ;
end procedure WriteCovHoles ;
------------------------------------------------------------
-- /////////////////////////////////////////
-- Writing Out RAW Coverage Bin Information
-- Note that read supports merging of coverage models
-- /////////////////////////////////////////
------------------------------------------------------------
procedure ReadCovDb (ID : CoverageIDType; FileName : string; Merge : boolean := FALSE) is
begin
CoverageStore.ReadCovDb (ID, FileName, Merge) ;
end procedure ReadCovDb ;
procedure WriteCovDb (ID : CoverageIDType; FileName : string; OpenKind : File_Open_Kind := WRITE_MODE ) is
begin
CoverageStore.WriteCovDb (ID, FileName, OpenKind) ;
end procedure WriteCovDb ;
-- procedure WriteCovDb (ID : CoverageIDType) is
-- ------------------------------------------------------------
-- procedure WriteCovYaml (ID : CoverageIDType; FileName : string; OpenKind : File_Open_Kind := WRITE_MODE ) is
-- ------------------------------------------------------------
-- file CovYamlFile : text open OpenKind is FileName ;
-- begin
-- CoverageStore.WriteCovYaml (ID, FileName, OpenKind) ;
-- end procedure WriteCovYaml ;
------------------------------------------------------------
procedure WriteCovYaml (FileName : string := ""; OpenKind : File_Open_Kind := WRITE_MODE) is
------------------------------------------------------------
begin
CoverageStore.WriteCovYaml(FileName, GetCov, OpenKind) ;
end procedure WriteCovYaml ;
------------------------------------------------------------
procedure ReadCovYaml (FileName : string := ""; Merge : boolean := FALSE) is
------------------------------------------------------------
begin
CoverageStore.ReadCovYaml(FileName, Merge) ;
end procedure ReadCovYaml ;
------------------------------------------------------------
impure function GotCoverage return boolean is
------------------------------------------------------------
begin
return CoverageStore.GotCoverage ;
end function GotCoverage ;
------------------------------------------------------------
impure function GetCov (PercentCov : real ) return real is
------------------------------------------------------------
variable ID : CoverageIDType ;
variable ItemCovCount, ItemCovGoal : integer ;
variable TotalCovCount, TotalCovGoal : integer := 0;
variable CovWeight : integer ;
variable ScaledCovGoal, rTotalCovCount : real ;
begin
for i in 1 to CoverageStore.GetNumIDs loop
ID := (ID => i) ;
CoverageStore.GetTotalCovCountAndGoal(ID, ItemCovCount, ItemCovGoal) ;
CovWeight := GetCovWeight(ID) ;
TotalCovCount := TotalCovCount + (ItemCovCount * CovWeight) ;
TotalCovGoal := TotalCovGoal + (ItemCovGoal * CovWeight) ;
end loop ;
ScaledCovGoal := PercentCov * real(TotalCovGoal) / 100.0 ;
rTotalCovCount := real(TotalCovCount) ;
if rTotalCovCount >= ScaledCovGoal then
return 100.0 ;
elsif ScaledCovGoal > 0.0 then
return (100.0 * rTotalCovCount) / ScaledCovGoal ;
else
return 0.0 ;
end if;
end function GetCov ;
------------------------------------------------------------
impure function GetCov return real is
------------------------------------------------------------
begin
return GetCov (100.0) ;
end function GetCov ;
------------------------------------------------------------
-- Experimental. Intended primarily for development.
procedure CompareBins (
------------------------------------------------------------
variable Bin1 : inout CovPType ;
variable Bin2 : inout CovPType ;
variable ErrorCount : inout integer
) is
variable NumBins1, NumBins2 : integer ;
variable BinInfo1, BinInfo2 : CovBinBaseType ;
variable BinVal1, BinVal2 : RangeArrayType(1 to Bin1.GetBinValLength) ;
variable buf : line ;
variable iAlertLogID : AlertLogIDType ;
begin
iAlertLogID := Bin1.GetAlertLogID ;
NumBins1 := Bin1.GetNumBins ;
NumBins2 := Bin2.GetNumBins ;
if (NumBins1 /= NumBins2) then
ErrorCount := ErrorCount + 1 ;
print("CoveragePkg.CompareBins: CoverageModels " & Bin1.GetCovModelName & " and " & Bin2.GetCovModelName &
" have different bin lengths") ;
return ;
end if ;
for i in 1 to NumBins1 loop
BinInfo1 := Bin1.GetBinInfo(i) ;
BinInfo2 := Bin2.GetBinInfo(i) ;
BinVal1 := Bin1.GetBinVal (i) ;
BinVal2 := Bin2.GetBinVal (i) ;
if BinInfo1 /= BinInfo2 or BinVal1 /= BinVal2 then
write(buf, "%% Bin:" & to_string(i) & " miscompare." & LF) ;
-- writeline(OUTPUT, buf) ;
swrite(buf, "%% Bin1: ") ;
write(buf, BinVal1) ;
write(buf, " Action = " & to_string(BinInfo1.action)) ;
write(buf, " Count = " & to_string(BinInfo1.count)) ;
write(buf, " AtLeast = " & to_string(BinInfo1.AtLeast)) ;
write(buf, " Weight = " & to_string(BinInfo1.Weight) & LF ) ;
-- writeline(OUTPUT, buf) ;
swrite(buf, "%% Bin2: ") ;
write(buf, BinVal2) ;
write(buf, " Action = " & to_string(BinInfo2.action)) ;
write(buf, " Count = " & to_string(BinInfo2.count)) ;
write(buf, " AtLeast = " & to_string(BinInfo2.AtLeast)) ;
write(buf, " Weight = " & to_string(BinInfo2.Weight) & LF ) ;
-- writeline(OUTPUT, buf) ;
ErrorCount := ErrorCount + 1 ;
writeline(buf) ;
-- Alert(iAlertLogID, buf.all, ERROR) ;
-- deallocate(buf) ;
end if ;
end loop ;
end procedure CompareBins ;
------------------------------------------------------------
-- Experimental. Intended primarily for development.
procedure CompareBins (
------------------------------------------------------------
variable Bin1 : inout CovPType ;
variable Bin2 : inout CovPType
) is
variable ErrorCount : integer ;
variable iAlertLogID : AlertLogIDType ;
begin
CompareBins(Bin1, Bin2, ErrorCount) ;
iAlertLogID := Bin1.GetAlertLogID ;
AffirmIfEqual(ErrorCount, 0, "CompareBins(Bin1, Bin2, ErrorCount) " & Bin1.GetCovModelName & " and " & Bin2.GetCovModelName & " ErrorCount:") ;
end procedure CompareBins ;
------------------------------------------------------------
-- Experimental. Intended primarily for development.
procedure CompareBins (
------------------------------------------------------------
constant Bin1 : in CoverageIDType ;
constant Bin2 : in CoverageIDType ;
variable Valid : out Boolean
) is
variable NumBins1, NumBins2 : integer ;
variable BinInfo1, BinInfo2 : CovBinBaseType ;
variable BinVal1, BinVal2 : RangeArrayType(1 to GetBinValLength(Bin1)) ;
variable buf : line ;
variable iAlertLogID : AlertLogIDType ;
begin
iAlertLogID := GetAlertLogID(Bin1) ;
NumBins1 := GetNumBins(Bin1) ;
NumBins2 := GetNumBins(Bin2) ;
Valid := TRUE ;
if (NumBins1 /= NumBins2) then
Valid := FALSE ;
print("CoveragePkg.CompareBins: CoverageModels " & GetCovModelName(Bin1) & " and " & GetCovModelName(Bin2) &
" have different bin lengths") ;
return ;
end if ;
for i in 1 to NumBins1 loop
BinInfo1 := GetBinInfo(Bin1, i) ;
BinInfo2 := GetBinInfo(Bin2, i) ;
BinVal1 := GetBinVal (Bin1, i) ;
BinVal2 := GetBinVal (Bin2, i) ;
if BinInfo1 /= BinInfo2 or BinVal1 /= BinVal2 then
write(buf, "%% Bin: " & to_string(i) & " miscompare." & LF) ;
-- writeline(OUTPUT, buf) ;
swrite(buf, "%% Bin1: ") ;
write(buf, BinVal1) ;
write(buf, " Action = " & to_string(BinInfo1.action)) ;
write(buf, " Count = " & to_string(BinInfo1.count)) ;
write(buf, " AtLeast = " & to_string(BinInfo1.AtLeast)) ;
write(buf, " Weight = " & to_string(BinInfo1.Weight) & LF ) ;
-- writeline(OUTPUT, buf) ;
swrite(buf, "%% Bin2: ") ;
write(buf, BinVal2) ;
write(buf, " Action = " & to_string(BinInfo2.action)) ;
write(buf, " Count = " & to_string(BinInfo2.count)) ;
write(buf, " AtLeast = " & to_string(BinInfo2.AtLeast)) ;
write(buf, " Weight = " & to_string(BinInfo2.Weight) ) ; -- & LF
-- writeline(OUTPUT, buf) ;
Valid := FALSE ;
writeline(buf) ;
-- Alert(iAlertLogID, buf.all, ERROR) ;
-- deallocate(buf) ;
end if ;
end loop ;
end procedure CompareBins ;
------------------------------------------------------------
-- Experimental. Intended primarily for development.
procedure CompareBins (
------------------------------------------------------------
constant Bin1 : in CoverageIDType ;
constant Bin2 : in CoverageIDType
) is
variable Valid : boolean ;
variable iAlertLogID : AlertLogIDType ;
begin
CompareBins(Bin1, Bin2, Valid) ;
iAlertLogID := GetAlertLogID(Bin1) ;
AffirmIf(iAlertLogID, Valid, "CompareBins(Bin1, Bin2) " & GetCovModelName(Bin1) & " and " & GetCovModelName(Bin2)) ;
end procedure CompareBins ;
------------------------------------------------------------
-- package local, Used by GenBin, IllegalBin, and IgnoreBin
function MakeBin(
-- Must be pure to allow initializing coverage models passed as generics.
-- Impure implies the expression is not globally static.
------------------------------------------------------------
Min, Max : integer ;
NumBin : integer ;
AtLeast : integer ;
Weight : integer ;
Action : integer
) return CovBinType is
variable iCovBin : CovBinType(1 to NumBin) ;
variable TotalBins : integer ; -- either real or integer
variable rMax, rCurMin, rNumItemsInBin, rRemainingBins : real ; -- must be real
variable iCurMin, iCurMax : integer ;
begin
if Min > Max then
-- Similar to NULL ranges. Only generate report warning.
report "OSVVM.CoveragePkg.MakeBin (called by GenBin, IllegalBin, or IgnoreBin) MAX > MIN generated NULL_BIN"
severity WARNING ;
-- No Alerts. They make this impure.
-- Alert(OSVVM_COVERAGE_ALERTLOG_ID, "CoveragePkg.MakeBin (called by GenBin, IllegalBin, IgnoreBin): Min must be <= Max", WARNING) ;
return NULL_BIN ;
elsif NumBin <= 0 then
-- Similar to NULL ranges. Only generate report warning.
report "OSVVM.CoveragePkg.MakeBin (called by GenBin, IllegalBin, or IgnoreBin) NumBin <= 0 generated NULL_BIN"
severity WARNING ;
-- Alerts make this impure.
-- Alert(OSVVM_COVERAGE_ALERTLOG_ID, "CoveragePkg.MakeBin (called by GenBin, IllegalBin, IgnoreBin): NumBin must be <= 0", WARNING) ;
return NULL_BIN ;
elsif NumBin = 1 then
iCovBin(1) := (
BinVal => (1 => (Min, Max)),
Action => Action,
Count => 0,
Weight => Weight,
AtLeast => AtLeast
) ;
return iCovBin ;
else
-- Using type real to work around issues with integer sizing
iCurMin := Min ;
rCurMin := real(iCurMin) ;
rMax := real(Max) ;
rRemainingBins := (minimum( real(NumBin), rMax - rCurMin + 1.0 )) ;
TotalBins := integer(rRemainingBins) ;
for i in iCovBin'range loop
rNumItemsInBin := trunc((rMax - rCurMin + 1.0) / rRemainingBins) ; -- Max - Min can be larger than integer range.
iCurMax := iCurMin - integer(-rNumItemsInBin + 1.0) ; -- Keep: the "minus negative" works around a simulator bounds issue found in 2015.06
iCovBin(i) := (
BinVal => (1 => (iCurMin, iCurMax)),
Action => Action,
Count => 0,
Weight => Weight,
AtLeast => AtLeast
) ;
rRemainingBins := rRemainingBins - 1.0 ;
exit when rRemainingBins = 0.0 ;
iCurMin := iCurMax + 1 ;
rCurMin := real(iCurMin) ;
end loop ;
return iCovBin(1 to TotalBins) ;
end if ;
end function MakeBin ;
------------------------------------------------------------
-- package local, Used by GenBin, IllegalBin, and IgnoreBin
function MakeBin(
------------------------------------------------------------
A : integer_vector ;
AtLeast : integer ;
Weight : integer ;
Action : integer
) return CovBinType is
alias NewA : integer_vector(1 to A'length) is A ;
variable iCovBin : CovBinType(1 to A'length) ;
begin
if A'length <= 0 then
-- Similar to NULL ranges. Only generate report warning.
report "OSVVM.CoveragePkg.MakeBin (called by GenBin, IllegalBin, or IgnoreBin) integer_vector length <= 0 generated NULL_BIN"
severity WARNING ;
-- Alerts make this impure.
-- Alert(OSVVM_COVERAGE_ALERTLOG_ID, "CoveragePkg.MakeBin (GenBin, IllegalBin, IgnoreBin): integer_vector parameter must have values", WARNING) ;
return NULL_BIN ;
else
for i in NewA'Range loop
iCovBin(i) := (
BinVal => (i => (NewA(i), NewA(i)) ),
Action => Action,
Count => 0,
Weight => Weight,
AtLeast => AtLeast
) ;
end loop ;
return iCovBin ;
end if ;
end function MakeBin ;
------------------------------------------------------------
function GenBin(
------------------------------------------------------------
AtLeast : integer ;
Weight : integer ;
Min, Max : integer ;
NumBin : integer
) return CovBinType is
begin
return MakeBin(
Min => Min,
Max => Max,
NumBin => NumBin,
AtLeast => AtLeast,
Weight => Weight,
Action => COV_COUNT
) ;
end function GenBin ;
------------------------------------------------------------
function GenBin(
------------------------------------------------------------
AtLeast : integer ;
Min, Max : integer ;
NumBin : integer
) return CovBinType is
begin
return MakeBin(
Min => Min,
Max => Max,
NumBin => NumBin,
AtLeast => AtLeast,
Weight => 1,
Action => COV_COUNT
) ;
end function GenBin ;
------------------------------------------------------------
function GenBin( Min, Max, NumBin : integer ) return CovBinType is
------------------------------------------------------------
begin
return MakeBin(
Min => Min,
Max => Max,
NumBin => NumBin,
AtLeast => 0,
Weight => 0,
Action => COV_COUNT
) ;
end function GenBin ;
------------------------------------------------------------
function GenBin ( Min, Max : integer) return CovBinType is
------------------------------------------------------------
begin
-- create a separate CovBin for each value
-- AtLeast and Weight = 1 (must use longer version to specify)
return MakeBin(
Min => Min,
Max => Max,
NumBin => Max - Min + 1,
AtLeast => 0,
Weight => 0,
Action => COV_COUNT
) ;
end function GenBin ;
------------------------------------------------------------
function GenBin ( A : integer ) return CovBinType is
------------------------------------------------------------
begin
-- create a single CovBin for A.
-- AtLeast and Weight = 1 (must use longer version to specify)
return MakeBin(
Min => A,
Max => A,
NumBin => 1,
AtLeast => 0,
Weight => 0,
Action => COV_COUNT
) ;
end function GenBin ;
------------------------------------------------------------
function GenBin(
------------------------------------------------------------
AtLeast : integer ;
Weight : integer ;
A : integer_vector
) return CovBinType is
begin
return MakeBin(
A => A,
AtLeast => AtLeast,
Weight => Weight,
Action => COV_COUNT
) ;
end function GenBin ;
------------------------------------------------------------
function GenBin ( AtLeast : integer ; A : integer_vector ) return CovBinType is
------------------------------------------------------------
begin
return MakeBin(
A => A,
AtLeast => AtLeast,
Weight => 0,
Action => COV_COUNT
) ;
end function GenBin ;
------------------------------------------------------------
function GenBin ( A : integer_vector ) return CovBinType is
------------------------------------------------------------
begin
return MakeBin(
A => A,
AtLeast => 0,
Weight => 0,
Action => COV_COUNT
) ;
end function GenBin ;
------------------------------------------------------------
function IllegalBin ( Min, Max, NumBin : integer ) return CovBinType is
------------------------------------------------------------
begin
return MakeBin(
Min => Min,
Max => Max,
NumBin => NumBin,
AtLeast => 0,
Weight => 0,
Action => COV_ILLEGAL
) ;
end function IllegalBin ;
------------------------------------------------------------
function IllegalBin ( Min, Max : integer ) return CovBinType is
------------------------------------------------------------
begin
-- default, generate one CovBin with the entire range of values
return MakeBin(
Min => Min,
Max => Max,
NumBin => 1,
AtLeast => 0,
Weight => 0,
Action => COV_ILLEGAL
) ;
end function IllegalBin ;
------------------------------------------------------------
function IllegalBin ( A : integer ) return CovBinType is
------------------------------------------------------------
begin
return MakeBin(
Min => A,
Max => A,
NumBin => 1,
AtLeast => 0,
Weight => 0,
Action => COV_ILLEGAL
) ;
end function IllegalBin ;
-- IgnoreBin should never have an AtLeast parameter
------------------------------------------------------------
function IgnoreBin (Min, Max, NumBin : integer) return CovBinType is
------------------------------------------------------------
begin
return MakeBin(
Min => Min,
Max => Max,
NumBin => NumBin,
AtLeast => 0,
Weight => 0,
Action => COV_IGNORE
) ;
end function IgnoreBin ;
------------------------------------------------------------
function IgnoreBin (Min, Max : integer) return CovBinType is
------------------------------------------------------------
begin
-- default, generate one CovBin with the entire range of values
return MakeBin(
Min => Min,
Max => Max,
NumBin => 1,
AtLeast => 0,
Weight => 0,
Action => COV_IGNORE
) ;
end function IgnoreBin ;
------------------------------------------------------------
function IgnoreBin (A : integer) return CovBinType is
------------------------------------------------------------
begin
return MakeBin(
Min => A,
Max => A,
NumBin => 1,
AtLeast => 0,
Weight => 0,
Action => COV_IGNORE
) ;
end function IgnoreBin ;
------------------------------------------------------------
function GenCross( -- 2
-- Cross existing bins
-- Use AddCross for adding values directly to coverage database
-- Use GenCross for constants
------------------------------------------------------------
AtLeast : integer ;
Weight : integer ;
Bin1, Bin2 : CovBinType
) return CovMatrix2Type is
constant BIN_LENS : integer_vector := BinLengths(Bin1, Bin2) ;
constant NUM_NEW_BINS : integer := CalcNumCrossBins(BIN_LENS) ;
variable BinIndex : integer_vector(1 to BIN_LENS'length) := (others => 1) ;
variable CrossBins : CovBinType(BinIndex'range) ;
variable Action : integer ;
variable iCovMatrix : CovMatrix2Type(1 to NUM_NEW_BINS) ;
begin
for MatrixIndex in iCovMatrix'range loop
CrossBins := ConcatenateBins(BinIndex, Bin1, Bin2) ;
Action := MergeState(CrossBins) ;
iCovMatrix(MatrixIndex).action := Action ;
iCovMatrix(MatrixIndex).count := 0 ;
iCovMatrix(MatrixIndex).BinVal := MergeBinVal(CrossBins) ;
iCovMatrix(MatrixIndex).AtLeast := MergeAtLeast( Action, AtLeast, CrossBins) ;
iCovMatrix(MatrixIndex).Weight := MergeWeight ( Action, Weight, CrossBins) ;
IncBinIndex( BinIndex, BIN_LENS ) ; -- increment right most one, then if overflow, increment next
end loop ;
return iCovMatrix ;
end function GenCross ;
------------------------------------------------------------
function GenCross(AtLeast : integer ; Bin1, Bin2 : CovBinType) return CovMatrix2Type is
-- Cross existing bins -- use AddCross instead
------------------------------------------------------------
begin
return GenCross(AtLeast, 1, Bin1, Bin2) ;
end function GenCross ;
------------------------------------------------------------
function GenCross(Bin1, Bin2 : CovBinType) return CovMatrix2Type is
-- Cross existing bins -- use AddCross instead
------------------------------------------------------------
begin
return GenCross(1, 1, Bin1, Bin2) ;
end function GenCross ;
------------------------------------------------------------
function GenCross( -- 3
------------------------------------------------------------
AtLeast : integer ;
Weight : integer ;
Bin1, Bin2, Bin3 : CovBinType
) return CovMatrix3Type is
constant BIN_LENS : integer_vector := BinLengths(Bin1, Bin2, Bin3) ;
constant NUM_NEW_BINS : integer := CalcNumCrossBins(BIN_LENS) ;
variable BinIndex : integer_vector(1 to BIN_LENS'length) := (others => 1) ;
variable CrossBins : CovBinType(BinIndex'range) ;
variable Action : integer ;
variable iCovMatrix : CovMatrix3Type(1 to NUM_NEW_BINS) ;
begin
for MatrixIndex in iCovMatrix'range loop
CrossBins := ConcatenateBins(BinIndex, Bin1, Bin2, Bin3) ;
Action := MergeState(CrossBins) ;
iCovMatrix(MatrixIndex).action := Action ;
iCovMatrix(MatrixIndex).count := 0 ;
iCovMatrix(MatrixIndex).BinVal := MergeBinVal(CrossBins) ;
iCovMatrix(MatrixIndex).AtLeast := MergeAtLeast( Action, AtLeast, CrossBins) ;
iCovMatrix(MatrixIndex).Weight := MergeWeight ( Action, Weight, CrossBins) ;
IncBinIndex( BinIndex, BIN_LENS ) ; -- increment right most one, then if overflow, increment next
end loop ;
return iCovMatrix ;
end function GenCross ;
------------------------------------------------------------
function GenCross( AtLeast : integer ; Bin1, Bin2, Bin3 : CovBinType ) return CovMatrix3Type is
------------------------------------------------------------
begin
return GenCross(AtLeast, 1, Bin1, Bin2, Bin3) ;
end function GenCross ;
------------------------------------------------------------
function GenCross( Bin1, Bin2, Bin3 : CovBinType ) return CovMatrix3Type is
------------------------------------------------------------
begin
return GenCross(1, 1, Bin1, Bin2, Bin3) ;
end function GenCross ;
------------------------------------------------------------
function GenCross( -- 4
------------------------------------------------------------
AtLeast : integer ;
Weight : integer ;
Bin1, Bin2, Bin3, Bin4 : CovBinType
) return CovMatrix4Type is
constant BIN_LENS : integer_vector := BinLengths(Bin1, Bin2, Bin3, Bin4) ;
constant NUM_NEW_BINS : integer := CalcNumCrossBins(BIN_LENS) ;
variable BinIndex : integer_vector(1 to BIN_LENS'length) := (others => 1) ;
variable CrossBins : CovBinType(BinIndex'range) ;
variable Action : integer ;
variable iCovMatrix : CovMatrix4Type(1 to NUM_NEW_BINS) ;
begin
for MatrixIndex in iCovMatrix'range loop
CrossBins := ConcatenateBins(BinIndex, Bin1, Bin2, Bin3, Bin4) ;
Action := MergeState(CrossBins) ;
iCovMatrix(MatrixIndex).action := Action ;
iCovMatrix(MatrixIndex).count := 0 ;
iCovMatrix(MatrixIndex).BinVal := MergeBinVal(CrossBins) ;
iCovMatrix(MatrixIndex).AtLeast := MergeAtLeast( Action, AtLeast, CrossBins) ;
iCovMatrix(MatrixIndex).Weight := MergeWeight ( Action, Weight, CrossBins) ;
IncBinIndex( BinIndex, BIN_LENS ) ; -- increment right most one, then if overflow, increment next
end loop ;
return iCovMatrix ;
end function GenCross ;
------------------------------------------------------------
function GenCross( AtLeast : integer ; Bin1, Bin2, Bin3, Bin4 : CovBinType ) return CovMatrix4Type is
------------------------------------------------------------
begin
return GenCross(AtLeast, 1, Bin1, Bin2, Bin3, Bin4) ;
end function GenCross ;
------------------------------------------------------------
function GenCross( Bin1, Bin2, Bin3, Bin4 : CovBinType ) return CovMatrix4Type is
------------------------------------------------------------
begin
return GenCross(1, 1, Bin1, Bin2, Bin3, Bin4) ;
end function GenCross ;
------------------------------------------------------------
function GenCross( -- 5
------------------------------------------------------------
AtLeast : integer ;
Weight : integer ;
Bin1, Bin2, Bin3, Bin4, Bin5 : CovBinType
) return CovMatrix5Type is
constant BIN_LENS : integer_vector := BinLengths(Bin1, Bin2, Bin3, Bin4, Bin5) ;
constant NUM_NEW_BINS : integer := CalcNumCrossBins(BIN_LENS) ;
variable BinIndex : integer_vector(1 to BIN_LENS'length) := (others => 1) ;
variable CrossBins : CovBinType(BinIndex'range) ;
variable Action : integer ;
variable iCovMatrix : CovMatrix5Type(1 to NUM_NEW_BINS) ;
begin
for MatrixIndex in iCovMatrix'range loop
CrossBins := ConcatenateBins(BinIndex, Bin1, Bin2, Bin3, Bin4, Bin5) ;
Action := MergeState(CrossBins) ;
iCovMatrix(MatrixIndex).action := Action ;
iCovMatrix(MatrixIndex).count := 0 ;
iCovMatrix(MatrixIndex).BinVal := MergeBinVal(CrossBins) ;
iCovMatrix(MatrixIndex).AtLeast := MergeAtLeast( Action, AtLeast, CrossBins) ;
iCovMatrix(MatrixIndex).Weight := MergeWeight ( Action, Weight, CrossBins) ;
IncBinIndex( BinIndex, BIN_LENS ) ; -- increment right most one, then if overflow, increment next
end loop ;
return iCovMatrix ;
end function GenCross ;
------------------------------------------------------------
function GenCross( AtLeast : integer ; Bin1, Bin2, Bin3, Bin4, Bin5 : CovBinType ) return CovMatrix5Type is
------------------------------------------------------------
begin
return GenCross(AtLeast, 1, Bin1, Bin2, Bin3, Bin4, Bin5) ;
end function GenCross ;
------------------------------------------------------------
function GenCross( Bin1, Bin2, Bin3, Bin4, Bin5 : CovBinType ) return CovMatrix5Type is
------------------------------------------------------------
begin
return GenCross(1, 1, Bin1, Bin2, Bin3, Bin4, Bin5) ;
end function GenCross ;
------------------------------------------------------------
function GenCross( -- 6
------------------------------------------------------------
AtLeast : integer ;
Weight : integer ;
Bin1, Bin2, Bin3, Bin4, Bin5, Bin6 : CovBinType
) return CovMatrix6Type is
constant BIN_LENS : integer_vector := BinLengths(Bin1, Bin2, Bin3, Bin4, Bin5, Bin6) ;
constant NUM_NEW_BINS : integer := CalcNumCrossBins(BIN_LENS) ;
variable BinIndex : integer_vector(1 to BIN_LENS'length) := (others => 1) ;
variable CrossBins : CovBinType(BinIndex'range) ;
variable Action : integer ;
variable iCovMatrix : CovMatrix6Type(1 to NUM_NEW_BINS) ;
begin
for MatrixIndex in iCovMatrix'range loop
CrossBins := ConcatenateBins(BinIndex, Bin1, Bin2, Bin3, Bin4, Bin5, Bin6) ;
Action := MergeState(CrossBins) ;
iCovMatrix(MatrixIndex).action := Action ;
iCovMatrix(MatrixIndex).count := 0 ;
iCovMatrix(MatrixIndex).BinVal := MergeBinVal(CrossBins) ;
iCovMatrix(MatrixIndex).AtLeast := MergeAtLeast( Action, AtLeast, CrossBins) ;
iCovMatrix(MatrixIndex).Weight := MergeWeight ( Action, Weight, CrossBins) ;
IncBinIndex( BinIndex, BIN_LENS ) ; -- increment right most one, then if overflow, increment next
end loop ;
return iCovMatrix ;
end function GenCross ;
------------------------------------------------------------
function GenCross( AtLeast : integer ; Bin1, Bin2, Bin3, Bin4, Bin5, Bin6 : CovBinType ) return CovMatrix6Type is
------------------------------------------------------------
begin
return GenCross(AtLeast, 1, Bin1, Bin2, Bin3, Bin4, Bin5, Bin6) ;
end function GenCross ;
------------------------------------------------------------
function GenCross( Bin1, Bin2, Bin3, Bin4, Bin5, Bin6 : CovBinType ) return CovMatrix6Type is
------------------------------------------------------------
begin
return GenCross(1, 1, Bin1, Bin2, Bin3, Bin4, Bin5, Bin6) ;
end function GenCross ;
------------------------------------------------------------
function GenCross( -- 7
------------------------------------------------------------
AtLeast : integer ;
Weight : integer ;
Bin1, Bin2, Bin3, Bin4, Bin5, Bin6, Bin7 : CovBinType
) return CovMatrix7Type is
constant BIN_LENS : integer_vector := BinLengths(Bin1, Bin2, Bin3, Bin4, Bin5, Bin6, Bin7) ;
constant NUM_NEW_BINS : integer := CalcNumCrossBins(BIN_LENS) ;
variable BinIndex : integer_vector(1 to BIN_LENS'length) := (others => 1) ;
variable CrossBins : CovBinType(BinIndex'range) ;
variable Action : integer ;
variable iCovMatrix : CovMatrix7Type(1 to NUM_NEW_BINS) ;
begin
for MatrixIndex in iCovMatrix'range loop
CrossBins := ConcatenateBins(BinIndex, Bin1, Bin2, Bin3, Bin4, Bin5, Bin6, Bin7) ;
Action := MergeState(CrossBins) ;
iCovMatrix(MatrixIndex).action := Action ;
iCovMatrix(MatrixIndex).count := 0 ;
iCovMatrix(MatrixIndex).BinVal := MergeBinVal(CrossBins) ;
iCovMatrix(MatrixIndex).AtLeast := MergeAtLeast( Action, AtLeast, CrossBins) ;
iCovMatrix(MatrixIndex).Weight := MergeWeight ( Action, Weight, CrossBins) ;
IncBinIndex( BinIndex, BIN_LENS ) ; -- increment right most one, then if overflow, increment next
end loop ;
return iCovMatrix ;
end function GenCross ;
------------------------------------------------------------
function GenCross( AtLeast : integer ; Bin1, Bin2, Bin3, Bin4, Bin5, Bin6, Bin7 : CovBinType ) return CovMatrix7Type is
------------------------------------------------------------
begin
return GenCross(AtLeast, 1, Bin1, Bin2, Bin3, Bin4, Bin5, Bin6, Bin7) ;
end function GenCross ;
------------------------------------------------------------
function GenCross( Bin1, Bin2, Bin3, Bin4, Bin5, Bin6, Bin7 : CovBinType ) return CovMatrix7Type is
------------------------------------------------------------
begin
return GenCross(1, 1, Bin1, Bin2, Bin3, Bin4, Bin5, Bin6, Bin7) ;
end function GenCross ;
------------------------------------------------------------
function GenCross( -- 8
------------------------------------------------------------
AtLeast : integer ;
Weight : integer ;
Bin1, Bin2, Bin3, Bin4, Bin5, Bin6, Bin7, Bin8 : CovBinType
) return CovMatrix8Type is
constant BIN_LENS : integer_vector := BinLengths(Bin1, Bin2, Bin3, Bin4, Bin5, Bin6, Bin7, Bin8) ;
constant NUM_NEW_BINS : integer := CalcNumCrossBins(BIN_LENS) ;
variable BinIndex : integer_vector(1 to BIN_LENS'length) := (others => 1) ;
variable CrossBins : CovBinType(BinIndex'range) ;
variable Action : integer ;
variable iCovMatrix : CovMatrix8Type(1 to NUM_NEW_BINS) ;
begin
for MatrixIndex in iCovMatrix'range loop
CrossBins := ConcatenateBins(BinIndex, Bin1, Bin2, Bin3, Bin4, Bin5, Bin6, Bin7, Bin8) ;
Action := MergeState(CrossBins) ;
iCovMatrix(MatrixIndex).action := Action ;
iCovMatrix(MatrixIndex).count := 0 ;
iCovMatrix(MatrixIndex).BinVal := MergeBinVal(CrossBins) ;
iCovMatrix(MatrixIndex).AtLeast := MergeAtLeast( Action, AtLeast, CrossBins) ;
iCovMatrix(MatrixIndex).Weight := MergeWeight ( Action, Weight, CrossBins) ;
IncBinIndex( BinIndex, BIN_LENS ) ; -- increment right most one, then if overflow, increment next
end loop ;
return iCovMatrix ;
end function GenCross ;
------------------------------------------------------------
function GenCross( AtLeast : integer ; Bin1, Bin2, Bin3, Bin4, Bin5, Bin6, Bin7, Bin8 : CovBinType ) return CovMatrix8Type is
------------------------------------------------------------
begin
return GenCross(AtLeast, 1, Bin1, Bin2, Bin3, Bin4, Bin5, Bin6, Bin7, Bin8) ;
end function GenCross ;
------------------------------------------------------------
function GenCross( Bin1, Bin2, Bin3, Bin4, Bin5, Bin6, Bin7, Bin8 : CovBinType ) return CovMatrix8Type is
------------------------------------------------------------
begin
return GenCross(1, 1, Bin1, Bin2, Bin3, Bin4, Bin5, Bin6, Bin7, Bin8) ;
end function GenCross ;
------------------------------------------------------------
function GenCross( -- 9
------------------------------------------------------------
AtLeast : integer ;
Weight : integer ;
Bin1, Bin2, Bin3, Bin4, Bin5, Bin6, Bin7, Bin8, Bin9 : CovBinType
) return CovMatrix9Type is
constant BIN_LENS : integer_vector := BinLengths(Bin1, Bin2, Bin3, Bin4, Bin5, Bin6, Bin7, Bin8, Bin9) ;
constant NUM_NEW_BINS : integer := CalcNumCrossBins(BIN_LENS) ;
variable BinIndex : integer_vector(1 to BIN_LENS'length) := (others => 1) ;
variable CrossBins : CovBinType(BinIndex'range) ;
variable Action : integer ;
variable iCovMatrix : CovMatrix9Type(1 to NUM_NEW_BINS) ;
begin
for MatrixIndex in iCovMatrix'range loop
CrossBins := ConcatenateBins(BinIndex, Bin1, Bin2, Bin3, Bin4, Bin5, Bin6, Bin7, Bin8, Bin9) ;
Action := MergeState(CrossBins) ;
iCovMatrix(MatrixIndex).action := Action ;
iCovMatrix(MatrixIndex).count := 0 ;
iCovMatrix(MatrixIndex).BinVal := MergeBinVal(CrossBins) ;
iCovMatrix(MatrixIndex).AtLeast := MergeAtLeast( Action, AtLeast, CrossBins) ;
iCovMatrix(MatrixIndex).Weight := MergeWeight ( Action, Weight, CrossBins) ;
IncBinIndex( BinIndex, BIN_LENS ) ; -- increment right most one, then if overflow, increment next
end loop ;
return iCovMatrix ;
end function GenCross ;
------------------------------------------------------------
function GenCross( AtLeast : integer ; Bin1, Bin2, Bin3, Bin4, Bin5, Bin6, Bin7, Bin8, Bin9 : CovBinType ) return CovMatrix9Type is
------------------------------------------------------------
begin
return GenCross(AtLeast, 1, Bin1, Bin2, Bin3, Bin4, Bin5, Bin6, Bin7, Bin8, Bin9) ;
end function GenCross ;
------------------------------------------------------------
function GenCross( Bin1, Bin2, Bin3, Bin4, Bin5, Bin6, Bin7, Bin8, Bin9 : CovBinType ) return CovMatrix9Type is
------------------------------------------------------------
begin
return GenCross(1, 1, Bin1, Bin2, Bin3, Bin4, Bin5, Bin6, Bin7, Bin8, Bin9) ;
end function GenCross ;
------------------------------------------------------------
function to_integer ( B : boolean ) return integer is
------------------------------------------------------------
begin
if B then
return 1 ;
else
return 0 ;
end if ;
end function to_integer ;
------------------------------------------------------------
function CheckInteger_1_0 ( I : integer ) return boolean is
-------------------------------------------------------------
begin
case I is
when 0 | 1 => return TRUE ;
when others => return FALSE ;
end case ;
end function CheckInteger_1_0 ;
------------------------------------------------------------
function local_to_boolean ( I : integer ) return boolean is
------------------------------------------------------------
begin
case I is
when 1 => return TRUE ;
when 0 => return FALSE ;
when others =>
return FALSE ;
end case ;
end function local_to_boolean ;
------------------------------------------------------------
function to_boolean ( I : integer ) return boolean is
------------------------------------------------------------
begin
if not CheckInteger_1_0(I) then
report
"CoveragePkg.to_boolean: invalid integer value: " & to_string(I) &
" returning FALSE" severity WARNING ;
end if ;
return local_to_boolean(I) ;
end function to_boolean ;
------------------------------------------------------------
function to_integer ( SL : std_logic ) return integer is
-------------------------------------------------------------
begin
case SL is
when '1' | 'H' => return 1 ;
when '0' | 'L' => return 0 ;
when others => return -1 ;
end case ;
end function to_integer ;
------------------------------------------------------------
function local_to_std_logic ( I : integer ) return std_logic is
-------------------------------------------------------------
begin
case I is
when 1 => return '1' ;
when 0 => return '0' ;
when others => return 'X' ;
end case ;
end function local_to_std_logic ;
------------------------------------------------------------
function to_std_logic ( I : integer ) return std_logic is
-------------------------------------------------------------
begin
if not CheckInteger_1_0(I) then
report
"CoveragePkg.to_std_logic: invalid integer value: " & to_string(I) &
" returning X" severity WARNING ;
end if ;
return local_to_std_logic(I) ;
end function to_std_logic ;
------------------------------------------------------------
function to_integer_vector ( BV : boolean_vector ) return integer_vector is
------------------------------------------------------------
variable result : integer_vector(BV'range) ;
begin
for i in BV'range loop
result(i) := to_integer(BV(i)) ;
end loop ;
return result ;
end function to_integer_vector ;
------------------------------------------------------------
function to_boolean_vector ( IV : integer_vector ) return boolean_vector is
------------------------------------------------------------
variable result : boolean_vector(IV'range) ;
variable HasError : boolean := FALSE ;
begin
for i in IV'range loop
result(i) := local_to_boolean(IV(i)) ;
if not CheckInteger_1_0(IV(i)) then
HasError := TRUE ;
end if ;
end loop ;
if HasError then
report
"CoveragePkg.to_boolean_vector: invalid integer value" &
" returning FALSE" severity WARNING ;
end if ;
return result ;
end function to_boolean_vector ;
------------------------------------------------------------
function to_integer_vector ( SLV : std_logic_vector ) return integer_vector is
-------------------------------------------------------------
variable result : integer_vector(SLV'range) ;
begin
for i in SLV'range loop
result(i) := to_integer(SLV(i)) ;
end loop ;
return result ;
end function to_integer_vector ;
------------------------------------------------------------
function to_std_logic_vector ( IV : integer_vector ) return std_logic_vector is
-------------------------------------------------------------
variable result : std_logic_vector(IV'range) ;
variable HasError : boolean := FALSE ;
begin
for i in IV'range loop
result(i) := local_to_std_logic(IV(i)) ;
if not CheckInteger_1_0(IV(i)) then
HasError := TRUE ;
end if ;
end loop ;
if HasError then
report
"CoveragePkg.to_std_logic_vector: invalid integer value" &
" returning FALSE" severity WARNING ;
end if ;
return result ;
end function to_std_logic_vector ;
end package body CoveragePkg ; |
-- $Id: sys_conf1_sim.vhd 441 2011-12-20 17:01:16Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for sys_tst_serloop1_n2 (for test bench)
--
-- Dependencies: -
-- Tool versions: xst 11.4; ghdl 0.26
-- Revision History:
-- Date Rev Version Comment
-- 2011-12-16 439 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
package sys_conf is
-- in simulation a usec is shortened to 10 cycles (0.2 usec) and a msec
-- to 50 cycles (1 usec). This affects the pulse generators (usec) and
-- mainly the autobauder. A break will be detected after 128 msec periods,
-- this in simulation after 128 usec or 6400 cycles. This is compatible with
-- bitrates of 115200 baud or higher (115200 <-> 8.68 usec <-> 521 cycles)
constant sys_conf_clkdiv_usecdiv : integer := 10; -- default usec
constant sys_conf_clkdiv_msecdiv : integer := 5; -- shortened !
constant sys_conf_hio_debounce : boolean := false; -- no debouncers
constant sys_conf_uart_cdinit : integer := 1-1; -- 1 cycle/bit in sim
end package sys_conf;
|
-- $Id: sys_conf1_sim.vhd 441 2011-12-20 17:01:16Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for sys_tst_serloop1_n2 (for test bench)
--
-- Dependencies: -
-- Tool versions: xst 11.4; ghdl 0.26
-- Revision History:
-- Date Rev Version Comment
-- 2011-12-16 439 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
package sys_conf is
-- in simulation a usec is shortened to 10 cycles (0.2 usec) and a msec
-- to 50 cycles (1 usec). This affects the pulse generators (usec) and
-- mainly the autobauder. A break will be detected after 128 msec periods,
-- this in simulation after 128 usec or 6400 cycles. This is compatible with
-- bitrates of 115200 baud or higher (115200 <-> 8.68 usec <-> 521 cycles)
constant sys_conf_clkdiv_usecdiv : integer := 10; -- default usec
constant sys_conf_clkdiv_msecdiv : integer := 5; -- shortened !
constant sys_conf_hio_debounce : boolean := false; -- no debouncers
constant sys_conf_uart_cdinit : integer := 1-1; -- 1 cycle/bit in sim
end package sys_conf;
|
package pkg is
end package;
context ctx is
library lib;
use lib.pkg.all;
end context;
|
package pkg is
end package;
context ctx is
library lib;
use lib.pkg.all;
end context;
|
package pkg is
end package;
context ctx is
library lib;
use lib.pkg.all;
end context;
|
-- NEED RESULT: ARCH00409.P1: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00409: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00409: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00409: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00409: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: P1: Inertial transactions completed entirely passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00409
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 9.5 (3)
-- 9.5.2 (1)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00409(ARCH00409)
-- ENT00409_Test_Bench(ARCH00409_Test_Bench)
--
-- REVISION HISTORY:
--
-- 30-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
entity ENT00409 is
end ENT00409 ;
--
--
architecture ARCH00409 of ENT00409 is
subtype chk_sig_type is integer range -1 to 100 ;
signal chk_st_rec3 : chk_sig_type := -1 ;
--
subtype chk_time_type is Time ;
signal s_st_rec3_savt : chk_time_type := 0 ns ;
--
subtype chk_cnt_type is Integer ;
signal s_st_rec3_cnt : chk_cnt_type := 0 ;
--
type select_type is range 1 to 6 ;
signal st_rec3_select : select_type := 1 ;
--
signal s_st_rec3 : st_rec3
:= c_st_rec3_1 ;
--
begin
CHG1 :
process
variable correct : boolean ;
begin
case s_st_rec3_cnt is
when 0
=> null ;
-- s_st_rec3.f3(lowb,true) <=
-- c_st_rec3_2.f3(lowb,true) after 10 ns,
-- c_st_rec3_1.f3(lowb,true) after 20 ns ;
--
when 1
=> correct :=
s_st_rec3.f3(lowb,true) =
c_st_rec3_2.f3(lowb,true) and
(s_st_rec3_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec3.f3(lowb,true) =
c_st_rec3_1.f3(lowb,true) and
(s_st_rec3_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00409.P1" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_rec3_select <= transport 2 ;
-- s_st_rec3.f3(lowb,true) <=
-- c_st_rec3_2.f3(lowb,true) after 10 ns ,
-- c_st_rec3_1.f3(lowb,true) after 20 ns ,
-- c_st_rec3_2.f3(lowb,true) after 30 ns ,
-- c_st_rec3_1.f3(lowb,true) after 40 ns ;
--
when 3
=> correct :=
s_st_rec3.f3(lowb,true) =
c_st_rec3_2.f3(lowb,true) and
(s_st_rec3_savt + 10 ns) = Std.Standard.Now ;
st_rec3_select <= transport 3 ;
-- s_st_rec3.f3(lowb,true) <=
-- c_st_rec3_1.f3(lowb,true) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec3.f3(lowb,true) =
c_st_rec3_1.f3(lowb,true) and
(s_st_rec3_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00409" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_rec3_select <= transport 4 ;
-- s_st_rec3.f3(lowb,true) <=
-- c_st_rec3_1.f3(lowb,true) after 100 ns ;
--
when 5
=> correct :=
correct and
s_st_rec3.f3(lowb,true) =
c_st_rec3_1.f3(lowb,true) and
(s_st_rec3_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00409" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
st_rec3_select <= transport 5 ;
-- s_st_rec3.f3(lowb,true) <=
-- c_st_rec3_2.f3(lowb,true) after 10 ns ,
-- c_st_rec3_1.f3(lowb,true) after 20 ns ,
-- c_st_rec3_2.f3(lowb,true) after 30 ns ,
-- c_st_rec3_1.f3(lowb,true) after 40 ns ;
--
when 6
=> correct :=
correct and
s_st_rec3.f3(lowb,true) =
c_st_rec3_2.f3(lowb,true) and
(s_st_rec3_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00409" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_rec3_select <= transport 6 ;
-- Last transaction above is marked
-- s_st_rec3.f3(lowb,true) <=
-- c_st_rec3_1.f3(lowb,true) after 40 ns ;
--
when 7
=> correct :=
correct and
s_st_rec3.f3(lowb,true) =
c_st_rec3_1.f3(lowb,true) and
(s_st_rec3_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_st_rec3.f3(lowb,true) =
c_st_rec3_1.f3(lowb,true) and
(s_st_rec3_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00409" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00409" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_st_rec3_savt <= transport Std.Standard.Now ;
chk_st_rec3 <= transport s_st_rec3_cnt
after (1 us - Std.Standard.Now) ;
s_st_rec3_cnt <= transport s_st_rec3_cnt + 1 ;
wait until (not s_st_rec3.f3(lowb,true)'Quiet) and
(s_st_rec3_savt /= Std.Standard.Now) ;
--
end process CHG1 ;
--
PGEN_CHKP_1 :
process ( chk_st_rec3 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P1" ,
"Inertial transactions completed entirely",
chk_st_rec3 = 8 ) ;
end if ;
end process PGEN_CHKP_1 ;
--
--
with st_rec3_select select
s_st_rec3.f3(lowb,true) <=
c_st_rec3_2.f3(lowb,true) after 10 ns,
c_st_rec3_1.f3(lowb,true) after 20 ns
when 1,
--
c_st_rec3_2.f3(lowb,true) after 10 ns ,
c_st_rec3_1.f3(lowb,true) after 20 ns ,
c_st_rec3_2.f3(lowb,true) after 30 ns ,
c_st_rec3_1.f3(lowb,true) after 40 ns
when 2,
--
c_st_rec3_1.f3(lowb,true) after 5 ns
when 3,
--
c_st_rec3_1.f3(lowb,true) after 100 ns
when 4,
--
c_st_rec3_2.f3(lowb,true) after 10 ns ,
c_st_rec3_1.f3(lowb,true) after 20 ns ,
c_st_rec3_2.f3(lowb,true) after 30 ns ,
c_st_rec3_1.f3(lowb,true) after 40 ns
when 5,
--
-- Last transaction above is marked
c_st_rec3_1.f3(lowb,true) after 40 ns when 6 ;
--
end ARCH00409 ;
--
--
use WORK.STANDARD_TYPES.all ;
entity ENT00409_Test_Bench is
end ENT00409_Test_Bench ;
--
--
architecture ARCH00409_Test_Bench of ENT00409_Test_Bench is
begin
L1:
block
component UUT
end component ;
--
for CIS1 : UUT use entity WORK.ENT00409 ( ARCH00409 ) ;
begin
CIS1 : UUT
;
end block L1 ;
end ARCH00409_Test_Bench ;
|
-- $Id: rbd_eyemon.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2010-2016 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: rbd_eyemon - syn
-- Description: rbus dev: eye monitor for serport's
--
-- Dependencies: memlib/ram_2swsr_wfirst_gen
--
-- Test bench: -
--
-- Target Devices: generic
-- Tool versions: xst 12.1-14.7; viv 2014.4-2016.1; ghdl 0.29-0.33
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2011-04-02 374 12.1 M53d xc3s1000-4 46 154 - 109 s 8.7
-- 2010-12-27 349 12.1 M53d xc3s1000-4 45 147 - 106 s 8.9
--
-- Revision History:
-- Date Rev Version Comment
-- 2016-05-22 767 4.1.1 don't init N_REGS (vivado fix for fsm inference)
-- 2014-09-13 593 4.1 no default rbus addess anymore, def=0
-- 2014-08-15 583 4.0 rb_mreq addr now 16 bit
-- 2011-11-19 427 1.0.3 now numeric_std clean
-- 2011-04-02 375 1.0.2 handle back-to-back chars properly (in sim..)
-- 2010-12-31 352 1.0.1 simplify irb_ack logic
-- 2010-12-27 349 1.0 Initial version
------------------------------------------------------------------------------
--
-- rbus registers:
--
-- Addr Bits Name r/w/f Function
-- 00 cntl r/w/- Control register
-- 03 ena01 r/w/- track 0->1 rxsd transitions
-- 02 ena10 r/w/- track 1->0 rxsd transitions
-- 01 clr r/-/f w: writing a 1 starts memory clear
-- r: 1 indicates clr in progress (512 cyc)
-- 00 go r/w/- enables monitor
-- 01 7:00 rdiv r/w/- Sample rate divider
-- 10 addr r/w/- Address register
-- 9:01 laddr r/w/ line address
-- 00 waddr r/w/ word address
-- 11 15:00 data r/-/- Data register
--
-- data format:
-- word 1 counter msb's
-- word 0 counter lsb's
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.memlib.all;
use work.rblib.all;
entity rbd_eyemon is -- rbus dev: eye monitor for serport's
generic (
RB_ADDR : slv16 := (others=>'0');
RDIV : slv8 := (others=>'0'));
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
RB_MREQ : in rb_mreq_type; -- rbus: request
RB_SRES : out rb_sres_type; -- rbus: response
RXSD : in slbit; -- rx: serial data
RXACT : in slbit -- rx: active (start seen)
);
end entity rbd_eyemon;
architecture syn of rbd_eyemon is
constant rbaddr_cntl : slv2 := "00"; -- cntl address offset
constant rbaddr_rdiv : slv2 := "01"; -- rdiv address offset
constant rbaddr_addr : slv2 := "10"; -- addr address offset
constant rbaddr_data : slv2 := "11"; -- data address offset
constant cntl_rbf_ena01 : integer := 3;
constant cntl_rbf_ena10 : integer := 2;
constant cntl_rbf_clr : integer := 1;
constant cntl_rbf_go : integer := 0;
subtype addr_rbf_laddr is integer range 9 downto 1;
constant addr_rbf_waddr : integer := 0;
type state_type is (
s_idle, -- s_idle: wait for char or clr
s_char, -- s_char: processing a char
s_clr -- s_clr: clear memory
);
type regs_type is record -- state registers
state : state_type; -- state
rbsel : slbit; -- rbus select
go : slbit; -- go flag
clr : slbit; -- clear pending
ena10 : slbit; -- enable 1->0
ena01 : slbit; -- enable 0->1
rdiv : slv8; -- rate divider
laddr : slv9; -- line address
waddr : slbit; -- word address
laddr_1 : slv9; -- line address last cycle
rxsd_1 : slbit; -- rxsd last cycle
memwe : slbit; -- write bram (clr or inc)
memclr : slbit; -- write zero into bram
rdivcnt : slv8; -- rate divider counter
end record regs_type;
constant regs_init : regs_type := (
s_idle, -- state
'0', -- rbsel
'0', -- go (default is off)
'0','0','0', -- clr,ena01,ena10
(others=>'0'), -- rdiv
(others=>'0'), -- laddr
'0', -- waddr
(others=>'0'), -- laddr_1
'0','0','0', -- rxsd_1,memwe,memclr
(others=>'0') -- rdivcnt
);
signal R_REGS : regs_type := regs_init;
signal N_REGS : regs_type; -- don't init (vivado fix for fsm infer)
signal BRAM_ENA : slbit := '0';
signal BRAM_DIA : slv32 := (others=>'0');
signal BRAM_DIB : slv32 := (others=>'0');
signal BRAM_DOA : slv32 := (others=>'0');
begin
BRAM_DIA <= (others=>'0'); -- always 0, no writes on this port
BRAM : ram_2swsr_wfirst_gen
generic map (
AWIDTH => 9,
DWIDTH => 32)
port map (
CLKA => CLK,
CLKB => CLK,
ENA => BRAM_ENA,
ENB => R_REGS.memwe,
WEA => '0',
WEB => R_REGS.memwe,
ADDRA => R_REGS.laddr,
ADDRB => R_REGS.laddr_1,
DIA => BRAM_DIA,
DIB => BRAM_DIB,
DOA => BRAM_DOA,
DOB => open
);
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
R_REGS <= regs_init;
else
R_REGS <= N_REGS;
end if;
end if;
end process proc_regs;
proc_next : process (R_REGS, RB_MREQ, RXSD, RXACT, BRAM_DOA)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
variable irb_ack : slbit := '0';
variable irb_busy : slbit := '0';
variable irb_err : slbit := '0';
variable irb_dout : slv16 := (others=>'0');
variable irbena : slbit := '0';
variable ibramen : slbit := '0';
variable ibramdi : slv32 := (others=>'0');
variable laddr_we : slbit := '0';
variable laddr_clr : slbit := '0';
variable laddr_inc : slbit := '0';
begin
r := R_REGS;
n := R_REGS;
irb_ack := '0';
irb_busy := '0';
irb_err := '0';
irb_dout := (others=>'0');
irbena := RB_MREQ.re or RB_MREQ.we;
ibramen := '0';
laddr_we := '0';
laddr_clr := '0';
laddr_inc := '0';
-- rbus address decoder
n.rbsel := '0';
if RB_MREQ.aval='1' and RB_MREQ.addr(15 downto 2)=RB_ADDR(15 downto 2) then
n.rbsel := '1';
ibramen := '1';
end if;
-- rbus transactions
if r.rbsel = '1' then
irb_ack := irbena; -- ack all accesses
case RB_MREQ.addr(1 downto 0) is
when rbaddr_cntl =>
if RB_MREQ.we = '1' then
n.ena01 := RB_MREQ.din(cntl_rbf_ena01);
n.ena10 := RB_MREQ.din(cntl_rbf_ena10);
if RB_MREQ.din(cntl_rbf_clr) = '1' then
n.clr := '1';
end if;
n.go := RB_MREQ.din(cntl_rbf_go);
end if;
when rbaddr_rdiv =>
if RB_MREQ.we = '1' then
n.rdiv := RB_MREQ.din(n.rdiv'range);
end if;
when rbaddr_addr =>
if RB_MREQ.we = '1' then
laddr_we := '1';
n.waddr := RB_MREQ.din(addr_rbf_waddr);
end if;
when rbaddr_data =>
if RB_MREQ.we='1' then
irb_err := '1';
end if;
if RB_MREQ.re = '1' then
if r.go='0' and r.clr='0' and r.state=s_idle then
n.waddr := not r.waddr;
if r.waddr = '1' then
laddr_inc := '1';
end if;
else
irb_err := '1';
end if;
end if;
when others => null;
end case;
end if;
-- rbus output driver
if r.rbsel = '1' then
case RB_MREQ.addr(1 downto 0) is
when rbaddr_cntl =>
irb_dout(cntl_rbf_ena01) := r.ena01;
irb_dout(cntl_rbf_ena10) := r.ena10;
irb_dout(cntl_rbf_clr) := r.clr;
irb_dout(cntl_rbf_go) := r.go;
when rbaddr_rdiv =>
irb_dout(r.rdiv'range) := r.rdiv;
when rbaddr_addr =>
irb_dout(addr_rbf_laddr) := r.laddr;
irb_dout(addr_rbf_waddr) := r.waddr;
when rbaddr_data =>
case r.waddr is
when '1' => irb_dout := BRAM_DOA(31 downto 16);
when '0' => irb_dout := BRAM_DOA(15 downto 0);
when others => null;
end case;
when others => null;
end case;
end if;
-- eye monitor
n.memwe := '0';
n.memclr := '0';
case r.state is
when s_idle => -- s_idle: wait for char or clr ------
if r.clr = '1' then
laddr_clr := '1';
n.state := s_clr;
elsif r.go = '1' and RXSD='0' then
laddr_clr := '1';
n.rdivcnt := r.rdiv;
n.state := s_char;
end if;
when s_char => -- s_char: processing a char ---------
n.state := s_char; -- needed to prevent vivado iSTATE
if RXACT = '0' then -- uart went unactive
if RXSD = '1' then -- line idle -> to s_idle
n.state := s_idle;
else -- already next start bit seen
laddr_clr := '1'; -- clear and restart
n.rdivcnt := r.rdiv; -- happens only in simulation...
end if;
else
if (r.ena01='1' and r.rxsd_1='0' and RXSD='1') or
(r.ena10='1' and r.rxsd_1='1' and RXSD='0') then
n.memwe := '1';
ibramen := '1';
end if;
end if;
if unsigned(r.rdiv)=0 or unsigned(r.rdivcnt)=0 then
n.rdivcnt := r.rdiv;
if unsigned(r.laddr) /= (2**r.laddr'length)-1 then
laddr_inc := '1';
end if;
else
n.rdivcnt := slv(unsigned(r.rdivcnt) - 1);
end if;
when s_clr => -- s_clr: clear memory ---------------
laddr_inc := '1';
n.memwe := '1';
n.memclr := '1';
if unsigned(r.laddr) = (2**r.laddr'length)-1 then
n.clr := '0';
n.state := s_idle;
end if;
when others => null;
end case;
if laddr_we = '1' then
n.laddr := RB_MREQ.din(addr_rbf_laddr);
elsif laddr_clr = '1' then
n.laddr := (others=>'0');
elsif laddr_inc = '1' then
n.laddr := slv(unsigned(r.laddr) + 1);
end if;
n.laddr_1 := r.laddr;
n.rxsd_1 := RXSD;
ibramdi := (others=>'0');
if r.memclr = '0' then
ibramdi := slv(unsigned(BRAM_DOA) + 1);
end if;
N_REGS <= n;
BRAM_ENA <= ibramen;
BRAM_DIB <= ibramdi;
RB_SRES.dout <= irb_dout;
RB_SRES.ack <= irb_ack;
RB_SRES.err <= irb_err;
RB_SRES.busy <= irb_busy;
end process proc_next;
end syn;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: bytefifo_tb.vhd
--
-- Description:
-- This is the demo testbench top file for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
LIBRARY std;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE IEEE.std_logic_arith.ALL;
USE IEEE.std_logic_misc.ALL;
USE ieee.numeric_std.ALL;
USE ieee.std_logic_textio.ALL;
USE std.textio.ALL;
LIBRARY work;
USE work.bytefifo_pkg.ALL;
ENTITY bytefifo_tb IS
END ENTITY;
ARCHITECTURE bytefifo_arch OF bytefifo_tb IS
SIGNAL status : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000";
SIGNAL wr_clk : STD_LOGIC;
SIGNAL rd_clk : STD_LOGIC;
SIGNAL reset : STD_LOGIC;
SIGNAL sim_done : STD_LOGIC := '0';
SIGNAL end_of_sim : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
-- Write and Read clock periods
CONSTANT wr_clk_period_by_2 : TIME := 100 ns;
CONSTANT rd_clk_period_by_2 : TIME := 200 ns;
-- Procedures to display strings
PROCEDURE disp_str(CONSTANT str:IN STRING) IS
variable dp_l : line := null;
BEGIN
write(dp_l,str);
writeline(output,dp_l);
END PROCEDURE;
PROCEDURE disp_hex(signal hex:IN STD_LOGIC_VECTOR(7 DOWNTO 0)) IS
variable dp_lx : line := null;
BEGIN
hwrite(dp_lx,hex);
writeline(output,dp_lx);
END PROCEDURE;
BEGIN
-- Generation of clock
PROCESS BEGIN
WAIT FOR 200 ns; -- Wait for global reset
WHILE 1 = 1 LOOP
wr_clk <= '0';
WAIT FOR wr_clk_period_by_2;
wr_clk <= '1';
WAIT FOR wr_clk_period_by_2;
END LOOP;
END PROCESS;
PROCESS BEGIN
WAIT FOR 400 ns;-- Wait for global reset
WHILE 1 = 1 LOOP
rd_clk <= '0';
WAIT FOR rd_clk_period_by_2;
rd_clk <= '1';
WAIT FOR rd_clk_period_by_2;
END LOOP;
END PROCESS;
-- Generation of Reset
PROCESS BEGIN
reset <= '1';
WAIT FOR 4200 ns;
reset <= '0';
WAIT;
END PROCESS;
-- Error message printing based on STATUS signal from bytefifo_synth
PROCESS(status)
BEGIN
IF(status /= "0" AND status /= "1") THEN
disp_str("STATUS:");
disp_hex(status);
END IF;
IF(status(7) = '1') THEN
assert false
report "Data mismatch found"
severity error;
END IF;
IF(status(1) = '1') THEN
END IF;
IF(status(3) = '1') THEN
assert false
report "Almost Empty flag Mismatch/timeout"
severity error;
END IF;
IF(status(4) = '1') THEN
assert false
report "Almost Full flag Mismatch/timeout"
severity error;
END IF;
IF(status(5) = '1') THEN
assert false
report "Empty flag Mismatch/timeout"
severity error;
END IF;
IF(status(6) = '1') THEN
assert false
report "Full Flag Mismatch/timeout"
severity error;
END IF;
END PROCESS;
PROCESS
BEGIN
wait until sim_done = '1';
IF(status /= "0" AND status /= "1") THEN
assert false
report "Simulation failed"
severity failure;
ELSE
assert false
report "Test Completed Successfully"
severity failure;
END IF;
END PROCESS;
PROCESS
BEGIN
wait for 400 ms;
assert false
report "Test bench timed out"
severity failure;
END PROCESS;
-- Instance of bytefifo_synth
bytefifo_synth_inst:bytefifo_synth
GENERIC MAP(
FREEZEON_ERROR => 0,
TB_STOP_CNT => 2,
TB_SEED => 12
)
PORT MAP(
WR_CLK => wr_clk,
RD_CLK => rd_clk,
RESET => reset,
SIM_DONE => sim_done,
STATUS => status
);
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: bytefifo_tb.vhd
--
-- Description:
-- This is the demo testbench top file for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
LIBRARY std;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE IEEE.std_logic_arith.ALL;
USE IEEE.std_logic_misc.ALL;
USE ieee.numeric_std.ALL;
USE ieee.std_logic_textio.ALL;
USE std.textio.ALL;
LIBRARY work;
USE work.bytefifo_pkg.ALL;
ENTITY bytefifo_tb IS
END ENTITY;
ARCHITECTURE bytefifo_arch OF bytefifo_tb IS
SIGNAL status : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000";
SIGNAL wr_clk : STD_LOGIC;
SIGNAL rd_clk : STD_LOGIC;
SIGNAL reset : STD_LOGIC;
SIGNAL sim_done : STD_LOGIC := '0';
SIGNAL end_of_sim : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
-- Write and Read clock periods
CONSTANT wr_clk_period_by_2 : TIME := 100 ns;
CONSTANT rd_clk_period_by_2 : TIME := 200 ns;
-- Procedures to display strings
PROCEDURE disp_str(CONSTANT str:IN STRING) IS
variable dp_l : line := null;
BEGIN
write(dp_l,str);
writeline(output,dp_l);
END PROCEDURE;
PROCEDURE disp_hex(signal hex:IN STD_LOGIC_VECTOR(7 DOWNTO 0)) IS
variable dp_lx : line := null;
BEGIN
hwrite(dp_lx,hex);
writeline(output,dp_lx);
END PROCEDURE;
BEGIN
-- Generation of clock
PROCESS BEGIN
WAIT FOR 200 ns; -- Wait for global reset
WHILE 1 = 1 LOOP
wr_clk <= '0';
WAIT FOR wr_clk_period_by_2;
wr_clk <= '1';
WAIT FOR wr_clk_period_by_2;
END LOOP;
END PROCESS;
PROCESS BEGIN
WAIT FOR 400 ns;-- Wait for global reset
WHILE 1 = 1 LOOP
rd_clk <= '0';
WAIT FOR rd_clk_period_by_2;
rd_clk <= '1';
WAIT FOR rd_clk_period_by_2;
END LOOP;
END PROCESS;
-- Generation of Reset
PROCESS BEGIN
reset <= '1';
WAIT FOR 4200 ns;
reset <= '0';
WAIT;
END PROCESS;
-- Error message printing based on STATUS signal from bytefifo_synth
PROCESS(status)
BEGIN
IF(status /= "0" AND status /= "1") THEN
disp_str("STATUS:");
disp_hex(status);
END IF;
IF(status(7) = '1') THEN
assert false
report "Data mismatch found"
severity error;
END IF;
IF(status(1) = '1') THEN
END IF;
IF(status(3) = '1') THEN
assert false
report "Almost Empty flag Mismatch/timeout"
severity error;
END IF;
IF(status(4) = '1') THEN
assert false
report "Almost Full flag Mismatch/timeout"
severity error;
END IF;
IF(status(5) = '1') THEN
assert false
report "Empty flag Mismatch/timeout"
severity error;
END IF;
IF(status(6) = '1') THEN
assert false
report "Full Flag Mismatch/timeout"
severity error;
END IF;
END PROCESS;
PROCESS
BEGIN
wait until sim_done = '1';
IF(status /= "0" AND status /= "1") THEN
assert false
report "Simulation failed"
severity failure;
ELSE
assert false
report "Test Completed Successfully"
severity failure;
END IF;
END PROCESS;
PROCESS
BEGIN
wait for 400 ms;
assert false
report "Test bench timed out"
severity failure;
END PROCESS;
-- Instance of bytefifo_synth
bytefifo_synth_inst:bytefifo_synth
GENERIC MAP(
FREEZEON_ERROR => 0,
TB_STOP_CNT => 2,
TB_SEED => 12
)
PORT MAP(
WR_CLK => wr_clk,
RD_CLK => rd_clk,
RESET => reset,
SIM_DONE => sim_done,
STATUS => status
);
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: bytefifo_tb.vhd
--
-- Description:
-- This is the demo testbench top file for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
LIBRARY std;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE IEEE.std_logic_arith.ALL;
USE IEEE.std_logic_misc.ALL;
USE ieee.numeric_std.ALL;
USE ieee.std_logic_textio.ALL;
USE std.textio.ALL;
LIBRARY work;
USE work.bytefifo_pkg.ALL;
ENTITY bytefifo_tb IS
END ENTITY;
ARCHITECTURE bytefifo_arch OF bytefifo_tb IS
SIGNAL status : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000";
SIGNAL wr_clk : STD_LOGIC;
SIGNAL rd_clk : STD_LOGIC;
SIGNAL reset : STD_LOGIC;
SIGNAL sim_done : STD_LOGIC := '0';
SIGNAL end_of_sim : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
-- Write and Read clock periods
CONSTANT wr_clk_period_by_2 : TIME := 100 ns;
CONSTANT rd_clk_period_by_2 : TIME := 200 ns;
-- Procedures to display strings
PROCEDURE disp_str(CONSTANT str:IN STRING) IS
variable dp_l : line := null;
BEGIN
write(dp_l,str);
writeline(output,dp_l);
END PROCEDURE;
PROCEDURE disp_hex(signal hex:IN STD_LOGIC_VECTOR(7 DOWNTO 0)) IS
variable dp_lx : line := null;
BEGIN
hwrite(dp_lx,hex);
writeline(output,dp_lx);
END PROCEDURE;
BEGIN
-- Generation of clock
PROCESS BEGIN
WAIT FOR 200 ns; -- Wait for global reset
WHILE 1 = 1 LOOP
wr_clk <= '0';
WAIT FOR wr_clk_period_by_2;
wr_clk <= '1';
WAIT FOR wr_clk_period_by_2;
END LOOP;
END PROCESS;
PROCESS BEGIN
WAIT FOR 400 ns;-- Wait for global reset
WHILE 1 = 1 LOOP
rd_clk <= '0';
WAIT FOR rd_clk_period_by_2;
rd_clk <= '1';
WAIT FOR rd_clk_period_by_2;
END LOOP;
END PROCESS;
-- Generation of Reset
PROCESS BEGIN
reset <= '1';
WAIT FOR 4200 ns;
reset <= '0';
WAIT;
END PROCESS;
-- Error message printing based on STATUS signal from bytefifo_synth
PROCESS(status)
BEGIN
IF(status /= "0" AND status /= "1") THEN
disp_str("STATUS:");
disp_hex(status);
END IF;
IF(status(7) = '1') THEN
assert false
report "Data mismatch found"
severity error;
END IF;
IF(status(1) = '1') THEN
END IF;
IF(status(3) = '1') THEN
assert false
report "Almost Empty flag Mismatch/timeout"
severity error;
END IF;
IF(status(4) = '1') THEN
assert false
report "Almost Full flag Mismatch/timeout"
severity error;
END IF;
IF(status(5) = '1') THEN
assert false
report "Empty flag Mismatch/timeout"
severity error;
END IF;
IF(status(6) = '1') THEN
assert false
report "Full Flag Mismatch/timeout"
severity error;
END IF;
END PROCESS;
PROCESS
BEGIN
wait until sim_done = '1';
IF(status /= "0" AND status /= "1") THEN
assert false
report "Simulation failed"
severity failure;
ELSE
assert false
report "Test Completed Successfully"
severity failure;
END IF;
END PROCESS;
PROCESS
BEGIN
wait for 400 ms;
assert false
report "Test bench timed out"
severity failure;
END PROCESS;
-- Instance of bytefifo_synth
bytefifo_synth_inst:bytefifo_synth
GENERIC MAP(
FREEZEON_ERROR => 0,
TB_STOP_CNT => 2,
TB_SEED => 12
)
PORT MAP(
WR_CLK => wr_clk,
RD_CLK => rd_clk,
RESET => reset,
SIM_DONE => sim_done,
STATUS => status
);
END ARCHITECTURE;
|
entity FIFO is
generic (
G_WIDTH : integer := 256;
G_DEPTH : integer := 32
);
port (
I_PORT1 : in std_logic;
I_PORT2 : out std_logic
);
end entity FIFO;
-- Violation below
entity FIFO is
GENERIC(g_size : integer := 10;
g_width : integer := 256;
g_depth : integer := 32
);
PORT (
i_port1 : in std_logic := '0';
i_port2 : out std_logic :='1'
);
end entity FIFO;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
-- Entity: spi2ahbx
-- File: spi2ahbx.vhd
-- Author: Jan Andersson - Aeroflex Gaisler AB
-- Contact: [email protected]
-- Description: Simple SPI slave providing a bridge to AMBA AHB
-- This entity is typically wrapped with spi2ahb or spi2ahb_apb.
-------------------------------------------------------------------------------
--
-- Short core documentation, for additional information see the GRLIB IP
-- Library User's Manual (GRIP):
--
-- The core functions as a SPI memory device. To write to the core, issue the
-- following SPI bus sequence:
--
-- 0. Assert chip select
-- 1. Write instruction
-- 2. Send 32-bit address
-- 3. Send data to be written
-- 4. Deassert chip select
--
-- The core will expect 32-bits of data and write these as a word. This can be
-- changed by writing to the core's control register. See documentation further
-- down. If less than HSIZE bytes are transferred the core will drop the data.
-- After HSIZE bytes has been transferred the core will perform the write to
-- memory. If another byte is received before the core has written its data
-- then the core will discard the current and any following bytes. This
-- condition can be detected by checking the MALFUNCTION bit in the core's
-- status register.
--
-- To read to the core, issue the following SPI bus sequence:
--
-- 0. Assert chip select
-- 1. Send read instruction
-- 2. Send 32-bit address to be used
-- 3. Send dummy byte (depending on read instruction used)
-- 4. Read bytes
-- 5. Deassert chip select
--
-- The core will perform 32-bit data accesses to fill its internal buffer. This
-- can be changed by writing to the core's control register (see documentation
-- further down). If the buffer is empty when the core should return the first
-- byte then the core will return invalid data. This condition can be later
-- detected by checking the MALFUNCTION bit in the core's status register.
-- When the core initiates additional data fetches can be configured via the
-- RAHEAD bit in the control/status register.
--
-- The cores control/status register is read via the RDSR instruction and
-- written via the WRSR instruction.
--
-- +--------+-----------------------------------------------------------------+
-- | Bit(s) | Description |
-- +--------+-----------------------------------------------------------------+
-- | 7 | Reserved, always zero (RO) |
-- | 6 | RAHEAD: Read ahead. When this bit is set the core will make a |
-- | | new access to fetch data as soon as the last current data bit |
-- | | has been moved. Otherwise the core will not attempt the new |
-- | | access until the 'change' transition on SCK. See GRIP doc. for |
-- | | details. Default value is '1'. (RW) |
-- | 5 | PROT: Memory protection triggered. Last access was outside |
-- | | range. Updated after each AMBA access (RO) |
-- | 4 | MEXC: Memory exception. Gets set if core receives AMBA ERROR |
-- | | response. Updated after each AMBA access. (RO) |
-- | 3 | DMAACT: Core is currently performing DMA (RO) |
-- | 2 | MALFUNCTION: Set to 1 if DMA is not finished when new byte |
-- | | starts getting shifted |
-- | 1:0 | HSIZE: Controls the access size core will use for AMBA accesses |
-- | | Default is HSIZE = WORD. HSIZE 11 is illegal (RW) |
-- +--------+-----------------------------------------------------------------+
--
-- Documentation of generics:
--
-- [hindex] AHB master index
--
-- [oepol] Output enable polarity
--
-- [filter] Length of filter used on SCK
--
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.spi.all;
library grlib;
use grlib.amba.all;
use grlib.devices.all;
use grlib.stdlib.all;
entity spi2ahbx is
generic (
-- AHB configuration
hindex : integer := 0;
oepol : integer range 0 to 1 := 0;
filter : integer range 2 to 512 := 2;
cpol : integer range 0 to 1 := 0;
cpha : integer range 0 to 1 := 0
);
port (
rstn : in std_ulogic;
clk : in std_ulogic;
-- AHB master interface
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
-- SPI signals
spii : in spi_in_type;
spio : out spi_out_type;
--
spi2ahbi : in spi2ahb_in_type;
spi2ahbo : out spi2ahb_out_type
);
end entity spi2ahbx;
architecture rtl of spi2ahbx is
-----------------------------------------------------------------------------
-- Constants
-----------------------------------------------------------------------------
constant OE : std_ulogic := conv_std_logic(oepol = 1);
constant HIZ : std_ulogic := not OE;
-----------------------------------------------------------------------------
-- Instructions
-----------------------------------------------------------------------------
constant RDSR_INST : std_logic_vector(7 downto 0) := X"05";
constant WRSR_INST : std_logic_vector(7 downto 0) := X"01";
constant READ_INST : std_logic_vector(7 downto 0) := X"03";
constant READD_INST : std_logic_vector(7 downto 0) := X"0B"; -- with dummy
constant WRITE_INST : std_logic_vector(7 downto 0) := X"02";
-----------------------------------------------------------------------------
-- Types
-----------------------------------------------------------------------------
type state_type is (decode, rdsr, wrsr, addr, dummy, rd, wr, idle, malfunction);
type spi2ahb_reg_type is record
state : state_type;
--
haddr : std_logic_vector(31 downto 0);
hdata : std_logic_vector(31 downto 0);
hsize : std_logic_vector(1 downto 0);
hwrite : std_ulogic;
--
rahead : std_ulogic;
mexc : std_ulogic;
dodma : std_ulogic;
prot : std_ulogic;
malf : std_ulogic;
--
brec : std_ulogic;
rec : std_ulogic;
dummy : std_ulogic;
cnt : std_logic_vector(2 downto 0);
bcnt : std_logic_vector(1 downto 0);
sreg : std_logic_vector(7 downto 0);
miso : std_ulogic;
rdop : std_logic_vector(1 downto 0);
--
misooen : std_ulogic;
sel : std_logic_vector(1 downto 0);
psck : std_ulogic;
sck : std_logic_vector(filter downto 0);
mosi : std_logic_vector(1 downto 0);
end record;
-----------------------------------------------------------------------------
-- Signals
-----------------------------------------------------------------------------
signal ami : ahb_dma_in_type;
signal amo : ahb_dma_out_type;
signal r, rin : spi2ahb_reg_type;
begin
-- Generic AHB master interface
ahbmst0 : ahbmst
generic map (hindex => hindex, hirq => 0, venid => VENDOR_GAISLER,
devid => GAISLER_SPI2AHB, version => 0,
chprot => 3, incaddr => 0)
port map (rstn, clk, ami, amo, ahbi, ahbo);
comb: process (r, rstn, spii, amo, spi2ahbi)
variable v : spi2ahb_reg_type;
variable hrdata : std_logic_vector(31 downto 0);
variable ahbreq : std_ulogic;
variable lb : std_ulogic;
variable sample : std_ulogic;
variable change : std_ulogic;
begin
v := r; ahbreq := '0'; lb := '0'; hrdata := (others => '0');
sample := '0'; change := '0'; v.brec := '0';
---------------------------------------------------------------------------
-- Sync input signals
---------------------------------------------------------------------------
v.sel := r.sel(0) & spii.spisel;
v.sck := r.sck(filter-1 downto 0) & spii.sck;
v.mosi := r.mosi(0) & spii.mosi;
---------------------------------------------------------------------------
-- DMA control
---------------------------------------------------------------------------
if r.dodma = '1' then
if amo.active = '1' then
if amo.ready = '1' then
hrdata := ahbreadword(amo.rdata);
case r.hsize is
when "00" =>
v.haddr := r.haddr + 1;
for i in 1 to 3 loop
if i = conv_integer(r.haddr(1 downto 0)) then
hrdata(31 downto 24) := hrdata(31-8*i downto 24-8*i);
end if;
end loop;
when "01" =>
v.haddr := r.haddr + 2;
if r.haddr(1) = '1' then
hrdata(31 downto 16) := hrdata(15 downto 0);
end if;
when others =>
v.haddr := r.haddr + 4;
end case;
v.sreg := hrdata(31 downto 24);
v.hdata(31 downto 8) := hrdata(23 downto 0);
v.mexc := '0';
v.dodma := '0';
end if;
if amo.mexc = '1' then
v.mexc := '1';
v.dodma := '0';
end if;
else
ahbreq := '1';
end if;
end if;
---------------------------------------------------------------------------
-- SPI communication
---------------------------------------------------------------------------
if andv(r.sck(filter downto 1)) = '1' then v.psck := '1'; end if;
if orv(r.sck(filter downto 1)) = '0' then v.psck := '0'; end if;
if (r.psck xor v.psck) = '1' then
if r.psck = conv_std_logic(cpol = 1) then
sample := not conv_std_logic(cpha = 1);
change := conv_std_logic(cpha = 1);
else
sample := conv_std_logic(cpha = 1);
change := not conv_std_logic(cpha = 1);
end if;
end if;
if sample = '1' then
v.cnt := r.cnt + 1;
if r.cnt = "111" then
v.cnt := (others => '0');
v.brec := '1';
end if;
if r.state /= dummy then
v.sreg := r.sreg(6 downto 0) & r.mosi(1);
end if;
end if;
if change = '1' then
v.miso := r.sreg(7);
end if;
---------------------------------------------------------------------------
-- SPI slave control FSM
---------------------------------------------------------------------------
if ((r.hsize = "00") or ((r.hsize(0) and r.bcnt(0)) = '1') or
(r.bcnt = "11")) then
lb := '1';
end if;
case r.state is
when decode =>
if r.brec = '1' then
case r.sreg is
when RDSR_INST =>
v.state := rdsr;
v.sreg := '0' & r.rahead & r.prot & r.mexc &
r.dodma & r.malf & r.hsize;
when WRSR_INST => v.state := wrsr;
when READ_INST | READD_INST=>
v.state := addr; v.rec := '0';
v.dummy := r.sreg(3);
when WRITE_INST => v.state := addr; v.rec := '1';
when others => null;
end case;
end if;
when rdsr =>
if r.brec = '1' then
v.sreg := '0' & r.rahead & r.prot & r.mexc &
r.dodma & r.malf & r.hsize;
end if;
when wrsr =>
if r.brec = '1' then
v.rahead := r.sreg(6);
v.hsize := r.sreg(1 downto 0);
end if;
when addr =>
-- First we need a 4 byte address, then we handle data.
if r.brec = '1' then
if r.dodma = '1' then
v.state := malfunction;
else
v.haddr := r.haddr(23 downto 0) & r.sreg;
end if;
v.bcnt := r.bcnt + 1;
if r.bcnt = "11" then
if r.rec = '1' then
v.state := wr;
else
if r.dummy = '1' then
v.state := dummy;
else
v.state := rd;
end if;
v.malf := '0';
v.dodma := '1';
v.hwrite := '0';
end if;
end if;
end if;
when dummy =>
if r.brec = '1' then
v.state := rd;
end if;
when rd =>
if r.brec = '1' then
v.bcnt := r.bcnt + 1;
v.hdata(31 downto 8) := r.hdata(23 downto 0);
v.sreg := r.hdata(31 downto 24);
if (lb and r.rahead) = '1' then
v.dodma := '1';
v.bcnt := "00";
end if;
v.rdop(0) := lb and not r.rahead;
end if;
if (change and v.dodma) = '1' then
v.state := malfunction;
end if;
-- Without readahead
if orv(r.rdop) = '1' then
if (sample and v.dodma) = '1' then
-- Case is a little tricky. Master may have sampled bad
-- data but we detect the DMA operation as completed.
v.state := malfunction;
end if;
if (r.rdop(0) and change) = '1' then
v.dodma := '1';
v.rdop := "10";
end if;
if (r.dodma and not v.dodma) = '1' then
v.miso := hrdata(31);
v.rdop := (others => '0');
end if;
end if;
when wr =>
if r.brec = '1' then
v.bcnt := r.bcnt + 1;
if v.dodma = '0' then
if r.bcnt = "00" then v.hdata(31 downto 24) := r.sreg; end if;
if r.bcnt(1) = '0' then v.hdata(23 downto 16) := r.sreg; end if;
if r.bcnt(0) = '0' then v.hdata(15 downto 8) := r.sreg; end if;
v.hdata(7 downto 0) := r.sreg;
if lb = '1' then v.dodma := '1'; v.hwrite := '1'; v.malf := '0'; end if;
else
v.state := malfunction;
end if;
end if;
when idle =>
if r.sel(1) = '0' then
v.state := decode;
v.misooen := OE;
v.cnt := (others => '0');
v.bcnt := (others => '0');
end if;
when malfunction =>
v.malf := '1';
end case;
if r.state /= rd then v.rdop := (others => '0'); end if;
if spi2ahbi.hmask /= zero32 then
if v.dodma = '1' then
if ((spi2ahbi.haddr xor r.haddr) and spi2ahbi.hmask) /= zero32 then
v.dodma := '0';
v.prot := '1';
v.state := idle;
else
v.prot := '0';
end if;
end if;
else
v.prot := '0';
end if;
if spi2ahbi.en = '1' then
if r.sel(1) = '1' then
v.state := idle;
v.misooen := HIZ;
end if;
else
v.state := idle;
v.misooen := HIZ;
end if;
----------------------------------------------------------------------------
-- Reset
----------------------------------------------------------------------------
if rstn = '0' then
v.state := idle;
v.haddr := (others => '0');
v.hdata := (others => '0');
v.hsize := HSIZE_WORD(1 downto 0);
v.rahead := '1';
v.mexc := '0';
v.dodma := '0';
v.prot := '0';
v.malf := '0';
v.psck := conv_std_logic(cpol = 1);
v.miso := '1';
v.misooen := HIZ;
end if;
if spi2ahbi.hmask = zero32 then v.prot := '0'; end if;
----------------------------------------------------------------------------
-- Signal assignments
----------------------------------------------------------------------------
-- Core registers
rin <= v;
-- AHB master control
ami.address <= r.haddr;
ami.wdata <= ahbdrivedata(r.hdata);
ami.start <= ahbreq;
ami.burst <= '0';
ami.write <= r.hwrite;
ami.busy <= '0';
ami.irq <= '0';
ami.size <= '0' & r.hsize;
-- Update outputs
spi2ahbo.dma <= r.dodma;
spi2ahbo.wr <= r.hwrite;
spi2ahbo.prot <= r.prot;
-- Several unused here..
spio.miso <= r.miso;
spio.misooen <= r.misooen;
spio.mosi <= '0';
spio.mosioen <= HIZ;
spio.sck <= '0';
spio.sckoen <= HIZ;
spio.ssn <= (others => '0');
spio.enable <= spi2ahbi.en;
spio.astart <= '0';
end process comb;
reg: process (clk)
begin
if rising_edge(clk) then r <= rin; end if;
end process reg;
-- Boot message
-- pragma translate_off
bootmsg : report_version
generic map ("spi2ahb" & tost(hindex) & ": SPI to AHB bridge");
-- pragma translate_on
end architecture rtl;
|
-- $Id: sys_conf.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2018-2019 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for sys_w11a_arty (for synthesis)
--
-- Dependencies: -
-- Tool versions: viv 2017.2-2018.3; ghdl 0.34-0.35
-- Revision History:
-- Date Rev Version Comment
-- 2019-06-05 1159 1.1.2 down-rate to 72 MHz, viv 2019.1 fails with 75 MHz
-- 2019-04-28 1142 1.1.1 add sys_conf_ibd_m9312
-- 2019-02-09 1110 1.1 use typ for DL,PC,LP; add dz11,ibtst
-- 2019-01-27 1108 1.0.1 down-rate to 75 MHz, viv 2018.3 fails with 80 MHz
-- 2018-11-17 1071 1.0 Initial version (derived from _br_arty version)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
package sys_conf is
-- configure clocks --------------------------------------------------------
constant sys_conf_clksys_vcodivide : positive := 5;
constant sys_conf_clksys_vcomultiply : positive := 54; -- vco 1080 MHz
constant sys_conf_clksys_outdivide : positive := 15; -- sys 72 MHz
constant sys_conf_clksys_gentype : string := "MMCM";
-- dual clock design, clkser = 120 MHz
constant sys_conf_clkser_vcodivide : positive := 1;
constant sys_conf_clkser_vcomultiply : positive := 12; -- vco 1200 MHz
constant sys_conf_clkser_outdivide : positive := 10; -- sys 120 MHz
constant sys_conf_clkser_gentype : string := "PLL";
-- configure rlink and hio interfaces --------------------------------------
constant sys_conf_ser2rri_defbaud : integer := 115200; -- default 115k baud
constant sys_conf_hio_debounce : boolean := true; -- instantiate debouncers
-- configure memory controller ---------------------------------------------
-- configure debug and monitoring units ------------------------------------
constant sys_conf_rbmon_awidth : integer := 9; -- use 0 to disable
constant sys_conf_ibmon_awidth : integer := 9; -- use 0 to disable
constant sys_conf_ibtst : boolean := true;
constant sys_conf_dmscnt : boolean := false;
constant sys_conf_dmpcnt : boolean := true;
constant sys_conf_dmhbpt_nunit : integer := 2; -- use 0 to disable
constant sys_conf_dmcmon_awidth : integer := 8; -- use 0 to disable, 8 to use
-- configure w11 cpu core --------------------------------------------------
constant sys_conf_mem_losize : natural := 8#167777#; -- 4 MByte
constant sys_conf_cache_fmiss : slbit := '0'; -- cache enabled
constant sys_conf_cache_twidth : integer := 7; -- 32kB cache
-- configure w11 system devices --------------------------------------------
-- configure character and communication devices
-- typ for DL,DZ,PC,LP: -1->none; 0->unbuffered; 4-7 buffered (typ=AWIDTH)
constant sys_conf_ibd_dl11_0 : integer := 6; -- 1st DL11
constant sys_conf_ibd_dl11_1 : integer := 6; -- 2nd DL11
constant sys_conf_ibd_dz11 : integer := 6; -- DZ11
constant sys_conf_ibd_pc11 : integer := 6; -- PC11
constant sys_conf_ibd_lp11 : integer := 7; -- LP11
constant sys_conf_ibd_deuna : boolean := true; -- DEUNA
-- configure mass storage devices
constant sys_conf_ibd_rk11 : boolean := true; -- RK11
constant sys_conf_ibd_rl11 : boolean := true; -- RL11
constant sys_conf_ibd_rhrp : boolean := true; -- RHRP
constant sys_conf_ibd_tm11 : boolean := true; -- TM11
-- configure other devices
constant sys_conf_ibd_iist : boolean := true; -- IIST
constant sys_conf_ibd_kw11p : boolean := true; -- KW11P
constant sys_conf_ibd_m9312 : boolean := true; -- M9312
-- derived constants =======================================================
constant sys_conf_clksys : integer :=
((100000000/sys_conf_clksys_vcodivide)*sys_conf_clksys_vcomultiply) /
sys_conf_clksys_outdivide;
constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000;
constant sys_conf_clkser : integer :=
((100000000/sys_conf_clkser_vcodivide)*sys_conf_clkser_vcomultiply) /
sys_conf_clkser_outdivide;
constant sys_conf_clkser_mhz : integer := sys_conf_clkser/1000000;
constant sys_conf_ser2rri_cdinit : integer :=
(sys_conf_clkser/sys_conf_ser2rri_defbaud)-1;
end package sys_conf;
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
lcLEUhFl0x6q4c8Lsuly3In5vNp7gT1QOB2xNiyV2VJn7oh99l7ssPfFXx9Sj3m4iLjHRcAzWQg0
M6s2ArG2IA==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
aDVERq09vEpxux9KNNAFDiM5twDtcHRqDCuY6TKCwN0uWbq2XDrrlgycu0NMBMzWbARtM2ZGlu8n
1cdDQu0fel3PN9Yxe4/8X+rEd70BOMJqMd/OEHJkjr6fSSM9r6uvVKp/jMbzXaQBn8/iExJi/fGC
qJ0nIvxkAH8ee4Y4/bg=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
MbYkAAana0SpOy4UsxBYugLLK9hbWDYI98nge/kX28U3t4CelLt2a7tfyzpWZQ9pWw5fznlnjFwO
6WjZHnecZtyX2UMT6tpI5EJmp5RXP4GBFOBuMzsXhOaGtaU3KnJqAxoTASlUBSjMj1/6Bpa20atX
npP1N3gRxaq30LjdKpeoNeBu1Ywqbdn8qTOmeZNPJeuzVZVg44H8WRcsQhP+OOqzRg4jMEwLvaTu
Ry8kSCmbfCz1aHWxX41bN3OYaCYCvI/A1K+KgLdy9yaQwelVBzn6nNPNcHItrvK/+4Bjl4AD6XzG
oNl3Bbv+5PCie3jh1KG//HuAnO0uB9DtVxi26w==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
NXUBIAP47OfKxZvMP2Q06k0ee1gmVxRcRsGIkHhFg7nlh2rEyCDI4CpRXWXyyH5sGCHBiuQCFfJG
eEvNf0/GG3Nj6i8tlvOVUzcEZBSzeVr5jbQEEwbW3jBsC8IcSrB0oO0ZqSPFhM1Mkm58f+NCZgu8
ixyxiavqojX3GcWkSgM=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
ZI9Lv/AWBd3rJBNjrkXPQiJtuq8f/eiiYTRPSjHQ7aNutFyEc5rS4/IdTSr7PoF1z/ZHpwJX4gd9
9SirllPHnmI8Ve7l/yLRPEirw5KyD2r0iIUs6/g4DarvtSpVzgb2Pjj5kZMDbXENZ1DWKdPLiMw3
U4rS9j2KVzFDAGMpBqfARpFJeEkj1pln+GOWI1i1JP4MGQc2BM7z22wO3PoD5cj46BfQRSBoAmSF
F4zyLL7ojGVOjRrIk1D+jGBs0T+YD/NpLxMTrjC9x5OE77JQezrEHDEhxmTrcW2f4BFkURqiZinD
LXw1yqlg+7ULZTfMlxhc69BpHbLmNlKnwtDoLg==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 280736)
`protect data_block
j89sMXCR+thMssXjetOozjSiNHC1jWgf3DoSfTNMg6gP+dtad8uiiAbZhkz9Cn9USHOwQz4M1qFz
QCsi8UW8KEzEtPsD0e3O/BBcYfJ3dt+8zj4EmjeLjXSPSSL2jgskEIVE0n3xdlI+Z0lWdM4K2ImD
D3vFvyQGIXRPT6hctU2nt0tJjFb95MBvvHQl6sdAg2BwXpy+Qj/v59ywbXSOQuZvZDNY7ZNfHx6W
LqfzW0xQ0NPcZ2tNMw2fDysI/jQAoJa6ZHFVQoBZdSzKisvSrsXWDImFd9Upgq6WjIWkPxzN0dD+
Y28haqDTLoPSDI4V8uOqsHgMMn44eFxZ1GjQGrFizC2Nb7Z1+5OOo5m9uCmXehRu3rrEWF9EoGgW
GSZQHLAaWGxyTmcGEUujencvOeUClNmxLI4pSIPOJ8WZCSjSNezG8guFJKe8GkHJIxFSRZjhIbpi
T4pbtk2Ujvlq62ce3KOzg9PAqj+u2hbGD91xo+CCM4Wi8BaU96XuVVYSXUs4j1m9NhotkaFgCzwR
J4sSJbHi9sZDeAI6mG2X0kaHy72dOpWmQ+Lm+bYVefzctK5jKDFLlu5ID2Iyn0wVdFazIkzTmd9b
+EePV9cWzxZsc1QLDW08Ec6IQlAzukEFgGAdu+lkI4g/CHZWO0Sp4cDkYkYeOD5bk0J9j+5oFfyU
rnEr7wtKk+yAYit5PZ1tZooGDr6s+ZkXM89mqO7Y0oeKw2HtcqRDY1bLkHjSJApXB2ntRugw5Ahn
M5CvbvDu3FL66Vm+PvgwFcvm/d+d0Ft+brlQMbsb8VyADcrybZzg8L5yzwX4RfN49A9+OhyJyjUU
Nx9vlscMTu4R736qzt37J2DulqTJyp/UudgO3rH1EgKJOCa79H1wUFP9OptIXBQGhCfJlgKV0uYS
mbVOIPkRdTFkrKeC1i/UMi0N1GUfjDg77yRVsp2JPf823f9HTYJcI/4O7g/K+8NZz0vTAWyZpAxZ
b/lh+0klXXO3UYxKqNHQg3pzCCqOz+ci8+7SsXFTmXf68fnbRoBWd4CtZtzirQVJxlMtsYpbC7Yi
39mYZDsHWUWBXqqwLbdBnrbCO8U8fgNOKJF1TkiwQThxdmwrdnv1s45PNVTYkSfYGAcP3ehzQ2sV
AB3GdWRuukA8sVZkT4jhDUyv1yt/OFzRDpGLIAfaZk5vEDF8ymf6VgQXaj97LvpVuxKeGLEUYgwX
7ED+zeDjNqatrmyf2IdQhd5plakGLL8ND0tWY/pZqNEvl6PR6ZASPgtUc+pnWcSRkUISscebnUk6
5j2bt6M/lWAjxNFyPqGajU7CH7GBQaCnmqPLK5K6s0sSjcD6R4cQ1XqOmyeRjh1aCW6u4iyif7Is
SmdE8OLpszOJdfu6Pwd5Ts05jO6GYyeX35+2vOm4j/2PJ2tFTVWOo7v6fB3j3s77X7LTC3FLFsmf
+L1KawwJYzaLDDjeBXjq80n/5V7Yg7oDlDXg8ANGSfVmFRBqzv1aoBJj5X92Ddi8+nKML9fmQOZt
3W30UONBJLTMzHBti07YJsMmfDdW92HxrlqaW7IACFbymMaJ0KHyuDqzS6SJQxd2xoVysUrpDhcB
tBGXAIz1pvehdvn3n8CL0Orl3mAgOr6XTdb2SbLy3Ib6xjVy3fidf8rUQLNz2Vdz7uq0JewI3zA1
N70LXEz+A9WWmBT0p1/Ikx4l0dv8xs3HY+kHhEozC1/S5smxDMsuN/tqXbhGDJHA+N5X20/xdKOW
JpD1fToY3QjLZ8IktpxOIxI9g2Tfz8cs4ZIchFPkkjtsBTIHdp0Hj4gqF4x5VqNcveepoD8yiRlk
pXnbmTTAOlFegTQdAsHW9gudE8nJdN3Lxl+aurIb0gKc7Mrqmxk9NX2epqoFk3Rc/HaUbOWoyw0o
dzX4+L/4kU9+Pm3kK5j+wxhzvSmabIS2k/WrISlPMUr9wzwl6eV0Vb6z4wzHGLjnUChMIPH2nOPZ
XVALl+0VyodaPwY6d8c+K86iGbq7h9/RzAvZEqLgmYXkGTD9raXd3R6Yy/BD7EAbN1aktNYr/Bn0
v5AqzzuIF7piBsI5neNQ+xHnPSQxxxAyXTpMyv3FbEp0fzpP9GUtIlzC4JPWqYRXYQA73QTpslwQ
QFouo6dgRG84+Q7pDmkMcJeLbbYNJdDg+ZZiyKBxEULNemqDi7HOEPeVZcvcQl2rJuYCNI635I50
BiJcw1r5ycOjRIaemgx2iVe7IxM5sZcujcAo3WmNIq+w/GmAGkWW4UjAGYFCvb0+sNTSmvBJ/Akv
GeOdNrCsgwBHMbNQeB9NvhrHR691DfD84GopL3H6fYCKOiq8A4+3CAFkNi80EpnTj6ReEbZPPo63
mJ+wbwpSJfObFqBkAycJPxpvVRwaySGYHOyK3rzeLiJPSOQtfHsTAu1TI8WYnJJr7fydAOlpy5lo
Z5wMrwSVq+SfilvYKD8DaPfYBPQUEGybtSVv9thaDhR44ihg3am1BPjUgCDEU/vSouFxabt+UfWW
CwDetxxvEd9hiVWo7pdTpIyhz+XtxaIzvyPIZxwdtBtXrVcZsuedreEA5yzwhb77gRJnd50VboF0
TCyoiWNAO+MXaGAVQHL4i91hDf6NH7or3zvfCuz2/XHRkiO5GM8KF+7CZidTOMYfDNPX36iHJ44u
12GdV5H8qhgmASThH6OOBSOwZAYiXLfS0JdR7Fj4Yrxeie61ETmJ7OdvjnJ6cX7lOzZq5VknzcaU
MHE8w2OqFd+l4b+vmI0/xVkWTTpoFt9MWIO01bVjLWtuAf8xJtFWEzbA8AtFSXAcxwYiEz4Butif
yRHVWLE2IS9nuMap1l3KQxhoBCvLl0LexQ6TMZ+TTUMH19rD7io4GZz3cpoe/sTP+9JSHQEzJbU8
qvN3NbuCXqRp151hP9/dEDfnDJe3rA1yCxBL5uye/4QYMk5NgRjHGoLWd8xvquzzq7p2HuWGPABc
+86yVsjri6LmmBe/1NddKHOOI+F/V5Kq+ONLgjJrbeeWmjSXClm0iZZ2LS3StfojByZXxDqoPD70
mzlsCZBjkqPW7fjWpDiEudMNlUoCkU0MvGb5UA94k45xkUnGoEttDrjbaoEiTX/uODwBfrFs3aLM
hKms86mdQcM00cxxO5CqyUwkUEt2JefSMPHiNi+snAAkeBdrlwWPS4r+viX/Q4vcBIXLlvSdMQ4E
OL2uyxK6O3jqwQnmjFBC6afR8m2C0lx3Y5r6vYas/QZMUFGh1QVn52nE+1OQ5N6sqvOSTUrxSYEB
7KhsV8V7URM9robWBVBSRUfgC72T1ucsgB6oYpGjnGHX2wl8qfRGvS66jGWX1fFenSCQpP/r4zN7
BH1drKjmFB7fDeyzesHNBDTRvX6aiMx+qUd7o0V/B8rB3w69HTeAi6hK4NEjd6X3t77oG//+sX1a
3DMzdc73avVq1o3cNO+WGn3mDIXFxbgrsQ3nuLu20ZsjA/+Z8i/7FxAP330sDM6mQh63yZC9o3wA
UhbS+Dn1UIC2ixQPFM1j2tpMwVZ1cwoA8raWsPa1Rbdtjn62tAXu87Emwnkfa0Cm5cyMvuHa7rgy
Z/nFVm/JfqW8dA582o6lhpPJ2qVO1cr3oExjwn4z9MSttGDrYlVklV4twN87t+IvqGfnk8GoJHnY
yNDkRhFJkw7ubWDgjKVKQSHR1xHwp6dWqFJN2z/W3jBJ/LlrEHvpsj3xuc9OXHeJbOfI+QYByOXh
a1FVUAXLHhofrjhsFdKn9E5kRaxLM1eba1QWFR3clH/maBAh5scNgatAda4lJo7EJnJ4+gZkoDb6
soxq1gDgFXwRiSReLoFZAPiwX1FPpScuxCTLFcySQM7pXJsv8PE/yYtxACe51Ndpf3l/KdbETJqL
xn4JOS5slqy+t7zyBQVt3CZbQYiqtu/S7stNOvlkNp3mTHGAW7pBMjbR7a4SoeEM8rqEgEuLX7tO
mkTm4AoT1ixEsKQgvl1OE7IFDvb9uauG2JBfLXUlVoUauYZFH6WDeam5SzOaOY2yLs7sg7KpQ0cd
wQWts6HzD7z5lcQCwxd+nhIuQifzNWJT0P139EsMqXI2B/D13W2/6k6qvZ+htNVajYekUyjlAsqs
DrK0d+JrQcAdzXIvARhuKLsYuRRu3krU2u0nEbhSbKrN/B9337U9Yr3EIcH6grlv0lLgRQJ7B7E2
RgzVIWxKIhoEfvx4yBXC838aXKywc3f5eGTHNEMWUWxxaPPbDNJ3L9T607bxd5BNf0jPHJSoOlXO
YaLPooNb/nEFjvz6O64c607ARQLeb2vGFoiTikhbKn1qDxEb74GkqCzFZAYjerTm0BIVtrtHuYZ3
gj6gDtS6uqyUwyXBbmhOHJCMmp8JwDJ/nZTAPcBwV0KyyR+fi8f4jy+Y3r9cU76Uryx9NKvjhz8j
aI3Wlt7oY32WOZukajcNZh3hBFXusCYSwCSYdUcGewsRoRJ1/XIm6xWBFsLOU90HtAvglj4sAWFW
jyPrKO35ZmX6tVGx3mUmDdveQeYEOKVIiB9qUsQwmLl4zYaFHM5y73PNLAC285oY64XqQLF+YngP
ykn8AJZlyGDLUxwgp80uJW7g+OHMPKjDxaQyDEvXEzg4mi1N2gjUnC8gBZ4GWtIOcQ58MK1iSt8G
jb4iqymRwUx5vbw/RqJty0j7qG6Fs+3yfN+hlqT013GlV0wojNwn8mdy2P2CgM15axKQYVEuJX9a
WY1KLu7KWXUH5vzW4MX55MsjGrzl9HXrMF/MSt58VdW5WH4RKXN0d6+l9MdvQPLA/C2w+Vyzre3x
i7FMOBpeYZde2FRejMfLwIs1bFMzaTIN3Ae415HIFC5zuhqBbCKrfyszLIDnASEjhpA35brCTBs7
EUV9Soq9vpa+PnO532twQ90Oy1CiSkMoZwkNMfgh54fLt9PEVn2xvzZyVxNyM/zumW6QTXlzLOTm
DqqvFBQ+l7+CksfG1TQRu97DSs5I3LIW85eTbKknlfUJgkZQTbrzjRtP3qvAN1KrFSMKKaxsgstv
7oBNCBsdeJBI9QYo7km8M2EHl08PA64FNUruMiM5edBgfjpmYoxjVLdByeEs41gYvbHgDUZ4pVXX
cQ6jZarvfiwP3mTUtPZPCsz7DtWxPOq7q8X0TWG6z2SrQzkGp8I5nXzfTEGX70fX/6BEAZEap4sH
euREmrjRLgZuxNNQRTJZ/ZXmTJv4xcbVWgfclN18FQCAs+nI1Jebi41HsLdMqfDw65m+K3GVVB42
Zb69z3WP10p92NnJY5RE+F5mnZOwsCmE5GeJ/qJJwj/i+TWZ1STILvAo7IacXqV4gSr9BymeWSdE
xMgVOKZUuu/15mlOyGBnlbuJZZcKI4U0+NaMY86535O3S9OasX7PBWscS6Wg14Gi4yFh16Eom3ul
HeW7s6XzMCoUTYdUuq+pGj/Ib08AwmJk+KWpl2NGKk7dASGXYyqexFyYJ9lYSqOQEPq4j7EryBTm
SVKobUgcWwK6BCLD+AwEXOVkxDFpsCNVXJ29AbS6hEbOqTkS6blm4lCZ0SQG5kENlAcPzWXShZXB
N+mewN5rgrrD+6KHFtWVmZ68YKEWr/ooYvlN43i56cDkFSVAEOUqedYcyJW0t4aboagWsIGpa+q+
+3qDvLkKWjfsMx91zH5FErFKQl1Zwx3Ios2dYSBO7bhc1/CQHIJ/2v8+pZIQe5DZJHjEAaH7iTHr
+5kfoL4Vh9ArWFU/Plu8/OEdoZC+9EdJyTiGevCJdlEZ10Ciy3JXPta20GBCSuXc0GzyqReEPFtt
+yFHoO2piSNROQuZHjM/bn9PVgT4oA5iA4fiIswqhXfafspnAqd2nQFbkHXVTpyK3NaYsldci+N9
ZjYqviEZN14qJjVFeKdBqxHfE1GFVvgVZQAZWbVL3xYLzhn7m7tcu/pPIiFYPM3yDJxHUeXn7Lko
O8xdzmX8Eb/ThGmKn/F9Zk4oPev9LLDA2zgUVIep2nb/oadLIqwQhu41NlMoeL/HDnyPeBm5daI2
opxrh94VOAvrbQNoJW8Axq3s/Ug8Y4Y98BekrSbexIr3afnss23bQi7MMFjJU95I9Fv6z7WFoCUH
O4p8c3kHNK3JWyLaiXaGYXPvJF/UOnLGDbeZXhXHfX8PN3t3SXSnQcjbi4P1RIFGkF5t/Zr/Y6E1
LGDdsNdG78awGpk8w9F7RqQvcRSZ4B2Op/IjLIWa/QrXMd2b6uf9Owi4dYvvvqXHj7+ZLAqRj9ue
DYAHlfNgHz7a3jkSWKpPSIC+bzB7+7krnEOQR0Hry8XxzL5AJmLQm9vfJCJAbIHpx+n92TNx7kLl
LCPet/K9XmKYGzqAAN/Rmyj/KfP90cCcjn3G0/NdRA16M9EDjzv+9ssrOsDJT9h23kxAR4EDF/U9
KBKDJD674H8w8afZDzcuy741PLl9d1jAofNH2QiBN27cRNLjNmxRecrRrXSDOsm7F9FhRx/ueHWN
zXXFBMT2LUBwmEK28SjDUrQAaVL5lW28wVOU1wTFKKp1jjWbuzGs9PJDEIKKuGev2++0RvfOHjVO
cVvIJhEHIHG+AJNxHVbD+Xh8cwq5S3RGcNpFwsKIFdzbFjRXzSgeEccZ1Zxq/G7weejtGdrITZDH
+PbxeXvHisCNjx+iClsKQq9Qui6sbdO+T4urx+r3DCa8fxFEhhHGkylq8xg/oI94Kr1nk1P0m/kC
TeqRMJxOAg+obrutpg8guMPFbINnyuE4RbaNC3vy56bX+jWY76qYV87ihj5SdX5iZNsTXLiDzNAd
ExbEy82W5662YP+fdqlgkDG19vQp1apt9IlvyCUjSm7Uc4iFAjpr0Vc3MrrEdevn6MfMg5ReDj/t
8DT1niiwNPKLzxKIHhxehnq5Mccl1jzsxCu9AjVAy5/p9KtaTw++LS/tfMGwp6LtuhWrqIGqUu8b
w6xLmC5Oefhu6WAv8s+Kkkp0RDWS/N2fotGRAh6YjusVNcRgTWA7Yu798S5u2wszKjx91w9OKH7q
hcUE6bxekBp+mS4NhQBma+Zu68FAEocIoLsLJc2tMnaABJ4puDE5kwg+8rLPUDdMfm/f/nsY7xa/
OyAhyWdWdascEVpRJy/zMJqvSfgbWfdFUesn1FDSPQ+CajOxp3zvhF5WDc9G7WqquwpvoPw5tZN4
32zXsTzqiHCKgT8O18Lqx37N5eBGg9BAuRLtbiK8SKnelezgiycYNxnSlt/6VL4tHewaF18M6rhp
3T7a26dk8x2pWznsznK4fDxJiCF2dax8d4UDo7EuustNt2U9Lh/s/fnKJX+mp15oJvXQaF74Lk+1
doQXTkWRUPXq6V4l1TKeP2+vapB6c14jM0LWLRmiZBioET8+NZUuGWC+uS7K+7iX0IfqmIs5b0Qu
VQMljgWyCSsmL1W+9P2JzKo2walEGZ8kp2tADuG+peuwQJc9MqfqqGAB9deYOP76McYMBtdmZJA5
AcPLuRxLPsheCpyi4UZgxoP6efvNGYirubb8nqNuFHWpn9g8A5FlUBVd+BdmSQO0EqHMWrgMIJFZ
1bHK8jITcr6FC3ut9g8RdXg4D+10uKB+EN1cMtWphwnbGc1sDlywdjj/1jo0fV65gIklhRNsWs2N
beXXsWYxicjXV6ETvO+t4d0n769WyFI/tH+LYQnd+ShP5AP5sTguSW38pHinZlCy1pqeganOix4U
O8urcgemS5Ovi6oDXlbKJKiAFWrqZcqj6Tftb9SZn7OdGhlzBafsNgdlfznbS01POZMed5iJ2IOe
m40SBYyhMpBczdSPW0Ljr78iKphtO0EHrBdUVKYVRLW4WIeHldzsiMx6R1AZXqgw+QvM353qhXgX
IzIVW3vH3n8Y5z2t1BIy8C4Z5GdmV9hyTb3SVWAVe2ALqvWyTKpYXf2CeaZKhXyHef5tyH1b5xE3
ojJ8TPM8bogzYicKddp/MdR7INDw1h+h1B6LcUNMmH2f9YMsaf35p02WUdmIKFRswvBq8oz5xvuV
H9FF6Fgettw/O7gjIvXboqo6cq3t2ZwIJQ9Qv5GlqaKrIgVKoY55ZAKCyu9yb9vtyHbZS7C6wbwG
WkR2G7OlGM98/ST89MVFA7WzADGuVcg2jQiiY0gMEDqSwvPTOJQQhnfQrsuUqnJ8aQGpps43lGDf
ZIsh/u2Iz788QgNOYkkwfpOwV32k1zGadP6aLj76/9EPe5r9XlN/YInZvIh5ihILqdTFoD5Gqazh
TKeMPyWpcy4qpwclkSYsf4e5NWUPeGfLXndO34heX0D4Hh5ZebZByzikv1CAI+4h36e6S0GgUOP3
1xX72Y05RQRaAViIeWzjLlxN46GlzBuk1oqY6QwJtIbnNIfd7KsdUCb3Tj9vgTSUl6IgHbRLxA9Z
nte1tbtZwRIlqBPLkDguaoM6fFw6QRxn7XHJPHEzRgoafzshDjQOpHPDbHC0fvur+E/F0qHEWWXw
ywAMtAFErG+T0Mj3lBU4k+uQhbCBI37Yk2Goo3SqznL42/H/+/02c7gXAv9hI1/LTBQQNh7TtsP+
OIj0aNgwvZLCax31p8n6Ka06xcCjNc2eVapBQpm0KxBAyoj0ve4X41y+CiOSiGDsY6pdpkHHIZMQ
pDriTygw8NgbZMsu7pjSJ5RHzJOP8ZK5+wokdIq7tbhmjDF6+Jv1wpkUZ4VBxDX85n2Fl6gKzqbB
Q2WA5Xxd5lZnucu7cIXnPuIYnslJPcihda0ANRLiyy08rCoy6DgljTQylpBd069mLq7JJMbznPDc
jHWb9Ot+hMjoBdfPtNQieHF9CEvXbuce34J3eJbmWsOYHDUQh+nqU7Pey+K30QIhFTI4uAUiLWuY
IO3EPbJOawjrFLqpRYVq0XuRcFkw60d393I0NMd2yIpAXANSZeW8x8VwuDfJnul2Zy6DzluK/4Us
ZU8j58crjdibmO3cldgeBgDKD6X7mgPf7KNZV44Po71ZQsISulAXyr1o79/LqwpVdFcj0aIC/A4K
zpnYQCJvagcVrM+P7Smj6/v5z8GM3HIk3mMkJF6JaQwL/7cOdpxdob/dn0ADgO3s/WU+qGEMXnsH
NnVNVM7598bvJ8eGHUrqR8d1m7pVSRHcnPvsP0xfi/tNduZcEp8UZevbId3p77KkoUJ/DDeWdsU9
0Kyfq142YiEh8eT7NdOT15NSuNgmaWrykxTXU+qjy59RmfSjJf0sApdUj3PE+8l2gF4ycN9eCNaz
QeG0JEsg2zX5CJ2HWB7zBFCa5rdT8SrKUYghwLTWPT/4RKIpbV6zDNIdcrmXPZRgx5gtS/mKDzDz
CK41epYIIEIJ9qZb8wUEPMLqfCR7l+eu3rBLwG4XdVOz1K0BgbjeFEkaTCq8Y9cz73PNxWisrgHx
nZucoIDLdnPk7+44Q7O63pQbTZDLIACKMYx25pAu2wD9POoNU73vINZW5EzCQOyTYFH49cMed6yQ
5ccfzG1uzSibLSB+qt4NFmbr6GslBsLt2poMwMpX10/L0JSVUK6ce1R7dsZ+42pVm0+qvDG68aG1
8aFQ9DP2A7DnjvB5jq8onvI08K9/TmY0+3n0ngIQOzgtMUuEN46ORpaImSkQIijPeu8Yc7xwx9c5
6AIW2Y4wIHmfOVRp47fA5lbL4NK7J6MFpGOjlu+dlfkyoDAOhyt3P/3Ch1p6sVQjLJCWrJTHug/8
xIuLhv6xb5DBQ+ZeePZnGIRTgMCn3Nh7gtqW+oO1UGILvDNhmOD5sNhI8QLUSr4PxApwFW1qo5Di
PjIGGENws1/crJPyqJSnAS2eOj6456e9y9SiTE4KYsqdUK+/p+Xc9e4SZMqBrzdbjFQtqGnddGs1
9lYwpw3voHekvRc/uaAC3v2OMCExpScg3gBGHOFeIqH64PyR+CBA3oWSb/6+KhQHt72MiVFvPR/J
aeP9z2M3wmLG8PAnLRIWJsMmIubfhoi7R5DtpGOKNpdyjF0JoDkG43mZJrhI5sQenPECfthMKkxN
MlmfSPHFzbB/bNMBt2GG2S6Ta+0Btqyp9VJZy9nx5JPddKeuj7oUZgXNwwiYrkJwneMrjxP92Pge
ODcXmaCWuSaan7rucqhN08KPg739zLzAkuCCos0cPWCqfRoLIj/uiVytO3TPuvd3Dp08DM9HxGTF
hZ3z4wE0+sJzuxcgldDIRIgzJ+33tHYwtk5o26bmUAunYPApFdJWIC9Su0Cy8ni2NIkR/X7vEUCD
8eFG6mC06OQnlT7Pk66B3f5QZSg6CZdwnR++jlQk+waCIWGjARxcitKX7cE8uPvgdgKklvugMBQc
0Ls59wb47Q81pS/nts6rQ5GMDtnopM4xSaXNA52uxbVZqyjHrdQTYEtEyF5OvBOvlQBvOvN7gkPK
2aFOGiTdO2H1h4XPikJCLt9E8GD9JdmDR/PjSuywQJzpTz7U0oVE1dV0wPO3i+WhCD+LiMK7T5kI
mXfIVOiF5bIu7UwRbeHU9vZ7wltF1u6FEmmmN32w3yif8eDKdAKM6GbS/MPWaWYWiTLiHDM9CdZg
ZB0hPoMnoXt6qr1lpteVlPizHmrqwbK9/2/vAbQbxi6/6iXYiX2M3PtBSI2Ec7JE0nZN3fh4Lf8q
pbZxU//bSUV3bxagAj5ztjXGqsnRB1LmryYB5kvvWiNfju8BvCYrVq6FqZ03Lo1EPSoRfuPD/FW1
g3DVpeHRNAHXxtCUIkF+0qEEuwPmQz/xFDz90mAzod1ZnoEW9pn1sQ4qMyNC8HAV9fPP87dDUJoo
9NbY+SL9X44zvXw22tKRDAd07YyF2LacqfuAVCFI6qIuiRB1KPwn/k1/00eJZXtqy8Yde6a4bdFa
Bd7rLnsJDQYVHwdh2kn7/Tt47ynqKFyR1S2ZmUlCwaZdMaX98sJlo+uaXfgFZmyiTBhkRYWoUO7K
G/B6ZO9lUkv1BBO4cF8wQCFxG0lOPt2P8D/9P1VOLyr+nuB7lIBjl7FzksqnCP5+XEGB2UsFfQkW
IeZUPNXcjH7fAtztKBzFy0LCPhdc7R0lSOVDwL9rwSiYDhfL0lwCY/DCDefBc8FZSCHnsqHiTckS
A/82qn3SE2tu7kSaLB/gN1cMdTuz6oXq0NS8m3DKrz8JAnWjQcwpMLmsNfPSMjkiqqUOVbgwtLMC
2+Sq8UAt2LcKH/Af2hUmBqFlq3LV5KrHECAzZbY7g0fpRHudniT1QDb2xrlE/EWidN3frTGXI8Qx
cT5M0ItC6gwsyt8+zAEph61vqr1POhOcvn+Wev9CSUHElkWESoZOfxwnQ1pNXGzDOLeArJIVjIHc
yRopQ1+fFvD6oa/7ts9omjmezQjahZjaW2dYEtg5oLT8CqFnRA2tf2KjSTEk/XwbZhAh6Tsps7jS
DdmB3zIH0mOszUZD1nAxUHT54D84p9ix/SCiIUfQw28vjGrSOTtIAiaodLKcDrLpZFI1e99obfo9
RzY8dYVkbxax2fdubQG7TyEkQZP6UXqud97awZEGVjBL7o220lqiyiJs0nV9MZ/VzI7Wy++FNEdy
ItpnhDd/aYX5n1IwEXy3tSzKQxKvuT4dKMz1FeVHZBf1b3zi1m9dMevzY/nv4aPMXm7ccBPLbcGf
QbmSqdJmCys3ybPHHgctdpHfisuevUKpTb0frmzqunvnkuK675UCFHJegoJjWLa9lgeMLdQmBy6q
75spM6QNXdei2HFxCTqeArnnmoiOkrJM+jkA4KlVHvSHzD5XgBwnxnhNVD5dziK3RzrQeou9nZoi
md/Vgf7FQbbNSDfRBDPWp1Wm7CnF8+tYdIvT3hlt5aL6BtYdjK0PdyevGLNIW2OU2P1A5VS1ot9G
heZGWjEZPfhqi4p2lSdHoJo7C8DhBFFXwnAeQnd0cBC6Dpe5k4HkQ+Y3P+BUO2BBqsj16gaZ1Q2E
ti2ER8sh+iqvBDWqvbFPFpl0CzOSEpjwzxEEaHGHy25Kdnjb9VV38v8Z7vK0dkMFNPG3kch5l5LF
BxlDwAmPY8SZcQ5MTlP6nXY5BY0TNeWWk/FIcJpYUKc/1+6CoYx6y1jKTo6kFTxL73KBGBWZhfpI
F8X6GWnDx3UiQID4ZnPmx4AcaEFYZdVYbcAGJLtmvs0jS2Hk6Aqc5TZLzUGabQvKGxXg/+g4SB+s
3m0W5ABh160o1JlxRyNRZMi+T07DLSVV8QfE6o3iaoSamkX7HYEACgfyBwR9HUnfrNWGMNHhwAFQ
xN5wTbDD1Tip3d/ScDEa/xTJRN6QaPvPLwDBA5AkFGdnpWyKl7u7VtcdiOuvEkIiHYLsh8u+AdXj
uMLkRYPT/Qzm2RtuX8lp8QNE7KTujFimpgdEkT/UicrAoEaY8Ku7W6oTnHjmeyYm/OjT9BrsVO/a
J7RePckaarTcCmVRrsWPw8MSiAsZvG8RbDj9WoeDrkH6LYdlck9a0na4leJ++JUi/Dt7/MiDNIoc
oOQUt9bPzOjnUv3qYKnQyfw/KZS4zSjSyXLHa8cKLIxpXwwwn+j+zoX978kmLFC1znsoY/A8XFnX
mrHqA+GBF+4hItqmcpG9iVk+4LwEjI3K72D9GFypC3ud7Pbplk3R8GJG6OiGwU//8kXbtjtXm+YT
7DE+PS0Qw2hLdSKm3MzB6hjfipv8+cG4B7UoSSUI76nShJA+PW6vSYNOaIKe2bt94+O1+wE2WyA8
l/Ocv0j7bb98OMOSocaxIFAcYOfCbRrEusK7yklDWgJWy4fvkscIUGyzp2scw/b7XmsqP09Kf74f
X0brigxsfc37Q+exVLdnKbh0rdrgHcf/wo8YPmcKz9f/Hrt3fLTftZvOwEmPMLPkTLQXMG5gmd56
kGG+xVZUEC568N3Jgn0ib4ALH8x/8Sf01micj/znQfoOhlexZHxtz5upiHotL0BJa26BNMBVvnpt
I91SfKxuMy99H0OzrOqqpKclTre2usQ2UhdDaRQYYcg0Kr3bTL01DKD7+ncH8PBtax0OeBeZ5cPZ
Di3WTgA0Hc4Ue2TsxeyI+waQr9en7M7rNQ9UQF+jIs93tAdxlBLW02Iiy1bD3IwH6LaKbNgMCaHw
VBsSvJWzmk4cYnw6KUsNYxl7wASR8xyGhfo7f1P8JfCaX+U3p7ecpUWBCrTfre2DZiAu3D/U9paW
94yvZeH5NkhIesV7iduu7BNgty8CwK4GGjwYZOQ2w8KIf8w9PKRo1ytHmcOmjwH0AqJggMHdXGQu
8DCCTBbEu31EP9swBONZMPEGTESDHw3pCpT9JJYtCJUpQBzSfzC09YgfJRVPtJ4RXpNl0aOeLVQ8
jfl/j6qRHxdE8kKh0jWGAOCCIQjiRGL8yhy8CpF2KQuuAuR7rFBJlLLBeyg7MvmdUhhdvlchCtp0
yCIeuYsvxmfVtSPyohdO+Cmx9P9yStzeFn5yMAieIudtE+MFBIAc6DFt/y7uUQQv7eL/heheetN+
2i33Y94bmEGmWmXc8VeGYcKa39Pc7HqQZiecR4a0xW3OZbth3CCmb2hbsc03pgs6sEnV78OP4B9O
RKZLTEgBut1DnRgE/+hji99ORE8BM2pfDf3L9f1Rf0827WcD4tUlAkxGQHF2zCnNeYwVMSFDecqE
IaZx9kR86YopHIc+bZsvr6vzBaivZG3Hmn9aI03+aXujJivzfaQiwxj9RbYRvDeQkPtjDQ9JrFiQ
BRwteRS1S+EbjYxMWBhnxboPnx+SUqE2qaUlzX/83NkKDnkm/nBVX2SGrocBByDT6s9SD4n+jCjj
jNhgrS7M4N1nKIFtfslfgB3PD0ZtVBGvBQBzNrC8Vb7ezLaCEt2OIEybet9k4sn1RQcwsfp+pb85
qWg2BJ70V1EyU9PeXpgw9o7RheWBQKYzU1mJmJ7KSfGfEkVaWlSfw8cqtC3gvm6wnVuwg+v41+dP
LvjLSG5oqo5fa/cVmDeZFhZzTNnrFylUxP+Bg1xJ+cY/YUGNBAmkY+DC5Deo5nEU9cxja+ORLgXi
H0eLrdZrznY0CmaJjH0d1Fv+6z3gIxdp/O6CpRqmSnJt7OGUnPlPW7nWSdiBSM3/yu1o1abZYL9H
PgCD797EgvREAnzkdhKV6Q/gkeCH2WT8+clyr3u8UEIvZF5dGVQoNF3u7bH/Ud9irrRGwIuKOFJa
Kj1qcIXhFsSX8jataQp460PTyRoDtgx0kWV+6ORS6EWcVNqmV+1//+bRK2MlgsVD8SP9HHurb4hk
XArzX/Pd2DNnCeHG5DtMC7vr9LzGeD3hUe9KNs8oICjxIHHC6AQDkrumfsY/IaQwbLTOtrBKAYWK
3ItULtanfhDE7MsMj7Mm8xbqgUkpwXuwqegNuAayCPTyUjW16F/nC8wqVMKxm5yGY64ExRKvPQiB
UnSIduLh7PtVs66vTYdGX0G0R1qyaCaQEGp4VU7aqf1TO+zC6bphjEcBKJMRoZdGTBvpQS6sbm4y
dHbZnytgTk9CWGsdKsfxMmXub+AuIi8IBiyosIhDpoUxCYjVRJbnx/VRy4lj6+nKpF8wb7LpbBAo
hZm/8BXrUkacBMTYxvGrFpFTwsA2KPnSMzXVHMBoPTMx+MR22r7d26o9wTlNXoRinKcN/hFCu7b/
fd3G1ewp8IKh+fagqktk3Zb6UK32Xm8/ubUuq5oqPKemOzfX+sjqBoFhWPiBRhRIOEHlP8YI+a8G
ZOcSVSUSb5fYbD4D38RofYk28WKhKK8lz9msUKlhW9f+YfAftQo9Z1PcS3jGgOa9wFC7mu86bYBf
jc19m5QC9HZX3dpR9di7PdROpiF32NKA0wEIAaa+8QwWxBFiZIgo1rIeeewbpDFzxgqxDmZ/R7WJ
JR0eTSq/WERRSneWruXL6QT6sxLFV5URIPL1ldnwUmMHj2790kkxLtCAs5I6V550KZPmPrMd98tO
XqZHgrTz5fU04MBkgok5Dpn8lEVnhOHVK6UKCsRMnX2H1xToK5gay+q2ylLGy4XaIbytLX/GJmhz
sHa5+4iZBWgw2ErzsB/dG/yO430lADiz0FPUYqExCxre36B6e/AXQuNRfGcLCLARAjeTFodPzKC+
2Ncj6lchL93zfmMCJmC3PvsIhKaxWr0LPN/q3jj0SU1Ikoqu38yO0E1T5Kgbg/GmoAcZDLIyFOEd
x3ir7nSl/VsMFXe8suTqEpTUmkOcKrsUwQYWj50T3yY9q7mDYZoxvhTUPOmcsa5J72Pcem+SJI2W
99EBVrPwbMgcP8dICDYe6+0E0phqWTy/pIoJ3MXVzssvieYvz6EJz7uvhdNkRxFdbb3s+bZ0e1hL
3JOd2+wRoyeviUzn0BfPqvgEGUFwoGTMmz+ulKQUIfmfVG++miaE9iroLJtp3Ao0h+B6gmCCyRIl
X3BDC27a5zglJMctB8ctRqLxK5sJ9nusvB2910A4kBfhOel9n83q8J/LuAIw0IINjZ3D3p1cJgiO
TXsdRQIQeiW1Zpib7sgL8cERbGSZcoicr6HO4bEfW8WCKERJ5aaCE+cXrtJMds4NbvwndaSaZgPq
F1pyMMEzCC+VcTeoa5Kbdawumlq8S9wvdhHYc44b8wI8C8K+LcsYv7d7UYiaeffkI/wiSlI2/o1W
IHG0O3kE5T5oSGuYsCug7qOHCnnT6Wy7sdLEscill6cXp54TR4acfH1EriEq11WWW18xPBDcLxnT
LeHG7rXeU4xmoMDopJ7z+IL6oKROvqcKtrlY3Yk5cRgQwJydhBeWJKRhi9Wtt3ePjAkBGQ8KYqxY
xfU9Vnz0Q8cSDMH7CTRSteNCbG93zuNfPGbJeYEdgs+jw0TP8Tm1gp1nNKwA/aF1JqRYb0GugQ5o
D6YcsO+BMJNmCBSkfdjxKi9bL/ZR5yMOG1N/6UqBiMiTyYZz/7Y0LERs5v449feyJJA7mqeOYnN3
QFGv5HL7KHtAQ9omdblUEo0qHgl/CREv0l2Zb1nrlTDGHUYiY+hIwT761irZSNK9K6ZQN7lMfEuH
h45iMADk6bT76x7ohpFr7B2tbdAI2GfPp2iWOfDw0HCFDqICSr8Gap7q611+VYYHhDZiykmdRhID
qZmqNFcA0lkGLbJizlMk3jcOGYFoYbzDviXm7Gi9cGVL4rAk96qcUj1a6w6YFNMciy++pIe8HKG9
e7t3wgh0HZF0X7fz97G1YGCVHzHcmLCEP+9OJ2DXsZlIGDodkArCeL8oOtL8xTK+cMhAfLLacV9P
H2jcV79BLNqzPUto50nj+/n4GC7qJvPfudVm4yDwl/0ywYWzB0L8KV82iHA+x950+DGSCJRSpxyi
MiyLFnZ8hkQEs2dMr36T2e9kZBSb9EvbSrBtrJpQEQUV4UXMZ90oBroaZxPtOgiwS6BpD8lgBT9F
+YUtFULltr/oJdrJHyHd7sCs7M5tm7jsA9tnYID4UfFryDuP6ZI1zYraY9aK38GBQLzPn/HKoKWt
NYffw/gwGp7X1i7ejRHcezjtND9Za17HBnWgFZe0d065V8e/Y+T24OZd4PDvhmtfDcbtldarOMKL
RxZ/z90MBBg+rAhEODq/11NkDhx6SKclpA7M3OMahI+onSLl/DQCU+3AKMKPDDmQYMV/jaLdlBrW
lbXerfQAAsHln8SD9DvBMlbOXo75Zb6iAEasI/V7uuwOdZLJ/4AQhvTnF5GX3bncCGDW7NAjNE0E
iAfYaAvPSo4yzR6nJjRwzPu3D1hH351S6VA7MPqyYNLyZQ165JmlufYdBaqo8rE/ylNbaL41549D
eLIQc9TYk55/itjEK13ECpBA2KFW28ucO5t2spdmqxPLCLntp7UZiaRfnXHXjBvEOspBlTDEwBR2
6FXTZYpAYD7tWCeaN8eVQp15FRQ437D6VEkPL1QiGSYz5WDSoqaCGyFnftaV3xpzseGime+OSpxp
KqAKHj88xJ8rrRsd/1COvoEcdKadTXgKgP2cB/WXrQsTx/WFGeTlnprFZfU94FmNs8+HdJAFtQ+2
zv49gzbM3xTafqneouZRXI4CBTXWHR6tJJlQ07kBnq5dAAA+PZo1T/yqFO3CRm6pQuJ1hzUBEY05
2XubSQsFtnEkVkaxa/u2uVIhA847+AaQZzi2ZtzXsNJOm5M0I5J6lTgoLEayt03MrC3qKe28m124
bfxxGhNaj7YPDT1bBtOnfq9/dN2NWuUZh2j/Mn41yonkV+f1p5MqkXti0qo332AaZ8yzLvAbSzUy
pePQtR/TOAFmqOv6PvzwQnblfy/sJj9huPZDOotUtR2oJ6J/5mo4vTvtENQLPmKD6d7lQ69BxNY8
LS84zlBZiM1RgGUJ6sr5DqcjRQjrcU8FChaPUlNLmi8bPWRNDv4C7gffl6v+ACD0ymUxO1ygdUaA
0NkH6qXQVQo1Zq0eIkX+46iLVfC7ykpKI8Lvh8NF5YcBdrf0iELwH9Qy2aSAiul/ZX1xdkdhR/1j
5YrrsfSt6FlcaPCKercYLYmiHLHdg6tnnQullJwo/LsIxgSnRsn9tlqUOMVQCB9dPCzBlJf4G6QA
u7rlX1w9Kf/jxyqLsNMixjGbGgRszbz+5SVhmaN1gOoqtUGtQEQg0dYKmsiKIqLCSLdxpuT6Uv/x
LUKNIsLsuFa1vk957aN00zL+nkDPSbowHmPm8Tds5hJoM1Ri2K9nq9j4+IjGw+pYfc1J6WNVRsTy
2gjCvWgr76oJp35MbJ57/kyNW5/npakWUc+DmmYl76qdX473OCH0sLbUEE0eia3m/49YLdKHzEmi
mPudFrY0CV+zh4GvY4IhNs/HKx3pD0r4vaBGy20vHmivKdYq8o1u3ri2JbDtDzDSmgzKwRcZ81it
3Ks2Gz4TwZhyVOxIbyxjitcv/xVAL7RG/cNLw2efFUnRwftKK0F4e///ELOTIcX7VuGFg4Bj2wwO
m4VR2SYWuPHRh/ubWkFeYgHb8P2zeY0qrnpedd37OlcGaSagPWR44Bc0W6O6nicjyd4twAbbtvop
Gc0HlTKNwQdkeH0Kam3XxOJiv2RNjKlYyzDOvQIiDgtDFj/blm0ufb0M+IXLzZHDlyjqMrrpPJV8
0cv/BtNG8SEXd/d1A0sRDdId9NLdr2IK4RwuJObrooBBwrKT7JuswIugnoR9PZTLwdrCDLF9822Y
kqhPUHzatXvpxK7Vi3RmEA5WTpl/YQkWDrDWsqfmIE6QG7KqBC6k0+q9SIhz5eaM+KnKZrfiX3sY
+XTu8n4eVs1z28W8cEXcnbEmj8oMAGnloZE+vGhc8CVO2C+BRtpK+K+ZOD9TUL//NLAa+eYJlt3k
yeVKnQnbU2OpqGqPB7CnS8Cq9QTTMhZpU2yfFUAX+074BRfHFBwiKyBXlV8YbvI9ZJfQtEDi2qGo
mUl1t/Wee24NF0dYJ+r8kj+VzjtUQ+hwKXC+eFh/z8VhCM748FmIDJqh4Akv0LCsiSblCAdA6fxl
+lLNNBruT8mfDnjzjegYwb4lMjZzUT2F3x0hR38l/JJI4IPFycEDo8eYZknvZAQWB10GMgCmE0Qy
UugDjYVMXRita6wOmJ2HFLS+d3N3gA3Z2JH3MqqRbB96N1NoCJVviqd/66tzBW7s1EzL9wKkrIVr
ujFjRpb5LUhLkRTRr2fKUXzL/cqAVB+AmIoZDJhuqoJVucNFQEJuxpRxbaF+fhnZ2Jyx869DP4Rd
9xpcBwV0w2UbrKPeua1RiKHQSI5xrB9YTJuJXzLhoB6zE0EZHRX+W5aOwxcWCxygm1a0GKDSNopJ
WPZnWYGvmajT9eMuIoTyl71Es/ZBgzboZcigoVBirWQ4tLeDYwvSFMfqCXKSvq6nP9UitiSrIyOy
Yt8m4DanWTPYyx800dEnvau2vwCNkeuql2/00FG8+idQLmTiIKHF7XkOe6ob9FYJW/Qu480YynNX
JolhG8nVwaGSadg93Wn43wV6Q/dFe38qyojiVpExGZ/6WrQRjgmK3P7FXLPvvFHHUoarXhsFgNwN
Ff3rcFc7Uu2vQOb2LoZ/aw5tBwJVttejCQFGM0yAR2k8pEOxvxtA9luZ2lO2E3c6Ffko3AV0i1Me
xuR2z7f44wkYcEs/SLDpvA+naFlWXQgBznh5/aHsz7SUcaa7KZBw4Cj1w7F/uk2im04yPCB/MiKo
/aWg59o3HhufY7cAGXy5ZfvhluAbbtRVq+xzfW9DCwSjt7KeePGJc8F/gZ08BCjYbwmipzWdoIL5
oTmsHJx+P+/PBo29nvQpqhahKqsZ8j1mEk9+aZcUlk09iNoeJa6mMfi/1RHDLvCn+faS57/5dr0+
4KfexExnTsz+YF/AZdOzPzUtonq+TqU7tuSxv4Tx++qlTUuJHWPk1wWEuKxD3sPe3fxzTL4KIk62
pe36t/xGHSPhrkXnc6LCqeuZe3k2TYNeUaaekyr17yFVqJBzZ7yDMPHg/YDqv1m74jfMfE014f1/
X8sKyhuebCBhLRQPOSrd/DbHY+NLWtv+ooatsbhFzPlIgoWhCEThz6kWPjzpbj5FiqIa8msmO5o6
gzU/RYrYwgZtUJRy/smGd4lzPyh4ntBT12ES44RC5CBtlA170QQnokTRTGiDonomr7a5gUEHhZNy
tTvHqFD1Fod04rJ22cxQtw+pQ7NGKZfP04NA53PfTYnjFiCEaOY2pxdQ1iASc7NaWwUlYWMpFQna
xH3DuVtFTXy0DDRJj6UEw10BXp58hyZ7OLQRVk6sExgMmgLm2L7gbDWz9DJTBtpi9tJ4vWS8dM9q
gdyQF9/4uXaX3Pj0QR6fXNmzc37VV6y8x3yEdJbnB2RnBDAGbYayua7ml+QC3jJ1gpF+j8VYiM8h
VZZbcJn5obKGxxkiif2Xvxc8fsjSEoq2oJIMQbvtY0DjX1py10B03RmYoGB91W6jZQsYDeoA5hf4
8Kero9agafktcF9QLqi8M8+q0xEhYWBKU+648EtvFC7tOCRvVjTbEHKKAx1vs1OIyKzvZ2LDSVxC
2eq4PirBFSFSUqwCn2Lxxz5GJf8hsH7iCHgPQb7BuoDaonXEqKubj2LiCrFjZ4JsOuXmZy2yU3zv
GPEGuK3RozhAvJgcZsU0csXXMPDe0gqgZcvwXbqBLUFFISiBKy9AcJ26kV8tGwqrQxKefFoZjfXg
t1ynPDVxE6nPrY8+emnG9JU3EbJK9oanP67AI5uKI6hAD+nb5tkHXSpeOQjRIuvWCjqnXBiE7XwF
eKHFIMe+wAJuy2PNKCTux1A0yNrMDrgtoLUbKp6D3bpnHtR4o4iMOttnUkMtTU0z6/LG3xuc8wbZ
ySIJJxNEBcibKe/Gf70codfXHw8nRc5IpRs/IiE+dCqJHsT0n5EKYb0VoBXDq/9V7BMZN7qe1BBw
VYj+zXwOrilER37ngy9f+Zv60kTJBaKZi2uHlIrzPwm7lVk56NQc0j6714L29xiIaLVfBzuNvxBA
JFAADos6O6KWUGr8a4hWnNpuGTQcrswcH61qIoe+/0MnYVGQAA5/MMNmCWPT7UodTaIrD0he3Sxz
gHZFpM3SysOBjwfMkTFCABBr47Sp/O1gNVaNC1GRo9mvAzwcQIhkEfXjaG4Qdd+kOQGpijWmHG48
krny8mPj1TyMx+ar+SxuIMVyLGP25FWzbU453hS8f+XlWXdVNJceAYNkx0qDyQQ9zxfKsKGuVpw2
7Lqx4Eiwta55E1aaiEtIJOToDR+Jby/diHhOXWjQPaw5nMy54RqL2ZW9MAw93L9EmkHJsw3dJn5s
2YotUY/JQSpmeW8/14QRoekMnghBRVhAJQmmknhjZzALD42Xkf2SsR3+u2qdVtzNLzHunXmdm/xm
S7Ekk5W+E8yuOHI+Dpg5J51al90YANRuWteJ1UFAy+g/4WAAzmaFV7rNKCvBIFgLwb98NPKdWldH
e9UWNjzmecFTUNXt/SxkRwOe51WLFzFy8FXiOGY3ghTceyxZkwoDIwBW7psYn870g4jPRQ/C4ejN
OzwvR7Fd3vKzxfxQW5s59Uztcb2XWPvcblhPR91rkSll/HApEFtlqx5tMfjMQ883Xn9qBNAfB1O4
wTAONNPGeibZedsA70+ruosrzYoDuAXET5HjXcJ6e0X9yQjpEuBLvZ4PAe7Cmaeq3dpmCeUQqO6y
aNeG/3dWnjtGch8ojjIFjSX8q9+Ye+5GRR+UewF2E2GpLPGEiBlEoJdA6iLeKNbtYCbY3HgWukGe
xrbb0adVJXKTNQGMap5mfBQA0Wvh3ZDnYdAJkTrzBc443dKJebCJ9INSHzxlu/TyTUfYV4V9DAT9
Wac0NJTw2HiU7TUAoCVKsTxkKDl4rBv9/mF1b8KeprI8Vc/13Jlx2GTJFFGPTeyvO0vVqQdDLRi3
dGJAtYLzS11jXwSguS5p0nNFZExC0AO4Qp6WAC2qeajpWevShKwvvQVmsFa4uE9bxqHxGid3sYsD
q69ZEz6TdTatw+Xms7Zpm/ZJiuiY+gLD0sebFd6AnaW7ux7wuJF7Ko3TltRc2DMaAZzXWTdW/Xui
cgkgJpoK+XFhk3869vn9lV3okPxO1VhSULre7OcZghiB3h8s9A+F2+PGmAoZnRz4ekIYzcYtGLkO
aF2yjuDaO/u/Jk11qjzcc+KLQuF3r2cOhx/3LrqTEs3W3ehyJdGNwtu1P68HZwocUcfjNliKpeNa
PylLsWXm4LJZBRD6TnqmH3MQUIzu7r0l6U3A2nnadnp1TZ6XiRMfcoSJ6E2yQ8SL6CIcf9KJnMIu
aXfWHqEgiR5pbfwOIwWstKxWdXTGxk7o73FyjYhqPMQ72S6It6qV+SoMcBTd4Dhlof8Bar5d5Wnk
yk2jaJr/kpdknmtY2C2RDZyA4tu8IMNxfkdWSZ4JzfQpfwNEg8uyodHHKI8BoB7sW0DzX5kb22ql
dICEWL4Lwru3mtTOZ58mUzzcIxTuFJ3QuvxNILAdTrCoB5KEisZe1zdHRwa3iTMbAi6mCDNsqgCK
IrklmVx2uAq3vnrHk3PSa6D4UeW/uH5LKDEKMk+GW1mDgUk1wPrvfRLryUKMgq7T/z05MlyBkq8D
tdc2d4zGAKiH8uAZmePfSXl0TYYN+u12/IdCwe8XMnHwnTAp11hQflyql2IDbWKj1qOW3RCSrH3b
mQ6i+QQ68976oNMAaiUlLg7Ece7W4ACxmgFshaQJCv3SJ2SwnFLNjYex7o1T5Quobg43Vi5uLSr2
6eM2dKMpk6iOrg9dgMJq5mxCUEwD9PMtoQBBIeZXekam0zRMIBdC2zsSmJoNr4KN/1Fk+GWqNE99
jUYP/JqtNJFSOmhjDqMiQ2hMPehSfjxqUVhxX0P58C++qdqUNQjl+2Nq2EOrDJkrJsJIlCNsRe9b
+roFa62iQUGQujNooSj+FtSpnKJpahf/yJgk6QcnZDwmyEnd/FD4Ydftshbg6tksR9exFqgxqycc
GtduAC6kwFpq7LAcSFa+jqjlB67zlC88CEQxLlP+azgizHIHVMvYDjkag8nggrl/W4MwXIU7X3dj
BG2+nNRRMdbg/VGVJBK4IA/d2kPuHy4LFphdwXuBklTU/xu+1ekKj05wceYkQ5xrQYdJSB5/bulR
R1EdEeGwZ3P4uR1WMoKYpGpAVH4DSdipChWPBYcprX1+WXC9i7BwQfUyEl13a+eXiTELnzCsHxEi
7z6A4yQ3WwKenpOb8gJ26JVKpSZ04QfzH0qQQa0jcm3jXLiqrJwdLUgLE1oFTutTNzoNClUpuhZH
nQCZ+kH2MVz/Kariqhs58wlgrsNy7przzlyn839bSV8lF8k2xINwx0Y41gw4lH1nUk4UwGe1EBgM
airsAgYOSVQBuSCycbQ6z0V639mouqHURx+/3sIaEOQ+2kwLmPB2dNRqvwiwNUD13Ig1IMT1UrOn
Wf8Y/nWdmm2ks5pyiVIpNHa0Lx5ZIfh1SncqRQy6qVeqT5hSkyCM5swkpEJtIdgg471YIG+O9wx1
LKVdpOKdrznuz7wo4vbHfpEvAAhL7uZJZSuYgPinfKfnlRvEirMzQmI+2+D6dEDT/XEpFd4Rd5Hq
Xah4/lPUjmuFxiMTb9s/7L2VRYiKutQ3GaW+NP/sM+wq8ahcYsu+1ajqUzsTvEibhaxd4gCCjf4b
h9w3nRRz7lvgJGxW+W4YeNUxokpgsokV4YSVx8ad2N9IKCw7M/l5rONZySjdro8m7prIHVsLJA9K
6iYy3FjFUX/NMGB1N28bw3lFT2Ifqs21N0lJsMLZiri5m/bShS07RPO56pgUWaBxEud6d09Z+Vee
maw1hJakxNhmVI+nMZbeqeU133I25LNyLWxtpVYb0EiDphr09cPlbCl54he37+vLdqVgQDbJMEd8
6813f9dzDhxb1hTPJBN7LrK9u7RidsgSlBnhlnh1IDkhPXe1NCb+Kg3+FWB0uKRemWx+/mIzkBVJ
H6SQbyXZ+fv23q0UUKk84dgKDLJUNEwlaupsc+dqA0rIuelEG3O/OEBk3yYBZrtlvr6MhFCI9Ua5
J9De0q5El9NhfRTf6jvUWvPDGC4Ol6Z7ifYg0dX+H0YuM28WAdDpotD7RpIBsLn1GkMlNcE2UAXB
9R/xSeEnNbARbzfzm1/JPYuMptt3ETmtcA0vYAHeiHGFBf1fAG/wuqCC10kxAEfmYSVdepQSh6Aq
gd+8TGIHr6zlCHV211QdS76ZFNWClGqq3EMNHqfPqOOuGDBh+2ssgR/xwauioGwSMLORE2Ok4Cy+
wgBwzFd8k45L7JdyebFsHG5x6btUN5SRJM/V2x7OtMcF/hCvO9FiAo1eTMLA3MbCw05hsvzZKv3l
U3+T7S++yItn2NBXeU0OJW/OanJa3gtUfvN1bGWME9mh1Uu3yZXloFmrI8P60AESo4+Rq0aMgZfb
kp0q1NamUazA5R3UtF9CcF/s14Vzx7MBwwSkCBIp5ACG2fUe7rvDgLv84zUSri0tXqnokUXPnNiN
c5IwlmBT5bUm2Rc45QHhmaslGDXgnHUIpk87+lYt++37Bc4uKYvblFg+ji9fjX5B6cSzdHBfPzeV
okzenIHKiUGatNjQx/X1tsy5KwfCqOyjivZg199X1amgmIBnmcrNa55At7LaINOYwYPm+y7uB8tE
O9myqUgOxz7eiJVx1c2SuhgGY2OZ96Gx2rqr7H1Beg47eumTjxrvDf2cp7eIEvq0aN8eHRvgrPcy
ai0RW+sNgMe/QaECj4JMUUhlbjQCF1o2h1DovZqVnTfUYkZRAQRX+V1O0kCOBFR9GnV3uiMlmmgc
wsECWAZt/tvQQjCZBchmPQdChdxg2Jd93EMgDkmfEfX+xZIDeO7hgjV0wVDEwfsDJ6QmRkNuOWEu
H0NFY4DkbJjNLxf8EIlNqpwCAz1HD0GfR8JKs1G8PSwx5WFI6rwoB9S59ew2J7dEcdxL9EKsZd87
QZ5BakR3Ej1hegGriB+oW5N8qOymuz8oIKuBql4zD4h/sGxkg/t3coaFadafc3Uacb+E7L31NPa0
BJcxSLBy4LAX2AxAmnbQDx4qxLFad4x8TZ9aO0N1g7H26qBr+fcAAYHs54x/n3yvBzXMKWQhie4X
VUvK47xRLb8zY0CVXPX3J+ASaeMI4FVkZ/UyCtiCbpVLT1jEvPRryVTdG4goKp8wrCdaS0dDFbYl
E1cjUuW1dldtRkbpyWLvWVcnyuoMhXGiVLKJizhkbt0s/j4OGsaPpyx7oS1C76M19Vj6mQyed/EL
eW3va7gYJISO9/M40lcxO8v22yy1wSUXrsoNT5WlzZzcRM65fj6pzOsGk48ASGp9jk6/9Fbr+Ymq
paaOIaDJyAKtySCLGWxHrA55nf3fmSEPOP5NcOBzTumjlWG9fod6CDKaEDVxBJMUtSiw9qBNinfc
N6KA6dmUIqUTexdRsMPSo88sQiqJbwnIZXd+ro0auYicSMJvd7o/ZSb7d9elKO5btOAschOi9zl4
+GaWQJsp+TVrPdNaPdoRuyg8mye2AK0e30EVQlN7KJkmokuQWZNQddPHNPvIMCGEkVB9s5Onw3zy
xKfyrdLtvWzF1G5JT8B3/pUMwYWW1H0PeHkOebySO74KA/9hFaq+G923N2qye0mshyEjr/lLSB3N
3B8nsdLpyOj4HqHucK5xRi1BIrE+YON59cIbECcpep3fZcbra6JczPpIW8XhS85MaX/5yCThlj7T
5RQvzVYBRXUBnFu+sfaQMQOTaNuKDQBi/eryYGVRLOC54LIo54hIe6u54wLv9KVX9cyjTSK45CEB
m8Yb7ce/ihG+EgUNTjDL3nJTsqbccv/DojAlsiE787q2svkOrRXzpQI+sVcrAATxp/0+35RrMtIb
krPmmtfQZCH3lXNDr7MZQCIva272kL6/VqXb/2ifoIZdcb35UijqmSnwFbIlh0l8jD4wjFn2GUNe
c+w9Tgql/XQz0FEtw3gGgOGg04rN4wYtM/oofcrBBYROjGoIsW0aZMPYT98jrqOCcmAE6MPKoRcn
dTipecc9f8+CvlJduBF3srA/18MW4nI2TMNwQuxgx0LZRr5tXQrNekGWuOdSBQ3a8po7gKV+Gbln
KfrMWB1T+fpeG8C5E86f+y+yPV5FGgeeXOtZqIEB9y7aJln8ARCCBy7QCm6gbEkphBPw+8HBcDaC
LU2vtmxujgsR8Zb4640Gjmu5VnMlSv+Quaf7sEwM5j6QqSEq2VaRad9xF619YfmT3a0MvnEAi9za
yhdORmLC9tF7AM2CAyWcM/EWZhRvMoKc+Le9hIMh60Xank6G0ZSYIsShXzpiS0giWF3asLYxDRXX
XIQX2ky08L32JWBLas0oiKWYR7gP0iTwulhGE4ljyKtlZpZqUwYE8WfJ1ZEnsfjkbqNHUU7Z1oJ8
cgwLKVgcsOwMEdtUqONOX5550v9S1tkAmmSxgqK3fDsTVyu06Y65y/rmUaqS9SS12Udnkpscwijp
wSuPk1vkNathOYxsBTrlCC6L5VWQy8+BkJNl5PTFg/2o2/6eQe5GxuGXGLoyUAu8nvQBdUhtyUlc
x6GCI+fSljYPShs8hOHQ5SdtaPnP3otZdrucPRYfJ0rY5VD6Q9B/ch1yhMPcumQBdzBJfJwnDLy3
2mtULb5LulVKOABof8peZPVyECg3ZCVxavdNOk6WD2pSQHqsHWgGJgrhdaL4ywkDsJEgh5xYhr83
rzIA0auM3j65pD7ENPH0qJ5GG0oUXIkbZSV50tdoY4LRExVi1tz4cRXKmAl7eC7zW16eCedEBSUV
BQ1XbnVHs9wb0F7czT4ZKJSpR0VJOm7/by5oRNfWGYPYpAHRDol5cuRY5jiyexYrrAqRHwDBzpgh
iBnNP796lFRKt22wvt59ONQd9q5342yyrXVYfpaLaYFIUqNbxdJQ8Zc3NTKSaH0VIOGQ7Aq1iIoB
nIHwgl7hpU0RNAg/5DwphxIpfH4DfAeJHgXhnvwKpE9mNJjb5Q0gLlFe1+1/96BXnW8+KFW83KC6
4Y3w4QuZl9CNvu4QYCuJnTW2nGPVPVskTOyvArYTiyggWamMSjXWecIclgtfiCxNvIMSZocvkJH3
9J2BrtyxkwrjzAM09RQtN6cq8fuUY0wwKc2MnpOUuWzqcIsuBTMEXSD5vxWupxyyHtdZFQkdTPyq
ri0RiWLqbgoXY6CyZxNRsSU5tI/9PEZ/bFxYbZc1C907ZeF/UViMz8opvKZ3Ze8GdPiKv8BUDJgQ
tz+T8yaSWqDL7Bj+d3P14Ahdz+iPJ5J33eR8j+VNCOy4L4fJWp/3BKPeG18se+25qRVgXJf9tIDM
PJ8/KFRFrlS2idTbazoqmLQkmPgFCB+6YPI+BagrF9rVRdgLcIMyr8P0zNFzcGBK8g1RZmF24Ibf
eZuV86Gj6CsZT1OUe3FEv/4Si7kkrjItI/he6MgVrI4sjrnVc7+pSfmkKaSuuJXR1XOBkKonU379
IPqoYiPDxToOojvkncaoOM60fssgiKs+1qSy757Hj3grZP+4P3qQY+ucGx9jMw41GLnusbCa09ns
PsdpggItOvvmtlafD30bdaU+7BTJB5e9TumA+qBcgirSpnChrUqmJlZY1cdhd1qn99nAfCEzV7jM
8xBoH3NXB01PW2xLTwoC/cnbJGpKX+PWyE6vEtqSymKDUxg3RGxV105Z9emf0rY+dnOjsss0ivEv
lFnsbORRwv2ha50rnJ8poCy2WDJNkZGMOsKGcsvKygscUXJymhqvNVZJtmta5eZK+XQs1yjdCqcR
/KHDI/LCYbtExLtlUl7gIDUVlaVaf3L/dfgbqavm5usOthyq4qkakTKznyLbhWBk8+v4cIQgPQ5F
vOIgeNxOQPH4Z0wTAZMsFVuCmWRw4OS7viaazLrhs4F7ZTHYLKcnhgGUw+Y5D7ng1K4kmpO/Ez5b
f9KZRtz1+IoBj8dvecYVHWjg0LPP4bOid2c/WZ3kRW6jpXTr+yiBtPb3jwuV6C6UISfrxPi14GEL
AfRyK9cldYHmaJdTfWfag+Kv4t9OJSUr2RWojFXa7+HIbI5KYdoKe8e+Y84yPfb5+W1nPy+M1BtW
ZODeHhvxbhVxuYRby4e4ceEvxitbfuwATx5Jh9XCYMCxBLDCYciMsvlLI4Q/e9b4wGSwIL91Mz1d
uITkOJvO6OX7QvQKPKgOxLnMPs7X2VwrctATIK/hOvjfdU9LncXs5bGAfzTPkR8KK6RjbY/WhL6S
Oe2LxLoNIKpnOmV25/6m6bXF/DzZjSWXnXRw++pusNZ3ZrdhyhuqcYtoU6iu7yi7KbMLfS2QcgIS
tw1XWjjQAtf8tZp9BwqeNiUpoeODe8FSDx5+6o3gm9Y4IZZK0On3NCvyGakbXWUmbiIomU9S2ZEc
fNMaNAL+Wf0Va9UcHZXImZ16RpzLPfclhhJ+60wj9jdeSkvrnog30v/tz9J1Z03tR+XEyAf1nM4X
gssN5McvJe29bLu/qkb4G1AGh+EXqB9AfOOcorDV5a75A+BH6OYycozoMeaJIudnqSaRpAesXG8G
Tla3R9LPT/zCCxqcg2DqOMCXqijd788t3F5PUc/0y4N9rJhg0zN2JPwf/uASNbZbcx1ort2xu/Jd
vxyT5k6DeOCs7XwbgSu+nK0BUxO5YcNJBTGg3/eiWiff8pZkVa7E7+aAX2AI+nEwSY/assY8O0kB
VUdwlI7ynOR431HkYLwkP2VzIyD/1D0ovBAey/dSOsCrE0QQaCSXXLnij0T1Q310RYQp8Ty9x7Jf
VYHxiWyrMfO08IJtOxM4kzW8KHr5gTY/anYcWHcMyGZKBx2ADAv0umsGGErIx4Et+DYAa99BI//T
nWazjzaw4SDRv5+CcgB/S+KyhPmLMLbeuAqIqeLXF5wlFEGQWEJr1LbyRQhYYkBc5oGquJoPNNMN
MzIwVD73d9rFct0xtNQ4ja9H6ylpq8TXStWlpE8dRH7VbQIklYP6XyyUtO6EA/Hk4Eb3stawn5aU
C9Wk7x60YbIAQ837oP555m+o5IcB/60LqVLvyR613th4D+qMhlWy3rivObfm1ZGoYYX1rVF7Azxv
sM+IXfNHkUyznWGNgsVjb9MuQd6YJ/BgZP0PjO+B8XI+I5x7YmY04HuXduRg6oULiCrsEOOJ9jsP
2s7ZpCTrQPAKDenNh4mYeJb/8NOO5dORzjpUYb97sPo63AHeHPb71AzYrss//3h3bbGl4JPqwHWs
XkvKsWp5fNZIw3obhTYKuLXyl3KkoW6owmAEP6xzK9l/gY9OyYtIpiBZn1eDqTcX7vfa0DlZUNpC
ANRw4z4s08jUMIhyPK4pD+4ET/hO/wnF0dCtQkO4KLB2kIOK9Q88HNoy8qks+UMbSWEpggoPOnfC
Qy9hXdEAIY8RYOviZEgge0IDmPo0qRPUkwk6JdtVj9C39CHMv/z3/OSoZ8+TimjYmAIWYzY1clhq
rqnqRvGbqV0jmCS/QIIGOSG/B++OQ9qSiVKCsD1bCh8kPWUQyoQJbBbgspzzUwnb/V3V2TncFi+3
qwf52qxs6UW7oTWWxFA3VARKGfAKdeLTWlVpFgj9b9yx72NVEGrj5AjkPF1j1Ou2Lom6FJ2s+XvX
w1/7J3fMyjH4ZhglNhmw2q64CLz9vFLbp9lzc1CC+JbkZVPZ4Q0Tb+Bul3jBwWNeif1kdjV6S6dv
MdZU0Y/Atv3ecQRQFTklnkbO+74UcwEI1JI7TCpPbXXH1m4vQ5k4WX+qHeNAfoW1nlStMBfD/p2s
H660v7qt+jSAXol0leqoxnTOliG0OyWFSUN7vrW1ZMw6g/8+2HwdvRm4EWoiOeKRtu0QvxzhveaX
VOlDmuXWc7DBnZekk99D7gg9i4DYTDNEHqKzHMsjGwuQ/FxI8ml8/cXKIDGptRBY8v8kTVMITRlW
mW4zAscjn1+q8PYpFuObYdtZYpdCxFG9uyWQv8tivbh8PYzStBM/49u4YuCj+WgEynrpr7UCBmpU
Gw5VoEKafMBGs0uh+bwgoIrHpEHHt12aNBgZWLi4AQJSM2bDN4R0pOcItL6z6Xn0WFjn297cfPRI
xuih9Z/ixDlLtVNrcpgwN7HoUcjfRnF+bcb8MuZyeQ4+5NSb44wOVN47wGIUKrRFReKR0p/i/KcU
JfjAD3H7pql8qJQ365+HmsTIT1n+VVHCUNZ6p2B0j7dZAoEjgMwhPGTZO5HmtDCwrzumeJKXlEmu
8a95vtPdpYFQxlENRkvMxYpl+GWDw9N/0UOTiQ4d/+hIGXGm/v3z4e2IseDlEmc0mTTkNcwzMS8b
VBcGFoKw5HqEijISojUy6+JR9HOiKMCrl+TfFoW54k7+BMFe4lg8Ut4qGpg7J8NWRqYYCpTsaVI1
/wWwnWymh2DnsYizDSfm3zqpaqyDfoI+ly2T968cz/mJiQXcCIPeX2iJF6oYn76FqfYLI1XFee8R
0zepiOnVaUxeQuk4ax7oUfeGW5BDyRveS8ZSWhZLR/7Cvv/F41z+3at56qoT6RwABzJmMac3+nkH
+SvOeK4HmuKZ3hHvxa6Mz+MAYQdWikp1ujKFOip10tsjvQqn7iiQ4d5PCMs6QOoDo0aiu745E2N7
uA6rlpc7si/XbKtuhX0+Td8MlxMMOJaisCsLveFhj7P34Ct2mdHLvJku/6v3Kgp7/tDJYMnRj7Er
KE5gk7JgRkpZuJrFn2pKzUc6pTHAmU3mH+CQjVuP1u9vPJ8nD21RWWbQFT6HDyx9VZRXfwsx2KpG
Xm4RMm2nVhthit+v3mcVyEie9mfxJboapefYoMv46pRdCT2LrRve2QESeQyoErOiCxEOKBy/pOeI
CiZbQO8pZ9/zaUsEKJSlRGMdGo35PbrYVPAXtjHMb6pcZBj/8no7mAFTeHp6Lqsi7MKaAwvZGlmC
cXs1u7b4cmfZ/D6eirdh0v+4hddew4/L3/DPrkW7O6v+Nn0k7jf5OyZC9bP3g0UMRdXCxxGwzRNM
lDlRynrERVBUUEUFnDSq4U35didKXAUMSmnWvRMdwNLDvzZauiMVLgavndof548Ry+B8zUIGZWmt
tEzipKty6gI9AyfFmN9bg15D0tqrsJhyZIiRr+wP7gHL4TcDF51QYQHTrWJOGCeTr3dLW0rZNXpe
Fyn4bedohbcgzgN34jKToyzWskmMqStkVFNX81wEXego9ABFNPrlkkD5C2fPIjXAARLJPjrL5x6h
kjUIst1s3qbzd8L1tFhqZApo7kSt9LU/zbnAgJyj9eQjxWBnaF4YqNyypy5wGG+EobJcX7O2zp7Y
vBJKgk82kFlVXEZtsdfqNDXo/XL3DRbE0n9ANe5u17mkc7BP6nqO7hAQDvkpW1KGp0PprhbLb1ll
eRPBkKgJF6SArC6sh1TAqLDHYHRQ6hYElHhG9RwsZvtp9Xw8v6u0HMy0umzjO4y73st0lGwRrQtb
oiBp1WlJ+kBwGiPQJQOWPuCrfbW9gqhZqgWXNZdpOGvseXD7e1gPe4Qxkr39Dh5BbUpw5uK9fB0D
SBIZrOBA0YyQPpRQE016/Bh8BJsupRXfbc8vDyPWRxKmF84Y+RLWcP0sCwbPaqtIWCteOjoJQjGC
7AidHZjO5WhrWfMJ6VtHWzxAdI9GXeAn8q131K2HnAu+0o0ksycHR74XYYyYNWSlDs3/tJnzgxxL
V/XIXWNpjD79qj1IeHHNHfhIXgNQJW2IAPMoshEO1BcKcUKO2ucDhbzHJ9DQ6WXzTcHU00Wkht3N
hVGt0djjUYtzSmcLkL1kYO7BWda5psrLenyDZVU3h/qBXIFUHTIwV3ZaqVcqBukK3MGSQFhAiifl
oaLRvpXUrfbDrCcdQNQ9j2fNKhdkPsvfNtUN4QTrQlywORMfWnfc+g4LsaXmHtezWa95veRrZgyD
lRMustp4CosI4c1Qsw1yVsC2swl+IuAc7iwnzPfLorEPFLNrlVHeYjzrc0SjilgQgXjPxAClP7yQ
GzpLV65e7MrR73gjdipifbSB8BWNMjCvdvJEUs2edbIY/435mKACtN6uuCIykpBjhZpmsy8JNV8u
t+LJeS4mzpzdr5ef7ms6wpW+nzsaRYf/VV3EGXBjzh4RPJ+zGN0QJSdd+x+icVrDLABVE+icqc7V
21S/O9scYB3Gd7gM7nN4Sg7tme9nUa8y6tEd5R2OmAWt35Ihpzw0fbTVLSMaO0OWBsVH3+ZQzcV4
jcKVI0E+VrvoV9dhwU43R2hZzGROXBvUv8XcEM2uwNOCucMrJorxAFiIkfsUIzAIgvam5zsm0/B4
/4z7cIf/lRsZOWwXvf8HG9IFFjBSlXBMFVXieCEmadLahgBneKEwmuogvXlCG5wlLeaV2bMMxnDm
cF0ENcm7YWAq36u5+uUEMrDWX1hDZbaVZlZ6s22/Y6O7Fe2KVgXpros/Z5TbCDAt3xY77x7n+53w
VgCCBRKOSdZxLnaG65dfdzpHmMWp/NAtDzMos953V62cOHWZZxUejdh61XfCo1FDPktYNF3wKs7C
rXCJfSOqJvdHu+je0J4nEuWG4/ED6xpTNcUd8RfQrvxNuhEsb2i/V30N0VCDK8JzT6FS169gB7qh
b2G8NCaOgtnHAZ73wMzZ8Ecv2VMBp8dMbp6FgSFhVIFAZseTsO1ZCQHGeU8ae2WpmCbQo38kXED3
YJ+WMqP3uopeiApnza0Xcmzo7bNA5UgN/Ab0+N+KAvdbouqIQiCvCPb8HR8HLdz4ZwtXOVR7pgVJ
+HD48lz/M+XdiGKPMgGDYL5j1dEtZDpit965A1HbB72NUhTty5XtIBkYW3tgmdNfAe+Ez4k48nuU
1kV+0CJK//1oqv5aIxrfOSzmdT2L+8FhMzMTtWU6lqmRlVDeJh4N6ZarAVgO5e5BuTHI9YYxr7k4
eaa+f8mfMRnHJ22jJXGKNvyYj0FSBDwk/2xBex13f9MFVz6MCzbk20q/4R76rNxCCL0sOnKn//nX
SfrnMdjJu3dv7scTb/D4eU74zLliqFtIEZuDpSGZQMzItapEFJHBpbckXDj135HRxNCqsVXkjAoN
70kAXbZFX1YRohIL4deBb4esXPr734X9ZWz8WXidymq8MbbRNGJ3vwOPgbMEBXl3nMvoTiTI34No
qfJIZv2bu/7MtqaG55g6AkkYBCm1ZCmwe6SgLMKupy6157m0rv3UBO0xsNdYXO93aveE77TkvK09
9wYSwwxYGa8GXD1re9GsegaHqDNSmFqOTUCNInsn2iVQnP3XeeqHFMwPsAriPSCk0wGqSSKtAIt2
Au6NWib4oMz3f+Ezk0SPrUBhhi42ejvFkjPXZpSgkNJVxcJYBG4qz96ATcre84XAQgRvw24+9N7Z
FiHes+/d691Tqne1y2El/TiQhY+aA/GcL3liVrLzUZN2++UNJKauPhgpIZ0TMDMETptL19SUDTVh
sRu3ZQzc7N6AXIQTU4qY3rA/HAiGtIcCYcD/cCDrvHV6/JhGfJuv4o3nli/Mg2aGmscBZDfsS9oG
ZH5cYzSCtOTdFsLzdspHZ3IWYfhd6hQQPh1PJNko9h/ZHPubbEbB8NFDE12u9ScsUgMU9PMjHxg4
lCWcr140op1tRtZTe/oiDXLrCKaUR/2ADdESNODT38/ShWdqxXbEKE7xpPzHaZOGcbb79/cawlJt
64RFPQLm2AeNKpTkbSLesU+BIOrbN5nlim3gaZMzFx5HLXrvKOjXkRLEMUUx4OJJSGpw6cu3xkNm
rJbu7liQuGlWiXaCPzwwEfWTWGg1a7CsHwuLEurTOfDNaAf7L22iX10Hn/FzSTHZL/ZLtD4HAQ79
3c/c4h6UTOT3JmhoJhTJZYobKwD7CSxm+ZIsQXXamrrkoLw+qqXEnisfz4qDv4dXrSxzLboJW6cn
U70/de6n8NtgT00AqS8aK71+yJQ5HaRbOm6tz4DWMdNd+IpDV03B/0DxHmNz/7MPvpwIN0Zw9qyx
hUN8t8JXekQVbES6zO/QD+U0EbhxTgB9mA12ur936zsrnUM5VdwJLIyPkg4SiYHvlb5bG+vtGTx/
iYKiVBggI377bEkkWN75O7BKWMZq3edcv9ZIzSI3KM+xwi1deVqWJbB1L4Pr0D5prEs9p5Ewh6EN
0liBfa0Uqb8OvGZMrkkQOSFuP1kf+UuxAmKWC7bXjK0Ik6MY4VAzoKn/zVA++jIoDEKqSy4ZH4i9
8WCDwTbJiJPVY7KainNGluadzKr86nzreJgP3KaGTsMgXcn6aHBIBt5huW/kYdscr6jsxX+0FxSh
K8CvrgtcSxAhx+fUSbMm70ZSjyxzK66gdljbYnrpxmXq1YCz9BXHadOHsL9f4xbo1/uC2nOKUCXG
EV/rS3DfAh0VbeDsOQoAeCVyqFANE/4KrVsQdklAucBa3xLBvbTTzbySF/HCWRboxwP15PkFX4n/
To8A9KYk5vgSkRInvaCdyfg+QenDsh4wMYsVfNyrCGlpt/eeSSGe7X8xew7nlHcFWdoxmVu+0tso
z6jRTbLdeKBT/K/laPN0tBwUHIUQfjc0LNkzLqUwfUnG6doo0gOcVvUArijNVqIPhKlYkWzJWb6y
muyh6Kv7ERk+OM9fMdvIU5RYXRTYGLwg8m3iEiW0rXmUI6CRib3BCFhmt1wDjVQwn1yf6EanWT6j
Lb7ZuyAry1YQksmEyT+SI1+e3ivXef/dio8XGVUrvjPU+WDCp8mqRlUyyAoQ5pFf7wTzi2VuW6Rw
ZkUKpkSxaoDCmgcoL8w6WfeYGft4jbhGTl/B944cXs2jHcru85bDPkyTSALKFKlWcIK9BXX4fQnq
5z5vCayKLQooxlFqLiHdkJDt6rl3EaEFfx7glbiquC1/k5kLJZE1mEoYuNTqgq/UiyvZeJqMXjnS
N1W/Q745HFynkduelraixfCzIylo4lpSePZbob6va1Cydgo+/LfJJr18zPFmvqpXp9LMVJ7nZROS
tS6szJiJh7Vwh6l89kAsml66t0JvhOKYmwKMg3vq+HWi0LeYCs/Khjs+tLKs/v+rFVEXZ6/MUtI1
zg3Tc6d1ak1X6VKmRvh8gfjQm1iMdCaKjI+LhHbjyVbsm/k6viXjBO+t8rIzVqeutjIySTNM5qOe
+nqn6m4YweP4KAKBbeZGAey88ZuF1GxhgDnduXniSqAz9gRjRpI7DFnDt5ndv0AVpZ62zRyNGXy3
fawiLh+hzHjWdjFctHs+urucUbN1l+k+dh1l095FC8Wl93eGa/HDI4wBxS3Lc4JvC/px2I09PHP2
87AOaLSWl1W4D/A6PK+MTB6eDU4vekSq5tcod+DtDKnuq62h+NJkcKUhE+1lRhQvmG0n3vTigO11
iOIpYMlaOI7/okW7Kw0W7NP7GfSeJkgx9NoCvu9xTMvSTJXFKmrXZtQvbGChhzMfC892Ats0c4RH
eO4/G70dNYsprfxpFD9vleeHiNZFx7kCrHv3uVRQhARJz/CP8nDA1YNt0CmYh2GIei9iJlcMwiN4
gMZK2Ywrf4oHFZEIDs7AQmXxXAaSIRS6e/5b8PpwOhuxLdLll0/c4MkAfUM/iqOpu9Ksvxuhmofe
5Y2TfUJTRErRrZ44sqQeQUmbSNyZKLWTBkiVEWaWWC80t2k5VBjLX6MuKIfp9uAQRlF661bPTZO0
FKGhS1gEevqM7e20ldUOrxVRmNqN9h6hwDB/sj8iqvjuXSWghvBKHz/eePHa0vx8DrhWRf4ylAhz
KfaMlFlPgJdhAgjA5fTmpvWfkVA09S292wsJe5kd3Srn9X+S/RIft5ITfzMj47HQPyiFXE32Wr6A
8VAQsnstwtieA9mLy8aqAzoMPrJLQ6P2wcaveLOBJ4vzCXQtql0N/tN/6BBiOnrQuN/tUnzQc0fQ
Pxrs2f/nqXx6lCAua8MYhSEs4VOPF+/UGWVEAL3aZ6fuMI6faHOwnWN5diQYlUmuXJd9CNkpRxlo
7EfHV5FYU0/QfXvLGCii0BfMj3CJroTSgGQ5XpqH3wZitOV+wSMMWGxytNkjq8bB5KxJwjrGKJ06
Y9sUG5tqFJa5gPSo3VTEZFLSJIJ7z8r2DV5U0vKriL4kZKbDq+HaEjya8Vh/6GBKZV7Hqo1WoWSC
QQYQz7nJu6Hjool5OOyyKG893McLeIXnEfKv1yfR1/nMgK+pCMaxlks5bVjzXuRgPSmNuNQUxL0M
2ctlwwcibsbwDdCOR1s5YWl+bTuATd1aDV1zbdDya1XvrSgFT2ZWWgTYB95dzBpY4VVKS8kipDSr
4QolTHidusGjh7+6HfBd86NF05k0HTqQ2UA1KLVJCIRsE5SDCB+jj2tfYR9WFAgeSQeSvv2K3tuu
mnSEow9Vx2dbeXbQ7/PN043+VGHpkwDYYbMOZthXM3cUDdImmfFuJ4L3jmiWM9nIji+i+APt1Ajb
Ys0LuVhMjrr9JrnLdwBQmPVdovt8TlpX6nCRORAq5pgRnVbTPqygg4QkQ8X7cPcKDq0J87+MFIX5
ZfhKbU/qi3CJKx7ZPfNEXHKZHCQc3SNO38ERG0xPZ/nk3hl1Wiqtkr57ijDpKjhJCagjrtTyPczy
85cbKT+MGs3+A3c92LxYrDFK0/ZsizCatLjzWewALNRmTkFE1blj5DXtONXqgVIlncLuvzzh54oG
5WljbwxsZs9xk2oIvg595ZcE5wBUdR9+TgiSRlTT57bzA8mn6wN4NVEr5GVShOH6KX1eqjnr0U8o
gw2AIRbUn19GTaJQEnOo3UC4YzINlKDLcbYn2sBxXTJx4M8IJVPSR9ORB9nYZkZLPnMuyq3XE5G1
Qd3GEceft7EXhf42TAFjYtBcn9mqKRuc5TS/Wtuu7OtsYAeoxMno6GUBTDpX2eDab+eAuGU/AsiY
PAs2fiOBpcDnUeRCbUEjMwsbi59ABPSxD6hjL1T1W0mug+MId7A2GGjowAZT4NoTOZealoyZ7Rwy
4LDs7WFuno7obr/MuaUcwV3Jv7oBcqS9yo5QiNfB5ehMX0G3Vt5Wi5pvZ6k/w55cKSOSRd4HTDWP
CJqB0OVWhhwVHtW5NqFuN8mKtShs3C04e0Mj6wNXkx0UlRQff87xAf9S4OcEP6v/614bCzYqNvKl
TX3CFS9a8T/kiSYyicUOfOwnwnCvIYgtYJqE5T4uFnT3GCh5jbNy07zjkbruXkWFmFFUw1P3vTQx
s1W+c6dOFuEsmnDV48qTu/fJrKom66KxDpqA+x9wX8OgiGTb6sxlPlviy+pWUyU4hfMduoH7LLyA
9Sq4iylXY6ZHVSBhyVdbKcCmrGyDAfl5KmTMD2rzjwRVwQgAvF1ZRHijAE4/sZkztYnJAGjvfX+O
2RZTIXf5FAh9OFdjqSvq8FbJ9qURhMUylYjXhUQKb6uIiBs3ZzTBGLXrsRCk76bx2BQC8lpAugWD
Zfpx3t3gLjBi42xX8dl84PLvb32QkPyPNW6T5A2oek5GwtPvM1VxlN0xyee3wmwLah3nQU9LkLwl
/R7ywsFKlP6m9TghIutvQNmRCwn9bJAWcJeDBknNYQF0Vn5EzQQC+wj1S5i+qKGkSZzMhuBz+WQ+
SRV/P8nJydi9XvFSx6DzNGJAq+gHFLbeGDkZUwb61FCZ4R07Q2+xU77q6Gj4LD1QJ0b7KHkKlST/
tmZL0QS2v6M9m5jF41HRGxUxYU74uDXlOKpweHMqATWYpsINfx/TfbPQdH/54Gwl+U75WHsTCQuu
weJdN0LXRu8Ym5mVMfK7uwLfyeyb6XbzjtGn41rp7K2TtTA9UtuC8KdGfzZJbsLuhsuTOtuPBP6X
/CJIqpHg3nVAEgIfMUXMhUPmxp34076M2SraNOyOpiMj4AzZmGGtEmcpaWSYoRvIuGivpeH+XCp0
E4DdjuoJOcJwSIv+fKx6FIH2a0yj0/ARpHjtd6QfK+WfLhhxBccwDeB5ZjX91fYEaJiFpJklEQRm
erbM8qBp9R/yR7nhxS/liqvx/JiIbCbROjYKvgmZuYj2Vsy4qJav6dgkPf82onCki+1f5sLjNWnM
WnfgI8k8SoeMzOSHxjp4fwtm6uOlfjZ9+j+7T+2vJq5+eGycDXZtJyhbTa8sExgNrA37cxONX4dt
zP6P9ygtWjdxaFYkTaJdPtJ2SP2BLc/1J/bKBQB06VD2aUGpqYee+z7ZozySyY9/krQV7rkzpXzB
OKFnr0vv3pgFIpY6Qf9WmvS4T08sez8etFRcZEusGxeIWVSRGFHEFafYkCsIJ6Qs5snNBXyOqL/l
E3rzb2RRIIprRCmx0VOiYiRFMRjq5WWLHA0cnK8OwhNwuG8fHkQt29maGO5RoX/bMJbnWR4XWRgN
vJvIKIy7d5nkqxn+iYWzf7/W81G6Fz3YoyAULWo7wtVWjg8FAv2hWmWoLOGtoQIQeYlyPzLdYXia
pnriRMGPqgJqlKs+30ZwC4NHBm4ZN7a1YKAJvJ4LW729XHjSavKhlSnDPyN2NrEhPjZYon25kvrT
Y9UIiEKJA0G9OUHu0laIcInE3sk02GfR4G7SHiz5E+LFTPvgPsGtnBel4C/BjXfmJCCFWHi0pZ0/
Ez+EcA6M+TK7ETeyVIcHScIZIeavSbZ+cpQT7fMMV5y+Q8PtkFqjGaXiLciFcQ21hB53JX8T9/GQ
1QkSsensGJbT5ozCb4Fu37yVWj6aRvu+UTFTREDL2CfrYkIHAaIXvLEPWLTNNWRdXZXwwDl6gy6F
LnuC5/ktC15TSDKOye0AxlGFiQ0gYPr6xR2Vf4w0o9QHNw6M5tr/qYo1nJQfJhcf4x9BgGYgORrU
DrCOreBkjE0i3to8SFEfZXIhSqOX643x5BieSdpc0AjSRIonhMGlWZs0ZDikvcfgiq8otT0W9K7+
M4G5x1HgmGK6yJUjp7LHeEoAKv2KldX5rrLxq7lfLYowoQfWobdjkLDY76XxltzM96FkCJgcLb3j
oVlSt2P0ONK6kMItiCR3ksotybMRIBndgikyZ23QZ6clDK/sRQdYM2PaZsKAYA2sP3ySJhNPc/9v
ingmy9sx91o1MWE3EoYHlS4NT3UXu07I5JWQYd7N1Epea60eUnDonFDDSATlxx1rjEPa+sQD4yfs
YebhNA28cQSbhdMSLlYJP1+uaUxAhxbMPe36dxdcMq3eM6RoXdaGxOVZogOq3JZ8IsjSAPsE1yzS
GZ0wj9+uxpA0o5PUB4p6qTjo5LR6oe1SJCSwVsB+FpIJ6JjA3CDEw4SHVv+zcND7LhufDi2gSJAq
S2dc9vZr2i2Mi9oVkZCcA59SL0vDEmvz5NVk6mATmnvL2sZPM0/WMBGKtcO4PsryJeuU23KFQ+6M
87aVZztvvRPOBvW1M1zok8Z8SA4xsYiHQxc3GCph06k66YqsIlyZLp6EhWEdiOGhskSzrnnhbMzP
37tZq+2dk9sa+22w1Ux/8ACVwjVw4vksk++NXTc5jvd4CMqG4PAjTc3EMQ3dUZQmhvghnl5mA9x5
ciRA0ZUGAtE7wfqrN4LuFzeO6xggKn/y0gMsOie0a5e7xV8MvyelzNsEFc9SBVffBEXVnLm/dHIJ
YvDIMYizELR6K8YEit8jzJB21OykWbEh4zRF2YqpjCNkPDPl6SNIofta0CdRJFqqbPMC0g9zhkJi
W8EZyu8IcY8wkG6c4GvBSv9dw9BTYV7DOMX+MxuBkwApyOPg0NUPY8xqnEA5ziSeFmmjiy8iGfM+
KQgNmjy4SHdKgfO0QwrtDWX7/HONjHtfflGa5qqrH1HZ8UBIIrLL9p6lBFAZCU0KCX76kjnUQh5t
6d1QU/1ccLICMjJDj3ugiU/zAhvmrYFfKGJ8ugIN1pTXgiCHZusVE/Se2H/N1jRz6T4SuRbIbcwn
CEvEczGm0fKRt8GHRjhLDTRVGPMYgU0c9TeJPvDndc/KvGtpfUZ/rM1fSItENlyEePlCoXYTUZoj
nfq+oa5J/C2BPQmXIrdSDeQEYHMIZKQWwLaICSA0/1c2nCdm8VXF8ZxjXqm6RjsrhKGDi8+XdFOl
6Zd8Avf50UN6byI53cxoJJ0yVtCsmowhKU4R+niYRvykYKLu/T62UIzru2onMNWUaOIXfUC2W96w
RRNw7azrRYMYfpzHjrUtL97rhWcscKAMoG+R9KQyT7xggLxed7xqAYif+W9p4zwyHhnxM4T9a7hP
qz7YVPHBFQ54ilauJjhbJZctLh+IsZSwqqQx9tc0HRIt3OTAOD9QNmggnfDKZBv0DcVDahNzRRqF
0/xVwXxrtpoJUSx5bXM+2Em4w/BRwZ5pmzNt3989tkNEI1MUO34tsP2GX2CM/vg8E1wM2q45niJJ
quDKwyVHgM8AdDCSFr3bee4208GRPPBk3vyemgqKnJghmeEuEJiPk0ueANVymxJ5utOxv8t4cYol
cx26SVwg8f+Jxprr8A/LPud6oPY5bNjQpSFqe/6kqKlv2u0+y8pFbja7h4hPCVOW1pqFVkGvq0cE
HL0ONHCS2c65y+3qhmwzk9f/Lcg2GA9sl+NnbURq3xYz+ZgFsbs4MipEINgK9sCQpgMNVJYl0lFY
FHosyoMuMybS8RkgqeifirLZ2PyqldBbiJFFeVjnz64Z+vh38Ip6Y8CTczkyQpMfquNiu/4XlCGC
hXF1KUPuvuY+Yr1Nl+AxVEeZezr/GcLbrpqMroB5pK9Ejv3QMUJBKt1l8kfT51zgTUzzezucgjsG
SFVt2kmwF1h8Sr6tb9ajfGf7bXEx7ZwIrZpVbN4aziJesRCTlF+Lb7a54TSKW1s9J3aK/kVnaPVx
OWChLxgy9hJ/j1pu5GcvAMsEmsuqH27oHHhRB53wfwDi7/wTQzExrnZH2+dNZIngmSURmIlczZCc
eqDsHIGxI6PLdP3fA1hylIxtK3cdx0XzB+BkjqDtsMMVFMAiNA1N/84zRy75SYVrxXzoa9KwkXrQ
UnaKvFA8dO7WXULRuR7nq4/0q53yK9zheCL2oKZ6BLDuo9GOeOIAf/Fr8rfRLn5buxGz1+s/hOZL
CUopqj21O8t2Cq/F2LI8+TZGO4oLOzJq1s2SinIju2RJMdiEDDG6mKuBgPSKQYkmvQhx6MiC8CdV
fsomk52O52mrzQ1YLgyebt15ElFlRTJK52IOdBkNKdFHDNIlu+/krs7sn12M530k+UTjDXftDyly
08izQrs2xgTV4OUtxmx5OeY6cnyMTurj7Mveiy3EzRm6nGKdzZ78ENBFHHdtx4PBoPNdBCu1JOJv
/CUWAKpOxYhsDfhK4R6EWH344sYSJvCvSvemABUw6rJCWy2gQyKKBQZLczks7sexRSlBMIHDThMi
VAatzRA6Hwz2yhwKklmulX2E/rCwP6O6WSzyStCalepEZEsSIPjMlZAM354MupdWuD+BcU/9k8Ro
axprf1+pBLppwH/zFileHduXXZvWmWftmNBApNJvtb4/CagUxqSzOBHrr1PQvhg7JNDwn20y1FRr
rE4U+7MJLrh9FfcbzQN3cmPLmsVdm0JwAvJdbuxmi/YwUCdfjGHs/IHfDCqkah4RoE4X0413u2ZA
gBZFO1sUlAMG2KMaiER0XY74HLcHAV9Sm2EXGZc8dbIjodzoSEsF6CiW7XMy1FzeJWCGx5GA5Hn/
yU9KUBM3I80/3rj1gk0GBVsvTQR83yVWi+Ha9CwTMpjfMZ+nANXlU9tBpUM2yREiD0OEaskutNuq
CdRZFEEbCiN1H4xQ61H1g7/6lhQQ+risasFrfZRMNpsSk8ySGPFX+USguiQ2ZOsoW2VXtvOt5c0f
fkq0nxHw/wo3Bqg5TsiQyVJokbKmBFcFQ83HxNRZ5auK4SEqeQHmWIIca7zkUjDoGG7L71rC++4p
jf+Pi40bhbOY0kl6sWqb9UQmxj/05qtAaeNKS2ikkqWzVu3qFzMhjEBDBeeUCflyz4wC6USROwYd
brxnBPvwYtoLpAnJ/UfEqb1w2ZuVd3MIPhX1ngl/6OSRJkaYBOlKoZMVlV+m0UIpwZSXoWlzV0vu
wb2LQ3ZX6a51w4iYFPC+a6Aw22v9CpyRHh0xA4ic0uesybJJ8WjYHjrrIoCJ7hKqlvou6chR/83l
7mgOywvwBym66nWkyRCuQ1+rnXixl0zqPP4Bp7xkKgUw0uvjbmsCNsKNS/QWOVWidAxQZd2feVbJ
sXrHFxJIzEGJyYmErUFUtM2DaDojACiOThbs66ZY9+WFrO/7PykzToEMPtoDQbnn+kMcmt7gyNhd
mTmB699TlCgrqpBM7Lkfn/TNqzhqrE33xleTXQHjkcTR12tDPLQpDD0xkv0S6U/qwuM3UedQSy5C
mQ+8LpuUZUprkR/ksf94c7e8ARO7zLY+VrTAvwb60LeDgPBrLsdzE6YhqKbtCQTSVKCCjE2nrH0c
cWbe7PSm1pn1CmfctmCFeeVqOzVsKA1jwRSxiefx05Z79jaewAsM++sfbj4ORou+8cEp0BQ3uy3E
JWQMfeIgGAm7Qhh6kqKxTEEQE99IN26SOXFqdJQeAxocQidkSRTBr61xSDIPCSSgry7NfsG66WIf
r9PaDf/QUmxdfMeCrqI4vs8ZyZbzuytg/OEHYjiulYd+N6ivJ/ul7q556taiEL1zGSDcxbHs85xx
16yTjHBBOIN/XmDZlja57199/u9Ut6h3A/JnSSw/W5FojAJPTQZgiapgeBIhl5MwMYYPlRFio205
Z+4S4FJcj3F6d3AV+diIsnTchuggIY+O8vn8V6slKAyRXPJgtSRO1bm6DDOR1oSz61BPxR1PmeBW
dK9W1EM2cVcReeB3dhqhBP8uzeD7nMl5oGtzdBQjSsv6ehtACnbPtgDT7hO7qUSjwhQLGn6111Kt
Q82TGuvoUc1n4oxYBSZTCBB2TdxewNKKpPgiTRR1+9eLDMEZ1SdiyTGCtniA6aY+BmNsaf+p/XpQ
gCm1QtRHjj7R7lB+cOPKfqVDvkuBbeBXL0w0kCA24FUTG32DW4BVCrBxgGvDIAqYaekTd9qT1ulT
K2k78L2s5mKQLujg0yIgZDXeQ5FrZmNNkWOWk4PZv+rnyovwuQ7gghs5CI/42mZOkPWHE1R7Wcb2
S3U2JCfzPj5666hiopslU/l707ildaSZycWWOKOAMbQEmHlRPHFSaOf/k0vvOawXtMpjZQvi5aa+
vzMwVahA5ug1URx0fDF7YB1S9cjIyKmhySXdzV6QdaGp7TKR6pz7bqzCGS7YjJzKy2v1nE1Zwp2X
vFGgRW5fQIP08iE4olRpS5T8rokFdXbmlP+10+0ljtdFHPTnDd2ds8YPOSdkm4NbQGpsTxZl6r3Q
hxmq/3DUPB+Gjq8Uf1lzUT4Z6whbxrcSzjx0zIuFJw8PJ1lAmxiXEzUIi5inVCJ2w0+xyi+ocEhc
ykgsmDLxG9MmRe3Ma/8GHEWedDrku8WNiX3LDRSuXykErA/4Oz8JZB6tiwcSTNpiT3geg2pOmdG+
mcJy25nT6a4AEkMlUeUJoHzGndWYF44kVcybO+y7i6rI/yP+2ze9Kx8wOA9E2edB16TtgbIEGhjU
DFFMithb31DzCnx0SRGSxsK/kur2+W+gRka4xV74zNPovPVu9+HlzfHwULsd9/uWXHq/JwcZvpjd
2Q+1u7z6eMiPFsL8rWmo5s8B694zIhq82EdY210xdfbFCWtczicwiYRVikECNryvjolpLVWt/18+
KFlPTDFHoKLEepJ6HnGOPFowd2GXaS7EV9hMhY+r1yW/1otvsF37lrN96Se9IAIgBM0W6m0YdIj5
VGCI+pFM5MHUYZl3pIr6mbJ3PP17p66nvatkwZMWS8xCf5ynEp23lFTEsaSNEHH55hiIXBcqbRaV
ugUG+dady0NVBkN2SIoLD8ocIaKIho0z1dt6gOMafqRXo2HPzOI0szjm1jDcNRYiJ+vgTt47oSpX
bKai2BpiYf7U5MRYwd8gzfmv1nOWl82GUXBmAg7kBHHSISSWMmyNdzkJZAWGJH02B3yefSW3KwU5
HVg1nzXMqDOjHOZ94Xr9wNNErBgEdznFBQzxS23QUoVECzeftswaaon7d3ASZj6OXqnNHyqEO5Ae
F7/jP8Dcjr8UOzZygS+x1qQNwJ20i+x8D3JhPbHszZAe/Zr0uHq7RgETgsstuyQwwaYeLENgIMTJ
6lWVcU3CyxCIh7d2R82WjnfMAhOcQ1tjnOfz1V4W8i9ZO2HLhrIZah+AW9OoAmYBtVj+2sRFPzdn
kEn+/SVo8c1xyZvvSZjeSkOiQCZiNqIHJalJIx7CGx8qCT+C/+vRoqPeAMpmIlJw2BS3i1pJZBPn
PsthxMOfXJyVFu8o+AVhg4en6QhXOMLAvf8xUQ/Ndd1ZUbvZaGnmIYwcjJi54KBdDq4kzY+m9vK8
CaXOaXaYQBhmkE+0kRP5wNI0uRiwE9PQVChwUuiS4Hf/5otthYkYI0gHyXJNELGmC0EO/O9qfGsw
ZqNh1D7pZ3TZz2/6PlIre7jESxKjmJFn9sCY74tAOTN6hbbw/IMnYo3ZTWLWvEA9LHLOOdw8ir6h
voOYd1iOrqe1qpoi3VlXyOCr3cw9c/G6m5DDTDlBGVpVovpTLVBvi9+DtreqDUXkZ9ejV/VG6M+x
lR5oo8EAqOEAO00sDatPkDnG+dcdxKk0p8VfEb8v7zPTKhomswcfA5QfZt2BwmtJoU5rjbs66Rn0
lKbtgiFVuk5TwP0jrZaOj2tMSiBfx37+DSnXuQhNkEumQc4xWGow0QZWxxKkm7W48JBzoRC6YOOp
6s5KXWIa0nKDlV9Ntex01yKxpZvFBaZiD53Web9/Ovr0EiPnPLW+Mw7jLgHPJRVmafc1a6k31Yo/
XOzzbzvrnEcivIMKGAwX23fe77yy0puSFQ3vbGv8f/6wB4kS7MbC4BWoz9QefO3i+AwU04kwOHFr
B5DTCxEGkkfu0HHBXb8X8C/50ip2UHRXvVG7lqXZQswFoNzbUDqiuAWzPx1jtRqbhRjhqUwb5Z8W
NlVir684aIsclRyWRaWPURM+TTVQrKwsW49xcQYwNFDil52JCIQ43lFvuXP2SQzUHeOYRZpL1/a4
BGMtyTyJBjfedYI6k9/dXF1UfR3gkXdDfkLYD8R+To3OqeojQYte+8Cvxp4bLn15eQHcPcr7u86w
EagzCvZb1ofCYA9ilOOUOvwjnUDcWoU7eFC5kJPZ+I98HDDCD6Xvp03uPBxYkUc0S07PWGB7AnY1
Gi4WhbsBlTou8JiJ8kLV0E8NuzXfh61ngH9lpixvaASYNZrGQNF01fx+1HiGpwiz1vFpjhtLyTTo
VUltQ20g/x9rwrxK2QxZo9xFjbSJ1Tz5967hARyzwXt+KQwsCE0zxDOW/CURc8REe5gDjouPEE66
7LrGDRKkktGPqxMEv1FqyFavs2AsYbLCwqHRgLR4BntzOjPbyG2fo4zFsLW/n4ETxQBvr7c/9RiD
r64ax2QNzR6ux4SAtY2GAFkDFbSTvYrcnDXpC5ro0g+P0B5Dkpyf9GR2zOm/N3tWDoAYe+hx8hS/
WnOaCSUCgoxpW9Vy7eFj03Q37ACUjSNH0IoplXb9+ypl+WpCHbDRMbHATjuudi020fLQDHtExT6A
kJkj3/7jcms3Wcwy/G1arlb1eFVSIS2TzXsCoJ3gsPZS+2GESYLUpXAiktjAq48STscbRoWuK+i9
na3uIB4n6g/BrTKS8wIw+d7guCEaR6xcUnAm7shk4TKGStm4kq3GghGNBhNTQIhdbLhEm59lAx9g
6vCZlbcocSe07RTroQgJ5oRCmLiIhW4qIJOlOIaOeSyKp9RWkOLwsRfrnNOcUTqofKqbZhR2qelf
uxTa6XmRDY/WDwn504o9Cni0yC8qEoLM01VQc50AjAkBQr+RinZUImOMIPv3mWmezW1/0c23//fH
eGiTkN/4dfEhzGFY69w2eObTzONHXvdvlq8vnCSnsqHTyk9KKMsIoWdTw/75eziucIBfTEo9Y+fg
uF9pIFNlgVurWyL4J3VWHHrmMbyIeKkslaZYd9ExJxpxNImRDx3HzhoQ6C7nefXeucP+YEeyBl+a
qyGseM7tzt3pltx2clfAwlez7dYKf9ZuaIPWuXQo72nNlgJyq1ectpTiWkUIQRmFJKD2eGUShSS6
tixu58zvlc/dKCVZiX6NQp3DvsC41YSfr0jExcyYwIbf05ZNDvwQ8rLmseTg8LQaYNV6+GKD3qs6
POtogLKMHjf8Owd0NrvcuHMzqcfShQXhNoak8JsKLIKAG/AnL3riE1rZcVGSQ+qUQ9XmQbIZDUc6
8jOTiKrKu2VI9cuT5gP6cCG1jmvaNvGuOX0UNESTiD1JsVThJJOerZv2eWUVzyF6X7CekOzBiCMr
/06qWuuibqFEHbDxhGu2i3GLpfGuY3Wkq+yzvuD90Auaa4AUuYzpSIuIIW0S5/jOacCwexM88oOX
al0bk2HeQ18SPAc2qd6S7T+Um5Y18f63yIAKLjKYHuERuVmA+rPwWb5pGtVP0vT4aE2zi8NsbnYS
7x6Nsrk+IouHTv1QHeImlfZUhuP1a7Y8Jp0IG386/qs692y4YxK10ImEsa59mdLKw2qXjVCKgfe4
lEbqn+74cPsuZUnf0Z9oaqGN4eJOo2HZjb4iqnRLHuVOXY/YVUVn38cVtjXB73fMfnr4yGyuK16i
TxNpSfH34wGQSypqxJnDdsVQ8qULSyYPm5OzxEcwiF5GUUFzRTJ7dYLW3b4ankVkK2nMxy4VBeaf
kUoJVbWfYL0pIn7PZtIdXrodFCOGOpn/dYA5W+nnqN5YoX6dDCIitxUO89vxisCXUeqel0WOIkIs
YomF8PynlpeAI9x0S1jTT3p2MAyea9y1c5c4nqTjRTlFa+kvcuXENAXcWdlBQwk+gLC4fh3kkiyj
nxIB/ihBthUiWdNsG+hMdc2OU0bYgMsF/DVddCzqRR+feYQmw10L9AejIwpNia5EHXusPsaW/fAa
rWFB0xE6RahgPBXHDoZMspGi+IfMoaAEsMXV2jW8tOtB89Y8DLk6UvGeEeH3cIwo+VUcrCjGp2GV
vLCcZhs+GU7jcusHkammlHHIayasf91eNBMG85HzqtzP7ip5Jxc25DQZ1rjs1b+czJl8qpypvIYr
f5m4p0J0fKUfM1GYGdYZAtl9dqxH+Ibtlm0DnSUDDpNe+rfXH5oMJIdw5KW+zetKp+5ynn58Bih9
vKK2umdGzVNFOd8+sN2TfYZdn/K09rLlxkUnuV1xDzyfsLGWBbarZyak/Sj1tGPk/WWqzbGpYkiK
fRmekVULTfsii8/UhrF0cjh7iJQf7o6gmNwxqA+5M4Rp/8egHZy48ckWffvtSZ4lr7tE80GTtkOm
mCJF/Ifa17L5t8jjGFmNX1Fl2ldyMY+I5gueHGHOlfZM7bIzIW3aV2KgL8auy4r1UOTmoHSklvd2
dxoSM2N6vGEmehBG9eeCA6350OkpsZCmhfVVPXDU71mfR806W+xHk14Ks8lTvrlj1NqOdz+BhT36
dZAC8pXCbrooSIzyRkxolLVSJ7oeOJKo/giyzPlkfSV2wNZHau8OMwhy4M8OSwxllB5Qr0p2vnvE
261AqEdtjuwzuk9TVGUixxD2ZtKFXr5/3YVYBs9cWG0g0Kx8sW9TuQaNIHZXJbB7DpwV0arQt0S0
KNhTrPjCry7l8+xKxT71OTAAbe33pC/9XAGZAXuTxWHLSTloAfFGZ6RUg+D7stiPNQ0Bhkih/uZi
d/eunwbccHfbxa50d1M5NNTTDycERJnPjGdFd8ra46TZ5TVXlDLJ8ofygr5jnuwXOZ/ljx3JtQiF
zL6sCADYN96Ck9j12i0REuSnI2qPh+V5e6xV+7Kjfe6BQgNEfDvOovKXVI9aTg+FE96Oiv23me+Q
eMpKWxHrudxjqCTHqwIrwxV1ELlfTLoX6uw4aNx+rDXwFyS8RQ06GyrEghOlI5qGcmm8Zt7DnjU1
ieDmU3CGWA/AnMrzZRdDaks8lT5jdTX5OVv+6Y1a1eSOrjmNYBEqBL19JC9OkQRpOrczxh2sHOhv
XuMOrxFvPZ8vR4DDFnkQUyxK+HV+7JGgpibtcBlyALzMTEt8bKyzJNJ/57uUmRN5nfKyTEFw+XRb
nBG6YlhiqDkK3MokbNwUfVkIy6WvmpfqJx7NyadtXA12KOjYBTh9S9mQzDzaXgUDqJsNj3rZTE6i
QDJ3sD0hXG0CWp0OPXsSHiN0KNtA6Am99VOcn2UYAavvjcO4w6nvNhOzDBENN+ge7/YygsnNbtIT
l5xCClDOCw4f7hfY8G6JqZqhihjQ/vvPrzglp1iAKE3cTv63oFE1obYoDPy+5pLOQbbtn3hnNUVj
MjCE1U2D8pinRYzO+cf70GrMZ8VJcmNgVgzvbgDwMPjnSLp17vPU7dxGSx90vHW3Y4Rz6WQAxYqQ
4+QDfLTf/2ovRaBRdlFyv7TQVNTmHNcabcF4/jBQuBaLtPTL7h3MaaK9OBc7lSBKzB6Tvz08UiWc
nWOkS2Xzcg/b9/JxFli/5/kIfe3nix9GaAC/vucDI72TB5lCZY7LTX042kuPQrlRQnyn7ewcR0Lr
xlGOnx29HDWc7l2RZ5kOAfKyY2SK9GjSiDk688GsWfkddDuBe14xTmiO/r52rCZh28DkA3p+0FEh
PnDi+yMhZv8wQyDcKpntjVi7rJ3TVegWotNJjJrpzjTbdet48+sM4qp47+6aSJWANcOcpfI4DPus
JtY6XpXXDymqXD6wv5F0iNBcoNsLCTFwkgukuJlk5OgdbbTsECZC3jcMia8u7pgWajPj8CbvwlTd
4rNanSWiHZYz3pyJSUv519oJatvH3NTUjjYAGIVKuM84AHjWbnxQSmK0raGt57/pcDxMN435yDOb
vnwM7HCcizO9zA0q/Xd5Sy19en60w60s0vrdoJyuU1c+mOD6vuB8aaeSdihuodJTZCYbteXkL/6r
+GRO2XphJsJchVOxMaeH+ghSPYyJcolhuceJxG6o117ydtuc/OAklRHFrbgKdBJnZ6zOJPhzxuRs
0Nx/Hcx/s/8V2+6ghx3PPM7R/t535tkecTIjmyzeXgmNL4MT5aMyBh1KOnzcIixi0gumP9Uccm57
l2LlfMLrAtH4cPHLvAa11+L3RqXc0FS50fHlrLVVrARDCRo0j6Zsx3RIYvV3HrKZ8dtuDhA7rpoS
dbqeBQizCSlJ+LDgghlSAjY7qyeEBzwS+MZe7nceL8Ca7ntLRNZSu6CvSbiDIMo158lQSsfb3ZY3
TTwzjc/Gr5i24w6CwaP3q9vhRItyn9MLZIWo/GmqKkssLR8yOUzppQyY4XXIIJXbi+jtTvsTULFL
FjdCIWXLeilNBBkjLTUWYYFJ3yPEnr/+mZqIOtXTnhsSXgyYfLmkm0mTEbMoVb4vfa+18avoOnPR
WqFKjLOribKlSOaykwCa6FQ0GM0Fd/7ez07opyg2U9ch6XuQ8Pg48TXbqqI2ZH5UjULUy1hIjRl7
NWwimMpwodfFNtP3NwJffJPx8L7eEHWNLT8+9Y03feskd26JRsxeX0kHhvEsotv/ZbLuSeAlfDWY
nXM+4n7KHXFVugSioqXctmJqjgdUjqAzXUhrF/AQWhDYSFSxY7SNno4ZlL26gFnXJpncZc6deGRy
RBNx7AfRay7nOLAiNEJwK1FnkVk4VdbXdFwbWU7gldwpjwRUIHE+9HdegBosCZCsWJ43Hic9qn+V
YVYWNyr9L336gAxgTsz3CW8mYKCv0Cm7xsymmxcEvF7byBUnHco4TWJqr6LlEWRDwy6oFoJvo/19
+R9lfi7mfhbg2fpRnNZaHPiu63/n9AVminXziqdHRSpvugeX3wYX+aifPyfq5K8kVmXVq2hdW6A4
fAcV2J56nPw+Gsar9pYPAYLvJJ0M1GtVGs7VfA7kNuPMC73zasZFXfLZDqXq8fyNRVOXAtuHj3b8
xbkW3abUa2kDRXUtOrR49a1ITDBwmYaCDOo2l93N9ZIR/iOtq5kj1QKDcStj7WSE6XwG9Sab2tn5
4xQZd47v9EcGw7g54+/jVLpusjtqJ2WAZn0t5QdwVe3EgnSRQdaUkzMjA3w55toN10UHmmv0sR1d
mpc1N0oVXNZoDp584Aei7GDoLia/vGxaOLDCPWTOfbHD3TuaMnWxw4Hu2um+K1yk7zbolBX2oISj
4J9Q0Hxab1yL3rC1rUbLvqZ16/fIX27PDH+54AWS53H3xMEpZfW08FcoZluoP85KkcW1ZvQYH52R
QJwUghNRYslMKHipwa1EzJSHjeJ71qVz6QtWepikBHAGtnS+2urvcH+xoR6lnwjSh/wUyaqgATXz
dykJ+MAQZIV7x3/4v+j34oZwJDwSYcjMy3ntw7zjMXtq1UTAtM71DDYhmOO+395CBX2ZIaWDKFtr
JiS4dMv2GSwDoev8zT7qVn0EikM8CRXz7z9JFVaxqpIQ1Ibsr+TWr22AG+KnRYx3HuMFBy8jphNI
+/Tnnk9oZIL/uN/GsdvL/mJq2aSzFgIT9V8ZlyXfJlTaDUbvItjnGtufkpaYYGduDClOZZ8xcI1B
1MTpee9NjFDNXKM4E2pVAhoTMZG/gZIWozfRMeERveweO7oZFJ7waBsLiIRucenjN/xaBwsCYMEM
iEUVCgG5ltSYPx/BBXdrwn33clsPiWwW2i3M3tw/EtjsMfR28V30Po+kRKla7hbBvrijMl5gLcMH
KC04H8p6EZ+noDhksy16RnPCeka/73kwTTcgiENdlCHDJMNgs26GGedMzIlDyPI15c5I2q/GpfSJ
4DahhgX8lEur0BLwA1dZTay9f8Pu1U+8M2MoFCbfmAe0EBCq0D49BX/Q9Cqxt4jiI1jFGdSAL9rY
3DM0Pt/S4Jy8+3RdRXG4SJU6JJkhby1nDimyzrJ6UzWNlvmI5uZLMTaLRV2Sei5i4I6H6aUhrpZp
TBo9NJB/T4VdH+SxegxL08KltUF2BDDzZAp3SEv5n/84YZePQvafXikgQlIFcDt27EGr4UGguRsR
JwNP17HZjwHs5iZfLggDivaq3vopH5B3Gx2j4hUISeFhotOD42jvcyMFkWjTc8ij0UxFL3IPbiIv
gRQ7wS4aJyNNgd+paazwvby6jcUFRgSTaY0fNiuCVzLI6lq7/Vmxx9OpVykXfzblU+HuYRyOydkF
BOw3bjvyLFK0kG1CrNZl3eeT6svWuGKnc9xiz3h4Z/BqbDJYpqDe/W0P8WUIUBxdKZqI1Z72QeVk
5LkX+ElPva4oyDYdMqUsfu3vDfzMpLwGOCTAXbwZoQMUBo1iR93ZTqBYYDglx1yvH1laQoxdof6d
LWdyLCWjFi1zjX60sW514BEcTclNEANMtttd3y6UUaIZGGGk4darJFZlTuWTDwOtZ+u6lLAUPYLA
Q5uNjMzb/mFeH3Sm1GPY2bJgg7S9viYuk/sqP8o1Stc1BCSzUVzJgRj3BJFdIK2kMYY0R+nLNTr5
o1OH5n2i99YnXcZ6L7dD9SFZJ7i4fvHfkqYLCyroPr8L5L6OFiae00bEVWC5sb4pECRi6FDhjGVK
H9F6FLRuRYdGvUtyBnaxVAv0hq8gpxg+wyd30hD+5T1++nDEruwKtn7avGlAEWNNtTby2uAot9bc
RNoBo2mdohNdf5cbigUxNYgO2A6bUQCF2LyQlqKngOGner2ipAJ2WVMosiQ+ProkPSKnPQFzbjUj
kg2ysPZ1XiPmWMvUYqMJmiQUP6ZZPan9v6+rgwkeJ+goVYAJKALCnulV8Hh7uNJSCXSIeh11Y3ev
Dd4mf+x0VBC66QA6afk/R/Ac4QiMUVDKebaze9uPWU6Ute0Qifq5JUaBvzpckkGgEIJgpQvZrMeW
UJ/CgRHmCB8sOCXGGjL3ka0HD5s5c9L+0sW0h4Yg4WsM7jsLHs4Y4I+oRYqwrMiOVeYEjy4ek//g
khfAQoIbs/8kRRRMpD7DxA572aTd2g85Hev1TqUInOoROTcXW8QGrHnShgk99U9olGxxM3MW95fb
bdguqnG9TUDp/IoY6Fd8EQa1nV3HKbyv1gqQumzYJOQaj5YIjYwmqgndrk9wLdvEkmkR19LsI+PG
qzLhF+xZWQoiENWpcn4C198EIbPhKEKtZy/WLTiXn8e6rLIVIEHA334LkLLSofd2CZ8JK6C0Lk2h
ooFZhTEvlqvgP4YAvj3rtjIzPRKeTfaFI68Dc4JdurYOfeuywLK0rhIXkLDrNoF6kzTUtqs6cVNb
nHAogOBOOjydsB3bdkKKmnyUCuLm3D6kzYyPyuxUqVFy7v7sI0xxim/p3QBFsLT2dt1111wscDYv
jxOKTG5xJwfi1KcXciMGF/s11hf8pV8+UBOPz9HvwwUdejiqKwgZ7pQnCn9xIS5oyE/r/s8x3oAH
vQxSMvpeiYWmMvuxYeOw4j6UYjmapJmZ32LyRj55Q3ql34voDLQtmHXSbZda3q7a9WxNlPSO0c6P
pXVv0zi4UusFk87sA7RuET/fGz/Ev6I6699NwtsTM3g3J5JPDILL5pXfE4lW1ubKfzf/UuRIBML/
WPALBSjspC9SvZT+Ci4bysvAdnkMHoGyHVGuuC72bJ8k6RIa0pcg1loPy94aCw1n7zjf07RjSBmM
NVsZUTrnUoyhFY1QLuPNjCnq8dXxNIJSJbZSthDU2VUqrOUE5Q158pis4Ia/1I9LNcwC4mA+EUtw
xO8iMsS4Ec6CIDKWLabQimyZECUHDATPmNU6Bdck4H4RCT0mdWrFRJTots2KUAQr4W4OvYla+u+8
m6tGFYCsw5uss9lGV/aOzki0RP/s/FkaRXU7bL701deCddhaiRRyIFFchq9xrcNdZIxH1JsyidP6
EIOELVNiS+uhIp6Shm7DCDr5kAFzR31Z0SPDHaLOP+HDQyimgaPQu5NnJjWXTruOG1UMqSCQtMTX
zmM7yFuT3p945DfCyA2WJ81wMJcLQ0L27aa5Dpy1lUK4cZ4+DG6eDFqUmwkfF8bT9uh8XCG+XkN7
JWrAa0qcOrwfb/Lt4wyagTS+OoBkx7Ag/QM9LS2nlsR/0vyJ5+8pflpUzUNntASOxxgqg2XGDUqj
wsSIEK1QXzv3EURAJH9kLTCLBccSrx17ug664kxkAxz0t0FvqNkMc/LtJ5vzz0HQYsdGXpUggOQV
cnEe5Ar7/+yrOrrwKJ4Zuz1luaIw6u4Sc4+HLA8lRVP5H/AMGzmPg2HUTnyD4trAlzlxzv6615Q6
1e++x5hL2NuPrH6o5AcXuiHYwGoXKb+2MCCW7LIo2ryeWvuYH6R9Eea9ihdQuFFy0O7qJz3zVRjk
debRlvZd/k8AjpEUXT6JG0idEEXfRKnp/0d1T5b9bnyb36qrYwYrySYzXj9zVNSHEeGdS2O2oMsv
pxSPrYdrmX/xzR5WwNntxsoBp8dzgpuKvhUkB6GS73u01ckscI6p3GhAJksvc2guBpA4UPvzFZe8
TU6zeUtc41oPZ29t2ohgflPhkXcxvcMWsHm3ELjgtvZBSPuaGZG/iET8WJCSbhXOEQ2m8wF3bStY
rhI7mHG33XLpaGH4FQIOjuqEk6A2647KeOV3Qd6aPp2y2ZXg4nkuas7kZvvAMWtHdiENnfVHGmcm
jiVOyK7fLKpKUp9r2n6xylWRjE4BFfdNAoRG9n8dbMnlukfpPq83sRXndwuihVhPuO1c9wbOfonw
pPEMsKFdHmUOhy9OZUyDd1huAGdhtJiooGoKBs+o3oqK4VtC0gNQhcWh0pM1lADxNVqgo5vRGeWP
JFQCeZS4i5ixqOf+1HbVJ9yTi/aHAUEslNTvzFhxHLfXcLOz7CCSz/zrmq7gC3I8QDSQb+KdmaB8
f2zSHEHmtvWRwQodkUquj33yFGVS7F/3qdRZg5gRBOLiZWJ8M7PLt6TsHdujuxqWWbI3r7IvtajL
bTWmPMPu6EinE/FNNqgMzqTiNxgEoytVpIEeDvQTnzpe3dBvQPNExIS4LqgGF6PniSNq7Jg2JUBD
F4CoKhYl5coUzIr8BJ3zrGWNXon1kIQMz9MYwyT1ghjo+EApMZwM/iP9Fl+t6HU3KLkn9uzr8Q5Z
HrVeIknbtF2Wp2yyZTbKw2swwTHMEAz2yYUhRDxALVKnw0Zot+ao2j6rcZxJ9XtYqhZLMiWGKYs1
N81H9QNAPW2kCH1871XfxKSHA5Y9N78fsbh4z9YbXKti3PwBDJnFq1YW1a9wbJQsgWLrccx1v/7V
44t5NvpjOj1tv7LyQt7B6pjanw+hvYr2TIzr090nHaFDzMMirBsgqHx7cGDevG8mxSsAeUkPNE7j
/WUZHEBc/c9azL4rCZSD12XAvb2It5E+sjGPbVLh57NzCVPjePIHSewKKLOEDW2Nv9F7xwqRQ5c5
bvcPRp6XvcZkcK0x2IVabl+c5u7k86CmJAvdxTrBkeCZfegylY8mx3prHy3IJm92S/DgaJvOwpEq
j6t/Rlh9I+qJ0l7nu0fUWaDFnEzyyoYjpB8eCANouh3k7YKtBL9eJQ/Sod+QU2KHayvWBz0U1V0M
dXikY12QFRzNlizxoRQwzC2Vr2UvutLEn3JDFZcUjq3b18+fkgxY5Pdv7ZF9VR4vtYyE4bixzFQw
EYTgEbaalQba/qQ81eTLH7D8uX6hB/Go4y/pA3pP4yTVpePpOtEnwKfuLvCdncgiI9EeKRNAPF25
fa8nZGx2Nz7tfHkNyd1WxFNGITkBMoAe0re0iGiyzwfF16c3U89M1vJdwrWX66lzmfDIcVzyEY+K
8ixpJaJ8BByUtfSxyjhhpztFbGhHAndsv2y1KdZNGwGTpAhCXHFTMDm7NY+y+a0KhQwjsaxrAa0+
ssSYUX/PGvEFdlPDNt+KX+pEEpri/5L9btNE4F9FnIHTASCmlNZUCEEFZgnNdtnWiVBoOu8cT4x3
HSon5nlKF5P7/DnZ/zOo8xbodo/FA8JnQbkTPrbMSEdbm+R/HafMNcT2gn9J6K6oatESd8W+ZvEI
+aXn6YZgCVSZ5Q4tJ/fxkcIMxi52Eg89eESo9mAqqTkYFtnmdnVAhEIDMO4grMnOvWsA1T1LrJwl
oQ90IUw89nj4Rp5Gaa/k2ozK9rzvGPPQFYQToMFqgh3HBeEnFFIgGoVl2w2bXJ+RC+J5c5yqaD2w
gCUSY67XQV92KCeWCp+DruG/xzK1in5cI/pEJBlP2FibnUlhko6sRN5Y3AS12KLHzl7E/Yv9h6pU
6OV1MzFWUfScIq95EiCdIAikfDreKTbRH4hBwwbCY50CkotGZA1WFVso58a5qOsuwJLhXhbBDFAY
wnRQ+A1Y/YEa0HquZtPsLBHjLwlBVXms/6XSz6phBpECCqVKkqha4m0uAKiDE7wMV7oyEuDvyxsj
9smMuxTn0XaaYanaGiXKEK/Y/K7r8lLbo1Qq6leofz2cataCYmnEOYW7H289lOKWdOQk7eqw99/Y
N2AAcbqiDiUiZFzNHtmhqBPLbBQP5wvR/WBuwm+wqmc6NeAKFc8RAtcOr/974+fTkglASsZaMLYU
bJOeoMac0vN3ay6WFpj28GUFWP/LBOdv4NkPlwnS21+v3nDmtnXEtv9zPWjTAkedaQOUHGaF0+s4
YsalH0W3qYzEIx7DAXwxKpy7r1oEjH4tz0M5li4CNN03n/jmhPQqNnsNSyD6jPJRmpS6FZQmx5Cp
Rkc1+SDodpEMqgaEgwK3LFuz9QNt97yNF9f1+/mS5i8GL/1mHWTtWZHZ1oApuwYc2chEekK5MeaO
FgSlaohuCF5olUeQVCnhCZSDNSzlQ/EBKve1gyY0TmHnwYOmLAX1GRT9nm6p4LU7E3itGczcvJLR
Q9J5VI3suepi+pHhmTnRkFocVOzR2BVgZw1ywI/s1Jzpc2R0iVhybp2fVsHrpVZi0iHS9TY5747l
yrTbYjCRIidYAv8MZCMwsBQxKd4OV32p9BskWBBMD8fPOv5Azx4HfZz2T98BbFXjV9oMOmmj7Qk/
s2znPLC12x6JtiIRUgbSRa8lWKwWpkED2MILewbZ/QA4mXm0eH5evuDxRtVW7pmAC+IBQoUYtmJx
hyqUj0XMvhFkRK6eQ009nErv0jx9ctrZZ4YVYh362SiFBIPBrV0t6S5TbIiZzgXrmiGAx+L6ecrB
5I1V10i/2n9sJpjyIBJ0QFqqUTOkMTuedpWOv4VGuv96iNI4nChR1GXyEQuxwzGdeD+HH22/bFlz
MkaEy/oKN7q5BnKk7Ue61kVstlHSW9IjsWik91iXWinBCi3lApOdOoQnsPGP9NFNuk4VNzBfGc7c
IOB9Sl6iKz/lmbfZbcyWw733evYXxD0A7aIFczKLfq5AH+xUxS92RZxHjylcBKqnYaKGKjlegEma
+aMYT4cAV/p6OU9KpOWahYQeNFTKicyaMzqo5jqmkWKuIY2QCaO6Y+pbnY+SjleRIFoqk+RTaJqU
koHsRsjyQnwpPVDtvwlYUM4c5r2iWl7QkLxjifHVqhNlHP8xFhUMC7HSDoVaD5eSMd5+tlUfTKrh
sO8Pk+Vhrfy/rHg60fIGG+ZzS1dfE8RMy1cMITq3Q+n0+P2mGaYDtD8eXBncHnpqOaiTgI42SytK
YIbK/ZfwbbInOjOxxMYy3OyfOB1d8Lm5gK9mxwOahwTf/wyvmWw0dhAaI+djrPcrfdClwBJEWTIg
HGo+Zwn5yh43rO51L7TuOrIgbpXKgip98ScZT9I9QSC5jWgKUVxCERo9eXc/2R1cWWmC6Nd5LTyk
gL4RW6ZsNt8ZBwJbItzfTb3/eP//YJxPxNO99sR2xllwEbI8388nspw9sz0+opwFiL/raOw+LQO+
UyXakXbbcjS4A5iic9vGOS/e3AnQK82tTGe2eFhrVGClOyEURBoFOBRMMVt95O7dyTq5YrfZzX/0
Zi3bCPe1J4TwaIhJhsl2LVtco5AvOfBo9tguhwb4NBiy+jn2vIH6d74TlvNHGxNt0Sekx8wHHFEz
Fu4ncFlR4qH08Ok9F1Xj6zLGONwMeu2FfjYEfRMJXtXEL9us4zY0YUYGyipihClSIxYkzlZ/eZoG
ycJf9An4U7AvS9irc+ylDOiRcqKrsVZ8jeB4nvHt69CB2y8YnjKDTtrrSYZnJ+oBvDFmjAGw/89u
qNtUAcKs3uxmmhtpHsLxvTfJQorGF/sBUhik8RaPrUDUpVv/38S1ZAm6YhjGm9Dw7eqJyrYmgjAJ
Wmc81kd4wFBXdsPMuN4cxw477nCeTIWCj4wwojg2uCeNpipvBE86ITGKacQngXrnVYUxRT7p+kva
XgRdG/ofPluLNI5Ypu1XJGQmjtA80EG2jTXg1BuDofhPvTAFfG8Q2bxG8TQ26r8b5ek3dN5Z+iZB
SYpch1FA/7ARBc8CgI/TqWpRwEUY9AOy/U39QFc23gLVHtQESvqZw9HD/rww/HADwCTGEID+Cxj7
SWoP0IWdnyZnL70Nqm2KLM6gGRKwArYGxzs4LxuLYWtMvozTtwbhR2BlTbhoWlRRSJVBKSbkswEl
qS+oy5Y9gTtCIffmbWjyGyrfp/vrrCjRNR6VzZy8QQtIC8+T9TVhsI+fIZ29t7y+K/lFgytej5hr
7xKczxPBV84EMBEkAudz4DkMvwPNxmuyfLkOKUhZZbcwBt/W9nUy4xqMOfQA47gON+yKvdunnsjW
S7ZrYAXZQ3Am2NyPECMEojYAGuCse27av8HFBy6izihp3KlQlYDTjui0jhaNmy3DKK7Y3b4uOnUU
953cZF2UIIuysgPuK3ED+8jRNblDIw59qBkUj2HlQB8Z6NdQHD2JtEP3MCyVJ8OJeUN7GqSdG1vV
zYhuJYPMx1DoJZ+hv0zcGt7QzMfwCmN/WHNw4ZO4yPSvlJk0RLxp5Am3jUtnXk7oSi/H22pnY/SH
NFVCuIikLa7h15KsBHAzWFaPn+eIXrIVJ09Md0AGt9CH0zQE0kuXcYF32e9W0YbXxeAZTA5XT6sk
vzT99CjDZFVvFlkzniE6ZO1JI5Go8670mdHG9pP7+iruQ123sDuH3jR3JpqXc8XHR1T1mGh3QsMf
8cub6HOk5eX7NUu3Qtm8m/bA2ECsZzlmHq3XmdJK3nCCq4qjG+j2lCojqnjUhWZxor2eBOGISVus
0+mF9n32obqsyN5BCdoseztrzCRPg9Rdf9pO7quBB2u9/vXV2d90OGVjQxgV1la/T6SveziHH4Pu
cO5PJz2C2BqnwuEvvLMYYtwTnhoK3Y1inhptueA7pvT/oF+t62MQlPMd2m5GiZTC0sX9CyttS2SI
qpMf2ZIm0WQOyqNqglnbINKI98Ze/5k35Nhl1xwi3l6MSpdmsmMtfr/yBVlnDwHXqdoSO+V1bJqM
dPpnixkEFgXuGZYVtniOo1Wzybe0Swo/Jrzopo5DxwYzugz1b+BG6MuhYY7ODqERVf8WRJkc7zx9
KoIuIfvqWqy08mRY3/aD3tp8efmoRM2WelZu4zjsp3L09YfMmcSm1mtDWpjsjzZjJRVQu2VM3Y/O
eLHqjtyRqsGE1F/PHPRLg6opRJ8xSaJoQ3jdaHK+PPzTfUYg+CEDxrDnA1hRU9ERxLyXDdbfhERO
CjlJXtJdaC77yexvfI7YIY1RbcSUD+BixZF5AJdDLbFb+3uxpdLoOBNxTKlM2uUGjVsbQuoF8eKF
n41GI8dQ1qgHoLdGnLpVrvpY4IWOHqSmk+Y4cVpKRX3bzi9taVTTgD2SOLBOdttCqBY9I1fcRz3k
QKw8up1nMJGTEN3WfPSHmb0fMfse6bxl7dr2BvpSZByqlQoPYmpie3bkZnyybB1d8LACOfp+XwBh
8s2TgzoveBnnit4IjuDTiq0/0APg/gnpq02Jz8kJoUwDhcmVl6VxeGzL4bRCt3p8udrHb2w5fyk7
i/M9asviiIZcv2UYqJLKHwE+whd0l85eBeA9m/DYbCHimXF9DCBPd2zTa2wFdeemgdNB3GDPW5Uu
rHhhgCtJKWfH4C8z5ADo/NqgB3X3Y7hQJr341hj22yszihJEeETpBOAZR1gJ32YMk0yE5voRlf9t
7oPKNA9ULoQc12IeHCSrAdjY4gSJlLsvze7OjsOxIl/R7CXiQb0aG4SJORMoXUumiWYKpb1q7m1M
xDnfd7K+uaNhcE04bbtw7Ve5KJ1Oidffjk9H/V7ivNcyp6Rx2qatdOZDWsYGm5fHyHCFMWd4rASK
wgAiQS78v8ZzNSq+zXS4HwPB/F3UInCsFpXEJieZ37eQEB7SQdxSqoZkrp9G6O/Wn/NaLuWtvLmu
ZHQWginlqTpav9aJNm5mJBYTz3uq8mLybSSIx+jDRma3KqAPk+bJXuTInVYZlPj//Pi8huBmyP3/
abg7z9ch3ih+3wLcazdWsRHzFYv366Pb1NhW21W/F6eYmlhwvmIhTf+rLl1gWSNeQheurp4/GNjk
wp0UnATv/9xFQEHLu257wt+Alxe6S8c25iYJgXmNDmHvV7bh1besMeFXuWxXMaLxzy/0VtEKnEys
rQ8vkSGZaGOIif+0rXbhYwIa7J8ntqCgikQ5IU3oueZc6Z/LNZ4agTLAEmVwbZKivxQu4aGL6OKI
k7ewa3BaxJq/NC7kklPQi9fy9RmhIKHM+377c/D2r2876FI6JWZNrLi02qmzm5GJqT2vcjEYAi1f
0eZ7Djlg+gViEMX3ZtOeH/PO7uYos26NzUdsuajmuxL+WKEKL26BF7xZv2w6ZO/PtvpwY6wp9jB8
VGQo641kZ/qfR21Jr51Ds5XaL9sqDOkG9dXKX+gS5PxIKqORfrlg8xHEerWXaaect9mAjn+suuAW
aOAE92Z+NUDTb9DVNIAX9vIbCmZgxmUbROYhJ581GnmqUEWFvuG0Prh5ISJinMd1M6tdGrtVUVWW
Nu9wNqAWWYtiwxEdWkis4J4qE61tMYwJk4ZiBVvgsRHkjVwbv0rXKlQHweNB+NToapyvaPianSiL
QXd74H+Q0AYrFyCkKT4/YGsRNyqAUH3FOPOO1Z4fa7YQcA93ZQcxifrEKG3bYFWuOWKwjl69kpK7
M4b/cGCWxBJiRA+9MqMjcfhfZY48wRLMzkgEFconx4ub8cFo7wepaKhGPh9cDiQImVR6YasyVaTJ
pP3kbT3zZ274s9ywGYgnLNNVwZd+/lw8I7FifwpVQ3HNgd4PaDyHFlVv0Ol4x51kHt8y7hxMqq2K
4KQJfPMILLoq/egh/dRvHW3NVixU3KscW+i4XO9ueBW+qb+RbN0lkWdshVcbNYyIummyiv4KVsyz
fkz+apspYWOyGXhd9LCYDQ6DjyzVmPRkLU1KDeWPbFNW+LAXzPxFfTg6rjtExPUFNh6Rd3aqJ5Pi
i2ylWH0fxKRFYeSDTFtxAIbw3n7jvaI7K8cOIeduZAMf1+3lp6B5HjAMiaVLuYHoEt0xPkrBUsqd
ATdzewLKzLaMwMrtTVDEqGkEb2EtrVsAw8S3giLD15iDFvZ8O4VyGHeNzEQe6rWhVZcyt0VhMxSb
uZQhXR0VS8FU3d6D2uQBig7lBMvoOOFAARC6pCZ8DJHfN3ogP/IwAo1pKtETij4rLhzvZyZBLetK
u4LnHOMn5rbyCQ4RQjPVYjzOMbR8EiSjb2vToOlL1TIHyQfSeocYz5iNp+8+OKttUhDfmklAgYDD
+a1Zs6WTQjPJPipNW3R5D6ofSUTgJa/JQ7FH1t/WL009JxXv7Z+52KI6WvhNifBNgqGjK5QSdS5/
OY9Zy0okOYD1VJx68hUeJB0wT6zYtepMTC/VfW4oy3ELj9meeVZw63aohwd27HtpAlpbV7L8JCoe
gw7HdPpqlhHWdvkLl+sEtPJDZP36slTku+y/TsT3s37eGMqQBnLdWmyZP+EU1XrRI5DOvZgJejPK
5W9OprZ+R6JXCwve/eozVMAEBExwQS9BFZUm1Uu51adF43RhDamWx1JAuntsFLnyc4nNB1+FY4Uq
wX/f+lU6NXZGcrgaX/9SL4sjXOXLACdnIew9nqpn2XjIUiUjb5O9EBGKf0e2ddKVu4HtXriuki8n
a+OdjmA5HyO8Cua+s13eV4qcqbeSisp0f5l4/XzvIelw2+XcMxb44j3DlWAa70WVg0L3N99MVWEr
Di/m2yix7Qp4D6ZJZaiJxFQBGSo+MEQayLe9jwZHvPcGv1LX9kBGcZ2zcB0p9cJvU4/fV+HWlAsq
WWIBmlIAvlNwMiDZ/tSfCCDQvKnnblYLtC6Fbk2a2LHmEJlLTplXO57rToNrTyzmBtonUnCYhFYE
h+Y9wU5kWpB04IfxlhDUh+Z56W2xq7A0kbIFwxbzup3N935CcE1SlZ0dRxmhilnX+ObcCL/dqZjo
3TB4UT4DeNIkyt7H4QVT81uBRvUu5uVQV9+srgj3o1jeRAv/8RwYH1KmX2YKxeyctaC8HUa/dE1O
91CJnsInM23mIyXLWE7VO3Y0veB/UCn2VxbiLY0ohhI9YTL5KajKm+kBnMOk3dboU+eQ3/8OSvkl
qgxRan7bDaC+HaKv5tpHOdxmg1mStHU8vM9g7aP+BTwlWWCkRBFit1WDHXixFgFnZSqtmKoJi6Wk
q2bSFtNtNZn4GtsAR2GYzGH/rFC8P4h6muutthpz7yIxel+u4Ccv5J1BSoNjTEHG3NjnqyWIU/Dg
z4szvYTHqYGXYtlwQOdtEh+OxEsSEdsDK5brG4xFfJS2lsBqgFSywFWJjwieK2ZyHI1Lr0CTUa2c
SlhtiWvK978AQ1FwSdIVQ1ewlwtp/sc/iWQJV/2yUd9OIt/P3qExKZlxV9zMdwVdOJ8sajN0op4w
VRAf0B438bgoL4Hxr1aiQgqPgco9eGQWb0gjz8OuhgKut/wAhya4G+HRcUTv8yWGVA/N3DClXpsi
1tQCATFTScp2wEdAPVU2Dy15tbTjA77V56b821E+r/kal8C44NooAyf65kSVw9A3QYa7jHaDy+Xs
ZqfBieVxGuBHwFbY02pgZ0cWKvMIwzcH2bfJMPgTdlrh6Yvvybdc8QszvdNMF3UrhcdCLs87bRrK
M+FNTQCijeq6sITHU+8ZJ8uHJlS7r8a+8+Hq0ylFFUQcnxsmysSeyM0QHYZxH3nCPBBFIC426dIP
jtW5o3nMhnJex13RmmS2BqJlZXbdZK5PBFet7+P6trtcpVsxKypMUE0fF9r99gr2rOaKvA2YW6n8
uSAy9aUziWINwBpjUd6OUTkOjFBej2gSTIw8D6CCoTJQitVJWUUEMerKwODh9abomlBqJMNg0Qyg
3qXbQp7BH2qx7fR9UYNbz7uZJhuPqFcZy+NEkR0Jqi8lDl3kpPFAyPQbuoV4yxYlnnD/A2Ftc47t
tTfcUu3r9xYEjzeAGhIFyIbBrySG6ta+CBP1ubCW/KwGkk7kjGnj3Vy0qxtOoJes7Oqzsn5aONHv
KK5OjCYptrjFUn6Me/nky8owKSJLZvs9MMTjzv0LQZ+I4G+KjwDcFtULfGQ/X2AUIM6uvMa8CrCr
IcV2qsOIV+Rs5wlYJqCweeuYtvFPDyHKS8x9KPGooyxUJ0zROzcrwDkJBsbZ4S/NDF5nXebzo5y2
ax3Ql/mfMwpH57BA4puAgDrwtUlfiMRSJofz9RBQ3lj18FvbUr166uKR6mLZ67jmXUDxpLkhJ02U
TgGMPRUyEkZDbQ5ue37wXgnTsEzHbpeiKJXwT68vekI8YJR98ADjl3sYr5xGV0YoR9EZZwprBWC8
/4p/fVv2eavqOtFcuftC33uaRF6pKSGR0ySO1L/1kamukG4bI5g18rikWzy6J58piqIj7z5a3PYu
BL/kQCGV+RdSOAZr1u6RWZnNJSRnzCF/9SCD2IwlxPV0unlcLo3EHwcwSeE310qlI5wlzNW2CN7J
qxn/TgIPVweaMDVvAaRykGSVpEjfF22jCUnahXcYVtCyH7ZrNxS+t6N1+SAiacUEC9STpm/7pL4x
4VKHKx0jNn3jmSK74g231WrgAXaH8SLIZjbSJHGF9VVxvBtzqbix9ySkCLJV9MK60RDt9rtWNBZr
hIZNYJQZGnwq6i60eq1EKQFOU1aK2AhCj7LJPPgUurtYTdSXIZmyZyb2Hug+AEXNBWEy+4pAtJMp
z4KwA+Eow6GdMYn560BkiV1ad+wOMRnJ4hvEaxS0cE/BE4Lk0TXcmaMzMb4yZVgi0Vi8TYf34oPC
TB0Arz2XFmcEqcVw6HPYzQNYB1Hp5fRvYsYuQR7ngS4xa64EA1u66grLZBpKo/4OYxHzWrGcVDfF
PR/UcfI0hxfldhf7iQtPNXJ0BdPLjS+G94UkNA8kRTuhFvc5mFRselwSKnYbcXEi4fKYRasX7ACh
OX1XV3oRQ8LgHoyDvxMGkHcGRADIiudl7h5iz80Gv7yE8li9DibZU9CRD5zUpLQfJ+DUeklRSuQR
Eq0CfZ36cG5Mpp6B5xMol7M7fs5m9Il02uTz1yxIt26BnSQ01jUbHowOjxpzHarRSHOYoeBrDMe7
lwXaOVwau9hRQlXRQkKDTZdYX7tfWRIV4OBnwPNSEqRnlgO1yxQzVqIk3GKrLGeU2Cq/FM91PNtN
ZBzH75cB2nUX+0U04Zbp/rcnxAqxVEy3LTkVz3/11r97xkejC0w+ySmIUZcuBbegwUUJVpGjf7iN
ANoIbrFEBlJ8MJREys15BhWmiig5dzrzY2ApQAos6QP32do0zbuF3w7Tk9c6baQemomw6yxNPmGa
OiA+iYPBT8TNgmh7PMss8x0zgudkr4eUsej1337C2Mvj8TjiVaAkKTgHmXkR+Tv2I4X2WfkIJI5r
FaQqeVckvyC4QKh0Gkomp0myeWGRPKG72sa1Rtk271cLu4sCt4Mlc6Gyg1zEBVYoQeL7xjSw8BRl
s5R9R6s18zQVLJjmxZdq/uAC3KVklKppG+xNTp+3/3XQjLtFnChF2OjpRZDi7xNAJ8RPe3xD70A1
RXM+fnYYoCppleax4ebAXwUcPCTLA16z9es6OCqdmNSXMXcPgZan9/HdkpCgo3EZ42FmZZ+BMsMc
X6PFa5J+dzr5FV0DRmpzs4JKhAygq7nYYa8Tz375Cj7U/goj5hJ4qZoQlT+8YKC9Xy/zGyAEa+gn
wXJUbA2s5bIeh3Ejn2Dr1nYGsCA0BOzxXEdEIjuS/soHbrHJSTx2pPF0UDgfV3Ym4x1xBo88U4wE
7vC3VKuzZpzvOpVM4cGLZNCXNUuyn9uIjmK6PUJSC2pmn/+ij2OPSnfQO2mbLOPMq8NqXf+XZxGq
3Hx3k3TdLCFljApxqxSfX4+Y1FCQ0fy4wrm4ozLTK3qDTKFOpCC1MU3ccmWXmnoUc+sRrOAR3726
PFNi4W59fdqPuq1dzLKhzVxZ0o56eG9Ht4rm5VDE9XD7NC34nfFkOPyj+94EODMLVyWnvv/vkE0d
jEeVH9+JnuazDz/dYA6LkuDF6l5R+MP8tyK4foRqnHk+kCssotAKe3cvHfB87py4NmLgU7n1z4jf
4pDl3p1uWFprAsv09v7bTJi0ydiYriCFt0edioS18HFadS0I1cvZJRRJeB9g1BqjcLxIg4arNDk/
O3+JNYuQjT7dgZGc0iu4ZvjD/OBMjr/FFVWhjNZOjejxcw9Va0EVBEl5MIEjJZTGdcq9+OjAz1ZX
TG7FavI3Ci8+72o2Jh2Mdhw29TtZQvY9Q1+sJm7CXPqYxrap5XIk/lXxXU4qdcOS+9uqEuuYM2He
Ds6o7gaPBj3huyeDhMFi0O1v/AF2YYVH+9hhIx3fJi+uqa4LLHzVCr+/z1stMbvACDJj3OwP1fbb
O0lHJdNlqBj6EceNaxEOWT3H1VG2seznADI+iipsaJMygeyIifey5UUs1rWELc1eCf+BH43SevLP
TKdIUcyW8D5r8n8UBs0cGVOY4NUHgv7PCPoAApS2htdX7b5/6fPRVp3lGEXmax4bg2XPyjI6FxOv
TtyGXoDYkwDdnh5soEVkajaGLNe7MylFUmWq6wyE9v9aUdeiYaG/NeHIZHbIntRyiC9QNCoSK9Yo
b7wjgvDzyrTQZykaQlxcQuQ7smEWW5vKWpMZSJM1rZo+E1axB0oAkI0friuknTJmX8fzKIvILqay
lCqHxWf9m4YBS6j6d9y5M2YsebDGwPiauaKTkgqauowxNRuEaZCHIVLxH65m6ZsMsuz49mcPmM/+
IKMw/yvz9y9sRprArbaba1uA8SSWIsc+pUIwR9sAiWxbjwruOdMupA0aSUJI7gkYlFOam9AcdmNz
hEJkKL4haTijsxfXzaIaNwEnbTNHPOAWlqubXWxyOMwn8e4Zc/UCj0Bt0c4/4kmWs6u+gH+eXMib
/jyTiJ9RRJv41OMPdwbZ65nfXeq4ON6n47R+3TPGzkc/GOUjd859oTR9AHzaWKYwr4yS9vnTnt9P
932V8d71tyLB6F6Jq5feUDh1R4dtRlAiFNK3WDljsSynheXVHvkeKN4RqoFo43fAEJ2Vo7lUWFWP
jsZsOrt/uJcX64ysSSvqKk8XkIvOQUP0fAJIY6SBpcs+OHDng9pBh18uJduTCV81a9POLuspdCTN
0CJPRLKTOMP+bwpLRE6OTpDU+uwlyHNRFvnJ1B7LUB2pJvtzW7BZpKy1YA7laA1vNwJnwkQf50dr
+4dmkRCUVzQTsrL2KcQgIPfOoHHQCDjSboaxdcBG6ovZRRGbyr2Iupxcm+pHQbE2lhDNYOv2jMPA
QHCQDtaUR7ITsP79lFuTseFyiDdkhAkMmF+ITM9I16K1nZp29qimcKucW8mnQn9b3jC6PI5ImpH4
RDAY+5cFtLfm1tVCLnOu888Vv5jyOEGE3s258dn1eN2znTTv8JIFAB9zCBxCmfcZae58mIIa8+uG
2qx6uCheNbqlBvKSeKFfBkghj0ryrL2UtCPMJ8emJuA2zPup8ZqMaNuh9uPQ/9YKBwe8YWOymkXR
73fZqMua2/7b9LjsAjgsq3q9Hil4qk9p8jo+yTyQdILhtcaAVEkkJSAGqvzqlHUPm+tn9kc4i64h
PI3xlhlhfEidQT3wb54iLpuQj/pCw3gawTeK93W5QLyW8CgjVzL2NYJ/IUHANp43AGWFZonD639z
cAh9jC+gghpxg1bJpHsDPuSD+de865zxv8fdwY+XmwOoM5Sr5TLcXishjzTyFd27q+gq8mnfKXuo
09Mk/ZkNOLmc/uASSItD7UPftU91snwmBqekpJVQF7WXSi4NClb+rspptRf0J+wbMQe8b/pEw4i5
bhKqJB290ZkqVUx6u3/J5klV0VAd+wKa1re4si+jn6P4Pj+etI+iwaPM+xffYP2PI7hr279MVwEu
vp8IsIZ7VdcKNy6wClhR9k7FlFyHVcnGdhALuCaQDycD7cxaGAs8rYnyuts84oY7xiQJwOcpZ/EA
yGtWIp0iLRot1oyOEl8RM32gJ/aKz6la+GRX8ceuarzQbkUWgJNTwd9AqPSAo7XDfNBOEQvg5M7f
Xd1wg24MPo5CquPnm956jPqPS95HkfrmHKSlFArYl+3wrMIyFh5Zhu7qAnYWDok/vOGMVF8TaPmW
DhPoMUOpdmYKeYrtQVRWhUVcHlR7d/x/GVyO5Iy584A8O1UxRlpeRnK1HY55H0RxdltQkKpGoNE3
2v3D4UoKMQIvL946NDAnMb+xbsTg6rj0ut/jeFb5/dMOns61sTHzx8DfNUFCPIlJEqBzcvJvYXCB
wImH40iwoW4Y5h+w3kGoSo3JmlEj+r+pgbBP5IcB4Pe+SqCwJvIc37pDH5OuMdaATM07SVt8No5y
58Y/RweZzlxf9TwIe4sp1INnA5zsbDXyXi3Jslv3aW7rBn+DCWPGOEBNDDq8Lo1+yOqZL78ideRv
MaEVlMvEjkcnJGl+AO913mIx8OKTtXsMLCZRqkaIGjVZHqXGia1tI946JKMpODeQea9Kur1sr5Uj
sXn3GM2EtWdoM9auAg0wdVcebxLdwP1e0uPBNxIiXjvjhYfk5rzt/gtx/84PB+IKdfs6wtph692I
+a+5jUXTc8Bl96rShSWvX9KL6qSt2TETIYDBxXB/EGV1KFE6PwhHVimx1K0pmC+OdqKRF4+P4jU6
RXbehwpaGZBfxfC47XZZuwPedaHTt4c7234OC50V4jClboBAaCv9QS2vf1FSo3XLceHO0KR4p/DO
G/owuauJ6/MiVu2JcNdIHe4VYUPajosLw9GixR0vU3Lg/9e41DIRAnxviQrKz/2t++3kBjPji4+c
UtpYdelFbec18iMnavsp5uokhC2S6W2RdSmxF4qIP9C6vqsq+DiA19PUCTlXeHre1TOPsjDPlG7Q
xRCtB0+WwpztxlfAvIcOHVjI3aYbT1r9AJeMGsDvKoFV6kiw1sghGDpmeQKPYKH7IiIOTTiUCS5q
gEnGXP0dgJrlVs75XopjSbOf9FjPCjPGyX/2SRSNkBqjydjjUzOFQVj2sRo3nqUB+Q+Jc/s+T3PC
vvtwOFRJ6f+QRO9BP/rdJszSX3jeFWZX4S/MxPmEBhxfjo2EyUavIVozeCe4FfNFmYF8cGlJSWcY
epB6dRA9fKu+bfLIDAxxjiMcvOqiG4jTu1Cm5PbcpnjeIQPoKwo6X7EUq+5qBpKYHpOPyqr1iVo/
ZqaCWx7Gu3+vqK+6VvnVO5F98ppkHp9FzBSK2mKCXw/UxkkePZZ7kOzcynPwcEMiWB1M/5nvlOrd
gifx6IHCg1PatYmdrScaT+WubhEAlNP97dZZGexIpi7Vr37dVAy6EWYQeeLvCjMv8Nevh+516O4w
7+49+iiZf/O7QrcJRrmwl7wRbxyMNAmvwMlog+MhPMndhpa0d/l8DWg1eYeWizQPurDMCyBKY3Q3
uj8MD0kBahYUyGFVPv2ykI7bWb8UBrikYHmRqr/a3I/OxlRbu/eOEbKosrU61SFJ2EOCc+jUIrE2
WgBuZt4YRba5fNii5KCC0H4M0MpXhp3RBkYgE+fSrD/JRllBZNu2qeIlMtxABsM6s+bjn14U3U/G
Y3uiXzbM0BFS7mQ4K/1rbTocIBPTx6Mo6hBg9PjkZCL/EZ3regOUqrcxIxEV+DpRnbi1RFoKa5Ui
2Uqm08NvBvU/lSniqOCcI2k/9v8SxnF0qqOQAEMxyWktkAY2I985m4zjRZlgpNXnNN/EIbAdGmmX
mQhILHYPGCbCN7tiYTuZ9MS/RsibzFCe16ym5noSvFD6Td8Ni9YHjl4acy/2uYG3tOA2UlfhRF1X
oR0o5Qsp3nvpfxL824+0FAdHJD25lWLPPk7RbFp10ltOmBJoUhgCyJ/mZw8FLzpxQy5YdiFd4FWp
71chyraN7KTHg38UKA+yRj2p9CmZbK6pLzofFiFnSGEwOu3DZJiXAJbqRBSciIDromFv5H/X7cRg
DeD0g3PeQR1A3REbnlWrVekc7T/EebTpKAAqOfjhCTSMJrUhLHfgOqhYc74YmbTSCCSC3SdIgP0T
EyV2Y1vaA4SXZNp0Cii6iM8/fsNoeQH5GB8wuWGsxFN7cmKcIqZZVy9YMPkskrit5Pv+7cfH9swz
Z2TAgbi52PbbC+hwInqhsik6H3kIud+mFO0k9kQYn9uhafC3tBqsqGIkQGIZ+mmH7RD2yrBDk3bm
+TkK90MFaV++huEClFawdHU153uDU1QJzCcyivRmPpR3AJ0l07nbHCaVfSuls1nEwYKcCHo3xb36
DT++MsdDd7wFidH6sDxdVGy1N8n0WZ/AIp5Ft8ZhE0wrzaS/I8iFd3eR6BoqlQbEfiiAP8U1RKML
txwpEnhLhfzyO138lu4F7Ns8uwYwwmPQ9J5y7yZEhCILP5Gk10l4/LgLSI7Rw1RNmnBXaS/NtrsN
GrWae4RHOGXMIs7zVYueTJIKp5twvoemwz2I41oogU+/7jWWw4cnIXP7WSnaPv82gqhzKR4GbTK+
f7HD6vbKXMc5v9JsQHK4aU3xeGne48MKpitHA4EXAuVzpJg4F6xYnT9zcHTdgDUE72ZsAIRL1urn
SVZIsJzR6PRhqidpiUGJ4suF8vf64ZCzzBuiJTBfHSqbR+8IHdbYheTjnes1LCY76aNJmL9bdiug
jT2nzwxILepz70oTcH+Ivwp8vSfTynYSAgP5fBbb4fjH/P+oYjNZRbXP0OBwGBCluibpt/cOVned
9UN0AC6ve2v0Lpq0t3nRI5/ybHi4TmXLkiYnLqz04/tTAnDAZ05sDz2vApUUPJeA7Z0WoHt/iPKm
rqTZWxU8YMElhTCBGAaAfAXLe8EwRr7/nJdPBPF1ER1dY+skJtz90hh174ZiieBtH/qsS3c1WNNo
gaUeqnQ0mZu2jN25PVClLWfGIvITaIqr4/CFHg5IDU/wqpbHWBDY+X/ZxTjkHC9WvtTCA6sdDlVe
7BvJ+8JMkj92c4aIoeb5fnHn06s3UC/d6lSAO6YD8c3BEmXkNszWvOdBet0X9E3R8Yn+zZpwV/0z
WwBIAhlLO373t3xt2Ef98df2xxo/DXca2dHVABUcxsjK7K+kcprYvncc/LVJiv3QlrrOxY2+c6BD
m6hcGuD6C5dkyIpvzIQpdwxNPuY3DzJgTXAHve42T8pT4B3Ppq8yzZczU+axIH1d4Z0qclIWmf3A
e+HhIOk+sFVl6ObTAXPG1L4sk9DK/g3yLj8rhZ2hS0UYS6qP09KPuBsVOhNSaED/eTc+orBvPjog
CeslEJsua/TRhNl+GI15WZeoIZz4pIgbj/pV4fNIU60zF1VgWWswtzLwoqbOgxZR4YkShJ6jxnAS
vo7eKUsjI0LxDv4sKM0Ya9gFRX74/SyQXBPUHCAqNHPKrKAmq20g4+du/Ld/otZnn300oXeL48mX
RyBaeCgVSEbJW1uoLhnh7V+hDo8groGLTrOa/nZ5cNC3+WjL5zJGLFAGs6CAgN5IfY62kt3TXfvD
s3n1oCDEwb9+f1gXrhgI1SwX1CihdLLoUDx3P3u3LHGcD2szorrv/dSrB9PWPKnqeQ1ZwHBzKXRb
ERBLNHBlNs3O6hudvEiduxpQi9aobgRLpbYJSPke6H+I7hgpHiTmS/QbzvfaW0h9HAK2A8Upj2qD
Q5LoJhEKqXkhkt+VmxeVuPXISjJyHnPiElU5hc+/vtR/TmqQy+V7tl2fpf+d2QRF2H7MX8o8rYJ/
xDtmbQlJVbluFb0EBFxOTXdh667F4FDpZO43T0oteWhq6zruwVw49jG0rP3IWRlhk/5xxsz2e2YO
u6fp5NymXczzQlJothWvaIXg+mk5HkjNWu5d/LwvpJSGbIlkmaotE8lWF6fx1iDj+u3MoFlrieXi
uLhzmDSnTmKQHysrWFTeMy7whO0ZrZ1m/jisssW+NCR0nHVN7FaIXnk3eG9I592ARQYwJruzLVzf
upxlnQlz1v15hv+mMevacZW0BZ6d8MBeeAnI8bCCKbvqKtBr7cxgKCdtYgs4Ea9BD/gL73fROdGt
gZmMHl5mPEt94ycpMshjtWbhSWkvl1OimhgTURkvZBZKjOc2SywKYJxinvOpiZoEu6UoOEvCrB89
MB4jBqGcxsGxJMvxZP3aBKQ06j+huSW7+//QwHJeiMYRI7R6v4OqrmcD3rvrpPIBdvtBm9hEFhd8
X82MxUKl5HRfEkuNbwtr6pEdTxYdD9+mfYufQF+cLZIw+F047pB0tYrhTciJKX9taAtgyiJVTZN5
ur+HPLUBI8NWp44Q4zenoeSqz8i3UCWuc1DOzVzHP8il+r69oVQECJsEB6n3wX2AXpDPaxUQPumF
Bta5pZZcjltKWdJf+B9Gh1fSzmlaA3rY3P3SQStlzx1c8p9j9gON8GyI6ixtdLLtsiICA7Tzawre
vJMVi32jlSG9ZAcLD+SbRQDy4OThQskBLa3huGqxD816bMFrEhtt7XSn/XaCnat3v8stBGYpos0D
HUDyyn0eByDRnqnx/IQ0c13WTq7LovIvPslDC+o5q/sd3o3nL5xoZxWU9//hT/P7f/fOQDqLOp1Z
mvg7hgF+mKk/BE3deeChW/6iYTPhNkRYv75uU3VMeLIfbq41paIfUb6y3OioqTczjuZM4ytYjcP8
rGwZiMDMN1cW8dAy2uO5Vc/On/7m8PPlzgjKBkqVZu+9YKXsfALZOeU4WPhv3Xx9ChuhYqXyC87t
IFBcoDeje2fu20cf9ePOV9LcuzHudfTHGNEmtMk99y6Gy0f9EV1obCxojQqcS4soCy65SRM/7b69
y4g0AiVz0q9UFgj14pKZmlIluD5Ql4kd15DJbxyzLTtHaf0ekMDZgaiNtL6KW6853QGBCSBkp8Fu
eFLb3YEp2ogxZCLQDbtherduGftyAaxcc1uvNNI3pYgAXQBbkecMkE76ufnxA/xHEV52hTKPUVPI
uem0M2rOvIfW+6/WYPQGkoW2xdJVPlB/hBQ5EGZqLikfI1jDv55XJNFTw91IoQ23mx+8UQNb+grQ
vO8+tBTnYZdd9gS/mgi+oJVeVpeVCFc0KAGDyXtMOyLIjUieJW7+QjFqdjRrrePGW1D7VikW3cuG
cUaY84Nn1y/gIWYVTu46DVmwAbSg/F6BaZEdknXjmd3k0GMRnhcoQjs/l480w9DWaiOuRfSnRkvF
QPjsl1Lmp1+Xw8UiBCYD/osGWa/gtvFE5W0CNK/NzBuyPx00tfuC30yAA+Nw+NwuzQazFkCP3L6u
j/xFixQ7rRIYm5iO+yK5KUQsxIe71NYvcADhmy51ZuasqjstM4CaGYQcwlZv0sP/t53hbjOikdac
0TNfXIi4rW9l/IdInFEkdOrUJTXqOXKBx6llBxa229ILJcPsLlErYmQklpd6bsOLEjenmq0t7sjO
2UNI4+OPKZ5MfYwCmYrtfNuBrD9ipOOUzaGx5epr5OGi07PINjzQM9FhljIzN4h12hqrfmU+lJSi
AuPjLmzxd0enmpg5BAdq0K7z35OHtNcvi6p4HruiHfarax8oH1oNXJ+fKsxhZ00l0BHG9+Qjg74C
CxKB0HAkgv/DmG59z9N1oZNm/dR8PZvFmcWqALRvCZn8pzPhotQXdu/nsAj2/TMlvXcDKfriAfq9
Xanjx1VIJKP+XBtemmOi4JZJbOcljhSMMei70p6Ma4YqLCWzsjsKjmixOs/sCSc5swsoNNAa4oux
mqQ3XdFlLZUYBuT9WoSbeCVvL775Flca/+oNSDUAMFIRJ5TUiW/HxMWEXglYoKezK7Tcg3VAOTGr
8zgnq3SyW4Bg71W6A3pU1huZ3vFOn2Kpk5A30ah0STs0zKDrkJtpnnd7gR8avyOiFjT3a/1u61Xj
2AIJJfoo1jw3wcXZWEbA01/NYvFWafHqxtbheW3bmWA0yyrOxQHh2C3Mp1z1i08VvVed8NF3gVXV
Wkfc1V+LYuY669OE3VhiIQWELC+q1bMcS0G0PXcSylCdgRzcF1Dz3XyVpu0B28lQAGrTLrh4eRki
Urt/hnqmj4kMI4b7ZlQZyi7/TruuD5zkrzzF3zyGGiBfsgvqNGmzS9M/04ZskYtGQlt77/V2wivO
hiiJBNoV5R03noA7OQ7ZiwNobs1B9H7NzVr6ZTisrUFUhF0sPVCAjrb4E9N90ylx6pCe/W2N4SpT
ULM5w/XrUvgAXw8iYSDAbmhyKRnW0qYXDwBbK3BcXY7FFvfEkuMIAc9EzZQBvIwebJrmbypGVc3X
E6DbMQtEgveMmxZH5P1oxVMJpck0PnDWeed+XedXga4kiosQ0/Vca7MlRJpoYUwqoDXEF43ma7N8
JQVL5vF13f7s5FOy0gYZ+mgIuN39dJHBOKm3GSCk+rEMTRrTVjBqzONexrTh6OQRk80btulM3ASw
EcQnupOecCKbC8oLHYCSRdfH5TedVxqS1MXi2+/Wj8JZnSJ26hqyv/KarfWyOkjknZ4x5uXAm+vs
MwEPDvCsLvrb3O9WmDdAtS2fC19BY8NZuLVOdbNMtYkMqcMNGApMMZKV8AeL3sibyIkxPu9mEg/T
AXrd1ifVMK63fNqbDfF6dJ/ewryrS7ao189nnBIHske7aDZaL0Nzn6jSpAM/OgAcvUvHnM1IH99M
qNTpQgbYpRQjhzrtlaI/HySAAVP99D29JuR4OmramkSF/OVtREqQXM0YLNVp7OR4DbKCKxvwcpDt
awrfUvWA8z/qvUnSoEIEmS8213jDsy7moygj8LvJr/2ZTrBL603q3fJLWsylOtA7+VX4S59iCykW
cZTOFEW3zyaUQWpJ5d7Vuc2LgWB327EHi9WNB8aPPsCc/NNDMzfe8yRaNHzSotOoRp56839Rw+d0
tRhCLy2DAlgTs621wBqG11cZ1aVlQ4i8Ijsqvea1+2bJN7jsUFKePjp/Jmxy+OLNln89QvKReXWY
iHCqLKs/k/4KDADuQ8ZBBeuRNtJSu2XM6dnUuAG9suLs1V1J1vsbcgb/v1AvDTart8AYFMN1Daq7
Iy3Vh7PIKq+UEj0ongIjZXxB0w0dEgU+KefYCPQqm4kmZsw7YsuyHt/N2VkcbD4CAwxn6RP9qvVQ
CeYSsLuMutfp8jLhGzLSKiNaJDdaObybbeIG1hbtwChcIb0fVB3k1grBzZF6/rvUELGLaF7oYmiY
bT1u1oOWlxOWgjZj0zZyQ0bI7dOguZK8Vb9pnQXnhd2IcO7r6srAqoLsTSoctfbP4mPBUujWZgjw
DyF5cn6vUJImiCQjZdRttDwc5EmLGPYwUN2pg8YEIAc5qdd0frNID+I1T5zLyZT8Ce3HDPOUYTEz
POAO653QTc53hDbo/mqMPEEUu6RcgO0aX9AiH1m6Ek1XBPLPl6rzQ+0CYjIChUyL9dXpB1Q1kttN
a1p4V45aAZVaOG7nk8JXFKz3X+LbwAShAiwoDHWRx7ITHBvneyYNrqq40duydReUUkE/gf09gj/O
FCFv/qQsVRMC0bdFaRJlYhslGToq5AQgcsxYBNePD4sSpYy/0VxS2kNVl5bEKqS30ty1WrkV6pMD
xr/3P1nOHzlVHnJQ0BI5Qar+rY30wteeyNxsbFRZyrZIfohuDej0PM3K8DE33rzo2l5zkuPej2bF
C7cwHQ4Tz9fB/HYWw4KIaTUQ08KBI+94oY6DYfFqqXD25FqQwMvip2XfhPcxL6y05/hk23kXHVfo
QppJ6SXE8N0R+nnGGKvdUw5+A5qwm/RKJZWGTZL0/gNcODa7PMHCQFqstwWRK8uqgwFq2sBVzST+
tQPI2ZHlUoWQfSlwwJm+ClKajcmzOoMp+qB3UrNx9DNKh51WSKvOc4W70e8NcnaiBJ3GT9VocV0h
ZUufDr17OAsB+daArGv3V/VnLevgQnkMwjlVBuPcw9YaYM9UAUBoVfsUvqUe4zqHsCh0RtVHDP5G
JP3ryvB4wHs7WXkGVzOv03/heorYE7/fzwxQvlM/GEnRugP4QZXeMg0K8HxuDI1KACeaVdGsb/RA
JKu76hvLBqWWHEkJsBuIpCAwLEGe1NIDTa7O2IT8CTtCRQUdfnaTHDLGFd7SYcIdLPWqgQxbUElf
Uy7gIxEaxQFO2NddYbk7BQ3jP4InpY2y4wU+upCtZ7gOhlkO20d9LSRvFDlPWO9ftT99jQpDXoHf
Od6FWXMPnL2yr4jIyctXjjnzJRqWsl21oFeoKEReIUK7brbFpdYZ7KI4VdGXsUcsscKEDtzahKu/
FfskjLPKdNFA6JbkmJRUgP1WdUVBy6vJsY8h7J4esNfOedhoKD9IeWthMwt318lBN6VdzX0s8+gb
ldC1UoNjveyOZax08+jnX7qQEbOfZxJPSujdge8gile4SnaV8nhQcbwlGpZBib3C6ppIfRDpNL/V
wS46rJ0NfflHh/CKhTpp5/zs3NbgYTn7O5gPpkHc3rKHocmk5537CnYosNMXgOZH5H/vC57P49Y4
BgZ/VrN2yp3QOfNBvQx8OzekFV0M0JtkUsqC8lY6+DT9jPO5pHStGf3uSUHgmT4/HweXuwRZ5G3d
6hOvLWev6inDblpy5jlGEzxjQZeT73ixbciisqYa9EHTM9iHD5Bzkysj4rHxZhHcahCFZVrY+BeI
TyvOLQhwstgdFu5NCGeoYWcflOctBBu2pU4U1dn4Ipe6/MXBpBUu42OQM26A4IRnst/ttxsH1OI6
3ofy7k/V7Ds22/FIoPtHJbIOr5q6+LDS6Gw53IK6fCM3eIENlbvmKTBP8ScdFR62SMMiGYDG1yUl
lGUJLF7Kb+4Iv2a3JtnbufMWS64Wn3Hty1lealvYG1Qw9P5apeO166RmhX5oWGITFBpGQV4OANhA
gQCqkWDvKQT58T6dpvxLPp5RISbpA9QwkcV5DUxva+HgaKM4+CrTosex3GEaCxrwMqVdOKmjiQZz
x1/b0i/U1Qrh1xHa9HaFbjDGIZtNKVxd1NukgdKgak3bzFtxiQe8yZYHmQOFImPOtPy7I9JUZfSD
M/ToTZZmWpfD1HZmvu1CFHuLJT1CaLtlZZLC+p2v9u9XG8sGBspd4XM4/mm3BKqU0amJPZ9ozel9
Ior1qjNfUwebn38axrpU2iB7hWmx5mHyOHazYqYB+n0/sU8hUbnbH59cTw35R3DoONnLS8P5NcdI
SjEk0E7OI4kocmLZCKGjvH2h5qt4dD/7VLLNHhbmfod12IuKC1rfpHbKFFVmgj7jAtYTUOMA6kBq
Io+Qf9tUL04dQ+jN/a4Wec8l8yAgncs7AQZLuTfm4frk1jgVutF+K6dwL05jkGRQSF44i/bpP9R/
Ltyh3ufJ5T1Fy75bEl9PuN9PucDZymytz5OcMHPjYPKfWjxtMv2mcNkXiDZxCR191tqChRQ2Yjy7
u2KyJk3hDY6FB3oN1YNbgN5QYL+KZjmohyX93C8QlK6c9x4RC64yYguu6RjLqL774lmlhB2cBK8t
d2tfX3sD5U2mRSbW49zciXYPC9YiXaEgj8VpImacrifhMSNwRxbuTkz36hwgI0mwk6FyPbajcxBI
BSA4MBKvFnqylWoQ7ykhx+46HCTBYxcTw+lR48zEcaY2IjT4WN01guHl7Ef0aNAL91JbhoejsJ9K
3ErLoYRxqOsXgbeXKhCj1477MgxQBx1K3KcGOtRWNB20Ku+hh13IRUll2+svl0gYwqDiE1U6NanF
345K+KKQdZsfZzYs+QVSC2jdcvxSPCCVTk66sMTY2/h/mwginnTYoYq/y85HInkAFvXoQsY6JmKX
8ldlFO7omg29CccyNGQwNV+u2sAASgC8kAxTfML7SshaQHA56FDNz7d53mF1XuZJugx7aFmXj/EP
pN0ZeVcPEXviFT/9OkJwHtI/3gub+WaEkslo3OOpy7V93XA7ACSL8JWbEKW2WFFmsprdxDH4a8Vr
zpIrBHmoBw2YxDhCgln9UKnVnjNzfNS9Gin55AwTJmVa4ESXy+p2oVxxK9z8ofAt6PCgkfB7BHMh
ExjvKSxTQYJQ9XEoyj9rpLdlbrvB94yUSdw8sKV16S0CFNfPi0Bz+e1zOfkDVjBQsL8m79ttUocY
oqpv0PWGV+Ho15iuMOBT6+cVrSah4ETFqRre/G5m0ovQPjMyvQ6IubSAoE7ceZPzIHCO/hiHBmXE
12OpnoYOOh8a/0+czIqCXdnT0ZgUK7YHZIRJ7IeUW6fr5YpsBZrs0E635xY5P06xmAYecFPhwGje
+4Dg+AKJnnGjE+rljScoMTwV9Koq9/JK6rqBdxj5zsUxmABVBE3vWWVnk/0coJ6NPFp3XY8+9YTu
WZryL0ZHsFbazL58xsNvAT0b2K71eEqYZbZ7zBAbbj6WKT0zdIyWc6M81q45pr1xkbm0gYLAobBA
7sVRuCpJvVLtoO6XilNKRlMQlFgkXHkhYtwgt8gTn9o5rm6AhwwuL0FAB0TkiRUvhik/XdH7cIih
0a3VhvqqVAggLTSU81RxvDUZKqC7bp7bLAhnBKyx1RBYSJQ8+4HVDoa0fnlImlHi819VWnppNgIk
oEg1X9CptmJsIypEhnx0m0EqhshwXG3XlejY+sKTIgHWx0O8nYgjLVELW7LaZkqIKFJCZ8gMj4ZJ
/Z19FzQdYp5ynFyEZq5HFP0Y0hLdEgsJ/1SqNxlUMQ/ZImIkTQwzp4mQwfMfjFZAvqnHE4a1koZ8
r6cuAgi4S0GbFoYqrV5sHNfCcLMlR9vaRzAQIxIN6R6Tdj6KJhFiEmhesu1yRV+EmOAVnJt6kJjq
IPHUiyyIguzQBzHiMTdj1ZYaYuR+n/yKLJYUq6jZim7ozXrNdkYukXWrRnLqS6RgGV7YEDQ31bQk
0mCUYCPePAYmeAFXXWFl9cdZaq4Fy3O7kpQXkBW/ti7VI0kZaSlXjPxqerkY8g99eVLjPogFjzY9
ww9zTANUVK2PhjLVtxwt9zHkT2KU1hyNxQJHINzamRZJ2G4YuwMpJGX+dis0//G8OSr3seqCVkPO
GXadNMOGG+2fhXiopWmPf3NEsMVazzrom9aYUuU8VMnQMT4JoG6GqqmGPb6r0iw8ATOddlrU8DLD
cQHXvKmwSOe9a9qODsi00Q2jBfiVhqUUFlcQFUEYAWpZUzCOLUNAQ4l3iGvUj/syhdAg/DsAquyc
txwkD6GBTRD+jTSd+JK2y2qeWwkSNz58u1dRIyV+ahEqU4sLzBx9QG4hvIouwp+Q6ngfcpWo6JZ8
StPhiCNX6JiYqM25dwbnHc/Rfw5AwUVhb9YKZRswJDbwPBqO3Hh2g3zTmbYF824C+rA/bE45oK0k
QhFzYb5xLau4dGl3qFWukS8jZSmYwB/WsxDGdctQ9FBmFNUZ6b0y8g/lYZiVI/fdfq5kfKz5Dnxd
SwfcW8MbEvACcCQgRoeIHTnzS13hPImH7g2JZi4N/0DCIkNdIh4n6vQ1q9M9af8mZOpCRo0r+uiw
KsiSHTcgZcE9FaxkZyE31LivcajUG7Me+sarWPSFxVJQPHhZ2f8leeRt+As2WIVu3LEAxfzd5LP3
O/a7gObtnSTkxetOIlAUaz9YKP72iCMy4moQE7/QAONkDotYATQlSRAb9wTa2Qmlf+zf8opAZPtU
et/xv66C7YHhcEYDO4aHcN7nScGFY9BNyAnZPddl6XjDAq8DVoZNlb+JzXHPI2AVvq/C0r0RXr0S
uYKgonhGa3txITA76Ag03C2O3tzbRYbaYmX6YwUNd2MPAd9C5uMcACwn+1dXWtoZ8Dnjtn/tSb4W
WTyMskBsFMs09GB+dA/Ba1CPLjUFhaNLmlaEPwEJ19VfETPMA/i2JVTX05WmRC3PB7i5wtLWjHhH
WhmC/wQjfPDYKZ+nWsxoeFk99VmyLLJmaftCZbKXYO7mjMEdGvTQmXH4+NrGrgNJ5zQt5NyHAl1m
rPGweSgj3V+0HYFtW5qwC2vaBVlvWQJk/dwUYRUrRbYH4NlVBTXDUNrl7/q4heUPLDRIJRSoX/vx
SjY5oYJzURFJR+TpzTg5IGq/Bypk5jvhDsKCk53GixNQYhulDpxSlqCdpPQ43K5awEd0JpzZIxkm
CX/gImbHXGefKWruMAeyUmy/kiLMVFHPIxdiVt6kLWXsX8Z6ha6X8MXYscBsDolh9lL5+PnfIggs
4QsKaJ+v8JQhCJ7WDvYhoyo5NGuGSvccNovVQIcU/QHKgWa6AdHwKnw1/I9UxYQ/9SIlmNx7c/7s
OSCioG1yiSx2jJZjxei0tgnYynOp9H46UBjT+fqUQ1fc88zYBv+bqxPtsCsy0oOSaD8pKJuXoRLB
0NdR08mFlTtJ3aOefqXPQaRCdA8mAy0BIuiPWuwY9xH8z0uMBju/n9SLTog/fJu3jhffB5tWpGrD
bRFq9C9t98St0LIQcl+A4rYeSz+oslrCnQrEx0R3pKkV6WssMNsmX+cik1JH69zLPNgTuC4lTyHJ
rgIcdJzx9RA0uke3Sd4/XAPOU7yudKx2SBTjO9fuIq11JmXsLpiFRr/QmhQA3PavzsWz4I4HL3SN
YIMPOL3x8bSkX8cBx9XHnrqW+M4QGwMTAR/9Of31hasvFWT5nrfdqXgvCijx2wamljxpTyXX+m/j
S55tx3k88z21Ee31wBsNu3CWojcCMAfOHPQ7aYIsQ4dVyyG77koYmDmo6UG1yMASpZOCjxIZZT8c
WNgIwfQvtPFOTC10NjoGL6IbWWRr//vvAIi5QKAevWMDBAjo12Y55f51hu+xPVfxE7EMDd8XBk2C
Keeu6qIGE4Jwi8FULPwKN07L4oS2T6xX26LvBQCBib8w84U7ywwebd7viuxJzM5xltNqVACk92Az
Tllvi25bL29T4K6hz09t2QmoLG1wllsQgp9XFXBzdWT6rt31JWseWBKKwnOK8GjYSL9mWidE1T6+
G+q+Ccn31bmu9zRZS+qNeeeKJkafUO6LP6uByhQ7GasIAzNp3jA1ZRzcihXIkf71epPJWyWfdWiD
PBtvIjJ056btMqbyBee7Vlia942UE9WPCeItbatfNGqKpboN5frk5qIc6ApjLUgtArav5pzstT5j
BPB9UzR/Kl8cv4CdpYYY6nmMKyQQALIrCRMh4dJR32jWbCjRmFieDUiJhlxcf9oU5c9IB/0VKvFh
z89/lnvLWzO4GIrhFGAv2eVemxeosRBNfZhCWNYU64brIGtb/qRgSj5PXyWduYuQdQp2RnPDWPfn
NLmMmCucFDvQmpGob9LZlrUSZo0idz7PTeddUtEEh3PwM9wuNRZkdBwunrCPrbO/QlOwWq/pxmfp
9JkCScG6CqyzuZWIjC1eE+Jo+IxAxRyWvz3FMJJkkhrHbA858Our38gxxZboEACFZk296JF8qbgy
CvGbtPFkypXioMP4JL6DfveXyg1oXCa4MRUSQAqfLyXVKnIP34ppT8Y/QOIlUOMXzyVUj1H7nXCa
G10x51xFiTLfbM04vK/ySronVt0LTM2OKM9eiuk35sWHdBYTu7s3Lb0ov31ISLKqRGwxHGlz0Xtr
fbnp4WTGV4kMZ0GXfH06TYd/DYO7/EBr4Rv7chTPFZ2ZhmuDgq/fpsa2Ut4kqD7pM7Q8/6oeYBlw
9p24upiYqELgpByeLZRkwjaT9rcuZzsqZbrG3MTfOdwP74t6d3mQRh0biaCJB5L0apcPuInBe22y
h4zxljQD/1JogJxhGyAqQjlIsBbN1PH9oqS5Lb6jywsPoSHkVrkgYn/ePVHaKwvbCjZKlDm3MuZ/
iPlSpfF4tXHxaurOlNYpfWCm6oTKEopNV1DnrUaj6u/jnKXWkpeyz9DfTKX16rlj1vGsqzj+dbr7
EX9wzBYHs1cG92Pda/Un/3Sk0OQFgmbiWOmBo8ppRsd2se+Ix0QcjvWeYM+CnbtK8VBIjh3opgm/
mf6NTL2wIThMnfO4yxyl0VsPHdwA4jCTLDbGngUegVuuCyyp0WxPW//3LBi8zUCagTLbJb9/PmhA
rkaUr64p7siYMtbZ8rA4OzL8ElbmopdfpNU+CTNHes014tm67EoLij5jUkEgYbO9z/LSyLDLv96s
rTVvZhKa4v07GqM2+EO3o2vOlXyNNL7nIA4tkV0WEwk0tIOQrhOZ+5TLRWSGoj6WV7uKCw0c4hWo
W7wO2cEk46FqucrA9naRAVjGp0a6oM5uEScjte0Pr4sGW68U/5SEkUi6jr1mCTrz9aAcKfFW1Orf
P+lsXIQMjDPIL6EhVFsEjQ6I1KOuEi4o1OZyqUm6IS4RsZfE7JoQnxToda45p+Xu7BnoUoF7eU0A
Ob7jnZo/fdDXcDNehkL6ZoONyau9o9Xn023MgZhDX23D5c9l68gFTwyacfW7nOUEYm8p0YzYwa9N
hvs7bnICUQh/1ykg2+27Y3SmSnH0nDcC1iLuAbygzuRtIV9W6ZXV0ikcFyVtVXCYNX1gbjw/qkpI
k/nRTV/StQosF89SGpEGtoMI+tePdsDzwpoYtFjDoAaQi3mCD2EEokJnZWi4PAvrXPgT0O6jOWU5
tmZ6bW8pKfF8s5vj0JgWS4Jowasp+oDxlqqykALJO9QDN10HAFANLDlCJET6DWNByc0ZPp67q3t8
aeVjavsyuXGRHef3raPUmoW4CKBq4g71OQF0yi4sdRR7Qkg+hIoW6K6ylvw8Nv6A7O7uxc/vlkgf
Kfy/+A4EnZ6PsvU5CFxRenaQGHJQS9Q7ZRVU7ReZ7po/S/e5lryf4emXuilAP5nz9b2eZL21cr4n
jhfW+moadtpwIx57lsakT90GRKgn3C+qq1A7JYA+iEMUIk4E2tZKFfQzRKxhTGnKFjAZnh81JecR
Vpy1RrzvCVE/OpRC8glFbY1mWKhRhp4YHbhrM7VWQOrjjIfK3nmn7/BAEbeCDXZmqFY5HAHFRUQJ
TdGKp0hYQxBmfiaMJS3HB3YUzUHfsOm4C9mX3ve25/WIjCiNDbGZgoyb+flTq6Xn5tWvOQ7Ydzff
zsGeZBVPlKBXpg+7AfTKKbyLfu4Xanuv+nwYYN7aCJUwvynQ5EZSkVLC+HBeGkxcm4XhSRxxBRI0
QyhPpX1KFwakOmzb0zf61At9ft1IIAR10VGvZSLF7/0mhMa7sv1QvkOR+mRcBnM2SGNE/d4j4092
ZoSqldqh8EY0rWBS5CXczJ0zSMqa+UmF3eLx50C6GyTYf1dMdW9iRezY7SubixWd9LhDUQxInwS0
zTnkIIzoeW8Jklp0tbhipoZycAdvv6QK5xHUfJYqsUW1Ucuav5Z9J3ZRRpABATmZM4yvivrhcc6a
t0N3dRLvOeGtv7LhnQMJmpaE/j+Qxgu3swpUjmkZDJu/g9NEG6Lie014pZtiSj+lvzOqSCvbQ78L
Y9rBL+lnSUmp8YtSnu2CYUSblZ/Tr0Qw4SO2rTfVoBpJqkNXL9+z8+ue5PYi8hzPbr0yk9whAo2Y
7LuzpU42++qocWJzOLxcsMvbTmE6UaVm/Vqtvke+wRGdBXxYg28ZKl6oxzfnIFa7sjYTTHtDFTcF
aecm0AQ7D/hZFpbMefPVfm31fioifeZhax17PAFPzW9QbWYZZY3OWkSAAB8yfV3bMTwKffmvXR9u
zsW1cohZWRwIjEo+fpjVWw18FDZEbBS/OLHS/XjxIoAP7PwpwvF8ARh2N98mq5/FI+7bFT3BJV3w
HHRxUuxF5F2lnhL+FY81z0pzQusz9SWvBoOY/g8UCv2sff9y4NNVqIatdW1NrkrTSn1CSy8QDRcW
Z93o7vd+Qxle44xbJg8YJxFOKdS85yEbLcVL4M1zfLwckwRyZwkfMGdZ4tx2m9LYJoCa9bWTr3zg
LCsVjLKKvAfLlSeJrhwxRc61mpqL47evmZ+DkIQ4t/pJb9Y9awIU4HrcXPSJHUsGyxCWEd182jZN
E8MM/O20RzdizRl5Jw3+tu6okwMaJi+cv9zQ9Om7N6E2OhokjX7kW2S6IizmI5TaycqCc9Uo9vHO
838g7aJFuKBlVELV5cT79DDnP8lGKGOqY+AEd3BR5yvNGi5mrw5NEDY+Wj00Btwr3Xqu8EOG8BmY
BFxTNNsdFf//ypzKk9ORRF3R5rQbMoLY6+hwioFpMHkbx3CAOxdVA+zy/1z36Fymk2eP9VlV2KW5
zh+Q8wCdZFifIAXK60DgtPI27zIsmRQbgaR8aa2u8ip1p2cy6YYrvuDpxgSCHnlt6mTrR5I/WVj+
Px126nvKC+evtkOvuYFTXoIuYiCnmpnaSZqL3kL0j1qk5/iuGi584/Ce8b8lhkhOnlmA8jJLSyMA
wLbQTr61GwopkVLlRcJwrs3mFLgNE3YDa2/uIkri/8kVTKdpy9OmzvQ7df7v+p7mQlcVJH2cl8sN
Rm5DyeQ3jK8bAQM2A1iF8paYDTZEy+fDTDCEY2SyBM/wlWvdi1HqsJBJXWH6/WFD4tu+aOqi6T3N
WVqp+eVQLzKMQhrVQkqsNuzssd/GMofbL+XbSufWcgFLsbBm5nf/FXFotXRhMn+HnKVhzxKquRZI
rfKykmxpB4ioYBCt8eMkI74UrxB1wn4vQ51nfoiLtYlh6RYc/bRRNs5MECwATOPDlv7mI8n1ggUy
zOWGENPDqZQNOahTUSXH73ZFStGq3N0MMiQn3J4JxUgq6Lv+EQ1qOJmpMuYbGJp6Sjlq/55+NiGO
FSDT/m4HHwquxqy1NRrn2SJDmJhzut6Z+ImhdO/hvgTc3gKOI/CjckCO1Cw1c4v4n27nPxrvkdK3
G50pYdgT5QW5uDJQozZC8n2AOi6amrNEqy7EgyBOMFw5m1PfKGwfPn1aRHV8NoK1+tXlP0+PpfgM
QSZSeYeweUkHFrXsUFxwPBH2TSjwmbB+MJqi81hwqTbruL9ZnfzDB3MNNzyXGtet2IN36b7ZGSUz
MGL0YhflBmoGDkegiZBHPXCDecT2v4FEmo7E4m/dwD9rEMNKtHL/DAv4kMg/NDntlcqRlbLf6U4W
355hld+3F3lCtLV/oPOx9Vtc6oXHh/b8rOIYZS3X4EFNqdsQ//UWH0cmOQT5MJOfrEhK5ioKp+Hh
IOcs2SUM97D4GrMcsHhZCycxtmtAzJRt9kL3FbHEV0wN69H6K0faevsjQTf83TiztpeExBreXn8H
5OxM7ipdXR0R+bPxnYKMJDCOp42odeH4YtcgntV2zYLk6FspOuv8IAuKOulnyRWdN2qcufXDdttX
PATF1alYld4E4gn9dnnbeqXtz+RTgIOYhVD96csH9oivufM4axcB72RnE9Jl9WQWYOOZdkWP8919
sqwsSMMxTEisAoFm7w3pZH3npI1WqHIjKQlNpYEfAb4R1hOJUHICKn4kbxTSgMmTWyroRK0iuwIK
8MeV/6AZhbTHJoJbytLbOUejGeVvTjinP/Cg79qnu9Rk1TKVhxo7tehiB5QqzdwjmAUbYadQRCNF
zXVV92hiIiUFwrrrDs7XSorUKzPKM5Pr0ak3y87wFfj1SfatyMLVwvwazk5r0YfONFdBARCZtP4B
yVf14cpXtzdzgWh43y18Lesfhm2vc7ic2AVL0VnTvnkyBqe3Q8OyyjMjdkapCbMS4s1QjSpugaD/
Ybx6yZjieEqHxxedUcDjQoTpUpECkPeYFDlKqedpDtw6lVpYs4ed6xPx3vZplSwc6ni8KmXHAq4v
huCBg24Ew1lJTZzLb9K5/km+V5llmCDqQsnAxBahaEkPfyZnb8vvycwvhA+h4j5Irt3FNKXw920s
LkG6YM8UnRNOEMSUBaFmzc2pwAS4RBPeRHTs7GlV1csxNChO8hYxGLut6bSVlDxtcX7ZbV0gwZhC
6wYc1zGDXRqZf3bd+6Doi77/K9ro9sEZjyw59JiQ5mlVp6489SHacLVs6VeO/MzTc+dU1kkaJ7xd
tC+bYoXB9zXBLAo44rYMMY/vg4MuZkLyw8n+90o99w5vP5pqnc/0SbgHFqYPktgQAezV8YVTE7Cz
TI6O8WacDaZumQy8Rul6Og2AlkFz+95BsaOYAwyXs9b1MUcH31Cn/PT6RM7nudiERGb4f+1N/IU/
WhLw/IdeXm3WVVsH+8nFERS1f0BNYUMag9dA53P0KosKAnpGDGTMvXRTa61e2+wWmSTC3Zx89FMr
S9RP4iDvUaj91JSlnc8hoFV1+tZFFEn84N7tGhTngCOFV0Ofc8O9vY54FCqRirfHzqmWtACxY007
22LDL6E3KnYJoyoJ/X6LVIMzwuw8bIBs3lXGhJC/1Vw9GdPG+2I0N5zL2am9wUvuDnw0kj9F3n9s
WQH3YXpt9jLxT3cGjYBUNpV+QPwD9Lqh2k3hX0Jz4dNmXvT4dd60dhteaeU/diZTv09/BOOW/Tow
NQ8lydmjilOjc1ted6EMM1LPtO4ezJIqeHjacjXrEIqG8G5p+o5iLe4i3D48L8PqTAfufucQ5BQq
9aAU/SAQ0p+oLgtRV2TihKoYqzTKsT6pfulnoK6kkWcu4a+6ZQ3zc78TeG/4YgYMO0POOgwZyhm3
AoE9v0+q/ds/vP2HLQ85sZy5qf0x8gGZ7wRyr+sL1ZTc8trD5nOSTevDlmvrB8ArnkHSeq6KXJkN
dFuij9YvWD/exLJT7Ds8I4JtwLrz7O2DFnimRPxCLQqo1Mnx9z6G9EjAm1evRIjOAxz7OCDRuPgQ
7q0Ry1vMhfpFLpKvu8USD6U5XhJXUYj+Y1+VjM+VIz36u/icaJV0mmOKAI58Mq1cKEvmNTcFf5ln
HIwc4qn7R2grQVH0ApOCY7RBVlQCcT8T+pUC9yqYALKM+Rd2bqO1+ridsySWv2B8Rg/E9ndju/vV
cCBurgi1uanYTwgHSiauaT7EWlpx0vqaXiOnfAeshhE/MvZK2IZoE7sVI+tI7+1TgdYyKiVSv87p
uEBeyBn8RuzhGNZRYGCfqTH6JPK0CaFLiM4G70W6SW4zLhnV4WES44OpjyD1qTuvM1gwGsYFbJz0
PnYjjsOfIU5TWkeA6lreKLnnuKVeI+tRy4bY/HIh/j+7ShFtsUqztkuM/J8QE9XmAZRz7P/4Cb5j
Qw0VoPNjbA2eI5+tYc9bnsDRtu+oLDRP401RjVojNV626z07aM7lieG3LJMuo4ANuGek55tDMdn0
VejK5jfqriBJaHkJvqGPn4/Hih380346OGEg4bGdxJ0b6k2Kv5Y1IQqArYx/lq8GoQMB9lCS0f6v
VLoKJtl+zEaFHbGlDiYxy/aLBouk2Te1/WKEBHpy3RSBFY1ber9dZkdXk5E53RbccCcxGY0lU277
X0MzOMUTruWxdc5ZRwxg+M62DE0ZUt1dORTX+41hTKfmKcwY7chKVGqk/YVLXIFM0st5C+ZzqU7F
W383j60syJVAAsLn898sWzGudgMRSJO6BBOLQmaOkWpFIzLaVaXtKwFWRSfw4+qIOugZfilWr2JS
jl6MQdlzTzKveOWPsbojG7vdqedOZswd1xNQv/TPZJEDla4qNlod9WYfZLu9HHZzCXyWn7GUpjwa
2tn6l+7OSEtRznydbzZDlADdFrXeM6xEaigbZofSche2MoBDJfZQE8MQFw4I0uqG2W5sYXo3mDxx
p+d2XMewIB8ULl01bMQMYortW8Bc7KTIlAKm4/DOZVbndUIa7VCKjqD1gxby9lmRH9F/SoIHrqQG
rLhOeGz/twEogW8+Roqw376AcpghYcqBYMaUEqLeh7A2QTFVNAULwDxc8ndX82b3rNC63mzSKPst
1HCILR0CiHoSfyPmF6VYFk1PHyb5SqfrtYlrz1iGzZmRUC5LAynyiUdbhQBQhPa+cB0DVl63H7ug
hm9ij49P6sXcqA0jEF4oExnx6lUNssrl9Zv7FjRPON5mD1mqmOdO3h6yCK+4BgLLmTXZW8isTk32
jVX5wYimVLKb9UZmvjnnd/I0ZPiKltpVCS+hRv9pgRw+giwhmOvDVb7+oQHzfZU/OGU79JtAfHh9
fXpzuM7FFP6gIyrATQCOrEwlLeZsJ/mPlrfzI3XbJz/i14gKE38dnTahInXhe4M+GiS7YE2x1QrI
dBAXe/llPEYpO6eH1MRKX/EsF89g0KCfTJKjU3vEMojfJinSB0UyJMmxajgTGJsvYUk/MAqa0cJF
ovBfsgyPJ3QwbtyreGS2w+A5ii8bW61JD0JdLR5JOODDM/XaBQVWMlm0lqXMEuI52TDG8PH5bN8Z
eIi8AKwBvVDGBFHA7f2WC352KUxKA6Y0PtQcobGFguf1dRisTxZv7zi6mbr4uXLfcjBbhFY50kIK
w5wh/XkONzoZlbhsTCN4Y6/VQL2CZ5CnxomfYAMrZkP0duMosfbu8XtKXg++6N7UHdoM5VDHF7FU
DAQkurjFAxSf7YfxngrPlPvtQIfR9FmXFm4GInwiDDVlGPsewWk6IGBxLpOYTG0Ey5p+Xumi6k4z
6ZHz9fT9+aAxvbTnBm825OWgn3+Yq3W++UR8hb0BkJJT4/vBCNSlOjQ6v+sLkE1b1uxFnz2LA3Xy
CDxRIxuJbId8Jvz8CxBCbvdJgLD+DM1hdK/8nGRCyEPrZeYGV3PhuYmGnDGgC1kto6i2v7Q6TGcp
RYaVHlS9h01rwKYWodOPTm4xIriLCd6Fz7bIstM1cnNGA/o0NTdPP57ntKbUgQa1vepkFtGl0oY1
oxPmCrOtXh59L4q0F0FFojtM21PV019tmEij+stoM7gxEvoju1zeYSqyIjL07M1TJ3tr585p6z6e
iNrlSekTyPHk3jbELVFESZOxzDMtiYxSnQ3NxE5JnM8Mu84v3daEepSg5hIqpFO+1CRb16xgNfJu
vu94cyuwCmmHX9X/ioVaOjs+x7VM1StJM+WjjhZd/iO9G9/cT75layBcmQr/hK0x3KMDXrkHza6U
BwW0lxw/Y7CPESLexw4a3Gr7jSKH9LrLFFsMuYDjsZ9U0sPH5y7wjALH7H+WGddDNbKWAfnCh8C/
PEB3HKroRwBoc3QcpfHkCpUGB4U9QLZmcrGpzPUp/+YqXvricsFe8ggKOJ7uav7mwf3ijoget4RH
24ITha0qNhRm60cXLPus+UvN0+jxrB+lgBExHffcxaDGaGmfeeXWFb+fMvqBUMuVBAVTmq2eQMiK
t4Uyb2n3rTa2lTONGa67MF4Zwz4tHi8xTOFlYEruRhvee4cAJA/OhPCUI/tSfDklQT9UNCD1s6rc
i3rkYTxnMOHM5p1wMQJKSOvM27oEdn0Y8cx9zLFNbdMgesdNT9gukLuNpfu08vJeonwCir2CnIgO
JTBwRhqs21LaDdd6gQMjimW3dauoCvYEIClkdHMcjoyPXbg6m3GshzMb4f+TdxkSduBOdV054nSf
qYqFepyxzTuN1gXSh6bjSmrAe74THMWiCeCU9rCjIrw7uAX7oa7ujeBgWdSgof7leSG94sAkGsO3
B/lBKnwHGLmv7y/3ePcot6HoXhyJk047iWz15UAjV24E3IU3mxHwIcYHFFVbgxLKPiod4ZNtqT9u
HoFKJiW1UtrfX/mX37tQH3Pp7XqYbF7+4j0ClogvpUCYLxQ4uGqbMNlzhyaSPrVKHBeOrM4pRT9U
EhR3rpElMOgbg0RcvB+tqbq54LQ7rVXszY34/MMuXtgZe290CQsZqmS5VRDhORrxR3T219jzowFn
v5fMhB3J5mWNi9ugu2JoPB/KkduigmhaGweLkKXyz/RJ1UTd0VV6QaD0bO+/8A/+1FrNd8+6tEqj
RetKbxE5lZ9Lqr0EFVAF48TA8/ldJPWzatmOtO37Bhh2rNQX/Z9XP8190BZZllndA3FiZjRsgXij
3+ZGeqDAMmzOishvzi5A+qdH5Enf5VjdMY9orB5up4zL+cAel90SH8wUnx0uu2ShY/NwCOZYLgwu
vpV+dXTedTMDvh23rWexiUQ0siDBlUEEFCCcx5oGtKJMI/Dz7FVqLlDRc689hLErzTonbfVtPUU5
xKaUk5+EYLQFCq8W6kG9Oeb5L9AbMyZZcnNTZHy+xlVP77gqLJtLuNEiuVoTmtH0hSi+QoYRGaS4
B5xsGFTpXH+ctae9bRuCKmn1WgVEe6dHOBGMSm+RMg0dbRSc815p4G8oCWYQIF2bzQvW4yx1nNUa
XUqjN4/4Uo7DHjDVz0+8VZOF5zTyKdccIlN5ak8ooM039AvL234fkY9KGE2X+eyKjqBOikbheBPf
wexjCp09+dbgsqspivuqaaQxocuPXGKxgkc2nqtcdgxYOq4DLWppxBA86itW18HQR6re4IdImG5t
PG6VsGSK5xim2YKpZTFebZFa+VTI+Y0qUnqEXvjH3u4SGXJOE/N3MEU1lTTn5cyKn9bsKNndK1/y
BQfRk2zopymVkNqxaOUkGCk3Y/SheTGpt13RJt2WKsRzFXn0EAhF1VYzB+rdWWC6AiC5kdQhOFyW
RwoqZ5Wu1yDCI3BmKlZ+mLcQMw+N2BLVnnkf42hj14yLIitwVX9d4afPGay83J6AoU89q6RCe6c1
98Vcctk8oJ4t3tTzDKTJEV0ZIwJeCSqX40GNDxS02wuNXEnurLVgknqHGGEwquy/Hu1zuJHnejrh
F5WuITgryfgJtKeTQHtQ1a2CZETbZpi79hQsHccSRix5ikiZnywH5QBTZtC94If76THf9AEjt29d
YKnjPUtI353e63mKLUTjgIKMFl6E/DwiOvX1yxDsWyVckQ0EUvSueelJHHUWyy0XEbBYXm+Jp6Eu
ls9I2+j5bwr4KkDwjkVAY4odhYZsHb/oGglk2p5P/Nl4b8y5iExf3GtRq+WtPkcFhcPs2sn9a3yb
33D0JUr74vn78zvAyEjjYEAEIoGOgYb/i03eFGZTJ3Nq8yFRBILE2q1nw52Qk3O96syS45Pi7FSV
9GazCCmnG/i84IP0GTE/JTQKwrqUkgQtIbXBcPMGFI4xTjB/yxlX2DkvU2viUV9Ofr6YOMM+k+J9
4zjQu6SOFtZNAHfYNhdJYPDeEX0WuLjaMU4+CO997HKemCbb7yoAFr1nsZxilHH4cKcf5y4G8vBA
5pCO/dhsdvn9/apvpO0Wr0VnFUr9u7jkMJPHdcCDVjhPE0PDR7R/EbwAsbAx4n97hcyk5Y7gnr3t
uDLpSEUOIAiV1lf2cOydBARHvu+oIg/U0Omt+cRXeRd0n4/EyXaie97HxM+8D6QWCwukEn/OQngM
rS9zm3pGUneSbZERCZ8qSYQF31j1xc5e5X4cHT8FbRLSGrakf6Ei/AeYHgkoigp43nnd4hMtDwh1
Bg2cVGc8kE9UjSrEe5E90SQsT7cpTQk5KKhwHdUqFqZ1VBamk6syKnArN7FkSS30sxUu5XAOlqim
SFs7rkxfLc19K3JTask7rFiaB9TfR33BmtvtHPdQqvdtkZbFiRmQE83WZvEVkkA5BSts8qMj6aU0
5fY7oC4Tq1bI28T/i0AekulhVKa+2qztxqsWrEBBDnXwf2lp7bdDNiUsOV8QBRwSzPR6LEM6caAF
o1EcHj22lef6LZzwdVWmac4Z6QaQkqOO+0pc1F7GFOsyLkfveckHZeG3BHb8HKLEAN2wAsPuQSIZ
nD2tLEksdI1hU5AIIqA1SHgA55Nra7LDmPcgtMe7FnBd6gp4QGZwmbsBnMZfvhDHrjhG8aC2ZAqp
QKeTrtUmEHjv7JPY8QDri3IqVjDZ4vnftLGtOI0/FimhOKnEtaJ0hadx3TSy39N2CNRvgsx18vAg
OtlfaBi8IShQPBNXJD6fvg194rrTVbQkhby/xHsdIHlAKznqPArSsCEqG6DMQQwYpUKnE59CiDcF
f7iJ1+0s7kvypgjWiyk/jv2T8GpYbmHUZoYlbPCsGJvBZ/ZEHCrF5t7JKeTpVoqXdh0pnkfOaGHo
sLNmXYrOUDlkwtu9ZoV5Zos7boogzvOthPnArW7phHrU6Nxyaqn95fXsa0iAwDoFbff4D++MFJ2t
UBFuujBpp/WKrw/86Tc62rncQmuqxWc2av6R0KuYdNA4fo+O0Ui0pz/sG5npKemZDyjI7cdWQqR5
bkqjO4n2+8cB0QC3nT+EUjqHx22Yr6E6R4Q2yScHgIkINwqdy2vfepQyjvyADtBOc9uX7nFSFkkH
WuEUFx5s2A47guzcuNueJmbhlCGMgYLBK2yucjNHqFrOacUl8JVihz10ZpukrGuq4JXHLKVFTsnQ
aSQaKyFgI9gGM+L8DVYfArH6Wxpl/8c6+0I6aGJuVwhPl5vK8f1P1WyDzrT5j9Pvt4DV73St4Vmf
WqgO2ONBzf+v/hFVRh4nJwQE/Ww/QUNT9Jcd8pDrEL2K/mc/PBj1q0CBEcc8Z7qdtr5iAIbUeDLU
Uwp10HDqb3qBCDBUV4xfWLgV0g/jc8y2vhaNeTSU63qbmBNZbcOxRkpumvCVC0VL+moMM4ylnd47
+fcHA1UdAp3AxoBT8Jf/+IJazJ0wVdWXIp5lfLzEF8oz8Ph5IriTj4ZCKcZnW4qRaq5dUkf0h0el
2oVkgrXuwY11qr1BiXHZYrTGeeUYZZTNgyh/7IvlD4V+4G5gprndoIajyYlOOg92atZNF6J5lme5
9a66n0toVSBX6ghGvifPJvnJxsS88k+6OfmKUwPEjZCv/MJikxzwvD4CfeoTL3iQ3oSkX5K3ypuq
DRCt8VP0R9xqhVIqzitWirg19b44ihX1W5KsJHBjdcaQ9iNW4CZzt4nIBlFh6sVf7OZz0H3orID6
yI9YmoDdltaFQyiq4Yj9DwOGGT8uwP04eD8z8Xi+Fp2PCKMFre+f/oYoMvVlcs9lI4xEmmGUv1I7
oAouHhTxiR+2i5uv41h/iHbVW+pV5xzlznuyZRv09Ypqsc9C59a2vZmVEzJAGffpDm9nnTskxBPC
T4MvI+x2MPZk8zX1jGzhrpeWF+GIaaW9BKltj7+Sug50/Ci+JWC9zK5qT+pEyXHfEAKbpNWeqz66
jfGQ7pfO5QGsMTkm81z3Zc4ra7qHKEuI89VHKafkQ1PeL2Lxg/gTn6uXyPF8eT7nIhbe+1oL18l+
Tywbi/F47TQcKA2iBDCmjCo0Nsa2a//39wxvflfqA0J17Ch2k7f2WpJAA8Ixtj/gcMcXKKWPBTIr
w1I390VLW2Y8C9HLckVfZRcmN4+T5r+vamFd6Q4ENulxQkjMmhMm1iZ7pEHGllFfWMM0o6l805L1
vhhKN5SkDeK0m4kK0WQb7XrL1Ph9fDqysAXoGiEkf2znM3dXw8T1G9IR/w59sp6umMH3YBcEhimK
oGcNrkZHgcTtQKiErMipww+0HmJz3hTANrsn6Y3pxWcjE3ZhjNYc7D2XHxbgdv+U5Z5Zzn8JG22K
zsN+eMnyL+SytEPw4bmODQPBTvezHzvkc4aG5NWAyIH6XFoBa2O6JXT2jznRpjc+jb7nHlQJ6ci3
xzVc2w2K7/G6BjN7tV+/LYQ69oQEIaV7K5SG771QCDbJ0XHXpiG/ZM9V8qHKTsMHR4rN+75fO0VG
4TyXLVYmN9fdUpGWuJW1nTqLtQylOUWb8G9MIzkT8JL9XIsXa6mPqClSVdhntOKZ1QpIokXUdmaf
kcbUxuXnMdRuoAXvvmr9AGN2t4fQ/XnetlgGqCeKu3qBn+4JnIxzKtsE6N1/BHmm2EGCeOVjbI6C
Uhv3mFBmSgSkCWmDqk99e0sCGrTD5LcnzGnfsR9Yu84tbi0j+xnqumcafq8fqFb9HRoyh5bzhRgd
eF76m5gHNlfTJ8Z9qRhH7+QovETu2e2PD2+8x8DePJKbA6edc/nrUXTTx976WAH4zBSasUnnUKM+
3DgJOTMNl5SaMf9Fe2wlTuUeUAeXyNvouOxq3G7kg4FzDzHwfDimt0R3/jbp1/LMfHxJQgbPeRA1
SeaRJ7xpPmKWuQ4cQgEWH9BPKIbZRg8j8s16H8hnWc0qND34Gbos9nB2TYdFAPPCD8YO6NZWdgSx
9xAdVCkHWK7TJFphTHhBwyoZXT5iNc4jZr2ph2S8PkBUjbFXGxSz5h9NgN4BhbRkCWrO4ZIyXpro
sr9EgiXWD53QJ2WRQgBtVKo90swYU+NC7HxO2AxP7pI4nVa8K+CNvP0H72B+N7brwgtz5mtQV/YU
4Ya7fLomJBRn43e/dnGh+Hxx0qL/J9OIrJFLjj2b+0gZzoxuFaAlA/qMnzy4OMuwZGdRFnT0V9If
ihhPX/ZjlESM9ct4p285S7SNyaJ4PaXLc9RctUmw0m7n97qupbehEZIUeg2Hp5sLBUZYuSEXa+6Y
fLnrCMOsusCF8iIwxRKyrcvWXnJe9GAcc9B3uQyE+zEK5PBXd5ILOHvoxrE86YLYvApvGyLZCMmU
ibhEoX8ERUD3VSS1DsYuDZKKqBS3Z9yeGKc3mWvOKsOS4ysJuLCqe8wpjp/9F/DaHKat7/mVYC0p
aDFwcrGYCSnzoidWkPXIPjOEH/pUAIj1VHKX/iNysSUVbyQPsB+9xD8GXtcTD3H5U/58yvmq7Erb
AUCwZon+TmbGK+lGfO8P/V8psCdK1HOM3IhsHqXIxLlv2kzxMMZJiQXjw3E96Vuj7MSY+t6DUrIl
u7dK4CFf0jQdzPycO/Ampu/VXF8FP0l03LvmS28s4FmZfGx2AiwKnrnvp+P3/gnVAAwiHyJ6Ys7E
QfO1rkpbzpXdE52VwZlKDmxUTWed0oqllwHOaPX5/QRFORhmj3y0IFmg9IWU17r3W0uRw8Ts+EHz
D9yWi+keHvUQpeiNH9u8P7zifjEA/ZUM0yPGXduFmz7BtbbAnOSs/hTnv6FULVee840OveXvvZHe
c/uivDza+P0uHjO7zpgL3nWCOywP80QpfNV8JYzl+mnzgCmQw1bH56VR8A5vn7wi53e9CgRx5OVb
mmUViPVyvIZUifvUSxN5JS1UJO4zKOHVqv79uVwIUuOzNuVSPXwEu5+KC0l+fVo0ilnAmgIcMybS
a6U3WfNeCn3Ppl1YXc6Wzmon/0BIByC/M9T8MAVHZo6u6AF10kwzccw53kxwbVkMQhQJTs57vaAY
4qohv7tqbC6QfE8jqlCSKRjWignXmuL5z7K3Aly8yHxXtd9RejIlHz8sGuTgP4hAWyKDWC0alK0x
PXqIdCTSspruhAL7vtqKaX1F+Tn0/Sp0znoJPdq5+IdiAKIjitjzcHcm+rKLTTh/5OXlf+xa+Ns0
5sCIr02RH8Y4RU6JAAZ7C1zJXUTu6xb2X/rS4d7uhPHTAX9WvpFUEWgwI10223RI69yYNx0e7CiS
ylHiAi8Vwz7nvmjAPk3ns+M7xKHcUj9b6mbxD9BWoVs3v/ULSfI41iIvE8swCLDu11pX8ArQkeq+
JOkU9d4pTOmsavedRVSLPVwyoTn018ek1BgS6gwQ8ljVrJSIF+ZDVPoTE2+ODIjclZZuRjZ3yE6p
cSc6fAQ6xqzgQAidnO3dA3iLb8N+OQSsOaL0UmW3V+iB1upPxKPFvhZNoFWbTLhptogTTAAxup2F
PKeH2qMHonLF8kp5Edeme5/j99z96fcsTUI8xGNlKx54e84B4yHJRU2EzNOJWnzLXz5QlOSqUMVc
uynJ2BrvrYQAO4NpXvfX0+7tiyH3z1jh4q80kxKGjUD6R9NvJar+wwpfuoZhEUOqRgrW+WNrOyLe
l7MvL+rOXYusSdPTdJijmYE1uyfbc+oij2uNPGxawgpNmajmZG4bQkpt3VbQyafOSrfYGZT+jOGr
FuhmmYlcgWyw2fIXScoI6F49lHyRuTs4LxQRYLc3TAVeJkRizhKDMKTvJk5j+xpqXoyP8wAFAjzL
RNujgxjBIlnebgCp2l5zIgtC1WC/WROvO1hljD1szw1doeshylBfDcGxEEFHYh1IP7Ii0lB12cxH
t1ZF9coNEjMV3MjpmvJAaAdey676TxzL/InkznF/BLcqCrHZ+Z2+VKKIZPS27ZJOev6GlJnv0rUr
GI6rInlim0HKG5hx5dlXqra/iLsD5Vf4kOt+Zk62fECkibHY/wgku9l2T+TP//8XarlvAtGZCt/X
A4r+yREdv0bRoU13Jfh9WtaLOjVRAcDXO6pz1GERQswl6ZooOX/stZ8oe9FPDcz5OfVmMKTfgDZ3
hhMDDA9AgVSsqGu7xVTmDEqAYEMuG6HxPhdEBoMNobylJM4Lai9ATQOsqO+HXCnMROdlDr+m4FUw
1+dXfjIGajnzgje9Au/wrxzfCp2jFThfID2jLhWZ9IM6lM+yuBLuM+SHj81r4JumjB8TEG/otQck
PDyT0BT9UwxvwS9q8qCmZOaRqGYLsFLc+38XMeysCl9y88yGYqvI3D+5WRPWIE2qpxRZqNxFvsTl
Nqy9SFmHb7IKziPr62rb4jw7+GtkMZLIccEz/2CUtUuvsaECEaquBWz+jJN4Qq2k7TyD/sHRCJB1
hQ2NSXMl6Pb09WrGFkCxAONdqRxnw0+uCQqFDmiX6CntI3V+DZgw2dbL8s4TNrna8I/K/aU2dkoQ
+fV72JSW9KeTscLInuHde4EJVIXJZyCmZlqX3MxJMjbK8UxEYOYiqW9FMX3B5VlloB52hglvlzeT
RBnglvXvZDSMQ8RhEe2jhxjtL/sxSLexQH+cJvLY6zgBMfsNFX/018lXvDQOAy1euM61rjBxaRyj
ROZd+d+gJhR1f45KlUQcDclPTAfhTe1+1aW9NmFAg+acaKeHd5nV3Cf9pCTuU4eZ0Ptls5TmW97L
DZnRMeuTQNyUbk4/+UxwLykW8eLkBhn7Q69DjkVLyTVTkoNj9K+fNcSst1oX2Y7aYlObXNte1gND
nQCtl1vJDf0Rwl6eDvbgHs3dEFL1DvEshjpp/wUAtl1MIpFIBmQ/9BjS7FvgY2BheGfQzWdNf9qj
hufcUmQY9nzEXftLpiGMOg3yCkUnc82co9cdfllLdi6pBCx/bHWrE8YeepcLupr9I10PVUWaBIMP
b1/FFaYuXEIT4yncpGuSo3A9HRYmLso4LJuN90Sa9j9ClY+FbCcIenCmJo2ZDkNWmiRPi2ylQSic
0GNuJmNrkUA6WO+sYhI2IHKG8mEc+XOu4fVR5YpLcNAB7VnNAqAaVHsYigR0Rj97unZvdmHb22mH
x6yXGbOr/9W803nsyF7oMx5CIRyg+o9TN3nae89dimiguQ+C/srB/WN6JpAF16N56ctJL4Ds/N3k
6/nQVVnj83GnLRDriKdgxPkF6pMFVrlWSzdUk8NVXeNf7qiABoDnFtECNV9pzk2Dv8WovtnA5bZi
iQaSbjhzJsM3d/uV+D9mrpLNhAE8dLjq6eqZT1gQdSmXB89BLuD7K5jqKdnIrt+0xqQqqBteUBN+
ncdPNDEhBzHgqLPCWkYAbTQMDXzyJopsA7pnXiECrTn9bdQpUuoV9fx8nhcN54huehpwSScatRD3
Y7TLfkSulFLiIPBSQAGJOGpuzD9WCnFFL27Yn+S9UKw4nVh+7rV5xSyCaE/CaG/vzu9Ga/au9Hbl
qbRV7ceZpt1dCy8nFiGTL6gun9qaQtl3raw9yInwZIKSZybCTbU6SK0M0CfnLDAZnmVeA3wDIDHN
zThvgBW6ppKzRqFyiPG9F3eayB8ki5S4qp1FATWuHhnuSv3gJctFtrCjWiRmXxTMB9YGp9MDFAQ4
TO31pRRFd5/n6Cs4ashjZ64x4hfzdrK63TtTONCnINnI6MDN/PpiPq4QPRGZ2aHkt+8aefr4yEtI
Y+aXzD5m6zj2wGAgk64X8/l8KxKTV750WiNldVcbWIYd+d6d/8ZyMpRaYEIIzH6HWaDdGf585TqP
2HE/dJUKgtqPbYmcANKF6j4JbzBAECFlzmJvpWOdwkBLk5zpmvpA48HDI0liH1Lusf4o6Zj3t7wa
sOn0Q7fLwulS7lKNW4zjl+t/jmVYfpZXe2Zd4lcP1gVOYX4k/DGhWcmDj2ANGJRxOPUAgTOdls29
zBvRxoVlJ8eRBi0iS911ivYrCWcAnlpspKnRfAgg0/W67FfQPt0VW3TSM0y8X2tVy/xewAlLhzBn
UYvVdAi4GJU7PYhS2NjwISlOp8p8cA7jC3fxLd1wSw9lRiGfM/3b9tSi7V39F3FFM2TzvsLr5qEl
Zh7ZoVvPu1gzIioq8jyns3h6zqu9EOjF9mABa5epmPJtL3oaFJbcBjtQFBUuVT7wFp4FeBHx3bMd
dF9QfKiDqx6xery0gKEs/+9v6MWax3WqnbhFOQJGs0Kl8BWpDspV9v91ROzu9Hjc89lehB1HyoaF
oHIP1d/gMIAq4diQcY1ikypxozepsfb6QYCnBxIs7jLd71LvpugUg3sPYt2P9T8TSv+jtVBPjSuD
8fVKIrXwQOOWnAh6HiLBR4kqYIE9I3G30smUu2NaTPZhP/pVBFmSJY5pFtbzlTG2l+JD/xeU6Jl2
5p8iJ7To6ZEXvf9ybDjXwhk1yzCxaA3gsutN96OhOafTcsnd1ZN89uTP6/cNVWRp/AFEuzZ4gBTb
Lc/RICsHtKLmZ1cSokp42UAbzyY42aQKQjhympTvrpVml5TrALyoRbfzCZw7R4k3hhTvqljJoPS9
ArDZDwgMzhp6uDADj3X33X0tAj5GnP42iwlTNwv8a9DJ0kdPlNB09XBV680RJgH1GOwt0gg9EvxD
XOPuO9jenR2mcYJKBH9cYThRRvLl5I8ug6U2MMFsZwzas/gruCMFCiNNCs+VIjEVtnIkXTQ0CZ+d
q3AhzEYXjE11h3ahiXKCDa5mj+pvrkmqt23ty/hJoV9QHamFTqecVmCw6MnMwdeCV1I7o7AZ+EtK
g/qzBfA6i1VLT3TwyfUwgKyhQuseb68CwYGMrTuRfpqQf9iR8j+8F2vCrJomxdatZVlKuKyzVaD3
tnZzCvFKlDDuSnTJ6uyot0YBxaItYB0d6X768/w5TT5CHH/gbIuJl6MwRU+WCGffi7exxEVat8uM
/JSbt+GVAt3hatdyA51/Ahw2JeFLl1vzAIbFpXW44G579LbwiuZh7riC+Se1lR8pdgLqr4LB/QWa
rg19mdDfbBTAbvw5MWHhjs1tEZKR31ZbojR6dXtRfz7BCGrFAlCmfOTkCf3dL8jmX9mFfVLIIGib
C7nFEZjEX14eiSrhkOB7GREyM8XocqPFGupsDd2RsI6SP7q/xadjr34TWtTqb5PMoNb+MksO2QNU
x62IVi58RuhFZheWGSYKUXXvLivtN+4WdIuY7W6kOsQ5R98I7v9U7b529CWD4sd/6eXV1Rk3/O3l
lNu83OTRlUTh2d4obt5IAfUJTIwx7nMewoPvCJaudRnAtIBaoQpr9YEPpn4aQIybVOnnut45cUV6
uYkeVdH7pjzUpe2S6GMFQGvSM3lhr0sbl+MGsEFvYDvJ60Di9ZwVBD6xPOlIHVCESdpnj1CpWevT
CkcwsEcs5Bh7VSXh0GFyR0Q3j9U5i1kIz6XHCnKUe7QVvlpuX+FYigvTPlTEjBWY3KbQXAoOuM7P
jyBKfVt1j0AcjLuyNFUaFp46QV+fAdIoweXsUl9rvTrS7prkEd7PeWoe5OG+J/Uha/gfB0ecFdA4
20i0ScFgrTV1s0DDnccHpneWAZKZTZIfrL3LYr31W2UmpYc6njGtAAaoRrKN2tgELLP33EIdr+vQ
M8fz1R9DygDL+ykP/7i74I9SvjaH1ck4XZtq1I6DMiDiyPTGK8HhCM46cRiWBFTPWiCH0j6CfEUv
h2wl0kIufbj0Z804C3lp4fKk+DV+iGC4XmM1Sp9/9mHAu35gL6vXBF57HRX6RgsxNj2OWotAjYlG
y3n/j1C9qS2NzJ14WVJbl0e6+ryyAAQaVwtQMftss9O439NwdzYtWh800QkYSeqiq++BdiuOYCBM
5nyE0CXqz3CKpU/wTiso+/9+nBWsoVMATT+NexhPNZuZjVG61PNWPbn/a9vZrEzQ3L9pe14/E2QX
B1JLx1/BhgbWaExssVUscgb72/jNnQK44GAKgEOaD0LAZ8CYOHnlBtN5lsBKa00QOpR7TczyAqgG
7MthOXkOWnFxhcYMNjLwsrFJiJS5lnELluxtd3qKFUmYZlgcsQ3ydEjoklHPZQXqAyCGCB12ku7d
askaUgklgYW83Ngoeb2GQZtOKBsuRmjBp/xl4cvzhdDm5eJaL6W1/8aL7uaRigY80zxzXMW9o4dd
lSdL8P8hOKKyrsna+gM0mX5UdajlVxtEvEsV8v1Vn9FjGFhOTnpv00bzwjF+QerLwRYjyt6FhZjO
EVmhF/xGeMiRbo7kqF6iPB7fPEKgk5QocGKXAJ/bZf0D1QhVPAxCAt8/f+G50q1c1U1I7EiD+D24
nRDbPrp/UwU0ASN5AxrT61GWGWw0Q9/9Wov2MB+DnFsafOXZ6q13PPrJl9IaR35tq6ms9ltJasi0
NH8DGlgCBSFN1XuM8VZnjBHf0o1Sm4YexafKgT6rLdbNlVRaoFrXhaamJqq4EYidKvSE6i9CWNac
5cwIEt0Pt0wX2fQTJBlnTjFgt4NZNNo6lIPHzI2TEc4XmIfNYoze/g9HXDtvlb2GDnRikRlV/i+m
0GYbhkrhoJevs02WDOG+VlKPIkt7FOIGgO0mW91tWR9lbknZnKqAoLj0u0KISf/AqzGOY+K+GcPb
beOfY/PQ9jks2X+U7WMpQY9y6Rott4pWlvPX9r4qqq6+onjGoslPSKN/i+dPplHaMydF2HCtQs1u
glFBT7EwSd7n6VYdV8LEsH4nNACJzURzr0cpUlPz7y+lPKzg/fWbrr85b7+mMLbrIsSsvQvBu3uy
JXVqcGhwyiRkCvQvk4fFCRfzAMz04/FK72s64WRof54w5GbjcgGro9+3SjtFojaGvsslIf20V1oT
3Mv58atCDEfJN82rOaYrfiU9/+jSsOk0Q1r4xZElxDLZJzypFIrZ482EliSV6kcgcMs0La1sKAJV
PuD93oopyZV+LtqGsCsaoCkE/02YEmNeQ3oAes995y15fo75nFEkTpyS9WLtGUd7dlt/kBpcDnEE
hC7jsT+h/GPNanTiHqZQe0u0yv9a5C9i8kjO3BSK7C+loL8maaGVOsoEpLQwninDCMAzYMc+mVoh
ybkWiIReSF1LLGeKUnuKWHzmptmh89kczVz9UifAxyRS3fBMel/nDw5UgKh1ksRzgJ63uG8pu0J9
peeDgPjApxHKYzdesZS69UqvxdGU3S2Zphs4qpA8vimz7ytSt2/lS/rJMrOue/oxcuDWo1qgLBpw
5IyGLDaOKAFKTNFocQa0YxbjRRMhFz61xVno1+dXo5lnBE5aEIuBTKimdSdTJkq9K2pFntTD4Cgs
0VjnfgsqdpdXq9pz4o3A/6cxlgtwM1qodfATI7Uv09Kd+yHuLmWGhk4Y2XbJ4ttuLgN7AShWzbPc
SXvx7o2GwYb8g6mxPfQk6o0d/PlAVbnS+t+mlfwav97Vgg0I4+KKkqZ0E0mVJ4Q/XB7AY1N/3coD
u0ZUAxm+Z7S1q4f0RHt6Bqg3MWG47XmM1Mj0Ces0W5iGTtS1l73pCbpo9AWlwx2/Iz9HZKYWfTS6
tCUPDr5yZaUqTn66LKCNy92XfuMMgl4tW1NUs8XkvrbzlXn0c5x+njQIN27TPjuiBpCGXI/sneeb
s5jWtsGyPCTvf8iE7aJQKmtK1dVf5976DIFhC95GnF8WC6tCfkaHORBWRgt4IC34+OkjaBQs3kQp
QItE/w5HlkbDTrvra1rOcnIcT5iEJtBmcHUiAYKSeW6se1rRj+TR6J4B3A7LYbsR1bYlqNtcwGKg
4wZqPVJ6n5Bs5gxGbWuLhcm+9x/VJlOG/7DeUgUcDuHFMu8KYsIdOQT/dmcZMUJH9XdUVc9FJVgM
togUtaDutjkY8Wt1cG/VJ86AktgBDscgwDUr6d0OG6Rsby0asOwzphMj1gQKN9OftOZy8LzYd6lN
9NwsdcZFLGJrul5uu+A9vq7xEeiE6YxIWjvcSHihtEN7xczVFgzW0qQK5Pib+ZE5EMjoXXYdjnO5
83+thJumzKrtskvYRY1vZBNucC+gIYYTnTs5MkCIt564iRfzEDQOcV4I6qK1xDXzqUS3og9YRPEx
DI2VTYSovDRchn05rjVMeDRz/yYR+cks+aPqQA03JOBjzRLo6H18Wgp9bHZ7BNWlgp6zfR5wcxhO
yraI+GuVRKHqFjPEfh8AOq6rDR+If+aWwjBbItm0sXxJ3sTyH8kdK2IQcdNBsDL9yILTA/hOopoN
Q0PZxy0Jes3gvdFcqrW9kMWBRYH8BX2WQyajfxiNtHIcR2xhRrVmxGxB2pxxwV2hE3QJ6zmLY4O1
3Dn3+4kv0i45cOxjgjQogNiBWnPD3F0EslJRg9b1nhiFpHX3V2+2UuYLiEIWIgFnjl1tnLtUwFZK
8B0yCmXur4GDmGBkG/kcskTaEePtnmtwY0c/30pATYJfuer0n136jNntH5ElLGEKKG2ltEHkLnRh
9Du5UzAOXp2hZNDfaXBPdQjeEUJdIqeNBy8PPzHxy9GS7zXPenePGHbeOynhQxlGWwEoEFPKQeGv
CSbYp3ComMrXlzCV7WL5p1nhAlmf93D6okqeyRtTfQMopzTlQQW3Q9ZOUylD/13flkhQimTG4Wca
96XWdoFCnk1Kjmr5PNuPFh9W+aZ6vqmMOidZABCx431DRSKCUC8MSzuoIs7efC7qfvqS0p9zg3sq
e4qoNkO1bm48Z/rwF9EMqzYM8BAsTAOStj74y3bq7SkPuw7pKaYE5Dh/ASKjqjCWBwbFWhekC42q
tAxgidMyM5xAZP183vm9Q1XDbDQhAo41ohwkpfg0M0yaB85qOUiijp8SZG6vtABFeAADhoYU55P6
Fufkk1J8r0jCzpcoiCFijhjPA5uXYEULYsuNH+t/KMpTC3464G4MRjQ2iKRYDI0sTVnn3buhLCYs
TJfNAk0fI/J9h69yZemwLyULdn1GWkSLgiR4VnHUoa8L1lS971zQYr/hygOOP/UE1ngsR5vvFEA8
eo6GEp3ZS+P0MUywlWpkYZCH9DZC8p7ovXAyGTQjOYp/OXnv1bLZMIEAe9JXRQn5UbEYd5e2rOfZ
hCr2G0bxuuvcgi9d3w6Hu7J8p85SsMy94e1e8WJfmmXg/iCusEo0ewcbmgeGqrRmqMZz5Uku6u+9
4HHrQPOJD3bMXTU1VMI64JMNf0n/9ikbvZ0mzGwMw4SxvzZxkb55ual2fc3ltzYuB29yfXyt76AA
jPivkf6+44dGXcTq14csk1tlsaSlB6eh1DlbC1tyB0yZgk4Y/YSthUASxr2bnU1NHMM+uS5PoY9o
rdeBUnu6z2bEGLgvxmp7gQevriLD0FMvWW4CBVl61BrTXVicp1RdtlusfF8I2cCqzrYF4cVu9Pw4
x+R1cQZ+DcetXbdAYippB0MfY3+CQQHaP7wBP63rWj4nYfgV74QbZ4SvNjAjQ/tf4T7s+pbb70U0
KNfr8LY7VeLPNwtvevvxX9nFUJtcLWiVP3jObNixFUR1zRLnPPclrFEPCXkEV7fBA5wHiCg55OaY
L7Qx5gPMmi3ACWUgIvbaoZJOg1PwL+Oygc31fZQnNylaNa6wI8hy/qISR3whLWC6zVouP7Ns9Hl/
UKHUqZUXaDMbjjYxLY3mlZbeeZlxrYkrjGRwaM0qoBR1eoA96dgaHKgu2kbvrruiNmB5rZ+mEcMj
0VkpVd3tytCk348oPQDxHJ1qCaqkpKvj1lTcN+hDpDse3F4eX4RhEsAePXkmayHYpc/17NyRafQv
BRPMd18kly9vLwQikomDbzw0EAk1LgeGef7eU083U1u50z1/Inh17/WXxAM8oL8OCVc/TekBdYft
kdOCwbxL9bK8id5FfcgWM/IyvbDEhrIYMLqa7CJjPTQpihH4XklAgQ4GJLJyDtsxPdrfr8euau7D
vHBzx2uLZCBs/jQrfrgH6Kcs7iTbC1e0TIa4iYEaFVir0BxI0zHdnOBRD3mmn3FL8O6n8buSaiaA
y1rWUQw5i3ngFM65uCV7JlTNFF2lpBq0PeKkGDJ9S8D+zpVeLSbqDy0tbP4Q7TriYjko4gLjEdXN
fytigTzckxJtGZKucE9gDUtd1GJ7t+zEpPQNQOwFuuqwreI5XKxKR7sSNsLrEJnzLzTI7kSx5Dxe
KHdiRqKupuXFrilq4JSxhg0YawM65OyiOXMhHu4s3lF5H0AKhBcPAIposKrrLhBMPRJdj0c9G5F9
22KPtmI/WSFSvNM7miJiUzQ+OX9sjpCHmVY8qh+uvsrBIZpZBN30X8DCv0xvcHJRCvV5q254gkRL
tPxd8+PqeceLEl6TBcCSEnevdeSWQZxS8CI3HGYU6aLY/UlL8lzET0fo5oxTE3UQ12tkLaTn7OR5
UX+jvzuq7XKU0/eQnTo3pSb6durlZ575FyaakMPVOCEpXnKKhGVTqiIjQYKyq8IJ7zZDf74BUBUi
kT3jSQGj5E9G67Lvh25nw4kMWS0OB8Ysw1bJU8Dk0T6pdYJE6fhUM+o5pZRz0TXhSqR99MpBAK+0
0LhTs97xyIpKXKo0iyjyp0Cjm7jeHdJNTRLj0n/pmYWmkXXduQbhfiTS1qGIpmaMfQMHlN++AH/S
ZgcUEgjSKukLtYxgNfNiNRajTa+X2c1nvOgLv5127fXXRgKZFGEcEC8++1BRKZmhU2pM6P2pkQJO
N9wX1CC27q/zZOSAZMk8NQX06498d+IHzH2HYNKCLvKUf4ES6MRO9fOaw2QfKgqnLj3KqFYsgktd
rKViMKdpPxoCW7hjQ7Fe9YD549C3ELvhmjIYXAvEAegTlliSFwGkhV/wMTVRyDgQAJNaPVEyq8Dg
ccb6oDvoR0yaN7tFaUrbNQ3oI7cFfWwHvarfh8l99evg7y9reQiqlz365eDfdwNdIpdMyKB7jxBk
P+sOpRfxfkx73ahbDqJ0ZOWx2EWJ0UkwDp3IVHXjIPwhX5LdffQMgIAao2+dVcvMmO4SwiFDPZQu
+f7A3rphnYWfgcXMQZwhJXnap06CYzZyUcdQpTOOzo80ED11YkgBqji8afjPeHtMMdBKaqGfE67U
grBAAdJk6WBxHsnueyU4SOEIEPlU31PA2SHDra+fx4KA4zNThAZ5/AVbqL7DnR1EybtDLsMgXeiX
N54VHlphlkZ61nJGql9Kt8Ct//vdAdR/RfriUAMSW84Mbi817fdC3VxIFjZpooZX7a9eSgI8uTy+
D+r66Y7yQnBpxhWEmfVLVWqSLyOpQrZipGGvSPfJ3jJvnnR30HinAXWo9vQcl99awHQXhWG2uVJy
0dcPxLLEtDx6+7kQtTBdMXLXnLWlLWdNWvb750UPgdm6QvGvyI8iEHtpTaNl7TyutsrdUEnZChmD
ggN3UDDtr8DhgNk9nD1ZduV4UM3FnQhjqWUuWk+Rq6t17biNUinz5s7qYvWiEJIoHwgW+/U5DXI1
JwdVopvzOTRQ84RA2y2K3PU+MCNjnpvuQ4MZSOSPGMzN+u0u5ZlUProTjtBJhvSQVUhfVupP0o1+
+KsYxQ/itLDGNbE1LpDBwtthwxKhODhYHvdGWkwVQjFoh9oLBu0prNi7KsMSTQtpnYgH8/DAN2Ii
ENaK0fp75UDRtNLE3PFaFohPrnRueme0hE/pXWErAxmjkWf1p6fTulr3emYpSsxgeOoEQ53aRjLJ
zxcFvfZe0SFECigk35ZvrIR5URZ8sNoKb8zM6tX/cYCLdJn9L4zYZc73p+9E2tzeGP0OTXhn9aJO
FrbXSj5TwbI+ltl6jyInQIDYScyVvqzLRot0VZy/4PZ+9q+Mg8G3z8vAsVQLYsdd2XMcDbLBRUor
1Ewlanvie4k+JlcELZKwjEzHLoACA1LdCenZGvjbx/PRHVmcV4wsiWBk8ZFNCh+52W7LZSs5z9P7
OJTdSCEEZk3sFovXs+YG43p+aDXcLtL8HUVaVWgGBK0If+9qA6yC43JavLANT58G886338i4DIX7
5kgCmicLIWsPQR4BurW0Iw8saFxGaxtD2noU2eFAbHgQFjGTIWP09y8qpV77vMq9SP0T0sHfPzUu
Hk3P+0Xlrd/JynluO6ndnsow3ISmtxIeu45f37cimjVFQmCF2osr4wdk9M8TZb9G21lGfbBWLSHG
fYaqrwjslVE4vyGvAXxw9Tv/Z8+bLCidRmDn8a1QOGRn9CRAWjnbSpOlRvXT53Xt4L66GD2R9Feo
hLDufrVh0CFGixTxSEXBl4H7/9qhuYjkFVoQfQrLTrjcFnsUDtH6VRn60Dmd6li3psPMzENaSuT3
KXUhq1g1Sp+nha3YxFM01173Edh/UO5tLYZ3/cMCYGHUNaX9l5MbaktqHqmqROawE7e9PhVld0i5
WoroKqoOXC5JNjB1sIxwxZCOI/WHSlTeoM9ccAK1GsMjTdGYyjoFWDcPQGpvIcubZiXR2aoojxlU
HCUAv+OCBjeiGHUvfrbxIsStWC3LOmI9ZvMa5t2oCysNrVOpw3rJiHjORA1h+k/gJAjKFNJhroyZ
xMUXPwzBiHTPWvj4RPwV8pqGysNrAT5me8BZSNGdvAg/1v/p35DXStx55T5x7peVth3j2ko3w5Xe
spoAt4EJishNY3m6xgJ1CVKcOAPxWImg6Iyumn3H/5fc9eamR/d5U1VUshlHIs/ZCoMHBbP9e7S6
ONUqNHFYdpRIr5jFilQggzhzImKR8KbzWj2X1sUyoWqxUoHjFWo1Cldoab/QeN+TODHPOBNPGq99
GchuIDa6XoMXdXxo06OSRw6otdRxMVI3Mf8ZFUgFuFhbvSnpx2v8EaeDzTd0ej8p9bBjo/S/UvXN
oiPA871/ToDO2FuDTR/CK7wvO3+ONfxmFTghmrXj30HraZ4N07SrVZ5JtMH8cNdKQFnQS8Hjc7my
hOr2aVxWv6fCsqIv9nlvvAc16eX/xIZtyEqiIzrECtwM+CHg94dX8ANj9W+rjeqvDbkFqleJ9eoC
uXw2PLlCrkzpakYjYK2eYj+MtqwVP+znsvE8yfBIdqBk/oLkbbsiTma31smSq3adD6n40mZfcAMd
jSZ5Mu4phni23B56sFTabggD/n+cWroj5ForbO3kPMZ5vgP1xka9K2vc4cyqYTTa80mmhtNNRA23
H5W/M2fzgynHod47CfHTCXMQoj0AT96ZsccEbpjVLW6PKi7VHeCWdDzoKTc41pGyNodknZSGw8BM
34FiDsr2ur5zQoQk63JJ40207Cy8aaaFbNU9E+TIZblhQqBAuxWxgn7VSUMCJSzcQXJd6/iv82ij
Qa4U+2MxbH4RC0pa3+UGq+/uqqqqEMER5nIQWTAWWN5ONX1tvayBJn/ZDMtKRXDRS5lTUNXNyKhN
QzVJwwLay60EBq1Igz9eL20WPgxunlbY7Agz8j4JWTgo8FeuTkcI6//Dwsz1k6Jx+XRX78R1mEO7
5kDDSIHDU3hJPjQW5ladfzX0yghffLzUD5uu+XDeGnGKdkxddS8MPE7Qkfj64XgPISbhgZULEHE0
xcX2+2fRCvKZ+MDnBGyg+zuUb5j5zCNHm8SzNCtJ+VwfDizNeQ7wKAL2La4Jp+RnOx7f6ZWjXQGo
zjiMFzQTFNVVwZIPtKKWkgfiZBAjSbaMj0j6yA8vWRZRZF9w2mlS8UABXGvOp/zpy+UNR30Da6dj
fz92RB8ywj9QYMXND4fkaG7B+6TiQW/1PSMSNXbSi5o/HuA4A7M7edqqxSDwZAZ2bkvuvAg/lw3G
/jYpLxoWWaUcJQDG3qvf1BFyWdoRNEAEKAGEvlaRG8HeIT0eJDSyip0azlckO81KYyNI29kJR2SY
6las99eCBF9vB8baRybO9uX/t2qE8b5Cep7e8XXUgpoD5tRX9+ufFIU8bCJCMvtYDe1usvEw/XNN
Bon2Xsmq3Bc9ShSuWleDaIRbVPuaB+Nhve7Oo6O9oPwKgrnLQjdLixCx1lR+HbEMEsNqhoe+MOs8
JhpKh2ENKm4PaVVVQ5WabMD9B1T/6u0H5PpeKW9zVrQXcGtYQxRICpq6hG6LeyZkYu2meYWefRdt
DRX79ZqZ4aeT033Joc+ZKePnrzLjZgesZ7QxCahKi639/t6Z4/+hZi45ZK9FML1FOMxhGsbFVZtW
bSac18voo+gehxj+p5w3srKk8mjUV+fy4tAvzukJXg6nmlyh0UIkaxOUFS8q8XZUs2rYMvur7aRp
yoMyg5XTL9j3IWKxZKIubWjPUcnsmGVN3x1G/FRJ2mNVn/ChQkkbcFByRV2eDvr4YuAm8HyjgW+K
vlCIAXGF81GytSElJLftN4l/N23HQkJwlip4aHHdMlGs61e/rUMli4BX5sVFRFYrtkaWKSC9rzMD
vPZFczUVkyOEuZ+4Ufn1NNGPyw9R6jljzvRSlDHm4zHajyfLaA8f29cgRsVGJ1fmaBefzUMVrxFl
HoGMy9ERShDAjugr5aKrxjzoXOMCYEGpxS/U/lZ2/9S0yFjdlKJMl04MIWLapj08ClvAZPolI2+I
OrkvfYHYPb+bERK80HadAx7Z/fVvSWylSDvDJsoaJdUgvj7h9YE5CG7NshBJ6DBDtHkw0gWItUz0
UAt26iqCCizzQ9J3W4U8Dxn6d1WkiSfUumWRV5n+rjp3ye66H2EW1foeRc9YV/qzHOdQtfg6Fgjo
xssZXyfqm/1CPcumG2wVAE9d9vXCfbkpAGEG2Y8RoOcLzikN6WiVUPyH4SdGz6nUuTAfkKu1T6Fs
cKK/GwDDA8BGhqkfrI1biEvErM105SAy5lp90vt+xp2fcmX0vV3ivCpT6MJE8wRMahufBLrSjVA7
DyCNuV9ZcoeFLnlPWlsDlBb2SnAiEhOUt4uXojoTK8DERi/H5WIw6Bv1WGuLnCxH+MlUQOBlpjYN
H+Gu4PSzVMY+PHmSUE3LgheFxsvxHcua9Wc5ZpAplWcj+Qn5wFkLa8bitU7J/1AZElQ7PqLOg/Uo
sOduiOW7Ifed9SGxmdZK1xqn3jxE2mHtV0WjcBWH1BDsr5teOhUALBZtEb+gnB+VmS0hTDe3GGxm
ftmiziP4Y3jLHb4TYc/KbTkex/wSyI4INhjM1uQavyQGT1oDt4PpFLs3VTTIrNRwCDxNxoO8gkIc
pjCOGIDJvRYZai8hgVmFxLpoilF4xnz6kE8h5J3QdF00sf6SZKkpMylyA1t9jWkmPupb5293IW3c
eEEhBrsjP3WwjpXPQ32FTokWX1HLqbvHIBpHHz1jKKAzht9VbeohcVnbA8soxXTGaWz8CpdLNZ6n
jdh/febqf1z6FZkF5FB27vSjsGW6xmAHa7COeSCbKmJ6w9ylkJrlO3KvnCq+aQyzcJ+W79CmxTPl
ORYMgZs+lMuoFkDI/Iu5JG+H1JEwifMfTCcojINUmyY33zR3lPyCj4T2kKWcOhSsID+AMjHNSxhZ
GTeoyXMOktMqxtLCoJk1CEyDDNKZM4Q0oKPDB5p4zWUKWtUiv9gQC4iIQ8K/YiCDuk0TmoQkvJL5
wDqgg8QXN2CeTNB5bcrtsxDk3mmg7+Ijv6QhWhYiC9xqlCvjfhCBRdB1OPjCmh2bZISCC0Obzjhy
luVXazbQ0OhbMXzBdp8sCviIWcudaFZEqicx/y6yZUz4pLiqPAY1gZ43fCCRiDAJZUJZTUzypY9L
DvsFb5rxiLqYLWLcmlTiPlgMylQ7cEDOp7fMEqTfAWyi81ubU/PAdas3vXc4YR/JMRApX9CuqyEx
Q23d3p1R8tJEC3AVg43Q1Ex8nYU6mWpSub4251rwUviHsvFdI7hiiY8Ifa6CWNx8XvbibgdGl6J5
FEl+9DmZB9eFK/oeH3X0AMBsdU1xuTI+8ydVR12Gaz6RLi5KkidsOEP8QR9ndqxSg9yoXLncc4fD
6YAM0pQt0+l2+qSGkgvQ9FdNKT3q4tayJkT1FOsCD+aU0PkkpDemWNjhGjxcWEh91qRLcpSf3apu
GVsZJLvdfQKYszx6O2kAtscKvsCwI/WXT6Sx0DhHc9ysAaJ+ohhZvdie5AZ4+Z90VzEJg5jYLK5z
BVmRiBPqoeuHzVLfGgcjO+E+Dk82DlSAxuPMKdwL36b14ko1vl7xP0fErYn/jOt3Ls0DmPxBxrjf
6+JMwc7Ab1nDbbcDn3+aJKRRVLs1x1omm5BxJU+PPDoYy6AuSbx9WCIGsy1/mL8w1IYWF27f2drd
ojJU3Rtzy2p4Z8uTkI161WZoZOk0CwR9FNiegE7rXnI//1UyPbxQU0Ts55GNz0IDDrhs42d2WM2w
DIDQPGdSMSPQRDSFc1frm1SSF+ZJZ79EZWTm1cf2QSIPR63IPrIMcX61RM7iv28CTUeFIDoFrcHR
jZgaQhFK3ssUMI4jeNyZA/FwONMfQn38qTY+ZNHxo9LyR+KPj55Km7ij27LvfI9Zy9Vi2X4dSE5D
0MsLrsFrMdtg2IO/YtI37EycbmZU4N4TAejZ6+MPUnBaUdBPhHECzmVxvVaeA4lEW7R9RPT5FVox
EN17jh/s8bmhu6qOQmy0saufsNqEzsa4HXIHE2JRUCmzCJ57wkmIgIl25BhSwYEtHaoM/sDmGIUY
txeJfceExt6tpYl9KNJboCEOGjeNNdswHu3uD0XY9lMON2i/n6YqB+1vZA4R0Lww9DhhXYi8uW8F
07aXIfj0xgSPcYuufMHjbNJp9Wk0xTdcBINAQ+ls9eHp4SnMEwqy12eFDwypZ5OiNoDGhL2bNxW0
LJsuZjQPQlR1yiO1SV9ma4V978MrFn1/KcMDhlkZH6CZkk8tJFjcI2nkIcDl7iakpJXY6WoUQHDG
UX9uWuWIvpwnl7HE5JKS95cB4CdN/wo3GPqdqMVNrlTa2yPLg8irDYMAKOxKi6pKTt4ZnvifVdWE
SV8LKy+0YXdxTWU9z1Gy3kDRgVeJNSmHRTzEXIZFWiLP2EYB1hJjj8gvZypXb6YM6/FQYziULIi7
iI+t6SQ9lB/o3jPIRaJfy5iPtjCHLGZ1t8h1MkTXjC/cE4exeIYb/BNAVt+H8CcS0hOTVWjz5MIt
Sw/jKyqWH6d/qCfNqUwXEn48Bq4QlfLtnSXTP4vvx2adfOL69aUbRJrdPqP9nVYDZ2yIfx+L6WMh
kfX7pE9a/6Hq+tWYxAF7tJ3jRPYLzB5ov4D3YXSGhg3P3gr8K42Zckice2aEerqrvBhe64mOSMVi
W+QVXXFHOJ/DYH7JRMr0BtRTlQyyklUCz9uW1sQtmUUghc4rondCj+fVSwJwc//ztMLhJCyXazNh
k/696bSleu2eQSKnEgJ84dQjeh0q+GhuYF9+UCKgrYM5OzDzYl5tszS99JsVUoIvlVdzWDtv37ot
36ZC8W/xHFJRi+J//V+6rfEizNSGB2ayq+NvompxmJ8434T5ArSr5WTDchJbHHs6i5vlyyRISgjl
KPYfCSl4iVwoREtGerr72kzHEN/kkwOwnmrJg5KFHFLA2gTAcoPD258HhUwCQq6iG8FtBoKE6AU2
c+LhXfUsxEB7zlmMCCkjx+fuGyRKpuBeLYNfXbKWqlIoN3jgMXa8Rfnu99xkmwTBRViRKGDHvhvS
hmIL1P+fSJGgjr2v5eHNhUdFG6sVS9xmwgSPVIKXOBhGk59eLgVvZHeClKj4MmeI6Gf0nY4fHRF1
jRkAslS7gXYJRqmjXgqsv7verEtnFNuDfEsFmYh75749mPUlCxkiMXVRk5pt3AdKzNvnN//Jug30
y6ts1CWbK6CnbAoj9vGM/DagiPj9+nlpAxf1M556ENV0YOioJEEBTPHdc6XtBrX0u9sH1x5TjFVD
UMK3+xGoNfhx0iRpujASk7lMAAn4ZZ/LXB4nI6SXbl4KgEEDhKncXZ0haaKHnx3Cr0EWhq2in2Xz
AAqP5cq6on7GFxrNJb9xc/mJ808KAUtmNYUfZMlBQAp20VBPdGLyZ7uyuAo19j9TTfoWPmtahl+j
qEdqdbHZdCpL9FEl4cY6DXnPcZuD5GaxOYu1BTevfgvGf2bfT9U8/YTCgP0aapWEaHSgEBNvTBL3
Xt9UY7vPndvjUn9FhvPClwp+m3igEIrYNnHROnxafQW2vh9LUVsXOqj2zAz6NCJl+rXHS/eNfCon
Zhaqkn6IHjDCFwSJrIS7Zljw8G2B8neZawTdYqFuLPv8yNO0+IFoJiTLHZ8fnND0dmfd9TJrWnnB
pjX4eWDN0ePkkXOfzhSBz4ribLo5oI3UGfaThZ2kKEzFPcebeB71pQQehrBZnOOjijtnByw1hP+t
9XY0XJ4a5Gm4g2NwVpqVPyM5kU0b8OCCDBZcLFCL/KeWopVJfSWuFE8VZl/w7vExqJ7P4Cr74Tv1
B796J7gdFldnNdq7iv9XLukRe+eDBb92tjj9Tf5qTgMyJT3RN4jw4LGJ+dFqbPu4GtQtYDLdPmMY
bJ2aBx4a6RbO2wVG5NVmrq1k3nvTC8MSKO7uNpnnoVVLbNN5pPq0BbNa0gS6tyrAqOmhX2da57ZG
s/069t+EaGUuIzPI+A9r/MKa6TJ2idV1l9PRs4dhtkddo/y+PfEds+BElMrqR3ZbvVcet8OCgR+e
BSchcHzlJHJ7rFYk7O+bumht/C4Yzv6TC8Ieo8IbKDc7pvUnq/ecWxEa7gddSr6eAUgc+JwEhV7Z
T5L9eAOH3lJ2RdEhT16GR7Oh7SEzkm2iGzr2VGsjhzKD8+oITSGErtHHqK2zPyP3YOU+sqISYZTT
EZm+b6/F10AsHH7dO9HV7FkGWfV150fKYy8MMMSLqga1SaVIFOLPJck7kQqsgfvq3nHFSoYid4FJ
+SAPZ3nbkyeuiyM6vr7e51WdpaIgPWucDAbg2/adv11zzd224s0XRMoSb/6K3pz0ynmQTinvnDu/
XJNfZPOT5J42jMV7cbm3nzByqbv32VH2QhgmrcNRGmRSVYPrckQralBaMyz+KfMKj+eTfqW3pGuE
ZHeqDLK3NGD2Dl1OpCxBN8O1Z+q7NYKZyBRapkKseiPG5MholPhgGx3lAOXK+19kYkxH1okcqr4q
7eKIvovCobYBoO21Kur0Os3CzW9O4PQYhzODDLGLsKCjjRtmdbRu4BxmcL8y00QMytz/UFDKtNn5
Iv2hdVYfuVpbRN7M+RBj8OMKKoukvGaNtdQypwPwrzmGw7LkH4nvoRHF7w6/BAJJWdkUovj0uyuD
NBaZxESPxyoZMpiTcPeIxGChQGv5ZtaCw4kNZNP0NyFNhmrbNmJ1c9fH7mHKElhiQ9uXQB19KDMI
QJGLguYMO1bXNoERd3nYhYTOFUW+PSGj++b4BeY90LbHhQ0DVkGNk/KoH+EjZuFNXrLfSiS3gjfu
cZHLHQkoAZu5yxY4oXXuTwMeFCEoSjiVehLWO1ETTDnV/08QIomNDQ/wLMo3S1xhe82ta7Z0svsT
a8JjiVBSE0IuhFg4BTnoEYLbgsNua6+UV9iGBiE4pCPyelh1I4Ny1mC26F8jQ/ThbdGa5bX3Qqhf
76WfKbXLlxvdMNn80VBKTgLYZI2K8xumVpkaHaD6sxCEp40uERG9NqZqQqQ5DAE+fBmHkr9fW51P
qfEu6edDBVwnVYi6Y0qE8//NWckG+sD+IeBlVQ7toqbecc/t+rThUdA90UsiRcb7o8OCHPp43xdf
AfqDAhY03Ylxdkc6T77Fe3S+iFmLHZPkArWoB/xWmuWU6dGQnJ6HNSqGcavlFBx72TnmxJn3wAyy
VhQh1iBlSFSKzKs1CydMlTIjLwS69xkUMHFEpN+aO/ntjxFPKlJ2N+YBBBMDS5v/M086hAEJwIQe
fxmM2lBa/3og+PsklWMajFQQzg1Z2Zcy6kTd3cQPQVhIkFufI7YsI6froSWy/yAAPovFDzzJ/fe7
VzOmSJ1Sc/mpLCHgKvv8zhuKhayyHd+RHLXYTiiEUm4E6sNDmX2ptCqlV/Hg19JxISYTlpC8P9ai
4LiQlyTwqreC7zI1YvaKx1U9bq2gm3Q783MGjM+si95/xpJ7zNwPe4Ffd2wGmf+rPpHX+zZNgFSE
+N/O07wx877Z0RGwCmMx0UsmFncD+LNUFG2zgvU7olxKdCe5HA9JKXkiIYDHTmpaOj0X2sxi8+SM
LQsTy83he1Vkv+k+JXrih+LIo3pDwIgDkOo0u9n38KRFo2l4Z494BFiZv6vof0XZ0yHcFS8MU4rW
DX4BxbpdrSgzMiMtSOzPWXZshofNsvmzV6hOwtlRRazdfe6iJkAjouwvhrzHfqCQQ+DoSf1pYjjA
UGqWaVqzGaT9AHxJOO/Y5otoBPPhqzstT/6+xsBWDDNfdNA/lpj6EHF/V/mG71zf9fO+0a01Rl3W
s5A3zNg8Wlp/BVSOluA/x8sTva29xSA1H7oNWmTD/fbbj0bXGlS3mxbwYAVB6JUb49j4tgBafFr1
JfyHSgpTcp1sI0s0tm+JERKuSJ36P/7IGkfOBDIQsTtMeFq/j4Rxq6Dn1cmhakmhAYaFwKqU3Cpx
jEfP0Y4LK1irQ2eQE8faw9zbbnoFfAu4GjvArbtc7pciVG0ainZTE6YUTCY1ggZFtssxf+HLG0Ae
nNMDNAJ55QsVSOUrlFZcY1uvB0NHlJvpPrfu8MOqls+fG479hB9T1xeGXILsyrUmo519lUTvsYrz
+ikjo8cmOqGeo9QJq1blaC9y1+H+bwhrdVdMW0syHsShsCaEHetfn4+On6HnM+Yikk/9GN81rPSU
vdragfBjRB6taWp9S/bIg6mIaytT0vr1ynQCTKXeyIMDTpuna21KxYDyIkpL+QNkaNyhwZZJxjmj
ZDtQHmNqTqG3pYdaOjjg3Gu6YDYr4fqOTUZcomGuM7buQneDynSrtfsuswB5/MP1LKmNj/QCQx08
DDBH7oo+OyJFCGxsHU3RfUGVec+GlDDn107KPj4wZwYbdkflMFd2RPkPFs23HfDGiH45WUwxb8Gr
V5S+o/qSv9M8VOzzUlTwHUFpu8X1tIWZaECTowT+tH6XZ9m/1qLMr6POzXZod8wEFeI62zhalhPw
l1wWt/jYv+CC/2VZeBbVLqTxUWVfFfYfLffBox4KCIh61/yx1O9pQSCCZOyweWvDHpPDpDVCiOi4
RGr0ar4uq+dALMlGTRRMmiDIMPfIIoAOu+3lnHdvIUSfDfBfHl4h8hX7ysI/M+LL/cVPU+D8mrUH
BlFVcITlT5L6cYm6lHuTymSunNfiWtTiY59S0JEQiSJmZC7SEQgEppDvcsZOnk5j8QUaKEjOudGN
HLXMjxQxD+KB6K0wCEjkqRcrdYVM6xu0r3JZ3BvWudTmSvET44FBUZmOj0cMBQLnSf2SJfkvr75J
v92W++LARCJlyUbskB1rtezdA2RXX6jyZ1VbSN1RrLUPZ0oh/btInqqo/fzmitIF9YRB2iEVxcp2
mPHFMkqlZPrYr2SqALhY3vsmv+X7CNYTYfgzOZnngZbFUTOGqZuzg0MSHYtFYvF+xVGprVUvq2Rp
o1td9mejtRGbUZdf93zHf4yM1yi2BkhKnmbDGRhCHIf83zWTlNgA0CHie93cyXfnY9uL2bWtjZpU
v6gADTpzf3IVEqfs6hAWqNob/IEDsfk/rzAzfacCH02QlZJNOiMJLfgg9DRjyodY768zgDEKbWlE
j/ZyC/A5gB2bFGEiKfOhYhIMSratmdeCDjSQ7pXa4v1m/+uAS5kbmh18aOKaFpUY8r2hWxX5K/9S
f4dZtJS9CekVyP2Tjm5GU7iYeG8A+nkkiWLA90JzD11I/Y1VpiZhb+sj5yBdh6w/MP9TSf575XdQ
KE9rFRuZEnzFR6BS4q7JVH3tmVQJinTvyXPlCO8rWhwqp6y6l1sAZmvCe9ELVxc6eoIfnIiV8BhZ
SaKNdf2DNQV1ZfG/t6z0Os46KxjMTEO6aU2VxBsK//vcbp4haE8jw3rWn25gX6qsjUPlRNE6cgQ0
gAXTkor97nOXJulKxt1+4paj5irW0+yVYVSd+F+YRoDDoz+/y+rXaz1FU1Qr7OsxiemYoj8ajRZ/
h0HbKGMh8GJEbgzIm0x+aznmzbhTJcJoA2ptnrV5KtaXmVff9LlLjKDrqZ/CCk9NMce92JQHhf0a
q7UDu/070E0z+ksw21Z3WOuXO/04oXM8MXEltsBbCIEdKL//pmBn8GgNDW+chHuiDuj5C2oRcLZQ
I8Y2avt+oMMNTAVCvDoxU6rE1foJjKoKoky3SBphzBwBIeCu9FeQqmFqBkKeO17+c+PF8fsHZV4x
aO3HjmmoMSmoiK7ssJk0DUTk35B2Mf9dIv6d+0AtShcWl4RFI/ux4AUepQJHlfTnHeePK7632fAZ
kNwZVH6+4+9WdaLZJoCJBX/TPlq6m1D3MQfCFvaAhppIPIY+H767NRx5rat4InXL8TAE9PGDsGd5
Cp4pJX4hxUyDkDKJipOvixhg0xSbe5qC65jSZriVsUHSg55PcZov2FEQBs0wD/iO16w9t7zAmjiz
YSnVbDibaTbCKiCIvhTZQM0IC8IVcXNxBCcby0uGG65os9DfCM9pOQF47Obz2ahOIFEy55TgyGVe
M9vS9qBcrtF2+vAqu9MXUcHU1hjBm1mjkS0mJ+0E4eIjjWAAZEi6BRgQvaAki64pc63UBJI6Pq1w
TCgIWuIHXq3/xEsEfTKUEs+nl1zwO081FrIdIrElefrrJrO9fJYeSEd4a4nJ4z1HFLElWW1kPxGc
1q/mUN9qE0p0+4uEbvdKsc+OKm7mVeeKU4Y0JgKD9Rw4Z05mJ4EXedcz0rixgHa5Wpnc4NtBzYoT
jPnADucVS3zMxqXaMuJZIspHFO22gDYdp+MdamRh3zni0nxTFmKDiFxPwSLlnvwHoH/xWiZtuZGk
oCUBaO6UKhOh2KGfcQKWfhPoGLd57VR+vDUDbgqVUzTYv+zQTnVijO1gcxpU4XdX3tPO+na9aBec
IXkbyyKn4M039m+Wz535bFthMFQ4B1tFmwzSE6RkrB4ugPbu+scLA1hJ9IPok2rknBl7KoT01X6K
Kd19ixJsw73UgvOZ2o81kkEuRD07m+46iyyt0tOj+qARQDIqXgftwHUXcT1tlXKiig+VMfyzHUAF
3pfrt3Db9ZsI+7/Q/r8YxSzBjzjyZvWJ8N0yUdjKk298h6bSEvODM6/2h6w3jYN1i8j6q0/B4/+6
4onCzUd1z8BqQcJ8rvKv9POa4GkaCh6P3wXXBwtWxYb88sHQHgK8jt75R+uYEgJ2LwzVoxMgNXJ8
jQ7b80jquhIp5uueh6ObSmUT7lUvHnGJ5NpKelS+xrv8pbjEYclvmbtMeDmwC9RqDTUJUD17ykRd
TrxIiBAfVD4CCuL72GeHz/8NLWgcUZbBn+dG7B7kzqO6WvpdUndWPaax5rm0jPGoClYxPVLpiFt5
Q6d+trxk+AOy0ugeR98Hw/Q0sdFWNf+hvSO60PdyofrhbttcK4N4u5eQS9l/CIflc00mgU7G8y3d
NPpdpqs2ZLofJTPNucsSIAwndaOkB+V/UUhTvsP8UwcHtil5sAYsM597nuqlipyt0f5tEVT96+CZ
QDv9Gl6NXGCNzAj7SWDibg+U9EQGX037PrZ8UwaJnfsxEWqBSpU9uYPKb2i2CsSSqhn3twv7K6TJ
/JOYqEOeN2xyKuOubF/DCHyaSek1SuAVLaEEB8wc/N2DE4imFtBFANBDY85BnIOikMTBX1bU6gud
9as3kjvNhWo7U4E9jUt0RU3p6UYvYnnT2R9gOKaZPr97ZH8FSEnzCCBs4T2P6L/cAIsVNvRhmIez
VKUvp9xmaensUqZgkUrpaAFaeOVa9CsXjlGMlsh4ljMJT5CWwwmpk63AOfod+Hlk14oXmaqyz17v
yjsB3ywgcl6oddLYTocjeVwnAGnZQxWaooedA9r7J1tPOvLT5BsMTVQ1POZjiru81Z33viArerNW
/OLHTEUl8lLBQOkt2IPbR3voClJdO7+9oY/d0GF2JJzJVaeX7I9ugibipuunXIoZn5jrMm8QFQYR
LzQ+LZWZJtJTrTbVBE3x0Su96FrwF0tZzSi631Mg/mXpNOHXyI8miDoG62h7mWm4CjE0XhoqTB+S
+EzM6G79GWK+/psO/QDtwdCZ5GVX1qavmeV6SvIbxQkTAKaOtn9SQMZr4XUYAZuw33Nl7df68631
dvJrTv15DAYTsFZVtflmDrl3hg1zYAtpEqXPTMjrYJk4COy1qNZveVk1Pg2ZpGtABnuqxsvBsmn4
YMJAuuO7s3wvctBZ1gyZweyzWtGzmeSkCX2SUtvAKTwQbZrtgb7XYp+zDzBmRhn7GJwdSAM+IsWQ
ftCIpAHpQkt4Zn+g5f4iX3qRxZ6VfNq6DiievSzeBBOsewhWki4Yekq1WNUbJuy5maXeiBgDmqvG
kRatXO3ZzRoCN+0TcifHnK2m7PjX0KKYSnogngEKm8a0JpVIAX4uopo5gr8yrLMitS3O48i5TZG2
kG3HPlwbgEAJ2OKp/MP1yXUoO6lyjkJsgDUB97wdcEiN7fpR6LfRkORlQ0Cp4eZ77NweN1S0tDsi
ONSXZc8e3Cxrz6owb5mK59j5s0m3guYOio+TaFOEQVfP+T+ldX5CIjc5cFi7VxlohabCuoD5X6xh
kl5tGCA/ZTxoVNWJa+JsRcGYD8Za5ScZn2RkSzJ+PF6pg/EGMuXTsHgJVd4HSkbE+caKuAaX6sgi
x5Zh8BJAYaBglwVZOWkfkPOGVia2yAJvfI4XbcFQ662ZFIhbuP9YfX9wUjosbYgHR5negQO61Vl0
GL3MxfM/y4m+/BHKrmW0aPygsw3hMKibuZdl8F3Uzu7SO4FQ9ghweImrgy+RgACjgv/8OUn7B/fE
auw9hEqfHWvjUXdRw3SqEdSCXQqCvAWSv1rk5W2soWR6PNtY3D/SiXlvKlR+6CRij+9Seu6wLY0/
nDzWlvnn/jwz6OvI0nZDW0lB5n/QakgadOMDP2vQzAd8PuJtBcTHvgyuJUZ4LVDaUasQshU2DQrb
Q4qDpZ09/Gj+480+FsKZ87WgfjMl4kRRWV3oARkCT0KeZLSxZtJFPjges770fpIVY2uD36WC5fL5
4c4LQqAbvElT5EwKyeNDYjL86OkcOB6zjrTf2ffSiRxdtriH/rkJa3g6yKw852ij85SczXGHvx7q
MydLTvGdqmvfQVykcdpemz0z5agjPY4voMEaBX7Wm4HqT3SQ8JX6Rxslpp2pE6Qolem2hPYKMs3f
JTF5KAYOceSmd5N/CfQcG18hDoTQ9Du7HbPRbpzBX4nYi+eJRbWj/ijON7AZ1nhzMdtUniCYJmBI
y86MVup8m9ZNYBIs833jYgMUUWGhKKQoCKnK5KQe1c7L41TWeZjuP/6v9Ukg2fPVRbLu4UUksyIp
AhgnhViAxImREDAGtkNvBK3tacWVArl8pGhZeNGjOLaVEAi9f4NobkjO0nayqQAMpFX65ho2w1sx
Z3XKQJOhtyqpBBiFbod9APrLaV+ReEtR5tytCmx318Tsec6pnsIBULdC82a14tPilfZL7FoUq08M
idDl9IAwh6xQXiUTvgXaU/7dB+GswPUenXrUON0DG711ENXqPTIqKCME13zznQz1+yo0SC7LspuU
rVBPdadZ4CzvPvmurmXBQliRwCc9oNfpSfmPYyyMbvaw7TkumjoXffPgUhn8oUQT1510P6VPjFYJ
B+3rtBv+mPRzM9N89c4jjZCtbSTiFXfWugWRYdRiPY5MqCQPyP4IiQ/qLT1aRdgKBaK7jMFwnc/W
y/IQ2MGj9XAWxvoHio+Kn9W9qKgUpjdQGb4C638kXiiYRiXR85ACELm9law72avWlMglR19pG/GM
WkqYjDu2hEESCfh+83bTkLEt7A0LIag71m3wysJR3spe6Y8Nb7c7Sfmw2qM8jaMO9Alo2AuX9JmG
IDNHx92f852ri9PId7YF9OEfyG7HxRPVyK/AbGxfiQo1FOvlJXojYqdKHIIP0E7l/LyUt6TzD3Zg
tyBwrKZjZNDY7MLPT2rLOotnlPDYT/d8ux+CRbnrGNvKrLgXrUYm+2VBZ9WvNs4BVUUBULTD5023
vBnW7wYZokndv1Ma94A/WvQVJHJalN4DQlfXDQT9ONXspQRAVOLkVsTi9xyShIjcYS0EyslFKgl5
cVWpBdB19CckNmxadFoDFaxFsaHhY/+A/ol5lUNJ1AiDGRz83F9lWTI558nx7VRn0hpvrUEvZ3RF
9AveNRwySb8DDhTL15AM/lSLL6kT3f4SYx1ZaFyx3tmE/sgn9xZXC7bVuBMLfR6D3wakvTm3o3gq
4IGqsyW5E1EMBrZx28NR5ygUbiAR6f+F8JpqnI3Wrszcqs5SsjBZ7ToL+wC4pt38z5ihxHxBGDTy
L4jh7xcWXlIoNGV9M8e72rPY1MQtMVSaRfGXXdZKF82xkVpM27KMBnQINDGOp/uT5X/nWFernd1O
qGoO5NpbO9PjEFrKfpfwh3QIZbQv4ZDrvU8Q09qH9e4XlO/Islu0jo/C/mlTkoUpmxGJD0/RVn9F
Eg7n1Fhlghi5P9LxzSFeM9+OfHbkbZ2zClVGGt34mCRMt9yGofkv+ITtgthmNRWXy/XwAf7kyydO
GX7NlmIDoaHzIYJ6xijnyZzxmMkvQXrB9IB8GS/gvZByTL+AmKV/swu+mfOUhmnd3JKApqCQsak3
jCuyM9WuX6t12FVNGjToVjHIk9BBGP18e+1dcrH6XfVLrPOyznqCP98ATw4gs8uaUrPDhR1mEUio
8g8BNZkA5fnEtBCZGZN0b9GRs/iamwNz6M9SnEICJzJg+JVHqI/tlyK+gskWNPSkY5QFstk7I+BV
XFDODdEBPVMpM04efHnpAj6Z3wCVPKJC37kvd1yGvjKFDoes2032HRb+sBbmyyUc0CcX7l0sFzqy
DpZ7dOxoF47k1iy5lzCSeqNFAPCJviMmuAM2kp3zpDyV9DEbxV2CtcazBwn9uotoIOIlKN2qHg9k
c/VOBAVe6RsGzTHnmc0HsYV5nBFxkvMfYjhxIS5UXXlNXlnfdLBpOQI9zN++a+Xm06iPimZVm6bu
Keq5CtPE3C2tIuBZTN7m7j2oqfKH/8CfI70visLrSHU7NMXHnkJitnxB3TVnyWlWu02U3ijRYlWP
G6NT414EoiTk1++aZJCTp3PfZaEBVQVp240T5GK/tYTWIlESC4TVlGo39cLpBElvZ81qD7oqvlfg
26gcEJeac3IgbjquT1mIZWAlu8F3foe60QNJGJT1TN0pGZ3C9pLA3PvM7Ia6cx6re3BsRWNUoDR6
i6I3ZrOn9ANbBuOQ/zHHVwFJZWRiB3/Ebjt5SCoiHG+wENmNJLeTr5XD/QzyJvfwrjElDOvFlVWb
NlPQLB2qQ0BBilViAsX6v7xHR1r+iY9hWt4KfsbsN7hqituLHZQgN1U3lrT8alR1K7lk+SeWQz/v
Zss6FL6HHI7mQwE5L0NIUjPTh8JAaBVlsL429V+a313DTvepTMMA88DWNSq0JIz0rrjlfQKP83mX
JZatt4ty6SLxZsIn2pxWkPITDodkjoZO78tLrjcM+VYntsFsXTFkx3nQE1lbYdaeRZEQ8mnpuWnk
WkzsAy0T2wR8lLDZjL+11I3xLmyh13CY2PfqetxRNRSm+cpa6EL6TXr21qRLlh792aMhHdto1/Xb
wRo0WIKa7BWfbFNNtUihHlFRiMwEktFFbvZIvm7lyu+O+QsZx0vpj0KlQwuCdlRsrof0BhBSTK45
Bq1KOuSKSr91JtcaKYbhhiwF03iLgcgb7d/xcukn4GW4SXW2lytvfwu+QLcXgZXzbSkFZrwfHBe7
LpHwEeEhVRmnJkk0VU0ojZWu+vEE9R/0ZtloRecNFP61LvKMeP8pKfaz2iEDALjILaNeNYzX4WJz
ROUP4cvrNiRbYtMNMnNSHRVWFVgbnJp14aFuYxkfWqcf/L+z8L/o7KQmDklqc3PZiyfgf/3qHQw8
Mnxk+DCTVyDAK9Y3ptV85WNAIPvBklApQU/5aBHjbtcfu2DEHQzB9c71A/7L3SIkEgpggAH9yw0W
TXZb00nYfsMRiv7L3R3OAXN4Nc9+ddMwim03rVTxSgHpRzKU1X+DFpyqkE2+Nkwpm+joA/RXiy4I
z3G9rMKVOkavKvqTY/KaLScgJa3wfc5blHA9luCorxCcLottQ0O61n5WyBCo61X22uuph7Boqh4I
nxzisUNqMUqXIJB0rtu7Psupa7frIvCvwxZ+jWqbj02l/NOp+W2EcPyxKGULnBZ/cSdPu3RBvRHN
v/EoYan7nLx2PJHuh4eWyetmSO/K5cU1iKsnrLbq26vPF/OQ6z06RrpiEsdxpasaopDgmLaR+r8C
gFgjwSmS7JhfoTbM2qdzZt6ziyHefA1JKaRlhhNrkupGUiacMI/RCHWQ6AJ2x7JER6rNS4oOSl8o
IfEueNR1MvPL3+YB4u/lD0JR2bCq+cMdHlDLzU3NSAUs/UvUupm+dMULyOohhXqAMfUPok16zHqI
IYd6HVX7boQcsNlbo1WF93A2QyQSXNqxmGP7XlynhgpOHco0fkrmze15okF1L+LGPGcyzZYGe6TT
4q33uu1Zktq+OkFGFodPP5aL31vW72Lh+8zNcGqKI8Lp0zmEPp3xaF/DDbOEDMwgw6uQZSNrZVZy
Rzsul43iRpgWXXjEOlAMhtdqvZ1REj5lOPPiV6Sv/KB2bqPtj6rQgkRdZxk5YeKOotRR97vnF/L/
yoOy2zdui74lVFncmDM4/NAFvKgROhyujy3P4vguHEdeNiaEbdfGIgGcauU0tICAea1sFMn+j4u1
i8Jufxw4oF/T96JwgtOCrXEoxPD6wLm67R13+qlADx2HkQUUJN15LUEvn3dgqorJavqGInVSgx6n
fL9Ee9WZYNd/KY52hhc6IvGXRKCPBUxHFoE9QEMgeLuR9HbQbF/Nbh7KHM47nx8x/4ttIwW91f3P
uD5pwwlZYwzGlcfPRMOtZk5LhP1Dl9Y1SQ319Qgzy2RO+/8aMJ/HXViJJlSDawe4ejcaxpAEAabE
9wly18ChILzdkMXl/DL8LSIljn9QrBc3xbMXZfTMMPYGMWr/3RN64hzealD9fxph24043P/ZAbgH
FhCrzxcLnvll4l2ddc7VOFzMwe75ClVkm8vHaTExVpNvhRNcouxoZNflkTgmQKUAygF/FVIJDuIo
OY4EFI+RWK6zTdllWgWpZne1d4cObHJtuY6KXT5jGV3pDRDeTM+1kYdycnmPVsbVE5xZZTQHx3Id
2Ctec56qdEBnfjZEflE+GPx0Ia9NYkVdlj1Br0HYSMJNS/TyhwE0EWL28gvrELxzBAvYSShEnUdH
DBT+soxAa0mTrKsLBJyZXJEk9d4f473FMBQoWxjOp8oHIcNbLEGUCx7dST9oHZaTaTGEUR6MgraH
fq7ue8YFNqHPABRK5U5TgtBUXIg+4csVmVm9CDx5/rKtnYREp/zdSv682qgFAMcVpx+/VAjcNx1+
ylsbJR4tP127qu/eN03a77Scr6MZon8PF2YS70QumGU8V0ZUosEf/f3d/Jz0Btrv5TwywxBdQ0Of
5FEast3epWpyw9/mI0wFOXg9fvxZDtHjRN43+qOEiaYJOBisoU0KnJNUsGPHow0aCurlx3SHnSI0
f3XacYV995OenEuVBIOqzB5242AzyQuVbHcygo4bFFyx6RmqmQ4EDQIsf0ql78C/y24BidfQDI1B
M7VslhU4cY35M4Wv+rMNtbJ3zk5gKjwE8vw3uyqU98joZ0GPqDfpMgIMu2r7gN50mDhKhnQclP+M
RtKxvDi5BtpyK1oUUdr3G43XppzOkzfJ3kcsDqkeusQMrsYYYTfLIRyYjkTLAxnSscpZuJnbEFXb
XfC9eP++eWE5JxAxQYLKgxIaBEu8G+mtd1Oid8+MTZ3S7If8cS83QLd/8LAnSRIxx06Ar6k4/x4T
utAcTdnufaTJXvMzcs0mJEVmb7tVMzgVTGfiHMNN67QmZixyTQUR1aSEUnKC6B/DK1klkI1IxU3D
/BJG1S7lVPe7xNiQyQTikSoV4Mhj70jjx8juQZnQtz/wj/xn2eL+cP4P89yTN9CQm98vx6mX5fnZ
9BvpK9agrhPqaWV5qgptjbjEecgHaQMUwmjNdvfSUhrmqw3vn8d2EI3BvUmyLS2VEySdv51WtwIn
73Pl/syb7j3uByd5FLt/bDbPCnuhDf1wgdLSF6fGpd0HLbab46pLYx9Hap2MdQAuuGpQ5IRYeof2
2/GzC96b7iQnUqVTI+Mjq3PgjhxbUeiCGN1NmX03HM5APt1FyJIbQbmg5rWhnDNGwztUM4ixgPVq
jl44kt7oZbifvjk79qyClxMlomx79A2igL4XLXu95RqTe+moK+cQYSeaOUDSEHELUdvIRd60Di4i
ii9p20urYZFgAHfVmRbWa+EnGnn1QnHN4m0rk2cuWWI9JmB4TDpI0rI5OdE9WNxfZE+v4FBUWlGd
FnN2c9MrRlLp/9qlDIlypfZtZpU+r2sqyT7e3ZZsn29W9TexxRardIIzbjPTK4jiImtG4dIyawNO
9u4HXHxzsLgMtiWI1eV61HzuIgGyYNzmXChzXmgS9sW4h3hXJ/S7TDCbnCVc2EfY7kyrSqFdnbwc
GUEvRoq/JJqYFgcyDxk2j7VHEE58NW6/BFfHsP0GVfHYKpfbpsxVz68jNA3KkT5cYgkdwX0GxvIa
7YmaM9SJhyKG4uP1t5U0nOGM51dO8zK31pO/S7oyLcHGWCqocq7QfQEzp2n4dalXAL5DrDWLFk3a
TX7uwrYO3gxb84Vi61qiCiEV7yUo3AFccvuVs857E0xBx3XQ4a1zjY4JTz4SxUP5UiIEjnoiI+cw
bqK17DDDFDiHysn+AZn2moKwWLcZaFkrq6L+vHgrl7pym5cSu4Xf47/BsMO97JJv8o9gkGXA+R7M
+Qov+X0CqaJKZ09zdAcZaG0wkBjOlh4IsFvGnb6o7Hek5bCq4HsnWUrn9jIpsW3a4r6eTsKSxGjc
rImiKrzbz7UmojvTRbnSFNDlU+1u/pJj/yd2Kk0+paAUiURlkYaXwg4Hkp+z5rNwf37SIWZ16JzJ
pQsNxaZFb6QC+mT6OaGPfMO2HyXWlr5DKj/DNW5+vh+mWXg271H+2YR4aNzSAb9qG6iSIZ18/Hhw
ADvu1qDZ3D4XzAULhQRAx2TxKPBu3m+LSw5ejF78ZyPclA6ytAG2Vu/K2SWCwDf8uUGGFTtT7C5w
54w97684WpFNehWr5dMh5WgzNE0WefccsrHz1dIgHD+98KAPQmhlt+KmJ457h8QFGgqJcHZp2OCq
zoekQ2w1l6UuhlIHI10vcb/dh/3BXTheCkvrrArNBg7VOBBzB7TpKxGzrYzlWwENNN3RB4FkijFF
BglzHTPFDZejUH87qOzdWYY3x9HYJSIVv0/ikSWKcJVh7KwR30Lpl96I2lCPAKZtYC8Cjz3kzwup
vUuIAGo/K1uj+x149BZVIb8rdyi4YjadyBsqTIrBkD2Z75bpeYvkWOou76YicjsrP6EVatvDlD2N
rJBqt2Y629jDTKcx0mDRJ0/KZKRt25DJ7pnLUxzXds/hABxtKHdSuRqlcuuZfNrbkg44OXmsEoJg
gtCUVx9jX40vu3VBtZkz4UvC8xhIAcO+Zz28PvJoJW8NUMeUvD2hZP0b1cu9VoDw+2+q544OsHtn
AxvWoxWcLzP9Kygd2QQ8zDBRUb1kYKT7B1i8ofFsPixrkuH/BRPXC+duJulHjz1g4tTh/wQayJu3
8shRrHmYI2xFEVoHtPmISCf6RQboqceC1VslxLx4+lfX1GTCaLaveK2nCmhyyW06wJq4LIJGPguE
k0vzha0zHdCFk+Y6izyoY1k7p/cOVp+a8YhO38w5v69ZE7VVk2PTP7qiQeHyWw6FPUlS23wEm11g
kK+iQWMzb/N+cXibvexmUCSr7yeG4q1b7hQub7YVx4YcEpSUZ/yGwxhXS1HDem++70EoWsppZ6iC
CTGsSo2rgYd0wXFrvBNpiR3FoTg7UeE6DBdvpYDCSSKCCyHr0VZ5k6Z0E1wGCWUgos+BZxP9f1G9
49PhUW8V9uqK8kJa/NHlzii4YV/hloBz7X+dodgWvn9UC6jlIewS2TTfqlUNzumyzzzwFsr0O0nV
2NLa5MNhElQvxSh/ps9P2hsYQnzSaPdwrtjDtPOCjwxeSYT1oeDKNtWN/a0+ooYJMizswvT0LtAJ
dPe1hd4LqeSSqDtHWLNa08dEaJxnDlHr7PASnpdauel9+ColrEpgYnECGX/ysqc44TV287bSBYlF
g24kaaAdUH/C/Kj6d7YPJhkDrnl8FxGXMugJEaVHjSIlhT2Mj3dNsu6w6K9a52y1EBGp0C6wJGBX
qmE54A1TQZn64QVeJNMrjsDnW/eJEjZqL9AmzOyaWOwCkdNUVUDhqMaLpb38XLGdEGKtRmPlyiG8
jOUae7g7ganZuDYInQbnc3qm3WcQgWVJBQDcnHI8At7us0WD8i2V+OlmhgmOYIaLeLy3xzhCKu+u
Ka3NpQ7eIDu4Hm+D+8QXkI8DtlGgtwN13fRVY5LRDUxB0Ftt3rWt5zvPP595pPWJ6bZ7hDmHA7k0
qYvKfePhGgD7DVKEU6pTJndt/zqLsuL56pNSXOjpIK/ZgJW5/fXIaj82FWH5fenrG6dxm5UCsmII
au1Bpqkq0EOfzDBbnPO7lKi9AhhIhKJfjSgXvVL8ut/BqxD2WgvfuNP3vXIGNzubyuOPrKThZB+b
73gISnWSkJN/ISgofYEOHGzrYn2mlFWVVkolS6TU32ZvAt8JSRWFQwqgmvEM130e7I4bEuVQ1Tv6
GboJP+fIWllEQOBo51DyXGkmVq4jiUlcArkG8aT5TVYtfYnv561uBlyBq8XnqRDJEM0kr0gl8315
Q06SQmV/jmcQad3ScTjlL3B+bGQUjq3EAfcRAgyL+OeXLg3DnNTRipBZ0lNpT15j0/PxIcpRPlju
iAAAsUNog0rdAIE3ywDrzO9O/836TdviAt7IL68IL4qkaIwract1coyHYb/6fFsObdPWo7UXO90k
jfbDpkDo86EJifQMYRZfN9Aj2NZZ9gNSpkmm9zs2H2pAEqNld9VqTZ4TOHFEO0Ax5oE4yH4CeChY
beevg0tbXZaLga5qqeLYiFdhEpnmzzPwwuTX5DalIMp/a2CghR3z++jCqL32wQjVBHfKyKmRnkvS
Y/0IGpw4fCIqnq7oLOru944F5+KydfeBFot9Y1XNo1JR+bmdKZwH9A0xtfER9hLZN1fGlWCVCggP
bSed/XuLBSZGosbHsoXJSxh2n5Ly9uMqnRCJ+aKSspgFDKgD+ZnH6iaGNeGf0Ll2RsLRm2UzAUDu
/cgTjF1VGhoTT8xkzI9s9+ONaWJ3SmYRKJY0UeMYhB7bQZNrRomOUwUqTqXbG5Ci04iydwEW/0ci
l+fuaysSZXHqSN5ruJGa3erGM7aWMV0X8TReOIP2m9TdjqFt2p7XLRZPmWUO78V+uP+lZ4srPA46
cqYH3lQmH32YE0Svl+qDTb39rFiU+HsUtqPVlMc+xevg3JdWdoxH7J4DlNtEDoJWyXR1lDJ3CPZX
4oWZ9l7+Z/dQllSVDmj8/vD/47JNls9R/4zx5VufT5/JDeSS4oIvOrRkXOwvcmhJDn/1VgdAjqkt
Lx40CWIGgT+2LtYwNeayOnnyZVcE1DzV+iZn9Ahsr3Lojh49AcpIEwBBTQlGXpEFwsNMxriPhI/W
hGlRkZ1XqjjUmVBLrnecEZ17SDg2aAJY3h/3DEj/w53xBg5sQcxneZH2iRJtEb83D2DjwpoyX9qf
f1tvHKw8vVue6WX76j2bhRBta++iDPDRp3VmglumXUChqvfwz8VRzpqp82Jz0jHNKn6Arc6FzdWX
IlrGu/vBI9LEAaE8SltZF80pFH6BqbAlF6ztb5Z7fJ36y9d78DvAcSGKff5kMU+FGiCoOVEPl/Rj
ZS3de8i3d4m1JUHO8nFhlpI/XKncUbBwAq2dHlOqurRvotn8QQpdUpzT9t1f8ATUO9f9sXG+TE8M
7YHKZJcOcMKaEgiSqwP84zNJZu1xdQM6SMuVChIAFJuiMb3WOqN4ejAobd/g8mPcysW5GL/qckiL
pZKD8qeWfH6SArkQvNXqD7r5OysDQgvExJTm15aW0IY+Hmu/yhcPofoApweZeh+0qXIXdu7+BISV
z7OWrvFPwkLE5YsNu656XIBSHLqXZhkHwcUGD71e9hYudfGU+O7EUtTiuNk4Y8N2lUV/cy1MRfkN
8cllR8FZ6y8yf5/3gowBRhGIda3HIXb5PjHLlx6m8gXr+M6+U5n7GcvCbCObJ8/YhuXcfMgMi0YK
27m5CXC3/RebTe/xCCX9U3Ef01YiGofxTPR4WrlX+8Zg3P//xgZ8XEUekMlxLUfzfD9naoMqMN75
jnSFktXQYcA4iQb9hYjvp6yONHVzt9ar3/ZeHabavjguLmSTo9Z/xr3TIWU513kKC4tj64TCih/5
qUOpGEqM1kMvxah4qORqga2eD6WB5r6FpPNlN05vwRsjuF0AOItyUQx05SEJ1eLbJPGYrEnIGDFF
GfVytLHIiEPdkV5igRbFjxOemAdFJjVMWidR8UbNNc74x9vvOvmNK72nxGEyPwTQcT5oWVCcHNi1
isTTVgAAugUBp4JuT3XblYD7PEcdrMsn2TWhjtjcMmViaY+6lfh13AEgoZoPbvJv6FWUlWaAT/B5
ItFt4MxiGF5oxu7H8mMUoftL7DTwmRNcRAGvCgR3+JwTZXFt/cVToRF7SsSvaAEimYqug68BZlDu
2vwTCipIofTE6xgHo0VKHnB66p1s8cSI2DL7fxcrvXSiAPjkCugIVbxy51vTmS6yqmA0wyv9T/cw
kFBIpQ4VVkFlo0pmhNw8PJYRPRCYNX1zItyoTDnG6IcHNmV5K8gPQlIW8emm/UEGXeYv9pGdVzh8
jh98XDZmspglXJdNvrZ7LlvF2HAeaWFD1yLS/I9Y7B7umTDhNwNXcenm3VWVxE53c1LnTghLjSz5
hNd70Y9rc7PlNPlgZ2xDBGG1d7yhnFyo5sGq4pau7OBomaGn/hUrPZ7DlauQJPnhmor7yjrfShrI
1sCq9mqaWPsdMxZbcFXX90y4WKqDoBoHtw6+FEgKECwupC30bdrRyDj6QLYwvu+oxdUSX8EgHwIq
/7A3cdaj0tCoYUx5ioiPS2Mw0cpuBtpcRc8EjQ0uPvPxP1eCKkCkQZS0XL3h0LH6aqAl1XYAgRtM
PMmq652nKi/GjAP/1VkuBhpavpFeDbIHLw2BxmaVWSl+Fu3vVcoRDej31AyujANs50BnfSJluhao
Z3orphCmFEaTGFOuCcfoCJmLPERWsfIPvZuCs0CERrxkWKlbtRfaZfr/YVTZA4boG4vTprCs4ghb
jNl1d7RFZ9wkAACemBPJyTJ0GVVO0yBhBHMGCCQ76aTLM4YmT5RnN56DUYdg7tWTSjbpOlNUn8gf
GWsvixBchwPKemF2vXAbnlubV1PfqHIYj4A1tEKItvgq/Ms9ooD8uz7Ne41ttIumxQVY0UylWjVW
B45EmSqz37Cx7QeVGWDELlIlDtQqwT/oUiP++HR40lfwAbKaDmrLSB1fMBkgciPdipYKq6F5Trpi
9mTAJYGZnaE0i0UTL28aSO5YlSH03GYYuWsph1EMnKO6fWTDxdJcArDkNqWlt/+Xxyq9HShzimL3
gMvuEovsm/izf0WTIJithSqCqBFEgo8bSsQgCjiztGWzKVwnkJkqadnFLFbqgY/qn4ALMvAu7Bdq
OhIWRV1EzzGgOZ8U4eY8K1AdaWkaR18L55yyb7xvDe1ZSNbw6Eq7jfBQ87pNzo/EQDO5da1AiUKD
RReT73k/B/InQNp3yu75IYW8zC5BMOI1zTHVAnXrGJx0TevFSNgocA+XlfDlOe5mPoGgBlmoBkvC
BCqcsQvU771fjsoKAveuQRJRReZbM+q2OaDT+ym+1MZVx0hk11hZIv5jhdd98JokfRx4ktDlhmi2
DIbYX95YkyHFX8Hoszzxm5n8wWWq+49d8STkRUf0E3mvgCl2cZK8aM1j24DUDw5oFzC/92P6l8tT
yc3E3hSn06e3b/QAAxI1nIryP1KTgbwJDgdKUiU7kPp1yz7AcvHG0ZZG27F8bPYF9LFD+xRXZi2P
y39QMR/4Br12wNQ4vKjGdTGcP4TSCDrzheA6PPLtdOJrMdLTnLqESBWyg/ZYXjVnK8OlnmAxB6VK
Iqp/NbSOtpYdFBEJBtkyBHLPHUEJ8bZcgFXL0h0LuS5pA0qf/Ku3RLHJx4/uSjS7S7qza/5VahCh
Rqer4c7rvhSv1zG9slXfpb3+FYXFJFDnnKPGm5oalVZehYjRVLp5oA228gwx4qzyt5Z6cty6E3fb
wSZHgCK7v/JG/9kD+Um54/bzKjSZEH2MhfyBsz9RbiFUGumbw0kYY/1h93GWmh/k9wuHghE6drJP
YDf8BqhnrBK7LRgIX8D9aXiYIV+Fn/Vt5fKSOGUEayfffejR+NBekFn2vKSoeiGFFYVYLaMU3tML
TmSoK2z6ggtFUR9l9/KcjvvJHrjm8MLaiGvpmnOKL17k2Da+DKwmQ7Y/VzsVGADG82le/n87NR9C
pfj5BXqKl9wVs2cS4Ch0NnTtKgv+GA1DyTbIkfI9wobxRgM+wbE43akTcEOgnYcS+17HyPs0NgDT
srLg4g6U8Rm+VaqzWVZxxvZFk8nqX5SlvIv/wqzgmRQakUdyZWAbwZFh7kqARquZ5Zd8vWF6lJEb
Td02RINvm3K8cI7P2yHVZGjg2afmkE/SoVbn5oiOj4ovEsHG5sMJdbFGKYBQQwAtGIFN2ieb7rG1
x6cPC/Iz1EtVFdIb/eRe30/3go+t4u/WqkJOBdsZi5fc58Zo8DHQfwgejuvzW2MmujQKo+qlxn7Y
jbSXwUCaDWcz7ciI/5B04OtVIHFAIOzHcA0Y/rpUiRctAzgs6xehknP/s8myr2C/Y1LbmAh8dycZ
2sVo2rhm1WH/xGkviCX92dS+1XB1CezUHj6a+0BkjL9KjYT/QvNZ+3eyEUNE6XN8+HDTuLtyc1nX
SD8v7uEdD02CFHeM9xhA1+UXR2Vv94MHrfeCOlHFX/1f83rtbcRst4O4lomii6i1+ASzyKTWMR84
8rwUhGeKg6OsnQipBoYIZvJjqISpkigNOXug0q/QuGbYB5WKcXPx5S6a92QHmJNOTJuQ/UJSJO7B
jl9/PUXpXUMcpX+Ae1uYL2CrGmXge0LxmV5fcsnA5z85K/Jx0+s518Pws0APcOXaO1dADHM16kOI
5uPh9HmfSzPIcDHxvh/66QsNpu+V1en/rfQUlzPPuuq00XnFnn3q13H5R88zvUXBWM5kuO39ew+z
dhzba8BsT0ikAyA+zsoDoarNbDvs3f/FrkTXJS03ZKN9hnsAeOdP//cP/k8nPEZ5rcJVb31HR5c1
mutAAZ6rbQ9XClBQDohkGNpSxA56//RwVWTegefW9OJ75iYjUeKKXlEQqGkw3deP6fgJPOzo01OX
1yFO9i3AP43TcJqmMHvgJyPGFlSm9iDlZhOVdNZ36naj6jNeJgLCWacL0awxoGsyINOv/uAWKf5n
HAYzU2XkoMsRdbHuIkM4P3Zf3ccDpY9HDrSXUk2WQJaZ/a/OYGjFhScS8DWGPbSne0M3yN5g6o9i
3LnIjwbgjpikayE23fxF+V7i33jfk2IhIshymI9Wm2AiboaXMoIRJESVbKizWMvMRtLijWarcsbM
IfdBFK4W8TAgwcdAsQ47oG1qREinoJJcVQr+iTSg9sDhfvy+BktpVZslIJiC8OIT3+K99TR9Mz8U
bpy4Dfqiqt0z4hrI3PbudS4jeJMXl7P+lfdaIq4XCfVzFkPhguUu6bJnM4tV6w7N1goclVdooh6F
eV2hgy9pVgYi/hidq0QfQL0SXYkWJ+dSzgLYh49U+Anq2H0f7ah+S8jwdMGp4hieGL/XYsbLDYi4
msYHJFWpgCx7eXzmnrv3xLL4s9bBIwbfHZYWbTNknev9P758cNYUC7UPfJSHbxYtgCxWlfxVD7Wd
4mVdLKsM5mWdtr6gcKdzbX+DqoUCxPAEw5D84kMUVCvATD8fTsVM+C+C5OWtbcHyV3Aq4Y88UFMK
NWB401ifq5YGU/f52uYHHjkrnd+6e7J9Pc/kWaXRVjjoUmac1O4//LTl441ZDJ0dFftbQT1Ch0zv
XXIWMs6Qj2PCmiEvPc2HwN8XmKftNjZMfy2AEg8GvSYqK/pAM3pXlALERUiylorinq8gtbq2jgN/
TWQSZ+FqTRrFm/WwXqBSnxQQLNcJj0W9thoRUlRww4YX1zgOpF5mHUSYD7RzZq/4MvIIO3r5omqf
z3Y7YEChR8E5FrHVHiESolJjFhWtgAqdymoUdyp1qGx4E1qal603xcS5m/Ueyuf0pMMAS/frN0if
u+IXpXlKIPVL9LNPunszVNmY6c2a5CUQtwPhoZPHyhqyHDC1P85gU0dDdXwoSyovCTeQ/OrhpAH4
QroLMppdV4eqnsfQivlqRD14UFxrt2GXZ8jD82lRIn8yDwoseXkOCRWJy9G04hVpR5FKc/J4vANA
zv4N/CZQqp/9yYikpISZnT2gdTFQw9rTBo3wwVGEV98TMipTUrvwoma7Uh0drC0+Z7V9mrxDBUdK
I6AIdn2whSMisyat+J5esxWOpHnBN+Y7MU5R/IDA0HeU+uvI6RRSOhggwiioUeICc1NERaxYzGqY
UR9jUecdVHhF0Rmkke5iI2OXpo21/buHbNNO44On1fH90g8x12Wz7bdztcjJ4FSePm4yW23XxZKJ
HzgIX+CjdAOwBwlwZaklkShd42jv3DWt0z+PY8PPOzCRgsKm9vJwrYr+11o1lHM3koR8S12yGaUC
4UHQAV68vh4xzoxZcLQhmqHCSi042iYbphg8RCK4Q5I5GGzSKm1wIaYdHOYiaHUIjAmAEZA90Hhe
8X0Kv+61y4uTkndsyMm3mTmSgFZRFKHwGNpj9YlzcytR67P7XUNjF289KPy7f2TlMMeN9sC9adBw
R9UfvavorRmNvK7ylT0PSgbMKLqMCYiNoksnPPNV4AV9R2xBN93NORihNz33V6XAa2KBGMCdnbru
PPuevLxTh/uqUsT8bgqXzfouyTzkTI71TnuaQbIHdkepuLwV/5dh8oXiEZHN9pvCtVLuqGHqSTxC
QQmvhG/gE5nR6OG5pkq1ELCZaHOYz/KC3vH6sHc9f0PsbSvNTfCihElo0ikCZEDHwHG3DRyCAlAN
y9jMlP9joBqAQBLVMIRdxIdLS5miMFVHnHT5q4yhD7i2c06e1TbANFoKctOc9tD/qWAg4qobCAoJ
zZM0l9ipgiDFRrTI6ULfVoebMhDucbSsoM+b8uQjVYIYG27ovxvbEZvIm6H9pbp3HuJsczPSE7fE
gCx0xUemmw5MTPsRjKf6NXVOVvt7jCjwmueTLQEnkstRCYJK75DWlubBzaDIJvjvRMGznuev1Tvq
4yWcJLftynR27J2bZFwKEpM3KDdyBegc/Elkb7IEkOQkojwGuqd9uwpJ5Ipgv+my4qdBN/nz+D6S
UOqd4PBDJ2TEn5v1bY8PH3/iKj6jYS0DB3lAOGD/i0QPv2ZGUNPvhQg2ygCwpXK9EwsVJDWWFU3n
TEkRWQjrOcUgGEXO8D6ANWGZ7gLmZ3ECjSzVvOtUUlQT1sSd+8Srl/nipHNRp4qPprMeHxk1KaMa
u/qiahEzsDIWA5m8GqC+XBv2m4cBjnHgl6JUU/oWpGOecySOg4WRzF51U6E+T3j+iusCP2OLyq9I
IUffexMOeqRhag2ngmQsX6ODliOwgMb76pQJT7EZLbkr2sTntONiJ56f7wOM2/xHvWW8DF6C6HW2
N6s/nEnICUHL3m/C7YDnPD/PlAA7ihvAmSjT7lifymm9dHJhC6/t0wQ7hREy3DLRgEhPMafhtoWV
v5DV2hiHTeCNLsxgzdc5p6S2+L6PwgWlbKq5DI7SRZ0o3GeXNAqODzwD/iLjAikyVuHBOxVPFJNL
oexsSHjueKy8T6lopsduH4SJSgkAX9juUx00Aakt5+qQ5J/LvDhnUQXYsWdFHhtDHMjdHRYoXIX9
Tl9N0+rCZLybhncNhzRratwAiqs9PRIM7GOAbAb3qtDHqhL3TQkrR9Z9wQWaF21GbhdVQzK5PSyE
YgPuzc6fNDn5291lxalhyZxP9b4U6LGEOtsn3KIVWj+e4zcHzHN7HqsQ1cwYjc/tnkC+JACWExhJ
eRafIJzj0gj+tmQ4QrYqB5O3+pNKo0WYtlw60kpUp2QYH0MuCFev+MPTvlZ51y4cEpJd+TJh9FKF
lREtkmCS3UaA7KonOvpWu9V9Ur/FgHKpUpcZUG6Zzq6p501RGP4A+MzUQPZIFIT3VcV99yVH2tk/
Ky81wWKsbKXmISBVH0sdqrc3LgEcvOql3STJQ/7UW4KVJDSxGGrTTQO8Pxf8KtpCLgcS42K2HYR6
AmN1abhSFtHyWSqOH7n7IlyqO1Tl2IN5hmJsPRMzoACyH3FaGBLEZh42eQScm9n/h7jO0O4QaKck
JDWUqtWju+MjRW9x3ipdWGmZigPTF3QRDzIvkfgmmRUUSOwQszFhvQSINnHDmsUV5zkyMBQul+cS
uHVQUQcDNKtgmM+hKOAbDCUezJwBzfz374AYg/MB5TXMIXTfoJUYEBzu718JRxdFPnD/izqpDtwC
ymgU1b32zR2esQaGmOSogJe8kMQgL1CvjYJK76ju+9GTMicHyPKzc70IGnYjrI37xwBgpcmjbc3n
PLYbv8sEe16y8MbTXZTikJV6JK4mbuiMsHwouk7082S0q1l3owWGneO5tBqgwSKmZgSOv2L+kVnE
QRlSgbymoiHGxU0M5Wrc2dP/t4Vxu24XoLZmdwlnJyRGn5fSvpAe7MMN98qYIpL7eDe9Ipf+XO50
WS8vTnMNEhqGMCxEAjuCcpbcqKdHWgSrNVrPHcc8xC6v6YGE6bh2Ox5699br1Uf3BKhTru1wJNi/
jen5eRJ2uY8xbsiCgzJMrgBKLn84CGXyXLOeGLPqYooaH7aElvCOdQeZrwA1HzBeWJ8uVa0F5ImG
APzkXm4KTmTy8hoPf3wD+lyKKmc/3Wog4G/Dlt0Na0atsQbuHFGglISElvp9KgQTGg0ey3D5dFl8
BuBG5JOA2L/glKIhu8dlsqAePQp6yzCaGjJg7FQgbX0OiP5akO8nuAMIH9gBo1whbgIuesSXkmPR
1GUrn8XrVZbLgOpztwv9jhXFPvyGbZNRKwpbckj+o576/sD3fL90SL7GoCk+qO0OaDaXXQtF26xb
/N9m8MrRHdqlvDJXZPHPT7shstcA28JGFjWI3uKsD8SI6DGXgxUzZfpK3/syGHDcw7YdN3Zw384g
WeO9mUZso33TzGUexbxib7XksNcx9PtnWfyJVkYUQFFj9nUFskEphMi/JTdHoOGwoJVftpajhads
7EQYS56Qojl5CXQPY8FwuG/42E/hr8Hf8D3nfkaDn7lTfNIN3XgGtm3YHBvWaG6z4HLJOLpDQKiY
y2YNaAl/Yoc2Gc7z6/XO6e2X+WtJlqqDYofmsc72ie93VgklLjZJexTvxV2gGfyQZ2adpgBEjpga
w5D+ZjDoWhJR1p5iIPZwdb8Tf0cHNiNf2VTUbyQHxX1DSROB5eVnYYb9F601uraRWSyPPztA5r94
g4fnFR9PEjJlHNCi+xJwOfxFRTDUBr0SEhVyD5T2H7ugSRGVFmgrDMaHF9p+oHim2qDLNGxX7u2x
vHIh5Ig9aDMthvffuN2YbBWJf2HoPQUpuGWCCeg6wOwmJtMMHq5OkC5rxOMHCsM0OD7tc311eVS1
1bvHOU25ez7MQk5OVUVcOl4tYyeSDKOI8BwU4Qp6BeVz6f3mX3yYVft9d3LxY6wqd55sX13qB2q+
tqbNjdU98ivyJzkbpLM9gbQI1kgKqpKZixadrWoGifyvM8UvjmwnFk3aNLEaWTNOZ0kimeCJ6MXU
nHs83Rp8ANDaUCDfOv2IBpdbBSDz9r+pld9bdbMi4NOY60YdT/mq8jr/s8bpL+q17ahnlktkLF8Q
ZuLj4NeA7+OqvuF3/AXE94iMriyV8OVmF1DG/HPTsIEsZLHTYIfdu+QnQJwSOjeJ1C0CShgwjyvG
C7q3pA6K74Vnx+DvUdlsoPP0ymD7M2wJuogPfV8sl7Y9WPS95W9xspzbpUU2HfBIfnr34aDmdTHn
vG6YPsR1661puCJXQ0AoeoXcKuVFvXKDdUKSbwalGkrSqbF5VEkzytQsOCGgE/AIlkevoJfkcnrm
3vEzxUoc8+CivIZc/fB9nHHMqyGRH4/xDsbsSes6L5jxLYWkA0Ygx9DucJjggFpmOa35bU7RhYDE
vgQvFjYDKm8VVZkSB3M55FAqMEeV05laHV6126o7zG2bUy6LDZoOJkVmh0jar117RCqh4+uGX/zX
9e3tH2ZgdaXiRQqCepB87MVBc8Lp2TWYo2F7L4znUkCREVWcq27jlPx6lGwpGKiqV0Fkqdvvy/8w
wFx3QeD5snMram+2o5Ta8P1+INcPrEWZAzI4fpKCYjx2UuQR5bmu5loWMNfMt2DZl1BtbxOA938P
a//CrZZMEjRA3iriquhs9epA/YK9LeRZnY5Wh+KtxbMsnCm74FrS8KeRwvlKvROiZLlFa1oYw/L2
uZP9U8DTQ7VxtLdM7uGRdsQStTw4hRYb3JC7L0zFdtPtIPmQ1LB5uLc5RfDB74Sf6JHXfdIrVnro
EFTnLiiiza+dgCmVyWe85Ce/lugK2AngYJSS/q3HkvPNvl6gZyLOx9btocxdJ+Xbw5hqdVWOq4FZ
HnXfbs2fG6wk/4d+nJrYOTjupSTohuOPr6qiBgb+x0OKbAKyHpCA1IBFUBGbwm2EpEdS6+A6aEzb
NhS/zFNZb/nRRKrcbSUMLA6qbliTQeNuh1rWeVxUeWXoPp+J+U2VmhnrMHAauTy7wba0DFIejDAz
NSNxkJ8qOBP1ekh+uBVdc6yaZGxoJFj0nGslurCDfYJ6K/bq4N1tixsjrfav1XqEgNXfi1OhcT/a
SBHW4HgGKixPw/607B+IBtdG77QB6luetaw1L71I6myNTt0b5D4Grv0tFHTWPU0/Cziqpmye3cbi
lzVh8LK54+3PX9IFe/7ytjHSMbTTn18FK6Jd2up0WfoVATb3xpA0VLimhMwMDIssVYOPJb5P7aCj
iTxFiPcGM8YP4bcSCWiwDfBk8R62m/pUBaaTrxoDTI14Ryk/o4e+Hu+QvAtLbwAPQ2u+6hlylrUV
kPFCubQsBZqzGbX0v+ZpzZy6BnT+DK4ITza3pm4SNyxcSEsGksdasFrZIwxvYvzRMZCcSxOkmMpA
HYEDOD9GK4C6EHA8BXDdOwxg9Qvb+jlmT57o6EgbqZ4G0acCDLaK/dnaLSoC5sWX3jNTIMux4fNU
YLDer/s/HaipHo5/ik1bYrrU1ifw0b3Id8LmKpTnYC+/AYur4EE8JJUy32VCW4rfBi6Ibt5IuSxG
r4hwB2NGkeJcGedUC4Nby8veUg6dtRgM1gh4KVuLhhNFfDjZseTuVNX0RICGOIcqqy8Kit9w7M34
9MctL04FwwietEp4ihrgF4CrUFoMerHi3mBdEUyWn3gshK/5/4fjMNtTosNmFvF2MMSwzpUTyvW0
p/ZFIgRQzLb/CzP7atDn+ZNzy91eqfxVcAC55kC6jqwsqyue2bXPjUdLJTd4IkPku0ytqAJCqXPR
otflYatcFIhEAQU0jo+0OHvceWNNWkkZhGyeUj8Zgc3D9qiJB/im+tTFczZQmQy83gjiusmhJu/L
t6xJadDJ+78DhY0Vmb+spCAOCDPHrzw5Y9A4bFMrXMXJY+3Q4IUX3cW1jPNHQoQa5VyueQmCdLcj
eUG/8qWlqnVV0t8oPUN9NKl6d4CCXfDaltRHwz3dEOB35XZJ5rxvUybczX/ocLzrAt8THw5JG1r/
+tkg1GfLNPxAkBmZDRzm3kCV7RC7QxLHZBjd5EMEKPzHHfF+pSp5mvYyq5R0msPC5EV6A/9PJ8MX
qsm6gUOx5qm9hUIE2Ymt1hi6au/mK3lStLEwm8Xc39enufSBMb8ZnnRPxiwv5Fq3Dx71XkbHSaKO
FOxt4x6TOn0ttWz4IiZPTux26SKdD+TCDkyTNA2C8mzxZwYcGtEN8ieD0JU4qjtrh0hp9fi9wiN6
MnycLgq1b+vwQDaysn1K+tJBs8c+BBxQn+Nys/6IpWLYy05G5Ol3HYvUTQBd4Tgg3Mxe4e/FhP/M
rZKv4hZzlcgRsZWTbxxe17M5WYXiKBhUdYCvb2qVMR0Cr5LKLiROAqCCHvW4CrUoBF/TRXUL4MXb
sEp/HusIMxX3dgpjHRdxeCEyUolWozIyaKXLmW/4M57EMjtMeZ9O2o4vqF/Eri6Lr6AwKUW14b1N
VVb8Qnf0xdZS/XubtZ3ZW/D9Z1CQwFhabVuSId7k5bFY0jtV9QEy/crl8k3ncZSbnF6do+IQTK/w
TTsicRS4N0yzXrAtIkyHmHK3lstfrY/idUJ8h9RclGVh0MhNwMYaI3nLpGM9tWAhyT67eCor/ezQ
Y99jU9k5JfmJGBQcDC4KYmEdgmsZMFYQFhIBntUodsWJ0er69ttq7QtHOtCTbyaaCYLBIKfdCySt
y0Qh7bqDTRLgGhCGReK9728WffWI+kCChuoQUQ19TE0gUrr9fAhG1Ni34o5a7jh3CKFDmV9iLhxc
3GGmYmQGCp31+oKegBozU6HTHgG05E7azUn5yWOVP9JnKeGVXV3cdmip/UFtZqU+/QScwcpYmcPg
X2ZleXNj5dySyNF4RaVeaMj8ggbGMolFVRV9d/ix8JyiV2Ei0H/7moNUoFZS8/lIa3H1VR3PI0A+
9CSAzTR8WLd4QVx4wPI7UdakLZcrWX2VGuWIFIW3BtqtJuhEmODINE6E5BqsuEjq/56zBdrG0xY0
7glXwB32wkXiPZqkBePCgJOQxPj03y22q0V55p44k54BaLcqfsaPe0G0UNEERWpLECT+tGqWW+5M
GWu5oaw8Iqw1cI43wpI+l5L94QiifWLfTrdnOl/caI9r6dlFOP5I0Gzmkh3s1+vVFPeA1lU3Mzu3
eBnW6ZjDHrkux+Wao9BsF01mDGUHdHbaRILx8T3A1/4jH7Kjato7m0O7gKhDnZsqgzGXrYmpw3WK
UbzHXhG38KHfMU0g3zGk4cjpoP9ea9Mp9q3ZTy9BhVzg+CcUVD7cgAa7tLH6xEK59stDSTnvuoMt
GRD5r+vppsw7U4nlTEFfdcffsPEGb7zia0CLFL4JuetbsqkKyrTXpnPkRF7WVqPAlFXdaGYB6mYm
yL02Hb8jeL5Ye9LjxE3SQzGcBlufG63zU+dJY/EjRWdb6gFdWepZeJfJCAgd0CgGaq2o7ahG1iLR
YT3rNXJ7wjsZF0ACRtisIRczotks3DH1ziwY8zvay9SeUZOo24vaHXSwx8//okxMLNre/cwAwSNF
5Rfq8UtQft4HiFyNnqYOua3q7u/psR08/zoKr4zyzyK43bJ51ZBfIolDlFzI+P3l3C40rt6FyfdN
vnr4apS/wXGusLhGEK+GpvM0tETnucne0x+8zqnX2Km1OOc4vD1487VmQ+D8HZoVA9Z47Hk/QpoG
vj9+cVy/ZSvRnYEN4+/YgdikSvrlE71RQC7ARQfksSubw7p9IcTjIgpc16QLAsL8h4YDlxDweR5h
9C0sthoP6yybnS/RwaXo2IcZnD0iDSFcYSmSeJpn5QSCIOr5SwwMdcLXTG5ZVWNkv30RbPsmWaO4
o/kvW8ecsOw3LDQFUwHkRZoBrauEm5k2B7cnC9kDu0Y8O9r3yMGycX3Nh//s5L/bZnwiGSa6iaX7
c4eErr4aU1SiufmCpyB5smZ5W6QZhVtJV4yaZ1iR5iafiMKvIQM6Q0LaLHOEqVMClN63es4wgyIU
rw78/Q6ycIxIYcSkmMu0a4GE5sGk1umu8nOPPtZPKAsQqDJK6zRvFJYX2y8L3fzhkrWIdwiYDSGw
OlAJS+N7/IRWvht/AMlYJ3LTH7ntTkysdcJLgNIeekTPfH8agmhh3uJavfAuzetseGn5hq6Ywk4m
56jog4O6uI9zdT7HFg8C3QFZG7AVReZjlOMnlG70qAdfeBH74ibZJx0VFiO/JQ77ACZSOfCV3FMJ
JG8MwEQE4bp6y2Eaw1e69GW9QEFNYS9X3ld+9c4h37+RmnnxfOiF4ok/ab5Fjf2pA0LZBhekcOnM
88F+Kjg2fqb3q5Vz4HZ03M2QvtVt+udc4zg/Kzv4+rpQY5ObYO412OCL25TtoJXgSo/kZ4n6qNUU
suz13B+/uEXOGjVL5QQZh7YC1e0XyDeaC9BkigdG8qdlJxgcTo3Lz/iicjk51ekvTOaauEeDIba1
BJe0ccZ8Rz8mb6lOOlZ1P5fYUFN+a+XgMuffTzSUsPk+hf7ZHTBZOyUNAIY3s/b2RXt6/BDzlioU
7m7zKa4N2kO4Ld9fSZuabakr+FzLqSHM7TD7CJfGlv/Qt42Fey1HtiEkbPihfhcvuVh7wqvZD9cS
qQyPzdwzO7Mkc4MQu1vXkViaXF9mojW/dt+xPZUaNt5xUbVoupKOnbbDp5KRtKYemW2rH6fczt48
PdIYYIQtjuzdGua4qxnbDq3kbuECyAI5QQ+z02R7cFk/bce3OyLvLsy9vDUW5fJ2OlYa0SxJF8xL
l6WwHH88Qc1eX9CiUCIa0g9G+eXZP1i1t8MZADSluvWI1I6WDzIF6TM98Rm2OLJ5Cvbt6VWhtFEr
YQi6QUZNPQUR/Sxahumqgc1aWTikuI+X8haJZN1brLNBXyhcATgKAfQxA/JdiRRv1PmnRMpt34Vb
u77nKbfnksr0jBwJiKlUupaNIHzlzYMaJoClx3o6TOWjtdnFXdrezJSUEhHC6nRyV1YLitgo9ozG
7XQ06GVUn5YvYRSx3f0PyfN+J71YARDwMYrcEAOFjf8owHcOkVK2AlzMU66dGEJ2P2jAaTVVKabh
Tnobc1B29HYjgrx0P9rgUvISjGqRwXKB8R2C/OeV12LVzmCBZcOv7GN5e8RpPHm4aiy067KY5UtE
ggbnDjZ0fWHgRswzx3Fd3VyKxFsppjCaJCs/QjzJ5QdR/5Nq/Lz9q1Bg2haGawvyU+Isd9giEcx5
fHULh10AtKe28FiiHMmAcSPmmIYmY2BE9L5h5Ll5dHXyV394wE2IrZAavL4KCQXuUhNdce5BkxEa
PSYUEN3Je5XMs2h5bOjZgfHSq5stxlU+Wuqe0cZRvwpgbmWJHc9MiODdU2w/NhQTiJT+RLuIiVfI
4ea+m+LWv+4AkT8lu1pnHwQTVS5OMgpWWRm7AZbjAEVxuo28GnoQA7muCK1A2N1HwbRKR86qN5fO
T/+MkTnee5K7p+DYKmULz6yPY8uGSaJB3dRWOsQjBxrJ23D46faw9pejrjFtFJKkKgCNbwY5WNpG
yFa2gK+NxWxdtX+iAcViNvUVQucQn+qG4DtDRitomUXbhzTQBubK2XaPHl9AA/EqJmZdzvSLX9We
3tOgbqV58K4mfx+WIuHG/MdV0yb9qbiasHxuVm5K1+zeqDpF9yqtIixMcZQe/cC7fmcVy69/+KDC
3UQN5X8ibRhwugu0z+cDsac5Ns8RKb6N5KnQc9F7WoTkmOM+EZYteCFzw7zN2/RYmWr0fsOTWfcd
Oa6bHULPOrqZgUpJ/eI8YxFA7YGR4ynUU+4zgb8RLIGXX9ked0iIxiEP8FyXGhoWD2PotBeqqeKk
oBXMpQefwjq9vG7QXbIlDIoWsUY7SrVHJnfWNlC9qmQtXF/v6DMvgr6Q2hO8WvE8cJCPj1/28+qk
sthDFr0VL1yWXhQf/orvm6/d/xbfRrvnpdzGGF7E2rDikCyUwnLeGfrDjPvL7E6Iv2MHV35oTNuv
THamKyIKMBRkagtJ2x/Ao+p1pGHR+OwgS0BaYIs5eSWkE62iv6Q3jrOOAD94YT8I7mUYpzonyHfS
fWKSk/2IbTZIkuVo1rPt08cR247kcz4fyIcml8YMQKJqrRpHb96HFSF/fZoPpAXMB8wbgVVz4bX2
dKObSdwN6PR/4QZ20RSmEV/lvPJyKLwXlpkuXSevhwbtLLTrnZCQ+7TUSW7SvqLr6beBz1scio9w
1rdotf/QvfmGzdSwj3gINILLMZZrV8x51XJN36RQ/4OZ5DRolOUV5cN2l/w4B2vJclUSNuQRbjOA
bqA9+nB6A13471t8+IxpYVUCV3YsZ/FRau2QiFwReuukTGgRS3uhUcR0zENwySGxMejQTlnyAqGQ
Ik7TdU4pzQ2c6Qc+9CT8ZgHEmvBAE2+RjzzI+w62M1QPtYpnshaHFCxCSk7zusBivyWj4weZKiMH
a0bvPALl7KL33KfeJwMmfM1sUiC1GuXOkVimFGnkbedtr2UctMc+vTGI6m9LqbM7fX8Swt2VX4dm
mnBZ97TFuyH4Pda+JrA0I+G2MUmWTc1BjiV+YWg//uNAALJIHi5b+OegideLiNXl9irgtL0IvbZK
a4cj7vXJ/aKoQfF5fqWC6Z9tV66raKszxQk+Y1vQ0dgYrHExu+/6ft071jMOAJSfx4NUalE3fD/Z
4pRM8+g4o5agWQ8+ZXQQZ2Y9gUPR+PeaU3rZeTw/AfuvWDD0osM94+Gc6BAwLBqt1ZfAGnKrE+Xp
LWZC6yZvEYCIMmUKwxcJfcWwKpVTCiv0DjgTRsEzYVysbKAmfmcb19UzDZtVuFIWF/UGNUJPRwsU
0/jhV6rB90P5AQwOIr1UXShmuV4JSJ1LUZxL6vmpI+YTnkpqT5MW8H3UD8JTnNGjj7OM6qbx7Q6L
DCGg5rgVW+DAEEUV197HCB2Fk3sjgavIqGYOD5/nveAj0WOMQhuKwfsjArHTfSULKTJDNdSG6GTY
xgntXMv5z+ntyI7EYEFnEltaf+OByGSZxyPHlfpA5iZMFl7474WPAyHQimScGMUI9ZFTBqsNm+4n
IeKmotqaQxg37bV7g5s0g3rWFzSrKD6WMnhXYyppyG9dhiUznfAXU09O9dnbNDz+txfXQHJR+yW3
kllVG0tkKwlYKhL9IYf8Bn4vEXayqdp1am78/yNDbRG5O6mOVUuCCTHgD1ZvzeZkUtmdzQiqQLy+
X+zWGa9GQ5TNTg/qjxNZI5+JVZpElKTPlxF1QdlhCodOSpqCZkR8ksrJUS4EUOK2pFbz+3S2u6Dv
8PkBIhWvX6ujUg+qhWVFO8GKAWbDoATmtDSyLfsfF5Yyh95hecvcWS23nK8NJO4Ot2Lt/tIkQzI0
7uMGhxj3QLouVvay119yyp7YTrZ2qfxID+0qclbzqYxXg6ggY9OAGd3YDSZW8e5TUx1n0Qy8Tw3J
yCbt+E8h5GxB6cAvRjXaJ6yW9yexq5LA2s4SHVu/j3sy+1/r6KennjcszWMgJ9xsCz2kEgHXTuur
OhlS6zrEXtwDdAgUeTfrzx3XdgM+CoaKHKPypLLI6/MsbIP85RXYr3oIjXl9px2STeHFEjgewCyE
T/jeQLR9r5WrKUqvjCuLAIb2dtcnjc/sf1Qjce2SQsIFQhBU3qdL3rsTxcDylifdzMMcX417rJ6x
+2anF9eTj5ik/pVdlWnfZiErVKep0ZZsyPXPw9cR5XL+XzYXPG142nGrEbF35Eqhx6rEhDswXuFG
OC5GPV8x6vHSa3sDpuereb2cEYNYFo/ccDwHACVIP5Krpg/OWzwGfIu6ZrqMbWYd51MxsBRcUGfz
B/IjWJRh66fTwGmxkWmJdVCOlmEcYPIzS5Qq5k0LUYa4qHdJp+KcEVYE43tjyxcKWUE1uUqsHN1C
yty30QahkYEhIA+sbiIAUzPjt2eBESTLdgHMaZH8Nki5s9HyHR3TkLnL6GbAjjTEWxLizxP7WIkc
t3jkRsEcSIYycHNYl9mk0l2qheLuL32jXh5Sia1/BDiCs6nXv2x9DynI632/NEehDw5JqLFmUlZY
bIeR3I+Wpx+1FkLu2AwUtiTVHYl5ZM4EmYf70Vqpy/z1ZNus2gMvdxmuTlqDHXJcwVVbi7G9Txga
gAzi/Br93n+x1BWZFW5bnPaeUrOKcumERpDRn3leYp1qEl+7KKsNR3c19ir82AEro3xmNcbwOqDh
LAGmpfMTxxWpsrhsuulutOQS+CjXuDJ2WOnnaHO09XS3Ypunq9J+lokpQ+h0N5yBv0AdrlI1VXEC
Vv6Bz92pdqtfMpvHOpxNsOXgHoDNxae5C6AGYCjIHsX/OzpNfWS1vbdgWgisM8KFDe5JZD7QhzKq
FOgLbkUsgKCs7w1E/zn8H1f8eKyEQe3WzylW5Q4twHaH9hhDUuw+zDSPCyTUGommh1MApFE8l10j
KiADLv8lxJptg0QiXhM0sprn1h0kVnkJcndwc3q2tWO52nbVBiYT3HlsRli1czt1WwHpuNTvkkNe
Q3koKTusqO7yTLve/fdy5lwy4XZ++kMcJK2LoMTp8U2GF0PYML4gVfuk7z9ZFTyexpffu6qcF5gh
dt+f6irwcZ0/4sJmeOZiETaIbdrLhfQoPgOvNlt86vj2Pk5kgqVF3QGaVcz5fbasXxFPO5Z/okw1
iC3BoVNEyWNYiAmasnH0AcaEU7MlNiwn0Tg3Xsx8mkfuEzApxFyxtxDnDyZ0kRWnhouyyjKOchCN
4VKH/sUkdipgdfqZzOVRJyRQmUNFuKjbvEmWlix/Gt79E2i2OUTJBfvxrXt9k+mnwLBizX6v6DcX
n2IVlk5lxLLiJxCTaPxXv31WGsOCg8qp+dtDp/KmwCo0ZmEBisZNPs2AtEVo23rgw5G1OaCb5W++
hgSZCfgltCVywSP4PHYwQxwDISackRTMX4W+t1IxWLYtvInZaRA/SKN2SO3ojkb/FalkJ6qQ/udN
gyd3uJIizBioeEAfB7U59MA1WsiFhN5LaxDQ6KFSwPV2ASk1Vb/cZx+J/sMxNkE7I/a/o1ViTOOn
MVts6lpSs+iKEY2YEJS3DsIQFwlqNGRrKzDgnDFatml/n86qhVUmziLPGgsK+islwdXry6JsuUei
NcOo1jQ7Qke/i17YncjcXe66fzTDv1Wlo0A8v63yHzxDbyobjqVrFLPLnKBVhg6jtymGM3YdUJZj
ukV5gR6RTworPgF8DMQCnJBJC0Hx7a0nivXt7j2FuFhh1j1gzOAmdABJe/O1THAcknZ4XUzN27XG
cFA2ZcZNkjqIRetoQmPzfx4V3C2GvRwwMeiuL56cRqI6ptepeRVjruUQ/uQyUEHGMyB4gfHIh3Du
jyudR5G2RjthNIV6+/RTjphMjX0ZB9YDj1V7Oesv2A0omWuOllnfVJegQ798c9b107r4zlZg4lb8
uyBo7OudMvbrCwzhAdhaLZjLo7EB5hLhvayoZZdvsZTE+cnKmCR07lfoiajO5nk5ZjE5OygZHQHO
CWvXUkPeKy38UG9QbcQptKiSI+M0yHQpfOX9mN+HvhweTr8XrTo227BqcZoN6rYEmRsBpbGgX3th
8je9IErnXw7txxoilMNvOhknliI0NqBHhPHTGlEVaXt/N1mXbJE1Bz9dz98kRFIabd8D0DiGYBvl
wvy6hR1O+unsw09pubUeD3lZqPSDWCLOQ2KINWR+RFvwYCyJUqRasrzq01/F0+QH0Lk8om/IDJnX
3q+9zFZO48FrGxAYYD9iJ0fx+2JOT/85pur5qLmUOvZbh3fdIw2Fcgl+2E2cDa2qIRmF5fTGKqnX
bxOcr5YzTcn+UtGYA/+xcUkFgWguEWWQLHtKUs/rR5R/myG+CnfTliGA5z+Z1VsiFwjofKIVNiA6
Gnn6/sWcq/XkIy/npdhlUtgFQzX2KcG4WRY4T/jFkG4vGZMIh1x2MNONK6Y/GMOIebeKaQDLXanE
1W9dWgwYUWYsF1T1XHpflHb8DAxx1dF1ERW2Dc6GC+8zE4TXcF4FEnp+SH9TmY8/pgfNSs/fE2EO
Gqtj/WeWiCMVJ9YSgy+sMGv1k+LP7yjDzegJwYK9Ckxad0+K1oOGyuZ+gCBQ+GNcSePXtTcEjqPS
S6Dj4qtqjgZbLDb+Mik4qBPJxcncnl2VXj1dNkIt/2zhPAqDUE49KSpOPULiDeLlga5lAj0c5hH4
pBBCx6JxXD5lE+rT8F+1+ALVvtANsfZzWrP3KGjBWg3w3Nd/ljfTOHlBhiZLXvO/o32EGIf67FqK
AgBofS+pbg/XZmiapdOHjt1ITNfkV5yLFpa9VMvGUgKQ2Z5IcfFqQ+h9wGmryKnh5LogBydfOcdE
9RDSV8xl0L8xsMRbnmbuEdyxiCI+Ans5CqLoczG5yOhbIbRs0fn8GyBh54IDYlj1IVeOvDwK3A3a
PzorxTwSJGH3JejecEBG2kuPzOIHg5cYhk8JznsGjbRHrn/VzntS/LMt5ed9VotB49lpbpmU01Ud
FwWVQJ6tIXKXRLEdfM1W7LiZFZhMwTE5BEbLXoccer3Z9RRgQYVpmhKQJB0DTGRSrAy3fIPHSwXi
NGIhuCGV7zy2pORnTOeBjo8jh2A+cJqehZsa7wIMHwC7yZC0BgRtXAqm18DsRnK1IH/TM9dd+ubR
Z2xh3Ufq+D2zlVaV8SJj0f/fl8JKcirP/+i2WHCpbQkF5Alzhhxl0Apchl4Jj+Mm45HxMV+BDCWa
qS8wvoJDzUnWRsFS0mMwHAc2coBOpp0wYASr1Vk5cIMoTbGmm9jeVJtuf1iNnzRlNE0gePf1gdFh
fvkBIfS8Vj7IkybxPt33/UpqEuEMSIoid5xPQeEPzYPlo/zx5RlCpwnYaaGnKeBJ5Hx3f6AO7JHJ
CojHJQoJAxXtjXkY3jY89TfXWcQ1BqKsvf5LJnoTd5+Tjgvga5iahMa2oUvRSg0q0lG7vJ0/KyLb
Xqc3gSYsVDPudY6yAIHknhodYmDa8+g1SzjpBOWziPnL3yx7xNyAkSK8rLwqvRUzAO8PcZPAjtYx
+sX5HPdplWxX4fePo7SJeDEheAjIeSlxnPYUwD+RJrM/gTMu0gtGwGZHLHAePiew/CapgSp+F8Dc
iL+jP9+lsHQ5dJcUkzR0FtaFIQru5sqknBbtUo8s00gvYtlYUI+ki21wgjLZPBFN2SvjdQc7dwSl
VDZsgyjcUcIzDfbIyZUZ7Xw4MU5kjs5JT8t14bdrPdxIvYKSUtlf5Z6HrdLsSV95F5SEyUS0HAzG
EXLwNf8BFg8X5iztkhuj1JAjgR/CsSO5XQ/MCHDkdT5f5Xjz6AuOgcjxCU+8KhoFx9s2n6jCwbak
GXgW4ttzXuyX4cnZGXKeGelfwMwLdgKXrhE+NZ8i7iVK+kREBDenN5sE+ONbCU1Yvri322Lt5WDx
qbLcdEt2DrPYYgmW4dRTas2adme+nSQedIwS5lGZ3ZOYRP/eEdDLNldSSYi7A+1L59vpI6Kh0A6o
0SvFYocsXLGlpb3UL48ipF8sfrTOz6YKqxsFztNppDg27TqIzn7t+AeL9JJSNa/VxPvdO+dh0KTU
KlHSREHf13ZDckTv44E2w5Tsr3xONTvEybUW9uAlzJbgq2pKNT3ISAtphJjSHHm/Nlhj2JTHecgM
8Pyry/9u94TPeOH4tKFvatEqsUIiE6BQti4DKoZyye9MQP+axIJaUFcdwt+KjUB04zoFSlPKFQkh
QIqlCzZlOWsqIxfZyK4iVdHVwvECR+6kt+kKU4ZhPnGTCDgoRNCvVXyTwcluauQkEjpdZobm8PZl
DOyZ1fVPPy6uSR00jAxKXpM59j9puz588Vd05QRMOdqeM4FAwhQg5Z3aTVk5MPPx9HhcNMhOHsNL
F+7BCm2vSzllH37HBdbTATcRPH2MXbfpTsLSIhC5762pwCAbpiZD5GEgbIS9aCdigRS3sU9+CNh0
qk1+Ry2T8dgW8XDKx1Y8UU0lZ1apYPfZny+asiXLGM9b2aAqQ26SjQfeK7ORzQLUPAiEOvDhzSlB
g1qACSkY52BusgGGOBiK045sOATy+S+xUcHqe9uMpqo1I4sVeVyoa5KO2h22ZxpsU9TcQeNs0qx3
+0fxsXHpa3ek3OP7PnZakBsxw4x9Bp9mBd841OxoKSq/GD1Jp4t0Wu1qEvDNT+6757la/ORaXCCM
GX+K6TcZwDblDXmGyLjXqD4BcF4gq+YFJNbc+TmYBXWvw8Scn2+9/uWqi471MFSPSkBwH/Okgiu6
9OcPoQBTBA7MIXmsux7XiJ9keIcSisyQllT4Td2Zcyt8BlDsxeG00Wa/39MjHfTvRzTo0JXtAdTG
d2Ixqb416OizPyoxTchkwRJvmS1zXvqwRA0tn4LLZbYWWynFELqqPPhL+nECskY/fMSc50DsnzU9
eFfW0gckBF8kh5feNCcQ5BS/rq2X+cbBeMz8v6Yzz+p0JtzujT18vknroMCrY0p1EuJLccSpcSEa
sOdudQfxpowX/UCUs09xEH1Wi97pKWFci/wM1xcKW8PvfjjCR17U7A5ochJyotBZmZniTzTOx9wl
vqRF8Px0QREr+6hfFvgA5BrvP+09x4PZVVVjRcp9PSU6lBwjbqcpzOvwCn/3pWa8IvWB7vnpqiR9
tpJoeL8hl3WtFc+hHzSSQbC2y9V9KQPgGAxY2TrvGEc4HOQgqyC4XuNomNWs1TGYVUHd3+tZKvT6
DDisGjHLWe9hRsfc6eKLmMIWANdLD4LSJfdjbhrxZ0lHZEiqv9aA/Q0JOJLwLXvKVP+YOlQEs8NO
fY1vZ2WOC+OWaJM1xDKPXkr10IaUfe+GfyWUM5h6+osGtZxjhSL3l6GkUflvzGq6o9JZzIZ4zb/w
qsdjq2EYSWCCYgafkFKkXRkpM7TU9/eNfGNAndQi7ZsrXClhkUIyDwP05wnlo2ADWbjp28csV3fL
uPgudKdxRpW6keA5V2fXZbK15jIcHTXCpOaPbOnOu5QefYFbNmZ6nNwJEQ3j7zxK4oaRL3c+oG2l
yz6VEiqSjX+MH3KTEznkZ5GW66SlEeorB9bfdwJUjvguDtIBNxOv9KppPD2Nz8ZRhP81OwTjD1PQ
Z3hXa4QhHcPlWSwDun39FSgHjZChY6SaGzFmfRDO2EfVHKvSwqZRjCvgVIqOuvEnhfalma0PdoRS
OhdYih0k2ROMpH1CLQaFtpbNKJn4vid5J4v+CK8O9XVXSGtjmbF5jw68EFPaX34A5GUYZZp7ir4G
iO09p0q7CSfJlJIeBgGlzaakj/EAwWMhdFnOoL2itNA3tQgDPOIOYY3K8p0pXHCjE0UJrJSMzIQv
ebBrwqwEz7KyKtIvhlxaMD98GfDbjOjjDDUm8oJMmhhv6ITNSgd5uzn8V+lmgSkl9EoJIVhMZUmv
RDqgDJNuXEdQlVk19jH5wdG6wST6WvFzaKX9u73zQdnvf8G+FKDqAh4ZJ4jXjfPPKWHmSyagTiSs
wLHYNwk4GA0Rsa1U62vQFrgKpUGG3xWSPJi987kweuvvp3bS506sbbeML3iR18/vvqwCqfD6kWvU
hA4bui3GZ+XhVJD3ntREbeXyEdtkefNpYoO1V/WZmegSr2bw2fwUKHJiKyVYdevqsBK/hJjTHzcM
t13iFOxVwNzkDVMHjfJC2WS7WGJPR0oJ50n5TEV8gjCg2BuKCKrrBVQB9QGJZC2fPzsUrHS6KW8o
oYkKOg7cOBTqydQi7tBLgKFcqOInojJzFH6KvYK6Qp7TnKrniBv+9a0l6whB+hEmoPHRPpyfpEg7
IKg/imVWeL0qp6iT8PYksIqXuDj996G1qUrOHSZyxE0NANIO40gc48DsH6/5fEdhJFvC/PISKDZ9
th7zTvMU1mUyrR1MON6RXZYWP82jyZqCmlA/Y4Qe1uFEYsEsFRZu3KVy/ytIN9FUcE7hMLNDJmFo
YTPmmPX1WHRJ7yLk2CAqP+YpZ18x9DmeybPFgjyYP+2p8PwflkcUaXQIfNSGsfD1myUEml/5Tjc9
IEHQXaplZc59lHwcHwx2QkJguN9i4NnT8WKBbBRLT3yJAgrVQ/0cSk1G3VnvHTPcaDb3Riyyfc5j
SWunpInHO5bKXxdE8qTUyUTJoca+UvIxeZDjksjm2gSlv3ytDV+bjsyY9xPnkW/rbO19qeOdpIGE
Xf/Y+0bzGYFmQ6ryDtEkSiQVRk05EuE5qieYwx4dwvPAWhNd2YQCYL4msG+nmRu4SGl4Bf5qrIRt
oEHEMbyzn3UqEVBZaUPCk7SEQw/UQ3qHtfN9KluOvB72JwWk0rqL1WY74DNgr5NAiia5eGpNAjcu
gImJ7N4DXfv1jAvLd5EiOaC8qWmln2+lOmsXTu8uRkXeP+FVGfTVEvzPJaFJsYTv8anSRT3RU1S+
fjoC1LgYRdDln2ubC6RdgemvtveQ3sU6s7ffomq37i8ILiEBL+280AEbwcEeKrcjoxs87bvBKbBV
ARzpRwD54XSyAuLQJfuVWghLLymzWkXBy8VPCrGPAkdhuJi37HOtTkoS+EZ/Qb1QyUdytHOsuvns
6eBVuIpA8ADkwVbZEZSaOPGLQXnaBzA552H6O3zN2j+YV41gBWZ66W796MJZhYzKr9JYGa5E0c2Q
SbE1Elk9kF3XRWVCNUKmKSorLCYiJzq2GIJoKFyAWhuUjmGhb0Jmx+4sMV5eOYkAJuHVCWNtTEmR
84xZd9X6MRfqO5uy99iLY/y2JQv4xstUZP1NfX5B0Bu3fOJ02eTyiMfpXA4V6SuclUB8l9srLpvD
PKWcX9PgYjJ9Xfh+NokGvz/WM5xL255heey53z7evUNrfDooy/XJA2AyF1EksAgI5ZHvzN2sjaG1
Mx/33FfiAkvOo7KgVNza4B1/qzh/HSfu/9mOkihNWReJtfGSF0G3tWo0bIHGHfyWW6mCbBDzEdsC
eAUSSCdUoYQD1jKe309d7BRP/UMn1rEKmILr/lUVCdnNB6Chl4oyt94ZV1QtLG/bV4+HU30b0nsT
bpZP1i+Zhk7ggNLkcan68FuiIQSpRYdVQI5DyvhyhExmQNFx3Jedrx6bBGamIcLXMd3wbnuE0qsn
kWLVkQrlY6J3wM2hOKOCbtCU6AGK9hPlsrgZbJFIMW44GGBjyl1KqblRD9XfEErqho/b7XDfzsAP
ATqvdJmU0Kjq0enLyvGJoyQt48uCaXe9BlFIzlB8ZugsFEJI+YPw9+paAeHG+UtN5/60GdF33Sdd
O8V28nPKfNRQAg/VoZp5HXG3i4k/vB4RCxA7Jr3VyJrroHcyjsAkSYMEudeI5IqN6QciTac2MDJc
/IfEr+hdaYHpsaHqCCUQzox+WF0hTyhpQaDF0Yaz0CYa/GxLnyG0U9ZCmT1wZnx2iD+3hzuZpZFH
C7E8xPnJjM1cWErBczjtIj0gdLsSg3QxbSXMGxVEQO0Oj5xLESBc5Lq2yK7OGZQS2HHjVxEM7MTQ
3lwi0+PI08/wqLNVE/ftaSrJN2WzSQpM+ZQQtqxSJIXLAVolC6ue7yToy0VV5rnHIAsiF525H2eg
EQWkdL/yTxl75V4dK2YdBaRdamKbmVxpf4dq2SXmSWssIg6BguiClVrllhZcVMy/syv9ZvLe5inu
Al3naWlK67be/CfRpx+HV42QlxbEo+mXE3nY3Q7ZSA4axZ9+7weFALNXA0bJzPTsnFRAJhOkJJUq
dgiNTNAZsvL2yvzVnTH/pmsO5dC8GSeS3nEI7c1wiffJsUh92GrwbV/HGummxuRqyqbIsSF2Gnrn
Jm3+qGA/4MHGg6pp14iHMZGGDiqVTxDAf6OYBjOQYpdGMb56of/imigRNAt+W5uSyDMJqkJ4LloY
K7uRhqjrAdY1zUZvyIShZB2y5wW2ufwZXOSXq+ZbXFjh1roAsDSs49aexMyLMXdD6qH2XL23GijF
2zFlpSuklDbHj0t6nQiDnwNHccFf4vy/wvNVDO1t2OyCqYZFVQikVrV4cxcQcC99gmupyMXLRPmE
nhFaP/wBqliE01KeKRFW2p4V/qEce0GQxphWV/JaMR2xzlPuRgv4GNnrSbBXghQ0BEN/D+TRxINW
JDwTFk+1v8oQEGk8KCkGdUnooUikAF/m/c/CttJhAruvI5EvbLj7ldsiGvWj70LXhdUInsafbY5S
8VXrEvQkfjxk2+kYR2iV1smLBcnj1H2pFOqj7F/h4IVKBiupwNfsg9Jr1/9RUDKpPLI5c9H1NYVS
KlmSib0E4n4gAYCyXXUQAt/E+ZXeEm/3VhZUCIXVy267AwfBNolLkahqRDdqqSCJIB7cy1+Dsq6A
NRDZ5kE8m5hIgJlSSigo9b5yGFFstxR2QQeI2oDr7j3+Hvgq8+fsUFa9v1G/cMyye0oCB5UhbiV8
4z/1uBnEyjmyRtauA84/uP+jGkiAx/NPueNflQaWeTdC6vqMqOd7N8ugXpoHH04tcMA4KjnCeUed
WDHRw1EHc3GWwDYMwG3QDrzapkzZuXiJ+yP1Obu8vovfdM496qDdmHFu1KovnW9D4N9/faAPY6Xg
GZc64pJAu9ITRdbHqfgitU7K8052miY2j52Br2xGYC5A4tWLQroXVi+HxJfAKvro/nreFeczbVSl
aDu7ADB26rMIelug3gaZJ9k1vmgB/5gLmvG2COB/V2Qv1fsqACOgxNrwlfNUDQPiG7dQzMcHpAyA
qpV+xWULGmJNHFe7UhHazH2ZnS4xnKQRkizYXSMN2CQN4fp2WsEizIn8BaRjWkjkZ/TvnrWKkQNg
E81VyaE1jSU7v7vMrRTBPbbQ6QEtBTRT/L4B9BYlUVcBPnUQgqM9lM/XQO97dAoRManG/g8jTJYK
HLGSmhAW3B5tXsX9ySbnmLo7Mw+2qFBD1WD8itwijX4N7biga0E5xm+0WB+sm/n7SgCduYDcfRhd
huY1/t+1tBx7BQk2P45L+6WBPzmv0L7zoP9sOXsqQVA8vvvuf3nUk2ZPuybMPoF9G4djXv0XnJmm
dwLi7j8Ohlc10/e/BFrvbavT+CsJYg+DiklkgWlbY4U509fEh2LitAJuEZbDnRtsooJ50ZmhSg/2
V5m1kzivCZ9CN6LuhZvWD1jx/BuCzOHAxCUrn2WLylgx+RT/KK/jP1PmDqVXkVOlqRAo4iiNcXmX
vRPYeUS7QM61v/wEY2RFpRN9Zlk3gvGfIxR7lyvayMw7hJgVGoU22OaWFO+rbdaJALR4CP0LlBgy
Kp84YUDzudU2zKjOK8PqyW0f/7/C/SOLQwtEQ9ORI9rxk1I9YIgEnt5dLTdrYp2cbD1HSsW/3JgI
DSkkK3dLVYi9GVbw4vDlpH6Y+LUJ2iKIQDcMtO92HULrWg9kIMfSq9hHZsQqIYqGfLIVeZGxvQAC
E0T52qJ4BZDXEHXU1jmswfbZVmDOOr3otn7GD/rzFcgFC3MHZW1Ls2ALBWX9xP+HFSlRbuMkPmhc
rKmKvHII0WvPqIxlEauY6SnERuSUBiank9Gx9MZ7CrlymrIubpoT3BisUHXVghu8BDs0o9/bxMEm
iUomyeJfkUIGMdS9ZQiaq8NLIgGARANqKaRIqgmOyq34lSvhOesj8yBUcGVGsPwD0P3WzPwePtd0
bdLTEnD/zYxLMXhzQDlg3RjqJ7XhYKCpU5NJfZN3zBInjBlaL5ayNldBcB0szWEXNuKTlbbXK705
CRTuXcM1YtLL6xVWGxe0OIFiH0xILlq3QiTZKU1Svt6dkflAZA5tR3yU/zUg2XU4lmE/28pmY/bZ
87jXznZfjXM6CvzKUoLqb1Ub5mWArJO9ahfBhU6JWhfQWcPqdZQi9IUDSIVondvc6K2dkh7jeucM
vyjKue+ykI4yTvXCM9HnBkrYXCJ+q8jdJfW7sPQkTthUS0H/5ltBtB7jtWmY1KnIX0eIyuqhMzgY
IafoGprO2de4gV6gkvNGIuqo/4ONU9FRkaspOEsCMe+0Kz1COC430LNs+yzbMnBo5xRxGG3w6L4r
bTr5e9xXp1YtDFZ7XSvTAgpypQWwMyxF5o04Lq5aziUzHu+K6jb6aQEP2N8A8hCZQ9CQrQPOwDCD
+jOy6NK7HhgIftfbX/3jWRDHrFbYuEqSVgrTH9ZwfIpwvOK/UIsMfK0XGBAPV3/fA0rtHgesb6bO
/q2P1Aq4WzeG9G2PmOW8PhV+Ut70339vKUJ624zxRUbfVMKDmeZe6d9ogvnIrJGcg6n9/UNclAY7
I3Py/7gYg10/yEJB0WCLLaW3B34suchkH42B2gUeZE33uAPzARfaa5ruClUYDf8I1Ed6vMNt9Fa7
0KKBBknmwY0dgEY+gvlQxvkrJYensi8RXnpmz59ThG0I1NpI3kdsJB76TM8653yIn97lh6iAaTFD
2wAYMTCtW/CJJg6dmFHkZ86QAzAWKqLe6qlvU2CJQd642py1+m1HQzCj5+GzParMHmW4WNY4oMS+
A9spiF3SnUGSVjKex7TMmwmS36GGc01pWHVQoW6o0m5xj0hd+jY1uPGJU4dsdki0I42EE9GVtHbd
XN0VJeppfaeGznaM4hgXoa5lODxn+urgspfdo+Z+OquuxB9RqD3T1bwqs/nqoNXlxa/2RQZXx+PO
NUg024AmxA6ZCyDGuhJ85UjHOQmEVNH/q0/15Z6ZATpIuLcjiRqr+EnyGaIFWiBmBp1HpEboh+Se
Y94oWldt4JJBnERcn/u3Xdx0SM71GqhBeZe8zYH1SNkupKIGixNW7FgP7oZrS6bOAptby2Kf7Tgp
0+wJdqohNUpJVToSL/5jgxSXTvFxkTMYCzBXsQ81ISLEcrrfAWMwi9CX/AqotUxmK4XQFJGvhu9y
bWaNpgo63PQ//smmfeG+jvMTwM82aZQWv8606XlxD/vc+ULdoipAd0fefEtG2GLORCfkjZnsSntG
2/BauW1p5tulXSi1HMb68L4m1ODyIKMeM5hB27s6Zk+ZPEe9Twmevf13dxrEfkfCgDQWf5+IZT78
mvjwClDuKtjXs2cW9e/VerMkrLPomc1YoB5V7OJPqS/t3HkGNN176m2Dhv41X1EGhpWphITz3Uub
mUsi5ah+Srlmi2cT+cYz7JdKGyGR1Qnq5j9fsXS/PElBoBE9pd8+PkutDyLTOC8b7KD+JvScFjMt
39YguX5i+5qvinh5GXc2743Qwhk+xQVEGHaPy/NnQogTLxkUAYN4DGN/OMpVaih1uSlvCr3lUt/f
hqheST/yPyrc5d0MX0rU/YZcStQdipcxVSKkYiqzG0uqQBdUCagn3p2/Kjq26IcofdrSi9/34XAF
7GsV5Js2yPefS9ZxthwHgaHRYgtNVmd4V6PomJW1MPlprDoqK2he/RPk9EzkSGR1uCDzCLAOH5gu
B9G2kG4Peq4Kbx60gq/T3t4+wx7O0dpTxh/RaIjxulnQQVrAw+/NChYhivcw51UDKHWVrEX6cnj1
Qbj95+4tCIErmKqRr6cMPAS8eISCbgfaAMOecWj9icxFNA82TzDrmejyEZ1JEvNWvQnS5ybKPNqD
6rNvexvLRDT+cpH7KGUuHniwKEKSrZRbxBC6Os8M8BRzk+P/63dVeOphCegc6msjSXvMsHo9yadF
n+WtXNceAVGtJwSm4aNMBQwdM7Q+ZZGNB0J2MC6l11TBZF+BfUzEu+WnCWzANCEiBPMBwcghYETo
Af2FA8qFHO/pSn0RVXW31U1OAioijkRa8ym8gMm9d8v976knPZsIMBQsTpLDrfXDsDzFe/z/hWk7
X5/lbw9Gf1+pIpLByb7uacGyEgvwz+4uDoP1PAc4Pg6gAb00MK97OIryTLjC/4WJrQlY3crhQgf0
XoCj1pVWYUmmesLw1A/gsB0zU1hv2a0HmSOcd1Z30WamZ51HFzzETn0C4KCVrhYMNbbq8NdgWjJc
d7tIiipppfGOwtV1pf0ND18sYb1OyiZ5vfy40Vd8Psn8kb7OaDPNFEcCcBfnUVxx7JFSq+a+d23K
/EM4j+je7Eb2BZOhTwtKjHRNfuazKMwyHGKzxjgjITy0c/SazygxSWhhVu3FbxFf7IJnQbNRzrAr
DlL6OaiaZFji5Meu536s63zCSeuSHImzBGD8cYrjWeHn5ySFCs/1jSBBXOmNi0ubHpb8hN1WXZW0
zT+MAM4BHdXRlHBC04X50YGU+EWMHmVPXUtTSVCmIJS7OCMPbLUy0GO/rFPMHnd5fU55KnpP0535
PbhA7gNDjzgSM7FGOLQCn69FUw7FPcIbaskRqdY2g7cgf1UWuHW3XjGMsYnM0lfykP5tIrwzp8W5
DSpy8v/fYgdtERQ9GJsLnTHGknsV/kqXDHp9Dqwntb2bm7k9AQlWAa+d89BlNML2Jle+nRnUo4Et
pTNzQwAGeL4PXMnlu8Nv/Ra0n9VxIbE1wL0ZMXOqxHtTq0KAJvc2rGmyfecdtj9elSHrHPOLULJ/
axKbu1p4gT8ug/yb73FDvoCBpKr75XfsUlyxC6I0nSgQbMBjAc+1jlFB0VumlRYC9TvZJQo7EcIV
GXxqRBBc3L0GZHbbgvHbXtQ9UEKDcYwGvQqcgf76raN3v2BxZ/BFsHkuHzqdRt0L+Z4+iazxY+dN
eaRx0H/6nXnUM8SvOxkDdiw6VtGJ2trQaKXQwn3Jxzx2tv6gHGDqPDx9Yq/kb4xLJjtQw9iUKPhe
QA1jJLYIFkIIIZhCz94ltQqy5bxudFQfuUOoKJAuA9DJ+/d9L21TCePBtj2sxh82n3w94ycMLaJZ
4Bv3wClPPnZ03faJq+AiDRcNSjuR7l+1rZZVbASShWDbehUcD1K/E3M7Y5ARS4F+tVRcEpKvEKeu
8qY3sK2W0gPMncDXb0jUOcH2Nrx+o/4nCW/6p3BvawRkEc2Y8tCAm5xUnZHR+phSy5kntUkyNvRY
KmXcrMRnqM15JHnacXXDdv8Lyep0jlI6SuuIIOMEmZLLx6RpVoaHybBZUEgC8aDLSCyyodRHIMHh
LWW5UzjxXCLdfKvsRaa4vS6XOHweIkyZAShEKqit0skfjCa+yVtO4mbLWRRPWN/SdrGt6yCt0X6p
VRGmsAHPc2s4ghQJR5D9DO3vdqa4YBqNsksaF7SJfkS82kv5eE7Xv/v8k2DzyJVcGsej4fPRK/Xw
8ooui4UTnZ2SEc9SGQ2gRU6Cn4DiFLtsMDdgpjCuDHKPjbYoU10UGHVEATVixP2bVmtQfLU7upq8
Jxq+Bp50mxtEpkfDez6Z7e8ab2lHwxbBYgA/zJ2dIXZKYzm5NZlK7ZSAJGh/DqvNxaJffs9uuHgn
KWv3neMH9W1akPV7fvHWMic4UMCeEujctAslgYeE+FCVJMqKBR3TrIFs+3r1HtRlAJAG9wy72Zmj
BwWSxYhay1pkSzwU+nHQKi4ovcwpOWF3aQ/atDqNAC1Qo+4j7yU/NjFuWixQ8cEGlEkQGFd918KJ
aT/hsEduESKxf/wG4ol2R5WT69RTMwKC60wncfm7rL4DEhwrPxVKl7m0dVSjndD5BN3jhe0W1bNL
YL4NV1GhDailbmBEC8O3fAj4kAgQS1BD3OPEXeusNELoWPz9I06fJVv4V5gNjaDdAzUzqm+QHPhi
NnlG9qWe0DeKjxyrvIBmfjtih8hdnsewjVMw8mlCZ82S9euOo9pIUxKrrW8iokSItVCvGb9cFuGJ
eNN0AUx8qpXm/6P958IdBQlDWY9+mfwHElT9Vh45meHq2rwt7O43QMuAPb2iTfoa6+ALnNh4ymav
u3VOTucp+KNQmLpxnTlDWETDB0iD61mGxWbQnROtg+blMCIyCJzIhD8/ZG1Sxs1/Plr9rLE3fnCi
4WOn/hvsCYRuZeaBKQgWdWtE472AEKDqQJXxFpOqxuqMiT0V5bIIE4iAo507DjGp3mMl8MGInzoG
vn1kp2T4J41TQanBIuMoJS8jlVw7EKy1sn2pnYVFPkLRadGHAhw5KuWhgjPdUosysVpKwtXDtLq2
6C8YhbB7XVcldkmw4SGxIa3JnC6htrcjjcu6chYpx4mTkda/6ezQjkdKjMrJeleA9hIsFhbZjwPx
SW66hNeyS+LZCjm4iLDi86plfFBfH/8x1KnqIBaqF3+C92xzZqHsl0seb83yxO0XuCoHRt6LjYZS
+fTFF+YJqLWA61h3gStoanHQsJxuxRUjPKfPF5ZRvgkvBYza1oLTmuKyM7oxZPWNE4ZR2vWgvcF4
lQbeHJyZI8e9+4Zpk+2Rp2dNe33AnZQuf36Dy9aJvOr0DrXTJ+5oscalhc8NIfgCiqgc7liLiBo8
XCzRdiirlT5BZTGKRMFzEMbaz6kSnf/1+aG5CtLX4WEbhr4XnKkKI5iUIrwquo10b7zMnuaiaCVj
1YQgBxqbkH8DedJdrfwasxubOrTmB/WIteKqBArhqywrrRNHiWWpNcIT9t29s5vS2ida4wH4vGNQ
usTQ5dgsHjy510l9rx8rqjoqvmV5gRVc1wdpkWaPr1cnq/Qx1dIwly+wNCbIAJja1XPAzpWxRxo/
6457iWYdcw/jf68c6umNYX5qx+hVJSW34xsstiog2h6q0mjF7vKwbn26AKO5UwAuNIVjY9fbcv2T
WR5AFK/IbE8k9WGLphjGKA6GUC3ZEZpHm/sEPkVpFJUbNMjSGk55wGX4seCkHkpnzr4OzvWz65P0
d95jupRaVyb21wpuuQlxL51XfjAmv8Q5E3V5zsaaGXf3iqQr6WW/oDkIFfWuW4EfIybtWOmgKskc
+SKDSRTtpzIYsFZ8UHw+BkZrSdnKthj4vGSi0TYiVmLgBdXYJocOmlew5D1CkcoOgHIndxPJ9xh3
H2BzO01UUAUhQ8BTEmi/VfLgkRQCRwYgjO/F4sXK2FaXv+ECcWlu0bOMF8Kn4whLfyim4Pfg2SXV
oaOSoy6u4KM4JPsfhcSgA49H3Y2+KIZlxxkUh699ayLYVD/Lm6sTavaF9AJ6HxoPk9qNK/EKBCmb
OM2VEAKHzvCcb6nXXOzARs5zpxIN7aox/n2PWI39UjEEJzNN8jp7NNwN/PO1o+m4GwZozf6Hoho8
oJFs2yWV4efNhg9UV7y/x/6nkTZESshbs3IKHx4iAGwBES3QjqQx5LbPdt2EwlDg6vXf964VWhi0
2biLKEElg13Ac8s7bJuIVNOKVCwYBfFTBhIWgoztzG80vZQYvOJ16w34xX1vaGGUVwgmlRTP5RIG
7F+QdiZApFLgVJFiUrp6/vGgQubinjjKmHMkpv+u/UrVmGtu6VN5lefzEslMdQfoI4h0zkjrusL1
2YW1HsJn2aM4rFRBMGVCaGcAXsSktr8saqxX8wGEyrgzPZiVmk+lSdLD5kgF6bvlT3W0YR3a8Nyt
X0BgArSAJNr7x476ZEi2ey5dIZJPuMHGu/GbIdtlhjTV3fbxIM71DkLaO8VnmfMm45gusRRQ5IFV
IWwKxLaEZEiLa+D15b1IhX1IRdOWRK78Nkcb0eoO8QK84FlwMbxQvCaLi3NmStzWZPqxoJ/eE8d2
ZYWXcTu+OdfPkbeNsPlV0vHcfbnAKb00kHjTIN8kD7CC5ELDdjOLiYoL/6LayIGBodOf/FbdVLf8
mi21re3EZv/INOPzPHNbfOsFQWSUUGOH/u+HCDKwW+jWow2qhr6DwqpY6ys96an5NrZLO54ZE32N
fN2ooUfisAk7qUo3Esxjl7OU9j/Ep/H8WSH/7u2hTiADHIslElY6Hxa/uMZPSmQaiqQk52/o55Om
Et5KtDDxQITF5c9AUK4cHhX8+ohPVYGPo7bKFTuMD4Qkep95ZFIoNwk8Nx8IPAsBfFfjPv2foBpW
NTIHxQx6cs5Fz/0KxRgSquhlc0C83XQmmMC7aBJHXRbt9zXl+fyh+dsNmEYx0mG+a7gDVHxw0qcI
XbLL+fE00wUfgEQ2H9KZz9uinCn5E5PB0SzZWLExTcQtrAt4GdX8qhJdDKuRhbts1fZB1SYPa5dU
nv/rAZUJi3JB/dqVSaDhZ4blc9BrTxW22/Xr2aQpV1/E1dX7Q4PpkW5JlBhNXxLohtetCfDT5ZuU
5qXjYwyfQtrHDzJsFlCMXSFAIprt43tJNGwindCIbMINPouvr2h3/nFKvkBmiawO2QuGkllmbSTt
eIRMkZSpI8JbrjIAQ55z59sVIr2dtBLEjh6/wi/6aWYcRa2zcbNc7RN057UlZYc2sGoxA6eAJZ1J
+ixeRjHCLlF3b1bRDKg6plf0+dwSt5/G4Z7uVP5pz2zdpcWv0k90YKxIwyDJXeRjgpBT2K1HVxnL
Sl4PFur4LySKvRUNYA+R5tl1s4EN11EhmHbsbYmKPgAkycvGopkweIs3yBhHH4EEL0Huk/Dlv1PH
dao8lAuJm46ddf/B4tHHwVeVNifJbPG6sVb2iBbiBBxbKdzAg/J564J9smW3isq90dRjPDOt4qju
anI8Zv/tMC9Ws+Tv+1ecg5H3jKLGhZGZhv2fCaTgHGrhwUhNOtI3tVOYCv0OQsy0RObMyx3gVIz2
aWWjQslaMooQfx1Dctx+i3J6a6v6ieE/KCeZKtfLqQ+3GkcWGSZhYoewoH7mOdS2tbf5U7bFBO86
lEk2jmIZpiv7VcVsCfBYmLbl/0OZDSZjeauXeqQD02o/OB3qnAvdtClwKQbOKGBRE1ROeIzt1LxW
anByWaSOgi63L6xAiAfQmokZu2BUM+tG30v46EjnOYKm0Dylvuj1XcF1O2snwUQk39OxPcHPL61U
RSWn5yzlwuDRdmZ5NrhyBsDG47eq0sk2RxtHquRq3YMFNqjrEH3bm9CgtS2VOSsEuEf9eYmmLYUD
chemh4dTIJQ2hg4jiXXFxI7UCtcOCpmilJTKzbSCjzf+WgxB20YAxr66WEUXE8YEgqKDJN//US5b
pplwyz2k4lJR+sM6TavABHe+HWPUo1rn9WKHCCVfmxVyVZ3g41J2Uf+OGu5FwK6rpZ1Jx0Q62LRY
wV237KCYaUGMB9JkWoubzniVBHOfRJkGJrO62rRrAPhn+JBQn9DmiO/zH+d24HyVmjL76TT7Em+y
P3juDku7rxLaOc/9RTkSe9opw0XNFmDShLfZhKhbrcd2mZyJ0Z4enrgc/xGGME5t4r5tUYyI2KqG
8iO4Z/BsuybrGolJDVJBYrwNeFjVPp4OwW4j6OzrO1ikabJjcwGE4o29Wtf2xWGEhtC/y2RTDNdV
472Gg7xbEAxHavUdc87lEoRL7egVCRGvOu+u2pytM1BqH9iijJNzV1ARC3AUwMnsS8sdGhozBXRy
8lB3RUG2GmxzT6LTxHgDggGvhi31Ox8JYfD2fPu7Dv3I4jWibzfrBB1kUKJPkN0VJ/BZooAE6m2h
NSu0KOb4tyFWSjEEOfAg5E67Ow6ldjwP1zt07LtYy6P3DaOeGCYmJ8wg4FpryjpIpBk4o0KJampE
SDrCKDvNReAPSm9XfywwbJvLdO62srCdJBViPN8OJYIWxTMTMOkIiClCOR1vuOehtOSsUqQtEsQ2
fGZa/8SYpWm+ysG8R401LGIFfxsVADu4FFQpBsfviJNgg1RM0PK1RFCpuE6yEVzps2Cd52/NEKqu
wmXdIwOIZ5HCnE7FlPN4E7oNIk1gWDFn21J7QQ0YIXeYrecAWUpjkLLkkmzrakVExDNTVTcUGrcE
PlN/o6+EJoByVyirPBguOuNQIYtwrkOnp5SJiyafnfnuwkCCefzDqbls1bUcavwFkMgxsTEgeMuz
q3LV4wF8+g5YIhzCkfUMeXoNuIoEGo9erJg/3mvDfi6Uw+iotdTjMNj8KTQXOLvPpeVLlHrUHgpf
UGRgXZ5YNk7Y2aieN+jrEVm4KH0kOieUBxFwioKR6vISleXU6LntY6emIg0dFxXYNbCa028o0RfO
LbZeu5kcV4XK3Zgh9YigrGMtiye3AzDCs4zseg0VmX9TS/j6rgjGGrjM78OL4Mcd18eBn/LT/REF
if643lQk/cJpNKitey1uwO2QsvvmBtqKyaCTYd9jS4gzNV6eci+HshUXpgmx3vFbHTGKygZNwfWr
vX64bYGqMMz33sVKWBYCH9uasMyAopxWQPFBhniDpT6yaSCYLh0SZvpME7fWrsyYgFs7XBfBeQiv
sxI9IFjShWrhJGKXzXMzekdx1dlpiLmhbjhBUq/2vm01qJaxrcH1ncaq16eSMEVNhEFO025yOUZn
SWrKhe5dVM15qY+nDWOGJJrsjYwYKl3q+KugehaGxQ17sHJl4Dv6Yaw6kvaTDItdtMlR/0ABfk8D
dvpwXbczWbl9OhJPMXUDgyZJhHiCGp0xpRv2R2Ji46NPkcJ0hVCimenTk3t7UQA2OWnUxArTGHec
RL6oqzDyvpmC4HCOWoql2s/vK65+0SfLEI+1SmmmGyRCrpAN3rfYi+ialPaV2/dGzbgsnP/v1HXE
/+mn1s6vlcRJ56vG1o7rWnu2hU4dLRgWLp72u//29s6Ouh/E/IDN/KXA2P3lV8YP1/EP5avXe5mh
qI0AOPmc/Pe/mFUOViCVFpnseHd486lAcBP20qWbfB6REJBEGupbvcmbx9DE2uOzMCRJBUDZnbz4
DrNtqJb7IZ/5ZvZvAj8z/A4/xOGcgTDzVy6DVp7AvCoBVyfSx+yh9tKmlGEp+MkNjGp3BZzHSjM4
BH6GDr2J6t/o7+BdwfW9OMDV5Dj2T5x/P7T9HE9AjA6G5XKkbvuqMnJv7W3OPZA2W8RQ1ljp6Gwx
Djd/Nr9TDcSnn4UgwcOxqsp09Kxyo5ZD7+iNeMKuT1c7Vr0V7mo+lwVMPSYCGoYGcQtDaN6yM+/x
zgnDi1rdWrwvfIb5MM3MG+bg3vcIoaBqlJQFlOrbbrlJ1BegqPa40WLVo7GhpsvW/YRuFg+MIT+Z
4bdH2kGvlLqHq7eNNZtMIdsbpWNY5L6N1rojFlGYv3MzT6oHhaO4Ks0+k18b+6vwERJctoBwHDyl
FjTkKpQUHVP984jH717FSHEkIawOzm0u3iq03to2NYtrijJpSDQCQdtrX1fYrMXsFccRXx1uvgZb
XoUWPvJAngRB8Lx/8+iMsvHRyUJ28lLJrY0T063UUsxZVmef8ReMskDjz9tQdeCEHCI2vxs8J8rD
hrjseolZcafiCqWT0goDQh4KWZRxt32egQZfj8IsNo/OcjUSOhr6Pg4SLf1WP7U/EEFVJkCr/Ofi
M7FK6agjeBvxhTeErY4RPwFhHWQVIZgPeAxqj4XG37rcVxhPoVtuMtXdULYn14EshNq4RJ8h3WIl
2yHSQMUDHV6Y5L9C93gSYBiZKIrUB2JD0jb2IXeHEH7zvJ1gFMMBT4o5psHmuqmgkR+nJP1MwoWd
HESpe4PO/V7xgFzdZyX1Cl27Yg3fLlTfK2N4Acvjx3RYBFa7ebjXGkvwqcUOMpPDEb8R6ZQ4zbE8
jtWbMqSW9J4iVLc3aJzmj4pjGswBmLVtqYSd8k1hbMtKt6/OOgzoRDh3Mw6a4ft6/tkEBOVLB1R9
/GVCWhnFcp9AtmJsoZumI8xWX6eJjUyMeEe4AyXSuJBCkB6UaU34VYGGIoQe8fKzjsa6KrVjaUr8
yCWn1MITwAZz/rQtxLsvxWMNbEXHAVMJJgYoRCtOw9NYK2MvLBV1XgP9TFEphrc7WFvq4nrEwsl/
wdvD4MmiK2sH8qAw7c7qFxlrmJDbsKIzkKEuYkLLdBEno2Xde9bHsITRSY9oR89cr7JJfYFgXIBl
dHkMMYuUDuyXfa0pX+yWlL/pYnrPOdL+9WxVOmFnAlfXR33yXeLdn2qhBTKF9zUZHd4tbTYckiKh
lY92GMykzpP63YKhPpl/vnkcg/nSmUIDwULWhP50kHUCWDyRK7Qf0O/b7S6k2YP+j3LUeoXImoXo
WacdC3Y0P1KSGG+cGvNuBdLovZV2w0L9N5peWYcRSm48RcMddtj3DmPgOPSwGGjMJ1hWvYM3pCuY
gsoGQJZQzo0HlMJXmpbWn/kJPCITIo/xxkbNAeCP/16fGhNyTtMv+gnlccnECo8fO9K8NSazyOzi
odaNOG0VKmqRcI3K5JaZHEF6f57BIik7knUqqgCZpf9Yxw5c/gilkCdw9N7vXgW6X1E0BIej+m3J
1w5UmMvC1A2vqTDyYu8zjtD+oQZLDrTfJ+RsPcqKzfi1Lr34YanpgVPrxGvFpXFjWkYEmWpTIeL3
H53FVgpM3n5+/juSMh7Sr+G+M2ptBCctdLgjKnJ5O59gyilvznNGDvWEY5uYmh/fTOlutXgQbcQJ
pWW4O95duQ+xNlRldwteL+Wj0/6Bz5R6AqsfduTNpNiSAH9G6S5NOrSgzLgeTMPf93KRBhIX9RR9
z0Bn+ZCWWx2d4zxVFbvQvxmCF+06b1IIQM4BUsYsFnhjQgEeq7oXdMQfB481fc7IswxDZLbp1uch
anzLIgc841WkHt3bnDAIFl+Jq65xsaTFYouQm2REXDt/rrdFJG5drfllXPbOSRb8rE4Kw3wunUJ4
rAS0QgkED8ji4dwCLygAJ0OvqVlziMqBWC4yIVtY9Tj+fH8CzTFVbleKMFjn7jhO9YW31yAX1KqV
qx8VYLqkR6Byzun+TVbiGNacNUME5BS1aydP9lvZs49psue9bQFDCR1PcnP8blkAGpB8nLZomPOd
ux/7EXKx5lZ5tpr7sF5iBIfZSQjW+wq6pj5ReQOxSfZUNO4IvDmBEJeIPqCfX9PPSUjtdinQrUlL
1OvpLWVr8X6yqr7mXUvQg+cvR6RxBoAWYWo7jXFQkkj7RwpfSxAqtd9YC+Wvf/e+WJ8suizUwTJr
ki/B2CceoDeGnpWBl+TSu4gQqUb8c20ExaEVjyWrmEWcmhAnoG7Q+IpRrrdafbc/IyPz4o7QdS5d
LxOal7mscgI83As+UeyUsJacpSdqfSxiFzwyBrEfoZImICHFj6wg7rC86YrHATPPLWKN8SKuyuOA
hGkra0NUBJecM1pBEMQogofcrjbVOv6iTPIa5zB9dmIS0Sx0tLmxAc5mcg0V8EQVLxbdY12i+WbY
QHFb1xmLmm/a1HVx0CKbt2g6ccoGApdwY5iU/2N+TqTX4/ry8rCNzXF6ZaxE9eTl88Lv5YPnHH2T
2WhZHvi4vRxMYUak82U8fWBf2n5MlPovxjSLcEdVZbXOuLOSzcv/+3K3RhyFDACYOMhIxNzchZHc
43TTfRdiVyMSn9o4h532m3fRP8baCi60cTHGn2uIb8000u0rM83T9IG6Jg6BbAz/GrzIZp5XSas3
vYNQeHSwPnvi5OFIBd4Kvg33OVE/Gh8XPApFeHD5p0HFq1EjW1cke2QG//0PByJiGGJPZLilZF6k
AHHTrhINZFYK93mQsqU8xn/X4rk4hKN4xWkJ81ZGsN8NXDYugN4YoBtKkjkcHfofgemG9IFzAyF+
dWjP7Rb9tSigjSZCh2MuVeZ3/NBxfJYsatG9uO5c9GXEGSjqq+dMFe7+Nxlk4mYrDx2CnleHF2wA
ZwfyJx77TdBTTEE35pTFmOdCbF9hFt1eh044hd4LjumL5ODOnvaQXNzFY3xjI09c2G8E+01f75FE
PazNOKfX/AHYOFVsZTlLcy+yH7yEbtVvnhK5RuUDOHjk3tb8KtNyZo5JD1KIiVgq9yOip8WWLrQ8
dClAZu/2QsGu7uA0FDIHzlcpyhiMx0xbQ/wge7yWb91lJpkA/oHwgd0acDwPsE2CRh5TO2qXVbGf
kfvrcaKOMXUXMcc9UOFaJDZ9rG4IFjtP6oY5KRJ+74NY3Xl6Zho8SzYpE1FYYpZt0CeAKvm3HDyb
tvJtZ4hrvFfTXoDnIrArPTZ3DZHb4vP1qp4VhsDRDA7ITxcKcoKviheltGJg0Hy2isn8eUyQu4ck
1lrd7ieY969JLO3oD2Rj1NB8RrCDo6nJ96WIYrhxYFBv5R06GPAEVC6kXFf3EwaA/al+jFkyylxe
nqHL9bdeIOse5OkJKS69tMHcvyrkg9LDUaTWenLpPVlZzG9Zv+sYWd6IRZTAlUvLqY0/VfckezLx
wCGy5xSq7BnvW831irN5R1Q5N1K9LCZEd1GpduWsk7t44wdz2/8MQJEccbTpkr9XvpCuBc9o/39u
3Rz7zhqNxFASHarjIGboTjkGrWZhxP8zc/7OGm0FFwbxo1FHQrzeaEOW2cJryWwySTEaXNd/HThq
Jj6ODzkVts6A3YqwYomgklB386cNqSQkA7NnhVGkI8pJ931V/n1W2TT82C8cgI8Q+BB4Z+9GAUtn
rd8yFJbh4CmSs/6T8SfFAK5mX1Dz04XxkTFH7OMg8kwFz125qXg6ljtWvSdHs0mUpgJuR/af8OZ7
mosenaYn5PWfapyC5DD+Cj6Bhn/Kd9iBvWbRuy0WtCuO1IzLdJwZanUdGcAUh6LwmM5LwdxQRRhK
Yhjk78KzNuIG6cUq7GATtBlKNTej1zGtdJ2+3NmkbacJ26TyBQC61ED68bz8Uivz/dllSljqSOtT
xIscgMYerOez6PsNMP9gcBhX5/Uz/nwhpnzyFRemqFCi/+XJWLjrbWLkvUSua1XblfgKTprP1OzW
viRsjD6/Pan5a7Xzg+RdbgffImt+ArCz59FV+I4D/FfqUWimSThmePtHjPHrvRqEfXWp+vADqlYz
Qn7TTadnNpg8HrfnMT97eLgVkcBh2yVTS0DwYO4/yVfjTRSzo7rYe4Ks2JslJDby1PmoVuueu6Wx
0wVXuo2FQeYKJ7DCl0LDuHAiepkm3F1vqIlVXBg3dJZwlo4zG0Mht66v/STBpFhCDaHNnoHqtR37
kPILlx4rdggl793ryDHTFABFbnA7ASArRVhTWPef2N8NuSAaG7hh60rroKCRId4V72+pmFIbnCVX
/rUHpDyTFJyu53cehtpt094faUCuSclS9iuLPlYtuY3ImTzZQnTJMW4dgPg8CxBF5pcFC0SdJY2y
hFcBXdW5NHkVdH/lSy/vp5X4YLu0GntFajrcLILzDQY5vUFrMpKK3xqf9eXu4hlaSH93uz5/3x1/
6osJYPh0EmhG1ph412IbDISz79erkjxcnPonmOqEs4lOX/Mq1OxaOSxvI4UWow10UVrigYXUGGWo
ebvpwmp3kFitamVbL3GjfwED4rD+8+IABT+kHnz93uUW80Zse8r/PJ32A8ZmqRGC+1wblNmBTZdx
UCY+r4Rf3bt+0jqtPw+fZBbRynGRyQYerMTtYWZYNvTAVh3OZ8RwkeZ/mEftpfguzPqwuy4XKOUv
1jla3BYecE5ntzI290qKpSCOgd46FB3fC0Wt1vqeYRuU6B33sHJ/Nm2ubj2xXphqE4ejQIE09yrU
6Q+duFL9reFs6r/Rj8uYN7dFh2FK7Sv6YViWCnYbhQQ4MMMK5Z+o8XELdacmgklIe9EankP1mJoT
3MdNt32GrjhJ8XtzchOFURReuHJOgSbPRUYuT4xCvSl0QecejPK8k2hP55EU3DKxz8AlGZQpsJRE
91ortYyprC2u8dp3ieI9gJA49F7lcwczl0c27wQbMpbNQY3UeQFiNZHfJZ394eM7uqVAso/YdCkG
cXHY6NMn5YJFQAfsZ51z9TNnjexAP6lyaK10pcBYI7Vj9VOhu9D2QE1WBSUa9espNoCAwW1WggFi
7PAIPmI/+BS5TljvPLDBt763FLsAPrMi0eKiB9Np8kC/8kKGOL0alO9k6XVV+z2bA5BvEd5xmZzT
XDee0mubIUsEd8+KiDsYJI3vR5PbXsoPdjtDpMCjY/ZxyXplGkcfMaMwBdhVqhwD3uVlBLyw7C1E
M3indSUHmActqQI7l6F5kEoeqBWIqFAnZqx+uxBnyAlg1GiWPv0cP9YcKkl6iegD8R6VlnEA/WNW
y7O4o2oOOUnnFSbG6WY4ZIgUQL84Aovp3MG51jViDlhDA8JfCQtMA20C3byQBoBhV2e1FXiJrnO4
SUaspwOif/yHh7FMbV4/H9bWCemrAr66n1OQ2l1tvlM6Np+I0xVo7wcQB2jyUEd4FbQ1nOoT9vyi
shzE4bhpqJYKWm4L7v8EqPmkRSJnxxg2mXfJoAI+rzsT1qc5/km56j6deZapKcq+IH1fDyNiT7uB
Rt999qEuH/LgzQv6pE07f7Zgb+AlR8TuivvOcAFnAjMKp0t3LTPDJJKQtIEk/g7SfAsgeccQOCvO
LYKFlC4jnuta9GcHGe/xPeNZ8MB/WrFykWACPfwwbrP6nY92EZAOef6+/jKRDNDUsuiyGW7SnczF
vvFI9jdRDAK+wSB32DpK+d3HENBTyPbEZt47NpTIeByqeIvDUClfqxB72mXxENa9XLOQ5YFKD1mX
+P24FPfvaw/uunDi2cen25t7MGO4LBzWbKAADC6VpOHbmZX95FaHoUTprtGjStR9MA2SV3BZZY0U
n3kv6LU/xRRQKwLCTyK03xpJ3jdE5MfuOaaz9XN3CZ5Ew2KOy6OcaM5CbXlgRailE2TgG9iZz2Hs
i4o+R2Jdkl5k3tLZ2KuX4cxpin/IYhocZ92Ppz2NsVO37BC9COVa7spQsazEEh7gmkyGSVH/YD2q
BlENaFUoKg3/Fq8M8vEu5b+Zi0C4Sy//l3wcPC1VGBrQK3sVFU5dFux6yM5UyvwdOda84chDU/jH
dRwDqrNLKgdbD5J0RXudqWZcNmJTnIi0xWBrW77WSMgN4fN1fDbm6PVIf5MIImVH+tSyKVbbxYfd
43Vg8E2tGbBB3n1vxNBOorV6jduO85IXRfl7GKRb4KOklAN0r0MkRxljALxJyMBswfwa+lbj/Vif
kj2Ax0ksQKvA+g7MQBLWnuMPPZeMl1EXF6sHddh1AmsV2+se+douGROS975QHbt2PkagvhPxRrJq
1j44ruWdPVSETdnKyU1xaFNZ01oshn7eACnk2T4jGq/GICKjIyfhglS9gRTAryubAcpoFwDmsfwO
jtiU8CLNvYIzpiHP+HeFZ784XnaDCZUjt5nQS/smB/ZshJoYo0byFvD68Nx/7olNOQRscrGLEUoe
Yq5PIYogmJhZsgBoL6EetW9U+ZPh4/X5qNb6jQGQVy0dJFdJmHivXgNua6gGXDOrUcgcVK2SPhsE
TL/HEnFZzYhbXVrt7hM4swcAHC7mHb7BKZ7I88Z1xK9WlwJDaEntMfSlmXLRgT3rE002Hn6xZ9YM
fsOA1qTic/OogYERCshYhxGPAepv/L9Mn9NCbeXK0TjJxsaAZwcb2CqLRFsYM+6ejmSGuCwMLZg5
IS7HPoFJhbJHQ+HPi0QJbx53WNFl1M/CaGDtr0+ZE9O9MGBhMo/dwg1PR2SzDIpPDRqv38/NEysc
6NSLuN9R7EdPqLnnsvo0NNIR2zGPJ1o7FLt6wJde31O5nkQv2NlgkvGZi96raYwVa6Vqi7KN4NvO
ro0VEIcWf6mglQGnxP9kieaZPTPbrpZQ+4a5UoojRUN8INxAK88aYFLQ5TAG/F7AFYT88ydjfL16
jYia16uOtzyr0JLGqVxXBIk1k5SAjFW2SBDcyA5PCCAvqcZtYlby78+JEo76ydHTJzWTOt9jnUlJ
J+Q77/PWHIY3opchBlRLjvZKdG30SM6H8IAmczxc6IOepagWcVu9YdDCrv3dE3vhwb9GZJ5WIOs+
4Y1weLkFDnOVVELVLs+B8XduVOYveGqlOEXFu6Tf0wuSHEXr+nRZ3SC2OnVvx6KLHQ9QILS28DET
CAYvZ8+jVC07/SpGevITwKvBARDR1rdgYTANOyMNnLI1cFRMjuir4w0yNeVTQenQH0C0T0RtCnbp
TD3Pr+FmIc2QS6ekP85rnXRBlXbknPHvx8Z4MMKUqSkiXvWmpwBC9+SxZTTywcVFnMEhNqNv30GA
WSbU3qZzEk30BUKMn38m5JOPOxIaU4nNGg7xccj9DtOQqMhGQZeglv7ThAXJAk5gjC1sX1SrYr1G
kWvev5L0/D1Urxp36COHCOQ/Qpof3YzUXdyHzpyD8JZ5MSWUq3UA7JNDdgRExMeoRHE8dX9MOLbA
UYn6I7kzi94t4Sl/8Mj00Ip3pBnzzN7g1x0nX/uVxqhep2nqZH5qbuKSTB8poH8bzANLo8rKLgun
UzK0hNQIa4OSqRjHPC0phIznnmIyIZnkjmhVS4s0uPptE5cYgE2+Qmrfy2eJNCIRlHtYATWnVcXB
phj4XvZZ57ifjWBvMSVHMpiexSkYIwC+VJlObncQjV98bwtxQfFvodLc6U5GInnfod2fxmMt9yag
EBm2j/InlEykzep/8q4Ak8QldOqhGvpLxkJXg576IjOTBGaqtdoNn2DgJKFBKdboOWP4E7SzVBue
4uVKVz9GJ1f3XRHjbKlxsQnOB025ZkLSLYmqIXIdbFpaFaynHMBmmvR4z0KlSbMgNeUcgbJGBp8O
xnW8RftY7mQQ5EuWLzxNe+tPB8TUggq3ZZVUIWYECRtniOy6laxgGdrUcspDCQG47LUfHJwDDgT0
fRN+XaUus3LVER40sI41S2+LY46rtdjjnp+O3lGDnBrWOOTefdrRBFSIym7ZvfBMmfsZpQ5Wdmlf
4wcQaxIh3LnFG3DBhLgCSe3Nn7bsjXPmNOPgpabBDXApfUvgcINcDU3zD7cmGDqGrYe0XjDkXdAk
acqEY8R841EWdT9n1FErI5eEKrQxSvGql1jayKofCBNZmtixgKtmoKkLn/Jss1MhbrPP8r2BsYrL
uXLF/dknKMDxtHdZ2AIbrAGDTdbcWGjDq349zWqm409eY8MwOUUWAN8+KzRXlDTrKe5MJEAQe8uX
edMpo8hM13ttOAz67V6w5L8WHNeBkRB2aB/tXQKz4CrTqo4h7hBmEkcbNqkSI7bnKAcZSr6NA1tc
EzI/xQWAAn7UZ/N7BrQCKel5i2Hf5BAVHTi6yIEc+ZlPc2NWbU0QgirtUY/MBNX5CjCaQLZsKnNB
hs0FB9XFSqEid0VoHbMVS3776BbMUL+Ahc4qX+KIo6FPiIFIfFuo1ZFh7fwGJNqAbDFVvP6U3VMy
IHQEwwy8F02QpjaIMoPNNNI9DGSbR+LSGUKleua1jwzDxiROZy1Au7wjL0J54PnqYR9iIgw6rDuA
epdtrsF0535xf7JZfuAnvRp5xMgkTXSRdd0O4iQiEpO3sDUqz3WzHuJ40QkIGXr9kVs6BJJ3Qpfb
8/yn2s9Q/T+7SackXApdbOvxWNXNw6ir/H0fGdKvdiz6bCEXhyv+HN/hzs09/Z+JkzcqjfFUUcIJ
JG0frTRl9eN7cKS+Oyro6ZhNZ5LZTwVVdzBIDv6Ld07atOHZboN6Lf5HjBXjpgn0VqSbL2DJ1CYp
+BjAacJn+ge23UMOd0HQ0cnnt6M2qcRqUBOHVtSenK6GkPSexrELu14Anrad23OK7OlbntCmQfQv
1sokIymHYPOyvV+luCsjTOVKBffB6WEyECHvEDE+EVcyYfvbJkmwCf/2X+m8Fgn5roEe5j1AwkOk
S6OTlzlc1zwWuLRgRjyngUTZqh2/4pD/hAzjMsfKszRU6H6gPEFtg9GBWHoHk36ZeDM/WUjRCCL0
ahRAy6A+um2BWYEJsBGcrnKXkXQi4iW6/RZQqdN268KpyK+mgnUaaDeBXt4wi7RuWvC5scccXNBf
jT2YEdWrTmMz2G7i787KTmHGQ97X1zjgaJeVsJVxBis+NwGNaTxHOqoyBcL07vqoh0Z0zmNIKC+V
dQIO+fpxcjaKT/bL/8JgHO8s8Y/SbKiqRnBn0RiJI0URRawiS2eVWBrj31eI5a2wiv4CHtkUg2V9
Z85sUgRf286ynBFnn1u6r8SkzLXCd48xc6JlzK2PG1ROWHmvEcgP/dhAzkbpghdp1JDhEf5iseK2
6Qv7C3km672HTYPc4mAr1QGioc4awpUChP3IppZD/DKg3ZlcMf+6okOONungg70FjZZSR4sEw3IS
RHGMjf2IzWajzuBXolc2x/f/5ooc7XBXt5NeMNhZX3ij8KtvnOqrzoPxsbehViRqe8M9OWYNCYVL
VcPURQVyQG4reJ0yltltan6rmxIpV8GROVeFr5bH+z1YoEXYVbGNGsYADBVQsfaJZIie7Td1hWMs
ijLR9lTwW4jm16Ag6l46mOzWeu8txQZD3/qE0QeABNb7MHYPf6kxdMNjgHV3I7O4v2iZAR4yQrwB
fYnN2tkx0+wOKV7d5lSg6zDNxcM2WHwa9NP9JLoTNH0G3A0PpRsagSveJOjI7hC/Gt3QPyYd6tP/
Trbk7OktCfyt2ZPueNPtFbVhw/w4I19k6hdO+EcFaFU8G97DiukRiZ67hYlVWFjhQwKn/JHXqFG8
qoJxNZwqCbgssFp0S8c2mdEgiw5pY6EEK1bG3W3UJZcjgO6Vrud8267Ogc8jj2nqrWixxxrrQCX+
EGkJYi23ZLRKkjYMLVyQhJ5mPatXjY6v0CP1sak/q6F/jSEFPs/B0bDkjcEEcinZtE+IhmMnzCmd
TyUeOb/bUaUytFwLcsId7Uefm38qKusurIGlIgDO1y4ceIn+s2+TZbDY8Ds3I5dgxK9eTF2d4CDK
+tlLRsMI5LDKHEzoC9WPw4YtRbXCFSGFV21OQchFikSRIlyuuomEhxxlJVtINf93NRN8tDiJpqN1
PlTgGJiKVr+F3bwz08V/Ps2pccjjiwK0/jZzDAlThM+F3T5qid/aQBfEqNXsW98sCVOI/9Gro+gf
mMO0PcEyUq01QwlXZBNS9LmC4jUupyBD1icagWWbs27N3OAcyAcIOJhnSm3r0StyqJC1W9+BXy2c
Ywyvx0a79BV4ucBiols4BEM36K1YH1i4Q2cowfCenBtZJH/y3faaHBM8Q7hJxQ7NGD79LkSdmpgh
VXBTiXnDRYnZe/0hku0eXB5NToZFvxVE8foPFydf2zPZWsTbyDEMrgag3e6OFBdaOhOIGTqUu1Kx
KVsceiZfh4A0Y81qfu7UsCwR5pI//mErjICO05IXB2Irs6oIw4zE+bm3nIHCTa7Nc+Nh2qt0fzyJ
reXBZORRwDzC82LFQ/3+zuUZdcXIW9pIJkyydwzdJ3sF/NEnkxrqmkx8DbwdouvtEs0aTGhvp/Ri
6YhhZiD8ucDNqzPWrmUm4n1FPFsBaX1H+W6sBZIGTAR99N+PGE7MyyUzWzCLz5zxII/mRjxNEi7c
fwVFA7G9m1TtifCIOpm0xJ8gwZWUzGlvA6XV8KNOTtUSRF+e3u/3LeUKtE5TjfMyyuxRed3Y6I5i
VeoPuLkp5Z1rVuwaJwwq++mNFbF5YBOO8r0DKUorNUdVjXKyqBGG9Vrhqcb6IrweRdAaMrRBLv8W
QB1sn5JHTjDr1hXgOHkXXuXlPaTaOVhLYNv/7MvXF7/1HhUEN+J9zfH0XikMSn3/DyFa2Qa2yuAV
A3mdixnKv+8h6hBkXiQCeuu+YpYGw4SwwRwbfnhTGge9ZQh2Dn4GwAc8okIXMLSxFhME117dqOJn
yJIEKxvqQbDegaP3N2BZTTOIfK+utNScfPZ0b9RbZ9IubgbTgylA6cuqLsMrcoGmJkosXYMOdB8C
opGOyM6UvCRfzlgCiVhDSCzTRIlc3CNJ0ofF4BUHy+FalqUD4w2G2duiwFY0PTyHGLg2lPv5xrey
b9llaCLb5x3vNlfEXgakw+pt0vInj50/dKgYDRHwEji3N4RCcqi1eoqSe3YiBq0T8y07KjVQS2RA
zpp+ymoErfLNMmVSww2a1kB+J+Vd9z6S94Dfiiz3dZ4f02m120ZbV0QT5PD2s10dWcOgezMLWntJ
2Yvlyk1t+OEejdej7PXHBj9tnA++eW0NDo7bayBjfwG+95wtQjAADx6C8ul7fEqbOPVSSJPYXiAl
xPhOJvWx6/MOhNm7bvyp16l597oVOpCTsICJ0MLmycImcZrxRlfxHC021zT5K4WQ9s/td3he0qWv
GRsJqcVls6BtSSaddn7/koEM0+PlkjgoN1pc3DV6H4VSCqdJCi4MDfv9Ds+r6hjlKGWITnqm8l06
VclQ7k4YqkeMQpago+wL9vRayRZiK68Z9V74vTk2D/F51Lc6+dvkrsiWQUWPP6qUZtnJr8awuVHo
wzX51R7n45//mcB0sruSMr+ltlhuiFp+p6U51T53tZi/J81e/KcnxwqOC3apbwIqn2DHgZmgAp2R
KcnOg3PvRx8G05LTn9eVu3mkblL7fkntcnIeCajnCoI8MPA+sL76nHPbPM3q6b/zhnlkf+UIS1R4
MpCFB4Ja1KRNLx0LMWJbuiR8MFtYECUHpWKYVMDi9gTXQ5MVvrYoty49Gnkfy4JWsiedgCDe0Hx3
3g6YuVOk/pDfgex/uqSQ3m1xuygK2YnMuRLxjDzyNDAcEzad2Q7hTuKoO3QtddqfdoIQDg0VASbw
TB7N/UTcgiAqeAv9lD0RiMojCujRz8hS558Mn57pIkbF8uu8O4UXMewtabsjrn3q2AztdNljKHhB
YgAcBPE/O5z1uf3GapzpdWvH6H2Wx6ocSAYGGxfHjKKFnY4dm6Of2tzziCmQpw6loZEYhcBtVywP
TbdnMfyKD3M9fN2HoZbU6UqH6L0uDLvH19MXOP2b/yL5EhpcmYNFGt9rAMK4UMdKKTVsuqu27lG4
AKzTybTgIdcB4KLaSVuQRNTZE4Gi8jXf/kYGyg3d+fzIUcQ1PUGSs/O33WKt8s5F2z1FL3Y04/uP
Ri11swjK3TZMjnz5KiY5SK/EzDe1OnYIkFyRDMtSJCz5vlzsNBvJavPB9gDBNqC+h2SeH+pgzdBH
qRXi8RQkZQklNGLtu7AKsGjVFGe/HdUxXPg0u2h6T5D9pQvYZD13RpISijuVy63D6SAWsfSwxVy4
YqbnbYsF0QlF1JCyS1GreoIH4Jcz98wxFFDGV5AAfZpc2oEHjmVENNVUfbL6eXFsq1s+Ch4TpcfS
zmmxLT46XYNoYfbFucdFsW1TNppXenQYn93pjRvBopaBAxsuuqcGnjhvh8Dg6z734ImolZNrmQXW
vugAkDnYccTYk7VLdJrt5WeqCiXipMb6oi09hDeGvAI5PSMqHzfsbIPrhLW5fjXVF/acOI9pdkMu
1zi7bs1s08Tel1yUO+WzsyN56l7mjfLHROMyeTjHpjOvvbevj5rzhU4FmGeppuMsdMNWYaOMyGms
AoGQezLrO0M7TbiNq2TADlmyLzI+Y+xREFz+prpPL7ABFB3qf3SBOijoXzm/oRHP3rxPc4YkDZ3M
xiVQ0vYH8lpGrJ0Yu/XChoFcWx1gJFqlEJ+UpwB+oKaXmZE20aokltDPAA2PVmq4VkkDStZviQfu
W3evWI4zbVuNWpEcHglaNPD7uf/XQUdQSqwBQbY57f7hm+/Y6fm6JNRO7Z/o214tsctNYNUFWMSI
t5U5vOvRXCP7YhVSuj22pK4NhjLDxOdoiTBPWBGQj0s4BviaLkGCXvbLXc6gh+nsrzWOZS++q+x8
OSb/koR3hzO/OyZ6bCzbsAIDagPHlJi3v+3UOL5nSY/UZrqdD6vqHMIPG2Lg96u+k/6t5qPbnLnk
nTnAnwITbRPynL4H6pQC/TClg782XaW22JL+IzRFH6XTh+HdYQEBOV76+UCzmricDO0JVfcew/5+
ItZcjChSIU2IIYKp7em7g120wjRB6zapPduZoXx7gNpAd9wzaFwbrd1eQ4UFMoD1m1NpIiVZT1YF
Yfn6UUiM68yGQlnaVLHOq95EMc3nJ2UoD0S2WEfs24ymMSE8/8jne9hiEdbEHF/SSxxSO9XrxnJW
TUbs8hLMxfHvwjXVbqmjyqWzTSFyg3pY2IHX/qckAvGudE3Qau9vv3HIYG3VQsW0m/5wAHIIWbbn
UkskK1m5Wmm4yXEnHrC3j8kk2ExMcfNSh+sNPR7NgT/NF4T6L5XKKJExAAlXOY92QtLGyaf5l/O/
Gz6uVmqPR59vlWY/f3p59I6pM9OJeMgAPUPjmru1MnvZLZXRRZRZZ0Quu3m8bNmAX24W0O1BNEEf
jQXht700iv0vLgN7Z5RvGGrVfj3ioT2pbuzU7PG/W1HuLVBIoaryujPuCyLNus+9CqDSf2CCMDrh
Ontybh8/E5CynFxqIm5jKCBVi/aLVajh3pOYXGN383gqxrTdvp2uzjjneGTSxRP38DW9nzU7FrKN
YZoXR955WHYlmyPxSzv9y8Zjtw1HqDokayuNWfxT+QpzJM3ALK4iC331OS3kOwD6T/j4NgJKgX0D
++1T1ZGg40aYtAEl635Wm3oqxzjbijLJWopUHIH8diF28eZrZ+8POzhcY4Y6zRaTSg3WULOAIeAb
blncGh3vyOsVwrZfbFx9qmK9k11gpLx+2PzQg+PPVgk3wja6+ISyhAGS19ylGT4GPLroV/qPovoQ
+93U73Ss0FEVTv6bZnhDaH1mncDjCLUNFAZHUQyNM5ecd+oK1t3RKISssSCpaeM3NSvVQqzaHM4c
z0XsDsi7GfWRsQ32Z30kLZv7oEB5HiJeqGY/GnhNSniP6B+9F5vHXpzERfqtDBCg7d3Wvt9A1ZAL
XJMk9s27uO27qDDBsoUhXeawqf5cTVC5nCj5CnR/D1Iv9IfrgXLQv+jBSUK5BLiVc9BaBmpLAsil
ZFivRnTXeB/Mut7HOqz+I78k6/NTogVwTdzGANqdgs0AsGP8daxw7+3qVRemcqaLdIcK9wCfxleX
4jaiaj895UAhdZwjNM8RIAzFctNt8CfdvXsKHIls3/bkve/3dsgOxgUN/WQZL6eGm8ejnn42TbWw
9JTUUAZTcz2aH80x09m5kvLI1+XeBosrY4S5RFQo9ZDIBR98GuvSulEkGTOXCYNgmeaydx2l6SWA
cNDzDbkI2e6YxekKNYqfjIuIerBzHOZa2s98UHdApumV1fs6ZWZcJ89O6ePSyfRixKN7iLOkAvAh
spCtonhaw8UWfnFIcmS8+sbS/2ZenJJyEMJM5e0IAXsPKc9MDyLWf0Ykb9/yGdXx7qtw0KcPqW46
365ZboOKyPfJu7kfYMlxXNsT+9fTmrftz6+hfRMLm/XxRUWlSiHZU/mWNgGeJ2dyglt5RBnj4XWp
hwNJCvz8Sn/IJMhanJkI4paQA7ylixYsxlddMI0MosSdGYqVXdBNFh20vucSdFQOhb++2PM+qfv4
lzyoNFwq8hCmQ86+83iAPsNLMyOO4dZqyHt6LCqOliaJAioGT5ZRTK8NOgxbX+qoHIUkE1fnh8c2
C08x/WExARw7e+5v9j7oirMEFjkTINP98do9sQRepIM2J6F+vudVPYg4BldEQ5MdNmbmJ2DoI5/2
KqoP1RHtMHzF/1PLSTcucFzZxqN0kpmrIYf2RlnVUPTWwnjyiMMzj5EywIUXdPZh+lDFOEXC9Pdi
FBTRffVLeLeXkBw2me0HpO99a/W4SmSjllia0aNKtzlWiZJ3MwIu8PPBBtr92DWQnjgdgBQ9nC05
/H0t5t6AmxkQDTal7KbR5Q+cub5Eor9vC5IF+wzfKltQp6NKDL5PmfKZK+VSWm+ydD0AXzSUT5JJ
kor+Tg87EUHSacqIINanCJy6Atn00074hh1ldUaCQCaIY4uJGayQE8FfmnV6Hf6p7pV6DiKeIRP3
uc+LQZ1aFB8XyGHDUPZOt1RjzCPUQcDkoRo79DZFsaRMFzScNxsOmmNPEqEkwwBPt19vgfSJ0WW5
iLMeGfol96y4MG5SsZjQJATMuvijhAlXcS1fg9NtC4pbqw7SEXJYfHyGUFsTRnVLhJxchsfv4raw
8GiwxPQ4BipJzUHIWe6n0/yIH+JnI7cfsVhNjx6vhnDTLzYs8XqsJNZLiBKuRoNj2X4WUajnbC4h
XU3PaJhyV1r1YZcCrbnrN+kGBV1BbPFR6BKqyf4sr23IkKUknr1H4Yl+TRD6h20uqCjmxpP+3ZLB
w5Qr+NIZI2lmIxVpWChlu4NPt7PgGxBqpkfz7S6m9tYy5z5qNJ8Un4k1kbR243Gp5b9KGpNYkR+N
h4SztmOck47a/7XnXhfUGQm5PtFZEFEYZKW1VwRlR0VLtYqyQVrS3Va0OwnDhpSxNtfBx6Rx554P
SnWEb65WD1bwqBO54P3/COk9Nuwo/EVj+zg5rwI92fzRXgbzu6cCy82ML766xnbBThk5ZIevf7pE
C87f+0L2cQs1qlaKMfAv7YD1KmhO3w7oak/rx5cw2DQbOLHp/KO1zCrz7bjswKUXkr8tPOY3mpJ0
gJARMNfzzaErGEnW3OCuZaKq/9cILX0UWaOBuCgpajThfz8Ul8NgamqD61jlGUfoYP8xk/aLihI3
02uaJDdHCml3SPYYG9KiMBEHgEamFfSm3we2jfy1o7jY6adG4vEmsq2r4NI6GzBIkEg5KPUadaQ5
vC3fdu0plgownnKWkbQsk8yJPxWJBzwriqGrUzgVc8sODDYHWygAXBA97jUCLkuM5W4oj92hvIwU
OMsLe2uvn7E/YqfThOtXIWo4UnX3LLUslhGej9L1p/DvmVIxmQrgZnk1dJGxz6V6IMB3IyWYwkAh
3Ewll6lD4LZOpUZJs30MwjINU5pgXKqzAAlqaWbjlSvB6Ka2iA9CM22OhIcBhvEjnbwJ6qTGzIUx
SdDUDszEVNlDtWP2q3dmr8e2vYHA4ADXyHmiu7QSEmwSqvJPPK8KXJ4D4e2YCIfRV4k5j6uG23Xc
/flrVcDe05lUomxOg3pxhvXFn0Je1ozZqj4BtNd0UOWUR/Gk/EwknlWP//4Pft1wWXb9OzGh+yvi
zJ3FHwV7yzk68K7OeK6CfO00ZXrodJ0DcXM1G/L96o2lGIZEWR7m/eDTSscmr8r0ftpGawT9D1nl
UMgBSrDX0LWwy9GaRvnQaTFD4oYVEuuvn4dT80LwYeoNr8Q5DrnVc50RA9aQkhdBpuIR2Rh1sF7o
caivqyZihLsgJ3dS7c9ehaP/PKnJZxPI9ytNf5FoJ6W0keUnTCSgvek5/+kzQT7yKJuPfDVnsniK
kbTSXCNvyiaMKLN94ijzvG9LGq79WVc9ZfBVeefxe9maEjsSN/QhivmrK85KhaMEkVcQCp0A5CNu
Io7re6swVRpzK8X7YDmbZK7g+xhQSDnEFzfxwXd9fVwgbjIwMIPaX7JPijFMaE0duqRDPygGM4mC
WPUQcKH5/uJkXMZhAS/XyBBWEYozeAieV1YYYO8h/ReNxsjoZmPKcL1AX7o9NRv3pllmYqny3Dva
oEOxit96LYPclpfwfjXrdRsOsIZWGWslJTTvkC6+Cz2D9uMJZpEKj2s+/rFXQRWIoZUtkXZ5xNtF
4cih5yr5pBxJoovQr9cAgjckiqEDQI4qPs7SLvvqfgbiJyPzYZTC5xVZVoZn9HHXDoCbo+2DegGA
owrItmcWt4CWarGloF/mz5w7ysZhTIIQBS00KN3Mw9FJnQsEpNKxsw04BDdnq3EUkeohfSPZBlWx
ooMugItVHYH9zSoECOzIgSu0O4kbcmotPuMiRBjydhuoxqQ6y/WzW/6Qh+NM5dH4gDrdjY2QZIkp
upTs9RH7rpDEdkl8EFOCVihnz3XPurB2AmSsVisURPDwPII0pNWywWi8CePScfTkBCLfJYLoJsKh
qxJ1t5O8EqC77mIrHXxu6Buq5kQMcgnfIZC2EAtEj49a1jZqbGJalJ/wLJ9pi5kH/W7lRkBNohZF
1IthqQyPBt6U2QMSjvBDZ1OP4dZFsd3j3oZ3dV14xX8N+jNfxYIi+iyhvnkFX2tQY3kYvcDw2ycU
0WxEqmLVI2Opc84vF3dzb/udABFO3yPz2q5sJJs+xNDLDavxsSITJ/LjKK5YNGXj7Z7CSGu6Sc+H
yZEjSZSIMcYQXT9Ir21/+ktf9R73IJBtPXY5zTdlcSNnxryJuPunpPW7kCc4OXzPPx7TqDhhG/Jf
QNgID0J3UxFhN/CQXJkU4XSLJiOprmZtaxI5U4We8GdDZjd8i1ykgIOzkXgv5PtjJxlEDAPka0FN
VqSGvwv29s338myoiPOjBHtI9PCt8ie5P+Rb4Wbn+TLBDGGolcqVRWFYUOTA5WjzZWJxpAFrZLsG
eC6dInVPvptVMaw6+q606XqQk4j9G7Em6oOeKxXCbrJyxl52RJzfG/I8NIvokVmco6pRz8Pifpxc
nqEcdlGFTTHlRGlFymNp8TwJlMHlhGCSVOqRXWmVfXzc2bXrpirbRhdCTDKcIXkJdjeLdyL+Q3C6
zRzdfFA8z8HS3jz7ZIJurLYJKkbuSznyW0UNchy0z4XYVlAnQpHVXi58OkuLeRCKZvzHTvKow8tZ
EAxIYf7ybKyLcxvJ/A8f5Ymc/3OLuEDjB8Jw5V66xFm6jhrOPlP0L2fr/8BtE8KK3bG9Kk+h+PmY
RJPaQgUacnREnuv/D2MaVnvjfS6zRFUdwsFR63H0/zUqW/7mEVMFtLKoYzYiYwzFUyyBl+41P0+q
+CJS6gOslH+v/gha+byMvBWRepTidA/GspjG6zqF37FfZBvL7vbonG+LARyAvX1BXt4U0QxJUWRe
49E5JyWTnTBK57JcX8AimQbDTmMJ20eDm0VSYI4tEN8b4qcwF1riwQp6aFHay4HUv5eRI60ea1d7
x1LdF95ZUG9HzGHUu/Jn4wDqnTCnJpJRFadgS8Q1oVqSUE2kj/HWtLT6odFS45GOFFZRXqUWXzVe
IyGG3aLyhEH8TZTQnD50/Mt87Rj8Src65grFwT5qmo6GEWskDqz/f3HFB10Oj3hMKVlzUS9b/GYZ
nuRu1OkYjnSAUQ0YiZafPqShux02kxJYi0DU9SPCDwKeopy5f/CyAae/eS7ZYFGtZcUEE9KVSttR
74kBRX7eqti1A+RsVoyeuNt8LJcsv2UV5bC7mmTp5v+78WdRvZVc1rPa0A0q+e23GV/L7+cYpNvn
vBMcIw7S60YfWTZXaVvBvGE8w8wfjeGoYlGnuk9q+ZSpO2Fz8y8JmUCvwI5G4e/0jNIK9mknUVgb
3XGQDW+X0pE6aGF3FFpLU4EyYPgAjJZm2GqTHs5aiYTPWbuULPkmyhxFYVOKG5trgqDcMYppXAnF
sOhWKlKpQ8QmX6/E8eEoaPfyLwkAS2seK2U770qUrvsibnLPfNmDKcR3FBlkyLunsXaSV4Kr41mT
GtO7zQRtVI/inhkHlo9POjl9Zq7P7rRqOQMvy6Rp+2Glp76ncDquWEUoKdz/zAc1tXjGJfvyyUWu
2hZXHWj7oob9TjA4lIGf4D44Ez/OQWzFz+vd2vwkEKOJwmmnvKbu9ML2OatgaBraVPtrDa3vl5xr
SdlEhP7qd6j+rwtrLDslx8JHRdokSJPjP1l2Fi6Jw1QpjrIiEQ0cMrShcWCq16HytdGnK9Kip0w1
lsnDFiDV8dEHkAM8oEqhAut+wzGFkDflGuT1nB2lJ+cUHWZC7UUYDyYKOGJZuEaDcQf9ZoCiUzxC
ajMtWVtaelXi+F7fngzIWV1TLLAUqLZAFAgWran/RbW29gyIIl2DdRY5LRE1UbD69CJJgr60Hbkd
vPu5tDvDnq2tFiNdNBMeCuTkQbXDGcckKm/ZZ2br2KvTxcVIEEPubl7JXHsQF4U09QbLC3WGH2TV
wX8Zpk+iiuLhwogLr7oB6GycqB9078l1nMEy91uBPQUjn4E9334PjcFIogVXmgfVeIu1rEFT7mj1
PnpdtfVafJpwVp/GVJ0ktXknjmn/v6wbENOK64ClfC5misKi4phmbxt09SnGmQeV5QmaXzdcb3bs
ZBQkouAxLxqMtUVZU3r58OyzAwEJOkINpRR2yE8nKM9TmMzZzUAW25X3xUAtwLXyt8jNzYeb2w+A
ggNlrdC4bMdQxg9BT8Lsd+iblp7ivn9NhEeCLqs1qpZsjbshqpov1Eq6+vu4bfxvcM/Tg/eTUIfa
qardtx7fnVRf2ZHrJYCiFoxv2SIuP10ChEwan/szzTmuvd1WsHp20kpe+TkbZYUnspJdjw8T15DZ
6VcI9p2xPzyS2v/Lq7wGpF9LhmfYklu+k8BdxQKv7aBMpL3l3pLrpUL/29fTGIjJuZ5NbAgYJEtI
Jwb7TTKyptPU8ouqmo+cCvmMsUtgrxxJon/8xx+/XwZfULeN3nnYUZmMOM+GioXCkYVS7z2L3tjh
5fzaOK5M5kGiflZS0TMD0sNf8O+RDVjaIoPeR2KoxkJ4yryz2GIhSODcB3gERgV3yMGcR6ZtQJNG
/azBGVwlMt11TZFLQk87cuqxca2MmKk9AsD3j5mG/f4UCRhH8fn8FrhrVUJw4qlERRyxAWJvVNC2
85uZq68mC/P5p1nZpzOUzpevUV7fsV6Guj22KSOkju7xe6ZjaXWxn7QLHjXRl0zD8jlvDre4xjZL
uHkwWOPapEZ8wJtwTh+0dbuA2+AVMDKOuLemu8hUwxmTke8skWRsO3cN8tsSCrKR+F3rED/CY8/i
AJxNilprZH4fqkoQ4jZCINySkWB8KtHniaA9XbTNZIVEZmIxKaDJuTKp1kJPUXQOA5BNIZv6B4+u
fu8X1s/A6i5VqLphSTbogoCto03sq7LjVo4AnodTnoqa7otS7Yba4MgEejwxVC4IuAlVmj+eVxEN
JJwIKGAFnCikzQ8HIWowQECSHX8mNdBlguZ57kk0sYPhRTFEYdG3i1CRL/Ukxy7sRYvcDFjbwx+g
WY4t7wKCvKDQqUjkaVpRlIc+XRngybaQLhfAvl00Kiv/s2OWkwrTHR6b5IogiKn1HuM/IZIIZBFf
6JcOrA7Jt/7Od4JXecChPfkfWKYYFvQ0EapMl+ZH+jVMQeh+xksyRhWnMz3f8sgilPTqrkzaG8mj
348PWYIKTeJPYsbrt+Jf9lAxdJBq+GEaWghOC3c0mSu7iWGLL+F8dbNtAQoKs3XJqWqOPVu5a1tr
x7RgdnlXZ8rERrNIsHZyoPC3AIt2TOzmK82l8qRJGReIu2L34RVX91qXq79rEd7V/cd9dyjl/DQz
FFgcSfi/38+buRNaY6CBGwS22YTLgtr1VB6kbVOTAkFaESIwdgfGpdZfkA0YEB8coqdjmnXs1y43
f67Q/JxJ4pUyU1NwRZ5MsY3gmo3iOcVknF+geRi4OMZa1adO7eOe46E2Y10cINIhLL5A94X5zUt+
fJLAp8RVASbrjFP7qPdOnAv32mpeSi5AqmYfZ15q3MXThOetNmykQL5xA47HwwxoxLi9kUCNK3of
0/99hy10sfRk2twCTU1tv8FHD/s+buWqtCStqvWbn03OKhzK5f8Hlwf8OW1+O6Q/fvNRN0C1vrmO
IxuAYlExfaSAqKnzX2dSyezzkcxQq7dsX3VCxn45Y9YWrDiCjCpPsSa9Aep8QKgKx1M5j+4Ad7R7
UZQqrN5UG/5I1qaAv21ZpN4BGDmsKLhGX9xe8YdJu1gAbnZsXS80qT78mdPlFDiRbg+P5mGRondH
gopeZb67OUYaiuMQ+4P/gZm5REXTcsS4ATINOjfb+r7VyzOZY8Pu//Q7Q3C9r3dx4+aIQOVVIqQH
BIKVuaAtqn7m+EXSNbV0M/vAxStDrmGknHX+LJLJotIVmBtCZeSSEn9pHyr84wl74DHZGbgtOyEG
Zfv3OT39CgUbjXVNYU9S4Dklr9/9eMTsEbFh0fB14SAdqlHCLofU3iCt8LanYLAdvd4Bm/a1ZSfq
uJGvOLdJwXQEFO1T4wqLdRHHHMwouq3ekK/n16E4w6/XqXVQbOMpoY1OhLLfcpCmDZvmuyGy7Rzs
9w1J9SQqlM57uGHCw18/W/PRfD/0gpnPZfRRdCsEtlAffCxU7778ghHRISDS8EICyTXQgBh7GGJI
3Kd5qOSuo24fTNSJFVI14SK5D8aX0R7WK7Hau6y8rFK0L3OwTlhIXQfyL7cTBsX3i8p5VY4BXITT
qsKbqjLippcCavDi2DGt0S9jjeq6JPIqeO6AUW3cupy0bKH8CqtTmcscn/kSwC+ArRH177UjmiQT
WbTIJwaCILO65orcCYSr92eq8yHiuHrrTH5zVrKwBmxygEmp7Of3ZcZ//2wnAUnvJa/eHeAwqWEs
gPNq4r4ybtzcIeEnrNPDq9q2H3VmQBw5Od1imUcXuHFdsPUr3ydHST2boNPgeM/xVQo54rqGggZr
K3vGm6ZiUDRN/F59cFJ//Gcrb2NcxBwI1cZbXd2Fr0uQTrcly9lYE3/RIkbGBXQdYP/AcYitoiL6
RV3euqYK8l8Tn2UNi8Et9tPyQYN5lIuW4Kg6JaQ1jKV2KjhB4Pn2Ja1Zq8yjevbyhLWkdUed70DB
BzlkRADfhNoWS8yAvnCAatVFzIa+FqAX7pIiDZcxIv5xczR3kc4yo30VuDwSyGeEqzwL566tYyrt
ygPs5M+5IbQpJedj1i2+stDCjD0n8zNHovkMJTyiJc3P0cUu6OovlSYbHtKsfHY2qJieQAoUfVuq
5eSXtoSU4satFCAJJnDUp1J+bvHfGV83J82YynEbh12J6QdOBaEmwIpLXv+K13QsjNk8FTKPOOgq
zTurGLcacpBIEKC/bP3ubbBTp7V6dB0aAle9N/sOIOuw/OU5blD/ooygScjL9iRQg2p/Qyrm5C97
9t+ADZB9Mt8lnQr7osraVRtLvxJ1aWWPjsTCJlFsg2WCSxDZOCfUb8UP68K8RoXoUUOCy+61J3ZA
spljTN9vBv7EjycSpbjaf61XzW16p95GcOBc/jzAY5zqnXScABuE5HJfcnHSXygOY8bk7C4fBZUS
m7+EU0Jv99oRSpxh5j4Fm92y5fU64e6+AK9PGtaF77Fi1blf7vMh59x4yVMyrwa1SzWUt4tBq1PT
GDaJBY/k+yQoFaH7UtUWvgfeqhgK6I5/7yicG1qBgIc2j+QzYFtwrLPdxmTz9PxI3NeRd4/0mmHT
koM0PY5xoWPePmgjkbmOZBmjSLo6ivuYROaXdMhkxXLNZPlPojnUN16+kWnco3qiKhj2MXqEuGvX
9PT4ugZo5C4LezemRQUK0iuR74eVegfFiRDfeLUbzJzzLD4VVRAF6Ugsq/SfYq4OJlKX48ggtVza
ABS5cVmefB2BXMugmTa3x8Mpj9vktjq/2b38twVqCPlk3ZAI6ZD3bHI+ga3mxx54qYfX9jwd4frt
I0NkKpVc4Zv2jEx8/9cC1dze5GvZHHWTtXNnM+7FdiFVNQ69CW6AprFIr0wvhw+lp3AP5A6N7nkP
GtyoyT3GJxN2OP5+odhldDxZP6FBdHALHTlFBTlvznEhS514PSjrM/kiHESupH+dmUb+D0pGM6Cx
ETqimvST7maRmlFeEk8SbZz2trOpcCkfbopaVANL3DxTCituCJ4D+tzuivyfWfaOdY39YudOS7mZ
snxy8u8dMonU6RwSsnQ7F99W/yrjnlsbDAbyVACw0+OcmYWkXE8RdvL3Ad1J3LhMm8EbBGXDGjQ8
yA2Cd+WvZY+KrLGcB3tdYWQhm9HrVirBSJsN2za7e5po5SIlm0gzE0+UraBHG+OzbzhmDx8RieVq
v7CKXOUHjqNqSUxilsE91Xnkcio8sJrCyGAaktHd5eimk/16utsEoT8Eq/4ULxn2qx4zofZHzw+v
I6ETANVXRMFO2H4tGWNMwG4W0GOOcqfTNpdF7Ih28ZiE4JSJ0AtFCNuuixeiPN5m6sq0tvztI4b9
8naf3G+fnLPniw+UqDmhCKYfYAl6Ro/e7nGqlldEr8LX6wvvP6E2J1ngyi6zreC7BDc4lmzOytJY
WCLaSZeYrxORfev7b20cBZLYGQq8iBEgOUrg2L9ZS3NntFHDoMbe/AH6Jv44hW24bWdDpmcgLW9L
uknEJcj59SE0aPAst0ulElXsv0m3GGtVn5f09g28XSJnVjU/+PmUc9nF4YKvNzYnO/ZrCbfLPP07
5Crg9K3RqRQ45o63i5r4/Cxkq8170vZr6/cS1SufEqs4yCa+MhLzqRrQQ1IXSSpND2j7E29dLAqZ
6Pz6Dxl5gSHqYPunfDUKVPfxLU5SkTWxqa7oXfWCPBbLwmbC6NoPTL8GkliEN+wnPxpbAX35Ok8I
xdbKhlRbN+JX4R1rl1VwnVVDcVVnMB24K29IODyU4Yub6kXcTn3zMzA4s76UJWkPf+SUbSfGsGbu
AtxyDHhBH9YwHGdxhy7Jaa78NvehsGcp/9hBBUjjLWI34I4nGguZQcWNHY3BtwS/q3reOLcfxl1u
2+JFDSwYzp5c85wgYgcvW670yFeDZGwOsPi098LtK2Fefp7M1V79spKOl96ddD7RW9wikR5aSEtW
usjue4AlayC3ZJhaWrBcnWyzWL7rOPHLiQlJStpL/GS8ip670VYR5yI4DXDUCJNpYC9s7Kg/jBT8
BcM3iKc/eZg+2u/gnrvzeCu4YppNbmzGYljc1bxXEPhDF88X876sH3vrzIxcQM7FEICj1M61cZow
fv3NpS1edaIilnlhhM5tVAzxB4ldfPBHGNAaEKpHC/g4v2+PWVF2iseuzFJtMLGxfa72k4x2U95f
uIFO8mRFV43Gk0QJiMRzgZ6TDcps+rH5BCPJF9tvDRPJQWG257QloFNsfOx6xFgW1gYWfBNsgsY0
e3iv/pLw7Uu+JTq2NSikQ/sBIjG+z0/ma9hMYwbbljNm3YQHNfb7n8mAIZIxMDCYiVuvPVt86+OI
rMN8aSRdIqc9aluf3FXCtqWD9ZyEgaX7NEM3S16YRPwNuSXJ8ph0Y456bnGrc34g830qsfg0pb1c
ysEETJbOuASY7IsqAHvor5vsTaY5U47GLASc2IawDsGpAtcpNSDLY2PQPhEH9FJCynrghMVDkgfr
BBdK1JVbHEx+8bhUpyDjcVczpidi8vxHqwF4JdrP485dG7yl50DfIREExy6OVvnHEa0XFQW2sngv
4yYfObi8sOUQ1oqs90Acj3Uy8+XHX3RhfvMMjZEMLxsENQviuqTEh5tcIC8BMNiLrQZuY93Wpwpn
7O7Ap2JZJL5abgNvZDHGcwPMpzLk4cxFY5s1rQoZtEeCnrk3G/Yl4rmT+aFYPesqH87MYeKQYOD3
uQy55HEZoBvg6831HZEKtd4964ZNn+wIEZtB6DLFk6vN3rJazGE0WTujGHI3k51KzaL5SSGhVJ4c
4d+xNwqGlnCrzvEofuD1wgU+8Ih0tLrb4tWPBQDw4GjhUFWL+3gCsZAWI2j4YKfoJf+zWe9AoZfo
wXjtihSbUx8lX1BZWg9EpRCo2d/QbeIkWQqBVQPXGxmUpuyomxsT9gwZko2qjswDu5BXHR/LW1lj
R58AP8P3+s9V/fa9Z3QgDMJYascnAV0upyv7iX3fqsqZc0P1JyTsl+ssPhQ4u84jrYRlkU0m6B7x
00zgMXUa5vEmclbamGoJ6Bv/XYmIGlHRf+ZWMWdBZdIuSIYUpucQOaelYbREljutLmPYjdEq0qW8
tLI6eI8DZvgScAHE4EZV8CfbozlP6aJqKVVbARRpJyN64rPAPw+q600qJt27A1cQl8XyGs66ocHz
Zuys8+ZvyfjQB3FU8vvFrMfwHQH8v8KltQAlWNTF1ECzMavIx4dcwD6kXRDGShmMKmaIGYYyhGL7
cxUHEouKwSQPgvwTD/gO8anW+HfczQizikJRi4+AczhKuNjnf1CY1Xe35d9AgbhKcQNM+dNi5Dbc
Zjn37geomLNBeVgvtdy+iCICli13HcOXbgeWTUhomdnYCIemXJBvJmprmWcwdtTRl7nduLFV0DcD
E5YLlPuCAtSPPn6foY4pxFmIMR+p6oJ4tIMCtE7lsmvh4xZmvpMuqyBYvE3sjAw+AF64QcOMSOwg
HLqVWQmMyP7I0YaNlemXHhlAN027eDuJnfy2/bcvi80+kwySCxBPL9lsT+v2OF7v/qHTC8dAmXAo
P+PMIE2ttr/NEDmUwuJZQeLWvEwyPtphthtRgIsPPV0nK6AVCbp/m93WPQHNSulZ/mpa2ZEQFRvb
H4ZgrBY6RIGrgIsP9mg44UCLkECN9EuGstxiF/n0eHuHH2EoJryzEdjSG8Ib2ixhWN4IKSmfIwf2
//A6xZPOiJCv4lzjPNMyxXc+0poqreN7IL1HDBHb7shYgQR9HTTKDODpXO4+rG6QwxOU4chioWQh
brQNij5mSRyesxi8KhiyBdRrU0KLI0benEafPZ5WYqc+LPZF4bR533wO7/uzdh+oJtIyhKbxBW8O
b99GHxjWhzaB6UvYMMkU4NJsTUcFaPeSqsll0qzSEB/Xvdu1Mhb750rIWlWM0uVWJW74p+D9SEyh
De8ir2p5sU/TKvTduLxPTJUhCwO5p40rTujf+XFYIVdrOQPz6y1YuOISSTVAkJppM0jDQeYnCUCl
GTp0baXZGM2ypgBU40wuzoyJB3korsS+zjc+O08pUx3cTFFBNnsvUAnANph1N+FgC8gCQBHiU1vB
Jz1hT0HaNQjFL2GtpE46Bj1qXgu2vVQaav/JmM30DW3/1IxuMEa0jTBmc0r/JEw1LhCKdg1bGzSH
a/vNvGe45zqJE0xOiwd33GwQI83BI79Gq/w66XOaxPsA/m5o7BmYHjfgoCu+58yIOxnjLKVMX1E3
QdIlLofl/JVpXxgt+uWHWbEAWKfaSsW+vroLUHwAsDa/IIxEK/XsvgfggF4Vmuisu6F0SACku0uI
XVzeRL3sUXmG/PjiMNMhH5tlla/37b3rX+j+04DdPFp01xSY2ud2FvGAQXnUpbwzt1O/xxmc73y1
wynKb6Vs2vxLGP+cLu7gOHDEEb2pfSw+mBuXzD5O2Ph3TdhMGxR27ledMHlgL5tuOi6mgeABO/KB
UVD0Y0Wlg9XJaxZjJkYlCf/SNhChy2B2mlRmIjrxErjzThJabYuvOzIWwS5NxX19o7Wg5I5DJezy
3vjfrpO4qdGds1vEAirXNZdMeadiwidqu/OOqtEmlhfCjJ1TPqsBnsQ6005drMvfg1ctJPSrQN1w
FbhkKfpCLBNESZ9DGU4Ra3XQ7wPlzBgB7VUV1ANNIAW3IW9xpD3y7jDhV36z2JkDViLOYrprqbei
gO8+NccCu6nJscGGmMgK5cp0MvQ4IBitthwaSYwOpSZqduwZQyMchZPFJDH4x3KHNOm6Y3PZQIKE
KzK3FunmhV6lATEjpZPe/Y1cwdgFW85UNGz8A98J/X3XvS47zXlNADqDjWNug4XoqhX6kuQaSCSC
JcP8sPkdke1HUdeSJC+we+sL6tfxBQVdYcZihmhVnoPbqnByHtEQMtaZ2bOY0YXbkANwCBrgyh/t
IoagwdKA7viDrRfUJ8Gc38BnvffuxZAtO1Hf9zZXkmNt+2wBnv5hEKWhDyLYwMRp3kN1y1W3zJH6
g1b9pC4q3WvA52UtBCg76FMIuKQv+mcfbZeAW3iScb7G7SKp34TY7Pjcf/1mxV0J+FhuICenM729
juVIM47+bTm6Ej4cboQceFZpXB/c8UmrCABu6YWXpi3EikIsxI+ImgjkPyqbhUrogDT/stAWOVS1
6SDeQHO8yJX3he+4WZS2mxHGdqBLIUsv2YkTDh4ugXcM+MDwDq6mz+zeIDv12Js95gHan4rhUnO9
ohf1CST5hV919u8sJ9Th4FGt6cGb6GHOrPNVe9a4w2PczVAcjmAOX2a3+lofU2QodBbKq/dwuy6y
IoE+oWEWLPh7De45wV7KLuoI8rbfC5Dr1ZJ+GFi2z5XbKnluWEtPy+Gyr85f5heQ5xIVzCHsRjsS
pe6CAmyK4h2v08FDm2TVZjt/5bfhCgQUzApWwdcyD8+DecfKSfs0soC04nVWAVdOFZKU721bmVZS
3gt8s4X3rpI+Cevr97j+fbhJqf1jzKSSxIEmKU9gZiB4O2a5n5a4u2r1xTbRoVCLF1wbg5hWso9V
H/iNkuesNISqB9nfQo78NML5GIFm+hkebVa88IFaZ4bS1iMev3UYh2OhFGWkvBB/FNHPOnStRtSa
Plmehouay/MPkxnWwPms0BFR5J5p69Zsz6vnVjY3Fea/teePvgfXPI6eilsNDPNx8ELTDUzIbReo
UyeiOuoIbPrtnBtljYdSjhD36PN4UbCbmmDApa7YzTPn9/7hhGraSapKKvPiJmbGH7aYIlw/DHA5
JPlqG3Tih7QAm8AkQ5Ug4Kdj5t7i7Oa2EnfYUTSFjOUuWcg2F1ripoTIqtCLWuznodEroIAP88J2
6jbiywqyQSw5I0PCc4mzi23FbpD3USZ5dtKGVsdDHEGO2ODMRF1J0DxPYdrWLDSBxQ4tHSrV0+xQ
6ZydLQxDe4s7HWwas/603Y1fk0v/7eicFBJCHd8KPb4I+LWAk2v7Pj8JsUSdqZUD9Ap0Xh+QlDUW
vRyFPjNOWBzsVE+wk0xvNe/hjLVJnDDl0/WfIc/ysUxCe75rEN5Yv4+s9uzgZceoLj0mB8WwjOro
s6GLJzI0AwWzv9HAOiLGisN5vCE66CkwsL/r928gBFNmvCSRpVo1PH7tpfPOGfIy5s6NlVRTIoNK
5wz4y9O8XXy2EDchiR/37/PQWviVfrtY+JaWhi3DLUnJ9KdxdSJvIpa+dh6sMj8rDvz38A3wKXUb
RC1l1YtalHhUAFWda/G2kD/D2GEoJz1YSR9sfpTJ+wDJ8ORgcVl2Ifkr+SCRrViFWoAkHqTj6jdy
D9Th2gAXV7vpYe4MRH+J+9PEveL7i9VlI1GzQsokUQZ3gTipU/j9clg4dryU4trOFzSmSETYu6XR
ApcNWZgDFp5R5QIbLkZ0vaqIRVSMZa6B1vo5IvOCnCo5y21bCAkbnvJLTKd+VtIbF1/nxesiRwWa
6UrOiR0D4giRXk4Majfnf9X4Ao0kvM+NiCX6NmiTNRBrHjZAe034ikeyMfWqo1ITcZ6h/7hgRKSi
zAs5qO6pmRlHBUEpf2dEH5M8nOx5YaV4NY5cLt5ossPnAI0UmFwsoDJp2hvzl6y3GQlDpFgxX7P+
JmkPk/KIqpDN/yii1aN4JZz5kFqRYjT5/gvuMdb8ChhQ4wRNI7WjUIsAVv6kuEFf8+wsmqo9Et38
gXEZz1Rk7rCtSyBfDEcAz32AqgeP8X1ceELDCrkMKivEVBBnh4fe1yaOrrbjzZA2YpFVd+no7B0S
HXkmIdvZKMXdzA/ISTRg0xwK3LZrkbsfNUkqCOwRz5xaopzqgs/zO/RQZ+UQaGENfwOZh2EWxzWX
9iqUMvzX6gl+OZoI69xxd/VZo/EvBPAWX4egiZb4rqjoEgDObXbgWo6b66KXer4+JvAqmIWfIslI
JnN0gmKSuuJohmOOOi0koRWa5/DbWN6u64Rs7PppRGvt5eU9wXlU8QdrRDOXsuSx3kuhJ0Wgw7TG
l1SJfFYtdxl47p/6cH2jiJq1pbx6APkV7cTzXDQGyAsjUqKhgLSg4dt49EYc9+OUCXnC45ReouNV
6Jp5Heyw1jon3Xr2fs7l6Lcr/snBvM/fvhhtyF2W0mpofb02zI8n0UAZfZWFJyuJz7seyR4s1CkR
YaRzbhAdMmL2IBi2uXZzBbNf0DHNqenOxY+JOhZ915Tsj/UFtr/TSF927x2tPh8+WrsNdkYliUFI
ot3biZrxZsyYHUU1dPHdao+c+U+G8Nz/gULmOWN5S1MmkHwVhm0jGSCZMS3WCXhOh+00sITcdKT5
8XNroCRurXNVty1lOyS+XZeevYMFASGJKOeSFQXhByBy6YJFIJUnzOrOr0VT5r88RvDgi0TTRcGG
Sxa8edzKCaPvMXGGgYVgjlXHCO0PMF0xsdhYPyIijQRwd2sZbabUDE+tfyY5i7Rf0Rk4SKN0fPOF
f+dXmTC9imnSPRe3wKYre61Af6/QKdxOuuSHVgpIZn4EYazxzNvDRY1iA2A0MXrbWG5bBwrlBjsQ
SZ+hsFMg1oLLO8lAeEM9vhz8SDfQ19mXyIywymuvwh/CNq5CMedkrmi2Ripew2RE1IGxU9KtmUbY
NR0Vh2S1qK+xwkktIyKqwFT6i8Jr93sBzuhK8jsaMcdPgC/y/6iU53M8xDkxctSfGx0RwTNiSJOR
/NYoftkIaXKp9mbOQNBZhZ7eoqp+H9jsJQ5P66+zG4vNoCi/ZY0KDJScw46jSaM/0JZ6mHgTy+Vd
o0qsWmSREECnzflsY22RB6w9LWLmN3kRMZ89jXDWSqbqV9W05IJTD7G73/j0FEKnn8VkVnEapGKK
IfKQbT8vXz0AhLJC/HIAIIJ+3mKqqdinIZpGwmRG9U+HXijTlCOrAwSkFfUZ2OB567WtHUyx4dIF
GAS5BHim8XwbfblMCZuSmszTlNEf0jNp+qiCdPFTl3H/aT6qRzEQEmd1S9tBBaloCABtFxgVL1JX
3Rul2/nbvIO/8krQBR4RIRwPEM3lqcMWG3eVW1XKx3Iy8ol+8nw0a/+RfVI7lNaiCvu6jprWARyx
AOD2TH/B/MYicwqgRMD5KlPb7U2KTWrudICy16+rtSUuFC5jcHuqCdxg7Xir/HEsBVXK0z74YVVF
XHYczY/US4usXo7qhPNFGuCFI8KApzfqjxcq8p0j2cTrIZRxMsam/Ek0H/iLyUsQLsfB72uv+n2A
W4bfK/RCtr8dj82ycUIOXBcRIpzJb1q7MTToDpJ9BxQ7BfqUJRG6vU7UUWHsqCPr4rCP6uZxm9ED
aCPLq17vhE+z1WZdwNbgTYDjh/YQm3bPuZiU1vb5l4RkoKSMSQGJmazYitTX2DL8IgOt3bbzqXjI
8OH5cmGFnqAf/tOvkJmJ6jvCYNULK3AQ/AOJzMcs4fiHrCiairoX0g5jkfIBshXqhQrYamNDRXeK
jBSsaJIgxZZRwynWtY0GGiYti0qrkqRS9EcR5IO1lKWWEpuE6eumN90GOnoSE8DyuSAM+4mtR7kU
Nd+Y46ylKODD489H01lAPCvEZg+4qE7/p0J4FcRwrs2QJMwGBUjSkgEbgwuiYFfBp+n35dUMXJWZ
tsPFTSJqFYK+4bLFYlTLlqzBP13kBa7Qu2UX9yMGabodPL/A8sgLUSYD7k0tXjBSypmIAqe+RqWG
hUC/frAznTHs/B9cnF6r6A1NVed8YtfJTVO/vaIT9IFJR8XeBXpb65ZTwuvUj/39KON8H+0rYrYI
fBhNTdfWVvaAiM/V248r4r40+Jl24g7ZGTd9HF79TOGcnnYHLXHsNxEeh/penrsk7HLLOXD46S59
46RDbHAA21J4/jhXCTOwp6URKownScwRo8jENMpPjotqbd31IG2bh2KMRgvAMpolITBKqCtzC5tz
bH6DfYn/qHlgPdPBZXzok0KRMN3ud/eVOmr8bHOTVSBFTCAOZ4Qpepf/t6wg+uqY8GbEQxe7EqlL
cw+fyv2Wa/6SCcGNqigeixbkxLB4ceow1qegMpEvf6zLyL2OOnAFJPZovVODTNFC92Yy+UtVpruN
pDHUExoyp/VG4rr3oSysGUisN3hBDvgoqZYOi6XfMh0mWWS/vWyVTo+PrDWIJLQaPPF+m4h99Hm0
3/SHNCMN7DbwTKKrCmbZ9+sA1ccn2WzCOoAl4uZLIvgWXXOzut2qGdoJSv1y27fYT63XpyLpOiqr
/WILEr6v8ziTlwdv+027iPF2Le6XtTMcQ+5DwWcBu893FA1Q0h23j7dhF0VKEVxAXsQbTDzHrKsO
WQvoYK2Srvh0rkn+52gtG2DzcZvtwSpXC4Evqu+k60A5GcoW99pX5nhBmW1kxbgytOAUIVYgbOTB
2pu03Isf4tT22v+tSgA6kn8UReSw+Nah7Bt2MbKPfqdcOGUBLdwPmeJoPehMVjpZ45bWY5TTM3vc
S6usjrEtdz6kc/1q/GfYkJWuGZC7w7HTMopGdFUMjrMZtzcauewu3DKXdLX2cW0RuCkdQZ1Y84+P
YhtWvprmpV+2+AVVjqt9lXm19yJGvVfmPcfArze5KFWE7I2zzyYiqvlZ9CiihFM0zsSyLeRQ2QRt
ivR/B6mz4ALhYNHk/MHLhTNYuTDj+ZpeO/d6SRsTPdMIX3mn3yosPnX1qiCfQXfe5dx4b0UuMim4
6i7Z0iq1mtKeXm+ABugbXsgnBZvjF9hWAW1ehL1sdMnDo3+z72gSrY44t/u9qSerQ3gTrIyacSlx
KX4tcJHB4P4VrTAPTydoHDbAcyKE5uXTIlaOce0tNAy9wDiw0PyyvEjHuZwLS3UFH27UB7ZXDJLU
RJhC6uLoeS+KVCcCm1FYd715ZH11fsc2qBIBBd5meeZhkYWXK/d4SGNQQ7xX7r3sFhA1C7DrNeYn
tlRmu8pah8GDlvsxHubG2N/kvkuDgBphte8qQbrc/suRWqcQZgqsQSS2yXwkNxRERg036K4GdwxB
xZo0Ob1OVaf8eloqWwXRloDuJphp3EKYNUN6ZlH3Oth2LRnXBNvDjhhjz5M3Wya69bIe9AAn4JI3
0yZVgto8TBcOj4V4jSbsgDKenVFRC1l3n6bNXZ9C1tTL3WoTrM/dRnw9bnqUJXArn+DxV/D7BMft
zOT/NkihM8bgndYJQSMTGrYsiJEHVY6owMr5lWc7oXNJYBhomW5G4H2xFJcFOXC53M9R6HbBfq8u
idk1DezdLFxr484tZCj0WSXSzO5EXamXB3QKUlhUtLwXHUINvVUVb5eIZbnfz0rVZdQDBYIUozrE
sZ8CXWZkIubBRrX2huaGsi+zVMpPqPKYGnvnez1pUISYVJp7xkJUgrRBLdCA2z61+uw5akxqHGGz
uMey8u3PatTOX8iVGpH1Vny4FFVZF4By0OePcWeH1Yltsgi3gp/c4AYXQfD71yVY6Ho7MldNzOj4
N1dAGj9wDquJLAfQQq+pKw7xasdChsbTlIgtbnQ75/9fMKWLLCieyTjygD8AWqJoSqft6FNmK+6j
V+oIlgKL+abSVtTTKpF3V9Y4ZHeYUVNQZokyGWr40EeHFpVIrmOtkZbFyu9f1AdlKMVWefEPZjDR
fMHrLXDoLHG5xXpCKZ4SVlrp3btAM3wYF5yw9RLRg+xIAV8hi9nk4cho+G1nOgP4UIhS3s6K2HrM
zByIqYWLZJ93rb0U2fBzSh/qEJE1xu3SUuIwAkeYrlMoa0dabkFMVQI9SGSLcXHP1LjntGSVDKEX
iPyExOEReQaP+UGhrozPe08Uzgqbmi0SkZxG4RJNHn/OTS6PvJUN9AdbecpCRGrBDlB0b/TaqmzG
cPE5MPsRiAYp98PjKCJDyuMbxP2Bq8TGEZ4/KLPamlLYGZ7jY5Hmzvj43fa3kqNBh6Ij9apOP6jw
78wHhimOFAMVCvvMkfRW3nnueWy0ffIaEk9ho9OM+6/IPPB815V+vFc1xEIDaHDTW93HkIr/Aeab
JumsDAe9w3c7t6pki9GZjDZjrhswP3VTT9Z5oqdwbWfaXOSXP8SqrG7/4WFD3zJej7X+q/mo56WD
E6+GRanpnWZbozFLnXVlYYdazz9L2/Em3vE1FkteOj8o0KZkS48cMPDXkcqAGAlGKYqAozCHDyca
CpadN4tT0qGC3UX6VanNxkPatSx0Vq+qF9M2HArBzL01PZ+649y27M96AIiFnRbSrocp/hH6KGc+
cmX75eOg74lDzFu/L/nq38i/6AE7LyvEQ2qjbu2POk/TiZ2NmCoSaXJT6loGJCuHamWeffyafpk+
hSq4FQSM7sib6W83nj5FqnBLDy2Be5B7BuGoA8ZlRZzsYb8fx8/D24NtoCAJFOZbOW/A/RSm7HRt
yFcRaqD63cRjtGi4ZXJDIIzKqO5hkLJjC9OsdhSbWfgPTH3Ilm085w+5MamX8VAdUSGM1/tF2Ghb
cg5fU+FAUfVFByPbARhRZuWsSpoRcIhXCmExV2tp8tFCbYsS9WOQN7LOC8NctmRcD9si58F4c03Z
/jz80jfBgLJ4Es2lMt9vCa2SfSfBE7fNxC+4nEUpSjbWCd8T5m9NOKvNZ1GfDjfhGQpH253sfHxj
+nVEAT2WJ0YVCWHrBNFKcc+/lClf0N5STSYQZd/NrzvAxFi8JKna0URMRul0rdywONzQLJ2NcRhE
pmEUBF6nd6eLnykHxBpE7Eib+2kZSD+p8A7U6qFc5gqku4CLAfCSF3iuElArz+YbfXFqR3TLgY8X
n6ruVKN76Z8ac9g2yP4oOD+C/8a4QLnGWLQdkWgy9gtySHTwH0g8GxTEQEDemIdCR7gG5S1BCAfH
CPS60jj8XZ8JMmHoTmv3QK5wwwDArA1n2MLVSLyZO9Z1EuSB3KvON82cfUnyZADPPhbj9pZDBX0z
3ilRQ/FoTPk8kr0QwpUPRzuHqxkITUHvXkjmJTGKiKfMmI27TI7HMCKoGV+HerRc9GwUrYm6KtY8
tiwJMvZgwH0jSILSGqA/z++fnUt0fK1STrw29Au/39RiJ3vTLD5nCrn6BMQ4vwYOCOZRQvVVD8r4
OB3uaW1b7sToXR3lwh2PhoCGvlz9Gqdi1Q78Rv8uNRNdtjApiU0TSp6nOS94RVfS5yolPQ9bXwQ8
hgKn2HZyXFubpFPw0TMtUSo4h9bMg2b0G0Ws2bVg8nwrfbpWCaoaVGJhe5OvaOSJ/CQU35D0Gp1H
IADL/rwoX3jKR3DsP+gXALC5P4vqImlHGx+DfnBB0CfXb3h/YIjgQAB8FqfUBDHDK0cuxPDjPI03
PFpPboSh9fB0+iudBROvFc6eaM4l5znShhnnyuwcBnfbi8mWPlGcVy8bDuAgtkqHOIqwRCCb6B6R
6b65E0RVYqC6l/rOl9t31YRyNcxZP0huwcX2f6HBeNaxUtXBAaulxpzwRtkF5ItAQU/P819NbLM7
zFSMgbLNTqc244/1zXehc7Kyui/8CpvGYDz0+hrE3xD97fNp5UXPxQf/ihgM7mnEABPZQzQxAG/I
cyudiYESORPkCmdtZbuvCrdvY3ah9uSWrHsdUL9VxtYv9khbEiGebZVBGpZlL+QJ//DBD+TAU1ei
pyXYIY8DyxeH1hQnJR44ci26rKPK4FWQbVtM946wUYo37dtbA1VJ4nW5zjb7pzoHUn4TpJuFBMzc
udhwPodsG/2764AI7OfVu8YlnvftOW2kk23JM7HWa5U2biDusTYm0OOqkqOAm0xCG966521hfh0u
tfJKLMG4U/znhcJT8ZB/qUqj2j2E213i8NPll08dr3jGcmu97RUgf78+CueUVH/kAGw+YTBC1XRR
Av9ofgIurUsSlHscvRSWoyRzBb2R4iBsoo34ev345GvXFqgEWpDjqdMj+mn+Y5M3u0B3OpMmZWfi
v4FrYeAmCgjzT/fyJvawV45SOCrPGOhA0UZLhetNCLnsakI+i4TEKa6dBT4kT1W5nqRPimeEfizA
8ErunXOlB5uPZjO3lrmgejAtBNfe9TPvuDUQX7ICRWN2I5rSzy13X27WN9F8QPIPJwbMIYeuWipv
ztMEucl5ZeCHEeuOUplousqBjMth9d5arnXugRuBJOM/ngIzeWxf0JxWwBxkK6CVjdtkxZD5yYM0
HEpmVoqnTv3Fo8rKFlAHmmAgv99bhzPEPcF03JouhXGG6Py/zVnF+m7cKGb0aSwdbyuv5Gp8onm+
LygxvdWMjkcMfgbmplw5vxIPV4YJhKdWYbZAH1bKk33wQH9pul4GnIlPWk4MtNjYPHtr6HlAfMco
z67B5qYmmdVKQClZb0PTaoLcUB8RlLxOzlWNT+pRwMwfJBGyrJoEtSmYZCBEOJuRQdJnvsWBz7SC
k4a536w7qnHCDhRELKRCk9dXxirakWijKuQNDtzD8K2u8XSPrYnI1fuDdkLyl+u/FAN1QZzUJvcn
vnb61klIgFS2P3IXNvP4YKFdbCL7tVze237qSpAlCSrunoHKUgWAdxVlGVhC4YEzza4bUyYIb6iE
zRLn1Yq9dUc/hpd9EgX7RhKtKMARKAi7djV1rBncBH+ZmP9m8cfSJASKvRgMGQFpBWIL1PFYN0Ur
tzysYcJqWjOIM5umUEh5phtZIs5uHMPl/I5/5QdIdZurWUaHEfwfVgs/R2wEtggY9rN92HraIgOv
EMPBH/t3qEyvnqp1FMA8Q2P57ekdWvxZ6tLSENCauw/8hx7yi4doADiV9BaIVI7V5Q8M1fM8soyd
yU6ruKvOT2Gui5mSD0Pon7ClKVpVzO4p5UyGQA10TpeLvFR89TfdotrtBlTsuTZYC8l6WhywArVV
dwvHzHJdIzjh7tU/HTl8Dn202mMgjOuKkrCHTKc4ENE4YZ+WVXBKQvyPaPRPp13fwHMn4seIc6Ty
1BoThA2R3VhiX/YFy42bJSiRfzXyE+KqexIyUvdA48ROvz3J1816hYEECLW0OZyZXYERyRXB17mq
FP4j5wzIM/42vr4EXATziO779GjGerRwWnL9xrSnMtAmnga8Pk53fDALv0YhNY6QzcfH2qG4CTzR
ZJkUZUBmyEJbaT1TfFZxwKc6JqVZEtxhtIK+a49l7uEEzN2qEZnVKs25RGiHpg3dW+2graKz4BdI
vhoTfgd4ZaxL7j3BeEKgoLeJ1pIetONpAzhLbh4aoISA+yzas1xZnkM8hNwmm5sJVoZ9FYi2J8p/
/0DtBmPK1JX2m55J0xT4RswqfJ4n7D/kbhjIuRYEMuGr8LCp3PeqF9e2bBQuroMYUhVNdXbmaguI
ZRXT96xi042xiCUORqyj41ULYqpkJfZsfzSYJhhc1UubnlsC/0c8muOJq4ML9eXQwyx5nWU7NJr2
4rvKtgEFzi2SxZlV2wOp9xDsxAOOZ2E3FYurep4JeLnf4FjDbEjnL1uQ4ncEmWzE0gqt2kXFIZrt
X1ZFgHt1Z/QlhD1r4OIjEX5IkRoXqspeYvNqm8Tz6rLtawaCoq6Ui72rPJ4tcvbfTrpt20MDwio/
H53+P6EhCTbwljeLIfyYl1D6rg8CGLOLmOETy2WkU+Hpk0e8ucAECZDbX1OrfaGBvJlaIjlBTjrW
dpDeOtdJw3TpKO8kbHnWcfi8WZ7k9K3FWEhXnlAfLuBbmAW7maJjuk/aBw6tMNC6kL5S+jnroMbP
NlDINAp2Wbr+HBpHFjY0hy5HMHy2iNExjrGhc8Avsu11VDYg8yquu0hNo6rYhFsRzitLz+0gnqFA
poMmk73zB6iL/9pawLduRiSWhaJyNHEWlN3c6fCCcqsfcHeS6tErbnbf3BlkBUPkTbboyid6CNGa
fMvb3kl3sfqFSYI+rryUvWRh6MjGDbj7M6pNaQjwY2EoRnvWX1GWzrLn5FHJsaqANkz8fKfH+x/h
+ozSaeZKPE/4zluJXtRztlWx26i1V8Z7YGHNF9RDJabU6l50PF1GpPQ/z3aVqfHmw6x8popeiCJe
RXZO5hXx8i/hX9zhpogr334GFB35TihPBf6cbwyPFTbEpVRiZezi6RknReXiXpbe4gRD6LaomZIc
p3XOuzFGLBRXaAoHm53v+hNWDTQO0b6lv4gBNWDRZAs1ed8zKfvLHY/y9yHmIpUC1kSNMeiYmJ3F
Ft5SOOqiFPCSwlvYplO9izREDNO5yMHI5nMFzgDf47WpRVtMvATOy2u1gfDRrOst7ZcDGjTc7zNl
WF1WI7UZPxts5svdy3TOfVB8Ywb/BRdUHbTMlOUHrFJc97Xwlz4FITQOC//k1LpEtRqJmIzE8rSR
mbT1MhLV2y5jh8o9frQKmN+60hDtlR1wNG1zoFSkIxH4u0bdKlV1DYIbA8ka4s2zmf02XLYfxOuz
5ijLrd6DGiv5jotzvrHFfksB4F2sE9XaJ5PmTdyCtRNAO4sjV9uZpN/dEmFitS8p0PGimsRTH5u/
6hXYglXY4h1rA+9Bw+X1/pmV5snxau4CJqFzByWvq8mM/p5p5Fmx6P+MAdCtGJWNJIR6WhqFZBj9
Q8CBL1DYF1+rvEFjJ7KKoG3Q9KZEvQf5l36UYfXkogzVVy5E5Fg4Dz+oW+Y/JmvqFhq7ZiWHMfqg
h8U7wtBA7lLEaLgx8dBa5tYUxF8i9VhIrhjgOL5YhPoQAoPI3Gj47GRLGhjx7X7PCvgnrEo18xUf
ifGspGxb4mk6KfsQrnUQcNuf/7P7mV4PrT+6AnltIJKZMJj9s/3S/hGmHo0PJ8U0GGHLBvlRJ+SZ
Jv3GoG8IkLsD4Iu9t3Kq+gueOYR6B0z7WTQmjh9aLtf5ssnWlgONlwrdnOGuGRiggf7p9COJbLvs
Kb3bG9If/e5aqWYYS7SdMwENPyXeDl3Ps/hZvA6O8ijo6t73/EeD3TBkypwfexGxj6fNWtQ3h5B+
Mz8EqcgkuxVjNX605p0qhhvQLHYvLHm4THI021Y+t1ist0ZlB9rm9TEzrxnM6d5RQAReLG0yFG7g
iGKIMVO1mzt6If9hTTJKSM6M8w+9UOLe1+aLUXD3bnXB6X0hzxOljAx6y1aoWFCWpfSAJBLN9FID
qBoSjwD/sgUzbvbuLQxErwz8wIspQLiNmvTXmzAUTgjKg5na0oOWOFo3lcrFx2Z8mOtzxEBRRO2s
yVa7drPqEUpydIr5kVU1TUgBEM1br5cnVdrHfwe3tUvXT/9KVqopwF94O1WHM1HZ7aVuoJdZvnsV
xGXGRhuAiL1YQNyqQkZeqhzh33eCDOFIGQc3yc9tyPQY5TK7Llf4y05L9IL9BNNCG16l5XYyx0Mq
5Hl3eEbq1NNtc0rJAp12rvQphvcUPCEN9lLSezi8SJ7qafEbFLnjcymgJCo2i4cgpFfPuuUHFsKG
BOq39ZYj51T9LnDDSwqcpanQYvcWUc9p4PQdsrZYGgWj9zNKLXqOeSZWQ1fvfoEwE+Ol4fPEFu4a
qbk0X2K185dqGl9VAzT5jIF9cSOUqyeGVgEr1YirM3qZoTUww5QdAYfHr6lTm1Xg8PmPgMrHYx5p
NKQ7TiI8pgHnMXqHJJAgVIAcZuFDuFSTw3DiMC+/cF4qG7uXQiqRsc5e3w1Tw0N4XmOWcq3pjE9/
AlGNdFTf3PWAld4ocfezqUmNbWW6DQyS/u13DEup6766vsdBP0D4a6Qb6yioilZeOqWIsDRPPAoW
GX/2mIpkR3BxfqrUcmkAUGIc9DPGK5zQ0EtTtNbxDnP5t1z9O5p1dy1nqF0/JBRHoPxmoKFfyuNM
ZP986K9mmFMpErko41k5YbiOOsCBlIgss9BleMJr+6Mk8b6YCXAtT0cbDD5QfkeQQrhrSUkkHILM
wSWKzcBGfKsRyu3Yxm9+rwwts0j+oIy/KzUoUKxF/de7Jz1YfvZzYBahK6VJMEm6Mj/jcW3Em2Z7
Xf11PgVY2I5hwg2V9oB8bEkxknYSsWGpJVxz/C/JWq+W9mu40dzGjSnW3frFNO6nvnF5uBzl07bF
uV8dyaFGEe+6KZGjk7gMuivjZsLSQqTsLY3m71Vy2y41ZBPrL6sk7j9kpmreyMhQv3klIz8jKOPH
MAuJmPE7U4FH8Uc8NAN0RSSTuTxdw0K2IYvEWkEYRm+4jiZ/bU0tUHn3J5b9sH1KMlIM/xhwtipt
YpoISO3GU+lKUnbvTrVPOYSSd7pbZBUZvMMX/3no1J0zBqMC5aNE6J4xOphl7afTlBoPLUg6lrFT
+GSesWDfxrPrFvRZz/BdqPSawEgfaZF+OIpf0yxjbxR7Z0f965QKvE/1GEFOP2GKvwazVlZUzyKK
YNJgsoQj4XWxCqw8Hi+tH2nZ7M+/bfdVscFEX9/NBvo2SlxyXlpONBf8CKFLtUpkd1ql23KQdGFM
qCa30frnc6jm9d/t2Y3uEkjxabnKY6KwE6DR99T4nYfGpt/zQT/pce+mwdkSbqVSXB1X04FKm+2V
9jGQexFOWHbhJL9qKCMTw6p1XKAfVeBtf1NjOt5buhr8g2QZbnmTSz1P1xBtTFTfBdhwBno1TttF
lohy918P9LFukBiCWZnpB0mysKwihnlZj/edBHNN7Jfa+hQVLg6LCziCW4lPz6401blL3cWyfe3G
p9MVZ9JXFXA7XXJTnDGTAMgfjnliOthvsGiWZFKFr2GG+Wtw6u0AYA4sDxV78fzlEKtO94LRl0Q9
nlQs1Bo4PqE+seV4PuWss7aUkizOqasyMVKdlUVDPG5DDkGsay5voWQD3ktyUC3WCA3n+a5hWS8K
eYEMA8z8/8Fx65B67Xv7I9OOlGKAQovoP+VFuL8+ak4AdPJpigNcg3NgFncrebC0+w0ZRnWGQaVe
9rhNIBVwr3CsWxj9ODith66QQnITj5sG07qayEE735i1PohftYggVmAYBDjcs8kixQIusivGNWKI
04CC4X0OKF+ubt1XpFrAXE6o0JSeFwe1wQ01jI7HxXxRECzFUHiXjsN8Kd3mdzGyxNCLoA9A6Ilk
8HvM3Oc1qR/d9ZzWCA3m49vLBWkJ+zXk8DgrAjWQBzcNuZco3+57Acdd6M6aqVt6YjmWTtUvFKFc
Uv97y3oLLPzbHmcV/piORTwXRYJ1KtYf3aV53CI0dcRzS0ZGqIvb4R8lP75naPgTAk/TgSTk/T3f
5S7Mom+z+U8gL/JH6/MJFuQcgK/Jbf2EOgP94khH3z3iiESylOx4Xekvg7gI+InjDpXEAqDSf2Fs
RPpmWxKAiuZRwQmFBBjonbW98BZ/QVGoc/IrVPtO5Ge5LarVvFm26UgQZkOwY50hivU8K4OtO9hb
Kf37cc6Xsk8SIXibrbjM8dmccIJKswoSTCcrYS1+vO1rSrmTrxvOrk4aiODuf5wH/LVuxHYfq5/Z
fQJWA+4vFuzLk6WVVc1Mb03k577Tpdr2CSzTOpIPLKR3R2EPTT2Hjx06WUD8uLoBxvds84PHG6ZH
f3csHJdAKVeRtEPIviHXFu7CL9SLuWEwYNBTY0afBxspmGKQ/XJz2Hmoq5mLzj0HT6G4e5RuyUMt
SmRKQJGCtjWLMVR33Rbckcs3dAeb3iHGYDd3O3uM4zmNIZp3fsh/ypw0NmThjVRKWsRtrDsgJeMD
Jh3U0dYMQ8e8FZlNZeUVfHs5fn8oYU5558jM2tEm4T4fCdZ02xQSUgWRgvoEFqDMKUvjqfXuf8+O
6aZXKUmMG/G/kuKUb9cQFsdekwwxACN+eXl0qHbVsMmIv4FD4zwxLOOKrO7VkFTIPqPyXdDimOzX
q++IGmyKz5vCazKk8DEu357DhR0IfLnDp2Xmfz62J3F/Vw46eiYhYuwOo+bAI570fxG10g1x/wwZ
r6tN4y50/e9BoyBPGUMA3TgqNqy41rKup0lsKzI2gdFFEqX1wKblyiWXGu/P/gPMBoUuEZ6U22q3
i+r6H5NsnKDgOKjJTs5I5x79oV6lxXzn2ijzUA1bXbt8TPoVgQmR7ItmG2ebkxznuvNqQgeWm15J
9DUghP37jPS3km8e67G8zFrFDBoXIs2knKs6a/LWYA6M7YpElt8D/DsJ6QDO6pwjNsTx3dMC23jC
YgHgbZGKtwmyV3WGay5MPBwY+agQkrP58/12pN1RD4FV9qyz+N+ZiRoRxABFUpx96x+gBojEu2Tw
ArDglfcYiwbeeE3V/XQc7Ibu65w+LttKIlSH2TddMoHXXsmveC7lQiH612V2Wx8qPtBVyruJK0RC
dtE37M+L7H7FNsi4hEMKAhx0bAibUmbcS3T8Kk2Nbm2i8lruxQlU5/d1dhWrWSx3Qz2+9glKhF2j
vdNquTnE8GxOQpaaksLrKW6Hb9WuKxvcA0+lsHxKhDBjoranMTW0s24F7LqPquGZ9+QVsvXH6/DS
9YZO6bp34l1dvfCVJPi/XHAMciK4V+w3/VCZeUq1NlQaPqjfaoVZAUYriBkl5rnS/302i+0OGOQs
Ve+p5lsj1SCTlVmgj9dp1sHwanQUv5sUey2wlH2hou55+FuXrxCABiyCLzsuxsB/ArlLbwUTxxJX
ILwz2qzqY1l32uaLzIaEyfKktKZyBaBeJ2ELjhvHtYvL0oL9afMq5LnVBhpHH1drKMkz+1E6HBx7
RAZdGJbunT+2OgPQA63QlsGwyZz7mHC5lHdzwoXdTC8zZVxdRHRLiTLqt5wgcjVBCAXf98hbtZE3
M6dVvgg36ammmVypMzLmeiOb83OgMzUZfwxsw4sTbtLe7FNH5dsVmPrpBpTnYC1qqeKIyli5kn/2
OQZnrPrtloGB7GobN78X2Pw1sdP0VzxUiqxiQjcMK1knickAMSZbRl0TuDCPp9G7L2fEvH2Jx93E
Yis/vXzou3HlmlPOLJo/+2nsExI+Z/6JPZ6Sr4i73B1YHdYU2C/NO0LH6xTSOElWMN+N3PcdUeZs
JzhFnlWla40veYUN5T7WILvYKrHR1RmpieZi2TJyxFT+AiX9pVQgblZ0wECbpY9F7oqb0TN8tQ8C
NIRhcPlnVrzylERS1TraydOTUeTQvkIyVcc2xejKYLWaAMdGoEEP0nIbN/fYOXvQ2jbMCO30brIS
AU5OZj36xwMvEI1yZI7pbRePwlod1X7MO7G4N/CAbMJBjJs+wrTITe/1RX+AoVMPRAXGrJ7NoZ6Y
mFBXhKn6s8pELSjluw0FDBJk0ko/osAlSl61+jp6Qm1GQYvbpm5b6BjQsJDYvCjJPHMSTPgsX7F3
bx8ySMTTKsyAeR6BFkFWWSkJgssWieRlkNK8Ryfblc4zI+PvuJt2Lx81VK5qtOc1I4Rs6GZ5ig6g
GGC6y4SWm9m/784HxnVfHUUoJBAYtdxphtcgldMAZ6BlWnKA0vi50+xWMzzSX3jpLjl5a1JIYsol
elfOdB8LG3nhIbi/6QiLGN3+7+t74UKPSqh8bF46hjBmd5UrUIjRnSdE632WLqgIHpxUGpkQ1QJL
1sUynHcKBNed6kQRWkjq2/pc+mQJZXtRWMUngQMpTtJeVqxP799fW+RduF9NlYPPdJg1QJXv2oj0
pABIxcALXnlB2hNWslwKuXCsPkWH4R6x54L89hUC0+bE0XXk7FXT4BeED9oP2lukUW49ijwuWSxW
nbIyPHUpJVmQC0usss3FLn/tEnj+0aauxYzoujgs3wU4xP6HIYwaWZOo9Z/rZMnbdCAcY0NApJJm
3ThqsKpI5SOiIWfNJQ1CTfTDnPIrihej/N7Gm2ZGKjuVq1f5JS5kdlZcbIv6BHD0auF+qFF2aaOa
uUxKJ0zioryk5DGsY2BXi31C4lREcAqfaVIuLN5PQlOvj9W24culGboiEV6dCuE2NpqLGzX8R/M5
4bXY/6e9yYSODORi89QZAa7gTff/uj23IGYP8tj/Lccji77EAn+5hJEW2YO5WY9Ga1qS4E+L0zb1
7L8ipBfGFuw3TjzhpR0hAbd0NAf7/oCLCXhRN0pDY2vEd18DiZkM8Y76J0ZK3KPNOH8tUf/imE0Q
TVIqr6yPYKC1wvjxSfDMOhj2P8q262VL3dFtPjrVVU0KxJZKG4C2dG/wKPS8Atq++NkEQeEvkJKn
2VZ6h9pg4Avwrn4llHUMkPn45Rq3acLspi2JVYxA4kYOADcixyrAjNGTUitD20s8Gf1TcP0syusw
OQ8nrwsfSbJVMpzkmayKA9OG8Z5jurfStelz4w+H5mDhUaGtFkOvQvGsY58UgRBGK7pX9ocWSnoJ
plqliWvinAIBumrgWJ98LU3MSjuitvnq3mgahrftZNF2+ycwLduH0j6KOd++N3Y+WQ32PSwlhxSJ
WYlipb+8B+ZkMYTY3xMdrSlR5AdeH+eu1m25JhtS0GbHGltZnvBn0UG7ary5dT591kPZ17NXeo/n
yQPUAib719pXRiruoASKVI/Wv/5QeIOvoCFPfhBQw3kFBzcJht4Am4I5D+gfMK/6kc0uLSddUvu5
/bx5qZAVHnVZMVlhVNGX2HeuPtqhd3CZSVI4v72ck8+r/oQpvu4wdKA+xDyvZ2nAmU746lL2ZXY6
YMtPtu7riqqKqPIgNhNGa3YZ61F/OokLdm8pJWPHCGHj9P8uB3QeWbPZCJKyt/zqRd7bRhqdODlL
crfVV6kLEP6D6rWZ6jcNI9soQmBUokyaQQfEEpw745+4IrnYvIGwbT5whtdvaoeg9pM3xhvMnuBi
k94xWW+D+gM98mERYDnqG1a3RFF0kabZmUQMre4lheiqfMzXQtemYBTNSxVO/1sNXJXpvXWKNzzY
xztaizvTSp6PJrjXx6uj3JTtaZkZtdiDdotLXjD6ndhRBi5V27Xa+ySN8xAUvdQ8AAWvCgnJ1z0B
wqcLhT68J91qUZsSY6oSTn/GVwgdSl+XDBUf+d6p8zIhMtw4/p8pDuPE3TuuK++1pBvUWXRaPKkB
vjk45PTP0l7GTd7+T0RFPInCIb7CY3p/5FI9iWqmeSLmI3bRgK2lF8HW+cy3HbXcQK4cGQuFg5T3
1OBD44pUFCQO9nT5CklIJJRVNCt3yXlrWy5nWHnwZx160o+k5XKT5mEPyqMwHAPtm+Z229Tup/EP
4ZtUW3Avxjq5LIdNEOJnNgfrXkkyTHHJaRgVPPnmd67rGmGhhKNbMLkbyHRNtOF1NNUS4E3VZBTh
R3WULZY63oedPIU8fycl/kDuBPlV0DM2L8YWpqINKhNX/YKMTXgm1AhSlQ8+8zn5jY3fsyYLctEn
EgHIopYItI1e306W2dECDWxX9aQA6YkQSHeklHky+8JflWOcd+Sf51aiip2GE+Nqa1tn540LRXLb
MNHlJx0hHckzTSurtc+ZT8xLcJNa34A+lqzA2wfGl7aQbx72wMQ+wRh97+SVeCoEiBIcKwIS4eh2
HJhWdXK4KONsd2dSmVtG9YWFX3UVTQDOvrZ8C87J0/hetptk2liFSFPsbmp/T1GSlNGspwFC8HAO
inW9JpKGQ+ntiWs8XbDkfGfSZnUIKABOFe7kBKr1tHQ8hQxNIFpVWVTfZV3fnIvYizLmUwd0cGL3
3H26vKAQ3/f12jzNSyEVUZp2Vw/MVbFxL+r3wUtF3UvkQW/7oPsL/UUtp/I8URQElsvkhdrMLQH+
728c97nzWcBm80xBRPNLbnxKrcPeeiYC/KjrCwznwIH8U6ZvGjDlXdV21st4bmwE+RfScx8kLZCI
bzafV4kdvWsZL/9n2YvvDVW4D1NNiEp/9aKSCD6rHvD7l0K4J9SIuFfHq3cbykWhLhPV4uGJYt8A
mumPFXyDF+j6o2R3cUfrYq7gidduCh/f7TmV2tO0/m4x+77yxg+uIEV46hChZG3UZybxK2oPXNah
rPFX1wShkNaYf5qu6M4n6iibg4+52EPRl3Af9XeY0ito8eS6FtqBu2D3lHgPc2pTE4YAxpo1D1Xq
5tGtpnh0dtISMZpwyRq4WC/ozGFIchLodcyfNIgIXPOyeYA2TQU5EMvBgmj5r4lLjwNHqI3cgrby
8H90fLJCRBieaqHz6+Cb3uCZfnAW77CHvMNoZSNm+Bc6ApuqKngZLGVmn8UOZf+5QEM+DM6N3/t/
igHyYo57gdsRETR8VBt5dFTGcNf6jbBtoMVWARUjqjBGgrmI1fpCv7iIdZUGVVevBnYIl96xFfjE
fXgrjDdFUksO0JEz1pw1Lx88Zm87vZ9w1ZkptMBhDqZzCBURVShvBC7yxCSS07XMNNz1K2YzC5vd
yTZvABq9Qm/gGdYIjwTInZ+SWlZEa2aDEbQQTlF55bR3kCcOlO5vL+m8UK0h+AJIG0cHHCQNBww6
TjJ5KwJupJh66zbOtUvDiKzUHqMLy+VzBJ+Hk8Nm8cdD74m+21kUJ2Eebmym8NyqXFP9h2muOpll
g9UVJLvbBXBeJR/T83rraVXwBIYh5p9GjqS/oFaCID9WW9mgsy/GCxx3Q2smdBZmrUnaQEzHEMDl
HQJKDDFuMrIBLEDcXLRT1ntaEKDCn+Zy6+218z6uKVXrrqYki24CvQ+aE9Dsq3P8NnrFhVnlAnQ/
Tj/+5ku0vA7dWBsaf4Uay9+mVdkbIUfdH0cnKJcC7+wykfr56GmRn94mz8H3+AicCgz2FKpLiYWk
VeflzsCVPXgBE5xvNDEde1kBAuk71MyerlhaLIDIq3bpvBmi+1e4c1gIARieYW9UDKMbhTqeHKhR
A/Z63/i926YC5uZQn5qFWYl3sXmXTVCiVGUB/PzIUwaK9bCVgiCowLsYFvyHIeNgRKvEc8+ZpavT
rTgdqbj8rCXvd+fyCB8GY8sTjDvt3Q5awbZSiIh36eDlpndMmm8FxBwIqCcc9havF3sgG9yF0fSX
R/dkfflezZ8VDgDpGuQdbfFOAJ8prwgjLHEL1g/3mbF/kCulVuliDTZF4W87IXoL9wZoAKGREWXl
JAuwA8RVnRfysO/YBauR1d8FSNtE8jVmE5u/oXqx92irz+tOPsJG9JAC0C7L3FRArDKHwblg/YmP
ksbpj8En3yiRSFOvXLHKb8ybX5wykOH7I9tnDUr7ASVKcCOdrwsLh96RVH0Y9aN2QR/kBrOuDLKk
MsqerMcqNr4cgVRcs+5fW9KZq5js5T0bPhWUoZ63J+SiJavVN22F9D7nobhg4Lpygk399td7iuFN
qy1N22UEIY4S4dJnEesoHGpzhg2U0NsJX9CRNJRp9a5i+hYDeDRBDFKujFHryoa6L/5++PWc1FwU
rbyZacsfcbzjj9v7DlDFXo3ExJA+ItrVfvAlJl2S6D68mP7066ICVLJXvUUu//OEGw7zFR4qe989
vdzjAD+Y0k7cqtYXuR9Lwmrh8BjAhQTwUa0O5cCgzTEUU2+Yq7TRxRYZALGSgc84Rj3czVNsLzzI
oM6ivnnHUNcd2UG6+BzuSvvavPHMrQH+TdCRFQfUFPiK7R/gHLZ/7gH0W7ncNGIsTwJ2H64pghwD
tQUaX3eI2hZH3n6Zcd2IqUDV4aKUHMEoFvbP/sN4z04z/Xh1pWX+we4R1fT7O2NAs8c5sht+rwKf
up3uLBpVaj2HNJTJOd6HcJl/jNO3bflPx38DbfTAATqPR5sJ17JXjgjfkJr8YTztkn3oEqvouZ7b
FWdN4KUS65367zxafy2usmBjFptXXDgDHoImwkurNASeL2KBjwRz0uV7H+HeR0y/DGVfW4vHKp31
jQxvEBha3Np49eM/X8WYhsdQPPttqQG/0suH1h6xdLcW934I3AEMxIs2tZoA9Vfvj9hp9Q4C1JJK
aWFXrGS5mmZbllt5xP9t3GKioWvZY7J7FNqrsTze/DREHdSd51ZyDt1lJlwXFUm/bkbCeH6tARyA
IDSQH/o8l/ZeB3gCA17v5D2d27whlj3g1dUn621hP2sw/PpBuV6HafzQDvh6MuPHNm9UCMhTDvbN
d715GaYBwGEeXxS+SiYKVycM0TTlcYaAZgAsL7Wm1t3upnvqSaMNFCWY3SiknYMgiSQFMW8/Bxhr
x/JOWe/LpjUeqf/UBaWX/fauZnqwapnrvNZASV5OgXiR72HAcJMkhWbQshsviVBil72M3LmWiWxa
U7CSqpvhYCParRoolrvv46PjC3G1xmCPj6y7P8LG9RS61ojDiCDjTYmwPtLZeCp8hwDb/Bi/HRnk
GP92ESoIiyg0AS2CmPUK3cDZMz0MDpMfF5Qa6IlqgTU6UDoBAKpPm7l/2pw33p7VEQHEvXLhlRl3
wO0eDAqmF2eISZk1p813aO7gmu9Dyn0im9X4hALYDH/OfFHXpEa7AskU2Alt9QMdC8R8H0rVvJD6
kMnyeWithJhUskveoEatDkIwE+73F73g0koKeibbA6lJJnr6AZiDNbKd95E8VFmtyjF41x5q9D7Q
y05XONofZ+ppdBqYnCupr4g3d8vM05+LDDf4TikL2W4StRgte5tYWZWA+YMjyvXYGtYNJFMtnqiW
SHRpIVh29QPmem+6BE/V6QQCujlg2vzwHqArOXmJIRPjYYivc60Om5VZv3litwggQnUZrGiliC9P
C+KIm4n8rHP4B5lFhLd1MSwFoCcvfRM3fCBnMsfflM0ragSfmahChDxQZx0kGT45W9za6yGHjjzg
7Qp0JktmH1S21lGpAjSVAo9uKMFImnXrZpj1C6tmWNkl2Pe3jOH9h+EMhCJRf6dApACQIFS0aOXC
l1uRgwjKCZR2oixJL49gXGI5DWiAuBvB6iYGQYQoO8xybCX7TNcY6rNLxCZK8DJpQL9Ci0Bd956G
1VawhVzbUA9f0qynH5rEHo5xDIP7eGZl9vpMKRfwEMa8t00upQ83ZBmFpWtwN90qKaKaN2Zxt7i7
SYDKBNWvoem0BMsodvQj9OtCot3iDQu+sLB9xpI3p8DJJmGIBE9ieLMHcj/2kWcoIhxxaqoCTWzS
7sCUMvgXj0NjVVIcB7tVlEmJWVGLQz13hR4utSaA3Fz/sar7XPUakO6wB3QiNtH05I/5jc9O1Mvf
LA5nTpfsd9k3T1v/ZNtJWl27gqtAqsqlwudr9NmtjlHGTCg3iUIqZj6md//uOpFAmyXqv5Nxre/I
bUf+jWxDS+iJJLtmcbsJ1sLa1FloDdc0NPO9jBGl74HNJYMtZe0jf8LPLEuirUxr1p0H8wSYGh/R
vB+C7FYb1wALWjt+6ixN5yTiN6wuQydQHJWv6Twioq9743VuFGPzxWZXpJk57izjn20+Yr0o8wJ0
mBLh6SKmuqCMjj0QgHDpzYdJWJsWwHyHyFFIaux5uxxWA7T8C3zmR0eS4nOGB/mHAwdPFEJ7xidP
nGMCEt8Wg9eRp6WdGkEcRMFin7xKU93mXD4kDL620aN/2JKAgLAPyNojCcUB6fFNX8cAVCTQQ5Qh
00s9bpzndfzrQqPWqtqtaEZu+cFyPDjo39Grxq9eGS1YcggR1U2MAQRq2VJzohMk9kEbBbNBapXo
aVqIQ0YGATK22BxhjVDjWZ9YJBeExMVCUvT3vClcHtYIwkWssyOc/H3TNh6Jbcoi9x/9SOROLi0G
2yfKAVNnJqxyCygQ+WWWZdh4rs5bPuDR54V3+zxpFv+HpqoMtxJLDLMOhu38ZBNnzInVayCwNLNR
Pl+X0+KEVQPa3Y5OoF/s2i0zZDQn3lKywq3tf2GpuINZT+aZf35qbLkq9VUjZSqYowNshat1cU12
egog1JYT9AjMjPyuQE2kQUNPP88jTmSpmPE4Q0Vcbo+UlUSM6VoGxt44ZgQJd8/c5sPkH3ivthJu
N/ixav/4EkGdyQPJmGJ5GD+0zHjH10cdSC4siVv34jD9gKBtghIjFl7+QgHgKcQk2/nDm7/7AZAm
DC/dGP3gGhD34ubb1E/AhhJREEucGHGz2I+l8Ku9qvMUPfEZZ/goP22U2qRFVMz+U7ciiHNZjh9A
/+p6u1BdbTr5Fo0AEk7TAM/ms23WrfA7L+29dtwSHHP1F59hv1+1m3jAikUeiLzcm0PBjY/RpdbI
rT6FVuJl6Q6SUu5V77ksqn3Vi11rhEmUHQnPylGMo+xx6bYQWmIIPyfeZKDzFyyR5zql4q29MARy
ydAVEtiiPFOVX6pdFecToB0gKi1IqG0qLjnx4qjgiZD8I+8FMsYY6anX5BbsuNFJG/NJKNw5ca+O
5ayaWZFOCLtnt0rYVHLh36Gj50597aDWIpj/2Qk4DsbaBFJTvOrmrHtgq6GodWswxrlgUC91Qp7i
AG/jf4b8ecfVYLBzck9+yKrB0EVMA6CbrMielSVnyrDIS2MOgIlsEFGijFEkYM2hkZ37squYgPap
mq00abXQavxPDjIUSqQr0dUm20LrBpShqFu7m0RARmQH37eMyVs9sNSeoTZHVljU+AnH6NQA3pFG
FhJHIyiNstCOfKg3bX0KD+Vi/kOTJfDe8McEVyx05iZwGWq3/BqPxww1FR3ETE6KP6PehNK13k2F
I5tG2Tcxa31+UdHvVnr6pqFl2sXxvZfh6DBPKHFFFL/3GUh5i4tAx8tdPRQhwVcESDwqjgsLVjkN
sYgLnUSAzMoR6NwzaYIZS5//qiYMNw/fzBQL34C64jHT2qTz1F3m1h4mRCu27dqj7T+TH/kqnbZc
VgNurF2LuiFzgVr9MYw3l1xCGPIu5zKVhOrhMbuF5HeNF0qXn4h+u9wlEZTobM3qQCRZp4cN4zvz
zGNTn3G/AqzdpyGocyHgzatZxcocTY+N2+sgM/Ner8xn7+B/WhrOqTkzjjLZNY4jtraE0fwesp6d
Nyo56ulhSXylEhvhhaaa2IMCJdSazX7vbQbCU1Sjwg+LtQFFEHUpgw2GaVOIM4p5y5lZq04c3xpv
lPf7gngToUzatU/D2Bn417Bli2RkUSzc+JV2zwVeJ0M3Ry4xdv2Wuoagx2/Fn//DCgrteBatWZJ+
2wYxt3Wrcv5xFkLGIX55i88oO+2TXKxgP7iezOA/39ftrfyHgn/a8E1eyVsflXr8S6/57j/t8LWf
M4ilAB839wRUtDidC1+uM9SwaLPOsPam9UoV6XaHs9a5wpEC0tlT6qX90DHzz4P4ZaVnycVEjgl6
szNRYE2S41A0kBbJ3DvQFmLXFeRB0Cs4yLsCG0MYfCcjNxUxVBBqBhinzGM0Zj5OFYceSzyXR2at
1mP33rTc5Ssv2djaNu9ZCWJWcuwKzqYZ+niNhhKYUtApTXHCtLwWSNJLiuekj2ZidOftBXkrRFFu
kPaLScOqHQgT7PjZ8InaaIFvF8nwzkJC0Glv7TdP3oSE9167Oir3sTrh6h+JtTyxvV5yFgDimwlY
1Qo/Hvs+IDA/QFlVNWlW9xRFcaz3KmmvNKMV2tfeye15E6C9Z4NSFykZb63ksgUVZ+P0L7QwRVBu
2+R3RSkt/J+WG/5Yx7bAgcYu8s5xCanGKpAfBR6jrJ1mBDgdqqvKhQq7brDFLYkYfA7lk1EvlKFg
K0wy7BsxO9XX8TmVoVh54TwFPRmAPKzRdLXAtY9yYU4P5c1shmrYvv6uF/4I878XN9mI7HND8z7s
gYP4anY5lnb4+JxRHqSjyCrnzZ1Thdaol4VYUuL+YWWLQ23X6Ywa8sj3erTkVS0glb6iSLc3oUpx
Go/ZYKtgVBuyranLEs/hCRmjUHhJTLVSOZL659aiuHrXNOJJQW7s97CfcGI2QUHVkp1V+fe8Btgk
EZs03XpCi923mjFfQNYeysBhSMVEeeZts0IuRX+NO/7P92V2aK2t2blDsdS81ImBR9EV0RK9NF7F
5f6tyQdS1etCVoM1Ru5T8vFNt07hpxMDBAuPs/CPRO/vjWQZkFn9P1ZtFCOVSudWvTGlz0MjSLZn
mgrNFywXEzd97uIfMbM3cRvPsWPA0SzJRwpKhQFD5yXJiiTSYn8tSVM9miwQKdi6NTp0x2S/3Zwb
qaFemZRC/qLfRLWQzHeIsK4JRXyjrMbQMTuEH3EKfr3HnR/1HEntjo6QXkIQhXDRQqXagcR4Hgjt
FWBJ4tKMm85ofrLP5ElZFHSw2IV5of/bfmIOVqRp6ZFwgobCFJI0cV2LH4ZbDOxCTu8fm8lDVLYV
sqYlMZZaU5oH2WblgUzbt4jNpZ8rFBoZnTjy3mGrcJgM26tYv4dNX+7cMyVJS2zL77dXRMkY5Bw7
wRGSr05gKZpTBkWPugaBIrZ9NvKishGPkFIBji7tHm3FYcwcMAN9em3yqVpfbETBXSajlFj6gpEj
CPkiRhY4xjYWjGK8Htt00NEioz63EMngg/8X2FBoNgMq19nH9H9BpozdUncSRs34Ldqe2LJBE1lO
EcjwU4F0jGoyxyyPAvkejNZLwmGDbscohR57kINEzKnNy+2TuPuK255usW3JzuYKWuMIC69C8Tmg
zrbayv7Z1tYPpbRzZ2n7JVlGFV25NEMg6LAyXvmp0NpCW/Hn0ccMe2guK33dSFWQZyj9nqGj6yqZ
Nw4oLWtxOXenIFIo1Kfwn7DSH/cO/xiDODxUI5kUcN+HRp48hXtbuhjHiEL0KCA+2v512TWRQPTo
gJeZMmSAn7P4ACdhcSnBIxcnQ6JQwepER31Gt5OkqMkFDs62rkIA5AUHlCTB3Vw74coKo+JyJ+E8
Xw4KyfnZtmuDluneXivHr7Cbc71CtPvE3WPrKI0hdHMFJqRLlX+ltcnbieEbJjOz92zi3OqM2iyi
SY5FuMQkVQlsxqoWoGNR/2lopqEj6Lw5UBfl4wDaPCSdxXmoLcOeYz+PrUAc3HvA8vvAuOzFDtuj
DL4BcKFV9VH5KFJcojTbYucRCQ4dl+Qq7ZjoAiFYajGJf/+j3E24QwR10sSNTZ7I+zo86AJA5cpx
zQKHleKgp7WEwdfaDlW+l/7Va41HU1zffvaGRFoxDaHaVVgZlgDbfPWpQoapwwzt9ANhxiEKKLC/
GGrzkqEKgg8EnyiRsVD7G8BGGsT3ts8k+aYzEe0oyzx0NJWiDbbg/FeE6nJy7qHpNHjOT/U7SGxu
3jfhJZr22Q+wYS9e0JwYrVWCGBFdvlHuK+H8TcyyudKEXtPkf8N2NdGMshulIILpETxWlyVgGyaP
j6n3FJhVinc+OwVDYzVYUOVkjJtViFNxJ4AiWIz+wXZrBZ347uYDRfuUiDBegTeM5N8eLKKv0tf4
6NoCkSPhcalHyoU+qRwtlW+wQZWEqhD8EDANoRTMf1y2Fr+TGM/Jdh0gB5P3lrP3GdMBOVz5vv4M
noWSdN9t8oj/i/sRvzOBnK017GNGOu/84BWLycGNZfESJ8lhiEofgGXmKIocj2w+fxD/1WqAIa0I
iNh/nv45qyN4cJMAgPBJlVNIYyvtd4TnGBFlQYcYiyjRJUP+/Erp+vRIT9P6pmbfvCVEZjSqHUA4
dIeM9kyioVsQgtzXpXJOimoPKGxYalhxUu7m47cV8/Zy5dcneMi9fN1vJmZ7/BOzEMfxw/DQcGFk
ijL/Q1l40ZaYS4OHipIpFVGsWRimDbyG3b5xhtx1ajqfKnzJvV4PfKI+/fp6GpEEXAF72g27FZkb
ygYAEapZNhl3PvhtGrMUw/kyg9S51ZCEiQI+vSUlGUOI2F8otTS5+LS7jaNZuxjvCb5sfn88NGq1
0ioFpYZh5N4BUvXDOetgjzFu79G13m6+YcR5WpkqECcb9EVV1KhNUDtyKrhPosgi/oD2bvc6rWOB
YxcSE4dDqKXSaklcDP6S/aDQrTk4c4xiAIXi2YqR0y4JMcQMSSZiwie1ZK3jszyV/kDzvb+HKKMC
7ekVOvYhxsjLkTraMoIBDdSlhECh1Q5i8kDffCj7uRk6ptg1YhyUs/gYvfZdn2+v1GpZXyyYGmHN
ct3j1NICrAudOoLCLBB6x5MriDlYgMuGhzUS6DjTlIVIFUGQ8s9SD7ecJCOOzhLEMAHtjes9+txb
ZUEP3Ng+Wj4OxIjKAl3NqXdYgyyKLsjX/kWFFE0AbN3wEdMvQdEv9JTldSzlQujd26l/nzyo1R5u
j1TGMwCcJOl3bF/jiV22/CLQpMI+dqOmgo3o5aNFIkN6TIeXZi+0LlwsiFSllW04GF8akQLZ31Zq
yE9X84qTj19QhwMiblkRF7tHlXPiMYGSQaBDbYZM05id1Kh9WtDAezkcx/GA/EmR7JLyvrzwLHaB
HTk4txB72SfMlYqkol0nJYu8F2pre/2ZZ9Oe6PCrQctspV+TvDkiOkNOIGL9qPnUhLRyUcxdfjLG
SkJ3Tluc7TtnzyiGx7Yj5XOPK08kB/EJ3N7fwSvywHlUwzP4ciUyCkZBDo+F68J9mzCyBZ2fZE5m
pONfg8Xew3RxHYYnmoYp8bTpFlzrAtObfD9/v1UjfSsGcU7e+ySL9lOuy9SCz/DeY7WxyB0F4UAQ
M6OQCTpNeDJhEGSPQ1CNZME1xOu5izaKbbtnjcKjCsu1HDw/9bNrtkXD0dPa7Dq+VPHaMg+G5bOr
OH+yS/dlPnqYWlnHmfw/ah+qZRVw27oXNnhZiIt6OwAgNTP9nm+7PfbY/xjHiXWiPBjNRcs9Z44Q
tDyvlaK7FVAUpjjSMowq+87T6u50v6VrUHzhcNNZFlIlkK3Q3QNCJLOlOeXVqgrZxbHUH1fhk02j
Cp0q8sZbonPl7U+DoUnadRgfzorGCqaGO/LdPlc62vRSkUX03kNvO/0XZb17eBf3540ubBTQc6Qf
AsQ5HZTnqYjhjuIdqu+mmduveytnV8PpuOLRVJxht245ZWzIfwBNRdw9TGIR07oEUQhdQ2ltvq8T
/q4ALMqHua+PzJvUR23UpggCOldsYQuywob2LxJb+XjVPFXGAr0KfxBdU7CIu5Ql6fbYVrNedMCj
6IN+B4tVH6nwtay3czmrv55hXt+U8Y2wSKigKHwZujSKbhQHXdtPauUoKZJ0GJAcC4RuU4rysess
/NwzICLgScgQhf83jVqKCSBbedbnaRYHtTfGwy32lS2m6g3Ek8NzFN6mcvVHokxD1vNqSLgEKWYM
HEkA7hwr9k+bhJz9r2F0exTIYwAaqOtd2qXmZ98vLwY0q0LDJPow3ZIwF+ZgTUatqEMXRo/E2Gmk
OuSl+3/wyvz6yumGaeU/zrNl6QdqrESXonGhs7sbSW+5ADciqk152kSj/4R7NX/Vs54I8h296Gzi
muA058cIPn1pU8UVmQ8nWVnksluPuYh4fCoUlq/HeAtc9Ae1mjpciEh4X+RWtcw7C6iGFwT8NOm8
RrWcLf0s1dFlvQbcKsyFwsikzdPEvNzEpOYasnSSxkPRIK+p0q2eU8w1RfegnJ9xvPJKleyGwEfv
64Hg1Q2ETYOW5r8ignL7U4MuM5QUaTUWkoCvH101VS8vN0tOY7lrpVl8JIcRLLq5JzNcx+riC7I9
DdaZ6ZccCO5+r8QXQbUM4JGqAAi27Y5CW67xLNwJDoIXOUMHuntGLr0dd82MDyQjNs1hdKujIkVU
BmRnftMtlMRnKrSntTrMAxkbczfCRLuQMtv7ycW2g6EKR1kw2D8SNK98XScjBfKXirRobqvHVzmg
2C5h9vzKlnWYUF4KAiiZPheeu34Q104fl5frHqHCDeZphmvQ5Qk8Viezf6BS2/L2DXKIA6xG5Tyt
IjqfYcRD7lF7cd7uyA1gYJzGyIm2q6n2HaqylSVg4VD8F8iduk7ddJpHtYIEtphQclW4f6/pxKT1
Hdt/ch+1HA225VCN9LjjEQk7VuFEk4hlPU9JUyQ4MBEqnFBEkFm+HfE12G5RP7fP+3eIvGqhX128
Uzbso8xlso8dtYhAympLTzaF+VoRKS3K4su1ndzxlPOtqmXz+14d1M4PWVZddDCD4GidpK4/br0j
J/fUyUzFvUKLdIgZ0JRhSdMcuq+nXOSbKUNUTjBf7KP+bfpp9r/a314/klmwIUrkav3wRWZGuvbw
0KPIiM79Hyojt0uHvOBPS+f4UKj4BmIGMrjMxWqhDoPYFxtNvXVobOMWkLrAl9Uyyx72jb++NaOb
OestKXz6lR6IdnejBc4ZppxCEjcMEtc4tQalYXcZ9O7LRBxxV3qTxYgs9oXFFpm8VrQuNd7+cyPq
9iWVug4Eo73s92xDN//Qzs5piPEPf9aIVFqieGWbj4F9/duWciEIktLdRq9FR6VTuUtlI3xxOeWW
2N3dfgFdhRfXH6T1hDkh8qP8hgWFQ1CdNWYd6s5gUTGxpIMLejEAzA8ZH63/FKq9MaNOFZ1P185q
RQO7jrbMUlIejdfJrDt+piQCi1GHY+T/+abiFda2PkE4oxcqmtbopZAxZSejlhBCcVVIndZtss8W
8CogBbF5f6rYNm8j7DO5XPQ6Oo6ZuVrcm99rI7nW5SOztqkXC8Gnvuvmn2ysoSEVA9HotEBwgBMY
67FM3pmk+6terNRJR/h8B1KrAwPanYoF4oh/vIxqB+cjZJhO8Xlh9bPYIjf7NwCGBR+V2nzSxQ+S
07kv/VZOAoIGoYNuzCsBaki9L7s9dVa6x8cylEKexpMmleTvOzpx+DjTTaJW5tQCKL9K9nqg7L9a
MMDTsjVpGmPykZeR4sDRCbu3ygM3UBAy0Tyfp9XrdlZzVEv6IL+kRqExPm/mG0vbhTu5XlRJpxWZ
KlV3n0YUd/s4J8JcocxRFclQHdUlA7zEXFggnZYxX956PulPnPUXI/PoE4POG+QoZmEuJIlrhTDQ
cD00kVmT5HVQ/UVys5QwW5lkKqoi8mO8Dq7Ucfi8hhLNM7//TTr3n9iSXogQrooWwXVc7BmGizpu
Vr1C6zeHoSSohtaVMCTirClr+UFyFta8QJiCJutbcM4LLAO6ATE6gCz67X++mDFnYviZzKnqs4lS
xLxLW34Gaa57JSpifjjB+gVY/q2WmN5AqO6za7Ky5O1D9pjxkfiKA13LFAl1XF1LHkmMoh6WPJ8j
mrwv5tAqu4M/oQE+eRX2n9JcUwJJ3f0/gDqNbu+yYARUWkrykecVDGJPgpUU5vEsbxbzjQQZYi/e
BsKmxRrdTa2iDlqJFWPAVFGHTYXsZNMi5EXeScFlTkC8ONos8H7Vm8LKj62107O8Mjy+zQ6Fun2x
BrBELufe//yBTIS37gJDw/Jtxznuo1LyJZrNxWMK4alSUPQoflAGf1NQ2q5xBkn4WCAhqyWwCWvD
ITvOE/bLh1audRxlZ4gGMMj7O8rjKVCtj4dSwXoWbkomCVoQVcBt0g20BkUQUWaInRuNeBjoA/Tc
2h3W7bkvQFVi0Qju3fJnV0DqcikgJZvsAR4qqJQe44cDBl8uT9QWmZSj/R1higAPcX7lsIH0XRN7
Scgp1xcT9E11uus7Mrxflq1MwJ2WompG6KE1zroOl+AAK3OirpUN7Be61thOkQ7LWQzx7VvK1tqA
NP961d3bUnXzqi/1vrt8c8Rl887Lx387AIRHcH6X5ENlvZd2Gl5JBWWzM1tyOtTCh7v/ah0bxenb
Ptr1Y1NwGwpyelJI90hxGPzUb9bK9DLyBe0jTua3YjO7CFnlLcjLrbXvqwBMrjSkivspUHEx8YyV
hVs5bb2syktkwPRoB0hFrXr4Z9QJbqNbts5AseW1e+b6aZAnAuI6iCQDuzyuUZNAY2k0xfNXTfRT
Tg73/MqthD5DMp0AKWmQYVRENW3JvYUtu5yYYFiFaNp7+x8MlqACkHrom62Zl02w/qvi0nU1bkvx
DoLGmp7dMcdmZFnaXLN8kFNwaYRiyKobUfzOMz8yDAU0nBsfKIzRkkM5UI63QOcpYrR7dmIIXJRp
0OmplG0hj9hxpIEHPy1sfOZ/Qdl/3x0INCU1kU+t/9CTXeQOlWrsBkqrGsAmuyjmdpRiMK2GfGrA
Hqd3S3+5lvRdI1JQt58uVHHcdvvM4mLKYSgfAz7BXzAARpNefPUVsnBbdqN+gsOGxI5sVoBnV0uc
Z0lAEBI/wKmTzuvxs59YbZIp0pfaxQ7qqHjsfwjoTL2O0RTJHKx6fvV2GQ8gzChLa7RMiWQDCdO8
xLx+r6/ud4iOO1J0Uci+3MZ+V/TPsorFBvaBFwItQggK0cwLoA9mTBrwBDHqLdmplfLuci6kWivX
jf2Br2naqMFEN6cngVV9ZcFHxRt6GI6GpVJsfhRKD45M+8lIZDIrcSCaNX/mvEe1SwSe4qi5KIBS
/GviAQ6tFZ+yFFFfsYexRZeTgZY+Q08D0pQEGHsVxF51x9XI7Z55O6LcJm68bd1iPRQlQGM8xqfm
d69WXfIn01Z1YpF9RDTraQ51Q8FYxEXd3M2scLTacwixF4px5HIitJl0YC8pngmp66rVgxgiGsvP
PUfBOaIUo7BT8a0FeIYBFy2OqiQ1cE6XgaoOOpEqhDls3zZCIRffMOucGeNL4ayJVqLvU1BM/JNK
YXwH2KFUVeBUNS1UNlScpwSeENISf4nJW+Pgvnu8/RCfKWuQs9QoZ7Z6gnNbChp3GbM8IQgumxj7
YbbQzzhjEox0DUrtT03rmWoNr7U13QiltQCY9uoUzWkZ53GNSBo03T+0p2DmtyNGyC/j7bE/wP3j
9hxs7lOpKxfiGHOYE59BG1GXj4OKSPcRoI0YdNcOzgpUzRfL81oxCDPYb/ce8xRWWC+yc0Ony6Jr
pr+pGUP1hk4pxIoBwN0s6bQNlFjCNTAMDinG4bkosZGQKidwzd65651jTsy8dKIEUXD0J1lOPdb/
uRV1+RIQDyyb2t8rmYv89Cpv2NHnQ5mnkj5Bjz/fhz9tXZ4/I5g1ZMjtgaqdVTTNvdibiD/YUGux
chQZK4gM/CQnYfmkgtZvN2QmLnCKP1Glm9y7ptNnkuJIHKdiIFuk0mTkN11PXVR5Cno4Pvum2a+9
eU7pFShb/m1N0tAfvaWz0fb5Y6/jsGMOu0z7LgorX3tOj1tiLKRqrwXw8C+MVeFc7D2SuQrkDKc0
7O9+iV+wfmhSbRv317KpnNbCJxaF0xMgzmfl37i3RSGs9JXbukXKLwtg2DHMGRVmgsZIPHxNUK5d
YiUqMaUFHAjiS/Sr2l1wNAVd1Z4d1B24dzjmZS8mf27MGJMfAxgHBu0T0NrM2fOudwH++JkKt4Ea
dqpYfA85eRYlKuejU3q8YTUB+FGpa+3SV73FHlTZ7VUqQgWykaC6lNbACu+QP2y8b12QvJj69hk8
Yfjoy1TftF4cyQ/BMS1ioF2kBIHqAoZ/++WlvEkVHFLGvLV6R+LFqWhL9i6gA/2PF3Egs8at0uwV
Gff+2FhCUQmTtKl4zUe2H9Mjqnwg4cErM4vP8SlwKZJ2NNij7mU8XuYc9Y7riNGgITht3wEguZs4
gj4Soo0fbrGsgbjHe+Hd2cm7nBBH3xvqI0Yck0ujDHppx/Ti+8z/DA/vIXWbo21KfY66YIrC0Cd8
85PKQ/BySWXKqAS+97hSj2hhuCDzoywEbigBOkuEciDZaWj6rBhAXDINDunCqORO2AIBKcbDsDlc
ooyqiRmZMUkP928p+cCAWaml12cctXLIS7Xh6ynAbfRzhPDm1rP52b/WgoM9bRolIX0lMm6W1o9i
Vw/G0CxJ3UCqJIlmQ8J5i3Qpfib8BG+MwYdRckjQj4XC/oVexwqMM+w/nxZ9YQUccpCItD/gISE1
08Endvo9MXwLSBRa0PqybsOql0lvnaMrpge9ruW0usKxVSNJ72BNDMfgfMt3sjDmEEGyfqyypi1Q
Jt1PUIGtV4o7HyLzsJHGzTB2XXtQ7LOhsrMezjyMepbhjsCtFJ0uncNElI+fHHHlYFtbv8b93wMU
ljQJIvQ2gjariv8TIsPR1ClY4oHre9aK8xsMrhEPhnyOLUHQzAAoyXOFQmvPhrX+NECZO+XRVuxv
tfz09U2sDA5tVmIaaJb6P5wigizr1W8vlNYLXRLoDA32qG8jV58NtwE1Kp6opPugwTOJJq5oYwVl
SQG6dnIqWyx9Xm5Xca/Ke7KCSlLXQ7XlP4r+fjQM4jpQqA5k1UrOomqMaWs7uRaWfhoLfB4D+db5
+5bpRzmQxv9PjSvRxc64JRF1il0x9Z9IKyqJMB4WEtukA3WPVmSXvsl4hgCkS00/rH6kZPpWJPpE
lxLHc3Tvcp6bF8dc/8IPQghum1B3F/lUSk+mm8+62ogz1zGjuDp8/oujhE1eAveF3EnVzXO4N3xm
BwkHiAxzTEbr7rduPXS4DyEiR8yy3ox2vUT1/ZSjxvpH7N0Z4UpwNmbFQ198+D1qKMTjfLAGXyzy
st6UM3w1N5fwRPl4SMkaOkoInsN8Bd/3tS7aYv+9u4QPg4GBH6YuJLk65+1+FFvSRTcP/PbGX9ad
TNqNSQGs1djqQaXIXdVbUoTPLLJ2qGktrJ9emSkLw2YxtGMecBoQUPRVRN4kz0QXppCiXyMj+wUr
nLXGYJT5D/oTmeqw5KYbTwx02KQRDj/ZuZCdZy6eFBn5Xs4P1Lc2OMhAugIeNSxtzCBh6xWngzvQ
sdXl1NKQspJzUWDO7ylsQQrUtcPkmm7Kp4btD1jOjN74qyiQzvUZlzHkm/IEXxG4pT6Ttd6BXhXu
YVn3k0CtHOG3Ss5dysaic33L1JMWNIjCqL4EtY7OtFtNmItrg7dOdUfQhhUTXFhQn5V4XHMBmb2N
6QqTAmGsMZAYJF02pu0hyvF3vwweqXBfpSmPGkxhRr6lcvZpQw/uUVXdIMSmkOOVyW+aWKktAKb5
CK13nVxx1EvHVeYsM9vV7uPu+r2orDMhrmxPIkJupiY34vphC/k+3v/cGRx+0vzQ6CK6htva+gwc
utX6L3d0HtbIHQ+nG3DzP84HbT1gGkpcfne+3kvKqYS3PdSRUhBlKZrCPJgqQ8OiYDW6Bk1w1n4G
0+UIgMqrJ6izcfDj+/y+p9WpqUeLoTeAsHIwJRnEJCBeVMD6fX1SKopy0YZiILzHqW80/ncx164O
nowzXRMr6ZpC9/n7pclXEbTjHpxtUKbu1POlR1N5ikAcRr+7ADTGy4bxIjSQgpg54yjnQVM90Epz
mQrlewf8lkM7SSuVZveBZKr9tReyl+nLE3xWT++A7mQcRcbyt9o1eRygMyvLkUT4VC+IXIEDJ9j6
IPNIRuuSYcqKO5ojREAECwIb4U4YQSEnf2aXQw99iRxWq+0b2q7buTf0ojPbK4LC4AZAyTsI45M1
ApLtPaI23P0N7N09bGAumHPnXTIXw3NE03V8GnMmJlYIEVNUxgx6aT0DwyQvn2agx8Ejfq0Tq3qT
b/gF7LqUd6cs81SwGwUqb+LDyzwc0MbIZMOBGakK5wemcb1BYqXPfuTsOg2ORox7ptzuzF9+yvSl
PUe8if+x6y0hWgtNGaperQp52AlcCGjNpVOS2XbOqF4s064vwvtfsyHJk+8cBUwGkxRTevelmjQA
rlQA+URxbjRaM38GxxLIQByGijGhDg4WFUDhgzvS/mwj8AuS+G2cUCVVQiDAl0EXFjsJMV7sPbGE
3kXrC68wCKdQAK2XSp3bqMDY3V1b28VqaGUcpTDsvJy/1a9QQSKym3smj5FyorhH4ZCuqgTqq0nt
BPxUy6hWXH8/jT7EOgxGIiOKdTBtkK0Yn7QAuG1ZsK/+IXvhQOZrkLzugBLsVCkD+nmU+TJ/EdKK
NIC2tx9SCNEMxL+hL9YmeGCbwOyb6w3v6I78ZCIKnqLx+XJgk5vAPTp+IY0kEzdw/PdTjWsGRWA0
DEN+vmJGasLRiA+x9akxw02GnKY9rIGVWytEkePVhCIB/SFLP1EHOtH1xw/nkvKMqqdbLpZZ/Idm
uk9zBRwSr0WpulcdMHia0dzOk+IPRpOujTx8Ma25C2TnOemwsXsKr/yHIZU3skWlYYIOOPQKCY2w
C197tLL//BL0CNeGnMQsEfrnrpF1gIEIEt4bFexRuudW6ppsDB3WOzbTSxG0Wo62h5mAUCrJKy9m
SwhJkN/DzspdndlrFI/Nb60eF3LUieWc45M0Qcll/3jcE2BzhNwDEqEHUuqUhv0So4+DSYACcuAd
Yie8nW1oesvUa0Eo+AXX0DlmugiE6icQyVdJjlRbozlFK8w5uxA2OPNjVlwYL9we9DHNvOccv+ly
25e+UwXEUppcsSpQ1zLQHx5ujcRl8xqlAdOcXN2aoeZk/ejDyRzeS0hYL8J29ker/HLuj/ZlPL5z
T0jOGMebMLOgM3vEQoT6TwRwPYOuh4WYx4YNxCmOfezXt0M5oxeTfH1wJL7Ulppv1i5R+zClbr3p
hlQlOKvW/Ny/B5CWwHbst5p2Ik248FEtpHPtlI9+vcqVeWJHovgkUbfWf5VjClFFfNp986yCqEgG
CgOzFb0UlxXd7mGV3d+Kq0QvtRlPNWDlLIgN3cAqO4B8R/zOgr/pOnbcWq5Oe/qRMl7NDvXVckQD
WOStLNlVBCnyx5Hrrafnpj9had3MBSAStZwbF4nTCuHQTP+mHbXuotFk5hd6QQ9zi7D9JyDGfYd/
rrUkoj9Jzu2PB5h2Mb6/pcR8amkbTfcpeLu7uAuHS89+AzhBmHD7CIzYVWanjStsp7rs+FT0PSph
5ZeOAYspTWudSvzz4LF3oORATQDZCgtZgVV3DsU2u89cAPr51GayDrkDyuN9TDW7Id9sGyvh/A66
ovVWqBE+R99d6Yzzuvz5egb9mTMBk7vKeE3D3BlSfC6BgN1QG4jEmIfTTA8XjgJI2jlxcBmuWYLH
SAdrJG9idJLRSyLTH4Evzv+XnGGH1biTLjK/3YKJkPycjH3bSIQY8RLrhaqJqXLR3ok/DzV7n5zW
fCCFulz606euSXsZpsNlnsKjNHhJXjQL+F6PxwjV/F81peFVbSS/q4MVPzcWADTe0OdYb1XZnDn5
LPkJ5kHCVBp+5AknSJ9B8PofPuDo+EZHhFXT5SBXW8hVsIQ9uBT9MbJH3DheEdj+KtyrhjI/67kq
cjf/EOMoPhHcnH1fUYc4vEeQym+96XnQ4obZ3uBqaza25CvBa0aZzkDL9wTFfhJyl/xOn2KfE8iI
AnNiyNnV8OAYrMhBfPxE0KcbeTNVcoUOf6WaB8okyuRIJX1ySedCGRk9J243CD2t4p3q64d/R0dM
1ZaPKMzKTfbyaNUMVwpTwA25hTSWeQk5qNQo46lfEQ8M0fDosxcb1o/5rXi/5uT0jAddhAgpRARt
jHQxz8iQ2GIFdDHHMGNddRjqZqkjtjYKCcri2aMQ3UTz4MYkH+rgndqfcdxi7K8yB15UTgiC06Pf
Wtx26Zrmol6+jX2v4ijT8m+smVMo1jN1sZtz2JHYBNWAubwSC3/qxW8neRX48tHWp8PUWY0La44G
SBNXVymni5Rm3Ss6LpRLz63B+1I96sYf0eK6ZwqZnUN9qOagV9dgnTaHSGMxtOg0lP4NfrJ4AvVB
GruFYrHcP/ErUZ5p+pjWudT7npt2po+ItnLEvmxVwnHSNuo2zNO6bJNgUtfAQt8Mn8ukx3oeODj/
l6GH6bhT94BO050I+VGnbz0yTTn9w+8ydIbq64pR4kll6wKHs9S5I+PEc/MpzrxlmnX7a6jMmOvT
Y/l3f60HPrmJ4woLqUed3SkTzSieVsRd9PYj7IBzSYz+r6vO1BHuEXJcBhzMFC3b4i1vy3cnJJzK
lVCRDPtiDXpxh8IGbRTJEpT6JvCir9amRUtZPl171+PzAvWrXZ53wo/BHA9Bj+IznGkS3NbYXtoq
UBdmFNhQbhkt9FC1QmRoMzywv/Yt1m24EEyOlHCCQDBkIrwHGG451t5388YswqSVNmDPbt0UXyl8
3dO+YgsDndKeOKfHOrKUZHITU4v9TeUbI1af+pQH+LmgTgTWbcFZj4s/gm8MsZ/ng8RucUj9lEDH
LkROjCLdFTQA5nT2sAv5TaudJvlt+TUPeP8NgSyGOS2Sy4UOXh+qm/6UwkBeI7ySMJseb6iYPrmy
pJ6Ts7MUTC6c5KzDfQXcvPqv4xWIgbZqMJOxokVP9rLIEcU3960+ua1LZlHK84gkDnS7EL5ZE2oH
8BNC8WMtnxQ4pYUYNyqrDjxj32tpj/lKkY1dPx07YvgG6cYD0svkl4j98nuud7HSKh4YTiO5oqQa
JOREDAWNTWY98pGqc+i59fce+9TeEI7dldVOgGdYx6+SJSKhmQ32qTpki9bse5e71pR2eBqLc1ZL
wTJYF8YgI7VuSAmoC5p0mi0QyLidgrX2zk4/vPzQbNgDboa8c411NrRmIQCarnl1vxNQRRPDVsh2
2Tey4psoRtszWzkXbie3GvL2PLrGuH5zeAuhIV0eNmuRwJvccZMYkFmhpMPT5ovLAfu7mLWF4D96
rrt/be8SwnD1/2vXIUXslc7ufq1W9x+csf92ZCmhyJbZDwIVNUiJ4HWoR3LAlcZzL12fEvRvYKas
iZhx//SmXWVA3M+56jvQvNZLnc7lSxHv1fjtVmZmW9WNFxdfTPnN+YO4njKAwLnf1Zrw/Sisylaz
o9LWdcYYTGLNBpXb53J2JLOVYF6uw+kUhG2ebMSsvHwvxZYChqcE5+pEiFLDlkKBkrVIsWB9bRFG
vgp0NQHoX50EJnqXypRPeojpcgf/Tj8nP92ksvsRxIg40RfH9Zk2Jz2Cy+LaWDHN2PRHDsM+Ts8W
woVOZ+F0KCBpHZv/Vzy77NtdudM0pEVlQ0NmM8OF3eQGKUMvgQXyKMyWbC7uj1vjMKdLH+Q8SBxy
SziFleZcpV/Asf8nPWFJtt9ux49+3b31pe1Iz0kZfxQiyjsm/alSWnETLU5W0WS2rA0dV6IukDq4
IH32v60dl0aBq8gNTKrnvBjqKjqKU1BIlsIYnD85pdhrDKqREr0QBSFReeC4VZfqVIyFG7hIp/77
JEVJHdf3ZVsF6c1gSSAy05a0bkIOFv0nUqNzG+PXjZP83h3bEsFrfcK1ywcZDmt985eegl5PL/Ie
tfN1/ZolHVpBnlFS4TQfxPqceFZNl7SUFMGzIsgBEWP6nG+/A3KM+urALcOfyAjpjRFPx5oUsKVi
p4zcFBIfX99ZV+Ai/HTlJ7x8NQfu6W6/2eT2WyU5jdrkzqZA2nlU8EQ4G0pjp4S9RQGGBy4Xe1/K
yULs6bhnMIoXCeeBudFl5N9CWKrSRbiluxmUI+9N4UfBF8yG0LCwsdm+dAssOWjrPTITj6pirVGa
j6+5U376nb6ullR3IXTXFaBHuW9NaCGAwznHWJEjpx/E1oVrpsKP0q0UgoYX18Yj01kQtyQd5JU0
Aju5RubZ5uYw392MrI5h3gw9ADQgOpYbNGMRy8BBS8MpUc4b2+bcGDAXHdHon1KANYe9oWiDFBLf
QYKq1CPLjspsvfG0aKvBmd284dO6tUOuPjyeE3u2pm8tczH5yZuPYnUm9utQKwt5Fa+DHIPh98Pr
9wj8XnCdEl9dIQ7tdSQW8QKM3/GeZULDsk6gTlYc2UySjRYTh2Z9JssqOHgwJeQVsMogWBSzMn5f
U8yjz3EpkI/QUR09GYUJm7XrojMFXvt+ESuonhqB94jHrg8QUgK3DOcDAEytPeM7dPNeyC8gUyCL
6JtMw+gnuA4OUOJMkTafsdWRoi0t+Eh9f9pV8Zp/PAOACZJYFZhrO85FfaXRs0VOgkKoU/SI4v6S
ZqJ9xOyVsJY8d57iPlHmQwAq94oYL46bjeTXmZAGSf87M8TQRvGsyMce1siT5icHRSwNym6rpMyL
T6lm5wXcqbSHxrIcy1CuTwqYhxPiQKX0uVZWkZVCmF+vrUhraRdFwJeiYMKRbj0rYd74zHPIierx
B0uvRyZUeAqtjWiG2QmhYHzebc8gtbqeM8cqVMfoo/BB5TPioKGDYUbBACz3+3TkmDi5BeMhaXRR
aB/vpZQmZGjDswNMwS+DgCDVnmikVRE0xygMtd6plOGezO8yxDm6NUi5tHvcC2wTMV7De4K4EMOb
ymlANHNS5uf5wG6dbWP3SaGAWt49ksIB9hyfEMOeartA/m4VYm5Us7ZQ3ip93OD970Cfla3IYC7E
gPvmPDqj8PmsNsnfYkTjr2Df0sp1Sn9b/5WcppCC3K1seJ9WU5db2Ejxfs/IV5qKYqwXcWrycKir
Q/KtR6QLbZz+5c2ZhDVqEjRJKUOwUj3xG30UywLKkWEr3U3HhEHUjAnokpTCeAmyd4scDJCTDgKv
9QZ/Aa5WXzCJzTM61FzHnTgIJTKK6n4ZwNdCV74x8B1y9y+Gq/Jee1SeAla/MpzpaWu57eAz3+me
XdJ/GiDAxeXnVheQiPri9Ro0SNMO3upKHu7+zQssFm3MOW3OmqXGPNfAUOUL+MQMgT2g0Q2fJpqc
UWZdIo1QqBKjNenfZBdTlYj8UzjN+EUc+GVStfh7Z2e/hLDk1GafA10RyEe/XOv7TVj1qg2CPZ5N
Bg4V+72Rvm0QRIyTp/Fc+noxdB6WKXReupDLCFNln+93ic3wpPd4EiyEn085yBVrAKaSaSBDqfbT
SjhsAldbemi59iiYBqSOO6EJPmTztVNMIZsLJwV4ysfVmpnb2vhrQMwOf/LbFmIAgwwWTWnAc6JV
wkfrRMBSYRWwxmb2mpGW7yNFdTDNCOzhJYZwimx7r1SPTWRfKPva/+I5P+IXLwNhhlwTeoz/LZOH
1xzBozo7HFf2SNdvHkxCYXN5OQnlCp5LJ/KiZGm7CpCSspo/38yEK2pIpti83x++fZthMKlqhTOd
eVjHq89XrRY8TDeq/i01O2FszFF4w0odEb+b3zVjat2yhnMebryRf8xK+D8L3wCh8KwHjwK+CUgy
2JRPudlR17qofMu2/v5C8+9RlxOu/8fVQtVChZikoy3UslJhMt7A7vvPfx1DR+wCCBhNS/l/Vwbf
g35w1kXfd9uRHz4OD93c5tTigu//77SeBlMN2EmLWIlzhlz9mOvAlLZ2QzXj7iw3Y1HlK3gdJPO5
SfvE6XXwpJp5NrF7dogeTcKNiiOMCTeG5YIL10sQjUL5PGpSpfiPMoimBjgJfLmegbNc45zlEvIS
t+4LzQ97DJpizqNr7bF1zcbXpqxoH9F/OOGwE1pvmnDv53IIJG1rbt87UlIAqkvISlKntrV2bc7N
IUgXERPMDyLda5Q5pA961sA5xZqteVqnNKJ99Bu4aYipvhy9jKTkLPW3RAMGS/6QhjbeTdcawj5t
PVlFzKuMTLVDPIxFVfIres6Pk+B6JLv4OgnFIsZZpDA2DEt83JWindUC1eqDfK8hDU74gL9Yb1h9
4pOa7FD5ZnG1gMVvUqXAzn6KDfrcI/kB8rP9oUb8SqTj/64w7m1FS8xX3kvlsrXliV6cPuiku6m8
9yk1Tw/iHD3sO8UX6anPQ4K/nIQItIquYK0Cr3QxxP6wx9Kw90QMCChzu6XXSi6kXCw0iQHOWt+S
qB64cWhtAH4R7D8MS7Unm0MQELz0Oj7tZZcLVU5G0veEuQszlmfw6UCoYVSGhQMM+XYaVPT91bd9
UcsPpmbP3HrFxzNQrmb4xXVlml9vOALNvItXFRPJY2Th2OX0xC7pRgBsSfbBMIjxXB28kEmx1S3j
O+vYfMnujFYG/yUjIo5YPzpcvRRwulNrJ7fP1DahPSVLcWHB5fbYJRZw98qPajglWhMYBVknOoPv
2uEbWDmvn0YPvUOJkfyu9Dfb8L7H6U9VTKEt7uQqX8as2xVZa0W36rwkjSXHEPwb6nIow42+VK4y
VxfYmJqXAoKg6G4rer8gRgs3fxmGixVVZZphSBt88qlQs2skdZl7gTRhWblNfndr5mutHzxOK+Gi
u8hyLw3iRFh4H8GWKTeGdS9ZeVrl5fLmKdkt8fLhmvklJKlG9ZcR4Olaj08NiIuSzBcAfyFo+0L9
0LmZ4htWQ675amg/x1OFu/tSeZlR5rpYAX6ThyAZ8HicLIgtztdgiBwhH/ycXv8XDFS2epWns93i
iC8eW/1otNxxOM4Qu0QeScbVFylxGA9TrGmbkLKzALWkCOUPZ81Ui8hMroIUXzpwHidPOS3M8jx1
P0d7aYa06ag5OtZR8vweaCwjVOjdgfX1OCpq2fLV2XumUNMzDiT5If6CxIyfVbyx0uSTs2EuVXDt
gA3+ViZwB/oTcoCUsmvxE1d3Ltp6D2IPveQvRpx3N16JBfIeZRsg0E/7nwBrU+zDeXe4bUGi5CQi
JpXwIYhEi1AbZMfj7E8/RnSz4cWEQXpHOn2XDxEVcbzQG2XWNg61yJubgpUektmbql984Xm0lCB0
TqRSjc3qINk0rRxLIYGtHwG+wIjID8s6Tdl6MCTXp2njfdJZXvVXmxQ/BWnKpF5jYzxU4CiNHrLD
77PIuNN8Sw0wj/FZraIgdNlmFiunAwBWSb+wD2N0Ou5BBr9vvF/s8hgcI4ZhclQQP70aSEw5wgSo
8xG9/q1UQJmi1mbJ7m0ZIdTuV8JgKhVMuAJyHR020LOnbqoGtqkIYdzoDWmdBtb0CNn9x5AFM9s2
iu+a4y/8TaM/whNOgbl1qxUKgDtcQUUlQ4GpxcCHaqtxHqcmdA2GMFgHjaMJtDTEm6rD3xDZsIg/
oi3CE+3Uwj7vsLopIrb75Wq3yrgDDbcDVJYaos39xgexik8rojrT/IfXwA9sB5e0o0ZKJS6J3F3/
4+9nN4+gR8uyooMldR/L+Fyw77HCnyAraFUcoKMiJ8KxY240XuNg2Qct5Q9k66Y5al/O1PR6GCrV
eVqg/aW3cUgF9ffzy7kiik7we566sf4Smxc9arSZYG1A378idih9cJz0JSFS+N0rwgQuU8d2L7qS
Ag7NmkL2k5g+OYXeTpjLTX7pGs98H0R50JYs131PHCA8wyRk8YDGq55YfFdcfYJAHfV2q7ST+smI
dgRIHHFkWhy8OYv5nltZoUbrQj8INdX8a3BpONkqUD9KpgK7Aa78U4lyV2dQ9tU6I1QtC+jrGZw9
dzVIqadcynm+R2ERG+5Hk0sZOeFiWOd50sqJp6bAr9z1HyL3dnTGQbAwNeuFn/n0mGFBJMf8Ex78
8e1LUk48bTL/MuhkMPSakIJ7a0ofLe7yoeITpghyTIrlXsvfQ2/dVaN4dmgcdocMZC8gyKCJiERb
DerVT3qNzo3D1ISxlF0cgnkvDVkRix1fDolJcp81uadJlCznM+3xAcMc75DUljCBUDbL2U0P31ug
g6MVwbBOaEGGhBJAJzm2hgZgnVSbKsebH371nxRiE9UeDBQ9xwDMK9XfRSxrvD96QJIOcrQaqNt2
6qASM0HKut3mYwy+Ut9KaxvuhSt/k14rFtRyG5pjoRQ1uFtp/yKps5JliQlvvbS9gqssY7oz1S3Y
wGfOrjpy/6q6pknIZ4lUB7pub3ECqElE/wMWZk+huDm5EzqCevQWtpnjqr2N1TMv5L9TlXfLeCZY
24Jz8AqwkKtGVyzS3mBECsTe8QIgJ7n8hcDMtowjEaKGHg388dTCL0ZkU0DY6jHsDlDaiZdPl3L5
2sB/7D6AvLgOP/+RRG59EqXmMI+ROBvLn70ifLcRV8tjESOe61UCkhM+lFuNhef8ek09KI26cWNg
QbtvhS/JjVzgVx8DxsJPmlk0L+0tTUZLfP1lw2jkjBYNspHMA3RdUz79Jsyg+6KumuTs/DcJAEqr
TZQZfsDg2zpAzlHl4tF87imuWSvPe0mTDVUC4NIlhRbL6dw6fmQ3Ymc4g2uuD74ihoLjcjPI+7YI
A/Idvh4RF9D7sx2ElpSRm3pp/YjiFsdM76GzAz4VMbh52ZTT34WqcaNHo/K3iEIU/uTwYIAPyjuG
3/Au/JtH4W6RiTlDUzSQj/FlmO2xQfu2abDX6t9qHi7x81Bjae6GbKTdlEbGslMqA4/Ta7Gx/e0o
8bpjyBOawmb9pSXYVrXbrGrjlq5lpiy4jbWZZfDHQ0Fv82xI+c3Hno+KiOFlYJuPmZfmI91Yyudv
8qdCtUQKlFLQJPIQUj6AtrLgifQ/hRKhjjl3Y/+m6amx8EsY3KhWjwptFxCDFQnsoodp76MtrMz6
DhxkBFlriBg46qC0iBF53/c1Q2BXMIFPFbqxVXW3FXPnQjDTbZoX+Ks7Yd7NKId+I1bb7jED38u+
pc5VTedq+ctcwXLGMiZZ+TwKdpDjQI4pLXSJUpm377zvkLoxAuEeQTQ/7tlmjBbyYpQMqUHhMBFo
onS2O6P3WDTrx4wJ03yzMnvNlyeh+QFMMK4ANB3Cl/v5yVv/VMTfhNcn5t/pFX9u5JlIBUch4FaH
4kB2pnX/9bw9qSUX7x3lpGpa2OXlalhUnGwZ/skgiaJul2kXgYZDrwAuKZqbsk3n3V0w9R1EENCI
oqFM/C6c19wQta4vzUPMmznvapwDFyL3KYwg54cD+yC3ltsxPwerD4JY9cIiK/rBiZ0HCM1u3HgH
THUnDavY7mTrLUfZk+zC2wgUMNZBIhB0JxBoqlTxht8hZROxHkxZCeuFaPpjphDxF2YnRlzBsLQa
IyJAInFfd9yQRDWvIZfEkBxJW4PU/Ic+KVRKi/oc9/azrXQR5NoU5dW5jTVjLvlXY9kG/KcN6dZl
Zy1bma+xto2a/7BllwTT5y/Nj+OO+zF1QoNAOzYrnqyFXyNvOytdoeU+0lVoQvF6bjZG9B+KDwRP
sadkBH59Z6yIRr//j5YFRViJlPJfF5BkHv47VskA8ryEgwiBBp3hZSv3jwzfvy1+CWlYmrNirF8b
iwya41vtdXgiGxGD0LX0eJ5U6YEH1jGMKI2O3oQ2hNigCRoNV0Va4EfeK8cbf/TvQMz3KVGzvm5F
sUoVoSV3Nku6ilZImTUB7n8hRzk/Lv5MyTE3RI9loa4XSOiqUA09rmo1gfXBoE11/vQQ/wadQWAs
LZ31R8+GnvmGhME13MiD40ICHh1bGnJ9A8Q8OKItR1NWDyt51muEWG4xgPWnZXSqJd3FmFLJohiS
Bpqo5IqES6p9/G/WskuVvGc9p06ialuV12mqkKdknefU9Kdf0Os0LjhATTbaDYdjZ30oQniESZqx
eyycGhqmjVWFP5p2HAtgMRhC9RVl9L2zdRqEX+srllOwecHUrYDFySOFS8hCjzQGMtHetz4ngevx
dp1WQKAMMg92Fxi2SEPwmLcckFEnhKMXkaakJD/OJRD2nHyPwnCLZa4kd+Dj1MfPnpL9iNu29w7d
94z6KbU/H0zINPoWD3DMsuDe1PNs0QzPziDBuyHtr+Tr4fCpgcyHWONFEif4Nbadc7p2kN4JKUx3
Vi7aLTx2hKOr9UDw2ScOxz4fZb7eHKiRcrk1cC+jKbdpCnFtiBU4hLR5qnBtuECsanR6F1QBKWMM
uABRKW+0OH+vz6Mk4LnZ+s6jPMmktiuXYy2tznCwSCexDyonsmwRm6F8UUnVniezzPFN8WyIJeL4
QAz0+iNRJZzk3qIYmKF+4OfonniMrtRr/1qTUaIoNgjHen33JppX5iyWpI5qyQtqyswZDa2YK/Na
Dje7qqYgMUDyWyjV5T9TU0V3jseOyBLt8+Vq77i9WLG7r6NycyuYsx6E8pPWnjLuuOYZVCnN6LmY
BRR/8W1gr9zvbNrKJgcUQmgUNjy6jmWzkc4AOedMMfegg+Jr7ZsYZzCQyK2birryUoBQBqHafiei
bbMDZNrsBaKTg0x+xbP8RFh4IeFYBLMmcXVBdHEKZAvNtIOY5sL6iXhhHMewhd3pNv7vruFIw+ia
uTZmwEn8iuZHNWvjxw+ZUZm7WQWSmHDKrHudua6IrEZtmYSv/ROVYT/IMyD+DhMEcea3smgaWZEk
yBqoqdizAoNND5uxt022qte7Oy8I7AiWCFx1mpdrthyo8fLtXpYvvPG3+zBgLIfAsDTky0NRnVBk
bdrOF/k6GwtmemLMlGJafTGr80BrPYewTrNXK/fx9C2UqAv2nGJHMkuLXIzoUA8pPgvN+FZeu/tm
zcbmb4yJPwZMBESqNTuYRHVzTgbmYJKFw55U9V6loHNSKtCPWyPi4L6meUmoaLm9SOL6S+91hLUS
8WtWR25uJDZHYORTDtzT6g5VvNAo3W9EBTDBNFBkyvLlipfP7On9fe523168+nf5Y3J4oOZkduWq
VovfT6I8YzX5jYgPxn7iOFCGXiEOe96rWUW2keRzSCthztH0bX386KB4Nj9ZTVJzgUeyoLmdQP5m
SZBIe8RhTaGUyM+At0PI3P+SmZDxZJgtagLHzRGHkleuNwhoWxWkkrpm1CO7qJlH265LJzIUs2ov
0EDySj23JA3kdSVSyfzmNTAlSvE0UqVo931+UKaoCzrzfo/Oz2BHWzGNLlsmgWxPeHn/greIS6iy
VwOIoBmcS1vC4VJ0CizMjy58nhO+yI8/aN2PmbKHJhVlEG5+8t3KeWpihYjfdhaCN0T5gnUY0NP3
teEP68yDr12I3wXG1AN8/6YWNi6ZZb+6BOEVqwfw30szBAIFqW4QcnhkiYx3D3qpfqBaUzQu04Ef
vqQ/Ci3HJ0YjQ5Z3yJJ7oiWO5Ivuh/Vdpr0LatVz2ZXEi05X1iR+zIqrnp6IwgioSfLmr1bempKy
JOtZDLGkpsPBcFti67SBv/79IHm+/a7xHKdWFrlOyQ5vGeOxfRVMwyOWyI8yq7vVOMzZTSR2ZceR
5Ci3565b+cFR6XJzwKVSPSF0s2Gn5ERZH3HfcPC75grsuZjXL1en9aNngjrMq3BMD/pkzetmrZoz
6mGpyRBagPKMt4+xu1YhvYMhekoRzm9WvHN2t1uWQ015toICHDtI/6OHpNaoeShOjnZBnlE8Vya+
cDeQWYLwYmjLW0l2idfir3Btj47DP1/dKZfWdo1tlvzA2NEbIQE9drU0rq3VlrtQh2e0ffvkzPFd
BqXpMVNBiLJpRjXnY2jM3/J9+D45xYSD018NiUz2LoKmqRUO1YPDlFdkE1NFBqh1Ksvz+LI/7rhS
Wc7RMkg4llje/GQw6iIAp8CA0+sa351ecWtCC5bNFmha+1qtmC+D99AWOKWieRbryj0TLMB7scBs
/6xZP3TE/A4z8qRHtq4ynmDR+bQ1LODcdk3tiM4qSRPz4rr/yugvef5yEjmSKiLa325hNFnaLzni
zJG8jgvSHJrX1CFGz3KlrDV4LpoU9H0IYcVVzmwNIxy8BxFMX1+1td//9vzKVqMcXenfIEeiJNcg
j5dcE/yC+9517JxUnhwYXzb3u4wFENxx0RnfLltOemXycwdD+FR7CRQEc3YEnG/WIFHRCqjNq7Bs
Ujql0dyLViCfiYvVP+HzTIpoDGWdzaNoRooRUFWpjW5EiEZa0VJwvxActxGk8AlZz0B0hClXq/P1
oCMu2v5wrqUElXhxoU80e+1grb5jgdXwsRv9PuqCGV1HLhuN8QtthbyFjl884P/R+vHKKmBYrM/i
ff83K1cOOZzvB55Kl2cvhwNVcM3Ran4C4ccJ+qLwGVN2cYvvp/sSWi/XQd9WPHLqwtLZZ7WlUprz
uadtGndnSWdYaSlUb0hph5/Cm4HlhB8aacYRRuf2ZPIrTkrI4KSw1O4VnkvMcJucCRldUqNglCoq
qBuZRhrem11n/RPAdej2V+qLe/s1k/7htrlh0JhkxzC7YwM+BkqkXaQz/2HL9r15ss00hluEGFs8
9/27tzjeuEYWTRaI1UmvfEP5xYRM7mILYJ+ZSv2guM9DIjicXYVJs6LiVvscsYs8MaD73+LH6vHq
ozb+HrxD3pW0fgGCY599mRrnXQYpMhQjQUKPdRw6rsbiAj4igiTdAQC0J3g8LcNVJnGQAny06+6G
/KbORnVKcvJxZU9xqapL7JP76jMfPwt05iLEqZipFBXGV2Z3CpSQiYX9XnlbEgZKe48gD8OTHz5b
miihGHCgsUuFmBZ4b3rg4wgCrkCf+c/eJIIMwVLhDHSlnK5MR41h+SJSzkjRUyr81vGPH837RZ0X
iLELM7BgViwybMmw7O/WDk7OmhHZ/037kIXarhBos/Dq60gAhYQGSdY7TNPKf0zEOxqMJRgSiPod
tEDFAZQYMZXVJJQSRVDL1Se5HdOIn7D+Fke2ipJQXbnyldQYpNvqPLRSVc5FQgvfAkBERDuI/4VU
rrk2X+qc+YbyLuaMJR2K3FC3fcYmDXeNNuYeOnuV0U0X4pEPfyXPmJiOIA7KwHfYcfPUxzjMoHCh
nefDz29gCVMkATdYaWPl7K/a36xYaP2+Uzp1eqCecqDmmt2A6Ak42rcz5a7lzWOlhU2HY++xvRZa
aWlsJ4mjUGmTwfFCi/8nhU5sLCPKMgurFc6rD1VW1Q1F9107xKPxPFjd2xnxd7mZlQ+41C1aA/Qi
N+nJvBObUW7dQVZ/p+A7Zw2U3P/Z36o7yEx+CDTeyhDc78yRsJsK7617gYS32XpE9fRtqDXRQKqc
pvy5cEQ2MSyybI/NAp8GOoeXFZUN4tr5yoZFu5sCD0UOPdIZJUk+cJPq03c4qMfTKYfBJPXLeyNB
a3gOBSSE8n4lpeY5qlsKnUzQyOW4ZbHJdKcVI7g730hXBa6kEALVWUO+xJYQF2CrcfJ+yhW7rfII
X03duYtqvk13p08JGWh+zaawcboAvNarjOBxBghflhJQ4P0CmvytMTgQO9LUDl1/204K4ZZnn567
ygp7ywgNUh9WA7OVxxLt3ja4kGYAmRB6EqbohGz7+xr4/UwNgGH5pkGyMArxCyR7zGYK56rwezIV
FSXAXntkp8eWkr0eqUm4P9YRrxe5rEj2B6AMn2gEFnNgUCxgkHvvtAszi2qcUQrAhrCvVCPdXoHh
OmPaQdwy6FSF0zC4Nl24dEHHDh36uelBwLXLE21k5duYKw/KFVKWAhD0sxmKrSYnenXPqYTi0QAm
T0cohaeRyBDxE+1XnJdWYNhWjZ4h/CzKoZOdq7L7590LJS8guN7RK8ciJRr6o9apCxcidxN2GKE7
iOa93cRkM7HoI0HiUF0/LhL4j1ucRhDFtTqxHfmaDvp657vurXPXh7MV6ZOHz4IOZMQhY4F3hCGl
fD6mHxpsfh5IZ7PjakX2+g+bBfNIecHaXgAZxDt8y/cAzEQKjt10sFwMJivj+UzOiYh4imFvkmw6
TN52FiCX/m3bo/huiYvHy371anXPu/utyBqzMOxjb5WLFT8knBEXx7/p6IPhsAZXB81xCfWg6Kao
9kMJEpTg3LooqgjmsA8zuGj1VDizW+tTPKd9kan6z3QfHCsEYJ3Q+ge7quBMC80XEercHVbL96K9
yVCrDAB8nyfQDlMWUES+mowaaSxw+DutXsV/ccaul9X8YFqYJtSEe8wVmNzrUcTik0WLGQnnTSUz
8We7+UnGkjHSzXx0o/WepV3ILbZOjwVT8W5UHsbYImX+o4OuKpKdCoTsCMYXMXZTn8694V5QpAIf
FNGQJb/S//lEQ650WW0xhjXI3kzqMxitcSdRDae56d5r2N7zCIB25DmczvUAsm/UJP7hBZzdrRi8
FTQNQbrU3Kel5rysJEf4WL7tZm98NlA8O+vkn3RAmVYWIMy2nCZDKqaVJosf9FZcrFPI71AD3yDo
SNgjmM+Ko+O3M97en8PeFtryoONTGA6M1+UxvcEzAXNnSQL9Y1TGKwzJxj0Sz2pmmT6svjO9y/LE
9wCbgsZ7pKXSpAiqzWLugaqDnRzuwOFAgSd4wK9+gVVZIHxhNgATEPThR3dfBB6KyP45CCa/USKQ
F5x9S4s0yJqo0h6PsANNyyUaNdHoCAlIp80KvFZdXTeiio7aWIqeF3bfpozw2xDacMtD7bEqzMkd
ZCBJnLKvu5lQv0+bHx7q17SaDhiqgqJGtzPuOIeBU8/xPICx2nyNVEw11ZYxZ9hL+ha25qbgS86o
EG2ffqQ8a3VrQLFhsN0ENDcGfbwbHEMGefJEgAGI4v57/okIg61dTMGvLBT8d8Pn9VcyjAOS9snE
zHZpErxdckLTHzQTivB2bLb2fKAdwJ6CBjv6k06jYPIgOo1xkuOIZrk832k660+5IYoq54YXQH9N
2kx8zHXnJnyoBncEKDVckGlHbzCrMBv5JQK8x1WZWathOKP3VsP54wnzHvsIDnweZfkCskDz6K5g
RPfu8VUQMJht6kX5/cV5ZiBEXj4H0iYfhukAy3hv/Jn6KdYLY4/o6w4mqnTRO9YD8+dRkRBPKO4P
aS54gqi6MiPrp0vBKGYEiDHbCNcfJhYFQtlrQ/u/dBLwLHdZYO6IXcaB388dUhgYkSeJa8b7bULV
u2O3FnRFXIS1BKg32xJV9zBPlfv/t3H41Ga37Yn7eFAq9MqIIyurlkKmSKorgSx8XxXXjnOcVc3d
4cUBeCc6CTKF9sxnDw0PBPhr4/U8dDzsm0c4aVOA2j3bg1vUzgmMIMCQbdKl/gEzxa8fdzsw4JjP
08D85AigX+ijkejN5AqyOE/+T+kEe3x5boAN7MbC0bjPBIrm026c215OPWTRFWlVz485eI5L86Je
4fIGi/IwGj5Q0O1Fj5vQwVddKq5XT2LKoVxk6ODe0OD7kweEzdbZauTgqU1kMQbBIoAG7inVxBGP
1luay+iaXKb+NbZZFlJOEdXQwWkzGRM482oKN5nL1hrXIcfvDmvCMiP+TkvP6ff+nMt6uphAU3pk
ZXQf2ggvITQSdpFlDTsugaS8MYTwSuPuFLeK5Xe8AzF+BmlIeBOlYrjlLd1oxZuH8mSLkO9Nr/AK
ib7tWW5PmtH6gCU9gbOdOl5rVDlmJcd5K7GX9kc3BN9kvjcZY570iFCxS3qJdhNWWvA2WLS2UhTf
DICEYxZCQjkXMN0uf/gj3DMNpHvt+hX0z5GETZTfu9m2oX+JWOTtuDtCul6HVtD01kz5jG0LAfXq
p5+3TieITvR8Hjamit14Vd8KkmVxskO/UAJOhcHM+tDiWaKoHibKF1wjNSM3lryjAc45HZL+leGy
8U6eoyWayyPRFJXPLMv+bQH+8MDQ4oGfjnNGgwYG/o36yCxm9/jqit8hpM4kQrnBfjrdKmc8VoVj
S4DvhnAvY7TvdRA8dI5BWSEQUWjxymGBq+nW/piORKoMOdkmCnqOLXkiuTS0QXPMQsyfF+dv/ZOT
FjUYH0ZIjtFEfkTaXIrDH5x4i9l/bkXvHz+OieOK1NMsZdYFllQpl38jwAVG0fhF9tbFB0qaWWbB
Q19yAmn34POADNATs7tDM2O+o6eRE+Lt4pMz1jt0x2fdAawdl7ibBziiBLwE23z/+j79oOXUfFnA
XSpRwlZcnMdyvrL7lJg/Cp74Y4RLUKoOtkyBDbUZAmIc8ECkxuJxAJLAybqjW3YM9+ky2KHuuzUX
r+7e4fHtVkZyW3ZdiVkga/wMCKmkTXieLXgmlIGtFi3BzVKaBlH4WL94A3uuhzC9MoDdt3cUtDkE
uvq0z+E+MnCiXCf5T9PN2i3uC6B5ViDGt/dLxAq+u4Y8x1cbh+F6EGZAZ9s/85YWcn5BXMS5Rwaa
DelA6oDGlejzmkutsVVc1+NJRZ3obcJMMnQwzNOTunVkm0dZmOAzNSXK8fRR+aWON9xQ0RAFeu9o
RUrpxQnvvWqR5pkW04dW7nsLnm3Izu3p6kNPYpiL6+KhiaXdYcejEKYdDv2m6EU6kmbXdwhJtJio
5elvuquYUDDA9vkYylfeKoxH/0QBmCCkqAuzNk6XZshpXLq464lOzqL7ziFGG7g094A/X56ZeJy4
2Q9V72cS5+3EYrZj3cJnyW2tbnNdca9x/wW6b+pMmlV9sFlv2siiUiaS4h+DDCCd+2elePTSNglb
zEGII1FrWHiHNb5MmwOZviArmiV+WIe4CLCvLYN9o3EUbANWlgcsG1TQo3Q2kvXXtAtLTnEeR5rS
Sg45ZZ34KE9uJC7mZ+O5ESYsC/uZBm+uI3mefr9Dk1vHozIrRlSKAqlbWMCgc3aQGk/Dv9WVqlnT
fpcoIVduA6UsWs9JzCxwEa77hxZX9SoXeVci4U+Z57bMBXxBWzmGcOCQqXay/ZAX9XvxHqy9IrtT
FTryULMveKZCfQXUnHhjwabH2Lb+Yh+Xve2HWTxE3VKjNhtQQ1brCV/sKCqlNLVCOgUFSTPqWb6U
yPW9YbC5vj/bv+vWhyJePZVfSbCUPAChEHY28RIM5cd/L1EYu0Ie6siRRYZseMyHPF/60v5REXZS
HyEg+ya47vjYHDuUP8O5jUiu24MkKmYGO6Au7/ugPQz7QaB+WU7KkFIcrz05IGxsVtaF+g15Dvhc
MNddWWwglCFUWiqCAzukbbb+Fxc6mhVlIwWT483SrLW34wreJhr/DgN/HsnTXZkDpCGJ6wpnQUtu
Zw6frzETtn1xOFggvFofSqZcUcwROsHxZ8yVO6VNbDaFUze+eW17R3pg+B/5T7y8X/vfMbjXtt5V
Vr95cJt0WEa+INitbgsZgMppveZKQ4H86ScMa75FoYmHZ//Cxo0ufNSqpWfK49uglKMF5TMdLAhh
tb5uuYNhWi8FBj9rd/ijQOHNEk7DAKnyyMil2BLWvC7XlVVz7dH/egCWa8IsEXJk3EGsa0FWja6N
30JLuUkNlh4pYY0fiXA4thdvbhzfhMbfHitT1CvcnlVJFWnskjEZGgXh7ELWYrb57wf4o/d7oI6H
rLzLx1WHDKtpQ4VRiRbJZVZc0niIvw4vWXoKLStNCcC6o4RwX6TyNaEUMIiO68WgbmGNohXo8/Uk
6nB5UKOHpr8NtkBlKy7wMdS6mj/Wjtj5pCQI6V7bU3gvQpt+eWszG7cFeveUlYjRyRU8K7nn40Lv
E2bvTV0ZVNukYQrPgHquUVFDLZQeRSul3EPiXyJbPPoK7b7iM3t6Wr5+y0YUJjlI9jXGX14NuTXx
pMJghE/sxoK+Z3lGKuMx0wBQz+wA0fpnAbkjlgb+ShuNkJ5WbyNYLSA73LtKIFdVOO+Jie+QWyAt
FcUJyiEznJnhOSqvWZrTUNv5trd7vRHWYdFcc1MDhhMV+GfgJ1SM8ZPEDFhMY7AiMx8JQzS2RTqV
gyDffijVuJTMYM9iKo61Zdmrl4knKc7OfjuOwivx8D4cEzy0jCtOjgCloQI9+pcC6TOqA90S7e3E
ip3FoDwFAanT0ra54sN4haP+HYAhAqaP8ECE2ImaeS2V7vqOFhBigIZe4EoPwPIjvIEFSgno06GK
RkV/SHv0z2kYvu1nZ/mIXGHo0RocHTkuhtpQCg7z2Ny+B7vkYMxUHzq0xPYZHaOIK/kSvXkBxZLu
7/LhUfgt6uJpWfSjKClxyaW5ez75dGzGHWKFP48UIsWQynhiyZqcmHdvgjqQf0xstxGZdp0aZSZI
pepmKyuiiosQS/6wWYcHBVUrfKmYWuoLG1GHGyQKcI2nON1xyEhX1mZ7pKdvSCxXOEt2yq7q6Y0v
u4fDmXPxWC6/09yZASu9L9bVTuClOm83dzlxEpzDT1kYAC5mtnRhQfYNDDUVYDxf6k7qBB3iLY5Q
geHDU1IL1LE8erzV9NnK74tGISnk63p3ZOQ5ZJ94qmZ3lh3o4sIcNiNVRNrPG4+Ik1k2c5XltwJX
a2X3Xo9O4BSEmtv2aXgAw77+Ebrl29VO2928BbPp/0gzXN0SDCyzK/Has4Ppu8MeG4eR21uGPW67
d/dt41SbvkVYxu0eLoakf3CPy41mXDRQ1l1LtxEr8MvzD7ul79yKIwplAp+gWgcvjwJxqCBgizDd
pqj7pIyBM0yjGBPI4wps4cj8y+r/B3PUJ6r+aUr3RdiwRN2/vzdUYUA3rE3wFAgFdZsGViPJ23tp
2kd0V6HnJMDrxjBqoSzxdHzVAjhweFl9u8WolhEQEhxC+Z+kjjFV2kaKk60i2p2tqf8p/+qN6O6I
txMquFuOWH7hS/QwGRe9n1yfrIcZMHj3T1Er2asRCniCMyc6/HDtQET6/fKjwds/V420CS7saKeM
1JNkOJEPA6AvnPF+j8QF/s1+LluYo0JSlh72zWlMMH/0Ny69BWmsqTJBcfmdXSSqjGuAB5bpp87n
jaRjtYfgZSaicRz0KF7nex29VJwcBagHV/LwsZt30uSR/75RX88AHoW45wJ/Q2stIqzvC8SF59MD
AgC7ncK8+pswPrVa/owlhlWEbUEgit4kVSMI023VeIdoeVgxfBRTcw9HbtQhzxWr6SAMwiI/DHZk
uPXqZoygs/QX94M0OA0NcimJyfdWWhPNDp7OoSPvNyzmjPwLOuRyW9ZMHIXiNUKe6Ghtv+jmLVFr
1JQAfVHp/tkXIRyWTJ3BCT8Rqhx/omXmilCOtXbiMOKkn+mf0k0cC6Os3FMWVly3ObxMkEy0HX1f
6nr7p/zuUETUa0I5i9Ztc1fbz378oYkqbjYqgCDFI3P4rcxPHZCtvySFmOI3PBSiNjT+pwNyBiJ8
9ml9PTHTWN6nGJs2CqFON0hLhCDLuGBYGkdeCSj2FXTBTOdpjddQbVz0RPIJtqJEBgnBTfLtL13y
8Jzp9AE46YCK/KcazFMrQHBXBtFie8aWsF17KzwyoB710m3CJ+2PfA9FDvBKStSQEKVY9WN98Z32
J9Ytp1SdacuDOM7LBYSlAjLQEDlI5t/lAe4CNBMwlB7xNIqn7qc2B1yvlGNePQbGp31UElVZPuPJ
vaF+mJcJixNMFL6kQz4XELD3IGw2dgV5Pod2LIT1KW85N7qI2yf1taRxPidgvE6SP09PXXQDE+zK
K45e1cQRhP3YL2U/vLOcBfJtO7UT2iUq7n6X766ZvQ4mk1LSDTVfiZRH6RgY0D8tsagz5Nx4F2Xp
9/PYhPCyNp+oYg+Tdei0C/K0yb60GKTuC0hclWz1qw+iP2FpU+BxRG+5dbLHIUWdlJlKsOXmeHFF
YWXdxCy8YBYczkRlbsUueCO+XbssEqe81JA0vVMxtleySWmQd/zD0mMj5K7qyiZaYM3++G3DqSa8
V/EPgsaSWrSYwEVLRJ1S+2w9EzvnUsNuseK34yepZtRBHWJoJmH153dZUwNbVLyKxHcJoZLrk7HS
PqBMwwNlJV0eIMU1H+E70IeWBeg0s5+JGEHoewg2bb2Np7aurqKB7levaDoePwFTOp5HvQFa60jJ
rBS9yceGBVsvUKw4uHFrW+pJpwOGmrSSiDC8vj52Emmuk7ipsCHj3/tRMfwoG+Ev6rWl540gkwPj
/8KIKFXiL52wFars3vCkXtthmsj7sydKNXNLG5QPbzUG67o8XjWdoX2wQkpbO+PoolS+g/f/U+yD
x5dUGKpiRP054mE93rlhVqNbsYPkSi15mmhvjMw9bEf5Mf2VSLFXPkjhudJOvfLFucVfk0Pib6gl
lszofEcPUQxpdRWRkqOhlaednDCGwi4uz3ywiH6DNRA91FmTleYU+aICesJebzATwo72vRAMxN1A
RZUlXrrt7YWfESApsVWf77VAR1AGAv1jdUJr9D2r207cHayx3CQWWESUjJgJ6bZrt6JxMOtdm7nV
ZpEQjecqX0J5l9NcI5/6ZY/JD1ywtGhNeGSEdoxPOGFu9dtelVqhcZJvL66su3ApgWa9uZRbkTEl
0vgDplXGbIOUVRi3e+z7MDzhv+I4mioREHxcCcKU9WWMo0BscrqSjWMi/EFoPG5imy4ro4gtR0uz
ByfDWtO1HhjXt7w55BKWckg52K+dwEGy0VYKnJihPa8rtmulUBcnYHbLe3GGWHbIIFCDvZ6BtkEh
+cmMUn7uyzFButz3OXRbNs5HtuU6dz82KSOzJBlSXtdlznF1Hsq5mpLycLB8SULCy8rF/Q/xEdBY
5YpyNthe4kq/wSXmdidrlTKHehbKNZcTdVD2aJbgOLUA5Fa/I9WQXn+tXGHNBXZq4nRnWon9ck7r
iCddHsRqW9UTV2HRptenzm/mUzYxYvsQ5OTfwotoDyiPCS0R3tpkp5wHxSR+2jZ0PkR7dfDWltw6
JahUCw7D5hdJbKzO0SHV7WkKdCNOqhbqEE/X1OdZFRbEVbJDNnQFDo51tct46CUSvJqBp8IWlEPh
0mYKb4gtNp7I4beMHNMTKySpjw0PBK229eYxvuckIUwlqY0i0My83z9HOeNq4VaYc9jEhpz0NFMB
pHl7tVp4Ml55TmYftms0t9Igyt1nY5bV0Z50/NTdg8RS5Mj7GKEtk4xjzPuQ+97L9yBxd4870l5f
8xwwOg1ekMWznwsdBktnrbK7da7IOhedG4m2acjzQPdD6a9FUEH+SdkaTwSpnEcjzqoq4BWVLbly
nUmFGaEPmyfSizRKobInCdW/7DdnkvQVRJlH+23gRdI20ghA6YVukKhshXRrgcnat5k3a8spF8yN
7JjPg9GUOY9V7PonwdVQXaY0X5nnX0kHymm/86sVkDay9aLtuAxgzqi13BW/aAP7pv9YLzYsc3Kq
lwqt0eNxztF8FPRaCWljgibHlrrrl/977xPWWC56eJWBHRZlNmpYz5IDLNskq9EJz95L4rhUnG2Y
Rm/9A5p+D1RHhIHrMvhWpthcvJSxF0bMDG0CReRgH7O+Uaxgedtqtr//CebtSl8bFE5CiU+FUX/M
2lfuLg3ezRNwauajY+CWVjJ5gUNLXdQj9WDNvXAFWg5mnws3rZlWWrdzvuTtiL+jNi/uoCOiqIFI
+iN8exl8/QmnGdHitHW9s23gSjW3tAwQrST2Hu3H/s5HrlYvy7EtRTE7bVmqSYZ4QpmlCHDjZssc
puE1qcbBFHFV8CBQlrX9Nj3RhH8zdz5KIUvFVIK7Nsktd3tCLVNWzKJdbiCqjxNnrFAx3olHTPng
8hHwdw7xbo2ePsuSdCbnf6QlsjkwtBI4+3I1zu1S3Osg/h09h5yL3j7ktgAoy5XVQEsV13cUUTeQ
nzBFnRh4PfvJ3jivQOSPKBgTzifSe+RRGFvpUB2vjupNqtC0owDLgPooy99IY8rcavoBwWKt0/jK
xumInjunmWJD2yafhpWU7rb9L1cTmDzorgsRBwNsx6SxWiynK1+lPqAeFqlkmjQYS0ky0KlVpwpE
yb25vt63YzrFRYI2uU/gDwFpweDsAYnL2z5sBH6yXu7pgCnPABJVdAQ+mL89YbLn4nI1vAz2BWJy
+YuQhoD5A1kj7CA+hlI5yua9QTOwOzV/AX6jbuv33W0pPSX5dp6J4dkbRMzcv5AuakoEN+V4rAcd
kH+7BSJ75qc4GyHGuOMlOEcbdWYotj3Un32bAEQR9vQly1BxwKlsea4AbmEZ6h/N7FvKjoNJ9P4M
wf/59Sv4ILk9W+AtiuZrzLtgeKM/jlmMOtrgPrsZ/cAVNtgActJ4AbU8c6Ng+5uhZqwk1wzD74eV
p0aNi4D4otPVqBQ5lg6fIaaz3xp3x+Ljyj3jRQjm9DMNjyJsSxEumohQtKh6MYOfQOHBNHlxgj3r
dxgsjIwFesRO1uJ5oshTbmejBzqp7cntuBNwu93rxlNZOh3GTmfsLUz9RQUl+vqhrWGp93xt/0sq
BCiU63ejZIFxDANtZ+Z1LyZsFZrHUwY5NllsWj7XoKkoOI4MbHBKefNEbuy6eAcauSOauvVjOa8f
YmGN5cdN4xFJaM6fTYD+D2EWBaUY6BBgwHIBhdaidx0EottUAVdExQ5ShSd/5zzJhqOQXZZ4WHBb
/eqqNTqaiMaiHPIpwOulltlNmX43GNk5Knlnq1wT3Kk0hzYEjZvQQhXl0txQ6typVqNDRhgls8mC
cE3abBvGcq4l65LqYvDaL9GmEasx/tbhdgTt7P8uUQBFANofx3+N7YGxxXyqTS/dlMNBYNxsi9Ac
McWy3NcASOW8qOQmsSJUoUDrwjXlL3DCL63jx8jNtRGNy88FkZJYWy2t0Uzk4krCf+Nu9aSMIPL0
AyabGxwTY4lDjsHTNDv60xNzQVYF/ox7DacoircBSGVTjcVJ7eYXnXJLnXqtI5Blvh01c/zCQDnA
X7rvNpI3nII5zFm3ejpMrCTH8l+aiXgNkUcr/cuTdMSIlZHWZUjylrotcWCHrRdzZIAqFS6WfsEc
AKRh4lQNuYsJngvLz8S6kOFYkWuVgnWN2D/Yd8vpHhj/FK7Ye1/1ZS5ERbRQvNdwQnRm/y3oi7kS
hSdByLHFkxJI41i3AKk7QEYHWYF+Pyg6KogzNvtkVhBs0EDEhAbVFuLCY29ecLUixXUiutShKOBB
JWiwW6x7N0BabhYYthHi6Xa+A9CjooSGEFQtnIhSpiGLi50xwQ9SUt8T+qiWQ2MzqxZd5nOBqDT3
6tZMeUxqQVDmI4pEJVHhtydBdN6PcXBixjkOxT5Dd/DEtVXxkn4D2dMIvEnONkQL69/cyNX6cigb
sz25v0CuAqvkCbd20IZzvYrKDdytlK/cLRBxThEyIXXMYxXZ+RJm2ZuFQtdxO9rF5xB4NIUSwNST
fyjnUPRpuoraqf/i6xyLYkX3Ou/YrmAaHV0ww93+/RZx6sEkveTXrkdDvQCxJ+F3RnI1sJLk40g7
Q00+b3noxikGiNTsS3i/K6sMtmsq89rdmK/Kzcly+wPboiON+l+uQYL/9zCgGhhdoBxTDHL3Sliy
wMJDGEWE3Hkf8gHXcia9rGJ6dOsahk1m75oH6NKxxOXYImCVYPenqyI/Q1LByXnZ9FOxNdOAE48M
Qu18Bo+/83sD6KH0RhoQQRVaQ39bjc0PwLIBz1OCjVsEd1ugubKK6tx4BE4xKBUIRbNB0g3OEM8D
TW9krOvuzjqzTkwTSBbzf6STsJRbTVSEx4pXmE5HI4TfdASosTrDsamimQbbKRTemtdC+sVKhBIc
o3QNG3Nq/0RRPc5Aoyb6UlxTCucmWq5udHs2ATKPRoweQGriwjDpI1V6h75TOCzw3FAXZFNXxyBM
AtYxOSGsjNDlV/J/e3oOfY2ST3s+hNIOXQ8459PQmLPV2w9X6f0amPStXnHsm/hjlGhn8ANLVbmu
iaf1KCB2mEs9pOT6ldNzTe4xXT4H9v7osWNYECnJ6Y1xLzPtCbWuqOHHAZaFF0b3WVtgoTTCJM4I
cSU58MWRnrKyg796l6SkngdKvbOqwcbjg3+zat0Zsz6lCmolDW5CF/ZBQ1Cg3MZEjX5F/0dq8mOZ
hytVLMa8169imq3b1RgFmty+4OxIvRR/epBxUvDU/lqNRLz7yEm+8IqLRVrgQdawos0ZSAkGBY3s
4suN2Ms4XdVzEh2C+9wZDTV0x2SoaPDaXUjg5A8974dK87ikeVcM+1ImJh4RwR1ySNtTvDheuMgQ
sJaK5RfRle2vXkuBJVCMZ1S/5TBhYBDFrJbIwgsPJv9svX35SqKQTaRT8RbU7PMoRN+0benvm64S
XcLK1o3YvFglRn97asoKg2a8AgEBA6BMFKNhufo3WwjOxTSnkK7g636qwGr3DW9IxpxZKCDtwfXx
VLmFc6Mx5K8/hdaButTplga9GrxkbOkY/cPPTYwRO9PmZdaiq0nfgUibHsXen4iXUsa0LtOLsjKW
Lp4f6EFgVPiBT1VEG8rcDsiJquatn5RVu/tzWdq4bqDwWg4zpAWjNb3D8Yj/kl2wavnVBtxbW4H6
FKLJQSEuUDF+XvpKImF5cXUEWAqycKIg/BuhxtYy+K49437PWBH39cJF1Bn04Fvzf/leXzeOLUdP
4Vkx/bTjiy8DdzQrhXxt6whQkpzM+Q4lIkTodhcXIBwxRRmKDJzjjD3nNI8n+VUpDhDu0Y6KwegP
tUOLqZTLCveRTLT49JjhmTd3BudZx/lh97UNYKdR9xe9wq3GaWUAq8ZMtszQXNb94TrMpysc8a7P
H2gf6YbgmtPbiQWRWrt18HEpilCmUcer36eQaxkig4ITp/WF6o911lTE3ETXBstDnkVVJkr7Poct
gxTg42U6QGIbdm5jX28aI14ns0DWS9bSdn7SmcVZH8jAKFHTPX48n6aPMHSbJ/pDrB5seSFO5vt6
pL1nl14GE+F6Fb3lyp9GZL2M86mHTlk4JX6XBHtuZNr/jrce4xZBY6ghwssk155V/ccBTW6hpU66
Z3IOUT+beCTMzx6jUWd+HpFRr6Ey0I9bOr318IdcwVfDI+F0tAf3cHmT3zZCy9y/fQa1TJZJuJ+9
ICCb1FX5X2jCveHYSC0SV4yiFO1u7ssUWEDgp3cEE7KAuyZpBGJvsIMNLVlyCIAWDQ8LzSGdt6nf
H9SFdTBdJt1TTZOTNtukyG7XlZ8MnAfgHS39C+hvVXWQvdoJqcDP6ikixZCXdnT1UqHRA4b290Rz
+ly/Mw0NGRRCCOz5qrh6x1sLdnmCq8Alzkv3TX1gEQNWFV7yUvi4Agwbp1Jgv24ETh3Nh7KSPLrR
I6UyWTPnldEOOuzNc0PbUzQuK6A1cgB4xnKhiGKbfE1dc/ZMFkDlwtvPBOZPRSVgMtFcPSI7hNjS
0D0nfE3Pk304DV1CzsnU7hbaZivmuHVAani18h6gLT5EwFPZKBGcCoS7REphvozLpBy1mDVBQB8U
q3nQCn+LXwEw4RoBKx+0LOI627S2PwOAKgyZnwMR0jFQZGNlLyRSRupE09f8X0eTgmdUlgs5AZjg
ypMdcuPFuHcZwN4frILMBJ3OfYkGKCj09gINvZ+NQ8yrgXZpDQujaVDFmQyXiVHIk+vIoxthIEjb
Mrrr3fQAITrRIbdqdTmB4rIsz7XS7DLvwtAEpwiT83RlwRd31AfXsjnbbMFohvbUGyxP8Z21YVkn
HHCNa1ryKnMYYwozB+2z5+gdSFIpKzKXYSRu+Eli//u7L6fmR3sMK4EF3jU/YhnOsnYw+zzhpGS8
HVbevIHO2OtvghniuuzFt6eA2ZUf68eTd6T23oakcaEh3oKcS8YIHDxWTwQPQ/zD/UKFEiO8GJy1
kVywEKV1byfa83h2ksjAj2m71/m8oMaPgkcrbSeGpfoiNSWGgvivRvGKEeF8LuT9LmTIghy4CLl2
24/MBaHoNxGl76qJRte44o/Ha0T9+Ue4XR7Rjeirpc9RR8sJdyrI966CDzsi+S5Ngyg2fnlj7oNl
9z/HKQmfYSmJBCYVDh4ZjI7nf9uasOjFFxs74S0n/HBqh2pCU7e6ygDhBqkwh8DehXDMtckV8uVR
IaQ6oradpJmcZtnLTt6tMY1og5c/Xu4/uwTn2WUBfk71bIBQ78T700ESlPdDeaWk01Y+yYGrqLig
ByjZKhb5X9EpwHeUO3qELrE6T//H7W2+tdUDNs+AEjstaoJ6Lqn+au7Y+x+zfjqc1kdw/kXmbDBW
WM/LdzMf3rKg8Ba5tDJmeTrXilI8iQ3CbMwjqgZZ1E542PiU3u1GBcihOqDfTGSjByvGrtL997oP
Ro4MS07Yo8PxwvfOMBw5kw6zFwPCzi4MUvcfG7y2lt7ZpZPfnSk0HZXAx2O12oGOOC6TC6ObwER2
eIyAkKlMWKWZ4GFbmYgjyFLLy8LA6LiiPdj1g85G9zXUBePvQR3HY7U9NbOimaUeMZDeNXj+ezdk
C0AQtPo5YVbzFCESZOfWF7wgH73odBNlry4af7aKxG9117vT0Yhy+KY1nckN4VYRf/Ba+r5Dv3t6
5bcvwMmQ4sqQiDa3KVla23syq1oSAQnENtkU0nWwxYmXGHzA2nBYk0VTxrFMbMb5tShrGwTu9s9S
hkkrLBoC2VAhYN+SC6t4mTi2/F6qxkEX54FD2Q/laC4FmfV+22zBFUbaHFagVUiykXJ5gztjeiI3
oGbrDvdFk0AGqHoHbMddnEMXcTSVfYJfogFrLovAHwJmatHvqHxrF7RnVxkJvmks2+jo7K5X7szQ
kbacL42qg6FHpbgehun3wlSeqOOv4wfs2D13F0QgVqkpKQb4qAzKR55mv7rd0CD8m+kaOjEqWODc
qhNZRTKi5J/DCiOLQ/sUmLg4Nmk+25nV6TOcWrj+XWFb6QjDACsMEUqrW+3TJAaD75RS1Oo7wc0o
GTZhqgW2p5tRHmroY+GOXj/DgAMtiKzlLI9uOlrzTB+iyx1JDTSSC8gheX+IsMNyHDMyFM2bx0jD
ZnECNKsuYzM21c6V3rcCa/6MEQ/K3LgWjjeVKzs3U3fuCc+37cXcQ9xE+XHrgW5QYPBsWNz9mwBs
NxyQhUrJW8jQ9KbUsEYsopqz+MG5i2exUtALoPVjKMaHIrivPuM6Dem3+l4gUGHuO+cEyxBQhixh
19qPsaob+BxoHeouLP6lfvK0U38B3UfOPUybiedW+c7CpJyeI1zaz3DhIU0E2rN+T2parWMI4x5F
Jpjf3cWREGOfdeMX81sT4rzoKmxjfphGAGbfg0XS+rmucwLeipPOBaGgMDqwS9OX7HJ9g1EkD/jN
0O3FI63CBkscj7B1ZAzD78sy3Gq1vuJRJ4XLjXfAZPUA/5BQVct5MHbeCCM15kxxGaAq1RgXxNa6
njF5ri1IS6Az4iqsV2+GvcZfjwI6OfU8kCNuRjnkS8q/MWf/eLr87i2Ig8QbmwNl3MmwHaO6aDq4
zy8sAa4+8Zxdo02WOTu/oJpkFY6U+AsaW/tm0+Ow/OAeQ/v0zWseeLb+Rj4mrdJ9Ln1jMvQsEYHe
Z7T6xeLYsAsVxvFRqNbXveQGpSWgzU2oYJKmqXmcoda3RaeUkJyIInEd6MfC+/q+NLliApp32c41
Ju361/CxKLlEccBJXrqG7InmCKTaDh7grjTRyFS0ItAZk+/pom3Y4y69Nbuu4XExw+TtLhcCChcV
J1c4BAAdA3PYvGdlbtzce8pR+e6uoUHfYTenbZth9FSw9aWTa+XJZ+SbXppriuGzF4Hc1ldrIMG5
a0m54GJjHIumpwCrWpgwvIPn36C0PEvuC3Uyhf+yGt+EhxA9RNnNDtzRF5xSH2nupYe3szWdklSE
vDOzFpffOinUhLjlKJgzgOgzzysk2U8gwAlbPp/Ogk6segx4YhnejOjAXQMUTTGWdev3dnOecjSC
UfemAYIFczf5dv6uYTYJiQ9i3JgdLLEc+ExatMOmDU2ZP1FEM53Mqd1XQLp645a6fxOeKBHWmFAa
OCZhMCcon/aKLOTArrF4wfMjSKcDUMqncrpaQZViNUImSFDj2YQjDip7XHohJb5GtW9GJraYl9/k
oTX+8MfzZMxl/edzXRugIJjDb1rQbtplSLF8cBZMIQ7sflhRpmTNvWFsfKJdiOoQH+Hgfi6yCE3f
+L8NwZ7BWOupYJfiUmx2BGmz7HwZE+izhYi7qxlg/l5RJIWX5ZANS19JoDkjFbDZYRN81MbDe7Xi
Wi5j2oqYA8NN0gKgvMXHjTaVo0attfvh/8rquwO0t2/od9OWR1+lII1AOKfnQfkeHK75IasRu4x2
JD7aX0XhgA+IKYj7nBQbDFqY99sQ6rs6P4V7RTvgx2vwWJq0AZkSNmpDqDZWVivJjJd3bpF/dgJu
pbl5TEuAXPcE1S+f425YLsj99nYRWGTom0inB4JOrcbJwt/akXdgLHgd+7KOpWecdicaX00/w0T8
31E9urQf+r9Fzpokx+U8Zi1v3H9O039HHEap0GFJUZG3VppcJNsv1KuRwBhsUmxLuKvfaVAv0aC+
duSC28RlY0gfdcIw8bn1elXrFK0KgakaEzfMss8XAVazQawIfNwl/kh7s55Lbv0TnizIYqrmmckU
70VPS0UYDQmn1YH3Go4wosjIJnn3TQlwSqSuDpgs+TFt3tkXBLGdYX5lLP4k0dA/1x6Dzz9mSRNL
GMLWojN9lGyKHie0xjHeJRKwhLvapUKHvDNEV/PwDC29pn0x6fRiWSnh/vAWxFi3zjkWO3b21mDs
DOOu4eeqU+VxWQl+DvfRwZazd5akstC2bXjM5R5iLK87uWxdex9pC3TT91vbuCQyarDpENd9YaxJ
GdMM1aW+CTuW6UqyHaWodILFU0TY0y5XdxxkcHaeG+fusFa2mmUrz0xoRfOXO49wGRdyIf4oyBtr
eP58447509w5OaLcWmvpWAEvD6fQrrswJOFZaS6KVMxG5O+ep8J2wvj1mbUdj9JkCtGSAlJo3LrB
0qSyEpys4aYFdv0VaygWV+VDW6W4j1uhl3XfQkPE/Q69kIO8YM0/+tHEU0DaIFfWZcJyAK46wh65
EpbxcHWx+vr+rjN7mBruTvElhCF+SeM8OCEMrN2toKMuLqC4EuT65Y3mueKa5Ztw2SYtyBv5+/Qd
LklrV94G8SHQlKPgByGoBfkC/nEKZ7V/K1aBPmBq4o50xydAx1RI3GxEw1yH8zp+9JguwDQk+QXL
rRsPfEhUaxMvN86cMu+0syFzMcTygY/SeB1K/QEOxiH6u7K9egVO+ia2k6j/1dBppajeTU9Fon9l
dx8XDAHMbvYngzRTbr8mGtM2kS04w8G0egq1S5f1hgxoTCKObVgq+nBUVNmJG86fHDZBUWDPnQcz
JDnJkwfozZEMyjZNUSNaWKhgcDR2XOMMrSoGJ7HXIing0x0V/RmVdKfN3+uz47m/FXlPjd3Kqsye
Ca2ysyPmAb6wmgzjj6x1cLUtQZbx0+piPMaLsQwbK6CzldN1KuXDaU7DnIT+i13hX4mw5eQGN21/
6o05VnQjeTWqjUdpIE9HMsmzRo0F7/j4cDr27etneA158W+X28DtARESyXFJdtlI0yt6c/NUG9u9
7Tkc0c4sFbYX3zqofP2/vFh0BEYXflPJ9cvaYoQFhg05t3Pd5A8+qol6cRtRdnTz6GZ46LjknaaP
2KWs7SYkMG3BBCO3glNTFk+YxOv7MDflcwcWoSt8MDbYvo35Nj2hfrqQzNRowQDQoimQK7UaecGp
yhGQ4C52JkhtQDNEe9EwXkce68+gwh84kgvy86NP+AxBL2Eb92xCc0kJG2zRTknU8FDumFMJZU3t
4lu2jp5DZS6hzzlVGxcWbmFh12CdUd/Dg4fXHQbs25LQO5nAjgndBN0sW75rDo5FBfAAqnwZSB2o
F24MfxmiGCZ5aHf1T/7x7lyRA36RpbfFUzdul7o8niBpvTYtvg3nwRLTtEsq2opOSYZ3tRyh8k8w
QVeBmRPpg45OQm+NteAPGw4a8ZkxJpRb3e3LipylPv3OyyTTJYg+i2G3/bKG2H0NVYsvPbopB2PH
JAgp2slBEoe9cjbflQm9wQ64/vUhdQmueSDZth6Q/fANL9XM2/o+xGeW9Wd4TuKHlLuMwPlMXeap
lzDFy5D5DBqCnrGj3yUx5Zx1Al88mR+DNOxI58Z6zmshkbb4V4w2J1D9gtqZJeypJPhxt/TFnoaA
5pbgtg5TJo5mdTJ+Zaqbz707k3+k2IaQ0Hz97AG/GhrdJW9iBXo6vpNJ2QkzNXvcILfm6LrYLCfY
LZgHEzaKzPPD77tsMzPMThX/Zb6iNB4Se1YBFVe7Zd87AZmwp3W4YW/Gn06+XmOE9OR3S+IOgBi9
uzKA2KTQgb8OlgS4dDuqYHkEc/jQzYJWxAi0aYYZ3TV2gzVCQ6GrCIjzWSOrtV46oVlDKsL2NR53
DTRuplWWFsaSDLtRJlwPkM2hrseD08liWQKJgWCZPDCyfm6cZG2lxlXPyzP8EsTeef0a44RohNrY
tu4HcQqtb9ukHRsKvJc+pFtmvWnNpNOxOQ1weP6uZ9Dxlw9VOSKYDvW0SHDDQVFqMEgCCF1hUJXD
p10zeDnXJcrG3R4Jrc13OoDkAs9SYDqbCaB/PHf/CyKFcbNBx20/LMJ/Jwg0EYL9Ba0gEW4uc1Ft
hJVuC+rz4DquKxAzV4C8pAJxYWjVYwQLUlxcxQ5L+Ufbe0hhxVKGohYeEICahyam/AJKgNw76Jql
2PJ77nAACCtX652tVwl0fydU9PE0t+zB9INsQX5z65ZQqIR6aWDJbKFewZyDHyzqbH3h/n8M4g7S
6GOuC7IFMvGS6BDKuxT0dqZ5zWMUVD3zjmnMKafE5qEJw7n2Vuv+cdkWmElVUY2TgccHJEK+Hu+l
kA/Vd+1LxSm+3D29vFS/W6cja8G4UyXn3kTMaN1H64sps89xfHcI8jfQKlvyn8XTTf7N8BeToUrl
8BW4EYPnLg7TdfHoUASs/1oeFrgAs86OH4pbJN7wf8loY7rZevvzgY1qKrWS9C4HkkB05ZW+SWB1
uXwO6na9w2gJIpzeyy2TaoA0CnrDsub25OZAaBMqX+RTXsxfswV5J+wo6pCrfC1f/D7m/r6SjBAg
F0fp5S59vyr0oI4X0dhWmKyi1mD5Z4vT+aqrvIckYwGZI9mMHBUu/cbHiUnWqB4VXdFWJIo/UiuQ
JWAbhJ9aXHs/ya+hAuw8vW9Q1PzE5DTxHiiyvI/QpA8PnMp1bigFsi6gKziandRHDV5TbSnERAAT
7scT6Bg2plxkYfhknub7/QS8GhJyHHnQhTDZY8VG0OHfOEZ6SfVJUbPNXqnlfcYY9NOn1GZ4Pq1/
iP4k5xTd3GrO0b6qt1ehU6/l/TWtUFCxMB3viikfhxmQ8iWzwXMe6e/noweaG9WlsGOKwPqacmHB
i4dEAukvwRMIPx9TEHRXYbOP/BfL3dcttqMaHNVQOXKn91rOYMOUtRNrnJmYuHZp7IUR54YS1pnw
uDR4S2FEKBfyjwa6ZCqmQ7NpklFJaQI88aYVMw6PHRz4wlGKKMdE7MKDfufcOL4biceecFLtG8uX
b99e2bX/Uhm2TjdKz9XYFWrzKrrsXTw/z9f6mENV0b587AXHTQIba7+SO9JA6iKkIMKw6eVUE2I7
H2haGE7bufevGUEBmgvG8X/+T7hYle8dwZkzE2XJhMLV516cEdTM8cE0V9DpCOfJNaKllOdxv/Rh
V8PgCQ4yRheGkP9F6CIVkpVDWbZ4MYpsmasg6YI7B9+WulJkDhM50T9NiBB9RpMXYRcwagbCyP+v
fki/Fdmuaw5wiZOzhy8Mj4Yk9jYKOWR5lTkK6rO52QDSSTvUOq/qyymO5euzTeK7rn2NI8YUQBF/
IAwcr+rsBRR8WdbbubLU7S7fJAAxbib+foFrobtHk5AejK3DFGdN+6JAEt9chO+XVAMCnkUyB0eI
H4IXkRY7t2sokFyj3ElUV5aM9vMj6vUYk486yQxj+iVU/e2kHn64+oSUB7EVp1VLKB302Qt21VLa
HXXHBWk3P2u0YGk71WsJbiRByTvohMA2ozeUydpvPn0jknDoVzefPWNgHxFiR62UTqpWeBTnhxvx
ctsOM5hnJ0RZk79l2ZJKhHj/x46fwXlWbbx/rF6Z4ip5GJIZhIR9sDwcjAxw42q+qZWzJdIK0SiY
pHX2sscz0W97b/y57zyrlkQ259va4rVDQDLO3pGXKSWzdct1cJD2G58isErmIXIdb0tmWk3S2ZNZ
8deLvEigia4CqiKXJxx/Xbgh8dGIl9i3tplUea0Yf5FGNKA+HNFdlO2EQuv2nN+GQ6R4avHlGr8M
TgV0kgrb0K0JpXM3FAB7eXNOq0NhGv0tG/4EA36gSOfwcuxX2y6XqM0ldWmR16EKeuLREWV19P71
/8cThR9C8Kwyq4jSfDxfU9bTP+rGLPpn3NEwaIkc+Y4hwW1fCaO3ibOk/pPDQm13RQ8DZLnIAHpH
TO+HuvzgibLXAJqqrXXNarrCQ8QFHTgGYQHS3i3jmCYU4K/P8Rqa2t2iFeTei0pNdxzygwkFQSy5
lHoEWhaKLHAGpYscw/rC4sX1JzLclLEP4/LbkZQ4jZEi8rcXe8z1S+EZvzp/YpNxUOvdnUxKzGqB
gwPTqzheNkK+DPMDfYY1PyOQwsAD03rhfKQA+9PQvSwMGUB78DUZS+pg93bx6izUCfe7ugpS0J2b
3z87w9bBEKGbD54Wk0I80ePGv3QSjRZk5RvZBjevCWKBH4i6n81A4yyAD2OfahVO5EcWZ9Fh0/Dn
Hz9LYuMXqxzOzVde4quN2A2KK9eTBzWVsO9fyctXhnqD2lJafdSNcryF8fXepYzbzpPaVTYHWEBM
6JtTV6dI5Iod/wy+0qrkimwi0spdvpl5Sk2P0ffs/F9wm2ufVZ89xr4dXejC92AXnoZ1Zw1p4vpE
BW/Mzi+VSkNVVIW5EcYhQhqINhmD/y/q0K4lpRwryBoPe09J5ckEQNdKOMxjKmvlC7Y3jmMtAuRh
SMXc5tMAJwPtx4MhwIGAg/DRhklP1lb9GU2KtMmAPv7jgZydl1JlDgNvGGR4zdgvIXP57UX5A3Ed
FP32fr752C+QQUrwmy5Fo73YH0GHOC1wVfBZuuIoMAM6Vz3GDDn/iZRHvKUOHIgsh3mopApjbwhF
tuUpIJwJPL0zKHo8RWYVR46pIiAIn5/uxeNDPNqzd5mohJJVjV/JA8LbcQhne0qS3uSjtQorxo/4
uL784pp1J8p0ARAGGorWt4y5oFdUP8vT4Rh2V/lxg7gMZXT9XMHgvUe+DPM+DY26HkPipsXL5xdV
EuFNGL7HnO3qqKBu6lesja9jRYqxX9OM0a8UooDG69R2Jz+g84rhQ3Gd+QHb1OaAv1+DkjdicvRT
CNSteL6O4KRLTKHTLj4dSlj1SPzqE9kgk0aZgMv5Bm3iPB31GONM8uKXSjivnM8S4mpeUOp9CsrM
hYDByxJlhRtO4S8bwB4Pxb6pi6PPaO8DskQSAUeCjf/rDLnbAL8W1YosWxFi7jYgPGf+MpQc9YLJ
Qv3PTIQEVZinHd8GSZF7dxchkb6+KW45zrFTenxuVENdb5gamEBs5H3dwaBL1zr9vkewte98NHwC
iB2BSS+4C0zoUohDow1/ebGnMEx3VWTcIjOSB//xFgRA2yRGyzcRkPPPDK9pTra3TA0MGTMRlJyW
2lMYjWQ01m1j9sEyVDCy5N5NLr+0FSy/AFKHvMnOX3CHnDx1yCmdHXMctoB4xLwBEYl1GKeKQXxW
+pXxFj+rn8mp4yG2qcOo8RKESwl/pb5vdE9ywKhc33ND8qsOn/EE9h6COXFX5qsrZnf88OeJeW6B
iRRYRbabbwSKWix5Rgf445+Y4lPpP/XIvaVmCMvGzUTzG2cd8deodNwMp9OerEh5uYoDenbrlm9/
izvIcaxnGI6gBFH+ndMIqmdVTJEjSCO3ENIk7Ux48XYlHX1IJprQPaCXtaqAom4mznGJq+6aym0P
5JKMqNN/f8Die4j9bBq5pAjibeChtBwZ9kStD+eu0uGKJEa0bJ36GwmffFD0DAo7GGeRsBJ7lBWU
cA+YBFdmGcoHvZg8moflj7WMZbAQpPAe/mFah2ILZfxd1vsckuEJsdXCeKKKAwg2VZnIf+iaMJob
Vkw/7EvxgB9PVZtb8ATtQgVSHc3oTQV5zaSwHpAo2JeKdayJpCuHgad2nG/FeOt1kabeWqMeQxrB
TVinqM9PNVWyX0hC8kTjx8ppwIQqtllPndGdw3EJcCwA5JMDOf/cWBk6LZTfBlEJLhMtcagp9/kB
/y8Y+qSEl6ZGr69wOYhxPCm04saaIFHg7TagTHm6ZiEo0RNH2wWZlgmTN0b9n+TcTd/zs2Mzgane
DT3p8Co1LWy3X9CdGrB4L4dgagelsEkDbaJirdadCEYbelmoKTY4T7XXhefuPsDXjeMg3aFhjBMV
4r8m7U/imfOX9e/OmvTMLLFZ5tvxvifsswYYQmwQGWFN/o05rKCT/tQWIgpJHYMqbw88aSNaxHAm
83FEU2jGo9p3sFM7sirwsfDa67NgMw6nq1Z37cGiYGPMTQkV8TKvxmNf7U/3iLO8XqrcQ8BErxDS
9Mi+cmJiol5rr2Hj0EnwFj3qvI1iQ2Jes9ZF4vGb6BICL7DmxWIbrRPqirarwBtuxp6SIX/nyXre
SVeAXWw8g4HUYWYLoIzx4bkJcxme4iTLpniRk5gLh5fG5+hD3ZFdMryPqR+1MQ3CYclJIFEXNXOq
3Aba8Dr35CWoVlPEvIlkmJzu5I/RxCoMQz8+DUf60tqDu+hVjYGv3HlRdRwt2IK5AoUH0HytyY3l
FKAplqrkqwiPH5wQ1nW//lW0kMTH0PHOngKOwmsH6CBFJyjYXFotkNnoraxsZqv5QrztlDtJUTvb
BwGh5PjSPNeNz+wxbYgga8HLaROf2JpyHvd7+lMshQ18St99ftVir9OWj9PoV/GqAqps2On+Erst
hlYGsvQN9gmqjGeN3p0C/UQ9immTZDnCPY8QVSi709uSAM+fZcE8WHhEfX1lAOMxk6n1R7dpATaY
zrrCHG4Z9fUP3gvzCtkFSEv181CX8GzfU7V23jRCdyoSW1bUQQE4x5weFp+Wc/k95dG9umRNp1h0
j7ZAQJkwBiB5du+bC0+0jZC+T83WCVQD9eH1JsCkRNtjjtxikFJEjVa8oeoJVpihrvglkz8/YnNN
BFuxIbhf/6Jci+XW/gSIbJRJXDkQ1eDI1zMG/feP76oW9DrWCFznD6NX81QRmj8RWJt0CaCTNTxT
4Xcd4kvtWFZ6NuZlslEHTbpip7e9YVFHNpbt5eKB85mO9VofaRRikKQtvobkJ3BXEgiM76eZGQ1J
T912r70Qz7cmJLtMQ1JOZ90IuG7w44d9/+LnmywGnUy6BDkZPV3zcQxNKpU1kkvnPUN3N5T07j/s
7jJV91IGx3QaeWgpyR6LRPu9FhYDpEDLLS5enXuzXUVEzVYoq+8PKbCyF8BFyWq6Q12SfC5ti160
nUrKV8dYa1ew3djopUqt2ZOTotTMAq4/YBENV3M8YWFJ5o5lN2Xy1q4mwncWoY8+eP3bhwWtL+kG
dfeVPSs77d3ckJvOnhVk/jh+grXgAf6gzBI9KI/WdFCiRIxCpqaIUsL+Mr5m0QvO26uD5mn9SNw3
eY38PIpVDE4oQNH48NYxoiEiE/jKRPzuoPZzb7cs7QP+BYk8DKVW6TY8pUwfTyq5BpO4o1thKWDB
GrZMk2PgFPkocMMxEcj6TSbnVPc50RlUx7XEMfVM65vvMCgyS35jLPHwKxroyh2xDH3y2a4giJsR
EhVSBqhlVRrusNhd2ZWU6bpY59XuHwH6/o4VApvBY/xZWCPSLbEnvT5AYDdqbN14GYTPjj2FHpqA
6HcXM6aRCpnlPygbYJYSkIK7OG0LbL9Xws/MMb3gM+12jPznT77dGL8Wj+ckWWZV3PaZ0eqtuG6I
imLrVtQje8O8igFJ2lOT7bW5p4DexllFoyb5s3iGfWvnItE7g4dWij8sBQyY4uaQXkWkR1UbZRDn
F+1ph2j3FfJWqTj6IQfVF1ykWBPPwsSd4I6AXiqsQw86dUGB5YtNClKBot5inu9C5h72bnvhgZBU
AYLAGgXt//8d8xMSX8XfN+myfgm9ZMi4+q634XBvp0wu4R3mxREdomTUIiqDhI3SmqlwcPWORCAu
08A5ECODHyh29cLi7HxwL+MnVKgVQhWlfAU4wGRCmdV53ROysKFTf2bjAuuA59YpYaUEOWFybK22
OFD14GFpCaVuF6t7R5Y9kFrOLO40hhQw63iyJ5tXPS0wcjc/npEfL0H8X/rQu+aOrdzxdVnJ1YzH
SEdzpYR37O1ABFN+Qy1WIbrNvrKJMbsZ6ntO+k200WZceH82rTckAnjQyMuN383L8EYu7nxtBiOa
JYQqOlJ0M1iZAZFSyd7U5u0BVu4k9nNDnMDzL5EmUs9o0N5NC5pL+9TY3mAJw4cLB07LfyHRcfvQ
u0l5h8XpBImnQQby9u0omckqKi8bu+0TtJMmuT49AQGvntVgIbqsdoEPjlfYxn9Ao+yQ9xvupQ6d
3MUaYHK8tq3fjoqx/I6U/ZhvFthN/K73vRQGW/Fh89FpDKEvsKjrcK7lny3jw6FIeiYqruZP2GYD
SstYP4ww5dqtcjWYeNnY1v6A1fwX2UfZL5VTVVjfqkEY5iZ4cSGLCuYVBk4TxVWvc+rY9BYbAhKZ
oyr7VgV9rMsyWcmko5Kc9ZzKvP7HGmknLLUT8kPYnJUvkPHNY+KqxdQShTCvELeE+DciGRDlYrOt
qiyAO7NMbt3Pe6Zi9QHwFfOxZhvJKY35dej65Rc9lRm0nDr4mLeX5NqqL4hcg1cOQd2f9WDgu4AM
tQ9veuyYxHPjNod8THQHU2Pen8Zk2FJ0V8RC4aqC02ikqC3ibElAdgJSsUugK+cUSP/iyv3jg7qD
rzhnLbzQbDjxlvyLdgL12o4LvduODFlAXp4ESL4V4BpEAleLiRWf4N+Lqot3wE1WCTTd4aXs9po4
l4WD2aZjyDsrKUyJMXe0yI1zj6ozv1abyHq3Ai1kIvvRsDtJYcni6S4MZfMPMPU6q5ZjMNioX6S/
zvDa+tlpPnnLEkRKvoew09sO9k1SQ7EuCCT6q4mvXZ7zkv3P7bMttmGK5dgwNwX9V7KX5ZSB2D6t
+nv7ykA3rT8K4udikCTU/tPo6zhXeAx8/s2xHkKFR3DL3n89pqZEbVBpmqdyKCYGMYxTb3tw8Z7k
15RfBA47EfDoFJyERj9pFpIH/+Hari+eusoElEJWwIDO7YHENYEX5qV20mOzMx8L59miycqsPOnG
HU2UlKlQuHGh3/lYXfKhu5stq6CeanU6GrpFDm0P5a1bqk5A+kkZi7K4vYDOmeen/0TMTL35Hjpt
jw+X+t07IyPID+FZl66ZhtXinfwqJXkmGCuPBAzhGxyTrhSEYhCPyDYCOxYfhxMvXAVAAS6bx6nX
edfzqgerIM5NNha93qRaWCv4eBhIeERzSnOSU/+0jjzENokqCyT+3tkAfBPZFy6DDJJD6LE/bWH5
IJI/A+63wfOTjWgTv2SYmX8TO544OTr4M4FZm74QQ9AOq6mwGx8GA0FuA4WWoKM/HEPwWJws6P/9
H33+0uWKZaosE18Pp+5ltD0lWPxNFzQNfdMJsjmoqCX2F3I0Rit/dPpVZ2gBhKv94/fs/f5luEZo
73m9gYg0AcUza7TgD0ik+J/6xFeijXuibVZ7Q1Y3exMDJY0wb5oJrlO8bxzFkrllFYLNGIWTc/N5
8goBAr9ulTLtLsIIweVDHKJq13KyXv9I3DUB4qZ+5N8pB18FKCaKtQA0LB4johhKnGSAt0+SlV1I
e0YTHYz9w5OiFgNlD/Sf/8RZkD8U6k4kT/nnvxtVBE5YM13gxAMCnevp0sVvlsOnwFi3sD57UBmX
kfTo55gZvsiZB0v4EgroskMC2/b1M4pLzSFGEwr3YeR6RK4COQqtjzOjY5vVw6ijbxRAbmmGfXxQ
bFa7xtCm61TaReRbc3vJt0CiLtfCA/pZcm4S/I9R2bIK8CltWBhDfssm4QhvNxgxSrerVzcTtits
dA8rRBJvoLOXGFlEwNQ3aGAZGmjsbUBKqx/S/3KjdltHjSoF8z2QQE027EQMiaiyByI2EH85vyPs
yEY9WlFSy+M4pysi0R7507vnGKs2PYcNO1Ov6iz7X+xw2kkg6umM9ApkoNDuBY8V8HDbodru244I
K5czVhwDUqguPGLAD7/hht8dkCbhWOpVjAfIZ+6vOopg9a2gcuxUUYtBWcEygU7pFGzE8IJeRXBf
pc4QqMPdswVgaagJvKkpll9XheJEDodMMt0caefDmQYTWAyl/b3HwVh99H4ppHhlXlKnnTh8THdc
djoZAVKA4n5zlJ8RlNUT6ShKnOSoiu76S1REGVoyXWx8kUGUNcIsDshR8YUlNt3D5iAQrKeeoxX5
23WAKCebGedTMawvqRrObrRyGPgjOl4bn6HPwIFfJ6L896mppxarScWSCVRqA2R4AZ/WojmCPiL9
g0qzArI/DcscWviVzFpOQ0PU3tT94LfMQx6UhPG7Oe77ha24Ar5IYYFtndX1aOZQcDJlQ6MNXRWV
d0u82+llcofcQagSD/blYQ0p1dBBIYi7n7OlZb4FhD2H30KX8UisQYjvmm+WYWkeeMmm/pFLhfLl
rz4zl0yxjknzmErvCCQqUb2uZDBuo3y2gOhqMqxVICruKzcRtSbDsZO2otvgwppP0uaXVl1rBdyB
e6cykRZX0aZf+Y7bpcSo54GWtg+7wbPThWZ2YX/bPJ9Rd00SFpIdu95Yj6MehdnF1pOel/aJdueW
gQa2L0ltwpvpYqgnipLwy/cwPQDUo0rhbtTvduBOxRWZcdDY/38OxHfl/Gii2Qcw02dNiPq1Wim9
BDDvhyLI6QaPi4UtkUim354pKPhTTOb+WBv5OncTtlmvV3dWy3hMNalxeIoJap8vipDs5RUacw8U
Ug66/bwf4GLyERVMTrTV8WEZiityGutgix9jVuxIfN0Fa4Kg2rX2aPzk7FH8PhBCkNrN4bf6cNC9
F87ntELp2LkLTEhh2uC0iLceHAeH2y4NGfiVdbArl/t4QinywrDKSh5pDUDLN8UsGgaxOHi9XYxW
nCGSHhCf/hwJw3jCxrfZ45ESZnEHHeXeEdF3uO3fCan1+u8IAavvugW913fayK7+sqsjHQ/PmZBV
eGjnQUMAiIgDoklBHgHBptH6HdJeHXYOOTht5RUKWx2Ukd5Gh3JNVRbm8Gtu4WAGHKTitQoH6QlY
30scHgrEEYFNpY6yBh2xz2p2ZHU0vcg2qYCpapyY4ule0T5Jbwvf6cFzbUtqCdPzD0FpZ1vBOP8s
CGUPLZIZRQ8vILY5IjoCazsJwWq8YnyhEUaFeAGJNrgvY2EGg4cV+4GPinZ6sw1SZ/rGAWlMvP0O
k3WYTkTa7GeQfMTQfvbmXIIdlvGK7cNjjebS4mAXayfv53xCm8b408tUKFD9JZ15vdiIJp8Yi4/6
gIvV11pwVlkoadwB3qcGhZI0j9XQx/vrqpV38XagC3MB1vxJMbHvENAPnkXixwzvdb+ko3ELf8Ea
zGsLd+Syj11W4yVjoY4RKG9p0+HLdR3htOpefgc4lZDORt1AG9KYgFeLfVZXu8+9+lT89UraPhke
6nwrsri0iN64CV4kFy5uTNBmAigiVrbY5z02Y+rdqj/Hosur8SObDQifTFOkn9xFyUVtvJ+oOZOK
YlY8/eE738mZicykuM51hpMvBWQiru2doEcmFsftZGOStGYboYl8rugKBHU78QHM/S7vyf5Hu8cl
017zGZFnyVx6yBvY+pU4/6sTSRnA/zbreRcVief+OFNFir/Yjgak3NH7LsukdKcHdQg/HssOk6bq
Y9EDAcEarak6m+PGEZDvhfXE74nElkD8hUp4EPSlxT6QM6Jubhf8HZNSpfGsfphqUHPZScnYh4o1
z2xY4357CoS08aErFbEPNi6c8LzBo/WTjmuhKfHwoGF6SpwUDFw28a/S6dNVIbmcubHuupm5WCKq
ZLA6qsAXFvzmiCjiBBOmgPLqj6AY5st48cdG87laNPboXgwOARiBaSMsObBwvJ2+ee/JVtGZ0BnA
+wIWdkvdj6enpRksVLDpXGmpNovjHcQwpiABqMUCrnmzYD/VzgnzbO3hamC8NZEp9yUmF2zioFmX
8rPwP8o64FA/WBov0rZkOVD5OZkvdVtvSowq3Rm5ymMpwlOmgBTzBYPF1G4Unt+cj8zq0cKlLm7k
ZrQKCdJ/lTmVbDLqAHzZeVW5NqoVvfEgWxYKq3MHqfy5IGMDrAibylHL/nqvuVHxBui5PLOQE0Kc
cWzrf91Lp21puFcOKy6CrMOJPWJrph0gEkXEr/RRB8RWyGoQgeKGsH3pVlmZEXtk5iwr0GwBXiv/
MqJsIdg5OdK4tDRDbdV/oizWAaPNXVdRT6I/+hYZWojStoGMAqKxQcUecDvgzfCmqffE5Fsl6r3d
DK53KNQwurE1kRZzcxGwDHoNaezlc4kpzQXxyegFHP+dbJESn2JHev7IlPWfyuTG0vnICDBwYKzT
YtWMPXh+CRbkOFWHxtRk79jiUmbfDDcj+PrNYIeBhyXfRm7uEO/TK/ubFxPpzm8fZNs6/Z+QmCEK
MHCNtaFixavK8nQUkRRaomMgd95Qh8zWsc5USbaGjFivkfT3U8atOs2kvg93Rgx3heZVI6PUTMMR
3rWGznakgGE4FNk3di8bN8pEn6woTuN/AXmQb0Zb81vo9xY5vUd1IT5qcs3CjMFM/2vTiML0L9S5
m4mExeHpTWneKO4bnmEOtdAGGy+EvM28GGhjZRVCakEE8n3c/aBJybqZf+D0iYOsStyEFcPkY2l1
wx7IozLKc/MxJE+m9z2JvjQqbluQlV3/WByfFjTyaBGFLq6A++xGDiPYyMnulethykZp+hTIX3Rw
yk5G8TAh2vccS9+l6rcxHU7UWA1b8W4dRYhivQppcigrZbfsoa3i5991l8eV83RUIoLm+86ygFc7
L7ydC0R091RxHq3eKQf9J/oYxcYxeXjZtU0yxMVr4ipPu5h4TYE6o8zN1PHjGTZ0/Ei5Y4x1KpGd
bSvP2uwAElDiUg0vV1Ras5BGyud6lzUTtC+dWszInqBrlhnqLZeRbBkO0HFKJJi9tFHMFXrYOj2r
7cr3v0hr3ksmqUQ3Z/AR6VwDkxtNTpjsMo65l2NJVs3P7Y+O5ECJkYOPVrlyF340Kk5cQpSy0U14
AnbtSPM4egiBkdnKf7lOud5NhdPElC+99fPcKvxIsborlbk7Z1kL5Kj/nl7BJoFnFcG+FBVuyuye
pIMySwDra3YHUxw84b9/4TAljpUwzx8CT10urwlnfb18mijZOABF5t4jiFIsSEEU4+Y9bzMu0IZz
Agwh8pQVminFwh6G67kyM9LM+zXThsPwfOhwFclhMTwrWrpP8jrpJEEB1coJyPjB8/5dfI0J2kCY
MQE7bt7BqATSHXfCuCo9bk//bREj46CFaxf4DL4NrDl2Rpf9eTxyoFStGOKEfLN8UM1Kg0NY+QSQ
FhAXYKarJbS28HOkXvVpITeXn5TEE7bx1S9eNzTatIEk/vdijUhhnmGSh0WQb0GlLVWlQxEkU/fN
CY4sp8llZkdTTOLnyXrKbzW+qjMPTYCc6J6IQQmSkd1EG0He9iC7tboiVG2VatAcJfyHXXW2RXnz
bcmWAEnyq4zRPHbRuOJxphNNPTW9FiL+lgT/46fDSMQC61Xg7izVEYHyfnsEgN26ArjcTmcFy4xr
lJdenJf+r+2jvm1VnXPS3BZErozeEUL9KvI2NavxwVu1SeEFwvOd5OljOmbg6iO67l5k3oInaFDK
AwcZdgRIJ0RIpkIRf7venObHWQtIP+O+jDFBPNtvYRKad8/CkvDK+8p1GgFI0hOsxWa9+eWel7yk
JMcelKNSKZhf+2jMiMTBHRZ/IJqjqwUDSjgvRJ4uYlWKRmxcifnCwJ7Yrgoi86w6EZ+cVc8azRra
3TKDbWG0prrqXj3r3EGZwWIi3pVD8RpZ09vDodWEcs7cmsaUzJCdGaz1rw2l0MA530EUbzOUMjbh
mLYbu0mG7+A6QYJsy7NCsiKX4pQvQRvxmXORcKrppMlky0Cuj3iqKTEnT75eE5/4az5ZAEA2TTw1
I3HQlRZ2Yb2yz75EStscOUBz1r1V3wFHUE+BLqExi5izq16m2GrPpKclae4ku/+tjxKk2hRoRW8m
YrjvfgsUewFXhSFgoqfP0FGDd3KMGC6EZNo637Pl0X/3WyZQxZPe423WEzo/8rF/vy45V9kJXAiQ
ygpGBUlWAEP3XzcvoAbAUjfY17dSItt43du1EVRnakIZE2lzTWzd0x9KARoa46rON2vSr/bEkCJE
Cfnb/dDm9pA82GbTXlUH7Ddsj5csHYVARBL6I05Woe7Rrwx8/7Pw0YkgjcrFyMoIp74be5z+g2Li
KCBd/DArtLiAFNnPiFi+fN4HgmoVa5oL5+azFtrpVrYWexgGDVOLYC8xRLztaUlOGErygxLeGm6c
mfbPtuxg66FhNAYyJES7hRM/ys8fNsyscQidDISNgPBuavIJE25jrv2lTCysnDmJ3IKmCtiyBQek
TmbrTYML+XaP8SoXhjUdpKy1HvmkTTsgNhgocK2kXzGNapLPkIpR+P2fW19j/A1Hw8Ao7DeU4uZI
j27ATvptuehj3rPAxSYqgsB4v2RCpWbANL6mmeytuvUEbQqE9ddLB64ZIag4lCkEGDtFbn0CaoiO
ytHKIGKH6Et/8W1dJ3f3feRhAiUCenqoUSqnrmHmgMmXGF+elVR0DVNfzICMoL42EgVDwrW/32z8
1ik3CW5/8WmzpA9/u4rXp2UvmG+kUZQosEbB0lW/orlsp3CfhebA3ufthl2J0bBatrM3c76qygIK
WVuSquApyTuFELJQgrV1NXwXjkfdxcezAb0FUKMYrVqwDrg9CY9Cl3kn1zZnIw6YW6Yu5R1Spjoa
YnOij1x6Z9cSbNH4k21H64NOTWy8T055kRDgIzf9fxPI9sGtWgKXAE/6vOIu8SFP0SW1smpWRgyN
j+Eu/Car5Mh0faHfKDzTnD+sNdyI1a00NfmrrnocJrZ7fdVcxSb4t2tyDohwpUptEdc1BHnfo82X
EVLlkCFIm3dlII4C7M7GqrRkQiokpgovIh0MmvZvpxKCseOiG1bn1KkNcwEmJfpFt0zHcYk/xQQB
nB13DQE5YC58sCfQxedSX1eb5le2can+q6R11ZVkq7dbWlFY3bCLhG1M8RlAU0dloUXqXE5JICy4
Z4eI0lsomwEVw9ukzTjihTK/SbIMDIeFuGmb+GPyj0VS4fexvXFm6f5bM5fC65NaIINRCIi5MYV+
rsfDdJSNNzR+IZqy4qacUWYsE9y3KOpQeR2UXDHQFAMTO7rTVy7tzSupVqrecqfyd0A1Dc7WsCMG
JYZ7YKDU/tUvruETEVAu7xZzkg8QhVj5W9r6zno9cFwPKkv7BX2gpOf9eJtu2T4W2eQHSvePqbvX
GLbJf1X4I98XDKfODwEkEQs8FpMsJ++nEnr+V9CsY9JtVWmmCm79fzANwzEz6sQ9A5N+lrSzrY+G
aBVSSP91CzpIcjdli0hcqAz8dBBapsk3ivNIQGwDlXLYYM/uT1V4JzqnbbgGpyeVOsAxOQpotldY
xo2imHmafTS3F4FbeGWhM11DM2KYjAOmp0xJSiVeSNwgEgOePtmiW9cElGS+EIxWfJyZ/LAvvumO
LUWQG1WYeteM9ref4fgXd8f2HqljCVVomWnupzz6aSaVuushBSILF8/YKzitrT0+bCAxzxgPasIv
xZTCM60bod8k123RekbMBwh4+w0NMFWX3G049s707W6MCWEo7Nm4cLF3g2OZsuOOJZ1CXsBL83pV
HNmy8gw6ci0soPG2s4YLTF68ZEkKvFkw74tQWzemitZ0CwyiwTICIQlXE7gBaZm7sfBSS7YvXVZF
bhcKShzYCHWFpyEU8FGNsnvnSZbmhVTtklVdn06gzJEBdY1fKfJao3Qaqu/m1VdcvCS37hL+5Ymt
lu2DWoh+hnnflsEj6gwV8C7v73Xtm+E7qtbxOwToVJJ4ixmtQ0a73UOXCyoMn08H9t+Ss5+8I6of
Qbl9ZC8pwx5wQtaSKxxv6n2fxVwD29NzTgRrxW39ZMgaohR8dU/GI/3HfG4g/uJU/ctYQ5Oziai2
6wOwmXJTLLsYqyb57y+E5FOeNWEn59NpeKFGSce7SWLrpNlQpEu1DJbbVmepOqmKWM53KrL+uODz
KnzBuEzG6QOLmVcnBO5RJjiPlx6jJ795E+ZgiX61whpSR7c3vvNifG3oBkVVC9eOvCkOUZeCG/6P
eRSsLu4QabLRAE9Ymk/D1pnLb7SE+yicuIJjP7RaBvnec90eMwO7vP1EoI98UfT4D5vUzjnHvH32
PjTq8iks9MlqartrT4jYkpC9mIFnQgNgh+pLT8MRztCSg5LDdtXGROpBfVOv4ZFfFimsRr9LOB3L
rq7p5HpEIDi2eYNf5S5TMK1oOf95viLXBeEKlrFcBDV3oHiFMdkPnlOYCIMOuXKMOX0lFxcN6MG2
UrBsv7uv01S3InxHhOCGHo/008brf/QbC9ZjMVcQifu5ErVijyUGrDs+cTtW4BwI8yot0McBFdY1
5OLxMWwNR+26agTcHkPefE9Ta4P+oODFcYLl7POkV958fO6wgCvymfEW0uoY/b9CFcwIA5ObfQuk
t2BF3IfZFfh0fZQf3e/cYEH/rGSZT3h0NrsyqwvMNwco+QNgD+4bDHHRyAq/iWGx1dKur+ZzRl0t
CbBi8F4+Vg5Fl2K1kRR5v6ysC1e4HF26cG71mIoOTTdxgcenBRgcIHmSogIf847N95umG93oGTTr
iMosRQqqrRgyxwjBbaUv3ZYvy7V/6REAE653Q5Bv1FmUzaADK17GKcQDzL03emUGdZo/icflMhLt
4Unlbau/D4eMMrHgKXYKVZKau4DwA+FKsGuEq3iIpMoAnoEjXTSzLyIYe4mZJn2aRWJtSMBs4lOw
Z2FlAcMQo5JABDIJzg2Xp3wByygFL3605dFmkxGqvm1RX3dAxvI2Z0MCKx1+4NvACLQsA2PkB/zn
tEkK/eicf/XFmokcUXmRNGy9522TWFkHbkfa8IEGkSB4GGeFITg0LFyekjOc8w1cGZ6PvDSBcW9J
k1ifA7MQBnd+x9madL0a50yHT1ZO03XjXx2xWwfPz+pk/JCbcG/F8nxQctDYla9FPNmFOuPZJXMH
MIy6aDO+I6o1vtj3FFeJrLftkXAi8QU+6MBQdMihg+ZBZ9C9rvMOUoTWdSJebFsDoH449Q1qSeRB
4rl9rT+/Z/wo+WcqdDu+4XyQ+TlFYdkmTuAJ2Nll41QqJBnHTshGTMndyyRlBToQBR2h+diBBhRX
Yr9BLzLyZkFmKi8Szet38GDznbt51TEAdoXiwbiCT2BSzWy8t5bD/ssBLNH/4grN3tDCmKMjk9BA
pgXMIQ25fzdEXH/tg0JOIUQ/+lhbyNWHvjLpRe++KOq5UAq80BFsKods9mNlTEezWQ6zX8ZlirWq
SQV7FhtVPi2qUkOjHM17qgHP2D9ghLrskc4osnBbV7TyL4pJwd6gWAZD6acZ+SRYlBfkkf03hafg
WHIkrapp8D9IV8YIJJmmZmrQKzuvVbgwx7+IaCqGI3h+FjBpbKaHwu80LhvBTgo8+kFEk5R7ZH94
mOV3HDhivnvLUGB5Y6y2WMRBmPISXJ4LkXYLs91k8S7V7pitVaTBJMHcNUHGqs+UZOnSEkoYiPdv
RouZTtW6V6cGUcHaaiUaChoxTC9GYshs8lBeOePHwNrlxn1yZTDCWSavBC+pRU3B7HaYYgSt5NPa
Cr0k4oBc0CnhT7QOdGa7adNdQaMdJ8Rm0Mk08bVN1dKkMgVYAsTB4271l1RIiAn2/R1ykPEG9hxf
arnBSmOc4E4yuUGH2I+CqHWMi/L8Luskr3eooZyFgoC4i6qZi4WcxQs8t+Be4Oh5JSf+tokEVAnw
Ufv6x1zeeKS5rDXAOUaiXbYtU1v20zQkFCjloxA3NmWA55MVsYSapcj/hBEW2vfAdyXUePLd2hZH
wVV+IHraI9unG8/1aEbT0hZqADN9EOM525qSH2qdCyAW37c1WQojYaUwRQrY+fCuGCEkSnAoJEAv
tGg8WsTlZplugxGJML27yUL7ml/uDFIYl5VK2FfqggduGnMjjs9JKCFY/w9lUouUO8Dl1M0a/R1W
MzKHMv8Kk0ma5l9WtHjEkCogX5HfisxTzkIY+nkaqrvuP5vAZ9pKbksOc2cKTbXcSQD9vacnfgv3
TUj+etl1eJI4rPFgfOkjHvq5fGzEdtQvRIUPaRqEGKaEb7ni8AjSh7EN5jJbR+G7ZprxjgkoXxyA
UIIJg0DfIZyWBerQ3gzZH2b5wRA8XsBivs+JxhX/Bs3r8k/SbuRqytQa2Y3YkEbh1E4XZprwEu+s
gzzvYZ+OU4lb9KEJAS9QP4dCCu7VtVd8ZTUjPZbQbU2w21PE8FIg5CNIfzt42Ra4ZzVtAyk0H8pk
AOVT+NPOk8icQ/LOQt1BL1s4AAjtmgoTGrDFcFQ3P9EeNCAoQP7PFzTSmtxuL9iEYkQA6I3XUUuV
QdgTNOiKVfWpwoKOI0GQvFvTjiFD+fBVwiQgwChyAE518YdIi9Q+Ll3OE07znV3anLuG3DK55J+N
EGY2fdn97g3W366OuZ4emw/IQC4El9Gh9IJ1BFUMY/HP7XNvQE86aXrq0vZc7/l/MaRP1tjNA8FG
GZ81/1r9QXueoIFq/vThQ5tCXD+zqb/7DMK7i2bGCzTHvLIIH7fKVaJ6xOmtFlYZlkar7wYEQKE3
AWP1R2x2C79OJ7Ae7rrcvLccgVhHmYnYIqwalLaE6NTKne44KnvBbJx3rJPwjkdamPufG0N8yEJJ
uz+hD5j62BY+q3tD4dEsdSfpryg/ZAJyZCe0kxYgp5f70LZTF1bu9S8HCeqJKyEzeZ+hXVCizqnK
UOkPDepK80nxzGQj04BClmkpSOGljb8cRAaFHOF32ppfCPIFSP58+/kcYW7k3ABBChrq12CO7luN
8X5Pv7pxiAbJhbisFTKh4f13t0bG4rZtVHLN7HezyRB2CMEwdnNwLRRc61QlNSHvs1QCzzp4vcDJ
pOwSXkVaPp2tO0jI55FLtJReQqGSeDNOB4zvFVPwkR5sAND1EEQKAnIfmLOupCbJ3K5xH90TqqA/
SQFzyJXbRxJLDks6qVPBSoyaZWSL/Jg+PQrwE5BKfdwraD+jT+vfRNAptvy7kRI7azGr90w4pTsZ
ESflSONz0Vi+8q5YM+AtyEnVpSEFThLEo6Vzsg3yrs5Ls0ArvtFYF1nU3t6Q8SpkFX1j1Tp895Sa
DMauVxmb4e9n3Lt8AnbuFrgRtXXc9bheSImhDYOPcnZ2KXUjMLSc9+ICwRVuBt++1V0139hWnlZv
xHE5o9NQ8TxmzZ4Xi44QobKUfY8oIjlYLHpN7/y5n/u0R6tlkasMr6XCiR0tqEpIJQdwotqkNBo2
uRvIuKFeW53KBc4NADjvuCwt5gmy/+RpXLl4jhh1Pb/9BVmpWmYcRtY+2C99esxEpuuWoTwvppaj
q3qlK0WP8uHr/GxEW3GUhGTKV3NIxzVMIWh0KJU31qTEJsxndZFuQy1wIeW8ZqCBN/iQXFEiVhFu
MBL0y1GbgVhph5n7+AfhMkoZDMh58cdw17WzlaQs3DcniElV5oUvRBB4/NJMu/raOLlhziG7dC0M
htodZnLuAUnwfYBsmXGBBsSE8ViqxlIj3CStFEqdI5nwDP2InEuBCzhK8sqsFicxTJuoNV1FHGK4
OIsPzDyAR1xmMxPzqQRSPNRHVJ7zJLcCxDo65oItDxjE59FNVG7Qu2+7LKfmg0vcITZ0FpydJl3N
SaFqrG2VbkSe0JAUgEqjuV/eo2/XxbNaX/mDpJidGb1mE8qZsmCMIehebD9SNFwAPVqTvcqlpmyJ
XhC97zx0sFUkzSe+3g3dCJQX1ZAKhY2uw9K3PcC31zuzN6CWKBehMr9Yh6A2aA3AYgpNb5Kb0eDV
QVmBQ26cwXRFEAu/JDByFk+qW/uw7vlrq2k/VPLodmpb6UdsZH1y75XU6vOmNjKScYnvPxDZ2Tep
dvc1Cb12CDI7Q/M9ZGxpLsTEfTsXzg2HzWza6tn8eypPfnMqeFke9P4EmsF/Aa8FsLge6PyeiKlS
EtbY8YfIPEVUzb81L0BYemiuG3Cttf80Objs4Y7LXIXAHDWuhb/4abk3z4b7FqJ7DYGNbo7CqC+v
BMmSS1bWt8J/2VIJHN3624d5moi0qO21ASQz7bh5KWIlXv8XhObqTtDoWSn6V7scFVycYOVCwqKr
Pr0WuLmsYmpS+S91JkpCNB752JvoylU6EPAp+cmI5O7GqSZChbAvSxtXiRwXXD0QVnnj4qUklvpu
0EIIFBF4lUCTAwhIlMOmwimKv7Tyv8RuFozhmABZnJ/NTJkguBjm+scx/47kspLINkdPOI6y21vh
4x19qaaYeYOtvfdevafGPvHFnvHeFhgXbmISnn4JfkfYeIzUwzv/l9qEUscGmkrUfWo9svYmhVtp
CdXrRS05DOfyOJiM5tYt458qi7dhRD4xIlmgd+Nqz554JPx/TOm2w4ZOkMvuGCSPbYuvBMtt3F3X
vEv7sfX5un4uF1d80BtJIe/tLmeDsk7JeWvjaxItZaUrh9iKqPCR6EWu2DsVhd7eFfYdeu2fNUHa
qgdEMvkZSLzZ220WvStDQzuP6sXwmc+P0TO3GELTVEAQp3vgN25zCsdAKIuwUZTrIrz1K70p8jiN
SBxlGydB2AEXoy9SXvhrN8dgPsPeerbWgZmNZyt06i1R2ZoS9X1RnnFFS7FGT1kRRqVdG6TJXtJO
l8OC5eWtqdzp0fO7fv6wCjfGyKmQQ4JU80A7tcZVHA/XKLyYkGST461OhSLYC1HVm3SPcMiF1WNw
q0mp8SP7te9Y1WnfyGbxPzp6sCWgm8YyLOPY2AnQNjA/wqcgvnrC+YBMxDN0sl1BpRWZ/yPoIfxc
epYiNDAHIG3z3RrcR3xMmYEFwa/XUkDVZBYEdFDg1pFi6/l6EY3QaLLqelsOp8hqxQ7LDFTc+wC5
jiiZI+Lt73F3B8tykulrsD6+E3D+8ThKeWSXAhexMx+OiTlyzzRFK3DX+Zr9LM0oauWzmaeqOn3b
XtFhKpEneZOuDp9YZkKYSDlFe8c9Qd5mla0hXV+FWAls6VSBjU/m8NDwkhZJNlGXIw5vwQqMiRlc
C2HTpnj02DbjreKGb6sFfu9ATHgORwt5TeFQXhnkkDbVF1OA675m8z70iNk0UYBBKnA3v/gMHx7L
wcd2U00u4gqThbKaR3p9G4L4asQZL7lRWv3t3E7mhqEY116yQwJf7FlJl6gAIcOQQqJad9g9vbx8
ErtyloPb5DAsxOkASdqeDeVBGxzxoiY5mCF2ExLbHbLbLi/clymSgLPrPW+UfUnmAaBxXVo8oRao
PVZH8N2nvBOcpDT208iGLFnC8eXwE49t8pxb1CNkOViP/tQrx5uzJStJzHHzWwQ88kG2baWE1VVR
eLUsS/nT8fN4/43X4uRp6iyrKANAuSiex78DV4d13xV/RtvQgraBS4uxHX4m8AbeUolaeYzcbo82
6AnrDPf8CkpH2QVuORKKGQlJWmqG49OFXo3I1y8bJD3jcufDnFGcyXn4dSNGHscmLZS5F9BYmaoK
/6B6k+qNZ77hSugaMtcBDh2tDjiy/eW8R0u03i8Gwx29APZOiIS8273PcTvp/mC7KjTWFO9DdS8J
wtsJgN+rkU4mnrIJHsHh8Vsi9T9mlQVe5N0DaWfztlJvZ5Wbc+UgPHeOI5R+19VRbLz7pRkNU6Wf
g+QIoZQSb6W8hNNeaghPT0wbCNvKhdHISOidBdJbONZMR1LHBr80POo52c5690KIqXpoffLMjU9h
EMsNHKhetg6QFV9Dzz3tZB5QCGW1ceYo8ZhMsKH1pkxGWorbGfat31iobos4yds2++YNxLlYkk/u
tBd45wMQkE/tjg2U+Xq0B6tLaTzVhGKpw95YcRZqJ/SlaAWKuXWzBEUQqmpaaq4PZmzPxhsUyUVh
+Uk4FK+bQX707k4T/A2fjOHoKW8CYXghd+SEhn6wfjW7qWk2+x4/RhOT/20+HQz1k/owX0utmJJs
Yo+38rpWYTr4KIPHUNXCfgeXf+A66znZrlj/7SNDwdfn/Z91XYSuNVzXdCnPjXk1bD6VwpiR/jx8
solitk/+iI0Km0yccXcPiV8LM7kQditx4BKnxtc5GjvrsNEQyTA7/hKrHcU68J7nURWr8G220Zt6
b5nThVFQ12vXxmLUJwwQDT6AfwvXkrkbpNMdWWLFgxx3Hxbd31u55jLOO8v9nkTwfe6MdF9Yc4Vw
ZrmFOaOvSMx1slT/gcA9QhgeKmFa6UdQrl/c+LigrFoo/ouAjuZe1vVLyBAjhCPi6YsVJgQTPxYg
acCCdO+smbVIXdPb+g1cDAm6mgVaJ3Q2zSH4WdoprPt+WkkQLPhvDFwHb8PV1k78+DNojMxK87nI
PuhjPzCaAiQkYPwAk2ANFfafsdqKqHG8l6+Qrm5IfZqq+TalV/PR0jQ2Wi+q6q+eWC1WNDdSAIK0
imAOOpiH4ritqGfF8eUO8K4m5SeBQ4ifz//8K5oJ1ZhcMPDnvrXcE4qiq+0mMjMw53gd5CK+sHNe
6hTjqjNCgj3bSBeSHKMQQninscoXV/WgiXFl+WmgWgFqsLdbrUnrsKLpW46jBZaFMfbteshJbVD2
Q34VzXu6MindmIy6BxCq3Ki48K6vOk/zYbMsqVHUjmcnXB8Bp8KlHqBwEtOn0x+WUbcoQzvSdoH+
NkqHdQrit891imWsRTq+1E7qFWuMAyjnKU3WfpgGdWxqsuK5S+3zsZMzxtX9pZE3i2ZxClY0sko0
JH+iTCiSGMdI9Bk6T39+y+mp7Ug3a2IeulDyxOzYgbQoHsYEUqMuG+0esXtpbnWZQWiqZ+oHcQv8
RF1PpIqlLUqlWDslP9Z7p5E1csn4ucUqKbu80sQSASsqAao0xfiPW3dgcWGDQZgZrJnOIYtMGFta
Q//wPsH2IIge4lgVctAMFNTxvhMB7poXN2R8QGESgdz7cKh5esvZPhjbrOhGvJjOz23UmNihpzyd
bjvLmBrJZE9EY1sqpLE6J9QhJvU85/trpSkzhUt0Ho4dj7mx73wSC3PRX+lNW+OcDtDR+Zp4aSN2
EjPhL+EP5Ju1swo84N6GpUS3SR/BkmDjfF1aEr+HbanU84Dx6yZEbFKVkMolUENzN/1Sy6/k+SBb
BpVgXKe6oggSsAmnI1aqulwOudXWERo01Xy8TwPXeNMDdR1xVyXaBWXAOF9DTRwFGdmh1edyT2LB
Reua3L9bNkSemFhDS/F3xuNSxQ2IqPLkPE6tsCtDAUQC1t4uQGL7aSsGu2xoLHRHLrZGJoodf/eS
b+gp6HZWk3WndCEVUJyoJK7O3ZVg9PhfrI0xiqJU9Q9dC4I9Q3dkrDHMgVWj9+ytZ8yJAqJEDr5w
qbMxVpiEWKT6kxkB6Tr+m4d1U2jwK5EOdwRLwlNHrDbSc2LcUQz3/klDMjANwr0uFoKZRVvBZLd0
IuJOAafbdnza4muYa9ttEbCShx+Ov6eRp/jONHEwlcBQV+3orB+wMZxRmvwJSWFCQwSIzWr0Qn6X
xpGaXyRM7Jb/8+AyZd7lFmfdBmj6BA9XQBitpolscyIDZDdRRChbERJ8EXqePok4ovxH8BHbTtKV
0hMGCb1RZVYq4H2O9WRcPdMwn1pp0ywik1xiY5t3jAFR2hS9an9Ps+2D5ZtlUpG2GU2ZGh8EPe7G
h/0+xt11iIyV27uSLPOtYglCiH93Y+O7EzKyQO9KlUF13IWSb98CKjmbnPmbjvIDepX7EK/vXeeU
H1sMnM1l4UdNJCR6SaTE68GZyHuPCZMBQmF30iyYzmFSsdK+pHnZdFFZaXTDG2n1TKy4Y8ONoxax
AG4eJVCgGS1XGDjZeD9wFEpd77iIfKNKKRgqnuRr+hAXoaQyTI8WfNrt+frAWwxPGzMwAzkWlVzy
dtG1VU0eZyAjdv/qUzjQgG5Bak9jnL2Zq/+77lqoSuERrc3j3FydfaQMF3CDE3Io6AhR7GWBbnK7
T+m+6pWg3sxGhiorSHpQAZiwBzAXjfSiI2klQhv1z74hce9uQrSLqlj4Mf78HKailx/HuLvy4TlV
S/+XSawFRDLOsoabi9+kEL+w/JDJTpFTNPHJm4J1txgIjJz8JPlVnFPkfzb9+9pUM6NC160eQtg3
Oa/kRBZYpo6f5O3yOVclQqaFgGHm9ypSN481WEA7BzA6OEmkKnT/5Vows2aj/t7Cw4I5rtRWkafm
PdzmbcMombwotOe0lZUj7kqtdpTFSPaPTsOdlqKBG68t0riOS9udnaSgpJk4cIFJl2H2UUl9SGIi
ehI96DAx/KgIbgXJz+lEe9WnMBt0kaUOk2dw5hj33k+CWRF/3nLaN+6NnbxgEJ1/eDj7PfRuWScf
pRkiDjG+y15l+WrJdL2lSG6IIw5/a+h8jK1/fQEFauH1ewykx84MZRNYqtaZjyXjE9edh37Mx1un
QHkUMCSXsRd2LIadcCZlc6eH4rhpkOUI+tsDtzK0nFNHNp0VjLlDixgniisXnnUpdMfE8rsyd9CK
B+C50PEWTowjjp+5QGOmQba+8DrpDJecFui9yma/2FrjHYQLt7Ewy1324iBP6qhXLh8+mP1R0GF8
D9WYpyePJvr/pMLkTKALSjNJe6ta9o1cxCfAZKO3fqClS/WcrBH5zjFh5eOnS9lbO5BcREHBWLDa
IR+Nl390fBKreB4/TRAExA7JUGj628oaoI7NvjqLBL0hMwmCo8IxkrHYjY81uyADHEoARjH3yWNe
ZXaXM2bvy3Jvqt27kdpkV4R3Tu+Zt84X+F1aXS9IwZwsJKU+/5mbYUOGDS9Y19/ZtFZqVBloa5Mc
hgEMEDXbrOMiZPWmnzTrN7kh0ukGRO3poJgC/roJT7UrnFziqzY5Xp+iab6T0JlF5/yllWpsXmX4
iz/P+OnclnOSFUO9ZLevRbTAhIt38yCOAtDxyEw0gnW7P6hQyNjdTE1DRVMcYOfqG/wCn8BYR8Uh
wJB6q0Umc9n9jpLKPxKHocPtDpu4Va5l+Dse4sYNtm5P7JqZgXJQXI7IVOsKbBPKJWGcVCow5NnN
CvXInEMeXKOphmauhq+b+OpXcQoSEazOR4VpKnuGcUVfpF8fXFxTq7tKNppeGdipPd9IP46BZcUe
KaG7uNAu/O45VYl4sUrwhbgDhSBoUJWAtfF5C4K4csOfD3dtqUZK1fvToO79hyBEaJiStVA/5LaS
JiKLI3kQJORM5pyEN6O9R4546JaGquMGdIxgbPCEDnax4YDLl+eFAjRoWJbf6D00txSb0yuFwXbn
gnut4SyJOSFZQTkTQ7Hp+tqE4SHewB/tCGL/5DRQKsYgo2+OBb355paBJS1UAl2h2/tLDzhbsD8s
F/VVqxIItTNg9ezhBZ8fbdDYFIU1iRomgiuBNLwGEiaRpuBWj4so5a7t5ZIO3FGRANMS0pN2tGwd
OqXB2Wt3Cqe/yPPM4bBXmLCJXdTy1f0g8CWfwgR6thMGIel5xWdRzqvaNzTyg3BrmXh9ssg/Awf8
gKlE1BUVdFb80ewmuF9L3jko6gQoVMrvLQF/T5OgHVBSxIsjBeS/oCtaSu57yCUwICoLO5455uYP
dINM/q4PiQoHWDNpTOJNguQWF+GsluO8z3KYAcSoDfBgPLfGQTkk5f0P8/iGOo8RWjZH4I3hU3FS
dEWzrPU6T0Yc3k3HBv6ZxUoz2Ju6OH8Qj/V/PbKII/GtUKmEltiB99j3pkTmx0YDdyUAShlyIYUd
h8l30PIMUfF7d9uQh0+nQFWcqhbD/8yEZUjI/mhcYKVKj5/gFAB8ca9jLWAPRN3+QQFxug6GzNIX
4YNuYcLVIc5uX41sFgrygPgk9as33CGJPCz4vnnwABk4cM2zrGvUpFKtVTdifoq6g8c4K/tnMduu
ZCq/ynOpTX9PptZPierNiA2SmGAzAjcpEnfHGlsMvPxuzec30ARe9i2LdIbgbASpEuY66M4PTG8v
d99//GOGCrVPjLCk65KAs/2MP40lfiDT6t6PGPkrghVgX64W8Z3BubHvYCKf7DmSYHCSJzubPzGS
3lvswxCknI60ZtGScZTVo1JiU2/2+upPW79D9S+lUml393N2rc+jf19LPClu7ktvCayDKBx899Wn
cUMJ1f4Hry8pK0nUAycW1pd4GgAupX9xoldMvStJkIOKjXh/SdhCh3rZCodzxYIuNSUeXwFzvqKv
BUXdB4vtojFhziW2QdqFihGCvvAOOPxSg0VLYQVQ+gZuINCSik2TOennOdmZdkt8HTXMRcifWWt7
FWBmoIkReCGsPp9Qo2Zz9H+gN4mT/U35EcPn5PUHsr4N9XwOl/3eMV43HyMfpcMzFoih7BOCa6Nc
QytFceo9/uaIF5S6VZIXBDs8QKYLm4IbFD7rMKFylPeFNS45UdomxBu8RJ7AxZAOeOhnOyQ8QYQ7
pA17huj5Fig9vHiIzfB6kY7ZFnQ7vB+g9WiCfED0tXqyBofLG0VkSqXTq8y3jWeBJYvHewGaadJj
SHxYxzRoNHiLjh3r0wKFQ0nlPlI5WGY3zEwC+ecN7jNxYZWZsj9Y1AqS6YegJprsPOVs5UINyOno
S7almxJy9AnozvkHuv8gf6eMBTyBn4y555SJp9LSVO1RIV+135bQyTK8QrGYeJ625/YUM+mY28/y
5E6fPSD0ZzD9FkcVsYrqpoFXC+1QuidAhoEVvA2SOi5LkInkX5mH3T993BOf+jBmim4TQOlOeY+c
125dda/CoOq5cSruj87l9Rkaxl25g0N2iYmsq5TsM1dInUe3l3H45IFdJKwBWDutK7IQAcglImSS
lxtLDK/RXPfWHqIfGqLhKB0I4dtikQlwOgUuNG0nvb0XGWab6F47yoUN/4o/qkPfLtLVVz8MO2rS
KAbAe8x2gjteGinhOu5lyxj/SqQRdEhAxP6QWBEhKsIsgqfdRSyQJI4J6M+DExqMjGyyYtymamne
SNQetmkNE5uOpMr8iZWFfAXUJaJUNeo7ihw3AGrXh+c2dOoa8Sxa2c34hEEjd+IZzvL60TrEDvkZ
Zdx86lUTMbedEKZCp2VPblJwHZg7ww2Tils7miuXzog+wBRGVGamQG/TTl8vOzPoglUTd7MpQMzi
+BmdBUXFE1uKZreJK0yAz9ZB3EjBEjjQtrILWhEVL6Nk5UoEDDqRkodGlyuQ6I/Jv0BqIPu6qZEu
AzGlEBzphXRCUuAal57plxDigzTssMDyu24ZYSmN9Tb9VzkZ2kbyh5FMpLQqZeydu0rp0TJbSBmq
V8lh9HDg1Lo9Xg8tcSlMKDqveLZ6FuCpPnYNAhopf7G49tWHqqF61xP0yNDWBS/5joMal94WYGB6
aBnGBx5sP/kJksKKrBlYg/d+uMCtY+UU4IFffcp/JHwl5mOPeprHavFbCIvnvF4mCELsf9Bbh3Ty
RhTasa3JWxZwUMjTX1pN0iFBH6sNo/MnLeS0vtU066CS3eZwOFMn2goOqweIO4hgRZnuL6YGiGcL
AsHaVvWAu/zHF9NaLlm7oFBmE1iNqO6q+FUY/h0Vw1vAUrLm/tswI8yvCPAiX/Tc/uuHXasPuTmz
09tIArK7c988xJuJO19w8Z+aiL/F6a9zY/xnBVtv1zCTpej17xk1KbsgjKHS/Xjpp4LVsJEf6N9b
lt14JgTEKaqMSb3Umx5H9evM4IotWFN6Q2of5lOkj3ZItZ2N+tVq19jedoCOmIweq+I0LLTG4HB0
Mr2fNIAYtM+rM72i4PsE2eNK9qCJZ92/gOP/gP8cNbjyOp+JZgc5+SPuHdG9kT8y85oXiN/hrL6m
43tna2tenLyDTdsBDL1CYu2EiH5/1GsMcxatrk759Wsk9lGv1IJOmgIFx+kBOgGynwuR/u5xJwo3
Vb/mS0jbHEac7QoaEkp/UV/DBhNe5lFcHjUNffnowq3qJ+AGNbt8ShNCQQ77m5gyHbwbsrTLG2zh
c/YUVmQB8bPqqFfOEb53Lub6xTz2ktfPY9mf7E1oqYA/GBZe1IlhF7zNzrfnW7/7GVqDzZ/S5hjN
R9Rym6P+M7FrARileSJKBL3FtzvH8wD9soN13Q//4mJNjPRg0TqS4S3vocITCp1tFZ5cMZ9uQCvS
cTUaWjTyi0l1v5cwsS+cwQrLzUpiQF4mAZgQGcAoInAibHxdN2gPpm2FhqICcCJXPeC1xVZ723as
iOM+ZNsT1i2sSu71aTwKUPO30APsBjGVOw9E9VFdjpwKNiyOpprsi85Ypwt9WnzOEZiS14R11lmy
DPHj229YmapnLlcUN5Pfvvf96vQfVKZ7By1gvLn0REKTVPZnO7QkAMj0FtyOtoVrhO3umxHp02yq
7uGUWKvMhMF6euh1WOE8MPcdvkXNXZiNwPoPLilp8zatgdcKcTkhULbT6WPGHr9TduPD1S/IDRpK
z6NkfwCETMEJpQag5sQe1EyAiXvof9B7xVsydVSMNBzD4CDUteMZqkOIJ7YeUJcqNeAgY5ivFgnG
y6Kf/oseYj3iUb4R7EPBN/gJ5oQOIURapCUUhwh01Ne8qrqxzW1Kh+RM1JvpdYhYr6lbI1VoM7QY
bSBKhw/GuQrfa+WlG1WIfb5q65FKPCQJTAW1b6GDHx8so647NlCIaR9ofhOjkG+N8ef/QeIH+p7s
zcJa2zZyH8U4ADa2YT4eBxuN8TKlBOSQVi2N1mRKzP8mA02VifErXOV+XsG5pTtKpFU7IMk0tnab
gCHMQOVvxV7DYpxPbZtXgMbljIK7vLbUfe27kzCcmMF+RD9IxfH+O8O80waSB5UaOP2HlGFWT3oQ
cyFOqGbk9gw94jeqFsUZRwcZCyZ5uSNYkfeyX1HxVU/zpqFayKx33Dzw8CiNvsVSkKQ8I7UQp9BM
INgAIHO4ceUTltqdA0YfRR3Mj3bkrgxjrmDgjRG5SX2NLxGNxcxXKFvefOFARTUmu86bFHM7M+Ao
MkhKahSouKRkiDlytKm3GTjvPogTPJVWpfFqAvG6XtWD3O8YI9zo2TF6XBhVjFPCv+AQB38RwQYq
l9kCfAw952p0bdoqPdd6lV0DjIN0u/yOGMsJ/Kn8GI1ecM9JsZL1rzALsSYzXZncYupi2mgwSK1C
ek0vFp3yPVDZCb9O/yTJLmeIvxg0dAkAQIQd7D5hsPNmarfrvcfWsZI2gTgFedludWvmgC0dcLWH
oSFsONjxXdwlaz5S+OZS+AdOmEcmA0BXiI5IgpuYaKKsDFgexSzceiP46MFooa3jWe+gx8wT5IZo
Ng3ryL90UOeyWWq2gf0pITy/IbvXLpuXje/IVok6W14MRrEVoomv7VXPsYGvI1/6XQMrC1YFeapw
exe5YqM+KH/IS/SZQAoZ1zlRWziWOIZczAtixatkhB0BmzMjVW3UTabmm6SGBotEbWGt8cxJKI/J
5kH1Yr5ARL+r3cYDPU1Pnf6O8a2S3I/m6YiSX+Xe08r3BQX709KMnps/jrgVzgin2FiWTcorUoZw
E7HiV50jItW2XGNq/1klAa93vP6F5ZTDvSbkLF9knGaFYLHGEepTiXE/fFOqEMj8Z+ftQ2S5g13I
4l7oOlwn6CL31Hp02g+uslR5WPaH7qVW35YOqsAfyLggYWCD+3jxsRSwcRmqIJbc7phCD9lkbS8z
50u0kHBEjaVpow4+/SY1ty5cTXz3BP4+o8CLKz5E409SmjT1sf2svlME4/fJ5nKVYFgNyWCq38x8
Xadv9Wb8Q0xSE5Ftp6YtmZGrbh4YNf/9rk/fvoFery0cSald2FV7Z357Vj0Co+jMfWs++HLYYBY2
K/UGE+isFfKuUdnrvIzjceVFQQm6PhR0D+gKFU7HbukWpa5hA2aPqEHI1e4vbj6x2TrPNxXgUqwh
ezw7sR+HrMKBInFnD3hJTiJhw8MwbXYOlzd99ynkSsEp9eLtDeP1bBx4bPn/JZS3IVQMdmbhdQs8
UZxP76ac8tT/yr2cEyxcN5A+j46xZl6PVyHUAlTor23tQcNljTUlCvLKSFgM+RB1f49jnbS6zKpB
Dkk2E3HCVFX3yw0ul81Pjl0dFyo8C+83ufmaZ0j9qUCP1+WclHlKmM7MIeC87+2abB4zd1h35JX3
IoDZF5O8As1e6Iyutn60k+m/dTX/BNUKojCpx1n7sur6nQoX8IEQCQqaFSgKsO8I6qk2Q4/7SOmU
Rug0ayjutFZKGfbdubMwa1SCQQ/ijsw2/8oe/ZZ88ZFjGqiwHEw59r/rp8Lj5QLs+uyniiODKrja
kSlRoU91y7eX3MXtrPzG7DYY23gi5p3mt0Yj/tVJuezutXkiWnyl42402fa+epMukkwFiDhRADac
btjfIZ64XS8g4Cb0YjjCnyl2e7ekPBdhCQjgJ5Z7Es0FAXAxMIj1qwapMHj7/YS8gCIQQARRf/gH
N4AN8WKzefQhLOc25R8TQ0S0roHA+p9LrKTLL4Unj8qAeIQG/6V42Vv6oXFxwk4Xrf+vAk6O7aJg
z9jCaIHidOO+1zVMJolqzPXlP7sKNtyTtkTzFg1pCoozXxq4kLxr5L78LMFIuRYDUgQKvztk+6ov
XUIcwwII58YhOBMRn7VMuyZJWzO3FEXO/jGBWeaSPaTf+h916/QNSIKPnndkZf2dzsZBwk79a5Ap
mBvp722CEU9oa4jeVGUgK84+BvKD6wsioBGFWQBWWUzP9qxRmd10eF7cVZrE6J39FHqH/3AVksBA
lplKalOOZoh0r/wLs5bcTwIsDf0+7FBmxSd3pYLYQDNml9hF0fHJnSWaMklkrfXXCGS5h3DjD9oV
zFDBCu4GYa8hBefyR/xbl/7IlpkiyJWo3eQgDYpJgh2+A9lhsKxx252Zoyuf0Ch416w8Sn4QuwS6
QlGU9mQ6zBSvk//q19Q8cIBUMmdiYewXH0sDzt3GCL+ENYzrCdded6Z6Iafxz9cT906HEAhK6OOv
JhTiWud9iN7BsbuDh/4G88bqJJl2RrD/Z6C3ClGOBa8xQ6g18vDJuf0Tqqxf2ZdY7ZtvCd48zp2+
FotIn/2TmKYVGxT50ywilm3NHN52DXl+gwcX/EEh29fY+d3G2qx/Ll9A2LXoN+9IhBAsYR65HMTN
4kfCcaXVGHsxi7NB1zPXcqJNEr0O5sg/iTf6BxVpR6FDeEfvc7rtUspaiJJG3BIxEph3tlfHJHjK
cYpNiGNLd/bEwZJuC+XfU2twQn3yNRdJc5ywMJwKvlGYd/5zLd3lktXQxgAfWqSn/v4LssN6FVAB
BHMP6GpNVUKldCBlPUrhtQwSx6V/ffrZwr13hrPhNQgDxIeSnPNf+0bCJAkp8uy7THAvxkJY5Sb/
kKRaxJ99Moy/PTLVqB5ymH99rTPWMY+ZvykIvmwIrliM1Wi0G7aoJPS1Ga+PVHcinwd8pmDQ4usG
abu2jAvcIErjUofezaU+oCrFJrU4lqhiSHP1BrblBTkrB0byyattKmmO4LObMbjy8PKiHu9EgsJk
Pmsw5qaifAiMZEACfb6cusMQ7HhyLOXyBTeZJ/4FOWAez/pyjp7ju6GisB2S/2ykTDg1nRnMMjq4
Emg2ZozPi6KIubWZGAxXk/TUSuL5e/0Pk2YGcTMzR9QJmQMzk8hl1w5l/9GKggzSZcA/KpBKuDpK
cqNAoOPYjpbOevB5Yti6jibIKDIuIE/6CRRHtq35OcJcHIYfWKweGpEkx+A+Sbh4HXC+tjsKPRio
UqP+fDAdTP4AFVoj9mwRRPKTm0CbtL6Ao+FTY93yYG7ICmOGRbuDkKFxbjuBKHiM8lMgnGUGf/fR
yLsCdVl3ZmJD660h4d8Gk1LarPTh8GQ1SYNWn0SaciQ+nMbxsnczRgCZGoNguKwoBtRHFt1vnfij
qsXgygS60iKOiUlOYPzGUU5lr2ay6RnQAl4gzvgoxBst8cZgrZr+ViXWQbxVOIskZUEpc8T5o8T7
bhnqBfO+17wYPVCg1Hfv5YC9VoZnFBk3DA2dw0O0Oigq5fY8D4i58f3RoxtpUKDK5HVSg/7hgzn5
D8HLoyJCweuqpDa210CdW80aVIxwe6gdDCtf1Asgm5Fc9OEKyDeXW1YMQnEiPAjDCRfPKWJ8sZa/
DWgWMmpwbU88ebPEs2791pPhjbokw2QiiSLKxkYySRtBr3wc8+nrZa4QJmNKeQIj/k39QEJI1x6F
w1Fnsys27uAGcXfuuIaK2X0wUYg6l/CRperh/NWzA9/KRs2GIqp5cbnuwIhmpMxApvVOnKmLcvbr
kg7N3gbJqNdzsOi6o0PLwdpCJ6AgAN2n9tJoBvuMVf9IbFQ6IHNQeVfEyC56mZwsoQHsLtaq1gKl
9n9GGTzk864qZDX6OftmMnagIYaqQ9b4vtsLpBATjB7xl6MvxCXaC7M7SZEZunryHSz3oZqSt0jl
lqRi3AQClBJBqKpVOVGd+iHYUJgOh5SX9r0dHa8N4Lhn3vnskJIiITMhJfbul7sXL5OcDGpojD1S
wc5BNzMeOoP7eo3jeZ4kaKINxfGdY/vcxQBMsXkDEcRcjHX/NVRIwwopMrC/PLdgEY4goonv0iSH
8fwxNhYmC92BeYwsspsAuOaidugJSn61BgeQUWGUGtDpdAOPb801bOMWQPcGuRF35U1czQDKG9vs
aSCTawlZMMNPoJc//Z3Z29E8LuBqobefMknZ2Uh3177FNJ5lqkZSbCeoKXQndTd2faMAKxAAr56D
c9RO/ur8MPwbBgeAlNe0m860E3PATfOsHOLsiuigBXuc3srNJYySrGZ628uC5n/oQ9M2m8RM/hFa
HHJuc+lA87u1+TNY7Do684v3g5jddNjkFZuESoiD0CKS/p13nHEeynN3UsP4tYet1JN0q7r920VN
2iu90FT94rKv95Ape9lIpPNZBuCzcT4HaQafNMTx4Il9WQFPu2pMBcpaSwCd/kYQQ6+dHi9QqRbJ
QbR/HjVHXNrjCCBIoCRJhRUgesT3j1kKjmV7LacYtgUDfmVY9hZwlfJDNIgKF8w6r4W7I4AGgpXe
pEc5zXWUzVuHMu1CuaCc7AJEI3phJ9ISE5tLgbBfKiVRiqi7Ab/ZCLAtF55YaXiMabbBJfmAHGld
OU4/hQsE3AZ2/DyeOKHkNSJxq9TGFYuO+63tHduTIUBY+knLZVlMI2SF0PbRBlduyBJ7shrbnMYD
mK2EdSPl0z0d+9CMU11jeizsfNWONNBzAMPQro0rDK4zNyiH/VPj+2n+78HReEplAbufqiFDZpzv
XROiDMCP6VJDc+wQWka3UsI9hz353ivkDzmWoAhiqmKFW/TUrGLsh7At1SL2PiLRYFg4plqs4k6V
+7WQv8+G59a4XpkiA/GnI5jJWBGJzv3ZeU+i9oWy/gaEtShiMwsOXkh0aZrxbCOnAPq4dpJzgipp
/HQUYpZMKeH2aN4nUj9GkhYfhVjrWz8ttu/zlVp5bmjucIiRqDSlM2KJxMLaw1uRhz24X55zz1fG
9RmLWdtgc08P9yIucUzcb9ErS0YLzrbrngU4btRrUQ9UY0kzBl/65BxbsoQxSqzvRWShr/foQKt7
ct5dnGd6/OQRu2T5JoCwdAuBAu6rshuvRrbnsob0izayB3b5dFdcWQ9DzCgV09coN9Rz0fvNd9LM
CBHEjJ7dMqCcWFtK85W14NzTrySE/7wXP2ph+z32TEGT0aWI4xUHa3525kn3lKLhwHYl5dZNTIix
n2nc2st8BrI2W19vA1ec9xcbqmT3AziU6HbDuQsvWePuv1NcOg8FR5Kp0AiBPJyXziDv5Z2mIL3U
CRGYcBbeQOXdzsqhVM3F5sjbjULXJvWnp0vN5BS9b7qKZF7tfXsHD8Hu2RD4GvWC/m/xrGnQYSeD
hc6/1l5ftH4X4560bUlhzxoGfaHHi9dac41KhH5CjpqQ6p442X1ra5Ov3zmEEXqx5BfXnTxkrHWI
fFLYBQgHg+1MBdM84X1vUntRarDOb/hHQeVKy6P0qEOmAyisTYuniMn35qe4onShSQEi3vUwD0S/
Dem3zANBrCiYnyXU3RYBjCYXbj597hw0ItJ/czgNuV2hiDTQxdUrq37TdWMYBrivvbMcEqSiLd/d
jAh53Y2Yd7z0Xytg4U4wyuuVVxtTz9+/rnv4Ue43ihBl/TZdziXUBYMYnHkDskq7pubbi6ClRBZQ
Po/gTsM7NcuEpAai6dTNRNqknzxaH37vVZ55hPuusg7ZsED6jZKli6G4zYiAdmON8ARXnuUC0++L
PASZuoB6iIT8+Wx87FxisFeH9t+vbE2QumfjxHMtFSlAy23p6wLrLS0CsQJOlzOYZW8cn4Sp2xuh
H1XoMsfxu1p1qSsedoE8BVe7kscytdmDFXfR8XJ7k73+WJqC/OAf5zJbyFB+0rDTu+ovwPMo8kX0
gDEAR8dQDZRHc6J6nm6wJe1HMvLVJdB4v6IEwVmz/HgvkKNgPSCjtngSAvogASe7hpq/zL+ti+an
8ab6nUj2SQsfn88RZ2wpfKqBR7kGO9U8RbmQTBUQXZhzeZTY/mGVG5DaQ6x9zydbdc7uQ/rxfkmT
aIlj0ctKRHJB4GMqGiNQGRPmmrYCwYMQgirEE91Ue8I2v3iW4IuwiE7L2zlHz+AtesltjmKjeYPL
m76knsSVrV9ZvtMCCQ2TwG3VWaARP9eF61HTDa3CbcAA2RY4vx9dbiyItRGLqFddsf/H8MU/xFK+
S/NAUkX/LnLfejtKkXgF8tgDUYruKC5bNNmHePJmIdvoORU9de1kJdJ6+GENThcV9aUo/11WgLCP
rl4bAWgjmwfvI1Dl4wUMwq9qFhxUiY/KolPzb5R/W5elbdIHwW4FRPw5jOkde8nEG00n8ySlCtyG
aCGuJ4clOt30mxOKjVW0TwDX5GX6zxAyYL2OAG+F9suSJXucnYlASrBBsF+y+s0aQStzoi66bajd
Zt17kVg20XRqzZTwwfl0fwq4tv2NvzdaB4mtVYwD4vkoUDuk/6U8kfN4hu3nzx4uidA1rb/MOjKB
vzDoLEnRbRKAw5D90dSMFb79zF4T5q//fNcTESq7K7jqie5WqaD/3Yi1ASTR542uECF20IYN8KFt
1+UCYI+/Rm5PJo+HR3IdqMRmQVRAlvlOq3VVjgGM8EPClNPX2DvTZHu8yVmpnihgEcNwYfWFHjdM
4m6qimRDo7GeftMrq3KmsDx3Y78SISxwLtkHX8DeFxnguZ4pCbC/+7IaWZPFtIq7ccsyY+vDG40U
ogWKBtkOeW0WARdx8Ow6c5Ox4LAlViso3B4pfEk7MU2OzdLxIjm73E+yh+hYHQRjYgAfJNrNmoKS
M9TDAlPvOm4DPaE9u4VBORiiFPKr1eLj6yaCOpRtLRrVY4ZrVBeq2cCn/PgMBUPVjWzGskSaXUNl
10eG4upyETGT0tFhaNxrj7uJH66agePmFsbZPr6gQDG9rLnLosqbQv4cjS90dvq8D+WhmVnNlBLz
zBhiuBFT2Ph8ljDan/Sa//DBFYa8oi9s28S3Zo0AdwPJQwotu/OrM383UGbd5/RaHctQyLMQgFzD
U/QYLHTcxf3UGwb+m5YCQ+ESnyeQ7+pdDRDkqM17cMxUSbVcvK1PUL4M0DhFvvb+YUvOHVNl+9vI
49DsH6gnWlNhUdCUtTucRTehg1NVqmOKaf2dvC1AWBvZWjS8LTEBsZ3yK2wooge4cKJGlde12ATS
QQdf0wLmVvO6ucKqNVwORzO6KgWV3A4Di9XsNHzJAkbehT2w/BDAV1ghSjJgu7yiNVyw7C0OQEUC
bpKWYaf+N4TAX9gGIoGcZZ1zZon/0hoqs3u0NxTO6Jqp/aA6dHGsFIqPVx0sH+ukLl2Sk+TP8I4V
nncZ06Vgu7rOIGn3cLOmv2sQzt8kz2foUI2C2SvHVTut+ECpERiulPA0McekRPspldTbhf0JpvK7
CDJ4HzSmPX748awMttVpzlWcfaQ87/mcRdmehThrVq1mevlLyO1U9skIrO/EcXwc8dWM4zgFoYKO
2rL8OERphMMJxeg8G5r3xhzP1+BccT2k3UBPv8g1rUAR3GKVFWZ6sfL6//6m5T3imlYxedvHnKfr
05R2W/fl32bmF72O9+uXN6CybrJy6v7+I/KduGdDK+cMC8M5aniLTabX0s/25fCAGb6YU8d9i8vJ
AD2sXXFBFat9EQi/JxPwKQere7x/J0wgL7ZShdi112rN4GM7vBWieE4BbSfNLqjw8d1TmPaObxBp
loXZ1ZnqLTB1c0uIyNPN2G7jAj598mDBLGIKYXUc4/QFQBbu0nItp+aF2o5js0TlF3j3mqdjVakh
QV0wIc3VRdEeixF0kOgvlgzAbja6GF32a2ayVny+0flOQ8/MxDgANwjz/5kFggYA1iYeJ4ifNSuh
a+HuFWcyi3lfE6uTojgFpPBWHpfGDW3CWq3sFzpuO1utJjY8eMUoYtiY9tMVHN8N1sbcX/OD0ZTV
A2EkFfv5hgnBqoMDIDVUFg1T49xa8sqABC9vA9dp7aBqdjshtkl4cftogdxBjoACV2Ab47eTnrNX
imVdFdX41tKUmh8TFTqZthereCqYK+C30ufAt59k/CAvFYaH6vLitxUglpKH1ore8cqBQyNJIC2z
WVNbZvOhcn3MpQ6xFX8zDbE1l04+c5JIoVXlS/s1yRDi0d+q+mqgBfWToJ5brCEJHvV8zoVRa7aY
Zg+f9M0OJ3nmDJtyd2IFmoFh5lP1mbBN2idI+RpEmY39UOrSvSNHfDk4Ym283nPIL1F97pCOE5au
E5pmI7LQlEfZKzn9ceaXI60Jhhdh09nSjLnW9WSHCoqzC79fswrMu5QizymyApTWbaruySi2qzaZ
KyjZWGc5u4k1Kbf8WH4kKua0eK4IpPLs7rF5WG8xwT62mQYjvxw2RDlb14Stt1x92PQgpBRV1VxO
ZlKWHnHi/7//pyMlhheCry31R/0vTyKbnLGLc7caZh7AlzkeAIVPNnvy9WO5mo6acHsorSX/yWph
QKqFJHy4fZi8YTn2dm4exrJdgGjXkZjgjlFSKZ3jFTTclXo/QZRhNujErXxWePRSKXlw4/+38FSZ
tq3BfACboQDFw4B/Ehw3oS/Pfq+AU428w0H0tjtNUGWfFoivEgnsX1Vxs3d/x5+Ruf/KlSogTp8B
SW0wTp99qLcs25m09vRHOmglwdKZQX6CRAXSUxAfTQA77qBhTJVedAq/ImAmJVFofI5ganvG3684
XbnUosJpbHNuoS3n8OPbWYoG+5StdIVG7MluiI5emYLdBRUfX4O4PM5FGHbICIqbAXLIGFDobigD
2pQYNJun9xq6U9miTfOayecgWTvh5AtHLWRJ8sPqL5oe4hAfQdb/Rr5hRi0aod44cCThP8MK1lbt
q+blOn5WL1zE2XVqn/pZiJo/Ckh1BRDDvyoxkKA6wX4o/ZCaMVaqnQ+R96ZvWYosk/FlpHkcVM75
Nb2F7oG5Zci6SfZT2xWqdR4pzgHtaQsXMINNTYwzuDsrwzSJJAktspPHHigoEmcGk/RkNgYJ+zHr
cp1jFzoY7FAFg6JRYZh9Hzvq+T70p9+uAkbQqJXq/dZlvWg7/we9k9LrDHlMyjwv0z+qxOyvkhpn
McsqVC9u7Xrq7HIDqrhwYclfNyKOOTyO33hBk9Wojj2j4w9fscPWKXRO9FnBAhErtg3+oqSBzef9
FzkRLfLxvAR8uyl+ZvSLL9pfOCird8ygljIZmouNtWIYuuKcXlgxh241tHaSK621MNDyPmLFb3An
y8Ygpm6jyS3w75RAPgEOxALzUZiQgabE2vh0Oy4JRxQ1tmiCD9qfgEtGNC39Ezsxi0xWiKfV9RF4
I4zk+j2e+00yULl86rlmdAYYuKciN/Alqrif24C1dzlLrpg0511Pr3+XAzLHDhT51Vg6npojXtFC
ngguGIWn+o5w3rZlJtzrRuvW0jWlKVQfYD+XL+Z+qR367b6N2ioD/yMwZbysLSQVGiAIQSmtgnRX
88jVbySypP4e/1TWvI1kHwaTi8x3/Wx1NOOXm190YuKb+9gaOGICSe4IkjvWgTi4NvwC1dFGXLAU
rqvDltoHPin/djk0Zy9Sk2omqlpwOxCqwZ//rz5v/hkX4IX88CZY9Zi/vaGjVYXixAIJBw+ndC7S
3q8IqWsELNlPfjPPeFlnA6hqYpTdUsyspiLMD+r8K3GlIGRnwMnrswBtw0+RvjyyS2YzIVj+5WMd
JCuPqAGm2f8Y/XirxfyeKFgAAZMDcQWG54QltMJlgmXJMIzP+NgnKbPlkuoIngFbFSUhDovyZA29
XsLrCj508uKsAEFcFc7dF+KqJvGUR/asQ5uB7+tatqXQTU9Vf36qHqO3gbQ2Nq5aKkeVIPT9Tx56
dcwrrgz3A00DuYzsPN3Bugk3pCJhUyKz9deD6TF6Jiam9wyPAA5hmFZJ8m+LnVTdCWFPgDCIbJyN
DHWwxsl06cIA3837K+2hFI+J5BrF5ikJmac131tX+hU6PXqBHD03mlbCNBVeBrLkjdbURAguAaWH
ZKBFG16LFc1PXsyUml2kL38X6MBn1I1SfEIDLxhNFs2a0aE1dAoAG/rEsb/OJaoDkLwQORIOOXOQ
snKsMCFs/GdO6sZcv9OJpmvYlFmdIrAiOIiTFPUaFfP4GPO0XQ8lbbKcXCAYWGk35pujaKSeRhe7
i8TovTSynYglqE6EaQCP7cD8GXS4WN6Xjvhy6Oa4vV1JKYCIkyOibPYjIGdwVXWQRtcMmX9ZrAmq
OfO/n/mNdRHz5nbyN9lbEteazBblaEL8Unm6jOnTqvuHCkmr0tE5Inxjc/a98DCaYLyX4XS3C6SM
DLD4gViV0Zib6yD/Pm9g+U6m/vXB+6MVAaCsDuo1QhJ0ZBzazOsq11O+pleR5Hd9gZl2CYLCkgM+
CCLz6E+f+OKFROQbgM0xYvfpB72cRZdmGVGQdQckYwmgAluzaiNtP06W+3+kjKoRHhCBPxXrzGrO
tXHcLsmA1cyNigwcFdyYfPZDgAeAaeks/PQSPeCXyIVwFjhIfLC1vGWDGPwbRXtIw1M8yXaSCseR
2XGrSiIj9OBKPaio55KvUH8gS5XgcBRI3iYp/58Q0fCGVKGQU+MfHgrY5PmjWzfkiNakogg1zNQj
kukM/dhHP/9hYUkWkp3lWJO5Iyhlplrq6735+ik3PJPHjsxZWgqR4VW1cY0PPwZhjb/FX8Vtgvwy
WCxuwld2/id/4G8DkTsZ68iyoSe0s9wPH1GQMbxjYwUj1LSqHi2oGeP2KIYTiL0g2LCXQBTtIjz6
qJne/kC+NtZh7kyKySvXwAYMTY3hOKvk02hSpUREqax8IHNgrgbkvvZ2ihnn2W8xRe5arp6KoP5m
WSUmDFxdA2TcHVEBau4s2nx3Uj3WvyIPMhxaC4QBojSL1Vny8qsxFcebNoQTFTBZZpQS+uroakDI
nnPsKfIHCRZWqvBlhBYWBvIkukv3r+H5gPTFfciaLtHTwhfofbvgMnReaCXaNYFYwcBX5bvF8s2l
IPFfGSA1m+o0S5+L+/xI6GK4Pbwpb2h9C++DYb5Owq3IbZHsre6E1i/jIMIzWkeQYHxccf0NSybc
Bo7rAvHlrKsZ3V9HCQ7ZvjxyfqOvXw5t5PF6KFjI67WZRryOo6H8TT5ICkJQK1dacumQUNtYUaKo
q7BVPK5x4SAQJIvhjiXD8umhpGvvGJUP11jBMibbbeA9X4URqDwG10h7HycqrKAk9nCQjozptdD5
EVJQASnCXZ3eML4g/N0TTlRfmrClV02FT/EAAlETvnCAifkJIJbRkCilm7ijT6sPvbQJso4tkIlc
ave/dVfry/27l3iMLqw2xUJi3FN+g2+qJdD207FPbDeUSQdPHv4UFx64QwHO1v/NcumeY/uD1q8I
hglLDgMNdWxg+EL0dcFg7KdvTGuxm81wJMYwLpd7jpzoJLWq7wX1S8VVaOLWoIGCg2yl1LBh2Hq5
K/t3qEozsMDfuF3i6Kv+LZaI8MaIpvY+6KG/cIPJVu2mAyf/FrSfTQKQxJ1KCGM/khY8fi4GJboA
h6la/u8ktfmNgEstmz1wrlmnEPnmBB5D5YdRFTCabQYL3D8MLg48VZtqKvAFjB1MoUKiG4IWRbv8
mCD+P07EoLuCE8XQJBio9hJzsRAk90ZjOwY1mNpwzhHmbe6i/DOAsvYAfAz0IwndfObC/ED+qjGp
f6Y+A3W/F5Z0+p1biN8I0NbFLRRzNbMqTGkI0rytN+7BipSQ8J0eAafzgKiSpEuNHpaIW6LD9Jfh
OomtXUpWfDwQGcxGYmbJHdC9f8WjVhbZQwijBgyvYfQPlDRFpkKl0UtAVq5ZoWdYtkcD9MZlnQ7e
n2JZW3ye4ok3O4UYDqOiqceQP+29RM2ZH3Y3hvTPKcqbe92mrtAt7oO41ExqeX4v5Zya1WM5TSiS
8Tnt6vuVTz6qWhdhuvGRvw7GI09nhG9KnfLaElu+HK4FxYLufwTs/0+TPjnD4YKTHyxkHs9N+OQl
t23u28u3LD14mg2kTdYLVMUSZ8tEjyepmY7Cq5erBNwAIaZO240kDcfLCo9G0C6REqC0VH9KpGRo
sss+iupuS81WRehrbPrdS5rk2QHgBwWQbR61zzHuJFnpWHmAIdWvSWf5c9njPcE1t4QqBahu2kEB
YtaHCLodF1IoP4mMbQNXgDY6TOYotrAKvEsHmjjxxys+tg9Sny/WqgRuObFrxp3IA1q8oXL9VGgf
Zy2mQTs2jDV79afH3ORgl8N8d6k3Hr/J2qhHUp2nwqE99imjLGG9mg5VMT8p7wo3VfriFiofk15B
EYGvgegOUE1a10Xn8NP0sCmorR0cp/wuv4nOexSqvfOXP69Fgn6MmqgIZCVjO+8XasL8i/e0F5jZ
ekb/O7HEE6DEvJpboRakMjVo8W8z3IzEyqasGzuHh7te0KMXGYda3jv3InZOaR4tBfKdoS6ZmEpk
Jz+Fa+28Z1zPyC5RKm8InSMspcnag56msgw99bWFsU26jqRWPINZa2zIX/3yOAqA0eV9uB+RP2hy
4assQ61D0JgILiZng3TA5OB3R1obFt/+4IoOWR5vpF1oF7JJs+BvAEc7NG5neap3iJq0db8Sxj23
mpebTrcn8/K1aZYGcGRMMMhHe2+rB2h7MdLtrpgLO+Ygyj7tn/rP/XluQVP93t+BlUFpMf6zoNUv
u2cpG8NehpYQxIPCXhJF/l3OGaX1dW/ff4m25AradVvfcDfss7GTjTP1oOjbAFWo6/K3GRDl5nu0
ACD9Q9sAII8vVSMiOb5xCZhtecjQ7nCnukCia4+SzPtw2vi0IfX3wmHhPdVvlISV0jF1o+plMo6j
3G0Evq65A4MRMAxYKAp58TByYkGi5ZrarBVhJJ0Rp/K8TDo4JZF7OWv69OFow5kVxORyhrJ8ajrz
5rMTUzjjr45PbGiVjlknLjyJTB5B+vctifi9hpQEIWnlnMRnWs+DChAsJxMEYAgZhLfBFkK3UoaH
B/7c/2jPSUV14GpsVg4GGAkXW5f0UoUpwMlpBHi5Mnw85NKgk2jH4sOJCK5/YNPaFoF0+w75VgVp
mzTINPFFsVW30MWA1xqIQDDwZXA23eW8pY29CGAX4Mk105LnKeiYMErOzWtD+fEShzRIjZZfbDmH
CZa2SqVerBbr9Umcfl4+RF/U23Dw+V358jIgY0LvIx9GtRUEY9w2wMdvF4kxWjQJc6lUrhaZsqqZ
pgd8xIOqGFB8a7/k3hWsVUbJA/qjqYe0klIpmlkoCwZESjFMukd4otXmtvuwVhGYdb7/yfw67ev2
Pr5o1XjHd2Urc8PfRXq+W++hJcN07df5p42326Y2PfYpR1HgpIfQDHTw8fxTwGXWzhASGoBKewB0
7PrWWy3yyZ7Lk4g3AKK7NO9tSXL4TbU+bZAeIWusUA27riLyiOfx3IVQ1qQqAY3A7Y4kFvNcEJ1r
DzdeUaIjeM4XypuklYo+7dQFDUt8NlxCGcirfhLKSu2034Pg7jjG7WxpHLMjQ77XDQLepwqh9fs8
iG6ZlfG7tRlX/RTE8wnMyYGGZTbWaAry+FHnUJOSsjL3qLtu1vb4lVVT5ZVTcR2qNBJWNO+GCtQw
nMgpo8NyjKtkHPcj/NarEXvolyIwzXqmOU7ty6Ag8YbcUlyzhENvjISAQ1kXF51buZevCKCKSZ5R
5PnqJiwL/cK5xH0QDv4T+y5M6FUzl6KUAK0fC32ZtXtoQQnHI/BCX1nhKy4OFV9Oql2IgGaYlyry
HWqPvxRjqo/hZaFmKb9J/4wWDcD3ZgsKT74H21e8O4r//TLVXvbE1Fs3wjFdNv8YTmZPRTWHPQp/
YafTYN7u2jwY8T/vhR71afTfd0ZVzBDLDBU76InwkxsMoDyd7MqBCB/NOX1DjFraRrBbuZDF8FdF
pnsxfnXcKUJY9S7RKXAaKGAuagEw+/00He5abj81OepGfZS2KYLzgiXpIRcEptyAAYFJsbUBU5Uf
SzeQPxKtRg0A2vW0x1Fo08yjpJad3Ws1fDaPcNPPQFWaQBquJhC/mFZZHEv4RRlSjsJ9645HyDZ2
0HNcJ1gtt658ck9cjiL3qjqT94E1+rTKr3vJCVXvnt7AuF7BSSDVBO2hW/E7JWldz5CS+myQupRB
sRQzeHrXI6TabcvOYJrYG7YG6c6SKUtemGHBPnWS6leRzLfXwAkHPWlLshNAu0yz+ucElcF2jWMd
PLVPBc8AcecsLPzh85bilbz6nZt2jz/K2w/vThQJcUGDt8e2Noe1WD7qe3HqCrHt8GmD2Rn7dkTE
OdNiF0fc2WKPj0LGfN0o2jvMfgrxWibKY3xMVfKiFhB+cgMuaBV8TZHhgPldElrzwxTpKgY73Fpq
cVbx8gFzVvoWa1UYpoGmtNr8KglxqEBD/+QgDAHe6j5wCedOz94yeVhyyOz0FXwclT7X5O6S1m4F
kbB+czmnsHOMuRbDUBG5qGsyPxqClfL6OF4OueGLGFY58rAMHEEHsXCFyWgGSKeIp3L/UkIkqKsD
T2zrQVr+5x8sWuKjRdnV/zPOSourckqKfdN+dBaKcDR9nABjUuZbfoNx/q1nyRMZyAJ1v3hslgPf
ip5Lz6QOgNBHpuHbgHpkp/vxyPJHXxU9gdW+12cTaFdHDL+PMhgkL9XiMRddbyfzRWoU5o0ogX8J
FCUYgEFHMQqLaR0Pd36F//Jm+oZZ+wLdmCP/U+5WcJit7aF+lMvSqy1LkpkbGEas3jUkLJZshqKR
020myaOg8e2Aonebe/Qp5bj4opV5sBISg4I4deKptzFWjJhqkJhvv4qi/b7plSH9IPcpUYqOdg9Q
V4WhmnGjEVNMBRUnYgygFWxnESymihNZyZwcVCR23bniWwM4SxVLP3YAwx+7WbfRlHmy6zvUlc7L
xXrwXOZj15Ml5vUymNn4knNYe6js/MuaFIHMuG4pGv4r0GFBAmx4qcYKaaLMiUVKuzyQRjFCt7SN
I6tk5g9/zbYxJ9ic16wKPM8ts8RGYCWYY0cy1MJU2Vk+Q0KirJTTdm/nzTvX2geMsKK42+0Q48WU
62IQ6auBPyrdLiMAHk2otnqEfC7uDKmK8aaaNO4gHNGMQ1Nfx81ig5pj4CCZi4YAZqfg28cb/6MH
MyXMCVv7Mco+iusWfBIb20CdzpriVT/olFE7BEy6K1bY+yO3Bi9Y/16kUHRQCxjpOZgfGnlKv45S
jTE9cWFBzZ6hSC2bCpnghBsR6/+GJx4i357CaD2MJCjTZ0WcgfQrotnu5/jqrRtGWbYoWTVBIR8W
76iwXnXf3ck8xjG63UeeHcYc7gnaku0wQrNL9LTsFK6Hg0L09nbWznDslVDFrTdHarBYSnrjX0xp
C/f7A/CR7kwzppuZc2+EOka+BOtnCjJ9eYxtU2/4A7WLGbgGf0boY8bUe7Ke1GoSz6Xf3j/pw482
JNx7Sn80u9tsVd0Qod7rTf2H95cX+6kJY4br1w8JD/OIwGR20DuckClNMj9uyv6VcTj+sqzaLsuk
IkeZB4VdgQL9pBPOdqNVvrV75jlBN/2OsKyKgLGmfYbPgGtaCufxJRdI/0JkIqUbAM9GLuySOtkf
MShimZNN0CAd8Itg1GK9+C8mJ+0hYwkgUTsq0wU7goJ5iefoMrMim1QThTrl+K+gqjdjZjwwVy0M
cM06eY/SPfTMbH4FGjG3GXFuPyweGOSmjN2I1gtrpV00K5PRTD1TZRJoNgPcEYEQY4zZoUch2zNV
CY974tAFQRl65T0xH6FfS1gsdci+89+/sUwSFN/lqJ1lk6K8Rqq804vef0R3NA+NHEyOZomOsj8+
q45fG7R1hHOs5uD+jZvwzmr6luvq9R9VAnVhgyEOjn2K1MZ4GyISNwIVoEMgE6i5gGwxjZjPGk8Z
g1NZeyQs29fe9+Dzf0xKD2Fy0VUAZX/Qz1jK8a7zwebj78PE4zpCMONC1/5Rsr8qMOYX5tVYYwx7
JTOP3+D2tWQ70vLKduNOs4B3gL7rBGgEFCNul/XXMw63JtdB5LMbv/AYqx7kT1iquNzyTQJmjGhO
Yg7r96heX4ZuhyKXM+2jk7r8Kbx80fzr0QQTq4DcMFYJmLfJdHm/FXBrKsM6nAhiyC/c59/jbvgw
j17Gj4J2kg2dth+7ZZZSRM+grMvwLJ8ljO+MXBxBfme9TruRG3ROTybV+TfSBonJOWotWQIsLECv
jsJMZ2DNeVi+oyE46Sks9vertZL3nIoddU6ab6/xvb3lYMTrGBx0mlSIPjtJxvexBjjLy9/tgMDK
EKY4QiExjpmAl+v8ns+isyfAgm1I+MAFoTuAfKO783FrYL+BvwOIupD1dIt/QcYbHQ/qLE1jPc0x
9+kYFxAt/ENxLvtCpaPKVLO47pfmy3ya15k3DSUn5zW+Jby/qDAvliq19AjoU7FZFQIbSRf6Z0x6
y9GBEdqqI2yazNLqk9JxmoLIrtcrJWT2PruAK6OdjPOs/xq9nRWRc7ByuInLc8mATpwJfnr7L15O
/Pt0PgnIRfLmccjb1np+ay6fDjPE8BeBUnGdLr7Hn60Y1Y1OC3RQ7LOWnybh6Y4SKf57DfFKd1OI
bmFbRtrtiyVuuhh+LXTFBU8C6x+M9CwDxal/Sa/gTqNZcjatF9RtrjECpZ25ZxNxsv79sg9ZQpaO
TkKP9MzBKTx6q9VvjD6aqEZaEQxUaFmaO2AhFRtVZrdjw/Va/3c+yqefuNfQsfihxWZCBgPBYfPr
0lvfKTCNULm2Y+dr7nOJc1TLYqfQcRt1T4h/sp17PVu8PfpFkp2Xa0UUjG+tkYWMhr6LAh9MncCf
lpaXWaUeJaZ8CDm8Hk0UpZsAaBRui5UwYldCVwLp9oWoanr7Cny6ImgDx65n2zpXYlaWRAzfbGDi
15NO0I5MlMuDuzGwq5S1SBrygZGGjbK0JhSzHp8E7eNWY/apeRV5A35xK6F98qpAo3sts//aVNqp
1pQwBzfgufajlPmc5wuuMTiVlBPsxb3+NYGy47/OG8KX4/OEK29MEJwlnuY5r8rwNcRqUN9rWep2
HHpNoO5YdMn7IQrLzv5xAEZ8uk9/ksM5NQAEk72YMEQyIiHT+hrL6+YMz+DoSP3oFR+wtmDROiuR
OJK9qqtKG/thumXECgQAsGxMMICbqC0MRbAyLHKp7q4RItMq+D7gx5Ml8lZpVD0ArfQo9z2jyPhR
L8urqim7TvcjQBKV69Z8tWYH20Cd1DO2Aq1cDt3LkxDXM4TV6UfTiJxCFsfEAK9tA9Ng+3cEsLSB
favK2mIybXSA2NrYjbc5N2WhIqx0p2o9KxzItNoXjhYa/AiNY4rWbInr1L6ipABLCyW8P8iQg541
iloxAM2Q59r3vNyz+jxvSva0iJbRgZjw64w6ssCxUfng0PcXv3hS0T4/qz5vLBz7FkREMWmMmGrz
IuMVpeoj8fsFPkBUJe8Syys2KAmRcdGAvvpe39TgAT/5cDDS7rb5wNO10kcgLGPBoC7kBOB9bew/
Ust9tSpQequMcedIRJqi6CUcNi/qICmTyLr1vu3LF8F5avgr2bFirbyU7cJAQ5lonkMV8T457l3B
MSqb9kGTH3ydu6n6JbHHuv8Qq9U1cD8qSEGopK0ZyoIi7EIQg/CXPLg1jUKGwo9BinvjH9dDZrsR
MBfmLBQYvgk/1zWyF4wRBFc6MdrfF08LpY9pHI94WDKb5H3ubYfcT+nRS5fpCu4/5AT61NvUGjbl
qphhuUmCJl43nuU2+vpzvjGRuoNY+CNmd6yZxn89a1S8AHBC25sc6eHFTtQ6FGaj8G5oMQVGOgTO
7rSQbN8AL9xEjNdU/2y5QTK5pUQJuazHhulAKOBA7cL/6t1boI0jy7zO/ejD+X7teFde0p+KHT5y
lTFrzb5ARFxuRJfBpU2/oZUGKed0U9zeqmJNAZeWG8hEreXhO19UKOPBtNm1A7cpiLTp41x+WMhv
vdf5M9LrF8neETVQZWAaIzoKm5tWGfF+almLYYvxVLjJVMgH4YIxb9FDJoyD9wcGf4cjsvhukpcp
YvDTy5oYuX6OYkriZFMy+Wf61RZPhGYicLD2DuIAqxnkxsyI5SAwPR9+qI8yJRXwgIKnYZf8K0u/
Kv8lHG2ktUCgFUNspwjLY2cnXtmjflsN8Dw31VLG1Pk1v3YUviPSGHqLValAvGp6qNH8k0cC/mt2
EAX4Z51bs+MjtJ1y0WhRJU3nIrGcv6CJNSAna+sl3o/mHt2ANgvF0qLUNkrcCc0AmlyWtVpcoRGc
rjjGTMlnmTnl3JenZH6LhfID4fiZX3N5dIhear+WEH/XiJG0WNPsyGpfMp9B6kQ7/rLp0lmKfEfQ
Sf9zVPmXkelcpg9f6SZMlW/cCeuZNgoDJc5YshGFcF9jEWpZ+oP1xH8CO5p0pNSNDCsKD6z1wOYj
Wr6Lu0/gIa+fS6idXZpyhjmqaLWncWT0PO6tPWF6pmHwrAvaBqkdBSu5YcWFFfuuCjI/pMEXEvod
Tuubk84xHNhIsbYboGILvqnRqg7jienj6vpWvHiuljaVl8crCrlbO8qbrOdJXBnEI6SniTQN5RqN
8tGQrRQ29KnQIB1SxUi2tt5kBV2cfxusnGflI+URGREG4rJE7HNU452Cj+nqBvrpeFJEiD7XXtr/
WH3k2xMOEEXIM2KemNzTVRwk/PbBYgZBfTVxm+/GaqPLVkMU7rwTifteATUMrP3l+C+5/F/Xzuy1
7RwQ27+Ozf6O9dVYqLgBUYcwx9Yy92H/wk4b+twlTNLv1m8pdBdkRaIigvfQLNtmiBlvxUZrhn2r
H+iULWa3axLjaUSy/y/2X1ZCOPpcvXnRdTfJDErvLbjEVtqCjaq5Qjyw+vw+75FXipPDyIUkANpE
ySnx67owf4FCAouivZt8MQhwXbwH5DEKsYXsIhU8XA4Y0UKLVimmws+VU1eq5Z8QJBIoaF/ejawp
+mcHnqWx9ehsZf31SP6GUcXOu5l/NAfz7o4Zf3qeN1WijnEWaPi4o2bwGiehC08q7i0zImVzOAU1
givzsemkYHYPDl5wNU57r7P+WYh3XgTGPd4w6DEiORwSMH+S7PVCYFCKODOaqvtfHHMyucBpyg/B
RXcxhZaO/3oE/fPiU67n4Fkp/AOC5lJxkIa4Au68an6ScgX1b6pZA3POxeJirL45he4LlZycogM3
qXOMuhkBQr89zA9r/or0jzSmcdiqHsm0xCccApTeqXwIdIAy0lvlLZl7pP+q5HVCG49RlKnunChx
iWd+PhlOT5Hj7EgKhQPc/87umkMMpUGVLqJmlcWcRWdGf8f/PUwi1ob4ESdGDzU39xR9alZkKmZy
0hkQhFOoysikGewljc0QXZhqyzbcbBaJ0NC2HBNfDJxSJ7OfEyXHcQxLi8KzRtcTn1UNtJxBN7pl
GTcqiQm8SOuVB9wOWXb8Q6U/nePmAJ66aFbgyN4US82WX32AzkWmCtExcHjz/+R4VULW9ZZwCSpk
lsOIp2cm3L1XyaovbVtlLT/zlnzbGamXhfEcdo1+NniPgd9hAWMl6MzPfep3sBkutZJk/SJVsJ4s
x8xoXCZwtcrFPD+7j76+QYqBdJnFQYOTWWv+ABYJmejEWUukNYhzVvF6Us74r8U7y89DIRpBJQEt
ZbOIE8fyQ3FDE0iM7FiXF20kFC2xz9DfsikkhMWag8UsDWNLm/PoF6V2f5JApo8sjKSSY3rcjOlQ
L4qAIMgq1NuPALL8BybfVt2X/BBTQcMXv7cemdqSauOp9Tw35QTe+pG2pLhIwsZBut/pAaerwBeL
2MHZDjzHcH4wMrMEpECtJ8LULAGNr4Noee4UplTeSDoesIkl5g3pg7MUS6Hs2wdH7ZPkxvu2rAQF
Py/vGPNYcMMBDYarZill44QXrVp163X/KOF8tVVAZoaKeZsC96Q6OwxkmYo8GTiP22gbmKJo3CXf
ryIiocBhNz48FeDubFk3V270mnn51QpN0yzzlwOFSW8wcCNXu92LrTdMV1ikvMH++NwtZK9xPRkY
uhcSKgoa0bHZjQaD7wEKTbVp1238ZjmjTtsPgnz+Xib3fzJTE37X3eNYsplHm0WS27OkNBUnLU/d
my9EB2B/0hFo3dJ2SnhyGfVdUGH3NcAimReeoberTC3yfWZrSXZc2XlVslCK+rzBj3qRbjJBkT0c
3UI81drM80+RlCDdQZ2fHiyENd5LyTvyPl+WsGqU9eC0Lqn1uvNAD33DMSQ0RFX6HkDtGk7sHGfU
vmGqTip194mYtZEeIpPrYQLWFdUirCrWV/E1eFls5rcDePVT16z7H5WQEiR8XIMesu51oJ8Fa4Bw
RxlggyDSoLdHmUAJ6xL+mkW/HQbpZptt7NQRhZpzD6jH+tg08d+vy2FWMiiOqmQNwXQn30KO944D
b4d/gY8qYxCyZ54EwU2L+R9hIHaax8LT/A6RTNJTcmtunxrYM7JIvEFxN2Lj3TW1PN0Pwz7HSJyc
l9d4JseKnWSYOLDV3breduzhAqI6+dQ1odbWemp6pZpH/AEG+44OjWHDhZuJ/q9dOAw2XlrGmHeU
c7owghT6ZiUOGQ6xiI/qE/15Q1q7y5voV9ftdC1CD8j07vBwFLMh5oYOAVZ4FDMFLk+zdiKHDM7G
OWwfjGb5yw4PghDcmH966MUjEhpwKsf+Ji/2tEnJCPi8U86jxtVM9cKOk9jIU3+B+fMIA5WNKh5Q
yOKjW5N+G7dgOUwPczqkUsijp2lKbWtPyCHOoX7E9RL/wPScteOpZXgynTxwEywhmUYL3fhqDl75
P1wn7MyyOZLdkjw2lMfW/7YfvFOMbNV/Q0cKlkws+LVf+XG2VmzZIT0IaUC3i/5xysbcRJAdbFft
c+IUFnN1q1x58kaoyiTUURzoV7BmhNIut13kl9ql78nV0t+nW+qaw8OQmB02rXGDcP5e6H30hij2
PFdQTlBKGedrdfkQdt31pu7SdwbrAy/mw7XXWAkE21QOooLRGMlBplhVE9qCj+pgIOk+WuHtzBU9
pHZCZIM+yjyxWsTpOLW4sP7+dOj9/1Y1Z+Pg1qsEqkdoLgcSYVamoCej7YLVuKWveI9nr+ePLIsI
Wu+c0MOvKB80VTd6dPYY35bf7Il4m35fqQb8xQ/PvJ7RGCpUSgPBz63Lp9viE1U6yEgOUr5rMxu/
zuiKkZqk9IxkA+GBJuGn2FEEhUuHcfLk5ChoeAwwKrTfaCjRWOz7jzE3dCqDRhn/AdPUkRCW+dG2
QCOWQ70Ojx2MuB7ESJOLeMp/d5jrdKYpTA3jlpdLg5pvRvs9Z4heFhfZ92eDZzJN+2+RcICMGeRq
+8bRwtDdfCeCDWW82AYldz7wxbxKwdAtCWtbAiaL0Q6P1Av04TMlNYQHroKVsZJxFaVMRoTrZYT4
6TsH0Z3ktMyUAPpIgJfLfwFMiugBvlJP+fJjw06jDLxMW3zHKJVJJsqoOXxxYCmZKI1ez4GhaZGr
KUeejYCW7G3Fo5YhsDiSWbxKT1bmLjIikas8xoRYEbcp0tFPt+/7GcAq+c7d1N78aOQOJGJaOrWf
g+7f3VAJlX22CspKIN98g4AEFbkWLGStOF7gl40km7Hja+9aVrw021KwfLZH/7PWL0QGZI6G4LX+
t/86UyovI31zW214k+vRtr6lrwjkS9rSW+446TBBJMoxyIa+1fhU6wZftzB+8GUdEtUzD0GnXKjQ
60YPEwgAzYGYG+2a1Yix1StgN4d7b+V2gO1s6+TvvFsLguTj3dWLRwuqeZ74rO+tw8zzp6yy9VzG
8REL2S1vzpo/h3IbzbRN5ipinSXCrJ1n9TgL687cl95tLhKc/Jom6h5ggOQMFp3VLFSFdQVWoRIX
CUtl1aRjA0nwO5Vrw01ubWLq4UfQRrNYsJ68cr9L1wBQ2F6iXBSIt0hMY3ydK4cCrHS5sPEZVxpf
tSMFRuRIBXZeTsguowD7tI/HssLdSsHe4SU779yIpxrJFqINKHPPkJR8BSCktpeRPs6q2pYg5j3d
I/NS1Ge5sd7Kp3Eley/AjTuHL6t6X+xSwGzD6pHx8IAsG3nlrvS9alVkGU5TnAD2LtmdBZOjYWNW
8o8tHEvTSiJgoHRTbLXC2w7C6/6zdHF5kxjsUG5T2CSxmwHJx0onhJr1iXXVxzEotW16sUaBe10n
kQ0XtEjt8d+GpUDFns3YpisCgsw8fNW5gb5eEGkBcT8XFbOiWUe1lPu0wAzT9TLgfG0Ij2k/PAL3
F7f1pO3aAXms7rfkvM4DZCdSZbrn1QZciY9bPY/yGUs707ARziALPFsgG2Jh+dBSv/eK8nvQxUtl
h12elC3ou68BlI3kdYihZu30mwDS++mps3QUDQJb8hIbNTY/tcsPyirTgVpqzjkspBwnUNYLNze+
baSOdf4I03+uKGVqwzczvy1f8lvioMkGM7KjrX/bmlWfvnv3OSD0s+ZZHysEhM+umCsUueEYhaFr
pBIBYSzx3hdlGGGPDXe//+GZs2K6tDUooqsbamOEBPwVTnb5j16I5iCpNgCV7jPdCguMmhiplgOb
qdZ3ZYOWRH6yxOnMh/Bxk93LgqpNpMtsG3wJ4m5HuwNvkEfQN6TGmnwR4UcGUdZ1Y+bHiRgHun3g
dE2jylGO6n8AVvPFjEup3svRQ/oogR09Qwq87yYXNimtbrSFJETzWOHQWxbbVOY/r990ji/P/GXV
WwQi8A+OF74r0xqhaRuO0jozAzyp9DBDNRGal8G8L4VV7TbbQii4eUR3E4WPFHKBBeG4vEwTUZrA
De4Y07WIUsKgkFKweM3pBDdywYLxG0mMsUo9+CNW571TJ61CImBXh8HkP0xh3gpSPSe3WDT0r8fE
GnjpIkXJTU+cf+aYWDjeikg9hqOYOVrDa9uc/rMjWocBETX/S4XX7rs4E6mIshy1t1eBJzgC9H5m
HaADOP0ICcFgZfOEpK2/MXWIypsirVJUyqYAhGS3VEsfgejsdEMbD7hc/mnwbj5xfp9z10yAbEwi
Rcmpnka4AW1tN6hHV5A/8MQPEOx8EslP7UzoW+dSBHpVBzfSqmB0V8I+mVK5I88zrml2PzQHrQhB
KG9KeEcsRyxW2waCzZGAW1dhgMvHCc9T/4krIAftVWbHr3lipfCZGomKuPLBBgvhOjhouq1YtjE8
c9vpd2nsqYNsJiP+PTpyLXFi69MlOexSFDiiWrzYaX4WiDVcb+IpY4VvwWPT1FJfypvBQZR8YVa4
kfQEF2esNFvOkljudhEZ2kNMLbubSVplCacVAwwlg2opwr+H76Im1GU8ino1dGolrbfRf7X1WXQr
oJWAG4ZqvfL2FOnabyJo+AzZC4XBoPdsTUZvrZ23CXT4zXz/rAorygo6QLTdEPC8dgWokNQ1ZipQ
we99iFDAXpx6PguEQLkw3tqbdre3QeLF13SlRu4BG4KA9YPLiR7YGd5ialToZOInAIK0EfDSXue0
w0/Oyex4HH6yxirss8XhKM9pVBQykTA5k3MieHs7xHuW6YKZ+gIkvkNEBlLDbv86sU+//iC0ZDR/
FWS+MzblPMLcSIHGKB33KcNFKZfDaz53mBe6IlUo1+I+BWMItUlsTOfolbkY2OTXMy0P1hKL+492
ty5+3eDdMvmhrRoq5K9g7NHbjzNZsSIsybATgQ75oX5HscxENQXBv/zXGDk0EFbQiIFBpfdNPIlN
q5zksJMaPs0Pjlos+vXD/nw+Z4m7svnmF8J+4dmQHjdSqoCNNQ1Vy2U3Mu72+nD2xoDPYlyl167u
0A/LC+J1oFTviJMYrgGTiUVoQnrX72TfrF3ffrhmO0siQEG0v7tleA5nGatLi11QJnhUxkAt5+C3
gzjY++6EXzfMm+zT5Bg9BEq6AOs4rzssauyaXHBMjXi5oeiSEu7VWzCNJv9aaxYigB6VgBdrIJjB
OIaGjTrkyJlnhfwoIIQj0k6xeic7IkR7o1AN6bcW6YL+rZcMsn3W5MJjCyxhHoiPLgogVeG0hqTB
B20djhqyVQZZ+MlqwYnI85PF6HGrOS/fpDwP3VlDxy2c+hQO4uHcWrVA3e949dfJz75GlDf+YbPt
p2PLtBC48biDZ6BVSKmvi0wBOsNItL8n7CQRYg8qNHYpQkhgGVmMB8EA0Ynt499XeA+26jHBgR1a
QFPSTyw/qEGWZxKzEWH+JAMRg+Rh/eQiRAgOlgqGTL3pXYdaqLkGSi0d3/YgHaauLsBNaUoHGtPz
73xIeefEZm2CdPDbtVSfhZVgI6IzJDD78IIL4G8D8K/OThgtV95KO6MM9fvzmwjtpq/x3car3NFR
99au6yGhVWgDDQw1+SmIOXgOuJTCQVOhQXPy+g0FGFAK8O31hkEPWHTa2easVQZ0V3Q+OXB0+le7
KGx0V5ogbNV83nHufTE0O9tSHiEvII/xxuzw46Au3HyeFIakPtz/Uau2QinZbfVMYouuQb2+CgQA
aieXMtXxNMFglRT8c4Z33Yd5bY2w3JOyEnbvbJ3vpOeRLQI1u0efm7zis0aaIebhPdizgTfjalsR
kW0yMMRkkc0VsaIbd2N7hJuMCVXaBnDO8T9FAeC/FN0QZJj7LUufAyGD6USvqT3dCAAAxJ2+Pevv
6qLfPFjX435W0oLo0XCPilN3fpvPXz7zgf4evU6LMiUs37QeHpa5JspBT+pvVnzS22e6jYydzvY5
NuDtUv/94sufFASmA3wpqlnNZBl4jVXoqABN6VUr4zSnWWquafz67GQOLu9z5n3ICKPwbj/Kre22
rGoKowxl3iqMEtIsAvyAunCF7j+uHMBqiV9++NQcyFfE4T2y5cfzqfjlUD8Zgf29tIhoJKrKfT19
62yjPLVvdVI9lUJrvdmJrxSFa0whlXWZXEd0k0r/NLUpIIU3veqvlTtZG4MfTNdRB9kTDTjdfbZC
WHQRasTdXPlrsbfiUH3dG1i3cWa3x+1pr3Qxn2i3XfFpEHwYoPv0lXjVmqZXYJCFf712t6AZGw56
LLAqdM2TOUNiLzLsC/yNXEmvlJImVBSWyhj8CRXS8X188X62YpN8ciE1lEbhW4orBenhbm/ctC9N
kBQEXdVXFYMYLIXf3fEBTPEtZgnqgIYLhRdNK8WF3fJUYD/NpH8v+8W8BSbroswNMxP53zYoFUmD
jykNvzt1H98MRVkeO3jal1QIa/174AMfPbr7RgkrW6mI5btFRXroaP3KaILaZ3qcDJiyT+Rwsq0W
64uOi9lDTHa3BG9eyEnCDW98z6q6f/7I4kcKY1vQKoXaZF5Gb5sFoz8BMTzYtYXavc8IRvKf+6eV
2MUHQwiu+qV+V52qszvapAqNCPjctfZj07NEcHfF2Y+cK0lnjq3oJ8WSPor4rPBw2Tk7bfULX2pA
cpuQfgYl8rfOs055xtutfxugBOVXycb+uR8hR8oOEn25Fsx8au97OTqDNdjMMoSKoQoOGdI8+O96
rPo9/SMT6GC6mRMvg6VI8+56ZLKl231yP4I17jZtp2dPrMStcAVW/huGI1v6HwS94QqPaP5gnAOW
9KReD6qDYeZtiOYoEBJwxFJfZ6QfjKngy6keVBL82UEZDOHrJrRglnRfW5WLG0obAmml/zwTyZQ0
LwT0KEsXkPDPkV6k42JnveTL4eVLcsreCXyjeSajt2E+t23QGewR3wKLtCWH9YT/pA3sBtHOpdmw
qezX6IyxHxbtscQE1HEE1VhYFR80Kl7LPDUpCwkLh3KqSrTy80uJWi3PRf7JHujXFb25+FNioYM4
4QsJMG1Ni4D1TED1pnj7gX4k49ssB/jI6jXtJ7XDf+mGkTAf9hBx7sIUhqNdzJpAcVlHJiBCHBt0
+Cowpt8vza/yPcklsJ7tOeV/tiLZTTtm8GqxqLZTf+x/96xszhv8tKPGQaCdUBDqmq/i+bmMJ/h2
NhMdXwx/znDE1onvgRCNNp/OhJE7ZcrHLDS0E0BXfvMIYXWJF7mh/NSebN/ZTWRsENKlW6+Zhmqf
t9RlDODIhvfvUljxcRtpwRnb05zn2tkOGz7gTpkAf2NV5ggrViQcLkg0+aPLo3IWipVl3skJlzjW
vULtfkux3eS9fbPrc9shDzuhQDrYsHb+PofQWpZ/FqBWwP5PHPYfYvw8NkwrAjo3rGwJcsuAkL0R
GzaksItEPfimzVP78oVn0klcdEEy+S8/g+6YnuqkaSL0EExbgNmpcbCDqde8u3R0ImARsRO7XLw+
OV6JPLVq+rBMksgB19vFllm0k+gaVyhieq++vrOK+3jothvLHaa/aQyTUMS1E+1cu4JOQzHu4KX2
fQbWl81pd8PiMLx6VeuJaVBoOu9SmAlRxyGhbE5nHPqkEbVt0qtpimELd2fBvLQK7lUjdFNket/l
/oQYaI6onzBZ47q4WQUlBmtexeTgLBUz4RGJryHhbKbYTkrv7u6rWm7wTqJAjQOQ5IMDXufUtf1F
o6GxTcEPL4RukWw0zuygrxwip6NYVgwSc9FWxeG2/xkH/KaNXVYDjRWvAUhqs5mn1LxE0UupVqQp
WjJaK9kHTLLGAE5VIFRF8uRCCEZzpeAgCG07TvOIobx8pc7sW4988hHxmzdoxth3GltiJmAP8VGG
fQdariPAp3snExRrD5c7inFwwFmcbRzcih4JcXuQb/1eH4ZLG9UKYHeqP1LP2nxynoTBZZz36MU4
vc11lSbVt+JsToJ2M967Lg28zbt7ubJ4IhzVXQxmWZIRTE1h0+D5gD8e72wEYJJzs6JcjTKqvcLY
pBt/cRhRbdBrHM4Ijymvv7D0FMfm+nprJjvoN9ti6zngqm9UAgrMVXGcecw3n2fDN0KuctKbcEnO
UlhKl9be3oCzD5DIh/pAibdeO/KHaKGpHR10+06ua+ri1ABoKIX5rUbz/0MFucjKSUawBKqteFhe
qZzI5K0Hj837tbXp0DxnECZ4ZFXDkm3QJ0ng3xB65OB8f3nNSY+eI1aZwtFr3yjQqNdNyUTs2Y8V
mEgF13VmMUFxDjXlXGCycyVoMnGJYk0Wjd40g33aHFuU8A6Sn2AT10ojekaCvqQNscrb7NfTJBTu
b/kKOSHJ3M+2kLiwQ6UVFpho13Cdb4NMiYQCWh+LDQbh3KZIeVd9we4EjpEkAK9Bir+XpE5yJqvG
6edRHqJIGc/myLOUeOJ6c3oxBSLUa3M/s8s/YVjsVIgTLlzZRT7HJ1VY8ARraxekHT/rHlEJMBBq
tEoPDkaaIvEHKcPOzuY8mR6zF1+QuoseKNV/u8YMjfY8ocUe4Ya3ISP1DBaGBIrr9W707CE2ouP0
jJPvpljL4nWEOX692Wq/9ZGLxNXZPJcr4xDpKI3xk3z+FsbqA88i69vbx7StvqBuQbQ4WCyJkcma
MX6/vbbMOmCgQMFeZXMCkm63el+w5u+eClLgwxTs5FJ15y6Q2MWOXjK3l9bxDs61uZGsbSumScQb
QFtgjuNWxWVVolsLXyrUrz9hA//sK2ye8a7KSXDTvQ0wKeIhDsNH+W1tR/YPWziSsHiORc5a0wdl
ViqBXOUudodg4xfihouokSoR+192Cr7lZjT6Nq4ulQi8tCcmbtT0I+C7kH83HbwDl8XU+i0XsqEY
UE8ldx+GkZ2B0NYOLLwKx72PBscwsF9pywv/OJL3r4Yj7nL3FA/ucEK/Vor9q1SX35tmXtO+8zil
JTS1RiWk238JqNgatwinbde0QIc5SwIp4TL71Ym580gNTu8PkeXW7Zq8kZcQuZoXYU1/FqYdq+Z6
FlEPKQmIrROJdWHbU3RjZfSqN4iJrArfn99PhrKblVdtfl6TKxHkb844SovVDPhn2wtiokjehugn
pKao4Z6fHzx01VXoXKr+ru8kna3O5Q+N7xp7uKOwM1TM+Dq+ZYZPliV184Idl7nTJ/HznpHk/ncp
nyT4ukW6xbkeSt0YlYH2i7A9sp6wt2BtlpnH5oBHTnJdbeMy5e3M/0gaCTDj7tOzFj3jGtFcefyd
CoLnkO4tKJA/2zO5+us7X2+tiLmDCYdR6NXC6oVfYMf6fPz7vnWx4c2dEKRaa2qVegdAYXg5X5+Q
trXq7NsVIYn1wQ3rE4U3/R7M6Cfs53Rm6dLqAM55jdzUxgpcZU/F9BruYS0kNrVQz7OteouM+zZO
aQjFUwbWb/Ob3kOF/Ujo+aR9umIBdON15ghzAG94UUxINoEDhM+FFvYbPc83eYwDU9puRhxZVVqZ
yKwiybrmI0iOgg6wwNHdZ1Qta/9/WQ0h7pNdqytXBz0779ivRGS3h5L6VCpTouHqOYChBs+bh388
+Ac2TrIZPNlYhBFxz9OzMasFmEN5ltZSUChCrpMGSgpOzLi4nESK0FUdhoTyJjWufQFK4dB8ILNJ
nC1tO5UTVNjJiRul1LyB19FLj1NGjc7TNF6d5HsRQPSMA5Mwnp8JP4UDM7Kmuk+uxj3cJk180e3d
rxhZBTJOiGnm81tBGIoybCUn5obfZKCXh/ZWDd9qibHj/4FrDUQceUkMmpHVVDMs7vMe5ZeYgxpc
wDveBUc/JSKxN4hvlBC8HntvFHXNFwo7AxFrol5z6JVMFuBnYrHTYZsKOEDe1AI2AgNPlR2P+aWI
rrBete2CxpLeJUp4ifUqbW0Xe/K7yaRETsOznW9gnKs+sZ8luKgIDo8l3ito1m9r1fA+kjyBODP8
YLsZHabofsB8xbjQwo6mG+ALQX/T7SZGiQSW1TP+0lVUuJQhnlMRBeZPYwl5G6qZfQNizZiJ5r1Z
AmPVznA0HCQDhsMgl9bngCoeg0m7HZUi5hhlrQ+qKruct5KR2u3WxDG30xJ+uuSRxjMX6tMVz91t
giCg+yVEP/Rd7FoTrGl3HhjetyUgZFa7wl9EaXK8HuBCR3pb6GSrcM2HlkXNht+SdsU6re4dhvDR
/LhyXC266WBCC/gb9JKJcmGVIdtpaBrTaZXHDn7q3bGoTfbA9I9vQ3csDpZe+F/VyVAihxlSNFZO
T7TtC5ZRjgIfbhOloVhUmBN6IMBwchDlK3Vs3EM/2MzPK0Zw1GlLW0/GG8ajc69uYQAd57kV6Vcs
YmVJEeLA9o+KH0SmPjeIBNrenNIaMUQF13f99GxqSuHK0NTbltELmDLVBN5Gjf3mkDCOH9M3ekEy
Hk4/E3EfQS+B7RV5s9rGr1APA8zwl2/dQ4NWgqazxgWxgp9eIRIgNVb296vwzbJOmdM0DlTh60so
trYx+qNSqy/pao5NksBG8m8pdQbnh3iJTCSE1xio1f5Fv0uqzKX8Z1yPhDD6VQmPavoFvSA6NDqL
G+fmHgZZrD3T+SEqqhE+kGLBku8GY33ClIEJ1oOvkFCRghpeZwz9vlxpJWeV9Ev857T8IfnYZtT+
bMoEE/6uMghE1k8YfLFQnG3odQNspTcp3zMWsunxWjVhcO+XwXvx7pGkKgXgmGfD2zbBAOAsOeFG
9pTPsQyeLSbMOrKyRoiO1tWm0H/Mj8nLTjuo5UVZ7gJj9IqkdRJelLQXm5Gk8/ejJNszQYX+BcXO
WhhSYBqfcyvAbwqcynhH5K6XySR4HAK32lE7XkBtfr0tgWLvh4H5u940aE3Da8kC6l75hCPHGEAe
oWNXp0JYMPQwyZHESWbnghJKaIZ9GcYz9Xf2/fxPRXoh5gmn8z1G0FlSW38cxCm9/Vc1g0wElWdT
yqc2gTokzg6P42xjn/ZNr+1qPNCmH7WjnW0xWB55mM0ArGp7HCQX404qSQWbj7oPTaijJI3vJ1xN
41/sYSfP5zcqDaHff6FTf5yBLj+sxZWGn0FaSDim22IsGi8GrOZFiqPYNLsoW8/Nglet8mKWgOJd
3bxnUBbkw8c5t4oEyMHq/l5R1xdWyXinJzboOCSRjRqXJ3Y3c2nzQe7mcU3x0nSIoBmeMc1uYKCr
nMZokC73zg95LlLQxuSt/obpcX1jfw8fPqZrrD79SSrwx0z0HYsvQHKReJ0p9d8AVWpdcV8MN80V
7nFpM14u5Cx2x7UGwBRz0NmHSX68n6hkmyqN3o1tKhizlZCLw82vV/o+KEZcby2H3hc+cXLYisr3
j9TqowbGMp4XCqyiokBPnqfoOErBK7jfwJPOHr+71XuHJk0zL3feayNatOFuNQQlGimRlhtZAtaD
rqbIRpB8yE/JjkrI6iiwUuvWN1AZOLNpZjC4lV6F9WSMPGiyMZzhG2aMBPbRWosBOF40Um9SZCKa
Izs8QgNQ7GjkF8ipDBk/+jH3XM4h8G69H9+ZCvbuGGdMvfLaFsCN6n6brorIShrzGphksVeZFhZC
pLeOduAlTHPBpngn4Bhoofho3Z9cgz9rRw7P6dU1NUbbGpDy1lIjtsHbGNF7tcA2ktzDcsUDPxHy
w/UvU70XnLNvXyoWHy7ooXxhq89sGUONC23peAyoBWe/HVDQFjUoZbwaNUxu4LO4KdXrwCfSyWen
uvUeRIO4HUgtbM9xHY2rAPVeUp6VF6/jnKjQGPMIOFrQ/PASD9YuiYDpdx4zQAbUuEuXYRXASMe6
vJ1HwtTKlCBsmJY1FU1wKRoRopmJTYFCSXyBeYmfQQRgVu1LT4d9nvRlUkqpgGInpLu3x2OcQRfT
YuOKogMRb1xy+XTuSGWBKxk5DbRhfIUWUMnOHPYnImELmgf8s9XlDJldi6iQGoYhcOHWCyacrdZz
2XhQrhZSujwLmvO4YBmNhhPGlYHfS1X4yB7BNaos7JhEg7WvziftuZsTCzC69DAYmGohQgQsyki6
VhCYtdCndLvNrkT3hoLxrW4dqrAZLex4QBZziPn0sVw0p3yCmOt/pcy6LgPwmQ/qByLxfBJwxqZU
GG/rVfy34cIXniUc8b02xVIVXLJCxIdsAf8JJ5I7krHZDCJJcmuWDTZ10ZXsmC7H8gA4WngvR8uF
IVGTFjuLA0uhFzkUfgZMALMIMyeeNdEmIfqMMKZXo3d+HH4z0+Y6I1iEpNT79tUO9CEwQLQ05INA
YRQ5cd1j5deV6Q39mPG/cT7FfMOUiLd+X+s4AIFdZhffx4yT2R7OZj3/cN+9AXaixeS0bQbMcvsB
CShbXsGQC7g45maJ5JTLKV16y2F73EXkotnr+9cvPoXxCtD3VzM3Qt0eg5Gg/0latwUHa4316sMn
ZBdfZmQ9eumUfLt+rfu2wwnHswplGEYnWShXZFj+YaPL8kC6oOlWWjenxKlfsgE/GJJ8I4PVKwvs
H/YsNAiip0SsuOGyHOidhnEqjnKsPvaLQ72UYoXMatdad459PcgAcY/3ePQ8EbDGc0Qm2Kk/2yQX
5AxZKAhaUNhUVY2nApDfGOKbTv5TOp51XOLjKvyTITlCRjM5kje2+8T2YBhBq15O+q2pk/7ZRS5E
rHySgT/glNvhhbZ4zZ9oCW1LJqgjzJAtLLc1V9S1Y5ARrEJjP99LwvgicOVJoLUPYg+j1AQ0cEeB
8rg0mcUruKpOJVeSB6NLmvLC8r9NnMaPCWNVJ7fmr2681fy3hcSG2FyNQHJzvUZIAJXK6pAHT/9T
PAtxBv88q+1a8pGTD3CUEAX75psqBTVdknxboE/UGsNG6vLxmxVw/OJ/XMQfOSeklfo08QUCrzD4
1j54ZyAFSlOpY4JnqgLDSMgGa+4Z20G4JJPB3v50WZFLQe+p0M+eORI9SIv/uDzbBoiQBPFoRRDf
qgko421n1J2Xy6Tht70cJVkwVfCA8W8M2trU7mMJNg5e1NGL7Hgh8xjvm74FZ3/P1aEKMLHoWZUJ
Qynv4DpAfw/gfDaIW35Njx0hVYwK67/W+U21cT8JKVrtjXS7OnMozhlz7xu1W5IlvEW1PWbwPEp4
XqzMqAGHiCe0guXUxyYvve4NCE7Mwc0pQrYUPbFH5acA2/nHTdyDj8VkykUzwggqVO+z1QlVcFg5
wzQbRarnUh/3c+7GiAdD8PKyJQRdFVOFXTCtPMIoeU+HyTl7DBT+l0Xw8m/kn7xPwBjYbXPbTxNb
poivQOwKp2Gw+NLfNXP4wSofp66YSSeHBvHTM53/tOHQbaNoUmHMQMPjFaVmkZti5zx3kvLK7b/K
M9NGQV5SK6e5ojwZxcTFiDi/w0nVGqUWFBPkItyQO1idDmrqBDwrsoe0bdqQfkZQ7naGG0YilwmM
LSPsV254aUyiWWjZ6f86YO8ZGOEeg98ZdWvNksQp4V96ifYLRUI+miho1lDEd/QXAKQWuUyoLGz8
YtrKqiFPruwB5KlK3By5csZzYDvrZ6qkq4WlZ1X0CaIM/zF1qPOXLfhykmttyai+ukddlTGBLQ22
LGyFP5nRVWsGtazZmg0V2rMslXjFUOkdhi/8XR9BuC51gBQpc96a98EhPM9yvBFzZIH6/mLtoWwc
J00claM9Zo0HYJw9X11kRSXYlUeUsnwiB2t5fB2jVvhrUXU9EaF/BYHRSLDNIZ7CrGqqJLSntJhv
94RDpHbgH7gtYmxlLTHs4vv1qU9qDiW9yXyCicg/M44Ya68F5U8DAJVrzEo+aKxl0AADweY0qrCg
NEhs6wLudtwrYN1Sf4csMyQH5a3WKqLNKiUCHZgx84y+aiMFEL/ZioxWQLfikUL8yNy92wqpO3an
EiCULXpcw6Tx6p5SpvYprbBSPOq6k83Db/Vh9G5fHX7ehYHAIG7p2a+qZGFftlwnjXrvzcxPssyp
oX/P/76+VP5RwZAR2d+TjwvUPcAQwK8lcfenSKZQDujWEMaRSq77yXOJ+0hIr7cZOCQWC2GeiK8v
Nv4hIuPNBGU/6k//VBMBfb2rc8ZKQvRaAh2sfa/mUcYNHtFeUFkn+aUu7psAvmGvk9NhOkQAEJXh
S3EtMGjt9fJpewdlFurGUY2hvHtF626Ibx67QQex/KkTwqnF+kEMnfTh/6xbksfawQ/23NXwpb9n
A1ZEXCtWyPOsCRebpZeIhPiPuVVCGK1rpCKq7KxxAqhhFUrX833Y9Gc4NdBD4PUGUvgi5MSK/gNN
bPC1JH1+UNKDJQVWKd8uf/Ny1ZhMZ94CwqrOM3bfuxdFjEOUlwXCCsrgUn99Ud+TgW5Wq/Ga31Ao
oRF7+7mQAg/aTWQuhJYemK9ZmHT1vSxhYL95tSCgzdU3rMRikZ2CVT523hf+VnMMjCsWHBaojXtp
wL3zQEqLZFwot3PORmH1fer7ujWMvYjInDuOW89+p8MQsilY7YeT6GWZGCk6SFi3O7KZ3rtQ3tBL
frmR7mkYOL8ZatJyRSGF6OXoOAkRHb05BRazOtau+vRk9ZpbrGeIhVCZdzGcyvciOtBHSSfsMQZt
8tbvrjyEtAFVxhS0x390v+Ad6rfyjSmuodMVJVoK6NeDe6c6G1IJjvk23zq7jhHuzgC9Y/AnqZey
NBcFW19TbS9IJ+Khgn1mVjSUfV/8WWuX72b0EBeWSgNmaC2BDV2M3ohcHVAqmuWb2x/8IthUDGEf
p1gKfpNr5ewAVatACzJv0zBAthJyYYC0hjTAxUnaToYdfJ0agmKlfxYk/IeSU9H9Q9KazUEjPVJ+
jmhOvbVMJi5A8Q1gXh/uni8DLazEdxmM958vJT8/0LO3KpeDxbCTrXHPvMkm17RCNeXISw44T6Ky
qoueKvtaF7JUHUisp/0QSod8CnYfSWADKJyC7dDz7L1KVclS8Jb6DNVuO+8jAqfAvfjSdmG+EwM/
+5rZARWQJl83/f4vcPM0KryYvZeh/xH/K4PiOzAs7nK0gF159KQLC1RSe8UN/3Aug929jJjPg5CL
CAVRtoWCVJv0yERgri1tctfulJA3lWPEsqo0no/nIMt5VikNby78oMxAp+WLs8nEoKc8sTpv/Cq7
/Cte99rpICFX/ixa91wqPqu2d1op8IWsbOOe1TlEayLmy1VKILQ3IvmkmsjNei2aaezBpLKHJaY/
gHXLuQULJyNTAHO8dXdDhq0mSPCLg0puWG/XK7L4P1l457FKtmMUCMNt7uupkd41kemBDGpK8AHu
63plkCkU2rwiZ4OHPVyOKkfw11iBZAD1mBtbyWnhsOaMrFFmejSYK2hOM05LztSuDIVv5WoD5jGK
6PSFNxzeXlxynNk8cg2ZBLEjmK2pR4tJB4Vu3BeYt4UoOzdyHdNd5iOWHZEz1FPI6RJHGF+C6PjL
Bp1G914KhBzhKQxBRutqDuz8fOEviGXOwV9NcAvJC2IFybEr7SY0D/qaCOEmp4CrW1l3dwmbg/Bl
MWCyrupQYqQmHFJdeeZry0kyRswFVX8SoNbeaYnyn1ZMQ675oZDB67JVRySUMylSq5VCsTX07giW
Q8zH/0sJIY6cqZNqHDuBsQkMEtH5r+7C/VVbH098ldI+0jjQs/L4ijl9mgMWJSDf0k4Y/QbyfO2T
xkGFSOA2643nBy0XRw8mb63tqP4IZnis6C4yyoDYbOiGtZwOFp42ITxsURvQgxPSuuGTV2SCgofQ
ozqCdPdY/4GB+HVjVyQ2IpSTQgYICO5AHcBe6wuYfUXYUtbcoRl4DqL6Evw+LTotBWfisAVL7vqd
/b/6+WFYiSuhlFmMPZqH0cehXrIMRnxseMbFNEW6U2HrVobxn/KPZDNuHaxX5NWhkY6Uc10KDmhT
jTfLtAScrCjgYPoUSNzA7bFHXGZ61nazzOKZgRmWCLwO5Z7uoDKjS88LWtjeRSEPcFYwYJPWY7Um
zFgKYfm+oKSdg3ClQSNgTIWCR03OegSqlYe5ebSYHVH5v4LQP9tO4xia814kNkDHDthTGDZzYnRh
H0LT/fyyxDEoJQVJankgPgU2J6Xasyr5bCpl3L88Aa+6VM51XmkCo/rAX1BZH6Mlo11IY7tCw4CO
VUo93pfyT4+F3xgBc/wz7oc2UviDV4n0Yk8cn5oLMyUuqxZ9rQF5OayyJ43BkY+D2N/WJw947Tm7
2gauKw6Xz2JTwCNxSQgnMtRTPcW4/IUXB+50A6qGzoG4qr1F4IuBRyRtRtp83+BAFtCk+NeqG1Jm
/386EgCmVM/ZS9upaIwc0nlZef9WnP0BIxLEdzSdiO4qQX0P6XYx4xcZW1+TV8TqFWWIT6UZIkOg
UucWc8ASoDSZcx4kzlSeS+sCevXcCPz0rYPxjlvox5IBlJMK/WHkPKTm+X6thSrDWfn6Ervujh2U
GlgjaWLRDYxH4iKFsYtWNpv9QhLQ7e5tC97p25RzgkbvBAAABurC5ioWSYk9WMwCrlwcj/ilkBVZ
qyLLXGLAO80DG+7sG2JnGZn48S8aUmaLr2WFA3D517+giL7ukVXlnZVy777oig2PGEKalJgK3RaA
DOIhjciplKu6vylwz4quMsAjBeKsqATsE/+vNfxXTd4vhUUzm0wqLvdKpxhN8ZsFcQx7zV3gYM7c
a4U0Qqqno7d1VxCOt9fv9eKMkWVYUuxN2OKoPDf/Euq9zAryCndZ1j94D0K8nnNC6L1wLBC8/2/p
/TvIRe1j/3d1oxcF0orf/vi6v8eWoLcIvz+LiPY5m2iF5112WMkB4LHQ4ZRC4l1UGfk0Yfz9hG+a
WM/CxZxDMlIc9+/ImWpOI4CexkRKjYx9eU56wxyjzD3u2hXU7hmfCpOyxSWrUIleubbRjufAP7AG
IjZ2fXrXJeiFudgwLkRKXVLy7Q8Ok0pI3D/iDOyCy96YuL13+jwyfD2gbNgErMElENnoaMoE/ZPa
mXeUw3Bm9rthJpUDJDv6c0AcaE7tvpMgeXd0S8LdHI+EJnf+6I4Gyo7APk7v7Dxr12Pm0zdVmCph
EedzK0BRWRnQclymJVwHNKrdQAzP83D4O33gvnQLFkkYSZIajHfB6DGno3+OjZNrMzqWDUJsGbmX
ZoHJd2illYxCJldZ3SQeOxcA1BkQ6ewsVwvuM5eYyGVVUFAjTUBIiPYs1VmEq9qGtXfKz9TV9nVe
T6vW13zcW9GkUlyWiPz/JFyRWczfinoZ+z7QpNGV2zYjTS9uCiGTKpCUOF4JGqvw9O3Wc0/IZDun
MdqBBdzajuoDFlNCf7L1mqEyFkaaHwORoxOxx9YMNgovIRHxkF4NAtqo1r2s6Sj/yeee4Qzm8MkR
KD0yzLsTxVU3e5syB5eIEkc80gzc2nFItZoqfzEpeMFGYJktFSWiZY8YetdbRZKtTRKUI+pYaawQ
qHD1D+PJr2S09S8KI0cLvffrrXA9+J8hr0LE4Osrbp4xaqMCXxAKFOnECPpLOdFddVjO6CGcBNOM
XcA3zxR2qAgsPLCrhrvOth3X7Q+BxIYlee/Ttyd3Iy+Vf+fEM9Ufm9Cubpdl6TAz8srCfDCFRL4W
+knH68jsxjNXWmSyzWNfNr1nVSqf7sPXJ4N9LhMtdqR9k/yW5HzntwKafimSKcUVjrxg7MGfQi0l
ZBJoLHccUdODBYhyQQPFlamWld+GPsDJJwNfGgQ90g+ckAmIHaccu/n1eDg9j+Ld/MGLC3+6FUaO
8wB0cylLkV/zsQS6z2TdZO64IW4d2U3JLPUNNDNTyTeT6HivYN6JMapmnsi4Kh7zhhV5qz55uhmM
h5QZumyFSDSA3dob1o+L2Qo7EiB6nXkfgfqzNodb99/gtcHPsIetg/bfv3Vc0MNiepIg188ZN79U
IRYgv/BIpDnePvr+/x8j8LVtkX5sPot+uDJ3eKjzKGWwgrgZbuvszIkVIBkwmxwU9GYks5pwmPD9
waIWFLdJcfoKVAStbXRokVvYt2O7MibeUke/CRdLFuSKh1nrmuriICcXNLOxKi4U1x1W9RlYfAVq
BSxWDXRZxrY9l83UvTou3Iirt20ykokcMklVxvxqPc1giQOi8mqYZAW+6drw04BusxRJMY7DHSJD
XfOgi1UM1XENKKeDEcA43EjUaw+if93KdDAdmUjUY/NgXcCSOFMThXA2ZNUjqWNUhY757moASov/
oneIM8tuh9T7Jms/NbZEKh9OwB9BMONER6sIdNGwmdHROi7NROkGoIANrsx8wYXy1fWNqW3ZMoc6
E/mlUOn9duJCu0CpbnMZz/4pdSYfwk6CvOw5GELSB9627m610fkuytyewE4j0eGyi8o7qQG/RdVU
cVh8PW64zrIRdaFR2N+pSTXcRvla6T5zIwYdDUSYYc/eB+29V9EBDW2zsRQ0vo3StBkvKy/12+0Y
hhI8M0JeBO5K8hvefLXb98fZRL8Z5ZEwjT6sqqZaCz0JCWl6J7GxinwUVe4BFUKSxZzcPQDPYXt8
XGHDZ1eNsqVdH1N2v+CMw+Ey9JNatmT5lRXLSWp3JueJw2HqLDmj1JcMAsPs2WxB4mDqNK1Hnb6L
XtFFYD6jxT5Y9x3mSazhmaTY3Ov8FiXy4tI7cWx9EQQ6xthfVKvepArno4T3oBuSv/PGX4rICrv6
VW1NVTZekHhd+047F7kFqMx6aR/A9f90K5GdtBdJY/hoyQoTitZ3jeeSzNbam8VoSIeONXHjkmrM
lPQ+xny96JYcbspH49fhD9h9qOjMaPjudAdYY1kqSBSILRzg0bi7sV2wLFgh+TqJGKUMZzASx8GD
vpZWZ5Kyv4yn6PBufvNXKNXYYQERbIXi32xNtG/Iwurbx4rSSJK+9ChIkTqmOb9Zi/N0CT7jy5+Z
BFK0F9ONnzjcsl4xcUac02kRfwsQp9dbJEVAQzmcUeG2L/MAeNCwtAfvVbl30rCH7q+exn9RIMBw
mPpWcRCoAwy9rtWNpnP4wgVhfUh0ZhzUoQZhtkmNR0AcKtT6E+ds/s9oDAiL6z6AXs+JmuRnXr5a
2aFyYDqKm4Z5s/3ed/paG4fnSlmYAwYGziX93DkQgsDEF1u3FCe4PoiVUiL/MW1P2AwRBtYdmx8y
DfIJYFdsurp2S6uB5UnX2W+1WPZEENjSHuY685w08loOqLQiOncSJcOMV306EOt/jSvFOD4I94CO
B9O7EoBVFQ2+NG3lkiaipSjBMlYe/gZp1fCm8mBKvGfM4UEH7gWh4Hu2m56fdcpdXYSzpiihPQVq
Cab+KFfSrdYh0WegtSXqw9++0nwdUoJ2iTUzJmD3D9eNETNHNTFAGOowBtnr+fOcXWzHCg45pFRr
UBwJD+Chw/rkYikR+zYCVQAHF+0qeGD3DkuL5TqWeC8jKlkz9YgB/lBpO958hXZEzVfbevYoHw+D
UkkMTbeL4zGAC6Qvdc67JfduhW+d2av4V8Fv/hoBBi9PDPKZwPE9dJqNvZ9XqbleHaiztgXxg9FO
RG7vRc3x8g0CrTo+cAWoaDA73aYkzuV1y7mY7oQb066NMS0jqrqwo4tvxWqdaGTaGGm67bJICiwr
S59pGepX6CEL88GAZYIPAcStccHIgAIvpRD+zHSgkCWCQBfwJ8yXG2pg90Y54VA+0iWewZVKNDu3
LPU+1O8ji4KbKqEfC6eSWXrm7qpN3bMh8QsTWJ9lKKCRP+K//+XeuMs3u1dcX4AGbdeQsHBxAtSu
K17rHw5lUfYpuaXT9+Z60okQagBeZv8wD7bABtdS1rAwF1Uc5Ox5Fljb1fExPN9R8fm63VrT+qOW
eR1GXlNuxHpWknvbkQZH6Fj4HrAEisQL7Wik1UkaSYFd+gV2uLGWd55bjTrLcLwDEoiLLjxk/x5A
/XvG0f+WeXmvETb8aP3ujmNov4wwmR302yc9NrHhYsBOfvQ2UBdnVVFPpckqb9gXl8SZHHBlYi1K
zMQAhpAqGJQYdylMHx0N+jIdH36vlBS8xueZkztQV8W6TqXO+5u9NYSjil0FPuniKYczw8+3/NQF
Ciu3PmjVPKP66L6xWsCZJ9wROl9R5ef+ssdQ9MedXFGoRcFe2RWX/vdbT3tOrVBzYLTADsLAy0g/
rbQI93/RbtyM5bcCQjqAz674r2OcxmfsSNvAI1XXaJUc8oQe8es/F18NOEJnsIKqR8e/13PsdS6e
edQaV2OP1WMjchEaZEuzU5n3qsVpv7v1wTk2DX+swdp6q6aqOmRX8HD0OrwzNhe9W++m0UCvRYh7
+dPdCPoLzKCrQ4EjTD2BLHZK2i7VgWiYgeZsqxDmItW7eB1ya+iG6tjHruY7fAdy16AlB8yAH+47
5xfgyfJ55O6QOlxlFwUvl30C4pChbfRwGHrhTuRQOCi4DtpVfJItsTM3zHFNOB8ty5JFjdr0P3Jf
8t4/rM9aeHxDnYcZE+CJhoOKnXVS//OlmGXv/w/T1E58MnPku4pUvTIxYFLciMajUAvhLvqSTsH7
lNlGdwmMwR/VUrqAE5NNwfsORXpVZhnwZgpuPNBhwC15ZomD/2KwZdsa3kSNQdFXh5fgonEHhaOb
tHdtfufdTCCqRmtNR2Czd4uaNJAl1pDDjHrtV5lEAhngimZmjXQvyY0GnKGcVeQnhDWos4obZ06J
n5kTjnvzxBrY4l0KbVyUpuwewbOZrYYl2mbrWA8EGvTYLfHxJaAMSkRRpf2i8ZgmW1eI1JS1wS/V
KoXCr1CmI+JvNhw260muusSEAczNSNT+pRfma1gnFLjM+AN3KMf7DnEjc5a7ppmEHLGeUTVMptd5
TwR7Zb2qEZwHU2Whtopeyo1/DROrxNwe3cGWePc23m+DtxABSRKP1gmM62zmBHdC/n3TR/E6obhN
Elkn5WMII9T5E4znAB5oL+Sa1I2k/m+dYE7Q23zKuAEbtg1eVUS8ckdBq1DX2iWOAxfGjH4JAfXB
vIQ/+SQgIeDgVb9DJTDlJqFVTvGGyK9dpOzzr//XjWpJlIJMKlGTnkqiLkqoUSkAxL5jFlaDJDra
YMwEt6h1C2CkVA3LZzR39lmDOb+a6f7ffLZKp8XCv4JyT/YnKoYbv1+9jbEuKUZQeQab7Rrvd88r
XxSX4gy5f4pKxXsggJh/3sI6Llly0ng5oNGnJUyTSsxTMWd2K7kfasW076JupFFm1xRZxxCe6vVT
EoHZx7GYiHkCN9cvminjKjhHigjYbEjgusUn3N2RDyycdvWf4wr5Rw7WRJe1D0BTIaVPnNo6dB3r
9ulW5CIV4Jg64XO02Qh9MutwTFzaq/rAWMk1wqBqihZaXHpO3sfyMISUZ51UAhlBKwFgkgizsPXN
qSygS/Dg7egK1vBGJaJYmUVHGaky4Is//241cOPxIvNhjyAA2iXsoDZoAtnOiZ05uVr6oiuIZldq
uXHn+SqsD55WLEfS49BLJF2Xz30SpOHdHrmlT+PkOBRGZUGST9FysuKelTRIJ2F17b1T9Ux1f3gd
MepnjU07f6lO6eJ+KjkgWPJpxMqK4ZL00/Vjgphu5/HO2b0yDHOxuKL46yJiSgMQovIAzORWHnK/
RvL75tKQRdNEF1tVsuXAE8m9GRyj5yHawqRlSr5RWYgQmDumx3OzDa9MUQoWu5l3la4m2C9f0LKD
iPhd7IM4aROJzAF4kg3/B/qOlwl5K4XLdEkVIxwQylXvdbQeQgk9hr/7mhhPL94ZmCR6CVENixgN
WVknSaGeuH88m1hct8c/snyleflu6LP3gnbd5RX/BoSgN9XD3jAgado6BLlVFmCtrtGNDora1DZF
uJtU6rqIY+AwgWDa9hKBxhRn1i/kKfxqSR0k4qeOGK5guFlEwG8LDO7i7WLufVtWVH2nwg4RniHG
0Nfc7ev5uCarB7uDQFNcQFu+f3vZ+M8PLibMR9t6i6GsfK/NU7kQ/HYKphMe9i+u+GQkyHUtZEe5
MKaQCeNLBm4t8taoj3c2e/QNYJwcbh+5q85YUKZV9sKfsfxnbxhnXqhZb/oK54DVPc+VNlBni3zN
gD/9+X2J72nJrGovU6h6z1ELbQgmwBBwBHJfT19T5pkGB4++CAhsShCxouRe9PaULqpmBBQEKmUB
gNTYM9/EvkAej4QYLVIT5rmBS/Kf/dt1PrPLFXmkklcQpIGKh/uA9cGw/HIDdHBWhSF7zjVv/vGF
/yoccykxvAbPKsk3rL6BWCiktGI6EkLIDD7NCr7zXioNbsqxGuJ+3P22VOhCeEaicy4YB6nhrK43
1Q/luTAvPvOzssHvlWE5dzx6hRiytc2yYAmioQbasXFyMDF86EdLgXS+QgjN+rUIIw5J2aJ0k80M
pQJ5g8bUOCJppIxrD/x23y+iKdAXtf/CMa/1DVVXO+0wMj9NmFnG8UKnYjmt0gpSjJHczKN5IB82
+fHclrhLvGjsq0o/KeeSEgMlJMgjyVUL4R++KBspU9g5JkXd7hwFCSRpHMnU8H55whSMyhgfK/oC
DryupFaiGDiMCAjhXoA22uZOTWeJt1T6vOu0KFd217uIm+NL2GKo5dlnWOx/4o+qF1vBV6iMWNZq
fjFR4SWwdkxR0W8Hf3a08NbvM4g9nnJE/YLl9IKmHu4jbo4snA4S/AtYRYYiO5mgUxUzrsq/Zj6q
4P66+rA2nleG2uTO8gIJyleRP/D7g/GZGbdUM3I08y1zXYJAMXNlLUn1gfwrIfVB1WMgYwAh9Uj+
LZE9yfnZLwRYn5caEk1BhKFiQtZoszpeZSdE/jX5MvV+euKU33vW1NK1ifsDujRqB1S2TOo9UQHA
/fyzAmjpwz7HoHuuYACTWGE/s7/aElse5VfHZaJimKBuV7+jH5cN5GLDykIux8ZQtifnSqg6nqSn
hkctp5JlA9QNFn4RnKfx0zTuvc+3fBY8gvvXXIF4Hn60+JlMyOEJTlHbAW/C5KjdWF1RBihItw1E
dtiuQJzzg+CoGwqN4VN5mKHDpx9WCDWG/RcN7/Tb0Lq1UHJqeD2mD0x706epQq1GCwY4thTn7FDB
nREuveZEmXYSUEb9mWQtVtFUsyzjCRoo9yc6f+gzbumEJRxuK8hExmt1B8K/9ZOD52rsZLDmSk5V
EumxNT4Z2e9xTMZS3A7FgwFW9Biv+O+TrCZobYPVc5fsAD9lsVIwb+wLVC4qHtaHbMScoHtIqPIU
nsSkGtJz5veq+xGnQjmxky42vJPIQSzeExfzVi5KBYd3kgr2Ykxa6J04btUs/SMg3l72ijiBGd99
GK9K2VYw4yEtypyOdyWOnPHPwDgPtPdRUG69zU3vgEBGujL60JsRRU8alvIXi4gU4JNT2Gf5WgV2
Jp0XBMQCJwq9kcVzAlsaxjV/PRS9Akz4dMixrPAIRWw7a53ayL4puucIG7fF2IDyXEYg6A7ZUMeL
WMA9VDFbeEyM/aj2VCySJXqqc1ckChBPur0Crbus6LwL+31jsFfy0GUjMTzATwKi/Rfm8qldQCjA
WPjCqGHAXk3b5c6ByGbBuoOTF8zHy/TkzbFnL6rIiVNGkfjfjGnC21yOlIZIwWochvgPeg/72CMK
M8LTDSh0l/CG8Swc2g26HkYJbAMRcYr6ZbDF/ycXnJrwGUYN9zNOp/p0bVMOrRiYLtqZf98rQ+bT
8l2+LVQhWaOOcjSD8FQMuwVmkb8Op7LPe4FQR6Tt72ZFmEf/rEfT02AFgcWZ018jbZeu6Ed/8UVG
iZC6YRnFYFYSvOGzImu0WbZIoAgM9fQv5kfftSwIk7Jw3Nruz+qD+o1p8ViTTnzVtldEBm9SOipg
PwWkORPXbHvMz0Kp4d+ZZadeaYH+bT0CXfZhwCR888B4N2eB/BTaBp7vZ5FFP64qEUPCwzRhwUix
NpzQxwfyPVQK1RxgjIdViSSsdtQzfOESvVDJqRkTh1X2UnOuG2NGowBsg4UYUYQzoDMlazlbKpKg
cp/BachUPNQFh4Vye5DeEOhoXyyCsWzwhib7Xmqc/KK6PYjlXz26i0ZGPukvvMmJ6vp3fgMXzIff
KEMv4karg4abglP8rXmbd8GDcChi9eBQtvL3YgxtlaAQi3rK5Rds2ha/fI2ShMv4UBzf3/oRdXhX
QOx3OwDXGBHtZAeLFIrxxipD3+gC9WcDclTtlDeCFJWUe+HYiR2gbMISv2eXzyW5S3IfB7JRAFq/
OABNzZ85w3y3ue5UvI0wq1GbvFB6+5HVbFNNxUOXI/QjSQqJ4JxU8C28bwJZvik87EYaG7qfna4M
BMJHzQ7uob4JGuwLbbrqxSrrTAh+L3SQdFV6MfiOrt0edmfbHdmksZUdQTnYIJt2gExKNEjpnji0
3n2T+oIqKRz9urmY/svrVgM+TB8amP6g1OXueHQ0e+1qlFgijI+c5QgsmlO7RYpnA84q1MWAz9K8
BT9uG1qgyyk+WIkVzVJLJOvb8xgJhYXH1B0PoOPP4JEIp8tCQ49SDKrtRtR0sAanG5eDoYGoUYhN
fL+YFheeY/0PxaRrYP263FhMMWIF7yNpMvQ5v7GjxK8FDHV6YLqSfnRNpIRroX0SUGiU9NybXH/O
Xa7ScdR1fNygVX2vsc4tzkGW9pcdW+prNBgW/01PJb/NJpvkJXGGCLPn5rU/qF5LjoHFF7vuSlzg
2z8Vyw3H75QvTOqX2yvaQ7n+oTJCxaTL00ENq4CbdVg0U5WC/9Km10tEV6eP1oLEnGTxioTLYd91
UUFwOijbfF2WFsKQXZA4gHMsV3m6EQ9kcSsGUcrFvZCBvBmO21XVbacW2gJHtZAATuwHzzN2dulc
jN5hVn+exsQBvS0eFavBuBlLJWY6gx8Fm9twwGwR9shnGLbaceGlvmv+Zd7p4Fp9eg/KDUoZXrCv
q2B6fF+HX1TGdeQN/H5anPqxnH06mOi3XCOhcZoeYxfZWekl/jMtBl36tttVCnonw8UbQ6L1wxAr
b895Rjl19r/Fp6FoniaDp+u68vQVEh6+Eh6wYywPNnahvnurb031GQKQSnOuteDW3Ky/l9+DMJ/C
C1NHq+DGaM2SZsHfrT2PVsMz4VJvUMwUS5QLB75h4SyEZNMk7S1v8lVs09fV779YS3PQqRUHQPBu
5OCPNkIIA8D4ea0Zdl6q9dDNNCE+Fnh3srU7M7LQ9SlkybOS8YJ4ORqA/Z/wB5CvLI78F6v+6mH2
roCbhwqmzGHCD+NIHwVetpHWqiwTESVboqQJFOv8SbYfaX5o+Ucka+HLbfETS29eOFUUlv4THNIp
NHGgfWdHVWmEg2Gf/nWaKS2L9w7JOV3wLqLsTiJMPMJh5cRs3zq3dgT+k2Uk519gTkNn601LP7RZ
hTlWkR9jMw1Gt2oZrnabCgMRiJSjP6rPJ5s0uh30NBicIiJdF2DP9xnKykL2MJj2oUjBiZ7esR1Q
cr36764zUVXvHlEsQV+35R5SqfVREOfgc7ju+fnYEVjOzyzujbmwT9PQtB38/VB3pRwBOpcX8ivK
N46BxlOXmOu+IMM/tuQ4FJrk42HRm8m964YuDGO/4vYMwa7cBiCaicZi754YHcaDTIfHI91lRqHB
ziWzMzY4CWSSLc3arvlltZlm4saaroJP4TklZD46ZlOSXdFDj3942e7vTPiKEaCuCO0bw4pQdWTn
QMM59/s5c/90U2lEUoVFszuy5OAT/mCzBFgDt3avjuIfWcClN7Ad6N0VC+uRIqcIGJTlwrfrvXiV
AAahvz7m5lSA2hjxiH6TNGEQipwqvKvS6IA21NSnw76SPC4i+WCyhxIYsVKGKFDEhuNS+InwfSMQ
gmYEB/W32Rx6z9TZCrl7X4/2aDPbRNnXj9ZlDYySt9+L7zIC0sYfSfN8z7iH8O2iDksovg9944c/
2fvWXuaeZWVvodj7KFC5+LHHgmhzodhJeGnytQq3cxKJBLmrb1QjOB9f1JPtDpCcWxDdnBwogowR
eIcSvlu/KrdkQlIRJWAxlWs3oucCAJ8+oKnCbeSQ5o6Cwa5x4BfiJhNgn4sSsuT+RPjHvkkUpDwb
3dzhbCXWVjenv0YTX7z3p8+FzQyX3C/fYksABwGpeERcb5E8jbheDjaK1gJUDC2xM9VYJjPckHm9
eb6wPJitLRBEXj545Z4Vx9+e6YiABIXgvWYCLvQxppyP7PRBjVgCpMQK3aE2qg7Sau9ZSuLJRjCO
nZ7annjSCTL0nyPlUzEFY0v7JCCZkHKikxCO79LH+TzqAfnLnuX/fSVkZOY94X7I2/mKpWXHfB3A
jAnCPqvDZp6/uW7jtZJuMjM0VYTDaDi8wMA4GzHB/ksFP4tvquhmLJYWqWMUaI366usCK05WhQ/h
4ZrGgyXStIzxcBXR3UkiXEjG95+6BQKUkBAnUZZQmFE/UX5cIBP3xbgd/kGq32uz5B8OnrtcChzm
zPTF6/4JbmPk4HI60XTfjAuNzJoSZdFvcRFqk5LC+OvDYYxTP6WL1LhWyGjPCV5Q911aT3vQJB4E
xRp7eLLzfTNRvVRFTWNq0mVB4forW8NeG3+Y3M/L51p299K7YshBddnYlbqRZXtA6utsPkUVt85T
zBR+ow6FYBZbQpW13fPnME/CpvwiRAzqO9CzHL0swo96pwdffiOANEzDSLf5+1tj8N/Hgs/IMU9H
G0EDm9HFhp8HD1qnox1ie1MUduOKZ22n52np1PBOvfQkV+Ox+hmF7yfpSUO90U0fpgSqI+f2kd78
mmYikdBJzLVFnRbJCa/AIyE0lJLrpT2CRdgGJHePKCDLA8iiyv97fgyzSkEoQsM0gHkmHwQ4HJ2W
lCdix+dQgVQa4vHB9P6ACaz2/Wyi9xL6e39yqjQg+1xGWJwzrL8hg8q6JVs9LRSBcw6HRfDT65NQ
/Ynnpj4iosBd8QqlQPoWyzN0iE40nfLexbKm9o1Zy3Yc+8WExOhpXIPrdYlwOqB3e5V83QNWui2r
jEjwIwg9W6+2F4qIGa6CsUhRVrbGo2lrKmu1jC0pAYBBfqVvvZY5iDTcnreTLM6VFNBZBOl5bYA7
Z4NvEbjGiqMU/dLCXu8yGnNgtzt5f3K+xmJRG048t0nnzet1+202osZf3XyBCxxXUtpFHldQAjk2
mxJ/dsx5YfS/tH7ank/VxccgJmKfAmbeYno0O4JIEebdnd66zWrgOd/lKWUF4R7qvdJf0YR/PpiE
lJGLLTT0JGeWdl2tO9KgKiHxZBHFC2J5QLyPT0HFVjPvXJUbRL1C3vCBoLqwsQLAzfqaJsm5cer3
wVofTaPef4eDelQhjaALytetSgpfcDn6snGUqloz39R/ac0Sg5mVB+GdYoTgKv9KeK/nKxIydiMn
LLUCLbEIZWuWyqI37NGL8KDAoL3pUVHxk3qbfYg6mVcLPa6Zh0Gn4v3fHUbWMLwINGqfgTAjST2U
8hb9JooQEYlkm4WuoaYWX4EGTCLZDPMo207K5cokVH/ScR7mRTCFAac3Vcuc7EuEc0mKAWEtwgTr
18vCopsKy1pY0JOUMM5hTqZnhVnl/6ygw6gadvk9OVmWg0hiLO7+WCbNRAn3g8S8wcSeEwa3J0kk
mdj98aqejcT6OuLv2KnARl7pUQ4GsVggzASCeXF/BKMQdJld8GczALURBAPX6owaTYUzcXJWea1u
LTCx6U9JjceCGIbf3CqGm4jRIsLO/ekhGzOFoetXo8Q7L5HjmzbUL1+WJLJrdbx4nneAtDBjkKs+
NLSarSoEYcxKlIyfOxM9whRpojRzlldlik2CPGEW5fxlG4WFgap7mTeyP9QeRLXmTzjEGygE1Y1X
azhLsrzqP5Cq1OXRtp8edOIw/T+sVe2WkKlY6PiSc5sskJnXD0VrcYmAExZQ0NqoS4Oxh0I2awOW
vVUJVUpnpVmyD76BQ99g8rSqYQfeD6ZGzOh75F41JEFCEnIvI31IzNEWqw8+WaoupQAy8tH+buLE
R73wygX4ZB6WhXhIoMgQCBdbxVkp6QRaMVyZdhh9rmOWLEEq4O6+l4kKM4DH5n2h5cvG2GE9x8iA
1J5TElZ8UqZtY4VvljFYpHpeDGt2XdwojPAC0C8+jjo5oDGcGrygNsSYoUMIWwekFBkLZE7fd5XC
U70X89HFpTx6YSrrLAh87jCjTPkpUakP9PaQN7JGkXWv5IeLUQ8NSocVaegf+zTbTXg7vQQs3xts
OA456yCIK0QZyugWifFTjfD+wlW4dn4Nh6GZtpB6UVsqOe5uGQUHVHeKPL4g4+F7W7jrYGtRS/c+
3u+tShmxQqYiaHaAZyS6ej8y/cZxcpKx4q+zWORbZ4VYwZD/zgjslek8Qs0qfFfvIjqGu+DcUrCI
FWa5hAa/4CDIOJJHGiR3+7oE9o44HKDQWOfcdKEvgpIOSWDZOGyEeOcYVrm9iV2NITqdwaJsTSkz
ncqd9GTb8mKl7fuq6ADjFsnsf8LmQXwryIpraUZSiUurPaVuEvfRL72ikblZsm9UXTAToYBIYj/A
ZKFLwitAlWCgrfi1cpzuq4feIbGy7pQ3h0glV9GIPCMMUNNYX78x8eN+QSMgb/HLC3bJXG/pQqeZ
vnSQUD5wJ2Md+dW/459Kr6uzYxxuhrR1EGMuvspJmUrU8sTb4CFOYkQiqMva0koyyxO5QfjysQuY
bWUdw2elrhZcs8E2SFxUQ/rDMnmncHVBSG8Jvt8gxGn/n37HoJJK9RT/B6Gw7+L61SwquW6RoItd
jl7Yu+jXkf7BFlXjNzsXijf61jzkpVPam2/mLowuJbcTKPUSNR9C3F4kGR1WZkJvWbdTWHmmhTMW
yRfL6h6q96HdAOYgAYI0npWgPIdH1lOEk42linAOPiedbeWSM/A5jKraTXiqgNHDC5rP+OaMbTIE
TFGwAiBz9lgL2AY6q+cZPwwVrQJLv09/VUrl/Dyo6FnO/xYv2Jsh5v7qIo9au5eNWwkCZu9d/Ero
lBLsZxK/2IY1FHYOFkvDPhHd03kvq3hA0sDxOLg6ZJWScCR9GWa2PAk9AKXawO6Q3mfCEt/bbwmd
scwHzr6Iel28EWYrU/gnCmS6R/2Lp4wcKiVOfbOzvLSuvnGpnVpoidFU5RD5LXQfflHcmaao6Srm
1nKxj6SbrKDzyR9K5wuvJTyqmykRjFdJZFHNLMImaI0TpcZ5aWdXJFwOh5qsdgMqbY4YGKd0AR5f
oSzSTAqE3BTB2VpB2sLMheowEf4jr0mGTDpF+2C2bQy8pO7yeH+gT9yu824jffL7SxDOJOWvr5Y5
f9fRxMSATwll9hAxw/BRkj0UE6KxOQ9jgXNJ8x4ODsocvT9th1OTUiHsjQM19kYVYypFVR0i6XN+
1+RKr4UJyGQREZ/5iasLVNwCcOoinN9ns/N3ZwexlWmGH99mwyBg4u+aF2B36ajhgsyA8uWuRhHu
JDPsVL0+swfSFsWXbn7coftopOSmA9KY64YOE3Cg8jbHRUh640near7AweiliMp4pv+J1iiY+44f
IUPQDjZJO0b+3FxOma1h0gpIr42eR7Qn5ZMlGXe+oEiT2ywODNOlJu0yIV2oAyD1mX9cfvKD28hV
3H4NiOiN/RUtBhAmmJ2LXcFXrYE2mncDe7dHKhtotA2tNveAa0GKaz4+Cs83VyUNcONE//NJoIeK
AqyWmAtaYhp9/RAF+S9Jb6CW/G8slYiXHIVvNOAWb4tV2jqsyFUZFSOPKBNuqUl5H6EvPhD2QLmZ
uf8NqkNib80H91DJ5TzYSKjXduJuZlBDQD4sld+j682QPL1+1HSJtPKJgtIxBE0ufb4/c07wXkXy
InHW5VXtg3/m/dcCO/uSxMr+kUeb1QdTY3X76+yz7paIKlrBXeaJEkRuRgucbukHpfdn2q5/Sf6f
PQl0rW4+Ivfn4SGe+sBkNM2gE40WbSBI78l2CKaBQwD7xll1quzcRkBTR/t3Q7RIaTm44+Qk5ICP
FdHdTmG3X0YGvL94DFBtSx8GUcxiFZAxFwAmA08+YUFw8YEfDtWOn97ptW+y4fsf2hNw+cWBuakg
7DeyuQZclOV7NaZ9ECdqS5eaI3lSCs8XW3urULsFAl+nN0MuvvUDQawKqXt4TduvQB0VKY8F3Cll
9yUGEcnHTiNUrnHWQVL7UKciDWKKHe6UNjTmQVYkC6x+u1AWOpSebs4meLdb9+5Al0esaDEJz59Y
C+SvMOFXYg0Hj0onNL8m/ANciYT9ipyd1o+d0UHTTMfinUq3NoT+TwEG1IsBjVWqJNSmfUcQisur
YVubvZCqLuRtyxuCtBJ4SZZfGtR6VYkKgzb11LFhjZzCbcw8hSuz5jrOWsgspEn2ZUZxFyTCNone
HuIKPly/UlxaAcmEP2mdNySt+C5AJlwEYISxHTkYXUT0AOL4Huc+ud8WnSEFDZyq7A4KfPty4w/l
7rKPL0yXYbLd9O9+WMBeURWc3pLisq2EsO4i3vGZI29kFRo10gh1vp6ZkjcQ1W22fwjpbiH+kZKX
BIKiYQ1WiILTs48BhmY+6sNye8bVJZE9mOmOqndQlWs8Jbmmopc5C8YHrXigp67UEk1r/5QK9Vgv
xfSR7n1ROM/GSP9/M2zRpyAl02ahYiw7B1KOoLoBqpPrG1Dn9utUYi9OYvtITdo2ghaMpKoRc31o
b3yAdb0I2yWb6CIYW+ZeeqZ3hcR6jVUsHewLWI9oaHwUmwBZVcZJdzwKjv0il8SVXviOXkOxKFQf
PIvtm+QHTHLJENnkOCEeZB83OnJw8k3hMSefTLrZudgUcXs0N3TwKrFFDydodiTtwoghHxjJlweI
RnD1Tm6SC2igsozggGepamm/4D8cmhgDq3KYp05iZ7Qq9DI25WISuZA8qlHdwSCJojoqyIWRoLxt
MCkoWOhgo0fMI6NDpRD3KeZRn3BFJ3/a7L6kQFJVPPo6A7sbWidyWw8TFwkKhKqj6fdO8xbIKQ6G
rjoENx8qnZSlS95f9F14Q3CSQn3e8TB+5vlqwOKCEv2omH8rXxj9mXUxkau0dbLhTiuGsUnYX7dH
UO9OAnZuzGvC/CxJ92khudz5nH/7+7rdIDSHRkzIIECe619kqzMl6CeTxx2+eAAEb29Xysw3z8r5
+3XuTWSdZkeKgASBggsavcUnlQdPWxz92LognKR9QpgNXPkgI2JO9mah8UclQqskprQPBI8uueIQ
vmibJ+DGb6DaXGyyUg8nZmohFVDKRdAckhJ88BmUHGiuucr7kE2p2xoqjUT/ftuF4qPVrrptjxFK
uTF7vfLfLK//oGDeRzn4gs6sO4WI/VT43TAaXd+V4m2zhXQmSBrMTNBkxU209W83K4nvyBgmNq27
y40zJdxsgrtYe8j6zdrkkHN48vg7NafUA7pfOvF7J2xGtT9et+V0m44rxMIQpHSPTPTMELoT7R99
XrT9HVqWc0BOa/zkQC9I6bSduTTbFd58LSmpYb48v27gqakv0BwMH4TUZQvpyuTO//vEjK3nIi8h
zKTSDvckE/DgIsGMdIF+iENsDXgQc9GSc4zMr+5wB8wVjs5595g37yi092zhVipBgq1UsMLXNdZq
nyyp5uZ6htR22RN0JT1wUbp0zAOeFi0zwixnfptdfK12FP874deidzz+nkbyGGw35SAofMrK9UYM
76Ws+uV8f4mB5a4faJFwT1VAjIHBZZsDA3zV436mmKSVyf/a4mLtCHaj9FsGuplGragLJCEyG7Pt
heYL2Vr5J4Spo922S9kJPbxnJFlFDAxh4Qc3TTM/GMHCTtydZPkE77eVO1+4qBzh8C4MeVui2mFu
s+nMvUNNypDrGeetaw9SuSOtE93XoAIeGGQduQKh6cDBCdmmcTW0b7N5W9h/Kz24ILL56Kc9FnWo
qDI12rNsg1mM4z0440CTqRS59wvqVNjopFM1caYIK0X6UCCmMd84Sh+z4a82UcJ3qSG/1ABtOM5+
YF4hE4kQsUBJwvLTXHfeNVa97KprYuibTXpk6qz+a8tRTDM9RivjB5N2igFOKYZ84LWbiVqgRkdt
yroUeAL1H0pYIK8sjUjvDiCBqRWU+93gh1+O8znevm02Cb/jpHDr86rHVHAvA767eP62m+RzUima
/krdJAIzw62OltUccIp85+/VxiRI1SdXjdNhrqP3iCxP16COCflyUCqNDsc5wG2Q2jO0n0YjjOTC
xOGiVNihaXN4SuaGiiTGszuhCbH/LW9xEY/mUfAK7wXVFkaa1UccfuzfMo3Hgccc3yE/aAzL0rDf
0eXe8RfIXvF41UFUy5h5RwlLaWyMH8Nnj1ZN9DQKm6wnFjYZ4FnKYeZmM56WCtAvwcAqSacAWkKY
MD3yZyafxMpisb9o7mTDkOxbOk521s0Mi4+GV17F7tD4Tdj8Qv8fSWEQTWgqnMMlg00AMrIPD5C0
z7IfrAo3LvcBYjHGVtRzoQNw399ZkFKifIHW/NTSLUJPjczm74+Nmm2dVnLnacZiGVaBbYY5/PD9
PUHYDbG3F3yyGC8gjrB0a+/htFufLbekY46F8FqA0jfQ9ufcef6rVlnonNBpLzUI66JQXT8gZmQu
3hCRkJEsfO+0PgO1oUAEcDZjhqOlAXw/urZF6wmoJ4olGUU3ccgcT8qWa/q2sKi0Y9MyUuy2WM9E
QGtImxKkgGHmGlh/xaV4BjEm4zsXrDpvlyzQ4O/Lp/Qm07ClWuvqe62QfPifzV8SdTB0Uc1d0DKL
GujY/APujOXdxq0BeoO5nRKUigXqBZUPSTQLrJ7p8K6dMEju7xpAssj5MkegL21hE10VfTlUqbjj
f/gQoVJbu3/7CbNxjkSZwntQyYY/1FSoWLFLcxZ9LBNcB0+yACOfeHAEKjUjI3Ay0J16Ize21uol
4mcEf9tB4AfmyqRAE0orF7pu8/1mwlbVwwX2vv5MGssdkklkbtJ7RrUSvggzGEbkS9kZIPooZFq3
5UXBwHY9HPM1HWiiXpTVJsm4L6v1IGjaGfrdgjXmgGG5SbEMKfbIUHsFC81Ov+r5PGIEALpoNBF2
a+8VWOyYESSosXarXlHbhPYcFGzrmyKYCyfkaxWilAeRrmJN0AE934sqjeKR6ulXDn4lhIXaCwyE
7Tb3nMNEPhijy2nSJA25lJYOcJ/TIMK2UipqE8g9iQcAPXgvD4AZNBYwTfvHaLW7b0RTy9u5P9V1
jwfu2Ssf1HfQHUOn5HsnvO8FF26NjokY5Jvum28hTLCzBby1bTznsBpFPz7O3gbiLaa1qFIB7tUo
7mR3B1js2h8h5ABhrbpTeNd3X68c2OuXpGs1UrgikwIijQXp+BFIBqCcA0YBgJuPRO2Kh6c2eAtt
Ag14DI28fOxOEtOSJ3H88vai++mnQDUeY8Xj16Umf+/kkuMYyYTOxGoN5YYPhymU0lztJHAdXJnP
l4PQkfPW6SIpVnJHF/+hMjhiIDdhfb4QyDH1+GvgnuJrjGz7T0MUCQSmKAVa7BKalukQ0CD2IG7V
S8WSOWEDc/HsnU2dZ/hJ861bM01ZjzB9pE6FwmETsOupW5LNgJ3O+6TSppxTThVtuk/qS1/lNZL0
uwGMexMLyo3cFErmPx5gV5HWKrvvSOUTm3aHiB1STNrpLI6gpCQb63dft3xaQOEJ1hFqTAh6xyO4
6eFNC9kxsBkYJkfFa5Y/mmm9r9cV+MMTdMhw9zXEbmvn3qwxF5BELj9n82PDmBtrUXTM/YL/RY6/
oiJuaxDI9eGQ3E3KpQYwPc+nLtNMylo/HODww75Fkfjy+kOlQrDldab/JVU/EDr9XT3yV+ED4hbF
C35jOjC0rXQvUbvC/A1hbbthbKZjT2XQO3mF4upIVT4OiPSl1IkQ1m6JQyTCb4XfN0G3Cdm8NDc/
d5ZispQWx2tCrcLJb6/oA3K5IsQSD/2+OAkIpEIdZYUcDstCEIYOFcfZO6mEXrUiD0KZ+rXzHz9y
+kbcF/ArZ66sf0OZPvbc7zBlA5jJ3LAbXGDj+mYanjdIi8JWxNuU7rR09aLR7N4KwP75r91xkoy9
B320mftw0jnhk46ASZbTZIL0DXCmIaGYy2P5PL/ujP850OXajjIdBOoNWTJEAt6iy8aSgp57U7Je
Yf9wTCoOr3IUbMP7slaYz1UFuyS+qoJOy8vjCLldXzKeUjDbhI9Ut5FN+XsRT1NoY8e99/ECiYaP
aK/0cS1wIPPJfKCbEd95Om8nxpDR24Qsqb6KXExDQyztqLsNuO00m44vt+WM1L5gJkY2m3QViP9u
uvqFjUTiyqPW9Z9A4MvKAIeSw7VNB0MtYal1/mLhX0rOgQCDTQdLw/57u0ilyjaZfrwagUlxJzD7
8KLHbxKavFmjvk5Ajfg7Km3xvhySBRmoY726vRGaVV6MJl79n0SJaTbGxUCGKNfMP7EbItpr5bI9
pw/URr18J+j2DGuqPWbIQ9JptoNN4PiHqSNshEBB8Z8ei5nTiQUqHyPy2JiNYHQH6YZhMgRLvN09
Ub8EhgpZ4zotMADeTN3f2ujIiPmGpMdlrslpMAQ8p3hheqbKv7GLRXPZXQfzvixZK9O6jecdvYqZ
YxbEMsa0wHKnitSxDVE22uU11KyIJ6H4DInB4L1lZTg34FFyU99O0ipAaoQTeGIYgEMFyz1adIKW
KvgX9BxZaRVwHTK5qnde+0A6j/AS1gP0qkY/hlczuaexA/y54weSdj8+9joLv+f8B+kZMJymvEU5
VKtlCEhrPQ+itrKJEDh1SwxNGaxfSQfA/RhfkNCA4pQQj2wmHpev+yQiaaWZp3rjkFgfKi/FVYET
mSlN7X87vfLAkO3+h/9lT2Hyr6Wt79WxwU2ANlKm4v5H4aR/cyDt8emlCS1T8347rr0TX4EBVyiR
xTnHuna9oQfZA6xMzM4F8SfYMIQMYRy9RvuZqJaA4QypRj+KaNN9/xMVYO0P73d79yWdXXWGyMBy
vCj+tyl39RmXuV22gdErYH+/DGOaq8DT8M44THJwbASLgRLwH9SpJ2Q+0sN80iI2R8p8JpJzcI7h
twY1jC8R+YFM2w4eiDsdeEonWGrWGwULNeidPuo9Q4fizcNEbzD3mSsJTbjUWy71zZ7B2dsV0y5R
yx3EPxIsXXnwgEXVlQxnJIPxyzfD7wef4Mh8j90voiEmiBedNU9wLzD2BPHMIxJqx5M7hcYVs6Zx
aijn6g3QE7d8FZcUJZOhlGWOl5mKeL8uJb84RiRNFKL0OQHIddgAwLs0CxTtmidrpCj/xw528Q2t
EYUv6aa1DMXVA13eeYdOAniqXUX/qbOhyHuVSRnS0OXxoSeNUBsx80Fvg6sT1wn4rPctxdCfUIfX
MmbwaQw98HdPsvFDN6fnKZY1d5B9p0voGTX7E8VPDYoazRqhk03izjM0tWCTI6EgH1x0fZIEIYAb
ive/RBBle6aEzcSK0kzZVWD9GRWCghxjZiedM91HX2E63wM+ugH9E1eJaPGGOqzJeupqLTgcRJmK
GW4EsJO/f40RICucuI7VDBbYvJtFJmnBiEt6X6zsl22mT+gn5o5LZVeNYhKlujWDsAQmr2o02XPJ
x0z2UMlSafN9ZJ2jcve4wr+xOlynxfWS6xdoBrQXmEApq30Jgtc41O/SZ3+Mrvj/JMzb9/lt5jtB
UQxR9/Mhn4aIJwlU9T/4Tr8OuZB0i64fveZxeM9HytY1iLprLRf+n/fIOjZVPmyQzlnK9NA/OYGb
vAsmfGmzLS2GU71aVqR24KClExXZaIhnaJXb1JzwUWNDPhtLDdtq6+jFY2FKwUpxbCxHiH11aG4M
3jY+SC4doJddivJgq6IzXa5vwJBLa0foRhk7f4lnJEXgk5tKjmiN4ETNKNyJ1MwMkEj+3ZHerfro
kHpHNInWQ3Ua9/SPDZz+hLoERnd4rFrUWHtt6hzinvk/FjSPY+YXjSqB1A1djIajYem0khSG1M9R
4vDbP1zqN+ySSfJnzxvELeFD9K9Z+G5hSJUiEI+Ew6GuPGjalcMonNhr/7ZqTCFrvteCqN0P2IvS
I9Kq3fThT0GQzTWa6PP9VbXcHlpqYlmDBH5tmBuyECufo+ZACnKosqtIyYVG2OCmMT4eC1PxOhoz
wypx1EUYN9K9AX7po7+8EkXV026whuHtiaUym/juo5xX/lN0wTTepdudB6cfDsIkLdr6mp4tfySh
4Xsw//1vFhyTVZYtVcCIBbadHUZgM5ym1Lku9zyZhFiD+i328tUXCSsUDSME9ncSVOwATtO7UIbm
Iux5KBhjfZjsYAkjUMoNJIorJBJZLiPDRfmhr8NJlJA6QEq2cRjd7uRlJLZ2Nd3TNuWBlzycC4zk
V3ihbTBhgWQI/y0b1fasTgkfLUaRDmL2AtVR0PxeIDHHTs223U0y4mY08m44T/JrqhXeslMcku1J
RtjAKsc1AhvJ4DB8LPetsMX2VeIyR3j4DgaKGi3vMEx1a9ZIV7kuKtVPzm8DwpybQKxOp/i8OByK
G/yhyoeLFSYZ8b0DicW4yubloXzj4slHc1p7Si8f2D5gI83bmt4zqkMKsZ+7V/jh0oozZ0CzFy29
DaUvY84HGQYJpireirqe6iXj7WqqATTTKSJgx+e3UQJnzKmKeB3ikdhlyO7gW6Iy6P9ZOgQYJw4c
CP83qhEbqLAw7uZHVy+nbUXhpo7qK2Y/LnbcKrBQ/d0Rp6mcQQ4DhqKzRHvPr6CASqygSOHxo78m
4pKjjD5H3ph36/gLQ28M7+fL5clf2PQaBlluDhoJCpJPEtmXCyJcsfwjYj+jtNQCtOigWeLU8K4c
M3T6fMFBQbhI8MkKl3wdCQg1yBjvjoliPQORZb8bE/gwjcaN1YcXx1UhmchilbKwhhieQH0TCB7V
6fdpJ2dE3IAkqYAHPvbYiJ4OjQscfwySetW9CLZ/FwDEndr1OgghV39VnHqqAQTyPqd4wHkIlPJf
xLmgCvOpw+Xn4/keijFeIhEvYfwCEudepG02EFyo9dbakrzAyCNbWdHV/ujiQWjoByfbdhlW15bQ
+9R+ej3EA5F4s+hPZ8BKwD8uDui4xOC1aBE9Cvbfj2DByD6NrVxcf11A25ltxzhptH9unBkjq4Ey
qxk52sYSyKpzDUqhmYAaaFklLN6FThGfN7ZApUOfPgiUovCtvQ9amj78VcHVztvz22mqKm5fGlZf
5eumj0d0VI5MVzCmX4E1iDK6/qrpW9EytGmtSB6nGpYDP0gsCigaaQf3Y4NKn6mdo57iN5pPyiMJ
MD9V5hjeiSFZ/BiS8Gr/ByxKG/g2GjKfZHFHeeXlTRr5mNaOFg1EWW/jF657SEdIiuQYG571Dye6
ceKaPiJ3X1rXkAtqrZ6iP/qN7kmy/r9uA2Y5RHgRuUClzvR7dBciuNoOC3DaHamxkicK74vCiXqA
PeQOu9bZpIBR5tjolvkLlEyL7ZRvOnFCjBVOY0eYhWCHCBMCJLynPT0mFpGnTySmAfvFGsI5fHTm
5zrB0slAT9EPljouX8nIKwVfyvtQJB1gYi0PQENuQFa6VnU2OeLGnexQhWzz33zSj/QPzGVE6HtU
70jXQwYug0e/BoiLN17r/50aAl+GDSDMjr20K9DpuUw2OPgWlWTBtDas8Cth/9mfJt/qCzjAgcMG
BDCTtbXP24YTcdhZzC/En9+IXJOja0zqggvsg1G+7SOIIOYNHxCQV3F5PehX+OKc8/R0xoyixfv1
T8Abnbu4vuanYJ0QoO5Xllv7b4aBCXRvykEl/hmRS0ztNXg3NigxMqk5VrW/qsfiA3XCTxA5RYIS
WUDpHVA+o6uQLG3EL+p12RswVlmb8eojHXNll/nzIrimgJgyzpOWGBASz30mkhaIxtPfg7M5qAgO
X+C7kKlt2WKl9fntUNnXBkGtDUpOEYRxBIQxf06NnIRaF33aakWaT9deYmBXrp4UteVN6Fcktyyl
58EftCdwrVseMRvoLCNolWBT54PKWbIEW7jq7Rnxf7BxQxCW+oSluKiR9oxSBr1dsRCqsKqT22q7
hFrgHAw5eG1rb1quNnnAQ1iX9XeD/ZjMtLA1mrfk73IPlqo+XOnAZ1oVmhg+bwfD9txoX8B7Fvyd
zlhPr2GqZXPTyCwZK4MMJZxVGHW3n7VMHLQwOb+BJ2yuWJ/AvEVjQEYO5Qzh61OMcetzAe//FEzT
k2asvMh4avyl5biGCEs4GsH3U3C9YqqnxoaTE478koyv5SbiH8FwHWmfh5xPdCUGlLoN3YK3wsHP
7X+NY4MsxUFJtm6CJ+mcJbslzEPc/ohDrLSoP0/RffVYtebd3pD/kt2wl7YPHrHC86RY/0zgAFPh
nKTqLrPk5Ck8WH31OtzKsyVMJFtjRawRURgcUDtHnGmooU5CXwLRHnDFFyta7TRSrCweFMLT6HWk
SypUzVGwdaaXE+6P1Xk4U+3JAcjlbIV+CnbodWagpJmBld2N4IPDpOkFSWC52s1rfHCBn2PtMNaG
4lH/K94R7fpaGT+NTFZ2vfsNG30Lm9S65yKp+YLiH9Tu6GV8m695rgINT6O68PDvRQ909N8AqMVC
8zTnKidj23QLwGHNoY4dSvLqx3/lCsMO/MKhVi6AJRJ7Heo9AU/79FS0omluxxurRrYRnnwsXzZW
mycDUk+7suDrONidKJbp2M8l1n/M9RiNKgG0d5tLwmQnxQlvxc83bRsBZU/uuUqYa2S/hP8OlmlW
DFZQqzlOrlmXGSatpMeBZMfyOzpxMbPThKektH87PGTtxzezE2yu120OOWoBczIcpnk/yZgGM7/K
+hxNwBdCZuH8JacjdUHaI8ZsVxMCZPcJF0w+KxGdWoKJUZTu9+8akCIqG6aHUzltFUxJr85M1QaH
4p/wD7FRipykrycpWw58YxMew4PrvoDRJnZfiB6rvGskIsMEP3jiJip3U6jAZ1nETaAbR/K/9iOb
hlMza/WFPlU6MZI2JUhfooi82v8WK6je3Ql2Xj7fpJ27+9BnpUAuyfe4MDvQW66GyyI8XwSTGoh6
DaMZ5iUHHFbtlC9z+pdsvtk029Ps6FZIaGfmbwu+/zt79GWcb9OQMXpIXrgwf/9Xwu/VnlNCs3Dc
yOlGWHTuSPAhGbSd1r+w4bYEsSyfu/7lNANvbPsuh2JsGp+BkbBbfZZZb96uu4MOL12uFR8n/vKU
AIA09e2ZS4SM+4DSKGaH/Er1rBTmvwlYvkhbViboLSrrycvoKkEo4f6KMxR/lu581h4i+Xe3uVg/
wh5L7IWqrvXprNG6BXt3qLZi0bRK0pltYT7bMN75z2NzA4mjaPezM9eLvR+GefkuZX/6pB64wHCG
6pMgz6cXSZzgLzr/gpr0Vv0RwK4ciwt4UZMtMA2sBNJxwdmiS7GZirRXIwa/8WSirxcJCoa7MJOM
ov1G6W6OO6si9b8v5PDAjLM6wBfzfxJL+vps8gK6ZsXocBYF7WpgXuP2uLHTe/c+/RVrcJtd4jHb
QI62soen4EPq1QjeUpyxgEySb/0SCpaBqn+xAlyHB/eqE3amM5Lo0YXQSYz4ooKrhX8QKf8Q6koD
K+bLAVDotLfe2663kki9/+96XFotPtKDFhBSrtorg4OXGj+BwbavEO5xvWuHeRp+7jtc0U7xn0xy
l5VSDnNuL6cWBunMIn2b6YpMDW4cnxO4NqH9UiO1k9qONQ38kDQW3aXoLAt7GbY3GTSS040mPDmg
coux+N0hYHrsGFLBGeW3F1T+VJN2+mlAsX3+wHOIusJ7IyhweZVdBx7fKEIdrUv/Pd37VBgncepm
81WmxGh3mhUYtnZ+puEkfv4OlqzGS8Xa46wkHmE+qtcPvBPQdezeruIwXsXy5VYX92D5T4HFSRd6
HlsJ9IeXeJiZ4VxVaga/rA2yUL5Zr0tx/L1Nhv8sw3g5i3m7GaGddSS0r8/RrU1TH5FZi3oUNGW+
04p2Ku2rkRL9QP5S44rnFeGeDESI7RnePI+xz00KyfoPKwYoyixmmEVu1tehQsht1bJLxSFg600O
aCvOhKBqJ4XM4U4mcp918c8CWPX7ieFEmMnqobWp66YAqhe5IJ0FHuVhssw6PjEDADf9h3Kxy/pa
oHdbMU6gvdp4qIai59LlYF1o/zu8gTwDZwgeExDrlomIvKJgh46n0UnlAUhVr3kXw5OhM0e6vg3P
+RErdqACseV0Zdpi4q7FATMPs9uBjZ2TBo8xENk+8COFrL0sVIDV1QOmSeqlRV3W19uTWnpOn5W/
mYRg+16m9HfYHiLOQfVXIb4IfGj+9yynsvcahaqjrulb85oZ63FyQLYMrtMWhrZ8ai9/94v3x/XV
9aJrrOQtAdsDKp57DbB/G9eQTJVJVfyBsYv5idEMJoVkh9tBfH4tZYQXsXKcKAPCJToXk7EFqfLc
KqV5id7hKWIfWd/wQuJZOrmqL8njpfxbz0ZHYWwvDmwj9AeNZEtnglOTmWFe1Bo7SWZ8x0lomCsw
bKOnZOeCNa9LzPbplmuC+cQz+zx5mzQA3j8LIyB0pUNPnsl6DAGMPFLm4MJWanWAIMIz/I2Lw1wi
So31Oqwp4K/7pBONnP5D6gQXiuzo/Cpljzhm2aHfji83hBFfBiYqWyBe3s2BjQ9/56OgYD2m5LEA
r3ZsGlKlQMa+SVkWFiZX3GdE1JX01gejZZUsHxhHISbYLikndDoaz+goSywGuwtM2GyS8LIGd90+
Wr1EFBRnUzglcov77+0HyUarlAr9+tUlvtbA6TGiimLRcCdPqA5oAxfrIs9OpIB1iEGgDb/1LqeU
3unIK73Ew+ZKA+prfBigrO2PlXz7CCLpopTYDEKhd11/73jR+HMGhj0PlraCI3F98Dt9XpuLZL+N
ntodjQjhEMaX1uhPblrOcl1J6Qlyd95BHGNdNMT7+g2JfGNxx0WOwr31b2na6bDpdAfmNlII4ayI
YEdtV1he2vFazNr6pd8l9mLU81o4l3wuhsi1Ug2voIxo7oMNdRRQ/V+a0ZbJlIqOw++Yw5JPpyoU
i4jCtUlhgtZHEVtXJTBWv5G4g5TggiQlojSH5Q6JBg3G/XyCSBGpZ4GFaPKxVSiEFjXWVE3/m39/
0heNg2d5gD7hC0pfgHjXKwOujrJQUk6Vxpofh7y6qLUU7vITLCIIb8SxZJ5+6fOB26eSxRNj/jfa
4xxo0B2R1c6zMMFjOa4JF05p+H8rXvqFb4qelHsm3mx7e3wkUPx3vqbI9Up19WctIhwg31K4Cfw8
e84OLjDQtGQ4287eMcxXh+5/rZarWFl6NFza6CER35zfzNs4g4MqxYEzf8m6FwWH5alD75R1OAcR
GG1E0IhZtLMDQa7uf5AOf0JDPUZU8yiCs8VEY6+EVTlP5ChxXsEK+P+Ha6qp03nbw0he+07UnE8x
QnHmltMXbR3zvNfKSlpm2hbMoppIFSLiQxzq4PuhotXyVPbiymtdFm80p8y+f0RgTApa7+m2yexE
bI4De8Zo1wwVpyICCrDC8OSvnuts3/f9PPWcoQHrvArIsr+vKl+HEsJSi6ktHuWg3GoAPEXZoIpx
FlRcNqDsH4I431XOwpDwGgoucQTBAdHvX1AdqkI9hStiX33w0oMrXJVEtFjqwAoOg1ZZkMgGcFRr
e6wv66JFY5D+Pj/Cf+MLUZAnosGQjOaFg2JxNBkZH16Bfta/jWQGB3J1JTj7F69GnX+BUv6hPsFv
L//5uwppKwpMz0UgzO0OgxipZWMxmrTa1mUbPf70nMIvztGDdrMyzgRMY4DVydUz+X8Tv8IOJ3cA
Hx3SOGUVXfwodvy8Dvu5znrGs0RGj4arBbF02W/I1YLF4ncyXiTF41Yd17blE1S05NdvyUvzBQTv
msv+vFyBaz6xPPZaISYBvltPCiLo7icdwvnnqXITAzr9mY3tQckysa/yLp8XeoEvtqLBLVv55v1m
YbvdgD2mQ9kKWdag+oh8ELo4icZDvwd16Wec9PDY4tCXcSZatQarLHAawNaNxR4nq20NC/KSgasJ
8vyNZ9d0hrk6/8mbqSiaJmcglQyTYCJXLbiYmAEnKEAJQo1NyEhA4O1guoLMNcagokJjIf9mSQrX
o9whXjcMXQkWaoi/0lD6DPHIT7j93MXBrvowDZ9/cHnXrR/GfdC9l8hPrPFIkrXuetXxEgVfljuV
PeTqhir7aTSSzAa78Jj9kJH5zOAKpFH0oq6etKLgFecJDjHdUQ7MmG1TbkxGXeVxpJkJH2ZBf46S
BQxkFsJdyzl4scoCbjwa7zsjK2SGrOX2n9L9AmNV5nqWKRr9RA57vg7RJwrdY0rArK0V1zhPxyRI
1PC0mCyGxZckZBj7nPqsuNmjrJUjLXCW13eIQCpIn5tj1DlUCz/j2/o7hphGzSsIBtqtbhbaEaIL
UsLCJNbAQkVi/Fpas5WxV+Rd7NclLZd25D/5lmtu3QQiolJcKZSjPeSXI5+ncqS1nATsPLX9pCD1
fLSt0nIJ23PzG0Ku95T4RW5xkWB6ZzreYqxgjx64D1DIom7ccA7i/Q9BIwa6Ar6y9rLxIEWnjl+P
3zIM4fKQv4CJi3YNz5YHwNbZZzHOcKddXDHjbbwbF1uIJo2M/9W16t5iK3MN1U9JRj0IVNCu4New
56WB8rFg59o6ByJI2nFF+blLEMiGw6GASujXgGKLVq30VrMbdOBBCrAt40v2qGBz54+Ya7uYCOeS
vV5z41oBlCE6rbNyBMNynAAKw4HckCsFGE86b3L6Btw1ERV6CgHUYBkSVjFTjNSI9SfDgGdBxqI7
nofCTTFoSjenKLitUfnAL9hdQ2MnWJjo9Ro0lS8D9W2jz3QjJz4co8SMzAJipiWopppEZISaiqxC
PjjZnZ4bXeWd8xnWpWY2QcNQJOSYCXFwYeJS+EUCNRnzBToa5S0bP8vlYJOIRE04jCiwJr3DEjve
lxVPr+IM9UQmvSnfhpLnu9CB0yA/K0EeQk9SzPdoE3fIdagu9SqaRNmpbR3R74ofBAohCKKlGCL4
AHjxP184iRtSC7ti/VQfzn4beYNdaKYer3FF74u6+BuEKCjhnF9X87f76gahCTiO9X5P0BQJnWRt
WoSPdSFtt2YtKAi/9drVH0UZ80mbPK2yMNB/W0TloBvgs9b33JC50mt6iIrHOFQhak3dSu2o7LzL
KKMwDjpMxAgnW6Qf67tEjr45aJx6+yo44NL+jK7NiWarQrDhWRGHF4znZAqeMCX522aGoVHJeXp8
fI6yY6FfR1bq1QS4I1LgKLsH3bNRhhLSsd5zlr4w2VTm2eZo95AKlFtI8ygBhVAWzISgoCi9vG7j
Xc1nDKNG9iUjJatOydiXDTaCbr5xi64VOnXLplDEr7XFCO3jB4rQNFf8s8t+IDfXQTeISWpMcdi/
tZiuR61vedAqpC7RTyIsbbgo25LlNmdd1wkGNSPyQ5m6lhPSBlS5vUBfRolsw62DuQX3WCipOSUO
nztefB3o+Xhy9hfGS9z8HsMKo81/q0d3kjG0EPki+9CWBI8SserPW9PSeoGs59B0nHPK2S0m7QfE
fhoY8JM0vNOP9ouwG8AZlaBr/v+WuZwVHyfMrkMTwqrfgwTbeFSI5bwNOj3snPYeTllLK9wCDwAg
0+sfu2UsT3a3DIIpXZjSUhn00pOxyiCTFQMedPtEZGotVslgnfnuQ5tBRLMVNWuQrdVJjP1bBHnq
rU/N/jLdSQEGwoc+jrTgFPk+Tll+OOSFxqH1X77yDBr7mYITS2x2dglDcRu6crEQ5PpLarMF5g5u
msBGRpq6ho6+qB1/Uii08KWwnObS1GhDMs/q9FSthKVGrX729S00QhYXyJ5EMpJVFZELnvmnUu75
gYZxQtKLH5mMyMinPWd3n/X/07hGUiQi5qB03dJfgOVzEVTg0Onf+G1L8HTBRoJ+nzm4aauzxaBV
yYMu20Hmr9GZKNeY2qiezeQPuvuDKUQrE7/6N2t2Zdsh4fdlj3XlQaqz88SSby937JyiPNG3EHXu
l6wvpXYTIX6nCMwImiM/c3O8leL4FtpqnvtbHWjcOP9uK69DYDxQyR2rIlydLXPfkzixlr3LwwJH
/0ninV5D7usIOEw+PqWO2h4X0UYzOHpNICtPqrGkhtXINV4Hyn3B6PWeK9Xo7WRT7mxO5q6UEBHm
owR8jnmt/wM4pYmnOk8xVIGzMirFyKhb3EwAwYCnEnaHqhDai3t7iHxCIpHe9BmoTCTPLBx4UKJ/
W2tt8PYu98nSzb1ktYOpyAwVh8H0FS18YzIJPl3n+tj2Uog3hoQyTvACjxJyzJM8OTI99aNI2o5c
GRRbnUkDW1qMipN/EaMNt7nOEjm5+V0SG25nSjOXStI7YN9z+YxdoqGKG5BL01Nn61PFEl2jqosa
N3/IfUAYxL5XMrUH2FnHF6A3SnZyF6AMqaOBS4R4XTSv8mrgOOFUTFlMcmVwtGTFjoWPtgk2KzAm
EMDA7od95XU8jXcT6k6qXkbDkYDm4PySKrcRX6aDux7Ng0oNEJHQtjrw/98Lj2/7BIz9eiWetJ0A
jc+mjNW6nPLqf5IH9vMINcfAv9pwfrW9KYAGNTLrEpnW4ex88Q3W9udagOJi0HDYDIwLHrZoVhPJ
qoWATzyDYl6lyZxwBn7ENT5yAf4/eaWN9OokKxheWxyJQVQWYncjVIDoiFSeL0Jn3NLttM1G1Q1u
hqiBGN6hGArZC7Ms2odaN4N3GATZGqgCfOm00TndK5VJT8Hx5C7Hnyo3EQGgKIkMOD4nAIKw9IgO
PsM/dFOdt4McrnQXEbFEgnrQGktU5DQA0dQgAciECw0qsrnQrCWrCZSqB6N0ysMxccNWUvUu7Wdq
DC9iTOsfQSkK7/LuyBQKTdOx569gF75b9JubVR1lppkVQIeOamJG699QA4aVOBmLjFnInQcD4a0b
LM9qcVyKPLUNBfjH6WcDhNIzGSX/kMj3AZlLfbPZtivoWGUpH6XaVQDn80fVd8k1vVUsq/yd46Jv
j9sP8Ttk2XKJLSoASLLLX1jjP7+JmpQU4VKTnAtt2SGcG7ZR3L0Qzdt2AaXklsbneVURy8pGE+Le
CLEnWJIl7zY+Pb4cT/X48W8mFNzz4WiUz7nWvMrgALphCIKx4kixxxzFSAZvpO9mutZKnBRTay0P
JrpXaJaGAQ26n2wVPQadIduG9NyQ/qxe1lek54SLZ1zYibsKGOdS43do+s49n5zHkZ09d2D76kMf
kBOtv+FJjUe0t1WK4/4GBQ4lI/iqZyWl7WD+RX3d6krbTZ0uRKVLKY1D5dShyrgwHfjinJd+4PTb
LTISkVW89oAVavR1YKdPVTRpX5GIeSkP573I3k/eisdbwr9uUE+rNPyqVgkP+qXuTrGbbNhBUEu4
EwTU3zr96uhUSGDFmPpDN/Lzakx9PuOm1HOd7VWIUeUUcvunr11zMZothLo1h0FQTCJZ93nbJLW0
BzagbtrCe9NXE/qw4TNBgESAtoY57IPWD80Jtd84oB/PxlEdsRvpfcYDzGWZqFdV+n8E569CiRUk
Xb/ytvE62U260pCj4bUbhT7Glhu/igE/QeVGZSuaSxESyEMhqEfsa1FWnJtQWBwR99MRlw8iScY2
KB7L7RXv985p6tJ4NLeSWbbrm/cWz+pGBnCEtyd1tGok5ztMZs+JJOhonZASXyPcalJyuGJt/LmO
qytktRxXUpTzsQHIhwfYNGZfHF8lEYAC4Ng6YtapCM4hTrKgtLfUL+mDG5JUhwzr5ZbtQzwBtuKL
oIU44SN6ocB9ctobDd2AbL77vA1NKBU1rXacPW8mCcydKsDrHEDkyJyo3NR9DBt/y+6yI0RN/df7
67NyNv0hgg1IpeiBSQQVt+RhA7UgTpD0ngHqTid3hNh15cLtDoii0xhQNgloSm5PKE8FPdCuggyj
XlWrkbYSjStP1wGZ6at9EzvaOSb1djeSibf63SYwaJ50qdliCLhLzZSrU9Gq9iCHhGxufNUzE21t
9m1G874GGZVdgpolb6fqskDOK7SiJocO3jH/v1KGR5AUQWVVQ9VaMLfIMEwqao9zu1SsSocvQzyf
RerloCUWBCzU1xZ4xbJMTdnkVfU+ECtdn+UWvffE1Fr8CA4nIhG6M7uI4KYMPD0qF9rHs0XPcccr
BpUcqd5IsBsIWuxNt91iDatyVei/EJcOQ4ASoVoS/Q0+wPerRND/GVRd/xCQvyotpxyCnYC60gjF
pI3TIY3djj2QNUk1DsDoFR5B90kDlpo9U9f2/MfYYkng86Rrd+zSoQ9hENLzLkO78TLTf4zo1Jz+
yvpsy/pLdkfce2p2tJ708vzqdrTFgXAafPeIesPB9uL62usGuTDRHyDnjr7cumZ1nmhnlEstwboS
lOinStxl44Tp7uIaNeCcu6TeS3WYsHSSJaCNb1ghEKJKC/9dGkL4B1uDGY/q01w/eX/VxhrkQUNv
RRxDt8/3UNLLSlisDsQ0MaOmiLX+bFFmWobonuKTdlV+geAMkJjDM727W3zPtTCXly3NQX0UgrGl
OPpp0hZNHd1UxjHq36DN9DdXpkWYb41LkbSFR5ps2k8B9wQkq+/pIJTx479Y4VUFSUKCdjyP+hK1
5oGEw/0prH1K9s74/XS2ENA0cwwg7ws0tAR7pQCWXudgeIYcoKZ8HnFNqKsJ6lW5TRh4H9wQKp9u
iHMBNSi8UEx6h+yuGV+OkrBMw4QGlJdUQYaVKGEAwktvKVQ3kPnFfqec37AbXOrKMRvvppp8EzBo
+c4BECOhVpKlO+2wLfjH3ZsECHFWOM0V3jiDXmlxspfmYxAk13008fGm4FWEdtJ5iG1Hf0D/ycC/
n1jBZTaQJcI0xIwasUYJtaLuTAKJgFqRS0wRbwkNMJk3vDdkyPKowDcFomvx9IJZQq+pG8h1C7b3
3JlP7X1sz0yrN8BIgrMrZAa9jIw6vbatyA488SMLqE3eKRnAPo2txBIq5lKWyHu0GF2rFzDpe6+u
FRJjCaEId1+CE/GpAGZqlTARKsQbLw26FONsLLYm89JFMa7N9+Y6YFr0KSIxL1d7Ei8XCOEhSSgP
3J+16UkjXLNa6gRPcS0kiZ5h+7h4MUuKviCpsZMjXod6Sy8eDPSCZX/EnrDLRPv8P65MbUu4DiXH
1XDc7QxNtgCtSiZn/WbsMRafH941S6hS6Zx1I6GNl6NHbEw3gsghtav4N0m6jygkeCLq9/2IWcY6
zzUnwlbfm6sjjySQRv5dOVSbTRClEleewmpY8o5pnrwhhdSwS+SeTxmgdmNbom3TLO2J2+NHEiu1
GnJebSHziQXgUQYLINQRURqTXQt3ngO/cTr1niKVbCK2/f0nErZ5D+PUoN+3sjwlbRwBF/NlJtOo
a+EkOBMCX9Un3gcsuyFe5iyaEJCBWUGvawANlxYQCYGkrwusLqU8USFxJcqvaVdZzYh16QvqYY6K
XJYUV2s3wUKbRhitkOUo5+IWWw32r914eVh/cysfZ4IPULTElkCRaBKoBYPmXFuxkwTDT/t6hyoY
0ETAvRBv/7tk8q98hBzUYwmCpgrtlU29uKVr6FJ+w4Oymth6o0BoAoiyrulnFuuzMQyoLZSVpB3m
LyayqRumKfQWAKhnTjeSm6IJ+v6WS7Or7qH44mWwgAwHfffGtBt8AambwP8caB/rPAWI2vR/xj4t
Kvbfb97LbKMBBweetMWl7JORr3CWOtO4wRDq7Ax5ZrK21kEEE7tVA1jQJByAkwzssyb/N8Otuvnw
cIvKqtAgm0O5uBHI/pV0wIYkoTL/Nc+AetG0B9oB2xA9arPvjwJKPsDoNZgd7rYhfSux9mxMkLQo
Mn/EZME11VdKMe9S+F1EWhFlPv4Nrd+X3TU53rwVmNX0y4oDCQZH9vGnozhsLA+fsZMzG3ijweh9
XzUd9/WM08cvRC1LP1r8BCLPIozSQfOBFiOvfmoZpjRieo+NS5ZAqYTN63lpiszpdiEajgG8HqIE
NDXFkKBte+xd9HuQzC/RdMtUwtgVCkSAP5ZgMUEMpsHacQ7ppwRi7qzbUyW8/Z1bP9aPgYvyuAty
ifW1VqHi0lU4lcCDWad3wTYvlpsVQ9TIKt6ePPdOFwhTBa6xhfxQxIO4AIZKPWL9FZZCFp60sQOq
FOydpVtAfCt4bsJs+1QN4Zy0XnvdJ3duz4zi7LIsDpoBNBHXGrpgM4SNfyUcy/DWGaZW3uYu5K+0
uliWnKijlLaVq4WDefboOTsjlarFsBHWMhgUg3UWjbiDGtWRh4Prmo1vmgEGUINpIRuaJLyiYTy4
3k7X8w6vozpREvXmXLxmFxysjOfWrkvL2FANEGnm/t2AZ5TdQam+S06rhyBeMJR8MdeMcPDSPBlM
n416bj603+zsEUvTqB7fUrMgP7UZGaDx5JYkq98OT9rRxI+DZDCBFk7WTPjvULTSLFyiOdhvld/u
C2yYDzACp7jxP6/S6pMHk5PaZ3xlMHC6xR5SSJzE30RxAF0IS+0oBdSKlH1sY7WTp34w68lO3XXB
zgzRgN/iUOtfVMIOCsjzc3k95nTjKCD8TMOv4Jb0XoPlbHyYybkHn0Gx+pUYVC71Zbs8pE2PfTPQ
a0MKvxuoju+zazDUDUqIgBt8t5PG4/RAlOq+1AosD1ON51Z+c+REglrCQ8YgANzijvwX2bK9Mol+
iSyOKPPkVY6mCQFVXcdVmo2cR0DA95GEGMerr2n9nbUVi1+TdMBKrW2E5+Pr85D3ivKrHdPCg6Ap
hfDIyr76C8W4L3Ejqlgg/LRxbk8OFsHAVCxMir7qbHfWV9ky8ksDMIzeafho7zVNvAktCgeu88c0
QJdWPgYvSHWuNTjJr9tT9fpZHEi2tccwzTGZags/rdEJgTDtUN0lEafn2xylZ904zSevxA4spGqD
V6Il2/KeCcdUsYM5y/D+Yoym3lQAMaJmU75UfbCmMuLrDwWwfxbGiWFoN7nMnF/0SmYD+E7TL06c
a/e4NPpfw085dNkPPujXv/jrWV6fIzFZhHP6/T2fELJtFoQ7F7LO559Au8kzWczKWDZl4C6PXzjA
FAX8PskhRDrc5z6ubDbLkEXx/wSi50TLeN51xfcOchu6r90RwRpxVTcj4DRCJk5Tl59yb+qVWE3u
EOBSang0nFMGWKdEI7ZRU20mM3aVsyGOYnMPl5XK0z6auev3NyN3Lgqzuputb4j74rjrLZK38iWs
mJhZaBl9g3vrG/NuhGKoL7jSox5HsLY0ZgVOnpzpem7FyFhHmgIlVLSXpMTyS9UJkX/fcMfKn5V7
+jLHWAA3AXScpZ0uMabL4VO8nNL+YUfs+U/j0VPfytVaBMBoK//B6be1dvjmdVWMtJB9GGcfGLfa
ZC3oOgFDCPBixHEeguCi4B1ykqK8h99yDscWpXXVJUT2/ANys3oboFJgoYT3EudtY7LJRsPL2g1X
sszi4KDgTSegQoxI2yqjQn4uKCjV5XazRApumUHzw9FrwTW2afPc6R0qUGALKCKTfIhWOm7TWq0d
g8Q5iww8oZwlt9qSVh9TuzQ2z0Rn11lxP3kWkF5ukqRzHAiwjLu/aF5+r/wGqnB5PzqGRUX3R7bR
UO33rGMuphS7nDVcj0rSCEVkmda025kuy1+2uooQ/tEFGiYBh5UgkMfsojCBSxSSnHsJthYfyZFt
Ajd/pPrg3YDw/BaSdkDHCP12kKK08+hU/xffmRrxkJQwJPqnGAa6oUkgrEslgVySMpkjcN7scdHq
ayWuPz3TnRCPocwzADehzMz6db/u3WqhYh+cSGpvy84f1uJ0yz6t2aa+dqNg4HSntcAAo5ADoOxN
RBg3BR5ByrCL021wR6CCtqveLYK9XYGoQE74xjWkR+6CKNepGpxinCLbqTSxTyFCrBx+Pw2T3bdq
buA+Gb4OyXNCPJlb6HrCQXuqtTBRmO8yTl7W7LY4BPIe63m/sE8E4ao1/HA0vi2LAHm+WeAlKV/S
qXXZADIugK+BFwUezYRMs4fJ/8e9SjXs3RsJ6NWIcxy4+B/8iCgWaOwO9bFitvLebUqI+P9VykcX
bc16LTmgnf/Z3NXFRSsiQjoHaZpbdNpexD5UTgms4XZWZARfxcYEMdVFVVXf0ddWG4cI+ubZDQbd
lozge8VeC1Mr74iuVbqHODRQjBj5b99vNiy+cqhmy+6qP5jtRxpPuxm44IkhLYM3C4rha37AO3uG
+fJYInLrd9jQjdsH9QQSVQrHIDevY955FTrUa3RNCj2q3xHlU9M95kcbYb6YzqDHyNMpaVO12FIH
EIT7LQReIqpmQhCWhdU/40d05rq60Qzy+mUAu/ZuDUm3AIq0aSepdecsYt9MDxdeTPOTZNbdjqWf
y4DRQKuIN9H6+LtOwEjzQ1JwV0O5M6Cv2LLz1+UUr8Xyu5OcmVH/iSi+kDL9ei1UyiIyAt/nJigT
w1LTZAQfusV7SQkdIcuMM535mnnKZn8jruI65MoF1cnQE5SciVLbK2N8OZHVFf1dhJEnAjtwpE4L
kmsXEMNt1Jz1ApdBkbtV4v1wx5Dkd18eZyia/Ct9Szmhfh0+mUpUtzco/GmZetAi9cc5UJ0/hUmT
r/ohWsjwRUCb9sXOpWCwoWY2KhOY+UZTxJz4/IjhQn72aZ+7U5d7mc9eZ1KT/eLYdN6tGaqUivMO
dpxgmitUc1ChNoVCOL8tjNrEnNWBjQNSOylxQXdkf2dJwM0iL6301iRD/dqk6sCriZycjvF/gXEW
RPmg+NyBI2fikbsPtspg//2oderWvmgI/NHhfTB06ULKITCONTjKl4Lv/9lZuwNFxlqCeu0jtjod
em0r3z0vDDTPvhX4lxFzQYAwDbOksUvV9lU8zsnPtHkecnZpr8srNnSINE56I8cC2tIonnR/crWS
52Y/d27zpjXYBut0brJ/Z6pN7yjZCS0lC8Du9ydzKXMGZGYOeHKISttQ+tuBb0rH9qbt5sbq9U1P
x8Y9cgQV0+s67j6WWiFXXhDjh4LjvWedMcTkxB3ICX2pAwO+eQ98FwKq8RJjaLfYrPwVAtMTcqo/
+Bf8E3IcLX3qRgLzcpdiqe5gwWa9W7hz+XpqrzSnDXpdgniwlMekkSMycyeX3oAVxGryPPFzhKgR
inubhD6ns+VXoGKfZKv0SlCVbu4G/rL1kEOpscBlWni6b0b/DIpT3SiX3hbM8Ewp1mMwIqLqX3Kj
fnrF1cPPDJA14fn1/T4cxJt70QiHvKXMm8G6WSV8ZdZyf0+vkmWMWbCo3QAoA6TOUNeBdJJktfZi
wHMDxAEvM3iC3Oqn6hm0oY5noJmpjnigBMs1ffsfoc5+XxJjCDAB+JoRTEljPLgrOCqwRnbmwuhD
rL2exY7ZjJqVYwXnSEl3cwsP8UyJYIpG7nnlAX7Q43hd+eETmG9le3fLfvYVqYCY52kSHQ7pjNFF
xvf6XZU/CcdFSja8FVvll0eAek07zqFneKutUShP4iDkPQTxSku8oR0cgVi+HPiuIqZn+Y/khm0x
ws+e0K1bhgnSw94HN+Dk/05zLSZluOJiXpXzB6Wm06dHBW8mzVY+tQ2xqRYxfwDhkxxzjY8CPZnc
bSH0Mz8+XJ8OPlvTJZbJo/Hu1wgnQLpZHaXTyEvqbZh5nE5A2OQvCZVuLJ6ffYwI+i6ZlFwdjsho
hA6T+dvKbRX1BmpjfnMHf9QLUhn6AjUx5XtuMAdjOcv6Q4dmfl9PNiwV/CB5XgxTnQ0jwljgQVZs
02tGT/a1kU85ED+YLzlHenQgJ4RdeOyJPiW44oDl+gP/PLwV3P9mYAZddratxPEJyJ7tTZpm4Ht9
KcjnznaMoTxxgTK5AhAWlvWnAHngzwuDoEN4wj8LKk5Zt5GFDPJSyOPdZfFBf0JANEICzpXQ9y8E
2WoMbh5y0lPiWOmWftVQFJ6TSmKgvgl9gFf/v+lwiDCBI7eay7S+0WV7u3Crw3aVJQgZITiy2ljN
xaO038FuIxHLRV5Al9cyXcNJiXzDid7V4IZ9GhQUkXU5p6RkADvMPFqbnyJYMQLt20nPUNg5mwjQ
geawtquZqNBRPDkAsY36g7POzoz6RyBSBW4XlDjz3tAhSopGcU/3ZTQwc6nrHReAi1z2K/HAYjY/
WbDa2nFFnnPYcgPxr0h6cKyKw+HME9U8ixcJxE/24I+5mNzYZj1X/h9/yhHS6Rha2zbZv1l18vaX
HRKQ6wzNqMkxBBg/CJA7hJjQYpZcBTYf+hzTdemjMmdVBVwa2AXQAQTpyHixqYFv5jw2Mup2OWQd
TUcBJPRhxOPBSedznoUo60sQScICZ7sTEYnHgTwn2rU/ydpprkKl9h5CCKt7nkit95WlG/BOAOqb
nRSHOYrqkYVTq4QGuLtZcMcUKhI0bFO2I7jPtO1bdg9/DpZchDC2c5sztI6qf6Nvt9HqAtUdbRDG
HCEctwtx9D8VhumnKllwN43icKXG6gIs+w9IJ5vugWRGS79a9wJF9E8sGESf9TUbKH2gHtzu8t58
/nM5XCHfKAk2SmH+mw4TrXrX2LOY/mQFqkkM1t0BD23nl16xAC/alnDNZJGjQurEzP9zD67uav00
Z65TDv9F4r2iXcyBczBVakX/ulphdjLPsFwxQUJB+KA5HWsFmcaWJqakEFjlZEIOBIQHuf6Nu50I
j7NmXqanuWWHRv9IcGDs0My4r6t1oLPXgvQgmUT08X79mdYajXQPR4E5Y/nQjRnWaDJWhb0VCynl
I3u8Z/wfTT67IITxXPbXp5Nv5WCE9n8zMM8dmbbOXYE/znX/LtHEn+mYwgPVXZCZSwLkIPxnIr0w
nrvmLfPK+TxgTHtyEW5Ia1KFvyG59jR50NVWZ2/X3FzN74fOaKm9w0rkqRsP6GR2tliVCWwvqVo9
IppNcw14gYyccvkkNkJEqlQnOTzOEwy/t6AqhiQuptyhdUaeKgatddhUj3lBBoKeCV+omsIbIpiP
ri7clsuI0OuuTV5y8mcPgoMelXuWseayvIuKN+7pPgQSCWOFFdd4M8KFJJEguvvABOQl8wfqsTpl
B/6Ez0GLyKzCGLFDNhcXVlK9YZGDM3ZkVYScYbbmyOQXLyXSMy2ifzRlpowQfqMb+pUNcB00meuV
Nh5OL9rMnodNY1OnqGc8rQQMbC/Bvr4/7yiSDA+q7/i89ofzLzdCXszELyzbzyKSP9F0pUNXNe/F
71uo0xjN4EzzGEAlDNYZN8OApXbwz3vCgWSntNGVVWWXfMQDOVoKqHXnI2f3beteiFTjQBONUfnA
+sRjX1zL38j5iksMi5EPpL+z39dYmnHXCGnZA7H1xa9hjfL7DxlauLGh6O8XNTb3Pibj0OUFS0NF
h4U2YVYlhFHMVJqM9mm5Qi0p98sIXeuaXcq+ffKDnlvfT3tOQTbeypjv3/2klEObmO+ubCqQKOAn
yqhrbNQKWt63t2gP5k8Y99xiLX8oGzyDxbCrxWYK/6WeYgK5qDjL7VMeOlFCacVDo2CCAbVERIFt
Jd9UoviHLnQtb9wHIxCLqpdiNyg9wr1yUMtq3HYCpKCbtlkmQ2nrThVbPyElxHtrNRIww+hfrb/9
hXdM+UsK/gTpRq/RJ8IAmGKb0SP40hSkb3W3p/ATwEKIs19ylGydvHoEXrU5N8WLsI0cbY6FkF2f
OPzEfXAQvPgI2R4K5FN88y7M1PUGW3/kFuvtcX2p5Bf+4XlW6LHQ90qa1k5XQ16P7/yHWDGUxVxW
8i6bD2HI1pbEyhdR39bbSkwRF4NaomlNtQ7AwgOSMYO8DrahsOcDeH1mUYEXf4xR+8ZegtmVKEPM
IgNIhVHIzh0Pca1kYzpTgx3hGPXe4KdEKqu/pjCBZZAkVbDXRYnz0cAG8YfF3EH+8JBO1FxWtB/T
omVJSHv/KEJQMCUpioF3v7At0wYDnAjJLNIgy9xWA4BzyPVDf4hyh7tC39cwZ6eTydGeRc9D5ggm
Q+HHIn21X3ZFRNFhFzzDsty+ayKasSL6YzAbxpbqLch6R157T/tRzGJ5nKhv6dYAYHgkBQ8+zgJ3
hLrrj6zlzmJ0obF+To6iQ8iNu8W1tnysAYDVfP5rY2i6XrnPCj+ltqtPotxL00UN/a4Vl9zi1tLl
HS4Y24DMm6+zTgUD95Ydfwt6d2323uFWHuYRalBMg18rAPa2ktoGDfUQkPpNz0eRQvqTcBvCXIGh
AO2y/lPX+UhUQ4PxXIf4bR4+WC+61+0WvcNMSkkGkJMTFmYo0tflsHgbTcr7M6ZwYgIIoA8WKSOM
EnNsR9ADVhs2uKZzlau6KVMs+/sCosfYbnlFCnB1dOpG4uhaHOkDfaO1WIb36IpJI45tBkPxBRnR
DUaQ7g2jLB+KI8vepPPuTS1qnoPKIgtdIsHWMNytOF6MLoXwdbmHWB0L2XBm62D9qiK99VPvPQHi
vHjnKvMkbzEqPO/1sMd1vXdM1K0+ik4fTSp4QJ+GrP7EtyqhMyYK2gzwmGZ3kOJjBlCandt3KCpx
ewubQ8duIrleqoDDn3TMc/r/jZoLnfRBUsZ89GwRUwZl6El9UEJtlXyZzoMK6TDNZgB258ErM6IB
TBZBjYvjlGAxXrJ8GVxbEBd1Dn99sUbLs2cSTyn1XHr71CybVN6znsQStuGKWOXh3IRggTp6UAXd
4DEsIZn8nMGfP0z+2N/Ks8MIm9W8xVMM4ngQhEQde08HXhFh1hgKVtkLs4NqRLAUYPbSnF5yIJMr
pF4PzbTPgzZ1H8lbv0K5lTc2Njhf21smY47uMkZtFXAybBbobhZA9IESW3dX2CqVnQ0/atqcawIM
QUXnrtCqEFoJC7vDGFBPBsCZUmRRuur1/ljwy4oc9gTvAqt3d+uyR4YJ9ud0/K9KwlFoYnIHi1b7
qiif2Kz+570rEk1YKNhNzJV2XtLuYKP7QGVfmRBVirER706t+SNfNBbbTGmQJ9TFFXHKkXAxLfcT
yWM/AUPQdwXUZSYj9KtFzZ43mMYR0PljsWrbepFJFdSmd1hsnqDsH7eXhpoKEdXxIUBxi73CArw7
wJ4fAFmGUxJBdrFP76HgTMXS53zm6jHLVsY6ogbTengBb8VBT9kujBIFL3fyrURGueIu1mjeHyN4
uZZJoQ6jXP72tLGxlYdgsbjQAHyIKmpq7F9XjNDEZL4ATHaqDfLnMJtS/wSB1G0ctfG8r0PmEiJ4
RCc8s110iNYi5XCgaPAAxPGzqFfnAgYr+VixumGB705LwilPrwvS72KvnMMohRe8nJFz65iOE9WT
KI9qiS4Xfu6ODmnZU+OCc0HlcLKK1OY+dp5Q+8UVkCDp3DhZHqfr46RJCSdjU7Uh7FkLElJnGyz9
XQhMaWApmPc81bwEw95WBPR9DlAscvTlbsS/mgnymrNth1O5Bod8SQ40Yu9Ktn97AZ5DB1+/lHmd
6Cuyx6aXrJQ9XsoJlJYd2X0fka21RhxW6v5iu24OOznL1iJc9wv2RonQWyKGPijZTM7fe8+kOIZN
gFfHSi4Qja7X3bPh/M9X/kQbaehtPbznicAKZRKleosrQsGgBApARuiDCcU4KdLHjBtpa1nVB7bR
6eJ3ik/3IeuJUx+8zaZ7DL3KSpHQi+FyYn4o7tl+VT95BgS35QMk3DpgueFfrU/h6XPkVCqU/rck
mJBjZsTaA/CD5IXmWz8XD/7tdJh5BQULK8SQR6qBQzCqDnyQmZF/SXrUN/BLtVcaT69nNfySrkTo
avVbt1eqDYsN5muC/EssV54RXIowcUw0dj6hR0u61d5Ct2cn+X1tJ1IbnIg/GH76DWY993B19H73
LN9JWuwCwS8oJXSpWoN9RuhX+RsslbsYxm7//QNJd75KWJkNQtAGa+afaGTFKALoEzDTZ7kE98WF
rm8ZdeggUaY9JiFq/avJ1GH5ijfIzoehPJcWS3GCEBnZXYOUjwSiyhaB3zLgBIA+LLQ65MHD6lwr
8gUaJDkX60Rg1qg6kEUK70Pr2xsyuBOwvWyE7dEs0ODMCrh8mVKNfui3WV0MiK2ZsNLIY3XQlOFi
iFXXHp3icKcsVkJowyHuGZjMtKTKVpf0p8Uv6U8C9XMKtHK7+tsh2vzQNws9raJUa4SpMNY/1J1Y
pTRzxiP8vcwEmpVxBRoOAx22EzbgLc5ur8USWfRkCLzdaCRpiX6IlEsj4GFHCUejxD5wy6ZTNzRI
FF5QptPYY8zbTiFGf5ov2m+3wk02eND0AKB8CPp4zWQvZPMuWRmN6b9IePzrkLkWL2BI2GIr2sEG
CbenUvcd6GkvXB1E+PLjbwIB6FzezGzaW39FjQfDzZTVH/f0kxEIGxvjYXaad5+z3uXfnrqgdUem
YqG5FHXJmeMnKSP1uhNl+IoLUFnVgZsiAnx9RbJTHmDNGBNdAT6FBSTYm3Mr1gWjZzoh/OApbqum
nKFVVG0UTcZd4qNM+wycFUFnb8XxqEOb9F6xC4aUWuOrE0Wn83kjiT1brM8uwH1Fpyez4zoGmitP
0GIOQSM7on4yT1jWk8Xu667Y6oHDoZ3kPKnsA7KqF0iFMU3+6xUljmYr4c3/By2GVVkF4Ar3Zalr
4UaGd6dTzJI+tRHLK3Ue6SSRzWaWmmEx0Z784j3WMJnRbj+yNjNGd4qtUYWBXcp2HzCvMdSmIuC7
8IcsLMwhoXdGtm2P5rsxCmabPcZqE1+OGDXtQZ/Zlc4cxdLKb4aN5T3HOE+p911y1pKVSGkULG9H
L4B53bKhCTtNBWcxS9IGa4HP8qkM/uH9hJADtv+qVrUe0Y9JX73O2KJ0RSb2Tn0WYS1XyrWSFXwg
VbhJQ/GDwB3JH5U+C2xVrYAC8cWbVCysYVjqEjMX3DZGspRcgwC3Nxr/AdGDZLC4/KukX8ACPJx8
gN2m9V7lvq8dMEACHsXFKaRqqhD9cufqfpdQpP9j6bjBj+8sl1/LWh7paaQoAjDH11Sp4ZLZnB4m
aG0Bq9MzN3cZzjPm3u87dUAra5/q4REjTdH7ZLctTVS/QEUZv6Jv4gEtny0sX6ZK2gLWdz9yupIP
a8L9LJe7wTCAFRWjapJON87d7yKCT19sbGGDY0d5QGDh/OQa+A8frMUUbtXP7ci/QXBVx0/DRc1Q
C9yFdXKR8UV2U0PiBVKpQbq8h0FDROhq7TNTH0rI0BJFxbWIMEhG4VOpKyFwj13jir8EJNE0iyXA
Hb/M+1+tn6FSlMIAJ15sXgXiLVXjxAeVj8Ru/Js6QW6Ztqyytu5tcLMIuNYKfAE8aWJUlkeiXRgu
HEY1QGtuUJpbNx2VMDSc1PSljGLH/ogURoXAvNzjNSatgeKM5CiNV66rFyE9h9Sdq43iN/BUsZm9
2PoYRlj8//gE/JD6HMDBdy3vLwgliDRqR5DT8rjDRa6hci9828YkuOnAIUsV7xi6Qy1BC/+1/i76
FYd1ixJXfaggwpLOwTV5qQDAcf2WK2Dju+3Bg7GVP7dMT14onwUjZdufLSETt3N0UVM82iCFkXr5
Ikpm3Biz9ukygKDuXc9N7YRxQ/s23Fl0x/0PQbzQW21+KBoI8l7OgAeThiJdiTixOPA7XhTphL1w
OisFTSjIDHvjfv+urke+Lwt78cdELSgNy94oMDQRmsJKbWbG4kvxDhYmeLcva24RizNmCYmMbRQR
SGtz33IUbC3IYckmjaQoAJEjMUK03t1KjhmKgz6o3EHW688MTMDI95TY2BX/QRR2BbT8vR5CX9k0
n8fJDWj3j178Ymwj+7LOYy/3yQC3ELYF7PaXwMsYi8ZgGlV50brbHtwjrd39nYdc/foW8hKP85Cb
waDJt0vB7+JJrpVOzp/mL1Io2s4wVofNMMlSgu1NVLkxfrGxp1Z3TvUIzvfOpxZ8BOOk8e5WbLQE
EnZqHRv+nF4CBpYhmXzaHTtODBo5cz5ur09kFyWuRB1KY4ipDi7vO4QWiQMKObWLr/yCoUle+9fE
d4ipli6JSo+1evC0V/A5L+bXgrUnxZcps3gm9rJXLouRFWhAtKGDU6LknRjQRVWMggP5yGVj162h
PV8n50CHxjXnpjX+uM7oWmiGONPzkXL9VUwJv3m5KLM4XpyrSTHSj5IzBwbhzz5JPW3QaFTiIEjy
lw0feC5Zgej+9anRnvsPhvgkXY05Tfh8yeKD7GcDxS52DbDjAzyj495CbhOMAdpz0q6ErGT/nbwM
u78neS36dzGRafixO2/cPJNorlSB6TfJq0nfJzzSELNPzxXsUC7RTv+SZpdqaAcHDNEURSbg8aVj
X2+NOj1nii7OwHPaEgaE1fN052c2alMCwdtWnLazddkVbn483KqJcIg5Nd+xlazEd1PldL9Pis2N
JP4ZAdDyLDPIRhjj7v7BywJTu1baMZM0WOqET/2b7AD/yHNBEs70/DqFYssAv6wkXBDF7vYn4Imz
wNQJI4BRQSvkTnvx79lP+j406rk1UCjGS27g+jeBSEqCuAlE2wQGQfUC0O5GXLfy4goCgLsvUC2K
we7EaEIZy6Y0CBJxXvGpeZUEbGNu5Gl7kxoPVH3UyIa5XOMCip4D/NS1/oDkR0EfgTjiMwGr7R+N
fC78P/KLPZTA2goOr6fK1DSD6SQiUuHHBIEkPcFg3ciPU8WaFfgz1KjVzqMIYjoGrJQF1DkJ5HO/
X49PE5kspbEqFughDqmmNQCdg5QP9GyM1g0nmymhxUKfvvHlNuSITOA5qx5aY3LWPjY+wt7Os+/u
TsjCQk1l5ZwdPiiJ+z88aj3UwKeQYJv/uNLnJEco6wE0DrUDlpOHFu1bY2+UlNJZ5OYtCRuaFdBL
9tsRQQBRMosOmM1laWxaKo6YUJ1DOxADYELtGQcnIl/acEaE4NSbwo1H6JGVLwNQt2l2UqmJFXaZ
I7YCgg3TBq+VoDIsvOLgkW9xdSIvz8Gp0a13nzkKWMmKofQxZaLCWxRX9fLQaS/2MmrSiuoVwANs
T2W2ltnbm49Ih7H9hTk6Zjc3W6gpdj55THMcMtN5IKG2/00MPSRFMiIrqRM+5UjDLww/zrNwonq8
B9p+VJWMfNjcwK7tOEiCsEGyKO4MOkajkf44a8rs20iTqOje19DohAZeO9sY/LAS5+GLimJZyurI
lST2Z/28WUNR+TeSM8BFP2c0o+vZyJlHqteic98evdULYH25W6RocO6dQa02w5muPcaQiaGMeMDT
9nUYUECoWcaigWBfv3YehlW71hFZju+cb0qADCr8IHgDTskLsuoKRUpki9LIubcRqu3IXoHnlMC6
pCr/IN7VKpaD1kdRBlwTy0NA2KPKWKYhs6yXIHgW8UsjuhEXzREDZarJUrBv5QnH5Z66WDTd7bJe
ju82o9vm0I+crwkkKAXDGZwA5wHRxBK5CA51kiGJ7G2nLr2NDG8BhKmmwNHgnq7sZAjldmAq5eoI
1LbmCsfTUDUCwkuumh5vkm3SrbqX0OzyjxHTa5kjzaKTm9v2nDrD3dw+3w13olfH98fHpt8yRWXS
PDPR/RBFaDLjl0YbWngR+r4ElacUXTSy8EKiM7L6wECRUo3AddTXLC6Cdz9svYBdMZyLs8a8GF7e
IEghER5gPa4D3r+BP//JdXpjbakvKu6b7bWiGwVBJ7KHWHXScWCbiBS6k5ViA9l9PPRm67zRfE5i
xp4RPU7e9OD85czWH58pSYcOdWZ82Cx1zBgs7WOLUpyXiMxrpT1CL+5gayp6Ad+MYIdELPLhLprR
exM3NTXrv60MK9QqljHysE3eYlmw1JbGQUrvbC3iBEvW4lr4vBJP4mvOLt3EjxGriLThm8zP7liI
MdMioTINW6q4plXlpD9+VXFgSdW5l55/ukC86wLrP+NIW8gPKsQZUxsbQFwQ8bw44oDWrueiXOwf
TxB1QM2Y+gMf6xXSwldLAl0GZLxqfxrStoanhGmNjnzCTlQNprL6tkhHo87jc0GVcPT3I0wFmN6a
Ph63vi7qe7QfTOEiQqrrdP92F8Ewmr1DsPsm8tgeTqEhyiZ3q26sPS/bC5KEBk8WVi4/+9xIW5xv
I1XBHm1SnYjQw9rPq9qpJq4V2FNFfbYcKm0k07ypY3+lsd09QkY38hRqzzc9SN0q2OW/SZx3adVm
Dv4ZzZP9F1/ZgA+o7DKrBhRMIEdiDioCDFKyPOUEExvQupmYd9uMA4JiTXX5nfIafrz82KWKeFjH
DxSpSQDmQYR2xacty0a7EOF3FU6l7O08mu7ACX+ku1UQIEHPNkYpX6IihLAHon9B/Zg5lrR/SQWj
09a+6iahDToAkylFO0I+yfgIKT1nJ8ZQ9w3ZZEoU9PVSS84KxI3fKjXDfq8C4VyNgwM74bMSVaO6
p2o2ehrCpX1h8q09pP4Brt+gzP/Y+oW7KwxRlylxAAyohN+xm/4Jkg1B7MVW4ia3zLKTniia+rsY
BwDLm8T3d0P4TqMf4gT+eMuEMotL+cZNFSskCzA36NI9Yyw8MnR/VJzAmz85RPS/sfFRi0O21Ovo
XfH8yvcnsskxgi7ChDXx6yPZMijGndCOdup3+yFBKxoyYBKIo/Ej7/THsjHpELEybfWVG8coFAB7
QpbIZe5UBx7PrMPzyzxIU9Lu9BAsbEYPzujX+ko+2gk6b/n6YnX7XS+DrTxCmcwWAIoRWbU/JWTd
NLNbRyls5u2z8vj7q4t1/fQJNrTncX54yUg/L4MNy7ZLj72wy1phqFe9KltfdNir2HvwVw16UVun
GbakyUhTKMQTmWnkcNbd6JJw8o527pEkhVM18WIHPgdsa+DdSkq61ToTTbC+PN1XRUCRQ6gv4QqJ
uTrNGniRWmzWMzheljsArvznoDM/LQQo7miyohw7U0xsDnxiUeDWR/3Lvh36WcOyLiOQHVO4YlJO
xU0mpk+IuqhBF05cXoh1K/xjhd0jKO0PtK6ABqCVIkO1QykC37IusvpoQL/OQKYttqHoOg6npp2p
qF9Af+b82vHTR9dxIuOzudBgq5SYlV5nyix3Ustmh1u7RyMthr7azk6DMkCiJytgkQNfDwb1ubfq
F8vX/O1KQxRdZKa7FQzugqkoEN+vDIcE23YaWc/89T801kQ14652wkLxtC8KHLUPp5yOO+GvF5am
zNCPWEeDrt8cZgNSJX3/4+Mpb7FCIGelSlqA5cjY7tgGAlWXznGRy2dfzKR0+LuaXF8jWAvETEnB
yVbx+lECmg9AstsO0xe4BQ69muPxjuoGySn/y4iew5T0gkUiWrJhlgtHEolDQVlanuFEiQW9H52j
WkGKLdnVJDPIcgsTB4p0qEYp/i/VcfwhcIEcMwS7oDNnZmkuD/MuLCdtwxgsjV+uv0Q4gQv7IRbL
hNAwLKqXLfB2G9XPKy7MAs9VruIHmsdRq0uprB0WuwufgKmWDeWfB1h9DIdLd+QPIMDvSibf8npk
paoOJGo1w5UBJne2qCc6g9CuBJeiUw1HGlyrh2FGLSbtmDvVQdZSmU1//K1z8kCA2wSKzkVZvl3/
B88eDwLR0/Scq/8SPbNx8aE4zB30W/XzCT1rBdj5lMYUdICrGXDeMcZBal/2ornNNP2lkOiHn5k2
LpID+EQ7JfywxOlabWusedIZCNM/NmzeTNpAC7GNKITzYPc1/oelR3skWT6AjsiavOSyBebmaby4
jth4Hom23yz1rulX+fF7hdZKPOsag138fCSTMxWbq2D4uMyzCcE4ZNMUWwzxH0wkvhjzsTD1ZIBQ
EPEnFDOsQkVGnHXjZ8waWg+yUvxPf4Ifb7CL/xM5ftznzkYCSMiWB8+d7b04pgOrKo98hQq8yYEV
HDW7Ln3Bkfb0CuIMlQpEnMXs66UV66EY7Sf1Lkf45yGiR2n5XHcFV2GPeO6L4MOx0t1c0Z8jB/0h
+k8EydVK3XHqhGW0Y8qG3Aby+ncURdQDuJsO6DS0cFajUgF8KuCWkygWPxn5SO6yeAmR1ZjUn6J5
pLOG8fgjOSYge11Im8mI4Dt/O6hbHAQQhG1dNB2RoLZb8fd4O4lFxqfyAhzmXMnQg4VuJjZwWRPT
yifRd0hv5g+ujpWCKONnZ4yISRub8EB72BfOBaqFD5TZomFUgKl8riMkdlIux5Js1HCb1S9EMwYm
JNNjXJXYeADmWMFR9kouvIuko5drwYEGFbY/PLCAM/xu0qm4ypLfETsNec0qv07eiDRBs6fR7oP2
kBTEOi/7D0cLE8EAWr9J589FPn4MtrVd442qFDly9qNwBGJTV25rGRqgw2GUuCXV7ASD4crfI13f
yOoToUP3K9ZXG4nv8CmHJ91lTdIEErOO1dUW+eiXeFFUnZfBgrRRnWf7sL5L5/+4rjtHOGrspdVq
DhtdsD3zdX1DrBg+S2usIKhlnvDJXYitYKJ8s4MSGDdz6TVzgB+QLqrt7czSMx+kTrvxtz+MIMhH
q+UjeRl4e9yYBUJV8KPimrny9y1TSvQ2aVNxKnhBZrYpX2kgTUyBHXKdh70E7Ncgq9Rydd4noHx5
ZSuuZ4yf8h55itWGKFdsI1EafZlRgv5RyZVEr3hTg3/Vvjgwlh77Rliwlq+CrVH++6s8bDhuQr4y
L4BU+0tYKuM+RZ7MznIYnw0wtGZWlnaNSfrTqThKLk7sTYaOa8VqqZlnSYWODUrpcNYdTXSvTkn7
Z8y4ns8yPy96kHpn9QW/1HWn/Ia6zZG8YhbUOPHOgYosueiIK9/+jv6+3voqZX6S2lofD8tcK1qQ
8lXxWGo/J54vel7FF+pTMHTx10DsPtvv2BGQLWXd/+ay7N6++2/uKs+Z8p79EQTIxk6VdB1Yplnq
cddxKGGW684LcqYPAz5vP1vaYMrZeyTlO0ZgRYpFlP1mwfOvDtuhiTZ1CwV5Xz5m5xD9McFNKJDG
fZMbmKfKz6a+dUP+ieOyG2DdVqxld0Iuxvs25LFw6rE8rTtkA4s8pyNvG1vqJpjGKrofdX0ZMMDP
kMqHxLKmvoMi0uThS8CdoFB+ldgjYHZG/vHIObjKX+L3QYNxiIhEWsRDcP4oxSeAwoxL0VTchCrz
Kkfi2izvHN99d33nZZ0A5++RTaX9UN0sX+TPPNVIlKfAvezeXJ8Lqk3Cy2f5+Obm/vobkQ3pv55x
HNaUvyLga0l2p6VxopVthiXmU0w/EGIptX4rX+C1amObn0YYM0nH9ieiN742JUHePDgriGPVy7NL
AqcNahGP8w+oNX5ThZno/1RnnyxW7AimW5uqO9Rd0LPyTRMbrka9HCCwhhGKh5YJNRxjaq8l6kKS
Vlkhc3+ljqDAiUUMFhiJGM6t+CVQpVV5lax7uR1YCY3QYz9qyvwZVWWJmcUJjQ9BtUBi/WUa6hLW
hJXvIID4Sjv83UyRxfi3W7+adX6B1l+oVxrfSfdWpS7u7/68ZaTJ6TyQJHpSGBJoNHKaeyky56NR
q8Y4TAL+ldXD3j0qPSmSKTIW8QuiUs1cLmvdPvNBWfh+SiXAKiCNhOft8DnPCa29EakgIYNxsE5m
1UYK1B62UwLE8UGtJgTeoo59XXxGsw8CpZwQivS3Iy2q0o+yoIoTnPFw97eDaF7uSuMtagfXN7Ym
gtv0UUSpR7uDeDhudxdyPKSuz99MsC6LqcXWTXrxn73/rXed7+4DYQwAnYU0eXhPNEAJGkj7zEoM
v+9X143yYxGX7vQ5ZkRrCQA0nGidkkNLJdlRIObJAqRbZQaa+YhmC1TsVsBvQebBwIk+VKOMeSEG
nWnmaWAH9euFELyV5UDm/TqQW0GV7g33VgIDLlByblCxnJxF0wwyeuF3RRWk0CtLM2fEp0KfFNYR
GJ4AZruOqpeXi1Vh0q6IpPwyAQmz80rw/Mg1BRzMSUpn0+INIaSZltqwdpInVn0bQTzj7ctXw8ek
fpbbq0lhiP6YOQ9ZNXEx/hWukYsgbpDUroAoXNU1GFMdvwvNO/ALigP1zx8GYwUgzg6uQlOZ4wsX
B/2A6BXxC6RqfBGd9HjycvEpwCZE6YBF5ivqU+F5wOuC7+vZ1/mxRlESgqBjvqpnT8KfpHiiSupY
Q5CwzLQ/6jOb02AgIfO1C/oL67YGeQcKEh0Il3wgyNeJswUSGuMMOINXj/J+S8HITsR6rOlinqmZ
KTnOhQNZzd5R03/12jCArWPQjkrR5YmKIvX6smQLuR9ASXQ+e8PqVJ9T1DvqolB1GUzpFIbTAKs+
u64ixEXHLn+Uii2uYcZMY/XSHZcQeoO/RhVdnwHfIXpjRJx+/49OyCGP11GXK0658zAMoxbHUtJi
o44MCMnBNAO4nXo0F7gPp6XytJI6v7cvpGxzrdwruXYSwVXc3EB8l/rlAdudtQY+pMClV/cblcCq
8SgtLD+6iSs8d2+6QIu7EVFIV/DD0QI7qGk0BiOwDjcP5Nq+t4QcpiEB+kyMD/wKIGfFoLCZUPRB
bVtLMGL+EEyEaXqAW8UPF6F2AMpn8zLkBldtoCa/IWeTZBosYgsMfzzNN9N4jsJ8Juf9STDVateX
TDZbi591cgxhbHg6xxa3X3q4Eco+U6mIj13PqwYO9ltMx+eRO6+7V6biKWfVgjdaNcamiGeBEv0v
7KFixf6IzIgHZTDjXLH4FKH4nypSbhNplvKSQq/p1s2DjEX2m1qFzEXcabKELIFujjJ7/e8PqawC
3Z+ltBlboyy+j2C090Fk9C+in8R2BC1pD5Tv8JXbqO/vh9NIf28CrGvzK0j7wrWHQyuTVfpMV3hx
JQXXmHFuoJR+9z79veMtfTZD2Qso+/5izaolWgWldybrwb59CMnDA69A3zUbFXXHh3Q7wRJNkb8n
dzs/aoU/6t02y8CtljMxfRk+A/VF2RDjctwkDjW2oCOjy/H60ORZPUw/XTU5mQQK76wluOesX2Kr
RFTZX4l8aC6hBFC+7A8icAjud4li/bM02nZFceY30IPF0VbnVh0RgONgRY2qaWP6sewkfGrzYbiK
cMr0p421UzozkO5zKUNlofwB8/qUYvcZhvyC9mEZmf8VtYt/dxU3y1TYtQmOA1+2x0fl42UB6QOI
BLAdi37xTxFhvlN26J76x1tQcACuzY1xS5bZ1hdO+qyoGXCmc07de65jmzgF4mBjxW6KnrKrh9cm
q2OAnWHd8cUc3ZzSjU3ZA22XP28UiUbwHAPvOE/b3Hi9/5vuyLpyLTRSOx4OYPPsNEvnBWhY/a2W
MHy5dHzGss2jZYCA6Kfk69qZuypOoO2AI8y+YTgwQm2VYRjSpZUEs7oi3r9GOAa+cJQvMyRRu7EX
CkrX7sBL2F+EKme8OmxA9YrYTKCjbeQjTqR8emL9ttBvjACJQmI02EHR1KY5XHxAD84mpMBop9iE
vHjGpn6xHUxH8+bllFnOJX83Cb7RIsPfdkM+vPom2YvnebHPu0Am14+LmYYqFgOz0+DpvDS1vOH0
/GTDr/WMy9ewrkaoL7+ol3vB+8+xfiwAV4XxHBUwHnGCl+D/c+UTOXn+XsOMq2q5PVEterYY2j0C
zvuietBBQaRkNdkGYcN/uVVokkl4aO4RYBVN2ffEmOB5t2NubZJsnPi16Y6ocGpvfr0XQQhbTauL
m8PfpV3ZEhLK3eENXb1qI65bZRJ8XrvBrKyxKufBCUGENso26Q1GYQXwyx20CgINnMkYXX8rUIdx
soKhmrHjqA2hEA+Oh0cOI0d5+ZGNGVqltYr7QwsnzcehgyJ6k7DukI9h8PHUU1EE+IWW725XSDvC
+WJHbn7KNpLKp7CNmAz9QJR2FJiPLdV19HHZ6rk6N9n2XQDXXZKitzJ9KCNH2l/tdkFKyU/j04pf
bWa1w3QDYqEsuiKr1KXlzlnf7+3oPDk/diJiefIg1SLqS8VmvxiwSAgQtJ4HTbHyAckhSon7LOg0
0buIvM7HsYzvkGSgdUz/5LWnXXVzyuBLpOR/pbDtfLsRZfyEFilIJuFWQe2ATisX0FR/6h2IjslS
DrFH3qUN+pZkVPrtnVJoL9Lr1DYUjpdm7hn7z8LR3KEjwLbfGaG9ysDTaGCIYWBfIQWvDS/L1nqB
KJ+hwgPNQlHWwT9DUr+S60QstSOmOYFEiEPGhlw4qborNyTogAjTjSeSF/oK11JQCk+yBBr5qYBc
UUIEvJ0TGUhLRz3LkAC+bEwhgsarFEBXwQQCoz0Kz/WDe/FxUDkZCIk3lkk0Xi4RvwKAjiwe2g98
LFcdekR9Dxx9lAnTm+gcgaP2eLFa9ZY3OpiqWl7lioIcG3wP6DqnDbGwhMEnUaCkb0KBr5dKDQEt
g6QX+sKpQPuj0GdNfv7PSloHsrnQeXQaDAnYwHkhmBh5LfGDVWwXAXRMRvKCzrgJPyB1veDsg6ca
9o+vOLhCExx7ZuBcsf7urPvkWrCdonPbj7vzPFwr5/jTW+7wqYzDHyWy/cwrIL8q8dvL58h3d+Dn
GtGKpjKyi9rdpZcnbVnnI/O8F6ezKJ2NZG5mrIw+Ma6ZNe1z6crsKMehTlk0Iaqft0P5rjS6WZYz
+I3ZNWq9kPYH6BrMmIiRapgUgzP2283WuWqjFwZmldkvjnXPSZCrsFZnt7Nh+SgsTKXY+hrlT7kY
WCLNMWHwcoo0W2MZkLzbZQOLwbjftW9lwsbP2mKCgT4ugXYUF8ndr8PPsp6p+4C0sjUiZK6KnREW
pMW9gfWa5K1kbzu8kBoEAXTBmin+HlTTvp/2CwM6Waet7s0sVoiOuHqsrgkiKOplz0vfQgH7oBTT
+wI6kcBkrLZkW6Jx9wVcVRN5M722lvCjaCXoAAJYz/BeFo4dQ+kGXDjLIZZMzdxVVAx2fxuLAdkE
3J/T6fOLZjsfAjyxGPPBEFb3uFolI8ik8Z7G/p9ry/RwwD78NekkGCsm7cVaeuot+uh8+b6l6ei7
l4s/iUKCvXDI98aGJS8saBbGJ94908hxF0NkpK49z6HWqkS1KXxH+WgIJ2Ruv5kHL2LPaBez5c7t
d1NHQvFNqGb+TtR7yXrWdAWseNwF5IqNMDme6hExO65JkuECCmPPk+zusdfJol5s1QXO4FR047/j
gMSFy/CAZ5rTiPMaurf+rXKsrI5p8p8BUxVjZqa3ue1F2KKuotVC6ynGWa8fELvSUVcIaOnrJaqF
dNpjpoxaptX+EusJW6/V54NmD5L/jhxn/OKuew7EW5FxgJ8aFOeBMlnUh1oS6xrdn03kg++u/KZQ
tl+WFZoyJMKtXPeZBL9xuqyLUe8dXolJFnVNt4S5RdlYv4fAxsdVOonIpqEjYcuFKZ5gXwBACNeO
q8BFN8y9nBLJ4JLgo0mfxntelVZ9mYSCzT8YO44S68heZipbZw83PLAj/4gWYgucrw9mumnDhCdC
+RX8OeYkXyiuPK8+3PzloxOBKbkB1iqkC2L8zNHVQVKEfc/8H/PwSuU8/HsEaCC9iK5SOFhTQ6ly
JO9aMxOT+a8DQbOw9+XBnvIfEbdwAnhFj09kYSA3nm7Sba50SmSyt2eEnMHA4EZvYa2ZfEcd/+kz
wTZoOi6nT0LQCw23J2Aj8QnRIsHf86U6rP+mWoFUKtEmip0XYpcBZSPtRDHUsf5uhvD6mlbh71v2
QB7lk/p5naIwUgiRLjQjk3gGd/xjDoJbAf8Skki7Ww5yopVP3V3ZmDwLsL7F7kZEeeCS5wAg3YQR
3Ziqnp9cUI8MksnwRyCCnAVsM9ul/UvNAHjNYCT+X7q4wIIyB05rOll+Aq3H+f3ELFh8vYb2Ug1p
rpIr7mfQ/U5iWfsWB65rbBfgWxeaUVaX1L6KF3LdZgavyJQBKwKoc+lsINm4BrUXEK29lXVbjzj1
Es6ltiVWudO0TmHXWfAI326q69ubKfEnV/o1Ssqjonxi3u2GBkgoqS1CZPjSYbzqcibm1DHjU+Lu
s3VvO9iVcD+gWI/XkHj7LanF1AFsByeM5bxkUd+RSd+buV5Cbl0bS/dvfuzacjqi74CM97plqWBk
1weGu1H8UgIOGar06V2F+TQ0FLQicUHD+NHNTKfdcGlN9L8pLVL9gyMukbcUAdgiEjZkkRWGs9JG
TGqsEsP7FJ2GRCcDt1I5F1Pu/hhD6m1UwxEa84pRQiT1+WBZCNDctbHJIdBhMZMiF+RrhgnL046h
bejkz2cp0IssfBTP0fO9tatDqYEvPlPYcqhYpd6X4qI3HC/v+GNqjOqwIVlkk+Dw96TNvSBLmiZi
egjVNHW81cEgpQ833zHObXhC5IbcKpSd811bg6Y9fph3dQAKzMVyMQy8NWmqtYPyVAmRSqYFIHXB
qtUjCBMk2wyJuwqwG3yhtb7BCke57q2wrKV5RjuvtyVk6kZZX2wGfqej1wlhEbub3CL/W0csUfOG
2v16RbXBR//PF2RgEjOVwcdcPa/akSBKAsMNIo1lqD0LHTiY+48BdEW8IvWLX9eb0DIuSfM+oTlN
q4FhU/slTApCaZFMqO94xCUEcdYnSCDofMLhZs38vJ04k59LL7jYTZ7Baztm6Wa6upOsCdF8c70O
7FVb1dpvap7p+VPkiL3lkWNaJLX9yDIhGeD//RW8qigfunlsUFJ25gcjkNUlyJC5Wf79AXigWl5v
ekZnA9wv7KT3lEZqC+EQh/R5vhMYQ6gE3c7ny96rjXxEkDnse7DTDjL43PfmT+4y+OK2UT81iK70
Qe0n3I/u19VzK7TSQlisvYn8pNxKYs0FCGVxbVPKpLYV3+/zqZDR9fpZUDf1snIulXSB28m/vArA
nW4hQGBNrUTyms384W0hjkQsioEOrzKkYobWuMmsLfuGUcLC9R9EAG6KEGom3z6pVJ1TSm3sQtRO
jO/T83JO8I8bLGqIPClQFPRElzLXaxoefHb9Buq1ZrdTfSBwC6TJdBao6lkRJFVZm+tBwTMus1id
tavzWnZ9wfwZnuKjFUbz92isuJ/2iBZx26IdLr885vrCijKWOqD4q5r/m1K83L/RVTM4M5QF2aV3
NMHG5lxFK06UM8JSqWYcZh7KVsZv/Z465u6wGMow46Scv+IbCiN3rhevo71jLIge2wLg6mLNDHb/
28IoChEFKBV1rZlNPQxiZp32kNhBVQCX/q6lF9AtB2xygEtIUqTk5rmtkM5/LxR2BFkOfUF4r5ot
uWUIozBYV0mMVuBrY6Ox+avfUEGQ/omYqTipZYZl1NKOVo1mCvK6NOvv/IaGQpq+WGQm50wd8+je
vuD78619UTKABHKq4xjK4LQBDC2Q92Tdtu08rpL+OkQg4a3AaDEeqjLti8D5IWsTzNV3a8Wlcn53
wnnDLK8ZsICVQrjHeQF+Nvo0/bGocg3JF9C9dadgVQ4ChWwprm1HOI8AHVtQUfNaQR/WqS61SgEP
iNejBjZnrZQYNL8EQERR9KYPjIy+lBcIa82utV3b8DBdYOOvrxFrKUq14mJWllPS23Id20hw4G2p
ZE6bxYzVz/J+Eo3Ua0wmdUX/ECW7oD3HCDqChaBYIk/l902G2mnemEHDFdhHgYEJLPjv3AV9gvRy
1l4lV5XRBBDfxtnFqenEg0h5bJf8OnDfWCZokbDi2xWuShkJ1XkEIkwCNNxja6ZL/T0bmCGMBou6
AR447WIzxs22IDzeUzN2RW86wSP+2dw+MMy98VM8ijmTSW1bmSY8lK+bGuqmKMJX7n+jxAMW0LcX
nQFW7T3LHxEJmUJCwlrPB3ojiWEge7swYchGLVbKJkCyfTPR7xgyRnKTs+d4Pi++1ZyvRIh6Y7D2
rJyWCwhZUEZ55Bm67GrByY4pC4LW8NWAv81beugf8sdJS1dWS3NnKdiGawgE5d7ItF8FaBbvV5vM
wrh2GvQytJDPsGTyHeLiNa8S26+CRlcOS8kbBmZewWzLNl10JZDzWEkSpKi1L7yhKTChWq2HZlKP
M/x+u35m6pxxaUNjNpZ0eEtgRzPvyCkV6iauvPKzvoznFbOiE57M/3uIX5mD5lVmTmy47JDywCzP
zxBW7lpCBUrW46HATR1lA50HZt9rDtTDJxfWUdUTQl9BELMqQmaTZChXVGM5STwzQxIJ+vxq5m9r
y+HG64EmKxewe4nGgRsseGOfpPJZjJtr6BdEZh5t2VjlJhnAUMogHmh/SHqDzrR2qwOWnmdPy7TZ
yz+0JaWqxFGHWzBA7SKRl1+3ckwxqOfrM3VLXV/dX4yltInzgzZEssho5//2DS7PfPC1CWdg+4l2
hIYJUEn7AccCudSgY4Twi42QX4QSn5DQ6Vt9anAF1dmBeDnLHiUY1Lrccvy/5UIugi9u25Y9Gx+S
GqQJQ/Ei2qwUHgEX/rtnVFwnU1mMmYX0idrE2iUlbRbGs8+RetEg4DDQLfBoP9Jc0D0kRYeowZDH
OJ64wWEd/TFGX/cMtwotJMEYwL4QsGFdjRID2FwnYL5JUD7aM4ehgJv44Dw1xBxdkqegFpmIFFvO
gFCf4oF4jtz2brrYfWtC25S/l1JZrCeWArIANhzJa17cyueRyDcAtGVdJEgdxG3q2MHfS0rJfTuG
qFYpzMIULxc8vFPmY70eJBhIL8XdE/XskUjeVPKin+c5DME2o0TrQXB+JhRtwo9AxlVKmjaH+Hb1
EgO8HJNVhJNL5vPTbsRDgkUVL7zu0/kRWXH9q9srv8/tksVdSmuc9TFfC061BOjbPtXBzt49qR+W
rmSekZizxJfZqZXpmLQt3wYvFx1qhzgdoZMmM+p/7OGYJLiS7+dx2xV4o3OG7j8ypNfdjXoZJzaI
6KlhVczSfsQX6TvQpGfozL/8SyS2UcKDgNoFKsqndA1n6SJ4EC0yimoc+pBhs6alzhOgadhQCAXS
MkntzIWoR/vyg8pgKNplPuOlPWUvaoMx3sRTqJ3RuQdD+YQlq8Rf6OUSakQYLnktwUlkWzTOpd6N
dT2oTAiVOVxroSEGf6qr7s/FH3u/B5urEBvQ+/p0gbbLQyvI97njs6E1eplcBA/4bNJuIW+At/Eb
x/fVY4vFu4HL6qET9qbqj0mg3o/JDjCGGTNchxbiNV7gxe8MNz8YOjzWwY5GNlL0eUo5g7fAyKGt
pDnu7AhPECN2qqTqV+QRHFW2WqgMPy+LU49ZqZsf8In94sXbs/LzVPBcX8HBSZGo/goFSPZTUWV+
pQk8ZX3eB2WggoRuksDTYnk6D9CWqTfomZCI6vywHnIytEPzsEbxFi7/ot5X87Bqj2rVtDePu7g7
T5rau5FlX4i3dSqjSI1yEf/QefQsHmAskVb6mDjPt+aeTutM8ZeMagxXyW9AudYTBxk0eS2WiMi4
NywMzZo3lUq/2MVwhsTGbOTFWAzqDTpvlh8/wjZ81dgA7SDTirJPPyA3QLgWbeo9q0aMEPG/qApW
sjoVkU63NDV/oyRN/Cm8H772r13qYDpAEtlR181BWIR3jdgKx4noeOxGRuINS6gCl9V2Xu3xRHe0
4VfpVKKi8ZtF/mOV9UCQtCN8MD4WY1uipYAXVmIN8T3U2sLvxu3xM6x+ToiPossffNp/Ss8gm0+V
VlcOhe7dwMN3W95qJD+G40mzPN8PcM1k0glxpQ34NKb0a0H8cCR2oAKB9zO29+j7iKmfoKnJkQuw
MBJOLfc2HtZBn0io14OR6hY5qmOTpu9TrvF6/N9Lb/cCH4NaXlleMrJN8pbGu294dLAvbrrEEbtI
4mqtfSyGe/ca6l7nDlqe2TwBo/pIpUQohAZjn33en3OoQ/PGAxLGhbZs1zAq58Uumtj2/1flLmab
UYUMhS2rYKJGv8X6ROa3hxTxWbDFcvUk57i9i1MOvK6zOKhYrpiGUO/51pVeMt91xhK3PmSut++Z
NUH35T7CQHlmtRbdxCDzcmkYKkuIu8CgT1fNR/z60jIjY0LHHoyBA+G8Un9LM4MN/wzRLoTy84dp
PcR1vqPdgWUs/CoAII3CLG0qNAqz02fi7kDvGDsfEfYF9724T7p+j0JUQC0oRxCyrWlTtS8KZLoA
6PTU0aLd3QkHosZLgRsHPixfz7pxyeSLb9EHj/H2pM28/ANptOnA6R3jmzLQKYNg3wP7bcYFETZc
Am2r7ZHHAevdSMEtccCJpwpK2+/B1X4SfEZCBXbsgDhihYQkBLjx+nNj+N2fjROQqKoQlWHUl/q9
0i8G9SjKP3UtzbGueKrkXPNCGI9jolLwnAu49t0urwfoJoFl2xgwXT71y+d2UYaD4wudHIu/alwT
wFNSQ1Lb5b3vYuyWB5KZH39hGLfHifBLuXn9uF2ep0uhHGeyecUe/EAfzcgRLzTCpFUcGJHFU0V7
k/CLvnVq784nbsfD6Mkt6ju8RLMPSacZsDrxU/z60WfhnMt3Gg9H+AfbcMpUH58gXXHDn/r5Zx53
Zw/v16E/QX/WptYoy12DBnshqeDm5Liyy7zapS7IzeLG0nOEI5J+nED4EPQzUd6nKjPHnRJJAYoN
9gJyRNDHy3FOPQU9MUqAs/aRcTXIcYue13ZcMh6t1PyWiXVwwsYfkdiwUpoRZzV73S1h3hnTkjxz
hiInfkyDIhtUeTjum0s2HGK5xS4b2hj6I2cxwBJXmXCRd2GrN4YATC2N+l7b4MlPgRgd41Ve0/Tt
Mza1M5aeWb34e8bajYzRUVgDRvKxn5m4gQogQdgaHnTTMMKKmapahhxSxyweacm8OWrk8BX700Zr
Gnp3K8MAow3fQ9yjEzzh6N+pnTc97B7NLXmTerreD/nbEb8dzVLOcePUUMK6YwE66RLS82ha4uXl
iX406HAGV9PKk7AZm8m2Kbr4cCWmU6DP1Q8+u3O+0zuDQnT69itQia26uoY753mbU/BbPmJzUNte
F001s8KYg/14dHuhCNSJNCpKn8nJLOP7K0vbQLkP9glfLZyVevJNW9QrCYQykpDFYbsWafhH3KIx
AE0QAvDG+YpqK2jpdB5WPZO4SkNRppqqQZM0+kOlUJxjIHR+Mx4IqknmJrLyScVJgz/BDKRvAjmi
1ciunrMr0E+L7ReuBaNY/33/AJ43LO7d3WJjyJuYksWBVcDVjZWHrJtewKzBhYVyPg+jJ37NNgIH
mJZvd0OGDmHaBGhIX3HVKnHZchGvddIlRL3hGU9CE336M069NjmUGG24IAYuBKo/ntVkiRMKjzrL
o04O8CEKMcAoP8A9F50p1efxnL2nH0Z5ffgwK9BlCvXViEar2iigFaCYp0HH2DHw/L7te+9s8lQb
XDEA1MaDRuNFWOherFDK54Er0AX1b+1P10NBzdxVszPGCtHhmJ/vTKKgu2CAIKEWYziipINgAmZg
ItER7b/6SasKGJuLA4MhV2BEy8uyHH4GdXyXoHvULP9wCW1u5X+R1mSFRybVnFDq9xDmXQaRpDw2
OaUTKsWdZdWPtQM2ADaZL58BGQp/iizRuA7agcXL8sl5DxywYtkTY38KxsIoM8P8oKb+UZHpO5HB
6/mou3A92oNgaWLM2PlHWZRsjHB2IbrGRT8ZSVmsud7fMj2KSJo7a9EK/OL4+OurJUftM06pzQEv
5wwUiMjyk5ORjiut/DrVEwhOfHJiJqDTEvWYjxCPKoOV9BhUCOnT9DHIKX5KepgWuB4K8++JaXrG
is++auctD3qBFg//7JI8TqxKk4G9RRX/sHLdsnzfV5dAQKHxDeSY6+rpufCxNTU5ooMeSzd9oDj7
8NMiTyxHh1zusLc8RTI3JriXaIThLepnmY5Kqz52EWEQ1WCDbM8KSxLtL6I7TL6KahWhcN9cbG3/
12TtYFkreVu6vKQRFqUlyACfC2z/onw4yt2xanvsNw6VD6Qaczf1rv4XKHb1mrMbUAUwDfj6pKL7
IQqrnojOdC6ZTWCN4K+skeWJhVCIVhCw5lRrjKQtg6AolYXI1SYTI16W+F7j7FJ31D/n6OcPl2un
u8SiM8JrzX6Igv4CvnRVJn/63pdjzRFMLLc3fAww4dxh3BBGXzY3M9MEKdjR3uEyUK+LSq+P3ftO
90Zc/DZ0ntwSR6jJwCVkvqnzjMlzVvCgLrHUWtCpQiTp6Iv7TC9PtQGDM4gRj95wu2OmTCwsOxzY
fDc0c8Hl4mwFUmmW84A0FeIoyi3/w5ZP0/bTPv48iJgtpPvMhAFxnrAk2eu4nLh0DlS3/MXlMTD1
Gj3ZKRJN+yalbwEpAeJ4zr+HUcGPld1Quz4pJEcc4lu5B4YlWLsL7pXscoYLLk46TRr9WViIl1XB
whwoWJNnlVk82t3AtkYWfmkxo1QUoq/GqXTiCgok2vl0Bb7xEwdVFWxw568YX51q84Clg93dXIyj
JITWUFowStq/EyJaNnOjtgpH2oWzagPBR9EIOi3C2UnkGlVp2iNLY5K0hjWnm5Bj191MGl4Iq7n4
ROzPTx69gs6XFWhddbBGwwH0jPlLgz1V6zmYQLuNpiLQ2LSNAJZX/usPdGQUCnVsGpsJzYCzCA9T
IROjrCUTfGcQtnsKq8xjUMGNt3D+TD3777Ug9VapE94icMH2cZTMXpoH1hQ4Pvj1sLuWAraF7xxv
HZy0uuQ/vHrN1AqrXigwhzqS01jtxfZRwZv0s2jgSyb/cWvgY7hAM2Je3QD7bultNsC6ZlPU9T+Q
VbH3YknTuSb3UPzpkKOqFyusU4+CMtnfTp4XNAWZKcsIO9k6/FldKAmvmXlEsJvYJTT3y8iJrVs1
eppDG3+EwSWL4ouKCYAL11cw0zhzM+FHc9poO7W306ooe/NKe1gsVh4r0ZxE5v+z38rJoj0y4PnX
GKh3eWOt832/kuH/ppm/CYlS0ZF5Yek+y3AdLxAqQQwm7MpbCiWBbVTAdyzBSufOI6uP6i+Xd+ix
sq8rsRzWMqCHCr6Q+8GW/KHy0EqRYYY3tXRy1ubeHQtZZpS2yIyYFMAYRNUrxp6OrlRffr3LGy3b
qoSMBYSOoUuDxnVtSmI//LNf0xDw0Db4LZKuhQRF1lkVCmahwspK2A7uxlHa5nNqyx+tH3X04am6
MLfa4N4fBxcCajOSZqveJhay2ATV3NTULy8ujkC8pHoprfOqn+JGVFtuh/q1SDYI3IQi6ZnAhZtl
djiEpHMOvfo9xJlPVGVkWiGDb3jXz1j1+s0kFmTo0/PzJNRKm9W0gigkNfmRjChAX89BNMO19K/v
QqtvlsxbfBXUwC5/5N8PZL9cxfRuJhpQ/cVuc8qh3FZaw6uLEZyGS6NkhEsDTxCNSZO8/lD+EOgD
qwV+DPcQzHqv5QmyJzhTk1FARLDEC/IjlC72n6tPNu/iDrFBeiy+WQjQnzFlUurlEPExxPMuSVdQ
BBAy3lv5UKfp9Xfp9BOq1EZojFWJy6rie8rptybRk7jhVtDovL8cIUrUpGr3mlxJxDp0dQb5kmlf
dS1l7hzTnhFI+B8KzsIVWiD3ZsJpXwuc7GfvsyGXrigu9nCETFk+jLHJKHQX/9V9XFEufJC+B4km
Qx0jAy1Jpcigre7ZLAWlp13CBnzamA5bCaMj3WV3LZSdQPdi8BR2FEsakLOQOmUmTvQrRsRiCKeT
ZppdZFOSqNqM6tl9f/lDMDsuQwgLHlJEhMSyDwu4xDrcb9LLZ7c0MgmilM8X3Oi7zVPSK/HxMxxa
bNxGbQUz3nQvX/mhl7LmvUUfJHPFN4A1sY/S40yQrxUDlOYgvfvcTtEq1v4fwU9yleqNW9jgQLmb
DnDD8zKqT7WgNNOMe4NiUiLe+0ZzRjCBWMW4B2XxbrKz/1Au/+qJgSJ7/v62xkXdaVXgpoR3YqU3
WLkJsasTOhposv5kUW8fL/VJdho01yow3SZBU8fXQ0u6VZzItI2yb12pgTaTW1bqPKA0zfoVPNTi
YYlK5zS533W/X1aiHY2E7T9edrkXuSMN7PSrc5g/nlRCnVyx8TRefAkucCbscSrCd9+oObjRYq3o
lIHtgPXpkQ1Nj9ts/d4UQqIyL7NbiX0bjJiwS3wOd9XekbDxwYrzOBA8oXg+Rf7dhFL4P6udscr+
/uBllyqz73TWPhMhm0XJRyTzwXfnjdF2Sgk6iR+ubJL9jtZaKFyxvxWeRz28NxK9KCCosx1jL3NZ
FuNtw9xvdg4lLwOvGGcE1S+Y8m5Lp7i+2Lu3mQKlyGD5QaEsor1t9DX0VnhKGmnBfG2no3C8NzrK
YuR5ZInt4ToV3shvAWNxNvvEBALsiCGAF+xSTCQp3Xzl03zE7I/jdOfqH0GinphMXAnoaR4wQUi/
05pCcw8V6ntE7ntwK07Ax/HBPlKomcIAaAaMt+fobXk8ljCVzuvlGk7VussFJnsL8HAEKyIlh5yI
i2f9DfX0GGSvGEt+uRpGEh3jkwDxs7BqM4sKEmmM2iUtaensohS7v3bnTYZ68+AJKNvh7CFU2NTW
C3VCJ0ZcwxlQzZVdoTQMOTpwaeaySmJ9wa3AO9pcUCvNUz9nChHhnq8BYBtiFW9klgwxbdXa09VY
X0IHAZC9LqRvfkD1nFjrPRRYq7LjCZm/3M7mWKpZGx5L6BMuhsHTHdiQ4EmiJfAI6ePwnE28jBV8
EG8AfBcc6eklJARi6fhPduWRy3b4UdgOT9dkWTsZZzTY19PDFEIxUiJzKKbjwQ+LHT+qSQZ3HXAp
FQq0sfqLpUcLYgPaVrMg/G1kDl15QxQ3dQTZ5TWpRuhcO374sXEs2OHy+Ryko8cZyLFhT7Qy9STN
wFPyyTDvrKq1Fdytbk5yuniMutl42HkvHlNmDotdETn4X9MRBu3SinTwCNycY+iVH+FlxWOvBAog
l6hx3lBcav4iD5SbKNafZGWw82/O7fztUJQxPzeVWyINaX+VLf9Nf/fJ9BDDPp4M1AfjSjC9m9vL
ylRsyFtEk7vVKjyqM6li9B20BvlixdVXMwQmcW/NGMZ9nmJLB4sYngHp46JM8MJtdw02uyLS8hE+
bc57MsqT6Qd1J+WRndj9LHeMxh4xSQmOqPh17TwpRCBv36TAGwMxq21RNoMBkJ6Wbuky+RFlYPE/
qHp7dV5pfrgeZXOzSbz50UHDp4l3/bCpL14H7BcXkaW0LEQW6Nn6dYmtQDiuInJErWrlYnyaHgLh
0kdPEDG4yuiTepBcOU47yLrxGTkCwCD4/C953tIAhGN+IG+p2+fZ9DBAz7uKwf+Y3hhRnNZmGR42
YsCjQ9a1NcpQogZV51SJ+Q5G6DCZVxQC4AEKl1Ajey154aWgyZde8Ot+mVmCcy6SqyCAUushClfw
pRDK8yVQTy88HQciIgufmRNJxQ5zcCEsFyTkg0bU74SG8MNwOgCJubXmPksleQX9KpO6ZkNaPVQq
W19srqKp983ak0Me6Qt4xGmIOq1cTRAgbRy87/nKVyrJ5x1dDie9GBH7WA/obWomCNwtmsiuU/Zx
cv4N6LyvDE7Hei0f6gXjxkmmPOxtT1qFraeZka8W0bJBO69m+Fx9aN/nrtAHevaDIWiapxmc9JFp
Zd3cUmLnF8/wrrKwvPkAPfoA/YuBX6wfBuNQ7xsXf3nEoaFmOvmZLGU5/msNsdD5Fjxe+K79AUbr
gnsSHJiKEWX2KfdXIvMeS1Q3o9FFAHR+LUao7WunDC6ASsq04wXAHAmlDHxQsnc83XHE2vNkGL2A
7PjWC30VZFHOQYJ2Elb/RbU3mLvf7nhvI15MoMQNng+Dg2U55B2dVUZog1tdtoGzmKXWm1SE/WtV
SwX5Fmmi6zYKXl4CDZLstFvS4PvrWctZS7YYAT58NtUd5m+rkcP43td7JKBxBhoduU+AKccDiyXj
5UAKYQQu0j6xxu/qAqYoBctXCO76dnGGGXAlNd3qgYF8OMrTIAd7UlAGtEN62w5bxg4S3GM0qkB8
ghYEsKG6INswWcirBk+MOQYMimoFMQEKhFCzACSEGFr57LI9GFvpMGP0pdINRgt4mD85sFrSqRR1
Mbyn0oTNAcomSQwD0khOrOLGGCqB9+7MkbEOy/8Hai6IslC8dIZmXP3fdNpzN15CSNiRzM2UI6fD
UBH/E7X/baRHnhoCUuIF1nHnv9GOE+2IgHvIzpqIgVkpkpO5okeTnzJ51KNwBW2ba8FBogALrfki
ctgYCrPfkb3i4cWzsUnIDEnB8fkgxpBA08wu4SIfZu1QKQ3glE5g2WMxNx2B373gXWBgwyvaS4t+
29D9LbN8RaMi0AA9EB++K6XCBG8hDCnBnGe31SSnDg9QtbwASmzSIxBpfgIz7q2Y5DR91OZ6x8WD
pZ6j7d6puZWxENRXhHhk6OiaPq9y5HPa3NNNYCsMZa5J8G/GEjQf5DxuP9BVZBRTktL4EZwkkADW
T1/eskADjPAUmQVAds3HAcwJ6fpGZiRVGxUyyl8jPV3n6smA1r0cMnUz++dVHxUBMg0TMEempSdm
eB7fJds4c9FvojneLHljbgtFs6fHTpfbRadGu6tEUtzptTs+f148zmp4Afzs89w0FYFYskB9PAUp
xs3IRtHrGngFH/ytHvpQf30GSbO/6W2jLQ1xvQH5HKgZ6tW9FVmwvS2KKdP7h3rOb0GF3DmTrpWw
ehHPhfjQBWBtO134i/j0P0Utd9sKuuUpBAk2ScJ2r6TeoNB11yuzX8ND2aCzCq/5ZGWDCOU+HYXQ
ZxKAHDNJEayJuIIlPgr/EYcm7beMxSF66NyUbG9hE1/g4uAv//ZxAmTgHt0+OjGB+USwMKWZHE1D
12K3ClsE2jWa8c2lvCb9x0JhX8AnbQUXKwh2FEHYDxKTMhC+XdcjEtyO+ME4oaCDnbaqx9eoakXr
nKOphyGN9OLvJT8qk7Nnkm81dlxUgUXopHsmhstCeOv3l9s9xabByo6TcAo0HgKnM+xg6Kv5X2Zb
11MoCLSVu57OeFTdSz9I/v2kjhkKR3ok170FVoUEoybpFbbB062QSm+92EyMYynQ0BMs6nwWRHxF
sv4LUP20QRTWkOX2pmIySDa1CJJRojTTYXNc/tHclsD7dgoaHtgLhDmRo/QtlnfCBmmX/KO0UJrK
eyuvgBObmCLCGTnPHcLGWHskqZtRtYKsS3vxaTK+/sxSd3qWYzHSEYOdltkD/HWG8Yj5e89aaz3H
4kIMEhB5bIQsjz+ZFYSu0GbREKleDZygeyPTmvmcXWNcRFPXWosQZ7zR/uWY9pCbhDg6TeU7dcEL
uLkkPAOSBw/WSXryy0r0J1PUWANSdjrhfYbHYVgdB+3wOnOfZsH3Cc2EVZ8bjg8EoOLkLzU/WZbE
FKeKlZjCuXWRuX3V9TTTntVQm9HILepKvqyEWCt1sNbeKBth6xHuQzqe1RL7HTGJjHDFqIEYx4kG
+bBiJZgW+KHpvvGjL+4LSMlJ/KwNw/6WnEi27Y7TskQlbAvb21fqKamhml2r0pLCj8u+Sk0rBjkl
MHo7/wHzJszroJD2kxls8e5KPOPIN3A/gHJFjOrs0GIK/3WFfcrU7wqK6TaVMtl1w8Ww+6UErMJs
iWqt+6dowVUwbf3v3382JVXJLk0h/VHhGP55fwq4z54nqLKvgzzx7vOIqvw8uXU/noEj4mIM+ZYK
B8Ac8FHnzGjbuLAu22wsGQMjAKVKU3VTlbVlUHNO9S/RT2P4Q15BAHXFF3Ov8c7yPu0rLFlbmVkR
XbKBS0mZD0M2RZZ0CSBECzUtnRrNSvjUld5L7Z7tbj+Xd/y/4OKOdzGj1PjjULY7UFIyK1eyu/3/
oGyGJdVV4mMR5VXAD0nvrtU7K2zFl1PexEprzl5M+MtIoGyPHS0hEflWLtdW8YuHEMePspgk44Sw
aVOmHlzXbeAJF/IADEfxM5wPiAfCe/svayhc+HxdS1qw/7C8trEheOiJ0HBFoq4gvszzmoXixT7p
Vin3Lk0Xwd/qs5kFQQJJTCDu4VAhAgeoEMR+pZxdhLlwb4DEbyDo45MAdXm8W8aHAdWuxG+gNZIe
JSHupJc/4q49JALBqTSgmvK9Vg4nZ4hi2VnVneiOJLVwBEr+vdTCZmi9CAELOZOevUVeTXHWtKjQ
rJuSgpEpmJRsbsCd88skhDsxtm+zMwphfbf/ZKiH9sEHof391txOwOMlBrJR/hHrRUyMKJe+7D4z
KTtoONMJuZPUd3xbw+xEBxOiLEjqfEuuQubRH1M2FEyKwTJgsiljmj/4bUPkOdgevaTRF73D00In
ONIY4h95PMn1nxOKlYp1v0EdzPCHfdA/YErEUB2+v6897Ek/u+Yv6xAuiXU0DxnrYzFr9Mp7MPdQ
nhCK2Y20zMTd1G2sri1yAxPbPEN7dnLnyP66orKGtJ9GpqUK7SSpEevELot1j0si8lTxsUKmldIW
09qfnJQmQg1J4Oc6/GX0ekh3e7mNvkJVtlzn2BSp3Evu/2Lyh1ikAJZXocbaIP5ahbWuVY8KDjxM
uHJvsh0rxaFAMrGSqA5ry0ixhnSvgw2z8LXZXMGnU7lI7Op51fknEmy8RTk9Gz6hWCDJHCKZN3sw
J4NmL4gsxViA09x0oGPiOl54yDELv69LnjxKwJ0k3BdsmmCiyHSqpIWvobs3vCsTxHszzlXFCh9U
B+B961TmYgcNok/yKyY87qK/xWOqMYTbFN9tz1MdBMnmw0owuIMiz/TFXxDrHXtu7+YyzPP0ni3B
igSKZfyYrevkWbtoqXE5mMKbJyE1PKmBRtB+JTksDiHgXcdun6DGfbOG2uAYM8IqTMcUuJDpEjh9
iiNMwK+CAsnRIFrS2+CNIhz0e6PfvFhojSB50t9f4V9RTfEsXl6hO4XVtn/R8S7ezPJh7+Qio6om
cSVROvZL5109R6TDq4FeAKdmNWk+im43GRV0wO0l84r9ce9UlSVeR/1GBys4/Fa5Xpa+VOEN85fU
Czqm6VzoGqnDLdRk0owlmTGBrG1SH1kSVrmBkvmuosecEW46py0IuC9mGuzocfMskLoEz22aMh7I
L8NPf+97VPZ1PflNSAiSkPxWFYpTraN7mErDz8XpPnXHHIOKwCAUsth9i2FHFFN3zQsXNKjEm98e
PPmc39FXD25q+CSFBlc/hLv3EtM8tsP13m0v7lAjm8+sVSn7O/EbqeoZmBpTZaNvvQpBA3W9Laqu
yYnpMKdce6sJp1zcwTDKI0tAZE7hJzQqTIx7xt5G7BIblDKiF7T/yGzfNi9JrXmS69lxu2xsSMs+
AQyl55h1xI4i7GLhg2PFED4CvlU8o1jl7y81y/XpK2sUIL2BnWyvGc6Ad2wWnL8BdhsHHH2zW3Ba
Tnx/Ycj2f5S4cgClIxwLtpaNEP+uEMG2aS+/1ZhNB1QIQdzu/CBj9XGmLGbIc+zyQ+MUL5wNiA0Q
uvv06lsIN/USLuyX3TSy9bFIg9Jd+HzLtyI9d9dAgQw+5qiraLZoQJBLxxX89A+WHyCoIEa8tzQ2
d9KWgo9u0Jti5H8LEqPsZZDqcDM+nHuFNYK+uv+IJCV4RtRAkaAQueHpgavz0Cepd+3mwVRtulq5
P3BrQ3RWEmsq0cfwJQwbkX2jL+0eMiy5LsAOhHeQqLOThiGUo/V/rzLIFovRFs8ra3UgV3uI/VOC
XkhnnFkUaKJKLgyiAUv/bm+/PHZxjQAQNdvltZ2ZJAAE4l26ZwNci6VQ7yDJZHxbcSjuccAmwzIT
XZE193Tuq1SoYnM=
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
lcLEUhFl0x6q4c8Lsuly3In5vNp7gT1QOB2xNiyV2VJn7oh99l7ssPfFXx9Sj3m4iLjHRcAzWQg0
M6s2ArG2IA==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
aDVERq09vEpxux9KNNAFDiM5twDtcHRqDCuY6TKCwN0uWbq2XDrrlgycu0NMBMzWbARtM2ZGlu8n
1cdDQu0fel3PN9Yxe4/8X+rEd70BOMJqMd/OEHJkjr6fSSM9r6uvVKp/jMbzXaQBn8/iExJi/fGC
qJ0nIvxkAH8ee4Y4/bg=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
MbYkAAana0SpOy4UsxBYugLLK9hbWDYI98nge/kX28U3t4CelLt2a7tfyzpWZQ9pWw5fznlnjFwO
6WjZHnecZtyX2UMT6tpI5EJmp5RXP4GBFOBuMzsXhOaGtaU3KnJqAxoTASlUBSjMj1/6Bpa20atX
npP1N3gRxaq30LjdKpeoNeBu1Ywqbdn8qTOmeZNPJeuzVZVg44H8WRcsQhP+OOqzRg4jMEwLvaTu
Ry8kSCmbfCz1aHWxX41bN3OYaCYCvI/A1K+KgLdy9yaQwelVBzn6nNPNcHItrvK/+4Bjl4AD6XzG
oNl3Bbv+5PCie3jh1KG//HuAnO0uB9DtVxi26w==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
NXUBIAP47OfKxZvMP2Q06k0ee1gmVxRcRsGIkHhFg7nlh2rEyCDI4CpRXWXyyH5sGCHBiuQCFfJG
eEvNf0/GG3Nj6i8tlvOVUzcEZBSzeVr5jbQEEwbW3jBsC8IcSrB0oO0ZqSPFhM1Mkm58f+NCZgu8
ixyxiavqojX3GcWkSgM=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
ZI9Lv/AWBd3rJBNjrkXPQiJtuq8f/eiiYTRPSjHQ7aNutFyEc5rS4/IdTSr7PoF1z/ZHpwJX4gd9
9SirllPHnmI8Ve7l/yLRPEirw5KyD2r0iIUs6/g4DarvtSpVzgb2Pjj5kZMDbXENZ1DWKdPLiMw3
U4rS9j2KVzFDAGMpBqfARpFJeEkj1pln+GOWI1i1JP4MGQc2BM7z22wO3PoD5cj46BfQRSBoAmSF
F4zyLL7ojGVOjRrIk1D+jGBs0T+YD/NpLxMTrjC9x5OE77JQezrEHDEhxmTrcW2f4BFkURqiZinD
LXw1yqlg+7ULZTfMlxhc69BpHbLmNlKnwtDoLg==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 280736)
`protect data_block
j89sMXCR+thMssXjetOozjSiNHC1jWgf3DoSfTNMg6gP+dtad8uiiAbZhkz9Cn9USHOwQz4M1qFz
QCsi8UW8KEzEtPsD0e3O/BBcYfJ3dt+8zj4EmjeLjXSPSSL2jgskEIVE0n3xdlI+Z0lWdM4K2ImD
D3vFvyQGIXRPT6hctU2nt0tJjFb95MBvvHQl6sdAg2BwXpy+Qj/v59ywbXSOQuZvZDNY7ZNfHx6W
LqfzW0xQ0NPcZ2tNMw2fDysI/jQAoJa6ZHFVQoBZdSzKisvSrsXWDImFd9Upgq6WjIWkPxzN0dD+
Y28haqDTLoPSDI4V8uOqsHgMMn44eFxZ1GjQGrFizC2Nb7Z1+5OOo5m9uCmXehRu3rrEWF9EoGgW
GSZQHLAaWGxyTmcGEUujencvOeUClNmxLI4pSIPOJ8WZCSjSNezG8guFJKe8GkHJIxFSRZjhIbpi
T4pbtk2Ujvlq62ce3KOzg9PAqj+u2hbGD91xo+CCM4Wi8BaU96XuVVYSXUs4j1m9NhotkaFgCzwR
J4sSJbHi9sZDeAI6mG2X0kaHy72dOpWmQ+Lm+bYVefzctK5jKDFLlu5ID2Iyn0wVdFazIkzTmd9b
+EePV9cWzxZsc1QLDW08Ec6IQlAzukEFgGAdu+lkI4g/CHZWO0Sp4cDkYkYeOD5bk0J9j+5oFfyU
rnEr7wtKk+yAYit5PZ1tZooGDr6s+ZkXM89mqO7Y0oeKw2HtcqRDY1bLkHjSJApXB2ntRugw5Ahn
M5CvbvDu3FL66Vm+PvgwFcvm/d+d0Ft+brlQMbsb8VyADcrybZzg8L5yzwX4RfN49A9+OhyJyjUU
Nx9vlscMTu4R736qzt37J2DulqTJyp/UudgO3rH1EgKJOCa79H1wUFP9OptIXBQGhCfJlgKV0uYS
mbVOIPkRdTFkrKeC1i/UMi0N1GUfjDg77yRVsp2JPf823f9HTYJcI/4O7g/K+8NZz0vTAWyZpAxZ
b/lh+0klXXO3UYxKqNHQg3pzCCqOz+ci8+7SsXFTmXf68fnbRoBWd4CtZtzirQVJxlMtsYpbC7Yi
39mYZDsHWUWBXqqwLbdBnrbCO8U8fgNOKJF1TkiwQThxdmwrdnv1s45PNVTYkSfYGAcP3ehzQ2sV
AB3GdWRuukA8sVZkT4jhDUyv1yt/OFzRDpGLIAfaZk5vEDF8ymf6VgQXaj97LvpVuxKeGLEUYgwX
7ED+zeDjNqatrmyf2IdQhd5plakGLL8ND0tWY/pZqNEvl6PR6ZASPgtUc+pnWcSRkUISscebnUk6
5j2bt6M/lWAjxNFyPqGajU7CH7GBQaCnmqPLK5K6s0sSjcD6R4cQ1XqOmyeRjh1aCW6u4iyif7Is
SmdE8OLpszOJdfu6Pwd5Ts05jO6GYyeX35+2vOm4j/2PJ2tFTVWOo7v6fB3j3s77X7LTC3FLFsmf
+L1KawwJYzaLDDjeBXjq80n/5V7Yg7oDlDXg8ANGSfVmFRBqzv1aoBJj5X92Ddi8+nKML9fmQOZt
3W30UONBJLTMzHBti07YJsMmfDdW92HxrlqaW7IACFbymMaJ0KHyuDqzS6SJQxd2xoVysUrpDhcB
tBGXAIz1pvehdvn3n8CL0Orl3mAgOr6XTdb2SbLy3Ib6xjVy3fidf8rUQLNz2Vdz7uq0JewI3zA1
N70LXEz+A9WWmBT0p1/Ikx4l0dv8xs3HY+kHhEozC1/S5smxDMsuN/tqXbhGDJHA+N5X20/xdKOW
JpD1fToY3QjLZ8IktpxOIxI9g2Tfz8cs4ZIchFPkkjtsBTIHdp0Hj4gqF4x5VqNcveepoD8yiRlk
pXnbmTTAOlFegTQdAsHW9gudE8nJdN3Lxl+aurIb0gKc7Mrqmxk9NX2epqoFk3Rc/HaUbOWoyw0o
dzX4+L/4kU9+Pm3kK5j+wxhzvSmabIS2k/WrISlPMUr9wzwl6eV0Vb6z4wzHGLjnUChMIPH2nOPZ
XVALl+0VyodaPwY6d8c+K86iGbq7h9/RzAvZEqLgmYXkGTD9raXd3R6Yy/BD7EAbN1aktNYr/Bn0
v5AqzzuIF7piBsI5neNQ+xHnPSQxxxAyXTpMyv3FbEp0fzpP9GUtIlzC4JPWqYRXYQA73QTpslwQ
QFouo6dgRG84+Q7pDmkMcJeLbbYNJdDg+ZZiyKBxEULNemqDi7HOEPeVZcvcQl2rJuYCNI635I50
BiJcw1r5ycOjRIaemgx2iVe7IxM5sZcujcAo3WmNIq+w/GmAGkWW4UjAGYFCvb0+sNTSmvBJ/Akv
GeOdNrCsgwBHMbNQeB9NvhrHR691DfD84GopL3H6fYCKOiq8A4+3CAFkNi80EpnTj6ReEbZPPo63
mJ+wbwpSJfObFqBkAycJPxpvVRwaySGYHOyK3rzeLiJPSOQtfHsTAu1TI8WYnJJr7fydAOlpy5lo
Z5wMrwSVq+SfilvYKD8DaPfYBPQUEGybtSVv9thaDhR44ihg3am1BPjUgCDEU/vSouFxabt+UfWW
CwDetxxvEd9hiVWo7pdTpIyhz+XtxaIzvyPIZxwdtBtXrVcZsuedreEA5yzwhb77gRJnd50VboF0
TCyoiWNAO+MXaGAVQHL4i91hDf6NH7or3zvfCuz2/XHRkiO5GM8KF+7CZidTOMYfDNPX36iHJ44u
12GdV5H8qhgmASThH6OOBSOwZAYiXLfS0JdR7Fj4Yrxeie61ETmJ7OdvjnJ6cX7lOzZq5VknzcaU
MHE8w2OqFd+l4b+vmI0/xVkWTTpoFt9MWIO01bVjLWtuAf8xJtFWEzbA8AtFSXAcxwYiEz4Butif
yRHVWLE2IS9nuMap1l3KQxhoBCvLl0LexQ6TMZ+TTUMH19rD7io4GZz3cpoe/sTP+9JSHQEzJbU8
qvN3NbuCXqRp151hP9/dEDfnDJe3rA1yCxBL5uye/4QYMk5NgRjHGoLWd8xvquzzq7p2HuWGPABc
+86yVsjri6LmmBe/1NddKHOOI+F/V5Kq+ONLgjJrbeeWmjSXClm0iZZ2LS3StfojByZXxDqoPD70
mzlsCZBjkqPW7fjWpDiEudMNlUoCkU0MvGb5UA94k45xkUnGoEttDrjbaoEiTX/uODwBfrFs3aLM
hKms86mdQcM00cxxO5CqyUwkUEt2JefSMPHiNi+snAAkeBdrlwWPS4r+viX/Q4vcBIXLlvSdMQ4E
OL2uyxK6O3jqwQnmjFBC6afR8m2C0lx3Y5r6vYas/QZMUFGh1QVn52nE+1OQ5N6sqvOSTUrxSYEB
7KhsV8V7URM9robWBVBSRUfgC72T1ucsgB6oYpGjnGHX2wl8qfRGvS66jGWX1fFenSCQpP/r4zN7
BH1drKjmFB7fDeyzesHNBDTRvX6aiMx+qUd7o0V/B8rB3w69HTeAi6hK4NEjd6X3t77oG//+sX1a
3DMzdc73avVq1o3cNO+WGn3mDIXFxbgrsQ3nuLu20ZsjA/+Z8i/7FxAP330sDM6mQh63yZC9o3wA
UhbS+Dn1UIC2ixQPFM1j2tpMwVZ1cwoA8raWsPa1Rbdtjn62tAXu87Emwnkfa0Cm5cyMvuHa7rgy
Z/nFVm/JfqW8dA582o6lhpPJ2qVO1cr3oExjwn4z9MSttGDrYlVklV4twN87t+IvqGfnk8GoJHnY
yNDkRhFJkw7ubWDgjKVKQSHR1xHwp6dWqFJN2z/W3jBJ/LlrEHvpsj3xuc9OXHeJbOfI+QYByOXh
a1FVUAXLHhofrjhsFdKn9E5kRaxLM1eba1QWFR3clH/maBAh5scNgatAda4lJo7EJnJ4+gZkoDb6
soxq1gDgFXwRiSReLoFZAPiwX1FPpScuxCTLFcySQM7pXJsv8PE/yYtxACe51Ndpf3l/KdbETJqL
xn4JOS5slqy+t7zyBQVt3CZbQYiqtu/S7stNOvlkNp3mTHGAW7pBMjbR7a4SoeEM8rqEgEuLX7tO
mkTm4AoT1ixEsKQgvl1OE7IFDvb9uauG2JBfLXUlVoUauYZFH6WDeam5SzOaOY2yLs7sg7KpQ0cd
wQWts6HzD7z5lcQCwxd+nhIuQifzNWJT0P139EsMqXI2B/D13W2/6k6qvZ+htNVajYekUyjlAsqs
DrK0d+JrQcAdzXIvARhuKLsYuRRu3krU2u0nEbhSbKrN/B9337U9Yr3EIcH6grlv0lLgRQJ7B7E2
RgzVIWxKIhoEfvx4yBXC838aXKywc3f5eGTHNEMWUWxxaPPbDNJ3L9T607bxd5BNf0jPHJSoOlXO
YaLPooNb/nEFjvz6O64c607ARQLeb2vGFoiTikhbKn1qDxEb74GkqCzFZAYjerTm0BIVtrtHuYZ3
gj6gDtS6uqyUwyXBbmhOHJCMmp8JwDJ/nZTAPcBwV0KyyR+fi8f4jy+Y3r9cU76Uryx9NKvjhz8j
aI3Wlt7oY32WOZukajcNZh3hBFXusCYSwCSYdUcGewsRoRJ1/XIm6xWBFsLOU90HtAvglj4sAWFW
jyPrKO35ZmX6tVGx3mUmDdveQeYEOKVIiB9qUsQwmLl4zYaFHM5y73PNLAC285oY64XqQLF+YngP
ykn8AJZlyGDLUxwgp80uJW7g+OHMPKjDxaQyDEvXEzg4mi1N2gjUnC8gBZ4GWtIOcQ58MK1iSt8G
jb4iqymRwUx5vbw/RqJty0j7qG6Fs+3yfN+hlqT013GlV0wojNwn8mdy2P2CgM15axKQYVEuJX9a
WY1KLu7KWXUH5vzW4MX55MsjGrzl9HXrMF/MSt58VdW5WH4RKXN0d6+l9MdvQPLA/C2w+Vyzre3x
i7FMOBpeYZde2FRejMfLwIs1bFMzaTIN3Ae415HIFC5zuhqBbCKrfyszLIDnASEjhpA35brCTBs7
EUV9Soq9vpa+PnO532twQ90Oy1CiSkMoZwkNMfgh54fLt9PEVn2xvzZyVxNyM/zumW6QTXlzLOTm
DqqvFBQ+l7+CksfG1TQRu97DSs5I3LIW85eTbKknlfUJgkZQTbrzjRtP3qvAN1KrFSMKKaxsgstv
7oBNCBsdeJBI9QYo7km8M2EHl08PA64FNUruMiM5edBgfjpmYoxjVLdByeEs41gYvbHgDUZ4pVXX
cQ6jZarvfiwP3mTUtPZPCsz7DtWxPOq7q8X0TWG6z2SrQzkGp8I5nXzfTEGX70fX/6BEAZEap4sH
euREmrjRLgZuxNNQRTJZ/ZXmTJv4xcbVWgfclN18FQCAs+nI1Jebi41HsLdMqfDw65m+K3GVVB42
Zb69z3WP10p92NnJY5RE+F5mnZOwsCmE5GeJ/qJJwj/i+TWZ1STILvAo7IacXqV4gSr9BymeWSdE
xMgVOKZUuu/15mlOyGBnlbuJZZcKI4U0+NaMY86535O3S9OasX7PBWscS6Wg14Gi4yFh16Eom3ul
HeW7s6XzMCoUTYdUuq+pGj/Ib08AwmJk+KWpl2NGKk7dASGXYyqexFyYJ9lYSqOQEPq4j7EryBTm
SVKobUgcWwK6BCLD+AwEXOVkxDFpsCNVXJ29AbS6hEbOqTkS6blm4lCZ0SQG5kENlAcPzWXShZXB
N+mewN5rgrrD+6KHFtWVmZ68YKEWr/ooYvlN43i56cDkFSVAEOUqedYcyJW0t4aboagWsIGpa+q+
+3qDvLkKWjfsMx91zH5FErFKQl1Zwx3Ios2dYSBO7bhc1/CQHIJ/2v8+pZIQe5DZJHjEAaH7iTHr
+5kfoL4Vh9ArWFU/Plu8/OEdoZC+9EdJyTiGevCJdlEZ10Ciy3JXPta20GBCSuXc0GzyqReEPFtt
+yFHoO2piSNROQuZHjM/bn9PVgT4oA5iA4fiIswqhXfafspnAqd2nQFbkHXVTpyK3NaYsldci+N9
ZjYqviEZN14qJjVFeKdBqxHfE1GFVvgVZQAZWbVL3xYLzhn7m7tcu/pPIiFYPM3yDJxHUeXn7Lko
O8xdzmX8Eb/ThGmKn/F9Zk4oPev9LLDA2zgUVIep2nb/oadLIqwQhu41NlMoeL/HDnyPeBm5daI2
opxrh94VOAvrbQNoJW8Axq3s/Ug8Y4Y98BekrSbexIr3afnss23bQi7MMFjJU95I9Fv6z7WFoCUH
O4p8c3kHNK3JWyLaiXaGYXPvJF/UOnLGDbeZXhXHfX8PN3t3SXSnQcjbi4P1RIFGkF5t/Zr/Y6E1
LGDdsNdG78awGpk8w9F7RqQvcRSZ4B2Op/IjLIWa/QrXMd2b6uf9Owi4dYvvvqXHj7+ZLAqRj9ue
DYAHlfNgHz7a3jkSWKpPSIC+bzB7+7krnEOQR0Hry8XxzL5AJmLQm9vfJCJAbIHpx+n92TNx7kLl
LCPet/K9XmKYGzqAAN/Rmyj/KfP90cCcjn3G0/NdRA16M9EDjzv+9ssrOsDJT9h23kxAR4EDF/U9
KBKDJD674H8w8afZDzcuy741PLl9d1jAofNH2QiBN27cRNLjNmxRecrRrXSDOsm7F9FhRx/ueHWN
zXXFBMT2LUBwmEK28SjDUrQAaVL5lW28wVOU1wTFKKp1jjWbuzGs9PJDEIKKuGev2++0RvfOHjVO
cVvIJhEHIHG+AJNxHVbD+Xh8cwq5S3RGcNpFwsKIFdzbFjRXzSgeEccZ1Zxq/G7weejtGdrITZDH
+PbxeXvHisCNjx+iClsKQq9Qui6sbdO+T4urx+r3DCa8fxFEhhHGkylq8xg/oI94Kr1nk1P0m/kC
TeqRMJxOAg+obrutpg8guMPFbINnyuE4RbaNC3vy56bX+jWY76qYV87ihj5SdX5iZNsTXLiDzNAd
ExbEy82W5662YP+fdqlgkDG19vQp1apt9IlvyCUjSm7Uc4iFAjpr0Vc3MrrEdevn6MfMg5ReDj/t
8DT1niiwNPKLzxKIHhxehnq5Mccl1jzsxCu9AjVAy5/p9KtaTw++LS/tfMGwp6LtuhWrqIGqUu8b
w6xLmC5Oefhu6WAv8s+Kkkp0RDWS/N2fotGRAh6YjusVNcRgTWA7Yu798S5u2wszKjx91w9OKH7q
hcUE6bxekBp+mS4NhQBma+Zu68FAEocIoLsLJc2tMnaABJ4puDE5kwg+8rLPUDdMfm/f/nsY7xa/
OyAhyWdWdascEVpRJy/zMJqvSfgbWfdFUesn1FDSPQ+CajOxp3zvhF5WDc9G7WqquwpvoPw5tZN4
32zXsTzqiHCKgT8O18Lqx37N5eBGg9BAuRLtbiK8SKnelezgiycYNxnSlt/6VL4tHewaF18M6rhp
3T7a26dk8x2pWznsznK4fDxJiCF2dax8d4UDo7EuustNt2U9Lh/s/fnKJX+mp15oJvXQaF74Lk+1
doQXTkWRUPXq6V4l1TKeP2+vapB6c14jM0LWLRmiZBioET8+NZUuGWC+uS7K+7iX0IfqmIs5b0Qu
VQMljgWyCSsmL1W+9P2JzKo2walEGZ8kp2tADuG+peuwQJc9MqfqqGAB9deYOP76McYMBtdmZJA5
AcPLuRxLPsheCpyi4UZgxoP6efvNGYirubb8nqNuFHWpn9g8A5FlUBVd+BdmSQO0EqHMWrgMIJFZ
1bHK8jITcr6FC3ut9g8RdXg4D+10uKB+EN1cMtWphwnbGc1sDlywdjj/1jo0fV65gIklhRNsWs2N
beXXsWYxicjXV6ETvO+t4d0n769WyFI/tH+LYQnd+ShP5AP5sTguSW38pHinZlCy1pqeganOix4U
O8urcgemS5Ovi6oDXlbKJKiAFWrqZcqj6Tftb9SZn7OdGhlzBafsNgdlfznbS01POZMed5iJ2IOe
m40SBYyhMpBczdSPW0Ljr78iKphtO0EHrBdUVKYVRLW4WIeHldzsiMx6R1AZXqgw+QvM353qhXgX
IzIVW3vH3n8Y5z2t1BIy8C4Z5GdmV9hyTb3SVWAVe2ALqvWyTKpYXf2CeaZKhXyHef5tyH1b5xE3
ojJ8TPM8bogzYicKddp/MdR7INDw1h+h1B6LcUNMmH2f9YMsaf35p02WUdmIKFRswvBq8oz5xvuV
H9FF6Fgettw/O7gjIvXboqo6cq3t2ZwIJQ9Qv5GlqaKrIgVKoY55ZAKCyu9yb9vtyHbZS7C6wbwG
WkR2G7OlGM98/ST89MVFA7WzADGuVcg2jQiiY0gMEDqSwvPTOJQQhnfQrsuUqnJ8aQGpps43lGDf
ZIsh/u2Iz788QgNOYkkwfpOwV32k1zGadP6aLj76/9EPe5r9XlN/YInZvIh5ihILqdTFoD5Gqazh
TKeMPyWpcy4qpwclkSYsf4e5NWUPeGfLXndO34heX0D4Hh5ZebZByzikv1CAI+4h36e6S0GgUOP3
1xX72Y05RQRaAViIeWzjLlxN46GlzBuk1oqY6QwJtIbnNIfd7KsdUCb3Tj9vgTSUl6IgHbRLxA9Z
nte1tbtZwRIlqBPLkDguaoM6fFw6QRxn7XHJPHEzRgoafzshDjQOpHPDbHC0fvur+E/F0qHEWWXw
ywAMtAFErG+T0Mj3lBU4k+uQhbCBI37Yk2Goo3SqznL42/H/+/02c7gXAv9hI1/LTBQQNh7TtsP+
OIj0aNgwvZLCax31p8n6Ka06xcCjNc2eVapBQpm0KxBAyoj0ve4X41y+CiOSiGDsY6pdpkHHIZMQ
pDriTygw8NgbZMsu7pjSJ5RHzJOP8ZK5+wokdIq7tbhmjDF6+Jv1wpkUZ4VBxDX85n2Fl6gKzqbB
Q2WA5Xxd5lZnucu7cIXnPuIYnslJPcihda0ANRLiyy08rCoy6DgljTQylpBd069mLq7JJMbznPDc
jHWb9Ot+hMjoBdfPtNQieHF9CEvXbuce34J3eJbmWsOYHDUQh+nqU7Pey+K30QIhFTI4uAUiLWuY
IO3EPbJOawjrFLqpRYVq0XuRcFkw60d393I0NMd2yIpAXANSZeW8x8VwuDfJnul2Zy6DzluK/4Us
ZU8j58crjdibmO3cldgeBgDKD6X7mgPf7KNZV44Po71ZQsISulAXyr1o79/LqwpVdFcj0aIC/A4K
zpnYQCJvagcVrM+P7Smj6/v5z8GM3HIk3mMkJF6JaQwL/7cOdpxdob/dn0ADgO3s/WU+qGEMXnsH
NnVNVM7598bvJ8eGHUrqR8d1m7pVSRHcnPvsP0xfi/tNduZcEp8UZevbId3p77KkoUJ/DDeWdsU9
0Kyfq142YiEh8eT7NdOT15NSuNgmaWrykxTXU+qjy59RmfSjJf0sApdUj3PE+8l2gF4ycN9eCNaz
QeG0JEsg2zX5CJ2HWB7zBFCa5rdT8SrKUYghwLTWPT/4RKIpbV6zDNIdcrmXPZRgx5gtS/mKDzDz
CK41epYIIEIJ9qZb8wUEPMLqfCR7l+eu3rBLwG4XdVOz1K0BgbjeFEkaTCq8Y9cz73PNxWisrgHx
nZucoIDLdnPk7+44Q7O63pQbTZDLIACKMYx25pAu2wD9POoNU73vINZW5EzCQOyTYFH49cMed6yQ
5ccfzG1uzSibLSB+qt4NFmbr6GslBsLt2poMwMpX10/L0JSVUK6ce1R7dsZ+42pVm0+qvDG68aG1
8aFQ9DP2A7DnjvB5jq8onvI08K9/TmY0+3n0ngIQOzgtMUuEN46ORpaImSkQIijPeu8Yc7xwx9c5
6AIW2Y4wIHmfOVRp47fA5lbL4NK7J6MFpGOjlu+dlfkyoDAOhyt3P/3Ch1p6sVQjLJCWrJTHug/8
xIuLhv6xb5DBQ+ZeePZnGIRTgMCn3Nh7gtqW+oO1UGILvDNhmOD5sNhI8QLUSr4PxApwFW1qo5Di
PjIGGENws1/crJPyqJSnAS2eOj6456e9y9SiTE4KYsqdUK+/p+Xc9e4SZMqBrzdbjFQtqGnddGs1
9lYwpw3voHekvRc/uaAC3v2OMCExpScg3gBGHOFeIqH64PyR+CBA3oWSb/6+KhQHt72MiVFvPR/J
aeP9z2M3wmLG8PAnLRIWJsMmIubfhoi7R5DtpGOKNpdyjF0JoDkG43mZJrhI5sQenPECfthMKkxN
MlmfSPHFzbB/bNMBt2GG2S6Ta+0Btqyp9VJZy9nx5JPddKeuj7oUZgXNwwiYrkJwneMrjxP92Pge
ODcXmaCWuSaan7rucqhN08KPg739zLzAkuCCos0cPWCqfRoLIj/uiVytO3TPuvd3Dp08DM9HxGTF
hZ3z4wE0+sJzuxcgldDIRIgzJ+33tHYwtk5o26bmUAunYPApFdJWIC9Su0Cy8ni2NIkR/X7vEUCD
8eFG6mC06OQnlT7Pk66B3f5QZSg6CZdwnR++jlQk+waCIWGjARxcitKX7cE8uPvgdgKklvugMBQc
0Ls59wb47Q81pS/nts6rQ5GMDtnopM4xSaXNA52uxbVZqyjHrdQTYEtEyF5OvBOvlQBvOvN7gkPK
2aFOGiTdO2H1h4XPikJCLt9E8GD9JdmDR/PjSuywQJzpTz7U0oVE1dV0wPO3i+WhCD+LiMK7T5kI
mXfIVOiF5bIu7UwRbeHU9vZ7wltF1u6FEmmmN32w3yif8eDKdAKM6GbS/MPWaWYWiTLiHDM9CdZg
ZB0hPoMnoXt6qr1lpteVlPizHmrqwbK9/2/vAbQbxi6/6iXYiX2M3PtBSI2Ec7JE0nZN3fh4Lf8q
pbZxU//bSUV3bxagAj5ztjXGqsnRB1LmryYB5kvvWiNfju8BvCYrVq6FqZ03Lo1EPSoRfuPD/FW1
g3DVpeHRNAHXxtCUIkF+0qEEuwPmQz/xFDz90mAzod1ZnoEW9pn1sQ4qMyNC8HAV9fPP87dDUJoo
9NbY+SL9X44zvXw22tKRDAd07YyF2LacqfuAVCFI6qIuiRB1KPwn/k1/00eJZXtqy8Yde6a4bdFa
Bd7rLnsJDQYVHwdh2kn7/Tt47ynqKFyR1S2ZmUlCwaZdMaX98sJlo+uaXfgFZmyiTBhkRYWoUO7K
G/B6ZO9lUkv1BBO4cF8wQCFxG0lOPt2P8D/9P1VOLyr+nuB7lIBjl7FzksqnCP5+XEGB2UsFfQkW
IeZUPNXcjH7fAtztKBzFy0LCPhdc7R0lSOVDwL9rwSiYDhfL0lwCY/DCDefBc8FZSCHnsqHiTckS
A/82qn3SE2tu7kSaLB/gN1cMdTuz6oXq0NS8m3DKrz8JAnWjQcwpMLmsNfPSMjkiqqUOVbgwtLMC
2+Sq8UAt2LcKH/Af2hUmBqFlq3LV5KrHECAzZbY7g0fpRHudniT1QDb2xrlE/EWidN3frTGXI8Qx
cT5M0ItC6gwsyt8+zAEph61vqr1POhOcvn+Wev9CSUHElkWESoZOfxwnQ1pNXGzDOLeArJIVjIHc
yRopQ1+fFvD6oa/7ts9omjmezQjahZjaW2dYEtg5oLT8CqFnRA2tf2KjSTEk/XwbZhAh6Tsps7jS
DdmB3zIH0mOszUZD1nAxUHT54D84p9ix/SCiIUfQw28vjGrSOTtIAiaodLKcDrLpZFI1e99obfo9
RzY8dYVkbxax2fdubQG7TyEkQZP6UXqud97awZEGVjBL7o220lqiyiJs0nV9MZ/VzI7Wy++FNEdy
ItpnhDd/aYX5n1IwEXy3tSzKQxKvuT4dKMz1FeVHZBf1b3zi1m9dMevzY/nv4aPMXm7ccBPLbcGf
QbmSqdJmCys3ybPHHgctdpHfisuevUKpTb0frmzqunvnkuK675UCFHJegoJjWLa9lgeMLdQmBy6q
75spM6QNXdei2HFxCTqeArnnmoiOkrJM+jkA4KlVHvSHzD5XgBwnxnhNVD5dziK3RzrQeou9nZoi
md/Vgf7FQbbNSDfRBDPWp1Wm7CnF8+tYdIvT3hlt5aL6BtYdjK0PdyevGLNIW2OU2P1A5VS1ot9G
heZGWjEZPfhqi4p2lSdHoJo7C8DhBFFXwnAeQnd0cBC6Dpe5k4HkQ+Y3P+BUO2BBqsj16gaZ1Q2E
ti2ER8sh+iqvBDWqvbFPFpl0CzOSEpjwzxEEaHGHy25Kdnjb9VV38v8Z7vK0dkMFNPG3kch5l5LF
BxlDwAmPY8SZcQ5MTlP6nXY5BY0TNeWWk/FIcJpYUKc/1+6CoYx6y1jKTo6kFTxL73KBGBWZhfpI
F8X6GWnDx3UiQID4ZnPmx4AcaEFYZdVYbcAGJLtmvs0jS2Hk6Aqc5TZLzUGabQvKGxXg/+g4SB+s
3m0W5ABh160o1JlxRyNRZMi+T07DLSVV8QfE6o3iaoSamkX7HYEACgfyBwR9HUnfrNWGMNHhwAFQ
xN5wTbDD1Tip3d/ScDEa/xTJRN6QaPvPLwDBA5AkFGdnpWyKl7u7VtcdiOuvEkIiHYLsh8u+AdXj
uMLkRYPT/Qzm2RtuX8lp8QNE7KTujFimpgdEkT/UicrAoEaY8Ku7W6oTnHjmeyYm/OjT9BrsVO/a
J7RePckaarTcCmVRrsWPw8MSiAsZvG8RbDj9WoeDrkH6LYdlck9a0na4leJ++JUi/Dt7/MiDNIoc
oOQUt9bPzOjnUv3qYKnQyfw/KZS4zSjSyXLHa8cKLIxpXwwwn+j+zoX978kmLFC1znsoY/A8XFnX
mrHqA+GBF+4hItqmcpG9iVk+4LwEjI3K72D9GFypC3ud7Pbplk3R8GJG6OiGwU//8kXbtjtXm+YT
7DE+PS0Qw2hLdSKm3MzB6hjfipv8+cG4B7UoSSUI76nShJA+PW6vSYNOaIKe2bt94+O1+wE2WyA8
l/Ocv0j7bb98OMOSocaxIFAcYOfCbRrEusK7yklDWgJWy4fvkscIUGyzp2scw/b7XmsqP09Kf74f
X0brigxsfc37Q+exVLdnKbh0rdrgHcf/wo8YPmcKz9f/Hrt3fLTftZvOwEmPMLPkTLQXMG5gmd56
kGG+xVZUEC568N3Jgn0ib4ALH8x/8Sf01micj/znQfoOhlexZHxtz5upiHotL0BJa26BNMBVvnpt
I91SfKxuMy99H0OzrOqqpKclTre2usQ2UhdDaRQYYcg0Kr3bTL01DKD7+ncH8PBtax0OeBeZ5cPZ
Di3WTgA0Hc4Ue2TsxeyI+waQr9en7M7rNQ9UQF+jIs93tAdxlBLW02Iiy1bD3IwH6LaKbNgMCaHw
VBsSvJWzmk4cYnw6KUsNYxl7wASR8xyGhfo7f1P8JfCaX+U3p7ecpUWBCrTfre2DZiAu3D/U9paW
94yvZeH5NkhIesV7iduu7BNgty8CwK4GGjwYZOQ2w8KIf8w9PKRo1ytHmcOmjwH0AqJggMHdXGQu
8DCCTBbEu31EP9swBONZMPEGTESDHw3pCpT9JJYtCJUpQBzSfzC09YgfJRVPtJ4RXpNl0aOeLVQ8
jfl/j6qRHxdE8kKh0jWGAOCCIQjiRGL8yhy8CpF2KQuuAuR7rFBJlLLBeyg7MvmdUhhdvlchCtp0
yCIeuYsvxmfVtSPyohdO+Cmx9P9yStzeFn5yMAieIudtE+MFBIAc6DFt/y7uUQQv7eL/heheetN+
2i33Y94bmEGmWmXc8VeGYcKa39Pc7HqQZiecR4a0xW3OZbth3CCmb2hbsc03pgs6sEnV78OP4B9O
RKZLTEgBut1DnRgE/+hji99ORE8BM2pfDf3L9f1Rf0827WcD4tUlAkxGQHF2zCnNeYwVMSFDecqE
IaZx9kR86YopHIc+bZsvr6vzBaivZG3Hmn9aI03+aXujJivzfaQiwxj9RbYRvDeQkPtjDQ9JrFiQ
BRwteRS1S+EbjYxMWBhnxboPnx+SUqE2qaUlzX/83NkKDnkm/nBVX2SGrocBByDT6s9SD4n+jCjj
jNhgrS7M4N1nKIFtfslfgB3PD0ZtVBGvBQBzNrC8Vb7ezLaCEt2OIEybet9k4sn1RQcwsfp+pb85
qWg2BJ70V1EyU9PeXpgw9o7RheWBQKYzU1mJmJ7KSfGfEkVaWlSfw8cqtC3gvm6wnVuwg+v41+dP
LvjLSG5oqo5fa/cVmDeZFhZzTNnrFylUxP+Bg1xJ+cY/YUGNBAmkY+DC5Deo5nEU9cxja+ORLgXi
H0eLrdZrznY0CmaJjH0d1Fv+6z3gIxdp/O6CpRqmSnJt7OGUnPlPW7nWSdiBSM3/yu1o1abZYL9H
PgCD797EgvREAnzkdhKV6Q/gkeCH2WT8+clyr3u8UEIvZF5dGVQoNF3u7bH/Ud9irrRGwIuKOFJa
Kj1qcIXhFsSX8jataQp460PTyRoDtgx0kWV+6ORS6EWcVNqmV+1//+bRK2MlgsVD8SP9HHurb4hk
XArzX/Pd2DNnCeHG5DtMC7vr9LzGeD3hUe9KNs8oICjxIHHC6AQDkrumfsY/IaQwbLTOtrBKAYWK
3ItULtanfhDE7MsMj7Mm8xbqgUkpwXuwqegNuAayCPTyUjW16F/nC8wqVMKxm5yGY64ExRKvPQiB
UnSIduLh7PtVs66vTYdGX0G0R1qyaCaQEGp4VU7aqf1TO+zC6bphjEcBKJMRoZdGTBvpQS6sbm4y
dHbZnytgTk9CWGsdKsfxMmXub+AuIi8IBiyosIhDpoUxCYjVRJbnx/VRy4lj6+nKpF8wb7LpbBAo
hZm/8BXrUkacBMTYxvGrFpFTwsA2KPnSMzXVHMBoPTMx+MR22r7d26o9wTlNXoRinKcN/hFCu7b/
fd3G1ewp8IKh+fagqktk3Zb6UK32Xm8/ubUuq5oqPKemOzfX+sjqBoFhWPiBRhRIOEHlP8YI+a8G
ZOcSVSUSb5fYbD4D38RofYk28WKhKK8lz9msUKlhW9f+YfAftQo9Z1PcS3jGgOa9wFC7mu86bYBf
jc19m5QC9HZX3dpR9di7PdROpiF32NKA0wEIAaa+8QwWxBFiZIgo1rIeeewbpDFzxgqxDmZ/R7WJ
JR0eTSq/WERRSneWruXL6QT6sxLFV5URIPL1ldnwUmMHj2790kkxLtCAs5I6V550KZPmPrMd98tO
XqZHgrTz5fU04MBkgok5Dpn8lEVnhOHVK6UKCsRMnX2H1xToK5gay+q2ylLGy4XaIbytLX/GJmhz
sHa5+4iZBWgw2ErzsB/dG/yO430lADiz0FPUYqExCxre36B6e/AXQuNRfGcLCLARAjeTFodPzKC+
2Ncj6lchL93zfmMCJmC3PvsIhKaxWr0LPN/q3jj0SU1Ikoqu38yO0E1T5Kgbg/GmoAcZDLIyFOEd
x3ir7nSl/VsMFXe8suTqEpTUmkOcKrsUwQYWj50T3yY9q7mDYZoxvhTUPOmcsa5J72Pcem+SJI2W
99EBVrPwbMgcP8dICDYe6+0E0phqWTy/pIoJ3MXVzssvieYvz6EJz7uvhdNkRxFdbb3s+bZ0e1hL
3JOd2+wRoyeviUzn0BfPqvgEGUFwoGTMmz+ulKQUIfmfVG++miaE9iroLJtp3Ao0h+B6gmCCyRIl
X3BDC27a5zglJMctB8ctRqLxK5sJ9nusvB2910A4kBfhOel9n83q8J/LuAIw0IINjZ3D3p1cJgiO
TXsdRQIQeiW1Zpib7sgL8cERbGSZcoicr6HO4bEfW8WCKERJ5aaCE+cXrtJMds4NbvwndaSaZgPq
F1pyMMEzCC+VcTeoa5Kbdawumlq8S9wvdhHYc44b8wI8C8K+LcsYv7d7UYiaeffkI/wiSlI2/o1W
IHG0O3kE5T5oSGuYsCug7qOHCnnT6Wy7sdLEscill6cXp54TR4acfH1EriEq11WWW18xPBDcLxnT
LeHG7rXeU4xmoMDopJ7z+IL6oKROvqcKtrlY3Yk5cRgQwJydhBeWJKRhi9Wtt3ePjAkBGQ8KYqxY
xfU9Vnz0Q8cSDMH7CTRSteNCbG93zuNfPGbJeYEdgs+jw0TP8Tm1gp1nNKwA/aF1JqRYb0GugQ5o
D6YcsO+BMJNmCBSkfdjxKi9bL/ZR5yMOG1N/6UqBiMiTyYZz/7Y0LERs5v449feyJJA7mqeOYnN3
QFGv5HL7KHtAQ9omdblUEo0qHgl/CREv0l2Zb1nrlTDGHUYiY+hIwT761irZSNK9K6ZQN7lMfEuH
h45iMADk6bT76x7ohpFr7B2tbdAI2GfPp2iWOfDw0HCFDqICSr8Gap7q611+VYYHhDZiykmdRhID
qZmqNFcA0lkGLbJizlMk3jcOGYFoYbzDviXm7Gi9cGVL4rAk96qcUj1a6w6YFNMciy++pIe8HKG9
e7t3wgh0HZF0X7fz97G1YGCVHzHcmLCEP+9OJ2DXsZlIGDodkArCeL8oOtL8xTK+cMhAfLLacV9P
H2jcV79BLNqzPUto50nj+/n4GC7qJvPfudVm4yDwl/0ywYWzB0L8KV82iHA+x950+DGSCJRSpxyi
MiyLFnZ8hkQEs2dMr36T2e9kZBSb9EvbSrBtrJpQEQUV4UXMZ90oBroaZxPtOgiwS6BpD8lgBT9F
+YUtFULltr/oJdrJHyHd7sCs7M5tm7jsA9tnYID4UfFryDuP6ZI1zYraY9aK38GBQLzPn/HKoKWt
NYffw/gwGp7X1i7ejRHcezjtND9Za17HBnWgFZe0d065V8e/Y+T24OZd4PDvhmtfDcbtldarOMKL
RxZ/z90MBBg+rAhEODq/11NkDhx6SKclpA7M3OMahI+onSLl/DQCU+3AKMKPDDmQYMV/jaLdlBrW
lbXerfQAAsHln8SD9DvBMlbOXo75Zb6iAEasI/V7uuwOdZLJ/4AQhvTnF5GX3bncCGDW7NAjNE0E
iAfYaAvPSo4yzR6nJjRwzPu3D1hH351S6VA7MPqyYNLyZQ165JmlufYdBaqo8rE/ylNbaL41549D
eLIQc9TYk55/itjEK13ECpBA2KFW28ucO5t2spdmqxPLCLntp7UZiaRfnXHXjBvEOspBlTDEwBR2
6FXTZYpAYD7tWCeaN8eVQp15FRQ437D6VEkPL1QiGSYz5WDSoqaCGyFnftaV3xpzseGime+OSpxp
KqAKHj88xJ8rrRsd/1COvoEcdKadTXgKgP2cB/WXrQsTx/WFGeTlnprFZfU94FmNs8+HdJAFtQ+2
zv49gzbM3xTafqneouZRXI4CBTXWHR6tJJlQ07kBnq5dAAA+PZo1T/yqFO3CRm6pQuJ1hzUBEY05
2XubSQsFtnEkVkaxa/u2uVIhA847+AaQZzi2ZtzXsNJOm5M0I5J6lTgoLEayt03MrC3qKe28m124
bfxxGhNaj7YPDT1bBtOnfq9/dN2NWuUZh2j/Mn41yonkV+f1p5MqkXti0qo332AaZ8yzLvAbSzUy
pePQtR/TOAFmqOv6PvzwQnblfy/sJj9huPZDOotUtR2oJ6J/5mo4vTvtENQLPmKD6d7lQ69BxNY8
LS84zlBZiM1RgGUJ6sr5DqcjRQjrcU8FChaPUlNLmi8bPWRNDv4C7gffl6v+ACD0ymUxO1ygdUaA
0NkH6qXQVQo1Zq0eIkX+46iLVfC7ykpKI8Lvh8NF5YcBdrf0iELwH9Qy2aSAiul/ZX1xdkdhR/1j
5YrrsfSt6FlcaPCKercYLYmiHLHdg6tnnQullJwo/LsIxgSnRsn9tlqUOMVQCB9dPCzBlJf4G6QA
u7rlX1w9Kf/jxyqLsNMixjGbGgRszbz+5SVhmaN1gOoqtUGtQEQg0dYKmsiKIqLCSLdxpuT6Uv/x
LUKNIsLsuFa1vk957aN00zL+nkDPSbowHmPm8Tds5hJoM1Ri2K9nq9j4+IjGw+pYfc1J6WNVRsTy
2gjCvWgr76oJp35MbJ57/kyNW5/npakWUc+DmmYl76qdX473OCH0sLbUEE0eia3m/49YLdKHzEmi
mPudFrY0CV+zh4GvY4IhNs/HKx3pD0r4vaBGy20vHmivKdYq8o1u3ri2JbDtDzDSmgzKwRcZ81it
3Ks2Gz4TwZhyVOxIbyxjitcv/xVAL7RG/cNLw2efFUnRwftKK0F4e///ELOTIcX7VuGFg4Bj2wwO
m4VR2SYWuPHRh/ubWkFeYgHb8P2zeY0qrnpedd37OlcGaSagPWR44Bc0W6O6nicjyd4twAbbtvop
Gc0HlTKNwQdkeH0Kam3XxOJiv2RNjKlYyzDOvQIiDgtDFj/blm0ufb0M+IXLzZHDlyjqMrrpPJV8
0cv/BtNG8SEXd/d1A0sRDdId9NLdr2IK4RwuJObrooBBwrKT7JuswIugnoR9PZTLwdrCDLF9822Y
kqhPUHzatXvpxK7Vi3RmEA5WTpl/YQkWDrDWsqfmIE6QG7KqBC6k0+q9SIhz5eaM+KnKZrfiX3sY
+XTu8n4eVs1z28W8cEXcnbEmj8oMAGnloZE+vGhc8CVO2C+BRtpK+K+ZOD9TUL//NLAa+eYJlt3k
yeVKnQnbU2OpqGqPB7CnS8Cq9QTTMhZpU2yfFUAX+074BRfHFBwiKyBXlV8YbvI9ZJfQtEDi2qGo
mUl1t/Wee24NF0dYJ+r8kj+VzjtUQ+hwKXC+eFh/z8VhCM748FmIDJqh4Akv0LCsiSblCAdA6fxl
+lLNNBruT8mfDnjzjegYwb4lMjZzUT2F3x0hR38l/JJI4IPFycEDo8eYZknvZAQWB10GMgCmE0Qy
UugDjYVMXRita6wOmJ2HFLS+d3N3gA3Z2JH3MqqRbB96N1NoCJVviqd/66tzBW7s1EzL9wKkrIVr
ujFjRpb5LUhLkRTRr2fKUXzL/cqAVB+AmIoZDJhuqoJVucNFQEJuxpRxbaF+fhnZ2Jyx869DP4Rd
9xpcBwV0w2UbrKPeua1RiKHQSI5xrB9YTJuJXzLhoB6zE0EZHRX+W5aOwxcWCxygm1a0GKDSNopJ
WPZnWYGvmajT9eMuIoTyl71Es/ZBgzboZcigoVBirWQ4tLeDYwvSFMfqCXKSvq6nP9UitiSrIyOy
Yt8m4DanWTPYyx800dEnvau2vwCNkeuql2/00FG8+idQLmTiIKHF7XkOe6ob9FYJW/Qu480YynNX
JolhG8nVwaGSadg93Wn43wV6Q/dFe38qyojiVpExGZ/6WrQRjgmK3P7FXLPvvFHHUoarXhsFgNwN
Ff3rcFc7Uu2vQOb2LoZ/aw5tBwJVttejCQFGM0yAR2k8pEOxvxtA9luZ2lO2E3c6Ffko3AV0i1Me
xuR2z7f44wkYcEs/SLDpvA+naFlWXQgBznh5/aHsz7SUcaa7KZBw4Cj1w7F/uk2im04yPCB/MiKo
/aWg59o3HhufY7cAGXy5ZfvhluAbbtRVq+xzfW9DCwSjt7KeePGJc8F/gZ08BCjYbwmipzWdoIL5
oTmsHJx+P+/PBo29nvQpqhahKqsZ8j1mEk9+aZcUlk09iNoeJa6mMfi/1RHDLvCn+faS57/5dr0+
4KfexExnTsz+YF/AZdOzPzUtonq+TqU7tuSxv4Tx++qlTUuJHWPk1wWEuKxD3sPe3fxzTL4KIk62
pe36t/xGHSPhrkXnc6LCqeuZe3k2TYNeUaaekyr17yFVqJBzZ7yDMPHg/YDqv1m74jfMfE014f1/
X8sKyhuebCBhLRQPOSrd/DbHY+NLWtv+ooatsbhFzPlIgoWhCEThz6kWPjzpbj5FiqIa8msmO5o6
gzU/RYrYwgZtUJRy/smGd4lzPyh4ntBT12ES44RC5CBtlA170QQnokTRTGiDonomr7a5gUEHhZNy
tTvHqFD1Fod04rJ22cxQtw+pQ7NGKZfP04NA53PfTYnjFiCEaOY2pxdQ1iASc7NaWwUlYWMpFQna
xH3DuVtFTXy0DDRJj6UEw10BXp58hyZ7OLQRVk6sExgMmgLm2L7gbDWz9DJTBtpi9tJ4vWS8dM9q
gdyQF9/4uXaX3Pj0QR6fXNmzc37VV6y8x3yEdJbnB2RnBDAGbYayua7ml+QC3jJ1gpF+j8VYiM8h
VZZbcJn5obKGxxkiif2Xvxc8fsjSEoq2oJIMQbvtY0DjX1py10B03RmYoGB91W6jZQsYDeoA5hf4
8Kero9agafktcF9QLqi8M8+q0xEhYWBKU+648EtvFC7tOCRvVjTbEHKKAx1vs1OIyKzvZ2LDSVxC
2eq4PirBFSFSUqwCn2Lxxz5GJf8hsH7iCHgPQb7BuoDaonXEqKubj2LiCrFjZ4JsOuXmZy2yU3zv
GPEGuK3RozhAvJgcZsU0csXXMPDe0gqgZcvwXbqBLUFFISiBKy9AcJ26kV8tGwqrQxKefFoZjfXg
t1ynPDVxE6nPrY8+emnG9JU3EbJK9oanP67AI5uKI6hAD+nb5tkHXSpeOQjRIuvWCjqnXBiE7XwF
eKHFIMe+wAJuy2PNKCTux1A0yNrMDrgtoLUbKp6D3bpnHtR4o4iMOttnUkMtTU0z6/LG3xuc8wbZ
ySIJJxNEBcibKe/Gf70codfXHw8nRc5IpRs/IiE+dCqJHsT0n5EKYb0VoBXDq/9V7BMZN7qe1BBw
VYj+zXwOrilER37ngy9f+Zv60kTJBaKZi2uHlIrzPwm7lVk56NQc0j6714L29xiIaLVfBzuNvxBA
JFAADos6O6KWUGr8a4hWnNpuGTQcrswcH61qIoe+/0MnYVGQAA5/MMNmCWPT7UodTaIrD0he3Sxz
gHZFpM3SysOBjwfMkTFCABBr47Sp/O1gNVaNC1GRo9mvAzwcQIhkEfXjaG4Qdd+kOQGpijWmHG48
krny8mPj1TyMx+ar+SxuIMVyLGP25FWzbU453hS8f+XlWXdVNJceAYNkx0qDyQQ9zxfKsKGuVpw2
7Lqx4Eiwta55E1aaiEtIJOToDR+Jby/diHhOXWjQPaw5nMy54RqL2ZW9MAw93L9EmkHJsw3dJn5s
2YotUY/JQSpmeW8/14QRoekMnghBRVhAJQmmknhjZzALD42Xkf2SsR3+u2qdVtzNLzHunXmdm/xm
S7Ekk5W+E8yuOHI+Dpg5J51al90YANRuWteJ1UFAy+g/4WAAzmaFV7rNKCvBIFgLwb98NPKdWldH
e9UWNjzmecFTUNXt/SxkRwOe51WLFzFy8FXiOGY3ghTceyxZkwoDIwBW7psYn870g4jPRQ/C4ejN
OzwvR7Fd3vKzxfxQW5s59Uztcb2XWPvcblhPR91rkSll/HApEFtlqx5tMfjMQ883Xn9qBNAfB1O4
wTAONNPGeibZedsA70+ruosrzYoDuAXET5HjXcJ6e0X9yQjpEuBLvZ4PAe7Cmaeq3dpmCeUQqO6y
aNeG/3dWnjtGch8ojjIFjSX8q9+Ye+5GRR+UewF2E2GpLPGEiBlEoJdA6iLeKNbtYCbY3HgWukGe
xrbb0adVJXKTNQGMap5mfBQA0Wvh3ZDnYdAJkTrzBc443dKJebCJ9INSHzxlu/TyTUfYV4V9DAT9
Wac0NJTw2HiU7TUAoCVKsTxkKDl4rBv9/mF1b8KeprI8Vc/13Jlx2GTJFFGPTeyvO0vVqQdDLRi3
dGJAtYLzS11jXwSguS5p0nNFZExC0AO4Qp6WAC2qeajpWevShKwvvQVmsFa4uE9bxqHxGid3sYsD
q69ZEz6TdTatw+Xms7Zpm/ZJiuiY+gLD0sebFd6AnaW7ux7wuJF7Ko3TltRc2DMaAZzXWTdW/Xui
cgkgJpoK+XFhk3869vn9lV3okPxO1VhSULre7OcZghiB3h8s9A+F2+PGmAoZnRz4ekIYzcYtGLkO
aF2yjuDaO/u/Jk11qjzcc+KLQuF3r2cOhx/3LrqTEs3W3ehyJdGNwtu1P68HZwocUcfjNliKpeNa
PylLsWXm4LJZBRD6TnqmH3MQUIzu7r0l6U3A2nnadnp1TZ6XiRMfcoSJ6E2yQ8SL6CIcf9KJnMIu
aXfWHqEgiR5pbfwOIwWstKxWdXTGxk7o73FyjYhqPMQ72S6It6qV+SoMcBTd4Dhlof8Bar5d5Wnk
yk2jaJr/kpdknmtY2C2RDZyA4tu8IMNxfkdWSZ4JzfQpfwNEg8uyodHHKI8BoB7sW0DzX5kb22ql
dICEWL4Lwru3mtTOZ58mUzzcIxTuFJ3QuvxNILAdTrCoB5KEisZe1zdHRwa3iTMbAi6mCDNsqgCK
IrklmVx2uAq3vnrHk3PSa6D4UeW/uH5LKDEKMk+GW1mDgUk1wPrvfRLryUKMgq7T/z05MlyBkq8D
tdc2d4zGAKiH8uAZmePfSXl0TYYN+u12/IdCwe8XMnHwnTAp11hQflyql2IDbWKj1qOW3RCSrH3b
mQ6i+QQ68976oNMAaiUlLg7Ece7W4ACxmgFshaQJCv3SJ2SwnFLNjYex7o1T5Quobg43Vi5uLSr2
6eM2dKMpk6iOrg9dgMJq5mxCUEwD9PMtoQBBIeZXekam0zRMIBdC2zsSmJoNr4KN/1Fk+GWqNE99
jUYP/JqtNJFSOmhjDqMiQ2hMPehSfjxqUVhxX0P58C++qdqUNQjl+2Nq2EOrDJkrJsJIlCNsRe9b
+roFa62iQUGQujNooSj+FtSpnKJpahf/yJgk6QcnZDwmyEnd/FD4Ydftshbg6tksR9exFqgxqycc
GtduAC6kwFpq7LAcSFa+jqjlB67zlC88CEQxLlP+azgizHIHVMvYDjkag8nggrl/W4MwXIU7X3dj
BG2+nNRRMdbg/VGVJBK4IA/d2kPuHy4LFphdwXuBklTU/xu+1ekKj05wceYkQ5xrQYdJSB5/bulR
R1EdEeGwZ3P4uR1WMoKYpGpAVH4DSdipChWPBYcprX1+WXC9i7BwQfUyEl13a+eXiTELnzCsHxEi
7z6A4yQ3WwKenpOb8gJ26JVKpSZ04QfzH0qQQa0jcm3jXLiqrJwdLUgLE1oFTutTNzoNClUpuhZH
nQCZ+kH2MVz/Kariqhs58wlgrsNy7przzlyn839bSV8lF8k2xINwx0Y41gw4lH1nUk4UwGe1EBgM
airsAgYOSVQBuSCycbQ6z0V639mouqHURx+/3sIaEOQ+2kwLmPB2dNRqvwiwNUD13Ig1IMT1UrOn
Wf8Y/nWdmm2ks5pyiVIpNHa0Lx5ZIfh1SncqRQy6qVeqT5hSkyCM5swkpEJtIdgg471YIG+O9wx1
LKVdpOKdrznuz7wo4vbHfpEvAAhL7uZJZSuYgPinfKfnlRvEirMzQmI+2+D6dEDT/XEpFd4Rd5Hq
Xah4/lPUjmuFxiMTb9s/7L2VRYiKutQ3GaW+NP/sM+wq8ahcYsu+1ajqUzsTvEibhaxd4gCCjf4b
h9w3nRRz7lvgJGxW+W4YeNUxokpgsokV4YSVx8ad2N9IKCw7M/l5rONZySjdro8m7prIHVsLJA9K
6iYy3FjFUX/NMGB1N28bw3lFT2Ifqs21N0lJsMLZiri5m/bShS07RPO56pgUWaBxEud6d09Z+Vee
maw1hJakxNhmVI+nMZbeqeU133I25LNyLWxtpVYb0EiDphr09cPlbCl54he37+vLdqVgQDbJMEd8
6813f9dzDhxb1hTPJBN7LrK9u7RidsgSlBnhlnh1IDkhPXe1NCb+Kg3+FWB0uKRemWx+/mIzkBVJ
H6SQbyXZ+fv23q0UUKk84dgKDLJUNEwlaupsc+dqA0rIuelEG3O/OEBk3yYBZrtlvr6MhFCI9Ua5
J9De0q5El9NhfRTf6jvUWvPDGC4Ol6Z7ifYg0dX+H0YuM28WAdDpotD7RpIBsLn1GkMlNcE2UAXB
9R/xSeEnNbARbzfzm1/JPYuMptt3ETmtcA0vYAHeiHGFBf1fAG/wuqCC10kxAEfmYSVdepQSh6Aq
gd+8TGIHr6zlCHV211QdS76ZFNWClGqq3EMNHqfPqOOuGDBh+2ssgR/xwauioGwSMLORE2Ok4Cy+
wgBwzFd8k45L7JdyebFsHG5x6btUN5SRJM/V2x7OtMcF/hCvO9FiAo1eTMLA3MbCw05hsvzZKv3l
U3+T7S++yItn2NBXeU0OJW/OanJa3gtUfvN1bGWME9mh1Uu3yZXloFmrI8P60AESo4+Rq0aMgZfb
kp0q1NamUazA5R3UtF9CcF/s14Vzx7MBwwSkCBIp5ACG2fUe7rvDgLv84zUSri0tXqnokUXPnNiN
c5IwlmBT5bUm2Rc45QHhmaslGDXgnHUIpk87+lYt++37Bc4uKYvblFg+ji9fjX5B6cSzdHBfPzeV
okzenIHKiUGatNjQx/X1tsy5KwfCqOyjivZg199X1amgmIBnmcrNa55At7LaINOYwYPm+y7uB8tE
O9myqUgOxz7eiJVx1c2SuhgGY2OZ96Gx2rqr7H1Beg47eumTjxrvDf2cp7eIEvq0aN8eHRvgrPcy
ai0RW+sNgMe/QaECj4JMUUhlbjQCF1o2h1DovZqVnTfUYkZRAQRX+V1O0kCOBFR9GnV3uiMlmmgc
wsECWAZt/tvQQjCZBchmPQdChdxg2Jd93EMgDkmfEfX+xZIDeO7hgjV0wVDEwfsDJ6QmRkNuOWEu
H0NFY4DkbJjNLxf8EIlNqpwCAz1HD0GfR8JKs1G8PSwx5WFI6rwoB9S59ew2J7dEcdxL9EKsZd87
QZ5BakR3Ej1hegGriB+oW5N8qOymuz8oIKuBql4zD4h/sGxkg/t3coaFadafc3Uacb+E7L31NPa0
BJcxSLBy4LAX2AxAmnbQDx4qxLFad4x8TZ9aO0N1g7H26qBr+fcAAYHs54x/n3yvBzXMKWQhie4X
VUvK47xRLb8zY0CVXPX3J+ASaeMI4FVkZ/UyCtiCbpVLT1jEvPRryVTdG4goKp8wrCdaS0dDFbYl
E1cjUuW1dldtRkbpyWLvWVcnyuoMhXGiVLKJizhkbt0s/j4OGsaPpyx7oS1C76M19Vj6mQyed/EL
eW3va7gYJISO9/M40lcxO8v22yy1wSUXrsoNT5WlzZzcRM65fj6pzOsGk48ASGp9jk6/9Fbr+Ymq
paaOIaDJyAKtySCLGWxHrA55nf3fmSEPOP5NcOBzTumjlWG9fod6CDKaEDVxBJMUtSiw9qBNinfc
N6KA6dmUIqUTexdRsMPSo88sQiqJbwnIZXd+ro0auYicSMJvd7o/ZSb7d9elKO5btOAschOi9zl4
+GaWQJsp+TVrPdNaPdoRuyg8mye2AK0e30EVQlN7KJkmokuQWZNQddPHNPvIMCGEkVB9s5Onw3zy
xKfyrdLtvWzF1G5JT8B3/pUMwYWW1H0PeHkOebySO74KA/9hFaq+G923N2qye0mshyEjr/lLSB3N
3B8nsdLpyOj4HqHucK5xRi1BIrE+YON59cIbECcpep3fZcbra6JczPpIW8XhS85MaX/5yCThlj7T
5RQvzVYBRXUBnFu+sfaQMQOTaNuKDQBi/eryYGVRLOC54LIo54hIe6u54wLv9KVX9cyjTSK45CEB
m8Yb7ce/ihG+EgUNTjDL3nJTsqbccv/DojAlsiE787q2svkOrRXzpQI+sVcrAATxp/0+35RrMtIb
krPmmtfQZCH3lXNDr7MZQCIva272kL6/VqXb/2ifoIZdcb35UijqmSnwFbIlh0l8jD4wjFn2GUNe
c+w9Tgql/XQz0FEtw3gGgOGg04rN4wYtM/oofcrBBYROjGoIsW0aZMPYT98jrqOCcmAE6MPKoRcn
dTipecc9f8+CvlJduBF3srA/18MW4nI2TMNwQuxgx0LZRr5tXQrNekGWuOdSBQ3a8po7gKV+Gbln
KfrMWB1T+fpeG8C5E86f+y+yPV5FGgeeXOtZqIEB9y7aJln8ARCCBy7QCm6gbEkphBPw+8HBcDaC
LU2vtmxujgsR8Zb4640Gjmu5VnMlSv+Quaf7sEwM5j6QqSEq2VaRad9xF619YfmT3a0MvnEAi9za
yhdORmLC9tF7AM2CAyWcM/EWZhRvMoKc+Le9hIMh60Xank6G0ZSYIsShXzpiS0giWF3asLYxDRXX
XIQX2ky08L32JWBLas0oiKWYR7gP0iTwulhGE4ljyKtlZpZqUwYE8WfJ1ZEnsfjkbqNHUU7Z1oJ8
cgwLKVgcsOwMEdtUqONOX5550v9S1tkAmmSxgqK3fDsTVyu06Y65y/rmUaqS9SS12Udnkpscwijp
wSuPk1vkNathOYxsBTrlCC6L5VWQy8+BkJNl5PTFg/2o2/6eQe5GxuGXGLoyUAu8nvQBdUhtyUlc
x6GCI+fSljYPShs8hOHQ5SdtaPnP3otZdrucPRYfJ0rY5VD6Q9B/ch1yhMPcumQBdzBJfJwnDLy3
2mtULb5LulVKOABof8peZPVyECg3ZCVxavdNOk6WD2pSQHqsHWgGJgrhdaL4ywkDsJEgh5xYhr83
rzIA0auM3j65pD7ENPH0qJ5GG0oUXIkbZSV50tdoY4LRExVi1tz4cRXKmAl7eC7zW16eCedEBSUV
BQ1XbnVHs9wb0F7czT4ZKJSpR0VJOm7/by5oRNfWGYPYpAHRDol5cuRY5jiyexYrrAqRHwDBzpgh
iBnNP796lFRKt22wvt59ONQd9q5342yyrXVYfpaLaYFIUqNbxdJQ8Zc3NTKSaH0VIOGQ7Aq1iIoB
nIHwgl7hpU0RNAg/5DwphxIpfH4DfAeJHgXhnvwKpE9mNJjb5Q0gLlFe1+1/96BXnW8+KFW83KC6
4Y3w4QuZl9CNvu4QYCuJnTW2nGPVPVskTOyvArYTiyggWamMSjXWecIclgtfiCxNvIMSZocvkJH3
9J2BrtyxkwrjzAM09RQtN6cq8fuUY0wwKc2MnpOUuWzqcIsuBTMEXSD5vxWupxyyHtdZFQkdTPyq
ri0RiWLqbgoXY6CyZxNRsSU5tI/9PEZ/bFxYbZc1C907ZeF/UViMz8opvKZ3Ze8GdPiKv8BUDJgQ
tz+T8yaSWqDL7Bj+d3P14Ahdz+iPJ5J33eR8j+VNCOy4L4fJWp/3BKPeG18se+25qRVgXJf9tIDM
PJ8/KFRFrlS2idTbazoqmLQkmPgFCB+6YPI+BagrF9rVRdgLcIMyr8P0zNFzcGBK8g1RZmF24Ibf
eZuV86Gj6CsZT1OUe3FEv/4Si7kkrjItI/he6MgVrI4sjrnVc7+pSfmkKaSuuJXR1XOBkKonU379
IPqoYiPDxToOojvkncaoOM60fssgiKs+1qSy757Hj3grZP+4P3qQY+ucGx9jMw41GLnusbCa09ns
PsdpggItOvvmtlafD30bdaU+7BTJB5e9TumA+qBcgirSpnChrUqmJlZY1cdhd1qn99nAfCEzV7jM
8xBoH3NXB01PW2xLTwoC/cnbJGpKX+PWyE6vEtqSymKDUxg3RGxV105Z9emf0rY+dnOjsss0ivEv
lFnsbORRwv2ha50rnJ8poCy2WDJNkZGMOsKGcsvKygscUXJymhqvNVZJtmta5eZK+XQs1yjdCqcR
/KHDI/LCYbtExLtlUl7gIDUVlaVaf3L/dfgbqavm5usOthyq4qkakTKznyLbhWBk8+v4cIQgPQ5F
vOIgeNxOQPH4Z0wTAZMsFVuCmWRw4OS7viaazLrhs4F7ZTHYLKcnhgGUw+Y5D7ng1K4kmpO/Ez5b
f9KZRtz1+IoBj8dvecYVHWjg0LPP4bOid2c/WZ3kRW6jpXTr+yiBtPb3jwuV6C6UISfrxPi14GEL
AfRyK9cldYHmaJdTfWfag+Kv4t9OJSUr2RWojFXa7+HIbI5KYdoKe8e+Y84yPfb5+W1nPy+M1BtW
ZODeHhvxbhVxuYRby4e4ceEvxitbfuwATx5Jh9XCYMCxBLDCYciMsvlLI4Q/e9b4wGSwIL91Mz1d
uITkOJvO6OX7QvQKPKgOxLnMPs7X2VwrctATIK/hOvjfdU9LncXs5bGAfzTPkR8KK6RjbY/WhL6S
Oe2LxLoNIKpnOmV25/6m6bXF/DzZjSWXnXRw++pusNZ3ZrdhyhuqcYtoU6iu7yi7KbMLfS2QcgIS
tw1XWjjQAtf8tZp9BwqeNiUpoeODe8FSDx5+6o3gm9Y4IZZK0On3NCvyGakbXWUmbiIomU9S2ZEc
fNMaNAL+Wf0Va9UcHZXImZ16RpzLPfclhhJ+60wj9jdeSkvrnog30v/tz9J1Z03tR+XEyAf1nM4X
gssN5McvJe29bLu/qkb4G1AGh+EXqB9AfOOcorDV5a75A+BH6OYycozoMeaJIudnqSaRpAesXG8G
Tla3R9LPT/zCCxqcg2DqOMCXqijd788t3F5PUc/0y4N9rJhg0zN2JPwf/uASNbZbcx1ort2xu/Jd
vxyT5k6DeOCs7XwbgSu+nK0BUxO5YcNJBTGg3/eiWiff8pZkVa7E7+aAX2AI+nEwSY/assY8O0kB
VUdwlI7ynOR431HkYLwkP2VzIyD/1D0ovBAey/dSOsCrE0QQaCSXXLnij0T1Q310RYQp8Ty9x7Jf
VYHxiWyrMfO08IJtOxM4kzW8KHr5gTY/anYcWHcMyGZKBx2ADAv0umsGGErIx4Et+DYAa99BI//T
nWazjzaw4SDRv5+CcgB/S+KyhPmLMLbeuAqIqeLXF5wlFEGQWEJr1LbyRQhYYkBc5oGquJoPNNMN
MzIwVD73d9rFct0xtNQ4ja9H6ylpq8TXStWlpE8dRH7VbQIklYP6XyyUtO6EA/Hk4Eb3stawn5aU
C9Wk7x60YbIAQ837oP555m+o5IcB/60LqVLvyR613th4D+qMhlWy3rivObfm1ZGoYYX1rVF7Azxv
sM+IXfNHkUyznWGNgsVjb9MuQd6YJ/BgZP0PjO+B8XI+I5x7YmY04HuXduRg6oULiCrsEOOJ9jsP
2s7ZpCTrQPAKDenNh4mYeJb/8NOO5dORzjpUYb97sPo63AHeHPb71AzYrss//3h3bbGl4JPqwHWs
XkvKsWp5fNZIw3obhTYKuLXyl3KkoW6owmAEP6xzK9l/gY9OyYtIpiBZn1eDqTcX7vfa0DlZUNpC
ANRw4z4s08jUMIhyPK4pD+4ET/hO/wnF0dCtQkO4KLB2kIOK9Q88HNoy8qks+UMbSWEpggoPOnfC
Qy9hXdEAIY8RYOviZEgge0IDmPo0qRPUkwk6JdtVj9C39CHMv/z3/OSoZ8+TimjYmAIWYzY1clhq
rqnqRvGbqV0jmCS/QIIGOSG/B++OQ9qSiVKCsD1bCh8kPWUQyoQJbBbgspzzUwnb/V3V2TncFi+3
qwf52qxs6UW7oTWWxFA3VARKGfAKdeLTWlVpFgj9b9yx72NVEGrj5AjkPF1j1Ou2Lom6FJ2s+XvX
w1/7J3fMyjH4ZhglNhmw2q64CLz9vFLbp9lzc1CC+JbkZVPZ4Q0Tb+Bul3jBwWNeif1kdjV6S6dv
MdZU0Y/Atv3ecQRQFTklnkbO+74UcwEI1JI7TCpPbXXH1m4vQ5k4WX+qHeNAfoW1nlStMBfD/p2s
H660v7qt+jSAXol0leqoxnTOliG0OyWFSUN7vrW1ZMw6g/8+2HwdvRm4EWoiOeKRtu0QvxzhveaX
VOlDmuXWc7DBnZekk99D7gg9i4DYTDNEHqKzHMsjGwuQ/FxI8ml8/cXKIDGptRBY8v8kTVMITRlW
mW4zAscjn1+q8PYpFuObYdtZYpdCxFG9uyWQv8tivbh8PYzStBM/49u4YuCj+WgEynrpr7UCBmpU
Gw5VoEKafMBGs0uh+bwgoIrHpEHHt12aNBgZWLi4AQJSM2bDN4R0pOcItL6z6Xn0WFjn297cfPRI
xuih9Z/ixDlLtVNrcpgwN7HoUcjfRnF+bcb8MuZyeQ4+5NSb44wOVN47wGIUKrRFReKR0p/i/KcU
JfjAD3H7pql8qJQ365+HmsTIT1n+VVHCUNZ6p2B0j7dZAoEjgMwhPGTZO5HmtDCwrzumeJKXlEmu
8a95vtPdpYFQxlENRkvMxYpl+GWDw9N/0UOTiQ4d/+hIGXGm/v3z4e2IseDlEmc0mTTkNcwzMS8b
VBcGFoKw5HqEijISojUy6+JR9HOiKMCrl+TfFoW54k7+BMFe4lg8Ut4qGpg7J8NWRqYYCpTsaVI1
/wWwnWymh2DnsYizDSfm3zqpaqyDfoI+ly2T968cz/mJiQXcCIPeX2iJF6oYn76FqfYLI1XFee8R
0zepiOnVaUxeQuk4ax7oUfeGW5BDyRveS8ZSWhZLR/7Cvv/F41z+3at56qoT6RwABzJmMac3+nkH
+SvOeK4HmuKZ3hHvxa6Mz+MAYQdWikp1ujKFOip10tsjvQqn7iiQ4d5PCMs6QOoDo0aiu745E2N7
uA6rlpc7si/XbKtuhX0+Td8MlxMMOJaisCsLveFhj7P34Ct2mdHLvJku/6v3Kgp7/tDJYMnRj7Er
KE5gk7JgRkpZuJrFn2pKzUc6pTHAmU3mH+CQjVuP1u9vPJ8nD21RWWbQFT6HDyx9VZRXfwsx2KpG
Xm4RMm2nVhthit+v3mcVyEie9mfxJboapefYoMv46pRdCT2LrRve2QESeQyoErOiCxEOKBy/pOeI
CiZbQO8pZ9/zaUsEKJSlRGMdGo35PbrYVPAXtjHMb6pcZBj/8no7mAFTeHp6Lqsi7MKaAwvZGlmC
cXs1u7b4cmfZ/D6eirdh0v+4hddew4/L3/DPrkW7O6v+Nn0k7jf5OyZC9bP3g0UMRdXCxxGwzRNM
lDlRynrERVBUUEUFnDSq4U35didKXAUMSmnWvRMdwNLDvzZauiMVLgavndof548Ry+B8zUIGZWmt
tEzipKty6gI9AyfFmN9bg15D0tqrsJhyZIiRr+wP7gHL4TcDF51QYQHTrWJOGCeTr3dLW0rZNXpe
Fyn4bedohbcgzgN34jKToyzWskmMqStkVFNX81wEXego9ABFNPrlkkD5C2fPIjXAARLJPjrL5x6h
kjUIst1s3qbzd8L1tFhqZApo7kSt9LU/zbnAgJyj9eQjxWBnaF4YqNyypy5wGG+EobJcX7O2zp7Y
vBJKgk82kFlVXEZtsdfqNDXo/XL3DRbE0n9ANe5u17mkc7BP6nqO7hAQDvkpW1KGp0PprhbLb1ll
eRPBkKgJF6SArC6sh1TAqLDHYHRQ6hYElHhG9RwsZvtp9Xw8v6u0HMy0umzjO4y73st0lGwRrQtb
oiBp1WlJ+kBwGiPQJQOWPuCrfbW9gqhZqgWXNZdpOGvseXD7e1gPe4Qxkr39Dh5BbUpw5uK9fB0D
SBIZrOBA0YyQPpRQE016/Bh8BJsupRXfbc8vDyPWRxKmF84Y+RLWcP0sCwbPaqtIWCteOjoJQjGC
7AidHZjO5WhrWfMJ6VtHWzxAdI9GXeAn8q131K2HnAu+0o0ksycHR74XYYyYNWSlDs3/tJnzgxxL
V/XIXWNpjD79qj1IeHHNHfhIXgNQJW2IAPMoshEO1BcKcUKO2ucDhbzHJ9DQ6WXzTcHU00Wkht3N
hVGt0djjUYtzSmcLkL1kYO7BWda5psrLenyDZVU3h/qBXIFUHTIwV3ZaqVcqBukK3MGSQFhAiifl
oaLRvpXUrfbDrCcdQNQ9j2fNKhdkPsvfNtUN4QTrQlywORMfWnfc+g4LsaXmHtezWa95veRrZgyD
lRMustp4CosI4c1Qsw1yVsC2swl+IuAc7iwnzPfLorEPFLNrlVHeYjzrc0SjilgQgXjPxAClP7yQ
GzpLV65e7MrR73gjdipifbSB8BWNMjCvdvJEUs2edbIY/435mKACtN6uuCIykpBjhZpmsy8JNV8u
t+LJeS4mzpzdr5ef7ms6wpW+nzsaRYf/VV3EGXBjzh4RPJ+zGN0QJSdd+x+icVrDLABVE+icqc7V
21S/O9scYB3Gd7gM7nN4Sg7tme9nUa8y6tEd5R2OmAWt35Ihpzw0fbTVLSMaO0OWBsVH3+ZQzcV4
jcKVI0E+VrvoV9dhwU43R2hZzGROXBvUv8XcEM2uwNOCucMrJorxAFiIkfsUIzAIgvam5zsm0/B4
/4z7cIf/lRsZOWwXvf8HG9IFFjBSlXBMFVXieCEmadLahgBneKEwmuogvXlCG5wlLeaV2bMMxnDm
cF0ENcm7YWAq36u5+uUEMrDWX1hDZbaVZlZ6s22/Y6O7Fe2KVgXpros/Z5TbCDAt3xY77x7n+53w
VgCCBRKOSdZxLnaG65dfdzpHmMWp/NAtDzMos953V62cOHWZZxUejdh61XfCo1FDPktYNF3wKs7C
rXCJfSOqJvdHu+je0J4nEuWG4/ED6xpTNcUd8RfQrvxNuhEsb2i/V30N0VCDK8JzT6FS169gB7qh
b2G8NCaOgtnHAZ73wMzZ8Ecv2VMBp8dMbp6FgSFhVIFAZseTsO1ZCQHGeU8ae2WpmCbQo38kXED3
YJ+WMqP3uopeiApnza0Xcmzo7bNA5UgN/Ab0+N+KAvdbouqIQiCvCPb8HR8HLdz4ZwtXOVR7pgVJ
+HD48lz/M+XdiGKPMgGDYL5j1dEtZDpit965A1HbB72NUhTty5XtIBkYW3tgmdNfAe+Ez4k48nuU
1kV+0CJK//1oqv5aIxrfOSzmdT2L+8FhMzMTtWU6lqmRlVDeJh4N6ZarAVgO5e5BuTHI9YYxr7k4
eaa+f8mfMRnHJ22jJXGKNvyYj0FSBDwk/2xBex13f9MFVz6MCzbk20q/4R76rNxCCL0sOnKn//nX
SfrnMdjJu3dv7scTb/D4eU74zLliqFtIEZuDpSGZQMzItapEFJHBpbckXDj135HRxNCqsVXkjAoN
70kAXbZFX1YRohIL4deBb4esXPr734X9ZWz8WXidymq8MbbRNGJ3vwOPgbMEBXl3nMvoTiTI34No
qfJIZv2bu/7MtqaG55g6AkkYBCm1ZCmwe6SgLMKupy6157m0rv3UBO0xsNdYXO93aveE77TkvK09
9wYSwwxYGa8GXD1re9GsegaHqDNSmFqOTUCNInsn2iVQnP3XeeqHFMwPsAriPSCk0wGqSSKtAIt2
Au6NWib4oMz3f+Ezk0SPrUBhhi42ejvFkjPXZpSgkNJVxcJYBG4qz96ATcre84XAQgRvw24+9N7Z
FiHes+/d691Tqne1y2El/TiQhY+aA/GcL3liVrLzUZN2++UNJKauPhgpIZ0TMDMETptL19SUDTVh
sRu3ZQzc7N6AXIQTU4qY3rA/HAiGtIcCYcD/cCDrvHV6/JhGfJuv4o3nli/Mg2aGmscBZDfsS9oG
ZH5cYzSCtOTdFsLzdspHZ3IWYfhd6hQQPh1PJNko9h/ZHPubbEbB8NFDE12u9ScsUgMU9PMjHxg4
lCWcr140op1tRtZTe/oiDXLrCKaUR/2ADdESNODT38/ShWdqxXbEKE7xpPzHaZOGcbb79/cawlJt
64RFPQLm2AeNKpTkbSLesU+BIOrbN5nlim3gaZMzFx5HLXrvKOjXkRLEMUUx4OJJSGpw6cu3xkNm
rJbu7liQuGlWiXaCPzwwEfWTWGg1a7CsHwuLEurTOfDNaAf7L22iX10Hn/FzSTHZL/ZLtD4HAQ79
3c/c4h6UTOT3JmhoJhTJZYobKwD7CSxm+ZIsQXXamrrkoLw+qqXEnisfz4qDv4dXrSxzLboJW6cn
U70/de6n8NtgT00AqS8aK71+yJQ5HaRbOm6tz4DWMdNd+IpDV03B/0DxHmNz/7MPvpwIN0Zw9qyx
hUN8t8JXekQVbES6zO/QD+U0EbhxTgB9mA12ur936zsrnUM5VdwJLIyPkg4SiYHvlb5bG+vtGTx/
iYKiVBggI377bEkkWN75O7BKWMZq3edcv9ZIzSI3KM+xwi1deVqWJbB1L4Pr0D5prEs9p5Ewh6EN
0liBfa0Uqb8OvGZMrkkQOSFuP1kf+UuxAmKWC7bXjK0Ik6MY4VAzoKn/zVA++jIoDEKqSy4ZH4i9
8WCDwTbJiJPVY7KainNGluadzKr86nzreJgP3KaGTsMgXcn6aHBIBt5huW/kYdscr6jsxX+0FxSh
K8CvrgtcSxAhx+fUSbMm70ZSjyxzK66gdljbYnrpxmXq1YCz9BXHadOHsL9f4xbo1/uC2nOKUCXG
EV/rS3DfAh0VbeDsOQoAeCVyqFANE/4KrVsQdklAucBa3xLBvbTTzbySF/HCWRboxwP15PkFX4n/
To8A9KYk5vgSkRInvaCdyfg+QenDsh4wMYsVfNyrCGlpt/eeSSGe7X8xew7nlHcFWdoxmVu+0tso
z6jRTbLdeKBT/K/laPN0tBwUHIUQfjc0LNkzLqUwfUnG6doo0gOcVvUArijNVqIPhKlYkWzJWb6y
muyh6Kv7ERk+OM9fMdvIU5RYXRTYGLwg8m3iEiW0rXmUI6CRib3BCFhmt1wDjVQwn1yf6EanWT6j
Lb7ZuyAry1YQksmEyT+SI1+e3ivXef/dio8XGVUrvjPU+WDCp8mqRlUyyAoQ5pFf7wTzi2VuW6Rw
ZkUKpkSxaoDCmgcoL8w6WfeYGft4jbhGTl/B944cXs2jHcru85bDPkyTSALKFKlWcIK9BXX4fQnq
5z5vCayKLQooxlFqLiHdkJDt6rl3EaEFfx7glbiquC1/k5kLJZE1mEoYuNTqgq/UiyvZeJqMXjnS
N1W/Q745HFynkduelraixfCzIylo4lpSePZbob6va1Cydgo+/LfJJr18zPFmvqpXp9LMVJ7nZROS
tS6szJiJh7Vwh6l89kAsml66t0JvhOKYmwKMg3vq+HWi0LeYCs/Khjs+tLKs/v+rFVEXZ6/MUtI1
zg3Tc6d1ak1X6VKmRvh8gfjQm1iMdCaKjI+LhHbjyVbsm/k6viXjBO+t8rIzVqeutjIySTNM5qOe
+nqn6m4YweP4KAKBbeZGAey88ZuF1GxhgDnduXniSqAz9gRjRpI7DFnDt5ndv0AVpZ62zRyNGXy3
fawiLh+hzHjWdjFctHs+urucUbN1l+k+dh1l095FC8Wl93eGa/HDI4wBxS3Lc4JvC/px2I09PHP2
87AOaLSWl1W4D/A6PK+MTB6eDU4vekSq5tcod+DtDKnuq62h+NJkcKUhE+1lRhQvmG0n3vTigO11
iOIpYMlaOI7/okW7Kw0W7NP7GfSeJkgx9NoCvu9xTMvSTJXFKmrXZtQvbGChhzMfC892Ats0c4RH
eO4/G70dNYsprfxpFD9vleeHiNZFx7kCrHv3uVRQhARJz/CP8nDA1YNt0CmYh2GIei9iJlcMwiN4
gMZK2Ywrf4oHFZEIDs7AQmXxXAaSIRS6e/5b8PpwOhuxLdLll0/c4MkAfUM/iqOpu9Ksvxuhmofe
5Y2TfUJTRErRrZ44sqQeQUmbSNyZKLWTBkiVEWaWWC80t2k5VBjLX6MuKIfp9uAQRlF661bPTZO0
FKGhS1gEevqM7e20ldUOrxVRmNqN9h6hwDB/sj8iqvjuXSWghvBKHz/eePHa0vx8DrhWRf4ylAhz
KfaMlFlPgJdhAgjA5fTmpvWfkVA09S292wsJe5kd3Srn9X+S/RIft5ITfzMj47HQPyiFXE32Wr6A
8VAQsnstwtieA9mLy8aqAzoMPrJLQ6P2wcaveLOBJ4vzCXQtql0N/tN/6BBiOnrQuN/tUnzQc0fQ
Pxrs2f/nqXx6lCAua8MYhSEs4VOPF+/UGWVEAL3aZ6fuMI6faHOwnWN5diQYlUmuXJd9CNkpRxlo
7EfHV5FYU0/QfXvLGCii0BfMj3CJroTSgGQ5XpqH3wZitOV+wSMMWGxytNkjq8bB5KxJwjrGKJ06
Y9sUG5tqFJa5gPSo3VTEZFLSJIJ7z8r2DV5U0vKriL4kZKbDq+HaEjya8Vh/6GBKZV7Hqo1WoWSC
QQYQz7nJu6Hjool5OOyyKG893McLeIXnEfKv1yfR1/nMgK+pCMaxlks5bVjzXuRgPSmNuNQUxL0M
2ctlwwcibsbwDdCOR1s5YWl+bTuATd1aDV1zbdDya1XvrSgFT2ZWWgTYB95dzBpY4VVKS8kipDSr
4QolTHidusGjh7+6HfBd86NF05k0HTqQ2UA1KLVJCIRsE5SDCB+jj2tfYR9WFAgeSQeSvv2K3tuu
mnSEow9Vx2dbeXbQ7/PN043+VGHpkwDYYbMOZthXM3cUDdImmfFuJ4L3jmiWM9nIji+i+APt1Ajb
Ys0LuVhMjrr9JrnLdwBQmPVdovt8TlpX6nCRORAq5pgRnVbTPqygg4QkQ8X7cPcKDq0J87+MFIX5
ZfhKbU/qi3CJKx7ZPfNEXHKZHCQc3SNO38ERG0xPZ/nk3hl1Wiqtkr57ijDpKjhJCagjrtTyPczy
85cbKT+MGs3+A3c92LxYrDFK0/ZsizCatLjzWewALNRmTkFE1blj5DXtONXqgVIlncLuvzzh54oG
5WljbwxsZs9xk2oIvg595ZcE5wBUdR9+TgiSRlTT57bzA8mn6wN4NVEr5GVShOH6KX1eqjnr0U8o
gw2AIRbUn19GTaJQEnOo3UC4YzINlKDLcbYn2sBxXTJx4M8IJVPSR9ORB9nYZkZLPnMuyq3XE5G1
Qd3GEceft7EXhf42TAFjYtBcn9mqKRuc5TS/Wtuu7OtsYAeoxMno6GUBTDpX2eDab+eAuGU/AsiY
PAs2fiOBpcDnUeRCbUEjMwsbi59ABPSxD6hjL1T1W0mug+MId7A2GGjowAZT4NoTOZealoyZ7Rwy
4LDs7WFuno7obr/MuaUcwV3Jv7oBcqS9yo5QiNfB5ehMX0G3Vt5Wi5pvZ6k/w55cKSOSRd4HTDWP
CJqB0OVWhhwVHtW5NqFuN8mKtShs3C04e0Mj6wNXkx0UlRQff87xAf9S4OcEP6v/614bCzYqNvKl
TX3CFS9a8T/kiSYyicUOfOwnwnCvIYgtYJqE5T4uFnT3GCh5jbNy07zjkbruXkWFmFFUw1P3vTQx
s1W+c6dOFuEsmnDV48qTu/fJrKom66KxDpqA+x9wX8OgiGTb6sxlPlviy+pWUyU4hfMduoH7LLyA
9Sq4iylXY6ZHVSBhyVdbKcCmrGyDAfl5KmTMD2rzjwRVwQgAvF1ZRHijAE4/sZkztYnJAGjvfX+O
2RZTIXf5FAh9OFdjqSvq8FbJ9qURhMUylYjXhUQKb6uIiBs3ZzTBGLXrsRCk76bx2BQC8lpAugWD
Zfpx3t3gLjBi42xX8dl84PLvb32QkPyPNW6T5A2oek5GwtPvM1VxlN0xyee3wmwLah3nQU9LkLwl
/R7ywsFKlP6m9TghIutvQNmRCwn9bJAWcJeDBknNYQF0Vn5EzQQC+wj1S5i+qKGkSZzMhuBz+WQ+
SRV/P8nJydi9XvFSx6DzNGJAq+gHFLbeGDkZUwb61FCZ4R07Q2+xU77q6Gj4LD1QJ0b7KHkKlST/
tmZL0QS2v6M9m5jF41HRGxUxYU74uDXlOKpweHMqATWYpsINfx/TfbPQdH/54Gwl+U75WHsTCQuu
weJdN0LXRu8Ym5mVMfK7uwLfyeyb6XbzjtGn41rp7K2TtTA9UtuC8KdGfzZJbsLuhsuTOtuPBP6X
/CJIqpHg3nVAEgIfMUXMhUPmxp34076M2SraNOyOpiMj4AzZmGGtEmcpaWSYoRvIuGivpeH+XCp0
E4DdjuoJOcJwSIv+fKx6FIH2a0yj0/ARpHjtd6QfK+WfLhhxBccwDeB5ZjX91fYEaJiFpJklEQRm
erbM8qBp9R/yR7nhxS/liqvx/JiIbCbROjYKvgmZuYj2Vsy4qJav6dgkPf82onCki+1f5sLjNWnM
WnfgI8k8SoeMzOSHxjp4fwtm6uOlfjZ9+j+7T+2vJq5+eGycDXZtJyhbTa8sExgNrA37cxONX4dt
zP6P9ygtWjdxaFYkTaJdPtJ2SP2BLc/1J/bKBQB06VD2aUGpqYee+z7ZozySyY9/krQV7rkzpXzB
OKFnr0vv3pgFIpY6Qf9WmvS4T08sez8etFRcZEusGxeIWVSRGFHEFafYkCsIJ6Qs5snNBXyOqL/l
E3rzb2RRIIprRCmx0VOiYiRFMRjq5WWLHA0cnK8OwhNwuG8fHkQt29maGO5RoX/bMJbnWR4XWRgN
vJvIKIy7d5nkqxn+iYWzf7/W81G6Fz3YoyAULWo7wtVWjg8FAv2hWmWoLOGtoQIQeYlyPzLdYXia
pnriRMGPqgJqlKs+30ZwC4NHBm4ZN7a1YKAJvJ4LW729XHjSavKhlSnDPyN2NrEhPjZYon25kvrT
Y9UIiEKJA0G9OUHu0laIcInE3sk02GfR4G7SHiz5E+LFTPvgPsGtnBel4C/BjXfmJCCFWHi0pZ0/
Ez+EcA6M+TK7ETeyVIcHScIZIeavSbZ+cpQT7fMMV5y+Q8PtkFqjGaXiLciFcQ21hB53JX8T9/GQ
1QkSsensGJbT5ozCb4Fu37yVWj6aRvu+UTFTREDL2CfrYkIHAaIXvLEPWLTNNWRdXZXwwDl6gy6F
LnuC5/ktC15TSDKOye0AxlGFiQ0gYPr6xR2Vf4w0o9QHNw6M5tr/qYo1nJQfJhcf4x9BgGYgORrU
DrCOreBkjE0i3to8SFEfZXIhSqOX643x5BieSdpc0AjSRIonhMGlWZs0ZDikvcfgiq8otT0W9K7+
M4G5x1HgmGK6yJUjp7LHeEoAKv2KldX5rrLxq7lfLYowoQfWobdjkLDY76XxltzM96FkCJgcLb3j
oVlSt2P0ONK6kMItiCR3ksotybMRIBndgikyZ23QZ6clDK/sRQdYM2PaZsKAYA2sP3ySJhNPc/9v
ingmy9sx91o1MWE3EoYHlS4NT3UXu07I5JWQYd7N1Epea60eUnDonFDDSATlxx1rjEPa+sQD4yfs
YebhNA28cQSbhdMSLlYJP1+uaUxAhxbMPe36dxdcMq3eM6RoXdaGxOVZogOq3JZ8IsjSAPsE1yzS
GZ0wj9+uxpA0o5PUB4p6qTjo5LR6oe1SJCSwVsB+FpIJ6JjA3CDEw4SHVv+zcND7LhufDi2gSJAq
S2dc9vZr2i2Mi9oVkZCcA59SL0vDEmvz5NVk6mATmnvL2sZPM0/WMBGKtcO4PsryJeuU23KFQ+6M
87aVZztvvRPOBvW1M1zok8Z8SA4xsYiHQxc3GCph06k66YqsIlyZLp6EhWEdiOGhskSzrnnhbMzP
37tZq+2dk9sa+22w1Ux/8ACVwjVw4vksk++NXTc5jvd4CMqG4PAjTc3EMQ3dUZQmhvghnl5mA9x5
ciRA0ZUGAtE7wfqrN4LuFzeO6xggKn/y0gMsOie0a5e7xV8MvyelzNsEFc9SBVffBEXVnLm/dHIJ
YvDIMYizELR6K8YEit8jzJB21OykWbEh4zRF2YqpjCNkPDPl6SNIofta0CdRJFqqbPMC0g9zhkJi
W8EZyu8IcY8wkG6c4GvBSv9dw9BTYV7DOMX+MxuBkwApyOPg0NUPY8xqnEA5ziSeFmmjiy8iGfM+
KQgNmjy4SHdKgfO0QwrtDWX7/HONjHtfflGa5qqrH1HZ8UBIIrLL9p6lBFAZCU0KCX76kjnUQh5t
6d1QU/1ccLICMjJDj3ugiU/zAhvmrYFfKGJ8ugIN1pTXgiCHZusVE/Se2H/N1jRz6T4SuRbIbcwn
CEvEczGm0fKRt8GHRjhLDTRVGPMYgU0c9TeJPvDndc/KvGtpfUZ/rM1fSItENlyEePlCoXYTUZoj
nfq+oa5J/C2BPQmXIrdSDeQEYHMIZKQWwLaICSA0/1c2nCdm8VXF8ZxjXqm6RjsrhKGDi8+XdFOl
6Zd8Avf50UN6byI53cxoJJ0yVtCsmowhKU4R+niYRvykYKLu/T62UIzru2onMNWUaOIXfUC2W96w
RRNw7azrRYMYfpzHjrUtL97rhWcscKAMoG+R9KQyT7xggLxed7xqAYif+W9p4zwyHhnxM4T9a7hP
qz7YVPHBFQ54ilauJjhbJZctLh+IsZSwqqQx9tc0HRIt3OTAOD9QNmggnfDKZBv0DcVDahNzRRqF
0/xVwXxrtpoJUSx5bXM+2Em4w/BRwZ5pmzNt3989tkNEI1MUO34tsP2GX2CM/vg8E1wM2q45niJJ
quDKwyVHgM8AdDCSFr3bee4208GRPPBk3vyemgqKnJghmeEuEJiPk0ueANVymxJ5utOxv8t4cYol
cx26SVwg8f+Jxprr8A/LPud6oPY5bNjQpSFqe/6kqKlv2u0+y8pFbja7h4hPCVOW1pqFVkGvq0cE
HL0ONHCS2c65y+3qhmwzk9f/Lcg2GA9sl+NnbURq3xYz+ZgFsbs4MipEINgK9sCQpgMNVJYl0lFY
FHosyoMuMybS8RkgqeifirLZ2PyqldBbiJFFeVjnz64Z+vh38Ip6Y8CTczkyQpMfquNiu/4XlCGC
hXF1KUPuvuY+Yr1Nl+AxVEeZezr/GcLbrpqMroB5pK9Ejv3QMUJBKt1l8kfT51zgTUzzezucgjsG
SFVt2kmwF1h8Sr6tb9ajfGf7bXEx7ZwIrZpVbN4aziJesRCTlF+Lb7a54TSKW1s9J3aK/kVnaPVx
OWChLxgy9hJ/j1pu5GcvAMsEmsuqH27oHHhRB53wfwDi7/wTQzExrnZH2+dNZIngmSURmIlczZCc
eqDsHIGxI6PLdP3fA1hylIxtK3cdx0XzB+BkjqDtsMMVFMAiNA1N/84zRy75SYVrxXzoa9KwkXrQ
UnaKvFA8dO7WXULRuR7nq4/0q53yK9zheCL2oKZ6BLDuo9GOeOIAf/Fr8rfRLn5buxGz1+s/hOZL
CUopqj21O8t2Cq/F2LI8+TZGO4oLOzJq1s2SinIju2RJMdiEDDG6mKuBgPSKQYkmvQhx6MiC8CdV
fsomk52O52mrzQ1YLgyebt15ElFlRTJK52IOdBkNKdFHDNIlu+/krs7sn12M530k+UTjDXftDyly
08izQrs2xgTV4OUtxmx5OeY6cnyMTurj7Mveiy3EzRm6nGKdzZ78ENBFHHdtx4PBoPNdBCu1JOJv
/CUWAKpOxYhsDfhK4R6EWH344sYSJvCvSvemABUw6rJCWy2gQyKKBQZLczks7sexRSlBMIHDThMi
VAatzRA6Hwz2yhwKklmulX2E/rCwP6O6WSzyStCalepEZEsSIPjMlZAM354MupdWuD+BcU/9k8Ro
axprf1+pBLppwH/zFileHduXXZvWmWftmNBApNJvtb4/CagUxqSzOBHrr1PQvhg7JNDwn20y1FRr
rE4U+7MJLrh9FfcbzQN3cmPLmsVdm0JwAvJdbuxmi/YwUCdfjGHs/IHfDCqkah4RoE4X0413u2ZA
gBZFO1sUlAMG2KMaiER0XY74HLcHAV9Sm2EXGZc8dbIjodzoSEsF6CiW7XMy1FzeJWCGx5GA5Hn/
yU9KUBM3I80/3rj1gk0GBVsvTQR83yVWi+Ha9CwTMpjfMZ+nANXlU9tBpUM2yREiD0OEaskutNuq
CdRZFEEbCiN1H4xQ61H1g7/6lhQQ+risasFrfZRMNpsSk8ySGPFX+USguiQ2ZOsoW2VXtvOt5c0f
fkq0nxHw/wo3Bqg5TsiQyVJokbKmBFcFQ83HxNRZ5auK4SEqeQHmWIIca7zkUjDoGG7L71rC++4p
jf+Pi40bhbOY0kl6sWqb9UQmxj/05qtAaeNKS2ikkqWzVu3qFzMhjEBDBeeUCflyz4wC6USROwYd
brxnBPvwYtoLpAnJ/UfEqb1w2ZuVd3MIPhX1ngl/6OSRJkaYBOlKoZMVlV+m0UIpwZSXoWlzV0vu
wb2LQ3ZX6a51w4iYFPC+a6Aw22v9CpyRHh0xA4ic0uesybJJ8WjYHjrrIoCJ7hKqlvou6chR/83l
7mgOywvwBym66nWkyRCuQ1+rnXixl0zqPP4Bp7xkKgUw0uvjbmsCNsKNS/QWOVWidAxQZd2feVbJ
sXrHFxJIzEGJyYmErUFUtM2DaDojACiOThbs66ZY9+WFrO/7PykzToEMPtoDQbnn+kMcmt7gyNhd
mTmB699TlCgrqpBM7Lkfn/TNqzhqrE33xleTXQHjkcTR12tDPLQpDD0xkv0S6U/qwuM3UedQSy5C
mQ+8LpuUZUprkR/ksf94c7e8ARO7zLY+VrTAvwb60LeDgPBrLsdzE6YhqKbtCQTSVKCCjE2nrH0c
cWbe7PSm1pn1CmfctmCFeeVqOzVsKA1jwRSxiefx05Z79jaewAsM++sfbj4ORou+8cEp0BQ3uy3E
JWQMfeIgGAm7Qhh6kqKxTEEQE99IN26SOXFqdJQeAxocQidkSRTBr61xSDIPCSSgry7NfsG66WIf
r9PaDf/QUmxdfMeCrqI4vs8ZyZbzuytg/OEHYjiulYd+N6ivJ/ul7q556taiEL1zGSDcxbHs85xx
16yTjHBBOIN/XmDZlja57199/u9Ut6h3A/JnSSw/W5FojAJPTQZgiapgeBIhl5MwMYYPlRFio205
Z+4S4FJcj3F6d3AV+diIsnTchuggIY+O8vn8V6slKAyRXPJgtSRO1bm6DDOR1oSz61BPxR1PmeBW
dK9W1EM2cVcReeB3dhqhBP8uzeD7nMl5oGtzdBQjSsv6ehtACnbPtgDT7hO7qUSjwhQLGn6111Kt
Q82TGuvoUc1n4oxYBSZTCBB2TdxewNKKpPgiTRR1+9eLDMEZ1SdiyTGCtniA6aY+BmNsaf+p/XpQ
gCm1QtRHjj7R7lB+cOPKfqVDvkuBbeBXL0w0kCA24FUTG32DW4BVCrBxgGvDIAqYaekTd9qT1ulT
K2k78L2s5mKQLujg0yIgZDXeQ5FrZmNNkWOWk4PZv+rnyovwuQ7gghs5CI/42mZOkPWHE1R7Wcb2
S3U2JCfzPj5666hiopslU/l707ildaSZycWWOKOAMbQEmHlRPHFSaOf/k0vvOawXtMpjZQvi5aa+
vzMwVahA5ug1URx0fDF7YB1S9cjIyKmhySXdzV6QdaGp7TKR6pz7bqzCGS7YjJzKy2v1nE1Zwp2X
vFGgRW5fQIP08iE4olRpS5T8rokFdXbmlP+10+0ljtdFHPTnDd2ds8YPOSdkm4NbQGpsTxZl6r3Q
hxmq/3DUPB+Gjq8Uf1lzUT4Z6whbxrcSzjx0zIuFJw8PJ1lAmxiXEzUIi5inVCJ2w0+xyi+ocEhc
ykgsmDLxG9MmRe3Ma/8GHEWedDrku8WNiX3LDRSuXykErA/4Oz8JZB6tiwcSTNpiT3geg2pOmdG+
mcJy25nT6a4AEkMlUeUJoHzGndWYF44kVcybO+y7i6rI/yP+2ze9Kx8wOA9E2edB16TtgbIEGhjU
DFFMithb31DzCnx0SRGSxsK/kur2+W+gRka4xV74zNPovPVu9+HlzfHwULsd9/uWXHq/JwcZvpjd
2Q+1u7z6eMiPFsL8rWmo5s8B694zIhq82EdY210xdfbFCWtczicwiYRVikECNryvjolpLVWt/18+
KFlPTDFHoKLEepJ6HnGOPFowd2GXaS7EV9hMhY+r1yW/1otvsF37lrN96Se9IAIgBM0W6m0YdIj5
VGCI+pFM5MHUYZl3pIr6mbJ3PP17p66nvatkwZMWS8xCf5ynEp23lFTEsaSNEHH55hiIXBcqbRaV
ugUG+dady0NVBkN2SIoLD8ocIaKIho0z1dt6gOMafqRXo2HPzOI0szjm1jDcNRYiJ+vgTt47oSpX
bKai2BpiYf7U5MRYwd8gzfmv1nOWl82GUXBmAg7kBHHSISSWMmyNdzkJZAWGJH02B3yefSW3KwU5
HVg1nzXMqDOjHOZ94Xr9wNNErBgEdznFBQzxS23QUoVECzeftswaaon7d3ASZj6OXqnNHyqEO5Ae
F7/jP8Dcjr8UOzZygS+x1qQNwJ20i+x8D3JhPbHszZAe/Zr0uHq7RgETgsstuyQwwaYeLENgIMTJ
6lWVcU3CyxCIh7d2R82WjnfMAhOcQ1tjnOfz1V4W8i9ZO2HLhrIZah+AW9OoAmYBtVj+2sRFPzdn
kEn+/SVo8c1xyZvvSZjeSkOiQCZiNqIHJalJIx7CGx8qCT+C/+vRoqPeAMpmIlJw2BS3i1pJZBPn
PsthxMOfXJyVFu8o+AVhg4en6QhXOMLAvf8xUQ/Ndd1ZUbvZaGnmIYwcjJi54KBdDq4kzY+m9vK8
CaXOaXaYQBhmkE+0kRP5wNI0uRiwE9PQVChwUuiS4Hf/5otthYkYI0gHyXJNELGmC0EO/O9qfGsw
ZqNh1D7pZ3TZz2/6PlIre7jESxKjmJFn9sCY74tAOTN6hbbw/IMnYo3ZTWLWvEA9LHLOOdw8ir6h
voOYd1iOrqe1qpoi3VlXyOCr3cw9c/G6m5DDTDlBGVpVovpTLVBvi9+DtreqDUXkZ9ejV/VG6M+x
lR5oo8EAqOEAO00sDatPkDnG+dcdxKk0p8VfEb8v7zPTKhomswcfA5QfZt2BwmtJoU5rjbs66Rn0
lKbtgiFVuk5TwP0jrZaOj2tMSiBfx37+DSnXuQhNkEumQc4xWGow0QZWxxKkm7W48JBzoRC6YOOp
6s5KXWIa0nKDlV9Ntex01yKxpZvFBaZiD53Web9/Ovr0EiPnPLW+Mw7jLgHPJRVmafc1a6k31Yo/
XOzzbzvrnEcivIMKGAwX23fe77yy0puSFQ3vbGv8f/6wB4kS7MbC4BWoz9QefO3i+AwU04kwOHFr
B5DTCxEGkkfu0HHBXb8X8C/50ip2UHRXvVG7lqXZQswFoNzbUDqiuAWzPx1jtRqbhRjhqUwb5Z8W
NlVir684aIsclRyWRaWPURM+TTVQrKwsW49xcQYwNFDil52JCIQ43lFvuXP2SQzUHeOYRZpL1/a4
BGMtyTyJBjfedYI6k9/dXF1UfR3gkXdDfkLYD8R+To3OqeojQYte+8Cvxp4bLn15eQHcPcr7u86w
EagzCvZb1ofCYA9ilOOUOvwjnUDcWoU7eFC5kJPZ+I98HDDCD6Xvp03uPBxYkUc0S07PWGB7AnY1
Gi4WhbsBlTou8JiJ8kLV0E8NuzXfh61ngH9lpixvaASYNZrGQNF01fx+1HiGpwiz1vFpjhtLyTTo
VUltQ20g/x9rwrxK2QxZo9xFjbSJ1Tz5967hARyzwXt+KQwsCE0zxDOW/CURc8REe5gDjouPEE66
7LrGDRKkktGPqxMEv1FqyFavs2AsYbLCwqHRgLR4BntzOjPbyG2fo4zFsLW/n4ETxQBvr7c/9RiD
r64ax2QNzR6ux4SAtY2GAFkDFbSTvYrcnDXpC5ro0g+P0B5Dkpyf9GR2zOm/N3tWDoAYe+hx8hS/
WnOaCSUCgoxpW9Vy7eFj03Q37ACUjSNH0IoplXb9+ypl+WpCHbDRMbHATjuudi020fLQDHtExT6A
kJkj3/7jcms3Wcwy/G1arlb1eFVSIS2TzXsCoJ3gsPZS+2GESYLUpXAiktjAq48STscbRoWuK+i9
na3uIB4n6g/BrTKS8wIw+d7guCEaR6xcUnAm7shk4TKGStm4kq3GghGNBhNTQIhdbLhEm59lAx9g
6vCZlbcocSe07RTroQgJ5oRCmLiIhW4qIJOlOIaOeSyKp9RWkOLwsRfrnNOcUTqofKqbZhR2qelf
uxTa6XmRDY/WDwn504o9Cni0yC8qEoLM01VQc50AjAkBQr+RinZUImOMIPv3mWmezW1/0c23//fH
eGiTkN/4dfEhzGFY69w2eObTzONHXvdvlq8vnCSnsqHTyk9KKMsIoWdTw/75eziucIBfTEo9Y+fg
uF9pIFNlgVurWyL4J3VWHHrmMbyIeKkslaZYd9ExJxpxNImRDx3HzhoQ6C7nefXeucP+YEeyBl+a
qyGseM7tzt3pltx2clfAwlez7dYKf9ZuaIPWuXQo72nNlgJyq1ectpTiWkUIQRmFJKD2eGUShSS6
tixu58zvlc/dKCVZiX6NQp3DvsC41YSfr0jExcyYwIbf05ZNDvwQ8rLmseTg8LQaYNV6+GKD3qs6
POtogLKMHjf8Owd0NrvcuHMzqcfShQXhNoak8JsKLIKAG/AnL3riE1rZcVGSQ+qUQ9XmQbIZDUc6
8jOTiKrKu2VI9cuT5gP6cCG1jmvaNvGuOX0UNESTiD1JsVThJJOerZv2eWUVzyF6X7CekOzBiCMr
/06qWuuibqFEHbDxhGu2i3GLpfGuY3Wkq+yzvuD90Auaa4AUuYzpSIuIIW0S5/jOacCwexM88oOX
al0bk2HeQ18SPAc2qd6S7T+Um5Y18f63yIAKLjKYHuERuVmA+rPwWb5pGtVP0vT4aE2zi8NsbnYS
7x6Nsrk+IouHTv1QHeImlfZUhuP1a7Y8Jp0IG386/qs692y4YxK10ImEsa59mdLKw2qXjVCKgfe4
lEbqn+74cPsuZUnf0Z9oaqGN4eJOo2HZjb4iqnRLHuVOXY/YVUVn38cVtjXB73fMfnr4yGyuK16i
TxNpSfH34wGQSypqxJnDdsVQ8qULSyYPm5OzxEcwiF5GUUFzRTJ7dYLW3b4ankVkK2nMxy4VBeaf
kUoJVbWfYL0pIn7PZtIdXrodFCOGOpn/dYA5W+nnqN5YoX6dDCIitxUO89vxisCXUeqel0WOIkIs
YomF8PynlpeAI9x0S1jTT3p2MAyea9y1c5c4nqTjRTlFa+kvcuXENAXcWdlBQwk+gLC4fh3kkiyj
nxIB/ihBthUiWdNsG+hMdc2OU0bYgMsF/DVddCzqRR+feYQmw10L9AejIwpNia5EHXusPsaW/fAa
rWFB0xE6RahgPBXHDoZMspGi+IfMoaAEsMXV2jW8tOtB89Y8DLk6UvGeEeH3cIwo+VUcrCjGp2GV
vLCcZhs+GU7jcusHkammlHHIayasf91eNBMG85HzqtzP7ip5Jxc25DQZ1rjs1b+czJl8qpypvIYr
f5m4p0J0fKUfM1GYGdYZAtl9dqxH+Ibtlm0DnSUDDpNe+rfXH5oMJIdw5KW+zetKp+5ynn58Bih9
vKK2umdGzVNFOd8+sN2TfYZdn/K09rLlxkUnuV1xDzyfsLGWBbarZyak/Sj1tGPk/WWqzbGpYkiK
fRmekVULTfsii8/UhrF0cjh7iJQf7o6gmNwxqA+5M4Rp/8egHZy48ckWffvtSZ4lr7tE80GTtkOm
mCJF/Ifa17L5t8jjGFmNX1Fl2ldyMY+I5gueHGHOlfZM7bIzIW3aV2KgL8auy4r1UOTmoHSklvd2
dxoSM2N6vGEmehBG9eeCA6350OkpsZCmhfVVPXDU71mfR806W+xHk14Ks8lTvrlj1NqOdz+BhT36
dZAC8pXCbrooSIzyRkxolLVSJ7oeOJKo/giyzPlkfSV2wNZHau8OMwhy4M8OSwxllB5Qr0p2vnvE
261AqEdtjuwzuk9TVGUixxD2ZtKFXr5/3YVYBs9cWG0g0Kx8sW9TuQaNIHZXJbB7DpwV0arQt0S0
KNhTrPjCry7l8+xKxT71OTAAbe33pC/9XAGZAXuTxWHLSTloAfFGZ6RUg+D7stiPNQ0Bhkih/uZi
d/eunwbccHfbxa50d1M5NNTTDycERJnPjGdFd8ra46TZ5TVXlDLJ8ofygr5jnuwXOZ/ljx3JtQiF
zL6sCADYN96Ck9j12i0REuSnI2qPh+V5e6xV+7Kjfe6BQgNEfDvOovKXVI9aTg+FE96Oiv23me+Q
eMpKWxHrudxjqCTHqwIrwxV1ELlfTLoX6uw4aNx+rDXwFyS8RQ06GyrEghOlI5qGcmm8Zt7DnjU1
ieDmU3CGWA/AnMrzZRdDaks8lT5jdTX5OVv+6Y1a1eSOrjmNYBEqBL19JC9OkQRpOrczxh2sHOhv
XuMOrxFvPZ8vR4DDFnkQUyxK+HV+7JGgpibtcBlyALzMTEt8bKyzJNJ/57uUmRN5nfKyTEFw+XRb
nBG6YlhiqDkK3MokbNwUfVkIy6WvmpfqJx7NyadtXA12KOjYBTh9S9mQzDzaXgUDqJsNj3rZTE6i
QDJ3sD0hXG0CWp0OPXsSHiN0KNtA6Am99VOcn2UYAavvjcO4w6nvNhOzDBENN+ge7/YygsnNbtIT
l5xCClDOCw4f7hfY8G6JqZqhihjQ/vvPrzglp1iAKE3cTv63oFE1obYoDPy+5pLOQbbtn3hnNUVj
MjCE1U2D8pinRYzO+cf70GrMZ8VJcmNgVgzvbgDwMPjnSLp17vPU7dxGSx90vHW3Y4Rz6WQAxYqQ
4+QDfLTf/2ovRaBRdlFyv7TQVNTmHNcabcF4/jBQuBaLtPTL7h3MaaK9OBc7lSBKzB6Tvz08UiWc
nWOkS2Xzcg/b9/JxFli/5/kIfe3nix9GaAC/vucDI72TB5lCZY7LTX042kuPQrlRQnyn7ewcR0Lr
xlGOnx29HDWc7l2RZ5kOAfKyY2SK9GjSiDk688GsWfkddDuBe14xTmiO/r52rCZh28DkA3p+0FEh
PnDi+yMhZv8wQyDcKpntjVi7rJ3TVegWotNJjJrpzjTbdet48+sM4qp47+6aSJWANcOcpfI4DPus
JtY6XpXXDymqXD6wv5F0iNBcoNsLCTFwkgukuJlk5OgdbbTsECZC3jcMia8u7pgWajPj8CbvwlTd
4rNanSWiHZYz3pyJSUv519oJatvH3NTUjjYAGIVKuM84AHjWbnxQSmK0raGt57/pcDxMN435yDOb
vnwM7HCcizO9zA0q/Xd5Sy19en60w60s0vrdoJyuU1c+mOD6vuB8aaeSdihuodJTZCYbteXkL/6r
+GRO2XphJsJchVOxMaeH+ghSPYyJcolhuceJxG6o117ydtuc/OAklRHFrbgKdBJnZ6zOJPhzxuRs
0Nx/Hcx/s/8V2+6ghx3PPM7R/t535tkecTIjmyzeXgmNL4MT5aMyBh1KOnzcIixi0gumP9Uccm57
l2LlfMLrAtH4cPHLvAa11+L3RqXc0FS50fHlrLVVrARDCRo0j6Zsx3RIYvV3HrKZ8dtuDhA7rpoS
dbqeBQizCSlJ+LDgghlSAjY7qyeEBzwS+MZe7nceL8Ca7ntLRNZSu6CvSbiDIMo158lQSsfb3ZY3
TTwzjc/Gr5i24w6CwaP3q9vhRItyn9MLZIWo/GmqKkssLR8yOUzppQyY4XXIIJXbi+jtTvsTULFL
FjdCIWXLeilNBBkjLTUWYYFJ3yPEnr/+mZqIOtXTnhsSXgyYfLmkm0mTEbMoVb4vfa+18avoOnPR
WqFKjLOribKlSOaykwCa6FQ0GM0Fd/7ez07opyg2U9ch6XuQ8Pg48TXbqqI2ZH5UjULUy1hIjRl7
NWwimMpwodfFNtP3NwJffJPx8L7eEHWNLT8+9Y03feskd26JRsxeX0kHhvEsotv/ZbLuSeAlfDWY
nXM+4n7KHXFVugSioqXctmJqjgdUjqAzXUhrF/AQWhDYSFSxY7SNno4ZlL26gFnXJpncZc6deGRy
RBNx7AfRay7nOLAiNEJwK1FnkVk4VdbXdFwbWU7gldwpjwRUIHE+9HdegBosCZCsWJ43Hic9qn+V
YVYWNyr9L336gAxgTsz3CW8mYKCv0Cm7xsymmxcEvF7byBUnHco4TWJqr6LlEWRDwy6oFoJvo/19
+R9lfi7mfhbg2fpRnNZaHPiu63/n9AVminXziqdHRSpvugeX3wYX+aifPyfq5K8kVmXVq2hdW6A4
fAcV2J56nPw+Gsar9pYPAYLvJJ0M1GtVGs7VfA7kNuPMC73zasZFXfLZDqXq8fyNRVOXAtuHj3b8
xbkW3abUa2kDRXUtOrR49a1ITDBwmYaCDOo2l93N9ZIR/iOtq5kj1QKDcStj7WSE6XwG9Sab2tn5
4xQZd47v9EcGw7g54+/jVLpusjtqJ2WAZn0t5QdwVe3EgnSRQdaUkzMjA3w55toN10UHmmv0sR1d
mpc1N0oVXNZoDp584Aei7GDoLia/vGxaOLDCPWTOfbHD3TuaMnWxw4Hu2um+K1yk7zbolBX2oISj
4J9Q0Hxab1yL3rC1rUbLvqZ16/fIX27PDH+54AWS53H3xMEpZfW08FcoZluoP85KkcW1ZvQYH52R
QJwUghNRYslMKHipwa1EzJSHjeJ71qVz6QtWepikBHAGtnS+2urvcH+xoR6lnwjSh/wUyaqgATXz
dykJ+MAQZIV7x3/4v+j34oZwJDwSYcjMy3ntw7zjMXtq1UTAtM71DDYhmOO+395CBX2ZIaWDKFtr
JiS4dMv2GSwDoev8zT7qVn0EikM8CRXz7z9JFVaxqpIQ1Ibsr+TWr22AG+KnRYx3HuMFBy8jphNI
+/Tnnk9oZIL/uN/GsdvL/mJq2aSzFgIT9V8ZlyXfJlTaDUbvItjnGtufkpaYYGduDClOZZ8xcI1B
1MTpee9NjFDNXKM4E2pVAhoTMZG/gZIWozfRMeERveweO7oZFJ7waBsLiIRucenjN/xaBwsCYMEM
iEUVCgG5ltSYPx/BBXdrwn33clsPiWwW2i3M3tw/EtjsMfR28V30Po+kRKla7hbBvrijMl5gLcMH
KC04H8p6EZ+noDhksy16RnPCeka/73kwTTcgiENdlCHDJMNgs26GGedMzIlDyPI15c5I2q/GpfSJ
4DahhgX8lEur0BLwA1dZTay9f8Pu1U+8M2MoFCbfmAe0EBCq0D49BX/Q9Cqxt4jiI1jFGdSAL9rY
3DM0Pt/S4Jy8+3RdRXG4SJU6JJkhby1nDimyzrJ6UzWNlvmI5uZLMTaLRV2Sei5i4I6H6aUhrpZp
TBo9NJB/T4VdH+SxegxL08KltUF2BDDzZAp3SEv5n/84YZePQvafXikgQlIFcDt27EGr4UGguRsR
JwNP17HZjwHs5iZfLggDivaq3vopH5B3Gx2j4hUISeFhotOD42jvcyMFkWjTc8ij0UxFL3IPbiIv
gRQ7wS4aJyNNgd+paazwvby6jcUFRgSTaY0fNiuCVzLI6lq7/Vmxx9OpVykXfzblU+HuYRyOydkF
BOw3bjvyLFK0kG1CrNZl3eeT6svWuGKnc9xiz3h4Z/BqbDJYpqDe/W0P8WUIUBxdKZqI1Z72QeVk
5LkX+ElPva4oyDYdMqUsfu3vDfzMpLwGOCTAXbwZoQMUBo1iR93ZTqBYYDglx1yvH1laQoxdof6d
LWdyLCWjFi1zjX60sW514BEcTclNEANMtttd3y6UUaIZGGGk4darJFZlTuWTDwOtZ+u6lLAUPYLA
Q5uNjMzb/mFeH3Sm1GPY2bJgg7S9viYuk/sqP8o1Stc1BCSzUVzJgRj3BJFdIK2kMYY0R+nLNTr5
o1OH5n2i99YnXcZ6L7dD9SFZJ7i4fvHfkqYLCyroPr8L5L6OFiae00bEVWC5sb4pECRi6FDhjGVK
H9F6FLRuRYdGvUtyBnaxVAv0hq8gpxg+wyd30hD+5T1++nDEruwKtn7avGlAEWNNtTby2uAot9bc
RNoBo2mdohNdf5cbigUxNYgO2A6bUQCF2LyQlqKngOGner2ipAJ2WVMosiQ+ProkPSKnPQFzbjUj
kg2ysPZ1XiPmWMvUYqMJmiQUP6ZZPan9v6+rgwkeJ+goVYAJKALCnulV8Hh7uNJSCXSIeh11Y3ev
Dd4mf+x0VBC66QA6afk/R/Ac4QiMUVDKebaze9uPWU6Ute0Qifq5JUaBvzpckkGgEIJgpQvZrMeW
UJ/CgRHmCB8sOCXGGjL3ka0HD5s5c9L+0sW0h4Yg4WsM7jsLHs4Y4I+oRYqwrMiOVeYEjy4ek//g
khfAQoIbs/8kRRRMpD7DxA572aTd2g85Hev1TqUInOoROTcXW8QGrHnShgk99U9olGxxM3MW95fb
bdguqnG9TUDp/IoY6Fd8EQa1nV3HKbyv1gqQumzYJOQaj5YIjYwmqgndrk9wLdvEkmkR19LsI+PG
qzLhF+xZWQoiENWpcn4C198EIbPhKEKtZy/WLTiXn8e6rLIVIEHA334LkLLSofd2CZ8JK6C0Lk2h
ooFZhTEvlqvgP4YAvj3rtjIzPRKeTfaFI68Dc4JdurYOfeuywLK0rhIXkLDrNoF6kzTUtqs6cVNb
nHAogOBOOjydsB3bdkKKmnyUCuLm3D6kzYyPyuxUqVFy7v7sI0xxim/p3QBFsLT2dt1111wscDYv
jxOKTG5xJwfi1KcXciMGF/s11hf8pV8+UBOPz9HvwwUdejiqKwgZ7pQnCn9xIS5oyE/r/s8x3oAH
vQxSMvpeiYWmMvuxYeOw4j6UYjmapJmZ32LyRj55Q3ql34voDLQtmHXSbZda3q7a9WxNlPSO0c6P
pXVv0zi4UusFk87sA7RuET/fGz/Ev6I6699NwtsTM3g3J5JPDILL5pXfE4lW1ubKfzf/UuRIBML/
WPALBSjspC9SvZT+Ci4bysvAdnkMHoGyHVGuuC72bJ8k6RIa0pcg1loPy94aCw1n7zjf07RjSBmM
NVsZUTrnUoyhFY1QLuPNjCnq8dXxNIJSJbZSthDU2VUqrOUE5Q158pis4Ia/1I9LNcwC4mA+EUtw
xO8iMsS4Ec6CIDKWLabQimyZECUHDATPmNU6Bdck4H4RCT0mdWrFRJTots2KUAQr4W4OvYla+u+8
m6tGFYCsw5uss9lGV/aOzki0RP/s/FkaRXU7bL701deCddhaiRRyIFFchq9xrcNdZIxH1JsyidP6
EIOELVNiS+uhIp6Shm7DCDr5kAFzR31Z0SPDHaLOP+HDQyimgaPQu5NnJjWXTruOG1UMqSCQtMTX
zmM7yFuT3p945DfCyA2WJ81wMJcLQ0L27aa5Dpy1lUK4cZ4+DG6eDFqUmwkfF8bT9uh8XCG+XkN7
JWrAa0qcOrwfb/Lt4wyagTS+OoBkx7Ag/QM9LS2nlsR/0vyJ5+8pflpUzUNntASOxxgqg2XGDUqj
wsSIEK1QXzv3EURAJH9kLTCLBccSrx17ug664kxkAxz0t0FvqNkMc/LtJ5vzz0HQYsdGXpUggOQV
cnEe5Ar7/+yrOrrwKJ4Zuz1luaIw6u4Sc4+HLA8lRVP5H/AMGzmPg2HUTnyD4trAlzlxzv6615Q6
1e++x5hL2NuPrH6o5AcXuiHYwGoXKb+2MCCW7LIo2ryeWvuYH6R9Eea9ihdQuFFy0O7qJz3zVRjk
debRlvZd/k8AjpEUXT6JG0idEEXfRKnp/0d1T5b9bnyb36qrYwYrySYzXj9zVNSHEeGdS2O2oMsv
pxSPrYdrmX/xzR5WwNntxsoBp8dzgpuKvhUkB6GS73u01ckscI6p3GhAJksvc2guBpA4UPvzFZe8
TU6zeUtc41oPZ29t2ohgflPhkXcxvcMWsHm3ELjgtvZBSPuaGZG/iET8WJCSbhXOEQ2m8wF3bStY
rhI7mHG33XLpaGH4FQIOjuqEk6A2647KeOV3Qd6aPp2y2ZXg4nkuas7kZvvAMWtHdiENnfVHGmcm
jiVOyK7fLKpKUp9r2n6xylWRjE4BFfdNAoRG9n8dbMnlukfpPq83sRXndwuihVhPuO1c9wbOfonw
pPEMsKFdHmUOhy9OZUyDd1huAGdhtJiooGoKBs+o3oqK4VtC0gNQhcWh0pM1lADxNVqgo5vRGeWP
JFQCeZS4i5ixqOf+1HbVJ9yTi/aHAUEslNTvzFhxHLfXcLOz7CCSz/zrmq7gC3I8QDSQb+KdmaB8
f2zSHEHmtvWRwQodkUquj33yFGVS7F/3qdRZg5gRBOLiZWJ8M7PLt6TsHdujuxqWWbI3r7IvtajL
bTWmPMPu6EinE/FNNqgMzqTiNxgEoytVpIEeDvQTnzpe3dBvQPNExIS4LqgGF6PniSNq7Jg2JUBD
F4CoKhYl5coUzIr8BJ3zrGWNXon1kIQMz9MYwyT1ghjo+EApMZwM/iP9Fl+t6HU3KLkn9uzr8Q5Z
HrVeIknbtF2Wp2yyZTbKw2swwTHMEAz2yYUhRDxALVKnw0Zot+ao2j6rcZxJ9XtYqhZLMiWGKYs1
N81H9QNAPW2kCH1871XfxKSHA5Y9N78fsbh4z9YbXKti3PwBDJnFq1YW1a9wbJQsgWLrccx1v/7V
44t5NvpjOj1tv7LyQt7B6pjanw+hvYr2TIzr090nHaFDzMMirBsgqHx7cGDevG8mxSsAeUkPNE7j
/WUZHEBc/c9azL4rCZSD12XAvb2It5E+sjGPbVLh57NzCVPjePIHSewKKLOEDW2Nv9F7xwqRQ5c5
bvcPRp6XvcZkcK0x2IVabl+c5u7k86CmJAvdxTrBkeCZfegylY8mx3prHy3IJm92S/DgaJvOwpEq
j6t/Rlh9I+qJ0l7nu0fUWaDFnEzyyoYjpB8eCANouh3k7YKtBL9eJQ/Sod+QU2KHayvWBz0U1V0M
dXikY12QFRzNlizxoRQwzC2Vr2UvutLEn3JDFZcUjq3b18+fkgxY5Pdv7ZF9VR4vtYyE4bixzFQw
EYTgEbaalQba/qQ81eTLH7D8uX6hB/Go4y/pA3pP4yTVpePpOtEnwKfuLvCdncgiI9EeKRNAPF25
fa8nZGx2Nz7tfHkNyd1WxFNGITkBMoAe0re0iGiyzwfF16c3U89M1vJdwrWX66lzmfDIcVzyEY+K
8ixpJaJ8BByUtfSxyjhhpztFbGhHAndsv2y1KdZNGwGTpAhCXHFTMDm7NY+y+a0KhQwjsaxrAa0+
ssSYUX/PGvEFdlPDNt+KX+pEEpri/5L9btNE4F9FnIHTASCmlNZUCEEFZgnNdtnWiVBoOu8cT4x3
HSon5nlKF5P7/DnZ/zOo8xbodo/FA8JnQbkTPrbMSEdbm+R/HafMNcT2gn9J6K6oatESd8W+ZvEI
+aXn6YZgCVSZ5Q4tJ/fxkcIMxi52Eg89eESo9mAqqTkYFtnmdnVAhEIDMO4grMnOvWsA1T1LrJwl
oQ90IUw89nj4Rp5Gaa/k2ozK9rzvGPPQFYQToMFqgh3HBeEnFFIgGoVl2w2bXJ+RC+J5c5yqaD2w
gCUSY67XQV92KCeWCp+DruG/xzK1in5cI/pEJBlP2FibnUlhko6sRN5Y3AS12KLHzl7E/Yv9h6pU
6OV1MzFWUfScIq95EiCdIAikfDreKTbRH4hBwwbCY50CkotGZA1WFVso58a5qOsuwJLhXhbBDFAY
wnRQ+A1Y/YEa0HquZtPsLBHjLwlBVXms/6XSz6phBpECCqVKkqha4m0uAKiDE7wMV7oyEuDvyxsj
9smMuxTn0XaaYanaGiXKEK/Y/K7r8lLbo1Qq6leofz2cataCYmnEOYW7H289lOKWdOQk7eqw99/Y
N2AAcbqiDiUiZFzNHtmhqBPLbBQP5wvR/WBuwm+wqmc6NeAKFc8RAtcOr/974+fTkglASsZaMLYU
bJOeoMac0vN3ay6WFpj28GUFWP/LBOdv4NkPlwnS21+v3nDmtnXEtv9zPWjTAkedaQOUHGaF0+s4
YsalH0W3qYzEIx7DAXwxKpy7r1oEjH4tz0M5li4CNN03n/jmhPQqNnsNSyD6jPJRmpS6FZQmx5Cp
Rkc1+SDodpEMqgaEgwK3LFuz9QNt97yNF9f1+/mS5i8GL/1mHWTtWZHZ1oApuwYc2chEekK5MeaO
FgSlaohuCF5olUeQVCnhCZSDNSzlQ/EBKve1gyY0TmHnwYOmLAX1GRT9nm6p4LU7E3itGczcvJLR
Q9J5VI3suepi+pHhmTnRkFocVOzR2BVgZw1ywI/s1Jzpc2R0iVhybp2fVsHrpVZi0iHS9TY5747l
yrTbYjCRIidYAv8MZCMwsBQxKd4OV32p9BskWBBMD8fPOv5Azx4HfZz2T98BbFXjV9oMOmmj7Qk/
s2znPLC12x6JtiIRUgbSRa8lWKwWpkED2MILewbZ/QA4mXm0eH5evuDxRtVW7pmAC+IBQoUYtmJx
hyqUj0XMvhFkRK6eQ009nErv0jx9ctrZZ4YVYh362SiFBIPBrV0t6S5TbIiZzgXrmiGAx+L6ecrB
5I1V10i/2n9sJpjyIBJ0QFqqUTOkMTuedpWOv4VGuv96iNI4nChR1GXyEQuxwzGdeD+HH22/bFlz
MkaEy/oKN7q5BnKk7Ue61kVstlHSW9IjsWik91iXWinBCi3lApOdOoQnsPGP9NFNuk4VNzBfGc7c
IOB9Sl6iKz/lmbfZbcyWw733evYXxD0A7aIFczKLfq5AH+xUxS92RZxHjylcBKqnYaKGKjlegEma
+aMYT4cAV/p6OU9KpOWahYQeNFTKicyaMzqo5jqmkWKuIY2QCaO6Y+pbnY+SjleRIFoqk+RTaJqU
koHsRsjyQnwpPVDtvwlYUM4c5r2iWl7QkLxjifHVqhNlHP8xFhUMC7HSDoVaD5eSMd5+tlUfTKrh
sO8Pk+Vhrfy/rHg60fIGG+ZzS1dfE8RMy1cMITq3Q+n0+P2mGaYDtD8eXBncHnpqOaiTgI42SytK
YIbK/ZfwbbInOjOxxMYy3OyfOB1d8Lm5gK9mxwOahwTf/wyvmWw0dhAaI+djrPcrfdClwBJEWTIg
HGo+Zwn5yh43rO51L7TuOrIgbpXKgip98ScZT9I9QSC5jWgKUVxCERo9eXc/2R1cWWmC6Nd5LTyk
gL4RW6ZsNt8ZBwJbItzfTb3/eP//YJxPxNO99sR2xllwEbI8388nspw9sz0+opwFiL/raOw+LQO+
UyXakXbbcjS4A5iic9vGOS/e3AnQK82tTGe2eFhrVGClOyEURBoFOBRMMVt95O7dyTq5YrfZzX/0
Zi3bCPe1J4TwaIhJhsl2LVtco5AvOfBo9tguhwb4NBiy+jn2vIH6d74TlvNHGxNt0Sekx8wHHFEz
Fu4ncFlR4qH08Ok9F1Xj6zLGONwMeu2FfjYEfRMJXtXEL9us4zY0YUYGyipihClSIxYkzlZ/eZoG
ycJf9An4U7AvS9irc+ylDOiRcqKrsVZ8jeB4nvHt69CB2y8YnjKDTtrrSYZnJ+oBvDFmjAGw/89u
qNtUAcKs3uxmmhtpHsLxvTfJQorGF/sBUhik8RaPrUDUpVv/38S1ZAm6YhjGm9Dw7eqJyrYmgjAJ
Wmc81kd4wFBXdsPMuN4cxw477nCeTIWCj4wwojg2uCeNpipvBE86ITGKacQngXrnVYUxRT7p+kva
XgRdG/ofPluLNI5Ypu1XJGQmjtA80EG2jTXg1BuDofhPvTAFfG8Q2bxG8TQ26r8b5ek3dN5Z+iZB
SYpch1FA/7ARBc8CgI/TqWpRwEUY9AOy/U39QFc23gLVHtQESvqZw9HD/rww/HADwCTGEID+Cxj7
SWoP0IWdnyZnL70Nqm2KLM6gGRKwArYGxzs4LxuLYWtMvozTtwbhR2BlTbhoWlRRSJVBKSbkswEl
qS+oy5Y9gTtCIffmbWjyGyrfp/vrrCjRNR6VzZy8QQtIC8+T9TVhsI+fIZ29t7y+K/lFgytej5hr
7xKczxPBV84EMBEkAudz4DkMvwPNxmuyfLkOKUhZZbcwBt/W9nUy4xqMOfQA47gON+yKvdunnsjW
S7ZrYAXZQ3Am2NyPECMEojYAGuCse27av8HFBy6izihp3KlQlYDTjui0jhaNmy3DKK7Y3b4uOnUU
953cZF2UIIuysgPuK3ED+8jRNblDIw59qBkUj2HlQB8Z6NdQHD2JtEP3MCyVJ8OJeUN7GqSdG1vV
zYhuJYPMx1DoJZ+hv0zcGt7QzMfwCmN/WHNw4ZO4yPSvlJk0RLxp5Am3jUtnXk7oSi/H22pnY/SH
NFVCuIikLa7h15KsBHAzWFaPn+eIXrIVJ09Md0AGt9CH0zQE0kuXcYF32e9W0YbXxeAZTA5XT6sk
vzT99CjDZFVvFlkzniE6ZO1JI5Go8670mdHG9pP7+iruQ123sDuH3jR3JpqXc8XHR1T1mGh3QsMf
8cub6HOk5eX7NUu3Qtm8m/bA2ECsZzlmHq3XmdJK3nCCq4qjG+j2lCojqnjUhWZxor2eBOGISVus
0+mF9n32obqsyN5BCdoseztrzCRPg9Rdf9pO7quBB2u9/vXV2d90OGVjQxgV1la/T6SveziHH4Pu
cO5PJz2C2BqnwuEvvLMYYtwTnhoK3Y1inhptueA7pvT/oF+t62MQlPMd2m5GiZTC0sX9CyttS2SI
qpMf2ZIm0WQOyqNqglnbINKI98Ze/5k35Nhl1xwi3l6MSpdmsmMtfr/yBVlnDwHXqdoSO+V1bJqM
dPpnixkEFgXuGZYVtniOo1Wzybe0Swo/Jrzopo5DxwYzugz1b+BG6MuhYY7ODqERVf8WRJkc7zx9
KoIuIfvqWqy08mRY3/aD3tp8efmoRM2WelZu4zjsp3L09YfMmcSm1mtDWpjsjzZjJRVQu2VM3Y/O
eLHqjtyRqsGE1F/PHPRLg6opRJ8xSaJoQ3jdaHK+PPzTfUYg+CEDxrDnA1hRU9ERxLyXDdbfhERO
CjlJXtJdaC77yexvfI7YIY1RbcSUD+BixZF5AJdDLbFb+3uxpdLoOBNxTKlM2uUGjVsbQuoF8eKF
n41GI8dQ1qgHoLdGnLpVrvpY4IWOHqSmk+Y4cVpKRX3bzi9taVTTgD2SOLBOdttCqBY9I1fcRz3k
QKw8up1nMJGTEN3WfPSHmb0fMfse6bxl7dr2BvpSZByqlQoPYmpie3bkZnyybB1d8LACOfp+XwBh
8s2TgzoveBnnit4IjuDTiq0/0APg/gnpq02Jz8kJoUwDhcmVl6VxeGzL4bRCt3p8udrHb2w5fyk7
i/M9asviiIZcv2UYqJLKHwE+whd0l85eBeA9m/DYbCHimXF9DCBPd2zTa2wFdeemgdNB3GDPW5Uu
rHhhgCtJKWfH4C8z5ADo/NqgB3X3Y7hQJr341hj22yszihJEeETpBOAZR1gJ32YMk0yE5voRlf9t
7oPKNA9ULoQc12IeHCSrAdjY4gSJlLsvze7OjsOxIl/R7CXiQb0aG4SJORMoXUumiWYKpb1q7m1M
xDnfd7K+uaNhcE04bbtw7Ve5KJ1Oidffjk9H/V7ivNcyp6Rx2qatdOZDWsYGm5fHyHCFMWd4rASK
wgAiQS78v8ZzNSq+zXS4HwPB/F3UInCsFpXEJieZ37eQEB7SQdxSqoZkrp9G6O/Wn/NaLuWtvLmu
ZHQWginlqTpav9aJNm5mJBYTz3uq8mLybSSIx+jDRma3KqAPk+bJXuTInVYZlPj//Pi8huBmyP3/
abg7z9ch3ih+3wLcazdWsRHzFYv366Pb1NhW21W/F6eYmlhwvmIhTf+rLl1gWSNeQheurp4/GNjk
wp0UnATv/9xFQEHLu257wt+Alxe6S8c25iYJgXmNDmHvV7bh1besMeFXuWxXMaLxzy/0VtEKnEys
rQ8vkSGZaGOIif+0rXbhYwIa7J8ntqCgikQ5IU3oueZc6Z/LNZ4agTLAEmVwbZKivxQu4aGL6OKI
k7ewa3BaxJq/NC7kklPQi9fy9RmhIKHM+377c/D2r2876FI6JWZNrLi02qmzm5GJqT2vcjEYAi1f
0eZ7Djlg+gViEMX3ZtOeH/PO7uYos26NzUdsuajmuxL+WKEKL26BF7xZv2w6ZO/PtvpwY6wp9jB8
VGQo641kZ/qfR21Jr51Ds5XaL9sqDOkG9dXKX+gS5PxIKqORfrlg8xHEerWXaaect9mAjn+suuAW
aOAE92Z+NUDTb9DVNIAX9vIbCmZgxmUbROYhJ581GnmqUEWFvuG0Prh5ISJinMd1M6tdGrtVUVWW
Nu9wNqAWWYtiwxEdWkis4J4qE61tMYwJk4ZiBVvgsRHkjVwbv0rXKlQHweNB+NToapyvaPianSiL
QXd74H+Q0AYrFyCkKT4/YGsRNyqAUH3FOPOO1Z4fa7YQcA93ZQcxifrEKG3bYFWuOWKwjl69kpK7
M4b/cGCWxBJiRA+9MqMjcfhfZY48wRLMzkgEFconx4ub8cFo7wepaKhGPh9cDiQImVR6YasyVaTJ
pP3kbT3zZ274s9ywGYgnLNNVwZd+/lw8I7FifwpVQ3HNgd4PaDyHFlVv0Ol4x51kHt8y7hxMqq2K
4KQJfPMILLoq/egh/dRvHW3NVixU3KscW+i4XO9ueBW+qb+RbN0lkWdshVcbNYyIummyiv4KVsyz
fkz+apspYWOyGXhd9LCYDQ6DjyzVmPRkLU1KDeWPbFNW+LAXzPxFfTg6rjtExPUFNh6Rd3aqJ5Pi
i2ylWH0fxKRFYeSDTFtxAIbw3n7jvaI7K8cOIeduZAMf1+3lp6B5HjAMiaVLuYHoEt0xPkrBUsqd
ATdzewLKzLaMwMrtTVDEqGkEb2EtrVsAw8S3giLD15iDFvZ8O4VyGHeNzEQe6rWhVZcyt0VhMxSb
uZQhXR0VS8FU3d6D2uQBig7lBMvoOOFAARC6pCZ8DJHfN3ogP/IwAo1pKtETij4rLhzvZyZBLetK
u4LnHOMn5rbyCQ4RQjPVYjzOMbR8EiSjb2vToOlL1TIHyQfSeocYz5iNp+8+OKttUhDfmklAgYDD
+a1Zs6WTQjPJPipNW3R5D6ofSUTgJa/JQ7FH1t/WL009JxXv7Z+52KI6WvhNifBNgqGjK5QSdS5/
OY9Zy0okOYD1VJx68hUeJB0wT6zYtepMTC/VfW4oy3ELj9meeVZw63aohwd27HtpAlpbV7L8JCoe
gw7HdPpqlhHWdvkLl+sEtPJDZP36slTku+y/TsT3s37eGMqQBnLdWmyZP+EU1XrRI5DOvZgJejPK
5W9OprZ+R6JXCwve/eozVMAEBExwQS9BFZUm1Uu51adF43RhDamWx1JAuntsFLnyc4nNB1+FY4Uq
wX/f+lU6NXZGcrgaX/9SL4sjXOXLACdnIew9nqpn2XjIUiUjb5O9EBGKf0e2ddKVu4HtXriuki8n
a+OdjmA5HyO8Cua+s13eV4qcqbeSisp0f5l4/XzvIelw2+XcMxb44j3DlWAa70WVg0L3N99MVWEr
Di/m2yix7Qp4D6ZJZaiJxFQBGSo+MEQayLe9jwZHvPcGv1LX9kBGcZ2zcB0p9cJvU4/fV+HWlAsq
WWIBmlIAvlNwMiDZ/tSfCCDQvKnnblYLtC6Fbk2a2LHmEJlLTplXO57rToNrTyzmBtonUnCYhFYE
h+Y9wU5kWpB04IfxlhDUh+Z56W2xq7A0kbIFwxbzup3N935CcE1SlZ0dRxmhilnX+ObcCL/dqZjo
3TB4UT4DeNIkyt7H4QVT81uBRvUu5uVQV9+srgj3o1jeRAv/8RwYH1KmX2YKxeyctaC8HUa/dE1O
91CJnsInM23mIyXLWE7VO3Y0veB/UCn2VxbiLY0ohhI9YTL5KajKm+kBnMOk3dboU+eQ3/8OSvkl
qgxRan7bDaC+HaKv5tpHOdxmg1mStHU8vM9g7aP+BTwlWWCkRBFit1WDHXixFgFnZSqtmKoJi6Wk
q2bSFtNtNZn4GtsAR2GYzGH/rFC8P4h6muutthpz7yIxel+u4Ccv5J1BSoNjTEHG3NjnqyWIU/Dg
z4szvYTHqYGXYtlwQOdtEh+OxEsSEdsDK5brG4xFfJS2lsBqgFSywFWJjwieK2ZyHI1Lr0CTUa2c
SlhtiWvK978AQ1FwSdIVQ1ewlwtp/sc/iWQJV/2yUd9OIt/P3qExKZlxV9zMdwVdOJ8sajN0op4w
VRAf0B438bgoL4Hxr1aiQgqPgco9eGQWb0gjz8OuhgKut/wAhya4G+HRcUTv8yWGVA/N3DClXpsi
1tQCATFTScp2wEdAPVU2Dy15tbTjA77V56b821E+r/kal8C44NooAyf65kSVw9A3QYa7jHaDy+Xs
ZqfBieVxGuBHwFbY02pgZ0cWKvMIwzcH2bfJMPgTdlrh6Yvvybdc8QszvdNMF3UrhcdCLs87bRrK
M+FNTQCijeq6sITHU+8ZJ8uHJlS7r8a+8+Hq0ylFFUQcnxsmysSeyM0QHYZxH3nCPBBFIC426dIP
jtW5o3nMhnJex13RmmS2BqJlZXbdZK5PBFet7+P6trtcpVsxKypMUE0fF9r99gr2rOaKvA2YW6n8
uSAy9aUziWINwBpjUd6OUTkOjFBej2gSTIw8D6CCoTJQitVJWUUEMerKwODh9abomlBqJMNg0Qyg
3qXbQp7BH2qx7fR9UYNbz7uZJhuPqFcZy+NEkR0Jqi8lDl3kpPFAyPQbuoV4yxYlnnD/A2Ftc47t
tTfcUu3r9xYEjzeAGhIFyIbBrySG6ta+CBP1ubCW/KwGkk7kjGnj3Vy0qxtOoJes7Oqzsn5aONHv
KK5OjCYptrjFUn6Me/nky8owKSJLZvs9MMTjzv0LQZ+I4G+KjwDcFtULfGQ/X2AUIM6uvMa8CrCr
IcV2qsOIV+Rs5wlYJqCweeuYtvFPDyHKS8x9KPGooyxUJ0zROzcrwDkJBsbZ4S/NDF5nXebzo5y2
ax3Ql/mfMwpH57BA4puAgDrwtUlfiMRSJofz9RBQ3lj18FvbUr166uKR6mLZ67jmXUDxpLkhJ02U
TgGMPRUyEkZDbQ5ue37wXgnTsEzHbpeiKJXwT68vekI8YJR98ADjl3sYr5xGV0YoR9EZZwprBWC8
/4p/fVv2eavqOtFcuftC33uaRF6pKSGR0ySO1L/1kamukG4bI5g18rikWzy6J58piqIj7z5a3PYu
BL/kQCGV+RdSOAZr1u6RWZnNJSRnzCF/9SCD2IwlxPV0unlcLo3EHwcwSeE310qlI5wlzNW2CN7J
qxn/TgIPVweaMDVvAaRykGSVpEjfF22jCUnahXcYVtCyH7ZrNxS+t6N1+SAiacUEC9STpm/7pL4x
4VKHKx0jNn3jmSK74g231WrgAXaH8SLIZjbSJHGF9VVxvBtzqbix9ySkCLJV9MK60RDt9rtWNBZr
hIZNYJQZGnwq6i60eq1EKQFOU1aK2AhCj7LJPPgUurtYTdSXIZmyZyb2Hug+AEXNBWEy+4pAtJMp
z4KwA+Eow6GdMYn560BkiV1ad+wOMRnJ4hvEaxS0cE/BE4Lk0TXcmaMzMb4yZVgi0Vi8TYf34oPC
TB0Arz2XFmcEqcVw6HPYzQNYB1Hp5fRvYsYuQR7ngS4xa64EA1u66grLZBpKo/4OYxHzWrGcVDfF
PR/UcfI0hxfldhf7iQtPNXJ0BdPLjS+G94UkNA8kRTuhFvc5mFRselwSKnYbcXEi4fKYRasX7ACh
OX1XV3oRQ8LgHoyDvxMGkHcGRADIiudl7h5iz80Gv7yE8li9DibZU9CRD5zUpLQfJ+DUeklRSuQR
Eq0CfZ36cG5Mpp6B5xMol7M7fs5m9Il02uTz1yxIt26BnSQ01jUbHowOjxpzHarRSHOYoeBrDMe7
lwXaOVwau9hRQlXRQkKDTZdYX7tfWRIV4OBnwPNSEqRnlgO1yxQzVqIk3GKrLGeU2Cq/FM91PNtN
ZBzH75cB2nUX+0U04Zbp/rcnxAqxVEy3LTkVz3/11r97xkejC0w+ySmIUZcuBbegwUUJVpGjf7iN
ANoIbrFEBlJ8MJREys15BhWmiig5dzrzY2ApQAos6QP32do0zbuF3w7Tk9c6baQemomw6yxNPmGa
OiA+iYPBT8TNgmh7PMss8x0zgudkr4eUsej1337C2Mvj8TjiVaAkKTgHmXkR+Tv2I4X2WfkIJI5r
FaQqeVckvyC4QKh0Gkomp0myeWGRPKG72sa1Rtk271cLu4sCt4Mlc6Gyg1zEBVYoQeL7xjSw8BRl
s5R9R6s18zQVLJjmxZdq/uAC3KVklKppG+xNTp+3/3XQjLtFnChF2OjpRZDi7xNAJ8RPe3xD70A1
RXM+fnYYoCppleax4ebAXwUcPCTLA16z9es6OCqdmNSXMXcPgZan9/HdkpCgo3EZ42FmZZ+BMsMc
X6PFa5J+dzr5FV0DRmpzs4JKhAygq7nYYa8Tz375Cj7U/goj5hJ4qZoQlT+8YKC9Xy/zGyAEa+gn
wXJUbA2s5bIeh3Ejn2Dr1nYGsCA0BOzxXEdEIjuS/soHbrHJSTx2pPF0UDgfV3Ym4x1xBo88U4wE
7vC3VKuzZpzvOpVM4cGLZNCXNUuyn9uIjmK6PUJSC2pmn/+ij2OPSnfQO2mbLOPMq8NqXf+XZxGq
3Hx3k3TdLCFljApxqxSfX4+Y1FCQ0fy4wrm4ozLTK3qDTKFOpCC1MU3ccmWXmnoUc+sRrOAR3726
PFNi4W59fdqPuq1dzLKhzVxZ0o56eG9Ht4rm5VDE9XD7NC34nfFkOPyj+94EODMLVyWnvv/vkE0d
jEeVH9+JnuazDz/dYA6LkuDF6l5R+MP8tyK4foRqnHk+kCssotAKe3cvHfB87py4NmLgU7n1z4jf
4pDl3p1uWFprAsv09v7bTJi0ydiYriCFt0edioS18HFadS0I1cvZJRRJeB9g1BqjcLxIg4arNDk/
O3+JNYuQjT7dgZGc0iu4ZvjD/OBMjr/FFVWhjNZOjejxcw9Va0EVBEl5MIEjJZTGdcq9+OjAz1ZX
TG7FavI3Ci8+72o2Jh2Mdhw29TtZQvY9Q1+sJm7CXPqYxrap5XIk/lXxXU4qdcOS+9uqEuuYM2He
Ds6o7gaPBj3huyeDhMFi0O1v/AF2YYVH+9hhIx3fJi+uqa4LLHzVCr+/z1stMbvACDJj3OwP1fbb
O0lHJdNlqBj6EceNaxEOWT3H1VG2seznADI+iipsaJMygeyIifey5UUs1rWELc1eCf+BH43SevLP
TKdIUcyW8D5r8n8UBs0cGVOY4NUHgv7PCPoAApS2htdX7b5/6fPRVp3lGEXmax4bg2XPyjI6FxOv
TtyGXoDYkwDdnh5soEVkajaGLNe7MylFUmWq6wyE9v9aUdeiYaG/NeHIZHbIntRyiC9QNCoSK9Yo
b7wjgvDzyrTQZykaQlxcQuQ7smEWW5vKWpMZSJM1rZo+E1axB0oAkI0friuknTJmX8fzKIvILqay
lCqHxWf9m4YBS6j6d9y5M2YsebDGwPiauaKTkgqauowxNRuEaZCHIVLxH65m6ZsMsuz49mcPmM/+
IKMw/yvz9y9sRprArbaba1uA8SSWIsc+pUIwR9sAiWxbjwruOdMupA0aSUJI7gkYlFOam9AcdmNz
hEJkKL4haTijsxfXzaIaNwEnbTNHPOAWlqubXWxyOMwn8e4Zc/UCj0Bt0c4/4kmWs6u+gH+eXMib
/jyTiJ9RRJv41OMPdwbZ65nfXeq4ON6n47R+3TPGzkc/GOUjd859oTR9AHzaWKYwr4yS9vnTnt9P
932V8d71tyLB6F6Jq5feUDh1R4dtRlAiFNK3WDljsSynheXVHvkeKN4RqoFo43fAEJ2Vo7lUWFWP
jsZsOrt/uJcX64ysSSvqKk8XkIvOQUP0fAJIY6SBpcs+OHDng9pBh18uJduTCV81a9POLuspdCTN
0CJPRLKTOMP+bwpLRE6OTpDU+uwlyHNRFvnJ1B7LUB2pJvtzW7BZpKy1YA7laA1vNwJnwkQf50dr
+4dmkRCUVzQTsrL2KcQgIPfOoHHQCDjSboaxdcBG6ovZRRGbyr2Iupxcm+pHQbE2lhDNYOv2jMPA
QHCQDtaUR7ITsP79lFuTseFyiDdkhAkMmF+ITM9I16K1nZp29qimcKucW8mnQn9b3jC6PI5ImpH4
RDAY+5cFtLfm1tVCLnOu888Vv5jyOEGE3s258dn1eN2znTTv8JIFAB9zCBxCmfcZae58mIIa8+uG
2qx6uCheNbqlBvKSeKFfBkghj0ryrL2UtCPMJ8emJuA2zPup8ZqMaNuh9uPQ/9YKBwe8YWOymkXR
73fZqMua2/7b9LjsAjgsq3q9Hil4qk9p8jo+yTyQdILhtcaAVEkkJSAGqvzqlHUPm+tn9kc4i64h
PI3xlhlhfEidQT3wb54iLpuQj/pCw3gawTeK93W5QLyW8CgjVzL2NYJ/IUHANp43AGWFZonD639z
cAh9jC+gghpxg1bJpHsDPuSD+de865zxv8fdwY+XmwOoM5Sr5TLcXishjzTyFd27q+gq8mnfKXuo
09Mk/ZkNOLmc/uASSItD7UPftU91snwmBqekpJVQF7WXSi4NClb+rspptRf0J+wbMQe8b/pEw4i5
bhKqJB290ZkqVUx6u3/J5klV0VAd+wKa1re4si+jn6P4Pj+etI+iwaPM+xffYP2PI7hr279MVwEu
vp8IsIZ7VdcKNy6wClhR9k7FlFyHVcnGdhALuCaQDycD7cxaGAs8rYnyuts84oY7xiQJwOcpZ/EA
yGtWIp0iLRot1oyOEl8RM32gJ/aKz6la+GRX8ceuarzQbkUWgJNTwd9AqPSAo7XDfNBOEQvg5M7f
Xd1wg24MPo5CquPnm956jPqPS95HkfrmHKSlFArYl+3wrMIyFh5Zhu7qAnYWDok/vOGMVF8TaPmW
DhPoMUOpdmYKeYrtQVRWhUVcHlR7d/x/GVyO5Iy584A8O1UxRlpeRnK1HY55H0RxdltQkKpGoNE3
2v3D4UoKMQIvL946NDAnMb+xbsTg6rj0ut/jeFb5/dMOns61sTHzx8DfNUFCPIlJEqBzcvJvYXCB
wImH40iwoW4Y5h+w3kGoSo3JmlEj+r+pgbBP5IcB4Pe+SqCwJvIc37pDH5OuMdaATM07SVt8No5y
58Y/RweZzlxf9TwIe4sp1INnA5zsbDXyXi3Jslv3aW7rBn+DCWPGOEBNDDq8Lo1+yOqZL78ideRv
MaEVlMvEjkcnJGl+AO913mIx8OKTtXsMLCZRqkaIGjVZHqXGia1tI946JKMpODeQea9Kur1sr5Uj
sXn3GM2EtWdoM9auAg0wdVcebxLdwP1e0uPBNxIiXjvjhYfk5rzt/gtx/84PB+IKdfs6wtph692I
+a+5jUXTc8Bl96rShSWvX9KL6qSt2TETIYDBxXB/EGV1KFE6PwhHVimx1K0pmC+OdqKRF4+P4jU6
RXbehwpaGZBfxfC47XZZuwPedaHTt4c7234OC50V4jClboBAaCv9QS2vf1FSo3XLceHO0KR4p/DO
G/owuauJ6/MiVu2JcNdIHe4VYUPajosLw9GixR0vU3Lg/9e41DIRAnxviQrKz/2t++3kBjPji4+c
UtpYdelFbec18iMnavsp5uokhC2S6W2RdSmxF4qIP9C6vqsq+DiA19PUCTlXeHre1TOPsjDPlG7Q
xRCtB0+WwpztxlfAvIcOHVjI3aYbT1r9AJeMGsDvKoFV6kiw1sghGDpmeQKPYKH7IiIOTTiUCS5q
gEnGXP0dgJrlVs75XopjSbOf9FjPCjPGyX/2SRSNkBqjydjjUzOFQVj2sRo3nqUB+Q+Jc/s+T3PC
vvtwOFRJ6f+QRO9BP/rdJszSX3jeFWZX4S/MxPmEBhxfjo2EyUavIVozeCe4FfNFmYF8cGlJSWcY
epB6dRA9fKu+bfLIDAxxjiMcvOqiG4jTu1Cm5PbcpnjeIQPoKwo6X7EUq+5qBpKYHpOPyqr1iVo/
ZqaCWx7Gu3+vqK+6VvnVO5F98ppkHp9FzBSK2mKCXw/UxkkePZZ7kOzcynPwcEMiWB1M/5nvlOrd
gifx6IHCg1PatYmdrScaT+WubhEAlNP97dZZGexIpi7Vr37dVAy6EWYQeeLvCjMv8Nevh+516O4w
7+49+iiZf/O7QrcJRrmwl7wRbxyMNAmvwMlog+MhPMndhpa0d/l8DWg1eYeWizQPurDMCyBKY3Q3
uj8MD0kBahYUyGFVPv2ykI7bWb8UBrikYHmRqr/a3I/OxlRbu/eOEbKosrU61SFJ2EOCc+jUIrE2
WgBuZt4YRba5fNii5KCC0H4M0MpXhp3RBkYgE+fSrD/JRllBZNu2qeIlMtxABsM6s+bjn14U3U/G
Y3uiXzbM0BFS7mQ4K/1rbTocIBPTx6Mo6hBg9PjkZCL/EZ3regOUqrcxIxEV+DpRnbi1RFoKa5Ui
2Uqm08NvBvU/lSniqOCcI2k/9v8SxnF0qqOQAEMxyWktkAY2I985m4zjRZlgpNXnNN/EIbAdGmmX
mQhILHYPGCbCN7tiYTuZ9MS/RsibzFCe16ym5noSvFD6Td8Ni9YHjl4acy/2uYG3tOA2UlfhRF1X
oR0o5Qsp3nvpfxL824+0FAdHJD25lWLPPk7RbFp10ltOmBJoUhgCyJ/mZw8FLzpxQy5YdiFd4FWp
71chyraN7KTHg38UKA+yRj2p9CmZbK6pLzofFiFnSGEwOu3DZJiXAJbqRBSciIDromFv5H/X7cRg
DeD0g3PeQR1A3REbnlWrVekc7T/EebTpKAAqOfjhCTSMJrUhLHfgOqhYc74YmbTSCCSC3SdIgP0T
EyV2Y1vaA4SXZNp0Cii6iM8/fsNoeQH5GB8wuWGsxFN7cmKcIqZZVy9YMPkskrit5Pv+7cfH9swz
Z2TAgbi52PbbC+hwInqhsik6H3kIud+mFO0k9kQYn9uhafC3tBqsqGIkQGIZ+mmH7RD2yrBDk3bm
+TkK90MFaV++huEClFawdHU153uDU1QJzCcyivRmPpR3AJ0l07nbHCaVfSuls1nEwYKcCHo3xb36
DT++MsdDd7wFidH6sDxdVGy1N8n0WZ/AIp5Ft8ZhE0wrzaS/I8iFd3eR6BoqlQbEfiiAP8U1RKML
txwpEnhLhfzyO138lu4F7Ns8uwYwwmPQ9J5y7yZEhCILP5Gk10l4/LgLSI7Rw1RNmnBXaS/NtrsN
GrWae4RHOGXMIs7zVYueTJIKp5twvoemwz2I41oogU+/7jWWw4cnIXP7WSnaPv82gqhzKR4GbTK+
f7HD6vbKXMc5v9JsQHK4aU3xeGne48MKpitHA4EXAuVzpJg4F6xYnT9zcHTdgDUE72ZsAIRL1urn
SVZIsJzR6PRhqidpiUGJ4suF8vf64ZCzzBuiJTBfHSqbR+8IHdbYheTjnes1LCY76aNJmL9bdiug
jT2nzwxILepz70oTcH+Ivwp8vSfTynYSAgP5fBbb4fjH/P+oYjNZRbXP0OBwGBCluibpt/cOVned
9UN0AC6ve2v0Lpq0t3nRI5/ybHi4TmXLkiYnLqz04/tTAnDAZ05sDz2vApUUPJeA7Z0WoHt/iPKm
rqTZWxU8YMElhTCBGAaAfAXLe8EwRr7/nJdPBPF1ER1dY+skJtz90hh174ZiieBtH/qsS3c1WNNo
gaUeqnQ0mZu2jN25PVClLWfGIvITaIqr4/CFHg5IDU/wqpbHWBDY+X/ZxTjkHC9WvtTCA6sdDlVe
7BvJ+8JMkj92c4aIoeb5fnHn06s3UC/d6lSAO6YD8c3BEmXkNszWvOdBet0X9E3R8Yn+zZpwV/0z
WwBIAhlLO373t3xt2Ef98df2xxo/DXca2dHVABUcxsjK7K+kcprYvncc/LVJiv3QlrrOxY2+c6BD
m6hcGuD6C5dkyIpvzIQpdwxNPuY3DzJgTXAHve42T8pT4B3Ppq8yzZczU+axIH1d4Z0qclIWmf3A
e+HhIOk+sFVl6ObTAXPG1L4sk9DK/g3yLj8rhZ2hS0UYS6qP09KPuBsVOhNSaED/eTc+orBvPjog
CeslEJsua/TRhNl+GI15WZeoIZz4pIgbj/pV4fNIU60zF1VgWWswtzLwoqbOgxZR4YkShJ6jxnAS
vo7eKUsjI0LxDv4sKM0Ya9gFRX74/SyQXBPUHCAqNHPKrKAmq20g4+du/Ld/otZnn300oXeL48mX
RyBaeCgVSEbJW1uoLhnh7V+hDo8groGLTrOa/nZ5cNC3+WjL5zJGLFAGs6CAgN5IfY62kt3TXfvD
s3n1oCDEwb9+f1gXrhgI1SwX1CihdLLoUDx3P3u3LHGcD2szorrv/dSrB9PWPKnqeQ1ZwHBzKXRb
ERBLNHBlNs3O6hudvEiduxpQi9aobgRLpbYJSPke6H+I7hgpHiTmS/QbzvfaW0h9HAK2A8Upj2qD
Q5LoJhEKqXkhkt+VmxeVuPXISjJyHnPiElU5hc+/vtR/TmqQy+V7tl2fpf+d2QRF2H7MX8o8rYJ/
xDtmbQlJVbluFb0EBFxOTXdh667F4FDpZO43T0oteWhq6zruwVw49jG0rP3IWRlhk/5xxsz2e2YO
u6fp5NymXczzQlJothWvaIXg+mk5HkjNWu5d/LwvpJSGbIlkmaotE8lWF6fx1iDj+u3MoFlrieXi
uLhzmDSnTmKQHysrWFTeMy7whO0ZrZ1m/jisssW+NCR0nHVN7FaIXnk3eG9I592ARQYwJruzLVzf
upxlnQlz1v15hv+mMevacZW0BZ6d8MBeeAnI8bCCKbvqKtBr7cxgKCdtYgs4Ea9BD/gL73fROdGt
gZmMHl5mPEt94ycpMshjtWbhSWkvl1OimhgTURkvZBZKjOc2SywKYJxinvOpiZoEu6UoOEvCrB89
MB4jBqGcxsGxJMvxZP3aBKQ06j+huSW7+//QwHJeiMYRI7R6v4OqrmcD3rvrpPIBdvtBm9hEFhd8
X82MxUKl5HRfEkuNbwtr6pEdTxYdD9+mfYufQF+cLZIw+F047pB0tYrhTciJKX9taAtgyiJVTZN5
ur+HPLUBI8NWp44Q4zenoeSqz8i3UCWuc1DOzVzHP8il+r69oVQECJsEB6n3wX2AXpDPaxUQPumF
Bta5pZZcjltKWdJf+B9Gh1fSzmlaA3rY3P3SQStlzx1c8p9j9gON8GyI6ixtdLLtsiICA7Tzawre
vJMVi32jlSG9ZAcLD+SbRQDy4OThQskBLa3huGqxD816bMFrEhtt7XSn/XaCnat3v8stBGYpos0D
HUDyyn0eByDRnqnx/IQ0c13WTq7LovIvPslDC+o5q/sd3o3nL5xoZxWU9//hT/P7f/fOQDqLOp1Z
mvg7hgF+mKk/BE3deeChW/6iYTPhNkRYv75uU3VMeLIfbq41paIfUb6y3OioqTczjuZM4ytYjcP8
rGwZiMDMN1cW8dAy2uO5Vc/On/7m8PPlzgjKBkqVZu+9YKXsfALZOeU4WPhv3Xx9ChuhYqXyC87t
IFBcoDeje2fu20cf9ePOV9LcuzHudfTHGNEmtMk99y6Gy0f9EV1obCxojQqcS4soCy65SRM/7b69
y4g0AiVz0q9UFgj14pKZmlIluD5Ql4kd15DJbxyzLTtHaf0ekMDZgaiNtL6KW6853QGBCSBkp8Fu
eFLb3YEp2ogxZCLQDbtherduGftyAaxcc1uvNNI3pYgAXQBbkecMkE76ufnxA/xHEV52hTKPUVPI
uem0M2rOvIfW+6/WYPQGkoW2xdJVPlB/hBQ5EGZqLikfI1jDv55XJNFTw91IoQ23mx+8UQNb+grQ
vO8+tBTnYZdd9gS/mgi+oJVeVpeVCFc0KAGDyXtMOyLIjUieJW7+QjFqdjRrrePGW1D7VikW3cuG
cUaY84Nn1y/gIWYVTu46DVmwAbSg/F6BaZEdknXjmd3k0GMRnhcoQjs/l480w9DWaiOuRfSnRkvF
QPjsl1Lmp1+Xw8UiBCYD/osGWa/gtvFE5W0CNK/NzBuyPx00tfuC30yAA+Nw+NwuzQazFkCP3L6u
j/xFixQ7rRIYm5iO+yK5KUQsxIe71NYvcADhmy51ZuasqjstM4CaGYQcwlZv0sP/t53hbjOikdac
0TNfXIi4rW9l/IdInFEkdOrUJTXqOXKBx6llBxa229ILJcPsLlErYmQklpd6bsOLEjenmq0t7sjO
2UNI4+OPKZ5MfYwCmYrtfNuBrD9ipOOUzaGx5epr5OGi07PINjzQM9FhljIzN4h12hqrfmU+lJSi
AuPjLmzxd0enmpg5BAdq0K7z35OHtNcvi6p4HruiHfarax8oH1oNXJ+fKsxhZ00l0BHG9+Qjg74C
CxKB0HAkgv/DmG59z9N1oZNm/dR8PZvFmcWqALRvCZn8pzPhotQXdu/nsAj2/TMlvXcDKfriAfq9
Xanjx1VIJKP+XBtemmOi4JZJbOcljhSMMei70p6Ma4YqLCWzsjsKjmixOs/sCSc5swsoNNAa4oux
mqQ3XdFlLZUYBuT9WoSbeCVvL775Flca/+oNSDUAMFIRJ5TUiW/HxMWEXglYoKezK7Tcg3VAOTGr
8zgnq3SyW4Bg71W6A3pU1huZ3vFOn2Kpk5A30ah0STs0zKDrkJtpnnd7gR8avyOiFjT3a/1u61Xj
2AIJJfoo1jw3wcXZWEbA01/NYvFWafHqxtbheW3bmWA0yyrOxQHh2C3Mp1z1i08VvVed8NF3gVXV
Wkfc1V+LYuY669OE3VhiIQWELC+q1bMcS0G0PXcSylCdgRzcF1Dz3XyVpu0B28lQAGrTLrh4eRki
Urt/hnqmj4kMI4b7ZlQZyi7/TruuD5zkrzzF3zyGGiBfsgvqNGmzS9M/04ZskYtGQlt77/V2wivO
hiiJBNoV5R03noA7OQ7ZiwNobs1B9H7NzVr6ZTisrUFUhF0sPVCAjrb4E9N90ylx6pCe/W2N4SpT
ULM5w/XrUvgAXw8iYSDAbmhyKRnW0qYXDwBbK3BcXY7FFvfEkuMIAc9EzZQBvIwebJrmbypGVc3X
E6DbMQtEgveMmxZH5P1oxVMJpck0PnDWeed+XedXga4kiosQ0/Vca7MlRJpoYUwqoDXEF43ma7N8
JQVL5vF13f7s5FOy0gYZ+mgIuN39dJHBOKm3GSCk+rEMTRrTVjBqzONexrTh6OQRk80btulM3ASw
EcQnupOecCKbC8oLHYCSRdfH5TedVxqS1MXi2+/Wj8JZnSJ26hqyv/KarfWyOkjknZ4x5uXAm+vs
MwEPDvCsLvrb3O9WmDdAtS2fC19BY8NZuLVOdbNMtYkMqcMNGApMMZKV8AeL3sibyIkxPu9mEg/T
AXrd1ifVMK63fNqbDfF6dJ/ewryrS7ao189nnBIHske7aDZaL0Nzn6jSpAM/OgAcvUvHnM1IH99M
qNTpQgbYpRQjhzrtlaI/HySAAVP99D29JuR4OmramkSF/OVtREqQXM0YLNVp7OR4DbKCKxvwcpDt
awrfUvWA8z/qvUnSoEIEmS8213jDsy7moygj8LvJr/2ZTrBL603q3fJLWsylOtA7+VX4S59iCykW
cZTOFEW3zyaUQWpJ5d7Vuc2LgWB327EHi9WNB8aPPsCc/NNDMzfe8yRaNHzSotOoRp56839Rw+d0
tRhCLy2DAlgTs621wBqG11cZ1aVlQ4i8Ijsqvea1+2bJN7jsUFKePjp/Jmxy+OLNln89QvKReXWY
iHCqLKs/k/4KDADuQ8ZBBeuRNtJSu2XM6dnUuAG9suLs1V1J1vsbcgb/v1AvDTart8AYFMN1Daq7
Iy3Vh7PIKq+UEj0ongIjZXxB0w0dEgU+KefYCPQqm4kmZsw7YsuyHt/N2VkcbD4CAwxn6RP9qvVQ
CeYSsLuMutfp8jLhGzLSKiNaJDdaObybbeIG1hbtwChcIb0fVB3k1grBzZF6/rvUELGLaF7oYmiY
bT1u1oOWlxOWgjZj0zZyQ0bI7dOguZK8Vb9pnQXnhd2IcO7r6srAqoLsTSoctfbP4mPBUujWZgjw
DyF5cn6vUJImiCQjZdRttDwc5EmLGPYwUN2pg8YEIAc5qdd0frNID+I1T5zLyZT8Ce3HDPOUYTEz
POAO653QTc53hDbo/mqMPEEUu6RcgO0aX9AiH1m6Ek1XBPLPl6rzQ+0CYjIChUyL9dXpB1Q1kttN
a1p4V45aAZVaOG7nk8JXFKz3X+LbwAShAiwoDHWRx7ITHBvneyYNrqq40duydReUUkE/gf09gj/O
FCFv/qQsVRMC0bdFaRJlYhslGToq5AQgcsxYBNePD4sSpYy/0VxS2kNVl5bEKqS30ty1WrkV6pMD
xr/3P1nOHzlVHnJQ0BI5Qar+rY30wteeyNxsbFRZyrZIfohuDej0PM3K8DE33rzo2l5zkuPej2bF
C7cwHQ4Tz9fB/HYWw4KIaTUQ08KBI+94oY6DYfFqqXD25FqQwMvip2XfhPcxL6y05/hk23kXHVfo
QppJ6SXE8N0R+nnGGKvdUw5+A5qwm/RKJZWGTZL0/gNcODa7PMHCQFqstwWRK8uqgwFq2sBVzST+
tQPI2ZHlUoWQfSlwwJm+ClKajcmzOoMp+qB3UrNx9DNKh51WSKvOc4W70e8NcnaiBJ3GT9VocV0h
ZUufDr17OAsB+daArGv3V/VnLevgQnkMwjlVBuPcw9YaYM9UAUBoVfsUvqUe4zqHsCh0RtVHDP5G
JP3ryvB4wHs7WXkGVzOv03/heorYE7/fzwxQvlM/GEnRugP4QZXeMg0K8HxuDI1KACeaVdGsb/RA
JKu76hvLBqWWHEkJsBuIpCAwLEGe1NIDTa7O2IT8CTtCRQUdfnaTHDLGFd7SYcIdLPWqgQxbUElf
Uy7gIxEaxQFO2NddYbk7BQ3jP4InpY2y4wU+upCtZ7gOhlkO20d9LSRvFDlPWO9ftT99jQpDXoHf
Od6FWXMPnL2yr4jIyctXjjnzJRqWsl21oFeoKEReIUK7brbFpdYZ7KI4VdGXsUcsscKEDtzahKu/
FfskjLPKdNFA6JbkmJRUgP1WdUVBy6vJsY8h7J4esNfOedhoKD9IeWthMwt318lBN6VdzX0s8+gb
ldC1UoNjveyOZax08+jnX7qQEbOfZxJPSujdge8gile4SnaV8nhQcbwlGpZBib3C6ppIfRDpNL/V
wS46rJ0NfflHh/CKhTpp5/zs3NbgYTn7O5gPpkHc3rKHocmk5537CnYosNMXgOZH5H/vC57P49Y4
BgZ/VrN2yp3QOfNBvQx8OzekFV0M0JtkUsqC8lY6+DT9jPO5pHStGf3uSUHgmT4/HweXuwRZ5G3d
6hOvLWev6inDblpy5jlGEzxjQZeT73ixbciisqYa9EHTM9iHD5Bzkysj4rHxZhHcahCFZVrY+BeI
TyvOLQhwstgdFu5NCGeoYWcflOctBBu2pU4U1dn4Ipe6/MXBpBUu42OQM26A4IRnst/ttxsH1OI6
3ofy7k/V7Ds22/FIoPtHJbIOr5q6+LDS6Gw53IK6fCM3eIENlbvmKTBP8ScdFR62SMMiGYDG1yUl
lGUJLF7Kb+4Iv2a3JtnbufMWS64Wn3Hty1lealvYG1Qw9P5apeO166RmhX5oWGITFBpGQV4OANhA
gQCqkWDvKQT58T6dpvxLPp5RISbpA9QwkcV5DUxva+HgaKM4+CrTosex3GEaCxrwMqVdOKmjiQZz
x1/b0i/U1Qrh1xHa9HaFbjDGIZtNKVxd1NukgdKgak3bzFtxiQe8yZYHmQOFImPOtPy7I9JUZfSD
M/ToTZZmWpfD1HZmvu1CFHuLJT1CaLtlZZLC+p2v9u9XG8sGBspd4XM4/mm3BKqU0amJPZ9ozel9
Ior1qjNfUwebn38axrpU2iB7hWmx5mHyOHazYqYB+n0/sU8hUbnbH59cTw35R3DoONnLS8P5NcdI
SjEk0E7OI4kocmLZCKGjvH2h5qt4dD/7VLLNHhbmfod12IuKC1rfpHbKFFVmgj7jAtYTUOMA6kBq
Io+Qf9tUL04dQ+jN/a4Wec8l8yAgncs7AQZLuTfm4frk1jgVutF+K6dwL05jkGRQSF44i/bpP9R/
Ltyh3ufJ5T1Fy75bEl9PuN9PucDZymytz5OcMHPjYPKfWjxtMv2mcNkXiDZxCR191tqChRQ2Yjy7
u2KyJk3hDY6FB3oN1YNbgN5QYL+KZjmohyX93C8QlK6c9x4RC64yYguu6RjLqL774lmlhB2cBK8t
d2tfX3sD5U2mRSbW49zciXYPC9YiXaEgj8VpImacrifhMSNwRxbuTkz36hwgI0mwk6FyPbajcxBI
BSA4MBKvFnqylWoQ7ykhx+46HCTBYxcTw+lR48zEcaY2IjT4WN01guHl7Ef0aNAL91JbhoejsJ9K
3ErLoYRxqOsXgbeXKhCj1477MgxQBx1K3KcGOtRWNB20Ku+hh13IRUll2+svl0gYwqDiE1U6NanF
345K+KKQdZsfZzYs+QVSC2jdcvxSPCCVTk66sMTY2/h/mwginnTYoYq/y85HInkAFvXoQsY6JmKX
8ldlFO7omg29CccyNGQwNV+u2sAASgC8kAxTfML7SshaQHA56FDNz7d53mF1XuZJugx7aFmXj/EP
pN0ZeVcPEXviFT/9OkJwHtI/3gub+WaEkslo3OOpy7V93XA7ACSL8JWbEKW2WFFmsprdxDH4a8Vr
zpIrBHmoBw2YxDhCgln9UKnVnjNzfNS9Gin55AwTJmVa4ESXy+p2oVxxK9z8ofAt6PCgkfB7BHMh
ExjvKSxTQYJQ9XEoyj9rpLdlbrvB94yUSdw8sKV16S0CFNfPi0Bz+e1zOfkDVjBQsL8m79ttUocY
oqpv0PWGV+Ho15iuMOBT6+cVrSah4ETFqRre/G5m0ovQPjMyvQ6IubSAoE7ceZPzIHCO/hiHBmXE
12OpnoYOOh8a/0+czIqCXdnT0ZgUK7YHZIRJ7IeUW6fr5YpsBZrs0E635xY5P06xmAYecFPhwGje
+4Dg+AKJnnGjE+rljScoMTwV9Koq9/JK6rqBdxj5zsUxmABVBE3vWWVnk/0coJ6NPFp3XY8+9YTu
WZryL0ZHsFbazL58xsNvAT0b2K71eEqYZbZ7zBAbbj6WKT0zdIyWc6M81q45pr1xkbm0gYLAobBA
7sVRuCpJvVLtoO6XilNKRlMQlFgkXHkhYtwgt8gTn9o5rm6AhwwuL0FAB0TkiRUvhik/XdH7cIih
0a3VhvqqVAggLTSU81RxvDUZKqC7bp7bLAhnBKyx1RBYSJQ8+4HVDoa0fnlImlHi819VWnppNgIk
oEg1X9CptmJsIypEhnx0m0EqhshwXG3XlejY+sKTIgHWx0O8nYgjLVELW7LaZkqIKFJCZ8gMj4ZJ
/Z19FzQdYp5ynFyEZq5HFP0Y0hLdEgsJ/1SqNxlUMQ/ZImIkTQwzp4mQwfMfjFZAvqnHE4a1koZ8
r6cuAgi4S0GbFoYqrV5sHNfCcLMlR9vaRzAQIxIN6R6Tdj6KJhFiEmhesu1yRV+EmOAVnJt6kJjq
IPHUiyyIguzQBzHiMTdj1ZYaYuR+n/yKLJYUq6jZim7ozXrNdkYukXWrRnLqS6RgGV7YEDQ31bQk
0mCUYCPePAYmeAFXXWFl9cdZaq4Fy3O7kpQXkBW/ti7VI0kZaSlXjPxqerkY8g99eVLjPogFjzY9
ww9zTANUVK2PhjLVtxwt9zHkT2KU1hyNxQJHINzamRZJ2G4YuwMpJGX+dis0//G8OSr3seqCVkPO
GXadNMOGG+2fhXiopWmPf3NEsMVazzrom9aYUuU8VMnQMT4JoG6GqqmGPb6r0iw8ATOddlrU8DLD
cQHXvKmwSOe9a9qODsi00Q2jBfiVhqUUFlcQFUEYAWpZUzCOLUNAQ4l3iGvUj/syhdAg/DsAquyc
txwkD6GBTRD+jTSd+JK2y2qeWwkSNz58u1dRIyV+ahEqU4sLzBx9QG4hvIouwp+Q6ngfcpWo6JZ8
StPhiCNX6JiYqM25dwbnHc/Rfw5AwUVhb9YKZRswJDbwPBqO3Hh2g3zTmbYF824C+rA/bE45oK0k
QhFzYb5xLau4dGl3qFWukS8jZSmYwB/WsxDGdctQ9FBmFNUZ6b0y8g/lYZiVI/fdfq5kfKz5Dnxd
SwfcW8MbEvACcCQgRoeIHTnzS13hPImH7g2JZi4N/0DCIkNdIh4n6vQ1q9M9af8mZOpCRo0r+uiw
KsiSHTcgZcE9FaxkZyE31LivcajUG7Me+sarWPSFxVJQPHhZ2f8leeRt+As2WIVu3LEAxfzd5LP3
O/a7gObtnSTkxetOIlAUaz9YKP72iCMy4moQE7/QAONkDotYATQlSRAb9wTa2Qmlf+zf8opAZPtU
et/xv66C7YHhcEYDO4aHcN7nScGFY9BNyAnZPddl6XjDAq8DVoZNlb+JzXHPI2AVvq/C0r0RXr0S
uYKgonhGa3txITA76Ag03C2O3tzbRYbaYmX6YwUNd2MPAd9C5uMcACwn+1dXWtoZ8Dnjtn/tSb4W
WTyMskBsFMs09GB+dA/Ba1CPLjUFhaNLmlaEPwEJ19VfETPMA/i2JVTX05WmRC3PB7i5wtLWjHhH
WhmC/wQjfPDYKZ+nWsxoeFk99VmyLLJmaftCZbKXYO7mjMEdGvTQmXH4+NrGrgNJ5zQt5NyHAl1m
rPGweSgj3V+0HYFtW5qwC2vaBVlvWQJk/dwUYRUrRbYH4NlVBTXDUNrl7/q4heUPLDRIJRSoX/vx
SjY5oYJzURFJR+TpzTg5IGq/Bypk5jvhDsKCk53GixNQYhulDpxSlqCdpPQ43K5awEd0JpzZIxkm
CX/gImbHXGefKWruMAeyUmy/kiLMVFHPIxdiVt6kLWXsX8Z6ha6X8MXYscBsDolh9lL5+PnfIggs
4QsKaJ+v8JQhCJ7WDvYhoyo5NGuGSvccNovVQIcU/QHKgWa6AdHwKnw1/I9UxYQ/9SIlmNx7c/7s
OSCioG1yiSx2jJZjxei0tgnYynOp9H46UBjT+fqUQ1fc88zYBv+bqxPtsCsy0oOSaD8pKJuXoRLB
0NdR08mFlTtJ3aOefqXPQaRCdA8mAy0BIuiPWuwY9xH8z0uMBju/n9SLTog/fJu3jhffB5tWpGrD
bRFq9C9t98St0LIQcl+A4rYeSz+oslrCnQrEx0R3pKkV6WssMNsmX+cik1JH69zLPNgTuC4lTyHJ
rgIcdJzx9RA0uke3Sd4/XAPOU7yudKx2SBTjO9fuIq11JmXsLpiFRr/QmhQA3PavzsWz4I4HL3SN
YIMPOL3x8bSkX8cBx9XHnrqW+M4QGwMTAR/9Of31hasvFWT5nrfdqXgvCijx2wamljxpTyXX+m/j
S55tx3k88z21Ee31wBsNu3CWojcCMAfOHPQ7aYIsQ4dVyyG77koYmDmo6UG1yMASpZOCjxIZZT8c
WNgIwfQvtPFOTC10NjoGL6IbWWRr//vvAIi5QKAevWMDBAjo12Y55f51hu+xPVfxE7EMDd8XBk2C
Keeu6qIGE4Jwi8FULPwKN07L4oS2T6xX26LvBQCBib8w84U7ywwebd7viuxJzM5xltNqVACk92Az
Tllvi25bL29T4K6hz09t2QmoLG1wllsQgp9XFXBzdWT6rt31JWseWBKKwnOK8GjYSL9mWidE1T6+
G+q+Ccn31bmu9zRZS+qNeeeKJkafUO6LP6uByhQ7GasIAzNp3jA1ZRzcihXIkf71epPJWyWfdWiD
PBtvIjJ056btMqbyBee7Vlia942UE9WPCeItbatfNGqKpboN5frk5qIc6ApjLUgtArav5pzstT5j
BPB9UzR/Kl8cv4CdpYYY6nmMKyQQALIrCRMh4dJR32jWbCjRmFieDUiJhlxcf9oU5c9IB/0VKvFh
z89/lnvLWzO4GIrhFGAv2eVemxeosRBNfZhCWNYU64brIGtb/qRgSj5PXyWduYuQdQp2RnPDWPfn
NLmMmCucFDvQmpGob9LZlrUSZo0idz7PTeddUtEEh3PwM9wuNRZkdBwunrCPrbO/QlOwWq/pxmfp
9JkCScG6CqyzuZWIjC1eE+Jo+IxAxRyWvz3FMJJkkhrHbA858Our38gxxZboEACFZk296JF8qbgy
CvGbtPFkypXioMP4JL6DfveXyg1oXCa4MRUSQAqfLyXVKnIP34ppT8Y/QOIlUOMXzyVUj1H7nXCa
G10x51xFiTLfbM04vK/ySronVt0LTM2OKM9eiuk35sWHdBYTu7s3Lb0ov31ISLKqRGwxHGlz0Xtr
fbnp4WTGV4kMZ0GXfH06TYd/DYO7/EBr4Rv7chTPFZ2ZhmuDgq/fpsa2Ut4kqD7pM7Q8/6oeYBlw
9p24upiYqELgpByeLZRkwjaT9rcuZzsqZbrG3MTfOdwP74t6d3mQRh0biaCJB5L0apcPuInBe22y
h4zxljQD/1JogJxhGyAqQjlIsBbN1PH9oqS5Lb6jywsPoSHkVrkgYn/ePVHaKwvbCjZKlDm3MuZ/
iPlSpfF4tXHxaurOlNYpfWCm6oTKEopNV1DnrUaj6u/jnKXWkpeyz9DfTKX16rlj1vGsqzj+dbr7
EX9wzBYHs1cG92Pda/Un/3Sk0OQFgmbiWOmBo8ppRsd2se+Ix0QcjvWeYM+CnbtK8VBIjh3opgm/
mf6NTL2wIThMnfO4yxyl0VsPHdwA4jCTLDbGngUegVuuCyyp0WxPW//3LBi8zUCagTLbJb9/PmhA
rkaUr64p7siYMtbZ8rA4OzL8ElbmopdfpNU+CTNHes014tm67EoLij5jUkEgYbO9z/LSyLDLv96s
rTVvZhKa4v07GqM2+EO3o2vOlXyNNL7nIA4tkV0WEwk0tIOQrhOZ+5TLRWSGoj6WV7uKCw0c4hWo
W7wO2cEk46FqucrA9naRAVjGp0a6oM5uEScjte0Pr4sGW68U/5SEkUi6jr1mCTrz9aAcKfFW1Orf
P+lsXIQMjDPIL6EhVFsEjQ6I1KOuEi4o1OZyqUm6IS4RsZfE7JoQnxToda45p+Xu7BnoUoF7eU0A
Ob7jnZo/fdDXcDNehkL6ZoONyau9o9Xn023MgZhDX23D5c9l68gFTwyacfW7nOUEYm8p0YzYwa9N
hvs7bnICUQh/1ykg2+27Y3SmSnH0nDcC1iLuAbygzuRtIV9W6ZXV0ikcFyVtVXCYNX1gbjw/qkpI
k/nRTV/StQosF89SGpEGtoMI+tePdsDzwpoYtFjDoAaQi3mCD2EEokJnZWi4PAvrXPgT0O6jOWU5
tmZ6bW8pKfF8s5vj0JgWS4Jowasp+oDxlqqykALJO9QDN10HAFANLDlCJET6DWNByc0ZPp67q3t8
aeVjavsyuXGRHef3raPUmoW4CKBq4g71OQF0yi4sdRR7Qkg+hIoW6K6ylvw8Nv6A7O7uxc/vlkgf
Kfy/+A4EnZ6PsvU5CFxRenaQGHJQS9Q7ZRVU7ReZ7po/S/e5lryf4emXuilAP5nz9b2eZL21cr4n
jhfW+moadtpwIx57lsakT90GRKgn3C+qq1A7JYA+iEMUIk4E2tZKFfQzRKxhTGnKFjAZnh81JecR
Vpy1RrzvCVE/OpRC8glFbY1mWKhRhp4YHbhrM7VWQOrjjIfK3nmn7/BAEbeCDXZmqFY5HAHFRUQJ
TdGKp0hYQxBmfiaMJS3HB3YUzUHfsOm4C9mX3ve25/WIjCiNDbGZgoyb+flTq6Xn5tWvOQ7Ydzff
zsGeZBVPlKBXpg+7AfTKKbyLfu4Xanuv+nwYYN7aCJUwvynQ5EZSkVLC+HBeGkxcm4XhSRxxBRI0
QyhPpX1KFwakOmzb0zf61At9ft1IIAR10VGvZSLF7/0mhMa7sv1QvkOR+mRcBnM2SGNE/d4j4092
ZoSqldqh8EY0rWBS5CXczJ0zSMqa+UmF3eLx50C6GyTYf1dMdW9iRezY7SubixWd9LhDUQxInwS0
zTnkIIzoeW8Jklp0tbhipoZycAdvv6QK5xHUfJYqsUW1Ucuav5Z9J3ZRRpABATmZM4yvivrhcc6a
t0N3dRLvOeGtv7LhnQMJmpaE/j+Qxgu3swpUjmkZDJu/g9NEG6Lie014pZtiSj+lvzOqSCvbQ78L
Y9rBL+lnSUmp8YtSnu2CYUSblZ/Tr0Qw4SO2rTfVoBpJqkNXL9+z8+ue5PYi8hzPbr0yk9whAo2Y
7LuzpU42++qocWJzOLxcsMvbTmE6UaVm/Vqtvke+wRGdBXxYg28ZKl6oxzfnIFa7sjYTTHtDFTcF
aecm0AQ7D/hZFpbMefPVfm31fioifeZhax17PAFPzW9QbWYZZY3OWkSAAB8yfV3bMTwKffmvXR9u
zsW1cohZWRwIjEo+fpjVWw18FDZEbBS/OLHS/XjxIoAP7PwpwvF8ARh2N98mq5/FI+7bFT3BJV3w
HHRxUuxF5F2lnhL+FY81z0pzQusz9SWvBoOY/g8UCv2sff9y4NNVqIatdW1NrkrTSn1CSy8QDRcW
Z93o7vd+Qxle44xbJg8YJxFOKdS85yEbLcVL4M1zfLwckwRyZwkfMGdZ4tx2m9LYJoCa9bWTr3zg
LCsVjLKKvAfLlSeJrhwxRc61mpqL47evmZ+DkIQ4t/pJb9Y9awIU4HrcXPSJHUsGyxCWEd182jZN
E8MM/O20RzdizRl5Jw3+tu6okwMaJi+cv9zQ9Om7N6E2OhokjX7kW2S6IizmI5TaycqCc9Uo9vHO
838g7aJFuKBlVELV5cT79DDnP8lGKGOqY+AEd3BR5yvNGi5mrw5NEDY+Wj00Btwr3Xqu8EOG8BmY
BFxTNNsdFf//ypzKk9ORRF3R5rQbMoLY6+hwioFpMHkbx3CAOxdVA+zy/1z36Fymk2eP9VlV2KW5
zh+Q8wCdZFifIAXK60DgtPI27zIsmRQbgaR8aa2u8ip1p2cy6YYrvuDpxgSCHnlt6mTrR5I/WVj+
Px126nvKC+evtkOvuYFTXoIuYiCnmpnaSZqL3kL0j1qk5/iuGi584/Ce8b8lhkhOnlmA8jJLSyMA
wLbQTr61GwopkVLlRcJwrs3mFLgNE3YDa2/uIkri/8kVTKdpy9OmzvQ7df7v+p7mQlcVJH2cl8sN
Rm5DyeQ3jK8bAQM2A1iF8paYDTZEy+fDTDCEY2SyBM/wlWvdi1HqsJBJXWH6/WFD4tu+aOqi6T3N
WVqp+eVQLzKMQhrVQkqsNuzssd/GMofbL+XbSufWcgFLsbBm5nf/FXFotXRhMn+HnKVhzxKquRZI
rfKykmxpB4ioYBCt8eMkI74UrxB1wn4vQ51nfoiLtYlh6RYc/bRRNs5MECwATOPDlv7mI8n1ggUy
zOWGENPDqZQNOahTUSXH73ZFStGq3N0MMiQn3J4JxUgq6Lv+EQ1qOJmpMuYbGJp6Sjlq/55+NiGO
FSDT/m4HHwquxqy1NRrn2SJDmJhzut6Z+ImhdO/hvgTc3gKOI/CjckCO1Cw1c4v4n27nPxrvkdK3
G50pYdgT5QW5uDJQozZC8n2AOi6amrNEqy7EgyBOMFw5m1PfKGwfPn1aRHV8NoK1+tXlP0+PpfgM
QSZSeYeweUkHFrXsUFxwPBH2TSjwmbB+MJqi81hwqTbruL9ZnfzDB3MNNzyXGtet2IN36b7ZGSUz
MGL0YhflBmoGDkegiZBHPXCDecT2v4FEmo7E4m/dwD9rEMNKtHL/DAv4kMg/NDntlcqRlbLf6U4W
355hld+3F3lCtLV/oPOx9Vtc6oXHh/b8rOIYZS3X4EFNqdsQ//UWH0cmOQT5MJOfrEhK5ioKp+Hh
IOcs2SUM97D4GrMcsHhZCycxtmtAzJRt9kL3FbHEV0wN69H6K0faevsjQTf83TiztpeExBreXn8H
5OxM7ipdXR0R+bPxnYKMJDCOp42odeH4YtcgntV2zYLk6FspOuv8IAuKOulnyRWdN2qcufXDdttX
PATF1alYld4E4gn9dnnbeqXtz+RTgIOYhVD96csH9oivufM4axcB72RnE9Jl9WQWYOOZdkWP8919
sqwsSMMxTEisAoFm7w3pZH3npI1WqHIjKQlNpYEfAb4R1hOJUHICKn4kbxTSgMmTWyroRK0iuwIK
8MeV/6AZhbTHJoJbytLbOUejGeVvTjinP/Cg79qnu9Rk1TKVhxo7tehiB5QqzdwjmAUbYadQRCNF
zXVV92hiIiUFwrrrDs7XSorUKzPKM5Pr0ak3y87wFfj1SfatyMLVwvwazk5r0YfONFdBARCZtP4B
yVf14cpXtzdzgWh43y18Lesfhm2vc7ic2AVL0VnTvnkyBqe3Q8OyyjMjdkapCbMS4s1QjSpugaD/
Ybx6yZjieEqHxxedUcDjQoTpUpECkPeYFDlKqedpDtw6lVpYs4ed6xPx3vZplSwc6ni8KmXHAq4v
huCBg24Ew1lJTZzLb9K5/km+V5llmCDqQsnAxBahaEkPfyZnb8vvycwvhA+h4j5Irt3FNKXw920s
LkG6YM8UnRNOEMSUBaFmzc2pwAS4RBPeRHTs7GlV1csxNChO8hYxGLut6bSVlDxtcX7ZbV0gwZhC
6wYc1zGDXRqZf3bd+6Doi77/K9ro9sEZjyw59JiQ5mlVp6489SHacLVs6VeO/MzTc+dU1kkaJ7xd
tC+bYoXB9zXBLAo44rYMMY/vg4MuZkLyw8n+90o99w5vP5pqnc/0SbgHFqYPktgQAezV8YVTE7Cz
TI6O8WacDaZumQy8Rul6Og2AlkFz+95BsaOYAwyXs9b1MUcH31Cn/PT6RM7nudiERGb4f+1N/IU/
WhLw/IdeXm3WVVsH+8nFERS1f0BNYUMag9dA53P0KosKAnpGDGTMvXRTa61e2+wWmSTC3Zx89FMr
S9RP4iDvUaj91JSlnc8hoFV1+tZFFEn84N7tGhTngCOFV0Ofc8O9vY54FCqRirfHzqmWtACxY007
22LDL6E3KnYJoyoJ/X6LVIMzwuw8bIBs3lXGhJC/1Vw9GdPG+2I0N5zL2am9wUvuDnw0kj9F3n9s
WQH3YXpt9jLxT3cGjYBUNpV+QPwD9Lqh2k3hX0Jz4dNmXvT4dd60dhteaeU/diZTv09/BOOW/Tow
NQ8lydmjilOjc1ted6EMM1LPtO4ezJIqeHjacjXrEIqG8G5p+o5iLe4i3D48L8PqTAfufucQ5BQq
9aAU/SAQ0p+oLgtRV2TihKoYqzTKsT6pfulnoK6kkWcu4a+6ZQ3zc78TeG/4YgYMO0POOgwZyhm3
AoE9v0+q/ds/vP2HLQ85sZy5qf0x8gGZ7wRyr+sL1ZTc8trD5nOSTevDlmvrB8ArnkHSeq6KXJkN
dFuij9YvWD/exLJT7Ds8I4JtwLrz7O2DFnimRPxCLQqo1Mnx9z6G9EjAm1evRIjOAxz7OCDRuPgQ
7q0Ry1vMhfpFLpKvu8USD6U5XhJXUYj+Y1+VjM+VIz36u/icaJV0mmOKAI58Mq1cKEvmNTcFf5ln
HIwc4qn7R2grQVH0ApOCY7RBVlQCcT8T+pUC9yqYALKM+Rd2bqO1+ridsySWv2B8Rg/E9ndju/vV
cCBurgi1uanYTwgHSiauaT7EWlpx0vqaXiOnfAeshhE/MvZK2IZoE7sVI+tI7+1TgdYyKiVSv87p
uEBeyBn8RuzhGNZRYGCfqTH6JPK0CaFLiM4G70W6SW4zLhnV4WES44OpjyD1qTuvM1gwGsYFbJz0
PnYjjsOfIU5TWkeA6lreKLnnuKVeI+tRy4bY/HIh/j+7ShFtsUqztkuM/J8QE9XmAZRz7P/4Cb5j
Qw0VoPNjbA2eI5+tYc9bnsDRtu+oLDRP401RjVojNV626z07aM7lieG3LJMuo4ANuGek55tDMdn0
VejK5jfqriBJaHkJvqGPn4/Hih380346OGEg4bGdxJ0b6k2Kv5Y1IQqArYx/lq8GoQMB9lCS0f6v
VLoKJtl+zEaFHbGlDiYxy/aLBouk2Te1/WKEBHpy3RSBFY1ber9dZkdXk5E53RbccCcxGY0lU277
X0MzOMUTruWxdc5ZRwxg+M62DE0ZUt1dORTX+41hTKfmKcwY7chKVGqk/YVLXIFM0st5C+ZzqU7F
W383j60syJVAAsLn898sWzGudgMRSJO6BBOLQmaOkWpFIzLaVaXtKwFWRSfw4+qIOugZfilWr2JS
jl6MQdlzTzKveOWPsbojG7vdqedOZswd1xNQv/TPZJEDla4qNlod9WYfZLu9HHZzCXyWn7GUpjwa
2tn6l+7OSEtRznydbzZDlADdFrXeM6xEaigbZofSche2MoBDJfZQE8MQFw4I0uqG2W5sYXo3mDxx
p+d2XMewIB8ULl01bMQMYortW8Bc7KTIlAKm4/DOZVbndUIa7VCKjqD1gxby9lmRH9F/SoIHrqQG
rLhOeGz/twEogW8+Roqw376AcpghYcqBYMaUEqLeh7A2QTFVNAULwDxc8ndX82b3rNC63mzSKPst
1HCILR0CiHoSfyPmF6VYFk1PHyb5SqfrtYlrz1iGzZmRUC5LAynyiUdbhQBQhPa+cB0DVl63H7ug
hm9ij49P6sXcqA0jEF4oExnx6lUNssrl9Zv7FjRPON5mD1mqmOdO3h6yCK+4BgLLmTXZW8isTk32
jVX5wYimVLKb9UZmvjnnd/I0ZPiKltpVCS+hRv9pgRw+giwhmOvDVb7+oQHzfZU/OGU79JtAfHh9
fXpzuM7FFP6gIyrATQCOrEwlLeZsJ/mPlrfzI3XbJz/i14gKE38dnTahInXhe4M+GiS7YE2x1QrI
dBAXe/llPEYpO6eH1MRKX/EsF89g0KCfTJKjU3vEMojfJinSB0UyJMmxajgTGJsvYUk/MAqa0cJF
ovBfsgyPJ3QwbtyreGS2w+A5ii8bW61JD0JdLR5JOODDM/XaBQVWMlm0lqXMEuI52TDG8PH5bN8Z
eIi8AKwBvVDGBFHA7f2WC352KUxKA6Y0PtQcobGFguf1dRisTxZv7zi6mbr4uXLfcjBbhFY50kIK
w5wh/XkONzoZlbhsTCN4Y6/VQL2CZ5CnxomfYAMrZkP0duMosfbu8XtKXg++6N7UHdoM5VDHF7FU
DAQkurjFAxSf7YfxngrPlPvtQIfR9FmXFm4GInwiDDVlGPsewWk6IGBxLpOYTG0Ey5p+Xumi6k4z
6ZHz9fT9+aAxvbTnBm825OWgn3+Yq3W++UR8hb0BkJJT4/vBCNSlOjQ6v+sLkE1b1uxFnz2LA3Xy
CDxRIxuJbId8Jvz8CxBCbvdJgLD+DM1hdK/8nGRCyEPrZeYGV3PhuYmGnDGgC1kto6i2v7Q6TGcp
RYaVHlS9h01rwKYWodOPTm4xIriLCd6Fz7bIstM1cnNGA/o0NTdPP57ntKbUgQa1vepkFtGl0oY1
oxPmCrOtXh59L4q0F0FFojtM21PV019tmEij+stoM7gxEvoju1zeYSqyIjL07M1TJ3tr585p6z6e
iNrlSekTyPHk3jbELVFESZOxzDMtiYxSnQ3NxE5JnM8Mu84v3daEepSg5hIqpFO+1CRb16xgNfJu
vu94cyuwCmmHX9X/ioVaOjs+x7VM1StJM+WjjhZd/iO9G9/cT75layBcmQr/hK0x3KMDXrkHza6U
BwW0lxw/Y7CPESLexw4a3Gr7jSKH9LrLFFsMuYDjsZ9U0sPH5y7wjALH7H+WGddDNbKWAfnCh8C/
PEB3HKroRwBoc3QcpfHkCpUGB4U9QLZmcrGpzPUp/+YqXvricsFe8ggKOJ7uav7mwf3ijoget4RH
24ITha0qNhRm60cXLPus+UvN0+jxrB+lgBExHffcxaDGaGmfeeXWFb+fMvqBUMuVBAVTmq2eQMiK
t4Uyb2n3rTa2lTONGa67MF4Zwz4tHi8xTOFlYEruRhvee4cAJA/OhPCUI/tSfDklQT9UNCD1s6rc
i3rkYTxnMOHM5p1wMQJKSOvM27oEdn0Y8cx9zLFNbdMgesdNT9gukLuNpfu08vJeonwCir2CnIgO
JTBwRhqs21LaDdd6gQMjimW3dauoCvYEIClkdHMcjoyPXbg6m3GshzMb4f+TdxkSduBOdV054nSf
qYqFepyxzTuN1gXSh6bjSmrAe74THMWiCeCU9rCjIrw7uAX7oa7ujeBgWdSgof7leSG94sAkGsO3
B/lBKnwHGLmv7y/3ePcot6HoXhyJk047iWz15UAjV24E3IU3mxHwIcYHFFVbgxLKPiod4ZNtqT9u
HoFKJiW1UtrfX/mX37tQH3Pp7XqYbF7+4j0ClogvpUCYLxQ4uGqbMNlzhyaSPrVKHBeOrM4pRT9U
EhR3rpElMOgbg0RcvB+tqbq54LQ7rVXszY34/MMuXtgZe290CQsZqmS5VRDhORrxR3T219jzowFn
v5fMhB3J5mWNi9ugu2JoPB/KkduigmhaGweLkKXyz/RJ1UTd0VV6QaD0bO+/8A/+1FrNd8+6tEqj
RetKbxE5lZ9Lqr0EFVAF48TA8/ldJPWzatmOtO37Bhh2rNQX/Z9XP8190BZZllndA3FiZjRsgXij
3+ZGeqDAMmzOishvzi5A+qdH5Enf5VjdMY9orB5up4zL+cAel90SH8wUnx0uu2ShY/NwCOZYLgwu
vpV+dXTedTMDvh23rWexiUQ0siDBlUEEFCCcx5oGtKJMI/Dz7FVqLlDRc689hLErzTonbfVtPUU5
xKaUk5+EYLQFCq8W6kG9Oeb5L9AbMyZZcnNTZHy+xlVP77gqLJtLuNEiuVoTmtH0hSi+QoYRGaS4
B5xsGFTpXH+ctae9bRuCKmn1WgVEe6dHOBGMSm+RMg0dbRSc815p4G8oCWYQIF2bzQvW4yx1nNUa
XUqjN4/4Uo7DHjDVz0+8VZOF5zTyKdccIlN5ak8ooM039AvL234fkY9KGE2X+eyKjqBOikbheBPf
wexjCp09+dbgsqspivuqaaQxocuPXGKxgkc2nqtcdgxYOq4DLWppxBA86itW18HQR6re4IdImG5t
PG6VsGSK5xim2YKpZTFebZFa+VTI+Y0qUnqEXvjH3u4SGXJOE/N3MEU1lTTn5cyKn9bsKNndK1/y
BQfRk2zopymVkNqxaOUkGCk3Y/SheTGpt13RJt2WKsRzFXn0EAhF1VYzB+rdWWC6AiC5kdQhOFyW
RwoqZ5Wu1yDCI3BmKlZ+mLcQMw+N2BLVnnkf42hj14yLIitwVX9d4afPGay83J6AoU89q6RCe6c1
98Vcctk8oJ4t3tTzDKTJEV0ZIwJeCSqX40GNDxS02wuNXEnurLVgknqHGGEwquy/Hu1zuJHnejrh
F5WuITgryfgJtKeTQHtQ1a2CZETbZpi79hQsHccSRix5ikiZnywH5QBTZtC94If76THf9AEjt29d
YKnjPUtI353e63mKLUTjgIKMFl6E/DwiOvX1yxDsWyVckQ0EUvSueelJHHUWyy0XEbBYXm+Jp6Eu
ls9I2+j5bwr4KkDwjkVAY4odhYZsHb/oGglk2p5P/Nl4b8y5iExf3GtRq+WtPkcFhcPs2sn9a3yb
33D0JUr74vn78zvAyEjjYEAEIoGOgYb/i03eFGZTJ3Nq8yFRBILE2q1nw52Qk3O96syS45Pi7FSV
9GazCCmnG/i84IP0GTE/JTQKwrqUkgQtIbXBcPMGFI4xTjB/yxlX2DkvU2viUV9Ofr6YOMM+k+J9
4zjQu6SOFtZNAHfYNhdJYPDeEX0WuLjaMU4+CO997HKemCbb7yoAFr1nsZxilHH4cKcf5y4G8vBA
5pCO/dhsdvn9/apvpO0Wr0VnFUr9u7jkMJPHdcCDVjhPE0PDR7R/EbwAsbAx4n97hcyk5Y7gnr3t
uDLpSEUOIAiV1lf2cOydBARHvu+oIg/U0Omt+cRXeRd0n4/EyXaie97HxM+8D6QWCwukEn/OQngM
rS9zm3pGUneSbZERCZ8qSYQF31j1xc5e5X4cHT8FbRLSGrakf6Ei/AeYHgkoigp43nnd4hMtDwh1
Bg2cVGc8kE9UjSrEe5E90SQsT7cpTQk5KKhwHdUqFqZ1VBamk6syKnArN7FkSS30sxUu5XAOlqim
SFs7rkxfLc19K3JTask7rFiaB9TfR33BmtvtHPdQqvdtkZbFiRmQE83WZvEVkkA5BSts8qMj6aU0
5fY7oC4Tq1bI28T/i0AekulhVKa+2qztxqsWrEBBDnXwf2lp7bdDNiUsOV8QBRwSzPR6LEM6caAF
o1EcHj22lef6LZzwdVWmac4Z6QaQkqOO+0pc1F7GFOsyLkfveckHZeG3BHb8HKLEAN2wAsPuQSIZ
nD2tLEksdI1hU5AIIqA1SHgA55Nra7LDmPcgtMe7FnBd6gp4QGZwmbsBnMZfvhDHrjhG8aC2ZAqp
QKeTrtUmEHjv7JPY8QDri3IqVjDZ4vnftLGtOI0/FimhOKnEtaJ0hadx3TSy39N2CNRvgsx18vAg
OtlfaBi8IShQPBNXJD6fvg194rrTVbQkhby/xHsdIHlAKznqPArSsCEqG6DMQQwYpUKnE59CiDcF
f7iJ1+0s7kvypgjWiyk/jv2T8GpYbmHUZoYlbPCsGJvBZ/ZEHCrF5t7JKeTpVoqXdh0pnkfOaGHo
sLNmXYrOUDlkwtu9ZoV5Zos7boogzvOthPnArW7phHrU6Nxyaqn95fXsa0iAwDoFbff4D++MFJ2t
UBFuujBpp/WKrw/86Tc62rncQmuqxWc2av6R0KuYdNA4fo+O0Ui0pz/sG5npKemZDyjI7cdWQqR5
bkqjO4n2+8cB0QC3nT+EUjqHx22Yr6E6R4Q2yScHgIkINwqdy2vfepQyjvyADtBOc9uX7nFSFkkH
WuEUFx5s2A47guzcuNueJmbhlCGMgYLBK2yucjNHqFrOacUl8JVihz10ZpukrGuq4JXHLKVFTsnQ
aSQaKyFgI9gGM+L8DVYfArH6Wxpl/8c6+0I6aGJuVwhPl5vK8f1P1WyDzrT5j9Pvt4DV73St4Vmf
WqgO2ONBzf+v/hFVRh4nJwQE/Ww/QUNT9Jcd8pDrEL2K/mc/PBj1q0CBEcc8Z7qdtr5iAIbUeDLU
Uwp10HDqb3qBCDBUV4xfWLgV0g/jc8y2vhaNeTSU63qbmBNZbcOxRkpumvCVC0VL+moMM4ylnd47
+fcHA1UdAp3AxoBT8Jf/+IJazJ0wVdWXIp5lfLzEF8oz8Ph5IriTj4ZCKcZnW4qRaq5dUkf0h0el
2oVkgrXuwY11qr1BiXHZYrTGeeUYZZTNgyh/7IvlD4V+4G5gprndoIajyYlOOg92atZNF6J5lme5
9a66n0toVSBX6ghGvifPJvnJxsS88k+6OfmKUwPEjZCv/MJikxzwvD4CfeoTL3iQ3oSkX5K3ypuq
DRCt8VP0R9xqhVIqzitWirg19b44ihX1W5KsJHBjdcaQ9iNW4CZzt4nIBlFh6sVf7OZz0H3orID6
yI9YmoDdltaFQyiq4Yj9DwOGGT8uwP04eD8z8Xi+Fp2PCKMFre+f/oYoMvVlcs9lI4xEmmGUv1I7
oAouHhTxiR+2i5uv41h/iHbVW+pV5xzlznuyZRv09Ypqsc9C59a2vZmVEzJAGffpDm9nnTskxBPC
T4MvI+x2MPZk8zX1jGzhrpeWF+GIaaW9BKltj7+Sug50/Ci+JWC9zK5qT+pEyXHfEAKbpNWeqz66
jfGQ7pfO5QGsMTkm81z3Zc4ra7qHKEuI89VHKafkQ1PeL2Lxg/gTn6uXyPF8eT7nIhbe+1oL18l+
Tywbi/F47TQcKA2iBDCmjCo0Nsa2a//39wxvflfqA0J17Ch2k7f2WpJAA8Ixtj/gcMcXKKWPBTIr
w1I390VLW2Y8C9HLckVfZRcmN4+T5r+vamFd6Q4ENulxQkjMmhMm1iZ7pEHGllFfWMM0o6l805L1
vhhKN5SkDeK0m4kK0WQb7XrL1Ph9fDqysAXoGiEkf2znM3dXw8T1G9IR/w59sp6umMH3YBcEhimK
oGcNrkZHgcTtQKiErMipww+0HmJz3hTANrsn6Y3pxWcjE3ZhjNYc7D2XHxbgdv+U5Z5Zzn8JG22K
zsN+eMnyL+SytEPw4bmODQPBTvezHzvkc4aG5NWAyIH6XFoBa2O6JXT2jznRpjc+jb7nHlQJ6ci3
xzVc2w2K7/G6BjN7tV+/LYQ69oQEIaV7K5SG771QCDbJ0XHXpiG/ZM9V8qHKTsMHR4rN+75fO0VG
4TyXLVYmN9fdUpGWuJW1nTqLtQylOUWb8G9MIzkT8JL9XIsXa6mPqClSVdhntOKZ1QpIokXUdmaf
kcbUxuXnMdRuoAXvvmr9AGN2t4fQ/XnetlgGqCeKu3qBn+4JnIxzKtsE6N1/BHmm2EGCeOVjbI6C
Uhv3mFBmSgSkCWmDqk99e0sCGrTD5LcnzGnfsR9Yu84tbi0j+xnqumcafq8fqFb9HRoyh5bzhRgd
eF76m5gHNlfTJ8Z9qRhH7+QovETu2e2PD2+8x8DePJKbA6edc/nrUXTTx976WAH4zBSasUnnUKM+
3DgJOTMNl5SaMf9Fe2wlTuUeUAeXyNvouOxq3G7kg4FzDzHwfDimt0R3/jbp1/LMfHxJQgbPeRA1
SeaRJ7xpPmKWuQ4cQgEWH9BPKIbZRg8j8s16H8hnWc0qND34Gbos9nB2TYdFAPPCD8YO6NZWdgSx
9xAdVCkHWK7TJFphTHhBwyoZXT5iNc4jZr2ph2S8PkBUjbFXGxSz5h9NgN4BhbRkCWrO4ZIyXpro
sr9EgiXWD53QJ2WRQgBtVKo90swYU+NC7HxO2AxP7pI4nVa8K+CNvP0H72B+N7brwgtz5mtQV/YU
4Ya7fLomJBRn43e/dnGh+Hxx0qL/J9OIrJFLjj2b+0gZzoxuFaAlA/qMnzy4OMuwZGdRFnT0V9If
ihhPX/ZjlESM9ct4p285S7SNyaJ4PaXLc9RctUmw0m7n97qupbehEZIUeg2Hp5sLBUZYuSEXa+6Y
fLnrCMOsusCF8iIwxRKyrcvWXnJe9GAcc9B3uQyE+zEK5PBXd5ILOHvoxrE86YLYvApvGyLZCMmU
ibhEoX8ERUD3VSS1DsYuDZKKqBS3Z9yeGKc3mWvOKsOS4ysJuLCqe8wpjp/9F/DaHKat7/mVYC0p
aDFwcrGYCSnzoidWkPXIPjOEH/pUAIj1VHKX/iNysSUVbyQPsB+9xD8GXtcTD3H5U/58yvmq7Erb
AUCwZon+TmbGK+lGfO8P/V8psCdK1HOM3IhsHqXIxLlv2kzxMMZJiQXjw3E96Vuj7MSY+t6DUrIl
u7dK4CFf0jQdzPycO/Ampu/VXF8FP0l03LvmS28s4FmZfGx2AiwKnrnvp+P3/gnVAAwiHyJ6Ys7E
QfO1rkpbzpXdE52VwZlKDmxUTWed0oqllwHOaPX5/QRFORhmj3y0IFmg9IWU17r3W0uRw8Ts+EHz
D9yWi+keHvUQpeiNH9u8P7zifjEA/ZUM0yPGXduFmz7BtbbAnOSs/hTnv6FULVee840OveXvvZHe
c/uivDza+P0uHjO7zpgL3nWCOywP80QpfNV8JYzl+mnzgCmQw1bH56VR8A5vn7wi53e9CgRx5OVb
mmUViPVyvIZUifvUSxN5JS1UJO4zKOHVqv79uVwIUuOzNuVSPXwEu5+KC0l+fVo0ilnAmgIcMybS
a6U3WfNeCn3Ppl1YXc6Wzmon/0BIByC/M9T8MAVHZo6u6AF10kwzccw53kxwbVkMQhQJTs57vaAY
4qohv7tqbC6QfE8jqlCSKRjWignXmuL5z7K3Aly8yHxXtd9RejIlHz8sGuTgP4hAWyKDWC0alK0x
PXqIdCTSspruhAL7vtqKaX1F+Tn0/Sp0znoJPdq5+IdiAKIjitjzcHcm+rKLTTh/5OXlf+xa+Ns0
5sCIr02RH8Y4RU6JAAZ7C1zJXUTu6xb2X/rS4d7uhPHTAX9WvpFUEWgwI10223RI69yYNx0e7CiS
ylHiAi8Vwz7nvmjAPk3ns+M7xKHcUj9b6mbxD9BWoVs3v/ULSfI41iIvE8swCLDu11pX8ArQkeq+
JOkU9d4pTOmsavedRVSLPVwyoTn018ek1BgS6gwQ8ljVrJSIF+ZDVPoTE2+ODIjclZZuRjZ3yE6p
cSc6fAQ6xqzgQAidnO3dA3iLb8N+OQSsOaL0UmW3V+iB1upPxKPFvhZNoFWbTLhptogTTAAxup2F
PKeH2qMHonLF8kp5Edeme5/j99z96fcsTUI8xGNlKx54e84B4yHJRU2EzNOJWnzLXz5QlOSqUMVc
uynJ2BrvrYQAO4NpXvfX0+7tiyH3z1jh4q80kxKGjUD6R9NvJar+wwpfuoZhEUOqRgrW+WNrOyLe
l7MvL+rOXYusSdPTdJijmYE1uyfbc+oij2uNPGxawgpNmajmZG4bQkpt3VbQyafOSrfYGZT+jOGr
FuhmmYlcgWyw2fIXScoI6F49lHyRuTs4LxQRYLc3TAVeJkRizhKDMKTvJk5j+xpqXoyP8wAFAjzL
RNujgxjBIlnebgCp2l5zIgtC1WC/WROvO1hljD1szw1doeshylBfDcGxEEFHYh1IP7Ii0lB12cxH
t1ZF9coNEjMV3MjpmvJAaAdey676TxzL/InkznF/BLcqCrHZ+Z2+VKKIZPS27ZJOev6GlJnv0rUr
GI6rInlim0HKG5hx5dlXqra/iLsD5Vf4kOt+Zk62fECkibHY/wgku9l2T+TP//8XarlvAtGZCt/X
A4r+yREdv0bRoU13Jfh9WtaLOjVRAcDXO6pz1GERQswl6ZooOX/stZ8oe9FPDcz5OfVmMKTfgDZ3
hhMDDA9AgVSsqGu7xVTmDEqAYEMuG6HxPhdEBoMNobylJM4Lai9ATQOsqO+HXCnMROdlDr+m4FUw
1+dXfjIGajnzgje9Au/wrxzfCp2jFThfID2jLhWZ9IM6lM+yuBLuM+SHj81r4JumjB8TEG/otQck
PDyT0BT9UwxvwS9q8qCmZOaRqGYLsFLc+38XMeysCl9y88yGYqvI3D+5WRPWIE2qpxRZqNxFvsTl
Nqy9SFmHb7IKziPr62rb4jw7+GtkMZLIccEz/2CUtUuvsaECEaquBWz+jJN4Qq2k7TyD/sHRCJB1
hQ2NSXMl6Pb09WrGFkCxAONdqRxnw0+uCQqFDmiX6CntI3V+DZgw2dbL8s4TNrna8I/K/aU2dkoQ
+fV72JSW9KeTscLInuHde4EJVIXJZyCmZlqX3MxJMjbK8UxEYOYiqW9FMX3B5VlloB52hglvlzeT
RBnglvXvZDSMQ8RhEe2jhxjtL/sxSLexQH+cJvLY6zgBMfsNFX/018lXvDQOAy1euM61rjBxaRyj
ROZd+d+gJhR1f45KlUQcDclPTAfhTe1+1aW9NmFAg+acaKeHd5nV3Cf9pCTuU4eZ0Ptls5TmW97L
DZnRMeuTQNyUbk4/+UxwLykW8eLkBhn7Q69DjkVLyTVTkoNj9K+fNcSst1oX2Y7aYlObXNte1gND
nQCtl1vJDf0Rwl6eDvbgHs3dEFL1DvEshjpp/wUAtl1MIpFIBmQ/9BjS7FvgY2BheGfQzWdNf9qj
hufcUmQY9nzEXftLpiGMOg3yCkUnc82co9cdfllLdi6pBCx/bHWrE8YeepcLupr9I10PVUWaBIMP
b1/FFaYuXEIT4yncpGuSo3A9HRYmLso4LJuN90Sa9j9ClY+FbCcIenCmJo2ZDkNWmiRPi2ylQSic
0GNuJmNrkUA6WO+sYhI2IHKG8mEc+XOu4fVR5YpLcNAB7VnNAqAaVHsYigR0Rj97unZvdmHb22mH
x6yXGbOr/9W803nsyF7oMx5CIRyg+o9TN3nae89dimiguQ+C/srB/WN6JpAF16N56ctJL4Ds/N3k
6/nQVVnj83GnLRDriKdgxPkF6pMFVrlWSzdUk8NVXeNf7qiABoDnFtECNV9pzk2Dv8WovtnA5bZi
iQaSbjhzJsM3d/uV+D9mrpLNhAE8dLjq6eqZT1gQdSmXB89BLuD7K5jqKdnIrt+0xqQqqBteUBN+
ncdPNDEhBzHgqLPCWkYAbTQMDXzyJopsA7pnXiECrTn9bdQpUuoV9fx8nhcN54huehpwSScatRD3
Y7TLfkSulFLiIPBSQAGJOGpuzD9WCnFFL27Yn+S9UKw4nVh+7rV5xSyCaE/CaG/vzu9Ga/au9Hbl
qbRV7ceZpt1dCy8nFiGTL6gun9qaQtl3raw9yInwZIKSZybCTbU6SK0M0CfnLDAZnmVeA3wDIDHN
zThvgBW6ppKzRqFyiPG9F3eayB8ki5S4qp1FATWuHhnuSv3gJctFtrCjWiRmXxTMB9YGp9MDFAQ4
TO31pRRFd5/n6Cs4ashjZ64x4hfzdrK63TtTONCnINnI6MDN/PpiPq4QPRGZ2aHkt+8aefr4yEtI
Y+aXzD5m6zj2wGAgk64X8/l8KxKTV750WiNldVcbWIYd+d6d/8ZyMpRaYEIIzH6HWaDdGf585TqP
2HE/dJUKgtqPbYmcANKF6j4JbzBAECFlzmJvpWOdwkBLk5zpmvpA48HDI0liH1Lusf4o6Zj3t7wa
sOn0Q7fLwulS7lKNW4zjl+t/jmVYfpZXe2Zd4lcP1gVOYX4k/DGhWcmDj2ANGJRxOPUAgTOdls29
zBvRxoVlJ8eRBi0iS911ivYrCWcAnlpspKnRfAgg0/W67FfQPt0VW3TSM0y8X2tVy/xewAlLhzBn
UYvVdAi4GJU7PYhS2NjwISlOp8p8cA7jC3fxLd1wSw9lRiGfM/3b9tSi7V39F3FFM2TzvsLr5qEl
Zh7ZoVvPu1gzIioq8jyns3h6zqu9EOjF9mABa5epmPJtL3oaFJbcBjtQFBUuVT7wFp4FeBHx3bMd
dF9QfKiDqx6xery0gKEs/+9v6MWax3WqnbhFOQJGs0Kl8BWpDspV9v91ROzu9Hjc89lehB1HyoaF
oHIP1d/gMIAq4diQcY1ikypxozepsfb6QYCnBxIs7jLd71LvpugUg3sPYt2P9T8TSv+jtVBPjSuD
8fVKIrXwQOOWnAh6HiLBR4kqYIE9I3G30smUu2NaTPZhP/pVBFmSJY5pFtbzlTG2l+JD/xeU6Jl2
5p8iJ7To6ZEXvf9ybDjXwhk1yzCxaA3gsutN96OhOafTcsnd1ZN89uTP6/cNVWRp/AFEuzZ4gBTb
Lc/RICsHtKLmZ1cSokp42UAbzyY42aQKQjhympTvrpVml5TrALyoRbfzCZw7R4k3hhTvqljJoPS9
ArDZDwgMzhp6uDADj3X33X0tAj5GnP42iwlTNwv8a9DJ0kdPlNB09XBV680RJgH1GOwt0gg9EvxD
XOPuO9jenR2mcYJKBH9cYThRRvLl5I8ug6U2MMFsZwzas/gruCMFCiNNCs+VIjEVtnIkXTQ0CZ+d
q3AhzEYXjE11h3ahiXKCDa5mj+pvrkmqt23ty/hJoV9QHamFTqecVmCw6MnMwdeCV1I7o7AZ+EtK
g/qzBfA6i1VLT3TwyfUwgKyhQuseb68CwYGMrTuRfpqQf9iR8j+8F2vCrJomxdatZVlKuKyzVaD3
tnZzCvFKlDDuSnTJ6uyot0YBxaItYB0d6X768/w5TT5CHH/gbIuJl6MwRU+WCGffi7exxEVat8uM
/JSbt+GVAt3hatdyA51/Ahw2JeFLl1vzAIbFpXW44G579LbwiuZh7riC+Se1lR8pdgLqr4LB/QWa
rg19mdDfbBTAbvw5MWHhjs1tEZKR31ZbojR6dXtRfz7BCGrFAlCmfOTkCf3dL8jmX9mFfVLIIGib
C7nFEZjEX14eiSrhkOB7GREyM8XocqPFGupsDd2RsI6SP7q/xadjr34TWtTqb5PMoNb+MksO2QNU
x62IVi58RuhFZheWGSYKUXXvLivtN+4WdIuY7W6kOsQ5R98I7v9U7b529CWD4sd/6eXV1Rk3/O3l
lNu83OTRlUTh2d4obt5IAfUJTIwx7nMewoPvCJaudRnAtIBaoQpr9YEPpn4aQIybVOnnut45cUV6
uYkeVdH7pjzUpe2S6GMFQGvSM3lhr0sbl+MGsEFvYDvJ60Di9ZwVBD6xPOlIHVCESdpnj1CpWevT
CkcwsEcs5Bh7VSXh0GFyR0Q3j9U5i1kIz6XHCnKUe7QVvlpuX+FYigvTPlTEjBWY3KbQXAoOuM7P
jyBKfVt1j0AcjLuyNFUaFp46QV+fAdIoweXsUl9rvTrS7prkEd7PeWoe5OG+J/Uha/gfB0ecFdA4
20i0ScFgrTV1s0DDnccHpneWAZKZTZIfrL3LYr31W2UmpYc6njGtAAaoRrKN2tgELLP33EIdr+vQ
M8fz1R9DygDL+ykP/7i74I9SvjaH1ck4XZtq1I6DMiDiyPTGK8HhCM46cRiWBFTPWiCH0j6CfEUv
h2wl0kIufbj0Z804C3lp4fKk+DV+iGC4XmM1Sp9/9mHAu35gL6vXBF57HRX6RgsxNj2OWotAjYlG
y3n/j1C9qS2NzJ14WVJbl0e6+ryyAAQaVwtQMftss9O439NwdzYtWh800QkYSeqiq++BdiuOYCBM
5nyE0CXqz3CKpU/wTiso+/9+nBWsoVMATT+NexhPNZuZjVG61PNWPbn/a9vZrEzQ3L9pe14/E2QX
B1JLx1/BhgbWaExssVUscgb72/jNnQK44GAKgEOaD0LAZ8CYOHnlBtN5lsBKa00QOpR7TczyAqgG
7MthOXkOWnFxhcYMNjLwsrFJiJS5lnELluxtd3qKFUmYZlgcsQ3ydEjoklHPZQXqAyCGCB12ku7d
askaUgklgYW83Ngoeb2GQZtOKBsuRmjBp/xl4cvzhdDm5eJaL6W1/8aL7uaRigY80zxzXMW9o4dd
lSdL8P8hOKKyrsna+gM0mX5UdajlVxtEvEsV8v1Vn9FjGFhOTnpv00bzwjF+QerLwRYjyt6FhZjO
EVmhF/xGeMiRbo7kqF6iPB7fPEKgk5QocGKXAJ/bZf0D1QhVPAxCAt8/f+G50q1c1U1I7EiD+D24
nRDbPrp/UwU0ASN5AxrT61GWGWw0Q9/9Wov2MB+DnFsafOXZ6q13PPrJl9IaR35tq6ms9ltJasi0
NH8DGlgCBSFN1XuM8VZnjBHf0o1Sm4YexafKgT6rLdbNlVRaoFrXhaamJqq4EYidKvSE6i9CWNac
5cwIEt0Pt0wX2fQTJBlnTjFgt4NZNNo6lIPHzI2TEc4XmIfNYoze/g9HXDtvlb2GDnRikRlV/i+m
0GYbhkrhoJevs02WDOG+VlKPIkt7FOIGgO0mW91tWR9lbknZnKqAoLj0u0KISf/AqzGOY+K+GcPb
beOfY/PQ9jks2X+U7WMpQY9y6Rott4pWlvPX9r4qqq6+onjGoslPSKN/i+dPplHaMydF2HCtQs1u
glFBT7EwSd7n6VYdV8LEsH4nNACJzURzr0cpUlPz7y+lPKzg/fWbrr85b7+mMLbrIsSsvQvBu3uy
JXVqcGhwyiRkCvQvk4fFCRfzAMz04/FK72s64WRof54w5GbjcgGro9+3SjtFojaGvsslIf20V1oT
3Mv58atCDEfJN82rOaYrfiU9/+jSsOk0Q1r4xZElxDLZJzypFIrZ482EliSV6kcgcMs0La1sKAJV
PuD93oopyZV+LtqGsCsaoCkE/02YEmNeQ3oAes995y15fo75nFEkTpyS9WLtGUd7dlt/kBpcDnEE
hC7jsT+h/GPNanTiHqZQe0u0yv9a5C9i8kjO3BSK7C+loL8maaGVOsoEpLQwninDCMAzYMc+mVoh
ybkWiIReSF1LLGeKUnuKWHzmptmh89kczVz9UifAxyRS3fBMel/nDw5UgKh1ksRzgJ63uG8pu0J9
peeDgPjApxHKYzdesZS69UqvxdGU3S2Zphs4qpA8vimz7ytSt2/lS/rJMrOue/oxcuDWo1qgLBpw
5IyGLDaOKAFKTNFocQa0YxbjRRMhFz61xVno1+dXo5lnBE5aEIuBTKimdSdTJkq9K2pFntTD4Cgs
0VjnfgsqdpdXq9pz4o3A/6cxlgtwM1qodfATI7Uv09Kd+yHuLmWGhk4Y2XbJ4ttuLgN7AShWzbPc
SXvx7o2GwYb8g6mxPfQk6o0d/PlAVbnS+t+mlfwav97Vgg0I4+KKkqZ0E0mVJ4Q/XB7AY1N/3coD
u0ZUAxm+Z7S1q4f0RHt6Bqg3MWG47XmM1Mj0Ces0W5iGTtS1l73pCbpo9AWlwx2/Iz9HZKYWfTS6
tCUPDr5yZaUqTn66LKCNy92XfuMMgl4tW1NUs8XkvrbzlXn0c5x+njQIN27TPjuiBpCGXI/sneeb
s5jWtsGyPCTvf8iE7aJQKmtK1dVf5976DIFhC95GnF8WC6tCfkaHORBWRgt4IC34+OkjaBQs3kQp
QItE/w5HlkbDTrvra1rOcnIcT5iEJtBmcHUiAYKSeW6se1rRj+TR6J4B3A7LYbsR1bYlqNtcwGKg
4wZqPVJ6n5Bs5gxGbWuLhcm+9x/VJlOG/7DeUgUcDuHFMu8KYsIdOQT/dmcZMUJH9XdUVc9FJVgM
togUtaDutjkY8Wt1cG/VJ86AktgBDscgwDUr6d0OG6Rsby0asOwzphMj1gQKN9OftOZy8LzYd6lN
9NwsdcZFLGJrul5uu+A9vq7xEeiE6YxIWjvcSHihtEN7xczVFgzW0qQK5Pib+ZE5EMjoXXYdjnO5
83+thJumzKrtskvYRY1vZBNucC+gIYYTnTs5MkCIt564iRfzEDQOcV4I6qK1xDXzqUS3og9YRPEx
DI2VTYSovDRchn05rjVMeDRz/yYR+cks+aPqQA03JOBjzRLo6H18Wgp9bHZ7BNWlgp6zfR5wcxhO
yraI+GuVRKHqFjPEfh8AOq6rDR+If+aWwjBbItm0sXxJ3sTyH8kdK2IQcdNBsDL9yILTA/hOopoN
Q0PZxy0Jes3gvdFcqrW9kMWBRYH8BX2WQyajfxiNtHIcR2xhRrVmxGxB2pxxwV2hE3QJ6zmLY4O1
3Dn3+4kv0i45cOxjgjQogNiBWnPD3F0EslJRg9b1nhiFpHX3V2+2UuYLiEIWIgFnjl1tnLtUwFZK
8B0yCmXur4GDmGBkG/kcskTaEePtnmtwY0c/30pATYJfuer0n136jNntH5ElLGEKKG2ltEHkLnRh
9Du5UzAOXp2hZNDfaXBPdQjeEUJdIqeNBy8PPzHxy9GS7zXPenePGHbeOynhQxlGWwEoEFPKQeGv
CSbYp3ComMrXlzCV7WL5p1nhAlmf93D6okqeyRtTfQMopzTlQQW3Q9ZOUylD/13flkhQimTG4Wca
96XWdoFCnk1Kjmr5PNuPFh9W+aZ6vqmMOidZABCx431DRSKCUC8MSzuoIs7efC7qfvqS0p9zg3sq
e4qoNkO1bm48Z/rwF9EMqzYM8BAsTAOStj74y3bq7SkPuw7pKaYE5Dh/ASKjqjCWBwbFWhekC42q
tAxgidMyM5xAZP183vm9Q1XDbDQhAo41ohwkpfg0M0yaB85qOUiijp8SZG6vtABFeAADhoYU55P6
Fufkk1J8r0jCzpcoiCFijhjPA5uXYEULYsuNH+t/KMpTC3464G4MRjQ2iKRYDI0sTVnn3buhLCYs
TJfNAk0fI/J9h69yZemwLyULdn1GWkSLgiR4VnHUoa8L1lS971zQYr/hygOOP/UE1ngsR5vvFEA8
eo6GEp3ZS+P0MUywlWpkYZCH9DZC8p7ovXAyGTQjOYp/OXnv1bLZMIEAe9JXRQn5UbEYd5e2rOfZ
hCr2G0bxuuvcgi9d3w6Hu7J8p85SsMy94e1e8WJfmmXg/iCusEo0ewcbmgeGqrRmqMZz5Uku6u+9
4HHrQPOJD3bMXTU1VMI64JMNf0n/9ikbvZ0mzGwMw4SxvzZxkb55ual2fc3ltzYuB29yfXyt76AA
jPivkf6+44dGXcTq14csk1tlsaSlB6eh1DlbC1tyB0yZgk4Y/YSthUASxr2bnU1NHMM+uS5PoY9o
rdeBUnu6z2bEGLgvxmp7gQevriLD0FMvWW4CBVl61BrTXVicp1RdtlusfF8I2cCqzrYF4cVu9Pw4
x+R1cQZ+DcetXbdAYippB0MfY3+CQQHaP7wBP63rWj4nYfgV74QbZ4SvNjAjQ/tf4T7s+pbb70U0
KNfr8LY7VeLPNwtvevvxX9nFUJtcLWiVP3jObNixFUR1zRLnPPclrFEPCXkEV7fBA5wHiCg55OaY
L7Qx5gPMmi3ACWUgIvbaoZJOg1PwL+Oygc31fZQnNylaNa6wI8hy/qISR3whLWC6zVouP7Ns9Hl/
UKHUqZUXaDMbjjYxLY3mlZbeeZlxrYkrjGRwaM0qoBR1eoA96dgaHKgu2kbvrruiNmB5rZ+mEcMj
0VkpVd3tytCk348oPQDxHJ1qCaqkpKvj1lTcN+hDpDse3F4eX4RhEsAePXkmayHYpc/17NyRafQv
BRPMd18kly9vLwQikomDbzw0EAk1LgeGef7eU083U1u50z1/Inh17/WXxAM8oL8OCVc/TekBdYft
kdOCwbxL9bK8id5FfcgWM/IyvbDEhrIYMLqa7CJjPTQpihH4XklAgQ4GJLJyDtsxPdrfr8euau7D
vHBzx2uLZCBs/jQrfrgH6Kcs7iTbC1e0TIa4iYEaFVir0BxI0zHdnOBRD3mmn3FL8O6n8buSaiaA
y1rWUQw5i3ngFM65uCV7JlTNFF2lpBq0PeKkGDJ9S8D+zpVeLSbqDy0tbP4Q7TriYjko4gLjEdXN
fytigTzckxJtGZKucE9gDUtd1GJ7t+zEpPQNQOwFuuqwreI5XKxKR7sSNsLrEJnzLzTI7kSx5Dxe
KHdiRqKupuXFrilq4JSxhg0YawM65OyiOXMhHu4s3lF5H0AKhBcPAIposKrrLhBMPRJdj0c9G5F9
22KPtmI/WSFSvNM7miJiUzQ+OX9sjpCHmVY8qh+uvsrBIZpZBN30X8DCv0xvcHJRCvV5q254gkRL
tPxd8+PqeceLEl6TBcCSEnevdeSWQZxS8CI3HGYU6aLY/UlL8lzET0fo5oxTE3UQ12tkLaTn7OR5
UX+jvzuq7XKU0/eQnTo3pSb6durlZ575FyaakMPVOCEpXnKKhGVTqiIjQYKyq8IJ7zZDf74BUBUi
kT3jSQGj5E9G67Lvh25nw4kMWS0OB8Ysw1bJU8Dk0T6pdYJE6fhUM+o5pZRz0TXhSqR99MpBAK+0
0LhTs97xyIpKXKo0iyjyp0Cjm7jeHdJNTRLj0n/pmYWmkXXduQbhfiTS1qGIpmaMfQMHlN++AH/S
ZgcUEgjSKukLtYxgNfNiNRajTa+X2c1nvOgLv5127fXXRgKZFGEcEC8++1BRKZmhU2pM6P2pkQJO
N9wX1CC27q/zZOSAZMk8NQX06498d+IHzH2HYNKCLvKUf4ES6MRO9fOaw2QfKgqnLj3KqFYsgktd
rKViMKdpPxoCW7hjQ7Fe9YD549C3ELvhmjIYXAvEAegTlliSFwGkhV/wMTVRyDgQAJNaPVEyq8Dg
ccb6oDvoR0yaN7tFaUrbNQ3oI7cFfWwHvarfh8l99evg7y9reQiqlz365eDfdwNdIpdMyKB7jxBk
P+sOpRfxfkx73ahbDqJ0ZOWx2EWJ0UkwDp3IVHXjIPwhX5LdffQMgIAao2+dVcvMmO4SwiFDPZQu
+f7A3rphnYWfgcXMQZwhJXnap06CYzZyUcdQpTOOzo80ED11YkgBqji8afjPeHtMMdBKaqGfE67U
grBAAdJk6WBxHsnueyU4SOEIEPlU31PA2SHDra+fx4KA4zNThAZ5/AVbqL7DnR1EybtDLsMgXeiX
N54VHlphlkZ61nJGql9Kt8Ct//vdAdR/RfriUAMSW84Mbi817fdC3VxIFjZpooZX7a9eSgI8uTy+
D+r66Y7yQnBpxhWEmfVLVWqSLyOpQrZipGGvSPfJ3jJvnnR30HinAXWo9vQcl99awHQXhWG2uVJy
0dcPxLLEtDx6+7kQtTBdMXLXnLWlLWdNWvb750UPgdm6QvGvyI8iEHtpTaNl7TyutsrdUEnZChmD
ggN3UDDtr8DhgNk9nD1ZduV4UM3FnQhjqWUuWk+Rq6t17biNUinz5s7qYvWiEJIoHwgW+/U5DXI1
JwdVopvzOTRQ84RA2y2K3PU+MCNjnpvuQ4MZSOSPGMzN+u0u5ZlUProTjtBJhvSQVUhfVupP0o1+
+KsYxQ/itLDGNbE1LpDBwtthwxKhODhYHvdGWkwVQjFoh9oLBu0prNi7KsMSTQtpnYgH8/DAN2Ii
ENaK0fp75UDRtNLE3PFaFohPrnRueme0hE/pXWErAxmjkWf1p6fTulr3emYpSsxgeOoEQ53aRjLJ
zxcFvfZe0SFECigk35ZvrIR5URZ8sNoKb8zM6tX/cYCLdJn9L4zYZc73p+9E2tzeGP0OTXhn9aJO
FrbXSj5TwbI+ltl6jyInQIDYScyVvqzLRot0VZy/4PZ+9q+Mg8G3z8vAsVQLYsdd2XMcDbLBRUor
1Ewlanvie4k+JlcELZKwjEzHLoACA1LdCenZGvjbx/PRHVmcV4wsiWBk8ZFNCh+52W7LZSs5z9P7
OJTdSCEEZk3sFovXs+YG43p+aDXcLtL8HUVaVWgGBK0If+9qA6yC43JavLANT58G886338i4DIX7
5kgCmicLIWsPQR4BurW0Iw8saFxGaxtD2noU2eFAbHgQFjGTIWP09y8qpV77vMq9SP0T0sHfPzUu
Hk3P+0Xlrd/JynluO6ndnsow3ISmtxIeu45f37cimjVFQmCF2osr4wdk9M8TZb9G21lGfbBWLSHG
fYaqrwjslVE4vyGvAXxw9Tv/Z8+bLCidRmDn8a1QOGRn9CRAWjnbSpOlRvXT53Xt4L66GD2R9Feo
hLDufrVh0CFGixTxSEXBl4H7/9qhuYjkFVoQfQrLTrjcFnsUDtH6VRn60Dmd6li3psPMzENaSuT3
KXUhq1g1Sp+nha3YxFM01173Edh/UO5tLYZ3/cMCYGHUNaX9l5MbaktqHqmqROawE7e9PhVld0i5
WoroKqoOXC5JNjB1sIxwxZCOI/WHSlTeoM9ccAK1GsMjTdGYyjoFWDcPQGpvIcubZiXR2aoojxlU
HCUAv+OCBjeiGHUvfrbxIsStWC3LOmI9ZvMa5t2oCysNrVOpw3rJiHjORA1h+k/gJAjKFNJhroyZ
xMUXPwzBiHTPWvj4RPwV8pqGysNrAT5me8BZSNGdvAg/1v/p35DXStx55T5x7peVth3j2ko3w5Xe
spoAt4EJishNY3m6xgJ1CVKcOAPxWImg6Iyumn3H/5fc9eamR/d5U1VUshlHIs/ZCoMHBbP9e7S6
ONUqNHFYdpRIr5jFilQggzhzImKR8KbzWj2X1sUyoWqxUoHjFWo1Cldoab/QeN+TODHPOBNPGq99
GchuIDa6XoMXdXxo06OSRw6otdRxMVI3Mf8ZFUgFuFhbvSnpx2v8EaeDzTd0ej8p9bBjo/S/UvXN
oiPA871/ToDO2FuDTR/CK7wvO3+ONfxmFTghmrXj30HraZ4N07SrVZ5JtMH8cNdKQFnQS8Hjc7my
hOr2aVxWv6fCsqIv9nlvvAc16eX/xIZtyEqiIzrECtwM+CHg94dX8ANj9W+rjeqvDbkFqleJ9eoC
uXw2PLlCrkzpakYjYK2eYj+MtqwVP+znsvE8yfBIdqBk/oLkbbsiTma31smSq3adD6n40mZfcAMd
jSZ5Mu4phni23B56sFTabggD/n+cWroj5ForbO3kPMZ5vgP1xka9K2vc4cyqYTTa80mmhtNNRA23
H5W/M2fzgynHod47CfHTCXMQoj0AT96ZsccEbpjVLW6PKi7VHeCWdDzoKTc41pGyNodknZSGw8BM
34FiDsr2ur5zQoQk63JJ40207Cy8aaaFbNU9E+TIZblhQqBAuxWxgn7VSUMCJSzcQXJd6/iv82ij
Qa4U+2MxbH4RC0pa3+UGq+/uqqqqEMER5nIQWTAWWN5ONX1tvayBJn/ZDMtKRXDRS5lTUNXNyKhN
QzVJwwLay60EBq1Igz9eL20WPgxunlbY7Agz8j4JWTgo8FeuTkcI6//Dwsz1k6Jx+XRX78R1mEO7
5kDDSIHDU3hJPjQW5ladfzX0yghffLzUD5uu+XDeGnGKdkxddS8MPE7Qkfj64XgPISbhgZULEHE0
xcX2+2fRCvKZ+MDnBGyg+zuUb5j5zCNHm8SzNCtJ+VwfDizNeQ7wKAL2La4Jp+RnOx7f6ZWjXQGo
zjiMFzQTFNVVwZIPtKKWkgfiZBAjSbaMj0j6yA8vWRZRZF9w2mlS8UABXGvOp/zpy+UNR30Da6dj
fz92RB8ywj9QYMXND4fkaG7B+6TiQW/1PSMSNXbSi5o/HuA4A7M7edqqxSDwZAZ2bkvuvAg/lw3G
/jYpLxoWWaUcJQDG3qvf1BFyWdoRNEAEKAGEvlaRG8HeIT0eJDSyip0azlckO81KYyNI29kJR2SY
6las99eCBF9vB8baRybO9uX/t2qE8b5Cep7e8XXUgpoD5tRX9+ufFIU8bCJCMvtYDe1usvEw/XNN
Bon2Xsmq3Bc9ShSuWleDaIRbVPuaB+Nhve7Oo6O9oPwKgrnLQjdLixCx1lR+HbEMEsNqhoe+MOs8
JhpKh2ENKm4PaVVVQ5WabMD9B1T/6u0H5PpeKW9zVrQXcGtYQxRICpq6hG6LeyZkYu2meYWefRdt
DRX79ZqZ4aeT033Joc+ZKePnrzLjZgesZ7QxCahKi639/t6Z4/+hZi45ZK9FML1FOMxhGsbFVZtW
bSac18voo+gehxj+p5w3srKk8mjUV+fy4tAvzukJXg6nmlyh0UIkaxOUFS8q8XZUs2rYMvur7aRp
yoMyg5XTL9j3IWKxZKIubWjPUcnsmGVN3x1G/FRJ2mNVn/ChQkkbcFByRV2eDvr4YuAm8HyjgW+K
vlCIAXGF81GytSElJLftN4l/N23HQkJwlip4aHHdMlGs61e/rUMli4BX5sVFRFYrtkaWKSC9rzMD
vPZFczUVkyOEuZ+4Ufn1NNGPyw9R6jljzvRSlDHm4zHajyfLaA8f29cgRsVGJ1fmaBefzUMVrxFl
HoGMy9ERShDAjugr5aKrxjzoXOMCYEGpxS/U/lZ2/9S0yFjdlKJMl04MIWLapj08ClvAZPolI2+I
OrkvfYHYPb+bERK80HadAx7Z/fVvSWylSDvDJsoaJdUgvj7h9YE5CG7NshBJ6DBDtHkw0gWItUz0
UAt26iqCCizzQ9J3W4U8Dxn6d1WkiSfUumWRV5n+rjp3ye66H2EW1foeRc9YV/qzHOdQtfg6Fgjo
xssZXyfqm/1CPcumG2wVAE9d9vXCfbkpAGEG2Y8RoOcLzikN6WiVUPyH4SdGz6nUuTAfkKu1T6Fs
cKK/GwDDA8BGhqkfrI1biEvErM105SAy5lp90vt+xp2fcmX0vV3ivCpT6MJE8wRMahufBLrSjVA7
DyCNuV9ZcoeFLnlPWlsDlBb2SnAiEhOUt4uXojoTK8DERi/H5WIw6Bv1WGuLnCxH+MlUQOBlpjYN
H+Gu4PSzVMY+PHmSUE3LgheFxsvxHcua9Wc5ZpAplWcj+Qn5wFkLa8bitU7J/1AZElQ7PqLOg/Uo
sOduiOW7Ifed9SGxmdZK1xqn3jxE2mHtV0WjcBWH1BDsr5teOhUALBZtEb+gnB+VmS0hTDe3GGxm
ftmiziP4Y3jLHb4TYc/KbTkex/wSyI4INhjM1uQavyQGT1oDt4PpFLs3VTTIrNRwCDxNxoO8gkIc
pjCOGIDJvRYZai8hgVmFxLpoilF4xnz6kE8h5J3QdF00sf6SZKkpMylyA1t9jWkmPupb5293IW3c
eEEhBrsjP3WwjpXPQ32FTokWX1HLqbvHIBpHHz1jKKAzht9VbeohcVnbA8soxXTGaWz8CpdLNZ6n
jdh/febqf1z6FZkF5FB27vSjsGW6xmAHa7COeSCbKmJ6w9ylkJrlO3KvnCq+aQyzcJ+W79CmxTPl
ORYMgZs+lMuoFkDI/Iu5JG+H1JEwifMfTCcojINUmyY33zR3lPyCj4T2kKWcOhSsID+AMjHNSxhZ
GTeoyXMOktMqxtLCoJk1CEyDDNKZM4Q0oKPDB5p4zWUKWtUiv9gQC4iIQ8K/YiCDuk0TmoQkvJL5
wDqgg8QXN2CeTNB5bcrtsxDk3mmg7+Ijv6QhWhYiC9xqlCvjfhCBRdB1OPjCmh2bZISCC0Obzjhy
luVXazbQ0OhbMXzBdp8sCviIWcudaFZEqicx/y6yZUz4pLiqPAY1gZ43fCCRiDAJZUJZTUzypY9L
DvsFb5rxiLqYLWLcmlTiPlgMylQ7cEDOp7fMEqTfAWyi81ubU/PAdas3vXc4YR/JMRApX9CuqyEx
Q23d3p1R8tJEC3AVg43Q1Ex8nYU6mWpSub4251rwUviHsvFdI7hiiY8Ifa6CWNx8XvbibgdGl6J5
FEl+9DmZB9eFK/oeH3X0AMBsdU1xuTI+8ydVR12Gaz6RLi5KkidsOEP8QR9ndqxSg9yoXLncc4fD
6YAM0pQt0+l2+qSGkgvQ9FdNKT3q4tayJkT1FOsCD+aU0PkkpDemWNjhGjxcWEh91qRLcpSf3apu
GVsZJLvdfQKYszx6O2kAtscKvsCwI/WXT6Sx0DhHc9ysAaJ+ohhZvdie5AZ4+Z90VzEJg5jYLK5z
BVmRiBPqoeuHzVLfGgcjO+E+Dk82DlSAxuPMKdwL36b14ko1vl7xP0fErYn/jOt3Ls0DmPxBxrjf
6+JMwc7Ab1nDbbcDn3+aJKRRVLs1x1omm5BxJU+PPDoYy6AuSbx9WCIGsy1/mL8w1IYWF27f2drd
ojJU3Rtzy2p4Z8uTkI161WZoZOk0CwR9FNiegE7rXnI//1UyPbxQU0Ts55GNz0IDDrhs42d2WM2w
DIDQPGdSMSPQRDSFc1frm1SSF+ZJZ79EZWTm1cf2QSIPR63IPrIMcX61RM7iv28CTUeFIDoFrcHR
jZgaQhFK3ssUMI4jeNyZA/FwONMfQn38qTY+ZNHxo9LyR+KPj55Km7ij27LvfI9Zy9Vi2X4dSE5D
0MsLrsFrMdtg2IO/YtI37EycbmZU4N4TAejZ6+MPUnBaUdBPhHECzmVxvVaeA4lEW7R9RPT5FVox
EN17jh/s8bmhu6qOQmy0saufsNqEzsa4HXIHE2JRUCmzCJ57wkmIgIl25BhSwYEtHaoM/sDmGIUY
txeJfceExt6tpYl9KNJboCEOGjeNNdswHu3uD0XY9lMON2i/n6YqB+1vZA4R0Lww9DhhXYi8uW8F
07aXIfj0xgSPcYuufMHjbNJp9Wk0xTdcBINAQ+ls9eHp4SnMEwqy12eFDwypZ5OiNoDGhL2bNxW0
LJsuZjQPQlR1yiO1SV9ma4V978MrFn1/KcMDhlkZH6CZkk8tJFjcI2nkIcDl7iakpJXY6WoUQHDG
UX9uWuWIvpwnl7HE5JKS95cB4CdN/wo3GPqdqMVNrlTa2yPLg8irDYMAKOxKi6pKTt4ZnvifVdWE
SV8LKy+0YXdxTWU9z1Gy3kDRgVeJNSmHRTzEXIZFWiLP2EYB1hJjj8gvZypXb6YM6/FQYziULIi7
iI+t6SQ9lB/o3jPIRaJfy5iPtjCHLGZ1t8h1MkTXjC/cE4exeIYb/BNAVt+H8CcS0hOTVWjz5MIt
Sw/jKyqWH6d/qCfNqUwXEn48Bq4QlfLtnSXTP4vvx2adfOL69aUbRJrdPqP9nVYDZ2yIfx+L6WMh
kfX7pE9a/6Hq+tWYxAF7tJ3jRPYLzB5ov4D3YXSGhg3P3gr8K42Zckice2aEerqrvBhe64mOSMVi
W+QVXXFHOJ/DYH7JRMr0BtRTlQyyklUCz9uW1sQtmUUghc4rondCj+fVSwJwc//ztMLhJCyXazNh
k/696bSleu2eQSKnEgJ84dQjeh0q+GhuYF9+UCKgrYM5OzDzYl5tszS99JsVUoIvlVdzWDtv37ot
36ZC8W/xHFJRi+J//V+6rfEizNSGB2ayq+NvompxmJ8434T5ArSr5WTDchJbHHs6i5vlyyRISgjl
KPYfCSl4iVwoREtGerr72kzHEN/kkwOwnmrJg5KFHFLA2gTAcoPD258HhUwCQq6iG8FtBoKE6AU2
c+LhXfUsxEB7zlmMCCkjx+fuGyRKpuBeLYNfXbKWqlIoN3jgMXa8Rfnu99xkmwTBRViRKGDHvhvS
hmIL1P+fSJGgjr2v5eHNhUdFG6sVS9xmwgSPVIKXOBhGk59eLgVvZHeClKj4MmeI6Gf0nY4fHRF1
jRkAslS7gXYJRqmjXgqsv7verEtnFNuDfEsFmYh75749mPUlCxkiMXVRk5pt3AdKzNvnN//Jug30
y6ts1CWbK6CnbAoj9vGM/DagiPj9+nlpAxf1M556ENV0YOioJEEBTPHdc6XtBrX0u9sH1x5TjFVD
UMK3+xGoNfhx0iRpujASk7lMAAn4ZZ/LXB4nI6SXbl4KgEEDhKncXZ0haaKHnx3Cr0EWhq2in2Xz
AAqP5cq6on7GFxrNJb9xc/mJ808KAUtmNYUfZMlBQAp20VBPdGLyZ7uyuAo19j9TTfoWPmtahl+j
qEdqdbHZdCpL9FEl4cY6DXnPcZuD5GaxOYu1BTevfgvGf2bfT9U8/YTCgP0aapWEaHSgEBNvTBL3
Xt9UY7vPndvjUn9FhvPClwp+m3igEIrYNnHROnxafQW2vh9LUVsXOqj2zAz6NCJl+rXHS/eNfCon
Zhaqkn6IHjDCFwSJrIS7Zljw8G2B8neZawTdYqFuLPv8yNO0+IFoJiTLHZ8fnND0dmfd9TJrWnnB
pjX4eWDN0ePkkXOfzhSBz4ribLo5oI3UGfaThZ2kKEzFPcebeB71pQQehrBZnOOjijtnByw1hP+t
9XY0XJ4a5Gm4g2NwVpqVPyM5kU0b8OCCDBZcLFCL/KeWopVJfSWuFE8VZl/w7vExqJ7P4Cr74Tv1
B796J7gdFldnNdq7iv9XLukRe+eDBb92tjj9Tf5qTgMyJT3RN4jw4LGJ+dFqbPu4GtQtYDLdPmMY
bJ2aBx4a6RbO2wVG5NVmrq1k3nvTC8MSKO7uNpnnoVVLbNN5pPq0BbNa0gS6tyrAqOmhX2da57ZG
s/069t+EaGUuIzPI+A9r/MKa6TJ2idV1l9PRs4dhtkddo/y+PfEds+BElMrqR3ZbvVcet8OCgR+e
BSchcHzlJHJ7rFYk7O+bumht/C4Yzv6TC8Ieo8IbKDc7pvUnq/ecWxEa7gddSr6eAUgc+JwEhV7Z
T5L9eAOH3lJ2RdEhT16GR7Oh7SEzkm2iGzr2VGsjhzKD8+oITSGErtHHqK2zPyP3YOU+sqISYZTT
EZm+b6/F10AsHH7dO9HV7FkGWfV150fKYy8MMMSLqga1SaVIFOLPJck7kQqsgfvq3nHFSoYid4FJ
+SAPZ3nbkyeuiyM6vr7e51WdpaIgPWucDAbg2/adv11zzd224s0XRMoSb/6K3pz0ynmQTinvnDu/
XJNfZPOT5J42jMV7cbm3nzByqbv32VH2QhgmrcNRGmRSVYPrckQralBaMyz+KfMKj+eTfqW3pGuE
ZHeqDLK3NGD2Dl1OpCxBN8O1Z+q7NYKZyBRapkKseiPG5MholPhgGx3lAOXK+19kYkxH1okcqr4q
7eKIvovCobYBoO21Kur0Os3CzW9O4PQYhzODDLGLsKCjjRtmdbRu4BxmcL8y00QMytz/UFDKtNn5
Iv2hdVYfuVpbRN7M+RBj8OMKKoukvGaNtdQypwPwrzmGw7LkH4nvoRHF7w6/BAJJWdkUovj0uyuD
NBaZxESPxyoZMpiTcPeIxGChQGv5ZtaCw4kNZNP0NyFNhmrbNmJ1c9fH7mHKElhiQ9uXQB19KDMI
QJGLguYMO1bXNoERd3nYhYTOFUW+PSGj++b4BeY90LbHhQ0DVkGNk/KoH+EjZuFNXrLfSiS3gjfu
cZHLHQkoAZu5yxY4oXXuTwMeFCEoSjiVehLWO1ETTDnV/08QIomNDQ/wLMo3S1xhe82ta7Z0svsT
a8JjiVBSE0IuhFg4BTnoEYLbgsNua6+UV9iGBiE4pCPyelh1I4Ny1mC26F8jQ/ThbdGa5bX3Qqhf
76WfKbXLlxvdMNn80VBKTgLYZI2K8xumVpkaHaD6sxCEp40uERG9NqZqQqQ5DAE+fBmHkr9fW51P
qfEu6edDBVwnVYi6Y0qE8//NWckG+sD+IeBlVQ7toqbecc/t+rThUdA90UsiRcb7o8OCHPp43xdf
AfqDAhY03Ylxdkc6T77Fe3S+iFmLHZPkArWoB/xWmuWU6dGQnJ6HNSqGcavlFBx72TnmxJn3wAyy
VhQh1iBlSFSKzKs1CydMlTIjLwS69xkUMHFEpN+aO/ntjxFPKlJ2N+YBBBMDS5v/M086hAEJwIQe
fxmM2lBa/3og+PsklWMajFQQzg1Z2Zcy6kTd3cQPQVhIkFufI7YsI6froSWy/yAAPovFDzzJ/fe7
VzOmSJ1Sc/mpLCHgKvv8zhuKhayyHd+RHLXYTiiEUm4E6sNDmX2ptCqlV/Hg19JxISYTlpC8P9ai
4LiQlyTwqreC7zI1YvaKx1U9bq2gm3Q783MGjM+si95/xpJ7zNwPe4Ffd2wGmf+rPpHX+zZNgFSE
+N/O07wx877Z0RGwCmMx0UsmFncD+LNUFG2zgvU7olxKdCe5HA9JKXkiIYDHTmpaOj0X2sxi8+SM
LQsTy83he1Vkv+k+JXrih+LIo3pDwIgDkOo0u9n38KRFo2l4Z494BFiZv6vof0XZ0yHcFS8MU4rW
DX4BxbpdrSgzMiMtSOzPWXZshofNsvmzV6hOwtlRRazdfe6iJkAjouwvhrzHfqCQQ+DoSf1pYjjA
UGqWaVqzGaT9AHxJOO/Y5otoBPPhqzstT/6+xsBWDDNfdNA/lpj6EHF/V/mG71zf9fO+0a01Rl3W
s5A3zNg8Wlp/BVSOluA/x8sTva29xSA1H7oNWmTD/fbbj0bXGlS3mxbwYAVB6JUb49j4tgBafFr1
JfyHSgpTcp1sI0s0tm+JERKuSJ36P/7IGkfOBDIQsTtMeFq/j4Rxq6Dn1cmhakmhAYaFwKqU3Cpx
jEfP0Y4LK1irQ2eQE8faw9zbbnoFfAu4GjvArbtc7pciVG0ainZTE6YUTCY1ggZFtssxf+HLG0Ae
nNMDNAJ55QsVSOUrlFZcY1uvB0NHlJvpPrfu8MOqls+fG479hB9T1xeGXILsyrUmo519lUTvsYrz
+ikjo8cmOqGeo9QJq1blaC9y1+H+bwhrdVdMW0syHsShsCaEHetfn4+On6HnM+Yikk/9GN81rPSU
vdragfBjRB6taWp9S/bIg6mIaytT0vr1ynQCTKXeyIMDTpuna21KxYDyIkpL+QNkaNyhwZZJxjmj
ZDtQHmNqTqG3pYdaOjjg3Gu6YDYr4fqOTUZcomGuM7buQneDynSrtfsuswB5/MP1LKmNj/QCQx08
DDBH7oo+OyJFCGxsHU3RfUGVec+GlDDn107KPj4wZwYbdkflMFd2RPkPFs23HfDGiH45WUwxb8Gr
V5S+o/qSv9M8VOzzUlTwHUFpu8X1tIWZaECTowT+tH6XZ9m/1qLMr6POzXZod8wEFeI62zhalhPw
l1wWt/jYv+CC/2VZeBbVLqTxUWVfFfYfLffBox4KCIh61/yx1O9pQSCCZOyweWvDHpPDpDVCiOi4
RGr0ar4uq+dALMlGTRRMmiDIMPfIIoAOu+3lnHdvIUSfDfBfHl4h8hX7ysI/M+LL/cVPU+D8mrUH
BlFVcITlT5L6cYm6lHuTymSunNfiWtTiY59S0JEQiSJmZC7SEQgEppDvcsZOnk5j8QUaKEjOudGN
HLXMjxQxD+KB6K0wCEjkqRcrdYVM6xu0r3JZ3BvWudTmSvET44FBUZmOj0cMBQLnSf2SJfkvr75J
v92W++LARCJlyUbskB1rtezdA2RXX6jyZ1VbSN1RrLUPZ0oh/btInqqo/fzmitIF9YRB2iEVxcp2
mPHFMkqlZPrYr2SqALhY3vsmv+X7CNYTYfgzOZnngZbFUTOGqZuzg0MSHYtFYvF+xVGprVUvq2Rp
o1td9mejtRGbUZdf93zHf4yM1yi2BkhKnmbDGRhCHIf83zWTlNgA0CHie93cyXfnY9uL2bWtjZpU
v6gADTpzf3IVEqfs6hAWqNob/IEDsfk/rzAzfacCH02QlZJNOiMJLfgg9DRjyodY768zgDEKbWlE
j/ZyC/A5gB2bFGEiKfOhYhIMSratmdeCDjSQ7pXa4v1m/+uAS5kbmh18aOKaFpUY8r2hWxX5K/9S
f4dZtJS9CekVyP2Tjm5GU7iYeG8A+nkkiWLA90JzD11I/Y1VpiZhb+sj5yBdh6w/MP9TSf575XdQ
KE9rFRuZEnzFR6BS4q7JVH3tmVQJinTvyXPlCO8rWhwqp6y6l1sAZmvCe9ELVxc6eoIfnIiV8BhZ
SaKNdf2DNQV1ZfG/t6z0Os46KxjMTEO6aU2VxBsK//vcbp4haE8jw3rWn25gX6qsjUPlRNE6cgQ0
gAXTkor97nOXJulKxt1+4paj5irW0+yVYVSd+F+YRoDDoz+/y+rXaz1FU1Qr7OsxiemYoj8ajRZ/
h0HbKGMh8GJEbgzIm0x+aznmzbhTJcJoA2ptnrV5KtaXmVff9LlLjKDrqZ/CCk9NMce92JQHhf0a
q7UDu/070E0z+ksw21Z3WOuXO/04oXM8MXEltsBbCIEdKL//pmBn8GgNDW+chHuiDuj5C2oRcLZQ
I8Y2avt+oMMNTAVCvDoxU6rE1foJjKoKoky3SBphzBwBIeCu9FeQqmFqBkKeO17+c+PF8fsHZV4x
aO3HjmmoMSmoiK7ssJk0DUTk35B2Mf9dIv6d+0AtShcWl4RFI/ux4AUepQJHlfTnHeePK7632fAZ
kNwZVH6+4+9WdaLZJoCJBX/TPlq6m1D3MQfCFvaAhppIPIY+H767NRx5rat4InXL8TAE9PGDsGd5
Cp4pJX4hxUyDkDKJipOvixhg0xSbe5qC65jSZriVsUHSg55PcZov2FEQBs0wD/iO16w9t7zAmjiz
YSnVbDibaTbCKiCIvhTZQM0IC8IVcXNxBCcby0uGG65os9DfCM9pOQF47Obz2ahOIFEy55TgyGVe
M9vS9qBcrtF2+vAqu9MXUcHU1hjBm1mjkS0mJ+0E4eIjjWAAZEi6BRgQvaAki64pc63UBJI6Pq1w
TCgIWuIHXq3/xEsEfTKUEs+nl1zwO081FrIdIrElefrrJrO9fJYeSEd4a4nJ4z1HFLElWW1kPxGc
1q/mUN9qE0p0+4uEbvdKsc+OKm7mVeeKU4Y0JgKD9Rw4Z05mJ4EXedcz0rixgHa5Wpnc4NtBzYoT
jPnADucVS3zMxqXaMuJZIspHFO22gDYdp+MdamRh3zni0nxTFmKDiFxPwSLlnvwHoH/xWiZtuZGk
oCUBaO6UKhOh2KGfcQKWfhPoGLd57VR+vDUDbgqVUzTYv+zQTnVijO1gcxpU4XdX3tPO+na9aBec
IXkbyyKn4M039m+Wz535bFthMFQ4B1tFmwzSE6RkrB4ugPbu+scLA1hJ9IPok2rknBl7KoT01X6K
Kd19ixJsw73UgvOZ2o81kkEuRD07m+46iyyt0tOj+qARQDIqXgftwHUXcT1tlXKiig+VMfyzHUAF
3pfrt3Db9ZsI+7/Q/r8YxSzBjzjyZvWJ8N0yUdjKk298h6bSEvODM6/2h6w3jYN1i8j6q0/B4/+6
4onCzUd1z8BqQcJ8rvKv9POa4GkaCh6P3wXXBwtWxYb88sHQHgK8jt75R+uYEgJ2LwzVoxMgNXJ8
jQ7b80jquhIp5uueh6ObSmUT7lUvHnGJ5NpKelS+xrv8pbjEYclvmbtMeDmwC9RqDTUJUD17ykRd
TrxIiBAfVD4CCuL72GeHz/8NLWgcUZbBn+dG7B7kzqO6WvpdUndWPaax5rm0jPGoClYxPVLpiFt5
Q6d+trxk+AOy0ugeR98Hw/Q0sdFWNf+hvSO60PdyofrhbttcK4N4u5eQS9l/CIflc00mgU7G8y3d
NPpdpqs2ZLofJTPNucsSIAwndaOkB+V/UUhTvsP8UwcHtil5sAYsM597nuqlipyt0f5tEVT96+CZ
QDv9Gl6NXGCNzAj7SWDibg+U9EQGX037PrZ8UwaJnfsxEWqBSpU9uYPKb2i2CsSSqhn3twv7K6TJ
/JOYqEOeN2xyKuOubF/DCHyaSek1SuAVLaEEB8wc/N2DE4imFtBFANBDY85BnIOikMTBX1bU6gud
9as3kjvNhWo7U4E9jUt0RU3p6UYvYnnT2R9gOKaZPr97ZH8FSEnzCCBs4T2P6L/cAIsVNvRhmIez
VKUvp9xmaensUqZgkUrpaAFaeOVa9CsXjlGMlsh4ljMJT5CWwwmpk63AOfod+Hlk14oXmaqyz17v
yjsB3ywgcl6oddLYTocjeVwnAGnZQxWaooedA9r7J1tPOvLT5BsMTVQ1POZjiru81Z33viArerNW
/OLHTEUl8lLBQOkt2IPbR3voClJdO7+9oY/d0GF2JJzJVaeX7I9ugibipuunXIoZn5jrMm8QFQYR
LzQ+LZWZJtJTrTbVBE3x0Su96FrwF0tZzSi631Mg/mXpNOHXyI8miDoG62h7mWm4CjE0XhoqTB+S
+EzM6G79GWK+/psO/QDtwdCZ5GVX1qavmeV6SvIbxQkTAKaOtn9SQMZr4XUYAZuw33Nl7df68631
dvJrTv15DAYTsFZVtflmDrl3hg1zYAtpEqXPTMjrYJk4COy1qNZveVk1Pg2ZpGtABnuqxsvBsmn4
YMJAuuO7s3wvctBZ1gyZweyzWtGzmeSkCX2SUtvAKTwQbZrtgb7XYp+zDzBmRhn7GJwdSAM+IsWQ
ftCIpAHpQkt4Zn+g5f4iX3qRxZ6VfNq6DiievSzeBBOsewhWki4Yekq1WNUbJuy5maXeiBgDmqvG
kRatXO3ZzRoCN+0TcifHnK2m7PjX0KKYSnogngEKm8a0JpVIAX4uopo5gr8yrLMitS3O48i5TZG2
kG3HPlwbgEAJ2OKp/MP1yXUoO6lyjkJsgDUB97wdcEiN7fpR6LfRkORlQ0Cp4eZ77NweN1S0tDsi
ONSXZc8e3Cxrz6owb5mK59j5s0m3guYOio+TaFOEQVfP+T+ldX5CIjc5cFi7VxlohabCuoD5X6xh
kl5tGCA/ZTxoVNWJa+JsRcGYD8Za5ScZn2RkSzJ+PF6pg/EGMuXTsHgJVd4HSkbE+caKuAaX6sgi
x5Zh8BJAYaBglwVZOWkfkPOGVia2yAJvfI4XbcFQ662ZFIhbuP9YfX9wUjosbYgHR5negQO61Vl0
GL3MxfM/y4m+/BHKrmW0aPygsw3hMKibuZdl8F3Uzu7SO4FQ9ghweImrgy+RgACjgv/8OUn7B/fE
auw9hEqfHWvjUXdRw3SqEdSCXQqCvAWSv1rk5W2soWR6PNtY3D/SiXlvKlR+6CRij+9Seu6wLY0/
nDzWlvnn/jwz6OvI0nZDW0lB5n/QakgadOMDP2vQzAd8PuJtBcTHvgyuJUZ4LVDaUasQshU2DQrb
Q4qDpZ09/Gj+480+FsKZ87WgfjMl4kRRWV3oARkCT0KeZLSxZtJFPjges770fpIVY2uD36WC5fL5
4c4LQqAbvElT5EwKyeNDYjL86OkcOB6zjrTf2ffSiRxdtriH/rkJa3g6yKw852ij85SczXGHvx7q
MydLTvGdqmvfQVykcdpemz0z5agjPY4voMEaBX7Wm4HqT3SQ8JX6Rxslpp2pE6Qolem2hPYKMs3f
JTF5KAYOceSmd5N/CfQcG18hDoTQ9Du7HbPRbpzBX4nYi+eJRbWj/ijON7AZ1nhzMdtUniCYJmBI
y86MVup8m9ZNYBIs833jYgMUUWGhKKQoCKnK5KQe1c7L41TWeZjuP/6v9Ukg2fPVRbLu4UUksyIp
AhgnhViAxImREDAGtkNvBK3tacWVArl8pGhZeNGjOLaVEAi9f4NobkjO0nayqQAMpFX65ho2w1sx
Z3XKQJOhtyqpBBiFbod9APrLaV+ReEtR5tytCmx318Tsec6pnsIBULdC82a14tPilfZL7FoUq08M
idDl9IAwh6xQXiUTvgXaU/7dB+GswPUenXrUON0DG711ENXqPTIqKCME13zznQz1+yo0SC7LspuU
rVBPdadZ4CzvPvmurmXBQliRwCc9oNfpSfmPYyyMbvaw7TkumjoXffPgUhn8oUQT1510P6VPjFYJ
B+3rtBv+mPRzM9N89c4jjZCtbSTiFXfWugWRYdRiPY5MqCQPyP4IiQ/qLT1aRdgKBaK7jMFwnc/W
y/IQ2MGj9XAWxvoHio+Kn9W9qKgUpjdQGb4C638kXiiYRiXR85ACELm9law72avWlMglR19pG/GM
WkqYjDu2hEESCfh+83bTkLEt7A0LIag71m3wysJR3spe6Y8Nb7c7Sfmw2qM8jaMO9Alo2AuX9JmG
IDNHx92f852ri9PId7YF9OEfyG7HxRPVyK/AbGxfiQo1FOvlJXojYqdKHIIP0E7l/LyUt6TzD3Zg
tyBwrKZjZNDY7MLPT2rLOotnlPDYT/d8ux+CRbnrGNvKrLgXrUYm+2VBZ9WvNs4BVUUBULTD5023
vBnW7wYZokndv1Ma94A/WvQVJHJalN4DQlfXDQT9ONXspQRAVOLkVsTi9xyShIjcYS0EyslFKgl5
cVWpBdB19CckNmxadFoDFaxFsaHhY/+A/ol5lUNJ1AiDGRz83F9lWTI558nx7VRn0hpvrUEvZ3RF
9AveNRwySb8DDhTL15AM/lSLL6kT3f4SYx1ZaFyx3tmE/sgn9xZXC7bVuBMLfR6D3wakvTm3o3gq
4IGqsyW5E1EMBrZx28NR5ygUbiAR6f+F8JpqnI3Wrszcqs5SsjBZ7ToL+wC4pt38z5ihxHxBGDTy
L4jh7xcWXlIoNGV9M8e72rPY1MQtMVSaRfGXXdZKF82xkVpM27KMBnQINDGOp/uT5X/nWFernd1O
qGoO5NpbO9PjEFrKfpfwh3QIZbQv4ZDrvU8Q09qH9e4XlO/Islu0jo/C/mlTkoUpmxGJD0/RVn9F
Eg7n1Fhlghi5P9LxzSFeM9+OfHbkbZ2zClVGGt34mCRMt9yGofkv+ITtgthmNRWXy/XwAf7kyydO
GX7NlmIDoaHzIYJ6xijnyZzxmMkvQXrB9IB8GS/gvZByTL+AmKV/swu+mfOUhmnd3JKApqCQsak3
jCuyM9WuX6t12FVNGjToVjHIk9BBGP18e+1dcrH6XfVLrPOyznqCP98ATw4gs8uaUrPDhR1mEUio
8g8BNZkA5fnEtBCZGZN0b9GRs/iamwNz6M9SnEICJzJg+JVHqI/tlyK+gskWNPSkY5QFstk7I+BV
XFDODdEBPVMpM04efHnpAj6Z3wCVPKJC37kvd1yGvjKFDoes2032HRb+sBbmyyUc0CcX7l0sFzqy
DpZ7dOxoF47k1iy5lzCSeqNFAPCJviMmuAM2kp3zpDyV9DEbxV2CtcazBwn9uotoIOIlKN2qHg9k
c/VOBAVe6RsGzTHnmc0HsYV5nBFxkvMfYjhxIS5UXXlNXlnfdLBpOQI9zN++a+Xm06iPimZVm6bu
Keq5CtPE3C2tIuBZTN7m7j2oqfKH/8CfI70visLrSHU7NMXHnkJitnxB3TVnyWlWu02U3ijRYlWP
G6NT414EoiTk1++aZJCTp3PfZaEBVQVp240T5GK/tYTWIlESC4TVlGo39cLpBElvZ81qD7oqvlfg
26gcEJeac3IgbjquT1mIZWAlu8F3foe60QNJGJT1TN0pGZ3C9pLA3PvM7Ia6cx6re3BsRWNUoDR6
i6I3ZrOn9ANbBuOQ/zHHVwFJZWRiB3/Ebjt5SCoiHG+wENmNJLeTr5XD/QzyJvfwrjElDOvFlVWb
NlPQLB2qQ0BBilViAsX6v7xHR1r+iY9hWt4KfsbsN7hqituLHZQgN1U3lrT8alR1K7lk+SeWQz/v
Zss6FL6HHI7mQwE5L0NIUjPTh8JAaBVlsL429V+a313DTvepTMMA88DWNSq0JIz0rrjlfQKP83mX
JZatt4ty6SLxZsIn2pxWkPITDodkjoZO78tLrjcM+VYntsFsXTFkx3nQE1lbYdaeRZEQ8mnpuWnk
WkzsAy0T2wR8lLDZjL+11I3xLmyh13CY2PfqetxRNRSm+cpa6EL6TXr21qRLlh792aMhHdto1/Xb
wRo0WIKa7BWfbFNNtUihHlFRiMwEktFFbvZIvm7lyu+O+QsZx0vpj0KlQwuCdlRsrof0BhBSTK45
Bq1KOuSKSr91JtcaKYbhhiwF03iLgcgb7d/xcukn4GW4SXW2lytvfwu+QLcXgZXzbSkFZrwfHBe7
LpHwEeEhVRmnJkk0VU0ojZWu+vEE9R/0ZtloRecNFP61LvKMeP8pKfaz2iEDALjILaNeNYzX4WJz
ROUP4cvrNiRbYtMNMnNSHRVWFVgbnJp14aFuYxkfWqcf/L+z8L/o7KQmDklqc3PZiyfgf/3qHQw8
Mnxk+DCTVyDAK9Y3ptV85WNAIPvBklApQU/5aBHjbtcfu2DEHQzB9c71A/7L3SIkEgpggAH9yw0W
TXZb00nYfsMRiv7L3R3OAXN4Nc9+ddMwim03rVTxSgHpRzKU1X+DFpyqkE2+Nkwpm+joA/RXiy4I
z3G9rMKVOkavKvqTY/KaLScgJa3wfc5blHA9luCorxCcLottQ0O61n5WyBCo61X22uuph7Boqh4I
nxzisUNqMUqXIJB0rtu7Psupa7frIvCvwxZ+jWqbj02l/NOp+W2EcPyxKGULnBZ/cSdPu3RBvRHN
v/EoYan7nLx2PJHuh4eWyetmSO/K5cU1iKsnrLbq26vPF/OQ6z06RrpiEsdxpasaopDgmLaR+r8C
gFgjwSmS7JhfoTbM2qdzZt6ziyHefA1JKaRlhhNrkupGUiacMI/RCHWQ6AJ2x7JER6rNS4oOSl8o
IfEueNR1MvPL3+YB4u/lD0JR2bCq+cMdHlDLzU3NSAUs/UvUupm+dMULyOohhXqAMfUPok16zHqI
IYd6HVX7boQcsNlbo1WF93A2QyQSXNqxmGP7XlynhgpOHco0fkrmze15okF1L+LGPGcyzZYGe6TT
4q33uu1Zktq+OkFGFodPP5aL31vW72Lh+8zNcGqKI8Lp0zmEPp3xaF/DDbOEDMwgw6uQZSNrZVZy
Rzsul43iRpgWXXjEOlAMhtdqvZ1REj5lOPPiV6Sv/KB2bqPtj6rQgkRdZxk5YeKOotRR97vnF/L/
yoOy2zdui74lVFncmDM4/NAFvKgROhyujy3P4vguHEdeNiaEbdfGIgGcauU0tICAea1sFMn+j4u1
i8Jufxw4oF/T96JwgtOCrXEoxPD6wLm67R13+qlADx2HkQUUJN15LUEvn3dgqorJavqGInVSgx6n
fL9Ee9WZYNd/KY52hhc6IvGXRKCPBUxHFoE9QEMgeLuR9HbQbF/Nbh7KHM47nx8x/4ttIwW91f3P
uD5pwwlZYwzGlcfPRMOtZk5LhP1Dl9Y1SQ319Qgzy2RO+/8aMJ/HXViJJlSDawe4ejcaxpAEAabE
9wly18ChILzdkMXl/DL8LSIljn9QrBc3xbMXZfTMMPYGMWr/3RN64hzealD9fxph24043P/ZAbgH
FhCrzxcLnvll4l2ddc7VOFzMwe75ClVkm8vHaTExVpNvhRNcouxoZNflkTgmQKUAygF/FVIJDuIo
OY4EFI+RWK6zTdllWgWpZne1d4cObHJtuY6KXT5jGV3pDRDeTM+1kYdycnmPVsbVE5xZZTQHx3Id
2Ctec56qdEBnfjZEflE+GPx0Ia9NYkVdlj1Br0HYSMJNS/TyhwE0EWL28gvrELxzBAvYSShEnUdH
DBT+soxAa0mTrKsLBJyZXJEk9d4f473FMBQoWxjOp8oHIcNbLEGUCx7dST9oHZaTaTGEUR6MgraH
fq7ue8YFNqHPABRK5U5TgtBUXIg+4csVmVm9CDx5/rKtnYREp/zdSv682qgFAMcVpx+/VAjcNx1+
ylsbJR4tP127qu/eN03a77Scr6MZon8PF2YS70QumGU8V0ZUosEf/f3d/Jz0Btrv5TwywxBdQ0Of
5FEast3epWpyw9/mI0wFOXg9fvxZDtHjRN43+qOEiaYJOBisoU0KnJNUsGPHow0aCurlx3SHnSI0
f3XacYV995OenEuVBIOqzB5242AzyQuVbHcygo4bFFyx6RmqmQ4EDQIsf0ql78C/y24BidfQDI1B
M7VslhU4cY35M4Wv+rMNtbJ3zk5gKjwE8vw3uyqU98joZ0GPqDfpMgIMu2r7gN50mDhKhnQclP+M
RtKxvDi5BtpyK1oUUdr3G43XppzOkzfJ3kcsDqkeusQMrsYYYTfLIRyYjkTLAxnSscpZuJnbEFXb
XfC9eP++eWE5JxAxQYLKgxIaBEu8G+mtd1Oid8+MTZ3S7If8cS83QLd/8LAnSRIxx06Ar6k4/x4T
utAcTdnufaTJXvMzcs0mJEVmb7tVMzgVTGfiHMNN67QmZixyTQUR1aSEUnKC6B/DK1klkI1IxU3D
/BJG1S7lVPe7xNiQyQTikSoV4Mhj70jjx8juQZnQtz/wj/xn2eL+cP4P89yTN9CQm98vx6mX5fnZ
9BvpK9agrhPqaWV5qgptjbjEecgHaQMUwmjNdvfSUhrmqw3vn8d2EI3BvUmyLS2VEySdv51WtwIn
73Pl/syb7j3uByd5FLt/bDbPCnuhDf1wgdLSF6fGpd0HLbab46pLYx9Hap2MdQAuuGpQ5IRYeof2
2/GzC96b7iQnUqVTI+Mjq3PgjhxbUeiCGN1NmX03HM5APt1FyJIbQbmg5rWhnDNGwztUM4ixgPVq
jl44kt7oZbifvjk79qyClxMlomx79A2igL4XLXu95RqTe+moK+cQYSeaOUDSEHELUdvIRd60Di4i
ii9p20urYZFgAHfVmRbWa+EnGnn1QnHN4m0rk2cuWWI9JmB4TDpI0rI5OdE9WNxfZE+v4FBUWlGd
FnN2c9MrRlLp/9qlDIlypfZtZpU+r2sqyT7e3ZZsn29W9TexxRardIIzbjPTK4jiImtG4dIyawNO
9u4HXHxzsLgMtiWI1eV61HzuIgGyYNzmXChzXmgS9sW4h3hXJ/S7TDCbnCVc2EfY7kyrSqFdnbwc
GUEvRoq/JJqYFgcyDxk2j7VHEE58NW6/BFfHsP0GVfHYKpfbpsxVz68jNA3KkT5cYgkdwX0GxvIa
7YmaM9SJhyKG4uP1t5U0nOGM51dO8zK31pO/S7oyLcHGWCqocq7QfQEzp2n4dalXAL5DrDWLFk3a
TX7uwrYO3gxb84Vi61qiCiEV7yUo3AFccvuVs857E0xBx3XQ4a1zjY4JTz4SxUP5UiIEjnoiI+cw
bqK17DDDFDiHysn+AZn2moKwWLcZaFkrq6L+vHgrl7pym5cSu4Xf47/BsMO97JJv8o9gkGXA+R7M
+Qov+X0CqaJKZ09zdAcZaG0wkBjOlh4IsFvGnb6o7Hek5bCq4HsnWUrn9jIpsW3a4r6eTsKSxGjc
rImiKrzbz7UmojvTRbnSFNDlU+1u/pJj/yd2Kk0+paAUiURlkYaXwg4Hkp+z5rNwf37SIWZ16JzJ
pQsNxaZFb6QC+mT6OaGPfMO2HyXWlr5DKj/DNW5+vh+mWXg271H+2YR4aNzSAb9qG6iSIZ18/Hhw
ADvu1qDZ3D4XzAULhQRAx2TxKPBu3m+LSw5ejF78ZyPclA6ytAG2Vu/K2SWCwDf8uUGGFTtT7C5w
54w97684WpFNehWr5dMh5WgzNE0WefccsrHz1dIgHD+98KAPQmhlt+KmJ457h8QFGgqJcHZp2OCq
zoekQ2w1l6UuhlIHI10vcb/dh/3BXTheCkvrrArNBg7VOBBzB7TpKxGzrYzlWwENNN3RB4FkijFF
BglzHTPFDZejUH87qOzdWYY3x9HYJSIVv0/ikSWKcJVh7KwR30Lpl96I2lCPAKZtYC8Cjz3kzwup
vUuIAGo/K1uj+x149BZVIb8rdyi4YjadyBsqTIrBkD2Z75bpeYvkWOou76YicjsrP6EVatvDlD2N
rJBqt2Y629jDTKcx0mDRJ0/KZKRt25DJ7pnLUxzXds/hABxtKHdSuRqlcuuZfNrbkg44OXmsEoJg
gtCUVx9jX40vu3VBtZkz4UvC8xhIAcO+Zz28PvJoJW8NUMeUvD2hZP0b1cu9VoDw+2+q544OsHtn
AxvWoxWcLzP9Kygd2QQ8zDBRUb1kYKT7B1i8ofFsPixrkuH/BRPXC+duJulHjz1g4tTh/wQayJu3
8shRrHmYI2xFEVoHtPmISCf6RQboqceC1VslxLx4+lfX1GTCaLaveK2nCmhyyW06wJq4LIJGPguE
k0vzha0zHdCFk+Y6izyoY1k7p/cOVp+a8YhO38w5v69ZE7VVk2PTP7qiQeHyWw6FPUlS23wEm11g
kK+iQWMzb/N+cXibvexmUCSr7yeG4q1b7hQub7YVx4YcEpSUZ/yGwxhXS1HDem++70EoWsppZ6iC
CTGsSo2rgYd0wXFrvBNpiR3FoTg7UeE6DBdvpYDCSSKCCyHr0VZ5k6Z0E1wGCWUgos+BZxP9f1G9
49PhUW8V9uqK8kJa/NHlzii4YV/hloBz7X+dodgWvn9UC6jlIewS2TTfqlUNzumyzzzwFsr0O0nV
2NLa5MNhElQvxSh/ps9P2hsYQnzSaPdwrtjDtPOCjwxeSYT1oeDKNtWN/a0+ooYJMizswvT0LtAJ
dPe1hd4LqeSSqDtHWLNa08dEaJxnDlHr7PASnpdauel9+ColrEpgYnECGX/ysqc44TV287bSBYlF
g24kaaAdUH/C/Kj6d7YPJhkDrnl8FxGXMugJEaVHjSIlhT2Mj3dNsu6w6K9a52y1EBGp0C6wJGBX
qmE54A1TQZn64QVeJNMrjsDnW/eJEjZqL9AmzOyaWOwCkdNUVUDhqMaLpb38XLGdEGKtRmPlyiG8
jOUae7g7ganZuDYInQbnc3qm3WcQgWVJBQDcnHI8At7us0WD8i2V+OlmhgmOYIaLeLy3xzhCKu+u
Ka3NpQ7eIDu4Hm+D+8QXkI8DtlGgtwN13fRVY5LRDUxB0Ftt3rWt5zvPP595pPWJ6bZ7hDmHA7k0
qYvKfePhGgD7DVKEU6pTJndt/zqLsuL56pNSXOjpIK/ZgJW5/fXIaj82FWH5fenrG6dxm5UCsmII
au1Bpqkq0EOfzDBbnPO7lKi9AhhIhKJfjSgXvVL8ut/BqxD2WgvfuNP3vXIGNzubyuOPrKThZB+b
73gISnWSkJN/ISgofYEOHGzrYn2mlFWVVkolS6TU32ZvAt8JSRWFQwqgmvEM130e7I4bEuVQ1Tv6
GboJP+fIWllEQOBo51DyXGkmVq4jiUlcArkG8aT5TVYtfYnv561uBlyBq8XnqRDJEM0kr0gl8315
Q06SQmV/jmcQad3ScTjlL3B+bGQUjq3EAfcRAgyL+OeXLg3DnNTRipBZ0lNpT15j0/PxIcpRPlju
iAAAsUNog0rdAIE3ywDrzO9O/836TdviAt7IL68IL4qkaIwract1coyHYb/6fFsObdPWo7UXO90k
jfbDpkDo86EJifQMYRZfN9Aj2NZZ9gNSpkmm9zs2H2pAEqNld9VqTZ4TOHFEO0Ax5oE4yH4CeChY
beevg0tbXZaLga5qqeLYiFdhEpnmzzPwwuTX5DalIMp/a2CghR3z++jCqL32wQjVBHfKyKmRnkvS
Y/0IGpw4fCIqnq7oLOru944F5+KydfeBFot9Y1XNo1JR+bmdKZwH9A0xtfER9hLZN1fGlWCVCggP
bSed/XuLBSZGosbHsoXJSxh2n5Ly9uMqnRCJ+aKSspgFDKgD+ZnH6iaGNeGf0Ll2RsLRm2UzAUDu
/cgTjF1VGhoTT8xkzI9s9+ONaWJ3SmYRKJY0UeMYhB7bQZNrRomOUwUqTqXbG5Ci04iydwEW/0ci
l+fuaysSZXHqSN5ruJGa3erGM7aWMV0X8TReOIP2m9TdjqFt2p7XLRZPmWUO78V+uP+lZ4srPA46
cqYH3lQmH32YE0Svl+qDTb39rFiU+HsUtqPVlMc+xevg3JdWdoxH7J4DlNtEDoJWyXR1lDJ3CPZX
4oWZ9l7+Z/dQllSVDmj8/vD/47JNls9R/4zx5VufT5/JDeSS4oIvOrRkXOwvcmhJDn/1VgdAjqkt
Lx40CWIGgT+2LtYwNeayOnnyZVcE1DzV+iZn9Ahsr3Lojh49AcpIEwBBTQlGXpEFwsNMxriPhI/W
hGlRkZ1XqjjUmVBLrnecEZ17SDg2aAJY3h/3DEj/w53xBg5sQcxneZH2iRJtEb83D2DjwpoyX9qf
f1tvHKw8vVue6WX76j2bhRBta++iDPDRp3VmglumXUChqvfwz8VRzpqp82Jz0jHNKn6Arc6FzdWX
IlrGu/vBI9LEAaE8SltZF80pFH6BqbAlF6ztb5Z7fJ36y9d78DvAcSGKff5kMU+FGiCoOVEPl/Rj
ZS3de8i3d4m1JUHO8nFhlpI/XKncUbBwAq2dHlOqurRvotn8QQpdUpzT9t1f8ATUO9f9sXG+TE8M
7YHKZJcOcMKaEgiSqwP84zNJZu1xdQM6SMuVChIAFJuiMb3WOqN4ejAobd/g8mPcysW5GL/qckiL
pZKD8qeWfH6SArkQvNXqD7r5OysDQgvExJTm15aW0IY+Hmu/yhcPofoApweZeh+0qXIXdu7+BISV
z7OWrvFPwkLE5YsNu656XIBSHLqXZhkHwcUGD71e9hYudfGU+O7EUtTiuNk4Y8N2lUV/cy1MRfkN
8cllR8FZ6y8yf5/3gowBRhGIda3HIXb5PjHLlx6m8gXr+M6+U5n7GcvCbCObJ8/YhuXcfMgMi0YK
27m5CXC3/RebTe/xCCX9U3Ef01YiGofxTPR4WrlX+8Zg3P//xgZ8XEUekMlxLUfzfD9naoMqMN75
jnSFktXQYcA4iQb9hYjvp6yONHVzt9ar3/ZeHabavjguLmSTo9Z/xr3TIWU513kKC4tj64TCih/5
qUOpGEqM1kMvxah4qORqga2eD6WB5r6FpPNlN05vwRsjuF0AOItyUQx05SEJ1eLbJPGYrEnIGDFF
GfVytLHIiEPdkV5igRbFjxOemAdFJjVMWidR8UbNNc74x9vvOvmNK72nxGEyPwTQcT5oWVCcHNi1
isTTVgAAugUBp4JuT3XblYD7PEcdrMsn2TWhjtjcMmViaY+6lfh13AEgoZoPbvJv6FWUlWaAT/B5
ItFt4MxiGF5oxu7H8mMUoftL7DTwmRNcRAGvCgR3+JwTZXFt/cVToRF7SsSvaAEimYqug68BZlDu
2vwTCipIofTE6xgHo0VKHnB66p1s8cSI2DL7fxcrvXSiAPjkCugIVbxy51vTmS6yqmA0wyv9T/cw
kFBIpQ4VVkFlo0pmhNw8PJYRPRCYNX1zItyoTDnG6IcHNmV5K8gPQlIW8emm/UEGXeYv9pGdVzh8
jh98XDZmspglXJdNvrZ7LlvF2HAeaWFD1yLS/I9Y7B7umTDhNwNXcenm3VWVxE53c1LnTghLjSz5
hNd70Y9rc7PlNPlgZ2xDBGG1d7yhnFyo5sGq4pau7OBomaGn/hUrPZ7DlauQJPnhmor7yjrfShrI
1sCq9mqaWPsdMxZbcFXX90y4WKqDoBoHtw6+FEgKECwupC30bdrRyDj6QLYwvu+oxdUSX8EgHwIq
/7A3cdaj0tCoYUx5ioiPS2Mw0cpuBtpcRc8EjQ0uPvPxP1eCKkCkQZS0XL3h0LH6aqAl1XYAgRtM
PMmq652nKi/GjAP/1VkuBhpavpFeDbIHLw2BxmaVWSl+Fu3vVcoRDej31AyujANs50BnfSJluhao
Z3orphCmFEaTGFOuCcfoCJmLPERWsfIPvZuCs0CERrxkWKlbtRfaZfr/YVTZA4boG4vTprCs4ghb
jNl1d7RFZ9wkAACemBPJyTJ0GVVO0yBhBHMGCCQ76aTLM4YmT5RnN56DUYdg7tWTSjbpOlNUn8gf
GWsvixBchwPKemF2vXAbnlubV1PfqHIYj4A1tEKItvgq/Ms9ooD8uz7Ne41ttIumxQVY0UylWjVW
B45EmSqz37Cx7QeVGWDELlIlDtQqwT/oUiP++HR40lfwAbKaDmrLSB1fMBkgciPdipYKq6F5Trpi
9mTAJYGZnaE0i0UTL28aSO5YlSH03GYYuWsph1EMnKO6fWTDxdJcArDkNqWlt/+Xxyq9HShzimL3
gMvuEovsm/izf0WTIJithSqCqBFEgo8bSsQgCjiztGWzKVwnkJkqadnFLFbqgY/qn4ALMvAu7Bdq
OhIWRV1EzzGgOZ8U4eY8K1AdaWkaR18L55yyb7xvDe1ZSNbw6Eq7jfBQ87pNzo/EQDO5da1AiUKD
RReT73k/B/InQNp3yu75IYW8zC5BMOI1zTHVAnXrGJx0TevFSNgocA+XlfDlOe5mPoGgBlmoBkvC
BCqcsQvU771fjsoKAveuQRJRReZbM+q2OaDT+ym+1MZVx0hk11hZIv5jhdd98JokfRx4ktDlhmi2
DIbYX95YkyHFX8Hoszzxm5n8wWWq+49d8STkRUf0E3mvgCl2cZK8aM1j24DUDw5oFzC/92P6l8tT
yc3E3hSn06e3b/QAAxI1nIryP1KTgbwJDgdKUiU7kPp1yz7AcvHG0ZZG27F8bPYF9LFD+xRXZi2P
y39QMR/4Br12wNQ4vKjGdTGcP4TSCDrzheA6PPLtdOJrMdLTnLqESBWyg/ZYXjVnK8OlnmAxB6VK
Iqp/NbSOtpYdFBEJBtkyBHLPHUEJ8bZcgFXL0h0LuS5pA0qf/Ku3RLHJx4/uSjS7S7qza/5VahCh
Rqer4c7rvhSv1zG9slXfpb3+FYXFJFDnnKPGm5oalVZehYjRVLp5oA228gwx4qzyt5Z6cty6E3fb
wSZHgCK7v/JG/9kD+Um54/bzKjSZEH2MhfyBsz9RbiFUGumbw0kYY/1h93GWmh/k9wuHghE6drJP
YDf8BqhnrBK7LRgIX8D9aXiYIV+Fn/Vt5fKSOGUEayfffejR+NBekFn2vKSoeiGFFYVYLaMU3tML
TmSoK2z6ggtFUR9l9/KcjvvJHrjm8MLaiGvpmnOKL17k2Da+DKwmQ7Y/VzsVGADG82le/n87NR9C
pfj5BXqKl9wVs2cS4Ch0NnTtKgv+GA1DyTbIkfI9wobxRgM+wbE43akTcEOgnYcS+17HyPs0NgDT
srLg4g6U8Rm+VaqzWVZxxvZFk8nqX5SlvIv/wqzgmRQakUdyZWAbwZFh7kqARquZ5Zd8vWF6lJEb
Td02RINvm3K8cI7P2yHVZGjg2afmkE/SoVbn5oiOj4ovEsHG5sMJdbFGKYBQQwAtGIFN2ieb7rG1
x6cPC/Iz1EtVFdIb/eRe30/3go+t4u/WqkJOBdsZi5fc58Zo8DHQfwgejuvzW2MmujQKo+qlxn7Y
jbSXwUCaDWcz7ciI/5B04OtVIHFAIOzHcA0Y/rpUiRctAzgs6xehknP/s8myr2C/Y1LbmAh8dycZ
2sVo2rhm1WH/xGkviCX92dS+1XB1CezUHj6a+0BkjL9KjYT/QvNZ+3eyEUNE6XN8+HDTuLtyc1nX
SD8v7uEdD02CFHeM9xhA1+UXR2Vv94MHrfeCOlHFX/1f83rtbcRst4O4lomii6i1+ASzyKTWMR84
8rwUhGeKg6OsnQipBoYIZvJjqISpkigNOXug0q/QuGbYB5WKcXPx5S6a92QHmJNOTJuQ/UJSJO7B
jl9/PUXpXUMcpX+Ae1uYL2CrGmXge0LxmV5fcsnA5z85K/Jx0+s518Pws0APcOXaO1dADHM16kOI
5uPh9HmfSzPIcDHxvh/66QsNpu+V1en/rfQUlzPPuuq00XnFnn3q13H5R88zvUXBWM5kuO39ew+z
dhzba8BsT0ikAyA+zsoDoarNbDvs3f/FrkTXJS03ZKN9hnsAeOdP//cP/k8nPEZ5rcJVb31HR5c1
mutAAZ6rbQ9XClBQDohkGNpSxA56//RwVWTegefW9OJ75iYjUeKKXlEQqGkw3deP6fgJPOzo01OX
1yFO9i3AP43TcJqmMHvgJyPGFlSm9iDlZhOVdNZ36naj6jNeJgLCWacL0awxoGsyINOv/uAWKf5n
HAYzU2XkoMsRdbHuIkM4P3Zf3ccDpY9HDrSXUk2WQJaZ/a/OYGjFhScS8DWGPbSne0M3yN5g6o9i
3LnIjwbgjpikayE23fxF+V7i33jfk2IhIshymI9Wm2AiboaXMoIRJESVbKizWMvMRtLijWarcsbM
IfdBFK4W8TAgwcdAsQ47oG1qREinoJJcVQr+iTSg9sDhfvy+BktpVZslIJiC8OIT3+K99TR9Mz8U
bpy4Dfqiqt0z4hrI3PbudS4jeJMXl7P+lfdaIq4XCfVzFkPhguUu6bJnM4tV6w7N1goclVdooh6F
eV2hgy9pVgYi/hidq0QfQL0SXYkWJ+dSzgLYh49U+Anq2H0f7ah+S8jwdMGp4hieGL/XYsbLDYi4
msYHJFWpgCx7eXzmnrv3xLL4s9bBIwbfHZYWbTNknev9P758cNYUC7UPfJSHbxYtgCxWlfxVD7Wd
4mVdLKsM5mWdtr6gcKdzbX+DqoUCxPAEw5D84kMUVCvATD8fTsVM+C+C5OWtbcHyV3Aq4Y88UFMK
NWB401ifq5YGU/f52uYHHjkrnd+6e7J9Pc/kWaXRVjjoUmac1O4//LTl441ZDJ0dFftbQT1Ch0zv
XXIWMs6Qj2PCmiEvPc2HwN8XmKftNjZMfy2AEg8GvSYqK/pAM3pXlALERUiylorinq8gtbq2jgN/
TWQSZ+FqTRrFm/WwXqBSnxQQLNcJj0W9thoRUlRww4YX1zgOpF5mHUSYD7RzZq/4MvIIO3r5omqf
z3Y7YEChR8E5FrHVHiESolJjFhWtgAqdymoUdyp1qGx4E1qal603xcS5m/Ueyuf0pMMAS/frN0if
u+IXpXlKIPVL9LNPunszVNmY6c2a5CUQtwPhoZPHyhqyHDC1P85gU0dDdXwoSyovCTeQ/OrhpAH4
QroLMppdV4eqnsfQivlqRD14UFxrt2GXZ8jD82lRIn8yDwoseXkOCRWJy9G04hVpR5FKc/J4vANA
zv4N/CZQqp/9yYikpISZnT2gdTFQw9rTBo3wwVGEV98TMipTUrvwoma7Uh0drC0+Z7V9mrxDBUdK
I6AIdn2whSMisyat+J5esxWOpHnBN+Y7MU5R/IDA0HeU+uvI6RRSOhggwiioUeICc1NERaxYzGqY
UR9jUecdVHhF0Rmkke5iI2OXpo21/buHbNNO44On1fH90g8x12Wz7bdztcjJ4FSePm4yW23XxZKJ
HzgIX+CjdAOwBwlwZaklkShd42jv3DWt0z+PY8PPOzCRgsKm9vJwrYr+11o1lHM3koR8S12yGaUC
4UHQAV68vh4xzoxZcLQhmqHCSi042iYbphg8RCK4Q5I5GGzSKm1wIaYdHOYiaHUIjAmAEZA90Hhe
8X0Kv+61y4uTkndsyMm3mTmSgFZRFKHwGNpj9YlzcytR67P7XUNjF289KPy7f2TlMMeN9sC9adBw
R9UfvavorRmNvK7ylT0PSgbMKLqMCYiNoksnPPNV4AV9R2xBN93NORihNz33V6XAa2KBGMCdnbru
PPuevLxTh/uqUsT8bgqXzfouyTzkTI71TnuaQbIHdkepuLwV/5dh8oXiEZHN9pvCtVLuqGHqSTxC
QQmvhG/gE5nR6OG5pkq1ELCZaHOYz/KC3vH6sHc9f0PsbSvNTfCihElo0ikCZEDHwHG3DRyCAlAN
y9jMlP9joBqAQBLVMIRdxIdLS5miMFVHnHT5q4yhD7i2c06e1TbANFoKctOc9tD/qWAg4qobCAoJ
zZM0l9ipgiDFRrTI6ULfVoebMhDucbSsoM+b8uQjVYIYG27ovxvbEZvIm6H9pbp3HuJsczPSE7fE
gCx0xUemmw5MTPsRjKf6NXVOVvt7jCjwmueTLQEnkstRCYJK75DWlubBzaDIJvjvRMGznuev1Tvq
4yWcJLftynR27J2bZFwKEpM3KDdyBegc/Elkb7IEkOQkojwGuqd9uwpJ5Ipgv+my4qdBN/nz+D6S
UOqd4PBDJ2TEn5v1bY8PH3/iKj6jYS0DB3lAOGD/i0QPv2ZGUNPvhQg2ygCwpXK9EwsVJDWWFU3n
TEkRWQjrOcUgGEXO8D6ANWGZ7gLmZ3ECjSzVvOtUUlQT1sSd+8Srl/nipHNRp4qPprMeHxk1KaMa
u/qiahEzsDIWA5m8GqC+XBv2m4cBjnHgl6JUU/oWpGOecySOg4WRzF51U6E+T3j+iusCP2OLyq9I
IUffexMOeqRhag2ngmQsX6ODliOwgMb76pQJT7EZLbkr2sTntONiJ56f7wOM2/xHvWW8DF6C6HW2
N6s/nEnICUHL3m/C7YDnPD/PlAA7ihvAmSjT7lifymm9dHJhC6/t0wQ7hREy3DLRgEhPMafhtoWV
v5DV2hiHTeCNLsxgzdc5p6S2+L6PwgWlbKq5DI7SRZ0o3GeXNAqODzwD/iLjAikyVuHBOxVPFJNL
oexsSHjueKy8T6lopsduH4SJSgkAX9juUx00Aakt5+qQ5J/LvDhnUQXYsWdFHhtDHMjdHRYoXIX9
Tl9N0+rCZLybhncNhzRratwAiqs9PRIM7GOAbAb3qtDHqhL3TQkrR9Z9wQWaF21GbhdVQzK5PSyE
YgPuzc6fNDn5291lxalhyZxP9b4U6LGEOtsn3KIVWj+e4zcHzHN7HqsQ1cwYjc/tnkC+JACWExhJ
eRafIJzj0gj+tmQ4QrYqB5O3+pNKo0WYtlw60kpUp2QYH0MuCFev+MPTvlZ51y4cEpJd+TJh9FKF
lREtkmCS3UaA7KonOvpWu9V9Ur/FgHKpUpcZUG6Zzq6p501RGP4A+MzUQPZIFIT3VcV99yVH2tk/
Ky81wWKsbKXmISBVH0sdqrc3LgEcvOql3STJQ/7UW4KVJDSxGGrTTQO8Pxf8KtpCLgcS42K2HYR6
AmN1abhSFtHyWSqOH7n7IlyqO1Tl2IN5hmJsPRMzoACyH3FaGBLEZh42eQScm9n/h7jO0O4QaKck
JDWUqtWju+MjRW9x3ipdWGmZigPTF3QRDzIvkfgmmRUUSOwQszFhvQSINnHDmsUV5zkyMBQul+cS
uHVQUQcDNKtgmM+hKOAbDCUezJwBzfz374AYg/MB5TXMIXTfoJUYEBzu718JRxdFPnD/izqpDtwC
ymgU1b32zR2esQaGmOSogJe8kMQgL1CvjYJK76ju+9GTMicHyPKzc70IGnYjrI37xwBgpcmjbc3n
PLYbv8sEe16y8MbTXZTikJV6JK4mbuiMsHwouk7082S0q1l3owWGneO5tBqgwSKmZgSOv2L+kVnE
QRlSgbymoiHGxU0M5Wrc2dP/t4Vxu24XoLZmdwlnJyRGn5fSvpAe7MMN98qYIpL7eDe9Ipf+XO50
WS8vTnMNEhqGMCxEAjuCcpbcqKdHWgSrNVrPHcc8xC6v6YGE6bh2Ox5699br1Uf3BKhTru1wJNi/
jen5eRJ2uY8xbsiCgzJMrgBKLn84CGXyXLOeGLPqYooaH7aElvCOdQeZrwA1HzBeWJ8uVa0F5ImG
APzkXm4KTmTy8hoPf3wD+lyKKmc/3Wog4G/Dlt0Na0atsQbuHFGglISElvp9KgQTGg0ey3D5dFl8
BuBG5JOA2L/glKIhu8dlsqAePQp6yzCaGjJg7FQgbX0OiP5akO8nuAMIH9gBo1whbgIuesSXkmPR
1GUrn8XrVZbLgOpztwv9jhXFPvyGbZNRKwpbckj+o576/sD3fL90SL7GoCk+qO0OaDaXXQtF26xb
/N9m8MrRHdqlvDJXZPHPT7shstcA28JGFjWI3uKsD8SI6DGXgxUzZfpK3/syGHDcw7YdN3Zw384g
WeO9mUZso33TzGUexbxib7XksNcx9PtnWfyJVkYUQFFj9nUFskEphMi/JTdHoOGwoJVftpajhads
7EQYS56Qojl5CXQPY8FwuG/42E/hr8Hf8D3nfkaDn7lTfNIN3XgGtm3YHBvWaG6z4HLJOLpDQKiY
y2YNaAl/Yoc2Gc7z6/XO6e2X+WtJlqqDYofmsc72ie93VgklLjZJexTvxV2gGfyQZ2adpgBEjpga
w5D+ZjDoWhJR1p5iIPZwdb8Tf0cHNiNf2VTUbyQHxX1DSROB5eVnYYb9F601uraRWSyPPztA5r94
g4fnFR9PEjJlHNCi+xJwOfxFRTDUBr0SEhVyD5T2H7ugSRGVFmgrDMaHF9p+oHim2qDLNGxX7u2x
vHIh5Ig9aDMthvffuN2YbBWJf2HoPQUpuGWCCeg6wOwmJtMMHq5OkC5rxOMHCsM0OD7tc311eVS1
1bvHOU25ez7MQk5OVUVcOl4tYyeSDKOI8BwU4Qp6BeVz6f3mX3yYVft9d3LxY6wqd55sX13qB2q+
tqbNjdU98ivyJzkbpLM9gbQI1kgKqpKZixadrWoGifyvM8UvjmwnFk3aNLEaWTNOZ0kimeCJ6MXU
nHs83Rp8ANDaUCDfOv2IBpdbBSDz9r+pld9bdbMi4NOY60YdT/mq8jr/s8bpL+q17ahnlktkLF8Q
ZuLj4NeA7+OqvuF3/AXE94iMriyV8OVmF1DG/HPTsIEsZLHTYIfdu+QnQJwSOjeJ1C0CShgwjyvG
C7q3pA6K74Vnx+DvUdlsoPP0ymD7M2wJuogPfV8sl7Y9WPS95W9xspzbpUU2HfBIfnr34aDmdTHn
vG6YPsR1661puCJXQ0AoeoXcKuVFvXKDdUKSbwalGkrSqbF5VEkzytQsOCGgE/AIlkevoJfkcnrm
3vEzxUoc8+CivIZc/fB9nHHMqyGRH4/xDsbsSes6L5jxLYWkA0Ygx9DucJjggFpmOa35bU7RhYDE
vgQvFjYDKm8VVZkSB3M55FAqMEeV05laHV6126o7zG2bUy6LDZoOJkVmh0jar117RCqh4+uGX/zX
9e3tH2ZgdaXiRQqCepB87MVBc8Lp2TWYo2F7L4znUkCREVWcq27jlPx6lGwpGKiqV0Fkqdvvy/8w
wFx3QeD5snMram+2o5Ta8P1+INcPrEWZAzI4fpKCYjx2UuQR5bmu5loWMNfMt2DZl1BtbxOA938P
a//CrZZMEjRA3iriquhs9epA/YK9LeRZnY5Wh+KtxbMsnCm74FrS8KeRwvlKvROiZLlFa1oYw/L2
uZP9U8DTQ7VxtLdM7uGRdsQStTw4hRYb3JC7L0zFdtPtIPmQ1LB5uLc5RfDB74Sf6JHXfdIrVnro
EFTnLiiiza+dgCmVyWe85Ce/lugK2AngYJSS/q3HkvPNvl6gZyLOx9btocxdJ+Xbw5hqdVWOq4FZ
HnXfbs2fG6wk/4d+nJrYOTjupSTohuOPr6qiBgb+x0OKbAKyHpCA1IBFUBGbwm2EpEdS6+A6aEzb
NhS/zFNZb/nRRKrcbSUMLA6qbliTQeNuh1rWeVxUeWXoPp+J+U2VmhnrMHAauTy7wba0DFIejDAz
NSNxkJ8qOBP1ekh+uBVdc6yaZGxoJFj0nGslurCDfYJ6K/bq4N1tixsjrfav1XqEgNXfi1OhcT/a
SBHW4HgGKixPw/607B+IBtdG77QB6luetaw1L71I6myNTt0b5D4Grv0tFHTWPU0/Cziqpmye3cbi
lzVh8LK54+3PX9IFe/7ytjHSMbTTn18FK6Jd2up0WfoVATb3xpA0VLimhMwMDIssVYOPJb5P7aCj
iTxFiPcGM8YP4bcSCWiwDfBk8R62m/pUBaaTrxoDTI14Ryk/o4e+Hu+QvAtLbwAPQ2u+6hlylrUV
kPFCubQsBZqzGbX0v+ZpzZy6BnT+DK4ITza3pm4SNyxcSEsGksdasFrZIwxvYvzRMZCcSxOkmMpA
HYEDOD9GK4C6EHA8BXDdOwxg9Qvb+jlmT57o6EgbqZ4G0acCDLaK/dnaLSoC5sWX3jNTIMux4fNU
YLDer/s/HaipHo5/ik1bYrrU1ifw0b3Id8LmKpTnYC+/AYur4EE8JJUy32VCW4rfBi6Ibt5IuSxG
r4hwB2NGkeJcGedUC4Nby8veUg6dtRgM1gh4KVuLhhNFfDjZseTuVNX0RICGOIcqqy8Kit9w7M34
9MctL04FwwietEp4ihrgF4CrUFoMerHi3mBdEUyWn3gshK/5/4fjMNtTosNmFvF2MMSwzpUTyvW0
p/ZFIgRQzLb/CzP7atDn+ZNzy91eqfxVcAC55kC6jqwsqyue2bXPjUdLJTd4IkPku0ytqAJCqXPR
otflYatcFIhEAQU0jo+0OHvceWNNWkkZhGyeUj8Zgc3D9qiJB/im+tTFczZQmQy83gjiusmhJu/L
t6xJadDJ+78DhY0Vmb+spCAOCDPHrzw5Y9A4bFMrXMXJY+3Q4IUX3cW1jPNHQoQa5VyueQmCdLcj
eUG/8qWlqnVV0t8oPUN9NKl6d4CCXfDaltRHwz3dEOB35XZJ5rxvUybczX/ocLzrAt8THw5JG1r/
+tkg1GfLNPxAkBmZDRzm3kCV7RC7QxLHZBjd5EMEKPzHHfF+pSp5mvYyq5R0msPC5EV6A/9PJ8MX
qsm6gUOx5qm9hUIE2Ymt1hi6au/mK3lStLEwm8Xc39enufSBMb8ZnnRPxiwv5Fq3Dx71XkbHSaKO
FOxt4x6TOn0ttWz4IiZPTux26SKdD+TCDkyTNA2C8mzxZwYcGtEN8ieD0JU4qjtrh0hp9fi9wiN6
MnycLgq1b+vwQDaysn1K+tJBs8c+BBxQn+Nys/6IpWLYy05G5Ol3HYvUTQBd4Tgg3Mxe4e/FhP/M
rZKv4hZzlcgRsZWTbxxe17M5WYXiKBhUdYCvb2qVMR0Cr5LKLiROAqCCHvW4CrUoBF/TRXUL4MXb
sEp/HusIMxX3dgpjHRdxeCEyUolWozIyaKXLmW/4M57EMjtMeZ9O2o4vqF/Eri6Lr6AwKUW14b1N
VVb8Qnf0xdZS/XubtZ3ZW/D9Z1CQwFhabVuSId7k5bFY0jtV9QEy/crl8k3ncZSbnF6do+IQTK/w
TTsicRS4N0yzXrAtIkyHmHK3lstfrY/idUJ8h9RclGVh0MhNwMYaI3nLpGM9tWAhyT67eCor/ezQ
Y99jU9k5JfmJGBQcDC4KYmEdgmsZMFYQFhIBntUodsWJ0er69ttq7QtHOtCTbyaaCYLBIKfdCySt
y0Qh7bqDTRLgGhCGReK9728WffWI+kCChuoQUQ19TE0gUrr9fAhG1Ni34o5a7jh3CKFDmV9iLhxc
3GGmYmQGCp31+oKegBozU6HTHgG05E7azUn5yWOVP9JnKeGVXV3cdmip/UFtZqU+/QScwcpYmcPg
X2ZleXNj5dySyNF4RaVeaMj8ggbGMolFVRV9d/ix8JyiV2Ei0H/7moNUoFZS8/lIa3H1VR3PI0A+
9CSAzTR8WLd4QVx4wPI7UdakLZcrWX2VGuWIFIW3BtqtJuhEmODINE6E5BqsuEjq/56zBdrG0xY0
7glXwB32wkXiPZqkBePCgJOQxPj03y22q0V55p44k54BaLcqfsaPe0G0UNEERWpLECT+tGqWW+5M
GWu5oaw8Iqw1cI43wpI+l5L94QiifWLfTrdnOl/caI9r6dlFOP5I0Gzmkh3s1+vVFPeA1lU3Mzu3
eBnW6ZjDHrkux+Wao9BsF01mDGUHdHbaRILx8T3A1/4jH7Kjato7m0O7gKhDnZsqgzGXrYmpw3WK
UbzHXhG38KHfMU0g3zGk4cjpoP9ea9Mp9q3ZTy9BhVzg+CcUVD7cgAa7tLH6xEK59stDSTnvuoMt
GRD5r+vppsw7U4nlTEFfdcffsPEGb7zia0CLFL4JuetbsqkKyrTXpnPkRF7WVqPAlFXdaGYB6mYm
yL02Hb8jeL5Ye9LjxE3SQzGcBlufG63zU+dJY/EjRWdb6gFdWepZeJfJCAgd0CgGaq2o7ahG1iLR
YT3rNXJ7wjsZF0ACRtisIRczotks3DH1ziwY8zvay9SeUZOo24vaHXSwx8//okxMLNre/cwAwSNF
5Rfq8UtQft4HiFyNnqYOua3q7u/psR08/zoKr4zyzyK43bJ51ZBfIolDlFzI+P3l3C40rt6FyfdN
vnr4apS/wXGusLhGEK+GpvM0tETnucne0x+8zqnX2Km1OOc4vD1487VmQ+D8HZoVA9Z47Hk/QpoG
vj9+cVy/ZSvRnYEN4+/YgdikSvrlE71RQC7ARQfksSubw7p9IcTjIgpc16QLAsL8h4YDlxDweR5h
9C0sthoP6yybnS/RwaXo2IcZnD0iDSFcYSmSeJpn5QSCIOr5SwwMdcLXTG5ZVWNkv30RbPsmWaO4
o/kvW8ecsOw3LDQFUwHkRZoBrauEm5k2B7cnC9kDu0Y8O9r3yMGycX3Nh//s5L/bZnwiGSa6iaX7
c4eErr4aU1SiufmCpyB5smZ5W6QZhVtJV4yaZ1iR5iafiMKvIQM6Q0LaLHOEqVMClN63es4wgyIU
rw78/Q6ycIxIYcSkmMu0a4GE5sGk1umu8nOPPtZPKAsQqDJK6zRvFJYX2y8L3fzhkrWIdwiYDSGw
OlAJS+N7/IRWvht/AMlYJ3LTH7ntTkysdcJLgNIeekTPfH8agmhh3uJavfAuzetseGn5hq6Ywk4m
56jog4O6uI9zdT7HFg8C3QFZG7AVReZjlOMnlG70qAdfeBH74ibZJx0VFiO/JQ77ACZSOfCV3FMJ
JG8MwEQE4bp6y2Eaw1e69GW9QEFNYS9X3ld+9c4h37+RmnnxfOiF4ok/ab5Fjf2pA0LZBhekcOnM
88F+Kjg2fqb3q5Vz4HZ03M2QvtVt+udc4zg/Kzv4+rpQY5ObYO412OCL25TtoJXgSo/kZ4n6qNUU
suz13B+/uEXOGjVL5QQZh7YC1e0XyDeaC9BkigdG8qdlJxgcTo3Lz/iicjk51ekvTOaauEeDIba1
BJe0ccZ8Rz8mb6lOOlZ1P5fYUFN+a+XgMuffTzSUsPk+hf7ZHTBZOyUNAIY3s/b2RXt6/BDzlioU
7m7zKa4N2kO4Ld9fSZuabakr+FzLqSHM7TD7CJfGlv/Qt42Fey1HtiEkbPihfhcvuVh7wqvZD9cS
qQyPzdwzO7Mkc4MQu1vXkViaXF9mojW/dt+xPZUaNt5xUbVoupKOnbbDp5KRtKYemW2rH6fczt48
PdIYYIQtjuzdGua4qxnbDq3kbuECyAI5QQ+z02R7cFk/bce3OyLvLsy9vDUW5fJ2OlYa0SxJF8xL
l6WwHH88Qc1eX9CiUCIa0g9G+eXZP1i1t8MZADSluvWI1I6WDzIF6TM98Rm2OLJ5Cvbt6VWhtFEr
YQi6QUZNPQUR/Sxahumqgc1aWTikuI+X8haJZN1brLNBXyhcATgKAfQxA/JdiRRv1PmnRMpt34Vb
u77nKbfnksr0jBwJiKlUupaNIHzlzYMaJoClx3o6TOWjtdnFXdrezJSUEhHC6nRyV1YLitgo9ozG
7XQ06GVUn5YvYRSx3f0PyfN+J71YARDwMYrcEAOFjf8owHcOkVK2AlzMU66dGEJ2P2jAaTVVKabh
Tnobc1B29HYjgrx0P9rgUvISjGqRwXKB8R2C/OeV12LVzmCBZcOv7GN5e8RpPHm4aiy067KY5UtE
ggbnDjZ0fWHgRswzx3Fd3VyKxFsppjCaJCs/QjzJ5QdR/5Nq/Lz9q1Bg2haGawvyU+Isd9giEcx5
fHULh10AtKe28FiiHMmAcSPmmIYmY2BE9L5h5Ll5dHXyV394wE2IrZAavL4KCQXuUhNdce5BkxEa
PSYUEN3Je5XMs2h5bOjZgfHSq5stxlU+Wuqe0cZRvwpgbmWJHc9MiODdU2w/NhQTiJT+RLuIiVfI
4ea+m+LWv+4AkT8lu1pnHwQTVS5OMgpWWRm7AZbjAEVxuo28GnoQA7muCK1A2N1HwbRKR86qN5fO
T/+MkTnee5K7p+DYKmULz6yPY8uGSaJB3dRWOsQjBxrJ23D46faw9pejrjFtFJKkKgCNbwY5WNpG
yFa2gK+NxWxdtX+iAcViNvUVQucQn+qG4DtDRitomUXbhzTQBubK2XaPHl9AA/EqJmZdzvSLX9We
3tOgbqV58K4mfx+WIuHG/MdV0yb9qbiasHxuVm5K1+zeqDpF9yqtIixMcZQe/cC7fmcVy69/+KDC
3UQN5X8ibRhwugu0z+cDsac5Ns8RKb6N5KnQc9F7WoTkmOM+EZYteCFzw7zN2/RYmWr0fsOTWfcd
Oa6bHULPOrqZgUpJ/eI8YxFA7YGR4ynUU+4zgb8RLIGXX9ked0iIxiEP8FyXGhoWD2PotBeqqeKk
oBXMpQefwjq9vG7QXbIlDIoWsUY7SrVHJnfWNlC9qmQtXF/v6DMvgr6Q2hO8WvE8cJCPj1/28+qk
sthDFr0VL1yWXhQf/orvm6/d/xbfRrvnpdzGGF7E2rDikCyUwnLeGfrDjPvL7E6Iv2MHV35oTNuv
THamKyIKMBRkagtJ2x/Ao+p1pGHR+OwgS0BaYIs5eSWkE62iv6Q3jrOOAD94YT8I7mUYpzonyHfS
fWKSk/2IbTZIkuVo1rPt08cR247kcz4fyIcml8YMQKJqrRpHb96HFSF/fZoPpAXMB8wbgVVz4bX2
dKObSdwN6PR/4QZ20RSmEV/lvPJyKLwXlpkuXSevhwbtLLTrnZCQ+7TUSW7SvqLr6beBz1scio9w
1rdotf/QvfmGzdSwj3gINILLMZZrV8x51XJN36RQ/4OZ5DRolOUV5cN2l/w4B2vJclUSNuQRbjOA
bqA9+nB6A13471t8+IxpYVUCV3YsZ/FRau2QiFwReuukTGgRS3uhUcR0zENwySGxMejQTlnyAqGQ
Ik7TdU4pzQ2c6Qc+9CT8ZgHEmvBAE2+RjzzI+w62M1QPtYpnshaHFCxCSk7zusBivyWj4weZKiMH
a0bvPALl7KL33KfeJwMmfM1sUiC1GuXOkVimFGnkbedtr2UctMc+vTGI6m9LqbM7fX8Swt2VX4dm
mnBZ97TFuyH4Pda+JrA0I+G2MUmWTc1BjiV+YWg//uNAALJIHi5b+OegideLiNXl9irgtL0IvbZK
a4cj7vXJ/aKoQfF5fqWC6Z9tV66raKszxQk+Y1vQ0dgYrHExu+/6ft071jMOAJSfx4NUalE3fD/Z
4pRM8+g4o5agWQ8+ZXQQZ2Y9gUPR+PeaU3rZeTw/AfuvWDD0osM94+Gc6BAwLBqt1ZfAGnKrE+Xp
LWZC6yZvEYCIMmUKwxcJfcWwKpVTCiv0DjgTRsEzYVysbKAmfmcb19UzDZtVuFIWF/UGNUJPRwsU
0/jhV6rB90P5AQwOIr1UXShmuV4JSJ1LUZxL6vmpI+YTnkpqT5MW8H3UD8JTnNGjj7OM6qbx7Q6L
DCGg5rgVW+DAEEUV197HCB2Fk3sjgavIqGYOD5/nveAj0WOMQhuKwfsjArHTfSULKTJDNdSG6GTY
xgntXMv5z+ntyI7EYEFnEltaf+OByGSZxyPHlfpA5iZMFl7474WPAyHQimScGMUI9ZFTBqsNm+4n
IeKmotqaQxg37bV7g5s0g3rWFzSrKD6WMnhXYyppyG9dhiUznfAXU09O9dnbNDz+txfXQHJR+yW3
kllVG0tkKwlYKhL9IYf8Bn4vEXayqdp1am78/yNDbRG5O6mOVUuCCTHgD1ZvzeZkUtmdzQiqQLy+
X+zWGa9GQ5TNTg/qjxNZI5+JVZpElKTPlxF1QdlhCodOSpqCZkR8ksrJUS4EUOK2pFbz+3S2u6Dv
8PkBIhWvX6ujUg+qhWVFO8GKAWbDoATmtDSyLfsfF5Yyh95hecvcWS23nK8NJO4Ot2Lt/tIkQzI0
7uMGhxj3QLouVvay119yyp7YTrZ2qfxID+0qclbzqYxXg6ggY9OAGd3YDSZW8e5TUx1n0Qy8Tw3J
yCbt+E8h5GxB6cAvRjXaJ6yW9yexq5LA2s4SHVu/j3sy+1/r6KennjcszWMgJ9xsCz2kEgHXTuur
OhlS6zrEXtwDdAgUeTfrzx3XdgM+CoaKHKPypLLI6/MsbIP85RXYr3oIjXl9px2STeHFEjgewCyE
T/jeQLR9r5WrKUqvjCuLAIb2dtcnjc/sf1Qjce2SQsIFQhBU3qdL3rsTxcDylifdzMMcX417rJ6x
+2anF9eTj5ik/pVdlWnfZiErVKep0ZZsyPXPw9cR5XL+XzYXPG142nGrEbF35Eqhx6rEhDswXuFG
OC5GPV8x6vHSa3sDpuereb2cEYNYFo/ccDwHACVIP5Krpg/OWzwGfIu6ZrqMbWYd51MxsBRcUGfz
B/IjWJRh66fTwGmxkWmJdVCOlmEcYPIzS5Qq5k0LUYa4qHdJp+KcEVYE43tjyxcKWUE1uUqsHN1C
yty30QahkYEhIA+sbiIAUzPjt2eBESTLdgHMaZH8Nki5s9HyHR3TkLnL6GbAjjTEWxLizxP7WIkc
t3jkRsEcSIYycHNYl9mk0l2qheLuL32jXh5Sia1/BDiCs6nXv2x9DynI632/NEehDw5JqLFmUlZY
bIeR3I+Wpx+1FkLu2AwUtiTVHYl5ZM4EmYf70Vqpy/z1ZNus2gMvdxmuTlqDHXJcwVVbi7G9Txga
gAzi/Br93n+x1BWZFW5bnPaeUrOKcumERpDRn3leYp1qEl+7KKsNR3c19ir82AEro3xmNcbwOqDh
LAGmpfMTxxWpsrhsuulutOQS+CjXuDJ2WOnnaHO09XS3Ypunq9J+lokpQ+h0N5yBv0AdrlI1VXEC
Vv6Bz92pdqtfMpvHOpxNsOXgHoDNxae5C6AGYCjIHsX/OzpNfWS1vbdgWgisM8KFDe5JZD7QhzKq
FOgLbkUsgKCs7w1E/zn8H1f8eKyEQe3WzylW5Q4twHaH9hhDUuw+zDSPCyTUGommh1MApFE8l10j
KiADLv8lxJptg0QiXhM0sprn1h0kVnkJcndwc3q2tWO52nbVBiYT3HlsRli1czt1WwHpuNTvkkNe
Q3koKTusqO7yTLve/fdy5lwy4XZ++kMcJK2LoMTp8U2GF0PYML4gVfuk7z9ZFTyexpffu6qcF5gh
dt+f6irwcZ0/4sJmeOZiETaIbdrLhfQoPgOvNlt86vj2Pk5kgqVF3QGaVcz5fbasXxFPO5Z/okw1
iC3BoVNEyWNYiAmasnH0AcaEU7MlNiwn0Tg3Xsx8mkfuEzApxFyxtxDnDyZ0kRWnhouyyjKOchCN
4VKH/sUkdipgdfqZzOVRJyRQmUNFuKjbvEmWlix/Gt79E2i2OUTJBfvxrXt9k+mnwLBizX6v6DcX
n2IVlk5lxLLiJxCTaPxXv31WGsOCg8qp+dtDp/KmwCo0ZmEBisZNPs2AtEVo23rgw5G1OaCb5W++
hgSZCfgltCVywSP4PHYwQxwDISackRTMX4W+t1IxWLYtvInZaRA/SKN2SO3ojkb/FalkJ6qQ/udN
gyd3uJIizBioeEAfB7U59MA1WsiFhN5LaxDQ6KFSwPV2ASk1Vb/cZx+J/sMxNkE7I/a/o1ViTOOn
MVts6lpSs+iKEY2YEJS3DsIQFwlqNGRrKzDgnDFatml/n86qhVUmziLPGgsK+islwdXry6JsuUei
NcOo1jQ7Qke/i17YncjcXe66fzTDv1Wlo0A8v63yHzxDbyobjqVrFLPLnKBVhg6jtymGM3YdUJZj
ukV5gR6RTworPgF8DMQCnJBJC0Hx7a0nivXt7j2FuFhh1j1gzOAmdABJe/O1THAcknZ4XUzN27XG
cFA2ZcZNkjqIRetoQmPzfx4V3C2GvRwwMeiuL56cRqI6ptepeRVjruUQ/uQyUEHGMyB4gfHIh3Du
jyudR5G2RjthNIV6+/RTjphMjX0ZB9YDj1V7Oesv2A0omWuOllnfVJegQ798c9b107r4zlZg4lb8
uyBo7OudMvbrCwzhAdhaLZjLo7EB5hLhvayoZZdvsZTE+cnKmCR07lfoiajO5nk5ZjE5OygZHQHO
CWvXUkPeKy38UG9QbcQptKiSI+M0yHQpfOX9mN+HvhweTr8XrTo227BqcZoN6rYEmRsBpbGgX3th
8je9IErnXw7txxoilMNvOhknliI0NqBHhPHTGlEVaXt/N1mXbJE1Bz9dz98kRFIabd8D0DiGYBvl
wvy6hR1O+unsw09pubUeD3lZqPSDWCLOQ2KINWR+RFvwYCyJUqRasrzq01/F0+QH0Lk8om/IDJnX
3q+9zFZO48FrGxAYYD9iJ0fx+2JOT/85pur5qLmUOvZbh3fdIw2Fcgl+2E2cDa2qIRmF5fTGKqnX
bxOcr5YzTcn+UtGYA/+xcUkFgWguEWWQLHtKUs/rR5R/myG+CnfTliGA5z+Z1VsiFwjofKIVNiA6
Gnn6/sWcq/XkIy/npdhlUtgFQzX2KcG4WRY4T/jFkG4vGZMIh1x2MNONK6Y/GMOIebeKaQDLXanE
1W9dWgwYUWYsF1T1XHpflHb8DAxx1dF1ERW2Dc6GC+8zE4TXcF4FEnp+SH9TmY8/pgfNSs/fE2EO
Gqtj/WeWiCMVJ9YSgy+sMGv1k+LP7yjDzegJwYK9Ckxad0+K1oOGyuZ+gCBQ+GNcSePXtTcEjqPS
S6Dj4qtqjgZbLDb+Mik4qBPJxcncnl2VXj1dNkIt/2zhPAqDUE49KSpOPULiDeLlga5lAj0c5hH4
pBBCx6JxXD5lE+rT8F+1+ALVvtANsfZzWrP3KGjBWg3w3Nd/ljfTOHlBhiZLXvO/o32EGIf67FqK
AgBofS+pbg/XZmiapdOHjt1ITNfkV5yLFpa9VMvGUgKQ2Z5IcfFqQ+h9wGmryKnh5LogBydfOcdE
9RDSV8xl0L8xsMRbnmbuEdyxiCI+Ans5CqLoczG5yOhbIbRs0fn8GyBh54IDYlj1IVeOvDwK3A3a
PzorxTwSJGH3JejecEBG2kuPzOIHg5cYhk8JznsGjbRHrn/VzntS/LMt5ed9VotB49lpbpmU01Ud
FwWVQJ6tIXKXRLEdfM1W7LiZFZhMwTE5BEbLXoccer3Z9RRgQYVpmhKQJB0DTGRSrAy3fIPHSwXi
NGIhuCGV7zy2pORnTOeBjo8jh2A+cJqehZsa7wIMHwC7yZC0BgRtXAqm18DsRnK1IH/TM9dd+ubR
Z2xh3Ufq+D2zlVaV8SJj0f/fl8JKcirP/+i2WHCpbQkF5Alzhhxl0Apchl4Jj+Mm45HxMV+BDCWa
qS8wvoJDzUnWRsFS0mMwHAc2coBOpp0wYASr1Vk5cIMoTbGmm9jeVJtuf1iNnzRlNE0gePf1gdFh
fvkBIfS8Vj7IkybxPt33/UpqEuEMSIoid5xPQeEPzYPlo/zx5RlCpwnYaaGnKeBJ5Hx3f6AO7JHJ
CojHJQoJAxXtjXkY3jY89TfXWcQ1BqKsvf5LJnoTd5+Tjgvga5iahMa2oUvRSg0q0lG7vJ0/KyLb
Xqc3gSYsVDPudY6yAIHknhodYmDa8+g1SzjpBOWziPnL3yx7xNyAkSK8rLwqvRUzAO8PcZPAjtYx
+sX5HPdplWxX4fePo7SJeDEheAjIeSlxnPYUwD+RJrM/gTMu0gtGwGZHLHAePiew/CapgSp+F8Dc
iL+jP9+lsHQ5dJcUkzR0FtaFIQru5sqknBbtUo8s00gvYtlYUI+ki21wgjLZPBFN2SvjdQc7dwSl
VDZsgyjcUcIzDfbIyZUZ7Xw4MU5kjs5JT8t14bdrPdxIvYKSUtlf5Z6HrdLsSV95F5SEyUS0HAzG
EXLwNf8BFg8X5iztkhuj1JAjgR/CsSO5XQ/MCHDkdT5f5Xjz6AuOgcjxCU+8KhoFx9s2n6jCwbak
GXgW4ttzXuyX4cnZGXKeGelfwMwLdgKXrhE+NZ8i7iVK+kREBDenN5sE+ONbCU1Yvri322Lt5WDx
qbLcdEt2DrPYYgmW4dRTas2adme+nSQedIwS5lGZ3ZOYRP/eEdDLNldSSYi7A+1L59vpI6Kh0A6o
0SvFYocsXLGlpb3UL48ipF8sfrTOz6YKqxsFztNppDg27TqIzn7t+AeL9JJSNa/VxPvdO+dh0KTU
KlHSREHf13ZDckTv44E2w5Tsr3xONTvEybUW9uAlzJbgq2pKNT3ISAtphJjSHHm/Nlhj2JTHecgM
8Pyry/9u94TPeOH4tKFvatEqsUIiE6BQti4DKoZyye9MQP+axIJaUFcdwt+KjUB04zoFSlPKFQkh
QIqlCzZlOWsqIxfZyK4iVdHVwvECR+6kt+kKU4ZhPnGTCDgoRNCvVXyTwcluauQkEjpdZobm8PZl
DOyZ1fVPPy6uSR00jAxKXpM59j9puz588Vd05QRMOdqeM4FAwhQg5Z3aTVk5MPPx9HhcNMhOHsNL
F+7BCm2vSzllH37HBdbTATcRPH2MXbfpTsLSIhC5762pwCAbpiZD5GEgbIS9aCdigRS3sU9+CNh0
qk1+Ry2T8dgW8XDKx1Y8UU0lZ1apYPfZny+asiXLGM9b2aAqQ26SjQfeK7ORzQLUPAiEOvDhzSlB
g1qACSkY52BusgGGOBiK045sOATy+S+xUcHqe9uMpqo1I4sVeVyoa5KO2h22ZxpsU9TcQeNs0qx3
+0fxsXHpa3ek3OP7PnZakBsxw4x9Bp9mBd841OxoKSq/GD1Jp4t0Wu1qEvDNT+6757la/ORaXCCM
GX+K6TcZwDblDXmGyLjXqD4BcF4gq+YFJNbc+TmYBXWvw8Scn2+9/uWqi471MFSPSkBwH/Okgiu6
9OcPoQBTBA7MIXmsux7XiJ9keIcSisyQllT4Td2Zcyt8BlDsxeG00Wa/39MjHfTvRzTo0JXtAdTG
d2Ixqb416OizPyoxTchkwRJvmS1zXvqwRA0tn4LLZbYWWynFELqqPPhL+nECskY/fMSc50DsnzU9
eFfW0gckBF8kh5feNCcQ5BS/rq2X+cbBeMz8v6Yzz+p0JtzujT18vknroMCrY0p1EuJLccSpcSEa
sOdudQfxpowX/UCUs09xEH1Wi97pKWFci/wM1xcKW8PvfjjCR17U7A5ochJyotBZmZniTzTOx9wl
vqRF8Px0QREr+6hfFvgA5BrvP+09x4PZVVVjRcp9PSU6lBwjbqcpzOvwCn/3pWa8IvWB7vnpqiR9
tpJoeL8hl3WtFc+hHzSSQbC2y9V9KQPgGAxY2TrvGEc4HOQgqyC4XuNomNWs1TGYVUHd3+tZKvT6
DDisGjHLWe9hRsfc6eKLmMIWANdLD4LSJfdjbhrxZ0lHZEiqv9aA/Q0JOJLwLXvKVP+YOlQEs8NO
fY1vZ2WOC+OWaJM1xDKPXkr10IaUfe+GfyWUM5h6+osGtZxjhSL3l6GkUflvzGq6o9JZzIZ4zb/w
qsdjq2EYSWCCYgafkFKkXRkpM7TU9/eNfGNAndQi7ZsrXClhkUIyDwP05wnlo2ADWbjp28csV3fL
uPgudKdxRpW6keA5V2fXZbK15jIcHTXCpOaPbOnOu5QefYFbNmZ6nNwJEQ3j7zxK4oaRL3c+oG2l
yz6VEiqSjX+MH3KTEznkZ5GW66SlEeorB9bfdwJUjvguDtIBNxOv9KppPD2Nz8ZRhP81OwTjD1PQ
Z3hXa4QhHcPlWSwDun39FSgHjZChY6SaGzFmfRDO2EfVHKvSwqZRjCvgVIqOuvEnhfalma0PdoRS
OhdYih0k2ROMpH1CLQaFtpbNKJn4vid5J4v+CK8O9XVXSGtjmbF5jw68EFPaX34A5GUYZZp7ir4G
iO09p0q7CSfJlJIeBgGlzaakj/EAwWMhdFnOoL2itNA3tQgDPOIOYY3K8p0pXHCjE0UJrJSMzIQv
ebBrwqwEz7KyKtIvhlxaMD98GfDbjOjjDDUm8oJMmhhv6ITNSgd5uzn8V+lmgSkl9EoJIVhMZUmv
RDqgDJNuXEdQlVk19jH5wdG6wST6WvFzaKX9u73zQdnvf8G+FKDqAh4ZJ4jXjfPPKWHmSyagTiSs
wLHYNwk4GA0Rsa1U62vQFrgKpUGG3xWSPJi987kweuvvp3bS506sbbeML3iR18/vvqwCqfD6kWvU
hA4bui3GZ+XhVJD3ntREbeXyEdtkefNpYoO1V/WZmegSr2bw2fwUKHJiKyVYdevqsBK/hJjTHzcM
t13iFOxVwNzkDVMHjfJC2WS7WGJPR0oJ50n5TEV8gjCg2BuKCKrrBVQB9QGJZC2fPzsUrHS6KW8o
oYkKOg7cOBTqydQi7tBLgKFcqOInojJzFH6KvYK6Qp7TnKrniBv+9a0l6whB+hEmoPHRPpyfpEg7
IKg/imVWeL0qp6iT8PYksIqXuDj996G1qUrOHSZyxE0NANIO40gc48DsH6/5fEdhJFvC/PISKDZ9
th7zTvMU1mUyrR1MON6RXZYWP82jyZqCmlA/Y4Qe1uFEYsEsFRZu3KVy/ytIN9FUcE7hMLNDJmFo
YTPmmPX1WHRJ7yLk2CAqP+YpZ18x9DmeybPFgjyYP+2p8PwflkcUaXQIfNSGsfD1myUEml/5Tjc9
IEHQXaplZc59lHwcHwx2QkJguN9i4NnT8WKBbBRLT3yJAgrVQ/0cSk1G3VnvHTPcaDb3Riyyfc5j
SWunpInHO5bKXxdE8qTUyUTJoca+UvIxeZDjksjm2gSlv3ytDV+bjsyY9xPnkW/rbO19qeOdpIGE
Xf/Y+0bzGYFmQ6ryDtEkSiQVRk05EuE5qieYwx4dwvPAWhNd2YQCYL4msG+nmRu4SGl4Bf5qrIRt
oEHEMbyzn3UqEVBZaUPCk7SEQw/UQ3qHtfN9KluOvB72JwWk0rqL1WY74DNgr5NAiia5eGpNAjcu
gImJ7N4DXfv1jAvLd5EiOaC8qWmln2+lOmsXTu8uRkXeP+FVGfTVEvzPJaFJsYTv8anSRT3RU1S+
fjoC1LgYRdDln2ubC6RdgemvtveQ3sU6s7ffomq37i8ILiEBL+280AEbwcEeKrcjoxs87bvBKbBV
ARzpRwD54XSyAuLQJfuVWghLLymzWkXBy8VPCrGPAkdhuJi37HOtTkoS+EZ/Qb1QyUdytHOsuvns
6eBVuIpA8ADkwVbZEZSaOPGLQXnaBzA552H6O3zN2j+YV41gBWZ66W796MJZhYzKr9JYGa5E0c2Q
SbE1Elk9kF3XRWVCNUKmKSorLCYiJzq2GIJoKFyAWhuUjmGhb0Jmx+4sMV5eOYkAJuHVCWNtTEmR
84xZd9X6MRfqO5uy99iLY/y2JQv4xstUZP1NfX5B0Bu3fOJ02eTyiMfpXA4V6SuclUB8l9srLpvD
PKWcX9PgYjJ9Xfh+NokGvz/WM5xL255heey53z7evUNrfDooy/XJA2AyF1EksAgI5ZHvzN2sjaG1
Mx/33FfiAkvOo7KgVNza4B1/qzh/HSfu/9mOkihNWReJtfGSF0G3tWo0bIHGHfyWW6mCbBDzEdsC
eAUSSCdUoYQD1jKe309d7BRP/UMn1rEKmILr/lUVCdnNB6Chl4oyt94ZV1QtLG/bV4+HU30b0nsT
bpZP1i+Zhk7ggNLkcan68FuiIQSpRYdVQI5DyvhyhExmQNFx3Jedrx6bBGamIcLXMd3wbnuE0qsn
kWLVkQrlY6J3wM2hOKOCbtCU6AGK9hPlsrgZbJFIMW44GGBjyl1KqblRD9XfEErqho/b7XDfzsAP
ATqvdJmU0Kjq0enLyvGJoyQt48uCaXe9BlFIzlB8ZugsFEJI+YPw9+paAeHG+UtN5/60GdF33Sdd
O8V28nPKfNRQAg/VoZp5HXG3i4k/vB4RCxA7Jr3VyJrroHcyjsAkSYMEudeI5IqN6QciTac2MDJc
/IfEr+hdaYHpsaHqCCUQzox+WF0hTyhpQaDF0Yaz0CYa/GxLnyG0U9ZCmT1wZnx2iD+3hzuZpZFH
C7E8xPnJjM1cWErBczjtIj0gdLsSg3QxbSXMGxVEQO0Oj5xLESBc5Lq2yK7OGZQS2HHjVxEM7MTQ
3lwi0+PI08/wqLNVE/ftaSrJN2WzSQpM+ZQQtqxSJIXLAVolC6ue7yToy0VV5rnHIAsiF525H2eg
EQWkdL/yTxl75V4dK2YdBaRdamKbmVxpf4dq2SXmSWssIg6BguiClVrllhZcVMy/syv9ZvLe5inu
Al3naWlK67be/CfRpx+HV42QlxbEo+mXE3nY3Q7ZSA4axZ9+7weFALNXA0bJzPTsnFRAJhOkJJUq
dgiNTNAZsvL2yvzVnTH/pmsO5dC8GSeS3nEI7c1wiffJsUh92GrwbV/HGummxuRqyqbIsSF2Gnrn
Jm3+qGA/4MHGg6pp14iHMZGGDiqVTxDAf6OYBjOQYpdGMb56of/imigRNAt+W5uSyDMJqkJ4LloY
K7uRhqjrAdY1zUZvyIShZB2y5wW2ufwZXOSXq+ZbXFjh1roAsDSs49aexMyLMXdD6qH2XL23GijF
2zFlpSuklDbHj0t6nQiDnwNHccFf4vy/wvNVDO1t2OyCqYZFVQikVrV4cxcQcC99gmupyMXLRPmE
nhFaP/wBqliE01KeKRFW2p4V/qEce0GQxphWV/JaMR2xzlPuRgv4GNnrSbBXghQ0BEN/D+TRxINW
JDwTFk+1v8oQEGk8KCkGdUnooUikAF/m/c/CttJhAruvI5EvbLj7ldsiGvWj70LXhdUInsafbY5S
8VXrEvQkfjxk2+kYR2iV1smLBcnj1H2pFOqj7F/h4IVKBiupwNfsg9Jr1/9RUDKpPLI5c9H1NYVS
KlmSib0E4n4gAYCyXXUQAt/E+ZXeEm/3VhZUCIXVy267AwfBNolLkahqRDdqqSCJIB7cy1+Dsq6A
NRDZ5kE8m5hIgJlSSigo9b5yGFFstxR2QQeI2oDr7j3+Hvgq8+fsUFa9v1G/cMyye0oCB5UhbiV8
4z/1uBnEyjmyRtauA84/uP+jGkiAx/NPueNflQaWeTdC6vqMqOd7N8ugXpoHH04tcMA4KjnCeUed
WDHRw1EHc3GWwDYMwG3QDrzapkzZuXiJ+yP1Obu8vovfdM496qDdmHFu1KovnW9D4N9/faAPY6Xg
GZc64pJAu9ITRdbHqfgitU7K8052miY2j52Br2xGYC5A4tWLQroXVi+HxJfAKvro/nreFeczbVSl
aDu7ADB26rMIelug3gaZJ9k1vmgB/5gLmvG2COB/V2Qv1fsqACOgxNrwlfNUDQPiG7dQzMcHpAyA
qpV+xWULGmJNHFe7UhHazH2ZnS4xnKQRkizYXSMN2CQN4fp2WsEizIn8BaRjWkjkZ/TvnrWKkQNg
E81VyaE1jSU7v7vMrRTBPbbQ6QEtBTRT/L4B9BYlUVcBPnUQgqM9lM/XQO97dAoRManG/g8jTJYK
HLGSmhAW3B5tXsX9ySbnmLo7Mw+2qFBD1WD8itwijX4N7biga0E5xm+0WB+sm/n7SgCduYDcfRhd
huY1/t+1tBx7BQk2P45L+6WBPzmv0L7zoP9sOXsqQVA8vvvuf3nUk2ZPuybMPoF9G4djXv0XnJmm
dwLi7j8Ohlc10/e/BFrvbavT+CsJYg+DiklkgWlbY4U509fEh2LitAJuEZbDnRtsooJ50ZmhSg/2
V5m1kzivCZ9CN6LuhZvWD1jx/BuCzOHAxCUrn2WLylgx+RT/KK/jP1PmDqVXkVOlqRAo4iiNcXmX
vRPYeUS7QM61v/wEY2RFpRN9Zlk3gvGfIxR7lyvayMw7hJgVGoU22OaWFO+rbdaJALR4CP0LlBgy
Kp84YUDzudU2zKjOK8PqyW0f/7/C/SOLQwtEQ9ORI9rxk1I9YIgEnt5dLTdrYp2cbD1HSsW/3JgI
DSkkK3dLVYi9GVbw4vDlpH6Y+LUJ2iKIQDcMtO92HULrWg9kIMfSq9hHZsQqIYqGfLIVeZGxvQAC
E0T52qJ4BZDXEHXU1jmswfbZVmDOOr3otn7GD/rzFcgFC3MHZW1Ls2ALBWX9xP+HFSlRbuMkPmhc
rKmKvHII0WvPqIxlEauY6SnERuSUBiank9Gx9MZ7CrlymrIubpoT3BisUHXVghu8BDs0o9/bxMEm
iUomyeJfkUIGMdS9ZQiaq8NLIgGARANqKaRIqgmOyq34lSvhOesj8yBUcGVGsPwD0P3WzPwePtd0
bdLTEnD/zYxLMXhzQDlg3RjqJ7XhYKCpU5NJfZN3zBInjBlaL5ayNldBcB0szWEXNuKTlbbXK705
CRTuXcM1YtLL6xVWGxe0OIFiH0xILlq3QiTZKU1Svt6dkflAZA5tR3yU/zUg2XU4lmE/28pmY/bZ
87jXznZfjXM6CvzKUoLqb1Ub5mWArJO9ahfBhU6JWhfQWcPqdZQi9IUDSIVondvc6K2dkh7jeucM
vyjKue+ykI4yTvXCM9HnBkrYXCJ+q8jdJfW7sPQkTthUS0H/5ltBtB7jtWmY1KnIX0eIyuqhMzgY
IafoGprO2de4gV6gkvNGIuqo/4ONU9FRkaspOEsCMe+0Kz1COC430LNs+yzbMnBo5xRxGG3w6L4r
bTr5e9xXp1YtDFZ7XSvTAgpypQWwMyxF5o04Lq5aziUzHu+K6jb6aQEP2N8A8hCZQ9CQrQPOwDCD
+jOy6NK7HhgIftfbX/3jWRDHrFbYuEqSVgrTH9ZwfIpwvOK/UIsMfK0XGBAPV3/fA0rtHgesb6bO
/q2P1Aq4WzeG9G2PmOW8PhV+Ut70339vKUJ624zxRUbfVMKDmeZe6d9ogvnIrJGcg6n9/UNclAY7
I3Py/7gYg10/yEJB0WCLLaW3B34suchkH42B2gUeZE33uAPzARfaa5ruClUYDf8I1Ed6vMNt9Fa7
0KKBBknmwY0dgEY+gvlQxvkrJYensi8RXnpmz59ThG0I1NpI3kdsJB76TM8653yIn97lh6iAaTFD
2wAYMTCtW/CJJg6dmFHkZ86QAzAWKqLe6qlvU2CJQd642py1+m1HQzCj5+GzParMHmW4WNY4oMS+
A9spiF3SnUGSVjKex7TMmwmS36GGc01pWHVQoW6o0m5xj0hd+jY1uPGJU4dsdki0I42EE9GVtHbd
XN0VJeppfaeGznaM4hgXoa5lODxn+urgspfdo+Z+OquuxB9RqD3T1bwqs/nqoNXlxa/2RQZXx+PO
NUg024AmxA6ZCyDGuhJ85UjHOQmEVNH/q0/15Z6ZATpIuLcjiRqr+EnyGaIFWiBmBp1HpEboh+Se
Y94oWldt4JJBnERcn/u3Xdx0SM71GqhBeZe8zYH1SNkupKIGixNW7FgP7oZrS6bOAptby2Kf7Tgp
0+wJdqohNUpJVToSL/5jgxSXTvFxkTMYCzBXsQ81ISLEcrrfAWMwi9CX/AqotUxmK4XQFJGvhu9y
bWaNpgo63PQ//smmfeG+jvMTwM82aZQWv8606XlxD/vc+ULdoipAd0fefEtG2GLORCfkjZnsSntG
2/BauW1p5tulXSi1HMb68L4m1ODyIKMeM5hB27s6Zk+ZPEe9Twmevf13dxrEfkfCgDQWf5+IZT78
mvjwClDuKtjXs2cW9e/VerMkrLPomc1YoB5V7OJPqS/t3HkGNN176m2Dhv41X1EGhpWphITz3Uub
mUsi5ah+Srlmi2cT+cYz7JdKGyGR1Qnq5j9fsXS/PElBoBE9pd8+PkutDyLTOC8b7KD+JvScFjMt
39YguX5i+5qvinh5GXc2743Qwhk+xQVEGHaPy/NnQogTLxkUAYN4DGN/OMpVaih1uSlvCr3lUt/f
hqheST/yPyrc5d0MX0rU/YZcStQdipcxVSKkYiqzG0uqQBdUCagn3p2/Kjq26IcofdrSi9/34XAF
7GsV5Js2yPefS9ZxthwHgaHRYgtNVmd4V6PomJW1MPlprDoqK2he/RPk9EzkSGR1uCDzCLAOH5gu
B9G2kG4Peq4Kbx60gq/T3t4+wx7O0dpTxh/RaIjxulnQQVrAw+/NChYhivcw51UDKHWVrEX6cnj1
Qbj95+4tCIErmKqRr6cMPAS8eISCbgfaAMOecWj9icxFNA82TzDrmejyEZ1JEvNWvQnS5ybKPNqD
6rNvexvLRDT+cpH7KGUuHniwKEKSrZRbxBC6Os8M8BRzk+P/63dVeOphCegc6msjSXvMsHo9yadF
n+WtXNceAVGtJwSm4aNMBQwdM7Q+ZZGNB0J2MC6l11TBZF+BfUzEu+WnCWzANCEiBPMBwcghYETo
Af2FA8qFHO/pSn0RVXW31U1OAioijkRa8ym8gMm9d8v976knPZsIMBQsTpLDrfXDsDzFe/z/hWk7
X5/lbw9Gf1+pIpLByb7uacGyEgvwz+4uDoP1PAc4Pg6gAb00MK97OIryTLjC/4WJrQlY3crhQgf0
XoCj1pVWYUmmesLw1A/gsB0zU1hv2a0HmSOcd1Z30WamZ51HFzzETn0C4KCVrhYMNbbq8NdgWjJc
d7tIiipppfGOwtV1pf0ND18sYb1OyiZ5vfy40Vd8Psn8kb7OaDPNFEcCcBfnUVxx7JFSq+a+d23K
/EM4j+je7Eb2BZOhTwtKjHRNfuazKMwyHGKzxjgjITy0c/SazygxSWhhVu3FbxFf7IJnQbNRzrAr
DlL6OaiaZFji5Meu536s63zCSeuSHImzBGD8cYrjWeHn5ySFCs/1jSBBXOmNi0ubHpb8hN1WXZW0
zT+MAM4BHdXRlHBC04X50YGU+EWMHmVPXUtTSVCmIJS7OCMPbLUy0GO/rFPMHnd5fU55KnpP0535
PbhA7gNDjzgSM7FGOLQCn69FUw7FPcIbaskRqdY2g7cgf1UWuHW3XjGMsYnM0lfykP5tIrwzp8W5
DSpy8v/fYgdtERQ9GJsLnTHGknsV/kqXDHp9Dqwntb2bm7k9AQlWAa+d89BlNML2Jle+nRnUo4Et
pTNzQwAGeL4PXMnlu8Nv/Ra0n9VxIbE1wL0ZMXOqxHtTq0KAJvc2rGmyfecdtj9elSHrHPOLULJ/
axKbu1p4gT8ug/yb73FDvoCBpKr75XfsUlyxC6I0nSgQbMBjAc+1jlFB0VumlRYC9TvZJQo7EcIV
GXxqRBBc3L0GZHbbgvHbXtQ9UEKDcYwGvQqcgf76raN3v2BxZ/BFsHkuHzqdRt0L+Z4+iazxY+dN
eaRx0H/6nXnUM8SvOxkDdiw6VtGJ2trQaKXQwn3Jxzx2tv6gHGDqPDx9Yq/kb4xLJjtQw9iUKPhe
QA1jJLYIFkIIIZhCz94ltQqy5bxudFQfuUOoKJAuA9DJ+/d9L21TCePBtj2sxh82n3w94ycMLaJZ
4Bv3wClPPnZ03faJq+AiDRcNSjuR7l+1rZZVbASShWDbehUcD1K/E3M7Y5ARS4F+tVRcEpKvEKeu
8qY3sK2W0gPMncDXb0jUOcH2Nrx+o/4nCW/6p3BvawRkEc2Y8tCAm5xUnZHR+phSy5kntUkyNvRY
KmXcrMRnqM15JHnacXXDdv8Lyep0jlI6SuuIIOMEmZLLx6RpVoaHybBZUEgC8aDLSCyyodRHIMHh
LWW5UzjxXCLdfKvsRaa4vS6XOHweIkyZAShEKqit0skfjCa+yVtO4mbLWRRPWN/SdrGt6yCt0X6p
VRGmsAHPc2s4ghQJR5D9DO3vdqa4YBqNsksaF7SJfkS82kv5eE7Xv/v8k2DzyJVcGsej4fPRK/Xw
8ooui4UTnZ2SEc9SGQ2gRU6Cn4DiFLtsMDdgpjCuDHKPjbYoU10UGHVEATVixP2bVmtQfLU7upq8
Jxq+Bp50mxtEpkfDez6Z7e8ab2lHwxbBYgA/zJ2dIXZKYzm5NZlK7ZSAJGh/DqvNxaJffs9uuHgn
KWv3neMH9W1akPV7fvHWMic4UMCeEujctAslgYeE+FCVJMqKBR3TrIFs+3r1HtRlAJAG9wy72Zmj
BwWSxYhay1pkSzwU+nHQKi4ovcwpOWF3aQ/atDqNAC1Qo+4j7yU/NjFuWixQ8cEGlEkQGFd918KJ
aT/hsEduESKxf/wG4ol2R5WT69RTMwKC60wncfm7rL4DEhwrPxVKl7m0dVSjndD5BN3jhe0W1bNL
YL4NV1GhDailbmBEC8O3fAj4kAgQS1BD3OPEXeusNELoWPz9I06fJVv4V5gNjaDdAzUzqm+QHPhi
NnlG9qWe0DeKjxyrvIBmfjtih8hdnsewjVMw8mlCZ82S9euOo9pIUxKrrW8iokSItVCvGb9cFuGJ
eNN0AUx8qpXm/6P958IdBQlDWY9+mfwHElT9Vh45meHq2rwt7O43QMuAPb2iTfoa6+ALnNh4ymav
u3VOTucp+KNQmLpxnTlDWETDB0iD61mGxWbQnROtg+blMCIyCJzIhD8/ZG1Sxs1/Plr9rLE3fnCi
4WOn/hvsCYRuZeaBKQgWdWtE472AEKDqQJXxFpOqxuqMiT0V5bIIE4iAo507DjGp3mMl8MGInzoG
vn1kp2T4J41TQanBIuMoJS8jlVw7EKy1sn2pnYVFPkLRadGHAhw5KuWhgjPdUosysVpKwtXDtLq2
6C8YhbB7XVcldkmw4SGxIa3JnC6htrcjjcu6chYpx4mTkda/6ezQjkdKjMrJeleA9hIsFhbZjwPx
SW66hNeyS+LZCjm4iLDi86plfFBfH/8x1KnqIBaqF3+C92xzZqHsl0seb83yxO0XuCoHRt6LjYZS
+fTFF+YJqLWA61h3gStoanHQsJxuxRUjPKfPF5ZRvgkvBYza1oLTmuKyM7oxZPWNE4ZR2vWgvcF4
lQbeHJyZI8e9+4Zpk+2Rp2dNe33AnZQuf36Dy9aJvOr0DrXTJ+5oscalhc8NIfgCiqgc7liLiBo8
XCzRdiirlT5BZTGKRMFzEMbaz6kSnf/1+aG5CtLX4WEbhr4XnKkKI5iUIrwquo10b7zMnuaiaCVj
1YQgBxqbkH8DedJdrfwasxubOrTmB/WIteKqBArhqywrrRNHiWWpNcIT9t29s5vS2ida4wH4vGNQ
usTQ5dgsHjy510l9rx8rqjoqvmV5gRVc1wdpkWaPr1cnq/Qx1dIwly+wNCbIAJja1XPAzpWxRxo/
6457iWYdcw/jf68c6umNYX5qx+hVJSW34xsstiog2h6q0mjF7vKwbn26AKO5UwAuNIVjY9fbcv2T
WR5AFK/IbE8k9WGLphjGKA6GUC3ZEZpHm/sEPkVpFJUbNMjSGk55wGX4seCkHkpnzr4OzvWz65P0
d95jupRaVyb21wpuuQlxL51XfjAmv8Q5E3V5zsaaGXf3iqQr6WW/oDkIFfWuW4EfIybtWOmgKskc
+SKDSRTtpzIYsFZ8UHw+BkZrSdnKthj4vGSi0TYiVmLgBdXYJocOmlew5D1CkcoOgHIndxPJ9xh3
H2BzO01UUAUhQ8BTEmi/VfLgkRQCRwYgjO/F4sXK2FaXv+ECcWlu0bOMF8Kn4whLfyim4Pfg2SXV
oaOSoy6u4KM4JPsfhcSgA49H3Y2+KIZlxxkUh699ayLYVD/Lm6sTavaF9AJ6HxoPk9qNK/EKBCmb
OM2VEAKHzvCcb6nXXOzARs5zpxIN7aox/n2PWI39UjEEJzNN8jp7NNwN/PO1o+m4GwZozf6Hoho8
oJFs2yWV4efNhg9UV7y/x/6nkTZESshbs3IKHx4iAGwBES3QjqQx5LbPdt2EwlDg6vXf964VWhi0
2biLKEElg13Ac8s7bJuIVNOKVCwYBfFTBhIWgoztzG80vZQYvOJ16w34xX1vaGGUVwgmlRTP5RIG
7F+QdiZApFLgVJFiUrp6/vGgQubinjjKmHMkpv+u/UrVmGtu6VN5lefzEslMdQfoI4h0zkjrusL1
2YW1HsJn2aM4rFRBMGVCaGcAXsSktr8saqxX8wGEyrgzPZiVmk+lSdLD5kgF6bvlT3W0YR3a8Nyt
X0BgArSAJNr7x476ZEi2ey5dIZJPuMHGu/GbIdtlhjTV3fbxIM71DkLaO8VnmfMm45gusRRQ5IFV
IWwKxLaEZEiLa+D15b1IhX1IRdOWRK78Nkcb0eoO8QK84FlwMbxQvCaLi3NmStzWZPqxoJ/eE8d2
ZYWXcTu+OdfPkbeNsPlV0vHcfbnAKb00kHjTIN8kD7CC5ELDdjOLiYoL/6LayIGBodOf/FbdVLf8
mi21re3EZv/INOPzPHNbfOsFQWSUUGOH/u+HCDKwW+jWow2qhr6DwqpY6ys96an5NrZLO54ZE32N
fN2ooUfisAk7qUo3Esxjl7OU9j/Ep/H8WSH/7u2hTiADHIslElY6Hxa/uMZPSmQaiqQk52/o55Om
Et5KtDDxQITF5c9AUK4cHhX8+ohPVYGPo7bKFTuMD4Qkep95ZFIoNwk8Nx8IPAsBfFfjPv2foBpW
NTIHxQx6cs5Fz/0KxRgSquhlc0C83XQmmMC7aBJHXRbt9zXl+fyh+dsNmEYx0mG+a7gDVHxw0qcI
XbLL+fE00wUfgEQ2H9KZz9uinCn5E5PB0SzZWLExTcQtrAt4GdX8qhJdDKuRhbts1fZB1SYPa5dU
nv/rAZUJi3JB/dqVSaDhZ4blc9BrTxW22/Xr2aQpV1/E1dX7Q4PpkW5JlBhNXxLohtetCfDT5ZuU
5qXjYwyfQtrHDzJsFlCMXSFAIprt43tJNGwindCIbMINPouvr2h3/nFKvkBmiawO2QuGkllmbSTt
eIRMkZSpI8JbrjIAQ55z59sVIr2dtBLEjh6/wi/6aWYcRa2zcbNc7RN057UlZYc2sGoxA6eAJZ1J
+ixeRjHCLlF3b1bRDKg6plf0+dwSt5/G4Z7uVP5pz2zdpcWv0k90YKxIwyDJXeRjgpBT2K1HVxnL
Sl4PFur4LySKvRUNYA+R5tl1s4EN11EhmHbsbYmKPgAkycvGopkweIs3yBhHH4EEL0Huk/Dlv1PH
dao8lAuJm46ddf/B4tHHwVeVNifJbPG6sVb2iBbiBBxbKdzAg/J564J9smW3isq90dRjPDOt4qju
anI8Zv/tMC9Ws+Tv+1ecg5H3jKLGhZGZhv2fCaTgHGrhwUhNOtI3tVOYCv0OQsy0RObMyx3gVIz2
aWWjQslaMooQfx1Dctx+i3J6a6v6ieE/KCeZKtfLqQ+3GkcWGSZhYoewoH7mOdS2tbf5U7bFBO86
lEk2jmIZpiv7VcVsCfBYmLbl/0OZDSZjeauXeqQD02o/OB3qnAvdtClwKQbOKGBRE1ROeIzt1LxW
anByWaSOgi63L6xAiAfQmokZu2BUM+tG30v46EjnOYKm0Dylvuj1XcF1O2snwUQk39OxPcHPL61U
RSWn5yzlwuDRdmZ5NrhyBsDG47eq0sk2RxtHquRq3YMFNqjrEH3bm9CgtS2VOSsEuEf9eYmmLYUD
chemh4dTIJQ2hg4jiXXFxI7UCtcOCpmilJTKzbSCjzf+WgxB20YAxr66WEUXE8YEgqKDJN//US5b
pplwyz2k4lJR+sM6TavABHe+HWPUo1rn9WKHCCVfmxVyVZ3g41J2Uf+OGu5FwK6rpZ1Jx0Q62LRY
wV237KCYaUGMB9JkWoubzniVBHOfRJkGJrO62rRrAPhn+JBQn9DmiO/zH+d24HyVmjL76TT7Em+y
P3juDku7rxLaOc/9RTkSe9opw0XNFmDShLfZhKhbrcd2mZyJ0Z4enrgc/xGGME5t4r5tUYyI2KqG
8iO4Z/BsuybrGolJDVJBYrwNeFjVPp4OwW4j6OzrO1ikabJjcwGE4o29Wtf2xWGEhtC/y2RTDNdV
472Gg7xbEAxHavUdc87lEoRL7egVCRGvOu+u2pytM1BqH9iijJNzV1ARC3AUwMnsS8sdGhozBXRy
8lB3RUG2GmxzT6LTxHgDggGvhi31Ox8JYfD2fPu7Dv3I4jWibzfrBB1kUKJPkN0VJ/BZooAE6m2h
NSu0KOb4tyFWSjEEOfAg5E67Ow6ldjwP1zt07LtYy6P3DaOeGCYmJ8wg4FpryjpIpBk4o0KJampE
SDrCKDvNReAPSm9XfywwbJvLdO62srCdJBViPN8OJYIWxTMTMOkIiClCOR1vuOehtOSsUqQtEsQ2
fGZa/8SYpWm+ysG8R401LGIFfxsVADu4FFQpBsfviJNgg1RM0PK1RFCpuE6yEVzps2Cd52/NEKqu
wmXdIwOIZ5HCnE7FlPN4E7oNIk1gWDFn21J7QQ0YIXeYrecAWUpjkLLkkmzrakVExDNTVTcUGrcE
PlN/o6+EJoByVyirPBguOuNQIYtwrkOnp5SJiyafnfnuwkCCefzDqbls1bUcavwFkMgxsTEgeMuz
q3LV4wF8+g5YIhzCkfUMeXoNuIoEGo9erJg/3mvDfi6Uw+iotdTjMNj8KTQXOLvPpeVLlHrUHgpf
UGRgXZ5YNk7Y2aieN+jrEVm4KH0kOieUBxFwioKR6vISleXU6LntY6emIg0dFxXYNbCa028o0RfO
LbZeu5kcV4XK3Zgh9YigrGMtiye3AzDCs4zseg0VmX9TS/j6rgjGGrjM78OL4Mcd18eBn/LT/REF
if643lQk/cJpNKitey1uwO2QsvvmBtqKyaCTYd9jS4gzNV6eci+HshUXpgmx3vFbHTGKygZNwfWr
vX64bYGqMMz33sVKWBYCH9uasMyAopxWQPFBhniDpT6yaSCYLh0SZvpME7fWrsyYgFs7XBfBeQiv
sxI9IFjShWrhJGKXzXMzekdx1dlpiLmhbjhBUq/2vm01qJaxrcH1ncaq16eSMEVNhEFO025yOUZn
SWrKhe5dVM15qY+nDWOGJJrsjYwYKl3q+KugehaGxQ17sHJl4Dv6Yaw6kvaTDItdtMlR/0ABfk8D
dvpwXbczWbl9OhJPMXUDgyZJhHiCGp0xpRv2R2Ji46NPkcJ0hVCimenTk3t7UQA2OWnUxArTGHec
RL6oqzDyvpmC4HCOWoql2s/vK65+0SfLEI+1SmmmGyRCrpAN3rfYi+ialPaV2/dGzbgsnP/v1HXE
/+mn1s6vlcRJ56vG1o7rWnu2hU4dLRgWLp72u//29s6Ouh/E/IDN/KXA2P3lV8YP1/EP5avXe5mh
qI0AOPmc/Pe/mFUOViCVFpnseHd486lAcBP20qWbfB6REJBEGupbvcmbx9DE2uOzMCRJBUDZnbz4
DrNtqJb7IZ/5ZvZvAj8z/A4/xOGcgTDzVy6DVp7AvCoBVyfSx+yh9tKmlGEp+MkNjGp3BZzHSjM4
BH6GDr2J6t/o7+BdwfW9OMDV5Dj2T5x/P7T9HE9AjA6G5XKkbvuqMnJv7W3OPZA2W8RQ1ljp6Gwx
Djd/Nr9TDcSnn4UgwcOxqsp09Kxyo5ZD7+iNeMKuT1c7Vr0V7mo+lwVMPSYCGoYGcQtDaN6yM+/x
zgnDi1rdWrwvfIb5MM3MG+bg3vcIoaBqlJQFlOrbbrlJ1BegqPa40WLVo7GhpsvW/YRuFg+MIT+Z
4bdH2kGvlLqHq7eNNZtMIdsbpWNY5L6N1rojFlGYv3MzT6oHhaO4Ks0+k18b+6vwERJctoBwHDyl
FjTkKpQUHVP984jH717FSHEkIawOzm0u3iq03to2NYtrijJpSDQCQdtrX1fYrMXsFccRXx1uvgZb
XoUWPvJAngRB8Lx/8+iMsvHRyUJ28lLJrY0T063UUsxZVmef8ReMskDjz9tQdeCEHCI2vxs8J8rD
hrjseolZcafiCqWT0goDQh4KWZRxt32egQZfj8IsNo/OcjUSOhr6Pg4SLf1WP7U/EEFVJkCr/Ofi
M7FK6agjeBvxhTeErY4RPwFhHWQVIZgPeAxqj4XG37rcVxhPoVtuMtXdULYn14EshNq4RJ8h3WIl
2yHSQMUDHV6Y5L9C93gSYBiZKIrUB2JD0jb2IXeHEH7zvJ1gFMMBT4o5psHmuqmgkR+nJP1MwoWd
HESpe4PO/V7xgFzdZyX1Cl27Yg3fLlTfK2N4Acvjx3RYBFa7ebjXGkvwqcUOMpPDEb8R6ZQ4zbE8
jtWbMqSW9J4iVLc3aJzmj4pjGswBmLVtqYSd8k1hbMtKt6/OOgzoRDh3Mw6a4ft6/tkEBOVLB1R9
/GVCWhnFcp9AtmJsoZumI8xWX6eJjUyMeEe4AyXSuJBCkB6UaU34VYGGIoQe8fKzjsa6KrVjaUr8
yCWn1MITwAZz/rQtxLsvxWMNbEXHAVMJJgYoRCtOw9NYK2MvLBV1XgP9TFEphrc7WFvq4nrEwsl/
wdvD4MmiK2sH8qAw7c7qFxlrmJDbsKIzkKEuYkLLdBEno2Xde9bHsITRSY9oR89cr7JJfYFgXIBl
dHkMMYuUDuyXfa0pX+yWlL/pYnrPOdL+9WxVOmFnAlfXR33yXeLdn2qhBTKF9zUZHd4tbTYckiKh
lY92GMykzpP63YKhPpl/vnkcg/nSmUIDwULWhP50kHUCWDyRK7Qf0O/b7S6k2YP+j3LUeoXImoXo
WacdC3Y0P1KSGG+cGvNuBdLovZV2w0L9N5peWYcRSm48RcMddtj3DmPgOPSwGGjMJ1hWvYM3pCuY
gsoGQJZQzo0HlMJXmpbWn/kJPCITIo/xxkbNAeCP/16fGhNyTtMv+gnlccnECo8fO9K8NSazyOzi
odaNOG0VKmqRcI3K5JaZHEF6f57BIik7knUqqgCZpf9Yxw5c/gilkCdw9N7vXgW6X1E0BIej+m3J
1w5UmMvC1A2vqTDyYu8zjtD+oQZLDrTfJ+RsPcqKzfi1Lr34YanpgVPrxGvFpXFjWkYEmWpTIeL3
H53FVgpM3n5+/juSMh7Sr+G+M2ptBCctdLgjKnJ5O59gyilvznNGDvWEY5uYmh/fTOlutXgQbcQJ
pWW4O95duQ+xNlRldwteL+Wj0/6Bz5R6AqsfduTNpNiSAH9G6S5NOrSgzLgeTMPf93KRBhIX9RR9
z0Bn+ZCWWx2d4zxVFbvQvxmCF+06b1IIQM4BUsYsFnhjQgEeq7oXdMQfB481fc7IswxDZLbp1uch
anzLIgc841WkHt3bnDAIFl+Jq65xsaTFYouQm2REXDt/rrdFJG5drfllXPbOSRb8rE4Kw3wunUJ4
rAS0QgkED8ji4dwCLygAJ0OvqVlziMqBWC4yIVtY9Tj+fH8CzTFVbleKMFjn7jhO9YW31yAX1KqV
qx8VYLqkR6Byzun+TVbiGNacNUME5BS1aydP9lvZs49psue9bQFDCR1PcnP8blkAGpB8nLZomPOd
ux/7EXKx5lZ5tpr7sF5iBIfZSQjW+wq6pj5ReQOxSfZUNO4IvDmBEJeIPqCfX9PPSUjtdinQrUlL
1OvpLWVr8X6yqr7mXUvQg+cvR6RxBoAWYWo7jXFQkkj7RwpfSxAqtd9YC+Wvf/e+WJ8suizUwTJr
ki/B2CceoDeGnpWBl+TSu4gQqUb8c20ExaEVjyWrmEWcmhAnoG7Q+IpRrrdafbc/IyPz4o7QdS5d
LxOal7mscgI83As+UeyUsJacpSdqfSxiFzwyBrEfoZImICHFj6wg7rC86YrHATPPLWKN8SKuyuOA
hGkra0NUBJecM1pBEMQogofcrjbVOv6iTPIa5zB9dmIS0Sx0tLmxAc5mcg0V8EQVLxbdY12i+WbY
QHFb1xmLmm/a1HVx0CKbt2g6ccoGApdwY5iU/2N+TqTX4/ry8rCNzXF6ZaxE9eTl88Lv5YPnHH2T
2WhZHvi4vRxMYUak82U8fWBf2n5MlPovxjSLcEdVZbXOuLOSzcv/+3K3RhyFDACYOMhIxNzchZHc
43TTfRdiVyMSn9o4h532m3fRP8baCi60cTHGn2uIb8000u0rM83T9IG6Jg6BbAz/GrzIZp5XSas3
vYNQeHSwPnvi5OFIBd4Kvg33OVE/Gh8XPApFeHD5p0HFq1EjW1cke2QG//0PByJiGGJPZLilZF6k
AHHTrhINZFYK93mQsqU8xn/X4rk4hKN4xWkJ81ZGsN8NXDYugN4YoBtKkjkcHfofgemG9IFzAyF+
dWjP7Rb9tSigjSZCh2MuVeZ3/NBxfJYsatG9uO5c9GXEGSjqq+dMFe7+Nxlk4mYrDx2CnleHF2wA
ZwfyJx77TdBTTEE35pTFmOdCbF9hFt1eh044hd4LjumL5ODOnvaQXNzFY3xjI09c2G8E+01f75FE
PazNOKfX/AHYOFVsZTlLcy+yH7yEbtVvnhK5RuUDOHjk3tb8KtNyZo5JD1KIiVgq9yOip8WWLrQ8
dClAZu/2QsGu7uA0FDIHzlcpyhiMx0xbQ/wge7yWb91lJpkA/oHwgd0acDwPsE2CRh5TO2qXVbGf
kfvrcaKOMXUXMcc9UOFaJDZ9rG4IFjtP6oY5KRJ+74NY3Xl6Zho8SzYpE1FYYpZt0CeAKvm3HDyb
tvJtZ4hrvFfTXoDnIrArPTZ3DZHb4vP1qp4VhsDRDA7ITxcKcoKviheltGJg0Hy2isn8eUyQu4ck
1lrd7ieY969JLO3oD2Rj1NB8RrCDo6nJ96WIYrhxYFBv5R06GPAEVC6kXFf3EwaA/al+jFkyylxe
nqHL9bdeIOse5OkJKS69tMHcvyrkg9LDUaTWenLpPVlZzG9Zv+sYWd6IRZTAlUvLqY0/VfckezLx
wCGy5xSq7BnvW831irN5R1Q5N1K9LCZEd1GpduWsk7t44wdz2/8MQJEccbTpkr9XvpCuBc9o/39u
3Rz7zhqNxFASHarjIGboTjkGrWZhxP8zc/7OGm0FFwbxo1FHQrzeaEOW2cJryWwySTEaXNd/HThq
Jj6ODzkVts6A3YqwYomgklB386cNqSQkA7NnhVGkI8pJ931V/n1W2TT82C8cgI8Q+BB4Z+9GAUtn
rd8yFJbh4CmSs/6T8SfFAK5mX1Dz04XxkTFH7OMg8kwFz125qXg6ljtWvSdHs0mUpgJuR/af8OZ7
mosenaYn5PWfapyC5DD+Cj6Bhn/Kd9iBvWbRuy0WtCuO1IzLdJwZanUdGcAUh6LwmM5LwdxQRRhK
Yhjk78KzNuIG6cUq7GATtBlKNTej1zGtdJ2+3NmkbacJ26TyBQC61ED68bz8Uivz/dllSljqSOtT
xIscgMYerOez6PsNMP9gcBhX5/Uz/nwhpnzyFRemqFCi/+XJWLjrbWLkvUSua1XblfgKTprP1OzW
viRsjD6/Pan5a7Xzg+RdbgffImt+ArCz59FV+I4D/FfqUWimSThmePtHjPHrvRqEfXWp+vADqlYz
Qn7TTadnNpg8HrfnMT97eLgVkcBh2yVTS0DwYO4/yVfjTRSzo7rYe4Ks2JslJDby1PmoVuueu6Wx
0wVXuo2FQeYKJ7DCl0LDuHAiepkm3F1vqIlVXBg3dJZwlo4zG0Mht66v/STBpFhCDaHNnoHqtR37
kPILlx4rdggl793ryDHTFABFbnA7ASArRVhTWPef2N8NuSAaG7hh60rroKCRId4V72+pmFIbnCVX
/rUHpDyTFJyu53cehtpt094faUCuSclS9iuLPlYtuY3ImTzZQnTJMW4dgPg8CxBF5pcFC0SdJY2y
hFcBXdW5NHkVdH/lSy/vp5X4YLu0GntFajrcLILzDQY5vUFrMpKK3xqf9eXu4hlaSH93uz5/3x1/
6osJYPh0EmhG1ph412IbDISz79erkjxcnPonmOqEs4lOX/Mq1OxaOSxvI4UWow10UVrigYXUGGWo
ebvpwmp3kFitamVbL3GjfwED4rD+8+IABT+kHnz93uUW80Zse8r/PJ32A8ZmqRGC+1wblNmBTZdx
UCY+r4Rf3bt+0jqtPw+fZBbRynGRyQYerMTtYWZYNvTAVh3OZ8RwkeZ/mEftpfguzPqwuy4XKOUv
1jla3BYecE5ntzI290qKpSCOgd46FB3fC0Wt1vqeYRuU6B33sHJ/Nm2ubj2xXphqE4ejQIE09yrU
6Q+duFL9reFs6r/Rj8uYN7dFh2FK7Sv6YViWCnYbhQQ4MMMK5Z+o8XELdacmgklIe9EankP1mJoT
3MdNt32GrjhJ8XtzchOFURReuHJOgSbPRUYuT4xCvSl0QecejPK8k2hP55EU3DKxz8AlGZQpsJRE
91ortYyprC2u8dp3ieI9gJA49F7lcwczl0c27wQbMpbNQY3UeQFiNZHfJZ394eM7uqVAso/YdCkG
cXHY6NMn5YJFQAfsZ51z9TNnjexAP6lyaK10pcBYI7Vj9VOhu9D2QE1WBSUa9espNoCAwW1WggFi
7PAIPmI/+BS5TljvPLDBt763FLsAPrMi0eKiB9Np8kC/8kKGOL0alO9k6XVV+z2bA5BvEd5xmZzT
XDee0mubIUsEd8+KiDsYJI3vR5PbXsoPdjtDpMCjY/ZxyXplGkcfMaMwBdhVqhwD3uVlBLyw7C1E
M3indSUHmActqQI7l6F5kEoeqBWIqFAnZqx+uxBnyAlg1GiWPv0cP9YcKkl6iegD8R6VlnEA/WNW
y7O4o2oOOUnnFSbG6WY4ZIgUQL84Aovp3MG51jViDlhDA8JfCQtMA20C3byQBoBhV2e1FXiJrnO4
SUaspwOif/yHh7FMbV4/H9bWCemrAr66n1OQ2l1tvlM6Np+I0xVo7wcQB2jyUEd4FbQ1nOoT9vyi
shzE4bhpqJYKWm4L7v8EqPmkRSJnxxg2mXfJoAI+rzsT1qc5/km56j6deZapKcq+IH1fDyNiT7uB
Rt999qEuH/LgzQv6pE07f7Zgb+AlR8TuivvOcAFnAjMKp0t3LTPDJJKQtIEk/g7SfAsgeccQOCvO
LYKFlC4jnuta9GcHGe/xPeNZ8MB/WrFykWACPfwwbrP6nY92EZAOef6+/jKRDNDUsuiyGW7SnczF
vvFI9jdRDAK+wSB32DpK+d3HENBTyPbEZt47NpTIeByqeIvDUClfqxB72mXxENa9XLOQ5YFKD1mX
+P24FPfvaw/uunDi2cen25t7MGO4LBzWbKAADC6VpOHbmZX95FaHoUTprtGjStR9MA2SV3BZZY0U
n3kv6LU/xRRQKwLCTyK03xpJ3jdE5MfuOaaz9XN3CZ5Ew2KOy6OcaM5CbXlgRailE2TgG9iZz2Hs
i4o+R2Jdkl5k3tLZ2KuX4cxpin/IYhocZ92Ppz2NsVO37BC9COVa7spQsazEEh7gmkyGSVH/YD2q
BlENaFUoKg3/Fq8M8vEu5b+Zi0C4Sy//l3wcPC1VGBrQK3sVFU5dFux6yM5UyvwdOda84chDU/jH
dRwDqrNLKgdbD5J0RXudqWZcNmJTnIi0xWBrW77WSMgN4fN1fDbm6PVIf5MIImVH+tSyKVbbxYfd
43Vg8E2tGbBB3n1vxNBOorV6jduO85IXRfl7GKRb4KOklAN0r0MkRxljALxJyMBswfwa+lbj/Vif
kj2Ax0ksQKvA+g7MQBLWnuMPPZeMl1EXF6sHddh1AmsV2+se+douGROS975QHbt2PkagvhPxRrJq
1j44ruWdPVSETdnKyU1xaFNZ01oshn7eACnk2T4jGq/GICKjIyfhglS9gRTAryubAcpoFwDmsfwO
jtiU8CLNvYIzpiHP+HeFZ784XnaDCZUjt5nQS/smB/ZshJoYo0byFvD68Nx/7olNOQRscrGLEUoe
Yq5PIYogmJhZsgBoL6EetW9U+ZPh4/X5qNb6jQGQVy0dJFdJmHivXgNua6gGXDOrUcgcVK2SPhsE
TL/HEnFZzYhbXVrt7hM4swcAHC7mHb7BKZ7I88Z1xK9WlwJDaEntMfSlmXLRgT3rE002Hn6xZ9YM
fsOA1qTic/OogYERCshYhxGPAepv/L9Mn9NCbeXK0TjJxsaAZwcb2CqLRFsYM+6ejmSGuCwMLZg5
IS7HPoFJhbJHQ+HPi0QJbx53WNFl1M/CaGDtr0+ZE9O9MGBhMo/dwg1PR2SzDIpPDRqv38/NEysc
6NSLuN9R7EdPqLnnsvo0NNIR2zGPJ1o7FLt6wJde31O5nkQv2NlgkvGZi96raYwVa6Vqi7KN4NvO
ro0VEIcWf6mglQGnxP9kieaZPTPbrpZQ+4a5UoojRUN8INxAK88aYFLQ5TAG/F7AFYT88ydjfL16
jYia16uOtzyr0JLGqVxXBIk1k5SAjFW2SBDcyA5PCCAvqcZtYlby78+JEo76ydHTJzWTOt9jnUlJ
J+Q77/PWHIY3opchBlRLjvZKdG30SM6H8IAmczxc6IOepagWcVu9YdDCrv3dE3vhwb9GZJ5WIOs+
4Y1weLkFDnOVVELVLs+B8XduVOYveGqlOEXFu6Tf0wuSHEXr+nRZ3SC2OnVvx6KLHQ9QILS28DET
CAYvZ8+jVC07/SpGevITwKvBARDR1rdgYTANOyMNnLI1cFRMjuir4w0yNeVTQenQH0C0T0RtCnbp
TD3Pr+FmIc2QS6ekP85rnXRBlXbknPHvx8Z4MMKUqSkiXvWmpwBC9+SxZTTywcVFnMEhNqNv30GA
WSbU3qZzEk30BUKMn38m5JOPOxIaU4nNGg7xccj9DtOQqMhGQZeglv7ThAXJAk5gjC1sX1SrYr1G
kWvev5L0/D1Urxp36COHCOQ/Qpof3YzUXdyHzpyD8JZ5MSWUq3UA7JNDdgRExMeoRHE8dX9MOLbA
UYn6I7kzi94t4Sl/8Mj00Ip3pBnzzN7g1x0nX/uVxqhep2nqZH5qbuKSTB8poH8bzANLo8rKLgun
UzK0hNQIa4OSqRjHPC0phIznnmIyIZnkjmhVS4s0uPptE5cYgE2+Qmrfy2eJNCIRlHtYATWnVcXB
phj4XvZZ57ifjWBvMSVHMpiexSkYIwC+VJlObncQjV98bwtxQfFvodLc6U5GInnfod2fxmMt9yag
EBm2j/InlEykzep/8q4Ak8QldOqhGvpLxkJXg576IjOTBGaqtdoNn2DgJKFBKdboOWP4E7SzVBue
4uVKVz9GJ1f3XRHjbKlxsQnOB025ZkLSLYmqIXIdbFpaFaynHMBmmvR4z0KlSbMgNeUcgbJGBp8O
xnW8RftY7mQQ5EuWLzxNe+tPB8TUggq3ZZVUIWYECRtniOy6laxgGdrUcspDCQG47LUfHJwDDgT0
fRN+XaUus3LVER40sI41S2+LY46rtdjjnp+O3lGDnBrWOOTefdrRBFSIym7ZvfBMmfsZpQ5Wdmlf
4wcQaxIh3LnFG3DBhLgCSe3Nn7bsjXPmNOPgpabBDXApfUvgcINcDU3zD7cmGDqGrYe0XjDkXdAk
acqEY8R841EWdT9n1FErI5eEKrQxSvGql1jayKofCBNZmtixgKtmoKkLn/Jss1MhbrPP8r2BsYrL
uXLF/dknKMDxtHdZ2AIbrAGDTdbcWGjDq349zWqm409eY8MwOUUWAN8+KzRXlDTrKe5MJEAQe8uX
edMpo8hM13ttOAz67V6w5L8WHNeBkRB2aB/tXQKz4CrTqo4h7hBmEkcbNqkSI7bnKAcZSr6NA1tc
EzI/xQWAAn7UZ/N7BrQCKel5i2Hf5BAVHTi6yIEc+ZlPc2NWbU0QgirtUY/MBNX5CjCaQLZsKnNB
hs0FB9XFSqEid0VoHbMVS3776BbMUL+Ahc4qX+KIo6FPiIFIfFuo1ZFh7fwGJNqAbDFVvP6U3VMy
IHQEwwy8F02QpjaIMoPNNNI9DGSbR+LSGUKleua1jwzDxiROZy1Au7wjL0J54PnqYR9iIgw6rDuA
epdtrsF0535xf7JZfuAnvRp5xMgkTXSRdd0O4iQiEpO3sDUqz3WzHuJ40QkIGXr9kVs6BJJ3Qpfb
8/yn2s9Q/T+7SackXApdbOvxWNXNw6ir/H0fGdKvdiz6bCEXhyv+HN/hzs09/Z+JkzcqjfFUUcIJ
JG0frTRl9eN7cKS+Oyro6ZhNZ5LZTwVVdzBIDv6Ld07atOHZboN6Lf5HjBXjpgn0VqSbL2DJ1CYp
+BjAacJn+ge23UMOd0HQ0cnnt6M2qcRqUBOHVtSenK6GkPSexrELu14Anrad23OK7OlbntCmQfQv
1sokIymHYPOyvV+luCsjTOVKBffB6WEyECHvEDE+EVcyYfvbJkmwCf/2X+m8Fgn5roEe5j1AwkOk
S6OTlzlc1zwWuLRgRjyngUTZqh2/4pD/hAzjMsfKszRU6H6gPEFtg9GBWHoHk36ZeDM/WUjRCCL0
ahRAy6A+um2BWYEJsBGcrnKXkXQi4iW6/RZQqdN268KpyK+mgnUaaDeBXt4wi7RuWvC5scccXNBf
jT2YEdWrTmMz2G7i787KTmHGQ97X1zjgaJeVsJVxBis+NwGNaTxHOqoyBcL07vqoh0Z0zmNIKC+V
dQIO+fpxcjaKT/bL/8JgHO8s8Y/SbKiqRnBn0RiJI0URRawiS2eVWBrj31eI5a2wiv4CHtkUg2V9
Z85sUgRf286ynBFnn1u6r8SkzLXCd48xc6JlzK2PG1ROWHmvEcgP/dhAzkbpghdp1JDhEf5iseK2
6Qv7C3km672HTYPc4mAr1QGioc4awpUChP3IppZD/DKg3ZlcMf+6okOONungg70FjZZSR4sEw3IS
RHGMjf2IzWajzuBXolc2x/f/5ooc7XBXt5NeMNhZX3ij8KtvnOqrzoPxsbehViRqe8M9OWYNCYVL
VcPURQVyQG4reJ0yltltan6rmxIpV8GROVeFr5bH+z1YoEXYVbGNGsYADBVQsfaJZIie7Td1hWMs
ijLR9lTwW4jm16Ag6l46mOzWeu8txQZD3/qE0QeABNb7MHYPf6kxdMNjgHV3I7O4v2iZAR4yQrwB
fYnN2tkx0+wOKV7d5lSg6zDNxcM2WHwa9NP9JLoTNH0G3A0PpRsagSveJOjI7hC/Gt3QPyYd6tP/
Trbk7OktCfyt2ZPueNPtFbVhw/w4I19k6hdO+EcFaFU8G97DiukRiZ67hYlVWFjhQwKn/JHXqFG8
qoJxNZwqCbgssFp0S8c2mdEgiw5pY6EEK1bG3W3UJZcjgO6Vrud8267Ogc8jj2nqrWixxxrrQCX+
EGkJYi23ZLRKkjYMLVyQhJ5mPatXjY6v0CP1sak/q6F/jSEFPs/B0bDkjcEEcinZtE+IhmMnzCmd
TyUeOb/bUaUytFwLcsId7Uefm38qKusurIGlIgDO1y4ceIn+s2+TZbDY8Ds3I5dgxK9eTF2d4CDK
+tlLRsMI5LDKHEzoC9WPw4YtRbXCFSGFV21OQchFikSRIlyuuomEhxxlJVtINf93NRN8tDiJpqN1
PlTgGJiKVr+F3bwz08V/Ps2pccjjiwK0/jZzDAlThM+F3T5qid/aQBfEqNXsW98sCVOI/9Gro+gf
mMO0PcEyUq01QwlXZBNS9LmC4jUupyBD1icagWWbs27N3OAcyAcIOJhnSm3r0StyqJC1W9+BXy2c
Ywyvx0a79BV4ucBiols4BEM36K1YH1i4Q2cowfCenBtZJH/y3faaHBM8Q7hJxQ7NGD79LkSdmpgh
VXBTiXnDRYnZe/0hku0eXB5NToZFvxVE8foPFydf2zPZWsTbyDEMrgag3e6OFBdaOhOIGTqUu1Kx
KVsceiZfh4A0Y81qfu7UsCwR5pI//mErjICO05IXB2Irs6oIw4zE+bm3nIHCTa7Nc+Nh2qt0fzyJ
reXBZORRwDzC82LFQ/3+zuUZdcXIW9pIJkyydwzdJ3sF/NEnkxrqmkx8DbwdouvtEs0aTGhvp/Ri
6YhhZiD8ucDNqzPWrmUm4n1FPFsBaX1H+W6sBZIGTAR99N+PGE7MyyUzWzCLz5zxII/mRjxNEi7c
fwVFA7G9m1TtifCIOpm0xJ8gwZWUzGlvA6XV8KNOTtUSRF+e3u/3LeUKtE5TjfMyyuxRed3Y6I5i
VeoPuLkp5Z1rVuwaJwwq++mNFbF5YBOO8r0DKUorNUdVjXKyqBGG9Vrhqcb6IrweRdAaMrRBLv8W
QB1sn5JHTjDr1hXgOHkXXuXlPaTaOVhLYNv/7MvXF7/1HhUEN+J9zfH0XikMSn3/DyFa2Qa2yuAV
A3mdixnKv+8h6hBkXiQCeuu+YpYGw4SwwRwbfnhTGge9ZQh2Dn4GwAc8okIXMLSxFhME117dqOJn
yJIEKxvqQbDegaP3N2BZTTOIfK+utNScfPZ0b9RbZ9IubgbTgylA6cuqLsMrcoGmJkosXYMOdB8C
opGOyM6UvCRfzlgCiVhDSCzTRIlc3CNJ0ofF4BUHy+FalqUD4w2G2duiwFY0PTyHGLg2lPv5xrey
b9llaCLb5x3vNlfEXgakw+pt0vInj50/dKgYDRHwEji3N4RCcqi1eoqSe3YiBq0T8y07KjVQS2RA
zpp+ymoErfLNMmVSww2a1kB+J+Vd9z6S94Dfiiz3dZ4f02m120ZbV0QT5PD2s10dWcOgezMLWntJ
2Yvlyk1t+OEejdej7PXHBj9tnA++eW0NDo7bayBjfwG+95wtQjAADx6C8ul7fEqbOPVSSJPYXiAl
xPhOJvWx6/MOhNm7bvyp16l597oVOpCTsICJ0MLmycImcZrxRlfxHC021zT5K4WQ9s/td3he0qWv
GRsJqcVls6BtSSaddn7/koEM0+PlkjgoN1pc3DV6H4VSCqdJCi4MDfv9Ds+r6hjlKGWITnqm8l06
VclQ7k4YqkeMQpago+wL9vRayRZiK68Z9V74vTk2D/F51Lc6+dvkrsiWQUWPP6qUZtnJr8awuVHo
wzX51R7n45//mcB0sruSMr+ltlhuiFp+p6U51T53tZi/J81e/KcnxwqOC3apbwIqn2DHgZmgAp2R
KcnOg3PvRx8G05LTn9eVu3mkblL7fkntcnIeCajnCoI8MPA+sL76nHPbPM3q6b/zhnlkf+UIS1R4
MpCFB4Ja1KRNLx0LMWJbuiR8MFtYECUHpWKYVMDi9gTXQ5MVvrYoty49Gnkfy4JWsiedgCDe0Hx3
3g6YuVOk/pDfgex/uqSQ3m1xuygK2YnMuRLxjDzyNDAcEzad2Q7hTuKoO3QtddqfdoIQDg0VASbw
TB7N/UTcgiAqeAv9lD0RiMojCujRz8hS558Mn57pIkbF8uu8O4UXMewtabsjrn3q2AztdNljKHhB
YgAcBPE/O5z1uf3GapzpdWvH6H2Wx6ocSAYGGxfHjKKFnY4dm6Of2tzziCmQpw6loZEYhcBtVywP
TbdnMfyKD3M9fN2HoZbU6UqH6L0uDLvH19MXOP2b/yL5EhpcmYNFGt9rAMK4UMdKKTVsuqu27lG4
AKzTybTgIdcB4KLaSVuQRNTZE4Gi8jXf/kYGyg3d+fzIUcQ1PUGSs/O33WKt8s5F2z1FL3Y04/uP
Ri11swjK3TZMjnz5KiY5SK/EzDe1OnYIkFyRDMtSJCz5vlzsNBvJavPB9gDBNqC+h2SeH+pgzdBH
qRXi8RQkZQklNGLtu7AKsGjVFGe/HdUxXPg0u2h6T5D9pQvYZD13RpISijuVy63D6SAWsfSwxVy4
YqbnbYsF0QlF1JCyS1GreoIH4Jcz98wxFFDGV5AAfZpc2oEHjmVENNVUfbL6eXFsq1s+Ch4TpcfS
zmmxLT46XYNoYfbFucdFsW1TNppXenQYn93pjRvBopaBAxsuuqcGnjhvh8Dg6z734ImolZNrmQXW
vugAkDnYccTYk7VLdJrt5WeqCiXipMb6oi09hDeGvAI5PSMqHzfsbIPrhLW5fjXVF/acOI9pdkMu
1zi7bs1s08Tel1yUO+WzsyN56l7mjfLHROMyeTjHpjOvvbevj5rzhU4FmGeppuMsdMNWYaOMyGms
AoGQezLrO0M7TbiNq2TADlmyLzI+Y+xREFz+prpPL7ABFB3qf3SBOijoXzm/oRHP3rxPc4YkDZ3M
xiVQ0vYH8lpGrJ0Yu/XChoFcWx1gJFqlEJ+UpwB+oKaXmZE20aokltDPAA2PVmq4VkkDStZviQfu
W3evWI4zbVuNWpEcHglaNPD7uf/XQUdQSqwBQbY57f7hm+/Y6fm6JNRO7Z/o214tsctNYNUFWMSI
t5U5vOvRXCP7YhVSuj22pK4NhjLDxOdoiTBPWBGQj0s4BviaLkGCXvbLXc6gh+nsrzWOZS++q+x8
OSb/koR3hzO/OyZ6bCzbsAIDagPHlJi3v+3UOL5nSY/UZrqdD6vqHMIPG2Lg96u+k/6t5qPbnLnk
nTnAnwITbRPynL4H6pQC/TClg782XaW22JL+IzRFH6XTh+HdYQEBOV76+UCzmricDO0JVfcew/5+
ItZcjChSIU2IIYKp7em7g120wjRB6zapPduZoXx7gNpAd9wzaFwbrd1eQ4UFMoD1m1NpIiVZT1YF
Yfn6UUiM68yGQlnaVLHOq95EMc3nJ2UoD0S2WEfs24ymMSE8/8jne9hiEdbEHF/SSxxSO9XrxnJW
TUbs8hLMxfHvwjXVbqmjyqWzTSFyg3pY2IHX/qckAvGudE3Qau9vv3HIYG3VQsW0m/5wAHIIWbbn
UkskK1m5Wmm4yXEnHrC3j8kk2ExMcfNSh+sNPR7NgT/NF4T6L5XKKJExAAlXOY92QtLGyaf5l/O/
Gz6uVmqPR59vlWY/f3p59I6pM9OJeMgAPUPjmru1MnvZLZXRRZRZZ0Quu3m8bNmAX24W0O1BNEEf
jQXht700iv0vLgN7Z5RvGGrVfj3ioT2pbuzU7PG/W1HuLVBIoaryujPuCyLNus+9CqDSf2CCMDrh
Ontybh8/E5CynFxqIm5jKCBVi/aLVajh3pOYXGN383gqxrTdvp2uzjjneGTSxRP38DW9nzU7FrKN
YZoXR955WHYlmyPxSzv9y8Zjtw1HqDokayuNWfxT+QpzJM3ALK4iC331OS3kOwD6T/j4NgJKgX0D
++1T1ZGg40aYtAEl635Wm3oqxzjbijLJWopUHIH8diF28eZrZ+8POzhcY4Y6zRaTSg3WULOAIeAb
blncGh3vyOsVwrZfbFx9qmK9k11gpLx+2PzQg+PPVgk3wja6+ISyhAGS19ylGT4GPLroV/qPovoQ
+93U73Ss0FEVTv6bZnhDaH1mncDjCLUNFAZHUQyNM5ecd+oK1t3RKISssSCpaeM3NSvVQqzaHM4c
z0XsDsi7GfWRsQ32Z30kLZv7oEB5HiJeqGY/GnhNSniP6B+9F5vHXpzERfqtDBCg7d3Wvt9A1ZAL
XJMk9s27uO27qDDBsoUhXeawqf5cTVC5nCj5CnR/D1Iv9IfrgXLQv+jBSUK5BLiVc9BaBmpLAsil
ZFivRnTXeB/Mut7HOqz+I78k6/NTogVwTdzGANqdgs0AsGP8daxw7+3qVRemcqaLdIcK9wCfxleX
4jaiaj895UAhdZwjNM8RIAzFctNt8CfdvXsKHIls3/bkve/3dsgOxgUN/WQZL6eGm8ejnn42TbWw
9JTUUAZTcz2aH80x09m5kvLI1+XeBosrY4S5RFQo9ZDIBR98GuvSulEkGTOXCYNgmeaydx2l6SWA
cNDzDbkI2e6YxekKNYqfjIuIerBzHOZa2s98UHdApumV1fs6ZWZcJ89O6ePSyfRixKN7iLOkAvAh
spCtonhaw8UWfnFIcmS8+sbS/2ZenJJyEMJM5e0IAXsPKc9MDyLWf0Ykb9/yGdXx7qtw0KcPqW46
365ZboOKyPfJu7kfYMlxXNsT+9fTmrftz6+hfRMLm/XxRUWlSiHZU/mWNgGeJ2dyglt5RBnj4XWp
hwNJCvz8Sn/IJMhanJkI4paQA7ylixYsxlddMI0MosSdGYqVXdBNFh20vucSdFQOhb++2PM+qfv4
lzyoNFwq8hCmQ86+83iAPsNLMyOO4dZqyHt6LCqOliaJAioGT5ZRTK8NOgxbX+qoHIUkE1fnh8c2
C08x/WExARw7e+5v9j7oirMEFjkTINP98do9sQRepIM2J6F+vudVPYg4BldEQ5MdNmbmJ2DoI5/2
KqoP1RHtMHzF/1PLSTcucFzZxqN0kpmrIYf2RlnVUPTWwnjyiMMzj5EywIUXdPZh+lDFOEXC9Pdi
FBTRffVLeLeXkBw2me0HpO99a/W4SmSjllia0aNKtzlWiZJ3MwIu8PPBBtr92DWQnjgdgBQ9nC05
/H0t5t6AmxkQDTal7KbR5Q+cub5Eor9vC5IF+wzfKltQp6NKDL5PmfKZK+VSWm+ydD0AXzSUT5JJ
kor+Tg87EUHSacqIINanCJy6Atn00074hh1ldUaCQCaIY4uJGayQE8FfmnV6Hf6p7pV6DiKeIRP3
uc+LQZ1aFB8XyGHDUPZOt1RjzCPUQcDkoRo79DZFsaRMFzScNxsOmmNPEqEkwwBPt19vgfSJ0WW5
iLMeGfol96y4MG5SsZjQJATMuvijhAlXcS1fg9NtC4pbqw7SEXJYfHyGUFsTRnVLhJxchsfv4raw
8GiwxPQ4BipJzUHIWe6n0/yIH+JnI7cfsVhNjx6vhnDTLzYs8XqsJNZLiBKuRoNj2X4WUajnbC4h
XU3PaJhyV1r1YZcCrbnrN+kGBV1BbPFR6BKqyf4sr23IkKUknr1H4Yl+TRD6h20uqCjmxpP+3ZLB
w5Qr+NIZI2lmIxVpWChlu4NPt7PgGxBqpkfz7S6m9tYy5z5qNJ8Un4k1kbR243Gp5b9KGpNYkR+N
h4SztmOck47a/7XnXhfUGQm5PtFZEFEYZKW1VwRlR0VLtYqyQVrS3Va0OwnDhpSxNtfBx6Rx554P
SnWEb65WD1bwqBO54P3/COk9Nuwo/EVj+zg5rwI92fzRXgbzu6cCy82ML766xnbBThk5ZIevf7pE
C87f+0L2cQs1qlaKMfAv7YD1KmhO3w7oak/rx5cw2DQbOLHp/KO1zCrz7bjswKUXkr8tPOY3mpJ0
gJARMNfzzaErGEnW3OCuZaKq/9cILX0UWaOBuCgpajThfz8Ul8NgamqD61jlGUfoYP8xk/aLihI3
02uaJDdHCml3SPYYG9KiMBEHgEamFfSm3we2jfy1o7jY6adG4vEmsq2r4NI6GzBIkEg5KPUadaQ5
vC3fdu0plgownnKWkbQsk8yJPxWJBzwriqGrUzgVc8sODDYHWygAXBA97jUCLkuM5W4oj92hvIwU
OMsLe2uvn7E/YqfThOtXIWo4UnX3LLUslhGej9L1p/DvmVIxmQrgZnk1dJGxz6V6IMB3IyWYwkAh
3Ewll6lD4LZOpUZJs30MwjINU5pgXKqzAAlqaWbjlSvB6Ka2iA9CM22OhIcBhvEjnbwJ6qTGzIUx
SdDUDszEVNlDtWP2q3dmr8e2vYHA4ADXyHmiu7QSEmwSqvJPPK8KXJ4D4e2YCIfRV4k5j6uG23Xc
/flrVcDe05lUomxOg3pxhvXFn0Je1ozZqj4BtNd0UOWUR/Gk/EwknlWP//4Pft1wWXb9OzGh+yvi
zJ3FHwV7yzk68K7OeK6CfO00ZXrodJ0DcXM1G/L96o2lGIZEWR7m/eDTSscmr8r0ftpGawT9D1nl
UMgBSrDX0LWwy9GaRvnQaTFD4oYVEuuvn4dT80LwYeoNr8Q5DrnVc50RA9aQkhdBpuIR2Rh1sF7o
caivqyZihLsgJ3dS7c9ehaP/PKnJZxPI9ytNf5FoJ6W0keUnTCSgvek5/+kzQT7yKJuPfDVnsniK
kbTSXCNvyiaMKLN94ijzvG9LGq79WVc9ZfBVeefxe9maEjsSN/QhivmrK85KhaMEkVcQCp0A5CNu
Io7re6swVRpzK8X7YDmbZK7g+xhQSDnEFzfxwXd9fVwgbjIwMIPaX7JPijFMaE0duqRDPygGM4mC
WPUQcKH5/uJkXMZhAS/XyBBWEYozeAieV1YYYO8h/ReNxsjoZmPKcL1AX7o9NRv3pllmYqny3Dva
oEOxit96LYPclpfwfjXrdRsOsIZWGWslJTTvkC6+Cz2D9uMJZpEKj2s+/rFXQRWIoZUtkXZ5xNtF
4cih5yr5pBxJoovQr9cAgjckiqEDQI4qPs7SLvvqfgbiJyPzYZTC5xVZVoZn9HHXDoCbo+2DegGA
owrItmcWt4CWarGloF/mz5w7ysZhTIIQBS00KN3Mw9FJnQsEpNKxsw04BDdnq3EUkeohfSPZBlWx
ooMugItVHYH9zSoECOzIgSu0O4kbcmotPuMiRBjydhuoxqQ6y/WzW/6Qh+NM5dH4gDrdjY2QZIkp
upTs9RH7rpDEdkl8EFOCVihnz3XPurB2AmSsVisURPDwPII0pNWywWi8CePScfTkBCLfJYLoJsKh
qxJ1t5O8EqC77mIrHXxu6Buq5kQMcgnfIZC2EAtEj49a1jZqbGJalJ/wLJ9pi5kH/W7lRkBNohZF
1IthqQyPBt6U2QMSjvBDZ1OP4dZFsd3j3oZ3dV14xX8N+jNfxYIi+iyhvnkFX2tQY3kYvcDw2ycU
0WxEqmLVI2Opc84vF3dzb/udABFO3yPz2q5sJJs+xNDLDavxsSITJ/LjKK5YNGXj7Z7CSGu6Sc+H
yZEjSZSIMcYQXT9Ir21/+ktf9R73IJBtPXY5zTdlcSNnxryJuPunpPW7kCc4OXzPPx7TqDhhG/Jf
QNgID0J3UxFhN/CQXJkU4XSLJiOprmZtaxI5U4We8GdDZjd8i1ykgIOzkXgv5PtjJxlEDAPka0FN
VqSGvwv29s338myoiPOjBHtI9PCt8ie5P+Rb4Wbn+TLBDGGolcqVRWFYUOTA5WjzZWJxpAFrZLsG
eC6dInVPvptVMaw6+q606XqQk4j9G7Em6oOeKxXCbrJyxl52RJzfG/I8NIvokVmco6pRz8Pifpxc
nqEcdlGFTTHlRGlFymNp8TwJlMHlhGCSVOqRXWmVfXzc2bXrpirbRhdCTDKcIXkJdjeLdyL+Q3C6
zRzdfFA8z8HS3jz7ZIJurLYJKkbuSznyW0UNchy0z4XYVlAnQpHVXi58OkuLeRCKZvzHTvKow8tZ
EAxIYf7ybKyLcxvJ/A8f5Ymc/3OLuEDjB8Jw5V66xFm6jhrOPlP0L2fr/8BtE8KK3bG9Kk+h+PmY
RJPaQgUacnREnuv/D2MaVnvjfS6zRFUdwsFR63H0/zUqW/7mEVMFtLKoYzYiYwzFUyyBl+41P0+q
+CJS6gOslH+v/gha+byMvBWRepTidA/GspjG6zqF37FfZBvL7vbonG+LARyAvX1BXt4U0QxJUWRe
49E5JyWTnTBK57JcX8AimQbDTmMJ20eDm0VSYI4tEN8b4qcwF1riwQp6aFHay4HUv5eRI60ea1d7
x1LdF95ZUG9HzGHUu/Jn4wDqnTCnJpJRFadgS8Q1oVqSUE2kj/HWtLT6odFS45GOFFZRXqUWXzVe
IyGG3aLyhEH8TZTQnD50/Mt87Rj8Src65grFwT5qmo6GEWskDqz/f3HFB10Oj3hMKVlzUS9b/GYZ
nuRu1OkYjnSAUQ0YiZafPqShux02kxJYi0DU9SPCDwKeopy5f/CyAae/eS7ZYFGtZcUEE9KVSttR
74kBRX7eqti1A+RsVoyeuNt8LJcsv2UV5bC7mmTp5v+78WdRvZVc1rPa0A0q+e23GV/L7+cYpNvn
vBMcIw7S60YfWTZXaVvBvGE8w8wfjeGoYlGnuk9q+ZSpO2Fz8y8JmUCvwI5G4e/0jNIK9mknUVgb
3XGQDW+X0pE6aGF3FFpLU4EyYPgAjJZm2GqTHs5aiYTPWbuULPkmyhxFYVOKG5trgqDcMYppXAnF
sOhWKlKpQ8QmX6/E8eEoaPfyLwkAS2seK2U770qUrvsibnLPfNmDKcR3FBlkyLunsXaSV4Kr41mT
GtO7zQRtVI/inhkHlo9POjl9Zq7P7rRqOQMvy6Rp+2Glp76ncDquWEUoKdz/zAc1tXjGJfvyyUWu
2hZXHWj7oob9TjA4lIGf4D44Ez/OQWzFz+vd2vwkEKOJwmmnvKbu9ML2OatgaBraVPtrDa3vl5xr
SdlEhP7qd6j+rwtrLDslx8JHRdokSJPjP1l2Fi6Jw1QpjrIiEQ0cMrShcWCq16HytdGnK9Kip0w1
lsnDFiDV8dEHkAM8oEqhAut+wzGFkDflGuT1nB2lJ+cUHWZC7UUYDyYKOGJZuEaDcQf9ZoCiUzxC
ajMtWVtaelXi+F7fngzIWV1TLLAUqLZAFAgWran/RbW29gyIIl2DdRY5LRE1UbD69CJJgr60Hbkd
vPu5tDvDnq2tFiNdNBMeCuTkQbXDGcckKm/ZZ2br2KvTxcVIEEPubl7JXHsQF4U09QbLC3WGH2TV
wX8Zpk+iiuLhwogLr7oB6GycqB9078l1nMEy91uBPQUjn4E9334PjcFIogVXmgfVeIu1rEFT7mj1
PnpdtfVafJpwVp/GVJ0ktXknjmn/v6wbENOK64ClfC5misKi4phmbxt09SnGmQeV5QmaXzdcb3bs
ZBQkouAxLxqMtUVZU3r58OyzAwEJOkINpRR2yE8nKM9TmMzZzUAW25X3xUAtwLXyt8jNzYeb2w+A
ggNlrdC4bMdQxg9BT8Lsd+iblp7ivn9NhEeCLqs1qpZsjbshqpov1Eq6+vu4bfxvcM/Tg/eTUIfa
qardtx7fnVRf2ZHrJYCiFoxv2SIuP10ChEwan/szzTmuvd1WsHp20kpe+TkbZYUnspJdjw8T15DZ
6VcI9p2xPzyS2v/Lq7wGpF9LhmfYklu+k8BdxQKv7aBMpL3l3pLrpUL/29fTGIjJuZ5NbAgYJEtI
Jwb7TTKyptPU8ouqmo+cCvmMsUtgrxxJon/8xx+/XwZfULeN3nnYUZmMOM+GioXCkYVS7z2L3tjh
5fzaOK5M5kGiflZS0TMD0sNf8O+RDVjaIoPeR2KoxkJ4yryz2GIhSODcB3gERgV3yMGcR6ZtQJNG
/azBGVwlMt11TZFLQk87cuqxca2MmKk9AsD3j5mG/f4UCRhH8fn8FrhrVUJw4qlERRyxAWJvVNC2
85uZq68mC/P5p1nZpzOUzpevUV7fsV6Guj22KSOkju7xe6ZjaXWxn7QLHjXRl0zD8jlvDre4xjZL
uHkwWOPapEZ8wJtwTh+0dbuA2+AVMDKOuLemu8hUwxmTke8skWRsO3cN8tsSCrKR+F3rED/CY8/i
AJxNilprZH4fqkoQ4jZCINySkWB8KtHniaA9XbTNZIVEZmIxKaDJuTKp1kJPUXQOA5BNIZv6B4+u
fu8X1s/A6i5VqLphSTbogoCto03sq7LjVo4AnodTnoqa7otS7Yba4MgEejwxVC4IuAlVmj+eVxEN
JJwIKGAFnCikzQ8HIWowQECSHX8mNdBlguZ57kk0sYPhRTFEYdG3i1CRL/Ukxy7sRYvcDFjbwx+g
WY4t7wKCvKDQqUjkaVpRlIc+XRngybaQLhfAvl00Kiv/s2OWkwrTHR6b5IogiKn1HuM/IZIIZBFf
6JcOrA7Jt/7Od4JXecChPfkfWKYYFvQ0EapMl+ZH+jVMQeh+xksyRhWnMz3f8sgilPTqrkzaG8mj
348PWYIKTeJPYsbrt+Jf9lAxdJBq+GEaWghOC3c0mSu7iWGLL+F8dbNtAQoKs3XJqWqOPVu5a1tr
x7RgdnlXZ8rERrNIsHZyoPC3AIt2TOzmK82l8qRJGReIu2L34RVX91qXq79rEd7V/cd9dyjl/DQz
FFgcSfi/38+buRNaY6CBGwS22YTLgtr1VB6kbVOTAkFaESIwdgfGpdZfkA0YEB8coqdjmnXs1y43
f67Q/JxJ4pUyU1NwRZ5MsY3gmo3iOcVknF+geRi4OMZa1adO7eOe46E2Y10cINIhLL5A94X5zUt+
fJLAp8RVASbrjFP7qPdOnAv32mpeSi5AqmYfZ15q3MXThOetNmykQL5xA47HwwxoxLi9kUCNK3of
0/99hy10sfRk2twCTU1tv8FHD/s+buWqtCStqvWbn03OKhzK5f8Hlwf8OW1+O6Q/fvNRN0C1vrmO
IxuAYlExfaSAqKnzX2dSyezzkcxQq7dsX3VCxn45Y9YWrDiCjCpPsSa9Aep8QKgKx1M5j+4Ad7R7
UZQqrN5UG/5I1qaAv21ZpN4BGDmsKLhGX9xe8YdJu1gAbnZsXS80qT78mdPlFDiRbg+P5mGRondH
gopeZb67OUYaiuMQ+4P/gZm5REXTcsS4ATINOjfb+r7VyzOZY8Pu//Q7Q3C9r3dx4+aIQOVVIqQH
BIKVuaAtqn7m+EXSNbV0M/vAxStDrmGknHX+LJLJotIVmBtCZeSSEn9pHyr84wl74DHZGbgtOyEG
Zfv3OT39CgUbjXVNYU9S4Dklr9/9eMTsEbFh0fB14SAdqlHCLofU3iCt8LanYLAdvd4Bm/a1ZSfq
uJGvOLdJwXQEFO1T4wqLdRHHHMwouq3ekK/n16E4w6/XqXVQbOMpoY1OhLLfcpCmDZvmuyGy7Rzs
9w1J9SQqlM57uGHCw18/W/PRfD/0gpnPZfRRdCsEtlAffCxU7778ghHRISDS8EICyTXQgBh7GGJI
3Kd5qOSuo24fTNSJFVI14SK5D8aX0R7WK7Hau6y8rFK0L3OwTlhIXQfyL7cTBsX3i8p5VY4BXITT
qsKbqjLippcCavDi2DGt0S9jjeq6JPIqeO6AUW3cupy0bKH8CqtTmcscn/kSwC+ArRH177UjmiQT
WbTIJwaCILO65orcCYSr92eq8yHiuHrrTH5zVrKwBmxygEmp7Of3ZcZ//2wnAUnvJa/eHeAwqWEs
gPNq4r4ybtzcIeEnrNPDq9q2H3VmQBw5Od1imUcXuHFdsPUr3ydHST2boNPgeM/xVQo54rqGggZr
K3vGm6ZiUDRN/F59cFJ//Gcrb2NcxBwI1cZbXd2Fr0uQTrcly9lYE3/RIkbGBXQdYP/AcYitoiL6
RV3euqYK8l8Tn2UNi8Et9tPyQYN5lIuW4Kg6JaQ1jKV2KjhB4Pn2Ja1Zq8yjevbyhLWkdUed70DB
BzlkRADfhNoWS8yAvnCAatVFzIa+FqAX7pIiDZcxIv5xczR3kc4yo30VuDwSyGeEqzwL566tYyrt
ygPs5M+5IbQpJedj1i2+stDCjD0n8zNHovkMJTyiJc3P0cUu6OovlSYbHtKsfHY2qJieQAoUfVuq
5eSXtoSU4satFCAJJnDUp1J+bvHfGV83J82YynEbh12J6QdOBaEmwIpLXv+K13QsjNk8FTKPOOgq
zTurGLcacpBIEKC/bP3ubbBTp7V6dB0aAle9N/sOIOuw/OU5blD/ooygScjL9iRQg2p/Qyrm5C97
9t+ADZB9Mt8lnQr7osraVRtLvxJ1aWWPjsTCJlFsg2WCSxDZOCfUb8UP68K8RoXoUUOCy+61J3ZA
spljTN9vBv7EjycSpbjaf61XzW16p95GcOBc/jzAY5zqnXScABuE5HJfcnHSXygOY8bk7C4fBZUS
m7+EU0Jv99oRSpxh5j4Fm92y5fU64e6+AK9PGtaF77Fi1blf7vMh59x4yVMyrwa1SzWUt4tBq1PT
GDaJBY/k+yQoFaH7UtUWvgfeqhgK6I5/7yicG1qBgIc2j+QzYFtwrLPdxmTz9PxI3NeRd4/0mmHT
koM0PY5xoWPePmgjkbmOZBmjSLo6ivuYROaXdMhkxXLNZPlPojnUN16+kWnco3qiKhj2MXqEuGvX
9PT4ugZo5C4LezemRQUK0iuR74eVegfFiRDfeLUbzJzzLD4VVRAF6Ugsq/SfYq4OJlKX48ggtVza
ABS5cVmefB2BXMugmTa3x8Mpj9vktjq/2b38twVqCPlk3ZAI6ZD3bHI+ga3mxx54qYfX9jwd4frt
I0NkKpVc4Zv2jEx8/9cC1dze5GvZHHWTtXNnM+7FdiFVNQ69CW6AprFIr0wvhw+lp3AP5A6N7nkP
GtyoyT3GJxN2OP5+odhldDxZP6FBdHALHTlFBTlvznEhS514PSjrM/kiHESupH+dmUb+D0pGM6Cx
ETqimvST7maRmlFeEk8SbZz2trOpcCkfbopaVANL3DxTCituCJ4D+tzuivyfWfaOdY39YudOS7mZ
snxy8u8dMonU6RwSsnQ7F99W/yrjnlsbDAbyVACw0+OcmYWkXE8RdvL3Ad1J3LhMm8EbBGXDGjQ8
yA2Cd+WvZY+KrLGcB3tdYWQhm9HrVirBSJsN2za7e5po5SIlm0gzE0+UraBHG+OzbzhmDx8RieVq
v7CKXOUHjqNqSUxilsE91Xnkcio8sJrCyGAaktHd5eimk/16utsEoT8Eq/4ULxn2qx4zofZHzw+v
I6ETANVXRMFO2H4tGWNMwG4W0GOOcqfTNpdF7Ih28ZiE4JSJ0AtFCNuuixeiPN5m6sq0tvztI4b9
8naf3G+fnLPniw+UqDmhCKYfYAl6Ro/e7nGqlldEr8LX6wvvP6E2J1ngyi6zreC7BDc4lmzOytJY
WCLaSZeYrxORfev7b20cBZLYGQq8iBEgOUrg2L9ZS3NntFHDoMbe/AH6Jv44hW24bWdDpmcgLW9L
uknEJcj59SE0aPAst0ulElXsv0m3GGtVn5f09g28XSJnVjU/+PmUc9nF4YKvNzYnO/ZrCbfLPP07
5Crg9K3RqRQ45o63i5r4/Cxkq8170vZr6/cS1SufEqs4yCa+MhLzqRrQQ1IXSSpND2j7E29dLAqZ
6Pz6Dxl5gSHqYPunfDUKVPfxLU5SkTWxqa7oXfWCPBbLwmbC6NoPTL8GkliEN+wnPxpbAX35Ok8I
xdbKhlRbN+JX4R1rl1VwnVVDcVVnMB24K29IODyU4Yub6kXcTn3zMzA4s76UJWkPf+SUbSfGsGbu
AtxyDHhBH9YwHGdxhy7Jaa78NvehsGcp/9hBBUjjLWI34I4nGguZQcWNHY3BtwS/q3reOLcfxl1u
2+JFDSwYzp5c85wgYgcvW670yFeDZGwOsPi098LtK2Fefp7M1V79spKOl96ddD7RW9wikR5aSEtW
usjue4AlayC3ZJhaWrBcnWyzWL7rOPHLiQlJStpL/GS8ip670VYR5yI4DXDUCJNpYC9s7Kg/jBT8
BcM3iKc/eZg+2u/gnrvzeCu4YppNbmzGYljc1bxXEPhDF88X876sH3vrzIxcQM7FEICj1M61cZow
fv3NpS1edaIilnlhhM5tVAzxB4ldfPBHGNAaEKpHC/g4v2+PWVF2iseuzFJtMLGxfa72k4x2U95f
uIFO8mRFV43Gk0QJiMRzgZ6TDcps+rH5BCPJF9tvDRPJQWG257QloFNsfOx6xFgW1gYWfBNsgsY0
e3iv/pLw7Uu+JTq2NSikQ/sBIjG+z0/ma9hMYwbbljNm3YQHNfb7n8mAIZIxMDCYiVuvPVt86+OI
rMN8aSRdIqc9aluf3FXCtqWD9ZyEgaX7NEM3S16YRPwNuSXJ8ph0Y456bnGrc34g830qsfg0pb1c
ysEETJbOuASY7IsqAHvor5vsTaY5U47GLASc2IawDsGpAtcpNSDLY2PQPhEH9FJCynrghMVDkgfr
BBdK1JVbHEx+8bhUpyDjcVczpidi8vxHqwF4JdrP485dG7yl50DfIREExy6OVvnHEa0XFQW2sngv
4yYfObi8sOUQ1oqs90Acj3Uy8+XHX3RhfvMMjZEMLxsENQviuqTEh5tcIC8BMNiLrQZuY93Wpwpn
7O7Ap2JZJL5abgNvZDHGcwPMpzLk4cxFY5s1rQoZtEeCnrk3G/Yl4rmT+aFYPesqH87MYeKQYOD3
uQy55HEZoBvg6831HZEKtd4964ZNn+wIEZtB6DLFk6vN3rJazGE0WTujGHI3k51KzaL5SSGhVJ4c
4d+xNwqGlnCrzvEofuD1wgU+8Ih0tLrb4tWPBQDw4GjhUFWL+3gCsZAWI2j4YKfoJf+zWe9AoZfo
wXjtihSbUx8lX1BZWg9EpRCo2d/QbeIkWQqBVQPXGxmUpuyomxsT9gwZko2qjswDu5BXHR/LW1lj
R58AP8P3+s9V/fa9Z3QgDMJYascnAV0upyv7iX3fqsqZc0P1JyTsl+ssPhQ4u84jrYRlkU0m6B7x
00zgMXUa5vEmclbamGoJ6Bv/XYmIGlHRf+ZWMWdBZdIuSIYUpucQOaelYbREljutLmPYjdEq0qW8
tLI6eI8DZvgScAHE4EZV8CfbozlP6aJqKVVbARRpJyN64rPAPw+q600qJt27A1cQl8XyGs66ocHz
Zuys8+ZvyfjQB3FU8vvFrMfwHQH8v8KltQAlWNTF1ECzMavIx4dcwD6kXRDGShmMKmaIGYYyhGL7
cxUHEouKwSQPgvwTD/gO8anW+HfczQizikJRi4+AczhKuNjnf1CY1Xe35d9AgbhKcQNM+dNi5Dbc
Zjn37geomLNBeVgvtdy+iCICli13HcOXbgeWTUhomdnYCIemXJBvJmprmWcwdtTRl7nduLFV0DcD
E5YLlPuCAtSPPn6foY4pxFmIMR+p6oJ4tIMCtE7lsmvh4xZmvpMuqyBYvE3sjAw+AF64QcOMSOwg
HLqVWQmMyP7I0YaNlemXHhlAN027eDuJnfy2/bcvi80+kwySCxBPL9lsT+v2OF7v/qHTC8dAmXAo
P+PMIE2ttr/NEDmUwuJZQeLWvEwyPtphthtRgIsPPV0nK6AVCbp/m93WPQHNSulZ/mpa2ZEQFRvb
H4ZgrBY6RIGrgIsP9mg44UCLkECN9EuGstxiF/n0eHuHH2EoJryzEdjSG8Ib2ixhWN4IKSmfIwf2
//A6xZPOiJCv4lzjPNMyxXc+0poqreN7IL1HDBHb7shYgQR9HTTKDODpXO4+rG6QwxOU4chioWQh
brQNij5mSRyesxi8KhiyBdRrU0KLI0benEafPZ5WYqc+LPZF4bR533wO7/uzdh+oJtIyhKbxBW8O
b99GHxjWhzaB6UvYMMkU4NJsTUcFaPeSqsll0qzSEB/Xvdu1Mhb750rIWlWM0uVWJW74p+D9SEyh
De8ir2p5sU/TKvTduLxPTJUhCwO5p40rTujf+XFYIVdrOQPz6y1YuOISSTVAkJppM0jDQeYnCUCl
GTp0baXZGM2ypgBU40wuzoyJB3korsS+zjc+O08pUx3cTFFBNnsvUAnANph1N+FgC8gCQBHiU1vB
Jz1hT0HaNQjFL2GtpE46Bj1qXgu2vVQaav/JmM30DW3/1IxuMEa0jTBmc0r/JEw1LhCKdg1bGzSH
a/vNvGe45zqJE0xOiwd33GwQI83BI79Gq/w66XOaxPsA/m5o7BmYHjfgoCu+58yIOxnjLKVMX1E3
QdIlLofl/JVpXxgt+uWHWbEAWKfaSsW+vroLUHwAsDa/IIxEK/XsvgfggF4Vmuisu6F0SACku0uI
XVzeRL3sUXmG/PjiMNMhH5tlla/37b3rX+j+04DdPFp01xSY2ud2FvGAQXnUpbwzt1O/xxmc73y1
wynKb6Vs2vxLGP+cLu7gOHDEEb2pfSw+mBuXzD5O2Ph3TdhMGxR27ledMHlgL5tuOi6mgeABO/KB
UVD0Y0Wlg9XJaxZjJkYlCf/SNhChy2B2mlRmIjrxErjzThJabYuvOzIWwS5NxX19o7Wg5I5DJezy
3vjfrpO4qdGds1vEAirXNZdMeadiwidqu/OOqtEmlhfCjJ1TPqsBnsQ6005drMvfg1ctJPSrQN1w
FbhkKfpCLBNESZ9DGU4Ra3XQ7wPlzBgB7VUV1ANNIAW3IW9xpD3y7jDhV36z2JkDViLOYrprqbei
gO8+NccCu6nJscGGmMgK5cp0MvQ4IBitthwaSYwOpSZqduwZQyMchZPFJDH4x3KHNOm6Y3PZQIKE
KzK3FunmhV6lATEjpZPe/Y1cwdgFW85UNGz8A98J/X3XvS47zXlNADqDjWNug4XoqhX6kuQaSCSC
JcP8sPkdke1HUdeSJC+we+sL6tfxBQVdYcZihmhVnoPbqnByHtEQMtaZ2bOY0YXbkANwCBrgyh/t
IoagwdKA7viDrRfUJ8Gc38BnvffuxZAtO1Hf9zZXkmNt+2wBnv5hEKWhDyLYwMRp3kN1y1W3zJH6
g1b9pC4q3WvA52UtBCg76FMIuKQv+mcfbZeAW3iScb7G7SKp34TY7Pjcf/1mxV0J+FhuICenM729
juVIM47+bTm6Ej4cboQceFZpXB/c8UmrCABu6YWXpi3EikIsxI+ImgjkPyqbhUrogDT/stAWOVS1
6SDeQHO8yJX3he+4WZS2mxHGdqBLIUsv2YkTDh4ugXcM+MDwDq6mz+zeIDv12Js95gHan4rhUnO9
ohf1CST5hV919u8sJ9Th4FGt6cGb6GHOrPNVe9a4w2PczVAcjmAOX2a3+lofU2QodBbKq/dwuy6y
IoE+oWEWLPh7De45wV7KLuoI8rbfC5Dr1ZJ+GFi2z5XbKnluWEtPy+Gyr85f5heQ5xIVzCHsRjsS
pe6CAmyK4h2v08FDm2TVZjt/5bfhCgQUzApWwdcyD8+DecfKSfs0soC04nVWAVdOFZKU721bmVZS
3gt8s4X3rpI+Cevr97j+fbhJqf1jzKSSxIEmKU9gZiB4O2a5n5a4u2r1xTbRoVCLF1wbg5hWso9V
H/iNkuesNISqB9nfQo78NML5GIFm+hkebVa88IFaZ4bS1iMev3UYh2OhFGWkvBB/FNHPOnStRtSa
Plmehouay/MPkxnWwPms0BFR5J5p69Zsz6vnVjY3Fea/teePvgfXPI6eilsNDPNx8ELTDUzIbReo
UyeiOuoIbPrtnBtljYdSjhD36PN4UbCbmmDApa7YzTPn9/7hhGraSapKKvPiJmbGH7aYIlw/DHA5
JPlqG3Tih7QAm8AkQ5Ug4Kdj5t7i7Oa2EnfYUTSFjOUuWcg2F1ripoTIqtCLWuznodEroIAP88J2
6jbiywqyQSw5I0PCc4mzi23FbpD3USZ5dtKGVsdDHEGO2ODMRF1J0DxPYdrWLDSBxQ4tHSrV0+xQ
6ZydLQxDe4s7HWwas/603Y1fk0v/7eicFBJCHd8KPb4I+LWAk2v7Pj8JsUSdqZUD9Ap0Xh+QlDUW
vRyFPjNOWBzsVE+wk0xvNe/hjLVJnDDl0/WfIc/ysUxCe75rEN5Yv4+s9uzgZceoLj0mB8WwjOro
s6GLJzI0AwWzv9HAOiLGisN5vCE66CkwsL/r928gBFNmvCSRpVo1PH7tpfPOGfIy5s6NlVRTIoNK
5wz4y9O8XXy2EDchiR/37/PQWviVfrtY+JaWhi3DLUnJ9KdxdSJvIpa+dh6sMj8rDvz38A3wKXUb
RC1l1YtalHhUAFWda/G2kD/D2GEoJz1YSR9sfpTJ+wDJ8ORgcVl2Ifkr+SCRrViFWoAkHqTj6jdy
D9Th2gAXV7vpYe4MRH+J+9PEveL7i9VlI1GzQsokUQZ3gTipU/j9clg4dryU4trOFzSmSETYu6XR
ApcNWZgDFp5R5QIbLkZ0vaqIRVSMZa6B1vo5IvOCnCo5y21bCAkbnvJLTKd+VtIbF1/nxesiRwWa
6UrOiR0D4giRXk4Majfnf9X4Ao0kvM+NiCX6NmiTNRBrHjZAe034ikeyMfWqo1ITcZ6h/7hgRKSi
zAs5qO6pmRlHBUEpf2dEH5M8nOx5YaV4NY5cLt5ossPnAI0UmFwsoDJp2hvzl6y3GQlDpFgxX7P+
JmkPk/KIqpDN/yii1aN4JZz5kFqRYjT5/gvuMdb8ChhQ4wRNI7WjUIsAVv6kuEFf8+wsmqo9Et38
gXEZz1Rk7rCtSyBfDEcAz32AqgeP8X1ceELDCrkMKivEVBBnh4fe1yaOrrbjzZA2YpFVd+no7B0S
HXkmIdvZKMXdzA/ISTRg0xwK3LZrkbsfNUkqCOwRz5xaopzqgs/zO/RQZ+UQaGENfwOZh2EWxzWX
9iqUMvzX6gl+OZoI69xxd/VZo/EvBPAWX4egiZb4rqjoEgDObXbgWo6b66KXer4+JvAqmIWfIslI
JnN0gmKSuuJohmOOOi0koRWa5/DbWN6u64Rs7PppRGvt5eU9wXlU8QdrRDOXsuSx3kuhJ0Wgw7TG
l1SJfFYtdxl47p/6cH2jiJq1pbx6APkV7cTzXDQGyAsjUqKhgLSg4dt49EYc9+OUCXnC45ReouNV
6Jp5Heyw1jon3Xr2fs7l6Lcr/snBvM/fvhhtyF2W0mpofb02zI8n0UAZfZWFJyuJz7seyR4s1CkR
YaRzbhAdMmL2IBi2uXZzBbNf0DHNqenOxY+JOhZ915Tsj/UFtr/TSF927x2tPh8+WrsNdkYliUFI
ot3biZrxZsyYHUU1dPHdao+c+U+G8Nz/gULmOWN5S1MmkHwVhm0jGSCZMS3WCXhOh+00sITcdKT5
8XNroCRurXNVty1lOyS+XZeevYMFASGJKOeSFQXhByBy6YJFIJUnzOrOr0VT5r88RvDgi0TTRcGG
Sxa8edzKCaPvMXGGgYVgjlXHCO0PMF0xsdhYPyIijQRwd2sZbabUDE+tfyY5i7Rf0Rk4SKN0fPOF
f+dXmTC9imnSPRe3wKYre61Af6/QKdxOuuSHVgpIZn4EYazxzNvDRY1iA2A0MXrbWG5bBwrlBjsQ
SZ+hsFMg1oLLO8lAeEM9vhz8SDfQ19mXyIywymuvwh/CNq5CMedkrmi2Ripew2RE1IGxU9KtmUbY
NR0Vh2S1qK+xwkktIyKqwFT6i8Jr93sBzuhK8jsaMcdPgC/y/6iU53M8xDkxctSfGx0RwTNiSJOR
/NYoftkIaXKp9mbOQNBZhZ7eoqp+H9jsJQ5P66+zG4vNoCi/ZY0KDJScw46jSaM/0JZ6mHgTy+Vd
o0qsWmSREECnzflsY22RB6w9LWLmN3kRMZ89jXDWSqbqV9W05IJTD7G73/j0FEKnn8VkVnEapGKK
IfKQbT8vXz0AhLJC/HIAIIJ+3mKqqdinIZpGwmRG9U+HXijTlCOrAwSkFfUZ2OB567WtHUyx4dIF
GAS5BHim8XwbfblMCZuSmszTlNEf0jNp+qiCdPFTl3H/aT6qRzEQEmd1S9tBBaloCABtFxgVL1JX
3Rul2/nbvIO/8krQBR4RIRwPEM3lqcMWG3eVW1XKx3Iy8ol+8nw0a/+RfVI7lNaiCvu6jprWARyx
AOD2TH/B/MYicwqgRMD5KlPb7U2KTWrudICy16+rtSUuFC5jcHuqCdxg7Xir/HEsBVXK0z74YVVF
XHYczY/US4usXo7qhPNFGuCFI8KApzfqjxcq8p0j2cTrIZRxMsam/Ek0H/iLyUsQLsfB72uv+n2A
W4bfK/RCtr8dj82ycUIOXBcRIpzJb1q7MTToDpJ9BxQ7BfqUJRG6vU7UUWHsqCPr4rCP6uZxm9ED
aCPLq17vhE+z1WZdwNbgTYDjh/YQm3bPuZiU1vb5l4RkoKSMSQGJmazYitTX2DL8IgOt3bbzqXjI
8OH5cmGFnqAf/tOvkJmJ6jvCYNULK3AQ/AOJzMcs4fiHrCiairoX0g5jkfIBshXqhQrYamNDRXeK
jBSsaJIgxZZRwynWtY0GGiYti0qrkqRS9EcR5IO1lKWWEpuE6eumN90GOnoSE8DyuSAM+4mtR7kU
Nd+Y46ylKODD489H01lAPCvEZg+4qE7/p0J4FcRwrs2QJMwGBUjSkgEbgwuiYFfBp+n35dUMXJWZ
tsPFTSJqFYK+4bLFYlTLlqzBP13kBa7Qu2UX9yMGabodPL/A8sgLUSYD7k0tXjBSypmIAqe+RqWG
hUC/frAznTHs/B9cnF6r6A1NVed8YtfJTVO/vaIT9IFJR8XeBXpb65ZTwuvUj/39KON8H+0rYrYI
fBhNTdfWVvaAiM/V248r4r40+Jl24g7ZGTd9HF79TOGcnnYHLXHsNxEeh/penrsk7HLLOXD46S59
46RDbHAA21J4/jhXCTOwp6URKownScwRo8jENMpPjotqbd31IG2bh2KMRgvAMpolITBKqCtzC5tz
bH6DfYn/qHlgPdPBZXzok0KRMN3ud/eVOmr8bHOTVSBFTCAOZ4Qpepf/t6wg+uqY8GbEQxe7EqlL
cw+fyv2Wa/6SCcGNqigeixbkxLB4ceow1qegMpEvf6zLyL2OOnAFJPZovVODTNFC92Yy+UtVpruN
pDHUExoyp/VG4rr3oSysGUisN3hBDvgoqZYOi6XfMh0mWWS/vWyVTo+PrDWIJLQaPPF+m4h99Hm0
3/SHNCMN7DbwTKKrCmbZ9+sA1ccn2WzCOoAl4uZLIvgWXXOzut2qGdoJSv1y27fYT63XpyLpOiqr
/WILEr6v8ziTlwdv+027iPF2Le6XtTMcQ+5DwWcBu893FA1Q0h23j7dhF0VKEVxAXsQbTDzHrKsO
WQvoYK2Srvh0rkn+52gtG2DzcZvtwSpXC4Evqu+k60A5GcoW99pX5nhBmW1kxbgytOAUIVYgbOTB
2pu03Isf4tT22v+tSgA6kn8UReSw+Nah7Bt2MbKPfqdcOGUBLdwPmeJoPehMVjpZ45bWY5TTM3vc
S6usjrEtdz6kc/1q/GfYkJWuGZC7w7HTMopGdFUMjrMZtzcauewu3DKXdLX2cW0RuCkdQZ1Y84+P
YhtWvprmpV+2+AVVjqt9lXm19yJGvVfmPcfArze5KFWE7I2zzyYiqvlZ9CiihFM0zsSyLeRQ2QRt
ivR/B6mz4ALhYNHk/MHLhTNYuTDj+ZpeO/d6SRsTPdMIX3mn3yosPnX1qiCfQXfe5dx4b0UuMim4
6i7Z0iq1mtKeXm+ABugbXsgnBZvjF9hWAW1ehL1sdMnDo3+z72gSrY44t/u9qSerQ3gTrIyacSlx
KX4tcJHB4P4VrTAPTydoHDbAcyKE5uXTIlaOce0tNAy9wDiw0PyyvEjHuZwLS3UFH27UB7ZXDJLU
RJhC6uLoeS+KVCcCm1FYd715ZH11fsc2qBIBBd5meeZhkYWXK/d4SGNQQ7xX7r3sFhA1C7DrNeYn
tlRmu8pah8GDlvsxHubG2N/kvkuDgBphte8qQbrc/suRWqcQZgqsQSS2yXwkNxRERg036K4GdwxB
xZo0Ob1OVaf8eloqWwXRloDuJphp3EKYNUN6ZlH3Oth2LRnXBNvDjhhjz5M3Wya69bIe9AAn4JI3
0yZVgto8TBcOj4V4jSbsgDKenVFRC1l3n6bNXZ9C1tTL3WoTrM/dRnw9bnqUJXArn+DxV/D7BMft
zOT/NkihM8bgndYJQSMTGrYsiJEHVY6owMr5lWc7oXNJYBhomW5G4H2xFJcFOXC53M9R6HbBfq8u
idk1DezdLFxr484tZCj0WSXSzO5EXamXB3QKUlhUtLwXHUINvVUVb5eIZbnfz0rVZdQDBYIUozrE
sZ8CXWZkIubBRrX2huaGsi+zVMpPqPKYGnvnez1pUISYVJp7xkJUgrRBLdCA2z61+uw5akxqHGGz
uMey8u3PatTOX8iVGpH1Vny4FFVZF4By0OePcWeH1Yltsgi3gp/c4AYXQfD71yVY6Ho7MldNzOj4
N1dAGj9wDquJLAfQQq+pKw7xasdChsbTlIgtbnQ75/9fMKWLLCieyTjygD8AWqJoSqft6FNmK+6j
V+oIlgKL+abSVtTTKpF3V9Y4ZHeYUVNQZokyGWr40EeHFpVIrmOtkZbFyu9f1AdlKMVWefEPZjDR
fMHrLXDoLHG5xXpCKZ4SVlrp3btAM3wYF5yw9RLRg+xIAV8hi9nk4cho+G1nOgP4UIhS3s6K2HrM
zByIqYWLZJ93rb0U2fBzSh/qEJE1xu3SUuIwAkeYrlMoa0dabkFMVQI9SGSLcXHP1LjntGSVDKEX
iPyExOEReQaP+UGhrozPe08Uzgqbmi0SkZxG4RJNHn/OTS6PvJUN9AdbecpCRGrBDlB0b/TaqmzG
cPE5MPsRiAYp98PjKCJDyuMbxP2Bq8TGEZ4/KLPamlLYGZ7jY5Hmzvj43fa3kqNBh6Ij9apOP6jw
78wHhimOFAMVCvvMkfRW3nnueWy0ffIaEk9ho9OM+6/IPPB815V+vFc1xEIDaHDTW93HkIr/Aeab
JumsDAe9w3c7t6pki9GZjDZjrhswP3VTT9Z5oqdwbWfaXOSXP8SqrG7/4WFD3zJej7X+q/mo56WD
E6+GRanpnWZbozFLnXVlYYdazz9L2/Em3vE1FkteOj8o0KZkS48cMPDXkcqAGAlGKYqAozCHDyca
CpadN4tT0qGC3UX6VanNxkPatSx0Vq+qF9M2HArBzL01PZ+649y27M96AIiFnRbSrocp/hH6KGc+
cmX75eOg74lDzFu/L/nq38i/6AE7LyvEQ2qjbu2POk/TiZ2NmCoSaXJT6loGJCuHamWeffyafpk+
hSq4FQSM7sib6W83nj5FqnBLDy2Be5B7BuGoA8ZlRZzsYb8fx8/D24NtoCAJFOZbOW/A/RSm7HRt
yFcRaqD63cRjtGi4ZXJDIIzKqO5hkLJjC9OsdhSbWfgPTH3Ilm085w+5MamX8VAdUSGM1/tF2Ghb
cg5fU+FAUfVFByPbARhRZuWsSpoRcIhXCmExV2tp8tFCbYsS9WOQN7LOC8NctmRcD9si58F4c03Z
/jz80jfBgLJ4Es2lMt9vCa2SfSfBE7fNxC+4nEUpSjbWCd8T5m9NOKvNZ1GfDjfhGQpH253sfHxj
+nVEAT2WJ0YVCWHrBNFKcc+/lClf0N5STSYQZd/NrzvAxFi8JKna0URMRul0rdywONzQLJ2NcRhE
pmEUBF6nd6eLnykHxBpE7Eib+2kZSD+p8A7U6qFc5gqku4CLAfCSF3iuElArz+YbfXFqR3TLgY8X
n6ruVKN76Z8ac9g2yP4oOD+C/8a4QLnGWLQdkWgy9gtySHTwH0g8GxTEQEDemIdCR7gG5S1BCAfH
CPS60jj8XZ8JMmHoTmv3QK5wwwDArA1n2MLVSLyZO9Z1EuSB3KvON82cfUnyZADPPhbj9pZDBX0z
3ilRQ/FoTPk8kr0QwpUPRzuHqxkITUHvXkjmJTGKiKfMmI27TI7HMCKoGV+HerRc9GwUrYm6KtY8
tiwJMvZgwH0jSILSGqA/z++fnUt0fK1STrw29Au/39RiJ3vTLD5nCrn6BMQ4vwYOCOZRQvVVD8r4
OB3uaW1b7sToXR3lwh2PhoCGvlz9Gqdi1Q78Rv8uNRNdtjApiU0TSp6nOS94RVfS5yolPQ9bXwQ8
hgKn2HZyXFubpFPw0TMtUSo4h9bMg2b0G0Ws2bVg8nwrfbpWCaoaVGJhe5OvaOSJ/CQU35D0Gp1H
IADL/rwoX3jKR3DsP+gXALC5P4vqImlHGx+DfnBB0CfXb3h/YIjgQAB8FqfUBDHDK0cuxPDjPI03
PFpPboSh9fB0+iudBROvFc6eaM4l5znShhnnyuwcBnfbi8mWPlGcVy8bDuAgtkqHOIqwRCCb6B6R
6b65E0RVYqC6l/rOl9t31YRyNcxZP0huwcX2f6HBeNaxUtXBAaulxpzwRtkF5ItAQU/P819NbLM7
zFSMgbLNTqc244/1zXehc7Kyui/8CpvGYDz0+hrE3xD97fNp5UXPxQf/ihgM7mnEABPZQzQxAG/I
cyudiYESORPkCmdtZbuvCrdvY3ah9uSWrHsdUL9VxtYv9khbEiGebZVBGpZlL+QJ//DBD+TAU1ei
pyXYIY8DyxeH1hQnJR44ci26rKPK4FWQbVtM946wUYo37dtbA1VJ4nW5zjb7pzoHUn4TpJuFBMzc
udhwPodsG/2764AI7OfVu8YlnvftOW2kk23JM7HWa5U2biDusTYm0OOqkqOAm0xCG966521hfh0u
tfJKLMG4U/znhcJT8ZB/qUqj2j2E213i8NPll08dr3jGcmu97RUgf78+CueUVH/kAGw+YTBC1XRR
Av9ofgIurUsSlHscvRSWoyRzBb2R4iBsoo34ev345GvXFqgEWpDjqdMj+mn+Y5M3u0B3OpMmZWfi
v4FrYeAmCgjzT/fyJvawV45SOCrPGOhA0UZLhetNCLnsakI+i4TEKa6dBT4kT1W5nqRPimeEfizA
8ErunXOlB5uPZjO3lrmgejAtBNfe9TPvuDUQX7ICRWN2I5rSzy13X27WN9F8QPIPJwbMIYeuWipv
ztMEucl5ZeCHEeuOUplousqBjMth9d5arnXugRuBJOM/ngIzeWxf0JxWwBxkK6CVjdtkxZD5yYM0
HEpmVoqnTv3Fo8rKFlAHmmAgv99bhzPEPcF03JouhXGG6Py/zVnF+m7cKGb0aSwdbyuv5Gp8onm+
LygxvdWMjkcMfgbmplw5vxIPV4YJhKdWYbZAH1bKk33wQH9pul4GnIlPWk4MtNjYPHtr6HlAfMco
z67B5qYmmdVKQClZb0PTaoLcUB8RlLxOzlWNT+pRwMwfJBGyrJoEtSmYZCBEOJuRQdJnvsWBz7SC
k4a536w7qnHCDhRELKRCk9dXxirakWijKuQNDtzD8K2u8XSPrYnI1fuDdkLyl+u/FAN1QZzUJvcn
vnb61klIgFS2P3IXNvP4YKFdbCL7tVze237qSpAlCSrunoHKUgWAdxVlGVhC4YEzza4bUyYIb6iE
zRLn1Yq9dUc/hpd9EgX7RhKtKMARKAi7djV1rBncBH+ZmP9m8cfSJASKvRgMGQFpBWIL1PFYN0Ur
tzysYcJqWjOIM5umUEh5phtZIs5uHMPl/I5/5QdIdZurWUaHEfwfVgs/R2wEtggY9rN92HraIgOv
EMPBH/t3qEyvnqp1FMA8Q2P57ekdWvxZ6tLSENCauw/8hx7yi4doADiV9BaIVI7V5Q8M1fM8soyd
yU6ruKvOT2Gui5mSD0Pon7ClKVpVzO4p5UyGQA10TpeLvFR89TfdotrtBlTsuTZYC8l6WhywArVV
dwvHzHJdIzjh7tU/HTl8Dn202mMgjOuKkrCHTKc4ENE4YZ+WVXBKQvyPaPRPp13fwHMn4seIc6Ty
1BoThA2R3VhiX/YFy42bJSiRfzXyE+KqexIyUvdA48ROvz3J1816hYEECLW0OZyZXYERyRXB17mq
FP4j5wzIM/42vr4EXATziO779GjGerRwWnL9xrSnMtAmnga8Pk53fDALv0YhNY6QzcfH2qG4CTzR
ZJkUZUBmyEJbaT1TfFZxwKc6JqVZEtxhtIK+a49l7uEEzN2qEZnVKs25RGiHpg3dW+2graKz4BdI
vhoTfgd4ZaxL7j3BeEKgoLeJ1pIetONpAzhLbh4aoISA+yzas1xZnkM8hNwmm5sJVoZ9FYi2J8p/
/0DtBmPK1JX2m55J0xT4RswqfJ4n7D/kbhjIuRYEMuGr8LCp3PeqF9e2bBQuroMYUhVNdXbmaguI
ZRXT96xi042xiCUORqyj41ULYqpkJfZsfzSYJhhc1UubnlsC/0c8muOJq4ML9eXQwyx5nWU7NJr2
4rvKtgEFzi2SxZlV2wOp9xDsxAOOZ2E3FYurep4JeLnf4FjDbEjnL1uQ4ncEmWzE0gqt2kXFIZrt
X1ZFgHt1Z/QlhD1r4OIjEX5IkRoXqspeYvNqm8Tz6rLtawaCoq6Ui72rPJ4tcvbfTrpt20MDwio/
H53+P6EhCTbwljeLIfyYl1D6rg8CGLOLmOETy2WkU+Hpk0e8ucAECZDbX1OrfaGBvJlaIjlBTjrW
dpDeOtdJw3TpKO8kbHnWcfi8WZ7k9K3FWEhXnlAfLuBbmAW7maJjuk/aBw6tMNC6kL5S+jnroMbP
NlDINAp2Wbr+HBpHFjY0hy5HMHy2iNExjrGhc8Avsu11VDYg8yquu0hNo6rYhFsRzitLz+0gnqFA
poMmk73zB6iL/9pawLduRiSWhaJyNHEWlN3c6fCCcqsfcHeS6tErbnbf3BlkBUPkTbboyid6CNGa
fMvb3kl3sfqFSYI+rryUvWRh6MjGDbj7M6pNaQjwY2EoRnvWX1GWzrLn5FHJsaqANkz8fKfH+x/h
+ozSaeZKPE/4zluJXtRztlWx26i1V8Z7YGHNF9RDJabU6l50PF1GpPQ/z3aVqfHmw6x8popeiCJe
RXZO5hXx8i/hX9zhpogr334GFB35TihPBf6cbwyPFTbEpVRiZezi6RknReXiXpbe4gRD6LaomZIc
p3XOuzFGLBRXaAoHm53v+hNWDTQO0b6lv4gBNWDRZAs1ed8zKfvLHY/y9yHmIpUC1kSNMeiYmJ3F
Ft5SOOqiFPCSwlvYplO9izREDNO5yMHI5nMFzgDf47WpRVtMvATOy2u1gfDRrOst7ZcDGjTc7zNl
WF1WI7UZPxts5svdy3TOfVB8Ywb/BRdUHbTMlOUHrFJc97Xwlz4FITQOC//k1LpEtRqJmIzE8rSR
mbT1MhLV2y5jh8o9frQKmN+60hDtlR1wNG1zoFSkIxH4u0bdKlV1DYIbA8ka4s2zmf02XLYfxOuz
5ijLrd6DGiv5jotzvrHFfksB4F2sE9XaJ5PmTdyCtRNAO4sjV9uZpN/dEmFitS8p0PGimsRTH5u/
6hXYglXY4h1rA+9Bw+X1/pmV5snxau4CJqFzByWvq8mM/p5p5Fmx6P+MAdCtGJWNJIR6WhqFZBj9
Q8CBL1DYF1+rvEFjJ7KKoG3Q9KZEvQf5l36UYfXkogzVVy5E5Fg4Dz+oW+Y/JmvqFhq7ZiWHMfqg
h8U7wtBA7lLEaLgx8dBa5tYUxF8i9VhIrhjgOL5YhPoQAoPI3Gj47GRLGhjx7X7PCvgnrEo18xUf
ifGspGxb4mk6KfsQrnUQcNuf/7P7mV4PrT+6AnltIJKZMJj9s/3S/hGmHo0PJ8U0GGHLBvlRJ+SZ
Jv3GoG8IkLsD4Iu9t3Kq+gueOYR6B0z7WTQmjh9aLtf5ssnWlgONlwrdnOGuGRiggf7p9COJbLvs
Kb3bG9If/e5aqWYYS7SdMwENPyXeDl3Ps/hZvA6O8ijo6t73/EeD3TBkypwfexGxj6fNWtQ3h5B+
Mz8EqcgkuxVjNX605p0qhhvQLHYvLHm4THI021Y+t1ist0ZlB9rm9TEzrxnM6d5RQAReLG0yFG7g
iGKIMVO1mzt6If9hTTJKSM6M8w+9UOLe1+aLUXD3bnXB6X0hzxOljAx6y1aoWFCWpfSAJBLN9FID
qBoSjwD/sgUzbvbuLQxErwz8wIspQLiNmvTXmzAUTgjKg5na0oOWOFo3lcrFx2Z8mOtzxEBRRO2s
yVa7drPqEUpydIr5kVU1TUgBEM1br5cnVdrHfwe3tUvXT/9KVqopwF94O1WHM1HZ7aVuoJdZvnsV
xGXGRhuAiL1YQNyqQkZeqhzh33eCDOFIGQc3yc9tyPQY5TK7Llf4y05L9IL9BNNCG16l5XYyx0Mq
5Hl3eEbq1NNtc0rJAp12rvQphvcUPCEN9lLSezi8SJ7qafEbFLnjcymgJCo2i4cgpFfPuuUHFsKG
BOq39ZYj51T9LnDDSwqcpanQYvcWUc9p4PQdsrZYGgWj9zNKLXqOeSZWQ1fvfoEwE+Ol4fPEFu4a
qbk0X2K185dqGl9VAzT5jIF9cSOUqyeGVgEr1YirM3qZoTUww5QdAYfHr6lTm1Xg8PmPgMrHYx5p
NKQ7TiI8pgHnMXqHJJAgVIAcZuFDuFSTw3DiMC+/cF4qG7uXQiqRsc5e3w1Tw0N4XmOWcq3pjE9/
AlGNdFTf3PWAld4ocfezqUmNbWW6DQyS/u13DEup6766vsdBP0D4a6Qb6yioilZeOqWIsDRPPAoW
GX/2mIpkR3BxfqrUcmkAUGIc9DPGK5zQ0EtTtNbxDnP5t1z9O5p1dy1nqF0/JBRHoPxmoKFfyuNM
ZP986K9mmFMpErko41k5YbiOOsCBlIgss9BleMJr+6Mk8b6YCXAtT0cbDD5QfkeQQrhrSUkkHILM
wSWKzcBGfKsRyu3Yxm9+rwwts0j+oIy/KzUoUKxF/de7Jz1YfvZzYBahK6VJMEm6Mj/jcW3Em2Z7
Xf11PgVY2I5hwg2V9oB8bEkxknYSsWGpJVxz/C/JWq+W9mu40dzGjSnW3frFNO6nvnF5uBzl07bF
uV8dyaFGEe+6KZGjk7gMuivjZsLSQqTsLY3m71Vy2y41ZBPrL6sk7j9kpmreyMhQv3klIz8jKOPH
MAuJmPE7U4FH8Uc8NAN0RSSTuTxdw0K2IYvEWkEYRm+4jiZ/bU0tUHn3J5b9sH1KMlIM/xhwtipt
YpoISO3GU+lKUnbvTrVPOYSSd7pbZBUZvMMX/3no1J0zBqMC5aNE6J4xOphl7afTlBoPLUg6lrFT
+GSesWDfxrPrFvRZz/BdqPSawEgfaZF+OIpf0yxjbxR7Z0f965QKvE/1GEFOP2GKvwazVlZUzyKK
YNJgsoQj4XWxCqw8Hi+tH2nZ7M+/bfdVscFEX9/NBvo2SlxyXlpONBf8CKFLtUpkd1ql23KQdGFM
qCa30frnc6jm9d/t2Y3uEkjxabnKY6KwE6DR99T4nYfGpt/zQT/pce+mwdkSbqVSXB1X04FKm+2V
9jGQexFOWHbhJL9qKCMTw6p1XKAfVeBtf1NjOt5buhr8g2QZbnmTSz1P1xBtTFTfBdhwBno1TttF
lohy918P9LFukBiCWZnpB0mysKwihnlZj/edBHNN7Jfa+hQVLg6LCziCW4lPz6401blL3cWyfe3G
p9MVZ9JXFXA7XXJTnDGTAMgfjnliOthvsGiWZFKFr2GG+Wtw6u0AYA4sDxV78fzlEKtO94LRl0Q9
nlQs1Bo4PqE+seV4PuWss7aUkizOqasyMVKdlUVDPG5DDkGsay5voWQD3ktyUC3WCA3n+a5hWS8K
eYEMA8z8/8Fx65B67Xv7I9OOlGKAQovoP+VFuL8+ak4AdPJpigNcg3NgFncrebC0+w0ZRnWGQaVe
9rhNIBVwr3CsWxj9ODith66QQnITj5sG07qayEE735i1PohftYggVmAYBDjcs8kixQIusivGNWKI
04CC4X0OKF+ubt1XpFrAXE6o0JSeFwe1wQ01jI7HxXxRECzFUHiXjsN8Kd3mdzGyxNCLoA9A6Ilk
8HvM3Oc1qR/d9ZzWCA3m49vLBWkJ+zXk8DgrAjWQBzcNuZco3+57Acdd6M6aqVt6YjmWTtUvFKFc
Uv97y3oLLPzbHmcV/piORTwXRYJ1KtYf3aV53CI0dcRzS0ZGqIvb4R8lP75naPgTAk/TgSTk/T3f
5S7Mom+z+U8gL/JH6/MJFuQcgK/Jbf2EOgP94khH3z3iiESylOx4Xekvg7gI+InjDpXEAqDSf2Fs
RPpmWxKAiuZRwQmFBBjonbW98BZ/QVGoc/IrVPtO5Ge5LarVvFm26UgQZkOwY50hivU8K4OtO9hb
Kf37cc6Xsk8SIXibrbjM8dmccIJKswoSTCcrYS1+vO1rSrmTrxvOrk4aiODuf5wH/LVuxHYfq5/Z
fQJWA+4vFuzLk6WVVc1Mb03k577Tpdr2CSzTOpIPLKR3R2EPTT2Hjx06WUD8uLoBxvds84PHG6ZH
f3csHJdAKVeRtEPIviHXFu7CL9SLuWEwYNBTY0afBxspmGKQ/XJz2Hmoq5mLzj0HT6G4e5RuyUMt
SmRKQJGCtjWLMVR33Rbckcs3dAeb3iHGYDd3O3uM4zmNIZp3fsh/ypw0NmThjVRKWsRtrDsgJeMD
Jh3U0dYMQ8e8FZlNZeUVfHs5fn8oYU5558jM2tEm4T4fCdZ02xQSUgWRgvoEFqDMKUvjqfXuf8+O
6aZXKUmMG/G/kuKUb9cQFsdekwwxACN+eXl0qHbVsMmIv4FD4zwxLOOKrO7VkFTIPqPyXdDimOzX
q++IGmyKz5vCazKk8DEu357DhR0IfLnDp2Xmfz62J3F/Vw46eiYhYuwOo+bAI570fxG10g1x/wwZ
r6tN4y50/e9BoyBPGUMA3TgqNqy41rKup0lsKzI2gdFFEqX1wKblyiWXGu/P/gPMBoUuEZ6U22q3
i+r6H5NsnKDgOKjJTs5I5x79oV6lxXzn2ijzUA1bXbt8TPoVgQmR7ItmG2ebkxznuvNqQgeWm15J
9DUghP37jPS3km8e67G8zFrFDBoXIs2knKs6a/LWYA6M7YpElt8D/DsJ6QDO6pwjNsTx3dMC23jC
YgHgbZGKtwmyV3WGay5MPBwY+agQkrP58/12pN1RD4FV9qyz+N+ZiRoRxABFUpx96x+gBojEu2Tw
ArDglfcYiwbeeE3V/XQc7Ibu65w+LttKIlSH2TddMoHXXsmveC7lQiH612V2Wx8qPtBVyruJK0RC
dtE37M+L7H7FNsi4hEMKAhx0bAibUmbcS3T8Kk2Nbm2i8lruxQlU5/d1dhWrWSx3Qz2+9glKhF2j
vdNquTnE8GxOQpaaksLrKW6Hb9WuKxvcA0+lsHxKhDBjoranMTW0s24F7LqPquGZ9+QVsvXH6/DS
9YZO6bp34l1dvfCVJPi/XHAMciK4V+w3/VCZeUq1NlQaPqjfaoVZAUYriBkl5rnS/302i+0OGOQs
Ve+p5lsj1SCTlVmgj9dp1sHwanQUv5sUey2wlH2hou55+FuXrxCABiyCLzsuxsB/ArlLbwUTxxJX
ILwz2qzqY1l32uaLzIaEyfKktKZyBaBeJ2ELjhvHtYvL0oL9afMq5LnVBhpHH1drKMkz+1E6HBx7
RAZdGJbunT+2OgPQA63QlsGwyZz7mHC5lHdzwoXdTC8zZVxdRHRLiTLqt5wgcjVBCAXf98hbtZE3
M6dVvgg36ammmVypMzLmeiOb83OgMzUZfwxsw4sTbtLe7FNH5dsVmPrpBpTnYC1qqeKIyli5kn/2
OQZnrPrtloGB7GobN78X2Pw1sdP0VzxUiqxiQjcMK1knickAMSZbRl0TuDCPp9G7L2fEvH2Jx93E
Yis/vXzou3HlmlPOLJo/+2nsExI+Z/6JPZ6Sr4i73B1YHdYU2C/NO0LH6xTSOElWMN+N3PcdUeZs
JzhFnlWla40veYUN5T7WILvYKrHR1RmpieZi2TJyxFT+AiX9pVQgblZ0wECbpY9F7oqb0TN8tQ8C
NIRhcPlnVrzylERS1TraydOTUeTQvkIyVcc2xejKYLWaAMdGoEEP0nIbN/fYOXvQ2jbMCO30brIS
AU5OZj36xwMvEI1yZI7pbRePwlod1X7MO7G4N/CAbMJBjJs+wrTITe/1RX+AoVMPRAXGrJ7NoZ6Y
mFBXhKn6s8pELSjluw0FDBJk0ko/osAlSl61+jp6Qm1GQYvbpm5b6BjQsJDYvCjJPHMSTPgsX7F3
bx8ySMTTKsyAeR6BFkFWWSkJgssWieRlkNK8Ryfblc4zI+PvuJt2Lx81VK5qtOc1I4Rs6GZ5ig6g
GGC6y4SWm9m/784HxnVfHUUoJBAYtdxphtcgldMAZ6BlWnKA0vi50+xWMzzSX3jpLjl5a1JIYsol
elfOdB8LG3nhIbi/6QiLGN3+7+t74UKPSqh8bF46hjBmd5UrUIjRnSdE632WLqgIHpxUGpkQ1QJL
1sUynHcKBNed6kQRWkjq2/pc+mQJZXtRWMUngQMpTtJeVqxP799fW+RduF9NlYPPdJg1QJXv2oj0
pABIxcALXnlB2hNWslwKuXCsPkWH4R6x54L89hUC0+bE0XXk7FXT4BeED9oP2lukUW49ijwuWSxW
nbIyPHUpJVmQC0usss3FLn/tEnj+0aauxYzoujgs3wU4xP6HIYwaWZOo9Z/rZMnbdCAcY0NApJJm
3ThqsKpI5SOiIWfNJQ1CTfTDnPIrihej/N7Gm2ZGKjuVq1f5JS5kdlZcbIv6BHD0auF+qFF2aaOa
uUxKJ0zioryk5DGsY2BXi31C4lREcAqfaVIuLN5PQlOvj9W24culGboiEV6dCuE2NpqLGzX8R/M5
4bXY/6e9yYSODORi89QZAa7gTff/uj23IGYP8tj/Lccji77EAn+5hJEW2YO5WY9Ga1qS4E+L0zb1
7L8ipBfGFuw3TjzhpR0hAbd0NAf7/oCLCXhRN0pDY2vEd18DiZkM8Y76J0ZK3KPNOH8tUf/imE0Q
TVIqr6yPYKC1wvjxSfDMOhj2P8q262VL3dFtPjrVVU0KxJZKG4C2dG/wKPS8Atq++NkEQeEvkJKn
2VZ6h9pg4Avwrn4llHUMkPn45Rq3acLspi2JVYxA4kYOADcixyrAjNGTUitD20s8Gf1TcP0syusw
OQ8nrwsfSbJVMpzkmayKA9OG8Z5jurfStelz4w+H5mDhUaGtFkOvQvGsY58UgRBGK7pX9ocWSnoJ
plqliWvinAIBumrgWJ98LU3MSjuitvnq3mgahrftZNF2+ycwLduH0j6KOd++N3Y+WQ32PSwlhxSJ
WYlipb+8B+ZkMYTY3xMdrSlR5AdeH+eu1m25JhtS0GbHGltZnvBn0UG7ary5dT591kPZ17NXeo/n
yQPUAib719pXRiruoASKVI/Wv/5QeIOvoCFPfhBQw3kFBzcJht4Am4I5D+gfMK/6kc0uLSddUvu5
/bx5qZAVHnVZMVlhVNGX2HeuPtqhd3CZSVI4v72ck8+r/oQpvu4wdKA+xDyvZ2nAmU746lL2ZXY6
YMtPtu7riqqKqPIgNhNGa3YZ61F/OokLdm8pJWPHCGHj9P8uB3QeWbPZCJKyt/zqRd7bRhqdODlL
crfVV6kLEP6D6rWZ6jcNI9soQmBUokyaQQfEEpw745+4IrnYvIGwbT5whtdvaoeg9pM3xhvMnuBi
k94xWW+D+gM98mERYDnqG1a3RFF0kabZmUQMre4lheiqfMzXQtemYBTNSxVO/1sNXJXpvXWKNzzY
xztaizvTSp6PJrjXx6uj3JTtaZkZtdiDdotLXjD6ndhRBi5V27Xa+ySN8xAUvdQ8AAWvCgnJ1z0B
wqcLhT68J91qUZsSY6oSTn/GVwgdSl+XDBUf+d6p8zIhMtw4/p8pDuPE3TuuK++1pBvUWXRaPKkB
vjk45PTP0l7GTd7+T0RFPInCIb7CY3p/5FI9iWqmeSLmI3bRgK2lF8HW+cy3HbXcQK4cGQuFg5T3
1OBD44pUFCQO9nT5CklIJJRVNCt3yXlrWy5nWHnwZx160o+k5XKT5mEPyqMwHAPtm+Z229Tup/EP
4ZtUW3Avxjq5LIdNEOJnNgfrXkkyTHHJaRgVPPnmd67rGmGhhKNbMLkbyHRNtOF1NNUS4E3VZBTh
R3WULZY63oedPIU8fycl/kDuBPlV0DM2L8YWpqINKhNX/YKMTXgm1AhSlQ8+8zn5jY3fsyYLctEn
EgHIopYItI1e306W2dECDWxX9aQA6YkQSHeklHky+8JflWOcd+Sf51aiip2GE+Nqa1tn540LRXLb
MNHlJx0hHckzTSurtc+ZT8xLcJNa34A+lqzA2wfGl7aQbx72wMQ+wRh97+SVeCoEiBIcKwIS4eh2
HJhWdXK4KONsd2dSmVtG9YWFX3UVTQDOvrZ8C87J0/hetptk2liFSFPsbmp/T1GSlNGspwFC8HAO
inW9JpKGQ+ntiWs8XbDkfGfSZnUIKABOFe7kBKr1tHQ8hQxNIFpVWVTfZV3fnIvYizLmUwd0cGL3
3H26vKAQ3/f12jzNSyEVUZp2Vw/MVbFxL+r3wUtF3UvkQW/7oPsL/UUtp/I8URQElsvkhdrMLQH+
728c97nzWcBm80xBRPNLbnxKrcPeeiYC/KjrCwznwIH8U6ZvGjDlXdV21st4bmwE+RfScx8kLZCI
bzafV4kdvWsZL/9n2YvvDVW4D1NNiEp/9aKSCD6rHvD7l0K4J9SIuFfHq3cbykWhLhPV4uGJYt8A
mumPFXyDF+j6o2R3cUfrYq7gidduCh/f7TmV2tO0/m4x+77yxg+uIEV46hChZG3UZybxK2oPXNah
rPFX1wShkNaYf5qu6M4n6iibg4+52EPRl3Af9XeY0ito8eS6FtqBu2D3lHgPc2pTE4YAxpo1D1Xq
5tGtpnh0dtISMZpwyRq4WC/ozGFIchLodcyfNIgIXPOyeYA2TQU5EMvBgmj5r4lLjwNHqI3cgrby
8H90fLJCRBieaqHz6+Cb3uCZfnAW77CHvMNoZSNm+Bc6ApuqKngZLGVmn8UOZf+5QEM+DM6N3/t/
igHyYo57gdsRETR8VBt5dFTGcNf6jbBtoMVWARUjqjBGgrmI1fpCv7iIdZUGVVevBnYIl96xFfjE
fXgrjDdFUksO0JEz1pw1Lx88Zm87vZ9w1ZkptMBhDqZzCBURVShvBC7yxCSS07XMNNz1K2YzC5vd
yTZvABq9Qm/gGdYIjwTInZ+SWlZEa2aDEbQQTlF55bR3kCcOlO5vL+m8UK0h+AJIG0cHHCQNBww6
TjJ5KwJupJh66zbOtUvDiKzUHqMLy+VzBJ+Hk8Nm8cdD74m+21kUJ2Eebmym8NyqXFP9h2muOpll
g9UVJLvbBXBeJR/T83rraVXwBIYh5p9GjqS/oFaCID9WW9mgsy/GCxx3Q2smdBZmrUnaQEzHEMDl
HQJKDDFuMrIBLEDcXLRT1ntaEKDCn+Zy6+218z6uKVXrrqYki24CvQ+aE9Dsq3P8NnrFhVnlAnQ/
Tj/+5ku0vA7dWBsaf4Uay9+mVdkbIUfdH0cnKJcC7+wykfr56GmRn94mz8H3+AicCgz2FKpLiYWk
VeflzsCVPXgBE5xvNDEde1kBAuk71MyerlhaLIDIq3bpvBmi+1e4c1gIARieYW9UDKMbhTqeHKhR
A/Z63/i926YC5uZQn5qFWYl3sXmXTVCiVGUB/PzIUwaK9bCVgiCowLsYFvyHIeNgRKvEc8+ZpavT
rTgdqbj8rCXvd+fyCB8GY8sTjDvt3Q5awbZSiIh36eDlpndMmm8FxBwIqCcc9havF3sgG9yF0fSX
R/dkfflezZ8VDgDpGuQdbfFOAJ8prwgjLHEL1g/3mbF/kCulVuliDTZF4W87IXoL9wZoAKGREWXl
JAuwA8RVnRfysO/YBauR1d8FSNtE8jVmE5u/oXqx92irz+tOPsJG9JAC0C7L3FRArDKHwblg/YmP
ksbpj8En3yiRSFOvXLHKb8ybX5wykOH7I9tnDUr7ASVKcCOdrwsLh96RVH0Y9aN2QR/kBrOuDLKk
MsqerMcqNr4cgVRcs+5fW9KZq5js5T0bPhWUoZ63J+SiJavVN22F9D7nobhg4Lpygk399td7iuFN
qy1N22UEIY4S4dJnEesoHGpzhg2U0NsJX9CRNJRp9a5i+hYDeDRBDFKujFHryoa6L/5++PWc1FwU
rbyZacsfcbzjj9v7DlDFXo3ExJA+ItrVfvAlJl2S6D68mP7066ICVLJXvUUu//OEGw7zFR4qe989
vdzjAD+Y0k7cqtYXuR9Lwmrh8BjAhQTwUa0O5cCgzTEUU2+Yq7TRxRYZALGSgc84Rj3czVNsLzzI
oM6ivnnHUNcd2UG6+BzuSvvavPHMrQH+TdCRFQfUFPiK7R/gHLZ/7gH0W7ncNGIsTwJ2H64pghwD
tQUaX3eI2hZH3n6Zcd2IqUDV4aKUHMEoFvbP/sN4z04z/Xh1pWX+we4R1fT7O2NAs8c5sht+rwKf
up3uLBpVaj2HNJTJOd6HcJl/jNO3bflPx38DbfTAATqPR5sJ17JXjgjfkJr8YTztkn3oEqvouZ7b
FWdN4KUS65367zxafy2usmBjFptXXDgDHoImwkurNASeL2KBjwRz0uV7H+HeR0y/DGVfW4vHKp31
jQxvEBha3Np49eM/X8WYhsdQPPttqQG/0suH1h6xdLcW934I3AEMxIs2tZoA9Vfvj9hp9Q4C1JJK
aWFXrGS5mmZbllt5xP9t3GKioWvZY7J7FNqrsTze/DREHdSd51ZyDt1lJlwXFUm/bkbCeH6tARyA
IDSQH/o8l/ZeB3gCA17v5D2d27whlj3g1dUn621hP2sw/PpBuV6HafzQDvh6MuPHNm9UCMhTDvbN
d715GaYBwGEeXxS+SiYKVycM0TTlcYaAZgAsL7Wm1t3upnvqSaMNFCWY3SiknYMgiSQFMW8/Bxhr
x/JOWe/LpjUeqf/UBaWX/fauZnqwapnrvNZASV5OgXiR72HAcJMkhWbQshsviVBil72M3LmWiWxa
U7CSqpvhYCParRoolrvv46PjC3G1xmCPj6y7P8LG9RS61ojDiCDjTYmwPtLZeCp8hwDb/Bi/HRnk
GP92ESoIiyg0AS2CmPUK3cDZMz0MDpMfF5Qa6IlqgTU6UDoBAKpPm7l/2pw33p7VEQHEvXLhlRl3
wO0eDAqmF2eISZk1p813aO7gmu9Dyn0im9X4hALYDH/OfFHXpEa7AskU2Alt9QMdC8R8H0rVvJD6
kMnyeWithJhUskveoEatDkIwE+73F73g0koKeibbA6lJJnr6AZiDNbKd95E8VFmtyjF41x5q9D7Q
y05XONofZ+ppdBqYnCupr4g3d8vM05+LDDf4TikL2W4StRgte5tYWZWA+YMjyvXYGtYNJFMtnqiW
SHRpIVh29QPmem+6BE/V6QQCujlg2vzwHqArOXmJIRPjYYivc60Om5VZv3litwggQnUZrGiliC9P
C+KIm4n8rHP4B5lFhLd1MSwFoCcvfRM3fCBnMsfflM0ragSfmahChDxQZx0kGT45W9za6yGHjjzg
7Qp0JktmH1S21lGpAjSVAo9uKMFImnXrZpj1C6tmWNkl2Pe3jOH9h+EMhCJRf6dApACQIFS0aOXC
l1uRgwjKCZR2oixJL49gXGI5DWiAuBvB6iYGQYQoO8xybCX7TNcY6rNLxCZK8DJpQL9Ci0Bd956G
1VawhVzbUA9f0qynH5rEHo5xDIP7eGZl9vpMKRfwEMa8t00upQ83ZBmFpWtwN90qKaKaN2Zxt7i7
SYDKBNWvoem0BMsodvQj9OtCot3iDQu+sLB9xpI3p8DJJmGIBE9ieLMHcj/2kWcoIhxxaqoCTWzS
7sCUMvgXj0NjVVIcB7tVlEmJWVGLQz13hR4utSaA3Fz/sar7XPUakO6wB3QiNtH05I/5jc9O1Mvf
LA5nTpfsd9k3T1v/ZNtJWl27gqtAqsqlwudr9NmtjlHGTCg3iUIqZj6md//uOpFAmyXqv5Nxre/I
bUf+jWxDS+iJJLtmcbsJ1sLa1FloDdc0NPO9jBGl74HNJYMtZe0jf8LPLEuirUxr1p0H8wSYGh/R
vB+C7FYb1wALWjt+6ixN5yTiN6wuQydQHJWv6Twioq9743VuFGPzxWZXpJk57izjn20+Yr0o8wJ0
mBLh6SKmuqCMjj0QgHDpzYdJWJsWwHyHyFFIaux5uxxWA7T8C3zmR0eS4nOGB/mHAwdPFEJ7xidP
nGMCEt8Wg9eRp6WdGkEcRMFin7xKU93mXD4kDL620aN/2JKAgLAPyNojCcUB6fFNX8cAVCTQQ5Qh
00s9bpzndfzrQqPWqtqtaEZu+cFyPDjo39Grxq9eGS1YcggR1U2MAQRq2VJzohMk9kEbBbNBapXo
aVqIQ0YGATK22BxhjVDjWZ9YJBeExMVCUvT3vClcHtYIwkWssyOc/H3TNh6Jbcoi9x/9SOROLi0G
2yfKAVNnJqxyCygQ+WWWZdh4rs5bPuDR54V3+zxpFv+HpqoMtxJLDLMOhu38ZBNnzInVayCwNLNR
Pl+X0+KEVQPa3Y5OoF/s2i0zZDQn3lKywq3tf2GpuINZT+aZf35qbLkq9VUjZSqYowNshat1cU12
egog1JYT9AjMjPyuQE2kQUNPP88jTmSpmPE4Q0Vcbo+UlUSM6VoGxt44ZgQJd8/c5sPkH3ivthJu
N/ixav/4EkGdyQPJmGJ5GD+0zHjH10cdSC4siVv34jD9gKBtghIjFl7+QgHgKcQk2/nDm7/7AZAm
DC/dGP3gGhD34ubb1E/AhhJREEucGHGz2I+l8Ku9qvMUPfEZZ/goP22U2qRFVMz+U7ciiHNZjh9A
/+p6u1BdbTr5Fo0AEk7TAM/ms23WrfA7L+29dtwSHHP1F59hv1+1m3jAikUeiLzcm0PBjY/RpdbI
rT6FVuJl6Q6SUu5V77ksqn3Vi11rhEmUHQnPylGMo+xx6bYQWmIIPyfeZKDzFyyR5zql4q29MARy
ydAVEtiiPFOVX6pdFecToB0gKi1IqG0qLjnx4qjgiZD8I+8FMsYY6anX5BbsuNFJG/NJKNw5ca+O
5ayaWZFOCLtnt0rYVHLh36Gj50597aDWIpj/2Qk4DsbaBFJTvOrmrHtgq6GodWswxrlgUC91Qp7i
AG/jf4b8ecfVYLBzck9+yKrB0EVMA6CbrMielSVnyrDIS2MOgIlsEFGijFEkYM2hkZ37squYgPap
mq00abXQavxPDjIUSqQr0dUm20LrBpShqFu7m0RARmQH37eMyVs9sNSeoTZHVljU+AnH6NQA3pFG
FhJHIyiNstCOfKg3bX0KD+Vi/kOTJfDe8McEVyx05iZwGWq3/BqPxww1FR3ETE6KP6PehNK13k2F
I5tG2Tcxa31+UdHvVnr6pqFl2sXxvZfh6DBPKHFFFL/3GUh5i4tAx8tdPRQhwVcESDwqjgsLVjkN
sYgLnUSAzMoR6NwzaYIZS5//qiYMNw/fzBQL34C64jHT2qTz1F3m1h4mRCu27dqj7T+TH/kqnbZc
VgNurF2LuiFzgVr9MYw3l1xCGPIu5zKVhOrhMbuF5HeNF0qXn4h+u9wlEZTobM3qQCRZp4cN4zvz
zGNTn3G/AqzdpyGocyHgzatZxcocTY+N2+sgM/Ner8xn7+B/WhrOqTkzjjLZNY4jtraE0fwesp6d
Nyo56ulhSXylEhvhhaaa2IMCJdSazX7vbQbCU1Sjwg+LtQFFEHUpgw2GaVOIM4p5y5lZq04c3xpv
lPf7gngToUzatU/D2Bn417Bli2RkUSzc+JV2zwVeJ0M3Ry4xdv2Wuoagx2/Fn//DCgrteBatWZJ+
2wYxt3Wrcv5xFkLGIX55i88oO+2TXKxgP7iezOA/39ftrfyHgn/a8E1eyVsflXr8S6/57j/t8LWf
M4ilAB839wRUtDidC1+uM9SwaLPOsPam9UoV6XaHs9a5wpEC0tlT6qX90DHzz4P4ZaVnycVEjgl6
szNRYE2S41A0kBbJ3DvQFmLXFeRB0Cs4yLsCG0MYfCcjNxUxVBBqBhinzGM0Zj5OFYceSzyXR2at
1mP33rTc5Ssv2djaNu9ZCWJWcuwKzqYZ+niNhhKYUtApTXHCtLwWSNJLiuekj2ZidOftBXkrRFFu
kPaLScOqHQgT7PjZ8InaaIFvF8nwzkJC0Glv7TdP3oSE9167Oir3sTrh6h+JtTyxvV5yFgDimwlY
1Qo/Hvs+IDA/QFlVNWlW9xRFcaz3KmmvNKMV2tfeye15E6C9Z4NSFykZb63ksgUVZ+P0L7QwRVBu
2+R3RSkt/J+WG/5Yx7bAgcYu8s5xCanGKpAfBR6jrJ1mBDgdqqvKhQq7brDFLYkYfA7lk1EvlKFg
K0wy7BsxO9XX8TmVoVh54TwFPRmAPKzRdLXAtY9yYU4P5c1shmrYvv6uF/4I878XN9mI7HND8z7s
gYP4anY5lnb4+JxRHqSjyCrnzZ1Thdaol4VYUuL+YWWLQ23X6Ywa8sj3erTkVS0glb6iSLc3oUpx
Go/ZYKtgVBuyranLEs/hCRmjUHhJTLVSOZL659aiuHrXNOJJQW7s97CfcGI2QUHVkp1V+fe8Btgk
EZs03XpCi923mjFfQNYeysBhSMVEeeZts0IuRX+NO/7P92V2aK2t2blDsdS81ImBR9EV0RK9NF7F
5f6tyQdS1etCVoM1Ru5T8vFNt07hpxMDBAuPs/CPRO/vjWQZkFn9P1ZtFCOVSudWvTGlz0MjSLZn
mgrNFywXEzd97uIfMbM3cRvPsWPA0SzJRwpKhQFD5yXJiiTSYn8tSVM9miwQKdi6NTp0x2S/3Zwb
qaFemZRC/qLfRLWQzHeIsK4JRXyjrMbQMTuEH3EKfr3HnR/1HEntjo6QXkIQhXDRQqXagcR4Hgjt
FWBJ4tKMm85ofrLP5ElZFHSw2IV5of/bfmIOVqRp6ZFwgobCFJI0cV2LH4ZbDOxCTu8fm8lDVLYV
sqYlMZZaU5oH2WblgUzbt4jNpZ8rFBoZnTjy3mGrcJgM26tYv4dNX+7cMyVJS2zL77dXRMkY5Bw7
wRGSr05gKZpTBkWPugaBIrZ9NvKishGPkFIBji7tHm3FYcwcMAN9em3yqVpfbETBXSajlFj6gpEj
CPkiRhY4xjYWjGK8Htt00NEioz63EMngg/8X2FBoNgMq19nH9H9BpozdUncSRs34Ldqe2LJBE1lO
EcjwU4F0jGoyxyyPAvkejNZLwmGDbscohR57kINEzKnNy+2TuPuK255usW3JzuYKWuMIC69C8Tmg
zrbayv7Z1tYPpbRzZ2n7JVlGFV25NEMg6LAyXvmp0NpCW/Hn0ccMe2guK33dSFWQZyj9nqGj6yqZ
Nw4oLWtxOXenIFIo1Kfwn7DSH/cO/xiDODxUI5kUcN+HRp48hXtbuhjHiEL0KCA+2v512TWRQPTo
gJeZMmSAn7P4ACdhcSnBIxcnQ6JQwepER31Gt5OkqMkFDs62rkIA5AUHlCTB3Vw74coKo+JyJ+E8
Xw4KyfnZtmuDluneXivHr7Cbc71CtPvE3WPrKI0hdHMFJqRLlX+ltcnbieEbJjOz92zi3OqM2iyi
SY5FuMQkVQlsxqoWoGNR/2lopqEj6Lw5UBfl4wDaPCSdxXmoLcOeYz+PrUAc3HvA8vvAuOzFDtuj
DL4BcKFV9VH5KFJcojTbYucRCQ4dl+Qq7ZjoAiFYajGJf/+j3E24QwR10sSNTZ7I+zo86AJA5cpx
zQKHleKgp7WEwdfaDlW+l/7Va41HU1zffvaGRFoxDaHaVVgZlgDbfPWpQoapwwzt9ANhxiEKKLC/
GGrzkqEKgg8EnyiRsVD7G8BGGsT3ts8k+aYzEe0oyzx0NJWiDbbg/FeE6nJy7qHpNHjOT/U7SGxu
3jfhJZr22Q+wYS9e0JwYrVWCGBFdvlHuK+H8TcyyudKEXtPkf8N2NdGMshulIILpETxWlyVgGyaP
j6n3FJhVinc+OwVDYzVYUOVkjJtViFNxJ4AiWIz+wXZrBZ347uYDRfuUiDBegTeM5N8eLKKv0tf4
6NoCkSPhcalHyoU+qRwtlW+wQZWEqhD8EDANoRTMf1y2Fr+TGM/Jdh0gB5P3lrP3GdMBOVz5vv4M
noWSdN9t8oj/i/sRvzOBnK017GNGOu/84BWLycGNZfESJ8lhiEofgGXmKIocj2w+fxD/1WqAIa0I
iNh/nv45qyN4cJMAgPBJlVNIYyvtd4TnGBFlQYcYiyjRJUP+/Erp+vRIT9P6pmbfvCVEZjSqHUA4
dIeM9kyioVsQgtzXpXJOimoPKGxYalhxUu7m47cV8/Zy5dcneMi9fN1vJmZ7/BOzEMfxw/DQcGFk
ijL/Q1l40ZaYS4OHipIpFVGsWRimDbyG3b5xhtx1ajqfKnzJvV4PfKI+/fp6GpEEXAF72g27FZkb
ygYAEapZNhl3PvhtGrMUw/kyg9S51ZCEiQI+vSUlGUOI2F8otTS5+LS7jaNZuxjvCb5sfn88NGq1
0ioFpYZh5N4BUvXDOetgjzFu79G13m6+YcR5WpkqECcb9EVV1KhNUDtyKrhPosgi/oD2bvc6rWOB
YxcSE4dDqKXSaklcDP6S/aDQrTk4c4xiAIXi2YqR0y4JMcQMSSZiwie1ZK3jszyV/kDzvb+HKKMC
7ekVOvYhxsjLkTraMoIBDdSlhECh1Q5i8kDffCj7uRk6ptg1YhyUs/gYvfZdn2+v1GpZXyyYGmHN
ct3j1NICrAudOoLCLBB6x5MriDlYgMuGhzUS6DjTlIVIFUGQ8s9SD7ecJCOOzhLEMAHtjes9+txb
ZUEP3Ng+Wj4OxIjKAl3NqXdYgyyKLsjX/kWFFE0AbN3wEdMvQdEv9JTldSzlQujd26l/nzyo1R5u
j1TGMwCcJOl3bF/jiV22/CLQpMI+dqOmgo3o5aNFIkN6TIeXZi+0LlwsiFSllW04GF8akQLZ31Zq
yE9X84qTj19QhwMiblkRF7tHlXPiMYGSQaBDbYZM05id1Kh9WtDAezkcx/GA/EmR7JLyvrzwLHaB
HTk4txB72SfMlYqkol0nJYu8F2pre/2ZZ9Oe6PCrQctspV+TvDkiOkNOIGL9qPnUhLRyUcxdfjLG
SkJ3Tluc7TtnzyiGx7Yj5XOPK08kB/EJ3N7fwSvywHlUwzP4ciUyCkZBDo+F68J9mzCyBZ2fZE5m
pONfg8Xew3RxHYYnmoYp8bTpFlzrAtObfD9/v1UjfSsGcU7e+ySL9lOuy9SCz/DeY7WxyB0F4UAQ
M6OQCTpNeDJhEGSPQ1CNZME1xOu5izaKbbtnjcKjCsu1HDw/9bNrtkXD0dPa7Dq+VPHaMg+G5bOr
OH+yS/dlPnqYWlnHmfw/ah+qZRVw27oXNnhZiIt6OwAgNTP9nm+7PfbY/xjHiXWiPBjNRcs9Z44Q
tDyvlaK7FVAUpjjSMowq+87T6u50v6VrUHzhcNNZFlIlkK3Q3QNCJLOlOeXVqgrZxbHUH1fhk02j
Cp0q8sZbonPl7U+DoUnadRgfzorGCqaGO/LdPlc62vRSkUX03kNvO/0XZb17eBf3540ubBTQc6Qf
AsQ5HZTnqYjhjuIdqu+mmduveytnV8PpuOLRVJxht245ZWzIfwBNRdw9TGIR07oEUQhdQ2ltvq8T
/q4ALMqHua+PzJvUR23UpggCOldsYQuywob2LxJb+XjVPFXGAr0KfxBdU7CIu5Ql6fbYVrNedMCj
6IN+B4tVH6nwtay3czmrv55hXt+U8Y2wSKigKHwZujSKbhQHXdtPauUoKZJ0GJAcC4RuU4rysess
/NwzICLgScgQhf83jVqKCSBbedbnaRYHtTfGwy32lS2m6g3Ek8NzFN6mcvVHokxD1vNqSLgEKWYM
HEkA7hwr9k+bhJz9r2F0exTIYwAaqOtd2qXmZ98vLwY0q0LDJPow3ZIwF+ZgTUatqEMXRo/E2Gmk
OuSl+3/wyvz6yumGaeU/zrNl6QdqrESXonGhs7sbSW+5ADciqk152kSj/4R7NX/Vs54I8h296Gzi
muA058cIPn1pU8UVmQ8nWVnksluPuYh4fCoUlq/HeAtc9Ae1mjpciEh4X+RWtcw7C6iGFwT8NOm8
RrWcLf0s1dFlvQbcKsyFwsikzdPEvNzEpOYasnSSxkPRIK+p0q2eU8w1RfegnJ9xvPJKleyGwEfv
64Hg1Q2ETYOW5r8ignL7U4MuM5QUaTUWkoCvH101VS8vN0tOY7lrpVl8JIcRLLq5JzNcx+riC7I9
DdaZ6ZccCO5+r8QXQbUM4JGqAAi27Y5CW67xLNwJDoIXOUMHuntGLr0dd82MDyQjNs1hdKujIkVU
BmRnftMtlMRnKrSntTrMAxkbczfCRLuQMtv7ycW2g6EKR1kw2D8SNK98XScjBfKXirRobqvHVzmg
2C5h9vzKlnWYUF4KAiiZPheeu34Q104fl5frHqHCDeZphmvQ5Qk8Viezf6BS2/L2DXKIA6xG5Tyt
IjqfYcRD7lF7cd7uyA1gYJzGyIm2q6n2HaqylSVg4VD8F8iduk7ddJpHtYIEtphQclW4f6/pxKT1
Hdt/ch+1HA225VCN9LjjEQk7VuFEk4hlPU9JUyQ4MBEqnFBEkFm+HfE12G5RP7fP+3eIvGqhX128
Uzbso8xlso8dtYhAympLTzaF+VoRKS3K4su1ndzxlPOtqmXz+14d1M4PWVZddDCD4GidpK4/br0j
J/fUyUzFvUKLdIgZ0JRhSdMcuq+nXOSbKUNUTjBf7KP+bfpp9r/a314/klmwIUrkav3wRWZGuvbw
0KPIiM79Hyojt0uHvOBPS+f4UKj4BmIGMrjMxWqhDoPYFxtNvXVobOMWkLrAl9Uyyx72jb++NaOb
OestKXz6lR6IdnejBc4ZppxCEjcMEtc4tQalYXcZ9O7LRBxxV3qTxYgs9oXFFpm8VrQuNd7+cyPq
9iWVug4Eo73s92xDN//Qzs5piPEPf9aIVFqieGWbj4F9/duWciEIktLdRq9FR6VTuUtlI3xxOeWW
2N3dfgFdhRfXH6T1hDkh8qP8hgWFQ1CdNWYd6s5gUTGxpIMLejEAzA8ZH63/FKq9MaNOFZ1P185q
RQO7jrbMUlIejdfJrDt+piQCi1GHY+T/+abiFda2PkE4oxcqmtbopZAxZSejlhBCcVVIndZtss8W
8CogBbF5f6rYNm8j7DO5XPQ6Oo6ZuVrcm99rI7nW5SOztqkXC8Gnvuvmn2ysoSEVA9HotEBwgBMY
67FM3pmk+6terNRJR/h8B1KrAwPanYoF4oh/vIxqB+cjZJhO8Xlh9bPYIjf7NwCGBR+V2nzSxQ+S
07kv/VZOAoIGoYNuzCsBaki9L7s9dVa6x8cylEKexpMmleTvOzpx+DjTTaJW5tQCKL9K9nqg7L9a
MMDTsjVpGmPykZeR4sDRCbu3ygM3UBAy0Tyfp9XrdlZzVEv6IL+kRqExPm/mG0vbhTu5XlRJpxWZ
KlV3n0YUd/s4J8JcocxRFclQHdUlA7zEXFggnZYxX956PulPnPUXI/PoE4POG+QoZmEuJIlrhTDQ
cD00kVmT5HVQ/UVys5QwW5lkKqoi8mO8Dq7Ucfi8hhLNM7//TTr3n9iSXogQrooWwXVc7BmGizpu
Vr1C6zeHoSSohtaVMCTirClr+UFyFta8QJiCJutbcM4LLAO6ATE6gCz67X++mDFnYviZzKnqs4lS
xLxLW34Gaa57JSpifjjB+gVY/q2WmN5AqO6za7Ky5O1D9pjxkfiKA13LFAl1XF1LHkmMoh6WPJ8j
mrwv5tAqu4M/oQE+eRX2n9JcUwJJ3f0/gDqNbu+yYARUWkrykecVDGJPgpUU5vEsbxbzjQQZYi/e
BsKmxRrdTa2iDlqJFWPAVFGHTYXsZNMi5EXeScFlTkC8ONos8H7Vm8LKj62107O8Mjy+zQ6Fun2x
BrBELufe//yBTIS37gJDw/Jtxznuo1LyJZrNxWMK4alSUPQoflAGf1NQ2q5xBkn4WCAhqyWwCWvD
ITvOE/bLh1audRxlZ4gGMMj7O8rjKVCtj4dSwXoWbkomCVoQVcBt0g20BkUQUWaInRuNeBjoA/Tc
2h3W7bkvQFVi0Qju3fJnV0DqcikgJZvsAR4qqJQe44cDBl8uT9QWmZSj/R1higAPcX7lsIH0XRN7
Scgp1xcT9E11uus7Mrxflq1MwJ2WompG6KE1zroOl+AAK3OirpUN7Be61thOkQ7LWQzx7VvK1tqA
NP961d3bUnXzqi/1vrt8c8Rl887Lx387AIRHcH6X5ENlvZd2Gl5JBWWzM1tyOtTCh7v/ah0bxenb
Ptr1Y1NwGwpyelJI90hxGPzUb9bK9DLyBe0jTua3YjO7CFnlLcjLrbXvqwBMrjSkivspUHEx8YyV
hVs5bb2syktkwPRoB0hFrXr4Z9QJbqNbts5AseW1e+b6aZAnAuI6iCQDuzyuUZNAY2k0xfNXTfRT
Tg73/MqthD5DMp0AKWmQYVRENW3JvYUtu5yYYFiFaNp7+x8MlqACkHrom62Zl02w/qvi0nU1bkvx
DoLGmp7dMcdmZFnaXLN8kFNwaYRiyKobUfzOMz8yDAU0nBsfKIzRkkM5UI63QOcpYrR7dmIIXJRp
0OmplG0hj9hxpIEHPy1sfOZ/Qdl/3x0INCU1kU+t/9CTXeQOlWrsBkqrGsAmuyjmdpRiMK2GfGrA
Hqd3S3+5lvRdI1JQt58uVHHcdvvM4mLKYSgfAz7BXzAARpNefPUVsnBbdqN+gsOGxI5sVoBnV0uc
Z0lAEBI/wKmTzuvxs59YbZIp0pfaxQ7qqHjsfwjoTL2O0RTJHKx6fvV2GQ8gzChLa7RMiWQDCdO8
xLx+r6/ud4iOO1J0Uci+3MZ+V/TPsorFBvaBFwItQggK0cwLoA9mTBrwBDHqLdmplfLuci6kWivX
jf2Br2naqMFEN6cngVV9ZcFHxRt6GI6GpVJsfhRKD45M+8lIZDIrcSCaNX/mvEe1SwSe4qi5KIBS
/GviAQ6tFZ+yFFFfsYexRZeTgZY+Q08D0pQEGHsVxF51x9XI7Z55O6LcJm68bd1iPRQlQGM8xqfm
d69WXfIn01Z1YpF9RDTraQ51Q8FYxEXd3M2scLTacwixF4px5HIitJl0YC8pngmp66rVgxgiGsvP
PUfBOaIUo7BT8a0FeIYBFy2OqiQ1cE6XgaoOOpEqhDls3zZCIRffMOucGeNL4ayJVqLvU1BM/JNK
YXwH2KFUVeBUNS1UNlScpwSeENISf4nJW+Pgvnu8/RCfKWuQs9QoZ7Z6gnNbChp3GbM8IQgumxj7
YbbQzzhjEox0DUrtT03rmWoNr7U13QiltQCY9uoUzWkZ53GNSBo03T+0p2DmtyNGyC/j7bE/wP3j
9hxs7lOpKxfiGHOYE59BG1GXj4OKSPcRoI0YdNcOzgpUzRfL81oxCDPYb/ce8xRWWC+yc0Ony6Jr
pr+pGUP1hk4pxIoBwN0s6bQNlFjCNTAMDinG4bkosZGQKidwzd65651jTsy8dKIEUXD0J1lOPdb/
uRV1+RIQDyyb2t8rmYv89Cpv2NHnQ5mnkj5Bjz/fhz9tXZ4/I5g1ZMjtgaqdVTTNvdibiD/YUGux
chQZK4gM/CQnYfmkgtZvN2QmLnCKP1Glm9y7ptNnkuJIHKdiIFuk0mTkN11PXVR5Cno4Pvum2a+9
eU7pFShb/m1N0tAfvaWz0fb5Y6/jsGMOu0z7LgorX3tOj1tiLKRqrwXw8C+MVeFc7D2SuQrkDKc0
7O9+iV+wfmhSbRv317KpnNbCJxaF0xMgzmfl37i3RSGs9JXbukXKLwtg2DHMGRVmgsZIPHxNUK5d
YiUqMaUFHAjiS/Sr2l1wNAVd1Z4d1B24dzjmZS8mf27MGJMfAxgHBu0T0NrM2fOudwH++JkKt4Ea
dqpYfA85eRYlKuejU3q8YTUB+FGpa+3SV73FHlTZ7VUqQgWykaC6lNbACu+QP2y8b12QvJj69hk8
Yfjoy1TftF4cyQ/BMS1ioF2kBIHqAoZ/++WlvEkVHFLGvLV6R+LFqWhL9i6gA/2PF3Egs8at0uwV
Gff+2FhCUQmTtKl4zUe2H9Mjqnwg4cErM4vP8SlwKZJ2NNij7mU8XuYc9Y7riNGgITht3wEguZs4
gj4Soo0fbrGsgbjHe+Hd2cm7nBBH3xvqI0Yck0ujDHppx/Ti+8z/DA/vIXWbo21KfY66YIrC0Cd8
85PKQ/BySWXKqAS+97hSj2hhuCDzoywEbigBOkuEciDZaWj6rBhAXDINDunCqORO2AIBKcbDsDlc
ooyqiRmZMUkP928p+cCAWaml12cctXLIS7Xh6ynAbfRzhPDm1rP52b/WgoM9bRolIX0lMm6W1o9i
Vw/G0CxJ3UCqJIlmQ8J5i3Qpfib8BG+MwYdRckjQj4XC/oVexwqMM+w/nxZ9YQUccpCItD/gISE1
08Endvo9MXwLSBRa0PqybsOql0lvnaMrpge9ruW0usKxVSNJ72BNDMfgfMt3sjDmEEGyfqyypi1Q
Jt1PUIGtV4o7HyLzsJHGzTB2XXtQ7LOhsrMezjyMepbhjsCtFJ0uncNElI+fHHHlYFtbv8b93wMU
ljQJIvQ2gjariv8TIsPR1ClY4oHre9aK8xsMrhEPhnyOLUHQzAAoyXOFQmvPhrX+NECZO+XRVuxv
tfz09U2sDA5tVmIaaJb6P5wigizr1W8vlNYLXRLoDA32qG8jV58NtwE1Kp6opPugwTOJJq5oYwVl
SQG6dnIqWyx9Xm5Xca/Ke7KCSlLXQ7XlP4r+fjQM4jpQqA5k1UrOomqMaWs7uRaWfhoLfB4D+db5
+5bpRzmQxv9PjSvRxc64JRF1il0x9Z9IKyqJMB4WEtukA3WPVmSXvsl4hgCkS00/rH6kZPpWJPpE
lxLHc3Tvcp6bF8dc/8IPQghum1B3F/lUSk+mm8+62ogz1zGjuDp8/oujhE1eAveF3EnVzXO4N3xm
BwkHiAxzTEbr7rduPXS4DyEiR8yy3ox2vUT1/ZSjxvpH7N0Z4UpwNmbFQ198+D1qKMTjfLAGXyzy
st6UM3w1N5fwRPl4SMkaOkoInsN8Bd/3tS7aYv+9u4QPg4GBH6YuJLk65+1+FFvSRTcP/PbGX9ad
TNqNSQGs1djqQaXIXdVbUoTPLLJ2qGktrJ9emSkLw2YxtGMecBoQUPRVRN4kz0QXppCiXyMj+wUr
nLXGYJT5D/oTmeqw5KYbTwx02KQRDj/ZuZCdZy6eFBn5Xs4P1Lc2OMhAugIeNSxtzCBh6xWngzvQ
sdXl1NKQspJzUWDO7ylsQQrUtcPkmm7Kp4btD1jOjN74qyiQzvUZlzHkm/IEXxG4pT6Ttd6BXhXu
YVn3k0CtHOG3Ss5dysaic33L1JMWNIjCqL4EtY7OtFtNmItrg7dOdUfQhhUTXFhQn5V4XHMBmb2N
6QqTAmGsMZAYJF02pu0hyvF3vwweqXBfpSmPGkxhRr6lcvZpQw/uUVXdIMSmkOOVyW+aWKktAKb5
CK13nVxx1EvHVeYsM9vV7uPu+r2orDMhrmxPIkJupiY34vphC/k+3v/cGRx+0vzQ6CK6htva+gwc
utX6L3d0HtbIHQ+nG3DzP84HbT1gGkpcfne+3kvKqYS3PdSRUhBlKZrCPJgqQ8OiYDW6Bk1w1n4G
0+UIgMqrJ6izcfDj+/y+p9WpqUeLoTeAsHIwJRnEJCBeVMD6fX1SKopy0YZiILzHqW80/ncx164O
nowzXRMr6ZpC9/n7pclXEbTjHpxtUKbu1POlR1N5ikAcRr+7ADTGy4bxIjSQgpg54yjnQVM90Epz
mQrlewf8lkM7SSuVZveBZKr9tReyl+nLE3xWT++A7mQcRcbyt9o1eRygMyvLkUT4VC+IXIEDJ9j6
IPNIRuuSYcqKO5ojREAECwIb4U4YQSEnf2aXQw99iRxWq+0b2q7buTf0ojPbK4LC4AZAyTsI45M1
ApLtPaI23P0N7N09bGAumHPnXTIXw3NE03V8GnMmJlYIEVNUxgx6aT0DwyQvn2agx8Ejfq0Tq3qT
b/gF7LqUd6cs81SwGwUqb+LDyzwc0MbIZMOBGakK5wemcb1BYqXPfuTsOg2ORox7ptzuzF9+yvSl
PUe8if+x6y0hWgtNGaperQp52AlcCGjNpVOS2XbOqF4s064vwvtfsyHJk+8cBUwGkxRTevelmjQA
rlQA+URxbjRaM38GxxLIQByGijGhDg4WFUDhgzvS/mwj8AuS+G2cUCVVQiDAl0EXFjsJMV7sPbGE
3kXrC68wCKdQAK2XSp3bqMDY3V1b28VqaGUcpTDsvJy/1a9QQSKym3smj5FyorhH4ZCuqgTqq0nt
BPxUy6hWXH8/jT7EOgxGIiOKdTBtkK0Yn7QAuG1ZsK/+IXvhQOZrkLzugBLsVCkD+nmU+TJ/EdKK
NIC2tx9SCNEMxL+hL9YmeGCbwOyb6w3v6I78ZCIKnqLx+XJgk5vAPTp+IY0kEzdw/PdTjWsGRWA0
DEN+vmJGasLRiA+x9akxw02GnKY9rIGVWytEkePVhCIB/SFLP1EHOtH1xw/nkvKMqqdbLpZZ/Idm
uk9zBRwSr0WpulcdMHia0dzOk+IPRpOujTx8Ma25C2TnOemwsXsKr/yHIZU3skWlYYIOOPQKCY2w
C197tLL//BL0CNeGnMQsEfrnrpF1gIEIEt4bFexRuudW6ppsDB3WOzbTSxG0Wo62h5mAUCrJKy9m
SwhJkN/DzspdndlrFI/Nb60eF3LUieWc45M0Qcll/3jcE2BzhNwDEqEHUuqUhv0So4+DSYACcuAd
Yie8nW1oesvUa0Eo+AXX0DlmugiE6icQyVdJjlRbozlFK8w5uxA2OPNjVlwYL9we9DHNvOccv+ly
25e+UwXEUppcsSpQ1zLQHx5ujcRl8xqlAdOcXN2aoeZk/ejDyRzeS0hYL8J29ker/HLuj/ZlPL5z
T0jOGMebMLOgM3vEQoT6TwRwPYOuh4WYx4YNxCmOfezXt0M5oxeTfH1wJL7Ulppv1i5R+zClbr3p
hlQlOKvW/Ny/B5CWwHbst5p2Ik248FEtpHPtlI9+vcqVeWJHovgkUbfWf5VjClFFfNp986yCqEgG
CgOzFb0UlxXd7mGV3d+Kq0QvtRlPNWDlLIgN3cAqO4B8R/zOgr/pOnbcWq5Oe/qRMl7NDvXVckQD
WOStLNlVBCnyx5Hrrafnpj9had3MBSAStZwbF4nTCuHQTP+mHbXuotFk5hd6QQ9zi7D9JyDGfYd/
rrUkoj9Jzu2PB5h2Mb6/pcR8amkbTfcpeLu7uAuHS89+AzhBmHD7CIzYVWanjStsp7rs+FT0PSph
5ZeOAYspTWudSvzz4LF3oORATQDZCgtZgVV3DsU2u89cAPr51GayDrkDyuN9TDW7Id9sGyvh/A66
ovVWqBE+R99d6Yzzuvz5egb9mTMBk7vKeE3D3BlSfC6BgN1QG4jEmIfTTA8XjgJI2jlxcBmuWYLH
SAdrJG9idJLRSyLTH4Evzv+XnGGH1biTLjK/3YKJkPycjH3bSIQY8RLrhaqJqXLR3ok/DzV7n5zW
fCCFulz606euSXsZpsNlnsKjNHhJXjQL+F6PxwjV/F81peFVbSS/q4MVPzcWADTe0OdYb1XZnDn5
LPkJ5kHCVBp+5AknSJ9B8PofPuDo+EZHhFXT5SBXW8hVsIQ9uBT9MbJH3DheEdj+KtyrhjI/67kq
cjf/EOMoPhHcnH1fUYc4vEeQym+96XnQ4obZ3uBqaza25CvBa0aZzkDL9wTFfhJyl/xOn2KfE8iI
AnNiyNnV8OAYrMhBfPxE0KcbeTNVcoUOf6WaB8okyuRIJX1ySedCGRk9J243CD2t4p3q64d/R0dM
1ZaPKMzKTfbyaNUMVwpTwA25hTSWeQk5qNQo46lfEQ8M0fDosxcb1o/5rXi/5uT0jAddhAgpRARt
jHQxz8iQ2GIFdDHHMGNddRjqZqkjtjYKCcri2aMQ3UTz4MYkH+rgndqfcdxi7K8yB15UTgiC06Pf
Wtx26Zrmol6+jX2v4ijT8m+smVMo1jN1sZtz2JHYBNWAubwSC3/qxW8neRX48tHWp8PUWY0La44G
SBNXVymni5Rm3Ss6LpRLz63B+1I96sYf0eK6ZwqZnUN9qOagV9dgnTaHSGMxtOg0lP4NfrJ4AvVB
GruFYrHcP/ErUZ5p+pjWudT7npt2po+ItnLEvmxVwnHSNuo2zNO6bJNgUtfAQt8Mn8ukx3oeODj/
l6GH6bhT94BO050I+VGnbz0yTTn9w+8ydIbq64pR4kll6wKHs9S5I+PEc/MpzrxlmnX7a6jMmOvT
Y/l3f60HPrmJ4woLqUed3SkTzSieVsRd9PYj7IBzSYz+r6vO1BHuEXJcBhzMFC3b4i1vy3cnJJzK
lVCRDPtiDXpxh8IGbRTJEpT6JvCir9amRUtZPl171+PzAvWrXZ53wo/BHA9Bj+IznGkS3NbYXtoq
UBdmFNhQbhkt9FC1QmRoMzywv/Yt1m24EEyOlHCCQDBkIrwHGG451t5388YswqSVNmDPbt0UXyl8
3dO+YgsDndKeOKfHOrKUZHITU4v9TeUbI1af+pQH+LmgTgTWbcFZj4s/gm8MsZ/ng8RucUj9lEDH
LkROjCLdFTQA5nT2sAv5TaudJvlt+TUPeP8NgSyGOS2Sy4UOXh+qm/6UwkBeI7ySMJseb6iYPrmy
pJ6Ts7MUTC6c5KzDfQXcvPqv4xWIgbZqMJOxokVP9rLIEcU3960+ua1LZlHK84gkDnS7EL5ZE2oH
8BNC8WMtnxQ4pYUYNyqrDjxj32tpj/lKkY1dPx07YvgG6cYD0svkl4j98nuud7HSKh4YTiO5oqQa
JOREDAWNTWY98pGqc+i59fce+9TeEI7dldVOgGdYx6+SJSKhmQ32qTpki9bse5e71pR2eBqLc1ZL
wTJYF8YgI7VuSAmoC5p0mi0QyLidgrX2zk4/vPzQbNgDboa8c411NrRmIQCarnl1vxNQRRPDVsh2
2Tey4psoRtszWzkXbie3GvL2PLrGuH5zeAuhIV0eNmuRwJvccZMYkFmhpMPT5ovLAfu7mLWF4D96
rrt/be8SwnD1/2vXIUXslc7ufq1W9x+csf92ZCmhyJbZDwIVNUiJ4HWoR3LAlcZzL12fEvRvYKas
iZhx//SmXWVA3M+56jvQvNZLnc7lSxHv1fjtVmZmW9WNFxdfTPnN+YO4njKAwLnf1Zrw/Sisylaz
o9LWdcYYTGLNBpXb53J2JLOVYF6uw+kUhG2ebMSsvHwvxZYChqcE5+pEiFLDlkKBkrVIsWB9bRFG
vgp0NQHoX50EJnqXypRPeojpcgf/Tj8nP92ksvsRxIg40RfH9Zk2Jz2Cy+LaWDHN2PRHDsM+Ts8W
woVOZ+F0KCBpHZv/Vzy77NtdudM0pEVlQ0NmM8OF3eQGKUMvgQXyKMyWbC7uj1vjMKdLH+Q8SBxy
SziFleZcpV/Asf8nPWFJtt9ux49+3b31pe1Iz0kZfxQiyjsm/alSWnETLU5W0WS2rA0dV6IukDq4
IH32v60dl0aBq8gNTKrnvBjqKjqKU1BIlsIYnD85pdhrDKqREr0QBSFReeC4VZfqVIyFG7hIp/77
JEVJHdf3ZVsF6c1gSSAy05a0bkIOFv0nUqNzG+PXjZP83h3bEsFrfcK1ywcZDmt985eegl5PL/Ie
tfN1/ZolHVpBnlFS4TQfxPqceFZNl7SUFMGzIsgBEWP6nG+/A3KM+urALcOfyAjpjRFPx5oUsKVi
p4zcFBIfX99ZV+Ai/HTlJ7x8NQfu6W6/2eT2WyU5jdrkzqZA2nlU8EQ4G0pjp4S9RQGGBy4Xe1/K
yULs6bhnMIoXCeeBudFl5N9CWKrSRbiluxmUI+9N4UfBF8yG0LCwsdm+dAssOWjrPTITj6pirVGa
j6+5U376nb6ullR3IXTXFaBHuW9NaCGAwznHWJEjpx/E1oVrpsKP0q0UgoYX18Yj01kQtyQd5JU0
Aju5RubZ5uYw392MrI5h3gw9ADQgOpYbNGMRy8BBS8MpUc4b2+bcGDAXHdHon1KANYe9oWiDFBLf
QYKq1CPLjspsvfG0aKvBmd284dO6tUOuPjyeE3u2pm8tczH5yZuPYnUm9utQKwt5Fa+DHIPh98Pr
9wj8XnCdEl9dIQ7tdSQW8QKM3/GeZULDsk6gTlYc2UySjRYTh2Z9JssqOHgwJeQVsMogWBSzMn5f
U8yjz3EpkI/QUR09GYUJm7XrojMFXvt+ESuonhqB94jHrg8QUgK3DOcDAEytPeM7dPNeyC8gUyCL
6JtMw+gnuA4OUOJMkTafsdWRoi0t+Eh9f9pV8Zp/PAOACZJYFZhrO85FfaXRs0VOgkKoU/SI4v6S
ZqJ9xOyVsJY8d57iPlHmQwAq94oYL46bjeTXmZAGSf87M8TQRvGsyMce1siT5icHRSwNym6rpMyL
T6lm5wXcqbSHxrIcy1CuTwqYhxPiQKX0uVZWkZVCmF+vrUhraRdFwJeiYMKRbj0rYd74zHPIierx
B0uvRyZUeAqtjWiG2QmhYHzebc8gtbqeM8cqVMfoo/BB5TPioKGDYUbBACz3+3TkmDi5BeMhaXRR
aB/vpZQmZGjDswNMwS+DgCDVnmikVRE0xygMtd6plOGezO8yxDm6NUi5tHvcC2wTMV7De4K4EMOb
ymlANHNS5uf5wG6dbWP3SaGAWt49ksIB9hyfEMOeartA/m4VYm5Us7ZQ3ip93OD970Cfla3IYC7E
gPvmPDqj8PmsNsnfYkTjr2Df0sp1Sn9b/5WcppCC3K1seJ9WU5db2Ejxfs/IV5qKYqwXcWrycKir
Q/KtR6QLbZz+5c2ZhDVqEjRJKUOwUj3xG30UywLKkWEr3U3HhEHUjAnokpTCeAmyd4scDJCTDgKv
9QZ/Aa5WXzCJzTM61FzHnTgIJTKK6n4ZwNdCV74x8B1y9y+Gq/Jee1SeAla/MpzpaWu57eAz3+me
XdJ/GiDAxeXnVheQiPri9Ro0SNMO3upKHu7+zQssFm3MOW3OmqXGPNfAUOUL+MQMgT2g0Q2fJpqc
UWZdIo1QqBKjNenfZBdTlYj8UzjN+EUc+GVStfh7Z2e/hLDk1GafA10RyEe/XOv7TVj1qg2CPZ5N
Bg4V+72Rvm0QRIyTp/Fc+noxdB6WKXReupDLCFNln+93ic3wpPd4EiyEn085yBVrAKaSaSBDqfbT
SjhsAldbemi59iiYBqSOO6EJPmTztVNMIZsLJwV4ysfVmpnb2vhrQMwOf/LbFmIAgwwWTWnAc6JV
wkfrRMBSYRWwxmb2mpGW7yNFdTDNCOzhJYZwimx7r1SPTWRfKPva/+I5P+IXLwNhhlwTeoz/LZOH
1xzBozo7HFf2SNdvHkxCYXN5OQnlCp5LJ/KiZGm7CpCSspo/38yEK2pIpti83x++fZthMKlqhTOd
eVjHq89XrRY8TDeq/i01O2FszFF4w0odEb+b3zVjat2yhnMebryRf8xK+D8L3wCh8KwHjwK+CUgy
2JRPudlR17qofMu2/v5C8+9RlxOu/8fVQtVChZikoy3UslJhMt7A7vvPfx1DR+wCCBhNS/l/Vwbf
g35w1kXfd9uRHz4OD93c5tTigu//77SeBlMN2EmLWIlzhlz9mOvAlLZ2QzXj7iw3Y1HlK3gdJPO5
SfvE6XXwpJp5NrF7dogeTcKNiiOMCTeG5YIL10sQjUL5PGpSpfiPMoimBjgJfLmegbNc45zlEvIS
t+4LzQ97DJpizqNr7bF1zcbXpqxoH9F/OOGwE1pvmnDv53IIJG1rbt87UlIAqkvISlKntrV2bc7N
IUgXERPMDyLda5Q5pA961sA5xZqteVqnNKJ99Bu4aYipvhy9jKTkLPW3RAMGS/6QhjbeTdcawj5t
PVlFzKuMTLVDPIxFVfIres6Pk+B6JLv4OgnFIsZZpDA2DEt83JWindUC1eqDfK8hDU74gL9Yb1h9
4pOa7FD5ZnG1gMVvUqXAzn6KDfrcI/kB8rP9oUb8SqTj/64w7m1FS8xX3kvlsrXliV6cPuiku6m8
9yk1Tw/iHD3sO8UX6anPQ4K/nIQItIquYK0Cr3QxxP6wx9Kw90QMCChzu6XXSi6kXCw0iQHOWt+S
qB64cWhtAH4R7D8MS7Unm0MQELz0Oj7tZZcLVU5G0veEuQszlmfw6UCoYVSGhQMM+XYaVPT91bd9
UcsPpmbP3HrFxzNQrmb4xXVlml9vOALNvItXFRPJY2Th2OX0xC7pRgBsSfbBMIjxXB28kEmx1S3j
O+vYfMnujFYG/yUjIo5YPzpcvRRwulNrJ7fP1DahPSVLcWHB5fbYJRZw98qPajglWhMYBVknOoPv
2uEbWDmvn0YPvUOJkfyu9Dfb8L7H6U9VTKEt7uQqX8as2xVZa0W36rwkjSXHEPwb6nIow42+VK4y
VxfYmJqXAoKg6G4rer8gRgs3fxmGixVVZZphSBt88qlQs2skdZl7gTRhWblNfndr5mutHzxOK+Gi
u8hyLw3iRFh4H8GWKTeGdS9ZeVrl5fLmKdkt8fLhmvklJKlG9ZcR4Olaj08NiIuSzBcAfyFo+0L9
0LmZ4htWQ675amg/x1OFu/tSeZlR5rpYAX6ThyAZ8HicLIgtztdgiBwhH/ycXv8XDFS2epWns93i
iC8eW/1otNxxOM4Qu0QeScbVFylxGA9TrGmbkLKzALWkCOUPZ81Ui8hMroIUXzpwHidPOS3M8jx1
P0d7aYa06ag5OtZR8vweaCwjVOjdgfX1OCpq2fLV2XumUNMzDiT5If6CxIyfVbyx0uSTs2EuVXDt
gA3+ViZwB/oTcoCUsmvxE1d3Ltp6D2IPveQvRpx3N16JBfIeZRsg0E/7nwBrU+zDeXe4bUGi5CQi
JpXwIYhEi1AbZMfj7E8/RnSz4cWEQXpHOn2XDxEVcbzQG2XWNg61yJubgpUektmbql984Xm0lCB0
TqRSjc3qINk0rRxLIYGtHwG+wIjID8s6Tdl6MCTXp2njfdJZXvVXmxQ/BWnKpF5jYzxU4CiNHrLD
77PIuNN8Sw0wj/FZraIgdNlmFiunAwBWSb+wD2N0Ou5BBr9vvF/s8hgcI4ZhclQQP70aSEw5wgSo
8xG9/q1UQJmi1mbJ7m0ZIdTuV8JgKhVMuAJyHR020LOnbqoGtqkIYdzoDWmdBtb0CNn9x5AFM9s2
iu+a4y/8TaM/whNOgbl1qxUKgDtcQUUlQ4GpxcCHaqtxHqcmdA2GMFgHjaMJtDTEm6rD3xDZsIg/
oi3CE+3Uwj7vsLopIrb75Wq3yrgDDbcDVJYaos39xgexik8rojrT/IfXwA9sB5e0o0ZKJS6J3F3/
4+9nN4+gR8uyooMldR/L+Fyw77HCnyAraFUcoKMiJ8KxY240XuNg2Qct5Q9k66Y5al/O1PR6GCrV
eVqg/aW3cUgF9ffzy7kiik7we566sf4Smxc9arSZYG1A378idih9cJz0JSFS+N0rwgQuU8d2L7qS
Ag7NmkL2k5g+OYXeTpjLTX7pGs98H0R50JYs131PHCA8wyRk8YDGq55YfFdcfYJAHfV2q7ST+smI
dgRIHHFkWhy8OYv5nltZoUbrQj8INdX8a3BpONkqUD9KpgK7Aa78U4lyV2dQ9tU6I1QtC+jrGZw9
dzVIqadcynm+R2ERG+5Hk0sZOeFiWOd50sqJp6bAr9z1HyL3dnTGQbAwNeuFn/n0mGFBJMf8Ex78
8e1LUk48bTL/MuhkMPSakIJ7a0ofLe7yoeITpghyTIrlXsvfQ2/dVaN4dmgcdocMZC8gyKCJiERb
DerVT3qNzo3D1ISxlF0cgnkvDVkRix1fDolJcp81uadJlCznM+3xAcMc75DUljCBUDbL2U0P31ug
g6MVwbBOaEGGhBJAJzm2hgZgnVSbKsebH371nxRiE9UeDBQ9xwDMK9XfRSxrvD96QJIOcrQaqNt2
6qASM0HKut3mYwy+Ut9KaxvuhSt/k14rFtRyG5pjoRQ1uFtp/yKps5JliQlvvbS9gqssY7oz1S3Y
wGfOrjpy/6q6pknIZ4lUB7pub3ECqElE/wMWZk+huDm5EzqCevQWtpnjqr2N1TMv5L9TlXfLeCZY
24Jz8AqwkKtGVyzS3mBECsTe8QIgJ7n8hcDMtowjEaKGHg388dTCL0ZkU0DY6jHsDlDaiZdPl3L5
2sB/7D6AvLgOP/+RRG59EqXmMI+ROBvLn70ifLcRV8tjESOe61UCkhM+lFuNhef8ek09KI26cWNg
QbtvhS/JjVzgVx8DxsJPmlk0L+0tTUZLfP1lw2jkjBYNspHMA3RdUz79Jsyg+6KumuTs/DcJAEqr
TZQZfsDg2zpAzlHl4tF87imuWSvPe0mTDVUC4NIlhRbL6dw6fmQ3Ymc4g2uuD74ihoLjcjPI+7YI
A/Idvh4RF9D7sx2ElpSRm3pp/YjiFsdM76GzAz4VMbh52ZTT34WqcaNHo/K3iEIU/uTwYIAPyjuG
3/Au/JtH4W6RiTlDUzSQj/FlmO2xQfu2abDX6t9qHi7x81Bjae6GbKTdlEbGslMqA4/Ta7Gx/e0o
8bpjyBOawmb9pSXYVrXbrGrjlq5lpiy4jbWZZfDHQ0Fv82xI+c3Hno+KiOFlYJuPmZfmI91Yyudv
8qdCtUQKlFLQJPIQUj6AtrLgifQ/hRKhjjl3Y/+m6amx8EsY3KhWjwptFxCDFQnsoodp76MtrMz6
DhxkBFlriBg46qC0iBF53/c1Q2BXMIFPFbqxVXW3FXPnQjDTbZoX+Ks7Yd7NKId+I1bb7jED38u+
pc5VTedq+ctcwXLGMiZZ+TwKdpDjQI4pLXSJUpm377zvkLoxAuEeQTQ/7tlmjBbyYpQMqUHhMBFo
onS2O6P3WDTrx4wJ03yzMnvNlyeh+QFMMK4ANB3Cl/v5yVv/VMTfhNcn5t/pFX9u5JlIBUch4FaH
4kB2pnX/9bw9qSUX7x3lpGpa2OXlalhUnGwZ/skgiaJul2kXgYZDrwAuKZqbsk3n3V0w9R1EENCI
oqFM/C6c19wQta4vzUPMmznvapwDFyL3KYwg54cD+yC3ltsxPwerD4JY9cIiK/rBiZ0HCM1u3HgH
THUnDavY7mTrLUfZk+zC2wgUMNZBIhB0JxBoqlTxht8hZROxHkxZCeuFaPpjphDxF2YnRlzBsLQa
IyJAInFfd9yQRDWvIZfEkBxJW4PU/Ic+KVRKi/oc9/azrXQR5NoU5dW5jTVjLvlXY9kG/KcN6dZl
Zy1bma+xto2a/7BllwTT5y/Nj+OO+zF1QoNAOzYrnqyFXyNvOytdoeU+0lVoQvF6bjZG9B+KDwRP
sadkBH59Z6yIRr//j5YFRViJlPJfF5BkHv47VskA8ryEgwiBBp3hZSv3jwzfvy1+CWlYmrNirF8b
iwya41vtdXgiGxGD0LX0eJ5U6YEH1jGMKI2O3oQ2hNigCRoNV0Va4EfeK8cbf/TvQMz3KVGzvm5F
sUoVoSV3Nku6ilZImTUB7n8hRzk/Lv5MyTE3RI9loa4XSOiqUA09rmo1gfXBoE11/vQQ/wadQWAs
LZ31R8+GnvmGhME13MiD40ICHh1bGnJ9A8Q8OKItR1NWDyt51muEWG4xgPWnZXSqJd3FmFLJohiS
Bpqo5IqES6p9/G/WskuVvGc9p06ialuV12mqkKdknefU9Kdf0Os0LjhATTbaDYdjZ30oQniESZqx
eyycGhqmjVWFP5p2HAtgMRhC9RVl9L2zdRqEX+srllOwecHUrYDFySOFS8hCjzQGMtHetz4ngevx
dp1WQKAMMg92Fxi2SEPwmLcckFEnhKMXkaakJD/OJRD2nHyPwnCLZa4kd+Dj1MfPnpL9iNu29w7d
94z6KbU/H0zINPoWD3DMsuDe1PNs0QzPziDBuyHtr+Tr4fCpgcyHWONFEif4Nbadc7p2kN4JKUx3
Vi7aLTx2hKOr9UDw2ScOxz4fZb7eHKiRcrk1cC+jKbdpCnFtiBU4hLR5qnBtuECsanR6F1QBKWMM
uABRKW+0OH+vz6Mk4LnZ+s6jPMmktiuXYy2tznCwSCexDyonsmwRm6F8UUnVniezzPFN8WyIJeL4
QAz0+iNRJZzk3qIYmKF+4OfonniMrtRr/1qTUaIoNgjHen33JppX5iyWpI5qyQtqyswZDa2YK/Na
Dje7qqYgMUDyWyjV5T9TU0V3jseOyBLt8+Vq77i9WLG7r6NycyuYsx6E8pPWnjLuuOYZVCnN6LmY
BRR/8W1gr9zvbNrKJgcUQmgUNjy6jmWzkc4AOedMMfegg+Jr7ZsYZzCQyK2birryUoBQBqHafiei
bbMDZNrsBaKTg0x+xbP8RFh4IeFYBLMmcXVBdHEKZAvNtIOY5sL6iXhhHMewhd3pNv7vruFIw+ia
uTZmwEn8iuZHNWvjxw+ZUZm7WQWSmHDKrHudua6IrEZtmYSv/ROVYT/IMyD+DhMEcea3smgaWZEk
yBqoqdizAoNND5uxt022qte7Oy8I7AiWCFx1mpdrthyo8fLtXpYvvPG3+zBgLIfAsDTky0NRnVBk
bdrOF/k6GwtmemLMlGJafTGr80BrPYewTrNXK/fx9C2UqAv2nGJHMkuLXIzoUA8pPgvN+FZeu/tm
zcbmb4yJPwZMBESqNTuYRHVzTgbmYJKFw55U9V6loHNSKtCPWyPi4L6meUmoaLm9SOL6S+91hLUS
8WtWR25uJDZHYORTDtzT6g5VvNAo3W9EBTDBNFBkyvLlipfP7On9fe523168+nf5Y3J4oOZkduWq
VovfT6I8YzX5jYgPxn7iOFCGXiEOe96rWUW2keRzSCthztH0bX386KB4Nj9ZTVJzgUeyoLmdQP5m
SZBIe8RhTaGUyM+At0PI3P+SmZDxZJgtagLHzRGHkleuNwhoWxWkkrpm1CO7qJlH265LJzIUs2ov
0EDySj23JA3kdSVSyfzmNTAlSvE0UqVo931+UKaoCzrzfo/Oz2BHWzGNLlsmgWxPeHn/greIS6iy
VwOIoBmcS1vC4VJ0CizMjy58nhO+yI8/aN2PmbKHJhVlEG5+8t3KeWpihYjfdhaCN0T5gnUY0NP3
teEP68yDr12I3wXG1AN8/6YWNi6ZZb+6BOEVqwfw30szBAIFqW4QcnhkiYx3D3qpfqBaUzQu04Ef
vqQ/Ci3HJ0YjQ5Z3yJJ7oiWO5Ivuh/Vdpr0LatVz2ZXEi05X1iR+zIqrnp6IwgioSfLmr1bempKy
JOtZDLGkpsPBcFti67SBv/79IHm+/a7xHKdWFrlOyQ5vGeOxfRVMwyOWyI8yq7vVOMzZTSR2ZceR
5Ci3565b+cFR6XJzwKVSPSF0s2Gn5ERZH3HfcPC75grsuZjXL1en9aNngjrMq3BMD/pkzetmrZoz
6mGpyRBagPKMt4+xu1YhvYMhekoRzm9WvHN2t1uWQ015toICHDtI/6OHpNaoeShOjnZBnlE8Vya+
cDeQWYLwYmjLW0l2idfir3Btj47DP1/dKZfWdo1tlvzA2NEbIQE9drU0rq3VlrtQh2e0ffvkzPFd
BqXpMVNBiLJpRjXnY2jM3/J9+D45xYSD018NiUz2LoKmqRUO1YPDlFdkE1NFBqh1Ksvz+LI/7rhS
Wc7RMkg4llje/GQw6iIAp8CA0+sa351ecWtCC5bNFmha+1qtmC+D99AWOKWieRbryj0TLMB7scBs
/6xZP3TE/A4z8qRHtq4ynmDR+bQ1LODcdk3tiM4qSRPz4rr/yugvef5yEjmSKiLa325hNFnaLzni
zJG8jgvSHJrX1CFGz3KlrDV4LpoU9H0IYcVVzmwNIxy8BxFMX1+1td//9vzKVqMcXenfIEeiJNcg
j5dcE/yC+9517JxUnhwYXzb3u4wFENxx0RnfLltOemXycwdD+FR7CRQEc3YEnG/WIFHRCqjNq7Bs
Ujql0dyLViCfiYvVP+HzTIpoDGWdzaNoRooRUFWpjW5EiEZa0VJwvxActxGk8AlZz0B0hClXq/P1
oCMu2v5wrqUElXhxoU80e+1grb5jgdXwsRv9PuqCGV1HLhuN8QtthbyFjl884P/R+vHKKmBYrM/i
ff83K1cOOZzvB55Kl2cvhwNVcM3Ran4C4ccJ+qLwGVN2cYvvp/sSWi/XQd9WPHLqwtLZZ7WlUprz
uadtGndnSWdYaSlUb0hph5/Cm4HlhB8aacYRRuf2ZPIrTkrI4KSw1O4VnkvMcJucCRldUqNglCoq
qBuZRhrem11n/RPAdej2V+qLe/s1k/7htrlh0JhkxzC7YwM+BkqkXaQz/2HL9r15ss00hluEGFs8
9/27tzjeuEYWTRaI1UmvfEP5xYRM7mILYJ+ZSv2guM9DIjicXYVJs6LiVvscsYs8MaD73+LH6vHq
ozb+HrxD3pW0fgGCY599mRrnXQYpMhQjQUKPdRw6rsbiAj4igiTdAQC0J3g8LcNVJnGQAny06+6G
/KbORnVKcvJxZU9xqapL7JP76jMfPwt05iLEqZipFBXGV2Z3CpSQiYX9XnlbEgZKe48gD8OTHz5b
miihGHCgsUuFmBZ4b3rg4wgCrkCf+c/eJIIMwVLhDHSlnK5MR41h+SJSzkjRUyr81vGPH837RZ0X
iLELM7BgViwybMmw7O/WDk7OmhHZ/037kIXarhBos/Dq60gAhYQGSdY7TNPKf0zEOxqMJRgSiPod
tEDFAZQYMZXVJJQSRVDL1Se5HdOIn7D+Fke2ipJQXbnyldQYpNvqPLRSVc5FQgvfAkBERDuI/4VU
rrk2X+qc+YbyLuaMJR2K3FC3fcYmDXeNNuYeOnuV0U0X4pEPfyXPmJiOIA7KwHfYcfPUxzjMoHCh
nefDz29gCVMkATdYaWPl7K/a36xYaP2+Uzp1eqCecqDmmt2A6Ak42rcz5a7lzWOlhU2HY++xvRZa
aWlsJ4mjUGmTwfFCi/8nhU5sLCPKMgurFc6rD1VW1Q1F9107xKPxPFjd2xnxd7mZlQ+41C1aA/Qi
N+nJvBObUW7dQVZ/p+A7Zw2U3P/Z36o7yEx+CDTeyhDc78yRsJsK7617gYS32XpE9fRtqDXRQKqc
pvy5cEQ2MSyybI/NAp8GOoeXFZUN4tr5yoZFu5sCD0UOPdIZJUk+cJPq03c4qMfTKYfBJPXLeyNB
a3gOBSSE8n4lpeY5qlsKnUzQyOW4ZbHJdKcVI7g730hXBa6kEALVWUO+xJYQF2CrcfJ+yhW7rfII
X03duYtqvk13p08JGWh+zaawcboAvNarjOBxBghflhJQ4P0CmvytMTgQO9LUDl1/204K4ZZnn567
ygp7ywgNUh9WA7OVxxLt3ja4kGYAmRB6EqbohGz7+xr4/UwNgGH5pkGyMArxCyR7zGYK56rwezIV
FSXAXntkp8eWkr0eqUm4P9YRrxe5rEj2B6AMn2gEFnNgUCxgkHvvtAszi2qcUQrAhrCvVCPdXoHh
OmPaQdwy6FSF0zC4Nl24dEHHDh36uelBwLXLE21k5duYKw/KFVKWAhD0sxmKrSYnenXPqYTi0QAm
T0cohaeRyBDxE+1XnJdWYNhWjZ4h/CzKoZOdq7L7590LJS8guN7RK8ciJRr6o9apCxcidxN2GKE7
iOa93cRkM7HoI0HiUF0/LhL4j1ucRhDFtTqxHfmaDvp657vurXPXh7MV6ZOHz4IOZMQhY4F3hCGl
fD6mHxpsfh5IZ7PjakX2+g+bBfNIecHaXgAZxDt8y/cAzEQKjt10sFwMJivj+UzOiYh4imFvkmw6
TN52FiCX/m3bo/huiYvHy371anXPu/utyBqzMOxjb5WLFT8knBEXx7/p6IPhsAZXB81xCfWg6Kao
9kMJEpTg3LooqgjmsA8zuGj1VDizW+tTPKd9kan6z3QfHCsEYJ3Q+ge7quBMC80XEercHVbL96K9
yVCrDAB8nyfQDlMWUES+mowaaSxw+DutXsV/ccaul9X8YFqYJtSEe8wVmNzrUcTik0WLGQnnTSUz
8We7+UnGkjHSzXx0o/WepV3ILbZOjwVT8W5UHsbYImX+o4OuKpKdCoTsCMYXMXZTn8694V5QpAIf
FNGQJb/S//lEQ650WW0xhjXI3kzqMxitcSdRDae56d5r2N7zCIB25DmczvUAsm/UJP7hBZzdrRi8
FTQNQbrU3Kel5rysJEf4WL7tZm98NlA8O+vkn3RAmVYWIMy2nCZDKqaVJosf9FZcrFPI71AD3yDo
SNgjmM+Ko+O3M97en8PeFtryoONTGA6M1+UxvcEzAXNnSQL9Y1TGKwzJxj0Sz2pmmT6svjO9y/LE
9wCbgsZ7pKXSpAiqzWLugaqDnRzuwOFAgSd4wK9+gVVZIHxhNgATEPThR3dfBB6KyP45CCa/USKQ
F5x9S4s0yJqo0h6PsANNyyUaNdHoCAlIp80KvFZdXTeiio7aWIqeF3bfpozw2xDacMtD7bEqzMkd
ZCBJnLKvu5lQv0+bHx7q17SaDhiqgqJGtzPuOIeBU8/xPICx2nyNVEw11ZYxZ9hL+ha25qbgS86o
EG2ffqQ8a3VrQLFhsN0ENDcGfbwbHEMGefJEgAGI4v57/okIg61dTMGvLBT8d8Pn9VcyjAOS9snE
zHZpErxdckLTHzQTivB2bLb2fKAdwJ6CBjv6k06jYPIgOo1xkuOIZrk832k660+5IYoq54YXQH9N
2kx8zHXnJnyoBncEKDVckGlHbzCrMBv5JQK8x1WZWathOKP3VsP54wnzHvsIDnweZfkCskDz6K5g
RPfu8VUQMJht6kX5/cV5ZiBEXj4H0iYfhukAy3hv/Jn6KdYLY4/o6w4mqnTRO9YD8+dRkRBPKO4P
aS54gqi6MiPrp0vBKGYEiDHbCNcfJhYFQtlrQ/u/dBLwLHdZYO6IXcaB388dUhgYkSeJa8b7bULV
u2O3FnRFXIS1BKg32xJV9zBPlfv/t3H41Ga37Yn7eFAq9MqIIyurlkKmSKorgSx8XxXXjnOcVc3d
4cUBeCc6CTKF9sxnDw0PBPhr4/U8dDzsm0c4aVOA2j3bg1vUzgmMIMCQbdKl/gEzxa8fdzsw4JjP
08D85AigX+ijkejN5AqyOE/+T+kEe3x5boAN7MbC0bjPBIrm026c215OPWTRFWlVz485eI5L86Je
4fIGi/IwGj5Q0O1Fj5vQwVddKq5XT2LKoVxk6ODe0OD7kweEzdbZauTgqU1kMQbBIoAG7inVxBGP
1luay+iaXKb+NbZZFlJOEdXQwWkzGRM482oKN5nL1hrXIcfvDmvCMiP+TkvP6ff+nMt6uphAU3pk
ZXQf2ggvITQSdpFlDTsugaS8MYTwSuPuFLeK5Xe8AzF+BmlIeBOlYrjlLd1oxZuH8mSLkO9Nr/AK
ib7tWW5PmtH6gCU9gbOdOl5rVDlmJcd5K7GX9kc3BN9kvjcZY570iFCxS3qJdhNWWvA2WLS2UhTf
DICEYxZCQjkXMN0uf/gj3DMNpHvt+hX0z5GETZTfu9m2oX+JWOTtuDtCul6HVtD01kz5jG0LAfXq
p5+3TieITvR8Hjamit14Vd8KkmVxskO/UAJOhcHM+tDiWaKoHibKF1wjNSM3lryjAc45HZL+leGy
8U6eoyWayyPRFJXPLMv+bQH+8MDQ4oGfjnNGgwYG/o36yCxm9/jqit8hpM4kQrnBfjrdKmc8VoVj
S4DvhnAvY7TvdRA8dI5BWSEQUWjxymGBq+nW/piORKoMOdkmCnqOLXkiuTS0QXPMQsyfF+dv/ZOT
FjUYH0ZIjtFEfkTaXIrDH5x4i9l/bkXvHz+OieOK1NMsZdYFllQpl38jwAVG0fhF9tbFB0qaWWbB
Q19yAmn34POADNATs7tDM2O+o6eRE+Lt4pMz1jt0x2fdAawdl7ibBziiBLwE23z/+j79oOXUfFnA
XSpRwlZcnMdyvrL7lJg/Cp74Y4RLUKoOtkyBDbUZAmIc8ECkxuJxAJLAybqjW3YM9+ky2KHuuzUX
r+7e4fHtVkZyW3ZdiVkga/wMCKmkTXieLXgmlIGtFi3BzVKaBlH4WL94A3uuhzC9MoDdt3cUtDkE
uvq0z+E+MnCiXCf5T9PN2i3uC6B5ViDGt/dLxAq+u4Y8x1cbh+F6EGZAZ9s/85YWcn5BXMS5Rwaa
DelA6oDGlejzmkutsVVc1+NJRZ3obcJMMnQwzNOTunVkm0dZmOAzNSXK8fRR+aWON9xQ0RAFeu9o
RUrpxQnvvWqR5pkW04dW7nsLnm3Izu3p6kNPYpiL6+KhiaXdYcejEKYdDv2m6EU6kmbXdwhJtJio
5elvuquYUDDA9vkYylfeKoxH/0QBmCCkqAuzNk6XZshpXLq464lOzqL7ziFGG7g094A/X56ZeJy4
2Q9V72cS5+3EYrZj3cJnyW2tbnNdca9x/wW6b+pMmlV9sFlv2siiUiaS4h+DDCCd+2elePTSNglb
zEGII1FrWHiHNb5MmwOZviArmiV+WIe4CLCvLYN9o3EUbANWlgcsG1TQo3Q2kvXXtAtLTnEeR5rS
Sg45ZZ34KE9uJC7mZ+O5ESYsC/uZBm+uI3mefr9Dk1vHozIrRlSKAqlbWMCgc3aQGk/Dv9WVqlnT
fpcoIVduA6UsWs9JzCxwEa77hxZX9SoXeVci4U+Z57bMBXxBWzmGcOCQqXay/ZAX9XvxHqy9IrtT
FTryULMveKZCfQXUnHhjwabH2Lb+Yh+Xve2HWTxE3VKjNhtQQ1brCV/sKCqlNLVCOgUFSTPqWb6U
yPW9YbC5vj/bv+vWhyJePZVfSbCUPAChEHY28RIM5cd/L1EYu0Ie6siRRYZseMyHPF/60v5REXZS
HyEg+ya47vjYHDuUP8O5jUiu24MkKmYGO6Au7/ugPQz7QaB+WU7KkFIcrz05IGxsVtaF+g15Dvhc
MNddWWwglCFUWiqCAzukbbb+Fxc6mhVlIwWT483SrLW34wreJhr/DgN/HsnTXZkDpCGJ6wpnQUtu
Zw6frzETtn1xOFggvFofSqZcUcwROsHxZ8yVO6VNbDaFUze+eW17R3pg+B/5T7y8X/vfMbjXtt5V
Vr95cJt0WEa+INitbgsZgMppveZKQ4H86ScMa75FoYmHZ//Cxo0ufNSqpWfK49uglKMF5TMdLAhh
tb5uuYNhWi8FBj9rd/ijQOHNEk7DAKnyyMil2BLWvC7XlVVz7dH/egCWa8IsEXJk3EGsa0FWja6N
30JLuUkNlh4pYY0fiXA4thdvbhzfhMbfHitT1CvcnlVJFWnskjEZGgXh7ELWYrb57wf4o/d7oI6H
rLzLx1WHDKtpQ4VRiRbJZVZc0niIvw4vWXoKLStNCcC6o4RwX6TyNaEUMIiO68WgbmGNohXo8/Uk
6nB5UKOHpr8NtkBlKy7wMdS6mj/Wjtj5pCQI6V7bU3gvQpt+eWszG7cFeveUlYjRyRU8K7nn40Lv
E2bvTV0ZVNukYQrPgHquUVFDLZQeRSul3EPiXyJbPPoK7b7iM3t6Wr5+y0YUJjlI9jXGX14NuTXx
pMJghE/sxoK+Z3lGKuMx0wBQz+wA0fpnAbkjlgb+ShuNkJ5WbyNYLSA73LtKIFdVOO+Jie+QWyAt
FcUJyiEznJnhOSqvWZrTUNv5trd7vRHWYdFcc1MDhhMV+GfgJ1SM8ZPEDFhMY7AiMx8JQzS2RTqV
gyDffijVuJTMYM9iKo61Zdmrl4knKc7OfjuOwivx8D4cEzy0jCtOjgCloQI9+pcC6TOqA90S7e3E
ip3FoDwFAanT0ra54sN4haP+HYAhAqaP8ECE2ImaeS2V7vqOFhBigIZe4EoPwPIjvIEFSgno06GK
RkV/SHv0z2kYvu1nZ/mIXGHo0RocHTkuhtpQCg7z2Ny+B7vkYMxUHzq0xPYZHaOIK/kSvXkBxZLu
7/LhUfgt6uJpWfSjKClxyaW5ez75dGzGHWKFP48UIsWQynhiyZqcmHdvgjqQf0xstxGZdp0aZSZI
pepmKyuiiosQS/6wWYcHBVUrfKmYWuoLG1GHGyQKcI2nON1xyEhX1mZ7pKdvSCxXOEt2yq7q6Y0v
u4fDmXPxWC6/09yZASu9L9bVTuClOm83dzlxEpzDT1kYAC5mtnRhQfYNDDUVYDxf6k7qBB3iLY5Q
geHDU1IL1LE8erzV9NnK74tGISnk63p3ZOQ5ZJ94qmZ3lh3o4sIcNiNVRNrPG4+Ik1k2c5XltwJX
a2X3Xo9O4BSEmtv2aXgAw77+Ebrl29VO2928BbPp/0gzXN0SDCyzK/Has4Ppu8MeG4eR21uGPW67
d/dt41SbvkVYxu0eLoakf3CPy41mXDRQ1l1LtxEr8MvzD7ul79yKIwplAp+gWgcvjwJxqCBgizDd
pqj7pIyBM0yjGBPI4wps4cj8y+r/B3PUJ6r+aUr3RdiwRN2/vzdUYUA3rE3wFAgFdZsGViPJ23tp
2kd0V6HnJMDrxjBqoSzxdHzVAjhweFl9u8WolhEQEhxC+Z+kjjFV2kaKk60i2p2tqf8p/+qN6O6I
txMquFuOWH7hS/QwGRe9n1yfrIcZMHj3T1Er2asRCniCMyc6/HDtQET6/fKjwds/V420CS7saKeM
1JNkOJEPA6AvnPF+j8QF/s1+LluYo0JSlh72zWlMMH/0Ny69BWmsqTJBcfmdXSSqjGuAB5bpp87n
jaRjtYfgZSaicRz0KF7nex29VJwcBagHV/LwsZt30uSR/75RX88AHoW45wJ/Q2stIqzvC8SF59MD
AgC7ncK8+pswPrVa/owlhlWEbUEgit4kVSMI023VeIdoeVgxfBRTcw9HbtQhzxWr6SAMwiI/DHZk
uPXqZoygs/QX94M0OA0NcimJyfdWWhPNDp7OoSPvNyzmjPwLOuRyW9ZMHIXiNUKe6Ghtv+jmLVFr
1JQAfVHp/tkXIRyWTJ3BCT8Rqhx/omXmilCOtXbiMOKkn+mf0k0cC6Os3FMWVly3ObxMkEy0HX1f
6nr7p/zuUETUa0I5i9Ztc1fbz378oYkqbjYqgCDFI3P4rcxPHZCtvySFmOI3PBSiNjT+pwNyBiJ8
9ml9PTHTWN6nGJs2CqFON0hLhCDLuGBYGkdeCSj2FXTBTOdpjddQbVz0RPIJtqJEBgnBTfLtL13y
8Jzp9AE46YCK/KcazFMrQHBXBtFie8aWsF17KzwyoB710m3CJ+2PfA9FDvBKStSQEKVY9WN98Z32
J9Ytp1SdacuDOM7LBYSlAjLQEDlI5t/lAe4CNBMwlB7xNIqn7qc2B1yvlGNePQbGp31UElVZPuPJ
vaF+mJcJixNMFL6kQz4XELD3IGw2dgV5Pod2LIT1KW85N7qI2yf1taRxPidgvE6SP09PXXQDE+zK
K45e1cQRhP3YL2U/vLOcBfJtO7UT2iUq7n6X766ZvQ4mk1LSDTVfiZRH6RgY0D8tsagz5Nx4F2Xp
9/PYhPCyNp+oYg+Tdei0C/K0yb60GKTuC0hclWz1qw+iP2FpU+BxRG+5dbLHIUWdlJlKsOXmeHFF
YWXdxCy8YBYczkRlbsUueCO+XbssEqe81JA0vVMxtleySWmQd/zD0mMj5K7qyiZaYM3++G3DqSa8
V/EPgsaSWrSYwEVLRJ1S+2w9EzvnUsNuseK34yepZtRBHWJoJmH153dZUwNbVLyKxHcJoZLrk7HS
PqBMwwNlJV0eIMU1H+E70IeWBeg0s5+JGEHoewg2bb2Np7aurqKB7levaDoePwFTOp5HvQFa60jJ
rBS9yceGBVsvUKw4uHFrW+pJpwOGmrSSiDC8vj52Emmuk7ipsCHj3/tRMfwoG+Ev6rWl540gkwPj
/8KIKFXiL52wFars3vCkXtthmsj7sydKNXNLG5QPbzUG67o8XjWdoX2wQkpbO+PoolS+g/f/U+yD
x5dUGKpiRP054mE93rlhVqNbsYPkSi15mmhvjMw9bEf5Mf2VSLFXPkjhudJOvfLFucVfk0Pib6gl
lszofEcPUQxpdRWRkqOhlaednDCGwi4uz3ywiH6DNRA91FmTleYU+aICesJebzATwo72vRAMxN1A
RZUlXrrt7YWfESApsVWf77VAR1AGAv1jdUJr9D2r207cHayx3CQWWESUjJgJ6bZrt6JxMOtdm7nV
ZpEQjecqX0J5l9NcI5/6ZY/JD1ywtGhNeGSEdoxPOGFu9dtelVqhcZJvL66su3ApgWa9uZRbkTEl
0vgDplXGbIOUVRi3e+z7MDzhv+I4mioREHxcCcKU9WWMo0BscrqSjWMi/EFoPG5imy4ro4gtR0uz
ByfDWtO1HhjXt7w55BKWckg52K+dwEGy0VYKnJihPa8rtmulUBcnYHbLe3GGWHbIIFCDvZ6BtkEh
+cmMUn7uyzFButz3OXRbNs5HtuU6dz82KSOzJBlSXtdlznF1Hsq5mpLycLB8SULCy8rF/Q/xEdBY
5YpyNthe4kq/wSXmdidrlTKHehbKNZcTdVD2aJbgOLUA5Fa/I9WQXn+tXGHNBXZq4nRnWon9ck7r
iCddHsRqW9UTV2HRptenzm/mUzYxYvsQ5OTfwotoDyiPCS0R3tpkp5wHxSR+2jZ0PkR7dfDWltw6
JahUCw7D5hdJbKzO0SHV7WkKdCNOqhbqEE/X1OdZFRbEVbJDNnQFDo51tct46CUSvJqBp8IWlEPh
0mYKb4gtNp7I4beMHNMTKySpjw0PBK229eYxvuckIUwlqY0i0My83z9HOeNq4VaYc9jEhpz0NFMB
pHl7tVp4Ml55TmYftms0t9Igyt1nY5bV0Z50/NTdg8RS5Mj7GKEtk4xjzPuQ+97L9yBxd4870l5f
8xwwOg1ekMWznwsdBktnrbK7da7IOhedG4m2acjzQPdD6a9FUEH+SdkaTwSpnEcjzqoq4BWVLbly
nUmFGaEPmyfSizRKobInCdW/7DdnkvQVRJlH+23gRdI20ghA6YVukKhshXRrgcnat5k3a8spF8yN
7JjPg9GUOY9V7PonwdVQXaY0X5nnX0kHymm/86sVkDay9aLtuAxgzqi13BW/aAP7pv9YLzYsc3Kq
lwqt0eNxztF8FPRaCWljgibHlrrrl/977xPWWC56eJWBHRZlNmpYz5IDLNskq9EJz95L4rhUnG2Y
Rm/9A5p+D1RHhIHrMvhWpthcvJSxF0bMDG0CReRgH7O+Uaxgedtqtr//CebtSl8bFE5CiU+FUX/M
2lfuLg3ezRNwauajY+CWVjJ5gUNLXdQj9WDNvXAFWg5mnws3rZlWWrdzvuTtiL+jNi/uoCOiqIFI
+iN8exl8/QmnGdHitHW9s23gSjW3tAwQrST2Hu3H/s5HrlYvy7EtRTE7bVmqSYZ4QpmlCHDjZssc
puE1qcbBFHFV8CBQlrX9Nj3RhH8zdz5KIUvFVIK7Nsktd3tCLVNWzKJdbiCqjxNnrFAx3olHTPng
8hHwdw7xbo2ePsuSdCbnf6QlsjkwtBI4+3I1zu1S3Osg/h09h5yL3j7ktgAoy5XVQEsV13cUUTeQ
nzBFnRh4PfvJ3jivQOSPKBgTzifSe+RRGFvpUB2vjupNqtC0owDLgPooy99IY8rcavoBwWKt0/jK
xumInjunmWJD2yafhpWU7rb9L1cTmDzorgsRBwNsx6SxWiynK1+lPqAeFqlkmjQYS0ky0KlVpwpE
yb25vt63YzrFRYI2uU/gDwFpweDsAYnL2z5sBH6yXu7pgCnPABJVdAQ+mL89YbLn4nI1vAz2BWJy
+YuQhoD5A1kj7CA+hlI5yua9QTOwOzV/AX6jbuv33W0pPSX5dp6J4dkbRMzcv5AuakoEN+V4rAcd
kH+7BSJ75qc4GyHGuOMlOEcbdWYotj3Un32bAEQR9vQly1BxwKlsea4AbmEZ6h/N7FvKjoNJ9P4M
wf/59Sv4ILk9W+AtiuZrzLtgeKM/jlmMOtrgPrsZ/cAVNtgActJ4AbU8c6Ng+5uhZqwk1wzD74eV
p0aNi4D4otPVqBQ5lg6fIaaz3xp3x+Ljyj3jRQjm9DMNjyJsSxEumohQtKh6MYOfQOHBNHlxgj3r
dxgsjIwFesRO1uJ5oshTbmejBzqp7cntuBNwu93rxlNZOh3GTmfsLUz9RQUl+vqhrWGp93xt/0sq
BCiU63ejZIFxDANtZ+Z1LyZsFZrHUwY5NllsWj7XoKkoOI4MbHBKefNEbuy6eAcauSOauvVjOa8f
YmGN5cdN4xFJaM6fTYD+D2EWBaUY6BBgwHIBhdaidx0EottUAVdExQ5ShSd/5zzJhqOQXZZ4WHBb
/eqqNTqaiMaiHPIpwOulltlNmX43GNk5Knlnq1wT3Kk0hzYEjZvQQhXl0txQ6typVqNDRhgls8mC
cE3abBvGcq4l65LqYvDaL9GmEasx/tbhdgTt7P8uUQBFANofx3+N7YGxxXyqTS/dlMNBYNxsi9Ac
McWy3NcASOW8qOQmsSJUoUDrwjXlL3DCL63jx8jNtRGNy88FkZJYWy2t0Uzk4krCf+Nu9aSMIPL0
AyabGxwTY4lDjsHTNDv60xNzQVYF/ox7DacoircBSGVTjcVJ7eYXnXJLnXqtI5Blvh01c/zCQDnA
X7rvNpI3nII5zFm3ejpMrCTH8l+aiXgNkUcr/cuTdMSIlZHWZUjylrotcWCHrRdzZIAqFS6WfsEc
AKRh4lQNuYsJngvLz8S6kOFYkWuVgnWN2D/Yd8vpHhj/FK7Ye1/1ZS5ERbRQvNdwQnRm/y3oi7kS
hSdByLHFkxJI41i3AKk7QEYHWYF+Pyg6KogzNvtkVhBs0EDEhAbVFuLCY29ecLUixXUiutShKOBB
JWiwW6x7N0BabhYYthHi6Xa+A9CjooSGEFQtnIhSpiGLi50xwQ9SUt8T+qiWQ2MzqxZd5nOBqDT3
6tZMeUxqQVDmI4pEJVHhtydBdN6PcXBixjkOxT5Dd/DEtVXxkn4D2dMIvEnONkQL69/cyNX6cigb
sz25v0CuAqvkCbd20IZzvYrKDdytlK/cLRBxThEyIXXMYxXZ+RJm2ZuFQtdxO9rF5xB4NIUSwNST
fyjnUPRpuoraqf/i6xyLYkX3Ou/YrmAaHV0ww93+/RZx6sEkveTXrkdDvQCxJ+F3RnI1sJLk40g7
Q00+b3noxikGiNTsS3i/K6sMtmsq89rdmK/Kzcly+wPboiON+l+uQYL/9zCgGhhdoBxTDHL3Sliy
wMJDGEWE3Hkf8gHXcia9rGJ6dOsahk1m75oH6NKxxOXYImCVYPenqyI/Q1LByXnZ9FOxNdOAE48M
Qu18Bo+/83sD6KH0RhoQQRVaQ39bjc0PwLIBz1OCjVsEd1ugubKK6tx4BE4xKBUIRbNB0g3OEM8D
TW9krOvuzjqzTkwTSBbzf6STsJRbTVSEx4pXmE5HI4TfdASosTrDsamimQbbKRTemtdC+sVKhBIc
o3QNG3Nq/0RRPc5Aoyb6UlxTCucmWq5udHs2ATKPRoweQGriwjDpI1V6h75TOCzw3FAXZFNXxyBM
AtYxOSGsjNDlV/J/e3oOfY2ST3s+hNIOXQ8459PQmLPV2w9X6f0amPStXnHsm/hjlGhn8ANLVbmu
iaf1KCB2mEs9pOT6ldNzTe4xXT4H9v7osWNYECnJ6Y1xLzPtCbWuqOHHAZaFF0b3WVtgoTTCJM4I
cSU58MWRnrKyg796l6SkngdKvbOqwcbjg3+zat0Zsz6lCmolDW5CF/ZBQ1Cg3MZEjX5F/0dq8mOZ
hytVLMa8169imq3b1RgFmty+4OxIvRR/epBxUvDU/lqNRLz7yEm+8IqLRVrgQdawos0ZSAkGBY3s
4suN2Ms4XdVzEh2C+9wZDTV0x2SoaPDaXUjg5A8974dK87ikeVcM+1ImJh4RwR1ySNtTvDheuMgQ
sJaK5RfRle2vXkuBJVCMZ1S/5TBhYBDFrJbIwgsPJv9svX35SqKQTaRT8RbU7PMoRN+0benvm64S
XcLK1o3YvFglRn97asoKg2a8AgEBA6BMFKNhufo3WwjOxTSnkK7g636qwGr3DW9IxpxZKCDtwfXx
VLmFc6Mx5K8/hdaButTplga9GrxkbOkY/cPPTYwRO9PmZdaiq0nfgUibHsXen4iXUsa0LtOLsjKW
Lp4f6EFgVPiBT1VEG8rcDsiJquatn5RVu/tzWdq4bqDwWg4zpAWjNb3D8Yj/kl2wavnVBtxbW4H6
FKLJQSEuUDF+XvpKImF5cXUEWAqycKIg/BuhxtYy+K49437PWBH39cJF1Bn04Fvzf/leXzeOLUdP
4Vkx/bTjiy8DdzQrhXxt6whQkpzM+Q4lIkTodhcXIBwxRRmKDJzjjD3nNI8n+VUpDhDu0Y6KwegP
tUOLqZTLCveRTLT49JjhmTd3BudZx/lh97UNYKdR9xe9wq3GaWUAq8ZMtszQXNb94TrMpysc8a7P
H2gf6YbgmtPbiQWRWrt18HEpilCmUcer36eQaxkig4ITp/WF6o911lTE3ETXBstDnkVVJkr7Poct
gxTg42U6QGIbdm5jX28aI14ns0DWS9bSdn7SmcVZH8jAKFHTPX48n6aPMHSbJ/pDrB5seSFO5vt6
pL1nl14GE+F6Fb3lyp9GZL2M86mHTlk4JX6XBHtuZNr/jrce4xZBY6ghwssk155V/ccBTW6hpU66
Z3IOUT+beCTMzx6jUWd+HpFRr6Ey0I9bOr318IdcwVfDI+F0tAf3cHmT3zZCy9y/fQa1TJZJuJ+9
ICCb1FX5X2jCveHYSC0SV4yiFO1u7ssUWEDgp3cEE7KAuyZpBGJvsIMNLVlyCIAWDQ8LzSGdt6nf
H9SFdTBdJt1TTZOTNtukyG7XlZ8MnAfgHS39C+hvVXWQvdoJqcDP6ikixZCXdnT1UqHRA4b290Rz
+ly/Mw0NGRRCCOz5qrh6x1sLdnmCq8Alzkv3TX1gEQNWFV7yUvi4Agwbp1Jgv24ETh3Nh7KSPLrR
I6UyWTPnldEOOuzNc0PbUzQuK6A1cgB4xnKhiGKbfE1dc/ZMFkDlwtvPBOZPRSVgMtFcPSI7hNjS
0D0nfE3Pk304DV1CzsnU7hbaZivmuHVAani18h6gLT5EwFPZKBGcCoS7REphvozLpBy1mDVBQB8U
q3nQCn+LXwEw4RoBKx+0LOI627S2PwOAKgyZnwMR0jFQZGNlLyRSRupE09f8X0eTgmdUlgs5AZjg
ypMdcuPFuHcZwN4frILMBJ3OfYkGKCj09gINvZ+NQ8yrgXZpDQujaVDFmQyXiVHIk+vIoxthIEjb
Mrrr3fQAITrRIbdqdTmB4rIsz7XS7DLvwtAEpwiT83RlwRd31AfXsjnbbMFohvbUGyxP8Z21YVkn
HHCNa1ryKnMYYwozB+2z5+gdSFIpKzKXYSRu+Eli//u7L6fmR3sMK4EF3jU/YhnOsnYw+zzhpGS8
HVbevIHO2OtvghniuuzFt6eA2ZUf68eTd6T23oakcaEh3oKcS8YIHDxWTwQPQ/zD/UKFEiO8GJy1
kVywEKV1byfa83h2ksjAj2m71/m8oMaPgkcrbSeGpfoiNSWGgvivRvGKEeF8LuT9LmTIghy4CLl2
24/MBaHoNxGl76qJRte44o/Ha0T9+Ue4XR7Rjeirpc9RR8sJdyrI966CDzsi+S5Ngyg2fnlj7oNl
9z/HKQmfYSmJBCYVDh4ZjI7nf9uasOjFFxs74S0n/HBqh2pCU7e6ygDhBqkwh8DehXDMtckV8uVR
IaQ6oradpJmcZtnLTt6tMY1og5c/Xu4/uwTn2WUBfk71bIBQ78T700ESlPdDeaWk01Y+yYGrqLig
ByjZKhb5X9EpwHeUO3qELrE6T//H7W2+tdUDNs+AEjstaoJ6Lqn+au7Y+x+zfjqc1kdw/kXmbDBW
WM/LdzMf3rKg8Ba5tDJmeTrXilI8iQ3CbMwjqgZZ1E542PiU3u1GBcihOqDfTGSjByvGrtL997oP
Ro4MS07Yo8PxwvfOMBw5kw6zFwPCzi4MUvcfG7y2lt7ZpZPfnSk0HZXAx2O12oGOOC6TC6ObwER2
eIyAkKlMWKWZ4GFbmYgjyFLLy8LA6LiiPdj1g85G9zXUBePvQR3HY7U9NbOimaUeMZDeNXj+ezdk
C0AQtPo5YVbzFCESZOfWF7wgH73odBNlry4af7aKxG9117vT0Yhy+KY1nckN4VYRf/Ba+r5Dv3t6
5bcvwMmQ4sqQiDa3KVla23syq1oSAQnENtkU0nWwxYmXGHzA2nBYk0VTxrFMbMb5tShrGwTu9s9S
hkkrLBoC2VAhYN+SC6t4mTi2/F6qxkEX54FD2Q/laC4FmfV+22zBFUbaHFagVUiykXJ5gztjeiI3
oGbrDvdFk0AGqHoHbMddnEMXcTSVfYJfogFrLovAHwJmatHvqHxrF7RnVxkJvmks2+jo7K5X7szQ
kbacL42qg6FHpbgehun3wlSeqOOv4wfs2D13F0QgVqkpKQb4qAzKR55mv7rd0CD8m+kaOjEqWODc
qhNZRTKi5J/DCiOLQ/sUmLg4Nmk+25nV6TOcWrj+XWFb6QjDACsMEUqrW+3TJAaD75RS1Oo7wc0o
GTZhqgW2p5tRHmroY+GOXj/DgAMtiKzlLI9uOlrzTB+iyx1JDTSSC8gheX+IsMNyHDMyFM2bx0jD
ZnECNKsuYzM21c6V3rcCa/6MEQ/K3LgWjjeVKzs3U3fuCc+37cXcQ9xE+XHrgW5QYPBsWNz9mwBs
NxyQhUrJW8jQ9KbUsEYsopqz+MG5i2exUtALoPVjKMaHIrivPuM6Dem3+l4gUGHuO+cEyxBQhixh
19qPsaob+BxoHeouLP6lfvK0U38B3UfOPUybiedW+c7CpJyeI1zaz3DhIU0E2rN+T2parWMI4x5F
Jpjf3cWREGOfdeMX81sT4rzoKmxjfphGAGbfg0XS+rmucwLeipPOBaGgMDqwS9OX7HJ9g1EkD/jN
0O3FI63CBkscj7B1ZAzD78sy3Gq1vuJRJ4XLjXfAZPUA/5BQVct5MHbeCCM15kxxGaAq1RgXxNa6
njF5ri1IS6Az4iqsV2+GvcZfjwI6OfU8kCNuRjnkS8q/MWf/eLr87i2Ig8QbmwNl3MmwHaO6aDq4
zy8sAa4+8Zxdo02WOTu/oJpkFY6U+AsaW/tm0+Ow/OAeQ/v0zWseeLb+Rj4mrdJ9Ln1jMvQsEYHe
Z7T6xeLYsAsVxvFRqNbXveQGpSWgzU2oYJKmqXmcoda3RaeUkJyIInEd6MfC+/q+NLliApp32c41
Ju361/CxKLlEccBJXrqG7InmCKTaDh7grjTRyFS0ItAZk+/pom3Y4y69Nbuu4XExw+TtLhcCChcV
J1c4BAAdA3PYvGdlbtzce8pR+e6uoUHfYTenbZth9FSw9aWTa+XJZ+SbXppriuGzF4Hc1ldrIMG5
a0m54GJjHIumpwCrWpgwvIPn36C0PEvuC3Uyhf+yGt+EhxA9RNnNDtzRF5xSH2nupYe3szWdklSE
vDOzFpffOinUhLjlKJgzgOgzzysk2U8gwAlbPp/Ogk6segx4YhnejOjAXQMUTTGWdev3dnOecjSC
UfemAYIFczf5dv6uYTYJiQ9i3JgdLLEc+ExatMOmDU2ZP1FEM53Mqd1XQLp645a6fxOeKBHWmFAa
OCZhMCcon/aKLOTArrF4wfMjSKcDUMqncrpaQZViNUImSFDj2YQjDip7XHohJb5GtW9GJraYl9/k
oTX+8MfzZMxl/edzXRugIJjDb1rQbtplSLF8cBZMIQ7sflhRpmTNvWFsfKJdiOoQH+Hgfi6yCE3f
+L8NwZ7BWOupYJfiUmx2BGmz7HwZE+izhYi7qxlg/l5RJIWX5ZANS19JoDkjFbDZYRN81MbDe7Xi
Wi5j2oqYA8NN0gKgvMXHjTaVo0attfvh/8rquwO0t2/od9OWR1+lII1AOKfnQfkeHK75IasRu4x2
JD7aX0XhgA+IKYj7nBQbDFqY99sQ6rs6P4V7RTvgx2vwWJq0AZkSNmpDqDZWVivJjJd3bpF/dgJu
pbl5TEuAXPcE1S+f425YLsj99nYRWGTom0inB4JOrcbJwt/akXdgLHgd+7KOpWecdicaX00/w0T8
31E9urQf+r9Fzpokx+U8Zi1v3H9O039HHEap0GFJUZG3VppcJNsv1KuRwBhsUmxLuKvfaVAv0aC+
duSC28RlY0gfdcIw8bn1elXrFK0KgakaEzfMss8XAVazQawIfNwl/kh7s55Lbv0TnizIYqrmmckU
70VPS0UYDQmn1YH3Go4wosjIJnn3TQlwSqSuDpgs+TFt3tkXBLGdYX5lLP4k0dA/1x6Dzz9mSRNL
GMLWojN9lGyKHie0xjHeJRKwhLvapUKHvDNEV/PwDC29pn0x6fRiWSnh/vAWxFi3zjkWO3b21mDs
DOOu4eeqU+VxWQl+DvfRwZazd5akstC2bXjM5R5iLK87uWxdex9pC3TT91vbuCQyarDpENd9YaxJ
GdMM1aW+CTuW6UqyHaWodILFU0TY0y5XdxxkcHaeG+fusFa2mmUrz0xoRfOXO49wGRdyIf4oyBtr
eP58447509w5OaLcWmvpWAEvD6fQrrswJOFZaS6KVMxG5O+ep8J2wvj1mbUdj9JkCtGSAlJo3LrB
0qSyEpys4aYFdv0VaygWV+VDW6W4j1uhl3XfQkPE/Q69kIO8YM0/+tHEU0DaIFfWZcJyAK46wh65
EpbxcHWx+vr+rjN7mBruTvElhCF+SeM8OCEMrN2toKMuLqC4EuT65Y3mueKa5Ztw2SYtyBv5+/Qd
LklrV94G8SHQlKPgByGoBfkC/nEKZ7V/K1aBPmBq4o50xydAx1RI3GxEw1yH8zp+9JguwDQk+QXL
rRsPfEhUaxMvN86cMu+0syFzMcTygY/SeB1K/QEOxiH6u7K9egVO+ia2k6j/1dBppajeTU9Fon9l
dx8XDAHMbvYngzRTbr8mGtM2kS04w8G0egq1S5f1hgxoTCKObVgq+nBUVNmJG86fHDZBUWDPnQcz
JDnJkwfozZEMyjZNUSNaWKhgcDR2XOMMrSoGJ7HXIing0x0V/RmVdKfN3+uz47m/FXlPjd3Kqsye
Ca2ysyPmAb6wmgzjj6x1cLUtQZbx0+piPMaLsQwbK6CzldN1KuXDaU7DnIT+i13hX4mw5eQGN21/
6o05VnQjeTWqjUdpIE9HMsmzRo0F7/j4cDr27etneA158W+X28DtARESyXFJdtlI0yt6c/NUG9u9
7Tkc0c4sFbYX3zqofP2/vFh0BEYXflPJ9cvaYoQFhg05t3Pd5A8+qol6cRtRdnTz6GZ46LjknaaP
2KWs7SYkMG3BBCO3glNTFk+YxOv7MDflcwcWoSt8MDbYvo35Nj2hfrqQzNRowQDQoimQK7UaecGp
yhGQ4C52JkhtQDNEe9EwXkce68+gwh84kgvy86NP+AxBL2Eb92xCc0kJG2zRTknU8FDumFMJZU3t
4lu2jp5DZS6hzzlVGxcWbmFh12CdUd/Dg4fXHQbs25LQO5nAjgndBN0sW75rDo5FBfAAqnwZSB2o
F24MfxmiGCZ5aHf1T/7x7lyRA36RpbfFUzdul7o8niBpvTYtvg3nwRLTtEsq2opOSYZ3tRyh8k8w
QVeBmRPpg45OQm+NteAPGw4a8ZkxJpRb3e3LipylPv3OyyTTJYg+i2G3/bKG2H0NVYsvPbopB2PH
JAgp2slBEoe9cjbflQm9wQ64/vUhdQmueSDZth6Q/fANL9XM2/o+xGeW9Wd4TuKHlLuMwPlMXeap
lzDFy5D5DBqCnrGj3yUx5Zx1Al88mR+DNOxI58Z6zmshkbb4V4w2J1D9gtqZJeypJPhxt/TFnoaA
5pbgtg5TJo5mdTJ+Zaqbz707k3+k2IaQ0Hz97AG/GhrdJW9iBXo6vpNJ2QkzNXvcILfm6LrYLCfY
LZgHEzaKzPPD77tsMzPMThX/Zb6iNB4Se1YBFVe7Zd87AZmwp3W4YW/Gn06+XmOE9OR3S+IOgBi9
uzKA2KTQgb8OlgS4dDuqYHkEc/jQzYJWxAi0aYYZ3TV2gzVCQ6GrCIjzWSOrtV46oVlDKsL2NR53
DTRuplWWFsaSDLtRJlwPkM2hrseD08liWQKJgWCZPDCyfm6cZG2lxlXPyzP8EsTeef0a44RohNrY
tu4HcQqtb9ukHRsKvJc+pFtmvWnNpNOxOQ1weP6uZ9Dxlw9VOSKYDvW0SHDDQVFqMEgCCF1hUJXD
p10zeDnXJcrG3R4Jrc13OoDkAs9SYDqbCaB/PHf/CyKFcbNBx20/LMJ/Jwg0EYL9Ba0gEW4uc1Ft
hJVuC+rz4DquKxAzV4C8pAJxYWjVYwQLUlxcxQ5L+Ufbe0hhxVKGohYeEICahyam/AJKgNw76Jql
2PJ77nAACCtX652tVwl0fydU9PE0t+zB9INsQX5z65ZQqIR6aWDJbKFewZyDHyzqbH3h/n8M4g7S
6GOuC7IFMvGS6BDKuxT0dqZ5zWMUVD3zjmnMKafE5qEJw7n2Vuv+cdkWmElVUY2TgccHJEK+Hu+l
kA/Vd+1LxSm+3D29vFS/W6cja8G4UyXn3kTMaN1H64sps89xfHcI8jfQKlvyn8XTTf7N8BeToUrl
8BW4EYPnLg7TdfHoUASs/1oeFrgAs86OH4pbJN7wf8loY7rZevvzgY1qKrWS9C4HkkB05ZW+SWB1
uXwO6na9w2gJIpzeyy2TaoA0CnrDsub25OZAaBMqX+RTXsxfswV5J+wo6pCrfC1f/D7m/r6SjBAg
F0fp5S59vyr0oI4X0dhWmKyi1mD5Z4vT+aqrvIckYwGZI9mMHBUu/cbHiUnWqB4VXdFWJIo/UiuQ
JWAbhJ9aXHs/ya+hAuw8vW9Q1PzE5DTxHiiyvI/QpA8PnMp1bigFsi6gKziandRHDV5TbSnERAAT
7scT6Bg2plxkYfhknub7/QS8GhJyHHnQhTDZY8VG0OHfOEZ6SfVJUbPNXqnlfcYY9NOn1GZ4Pq1/
iP4k5xTd3GrO0b6qt1ehU6/l/TWtUFCxMB3viikfhxmQ8iWzwXMe6e/noweaG9WlsGOKwPqacmHB
i4dEAukvwRMIPx9TEHRXYbOP/BfL3dcttqMaHNVQOXKn91rOYMOUtRNrnJmYuHZp7IUR54YS1pnw
uDR4S2FEKBfyjwa6ZCqmQ7NpklFJaQI88aYVMw6PHRz4wlGKKMdE7MKDfufcOL4biceecFLtG8uX
b99e2bX/Uhm2TjdKz9XYFWrzKrrsXTw/z9f6mENV0b587AXHTQIba7+SO9JA6iKkIMKw6eVUE2I7
H2haGE7bufevGUEBmgvG8X/+T7hYle8dwZkzE2XJhMLV516cEdTM8cE0V9DpCOfJNaKllOdxv/Rh
V8PgCQ4yRheGkP9F6CIVkpVDWbZ4MYpsmasg6YI7B9+WulJkDhM50T9NiBB9RpMXYRcwagbCyP+v
fki/Fdmuaw5wiZOzhy8Mj4Yk9jYKOWR5lTkK6rO52QDSSTvUOq/qyymO5euzTeK7rn2NI8YUQBF/
IAwcr+rsBRR8WdbbubLU7S7fJAAxbib+foFrobtHk5AejK3DFGdN+6JAEt9chO+XVAMCnkUyB0eI
H4IXkRY7t2sokFyj3ElUV5aM9vMj6vUYk486yQxj+iVU/e2kHn64+oSUB7EVp1VLKB302Qt21VLa
HXXHBWk3P2u0YGk71WsJbiRByTvohMA2ozeUydpvPn0jknDoVzefPWNgHxFiR62UTqpWeBTnhxvx
ctsOM5hnJ0RZk79l2ZJKhHj/x46fwXlWbbx/rF6Z4ip5GJIZhIR9sDwcjAxw42q+qZWzJdIK0SiY
pHX2sscz0W97b/y57zyrlkQ259va4rVDQDLO3pGXKSWzdct1cJD2G58isErmIXIdb0tmWk3S2ZNZ
8deLvEigia4CqiKXJxx/Xbgh8dGIl9i3tplUea0Yf5FGNKA+HNFdlO2EQuv2nN+GQ6R4avHlGr8M
TgV0kgrb0K0JpXM3FAB7eXNOq0NhGv0tG/4EA36gSOfwcuxX2y6XqM0ldWmR16EKeuLREWV19P71
/8cThR9C8Kwyq4jSfDxfU9bTP+rGLPpn3NEwaIkc+Y4hwW1fCaO3ibOk/pPDQm13RQ8DZLnIAHpH
TO+HuvzgibLXAJqqrXXNarrCQ8QFHTgGYQHS3i3jmCYU4K/P8Rqa2t2iFeTei0pNdxzygwkFQSy5
lHoEWhaKLHAGpYscw/rC4sX1JzLclLEP4/LbkZQ4jZEi8rcXe8z1S+EZvzp/YpNxUOvdnUxKzGqB
gwPTqzheNkK+DPMDfYY1PyOQwsAD03rhfKQA+9PQvSwMGUB78DUZS+pg93bx6izUCfe7ugpS0J2b
3z87w9bBEKGbD54Wk0I80ePGv3QSjRZk5RvZBjevCWKBH4i6n81A4yyAD2OfahVO5EcWZ9Fh0/Dn
Hz9LYuMXqxzOzVde4quN2A2KK9eTBzWVsO9fyctXhnqD2lJafdSNcryF8fXepYzbzpPaVTYHWEBM
6JtTV6dI5Iod/wy+0qrkimwi0spdvpl5Sk2P0ffs/F9wm2ufVZ89xr4dXejC92AXnoZ1Zw1p4vpE
BW/Mzi+VSkNVVIW5EcYhQhqINhmD/y/q0K4lpRwryBoPe09J5ckEQNdKOMxjKmvlC7Y3jmMtAuRh
SMXc5tMAJwPtx4MhwIGAg/DRhklP1lb9GU2KtMmAPv7jgZydl1JlDgNvGGR4zdgvIXP57UX5A3Ed
FP32fr752C+QQUrwmy5Fo73YH0GHOC1wVfBZuuIoMAM6Vz3GDDn/iZRHvKUOHIgsh3mopApjbwhF
tuUpIJwJPL0zKHo8RWYVR46pIiAIn5/uxeNDPNqzd5mohJJVjV/JA8LbcQhne0qS3uSjtQorxo/4
uL784pp1J8p0ARAGGorWt4y5oFdUP8vT4Rh2V/lxg7gMZXT9XMHgvUe+DPM+DY26HkPipsXL5xdV
EuFNGL7HnO3qqKBu6lesja9jRYqxX9OM0a8UooDG69R2Jz+g84rhQ3Gd+QHb1OaAv1+DkjdicvRT
CNSteL6O4KRLTKHTLj4dSlj1SPzqE9kgk0aZgMv5Bm3iPB31GONM8uKXSjivnM8S4mpeUOp9CsrM
hYDByxJlhRtO4S8bwB4Pxb6pi6PPaO8DskQSAUeCjf/rDLnbAL8W1YosWxFi7jYgPGf+MpQc9YLJ
Qv3PTIQEVZinHd8GSZF7dxchkb6+KW45zrFTenxuVENdb5gamEBs5H3dwaBL1zr9vkewte98NHwC
iB2BSS+4C0zoUohDow1/ebGnMEx3VWTcIjOSB//xFgRA2yRGyzcRkPPPDK9pTra3TA0MGTMRlJyW
2lMYjWQ01m1j9sEyVDCy5N5NLr+0FSy/AFKHvMnOX3CHnDx1yCmdHXMctoB4xLwBEYl1GKeKQXxW
+pXxFj+rn8mp4yG2qcOo8RKESwl/pb5vdE9ywKhc33ND8qsOn/EE9h6COXFX5qsrZnf88OeJeW6B
iRRYRbabbwSKWix5Rgf445+Y4lPpP/XIvaVmCMvGzUTzG2cd8deodNwMp9OerEh5uYoDenbrlm9/
izvIcaxnGI6gBFH+ndMIqmdVTJEjSCO3ENIk7Ux48XYlHX1IJprQPaCXtaqAom4mznGJq+6aym0P
5JKMqNN/f8Die4j9bBq5pAjibeChtBwZ9kStD+eu0uGKJEa0bJ36GwmffFD0DAo7GGeRsBJ7lBWU
cA+YBFdmGcoHvZg8moflj7WMZbAQpPAe/mFah2ILZfxd1vsckuEJsdXCeKKKAwg2VZnIf+iaMJob
Vkw/7EvxgB9PVZtb8ATtQgVSHc3oTQV5zaSwHpAo2JeKdayJpCuHgad2nG/FeOt1kabeWqMeQxrB
TVinqM9PNVWyX0hC8kTjx8ppwIQqtllPndGdw3EJcCwA5JMDOf/cWBk6LZTfBlEJLhMtcagp9/kB
/y8Y+qSEl6ZGr69wOYhxPCm04saaIFHg7TagTHm6ZiEo0RNH2wWZlgmTN0b9n+TcTd/zs2Mzgane
DT3p8Co1LWy3X9CdGrB4L4dgagelsEkDbaJirdadCEYbelmoKTY4T7XXhefuPsDXjeMg3aFhjBMV
4r8m7U/imfOX9e/OmvTMLLFZ5tvxvifsswYYQmwQGWFN/o05rKCT/tQWIgpJHYMqbw88aSNaxHAm
83FEU2jGo9p3sFM7sirwsfDa67NgMw6nq1Z37cGiYGPMTQkV8TKvxmNf7U/3iLO8XqrcQ8BErxDS
9Mi+cmJiol5rr2Hj0EnwFj3qvI1iQ2Jes9ZF4vGb6BICL7DmxWIbrRPqirarwBtuxp6SIX/nyXre
SVeAXWw8g4HUYWYLoIzx4bkJcxme4iTLpniRk5gLh5fG5+hD3ZFdMryPqR+1MQ3CYclJIFEXNXOq
3Aba8Dr35CWoVlPEvIlkmJzu5I/RxCoMQz8+DUf60tqDu+hVjYGv3HlRdRwt2IK5AoUH0HytyY3l
FKAplqrkqwiPH5wQ1nW//lW0kMTH0PHOngKOwmsH6CBFJyjYXFotkNnoraxsZqv5QrztlDtJUTvb
BwGh5PjSPNeNz+wxbYgga8HLaROf2JpyHvd7+lMshQ18St99ftVir9OWj9PoV/GqAqps2On+Erst
hlYGsvQN9gmqjGeN3p0C/UQ9immTZDnCPY8QVSi709uSAM+fZcE8WHhEfX1lAOMxk6n1R7dpATaY
zrrCHG4Z9fUP3gvzCtkFSEv181CX8GzfU7V23jRCdyoSW1bUQQE4x5weFp+Wc/k95dG9umRNp1h0
j7ZAQJkwBiB5du+bC0+0jZC+T83WCVQD9eH1JsCkRNtjjtxikFJEjVa8oeoJVpihrvglkz8/YnNN
BFuxIbhf/6Jci+XW/gSIbJRJXDkQ1eDI1zMG/feP76oW9DrWCFznD6NX81QRmj8RWJt0CaCTNTxT
4Xcd4kvtWFZ6NuZlslEHTbpip7e9YVFHNpbt5eKB85mO9VofaRRikKQtvobkJ3BXEgiM76eZGQ1J
T912r70Qz7cmJLtMQ1JOZ90IuG7w44d9/+LnmywGnUy6BDkZPV3zcQxNKpU1kkvnPUN3N5T07j/s
7jJV91IGx3QaeWgpyR6LRPu9FhYDpEDLLS5enXuzXUVEzVYoq+8PKbCyF8BFyWq6Q12SfC5ti160
nUrKV8dYa1ew3djopUqt2ZOTotTMAq4/YBENV3M8YWFJ5o5lN2Xy1q4mwncWoY8+eP3bhwWtL+kG
dfeVPSs77d3ckJvOnhVk/jh+grXgAf6gzBI9KI/WdFCiRIxCpqaIUsL+Mr5m0QvO26uD5mn9SNw3
eY38PIpVDE4oQNH48NYxoiEiE/jKRPzuoPZzb7cs7QP+BYk8DKVW6TY8pUwfTyq5BpO4o1thKWDB
GrZMk2PgFPkocMMxEcj6TSbnVPc50RlUx7XEMfVM65vvMCgyS35jLPHwKxroyh2xDH3y2a4giJsR
EhVSBqhlVRrusNhd2ZWU6bpY59XuHwH6/o4VApvBY/xZWCPSLbEnvT5AYDdqbN14GYTPjj2FHpqA
6HcXM6aRCpnlPygbYJYSkIK7OG0LbL9Xws/MMb3gM+12jPznT77dGL8Wj+ckWWZV3PaZ0eqtuG6I
imLrVtQje8O8igFJ2lOT7bW5p4DexllFoyb5s3iGfWvnItE7g4dWij8sBQyY4uaQXkWkR1UbZRDn
F+1ph2j3FfJWqTj6IQfVF1ykWBPPwsSd4I6AXiqsQw86dUGB5YtNClKBot5inu9C5h72bnvhgZBU
AYLAGgXt//8d8xMSX8XfN+myfgm9ZMi4+q634XBvp0wu4R3mxREdomTUIiqDhI3SmqlwcPWORCAu
08A5ECODHyh29cLi7HxwL+MnVKgVQhWlfAU4wGRCmdV53ROysKFTf2bjAuuA59YpYaUEOWFybK22
OFD14GFpCaVuF6t7R5Y9kFrOLO40hhQw63iyJ5tXPS0wcjc/npEfL0H8X/rQu+aOrdzxdVnJ1YzH
SEdzpYR37O1ABFN+Qy1WIbrNvrKJMbsZ6ntO+k200WZceH82rTckAnjQyMuN383L8EYu7nxtBiOa
JYQqOlJ0M1iZAZFSyd7U5u0BVu4k9nNDnMDzL5EmUs9o0N5NC5pL+9TY3mAJw4cLB07LfyHRcfvQ
u0l5h8XpBImnQQby9u0omckqKi8bu+0TtJMmuT49AQGvntVgIbqsdoEPjlfYxn9Ao+yQ9xvupQ6d
3MUaYHK8tq3fjoqx/I6U/ZhvFthN/K73vRQGW/Fh89FpDKEvsKjrcK7lny3jw6FIeiYqruZP2GYD
SstYP4ww5dqtcjWYeNnY1v6A1fwX2UfZL5VTVVjfqkEY5iZ4cSGLCuYVBk4TxVWvc+rY9BYbAhKZ
oyr7VgV9rMsyWcmko5Kc9ZzKvP7HGmknLLUT8kPYnJUvkPHNY+KqxdQShTCvELeE+DciGRDlYrOt
qiyAO7NMbt3Pe6Zi9QHwFfOxZhvJKY35dej65Rc9lRm0nDr4mLeX5NqqL4hcg1cOQd2f9WDgu4AM
tQ9veuyYxHPjNod8THQHU2Pen8Zk2FJ0V8RC4aqC02ikqC3ibElAdgJSsUugK+cUSP/iyv3jg7qD
rzhnLbzQbDjxlvyLdgL12o4LvduODFlAXp4ESL4V4BpEAleLiRWf4N+Lqot3wE1WCTTd4aXs9po4
l4WD2aZjyDsrKUyJMXe0yI1zj6ozv1abyHq3Ai1kIvvRsDtJYcni6S4MZfMPMPU6q5ZjMNioX6S/
zvDa+tlpPnnLEkRKvoew09sO9k1SQ7EuCCT6q4mvXZ7zkv3P7bMttmGK5dgwNwX9V7KX5ZSB2D6t
+nv7ykA3rT8K4udikCTU/tPo6zhXeAx8/s2xHkKFR3DL3n89pqZEbVBpmqdyKCYGMYxTb3tw8Z7k
15RfBA47EfDoFJyERj9pFpIH/+Hari+eusoElEJWwIDO7YHENYEX5qV20mOzMx8L59miycqsPOnG
HU2UlKlQuHGh3/lYXfKhu5stq6CeanU6GrpFDm0P5a1bqk5A+kkZi7K4vYDOmeen/0TMTL35Hjpt
jw+X+t07IyPID+FZl66ZhtXinfwqJXkmGCuPBAzhGxyTrhSEYhCPyDYCOxYfhxMvXAVAAS6bx6nX
edfzqgerIM5NNha93qRaWCv4eBhIeERzSnOSU/+0jjzENokqCyT+3tkAfBPZFy6DDJJD6LE/bWH5
IJI/A+63wfOTjWgTv2SYmX8TO544OTr4M4FZm74QQ9AOq6mwGx8GA0FuA4WWoKM/HEPwWJws6P/9
H33+0uWKZaosE18Pp+5ltD0lWPxNFzQNfdMJsjmoqCX2F3I0Rit/dPpVZ2gBhKv94/fs/f5luEZo
73m9gYg0AcUza7TgD0ik+J/6xFeijXuibVZ7Q1Y3exMDJY0wb5oJrlO8bxzFkrllFYLNGIWTc/N5
8goBAr9ulTLtLsIIweVDHKJq13KyXv9I3DUB4qZ+5N8pB18FKCaKtQA0LB4johhKnGSAt0+SlV1I
e0YTHYz9w5OiFgNlD/Sf/8RZkD8U6k4kT/nnvxtVBE5YM13gxAMCnevp0sVvlsOnwFi3sD57UBmX
kfTo55gZvsiZB0v4EgroskMC2/b1M4pLzSFGEwr3YeR6RK4COQqtjzOjY5vVw6ijbxRAbmmGfXxQ
bFa7xtCm61TaReRbc3vJt0CiLtfCA/pZcm4S/I9R2bIK8CltWBhDfssm4QhvNxgxSrerVzcTtits
dA8rRBJvoLOXGFlEwNQ3aGAZGmjsbUBKqx/S/3KjdltHjSoF8z2QQE027EQMiaiyByI2EH85vyPs
yEY9WlFSy+M4pysi0R7507vnGKs2PYcNO1Ov6iz7X+xw2kkg6umM9ApkoNDuBY8V8HDbodru244I
K5czVhwDUqguPGLAD7/hht8dkCbhWOpVjAfIZ+6vOopg9a2gcuxUUYtBWcEygU7pFGzE8IJeRXBf
pc4QqMPdswVgaagJvKkpll9XheJEDodMMt0caefDmQYTWAyl/b3HwVh99H4ppHhlXlKnnTh8THdc
djoZAVKA4n5zlJ8RlNUT6ShKnOSoiu76S1REGVoyXWx8kUGUNcIsDshR8YUlNt3D5iAQrKeeoxX5
23WAKCebGedTMawvqRrObrRyGPgjOl4bn6HPwIFfJ6L896mppxarScWSCVRqA2R4AZ/WojmCPiL9
g0qzArI/DcscWviVzFpOQ0PU3tT94LfMQx6UhPG7Oe77ha24Ar5IYYFtndX1aOZQcDJlQ6MNXRWV
d0u82+llcofcQagSD/blYQ0p1dBBIYi7n7OlZb4FhD2H30KX8UisQYjvmm+WYWkeeMmm/pFLhfLl
rz4zl0yxjknzmErvCCQqUb2uZDBuo3y2gOhqMqxVICruKzcRtSbDsZO2otvgwppP0uaXVl1rBdyB
e6cykRZX0aZf+Y7bpcSo54GWtg+7wbPThWZ2YX/bPJ9Rd00SFpIdu95Yj6MehdnF1pOel/aJdueW
gQa2L0ltwpvpYqgnipLwy/cwPQDUo0rhbtTvduBOxRWZcdDY/38OxHfl/Gii2Qcw02dNiPq1Wim9
BDDvhyLI6QaPi4UtkUim354pKPhTTOb+WBv5OncTtlmvV3dWy3hMNalxeIoJap8vipDs5RUacw8U
Ug66/bwf4GLyERVMTrTV8WEZiityGutgix9jVuxIfN0Fa4Kg2rX2aPzk7FH8PhBCkNrN4bf6cNC9
F87ntELp2LkLTEhh2uC0iLceHAeH2y4NGfiVdbArl/t4QinywrDKSh5pDUDLN8UsGgaxOHi9XYxW
nCGSHhCf/hwJw3jCxrfZ45ESZnEHHeXeEdF3uO3fCan1+u8IAavvugW913fayK7+sqsjHQ/PmZBV
eGjnQUMAiIgDoklBHgHBptH6HdJeHXYOOTht5RUKWx2Ukd5Gh3JNVRbm8Gtu4WAGHKTitQoH6QlY
30scHgrEEYFNpY6yBh2xz2p2ZHU0vcg2qYCpapyY4ule0T5Jbwvf6cFzbUtqCdPzD0FpZ1vBOP8s
CGUPLZIZRQ8vILY5IjoCazsJwWq8YnyhEUaFeAGJNrgvY2EGg4cV+4GPinZ6sw1SZ/rGAWlMvP0O
k3WYTkTa7GeQfMTQfvbmXIIdlvGK7cNjjebS4mAXayfv53xCm8b408tUKFD9JZ15vdiIJp8Yi4/6
gIvV11pwVlkoadwB3qcGhZI0j9XQx/vrqpV38XagC3MB1vxJMbHvENAPnkXixwzvdb+ko3ELf8Ea
zGsLd+Syj11W4yVjoY4RKG9p0+HLdR3htOpefgc4lZDORt1AG9KYgFeLfVZXu8+9+lT89UraPhke
6nwrsri0iN64CV4kFy5uTNBmAigiVrbY5z02Y+rdqj/Hosur8SObDQifTFOkn9xFyUVtvJ+oOZOK
YlY8/eE738mZicykuM51hpMvBWQiru2doEcmFsftZGOStGYboYl8rugKBHU78QHM/S7vyf5Hu8cl
017zGZFnyVx6yBvY+pU4/6sTSRnA/zbreRcVief+OFNFir/Yjgak3NH7LsukdKcHdQg/HssOk6bq
Y9EDAcEarak6m+PGEZDvhfXE74nElkD8hUp4EPSlxT6QM6Jubhf8HZNSpfGsfphqUHPZScnYh4o1
z2xY4357CoS08aErFbEPNi6c8LzBo/WTjmuhKfHwoGF6SpwUDFw28a/S6dNVIbmcubHuupm5WCKq
ZLA6qsAXFvzmiCjiBBOmgPLqj6AY5st48cdG87laNPboXgwOARiBaSMsObBwvJ2+ee/JVtGZ0BnA
+wIWdkvdj6enpRksVLDpXGmpNovjHcQwpiABqMUCrnmzYD/VzgnzbO3hamC8NZEp9yUmF2zioFmX
8rPwP8o64FA/WBov0rZkOVD5OZkvdVtvSowq3Rm5ymMpwlOmgBTzBYPF1G4Unt+cj8zq0cKlLm7k
ZrQKCdJ/lTmVbDLqAHzZeVW5NqoVvfEgWxYKq3MHqfy5IGMDrAibylHL/nqvuVHxBui5PLOQE0Kc
cWzrf91Lp21puFcOKy6CrMOJPWJrph0gEkXEr/RRB8RWyGoQgeKGsH3pVlmZEXtk5iwr0GwBXiv/
MqJsIdg5OdK4tDRDbdV/oizWAaPNXVdRT6I/+hYZWojStoGMAqKxQcUecDvgzfCmqffE5Fsl6r3d
DK53KNQwurE1kRZzcxGwDHoNaezlc4kpzQXxyegFHP+dbJESn2JHev7IlPWfyuTG0vnICDBwYKzT
YtWMPXh+CRbkOFWHxtRk79jiUmbfDDcj+PrNYIeBhyXfRm7uEO/TK/ubFxPpzm8fZNs6/Z+QmCEK
MHCNtaFixavK8nQUkRRaomMgd95Qh8zWsc5USbaGjFivkfT3U8atOs2kvg93Rgx3heZVI6PUTMMR
3rWGznakgGE4FNk3di8bN8pEn6woTuN/AXmQb0Zb81vo9xY5vUd1IT5qcs3CjMFM/2vTiML0L9S5
m4mExeHpTWneKO4bnmEOtdAGGy+EvM28GGhjZRVCakEE8n3c/aBJybqZf+D0iYOsStyEFcPkY2l1
wx7IozLKc/MxJE+m9z2JvjQqbluQlV3/WByfFjTyaBGFLq6A++xGDiPYyMnulethykZp+hTIX3Rw
yk5G8TAh2vccS9+l6rcxHU7UWA1b8W4dRYhivQppcigrZbfsoa3i5991l8eV83RUIoLm+86ygFc7
L7ydC0R091RxHq3eKQf9J/oYxcYxeXjZtU0yxMVr4ipPu5h4TYE6o8zN1PHjGTZ0/Ei5Y4x1KpGd
bSvP2uwAElDiUg0vV1Ras5BGyud6lzUTtC+dWszInqBrlhnqLZeRbBkO0HFKJJi9tFHMFXrYOj2r
7cr3v0hr3ksmqUQ3Z/AR6VwDkxtNTpjsMo65l2NJVs3P7Y+O5ECJkYOPVrlyF340Kk5cQpSy0U14
AnbtSPM4egiBkdnKf7lOud5NhdPElC+99fPcKvxIsborlbk7Z1kL5Kj/nl7BJoFnFcG+FBVuyuye
pIMySwDra3YHUxw84b9/4TAljpUwzx8CT10urwlnfb18mijZOABF5t4jiFIsSEEU4+Y9bzMu0IZz
Agwh8pQVminFwh6G67kyM9LM+zXThsPwfOhwFclhMTwrWrpP8jrpJEEB1coJyPjB8/5dfI0J2kCY
MQE7bt7BqATSHXfCuCo9bk//bREj46CFaxf4DL4NrDl2Rpf9eTxyoFStGOKEfLN8UM1Kg0NY+QSQ
FhAXYKarJbS28HOkXvVpITeXn5TEE7bx1S9eNzTatIEk/vdijUhhnmGSh0WQb0GlLVWlQxEkU/fN
CY4sp8llZkdTTOLnyXrKbzW+qjMPTYCc6J6IQQmSkd1EG0He9iC7tboiVG2VatAcJfyHXXW2RXnz
bcmWAEnyq4zRPHbRuOJxphNNPTW9FiL+lgT/46fDSMQC61Xg7izVEYHyfnsEgN26ArjcTmcFy4xr
lJdenJf+r+2jvm1VnXPS3BZErozeEUL9KvI2NavxwVu1SeEFwvOd5OljOmbg6iO67l5k3oInaFDK
AwcZdgRIJ0RIpkIRf7venObHWQtIP+O+jDFBPNtvYRKad8/CkvDK+8p1GgFI0hOsxWa9+eWel7yk
JMcelKNSKZhf+2jMiMTBHRZ/IJqjqwUDSjgvRJ4uYlWKRmxcifnCwJ7Yrgoi86w6EZ+cVc8azRra
3TKDbWG0prrqXj3r3EGZwWIi3pVD8RpZ09vDodWEcs7cmsaUzJCdGaz1rw2l0MA530EUbzOUMjbh
mLYbu0mG7+A6QYJsy7NCsiKX4pQvQRvxmXORcKrppMlky0Cuj3iqKTEnT75eE5/4az5ZAEA2TTw1
I3HQlRZ2Yb2yz75EStscOUBz1r1V3wFHUE+BLqExi5izq16m2GrPpKclae4ku/+tjxKk2hRoRW8m
YrjvfgsUewFXhSFgoqfP0FGDd3KMGC6EZNo637Pl0X/3WyZQxZPe423WEzo/8rF/vy45V9kJXAiQ
ygpGBUlWAEP3XzcvoAbAUjfY17dSItt43du1EVRnakIZE2lzTWzd0x9KARoa46rON2vSr/bEkCJE
Cfnb/dDm9pA82GbTXlUH7Ddsj5csHYVARBL6I05Woe7Rrwx8/7Pw0YkgjcrFyMoIp74be5z+g2Li
KCBd/DArtLiAFNnPiFi+fN4HgmoVa5oL5+azFtrpVrYWexgGDVOLYC8xRLztaUlOGErygxLeGm6c
mfbPtuxg66FhNAYyJES7hRM/ys8fNsyscQidDISNgPBuavIJE25jrv2lTCysnDmJ3IKmCtiyBQek
TmbrTYML+XaP8SoXhjUdpKy1HvmkTTsgNhgocK2kXzGNapLPkIpR+P2fW19j/A1Hw8Ao7DeU4uZI
j27ATvptuehj3rPAxSYqgsB4v2RCpWbANL6mmeytuvUEbQqE9ddLB64ZIag4lCkEGDtFbn0CaoiO
ytHKIGKH6Et/8W1dJ3f3feRhAiUCenqoUSqnrmHmgMmXGF+elVR0DVNfzICMoL42EgVDwrW/32z8
1ik3CW5/8WmzpA9/u4rXp2UvmG+kUZQosEbB0lW/orlsp3CfhebA3ufthl2J0bBatrM3c76qygIK
WVuSquApyTuFELJQgrV1NXwXjkfdxcezAb0FUKMYrVqwDrg9CY9Cl3kn1zZnIw6YW6Yu5R1Spjoa
YnOij1x6Z9cSbNH4k21H64NOTWy8T055kRDgIzf9fxPI9sGtWgKXAE/6vOIu8SFP0SW1smpWRgyN
j+Eu/Car5Mh0faHfKDzTnD+sNdyI1a00NfmrrnocJrZ7fdVcxSb4t2tyDohwpUptEdc1BHnfo82X
EVLlkCFIm3dlII4C7M7GqrRkQiokpgovIh0MmvZvpxKCseOiG1bn1KkNcwEmJfpFt0zHcYk/xQQB
nB13DQE5YC58sCfQxedSX1eb5le2can+q6R11ZVkq7dbWlFY3bCLhG1M8RlAU0dloUXqXE5JICy4
Z4eI0lsomwEVw9ukzTjihTK/SbIMDIeFuGmb+GPyj0VS4fexvXFm6f5bM5fC65NaIINRCIi5MYV+
rsfDdJSNNzR+IZqy4qacUWYsE9y3KOpQeR2UXDHQFAMTO7rTVy7tzSupVqrecqfyd0A1Dc7WsCMG
JYZ7YKDU/tUvruETEVAu7xZzkg8QhVj5W9r6zno9cFwPKkv7BX2gpOf9eJtu2T4W2eQHSvePqbvX
GLbJf1X4I98XDKfODwEkEQs8FpMsJ++nEnr+V9CsY9JtVWmmCm79fzANwzEz6sQ9A5N+lrSzrY+G
aBVSSP91CzpIcjdli0hcqAz8dBBapsk3ivNIQGwDlXLYYM/uT1V4JzqnbbgGpyeVOsAxOQpotldY
xo2imHmafTS3F4FbeGWhM11DM2KYjAOmp0xJSiVeSNwgEgOePtmiW9cElGS+EIxWfJyZ/LAvvumO
LUWQG1WYeteM9ref4fgXd8f2HqljCVVomWnupzz6aSaVuushBSILF8/YKzitrT0+bCAxzxgPasIv
xZTCM60bod8k123RekbMBwh4+w0NMFWX3G049s707W6MCWEo7Nm4cLF3g2OZsuOOJZ1CXsBL83pV
HNmy8gw6ci0soPG2s4YLTF68ZEkKvFkw74tQWzemitZ0CwyiwTICIQlXE7gBaZm7sfBSS7YvXVZF
bhcKShzYCHWFpyEU8FGNsnvnSZbmhVTtklVdn06gzJEBdY1fKfJao3Qaqu/m1VdcvCS37hL+5Ymt
lu2DWoh+hnnflsEj6gwV8C7v73Xtm+E7qtbxOwToVJJ4ixmtQ0a73UOXCyoMn08H9t+Ss5+8I6of
Qbl9ZC8pwx5wQtaSKxxv6n2fxVwD29NzTgRrxW39ZMgaohR8dU/GI/3HfG4g/uJU/ctYQ5Oziai2
6wOwmXJTLLsYqyb57y+E5FOeNWEn59NpeKFGSce7SWLrpNlQpEu1DJbbVmepOqmKWM53KrL+uODz
KnzBuEzG6QOLmVcnBO5RJjiPlx6jJ795E+ZgiX61whpSR7c3vvNifG3oBkVVC9eOvCkOUZeCG/6P
eRSsLu4QabLRAE9Ymk/D1pnLb7SE+yicuIJjP7RaBvnec90eMwO7vP1EoI98UfT4D5vUzjnHvH32
PjTq8iks9MlqartrT4jYkpC9mIFnQgNgh+pLT8MRztCSg5LDdtXGROpBfVOv4ZFfFimsRr9LOB3L
rq7p5HpEIDi2eYNf5S5TMK1oOf95viLXBeEKlrFcBDV3oHiFMdkPnlOYCIMOuXKMOX0lFxcN6MG2
UrBsv7uv01S3InxHhOCGHo/008brf/QbC9ZjMVcQifu5ErVijyUGrDs+cTtW4BwI8yot0McBFdY1
5OLxMWwNR+26agTcHkPefE9Ta4P+oODFcYLl7POkV958fO6wgCvymfEW0uoY/b9CFcwIA5ObfQuk
t2BF3IfZFfh0fZQf3e/cYEH/rGSZT3h0NrsyqwvMNwco+QNgD+4bDHHRyAq/iWGx1dKur+ZzRl0t
CbBi8F4+Vg5Fl2K1kRR5v6ysC1e4HF26cG71mIoOTTdxgcenBRgcIHmSogIf847N95umG93oGTTr
iMosRQqqrRgyxwjBbaUv3ZYvy7V/6REAE653Q5Bv1FmUzaADK17GKcQDzL03emUGdZo/icflMhLt
4Unlbau/D4eMMrHgKXYKVZKau4DwA+FKsGuEq3iIpMoAnoEjXTSzLyIYe4mZJn2aRWJtSMBs4lOw
Z2FlAcMQo5JABDIJzg2Xp3wByygFL3605dFmkxGqvm1RX3dAxvI2Z0MCKx1+4NvACLQsA2PkB/zn
tEkK/eicf/XFmokcUXmRNGy9522TWFkHbkfa8IEGkSB4GGeFITg0LFyekjOc8w1cGZ6PvDSBcW9J
k1ifA7MQBnd+x9madL0a50yHT1ZO03XjXx2xWwfPz+pk/JCbcG/F8nxQctDYla9FPNmFOuPZJXMH
MIy6aDO+I6o1vtj3FFeJrLftkXAi8QU+6MBQdMihg+ZBZ9C9rvMOUoTWdSJebFsDoH449Q1qSeRB
4rl9rT+/Z/wo+WcqdDu+4XyQ+TlFYdkmTuAJ2Nll41QqJBnHTshGTMndyyRlBToQBR2h+diBBhRX
Yr9BLzLyZkFmKi8Szet38GDznbt51TEAdoXiwbiCT2BSzWy8t5bD/ssBLNH/4grN3tDCmKMjk9BA
pgXMIQ25fzdEXH/tg0JOIUQ/+lhbyNWHvjLpRe++KOq5UAq80BFsKods9mNlTEezWQ6zX8ZlirWq
SQV7FhtVPi2qUkOjHM17qgHP2D9ghLrskc4osnBbV7TyL4pJwd6gWAZD6acZ+SRYlBfkkf03hafg
WHIkrapp8D9IV8YIJJmmZmrQKzuvVbgwx7+IaCqGI3h+FjBpbKaHwu80LhvBTgo8+kFEk5R7ZH94
mOV3HDhivnvLUGB5Y6y2WMRBmPISXJ4LkXYLs91k8S7V7pitVaTBJMHcNUHGqs+UZOnSEkoYiPdv
RouZTtW6V6cGUcHaaiUaChoxTC9GYshs8lBeOePHwNrlxn1yZTDCWSavBC+pRU3B7HaYYgSt5NPa
Cr0k4oBc0CnhT7QOdGa7adNdQaMdJ8Rm0Mk08bVN1dKkMgVYAsTB4271l1RIiAn2/R1ykPEG9hxf
arnBSmOc4E4yuUGH2I+CqHWMi/L8Luskr3eooZyFgoC4i6qZi4WcxQs8t+Be4Oh5JSf+tokEVAnw
Ufv6x1zeeKS5rDXAOUaiXbYtU1v20zQkFCjloxA3NmWA55MVsYSapcj/hBEW2vfAdyXUePLd2hZH
wVV+IHraI9unG8/1aEbT0hZqADN9EOM525qSH2qdCyAW37c1WQojYaUwRQrY+fCuGCEkSnAoJEAv
tGg8WsTlZplugxGJML27yUL7ml/uDFIYl5VK2FfqggduGnMjjs9JKCFY/w9lUouUO8Dl1M0a/R1W
MzKHMv8Kk0ma5l9WtHjEkCogX5HfisxTzkIY+nkaqrvuP5vAZ9pKbksOc2cKTbXcSQD9vacnfgv3
TUj+etl1eJI4rPFgfOkjHvq5fGzEdtQvRIUPaRqEGKaEb7ni8AjSh7EN5jJbR+G7ZprxjgkoXxyA
UIIJg0DfIZyWBerQ3gzZH2b5wRA8XsBivs+JxhX/Bs3r8k/SbuRqytQa2Y3YkEbh1E4XZprwEu+s
gzzvYZ+OU4lb9KEJAS9QP4dCCu7VtVd8ZTUjPZbQbU2w21PE8FIg5CNIfzt42Ra4ZzVtAyk0H8pk
AOVT+NPOk8icQ/LOQt1BL1s4AAjtmgoTGrDFcFQ3P9EeNCAoQP7PFzTSmtxuL9iEYkQA6I3XUUuV
QdgTNOiKVfWpwoKOI0GQvFvTjiFD+fBVwiQgwChyAE518YdIi9Q+Ll3OE07znV3anLuG3DK55J+N
EGY2fdn97g3W366OuZ4emw/IQC4El9Gh9IJ1BFUMY/HP7XNvQE86aXrq0vZc7/l/MaRP1tjNA8FG
GZ81/1r9QXueoIFq/vThQ5tCXD+zqb/7DMK7i2bGCzTHvLIIH7fKVaJ6xOmtFlYZlkar7wYEQKE3
AWP1R2x2C79OJ7Ae7rrcvLccgVhHmYnYIqwalLaE6NTKne44KnvBbJx3rJPwjkdamPufG0N8yEJJ
uz+hD5j62BY+q3tD4dEsdSfpryg/ZAJyZCe0kxYgp5f70LZTF1bu9S8HCeqJKyEzeZ+hXVCizqnK
UOkPDepK80nxzGQj04BClmkpSOGljb8cRAaFHOF32ppfCPIFSP58+/kcYW7k3ABBChrq12CO7luN
8X5Pv7pxiAbJhbisFTKh4f13t0bG4rZtVHLN7HezyRB2CMEwdnNwLRRc61QlNSHvs1QCzzp4vcDJ
pOwSXkVaPp2tO0jI55FLtJReQqGSeDNOB4zvFVPwkR5sAND1EEQKAnIfmLOupCbJ3K5xH90TqqA/
SQFzyJXbRxJLDks6qVPBSoyaZWSL/Jg+PQrwE5BKfdwraD+jT+vfRNAptvy7kRI7azGr90w4pTsZ
ESflSONz0Vi+8q5YM+AtyEnVpSEFThLEo6Vzsg3yrs5Ls0ArvtFYF1nU3t6Q8SpkFX1j1Tp895Sa
DMauVxmb4e9n3Lt8AnbuFrgRtXXc9bheSImhDYOPcnZ2KXUjMLSc9+ICwRVuBt++1V0139hWnlZv
xHE5o9NQ8TxmzZ4Xi44QobKUfY8oIjlYLHpN7/y5n/u0R6tlkasMr6XCiR0tqEpIJQdwotqkNBo2
uRvIuKFeW53KBc4NADjvuCwt5gmy/+RpXLl4jhh1Pb/9BVmpWmYcRtY+2C99esxEpuuWoTwvppaj
q3qlK0WP8uHr/GxEW3GUhGTKV3NIxzVMIWh0KJU31qTEJsxndZFuQy1wIeW8ZqCBN/iQXFEiVhFu
MBL0y1GbgVhph5n7+AfhMkoZDMh58cdw17WzlaQs3DcniElV5oUvRBB4/NJMu/raOLlhziG7dC0M
htodZnLuAUnwfYBsmXGBBsSE8ViqxlIj3CStFEqdI5nwDP2InEuBCzhK8sqsFicxTJuoNV1FHGK4
OIsPzDyAR1xmMxPzqQRSPNRHVJ7zJLcCxDo65oItDxjE59FNVG7Qu2+7LKfmg0vcITZ0FpydJl3N
SaFqrG2VbkSe0JAUgEqjuV/eo2/XxbNaX/mDpJidGb1mE8qZsmCMIehebD9SNFwAPVqTvcqlpmyJ
XhC97zx0sFUkzSe+3g3dCJQX1ZAKhY2uw9K3PcC31zuzN6CWKBehMr9Yh6A2aA3AYgpNb5Kb0eDV
QVmBQ26cwXRFEAu/JDByFk+qW/uw7vlrq2k/VPLodmpb6UdsZH1y75XU6vOmNjKScYnvPxDZ2Tep
dvc1Cb12CDI7Q/M9ZGxpLsTEfTsXzg2HzWza6tn8eypPfnMqeFke9P4EmsF/Aa8FsLge6PyeiKlS
EtbY8YfIPEVUzb81L0BYemiuG3Cttf80Objs4Y7LXIXAHDWuhb/4abk3z4b7FqJ7DYGNbo7CqC+v
BMmSS1bWt8J/2VIJHN3624d5moi0qO21ASQz7bh5KWIlXv8XhObqTtDoWSn6V7scFVycYOVCwqKr
Pr0WuLmsYmpS+S91JkpCNB752JvoylU6EPAp+cmI5O7GqSZChbAvSxtXiRwXXD0QVnnj4qUklvpu
0EIIFBF4lUCTAwhIlMOmwimKv7Tyv8RuFozhmABZnJ/NTJkguBjm+scx/47kspLINkdPOI6y21vh
4x19qaaYeYOtvfdevafGPvHFnvHeFhgXbmISnn4JfkfYeIzUwzv/l9qEUscGmkrUfWo9svYmhVtp
CdXrRS05DOfyOJiM5tYt458qi7dhRD4xIlmgd+Nqz554JPx/TOm2w4ZOkMvuGCSPbYuvBMtt3F3X
vEv7sfX5un4uF1d80BtJIe/tLmeDsk7JeWvjaxItZaUrh9iKqPCR6EWu2DsVhd7eFfYdeu2fNUHa
qgdEMvkZSLzZ220WvStDQzuP6sXwmc+P0TO3GELTVEAQp3vgN25zCsdAKIuwUZTrIrz1K70p8jiN
SBxlGydB2AEXoy9SXvhrN8dgPsPeerbWgZmNZyt06i1R2ZoS9X1RnnFFS7FGT1kRRqVdG6TJXtJO
l8OC5eWtqdzp0fO7fv6wCjfGyKmQQ4JU80A7tcZVHA/XKLyYkGST461OhSLYC1HVm3SPcMiF1WNw
q0mp8SP7te9Y1WnfyGbxPzp6sCWgm8YyLOPY2AnQNjA/wqcgvnrC+YBMxDN0sl1BpRWZ/yPoIfxc
epYiNDAHIG3z3RrcR3xMmYEFwa/XUkDVZBYEdFDg1pFi6/l6EY3QaLLqelsOp8hqxQ7LDFTc+wC5
jiiZI+Lt73F3B8tykulrsD6+E3D+8ThKeWSXAhexMx+OiTlyzzRFK3DX+Zr9LM0oauWzmaeqOn3b
XtFhKpEneZOuDp9YZkKYSDlFe8c9Qd5mla0hXV+FWAls6VSBjU/m8NDwkhZJNlGXIw5vwQqMiRlc
C2HTpnj02DbjreKGb6sFfu9ATHgORwt5TeFQXhnkkDbVF1OA675m8z70iNk0UYBBKnA3v/gMHx7L
wcd2U00u4gqThbKaR3p9G4L4asQZL7lRWv3t3E7mhqEY116yQwJf7FlJl6gAIcOQQqJad9g9vbx8
ErtyloPb5DAsxOkASdqeDeVBGxzxoiY5mCF2ExLbHbLbLi/clymSgLPrPW+UfUnmAaBxXVo8oRao
PVZH8N2nvBOcpDT208iGLFnC8eXwE49t8pxb1CNkOViP/tQrx5uzJStJzHHzWwQ88kG2baWE1VVR
eLUsS/nT8fN4/43X4uRp6iyrKANAuSiex78DV4d13xV/RtvQgraBS4uxHX4m8AbeUolaeYzcbo82
6AnrDPf8CkpH2QVuORKKGQlJWmqG49OFXo3I1y8bJD3jcufDnFGcyXn4dSNGHscmLZS5F9BYmaoK
/6B6k+qNZ77hSugaMtcBDh2tDjiy/eW8R0u03i8Gwx29APZOiIS8273PcTvp/mC7KjTWFO9DdS8J
wtsJgN+rkU4mnrIJHsHh8Vsi9T9mlQVe5N0DaWfztlJvZ5Wbc+UgPHeOI5R+19VRbLz7pRkNU6Wf
g+QIoZQSb6W8hNNeaghPT0wbCNvKhdHISOidBdJbONZMR1LHBr80POo52c5690KIqXpoffLMjU9h
EMsNHKhetg6QFV9Dzz3tZB5QCGW1ceYo8ZhMsKH1pkxGWorbGfat31iobos4yds2++YNxLlYkk/u
tBd45wMQkE/tjg2U+Xq0B6tLaTzVhGKpw95YcRZqJ/SlaAWKuXWzBEUQqmpaaq4PZmzPxhsUyUVh
+Uk4FK+bQX707k4T/A2fjOHoKW8CYXghd+SEhn6wfjW7qWk2+x4/RhOT/20+HQz1k/owX0utmJJs
Yo+38rpWYTr4KIPHUNXCfgeXf+A66znZrlj/7SNDwdfn/Z91XYSuNVzXdCnPjXk1bD6VwpiR/jx8
solitk/+iI0Km0yccXcPiV8LM7kQditx4BKnxtc5GjvrsNEQyTA7/hKrHcU68J7nURWr8G220Zt6
b5nThVFQ12vXxmLUJwwQDT6AfwvXkrkbpNMdWWLFgxx3Hxbd31u55jLOO8v9nkTwfe6MdF9Yc4Vw
ZrmFOaOvSMx1slT/gcA9QhgeKmFa6UdQrl/c+LigrFoo/ouAjuZe1vVLyBAjhCPi6YsVJgQTPxYg
acCCdO+smbVIXdPb+g1cDAm6mgVaJ3Q2zSH4WdoprPt+WkkQLPhvDFwHb8PV1k78+DNojMxK87nI
PuhjPzCaAiQkYPwAk2ANFfafsdqKqHG8l6+Qrm5IfZqq+TalV/PR0jQ2Wi+q6q+eWC1WNDdSAIK0
imAOOpiH4ritqGfF8eUO8K4m5SeBQ4ifz//8K5oJ1ZhcMPDnvrXcE4qiq+0mMjMw53gd5CK+sHNe
6hTjqjNCgj3bSBeSHKMQQninscoXV/WgiXFl+WmgWgFqsLdbrUnrsKLpW46jBZaFMfbteshJbVD2
Q34VzXu6MindmIy6BxCq3Ki48K6vOk/zYbMsqVHUjmcnXB8Bp8KlHqBwEtOn0x+WUbcoQzvSdoH+
NkqHdQrit891imWsRTq+1E7qFWuMAyjnKU3WfpgGdWxqsuK5S+3zsZMzxtX9pZE3i2ZxClY0sko0
JH+iTCiSGMdI9Bk6T39+y+mp7Ug3a2IeulDyxOzYgbQoHsYEUqMuG+0esXtpbnWZQWiqZ+oHcQv8
RF1PpIqlLUqlWDslP9Z7p5E1csn4ucUqKbu80sQSASsqAao0xfiPW3dgcWGDQZgZrJnOIYtMGFta
Q//wPsH2IIge4lgVctAMFNTxvhMB7poXN2R8QGESgdz7cKh5esvZPhjbrOhGvJjOz23UmNihpzyd
bjvLmBrJZE9EY1sqpLE6J9QhJvU85/trpSkzhUt0Ho4dj7mx73wSC3PRX+lNW+OcDtDR+Zp4aSN2
EjPhL+EP5Ju1swo84N6GpUS3SR/BkmDjfF1aEr+HbanU84Dx6yZEbFKVkMolUENzN/1Sy6/k+SBb
BpVgXKe6oggSsAmnI1aqulwOudXWERo01Xy8TwPXeNMDdR1xVyXaBWXAOF9DTRwFGdmh1edyT2LB
Reua3L9bNkSemFhDS/F3xuNSxQ2IqPLkPE6tsCtDAUQC1t4uQGL7aSsGu2xoLHRHLrZGJoodf/eS
b+gp6HZWk3WndCEVUJyoJK7O3ZVg9PhfrI0xiqJU9Q9dC4I9Q3dkrDHMgVWj9+ytZ8yJAqJEDr5w
qbMxVpiEWKT6kxkB6Tr+m4d1U2jwK5EOdwRLwlNHrDbSc2LcUQz3/klDMjANwr0uFoKZRVvBZLd0
IuJOAafbdnza4muYa9ttEbCShx+Ov6eRp/jONHEwlcBQV+3orB+wMZxRmvwJSWFCQwSIzWr0Qn6X
xpGaXyRM7Jb/8+AyZd7lFmfdBmj6BA9XQBitpolscyIDZDdRRChbERJ8EXqePok4ovxH8BHbTtKV
0hMGCb1RZVYq4H2O9WRcPdMwn1pp0ywik1xiY5t3jAFR2hS9an9Ps+2D5ZtlUpG2GU2ZGh8EPe7G
h/0+xt11iIyV27uSLPOtYglCiH93Y+O7EzKyQO9KlUF13IWSb98CKjmbnPmbjvIDepX7EK/vXeeU
H1sMnM1l4UdNJCR6SaTE68GZyHuPCZMBQmF30iyYzmFSsdK+pHnZdFFZaXTDG2n1TKy4Y8ONoxax
AG4eJVCgGS1XGDjZeD9wFEpd77iIfKNKKRgqnuRr+hAXoaQyTI8WfNrt+frAWwxPGzMwAzkWlVzy
dtG1VU0eZyAjdv/qUzjQgG5Bak9jnL2Zq/+77lqoSuERrc3j3FydfaQMF3CDE3Io6AhR7GWBbnK7
T+m+6pWg3sxGhiorSHpQAZiwBzAXjfSiI2klQhv1z74hce9uQrSLqlj4Mf78HKailx/HuLvy4TlV
S/+XSawFRDLOsoabi9+kEL+w/JDJTpFTNPHJm4J1txgIjJz8JPlVnFPkfzb9+9pUM6NC160eQtg3
Oa/kRBZYpo6f5O3yOVclQqaFgGHm9ypSN481WEA7BzA6OEmkKnT/5Vows2aj/t7Cw4I5rtRWkafm
PdzmbcMombwotOe0lZUj7kqtdpTFSPaPTsOdlqKBG68t0riOS9udnaSgpJk4cIFJl2H2UUl9SGIi
ehI96DAx/KgIbgXJz+lEe9WnMBt0kaUOk2dw5hj33k+CWRF/3nLaN+6NnbxgEJ1/eDj7PfRuWScf
pRkiDjG+y15l+WrJdL2lSG6IIw5/a+h8jK1/fQEFauH1ewykx84MZRNYqtaZjyXjE9edh37Mx1un
QHkUMCSXsRd2LIadcCZlc6eH4rhpkOUI+tsDtzK0nFNHNp0VjLlDixgniisXnnUpdMfE8rsyd9CK
B+C50PEWTowjjp+5QGOmQba+8DrpDJecFui9yma/2FrjHYQLt7Ewy1324iBP6qhXLh8+mP1R0GF8
D9WYpyePJvr/pMLkTKALSjNJe6ta9o1cxCfAZKO3fqClS/WcrBH5zjFh5eOnS9lbO5BcREHBWLDa
IR+Nl390fBKreB4/TRAExA7JUGj628oaoI7NvjqLBL0hMwmCo8IxkrHYjY81uyADHEoARjH3yWNe
ZXaXM2bvy3Jvqt27kdpkV4R3Tu+Zt84X+F1aXS9IwZwsJKU+/5mbYUOGDS9Y19/ZtFZqVBloa5Mc
hgEMEDXbrOMiZPWmnzTrN7kh0ukGRO3poJgC/roJT7UrnFziqzY5Xp+iab6T0JlF5/yllWpsXmX4
iz/P+OnclnOSFUO9ZLevRbTAhIt38yCOAtDxyEw0gnW7P6hQyNjdTE1DRVMcYOfqG/wCn8BYR8Uh
wJB6q0Umc9n9jpLKPxKHocPtDpu4Va5l+Dse4sYNtm5P7JqZgXJQXI7IVOsKbBPKJWGcVCow5NnN
CvXInEMeXKOphmauhq+b+OpXcQoSEazOR4VpKnuGcUVfpF8fXFxTq7tKNppeGdipPd9IP46BZcUe
KaG7uNAu/O45VYl4sUrwhbgDhSBoUJWAtfF5C4K4csOfD3dtqUZK1fvToO79hyBEaJiStVA/5LaS
JiKLI3kQJORM5pyEN6O9R4546JaGquMGdIxgbPCEDnax4YDLl+eFAjRoWJbf6D00txSb0yuFwXbn
gnut4SyJOSFZQTkTQ7Hp+tqE4SHewB/tCGL/5DRQKsYgo2+OBb355paBJS1UAl2h2/tLDzhbsD8s
F/VVqxIItTNg9ezhBZ8fbdDYFIU1iRomgiuBNLwGEiaRpuBWj4so5a7t5ZIO3FGRANMS0pN2tGwd
OqXB2Wt3Cqe/yPPM4bBXmLCJXdTy1f0g8CWfwgR6thMGIel5xWdRzqvaNzTyg3BrmXh9ssg/Awf8
gKlE1BUVdFb80ewmuF9L3jko6gQoVMrvLQF/T5OgHVBSxIsjBeS/oCtaSu57yCUwICoLO5455uYP
dINM/q4PiQoHWDNpTOJNguQWF+GsluO8z3KYAcSoDfBgPLfGQTkk5f0P8/iGOo8RWjZH4I3hU3FS
dEWzrPU6T0Yc3k3HBv6ZxUoz2Ju6OH8Qj/V/PbKII/GtUKmEltiB99j3pkTmx0YDdyUAShlyIYUd
h8l30PIMUfF7d9uQh0+nQFWcqhbD/8yEZUjI/mhcYKVKj5/gFAB8ca9jLWAPRN3+QQFxug6GzNIX
4YNuYcLVIc5uX41sFgrygPgk9as33CGJPCz4vnnwABk4cM2zrGvUpFKtVTdifoq6g8c4K/tnMduu
ZCq/ynOpTX9PptZPierNiA2SmGAzAjcpEnfHGlsMvPxuzec30ARe9i2LdIbgbASpEuY66M4PTG8v
d99//GOGCrVPjLCk65KAs/2MP40lfiDT6t6PGPkrghVgX64W8Z3BubHvYCKf7DmSYHCSJzubPzGS
3lvswxCknI60ZtGScZTVo1JiU2/2+upPW79D9S+lUml393N2rc+jf19LPClu7ktvCayDKBx899Wn
cUMJ1f4Hry8pK0nUAycW1pd4GgAupX9xoldMvStJkIOKjXh/SdhCh3rZCodzxYIuNSUeXwFzvqKv
BUXdB4vtojFhziW2QdqFihGCvvAOOPxSg0VLYQVQ+gZuINCSik2TOennOdmZdkt8HTXMRcifWWt7
FWBmoIkReCGsPp9Qo2Zz9H+gN4mT/U35EcPn5PUHsr4N9XwOl/3eMV43HyMfpcMzFoih7BOCa6Nc
QytFceo9/uaIF5S6VZIXBDs8QKYLm4IbFD7rMKFylPeFNS45UdomxBu8RJ7AxZAOeOhnOyQ8QYQ7
pA17huj5Fig9vHiIzfB6kY7ZFnQ7vB+g9WiCfED0tXqyBofLG0VkSqXTq8y3jWeBJYvHewGaadJj
SHxYxzRoNHiLjh3r0wKFQ0nlPlI5WGY3zEwC+ecN7jNxYZWZsj9Y1AqS6YegJprsPOVs5UINyOno
S7almxJy9AnozvkHuv8gf6eMBTyBn4y555SJp9LSVO1RIV+135bQyTK8QrGYeJ625/YUM+mY28/y
5E6fPSD0ZzD9FkcVsYrqpoFXC+1QuidAhoEVvA2SOi5LkInkX5mH3T993BOf+jBmim4TQOlOeY+c
125dda/CoOq5cSruj87l9Rkaxl25g0N2iYmsq5TsM1dInUe3l3H45IFdJKwBWDutK7IQAcglImSS
lxtLDK/RXPfWHqIfGqLhKB0I4dtikQlwOgUuNG0nvb0XGWab6F47yoUN/4o/qkPfLtLVVz8MO2rS
KAbAe8x2gjteGinhOu5lyxj/SqQRdEhAxP6QWBEhKsIsgqfdRSyQJI4J6M+DExqMjGyyYtymamne
SNQetmkNE5uOpMr8iZWFfAXUJaJUNeo7ihw3AGrXh+c2dOoa8Sxa2c34hEEjd+IZzvL60TrEDvkZ
Zdx86lUTMbedEKZCp2VPblJwHZg7ww2Tils7miuXzog+wBRGVGamQG/TTl8vOzPoglUTd7MpQMzi
+BmdBUXFE1uKZreJK0yAz9ZB3EjBEjjQtrILWhEVL6Nk5UoEDDqRkodGlyuQ6I/Jv0BqIPu6qZEu
AzGlEBzphXRCUuAal57plxDigzTssMDyu24ZYSmN9Tb9VzkZ2kbyh5FMpLQqZeydu0rp0TJbSBmq
V8lh9HDg1Lo9Xg8tcSlMKDqveLZ6FuCpPnYNAhopf7G49tWHqqF61xP0yNDWBS/5joMal94WYGB6
aBnGBx5sP/kJksKKrBlYg/d+uMCtY+UU4IFffcp/JHwl5mOPeprHavFbCIvnvF4mCELsf9Bbh3Ty
RhTasa3JWxZwUMjTX1pN0iFBH6sNo/MnLeS0vtU066CS3eZwOFMn2goOqweIO4hgRZnuL6YGiGcL
AsHaVvWAu/zHF9NaLlm7oFBmE1iNqO6q+FUY/h0Vw1vAUrLm/tswI8yvCPAiX/Tc/uuHXasPuTmz
09tIArK7c988xJuJO19w8Z+aiL/F6a9zY/xnBVtv1zCTpej17xk1KbsgjKHS/Xjpp4LVsJEf6N9b
lt14JgTEKaqMSb3Umx5H9evM4IotWFN6Q2of5lOkj3ZItZ2N+tVq19jedoCOmIweq+I0LLTG4HB0
Mr2fNIAYtM+rM72i4PsE2eNK9qCJZ92/gOP/gP8cNbjyOp+JZgc5+SPuHdG9kT8y85oXiN/hrL6m
43tna2tenLyDTdsBDL1CYu2EiH5/1GsMcxatrk759Wsk9lGv1IJOmgIFx+kBOgGynwuR/u5xJwo3
Vb/mS0jbHEac7QoaEkp/UV/DBhNe5lFcHjUNffnowq3qJ+AGNbt8ShNCQQ77m5gyHbwbsrTLG2zh
c/YUVmQB8bPqqFfOEb53Lub6xTz2ktfPY9mf7E1oqYA/GBZe1IlhF7zNzrfnW7/7GVqDzZ/S5hjN
R9Rym6P+M7FrARileSJKBL3FtzvH8wD9soN13Q//4mJNjPRg0TqS4S3vocITCp1tFZ5cMZ9uQCvS
cTUaWjTyi0l1v5cwsS+cwQrLzUpiQF4mAZgQGcAoInAibHxdN2gPpm2FhqICcCJXPeC1xVZ723as
iOM+ZNsT1i2sSu71aTwKUPO30APsBjGVOw9E9VFdjpwKNiyOpprsi85Ypwt9WnzOEZiS14R11lmy
DPHj229YmapnLlcUN5Pfvvf96vQfVKZ7By1gvLn0REKTVPZnO7QkAMj0FtyOtoVrhO3umxHp02yq
7uGUWKvMhMF6euh1WOE8MPcdvkXNXZiNwPoPLilp8zatgdcKcTkhULbT6WPGHr9TduPD1S/IDRpK
z6NkfwCETMEJpQag5sQe1EyAiXvof9B7xVsydVSMNBzD4CDUteMZqkOIJ7YeUJcqNeAgY5ivFgnG
y6Kf/oseYj3iUb4R7EPBN/gJ5oQOIURapCUUhwh01Ne8qrqxzW1Kh+RM1JvpdYhYr6lbI1VoM7QY
bSBKhw/GuQrfa+WlG1WIfb5q65FKPCQJTAW1b6GDHx8so647NlCIaR9ofhOjkG+N8ef/QeIH+p7s
zcJa2zZyH8U4ADa2YT4eBxuN8TKlBOSQVi2N1mRKzP8mA02VifErXOV+XsG5pTtKpFU7IMk0tnab
gCHMQOVvxV7DYpxPbZtXgMbljIK7vLbUfe27kzCcmMF+RD9IxfH+O8O80waSB5UaOP2HlGFWT3oQ
cyFOqGbk9gw94jeqFsUZRwcZCyZ5uSNYkfeyX1HxVU/zpqFayKx33Dzw8CiNvsVSkKQ8I7UQp9BM
INgAIHO4ceUTltqdA0YfRR3Mj3bkrgxjrmDgjRG5SX2NLxGNxcxXKFvefOFARTUmu86bFHM7M+Ao
MkhKahSouKRkiDlytKm3GTjvPogTPJVWpfFqAvG6XtWD3O8YI9zo2TF6XBhVjFPCv+AQB38RwQYq
l9kCfAw952p0bdoqPdd6lV0DjIN0u/yOGMsJ/Kn8GI1ecM9JsZL1rzALsSYzXZncYupi2mgwSK1C
ek0vFp3yPVDZCb9O/yTJLmeIvxg0dAkAQIQd7D5hsPNmarfrvcfWsZI2gTgFedludWvmgC0dcLWH
oSFsONjxXdwlaz5S+OZS+AdOmEcmA0BXiI5IgpuYaKKsDFgexSzceiP46MFooa3jWe+gx8wT5IZo
Ng3ryL90UOeyWWq2gf0pITy/IbvXLpuXje/IVok6W14MRrEVoomv7VXPsYGvI1/6XQMrC1YFeapw
exe5YqM+KH/IS/SZQAoZ1zlRWziWOIZczAtixatkhB0BmzMjVW3UTabmm6SGBotEbWGt8cxJKI/J
5kH1Yr5ARL+r3cYDPU1Pnf6O8a2S3I/m6YiSX+Xe08r3BQX709KMnps/jrgVzgin2FiWTcorUoZw
E7HiV50jItW2XGNq/1klAa93vP6F5ZTDvSbkLF9knGaFYLHGEepTiXE/fFOqEMj8Z+ftQ2S5g13I
4l7oOlwn6CL31Hp02g+uslR5WPaH7qVW35YOqsAfyLggYWCD+3jxsRSwcRmqIJbc7phCD9lkbS8z
50u0kHBEjaVpow4+/SY1ty5cTXz3BP4+o8CLKz5E409SmjT1sf2svlME4/fJ5nKVYFgNyWCq38x8
Xadv9Wb8Q0xSE5Ftp6YtmZGrbh4YNf/9rk/fvoFery0cSald2FV7Z357Vj0Co+jMfWs++HLYYBY2
K/UGE+isFfKuUdnrvIzjceVFQQm6PhR0D+gKFU7HbukWpa5hA2aPqEHI1e4vbj6x2TrPNxXgUqwh
ezw7sR+HrMKBInFnD3hJTiJhw8MwbXYOlzd99ynkSsEp9eLtDeP1bBx4bPn/JZS3IVQMdmbhdQs8
UZxP76ac8tT/yr2cEyxcN5A+j46xZl6PVyHUAlTor23tQcNljTUlCvLKSFgM+RB1f49jnbS6zKpB
Dkk2E3HCVFX3yw0ul81Pjl0dFyo8C+83ufmaZ0j9qUCP1+WclHlKmM7MIeC87+2abB4zd1h35JX3
IoDZF5O8As1e6Iyutn60k+m/dTX/BNUKojCpx1n7sur6nQoX8IEQCQqaFSgKsO8I6qk2Q4/7SOmU
Rug0ayjutFZKGfbdubMwa1SCQQ/ijsw2/8oe/ZZ88ZFjGqiwHEw59r/rp8Lj5QLs+uyniiODKrja
kSlRoU91y7eX3MXtrPzG7DYY23gi5p3mt0Yj/tVJuezutXkiWnyl42402fa+epMukkwFiDhRADac
btjfIZ64XS8g4Cb0YjjCnyl2e7ekPBdhCQjgJ5Z7Es0FAXAxMIj1qwapMHj7/YS8gCIQQARRf/gH
N4AN8WKzefQhLOc25R8TQ0S0roHA+p9LrKTLL4Unj8qAeIQG/6V42Vv6oXFxwk4Xrf+vAk6O7aJg
z9jCaIHidOO+1zVMJolqzPXlP7sKNtyTtkTzFg1pCoozXxq4kLxr5L78LMFIuRYDUgQKvztk+6ov
XUIcwwII58YhOBMRn7VMuyZJWzO3FEXO/jGBWeaSPaTf+h916/QNSIKPnndkZf2dzsZBwk79a5Ap
mBvp722CEU9oa4jeVGUgK84+BvKD6wsioBGFWQBWWUzP9qxRmd10eF7cVZrE6J39FHqH/3AVksBA
lplKalOOZoh0r/wLs5bcTwIsDf0+7FBmxSd3pYLYQDNml9hF0fHJnSWaMklkrfXXCGS5h3DjD9oV
zFDBCu4GYa8hBefyR/xbl/7IlpkiyJWo3eQgDYpJgh2+A9lhsKxx252Zoyuf0Ch416w8Sn4QuwS6
QlGU9mQ6zBSvk//q19Q8cIBUMmdiYewXH0sDzt3GCL+ENYzrCdded6Z6Iafxz9cT906HEAhK6OOv
JhTiWud9iN7BsbuDh/4G88bqJJl2RrD/Z6C3ClGOBa8xQ6g18vDJuf0Tqqxf2ZdY7ZtvCd48zp2+
FotIn/2TmKYVGxT50ywilm3NHN52DXl+gwcX/EEh29fY+d3G2qx/Ll9A2LXoN+9IhBAsYR65HMTN
4kfCcaXVGHsxi7NB1zPXcqJNEr0O5sg/iTf6BxVpR6FDeEfvc7rtUspaiJJG3BIxEph3tlfHJHjK
cYpNiGNLd/bEwZJuC+XfU2twQn3yNRdJc5ywMJwKvlGYd/5zLd3lktXQxgAfWqSn/v4LssN6FVAB
BHMP6GpNVUKldCBlPUrhtQwSx6V/ffrZwr13hrPhNQgDxIeSnPNf+0bCJAkp8uy7THAvxkJY5Sb/
kKRaxJ99Moy/PTLVqB5ymH99rTPWMY+ZvykIvmwIrliM1Wi0G7aoJPS1Ga+PVHcinwd8pmDQ4usG
abu2jAvcIErjUofezaU+oCrFJrU4lqhiSHP1BrblBTkrB0byyattKmmO4LObMbjy8PKiHu9EgsJk
Pmsw5qaifAiMZEACfb6cusMQ7HhyLOXyBTeZJ/4FOWAez/pyjp7ju6GisB2S/2ykTDg1nRnMMjq4
Emg2ZozPi6KIubWZGAxXk/TUSuL5e/0Pk2YGcTMzR9QJmQMzk8hl1w5l/9GKggzSZcA/KpBKuDpK
cqNAoOPYjpbOevB5Yti6jibIKDIuIE/6CRRHtq35OcJcHIYfWKweGpEkx+A+Sbh4HXC+tjsKPRio
UqP+fDAdTP4AFVoj9mwRRPKTm0CbtL6Ao+FTY93yYG7ICmOGRbuDkKFxbjuBKHiM8lMgnGUGf/fR
yLsCdVl3ZmJD660h4d8Gk1LarPTh8GQ1SYNWn0SaciQ+nMbxsnczRgCZGoNguKwoBtRHFt1vnfij
qsXgygS60iKOiUlOYPzGUU5lr2ay6RnQAl4gzvgoxBst8cZgrZr+ViXWQbxVOIskZUEpc8T5o8T7
bhnqBfO+17wYPVCg1Hfv5YC9VoZnFBk3DA2dw0O0Oigq5fY8D4i58f3RoxtpUKDK5HVSg/7hgzn5
D8HLoyJCweuqpDa210CdW80aVIxwe6gdDCtf1Asgm5Fc9OEKyDeXW1YMQnEiPAjDCRfPKWJ8sZa/
DWgWMmpwbU88ebPEs2791pPhjbokw2QiiSLKxkYySRtBr3wc8+nrZa4QJmNKeQIj/k39QEJI1x6F
w1Fnsys27uAGcXfuuIaK2X0wUYg6l/CRperh/NWzA9/KRs2GIqp5cbnuwIhmpMxApvVOnKmLcvbr
kg7N3gbJqNdzsOi6o0PLwdpCJ6AgAN2n9tJoBvuMVf9IbFQ6IHNQeVfEyC56mZwsoQHsLtaq1gKl
9n9GGTzk864qZDX6OftmMnagIYaqQ9b4vtsLpBATjB7xl6MvxCXaC7M7SZEZunryHSz3oZqSt0jl
lqRi3AQClBJBqKpVOVGd+iHYUJgOh5SX9r0dHa8N4Lhn3vnskJIiITMhJfbul7sXL5OcDGpojD1S
wc5BNzMeOoP7eo3jeZ4kaKINxfGdY/vcxQBMsXkDEcRcjHX/NVRIwwopMrC/PLdgEY4goonv0iSH
8fwxNhYmC92BeYwsspsAuOaidugJSn61BgeQUWGUGtDpdAOPb801bOMWQPcGuRF35U1czQDKG9vs
aSCTawlZMMNPoJc//Z3Z29E8LuBqobefMknZ2Uh3177FNJ5lqkZSbCeoKXQndTd2faMAKxAAr56D
c9RO/ur8MPwbBgeAlNe0m860E3PATfOsHOLsiuigBXuc3srNJYySrGZ628uC5n/oQ9M2m8RM/hFa
HHJuc+lA87u1+TNY7Do684v3g5jddNjkFZuESoiD0CKS/p13nHEeynN3UsP4tYet1JN0q7r920VN
2iu90FT94rKv95Ape9lIpPNZBuCzcT4HaQafNMTx4Il9WQFPu2pMBcpaSwCd/kYQQ6+dHi9QqRbJ
QbR/HjVHXNrjCCBIoCRJhRUgesT3j1kKjmV7LacYtgUDfmVY9hZwlfJDNIgKF8w6r4W7I4AGgpXe
pEc5zXWUzVuHMu1CuaCc7AJEI3phJ9ISE5tLgbBfKiVRiqi7Ab/ZCLAtF55YaXiMabbBJfmAHGld
OU4/hQsE3AZ2/DyeOKHkNSJxq9TGFYuO+63tHduTIUBY+knLZVlMI2SF0PbRBlduyBJ7shrbnMYD
mK2EdSPl0z0d+9CMU11jeizsfNWONNBzAMPQro0rDK4zNyiH/VPj+2n+78HReEplAbufqiFDZpzv
XROiDMCP6VJDc+wQWka3UsI9hz353ivkDzmWoAhiqmKFW/TUrGLsh7At1SL2PiLRYFg4plqs4k6V
+7WQv8+G59a4XpkiA/GnI5jJWBGJzv3ZeU+i9oWy/gaEtShiMwsOXkh0aZrxbCOnAPq4dpJzgipp
/HQUYpZMKeH2aN4nUj9GkhYfhVjrWz8ttu/zlVp5bmjucIiRqDSlM2KJxMLaw1uRhz24X55zz1fG
9RmLWdtgc08P9yIucUzcb9ErS0YLzrbrngU4btRrUQ9UY0kzBl/65BxbsoQxSqzvRWShr/foQKt7
ct5dnGd6/OQRu2T5JoCwdAuBAu6rshuvRrbnsob0izayB3b5dFdcWQ9DzCgV09coN9Rz0fvNd9LM
CBHEjJ7dMqCcWFtK85W14NzTrySE/7wXP2ph+z32TEGT0aWI4xUHa3525kn3lKLhwHYl5dZNTIix
n2nc2st8BrI2W19vA1ec9xcbqmT3AziU6HbDuQsvWePuv1NcOg8FR5Kp0AiBPJyXziDv5Z2mIL3U
CRGYcBbeQOXdzsqhVM3F5sjbjULXJvWnp0vN5BS9b7qKZF7tfXsHD8Hu2RD4GvWC/m/xrGnQYSeD
hc6/1l5ftH4X4560bUlhzxoGfaHHi9dac41KhH5CjpqQ6p442X1ra5Ov3zmEEXqx5BfXnTxkrHWI
fFLYBQgHg+1MBdM84X1vUntRarDOb/hHQeVKy6P0qEOmAyisTYuniMn35qe4onShSQEi3vUwD0S/
Dem3zANBrCiYnyXU3RYBjCYXbj597hw0ItJ/czgNuV2hiDTQxdUrq37TdWMYBrivvbMcEqSiLd/d
jAh53Y2Yd7z0Xytg4U4wyuuVVxtTz9+/rnv4Ue43ihBl/TZdziXUBYMYnHkDskq7pubbi6ClRBZQ
Po/gTsM7NcuEpAai6dTNRNqknzxaH37vVZ55hPuusg7ZsED6jZKli6G4zYiAdmON8ARXnuUC0++L
PASZuoB6iIT8+Wx87FxisFeH9t+vbE2QumfjxHMtFSlAy23p6wLrLS0CsQJOlzOYZW8cn4Sp2xuh
H1XoMsfxu1p1qSsedoE8BVe7kscytdmDFXfR8XJ7k73+WJqC/OAf5zJbyFB+0rDTu+ovwPMo8kX0
gDEAR8dQDZRHc6J6nm6wJe1HMvLVJdB4v6IEwVmz/HgvkKNgPSCjtngSAvogASe7hpq/zL+ti+an
8ab6nUj2SQsfn88RZ2wpfKqBR7kGO9U8RbmQTBUQXZhzeZTY/mGVG5DaQ6x9zydbdc7uQ/rxfkmT
aIlj0ctKRHJB4GMqGiNQGRPmmrYCwYMQgirEE91Ue8I2v3iW4IuwiE7L2zlHz+AtesltjmKjeYPL
m76knsSVrV9ZvtMCCQ2TwG3VWaARP9eF61HTDa3CbcAA2RY4vx9dbiyItRGLqFddsf/H8MU/xFK+
S/NAUkX/LnLfejtKkXgF8tgDUYruKC5bNNmHePJmIdvoORU9de1kJdJ6+GENThcV9aUo/11WgLCP
rl4bAWgjmwfvI1Dl4wUMwq9qFhxUiY/KolPzb5R/W5elbdIHwW4FRPw5jOkde8nEG00n8ySlCtyG
aCGuJ4clOt30mxOKjVW0TwDX5GX6zxAyYL2OAG+F9suSJXucnYlASrBBsF+y+s0aQStzoi66bajd
Zt17kVg20XRqzZTwwfl0fwq4tv2NvzdaB4mtVYwD4vkoUDuk/6U8kfN4hu3nzx4uidA1rb/MOjKB
vzDoLEnRbRKAw5D90dSMFb79zF4T5q//fNcTESq7K7jqie5WqaD/3Yi1ASTR542uECF20IYN8KFt
1+UCYI+/Rm5PJo+HR3IdqMRmQVRAlvlOq3VVjgGM8EPClNPX2DvTZHu8yVmpnihgEcNwYfWFHjdM
4m6qimRDo7GeftMrq3KmsDx3Y78SISxwLtkHX8DeFxnguZ4pCbC/+7IaWZPFtIq7ccsyY+vDG40U
ogWKBtkOeW0WARdx8Ow6c5Ox4LAlViso3B4pfEk7MU2OzdLxIjm73E+yh+hYHQRjYgAfJNrNmoKS
M9TDAlPvOm4DPaE9u4VBORiiFPKr1eLj6yaCOpRtLRrVY4ZrVBeq2cCn/PgMBUPVjWzGskSaXUNl
10eG4upyETGT0tFhaNxrj7uJH66agePmFsbZPr6gQDG9rLnLosqbQv4cjS90dvq8D+WhmVnNlBLz
zBhiuBFT2Ph8ljDan/Sa//DBFYa8oi9s28S3Zo0AdwPJQwotu/OrM383UGbd5/RaHctQyLMQgFzD
U/QYLHTcxf3UGwb+m5YCQ+ESnyeQ7+pdDRDkqM17cMxUSbVcvK1PUL4M0DhFvvb+YUvOHVNl+9vI
49DsH6gnWlNhUdCUtTucRTehg1NVqmOKaf2dvC1AWBvZWjS8LTEBsZ3yK2wooge4cKJGlde12ATS
QQdf0wLmVvO6ucKqNVwORzO6KgWV3A4Di9XsNHzJAkbehT2w/BDAV1ghSjJgu7yiNVyw7C0OQEUC
bpKWYaf+N4TAX9gGIoGcZZ1zZon/0hoqs3u0NxTO6Jqp/aA6dHGsFIqPVx0sH+ukLl2Sk+TP8I4V
nncZ06Vgu7rOIGn3cLOmv2sQzt8kz2foUI2C2SvHVTut+ECpERiulPA0McekRPspldTbhf0JpvK7
CDJ4HzSmPX748awMttVpzlWcfaQ87/mcRdmehThrVq1mevlLyO1U9skIrO/EcXwc8dWM4zgFoYKO
2rL8OERphMMJxeg8G5r3xhzP1+BccT2k3UBPv8g1rUAR3GKVFWZ6sfL6//6m5T3imlYxedvHnKfr
05R2W/fl32bmF72O9+uXN6CybrJy6v7+I/KduGdDK+cMC8M5aniLTabX0s/25fCAGb6YU8d9i8vJ
AD2sXXFBFat9EQi/JxPwKQere7x/J0wgL7ZShdi112rN4GM7vBWieE4BbSfNLqjw8d1TmPaObxBp
loXZ1ZnqLTB1c0uIyNPN2G7jAj598mDBLGIKYXUc4/QFQBbu0nItp+aF2o5js0TlF3j3mqdjVakh
QV0wIc3VRdEeixF0kOgvlgzAbja6GF32a2ayVny+0flOQ8/MxDgANwjz/5kFggYA1iYeJ4ifNSuh
a+HuFWcyi3lfE6uTojgFpPBWHpfGDW3CWq3sFzpuO1utJjY8eMUoYtiY9tMVHN8N1sbcX/OD0ZTV
A2EkFfv5hgnBqoMDIDVUFg1T49xa8sqABC9vA9dp7aBqdjshtkl4cftogdxBjoACV2Ab47eTnrNX
imVdFdX41tKUmh8TFTqZthereCqYK+C30ufAt59k/CAvFYaH6vLitxUglpKH1ore8cqBQyNJIC2z
WVNbZvOhcn3MpQ6xFX8zDbE1l04+c5JIoVXlS/s1yRDi0d+q+mqgBfWToJ5brCEJHvV8zoVRa7aY
Zg+f9M0OJ3nmDJtyd2IFmoFh5lP1mbBN2idI+RpEmY39UOrSvSNHfDk4Ym283nPIL1F97pCOE5au
E5pmI7LQlEfZKzn9ceaXI60Jhhdh09nSjLnW9WSHCoqzC79fswrMu5QizymyApTWbaruySi2qzaZ
KyjZWGc5u4k1Kbf8WH4kKua0eK4IpPLs7rF5WG8xwT62mQYjvxw2RDlb14Stt1x92PQgpBRV1VxO
ZlKWHnHi/7//pyMlhheCry31R/0vTyKbnLGLc7caZh7AlzkeAIVPNnvy9WO5mo6acHsorSX/yWph
QKqFJHy4fZi8YTn2dm4exrJdgGjXkZjgjlFSKZ3jFTTclXo/QZRhNujErXxWePRSKXlw4/+38FSZ
tq3BfACboQDFw4B/Ehw3oS/Pfq+AU428w0H0tjtNUGWfFoivEgnsX1Vxs3d/x5+Ruf/KlSogTp8B
SW0wTp99qLcs25m09vRHOmglwdKZQX6CRAXSUxAfTQA77qBhTJVedAq/ImAmJVFofI5ganvG3684
XbnUosJpbHNuoS3n8OPbWYoG+5StdIVG7MluiI5emYLdBRUfX4O4PM5FGHbICIqbAXLIGFDobigD
2pQYNJun9xq6U9miTfOayecgWTvh5AtHLWRJ8sPqL5oe4hAfQdb/Rr5hRi0aod44cCThP8MK1lbt
q+blOn5WL1zE2XVqn/pZiJo/Ckh1BRDDvyoxkKA6wX4o/ZCaMVaqnQ+R96ZvWYosk/FlpHkcVM75
Nb2F7oG5Zci6SfZT2xWqdR4pzgHtaQsXMINNTYwzuDsrwzSJJAktspPHHigoEmcGk/RkNgYJ+zHr
cp1jFzoY7FAFg6JRYZh9Hzvq+T70p9+uAkbQqJXq/dZlvWg7/we9k9LrDHlMyjwv0z+qxOyvkhpn
McsqVC9u7Xrq7HIDqrhwYclfNyKOOTyO33hBk9Wojj2j4w9fscPWKXRO9FnBAhErtg3+oqSBzef9
FzkRLfLxvAR8uyl+ZvSLL9pfOCird8ygljIZmouNtWIYuuKcXlgxh241tHaSK621MNDyPmLFb3An
y8Ygpm6jyS3w75RAPgEOxALzUZiQgabE2vh0Oy4JRxQ1tmiCD9qfgEtGNC39Ezsxi0xWiKfV9RF4
I4zk+j2e+00yULl86rlmdAYYuKciN/Alqrif24C1dzlLrpg0511Pr3+XAzLHDhT51Vg6npojXtFC
ngguGIWn+o5w3rZlJtzrRuvW0jWlKVQfYD+XL+Z+qR367b6N2ioD/yMwZbysLSQVGiAIQSmtgnRX
88jVbySypP4e/1TWvI1kHwaTi8x3/Wx1NOOXm190YuKb+9gaOGICSe4IkjvWgTi4NvwC1dFGXLAU
rqvDltoHPin/djk0Zy9Sk2omqlpwOxCqwZ//rz5v/hkX4IX88CZY9Zi/vaGjVYXixAIJBw+ndC7S
3q8IqWsELNlPfjPPeFlnA6hqYpTdUsyspiLMD+r8K3GlIGRnwMnrswBtw0+RvjyyS2YzIVj+5WMd
JCuPqAGm2f8Y/XirxfyeKFgAAZMDcQWG54QltMJlgmXJMIzP+NgnKbPlkuoIngFbFSUhDovyZA29
XsLrCj508uKsAEFcFc7dF+KqJvGUR/asQ5uB7+tatqXQTU9Vf36qHqO3gbQ2Nq5aKkeVIPT9Tx56
dcwrrgz3A00DuYzsPN3Bugk3pCJhUyKz9deD6TF6Jiam9wyPAA5hmFZJ8m+LnVTdCWFPgDCIbJyN
DHWwxsl06cIA3837K+2hFI+J5BrF5ikJmac131tX+hU6PXqBHD03mlbCNBVeBrLkjdbURAguAaWH
ZKBFG16LFc1PXsyUml2kL38X6MBn1I1SfEIDLxhNFs2a0aE1dAoAG/rEsb/OJaoDkLwQORIOOXOQ
snKsMCFs/GdO6sZcv9OJpmvYlFmdIrAiOIiTFPUaFfP4GPO0XQ8lbbKcXCAYWGk35pujaKSeRhe7
i8TovTSynYglqE6EaQCP7cD8GXS4WN6Xjvhy6Oa4vV1JKYCIkyOibPYjIGdwVXWQRtcMmX9ZrAmq
OfO/n/mNdRHz5nbyN9lbEteazBblaEL8Unm6jOnTqvuHCkmr0tE5Inxjc/a98DCaYLyX4XS3C6SM
DLD4gViV0Zib6yD/Pm9g+U6m/vXB+6MVAaCsDuo1QhJ0ZBzazOsq11O+pleR5Hd9gZl2CYLCkgM+
CCLz6E+f+OKFROQbgM0xYvfpB72cRZdmGVGQdQckYwmgAluzaiNtP06W+3+kjKoRHhCBPxXrzGrO
tXHcLsmA1cyNigwcFdyYfPZDgAeAaeks/PQSPeCXyIVwFjhIfLC1vGWDGPwbRXtIw1M8yXaSCseR
2XGrSiIj9OBKPaio55KvUH8gS5XgcBRI3iYp/58Q0fCGVKGQU+MfHgrY5PmjWzfkiNakogg1zNQj
kukM/dhHP/9hYUkWkp3lWJO5Iyhlplrq6735+ik3PJPHjsxZWgqR4VW1cY0PPwZhjb/FX8Vtgvwy
WCxuwld2/id/4G8DkTsZ68iyoSe0s9wPH1GQMbxjYwUj1LSqHi2oGeP2KIYTiL0g2LCXQBTtIjz6
qJne/kC+NtZh7kyKySvXwAYMTY3hOKvk02hSpUREqax8IHNgrgbkvvZ2ihnn2W8xRe5arp6KoP5m
WSUmDFxdA2TcHVEBau4s2nx3Uj3WvyIPMhxaC4QBojSL1Vny8qsxFcebNoQTFTBZZpQS+uroakDI
nnPsKfIHCRZWqvBlhBYWBvIkukv3r+H5gPTFfciaLtHTwhfofbvgMnReaCXaNYFYwcBX5bvF8s2l
IPFfGSA1m+o0S5+L+/xI6GK4Pbwpb2h9C++DYb5Owq3IbZHsre6E1i/jIMIzWkeQYHxccf0NSybc
Bo7rAvHlrKsZ3V9HCQ7ZvjxyfqOvXw5t5PF6KFjI67WZRryOo6H8TT5ICkJQK1dacumQUNtYUaKo
q7BVPK5x4SAQJIvhjiXD8umhpGvvGJUP11jBMibbbeA9X4URqDwG10h7HycqrKAk9nCQjozptdD5
EVJQASnCXZ3eML4g/N0TTlRfmrClV02FT/EAAlETvnCAifkJIJbRkCilm7ijT6sPvbQJso4tkIlc
ave/dVfry/27l3iMLqw2xUJi3FN+g2+qJdD207FPbDeUSQdPHv4UFx64QwHO1v/NcumeY/uD1q8I
hglLDgMNdWxg+EL0dcFg7KdvTGuxm81wJMYwLpd7jpzoJLWq7wX1S8VVaOLWoIGCg2yl1LBh2Hq5
K/t3qEozsMDfuF3i6Kv+LZaI8MaIpvY+6KG/cIPJVu2mAyf/FrSfTQKQxJ1KCGM/khY8fi4GJboA
h6la/u8ktfmNgEstmz1wrlmnEPnmBB5D5YdRFTCabQYL3D8MLg48VZtqKvAFjB1MoUKiG4IWRbv8
mCD+P07EoLuCE8XQJBio9hJzsRAk90ZjOwY1mNpwzhHmbe6i/DOAsvYAfAz0IwndfObC/ED+qjGp
f6Y+A3W/F5Z0+p1biN8I0NbFLRRzNbMqTGkI0rytN+7BipSQ8J0eAafzgKiSpEuNHpaIW6LD9Jfh
OomtXUpWfDwQGcxGYmbJHdC9f8WjVhbZQwijBgyvYfQPlDRFpkKl0UtAVq5ZoWdYtkcD9MZlnQ7e
n2JZW3ye4ok3O4UYDqOiqceQP+29RM2ZH3Y3hvTPKcqbe92mrtAt7oO41ExqeX4v5Zya1WM5TSiS
8Tnt6vuVTz6qWhdhuvGRvw7GI09nhG9KnfLaElu+HK4FxYLufwTs/0+TPjnD4YKTHyxkHs9N+OQl
t23u28u3LD14mg2kTdYLVMUSZ8tEjyepmY7Cq5erBNwAIaZO240kDcfLCo9G0C6REqC0VH9KpGRo
sss+iupuS81WRehrbPrdS5rk2QHgBwWQbR61zzHuJFnpWHmAIdWvSWf5c9njPcE1t4QqBahu2kEB
YtaHCLodF1IoP4mMbQNXgDY6TOYotrAKvEsHmjjxxys+tg9Sny/WqgRuObFrxp3IA1q8oXL9VGgf
Zy2mQTs2jDV79afH3ORgl8N8d6k3Hr/J2qhHUp2nwqE99imjLGG9mg5VMT8p7wo3VfriFiofk15B
EYGvgegOUE1a10Xn8NP0sCmorR0cp/wuv4nOexSqvfOXP69Fgn6MmqgIZCVjO+8XasL8i/e0F5jZ
ekb/O7HEE6DEvJpboRakMjVo8W8z3IzEyqasGzuHh7te0KMXGYda3jv3InZOaR4tBfKdoS6ZmEpk
Jz+Fa+28Z1zPyC5RKm8InSMspcnag56msgw99bWFsU26jqRWPINZa2zIX/3yOAqA0eV9uB+RP2hy
4assQ61D0JgILiZng3TA5OB3R1obFt/+4IoOWR5vpF1oF7JJs+BvAEc7NG5neap3iJq0db8Sxj23
mpebTrcn8/K1aZYGcGRMMMhHe2+rB2h7MdLtrpgLO+Ygyj7tn/rP/XluQVP93t+BlUFpMf6zoNUv
u2cpG8NehpYQxIPCXhJF/l3OGaX1dW/ff4m25AradVvfcDfss7GTjTP1oOjbAFWo6/K3GRDl5nu0
ACD9Q9sAII8vVSMiOb5xCZhtecjQ7nCnukCia4+SzPtw2vi0IfX3wmHhPdVvlISV0jF1o+plMo6j
3G0Evq65A4MRMAxYKAp58TByYkGi5ZrarBVhJJ0Rp/K8TDo4JZF7OWv69OFow5kVxORyhrJ8ajrz
5rMTUzjjr45PbGiVjlknLjyJTB5B+vctifi9hpQEIWnlnMRnWs+DChAsJxMEYAgZhLfBFkK3UoaH
B/7c/2jPSUV14GpsVg4GGAkXW5f0UoUpwMlpBHi5Mnw85NKgk2jH4sOJCK5/YNPaFoF0+w75VgVp
mzTINPFFsVW30MWA1xqIQDDwZXA23eW8pY29CGAX4Mk105LnKeiYMErOzWtD+fEShzRIjZZfbDmH
CZa2SqVerBbr9Umcfl4+RF/U23Dw+V358jIgY0LvIx9GtRUEY9w2wMdvF4kxWjQJc6lUrhaZsqqZ
pgd8xIOqGFB8a7/k3hWsVUbJA/qjqYe0klIpmlkoCwZESjFMukd4otXmtvuwVhGYdb7/yfw67ev2
Pr5o1XjHd2Urc8PfRXq+W++hJcN07df5p42326Y2PfYpR1HgpIfQDHTw8fxTwGXWzhASGoBKewB0
7PrWWy3yyZ7Lk4g3AKK7NO9tSXL4TbU+bZAeIWusUA27riLyiOfx3IVQ1qQqAY3A7Y4kFvNcEJ1r
DzdeUaIjeM4XypuklYo+7dQFDUt8NlxCGcirfhLKSu2034Pg7jjG7WxpHLMjQ77XDQLepwqh9fs8
iG6ZlfG7tRlX/RTE8wnMyYGGZTbWaAry+FHnUJOSsjL3qLtu1vb4lVVT5ZVTcR2qNBJWNO+GCtQw
nMgpo8NyjKtkHPcj/NarEXvolyIwzXqmOU7ty6Ag8YbcUlyzhENvjISAQ1kXF51buZevCKCKSZ5R
5PnqJiwL/cK5xH0QDv4T+y5M6FUzl6KUAK0fC32ZtXtoQQnHI/BCX1nhKy4OFV9Oql2IgGaYlyry
HWqPvxRjqo/hZaFmKb9J/4wWDcD3ZgsKT74H21e8O4r//TLVXvbE1Fs3wjFdNv8YTmZPRTWHPQp/
YafTYN7u2jwY8T/vhR71afTfd0ZVzBDLDBU76InwkxsMoDyd7MqBCB/NOX1DjFraRrBbuZDF8FdF
pnsxfnXcKUJY9S7RKXAaKGAuagEw+/00He5abj81OepGfZS2KYLzgiXpIRcEptyAAYFJsbUBU5Uf
SzeQPxKtRg0A2vW0x1Fo08yjpJad3Ws1fDaPcNPPQFWaQBquJhC/mFZZHEv4RRlSjsJ9645HyDZ2
0HNcJ1gtt658ck9cjiL3qjqT94E1+rTKr3vJCVXvnt7AuF7BSSDVBO2hW/E7JWldz5CS+myQupRB
sRQzeHrXI6TabcvOYJrYG7YG6c6SKUtemGHBPnWS6leRzLfXwAkHPWlLshNAu0yz+ucElcF2jWMd
PLVPBc8AcecsLPzh85bilbz6nZt2jz/K2w/vThQJcUGDt8e2Noe1WD7qe3HqCrHt8GmD2Rn7dkTE
OdNiF0fc2WKPj0LGfN0o2jvMfgrxWibKY3xMVfKiFhB+cgMuaBV8TZHhgPldElrzwxTpKgY73Fpq
cVbx8gFzVvoWa1UYpoGmtNr8KglxqEBD/+QgDAHe6j5wCedOz94yeVhyyOz0FXwclT7X5O6S1m4F
kbB+czmnsHOMuRbDUBG5qGsyPxqClfL6OF4OueGLGFY58rAMHEEHsXCFyWgGSKeIp3L/UkIkqKsD
T2zrQVr+5x8sWuKjRdnV/zPOSourckqKfdN+dBaKcDR9nABjUuZbfoNx/q1nyRMZyAJ1v3hslgPf
ip5Lz6QOgNBHpuHbgHpkp/vxyPJHXxU9gdW+12cTaFdHDL+PMhgkL9XiMRddbyfzRWoU5o0ogX8J
FCUYgEFHMQqLaR0Pd36F//Jm+oZZ+wLdmCP/U+5WcJit7aF+lMvSqy1LkpkbGEas3jUkLJZshqKR
020myaOg8e2Aonebe/Qp5bj4opV5sBISg4I4deKptzFWjJhqkJhvv4qi/b7plSH9IPcpUYqOdg9Q
V4WhmnGjEVNMBRUnYgygFWxnESymihNZyZwcVCR23bniWwM4SxVLP3YAwx+7WbfRlHmy6zvUlc7L
xXrwXOZj15Ml5vUymNn4knNYe6js/MuaFIHMuG4pGv4r0GFBAmx4qcYKaaLMiUVKuzyQRjFCt7SN
I6tk5g9/zbYxJ9ic16wKPM8ts8RGYCWYY0cy1MJU2Vk+Q0KirJTTdm/nzTvX2geMsKK42+0Q48WU
62IQ6auBPyrdLiMAHk2otnqEfC7uDKmK8aaaNO4gHNGMQ1Nfx81ig5pj4CCZi4YAZqfg28cb/6MH
MyXMCVv7Mco+iusWfBIb20CdzpriVT/olFE7BEy6K1bY+yO3Bi9Y/16kUHRQCxjpOZgfGnlKv45S
jTE9cWFBzZ6hSC2bCpnghBsR6/+GJx4i357CaD2MJCjTZ0WcgfQrotnu5/jqrRtGWbYoWTVBIR8W
76iwXnXf3ck8xjG63UeeHcYc7gnaku0wQrNL9LTsFK6Hg0L09nbWznDslVDFrTdHarBYSnrjX0xp
C/f7A/CR7kwzppuZc2+EOka+BOtnCjJ9eYxtU2/4A7WLGbgGf0boY8bUe7Ke1GoSz6Xf3j/pw482
JNx7Sn80u9tsVd0Qod7rTf2H95cX+6kJY4br1w8JD/OIwGR20DuckClNMj9uyv6VcTj+sqzaLsuk
IkeZB4VdgQL9pBPOdqNVvrV75jlBN/2OsKyKgLGmfYbPgGtaCufxJRdI/0JkIqUbAM9GLuySOtkf
MShimZNN0CAd8Itg1GK9+C8mJ+0hYwkgUTsq0wU7goJ5iefoMrMim1QThTrl+K+gqjdjZjwwVy0M
cM06eY/SPfTMbH4FGjG3GXFuPyweGOSmjN2I1gtrpV00K5PRTD1TZRJoNgPcEYEQY4zZoUch2zNV
CY974tAFQRl65T0xH6FfS1gsdci+89+/sUwSFN/lqJ1lk6K8Rqq804vef0R3NA+NHEyOZomOsj8+
q45fG7R1hHOs5uD+jZvwzmr6luvq9R9VAnVhgyEOjn2K1MZ4GyISNwIVoEMgE6i5gGwxjZjPGk8Z
g1NZeyQs29fe9+Dzf0xKD2Fy0VUAZX/Qz1jK8a7zwebj78PE4zpCMONC1/5Rsr8qMOYX5tVYYwx7
JTOP3+D2tWQ70vLKduNOs4B3gL7rBGgEFCNul/XXMw63JtdB5LMbv/AYqx7kT1iquNzyTQJmjGhO
Yg7r96heX4ZuhyKXM+2jk7r8Kbx80fzr0QQTq4DcMFYJmLfJdHm/FXBrKsM6nAhiyC/c59/jbvgw
j17Gj4J2kg2dth+7ZZZSRM+grMvwLJ8ljO+MXBxBfme9TruRG3ROTybV+TfSBonJOWotWQIsLECv
jsJMZ2DNeVi+oyE46Sks9vertZL3nIoddU6ab6/xvb3lYMTrGBx0mlSIPjtJxvexBjjLy9/tgMDK
EKY4QiExjpmAl+v8ns+isyfAgm1I+MAFoTuAfKO783FrYL+BvwOIupD1dIt/QcYbHQ/qLE1jPc0x
9+kYFxAt/ENxLvtCpaPKVLO47pfmy3ya15k3DSUn5zW+Jby/qDAvliq19AjoU7FZFQIbSRf6Z0x6
y9GBEdqqI2yazNLqk9JxmoLIrtcrJWT2PruAK6OdjPOs/xq9nRWRc7ByuInLc8mATpwJfnr7L15O
/Pt0PgnIRfLmccjb1np+ay6fDjPE8BeBUnGdLr7Hn60Y1Y1OC3RQ7LOWnybh6Y4SKf57DfFKd1OI
bmFbRtrtiyVuuhh+LXTFBU8C6x+M9CwDxal/Sa/gTqNZcjatF9RtrjECpZ25ZxNxsv79sg9ZQpaO
TkKP9MzBKTx6q9VvjD6aqEZaEQxUaFmaO2AhFRtVZrdjw/Va/3c+yqefuNfQsfihxWZCBgPBYfPr
0lvfKTCNULm2Y+dr7nOJc1TLYqfQcRt1T4h/sp17PVu8PfpFkp2Xa0UUjG+tkYWMhr6LAh9MncCf
lpaXWaUeJaZ8CDm8Hk0UpZsAaBRui5UwYldCVwLp9oWoanr7Cny6ImgDx65n2zpXYlaWRAzfbGDi
15NO0I5MlMuDuzGwq5S1SBrygZGGjbK0JhSzHp8E7eNWY/apeRV5A35xK6F98qpAo3sts//aVNqp
1pQwBzfgufajlPmc5wuuMTiVlBPsxb3+NYGy47/OG8KX4/OEK29MEJwlnuY5r8rwNcRqUN9rWep2
HHpNoO5YdMn7IQrLzv5xAEZ8uk9/ksM5NQAEk72YMEQyIiHT+hrL6+YMz+DoSP3oFR+wtmDROiuR
OJK9qqtKG/thumXECgQAsGxMMICbqC0MRbAyLHKp7q4RItMq+D7gx5Ml8lZpVD0ArfQo9z2jyPhR
L8urqim7TvcjQBKV69Z8tWYH20Cd1DO2Aq1cDt3LkxDXM4TV6UfTiJxCFsfEAK9tA9Ng+3cEsLSB
favK2mIybXSA2NrYjbc5N2WhIqx0p2o9KxzItNoXjhYa/AiNY4rWbInr1L6ipABLCyW8P8iQg541
iloxAM2Q59r3vNyz+jxvSva0iJbRgZjw64w6ssCxUfng0PcXv3hS0T4/qz5vLBz7FkREMWmMmGrz
IuMVpeoj8fsFPkBUJe8Syys2KAmRcdGAvvpe39TgAT/5cDDS7rb5wNO10kcgLGPBoC7kBOB9bew/
Ust9tSpQequMcedIRJqi6CUcNi/qICmTyLr1vu3LF8F5avgr2bFirbyU7cJAQ5lonkMV8T457l3B
MSqb9kGTH3ydu6n6JbHHuv8Qq9U1cD8qSEGopK0ZyoIi7EIQg/CXPLg1jUKGwo9BinvjH9dDZrsR
MBfmLBQYvgk/1zWyF4wRBFc6MdrfF08LpY9pHI94WDKb5H3ubYfcT+nRS5fpCu4/5AT61NvUGjbl
qphhuUmCJl43nuU2+vpzvjGRuoNY+CNmd6yZxn89a1S8AHBC25sc6eHFTtQ6FGaj8G5oMQVGOgTO
7rSQbN8AL9xEjNdU/2y5QTK5pUQJuazHhulAKOBA7cL/6t1boI0jy7zO/ejD+X7teFde0p+KHT5y
lTFrzb5ARFxuRJfBpU2/oZUGKed0U9zeqmJNAZeWG8hEreXhO19UKOPBtNm1A7cpiLTp41x+WMhv
vdf5M9LrF8neETVQZWAaIzoKm5tWGfF+almLYYvxVLjJVMgH4YIxb9FDJoyD9wcGf4cjsvhukpcp
YvDTy5oYuX6OYkriZFMy+Wf61RZPhGYicLD2DuIAqxnkxsyI5SAwPR9+qI8yJRXwgIKnYZf8K0u/
Kv8lHG2ktUCgFUNspwjLY2cnXtmjflsN8Dw31VLG1Pk1v3YUviPSGHqLValAvGp6qNH8k0cC/mt2
EAX4Z51bs+MjtJ1y0WhRJU3nIrGcv6CJNSAna+sl3o/mHt2ANgvF0qLUNkrcCc0AmlyWtVpcoRGc
rjjGTMlnmTnl3JenZH6LhfID4fiZX3N5dIhear+WEH/XiJG0WNPsyGpfMp9B6kQ7/rLp0lmKfEfQ
Sf9zVPmXkelcpg9f6SZMlW/cCeuZNgoDJc5YshGFcF9jEWpZ+oP1xH8CO5p0pNSNDCsKD6z1wOYj
Wr6Lu0/gIa+fS6idXZpyhjmqaLWncWT0PO6tPWF6pmHwrAvaBqkdBSu5YcWFFfuuCjI/pMEXEvod
Tuubk84xHNhIsbYboGILvqnRqg7jienj6vpWvHiuljaVl8crCrlbO8qbrOdJXBnEI6SniTQN5RqN
8tGQrRQ29KnQIB1SxUi2tt5kBV2cfxusnGflI+URGREG4rJE7HNU452Cj+nqBvrpeFJEiD7XXtr/
WH3k2xMOEEXIM2KemNzTVRwk/PbBYgZBfTVxm+/GaqPLVkMU7rwTifteATUMrP3l+C+5/F/Xzuy1
7RwQ27+Ozf6O9dVYqLgBUYcwx9Yy92H/wk4b+twlTNLv1m8pdBdkRaIigvfQLNtmiBlvxUZrhn2r
H+iULWa3axLjaUSy/y/2X1ZCOPpcvXnRdTfJDErvLbjEVtqCjaq5Qjyw+vw+75FXipPDyIUkANpE
ySnx67owf4FCAouivZt8MQhwXbwH5DEKsYXsIhU8XA4Y0UKLVimmws+VU1eq5Z8QJBIoaF/ejawp
+mcHnqWx9ehsZf31SP6GUcXOu5l/NAfz7o4Zf3qeN1WijnEWaPi4o2bwGiehC08q7i0zImVzOAU1
givzsemkYHYPDl5wNU57r7P+WYh3XgTGPd4w6DEiORwSMH+S7PVCYFCKODOaqvtfHHMyucBpyg/B
RXcxhZaO/3oE/fPiU67n4Fkp/AOC5lJxkIa4Au68an6ScgX1b6pZA3POxeJirL45he4LlZycogM3
qXOMuhkBQr89zA9r/or0jzSmcdiqHsm0xCccApTeqXwIdIAy0lvlLZl7pP+q5HVCG49RlKnunChx
iWd+PhlOT5Hj7EgKhQPc/87umkMMpUGVLqJmlcWcRWdGf8f/PUwi1ob4ESdGDzU39xR9alZkKmZy
0hkQhFOoysikGewljc0QXZhqyzbcbBaJ0NC2HBNfDJxSJ7OfEyXHcQxLi8KzRtcTn1UNtJxBN7pl
GTcqiQm8SOuVB9wOWXb8Q6U/nePmAJ66aFbgyN4US82WX32AzkWmCtExcHjz/+R4VULW9ZZwCSpk
lsOIp2cm3L1XyaovbVtlLT/zlnzbGamXhfEcdo1+NniPgd9hAWMl6MzPfep3sBkutZJk/SJVsJ4s
x8xoXCZwtcrFPD+7j76+QYqBdJnFQYOTWWv+ABYJmejEWUukNYhzVvF6Us74r8U7y89DIRpBJQEt
ZbOIE8fyQ3FDE0iM7FiXF20kFC2xz9DfsikkhMWag8UsDWNLm/PoF6V2f5JApo8sjKSSY3rcjOlQ
L4qAIMgq1NuPALL8BybfVt2X/BBTQcMXv7cemdqSauOp9Tw35QTe+pG2pLhIwsZBut/pAaerwBeL
2MHZDjzHcH4wMrMEpECtJ8LULAGNr4Noee4UplTeSDoesIkl5g3pg7MUS6Hs2wdH7ZPkxvu2rAQF
Py/vGPNYcMMBDYarZill44QXrVp163X/KOF8tVVAZoaKeZsC96Q6OwxkmYo8GTiP22gbmKJo3CXf
ryIiocBhNz48FeDubFk3V270mnn51QpN0yzzlwOFSW8wcCNXu92LrTdMV1ikvMH++NwtZK9xPRkY
uhcSKgoa0bHZjQaD7wEKTbVp1238ZjmjTtsPgnz+Xib3fzJTE37X3eNYsplHm0WS27OkNBUnLU/d
my9EB2B/0hFo3dJ2SnhyGfVdUGH3NcAimReeoberTC3yfWZrSXZc2XlVslCK+rzBj3qRbjJBkT0c
3UI81drM80+RlCDdQZ2fHiyENd5LyTvyPl+WsGqU9eC0Lqn1uvNAD33DMSQ0RFX6HkDtGk7sHGfU
vmGqTip194mYtZEeIpPrYQLWFdUirCrWV/E1eFls5rcDePVT16z7H5WQEiR8XIMesu51oJ8Fa4Bw
RxlggyDSoLdHmUAJ6xL+mkW/HQbpZptt7NQRhZpzD6jH+tg08d+vy2FWMiiOqmQNwXQn30KO944D
b4d/gY8qYxCyZ54EwU2L+R9hIHaax8LT/A6RTNJTcmtunxrYM7JIvEFxN2Lj3TW1PN0Pwz7HSJyc
l9d4JseKnWSYOLDV3breduzhAqI6+dQ1odbWemp6pZpH/AEG+44OjWHDhZuJ/q9dOAw2XlrGmHeU
c7owghT6ZiUOGQ6xiI/qE/15Q1q7y5voV9ftdC1CD8j07vBwFLMh5oYOAVZ4FDMFLk+zdiKHDM7G
OWwfjGb5yw4PghDcmH966MUjEhpwKsf+Ji/2tEnJCPi8U86jxtVM9cKOk9jIU3+B+fMIA5WNKh5Q
yOKjW5N+G7dgOUwPczqkUsijp2lKbWtPyCHOoX7E9RL/wPScteOpZXgynTxwEywhmUYL3fhqDl75
P1wn7MyyOZLdkjw2lMfW/7YfvFOMbNV/Q0cKlkws+LVf+XG2VmzZIT0IaUC3i/5xysbcRJAdbFft
c+IUFnN1q1x58kaoyiTUURzoV7BmhNIut13kl9ql78nV0t+nW+qaw8OQmB02rXGDcP5e6H30hij2
PFdQTlBKGedrdfkQdt31pu7SdwbrAy/mw7XXWAkE21QOooLRGMlBplhVE9qCj+pgIOk+WuHtzBU9
pHZCZIM+yjyxWsTpOLW4sP7+dOj9/1Y1Z+Pg1qsEqkdoLgcSYVamoCej7YLVuKWveI9nr+ePLIsI
Wu+c0MOvKB80VTd6dPYY35bf7Il4m35fqQb8xQ/PvJ7RGCpUSgPBz63Lp9viE1U6yEgOUr5rMxu/
zuiKkZqk9IxkA+GBJuGn2FEEhUuHcfLk5ChoeAwwKrTfaCjRWOz7jzE3dCqDRhn/AdPUkRCW+dG2
QCOWQ70Ojx2MuB7ESJOLeMp/d5jrdKYpTA3jlpdLg5pvRvs9Z4heFhfZ92eDZzJN+2+RcICMGeRq
+8bRwtDdfCeCDWW82AYldz7wxbxKwdAtCWtbAiaL0Q6P1Av04TMlNYQHroKVsZJxFaVMRoTrZYT4
6TsH0Z3ktMyUAPpIgJfLfwFMiugBvlJP+fJjw06jDLxMW3zHKJVJJsqoOXxxYCmZKI1ez4GhaZGr
KUeejYCW7G3Fo5YhsDiSWbxKT1bmLjIikas8xoRYEbcp0tFPt+/7GcAq+c7d1N78aOQOJGJaOrWf
g+7f3VAJlX22CspKIN98g4AEFbkWLGStOF7gl40km7Hja+9aVrw021KwfLZH/7PWL0QGZI6G4LX+
t/86UyovI31zW214k+vRtr6lrwjkS9rSW+446TBBJMoxyIa+1fhU6wZftzB+8GUdEtUzD0GnXKjQ
60YPEwgAzYGYG+2a1Yix1StgN4d7b+V2gO1s6+TvvFsLguTj3dWLRwuqeZ74rO+tw8zzp6yy9VzG
8REL2S1vzpo/h3IbzbRN5ipinSXCrJ1n9TgL687cl95tLhKc/Jom6h5ggOQMFp3VLFSFdQVWoRIX
CUtl1aRjA0nwO5Vrw01ubWLq4UfQRrNYsJ68cr9L1wBQ2F6iXBSIt0hMY3ydK4cCrHS5sPEZVxpf
tSMFRuRIBXZeTsguowD7tI/HssLdSsHe4SU779yIpxrJFqINKHPPkJR8BSCktpeRPs6q2pYg5j3d
I/NS1Ge5sd7Kp3Eley/AjTuHL6t6X+xSwGzD6pHx8IAsG3nlrvS9alVkGU5TnAD2LtmdBZOjYWNW
8o8tHEvTSiJgoHRTbLXC2w7C6/6zdHF5kxjsUG5T2CSxmwHJx0onhJr1iXXVxzEotW16sUaBe10n
kQ0XtEjt8d+GpUDFns3YpisCgsw8fNW5gb5eEGkBcT8XFbOiWUe1lPu0wAzT9TLgfG0Ij2k/PAL3
F7f1pO3aAXms7rfkvM4DZCdSZbrn1QZciY9bPY/yGUs707ARziALPFsgG2Jh+dBSv/eK8nvQxUtl
h12elC3ou68BlI3kdYihZu30mwDS++mps3QUDQJb8hIbNTY/tcsPyirTgVpqzjkspBwnUNYLNze+
baSOdf4I03+uKGVqwzczvy1f8lvioMkGM7KjrX/bmlWfvnv3OSD0s+ZZHysEhM+umCsUueEYhaFr
pBIBYSzx3hdlGGGPDXe//+GZs2K6tDUooqsbamOEBPwVTnb5j16I5iCpNgCV7jPdCguMmhiplgOb
qdZ3ZYOWRH6yxOnMh/Bxk93LgqpNpMtsG3wJ4m5HuwNvkEfQN6TGmnwR4UcGUdZ1Y+bHiRgHun3g
dE2jylGO6n8AVvPFjEup3svRQ/oogR09Qwq87yYXNimtbrSFJETzWOHQWxbbVOY/r990ji/P/GXV
WwQi8A+OF74r0xqhaRuO0jozAzyp9DBDNRGal8G8L4VV7TbbQii4eUR3E4WPFHKBBeG4vEwTUZrA
De4Y07WIUsKgkFKweM3pBDdywYLxG0mMsUo9+CNW571TJ61CImBXh8HkP0xh3gpSPSe3WDT0r8fE
GnjpIkXJTU+cf+aYWDjeikg9hqOYOVrDa9uc/rMjWocBETX/S4XX7rs4E6mIshy1t1eBJzgC9H5m
HaADOP0ICcFgZfOEpK2/MXWIypsirVJUyqYAhGS3VEsfgejsdEMbD7hc/mnwbj5xfp9z10yAbEwi
Rcmpnka4AW1tN6hHV5A/8MQPEOx8EslP7UzoW+dSBHpVBzfSqmB0V8I+mVK5I88zrml2PzQHrQhB
KG9KeEcsRyxW2waCzZGAW1dhgMvHCc9T/4krIAftVWbHr3lipfCZGomKuPLBBgvhOjhouq1YtjE8
c9vpd2nsqYNsJiP+PTpyLXFi69MlOexSFDiiWrzYaX4WiDVcb+IpY4VvwWPT1FJfypvBQZR8YVa4
kfQEF2esNFvOkljudhEZ2kNMLbubSVplCacVAwwlg2opwr+H76Im1GU8ino1dGolrbfRf7X1WXQr
oJWAG4ZqvfL2FOnabyJo+AzZC4XBoPdsTUZvrZ23CXT4zXz/rAorygo6QLTdEPC8dgWokNQ1ZipQ
we99iFDAXpx6PguEQLkw3tqbdre3QeLF13SlRu4BG4KA9YPLiR7YGd5ialToZOInAIK0EfDSXue0
w0/Oyex4HH6yxirss8XhKM9pVBQykTA5k3MieHs7xHuW6YKZ+gIkvkNEBlLDbv86sU+//iC0ZDR/
FWS+MzblPMLcSIHGKB33KcNFKZfDaz53mBe6IlUo1+I+BWMItUlsTOfolbkY2OTXMy0P1hKL+492
ty5+3eDdMvmhrRoq5K9g7NHbjzNZsSIsybATgQ75oX5HscxENQXBv/zXGDk0EFbQiIFBpfdNPIlN
q5zksJMaPs0Pjlos+vXD/nw+Z4m7svnmF8J+4dmQHjdSqoCNNQ1Vy2U3Mu72+nD2xoDPYlyl167u
0A/LC+J1oFTviJMYrgGTiUVoQnrX72TfrF3ffrhmO0siQEG0v7tleA5nGatLi11QJnhUxkAt5+C3
gzjY++6EXzfMm+zT5Bg9BEq6AOs4rzssauyaXHBMjXi5oeiSEu7VWzCNJv9aaxYigB6VgBdrIJjB
OIaGjTrkyJlnhfwoIIQj0k6xeic7IkR7o1AN6bcW6YL+rZcMsn3W5MJjCyxhHoiPLgogVeG0hqTB
B20djhqyVQZZ+MlqwYnI85PF6HGrOS/fpDwP3VlDxy2c+hQO4uHcWrVA3e949dfJz75GlDf+YbPt
p2PLtBC48biDZ6BVSKmvi0wBOsNItL8n7CQRYg8qNHYpQkhgGVmMB8EA0Ynt499XeA+26jHBgR1a
QFPSTyw/qEGWZxKzEWH+JAMRg+Rh/eQiRAgOlgqGTL3pXYdaqLkGSi0d3/YgHaauLsBNaUoHGtPz
73xIeefEZm2CdPDbtVSfhZVgI6IzJDD78IIL4G8D8K/OThgtV95KO6MM9fvzmwjtpq/x3car3NFR
99au6yGhVWgDDQw1+SmIOXgOuJTCQVOhQXPy+g0FGFAK8O31hkEPWHTa2easVQZ0V3Q+OXB0+le7
KGx0V5ogbNV83nHufTE0O9tSHiEvII/xxuzw46Au3HyeFIakPtz/Uau2QinZbfVMYouuQb2+CgQA
aieXMtXxNMFglRT8c4Z33Yd5bY2w3JOyEnbvbJ3vpOeRLQI1u0efm7zis0aaIebhPdizgTfjalsR
kW0yMMRkkc0VsaIbd2N7hJuMCVXaBnDO8T9FAeC/FN0QZJj7LUufAyGD6USvqT3dCAAAxJ2+Pevv
6qLfPFjX435W0oLo0XCPilN3fpvPXz7zgf4evU6LMiUs37QeHpa5JspBT+pvVnzS22e6jYydzvY5
NuDtUv/94sufFASmA3wpqlnNZBl4jVXoqABN6VUr4zSnWWquafz67GQOLu9z5n3ICKPwbj/Kre22
rGoKowxl3iqMEtIsAvyAunCF7j+uHMBqiV9++NQcyFfE4T2y5cfzqfjlUD8Zgf29tIhoJKrKfT19
62yjPLVvdVI9lUJrvdmJrxSFa0whlXWZXEd0k0r/NLUpIIU3veqvlTtZG4MfTNdRB9kTDTjdfbZC
WHQRasTdXPlrsbfiUH3dG1i3cWa3x+1pr3Qxn2i3XfFpEHwYoPv0lXjVmqZXYJCFf712t6AZGw56
LLAqdM2TOUNiLzLsC/yNXEmvlJImVBSWyhj8CRXS8X188X62YpN8ciE1lEbhW4orBenhbm/ctC9N
kBQEXdVXFYMYLIXf3fEBTPEtZgnqgIYLhRdNK8WF3fJUYD/NpH8v+8W8BSbroswNMxP53zYoFUmD
jykNvzt1H98MRVkeO3jal1QIa/174AMfPbr7RgkrW6mI5btFRXroaP3KaILaZ3qcDJiyT+Rwsq0W
64uOi9lDTHa3BG9eyEnCDW98z6q6f/7I4kcKY1vQKoXaZF5Gb5sFoz8BMTzYtYXavc8IRvKf+6eV
2MUHQwiu+qV+V52qszvapAqNCPjctfZj07NEcHfF2Y+cK0lnjq3oJ8WSPor4rPBw2Tk7bfULX2pA
cpuQfgYl8rfOs055xtutfxugBOVXycb+uR8hR8oOEn25Fsx8au97OTqDNdjMMoSKoQoOGdI8+O96
rPo9/SMT6GC6mRMvg6VI8+56ZLKl231yP4I17jZtp2dPrMStcAVW/huGI1v6HwS94QqPaP5gnAOW
9KReD6qDYeZtiOYoEBJwxFJfZ6QfjKngy6keVBL82UEZDOHrJrRglnRfW5WLG0obAmml/zwTyZQ0
LwT0KEsXkPDPkV6k42JnveTL4eVLcsreCXyjeSajt2E+t23QGewR3wKLtCWH9YT/pA3sBtHOpdmw
qezX6IyxHxbtscQE1HEE1VhYFR80Kl7LPDUpCwkLh3KqSrTy80uJWi3PRf7JHujXFb25+FNioYM4
4QsJMG1Ni4D1TED1pnj7gX4k49ssB/jI6jXtJ7XDf+mGkTAf9hBx7sIUhqNdzJpAcVlHJiBCHBt0
+Cowpt8vza/yPcklsJ7tOeV/tiLZTTtm8GqxqLZTf+x/96xszhv8tKPGQaCdUBDqmq/i+bmMJ/h2
NhMdXwx/znDE1onvgRCNNp/OhJE7ZcrHLDS0E0BXfvMIYXWJF7mh/NSebN/ZTWRsENKlW6+Zhmqf
t9RlDODIhvfvUljxcRtpwRnb05zn2tkOGz7gTpkAf2NV5ggrViQcLkg0+aPLo3IWipVl3skJlzjW
vULtfkux3eS9fbPrc9shDzuhQDrYsHb+PofQWpZ/FqBWwP5PHPYfYvw8NkwrAjo3rGwJcsuAkL0R
GzaksItEPfimzVP78oVn0klcdEEy+S8/g+6YnuqkaSL0EExbgNmpcbCDqde8u3R0ImARsRO7XLw+
OV6JPLVq+rBMksgB19vFllm0k+gaVyhieq++vrOK+3jothvLHaa/aQyTUMS1E+1cu4JOQzHu4KX2
fQbWl81pd8PiMLx6VeuJaVBoOu9SmAlRxyGhbE5nHPqkEbVt0qtpimELd2fBvLQK7lUjdFNket/l
/oQYaI6onzBZ47q4WQUlBmtexeTgLBUz4RGJryHhbKbYTkrv7u6rWm7wTqJAjQOQ5IMDXufUtf1F
o6GxTcEPL4RukWw0zuygrxwip6NYVgwSc9FWxeG2/xkH/KaNXVYDjRWvAUhqs5mn1LxE0UupVqQp
WjJaK9kHTLLGAE5VIFRF8uRCCEZzpeAgCG07TvOIobx8pc7sW4988hHxmzdoxth3GltiJmAP8VGG
fQdariPAp3snExRrD5c7inFwwFmcbRzcih4JcXuQb/1eH4ZLG9UKYHeqP1LP2nxynoTBZZz36MU4
vc11lSbVt+JsToJ2M967Lg28zbt7ubJ4IhzVXQxmWZIRTE1h0+D5gD8e72wEYJJzs6JcjTKqvcLY
pBt/cRhRbdBrHM4Ijymvv7D0FMfm+nprJjvoN9ti6zngqm9UAgrMVXGcecw3n2fDN0KuctKbcEnO
UlhKl9be3oCzD5DIh/pAibdeO/KHaKGpHR10+06ua+ri1ABoKIX5rUbz/0MFucjKSUawBKqteFhe
qZzI5K0Hj837tbXp0DxnECZ4ZFXDkm3QJ0ng3xB65OB8f3nNSY+eI1aZwtFr3yjQqNdNyUTs2Y8V
mEgF13VmMUFxDjXlXGCycyVoMnGJYk0Wjd40g33aHFuU8A6Sn2AT10ojekaCvqQNscrb7NfTJBTu
b/kKOSHJ3M+2kLiwQ6UVFpho13Cdb4NMiYQCWh+LDQbh3KZIeVd9we4EjpEkAK9Bir+XpE5yJqvG
6edRHqJIGc/myLOUeOJ6c3oxBSLUa3M/s8s/YVjsVIgTLlzZRT7HJ1VY8ARraxekHT/rHlEJMBBq
tEoPDkaaIvEHKcPOzuY8mR6zF1+QuoseKNV/u8YMjfY8ocUe4Ya3ISP1DBaGBIrr9W707CE2ouP0
jJPvpljL4nWEOX692Wq/9ZGLxNXZPJcr4xDpKI3xk3z+FsbqA88i69vbx7StvqBuQbQ4WCyJkcma
MX6/vbbMOmCgQMFeZXMCkm63el+w5u+eClLgwxTs5FJ15y6Q2MWOXjK3l9bxDs61uZGsbSumScQb
QFtgjuNWxWVVolsLXyrUrz9hA//sK2ye8a7KSXDTvQ0wKeIhDsNH+W1tR/YPWziSsHiORc5a0wdl
ViqBXOUudodg4xfihouokSoR+192Cr7lZjT6Nq4ulQi8tCcmbtT0I+C7kH83HbwDl8XU+i0XsqEY
UE8ldx+GkZ2B0NYOLLwKx72PBscwsF9pywv/OJL3r4Yj7nL3FA/ucEK/Vor9q1SX35tmXtO+8zil
JTS1RiWk238JqNgatwinbde0QIc5SwIp4TL71Ym580gNTu8PkeXW7Zq8kZcQuZoXYU1/FqYdq+Z6
FlEPKQmIrROJdWHbU3RjZfSqN4iJrArfn99PhrKblVdtfl6TKxHkb844SovVDPhn2wtiokjehugn
pKao4Z6fHzx01VXoXKr+ru8kna3O5Q+N7xp7uKOwM1TM+Dq+ZYZPliV184Idl7nTJ/HznpHk/ncp
nyT4ukW6xbkeSt0YlYH2i7A9sp6wt2BtlpnH5oBHTnJdbeMy5e3M/0gaCTDj7tOzFj3jGtFcefyd
CoLnkO4tKJA/2zO5+us7X2+tiLmDCYdR6NXC6oVfYMf6fPz7vnWx4c2dEKRaa2qVegdAYXg5X5+Q
trXq7NsVIYn1wQ3rE4U3/R7M6Cfs53Rm6dLqAM55jdzUxgpcZU/F9BruYS0kNrVQz7OteouM+zZO
aQjFUwbWb/Ob3kOF/Ujo+aR9umIBdON15ghzAG94UUxINoEDhM+FFvYbPc83eYwDU9puRhxZVVqZ
yKwiybrmI0iOgg6wwNHdZ1Qta/9/WQ0h7pNdqytXBz0779ivRGS3h5L6VCpTouHqOYChBs+bh388
+Ac2TrIZPNlYhBFxz9OzMasFmEN5ltZSUChCrpMGSgpOzLi4nESK0FUdhoTyJjWufQFK4dB8ILNJ
nC1tO5UTVNjJiRul1LyB19FLj1NGjc7TNF6d5HsRQPSMA5Mwnp8JP4UDM7Kmuk+uxj3cJk180e3d
rxhZBTJOiGnm81tBGIoybCUn5obfZKCXh/ZWDd9qibHj/4FrDUQceUkMmpHVVDMs7vMe5ZeYgxpc
wDveBUc/JSKxN4hvlBC8HntvFHXNFwo7AxFrol5z6JVMFuBnYrHTYZsKOEDe1AI2AgNPlR2P+aWI
rrBete2CxpLeJUp4ifUqbW0Xe/K7yaRETsOznW9gnKs+sZ8luKgIDo8l3ito1m9r1fA+kjyBODP8
YLsZHabofsB8xbjQwo6mG+ALQX/T7SZGiQSW1TP+0lVUuJQhnlMRBeZPYwl5G6qZfQNizZiJ5r1Z
AmPVznA0HCQDhsMgl9bngCoeg0m7HZUi5hhlrQ+qKruct5KR2u3WxDG30xJ+uuSRxjMX6tMVz91t
giCg+yVEP/Rd7FoTrGl3HhjetyUgZFa7wl9EaXK8HuBCR3pb6GSrcM2HlkXNht+SdsU6re4dhvDR
/LhyXC266WBCC/gb9JKJcmGVIdtpaBrTaZXHDn7q3bGoTfbA9I9vQ3csDpZe+F/VyVAihxlSNFZO
T7TtC5ZRjgIfbhOloVhUmBN6IMBwchDlK3Vs3EM/2MzPK0Zw1GlLW0/GG8ajc69uYQAd57kV6Vcs
YmVJEeLA9o+KH0SmPjeIBNrenNIaMUQF13f99GxqSuHK0NTbltELmDLVBN5Gjf3mkDCOH9M3ekEy
Hk4/E3EfQS+B7RV5s9rGr1APA8zwl2/dQ4NWgqazxgWxgp9eIRIgNVb296vwzbJOmdM0DlTh60so
trYx+qNSqy/pao5NksBG8m8pdQbnh3iJTCSE1xio1f5Fv0uqzKX8Z1yPhDD6VQmPavoFvSA6NDqL
G+fmHgZZrD3T+SEqqhE+kGLBku8GY33ClIEJ1oOvkFCRghpeZwz9vlxpJWeV9Ev857T8IfnYZtT+
bMoEE/6uMghE1k8YfLFQnG3odQNspTcp3zMWsunxWjVhcO+XwXvx7pGkKgXgmGfD2zbBAOAsOeFG
9pTPsQyeLSbMOrKyRoiO1tWm0H/Mj8nLTjuo5UVZ7gJj9IqkdRJelLQXm5Gk8/ejJNszQYX+BcXO
WhhSYBqfcyvAbwqcynhH5K6XySR4HAK32lE7XkBtfr0tgWLvh4H5u940aE3Da8kC6l75hCPHGEAe
oWNXp0JYMPQwyZHESWbnghJKaIZ9GcYz9Xf2/fxPRXoh5gmn8z1G0FlSW38cxCm9/Vc1g0wElWdT
yqc2gTokzg6P42xjn/ZNr+1qPNCmH7WjnW0xWB55mM0ArGp7HCQX404qSQWbj7oPTaijJI3vJ1xN
41/sYSfP5zcqDaHff6FTf5yBLj+sxZWGn0FaSDim22IsGi8GrOZFiqPYNLsoW8/Nglet8mKWgOJd
3bxnUBbkw8c5t4oEyMHq/l5R1xdWyXinJzboOCSRjRqXJ3Y3c2nzQe7mcU3x0nSIoBmeMc1uYKCr
nMZokC73zg95LlLQxuSt/obpcX1jfw8fPqZrrD79SSrwx0z0HYsvQHKReJ0p9d8AVWpdcV8MN80V
7nFpM14u5Cx2x7UGwBRz0NmHSX68n6hkmyqN3o1tKhizlZCLw82vV/o+KEZcby2H3hc+cXLYisr3
j9TqowbGMp4XCqyiokBPnqfoOErBK7jfwJPOHr+71XuHJk0zL3feayNatOFuNQQlGimRlhtZAtaD
rqbIRpB8yE/JjkrI6iiwUuvWN1AZOLNpZjC4lV6F9WSMPGiyMZzhG2aMBPbRWosBOF40Um9SZCKa
Izs8QgNQ7GjkF8ipDBk/+jH3XM4h8G69H9+ZCvbuGGdMvfLaFsCN6n6brorIShrzGphksVeZFhZC
pLeOduAlTHPBpngn4Bhoofho3Z9cgz9rRw7P6dU1NUbbGpDy1lIjtsHbGNF7tcA2ktzDcsUDPxHy
w/UvU70XnLNvXyoWHy7ooXxhq89sGUONC23peAyoBWe/HVDQFjUoZbwaNUxu4LO4KdXrwCfSyWen
uvUeRIO4HUgtbM9xHY2rAPVeUp6VF6/jnKjQGPMIOFrQ/PASD9YuiYDpdx4zQAbUuEuXYRXASMe6
vJ1HwtTKlCBsmJY1FU1wKRoRopmJTYFCSXyBeYmfQQRgVu1LT4d9nvRlUkqpgGInpLu3x2OcQRfT
YuOKogMRb1xy+XTuSGWBKxk5DbRhfIUWUMnOHPYnImELmgf8s9XlDJldi6iQGoYhcOHWCyacrdZz
2XhQrhZSujwLmvO4YBmNhhPGlYHfS1X4yB7BNaos7JhEg7WvziftuZsTCzC69DAYmGohQgQsyki6
VhCYtdCndLvNrkT3hoLxrW4dqrAZLex4QBZziPn0sVw0p3yCmOt/pcy6LgPwmQ/qByLxfBJwxqZU
GG/rVfy34cIXniUc8b02xVIVXLJCxIdsAf8JJ5I7krHZDCJJcmuWDTZ10ZXsmC7H8gA4WngvR8uF
IVGTFjuLA0uhFzkUfgZMALMIMyeeNdEmIfqMMKZXo3d+HH4z0+Y6I1iEpNT79tUO9CEwQLQ05INA
YRQ5cd1j5deV6Q39mPG/cT7FfMOUiLd+X+s4AIFdZhffx4yT2R7OZj3/cN+9AXaixeS0bQbMcvsB
CShbXsGQC7g45maJ5JTLKV16y2F73EXkotnr+9cvPoXxCtD3VzM3Qt0eg5Gg/0latwUHa4316sMn
ZBdfZmQ9eumUfLt+rfu2wwnHswplGEYnWShXZFj+YaPL8kC6oOlWWjenxKlfsgE/GJJ8I4PVKwvs
H/YsNAiip0SsuOGyHOidhnEqjnKsPvaLQ72UYoXMatdad459PcgAcY/3ePQ8EbDGc0Qm2Kk/2yQX
5AxZKAhaUNhUVY2nApDfGOKbTv5TOp51XOLjKvyTITlCRjM5kje2+8T2YBhBq15O+q2pk/7ZRS5E
rHySgT/glNvhhbZ4zZ9oCW1LJqgjzJAtLLc1V9S1Y5ARrEJjP99LwvgicOVJoLUPYg+j1AQ0cEeB
8rg0mcUruKpOJVeSB6NLmvLC8r9NnMaPCWNVJ7fmr2681fy3hcSG2FyNQHJzvUZIAJXK6pAHT/9T
PAtxBv88q+1a8pGTD3CUEAX75psqBTVdknxboE/UGsNG6vLxmxVw/OJ/XMQfOSeklfo08QUCrzD4
1j54ZyAFSlOpY4JnqgLDSMgGa+4Z20G4JJPB3v50WZFLQe+p0M+eORI9SIv/uDzbBoiQBPFoRRDf
qgko421n1J2Xy6Tht70cJVkwVfCA8W8M2trU7mMJNg5e1NGL7Hgh8xjvm74FZ3/P1aEKMLHoWZUJ
Qynv4DpAfw/gfDaIW35Njx0hVYwK67/W+U21cT8JKVrtjXS7OnMozhlz7xu1W5IlvEW1PWbwPEp4
XqzMqAGHiCe0guXUxyYvve4NCE7Mwc0pQrYUPbFH5acA2/nHTdyDj8VkykUzwggqVO+z1QlVcFg5
wzQbRarnUh/3c+7GiAdD8PKyJQRdFVOFXTCtPMIoeU+HyTl7DBT+l0Xw8m/kn7xPwBjYbXPbTxNb
poivQOwKp2Gw+NLfNXP4wSofp66YSSeHBvHTM53/tOHQbaNoUmHMQMPjFaVmkZti5zx3kvLK7b/K
M9NGQV5SK6e5ojwZxcTFiDi/w0nVGqUWFBPkItyQO1idDmrqBDwrsoe0bdqQfkZQ7naGG0YilwmM
LSPsV254aUyiWWjZ6f86YO8ZGOEeg98ZdWvNksQp4V96ifYLRUI+miho1lDEd/QXAKQWuUyoLGz8
YtrKqiFPruwB5KlK3By5csZzYDvrZ6qkq4WlZ1X0CaIM/zF1qPOXLfhykmttyai+ukddlTGBLQ22
LGyFP5nRVWsGtazZmg0V2rMslXjFUOkdhi/8XR9BuC51gBQpc96a98EhPM9yvBFzZIH6/mLtoWwc
J00claM9Zo0HYJw9X11kRSXYlUeUsnwiB2t5fB2jVvhrUXU9EaF/BYHRSLDNIZ7CrGqqJLSntJhv
94RDpHbgH7gtYmxlLTHs4vv1qU9qDiW9yXyCicg/M44Ya68F5U8DAJVrzEo+aKxl0AADweY0qrCg
NEhs6wLudtwrYN1Sf4csMyQH5a3WKqLNKiUCHZgx84y+aiMFEL/ZioxWQLfikUL8yNy92wqpO3an
EiCULXpcw6Tx6p5SpvYprbBSPOq6k83Db/Vh9G5fHX7ehYHAIG7p2a+qZGFftlwnjXrvzcxPssyp
oX/P/76+VP5RwZAR2d+TjwvUPcAQwK8lcfenSKZQDujWEMaRSq77yXOJ+0hIr7cZOCQWC2GeiK8v
Nv4hIuPNBGU/6k//VBMBfb2rc8ZKQvRaAh2sfa/mUcYNHtFeUFkn+aUu7psAvmGvk9NhOkQAEJXh
S3EtMGjt9fJpewdlFurGUY2hvHtF626Ibx67QQex/KkTwqnF+kEMnfTh/6xbksfawQ/23NXwpb9n
A1ZEXCtWyPOsCRebpZeIhPiPuVVCGK1rpCKq7KxxAqhhFUrX833Y9Gc4NdBD4PUGUvgi5MSK/gNN
bPC1JH1+UNKDJQVWKd8uf/Ny1ZhMZ94CwqrOM3bfuxdFjEOUlwXCCsrgUn99Ud+TgW5Wq/Ga31Ao
oRF7+7mQAg/aTWQuhJYemK9ZmHT1vSxhYL95tSCgzdU3rMRikZ2CVT523hf+VnMMjCsWHBaojXtp
wL3zQEqLZFwot3PORmH1fer7ujWMvYjInDuOW89+p8MQsilY7YeT6GWZGCk6SFi3O7KZ3rtQ3tBL
frmR7mkYOL8ZatJyRSGF6OXoOAkRHb05BRazOtau+vRk9ZpbrGeIhVCZdzGcyvciOtBHSSfsMQZt
8tbvrjyEtAFVxhS0x390v+Ad6rfyjSmuodMVJVoK6NeDe6c6G1IJjvk23zq7jhHuzgC9Y/AnqZey
NBcFW19TbS9IJ+Khgn1mVjSUfV/8WWuX72b0EBeWSgNmaC2BDV2M3ohcHVAqmuWb2x/8IthUDGEf
p1gKfpNr5ewAVatACzJv0zBAthJyYYC0hjTAxUnaToYdfJ0agmKlfxYk/IeSU9H9Q9KazUEjPVJ+
jmhOvbVMJi5A8Q1gXh/uni8DLazEdxmM958vJT8/0LO3KpeDxbCTrXHPvMkm17RCNeXISw44T6Ky
qoueKvtaF7JUHUisp/0QSod8CnYfSWADKJyC7dDz7L1KVclS8Jb6DNVuO+8jAqfAvfjSdmG+EwM/
+5rZARWQJl83/f4vcPM0KryYvZeh/xH/K4PiOzAs7nK0gF159KQLC1RSe8UN/3Aug929jJjPg5CL
CAVRtoWCVJv0yERgri1tctfulJA3lWPEsqo0no/nIMt5VikNby78oMxAp+WLs8nEoKc8sTpv/Cq7
/Cte99rpICFX/ixa91wqPqu2d1op8IWsbOOe1TlEayLmy1VKILQ3IvmkmsjNei2aaezBpLKHJaY/
gHXLuQULJyNTAHO8dXdDhq0mSPCLg0puWG/XK7L4P1l457FKtmMUCMNt7uupkd41kemBDGpK8AHu
63plkCkU2rwiZ4OHPVyOKkfw11iBZAD1mBtbyWnhsOaMrFFmejSYK2hOM05LztSuDIVv5WoD5jGK
6PSFNxzeXlxynNk8cg2ZBLEjmK2pR4tJB4Vu3BeYt4UoOzdyHdNd5iOWHZEz1FPI6RJHGF+C6PjL
Bp1G914KhBzhKQxBRutqDuz8fOEviGXOwV9NcAvJC2IFybEr7SY0D/qaCOEmp4CrW1l3dwmbg/Bl
MWCyrupQYqQmHFJdeeZry0kyRswFVX8SoNbeaYnyn1ZMQ675oZDB67JVRySUMylSq5VCsTX07giW
Q8zH/0sJIY6cqZNqHDuBsQkMEtH5r+7C/VVbH098ldI+0jjQs/L4ijl9mgMWJSDf0k4Y/QbyfO2T
xkGFSOA2643nBy0XRw8mb63tqP4IZnis6C4yyoDYbOiGtZwOFp42ITxsURvQgxPSuuGTV2SCgofQ
ozqCdPdY/4GB+HVjVyQ2IpSTQgYICO5AHcBe6wuYfUXYUtbcoRl4DqL6Evw+LTotBWfisAVL7vqd
/b/6+WFYiSuhlFmMPZqH0cehXrIMRnxseMbFNEW6U2HrVobxn/KPZDNuHaxX5NWhkY6Uc10KDmhT
jTfLtAScrCjgYPoUSNzA7bFHXGZ61nazzOKZgRmWCLwO5Z7uoDKjS88LWtjeRSEPcFYwYJPWY7Um
zFgKYfm+oKSdg3ClQSNgTIWCR03OegSqlYe5ebSYHVH5v4LQP9tO4xia814kNkDHDthTGDZzYnRh
H0LT/fyyxDEoJQVJankgPgU2J6Xasyr5bCpl3L88Aa+6VM51XmkCo/rAX1BZH6Mlo11IY7tCw4CO
VUo93pfyT4+F3xgBc/wz7oc2UviDV4n0Yk8cn5oLMyUuqxZ9rQF5OayyJ43BkY+D2N/WJw947Tm7
2gauKw6Xz2JTwCNxSQgnMtRTPcW4/IUXB+50A6qGzoG4qr1F4IuBRyRtRtp83+BAFtCk+NeqG1Jm
/386EgCmVM/ZS9upaIwc0nlZef9WnP0BIxLEdzSdiO4qQX0P6XYx4xcZW1+TV8TqFWWIT6UZIkOg
UucWc8ASoDSZcx4kzlSeS+sCevXcCPz0rYPxjlvox5IBlJMK/WHkPKTm+X6thSrDWfn6Ervujh2U
GlgjaWLRDYxH4iKFsYtWNpv9QhLQ7e5tC97p25RzgkbvBAAABurC5ioWSYk9WMwCrlwcj/ilkBVZ
qyLLXGLAO80DG+7sG2JnGZn48S8aUmaLr2WFA3D517+giL7ukVXlnZVy777oig2PGEKalJgK3RaA
DOIhjciplKu6vylwz4quMsAjBeKsqATsE/+vNfxXTd4vhUUzm0wqLvdKpxhN8ZsFcQx7zV3gYM7c
a4U0Qqqno7d1VxCOt9fv9eKMkWVYUuxN2OKoPDf/Euq9zAryCndZ1j94D0K8nnNC6L1wLBC8/2/p
/TvIRe1j/3d1oxcF0orf/vi6v8eWoLcIvz+LiPY5m2iF5112WMkB4LHQ4ZRC4l1UGfk0Yfz9hG+a
WM/CxZxDMlIc9+/ImWpOI4CexkRKjYx9eU56wxyjzD3u2hXU7hmfCpOyxSWrUIleubbRjufAP7AG
IjZ2fXrXJeiFudgwLkRKXVLy7Q8Ok0pI3D/iDOyCy96YuL13+jwyfD2gbNgErMElENnoaMoE/ZPa
mXeUw3Bm9rthJpUDJDv6c0AcaE7tvpMgeXd0S8LdHI+EJnf+6I4Gyo7APk7v7Dxr12Pm0zdVmCph
EedzK0BRWRnQclymJVwHNKrdQAzP83D4O33gvnQLFkkYSZIajHfB6DGno3+OjZNrMzqWDUJsGbmX
ZoHJd2illYxCJldZ3SQeOxcA1BkQ6ewsVwvuM5eYyGVVUFAjTUBIiPYs1VmEq9qGtXfKz9TV9nVe
T6vW13zcW9GkUlyWiPz/JFyRWczfinoZ+z7QpNGV2zYjTS9uCiGTKpCUOF4JGqvw9O3Wc0/IZDun
MdqBBdzajuoDFlNCf7L1mqEyFkaaHwORoxOxx9YMNgovIRHxkF4NAtqo1r2s6Sj/yeee4Qzm8MkR
KD0yzLsTxVU3e5syB5eIEkc80gzc2nFItZoqfzEpeMFGYJktFSWiZY8YetdbRZKtTRKUI+pYaawQ
qHD1D+PJr2S09S8KI0cLvffrrXA9+J8hr0LE4Osrbp4xaqMCXxAKFOnECPpLOdFddVjO6CGcBNOM
XcA3zxR2qAgsPLCrhrvOth3X7Q+BxIYlee/Ttyd3Iy+Vf+fEM9Ufm9Cubpdl6TAz8srCfDCFRL4W
+knH68jsxjNXWmSyzWNfNr1nVSqf7sPXJ4N9LhMtdqR9k/yW5HzntwKafimSKcUVjrxg7MGfQi0l
ZBJoLHccUdODBYhyQQPFlamWld+GPsDJJwNfGgQ90g+ckAmIHaccu/n1eDg9j+Ld/MGLC3+6FUaO
8wB0cylLkV/zsQS6z2TdZO64IW4d2U3JLPUNNDNTyTeT6HivYN6JMapmnsi4Kh7zhhV5qz55uhmM
h5QZumyFSDSA3dob1o+L2Qo7EiB6nXkfgfqzNodb99/gtcHPsIetg/bfv3Vc0MNiepIg188ZN79U
IRYgv/BIpDnePvr+/x8j8LVtkX5sPot+uDJ3eKjzKGWwgrgZbuvszIkVIBkwmxwU9GYks5pwmPD9
waIWFLdJcfoKVAStbXRokVvYt2O7MibeUke/CRdLFuSKh1nrmuriICcXNLOxKi4U1x1W9RlYfAVq
BSxWDXRZxrY9l83UvTou3Iirt20ykokcMklVxvxqPc1giQOi8mqYZAW+6drw04BusxRJMY7DHSJD
XfOgi1UM1XENKKeDEcA43EjUaw+if93KdDAdmUjUY/NgXcCSOFMThXA2ZNUjqWNUhY757moASov/
oneIM8tuh9T7Jms/NbZEKh9OwB9BMONER6sIdNGwmdHROi7NROkGoIANrsx8wYXy1fWNqW3ZMoc6
E/mlUOn9duJCu0CpbnMZz/4pdSYfwk6CvOw5GELSB9627m610fkuytyewE4j0eGyi8o7qQG/RdVU
cVh8PW64zrIRdaFR2N+pSTXcRvla6T5zIwYdDUSYYc/eB+29V9EBDW2zsRQ0vo3StBkvKy/12+0Y
hhI8M0JeBO5K8hvefLXb98fZRL8Z5ZEwjT6sqqZaCz0JCWl6J7GxinwUVe4BFUKSxZzcPQDPYXt8
XGHDZ1eNsqVdH1N2v+CMw+Ey9JNatmT5lRXLSWp3JueJw2HqLDmj1JcMAsPs2WxB4mDqNK1Hnb6L
XtFFYD6jxT5Y9x3mSazhmaTY3Ov8FiXy4tI7cWx9EQQ6xthfVKvepArno4T3oBuSv/PGX4rICrv6
VW1NVTZekHhd+047F7kFqMx6aR/A9f90K5GdtBdJY/hoyQoTitZ3jeeSzNbam8VoSIeONXHjkmrM
lPQ+xny96JYcbspH49fhD9h9qOjMaPjudAdYY1kqSBSILRzg0bi7sV2wLFgh+TqJGKUMZzASx8GD
vpZWZ5Kyv4yn6PBufvNXKNXYYQERbIXi32xNtG/Iwurbx4rSSJK+9ChIkTqmOb9Zi/N0CT7jy5+Z
BFK0F9ONnzjcsl4xcUac02kRfwsQp9dbJEVAQzmcUeG2L/MAeNCwtAfvVbl30rCH7q+exn9RIMBw
mPpWcRCoAwy9rtWNpnP4wgVhfUh0ZhzUoQZhtkmNR0AcKtT6E+ds/s9oDAiL6z6AXs+JmuRnXr5a
2aFyYDqKm4Z5s/3ed/paG4fnSlmYAwYGziX93DkQgsDEF1u3FCe4PoiVUiL/MW1P2AwRBtYdmx8y
DfIJYFdsurp2S6uB5UnX2W+1WPZEENjSHuY685w08loOqLQiOncSJcOMV306EOt/jSvFOD4I94CO
B9O7EoBVFQ2+NG3lkiaipSjBMlYe/gZp1fCm8mBKvGfM4UEH7gWh4Hu2m56fdcpdXYSzpiihPQVq
Cab+KFfSrdYh0WegtSXqw9++0nwdUoJ2iTUzJmD3D9eNETNHNTFAGOowBtnr+fOcXWzHCg45pFRr
UBwJD+Chw/rkYikR+zYCVQAHF+0qeGD3DkuL5TqWeC8jKlkz9YgB/lBpO958hXZEzVfbevYoHw+D
UkkMTbeL4zGAC6Qvdc67JfduhW+d2av4V8Fv/hoBBi9PDPKZwPE9dJqNvZ9XqbleHaiztgXxg9FO
RG7vRc3x8g0CrTo+cAWoaDA73aYkzuV1y7mY7oQb066NMS0jqrqwo4tvxWqdaGTaGGm67bJICiwr
S59pGepX6CEL88GAZYIPAcStccHIgAIvpRD+zHSgkCWCQBfwJ8yXG2pg90Y54VA+0iWewZVKNDu3
LPU+1O8ji4KbKqEfC6eSWXrm7qpN3bMh8QsTWJ9lKKCRP+K//+XeuMs3u1dcX4AGbdeQsHBxAtSu
K17rHw5lUfYpuaXT9+Z60okQagBeZv8wD7bABtdS1rAwF1Uc5Ox5Fljb1fExPN9R8fm63VrT+qOW
eR1GXlNuxHpWknvbkQZH6Fj4HrAEisQL7Wik1UkaSYFd+gV2uLGWd55bjTrLcLwDEoiLLjxk/x5A
/XvG0f+WeXmvETb8aP3ujmNov4wwmR302yc9NrHhYsBOfvQ2UBdnVVFPpckqb9gXl8SZHHBlYi1K
zMQAhpAqGJQYdylMHx0N+jIdH36vlBS8xueZkztQV8W6TqXO+5u9NYSjil0FPuniKYczw8+3/NQF
Ciu3PmjVPKP66L6xWsCZJ9wROl9R5ef+ssdQ9MedXFGoRcFe2RWX/vdbT3tOrVBzYLTADsLAy0g/
rbQI93/RbtyM5bcCQjqAz674r2OcxmfsSNvAI1XXaJUc8oQe8es/F18NOEJnsIKqR8e/13PsdS6e
edQaV2OP1WMjchEaZEuzU5n3qsVpv7v1wTk2DX+swdp6q6aqOmRX8HD0OrwzNhe9W++m0UCvRYh7
+dPdCPoLzKCrQ4EjTD2BLHZK2i7VgWiYgeZsqxDmItW7eB1ya+iG6tjHruY7fAdy16AlB8yAH+47
5xfgyfJ55O6QOlxlFwUvl30C4pChbfRwGHrhTuRQOCi4DtpVfJItsTM3zHFNOB8ty5JFjdr0P3Jf
8t4/rM9aeHxDnYcZE+CJhoOKnXVS//OlmGXv/w/T1E58MnPku4pUvTIxYFLciMajUAvhLvqSTsH7
lNlGdwmMwR/VUrqAE5NNwfsORXpVZhnwZgpuPNBhwC15ZomD/2KwZdsa3kSNQdFXh5fgonEHhaOb
tHdtfufdTCCqRmtNR2Czd4uaNJAl1pDDjHrtV5lEAhngimZmjXQvyY0GnKGcVeQnhDWos4obZ06J
n5kTjnvzxBrY4l0KbVyUpuwewbOZrYYl2mbrWA8EGvTYLfHxJaAMSkRRpf2i8ZgmW1eI1JS1wS/V
KoXCr1CmI+JvNhw260muusSEAczNSNT+pRfma1gnFLjM+AN3KMf7DnEjc5a7ppmEHLGeUTVMptd5
TwR7Zb2qEZwHU2Whtopeyo1/DROrxNwe3cGWePc23m+DtxABSRKP1gmM62zmBHdC/n3TR/E6obhN
Elkn5WMII9T5E4znAB5oL+Sa1I2k/m+dYE7Q23zKuAEbtg1eVUS8ckdBq1DX2iWOAxfGjH4JAfXB
vIQ/+SQgIeDgVb9DJTDlJqFVTvGGyK9dpOzzr//XjWpJlIJMKlGTnkqiLkqoUSkAxL5jFlaDJDra
YMwEt6h1C2CkVA3LZzR39lmDOb+a6f7ffLZKp8XCv4JyT/YnKoYbv1+9jbEuKUZQeQab7Rrvd88r
XxSX4gy5f4pKxXsggJh/3sI6Llly0ng5oNGnJUyTSsxTMWd2K7kfasW076JupFFm1xRZxxCe6vVT
EoHZx7GYiHkCN9cvminjKjhHigjYbEjgusUn3N2RDyycdvWf4wr5Rw7WRJe1D0BTIaVPnNo6dB3r
9ulW5CIV4Jg64XO02Qh9MutwTFzaq/rAWMk1wqBqihZaXHpO3sfyMISUZ51UAhlBKwFgkgizsPXN
qSygS/Dg7egK1vBGJaJYmUVHGaky4Is//241cOPxIvNhjyAA2iXsoDZoAtnOiZ05uVr6oiuIZldq
uXHn+SqsD55WLEfS49BLJF2Xz30SpOHdHrmlT+PkOBRGZUGST9FysuKelTRIJ2F17b1T9Ux1f3gd
MepnjU07f6lO6eJ+KjkgWPJpxMqK4ZL00/Vjgphu5/HO2b0yDHOxuKL46yJiSgMQovIAzORWHnK/
RvL75tKQRdNEF1tVsuXAE8m9GRyj5yHawqRlSr5RWYgQmDumx3OzDa9MUQoWu5l3la4m2C9f0LKD
iPhd7IM4aROJzAF4kg3/B/qOlwl5K4XLdEkVIxwQylXvdbQeQgk9hr/7mhhPL94ZmCR6CVENixgN
WVknSaGeuH88m1hct8c/snyleflu6LP3gnbd5RX/BoSgN9XD3jAgado6BLlVFmCtrtGNDora1DZF
uJtU6rqIY+AwgWDa9hKBxhRn1i/kKfxqSR0k4qeOGK5guFlEwG8LDO7i7WLufVtWVH2nwg4RniHG
0Nfc7ev5uCarB7uDQFNcQFu+f3vZ+M8PLibMR9t6i6GsfK/NU7kQ/HYKphMe9i+u+GQkyHUtZEe5
MKaQCeNLBm4t8taoj3c2e/QNYJwcbh+5q85YUKZV9sKfsfxnbxhnXqhZb/oK54DVPc+VNlBni3zN
gD/9+X2J72nJrGovU6h6z1ELbQgmwBBwBHJfT19T5pkGB4++CAhsShCxouRe9PaULqpmBBQEKmUB
gNTYM9/EvkAej4QYLVIT5rmBS/Kf/dt1PrPLFXmkklcQpIGKh/uA9cGw/HIDdHBWhSF7zjVv/vGF
/yoccykxvAbPKsk3rL6BWCiktGI6EkLIDD7NCr7zXioNbsqxGuJ+3P22VOhCeEaicy4YB6nhrK43
1Q/luTAvPvOzssHvlWE5dzx6hRiytc2yYAmioQbasXFyMDF86EdLgXS+QgjN+rUIIw5J2aJ0k80M
pQJ5g8bUOCJppIxrD/x23y+iKdAXtf/CMa/1DVVXO+0wMj9NmFnG8UKnYjmt0gpSjJHczKN5IB82
+fHclrhLvGjsq0o/KeeSEgMlJMgjyVUL4R++KBspU9g5JkXd7hwFCSRpHMnU8H55whSMyhgfK/oC
DryupFaiGDiMCAjhXoA22uZOTWeJt1T6vOu0KFd217uIm+NL2GKo5dlnWOx/4o+qF1vBV6iMWNZq
fjFR4SWwdkxR0W8Hf3a08NbvM4g9nnJE/YLl9IKmHu4jbo4snA4S/AtYRYYiO5mgUxUzrsq/Zj6q
4P66+rA2nleG2uTO8gIJyleRP/D7g/GZGbdUM3I08y1zXYJAMXNlLUn1gfwrIfVB1WMgYwAh9Uj+
LZE9yfnZLwRYn5caEk1BhKFiQtZoszpeZSdE/jX5MvV+euKU33vW1NK1ifsDujRqB1S2TOo9UQHA
/fyzAmjpwz7HoHuuYACTWGE/s7/aElse5VfHZaJimKBuV7+jH5cN5GLDykIux8ZQtifnSqg6nqSn
hkctp5JlA9QNFn4RnKfx0zTuvc+3fBY8gvvXXIF4Hn60+JlMyOEJTlHbAW/C5KjdWF1RBihItw1E
dtiuQJzzg+CoGwqN4VN5mKHDpx9WCDWG/RcN7/Tb0Lq1UHJqeD2mD0x706epQq1GCwY4thTn7FDB
nREuveZEmXYSUEb9mWQtVtFUsyzjCRoo9yc6f+gzbumEJRxuK8hExmt1B8K/9ZOD52rsZLDmSk5V
EumxNT4Z2e9xTMZS3A7FgwFW9Biv+O+TrCZobYPVc5fsAD9lsVIwb+wLVC4qHtaHbMScoHtIqPIU
nsSkGtJz5veq+xGnQjmxky42vJPIQSzeExfzVi5KBYd3kgr2Ykxa6J04btUs/SMg3l72ijiBGd99
GK9K2VYw4yEtypyOdyWOnPHPwDgPtPdRUG69zU3vgEBGujL60JsRRU8alvIXi4gU4JNT2Gf5WgV2
Jp0XBMQCJwq9kcVzAlsaxjV/PRS9Akz4dMixrPAIRWw7a53ayL4puucIG7fF2IDyXEYg6A7ZUMeL
WMA9VDFbeEyM/aj2VCySJXqqc1ckChBPur0Crbus6LwL+31jsFfy0GUjMTzATwKi/Rfm8qldQCjA
WPjCqGHAXk3b5c6ByGbBuoOTF8zHy/TkzbFnL6rIiVNGkfjfjGnC21yOlIZIwWochvgPeg/72CMK
M8LTDSh0l/CG8Swc2g26HkYJbAMRcYr6ZbDF/ycXnJrwGUYN9zNOp/p0bVMOrRiYLtqZf98rQ+bT
8l2+LVQhWaOOcjSD8FQMuwVmkb8Op7LPe4FQR6Tt72ZFmEf/rEfT02AFgcWZ018jbZeu6Ed/8UVG
iZC6YRnFYFYSvOGzImu0WbZIoAgM9fQv5kfftSwIk7Jw3Nruz+qD+o1p8ViTTnzVtldEBm9SOipg
PwWkORPXbHvMz0Kp4d+ZZadeaYH+bT0CXfZhwCR888B4N2eB/BTaBp7vZ5FFP64qEUPCwzRhwUix
NpzQxwfyPVQK1RxgjIdViSSsdtQzfOESvVDJqRkTh1X2UnOuG2NGowBsg4UYUYQzoDMlazlbKpKg
cp/BachUPNQFh4Vye5DeEOhoXyyCsWzwhib7Xmqc/KK6PYjlXz26i0ZGPukvvMmJ6vp3fgMXzIff
KEMv4karg4abglP8rXmbd8GDcChi9eBQtvL3YgxtlaAQi3rK5Rds2ha/fI2ShMv4UBzf3/oRdXhX
QOx3OwDXGBHtZAeLFIrxxipD3+gC9WcDclTtlDeCFJWUe+HYiR2gbMISv2eXzyW5S3IfB7JRAFq/
OABNzZ85w3y3ue5UvI0wq1GbvFB6+5HVbFNNxUOXI/QjSQqJ4JxU8C28bwJZvik87EYaG7qfna4M
BMJHzQ7uob4JGuwLbbrqxSrrTAh+L3SQdFV6MfiOrt0edmfbHdmksZUdQTnYIJt2gExKNEjpnji0
3n2T+oIqKRz9urmY/svrVgM+TB8amP6g1OXueHQ0e+1qlFgijI+c5QgsmlO7RYpnA84q1MWAz9K8
BT9uG1qgyyk+WIkVzVJLJOvb8xgJhYXH1B0PoOPP4JEIp8tCQ49SDKrtRtR0sAanG5eDoYGoUYhN
fL+YFheeY/0PxaRrYP263FhMMWIF7yNpMvQ5v7GjxK8FDHV6YLqSfnRNpIRroX0SUGiU9NybXH/O
Xa7ScdR1fNygVX2vsc4tzkGW9pcdW+prNBgW/01PJb/NJpvkJXGGCLPn5rU/qF5LjoHFF7vuSlzg
2z8Vyw3H75QvTOqX2yvaQ7n+oTJCxaTL00ENq4CbdVg0U5WC/9Km10tEV6eP1oLEnGTxioTLYd91
UUFwOijbfF2WFsKQXZA4gHMsV3m6EQ9kcSsGUcrFvZCBvBmO21XVbacW2gJHtZAATuwHzzN2dulc
jN5hVn+exsQBvS0eFavBuBlLJWY6gx8Fm9twwGwR9shnGLbaceGlvmv+Zd7p4Fp9eg/KDUoZXrCv
q2B6fF+HX1TGdeQN/H5anPqxnH06mOi3XCOhcZoeYxfZWekl/jMtBl36tttVCnonw8UbQ6L1wxAr
b895Rjl19r/Fp6FoniaDp+u68vQVEh6+Eh6wYywPNnahvnurb031GQKQSnOuteDW3Ky/l9+DMJ/C
C1NHq+DGaM2SZsHfrT2PVsMz4VJvUMwUS5QLB75h4SyEZNMk7S1v8lVs09fV779YS3PQqRUHQPBu
5OCPNkIIA8D4ea0Zdl6q9dDNNCE+Fnh3srU7M7LQ9SlkybOS8YJ4ORqA/Z/wB5CvLI78F6v+6mH2
roCbhwqmzGHCD+NIHwVetpHWqiwTESVboqQJFOv8SbYfaX5o+Ucka+HLbfETS29eOFUUlv4THNIp
NHGgfWdHVWmEg2Gf/nWaKS2L9w7JOV3wLqLsTiJMPMJh5cRs3zq3dgT+k2Uk519gTkNn601LP7RZ
hTlWkR9jMw1Gt2oZrnabCgMRiJSjP6rPJ5s0uh30NBicIiJdF2DP9xnKykL2MJj2oUjBiZ7esR1Q
cr36764zUVXvHlEsQV+35R5SqfVREOfgc7ju+fnYEVjOzyzujbmwT9PQtB38/VB3pRwBOpcX8ivK
N46BxlOXmOu+IMM/tuQ4FJrk42HRm8m964YuDGO/4vYMwa7cBiCaicZi754YHcaDTIfHI91lRqHB
ziWzMzY4CWSSLc3arvlltZlm4saaroJP4TklZD46ZlOSXdFDj3942e7vTPiKEaCuCO0bw4pQdWTn
QMM59/s5c/90U2lEUoVFszuy5OAT/mCzBFgDt3avjuIfWcClN7Ad6N0VC+uRIqcIGJTlwrfrvXiV
AAahvz7m5lSA2hjxiH6TNGEQipwqvKvS6IA21NSnw76SPC4i+WCyhxIYsVKGKFDEhuNS+InwfSMQ
gmYEB/W32Rx6z9TZCrl7X4/2aDPbRNnXj9ZlDYySt9+L7zIC0sYfSfN8z7iH8O2iDksovg9944c/
2fvWXuaeZWVvodj7KFC5+LHHgmhzodhJeGnytQq3cxKJBLmrb1QjOB9f1JPtDpCcWxDdnBwogowR
eIcSvlu/KrdkQlIRJWAxlWs3oucCAJ8+oKnCbeSQ5o6Cwa5x4BfiJhNgn4sSsuT+RPjHvkkUpDwb
3dzhbCXWVjenv0YTX7z3p8+FzQyX3C/fYksABwGpeERcb5E8jbheDjaK1gJUDC2xM9VYJjPckHm9
eb6wPJitLRBEXj545Z4Vx9+e6YiABIXgvWYCLvQxppyP7PRBjVgCpMQK3aE2qg7Sau9ZSuLJRjCO
nZ7annjSCTL0nyPlUzEFY0v7JCCZkHKikxCO79LH+TzqAfnLnuX/fSVkZOY94X7I2/mKpWXHfB3A
jAnCPqvDZp6/uW7jtZJuMjM0VYTDaDi8wMA4GzHB/ksFP4tvquhmLJYWqWMUaI366usCK05WhQ/h
4ZrGgyXStIzxcBXR3UkiXEjG95+6BQKUkBAnUZZQmFE/UX5cIBP3xbgd/kGq32uz5B8OnrtcChzm
zPTF6/4JbmPk4HI60XTfjAuNzJoSZdFvcRFqk5LC+OvDYYxTP6WL1LhWyGjPCV5Q911aT3vQJB4E
xRp7eLLzfTNRvVRFTWNq0mVB4forW8NeG3+Y3M/L51p299K7YshBddnYlbqRZXtA6utsPkUVt85T
zBR+ow6FYBZbQpW13fPnME/CpvwiRAzqO9CzHL0swo96pwdffiOANEzDSLf5+1tj8N/Hgs/IMU9H
G0EDm9HFhp8HD1qnox1ie1MUduOKZ22n52np1PBOvfQkV+Ox+hmF7yfpSUO90U0fpgSqI+f2kd78
mmYikdBJzLVFnRbJCa/AIyE0lJLrpT2CRdgGJHePKCDLA8iiyv97fgyzSkEoQsM0gHkmHwQ4HJ2W
lCdix+dQgVQa4vHB9P6ACaz2/Wyi9xL6e39yqjQg+1xGWJwzrL8hg8q6JVs9LRSBcw6HRfDT65NQ
/Ynnpj4iosBd8QqlQPoWyzN0iE40nfLexbKm9o1Zy3Yc+8WExOhpXIPrdYlwOqB3e5V83QNWui2r
jEjwIwg9W6+2F4qIGa6CsUhRVrbGo2lrKmu1jC0pAYBBfqVvvZY5iDTcnreTLM6VFNBZBOl5bYA7
Z4NvEbjGiqMU/dLCXu8yGnNgtzt5f3K+xmJRG048t0nnzet1+202osZf3XyBCxxXUtpFHldQAjk2
mxJ/dsx5YfS/tH7ank/VxccgJmKfAmbeYno0O4JIEebdnd66zWrgOd/lKWUF4R7qvdJf0YR/PpiE
lJGLLTT0JGeWdl2tO9KgKiHxZBHFC2J5QLyPT0HFVjPvXJUbRL1C3vCBoLqwsQLAzfqaJsm5cer3
wVofTaPef4eDelQhjaALytetSgpfcDn6snGUqloz39R/ac0Sg5mVB+GdYoTgKv9KeK/nKxIydiMn
LLUCLbEIZWuWyqI37NGL8KDAoL3pUVHxk3qbfYg6mVcLPa6Zh0Gn4v3fHUbWMLwINGqfgTAjST2U
8hb9JooQEYlkm4WuoaYWX4EGTCLZDPMo207K5cokVH/ScR7mRTCFAac3Vcuc7EuEc0mKAWEtwgTr
18vCopsKy1pY0JOUMM5hTqZnhVnl/6ygw6gadvk9OVmWg0hiLO7+WCbNRAn3g8S8wcSeEwa3J0kk
mdj98aqejcT6OuLv2KnARl7pUQ4GsVggzASCeXF/BKMQdJld8GczALURBAPX6owaTYUzcXJWea1u
LTCx6U9JjceCGIbf3CqGm4jRIsLO/ekhGzOFoetXo8Q7L5HjmzbUL1+WJLJrdbx4nneAtDBjkKs+
NLSarSoEYcxKlIyfOxM9whRpojRzlldlik2CPGEW5fxlG4WFgap7mTeyP9QeRLXmTzjEGygE1Y1X
azhLsrzqP5Cq1OXRtp8edOIw/T+sVe2WkKlY6PiSc5sskJnXD0VrcYmAExZQ0NqoS4Oxh0I2awOW
vVUJVUpnpVmyD76BQ99g8rSqYQfeD6ZGzOh75F41JEFCEnIvI31IzNEWqw8+WaoupQAy8tH+buLE
R73wygX4ZB6WhXhIoMgQCBdbxVkp6QRaMVyZdhh9rmOWLEEq4O6+l4kKM4DH5n2h5cvG2GE9x8iA
1J5TElZ8UqZtY4VvljFYpHpeDGt2XdwojPAC0C8+jjo5oDGcGrygNsSYoUMIWwekFBkLZE7fd5XC
U70X89HFpTx6YSrrLAh87jCjTPkpUakP9PaQN7JGkXWv5IeLUQ8NSocVaegf+zTbTXg7vQQs3xts
OA456yCIK0QZyugWifFTjfD+wlW4dn4Nh6GZtpB6UVsqOe5uGQUHVHeKPL4g4+F7W7jrYGtRS/c+
3u+tShmxQqYiaHaAZyS6ej8y/cZxcpKx4q+zWORbZ4VYwZD/zgjslek8Qs0qfFfvIjqGu+DcUrCI
FWa5hAa/4CDIOJJHGiR3+7oE9o44HKDQWOfcdKEvgpIOSWDZOGyEeOcYVrm9iV2NITqdwaJsTSkz
ncqd9GTb8mKl7fuq6ADjFsnsf8LmQXwryIpraUZSiUurPaVuEvfRL72ikblZsm9UXTAToYBIYj/A
ZKFLwitAlWCgrfi1cpzuq4feIbGy7pQ3h0glV9GIPCMMUNNYX78x8eN+QSMgb/HLC3bJXG/pQqeZ
vnSQUD5wJ2Md+dW/459Kr6uzYxxuhrR1EGMuvspJmUrU8sTb4CFOYkQiqMva0koyyxO5QfjysQuY
bWUdw2elrhZcs8E2SFxUQ/rDMnmncHVBSG8Jvt8gxGn/n37HoJJK9RT/B6Gw7+L61SwquW6RoItd
jl7Yu+jXkf7BFlXjNzsXijf61jzkpVPam2/mLowuJbcTKPUSNR9C3F4kGR1WZkJvWbdTWHmmhTMW
yRfL6h6q96HdAOYgAYI0npWgPIdH1lOEk42linAOPiedbeWSM/A5jKraTXiqgNHDC5rP+OaMbTIE
TFGwAiBz9lgL2AY6q+cZPwwVrQJLv09/VUrl/Dyo6FnO/xYv2Jsh5v7qIo9au5eNWwkCZu9d/Ero
lBLsZxK/2IY1FHYOFkvDPhHd03kvq3hA0sDxOLg6ZJWScCR9GWa2PAk9AKXawO6Q3mfCEt/bbwmd
scwHzr6Iel28EWYrU/gnCmS6R/2Lp4wcKiVOfbOzvLSuvnGpnVpoidFU5RD5LXQfflHcmaao6Srm
1nKxj6SbrKDzyR9K5wuvJTyqmykRjFdJZFHNLMImaI0TpcZ5aWdXJFwOh5qsdgMqbY4YGKd0AR5f
oSzSTAqE3BTB2VpB2sLMheowEf4jr0mGTDpF+2C2bQy8pO7yeH+gT9yu824jffL7SxDOJOWvr5Y5
f9fRxMSATwll9hAxw/BRkj0UE6KxOQ9jgXNJ8x4ODsocvT9th1OTUiHsjQM19kYVYypFVR0i6XN+
1+RKr4UJyGQREZ/5iasLVNwCcOoinN9ns/N3ZwexlWmGH99mwyBg4u+aF2B36ajhgsyA8uWuRhHu
JDPsVL0+swfSFsWXbn7coftopOSmA9KY64YOE3Cg8jbHRUh640near7AweiliMp4pv+J1iiY+44f
IUPQDjZJO0b+3FxOma1h0gpIr42eR7Qn5ZMlGXe+oEiT2ywODNOlJu0yIV2oAyD1mX9cfvKD28hV
3H4NiOiN/RUtBhAmmJ2LXcFXrYE2mncDe7dHKhtotA2tNveAa0GKaz4+Cs83VyUNcONE//NJoIeK
AqyWmAtaYhp9/RAF+S9Jb6CW/G8slYiXHIVvNOAWb4tV2jqsyFUZFSOPKBNuqUl5H6EvPhD2QLmZ
uf8NqkNib80H91DJ5TzYSKjXduJuZlBDQD4sld+j682QPL1+1HSJtPKJgtIxBE0ufb4/c07wXkXy
InHW5VXtg3/m/dcCO/uSxMr+kUeb1QdTY3X76+yz7paIKlrBXeaJEkRuRgucbukHpfdn2q5/Sf6f
PQl0rW4+Ivfn4SGe+sBkNM2gE40WbSBI78l2CKaBQwD7xll1quzcRkBTR/t3Q7RIaTm44+Qk5ICP
FdHdTmG3X0YGvL94DFBtSx8GUcxiFZAxFwAmA08+YUFw8YEfDtWOn97ptW+y4fsf2hNw+cWBuakg
7DeyuQZclOV7NaZ9ECdqS5eaI3lSCs8XW3urULsFAl+nN0MuvvUDQawKqXt4TduvQB0VKY8F3Cll
9yUGEcnHTiNUrnHWQVL7UKciDWKKHe6UNjTmQVYkC6x+u1AWOpSebs4meLdb9+5Al0esaDEJz59Y
C+SvMOFXYg0Hj0onNL8m/ANciYT9ipyd1o+d0UHTTMfinUq3NoT+TwEG1IsBjVWqJNSmfUcQisur
YVubvZCqLuRtyxuCtBJ4SZZfGtR6VYkKgzb11LFhjZzCbcw8hSuz5jrOWsgspEn2ZUZxFyTCNone
HuIKPly/UlxaAcmEP2mdNySt+C5AJlwEYISxHTkYXUT0AOL4Huc+ud8WnSEFDZyq7A4KfPty4w/l
7rKPL0yXYbLd9O9+WMBeURWc3pLisq2EsO4i3vGZI29kFRo10gh1vp6ZkjcQ1W22fwjpbiH+kZKX
BIKiYQ1WiILTs48BhmY+6sNye8bVJZE9mOmOqndQlWs8Jbmmopc5C8YHrXigp67UEk1r/5QK9Vgv
xfSR7n1ROM/GSP9/M2zRpyAl02ahYiw7B1KOoLoBqpPrG1Dn9utUYi9OYvtITdo2ghaMpKoRc31o
b3yAdb0I2yWb6CIYW+ZeeqZ3hcR6jVUsHewLWI9oaHwUmwBZVcZJdzwKjv0il8SVXviOXkOxKFQf
PIvtm+QHTHLJENnkOCEeZB83OnJw8k3hMSefTLrZudgUcXs0N3TwKrFFDydodiTtwoghHxjJlweI
RnD1Tm6SC2igsozggGepamm/4D8cmhgDq3KYp05iZ7Qq9DI25WISuZA8qlHdwSCJojoqyIWRoLxt
MCkoWOhgo0fMI6NDpRD3KeZRn3BFJ3/a7L6kQFJVPPo6A7sbWidyWw8TFwkKhKqj6fdO8xbIKQ6G
rjoENx8qnZSlS95f9F14Q3CSQn3e8TB+5vlqwOKCEv2omH8rXxj9mXUxkau0dbLhTiuGsUnYX7dH
UO9OAnZuzGvC/CxJ92khudz5nH/7+7rdIDSHRkzIIECe619kqzMl6CeTxx2+eAAEb29Xysw3z8r5
+3XuTWSdZkeKgASBggsavcUnlQdPWxz92LognKR9QpgNXPkgI2JO9mah8UclQqskprQPBI8uueIQ
vmibJ+DGb6DaXGyyUg8nZmohFVDKRdAckhJ88BmUHGiuucr7kE2p2xoqjUT/ftuF4qPVrrptjxFK
uTF7vfLfLK//oGDeRzn4gs6sO4WI/VT43TAaXd+V4m2zhXQmSBrMTNBkxU209W83K4nvyBgmNq27
y40zJdxsgrtYe8j6zdrkkHN48vg7NafUA7pfOvF7J2xGtT9et+V0m44rxMIQpHSPTPTMELoT7R99
XrT9HVqWc0BOa/zkQC9I6bSduTTbFd58LSmpYb48v27gqakv0BwMH4TUZQvpyuTO//vEjK3nIi8h
zKTSDvckE/DgIsGMdIF+iENsDXgQc9GSc4zMr+5wB8wVjs5595g37yi092zhVipBgq1UsMLXNdZq
nyyp5uZ6htR22RN0JT1wUbp0zAOeFi0zwixnfptdfK12FP874deidzz+nkbyGGw35SAofMrK9UYM
76Ws+uV8f4mB5a4faJFwT1VAjIHBZZsDA3zV436mmKSVyf/a4mLtCHaj9FsGuplGragLJCEyG7Pt
heYL2Vr5J4Spo922S9kJPbxnJFlFDAxh4Qc3TTM/GMHCTtydZPkE77eVO1+4qBzh8C4MeVui2mFu
s+nMvUNNypDrGeetaw9SuSOtE93XoAIeGGQduQKh6cDBCdmmcTW0b7N5W9h/Kz24ILL56Kc9FnWo
qDI12rNsg1mM4z0440CTqRS59wvqVNjopFM1caYIK0X6UCCmMd84Sh+z4a82UcJ3qSG/1ABtOM5+
YF4hE4kQsUBJwvLTXHfeNVa97KprYuibTXpk6qz+a8tRTDM9RivjB5N2igFOKYZ84LWbiVqgRkdt
yroUeAL1H0pYIK8sjUjvDiCBqRWU+93gh1+O8znevm02Cb/jpHDr86rHVHAvA767eP62m+RzUima
/krdJAIzw62OltUccIp85+/VxiRI1SdXjdNhrqP3iCxP16COCflyUCqNDsc5wG2Q2jO0n0YjjOTC
xOGiVNihaXN4SuaGiiTGszuhCbH/LW9xEY/mUfAK7wXVFkaa1UccfuzfMo3Hgccc3yE/aAzL0rDf
0eXe8RfIXvF41UFUy5h5RwlLaWyMH8Nnj1ZN9DQKm6wnFjYZ4FnKYeZmM56WCtAvwcAqSacAWkKY
MD3yZyafxMpisb9o7mTDkOxbOk521s0Mi4+GV17F7tD4Tdj8Qv8fSWEQTWgqnMMlg00AMrIPD5C0
z7IfrAo3LvcBYjHGVtRzoQNw399ZkFKifIHW/NTSLUJPjczm74+Nmm2dVnLnacZiGVaBbYY5/PD9
PUHYDbG3F3yyGC8gjrB0a+/htFufLbekY46F8FqA0jfQ9ufcef6rVlnonNBpLzUI66JQXT8gZmQu
3hCRkJEsfO+0PgO1oUAEcDZjhqOlAXw/urZF6wmoJ4olGUU3ccgcT8qWa/q2sKi0Y9MyUuy2WM9E
QGtImxKkgGHmGlh/xaV4BjEm4zsXrDpvlyzQ4O/Lp/Qm07ClWuvqe62QfPifzV8SdTB0Uc1d0DKL
GujY/APujOXdxq0BeoO5nRKUigXqBZUPSTQLrJ7p8K6dMEju7xpAssj5MkegL21hE10VfTlUqbjj
f/gQoVJbu3/7CbNxjkSZwntQyYY/1FSoWLFLcxZ9LBNcB0+yACOfeHAEKjUjI3Ay0J16Ize21uol
4mcEf9tB4AfmyqRAE0orF7pu8/1mwlbVwwX2vv5MGssdkklkbtJ7RrUSvggzGEbkS9kZIPooZFq3
5UXBwHY9HPM1HWiiXpTVJsm4L6v1IGjaGfrdgjXmgGG5SbEMKfbIUHsFC81Ov+r5PGIEALpoNBF2
a+8VWOyYESSosXarXlHbhPYcFGzrmyKYCyfkaxWilAeRrmJN0AE934sqjeKR6ulXDn4lhIXaCwyE
7Tb3nMNEPhijy2nSJA25lJYOcJ/TIMK2UipqE8g9iQcAPXgvD4AZNBYwTfvHaLW7b0RTy9u5P9V1
jwfu2Ssf1HfQHUOn5HsnvO8FF26NjokY5Jvum28hTLCzBby1bTznsBpFPz7O3gbiLaa1qFIB7tUo
7mR3B1js2h8h5ABhrbpTeNd3X68c2OuXpGs1UrgikwIijQXp+BFIBqCcA0YBgJuPRO2Kh6c2eAtt
Ag14DI28fOxOEtOSJ3H88vai++mnQDUeY8Xj16Umf+/kkuMYyYTOxGoN5YYPhymU0lztJHAdXJnP
l4PQkfPW6SIpVnJHF/+hMjhiIDdhfb4QyDH1+GvgnuJrjGz7T0MUCQSmKAVa7BKalukQ0CD2IG7V
S8WSOWEDc/HsnU2dZ/hJ861bM01ZjzB9pE6FwmETsOupW5LNgJ3O+6TSppxTThVtuk/qS1/lNZL0
uwGMexMLyo3cFErmPx5gV5HWKrvvSOUTm3aHiB1STNrpLI6gpCQb63dft3xaQOEJ1hFqTAh6xyO4
6eFNC9kxsBkYJkfFa5Y/mmm9r9cV+MMTdMhw9zXEbmvn3qwxF5BELj9n82PDmBtrUXTM/YL/RY6/
oiJuaxDI9eGQ3E3KpQYwPc+nLtNMylo/HODww75Fkfjy+kOlQrDldab/JVU/EDr9XT3yV+ED4hbF
C35jOjC0rXQvUbvC/A1hbbthbKZjT2XQO3mF4upIVT4OiPSl1IkQ1m6JQyTCb4XfN0G3Cdm8NDc/
d5ZispQWx2tCrcLJb6/oA3K5IsQSD/2+OAkIpEIdZYUcDstCEIYOFcfZO6mEXrUiD0KZ+rXzHz9y
+kbcF/ArZ66sf0OZPvbc7zBlA5jJ3LAbXGDj+mYanjdIi8JWxNuU7rR09aLR7N4KwP75r91xkoy9
B320mftw0jnhk46ASZbTZIL0DXCmIaGYy2P5PL/ujP850OXajjIdBOoNWTJEAt6iy8aSgp57U7Je
Yf9wTCoOr3IUbMP7slaYz1UFuyS+qoJOy8vjCLldXzKeUjDbhI9Ut5FN+XsRT1NoY8e99/ECiYaP
aK/0cS1wIPPJfKCbEd95Om8nxpDR24Qsqb6KXExDQyztqLsNuO00m44vt+WM1L5gJkY2m3QViP9u
uvqFjUTiyqPW9Z9A4MvKAIeSw7VNB0MtYal1/mLhX0rOgQCDTQdLw/57u0ilyjaZfrwagUlxJzD7
8KLHbxKavFmjvk5Ajfg7Km3xvhySBRmoY726vRGaVV6MJl79n0SJaTbGxUCGKNfMP7EbItpr5bI9
pw/URr18J+j2DGuqPWbIQ9JptoNN4PiHqSNshEBB8Z8ei5nTiQUqHyPy2JiNYHQH6YZhMgRLvN09
Ub8EhgpZ4zotMADeTN3f2ujIiPmGpMdlrslpMAQ8p3hheqbKv7GLRXPZXQfzvixZK9O6jecdvYqZ
YxbEMsa0wHKnitSxDVE22uU11KyIJ6H4DInB4L1lZTg34FFyU99O0ipAaoQTeGIYgEMFyz1adIKW
KvgX9BxZaRVwHTK5qnde+0A6j/AS1gP0qkY/hlczuaexA/y54weSdj8+9joLv+f8B+kZMJymvEU5
VKtlCEhrPQ+itrKJEDh1SwxNGaxfSQfA/RhfkNCA4pQQj2wmHpev+yQiaaWZp3rjkFgfKi/FVYET
mSlN7X87vfLAkO3+h/9lT2Hyr6Wt79WxwU2ANlKm4v5H4aR/cyDt8emlCS1T8347rr0TX4EBVyiR
xTnHuna9oQfZA6xMzM4F8SfYMIQMYRy9RvuZqJaA4QypRj+KaNN9/xMVYO0P73d79yWdXXWGyMBy
vCj+tyl39RmXuV22gdErYH+/DGOaq8DT8M44THJwbASLgRLwH9SpJ2Q+0sN80iI2R8p8JpJzcI7h
twY1jC8R+YFM2w4eiDsdeEonWGrWGwULNeidPuo9Q4fizcNEbzD3mSsJTbjUWy71zZ7B2dsV0y5R
yx3EPxIsXXnwgEXVlQxnJIPxyzfD7wef4Mh8j90voiEmiBedNU9wLzD2BPHMIxJqx5M7hcYVs6Zx
aijn6g3QE7d8FZcUJZOhlGWOl5mKeL8uJb84RiRNFKL0OQHIddgAwLs0CxTtmidrpCj/xw528Q2t
EYUv6aa1DMXVA13eeYdOAniqXUX/qbOhyHuVSRnS0OXxoSeNUBsx80Fvg6sT1wn4rPctxdCfUIfX
MmbwaQw98HdPsvFDN6fnKZY1d5B9p0voGTX7E8VPDYoazRqhk03izjM0tWCTI6EgH1x0fZIEIYAb
ive/RBBle6aEzcSK0kzZVWD9GRWCghxjZiedM91HX2E63wM+ugH9E1eJaPGGOqzJeupqLTgcRJmK
GW4EsJO/f40RICucuI7VDBbYvJtFJmnBiEt6X6zsl22mT+gn5o5LZVeNYhKlujWDsAQmr2o02XPJ
x0z2UMlSafN9ZJ2jcve4wr+xOlynxfWS6xdoBrQXmEApq30Jgtc41O/SZ3+Mrvj/JMzb9/lt5jtB
UQxR9/Mhn4aIJwlU9T/4Tr8OuZB0i64fveZxeM9HytY1iLprLRf+n/fIOjZVPmyQzlnK9NA/OYGb
vAsmfGmzLS2GU71aVqR24KClExXZaIhnaJXb1JzwUWNDPhtLDdtq6+jFY2FKwUpxbCxHiH11aG4M
3jY+SC4doJddivJgq6IzXa5vwJBLa0foRhk7f4lnJEXgk5tKjmiN4ETNKNyJ1MwMkEj+3ZHerfro
kHpHNInWQ3Ua9/SPDZz+hLoERnd4rFrUWHtt6hzinvk/FjSPY+YXjSqB1A1djIajYem0khSG1M9R
4vDbP1zqN+ySSfJnzxvELeFD9K9Z+G5hSJUiEI+Ew6GuPGjalcMonNhr/7ZqTCFrvteCqN0P2IvS
I9Kq3fThT0GQzTWa6PP9VbXcHlpqYlmDBH5tmBuyECufo+ZACnKosqtIyYVG2OCmMT4eC1PxOhoz
wypx1EUYN9K9AX7po7+8EkXV026whuHtiaUym/juo5xX/lN0wTTepdudB6cfDsIkLdr6mp4tfySh
4Xsw//1vFhyTVZYtVcCIBbadHUZgM5ym1Lku9zyZhFiD+i328tUXCSsUDSME9ncSVOwATtO7UIbm
Iux5KBhjfZjsYAkjUMoNJIorJBJZLiPDRfmhr8NJlJA6QEq2cRjd7uRlJLZ2Nd3TNuWBlzycC4zk
V3ihbTBhgWQI/y0b1fasTgkfLUaRDmL2AtVR0PxeIDHHTs223U0y4mY08m44T/JrqhXeslMcku1J
RtjAKsc1AhvJ4DB8LPetsMX2VeIyR3j4DgaKGi3vMEx1a9ZIV7kuKtVPzm8DwpybQKxOp/i8OByK
G/yhyoeLFSYZ8b0DicW4yubloXzj4slHc1p7Si8f2D5gI83bmt4zqkMKsZ+7V/jh0oozZ0CzFy29
DaUvY84HGQYJpireirqe6iXj7WqqATTTKSJgx+e3UQJnzKmKeB3ikdhlyO7gW6Iy6P9ZOgQYJw4c
CP83qhEbqLAw7uZHVy+nbUXhpo7qK2Y/LnbcKrBQ/d0Rp6mcQQ4DhqKzRHvPr6CASqygSOHxo78m
4pKjjD5H3ph36/gLQ28M7+fL5clf2PQaBlluDhoJCpJPEtmXCyJcsfwjYj+jtNQCtOigWeLU8K4c
M3T6fMFBQbhI8MkKl3wdCQg1yBjvjoliPQORZb8bE/gwjcaN1YcXx1UhmchilbKwhhieQH0TCB7V
6fdpJ2dE3IAkqYAHPvbYiJ4OjQscfwySetW9CLZ/FwDEndr1OgghV39VnHqqAQTyPqd4wHkIlPJf
xLmgCvOpw+Xn4/keijFeIhEvYfwCEudepG02EFyo9dbakrzAyCNbWdHV/ujiQWjoByfbdhlW15bQ
+9R+ej3EA5F4s+hPZ8BKwD8uDui4xOC1aBE9Cvbfj2DByD6NrVxcf11A25ltxzhptH9unBkjq4Ey
qxk52sYSyKpzDUqhmYAaaFklLN6FThGfN7ZApUOfPgiUovCtvQ9amj78VcHVztvz22mqKm5fGlZf
5eumj0d0VI5MVzCmX4E1iDK6/qrpW9EytGmtSB6nGpYDP0gsCigaaQf3Y4NKn6mdo57iN5pPyiMJ
MD9V5hjeiSFZ/BiS8Gr/ByxKG/g2GjKfZHFHeeXlTRr5mNaOFg1EWW/jF657SEdIiuQYG571Dye6
ceKaPiJ3X1rXkAtqrZ6iP/qN7kmy/r9uA2Y5RHgRuUClzvR7dBciuNoOC3DaHamxkicK74vCiXqA
PeQOu9bZpIBR5tjolvkLlEyL7ZRvOnFCjBVOY0eYhWCHCBMCJLynPT0mFpGnTySmAfvFGsI5fHTm
5zrB0slAT9EPljouX8nIKwVfyvtQJB1gYi0PQENuQFa6VnU2OeLGnexQhWzz33zSj/QPzGVE6HtU
70jXQwYug0e/BoiLN17r/50aAl+GDSDMjr20K9DpuUw2OPgWlWTBtDas8Cth/9mfJt/qCzjAgcMG
BDCTtbXP24YTcdhZzC/En9+IXJOja0zqggvsg1G+7SOIIOYNHxCQV3F5PehX+OKc8/R0xoyixfv1
T8Abnbu4vuanYJ0QoO5Xllv7b4aBCXRvykEl/hmRS0ztNXg3NigxMqk5VrW/qsfiA3XCTxA5RYIS
WUDpHVA+o6uQLG3EL+p12RswVlmb8eojHXNll/nzIrimgJgyzpOWGBASz30mkhaIxtPfg7M5qAgO
X+C7kKlt2WKl9fntUNnXBkGtDUpOEYRxBIQxf06NnIRaF33aakWaT9deYmBXrp4UteVN6Fcktyyl
58EftCdwrVseMRvoLCNolWBT54PKWbIEW7jq7Rnxf7BxQxCW+oSluKiR9oxSBr1dsRCqsKqT22q7
hFrgHAw5eG1rb1quNnnAQ1iX9XeD/ZjMtLA1mrfk73IPlqo+XOnAZ1oVmhg+bwfD9txoX8B7Fvyd
zlhPr2GqZXPTyCwZK4MMJZxVGHW3n7VMHLQwOb+BJ2yuWJ/AvEVjQEYO5Qzh61OMcetzAe//FEzT
k2asvMh4avyl5biGCEs4GsH3U3C9YqqnxoaTE478koyv5SbiH8FwHWmfh5xPdCUGlLoN3YK3wsHP
7X+NY4MsxUFJtm6CJ+mcJbslzEPc/ohDrLSoP0/RffVYtebd3pD/kt2wl7YPHrHC86RY/0zgAFPh
nKTqLrPk5Ck8WH31OtzKsyVMJFtjRawRURgcUDtHnGmooU5CXwLRHnDFFyta7TRSrCweFMLT6HWk
SypUzVGwdaaXE+6P1Xk4U+3JAcjlbIV+CnbodWagpJmBld2N4IPDpOkFSWC52s1rfHCBn2PtMNaG
4lH/K94R7fpaGT+NTFZ2vfsNG30Lm9S65yKp+YLiH9Tu6GV8m695rgINT6O68PDvRQ909N8AqMVC
8zTnKidj23QLwGHNoY4dSvLqx3/lCsMO/MKhVi6AJRJ7Heo9AU/79FS0omluxxurRrYRnnwsXzZW
mycDUk+7suDrONidKJbp2M8l1n/M9RiNKgG0d5tLwmQnxQlvxc83bRsBZU/uuUqYa2S/hP8OlmlW
DFZQqzlOrlmXGSatpMeBZMfyOzpxMbPThKektH87PGTtxzezE2yu120OOWoBczIcpnk/yZgGM7/K
+hxNwBdCZuH8JacjdUHaI8ZsVxMCZPcJF0w+KxGdWoKJUZTu9+8akCIqG6aHUzltFUxJr85M1QaH
4p/wD7FRipykrycpWw58YxMew4PrvoDRJnZfiB6rvGskIsMEP3jiJip3U6jAZ1nETaAbR/K/9iOb
hlMza/WFPlU6MZI2JUhfooi82v8WK6je3Ql2Xj7fpJ27+9BnpUAuyfe4MDvQW66GyyI8XwSTGoh6
DaMZ5iUHHFbtlC9z+pdsvtk029Ps6FZIaGfmbwu+/zt79GWcb9OQMXpIXrgwf/9Xwu/VnlNCs3Dc
yOlGWHTuSPAhGbSd1r+w4bYEsSyfu/7lNANvbPsuh2JsGp+BkbBbfZZZb96uu4MOL12uFR8n/vKU
AIA09e2ZS4SM+4DSKGaH/Er1rBTmvwlYvkhbViboLSrrycvoKkEo4f6KMxR/lu581h4i+Xe3uVg/
wh5L7IWqrvXprNG6BXt3qLZi0bRK0pltYT7bMN75z2NzA4mjaPezM9eLvR+GefkuZX/6pB64wHCG
6pMgz6cXSZzgLzr/gpr0Vv0RwK4ciwt4UZMtMA2sBNJxwdmiS7GZirRXIwa/8WSirxcJCoa7MJOM
ov1G6W6OO6si9b8v5PDAjLM6wBfzfxJL+vps8gK6ZsXocBYF7WpgXuP2uLHTe/c+/RVrcJtd4jHb
QI62soen4EPq1QjeUpyxgEySb/0SCpaBqn+xAlyHB/eqE3amM5Lo0YXQSYz4ooKrhX8QKf8Q6koD
K+bLAVDotLfe2663kki9/+96XFotPtKDFhBSrtorg4OXGj+BwbavEO5xvWuHeRp+7jtc0U7xn0xy
l5VSDnNuL6cWBunMIn2b6YpMDW4cnxO4NqH9UiO1k9qONQ38kDQW3aXoLAt7GbY3GTSS040mPDmg
coux+N0hYHrsGFLBGeW3F1T+VJN2+mlAsX3+wHOIusJ7IyhweZVdBx7fKEIdrUv/Pd37VBgncepm
81WmxGh3mhUYtnZ+puEkfv4OlqzGS8Xa46wkHmE+qtcPvBPQdezeruIwXsXy5VYX92D5T4HFSRd6
HlsJ9IeXeJiZ4VxVaga/rA2yUL5Zr0tx/L1Nhv8sw3g5i3m7GaGddSS0r8/RrU1TH5FZi3oUNGW+
04p2Ku2rkRL9QP5S44rnFeGeDESI7RnePI+xz00KyfoPKwYoyixmmEVu1tehQsht1bJLxSFg600O
aCvOhKBqJ4XM4U4mcp918c8CWPX7ieFEmMnqobWp66YAqhe5IJ0FHuVhssw6PjEDADf9h3Kxy/pa
oHdbMU6gvdp4qIai59LlYF1o/zu8gTwDZwgeExDrlomIvKJgh46n0UnlAUhVr3kXw5OhM0e6vg3P
+RErdqACseV0Zdpi4q7FATMPs9uBjZ2TBo8xENk+8COFrL0sVIDV1QOmSeqlRV3W19uTWnpOn5W/
mYRg+16m9HfYHiLOQfVXIb4IfGj+9yynsvcahaqjrulb85oZ63FyQLYMrtMWhrZ8ai9/94v3x/XV
9aJrrOQtAdsDKp57DbB/G9eQTJVJVfyBsYv5idEMJoVkh9tBfH4tZYQXsXKcKAPCJToXk7EFqfLc
KqV5id7hKWIfWd/wQuJZOrmqL8njpfxbz0ZHYWwvDmwj9AeNZEtnglOTmWFe1Bo7SWZ8x0lomCsw
bKOnZOeCNa9LzPbplmuC+cQz+zx5mzQA3j8LIyB0pUNPnsl6DAGMPFLm4MJWanWAIMIz/I2Lw1wi
So31Oqwp4K/7pBONnP5D6gQXiuzo/Cpljzhm2aHfji83hBFfBiYqWyBe3s2BjQ9/56OgYD2m5LEA
r3ZsGlKlQMa+SVkWFiZX3GdE1JX01gejZZUsHxhHISbYLikndDoaz+goSywGuwtM2GyS8LIGd90+
Wr1EFBRnUzglcov77+0HyUarlAr9+tUlvtbA6TGiimLRcCdPqA5oAxfrIs9OpIB1iEGgDb/1LqeU
3unIK73Ew+ZKA+prfBigrO2PlXz7CCLpopTYDEKhd11/73jR+HMGhj0PlraCI3F98Dt9XpuLZL+N
ntodjQjhEMaX1uhPblrOcl1J6Qlyd95BHGNdNMT7+g2JfGNxx0WOwr31b2na6bDpdAfmNlII4ayI
YEdtV1he2vFazNr6pd8l9mLU81o4l3wuhsi1Ug2voIxo7oMNdRRQ/V+a0ZbJlIqOw++Yw5JPpyoU
i4jCtUlhgtZHEVtXJTBWv5G4g5TggiQlojSH5Q6JBg3G/XyCSBGpZ4GFaPKxVSiEFjXWVE3/m39/
0heNg2d5gD7hC0pfgHjXKwOujrJQUk6Vxpofh7y6qLUU7vITLCIIb8SxZJ5+6fOB26eSxRNj/jfa
4xxo0B2R1c6zMMFjOa4JF05p+H8rXvqFb4qelHsm3mx7e3wkUPx3vqbI9Up19WctIhwg31K4Cfw8
e84OLjDQtGQ4287eMcxXh+5/rZarWFl6NFza6CER35zfzNs4g4MqxYEzf8m6FwWH5alD75R1OAcR
GG1E0IhZtLMDQa7uf5AOf0JDPUZU8yiCs8VEY6+EVTlP5ChxXsEK+P+Ha6qp03nbw0he+07UnE8x
QnHmltMXbR3zvNfKSlpm2hbMoppIFSLiQxzq4PuhotXyVPbiymtdFm80p8y+f0RgTApa7+m2yexE
bI4De8Zo1wwVpyICCrDC8OSvnuts3/f9PPWcoQHrvArIsr+vKl+HEsJSi6ktHuWg3GoAPEXZoIpx
FlRcNqDsH4I431XOwpDwGgoucQTBAdHvX1AdqkI9hStiX33w0oMrXJVEtFjqwAoOg1ZZkMgGcFRr
e6wv66JFY5D+Pj/Cf+MLUZAnosGQjOaFg2JxNBkZH16Bfta/jWQGB3J1JTj7F69GnX+BUv6hPsFv
L//5uwppKwpMz0UgzO0OgxipZWMxmrTa1mUbPf70nMIvztGDdrMyzgRMY4DVydUz+X8Tv8IOJ3cA
Hx3SOGUVXfwodvy8Dvu5znrGs0RGj4arBbF02W/I1YLF4ncyXiTF41Yd17blE1S05NdvyUvzBQTv
msv+vFyBaz6xPPZaISYBvltPCiLo7icdwvnnqXITAzr9mY3tQckysa/yLp8XeoEvtqLBLVv55v1m
YbvdgD2mQ9kKWdag+oh8ELo4icZDvwd16Wec9PDY4tCXcSZatQarLHAawNaNxR4nq20NC/KSgasJ
8vyNZ9d0hrk6/8mbqSiaJmcglQyTYCJXLbiYmAEnKEAJQo1NyEhA4O1guoLMNcagokJjIf9mSQrX
o9whXjcMXQkWaoi/0lD6DPHIT7j93MXBrvowDZ9/cHnXrR/GfdC9l8hPrPFIkrXuetXxEgVfljuV
PeTqhir7aTSSzAa78Jj9kJH5zOAKpFH0oq6etKLgFecJDjHdUQ7MmG1TbkxGXeVxpJkJH2ZBf46S
BQxkFsJdyzl4scoCbjwa7zsjK2SGrOX2n9L9AmNV5nqWKRr9RA57vg7RJwrdY0rArK0V1zhPxyRI
1PC0mCyGxZckZBj7nPqsuNmjrJUjLXCW13eIQCpIn5tj1DlUCz/j2/o7hphGzSsIBtqtbhbaEaIL
UsLCJNbAQkVi/Fpas5WxV+Rd7NclLZd25D/5lmtu3QQiolJcKZSjPeSXI5+ncqS1nATsPLX9pCD1
fLSt0nIJ23PzG0Ku95T4RW5xkWB6ZzreYqxgjx64D1DIom7ccA7i/Q9BIwa6Ar6y9rLxIEWnjl+P
3zIM4fKQv4CJi3YNz5YHwNbZZzHOcKddXDHjbbwbF1uIJo2M/9W16t5iK3MN1U9JRj0IVNCu4New
56WB8rFg59o6ByJI2nFF+blLEMiGw6GASujXgGKLVq30VrMbdOBBCrAt40v2qGBz54+Ya7uYCOeS
vV5z41oBlCE6rbNyBMNynAAKw4HckCsFGE86b3L6Btw1ERV6CgHUYBkSVjFTjNSI9SfDgGdBxqI7
nofCTTFoSjenKLitUfnAL9hdQ2MnWJjo9Ro0lS8D9W2jz3QjJz4co8SMzAJipiWopppEZISaiqxC
PjjZnZ4bXeWd8xnWpWY2QcNQJOSYCXFwYeJS+EUCNRnzBToa5S0bP8vlYJOIRE04jCiwJr3DEjve
lxVPr+IM9UQmvSnfhpLnu9CB0yA/K0EeQk9SzPdoE3fIdagu9SqaRNmpbR3R74ofBAohCKKlGCL4
AHjxP184iRtSC7ti/VQfzn4beYNdaKYer3FF74u6+BuEKCjhnF9X87f76gahCTiO9X5P0BQJnWRt
WoSPdSFtt2YtKAi/9drVH0UZ80mbPK2yMNB/W0TloBvgs9b33JC50mt6iIrHOFQhak3dSu2o7LzL
KKMwDjpMxAgnW6Qf67tEjr45aJx6+yo44NL+jK7NiWarQrDhWRGHF4znZAqeMCX522aGoVHJeXp8
fI6yY6FfR1bq1QS4I1LgKLsH3bNRhhLSsd5zlr4w2VTm2eZo95AKlFtI8ygBhVAWzISgoCi9vG7j
Xc1nDKNG9iUjJatOydiXDTaCbr5xi64VOnXLplDEr7XFCO3jB4rQNFf8s8t+IDfXQTeISWpMcdi/
tZiuR61vedAqpC7RTyIsbbgo25LlNmdd1wkGNSPyQ5m6lhPSBlS5vUBfRolsw62DuQX3WCipOSUO
nztefB3o+Xhy9hfGS9z8HsMKo81/q0d3kjG0EPki+9CWBI8SserPW9PSeoGs59B0nHPK2S0m7QfE
fhoY8JM0vNOP9ouwG8AZlaBr/v+WuZwVHyfMrkMTwqrfgwTbeFSI5bwNOj3snPYeTllLK9wCDwAg
0+sfu2UsT3a3DIIpXZjSUhn00pOxyiCTFQMedPtEZGotVslgnfnuQ5tBRLMVNWuQrdVJjP1bBHnq
rU/N/jLdSQEGwoc+jrTgFPk+Tll+OOSFxqH1X77yDBr7mYITS2x2dglDcRu6crEQ5PpLarMF5g5u
msBGRpq6ho6+qB1/Uii08KWwnObS1GhDMs/q9FSthKVGrX729S00QhYXyJ5EMpJVFZELnvmnUu75
gYZxQtKLH5mMyMinPWd3n/X/07hGUiQi5qB03dJfgOVzEVTg0Onf+G1L8HTBRoJ+nzm4aauzxaBV
yYMu20Hmr9GZKNeY2qiezeQPuvuDKUQrE7/6N2t2Zdsh4fdlj3XlQaqz88SSby937JyiPNG3EHXu
l6wvpXYTIX6nCMwImiM/c3O8leL4FtpqnvtbHWjcOP9uK69DYDxQyR2rIlydLXPfkzixlr3LwwJH
/0ninV5D7usIOEw+PqWO2h4X0UYzOHpNICtPqrGkhtXINV4Hyn3B6PWeK9Xo7WRT7mxO5q6UEBHm
owR8jnmt/wM4pYmnOk8xVIGzMirFyKhb3EwAwYCnEnaHqhDai3t7iHxCIpHe9BmoTCTPLBx4UKJ/
W2tt8PYu98nSzb1ktYOpyAwVh8H0FS18YzIJPl3n+tj2Uog3hoQyTvACjxJyzJM8OTI99aNI2o5c
GRRbnUkDW1qMipN/EaMNt7nOEjm5+V0SG25nSjOXStI7YN9z+YxdoqGKG5BL01Nn61PFEl2jqosa
N3/IfUAYxL5XMrUH2FnHF6A3SnZyF6AMqaOBS4R4XTSv8mrgOOFUTFlMcmVwtGTFjoWPtgk2KzAm
EMDA7od95XU8jXcT6k6qXkbDkYDm4PySKrcRX6aDux7Ng0oNEJHQtjrw/98Lj2/7BIz9eiWetJ0A
jc+mjNW6nPLqf5IH9vMINcfAv9pwfrW9KYAGNTLrEpnW4ex88Q3W9udagOJi0HDYDIwLHrZoVhPJ
qoWATzyDYl6lyZxwBn7ENT5yAf4/eaWN9OokKxheWxyJQVQWYncjVIDoiFSeL0Jn3NLttM1G1Q1u
hqiBGN6hGArZC7Ms2odaN4N3GATZGqgCfOm00TndK5VJT8Hx5C7Hnyo3EQGgKIkMOD4nAIKw9IgO
PsM/dFOdt4McrnQXEbFEgnrQGktU5DQA0dQgAciECw0qsrnQrCWrCZSqB6N0ysMxccNWUvUu7Wdq
DC9iTOsfQSkK7/LuyBQKTdOx569gF75b9JubVR1lppkVQIeOamJG699QA4aVOBmLjFnInQcD4a0b
LM9qcVyKPLUNBfjH6WcDhNIzGSX/kMj3AZlLfbPZtivoWGUpH6XaVQDn80fVd8k1vVUsq/yd46Jv
j9sP8Ttk2XKJLSoASLLLX1jjP7+JmpQU4VKTnAtt2SGcG7ZR3L0Qzdt2AaXklsbneVURy8pGE+Le
CLEnWJIl7zY+Pb4cT/X48W8mFNzz4WiUz7nWvMrgALphCIKx4kixxxzFSAZvpO9mutZKnBRTay0P
JrpXaJaGAQ26n2wVPQadIduG9NyQ/qxe1lek54SLZ1zYibsKGOdS43do+s49n5zHkZ09d2D76kMf
kBOtv+FJjUe0t1WK4/4GBQ4lI/iqZyWl7WD+RX3d6krbTZ0uRKVLKY1D5dShyrgwHfjinJd+4PTb
LTISkVW89oAVavR1YKdPVTRpX5GIeSkP573I3k/eisdbwr9uUE+rNPyqVgkP+qXuTrGbbNhBUEu4
EwTU3zr96uhUSGDFmPpDN/Lzakx9PuOm1HOd7VWIUeUUcvunr11zMZothLo1h0FQTCJZ93nbJLW0
BzagbtrCe9NXE/qw4TNBgESAtoY57IPWD80Jtd84oB/PxlEdsRvpfcYDzGWZqFdV+n8E569CiRUk
Xb/ytvE62U260pCj4bUbhT7Glhu/igE/QeVGZSuaSxESyEMhqEfsa1FWnJtQWBwR99MRlw8iScY2
KB7L7RXv985p6tJ4NLeSWbbrm/cWz+pGBnCEtyd1tGok5ztMZs+JJOhonZASXyPcalJyuGJt/LmO
qytktRxXUpTzsQHIhwfYNGZfHF8lEYAC4Ng6YtapCM4hTrKgtLfUL+mDG5JUhwzr5ZbtQzwBtuKL
oIU44SN6ocB9ctobDd2AbL77vA1NKBU1rXacPW8mCcydKsDrHEDkyJyo3NR9DBt/y+6yI0RN/df7
67NyNv0hgg1IpeiBSQQVt+RhA7UgTpD0ngHqTid3hNh15cLtDoii0xhQNgloSm5PKE8FPdCuggyj
XlWrkbYSjStP1wGZ6at9EzvaOSb1djeSibf63SYwaJ50qdliCLhLzZSrU9Gq9iCHhGxufNUzE21t
9m1G874GGZVdgpolb6fqskDOK7SiJocO3jH/v1KGR5AUQWVVQ9VaMLfIMEwqao9zu1SsSocvQzyf
RerloCUWBCzU1xZ4xbJMTdnkVfU+ECtdn+UWvffE1Fr8CA4nIhG6M7uI4KYMPD0qF9rHs0XPcccr
BpUcqd5IsBsIWuxNt91iDatyVei/EJcOQ4ASoVoS/Q0+wPerRND/GVRd/xCQvyotpxyCnYC60gjF
pI3TIY3djj2QNUk1DsDoFR5B90kDlpo9U9f2/MfYYkng86Rrd+zSoQ9hENLzLkO78TLTf4zo1Jz+
yvpsy/pLdkfce2p2tJ708vzqdrTFgXAafPeIesPB9uL62usGuTDRHyDnjr7cumZ1nmhnlEstwboS
lOinStxl44Tp7uIaNeCcu6TeS3WYsHSSJaCNb1ghEKJKC/9dGkL4B1uDGY/q01w/eX/VxhrkQUNv
RRxDt8/3UNLLSlisDsQ0MaOmiLX+bFFmWobonuKTdlV+geAMkJjDM727W3zPtTCXly3NQX0UgrGl
OPpp0hZNHd1UxjHq36DN9DdXpkWYb41LkbSFR5ps2k8B9wQkq+/pIJTx479Y4VUFSUKCdjyP+hK1
5oGEw/0prH1K9s74/XS2ENA0cwwg7ws0tAR7pQCWXudgeIYcoKZ8HnFNqKsJ6lW5TRh4H9wQKp9u
iHMBNSi8UEx6h+yuGV+OkrBMw4QGlJdUQYaVKGEAwktvKVQ3kPnFfqec37AbXOrKMRvvppp8EzBo
+c4BECOhVpKlO+2wLfjH3ZsECHFWOM0V3jiDXmlxspfmYxAk13008fGm4FWEdtJ5iG1Hf0D/ycC/
n1jBZTaQJcI0xIwasUYJtaLuTAKJgFqRS0wRbwkNMJk3vDdkyPKowDcFomvx9IJZQq+pG8h1C7b3
3JlP7X1sz0yrN8BIgrMrZAa9jIw6vbatyA488SMLqE3eKRnAPo2txBIq5lKWyHu0GF2rFzDpe6+u
FRJjCaEId1+CE/GpAGZqlTARKsQbLw26FONsLLYm89JFMa7N9+Y6YFr0KSIxL1d7Ei8XCOEhSSgP
3J+16UkjXLNa6gRPcS0kiZ5h+7h4MUuKviCpsZMjXod6Sy8eDPSCZX/EnrDLRPv8P65MbUu4DiXH
1XDc7QxNtgCtSiZn/WbsMRafH941S6hS6Zx1I6GNl6NHbEw3gsghtav4N0m6jygkeCLq9/2IWcY6
zzUnwlbfm6sjjySQRv5dOVSbTRClEleewmpY8o5pnrwhhdSwS+SeTxmgdmNbom3TLO2J2+NHEiu1
GnJebSHziQXgUQYLINQRURqTXQt3ngO/cTr1niKVbCK2/f0nErZ5D+PUoN+3sjwlbRwBF/NlJtOo
a+EkOBMCX9Un3gcsuyFe5iyaEJCBWUGvawANlxYQCYGkrwusLqU8USFxJcqvaVdZzYh16QvqYY6K
XJYUV2s3wUKbRhitkOUo5+IWWw32r914eVh/cysfZ4IPULTElkCRaBKoBYPmXFuxkwTDT/t6hyoY
0ETAvRBv/7tk8q98hBzUYwmCpgrtlU29uKVr6FJ+w4Oymth6o0BoAoiyrulnFuuzMQyoLZSVpB3m
LyayqRumKfQWAKhnTjeSm6IJ+v6WS7Or7qH44mWwgAwHfffGtBt8AambwP8caB/rPAWI2vR/xj4t
Kvbfb97LbKMBBweetMWl7JORr3CWOtO4wRDq7Ax5ZrK21kEEE7tVA1jQJByAkwzssyb/N8Otuvnw
cIvKqtAgm0O5uBHI/pV0wIYkoTL/Nc+AetG0B9oB2xA9arPvjwJKPsDoNZgd7rYhfSux9mxMkLQo
Mn/EZME11VdKMe9S+F1EWhFlPv4Nrd+X3TU53rwVmNX0y4oDCQZH9vGnozhsLA+fsZMzG3ijweh9
XzUd9/WM08cvRC1LP1r8BCLPIozSQfOBFiOvfmoZpjRieo+NS5ZAqYTN63lpiszpdiEajgG8HqIE
NDXFkKBte+xd9HuQzC/RdMtUwtgVCkSAP5ZgMUEMpsHacQ7ppwRi7qzbUyW8/Z1bP9aPgYvyuAty
ifW1VqHi0lU4lcCDWad3wTYvlpsVQ9TIKt6ePPdOFwhTBa6xhfxQxIO4AIZKPWL9FZZCFp60sQOq
FOydpVtAfCt4bsJs+1QN4Zy0XnvdJ3duz4zi7LIsDpoBNBHXGrpgM4SNfyUcy/DWGaZW3uYu5K+0
uliWnKijlLaVq4WDefboOTsjlarFsBHWMhgUg3UWjbiDGtWRh4Prmo1vmgEGUINpIRuaJLyiYTy4
3k7X8w6vozpREvXmXLxmFxysjOfWrkvL2FANEGnm/t2AZ5TdQam+S06rhyBeMJR8MdeMcPDSPBlM
n416bj603+zsEUvTqB7fUrMgP7UZGaDx5JYkq98OT9rRxI+DZDCBFk7WTPjvULTSLFyiOdhvld/u
C2yYDzACp7jxP6/S6pMHk5PaZ3xlMHC6xR5SSJzE30RxAF0IS+0oBdSKlH1sY7WTp34w68lO3XXB
zgzRgN/iUOtfVMIOCsjzc3k95nTjKCD8TMOv4Jb0XoPlbHyYybkHn0Gx+pUYVC71Zbs8pE2PfTPQ
a0MKvxuoju+zazDUDUqIgBt8t5PG4/RAlOq+1AosD1ON51Z+c+REglrCQ8YgANzijvwX2bK9Mol+
iSyOKPPkVY6mCQFVXcdVmo2cR0DA95GEGMerr2n9nbUVi1+TdMBKrW2E5+Pr85D3ivKrHdPCg6Ap
hfDIyr76C8W4L3Ejqlgg/LRxbk8OFsHAVCxMir7qbHfWV9ky8ksDMIzeafho7zVNvAktCgeu88c0
QJdWPgYvSHWuNTjJr9tT9fpZHEi2tccwzTGZags/rdEJgTDtUN0lEafn2xylZ904zSevxA4spGqD
V6Il2/KeCcdUsYM5y/D+Yoym3lQAMaJmU75UfbCmMuLrDwWwfxbGiWFoN7nMnF/0SmYD+E7TL06c
a/e4NPpfw085dNkPPujXv/jrWV6fIzFZhHP6/T2fELJtFoQ7F7LO559Au8kzWczKWDZl4C6PXzjA
FAX8PskhRDrc5z6ubDbLkEXx/wSi50TLeN51xfcOchu6r90RwRpxVTcj4DRCJk5Tl59yb+qVWE3u
EOBSang0nFMGWKdEI7ZRU20mM3aVsyGOYnMPl5XK0z6auev3NyN3Lgqzuputb4j74rjrLZK38iWs
mJhZaBl9g3vrG/NuhGKoL7jSox5HsLY0ZgVOnpzpem7FyFhHmgIlVLSXpMTyS9UJkX/fcMfKn5V7
+jLHWAA3AXScpZ0uMabL4VO8nNL+YUfs+U/j0VPfytVaBMBoK//B6be1dvjmdVWMtJB9GGcfGLfa
ZC3oOgFDCPBixHEeguCi4B1ykqK8h99yDscWpXXVJUT2/ANys3oboFJgoYT3EudtY7LJRsPL2g1X
sszi4KDgTSegQoxI2yqjQn4uKCjV5XazRApumUHzw9FrwTW2afPc6R0qUGALKCKTfIhWOm7TWq0d
g8Q5iww8oZwlt9qSVh9TuzQ2z0Rn11lxP3kWkF5ukqRzHAiwjLu/aF5+r/wGqnB5PzqGRUX3R7bR
UO33rGMuphS7nDVcj0rSCEVkmda025kuy1+2uooQ/tEFGiYBh5UgkMfsojCBSxSSnHsJthYfyZFt
Ajd/pPrg3YDw/BaSdkDHCP12kKK08+hU/xffmRrxkJQwJPqnGAa6oUkgrEslgVySMpkjcN7scdHq
ayWuPz3TnRCPocwzADehzMz6db/u3WqhYh+cSGpvy84f1uJ0yz6t2aa+dqNg4HSntcAAo5ADoOxN
RBg3BR5ByrCL021wR6CCtqveLYK9XYGoQE74xjWkR+6CKNepGpxinCLbqTSxTyFCrBx+Pw2T3bdq
buA+Gb4OyXNCPJlb6HrCQXuqtTBRmO8yTl7W7LY4BPIe63m/sE8E4ao1/HA0vi2LAHm+WeAlKV/S
qXXZADIugK+BFwUezYRMs4fJ/8e9SjXs3RsJ6NWIcxy4+B/8iCgWaOwO9bFitvLebUqI+P9VykcX
bc16LTmgnf/Z3NXFRSsiQjoHaZpbdNpexD5UTgms4XZWZARfxcYEMdVFVVXf0ddWG4cI+ubZDQbd
lozge8VeC1Mr74iuVbqHODRQjBj5b99vNiy+cqhmy+6qP5jtRxpPuxm44IkhLYM3C4rha37AO3uG
+fJYInLrd9jQjdsH9QQSVQrHIDevY955FTrUa3RNCj2q3xHlU9M95kcbYb6YzqDHyNMpaVO12FIH
EIT7LQReIqpmQhCWhdU/40d05rq60Qzy+mUAu/ZuDUm3AIq0aSepdecsYt9MDxdeTPOTZNbdjqWf
y4DRQKuIN9H6+LtOwEjzQ1JwV0O5M6Cv2LLz1+UUr8Xyu5OcmVH/iSi+kDL9ei1UyiIyAt/nJigT
w1LTZAQfusV7SQkdIcuMM535mnnKZn8jruI65MoF1cnQE5SciVLbK2N8OZHVFf1dhJEnAjtwpE4L
kmsXEMNt1Jz1ApdBkbtV4v1wx5Dkd18eZyia/Ct9Szmhfh0+mUpUtzco/GmZetAi9cc5UJ0/hUmT
r/ohWsjwRUCb9sXOpWCwoWY2KhOY+UZTxJz4/IjhQn72aZ+7U5d7mc9eZ1KT/eLYdN6tGaqUivMO
dpxgmitUc1ChNoVCOL8tjNrEnNWBjQNSOylxQXdkf2dJwM0iL6301iRD/dqk6sCriZycjvF/gXEW
RPmg+NyBI2fikbsPtspg//2oderWvmgI/NHhfTB06ULKITCONTjKl4Lv/9lZuwNFxlqCeu0jtjod
em0r3z0vDDTPvhX4lxFzQYAwDbOksUvV9lU8zsnPtHkecnZpr8srNnSINE56I8cC2tIonnR/crWS
52Y/d27zpjXYBut0brJ/Z6pN7yjZCS0lC8Du9ydzKXMGZGYOeHKISttQ+tuBb0rH9qbt5sbq9U1P
x8Y9cgQV0+s67j6WWiFXXhDjh4LjvWedMcTkxB3ICX2pAwO+eQ98FwKq8RJjaLfYrPwVAtMTcqo/
+Bf8E3IcLX3qRgLzcpdiqe5gwWa9W7hz+XpqrzSnDXpdgniwlMekkSMycyeX3oAVxGryPPFzhKgR
inubhD6ns+VXoGKfZKv0SlCVbu4G/rL1kEOpscBlWni6b0b/DIpT3SiX3hbM8Ewp1mMwIqLqX3Kj
fnrF1cPPDJA14fn1/T4cxJt70QiHvKXMm8G6WSV8ZdZyf0+vkmWMWbCo3QAoA6TOUNeBdJJktfZi
wHMDxAEvM3iC3Oqn6hm0oY5noJmpjnigBMs1ffsfoc5+XxJjCDAB+JoRTEljPLgrOCqwRnbmwuhD
rL2exY7ZjJqVYwXnSEl3cwsP8UyJYIpG7nnlAX7Q43hd+eETmG9le3fLfvYVqYCY52kSHQ7pjNFF
xvf6XZU/CcdFSja8FVvll0eAek07zqFneKutUShP4iDkPQTxSku8oR0cgVi+HPiuIqZn+Y/khm0x
ws+e0K1bhgnSw94HN+Dk/05zLSZluOJiXpXzB6Wm06dHBW8mzVY+tQ2xqRYxfwDhkxxzjY8CPZnc
bSH0Mz8+XJ8OPlvTJZbJo/Hu1wgnQLpZHaXTyEvqbZh5nE5A2OQvCZVuLJ6ffYwI+i6ZlFwdjsho
hA6T+dvKbRX1BmpjfnMHf9QLUhn6AjUx5XtuMAdjOcv6Q4dmfl9PNiwV/CB5XgxTnQ0jwljgQVZs
02tGT/a1kU85ED+YLzlHenQgJ4RdeOyJPiW44oDl+gP/PLwV3P9mYAZddratxPEJyJ7tTZpm4Ht9
KcjnznaMoTxxgTK5AhAWlvWnAHngzwuDoEN4wj8LKk5Zt5GFDPJSyOPdZfFBf0JANEICzpXQ9y8E
2WoMbh5y0lPiWOmWftVQFJ6TSmKgvgl9gFf/v+lwiDCBI7eay7S+0WV7u3Crw3aVJQgZITiy2ljN
xaO038FuIxHLRV5Al9cyXcNJiXzDid7V4IZ9GhQUkXU5p6RkADvMPFqbnyJYMQLt20nPUNg5mwjQ
geawtquZqNBRPDkAsY36g7POzoz6RyBSBW4XlDjz3tAhSopGcU/3ZTQwc6nrHReAi1z2K/HAYjY/
WbDa2nFFnnPYcgPxr0h6cKyKw+HME9U8ixcJxE/24I+5mNzYZj1X/h9/yhHS6Rha2zbZv1l18vaX
HRKQ6wzNqMkxBBg/CJA7hJjQYpZcBTYf+hzTdemjMmdVBVwa2AXQAQTpyHixqYFv5jw2Mup2OWQd
TUcBJPRhxOPBSedznoUo60sQScICZ7sTEYnHgTwn2rU/ydpprkKl9h5CCKt7nkit95WlG/BOAOqb
nRSHOYrqkYVTq4QGuLtZcMcUKhI0bFO2I7jPtO1bdg9/DpZchDC2c5sztI6qf6Nvt9HqAtUdbRDG
HCEctwtx9D8VhumnKllwN43icKXG6gIs+w9IJ5vugWRGS79a9wJF9E8sGESf9TUbKH2gHtzu8t58
/nM5XCHfKAk2SmH+mw4TrXrX2LOY/mQFqkkM1t0BD23nl16xAC/alnDNZJGjQurEzP9zD67uav00
Z65TDv9F4r2iXcyBczBVakX/ulphdjLPsFwxQUJB+KA5HWsFmcaWJqakEFjlZEIOBIQHuf6Nu50I
j7NmXqanuWWHRv9IcGDs0My4r6t1oLPXgvQgmUT08X79mdYajXQPR4E5Y/nQjRnWaDJWhb0VCynl
I3u8Z/wfTT67IITxXPbXp5Nv5WCE9n8zMM8dmbbOXYE/znX/LtHEn+mYwgPVXZCZSwLkIPxnIr0w
nrvmLfPK+TxgTHtyEW5Ia1KFvyG59jR50NVWZ2/X3FzN74fOaKm9w0rkqRsP6GR2tliVCWwvqVo9
IppNcw14gYyccvkkNkJEqlQnOTzOEwy/t6AqhiQuptyhdUaeKgatddhUj3lBBoKeCV+omsIbIpiP
ri7clsuI0OuuTV5y8mcPgoMelXuWseayvIuKN+7pPgQSCWOFFdd4M8KFJJEguvvABOQl8wfqsTpl
B/6Ez0GLyKzCGLFDNhcXVlK9YZGDM3ZkVYScYbbmyOQXLyXSMy2ifzRlpowQfqMb+pUNcB00meuV
Nh5OL9rMnodNY1OnqGc8rQQMbC/Bvr4/7yiSDA+q7/i89ofzLzdCXszELyzbzyKSP9F0pUNXNe/F
71uo0xjN4EzzGEAlDNYZN8OApXbwz3vCgWSntNGVVWWXfMQDOVoKqHXnI2f3beteiFTjQBONUfnA
+sRjX1zL38j5iksMi5EPpL+z39dYmnHXCGnZA7H1xa9hjfL7DxlauLGh6O8XNTb3Pibj0OUFS0NF
h4U2YVYlhFHMVJqM9mm5Qi0p98sIXeuaXcq+ffKDnlvfT3tOQTbeypjv3/2klEObmO+ubCqQKOAn
yqhrbNQKWt63t2gP5k8Y99xiLX8oGzyDxbCrxWYK/6WeYgK5qDjL7VMeOlFCacVDo2CCAbVERIFt
Jd9UoviHLnQtb9wHIxCLqpdiNyg9wr1yUMtq3HYCpKCbtlkmQ2nrThVbPyElxHtrNRIww+hfrb/9
hXdM+UsK/gTpRq/RJ8IAmGKb0SP40hSkb3W3p/ATwEKIs19ylGydvHoEXrU5N8WLsI0cbY6FkF2f
OPzEfXAQvPgI2R4K5FN88y7M1PUGW3/kFuvtcX2p5Bf+4XlW6LHQ90qa1k5XQ16P7/yHWDGUxVxW
8i6bD2HI1pbEyhdR39bbSkwRF4NaomlNtQ7AwgOSMYO8DrahsOcDeH1mUYEXf4xR+8ZegtmVKEPM
IgNIhVHIzh0Pca1kYzpTgx3hGPXe4KdEKqu/pjCBZZAkVbDXRYnz0cAG8YfF3EH+8JBO1FxWtB/T
omVJSHv/KEJQMCUpioF3v7At0wYDnAjJLNIgy9xWA4BzyPVDf4hyh7tC39cwZ6eTydGeRc9D5ggm
Q+HHIn21X3ZFRNFhFzzDsty+ayKasSL6YzAbxpbqLch6R157T/tRzGJ5nKhv6dYAYHgkBQ8+zgJ3
hLrrj6zlzmJ0obF+To6iQ8iNu8W1tnysAYDVfP5rY2i6XrnPCj+ltqtPotxL00UN/a4Vl9zi1tLl
HS4Y24DMm6+zTgUD95Ydfwt6d2323uFWHuYRalBMg18rAPa2ktoGDfUQkPpNz0eRQvqTcBvCXIGh
AO2y/lPX+UhUQ4PxXIf4bR4+WC+61+0WvcNMSkkGkJMTFmYo0tflsHgbTcr7M6ZwYgIIoA8WKSOM
EnNsR9ADVhs2uKZzlau6KVMs+/sCosfYbnlFCnB1dOpG4uhaHOkDfaO1WIb36IpJI45tBkPxBRnR
DUaQ7g2jLB+KI8vepPPuTS1qnoPKIgtdIsHWMNytOF6MLoXwdbmHWB0L2XBm62D9qiK99VPvPQHi
vHjnKvMkbzEqPO/1sMd1vXdM1K0+ik4fTSp4QJ+GrP7EtyqhMyYK2gzwmGZ3kOJjBlCandt3KCpx
ewubQ8duIrleqoDDn3TMc/r/jZoLnfRBUsZ89GwRUwZl6El9UEJtlXyZzoMK6TDNZgB258ErM6IB
TBZBjYvjlGAxXrJ8GVxbEBd1Dn99sUbLs2cSTyn1XHr71CybVN6znsQStuGKWOXh3IRggTp6UAXd
4DEsIZn8nMGfP0z+2N/Ks8MIm9W8xVMM4ngQhEQde08HXhFh1hgKVtkLs4NqRLAUYPbSnF5yIJMr
pF4PzbTPgzZ1H8lbv0K5lTc2Njhf21smY47uMkZtFXAybBbobhZA9IESW3dX2CqVnQ0/atqcawIM
QUXnrtCqEFoJC7vDGFBPBsCZUmRRuur1/ljwy4oc9gTvAqt3d+uyR4YJ9ud0/K9KwlFoYnIHi1b7
qiif2Kz+570rEk1YKNhNzJV2XtLuYKP7QGVfmRBVirER706t+SNfNBbbTGmQJ9TFFXHKkXAxLfcT
yWM/AUPQdwXUZSYj9KtFzZ43mMYR0PljsWrbepFJFdSmd1hsnqDsH7eXhpoKEdXxIUBxi73CArw7
wJ4fAFmGUxJBdrFP76HgTMXS53zm6jHLVsY6ogbTengBb8VBT9kujBIFL3fyrURGueIu1mjeHyN4
uZZJoQ6jXP72tLGxlYdgsbjQAHyIKmpq7F9XjNDEZL4ATHaqDfLnMJtS/wSB1G0ctfG8r0PmEiJ4
RCc8s110iNYi5XCgaPAAxPGzqFfnAgYr+VixumGB705LwilPrwvS72KvnMMohRe8nJFz65iOE9WT
KI9qiS4Xfu6ODmnZU+OCc0HlcLKK1OY+dp5Q+8UVkCDp3DhZHqfr46RJCSdjU7Uh7FkLElJnGyz9
XQhMaWApmPc81bwEw95WBPR9DlAscvTlbsS/mgnymrNth1O5Bod8SQ40Yu9Ktn97AZ5DB1+/lHmd
6Cuyx6aXrJQ9XsoJlJYd2X0fka21RhxW6v5iu24OOznL1iJc9wv2RonQWyKGPijZTM7fe8+kOIZN
gFfHSi4Qja7X3bPh/M9X/kQbaehtPbznicAKZRKleosrQsGgBApARuiDCcU4KdLHjBtpa1nVB7bR
6eJ3ik/3IeuJUx+8zaZ7DL3KSpHQi+FyYn4o7tl+VT95BgS35QMk3DpgueFfrU/h6XPkVCqU/rck
mJBjZsTaA/CD5IXmWz8XD/7tdJh5BQULK8SQR6qBQzCqDnyQmZF/SXrUN/BLtVcaT69nNfySrkTo
avVbt1eqDYsN5muC/EssV54RXIowcUw0dj6hR0u61d5Ct2cn+X1tJ1IbnIg/GH76DWY993B19H73
LN9JWuwCwS8oJXSpWoN9RuhX+RsslbsYxm7//QNJd75KWJkNQtAGa+afaGTFKALoEzDTZ7kE98WF
rm8ZdeggUaY9JiFq/avJ1GH5ijfIzoehPJcWS3GCEBnZXYOUjwSiyhaB3zLgBIA+LLQ65MHD6lwr
8gUaJDkX60Rg1qg6kEUK70Pr2xsyuBOwvWyE7dEs0ODMCrh8mVKNfui3WV0MiK2ZsNLIY3XQlOFi
iFXXHp3icKcsVkJowyHuGZjMtKTKVpf0p8Uv6U8C9XMKtHK7+tsh2vzQNws9raJUa4SpMNY/1J1Y
pTRzxiP8vcwEmpVxBRoOAx22EzbgLc5ur8USWfRkCLzdaCRpiX6IlEsj4GFHCUejxD5wy6ZTNzRI
FF5QptPYY8zbTiFGf5ov2m+3wk02eND0AKB8CPp4zWQvZPMuWRmN6b9IePzrkLkWL2BI2GIr2sEG
CbenUvcd6GkvXB1E+PLjbwIB6FzezGzaW39FjQfDzZTVH/f0kxEIGxvjYXaad5+z3uXfnrqgdUem
YqG5FHXJmeMnKSP1uhNl+IoLUFnVgZsiAnx9RbJTHmDNGBNdAT6FBSTYm3Mr1gWjZzoh/OApbqum
nKFVVG0UTcZd4qNM+wycFUFnb8XxqEOb9F6xC4aUWuOrE0Wn83kjiT1brM8uwH1Fpyez4zoGmitP
0GIOQSM7on4yT1jWk8Xu667Y6oHDoZ3kPKnsA7KqF0iFMU3+6xUljmYr4c3/By2GVVkF4Ar3Zalr
4UaGd6dTzJI+tRHLK3Ue6SSRzWaWmmEx0Z784j3WMJnRbj+yNjNGd4qtUYWBXcp2HzCvMdSmIuC7
8IcsLMwhoXdGtm2P5rsxCmabPcZqE1+OGDXtQZ/Zlc4cxdLKb4aN5T3HOE+p911y1pKVSGkULG9H
L4B53bKhCTtNBWcxS9IGa4HP8qkM/uH9hJADtv+qVrUe0Y9JX73O2KJ0RSb2Tn0WYS1XyrWSFXwg
VbhJQ/GDwB3JH5U+C2xVrYAC8cWbVCysYVjqEjMX3DZGspRcgwC3Nxr/AdGDZLC4/KukX8ACPJx8
gN2m9V7lvq8dMEACHsXFKaRqqhD9cufqfpdQpP9j6bjBj+8sl1/LWh7paaQoAjDH11Sp4ZLZnB4m
aG0Bq9MzN3cZzjPm3u87dUAra5/q4REjTdH7ZLctTVS/QEUZv6Jv4gEtny0sX6ZK2gLWdz9yupIP
a8L9LJe7wTCAFRWjapJON87d7yKCT19sbGGDY0d5QGDh/OQa+A8frMUUbtXP7ci/QXBVx0/DRc1Q
C9yFdXKR8UV2U0PiBVKpQbq8h0FDROhq7TNTH0rI0BJFxbWIMEhG4VOpKyFwj13jir8EJNE0iyXA
Hb/M+1+tn6FSlMIAJ15sXgXiLVXjxAeVj8Ru/Js6QW6Ztqyytu5tcLMIuNYKfAE8aWJUlkeiXRgu
HEY1QGtuUJpbNx2VMDSc1PSljGLH/ogURoXAvNzjNSatgeKM5CiNV66rFyE9h9Sdq43iN/BUsZm9
2PoYRlj8//gE/JD6HMDBdy3vLwgliDRqR5DT8rjDRa6hci9828YkuOnAIUsV7xi6Qy1BC/+1/i76
FYd1ixJXfaggwpLOwTV5qQDAcf2WK2Dju+3Bg7GVP7dMT14onwUjZdufLSETt3N0UVM82iCFkXr5
Ikpm3Biz9ukygKDuXc9N7YRxQ/s23Fl0x/0PQbzQW21+KBoI8l7OgAeThiJdiTixOPA7XhTphL1w
OisFTSjIDHvjfv+urke+Lwt78cdELSgNy94oMDQRmsJKbWbG4kvxDhYmeLcva24RizNmCYmMbRQR
SGtz33IUbC3IYckmjaQoAJEjMUK03t1KjhmKgz6o3EHW688MTMDI95TY2BX/QRR2BbT8vR5CX9k0
n8fJDWj3j178Ymwj+7LOYy/3yQC3ELYF7PaXwMsYi8ZgGlV50brbHtwjrd39nYdc/foW8hKP85Cb
waDJt0vB7+JJrpVOzp/mL1Io2s4wVofNMMlSgu1NVLkxfrGxp1Z3TvUIzvfOpxZ8BOOk8e5WbLQE
EnZqHRv+nF4CBpYhmXzaHTtODBo5cz5ur09kFyWuRB1KY4ipDi7vO4QWiQMKObWLr/yCoUle+9fE
d4ipli6JSo+1evC0V/A5L+bXgrUnxZcps3gm9rJXLouRFWhAtKGDU6LknRjQRVWMggP5yGVj162h
PV8n50CHxjXnpjX+uM7oWmiGONPzkXL9VUwJv3m5KLM4XpyrSTHSj5IzBwbhzz5JPW3QaFTiIEjy
lw0feC5Zgej+9anRnvsPhvgkXY05Tfh8yeKD7GcDxS52DbDjAzyj495CbhOMAdpz0q6ErGT/nbwM
u78neS36dzGRafixO2/cPJNorlSB6TfJq0nfJzzSELNPzxXsUC7RTv+SZpdqaAcHDNEURSbg8aVj
X2+NOj1nii7OwHPaEgaE1fN052c2alMCwdtWnLazddkVbn483KqJcIg5Nd+xlazEd1PldL9Pis2N
JP4ZAdDyLDPIRhjj7v7BywJTu1baMZM0WOqET/2b7AD/yHNBEs70/DqFYssAv6wkXBDF7vYn4Imz
wNQJI4BRQSvkTnvx79lP+j406rk1UCjGS27g+jeBSEqCuAlE2wQGQfUC0O5GXLfy4goCgLsvUC2K
we7EaEIZy6Y0CBJxXvGpeZUEbGNu5Gl7kxoPVH3UyIa5XOMCip4D/NS1/oDkR0EfgTjiMwGr7R+N
fC78P/KLPZTA2goOr6fK1DSD6SQiUuHHBIEkPcFg3ciPU8WaFfgz1KjVzqMIYjoGrJQF1DkJ5HO/
X49PE5kspbEqFughDqmmNQCdg5QP9GyM1g0nmymhxUKfvvHlNuSITOA5qx5aY3LWPjY+wt7Os+/u
TsjCQk1l5ZwdPiiJ+z88aj3UwKeQYJv/uNLnJEco6wE0DrUDlpOHFu1bY2+UlNJZ5OYtCRuaFdBL
9tsRQQBRMosOmM1laWxaKo6YUJ1DOxADYELtGQcnIl/acEaE4NSbwo1H6JGVLwNQt2l2UqmJFXaZ
I7YCgg3TBq+VoDIsvOLgkW9xdSIvz8Gp0a13nzkKWMmKofQxZaLCWxRX9fLQaS/2MmrSiuoVwANs
T2W2ltnbm49Ih7H9hTk6Zjc3W6gpdj55THMcMtN5IKG2/00MPSRFMiIrqRM+5UjDLww/zrNwonq8
B9p+VJWMfNjcwK7tOEiCsEGyKO4MOkajkf44a8rs20iTqOje19DohAZeO9sY/LAS5+GLimJZyurI
lST2Z/28WUNR+TeSM8BFP2c0o+vZyJlHqteic98evdULYH25W6RocO6dQa02w5muPcaQiaGMeMDT
9nUYUECoWcaigWBfv3YehlW71hFZju+cb0qADCr8IHgDTskLsuoKRUpki9LIubcRqu3IXoHnlMC6
pCr/IN7VKpaD1kdRBlwTy0NA2KPKWKYhs6yXIHgW8UsjuhEXzREDZarJUrBv5QnH5Z66WDTd7bJe
ju82o9vm0I+crwkkKAXDGZwA5wHRxBK5CA51kiGJ7G2nLr2NDG8BhKmmwNHgnq7sZAjldmAq5eoI
1LbmCsfTUDUCwkuumh5vkm3SrbqX0OzyjxHTa5kjzaKTm9v2nDrD3dw+3w13olfH98fHpt8yRWXS
PDPR/RBFaDLjl0YbWngR+r4ElacUXTSy8EKiM7L6wECRUo3AddTXLC6Cdz9svYBdMZyLs8a8GF7e
IEghER5gPa4D3r+BP//JdXpjbakvKu6b7bWiGwVBJ7KHWHXScWCbiBS6k5ViA9l9PPRm67zRfE5i
xp4RPU7e9OD85czWH58pSYcOdWZ82Cx1zBgs7WOLUpyXiMxrpT1CL+5gayp6Ad+MYIdELPLhLprR
exM3NTXrv60MK9QqljHysE3eYlmw1JbGQUrvbC3iBEvW4lr4vBJP4mvOLt3EjxGriLThm8zP7liI
MdMioTINW6q4plXlpD9+VXFgSdW5l55/ukC86wLrP+NIW8gPKsQZUxsbQFwQ8bw44oDWrueiXOwf
TxB1QM2Y+gMf6xXSwldLAl0GZLxqfxrStoanhGmNjnzCTlQNprL6tkhHo87jc0GVcPT3I0wFmN6a
Ph63vi7qe7QfTOEiQqrrdP92F8Ewmr1DsPsm8tgeTqEhyiZ3q26sPS/bC5KEBk8WVi4/+9xIW5xv
I1XBHm1SnYjQw9rPq9qpJq4V2FNFfbYcKm0k07ypY3+lsd09QkY38hRqzzc9SN0q2OW/SZx3adVm
Dv4ZzZP9F1/ZgA+o7DKrBhRMIEdiDioCDFKyPOUEExvQupmYd9uMA4JiTXX5nfIafrz82KWKeFjH
DxSpSQDmQYR2xacty0a7EOF3FU6l7O08mu7ACX+ku1UQIEHPNkYpX6IihLAHon9B/Zg5lrR/SQWj
09a+6iahDToAkylFO0I+yfgIKT1nJ8ZQ9w3ZZEoU9PVSS84KxI3fKjXDfq8C4VyNgwM74bMSVaO6
p2o2ehrCpX1h8q09pP4Brt+gzP/Y+oW7KwxRlylxAAyohN+xm/4Jkg1B7MVW4ia3zLKTniia+rsY
BwDLm8T3d0P4TqMf4gT+eMuEMotL+cZNFSskCzA36NI9Yyw8MnR/VJzAmz85RPS/sfFRi0O21Ovo
XfH8yvcnsskxgi7ChDXx6yPZMijGndCOdup3+yFBKxoyYBKIo/Ej7/THsjHpELEybfWVG8coFAB7
QpbIZe5UBx7PrMPzyzxIU9Lu9BAsbEYPzujX+ko+2gk6b/n6YnX7XS+DrTxCmcwWAIoRWbU/JWTd
NLNbRyls5u2z8vj7q4t1/fQJNrTncX54yUg/L4MNy7ZLj72wy1phqFe9KltfdNir2HvwVw16UVun
GbakyUhTKMQTmWnkcNbd6JJw8o527pEkhVM18WIHPgdsa+DdSkq61ToTTbC+PN1XRUCRQ6gv4QqJ
uTrNGniRWmzWMzheljsArvznoDM/LQQo7miyohw7U0xsDnxiUeDWR/3Lvh36WcOyLiOQHVO4YlJO
xU0mpk+IuqhBF05cXoh1K/xjhd0jKO0PtK6ABqCVIkO1QykC37IusvpoQL/OQKYttqHoOg6npp2p
qF9Af+b82vHTR9dxIuOzudBgq5SYlV5nyix3Ustmh1u7RyMthr7azk6DMkCiJytgkQNfDwb1ubfq
F8vX/O1KQxRdZKa7FQzugqkoEN+vDIcE23YaWc/89T801kQ14652wkLxtC8KHLUPp5yOO+GvF5am
zNCPWEeDrt8cZgNSJX3/4+Mpb7FCIGelSlqA5cjY7tgGAlWXznGRy2dfzKR0+LuaXF8jWAvETEnB
yVbx+lECmg9AstsO0xe4BQ69muPxjuoGySn/y4iew5T0gkUiWrJhlgtHEolDQVlanuFEiQW9H52j
WkGKLdnVJDPIcgsTB4p0qEYp/i/VcfwhcIEcMwS7oDNnZmkuD/MuLCdtwxgsjV+uv0Q4gQv7IRbL
hNAwLKqXLfB2G9XPKy7MAs9VruIHmsdRq0uprB0WuwufgKmWDeWfB1h9DIdLd+QPIMDvSibf8npk
paoOJGo1w5UBJne2qCc6g9CuBJeiUw1HGlyrh2FGLSbtmDvVQdZSmU1//K1z8kCA2wSKzkVZvl3/
B88eDwLR0/Scq/8SPbNx8aE4zB30W/XzCT1rBdj5lMYUdICrGXDeMcZBal/2ornNNP2lkOiHn5k2
LpID+EQ7JfywxOlabWusedIZCNM/NmzeTNpAC7GNKITzYPc1/oelR3skWT6AjsiavOSyBebmaby4
jth4Hom23yz1rulX+fF7hdZKPOsag138fCSTMxWbq2D4uMyzCcE4ZNMUWwzxH0wkvhjzsTD1ZIBQ
EPEnFDOsQkVGnHXjZ8waWg+yUvxPf4Ifb7CL/xM5ftznzkYCSMiWB8+d7b04pgOrKo98hQq8yYEV
HDW7Ln3Bkfb0CuIMlQpEnMXs66UV66EY7Sf1Lkf45yGiR2n5XHcFV2GPeO6L4MOx0t1c0Z8jB/0h
+k8EydVK3XHqhGW0Y8qG3Aby+ncURdQDuJsO6DS0cFajUgF8KuCWkygWPxn5SO6yeAmR1ZjUn6J5
pLOG8fgjOSYge11Im8mI4Dt/O6hbHAQQhG1dNB2RoLZb8fd4O4lFxqfyAhzmXMnQg4VuJjZwWRPT
yifRd0hv5g+ujpWCKONnZ4yISRub8EB72BfOBaqFD5TZomFUgKl8riMkdlIux5Js1HCb1S9EMwYm
JNNjXJXYeADmWMFR9kouvIuko5drwYEGFbY/PLCAM/xu0qm4ypLfETsNec0qv07eiDRBs6fR7oP2
kBTEOi/7D0cLE8EAWr9J589FPn4MtrVd442qFDly9qNwBGJTV25rGRqgw2GUuCXV7ASD4crfI13f
yOoToUP3K9ZXG4nv8CmHJ91lTdIEErOO1dUW+eiXeFFUnZfBgrRRnWf7sL5L5/+4rjtHOGrspdVq
DhtdsD3zdX1DrBg+S2usIKhlnvDJXYitYKJ8s4MSGDdz6TVzgB+QLqrt7czSMx+kTrvxtz+MIMhH
q+UjeRl4e9yYBUJV8KPimrny9y1TSvQ2aVNxKnhBZrYpX2kgTUyBHXKdh70E7Ncgq9Rydd4noHx5
ZSuuZ4yf8h55itWGKFdsI1EafZlRgv5RyZVEr3hTg3/Vvjgwlh77Rliwlq+CrVH++6s8bDhuQr4y
L4BU+0tYKuM+RZ7MznIYnw0wtGZWlnaNSfrTqThKLk7sTYaOa8VqqZlnSYWODUrpcNYdTXSvTkn7
Z8y4ns8yPy96kHpn9QW/1HWn/Ia6zZG8YhbUOPHOgYosueiIK9/+jv6+3voqZX6S2lofD8tcK1qQ
8lXxWGo/J54vel7FF+pTMHTx10DsPtvv2BGQLWXd/+ay7N6++2/uKs+Z8p79EQTIxk6VdB1Yplnq
cddxKGGW684LcqYPAz5vP1vaYMrZeyTlO0ZgRYpFlP1mwfOvDtuhiTZ1CwV5Xz5m5xD9McFNKJDG
fZMbmKfKz6a+dUP+ieOyG2DdVqxld0Iuxvs25LFw6rE8rTtkA4s8pyNvG1vqJpjGKrofdX0ZMMDP
kMqHxLKmvoMi0uThS8CdoFB+ldgjYHZG/vHIObjKX+L3QYNxiIhEWsRDcP4oxSeAwoxL0VTchCrz
Kkfi2izvHN99d33nZZ0A5++RTaX9UN0sX+TPPNVIlKfAvezeXJ8Lqk3Cy2f5+Obm/vobkQ3pv55x
HNaUvyLga0l2p6VxopVthiXmU0w/EGIptX4rX+C1amObn0YYM0nH9ieiN742JUHePDgriGPVy7NL
AqcNahGP8w+oNX5ThZno/1RnnyxW7AimW5uqO9Rd0LPyTRMbrka9HCCwhhGKh5YJNRxjaq8l6kKS
Vlkhc3+ljqDAiUUMFhiJGM6t+CVQpVV5lax7uR1YCY3QYz9qyvwZVWWJmcUJjQ9BtUBi/WUa6hLW
hJXvIID4Sjv83UyRxfi3W7+adX6B1l+oVxrfSfdWpS7u7/68ZaTJ6TyQJHpSGBJoNHKaeyky56NR
q8Y4TAL+ldXD3j0qPSmSKTIW8QuiUs1cLmvdPvNBWfh+SiXAKiCNhOft8DnPCa29EakgIYNxsE5m
1UYK1B62UwLE8UGtJgTeoo59XXxGsw8CpZwQivS3Iy2q0o+yoIoTnPFw97eDaF7uSuMtagfXN7Ym
gtv0UUSpR7uDeDhudxdyPKSuz99MsC6LqcXWTXrxn73/rXed7+4DYQwAnYU0eXhPNEAJGkj7zEoM
v+9X143yYxGX7vQ5ZkRrCQA0nGidkkNLJdlRIObJAqRbZQaa+YhmC1TsVsBvQebBwIk+VKOMeSEG
nWnmaWAH9euFELyV5UDm/TqQW0GV7g33VgIDLlByblCxnJxF0wwyeuF3RRWk0CtLM2fEp0KfFNYR
GJ4AZruOqpeXi1Vh0q6IpPwyAQmz80rw/Mg1BRzMSUpn0+INIaSZltqwdpInVn0bQTzj7ctXw8ek
fpbbq0lhiP6YOQ9ZNXEx/hWukYsgbpDUroAoXNU1GFMdvwvNO/ALigP1zx8GYwUgzg6uQlOZ4wsX
B/2A6BXxC6RqfBGd9HjycvEpwCZE6YBF5ivqU+F5wOuC7+vZ1/mxRlESgqBjvqpnT8KfpHiiSupY
Q5CwzLQ/6jOb02AgIfO1C/oL67YGeQcKEh0Il3wgyNeJswUSGuMMOINXj/J+S8HITsR6rOlinqmZ
KTnOhQNZzd5R03/12jCArWPQjkrR5YmKIvX6smQLuR9ASXQ+e8PqVJ9T1DvqolB1GUzpFIbTAKs+
u64ixEXHLn+Uii2uYcZMY/XSHZcQeoO/RhVdnwHfIXpjRJx+/49OyCGP11GXK0658zAMoxbHUtJi
o44MCMnBNAO4nXo0F7gPp6XytJI6v7cvpGxzrdwruXYSwVXc3EB8l/rlAdudtQY+pMClV/cblcCq
8SgtLD+6iSs8d2+6QIu7EVFIV/DD0QI7qGk0BiOwDjcP5Nq+t4QcpiEB+kyMD/wKIGfFoLCZUPRB
bVtLMGL+EEyEaXqAW8UPF6F2AMpn8zLkBldtoCa/IWeTZBosYgsMfzzNN9N4jsJ8Juf9STDVateX
TDZbi591cgxhbHg6xxa3X3q4Eco+U6mIj13PqwYO9ltMx+eRO6+7V6biKWfVgjdaNcamiGeBEv0v
7KFixf6IzIgHZTDjXLH4FKH4nypSbhNplvKSQq/p1s2DjEX2m1qFzEXcabKELIFujjJ7/e8PqawC
3Z+ltBlboyy+j2C090Fk9C+in8R2BC1pD5Tv8JXbqO/vh9NIf28CrGvzK0j7wrWHQyuTVfpMV3hx
JQXXmHFuoJR+9z79veMtfTZD2Qso+/5izaolWgWldybrwb59CMnDA69A3zUbFXXHh3Q7wRJNkb8n
dzs/aoU/6t02y8CtljMxfRk+A/VF2RDjctwkDjW2oCOjy/H60ORZPUw/XTU5mQQK76wluOesX2Kr
RFTZX4l8aC6hBFC+7A8icAjud4li/bM02nZFceY30IPF0VbnVh0RgONgRY2qaWP6sewkfGrzYbiK
cMr0p421UzozkO5zKUNlofwB8/qUYvcZhvyC9mEZmf8VtYt/dxU3y1TYtQmOA1+2x0fl42UB6QOI
BLAdi37xTxFhvlN26J76x1tQcACuzY1xS5bZ1hdO+qyoGXCmc07de65jmzgF4mBjxW6KnrKrh9cm
q2OAnWHd8cUc3ZzSjU3ZA22XP28UiUbwHAPvOE/b3Hi9/5vuyLpyLTRSOx4OYPPsNEvnBWhY/a2W
MHy5dHzGss2jZYCA6Kfk69qZuypOoO2AI8y+YTgwQm2VYRjSpZUEs7oi3r9GOAa+cJQvMyRRu7EX
CkrX7sBL2F+EKme8OmxA9YrYTKCjbeQjTqR8emL9ttBvjACJQmI02EHR1KY5XHxAD84mpMBop9iE
vHjGpn6xHUxH8+bllFnOJX83Cb7RIsPfdkM+vPom2YvnebHPu0Am14+LmYYqFgOz0+DpvDS1vOH0
/GTDr/WMy9ewrkaoL7+ol3vB+8+xfiwAV4XxHBUwHnGCl+D/c+UTOXn+XsOMq2q5PVEterYY2j0C
zvuietBBQaRkNdkGYcN/uVVokkl4aO4RYBVN2ffEmOB5t2NubZJsnPi16Y6ocGpvfr0XQQhbTauL
m8PfpV3ZEhLK3eENXb1qI65bZRJ8XrvBrKyxKufBCUGENso26Q1GYQXwyx20CgINnMkYXX8rUIdx
soKhmrHjqA2hEA+Oh0cOI0d5+ZGNGVqltYr7QwsnzcehgyJ6k7DukI9h8PHUU1EE+IWW725XSDvC
+WJHbn7KNpLKp7CNmAz9QJR2FJiPLdV19HHZ6rk6N9n2XQDXXZKitzJ9KCNH2l/tdkFKyU/j04pf
bWa1w3QDYqEsuiKr1KXlzlnf7+3oPDk/diJiefIg1SLqS8VmvxiwSAgQtJ4HTbHyAckhSon7LOg0
0buIvM7HsYzvkGSgdUz/5LWnXXVzyuBLpOR/pbDtfLsRZfyEFilIJuFWQe2ATisX0FR/6h2IjslS
DrFH3qUN+pZkVPrtnVJoL9Lr1DYUjpdm7hn7z8LR3KEjwLbfGaG9ysDTaGCIYWBfIQWvDS/L1nqB
KJ+hwgPNQlHWwT9DUr+S60QstSOmOYFEiEPGhlw4qborNyTogAjTjSeSF/oK11JQCk+yBBr5qYBc
UUIEvJ0TGUhLRz3LkAC+bEwhgsarFEBXwQQCoz0Kz/WDe/FxUDkZCIk3lkk0Xi4RvwKAjiwe2g98
LFcdekR9Dxx9lAnTm+gcgaP2eLFa9ZY3OpiqWl7lioIcG3wP6DqnDbGwhMEnUaCkb0KBr5dKDQEt
g6QX+sKpQPuj0GdNfv7PSloHsrnQeXQaDAnYwHkhmBh5LfGDVWwXAXRMRvKCzrgJPyB1veDsg6ca
9o+vOLhCExx7ZuBcsf7urPvkWrCdonPbj7vzPFwr5/jTW+7wqYzDHyWy/cwrIL8q8dvL58h3d+Dn
GtGKpjKyi9rdpZcnbVnnI/O8F6ezKJ2NZG5mrIw+Ma6ZNe1z6crsKMehTlk0Iaqft0P5rjS6WZYz
+I3ZNWq9kPYH6BrMmIiRapgUgzP2283WuWqjFwZmldkvjnXPSZCrsFZnt7Nh+SgsTKXY+hrlT7kY
WCLNMWHwcoo0W2MZkLzbZQOLwbjftW9lwsbP2mKCgT4ugXYUF8ndr8PPsp6p+4C0sjUiZK6KnREW
pMW9gfWa5K1kbzu8kBoEAXTBmin+HlTTvp/2CwM6Waet7s0sVoiOuHqsrgkiKOplz0vfQgH7oBTT
+wI6kcBkrLZkW6Jx9wVcVRN5M722lvCjaCXoAAJYz/BeFo4dQ+kGXDjLIZZMzdxVVAx2fxuLAdkE
3J/T6fOLZjsfAjyxGPPBEFb3uFolI8ik8Z7G/p9ry/RwwD78NekkGCsm7cVaeuot+uh8+b6l6ei7
l4s/iUKCvXDI98aGJS8saBbGJ94908hxF0NkpK49z6HWqkS1KXxH+WgIJ2Ruv5kHL2LPaBez5c7t
d1NHQvFNqGb+TtR7yXrWdAWseNwF5IqNMDme6hExO65JkuECCmPPk+zusdfJol5s1QXO4FR047/j
gMSFy/CAZ5rTiPMaurf+rXKsrI5p8p8BUxVjZqa3ue1F2KKuotVC6ynGWa8fELvSUVcIaOnrJaqF
dNpjpoxaptX+EusJW6/V54NmD5L/jhxn/OKuew7EW5FxgJ8aFOeBMlnUh1oS6xrdn03kg++u/KZQ
tl+WFZoyJMKtXPeZBL9xuqyLUe8dXolJFnVNt4S5RdlYv4fAxsdVOonIpqEjYcuFKZ5gXwBACNeO
q8BFN8y9nBLJ4JLgo0mfxntelVZ9mYSCzT8YO44S68heZipbZw83PLAj/4gWYgucrw9mumnDhCdC
+RX8OeYkXyiuPK8+3PzloxOBKbkB1iqkC2L8zNHVQVKEfc/8H/PwSuU8/HsEaCC9iK5SOFhTQ6ly
JO9aMxOT+a8DQbOw9+XBnvIfEbdwAnhFj09kYSA3nm7Sba50SmSyt2eEnMHA4EZvYa2ZfEcd/+kz
wTZoOi6nT0LQCw23J2Aj8QnRIsHf86U6rP+mWoFUKtEmip0XYpcBZSPtRDHUsf5uhvD6mlbh71v2
QB7lk/p5naIwUgiRLjQjk3gGd/xjDoJbAf8Skki7Ww5yopVP3V3ZmDwLsL7F7kZEeeCS5wAg3YQR
3Ziqnp9cUI8MksnwRyCCnAVsM9ul/UvNAHjNYCT+X7q4wIIyB05rOll+Aq3H+f3ELFh8vYb2Ug1p
rpIr7mfQ/U5iWfsWB65rbBfgWxeaUVaX1L6KF3LdZgavyJQBKwKoc+lsINm4BrUXEK29lXVbjzj1
Es6ltiVWudO0TmHXWfAI326q69ubKfEnV/o1Ssqjonxi3u2GBkgoqS1CZPjSYbzqcibm1DHjU+Lu
s3VvO9iVcD+gWI/XkHj7LanF1AFsByeM5bxkUd+RSd+buV5Cbl0bS/dvfuzacjqi74CM97plqWBk
1weGu1H8UgIOGar06V2F+TQ0FLQicUHD+NHNTKfdcGlN9L8pLVL9gyMukbcUAdgiEjZkkRWGs9JG
TGqsEsP7FJ2GRCcDt1I5F1Pu/hhD6m1UwxEa84pRQiT1+WBZCNDctbHJIdBhMZMiF+RrhgnL046h
bejkz2cp0IssfBTP0fO9tatDqYEvPlPYcqhYpd6X4qI3HC/v+GNqjOqwIVlkk+Dw96TNvSBLmiZi
egjVNHW81cEgpQ833zHObXhC5IbcKpSd811bg6Y9fph3dQAKzMVyMQy8NWmqtYPyVAmRSqYFIHXB
qtUjCBMk2wyJuwqwG3yhtb7BCke57q2wrKV5RjuvtyVk6kZZX2wGfqej1wlhEbub3CL/W0csUfOG
2v16RbXBR//PF2RgEjOVwcdcPa/akSBKAsMNIo1lqD0LHTiY+48BdEW8IvWLX9eb0DIuSfM+oTlN
q4FhU/slTApCaZFMqO94xCUEcdYnSCDofMLhZs38vJ04k59LL7jYTZ7Baztm6Wa6upOsCdF8c70O
7FVb1dpvap7p+VPkiL3lkWNaJLX9yDIhGeD//RW8qigfunlsUFJ25gcjkNUlyJC5Wf79AXigWl5v
ekZnA9wv7KT3lEZqC+EQh/R5vhMYQ6gE3c7ny96rjXxEkDnse7DTDjL43PfmT+4y+OK2UT81iK70
Qe0n3I/u19VzK7TSQlisvYn8pNxKYs0FCGVxbVPKpLYV3+/zqZDR9fpZUDf1snIulXSB28m/vArA
nW4hQGBNrUTyms384W0hjkQsioEOrzKkYobWuMmsLfuGUcLC9R9EAG6KEGom3z6pVJ1TSm3sQtRO
jO/T83JO8I8bLGqIPClQFPRElzLXaxoefHb9Buq1ZrdTfSBwC6TJdBao6lkRJFVZm+tBwTMus1id
tavzWnZ9wfwZnuKjFUbz92isuJ/2iBZx26IdLr885vrCijKWOqD4q5r/m1K83L/RVTM4M5QF2aV3
NMHG5lxFK06UM8JSqWYcZh7KVsZv/Z465u6wGMow46Scv+IbCiN3rhevo71jLIge2wLg6mLNDHb/
28IoChEFKBV1rZlNPQxiZp32kNhBVQCX/q6lF9AtB2xygEtIUqTk5rmtkM5/LxR2BFkOfUF4r5ot
uWUIozBYV0mMVuBrY6Ox+avfUEGQ/omYqTipZYZl1NKOVo1mCvK6NOvv/IaGQpq+WGQm50wd8+je
vuD78619UTKABHKq4xjK4LQBDC2Q92Tdtu08rpL+OkQg4a3AaDEeqjLti8D5IWsTzNV3a8Wlcn53
wnnDLK8ZsICVQrjHeQF+Nvo0/bGocg3JF9C9dadgVQ4ChWwprm1HOI8AHVtQUfNaQR/WqS61SgEP
iNejBjZnrZQYNL8EQERR9KYPjIy+lBcIa82utV3b8DBdYOOvrxFrKUq14mJWllPS23Id20hw4G2p
ZE6bxYzVz/J+Eo3Ua0wmdUX/ECW7oD3HCDqChaBYIk/l902G2mnemEHDFdhHgYEJLPjv3AV9gvRy
1l4lV5XRBBDfxtnFqenEg0h5bJf8OnDfWCZokbDi2xWuShkJ1XkEIkwCNNxja6ZL/T0bmCGMBou6
AR447WIzxs22IDzeUzN2RW86wSP+2dw+MMy98VM8ijmTSW1bmSY8lK+bGuqmKMJX7n+jxAMW0LcX
nQFW7T3LHxEJmUJCwlrPB3ojiWEge7swYchGLVbKJkCyfTPR7xgyRnKTs+d4Pi++1ZyvRIh6Y7D2
rJyWCwhZUEZ55Bm67GrByY4pC4LW8NWAv81beugf8sdJS1dWS3NnKdiGawgE5d7ItF8FaBbvV5vM
wrh2GvQytJDPsGTyHeLiNa8S26+CRlcOS8kbBmZewWzLNl10JZDzWEkSpKi1L7yhKTChWq2HZlKP
M/x+u35m6pxxaUNjNpZ0eEtgRzPvyCkV6iauvPKzvoznFbOiE57M/3uIX5mD5lVmTmy47JDywCzP
zxBW7lpCBUrW46HATR1lA50HZt9rDtTDJxfWUdUTQl9BELMqQmaTZChXVGM5STwzQxIJ+vxq5m9r
y+HG64EmKxewe4nGgRsseGOfpPJZjJtr6BdEZh5t2VjlJhnAUMogHmh/SHqDzrR2qwOWnmdPy7TZ
yz+0JaWqxFGHWzBA7SKRl1+3ckwxqOfrM3VLXV/dX4yltInzgzZEssho5//2DS7PfPC1CWdg+4l2
hIYJUEn7AccCudSgY4Twi42QX4QSn5DQ6Vt9anAF1dmBeDnLHiUY1Lrccvy/5UIugi9u25Y9Gx+S
GqQJQ/Ei2qwUHgEX/rtnVFwnU1mMmYX0idrE2iUlbRbGs8+RetEg4DDQLfBoP9Jc0D0kRYeowZDH
OJ64wWEd/TFGX/cMtwotJMEYwL4QsGFdjRID2FwnYL5JUD7aM4ehgJv44Dw1xBxdkqegFpmIFFvO
gFCf4oF4jtz2brrYfWtC25S/l1JZrCeWArIANhzJa17cyueRyDcAtGVdJEgdxG3q2MHfS0rJfTuG
qFYpzMIULxc8vFPmY70eJBhIL8XdE/XskUjeVPKin+c5DME2o0TrQXB+JhRtwo9AxlVKmjaH+Hb1
EgO8HJNVhJNL5vPTbsRDgkUVL7zu0/kRWXH9q9srv8/tksVdSmuc9TFfC061BOjbPtXBzt49qR+W
rmSekZizxJfZqZXpmLQt3wYvFx1qhzgdoZMmM+p/7OGYJLiS7+dx2xV4o3OG7j8ypNfdjXoZJzaI
6KlhVczSfsQX6TvQpGfozL/8SyS2UcKDgNoFKsqndA1n6SJ4EC0yimoc+pBhs6alzhOgadhQCAXS
MkntzIWoR/vyg8pgKNplPuOlPWUvaoMx3sRTqJ3RuQdD+YQlq8Rf6OUSakQYLnktwUlkWzTOpd6N
dT2oTAiVOVxroSEGf6qr7s/FH3u/B5urEBvQ+/p0gbbLQyvI97njs6E1eplcBA/4bNJuIW+At/Eb
x/fVY4vFu4HL6qET9qbqj0mg3o/JDjCGGTNchxbiNV7gxe8MNz8YOjzWwY5GNlL0eUo5g7fAyKGt
pDnu7AhPECN2qqTqV+QRHFW2WqgMPy+LU49ZqZsf8In94sXbs/LzVPBcX8HBSZGo/goFSPZTUWV+
pQk8ZX3eB2WggoRuksDTYnk6D9CWqTfomZCI6vywHnIytEPzsEbxFi7/ot5X87Bqj2rVtDePu7g7
T5rau5FlX4i3dSqjSI1yEf/QefQsHmAskVb6mDjPt+aeTutM8ZeMagxXyW9AudYTBxk0eS2WiMi4
NywMzZo3lUq/2MVwhsTGbOTFWAzqDTpvlh8/wjZ81dgA7SDTirJPPyA3QLgWbeo9q0aMEPG/qApW
sjoVkU63NDV/oyRN/Cm8H772r13qYDpAEtlR181BWIR3jdgKx4noeOxGRuINS6gCl9V2Xu3xRHe0
4VfpVKKi8ZtF/mOV9UCQtCN8MD4WY1uipYAXVmIN8T3U2sLvxu3xM6x+ToiPossffNp/Ss8gm0+V
VlcOhe7dwMN3W95qJD+G40mzPN8PcM1k0glxpQ34NKb0a0H8cCR2oAKB9zO29+j7iKmfoKnJkQuw
MBJOLfc2HtZBn0io14OR6hY5qmOTpu9TrvF6/N9Lb/cCH4NaXlleMrJN8pbGu294dLAvbrrEEbtI
4mqtfSyGe/ca6l7nDlqe2TwBo/pIpUQohAZjn33en3OoQ/PGAxLGhbZs1zAq58Uumtj2/1flLmab
UYUMhS2rYKJGv8X6ROa3hxTxWbDFcvUk57i9i1MOvK6zOKhYrpiGUO/51pVeMt91xhK3PmSut++Z
NUH35T7CQHlmtRbdxCDzcmkYKkuIu8CgT1fNR/z60jIjY0LHHoyBA+G8Un9LM4MN/wzRLoTy84dp
PcR1vqPdgWUs/CoAII3CLG0qNAqz02fi7kDvGDsfEfYF9724T7p+j0JUQC0oRxCyrWlTtS8KZLoA
6PTU0aLd3QkHosZLgRsHPixfz7pxyeSLb9EHj/H2pM28/ANptOnA6R3jmzLQKYNg3wP7bcYFETZc
Am2r7ZHHAevdSMEtccCJpwpK2+/B1X4SfEZCBXbsgDhihYQkBLjx+nNj+N2fjROQqKoQlWHUl/q9
0i8G9SjKP3UtzbGueKrkXPNCGI9jolLwnAu49t0urwfoJoFl2xgwXT71y+d2UYaD4wudHIu/alwT
wFNSQ1Lb5b3vYuyWB5KZH39hGLfHifBLuXn9uF2ep0uhHGeyecUe/EAfzcgRLzTCpFUcGJHFU0V7
k/CLvnVq784nbsfD6Mkt6ju8RLMPSacZsDrxU/z60WfhnMt3Gg9H+AfbcMpUH58gXXHDn/r5Zx53
Zw/v16E/QX/WptYoy12DBnshqeDm5Liyy7zapS7IzeLG0nOEI5J+nED4EPQzUd6nKjPHnRJJAYoN
9gJyRNDHy3FOPQU9MUqAs/aRcTXIcYue13ZcMh6t1PyWiXVwwsYfkdiwUpoRZzV73S1h3hnTkjxz
hiInfkyDIhtUeTjum0s2HGK5xS4b2hj6I2cxwBJXmXCRd2GrN4YATC2N+l7b4MlPgRgd41Ve0/Tt
Mza1M5aeWb34e8bajYzRUVgDRvKxn5m4gQogQdgaHnTTMMKKmapahhxSxyweacm8OWrk8BX700Zr
Gnp3K8MAow3fQ9yjEzzh6N+pnTc97B7NLXmTerreD/nbEb8dzVLOcePUUMK6YwE66RLS82ha4uXl
iX406HAGV9PKk7AZm8m2Kbr4cCWmU6DP1Q8+u3O+0zuDQnT69itQia26uoY753mbU/BbPmJzUNte
F001s8KYg/14dHuhCNSJNCpKn8nJLOP7K0vbQLkP9glfLZyVevJNW9QrCYQykpDFYbsWafhH3KIx
AE0QAvDG+YpqK2jpdB5WPZO4SkNRppqqQZM0+kOlUJxjIHR+Mx4IqknmJrLyScVJgz/BDKRvAjmi
1ciunrMr0E+L7ReuBaNY/33/AJ43LO7d3WJjyJuYksWBVcDVjZWHrJtewKzBhYVyPg+jJ37NNgIH
mJZvd0OGDmHaBGhIX3HVKnHZchGvddIlRL3hGU9CE336M069NjmUGG24IAYuBKo/ntVkiRMKjzrL
o04O8CEKMcAoP8A9F50p1efxnL2nH0Z5ffgwK9BlCvXViEar2iigFaCYp0HH2DHw/L7te+9s8lQb
XDEA1MaDRuNFWOherFDK54Er0AX1b+1P10NBzdxVszPGCtHhmJ/vTKKgu2CAIKEWYziipINgAmZg
ItER7b/6SasKGJuLA4MhV2BEy8uyHH4GdXyXoHvULP9wCW1u5X+R1mSFRybVnFDq9xDmXQaRpDw2
OaUTKsWdZdWPtQM2ADaZL58BGQp/iizRuA7agcXL8sl5DxywYtkTY38KxsIoM8P8oKb+UZHpO5HB
6/mou3A92oNgaWLM2PlHWZRsjHB2IbrGRT8ZSVmsud7fMj2KSJo7a9EK/OL4+OurJUftM06pzQEv
5wwUiMjyk5ORjiut/DrVEwhOfHJiJqDTEvWYjxCPKoOV9BhUCOnT9DHIKX5KepgWuB4K8++JaXrG
is++auctD3qBFg//7JI8TqxKk4G9RRX/sHLdsnzfV5dAQKHxDeSY6+rpufCxNTU5ooMeSzd9oDj7
8NMiTyxHh1zusLc8RTI3JriXaIThLepnmY5Kqz52EWEQ1WCDbM8KSxLtL6I7TL6KahWhcN9cbG3/
12TtYFkreVu6vKQRFqUlyACfC2z/onw4yt2xanvsNw6VD6Qaczf1rv4XKHb1mrMbUAUwDfj6pKL7
IQqrnojOdC6ZTWCN4K+skeWJhVCIVhCw5lRrjKQtg6AolYXI1SYTI16W+F7j7FJ31D/n6OcPl2un
u8SiM8JrzX6Igv4CvnRVJn/63pdjzRFMLLc3fAww4dxh3BBGXzY3M9MEKdjR3uEyUK+LSq+P3ftO
90Zc/DZ0ntwSR6jJwCVkvqnzjMlzVvCgLrHUWtCpQiTp6Iv7TC9PtQGDM4gRj95wu2OmTCwsOxzY
fDc0c8Hl4mwFUmmW84A0FeIoyi3/w5ZP0/bTPv48iJgtpPvMhAFxnrAk2eu4nLh0DlS3/MXlMTD1
Gj3ZKRJN+yalbwEpAeJ4zr+HUcGPld1Quz4pJEcc4lu5B4YlWLsL7pXscoYLLk46TRr9WViIl1XB
whwoWJNnlVk82t3AtkYWfmkxo1QUoq/GqXTiCgok2vl0Bb7xEwdVFWxw568YX51q84Clg93dXIyj
JITWUFowStq/EyJaNnOjtgpH2oWzagPBR9EIOi3C2UnkGlVp2iNLY5K0hjWnm5Bj191MGl4Iq7n4
ROzPTx69gs6XFWhddbBGwwH0jPlLgz1V6zmYQLuNpiLQ2LSNAJZX/usPdGQUCnVsGpsJzYCzCA9T
IROjrCUTfGcQtnsKq8xjUMGNt3D+TD3777Ug9VapE94icMH2cZTMXpoH1hQ4Pvj1sLuWAraF7xxv
HZy0uuQ/vHrN1AqrXigwhzqS01jtxfZRwZv0s2jgSyb/cWvgY7hAM2Je3QD7bultNsC6ZlPU9T+Q
VbH3YknTuSb3UPzpkKOqFyusU4+CMtnfTp4XNAWZKcsIO9k6/FldKAmvmXlEsJvYJTT3y8iJrVs1
eppDG3+EwSWL4ouKCYAL11cw0zhzM+FHc9poO7W306ooe/NKe1gsVh4r0ZxE5v+z38rJoj0y4PnX
GKh3eWOt832/kuH/ppm/CYlS0ZF5Yek+y3AdLxAqQQwm7MpbCiWBbVTAdyzBSufOI6uP6i+Xd+ix
sq8rsRzWMqCHCr6Q+8GW/KHy0EqRYYY3tXRy1ubeHQtZZpS2yIyYFMAYRNUrxp6OrlRffr3LGy3b
qoSMBYSOoUuDxnVtSmI//LNf0xDw0Db4LZKuhQRF1lkVCmahwspK2A7uxlHa5nNqyx+tH3X04am6
MLfa4N4fBxcCajOSZqveJhay2ATV3NTULy8ujkC8pHoprfOqn+JGVFtuh/q1SDYI3IQi6ZnAhZtl
djiEpHMOvfo9xJlPVGVkWiGDb3jXz1j1+s0kFmTo0/PzJNRKm9W0gigkNfmRjChAX89BNMO19K/v
QqtvlsxbfBXUwC5/5N8PZL9cxfRuJhpQ/cVuc8qh3FZaw6uLEZyGS6NkhEsDTxCNSZO8/lD+EOgD
qwV+DPcQzHqv5QmyJzhTk1FARLDEC/IjlC72n6tPNu/iDrFBeiy+WQjQnzFlUurlEPExxPMuSVdQ
BBAy3lv5UKfp9Xfp9BOq1EZojFWJy6rie8rptybRk7jhVtDovL8cIUrUpGr3mlxJxDp0dQb5kmlf
dS1l7hzTnhFI+B8KzsIVWiD3ZsJpXwuc7GfvsyGXrigu9nCETFk+jLHJKHQX/9V9XFEufJC+B4km
Qx0jAy1Jpcigre7ZLAWlp13CBnzamA5bCaMj3WV3LZSdQPdi8BR2FEsakLOQOmUmTvQrRsRiCKeT
ZppdZFOSqNqM6tl9f/lDMDsuQwgLHlJEhMSyDwu4xDrcb9LLZ7c0MgmilM8X3Oi7zVPSK/HxMxxa
bNxGbQUz3nQvX/mhl7LmvUUfJHPFN4A1sY/S40yQrxUDlOYgvfvcTtEq1v4fwU9yleqNW9jgQLmb
DnDD8zKqT7WgNNOMe4NiUiLe+0ZzRjCBWMW4B2XxbrKz/1Au/+qJgSJ7/v62xkXdaVXgpoR3YqU3
WLkJsasTOhposv5kUW8fL/VJdho01yow3SZBU8fXQ0u6VZzItI2yb12pgTaTW1bqPKA0zfoVPNTi
YYlK5zS533W/X1aiHY2E7T9edrkXuSMN7PSrc5g/nlRCnVyx8TRefAkucCbscSrCd9+oObjRYq3o
lIHtgPXpkQ1Nj9ts/d4UQqIyL7NbiX0bjJiwS3wOd9XekbDxwYrzOBA8oXg+Rf7dhFL4P6udscr+
/uBllyqz73TWPhMhm0XJRyTzwXfnjdF2Sgk6iR+ubJL9jtZaKFyxvxWeRz28NxK9KCCosx1jL3NZ
FuNtw9xvdg4lLwOvGGcE1S+Y8m5Lp7i+2Lu3mQKlyGD5QaEsor1t9DX0VnhKGmnBfG2no3C8NzrK
YuR5ZInt4ToV3shvAWNxNvvEBALsiCGAF+xSTCQp3Xzl03zE7I/jdOfqH0GinphMXAnoaR4wQUi/
05pCcw8V6ntE7ntwK07Ax/HBPlKomcIAaAaMt+fobXk8ljCVzuvlGk7VussFJnsL8HAEKyIlh5yI
i2f9DfX0GGSvGEt+uRpGEh3jkwDxs7BqM4sKEmmM2iUtaensohS7v3bnTYZ68+AJKNvh7CFU2NTW
C3VCJ0ZcwxlQzZVdoTQMOTpwaeaySmJ9wa3AO9pcUCvNUz9nChHhnq8BYBtiFW9klgwxbdXa09VY
X0IHAZC9LqRvfkD1nFjrPRRYq7LjCZm/3M7mWKpZGx5L6BMuhsHTHdiQ4EmiJfAI6ePwnE28jBV8
EG8AfBcc6eklJARi6fhPduWRy3b4UdgOT9dkWTsZZzTY19PDFEIxUiJzKKbjwQ+LHT+qSQZ3HXAp
FQq0sfqLpUcLYgPaVrMg/G1kDl15QxQ3dQTZ5TWpRuhcO374sXEs2OHy+Ryko8cZyLFhT7Qy9STN
wFPyyTDvrKq1Fdytbk5yuniMutl42HkvHlNmDotdETn4X9MRBu3SinTwCNycY+iVH+FlxWOvBAog
l6hx3lBcav4iD5SbKNafZGWw82/O7fztUJQxPzeVWyINaX+VLf9Nf/fJ9BDDPp4M1AfjSjC9m9vL
ylRsyFtEk7vVKjyqM6li9B20BvlixdVXMwQmcW/NGMZ9nmJLB4sYngHp46JM8MJtdw02uyLS8hE+
bc57MsqT6Qd1J+WRndj9LHeMxh4xSQmOqPh17TwpRCBv36TAGwMxq21RNoMBkJ6Wbuky+RFlYPE/
qHp7dV5pfrgeZXOzSbz50UHDp4l3/bCpL14H7BcXkaW0LEQW6Nn6dYmtQDiuInJErWrlYnyaHgLh
0kdPEDG4yuiTepBcOU47yLrxGTkCwCD4/C953tIAhGN+IG+p2+fZ9DBAz7uKwf+Y3hhRnNZmGR42
YsCjQ9a1NcpQogZV51SJ+Q5G6DCZVxQC4AEKl1Ajey154aWgyZde8Ot+mVmCcy6SqyCAUushClfw
pRDK8yVQTy88HQciIgufmRNJxQ5zcCEsFyTkg0bU74SG8MNwOgCJubXmPksleQX9KpO6ZkNaPVQq
W19srqKp983ak0Me6Qt4xGmIOq1cTRAgbRy87/nKVyrJ5x1dDie9GBH7WA/obWomCNwtmsiuU/Zx
cv4N6LyvDE7Hei0f6gXjxkmmPOxtT1qFraeZka8W0bJBO69m+Fx9aN/nrtAHevaDIWiapxmc9JFp
Zd3cUmLnF8/wrrKwvPkAPfoA/YuBX6wfBuNQ7xsXf3nEoaFmOvmZLGU5/msNsdD5Fjxe+K79AUbr
gnsSHJiKEWX2KfdXIvMeS1Q3o9FFAHR+LUao7WunDC6ASsq04wXAHAmlDHxQsnc83XHE2vNkGL2A
7PjWC30VZFHOQYJ2Elb/RbU3mLvf7nhvI15MoMQNng+Dg2U55B2dVUZog1tdtoGzmKXWm1SE/WtV
SwX5Fmmi6zYKXl4CDZLstFvS4PvrWctZS7YYAT58NtUd5m+rkcP43td7JKBxBhoduU+AKccDiyXj
5UAKYQQu0j6xxu/qAqYoBctXCO76dnGGGXAlNd3qgYF8OMrTIAd7UlAGtEN62w5bxg4S3GM0qkB8
ghYEsKG6INswWcirBk+MOQYMimoFMQEKhFCzACSEGFr57LI9GFvpMGP0pdINRgt4mD85sFrSqRR1
Mbyn0oTNAcomSQwD0khOrOLGGCqB9+7MkbEOy/8Hai6IslC8dIZmXP3fdNpzN15CSNiRzM2UI6fD
UBH/E7X/baRHnhoCUuIF1nHnv9GOE+2IgHvIzpqIgVkpkpO5okeTnzJ51KNwBW2ba8FBogALrfki
ctgYCrPfkb3i4cWzsUnIDEnB8fkgxpBA08wu4SIfZu1QKQ3glE5g2WMxNx2B373gXWBgwyvaS4t+
29D9LbN8RaMi0AA9EB++K6XCBG8hDCnBnGe31SSnDg9QtbwASmzSIxBpfgIz7q2Y5DR91OZ6x8WD
pZ6j7d6puZWxENRXhHhk6OiaPq9y5HPa3NNNYCsMZa5J8G/GEjQf5DxuP9BVZBRTktL4EZwkkADW
T1/eskADjPAUmQVAds3HAcwJ6fpGZiRVGxUyyl8jPV3n6smA1r0cMnUz++dVHxUBMg0TMEempSdm
eB7fJds4c9FvojneLHljbgtFs6fHTpfbRadGu6tEUtzptTs+f148zmp4Afzs89w0FYFYskB9PAUp
xs3IRtHrGngFH/ytHvpQf30GSbO/6W2jLQ1xvQH5HKgZ6tW9FVmwvS2KKdP7h3rOb0GF3DmTrpWw
ehHPhfjQBWBtO134i/j0P0Utd9sKuuUpBAk2ScJ2r6TeoNB11yuzX8ND2aCzCq/5ZGWDCOU+HYXQ
ZxKAHDNJEayJuIIlPgr/EYcm7beMxSF66NyUbG9hE1/g4uAv//ZxAmTgHt0+OjGB+USwMKWZHE1D
12K3ClsE2jWa8c2lvCb9x0JhX8AnbQUXKwh2FEHYDxKTMhC+XdcjEtyO+ME4oaCDnbaqx9eoakXr
nKOphyGN9OLvJT8qk7Nnkm81dlxUgUXopHsmhstCeOv3l9s9xabByo6TcAo0HgKnM+xg6Kv5X2Zb
11MoCLSVu57OeFTdSz9I/v2kjhkKR3ok170FVoUEoybpFbbB062QSm+92EyMYynQ0BMs6nwWRHxF
sv4LUP20QRTWkOX2pmIySDa1CJJRojTTYXNc/tHclsD7dgoaHtgLhDmRo/QtlnfCBmmX/KO0UJrK
eyuvgBObmCLCGTnPHcLGWHskqZtRtYKsS3vxaTK+/sxSd3qWYzHSEYOdltkD/HWG8Yj5e89aaz3H
4kIMEhB5bIQsjz+ZFYSu0GbREKleDZygeyPTmvmcXWNcRFPXWosQZ7zR/uWY9pCbhDg6TeU7dcEL
uLkkPAOSBw/WSXryy0r0J1PUWANSdjrhfYbHYVgdB+3wOnOfZsH3Cc2EVZ8bjg8EoOLkLzU/WZbE
FKeKlZjCuXWRuX3V9TTTntVQm9HILepKvqyEWCt1sNbeKBth6xHuQzqe1RL7HTGJjHDFqIEYx4kG
+bBiJZgW+KHpvvGjL+4LSMlJ/KwNw/6WnEi27Y7TskQlbAvb21fqKamhml2r0pLCj8u+Sk0rBjkl
MHo7/wHzJszroJD2kxls8e5KPOPIN3A/gHJFjOrs0GIK/3WFfcrU7wqK6TaVMtl1w8Ww+6UErMJs
iWqt+6dowVUwbf3v3382JVXJLk0h/VHhGP55fwq4z54nqLKvgzzx7vOIqvw8uXU/noEj4mIM+ZYK
B8Ac8FHnzGjbuLAu22wsGQMjAKVKU3VTlbVlUHNO9S/RT2P4Q15BAHXFF3Ov8c7yPu0rLFlbmVkR
XbKBS0mZD0M2RZZ0CSBECzUtnRrNSvjUld5L7Z7tbj+Xd/y/4OKOdzGj1PjjULY7UFIyK1eyu/3/
oGyGJdVV4mMR5VXAD0nvrtU7K2zFl1PexEprzl5M+MtIoGyPHS0hEflWLtdW8YuHEMePspgk44Sw
aVOmHlzXbeAJF/IADEfxM5wPiAfCe/svayhc+HxdS1qw/7C8trEheOiJ0HBFoq4gvszzmoXixT7p
Vin3Lk0Xwd/qs5kFQQJJTCDu4VAhAgeoEMR+pZxdhLlwb4DEbyDo45MAdXm8W8aHAdWuxG+gNZIe
JSHupJc/4q49JALBqTSgmvK9Vg4nZ4hi2VnVneiOJLVwBEr+vdTCZmi9CAELOZOevUVeTXHWtKjQ
rJuSgpEpmJRsbsCd88skhDsxtm+zMwphfbf/ZKiH9sEHof391txOwOMlBrJR/hHrRUyMKJe+7D4z
KTtoONMJuZPUd3xbw+xEBxOiLEjqfEuuQubRH1M2FEyKwTJgsiljmj/4bUPkOdgevaTRF73D00In
ONIY4h95PMn1nxOKlYp1v0EdzPCHfdA/YErEUB2+v6897Ek/u+Yv6xAuiXU0DxnrYzFr9Mp7MPdQ
nhCK2Y20zMTd1G2sri1yAxPbPEN7dnLnyP66orKGtJ9GpqUK7SSpEevELot1j0si8lTxsUKmldIW
09qfnJQmQg1J4Oc6/GX0ekh3e7mNvkJVtlzn2BSp3Evu/2Lyh1ikAJZXocbaIP5ahbWuVY8KDjxM
uHJvsh0rxaFAMrGSqA5ry0ixhnSvgw2z8LXZXMGnU7lI7Op51fknEmy8RTk9Gz6hWCDJHCKZN3sw
J4NmL4gsxViA09x0oGPiOl54yDELv69LnjxKwJ0k3BdsmmCiyHSqpIWvobs3vCsTxHszzlXFCh9U
B+B961TmYgcNok/yKyY87qK/xWOqMYTbFN9tz1MdBMnmw0owuIMiz/TFXxDrHXtu7+YyzPP0ni3B
igSKZfyYrevkWbtoqXE5mMKbJyE1PKmBRtB+JTksDiHgXcdun6DGfbOG2uAYM8IqTMcUuJDpEjh9
iiNMwK+CAsnRIFrS2+CNIhz0e6PfvFhojSB50t9f4V9RTfEsXl6hO4XVtn/R8S7ezPJh7+Qio6om
cSVROvZL5109R6TDq4FeAKdmNWk+im43GRV0wO0l84r9ce9UlSVeR/1GBys4/Fa5Xpa+VOEN85fU
Czqm6VzoGqnDLdRk0owlmTGBrG1SH1kSVrmBkvmuosecEW46py0IuC9mGuzocfMskLoEz22aMh7I
L8NPf+97VPZ1PflNSAiSkPxWFYpTraN7mErDz8XpPnXHHIOKwCAUsth9i2FHFFN3zQsXNKjEm98e
PPmc39FXD25q+CSFBlc/hLv3EtM8tsP13m0v7lAjm8+sVSn7O/EbqeoZmBpTZaNvvQpBA3W9Laqu
yYnpMKdce6sJp1zcwTDKI0tAZE7hJzQqTIx7xt5G7BIblDKiF7T/yGzfNi9JrXmS69lxu2xsSMs+
AQyl55h1xI4i7GLhg2PFED4CvlU8o1jl7y81y/XpK2sUIL2BnWyvGc6Ad2wWnL8BdhsHHH2zW3Ba
Tnx/Ycj2f5S4cgClIxwLtpaNEP+uEMG2aS+/1ZhNB1QIQdzu/CBj9XGmLGbIc+zyQ+MUL5wNiA0Q
uvv06lsIN/USLuyX3TSy9bFIg9Jd+HzLtyI9d9dAgQw+5qiraLZoQJBLxxX89A+WHyCoIEa8tzQ2
d9KWgo9u0Jti5H8LEqPsZZDqcDM+nHuFNYK+uv+IJCV4RtRAkaAQueHpgavz0Cepd+3mwVRtulq5
P3BrQ3RWEmsq0cfwJQwbkX2jL+0eMiy5LsAOhHeQqLOThiGUo/V/rzLIFovRFs8ra3UgV3uI/VOC
XkhnnFkUaKJKLgyiAUv/bm+/PHZxjQAQNdvltZ2ZJAAE4l26ZwNci6VQ7yDJZHxbcSjuccAmwzIT
XZE193Tuq1SoYnM=
`protect end_protected
|
-- Author: Varun Nagpal
-- May 4th, 2019
library IEEE;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- This design implements an FIR Moving Average filter
-- which averages L points
--
-- y[n] = ( x[n] + x[n-1] + .. + x[n-L-1] ) / L
--
-- To design above FIR filer using minimum number of adders,
-- we modify the difference equation as follows:
--
-- y[n] = y[n-1] + ( x[n] - x[n-L] ) / L
-- => Ly[n] = Ly[n-1] + ( x[n] - x[n-L] )
--
-- Assume Y[n] = Ly[n]
--
-- 1. Y[n] = Y[n-1] + ( x[n] - x[n-L] )
-- 2. y[n] = Y[n]/L
--
-- In our design we implement the above two equations
-- L= length of filter
-- N = L-1 = order of the filter
entity fir is
generic( L : natural := 256; -- L = Filter length or number of points to be averaged
L_BW : natural := 8; -- Ceil(Log2(L))
W : natural := 16 ); -- Bit width of input and output sample data(signed)
port (clk : in std_logic; -- clock
reset_n : in std_logic; -- active low asynchronous reset
fir_en : in std_logic; -- handshake signal
fir_in : in std_logic_vector( W-1 downto 0 ); -- sample inout x[n]
fir_out : out std_logic_vector( W-1 downto 0 ); -- sample output y[n]
fir_rdy : out std_logic -- handshake signal
);
end fir;
architecture rtl of fir is
type t_reg_xn_del is array ( 0 to L-1 ) of signed( W-1 downto 0 );
signal reg_x_del : t_reg_xn_del := ( others => ( others => '0' ) );
signal sig_x_diff : signed( W downto 0 ) := ( others => '0' ); -- add/sub of two W-bit signed numbers requires W+1 bits
signal sig_y_sum : signed( W+L_BW-1 downto 0 ) := ( others => '0' ); -- add/sub of two W+1 bit signed number did L_BW = log2(L)
-- times requires ((W+1)+L_BW)-1 = W+L_BW bits
signal reg_y_del : signed( W+L_BW-1 downto 0 ) := ( others => '0' );
signal sig_y_out : signed( W+L_BW-1 downto 0 ) := ( others => '0' );
signal reg_fir_rdy : std_logic := '0';
begin
-- Generate ready signal 1 cc after enable input changes
process( clk, reset_n )
begin
if( reset_n = '0' ) then
reg_fir_rdy <= '0';
fir_rdy <= '0';
elsif ( rising_edge(clk) ) then
if( fir_en = '1' ) then
reg_fir_rdy <= '1';
else
reg_fir_rdy <= '0';
end if;
fir_rdy <= reg_fir_rdy;
end if;
end process;
-- Get x[n-L], Y[n-1]
process (clk, reset_n)
begin
if (reset_n = '0') then
for i in reg_x_del'RANGE(1) loop
reg_x_del(i) <= ( others => '0');
end loop;
reg_y_del <= ( others => '0' );
elsif ( rising_edge(clk) ) then
-- Shift new data only when filter is enabled
if( fir_en = '1' ) then
reg_x_del(0) <= signed(fir_in);
for i in 1 to reg_x_del'RIGHT(1) loop
reg_x_del(i) <= reg_x_del(i-1);
end loop;
reg_y_del <= sig_y_sum;
end if;
end if;
end process;
-- Calculate difference ( x[n] - x[n-L] ).
-- Note sign extension done befofe subtracting the two (W+1)-bit numbers
sig_x_diff <= signed( fir_in( W - 1 ) & fir_in ) - ( reg_x_del( L - 1 )( W - 1 ) & reg_x_del( L - 1 ) );
-- calculate sum Y[n] = Y[n-1] + ( x[n] - x[n-L] )
-- Note sign extension done befofe subtracting the two W-bit numbers
comb_adder: process ( sig_x_diff, reg_y_del )
-- sign extend sig_x_diff with bit size W+1 bits by L_BW-1 bits
-- before it can be added to reg_y_del of bit-size W+L_BW bits
variable signvec: signed( L_BW-2 downto 0 ) := ( others => '0' );
variable tmp_sig_x_diff: signed( W+L_BW-1 downto 0 ) := ( others => '0' );
begin
signvec := ( others => sig_x_diff( W ) );
tmp_sig_x_diff := signvec & sig_x_diff;
sig_y_sum <= tmp_sig_x_diff + reg_y_del;
end process;
-- y[n] = Y[n]/L = Y[n] >> L_BW, where L_BW=log2(L)
sig_y_out <= sig_y_sum srl L_BW;
process ( clk, reset_n )
variable temp : signed( W-1 downto 0 ) := ( others => '0' );
begin
if ( reset_n = '0' ) then
fir_out <= ( others => '0' );
elsif ( rising_edge( clk ) ) then
temp := ( others => '0' );
-- Produce new output sample only when filter is enabled
if( fir_en = '1' ) then
-- Round towards 0.
-- This means when doing binary division of a negative signed number
-- with a positive number through right shifting operation,
-- the rounding of quotient happens towards +infinity.
-- So there is a DC offset in negative quotients which needs to be eliminated
-- by rounding negative quotients towards zero instead of +infinity
temp := sig_y_out( W-1 downto 0 );
if ( temp(W-1) = '1' ) then
temp := temp+1;
end if;
fir_out <= std_logic_vector( temp );
end if;
end if;
end process;
end rtl; |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Mon Feb 20 13:53:00 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub -rename_top affine_block_ieee754_fp_multiplier_1_2 -prefix
-- affine_block_ieee754_fp_multiplier_1_2_ affine_block_ieee754_fp_multiplier_0_0_stub.vhdl
-- Design : affine_block_ieee754_fp_multiplier_0_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z010clg400-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity affine_block_ieee754_fp_multiplier_1_2 is
Port (
x : in STD_LOGIC_VECTOR ( 31 downto 0 );
y : in STD_LOGIC_VECTOR ( 31 downto 0 );
z : out STD_LOGIC_VECTOR ( 31 downto 0 )
);
end affine_block_ieee754_fp_multiplier_1_2;
architecture stub of affine_block_ieee754_fp_multiplier_1_2 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "x[31:0],y[31:0],z[31:0]";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "ieee754_fp_multiplier,Vivado 2016.4";
begin
end;
|
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity ControlUnit is
port(reset : in std_logic;
clk : in std_logic;
statop : in std_logic;
laprst : in std_logic;
cntReset : out std_logic;
cntEnable : out std_logic;
regEnable : out std_logic);
end ControlUnit;
architecture Behavioral of ControlUnit is
type TState is (TCleared, TStarted, TStopped, TLapView);
signal s_currentState, s_nextState : TState;
begin
sync_proc : process(clk)
begin
if (rising_edge(clk)) then
if (reset = '1') then
s_currentState <= TCleared;
else
s_currentState <= s_nextState;
end if;
end if;
end process;
comb_proc : process(s_currentState, statop, laprst)
begin
case (s_currentState) is
when TCleared =>
cntReset <= '1';
cntEnable <= '1';
regEnable <= '1';
if (statop = '1') then
s_nextState <= TStarted;
else
s_nextState <= TCleared;
end if;
when TStarted =>
cntReset <= '0';
cntEnable <= '1';
regEnable <= '1';
if (statop = '1') then
s_nextState <= TStopped;
elsif (laprst = '1') then
s_nextState <= TLapView;
else
s_nextState <= TStarted;
end if;
when TStopped =>
cntReset <= '0';
cntEnable <= '0';
regEnable <= '1';
if (statop = '1') then
s_nextState <= TStarted;
elsif (laprst = '1') then
s_nextState <= TCleared;
else
s_nextState <= TStopped;
end if;
when TLapView =>
cntReset <= '0';
cntEnable <= '1';
regEnable <= '0';
if (laprst = '1') then
s_nextState <= TStarted;
elsif(statop='1') then
regEnable <= '1';
s_nextState <= TCleared;
else
s_nextState <= TLapView;
end if;
end case;
end process;
end Behavioral;
|
--------------------------------------------------------------------------------
-- Gideon's Logic Architectures - Copyright 2014
-- Entity: endianness_pkg
-- Date:2015-01-15
-- Author: Gideon
-- Description:
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package endianness_pkg is
function byte_swap(a : std_logic_vector(31 downto 0); do_swap : boolean) return std_logic_vector;
end package;
package body endianness_pkg is
function byte_swap(a : std_logic_vector(31 downto 0); do_swap : boolean) return std_logic_vector is
begin
if do_swap then
return a(7 downto 0) & a(15 downto 8) & a(23 downto 16) & a(31 downto 24);
end if;
return a;
end function;
end package body;
|
entity reader is
end reader;
use std.textio.all;
architecture behav of reader is
begin
process
file f : text is in "input.txt";
variable l : line;
begin
for i in 1 to 5 loop
readline (f, l);
end loop;
wait;
end process;
end behav;
|
package pkg is
type prot_t is protected
procedure proc;
end protected;
end package;
package body pkg is
type prot_t is protected body
procedure proc is
procedure nested_proc is
begin
end procedure;
function nested_fun return integer is
begin
return 0;
end function;
function nested_ifun return integer is
begin
return 0;
end function;
begin
end procedure;
end protected body;
end package body;
|
package pkg is
type prot_t is protected
procedure proc;
end protected;
end package;
package body pkg is
type prot_t is protected body
procedure proc is
procedure nested_proc is
begin
end procedure;
function nested_fun return integer is
begin
return 0;
end function;
function nested_ifun return integer is
begin
return 0;
end function;
begin
end procedure;
end protected body;
end package body;
|
package pkg is
type prot_t is protected
procedure proc;
end protected;
end package;
package body pkg is
type prot_t is protected body
procedure proc is
procedure nested_proc is
begin
end procedure;
function nested_fun return integer is
begin
return 0;
end function;
function nested_ifun return integer is
begin
return 0;
end function;
begin
end procedure;
end protected body;
end package body;
|
package pkg is
type prot_t is protected
procedure proc;
end protected;
end package;
package body pkg is
type prot_t is protected body
procedure proc is
procedure nested_proc is
begin
end procedure;
function nested_fun return integer is
begin
return 0;
end function;
function nested_ifun return integer is
begin
return 0;
end function;
begin
end procedure;
end protected body;
end package body;
|
package pkg is
type prot_t is protected
procedure proc;
end protected;
end package;
package body pkg is
type prot_t is protected body
procedure proc is
procedure nested_proc is
begin
end procedure;
function nested_fun return integer is
begin
return 0;
end function;
function nested_ifun return integer is
begin
return 0;
end function;
begin
end procedure;
end protected body;
end package body;
|
library IEEE;
use IEEE.STD_LOGIC_1164.all;
--use IEEE.STD_LOGIC_ARITH.all;
--use IEEE.STD_LOGIC_UNSIGNED.all;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library reconos_v1_03_a;
use reconos_v1_03_a.reconos_pkg.all;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity resampling is
generic (
C_TASK_BURST_AWIDTH : integer := 11;
C_TASK_BURST_DWIDTH : integer := 32
);
port (
clk : in std_logic;
reset : in std_logic;
i_osif : in osif_os2task_t;
o_osif : out osif_task2os_t;
-- burst ram interface
o_RAMAddr : out std_logic_vector(0 to C_TASK_BURST_AWIDTH-1);
o_RAMData : out std_logic_vector(0 to C_TASK_BURST_DWIDTH-1);
i_RAMData : in std_logic_vector(0 to C_TASK_BURST_DWIDTH-1);
o_RAMWE : out std_logic;
o_RAMClk : out std_logic
);
end resampling;
architecture Behavioral of resampling is
attribute keep_hierarchy : string;
attribute keep_hierarchy of Behavioral : architecture is "true";
-- resources:
-- semaphores
constant C_SEM_WAIT : std_logic_vector(0 to 31) := X"00000000";
constant C_SEM_POST : std_logic_vector(0 to 31) := X"00000001";
-- message box
constant C_MB_START : std_logic_vector(0 to 31) := X"00000002";
constant GRANULARITY :integer := 16384;
-- states
type t_state is (STATE_INIT, STATE_GET_MB, STATE_READ_N_1, STATE_READ_N_2,
STATE_READ_PARTICLE_SIZE_1, STATE_READ_PARTICLE_SIZE_2,
STATE_SEM_WAIT, STATE_LOAD_PARTICLE, STATE_LOAD_W, STATE_CALCULATE_BEST_PARTICLE,
STATE_RESAMPLING, STATE_LOAD_WEIGHT, STATE_CALCULATE_CLONE_FACTOR_1,
STATE_CALCULATE_CLONE_FACTOR_2, STATE_CALCULATE_CLONE_FACTOR_3, STATE_CALCULATE_CLONE_FACTOR_4,
STATE_CLONE_PARTICLE, STATE_CLONE_PARTICLE_READ, STATE_CLONE_PARTICLE_WRITE,
STATE_CORRECTION_READ, STATE_CORRECTION, STATE_CORRECTION_WRITE, STATE_SEM_POST);
-- current state
signal state : t_state := STATE_SEM_WAIT;
-- input, output
signal in_value : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
signal out_value : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
-- particle array
signal particle_array_address : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1);
signal current_particle_array_address : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
-- old particle array
signal old_particle_array_address : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1);
signal current_old_particle_array_address : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
-- local RAM address
signal local_ram_address : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
-- message box
signal mb_address : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
-- number of particles (set by message box, default = 100)
signal N : integer := 100;
-- size of a particle
signal particle_size : integer := 128;
-- particle counter
signal counter : integer;
-- particle counter for clone factor
signal counter_clone_factor : integer;
-- particle counter for cloned particles at all
signal counter_cloned_particles : integer;
-- current particle weight
signal current_particle_weight : integer;
-- sum of particle weights
signal sum_of_particle_weights : integer;
-- current clone factor
signal current_clone_factor : integer;
-- best particle
signal best_particle_address : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1);
signal highest_particle_weight : integer;
--signal init_data : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
begin
-- burst ram interface is not used
o_RAMAddr <= (others => '0');
o_RAMData <= (others => '0');
o_RAMWE <= '0';
o_RAMClk <= clk;
state_proc : process(clk, reset)
-- done signal for Reconos methods
variable done : boolean;
-- success signal for Reconos method, which gets a message box
variable success : boolean;
-- signals for particle weight, N, particle_size and old_particle_array_address
variable particle_weight_sig : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
variable N_sig : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
variable particle_size_sig : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
variable old_particle_array_address_sig : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
--variable factor : integer;
begin
if reset = '1' then
reconos_reset(o_osif, i_osif);
state <= STATE_INIT;
elsif rising_edge(clk) then
reconos_begin(o_osif, i_osif);
if reconos_ready(i_osif) then
case state is
when STATE_INIT =>
--! init state, receive particle array address
reconos_get_init_data_s (done, o_osif, i_osif, particle_array_address);
if done then
state <= STATE_GET_MB;
--state <= STATE_SEM_WAIT;
end if;
when STATE_GET_MB =>
--! receive message box
--reconos_mbox_get_s(done, success, o_osif, i_osif, C_MB_START, mb_address);
reconos_mbox_get_s(done, success, o_osif, i_osif, C_MB_START, old_particle_array_address);
if done then
--old_particle_array_address <= mb_address;
state <= STATE_READ_N_1;
end if;
when STATE_READ_N_1 =>
--! read variable N (= # of particles)
reconos_mbox_get_s (done, success, o_osif, i_osif, C_MB_START, mb_address);
if done then
state <= STATE_READ_N_2;
end if;
when STATE_READ_N_2 =>
--! read variable N (= # of particles)
reconos_read (done, o_osif, i_osif, mb_address, N_sig);
if done then
N <= TO_INTEGER(SIGNED(N_sig));
state <= STATE_READ_PARTICLE_SIZE_1;
end if;
when STATE_READ_PARTICLE_SIZE_1 =>
--! read particle size
reconos_mbox_get_s (done, success, o_osif, i_osif, C_MB_START, mb_address);
if done then
state <= STATE_READ_PARTICLE_SIZE_2;
end if;
when STATE_READ_PARTICLE_SIZE_2 =>
--! read particle size
reconos_read (done, o_osif, i_osif, mb_address, particle_size_sig);
if done then
particle_size <= TO_INTEGER(SIGNED(particle_size_sig));
state <= STATE_SEM_WAIT;
end if;
when STATE_SEM_WAIT =>
--! wait for semaphore
reconos_sem_wait (o_osif, i_osif, C_SEM_WAIT);
state <= STATE_LOAD_PARTICLE;
--state <= STATE_SEM_POST;
when STATE_LOAD_PARTICLE =>
--! set current array addresses to the first elements in the arrays
-- and init sum of weights
current_old_particle_array_address <= old_particle_array_address;
current_particle_array_address <= particle_array_address;
--sum_of_particle_weights <= 0;
counter <= 0;
highest_particle_weight <= 0;
best_particle_address <= old_particle_array_address;
state <= STATE_LOAD_W;
--state <= STATE_RESAMPLING;
when STATE_LOAD_W =>
--! load weight of current particle
reconos_read(done, o_osif, i_osif, current_old_particle_array_address, particle_weight_sig);
if done then
state <= STATE_CALCULATE_BEST_PARTICLE;
current_particle_weight <= TO_INTEGER(SIGNED(particle_weight_sig));
counter <= counter + 1;
end if;
when STATE_CALCULATE_BEST_PARTICLE =>
--! calculate the sum of all particle weights
--sum_of_particle_weights <= sum_of_particle_weights + current_particle_weight;
if (current_particle_weight > highest_particle_weight) then
-- remember best position
highest_particle_weight <= current_particle_weight;
best_particle_address <= current_old_particle_array_address;
end if;
if (counter < N) then
current_old_particle_array_address <= current_old_particle_array_address + particle_size;
state <= STATE_LOAD_W;
else
state <= STATE_RESAMPLING;
--state <= STATE_SEM_POST;
end if;
--
-- THE RESAMPLING PART IN DETAIL
--
-- 0) STATE_RESAMPLING:
--
-- init addresses and counter
-- i = 0; // old_particles
-- k = 0; // particles
--
--
-- 1) STATE_LOAD_WEIGHT:
--
-- load weight of i-th old particle
-- i++
--
--
-- 2) STATE_CALCULATE_CLONE_FACTOR
--
-- calculate clone factor = round (w * N / sum_weights)
-- j = 0; // clone factor counter
--
--
-- 3) STATE_CLONE_PARTICLE
--
-- if (i > N) then
--
-- if (k < N) then
-- go to step 6 // not enough particles cloned, but no more old particles
-- else
-- go to end // enough particles cloned
-- end if
--
-- elsif (N <= k) then
--
-- go to end // enough particles cloned
--
-- elsif (clone_factor <= j)
--
-- go to step 1 // no more cloning needed for this particle, get next
--
-- elsif (j < clone_factor)
--
-- if (j == 0)
--
-- go to step 4 // first load particle to local RAM
--
-- else
--
-- go to step 5 // particle allready loaded to local RAM
--
-- end if
--
-- end if
--
--
-- 4) STATE_CLONE_PARTICLE_READ
--
-- read old particle [i] to local RAM
--
--
-- 5) STATE_CLONE_PARTICLE_WRITE
--
-- write local RAM to particle [k]
-- k++
-- j++
-- go to step 3
--
--
-- 6) STATE_CORRECTION_READ
--
-- read best particle to local RAM
--
--
-- 7) STATE_CORRECTION
--
-- if (k <= N) then
-- go to step 8
-- else
-- go to end
-- end if
--
--
-- 8) STATE_CORRECTION_WRITE
--
-- write best particle to particles[k];
-- k++;
-- go to step 7
when STATE_RESAMPLING =>
--! init counter and array addresses
current_old_particle_array_address <= old_particle_array_address;
current_particle_array_address <= particle_array_address;
counter <= 0;
counter_cloned_particles <= 0;
state <= STATE_LOAD_WEIGHT;
when STATE_LOAD_WEIGHT =>
--! load weight of current particle
reconos_read(done, o_osif, i_osif, current_old_particle_array_address, particle_weight_sig);
if done then
state <= STATE_CALCULATE_CLONE_FACTOR_1;
current_particle_weight <= TO_INTEGER(SIGNED(particle_weight_sig));
counter <= counter + 1;
end if;
when STATE_CALCULATE_CLONE_FACTOR_1 =>
--! calculate the factor the current particle has to be cloned
current_clone_factor <= 2 * N * current_particle_weight;
state <= STATE_CALCULATE_CLONE_FACTOR_2;
when STATE_CALCULATE_CLONE_FACTOR_2 =>
--! calculate the factor the current particle has to be cloned
current_clone_factor <= current_clone_factor / GRANULARITY;
state <= STATE_CALCULATE_CLONE_FACTOR_3;
when STATE_CALCULATE_CLONE_FACTOR_3 =>
--! calculate the factor the current particle has to be cloned
current_clone_factor <= current_clone_factor + 1;
state <= STATE_CALCULATE_CLONE_FACTOR_4;
when STATE_CALCULATE_CLONE_FACTOR_4 =>
--! calculate the factor the current particle has to be cloned
current_clone_factor <= current_clone_factor / 2;
counter_clone_factor <= 0;
state <= STATE_CLONE_PARTICLE;
when STATE_CLONE_PARTICLE =>
--! clone partice as often as needed
if (counter > N) then
if (counter_cloned_particles < N) then
-- there are not enough clones, so correct it
state <= STATE_CORRECTION_READ;
--state <= STATE_SEM_POST;
else
-- everything finished, because there are enough clones
state <= STATE_SEM_POST;
end if;
elsif (N <= counter_cloned_particles) then
-- everything finished, because there are enough clones
state <= STATE_SEM_POST;
elsif (current_clone_factor <= counter_clone_factor) then
-- get next particle
state <= STATE_LOAD_WEIGHT;
current_old_particle_array_address <= current_old_particle_array_address + particle_size;
elsif (counter_clone_factor < current_clone_factor) then
if (counter_clone_factor = 0) then
-- first load the particle to local RAM
state <= STATE_CLONE_PARTICLE_READ;
else
-- later, the particles can be just written
state <= STATE_CLONE_PARTICLE_WRITE;
end if;
end if;
when STATE_CLONE_PARTICLE_READ =>
--! load old particles [counter] to local RAM
reconos_read_burst(done, o_osif, i_osif, local_ram_address, current_old_particle_array_address);
if done then
state <= STATE_CLONE_PARTICLE_WRITE;
end if;
when STATE_CLONE_PARTICLE_WRITE =>
--! write particles [counter_cloned_particles] from RAM
reconos_write_burst(done, o_osif, i_osif, local_ram_address, current_particle_array_address);
if done then
state <= STATE_CLONE_PARTICLE;
counter_clone_factor <= counter_clone_factor + 1;
counter_cloned_particles <= counter_cloned_particles + 1;
current_particle_array_address <= current_particle_array_address + particle_size;
end if;
when STATE_CORRECTION_READ =>
--! load best particle
--reconos_read_burst(done, o_osif, i_osif, local_ram_address, old_particle_array_address);
reconos_read_burst(done, o_osif, i_osif, local_ram_address, best_particle_address);
if done then
state <= STATE_CORRECTION;
end if;
when STATE_CORRECTION =>
--! if less than N particles are cloned, clone another particle (the best one)
if (counter_cloned_particles <= N) then
-- write correction
state <= STATE_CORRECTION_WRITE;
else
-- correction finished, N particles are cloned
state <= STATE_SEM_POST;
end if;
when STATE_CORRECTION_WRITE =>
--! CLONE PARTICLE
-- particles_array[counter_cloned_particles] <= old_particle_array[best]
--PUT IT AWAY
--reconos_write_burst(done, o_osif, i_osif, local_ram_address, current_particle_array_address);
if done then
state <= STATE_CORRECTION;
counter_cloned_particles <= counter_cloned_particles + 1;
current_particle_array_address <= current_particle_array_address + particle_size;
end if;
when STATE_SEM_POST =>
reconos_sem_post (o_osif, i_osif, C_SEM_POST);
state <= STATE_SEM_WAIT;
when others =>
state <= STATE_SEM_WAIT;
end case;
end if;
end if;
end process;
end Behavioral;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity game_rom is
Port ( address : in STD_LOGIC_VECTOR (15 downto 0);
clock : in STD_LOGIC;
we : in STD_LOGIC;
dataIn : in STD_LOGIC_VECTOR (7 downto 0);
dataOut : out STD_LOGIC_VECTOR (7 downto 0));
end game_rom;
architecture Behavioral of game_rom is
type RAM is array ( ( 16 * 4096 ) - 1 downto 0 ) of std_logic_vector( 7 downto 0 );
signal sys_RAM : RAM := (
-- light travels left
(0 + 136) => x"00", (0 + 137) => x"00", -- delay
(0 + 138) => x"00",
512 => x"66", 513 => x"01", -- LD V6, 0x01
514 => x"61", 515 => x"3C", -- LD V1, 0x3C
516 => x"F1", 517 => x"15", -- LD DT, V1; ; loop
518 => x"86", 519 => x"6E", -- SHL V6, V6
520 => x"4F", 521 => x"01", -- SNE VF, 0x01
522 => x"66", 523 => x"01", -- LD V6, 0x01
524 => x"80", 525 => x"60", -- LD V0, V6
526 => x"A1", 527 => x"FF", -- LD I, 0x1FF
528 => x"F0", 529 => x"55", -- LD [I], V0
530 => x"F2", 531 => x"07", -- LD V2, DT ; wait
532 => x"32", 533 => x"00", -- SE V2, 0x00
534 => x"12", 535 => x"12", -- JP wait
536 => x"12", 537 => x"04", -- JP loop
-- light travels right
(4096 + 136) => x"00", (4096 + 137) => x"00", -- delay
(4096 + 138) => x"00",
(4096 + 512) => x"66", (4096 + 513) => x"80", -- LD V6, 0x80
(4096 + 514) => x"61", (4096 + 515) => x"3C", -- LD V1, 0x3C
(4096 + 516) => x"F1", (4096 + 517) => x"15", -- LD DT, V1; ; loop
(4096 + 518) => x"86", (4096 + 519) => x"66", -- SHR V6, V6
(4096 + 520) => x"4F", (4096 + 521) => x"01", -- SNE VF, 0x01
(4096 + 522) => x"66", (4096 + 523) => x"80", -- LD V6, 0x80
(4096 + 524) => x"80", (4096 + 525) => x"60", -- LD V0, V6
(4096 + 526) => x"A1", (4096 + 527) => x"FF", -- LD I, 0x1FF
(4096 + 528) => x"F0", (4096 + 529) => x"55", -- LD [I], V0
(4096 + 530) => x"F2", (4096 + 531) => x"07", -- LD V2, DT ; wait
(4096 + 532) => x"32", (4096 + 533) => x"00", -- SE V2, 0x00
(4096 + 534) => x"12", (4096 + 535) => x"12", -- JP wait
(4096 + 536) => x"12", (4096 + 537) => x"04", -- JP loop
-- random lights
(8192 + 136) => x"00", (8192 + 137) => x"00", -- delay
(8192 + 138) => x"00",
(8192 + 512) => x"61", (8192 + 513) => x"3C", -- LD V1, 0x3C
(8192 + 514) => x"F1", (8192 + 515) => x"15", -- LD DT, V1; ; loop
(8192 + 516) => x"C0", (8192 + 517) => x"FF", -- RND V0, FF
(8192 + 518) => x"A1", (8192 + 519) => x"FF", -- LD I, 0x1FF
(8192 + 520) => x"F0", (8192 + 521) => x"55", -- LD [I], V0
(8192 + 522) => x"F2", (8192 + 523) => x"07", -- LD V2, DT ; wait
(8192 + 524) => x"32", (8192 + 525) => x"00", -- SE V2, 0x00
(8192 + 526) => x"12", (8192 + 527) => x"0A", -- JP wait
(8192 + 528) => x"12", (8192 + 529) => x"02", -- JP loop
-- PONG by Paul Vervalin
(12288 + 128) => x"0C", (12288 + 129) => x"00",
(12288 + 130) => x"F0", (12288 + 131) => x"00",
(12288 + 132) => x"00", (12288 + 133) => x"00",
(12288 + 134) => x"BE", (12288 + 135) => x"00",
(12288 + 136) => x"00", (12288 + 137) => x"30", -- delay
(12288 + 138) => x"00",
(12288 + 512) => x"6a", (12288 + 513) => x"02", (12288 + 514) => x"6b", (12288 + 515) => x"0c", (12288 + 516) => x"6c", (12288 + 517) => x"3f", (12288 + 518) => x"6d", (12288 + 519) => x"0c", (12288 + 520) => x"a2", (12288 + 521) => x"ea", (12288 + 522) => x"da", (12288 + 523) => x"b6", (12288 + 524) => x"dc", (12288 + 525) => x"d6", (12288 + 526) => x"6e", (12288 + 527) => x"00", (12288 + 528) => x"22", (12288 + 529) => x"d4", (12288 + 530) => x"66", (12288 + 531) => x"03", (12288 + 532) => x"68", (12288 + 533) => x"02", (12288 + 534) => x"60", (12288 + 535) => x"60", (12288 + 536) => x"f0", (12288 + 537) => x"15", (12288 + 538) => x"f0", (12288 + 539) => x"07", (12288 + 540) => x"30", (12288 + 541) => x"00", (12288 + 542) => x"12", (12288 + 543) => x"1a", (12288 + 544) => x"c7", (12288 + 545) => x"17", (12288 + 546) => x"77", (12288 + 547) => x"08", (12288 + 548) => x"69", (12288 + 549) => x"ff", (12288 + 550) => x"a2", (12288 + 551) => x"f0", (12288 + 552) => x"d6", (12288 + 553) => x"71", (12288 + 554) => x"a2", (12288 + 555) => x"ea", (12288 + 556) => x"da", (12288 + 557) => x"b6", (12288 + 558) => x"dc", (12288 + 559) => x"d6", (12288 + 560) => x"60", (12288 + 561) => x"01", (12288 + 562) => x"e0", (12288 + 563) => x"a1", (12288 + 564) => x"7b", (12288 + 565) => x"fe", (12288 + 566) => x"60", (12288 + 567) => x"04", (12288 + 568) => x"e0", (12288 + 569) => x"a1", (12288 + 570) => x"7b", (12288 + 571) => x"02", (12288 + 572) => x"60", (12288 + 573) => x"1f", (12288 + 574) => x"8b", (12288 + 575) => x"02", (12288 + 576) => x"da", (12288 + 577) => x"b6", (12288 + 578) => x"60", (12288 + 579) => x"0c", (12288 + 580) => x"e0", (12288 + 581) => x"a1", (12288 + 582) => x"7d", (12288 + 583) => x"fe", (12288 + 584) => x"60", (12288 + 585) => x"0d", (12288 + 586) => x"e0", (12288 + 587) => x"a1", (12288 + 588) => x"7d", (12288 + 589) => x"02", (12288 + 590) => x"60", (12288 + 591) => x"1f", (12288 + 592) => x"8d", (12288 + 593) => x"02", (12288 + 594) => x"dc", (12288 + 595) => x"d6", (12288 + 596) => x"a2", (12288 + 597) => x"f0", (12288 + 598) => x"d6", (12288 + 599) => x"71", (12288 + 600) => x"86", (12288 + 601) => x"84", (12288 + 602) => x"87", (12288 + 603) => x"94", (12288 + 604) => x"60", (12288 + 605) => x"3f", (12288 + 606) => x"86", (12288 + 607) => x"02", (12288 + 608) => x"61", (12288 + 609) => x"1f", (12288 + 610) => x"87", (12288 + 611) => x"12", (12288 + 612) => x"46", (12288 + 613) => x"02", (12288 + 614) => x"12", (12288 + 615) => x"78", (12288 + 616) => x"46", (12288 + 617) => x"3f", (12288 + 618) => x"12", (12288 + 619) => x"82", (12288 + 620) => x"47", (12288 + 621) => x"1f", (12288 + 622) => x"69", (12288 + 623) => x"ff", (12288 + 624) => x"47", (12288 + 625) => x"00", (12288 + 626) => x"69", (12288 + 627) => x"01", (12288 + 628) => x"d6", (12288 + 629) => x"71", (12288 + 630) => x"12", (12288 + 631) => x"2a", (12288 + 632) => x"68", (12288 + 633) => x"02", (12288 + 634) => x"63", (12288 + 635) => x"01", (12288 + 636) => x"80", (12288 + 637) => x"70", (12288 + 638) => x"80", (12288 + 639) => x"b5", (12288 + 640) => x"12", (12288 + 641) => x"8a", (12288 + 642) => x"68", (12288 + 643) => x"fe", (12288 + 644) => x"63", (12288 + 645) => x"0a", (12288 + 646) => x"80", (12288 + 647) => x"70", (12288 + 648) => x"80", (12288 + 649) => x"d5", (12288 + 650) => x"3f", (12288 + 651) => x"01", (12288 + 652) => x"12", (12288 + 653) => x"a2", (12288 + 654) => x"61", (12288 + 655) => x"02", (12288 + 656) => x"80", (12288 + 657) => x"15", (12288 + 658) => x"3f", (12288 + 659) => x"01", (12288 + 660) => x"12", (12288 + 661) => x"ba", (12288 + 662) => x"80", (12288 + 663) => x"15", (12288 + 664) => x"3f", (12288 + 665) => x"01", (12288 + 666) => x"12", (12288 + 667) => x"c8", (12288 + 668) => x"80", (12288 + 669) => x"15", (12288 + 670) => x"3f", (12288 + 671) => x"01", (12288 + 672) => x"12", (12288 + 673) => x"c2", (12288 + 674) => x"60", (12288 + 675) => x"20", (12288 + 676) => x"f0", (12288 + 677) => x"18", (12288 + 678) => x"22", (12288 + 679) => x"d4", (12288 + 680) => x"8e", (12288 + 681) => x"34", (12288 + 682) => x"22", (12288 + 683) => x"d4", (12288 + 684) => x"66", (12288 + 685) => x"3e", (12288 + 686) => x"33", (12288 + 687) => x"01", (12288 + 688) => x"66", (12288 + 689) => x"03", (12288 + 690) => x"68", (12288 + 691) => x"fe", (12288 + 692) => x"33", (12288 + 693) => x"01", (12288 + 694) => x"68", (12288 + 695) => x"02", (12288 + 696) => x"12", (12288 + 697) => x"16", (12288 + 698) => x"79", (12288 + 699) => x"ff", (12288 + 700) => x"49", (12288 + 701) => x"fe", (12288 + 702) => x"69", (12288 + 703) => x"ff", (12288 + 704) => x"12", (12288 + 705) => x"c8", (12288 + 706) => x"79", (12288 + 707) => x"01", (12288 + 708) => x"49", (12288 + 709) => x"02", (12288 + 710) => x"69", (12288 + 711) => x"01", (12288 + 712) => x"60", (12288 + 713) => x"04", (12288 + 714) => x"f0", (12288 + 715) => x"18", (12288 + 716) => x"76", (12288 + 717) => x"01", (12288 + 718) => x"46", (12288 + 719) => x"40", (12288 + 720) => x"76", (12288 + 721) => x"fe", (12288 + 722) => x"12", (12288 + 723) => x"6c", (12288 + 724) => x"a2", (12288 + 725) => x"f2", (12288 + 726) => x"fe", (12288 + 727) => x"33", (12288 + 728) => x"f2", (12288 + 729) => x"65", (12288 + 730) => x"f1", (12288 + 731) => x"29", (12288 + 732) => x"64", (12288 + 733) => x"14", (12288 + 734) => x"65", (12288 + 735) => x"00", (12288 + 736) => x"d4", (12288 + 737) => x"55", (12288 + 738) => x"74", (12288 + 739) => x"15", (12288 + 740) => x"f2", (12288 + 741) => x"29", (12288 + 742) => x"d4", (12288 + 743) => x"55", (12288 + 744) => x"00", (12288 + 745) => x"ee", (12288 + 746) => x"80", (12288 + 747) => x"80", (12288 + 748) => x"80", (12288 + 749) => x"80", (12288 + 750) => x"80", (12288 + 751) => x"80", (12288 + 752) => x"80", (12288 + 753) => x"00", (12288 + 754) => x"00", (12288 + 755) => x"00", (12288 + 756) => x"00", (12288 + 757) => x"00",
-- Tetris by Fran Dachille
(16384 + 128) => x"00", (16384 + 129) => x"F0",
(16384 + 130) => x"DC", (16384 + 131) => x"E0",
(16384 + 132) => x"F0", (16384 + 133) => x"00",
(16384 + 134) => x"BE", (16384 + 135) => x"00",
(16384 + 136) => x"00", (16384 + 137) => x"20", -- delay
(16384 + 138) => x"00",
(16384 + 512) => x"a2", (16384 + 513) => x"b4", (16384 + 514) => x"23", (16384 + 515) => x"e6", (16384 + 516) => x"22", (16384 + 517) => x"b6", (16384 + 518) => x"70", (16384 + 519) => x"01", (16384 + 520) => x"d0", (16384 + 521) => x"11", (16384 + 522) => x"30", (16384 + 523) => x"25", (16384 + 524) => x"12", (16384 + 525) => x"06", (16384 + 526) => x"71", (16384 + 527) => x"ff", (16384 + 528) => x"d0", (16384 + 529) => x"11", (16384 + 530) => x"60", (16384 + 531) => x"1a", (16384 + 532) => x"d0", (16384 + 533) => x"11", (16384 + 534) => x"60", (16384 + 535) => x"25", (16384 + 536) => x"31", (16384 + 537) => x"00", (16384 + 538) => x"12", (16384 + 539) => x"0e", (16384 + 540) => x"c4", (16384 + 541) => x"70", (16384 + 542) => x"44", (16384 + 543) => x"70", (16384 + 544) => x"12", (16384 + 545) => x"1c", (16384 + 546) => x"c3", (16384 + 547) => x"03", (16384 + 548) => x"60", (16384 + 549) => x"1e", (16384 + 550) => x"61", (16384 + 551) => x"03", (16384 + 552) => x"22", (16384 + 553) => x"5c", (16384 + 554) => x"f5", (16384 + 555) => x"15", (16384 + 556) => x"d0", (16384 + 557) => x"14", (16384 + 558) => x"3f", (16384 + 559) => x"01", (16384 + 560) => x"12", (16384 + 561) => x"3c", (16384 + 562) => x"d0", (16384 + 563) => x"14", (16384 + 564) => x"71", (16384 + 565) => x"ff", (16384 + 566) => x"d0", (16384 + 567) => x"14", (16384 + 568) => x"23", (16384 + 569) => x"40", (16384 + 570) => x"12", (16384 + 571) => x"1c", (16384 + 572) => x"e7", (16384 + 573) => x"a1", (16384 + 574) => x"22", (16384 + 575) => x"72", (16384 + 576) => x"e8", (16384 + 577) => x"a1", (16384 + 578) => x"22", (16384 + 579) => x"84", (16384 + 580) => x"e9", (16384 + 581) => x"a1", (16384 + 582) => x"22", (16384 + 583) => x"96", (16384 + 584) => x"e2", (16384 + 585) => x"9e", (16384 + 586) => x"12", (16384 + 587) => x"50", (16384 + 588) => x"66", (16384 + 589) => x"00", (16384 + 590) => x"f6", (16384 + 591) => x"15", (16384 + 592) => x"f6", (16384 + 593) => x"07", (16384 + 594) => x"36", (16384 + 595) => x"00", (16384 + 596) => x"12", (16384 + 597) => x"3c", (16384 + 598) => x"d0", (16384 + 599) => x"14", (16384 + 600) => x"71", (16384 + 601) => x"01", (16384 + 602) => x"12", (16384 + 603) => x"2a", (16384 + 604) => x"a2", (16384 + 605) => x"c4", (16384 + 606) => x"f4", (16384 + 607) => x"1e", (16384 + 608) => x"66", (16384 + 609) => x"00", (16384 + 610) => x"43", (16384 + 611) => x"01", (16384 + 612) => x"66", (16384 + 613) => x"04", (16384 + 614) => x"43", (16384 + 615) => x"02", (16384 + 616) => x"66", (16384 + 617) => x"08", (16384 + 618) => x"43", (16384 + 619) => x"03", (16384 + 620) => x"66", (16384 + 621) => x"0c", (16384 + 622) => x"f6", (16384 + 623) => x"1e", (16384 + 624) => x"00", (16384 + 625) => x"ee", (16384 + 626) => x"d0", (16384 + 627) => x"14", (16384 + 628) => x"70", (16384 + 629) => x"ff", (16384 + 630) => x"23", (16384 + 631) => x"34", (16384 + 632) => x"3f", (16384 + 633) => x"01", (16384 + 634) => x"00", (16384 + 635) => x"ee", (16384 + 636) => x"d0", (16384 + 637) => x"14", (16384 + 638) => x"70", (16384 + 639) => x"01", (16384 + 640) => x"23", (16384 + 641) => x"34", (16384 + 642) => x"00", (16384 + 643) => x"ee", (16384 + 644) => x"d0", (16384 + 645) => x"14", (16384 + 646) => x"70", (16384 + 647) => x"01", (16384 + 648) => x"23", (16384 + 649) => x"34", (16384 + 650) => x"3f", (16384 + 651) => x"01", (16384 + 652) => x"00", (16384 + 653) => x"ee", (16384 + 654) => x"d0", (16384 + 655) => x"14", (16384 + 656) => x"70", (16384 + 657) => x"ff", (16384 + 658) => x"23", (16384 + 659) => x"34", (16384 + 660) => x"00", (16384 + 661) => x"ee", (16384 + 662) => x"d0", (16384 + 663) => x"14", (16384 + 664) => x"73", (16384 + 665) => x"01", (16384 + 666) => x"43", (16384 + 667) => x"04", (16384 + 668) => x"63", (16384 + 669) => x"00", (16384 + 670) => x"22", (16384 + 671) => x"5c", (16384 + 672) => x"23", (16384 + 673) => x"34", (16384 + 674) => x"3f", (16384 + 675) => x"01", (16384 + 676) => x"00", (16384 + 677) => x"ee", (16384 + 678) => x"d0", (16384 + 679) => x"14", (16384 + 680) => x"73", (16384 + 681) => x"ff", (16384 + 682) => x"43", (16384 + 683) => x"ff", (16384 + 684) => x"63", (16384 + 685) => x"03", (16384 + 686) => x"22", (16384 + 687) => x"5c", (16384 + 688) => x"23", (16384 + 689) => x"34", (16384 + 690) => x"00", (16384 + 691) => x"ee", (16384 + 692) => x"80", (16384 + 693) => x"00", (16384 + 694) => x"67", (16384 + 695) => x"05", (16384 + 696) => x"68", (16384 + 697) => x"06", (16384 + 698) => x"69", (16384 + 699) => x"04", (16384 + 700) => x"61", (16384 + 701) => x"1f", (16384 + 702) => x"65", (16384 + 703) => x"10", (16384 + 704) => x"62", (16384 + 705) => x"07", (16384 + 706) => x"00", (16384 + 707) => x"ee", (16384 + 708) => x"40", (16384 + 709) => x"e0", (16384 + 710) => x"00", (16384 + 711) => x"00", (16384 + 712) => x"40", (16384 + 713) => x"c0", (16384 + 714) => x"40", (16384 + 715) => x"00", (16384 + 716) => x"00", (16384 + 717) => x"e0", (16384 + 718) => x"40", (16384 + 719) => x"00", (16384 + 720) => x"40", (16384 + 721) => x"60", (16384 + 722) => x"40", (16384 + 723) => x"00", (16384 + 724) => x"40", (16384 + 725) => x"40", (16384 + 726) => x"60", (16384 + 727) => x"00", (16384 + 728) => x"20", (16384 + 729) => x"e0", (16384 + 730) => x"00", (16384 + 731) => x"00", (16384 + 732) => x"c0", (16384 + 733) => x"40", (16384 + 734) => x"40", (16384 + 735) => x"00", (16384 + 736) => x"00", (16384 + 737) => x"e0", (16384 + 738) => x"80", (16384 + 739) => x"00", (16384 + 740) => x"40", (16384 + 741) => x"40", (16384 + 742) => x"c0", (16384 + 743) => x"00", (16384 + 744) => x"00", (16384 + 745) => x"e0", (16384 + 746) => x"20", (16384 + 747) => x"00", (16384 + 748) => x"60", (16384 + 749) => x"40", (16384 + 750) => x"40", (16384 + 751) => x"00", (16384 + 752) => x"80", (16384 + 753) => x"e0", (16384 + 754) => x"00", (16384 + 755) => x"00", (16384 + 756) => x"40", (16384 + 757) => x"c0", (16384 + 758) => x"80", (16384 + 759) => x"00", (16384 + 760) => x"c0", (16384 + 761) => x"60", (16384 + 762) => x"00", (16384 + 763) => x"00", (16384 + 764) => x"40", (16384 + 765) => x"c0", (16384 + 766) => x"80", (16384 + 767) => x"00", (16384 + 768) => x"c0", (16384 + 769) => x"60", (16384 + 770) => x"00", (16384 + 771) => x"00", (16384 + 772) => x"80", (16384 + 773) => x"c0", (16384 + 774) => x"40", (16384 + 775) => x"00", (16384 + 776) => x"00", (16384 + 777) => x"60", (16384 + 778) => x"c0", (16384 + 779) => x"00", (16384 + 780) => x"80", (16384 + 781) => x"c0", (16384 + 782) => x"40", (16384 + 783) => x"00", (16384 + 784) => x"00", (16384 + 785) => x"60", (16384 + 786) => x"c0", (16384 + 787) => x"00", (16384 + 788) => x"c0", (16384 + 789) => x"c0", (16384 + 790) => x"00", (16384 + 791) => x"00", (16384 + 792) => x"c0", (16384 + 793) => x"c0", (16384 + 794) => x"00", (16384 + 795) => x"00", (16384 + 796) => x"c0", (16384 + 797) => x"c0", (16384 + 798) => x"00", (16384 + 799) => x"00", (16384 + 800) => x"c0", (16384 + 801) => x"c0", (16384 + 802) => x"00", (16384 + 803) => x"00", (16384 + 804) => x"40", (16384 + 805) => x"40", (16384 + 806) => x"40", (16384 + 807) => x"40", (16384 + 808) => x"00", (16384 + 809) => x"f0", (16384 + 810) => x"00", (16384 + 811) => x"00", (16384 + 812) => x"40", (16384 + 813) => x"40", (16384 + 814) => x"40", (16384 + 815) => x"40", (16384 + 816) => x"00", (16384 + 817) => x"f0", (16384 + 818) => x"00", (16384 + 819) => x"00", (16384 + 820) => x"d0", (16384 + 821) => x"14", (16384 + 822) => x"66", (16384 + 823) => x"35", (16384 + 824) => x"76", (16384 + 825) => x"ff", (16384 + 826) => x"36", (16384 + 827) => x"00", (16384 + 828) => x"13", (16384 + 829) => x"38", (16384 + 830) => x"00", (16384 + 831) => x"ee", (16384 + 832) => x"a2", (16384 + 833) => x"b4", (16384 + 834) => x"8c", (16384 + 835) => x"10", (16384 + 836) => x"3c", (16384 + 837) => x"1e", (16384 + 838) => x"7c", (16384 + 839) => x"01", (16384 + 840) => x"3c", (16384 + 841) => x"1e", (16384 + 842) => x"7c", (16384 + 843) => x"01", (16384 + 844) => x"3c", (16384 + 845) => x"1e", (16384 + 846) => x"7c", (16384 + 847) => x"01", (16384 + 848) => x"23", (16384 + 849) => x"5e", (16384 + 850) => x"4b", (16384 + 851) => x"0a", (16384 + 852) => x"23", (16384 + 853) => x"72", (16384 + 854) => x"91", (16384 + 855) => x"c0", (16384 + 856) => x"00", (16384 + 857) => x"ee", (16384 + 858) => x"71", (16384 + 859) => x"01", (16384 + 860) => x"13", (16384 + 861) => x"50", (16384 + 862) => x"60", (16384 + 863) => x"1b", (16384 + 864) => x"6b", (16384 + 865) => x"00", (16384 + 866) => x"d0", (16384 + 867) => x"11", (16384 + 868) => x"3f", (16384 + 869) => x"00", (16384 + 870) => x"7b", (16384 + 871) => x"01", (16384 + 872) => x"d0", (16384 + 873) => x"11", (16384 + 874) => x"70", (16384 + 875) => x"01", (16384 + 876) => x"30", (16384 + 877) => x"25", (16384 + 878) => x"13", (16384 + 879) => x"62", (16384 + 880) => x"00", (16384 + 881) => x"ee", (16384 + 882) => x"60", (16384 + 883) => x"1b", (16384 + 884) => x"d0", (16384 + 885) => x"11", (16384 + 886) => x"70", (16384 + 887) => x"01", (16384 + 888) => x"30", (16384 + 889) => x"25", (16384 + 890) => x"13", (16384 + 891) => x"74", (16384 + 892) => x"8e", (16384 + 893) => x"10", (16384 + 894) => x"8d", (16384 + 895) => x"e0", (16384 + 896) => x"7e", (16384 + 897) => x"ff", (16384 + 898) => x"60", (16384 + 899) => x"1b", (16384 + 900) => x"6b", (16384 + 901) => x"00", (16384 + 902) => x"d0", (16384 + 903) => x"e1", (16384 + 904) => x"3f", (16384 + 905) => x"00", (16384 + 906) => x"13", (16384 + 907) => x"90", (16384 + 908) => x"d0", (16384 + 909) => x"e1", (16384 + 910) => x"13", (16384 + 911) => x"94", (16384 + 912) => x"d0", (16384 + 913) => x"d1", (16384 + 914) => x"7b", (16384 + 915) => x"01", (16384 + 916) => x"70", (16384 + 917) => x"01", (16384 + 918) => x"30", (16384 + 919) => x"25", (16384 + 920) => x"13", (16384 + 921) => x"86", (16384 + 922) => x"4b", (16384 + 923) => x"00", (16384 + 924) => x"13", (16384 + 925) => x"a6", (16384 + 926) => x"7d", (16384 + 927) => x"ff", (16384 + 928) => x"7e", (16384 + 929) => x"ff", (16384 + 930) => x"3d", (16384 + 931) => x"01", (16384 + 932) => x"13", (16384 + 933) => x"82", (16384 + 934) => x"23", (16384 + 935) => x"c0", (16384 + 936) => x"3f", (16384 + 937) => x"01", (16384 + 938) => x"23", (16384 + 939) => x"c0", (16384 + 940) => x"7a", (16384 + 941) => x"01", (16384 + 942) => x"23", (16384 + 943) => x"c0", (16384 + 944) => x"80", (16384 + 945) => x"a0", (16384 + 946) => x"6d", (16384 + 947) => x"07", (16384 + 948) => x"80", (16384 + 949) => x"d2", (16384 + 950) => x"40", (16384 + 951) => x"04", (16384 + 952) => x"75", (16384 + 953) => x"fe", (16384 + 954) => x"45", (16384 + 955) => x"02", (16384 + 956) => x"65", (16384 + 957) => x"04", (16384 + 958) => x"00", (16384 + 959) => x"ee", (16384 + 960) => x"a7", (16384 + 961) => x"00", (16384 + 962) => x"f2", (16384 + 963) => x"55", (16384 + 964) => x"a8", (16384 + 965) => x"04", (16384 + 966) => x"fa", (16384 + 967) => x"33", (16384 + 968) => x"f2", (16384 + 969) => x"65", (16384 + 970) => x"f0", (16384 + 971) => x"29", (16384 + 972) => x"6d", (16384 + 973) => x"32", (16384 + 974) => x"6e", (16384 + 975) => x"00", (16384 + 976) => x"dd", (16384 + 977) => x"e5", (16384 + 978) => x"7d", (16384 + 979) => x"05", (16384 + 980) => x"f1", (16384 + 981) => x"29", (16384 + 982) => x"dd", (16384 + 983) => x"e5", (16384 + 984) => x"7d", (16384 + 985) => x"05", (16384 + 986) => x"f2", (16384 + 987) => x"29", (16384 + 988) => x"dd", (16384 + 989) => x"e5", (16384 + 990) => x"a7", (16384 + 991) => x"00", (16384 + 992) => x"f2", (16384 + 993) => x"65", (16384 + 994) => x"a2", (16384 + 995) => x"b4", (16384 + 996) => x"00", (16384 + 997) => x"ee", (16384 + 998) => x"6a", (16384 + 999) => x"00", (16384 + 1000) => x"60", (16384 + 1001) => x"19", (16384 + 1002) => x"00", (16384 + 1003) => x"ee", (16384 + 1004) => x"37", (16384 + 1005) => x"23",
-- Blitz by David Winter
(20480 + 128) => x"00", (20480 + 129) => x"00",
(20480 + 130) => x"0D", (20480 + 131) => x"00",
(20480 + 132) => x"00", (20480 + 133) => x"00",
(20480 + 134) => x"00", (20480 + 135) => x"00",
(20480 + 136) => x"00", (20480 + 137) => x"20", -- delay
(20480 + 138) => x"00",
(20480 + 512) => x"12", (20480 + 513) => x"17", (20480 + 514) => x"42", (20480 + 515) => x"4c", (20480 + 516) => x"49", (20480 + 517) => x"54", (20480 + 518) => x"5a", (20480 + 519) => x"20", (20480 + 520) => x"42", (20480 + 521) => x"79", (20480 + 522) => x"20", (20480 + 523) => x"44", (20480 + 524) => x"61", (20480 + 525) => x"76", (20480 + 526) => x"69", (20480 + 527) => x"64", (20480 + 528) => x"20", (20480 + 529) => x"57", (20480 + 530) => x"49", (20480 + 531) => x"4e", (20480 + 532) => x"54", (20480 + 533) => x"45", (20480 + 534) => x"52", (20480 + 535) => x"a3", (20480 + 536) => x"41", (20480 + 537) => x"60", (20480 + 538) => x"04", (20480 + 539) => x"61", (20480 + 540) => x"09", (20480 + 541) => x"62", (20480 + 542) => x"0e", (20480 + 543) => x"67", (20480 + 544) => x"04", (20480 + 545) => x"d0", (20480 + 546) => x"1e", (20480 + 547) => x"f2", (20480 + 548) => x"1e", (20480 + 549) => x"70", (20480 + 550) => x"0c", (20480 + 551) => x"30", (20480 + 552) => x"40", (20480 + 553) => x"12", (20480 + 554) => x"21", (20480 + 555) => x"f0", (20480 + 556) => x"0a", (20480 + 557) => x"00", (20480 + 558) => x"e0", (20480 + 559) => x"22", (20480 + 560) => x"d9", (20480 + 561) => x"f0", (20480 + 562) => x"0a", (20480 + 563) => x"00", (20480 + 564) => x"e0", (20480 + 565) => x"8e", (20480 + 566) => x"70", (20480 + 567) => x"a3", (20480 + 568) => x"1e", (20480 + 569) => x"6b", (20480 + 570) => x"1f", (20480 + 571) => x"cc", (20480 + 572) => x"1f", (20480 + 573) => x"8c", (20480 + 574) => x"c4", (20480 + 575) => x"dc", (20480 + 576) => x"b2", (20480 + 577) => x"3f", (20480 + 578) => x"01", (20480 + 579) => x"12", (20480 + 580) => x"49", (20480 + 581) => x"dc", (20480 + 582) => x"b2", (20480 + 583) => x"12", (20480 + 584) => x"39", (20480 + 585) => x"ca", (20480 + 586) => x"07", (20480 + 587) => x"7a", (20480 + 588) => x"01", (20480 + 589) => x"7b", (20480 + 590) => x"fe", (20480 + 591) => x"dc", (20480 + 592) => x"b2", (20480 + 593) => x"7a", (20480 + 594) => x"ff", (20480 + 595) => x"3a", (20480 + 596) => x"00", (20480 + 597) => x"12", (20480 + 598) => x"4d", (20480 + 599) => x"7e", (20480 + 600) => x"ff", (20480 + 601) => x"3e", (20480 + 602) => x"00", (20480 + 603) => x"12", (20480 + 604) => x"39", (20480 + 605) => x"6b", (20480 + 606) => x"00", (20480 + 607) => x"8c", (20480 + 608) => x"70", (20480 + 609) => x"6d", (20480 + 610) => x"00", (20480 + 611) => x"6e", (20480 + 612) => x"00", (20480 + 613) => x"a3", (20480 + 614) => x"1b", (20480 + 615) => x"dd", (20480 + 616) => x"e3", (20480 + 617) => x"3f", (20480 + 618) => x"00", (20480 + 619) => x"12", (20480 + 620) => x"c1", (20480 + 621) => x"3b", (20480 + 622) => x"00", (20480 + 623) => x"12", (20480 + 624) => x"81", (20480 + 625) => x"60", (20480 + 626) => x"05", (20480 + 627) => x"e0", (20480 + 628) => x"9e", (20480 + 629) => x"12", (20480 + 630) => x"87", (20480 + 631) => x"6b", (20480 + 632) => x"01", (20480 + 633) => x"88", (20480 + 634) => x"d0", (20480 + 635) => x"78", (20480 + 636) => x"02", (20480 + 637) => x"89", (20480 + 638) => x"e0", (20480 + 639) => x"79", (20480 + 640) => x"03", (20480 + 641) => x"a3", (20480 + 642) => x"1e", (20480 + 643) => x"d8", (20480 + 644) => x"91", (20480 + 645) => x"81", (20480 + 646) => x"f0", (20480 + 647) => x"60", (20480 + 648) => x"05", (20480 + 649) => x"f0", (20480 + 650) => x"15", (20480 + 651) => x"f0", (20480 + 652) => x"07", (20480 + 653) => x"30", (20480 + 654) => x"00", (20480 + 655) => x"12", (20480 + 656) => x"8b", (20480 + 657) => x"3b", (20480 + 658) => x"01", (20480 + 659) => x"12", (20480 + 660) => x"ab", (20480 + 661) => x"a3", (20480 + 662) => x"1e", (20480 + 663) => x"31", (20480 + 664) => x"01", (20480 + 665) => x"d8", (20480 + 666) => x"91", (20480 + 667) => x"79", (20480 + 668) => x"01", (20480 + 669) => x"39", (20480 + 670) => x"20", (20480 + 671) => x"12", (20480 + 672) => x"ab", (20480 + 673) => x"6b", (20480 + 674) => x"00", (20480 + 675) => x"31", (20480 + 676) => x"00", (20480 + 677) => x"7c", (20480 + 678) => x"ff", (20480 + 679) => x"4c", (20480 + 680) => x"00", (20480 + 681) => x"12", (20480 + 682) => x"bb", (20480 + 683) => x"a3", (20480 + 684) => x"1b", (20480 + 685) => x"dd", (20480 + 686) => x"e3", (20480 + 687) => x"7d", (20480 + 688) => x"02", (20480 + 689) => x"3d", (20480 + 690) => x"40", (20480 + 691) => x"12", (20480 + 692) => x"b9", (20480 + 693) => x"6d", (20480 + 694) => x"00", (20480 + 695) => x"7e", (20480 + 696) => x"01", (20480 + 697) => x"12", (20480 + 698) => x"65", (20480 + 699) => x"00", (20480 + 700) => x"e0", (20480 + 701) => x"77", (20480 + 702) => x"02", (20480 + 703) => x"12", (20480 + 704) => x"2d", (20480 + 705) => x"a3", (20480 + 706) => x"1b", (20480 + 707) => x"dd", (20480 + 708) => x"e3", (20480 + 709) => x"60", (20480 + 710) => x"14", (20480 + 711) => x"61", (20480 + 712) => x"02", (20480 + 713) => x"62", (20480 + 714) => x"0b", (20480 + 715) => x"a3", (20480 + 716) => x"20", (20480 + 717) => x"d0", (20480 + 718) => x"1b", (20480 + 719) => x"f2", (20480 + 720) => x"1e", (20480 + 721) => x"70", (20480 + 722) => x"08", (20480 + 723) => x"30", (20480 + 724) => x"2c", (20480 + 725) => x"12", (20480 + 726) => x"cd", (20480 + 727) => x"12", (20480 + 728) => x"d7", (20480 + 729) => x"60", (20480 + 730) => x"0a", (20480 + 731) => x"61", (20480 + 732) => x"0d", (20480 + 733) => x"62", (20480 + 734) => x"05", (20480 + 735) => x"a3", (20480 + 736) => x"07", (20480 + 737) => x"d0", (20480 + 738) => x"15", (20480 + 739) => x"f2", (20480 + 740) => x"1e", (20480 + 741) => x"70", (20480 + 742) => x"08", (20480 + 743) => x"30", (20480 + 744) => x"2a", (20480 + 745) => x"12", (20480 + 746) => x"e1", (20480 + 747) => x"80", (20480 + 748) => x"70", (20480 + 749) => x"70", (20480 + 750) => x"fe", (20480 + 751) => x"80", (20480 + 752) => x"06", (20480 + 753) => x"a3", (20480 + 754) => x"87", (20480 + 755) => x"f0", (20480 + 756) => x"33", (20480 + 757) => x"f2", (20480 + 758) => x"65", (20480 + 759) => x"60", (20480 + 760) => x"2d", (20480 + 761) => x"f1", (20480 + 762) => x"29", (20480 + 763) => x"61", (20480 + 764) => x"0d", (20480 + 765) => x"d0", (20480 + 766) => x"15", (20480 + 767) => x"70", (20480 + 768) => x"05", (20480 + 769) => x"f2", (20480 + 770) => x"29", (20480 + 771) => x"d0", (20480 + 772) => x"15", (20480 + 773) => x"00", (20480 + 774) => x"ee", (20480 + 775) => x"83", (20480 + 776) => x"82", (20480 + 777) => x"83", (20480 + 778) => x"82", (20480 + 779) => x"fb", (20480 + 780) => x"e8", (20480 + 781) => x"08", (20480 + 782) => x"88", (20480 + 783) => x"05", (20480 + 784) => x"e2", (20480 + 785) => x"be", (20480 + 786) => x"a0", (20480 + 787) => x"b8", (20480 + 788) => x"20", (20480 + 789) => x"3e", (20480 + 790) => x"80", (20480 + 791) => x"80", (20480 + 792) => x"80", (20480 + 793) => x"80", (20480 + 794) => x"f8", (20480 + 795) => x"80", (20480 + 796) => x"f8", (20480 + 797) => x"fc", (20480 + 798) => x"c0", (20480 + 799) => x"c0", (20480 + 800) => x"f9", (20480 + 801) => x"81", (20480 + 802) => x"db", (20480 + 803) => x"cb", (20480 + 804) => x"fb", (20480 + 805) => x"00", (20480 + 806) => x"fa", (20480 + 807) => x"8a", (20480 + 808) => x"9a", (20480 + 809) => x"99", (20480 + 810) => x"f8", (20480 + 811) => x"ef", (20480 + 812) => x"2a", (20480 + 813) => x"e8", (20480 + 814) => x"29", (20480 + 815) => x"29", (20480 + 816) => x"00", (20480 + 817) => x"6f", (20480 + 818) => x"68", (20480 + 819) => x"2e", (20480 + 820) => x"4c", (20480 + 821) => x"8f", (20480 + 822) => x"be", (20480 + 823) => x"a0", (20480 + 824) => x"b8", (20480 + 825) => x"b0", (20480 + 826) => x"be", (20480 + 827) => x"00", (20480 + 828) => x"be", (20480 + 829) => x"22", (20480 + 830) => x"3e", (20480 + 831) => x"34", (20480 + 832) => x"b2", (20480 + 833) => x"d8", (20480 + 834) => x"d8", (20480 + 835) => x"00", (20480 + 836) => x"c3", (20480 + 837) => x"c3", (20480 + 838) => x"00", (20480 + 839) => x"d8", (20480 + 840) => x"d8", (20480 + 841) => x"00", (20480 + 842) => x"c3", (20480 + 843) => x"c3", (20480 + 844) => x"00", (20480 + 845) => x"d8", (20480 + 846) => x"d8", (20480 + 847) => x"c0", (20480 + 848) => x"c0", (20480 + 849) => x"00", (20480 + 850) => x"c0", (20480 + 851) => x"c0", (20480 + 852) => x"00", (20480 + 853) => x"c0", (20480 + 854) => x"c0", (20480 + 855) => x"00", (20480 + 856) => x"c0", (20480 + 857) => x"c0", (20480 + 858) => x"00", (20480 + 859) => x"db", (20480 + 860) => x"db", (20480 + 861) => x"db", (20480 + 862) => x"db", (20480 + 863) => x"00", (20480 + 864) => x"18", (20480 + 865) => x"18", (20480 + 866) => x"00", (20480 + 867) => x"18", (20480 + 868) => x"18", (20480 + 869) => x"00", (20480 + 870) => x"18", (20480 + 871) => x"18", (20480 + 872) => x"00", (20480 + 873) => x"db", (20480 + 874) => x"db", (20480 + 875) => x"db", (20480 + 876) => x"db", (20480 + 877) => x"00", (20480 + 878) => x"18", (20480 + 879) => x"18", (20480 + 880) => x"00", (20480 + 881) => x"18", (20480 + 882) => x"18", (20480 + 883) => x"00", (20480 + 884) => x"18", (20480 + 885) => x"18", (20480 + 886) => x"00", (20480 + 887) => x"18", (20480 + 888) => x"18", (20480 + 889) => x"db", (20480 + 890) => x"db", (20480 + 891) => x"00", (20480 + 892) => x"03", (20480 + 893) => x"03", (20480 + 894) => x"00", (20480 + 895) => x"18", (20480 + 896) => x"18", (20480 + 897) => x"00", (20480 + 898) => x"c0", (20480 + 899) => x"c0", (20480 + 900) => x"00", (20480 + 901) => x"db", (20480 + 902) => x"db", (20480 + 903) => x"00",
-- Brix by Andre Gustafsson
(24576 + 128) => x"00", (24576 + 129) => x"00",
(24576 + 130) => x"C0", (24576 + 131) => x"E0",
(24576 + 132) => x"00", (24576 + 133) => x"00",
(24576 + 134) => x"00", (24576 + 135) => x"00",
(24576 + 136) => x"00", (24576 + 137) => x"30", -- delay
(24576 + 138) => x"00",
(24576 + 512) => x"6e", (24576 + 513) => x"05", (24576 + 514) => x"65", (24576 + 515) => x"00", (24576 + 516) => x"6b", (24576 + 517) => x"06", (24576 + 518) => x"6a", (24576 + 519) => x"00", (24576 + 520) => x"a3", (24576 + 521) => x"0c", (24576 + 522) => x"da", (24576 + 523) => x"b1", (24576 + 524) => x"7a", (24576 + 525) => x"04", (24576 + 526) => x"3a", (24576 + 527) => x"40", (24576 + 528) => x"12", (24576 + 529) => x"08", (24576 + 530) => x"7b", (24576 + 531) => x"02", (24576 + 532) => x"3b", (24576 + 533) => x"12", (24576 + 534) => x"12", (24576 + 535) => x"06", (24576 + 536) => x"6c", (24576 + 537) => x"20", (24576 + 538) => x"6d", (24576 + 539) => x"1f", (24576 + 540) => x"a3", (24576 + 541) => x"10", (24576 + 542) => x"dc", (24576 + 543) => x"d1", (24576 + 544) => x"22", (24576 + 545) => x"f6", (24576 + 546) => x"60", (24576 + 547) => x"00", (24576 + 548) => x"61", (24576 + 549) => x"00", (24576 + 550) => x"a3", (24576 + 551) => x"12", (24576 + 552) => x"d0", (24576 + 553) => x"11", (24576 + 554) => x"70", (24576 + 555) => x"08", (24576 + 556) => x"a3", (24576 + 557) => x"0e", (24576 + 558) => x"d0", (24576 + 559) => x"11", (24576 + 560) => x"60", (24576 + 561) => x"40", (24576 + 562) => x"f0", (24576 + 563) => x"15", (24576 + 564) => x"f0", (24576 + 565) => x"07", (24576 + 566) => x"30", (24576 + 567) => x"00", (24576 + 568) => x"12", (24576 + 569) => x"34", (24576 + 570) => x"c6", (24576 + 571) => x"0f", (24576 + 572) => x"67", (24576 + 573) => x"1e", (24576 + 574) => x"68", (24576 + 575) => x"01", (24576 + 576) => x"69", (24576 + 577) => x"ff", (24576 + 578) => x"a3", (24576 + 579) => x"0e", (24576 + 580) => x"d6", (24576 + 581) => x"71", (24576 + 582) => x"a3", (24576 + 583) => x"10", (24576 + 584) => x"dc", (24576 + 585) => x"d1", (24576 + 586) => x"60", (24576 + 587) => x"04", (24576 + 588) => x"e0", (24576 + 589) => x"a1", (24576 + 590) => x"7c", (24576 + 591) => x"fe", (24576 + 592) => x"60", (24576 + 593) => x"06", (24576 + 594) => x"e0", (24576 + 595) => x"a1", (24576 + 596) => x"7c", (24576 + 597) => x"02", (24576 + 598) => x"60", (24576 + 599) => x"3f", (24576 + 600) => x"8c", (24576 + 601) => x"02", (24576 + 602) => x"dc", (24576 + 603) => x"d1", (24576 + 604) => x"a3", (24576 + 605) => x"0e", (24576 + 606) => x"d6", (24576 + 607) => x"71", (24576 + 608) => x"86", (24576 + 609) => x"84", (24576 + 610) => x"87", (24576 + 611) => x"94", (24576 + 612) => x"60", (24576 + 613) => x"3f", (24576 + 614) => x"86", (24576 + 615) => x"02", (24576 + 616) => x"61", (24576 + 617) => x"1f", (24576 + 618) => x"87", (24576 + 619) => x"12", (24576 + 620) => x"47", (24576 + 621) => x"1f", (24576 + 622) => x"12", (24576 + 623) => x"ac", (24576 + 624) => x"46", (24576 + 625) => x"00", (24576 + 626) => x"68", (24576 + 627) => x"01", (24576 + 628) => x"46", (24576 + 629) => x"3f", (24576 + 630) => x"68", (24576 + 631) => x"ff", (24576 + 632) => x"47", (24576 + 633) => x"00", (24576 + 634) => x"69", (24576 + 635) => x"01", (24576 + 636) => x"d6", (24576 + 637) => x"71", (24576 + 638) => x"3f", (24576 + 639) => x"01", (24576 + 640) => x"12", (24576 + 641) => x"aa", (24576 + 642) => x"47", (24576 + 643) => x"1f", (24576 + 644) => x"12", (24576 + 645) => x"aa", (24576 + 646) => x"60", (24576 + 647) => x"05", (24576 + 648) => x"80", (24576 + 649) => x"75", (24576 + 650) => x"3f", (24576 + 651) => x"00", (24576 + 652) => x"12", (24576 + 653) => x"aa", (24576 + 654) => x"60", (24576 + 655) => x"01", (24576 + 656) => x"f0", (24576 + 657) => x"18", (24576 + 658) => x"80", (24576 + 659) => x"60", (24576 + 660) => x"61", (24576 + 661) => x"fc", (24576 + 662) => x"80", (24576 + 663) => x"12", (24576 + 664) => x"a3", (24576 + 665) => x"0c", (24576 + 666) => x"d0", (24576 + 667) => x"71", (24576 + 668) => x"60", (24576 + 669) => x"fe", (24576 + 670) => x"89", (24576 + 671) => x"03", (24576 + 672) => x"22", (24576 + 673) => x"f6", (24576 + 674) => x"75", (24576 + 675) => x"01", (24576 + 676) => x"22", (24576 + 677) => x"f6", (24576 + 678) => x"45", (24576 + 679) => x"60", (24576 + 680) => x"12", (24576 + 681) => x"de", (24576 + 682) => x"12", (24576 + 683) => x"46", (24576 + 684) => x"69", (24576 + 685) => x"ff", (24576 + 686) => x"80", (24576 + 687) => x"60", (24576 + 688) => x"80", (24576 + 689) => x"c5", (24576 + 690) => x"3f", (24576 + 691) => x"01", (24576 + 692) => x"12", (24576 + 693) => x"ca", (24576 + 694) => x"61", (24576 + 695) => x"02", (24576 + 696) => x"80", (24576 + 697) => x"15", (24576 + 698) => x"3f", (24576 + 699) => x"01", (24576 + 700) => x"12", (24576 + 701) => x"e0", (24576 + 702) => x"80", (24576 + 703) => x"15", (24576 + 704) => x"3f", (24576 + 705) => x"01", (24576 + 706) => x"12", (24576 + 707) => x"ee", (24576 + 708) => x"80", (24576 + 709) => x"15", (24576 + 710) => x"3f", (24576 + 711) => x"01", (24576 + 712) => x"12", (24576 + 713) => x"e8", (24576 + 714) => x"60", (24576 + 715) => x"20", (24576 + 716) => x"f0", (24576 + 717) => x"18", (24576 + 718) => x"a3", (24576 + 719) => x"0e", (24576 + 720) => x"7e", (24576 + 721) => x"ff", (24576 + 722) => x"80", (24576 + 723) => x"e0", (24576 + 724) => x"80", (24576 + 725) => x"04", (24576 + 726) => x"61", (24576 + 727) => x"00", (24576 + 728) => x"d0", (24576 + 729) => x"11", (24576 + 730) => x"3e", (24576 + 731) => x"00", (24576 + 732) => x"12", (24576 + 733) => x"30", (24576 + 734) => x"12", (24576 + 735) => x"de", (24576 + 736) => x"78", (24576 + 737) => x"ff", (24576 + 738) => x"48", (24576 + 739) => x"fe", (24576 + 740) => x"68", (24576 + 741) => x"ff", (24576 + 742) => x"12", (24576 + 743) => x"ee", (24576 + 744) => x"78", (24576 + 745) => x"01", (24576 + 746) => x"48", (24576 + 747) => x"02", (24576 + 748) => x"68", (24576 + 749) => x"01", (24576 + 750) => x"60", (24576 + 751) => x"04", (24576 + 752) => x"f0", (24576 + 753) => x"18", (24576 + 754) => x"69", (24576 + 755) => x"ff", (24576 + 756) => x"12", (24576 + 757) => x"70", (24576 + 758) => x"a3", (24576 + 759) => x"14", (24576 + 760) => x"f5", (24576 + 761) => x"33", (24576 + 762) => x"f2", (24576 + 763) => x"65", (24576 + 764) => x"f1", (24576 + 765) => x"29", (24576 + 766) => x"63", (24576 + 767) => x"37", (24576 + 768) => x"64", (24576 + 769) => x"00", (24576 + 770) => x"d3", (24576 + 771) => x"45", (24576 + 772) => x"73", (24576 + 773) => x"05", (24576 + 774) => x"f2", (24576 + 775) => x"29", (24576 + 776) => x"d3", (24576 + 777) => x"45", (24576 + 778) => x"00", (24576 + 779) => x"ee", (24576 + 780) => x"e0", (24576 + 781) => x"00", (24576 + 782) => x"80", (24576 + 783) => x"00", (24576 + 784) => x"fc", (24576 + 785) => x"00", (24576 + 786) => x"aa", (24576 + 787) => x"00", (24576 + 788) => x"00", (24576 + 789) => x"00", (24576 + 790) => x"00", (24576 + 791) => x"00",
-- Cave by 199x
(28672 + 128) => x"00", (28672 + 129) => x"B0",
(28672 + 130) => x"C0", (28672 + 131) => x"E0",
(28672 + 132) => x"F0", (28672 + 133) => x"00",
(28672 + 134) => x"BE", (28672 + 135) => x"0D",
(28672 + 136) => x"00", (28672 + 137) => x"30", -- delay
(28672 + 138) => x"00",
(28672 + 512) => x"00", (28672 + 513) => x"e0", (28672 + 514) => x"64", (28672 + 515) => x"00", (28672 + 516) => x"65", (28672 + 517) => x"00", (28672 + 518) => x"a2", (28672 + 519) => x"0a", (28672 + 520) => x"12", (28672 + 521) => x"0c", (28672 + 522) => x"cc", (28672 + 523) => x"33", (28672 + 524) => x"66", (28672 + 525) => x"1e", (28672 + 526) => x"d4", (28672 + 527) => x"52", (28672 + 528) => x"d4", (28672 + 529) => x"62", (28672 + 530) => x"74", (28672 + 531) => x"08", (28672 + 532) => x"44", (28672 + 533) => x"40", (28672 + 534) => x"12", (28672 + 535) => x"1a", (28672 + 536) => x"12", (28672 + 537) => x"0e", (28672 + 538) => x"a2", (28672 + 539) => x"1e", (28672 + 540) => x"12", (28672 + 541) => x"2c", (28672 + 542) => x"ff", (28672 + 543) => x"ff", (28672 + 544) => x"c0", (28672 + 545) => x"c0", (28672 + 546) => x"c0", (28672 + 547) => x"c0", (28672 + 548) => x"c0", (28672 + 549) => x"c0", (28672 + 550) => x"c0", (28672 + 551) => x"c0", (28672 + 552) => x"c0", (28672 + 553) => x"c0", (28672 + 554) => x"ff", (28672 + 555) => x"ff", (28672 + 556) => x"64", (28672 + 557) => x"0d", (28672 + 558) => x"65", (28672 + 559) => x"09", (28672 + 560) => x"d4", (28672 + 561) => x"5e", (28672 + 562) => x"74", (28672 + 563) => x"0a", (28672 + 564) => x"a2", (28672 + 565) => x"3a", (28672 + 566) => x"d4", (28672 + 567) => x"5e", (28672 + 568) => x"12", (28672 + 569) => x"48", (28672 + 570) => x"ff", (28672 + 571) => x"ff", (28672 + 572) => x"c3", (28672 + 573) => x"c3", (28672 + 574) => x"c3", (28672 + 575) => x"c3", (28672 + 576) => x"c3", (28672 + 577) => x"ff", (28672 + 578) => x"ff", (28672 + 579) => x"c3", (28672 + 580) => x"c3", (28672 + 581) => x"c3", (28672 + 582) => x"c3", (28672 + 583) => x"c3", (28672 + 584) => x"74", (28672 + 585) => x"0a", (28672 + 586) => x"a2", (28672 + 587) => x"50", (28672 + 588) => x"d4", (28672 + 589) => x"5e", (28672 + 590) => x"12", (28672 + 591) => x"5e", (28672 + 592) => x"c3", (28672 + 593) => x"c3", (28672 + 594) => x"c3", (28672 + 595) => x"c3", (28672 + 596) => x"c3", (28672 + 597) => x"66", (28672 + 598) => x"66", (28672 + 599) => x"66", (28672 + 600) => x"66", (28672 + 601) => x"66", (28672 + 602) => x"3c", (28672 + 603) => x"3c", (28672 + 604) => x"18", (28672 + 605) => x"18", (28672 + 606) => x"74", (28672 + 607) => x"0a", (28672 + 608) => x"a2", (28672 + 609) => x"66", (28672 + 610) => x"d4", (28672 + 611) => x"5e", (28672 + 612) => x"12", (28672 + 613) => x"74", (28672 + 614) => x"ff", (28672 + 615) => x"ff", (28672 + 616) => x"c0", (28672 + 617) => x"c0", (28672 + 618) => x"c0", (28672 + 619) => x"c0", (28672 + 620) => x"ff", (28672 + 621) => x"ff", (28672 + 622) => x"c0", (28672 + 623) => x"c0", (28672 + 624) => x"c0", (28672 + 625) => x"c0", (28672 + 626) => x"ff", (28672 + 627) => x"ff", (28672 + 628) => x"6a", (28672 + 629) => x"01", (28672 + 630) => x"6b", (28672 + 631) => x"04", (28672 + 632) => x"6c", (28672 + 633) => x"0e", (28672 + 634) => x"6d", (28672 + 635) => x"00", (28672 + 636) => x"a2", (28672 + 637) => x"81", (28672 + 638) => x"12", (28672 + 639) => x"a6", (28672 + 640) => x"80", (28672 + 641) => x"ff", (28672 + 642) => x"ff", (28672 + 643) => x"ff", (28672 + 644) => x"ff", (28672 + 645) => x"ff", (28672 + 646) => x"ff", (28672 + 647) => x"ff", (28672 + 648) => x"ff", (28672 + 649) => x"ff", (28672 + 650) => x"00", (28672 + 651) => x"e0", (28672 + 652) => x"64", (28672 + 653) => x"00", (28672 + 654) => x"65", (28672 + 655) => x"00", (28672 + 656) => x"d4", (28672 + 657) => x"58", (28672 + 658) => x"74", (28672 + 659) => x"08", (28672 + 660) => x"44", (28672 + 661) => x"40", (28672 + 662) => x"22", (28672 + 663) => x"9e", (28672 + 664) => x"45", (28672 + 665) => x"20", (28672 + 666) => x"12", (28672 + 667) => x"a4", (28672 + 668) => x"12", (28672 + 669) => x"90", (28672 + 670) => x"64", (28672 + 671) => x"00", (28672 + 672) => x"75", (28672 + 673) => x"08", (28672 + 674) => x"00", (28672 + 675) => x"ee", (28672 + 676) => x"12", (28672 + 677) => x"ae", (28672 + 678) => x"60", (28672 + 679) => x"0f", (28672 + 680) => x"e0", (28672 + 681) => x"9e", (28672 + 682) => x"12", (28672 + 683) => x"a8", (28672 + 684) => x"12", (28672 + 685) => x"8a", (28672 + 686) => x"4a", (28672 + 687) => x"01", (28672 + 688) => x"22", (28672 + 689) => x"d0", (28672 + 690) => x"4a", (28672 + 691) => x"02", (28672 + 692) => x"23", (28672 + 693) => x"8a", (28672 + 694) => x"4a", (28672 + 695) => x"03", (28672 + 696) => x"23", (28672 + 697) => x"b8", (28672 + 698) => x"4a", (28672 + 699) => x"04", (28672 + 700) => x"23", (28672 + 701) => x"e0", (28672 + 702) => x"4a", (28672 + 703) => x"05", (28672 + 704) => x"24", (28672 + 705) => x"18", (28672 + 706) => x"4a", (28672 + 707) => x"06", (28672 + 708) => x"24", (28672 + 709) => x"78", (28672 + 710) => x"4a", (28672 + 711) => x"07", (28672 + 712) => x"24", (28672 + 713) => x"e6", (28672 + 714) => x"4a", (28672 + 715) => x"08", (28672 + 716) => x"25", (28672 + 717) => x"10", (28672 + 718) => x"13", (28672 + 719) => x"18", (28672 + 720) => x"a2", (28672 + 721) => x"81", (28672 + 722) => x"64", (28672 + 723) => x"02", (28672 + 724) => x"65", (28672 + 725) => x"02", (28672 + 726) => x"d4", (28672 + 727) => x"58", (28672 + 728) => x"65", (28672 + 729) => x"0a", (28672 + 730) => x"d4", (28672 + 731) => x"58", (28672 + 732) => x"65", (28672 + 733) => x"12", (28672 + 734) => x"d4", (28672 + 735) => x"58", (28672 + 736) => x"64", (28672 + 737) => x"0a", (28672 + 738) => x"65", (28672 + 739) => x"05", (28672 + 740) => x"d4", (28672 + 741) => x"53", (28672 + 742) => x"64", (28672 + 743) => x"12", (28672 + 744) => x"d4", (28672 + 745) => x"53", (28672 + 746) => x"64", (28672 + 747) => x"1a", (28672 + 748) => x"d4", (28672 + 749) => x"53", (28672 + 750) => x"64", (28672 + 751) => x"22", (28672 + 752) => x"d4", (28672 + 753) => x"53", (28672 + 754) => x"64", (28672 + 755) => x"2a", (28672 + 756) => x"d4", (28672 + 757) => x"53", (28672 + 758) => x"64", (28672 + 759) => x"32", (28672 + 760) => x"d4", (28672 + 761) => x"53", (28672 + 762) => x"a2", (28672 + 763) => x"fe", (28672 + 764) => x"13", (28672 + 765) => x"0a", (28672 + 766) => x"fc", (28672 + 767) => x"fc", (28672 + 768) => x"fc", (28672 + 769) => x"fc", (28672 + 770) => x"fc", (28672 + 771) => x"fc", (28672 + 772) => x"fc", (28672 + 773) => x"fc", (28672 + 774) => x"fc", (28672 + 775) => x"fc", (28672 + 776) => x"fc", (28672 + 777) => x"fc", (28672 + 778) => x"75", (28672 + 779) => x"03", (28672 + 780) => x"74", (28672 + 781) => x"02", (28672 + 782) => x"d4", (28672 + 783) => x"5c", (28672 + 784) => x"74", (28672 + 785) => x"06", (28672 + 786) => x"75", (28672 + 787) => x"09", (28672 + 788) => x"d4", (28672 + 789) => x"53", (28672 + 790) => x"00", (28672 + 791) => x"ee", (28672 + 792) => x"a2", (28672 + 793) => x"80", (28672 + 794) => x"db", (28672 + 795) => x"c1", (28672 + 796) => x"4f", (28672 + 797) => x"01", (28672 + 798) => x"13", (28672 + 799) => x"72", (28672 + 800) => x"60", (28672 + 801) => x"02", (28672 + 802) => x"e0", (28672 + 803) => x"a1", (28672 + 804) => x"6d", (28672 + 805) => x"02", (28672 + 806) => x"60", (28672 + 807) => x"04", (28672 + 808) => x"e0", (28672 + 809) => x"a1", (28672 + 810) => x"6d", (28672 + 811) => x"04", (28672 + 812) => x"60", (28672 + 813) => x"06", (28672 + 814) => x"e0", (28672 + 815) => x"a1", (28672 + 816) => x"6d", (28672 + 817) => x"06", (28672 + 818) => x"60", (28672 + 819) => x"08", (28672 + 820) => x"e0", (28672 + 821) => x"a1", (28672 + 822) => x"6d", (28672 + 823) => x"08", (28672 + 824) => x"db", (28672 + 825) => x"c1", (28672 + 826) => x"4d", (28672 + 827) => x"02", (28672 + 828) => x"7c", (28672 + 829) => x"ff", (28672 + 830) => x"4d", (28672 + 831) => x"04", (28672 + 832) => x"7b", (28672 + 833) => x"ff", (28672 + 834) => x"4d", (28672 + 835) => x"06", (28672 + 836) => x"7b", (28672 + 837) => x"01", (28672 + 838) => x"4d", (28672 + 839) => x"08", (28672 + 840) => x"7c", (28672 + 841) => x"01", (28672 + 842) => x"4b", (28672 + 843) => x"40", (28672 + 844) => x"13", (28672 + 845) => x"5e", (28672 + 846) => x"4b", (28672 + 847) => x"ff", (28672 + 848) => x"13", (28672 + 849) => x"64", (28672 + 850) => x"60", (28672 + 851) => x"02", (28672 + 852) => x"f0", (28672 + 853) => x"15", (28672 + 854) => x"f0", (28672 + 855) => x"07", (28672 + 856) => x"30", (28672 + 857) => x"00", (28672 + 858) => x"13", (28672 + 859) => x"56", (28672 + 860) => x"13", (28672 + 861) => x"18", (28672 + 862) => x"7a", (28672 + 863) => x"01", (28672 + 864) => x"4a", (28672 + 865) => x"09", (28672 + 866) => x"15", (28672 + 867) => x"3a", (28672 + 868) => x"6b", (28672 + 869) => x"01", (28672 + 870) => x"a2", (28672 + 871) => x"81", (28672 + 872) => x"12", (28672 + 873) => x"8a", (28672 + 874) => x"7a", (28672 + 875) => x"ff", (28672 + 876) => x"6b", (28672 + 877) => x"3e", (28672 + 878) => x"a2", (28672 + 879) => x"81", (28672 + 880) => x"12", (28672 + 881) => x"8a", (28672 + 882) => x"60", (28672 + 883) => x"03", (28672 + 884) => x"f0", (28672 + 885) => x"18", (28672 + 886) => x"60", (28672 + 887) => x"0f", (28672 + 888) => x"e0", (28672 + 889) => x"9e", (28672 + 890) => x"13", (28672 + 891) => x"78", (28672 + 892) => x"6a", (28672 + 893) => x"01", (28672 + 894) => x"6b", (28672 + 895) => x"04", (28672 + 896) => x"6c", (28672 + 897) => x"0e", (28672 + 898) => x"6d", (28672 + 899) => x"00", (28672 + 900) => x"a2", (28672 + 901) => x"81", (28672 + 902) => x"00", (28672 + 903) => x"e0", (28672 + 904) => x"12", (28672 + 905) => x"8a", (28672 + 906) => x"64", (28672 + 907) => x"00", (28672 + 908) => x"65", (28672 + 909) => x"11", (28672 + 910) => x"a2", (28672 + 911) => x"81", (28672 + 912) => x"d4", (28672 + 913) => x"53", (28672 + 914) => x"74", (28672 + 915) => x"08", (28672 + 916) => x"d4", (28672 + 917) => x"53", (28672 + 918) => x"74", (28672 + 919) => x"08", (28672 + 920) => x"75", (28672 + 921) => x"ff", (28672 + 922) => x"d4", (28672 + 923) => x"53", (28672 + 924) => x"74", (28672 + 925) => x"08", (28672 + 926) => x"75", (28672 + 927) => x"ff", (28672 + 928) => x"d4", (28672 + 929) => x"53", (28672 + 930) => x"74", (28672 + 931) => x"08", (28672 + 932) => x"d4", (28672 + 933) => x"53", (28672 + 934) => x"74", (28672 + 935) => x"08", (28672 + 936) => x"d4", (28672 + 937) => x"53", (28672 + 938) => x"74", (28672 + 939) => x"08", (28672 + 940) => x"75", (28672 + 941) => x"01", (28672 + 942) => x"d4", (28672 + 943) => x"53", (28672 + 944) => x"74", (28672 + 945) => x"08", (28672 + 946) => x"75", (28672 + 947) => x"01", (28672 + 948) => x"d4", (28672 + 949) => x"53", (28672 + 950) => x"00", (28672 + 951) => x"ee", (28672 + 952) => x"64", (28672 + 953) => x"00", (28672 + 954) => x"65", (28672 + 955) => x"11", (28672 + 956) => x"a2", (28672 + 957) => x"81", (28672 + 958) => x"d4", (28672 + 959) => x"53", (28672 + 960) => x"74", (28672 + 961) => x"08", (28672 + 962) => x"d4", (28672 + 963) => x"53", (28672 + 964) => x"74", (28672 + 965) => x"08", (28672 + 966) => x"75", (28672 + 967) => x"02", (28672 + 968) => x"d4", (28672 + 969) => x"52", (28672 + 970) => x"74", (28672 + 971) => x"08", (28672 + 972) => x"d4", (28672 + 973) => x"51", (28672 + 974) => x"74", (28672 + 975) => x"08", (28672 + 976) => x"d4", (28672 + 977) => x"51", (28672 + 978) => x"74", (28672 + 979) => x"08", (28672 + 980) => x"d4", (28672 + 981) => x"51", (28672 + 982) => x"74", (28672 + 983) => x"08", (28672 + 984) => x"d4", (28672 + 985) => x"51", (28672 + 986) => x"74", (28672 + 987) => x"08", (28672 + 988) => x"d4", (28672 + 989) => x"51", (28672 + 990) => x"00", (28672 + 991) => x"ee", (28672 + 992) => x"64", (28672 + 993) => x"00", (28672 + 994) => x"65", (28672 + 995) => x"13", (28672 + 996) => x"a2", (28672 + 997) => x"81", (28672 + 998) => x"d4", (28672 + 999) => x"51", (28672 + 1000) => x"a2", (28672 + 1001) => x"80", (28672 + 1002) => x"74", (28672 + 1003) => x"08", (28672 + 1004) => x"d4", (28672 + 1005) => x"51", (28672 + 1006) => x"75", (28672 + 1007) => x"01", (28672 + 1008) => x"d4", (28672 + 1009) => x"51", (28672 + 1010) => x"75", (28672 + 1011) => x"01", (28672 + 1012) => x"a2", (28672 + 1013) => x"81", (28672 + 1014) => x"d4", (28672 + 1015) => x"51", (28672 + 1016) => x"74", (28672 + 1017) => x"08", (28672 + 1018) => x"d4", (28672 + 1019) => x"51", (28672 + 1020) => x"74", (28672 + 1021) => x"08", (28672 + 1022) => x"d4", (28672 + 1023) => x"52", (28672 + 1024) => x"74", (28672 + 1025) => x"08", (28672 + 1026) => x"75", (28672 + 1027) => x"ff", (28672 + 1028) => x"d4", (28672 + 1029) => x"53", (28672 + 1030) => x"74", (28672 + 1031) => x"08", (28672 + 1032) => x"d4", (28672 + 1033) => x"54", (28672 + 1034) => x"74", (28672 + 1035) => x"08", (28672 + 1036) => x"75", (28672 + 1037) => x"ff", (28672 + 1038) => x"d4", (28672 + 1039) => x"56", (28672 + 1040) => x"74", (28672 + 1041) => x"08", (28672 + 1042) => x"75", (28672 + 1043) => x"ff", (28672 + 1044) => x"d4", (28672 + 1045) => x"58", (28672 + 1046) => x"00", (28672 + 1047) => x"ee", (28672 + 1048) => x"64", (28672 + 1049) => x"00", (28672 + 1050) => x"65", (28672 + 1051) => x"12", (28672 + 1052) => x"a2", (28672 + 1053) => x"81", (28672 + 1054) => x"d4", (28672 + 1055) => x"58", (28672 + 1056) => x"74", (28672 + 1057) => x"08", (28672 + 1058) => x"d4", (28672 + 1059) => x"58", (28672 + 1060) => x"74", (28672 + 1061) => x"08", (28672 + 1062) => x"d4", (28672 + 1063) => x"58", (28672 + 1064) => x"74", (28672 + 1065) => x"08", (28672 + 1066) => x"d4", (28672 + 1067) => x"58", (28672 + 1068) => x"74", (28672 + 1069) => x"08", (28672 + 1070) => x"d4", (28672 + 1071) => x"58", (28672 + 1072) => x"74", (28672 + 1073) => x"08", (28672 + 1074) => x"d4", (28672 + 1075) => x"58", (28672 + 1076) => x"74", (28672 + 1077) => x"08", (28672 + 1078) => x"d4", (28672 + 1079) => x"58", (28672 + 1080) => x"a2", (28672 + 1081) => x"80", (28672 + 1082) => x"75", (28672 + 1083) => x"ff", (28672 + 1084) => x"74", (28672 + 1085) => x"20", (28672 + 1086) => x"d4", (28672 + 1087) => x"51", (28672 + 1088) => x"75", (28672 + 1089) => x"ff", (28672 + 1090) => x"d4", (28672 + 1091) => x"51", (28672 + 1092) => x"75", (28672 + 1093) => x"ff", (28672 + 1094) => x"d4", (28672 + 1095) => x"51", (28672 + 1096) => x"75", (28672 + 1097) => x"ff", (28672 + 1098) => x"d4", (28672 + 1099) => x"51", (28672 + 1100) => x"75", (28672 + 1101) => x"ff", (28672 + 1102) => x"d4", (28672 + 1103) => x"51", (28672 + 1104) => x"75", (28672 + 1105) => x"ff", (28672 + 1106) => x"d4", (28672 + 1107) => x"51", (28672 + 1108) => x"75", (28672 + 1109) => x"ff", (28672 + 1110) => x"d4", (28672 + 1111) => x"51", (28672 + 1112) => x"75", (28672 + 1113) => x"ff", (28672 + 1114) => x"d4", (28672 + 1115) => x"51", (28672 + 1116) => x"75", (28672 + 1117) => x"ff", (28672 + 1118) => x"a2", (28672 + 1119) => x"81", (28672 + 1120) => x"d4", (28672 + 1121) => x"51", (28672 + 1122) => x"74", (28672 + 1123) => x"08", (28672 + 1124) => x"d4", (28672 + 1125) => x"51", (28672 + 1126) => x"74", (28672 + 1127) => x"08", (28672 + 1128) => x"d4", (28672 + 1129) => x"51", (28672 + 1130) => x"74", (28672 + 1131) => x"08", (28672 + 1132) => x"d4", (28672 + 1133) => x"51", (28672 + 1134) => x"74", (28672 + 1135) => x"08", (28672 + 1136) => x"d4", (28672 + 1137) => x"51", (28672 + 1138) => x"74", (28672 + 1139) => x"08", (28672 + 1140) => x"d4", (28672 + 1141) => x"51", (28672 + 1142) => x"00", (28672 + 1143) => x"ee", (28672 + 1144) => x"64", (28672 + 1145) => x"00", (28672 + 1146) => x"65", (28672 + 1147) => x"09", (28672 + 1148) => x"a2", (28672 + 1149) => x"81", (28672 + 1150) => x"d4", (28672 + 1151) => x"51", (28672 + 1152) => x"74", (28672 + 1153) => x"08", (28672 + 1154) => x"d4", (28672 + 1155) => x"51", (28672 + 1156) => x"74", (28672 + 1157) => x"08", (28672 + 1158) => x"d4", (28672 + 1159) => x"51", (28672 + 1160) => x"74", (28672 + 1161) => x"08", (28672 + 1162) => x"d4", (28672 + 1163) => x"51", (28672 + 1164) => x"74", (28672 + 1165) => x"08", (28672 + 1166) => x"d4", (28672 + 1167) => x"51", (28672 + 1168) => x"74", (28672 + 1169) => x"08", (28672 + 1170) => x"d4", (28672 + 1171) => x"51", (28672 + 1172) => x"a2", (28672 + 1173) => x"80", (28672 + 1174) => x"75", (28672 + 1175) => x"01", (28672 + 1176) => x"d4", (28672 + 1177) => x"51", (28672 + 1178) => x"75", (28672 + 1179) => x"01", (28672 + 1180) => x"d4", (28672 + 1181) => x"51", (28672 + 1182) => x"75", (28672 + 1183) => x"01", (28672 + 1184) => x"d4", (28672 + 1185) => x"51", (28672 + 1186) => x"75", (28672 + 1187) => x"01", (28672 + 1188) => x"d4", (28672 + 1189) => x"51", (28672 + 1190) => x"75", (28672 + 1191) => x"01", (28672 + 1192) => x"d4", (28672 + 1193) => x"51", (28672 + 1194) => x"75", (28672 + 1195) => x"01", (28672 + 1196) => x"d4", (28672 + 1197) => x"51", (28672 + 1198) => x"75", (28672 + 1199) => x"01", (28672 + 1200) => x"d4", (28672 + 1201) => x"51", (28672 + 1202) => x"75", (28672 + 1203) => x"01", (28672 + 1204) => x"d4", (28672 + 1205) => x"51", (28672 + 1206) => x"75", (28672 + 1207) => x"01", (28672 + 1208) => x"a2", (28672 + 1209) => x"81", (28672 + 1210) => x"d4", (28672 + 1211) => x"51", (28672 + 1212) => x"74", (28672 + 1213) => x"08", (28672 + 1214) => x"d4", (28672 + 1215) => x"51", (28672 + 1216) => x"74", (28672 + 1217) => x"08", (28672 + 1218) => x"d4", (28672 + 1219) => x"51", (28672 + 1220) => x"00", (28672 + 1221) => x"ee", (28672 + 1222) => x"64", (28672 + 1223) => x"00", (28672 + 1224) => x"65", (28672 + 1225) => x"1a", (28672 + 1226) => x"a2", (28672 + 1227) => x"81", (28672 + 1228) => x"d4", (28672 + 1229) => x"51", (28672 + 1230) => x"74", (28672 + 1231) => x"08", (28672 + 1232) => x"d4", (28672 + 1233) => x"51", (28672 + 1234) => x"74", (28672 + 1235) => x"08", (28672 + 1236) => x"d4", (28672 + 1237) => x"51", (28672 + 1238) => x"74", (28672 + 1239) => x"08", (28672 + 1240) => x"d4", (28672 + 1241) => x"51", (28672 + 1242) => x"74", (28672 + 1243) => x"08", (28672 + 1244) => x"d4", (28672 + 1245) => x"51", (28672 + 1246) => x"75", (28672 + 1247) => x"ff", (28672 + 1248) => x"d4", (28672 + 1249) => x"51", (28672 + 1250) => x"74", (28672 + 1251) => x"08", (28672 + 1252) => x"d4", (28672 + 1253) => x"51", (28672 + 1254) => x"74", (28672 + 1255) => x"08", (28672 + 1256) => x"d4", (28672 + 1257) => x"51", (28672 + 1258) => x"74", (28672 + 1259) => x"08", (28672 + 1260) => x"d4", (28672 + 1261) => x"51", (28672 + 1262) => x"00", (28672 + 1263) => x"ee", (28672 + 1264) => x"64", (28672 + 1265) => x"00", (28672 + 1266) => x"65", (28672 + 1267) => x"19", (28672 + 1268) => x"a2", (28672 + 1269) => x"81", (28672 + 1270) => x"d4", (28672 + 1271) => x"51", (28672 + 1272) => x"74", (28672 + 1273) => x"08", (28672 + 1274) => x"d4", (28672 + 1275) => x"51", (28672 + 1276) => x"74", (28672 + 1277) => x"08", (28672 + 1278) => x"d4", (28672 + 1279) => x"51", (28672 + 1280) => x"74", (28672 + 1281) => x"08", (28672 + 1282) => x"d4", (28672 + 1283) => x"51", (28672 + 1284) => x"74", (28672 + 1285) => x"08", (28672 + 1286) => x"d4", (28672 + 1287) => x"51", (28672 + 1288) => x"75", (28672 + 1289) => x"ff", (28672 + 1290) => x"d4", (28672 + 1291) => x"51", (28672 + 1292) => x"74", (28672 + 1293) => x"08", (28672 + 1294) => x"d4", (28672 + 1295) => x"51", (28672 + 1296) => x"74", (28672 + 1297) => x"08", (28672 + 1298) => x"d4", (28672 + 1299) => x"51", (28672 + 1300) => x"74", (28672 + 1301) => x"08", (28672 + 1302) => x"d4", (28672 + 1303) => x"51", (28672 + 1304) => x"00", (28672 + 1305) => x"ee", (28672 + 1306) => x"00", (28672 + 1307) => x"e0", (28672 + 1308) => x"67", (28672 + 1309) => x"03", (28672 + 1310) => x"68", (28672 + 1311) => x"03", (28672 + 1312) => x"a5", (28672 + 1313) => x"44", (28672 + 1314) => x"15", (28672 + 1315) => x"5c", (28672 + 1316) => x"ae", (28672 + 1317) => x"aa", (28672 + 1318) => x"ea", (28672 + 1319) => x"4a", (28672 + 1320) => x"4e", (28672 + 1321) => x"00", (28672 + 1322) => x"a4", (28672 + 1323) => x"a4", (28672 + 1324) => x"a4", (28672 + 1325) => x"a5", (28672 + 1326) => x"e2", (28672 + 1327) => x"00", (28672 + 1328) => x"5d", (28672 + 1329) => x"55", (28672 + 1330) => x"55", (28672 + 1331) => x"55", (28672 + 1332) => x"9d", (28672 + 1333) => x"00", (28672 + 1334) => x"c8", (28672 + 1335) => x"48", (28672 + 1336) => x"48", (28672 + 1337) => x"40", (28672 + 1338) => x"48", (28672 + 1339) => x"00", (28672 + 1340) => x"d7", (28672 + 1341) => x"85", (28672 + 1342) => x"a5", (28672 + 1343) => x"4a", (28672 + 1344) => x"77", (28672 + 1345) => x"08", (28672 + 1346) => x"d7", (28672 + 1347) => x"85", (28672 + 1348) => x"77", (28672 + 1349) => x"08", (28672 + 1350) => x"a5", (28672 + 1351) => x"50", (28672 + 1352) => x"d7", (28672 + 1353) => x"85", (28672 + 1354) => x"77", (28672 + 1355) => x"08", (28672 + 1356) => x"a5", (28672 + 1357) => x"56", (28672 + 1358) => x"d7", (28672 + 1359) => x"85", (28672 + 1360) => x"15", (28672 + 1361) => x"70",
-- Hidden by David Winter
(32768 + 128) => x"00", (32768 + 129) => x"B0",
(32768 + 130) => x"CD", (32768 + 131) => x"E0",
(32768 + 132) => x"F0", (32768 + 133) => x"00",
(32768 + 134) => x"BE", (32768 + 135) => x"00",
(32768 + 136) => x"00", (32768 + 137) => x"60", -- delay
(32768 + 138) => x"00",
(32768 + 512) => x"12", (32768 + 513) => x"1d", (32768 + 514) => x"48", (32768 + 515) => x"49", (32768 + 516) => x"44", (32768 + 517) => x"44", (32768 + 518) => x"45", (32768 + 519) => x"4e", (32768 + 520) => x"21", (32768 + 521) => x"20", (32768 + 522) => x"31", (32768 + 523) => x"2e", (32768 + 524) => x"30", (32768 + 525) => x"20", (32768 + 526) => x"42", (32768 + 527) => x"79", (32768 + 528) => x"20", (32768 + 529) => x"44", (32768 + 530) => x"61", (32768 + 531) => x"76", (32768 + 532) => x"69", (32768 + 533) => x"64", (32768 + 534) => x"20", (32768 + 535) => x"57", (32768 + 536) => x"49", (32768 + 537) => x"4e", (32768 + 538) => x"54", (32768 + 539) => x"45", (32768 + 540) => x"52", (32768 + 541) => x"a4", (32768 + 542) => x"3f", (32768 + 543) => x"60", (32768 + 544) => x"00", (32768 + 545) => x"61", (32768 + 546) => x"40", (32768 + 547) => x"f1", (32768 + 548) => x"55", (32768 + 549) => x"a4", (32768 + 550) => x"3f", (32768 + 551) => x"60", (32768 + 552) => x"00", (32768 + 553) => x"f0", (32768 + 554) => x"55", (32768 + 555) => x"00", (32768 + 556) => x"e0", (32768 + 557) => x"a4", (32768 + 558) => x"7e", (32768 + 559) => x"60", (32768 + 560) => x"0c", (32768 + 561) => x"61", (32768 + 562) => x"08", (32768 + 563) => x"62", (32768 + 564) => x"0f", (32768 + 565) => x"d0", (32768 + 566) => x"1f", (32768 + 567) => x"70", (32768 + 568) => x"08", (32768 + 569) => x"f2", (32768 + 570) => x"1e", (32768 + 571) => x"30", (32768 + 572) => x"34", (32768 + 573) => x"12", (32768 + 574) => x"35", (32768 + 575) => x"f0", (32768 + 576) => x"0a", (32768 + 577) => x"00", (32768 + 578) => x"e0", (32768 + 579) => x"a4", (32768 + 580) => x"c9", (32768 + 581) => x"60", (32768 + 582) => x"13", (32768 + 583) => x"61", (32768 + 584) => x"0d", (32768 + 585) => x"62", (32768 + 586) => x"04", (32768 + 587) => x"d0", (32768 + 588) => x"14", (32768 + 589) => x"70", (32768 + 590) => x"08", (32768 + 591) => x"f2", (32768 + 592) => x"1e", (32768 + 593) => x"30", (32768 + 594) => x"2b", (32768 + 595) => x"12", (32768 + 596) => x"4b", (32768 + 597) => x"a4", (32768 + 598) => x"1f", (32768 + 599) => x"ff", (32768 + 600) => x"65", (32768 + 601) => x"a4", (32768 + 602) => x"2f", (32768 + 603) => x"ff", (32768 + 604) => x"55", (32768 + 605) => x"63", (32768 + 606) => x"40", (32768 + 607) => x"66", (32768 + 608) => x"08", (32768 + 609) => x"c1", (32768 + 610) => x"0f", (32768 + 611) => x"c2", (32768 + 612) => x"0f", (32768 + 613) => x"a4", (32768 + 614) => x"2f", (32768 + 615) => x"f1", (32768 + 616) => x"1e", (32768 + 617) => x"f0", (32768 + 618) => x"65", (32768 + 619) => x"84", (32768 + 620) => x"00", (32768 + 621) => x"a4", (32768 + 622) => x"2f", (32768 + 623) => x"f2", (32768 + 624) => x"1e", (32768 + 625) => x"f0", (32768 + 626) => x"65", (32768 + 627) => x"85", (32768 + 628) => x"00", (32768 + 629) => x"80", (32768 + 630) => x"40", (32768 + 631) => x"f0", (32768 + 632) => x"55", (32768 + 633) => x"a4", (32768 + 634) => x"2f", (32768 + 635) => x"f1", (32768 + 636) => x"1e", (32768 + 637) => x"80", (32768 + 638) => x"50", (32768 + 639) => x"f0", (32768 + 640) => x"55", (32768 + 641) => x"73", (32768 + 642) => x"ff", (32768 + 643) => x"33", (32768 + 644) => x"00", (32768 + 645) => x"12", (32768 + 646) => x"61", (32768 + 647) => x"00", (32768 + 648) => x"e0", (32768 + 649) => x"60", (32768 + 650) => x"00", (32768 + 651) => x"61", (32768 + 652) => x"00", (32768 + 653) => x"a4", (32768 + 654) => x"77", (32768 + 655) => x"d0", (32768 + 656) => x"17", (32768 + 657) => x"70", (32768 + 658) => x"08", (32768 + 659) => x"30", (32768 + 660) => x"20", (32768 + 661) => x"12", (32768 + 662) => x"8f", (32768 + 663) => x"60", (32768 + 664) => x"00", (32768 + 665) => x"71", (32768 + 666) => x"08", (32768 + 667) => x"31", (32768 + 668) => x"20", (32768 + 669) => x"12", (32768 + 670) => x"8f", (32768 + 671) => x"6c", (32768 + 672) => x"00", (32768 + 673) => x"6d", (32768 + 674) => x"00", (32768 + 675) => x"6e", (32768 + 676) => x"00", (32768 + 677) => x"a4", (32768 + 678) => x"3f", (32768 + 679) => x"f0", (32768 + 680) => x"65", (32768 + 681) => x"70", (32768 + 682) => x"01", (32768 + 683) => x"f0", (32768 + 684) => x"55", (32768 + 685) => x"23", (32768 + 686) => x"b9", (32768 + 687) => x"6a", (32768 + 688) => x"10", (32768 + 689) => x"23", (32768 + 690) => x"5d", (32768 + 691) => x"23", (32768 + 692) => x"cd", (32768 + 693) => x"8a", (32768 + 694) => x"90", (32768 + 695) => x"87", (32768 + 696) => x"d0", (32768 + 697) => x"88", (32768 + 698) => x"e0", (32768 + 699) => x"23", (32768 + 700) => x"5d", (32768 + 701) => x"23", (32768 + 702) => x"cd", (32768 + 703) => x"23", (32768 + 704) => x"b9", (32768 + 705) => x"a4", (32768 + 706) => x"2f", (32768 + 707) => x"f9", (32768 + 708) => x"1e", (32768 + 709) => x"f0", (32768 + 710) => x"65", (32768 + 711) => x"81", (32768 + 712) => x"00", (32768 + 713) => x"a4", (32768 + 714) => x"2f", (32768 + 715) => x"fa", (32768 + 716) => x"1e", (32768 + 717) => x"f0", (32768 + 718) => x"65", (32768 + 719) => x"50", (32768 + 720) => x"10", (32768 + 721) => x"13", (32768 + 722) => x"2b", (32768 + 723) => x"23", (32768 + 724) => x"df", (32768 + 725) => x"60", (32768 + 726) => x"20", (32768 + 727) => x"24", (32768 + 728) => x"01", (32768 + 729) => x"23", (32768 + 730) => x"df", (32768 + 731) => x"60", (32768 + 732) => x"00", (32768 + 733) => x"a4", (32768 + 734) => x"2f", (32768 + 735) => x"f9", (32768 + 736) => x"1e", (32768 + 737) => x"f0", (32768 + 738) => x"55", (32768 + 739) => x"a4", (32768 + 740) => x"2f", (32768 + 741) => x"fa", (32768 + 742) => x"1e", (32768 + 743) => x"f0", (32768 + 744) => x"55", (32768 + 745) => x"76", (32768 + 746) => x"ff", (32768 + 747) => x"36", (32768 + 748) => x"00", (32768 + 749) => x"12", (32768 + 750) => x"a5", (32768 + 751) => x"a4", (32768 + 752) => x"3f", (32768 + 753) => x"f1", (32768 + 754) => x"65", (32768 + 755) => x"82", (32768 + 756) => x"00", (32768 + 757) => x"80", (32768 + 758) => x"15", (32768 + 759) => x"3f", (32768 + 760) => x"00", (32768 + 761) => x"13", (32768 + 762) => x"01", (32768 + 763) => x"80", (32768 + 764) => x"20", (32768 + 765) => x"81", (32768 + 766) => x"20", (32768 + 767) => x"f1", (32768 + 768) => x"55", (32768 + 769) => x"00", (32768 + 770) => x"e0", (32768 + 771) => x"a5", (32768 + 772) => x"19", (32768 + 773) => x"60", (32768 + 774) => x"10", (32768 + 775) => x"61", (32768 + 776) => x"07", (32768 + 777) => x"62", (32768 + 778) => x"0e", (32768 + 779) => x"d0", (32768 + 780) => x"1f", (32768 + 781) => x"70", (32768 + 782) => x"08", (32768 + 783) => x"f2", (32768 + 784) => x"1e", (32768 + 785) => x"30", (32768 + 786) => x"30", (32768 + 787) => x"13", (32768 + 788) => x"0b", (32768 + 789) => x"a4", (32768 + 790) => x"3f", (32768 + 791) => x"f1", (32768 + 792) => x"65", (32768 + 793) => x"84", (32768 + 794) => x"10", (32768 + 795) => x"83", (32768 + 796) => x"00", (32768 + 797) => x"66", (32768 + 798) => x"09", (32768 + 799) => x"24", (32768 + 800) => x"0b", (32768 + 801) => x"66", (32768 + 802) => x"0f", (32768 + 803) => x"83", (32768 + 804) => x"40", (32768 + 805) => x"24", (32768 + 806) => x"0b", (32768 + 807) => x"f0", (32768 + 808) => x"0a", (32768 + 809) => x"12", (32768 + 810) => x"25", (32768 + 811) => x"23", (32768 + 812) => x"db", (32768 + 813) => x"60", (32768 + 814) => x"80", (32768 + 815) => x"24", (32768 + 816) => x"01", (32768 + 817) => x"23", (32768 + 818) => x"db", (32768 + 819) => x"a4", (32768 + 820) => x"2f", (32768 + 821) => x"fa", (32768 + 822) => x"1e", (32768 + 823) => x"f0", (32768 + 824) => x"65", (32768 + 825) => x"70", (32768 + 826) => x"ff", (32768 + 827) => x"23", (32768 + 828) => x"f3", (32768 + 829) => x"a4", (32768 + 830) => x"41", (32768 + 831) => x"f0", (32768 + 832) => x"1e", (32768 + 833) => x"d7", (32768 + 834) => x"87", (32768 + 835) => x"a4", (32768 + 836) => x"77", (32768 + 837) => x"d7", (32768 + 838) => x"87", (32768 + 839) => x"a4", (32768 + 840) => x"2f", (32768 + 841) => x"f9", (32768 + 842) => x"1e", (32768 + 843) => x"f0", (32768 + 844) => x"65", (32768 + 845) => x"70", (32768 + 846) => x"ff", (32768 + 847) => x"23", (32768 + 848) => x"f3", (32768 + 849) => x"a4", (32768 + 850) => x"41", (32768 + 851) => x"f0", (32768 + 852) => x"1e", (32768 + 853) => x"dd", (32768 + 854) => x"e7", (32768 + 855) => x"a4", (32768 + 856) => x"77", (32768 + 857) => x"dd", (32768 + 858) => x"e7", (32768 + 859) => x"12", (32768 + 860) => x"a5", (32768 + 861) => x"a4", (32768 + 862) => x"71", (32768 + 863) => x"dd", (32768 + 864) => x"e7", (32768 + 865) => x"fb", (32768 + 866) => x"0a", (32768 + 867) => x"dd", (32768 + 868) => x"e7", (32768 + 869) => x"3b", (32768 + 870) => x"04", (32768 + 871) => x"13", (32768 + 872) => x"71", (32768 + 873) => x"4d", (32768 + 874) => x"00", (32768 + 875) => x"13", (32768 + 876) => x"5d", (32768 + 877) => x"7d", (32768 + 878) => x"f8", (32768 + 879) => x"7c", (32768 + 880) => x"ff", (32768 + 881) => x"3b", (32768 + 882) => x"06", (32768 + 883) => x"13", (32768 + 884) => x"7d", (32768 + 885) => x"4d", (32768 + 886) => x"18", (32768 + 887) => x"13", (32768 + 888) => x"5d", (32768 + 889) => x"7d", (32768 + 890) => x"08", (32768 + 891) => x"7c", (32768 + 892) => x"01", (32768 + 893) => x"3b", (32768 + 894) => x"02", (32768 + 895) => x"13", (32768 + 896) => x"89", (32768 + 897) => x"4e", (32768 + 898) => x"00", (32768 + 899) => x"13", (32768 + 900) => x"5d", (32768 + 901) => x"7e", (32768 + 902) => x"f8", (32768 + 903) => x"7c", (32768 + 904) => x"fc", (32768 + 905) => x"3b", (32768 + 906) => x"08", (32768 + 907) => x"13", (32768 + 908) => x"95", (32768 + 909) => x"4e", (32768 + 910) => x"18", (32768 + 911) => x"13", (32768 + 912) => x"5d", (32768 + 913) => x"7e", (32768 + 914) => x"08", (32768 + 915) => x"7c", (32768 + 916) => x"04", (32768 + 917) => x"3b", (32768 + 918) => x"05", (32768 + 919) => x"13", (32768 + 920) => x"5d", (32768 + 921) => x"a4", (32768 + 922) => x"2f", (32768 + 923) => x"fc", (32768 + 924) => x"1e", (32768 + 925) => x"f0", (32768 + 926) => x"65", (32768 + 927) => x"40", (32768 + 928) => x"00", (32768 + 929) => x"13", (32768 + 930) => x"5d", (32768 + 931) => x"89", (32768 + 932) => x"c0", (32768 + 933) => x"99", (32768 + 934) => x"a0", (32768 + 935) => x"13", (32768 + 936) => x"5d", (32768 + 937) => x"70", (32768 + 938) => x"ff", (32768 + 939) => x"a4", (32768 + 940) => x"77", (32768 + 941) => x"dd", (32768 + 942) => x"e7", (32768 + 943) => x"a4", (32768 + 944) => x"41", (32768 + 945) => x"23", (32768 + 946) => x"f3", (32768 + 947) => x"f0", (32768 + 948) => x"1e", (32768 + 949) => x"dd", (32768 + 950) => x"e7", (32768 + 951) => x"00", (32768 + 952) => x"ee", (32768 + 953) => x"a4", (32768 + 954) => x"d5", (32768 + 955) => x"60", (32768 + 956) => x"24", (32768 + 957) => x"61", (32768 + 958) => x"0a", (32768 + 959) => x"62", (32768 + 960) => x"0b", (32768 + 961) => x"d0", (32768 + 962) => x"1b", (32768 + 963) => x"70", (32768 + 964) => x"08", (32768 + 965) => x"f2", (32768 + 966) => x"1e", (32768 + 967) => x"30", (32768 + 968) => x"3c", (32768 + 969) => x"13", (32768 + 970) => x"c1", (32768 + 971) => x"00", (32768 + 972) => x"ee", (32768 + 973) => x"60", (32768 + 974) => x"34", (32768 + 975) => x"61", (32768 + 976) => x"10", (32768 + 977) => x"a4", (32768 + 978) => x"f1", (32768 + 979) => x"d0", (32768 + 980) => x"15", (32768 + 981) => x"a4", (32768 + 982) => x"f6", (32768 + 983) => x"d0", (32768 + 984) => x"15", (32768 + 985) => x"00", (32768 + 986) => x"ee", (32768 + 987) => x"a4", (32768 + 988) => x"fb", (32768 + 989) => x"13", (32768 + 990) => x"e1", (32768 + 991) => x"a5", (32768 + 992) => x"0a", (32768 + 993) => x"60", (32768 + 994) => x"24", (32768 + 995) => x"61", (32768 + 996) => x"0d", (32768 + 997) => x"62", (32768 + 998) => x"05", (32768 + 999) => x"d0", (32768 + 1000) => x"15", (32768 + 1001) => x"70", (32768 + 1002) => x"08", (32768 + 1003) => x"f2", (32768 + 1004) => x"1e", (32768 + 1005) => x"30", (32768 + 1006) => x"3c", (32768 + 1007) => x"13", (32768 + 1008) => x"e7", (32768 + 1009) => x"00", (32768 + 1010) => x"ee", (32768 + 1011) => x"81", (32768 + 1012) => x"00", (32768 + 1013) => x"81", (32768 + 1014) => x"14", (32768 + 1015) => x"80", (32768 + 1016) => x"04", (32768 + 1017) => x"80", (32768 + 1018) => x"04", (32768 + 1019) => x"80", (32768 + 1020) => x"04", (32768 + 1021) => x"80", (32768 + 1022) => x"15", (32768 + 1023) => x"00", (32768 + 1024) => x"ee", (32768 + 1025) => x"f0", (32768 + 1026) => x"15", (32768 + 1027) => x"f0", (32768 + 1028) => x"07", (32768 + 1029) => x"30", (32768 + 1030) => x"00", (32768 + 1031) => x"14", (32768 + 1032) => x"03", (32768 + 1033) => x"00", (32768 + 1034) => x"ee", (32768 + 1035) => x"a4", (32768 + 1036) => x"2f", (32768 + 1037) => x"f3", (32768 + 1038) => x"33", (32768 + 1039) => x"f2", (32768 + 1040) => x"65", (32768 + 1041) => x"65", (32768 + 1042) => x"23", (32768 + 1043) => x"f1", (32768 + 1044) => x"29", (32768 + 1045) => x"d5", (32768 + 1046) => x"65", (32768 + 1047) => x"65", (32768 + 1048) => x"28", (32768 + 1049) => x"f2", (32768 + 1050) => x"29", (32768 + 1051) => x"d5", (32768 + 1052) => x"65", (32768 + 1053) => x"00", (32768 + 1054) => x"ee", (32768 + 1055) => x"01", (32768 + 1056) => x"02", (32768 + 1057) => x"03", (32768 + 1058) => x"04", (32768 + 1059) => x"08", (32768 + 1060) => x"07", (32768 + 1061) => x"06", (32768 + 1062) => x"05", (32768 + 1063) => x"05", (32768 + 1064) => x"06", (32768 + 1065) => x"07", (32768 + 1066) => x"08", (32768 + 1067) => x"04", (32768 + 1068) => x"03", (32768 + 1069) => x"02", (32768 + 1070) => x"01", (32768 + 1071) => x"01", (32768 + 1072) => x"02", (32768 + 1073) => x"03", (32768 + 1074) => x"04", (32768 + 1075) => x"08", (32768 + 1076) => x"07", (32768 + 1077) => x"06", (32768 + 1078) => x"05", (32768 + 1079) => x"05", (32768 + 1080) => x"06", (32768 + 1081) => x"07", (32768 + 1082) => x"08", (32768 + 1083) => x"04", (32768 + 1084) => x"03", (32768 + 1085) => x"02", (32768 + 1086) => x"01", (32768 + 1087) => x"00", (32768 + 1088) => x"00", (32768 + 1089) => x"fe", (32768 + 1090) => x"ee", (32768 + 1091) => x"c6", (32768 + 1092) => x"82", (32768 + 1093) => x"c6", (32768 + 1094) => x"ee", (32768 + 1095) => x"fe", (32768 + 1096) => x"fe", (32768 + 1097) => x"c6", (32768 + 1098) => x"c6", (32768 + 1099) => x"c6", (32768 + 1100) => x"fe", (32768 + 1101) => x"fe", (32768 + 1102) => x"c6", (32768 + 1103) => x"aa", (32768 + 1104) => x"82", (32768 + 1105) => x"aa", (32768 + 1106) => x"c6", (32768 + 1107) => x"fe", (32768 + 1108) => x"c6", (32768 + 1109) => x"82", (32768 + 1110) => x"82", (32768 + 1111) => x"82", (32768 + 1112) => x"c6", (32768 + 1113) => x"fe", (32768 + 1114) => x"ba", (32768 + 1115) => x"d6", (32768 + 1116) => x"ee", (32768 + 1117) => x"d6", (32768 + 1118) => x"ba", (32768 + 1119) => x"fe", (32768 + 1120) => x"ee", (32768 + 1121) => x"ee", (32768 + 1122) => x"82", (32768 + 1123) => x"ee", (32768 + 1124) => x"ee", (32768 + 1125) => x"fe", (32768 + 1126) => x"82", (32768 + 1127) => x"fe", (32768 + 1128) => x"82", (32768 + 1129) => x"fe", (32768 + 1130) => x"82", (32768 + 1131) => x"fe", (32768 + 1132) => x"aa", (32768 + 1133) => x"aa", (32768 + 1134) => x"aa", (32768 + 1135) => x"aa", (32768 + 1136) => x"aa", (32768 + 1137) => x"fe", (32768 + 1138) => x"fe", (32768 + 1139) => x"fe", (32768 + 1140) => x"fe", (32768 + 1141) => x"fe", (32768 + 1142) => x"fe", (32768 + 1143) => x"fe", (32768 + 1144) => x"aa", (32768 + 1145) => x"d6", (32768 + 1146) => x"aa", (32768 + 1147) => x"d6", (32768 + 1148) => x"aa", (32768 + 1149) => x"fe", (32768 + 1150) => x"8b", (32768 + 1151) => x"88", (32768 + 1152) => x"f8", (32768 + 1153) => x"88", (32768 + 1154) => x"8b", (32768 + 1155) => x"00", (32768 + 1156) => x"00", (32768 + 1157) => x"00", (32768 + 1158) => x"00", (32768 + 1159) => x"00", (32768 + 1160) => x"f0", (32768 + 1161) => x"48", (32768 + 1162) => x"48", (32768 + 1163) => x"48", (32768 + 1164) => x"f2", (32768 + 1165) => x"ef", (32768 + 1166) => x"84", (32768 + 1167) => x"84", (32768 + 1168) => x"84", (32768 + 1169) => x"ef", (32768 + 1170) => x"00", (32768 + 1171) => x"08", (32768 + 1172) => x"08", (32768 + 1173) => x"0a", (32768 + 1174) => x"00", (32768 + 1175) => x"8a", (32768 + 1176) => x"8a", (32768 + 1177) => x"aa", (32768 + 1178) => x"aa", (32768 + 1179) => x"52", (32768 + 1180) => x"3c", (32768 + 1181) => x"92", (32768 + 1182) => x"92", (32768 + 1183) => x"92", (32768 + 1184) => x"3c", (32768 + 1185) => x"00", (32768 + 1186) => x"e2", (32768 + 1187) => x"a3", (32768 + 1188) => x"e3", (32768 + 1189) => x"00", (32768 + 1190) => x"8b", (32768 + 1191) => x"c8", (32768 + 1192) => x"a8", (32768 + 1193) => x"98", (32768 + 1194) => x"88", (32768 + 1195) => x"fa", (32768 + 1196) => x"83", (32768 + 1197) => x"e2", (32768 + 1198) => x"82", (32768 + 1199) => x"fa", (32768 + 1200) => x"00", (32768 + 1201) => x"28", (32768 + 1202) => x"b8", (32768 + 1203) => x"90", (32768 + 1204) => x"00", (32768 + 1205) => x"ef", (32768 + 1206) => x"88", (32768 + 1207) => x"8e", (32768 + 1208) => x"88", (32768 + 1209) => x"8f", (32768 + 1210) => x"21", (32768 + 1211) => x"21", (32768 + 1212) => x"a1", (32768 + 1213) => x"60", (32768 + 1214) => x"21", (32768 + 1215) => x"00", (32768 + 1216) => x"00", (32768 + 1217) => x"00", (32768 + 1218) => x"00", (32768 + 1219) => x"00", (32768 + 1220) => x"bc", (32768 + 1221) => x"22", (32768 + 1222) => x"3c", (32768 + 1223) => x"28", (32768 + 1224) => x"a4", (32768 + 1225) => x"89", (32768 + 1226) => x"8a", (32768 + 1227) => x"ab", (32768 + 1228) => x"52", (32768 + 1229) => x"97", (32768 + 1230) => x"51", (32768 + 1231) => x"d1", (32768 + 1232) => x"51", (32768 + 1233) => x"c0", (32768 + 1234) => x"00", (32768 + 1235) => x"00", (32768 + 1236) => x"15", (32768 + 1237) => x"6a", (32768 + 1238) => x"8a", (32768 + 1239) => x"8e", (32768 + 1240) => x"8a", (32768 + 1241) => x"6a", (32768 + 1242) => x"00", (32768 + 1243) => x"64", (32768 + 1244) => x"8a", (32768 + 1245) => x"8e", (32768 + 1246) => x"8a", (32768 + 1247) => x"6a", (32768 + 1248) => x"44", (32768 + 1249) => x"aa", (32768 + 1250) => x"aa", (32768 + 1251) => x"aa", (32768 + 1252) => x"44", (32768 + 1253) => x"00", (32768 + 1254) => x"cc", (32768 + 1255) => x"aa", (32768 + 1256) => x"ca", (32768 + 1257) => x"aa", (32768 + 1258) => x"ac", (32768 + 1259) => x"6e", (32768 + 1260) => x"88", (32768 + 1261) => x"4c", (32768 + 1262) => x"28", (32768 + 1263) => x"ce", (32768 + 1264) => x"00", (32768 + 1265) => x"04", (32768 + 1266) => x"0c", (32768 + 1267) => x"04", (32768 + 1268) => x"04", (32768 + 1269) => x"0e", (32768 + 1270) => x"0c", (32768 + 1271) => x"12", (32768 + 1272) => x"04", (32768 + 1273) => x"08", (32768 + 1274) => x"1e", (32768 + 1275) => x"63", (32768 + 1276) => x"94", (32768 + 1277) => x"94", (32768 + 1278) => x"94", (32768 + 1279) => x"63", (32768 + 1280) => x"38", (32768 + 1281) => x"a5", (32768 + 1282) => x"b8", (32768 + 1283) => x"a0", (32768 + 1284) => x"21", (32768 + 1285) => x"e1", (32768 + 1286) => x"01", (32768 + 1287) => x"c1", (32768 + 1288) => x"20", (32768 + 1289) => x"c1", (32768 + 1290) => x"89", (32768 + 1291) => x"8a", (32768 + 1292) => x"52", (32768 + 1293) => x"22", (32768 + 1294) => x"21", (32768 + 1295) => x"cf", (32768 + 1296) => x"28", (32768 + 1297) => x"2f", (32768 + 1298) => x"28", (32768 + 1299) => x"c8", (32768 + 1300) => x"02", (32768 + 1301) => x"82", (32768 + 1302) => x"02", (32768 + 1303) => x"00", (32768 + 1304) => x"02", (32768 + 1305) => x"ff", (32768 + 1306) => x"80", (32768 + 1307) => x"8f", (32768 + 1308) => x"90", (32768 + 1309) => x"8e", (32768 + 1310) => x"81", (32768 + 1311) => x"9e", (32768 + 1312) => x"80", (32768 + 1313) => x"91", (32768 + 1314) => x"91", (32768 + 1315) => x"9f", (32768 + 1316) => x"91", (32768 + 1317) => x"91", (32768 + 1318) => x"80", (32768 + 1319) => x"ff", (32768 + 1320) => x"00", (32768 + 1321) => x"3c", (32768 + 1322) => x"40", (32768 + 1323) => x"40", (32768 + 1324) => x"40", (32768 + 1325) => x"3c", (32768 + 1326) => x"00", (32768 + 1327) => x"7c", (32768 + 1328) => x"10", (32768 + 1329) => x"10", (32768 + 1330) => x"10", (32768 + 1331) => x"7c", (32768 + 1332) => x"00", (32768 + 1333) => x"ff", (32768 + 1334) => x"00", (32768 + 1335) => x"00", (32768 + 1336) => x"80", (32768 + 1337) => x"00", (32768 + 1338) => x"80", (32768 + 1339) => x"00", (32768 + 1340) => x"00", (32768 + 1341) => x"00", (32768 + 1342) => x"80", (32768 + 1343) => x"00", (32768 + 1344) => x"80", (32768 + 1345) => x"00", (32768 + 1346) => x"00", (32768 + 1347) => x"ff", (32768 + 1348) => x"01", (32768 + 1349) => x"01", (32768 + 1350) => x"01", (32768 + 1351) => x"01", (32768 + 1352) => x"01", (32768 + 1353) => x"01", (32768 + 1354) => x"01", (32768 + 1355) => x"01", (32768 + 1356) => x"01", (32768 + 1357) => x"01", (32768 + 1358) => x"01", (32768 + 1359) => x"01", (32768 + 1360) => x"01", (32768 + 1361) => x"ff",
-- Kaleid by Joseph Weisbecker (RCA)
(36864 + 128) => x"00", (36864 + 129) => x"B0",
(36864 + 130) => x"CD", (36864 + 131) => x"E0",
(36864 + 132) => x"F0", (36864 + 133) => x"00",
(36864 + 134) => x"BE", (36864 + 135) => x"00",
(36864 + 136) => x"00", (36864 + 137) => x"20", -- delay
(36864 + 138) => x"00",
(36864 + 512) => x"60", (36864 + 513) => x"00", (36864 + 514) => x"63", (36864 + 515) => x"80", (36864 + 516) => x"61", (36864 + 517) => x"1f", (36864 + 518) => x"62", (36864 + 519) => x"0f", (36864 + 520) => x"22", (36864 + 521) => x"32", (36864 + 522) => x"a2", (36864 + 523) => x"00", (36864 + 524) => x"f3", (36864 + 525) => x"1e", (36864 + 526) => x"f0", (36864 + 527) => x"0a", (36864 + 528) => x"f0", (36864 + 529) => x"55", (36864 + 530) => x"40", (36864 + 531) => x"00", (36864 + 532) => x"12", (36864 + 533) => x"1c", (36864 + 534) => x"73", (36864 + 535) => x"01", (36864 + 536) => x"33", (36864 + 537) => x"00", (36864 + 538) => x"12", (36864 + 539) => x"08", (36864 + 540) => x"63", (36864 + 541) => x"80", (36864 + 542) => x"a2", (36864 + 543) => x"00", (36864 + 544) => x"f3", (36864 + 545) => x"1e", (36864 + 546) => x"f0", (36864 + 547) => x"65", (36864 + 548) => x"40", (36864 + 549) => x"00", (36864 + 550) => x"12", (36864 + 551) => x"1c", (36864 + 552) => x"73", (36864 + 553) => x"01", (36864 + 554) => x"43", (36864 + 555) => x"00", (36864 + 556) => x"12", (36864 + 557) => x"1c", (36864 + 558) => x"22", (36864 + 559) => x"32", (36864 + 560) => x"12", (36864 + 561) => x"1e", (36864 + 562) => x"40", (36864 + 563) => x"02", (36864 + 564) => x"72", (36864 + 565) => x"ff", (36864 + 566) => x"40", (36864 + 567) => x"04", (36864 + 568) => x"71", (36864 + 569) => x"ff", (36864 + 570) => x"40", (36864 + 571) => x"06", (36864 + 572) => x"71", (36864 + 573) => x"01", (36864 + 574) => x"40", (36864 + 575) => x"08", (36864 + 576) => x"72", (36864 + 577) => x"01", (36864 + 578) => x"a2", (36864 + 579) => x"77", (36864 + 580) => x"6a", (36864 + 581) => x"e0", (36864 + 582) => x"8a", (36864 + 583) => x"12", (36864 + 584) => x"6b", (36864 + 585) => x"1f", (36864 + 586) => x"81", (36864 + 587) => x"b2", (36864 + 588) => x"3a", (36864 + 589) => x"00", (36864 + 590) => x"72", (36864 + 591) => x"01", (36864 + 592) => x"6a", (36864 + 593) => x"f0", (36864 + 594) => x"8a", (36864 + 595) => x"22", (36864 + 596) => x"6b", (36864 + 597) => x"0f", (36864 + 598) => x"82", (36864 + 599) => x"b2", (36864 + 600) => x"3a", (36864 + 601) => x"00", (36864 + 602) => x"71", (36864 + 603) => x"01", (36864 + 604) => x"6b", (36864 + 605) => x"1f", (36864 + 606) => x"81", (36864 + 607) => x"b2", (36864 + 608) => x"d1", (36864 + 609) => x"21", (36864 + 610) => x"8a", (36864 + 611) => x"10", (36864 + 612) => x"6b", (36864 + 613) => x"1f", (36864 + 614) => x"8b", (36864 + 615) => x"25", (36864 + 616) => x"da", (36864 + 617) => x"b1", (36864 + 618) => x"6a", (36864 + 619) => x"3f", (36864 + 620) => x"8a", (36864 + 621) => x"15", (36864 + 622) => x"da", (36864 + 623) => x"b1", (36864 + 624) => x"8b", (36864 + 625) => x"20", (36864 + 626) => x"da", (36864 + 627) => x"b1", (36864 + 628) => x"00", (36864 + 629) => x"ee", (36864 + 630) => x"01", (36864 + 631) => x"80",
-- Merlin by David Winter
(40960 + 128) => x"00", (40960 + 129) => x"00",
(40960 + 130) => x"CB", (40960 + 131) => x"0F",
(40960 + 132) => x"E0", (40960 + 133) => x"00",
(40960 + 134) => x"BE", (40960 + 135) => x"00",
(40960 + 136) => x"00", (40960 + 137) => x"30", -- delay
(40960 + 138) => x"00",
(40960 + 512) => x"12", (40960 + 513) => x"19", (40960 + 514) => x"20", (40960 + 515) => x"4d", (40960 + 516) => x"45", (40960 + 517) => x"52", (40960 + 518) => x"4c", (40960 + 519) => x"49", (40960 + 520) => x"4e", (40960 + 521) => x"20", (40960 + 522) => x"42", (40960 + 523) => x"79", (40960 + 524) => x"20", (40960 + 525) => x"44", (40960 + 526) => x"61", (40960 + 527) => x"76", (40960 + 528) => x"69", (40960 + 529) => x"64", (40960 + 530) => x"20", (40960 + 531) => x"57", (40960 + 532) => x"49", (40960 + 533) => x"4e", (40960 + 534) => x"54", (40960 + 535) => x"45", (40960 + 536) => x"52", (40960 + 537) => x"22", (40960 + 538) => x"f9", (40960 + 539) => x"a3", (40960 + 540) => x"1d", (40960 + 541) => x"60", (40960 + 542) => x"10", (40960 + 543) => x"61", (40960 + 544) => x"00", (40960 + 545) => x"22", (40960 + 546) => x"cb", (40960 + 547) => x"a3", (40960 + 548) => x"31", (40960 + 549) => x"60", (40960 + 550) => x"0b", (40960 + 551) => x"61", (40960 + 552) => x"1b", (40960 + 553) => x"22", (40960 + 554) => x"cb", (40960 + 555) => x"64", (40960 + 556) => x"04", (40960 + 557) => x"22", (40960 + 558) => x"df", (40960 + 559) => x"65", (40960 + 560) => x"00", (40960 + 561) => x"62", (40960 + 562) => x"28", (40960 + 563) => x"22", (40960 + 564) => x"c1", (40960 + 565) => x"c2", (40960 + 566) => x"03", (40960 + 567) => x"80", (40960 + 568) => x"20", (40960 + 569) => x"a3", (40960 + 570) => x"59", (40960 + 571) => x"f5", (40960 + 572) => x"1e", (40960 + 573) => x"f0", (40960 + 574) => x"55", (40960 + 575) => x"60", (40960 + 576) => x"17", (40960 + 577) => x"61", (40960 + 578) => x"08", (40960 + 579) => x"63", (40960 + 580) => x"01", (40960 + 581) => x"83", (40960 + 582) => x"22", (40960 + 583) => x"33", (40960 + 584) => x"00", (40960 + 585) => x"70", (40960 + 586) => x"0a", (40960 + 587) => x"63", (40960 + 588) => x"02", (40960 + 589) => x"83", (40960 + 590) => x"22", (40960 + 591) => x"33", (40960 + 592) => x"00", (40960 + 593) => x"71", (40960 + 594) => x"0a", (40960 + 595) => x"a3", (40960 + 596) => x"17", (40960 + 597) => x"d0", (40960 + 598) => x"16", (40960 + 599) => x"62", (40960 + 600) => x"14", (40960 + 601) => x"22", (40960 + 602) => x"c1", (40960 + 603) => x"d0", (40960 + 604) => x"16", (40960 + 605) => x"62", (40960 + 606) => x"05", (40960 + 607) => x"22", (40960 + 608) => x"c1", (40960 + 609) => x"75", (40960 + 610) => x"01", (40960 + 611) => x"54", (40960 + 612) => x"50", (40960 + 613) => x"12", (40960 + 614) => x"35", (40960 + 615) => x"65", (40960 + 616) => x"00", (40960 + 617) => x"60", (40960 + 618) => x"17", (40960 + 619) => x"61", (40960 + 620) => x"08", (40960 + 621) => x"a3", (40960 + 622) => x"17", (40960 + 623) => x"f3", (40960 + 624) => x"0a", (40960 + 625) => x"33", (40960 + 626) => x"04", (40960 + 627) => x"12", (40960 + 628) => x"79", (40960 + 629) => x"63", (40960 + 630) => x"00", (40960 + 631) => x"12", (40960 + 632) => x"97", (40960 + 633) => x"33", (40960 + 634) => x"05", (40960 + 635) => x"12", (40960 + 636) => x"83", (40960 + 637) => x"70", (40960 + 638) => x"0a", (40960 + 639) => x"63", (40960 + 640) => x"01", (40960 + 641) => x"12", (40960 + 642) => x"97", (40960 + 643) => x"33", (40960 + 644) => x"07", (40960 + 645) => x"12", (40960 + 646) => x"8d", (40960 + 647) => x"71", (40960 + 648) => x"0a", (40960 + 649) => x"63", (40960 + 650) => x"02", (40960 + 651) => x"12", (40960 + 652) => x"97", (40960 + 653) => x"33", (40960 + 654) => x"08", (40960 + 655) => x"12", (40960 + 656) => x"69", (40960 + 657) => x"70", (40960 + 658) => x"0a", (40960 + 659) => x"71", (40960 + 660) => x"0a", (40960 + 661) => x"63", (40960 + 662) => x"03", (40960 + 663) => x"d0", (40960 + 664) => x"16", (40960 + 665) => x"62", (40960 + 666) => x"14", (40960 + 667) => x"22", (40960 + 668) => x"c1", (40960 + 669) => x"d0", (40960 + 670) => x"16", (40960 + 671) => x"a3", (40960 + 672) => x"59", (40960 + 673) => x"f5", (40960 + 674) => x"1e", (40960 + 675) => x"f0", (40960 + 676) => x"65", (40960 + 677) => x"75", (40960 + 678) => x"01", (40960 + 679) => x"50", (40960 + 680) => x"30", (40960 + 681) => x"12", (40960 + 682) => x"b5", (40960 + 683) => x"55", (40960 + 684) => x"40", (40960 + 685) => x"12", (40960 + 686) => x"69", (40960 + 687) => x"22", (40960 + 688) => x"df", (40960 + 689) => x"74", (40960 + 690) => x"01", (40960 + 691) => x"12", (40960 + 692) => x"2d", (40960 + 693) => x"22", (40960 + 694) => x"f9", (40960 + 695) => x"a3", (40960 + 696) => x"45", (40960 + 697) => x"60", (40960 + 698) => x"10", (40960 + 699) => x"61", (40960 + 700) => x"0e", (40960 + 701) => x"22", (40960 + 702) => x"cb", (40960 + 703) => x"12", (40960 + 704) => x"bf", (40960 + 705) => x"f2", (40960 + 706) => x"15", (40960 + 707) => x"f2", (40960 + 708) => x"07", (40960 + 709) => x"32", (40960 + 710) => x"00", (40960 + 711) => x"12", (40960 + 712) => x"c3", (40960 + 713) => x"00", (40960 + 714) => x"ee", (40960 + 715) => x"83", (40960 + 716) => x"00", (40960 + 717) => x"62", (40960 + 718) => x"05", (40960 + 719) => x"d0", (40960 + 720) => x"15", (40960 + 721) => x"f2", (40960 + 722) => x"1e", (40960 + 723) => x"70", (40960 + 724) => x"08", (40960 + 725) => x"85", (40960 + 726) => x"30", (40960 + 727) => x"75", (40960 + 728) => x"20", (40960 + 729) => x"50", (40960 + 730) => x"50", (40960 + 731) => x"12", (40960 + 732) => x"cf", (40960 + 733) => x"00", (40960 + 734) => x"ee", (40960 + 735) => x"a3", (40960 + 736) => x"59", (40960 + 737) => x"83", (40960 + 738) => x"40", (40960 + 739) => x"73", (40960 + 740) => x"fd", (40960 + 741) => x"f3", (40960 + 742) => x"33", (40960 + 743) => x"f2", (40960 + 744) => x"65", (40960 + 745) => x"f1", (40960 + 746) => x"29", (40960 + 747) => x"60", (40960 + 748) => x"2b", (40960 + 749) => x"63", (40960 + 750) => x"1b", (40960 + 751) => x"d0", (40960 + 752) => x"35", (40960 + 753) => x"70", (40960 + 754) => x"05", (40960 + 755) => x"f2", (40960 + 756) => x"29", (40960 + 757) => x"d0", (40960 + 758) => x"35", (40960 + 759) => x"00", (40960 + 760) => x"ee", (40960 + 761) => x"a3", (40960 + 762) => x"0f", (40960 + 763) => x"60", (40960 + 764) => x"17", (40960 + 765) => x"61", (40960 + 766) => x"07", (40960 + 767) => x"d0", (40960 + 768) => x"18", (40960 + 769) => x"70", (40960 + 770) => x"0a", (40960 + 771) => x"d0", (40960 + 772) => x"18", (40960 + 773) => x"71", (40960 + 774) => x"0a", (40960 + 775) => x"d0", (40960 + 776) => x"18", (40960 + 777) => x"70", (40960 + 778) => x"f6", (40960 + 779) => x"d0", (40960 + 780) => x"18", (40960 + 781) => x"00", (40960 + 782) => x"ee", (40960 + 783) => x"ff", (40960 + 784) => x"81", (40960 + 785) => x"81", (40960 + 786) => x"81", (40960 + 787) => x"81", (40960 + 788) => x"81", (40960 + 789) => x"81", (40960 + 790) => x"ff", (40960 + 791) => x"7e", (40960 + 792) => x"7e", (40960 + 793) => x"7e", (40960 + 794) => x"7e", (40960 + 795) => x"7e", (40960 + 796) => x"7e", (40960 + 797) => x"db", (40960 + 798) => x"aa", (40960 + 799) => x"8b", (40960 + 800) => x"cb", (40960 + 801) => x"cb", (40960 + 802) => x"ef", (40960 + 803) => x"08", (40960 + 804) => x"8f", (40960 + 805) => x"0d", (40960 + 806) => x"ec", (40960 + 807) => x"a0", (40960 + 808) => x"a0", (40960 + 809) => x"b0", (40960 + 810) => x"30", (40960 + 811) => x"be", (40960 + 812) => x"5f", (40960 + 813) => x"51", (40960 + 814) => x"51", (40960 + 815) => x"d9", (40960 + 816) => x"d9", (40960 + 817) => x"83", (40960 + 818) => x"82", (40960 + 819) => x"83", (40960 + 820) => x"82", (40960 + 821) => x"fb", (40960 + 822) => x"e8", (40960 + 823) => x"08", (40960 + 824) => x"88", (40960 + 825) => x"05", (40960 + 826) => x"e2", (40960 + 827) => x"be", (40960 + 828) => x"a0", (40960 + 829) => x"b8", (40960 + 830) => x"20", (40960 + 831) => x"3e", (40960 + 832) => x"80", (40960 + 833) => x"80", (40960 + 834) => x"80", (40960 + 835) => x"80", (40960 + 836) => x"f8", (40960 + 837) => x"f7", (40960 + 838) => x"85", (40960 + 839) => x"b7", (40960 + 840) => x"95", (40960 + 841) => x"f5", (40960 + 842) => x"76", (40960 + 843) => x"54", (40960 + 844) => x"56", (40960 + 845) => x"54", (40960 + 846) => x"56", (40960 + 847) => x"3a", (40960 + 848) => x"2a", (40960 + 849) => x"2a", (40960 + 850) => x"2a", (40960 + 851) => x"39", (40960 + 852) => x"b6", (40960 + 853) => x"a5", (40960 + 854) => x"b6", (40960 + 855) => x"a5", (40960 + 856) => x"35", (40960 + 857) => x"00",
-- Missile by David Winter
(45056 + 128) => x"0F", (45056 + 129) => x"00",
(45056 + 130) => x"C0", (45056 + 131) => x"00",
(45056 + 132) => x"D0", (45056 + 133) => x"00",
(45056 + 134) => x"BE", (45056 + 135) => x"00",
(45056 + 136) => x"00", (45056 + 137) => x"30", -- delay
(45056 + 138) => x"00",
(45056 + 512) => x"12", (45056 + 513) => x"19", (45056 + 514) => x"4d", (45056 + 515) => x"49", (45056 + 516) => x"53", (45056 + 517) => x"53", (45056 + 518) => x"49", (45056 + 519) => x"4c", (45056 + 520) => x"45", (45056 + 521) => x"20", (45056 + 522) => x"62", (45056 + 523) => x"79", (45056 + 524) => x"20", (45056 + 525) => x"44", (45056 + 526) => x"61", (45056 + 527) => x"76", (45056 + 528) => x"69", (45056 + 529) => x"64", (45056 + 530) => x"20", (45056 + 531) => x"57", (45056 + 532) => x"49", (45056 + 533) => x"4e", (45056 + 534) => x"54", (45056 + 535) => x"45", (45056 + 536) => x"52", (45056 + 537) => x"6c", (45056 + 538) => x"0c", (45056 + 539) => x"60", (45056 + 540) => x"00", (45056 + 541) => x"61", (45056 + 542) => x"00", (45056 + 543) => x"65", (45056 + 544) => x"08", (45056 + 545) => x"66", (45056 + 546) => x"0a", (45056 + 547) => x"67", (45056 + 548) => x"00", (45056 + 549) => x"6e", (45056 + 550) => x"01", (45056 + 551) => x"a2", (45056 + 552) => x"ad", (45056 + 553) => x"d0", (45056 + 554) => x"14", (45056 + 555) => x"70", (45056 + 556) => x"08", (45056 + 557) => x"30", (45056 + 558) => x"40", (45056 + 559) => x"12", (45056 + 560) => x"29", (45056 + 561) => x"60", (45056 + 562) => x"00", (45056 + 563) => x"61", (45056 + 564) => x"1c", (45056 + 565) => x"a2", (45056 + 566) => x"b0", (45056 + 567) => x"d0", (45056 + 568) => x"14", (45056 + 569) => x"a2", (45056 + 570) => x"b0", (45056 + 571) => x"d0", (45056 + 572) => x"14", (45056 + 573) => x"3e", (45056 + 574) => x"01", (45056 + 575) => x"12", (45056 + 576) => x"49", (45056 + 577) => x"70", (45056 + 578) => x"04", (45056 + 579) => x"40", (45056 + 580) => x"38", (45056 + 581) => x"6e", (45056 + 582) => x"00", (45056 + 583) => x"12", (45056 + 584) => x"4f", (45056 + 585) => x"70", (45056 + 586) => x"fc", (45056 + 587) => x"40", (45056 + 588) => x"00", (45056 + 589) => x"6e", (45056 + 590) => x"01", (45056 + 591) => x"d0", (45056 + 592) => x"14", (45056 + 593) => x"fc", (45056 + 594) => x"15", (45056 + 595) => x"fb", (45056 + 596) => x"07", (45056 + 597) => x"3b", (45056 + 598) => x"00", (45056 + 599) => x"12", (45056 + 600) => x"53", (45056 + 601) => x"62", (45056 + 602) => x"08", (45056 + 603) => x"e2", (45056 + 604) => x"9e", (45056 + 605) => x"12", (45056 + 606) => x"95", (45056 + 607) => x"3c", (45056 + 608) => x"00", (45056 + 609) => x"7c", (45056 + 610) => x"fe", (45056 + 611) => x"63", (45056 + 612) => x"1b", (45056 + 613) => x"82", (45056 + 614) => x"00", (45056 + 615) => x"a2", (45056 + 616) => x"b0", (45056 + 617) => x"d2", (45056 + 618) => x"31", (45056 + 619) => x"64", (45056 + 620) => x"00", (45056 + 621) => x"d2", (45056 + 622) => x"31", (45056 + 623) => x"73", (45056 + 624) => x"ff", (45056 + 625) => x"d2", (45056 + 626) => x"31", (45056 + 627) => x"3f", (45056 + 628) => x"00", (45056 + 629) => x"64", (45056 + 630) => x"01", (45056 + 631) => x"33", (45056 + 632) => x"03", (45056 + 633) => x"12", (45056 + 634) => x"6d", (45056 + 635) => x"d2", (45056 + 636) => x"31", (45056 + 637) => x"34", (45056 + 638) => x"01", (45056 + 639) => x"12", (45056 + 640) => x"91", (45056 + 641) => x"77", (45056 + 642) => x"05", (45056 + 643) => x"75", (45056 + 644) => x"ff", (45056 + 645) => x"82", (45056 + 646) => x"00", (45056 + 647) => x"63", (45056 + 648) => x"00", (45056 + 649) => x"a2", (45056 + 650) => x"ad", (45056 + 651) => x"d2", (45056 + 652) => x"34", (45056 + 653) => x"45", (45056 + 654) => x"00", (45056 + 655) => x"12", (45056 + 656) => x"97", (45056 + 657) => x"76", (45056 + 658) => x"ff", (45056 + 659) => x"36", (45056 + 660) => x"00", (45056 + 661) => x"12", (45056 + 662) => x"39", (45056 + 663) => x"a2", (45056 + 664) => x"b4", (45056 + 665) => x"f7", (45056 + 666) => x"33", (45056 + 667) => x"f2", (45056 + 668) => x"65", (45056 + 669) => x"63", (45056 + 670) => x"1b", (45056 + 671) => x"64", (45056 + 672) => x"0d", (45056 + 673) => x"f1", (45056 + 674) => x"29", (45056 + 675) => x"d3", (45056 + 676) => x"45", (45056 + 677) => x"73", (45056 + 678) => x"05", (45056 + 679) => x"f2", (45056 + 680) => x"29", (45056 + 681) => x"d3", (45056 + 682) => x"45", (45056 + 683) => x"12", (45056 + 684) => x"ab", (45056 + 685) => x"10", (45056 + 686) => x"38", (45056 + 687) => x"38", (45056 + 688) => x"10", (45056 + 689) => x"38", (45056 + 690) => x"7c", (45056 + 691) => x"fe",
-- Puzzle by Joseph Weisbecker (RCA)
(49152 + 128) => x"00", (49152 + 129) => x"B0",
(49152 + 130) => x"C0", (49152 + 131) => x"E0",
(49152 + 132) => x"F0", (49152 + 133) => x"00",
(49152 + 134) => x"BE", (49152 + 135) => x"00",
(49152 + 136) => x"00", (49152 + 137) => x"30", -- delay
(49152 + 138) => x"00",
(49152 + 512) => x"6a", (49152 + 513) => x"12", (49152 + 514) => x"6b", (49152 + 515) => x"01", (49152 + 516) => x"61", (49152 + 517) => x"10", (49152 + 518) => x"62", (49152 + 519) => x"00", (49152 + 520) => x"60", (49152 + 521) => x"00", (49152 + 522) => x"a2", (49152 + 523) => x"b0", (49152 + 524) => x"d1", (49152 + 525) => x"27", (49152 + 526) => x"f0", (49152 + 527) => x"29", (49152 + 528) => x"30", (49152 + 529) => x"00", (49152 + 530) => x"da", (49152 + 531) => x"b5", (49152 + 532) => x"71", (49152 + 533) => x"08", (49152 + 534) => x"7a", (49152 + 535) => x"08", (49152 + 536) => x"31", (49152 + 537) => x"30", (49152 + 538) => x"12", (49152 + 539) => x"24", (49152 + 540) => x"61", (49152 + 541) => x"10", (49152 + 542) => x"72", (49152 + 543) => x"08", (49152 + 544) => x"6a", (49152 + 545) => x"12", (49152 + 546) => x"7b", (49152 + 547) => x"08", (49152 + 548) => x"a3", (49152 + 549) => x"00", (49152 + 550) => x"f0", (49152 + 551) => x"1e", (49152 + 552) => x"f0", (49152 + 553) => x"55", (49152 + 554) => x"70", (49152 + 555) => x"01", (49152 + 556) => x"30", (49152 + 557) => x"10", (49152 + 558) => x"12", (49152 + 559) => x"0a", (49152 + 560) => x"6a", (49152 + 561) => x"12", (49152 + 562) => x"6b", (49152 + 563) => x"01", (49152 + 564) => x"6c", (49152 + 565) => x"00", (49152 + 566) => x"62", (49152 + 567) => x"ff", (49152 + 568) => x"c0", (49152 + 569) => x"06", (49152 + 570) => x"70", (49152 + 571) => x"02", (49152 + 572) => x"22", (49152 + 573) => x"52", (49152 + 574) => x"72", (49152 + 575) => x"ff", (49152 + 576) => x"32", (49152 + 577) => x"00", (49152 + 578) => x"12", (49152 + 579) => x"38", (49152 + 580) => x"6e", (49152 + 581) => x"00", (49152 + 582) => x"6e", (49152 + 583) => x"00", (49152 + 584) => x"f0", (49152 + 585) => x"0a", (49152 + 586) => x"22", (49152 + 587) => x"52", (49152 + 588) => x"7e", (49152 + 589) => x"01", (49152 + 590) => x"7e", (49152 + 591) => x"01", (49152 + 592) => x"12", (49152 + 593) => x"48", (49152 + 594) => x"84", (49152 + 595) => x"a0", (49152 + 596) => x"85", (49152 + 597) => x"b0", (49152 + 598) => x"86", (49152 + 599) => x"c0", (49152 + 600) => x"30", (49152 + 601) => x"02", (49152 + 602) => x"12", (49152 + 603) => x"64", (49152 + 604) => x"45", (49152 + 605) => x"01", (49152 + 606) => x"12", (49152 + 607) => x"64", (49152 + 608) => x"75", (49152 + 609) => x"f8", (49152 + 610) => x"76", (49152 + 611) => x"fc", (49152 + 612) => x"30", (49152 + 613) => x"08", (49152 + 614) => x"12", (49152 + 615) => x"70", (49152 + 616) => x"45", (49152 + 617) => x"19", (49152 + 618) => x"12", (49152 + 619) => x"70", (49152 + 620) => x"75", (49152 + 621) => x"08", (49152 + 622) => x"76", (49152 + 623) => x"04", (49152 + 624) => x"30", (49152 + 625) => x"06", (49152 + 626) => x"12", (49152 + 627) => x"7c", (49152 + 628) => x"44", (49152 + 629) => x"12", (49152 + 630) => x"12", (49152 + 631) => x"7c", (49152 + 632) => x"74", (49152 + 633) => x"f8", (49152 + 634) => x"76", (49152 + 635) => x"ff", (49152 + 636) => x"30", (49152 + 637) => x"04", (49152 + 638) => x"12", (49152 + 639) => x"88", (49152 + 640) => x"44", (49152 + 641) => x"2a", (49152 + 642) => x"12", (49152 + 643) => x"88", (49152 + 644) => x"74", (49152 + 645) => x"08", (49152 + 646) => x"76", (49152 + 647) => x"01", (49152 + 648) => x"a3", (49152 + 649) => x"00", (49152 + 650) => x"f6", (49152 + 651) => x"1e", (49152 + 652) => x"f0", (49152 + 653) => x"65", (49152 + 654) => x"81", (49152 + 655) => x"00", (49152 + 656) => x"60", (49152 + 657) => x"00", (49152 + 658) => x"a3", (49152 + 659) => x"00", (49152 + 660) => x"f6", (49152 + 661) => x"1e", (49152 + 662) => x"f0", (49152 + 663) => x"55", (49152 + 664) => x"a3", (49152 + 665) => x"00", (49152 + 666) => x"fc", (49152 + 667) => x"1e", (49152 + 668) => x"80", (49152 + 669) => x"10", (49152 + 670) => x"f0", (49152 + 671) => x"55", (49152 + 672) => x"f1", (49152 + 673) => x"29", (49152 + 674) => x"d4", (49152 + 675) => x"55", (49152 + 676) => x"da", (49152 + 677) => x"b5", (49152 + 678) => x"8a", (49152 + 679) => x"40", (49152 + 680) => x"8b", (49152 + 681) => x"50", (49152 + 682) => x"8c", (49152 + 683) => x"60", (49152 + 684) => x"00", (49152 + 685) => x"ee", (49152 + 686) => x"ee", (49152 + 687) => x"5e", (49152 + 688) => x"fe", (49152 + 689) => x"fe", (49152 + 690) => x"fe", (49152 + 691) => x"fe", (49152 + 692) => x"fe", (49152 + 693) => x"fe", (49152 + 694) => x"fe", (49152 + 695) => x"fe",
-- Tank by Joseph Weisbecker (RCA)
(53248 + 128) => x"00", (53248 + 129) => x"B0",
(53248 + 130) => x"CD", (53248 + 131) => x"E0",
(53248 + 132) => x"F0", (53248 + 133) => x"00",
(53248 + 134) => x"BE", (53248 + 135) => x"00",
(53248 + 136) => x"00", (53248 + 137) => x"30", -- delay
(53248 + 138) => x"00",
(53248 + 512) => x"12", (53248 + 513) => x"30", (53248 + 514) => x"76", (53248 + 515) => x"fb", (53248 + 516) => x"60", (53248 + 517) => x"20", (53248 + 518) => x"80", (53248 + 519) => x"65", (53248 + 520) => x"4f", (53248 + 521) => x"00", (53248 + 522) => x"66", (53248 + 523) => x"00", (53248 + 524) => x"13", (53248 + 525) => x"84", (53248 + 526) => x"00", (53248 + 527) => x"ff", (53248 + 528) => x"00", (53248 + 529) => x"00", (53248 + 530) => x"00", (53248 + 531) => x"01", (53248 + 532) => x"00", (53248 + 533) => x"0c", (53248 + 534) => x"0a", (53248 + 535) => x"00", (53248 + 536) => x"19", (53248 + 537) => x"02", (53248 + 538) => x"04", (53248 + 539) => x"06", (53248 + 540) => x"08", (53248 + 541) => x"02", (53248 + 542) => x"02", (53248 + 543) => x"03", (53248 + 544) => x"2c", (53248 + 545) => x"00", (53248 + 546) => x"0f", (53248 + 547) => x"00", (53248 + 548) => x"02", (53248 + 549) => x"05", (53248 + 550) => x"2e", (53248 + 551) => x"08", (53248 + 552) => x"00", (53248 + 553) => x"00", (53248 + 554) => x"02", (53248 + 555) => x"05", (53248 + 556) => x"00", (53248 + 557) => x"00", (53248 + 558) => x"00", (53248 + 559) => x"00", (53248 + 560) => x"6e", (53248 + 561) => x"00", (53248 + 562) => x"6d", (53248 + 563) => x"a0", (53248 + 564) => x"6a", (53248 + 565) => x"08", (53248 + 566) => x"69", (53248 + 567) => x"06", (53248 + 568) => x"68", (53248 + 569) => x"04", (53248 + 570) => x"67", (53248 + 571) => x"02", (53248 + 572) => x"66", (53248 + 573) => x"19", (53248 + 574) => x"64", (53248 + 575) => x"10", (53248 + 576) => x"63", (53248 + 577) => x"0c", (53248 + 578) => x"62", (53248 + 579) => x"00", (53248 + 580) => x"61", (53248 + 581) => x"06", (53248 + 582) => x"a2", (53248 + 583) => x"12", (53248 + 584) => x"fa", (53248 + 585) => x"55", (53248 + 586) => x"23", (53248 + 587) => x"d4", (53248 + 588) => x"60", (53248 + 589) => x"40", (53248 + 590) => x"f0", (53248 + 591) => x"15", (53248 + 592) => x"f0", (53248 + 593) => x"07", (53248 + 594) => x"30", (53248 + 595) => x"00", (53248 + 596) => x"12", (53248 + 597) => x"50", (53248 + 598) => x"23", (53248 + 599) => x"d4", (53248 + 600) => x"23", (53248 + 601) => x"0a", (53248 + 602) => x"23", (53248 + 603) => x"62", (53248 + 604) => x"a2", (53248 + 605) => x"12", (53248 + 606) => x"f5", (53248 + 607) => x"65", (53248 + 608) => x"22", (53248 + 609) => x"ae", (53248 + 610) => x"22", (53248 + 611) => x"c6", (53248 + 612) => x"22", (53248 + 613) => x"ec", (53248 + 614) => x"3f", (53248 + 615) => x"01", (53248 + 616) => x"23", (53248 + 617) => x"14", (53248 + 618) => x"3f", (53248 + 619) => x"01", (53248 + 620) => x"22", (53248 + 621) => x"ec", (53248 + 622) => x"3f", (53248 + 623) => x"01", (53248 + 624) => x"22", (53248 + 625) => x"ec", (53248 + 626) => x"3f", (53248 + 627) => x"01", (53248 + 628) => x"22", (53248 + 629) => x"7c", (53248 + 630) => x"4f", (53248 + 631) => x"01", (53248 + 632) => x"13", (53248 + 633) => x"66", (53248 + 634) => x"12", (53248 + 635) => x"62", (53248 + 636) => x"a2", (53248 + 637) => x"12", (53248 + 638) => x"f5", (53248 + 639) => x"65", (53248 + 640) => x"46", (53248 + 641) => x"00", (53248 + 642) => x"35", (53248 + 643) => x"00", (53248 + 644) => x"12", (53248 + 645) => x"88", (53248 + 646) => x"13", (53248 + 647) => x"8c", (53248 + 648) => x"e7", (53248 + 649) => x"a1", (53248 + 650) => x"62", (53248 + 651) => x"09", (53248 + 652) => x"e8", (53248 + 653) => x"a1", (53248 + 654) => x"62", (53248 + 655) => x"04", (53248 + 656) => x"e9", (53248 + 657) => x"a1", (53248 + 658) => x"62", (53248 + 659) => x"06", (53248 + 660) => x"ea", (53248 + 661) => x"a1", (53248 + 662) => x"62", (53248 + 663) => x"01", (53248 + 664) => x"42", (53248 + 665) => x"00", (53248 + 666) => x"00", (53248 + 667) => x"ee", (53248 + 668) => x"22", (53248 + 669) => x"ae", (53248 + 670) => x"81", (53248 + 671) => x"20", (53248 + 672) => x"23", (53248 + 673) => x"9a", (53248 + 674) => x"23", (53248 + 675) => x"ac", (53248 + 676) => x"6c", (53248 + 677) => x"01", (53248 + 678) => x"62", (53248 + 679) => x"00", (53248 + 680) => x"6f", (53248 + 681) => x"00", (53248 + 682) => x"a2", (53248 + 683) => x"12", (53248 + 684) => x"f5", (53248 + 685) => x"55", (53248 + 686) => x"a3", (53248 + 687) => x"ff", (53248 + 688) => x"41", (53248 + 689) => x"01", (53248 + 690) => x"60", (53248 + 691) => x"00", (53248 + 692) => x"41", (53248 + 693) => x"04", (53248 + 694) => x"60", (53248 + 695) => x"13", (53248 + 696) => x"41", (53248 + 697) => x"06", (53248 + 698) => x"60", (53248 + 699) => x"0d", (53248 + 700) => x"41", (53248 + 701) => x"09", (53248 + 702) => x"60", (53248 + 703) => x"06", (53248 + 704) => x"f0", (53248 + 705) => x"1e", (53248 + 706) => x"d3", (53248 + 707) => x"47", (53248 + 708) => x"00", (53248 + 709) => x"ee", (53248 + 710) => x"60", (53248 + 711) => x"05", (53248 + 712) => x"e0", (53248 + 713) => x"9e", (53248 + 714) => x"00", (53248 + 715) => x"ee", (53248 + 716) => x"45", (53248 + 717) => x"0f", (53248 + 718) => x"00", (53248 + 719) => x"ee", (53248 + 720) => x"65", (53248 + 721) => x"0f", (53248 + 722) => x"76", (53248 + 723) => x"ff", (53248 + 724) => x"a2", (53248 + 725) => x"12", (53248 + 726) => x"f5", (53248 + 727) => x"55", (53248 + 728) => x"74", (53248 + 729) => x"03", (53248 + 730) => x"73", (53248 + 731) => x"03", (53248 + 732) => x"23", (53248 + 733) => x"9a", (53248 + 734) => x"23", (53248 + 735) => x"9a", (53248 + 736) => x"23", (53248 + 737) => x"9a", (53248 + 738) => x"a2", (53248 + 739) => x"23", (53248 + 740) => x"f5", (53248 + 741) => x"55", (53248 + 742) => x"a4", (53248 + 743) => x"19", (53248 + 744) => x"d3", (53248 + 745) => x"41", (53248 + 746) => x"00", (53248 + 747) => x"ee", (53248 + 748) => x"a2", (53248 + 749) => x"23", (53248 + 750) => x"f5", (53248 + 751) => x"65", (53248 + 752) => x"45", (53248 + 753) => x"00", (53248 + 754) => x"00", (53248 + 755) => x"ee", (53248 + 756) => x"a4", (53248 + 757) => x"19", (53248 + 758) => x"d3", (53248 + 759) => x"41", (53248 + 760) => x"23", (53248 + 761) => x"9a", (53248 + 762) => x"6c", (53248 + 763) => x"02", (53248 + 764) => x"23", (53248 + 765) => x"be", (53248 + 766) => x"4b", (53248 + 767) => x"bb", (53248 + 768) => x"13", (53248 + 769) => x"0a", (53248 + 770) => x"d3", (53248 + 771) => x"41", (53248 + 772) => x"a2", (53248 + 773) => x"23", (53248 + 774) => x"f5", (53248 + 775) => x"55", (53248 + 776) => x"00", (53248 + 777) => x"ee", (53248 + 778) => x"65", (53248 + 779) => x"00", (53248 + 780) => x"60", (53248 + 781) => x"00", (53248 + 782) => x"a2", (53248 + 783) => x"17", (53248 + 784) => x"f0", (53248 + 785) => x"55", (53248 + 786) => x"13", (53248 + 787) => x"04", (53248 + 788) => x"a2", (53248 + 789) => x"1d", (53248 + 790) => x"f5", (53248 + 791) => x"65", (53248 + 792) => x"35", (53248 + 793) => x"0f", (53248 + 794) => x"13", (53248 + 795) => x"44", (53248 + 796) => x"a4", (53248 + 797) => x"1a", (53248 + 798) => x"d3", (53248 + 799) => x"45", (53248 + 800) => x"32", (53248 + 801) => x"00", (53248 + 802) => x"13", (53248 + 803) => x"32", (53248 + 804) => x"c1", (53248 + 805) => x"03", (53248 + 806) => x"a2", (53248 + 807) => x"19", (53248 + 808) => x"f1", (53248 + 809) => x"1e", (53248 + 810) => x"f0", (53248 + 811) => x"65", (53248 + 812) => x"81", (53248 + 813) => x"00", (53248 + 814) => x"c2", (53248 + 815) => x"0f", (53248 + 816) => x"72", (53248 + 817) => x"01", (53248 + 818) => x"23", (53248 + 819) => x"9a", (53248 + 820) => x"a4", (53248 + 821) => x"1a", (53248 + 822) => x"6c", (53248 + 823) => x"03", (53248 + 824) => x"72", (53248 + 825) => x"ff", (53248 + 826) => x"6f", (53248 + 827) => x"00", (53248 + 828) => x"d3", (53248 + 829) => x"45", (53248 + 830) => x"a2", (53248 + 831) => x"1d", (53248 + 832) => x"f5", (53248 + 833) => x"55", (53248 + 834) => x"00", (53248 + 835) => x"ee", (53248 + 836) => x"c4", (53248 + 837) => x"07", (53248 + 838) => x"a4", (53248 + 839) => x"1f", (53248 + 840) => x"f4", (53248 + 841) => x"1e", (53248 + 842) => x"f0", (53248 + 843) => x"65", (53248 + 844) => x"83", (53248 + 845) => x"00", (53248 + 846) => x"a4", (53248 + 847) => x"27", (53248 + 848) => x"f4", (53248 + 849) => x"1e", (53248 + 850) => x"f0", (53248 + 851) => x"65", (53248 + 852) => x"84", (53248 + 853) => x"00", (53248 + 854) => x"a4", (53248 + 855) => x"1a", (53248 + 856) => x"d3", (53248 + 857) => x"45", (53248 + 858) => x"60", (53248 + 859) => x"20", (53248 + 860) => x"f0", (53248 + 861) => x"18", (53248 + 862) => x"65", (53248 + 863) => x"0f", (53248 + 864) => x"13", (53248 + 865) => x"3e", (53248 + 866) => x"65", (53248 + 867) => x"00", (53248 + 868) => x"13", (53248 + 869) => x"3e", (53248 + 870) => x"4c", (53248 + 871) => x"01", (53248 + 872) => x"12", (53248 + 873) => x"02", (53248 + 874) => x"4c", (53248 + 875) => x"02", (53248 + 876) => x"13", (53248 + 877) => x"82", (53248 + 878) => x"a2", (53248 + 879) => x"23", (53248 + 880) => x"f5", (53248 + 881) => x"65", (53248 + 882) => x"45", (53248 + 883) => x"00", (53248 + 884) => x"12", (53248 + 885) => x"02", (53248 + 886) => x"a4", (53248 + 887) => x"19", (53248 + 888) => x"d3", (53248 + 889) => x"41", (53248 + 890) => x"6f", (53248 + 891) => x"00", (53248 + 892) => x"d3", (53248 + 893) => x"41", (53248 + 894) => x"3f", (53248 + 895) => x"01", (53248 + 896) => x"12", (53248 + 897) => x"02", (53248 + 898) => x"7e", (53248 + 899) => x"0a", (53248 + 900) => x"60", (53248 + 901) => x"40", (53248 + 902) => x"f0", (53248 + 903) => x"18", (53248 + 904) => x"00", (53248 + 905) => x"e0", (53248 + 906) => x"12", (53248 + 907) => x"4a", (53248 + 908) => x"00", (53248 + 909) => x"e0", (53248 + 910) => x"23", (53248 + 911) => x"d4", (53248 + 912) => x"60", (53248 + 913) => x"60", (53248 + 914) => x"f0", (53248 + 915) => x"18", (53248 + 916) => x"13", (53248 + 917) => x"94", (53248 + 918) => x"6e", (53248 + 919) => x"00", (53248 + 920) => x"13", (53248 + 921) => x"84", (53248 + 922) => x"41", (53248 + 923) => x"01", (53248 + 924) => x"74", (53248 + 925) => x"ff", (53248 + 926) => x"41", (53248 + 927) => x"04", (53248 + 928) => x"73", (53248 + 929) => x"ff", (53248 + 930) => x"41", (53248 + 931) => x"06", (53248 + 932) => x"73", (53248 + 933) => x"01", (53248 + 934) => x"41", (53248 + 935) => x"09", (53248 + 936) => x"74", (53248 + 937) => x"01", (53248 + 938) => x"00", (53248 + 939) => x"ee", (53248 + 940) => x"44", (53248 + 941) => x"00", (53248 + 942) => x"74", (53248 + 943) => x"01", (53248 + 944) => x"43", (53248 + 945) => x"00", (53248 + 946) => x"73", (53248 + 947) => x"01", (53248 + 948) => x"43", (53248 + 949) => x"38", (53248 + 950) => x"73", (53248 + 951) => x"ff", (53248 + 952) => x"44", (53248 + 953) => x"18", (53248 + 954) => x"74", (53248 + 955) => x"ff", (53248 + 956) => x"00", (53248 + 957) => x"ee", (53248 + 958) => x"6b", (53248 + 959) => x"00", (53248 + 960) => x"44", (53248 + 961) => x"00", (53248 + 962) => x"13", (53248 + 963) => x"ce", (53248 + 964) => x"43", (53248 + 965) => x"00", (53248 + 966) => x"13", (53248 + 967) => x"ce", (53248 + 968) => x"43", (53248 + 969) => x"3f", (53248 + 970) => x"13", (53248 + 971) => x"ce", (53248 + 972) => x"44", (53248 + 973) => x"1f", (53248 + 974) => x"6b", (53248 + 975) => x"bb", (53248 + 976) => x"6f", (53248 + 977) => x"00", (53248 + 978) => x"00", (53248 + 979) => x"ee", (53248 + 980) => x"63", (53248 + 981) => x"08", (53248 + 982) => x"64", (53248 + 983) => x"08", (53248 + 984) => x"a2", (53248 + 985) => x"29", (53248 + 986) => x"fe", (53248 + 987) => x"33", (53248 + 988) => x"f2", (53248 + 989) => x"65", (53248 + 990) => x"23", (53248 + 991) => x"ec", (53248 + 992) => x"63", (53248 + 993) => x"28", (53248 + 994) => x"a2", (53248 + 995) => x"29", (53248 + 996) => x"f6", (53248 + 997) => x"33", (53248 + 998) => x"f2", (53248 + 999) => x"65", (53248 + 1000) => x"23", (53248 + 1001) => x"f2", (53248 + 1002) => x"00", (53248 + 1003) => x"ee", (53248 + 1004) => x"f0", (53248 + 1005) => x"29", (53248 + 1006) => x"d3", (53248 + 1007) => x"45", (53248 + 1008) => x"73", (53248 + 1009) => x"06", (53248 + 1010) => x"f1", (53248 + 1011) => x"29", (53248 + 1012) => x"d3", (53248 + 1013) => x"45", (53248 + 1014) => x"73", (53248 + 1015) => x"06", (53248 + 1016) => x"f2", (53248 + 1017) => x"29", (53248 + 1018) => x"d3", (53248 + 1019) => x"45", (53248 + 1020) => x"00", (53248 + 1021) => x"ee", (53248 + 1022) => x"01", (53248 + 1023) => x"10", (53248 + 1024) => x"54", (53248 + 1025) => x"7c", (53248 + 1026) => x"6c", (53248 + 1027) => x"7c", (53248 + 1028) => x"7c", (53248 + 1029) => x"44", (53248 + 1030) => x"7c", (53248 + 1031) => x"7c", (53248 + 1032) => x"6c", (53248 + 1033) => x"7c", (53248 + 1034) => x"54", (53248 + 1035) => x"10", (53248 + 1036) => x"00", (53248 + 1037) => x"fc", (53248 + 1038) => x"78", (53248 + 1039) => x"6e", (53248 + 1040) => x"78", (53248 + 1041) => x"fc", (53248 + 1042) => x"00", (53248 + 1043) => x"3f", (53248 + 1044) => x"1e", (53248 + 1045) => x"76", (53248 + 1046) => x"1e", (53248 + 1047) => x"3f", (53248 + 1048) => x"00", (53248 + 1049) => x"80", (53248 + 1050) => x"a8", (53248 + 1051) => x"70", (53248 + 1052) => x"f8", (53248 + 1053) => x"70", (53248 + 1054) => x"a8", (53248 + 1055) => x"0b", (53248 + 1056) => x"1b", (53248 + 1057) => x"28", (53248 + 1058) => x"38", (53248 + 1059) => x"30", (53248 + 1060) => x"20", (53248 + 1061) => x"10", (53248 + 1062) => x"00", (53248 + 1063) => x"00", (53248 + 1064) => x"00", (53248 + 1065) => x"00", (53248 + 1066) => x"08", (53248 + 1067) => x"1b", (53248 + 1068) => x"1b", (53248 + 1069) => x"1b", (53248 + 1070) => x"18", (53248 + 1071) => x"04",
-- Vers by JMN
(57344 + 128) => x"03", (57344 + 129) => x"00",
(57344 + 130) => x"00", (57344 + 131) => x"02",
(57344 + 132) => x"00", (57344 + 133) => x"1C",
(57344 + 134) => x"BF", (57344 + 135) => x"0E",
(57344 + 136) => x"00", (57344 + 137) => x"30", -- delay
(57344 + 138) => x"00",
(57344 + 512) => x"12", (57344 + 513) => x"1a", (57344 + 514) => x"4a", (57344 + 515) => x"4d", (57344 + 516) => x"4e", (57344 + 517) => x"20", (57344 + 518) => x"31", (57344 + 519) => x"39", (57344 + 520) => x"39", (57344 + 521) => x"31", (57344 + 522) => x"20", (57344 + 523) => x"53", (57344 + 524) => x"4f", (57344 + 525) => x"46", (57344 + 526) => x"54", (57344 + 527) => x"57", (57344 + 528) => x"41", (57344 + 529) => x"52", (57344 + 530) => x"45", (57344 + 531) => x"53", (57344 + 532) => x"20", (57344 + 533) => x"80", (57344 + 534) => x"80", (57344 + 535) => x"ff", (57344 + 536) => x"00", (57344 + 537) => x"00", (57344 + 538) => x"63", (57344 + 539) => x"00", (57344 + 540) => x"67", (57344 + 541) => x"00", (57344 + 542) => x"00", (57344 + 543) => x"e0", (57344 + 544) => x"a2", (57344 + 545) => x"17", (57344 + 546) => x"60", (57344 + 547) => x"00", (57344 + 548) => x"61", (57344 + 549) => x"00", (57344 + 550) => x"d0", (57344 + 551) => x"11", (57344 + 552) => x"71", (57344 + 553) => x"ff", (57344 + 554) => x"d0", (57344 + 555) => x"11", (57344 + 556) => x"71", (57344 + 557) => x"01", (57344 + 558) => x"70", (57344 + 559) => x"08", (57344 + 560) => x"30", (57344 + 561) => x"40", (57344 + 562) => x"12", (57344 + 563) => x"26", (57344 + 564) => x"71", (57344 + 565) => x"01", (57344 + 566) => x"a2", (57344 + 567) => x"15", (57344 + 568) => x"d0", (57344 + 569) => x"12", (57344 + 570) => x"70", (57344 + 571) => x"ff", (57344 + 572) => x"d0", (57344 + 573) => x"12", (57344 + 574) => x"70", (57344 + 575) => x"01", (57344 + 576) => x"71", (57344 + 577) => x"02", (57344 + 578) => x"31", (57344 + 579) => x"1f", (57344 + 580) => x"12", (57344 + 581) => x"38", (57344 + 582) => x"60", (57344 + 583) => x"08", (57344 + 584) => x"61", (57344 + 585) => x"10", (57344 + 586) => x"62", (57344 + 587) => x"04", (57344 + 588) => x"64", (57344 + 589) => x"37", (57344 + 590) => x"65", (57344 + 591) => x"0f", (57344 + 592) => x"66", (57344 + 593) => x"02", (57344 + 594) => x"d0", (57344 + 595) => x"11", (57344 + 596) => x"d4", (57344 + 597) => x"51", (57344 + 598) => x"68", (57344 + 599) => x"01", (57344 + 600) => x"e8", (57344 + 601) => x"a1", (57344 + 602) => x"62", (57344 + 603) => x"02", (57344 + 604) => x"68", (57344 + 605) => x"02", (57344 + 606) => x"e8", (57344 + 607) => x"a1", (57344 + 608) => x"62", (57344 + 609) => x"04", (57344 + 610) => x"68", (57344 + 611) => x"07", (57344 + 612) => x"e8", (57344 + 613) => x"a1", (57344 + 614) => x"62", (57344 + 615) => x"01", (57344 + 616) => x"68", (57344 + 617) => x"0a", (57344 + 618) => x"e8", (57344 + 619) => x"a1", (57344 + 620) => x"62", (57344 + 621) => x"03", (57344 + 622) => x"68", (57344 + 623) => x"0b", (57344 + 624) => x"e8", (57344 + 625) => x"a1", (57344 + 626) => x"66", (57344 + 627) => x"02", (57344 + 628) => x"68", (57344 + 629) => x"0f", (57344 + 630) => x"e8", (57344 + 631) => x"a1", (57344 + 632) => x"66", (57344 + 633) => x"04", (57344 + 634) => x"68", (57344 + 635) => x"0c", (57344 + 636) => x"e8", (57344 + 637) => x"a1", (57344 + 638) => x"66", (57344 + 639) => x"01", (57344 + 640) => x"68", (57344 + 641) => x"0d", (57344 + 642) => x"e8", (57344 + 643) => x"a1", (57344 + 644) => x"66", (57344 + 645) => x"03", (57344 + 646) => x"42", (57344 + 647) => x"01", (57344 + 648) => x"71", (57344 + 649) => x"ff", (57344 + 650) => x"42", (57344 + 651) => x"02", (57344 + 652) => x"70", (57344 + 653) => x"ff", (57344 + 654) => x"42", (57344 + 655) => x"03", (57344 + 656) => x"71", (57344 + 657) => x"01", (57344 + 658) => x"42", (57344 + 659) => x"04", (57344 + 660) => x"70", (57344 + 661) => x"01", (57344 + 662) => x"46", (57344 + 663) => x"01", (57344 + 664) => x"75", (57344 + 665) => x"ff", (57344 + 666) => x"46", (57344 + 667) => x"02", (57344 + 668) => x"74", (57344 + 669) => x"ff", (57344 + 670) => x"46", (57344 + 671) => x"03", (57344 + 672) => x"75", (57344 + 673) => x"01", (57344 + 674) => x"46", (57344 + 675) => x"04", (57344 + 676) => x"74", (57344 + 677) => x"01", (57344 + 678) => x"d0", (57344 + 679) => x"11", (57344 + 680) => x"3f", (57344 + 681) => x"00", (57344 + 682) => x"12", (57344 + 683) => x"b4", (57344 + 684) => x"d4", (57344 + 685) => x"51", (57344 + 686) => x"3f", (57344 + 687) => x"00", (57344 + 688) => x"12", (57344 + 689) => x"b8", (57344 + 690) => x"12", (57344 + 691) => x"56", (57344 + 692) => x"77", (57344 + 693) => x"01", (57344 + 694) => x"12", (57344 + 695) => x"ba", (57344 + 696) => x"73", (57344 + 697) => x"01", (57344 + 698) => x"68", (57344 + 699) => x"00", (57344 + 700) => x"78", (57344 + 701) => x"01", (57344 + 702) => x"38", (57344 + 703) => x"00", (57344 + 704) => x"12", (57344 + 705) => x"bc", (57344 + 706) => x"00", (57344 + 707) => x"e0", (57344 + 708) => x"60", (57344 + 709) => x"08", (57344 + 710) => x"61", (57344 + 711) => x"04", (57344 + 712) => x"f3", (57344 + 713) => x"29", (57344 + 714) => x"d0", (57344 + 715) => x"15", (57344 + 716) => x"60", (57344 + 717) => x"34", (57344 + 718) => x"f7", (57344 + 719) => x"29", (57344 + 720) => x"d0", (57344 + 721) => x"15", (57344 + 722) => x"68", (57344 + 723) => x"00", (57344 + 724) => x"78", (57344 + 725) => x"01", (57344 + 726) => x"38", (57344 + 727) => x"00", (57344 + 728) => x"12", (57344 + 729) => x"d4", (57344 + 730) => x"43", (57344 + 731) => x"08", (57344 + 732) => x"12", (57344 + 733) => x"e4", (57344 + 734) => x"47", (57344 + 735) => x"08", (57344 + 736) => x"12", (57344 + 737) => x"e4", (57344 + 738) => x"12", (57344 + 739) => x"1e", (57344 + 740) => x"12", (57344 + 741) => x"e4",
others => ( others => '0')
);
signal read_address : std_logic_vector( 15 downto 0 );
begin
process ( clock )
begin
if ( rising_edge( clock ) ) then
if( we = '1' ) then
sys_RAM( to_integer( unsigned( address ))) <= dataIn;
end if;
read_address <= address;
end if;
end process;
dataOut <= sys_RAM( to_integer( unsigned( read_address )));
end Behavioral;
|
-----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Release Version 13.1
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing device programming or simulation files), and
-- any associated documentation or information are expressly subject to the
-- terms and conditions of the Altera Program License Subscription Agreement,
-- Altera MegaCore Function License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for the sole
-- purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
-----------------------------------------------------------------------------
-- VHDL created from fp_cospi_s5
-- VHDL created on Wed Feb 27 15:22:33 2013
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.all;
use std.TextIO.all;
use work.dspba_library_package.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
entity fp_cospi_s5 is
port (
a : in std_logic_vector(31 downto 0);
en : in std_logic_vector(0 downto 0);
q : out std_logic_vector(31 downto 0);
clk : in std_logic;
areset : in std_logic
);
end;
architecture normal of fp_cospi_s5 is
attribute altera_attribute : string;
attribute altera_attribute of normal : architecture is "-name NOT_GATE_PUSH_BACK OFF; -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON; -name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410";
signal GND_q : std_logic_vector (0 downto 0);
signal VCC_q : std_logic_vector (0 downto 0);
signal cstAllOWE_uid8_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal cstAllZWF_uid9_fpCosPiTest_q : std_logic_vector (22 downto 0);
signal cstBias_uid10_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal cstBiasM1_uid11_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal cstBiasPwF_uid12_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal biasMwShiftMO_uid13_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal cst01pWShift_uid14_fpCosPiTest_q : std_logic_vector (12 downto 0);
signal cstZwSwF_uid15_fpCosPiTest_q : std_logic_vector (34 downto 0);
signal cstAllZWE_uid21_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal rangeReducedFxPX_uid51_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal rangeReducedFxPX_uid51_fpCosPiTest_q : std_logic_vector (35 downto 0);
signal fracRPostExc1_uid86_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal fracRPostExc1_uid86_fpCosPiTest_q : std_logic_vector (22 downto 0);
signal oneFracRPostExc2_uid87_fpCosPiTest_q : std_logic_vector (22 downto 0);
signal expRPostExc1_uid91_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal expRPostExc1_uid91_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal signRComp_uid99_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal signRComp_uid99_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal signRComp_uid99_fpCosPiTest_c : std_logic_vector(0 downto 0);
signal signRComp_uid99_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal signR_uid101_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal signR_uid101_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal signR_uid101_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal leftShiftStage0Idx1Pad16_uid105_fxpX_uid41_fpCosPiTest_q : std_logic_vector (15 downto 0);
signal leftShiftStage0Idx2Pad32_uid108_fxpX_uid41_fpCosPiTest_q : std_logic_vector (31 downto 0);
signal leftShiftStage0Idx3_uid111_fxpX_uid41_fpCosPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage1Idx1Pad4_uid114_fxpX_uid41_fpCosPiTest_q : std_logic_vector (3 downto 0);
signal leftShiftStage1Idx3Pad12_uid120_fxpX_uid41_fpCosPiTest_q : std_logic_vector (11 downto 0);
signal leftShiftStage2Idx2Pad2_uid128_fxpX_uid41_fpCosPiTest_q : std_logic_vector (1 downto 0);
signal leftShiftStage2Idx3Pad3_uid131_fxpX_uid41_fpCosPiTest_q : std_logic_vector (2 downto 0);
signal mO_uid140_lzcZ_uid56_fpCosPiTest_q : std_logic_vector (28 downto 0);
signal memoryC2_uid209_sinPiZTableGenerator_q : std_logic_vector(13 downto 0);
signal prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_a : std_logic_vector (23 downto 0);
signal prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_b : std_logic_vector (24 downto 0);
signal prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_s1 : std_logic_vector (48 downto 0);
signal prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_pr : UNSIGNED (48 downto 0);
signal prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_q : std_logic_vector (48 downto 0);
signal prodXY_uid226_pT1_uid211_sinPiZPolyEval_a : std_logic_vector (13 downto 0);
signal prodXY_uid226_pT1_uid211_sinPiZPolyEval_b : std_logic_vector (13 downto 0);
signal prodXY_uid226_pT1_uid211_sinPiZPolyEval_s1 : std_logic_vector (27 downto 0);
signal prodXY_uid226_pT1_uid211_sinPiZPolyEval_pr : SIGNED (28 downto 0);
signal prodXY_uid226_pT1_uid211_sinPiZPolyEval_q : std_logic_vector (27 downto 0);
signal prodXY_uid229_pT2_uid217_sinPiZPolyEval_a : std_logic_vector (15 downto 0);
signal prodXY_uid229_pT2_uid217_sinPiZPolyEval_b : std_logic_vector (22 downto 0);
signal prodXY_uid229_pT2_uid217_sinPiZPolyEval_s1 : std_logic_vector (38 downto 0);
signal prodXY_uid229_pT2_uid217_sinPiZPolyEval_pr : SIGNED (39 downto 0);
signal prodXY_uid229_pT2_uid217_sinPiZPolyEval_q : std_logic_vector (38 downto 0);
signal reg_leftShiftStageSel3Dto2_uid123_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_2_q : std_logic_vector (36 downto 0);
signal reg_leftShiftStage1Idx1_uid116_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_3_q : std_logic_vector (36 downto 0);
signal reg_leftShiftStage1Idx2_uid119_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_4_q : std_logic_vector (36 downto 0);
signal reg_leftShiftStage1Idx3_uid122_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_5_q : std_logic_vector (36 downto 0);
signal reg_leftShiftStageSel1Dto0_uid134_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_fxpXFrac_uid43_fpCosPiTest_0_to_fxpXFracZero_uid45_fpCosPiTest_1_q : std_logic_vector (35 downto 0);
signal reg_cosXIsOne_uid36_fpCosPiTest_1_to_bigCond_uid85_fpCosPiTest_1_q : std_logic_vector (0 downto 0);
signal reg_xIsInt_uid80_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_2_q : std_logic_vector (0 downto 0);
signal reg_fxpXFracHalf_uid46_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_3_q : std_logic_vector (0 downto 0);
signal reg_expXIsZero_uid23_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_4_q : std_logic_vector (0 downto 0);
signal reg_xIsHalf_uid83_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_5_q : std_logic_vector (0 downto 0);
signal reg_pad_o_uid16_uid47_fpCosPiTest_0_to_oMFxpXFrac_uid47_fpCosPiTest_0_q : std_logic_vector (36 downto 0);
signal reg_pad_half_uid17_uid52_fpCosPiTest_0_to_z_halfMRRFxPXE_uid52_fpCosPiTest_0_q : std_logic_vector (35 downto 0);
signal reg_rVStage_uid138_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid139_lzcZ_uid56_fpCosPiTest_1_q : std_logic_vector (31 downto 0);
signal reg_cStage_uid142_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid144_lzcZ_uid56_fpCosPiTest_3_q : std_logic_vector (31 downto 0);
signal reg_rVStage_uid146_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid147_lzcZ_uid56_fpCosPiTest_1_q : std_logic_vector (15 downto 0);
signal reg_vStage_uid148_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid150_lzcZ_uid56_fpCosPiTest_3_q : std_logic_vector (15 downto 0);
signal reg_rVStage_uid158_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid159_lzcZ_uid56_fpCosPiTest_1_q : std_logic_vector (3 downto 0);
signal reg_vStage_uid160_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid162_lzcZ_uid56_fpCosPiTest_3_q : std_logic_vector (3 downto 0);
signal reg_vCount_uid153_lzcZ_uid56_fpCosPiTest_0_to_r_uid172_lzcZ_uid56_fpCosPiTest_3_q : std_logic_vector (0 downto 0);
signal reg_leftShiftStageSel3Dto2_uid193_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_2_q : std_logic_vector (34 downto 0);
signal reg_leftShiftStage1Idx1_uid186_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_3_q : std_logic_vector (34 downto 0);
signal reg_leftShiftStage1Idx2_uid189_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_4_q : std_logic_vector (34 downto 0);
signal reg_leftShiftStage1Idx3_uid192_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_5_q : std_logic_vector (34 downto 0);
signal reg_leftShiftStageSel1Dto0_uid204_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_zAddr_uid62_fpCosPiTest_0_to_memoryC2_uid209_sinPiZTableGenerator_0_q : std_logic_vector (6 downto 0);
signal reg_yT1_uid210_sinPiZPolyEval_0_to_prodXY_uid226_pT1_uid211_sinPiZPolyEval_0_q : std_logic_vector (13 downto 0);
signal reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_q : std_logic_vector (15 downto 0);
signal reg_s1_uid212_uid215_sinPiZPolyEval_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_1_q : std_logic_vector (22 downto 0);
signal reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_q : std_logic_vector (23 downto 0);
signal reg_fxpSinRes_uid65_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_1_q : std_logic_vector (24 downto 0);
signal reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q : std_logic_vector (5 downto 0);
signal reg_expP_uid60_fpCosPiTest_0_to_expFracPreRnd_uid71_uid71_fpCosPiTest_1_q : std_logic_vector (7 downto 0);
signal reg_excRNaN_uid84_fpCosPiTest_0_to_fracRPostExc_uid88_fpCosPiTest_1_q : std_logic_vector (0 downto 0);
signal reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q : std_logic_vector (1 downto 0);
signal ld_FxpXFrac35_uid44_fpCosPiTest_b_to_rangeReducedFxPX_uid51_fpCosPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_fxpXFrac_uid43_fpCosPiTest_b_to_rangeReducedFxPX_uid51_fpCosPiTest_c_q : std_logic_vector (35 downto 0);
signal ld_cosXIsOne_uid36_fpCosPiTest_c_to_InvCosXIsOne_uid77_fpCosPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_xEvenInt_uid35_fpCosPiTest_c_to_evenIntCosNotOneFZ_uid79_fpCosPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_exc_R_uid34_fpCosPiTest_q_to_xIsInt_uid80_fpCosPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_reg_cosXIsOne_uid36_fpCosPiTest_1_to_bigCond_uid85_fpCosPiTest_1_q_to_bigCond_uid85_fpCosPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_bigCond_uid85_fpCosPiTest_q_to_fracRPostExc1_uid86_fpCosPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_reg_excRNaN_uid84_fpCosPiTest_0_to_fracRPostExc_uid88_fpCosPiTest_1_q_to_fracRPostExc_uid88_fpCosPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_xIsHalf_uid83_fpCosPiTest_q_to_expRPostExc1_uid91_fpCosPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_expXIsZero_uid23_fpCosPiTest_q_to_xIntOrXZOrCosOne_uid93_fpCosPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_rInfOrNaN_uid92_fpCosPiTest_q_to_join_uid94_fpCosPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_xParityXorHalfParity_uid96_fpCosPiTest_q_to_signRComp_uid99_fpCosPiTest_c_q : std_logic_vector (0 downto 0);
signal ld_fxpXFracHalf_uid46_fpCosPiTest_q_to_InvFxpXFracHalf_uid100_fpCosPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_signR_uid101_fpCosPiTest_q_to_R_uid102_fpCosPiTest_c_q : std_logic_vector (0 downto 0);
signal ld_vCount_uid147_lzcZ_uid56_fpCosPiTest_q_to_r_uid172_lzcZ_uid56_fpCosPiTest_e_q : std_logic_vector (0 downto 0);
signal ld_vCount_uid139_lzcZ_uid56_fpCosPiTest_q_to_r_uid172_lzcZ_uid56_fpCosPiTest_f_q : std_logic_vector (0 downto 0);
signal ld_X18dto0_uid176_alignedZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx1_uid177_alignedZ_uid57_fpCosPiTest_b_q : std_logic_vector (18 downto 0);
signal ld_vStage_uid141_lzcZ_uid56_fpCosPiTest_b_to_leftShiftStage0Idx2_uid180_alignedZ_uid57_fpCosPiTest_b_q : std_logic_vector (2 downto 0);
signal ld_z_uid54_fpCosPiTest_b_to_leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_c_q : std_logic_vector (34 downto 0);
signal ld_reg_yT1_uid210_sinPiZPolyEval_0_to_prodXY_uid226_pT1_uid211_sinPiZPolyEval_0_q_to_prodXY_uid226_pT1_uid211_sinPiZPolyEval_a_q : std_logic_vector (13 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_reset0 : std_logic;
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_ia : std_logic_vector (5 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_iq : std_logic_vector (5 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_q : std_logic_vector (5 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt_eq : std_logic;
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_mem_top_q : std_logic_vector (3 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve : boolean;
attribute preserve of ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_sticky_ena_q : signal is true;
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_reset0 : std_logic;
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_ia : std_logic_vector (1 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_iq : std_logic_vector (1 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_q : std_logic_vector (1 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt_eq : std_logic;
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_mem_top_q : std_logic_vector (4 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_sticky_ena_q : signal is true;
signal ld_X18dto0_uid176_alignedZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx1_uid177_alignedZ_uid57_fpCosPiTest_b_inputreg_q : std_logic_vector (18 downto 0);
signal ld_z_uid54_fpCosPiTest_b_to_leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_c_inputreg_q : std_logic_vector (34 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_reset0 : std_logic;
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_ia : std_logic_vector (6 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_iq : std_logic_vector (6 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_q : std_logic_vector (6 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_sticky_ena_q : signal is true;
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_reset0 : std_logic;
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_ia : std_logic_vector (6 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_aa : std_logic_vector (1 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_ab : std_logic_vector (1 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_iq : std_logic_vector (6 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_q : std_logic_vector (6 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt_q : std_logic_vector(1 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt_i : unsigned(1 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt_eq : std_logic;
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdreg_q : std_logic_vector (1 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_mem_top_q : std_logic_vector (2 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_sticky_ena_q : signal is true;
signal ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_inputreg_q : std_logic_vector (15 downto 0);
signal ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_reset0 : std_logic;
signal ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_ia : std_logic_vector (15 downto 0);
signal ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_aa : std_logic_vector (1 downto 0);
signal ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_ab : std_logic_vector (1 downto 0);
signal ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_iq : std_logic_vector (15 downto 0);
signal ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_q : std_logic_vector (15 downto 0);
signal ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_sticky_ena_q : signal is true;
signal ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_inputreg_q : std_logic_vector (23 downto 0);
signal ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_reset0 : std_logic;
signal ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_ia : std_logic_vector (23 downto 0);
signal ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_aa : std_logic_vector (1 downto 0);
signal ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_ab : std_logic_vector (1 downto 0);
signal ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_iq : std_logic_vector (23 downto 0);
signal ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_q : std_logic_vector (23 downto 0);
signal ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_sticky_ena_q : signal is true;
signal pad_o_uid16_uid47_fpCosPiTest_q : std_logic_vector (36 downto 0);
signal pad_half_uid17_uid52_fpCosPiTest_q : std_logic_vector (35 downto 0);
signal bigCond_uid85_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal bigCond_uid85_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal bigCond_uid85_fpCosPiTest_c : std_logic_vector(0 downto 0);
signal bigCond_uid85_fpCosPiTest_d : std_logic_vector(0 downto 0);
signal bigCond_uid85_fpCosPiTest_f : std_logic_vector(0 downto 0);
signal bigCond_uid85_fpCosPiTest_g : std_logic_vector(0 downto 0);
signal bigCond_uid85_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal InvCosXIsOne_uid77_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal InvCosXIsOne_uid77_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal InvXEvenInt_uid81_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal InvXEvenInt_uid81_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal InvFxpXFracHalf_uid100_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal InvFxpXFracHalf_uid100_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal cstHalfwSwFP1_uid18_fpCosPiTest_q : std_logic_vector (35 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_notEnable_a : std_logic_vector(0 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_notEnable_q : std_logic_vector(0 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdmux_q : std_logic_vector (1 downto 0);
signal expX_uid6_fpCosPiTest_in : std_logic_vector (30 downto 0);
signal expX_uid6_fpCosPiTest_b : std_logic_vector (7 downto 0);
signal fracX_uid7_fpCosPiTest_in : std_logic_vector (22 downto 0);
signal fracX_uid7_fpCosPiTest_b : std_logic_vector (22 downto 0);
signal expXIsZero_uid23_fpCosPiTest_a : std_logic_vector(7 downto 0);
signal expXIsZero_uid23_fpCosPiTest_b : std_logic_vector(7 downto 0);
signal expXIsZero_uid23_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal expXIsMax_uid25_fpCosPiTest_a : std_logic_vector(7 downto 0);
signal expXIsMax_uid25_fpCosPiTest_b : std_logic_vector(7 downto 0);
signal expXIsMax_uid25_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal fracXIsZero_uid27_fpCosPiTest_a : std_logic_vector(22 downto 0);
signal fracXIsZero_uid27_fpCosPiTest_b : std_logic_vector(22 downto 0);
signal fracXIsZero_uid27_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal exc_I_uid28_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal exc_I_uid28_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal exc_I_uid28_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal xEvenInt_uid35_fpCosPiTest_a : std_logic_vector(10 downto 0);
signal xEvenInt_uid35_fpCosPiTest_b : std_logic_vector(10 downto 0);
signal xEvenInt_uid35_fpCosPiTest_o : std_logic_vector (10 downto 0);
signal xEvenInt_uid35_fpCosPiTest_cin : std_logic_vector (0 downto 0);
signal xEvenInt_uid35_fpCosPiTest_c : std_logic_vector (0 downto 0);
signal cosXIsOne_uid36_fpCosPiTest_a : std_logic_vector(10 downto 0);
signal cosXIsOne_uid36_fpCosPiTest_b : std_logic_vector(10 downto 0);
signal cosXIsOne_uid36_fpCosPiTest_o : std_logic_vector (10 downto 0);
signal cosXIsOne_uid36_fpCosPiTest_cin : std_logic_vector (0 downto 0);
signal cosXIsOne_uid36_fpCosPiTest_c : std_logic_vector (0 downto 0);
signal shiftValFxPX_uid38_fpCosPiTest_a : std_logic_vector(8 downto 0);
signal shiftValFxPX_uid38_fpCosPiTest_b : std_logic_vector(8 downto 0);
signal shiftValFxPX_uid38_fpCosPiTest_o : std_logic_vector (8 downto 0);
signal shiftValFxPX_uid38_fpCosPiTest_q : std_logic_vector (8 downto 0);
signal fxpXFracZero_uid45_fpCosPiTest_a : std_logic_vector(35 downto 0);
signal fxpXFracZero_uid45_fpCosPiTest_b : std_logic_vector(35 downto 0);
signal fxpXFracZero_uid45_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal fxpXFracHalf_uid46_fpCosPiTest_a : std_logic_vector(35 downto 0);
signal fxpXFracHalf_uid46_fpCosPiTest_b : std_logic_vector(35 downto 0);
signal fxpXFracHalf_uid46_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal oMFxpXFrac_uid47_fpCosPiTest_a : std_logic_vector(37 downto 0);
signal oMFxpXFrac_uid47_fpCosPiTest_b : std_logic_vector(37 downto 0);
signal oMFxpXFrac_uid47_fpCosPiTest_o : std_logic_vector (37 downto 0);
signal oMFxpXFrac_uid47_fpCosPiTest_q : std_logic_vector (37 downto 0);
signal z_halfMRRFxPXE_uid52_fpCosPiTest_a : std_logic_vector(36 downto 0);
signal z_halfMRRFxPXE_uid52_fpCosPiTest_b : std_logic_vector(36 downto 0);
signal z_halfMRRFxPXE_uid52_fpCosPiTest_o : std_logic_vector (36 downto 0);
signal z_halfMRRFxPXE_uid52_fpCosPiTest_q : std_logic_vector (36 downto 0);
signal expHardCase_uid59_fpCosPiTest_a : std_logic_vector(8 downto 0);
signal expHardCase_uid59_fpCosPiTest_b : std_logic_vector(8 downto 0);
signal expHardCase_uid59_fpCosPiTest_o : std_logic_vector (8 downto 0);
signal expHardCase_uid59_fpCosPiTest_q : std_logic_vector (8 downto 0);
signal fracZCosNotOne_uid78_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal fracZCosNotOne_uid78_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal fracZCosNotOne_uid78_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal evenIntCosNotOneFZ_uid79_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal evenIntCosNotOneFZ_uid79_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal evenIntCosNotOneFZ_uid79_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal xIsInt_uid80_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal xIsInt_uid80_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal xIsInt_uid80_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal xIsHalf_uid83_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal xIsHalf_uid83_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal xIsHalf_uid83_fpCosPiTest_c : std_logic_vector(0 downto 0);
signal xIsHalf_uid83_fpCosPiTest_d : std_logic_vector(0 downto 0);
signal xIsHalf_uid83_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal fracRPostExc_uid88_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal fracRPostExc_uid88_fpCosPiTest_q : std_logic_vector (22 downto 0);
signal xIntOrXZOrCosOne_uid93_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal xIntOrXZOrCosOne_uid93_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal xIntOrXZOrCosOne_uid93_fpCosPiTest_c : std_logic_vector(0 downto 0);
signal xIntOrXZOrCosOne_uid93_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal expRPostExc_uid95_fpCosPiTest_s : std_logic_vector (1 downto 0);
signal expRPostExc_uid95_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_q : std_logic_vector (36 downto 0);
signal vCount_uid139_lzcZ_uid56_fpCosPiTest_a : std_logic_vector(31 downto 0);
signal vCount_uid139_lzcZ_uid56_fpCosPiTest_b : std_logic_vector(31 downto 0);
signal vCount_uid139_lzcZ_uid56_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid144_lzcZ_uid56_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid144_lzcZ_uid56_fpCosPiTest_q : std_logic_vector (31 downto 0);
signal vCount_uid147_lzcZ_uid56_fpCosPiTest_a : std_logic_vector(15 downto 0);
signal vCount_uid147_lzcZ_uid56_fpCosPiTest_b : std_logic_vector(15 downto 0);
signal vCount_uid147_lzcZ_uid56_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid150_lzcZ_uid56_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid150_lzcZ_uid56_fpCosPiTest_q : std_logic_vector (15 downto 0);
signal vCount_uid159_lzcZ_uid56_fpCosPiTest_a : std_logic_vector(3 downto 0);
signal vCount_uid159_lzcZ_uid56_fpCosPiTest_b : std_logic_vector(3 downto 0);
signal vCount_uid159_lzcZ_uid56_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid162_lzcZ_uid56_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid162_lzcZ_uid56_fpCosPiTest_q : std_logic_vector (3 downto 0);
signal leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_q : std_logic_vector (34 downto 0);
signal memoryC0_uid207_sinPiZTableGenerator_q : std_logic_vector(28 downto 0);
signal memoryC1_uid208_sinPiZTableGenerator_q : std_logic_vector(20 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal leftShiftStage0Idx1_uid177_alignedZ_uid57_fpCosPiTest_q : std_logic_vector (34 downto 0);
signal leftShiftStage0Idx2_uid180_alignedZ_uid57_fpCosPiTest_q : std_logic_vector (34 downto 0);
signal prodXYTruncFR_uid224_mul2xSinRes_uid66_fpCosPiTest_in : std_logic_vector (48 downto 0);
signal prodXYTruncFR_uid224_mul2xSinRes_uid66_fpCosPiTest_b : std_logic_vector (25 downto 0);
signal prodXYTruncFR_uid227_pT1_uid211_sinPiZPolyEval_in : std_logic_vector (27 downto 0);
signal prodXYTruncFR_uid227_pT1_uid211_sinPiZPolyEval_b : std_logic_vector (14 downto 0);
signal prodXYTruncFR_uid230_pT2_uid217_sinPiZPolyEval_in : std_logic_vector (38 downto 0);
signal prodXYTruncFR_uid230_pT2_uid217_sinPiZPolyEval_b : std_logic_vector (23 downto 0);
signal join_uid94_fpCosPiTest_q : std_logic_vector (1 downto 0);
signal R_uid102_fpCosPiTest_q : std_logic_vector (31 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_cmp_a : std_logic_vector(3 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_cmp_b : std_logic_vector(3 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_cmp_a : std_logic_vector(4 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_cmp_b : std_logic_vector(4 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_cmp_a : std_logic_vector(2 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_cmp_b : std_logic_vector(2 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_nor_q : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_nor_q : std_logic_vector(0 downto 0);
signal oFracX_uid37_uid37_fpCosPiTest_q : std_logic_vector (23 downto 0);
signal InvExpXIsZero_uid33_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid33_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid29_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid29_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal InvExc_I_uid32_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal InvExc_I_uid32_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal fxpShifterBits_uid40_fpCosPiTest_in : std_logic_vector (5 downto 0);
signal fxpShifterBits_uid40_fpCosPiTest_b : std_logic_vector (5 downto 0);
signal oMFxpXFrac_uid49_fpCosPiTest_in : std_logic_vector (35 downto 0);
signal oMFxpXFrac_uid49_fpCosPiTest_b : std_logic_vector (35 downto 0);
signal z_uid54_fpCosPiTest_in : std_logic_vector (34 downto 0);
signal z_uid54_fpCosPiTest_b : std_logic_vector (34 downto 0);
signal expP_uid60_fpCosPiTest_in : std_logic_vector (7 downto 0);
signal expP_uid60_fpCosPiTest_b : std_logic_vector (7 downto 0);
signal LeftShiftStage135dto0_uid126_fxpX_uid41_fpCosPiTest_in : std_logic_vector (35 downto 0);
signal LeftShiftStage135dto0_uid126_fxpX_uid41_fpCosPiTest_b : std_logic_vector (35 downto 0);
signal LeftShiftStage134dto0_uid129_fxpX_uid41_fpCosPiTest_in : std_logic_vector (34 downto 0);
signal LeftShiftStage134dto0_uid129_fxpX_uid41_fpCosPiTest_b : std_logic_vector (34 downto 0);
signal LeftShiftStage133dto0_uid132_fxpX_uid41_fpCosPiTest_in : std_logic_vector (33 downto 0);
signal LeftShiftStage133dto0_uid132_fxpX_uid41_fpCosPiTest_b : std_logic_vector (33 downto 0);
signal rVStage_uid146_lzcZ_uid56_fpCosPiTest_in : std_logic_vector (31 downto 0);
signal rVStage_uid146_lzcZ_uid56_fpCosPiTest_b : std_logic_vector (15 downto 0);
signal vStage_uid148_lzcZ_uid56_fpCosPiTest_in : std_logic_vector (15 downto 0);
signal vStage_uid148_lzcZ_uid56_fpCosPiTest_b : std_logic_vector (15 downto 0);
signal rVStage_uid152_lzcZ_uid56_fpCosPiTest_in : std_logic_vector (15 downto 0);
signal rVStage_uid152_lzcZ_uid56_fpCosPiTest_b : std_logic_vector (7 downto 0);
signal vStage_uid154_lzcZ_uid56_fpCosPiTest_in : std_logic_vector (7 downto 0);
signal vStage_uid154_lzcZ_uid56_fpCosPiTest_b : std_logic_vector (7 downto 0);
signal rVStage_uid164_lzcZ_uid56_fpCosPiTest_in : std_logic_vector (3 downto 0);
signal rVStage_uid164_lzcZ_uid56_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal vStage_uid166_lzcZ_uid56_fpCosPiTest_in : std_logic_vector (1 downto 0);
signal vStage_uid166_lzcZ_uid56_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal LeftShiftStage133dto0_uid196_alignedZ_uid57_fpCosPiTest_in : std_logic_vector (33 downto 0);
signal LeftShiftStage133dto0_uid196_alignedZ_uid57_fpCosPiTest_b : std_logic_vector (33 downto 0);
signal LeftShiftStage132dto0_uid199_alignedZ_uid57_fpCosPiTest_in : std_logic_vector (32 downto 0);
signal LeftShiftStage132dto0_uid199_alignedZ_uid57_fpCosPiTest_b : std_logic_vector (32 downto 0);
signal LeftShiftStage131dto0_uid202_alignedZ_uid57_fpCosPiTest_in : std_logic_vector (31 downto 0);
signal LeftShiftStage131dto0_uid202_alignedZ_uid57_fpCosPiTest_b : std_logic_vector (31 downto 0);
signal normBit_uid67_fpCosPiTest_in : std_logic_vector (25 downto 0);
signal normBit_uid67_fpCosPiTest_b : std_logic_vector (0 downto 0);
signal highRes_uid68_fpCosPiTest_in : std_logic_vector (24 downto 0);
signal highRes_uid68_fpCosPiTest_b : std_logic_vector (23 downto 0);
signal lowRes_uid69_fpCosPiTest_in : std_logic_vector (23 downto 0);
signal lowRes_uid69_fpCosPiTest_b : std_logic_vector (23 downto 0);
signal lowRangeB_uid212_sinPiZPolyEval_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid212_sinPiZPolyEval_b : std_logic_vector (0 downto 0);
signal highBBits_uid213_sinPiZPolyEval_in : std_logic_vector (14 downto 0);
signal highBBits_uid213_sinPiZPolyEval_b : std_logic_vector (13 downto 0);
signal lowRangeB_uid218_sinPiZPolyEval_in : std_logic_vector (1 downto 0);
signal lowRangeB_uid218_sinPiZPolyEval_b : std_logic_vector (1 downto 0);
signal highBBits_uid219_sinPiZPolyEval_in : std_logic_vector (23 downto 0);
signal highBBits_uid219_sinPiZPolyEval_b : std_logic_vector (21 downto 0);
signal oFracXExt_uid39_fpCosPiTest_q : std_logic_vector (36 downto 0);
signal exc_N_uid30_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal exc_N_uid30_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal exc_N_uid30_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal leftShiftStageSel5Dto4_uid112_fxpX_uid41_fpCosPiTest_in : std_logic_vector (5 downto 0);
signal leftShiftStageSel5Dto4_uid112_fxpX_uid41_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel3Dto2_uid123_fxpX_uid41_fpCosPiTest_in : std_logic_vector (3 downto 0);
signal leftShiftStageSel3Dto2_uid123_fxpX_uid41_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid134_fxpX_uid41_fpCosPiTest_in : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid134_fxpX_uid41_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal zAddr_uid62_fpCosPiTest_in : std_logic_vector (34 downto 0);
signal zAddr_uid62_fpCosPiTest_b : std_logic_vector (6 downto 0);
signal zPPolyEval_uid63_fpCosPiTest_in : std_logic_vector (27 downto 0);
signal zPPolyEval_uid63_fpCosPiTest_b : std_logic_vector (15 downto 0);
signal rVStage_uid138_lzcZ_uid56_fpCosPiTest_in : std_logic_vector (34 downto 0);
signal rVStage_uid138_lzcZ_uid56_fpCosPiTest_b : std_logic_vector (31 downto 0);
signal vStage_uid141_lzcZ_uid56_fpCosPiTest_in : std_logic_vector (2 downto 0);
signal vStage_uid141_lzcZ_uid56_fpCosPiTest_b : std_logic_vector (2 downto 0);
signal X18dto0_uid176_alignedZ_uid57_fpCosPiTest_in : std_logic_vector (18 downto 0);
signal X18dto0_uid176_alignedZ_uid57_fpCosPiTest_b : std_logic_vector (18 downto 0);
signal leftShiftStage2Idx1_uid127_fxpX_uid41_fpCosPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage2Idx2_uid130_fxpX_uid41_fpCosPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage2Idx3_uid133_fxpX_uid41_fpCosPiTest_q : std_logic_vector (36 downto 0);
signal vCount_uid153_lzcZ_uid56_fpCosPiTest_a : std_logic_vector(7 downto 0);
signal vCount_uid153_lzcZ_uid56_fpCosPiTest_b : std_logic_vector(7 downto 0);
signal vCount_uid153_lzcZ_uid56_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid156_lzcZ_uid56_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid156_lzcZ_uid56_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal vCount_uid165_lzcZ_uid56_fpCosPiTest_a : std_logic_vector(1 downto 0);
signal vCount_uid165_lzcZ_uid56_fpCosPiTest_b : std_logic_vector(1 downto 0);
signal vCount_uid165_lzcZ_uid56_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid168_lzcZ_uid56_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid168_lzcZ_uid56_fpCosPiTest_q : std_logic_vector (1 downto 0);
signal leftShiftStage2Idx1_uid197_alignedZ_uid57_fpCosPiTest_q : std_logic_vector (34 downto 0);
signal leftShiftStage2Idx2_uid200_alignedZ_uid57_fpCosPiTest_q : std_logic_vector (34 downto 0);
signal leftShiftStage2Idx3_uid203_alignedZ_uid57_fpCosPiTest_q : std_logic_vector (34 downto 0);
signal fracRCompPreRnd_uid70_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal fracRCompPreRnd_uid70_fpCosPiTest_q : std_logic_vector (23 downto 0);
signal rndExpUpdate_uid72_uid73_fpCosPiTest_q : std_logic_vector (24 downto 0);
signal sumAHighB_uid214_sinPiZPolyEval_a : std_logic_vector(21 downto 0);
signal sumAHighB_uid214_sinPiZPolyEval_b : std_logic_vector(21 downto 0);
signal sumAHighB_uid214_sinPiZPolyEval_o : std_logic_vector (21 downto 0);
signal sumAHighB_uid214_sinPiZPolyEval_q : std_logic_vector (21 downto 0);
signal sumAHighB_uid220_sinPiZPolyEval_a : std_logic_vector(29 downto 0);
signal sumAHighB_uid220_sinPiZPolyEval_b : std_logic_vector(29 downto 0);
signal sumAHighB_uid220_sinPiZPolyEval_o : std_logic_vector (29 downto 0);
signal sumAHighB_uid220_sinPiZPolyEval_q : std_logic_vector (29 downto 0);
signal X20dto0_uid106_fxpX_uid41_fpCosPiTest_in : std_logic_vector (20 downto 0);
signal X20dto0_uid106_fxpX_uid41_fpCosPiTest_b : std_logic_vector (20 downto 0);
signal X4dto0_uid109_fxpX_uid41_fpCosPiTest_in : std_logic_vector (4 downto 0);
signal X4dto0_uid109_fxpX_uid41_fpCosPiTest_b : std_logic_vector (4 downto 0);
signal InvExc_N_uid31_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal InvExc_N_uid31_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal excRNaN_uid84_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal excRNaN_uid84_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal excRNaN_uid84_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal yT1_uid210_sinPiZPolyEval_in : std_logic_vector (15 downto 0);
signal yT1_uid210_sinPiZPolyEval_b : std_logic_vector (13 downto 0);
signal cStage_uid142_lzcZ_uid56_fpCosPiTest_q : std_logic_vector (31 downto 0);
signal leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest_q : std_logic_vector (36 downto 0);
signal rVStage_uid158_lzcZ_uid56_fpCosPiTest_in : std_logic_vector (7 downto 0);
signal rVStage_uid158_lzcZ_uid56_fpCosPiTest_b : std_logic_vector (3 downto 0);
signal vStage_uid160_lzcZ_uid56_fpCosPiTest_in : std_logic_vector (3 downto 0);
signal vStage_uid160_lzcZ_uid56_fpCosPiTest_b : std_logic_vector (3 downto 0);
signal rVStage_uid170_lzcZ_uid56_fpCosPiTest_in : std_logic_vector (1 downto 0);
signal rVStage_uid170_lzcZ_uid56_fpCosPiTest_b : std_logic_vector (0 downto 0);
signal leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest_q : std_logic_vector (34 downto 0);
signal expFracPreRnd_uid71_uid71_fpCosPiTest_q : std_logic_vector (31 downto 0);
signal expFracComp_uid74_fpCosPiTest_a : std_logic_vector(32 downto 0);
signal expFracComp_uid74_fpCosPiTest_b : std_logic_vector(32 downto 0);
signal expFracComp_uid74_fpCosPiTest_o : std_logic_vector (32 downto 0);
signal expFracComp_uid74_fpCosPiTest_q : std_logic_vector (32 downto 0);
signal s1_uid212_uid215_sinPiZPolyEval_q : std_logic_vector (22 downto 0);
signal s2_uid218_uid221_sinPiZPolyEval_q : std_logic_vector (31 downto 0);
signal leftShiftStage0Idx1_uid107_fxpX_uid41_fpCosPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage0Idx2_uid110_fxpX_uid41_fpCosPiTest_q : std_logic_vector (36 downto 0);
signal exc_R_uid34_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal exc_R_uid34_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal exc_R_uid34_fpCosPiTest_c : std_logic_vector(0 downto 0);
signal exc_R_uid34_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal rInfOrNaN_uid92_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal rInfOrNaN_uid92_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal rInfOrNaN_uid92_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal FxpX36_uid42_fpCosPiTest_in : std_logic_vector (36 downto 0);
signal FxpX36_uid42_fpCosPiTest_b : std_logic_vector (0 downto 0);
signal fxpXFrac_uid43_fpCosPiTest_in : std_logic_vector (35 downto 0);
signal fxpXFrac_uid43_fpCosPiTest_b : std_logic_vector (35 downto 0);
signal vCount_uid171_lzcZ_uid56_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal vCount_uid171_lzcZ_uid56_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal vCount_uid171_lzcZ_uid56_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal alignedZLow_uid58_fpCosPiTest_in : std_logic_vector (34 downto 0);
signal alignedZLow_uid58_fpCosPiTest_b : std_logic_vector (23 downto 0);
signal fracRComp_uid75_fpCosPiTest_in : std_logic_vector (23 downto 0);
signal fracRComp_uid75_fpCosPiTest_b : std_logic_vector (22 downto 0);
signal expRComp_uid76_fpCosPiTest_in : std_logic_vector (31 downto 0);
signal expRComp_uid76_fpCosPiTest_b : std_logic_vector (7 downto 0);
signal fxpSinRes_uid65_fpCosPiTest_in : std_logic_vector (29 downto 0);
signal fxpSinRes_uid65_fpCosPiTest_b : std_logic_vector (24 downto 0);
signal leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_q : std_logic_vector (36 downto 0);
signal FxpXFrac35_uid44_fpCosPiTest_in : std_logic_vector (35 downto 0);
signal FxpXFrac35_uid44_fpCosPiTest_b : std_logic_vector (0 downto 0);
signal r_uid172_lzcZ_uid56_fpCosPiTest_q : std_logic_vector (5 downto 0);
signal LeftShiftStage032dto0_uid115_fxpX_uid41_fpCosPiTest_in : std_logic_vector (32 downto 0);
signal LeftShiftStage032dto0_uid115_fxpX_uid41_fpCosPiTest_b : std_logic_vector (32 downto 0);
signal LeftShiftStage028dto0_uid118_fxpX_uid41_fpCosPiTest_in : std_logic_vector (28 downto 0);
signal LeftShiftStage028dto0_uid118_fxpX_uid41_fpCosPiTest_b : std_logic_vector (28 downto 0);
signal LeftShiftStage024dto0_uid121_fxpX_uid41_fpCosPiTest_in : std_logic_vector (24 downto 0);
signal LeftShiftStage024dto0_uid121_fxpX_uid41_fpCosPiTest_b : std_logic_vector (24 downto 0);
signal xParityXorHalfParity_uid96_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal xParityXorHalfParity_uid96_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal xParityXorHalfParity_uid96_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal leftShiftStageSel5Dto4_uid182_alignedZ_uid57_fpCosPiTest_in : std_logic_vector (5 downto 0);
signal leftShiftStageSel5Dto4_uid182_alignedZ_uid57_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel3Dto2_uid193_alignedZ_uid57_fpCosPiTest_in : std_logic_vector (3 downto 0);
signal leftShiftStageSel3Dto2_uid193_alignedZ_uid57_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid204_alignedZ_uid57_fpCosPiTest_in : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid204_alignedZ_uid57_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStage1Idx1_uid116_fxpX_uid41_fpCosPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage1Idx2_uid119_fxpX_uid41_fpCosPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage1Idx3_uid122_fxpX_uid41_fpCosPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_q : std_logic_vector (34 downto 0);
signal LeftShiftStage030dto0_uid185_alignedZ_uid57_fpCosPiTest_in : std_logic_vector (30 downto 0);
signal LeftShiftStage030dto0_uid185_alignedZ_uid57_fpCosPiTest_b : std_logic_vector (30 downto 0);
signal LeftShiftStage026dto0_uid188_alignedZ_uid57_fpCosPiTest_in : std_logic_vector (26 downto 0);
signal LeftShiftStage026dto0_uid188_alignedZ_uid57_fpCosPiTest_b : std_logic_vector (26 downto 0);
signal LeftShiftStage022dto0_uid191_alignedZ_uid57_fpCosPiTest_in : std_logic_vector (22 downto 0);
signal LeftShiftStage022dto0_uid191_alignedZ_uid57_fpCosPiTest_b : std_logic_vector (22 downto 0);
signal leftShiftStage1Idx1_uid186_alignedZ_uid57_fpCosPiTest_q : std_logic_vector (34 downto 0);
signal leftShiftStage1Idx2_uid189_alignedZ_uid57_fpCosPiTest_q : std_logic_vector (34 downto 0);
signal leftShiftStage1Idx3_uid192_alignedZ_uid57_fpCosPiTest_q : std_logic_vector (34 downto 0);
begin
--xIn(GPIN,3)@0
--LeftShiftStage133dto0_uid132_fxpX_uid41_fpCosPiTest(BITSELECT,131)@1
LeftShiftStage133dto0_uid132_fxpX_uid41_fpCosPiTest_in <= leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_q(33 downto 0);
LeftShiftStage133dto0_uid132_fxpX_uid41_fpCosPiTest_b <= LeftShiftStage133dto0_uid132_fxpX_uid41_fpCosPiTest_in(33 downto 0);
--leftShiftStage2Idx3Pad3_uid131_fxpX_uid41_fpCosPiTest(CONSTANT,130)
leftShiftStage2Idx3Pad3_uid131_fxpX_uid41_fpCosPiTest_q <= "000";
--leftShiftStage2Idx3_uid133_fxpX_uid41_fpCosPiTest(BITJOIN,132)@1
leftShiftStage2Idx3_uid133_fxpX_uid41_fpCosPiTest_q <= LeftShiftStage133dto0_uid132_fxpX_uid41_fpCosPiTest_b & leftShiftStage2Idx3Pad3_uid131_fxpX_uid41_fpCosPiTest_q;
--LeftShiftStage134dto0_uid129_fxpX_uid41_fpCosPiTest(BITSELECT,128)@1
LeftShiftStage134dto0_uid129_fxpX_uid41_fpCosPiTest_in <= leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_q(34 downto 0);
LeftShiftStage134dto0_uid129_fxpX_uid41_fpCosPiTest_b <= LeftShiftStage134dto0_uid129_fxpX_uid41_fpCosPiTest_in(34 downto 0);
--leftShiftStage2Idx2Pad2_uid128_fxpX_uid41_fpCosPiTest(CONSTANT,127)
leftShiftStage2Idx2Pad2_uid128_fxpX_uid41_fpCosPiTest_q <= "00";
--leftShiftStage2Idx2_uid130_fxpX_uid41_fpCosPiTest(BITJOIN,129)@1
leftShiftStage2Idx2_uid130_fxpX_uid41_fpCosPiTest_q <= LeftShiftStage134dto0_uid129_fxpX_uid41_fpCosPiTest_b & leftShiftStage2Idx2Pad2_uid128_fxpX_uid41_fpCosPiTest_q;
--LeftShiftStage135dto0_uid126_fxpX_uid41_fpCosPiTest(BITSELECT,125)@1
LeftShiftStage135dto0_uid126_fxpX_uid41_fpCosPiTest_in <= leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_q(35 downto 0);
LeftShiftStage135dto0_uid126_fxpX_uid41_fpCosPiTest_b <= LeftShiftStage135dto0_uid126_fxpX_uid41_fpCosPiTest_in(35 downto 0);
--GND(CONSTANT,0)
GND_q <= "0";
--leftShiftStage2Idx1_uid127_fxpX_uid41_fpCosPiTest(BITJOIN,126)@1
leftShiftStage2Idx1_uid127_fxpX_uid41_fpCosPiTest_q <= LeftShiftStage135dto0_uid126_fxpX_uid41_fpCosPiTest_b & GND_q;
--leftShiftStage0Idx3_uid111_fxpX_uid41_fpCosPiTest(CONSTANT,110)
leftShiftStage0Idx3_uid111_fxpX_uid41_fpCosPiTest_q <= "0000000000000000000000000000000000000";
--X4dto0_uid109_fxpX_uid41_fpCosPiTest(BITSELECT,108)@0
X4dto0_uid109_fxpX_uid41_fpCosPiTest_in <= oFracXExt_uid39_fpCosPiTest_q(4 downto 0);
X4dto0_uid109_fxpX_uid41_fpCosPiTest_b <= X4dto0_uid109_fxpX_uid41_fpCosPiTest_in(4 downto 0);
--leftShiftStage0Idx2Pad32_uid108_fxpX_uid41_fpCosPiTest(CONSTANT,107)
leftShiftStage0Idx2Pad32_uid108_fxpX_uid41_fpCosPiTest_q <= "00000000000000000000000000000000";
--leftShiftStage0Idx2_uid110_fxpX_uid41_fpCosPiTest(BITJOIN,109)@0
leftShiftStage0Idx2_uid110_fxpX_uid41_fpCosPiTest_q <= X4dto0_uid109_fxpX_uid41_fpCosPiTest_b & leftShiftStage0Idx2Pad32_uid108_fxpX_uid41_fpCosPiTest_q;
--X20dto0_uid106_fxpX_uid41_fpCosPiTest(BITSELECT,105)@0
X20dto0_uid106_fxpX_uid41_fpCosPiTest_in <= oFracXExt_uid39_fpCosPiTest_q(20 downto 0);
X20dto0_uid106_fxpX_uid41_fpCosPiTest_b <= X20dto0_uid106_fxpX_uid41_fpCosPiTest_in(20 downto 0);
--leftShiftStage0Idx1Pad16_uid105_fxpX_uid41_fpCosPiTest(CONSTANT,104)
leftShiftStage0Idx1Pad16_uid105_fxpX_uid41_fpCosPiTest_q <= "0000000000000000";
--leftShiftStage0Idx1_uid107_fxpX_uid41_fpCosPiTest(BITJOIN,106)@0
leftShiftStage0Idx1_uid107_fxpX_uid41_fpCosPiTest_q <= X20dto0_uid106_fxpX_uid41_fpCosPiTest_b & leftShiftStage0Idx1Pad16_uid105_fxpX_uid41_fpCosPiTest_q;
--cst01pWShift_uid14_fpCosPiTest(CONSTANT,13)
cst01pWShift_uid14_fpCosPiTest_q <= "0000000000000";
--VCC(CONSTANT,1)
VCC_q <= "1";
--fracX_uid7_fpCosPiTest(BITSELECT,6)@0
fracX_uid7_fpCosPiTest_in <= a(22 downto 0);
fracX_uid7_fpCosPiTest_b <= fracX_uid7_fpCosPiTest_in(22 downto 0);
--oFracX_uid37_uid37_fpCosPiTest(BITJOIN,36)@0
oFracX_uid37_uid37_fpCosPiTest_q <= VCC_q & fracX_uid7_fpCosPiTest_b;
--oFracXExt_uid39_fpCosPiTest(BITJOIN,38)@0
oFracXExt_uid39_fpCosPiTest_q <= cst01pWShift_uid14_fpCosPiTest_q & oFracX_uid37_uid37_fpCosPiTest_q;
--biasMwShiftMO_uid13_fpCosPiTest(CONSTANT,12)
biasMwShiftMO_uid13_fpCosPiTest_q <= "01110010";
--expX_uid6_fpCosPiTest(BITSELECT,5)@0
expX_uid6_fpCosPiTest_in <= a(30 downto 0);
expX_uid6_fpCosPiTest_b <= expX_uid6_fpCosPiTest_in(30 downto 23);
--shiftValFxPX_uid38_fpCosPiTest(SUB,37)@0
shiftValFxPX_uid38_fpCosPiTest_a <= STD_LOGIC_VECTOR("0" & expX_uid6_fpCosPiTest_b);
shiftValFxPX_uid38_fpCosPiTest_b <= STD_LOGIC_VECTOR("0" & biasMwShiftMO_uid13_fpCosPiTest_q);
shiftValFxPX_uid38_fpCosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(shiftValFxPX_uid38_fpCosPiTest_a) - UNSIGNED(shiftValFxPX_uid38_fpCosPiTest_b));
shiftValFxPX_uid38_fpCosPiTest_q <= shiftValFxPX_uid38_fpCosPiTest_o(8 downto 0);
--fxpShifterBits_uid40_fpCosPiTest(BITSELECT,39)@0
fxpShifterBits_uid40_fpCosPiTest_in <= shiftValFxPX_uid38_fpCosPiTest_q(5 downto 0);
fxpShifterBits_uid40_fpCosPiTest_b <= fxpShifterBits_uid40_fpCosPiTest_in(5 downto 0);
--leftShiftStageSel5Dto4_uid112_fxpX_uid41_fpCosPiTest(BITSELECT,111)@0
leftShiftStageSel5Dto4_uid112_fxpX_uid41_fpCosPiTest_in <= fxpShifterBits_uid40_fpCosPiTest_b;
leftShiftStageSel5Dto4_uid112_fxpX_uid41_fpCosPiTest_b <= leftShiftStageSel5Dto4_uid112_fxpX_uid41_fpCosPiTest_in(5 downto 4);
--leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest(MUX,112)@0
leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_s <= leftShiftStageSel5Dto4_uid112_fxpX_uid41_fpCosPiTest_b;
leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest: PROCESS (leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_s, en, oFracXExt_uid39_fpCosPiTest_q, leftShiftStage0Idx1_uid107_fxpX_uid41_fpCosPiTest_q, leftShiftStage0Idx2_uid110_fxpX_uid41_fpCosPiTest_q, leftShiftStage0Idx3_uid111_fxpX_uid41_fpCosPiTest_q)
BEGIN
CASE leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_s IS
WHEN "00" => leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_q <= oFracXExt_uid39_fpCosPiTest_q;
WHEN "01" => leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_q <= leftShiftStage0Idx1_uid107_fxpX_uid41_fpCosPiTest_q;
WHEN "10" => leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_q <= leftShiftStage0Idx2_uid110_fxpX_uid41_fpCosPiTest_q;
WHEN "11" => leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_q <= leftShiftStage0Idx3_uid111_fxpX_uid41_fpCosPiTest_q;
WHEN OTHERS => leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage024dto0_uid121_fxpX_uid41_fpCosPiTest(BITSELECT,120)@0
LeftShiftStage024dto0_uid121_fxpX_uid41_fpCosPiTest_in <= leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_q(24 downto 0);
LeftShiftStage024dto0_uid121_fxpX_uid41_fpCosPiTest_b <= LeftShiftStage024dto0_uid121_fxpX_uid41_fpCosPiTest_in(24 downto 0);
--leftShiftStage1Idx3Pad12_uid120_fxpX_uid41_fpCosPiTest(CONSTANT,119)
leftShiftStage1Idx3Pad12_uid120_fxpX_uid41_fpCosPiTest_q <= "000000000000";
--leftShiftStage1Idx3_uid122_fxpX_uid41_fpCosPiTest(BITJOIN,121)@0
leftShiftStage1Idx3_uid122_fxpX_uid41_fpCosPiTest_q <= LeftShiftStage024dto0_uid121_fxpX_uid41_fpCosPiTest_b & leftShiftStage1Idx3Pad12_uid120_fxpX_uid41_fpCosPiTest_q;
--reg_leftShiftStage1Idx3_uid122_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_5(REG,235)@0
reg_leftShiftStage1Idx3_uid122_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx3_uid122_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_5_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx3_uid122_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_5_q <= leftShiftStage1Idx3_uid122_fxpX_uid41_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage028dto0_uid118_fxpX_uid41_fpCosPiTest(BITSELECT,117)@0
LeftShiftStage028dto0_uid118_fxpX_uid41_fpCosPiTest_in <= leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_q(28 downto 0);
LeftShiftStage028dto0_uid118_fxpX_uid41_fpCosPiTest_b <= LeftShiftStage028dto0_uid118_fxpX_uid41_fpCosPiTest_in(28 downto 0);
--cstAllZWE_uid21_fpCosPiTest(CONSTANT,20)
cstAllZWE_uid21_fpCosPiTest_q <= "00000000";
--leftShiftStage1Idx2_uid119_fxpX_uid41_fpCosPiTest(BITJOIN,118)@0
leftShiftStage1Idx2_uid119_fxpX_uid41_fpCosPiTest_q <= LeftShiftStage028dto0_uid118_fxpX_uid41_fpCosPiTest_b & cstAllZWE_uid21_fpCosPiTest_q;
--reg_leftShiftStage1Idx2_uid119_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_4(REG,234)@0
reg_leftShiftStage1Idx2_uid119_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx2_uid119_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_4_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx2_uid119_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_4_q <= leftShiftStage1Idx2_uid119_fxpX_uid41_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage032dto0_uid115_fxpX_uid41_fpCosPiTest(BITSELECT,114)@0
LeftShiftStage032dto0_uid115_fxpX_uid41_fpCosPiTest_in <= leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_q(32 downto 0);
LeftShiftStage032dto0_uid115_fxpX_uid41_fpCosPiTest_b <= LeftShiftStage032dto0_uid115_fxpX_uid41_fpCosPiTest_in(32 downto 0);
--leftShiftStage1Idx1Pad4_uid114_fxpX_uid41_fpCosPiTest(CONSTANT,113)
leftShiftStage1Idx1Pad4_uid114_fxpX_uid41_fpCosPiTest_q <= "0000";
--leftShiftStage1Idx1_uid116_fxpX_uid41_fpCosPiTest(BITJOIN,115)@0
leftShiftStage1Idx1_uid116_fxpX_uid41_fpCosPiTest_q <= LeftShiftStage032dto0_uid115_fxpX_uid41_fpCosPiTest_b & leftShiftStage1Idx1Pad4_uid114_fxpX_uid41_fpCosPiTest_q;
--reg_leftShiftStage1Idx1_uid116_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_3(REG,233)@0
reg_leftShiftStage1Idx1_uid116_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx1_uid116_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_3_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx1_uid116_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_3_q <= leftShiftStage1Idx1_uid116_fxpX_uid41_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--reg_leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_2(REG,232)@0
reg_leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_2_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_2_q <= leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel3Dto2_uid123_fxpX_uid41_fpCosPiTest(BITSELECT,122)@0
leftShiftStageSel3Dto2_uid123_fxpX_uid41_fpCosPiTest_in <= fxpShifterBits_uid40_fpCosPiTest_b(3 downto 0);
leftShiftStageSel3Dto2_uid123_fxpX_uid41_fpCosPiTest_b <= leftShiftStageSel3Dto2_uid123_fxpX_uid41_fpCosPiTest_in(3 downto 2);
--reg_leftShiftStageSel3Dto2_uid123_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_1(REG,231)@0
reg_leftShiftStageSel3Dto2_uid123_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel3Dto2_uid123_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel3Dto2_uid123_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_1_q <= leftShiftStageSel3Dto2_uid123_fxpX_uid41_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest(MUX,123)@1
leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_s <= reg_leftShiftStageSel3Dto2_uid123_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_1_q;
leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest: PROCESS (leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_s, en, reg_leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_2_q, reg_leftShiftStage1Idx1_uid116_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_3_q, reg_leftShiftStage1Idx2_uid119_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_4_q, reg_leftShiftStage1Idx3_uid122_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_5_q)
BEGIN
CASE leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_s IS
WHEN "00" => leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_q <= reg_leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_2_q;
WHEN "01" => leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_q <= reg_leftShiftStage1Idx1_uid116_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_3_q;
WHEN "10" => leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_q <= reg_leftShiftStage1Idx2_uid119_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_4_q;
WHEN "11" => leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_q <= reg_leftShiftStage1Idx3_uid122_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_5_q;
WHEN OTHERS => leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--leftShiftStageSel1Dto0_uid134_fxpX_uid41_fpCosPiTest(BITSELECT,133)@0
leftShiftStageSel1Dto0_uid134_fxpX_uid41_fpCosPiTest_in <= fxpShifterBits_uid40_fpCosPiTest_b(1 downto 0);
leftShiftStageSel1Dto0_uid134_fxpX_uid41_fpCosPiTest_b <= leftShiftStageSel1Dto0_uid134_fxpX_uid41_fpCosPiTest_in(1 downto 0);
--reg_leftShiftStageSel1Dto0_uid134_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest_1(REG,236)@0
reg_leftShiftStageSel1Dto0_uid134_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel1Dto0_uid134_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel1Dto0_uid134_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest_1_q <= leftShiftStageSel1Dto0_uid134_fxpX_uid41_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest(MUX,134)@1
leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest_s <= reg_leftShiftStageSel1Dto0_uid134_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest_1_q;
leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest: PROCESS (leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest_s, en, leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_q, leftShiftStage2Idx1_uid127_fxpX_uid41_fpCosPiTest_q, leftShiftStage2Idx2_uid130_fxpX_uid41_fpCosPiTest_q, leftShiftStage2Idx3_uid133_fxpX_uid41_fpCosPiTest_q)
BEGIN
CASE leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest_s IS
WHEN "00" => leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest_q <= leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_q;
WHEN "01" => leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest_q <= leftShiftStage2Idx1_uid127_fxpX_uid41_fpCosPiTest_q;
WHEN "10" => leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest_q <= leftShiftStage2Idx2_uid130_fxpX_uid41_fpCosPiTest_q;
WHEN "11" => leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest_q <= leftShiftStage2Idx3_uid133_fxpX_uid41_fpCosPiTest_q;
WHEN OTHERS => leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--fxpXFrac_uid43_fpCosPiTest(BITSELECT,42)@1
fxpXFrac_uid43_fpCosPiTest_in <= leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest_q(35 downto 0);
fxpXFrac_uid43_fpCosPiTest_b <= fxpXFrac_uid43_fpCosPiTest_in(35 downto 0);
--FxpXFrac35_uid44_fpCosPiTest(BITSELECT,43)@1
FxpXFrac35_uid44_fpCosPiTest_in <= fxpXFrac_uid43_fpCosPiTest_b;
FxpXFrac35_uid44_fpCosPiTest_b <= FxpXFrac35_uid44_fpCosPiTest_in(35 downto 35);
--FxpX36_uid42_fpCosPiTest(BITSELECT,41)@1
FxpX36_uid42_fpCosPiTest_in <= leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest_q;
FxpX36_uid42_fpCosPiTest_b <= FxpX36_uid42_fpCosPiTest_in(36 downto 36);
--xParityXorHalfParity_uid96_fpCosPiTest(LOGICAL,95)@1
xParityXorHalfParity_uid96_fpCosPiTest_a <= FxpX36_uid42_fpCosPiTest_b;
xParityXorHalfParity_uid96_fpCosPiTest_b <= FxpXFrac35_uid44_fpCosPiTest_b;
xParityXorHalfParity_uid96_fpCosPiTest_q <= xParityXorHalfParity_uid96_fpCosPiTest_a xor xParityXorHalfParity_uid96_fpCosPiTest_b;
--ld_xParityXorHalfParity_uid96_fpCosPiTest_q_to_signRComp_uid99_fpCosPiTest_c(DELAY,369)@1
ld_xParityXorHalfParity_uid96_fpCosPiTest_q_to_signRComp_uid99_fpCosPiTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => xParityXorHalfParity_uid96_fpCosPiTest_q, xout => ld_xParityXorHalfParity_uid96_fpCosPiTest_q_to_signRComp_uid99_fpCosPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--cstBiasPwF_uid12_fpCosPiTest(CONSTANT,11)
cstBiasPwF_uid12_fpCosPiTest_q <= "10010110";
--xEvenInt_uid35_fpCosPiTest(COMPARE,34)@0
xEvenInt_uid35_fpCosPiTest_cin <= GND_q;
xEvenInt_uid35_fpCosPiTest_a <= STD_LOGIC_VECTOR("00" & cstBiasPwF_uid12_fpCosPiTest_q) & '0';
xEvenInt_uid35_fpCosPiTest_b <= STD_LOGIC_VECTOR("00" & expX_uid6_fpCosPiTest_b) & xEvenInt_uid35_fpCosPiTest_cin(0);
xEvenInt_uid35_fpCosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(xEvenInt_uid35_fpCosPiTest_a) - UNSIGNED(xEvenInt_uid35_fpCosPiTest_b));
xEvenInt_uid35_fpCosPiTest_c(0) <= xEvenInt_uid35_fpCosPiTest_o(10);
--ld_xEvenInt_uid35_fpCosPiTest_c_to_evenIntCosNotOneFZ_uid79_fpCosPiTest_a(DELAY,335)@0
ld_xEvenInt_uid35_fpCosPiTest_c_to_evenIntCosNotOneFZ_uid79_fpCosPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => xEvenInt_uid35_fpCosPiTest_c, xout => ld_xEvenInt_uid35_fpCosPiTest_c_to_evenIntCosNotOneFZ_uid79_fpCosPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--InvXEvenInt_uid81_fpCosPiTest(LOGICAL,80)@2
InvXEvenInt_uid81_fpCosPiTest_a <= ld_xEvenInt_uid35_fpCosPiTest_c_to_evenIntCosNotOneFZ_uid79_fpCosPiTest_a_q;
InvXEvenInt_uid81_fpCosPiTest_q <= not InvXEvenInt_uid81_fpCosPiTest_a;
--cosXIsOne_uid36_fpCosPiTest(COMPARE,35)@0
cosXIsOne_uid36_fpCosPiTest_cin <= GND_q;
cosXIsOne_uid36_fpCosPiTest_a <= STD_LOGIC_VECTOR("00" & expX_uid6_fpCosPiTest_b) & '0';
cosXIsOne_uid36_fpCosPiTest_b <= STD_LOGIC_VECTOR("00" & biasMwShiftMO_uid13_fpCosPiTest_q) & cosXIsOne_uid36_fpCosPiTest_cin(0);
cosXIsOne_uid36_fpCosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(cosXIsOne_uid36_fpCosPiTest_a) - UNSIGNED(cosXIsOne_uid36_fpCosPiTest_b));
cosXIsOne_uid36_fpCosPiTest_c(0) <= cosXIsOne_uid36_fpCosPiTest_o(10);
--ld_cosXIsOne_uid36_fpCosPiTest_c_to_InvCosXIsOne_uid77_fpCosPiTest_a(DELAY,332)@0
ld_cosXIsOne_uid36_fpCosPiTest_c_to_InvCosXIsOne_uid77_fpCosPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => cosXIsOne_uid36_fpCosPiTest_c, xout => ld_cosXIsOne_uid36_fpCosPiTest_c_to_InvCosXIsOne_uid77_fpCosPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--InvCosXIsOne_uid77_fpCosPiTest(LOGICAL,76)@2
InvCosXIsOne_uid77_fpCosPiTest_a <= ld_cosXIsOne_uid36_fpCosPiTest_c_to_InvCosXIsOne_uid77_fpCosPiTest_a_q;
InvCosXIsOne_uid77_fpCosPiTest_q <= not InvCosXIsOne_uid77_fpCosPiTest_a;
--signRComp_uid99_fpCosPiTest(LOGICAL,98)@2
signRComp_uid99_fpCosPiTest_a <= InvCosXIsOne_uid77_fpCosPiTest_q;
signRComp_uid99_fpCosPiTest_b <= InvXEvenInt_uid81_fpCosPiTest_q;
signRComp_uid99_fpCosPiTest_c <= ld_xParityXorHalfParity_uid96_fpCosPiTest_q_to_signRComp_uid99_fpCosPiTest_c_q;
signRComp_uid99_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
signRComp_uid99_fpCosPiTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1' AND en = "1") THEN
signRComp_uid99_fpCosPiTest_q <= signRComp_uid99_fpCosPiTest_a and signRComp_uid99_fpCosPiTest_b and signRComp_uid99_fpCosPiTest_c;
END IF;
END PROCESS;
--cstZwSwF_uid15_fpCosPiTest(CONSTANT,14)
cstZwSwF_uid15_fpCosPiTest_q <= "00000000000000000000000000000000000";
--cstHalfwSwFP1_uid18_fpCosPiTest(BITJOIN,17)@2
cstHalfwSwFP1_uid18_fpCosPiTest_q <= VCC_q & cstZwSwF_uid15_fpCosPiTest_q;
--reg_fxpXFrac_uid43_fpCosPiTest_0_to_fxpXFracZero_uid45_fpCosPiTest_1(REG,237)@1
reg_fxpXFrac_uid43_fpCosPiTest_0_to_fxpXFracZero_uid45_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fxpXFrac_uid43_fpCosPiTest_0_to_fxpXFracZero_uid45_fpCosPiTest_1_q <= "000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fxpXFrac_uid43_fpCosPiTest_0_to_fxpXFracZero_uid45_fpCosPiTest_1_q <= fxpXFrac_uid43_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--fxpXFracHalf_uid46_fpCosPiTest(LOGICAL,45)@2
fxpXFracHalf_uid46_fpCosPiTest_a <= reg_fxpXFrac_uid43_fpCosPiTest_0_to_fxpXFracZero_uid45_fpCosPiTest_1_q;
fxpXFracHalf_uid46_fpCosPiTest_b <= cstHalfwSwFP1_uid18_fpCosPiTest_q;
fxpXFracHalf_uid46_fpCosPiTest_q <= "1" when fxpXFracHalf_uid46_fpCosPiTest_a = fxpXFracHalf_uid46_fpCosPiTest_b else "0";
--ld_fxpXFracHalf_uid46_fpCosPiTest_q_to_InvFxpXFracHalf_uid100_fpCosPiTest_a(DELAY,370)@2
ld_fxpXFracHalf_uid46_fpCosPiTest_q_to_InvFxpXFracHalf_uid100_fpCosPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => fxpXFracHalf_uid46_fpCosPiTest_q, xout => ld_fxpXFracHalf_uid46_fpCosPiTest_q_to_InvFxpXFracHalf_uid100_fpCosPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--InvFxpXFracHalf_uid100_fpCosPiTest(LOGICAL,99)@3
InvFxpXFracHalf_uid100_fpCosPiTest_a <= ld_fxpXFracHalf_uid46_fpCosPiTest_q_to_InvFxpXFracHalf_uid100_fpCosPiTest_a_q;
InvFxpXFracHalf_uid100_fpCosPiTest_q <= not InvFxpXFracHalf_uid100_fpCosPiTest_a;
--signR_uid101_fpCosPiTest(LOGICAL,100)@3
signR_uid101_fpCosPiTest_a <= InvFxpXFracHalf_uid100_fpCosPiTest_q;
signR_uid101_fpCosPiTest_b <= signRComp_uid99_fpCosPiTest_q;
signR_uid101_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
signR_uid101_fpCosPiTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1' AND en = "1") THEN
signR_uid101_fpCosPiTest_q <= signR_uid101_fpCosPiTest_a and signR_uid101_fpCosPiTest_b;
END IF;
END PROCESS;
--ld_signR_uid101_fpCosPiTest_q_to_R_uid102_fpCosPiTest_c(DELAY,375)@4
ld_signR_uid101_fpCosPiTest_q_to_R_uid102_fpCosPiTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 13 )
PORT MAP ( xin => signR_uid101_fpCosPiTest_q, xout => ld_signR_uid101_fpCosPiTest_q_to_R_uid102_fpCosPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--cstBias_uid10_fpCosPiTest(CONSTANT,9)
cstBias_uid10_fpCosPiTest_q <= "01111111";
--cstAllOWE_uid8_fpCosPiTest(CONSTANT,7)
cstAllOWE_uid8_fpCosPiTest_q <= "11111111";
--pad_o_uid16_uid47_fpCosPiTest(BITJOIN,46)@1
pad_o_uid16_uid47_fpCosPiTest_q <= VCC_q & STD_LOGIC_VECTOR((35 downto 1 => GND_q(0)) & GND_q);
--reg_pad_o_uid16_uid47_fpCosPiTest_0_to_oMFxpXFrac_uid47_fpCosPiTest_0(REG,244)@1
reg_pad_o_uid16_uid47_fpCosPiTest_0_to_oMFxpXFrac_uid47_fpCosPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_o_uid16_uid47_fpCosPiTest_0_to_oMFxpXFrac_uid47_fpCosPiTest_0_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_o_uid16_uid47_fpCosPiTest_0_to_oMFxpXFrac_uid47_fpCosPiTest_0_q <= pad_o_uid16_uid47_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--oMFxpXFrac_uid47_fpCosPiTest(SUB,47)@2
oMFxpXFrac_uid47_fpCosPiTest_a <= STD_LOGIC_VECTOR("0" & reg_pad_o_uid16_uid47_fpCosPiTest_0_to_oMFxpXFrac_uid47_fpCosPiTest_0_q);
oMFxpXFrac_uid47_fpCosPiTest_b <= STD_LOGIC_VECTOR("00" & reg_fxpXFrac_uid43_fpCosPiTest_0_to_fxpXFracZero_uid45_fpCosPiTest_1_q);
oMFxpXFrac_uid47_fpCosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(oMFxpXFrac_uid47_fpCosPiTest_a) - UNSIGNED(oMFxpXFrac_uid47_fpCosPiTest_b));
oMFxpXFrac_uid47_fpCosPiTest_q <= oMFxpXFrac_uid47_fpCosPiTest_o(37 downto 0);
--oMFxpXFrac_uid49_fpCosPiTest(BITSELECT,48)@2
oMFxpXFrac_uid49_fpCosPiTest_in <= oMFxpXFrac_uid47_fpCosPiTest_q(35 downto 0);
oMFxpXFrac_uid49_fpCosPiTest_b <= oMFxpXFrac_uid49_fpCosPiTest_in(35 downto 0);
--ld_fxpXFrac_uid43_fpCosPiTest_b_to_rangeReducedFxPX_uid51_fpCosPiTest_c(DELAY,308)@1
ld_fxpXFrac_uid43_fpCosPiTest_b_to_rangeReducedFxPX_uid51_fpCosPiTest_c : dspba_delay
GENERIC MAP ( width => 36, depth => 1 )
PORT MAP ( xin => fxpXFrac_uid43_fpCosPiTest_b, xout => ld_fxpXFrac_uid43_fpCosPiTest_b_to_rangeReducedFxPX_uid51_fpCosPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--ld_FxpXFrac35_uid44_fpCosPiTest_b_to_rangeReducedFxPX_uid51_fpCosPiTest_b(DELAY,307)@1
ld_FxpXFrac35_uid44_fpCosPiTest_b_to_rangeReducedFxPX_uid51_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => FxpXFrac35_uid44_fpCosPiTest_b, xout => ld_FxpXFrac35_uid44_fpCosPiTest_b_to_rangeReducedFxPX_uid51_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--rangeReducedFxPX_uid51_fpCosPiTest(MUX,50)@2
rangeReducedFxPX_uid51_fpCosPiTest_s <= ld_FxpXFrac35_uid44_fpCosPiTest_b_to_rangeReducedFxPX_uid51_fpCosPiTest_b_q;
rangeReducedFxPX_uid51_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
rangeReducedFxPX_uid51_fpCosPiTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE rangeReducedFxPX_uid51_fpCosPiTest_s IS
WHEN "0" => rangeReducedFxPX_uid51_fpCosPiTest_q <= ld_fxpXFrac_uid43_fpCosPiTest_b_to_rangeReducedFxPX_uid51_fpCosPiTest_c_q;
WHEN "1" => rangeReducedFxPX_uid51_fpCosPiTest_q <= oMFxpXFrac_uid49_fpCosPiTest_b;
WHEN OTHERS => rangeReducedFxPX_uid51_fpCosPiTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--pad_half_uid17_uid52_fpCosPiTest(BITJOIN,51)@2
pad_half_uid17_uid52_fpCosPiTest_q <= VCC_q & STD_LOGIC_VECTOR((34 downto 1 => GND_q(0)) & GND_q);
--reg_pad_half_uid17_uid52_fpCosPiTest_0_to_z_halfMRRFxPXE_uid52_fpCosPiTest_0(REG,246)@2
reg_pad_half_uid17_uid52_fpCosPiTest_0_to_z_halfMRRFxPXE_uid52_fpCosPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_half_uid17_uid52_fpCosPiTest_0_to_z_halfMRRFxPXE_uid52_fpCosPiTest_0_q <= "000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_half_uid17_uid52_fpCosPiTest_0_to_z_halfMRRFxPXE_uid52_fpCosPiTest_0_q <= pad_half_uid17_uid52_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--z_halfMRRFxPXE_uid52_fpCosPiTest(SUB,52)@3
z_halfMRRFxPXE_uid52_fpCosPiTest_a <= STD_LOGIC_VECTOR("0" & reg_pad_half_uid17_uid52_fpCosPiTest_0_to_z_halfMRRFxPXE_uid52_fpCosPiTest_0_q);
z_halfMRRFxPXE_uid52_fpCosPiTest_b <= STD_LOGIC_VECTOR("0" & rangeReducedFxPX_uid51_fpCosPiTest_q);
z_halfMRRFxPXE_uid52_fpCosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(z_halfMRRFxPXE_uid52_fpCosPiTest_a) - UNSIGNED(z_halfMRRFxPXE_uid52_fpCosPiTest_b));
z_halfMRRFxPXE_uid52_fpCosPiTest_q <= z_halfMRRFxPXE_uid52_fpCosPiTest_o(36 downto 0);
--z_uid54_fpCosPiTest(BITSELECT,53)@3
z_uid54_fpCosPiTest_in <= z_halfMRRFxPXE_uid52_fpCosPiTest_q(34 downto 0);
z_uid54_fpCosPiTest_b <= z_uid54_fpCosPiTest_in(34 downto 0);
--zAddr_uid62_fpCosPiTest(BITSELECT,61)@3
zAddr_uid62_fpCosPiTest_in <= z_uid54_fpCosPiTest_b;
zAddr_uid62_fpCosPiTest_b <= zAddr_uid62_fpCosPiTest_in(34 downto 28);
--reg_zAddr_uid62_fpCosPiTest_0_to_memoryC2_uid209_sinPiZTableGenerator_0(REG,263)@3
reg_zAddr_uid62_fpCosPiTest_0_to_memoryC2_uid209_sinPiZTableGenerator_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_zAddr_uid62_fpCosPiTest_0_to_memoryC2_uid209_sinPiZTableGenerator_0_q <= "0000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_zAddr_uid62_fpCosPiTest_0_to_memoryC2_uid209_sinPiZTableGenerator_0_q <= zAddr_uid62_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--memoryC2_uid209_sinPiZTableGenerator(LOOKUP,208)@4
memoryC2_uid209_sinPiZTableGenerator: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
memoryC2_uid209_sinPiZTableGenerator_q <= "10101101010011";
ELSIF (clk'EVENT AND clk = '1' AND en = "1") THEN
CASE (reg_zAddr_uid62_fpCosPiTest_0_to_memoryC2_uid209_sinPiZTableGenerator_0_q) IS
WHEN "0000000" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101101010011";
WHEN "0000001" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101101010100";
WHEN "0000010" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101101010111";
WHEN "0000011" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101101011001";
WHEN "0000100" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101101011011";
WHEN "0000101" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101101011100";
WHEN "0000110" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101101011111";
WHEN "0000111" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101101100010";
WHEN "0001000" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101101100110";
WHEN "0001001" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101101101011";
WHEN "0001010" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101101110000";
WHEN "0001011" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101101110101";
WHEN "0001100" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101101111011";
WHEN "0001101" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101110000000";
WHEN "0001110" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101110000111";
WHEN "0001111" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101110001110";
WHEN "0010000" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101110010011";
WHEN "0010001" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101110011110";
WHEN "0010010" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101110100110";
WHEN "0010011" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101110101111";
WHEN "0010100" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101110111000";
WHEN "0010101" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101111000011";
WHEN "0010110" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101111001100";
WHEN "0010111" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101111010111";
WHEN "0011000" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101111100011";
WHEN "0011001" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101111101110";
WHEN "0011010" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101111111011";
WHEN "0011011" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110000001001";
WHEN "0011100" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110000010101";
WHEN "0011101" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110000100000";
WHEN "0011110" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110000110001";
WHEN "0011111" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110001000000";
WHEN "0100000" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110001001101";
WHEN "0100001" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110001011110";
WHEN "0100010" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110001101100";
WHEN "0100011" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110001111111";
WHEN "0100100" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110010001111";
WHEN "0100101" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110010100001";
WHEN "0100110" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110010110011";
WHEN "0100111" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110011000101";
WHEN "0101000" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110011010110";
WHEN "0101001" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110011101011";
WHEN "0101010" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110011111111";
WHEN "0101011" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110100010010";
WHEN "0101100" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110100100101";
WHEN "0101101" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110100111011";
WHEN "0101110" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110101001110";
WHEN "0101111" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110101100111";
WHEN "0110000" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110101111100";
WHEN "0110001" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110110010010";
WHEN "0110010" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110110100110";
WHEN "0110011" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110111000000";
WHEN "0110100" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110111010101";
WHEN "0110101" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110111110000";
WHEN "0110110" => memoryC2_uid209_sinPiZTableGenerator_q <= "10111000000110";
WHEN "0110111" => memoryC2_uid209_sinPiZTableGenerator_q <= "10111000100010";
WHEN "0111000" => memoryC2_uid209_sinPiZTableGenerator_q <= "10111000111001";
WHEN "0111001" => memoryC2_uid209_sinPiZTableGenerator_q <= "10111001010100";
WHEN "0111010" => memoryC2_uid209_sinPiZTableGenerator_q <= "10111001101111";
WHEN "0111011" => memoryC2_uid209_sinPiZTableGenerator_q <= "10111010001001";
WHEN "0111100" => memoryC2_uid209_sinPiZTableGenerator_q <= "10111010100011";
WHEN "0111101" => memoryC2_uid209_sinPiZTableGenerator_q <= "10111010111100";
WHEN "0111110" => memoryC2_uid209_sinPiZTableGenerator_q <= "10111011011001";
WHEN "0111111" => memoryC2_uid209_sinPiZTableGenerator_q <= "10111011110111";
WHEN "1000000" => memoryC2_uid209_sinPiZTableGenerator_q <= "10111100010100";
WHEN "1000001" => memoryC2_uid209_sinPiZTableGenerator_q <= "10111100110001";
WHEN "1000010" => memoryC2_uid209_sinPiZTableGenerator_q <= "10111101001101";
WHEN "1000011" => memoryC2_uid209_sinPiZTableGenerator_q <= "10111101101010";
WHEN "1000100" => memoryC2_uid209_sinPiZTableGenerator_q <= "10111110001000";
WHEN "1000101" => memoryC2_uid209_sinPiZTableGenerator_q <= "10111110100101";
WHEN "1000110" => memoryC2_uid209_sinPiZTableGenerator_q <= "10111111000101";
WHEN "1000111" => memoryC2_uid209_sinPiZTableGenerator_q <= "10111111100011";
WHEN "1001000" => memoryC2_uid209_sinPiZTableGenerator_q <= "11000000000011";
WHEN "1001001" => memoryC2_uid209_sinPiZTableGenerator_q <= "11000000100011";
WHEN "1001010" => memoryC2_uid209_sinPiZTableGenerator_q <= "11000001000100";
WHEN "1001011" => memoryC2_uid209_sinPiZTableGenerator_q <= "11000001100010";
WHEN "1001100" => memoryC2_uid209_sinPiZTableGenerator_q <= "11000010000100";
WHEN "1001101" => memoryC2_uid209_sinPiZTableGenerator_q <= "11000010100010";
WHEN "1001110" => memoryC2_uid209_sinPiZTableGenerator_q <= "11000011000110";
WHEN "1001111" => memoryC2_uid209_sinPiZTableGenerator_q <= "11000011101000";
WHEN "1010000" => memoryC2_uid209_sinPiZTableGenerator_q <= "11000100001010";
WHEN "1010001" => memoryC2_uid209_sinPiZTableGenerator_q <= "11000100101101";
WHEN "1010010" => memoryC2_uid209_sinPiZTableGenerator_q <= "11000101010001";
WHEN "1010011" => memoryC2_uid209_sinPiZTableGenerator_q <= "11000101110010";
WHEN "1010100" => memoryC2_uid209_sinPiZTableGenerator_q <= "11000110010100";
WHEN "1010101" => memoryC2_uid209_sinPiZTableGenerator_q <= "11000110111011";
WHEN "1010110" => memoryC2_uid209_sinPiZTableGenerator_q <= "11000111011010";
WHEN "1010111" => memoryC2_uid209_sinPiZTableGenerator_q <= "11001000000001";
WHEN "1011000" => memoryC2_uid209_sinPiZTableGenerator_q <= "11001000100110";
WHEN "1011001" => memoryC2_uid209_sinPiZTableGenerator_q <= "11001001001011";
WHEN "1011010" => memoryC2_uid209_sinPiZTableGenerator_q <= "11001001101101";
WHEN "1011011" => memoryC2_uid209_sinPiZTableGenerator_q <= "11001010010101";
WHEN "1011100" => memoryC2_uid209_sinPiZTableGenerator_q <= "11001010111100";
WHEN "1011101" => memoryC2_uid209_sinPiZTableGenerator_q <= "11001011100000";
WHEN "1011110" => memoryC2_uid209_sinPiZTableGenerator_q <= "11001100000101";
WHEN "1011111" => memoryC2_uid209_sinPiZTableGenerator_q <= "11001100101110";
WHEN "1100000" => memoryC2_uid209_sinPiZTableGenerator_q <= "11001101010100";
WHEN "1100001" => memoryC2_uid209_sinPiZTableGenerator_q <= "11001101111010";
WHEN "1100010" => memoryC2_uid209_sinPiZTableGenerator_q <= "11001110100010";
WHEN "1100011" => memoryC2_uid209_sinPiZTableGenerator_q <= "11001111001001";
WHEN "1100100" => memoryC2_uid209_sinPiZTableGenerator_q <= "11001111110001";
WHEN "1100101" => memoryC2_uid209_sinPiZTableGenerator_q <= "11010000010110";
WHEN "1100110" => memoryC2_uid209_sinPiZTableGenerator_q <= "11010000111111";
WHEN "1100111" => memoryC2_uid209_sinPiZTableGenerator_q <= "11010001101001";
WHEN "1101000" => memoryC2_uid209_sinPiZTableGenerator_q <= "11010010010010";
WHEN "1101001" => memoryC2_uid209_sinPiZTableGenerator_q <= "11010010111101";
WHEN "1101010" => memoryC2_uid209_sinPiZTableGenerator_q <= "11010011100001";
WHEN "1101011" => memoryC2_uid209_sinPiZTableGenerator_q <= "11010100001100";
WHEN "1101100" => memoryC2_uid209_sinPiZTableGenerator_q <= "11010100110111";
WHEN "1101101" => memoryC2_uid209_sinPiZTableGenerator_q <= "11010101100001";
WHEN "1101110" => memoryC2_uid209_sinPiZTableGenerator_q <= "11010110001011";
WHEN "1101111" => memoryC2_uid209_sinPiZTableGenerator_q <= "11010110110011";
WHEN "1110000" => memoryC2_uid209_sinPiZTableGenerator_q <= "11010111011111";
WHEN "1110001" => memoryC2_uid209_sinPiZTableGenerator_q <= "11011000001010";
WHEN "1110010" => memoryC2_uid209_sinPiZTableGenerator_q <= "11011000110100";
WHEN "1110011" => memoryC2_uid209_sinPiZTableGenerator_q <= "11011001011111";
WHEN "1110100" => memoryC2_uid209_sinPiZTableGenerator_q <= "11011010001010";
WHEN "1110101" => memoryC2_uid209_sinPiZTableGenerator_q <= "11011010110110";
WHEN "1110110" => memoryC2_uid209_sinPiZTableGenerator_q <= "11011011100011";
WHEN "1110111" => memoryC2_uid209_sinPiZTableGenerator_q <= "11011100001111";
WHEN "1111000" => memoryC2_uid209_sinPiZTableGenerator_q <= "11011100111001";
WHEN "1111001" => memoryC2_uid209_sinPiZTableGenerator_q <= "11011101100011";
WHEN "1111010" => memoryC2_uid209_sinPiZTableGenerator_q <= "11011110010001";
WHEN "1111011" => memoryC2_uid209_sinPiZTableGenerator_q <= "11011110111011";
WHEN "1111100" => memoryC2_uid209_sinPiZTableGenerator_q <= "11011111101000";
WHEN "1111101" => memoryC2_uid209_sinPiZTableGenerator_q <= "11100000010101";
WHEN "1111110" => memoryC2_uid209_sinPiZTableGenerator_q <= "11100001000010";
WHEN "1111111" => memoryC2_uid209_sinPiZTableGenerator_q <= "11100001110000";
WHEN OTHERS =>
memoryC2_uid209_sinPiZTableGenerator_q <= (others => '-');
END CASE;
END IF;
END PROCESS;
--zPPolyEval_uid63_fpCosPiTest(BITSELECT,62)@3
zPPolyEval_uid63_fpCosPiTest_in <= z_uid54_fpCosPiTest_b(27 downto 0);
zPPolyEval_uid63_fpCosPiTest_b <= zPPolyEval_uid63_fpCosPiTest_in(27 downto 12);
--yT1_uid210_sinPiZPolyEval(BITSELECT,209)@3
yT1_uid210_sinPiZPolyEval_in <= zPPolyEval_uid63_fpCosPiTest_b;
yT1_uid210_sinPiZPolyEval_b <= yT1_uid210_sinPiZPolyEval_in(15 downto 2);
--reg_yT1_uid210_sinPiZPolyEval_0_to_prodXY_uid226_pT1_uid211_sinPiZPolyEval_0(REG,264)@3
reg_yT1_uid210_sinPiZPolyEval_0_to_prodXY_uid226_pT1_uid211_sinPiZPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT1_uid210_sinPiZPolyEval_0_to_prodXY_uid226_pT1_uid211_sinPiZPolyEval_0_q <= "00000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT1_uid210_sinPiZPolyEval_0_to_prodXY_uid226_pT1_uid211_sinPiZPolyEval_0_q <= yT1_uid210_sinPiZPolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_reg_yT1_uid210_sinPiZPolyEval_0_to_prodXY_uid226_pT1_uid211_sinPiZPolyEval_0_q_to_prodXY_uid226_pT1_uid211_sinPiZPolyEval_a(DELAY,499)@4
ld_reg_yT1_uid210_sinPiZPolyEval_0_to_prodXY_uid226_pT1_uid211_sinPiZPolyEval_0_q_to_prodXY_uid226_pT1_uid211_sinPiZPolyEval_a : dspba_delay
GENERIC MAP ( width => 14, depth => 1 )
PORT MAP ( xin => reg_yT1_uid210_sinPiZPolyEval_0_to_prodXY_uid226_pT1_uid211_sinPiZPolyEval_0_q, xout => ld_reg_yT1_uid210_sinPiZPolyEval_0_to_prodXY_uid226_pT1_uid211_sinPiZPolyEval_0_q_to_prodXY_uid226_pT1_uid211_sinPiZPolyEval_a_q, ena => en(0), clk => clk, aclr => areset );
--prodXY_uid226_pT1_uid211_sinPiZPolyEval(MULT,225)@5
prodXY_uid226_pT1_uid211_sinPiZPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid226_pT1_uid211_sinPiZPolyEval_a),15)) * SIGNED(prodXY_uid226_pT1_uid211_sinPiZPolyEval_b);
prodXY_uid226_pT1_uid211_sinPiZPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid226_pT1_uid211_sinPiZPolyEval_a <= (others => '0');
prodXY_uid226_pT1_uid211_sinPiZPolyEval_b <= (others => '0');
prodXY_uid226_pT1_uid211_sinPiZPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid226_pT1_uid211_sinPiZPolyEval_a <= ld_reg_yT1_uid210_sinPiZPolyEval_0_to_prodXY_uid226_pT1_uid211_sinPiZPolyEval_0_q_to_prodXY_uid226_pT1_uid211_sinPiZPolyEval_a_q;
prodXY_uid226_pT1_uid211_sinPiZPolyEval_b <= memoryC2_uid209_sinPiZTableGenerator_q;
prodXY_uid226_pT1_uid211_sinPiZPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid226_pT1_uid211_sinPiZPolyEval_pr,28));
END IF;
END IF;
END PROCESS;
prodXY_uid226_pT1_uid211_sinPiZPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid226_pT1_uid211_sinPiZPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid226_pT1_uid211_sinPiZPolyEval_q <= prodXY_uid226_pT1_uid211_sinPiZPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid227_pT1_uid211_sinPiZPolyEval(BITSELECT,226)@8
prodXYTruncFR_uid227_pT1_uid211_sinPiZPolyEval_in <= prodXY_uid226_pT1_uid211_sinPiZPolyEval_q;
prodXYTruncFR_uid227_pT1_uid211_sinPiZPolyEval_b <= prodXYTruncFR_uid227_pT1_uid211_sinPiZPolyEval_in(27 downto 13);
--highBBits_uid213_sinPiZPolyEval(BITSELECT,212)@8
highBBits_uid213_sinPiZPolyEval_in <= prodXYTruncFR_uid227_pT1_uid211_sinPiZPolyEval_b;
highBBits_uid213_sinPiZPolyEval_b <= highBBits_uid213_sinPiZPolyEval_in(14 downto 1);
--ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_notEnable(LOGICAL,557)
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_notEnable_a <= en;
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_notEnable_q <= not ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_notEnable_a;
--ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_nor(LOGICAL,596)
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_nor_a <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_notEnable_q;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_nor_b <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_sticky_ena_q;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_nor_q <= not (ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_nor_a or ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_nor_b);
--ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_mem_top(CONSTANT,592)
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_mem_top_q <= "010";
--ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_cmp(LOGICAL,593)
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_cmp_a <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_mem_top_q;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdmux_q);
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_cmp_q <= "1" when ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_cmp_a = ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_cmp_b else "0";
--ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_cmpReg(REG,594)
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_cmpReg_q <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_sticky_ena(REG,597)
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_nor_q = "1") THEN
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_sticky_ena_q <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_enaAnd(LOGICAL,598)
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_enaAnd_a <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_sticky_ena_q;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_enaAnd_b <= en;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_enaAnd_q <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_enaAnd_a and ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_enaAnd_b;
--ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt(COUNTER,588)
-- every=1, low=0, high=2, step=1, init=1
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt_i <= TO_UNSIGNED(1,2);
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt_i = 1 THEN
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt_eq = '1') THEN
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt_i <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt_i - 2;
ELSE
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt_i <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt_i,2));
--ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdreg(REG,589)
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdreg_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdreg_q <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdmux(MUX,590)
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdmux_s <= en;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdmux: PROCESS (ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdmux_s, ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdreg_q, ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdmux_s IS
WHEN "0" => ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdmux_q <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdreg_q;
WHEN "1" => ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdmux_q <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem(DUALMEM,587)
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_reset0 <= areset;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_ia <= reg_zAddr_uid62_fpCosPiTest_0_to_memoryC2_uid209_sinPiZTableGenerator_0_q;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_aa <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdreg_q;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_ab <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdmux_q;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 7,
widthad_a => 2,
numwords_a => 3,
width_b => 7,
widthad_b => 2,
numwords_b => 3,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_iq,
address_a => ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_aa,
data_a => ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_ia
);
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_q <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_iq(6 downto 0);
--memoryC1_uid208_sinPiZTableGenerator(LOOKUP,207)@8
memoryC1_uid208_sinPiZTableGenerator: PROCESS (ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_q)
BEGIN
-- Begin reserved scope level
CASE (ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_q) IS
WHEN "0000000" => memoryC1_uid208_sinPiZTableGenerator_q <= "000000000000000000001";
WHEN "0000001" => memoryC1_uid208_sinPiZTableGenerator_q <= "111111101011010101010";
WHEN "0000010" => memoryC1_uid208_sinPiZTableGenerator_q <= "111111010110101010001";
WHEN "0000011" => memoryC1_uid208_sinPiZTableGenerator_q <= "111111000001111111100";
WHEN "0000100" => memoryC1_uid208_sinPiZTableGenerator_q <= "111110101101010101010";
WHEN "0000101" => memoryC1_uid208_sinPiZTableGenerator_q <= "111110011000101011101";
WHEN "0000110" => memoryC1_uid208_sinPiZTableGenerator_q <= "111110000100000010101";
WHEN "0000111" => memoryC1_uid208_sinPiZTableGenerator_q <= "111101101111011010001";
WHEN "0001000" => memoryC1_uid208_sinPiZTableGenerator_q <= "111101011010110010101";
WHEN "0001001" => memoryC1_uid208_sinPiZTableGenerator_q <= "111101000110001011111";
WHEN "0001010" => memoryC1_uid208_sinPiZTableGenerator_q <= "111100110001100110010";
WHEN "0001011" => memoryC1_uid208_sinPiZTableGenerator_q <= "111100011101000010000";
WHEN "0001100" => memoryC1_uid208_sinPiZTableGenerator_q <= "111100001000011110111";
WHEN "0001101" => memoryC1_uid208_sinPiZTableGenerator_q <= "111011110011111101011";
WHEN "0001110" => memoryC1_uid208_sinPiZTableGenerator_q <= "111011011111011101011";
WHEN "0001111" => memoryC1_uid208_sinPiZTableGenerator_q <= "111011001010111110111";
WHEN "0010000" => memoryC1_uid208_sinPiZTableGenerator_q <= "111010110110100010101";
WHEN "0010001" => memoryC1_uid208_sinPiZTableGenerator_q <= "111010100010000111100";
WHEN "0010010" => memoryC1_uid208_sinPiZTableGenerator_q <= "111010001101101111000";
WHEN "0010011" => memoryC1_uid208_sinPiZTableGenerator_q <= "111001111001011000011";
WHEN "0010100" => memoryC1_uid208_sinPiZTableGenerator_q <= "111001100101000100010";
WHEN "0010101" => memoryC1_uid208_sinPiZTableGenerator_q <= "111001010000110010001";
WHEN "0010110" => memoryC1_uid208_sinPiZTableGenerator_q <= "111000111100100010111";
WHEN "0010111" => memoryC1_uid208_sinPiZTableGenerator_q <= "111000101000010110001";
WHEN "0011000" => memoryC1_uid208_sinPiZTableGenerator_q <= "111000010100001011111";
WHEN "0011001" => memoryC1_uid208_sinPiZTableGenerator_q <= "111000000000000100110";
WHEN "0011010" => memoryC1_uid208_sinPiZTableGenerator_q <= "110111101100000000011";
WHEN "0011011" => memoryC1_uid208_sinPiZTableGenerator_q <= "110111010111111111000";
WHEN "0011100" => memoryC1_uid208_sinPiZTableGenerator_q <= "110111000100000001000";
WHEN "0011101" => memoryC1_uid208_sinPiZTableGenerator_q <= "110110110000000110101";
WHEN "0011110" => memoryC1_uid208_sinPiZTableGenerator_q <= "110110011100001110111";
WHEN "0011111" => memoryC1_uid208_sinPiZTableGenerator_q <= "110110001000011011000";
WHEN "0100000" => memoryC1_uid208_sinPiZTableGenerator_q <= "110101110100101011010";
WHEN "0100001" => memoryC1_uid208_sinPiZTableGenerator_q <= "110101100000111110101";
WHEN "0100010" => memoryC1_uid208_sinPiZTableGenerator_q <= "110101001101010110010";
WHEN "0100011" => memoryC1_uid208_sinPiZTableGenerator_q <= "110100111001110001011";
WHEN "0100100" => memoryC1_uid208_sinPiZTableGenerator_q <= "110100100110010001001";
WHEN "0100101" => memoryC1_uid208_sinPiZTableGenerator_q <= "110100010010110100110";
WHEN "0100110" => memoryC1_uid208_sinPiZTableGenerator_q <= "110011111111011100110";
WHEN "0100111" => memoryC1_uid208_sinPiZTableGenerator_q <= "110011101100001001010";
WHEN "0101000" => memoryC1_uid208_sinPiZTableGenerator_q <= "110011011000111010011";
WHEN "0101001" => memoryC1_uid208_sinPiZTableGenerator_q <= "110011000101101111111";
WHEN "0101010" => memoryC1_uid208_sinPiZTableGenerator_q <= "110010110010101010010";
WHEN "0101011" => memoryC1_uid208_sinPiZTableGenerator_q <= "110010011111101001101";
WHEN "0101100" => memoryC1_uid208_sinPiZTableGenerator_q <= "110010001100101110000";
WHEN "0101101" => memoryC1_uid208_sinPiZTableGenerator_q <= "110001111001110111001";
WHEN "0101110" => memoryC1_uid208_sinPiZTableGenerator_q <= "110001100111000110000";
WHEN "0101111" => memoryC1_uid208_sinPiZTableGenerator_q <= "110001010100011001011";
WHEN "0110000" => memoryC1_uid208_sinPiZTableGenerator_q <= "110001000001110010110";
WHEN "0110001" => memoryC1_uid208_sinPiZTableGenerator_q <= "110000101111010001100";
WHEN "0110010" => memoryC1_uid208_sinPiZTableGenerator_q <= "110000011100110110001";
WHEN "0110011" => memoryC1_uid208_sinPiZTableGenerator_q <= "110000001010011111111";
WHEN "0110100" => memoryC1_uid208_sinPiZTableGenerator_q <= "101111111000010000000";
WHEN "0110101" => memoryC1_uid208_sinPiZTableGenerator_q <= "101111100110000101100";
WHEN "0110110" => memoryC1_uid208_sinPiZTableGenerator_q <= "101111010100000001100";
WHEN "0110111" => memoryC1_uid208_sinPiZTableGenerator_q <= "101111000010000011001";
WHEN "0111000" => memoryC1_uid208_sinPiZTableGenerator_q <= "101110110000001011100";
WHEN "0111001" => memoryC1_uid208_sinPiZTableGenerator_q <= "101110011110011001110";
WHEN "0111010" => memoryC1_uid208_sinPiZTableGenerator_q <= "101110001100101110101";
WHEN "0111011" => memoryC1_uid208_sinPiZTableGenerator_q <= "101101111011001010001";
WHEN "0111100" => memoryC1_uid208_sinPiZTableGenerator_q <= "101101101001101100010";
WHEN "0111101" => memoryC1_uid208_sinPiZTableGenerator_q <= "101101011000010101010";
WHEN "0111110" => memoryC1_uid208_sinPiZTableGenerator_q <= "101101000111000100101";
WHEN "0111111" => memoryC1_uid208_sinPiZTableGenerator_q <= "101100110101111010111";
WHEN "1000000" => memoryC1_uid208_sinPiZTableGenerator_q <= "101100100100111000010";
WHEN "1000001" => memoryC1_uid208_sinPiZTableGenerator_q <= "101100010011111100111";
WHEN "1000010" => memoryC1_uid208_sinPiZTableGenerator_q <= "101100000011001000111";
WHEN "1000011" => memoryC1_uid208_sinPiZTableGenerator_q <= "101011110010011100000";
WHEN "1000100" => memoryC1_uid208_sinPiZTableGenerator_q <= "101011100001110110100";
WHEN "1000101" => memoryC1_uid208_sinPiZTableGenerator_q <= "101011010001011000100";
WHEN "1000110" => memoryC1_uid208_sinPiZTableGenerator_q <= "101011000001000001110";
WHEN "1000111" => memoryC1_uid208_sinPiZTableGenerator_q <= "101010110000110011000";
WHEN "1001000" => memoryC1_uid208_sinPiZTableGenerator_q <= "101010100000101011111";
WHEN "1001001" => memoryC1_uid208_sinPiZTableGenerator_q <= "101010010000101100100";
WHEN "1001010" => memoryC1_uid208_sinPiZTableGenerator_q <= "101010000000110101001";
WHEN "1001011" => memoryC1_uid208_sinPiZTableGenerator_q <= "101001110001000110000";
WHEN "1001100" => memoryC1_uid208_sinPiZTableGenerator_q <= "101001100001011110101";
WHEN "1001101" => memoryC1_uid208_sinPiZTableGenerator_q <= "101001010001111111111";
WHEN "1001110" => memoryC1_uid208_sinPiZTableGenerator_q <= "101001000010101000110";
WHEN "1001111" => memoryC1_uid208_sinPiZTableGenerator_q <= "101000110011011010001";
WHEN "1010000" => memoryC1_uid208_sinPiZTableGenerator_q <= "101000100100010100001";
WHEN "1010001" => memoryC1_uid208_sinPiZTableGenerator_q <= "101000010101010110100";
WHEN "1010010" => memoryC1_uid208_sinPiZTableGenerator_q <= "101000000110100001011";
WHEN "1010011" => memoryC1_uid208_sinPiZTableGenerator_q <= "100111110111110101011";
WHEN "1010100" => memoryC1_uid208_sinPiZTableGenerator_q <= "100111101001010010000";
WHEN "1010101" => memoryC1_uid208_sinPiZTableGenerator_q <= "100111011010110110110";
WHEN "1010110" => memoryC1_uid208_sinPiZTableGenerator_q <= "100111001100100101100";
WHEN "1010111" => memoryC1_uid208_sinPiZTableGenerator_q <= "100110111110011100011";
WHEN "1011000" => memoryC1_uid208_sinPiZTableGenerator_q <= "100110110000011100011";
WHEN "1011001" => memoryC1_uid208_sinPiZTableGenerator_q <= "100110100010100101110";
WHEN "1011010" => memoryC1_uid208_sinPiZTableGenerator_q <= "100110010100111000101";
WHEN "1011011" => memoryC1_uid208_sinPiZTableGenerator_q <= "100110000111010100001";
WHEN "1011100" => memoryC1_uid208_sinPiZTableGenerator_q <= "100101111001111001000";
WHEN "1011101" => memoryC1_uid208_sinPiZTableGenerator_q <= "100101101100100111111";
WHEN "1011110" => memoryC1_uid208_sinPiZTableGenerator_q <= "100101011111100000000";
WHEN "1011111" => memoryC1_uid208_sinPiZTableGenerator_q <= "100101010010100001001";
WHEN "1100000" => memoryC1_uid208_sinPiZTableGenerator_q <= "100101000101101100011";
WHEN "1100001" => memoryC1_uid208_sinPiZTableGenerator_q <= "100100111001000001011";
WHEN "1100010" => memoryC1_uid208_sinPiZTableGenerator_q <= "100100101100011111111";
WHEN "1100011" => memoryC1_uid208_sinPiZTableGenerator_q <= "100100100000001000010";
WHEN "1100100" => memoryC1_uid208_sinPiZTableGenerator_q <= "100100010011111010101";
WHEN "1100101" => memoryC1_uid208_sinPiZTableGenerator_q <= "100100000111110111001";
WHEN "1100110" => memoryC1_uid208_sinPiZTableGenerator_q <= "100011111011111101010";
WHEN "1100111" => memoryC1_uid208_sinPiZTableGenerator_q <= "100011110000001101010";
WHEN "1101000" => memoryC1_uid208_sinPiZTableGenerator_q <= "100011100100100111101";
WHEN "1101001" => memoryC1_uid208_sinPiZTableGenerator_q <= "100011011001001011111";
WHEN "1101010" => memoryC1_uid208_sinPiZTableGenerator_q <= "100011001101111011010";
WHEN "1101011" => memoryC1_uid208_sinPiZTableGenerator_q <= "100011000010110100001";
WHEN "1101100" => memoryC1_uid208_sinPiZTableGenerator_q <= "100010110111110111010";
WHEN "1101101" => memoryC1_uid208_sinPiZTableGenerator_q <= "100010101101000101000";
WHEN "1101110" => memoryC1_uid208_sinPiZTableGenerator_q <= "100010100010011101001";
WHEN "1101111" => memoryC1_uid208_sinPiZTableGenerator_q <= "100010011000000000001";
WHEN "1110000" => memoryC1_uid208_sinPiZTableGenerator_q <= "100010001101101101010";
WHEN "1110001" => memoryC1_uid208_sinPiZTableGenerator_q <= "100010000011100100111";
WHEN "1110010" => memoryC1_uid208_sinPiZTableGenerator_q <= "100001111001100111100";
WHEN "1110011" => memoryC1_uid208_sinPiZTableGenerator_q <= "100001101111110100101";
WHEN "1110100" => memoryC1_uid208_sinPiZTableGenerator_q <= "100001100110001100100";
WHEN "1110101" => memoryC1_uid208_sinPiZTableGenerator_q <= "100001011100101111001";
WHEN "1110110" => memoryC1_uid208_sinPiZTableGenerator_q <= "100001010011011100011";
WHEN "1110111" => memoryC1_uid208_sinPiZTableGenerator_q <= "100001001010010100101";
WHEN "1111000" => memoryC1_uid208_sinPiZTableGenerator_q <= "100001000001011000000";
WHEN "1111001" => memoryC1_uid208_sinPiZTableGenerator_q <= "100000111000100110100";
WHEN "1111010" => memoryC1_uid208_sinPiZTableGenerator_q <= "100000101111111111100";
WHEN "1111011" => memoryC1_uid208_sinPiZTableGenerator_q <= "100000100111100011111";
WHEN "1111100" => memoryC1_uid208_sinPiZTableGenerator_q <= "100000011111010011000";
WHEN "1111101" => memoryC1_uid208_sinPiZTableGenerator_q <= "100000010111001101010";
WHEN "1111110" => memoryC1_uid208_sinPiZTableGenerator_q <= "100000001111010010101";
WHEN "1111111" => memoryC1_uid208_sinPiZTableGenerator_q <= "100000000111100011001";
WHEN OTHERS =>
memoryC1_uid208_sinPiZTableGenerator_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--sumAHighB_uid214_sinPiZPolyEval(ADD,213)@8
sumAHighB_uid214_sinPiZPolyEval_a <= STD_LOGIC_VECTOR((21 downto 21 => memoryC1_uid208_sinPiZTableGenerator_q(20)) & memoryC1_uid208_sinPiZTableGenerator_q);
sumAHighB_uid214_sinPiZPolyEval_b <= STD_LOGIC_VECTOR((21 downto 14 => highBBits_uid213_sinPiZPolyEval_b(13)) & highBBits_uid213_sinPiZPolyEval_b);
sumAHighB_uid214_sinPiZPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid214_sinPiZPolyEval_a) + SIGNED(sumAHighB_uid214_sinPiZPolyEval_b));
sumAHighB_uid214_sinPiZPolyEval_q <= sumAHighB_uid214_sinPiZPolyEval_o(21 downto 0);
--lowRangeB_uid212_sinPiZPolyEval(BITSELECT,211)@8
lowRangeB_uid212_sinPiZPolyEval_in <= prodXYTruncFR_uid227_pT1_uid211_sinPiZPolyEval_b(0 downto 0);
lowRangeB_uid212_sinPiZPolyEval_b <= lowRangeB_uid212_sinPiZPolyEval_in(0 downto 0);
--s1_uid212_uid215_sinPiZPolyEval(BITJOIN,214)@8
s1_uid212_uid215_sinPiZPolyEval_q <= sumAHighB_uid214_sinPiZPolyEval_q & lowRangeB_uid212_sinPiZPolyEval_b;
--reg_s1_uid212_uid215_sinPiZPolyEval_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_1(REG,267)@8
reg_s1_uid212_uid215_sinPiZPolyEval_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_s1_uid212_uid215_sinPiZPolyEval_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_1_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_s1_uid212_uid215_sinPiZPolyEval_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_1_q <= s1_uid212_uid215_sinPiZPolyEval_q;
END IF;
END IF;
END PROCESS;
--ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_nor(LOGICAL,609)
ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_nor_a <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_notEnable_q;
ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_nor_b <= ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_sticky_ena_q;
ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_nor_q <= not (ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_nor_a or ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_nor_b);
--ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_sticky_ena(REG,610)
ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_nor_q = "1") THEN
ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_sticky_ena_q <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_enaAnd(LOGICAL,611)
ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_enaAnd_a <= ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_sticky_ena_q;
ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_enaAnd_b <= en;
ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_enaAnd_q <= ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_enaAnd_a and ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_enaAnd_b;
--ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_inputreg(DELAY,599)
ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 16, depth => 1 )
PORT MAP ( xin => zPPolyEval_uid63_fpCosPiTest_b, xout => ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem(DUALMEM,600)
ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_reset0 <= areset;
ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_ia <= ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_inputreg_q;
ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_aa <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdreg_q;
ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_ab <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdmux_q;
ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 16,
widthad_a => 2,
numwords_a => 3,
width_b => 16,
widthad_b => 2,
numwords_b => 3,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_iq,
address_a => ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_aa,
data_a => ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_ia
);
ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_q <= ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_iq(15 downto 0);
--reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0(REG,266)@8
reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_q <= ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--prodXY_uid229_pT2_uid217_sinPiZPolyEval(MULT,228)@9
prodXY_uid229_pT2_uid217_sinPiZPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid229_pT2_uid217_sinPiZPolyEval_a),17)) * SIGNED(prodXY_uid229_pT2_uid217_sinPiZPolyEval_b);
prodXY_uid229_pT2_uid217_sinPiZPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid229_pT2_uid217_sinPiZPolyEval_a <= (others => '0');
prodXY_uid229_pT2_uid217_sinPiZPolyEval_b <= (others => '0');
prodXY_uid229_pT2_uid217_sinPiZPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid229_pT2_uid217_sinPiZPolyEval_a <= reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_q;
prodXY_uid229_pT2_uid217_sinPiZPolyEval_b <= reg_s1_uid212_uid215_sinPiZPolyEval_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_1_q;
prodXY_uid229_pT2_uid217_sinPiZPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid229_pT2_uid217_sinPiZPolyEval_pr,39));
END IF;
END IF;
END PROCESS;
prodXY_uid229_pT2_uid217_sinPiZPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid229_pT2_uid217_sinPiZPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid229_pT2_uid217_sinPiZPolyEval_q <= prodXY_uid229_pT2_uid217_sinPiZPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid230_pT2_uid217_sinPiZPolyEval(BITSELECT,229)@12
prodXYTruncFR_uid230_pT2_uid217_sinPiZPolyEval_in <= prodXY_uid229_pT2_uid217_sinPiZPolyEval_q;
prodXYTruncFR_uid230_pT2_uid217_sinPiZPolyEval_b <= prodXYTruncFR_uid230_pT2_uid217_sinPiZPolyEval_in(38 downto 15);
--highBBits_uid219_sinPiZPolyEval(BITSELECT,218)@12
highBBits_uid219_sinPiZPolyEval_in <= prodXYTruncFR_uid230_pT2_uid217_sinPiZPolyEval_b;
highBBits_uid219_sinPiZPolyEval_b <= highBBits_uid219_sinPiZPolyEval_in(23 downto 2);
--ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_nor(LOGICAL,584)
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_nor_a <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_notEnable_q;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_nor_b <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_sticky_ena_q;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_nor_q <= not (ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_nor_a or ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_nor_b);
--ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_mem_top(CONSTANT,554)
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_mem_top_q <= "0110";
--ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_cmp(LOGICAL,555)
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_cmp_a <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_mem_top_q;
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdmux_q);
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_cmp_q <= "1" when ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_cmp_a = ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_cmp_b else "0";
--ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_cmpReg(REG,556)
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_cmpReg_q <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_sticky_ena(REG,585)
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_nor_q = "1") THEN
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_sticky_ena_q <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_enaAnd(LOGICAL,586)
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_enaAnd_a <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_sticky_ena_q;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_enaAnd_b <= en;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_enaAnd_q <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_enaAnd_a and ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_enaAnd_b;
--ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt(COUNTER,550)
-- every=1, low=0, high=6, step=1, init=1
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt_i = 5 THEN
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt_eq <= '1';
ELSE
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt_eq = '1') THEN
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt_i <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt_i - 6;
ELSE
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt_i <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt_i,3));
--ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdreg(REG,551)
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdreg_q <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdmux(MUX,552)
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdmux_s <= en;
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdmux: PROCESS (ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdmux_s, ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdreg_q, ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt_q)
BEGIN
CASE ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdmux_s IS
WHEN "0" => ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdmux_q <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdreg_q;
WHEN "1" => ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdmux_q <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem(DUALMEM,575)
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_reset0 <= areset;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_ia <= reg_zAddr_uid62_fpCosPiTest_0_to_memoryC2_uid209_sinPiZTableGenerator_0_q;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_aa <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdreg_q;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_ab <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdmux_q;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 7,
widthad_a => 3,
numwords_a => 7,
width_b => 7,
widthad_b => 3,
numwords_b => 7,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_iq,
address_a => ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_aa,
data_a => ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_ia
);
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_q <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_iq(6 downto 0);
--memoryC0_uid207_sinPiZTableGenerator(LOOKUP,206)@12
memoryC0_uid207_sinPiZTableGenerator: PROCESS (ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_q)
BEGIN
-- Begin reserved scope level
CASE (ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_q) IS
WHEN "0000000" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100100100001111110110101110";
WHEN "0000001" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100100100001110100100000010";
WHEN "0000010" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100100100001010101100000000";
WHEN "0000011" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100100100000100001110101000";
WHEN "0000100" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100100011111011001011111101";
WHEN "0000101" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100100011101111100100000010";
WHEN "0000110" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100100011100001010110111011";
WHEN "0000111" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100100011010000100100101111";
WHEN "0001000" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100100010111101001101100010";
WHEN "0001001" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100100010100111010001011101";
WHEN "0001010" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100100010001110110000100111";
WHEN "0001011" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100100001110011101011001001";
WHEN "0001100" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100100001010110000001001110";
WHEN "0001101" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100100000110101110011000000";
WHEN "0001110" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100100000010011000000101011";
WHEN "0001111" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100011111101101101010011101";
WHEN "0010000" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100011111000101110000100010";
WHEN "0010001" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100011110011011010011001011";
WHEN "0010010" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100011101101110010010100101";
WHEN "0010011" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100011100111110101111000011";
WHEN "0010100" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100011100001100101000110101";
WHEN "0010101" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100011011011000000000001111";
WHEN "0010110" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100011010100000110101100011";
WHEN "0010111" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100011001100111001001000110";
WHEN "0011000" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100011000101010111011001110";
WHEN "0011001" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100010111101100001100010000";
WHEN "0011010" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100010110101010111100100100";
WHEN "0011011" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100010101100111001100100010";
WHEN "0011100" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100010100100000111100100011";
WHEN "0011101" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100010011011000001101000000";
WHEN "0011110" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100010010001100111110010110";
WHEN "0011111" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100010000111111010000111111";
WHEN "0100000" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100001111101111000101010111";
WHEN "0100001" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100001110011100011011111110";
WHEN "0100010" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100001101000111010101010001";
WHEN "0100011" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100001011101111110001110000";
WHEN "0100100" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100001010010101110001111010";
WHEN "0100101" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100001000111001010110010010";
WHEN "0100110" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100000111011010011111011001";
WHEN "0100111" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100000101111001001101110010";
WHEN "0101000" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100000100010101100010000001";
WHEN "0101001" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100000010101111011100101011";
WHEN "0101010" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100000001000110111110010101";
WHEN "0101011" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011111111011100000111100110";
WHEN "0101100" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011111101101110111001000101";
WHEN "0101101" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011111011111111010011011011";
WHEN "0101110" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011111010001101010111001111";
WHEN "0101111" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011111000011001000101001110";
WHEN "0110000" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011110110100010011110000000";
WHEN "0110001" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011110100101001100010010010";
WHEN "0110010" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011110010101110010010110000";
WHEN "0110011" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011110000110000110000001000";
WHEN "0110100" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011101110110000111011000111";
WHEN "0110101" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011101100101110110100011101";
WHEN "0110110" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011101010101010011100111001";
WHEN "0110111" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011101000100011110101001100";
WHEN "0111000" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011100110011010111110000111";
WHEN "0111001" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011100100001111111000011101";
WHEN "0111010" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011100010000010100101000000";
WHEN "0111011" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011011111110011000100100100";
WHEN "0111100" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011011101100001010111111110";
WHEN "0111101" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011011011001101100000000011";
WHEN "0111110" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011011000110111011101101010";
WHEN "0111111" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011010110011111010001101001";
WHEN "1000000" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011010100000100111100111000";
WHEN "1000001" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011010001101000100000001111";
WHEN "1000010" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011001111001001111100100111";
WHEN "1000011" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011001100101001010010111011";
WHEN "1000100" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011001010000110100100000101";
WHEN "1000101" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011000111100001110001000001";
WHEN "1000110" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011000100111010111010101011";
WHEN "1000111" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011000010010010000001111111";
WHEN "1001000" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010111111100111000111111011";
WHEN "1001001" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010111100111010001101011110";
WHEN "1001010" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010111010001011010011100110";
WHEN "1001011" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010110111011010011011010011";
WHEN "1001100" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010110100100111100101100110";
WHEN "1001101" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010110001110010110011011111";
WHEN "1001110" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010101110111100000110000001";
WHEN "1001111" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010101100000011011110001110";
WHEN "1010000" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010101001001000111101001000";
WHEN "1010001" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010100110001100100011110100";
WHEN "1010010" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010100011001110010011010110";
WHEN "1010011" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010100000001110001100110010";
WHEN "1010100" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010011101001100010001001111";
WHEN "1010101" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010011010001000100001110100";
WHEN "1010110" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010010111000010111111100101";
WHEN "1010111" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010010011111011101011101100";
WHEN "1011000" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010010000110010100111010001";
WHEN "1011001" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010001101100111110011011011";
WHEN "1011010" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010001010011011010001010100";
WHEN "1011011" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010000111001101000010000111";
WHEN "1011100" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010000011111101000110111110";
WHEN "1011101" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010000000101011100001000010";
WHEN "1011110" => memoryC0_uid207_sinPiZTableGenerator_q <= "01001111101011000010001100001";
WHEN "1011111" => memoryC0_uid207_sinPiZTableGenerator_q <= "01001111010000011011001100111";
WHEN "1100000" => memoryC0_uid207_sinPiZTableGenerator_q <= "01001110110101100111010011111";
WHEN "1100001" => memoryC0_uid207_sinPiZTableGenerator_q <= "01001110011010100110101010111";
WHEN "1100010" => memoryC0_uid207_sinPiZTableGenerator_q <= "01001101111111011001011011101";
WHEN "1100011" => memoryC0_uid207_sinPiZTableGenerator_q <= "01001101100011111111101111111";
WHEN "1100100" => memoryC0_uid207_sinPiZTableGenerator_q <= "01001101001000011001110001011";
WHEN "1100101" => memoryC0_uid207_sinPiZTableGenerator_q <= "01001100101100100111101010001";
WHEN "1100110" => memoryC0_uid207_sinPiZTableGenerator_q <= "01001100010000101001100100001";
WHEN "1100111" => memoryC0_uid207_sinPiZTableGenerator_q <= "01001011110100011111101001011";
WHEN "1101000" => memoryC0_uid207_sinPiZTableGenerator_q <= "01001011011000001010000011111";
WHEN "1101001" => memoryC0_uid207_sinPiZTableGenerator_q <= "01001010111011101000111101111";
WHEN "1101010" => memoryC0_uid207_sinPiZTableGenerator_q <= "01001010011110111100100001011";
WHEN "1101011" => memoryC0_uid207_sinPiZTableGenerator_q <= "01001010000010000100111000111";
WHEN "1101100" => memoryC0_uid207_sinPiZTableGenerator_q <= "01001001100101000010001110101";
WHEN "1101101" => memoryC0_uid207_sinPiZTableGenerator_q <= "01001001000111110100101100111";
WHEN "1101110" => memoryC0_uid207_sinPiZTableGenerator_q <= "01001000101010011100011110001";
WHEN "1101111" => memoryC0_uid207_sinPiZTableGenerator_q <= "01001000001100111001101100110";
WHEN "1110000" => memoryC0_uid207_sinPiZTableGenerator_q <= "01000111101111001100100011011";
WHEN "1110001" => memoryC0_uid207_sinPiZTableGenerator_q <= "01000111010001010101001100101";
WHEN "1110010" => memoryC0_uid207_sinPiZTableGenerator_q <= "01000110110011010011110010111";
WHEN "1110011" => memoryC0_uid207_sinPiZTableGenerator_q <= "01000110010101001000100001000";
WHEN "1110100" => memoryC0_uid207_sinPiZTableGenerator_q <= "01000101110110110011100001101";
WHEN "1110101" => memoryC0_uid207_sinPiZTableGenerator_q <= "01000101011000010100111111100";
WHEN "1110110" => memoryC0_uid207_sinPiZTableGenerator_q <= "01000100111001101101000101100";
WHEN "1110111" => memoryC0_uid207_sinPiZTableGenerator_q <= "01000100011010111011111110011";
WHEN "1111000" => memoryC0_uid207_sinPiZTableGenerator_q <= "01000011111100000001110101000";
WHEN "1111001" => memoryC0_uid207_sinPiZTableGenerator_q <= "01000011011100111110110100010";
WHEN "1111010" => memoryC0_uid207_sinPiZTableGenerator_q <= "01000010111101110011000111010";
WHEN "1111011" => memoryC0_uid207_sinPiZTableGenerator_q <= "01000010011110011110111000111";
WHEN "1111100" => memoryC0_uid207_sinPiZTableGenerator_q <= "01000001111111000010010100010";
WHEN "1111101" => memoryC0_uid207_sinPiZTableGenerator_q <= "01000001011111011101100100011";
WHEN "1111110" => memoryC0_uid207_sinPiZTableGenerator_q <= "01000000111111110000110100011";
WHEN "1111111" => memoryC0_uid207_sinPiZTableGenerator_q <= "01000000011111111100001111011";
WHEN OTHERS =>
memoryC0_uid207_sinPiZTableGenerator_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--sumAHighB_uid220_sinPiZPolyEval(ADD,219)@12
sumAHighB_uid220_sinPiZPolyEval_a <= STD_LOGIC_VECTOR((29 downto 29 => memoryC0_uid207_sinPiZTableGenerator_q(28)) & memoryC0_uid207_sinPiZTableGenerator_q);
sumAHighB_uid220_sinPiZPolyEval_b <= STD_LOGIC_VECTOR((29 downto 22 => highBBits_uid219_sinPiZPolyEval_b(21)) & highBBits_uid219_sinPiZPolyEval_b);
sumAHighB_uid220_sinPiZPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid220_sinPiZPolyEval_a) + SIGNED(sumAHighB_uid220_sinPiZPolyEval_b));
sumAHighB_uid220_sinPiZPolyEval_q <= sumAHighB_uid220_sinPiZPolyEval_o(29 downto 0);
--lowRangeB_uid218_sinPiZPolyEval(BITSELECT,217)@12
lowRangeB_uid218_sinPiZPolyEval_in <= prodXYTruncFR_uid230_pT2_uid217_sinPiZPolyEval_b(1 downto 0);
lowRangeB_uid218_sinPiZPolyEval_b <= lowRangeB_uid218_sinPiZPolyEval_in(1 downto 0);
--s2_uid218_uid221_sinPiZPolyEval(BITJOIN,220)@12
s2_uid218_uid221_sinPiZPolyEval_q <= sumAHighB_uid220_sinPiZPolyEval_q & lowRangeB_uid218_sinPiZPolyEval_b;
--fxpSinRes_uid65_fpCosPiTest(BITSELECT,64)@12
fxpSinRes_uid65_fpCosPiTest_in <= s2_uid218_uid221_sinPiZPolyEval_q(29 downto 0);
fxpSinRes_uid65_fpCosPiTest_b <= fxpSinRes_uid65_fpCosPiTest_in(29 downto 5);
--reg_fxpSinRes_uid65_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_1(REG,270)@12
reg_fxpSinRes_uid65_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fxpSinRes_uid65_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_1_q <= "0000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fxpSinRes_uid65_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_1_q <= fxpSinRes_uid65_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_nor(LOGICAL,622)
ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_nor_a <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_notEnable_q;
ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_nor_b <= ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_sticky_ena_q;
ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_nor_q <= not (ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_nor_a or ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_nor_b);
--ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_sticky_ena(REG,623)
ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_nor_q = "1") THEN
ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_sticky_ena_q <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_enaAnd(LOGICAL,624)
ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_enaAnd_a <= ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_sticky_ena_q;
ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_enaAnd_b <= en;
ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_enaAnd_q <= ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_enaAnd_a and ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_enaAnd_b;
--LeftShiftStage131dto0_uid202_alignedZ_uid57_fpCosPiTest(BITSELECT,201)@7
LeftShiftStage131dto0_uid202_alignedZ_uid57_fpCosPiTest_in <= leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_q(31 downto 0);
LeftShiftStage131dto0_uid202_alignedZ_uid57_fpCosPiTest_b <= LeftShiftStage131dto0_uid202_alignedZ_uid57_fpCosPiTest_in(31 downto 0);
--leftShiftStage2Idx3_uid203_alignedZ_uid57_fpCosPiTest(BITJOIN,202)@7
leftShiftStage2Idx3_uid203_alignedZ_uid57_fpCosPiTest_q <= LeftShiftStage131dto0_uid202_alignedZ_uid57_fpCosPiTest_b & leftShiftStage2Idx3Pad3_uid131_fxpX_uid41_fpCosPiTest_q;
--LeftShiftStage132dto0_uid199_alignedZ_uid57_fpCosPiTest(BITSELECT,198)@7
LeftShiftStage132dto0_uid199_alignedZ_uid57_fpCosPiTest_in <= leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_q(32 downto 0);
LeftShiftStage132dto0_uid199_alignedZ_uid57_fpCosPiTest_b <= LeftShiftStage132dto0_uid199_alignedZ_uid57_fpCosPiTest_in(32 downto 0);
--leftShiftStage2Idx2_uid200_alignedZ_uid57_fpCosPiTest(BITJOIN,199)@7
leftShiftStage2Idx2_uid200_alignedZ_uid57_fpCosPiTest_q <= LeftShiftStage132dto0_uid199_alignedZ_uid57_fpCosPiTest_b & leftShiftStage2Idx2Pad2_uid128_fxpX_uid41_fpCosPiTest_q;
--LeftShiftStage133dto0_uid196_alignedZ_uid57_fpCosPiTest(BITSELECT,195)@7
LeftShiftStage133dto0_uid196_alignedZ_uid57_fpCosPiTest_in <= leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_q(33 downto 0);
LeftShiftStage133dto0_uid196_alignedZ_uid57_fpCosPiTest_b <= LeftShiftStage133dto0_uid196_alignedZ_uid57_fpCosPiTest_in(33 downto 0);
--leftShiftStage2Idx1_uid197_alignedZ_uid57_fpCosPiTest(BITJOIN,196)@7
leftShiftStage2Idx1_uid197_alignedZ_uid57_fpCosPiTest_q <= LeftShiftStage133dto0_uid196_alignedZ_uid57_fpCosPiTest_b & GND_q;
--vStage_uid141_lzcZ_uid56_fpCosPiTest(BITSELECT,140)@3
vStage_uid141_lzcZ_uid56_fpCosPiTest_in <= z_uid54_fpCosPiTest_b(2 downto 0);
vStage_uid141_lzcZ_uid56_fpCosPiTest_b <= vStage_uid141_lzcZ_uid56_fpCosPiTest_in(2 downto 0);
--ld_vStage_uid141_lzcZ_uid56_fpCosPiTest_b_to_leftShiftStage0Idx2_uid180_alignedZ_uid57_fpCosPiTest_b(DELAY,450)@3
ld_vStage_uid141_lzcZ_uid56_fpCosPiTest_b_to_leftShiftStage0Idx2_uid180_alignedZ_uid57_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 3, depth => 3 )
PORT MAP ( xin => vStage_uid141_lzcZ_uid56_fpCosPiTest_b, xout => ld_vStage_uid141_lzcZ_uid56_fpCosPiTest_b_to_leftShiftStage0Idx2_uid180_alignedZ_uid57_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage0Idx2_uid180_alignedZ_uid57_fpCosPiTest(BITJOIN,179)@6
leftShiftStage0Idx2_uid180_alignedZ_uid57_fpCosPiTest_q <= ld_vStage_uid141_lzcZ_uid56_fpCosPiTest_b_to_leftShiftStage0Idx2_uid180_alignedZ_uid57_fpCosPiTest_b_q & leftShiftStage0Idx2Pad32_uid108_fxpX_uid41_fpCosPiTest_q;
--X18dto0_uid176_alignedZ_uid57_fpCosPiTest(BITSELECT,175)@3
X18dto0_uid176_alignedZ_uid57_fpCosPiTest_in <= z_uid54_fpCosPiTest_b(18 downto 0);
X18dto0_uid176_alignedZ_uid57_fpCosPiTest_b <= X18dto0_uid176_alignedZ_uid57_fpCosPiTest_in(18 downto 0);
--ld_X18dto0_uid176_alignedZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx1_uid177_alignedZ_uid57_fpCosPiTest_b_inputreg(DELAY,573)
ld_X18dto0_uid176_alignedZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx1_uid177_alignedZ_uid57_fpCosPiTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 19, depth => 1 )
PORT MAP ( xin => X18dto0_uid176_alignedZ_uid57_fpCosPiTest_b, xout => ld_X18dto0_uid176_alignedZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx1_uid177_alignedZ_uid57_fpCosPiTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_X18dto0_uid176_alignedZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx1_uid177_alignedZ_uid57_fpCosPiTest_b(DELAY,449)@3
ld_X18dto0_uid176_alignedZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx1_uid177_alignedZ_uid57_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 19, depth => 2 )
PORT MAP ( xin => ld_X18dto0_uid176_alignedZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx1_uid177_alignedZ_uid57_fpCosPiTest_b_inputreg_q, xout => ld_X18dto0_uid176_alignedZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx1_uid177_alignedZ_uid57_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage0Idx1_uid177_alignedZ_uid57_fpCosPiTest(BITJOIN,176)@6
leftShiftStage0Idx1_uid177_alignedZ_uid57_fpCosPiTest_q <= ld_X18dto0_uid176_alignedZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx1_uid177_alignedZ_uid57_fpCosPiTest_b_q & leftShiftStage0Idx1Pad16_uid105_fxpX_uid41_fpCosPiTest_q;
--ld_z_uid54_fpCosPiTest_b_to_leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_c_inputreg(DELAY,574)
ld_z_uid54_fpCosPiTest_b_to_leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 35, depth => 1 )
PORT MAP ( xin => z_uid54_fpCosPiTest_b, xout => ld_z_uid54_fpCosPiTest_b_to_leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_z_uid54_fpCosPiTest_b_to_leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_c(DELAY,453)@3
ld_z_uid54_fpCosPiTest_b_to_leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_c : dspba_delay
GENERIC MAP ( width => 35, depth => 2 )
PORT MAP ( xin => ld_z_uid54_fpCosPiTest_b_to_leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_c_inputreg_q, xout => ld_z_uid54_fpCosPiTest_b_to_leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--rVStage_uid138_lzcZ_uid56_fpCosPiTest(BITSELECT,137)@3
rVStage_uid138_lzcZ_uid56_fpCosPiTest_in <= z_uid54_fpCosPiTest_b;
rVStage_uid138_lzcZ_uid56_fpCosPiTest_b <= rVStage_uid138_lzcZ_uid56_fpCosPiTest_in(34 downto 3);
--reg_rVStage_uid138_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid139_lzcZ_uid56_fpCosPiTest_1(REG,247)@3
reg_rVStage_uid138_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid139_lzcZ_uid56_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid138_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid139_lzcZ_uid56_fpCosPiTest_1_q <= "00000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid138_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid139_lzcZ_uid56_fpCosPiTest_1_q <= rVStage_uid138_lzcZ_uid56_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid139_lzcZ_uid56_fpCosPiTest(LOGICAL,138)@4
vCount_uid139_lzcZ_uid56_fpCosPiTest_a <= reg_rVStage_uid138_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid139_lzcZ_uid56_fpCosPiTest_1_q;
vCount_uid139_lzcZ_uid56_fpCosPiTest_b <= leftShiftStage0Idx2Pad32_uid108_fxpX_uid41_fpCosPiTest_q;
vCount_uid139_lzcZ_uid56_fpCosPiTest_q <= "1" when vCount_uid139_lzcZ_uid56_fpCosPiTest_a = vCount_uid139_lzcZ_uid56_fpCosPiTest_b else "0";
--ld_vCount_uid139_lzcZ_uid56_fpCosPiTest_q_to_r_uid172_lzcZ_uid56_fpCosPiTest_f(DELAY,447)@4
ld_vCount_uid139_lzcZ_uid56_fpCosPiTest_q_to_r_uid172_lzcZ_uid56_fpCosPiTest_f : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => vCount_uid139_lzcZ_uid56_fpCosPiTest_q, xout => ld_vCount_uid139_lzcZ_uid56_fpCosPiTest_q_to_r_uid172_lzcZ_uid56_fpCosPiTest_f_q, ena => en(0), clk => clk, aclr => areset );
--mO_uid140_lzcZ_uid56_fpCosPiTest(CONSTANT,139)
mO_uid140_lzcZ_uid56_fpCosPiTest_q <= "11111111111111111111111111111";
--cStage_uid142_lzcZ_uid56_fpCosPiTest(BITJOIN,141)@3
cStage_uid142_lzcZ_uid56_fpCosPiTest_q <= vStage_uid141_lzcZ_uid56_fpCosPiTest_b & mO_uid140_lzcZ_uid56_fpCosPiTest_q;
--reg_cStage_uid142_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid144_lzcZ_uid56_fpCosPiTest_3(REG,249)@3
reg_cStage_uid142_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid144_lzcZ_uid56_fpCosPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cStage_uid142_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid144_lzcZ_uid56_fpCosPiTest_3_q <= "00000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cStage_uid142_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid144_lzcZ_uid56_fpCosPiTest_3_q <= cStage_uid142_lzcZ_uid56_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--vStagei_uid144_lzcZ_uid56_fpCosPiTest(MUX,143)@4
vStagei_uid144_lzcZ_uid56_fpCosPiTest_s <= vCount_uid139_lzcZ_uid56_fpCosPiTest_q;
vStagei_uid144_lzcZ_uid56_fpCosPiTest: PROCESS (vStagei_uid144_lzcZ_uid56_fpCosPiTest_s, en, reg_rVStage_uid138_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid139_lzcZ_uid56_fpCosPiTest_1_q, reg_cStage_uid142_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid144_lzcZ_uid56_fpCosPiTest_3_q)
BEGIN
CASE vStagei_uid144_lzcZ_uid56_fpCosPiTest_s IS
WHEN "0" => vStagei_uid144_lzcZ_uid56_fpCosPiTest_q <= reg_rVStage_uid138_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid139_lzcZ_uid56_fpCosPiTest_1_q;
WHEN "1" => vStagei_uid144_lzcZ_uid56_fpCosPiTest_q <= reg_cStage_uid142_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid144_lzcZ_uid56_fpCosPiTest_3_q;
WHEN OTHERS => vStagei_uid144_lzcZ_uid56_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid146_lzcZ_uid56_fpCosPiTest(BITSELECT,145)@4
rVStage_uid146_lzcZ_uid56_fpCosPiTest_in <= vStagei_uid144_lzcZ_uid56_fpCosPiTest_q;
rVStage_uid146_lzcZ_uid56_fpCosPiTest_b <= rVStage_uid146_lzcZ_uid56_fpCosPiTest_in(31 downto 16);
--reg_rVStage_uid146_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid147_lzcZ_uid56_fpCosPiTest_1(REG,250)@4
reg_rVStage_uid146_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid147_lzcZ_uid56_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid146_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid147_lzcZ_uid56_fpCosPiTest_1_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid146_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid147_lzcZ_uid56_fpCosPiTest_1_q <= rVStage_uid146_lzcZ_uid56_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid147_lzcZ_uid56_fpCosPiTest(LOGICAL,146)@5
vCount_uid147_lzcZ_uid56_fpCosPiTest_a <= reg_rVStage_uid146_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid147_lzcZ_uid56_fpCosPiTest_1_q;
vCount_uid147_lzcZ_uid56_fpCosPiTest_b <= leftShiftStage0Idx1Pad16_uid105_fxpX_uid41_fpCosPiTest_q;
vCount_uid147_lzcZ_uid56_fpCosPiTest_q <= "1" when vCount_uid147_lzcZ_uid56_fpCosPiTest_a = vCount_uid147_lzcZ_uid56_fpCosPiTest_b else "0";
--ld_vCount_uid147_lzcZ_uid56_fpCosPiTest_q_to_r_uid172_lzcZ_uid56_fpCosPiTest_e(DELAY,446)@5
ld_vCount_uid147_lzcZ_uid56_fpCosPiTest_q_to_r_uid172_lzcZ_uid56_fpCosPiTest_e : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vCount_uid147_lzcZ_uid56_fpCosPiTest_q, xout => ld_vCount_uid147_lzcZ_uid56_fpCosPiTest_q_to_r_uid172_lzcZ_uid56_fpCosPiTest_e_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid148_lzcZ_uid56_fpCosPiTest(BITSELECT,147)@4
vStage_uid148_lzcZ_uid56_fpCosPiTest_in <= vStagei_uid144_lzcZ_uid56_fpCosPiTest_q(15 downto 0);
vStage_uid148_lzcZ_uid56_fpCosPiTest_b <= vStage_uid148_lzcZ_uid56_fpCosPiTest_in(15 downto 0);
--reg_vStage_uid148_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid150_lzcZ_uid56_fpCosPiTest_3(REG,252)@4
reg_vStage_uid148_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid150_lzcZ_uid56_fpCosPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid148_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid150_lzcZ_uid56_fpCosPiTest_3_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid148_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid150_lzcZ_uid56_fpCosPiTest_3_q <= vStage_uid148_lzcZ_uid56_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid150_lzcZ_uid56_fpCosPiTest(MUX,149)@5
vStagei_uid150_lzcZ_uid56_fpCosPiTest_s <= vCount_uid147_lzcZ_uid56_fpCosPiTest_q;
vStagei_uid150_lzcZ_uid56_fpCosPiTest: PROCESS (vStagei_uid150_lzcZ_uid56_fpCosPiTest_s, en, reg_rVStage_uid146_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid147_lzcZ_uid56_fpCosPiTest_1_q, reg_vStage_uid148_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid150_lzcZ_uid56_fpCosPiTest_3_q)
BEGIN
CASE vStagei_uid150_lzcZ_uid56_fpCosPiTest_s IS
WHEN "0" => vStagei_uid150_lzcZ_uid56_fpCosPiTest_q <= reg_rVStage_uid146_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid147_lzcZ_uid56_fpCosPiTest_1_q;
WHEN "1" => vStagei_uid150_lzcZ_uid56_fpCosPiTest_q <= reg_vStage_uid148_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid150_lzcZ_uid56_fpCosPiTest_3_q;
WHEN OTHERS => vStagei_uid150_lzcZ_uid56_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid152_lzcZ_uid56_fpCosPiTest(BITSELECT,151)@5
rVStage_uid152_lzcZ_uid56_fpCosPiTest_in <= vStagei_uid150_lzcZ_uid56_fpCosPiTest_q;
rVStage_uid152_lzcZ_uid56_fpCosPiTest_b <= rVStage_uid152_lzcZ_uid56_fpCosPiTest_in(15 downto 8);
--vCount_uid153_lzcZ_uid56_fpCosPiTest(LOGICAL,152)@5
vCount_uid153_lzcZ_uid56_fpCosPiTest_a <= rVStage_uid152_lzcZ_uid56_fpCosPiTest_b;
vCount_uid153_lzcZ_uid56_fpCosPiTest_b <= cstAllZWE_uid21_fpCosPiTest_q;
vCount_uid153_lzcZ_uid56_fpCosPiTest_q <= "1" when vCount_uid153_lzcZ_uid56_fpCosPiTest_a = vCount_uid153_lzcZ_uid56_fpCosPiTest_b else "0";
--reg_vCount_uid153_lzcZ_uid56_fpCosPiTest_0_to_r_uid172_lzcZ_uid56_fpCosPiTest_3(REG,256)@5
reg_vCount_uid153_lzcZ_uid56_fpCosPiTest_0_to_r_uid172_lzcZ_uid56_fpCosPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid153_lzcZ_uid56_fpCosPiTest_0_to_r_uid172_lzcZ_uid56_fpCosPiTest_3_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid153_lzcZ_uid56_fpCosPiTest_0_to_r_uid172_lzcZ_uid56_fpCosPiTest_3_q <= vCount_uid153_lzcZ_uid56_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--vStage_uid154_lzcZ_uid56_fpCosPiTest(BITSELECT,153)@5
vStage_uid154_lzcZ_uid56_fpCosPiTest_in <= vStagei_uid150_lzcZ_uid56_fpCosPiTest_q(7 downto 0);
vStage_uid154_lzcZ_uid56_fpCosPiTest_b <= vStage_uid154_lzcZ_uid56_fpCosPiTest_in(7 downto 0);
--vStagei_uid156_lzcZ_uid56_fpCosPiTest(MUX,155)@5
vStagei_uid156_lzcZ_uid56_fpCosPiTest_s <= vCount_uid153_lzcZ_uid56_fpCosPiTest_q;
vStagei_uid156_lzcZ_uid56_fpCosPiTest: PROCESS (vStagei_uid156_lzcZ_uid56_fpCosPiTest_s, en, rVStage_uid152_lzcZ_uid56_fpCosPiTest_b, vStage_uid154_lzcZ_uid56_fpCosPiTest_b)
BEGIN
CASE vStagei_uid156_lzcZ_uid56_fpCosPiTest_s IS
WHEN "0" => vStagei_uid156_lzcZ_uid56_fpCosPiTest_q <= rVStage_uid152_lzcZ_uid56_fpCosPiTest_b;
WHEN "1" => vStagei_uid156_lzcZ_uid56_fpCosPiTest_q <= vStage_uid154_lzcZ_uid56_fpCosPiTest_b;
WHEN OTHERS => vStagei_uid156_lzcZ_uid56_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid158_lzcZ_uid56_fpCosPiTest(BITSELECT,157)@5
rVStage_uid158_lzcZ_uid56_fpCosPiTest_in <= vStagei_uid156_lzcZ_uid56_fpCosPiTest_q;
rVStage_uid158_lzcZ_uid56_fpCosPiTest_b <= rVStage_uid158_lzcZ_uid56_fpCosPiTest_in(7 downto 4);
--reg_rVStage_uid158_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid159_lzcZ_uid56_fpCosPiTest_1(REG,253)@5
reg_rVStage_uid158_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid159_lzcZ_uid56_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid158_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid159_lzcZ_uid56_fpCosPiTest_1_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid158_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid159_lzcZ_uid56_fpCosPiTest_1_q <= rVStage_uid158_lzcZ_uid56_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid159_lzcZ_uid56_fpCosPiTest(LOGICAL,158)@6
vCount_uid159_lzcZ_uid56_fpCosPiTest_a <= reg_rVStage_uid158_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid159_lzcZ_uid56_fpCosPiTest_1_q;
vCount_uid159_lzcZ_uid56_fpCosPiTest_b <= leftShiftStage1Idx1Pad4_uid114_fxpX_uid41_fpCosPiTest_q;
vCount_uid159_lzcZ_uid56_fpCosPiTest_q <= "1" when vCount_uid159_lzcZ_uid56_fpCosPiTest_a = vCount_uid159_lzcZ_uid56_fpCosPiTest_b else "0";
--vStage_uid160_lzcZ_uid56_fpCosPiTest(BITSELECT,159)@5
vStage_uid160_lzcZ_uid56_fpCosPiTest_in <= vStagei_uid156_lzcZ_uid56_fpCosPiTest_q(3 downto 0);
vStage_uid160_lzcZ_uid56_fpCosPiTest_b <= vStage_uid160_lzcZ_uid56_fpCosPiTest_in(3 downto 0);
--reg_vStage_uid160_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid162_lzcZ_uid56_fpCosPiTest_3(REG,255)@5
reg_vStage_uid160_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid162_lzcZ_uid56_fpCosPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid160_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid162_lzcZ_uid56_fpCosPiTest_3_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid160_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid162_lzcZ_uid56_fpCosPiTest_3_q <= vStage_uid160_lzcZ_uid56_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid162_lzcZ_uid56_fpCosPiTest(MUX,161)@6
vStagei_uid162_lzcZ_uid56_fpCosPiTest_s <= vCount_uid159_lzcZ_uid56_fpCosPiTest_q;
vStagei_uid162_lzcZ_uid56_fpCosPiTest: PROCESS (vStagei_uid162_lzcZ_uid56_fpCosPiTest_s, en, reg_rVStage_uid158_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid159_lzcZ_uid56_fpCosPiTest_1_q, reg_vStage_uid160_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid162_lzcZ_uid56_fpCosPiTest_3_q)
BEGIN
CASE vStagei_uid162_lzcZ_uid56_fpCosPiTest_s IS
WHEN "0" => vStagei_uid162_lzcZ_uid56_fpCosPiTest_q <= reg_rVStage_uid158_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid159_lzcZ_uid56_fpCosPiTest_1_q;
WHEN "1" => vStagei_uid162_lzcZ_uid56_fpCosPiTest_q <= reg_vStage_uid160_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid162_lzcZ_uid56_fpCosPiTest_3_q;
WHEN OTHERS => vStagei_uid162_lzcZ_uid56_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid164_lzcZ_uid56_fpCosPiTest(BITSELECT,163)@6
rVStage_uid164_lzcZ_uid56_fpCosPiTest_in <= vStagei_uid162_lzcZ_uid56_fpCosPiTest_q;
rVStage_uid164_lzcZ_uid56_fpCosPiTest_b <= rVStage_uid164_lzcZ_uid56_fpCosPiTest_in(3 downto 2);
--vCount_uid165_lzcZ_uid56_fpCosPiTest(LOGICAL,164)@6
vCount_uid165_lzcZ_uid56_fpCosPiTest_a <= rVStage_uid164_lzcZ_uid56_fpCosPiTest_b;
vCount_uid165_lzcZ_uid56_fpCosPiTest_b <= leftShiftStage2Idx2Pad2_uid128_fxpX_uid41_fpCosPiTest_q;
vCount_uid165_lzcZ_uid56_fpCosPiTest_q <= "1" when vCount_uid165_lzcZ_uid56_fpCosPiTest_a = vCount_uid165_lzcZ_uid56_fpCosPiTest_b else "0";
--vStage_uid166_lzcZ_uid56_fpCosPiTest(BITSELECT,165)@6
vStage_uid166_lzcZ_uid56_fpCosPiTest_in <= vStagei_uid162_lzcZ_uid56_fpCosPiTest_q(1 downto 0);
vStage_uid166_lzcZ_uid56_fpCosPiTest_b <= vStage_uid166_lzcZ_uid56_fpCosPiTest_in(1 downto 0);
--vStagei_uid168_lzcZ_uid56_fpCosPiTest(MUX,167)@6
vStagei_uid168_lzcZ_uid56_fpCosPiTest_s <= vCount_uid165_lzcZ_uid56_fpCosPiTest_q;
vStagei_uid168_lzcZ_uid56_fpCosPiTest: PROCESS (vStagei_uid168_lzcZ_uid56_fpCosPiTest_s, en, rVStage_uid164_lzcZ_uid56_fpCosPiTest_b, vStage_uid166_lzcZ_uid56_fpCosPiTest_b)
BEGIN
CASE vStagei_uid168_lzcZ_uid56_fpCosPiTest_s IS
WHEN "0" => vStagei_uid168_lzcZ_uid56_fpCosPiTest_q <= rVStage_uid164_lzcZ_uid56_fpCosPiTest_b;
WHEN "1" => vStagei_uid168_lzcZ_uid56_fpCosPiTest_q <= vStage_uid166_lzcZ_uid56_fpCosPiTest_b;
WHEN OTHERS => vStagei_uid168_lzcZ_uid56_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid170_lzcZ_uid56_fpCosPiTest(BITSELECT,169)@6
rVStage_uid170_lzcZ_uid56_fpCosPiTest_in <= vStagei_uid168_lzcZ_uid56_fpCosPiTest_q;
rVStage_uid170_lzcZ_uid56_fpCosPiTest_b <= rVStage_uid170_lzcZ_uid56_fpCosPiTest_in(1 downto 1);
--vCount_uid171_lzcZ_uid56_fpCosPiTest(LOGICAL,170)@6
vCount_uid171_lzcZ_uid56_fpCosPiTest_a <= rVStage_uid170_lzcZ_uid56_fpCosPiTest_b;
vCount_uid171_lzcZ_uid56_fpCosPiTest_b <= GND_q;
vCount_uid171_lzcZ_uid56_fpCosPiTest_q <= "1" when vCount_uid171_lzcZ_uid56_fpCosPiTest_a = vCount_uid171_lzcZ_uid56_fpCosPiTest_b else "0";
--r_uid172_lzcZ_uid56_fpCosPiTest(BITJOIN,171)@6
r_uid172_lzcZ_uid56_fpCosPiTest_q <= ld_vCount_uid139_lzcZ_uid56_fpCosPiTest_q_to_r_uid172_lzcZ_uid56_fpCosPiTest_f_q & ld_vCount_uid147_lzcZ_uid56_fpCosPiTest_q_to_r_uid172_lzcZ_uid56_fpCosPiTest_e_q & reg_vCount_uid153_lzcZ_uid56_fpCosPiTest_0_to_r_uid172_lzcZ_uid56_fpCosPiTest_3_q & vCount_uid159_lzcZ_uid56_fpCosPiTest_q & vCount_uid165_lzcZ_uid56_fpCosPiTest_q & vCount_uid171_lzcZ_uid56_fpCosPiTest_q;
--leftShiftStageSel5Dto4_uid182_alignedZ_uid57_fpCosPiTest(BITSELECT,181)@6
leftShiftStageSel5Dto4_uid182_alignedZ_uid57_fpCosPiTest_in <= r_uid172_lzcZ_uid56_fpCosPiTest_q;
leftShiftStageSel5Dto4_uid182_alignedZ_uid57_fpCosPiTest_b <= leftShiftStageSel5Dto4_uid182_alignedZ_uid57_fpCosPiTest_in(5 downto 4);
--leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest(MUX,182)@6
leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_s <= leftShiftStageSel5Dto4_uid182_alignedZ_uid57_fpCosPiTest_b;
leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest: PROCESS (leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_s, en, ld_z_uid54_fpCosPiTest_b_to_leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_c_q, leftShiftStage0Idx1_uid177_alignedZ_uid57_fpCosPiTest_q, leftShiftStage0Idx2_uid180_alignedZ_uid57_fpCosPiTest_q, cstZwSwF_uid15_fpCosPiTest_q)
BEGIN
CASE leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_s IS
WHEN "00" => leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_q <= ld_z_uid54_fpCosPiTest_b_to_leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_c_q;
WHEN "01" => leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_q <= leftShiftStage0Idx1_uid177_alignedZ_uid57_fpCosPiTest_q;
WHEN "10" => leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_q <= leftShiftStage0Idx2_uid180_alignedZ_uid57_fpCosPiTest_q;
WHEN "11" => leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_q <= cstZwSwF_uid15_fpCosPiTest_q;
WHEN OTHERS => leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage022dto0_uid191_alignedZ_uid57_fpCosPiTest(BITSELECT,190)@6
LeftShiftStage022dto0_uid191_alignedZ_uid57_fpCosPiTest_in <= leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_q(22 downto 0);
LeftShiftStage022dto0_uid191_alignedZ_uid57_fpCosPiTest_b <= LeftShiftStage022dto0_uid191_alignedZ_uid57_fpCosPiTest_in(22 downto 0);
--leftShiftStage1Idx3_uid192_alignedZ_uid57_fpCosPiTest(BITJOIN,191)@6
leftShiftStage1Idx3_uid192_alignedZ_uid57_fpCosPiTest_q <= LeftShiftStage022dto0_uid191_alignedZ_uid57_fpCosPiTest_b & leftShiftStage1Idx3Pad12_uid120_fxpX_uid41_fpCosPiTest_q;
--reg_leftShiftStage1Idx3_uid192_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_5(REG,261)@6
reg_leftShiftStage1Idx3_uid192_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx3_uid192_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_5_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx3_uid192_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_5_q <= leftShiftStage1Idx3_uid192_alignedZ_uid57_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage026dto0_uid188_alignedZ_uid57_fpCosPiTest(BITSELECT,187)@6
LeftShiftStage026dto0_uid188_alignedZ_uid57_fpCosPiTest_in <= leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_q(26 downto 0);
LeftShiftStage026dto0_uid188_alignedZ_uid57_fpCosPiTest_b <= LeftShiftStage026dto0_uid188_alignedZ_uid57_fpCosPiTest_in(26 downto 0);
--leftShiftStage1Idx2_uid189_alignedZ_uid57_fpCosPiTest(BITJOIN,188)@6
leftShiftStage1Idx2_uid189_alignedZ_uid57_fpCosPiTest_q <= LeftShiftStage026dto0_uid188_alignedZ_uid57_fpCosPiTest_b & cstAllZWE_uid21_fpCosPiTest_q;
--reg_leftShiftStage1Idx2_uid189_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_4(REG,260)@6
reg_leftShiftStage1Idx2_uid189_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx2_uid189_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_4_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx2_uid189_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_4_q <= leftShiftStage1Idx2_uid189_alignedZ_uid57_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage030dto0_uid185_alignedZ_uid57_fpCosPiTest(BITSELECT,184)@6
LeftShiftStage030dto0_uid185_alignedZ_uid57_fpCosPiTest_in <= leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_q(30 downto 0);
LeftShiftStage030dto0_uid185_alignedZ_uid57_fpCosPiTest_b <= LeftShiftStage030dto0_uid185_alignedZ_uid57_fpCosPiTest_in(30 downto 0);
--leftShiftStage1Idx1_uid186_alignedZ_uid57_fpCosPiTest(BITJOIN,185)@6
leftShiftStage1Idx1_uid186_alignedZ_uid57_fpCosPiTest_q <= LeftShiftStage030dto0_uid185_alignedZ_uid57_fpCosPiTest_b & leftShiftStage1Idx1Pad4_uid114_fxpX_uid41_fpCosPiTest_q;
--reg_leftShiftStage1Idx1_uid186_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_3(REG,259)@6
reg_leftShiftStage1Idx1_uid186_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx1_uid186_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_3_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx1_uid186_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_3_q <= leftShiftStage1Idx1_uid186_alignedZ_uid57_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--reg_leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_2(REG,258)@6
reg_leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_2_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_2_q <= leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel3Dto2_uid193_alignedZ_uid57_fpCosPiTest(BITSELECT,192)@6
leftShiftStageSel3Dto2_uid193_alignedZ_uid57_fpCosPiTest_in <= r_uid172_lzcZ_uid56_fpCosPiTest_q(3 downto 0);
leftShiftStageSel3Dto2_uid193_alignedZ_uid57_fpCosPiTest_b <= leftShiftStageSel3Dto2_uid193_alignedZ_uid57_fpCosPiTest_in(3 downto 2);
--reg_leftShiftStageSel3Dto2_uid193_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_1(REG,257)@6
reg_leftShiftStageSel3Dto2_uid193_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel3Dto2_uid193_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel3Dto2_uid193_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_1_q <= leftShiftStageSel3Dto2_uid193_alignedZ_uid57_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest(MUX,193)@7
leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_s <= reg_leftShiftStageSel3Dto2_uid193_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_1_q;
leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest: PROCESS (leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_s, en, reg_leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_2_q, reg_leftShiftStage1Idx1_uid186_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_3_q, reg_leftShiftStage1Idx2_uid189_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_4_q, reg_leftShiftStage1Idx3_uid192_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_5_q)
BEGIN
CASE leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_s IS
WHEN "00" => leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_q <= reg_leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_2_q;
WHEN "01" => leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_q <= reg_leftShiftStage1Idx1_uid186_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_3_q;
WHEN "10" => leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_q <= reg_leftShiftStage1Idx2_uid189_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_4_q;
WHEN "11" => leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_q <= reg_leftShiftStage1Idx3_uid192_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_5_q;
WHEN OTHERS => leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--leftShiftStageSel1Dto0_uid204_alignedZ_uid57_fpCosPiTest(BITSELECT,203)@6
leftShiftStageSel1Dto0_uid204_alignedZ_uid57_fpCosPiTest_in <= r_uid172_lzcZ_uid56_fpCosPiTest_q(1 downto 0);
leftShiftStageSel1Dto0_uid204_alignedZ_uid57_fpCosPiTest_b <= leftShiftStageSel1Dto0_uid204_alignedZ_uid57_fpCosPiTest_in(1 downto 0);
--reg_leftShiftStageSel1Dto0_uid204_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest_1(REG,262)@6
reg_leftShiftStageSel1Dto0_uid204_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel1Dto0_uid204_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel1Dto0_uid204_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest_1_q <= leftShiftStageSel1Dto0_uid204_alignedZ_uid57_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest(MUX,204)@7
leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest_s <= reg_leftShiftStageSel1Dto0_uid204_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest_1_q;
leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest: PROCESS (leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest_s, en, leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_q, leftShiftStage2Idx1_uid197_alignedZ_uid57_fpCosPiTest_q, leftShiftStage2Idx2_uid200_alignedZ_uid57_fpCosPiTest_q, leftShiftStage2Idx3_uid203_alignedZ_uid57_fpCosPiTest_q)
BEGIN
CASE leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest_s IS
WHEN "00" => leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest_q <= leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_q;
WHEN "01" => leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest_q <= leftShiftStage2Idx1_uid197_alignedZ_uid57_fpCosPiTest_q;
WHEN "10" => leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest_q <= leftShiftStage2Idx2_uid200_alignedZ_uid57_fpCosPiTest_q;
WHEN "11" => leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest_q <= leftShiftStage2Idx3_uid203_alignedZ_uid57_fpCosPiTest_q;
WHEN OTHERS => leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--alignedZLow_uid58_fpCosPiTest(BITSELECT,57)@7
alignedZLow_uid58_fpCosPiTest_in <= leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest_q;
alignedZLow_uid58_fpCosPiTest_b <= alignedZLow_uid58_fpCosPiTest_in(34 downto 11);
--ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_inputreg(DELAY,612)
ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 24, depth => 1 )
PORT MAP ( xin => alignedZLow_uid58_fpCosPiTest_b, xout => ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem(DUALMEM,613)
ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_reset0 <= areset;
ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_ia <= ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_inputreg_q;
ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_aa <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdreg_q;
ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_ab <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdmux_q;
ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 24,
widthad_a => 2,
numwords_a => 3,
width_b => 24,
widthad_b => 2,
numwords_b => 3,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_iq,
address_a => ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_aa,
data_a => ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_ia
);
ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_q <= ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_iq(23 downto 0);
--reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0(REG,269)@12
reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_q <= ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest(MULT,222)@13
prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_pr <= UNSIGNED(prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_a) * UNSIGNED(prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_b);
prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_a <= (others => '0');
prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_b <= (others => '0');
prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_a <= reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_q;
prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_b <= reg_fxpSinRes_uid65_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_1_q;
prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_s1 <= STD_LOGIC_VECTOR(prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_pr);
END IF;
END IF;
END PROCESS;
prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_q <= prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid224_mul2xSinRes_uid66_fpCosPiTest(BITSELECT,223)@16
prodXYTruncFR_uid224_mul2xSinRes_uid66_fpCosPiTest_in <= prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_q;
prodXYTruncFR_uid224_mul2xSinRes_uid66_fpCosPiTest_b <= prodXYTruncFR_uid224_mul2xSinRes_uid66_fpCosPiTest_in(48 downto 23);
--normBit_uid67_fpCosPiTest(BITSELECT,66)@16
normBit_uid67_fpCosPiTest_in <= prodXYTruncFR_uid224_mul2xSinRes_uid66_fpCosPiTest_b;
normBit_uid67_fpCosPiTest_b <= normBit_uid67_fpCosPiTest_in(25 downto 25);
--cstAllZWF_uid9_fpCosPiTest(CONSTANT,8)
cstAllZWF_uid9_fpCosPiTest_q <= "00000000000000000000000";
--rndExpUpdate_uid72_uid73_fpCosPiTest(BITJOIN,72)@16
rndExpUpdate_uid72_uid73_fpCosPiTest_q <= normBit_uid67_fpCosPiTest_b & cstAllZWF_uid9_fpCosPiTest_q & VCC_q;
--ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_nor(LOGICAL,558)
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_nor_a <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_notEnable_q;
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_nor_b <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_sticky_ena_q;
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_nor_q <= not (ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_nor_a or ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_nor_b);
--ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_sticky_ena(REG,559)
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_nor_q = "1") THEN
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_sticky_ena_q <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_enaAnd(LOGICAL,560)
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_enaAnd_a <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_sticky_ena_q;
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_enaAnd_b <= en;
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_enaAnd_q <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_enaAnd_a and ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_enaAnd_b;
--reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1(REG,271)@6
reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q <= r_uid172_lzcZ_uid56_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem(DUALMEM,549)
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_reset0 <= areset;
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_ia <= reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q;
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_aa <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdreg_q;
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_ab <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdmux_q;
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 6,
widthad_a => 3,
numwords_a => 7,
width_b => 6,
widthad_b => 3,
numwords_b => 7,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_iq,
address_a => ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_aa,
data_a => ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_ia
);
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_q <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_iq(5 downto 0);
--cstBiasM1_uid11_fpCosPiTest(CONSTANT,10)
cstBiasM1_uid11_fpCosPiTest_q <= "01111110";
--expHardCase_uid59_fpCosPiTest(SUB,58)@15
expHardCase_uid59_fpCosPiTest_a <= STD_LOGIC_VECTOR("0" & cstBiasM1_uid11_fpCosPiTest_q);
expHardCase_uid59_fpCosPiTest_b <= STD_LOGIC_VECTOR("000" & ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_q);
expHardCase_uid59_fpCosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expHardCase_uid59_fpCosPiTest_a) - UNSIGNED(expHardCase_uid59_fpCosPiTest_b));
expHardCase_uid59_fpCosPiTest_q <= expHardCase_uid59_fpCosPiTest_o(8 downto 0);
--expP_uid60_fpCosPiTest(BITSELECT,59)@15
expP_uid60_fpCosPiTest_in <= expHardCase_uid59_fpCosPiTest_q(7 downto 0);
expP_uid60_fpCosPiTest_b <= expP_uid60_fpCosPiTest_in(7 downto 0);
--reg_expP_uid60_fpCosPiTest_0_to_expFracPreRnd_uid71_uid71_fpCosPiTest_1(REG,272)@15
reg_expP_uid60_fpCosPiTest_0_to_expFracPreRnd_uid71_uid71_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expP_uid60_fpCosPiTest_0_to_expFracPreRnd_uid71_uid71_fpCosPiTest_1_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expP_uid60_fpCosPiTest_0_to_expFracPreRnd_uid71_uid71_fpCosPiTest_1_q <= expP_uid60_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--highRes_uid68_fpCosPiTest(BITSELECT,67)@16
highRes_uid68_fpCosPiTest_in <= prodXYTruncFR_uid224_mul2xSinRes_uid66_fpCosPiTest_b(24 downto 0);
highRes_uid68_fpCosPiTest_b <= highRes_uid68_fpCosPiTest_in(24 downto 1);
--lowRes_uid69_fpCosPiTest(BITSELECT,68)@16
lowRes_uid69_fpCosPiTest_in <= prodXYTruncFR_uid224_mul2xSinRes_uid66_fpCosPiTest_b(23 downto 0);
lowRes_uid69_fpCosPiTest_b <= lowRes_uid69_fpCosPiTest_in(23 downto 0);
--fracRCompPreRnd_uid70_fpCosPiTest(MUX,69)@16
fracRCompPreRnd_uid70_fpCosPiTest_s <= normBit_uid67_fpCosPiTest_b;
fracRCompPreRnd_uid70_fpCosPiTest: PROCESS (fracRCompPreRnd_uid70_fpCosPiTest_s, en, lowRes_uid69_fpCosPiTest_b, highRes_uid68_fpCosPiTest_b)
BEGIN
CASE fracRCompPreRnd_uid70_fpCosPiTest_s IS
WHEN "0" => fracRCompPreRnd_uid70_fpCosPiTest_q <= lowRes_uid69_fpCosPiTest_b;
WHEN "1" => fracRCompPreRnd_uid70_fpCosPiTest_q <= highRes_uid68_fpCosPiTest_b;
WHEN OTHERS => fracRCompPreRnd_uid70_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--expFracPreRnd_uid71_uid71_fpCosPiTest(BITJOIN,70)@16
expFracPreRnd_uid71_uid71_fpCosPiTest_q <= reg_expP_uid60_fpCosPiTest_0_to_expFracPreRnd_uid71_uid71_fpCosPiTest_1_q & fracRCompPreRnd_uid70_fpCosPiTest_q;
--expFracComp_uid74_fpCosPiTest(ADD,73)@16
expFracComp_uid74_fpCosPiTest_a <= STD_LOGIC_VECTOR("0" & expFracPreRnd_uid71_uid71_fpCosPiTest_q);
expFracComp_uid74_fpCosPiTest_b <= STD_LOGIC_VECTOR("00000000" & rndExpUpdate_uid72_uid73_fpCosPiTest_q);
expFracComp_uid74_fpCosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expFracComp_uid74_fpCosPiTest_a) + UNSIGNED(expFracComp_uid74_fpCosPiTest_b));
expFracComp_uid74_fpCosPiTest_q <= expFracComp_uid74_fpCosPiTest_o(32 downto 0);
--expRComp_uid76_fpCosPiTest(BITSELECT,75)@16
expRComp_uid76_fpCosPiTest_in <= expFracComp_uid74_fpCosPiTest_q(31 downto 0);
expRComp_uid76_fpCosPiTest_b <= expRComp_uid76_fpCosPiTest_in(31 downto 24);
--fracXIsZero_uid27_fpCosPiTest(LOGICAL,26)@0
fracXIsZero_uid27_fpCosPiTest_a <= fracX_uid7_fpCosPiTest_b;
fracXIsZero_uid27_fpCosPiTest_b <= cstAllZWF_uid9_fpCosPiTest_q;
fracXIsZero_uid27_fpCosPiTest_q <= "1" when fracXIsZero_uid27_fpCosPiTest_a = fracXIsZero_uid27_fpCosPiTest_b else "0";
--InvFracXIsZero_uid29_fpCosPiTest(LOGICAL,28)@0
InvFracXIsZero_uid29_fpCosPiTest_a <= fracXIsZero_uid27_fpCosPiTest_q;
InvFracXIsZero_uid29_fpCosPiTest_q <= not InvFracXIsZero_uid29_fpCosPiTest_a;
--expXIsMax_uid25_fpCosPiTest(LOGICAL,24)@0
expXIsMax_uid25_fpCosPiTest_a <= expX_uid6_fpCosPiTest_b;
expXIsMax_uid25_fpCosPiTest_b <= cstAllOWE_uid8_fpCosPiTest_q;
expXIsMax_uid25_fpCosPiTest_q <= "1" when expXIsMax_uid25_fpCosPiTest_a = expXIsMax_uid25_fpCosPiTest_b else "0";
--exc_N_uid30_fpCosPiTest(LOGICAL,29)@0
exc_N_uid30_fpCosPiTest_a <= expXIsMax_uid25_fpCosPiTest_q;
exc_N_uid30_fpCosPiTest_b <= InvFracXIsZero_uid29_fpCosPiTest_q;
exc_N_uid30_fpCosPiTest_q <= exc_N_uid30_fpCosPiTest_a and exc_N_uid30_fpCosPiTest_b;
--InvExc_N_uid31_fpCosPiTest(LOGICAL,30)@0
InvExc_N_uid31_fpCosPiTest_a <= exc_N_uid30_fpCosPiTest_q;
InvExc_N_uid31_fpCosPiTest_q <= not InvExc_N_uid31_fpCosPiTest_a;
--exc_I_uid28_fpCosPiTest(LOGICAL,27)@0
exc_I_uid28_fpCosPiTest_a <= expXIsMax_uid25_fpCosPiTest_q;
exc_I_uid28_fpCosPiTest_b <= fracXIsZero_uid27_fpCosPiTest_q;
exc_I_uid28_fpCosPiTest_q <= exc_I_uid28_fpCosPiTest_a and exc_I_uid28_fpCosPiTest_b;
--InvExc_I_uid32_fpCosPiTest(LOGICAL,31)@0
InvExc_I_uid32_fpCosPiTest_a <= exc_I_uid28_fpCosPiTest_q;
InvExc_I_uid32_fpCosPiTest_q <= not InvExc_I_uid32_fpCosPiTest_a;
--expXIsZero_uid23_fpCosPiTest(LOGICAL,22)@0
expXIsZero_uid23_fpCosPiTest_a <= expX_uid6_fpCosPiTest_b;
expXIsZero_uid23_fpCosPiTest_b <= cstAllZWE_uid21_fpCosPiTest_q;
expXIsZero_uid23_fpCosPiTest_q <= "1" when expXIsZero_uid23_fpCosPiTest_a = expXIsZero_uid23_fpCosPiTest_b else "0";
--InvExpXIsZero_uid33_fpCosPiTest(LOGICAL,32)@0
InvExpXIsZero_uid33_fpCosPiTest_a <= expXIsZero_uid23_fpCosPiTest_q;
InvExpXIsZero_uid33_fpCosPiTest_q <= not InvExpXIsZero_uid33_fpCosPiTest_a;
--exc_R_uid34_fpCosPiTest(LOGICAL,33)@0
exc_R_uid34_fpCosPiTest_a <= InvExpXIsZero_uid33_fpCosPiTest_q;
exc_R_uid34_fpCosPiTest_b <= InvExc_I_uid32_fpCosPiTest_q;
exc_R_uid34_fpCosPiTest_c <= InvExc_N_uid31_fpCosPiTest_q;
exc_R_uid34_fpCosPiTest_q <= exc_R_uid34_fpCosPiTest_a and exc_R_uid34_fpCosPiTest_b and exc_R_uid34_fpCosPiTest_c;
--ld_exc_R_uid34_fpCosPiTest_q_to_xIsInt_uid80_fpCosPiTest_a(DELAY,337)@0
ld_exc_R_uid34_fpCosPiTest_q_to_xIsInt_uid80_fpCosPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => exc_R_uid34_fpCosPiTest_q, xout => ld_exc_R_uid34_fpCosPiTest_q_to_xIsInt_uid80_fpCosPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--xIsHalf_uid83_fpCosPiTest(LOGICAL,82)@2
xIsHalf_uid83_fpCosPiTest_a <= ld_exc_R_uid34_fpCosPiTest_q_to_xIsInt_uid80_fpCosPiTest_a_q;
xIsHalf_uid83_fpCosPiTest_b <= fxpXFracHalf_uid46_fpCosPiTest_q;
xIsHalf_uid83_fpCosPiTest_c <= InvCosXIsOne_uid77_fpCosPiTest_q;
xIsHalf_uid83_fpCosPiTest_d <= InvXEvenInt_uid81_fpCosPiTest_q;
xIsHalf_uid83_fpCosPiTest_q <= xIsHalf_uid83_fpCosPiTest_a and xIsHalf_uid83_fpCosPiTest_b and xIsHalf_uid83_fpCosPiTest_c and xIsHalf_uid83_fpCosPiTest_d;
--ld_xIsHalf_uid83_fpCosPiTest_q_to_expRPostExc1_uid91_fpCosPiTest_b(DELAY,355)@2
ld_xIsHalf_uid83_fpCosPiTest_q_to_expRPostExc1_uid91_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 14 )
PORT MAP ( xin => xIsHalf_uid83_fpCosPiTest_q, xout => ld_xIsHalf_uid83_fpCosPiTest_q_to_expRPostExc1_uid91_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--expRPostExc1_uid91_fpCosPiTest(MUX,90)@16
expRPostExc1_uid91_fpCosPiTest_s <= ld_xIsHalf_uid83_fpCosPiTest_q_to_expRPostExc1_uid91_fpCosPiTest_b_q;
expRPostExc1_uid91_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expRPostExc1_uid91_fpCosPiTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE expRPostExc1_uid91_fpCosPiTest_s IS
WHEN "0" => expRPostExc1_uid91_fpCosPiTest_q <= expRComp_uid76_fpCosPiTest_b;
WHEN "1" => expRPostExc1_uid91_fpCosPiTest_q <= cstAllZWE_uid21_fpCosPiTest_q;
WHEN OTHERS => expRPostExc1_uid91_fpCosPiTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_nor(LOGICAL,570)
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_nor_a <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_notEnable_q;
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_nor_b <= ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_sticky_ena_q;
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_nor_q <= not (ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_nor_a or ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_nor_b);
--ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_mem_top(CONSTANT,566)
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_mem_top_q <= "01100";
--ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_cmp(LOGICAL,567)
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_cmp_a <= ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_mem_top_q;
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdmux_q);
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_cmp_q <= "1" when ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_cmp_a = ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_cmp_b else "0";
--ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_cmpReg(REG,568)
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_cmpReg_q <= ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_sticky_ena(REG,571)
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_nor_q = "1") THEN
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_sticky_ena_q <= ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_enaAnd(LOGICAL,572)
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_enaAnd_a <= ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_sticky_ena_q;
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_enaAnd_b <= en;
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_enaAnd_q <= ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_enaAnd_a and ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_enaAnd_b;
--ld_expXIsZero_uid23_fpCosPiTest_q_to_xIntOrXZOrCosOne_uid93_fpCosPiTest_b(DELAY,359)@0
ld_expXIsZero_uid23_fpCosPiTest_q_to_xIntOrXZOrCosOne_uid93_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => expXIsZero_uid23_fpCosPiTest_q, xout => ld_expXIsZero_uid23_fpCosPiTest_q_to_xIntOrXZOrCosOne_uid93_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--fxpXFracZero_uid45_fpCosPiTest(LOGICAL,44)@2
fxpXFracZero_uid45_fpCosPiTest_a <= reg_fxpXFrac_uid43_fpCosPiTest_0_to_fxpXFracZero_uid45_fpCosPiTest_1_q;
fxpXFracZero_uid45_fpCosPiTest_b <= STD_LOGIC_VECTOR("0" & cstZwSwF_uid15_fpCosPiTest_q);
fxpXFracZero_uid45_fpCosPiTest_q <= "1" when fxpXFracZero_uid45_fpCosPiTest_a = fxpXFracZero_uid45_fpCosPiTest_b else "0";
--fracZCosNotOne_uid78_fpCosPiTest(LOGICAL,77)@2
fracZCosNotOne_uid78_fpCosPiTest_a <= fxpXFracZero_uid45_fpCosPiTest_q;
fracZCosNotOne_uid78_fpCosPiTest_b <= InvCosXIsOne_uid77_fpCosPiTest_q;
fracZCosNotOne_uid78_fpCosPiTest_q <= fracZCosNotOne_uid78_fpCosPiTest_a and fracZCosNotOne_uid78_fpCosPiTest_b;
--evenIntCosNotOneFZ_uid79_fpCosPiTest(LOGICAL,78)@2
evenIntCosNotOneFZ_uid79_fpCosPiTest_a <= ld_xEvenInt_uid35_fpCosPiTest_c_to_evenIntCosNotOneFZ_uid79_fpCosPiTest_a_q;
evenIntCosNotOneFZ_uid79_fpCosPiTest_b <= fracZCosNotOne_uid78_fpCosPiTest_q;
evenIntCosNotOneFZ_uid79_fpCosPiTest_q <= evenIntCosNotOneFZ_uid79_fpCosPiTest_a or evenIntCosNotOneFZ_uid79_fpCosPiTest_b;
--xIsInt_uid80_fpCosPiTest(LOGICAL,79)@2
xIsInt_uid80_fpCosPiTest_a <= ld_exc_R_uid34_fpCosPiTest_q_to_xIsInt_uid80_fpCosPiTest_a_q;
xIsInt_uid80_fpCosPiTest_b <= evenIntCosNotOneFZ_uid79_fpCosPiTest_q;
xIsInt_uid80_fpCosPiTest_q <= xIsInt_uid80_fpCosPiTest_a and xIsInt_uid80_fpCosPiTest_b;
--xIntOrXZOrCosOne_uid93_fpCosPiTest(LOGICAL,92)@2
xIntOrXZOrCosOne_uid93_fpCosPiTest_a <= xIsInt_uid80_fpCosPiTest_q;
xIntOrXZOrCosOne_uid93_fpCosPiTest_b <= ld_expXIsZero_uid23_fpCosPiTest_q_to_xIntOrXZOrCosOne_uid93_fpCosPiTest_b_q;
xIntOrXZOrCosOne_uid93_fpCosPiTest_c <= ld_cosXIsOne_uid36_fpCosPiTest_c_to_InvCosXIsOne_uid77_fpCosPiTest_a_q;
xIntOrXZOrCosOne_uid93_fpCosPiTest_q <= xIntOrXZOrCosOne_uid93_fpCosPiTest_a or xIntOrXZOrCosOne_uid93_fpCosPiTest_b or xIntOrXZOrCosOne_uid93_fpCosPiTest_c;
--excRNaN_uid84_fpCosPiTest(LOGICAL,83)@0
excRNaN_uid84_fpCosPiTest_a <= exc_N_uid30_fpCosPiTest_q;
excRNaN_uid84_fpCosPiTest_b <= exc_I_uid28_fpCosPiTest_q;
excRNaN_uid84_fpCosPiTest_q <= excRNaN_uid84_fpCosPiTest_a or excRNaN_uid84_fpCosPiTest_b;
--rInfOrNaN_uid92_fpCosPiTest(LOGICAL,91)@0
rInfOrNaN_uid92_fpCosPiTest_a <= GND_q;
rInfOrNaN_uid92_fpCosPiTest_b <= excRNaN_uid84_fpCosPiTest_q;
rInfOrNaN_uid92_fpCosPiTest_q <= rInfOrNaN_uid92_fpCosPiTest_a or rInfOrNaN_uid92_fpCosPiTest_b;
--ld_rInfOrNaN_uid92_fpCosPiTest_q_to_join_uid94_fpCosPiTest_a(DELAY,361)@0
ld_rInfOrNaN_uid92_fpCosPiTest_q_to_join_uid94_fpCosPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => rInfOrNaN_uid92_fpCosPiTest_q, xout => ld_rInfOrNaN_uid92_fpCosPiTest_q_to_join_uid94_fpCosPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--join_uid94_fpCosPiTest(BITJOIN,93)@2
join_uid94_fpCosPiTest_q <= xIntOrXZOrCosOne_uid93_fpCosPiTest_q & ld_rInfOrNaN_uid92_fpCosPiTest_q_to_join_uid94_fpCosPiTest_a_q;
--reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1(REG,274)@2
reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q <= join_uid94_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt(COUNTER,562)
-- every=1, low=0, high=12, step=1, init=1
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt_i = 11 THEN
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt_eq <= '1';
ELSE
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt_eq = '1') THEN
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt_i <= ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt_i - 12;
ELSE
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt_i <= ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt_i,4));
--ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdreg(REG,563)
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdreg_q <= ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdmux(MUX,564)
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdmux_s <= en;
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdmux: PROCESS (ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdmux_s, ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdreg_q, ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt_q)
BEGIN
CASE ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdmux_s IS
WHEN "0" => ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdmux_q <= ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdreg_q;
WHEN "1" => ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdmux_q <= ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem(DUALMEM,561)
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_reset0 <= areset;
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_ia <= reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q;
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_aa <= ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdreg_q;
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_ab <= ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdmux_q;
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 2,
widthad_a => 4,
numwords_a => 13,
width_b => 2,
widthad_b => 4,
numwords_b => 13,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_iq,
address_a => ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_aa,
data_a => ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_ia
);
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_q <= ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_iq(1 downto 0);
--expRPostExc_uid95_fpCosPiTest(MUX,94)@17
expRPostExc_uid95_fpCosPiTest_s <= ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_q;
expRPostExc_uid95_fpCosPiTest: PROCESS (expRPostExc_uid95_fpCosPiTest_s, en, expRPostExc1_uid91_fpCosPiTest_q, cstAllOWE_uid8_fpCosPiTest_q, cstBias_uid10_fpCosPiTest_q, cstBias_uid10_fpCosPiTest_q)
BEGIN
CASE expRPostExc_uid95_fpCosPiTest_s IS
WHEN "00" => expRPostExc_uid95_fpCosPiTest_q <= expRPostExc1_uid91_fpCosPiTest_q;
WHEN "01" => expRPostExc_uid95_fpCosPiTest_q <= cstAllOWE_uid8_fpCosPiTest_q;
WHEN "10" => expRPostExc_uid95_fpCosPiTest_q <= cstBias_uid10_fpCosPiTest_q;
WHEN "11" => expRPostExc_uid95_fpCosPiTest_q <= cstBias_uid10_fpCosPiTest_q;
WHEN OTHERS => expRPostExc_uid95_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--oneFracRPostExc2_uid87_fpCosPiTest(CONSTANT,86)
oneFracRPostExc2_uid87_fpCosPiTest_q <= "00000000000000000000001";
--fracRComp_uid75_fpCosPiTest(BITSELECT,74)@16
fracRComp_uid75_fpCosPiTest_in <= expFracComp_uid74_fpCosPiTest_q(23 downto 0);
fracRComp_uid75_fpCosPiTest_b <= fracRComp_uid75_fpCosPiTest_in(23 downto 1);
--reg_xIsHalf_uid83_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_5(REG,243)@2
reg_xIsHalf_uid83_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xIsHalf_uid83_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_5_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xIsHalf_uid83_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_5_q <= xIsHalf_uid83_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--reg_expXIsZero_uid23_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_4(REG,242)@2
reg_expXIsZero_uid23_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expXIsZero_uid23_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_4_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expXIsZero_uid23_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_4_q <= ld_expXIsZero_uid23_fpCosPiTest_q_to_xIntOrXZOrCosOne_uid93_fpCosPiTest_b_q;
END IF;
END IF;
END PROCESS;
--reg_fxpXFracHalf_uid46_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_3(REG,241)@2
reg_fxpXFracHalf_uid46_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fxpXFracHalf_uid46_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_3_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fxpXFracHalf_uid46_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_3_q <= fxpXFracHalf_uid46_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--reg_xIsInt_uid80_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_2(REG,240)@2
reg_xIsInt_uid80_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xIsInt_uid80_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xIsInt_uid80_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_2_q <= xIsInt_uid80_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--reg_cosXIsOne_uid36_fpCosPiTest_1_to_bigCond_uid85_fpCosPiTest_1(REG,239)@0
reg_cosXIsOne_uid36_fpCosPiTest_1_to_bigCond_uid85_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cosXIsOne_uid36_fpCosPiTest_1_to_bigCond_uid85_fpCosPiTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cosXIsOne_uid36_fpCosPiTest_1_to_bigCond_uid85_fpCosPiTest_1_q <= cosXIsOne_uid36_fpCosPiTest_c;
END IF;
END IF;
END PROCESS;
--ld_reg_cosXIsOne_uid36_fpCosPiTest_1_to_bigCond_uid85_fpCosPiTest_1_q_to_bigCond_uid85_fpCosPiTest_a(DELAY,346)@1
ld_reg_cosXIsOne_uid36_fpCosPiTest_1_to_bigCond_uid85_fpCosPiTest_1_q_to_bigCond_uid85_fpCosPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => reg_cosXIsOne_uid36_fpCosPiTest_1_to_bigCond_uid85_fpCosPiTest_1_q, xout => ld_reg_cosXIsOne_uid36_fpCosPiTest_1_to_bigCond_uid85_fpCosPiTest_1_q_to_bigCond_uid85_fpCosPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--bigCond_uid85_fpCosPiTest(LOGICAL,84)@3
bigCond_uid85_fpCosPiTest_a <= ld_reg_cosXIsOne_uid36_fpCosPiTest_1_to_bigCond_uid85_fpCosPiTest_1_q_to_bigCond_uid85_fpCosPiTest_a_q;
bigCond_uid85_fpCosPiTest_b <= reg_xIsInt_uid80_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_2_q;
bigCond_uid85_fpCosPiTest_c <= reg_fxpXFracHalf_uid46_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_3_q;
bigCond_uid85_fpCosPiTest_d <= reg_expXIsZero_uid23_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_4_q;
bigCond_uid85_fpCosPiTest_f <= reg_xIsHalf_uid83_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_5_q;
bigCond_uid85_fpCosPiTest_g <= GND_q;
bigCond_uid85_fpCosPiTest_q <= bigCond_uid85_fpCosPiTest_a or bigCond_uid85_fpCosPiTest_b or bigCond_uid85_fpCosPiTest_c or bigCond_uid85_fpCosPiTest_d or bigCond_uid85_fpCosPiTest_f or bigCond_uid85_fpCosPiTest_g;
--ld_bigCond_uid85_fpCosPiTest_q_to_fracRPostExc1_uid86_fpCosPiTest_b(DELAY,351)@3
ld_bigCond_uid85_fpCosPiTest_q_to_fracRPostExc1_uid86_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 13 )
PORT MAP ( xin => bigCond_uid85_fpCosPiTest_q, xout => ld_bigCond_uid85_fpCosPiTest_q_to_fracRPostExc1_uid86_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--fracRPostExc1_uid86_fpCosPiTest(MUX,85)@16
fracRPostExc1_uid86_fpCosPiTest_s <= ld_bigCond_uid85_fpCosPiTest_q_to_fracRPostExc1_uid86_fpCosPiTest_b_q;
fracRPostExc1_uid86_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
fracRPostExc1_uid86_fpCosPiTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE fracRPostExc1_uid86_fpCosPiTest_s IS
WHEN "0" => fracRPostExc1_uid86_fpCosPiTest_q <= fracRComp_uid75_fpCosPiTest_b;
WHEN "1" => fracRPostExc1_uid86_fpCosPiTest_q <= cstAllZWF_uid9_fpCosPiTest_q;
WHEN OTHERS => fracRPostExc1_uid86_fpCosPiTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--reg_excRNaN_uid84_fpCosPiTest_0_to_fracRPostExc_uid88_fpCosPiTest_1(REG,273)@0
reg_excRNaN_uid84_fpCosPiTest_0_to_fracRPostExc_uid88_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_excRNaN_uid84_fpCosPiTest_0_to_fracRPostExc_uid88_fpCosPiTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_excRNaN_uid84_fpCosPiTest_0_to_fracRPostExc_uid88_fpCosPiTest_1_q <= excRNaN_uid84_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_excRNaN_uid84_fpCosPiTest_0_to_fracRPostExc_uid88_fpCosPiTest_1_q_to_fracRPostExc_uid88_fpCosPiTest_b(DELAY,353)@1
ld_reg_excRNaN_uid84_fpCosPiTest_0_to_fracRPostExc_uid88_fpCosPiTest_1_q_to_fracRPostExc_uid88_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 16 )
PORT MAP ( xin => reg_excRNaN_uid84_fpCosPiTest_0_to_fracRPostExc_uid88_fpCosPiTest_1_q, xout => ld_reg_excRNaN_uid84_fpCosPiTest_0_to_fracRPostExc_uid88_fpCosPiTest_1_q_to_fracRPostExc_uid88_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--fracRPostExc_uid88_fpCosPiTest(MUX,87)@17
fracRPostExc_uid88_fpCosPiTest_s <= ld_reg_excRNaN_uid84_fpCosPiTest_0_to_fracRPostExc_uid88_fpCosPiTest_1_q_to_fracRPostExc_uid88_fpCosPiTest_b_q;
fracRPostExc_uid88_fpCosPiTest: PROCESS (fracRPostExc_uid88_fpCosPiTest_s, en, fracRPostExc1_uid86_fpCosPiTest_q, oneFracRPostExc2_uid87_fpCosPiTest_q)
BEGIN
CASE fracRPostExc_uid88_fpCosPiTest_s IS
WHEN "0" => fracRPostExc_uid88_fpCosPiTest_q <= fracRPostExc1_uid86_fpCosPiTest_q;
WHEN "1" => fracRPostExc_uid88_fpCosPiTest_q <= oneFracRPostExc2_uid87_fpCosPiTest_q;
WHEN OTHERS => fracRPostExc_uid88_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--R_uid102_fpCosPiTest(BITJOIN,101)@17
R_uid102_fpCosPiTest_q <= ld_signR_uid101_fpCosPiTest_q_to_R_uid102_fpCosPiTest_c_q & expRPostExc_uid95_fpCosPiTest_q & fracRPostExc_uid88_fpCosPiTest_q;
--xOut(GPOUT,4)@17
q <= R_uid102_fpCosPiTest_q;
end normal;
|
-----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Release Version 13.1
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing device programming or simulation files), and
-- any associated documentation or information are expressly subject to the
-- terms and conditions of the Altera Program License Subscription Agreement,
-- Altera MegaCore Function License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for the sole
-- purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
-----------------------------------------------------------------------------
-- VHDL created from fp_cospi_s5
-- VHDL created on Wed Feb 27 15:22:33 2013
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.all;
use std.TextIO.all;
use work.dspba_library_package.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
entity fp_cospi_s5 is
port (
a : in std_logic_vector(31 downto 0);
en : in std_logic_vector(0 downto 0);
q : out std_logic_vector(31 downto 0);
clk : in std_logic;
areset : in std_logic
);
end;
architecture normal of fp_cospi_s5 is
attribute altera_attribute : string;
attribute altera_attribute of normal : architecture is "-name NOT_GATE_PUSH_BACK OFF; -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON; -name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410";
signal GND_q : std_logic_vector (0 downto 0);
signal VCC_q : std_logic_vector (0 downto 0);
signal cstAllOWE_uid8_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal cstAllZWF_uid9_fpCosPiTest_q : std_logic_vector (22 downto 0);
signal cstBias_uid10_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal cstBiasM1_uid11_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal cstBiasPwF_uid12_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal biasMwShiftMO_uid13_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal cst01pWShift_uid14_fpCosPiTest_q : std_logic_vector (12 downto 0);
signal cstZwSwF_uid15_fpCosPiTest_q : std_logic_vector (34 downto 0);
signal cstAllZWE_uid21_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal rangeReducedFxPX_uid51_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal rangeReducedFxPX_uid51_fpCosPiTest_q : std_logic_vector (35 downto 0);
signal fracRPostExc1_uid86_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal fracRPostExc1_uid86_fpCosPiTest_q : std_logic_vector (22 downto 0);
signal oneFracRPostExc2_uid87_fpCosPiTest_q : std_logic_vector (22 downto 0);
signal expRPostExc1_uid91_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal expRPostExc1_uid91_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal signRComp_uid99_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal signRComp_uid99_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal signRComp_uid99_fpCosPiTest_c : std_logic_vector(0 downto 0);
signal signRComp_uid99_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal signR_uid101_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal signR_uid101_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal signR_uid101_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal leftShiftStage0Idx1Pad16_uid105_fxpX_uid41_fpCosPiTest_q : std_logic_vector (15 downto 0);
signal leftShiftStage0Idx2Pad32_uid108_fxpX_uid41_fpCosPiTest_q : std_logic_vector (31 downto 0);
signal leftShiftStage0Idx3_uid111_fxpX_uid41_fpCosPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage1Idx1Pad4_uid114_fxpX_uid41_fpCosPiTest_q : std_logic_vector (3 downto 0);
signal leftShiftStage1Idx3Pad12_uid120_fxpX_uid41_fpCosPiTest_q : std_logic_vector (11 downto 0);
signal leftShiftStage2Idx2Pad2_uid128_fxpX_uid41_fpCosPiTest_q : std_logic_vector (1 downto 0);
signal leftShiftStage2Idx3Pad3_uid131_fxpX_uid41_fpCosPiTest_q : std_logic_vector (2 downto 0);
signal mO_uid140_lzcZ_uid56_fpCosPiTest_q : std_logic_vector (28 downto 0);
signal memoryC2_uid209_sinPiZTableGenerator_q : std_logic_vector(13 downto 0);
signal prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_a : std_logic_vector (23 downto 0);
signal prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_b : std_logic_vector (24 downto 0);
signal prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_s1 : std_logic_vector (48 downto 0);
signal prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_pr : UNSIGNED (48 downto 0);
signal prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_q : std_logic_vector (48 downto 0);
signal prodXY_uid226_pT1_uid211_sinPiZPolyEval_a : std_logic_vector (13 downto 0);
signal prodXY_uid226_pT1_uid211_sinPiZPolyEval_b : std_logic_vector (13 downto 0);
signal prodXY_uid226_pT1_uid211_sinPiZPolyEval_s1 : std_logic_vector (27 downto 0);
signal prodXY_uid226_pT1_uid211_sinPiZPolyEval_pr : SIGNED (28 downto 0);
signal prodXY_uid226_pT1_uid211_sinPiZPolyEval_q : std_logic_vector (27 downto 0);
signal prodXY_uid229_pT2_uid217_sinPiZPolyEval_a : std_logic_vector (15 downto 0);
signal prodXY_uid229_pT2_uid217_sinPiZPolyEval_b : std_logic_vector (22 downto 0);
signal prodXY_uid229_pT2_uid217_sinPiZPolyEval_s1 : std_logic_vector (38 downto 0);
signal prodXY_uid229_pT2_uid217_sinPiZPolyEval_pr : SIGNED (39 downto 0);
signal prodXY_uid229_pT2_uid217_sinPiZPolyEval_q : std_logic_vector (38 downto 0);
signal reg_leftShiftStageSel3Dto2_uid123_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_2_q : std_logic_vector (36 downto 0);
signal reg_leftShiftStage1Idx1_uid116_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_3_q : std_logic_vector (36 downto 0);
signal reg_leftShiftStage1Idx2_uid119_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_4_q : std_logic_vector (36 downto 0);
signal reg_leftShiftStage1Idx3_uid122_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_5_q : std_logic_vector (36 downto 0);
signal reg_leftShiftStageSel1Dto0_uid134_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_fxpXFrac_uid43_fpCosPiTest_0_to_fxpXFracZero_uid45_fpCosPiTest_1_q : std_logic_vector (35 downto 0);
signal reg_cosXIsOne_uid36_fpCosPiTest_1_to_bigCond_uid85_fpCosPiTest_1_q : std_logic_vector (0 downto 0);
signal reg_xIsInt_uid80_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_2_q : std_logic_vector (0 downto 0);
signal reg_fxpXFracHalf_uid46_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_3_q : std_logic_vector (0 downto 0);
signal reg_expXIsZero_uid23_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_4_q : std_logic_vector (0 downto 0);
signal reg_xIsHalf_uid83_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_5_q : std_logic_vector (0 downto 0);
signal reg_pad_o_uid16_uid47_fpCosPiTest_0_to_oMFxpXFrac_uid47_fpCosPiTest_0_q : std_logic_vector (36 downto 0);
signal reg_pad_half_uid17_uid52_fpCosPiTest_0_to_z_halfMRRFxPXE_uid52_fpCosPiTest_0_q : std_logic_vector (35 downto 0);
signal reg_rVStage_uid138_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid139_lzcZ_uid56_fpCosPiTest_1_q : std_logic_vector (31 downto 0);
signal reg_cStage_uid142_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid144_lzcZ_uid56_fpCosPiTest_3_q : std_logic_vector (31 downto 0);
signal reg_rVStage_uid146_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid147_lzcZ_uid56_fpCosPiTest_1_q : std_logic_vector (15 downto 0);
signal reg_vStage_uid148_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid150_lzcZ_uid56_fpCosPiTest_3_q : std_logic_vector (15 downto 0);
signal reg_rVStage_uid158_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid159_lzcZ_uid56_fpCosPiTest_1_q : std_logic_vector (3 downto 0);
signal reg_vStage_uid160_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid162_lzcZ_uid56_fpCosPiTest_3_q : std_logic_vector (3 downto 0);
signal reg_vCount_uid153_lzcZ_uid56_fpCosPiTest_0_to_r_uid172_lzcZ_uid56_fpCosPiTest_3_q : std_logic_vector (0 downto 0);
signal reg_leftShiftStageSel3Dto2_uid193_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_2_q : std_logic_vector (34 downto 0);
signal reg_leftShiftStage1Idx1_uid186_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_3_q : std_logic_vector (34 downto 0);
signal reg_leftShiftStage1Idx2_uid189_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_4_q : std_logic_vector (34 downto 0);
signal reg_leftShiftStage1Idx3_uid192_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_5_q : std_logic_vector (34 downto 0);
signal reg_leftShiftStageSel1Dto0_uid204_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_zAddr_uid62_fpCosPiTest_0_to_memoryC2_uid209_sinPiZTableGenerator_0_q : std_logic_vector (6 downto 0);
signal reg_yT1_uid210_sinPiZPolyEval_0_to_prodXY_uid226_pT1_uid211_sinPiZPolyEval_0_q : std_logic_vector (13 downto 0);
signal reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_q : std_logic_vector (15 downto 0);
signal reg_s1_uid212_uid215_sinPiZPolyEval_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_1_q : std_logic_vector (22 downto 0);
signal reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_q : std_logic_vector (23 downto 0);
signal reg_fxpSinRes_uid65_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_1_q : std_logic_vector (24 downto 0);
signal reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q : std_logic_vector (5 downto 0);
signal reg_expP_uid60_fpCosPiTest_0_to_expFracPreRnd_uid71_uid71_fpCosPiTest_1_q : std_logic_vector (7 downto 0);
signal reg_excRNaN_uid84_fpCosPiTest_0_to_fracRPostExc_uid88_fpCosPiTest_1_q : std_logic_vector (0 downto 0);
signal reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q : std_logic_vector (1 downto 0);
signal ld_FxpXFrac35_uid44_fpCosPiTest_b_to_rangeReducedFxPX_uid51_fpCosPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_fxpXFrac_uid43_fpCosPiTest_b_to_rangeReducedFxPX_uid51_fpCosPiTest_c_q : std_logic_vector (35 downto 0);
signal ld_cosXIsOne_uid36_fpCosPiTest_c_to_InvCosXIsOne_uid77_fpCosPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_xEvenInt_uid35_fpCosPiTest_c_to_evenIntCosNotOneFZ_uid79_fpCosPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_exc_R_uid34_fpCosPiTest_q_to_xIsInt_uid80_fpCosPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_reg_cosXIsOne_uid36_fpCosPiTest_1_to_bigCond_uid85_fpCosPiTest_1_q_to_bigCond_uid85_fpCosPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_bigCond_uid85_fpCosPiTest_q_to_fracRPostExc1_uid86_fpCosPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_reg_excRNaN_uid84_fpCosPiTest_0_to_fracRPostExc_uid88_fpCosPiTest_1_q_to_fracRPostExc_uid88_fpCosPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_xIsHalf_uid83_fpCosPiTest_q_to_expRPostExc1_uid91_fpCosPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_expXIsZero_uid23_fpCosPiTest_q_to_xIntOrXZOrCosOne_uid93_fpCosPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_rInfOrNaN_uid92_fpCosPiTest_q_to_join_uid94_fpCosPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_xParityXorHalfParity_uid96_fpCosPiTest_q_to_signRComp_uid99_fpCosPiTest_c_q : std_logic_vector (0 downto 0);
signal ld_fxpXFracHalf_uid46_fpCosPiTest_q_to_InvFxpXFracHalf_uid100_fpCosPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_signR_uid101_fpCosPiTest_q_to_R_uid102_fpCosPiTest_c_q : std_logic_vector (0 downto 0);
signal ld_vCount_uid147_lzcZ_uid56_fpCosPiTest_q_to_r_uid172_lzcZ_uid56_fpCosPiTest_e_q : std_logic_vector (0 downto 0);
signal ld_vCount_uid139_lzcZ_uid56_fpCosPiTest_q_to_r_uid172_lzcZ_uid56_fpCosPiTest_f_q : std_logic_vector (0 downto 0);
signal ld_X18dto0_uid176_alignedZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx1_uid177_alignedZ_uid57_fpCosPiTest_b_q : std_logic_vector (18 downto 0);
signal ld_vStage_uid141_lzcZ_uid56_fpCosPiTest_b_to_leftShiftStage0Idx2_uid180_alignedZ_uid57_fpCosPiTest_b_q : std_logic_vector (2 downto 0);
signal ld_z_uid54_fpCosPiTest_b_to_leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_c_q : std_logic_vector (34 downto 0);
signal ld_reg_yT1_uid210_sinPiZPolyEval_0_to_prodXY_uid226_pT1_uid211_sinPiZPolyEval_0_q_to_prodXY_uid226_pT1_uid211_sinPiZPolyEval_a_q : std_logic_vector (13 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_reset0 : std_logic;
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_ia : std_logic_vector (5 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_iq : std_logic_vector (5 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_q : std_logic_vector (5 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt_eq : std_logic;
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_mem_top_q : std_logic_vector (3 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve : boolean;
attribute preserve of ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_sticky_ena_q : signal is true;
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_reset0 : std_logic;
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_ia : std_logic_vector (1 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_iq : std_logic_vector (1 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_q : std_logic_vector (1 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt_eq : std_logic;
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_mem_top_q : std_logic_vector (4 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_sticky_ena_q : signal is true;
signal ld_X18dto0_uid176_alignedZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx1_uid177_alignedZ_uid57_fpCosPiTest_b_inputreg_q : std_logic_vector (18 downto 0);
signal ld_z_uid54_fpCosPiTest_b_to_leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_c_inputreg_q : std_logic_vector (34 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_reset0 : std_logic;
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_ia : std_logic_vector (6 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_iq : std_logic_vector (6 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_q : std_logic_vector (6 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_sticky_ena_q : signal is true;
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_reset0 : std_logic;
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_ia : std_logic_vector (6 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_aa : std_logic_vector (1 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_ab : std_logic_vector (1 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_iq : std_logic_vector (6 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_q : std_logic_vector (6 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt_q : std_logic_vector(1 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt_i : unsigned(1 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt_eq : std_logic;
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdreg_q : std_logic_vector (1 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_mem_top_q : std_logic_vector (2 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_sticky_ena_q : signal is true;
signal ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_inputreg_q : std_logic_vector (15 downto 0);
signal ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_reset0 : std_logic;
signal ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_ia : std_logic_vector (15 downto 0);
signal ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_aa : std_logic_vector (1 downto 0);
signal ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_ab : std_logic_vector (1 downto 0);
signal ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_iq : std_logic_vector (15 downto 0);
signal ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_q : std_logic_vector (15 downto 0);
signal ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_sticky_ena_q : signal is true;
signal ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_inputreg_q : std_logic_vector (23 downto 0);
signal ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_reset0 : std_logic;
signal ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_ia : std_logic_vector (23 downto 0);
signal ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_aa : std_logic_vector (1 downto 0);
signal ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_ab : std_logic_vector (1 downto 0);
signal ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_iq : std_logic_vector (23 downto 0);
signal ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_q : std_logic_vector (23 downto 0);
signal ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_sticky_ena_q : signal is true;
signal pad_o_uid16_uid47_fpCosPiTest_q : std_logic_vector (36 downto 0);
signal pad_half_uid17_uid52_fpCosPiTest_q : std_logic_vector (35 downto 0);
signal bigCond_uid85_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal bigCond_uid85_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal bigCond_uid85_fpCosPiTest_c : std_logic_vector(0 downto 0);
signal bigCond_uid85_fpCosPiTest_d : std_logic_vector(0 downto 0);
signal bigCond_uid85_fpCosPiTest_f : std_logic_vector(0 downto 0);
signal bigCond_uid85_fpCosPiTest_g : std_logic_vector(0 downto 0);
signal bigCond_uid85_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal InvCosXIsOne_uid77_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal InvCosXIsOne_uid77_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal InvXEvenInt_uid81_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal InvXEvenInt_uid81_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal InvFxpXFracHalf_uid100_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal InvFxpXFracHalf_uid100_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal cstHalfwSwFP1_uid18_fpCosPiTest_q : std_logic_vector (35 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_notEnable_a : std_logic_vector(0 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_notEnable_q : std_logic_vector(0 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdmux_q : std_logic_vector (1 downto 0);
signal expX_uid6_fpCosPiTest_in : std_logic_vector (30 downto 0);
signal expX_uid6_fpCosPiTest_b : std_logic_vector (7 downto 0);
signal fracX_uid7_fpCosPiTest_in : std_logic_vector (22 downto 0);
signal fracX_uid7_fpCosPiTest_b : std_logic_vector (22 downto 0);
signal expXIsZero_uid23_fpCosPiTest_a : std_logic_vector(7 downto 0);
signal expXIsZero_uid23_fpCosPiTest_b : std_logic_vector(7 downto 0);
signal expXIsZero_uid23_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal expXIsMax_uid25_fpCosPiTest_a : std_logic_vector(7 downto 0);
signal expXIsMax_uid25_fpCosPiTest_b : std_logic_vector(7 downto 0);
signal expXIsMax_uid25_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal fracXIsZero_uid27_fpCosPiTest_a : std_logic_vector(22 downto 0);
signal fracXIsZero_uid27_fpCosPiTest_b : std_logic_vector(22 downto 0);
signal fracXIsZero_uid27_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal exc_I_uid28_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal exc_I_uid28_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal exc_I_uid28_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal xEvenInt_uid35_fpCosPiTest_a : std_logic_vector(10 downto 0);
signal xEvenInt_uid35_fpCosPiTest_b : std_logic_vector(10 downto 0);
signal xEvenInt_uid35_fpCosPiTest_o : std_logic_vector (10 downto 0);
signal xEvenInt_uid35_fpCosPiTest_cin : std_logic_vector (0 downto 0);
signal xEvenInt_uid35_fpCosPiTest_c : std_logic_vector (0 downto 0);
signal cosXIsOne_uid36_fpCosPiTest_a : std_logic_vector(10 downto 0);
signal cosXIsOne_uid36_fpCosPiTest_b : std_logic_vector(10 downto 0);
signal cosXIsOne_uid36_fpCosPiTest_o : std_logic_vector (10 downto 0);
signal cosXIsOne_uid36_fpCosPiTest_cin : std_logic_vector (0 downto 0);
signal cosXIsOne_uid36_fpCosPiTest_c : std_logic_vector (0 downto 0);
signal shiftValFxPX_uid38_fpCosPiTest_a : std_logic_vector(8 downto 0);
signal shiftValFxPX_uid38_fpCosPiTest_b : std_logic_vector(8 downto 0);
signal shiftValFxPX_uid38_fpCosPiTest_o : std_logic_vector (8 downto 0);
signal shiftValFxPX_uid38_fpCosPiTest_q : std_logic_vector (8 downto 0);
signal fxpXFracZero_uid45_fpCosPiTest_a : std_logic_vector(35 downto 0);
signal fxpXFracZero_uid45_fpCosPiTest_b : std_logic_vector(35 downto 0);
signal fxpXFracZero_uid45_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal fxpXFracHalf_uid46_fpCosPiTest_a : std_logic_vector(35 downto 0);
signal fxpXFracHalf_uid46_fpCosPiTest_b : std_logic_vector(35 downto 0);
signal fxpXFracHalf_uid46_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal oMFxpXFrac_uid47_fpCosPiTest_a : std_logic_vector(37 downto 0);
signal oMFxpXFrac_uid47_fpCosPiTest_b : std_logic_vector(37 downto 0);
signal oMFxpXFrac_uid47_fpCosPiTest_o : std_logic_vector (37 downto 0);
signal oMFxpXFrac_uid47_fpCosPiTest_q : std_logic_vector (37 downto 0);
signal z_halfMRRFxPXE_uid52_fpCosPiTest_a : std_logic_vector(36 downto 0);
signal z_halfMRRFxPXE_uid52_fpCosPiTest_b : std_logic_vector(36 downto 0);
signal z_halfMRRFxPXE_uid52_fpCosPiTest_o : std_logic_vector (36 downto 0);
signal z_halfMRRFxPXE_uid52_fpCosPiTest_q : std_logic_vector (36 downto 0);
signal expHardCase_uid59_fpCosPiTest_a : std_logic_vector(8 downto 0);
signal expHardCase_uid59_fpCosPiTest_b : std_logic_vector(8 downto 0);
signal expHardCase_uid59_fpCosPiTest_o : std_logic_vector (8 downto 0);
signal expHardCase_uid59_fpCosPiTest_q : std_logic_vector (8 downto 0);
signal fracZCosNotOne_uid78_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal fracZCosNotOne_uid78_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal fracZCosNotOne_uid78_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal evenIntCosNotOneFZ_uid79_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal evenIntCosNotOneFZ_uid79_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal evenIntCosNotOneFZ_uid79_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal xIsInt_uid80_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal xIsInt_uid80_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal xIsInt_uid80_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal xIsHalf_uid83_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal xIsHalf_uid83_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal xIsHalf_uid83_fpCosPiTest_c : std_logic_vector(0 downto 0);
signal xIsHalf_uid83_fpCosPiTest_d : std_logic_vector(0 downto 0);
signal xIsHalf_uid83_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal fracRPostExc_uid88_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal fracRPostExc_uid88_fpCosPiTest_q : std_logic_vector (22 downto 0);
signal xIntOrXZOrCosOne_uid93_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal xIntOrXZOrCosOne_uid93_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal xIntOrXZOrCosOne_uid93_fpCosPiTest_c : std_logic_vector(0 downto 0);
signal xIntOrXZOrCosOne_uid93_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal expRPostExc_uid95_fpCosPiTest_s : std_logic_vector (1 downto 0);
signal expRPostExc_uid95_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_q : std_logic_vector (36 downto 0);
signal vCount_uid139_lzcZ_uid56_fpCosPiTest_a : std_logic_vector(31 downto 0);
signal vCount_uid139_lzcZ_uid56_fpCosPiTest_b : std_logic_vector(31 downto 0);
signal vCount_uid139_lzcZ_uid56_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid144_lzcZ_uid56_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid144_lzcZ_uid56_fpCosPiTest_q : std_logic_vector (31 downto 0);
signal vCount_uid147_lzcZ_uid56_fpCosPiTest_a : std_logic_vector(15 downto 0);
signal vCount_uid147_lzcZ_uid56_fpCosPiTest_b : std_logic_vector(15 downto 0);
signal vCount_uid147_lzcZ_uid56_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid150_lzcZ_uid56_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid150_lzcZ_uid56_fpCosPiTest_q : std_logic_vector (15 downto 0);
signal vCount_uid159_lzcZ_uid56_fpCosPiTest_a : std_logic_vector(3 downto 0);
signal vCount_uid159_lzcZ_uid56_fpCosPiTest_b : std_logic_vector(3 downto 0);
signal vCount_uid159_lzcZ_uid56_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid162_lzcZ_uid56_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid162_lzcZ_uid56_fpCosPiTest_q : std_logic_vector (3 downto 0);
signal leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_q : std_logic_vector (34 downto 0);
signal memoryC0_uid207_sinPiZTableGenerator_q : std_logic_vector(28 downto 0);
signal memoryC1_uid208_sinPiZTableGenerator_q : std_logic_vector(20 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal leftShiftStage0Idx1_uid177_alignedZ_uid57_fpCosPiTest_q : std_logic_vector (34 downto 0);
signal leftShiftStage0Idx2_uid180_alignedZ_uid57_fpCosPiTest_q : std_logic_vector (34 downto 0);
signal prodXYTruncFR_uid224_mul2xSinRes_uid66_fpCosPiTest_in : std_logic_vector (48 downto 0);
signal prodXYTruncFR_uid224_mul2xSinRes_uid66_fpCosPiTest_b : std_logic_vector (25 downto 0);
signal prodXYTruncFR_uid227_pT1_uid211_sinPiZPolyEval_in : std_logic_vector (27 downto 0);
signal prodXYTruncFR_uid227_pT1_uid211_sinPiZPolyEval_b : std_logic_vector (14 downto 0);
signal prodXYTruncFR_uid230_pT2_uid217_sinPiZPolyEval_in : std_logic_vector (38 downto 0);
signal prodXYTruncFR_uid230_pT2_uid217_sinPiZPolyEval_b : std_logic_vector (23 downto 0);
signal join_uid94_fpCosPiTest_q : std_logic_vector (1 downto 0);
signal R_uid102_fpCosPiTest_q : std_logic_vector (31 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_cmp_a : std_logic_vector(3 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_cmp_b : std_logic_vector(3 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_cmp_a : std_logic_vector(4 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_cmp_b : std_logic_vector(4 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_cmp_a : std_logic_vector(2 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_cmp_b : std_logic_vector(2 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_nor_q : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_nor_q : std_logic_vector(0 downto 0);
signal oFracX_uid37_uid37_fpCosPiTest_q : std_logic_vector (23 downto 0);
signal InvExpXIsZero_uid33_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid33_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid29_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid29_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal InvExc_I_uid32_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal InvExc_I_uid32_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal fxpShifterBits_uid40_fpCosPiTest_in : std_logic_vector (5 downto 0);
signal fxpShifterBits_uid40_fpCosPiTest_b : std_logic_vector (5 downto 0);
signal oMFxpXFrac_uid49_fpCosPiTest_in : std_logic_vector (35 downto 0);
signal oMFxpXFrac_uid49_fpCosPiTest_b : std_logic_vector (35 downto 0);
signal z_uid54_fpCosPiTest_in : std_logic_vector (34 downto 0);
signal z_uid54_fpCosPiTest_b : std_logic_vector (34 downto 0);
signal expP_uid60_fpCosPiTest_in : std_logic_vector (7 downto 0);
signal expP_uid60_fpCosPiTest_b : std_logic_vector (7 downto 0);
signal LeftShiftStage135dto0_uid126_fxpX_uid41_fpCosPiTest_in : std_logic_vector (35 downto 0);
signal LeftShiftStage135dto0_uid126_fxpX_uid41_fpCosPiTest_b : std_logic_vector (35 downto 0);
signal LeftShiftStage134dto0_uid129_fxpX_uid41_fpCosPiTest_in : std_logic_vector (34 downto 0);
signal LeftShiftStage134dto0_uid129_fxpX_uid41_fpCosPiTest_b : std_logic_vector (34 downto 0);
signal LeftShiftStage133dto0_uid132_fxpX_uid41_fpCosPiTest_in : std_logic_vector (33 downto 0);
signal LeftShiftStage133dto0_uid132_fxpX_uid41_fpCosPiTest_b : std_logic_vector (33 downto 0);
signal rVStage_uid146_lzcZ_uid56_fpCosPiTest_in : std_logic_vector (31 downto 0);
signal rVStage_uid146_lzcZ_uid56_fpCosPiTest_b : std_logic_vector (15 downto 0);
signal vStage_uid148_lzcZ_uid56_fpCosPiTest_in : std_logic_vector (15 downto 0);
signal vStage_uid148_lzcZ_uid56_fpCosPiTest_b : std_logic_vector (15 downto 0);
signal rVStage_uid152_lzcZ_uid56_fpCosPiTest_in : std_logic_vector (15 downto 0);
signal rVStage_uid152_lzcZ_uid56_fpCosPiTest_b : std_logic_vector (7 downto 0);
signal vStage_uid154_lzcZ_uid56_fpCosPiTest_in : std_logic_vector (7 downto 0);
signal vStage_uid154_lzcZ_uid56_fpCosPiTest_b : std_logic_vector (7 downto 0);
signal rVStage_uid164_lzcZ_uid56_fpCosPiTest_in : std_logic_vector (3 downto 0);
signal rVStage_uid164_lzcZ_uid56_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal vStage_uid166_lzcZ_uid56_fpCosPiTest_in : std_logic_vector (1 downto 0);
signal vStage_uid166_lzcZ_uid56_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal LeftShiftStage133dto0_uid196_alignedZ_uid57_fpCosPiTest_in : std_logic_vector (33 downto 0);
signal LeftShiftStage133dto0_uid196_alignedZ_uid57_fpCosPiTest_b : std_logic_vector (33 downto 0);
signal LeftShiftStage132dto0_uid199_alignedZ_uid57_fpCosPiTest_in : std_logic_vector (32 downto 0);
signal LeftShiftStage132dto0_uid199_alignedZ_uid57_fpCosPiTest_b : std_logic_vector (32 downto 0);
signal LeftShiftStage131dto0_uid202_alignedZ_uid57_fpCosPiTest_in : std_logic_vector (31 downto 0);
signal LeftShiftStage131dto0_uid202_alignedZ_uid57_fpCosPiTest_b : std_logic_vector (31 downto 0);
signal normBit_uid67_fpCosPiTest_in : std_logic_vector (25 downto 0);
signal normBit_uid67_fpCosPiTest_b : std_logic_vector (0 downto 0);
signal highRes_uid68_fpCosPiTest_in : std_logic_vector (24 downto 0);
signal highRes_uid68_fpCosPiTest_b : std_logic_vector (23 downto 0);
signal lowRes_uid69_fpCosPiTest_in : std_logic_vector (23 downto 0);
signal lowRes_uid69_fpCosPiTest_b : std_logic_vector (23 downto 0);
signal lowRangeB_uid212_sinPiZPolyEval_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid212_sinPiZPolyEval_b : std_logic_vector (0 downto 0);
signal highBBits_uid213_sinPiZPolyEval_in : std_logic_vector (14 downto 0);
signal highBBits_uid213_sinPiZPolyEval_b : std_logic_vector (13 downto 0);
signal lowRangeB_uid218_sinPiZPolyEval_in : std_logic_vector (1 downto 0);
signal lowRangeB_uid218_sinPiZPolyEval_b : std_logic_vector (1 downto 0);
signal highBBits_uid219_sinPiZPolyEval_in : std_logic_vector (23 downto 0);
signal highBBits_uid219_sinPiZPolyEval_b : std_logic_vector (21 downto 0);
signal oFracXExt_uid39_fpCosPiTest_q : std_logic_vector (36 downto 0);
signal exc_N_uid30_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal exc_N_uid30_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal exc_N_uid30_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal leftShiftStageSel5Dto4_uid112_fxpX_uid41_fpCosPiTest_in : std_logic_vector (5 downto 0);
signal leftShiftStageSel5Dto4_uid112_fxpX_uid41_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel3Dto2_uid123_fxpX_uid41_fpCosPiTest_in : std_logic_vector (3 downto 0);
signal leftShiftStageSel3Dto2_uid123_fxpX_uid41_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid134_fxpX_uid41_fpCosPiTest_in : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid134_fxpX_uid41_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal zAddr_uid62_fpCosPiTest_in : std_logic_vector (34 downto 0);
signal zAddr_uid62_fpCosPiTest_b : std_logic_vector (6 downto 0);
signal zPPolyEval_uid63_fpCosPiTest_in : std_logic_vector (27 downto 0);
signal zPPolyEval_uid63_fpCosPiTest_b : std_logic_vector (15 downto 0);
signal rVStage_uid138_lzcZ_uid56_fpCosPiTest_in : std_logic_vector (34 downto 0);
signal rVStage_uid138_lzcZ_uid56_fpCosPiTest_b : std_logic_vector (31 downto 0);
signal vStage_uid141_lzcZ_uid56_fpCosPiTest_in : std_logic_vector (2 downto 0);
signal vStage_uid141_lzcZ_uid56_fpCosPiTest_b : std_logic_vector (2 downto 0);
signal X18dto0_uid176_alignedZ_uid57_fpCosPiTest_in : std_logic_vector (18 downto 0);
signal X18dto0_uid176_alignedZ_uid57_fpCosPiTest_b : std_logic_vector (18 downto 0);
signal leftShiftStage2Idx1_uid127_fxpX_uid41_fpCosPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage2Idx2_uid130_fxpX_uid41_fpCosPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage2Idx3_uid133_fxpX_uid41_fpCosPiTest_q : std_logic_vector (36 downto 0);
signal vCount_uid153_lzcZ_uid56_fpCosPiTest_a : std_logic_vector(7 downto 0);
signal vCount_uid153_lzcZ_uid56_fpCosPiTest_b : std_logic_vector(7 downto 0);
signal vCount_uid153_lzcZ_uid56_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid156_lzcZ_uid56_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid156_lzcZ_uid56_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal vCount_uid165_lzcZ_uid56_fpCosPiTest_a : std_logic_vector(1 downto 0);
signal vCount_uid165_lzcZ_uid56_fpCosPiTest_b : std_logic_vector(1 downto 0);
signal vCount_uid165_lzcZ_uid56_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid168_lzcZ_uid56_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid168_lzcZ_uid56_fpCosPiTest_q : std_logic_vector (1 downto 0);
signal leftShiftStage2Idx1_uid197_alignedZ_uid57_fpCosPiTest_q : std_logic_vector (34 downto 0);
signal leftShiftStage2Idx2_uid200_alignedZ_uid57_fpCosPiTest_q : std_logic_vector (34 downto 0);
signal leftShiftStage2Idx3_uid203_alignedZ_uid57_fpCosPiTest_q : std_logic_vector (34 downto 0);
signal fracRCompPreRnd_uid70_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal fracRCompPreRnd_uid70_fpCosPiTest_q : std_logic_vector (23 downto 0);
signal rndExpUpdate_uid72_uid73_fpCosPiTest_q : std_logic_vector (24 downto 0);
signal sumAHighB_uid214_sinPiZPolyEval_a : std_logic_vector(21 downto 0);
signal sumAHighB_uid214_sinPiZPolyEval_b : std_logic_vector(21 downto 0);
signal sumAHighB_uid214_sinPiZPolyEval_o : std_logic_vector (21 downto 0);
signal sumAHighB_uid214_sinPiZPolyEval_q : std_logic_vector (21 downto 0);
signal sumAHighB_uid220_sinPiZPolyEval_a : std_logic_vector(29 downto 0);
signal sumAHighB_uid220_sinPiZPolyEval_b : std_logic_vector(29 downto 0);
signal sumAHighB_uid220_sinPiZPolyEval_o : std_logic_vector (29 downto 0);
signal sumAHighB_uid220_sinPiZPolyEval_q : std_logic_vector (29 downto 0);
signal X20dto0_uid106_fxpX_uid41_fpCosPiTest_in : std_logic_vector (20 downto 0);
signal X20dto0_uid106_fxpX_uid41_fpCosPiTest_b : std_logic_vector (20 downto 0);
signal X4dto0_uid109_fxpX_uid41_fpCosPiTest_in : std_logic_vector (4 downto 0);
signal X4dto0_uid109_fxpX_uid41_fpCosPiTest_b : std_logic_vector (4 downto 0);
signal InvExc_N_uid31_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal InvExc_N_uid31_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal excRNaN_uid84_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal excRNaN_uid84_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal excRNaN_uid84_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal yT1_uid210_sinPiZPolyEval_in : std_logic_vector (15 downto 0);
signal yT1_uid210_sinPiZPolyEval_b : std_logic_vector (13 downto 0);
signal cStage_uid142_lzcZ_uid56_fpCosPiTest_q : std_logic_vector (31 downto 0);
signal leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest_q : std_logic_vector (36 downto 0);
signal rVStage_uid158_lzcZ_uid56_fpCosPiTest_in : std_logic_vector (7 downto 0);
signal rVStage_uid158_lzcZ_uid56_fpCosPiTest_b : std_logic_vector (3 downto 0);
signal vStage_uid160_lzcZ_uid56_fpCosPiTest_in : std_logic_vector (3 downto 0);
signal vStage_uid160_lzcZ_uid56_fpCosPiTest_b : std_logic_vector (3 downto 0);
signal rVStage_uid170_lzcZ_uid56_fpCosPiTest_in : std_logic_vector (1 downto 0);
signal rVStage_uid170_lzcZ_uid56_fpCosPiTest_b : std_logic_vector (0 downto 0);
signal leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest_q : std_logic_vector (34 downto 0);
signal expFracPreRnd_uid71_uid71_fpCosPiTest_q : std_logic_vector (31 downto 0);
signal expFracComp_uid74_fpCosPiTest_a : std_logic_vector(32 downto 0);
signal expFracComp_uid74_fpCosPiTest_b : std_logic_vector(32 downto 0);
signal expFracComp_uid74_fpCosPiTest_o : std_logic_vector (32 downto 0);
signal expFracComp_uid74_fpCosPiTest_q : std_logic_vector (32 downto 0);
signal s1_uid212_uid215_sinPiZPolyEval_q : std_logic_vector (22 downto 0);
signal s2_uid218_uid221_sinPiZPolyEval_q : std_logic_vector (31 downto 0);
signal leftShiftStage0Idx1_uid107_fxpX_uid41_fpCosPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage0Idx2_uid110_fxpX_uid41_fpCosPiTest_q : std_logic_vector (36 downto 0);
signal exc_R_uid34_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal exc_R_uid34_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal exc_R_uid34_fpCosPiTest_c : std_logic_vector(0 downto 0);
signal exc_R_uid34_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal rInfOrNaN_uid92_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal rInfOrNaN_uid92_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal rInfOrNaN_uid92_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal FxpX36_uid42_fpCosPiTest_in : std_logic_vector (36 downto 0);
signal FxpX36_uid42_fpCosPiTest_b : std_logic_vector (0 downto 0);
signal fxpXFrac_uid43_fpCosPiTest_in : std_logic_vector (35 downto 0);
signal fxpXFrac_uid43_fpCosPiTest_b : std_logic_vector (35 downto 0);
signal vCount_uid171_lzcZ_uid56_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal vCount_uid171_lzcZ_uid56_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal vCount_uid171_lzcZ_uid56_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal alignedZLow_uid58_fpCosPiTest_in : std_logic_vector (34 downto 0);
signal alignedZLow_uid58_fpCosPiTest_b : std_logic_vector (23 downto 0);
signal fracRComp_uid75_fpCosPiTest_in : std_logic_vector (23 downto 0);
signal fracRComp_uid75_fpCosPiTest_b : std_logic_vector (22 downto 0);
signal expRComp_uid76_fpCosPiTest_in : std_logic_vector (31 downto 0);
signal expRComp_uid76_fpCosPiTest_b : std_logic_vector (7 downto 0);
signal fxpSinRes_uid65_fpCosPiTest_in : std_logic_vector (29 downto 0);
signal fxpSinRes_uid65_fpCosPiTest_b : std_logic_vector (24 downto 0);
signal leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_q : std_logic_vector (36 downto 0);
signal FxpXFrac35_uid44_fpCosPiTest_in : std_logic_vector (35 downto 0);
signal FxpXFrac35_uid44_fpCosPiTest_b : std_logic_vector (0 downto 0);
signal r_uid172_lzcZ_uid56_fpCosPiTest_q : std_logic_vector (5 downto 0);
signal LeftShiftStage032dto0_uid115_fxpX_uid41_fpCosPiTest_in : std_logic_vector (32 downto 0);
signal LeftShiftStage032dto0_uid115_fxpX_uid41_fpCosPiTest_b : std_logic_vector (32 downto 0);
signal LeftShiftStage028dto0_uid118_fxpX_uid41_fpCosPiTest_in : std_logic_vector (28 downto 0);
signal LeftShiftStage028dto0_uid118_fxpX_uid41_fpCosPiTest_b : std_logic_vector (28 downto 0);
signal LeftShiftStage024dto0_uid121_fxpX_uid41_fpCosPiTest_in : std_logic_vector (24 downto 0);
signal LeftShiftStage024dto0_uid121_fxpX_uid41_fpCosPiTest_b : std_logic_vector (24 downto 0);
signal xParityXorHalfParity_uid96_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal xParityXorHalfParity_uid96_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal xParityXorHalfParity_uid96_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal leftShiftStageSel5Dto4_uid182_alignedZ_uid57_fpCosPiTest_in : std_logic_vector (5 downto 0);
signal leftShiftStageSel5Dto4_uid182_alignedZ_uid57_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel3Dto2_uid193_alignedZ_uid57_fpCosPiTest_in : std_logic_vector (3 downto 0);
signal leftShiftStageSel3Dto2_uid193_alignedZ_uid57_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid204_alignedZ_uid57_fpCosPiTest_in : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid204_alignedZ_uid57_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStage1Idx1_uid116_fxpX_uid41_fpCosPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage1Idx2_uid119_fxpX_uid41_fpCosPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage1Idx3_uid122_fxpX_uid41_fpCosPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_q : std_logic_vector (34 downto 0);
signal LeftShiftStage030dto0_uid185_alignedZ_uid57_fpCosPiTest_in : std_logic_vector (30 downto 0);
signal LeftShiftStage030dto0_uid185_alignedZ_uid57_fpCosPiTest_b : std_logic_vector (30 downto 0);
signal LeftShiftStage026dto0_uid188_alignedZ_uid57_fpCosPiTest_in : std_logic_vector (26 downto 0);
signal LeftShiftStage026dto0_uid188_alignedZ_uid57_fpCosPiTest_b : std_logic_vector (26 downto 0);
signal LeftShiftStage022dto0_uid191_alignedZ_uid57_fpCosPiTest_in : std_logic_vector (22 downto 0);
signal LeftShiftStage022dto0_uid191_alignedZ_uid57_fpCosPiTest_b : std_logic_vector (22 downto 0);
signal leftShiftStage1Idx1_uid186_alignedZ_uid57_fpCosPiTest_q : std_logic_vector (34 downto 0);
signal leftShiftStage1Idx2_uid189_alignedZ_uid57_fpCosPiTest_q : std_logic_vector (34 downto 0);
signal leftShiftStage1Idx3_uid192_alignedZ_uid57_fpCosPiTest_q : std_logic_vector (34 downto 0);
begin
--xIn(GPIN,3)@0
--LeftShiftStage133dto0_uid132_fxpX_uid41_fpCosPiTest(BITSELECT,131)@1
LeftShiftStage133dto0_uid132_fxpX_uid41_fpCosPiTest_in <= leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_q(33 downto 0);
LeftShiftStage133dto0_uid132_fxpX_uid41_fpCosPiTest_b <= LeftShiftStage133dto0_uid132_fxpX_uid41_fpCosPiTest_in(33 downto 0);
--leftShiftStage2Idx3Pad3_uid131_fxpX_uid41_fpCosPiTest(CONSTANT,130)
leftShiftStage2Idx3Pad3_uid131_fxpX_uid41_fpCosPiTest_q <= "000";
--leftShiftStage2Idx3_uid133_fxpX_uid41_fpCosPiTest(BITJOIN,132)@1
leftShiftStage2Idx3_uid133_fxpX_uid41_fpCosPiTest_q <= LeftShiftStage133dto0_uid132_fxpX_uid41_fpCosPiTest_b & leftShiftStage2Idx3Pad3_uid131_fxpX_uid41_fpCosPiTest_q;
--LeftShiftStage134dto0_uid129_fxpX_uid41_fpCosPiTest(BITSELECT,128)@1
LeftShiftStage134dto0_uid129_fxpX_uid41_fpCosPiTest_in <= leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_q(34 downto 0);
LeftShiftStage134dto0_uid129_fxpX_uid41_fpCosPiTest_b <= LeftShiftStage134dto0_uid129_fxpX_uid41_fpCosPiTest_in(34 downto 0);
--leftShiftStage2Idx2Pad2_uid128_fxpX_uid41_fpCosPiTest(CONSTANT,127)
leftShiftStage2Idx2Pad2_uid128_fxpX_uid41_fpCosPiTest_q <= "00";
--leftShiftStage2Idx2_uid130_fxpX_uid41_fpCosPiTest(BITJOIN,129)@1
leftShiftStage2Idx2_uid130_fxpX_uid41_fpCosPiTest_q <= LeftShiftStage134dto0_uid129_fxpX_uid41_fpCosPiTest_b & leftShiftStage2Idx2Pad2_uid128_fxpX_uid41_fpCosPiTest_q;
--LeftShiftStage135dto0_uid126_fxpX_uid41_fpCosPiTest(BITSELECT,125)@1
LeftShiftStage135dto0_uid126_fxpX_uid41_fpCosPiTest_in <= leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_q(35 downto 0);
LeftShiftStage135dto0_uid126_fxpX_uid41_fpCosPiTest_b <= LeftShiftStage135dto0_uid126_fxpX_uid41_fpCosPiTest_in(35 downto 0);
--GND(CONSTANT,0)
GND_q <= "0";
--leftShiftStage2Idx1_uid127_fxpX_uid41_fpCosPiTest(BITJOIN,126)@1
leftShiftStage2Idx1_uid127_fxpX_uid41_fpCosPiTest_q <= LeftShiftStage135dto0_uid126_fxpX_uid41_fpCosPiTest_b & GND_q;
--leftShiftStage0Idx3_uid111_fxpX_uid41_fpCosPiTest(CONSTANT,110)
leftShiftStage0Idx3_uid111_fxpX_uid41_fpCosPiTest_q <= "0000000000000000000000000000000000000";
--X4dto0_uid109_fxpX_uid41_fpCosPiTest(BITSELECT,108)@0
X4dto0_uid109_fxpX_uid41_fpCosPiTest_in <= oFracXExt_uid39_fpCosPiTest_q(4 downto 0);
X4dto0_uid109_fxpX_uid41_fpCosPiTest_b <= X4dto0_uid109_fxpX_uid41_fpCosPiTest_in(4 downto 0);
--leftShiftStage0Idx2Pad32_uid108_fxpX_uid41_fpCosPiTest(CONSTANT,107)
leftShiftStage0Idx2Pad32_uid108_fxpX_uid41_fpCosPiTest_q <= "00000000000000000000000000000000";
--leftShiftStage0Idx2_uid110_fxpX_uid41_fpCosPiTest(BITJOIN,109)@0
leftShiftStage0Idx2_uid110_fxpX_uid41_fpCosPiTest_q <= X4dto0_uid109_fxpX_uid41_fpCosPiTest_b & leftShiftStage0Idx2Pad32_uid108_fxpX_uid41_fpCosPiTest_q;
--X20dto0_uid106_fxpX_uid41_fpCosPiTest(BITSELECT,105)@0
X20dto0_uid106_fxpX_uid41_fpCosPiTest_in <= oFracXExt_uid39_fpCosPiTest_q(20 downto 0);
X20dto0_uid106_fxpX_uid41_fpCosPiTest_b <= X20dto0_uid106_fxpX_uid41_fpCosPiTest_in(20 downto 0);
--leftShiftStage0Idx1Pad16_uid105_fxpX_uid41_fpCosPiTest(CONSTANT,104)
leftShiftStage0Idx1Pad16_uid105_fxpX_uid41_fpCosPiTest_q <= "0000000000000000";
--leftShiftStage0Idx1_uid107_fxpX_uid41_fpCosPiTest(BITJOIN,106)@0
leftShiftStage0Idx1_uid107_fxpX_uid41_fpCosPiTest_q <= X20dto0_uid106_fxpX_uid41_fpCosPiTest_b & leftShiftStage0Idx1Pad16_uid105_fxpX_uid41_fpCosPiTest_q;
--cst01pWShift_uid14_fpCosPiTest(CONSTANT,13)
cst01pWShift_uid14_fpCosPiTest_q <= "0000000000000";
--VCC(CONSTANT,1)
VCC_q <= "1";
--fracX_uid7_fpCosPiTest(BITSELECT,6)@0
fracX_uid7_fpCosPiTest_in <= a(22 downto 0);
fracX_uid7_fpCosPiTest_b <= fracX_uid7_fpCosPiTest_in(22 downto 0);
--oFracX_uid37_uid37_fpCosPiTest(BITJOIN,36)@0
oFracX_uid37_uid37_fpCosPiTest_q <= VCC_q & fracX_uid7_fpCosPiTest_b;
--oFracXExt_uid39_fpCosPiTest(BITJOIN,38)@0
oFracXExt_uid39_fpCosPiTest_q <= cst01pWShift_uid14_fpCosPiTest_q & oFracX_uid37_uid37_fpCosPiTest_q;
--biasMwShiftMO_uid13_fpCosPiTest(CONSTANT,12)
biasMwShiftMO_uid13_fpCosPiTest_q <= "01110010";
--expX_uid6_fpCosPiTest(BITSELECT,5)@0
expX_uid6_fpCosPiTest_in <= a(30 downto 0);
expX_uid6_fpCosPiTest_b <= expX_uid6_fpCosPiTest_in(30 downto 23);
--shiftValFxPX_uid38_fpCosPiTest(SUB,37)@0
shiftValFxPX_uid38_fpCosPiTest_a <= STD_LOGIC_VECTOR("0" & expX_uid6_fpCosPiTest_b);
shiftValFxPX_uid38_fpCosPiTest_b <= STD_LOGIC_VECTOR("0" & biasMwShiftMO_uid13_fpCosPiTest_q);
shiftValFxPX_uid38_fpCosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(shiftValFxPX_uid38_fpCosPiTest_a) - UNSIGNED(shiftValFxPX_uid38_fpCosPiTest_b));
shiftValFxPX_uid38_fpCosPiTest_q <= shiftValFxPX_uid38_fpCosPiTest_o(8 downto 0);
--fxpShifterBits_uid40_fpCosPiTest(BITSELECT,39)@0
fxpShifterBits_uid40_fpCosPiTest_in <= shiftValFxPX_uid38_fpCosPiTest_q(5 downto 0);
fxpShifterBits_uid40_fpCosPiTest_b <= fxpShifterBits_uid40_fpCosPiTest_in(5 downto 0);
--leftShiftStageSel5Dto4_uid112_fxpX_uid41_fpCosPiTest(BITSELECT,111)@0
leftShiftStageSel5Dto4_uid112_fxpX_uid41_fpCosPiTest_in <= fxpShifterBits_uid40_fpCosPiTest_b;
leftShiftStageSel5Dto4_uid112_fxpX_uid41_fpCosPiTest_b <= leftShiftStageSel5Dto4_uid112_fxpX_uid41_fpCosPiTest_in(5 downto 4);
--leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest(MUX,112)@0
leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_s <= leftShiftStageSel5Dto4_uid112_fxpX_uid41_fpCosPiTest_b;
leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest: PROCESS (leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_s, en, oFracXExt_uid39_fpCosPiTest_q, leftShiftStage0Idx1_uid107_fxpX_uid41_fpCosPiTest_q, leftShiftStage0Idx2_uid110_fxpX_uid41_fpCosPiTest_q, leftShiftStage0Idx3_uid111_fxpX_uid41_fpCosPiTest_q)
BEGIN
CASE leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_s IS
WHEN "00" => leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_q <= oFracXExt_uid39_fpCosPiTest_q;
WHEN "01" => leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_q <= leftShiftStage0Idx1_uid107_fxpX_uid41_fpCosPiTest_q;
WHEN "10" => leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_q <= leftShiftStage0Idx2_uid110_fxpX_uid41_fpCosPiTest_q;
WHEN "11" => leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_q <= leftShiftStage0Idx3_uid111_fxpX_uid41_fpCosPiTest_q;
WHEN OTHERS => leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage024dto0_uid121_fxpX_uid41_fpCosPiTest(BITSELECT,120)@0
LeftShiftStage024dto0_uid121_fxpX_uid41_fpCosPiTest_in <= leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_q(24 downto 0);
LeftShiftStage024dto0_uid121_fxpX_uid41_fpCosPiTest_b <= LeftShiftStage024dto0_uid121_fxpX_uid41_fpCosPiTest_in(24 downto 0);
--leftShiftStage1Idx3Pad12_uid120_fxpX_uid41_fpCosPiTest(CONSTANT,119)
leftShiftStage1Idx3Pad12_uid120_fxpX_uid41_fpCosPiTest_q <= "000000000000";
--leftShiftStage1Idx3_uid122_fxpX_uid41_fpCosPiTest(BITJOIN,121)@0
leftShiftStage1Idx3_uid122_fxpX_uid41_fpCosPiTest_q <= LeftShiftStage024dto0_uid121_fxpX_uid41_fpCosPiTest_b & leftShiftStage1Idx3Pad12_uid120_fxpX_uid41_fpCosPiTest_q;
--reg_leftShiftStage1Idx3_uid122_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_5(REG,235)@0
reg_leftShiftStage1Idx3_uid122_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx3_uid122_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_5_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx3_uid122_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_5_q <= leftShiftStage1Idx3_uid122_fxpX_uid41_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage028dto0_uid118_fxpX_uid41_fpCosPiTest(BITSELECT,117)@0
LeftShiftStage028dto0_uid118_fxpX_uid41_fpCosPiTest_in <= leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_q(28 downto 0);
LeftShiftStage028dto0_uid118_fxpX_uid41_fpCosPiTest_b <= LeftShiftStage028dto0_uid118_fxpX_uid41_fpCosPiTest_in(28 downto 0);
--cstAllZWE_uid21_fpCosPiTest(CONSTANT,20)
cstAllZWE_uid21_fpCosPiTest_q <= "00000000";
--leftShiftStage1Idx2_uid119_fxpX_uid41_fpCosPiTest(BITJOIN,118)@0
leftShiftStage1Idx2_uid119_fxpX_uid41_fpCosPiTest_q <= LeftShiftStage028dto0_uid118_fxpX_uid41_fpCosPiTest_b & cstAllZWE_uid21_fpCosPiTest_q;
--reg_leftShiftStage1Idx2_uid119_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_4(REG,234)@0
reg_leftShiftStage1Idx2_uid119_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx2_uid119_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_4_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx2_uid119_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_4_q <= leftShiftStage1Idx2_uid119_fxpX_uid41_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage032dto0_uid115_fxpX_uid41_fpCosPiTest(BITSELECT,114)@0
LeftShiftStage032dto0_uid115_fxpX_uid41_fpCosPiTest_in <= leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_q(32 downto 0);
LeftShiftStage032dto0_uid115_fxpX_uid41_fpCosPiTest_b <= LeftShiftStage032dto0_uid115_fxpX_uid41_fpCosPiTest_in(32 downto 0);
--leftShiftStage1Idx1Pad4_uid114_fxpX_uid41_fpCosPiTest(CONSTANT,113)
leftShiftStage1Idx1Pad4_uid114_fxpX_uid41_fpCosPiTest_q <= "0000";
--leftShiftStage1Idx1_uid116_fxpX_uid41_fpCosPiTest(BITJOIN,115)@0
leftShiftStage1Idx1_uid116_fxpX_uid41_fpCosPiTest_q <= LeftShiftStage032dto0_uid115_fxpX_uid41_fpCosPiTest_b & leftShiftStage1Idx1Pad4_uid114_fxpX_uid41_fpCosPiTest_q;
--reg_leftShiftStage1Idx1_uid116_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_3(REG,233)@0
reg_leftShiftStage1Idx1_uid116_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx1_uid116_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_3_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx1_uid116_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_3_q <= leftShiftStage1Idx1_uid116_fxpX_uid41_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--reg_leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_2(REG,232)@0
reg_leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_2_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_2_q <= leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel3Dto2_uid123_fxpX_uid41_fpCosPiTest(BITSELECT,122)@0
leftShiftStageSel3Dto2_uid123_fxpX_uid41_fpCosPiTest_in <= fxpShifterBits_uid40_fpCosPiTest_b(3 downto 0);
leftShiftStageSel3Dto2_uid123_fxpX_uid41_fpCosPiTest_b <= leftShiftStageSel3Dto2_uid123_fxpX_uid41_fpCosPiTest_in(3 downto 2);
--reg_leftShiftStageSel3Dto2_uid123_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_1(REG,231)@0
reg_leftShiftStageSel3Dto2_uid123_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel3Dto2_uid123_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel3Dto2_uid123_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_1_q <= leftShiftStageSel3Dto2_uid123_fxpX_uid41_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest(MUX,123)@1
leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_s <= reg_leftShiftStageSel3Dto2_uid123_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_1_q;
leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest: PROCESS (leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_s, en, reg_leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_2_q, reg_leftShiftStage1Idx1_uid116_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_3_q, reg_leftShiftStage1Idx2_uid119_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_4_q, reg_leftShiftStage1Idx3_uid122_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_5_q)
BEGIN
CASE leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_s IS
WHEN "00" => leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_q <= reg_leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_2_q;
WHEN "01" => leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_q <= reg_leftShiftStage1Idx1_uid116_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_3_q;
WHEN "10" => leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_q <= reg_leftShiftStage1Idx2_uid119_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_4_q;
WHEN "11" => leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_q <= reg_leftShiftStage1Idx3_uid122_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_5_q;
WHEN OTHERS => leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--leftShiftStageSel1Dto0_uid134_fxpX_uid41_fpCosPiTest(BITSELECT,133)@0
leftShiftStageSel1Dto0_uid134_fxpX_uid41_fpCosPiTest_in <= fxpShifterBits_uid40_fpCosPiTest_b(1 downto 0);
leftShiftStageSel1Dto0_uid134_fxpX_uid41_fpCosPiTest_b <= leftShiftStageSel1Dto0_uid134_fxpX_uid41_fpCosPiTest_in(1 downto 0);
--reg_leftShiftStageSel1Dto0_uid134_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest_1(REG,236)@0
reg_leftShiftStageSel1Dto0_uid134_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel1Dto0_uid134_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel1Dto0_uid134_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest_1_q <= leftShiftStageSel1Dto0_uid134_fxpX_uid41_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest(MUX,134)@1
leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest_s <= reg_leftShiftStageSel1Dto0_uid134_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest_1_q;
leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest: PROCESS (leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest_s, en, leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_q, leftShiftStage2Idx1_uid127_fxpX_uid41_fpCosPiTest_q, leftShiftStage2Idx2_uid130_fxpX_uid41_fpCosPiTest_q, leftShiftStage2Idx3_uid133_fxpX_uid41_fpCosPiTest_q)
BEGIN
CASE leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest_s IS
WHEN "00" => leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest_q <= leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_q;
WHEN "01" => leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest_q <= leftShiftStage2Idx1_uid127_fxpX_uid41_fpCosPiTest_q;
WHEN "10" => leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest_q <= leftShiftStage2Idx2_uid130_fxpX_uid41_fpCosPiTest_q;
WHEN "11" => leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest_q <= leftShiftStage2Idx3_uid133_fxpX_uid41_fpCosPiTest_q;
WHEN OTHERS => leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--fxpXFrac_uid43_fpCosPiTest(BITSELECT,42)@1
fxpXFrac_uid43_fpCosPiTest_in <= leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest_q(35 downto 0);
fxpXFrac_uid43_fpCosPiTest_b <= fxpXFrac_uid43_fpCosPiTest_in(35 downto 0);
--FxpXFrac35_uid44_fpCosPiTest(BITSELECT,43)@1
FxpXFrac35_uid44_fpCosPiTest_in <= fxpXFrac_uid43_fpCosPiTest_b;
FxpXFrac35_uid44_fpCosPiTest_b <= FxpXFrac35_uid44_fpCosPiTest_in(35 downto 35);
--FxpX36_uid42_fpCosPiTest(BITSELECT,41)@1
FxpX36_uid42_fpCosPiTest_in <= leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest_q;
FxpX36_uid42_fpCosPiTest_b <= FxpX36_uid42_fpCosPiTest_in(36 downto 36);
--xParityXorHalfParity_uid96_fpCosPiTest(LOGICAL,95)@1
xParityXorHalfParity_uid96_fpCosPiTest_a <= FxpX36_uid42_fpCosPiTest_b;
xParityXorHalfParity_uid96_fpCosPiTest_b <= FxpXFrac35_uid44_fpCosPiTest_b;
xParityXorHalfParity_uid96_fpCosPiTest_q <= xParityXorHalfParity_uid96_fpCosPiTest_a xor xParityXorHalfParity_uid96_fpCosPiTest_b;
--ld_xParityXorHalfParity_uid96_fpCosPiTest_q_to_signRComp_uid99_fpCosPiTest_c(DELAY,369)@1
ld_xParityXorHalfParity_uid96_fpCosPiTest_q_to_signRComp_uid99_fpCosPiTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => xParityXorHalfParity_uid96_fpCosPiTest_q, xout => ld_xParityXorHalfParity_uid96_fpCosPiTest_q_to_signRComp_uid99_fpCosPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--cstBiasPwF_uid12_fpCosPiTest(CONSTANT,11)
cstBiasPwF_uid12_fpCosPiTest_q <= "10010110";
--xEvenInt_uid35_fpCosPiTest(COMPARE,34)@0
xEvenInt_uid35_fpCosPiTest_cin <= GND_q;
xEvenInt_uid35_fpCosPiTest_a <= STD_LOGIC_VECTOR("00" & cstBiasPwF_uid12_fpCosPiTest_q) & '0';
xEvenInt_uid35_fpCosPiTest_b <= STD_LOGIC_VECTOR("00" & expX_uid6_fpCosPiTest_b) & xEvenInt_uid35_fpCosPiTest_cin(0);
xEvenInt_uid35_fpCosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(xEvenInt_uid35_fpCosPiTest_a) - UNSIGNED(xEvenInt_uid35_fpCosPiTest_b));
xEvenInt_uid35_fpCosPiTest_c(0) <= xEvenInt_uid35_fpCosPiTest_o(10);
--ld_xEvenInt_uid35_fpCosPiTest_c_to_evenIntCosNotOneFZ_uid79_fpCosPiTest_a(DELAY,335)@0
ld_xEvenInt_uid35_fpCosPiTest_c_to_evenIntCosNotOneFZ_uid79_fpCosPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => xEvenInt_uid35_fpCosPiTest_c, xout => ld_xEvenInt_uid35_fpCosPiTest_c_to_evenIntCosNotOneFZ_uid79_fpCosPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--InvXEvenInt_uid81_fpCosPiTest(LOGICAL,80)@2
InvXEvenInt_uid81_fpCosPiTest_a <= ld_xEvenInt_uid35_fpCosPiTest_c_to_evenIntCosNotOneFZ_uid79_fpCosPiTest_a_q;
InvXEvenInt_uid81_fpCosPiTest_q <= not InvXEvenInt_uid81_fpCosPiTest_a;
--cosXIsOne_uid36_fpCosPiTest(COMPARE,35)@0
cosXIsOne_uid36_fpCosPiTest_cin <= GND_q;
cosXIsOne_uid36_fpCosPiTest_a <= STD_LOGIC_VECTOR("00" & expX_uid6_fpCosPiTest_b) & '0';
cosXIsOne_uid36_fpCosPiTest_b <= STD_LOGIC_VECTOR("00" & biasMwShiftMO_uid13_fpCosPiTest_q) & cosXIsOne_uid36_fpCosPiTest_cin(0);
cosXIsOne_uid36_fpCosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(cosXIsOne_uid36_fpCosPiTest_a) - UNSIGNED(cosXIsOne_uid36_fpCosPiTest_b));
cosXIsOne_uid36_fpCosPiTest_c(0) <= cosXIsOne_uid36_fpCosPiTest_o(10);
--ld_cosXIsOne_uid36_fpCosPiTest_c_to_InvCosXIsOne_uid77_fpCosPiTest_a(DELAY,332)@0
ld_cosXIsOne_uid36_fpCosPiTest_c_to_InvCosXIsOne_uid77_fpCosPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => cosXIsOne_uid36_fpCosPiTest_c, xout => ld_cosXIsOne_uid36_fpCosPiTest_c_to_InvCosXIsOne_uid77_fpCosPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--InvCosXIsOne_uid77_fpCosPiTest(LOGICAL,76)@2
InvCosXIsOne_uid77_fpCosPiTest_a <= ld_cosXIsOne_uid36_fpCosPiTest_c_to_InvCosXIsOne_uid77_fpCosPiTest_a_q;
InvCosXIsOne_uid77_fpCosPiTest_q <= not InvCosXIsOne_uid77_fpCosPiTest_a;
--signRComp_uid99_fpCosPiTest(LOGICAL,98)@2
signRComp_uid99_fpCosPiTest_a <= InvCosXIsOne_uid77_fpCosPiTest_q;
signRComp_uid99_fpCosPiTest_b <= InvXEvenInt_uid81_fpCosPiTest_q;
signRComp_uid99_fpCosPiTest_c <= ld_xParityXorHalfParity_uid96_fpCosPiTest_q_to_signRComp_uid99_fpCosPiTest_c_q;
signRComp_uid99_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
signRComp_uid99_fpCosPiTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1' AND en = "1") THEN
signRComp_uid99_fpCosPiTest_q <= signRComp_uid99_fpCosPiTest_a and signRComp_uid99_fpCosPiTest_b and signRComp_uid99_fpCosPiTest_c;
END IF;
END PROCESS;
--cstZwSwF_uid15_fpCosPiTest(CONSTANT,14)
cstZwSwF_uid15_fpCosPiTest_q <= "00000000000000000000000000000000000";
--cstHalfwSwFP1_uid18_fpCosPiTest(BITJOIN,17)@2
cstHalfwSwFP1_uid18_fpCosPiTest_q <= VCC_q & cstZwSwF_uid15_fpCosPiTest_q;
--reg_fxpXFrac_uid43_fpCosPiTest_0_to_fxpXFracZero_uid45_fpCosPiTest_1(REG,237)@1
reg_fxpXFrac_uid43_fpCosPiTest_0_to_fxpXFracZero_uid45_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fxpXFrac_uid43_fpCosPiTest_0_to_fxpXFracZero_uid45_fpCosPiTest_1_q <= "000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fxpXFrac_uid43_fpCosPiTest_0_to_fxpXFracZero_uid45_fpCosPiTest_1_q <= fxpXFrac_uid43_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--fxpXFracHalf_uid46_fpCosPiTest(LOGICAL,45)@2
fxpXFracHalf_uid46_fpCosPiTest_a <= reg_fxpXFrac_uid43_fpCosPiTest_0_to_fxpXFracZero_uid45_fpCosPiTest_1_q;
fxpXFracHalf_uid46_fpCosPiTest_b <= cstHalfwSwFP1_uid18_fpCosPiTest_q;
fxpXFracHalf_uid46_fpCosPiTest_q <= "1" when fxpXFracHalf_uid46_fpCosPiTest_a = fxpXFracHalf_uid46_fpCosPiTest_b else "0";
--ld_fxpXFracHalf_uid46_fpCosPiTest_q_to_InvFxpXFracHalf_uid100_fpCosPiTest_a(DELAY,370)@2
ld_fxpXFracHalf_uid46_fpCosPiTest_q_to_InvFxpXFracHalf_uid100_fpCosPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => fxpXFracHalf_uid46_fpCosPiTest_q, xout => ld_fxpXFracHalf_uid46_fpCosPiTest_q_to_InvFxpXFracHalf_uid100_fpCosPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--InvFxpXFracHalf_uid100_fpCosPiTest(LOGICAL,99)@3
InvFxpXFracHalf_uid100_fpCosPiTest_a <= ld_fxpXFracHalf_uid46_fpCosPiTest_q_to_InvFxpXFracHalf_uid100_fpCosPiTest_a_q;
InvFxpXFracHalf_uid100_fpCosPiTest_q <= not InvFxpXFracHalf_uid100_fpCosPiTest_a;
--signR_uid101_fpCosPiTest(LOGICAL,100)@3
signR_uid101_fpCosPiTest_a <= InvFxpXFracHalf_uid100_fpCosPiTest_q;
signR_uid101_fpCosPiTest_b <= signRComp_uid99_fpCosPiTest_q;
signR_uid101_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
signR_uid101_fpCosPiTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1' AND en = "1") THEN
signR_uid101_fpCosPiTest_q <= signR_uid101_fpCosPiTest_a and signR_uid101_fpCosPiTest_b;
END IF;
END PROCESS;
--ld_signR_uid101_fpCosPiTest_q_to_R_uid102_fpCosPiTest_c(DELAY,375)@4
ld_signR_uid101_fpCosPiTest_q_to_R_uid102_fpCosPiTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 13 )
PORT MAP ( xin => signR_uid101_fpCosPiTest_q, xout => ld_signR_uid101_fpCosPiTest_q_to_R_uid102_fpCosPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--cstBias_uid10_fpCosPiTest(CONSTANT,9)
cstBias_uid10_fpCosPiTest_q <= "01111111";
--cstAllOWE_uid8_fpCosPiTest(CONSTANT,7)
cstAllOWE_uid8_fpCosPiTest_q <= "11111111";
--pad_o_uid16_uid47_fpCosPiTest(BITJOIN,46)@1
pad_o_uid16_uid47_fpCosPiTest_q <= VCC_q & STD_LOGIC_VECTOR((35 downto 1 => GND_q(0)) & GND_q);
--reg_pad_o_uid16_uid47_fpCosPiTest_0_to_oMFxpXFrac_uid47_fpCosPiTest_0(REG,244)@1
reg_pad_o_uid16_uid47_fpCosPiTest_0_to_oMFxpXFrac_uid47_fpCosPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_o_uid16_uid47_fpCosPiTest_0_to_oMFxpXFrac_uid47_fpCosPiTest_0_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_o_uid16_uid47_fpCosPiTest_0_to_oMFxpXFrac_uid47_fpCosPiTest_0_q <= pad_o_uid16_uid47_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--oMFxpXFrac_uid47_fpCosPiTest(SUB,47)@2
oMFxpXFrac_uid47_fpCosPiTest_a <= STD_LOGIC_VECTOR("0" & reg_pad_o_uid16_uid47_fpCosPiTest_0_to_oMFxpXFrac_uid47_fpCosPiTest_0_q);
oMFxpXFrac_uid47_fpCosPiTest_b <= STD_LOGIC_VECTOR("00" & reg_fxpXFrac_uid43_fpCosPiTest_0_to_fxpXFracZero_uid45_fpCosPiTest_1_q);
oMFxpXFrac_uid47_fpCosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(oMFxpXFrac_uid47_fpCosPiTest_a) - UNSIGNED(oMFxpXFrac_uid47_fpCosPiTest_b));
oMFxpXFrac_uid47_fpCosPiTest_q <= oMFxpXFrac_uid47_fpCosPiTest_o(37 downto 0);
--oMFxpXFrac_uid49_fpCosPiTest(BITSELECT,48)@2
oMFxpXFrac_uid49_fpCosPiTest_in <= oMFxpXFrac_uid47_fpCosPiTest_q(35 downto 0);
oMFxpXFrac_uid49_fpCosPiTest_b <= oMFxpXFrac_uid49_fpCosPiTest_in(35 downto 0);
--ld_fxpXFrac_uid43_fpCosPiTest_b_to_rangeReducedFxPX_uid51_fpCosPiTest_c(DELAY,308)@1
ld_fxpXFrac_uid43_fpCosPiTest_b_to_rangeReducedFxPX_uid51_fpCosPiTest_c : dspba_delay
GENERIC MAP ( width => 36, depth => 1 )
PORT MAP ( xin => fxpXFrac_uid43_fpCosPiTest_b, xout => ld_fxpXFrac_uid43_fpCosPiTest_b_to_rangeReducedFxPX_uid51_fpCosPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--ld_FxpXFrac35_uid44_fpCosPiTest_b_to_rangeReducedFxPX_uid51_fpCosPiTest_b(DELAY,307)@1
ld_FxpXFrac35_uid44_fpCosPiTest_b_to_rangeReducedFxPX_uid51_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => FxpXFrac35_uid44_fpCosPiTest_b, xout => ld_FxpXFrac35_uid44_fpCosPiTest_b_to_rangeReducedFxPX_uid51_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--rangeReducedFxPX_uid51_fpCosPiTest(MUX,50)@2
rangeReducedFxPX_uid51_fpCosPiTest_s <= ld_FxpXFrac35_uid44_fpCosPiTest_b_to_rangeReducedFxPX_uid51_fpCosPiTest_b_q;
rangeReducedFxPX_uid51_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
rangeReducedFxPX_uid51_fpCosPiTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE rangeReducedFxPX_uid51_fpCosPiTest_s IS
WHEN "0" => rangeReducedFxPX_uid51_fpCosPiTest_q <= ld_fxpXFrac_uid43_fpCosPiTest_b_to_rangeReducedFxPX_uid51_fpCosPiTest_c_q;
WHEN "1" => rangeReducedFxPX_uid51_fpCosPiTest_q <= oMFxpXFrac_uid49_fpCosPiTest_b;
WHEN OTHERS => rangeReducedFxPX_uid51_fpCosPiTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--pad_half_uid17_uid52_fpCosPiTest(BITJOIN,51)@2
pad_half_uid17_uid52_fpCosPiTest_q <= VCC_q & STD_LOGIC_VECTOR((34 downto 1 => GND_q(0)) & GND_q);
--reg_pad_half_uid17_uid52_fpCosPiTest_0_to_z_halfMRRFxPXE_uid52_fpCosPiTest_0(REG,246)@2
reg_pad_half_uid17_uid52_fpCosPiTest_0_to_z_halfMRRFxPXE_uid52_fpCosPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_half_uid17_uid52_fpCosPiTest_0_to_z_halfMRRFxPXE_uid52_fpCosPiTest_0_q <= "000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_half_uid17_uid52_fpCosPiTest_0_to_z_halfMRRFxPXE_uid52_fpCosPiTest_0_q <= pad_half_uid17_uid52_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--z_halfMRRFxPXE_uid52_fpCosPiTest(SUB,52)@3
z_halfMRRFxPXE_uid52_fpCosPiTest_a <= STD_LOGIC_VECTOR("0" & reg_pad_half_uid17_uid52_fpCosPiTest_0_to_z_halfMRRFxPXE_uid52_fpCosPiTest_0_q);
z_halfMRRFxPXE_uid52_fpCosPiTest_b <= STD_LOGIC_VECTOR("0" & rangeReducedFxPX_uid51_fpCosPiTest_q);
z_halfMRRFxPXE_uid52_fpCosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(z_halfMRRFxPXE_uid52_fpCosPiTest_a) - UNSIGNED(z_halfMRRFxPXE_uid52_fpCosPiTest_b));
z_halfMRRFxPXE_uid52_fpCosPiTest_q <= z_halfMRRFxPXE_uid52_fpCosPiTest_o(36 downto 0);
--z_uid54_fpCosPiTest(BITSELECT,53)@3
z_uid54_fpCosPiTest_in <= z_halfMRRFxPXE_uid52_fpCosPiTest_q(34 downto 0);
z_uid54_fpCosPiTest_b <= z_uid54_fpCosPiTest_in(34 downto 0);
--zAddr_uid62_fpCosPiTest(BITSELECT,61)@3
zAddr_uid62_fpCosPiTest_in <= z_uid54_fpCosPiTest_b;
zAddr_uid62_fpCosPiTest_b <= zAddr_uid62_fpCosPiTest_in(34 downto 28);
--reg_zAddr_uid62_fpCosPiTest_0_to_memoryC2_uid209_sinPiZTableGenerator_0(REG,263)@3
reg_zAddr_uid62_fpCosPiTest_0_to_memoryC2_uid209_sinPiZTableGenerator_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_zAddr_uid62_fpCosPiTest_0_to_memoryC2_uid209_sinPiZTableGenerator_0_q <= "0000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_zAddr_uid62_fpCosPiTest_0_to_memoryC2_uid209_sinPiZTableGenerator_0_q <= zAddr_uid62_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--memoryC2_uid209_sinPiZTableGenerator(LOOKUP,208)@4
memoryC2_uid209_sinPiZTableGenerator: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
memoryC2_uid209_sinPiZTableGenerator_q <= "10101101010011";
ELSIF (clk'EVENT AND clk = '1' AND en = "1") THEN
CASE (reg_zAddr_uid62_fpCosPiTest_0_to_memoryC2_uid209_sinPiZTableGenerator_0_q) IS
WHEN "0000000" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101101010011";
WHEN "0000001" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101101010100";
WHEN "0000010" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101101010111";
WHEN "0000011" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101101011001";
WHEN "0000100" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101101011011";
WHEN "0000101" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101101011100";
WHEN "0000110" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101101011111";
WHEN "0000111" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101101100010";
WHEN "0001000" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101101100110";
WHEN "0001001" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101101101011";
WHEN "0001010" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101101110000";
WHEN "0001011" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101101110101";
WHEN "0001100" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101101111011";
WHEN "0001101" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101110000000";
WHEN "0001110" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101110000111";
WHEN "0001111" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101110001110";
WHEN "0010000" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101110010011";
WHEN "0010001" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101110011110";
WHEN "0010010" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101110100110";
WHEN "0010011" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101110101111";
WHEN "0010100" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101110111000";
WHEN "0010101" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101111000011";
WHEN "0010110" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101111001100";
WHEN "0010111" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101111010111";
WHEN "0011000" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101111100011";
WHEN "0011001" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101111101110";
WHEN "0011010" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101111111011";
WHEN "0011011" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110000001001";
WHEN "0011100" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110000010101";
WHEN "0011101" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110000100000";
WHEN "0011110" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110000110001";
WHEN "0011111" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110001000000";
WHEN "0100000" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110001001101";
WHEN "0100001" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110001011110";
WHEN "0100010" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110001101100";
WHEN "0100011" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110001111111";
WHEN "0100100" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110010001111";
WHEN "0100101" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110010100001";
WHEN "0100110" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110010110011";
WHEN "0100111" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110011000101";
WHEN "0101000" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110011010110";
WHEN "0101001" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110011101011";
WHEN "0101010" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110011111111";
WHEN "0101011" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110100010010";
WHEN "0101100" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110100100101";
WHEN "0101101" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110100111011";
WHEN "0101110" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110101001110";
WHEN "0101111" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110101100111";
WHEN "0110000" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110101111100";
WHEN "0110001" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110110010010";
WHEN "0110010" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110110100110";
WHEN "0110011" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110111000000";
WHEN "0110100" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110111010101";
WHEN "0110101" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110111110000";
WHEN "0110110" => memoryC2_uid209_sinPiZTableGenerator_q <= "10111000000110";
WHEN "0110111" => memoryC2_uid209_sinPiZTableGenerator_q <= "10111000100010";
WHEN "0111000" => memoryC2_uid209_sinPiZTableGenerator_q <= "10111000111001";
WHEN "0111001" => memoryC2_uid209_sinPiZTableGenerator_q <= "10111001010100";
WHEN "0111010" => memoryC2_uid209_sinPiZTableGenerator_q <= "10111001101111";
WHEN "0111011" => memoryC2_uid209_sinPiZTableGenerator_q <= "10111010001001";
WHEN "0111100" => memoryC2_uid209_sinPiZTableGenerator_q <= "10111010100011";
WHEN "0111101" => memoryC2_uid209_sinPiZTableGenerator_q <= "10111010111100";
WHEN "0111110" => memoryC2_uid209_sinPiZTableGenerator_q <= "10111011011001";
WHEN "0111111" => memoryC2_uid209_sinPiZTableGenerator_q <= "10111011110111";
WHEN "1000000" => memoryC2_uid209_sinPiZTableGenerator_q <= "10111100010100";
WHEN "1000001" => memoryC2_uid209_sinPiZTableGenerator_q <= "10111100110001";
WHEN "1000010" => memoryC2_uid209_sinPiZTableGenerator_q <= "10111101001101";
WHEN "1000011" => memoryC2_uid209_sinPiZTableGenerator_q <= "10111101101010";
WHEN "1000100" => memoryC2_uid209_sinPiZTableGenerator_q <= "10111110001000";
WHEN "1000101" => memoryC2_uid209_sinPiZTableGenerator_q <= "10111110100101";
WHEN "1000110" => memoryC2_uid209_sinPiZTableGenerator_q <= "10111111000101";
WHEN "1000111" => memoryC2_uid209_sinPiZTableGenerator_q <= "10111111100011";
WHEN "1001000" => memoryC2_uid209_sinPiZTableGenerator_q <= "11000000000011";
WHEN "1001001" => memoryC2_uid209_sinPiZTableGenerator_q <= "11000000100011";
WHEN "1001010" => memoryC2_uid209_sinPiZTableGenerator_q <= "11000001000100";
WHEN "1001011" => memoryC2_uid209_sinPiZTableGenerator_q <= "11000001100010";
WHEN "1001100" => memoryC2_uid209_sinPiZTableGenerator_q <= "11000010000100";
WHEN "1001101" => memoryC2_uid209_sinPiZTableGenerator_q <= "11000010100010";
WHEN "1001110" => memoryC2_uid209_sinPiZTableGenerator_q <= "11000011000110";
WHEN "1001111" => memoryC2_uid209_sinPiZTableGenerator_q <= "11000011101000";
WHEN "1010000" => memoryC2_uid209_sinPiZTableGenerator_q <= "11000100001010";
WHEN "1010001" => memoryC2_uid209_sinPiZTableGenerator_q <= "11000100101101";
WHEN "1010010" => memoryC2_uid209_sinPiZTableGenerator_q <= "11000101010001";
WHEN "1010011" => memoryC2_uid209_sinPiZTableGenerator_q <= "11000101110010";
WHEN "1010100" => memoryC2_uid209_sinPiZTableGenerator_q <= "11000110010100";
WHEN "1010101" => memoryC2_uid209_sinPiZTableGenerator_q <= "11000110111011";
WHEN "1010110" => memoryC2_uid209_sinPiZTableGenerator_q <= "11000111011010";
WHEN "1010111" => memoryC2_uid209_sinPiZTableGenerator_q <= "11001000000001";
WHEN "1011000" => memoryC2_uid209_sinPiZTableGenerator_q <= "11001000100110";
WHEN "1011001" => memoryC2_uid209_sinPiZTableGenerator_q <= "11001001001011";
WHEN "1011010" => memoryC2_uid209_sinPiZTableGenerator_q <= "11001001101101";
WHEN "1011011" => memoryC2_uid209_sinPiZTableGenerator_q <= "11001010010101";
WHEN "1011100" => memoryC2_uid209_sinPiZTableGenerator_q <= "11001010111100";
WHEN "1011101" => memoryC2_uid209_sinPiZTableGenerator_q <= "11001011100000";
WHEN "1011110" => memoryC2_uid209_sinPiZTableGenerator_q <= "11001100000101";
WHEN "1011111" => memoryC2_uid209_sinPiZTableGenerator_q <= "11001100101110";
WHEN "1100000" => memoryC2_uid209_sinPiZTableGenerator_q <= "11001101010100";
WHEN "1100001" => memoryC2_uid209_sinPiZTableGenerator_q <= "11001101111010";
WHEN "1100010" => memoryC2_uid209_sinPiZTableGenerator_q <= "11001110100010";
WHEN "1100011" => memoryC2_uid209_sinPiZTableGenerator_q <= "11001111001001";
WHEN "1100100" => memoryC2_uid209_sinPiZTableGenerator_q <= "11001111110001";
WHEN "1100101" => memoryC2_uid209_sinPiZTableGenerator_q <= "11010000010110";
WHEN "1100110" => memoryC2_uid209_sinPiZTableGenerator_q <= "11010000111111";
WHEN "1100111" => memoryC2_uid209_sinPiZTableGenerator_q <= "11010001101001";
WHEN "1101000" => memoryC2_uid209_sinPiZTableGenerator_q <= "11010010010010";
WHEN "1101001" => memoryC2_uid209_sinPiZTableGenerator_q <= "11010010111101";
WHEN "1101010" => memoryC2_uid209_sinPiZTableGenerator_q <= "11010011100001";
WHEN "1101011" => memoryC2_uid209_sinPiZTableGenerator_q <= "11010100001100";
WHEN "1101100" => memoryC2_uid209_sinPiZTableGenerator_q <= "11010100110111";
WHEN "1101101" => memoryC2_uid209_sinPiZTableGenerator_q <= "11010101100001";
WHEN "1101110" => memoryC2_uid209_sinPiZTableGenerator_q <= "11010110001011";
WHEN "1101111" => memoryC2_uid209_sinPiZTableGenerator_q <= "11010110110011";
WHEN "1110000" => memoryC2_uid209_sinPiZTableGenerator_q <= "11010111011111";
WHEN "1110001" => memoryC2_uid209_sinPiZTableGenerator_q <= "11011000001010";
WHEN "1110010" => memoryC2_uid209_sinPiZTableGenerator_q <= "11011000110100";
WHEN "1110011" => memoryC2_uid209_sinPiZTableGenerator_q <= "11011001011111";
WHEN "1110100" => memoryC2_uid209_sinPiZTableGenerator_q <= "11011010001010";
WHEN "1110101" => memoryC2_uid209_sinPiZTableGenerator_q <= "11011010110110";
WHEN "1110110" => memoryC2_uid209_sinPiZTableGenerator_q <= "11011011100011";
WHEN "1110111" => memoryC2_uid209_sinPiZTableGenerator_q <= "11011100001111";
WHEN "1111000" => memoryC2_uid209_sinPiZTableGenerator_q <= "11011100111001";
WHEN "1111001" => memoryC2_uid209_sinPiZTableGenerator_q <= "11011101100011";
WHEN "1111010" => memoryC2_uid209_sinPiZTableGenerator_q <= "11011110010001";
WHEN "1111011" => memoryC2_uid209_sinPiZTableGenerator_q <= "11011110111011";
WHEN "1111100" => memoryC2_uid209_sinPiZTableGenerator_q <= "11011111101000";
WHEN "1111101" => memoryC2_uid209_sinPiZTableGenerator_q <= "11100000010101";
WHEN "1111110" => memoryC2_uid209_sinPiZTableGenerator_q <= "11100001000010";
WHEN "1111111" => memoryC2_uid209_sinPiZTableGenerator_q <= "11100001110000";
WHEN OTHERS =>
memoryC2_uid209_sinPiZTableGenerator_q <= (others => '-');
END CASE;
END IF;
END PROCESS;
--zPPolyEval_uid63_fpCosPiTest(BITSELECT,62)@3
zPPolyEval_uid63_fpCosPiTest_in <= z_uid54_fpCosPiTest_b(27 downto 0);
zPPolyEval_uid63_fpCosPiTest_b <= zPPolyEval_uid63_fpCosPiTest_in(27 downto 12);
--yT1_uid210_sinPiZPolyEval(BITSELECT,209)@3
yT1_uid210_sinPiZPolyEval_in <= zPPolyEval_uid63_fpCosPiTest_b;
yT1_uid210_sinPiZPolyEval_b <= yT1_uid210_sinPiZPolyEval_in(15 downto 2);
--reg_yT1_uid210_sinPiZPolyEval_0_to_prodXY_uid226_pT1_uid211_sinPiZPolyEval_0(REG,264)@3
reg_yT1_uid210_sinPiZPolyEval_0_to_prodXY_uid226_pT1_uid211_sinPiZPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT1_uid210_sinPiZPolyEval_0_to_prodXY_uid226_pT1_uid211_sinPiZPolyEval_0_q <= "00000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT1_uid210_sinPiZPolyEval_0_to_prodXY_uid226_pT1_uid211_sinPiZPolyEval_0_q <= yT1_uid210_sinPiZPolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_reg_yT1_uid210_sinPiZPolyEval_0_to_prodXY_uid226_pT1_uid211_sinPiZPolyEval_0_q_to_prodXY_uid226_pT1_uid211_sinPiZPolyEval_a(DELAY,499)@4
ld_reg_yT1_uid210_sinPiZPolyEval_0_to_prodXY_uid226_pT1_uid211_sinPiZPolyEval_0_q_to_prodXY_uid226_pT1_uid211_sinPiZPolyEval_a : dspba_delay
GENERIC MAP ( width => 14, depth => 1 )
PORT MAP ( xin => reg_yT1_uid210_sinPiZPolyEval_0_to_prodXY_uid226_pT1_uid211_sinPiZPolyEval_0_q, xout => ld_reg_yT1_uid210_sinPiZPolyEval_0_to_prodXY_uid226_pT1_uid211_sinPiZPolyEval_0_q_to_prodXY_uid226_pT1_uid211_sinPiZPolyEval_a_q, ena => en(0), clk => clk, aclr => areset );
--prodXY_uid226_pT1_uid211_sinPiZPolyEval(MULT,225)@5
prodXY_uid226_pT1_uid211_sinPiZPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid226_pT1_uid211_sinPiZPolyEval_a),15)) * SIGNED(prodXY_uid226_pT1_uid211_sinPiZPolyEval_b);
prodXY_uid226_pT1_uid211_sinPiZPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid226_pT1_uid211_sinPiZPolyEval_a <= (others => '0');
prodXY_uid226_pT1_uid211_sinPiZPolyEval_b <= (others => '0');
prodXY_uid226_pT1_uid211_sinPiZPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid226_pT1_uid211_sinPiZPolyEval_a <= ld_reg_yT1_uid210_sinPiZPolyEval_0_to_prodXY_uid226_pT1_uid211_sinPiZPolyEval_0_q_to_prodXY_uid226_pT1_uid211_sinPiZPolyEval_a_q;
prodXY_uid226_pT1_uid211_sinPiZPolyEval_b <= memoryC2_uid209_sinPiZTableGenerator_q;
prodXY_uid226_pT1_uid211_sinPiZPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid226_pT1_uid211_sinPiZPolyEval_pr,28));
END IF;
END IF;
END PROCESS;
prodXY_uid226_pT1_uid211_sinPiZPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid226_pT1_uid211_sinPiZPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid226_pT1_uid211_sinPiZPolyEval_q <= prodXY_uid226_pT1_uid211_sinPiZPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid227_pT1_uid211_sinPiZPolyEval(BITSELECT,226)@8
prodXYTruncFR_uid227_pT1_uid211_sinPiZPolyEval_in <= prodXY_uid226_pT1_uid211_sinPiZPolyEval_q;
prodXYTruncFR_uid227_pT1_uid211_sinPiZPolyEval_b <= prodXYTruncFR_uid227_pT1_uid211_sinPiZPolyEval_in(27 downto 13);
--highBBits_uid213_sinPiZPolyEval(BITSELECT,212)@8
highBBits_uid213_sinPiZPolyEval_in <= prodXYTruncFR_uid227_pT1_uid211_sinPiZPolyEval_b;
highBBits_uid213_sinPiZPolyEval_b <= highBBits_uid213_sinPiZPolyEval_in(14 downto 1);
--ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_notEnable(LOGICAL,557)
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_notEnable_a <= en;
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_notEnable_q <= not ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_notEnable_a;
--ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_nor(LOGICAL,596)
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_nor_a <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_notEnable_q;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_nor_b <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_sticky_ena_q;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_nor_q <= not (ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_nor_a or ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_nor_b);
--ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_mem_top(CONSTANT,592)
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_mem_top_q <= "010";
--ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_cmp(LOGICAL,593)
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_cmp_a <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_mem_top_q;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdmux_q);
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_cmp_q <= "1" when ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_cmp_a = ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_cmp_b else "0";
--ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_cmpReg(REG,594)
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_cmpReg_q <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_sticky_ena(REG,597)
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_nor_q = "1") THEN
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_sticky_ena_q <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_enaAnd(LOGICAL,598)
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_enaAnd_a <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_sticky_ena_q;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_enaAnd_b <= en;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_enaAnd_q <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_enaAnd_a and ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_enaAnd_b;
--ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt(COUNTER,588)
-- every=1, low=0, high=2, step=1, init=1
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt_i <= TO_UNSIGNED(1,2);
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt_i = 1 THEN
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt_eq = '1') THEN
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt_i <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt_i - 2;
ELSE
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt_i <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt_i,2));
--ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdreg(REG,589)
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdreg_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdreg_q <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdmux(MUX,590)
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdmux_s <= en;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdmux: PROCESS (ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdmux_s, ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdreg_q, ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdmux_s IS
WHEN "0" => ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdmux_q <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdreg_q;
WHEN "1" => ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdmux_q <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem(DUALMEM,587)
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_reset0 <= areset;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_ia <= reg_zAddr_uid62_fpCosPiTest_0_to_memoryC2_uid209_sinPiZTableGenerator_0_q;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_aa <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdreg_q;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_ab <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdmux_q;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 7,
widthad_a => 2,
numwords_a => 3,
width_b => 7,
widthad_b => 2,
numwords_b => 3,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_iq,
address_a => ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_aa,
data_a => ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_ia
);
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_q <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_iq(6 downto 0);
--memoryC1_uid208_sinPiZTableGenerator(LOOKUP,207)@8
memoryC1_uid208_sinPiZTableGenerator: PROCESS (ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_q)
BEGIN
-- Begin reserved scope level
CASE (ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_q) IS
WHEN "0000000" => memoryC1_uid208_sinPiZTableGenerator_q <= "000000000000000000001";
WHEN "0000001" => memoryC1_uid208_sinPiZTableGenerator_q <= "111111101011010101010";
WHEN "0000010" => memoryC1_uid208_sinPiZTableGenerator_q <= "111111010110101010001";
WHEN "0000011" => memoryC1_uid208_sinPiZTableGenerator_q <= "111111000001111111100";
WHEN "0000100" => memoryC1_uid208_sinPiZTableGenerator_q <= "111110101101010101010";
WHEN "0000101" => memoryC1_uid208_sinPiZTableGenerator_q <= "111110011000101011101";
WHEN "0000110" => memoryC1_uid208_sinPiZTableGenerator_q <= "111110000100000010101";
WHEN "0000111" => memoryC1_uid208_sinPiZTableGenerator_q <= "111101101111011010001";
WHEN "0001000" => memoryC1_uid208_sinPiZTableGenerator_q <= "111101011010110010101";
WHEN "0001001" => memoryC1_uid208_sinPiZTableGenerator_q <= "111101000110001011111";
WHEN "0001010" => memoryC1_uid208_sinPiZTableGenerator_q <= "111100110001100110010";
WHEN "0001011" => memoryC1_uid208_sinPiZTableGenerator_q <= "111100011101000010000";
WHEN "0001100" => memoryC1_uid208_sinPiZTableGenerator_q <= "111100001000011110111";
WHEN "0001101" => memoryC1_uid208_sinPiZTableGenerator_q <= "111011110011111101011";
WHEN "0001110" => memoryC1_uid208_sinPiZTableGenerator_q <= "111011011111011101011";
WHEN "0001111" => memoryC1_uid208_sinPiZTableGenerator_q <= "111011001010111110111";
WHEN "0010000" => memoryC1_uid208_sinPiZTableGenerator_q <= "111010110110100010101";
WHEN "0010001" => memoryC1_uid208_sinPiZTableGenerator_q <= "111010100010000111100";
WHEN "0010010" => memoryC1_uid208_sinPiZTableGenerator_q <= "111010001101101111000";
WHEN "0010011" => memoryC1_uid208_sinPiZTableGenerator_q <= "111001111001011000011";
WHEN "0010100" => memoryC1_uid208_sinPiZTableGenerator_q <= "111001100101000100010";
WHEN "0010101" => memoryC1_uid208_sinPiZTableGenerator_q <= "111001010000110010001";
WHEN "0010110" => memoryC1_uid208_sinPiZTableGenerator_q <= "111000111100100010111";
WHEN "0010111" => memoryC1_uid208_sinPiZTableGenerator_q <= "111000101000010110001";
WHEN "0011000" => memoryC1_uid208_sinPiZTableGenerator_q <= "111000010100001011111";
WHEN "0011001" => memoryC1_uid208_sinPiZTableGenerator_q <= "111000000000000100110";
WHEN "0011010" => memoryC1_uid208_sinPiZTableGenerator_q <= "110111101100000000011";
WHEN "0011011" => memoryC1_uid208_sinPiZTableGenerator_q <= "110111010111111111000";
WHEN "0011100" => memoryC1_uid208_sinPiZTableGenerator_q <= "110111000100000001000";
WHEN "0011101" => memoryC1_uid208_sinPiZTableGenerator_q <= "110110110000000110101";
WHEN "0011110" => memoryC1_uid208_sinPiZTableGenerator_q <= "110110011100001110111";
WHEN "0011111" => memoryC1_uid208_sinPiZTableGenerator_q <= "110110001000011011000";
WHEN "0100000" => memoryC1_uid208_sinPiZTableGenerator_q <= "110101110100101011010";
WHEN "0100001" => memoryC1_uid208_sinPiZTableGenerator_q <= "110101100000111110101";
WHEN "0100010" => memoryC1_uid208_sinPiZTableGenerator_q <= "110101001101010110010";
WHEN "0100011" => memoryC1_uid208_sinPiZTableGenerator_q <= "110100111001110001011";
WHEN "0100100" => memoryC1_uid208_sinPiZTableGenerator_q <= "110100100110010001001";
WHEN "0100101" => memoryC1_uid208_sinPiZTableGenerator_q <= "110100010010110100110";
WHEN "0100110" => memoryC1_uid208_sinPiZTableGenerator_q <= "110011111111011100110";
WHEN "0100111" => memoryC1_uid208_sinPiZTableGenerator_q <= "110011101100001001010";
WHEN "0101000" => memoryC1_uid208_sinPiZTableGenerator_q <= "110011011000111010011";
WHEN "0101001" => memoryC1_uid208_sinPiZTableGenerator_q <= "110011000101101111111";
WHEN "0101010" => memoryC1_uid208_sinPiZTableGenerator_q <= "110010110010101010010";
WHEN "0101011" => memoryC1_uid208_sinPiZTableGenerator_q <= "110010011111101001101";
WHEN "0101100" => memoryC1_uid208_sinPiZTableGenerator_q <= "110010001100101110000";
WHEN "0101101" => memoryC1_uid208_sinPiZTableGenerator_q <= "110001111001110111001";
WHEN "0101110" => memoryC1_uid208_sinPiZTableGenerator_q <= "110001100111000110000";
WHEN "0101111" => memoryC1_uid208_sinPiZTableGenerator_q <= "110001010100011001011";
WHEN "0110000" => memoryC1_uid208_sinPiZTableGenerator_q <= "110001000001110010110";
WHEN "0110001" => memoryC1_uid208_sinPiZTableGenerator_q <= "110000101111010001100";
WHEN "0110010" => memoryC1_uid208_sinPiZTableGenerator_q <= "110000011100110110001";
WHEN "0110011" => memoryC1_uid208_sinPiZTableGenerator_q <= "110000001010011111111";
WHEN "0110100" => memoryC1_uid208_sinPiZTableGenerator_q <= "101111111000010000000";
WHEN "0110101" => memoryC1_uid208_sinPiZTableGenerator_q <= "101111100110000101100";
WHEN "0110110" => memoryC1_uid208_sinPiZTableGenerator_q <= "101111010100000001100";
WHEN "0110111" => memoryC1_uid208_sinPiZTableGenerator_q <= "101111000010000011001";
WHEN "0111000" => memoryC1_uid208_sinPiZTableGenerator_q <= "101110110000001011100";
WHEN "0111001" => memoryC1_uid208_sinPiZTableGenerator_q <= "101110011110011001110";
WHEN "0111010" => memoryC1_uid208_sinPiZTableGenerator_q <= "101110001100101110101";
WHEN "0111011" => memoryC1_uid208_sinPiZTableGenerator_q <= "101101111011001010001";
WHEN "0111100" => memoryC1_uid208_sinPiZTableGenerator_q <= "101101101001101100010";
WHEN "0111101" => memoryC1_uid208_sinPiZTableGenerator_q <= "101101011000010101010";
WHEN "0111110" => memoryC1_uid208_sinPiZTableGenerator_q <= "101101000111000100101";
WHEN "0111111" => memoryC1_uid208_sinPiZTableGenerator_q <= "101100110101111010111";
WHEN "1000000" => memoryC1_uid208_sinPiZTableGenerator_q <= "101100100100111000010";
WHEN "1000001" => memoryC1_uid208_sinPiZTableGenerator_q <= "101100010011111100111";
WHEN "1000010" => memoryC1_uid208_sinPiZTableGenerator_q <= "101100000011001000111";
WHEN "1000011" => memoryC1_uid208_sinPiZTableGenerator_q <= "101011110010011100000";
WHEN "1000100" => memoryC1_uid208_sinPiZTableGenerator_q <= "101011100001110110100";
WHEN "1000101" => memoryC1_uid208_sinPiZTableGenerator_q <= "101011010001011000100";
WHEN "1000110" => memoryC1_uid208_sinPiZTableGenerator_q <= "101011000001000001110";
WHEN "1000111" => memoryC1_uid208_sinPiZTableGenerator_q <= "101010110000110011000";
WHEN "1001000" => memoryC1_uid208_sinPiZTableGenerator_q <= "101010100000101011111";
WHEN "1001001" => memoryC1_uid208_sinPiZTableGenerator_q <= "101010010000101100100";
WHEN "1001010" => memoryC1_uid208_sinPiZTableGenerator_q <= "101010000000110101001";
WHEN "1001011" => memoryC1_uid208_sinPiZTableGenerator_q <= "101001110001000110000";
WHEN "1001100" => memoryC1_uid208_sinPiZTableGenerator_q <= "101001100001011110101";
WHEN "1001101" => memoryC1_uid208_sinPiZTableGenerator_q <= "101001010001111111111";
WHEN "1001110" => memoryC1_uid208_sinPiZTableGenerator_q <= "101001000010101000110";
WHEN "1001111" => memoryC1_uid208_sinPiZTableGenerator_q <= "101000110011011010001";
WHEN "1010000" => memoryC1_uid208_sinPiZTableGenerator_q <= "101000100100010100001";
WHEN "1010001" => memoryC1_uid208_sinPiZTableGenerator_q <= "101000010101010110100";
WHEN "1010010" => memoryC1_uid208_sinPiZTableGenerator_q <= "101000000110100001011";
WHEN "1010011" => memoryC1_uid208_sinPiZTableGenerator_q <= "100111110111110101011";
WHEN "1010100" => memoryC1_uid208_sinPiZTableGenerator_q <= "100111101001010010000";
WHEN "1010101" => memoryC1_uid208_sinPiZTableGenerator_q <= "100111011010110110110";
WHEN "1010110" => memoryC1_uid208_sinPiZTableGenerator_q <= "100111001100100101100";
WHEN "1010111" => memoryC1_uid208_sinPiZTableGenerator_q <= "100110111110011100011";
WHEN "1011000" => memoryC1_uid208_sinPiZTableGenerator_q <= "100110110000011100011";
WHEN "1011001" => memoryC1_uid208_sinPiZTableGenerator_q <= "100110100010100101110";
WHEN "1011010" => memoryC1_uid208_sinPiZTableGenerator_q <= "100110010100111000101";
WHEN "1011011" => memoryC1_uid208_sinPiZTableGenerator_q <= "100110000111010100001";
WHEN "1011100" => memoryC1_uid208_sinPiZTableGenerator_q <= "100101111001111001000";
WHEN "1011101" => memoryC1_uid208_sinPiZTableGenerator_q <= "100101101100100111111";
WHEN "1011110" => memoryC1_uid208_sinPiZTableGenerator_q <= "100101011111100000000";
WHEN "1011111" => memoryC1_uid208_sinPiZTableGenerator_q <= "100101010010100001001";
WHEN "1100000" => memoryC1_uid208_sinPiZTableGenerator_q <= "100101000101101100011";
WHEN "1100001" => memoryC1_uid208_sinPiZTableGenerator_q <= "100100111001000001011";
WHEN "1100010" => memoryC1_uid208_sinPiZTableGenerator_q <= "100100101100011111111";
WHEN "1100011" => memoryC1_uid208_sinPiZTableGenerator_q <= "100100100000001000010";
WHEN "1100100" => memoryC1_uid208_sinPiZTableGenerator_q <= "100100010011111010101";
WHEN "1100101" => memoryC1_uid208_sinPiZTableGenerator_q <= "100100000111110111001";
WHEN "1100110" => memoryC1_uid208_sinPiZTableGenerator_q <= "100011111011111101010";
WHEN "1100111" => memoryC1_uid208_sinPiZTableGenerator_q <= "100011110000001101010";
WHEN "1101000" => memoryC1_uid208_sinPiZTableGenerator_q <= "100011100100100111101";
WHEN "1101001" => memoryC1_uid208_sinPiZTableGenerator_q <= "100011011001001011111";
WHEN "1101010" => memoryC1_uid208_sinPiZTableGenerator_q <= "100011001101111011010";
WHEN "1101011" => memoryC1_uid208_sinPiZTableGenerator_q <= "100011000010110100001";
WHEN "1101100" => memoryC1_uid208_sinPiZTableGenerator_q <= "100010110111110111010";
WHEN "1101101" => memoryC1_uid208_sinPiZTableGenerator_q <= "100010101101000101000";
WHEN "1101110" => memoryC1_uid208_sinPiZTableGenerator_q <= "100010100010011101001";
WHEN "1101111" => memoryC1_uid208_sinPiZTableGenerator_q <= "100010011000000000001";
WHEN "1110000" => memoryC1_uid208_sinPiZTableGenerator_q <= "100010001101101101010";
WHEN "1110001" => memoryC1_uid208_sinPiZTableGenerator_q <= "100010000011100100111";
WHEN "1110010" => memoryC1_uid208_sinPiZTableGenerator_q <= "100001111001100111100";
WHEN "1110011" => memoryC1_uid208_sinPiZTableGenerator_q <= "100001101111110100101";
WHEN "1110100" => memoryC1_uid208_sinPiZTableGenerator_q <= "100001100110001100100";
WHEN "1110101" => memoryC1_uid208_sinPiZTableGenerator_q <= "100001011100101111001";
WHEN "1110110" => memoryC1_uid208_sinPiZTableGenerator_q <= "100001010011011100011";
WHEN "1110111" => memoryC1_uid208_sinPiZTableGenerator_q <= "100001001010010100101";
WHEN "1111000" => memoryC1_uid208_sinPiZTableGenerator_q <= "100001000001011000000";
WHEN "1111001" => memoryC1_uid208_sinPiZTableGenerator_q <= "100000111000100110100";
WHEN "1111010" => memoryC1_uid208_sinPiZTableGenerator_q <= "100000101111111111100";
WHEN "1111011" => memoryC1_uid208_sinPiZTableGenerator_q <= "100000100111100011111";
WHEN "1111100" => memoryC1_uid208_sinPiZTableGenerator_q <= "100000011111010011000";
WHEN "1111101" => memoryC1_uid208_sinPiZTableGenerator_q <= "100000010111001101010";
WHEN "1111110" => memoryC1_uid208_sinPiZTableGenerator_q <= "100000001111010010101";
WHEN "1111111" => memoryC1_uid208_sinPiZTableGenerator_q <= "100000000111100011001";
WHEN OTHERS =>
memoryC1_uid208_sinPiZTableGenerator_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--sumAHighB_uid214_sinPiZPolyEval(ADD,213)@8
sumAHighB_uid214_sinPiZPolyEval_a <= STD_LOGIC_VECTOR((21 downto 21 => memoryC1_uid208_sinPiZTableGenerator_q(20)) & memoryC1_uid208_sinPiZTableGenerator_q);
sumAHighB_uid214_sinPiZPolyEval_b <= STD_LOGIC_VECTOR((21 downto 14 => highBBits_uid213_sinPiZPolyEval_b(13)) & highBBits_uid213_sinPiZPolyEval_b);
sumAHighB_uid214_sinPiZPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid214_sinPiZPolyEval_a) + SIGNED(sumAHighB_uid214_sinPiZPolyEval_b));
sumAHighB_uid214_sinPiZPolyEval_q <= sumAHighB_uid214_sinPiZPolyEval_o(21 downto 0);
--lowRangeB_uid212_sinPiZPolyEval(BITSELECT,211)@8
lowRangeB_uid212_sinPiZPolyEval_in <= prodXYTruncFR_uid227_pT1_uid211_sinPiZPolyEval_b(0 downto 0);
lowRangeB_uid212_sinPiZPolyEval_b <= lowRangeB_uid212_sinPiZPolyEval_in(0 downto 0);
--s1_uid212_uid215_sinPiZPolyEval(BITJOIN,214)@8
s1_uid212_uid215_sinPiZPolyEval_q <= sumAHighB_uid214_sinPiZPolyEval_q & lowRangeB_uid212_sinPiZPolyEval_b;
--reg_s1_uid212_uid215_sinPiZPolyEval_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_1(REG,267)@8
reg_s1_uid212_uid215_sinPiZPolyEval_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_s1_uid212_uid215_sinPiZPolyEval_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_1_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_s1_uid212_uid215_sinPiZPolyEval_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_1_q <= s1_uid212_uid215_sinPiZPolyEval_q;
END IF;
END IF;
END PROCESS;
--ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_nor(LOGICAL,609)
ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_nor_a <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_notEnable_q;
ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_nor_b <= ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_sticky_ena_q;
ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_nor_q <= not (ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_nor_a or ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_nor_b);
--ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_sticky_ena(REG,610)
ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_nor_q = "1") THEN
ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_sticky_ena_q <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_enaAnd(LOGICAL,611)
ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_enaAnd_a <= ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_sticky_ena_q;
ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_enaAnd_b <= en;
ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_enaAnd_q <= ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_enaAnd_a and ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_enaAnd_b;
--ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_inputreg(DELAY,599)
ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 16, depth => 1 )
PORT MAP ( xin => zPPolyEval_uid63_fpCosPiTest_b, xout => ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem(DUALMEM,600)
ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_reset0 <= areset;
ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_ia <= ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_inputreg_q;
ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_aa <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdreg_q;
ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_ab <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdmux_q;
ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 16,
widthad_a => 2,
numwords_a => 3,
width_b => 16,
widthad_b => 2,
numwords_b => 3,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_iq,
address_a => ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_aa,
data_a => ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_ia
);
ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_q <= ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_iq(15 downto 0);
--reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0(REG,266)@8
reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_q <= ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--prodXY_uid229_pT2_uid217_sinPiZPolyEval(MULT,228)@9
prodXY_uid229_pT2_uid217_sinPiZPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid229_pT2_uid217_sinPiZPolyEval_a),17)) * SIGNED(prodXY_uid229_pT2_uid217_sinPiZPolyEval_b);
prodXY_uid229_pT2_uid217_sinPiZPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid229_pT2_uid217_sinPiZPolyEval_a <= (others => '0');
prodXY_uid229_pT2_uid217_sinPiZPolyEval_b <= (others => '0');
prodXY_uid229_pT2_uid217_sinPiZPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid229_pT2_uid217_sinPiZPolyEval_a <= reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_q;
prodXY_uid229_pT2_uid217_sinPiZPolyEval_b <= reg_s1_uid212_uid215_sinPiZPolyEval_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_1_q;
prodXY_uid229_pT2_uid217_sinPiZPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid229_pT2_uid217_sinPiZPolyEval_pr,39));
END IF;
END IF;
END PROCESS;
prodXY_uid229_pT2_uid217_sinPiZPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid229_pT2_uid217_sinPiZPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid229_pT2_uid217_sinPiZPolyEval_q <= prodXY_uid229_pT2_uid217_sinPiZPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid230_pT2_uid217_sinPiZPolyEval(BITSELECT,229)@12
prodXYTruncFR_uid230_pT2_uid217_sinPiZPolyEval_in <= prodXY_uid229_pT2_uid217_sinPiZPolyEval_q;
prodXYTruncFR_uid230_pT2_uid217_sinPiZPolyEval_b <= prodXYTruncFR_uid230_pT2_uid217_sinPiZPolyEval_in(38 downto 15);
--highBBits_uid219_sinPiZPolyEval(BITSELECT,218)@12
highBBits_uid219_sinPiZPolyEval_in <= prodXYTruncFR_uid230_pT2_uid217_sinPiZPolyEval_b;
highBBits_uid219_sinPiZPolyEval_b <= highBBits_uid219_sinPiZPolyEval_in(23 downto 2);
--ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_nor(LOGICAL,584)
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_nor_a <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_notEnable_q;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_nor_b <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_sticky_ena_q;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_nor_q <= not (ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_nor_a or ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_nor_b);
--ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_mem_top(CONSTANT,554)
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_mem_top_q <= "0110";
--ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_cmp(LOGICAL,555)
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_cmp_a <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_mem_top_q;
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdmux_q);
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_cmp_q <= "1" when ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_cmp_a = ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_cmp_b else "0";
--ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_cmpReg(REG,556)
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_cmpReg_q <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_sticky_ena(REG,585)
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_nor_q = "1") THEN
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_sticky_ena_q <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_enaAnd(LOGICAL,586)
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_enaAnd_a <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_sticky_ena_q;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_enaAnd_b <= en;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_enaAnd_q <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_enaAnd_a and ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_enaAnd_b;
--ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt(COUNTER,550)
-- every=1, low=0, high=6, step=1, init=1
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt_i = 5 THEN
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt_eq <= '1';
ELSE
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt_eq = '1') THEN
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt_i <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt_i - 6;
ELSE
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt_i <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt_i,3));
--ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdreg(REG,551)
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdreg_q <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdmux(MUX,552)
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdmux_s <= en;
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdmux: PROCESS (ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdmux_s, ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdreg_q, ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt_q)
BEGIN
CASE ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdmux_s IS
WHEN "0" => ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdmux_q <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdreg_q;
WHEN "1" => ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdmux_q <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem(DUALMEM,575)
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_reset0 <= areset;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_ia <= reg_zAddr_uid62_fpCosPiTest_0_to_memoryC2_uid209_sinPiZTableGenerator_0_q;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_aa <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdreg_q;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_ab <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdmux_q;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 7,
widthad_a => 3,
numwords_a => 7,
width_b => 7,
widthad_b => 3,
numwords_b => 7,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_iq,
address_a => ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_aa,
data_a => ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_ia
);
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_q <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_iq(6 downto 0);
--memoryC0_uid207_sinPiZTableGenerator(LOOKUP,206)@12
memoryC0_uid207_sinPiZTableGenerator: PROCESS (ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_q)
BEGIN
-- Begin reserved scope level
CASE (ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_q) IS
WHEN "0000000" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100100100001111110110101110";
WHEN "0000001" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100100100001110100100000010";
WHEN "0000010" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100100100001010101100000000";
WHEN "0000011" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100100100000100001110101000";
WHEN "0000100" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100100011111011001011111101";
WHEN "0000101" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100100011101111100100000010";
WHEN "0000110" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100100011100001010110111011";
WHEN "0000111" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100100011010000100100101111";
WHEN "0001000" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100100010111101001101100010";
WHEN "0001001" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100100010100111010001011101";
WHEN "0001010" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100100010001110110000100111";
WHEN "0001011" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100100001110011101011001001";
WHEN "0001100" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100100001010110000001001110";
WHEN "0001101" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100100000110101110011000000";
WHEN "0001110" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100100000010011000000101011";
WHEN "0001111" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100011111101101101010011101";
WHEN "0010000" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100011111000101110000100010";
WHEN "0010001" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100011110011011010011001011";
WHEN "0010010" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100011101101110010010100101";
WHEN "0010011" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100011100111110101111000011";
WHEN "0010100" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100011100001100101000110101";
WHEN "0010101" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100011011011000000000001111";
WHEN "0010110" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100011010100000110101100011";
WHEN "0010111" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100011001100111001001000110";
WHEN "0011000" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100011000101010111011001110";
WHEN "0011001" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100010111101100001100010000";
WHEN "0011010" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100010110101010111100100100";
WHEN "0011011" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100010101100111001100100010";
WHEN "0011100" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100010100100000111100100011";
WHEN "0011101" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100010011011000001101000000";
WHEN "0011110" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100010010001100111110010110";
WHEN "0011111" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100010000111111010000111111";
WHEN "0100000" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100001111101111000101010111";
WHEN "0100001" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100001110011100011011111110";
WHEN "0100010" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100001101000111010101010001";
WHEN "0100011" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100001011101111110001110000";
WHEN "0100100" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100001010010101110001111010";
WHEN "0100101" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100001000111001010110010010";
WHEN "0100110" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100000111011010011111011001";
WHEN "0100111" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100000101111001001101110010";
WHEN "0101000" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100000100010101100010000001";
WHEN "0101001" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100000010101111011100101011";
WHEN "0101010" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100000001000110111110010101";
WHEN "0101011" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011111111011100000111100110";
WHEN "0101100" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011111101101110111001000101";
WHEN "0101101" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011111011111111010011011011";
WHEN "0101110" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011111010001101010111001111";
WHEN "0101111" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011111000011001000101001110";
WHEN "0110000" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011110110100010011110000000";
WHEN "0110001" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011110100101001100010010010";
WHEN "0110010" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011110010101110010010110000";
WHEN "0110011" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011110000110000110000001000";
WHEN "0110100" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011101110110000111011000111";
WHEN "0110101" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011101100101110110100011101";
WHEN "0110110" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011101010101010011100111001";
WHEN "0110111" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011101000100011110101001100";
WHEN "0111000" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011100110011010111110000111";
WHEN "0111001" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011100100001111111000011101";
WHEN "0111010" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011100010000010100101000000";
WHEN "0111011" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011011111110011000100100100";
WHEN "0111100" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011011101100001010111111110";
WHEN "0111101" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011011011001101100000000011";
WHEN "0111110" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011011000110111011101101010";
WHEN "0111111" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011010110011111010001101001";
WHEN "1000000" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011010100000100111100111000";
WHEN "1000001" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011010001101000100000001111";
WHEN "1000010" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011001111001001111100100111";
WHEN "1000011" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011001100101001010010111011";
WHEN "1000100" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011001010000110100100000101";
WHEN "1000101" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011000111100001110001000001";
WHEN "1000110" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011000100111010111010101011";
WHEN "1000111" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011000010010010000001111111";
WHEN "1001000" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010111111100111000111111011";
WHEN "1001001" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010111100111010001101011110";
WHEN "1001010" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010111010001011010011100110";
WHEN "1001011" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010110111011010011011010011";
WHEN "1001100" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010110100100111100101100110";
WHEN "1001101" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010110001110010110011011111";
WHEN "1001110" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010101110111100000110000001";
WHEN "1001111" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010101100000011011110001110";
WHEN "1010000" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010101001001000111101001000";
WHEN "1010001" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010100110001100100011110100";
WHEN "1010010" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010100011001110010011010110";
WHEN "1010011" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010100000001110001100110010";
WHEN "1010100" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010011101001100010001001111";
WHEN "1010101" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010011010001000100001110100";
WHEN "1010110" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010010111000010111111100101";
WHEN "1010111" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010010011111011101011101100";
WHEN "1011000" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010010000110010100111010001";
WHEN "1011001" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010001101100111110011011011";
WHEN "1011010" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010001010011011010001010100";
WHEN "1011011" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010000111001101000010000111";
WHEN "1011100" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010000011111101000110111110";
WHEN "1011101" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010000000101011100001000010";
WHEN "1011110" => memoryC0_uid207_sinPiZTableGenerator_q <= "01001111101011000010001100001";
WHEN "1011111" => memoryC0_uid207_sinPiZTableGenerator_q <= "01001111010000011011001100111";
WHEN "1100000" => memoryC0_uid207_sinPiZTableGenerator_q <= "01001110110101100111010011111";
WHEN "1100001" => memoryC0_uid207_sinPiZTableGenerator_q <= "01001110011010100110101010111";
WHEN "1100010" => memoryC0_uid207_sinPiZTableGenerator_q <= "01001101111111011001011011101";
WHEN "1100011" => memoryC0_uid207_sinPiZTableGenerator_q <= "01001101100011111111101111111";
WHEN "1100100" => memoryC0_uid207_sinPiZTableGenerator_q <= "01001101001000011001110001011";
WHEN "1100101" => memoryC0_uid207_sinPiZTableGenerator_q <= "01001100101100100111101010001";
WHEN "1100110" => memoryC0_uid207_sinPiZTableGenerator_q <= "01001100010000101001100100001";
WHEN "1100111" => memoryC0_uid207_sinPiZTableGenerator_q <= "01001011110100011111101001011";
WHEN "1101000" => memoryC0_uid207_sinPiZTableGenerator_q <= "01001011011000001010000011111";
WHEN "1101001" => memoryC0_uid207_sinPiZTableGenerator_q <= "01001010111011101000111101111";
WHEN "1101010" => memoryC0_uid207_sinPiZTableGenerator_q <= "01001010011110111100100001011";
WHEN "1101011" => memoryC0_uid207_sinPiZTableGenerator_q <= "01001010000010000100111000111";
WHEN "1101100" => memoryC0_uid207_sinPiZTableGenerator_q <= "01001001100101000010001110101";
WHEN "1101101" => memoryC0_uid207_sinPiZTableGenerator_q <= "01001001000111110100101100111";
WHEN "1101110" => memoryC0_uid207_sinPiZTableGenerator_q <= "01001000101010011100011110001";
WHEN "1101111" => memoryC0_uid207_sinPiZTableGenerator_q <= "01001000001100111001101100110";
WHEN "1110000" => memoryC0_uid207_sinPiZTableGenerator_q <= "01000111101111001100100011011";
WHEN "1110001" => memoryC0_uid207_sinPiZTableGenerator_q <= "01000111010001010101001100101";
WHEN "1110010" => memoryC0_uid207_sinPiZTableGenerator_q <= "01000110110011010011110010111";
WHEN "1110011" => memoryC0_uid207_sinPiZTableGenerator_q <= "01000110010101001000100001000";
WHEN "1110100" => memoryC0_uid207_sinPiZTableGenerator_q <= "01000101110110110011100001101";
WHEN "1110101" => memoryC0_uid207_sinPiZTableGenerator_q <= "01000101011000010100111111100";
WHEN "1110110" => memoryC0_uid207_sinPiZTableGenerator_q <= "01000100111001101101000101100";
WHEN "1110111" => memoryC0_uid207_sinPiZTableGenerator_q <= "01000100011010111011111110011";
WHEN "1111000" => memoryC0_uid207_sinPiZTableGenerator_q <= "01000011111100000001110101000";
WHEN "1111001" => memoryC0_uid207_sinPiZTableGenerator_q <= "01000011011100111110110100010";
WHEN "1111010" => memoryC0_uid207_sinPiZTableGenerator_q <= "01000010111101110011000111010";
WHEN "1111011" => memoryC0_uid207_sinPiZTableGenerator_q <= "01000010011110011110111000111";
WHEN "1111100" => memoryC0_uid207_sinPiZTableGenerator_q <= "01000001111111000010010100010";
WHEN "1111101" => memoryC0_uid207_sinPiZTableGenerator_q <= "01000001011111011101100100011";
WHEN "1111110" => memoryC0_uid207_sinPiZTableGenerator_q <= "01000000111111110000110100011";
WHEN "1111111" => memoryC0_uid207_sinPiZTableGenerator_q <= "01000000011111111100001111011";
WHEN OTHERS =>
memoryC0_uid207_sinPiZTableGenerator_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--sumAHighB_uid220_sinPiZPolyEval(ADD,219)@12
sumAHighB_uid220_sinPiZPolyEval_a <= STD_LOGIC_VECTOR((29 downto 29 => memoryC0_uid207_sinPiZTableGenerator_q(28)) & memoryC0_uid207_sinPiZTableGenerator_q);
sumAHighB_uid220_sinPiZPolyEval_b <= STD_LOGIC_VECTOR((29 downto 22 => highBBits_uid219_sinPiZPolyEval_b(21)) & highBBits_uid219_sinPiZPolyEval_b);
sumAHighB_uid220_sinPiZPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid220_sinPiZPolyEval_a) + SIGNED(sumAHighB_uid220_sinPiZPolyEval_b));
sumAHighB_uid220_sinPiZPolyEval_q <= sumAHighB_uid220_sinPiZPolyEval_o(29 downto 0);
--lowRangeB_uid218_sinPiZPolyEval(BITSELECT,217)@12
lowRangeB_uid218_sinPiZPolyEval_in <= prodXYTruncFR_uid230_pT2_uid217_sinPiZPolyEval_b(1 downto 0);
lowRangeB_uid218_sinPiZPolyEval_b <= lowRangeB_uid218_sinPiZPolyEval_in(1 downto 0);
--s2_uid218_uid221_sinPiZPolyEval(BITJOIN,220)@12
s2_uid218_uid221_sinPiZPolyEval_q <= sumAHighB_uid220_sinPiZPolyEval_q & lowRangeB_uid218_sinPiZPolyEval_b;
--fxpSinRes_uid65_fpCosPiTest(BITSELECT,64)@12
fxpSinRes_uid65_fpCosPiTest_in <= s2_uid218_uid221_sinPiZPolyEval_q(29 downto 0);
fxpSinRes_uid65_fpCosPiTest_b <= fxpSinRes_uid65_fpCosPiTest_in(29 downto 5);
--reg_fxpSinRes_uid65_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_1(REG,270)@12
reg_fxpSinRes_uid65_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fxpSinRes_uid65_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_1_q <= "0000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fxpSinRes_uid65_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_1_q <= fxpSinRes_uid65_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_nor(LOGICAL,622)
ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_nor_a <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_notEnable_q;
ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_nor_b <= ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_sticky_ena_q;
ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_nor_q <= not (ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_nor_a or ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_nor_b);
--ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_sticky_ena(REG,623)
ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_nor_q = "1") THEN
ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_sticky_ena_q <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_enaAnd(LOGICAL,624)
ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_enaAnd_a <= ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_sticky_ena_q;
ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_enaAnd_b <= en;
ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_enaAnd_q <= ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_enaAnd_a and ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_enaAnd_b;
--LeftShiftStage131dto0_uid202_alignedZ_uid57_fpCosPiTest(BITSELECT,201)@7
LeftShiftStage131dto0_uid202_alignedZ_uid57_fpCosPiTest_in <= leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_q(31 downto 0);
LeftShiftStage131dto0_uid202_alignedZ_uid57_fpCosPiTest_b <= LeftShiftStage131dto0_uid202_alignedZ_uid57_fpCosPiTest_in(31 downto 0);
--leftShiftStage2Idx3_uid203_alignedZ_uid57_fpCosPiTest(BITJOIN,202)@7
leftShiftStage2Idx3_uid203_alignedZ_uid57_fpCosPiTest_q <= LeftShiftStage131dto0_uid202_alignedZ_uid57_fpCosPiTest_b & leftShiftStage2Idx3Pad3_uid131_fxpX_uid41_fpCosPiTest_q;
--LeftShiftStage132dto0_uid199_alignedZ_uid57_fpCosPiTest(BITSELECT,198)@7
LeftShiftStage132dto0_uid199_alignedZ_uid57_fpCosPiTest_in <= leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_q(32 downto 0);
LeftShiftStage132dto0_uid199_alignedZ_uid57_fpCosPiTest_b <= LeftShiftStage132dto0_uid199_alignedZ_uid57_fpCosPiTest_in(32 downto 0);
--leftShiftStage2Idx2_uid200_alignedZ_uid57_fpCosPiTest(BITJOIN,199)@7
leftShiftStage2Idx2_uid200_alignedZ_uid57_fpCosPiTest_q <= LeftShiftStage132dto0_uid199_alignedZ_uid57_fpCosPiTest_b & leftShiftStage2Idx2Pad2_uid128_fxpX_uid41_fpCosPiTest_q;
--LeftShiftStage133dto0_uid196_alignedZ_uid57_fpCosPiTest(BITSELECT,195)@7
LeftShiftStage133dto0_uid196_alignedZ_uid57_fpCosPiTest_in <= leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_q(33 downto 0);
LeftShiftStage133dto0_uid196_alignedZ_uid57_fpCosPiTest_b <= LeftShiftStage133dto0_uid196_alignedZ_uid57_fpCosPiTest_in(33 downto 0);
--leftShiftStage2Idx1_uid197_alignedZ_uid57_fpCosPiTest(BITJOIN,196)@7
leftShiftStage2Idx1_uid197_alignedZ_uid57_fpCosPiTest_q <= LeftShiftStage133dto0_uid196_alignedZ_uid57_fpCosPiTest_b & GND_q;
--vStage_uid141_lzcZ_uid56_fpCosPiTest(BITSELECT,140)@3
vStage_uid141_lzcZ_uid56_fpCosPiTest_in <= z_uid54_fpCosPiTest_b(2 downto 0);
vStage_uid141_lzcZ_uid56_fpCosPiTest_b <= vStage_uid141_lzcZ_uid56_fpCosPiTest_in(2 downto 0);
--ld_vStage_uid141_lzcZ_uid56_fpCosPiTest_b_to_leftShiftStage0Idx2_uid180_alignedZ_uid57_fpCosPiTest_b(DELAY,450)@3
ld_vStage_uid141_lzcZ_uid56_fpCosPiTest_b_to_leftShiftStage0Idx2_uid180_alignedZ_uid57_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 3, depth => 3 )
PORT MAP ( xin => vStage_uid141_lzcZ_uid56_fpCosPiTest_b, xout => ld_vStage_uid141_lzcZ_uid56_fpCosPiTest_b_to_leftShiftStage0Idx2_uid180_alignedZ_uid57_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage0Idx2_uid180_alignedZ_uid57_fpCosPiTest(BITJOIN,179)@6
leftShiftStage0Idx2_uid180_alignedZ_uid57_fpCosPiTest_q <= ld_vStage_uid141_lzcZ_uid56_fpCosPiTest_b_to_leftShiftStage0Idx2_uid180_alignedZ_uid57_fpCosPiTest_b_q & leftShiftStage0Idx2Pad32_uid108_fxpX_uid41_fpCosPiTest_q;
--X18dto0_uid176_alignedZ_uid57_fpCosPiTest(BITSELECT,175)@3
X18dto0_uid176_alignedZ_uid57_fpCosPiTest_in <= z_uid54_fpCosPiTest_b(18 downto 0);
X18dto0_uid176_alignedZ_uid57_fpCosPiTest_b <= X18dto0_uid176_alignedZ_uid57_fpCosPiTest_in(18 downto 0);
--ld_X18dto0_uid176_alignedZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx1_uid177_alignedZ_uid57_fpCosPiTest_b_inputreg(DELAY,573)
ld_X18dto0_uid176_alignedZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx1_uid177_alignedZ_uid57_fpCosPiTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 19, depth => 1 )
PORT MAP ( xin => X18dto0_uid176_alignedZ_uid57_fpCosPiTest_b, xout => ld_X18dto0_uid176_alignedZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx1_uid177_alignedZ_uid57_fpCosPiTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_X18dto0_uid176_alignedZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx1_uid177_alignedZ_uid57_fpCosPiTest_b(DELAY,449)@3
ld_X18dto0_uid176_alignedZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx1_uid177_alignedZ_uid57_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 19, depth => 2 )
PORT MAP ( xin => ld_X18dto0_uid176_alignedZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx1_uid177_alignedZ_uid57_fpCosPiTest_b_inputreg_q, xout => ld_X18dto0_uid176_alignedZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx1_uid177_alignedZ_uid57_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage0Idx1_uid177_alignedZ_uid57_fpCosPiTest(BITJOIN,176)@6
leftShiftStage0Idx1_uid177_alignedZ_uid57_fpCosPiTest_q <= ld_X18dto0_uid176_alignedZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx1_uid177_alignedZ_uid57_fpCosPiTest_b_q & leftShiftStage0Idx1Pad16_uid105_fxpX_uid41_fpCosPiTest_q;
--ld_z_uid54_fpCosPiTest_b_to_leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_c_inputreg(DELAY,574)
ld_z_uid54_fpCosPiTest_b_to_leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 35, depth => 1 )
PORT MAP ( xin => z_uid54_fpCosPiTest_b, xout => ld_z_uid54_fpCosPiTest_b_to_leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_z_uid54_fpCosPiTest_b_to_leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_c(DELAY,453)@3
ld_z_uid54_fpCosPiTest_b_to_leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_c : dspba_delay
GENERIC MAP ( width => 35, depth => 2 )
PORT MAP ( xin => ld_z_uid54_fpCosPiTest_b_to_leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_c_inputreg_q, xout => ld_z_uid54_fpCosPiTest_b_to_leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--rVStage_uid138_lzcZ_uid56_fpCosPiTest(BITSELECT,137)@3
rVStage_uid138_lzcZ_uid56_fpCosPiTest_in <= z_uid54_fpCosPiTest_b;
rVStage_uid138_lzcZ_uid56_fpCosPiTest_b <= rVStage_uid138_lzcZ_uid56_fpCosPiTest_in(34 downto 3);
--reg_rVStage_uid138_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid139_lzcZ_uid56_fpCosPiTest_1(REG,247)@3
reg_rVStage_uid138_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid139_lzcZ_uid56_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid138_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid139_lzcZ_uid56_fpCosPiTest_1_q <= "00000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid138_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid139_lzcZ_uid56_fpCosPiTest_1_q <= rVStage_uid138_lzcZ_uid56_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid139_lzcZ_uid56_fpCosPiTest(LOGICAL,138)@4
vCount_uid139_lzcZ_uid56_fpCosPiTest_a <= reg_rVStage_uid138_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid139_lzcZ_uid56_fpCosPiTest_1_q;
vCount_uid139_lzcZ_uid56_fpCosPiTest_b <= leftShiftStage0Idx2Pad32_uid108_fxpX_uid41_fpCosPiTest_q;
vCount_uid139_lzcZ_uid56_fpCosPiTest_q <= "1" when vCount_uid139_lzcZ_uid56_fpCosPiTest_a = vCount_uid139_lzcZ_uid56_fpCosPiTest_b else "0";
--ld_vCount_uid139_lzcZ_uid56_fpCosPiTest_q_to_r_uid172_lzcZ_uid56_fpCosPiTest_f(DELAY,447)@4
ld_vCount_uid139_lzcZ_uid56_fpCosPiTest_q_to_r_uid172_lzcZ_uid56_fpCosPiTest_f : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => vCount_uid139_lzcZ_uid56_fpCosPiTest_q, xout => ld_vCount_uid139_lzcZ_uid56_fpCosPiTest_q_to_r_uid172_lzcZ_uid56_fpCosPiTest_f_q, ena => en(0), clk => clk, aclr => areset );
--mO_uid140_lzcZ_uid56_fpCosPiTest(CONSTANT,139)
mO_uid140_lzcZ_uid56_fpCosPiTest_q <= "11111111111111111111111111111";
--cStage_uid142_lzcZ_uid56_fpCosPiTest(BITJOIN,141)@3
cStage_uid142_lzcZ_uid56_fpCosPiTest_q <= vStage_uid141_lzcZ_uid56_fpCosPiTest_b & mO_uid140_lzcZ_uid56_fpCosPiTest_q;
--reg_cStage_uid142_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid144_lzcZ_uid56_fpCosPiTest_3(REG,249)@3
reg_cStage_uid142_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid144_lzcZ_uid56_fpCosPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cStage_uid142_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid144_lzcZ_uid56_fpCosPiTest_3_q <= "00000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cStage_uid142_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid144_lzcZ_uid56_fpCosPiTest_3_q <= cStage_uid142_lzcZ_uid56_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--vStagei_uid144_lzcZ_uid56_fpCosPiTest(MUX,143)@4
vStagei_uid144_lzcZ_uid56_fpCosPiTest_s <= vCount_uid139_lzcZ_uid56_fpCosPiTest_q;
vStagei_uid144_lzcZ_uid56_fpCosPiTest: PROCESS (vStagei_uid144_lzcZ_uid56_fpCosPiTest_s, en, reg_rVStage_uid138_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid139_lzcZ_uid56_fpCosPiTest_1_q, reg_cStage_uid142_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid144_lzcZ_uid56_fpCosPiTest_3_q)
BEGIN
CASE vStagei_uid144_lzcZ_uid56_fpCosPiTest_s IS
WHEN "0" => vStagei_uid144_lzcZ_uid56_fpCosPiTest_q <= reg_rVStage_uid138_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid139_lzcZ_uid56_fpCosPiTest_1_q;
WHEN "1" => vStagei_uid144_lzcZ_uid56_fpCosPiTest_q <= reg_cStage_uid142_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid144_lzcZ_uid56_fpCosPiTest_3_q;
WHEN OTHERS => vStagei_uid144_lzcZ_uid56_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid146_lzcZ_uid56_fpCosPiTest(BITSELECT,145)@4
rVStage_uid146_lzcZ_uid56_fpCosPiTest_in <= vStagei_uid144_lzcZ_uid56_fpCosPiTest_q;
rVStage_uid146_lzcZ_uid56_fpCosPiTest_b <= rVStage_uid146_lzcZ_uid56_fpCosPiTest_in(31 downto 16);
--reg_rVStage_uid146_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid147_lzcZ_uid56_fpCosPiTest_1(REG,250)@4
reg_rVStage_uid146_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid147_lzcZ_uid56_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid146_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid147_lzcZ_uid56_fpCosPiTest_1_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid146_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid147_lzcZ_uid56_fpCosPiTest_1_q <= rVStage_uid146_lzcZ_uid56_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid147_lzcZ_uid56_fpCosPiTest(LOGICAL,146)@5
vCount_uid147_lzcZ_uid56_fpCosPiTest_a <= reg_rVStage_uid146_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid147_lzcZ_uid56_fpCosPiTest_1_q;
vCount_uid147_lzcZ_uid56_fpCosPiTest_b <= leftShiftStage0Idx1Pad16_uid105_fxpX_uid41_fpCosPiTest_q;
vCount_uid147_lzcZ_uid56_fpCosPiTest_q <= "1" when vCount_uid147_lzcZ_uid56_fpCosPiTest_a = vCount_uid147_lzcZ_uid56_fpCosPiTest_b else "0";
--ld_vCount_uid147_lzcZ_uid56_fpCosPiTest_q_to_r_uid172_lzcZ_uid56_fpCosPiTest_e(DELAY,446)@5
ld_vCount_uid147_lzcZ_uid56_fpCosPiTest_q_to_r_uid172_lzcZ_uid56_fpCosPiTest_e : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vCount_uid147_lzcZ_uid56_fpCosPiTest_q, xout => ld_vCount_uid147_lzcZ_uid56_fpCosPiTest_q_to_r_uid172_lzcZ_uid56_fpCosPiTest_e_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid148_lzcZ_uid56_fpCosPiTest(BITSELECT,147)@4
vStage_uid148_lzcZ_uid56_fpCosPiTest_in <= vStagei_uid144_lzcZ_uid56_fpCosPiTest_q(15 downto 0);
vStage_uid148_lzcZ_uid56_fpCosPiTest_b <= vStage_uid148_lzcZ_uid56_fpCosPiTest_in(15 downto 0);
--reg_vStage_uid148_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid150_lzcZ_uid56_fpCosPiTest_3(REG,252)@4
reg_vStage_uid148_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid150_lzcZ_uid56_fpCosPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid148_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid150_lzcZ_uid56_fpCosPiTest_3_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid148_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid150_lzcZ_uid56_fpCosPiTest_3_q <= vStage_uid148_lzcZ_uid56_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid150_lzcZ_uid56_fpCosPiTest(MUX,149)@5
vStagei_uid150_lzcZ_uid56_fpCosPiTest_s <= vCount_uid147_lzcZ_uid56_fpCosPiTest_q;
vStagei_uid150_lzcZ_uid56_fpCosPiTest: PROCESS (vStagei_uid150_lzcZ_uid56_fpCosPiTest_s, en, reg_rVStage_uid146_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid147_lzcZ_uid56_fpCosPiTest_1_q, reg_vStage_uid148_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid150_lzcZ_uid56_fpCosPiTest_3_q)
BEGIN
CASE vStagei_uid150_lzcZ_uid56_fpCosPiTest_s IS
WHEN "0" => vStagei_uid150_lzcZ_uid56_fpCosPiTest_q <= reg_rVStage_uid146_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid147_lzcZ_uid56_fpCosPiTest_1_q;
WHEN "1" => vStagei_uid150_lzcZ_uid56_fpCosPiTest_q <= reg_vStage_uid148_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid150_lzcZ_uid56_fpCosPiTest_3_q;
WHEN OTHERS => vStagei_uid150_lzcZ_uid56_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid152_lzcZ_uid56_fpCosPiTest(BITSELECT,151)@5
rVStage_uid152_lzcZ_uid56_fpCosPiTest_in <= vStagei_uid150_lzcZ_uid56_fpCosPiTest_q;
rVStage_uid152_lzcZ_uid56_fpCosPiTest_b <= rVStage_uid152_lzcZ_uid56_fpCosPiTest_in(15 downto 8);
--vCount_uid153_lzcZ_uid56_fpCosPiTest(LOGICAL,152)@5
vCount_uid153_lzcZ_uid56_fpCosPiTest_a <= rVStage_uid152_lzcZ_uid56_fpCosPiTest_b;
vCount_uid153_lzcZ_uid56_fpCosPiTest_b <= cstAllZWE_uid21_fpCosPiTest_q;
vCount_uid153_lzcZ_uid56_fpCosPiTest_q <= "1" when vCount_uid153_lzcZ_uid56_fpCosPiTest_a = vCount_uid153_lzcZ_uid56_fpCosPiTest_b else "0";
--reg_vCount_uid153_lzcZ_uid56_fpCosPiTest_0_to_r_uid172_lzcZ_uid56_fpCosPiTest_3(REG,256)@5
reg_vCount_uid153_lzcZ_uid56_fpCosPiTest_0_to_r_uid172_lzcZ_uid56_fpCosPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid153_lzcZ_uid56_fpCosPiTest_0_to_r_uid172_lzcZ_uid56_fpCosPiTest_3_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid153_lzcZ_uid56_fpCosPiTest_0_to_r_uid172_lzcZ_uid56_fpCosPiTest_3_q <= vCount_uid153_lzcZ_uid56_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--vStage_uid154_lzcZ_uid56_fpCosPiTest(BITSELECT,153)@5
vStage_uid154_lzcZ_uid56_fpCosPiTest_in <= vStagei_uid150_lzcZ_uid56_fpCosPiTest_q(7 downto 0);
vStage_uid154_lzcZ_uid56_fpCosPiTest_b <= vStage_uid154_lzcZ_uid56_fpCosPiTest_in(7 downto 0);
--vStagei_uid156_lzcZ_uid56_fpCosPiTest(MUX,155)@5
vStagei_uid156_lzcZ_uid56_fpCosPiTest_s <= vCount_uid153_lzcZ_uid56_fpCosPiTest_q;
vStagei_uid156_lzcZ_uid56_fpCosPiTest: PROCESS (vStagei_uid156_lzcZ_uid56_fpCosPiTest_s, en, rVStage_uid152_lzcZ_uid56_fpCosPiTest_b, vStage_uid154_lzcZ_uid56_fpCosPiTest_b)
BEGIN
CASE vStagei_uid156_lzcZ_uid56_fpCosPiTest_s IS
WHEN "0" => vStagei_uid156_lzcZ_uid56_fpCosPiTest_q <= rVStage_uid152_lzcZ_uid56_fpCosPiTest_b;
WHEN "1" => vStagei_uid156_lzcZ_uid56_fpCosPiTest_q <= vStage_uid154_lzcZ_uid56_fpCosPiTest_b;
WHEN OTHERS => vStagei_uid156_lzcZ_uid56_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid158_lzcZ_uid56_fpCosPiTest(BITSELECT,157)@5
rVStage_uid158_lzcZ_uid56_fpCosPiTest_in <= vStagei_uid156_lzcZ_uid56_fpCosPiTest_q;
rVStage_uid158_lzcZ_uid56_fpCosPiTest_b <= rVStage_uid158_lzcZ_uid56_fpCosPiTest_in(7 downto 4);
--reg_rVStage_uid158_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid159_lzcZ_uid56_fpCosPiTest_1(REG,253)@5
reg_rVStage_uid158_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid159_lzcZ_uid56_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid158_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid159_lzcZ_uid56_fpCosPiTest_1_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid158_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid159_lzcZ_uid56_fpCosPiTest_1_q <= rVStage_uid158_lzcZ_uid56_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid159_lzcZ_uid56_fpCosPiTest(LOGICAL,158)@6
vCount_uid159_lzcZ_uid56_fpCosPiTest_a <= reg_rVStage_uid158_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid159_lzcZ_uid56_fpCosPiTest_1_q;
vCount_uid159_lzcZ_uid56_fpCosPiTest_b <= leftShiftStage1Idx1Pad4_uid114_fxpX_uid41_fpCosPiTest_q;
vCount_uid159_lzcZ_uid56_fpCosPiTest_q <= "1" when vCount_uid159_lzcZ_uid56_fpCosPiTest_a = vCount_uid159_lzcZ_uid56_fpCosPiTest_b else "0";
--vStage_uid160_lzcZ_uid56_fpCosPiTest(BITSELECT,159)@5
vStage_uid160_lzcZ_uid56_fpCosPiTest_in <= vStagei_uid156_lzcZ_uid56_fpCosPiTest_q(3 downto 0);
vStage_uid160_lzcZ_uid56_fpCosPiTest_b <= vStage_uid160_lzcZ_uid56_fpCosPiTest_in(3 downto 0);
--reg_vStage_uid160_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid162_lzcZ_uid56_fpCosPiTest_3(REG,255)@5
reg_vStage_uid160_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid162_lzcZ_uid56_fpCosPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid160_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid162_lzcZ_uid56_fpCosPiTest_3_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid160_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid162_lzcZ_uid56_fpCosPiTest_3_q <= vStage_uid160_lzcZ_uid56_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid162_lzcZ_uid56_fpCosPiTest(MUX,161)@6
vStagei_uid162_lzcZ_uid56_fpCosPiTest_s <= vCount_uid159_lzcZ_uid56_fpCosPiTest_q;
vStagei_uid162_lzcZ_uid56_fpCosPiTest: PROCESS (vStagei_uid162_lzcZ_uid56_fpCosPiTest_s, en, reg_rVStage_uid158_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid159_lzcZ_uid56_fpCosPiTest_1_q, reg_vStage_uid160_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid162_lzcZ_uid56_fpCosPiTest_3_q)
BEGIN
CASE vStagei_uid162_lzcZ_uid56_fpCosPiTest_s IS
WHEN "0" => vStagei_uid162_lzcZ_uid56_fpCosPiTest_q <= reg_rVStage_uid158_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid159_lzcZ_uid56_fpCosPiTest_1_q;
WHEN "1" => vStagei_uid162_lzcZ_uid56_fpCosPiTest_q <= reg_vStage_uid160_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid162_lzcZ_uid56_fpCosPiTest_3_q;
WHEN OTHERS => vStagei_uid162_lzcZ_uid56_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid164_lzcZ_uid56_fpCosPiTest(BITSELECT,163)@6
rVStage_uid164_lzcZ_uid56_fpCosPiTest_in <= vStagei_uid162_lzcZ_uid56_fpCosPiTest_q;
rVStage_uid164_lzcZ_uid56_fpCosPiTest_b <= rVStage_uid164_lzcZ_uid56_fpCosPiTest_in(3 downto 2);
--vCount_uid165_lzcZ_uid56_fpCosPiTest(LOGICAL,164)@6
vCount_uid165_lzcZ_uid56_fpCosPiTest_a <= rVStage_uid164_lzcZ_uid56_fpCosPiTest_b;
vCount_uid165_lzcZ_uid56_fpCosPiTest_b <= leftShiftStage2Idx2Pad2_uid128_fxpX_uid41_fpCosPiTest_q;
vCount_uid165_lzcZ_uid56_fpCosPiTest_q <= "1" when vCount_uid165_lzcZ_uid56_fpCosPiTest_a = vCount_uid165_lzcZ_uid56_fpCosPiTest_b else "0";
--vStage_uid166_lzcZ_uid56_fpCosPiTest(BITSELECT,165)@6
vStage_uid166_lzcZ_uid56_fpCosPiTest_in <= vStagei_uid162_lzcZ_uid56_fpCosPiTest_q(1 downto 0);
vStage_uid166_lzcZ_uid56_fpCosPiTest_b <= vStage_uid166_lzcZ_uid56_fpCosPiTest_in(1 downto 0);
--vStagei_uid168_lzcZ_uid56_fpCosPiTest(MUX,167)@6
vStagei_uid168_lzcZ_uid56_fpCosPiTest_s <= vCount_uid165_lzcZ_uid56_fpCosPiTest_q;
vStagei_uid168_lzcZ_uid56_fpCosPiTest: PROCESS (vStagei_uid168_lzcZ_uid56_fpCosPiTest_s, en, rVStage_uid164_lzcZ_uid56_fpCosPiTest_b, vStage_uid166_lzcZ_uid56_fpCosPiTest_b)
BEGIN
CASE vStagei_uid168_lzcZ_uid56_fpCosPiTest_s IS
WHEN "0" => vStagei_uid168_lzcZ_uid56_fpCosPiTest_q <= rVStage_uid164_lzcZ_uid56_fpCosPiTest_b;
WHEN "1" => vStagei_uid168_lzcZ_uid56_fpCosPiTest_q <= vStage_uid166_lzcZ_uid56_fpCosPiTest_b;
WHEN OTHERS => vStagei_uid168_lzcZ_uid56_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid170_lzcZ_uid56_fpCosPiTest(BITSELECT,169)@6
rVStage_uid170_lzcZ_uid56_fpCosPiTest_in <= vStagei_uid168_lzcZ_uid56_fpCosPiTest_q;
rVStage_uid170_lzcZ_uid56_fpCosPiTest_b <= rVStage_uid170_lzcZ_uid56_fpCosPiTest_in(1 downto 1);
--vCount_uid171_lzcZ_uid56_fpCosPiTest(LOGICAL,170)@6
vCount_uid171_lzcZ_uid56_fpCosPiTest_a <= rVStage_uid170_lzcZ_uid56_fpCosPiTest_b;
vCount_uid171_lzcZ_uid56_fpCosPiTest_b <= GND_q;
vCount_uid171_lzcZ_uid56_fpCosPiTest_q <= "1" when vCount_uid171_lzcZ_uid56_fpCosPiTest_a = vCount_uid171_lzcZ_uid56_fpCosPiTest_b else "0";
--r_uid172_lzcZ_uid56_fpCosPiTest(BITJOIN,171)@6
r_uid172_lzcZ_uid56_fpCosPiTest_q <= ld_vCount_uid139_lzcZ_uid56_fpCosPiTest_q_to_r_uid172_lzcZ_uid56_fpCosPiTest_f_q & ld_vCount_uid147_lzcZ_uid56_fpCosPiTest_q_to_r_uid172_lzcZ_uid56_fpCosPiTest_e_q & reg_vCount_uid153_lzcZ_uid56_fpCosPiTest_0_to_r_uid172_lzcZ_uid56_fpCosPiTest_3_q & vCount_uid159_lzcZ_uid56_fpCosPiTest_q & vCount_uid165_lzcZ_uid56_fpCosPiTest_q & vCount_uid171_lzcZ_uid56_fpCosPiTest_q;
--leftShiftStageSel5Dto4_uid182_alignedZ_uid57_fpCosPiTest(BITSELECT,181)@6
leftShiftStageSel5Dto4_uid182_alignedZ_uid57_fpCosPiTest_in <= r_uid172_lzcZ_uid56_fpCosPiTest_q;
leftShiftStageSel5Dto4_uid182_alignedZ_uid57_fpCosPiTest_b <= leftShiftStageSel5Dto4_uid182_alignedZ_uid57_fpCosPiTest_in(5 downto 4);
--leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest(MUX,182)@6
leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_s <= leftShiftStageSel5Dto4_uid182_alignedZ_uid57_fpCosPiTest_b;
leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest: PROCESS (leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_s, en, ld_z_uid54_fpCosPiTest_b_to_leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_c_q, leftShiftStage0Idx1_uid177_alignedZ_uid57_fpCosPiTest_q, leftShiftStage0Idx2_uid180_alignedZ_uid57_fpCosPiTest_q, cstZwSwF_uid15_fpCosPiTest_q)
BEGIN
CASE leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_s IS
WHEN "00" => leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_q <= ld_z_uid54_fpCosPiTest_b_to_leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_c_q;
WHEN "01" => leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_q <= leftShiftStage0Idx1_uid177_alignedZ_uid57_fpCosPiTest_q;
WHEN "10" => leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_q <= leftShiftStage0Idx2_uid180_alignedZ_uid57_fpCosPiTest_q;
WHEN "11" => leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_q <= cstZwSwF_uid15_fpCosPiTest_q;
WHEN OTHERS => leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage022dto0_uid191_alignedZ_uid57_fpCosPiTest(BITSELECT,190)@6
LeftShiftStage022dto0_uid191_alignedZ_uid57_fpCosPiTest_in <= leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_q(22 downto 0);
LeftShiftStage022dto0_uid191_alignedZ_uid57_fpCosPiTest_b <= LeftShiftStage022dto0_uid191_alignedZ_uid57_fpCosPiTest_in(22 downto 0);
--leftShiftStage1Idx3_uid192_alignedZ_uid57_fpCosPiTest(BITJOIN,191)@6
leftShiftStage1Idx3_uid192_alignedZ_uid57_fpCosPiTest_q <= LeftShiftStage022dto0_uid191_alignedZ_uid57_fpCosPiTest_b & leftShiftStage1Idx3Pad12_uid120_fxpX_uid41_fpCosPiTest_q;
--reg_leftShiftStage1Idx3_uid192_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_5(REG,261)@6
reg_leftShiftStage1Idx3_uid192_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx3_uid192_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_5_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx3_uid192_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_5_q <= leftShiftStage1Idx3_uid192_alignedZ_uid57_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage026dto0_uid188_alignedZ_uid57_fpCosPiTest(BITSELECT,187)@6
LeftShiftStage026dto0_uid188_alignedZ_uid57_fpCosPiTest_in <= leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_q(26 downto 0);
LeftShiftStage026dto0_uid188_alignedZ_uid57_fpCosPiTest_b <= LeftShiftStage026dto0_uid188_alignedZ_uid57_fpCosPiTest_in(26 downto 0);
--leftShiftStage1Idx2_uid189_alignedZ_uid57_fpCosPiTest(BITJOIN,188)@6
leftShiftStage1Idx2_uid189_alignedZ_uid57_fpCosPiTest_q <= LeftShiftStage026dto0_uid188_alignedZ_uid57_fpCosPiTest_b & cstAllZWE_uid21_fpCosPiTest_q;
--reg_leftShiftStage1Idx2_uid189_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_4(REG,260)@6
reg_leftShiftStage1Idx2_uid189_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx2_uid189_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_4_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx2_uid189_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_4_q <= leftShiftStage1Idx2_uid189_alignedZ_uid57_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage030dto0_uid185_alignedZ_uid57_fpCosPiTest(BITSELECT,184)@6
LeftShiftStage030dto0_uid185_alignedZ_uid57_fpCosPiTest_in <= leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_q(30 downto 0);
LeftShiftStage030dto0_uid185_alignedZ_uid57_fpCosPiTest_b <= LeftShiftStage030dto0_uid185_alignedZ_uid57_fpCosPiTest_in(30 downto 0);
--leftShiftStage1Idx1_uid186_alignedZ_uid57_fpCosPiTest(BITJOIN,185)@6
leftShiftStage1Idx1_uid186_alignedZ_uid57_fpCosPiTest_q <= LeftShiftStage030dto0_uid185_alignedZ_uid57_fpCosPiTest_b & leftShiftStage1Idx1Pad4_uid114_fxpX_uid41_fpCosPiTest_q;
--reg_leftShiftStage1Idx1_uid186_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_3(REG,259)@6
reg_leftShiftStage1Idx1_uid186_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx1_uid186_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_3_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx1_uid186_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_3_q <= leftShiftStage1Idx1_uid186_alignedZ_uid57_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--reg_leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_2(REG,258)@6
reg_leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_2_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_2_q <= leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel3Dto2_uid193_alignedZ_uid57_fpCosPiTest(BITSELECT,192)@6
leftShiftStageSel3Dto2_uid193_alignedZ_uid57_fpCosPiTest_in <= r_uid172_lzcZ_uid56_fpCosPiTest_q(3 downto 0);
leftShiftStageSel3Dto2_uid193_alignedZ_uid57_fpCosPiTest_b <= leftShiftStageSel3Dto2_uid193_alignedZ_uid57_fpCosPiTest_in(3 downto 2);
--reg_leftShiftStageSel3Dto2_uid193_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_1(REG,257)@6
reg_leftShiftStageSel3Dto2_uid193_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel3Dto2_uid193_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel3Dto2_uid193_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_1_q <= leftShiftStageSel3Dto2_uid193_alignedZ_uid57_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest(MUX,193)@7
leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_s <= reg_leftShiftStageSel3Dto2_uid193_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_1_q;
leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest: PROCESS (leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_s, en, reg_leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_2_q, reg_leftShiftStage1Idx1_uid186_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_3_q, reg_leftShiftStage1Idx2_uid189_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_4_q, reg_leftShiftStage1Idx3_uid192_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_5_q)
BEGIN
CASE leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_s IS
WHEN "00" => leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_q <= reg_leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_2_q;
WHEN "01" => leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_q <= reg_leftShiftStage1Idx1_uid186_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_3_q;
WHEN "10" => leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_q <= reg_leftShiftStage1Idx2_uid189_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_4_q;
WHEN "11" => leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_q <= reg_leftShiftStage1Idx3_uid192_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_5_q;
WHEN OTHERS => leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--leftShiftStageSel1Dto0_uid204_alignedZ_uid57_fpCosPiTest(BITSELECT,203)@6
leftShiftStageSel1Dto0_uid204_alignedZ_uid57_fpCosPiTest_in <= r_uid172_lzcZ_uid56_fpCosPiTest_q(1 downto 0);
leftShiftStageSel1Dto0_uid204_alignedZ_uid57_fpCosPiTest_b <= leftShiftStageSel1Dto0_uid204_alignedZ_uid57_fpCosPiTest_in(1 downto 0);
--reg_leftShiftStageSel1Dto0_uid204_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest_1(REG,262)@6
reg_leftShiftStageSel1Dto0_uid204_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel1Dto0_uid204_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel1Dto0_uid204_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest_1_q <= leftShiftStageSel1Dto0_uid204_alignedZ_uid57_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest(MUX,204)@7
leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest_s <= reg_leftShiftStageSel1Dto0_uid204_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest_1_q;
leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest: PROCESS (leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest_s, en, leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_q, leftShiftStage2Idx1_uid197_alignedZ_uid57_fpCosPiTest_q, leftShiftStage2Idx2_uid200_alignedZ_uid57_fpCosPiTest_q, leftShiftStage2Idx3_uid203_alignedZ_uid57_fpCosPiTest_q)
BEGIN
CASE leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest_s IS
WHEN "00" => leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest_q <= leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_q;
WHEN "01" => leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest_q <= leftShiftStage2Idx1_uid197_alignedZ_uid57_fpCosPiTest_q;
WHEN "10" => leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest_q <= leftShiftStage2Idx2_uid200_alignedZ_uid57_fpCosPiTest_q;
WHEN "11" => leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest_q <= leftShiftStage2Idx3_uid203_alignedZ_uid57_fpCosPiTest_q;
WHEN OTHERS => leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--alignedZLow_uid58_fpCosPiTest(BITSELECT,57)@7
alignedZLow_uid58_fpCosPiTest_in <= leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest_q;
alignedZLow_uid58_fpCosPiTest_b <= alignedZLow_uid58_fpCosPiTest_in(34 downto 11);
--ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_inputreg(DELAY,612)
ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 24, depth => 1 )
PORT MAP ( xin => alignedZLow_uid58_fpCosPiTest_b, xout => ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem(DUALMEM,613)
ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_reset0 <= areset;
ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_ia <= ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_inputreg_q;
ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_aa <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdreg_q;
ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_ab <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdmux_q;
ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 24,
widthad_a => 2,
numwords_a => 3,
width_b => 24,
widthad_b => 2,
numwords_b => 3,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_iq,
address_a => ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_aa,
data_a => ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_ia
);
ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_q <= ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_iq(23 downto 0);
--reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0(REG,269)@12
reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_q <= ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest(MULT,222)@13
prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_pr <= UNSIGNED(prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_a) * UNSIGNED(prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_b);
prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_a <= (others => '0');
prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_b <= (others => '0');
prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_a <= reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_q;
prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_b <= reg_fxpSinRes_uid65_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_1_q;
prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_s1 <= STD_LOGIC_VECTOR(prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_pr);
END IF;
END IF;
END PROCESS;
prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_q <= prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid224_mul2xSinRes_uid66_fpCosPiTest(BITSELECT,223)@16
prodXYTruncFR_uid224_mul2xSinRes_uid66_fpCosPiTest_in <= prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_q;
prodXYTruncFR_uid224_mul2xSinRes_uid66_fpCosPiTest_b <= prodXYTruncFR_uid224_mul2xSinRes_uid66_fpCosPiTest_in(48 downto 23);
--normBit_uid67_fpCosPiTest(BITSELECT,66)@16
normBit_uid67_fpCosPiTest_in <= prodXYTruncFR_uid224_mul2xSinRes_uid66_fpCosPiTest_b;
normBit_uid67_fpCosPiTest_b <= normBit_uid67_fpCosPiTest_in(25 downto 25);
--cstAllZWF_uid9_fpCosPiTest(CONSTANT,8)
cstAllZWF_uid9_fpCosPiTest_q <= "00000000000000000000000";
--rndExpUpdate_uid72_uid73_fpCosPiTest(BITJOIN,72)@16
rndExpUpdate_uid72_uid73_fpCosPiTest_q <= normBit_uid67_fpCosPiTest_b & cstAllZWF_uid9_fpCosPiTest_q & VCC_q;
--ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_nor(LOGICAL,558)
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_nor_a <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_notEnable_q;
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_nor_b <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_sticky_ena_q;
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_nor_q <= not (ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_nor_a or ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_nor_b);
--ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_sticky_ena(REG,559)
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_nor_q = "1") THEN
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_sticky_ena_q <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_enaAnd(LOGICAL,560)
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_enaAnd_a <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_sticky_ena_q;
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_enaAnd_b <= en;
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_enaAnd_q <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_enaAnd_a and ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_enaAnd_b;
--reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1(REG,271)@6
reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q <= r_uid172_lzcZ_uid56_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem(DUALMEM,549)
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_reset0 <= areset;
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_ia <= reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q;
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_aa <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdreg_q;
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_ab <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdmux_q;
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 6,
widthad_a => 3,
numwords_a => 7,
width_b => 6,
widthad_b => 3,
numwords_b => 7,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_iq,
address_a => ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_aa,
data_a => ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_ia
);
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_q <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_iq(5 downto 0);
--cstBiasM1_uid11_fpCosPiTest(CONSTANT,10)
cstBiasM1_uid11_fpCosPiTest_q <= "01111110";
--expHardCase_uid59_fpCosPiTest(SUB,58)@15
expHardCase_uid59_fpCosPiTest_a <= STD_LOGIC_VECTOR("0" & cstBiasM1_uid11_fpCosPiTest_q);
expHardCase_uid59_fpCosPiTest_b <= STD_LOGIC_VECTOR("000" & ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_q);
expHardCase_uid59_fpCosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expHardCase_uid59_fpCosPiTest_a) - UNSIGNED(expHardCase_uid59_fpCosPiTest_b));
expHardCase_uid59_fpCosPiTest_q <= expHardCase_uid59_fpCosPiTest_o(8 downto 0);
--expP_uid60_fpCosPiTest(BITSELECT,59)@15
expP_uid60_fpCosPiTest_in <= expHardCase_uid59_fpCosPiTest_q(7 downto 0);
expP_uid60_fpCosPiTest_b <= expP_uid60_fpCosPiTest_in(7 downto 0);
--reg_expP_uid60_fpCosPiTest_0_to_expFracPreRnd_uid71_uid71_fpCosPiTest_1(REG,272)@15
reg_expP_uid60_fpCosPiTest_0_to_expFracPreRnd_uid71_uid71_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expP_uid60_fpCosPiTest_0_to_expFracPreRnd_uid71_uid71_fpCosPiTest_1_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expP_uid60_fpCosPiTest_0_to_expFracPreRnd_uid71_uid71_fpCosPiTest_1_q <= expP_uid60_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--highRes_uid68_fpCosPiTest(BITSELECT,67)@16
highRes_uid68_fpCosPiTest_in <= prodXYTruncFR_uid224_mul2xSinRes_uid66_fpCosPiTest_b(24 downto 0);
highRes_uid68_fpCosPiTest_b <= highRes_uid68_fpCosPiTest_in(24 downto 1);
--lowRes_uid69_fpCosPiTest(BITSELECT,68)@16
lowRes_uid69_fpCosPiTest_in <= prodXYTruncFR_uid224_mul2xSinRes_uid66_fpCosPiTest_b(23 downto 0);
lowRes_uid69_fpCosPiTest_b <= lowRes_uid69_fpCosPiTest_in(23 downto 0);
--fracRCompPreRnd_uid70_fpCosPiTest(MUX,69)@16
fracRCompPreRnd_uid70_fpCosPiTest_s <= normBit_uid67_fpCosPiTest_b;
fracRCompPreRnd_uid70_fpCosPiTest: PROCESS (fracRCompPreRnd_uid70_fpCosPiTest_s, en, lowRes_uid69_fpCosPiTest_b, highRes_uid68_fpCosPiTest_b)
BEGIN
CASE fracRCompPreRnd_uid70_fpCosPiTest_s IS
WHEN "0" => fracRCompPreRnd_uid70_fpCosPiTest_q <= lowRes_uid69_fpCosPiTest_b;
WHEN "1" => fracRCompPreRnd_uid70_fpCosPiTest_q <= highRes_uid68_fpCosPiTest_b;
WHEN OTHERS => fracRCompPreRnd_uid70_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--expFracPreRnd_uid71_uid71_fpCosPiTest(BITJOIN,70)@16
expFracPreRnd_uid71_uid71_fpCosPiTest_q <= reg_expP_uid60_fpCosPiTest_0_to_expFracPreRnd_uid71_uid71_fpCosPiTest_1_q & fracRCompPreRnd_uid70_fpCosPiTest_q;
--expFracComp_uid74_fpCosPiTest(ADD,73)@16
expFracComp_uid74_fpCosPiTest_a <= STD_LOGIC_VECTOR("0" & expFracPreRnd_uid71_uid71_fpCosPiTest_q);
expFracComp_uid74_fpCosPiTest_b <= STD_LOGIC_VECTOR("00000000" & rndExpUpdate_uid72_uid73_fpCosPiTest_q);
expFracComp_uid74_fpCosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expFracComp_uid74_fpCosPiTest_a) + UNSIGNED(expFracComp_uid74_fpCosPiTest_b));
expFracComp_uid74_fpCosPiTest_q <= expFracComp_uid74_fpCosPiTest_o(32 downto 0);
--expRComp_uid76_fpCosPiTest(BITSELECT,75)@16
expRComp_uid76_fpCosPiTest_in <= expFracComp_uid74_fpCosPiTest_q(31 downto 0);
expRComp_uid76_fpCosPiTest_b <= expRComp_uid76_fpCosPiTest_in(31 downto 24);
--fracXIsZero_uid27_fpCosPiTest(LOGICAL,26)@0
fracXIsZero_uid27_fpCosPiTest_a <= fracX_uid7_fpCosPiTest_b;
fracXIsZero_uid27_fpCosPiTest_b <= cstAllZWF_uid9_fpCosPiTest_q;
fracXIsZero_uid27_fpCosPiTest_q <= "1" when fracXIsZero_uid27_fpCosPiTest_a = fracXIsZero_uid27_fpCosPiTest_b else "0";
--InvFracXIsZero_uid29_fpCosPiTest(LOGICAL,28)@0
InvFracXIsZero_uid29_fpCosPiTest_a <= fracXIsZero_uid27_fpCosPiTest_q;
InvFracXIsZero_uid29_fpCosPiTest_q <= not InvFracXIsZero_uid29_fpCosPiTest_a;
--expXIsMax_uid25_fpCosPiTest(LOGICAL,24)@0
expXIsMax_uid25_fpCosPiTest_a <= expX_uid6_fpCosPiTest_b;
expXIsMax_uid25_fpCosPiTest_b <= cstAllOWE_uid8_fpCosPiTest_q;
expXIsMax_uid25_fpCosPiTest_q <= "1" when expXIsMax_uid25_fpCosPiTest_a = expXIsMax_uid25_fpCosPiTest_b else "0";
--exc_N_uid30_fpCosPiTest(LOGICAL,29)@0
exc_N_uid30_fpCosPiTest_a <= expXIsMax_uid25_fpCosPiTest_q;
exc_N_uid30_fpCosPiTest_b <= InvFracXIsZero_uid29_fpCosPiTest_q;
exc_N_uid30_fpCosPiTest_q <= exc_N_uid30_fpCosPiTest_a and exc_N_uid30_fpCosPiTest_b;
--InvExc_N_uid31_fpCosPiTest(LOGICAL,30)@0
InvExc_N_uid31_fpCosPiTest_a <= exc_N_uid30_fpCosPiTest_q;
InvExc_N_uid31_fpCosPiTest_q <= not InvExc_N_uid31_fpCosPiTest_a;
--exc_I_uid28_fpCosPiTest(LOGICAL,27)@0
exc_I_uid28_fpCosPiTest_a <= expXIsMax_uid25_fpCosPiTest_q;
exc_I_uid28_fpCosPiTest_b <= fracXIsZero_uid27_fpCosPiTest_q;
exc_I_uid28_fpCosPiTest_q <= exc_I_uid28_fpCosPiTest_a and exc_I_uid28_fpCosPiTest_b;
--InvExc_I_uid32_fpCosPiTest(LOGICAL,31)@0
InvExc_I_uid32_fpCosPiTest_a <= exc_I_uid28_fpCosPiTest_q;
InvExc_I_uid32_fpCosPiTest_q <= not InvExc_I_uid32_fpCosPiTest_a;
--expXIsZero_uid23_fpCosPiTest(LOGICAL,22)@0
expXIsZero_uid23_fpCosPiTest_a <= expX_uid6_fpCosPiTest_b;
expXIsZero_uid23_fpCosPiTest_b <= cstAllZWE_uid21_fpCosPiTest_q;
expXIsZero_uid23_fpCosPiTest_q <= "1" when expXIsZero_uid23_fpCosPiTest_a = expXIsZero_uid23_fpCosPiTest_b else "0";
--InvExpXIsZero_uid33_fpCosPiTest(LOGICAL,32)@0
InvExpXIsZero_uid33_fpCosPiTest_a <= expXIsZero_uid23_fpCosPiTest_q;
InvExpXIsZero_uid33_fpCosPiTest_q <= not InvExpXIsZero_uid33_fpCosPiTest_a;
--exc_R_uid34_fpCosPiTest(LOGICAL,33)@0
exc_R_uid34_fpCosPiTest_a <= InvExpXIsZero_uid33_fpCosPiTest_q;
exc_R_uid34_fpCosPiTest_b <= InvExc_I_uid32_fpCosPiTest_q;
exc_R_uid34_fpCosPiTest_c <= InvExc_N_uid31_fpCosPiTest_q;
exc_R_uid34_fpCosPiTest_q <= exc_R_uid34_fpCosPiTest_a and exc_R_uid34_fpCosPiTest_b and exc_R_uid34_fpCosPiTest_c;
--ld_exc_R_uid34_fpCosPiTest_q_to_xIsInt_uid80_fpCosPiTest_a(DELAY,337)@0
ld_exc_R_uid34_fpCosPiTest_q_to_xIsInt_uid80_fpCosPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => exc_R_uid34_fpCosPiTest_q, xout => ld_exc_R_uid34_fpCosPiTest_q_to_xIsInt_uid80_fpCosPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--xIsHalf_uid83_fpCosPiTest(LOGICAL,82)@2
xIsHalf_uid83_fpCosPiTest_a <= ld_exc_R_uid34_fpCosPiTest_q_to_xIsInt_uid80_fpCosPiTest_a_q;
xIsHalf_uid83_fpCosPiTest_b <= fxpXFracHalf_uid46_fpCosPiTest_q;
xIsHalf_uid83_fpCosPiTest_c <= InvCosXIsOne_uid77_fpCosPiTest_q;
xIsHalf_uid83_fpCosPiTest_d <= InvXEvenInt_uid81_fpCosPiTest_q;
xIsHalf_uid83_fpCosPiTest_q <= xIsHalf_uid83_fpCosPiTest_a and xIsHalf_uid83_fpCosPiTest_b and xIsHalf_uid83_fpCosPiTest_c and xIsHalf_uid83_fpCosPiTest_d;
--ld_xIsHalf_uid83_fpCosPiTest_q_to_expRPostExc1_uid91_fpCosPiTest_b(DELAY,355)@2
ld_xIsHalf_uid83_fpCosPiTest_q_to_expRPostExc1_uid91_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 14 )
PORT MAP ( xin => xIsHalf_uid83_fpCosPiTest_q, xout => ld_xIsHalf_uid83_fpCosPiTest_q_to_expRPostExc1_uid91_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--expRPostExc1_uid91_fpCosPiTest(MUX,90)@16
expRPostExc1_uid91_fpCosPiTest_s <= ld_xIsHalf_uid83_fpCosPiTest_q_to_expRPostExc1_uid91_fpCosPiTest_b_q;
expRPostExc1_uid91_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expRPostExc1_uid91_fpCosPiTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE expRPostExc1_uid91_fpCosPiTest_s IS
WHEN "0" => expRPostExc1_uid91_fpCosPiTest_q <= expRComp_uid76_fpCosPiTest_b;
WHEN "1" => expRPostExc1_uid91_fpCosPiTest_q <= cstAllZWE_uid21_fpCosPiTest_q;
WHEN OTHERS => expRPostExc1_uid91_fpCosPiTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_nor(LOGICAL,570)
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_nor_a <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_notEnable_q;
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_nor_b <= ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_sticky_ena_q;
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_nor_q <= not (ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_nor_a or ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_nor_b);
--ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_mem_top(CONSTANT,566)
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_mem_top_q <= "01100";
--ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_cmp(LOGICAL,567)
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_cmp_a <= ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_mem_top_q;
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdmux_q);
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_cmp_q <= "1" when ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_cmp_a = ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_cmp_b else "0";
--ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_cmpReg(REG,568)
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_cmpReg_q <= ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_sticky_ena(REG,571)
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_nor_q = "1") THEN
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_sticky_ena_q <= ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_enaAnd(LOGICAL,572)
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_enaAnd_a <= ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_sticky_ena_q;
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_enaAnd_b <= en;
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_enaAnd_q <= ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_enaAnd_a and ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_enaAnd_b;
--ld_expXIsZero_uid23_fpCosPiTest_q_to_xIntOrXZOrCosOne_uid93_fpCosPiTest_b(DELAY,359)@0
ld_expXIsZero_uid23_fpCosPiTest_q_to_xIntOrXZOrCosOne_uid93_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => expXIsZero_uid23_fpCosPiTest_q, xout => ld_expXIsZero_uid23_fpCosPiTest_q_to_xIntOrXZOrCosOne_uid93_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--fxpXFracZero_uid45_fpCosPiTest(LOGICAL,44)@2
fxpXFracZero_uid45_fpCosPiTest_a <= reg_fxpXFrac_uid43_fpCosPiTest_0_to_fxpXFracZero_uid45_fpCosPiTest_1_q;
fxpXFracZero_uid45_fpCosPiTest_b <= STD_LOGIC_VECTOR("0" & cstZwSwF_uid15_fpCosPiTest_q);
fxpXFracZero_uid45_fpCosPiTest_q <= "1" when fxpXFracZero_uid45_fpCosPiTest_a = fxpXFracZero_uid45_fpCosPiTest_b else "0";
--fracZCosNotOne_uid78_fpCosPiTest(LOGICAL,77)@2
fracZCosNotOne_uid78_fpCosPiTest_a <= fxpXFracZero_uid45_fpCosPiTest_q;
fracZCosNotOne_uid78_fpCosPiTest_b <= InvCosXIsOne_uid77_fpCosPiTest_q;
fracZCosNotOne_uid78_fpCosPiTest_q <= fracZCosNotOne_uid78_fpCosPiTest_a and fracZCosNotOne_uid78_fpCosPiTest_b;
--evenIntCosNotOneFZ_uid79_fpCosPiTest(LOGICAL,78)@2
evenIntCosNotOneFZ_uid79_fpCosPiTest_a <= ld_xEvenInt_uid35_fpCosPiTest_c_to_evenIntCosNotOneFZ_uid79_fpCosPiTest_a_q;
evenIntCosNotOneFZ_uid79_fpCosPiTest_b <= fracZCosNotOne_uid78_fpCosPiTest_q;
evenIntCosNotOneFZ_uid79_fpCosPiTest_q <= evenIntCosNotOneFZ_uid79_fpCosPiTest_a or evenIntCosNotOneFZ_uid79_fpCosPiTest_b;
--xIsInt_uid80_fpCosPiTest(LOGICAL,79)@2
xIsInt_uid80_fpCosPiTest_a <= ld_exc_R_uid34_fpCosPiTest_q_to_xIsInt_uid80_fpCosPiTest_a_q;
xIsInt_uid80_fpCosPiTest_b <= evenIntCosNotOneFZ_uid79_fpCosPiTest_q;
xIsInt_uid80_fpCosPiTest_q <= xIsInt_uid80_fpCosPiTest_a and xIsInt_uid80_fpCosPiTest_b;
--xIntOrXZOrCosOne_uid93_fpCosPiTest(LOGICAL,92)@2
xIntOrXZOrCosOne_uid93_fpCosPiTest_a <= xIsInt_uid80_fpCosPiTest_q;
xIntOrXZOrCosOne_uid93_fpCosPiTest_b <= ld_expXIsZero_uid23_fpCosPiTest_q_to_xIntOrXZOrCosOne_uid93_fpCosPiTest_b_q;
xIntOrXZOrCosOne_uid93_fpCosPiTest_c <= ld_cosXIsOne_uid36_fpCosPiTest_c_to_InvCosXIsOne_uid77_fpCosPiTest_a_q;
xIntOrXZOrCosOne_uid93_fpCosPiTest_q <= xIntOrXZOrCosOne_uid93_fpCosPiTest_a or xIntOrXZOrCosOne_uid93_fpCosPiTest_b or xIntOrXZOrCosOne_uid93_fpCosPiTest_c;
--excRNaN_uid84_fpCosPiTest(LOGICAL,83)@0
excRNaN_uid84_fpCosPiTest_a <= exc_N_uid30_fpCosPiTest_q;
excRNaN_uid84_fpCosPiTest_b <= exc_I_uid28_fpCosPiTest_q;
excRNaN_uid84_fpCosPiTest_q <= excRNaN_uid84_fpCosPiTest_a or excRNaN_uid84_fpCosPiTest_b;
--rInfOrNaN_uid92_fpCosPiTest(LOGICAL,91)@0
rInfOrNaN_uid92_fpCosPiTest_a <= GND_q;
rInfOrNaN_uid92_fpCosPiTest_b <= excRNaN_uid84_fpCosPiTest_q;
rInfOrNaN_uid92_fpCosPiTest_q <= rInfOrNaN_uid92_fpCosPiTest_a or rInfOrNaN_uid92_fpCosPiTest_b;
--ld_rInfOrNaN_uid92_fpCosPiTest_q_to_join_uid94_fpCosPiTest_a(DELAY,361)@0
ld_rInfOrNaN_uid92_fpCosPiTest_q_to_join_uid94_fpCosPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => rInfOrNaN_uid92_fpCosPiTest_q, xout => ld_rInfOrNaN_uid92_fpCosPiTest_q_to_join_uid94_fpCosPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--join_uid94_fpCosPiTest(BITJOIN,93)@2
join_uid94_fpCosPiTest_q <= xIntOrXZOrCosOne_uid93_fpCosPiTest_q & ld_rInfOrNaN_uid92_fpCosPiTest_q_to_join_uid94_fpCosPiTest_a_q;
--reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1(REG,274)@2
reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q <= join_uid94_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt(COUNTER,562)
-- every=1, low=0, high=12, step=1, init=1
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt_i = 11 THEN
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt_eq <= '1';
ELSE
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt_eq = '1') THEN
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt_i <= ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt_i - 12;
ELSE
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt_i <= ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt_i,4));
--ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdreg(REG,563)
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdreg_q <= ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdmux(MUX,564)
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdmux_s <= en;
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdmux: PROCESS (ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdmux_s, ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdreg_q, ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt_q)
BEGIN
CASE ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdmux_s IS
WHEN "0" => ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdmux_q <= ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdreg_q;
WHEN "1" => ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdmux_q <= ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem(DUALMEM,561)
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_reset0 <= areset;
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_ia <= reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q;
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_aa <= ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdreg_q;
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_ab <= ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdmux_q;
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 2,
widthad_a => 4,
numwords_a => 13,
width_b => 2,
widthad_b => 4,
numwords_b => 13,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_iq,
address_a => ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_aa,
data_a => ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_ia
);
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_q <= ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_iq(1 downto 0);
--expRPostExc_uid95_fpCosPiTest(MUX,94)@17
expRPostExc_uid95_fpCosPiTest_s <= ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_q;
expRPostExc_uid95_fpCosPiTest: PROCESS (expRPostExc_uid95_fpCosPiTest_s, en, expRPostExc1_uid91_fpCosPiTest_q, cstAllOWE_uid8_fpCosPiTest_q, cstBias_uid10_fpCosPiTest_q, cstBias_uid10_fpCosPiTest_q)
BEGIN
CASE expRPostExc_uid95_fpCosPiTest_s IS
WHEN "00" => expRPostExc_uid95_fpCosPiTest_q <= expRPostExc1_uid91_fpCosPiTest_q;
WHEN "01" => expRPostExc_uid95_fpCosPiTest_q <= cstAllOWE_uid8_fpCosPiTest_q;
WHEN "10" => expRPostExc_uid95_fpCosPiTest_q <= cstBias_uid10_fpCosPiTest_q;
WHEN "11" => expRPostExc_uid95_fpCosPiTest_q <= cstBias_uid10_fpCosPiTest_q;
WHEN OTHERS => expRPostExc_uid95_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--oneFracRPostExc2_uid87_fpCosPiTest(CONSTANT,86)
oneFracRPostExc2_uid87_fpCosPiTest_q <= "00000000000000000000001";
--fracRComp_uid75_fpCosPiTest(BITSELECT,74)@16
fracRComp_uid75_fpCosPiTest_in <= expFracComp_uid74_fpCosPiTest_q(23 downto 0);
fracRComp_uid75_fpCosPiTest_b <= fracRComp_uid75_fpCosPiTest_in(23 downto 1);
--reg_xIsHalf_uid83_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_5(REG,243)@2
reg_xIsHalf_uid83_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xIsHalf_uid83_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_5_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xIsHalf_uid83_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_5_q <= xIsHalf_uid83_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--reg_expXIsZero_uid23_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_4(REG,242)@2
reg_expXIsZero_uid23_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expXIsZero_uid23_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_4_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expXIsZero_uid23_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_4_q <= ld_expXIsZero_uid23_fpCosPiTest_q_to_xIntOrXZOrCosOne_uid93_fpCosPiTest_b_q;
END IF;
END IF;
END PROCESS;
--reg_fxpXFracHalf_uid46_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_3(REG,241)@2
reg_fxpXFracHalf_uid46_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fxpXFracHalf_uid46_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_3_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fxpXFracHalf_uid46_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_3_q <= fxpXFracHalf_uid46_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--reg_xIsInt_uid80_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_2(REG,240)@2
reg_xIsInt_uid80_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xIsInt_uid80_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xIsInt_uid80_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_2_q <= xIsInt_uid80_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--reg_cosXIsOne_uid36_fpCosPiTest_1_to_bigCond_uid85_fpCosPiTest_1(REG,239)@0
reg_cosXIsOne_uid36_fpCosPiTest_1_to_bigCond_uid85_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cosXIsOne_uid36_fpCosPiTest_1_to_bigCond_uid85_fpCosPiTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cosXIsOne_uid36_fpCosPiTest_1_to_bigCond_uid85_fpCosPiTest_1_q <= cosXIsOne_uid36_fpCosPiTest_c;
END IF;
END IF;
END PROCESS;
--ld_reg_cosXIsOne_uid36_fpCosPiTest_1_to_bigCond_uid85_fpCosPiTest_1_q_to_bigCond_uid85_fpCosPiTest_a(DELAY,346)@1
ld_reg_cosXIsOne_uid36_fpCosPiTest_1_to_bigCond_uid85_fpCosPiTest_1_q_to_bigCond_uid85_fpCosPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => reg_cosXIsOne_uid36_fpCosPiTest_1_to_bigCond_uid85_fpCosPiTest_1_q, xout => ld_reg_cosXIsOne_uid36_fpCosPiTest_1_to_bigCond_uid85_fpCosPiTest_1_q_to_bigCond_uid85_fpCosPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--bigCond_uid85_fpCosPiTest(LOGICAL,84)@3
bigCond_uid85_fpCosPiTest_a <= ld_reg_cosXIsOne_uid36_fpCosPiTest_1_to_bigCond_uid85_fpCosPiTest_1_q_to_bigCond_uid85_fpCosPiTest_a_q;
bigCond_uid85_fpCosPiTest_b <= reg_xIsInt_uid80_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_2_q;
bigCond_uid85_fpCosPiTest_c <= reg_fxpXFracHalf_uid46_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_3_q;
bigCond_uid85_fpCosPiTest_d <= reg_expXIsZero_uid23_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_4_q;
bigCond_uid85_fpCosPiTest_f <= reg_xIsHalf_uid83_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_5_q;
bigCond_uid85_fpCosPiTest_g <= GND_q;
bigCond_uid85_fpCosPiTest_q <= bigCond_uid85_fpCosPiTest_a or bigCond_uid85_fpCosPiTest_b or bigCond_uid85_fpCosPiTest_c or bigCond_uid85_fpCosPiTest_d or bigCond_uid85_fpCosPiTest_f or bigCond_uid85_fpCosPiTest_g;
--ld_bigCond_uid85_fpCosPiTest_q_to_fracRPostExc1_uid86_fpCosPiTest_b(DELAY,351)@3
ld_bigCond_uid85_fpCosPiTest_q_to_fracRPostExc1_uid86_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 13 )
PORT MAP ( xin => bigCond_uid85_fpCosPiTest_q, xout => ld_bigCond_uid85_fpCosPiTest_q_to_fracRPostExc1_uid86_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--fracRPostExc1_uid86_fpCosPiTest(MUX,85)@16
fracRPostExc1_uid86_fpCosPiTest_s <= ld_bigCond_uid85_fpCosPiTest_q_to_fracRPostExc1_uid86_fpCosPiTest_b_q;
fracRPostExc1_uid86_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
fracRPostExc1_uid86_fpCosPiTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE fracRPostExc1_uid86_fpCosPiTest_s IS
WHEN "0" => fracRPostExc1_uid86_fpCosPiTest_q <= fracRComp_uid75_fpCosPiTest_b;
WHEN "1" => fracRPostExc1_uid86_fpCosPiTest_q <= cstAllZWF_uid9_fpCosPiTest_q;
WHEN OTHERS => fracRPostExc1_uid86_fpCosPiTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--reg_excRNaN_uid84_fpCosPiTest_0_to_fracRPostExc_uid88_fpCosPiTest_1(REG,273)@0
reg_excRNaN_uid84_fpCosPiTest_0_to_fracRPostExc_uid88_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_excRNaN_uid84_fpCosPiTest_0_to_fracRPostExc_uid88_fpCosPiTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_excRNaN_uid84_fpCosPiTest_0_to_fracRPostExc_uid88_fpCosPiTest_1_q <= excRNaN_uid84_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_excRNaN_uid84_fpCosPiTest_0_to_fracRPostExc_uid88_fpCosPiTest_1_q_to_fracRPostExc_uid88_fpCosPiTest_b(DELAY,353)@1
ld_reg_excRNaN_uid84_fpCosPiTest_0_to_fracRPostExc_uid88_fpCosPiTest_1_q_to_fracRPostExc_uid88_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 16 )
PORT MAP ( xin => reg_excRNaN_uid84_fpCosPiTest_0_to_fracRPostExc_uid88_fpCosPiTest_1_q, xout => ld_reg_excRNaN_uid84_fpCosPiTest_0_to_fracRPostExc_uid88_fpCosPiTest_1_q_to_fracRPostExc_uid88_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--fracRPostExc_uid88_fpCosPiTest(MUX,87)@17
fracRPostExc_uid88_fpCosPiTest_s <= ld_reg_excRNaN_uid84_fpCosPiTest_0_to_fracRPostExc_uid88_fpCosPiTest_1_q_to_fracRPostExc_uid88_fpCosPiTest_b_q;
fracRPostExc_uid88_fpCosPiTest: PROCESS (fracRPostExc_uid88_fpCosPiTest_s, en, fracRPostExc1_uid86_fpCosPiTest_q, oneFracRPostExc2_uid87_fpCosPiTest_q)
BEGIN
CASE fracRPostExc_uid88_fpCosPiTest_s IS
WHEN "0" => fracRPostExc_uid88_fpCosPiTest_q <= fracRPostExc1_uid86_fpCosPiTest_q;
WHEN "1" => fracRPostExc_uid88_fpCosPiTest_q <= oneFracRPostExc2_uid87_fpCosPiTest_q;
WHEN OTHERS => fracRPostExc_uid88_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--R_uid102_fpCosPiTest(BITJOIN,101)@17
R_uid102_fpCosPiTest_q <= ld_signR_uid101_fpCosPiTest_q_to_R_uid102_fpCosPiTest_c_q & expRPostExc_uid95_fpCosPiTest_q & fracRPostExc_uid88_fpCosPiTest_q;
--xOut(GPOUT,4)@17
q <= R_uid102_fpCosPiTest_q;
end normal;
|
-----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Release Version 13.1
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing device programming or simulation files), and
-- any associated documentation or information are expressly subject to the
-- terms and conditions of the Altera Program License Subscription Agreement,
-- Altera MegaCore Function License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for the sole
-- purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
-----------------------------------------------------------------------------
-- VHDL created from fp_cospi_s5
-- VHDL created on Wed Feb 27 15:22:33 2013
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.all;
use std.TextIO.all;
use work.dspba_library_package.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
entity fp_cospi_s5 is
port (
a : in std_logic_vector(31 downto 0);
en : in std_logic_vector(0 downto 0);
q : out std_logic_vector(31 downto 0);
clk : in std_logic;
areset : in std_logic
);
end;
architecture normal of fp_cospi_s5 is
attribute altera_attribute : string;
attribute altera_attribute of normal : architecture is "-name NOT_GATE_PUSH_BACK OFF; -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON; -name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410";
signal GND_q : std_logic_vector (0 downto 0);
signal VCC_q : std_logic_vector (0 downto 0);
signal cstAllOWE_uid8_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal cstAllZWF_uid9_fpCosPiTest_q : std_logic_vector (22 downto 0);
signal cstBias_uid10_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal cstBiasM1_uid11_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal cstBiasPwF_uid12_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal biasMwShiftMO_uid13_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal cst01pWShift_uid14_fpCosPiTest_q : std_logic_vector (12 downto 0);
signal cstZwSwF_uid15_fpCosPiTest_q : std_logic_vector (34 downto 0);
signal cstAllZWE_uid21_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal rangeReducedFxPX_uid51_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal rangeReducedFxPX_uid51_fpCosPiTest_q : std_logic_vector (35 downto 0);
signal fracRPostExc1_uid86_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal fracRPostExc1_uid86_fpCosPiTest_q : std_logic_vector (22 downto 0);
signal oneFracRPostExc2_uid87_fpCosPiTest_q : std_logic_vector (22 downto 0);
signal expRPostExc1_uid91_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal expRPostExc1_uid91_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal signRComp_uid99_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal signRComp_uid99_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal signRComp_uid99_fpCosPiTest_c : std_logic_vector(0 downto 0);
signal signRComp_uid99_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal signR_uid101_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal signR_uid101_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal signR_uid101_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal leftShiftStage0Idx1Pad16_uid105_fxpX_uid41_fpCosPiTest_q : std_logic_vector (15 downto 0);
signal leftShiftStage0Idx2Pad32_uid108_fxpX_uid41_fpCosPiTest_q : std_logic_vector (31 downto 0);
signal leftShiftStage0Idx3_uid111_fxpX_uid41_fpCosPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage1Idx1Pad4_uid114_fxpX_uid41_fpCosPiTest_q : std_logic_vector (3 downto 0);
signal leftShiftStage1Idx3Pad12_uid120_fxpX_uid41_fpCosPiTest_q : std_logic_vector (11 downto 0);
signal leftShiftStage2Idx2Pad2_uid128_fxpX_uid41_fpCosPiTest_q : std_logic_vector (1 downto 0);
signal leftShiftStage2Idx3Pad3_uid131_fxpX_uid41_fpCosPiTest_q : std_logic_vector (2 downto 0);
signal mO_uid140_lzcZ_uid56_fpCosPiTest_q : std_logic_vector (28 downto 0);
signal memoryC2_uid209_sinPiZTableGenerator_q : std_logic_vector(13 downto 0);
signal prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_a : std_logic_vector (23 downto 0);
signal prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_b : std_logic_vector (24 downto 0);
signal prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_s1 : std_logic_vector (48 downto 0);
signal prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_pr : UNSIGNED (48 downto 0);
signal prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_q : std_logic_vector (48 downto 0);
signal prodXY_uid226_pT1_uid211_sinPiZPolyEval_a : std_logic_vector (13 downto 0);
signal prodXY_uid226_pT1_uid211_sinPiZPolyEval_b : std_logic_vector (13 downto 0);
signal prodXY_uid226_pT1_uid211_sinPiZPolyEval_s1 : std_logic_vector (27 downto 0);
signal prodXY_uid226_pT1_uid211_sinPiZPolyEval_pr : SIGNED (28 downto 0);
signal prodXY_uid226_pT1_uid211_sinPiZPolyEval_q : std_logic_vector (27 downto 0);
signal prodXY_uid229_pT2_uid217_sinPiZPolyEval_a : std_logic_vector (15 downto 0);
signal prodXY_uid229_pT2_uid217_sinPiZPolyEval_b : std_logic_vector (22 downto 0);
signal prodXY_uid229_pT2_uid217_sinPiZPolyEval_s1 : std_logic_vector (38 downto 0);
signal prodXY_uid229_pT2_uid217_sinPiZPolyEval_pr : SIGNED (39 downto 0);
signal prodXY_uid229_pT2_uid217_sinPiZPolyEval_q : std_logic_vector (38 downto 0);
signal reg_leftShiftStageSel3Dto2_uid123_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_2_q : std_logic_vector (36 downto 0);
signal reg_leftShiftStage1Idx1_uid116_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_3_q : std_logic_vector (36 downto 0);
signal reg_leftShiftStage1Idx2_uid119_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_4_q : std_logic_vector (36 downto 0);
signal reg_leftShiftStage1Idx3_uid122_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_5_q : std_logic_vector (36 downto 0);
signal reg_leftShiftStageSel1Dto0_uid134_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_fxpXFrac_uid43_fpCosPiTest_0_to_fxpXFracZero_uid45_fpCosPiTest_1_q : std_logic_vector (35 downto 0);
signal reg_cosXIsOne_uid36_fpCosPiTest_1_to_bigCond_uid85_fpCosPiTest_1_q : std_logic_vector (0 downto 0);
signal reg_xIsInt_uid80_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_2_q : std_logic_vector (0 downto 0);
signal reg_fxpXFracHalf_uid46_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_3_q : std_logic_vector (0 downto 0);
signal reg_expXIsZero_uid23_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_4_q : std_logic_vector (0 downto 0);
signal reg_xIsHalf_uid83_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_5_q : std_logic_vector (0 downto 0);
signal reg_pad_o_uid16_uid47_fpCosPiTest_0_to_oMFxpXFrac_uid47_fpCosPiTest_0_q : std_logic_vector (36 downto 0);
signal reg_pad_half_uid17_uid52_fpCosPiTest_0_to_z_halfMRRFxPXE_uid52_fpCosPiTest_0_q : std_logic_vector (35 downto 0);
signal reg_rVStage_uid138_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid139_lzcZ_uid56_fpCosPiTest_1_q : std_logic_vector (31 downto 0);
signal reg_cStage_uid142_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid144_lzcZ_uid56_fpCosPiTest_3_q : std_logic_vector (31 downto 0);
signal reg_rVStage_uid146_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid147_lzcZ_uid56_fpCosPiTest_1_q : std_logic_vector (15 downto 0);
signal reg_vStage_uid148_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid150_lzcZ_uid56_fpCosPiTest_3_q : std_logic_vector (15 downto 0);
signal reg_rVStage_uid158_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid159_lzcZ_uid56_fpCosPiTest_1_q : std_logic_vector (3 downto 0);
signal reg_vStage_uid160_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid162_lzcZ_uid56_fpCosPiTest_3_q : std_logic_vector (3 downto 0);
signal reg_vCount_uid153_lzcZ_uid56_fpCosPiTest_0_to_r_uid172_lzcZ_uid56_fpCosPiTest_3_q : std_logic_vector (0 downto 0);
signal reg_leftShiftStageSel3Dto2_uid193_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_2_q : std_logic_vector (34 downto 0);
signal reg_leftShiftStage1Idx1_uid186_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_3_q : std_logic_vector (34 downto 0);
signal reg_leftShiftStage1Idx2_uid189_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_4_q : std_logic_vector (34 downto 0);
signal reg_leftShiftStage1Idx3_uid192_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_5_q : std_logic_vector (34 downto 0);
signal reg_leftShiftStageSel1Dto0_uid204_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_zAddr_uid62_fpCosPiTest_0_to_memoryC2_uid209_sinPiZTableGenerator_0_q : std_logic_vector (6 downto 0);
signal reg_yT1_uid210_sinPiZPolyEval_0_to_prodXY_uid226_pT1_uid211_sinPiZPolyEval_0_q : std_logic_vector (13 downto 0);
signal reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_q : std_logic_vector (15 downto 0);
signal reg_s1_uid212_uid215_sinPiZPolyEval_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_1_q : std_logic_vector (22 downto 0);
signal reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_q : std_logic_vector (23 downto 0);
signal reg_fxpSinRes_uid65_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_1_q : std_logic_vector (24 downto 0);
signal reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q : std_logic_vector (5 downto 0);
signal reg_expP_uid60_fpCosPiTest_0_to_expFracPreRnd_uid71_uid71_fpCosPiTest_1_q : std_logic_vector (7 downto 0);
signal reg_excRNaN_uid84_fpCosPiTest_0_to_fracRPostExc_uid88_fpCosPiTest_1_q : std_logic_vector (0 downto 0);
signal reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q : std_logic_vector (1 downto 0);
signal ld_FxpXFrac35_uid44_fpCosPiTest_b_to_rangeReducedFxPX_uid51_fpCosPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_fxpXFrac_uid43_fpCosPiTest_b_to_rangeReducedFxPX_uid51_fpCosPiTest_c_q : std_logic_vector (35 downto 0);
signal ld_cosXIsOne_uid36_fpCosPiTest_c_to_InvCosXIsOne_uid77_fpCosPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_xEvenInt_uid35_fpCosPiTest_c_to_evenIntCosNotOneFZ_uid79_fpCosPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_exc_R_uid34_fpCosPiTest_q_to_xIsInt_uid80_fpCosPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_reg_cosXIsOne_uid36_fpCosPiTest_1_to_bigCond_uid85_fpCosPiTest_1_q_to_bigCond_uid85_fpCosPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_bigCond_uid85_fpCosPiTest_q_to_fracRPostExc1_uid86_fpCosPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_reg_excRNaN_uid84_fpCosPiTest_0_to_fracRPostExc_uid88_fpCosPiTest_1_q_to_fracRPostExc_uid88_fpCosPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_xIsHalf_uid83_fpCosPiTest_q_to_expRPostExc1_uid91_fpCosPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_expXIsZero_uid23_fpCosPiTest_q_to_xIntOrXZOrCosOne_uid93_fpCosPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_rInfOrNaN_uid92_fpCosPiTest_q_to_join_uid94_fpCosPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_xParityXorHalfParity_uid96_fpCosPiTest_q_to_signRComp_uid99_fpCosPiTest_c_q : std_logic_vector (0 downto 0);
signal ld_fxpXFracHalf_uid46_fpCosPiTest_q_to_InvFxpXFracHalf_uid100_fpCosPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_signR_uid101_fpCosPiTest_q_to_R_uid102_fpCosPiTest_c_q : std_logic_vector (0 downto 0);
signal ld_vCount_uid147_lzcZ_uid56_fpCosPiTest_q_to_r_uid172_lzcZ_uid56_fpCosPiTest_e_q : std_logic_vector (0 downto 0);
signal ld_vCount_uid139_lzcZ_uid56_fpCosPiTest_q_to_r_uid172_lzcZ_uid56_fpCosPiTest_f_q : std_logic_vector (0 downto 0);
signal ld_X18dto0_uid176_alignedZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx1_uid177_alignedZ_uid57_fpCosPiTest_b_q : std_logic_vector (18 downto 0);
signal ld_vStage_uid141_lzcZ_uid56_fpCosPiTest_b_to_leftShiftStage0Idx2_uid180_alignedZ_uid57_fpCosPiTest_b_q : std_logic_vector (2 downto 0);
signal ld_z_uid54_fpCosPiTest_b_to_leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_c_q : std_logic_vector (34 downto 0);
signal ld_reg_yT1_uid210_sinPiZPolyEval_0_to_prodXY_uid226_pT1_uid211_sinPiZPolyEval_0_q_to_prodXY_uid226_pT1_uid211_sinPiZPolyEval_a_q : std_logic_vector (13 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_reset0 : std_logic;
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_ia : std_logic_vector (5 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_iq : std_logic_vector (5 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_q : std_logic_vector (5 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt_eq : std_logic;
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_mem_top_q : std_logic_vector (3 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve : boolean;
attribute preserve of ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_sticky_ena_q : signal is true;
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_reset0 : std_logic;
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_ia : std_logic_vector (1 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_iq : std_logic_vector (1 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_q : std_logic_vector (1 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt_eq : std_logic;
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_mem_top_q : std_logic_vector (4 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_sticky_ena_q : signal is true;
signal ld_X18dto0_uid176_alignedZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx1_uid177_alignedZ_uid57_fpCosPiTest_b_inputreg_q : std_logic_vector (18 downto 0);
signal ld_z_uid54_fpCosPiTest_b_to_leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_c_inputreg_q : std_logic_vector (34 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_reset0 : std_logic;
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_ia : std_logic_vector (6 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_iq : std_logic_vector (6 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_q : std_logic_vector (6 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_sticky_ena_q : signal is true;
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_reset0 : std_logic;
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_ia : std_logic_vector (6 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_aa : std_logic_vector (1 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_ab : std_logic_vector (1 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_iq : std_logic_vector (6 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_q : std_logic_vector (6 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt_q : std_logic_vector(1 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt_i : unsigned(1 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt_eq : std_logic;
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdreg_q : std_logic_vector (1 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_mem_top_q : std_logic_vector (2 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_sticky_ena_q : signal is true;
signal ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_inputreg_q : std_logic_vector (15 downto 0);
signal ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_reset0 : std_logic;
signal ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_ia : std_logic_vector (15 downto 0);
signal ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_aa : std_logic_vector (1 downto 0);
signal ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_ab : std_logic_vector (1 downto 0);
signal ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_iq : std_logic_vector (15 downto 0);
signal ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_q : std_logic_vector (15 downto 0);
signal ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_sticky_ena_q : signal is true;
signal ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_inputreg_q : std_logic_vector (23 downto 0);
signal ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_reset0 : std_logic;
signal ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_ia : std_logic_vector (23 downto 0);
signal ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_aa : std_logic_vector (1 downto 0);
signal ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_ab : std_logic_vector (1 downto 0);
signal ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_iq : std_logic_vector (23 downto 0);
signal ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_q : std_logic_vector (23 downto 0);
signal ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_sticky_ena_q : signal is true;
signal pad_o_uid16_uid47_fpCosPiTest_q : std_logic_vector (36 downto 0);
signal pad_half_uid17_uid52_fpCosPiTest_q : std_logic_vector (35 downto 0);
signal bigCond_uid85_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal bigCond_uid85_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal bigCond_uid85_fpCosPiTest_c : std_logic_vector(0 downto 0);
signal bigCond_uid85_fpCosPiTest_d : std_logic_vector(0 downto 0);
signal bigCond_uid85_fpCosPiTest_f : std_logic_vector(0 downto 0);
signal bigCond_uid85_fpCosPiTest_g : std_logic_vector(0 downto 0);
signal bigCond_uid85_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal InvCosXIsOne_uid77_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal InvCosXIsOne_uid77_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal InvXEvenInt_uid81_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal InvXEvenInt_uid81_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal InvFxpXFracHalf_uid100_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal InvFxpXFracHalf_uid100_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal cstHalfwSwFP1_uid18_fpCosPiTest_q : std_logic_vector (35 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_notEnable_a : std_logic_vector(0 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_notEnable_q : std_logic_vector(0 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdmux_q : std_logic_vector (1 downto 0);
signal expX_uid6_fpCosPiTest_in : std_logic_vector (30 downto 0);
signal expX_uid6_fpCosPiTest_b : std_logic_vector (7 downto 0);
signal fracX_uid7_fpCosPiTest_in : std_logic_vector (22 downto 0);
signal fracX_uid7_fpCosPiTest_b : std_logic_vector (22 downto 0);
signal expXIsZero_uid23_fpCosPiTest_a : std_logic_vector(7 downto 0);
signal expXIsZero_uid23_fpCosPiTest_b : std_logic_vector(7 downto 0);
signal expXIsZero_uid23_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal expXIsMax_uid25_fpCosPiTest_a : std_logic_vector(7 downto 0);
signal expXIsMax_uid25_fpCosPiTest_b : std_logic_vector(7 downto 0);
signal expXIsMax_uid25_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal fracXIsZero_uid27_fpCosPiTest_a : std_logic_vector(22 downto 0);
signal fracXIsZero_uid27_fpCosPiTest_b : std_logic_vector(22 downto 0);
signal fracXIsZero_uid27_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal exc_I_uid28_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal exc_I_uid28_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal exc_I_uid28_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal xEvenInt_uid35_fpCosPiTest_a : std_logic_vector(10 downto 0);
signal xEvenInt_uid35_fpCosPiTest_b : std_logic_vector(10 downto 0);
signal xEvenInt_uid35_fpCosPiTest_o : std_logic_vector (10 downto 0);
signal xEvenInt_uid35_fpCosPiTest_cin : std_logic_vector (0 downto 0);
signal xEvenInt_uid35_fpCosPiTest_c : std_logic_vector (0 downto 0);
signal cosXIsOne_uid36_fpCosPiTest_a : std_logic_vector(10 downto 0);
signal cosXIsOne_uid36_fpCosPiTest_b : std_logic_vector(10 downto 0);
signal cosXIsOne_uid36_fpCosPiTest_o : std_logic_vector (10 downto 0);
signal cosXIsOne_uid36_fpCosPiTest_cin : std_logic_vector (0 downto 0);
signal cosXIsOne_uid36_fpCosPiTest_c : std_logic_vector (0 downto 0);
signal shiftValFxPX_uid38_fpCosPiTest_a : std_logic_vector(8 downto 0);
signal shiftValFxPX_uid38_fpCosPiTest_b : std_logic_vector(8 downto 0);
signal shiftValFxPX_uid38_fpCosPiTest_o : std_logic_vector (8 downto 0);
signal shiftValFxPX_uid38_fpCosPiTest_q : std_logic_vector (8 downto 0);
signal fxpXFracZero_uid45_fpCosPiTest_a : std_logic_vector(35 downto 0);
signal fxpXFracZero_uid45_fpCosPiTest_b : std_logic_vector(35 downto 0);
signal fxpXFracZero_uid45_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal fxpXFracHalf_uid46_fpCosPiTest_a : std_logic_vector(35 downto 0);
signal fxpXFracHalf_uid46_fpCosPiTest_b : std_logic_vector(35 downto 0);
signal fxpXFracHalf_uid46_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal oMFxpXFrac_uid47_fpCosPiTest_a : std_logic_vector(37 downto 0);
signal oMFxpXFrac_uid47_fpCosPiTest_b : std_logic_vector(37 downto 0);
signal oMFxpXFrac_uid47_fpCosPiTest_o : std_logic_vector (37 downto 0);
signal oMFxpXFrac_uid47_fpCosPiTest_q : std_logic_vector (37 downto 0);
signal z_halfMRRFxPXE_uid52_fpCosPiTest_a : std_logic_vector(36 downto 0);
signal z_halfMRRFxPXE_uid52_fpCosPiTest_b : std_logic_vector(36 downto 0);
signal z_halfMRRFxPXE_uid52_fpCosPiTest_o : std_logic_vector (36 downto 0);
signal z_halfMRRFxPXE_uid52_fpCosPiTest_q : std_logic_vector (36 downto 0);
signal expHardCase_uid59_fpCosPiTest_a : std_logic_vector(8 downto 0);
signal expHardCase_uid59_fpCosPiTest_b : std_logic_vector(8 downto 0);
signal expHardCase_uid59_fpCosPiTest_o : std_logic_vector (8 downto 0);
signal expHardCase_uid59_fpCosPiTest_q : std_logic_vector (8 downto 0);
signal fracZCosNotOne_uid78_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal fracZCosNotOne_uid78_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal fracZCosNotOne_uid78_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal evenIntCosNotOneFZ_uid79_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal evenIntCosNotOneFZ_uid79_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal evenIntCosNotOneFZ_uid79_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal xIsInt_uid80_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal xIsInt_uid80_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal xIsInt_uid80_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal xIsHalf_uid83_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal xIsHalf_uid83_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal xIsHalf_uid83_fpCosPiTest_c : std_logic_vector(0 downto 0);
signal xIsHalf_uid83_fpCosPiTest_d : std_logic_vector(0 downto 0);
signal xIsHalf_uid83_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal fracRPostExc_uid88_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal fracRPostExc_uid88_fpCosPiTest_q : std_logic_vector (22 downto 0);
signal xIntOrXZOrCosOne_uid93_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal xIntOrXZOrCosOne_uid93_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal xIntOrXZOrCosOne_uid93_fpCosPiTest_c : std_logic_vector(0 downto 0);
signal xIntOrXZOrCosOne_uid93_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal expRPostExc_uid95_fpCosPiTest_s : std_logic_vector (1 downto 0);
signal expRPostExc_uid95_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_q : std_logic_vector (36 downto 0);
signal vCount_uid139_lzcZ_uid56_fpCosPiTest_a : std_logic_vector(31 downto 0);
signal vCount_uid139_lzcZ_uid56_fpCosPiTest_b : std_logic_vector(31 downto 0);
signal vCount_uid139_lzcZ_uid56_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid144_lzcZ_uid56_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid144_lzcZ_uid56_fpCosPiTest_q : std_logic_vector (31 downto 0);
signal vCount_uid147_lzcZ_uid56_fpCosPiTest_a : std_logic_vector(15 downto 0);
signal vCount_uid147_lzcZ_uid56_fpCosPiTest_b : std_logic_vector(15 downto 0);
signal vCount_uid147_lzcZ_uid56_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid150_lzcZ_uid56_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid150_lzcZ_uid56_fpCosPiTest_q : std_logic_vector (15 downto 0);
signal vCount_uid159_lzcZ_uid56_fpCosPiTest_a : std_logic_vector(3 downto 0);
signal vCount_uid159_lzcZ_uid56_fpCosPiTest_b : std_logic_vector(3 downto 0);
signal vCount_uid159_lzcZ_uid56_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid162_lzcZ_uid56_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid162_lzcZ_uid56_fpCosPiTest_q : std_logic_vector (3 downto 0);
signal leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_q : std_logic_vector (34 downto 0);
signal memoryC0_uid207_sinPiZTableGenerator_q : std_logic_vector(28 downto 0);
signal memoryC1_uid208_sinPiZTableGenerator_q : std_logic_vector(20 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal leftShiftStage0Idx1_uid177_alignedZ_uid57_fpCosPiTest_q : std_logic_vector (34 downto 0);
signal leftShiftStage0Idx2_uid180_alignedZ_uid57_fpCosPiTest_q : std_logic_vector (34 downto 0);
signal prodXYTruncFR_uid224_mul2xSinRes_uid66_fpCosPiTest_in : std_logic_vector (48 downto 0);
signal prodXYTruncFR_uid224_mul2xSinRes_uid66_fpCosPiTest_b : std_logic_vector (25 downto 0);
signal prodXYTruncFR_uid227_pT1_uid211_sinPiZPolyEval_in : std_logic_vector (27 downto 0);
signal prodXYTruncFR_uid227_pT1_uid211_sinPiZPolyEval_b : std_logic_vector (14 downto 0);
signal prodXYTruncFR_uid230_pT2_uid217_sinPiZPolyEval_in : std_logic_vector (38 downto 0);
signal prodXYTruncFR_uid230_pT2_uid217_sinPiZPolyEval_b : std_logic_vector (23 downto 0);
signal join_uid94_fpCosPiTest_q : std_logic_vector (1 downto 0);
signal R_uid102_fpCosPiTest_q : std_logic_vector (31 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_cmp_a : std_logic_vector(3 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_cmp_b : std_logic_vector(3 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_cmp_a : std_logic_vector(4 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_cmp_b : std_logic_vector(4 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_cmp_a : std_logic_vector(2 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_cmp_b : std_logic_vector(2 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_nor_q : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_nor_q : std_logic_vector(0 downto 0);
signal oFracX_uid37_uid37_fpCosPiTest_q : std_logic_vector (23 downto 0);
signal InvExpXIsZero_uid33_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid33_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid29_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid29_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal InvExc_I_uid32_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal InvExc_I_uid32_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal fxpShifterBits_uid40_fpCosPiTest_in : std_logic_vector (5 downto 0);
signal fxpShifterBits_uid40_fpCosPiTest_b : std_logic_vector (5 downto 0);
signal oMFxpXFrac_uid49_fpCosPiTest_in : std_logic_vector (35 downto 0);
signal oMFxpXFrac_uid49_fpCosPiTest_b : std_logic_vector (35 downto 0);
signal z_uid54_fpCosPiTest_in : std_logic_vector (34 downto 0);
signal z_uid54_fpCosPiTest_b : std_logic_vector (34 downto 0);
signal expP_uid60_fpCosPiTest_in : std_logic_vector (7 downto 0);
signal expP_uid60_fpCosPiTest_b : std_logic_vector (7 downto 0);
signal LeftShiftStage135dto0_uid126_fxpX_uid41_fpCosPiTest_in : std_logic_vector (35 downto 0);
signal LeftShiftStage135dto0_uid126_fxpX_uid41_fpCosPiTest_b : std_logic_vector (35 downto 0);
signal LeftShiftStage134dto0_uid129_fxpX_uid41_fpCosPiTest_in : std_logic_vector (34 downto 0);
signal LeftShiftStage134dto0_uid129_fxpX_uid41_fpCosPiTest_b : std_logic_vector (34 downto 0);
signal LeftShiftStage133dto0_uid132_fxpX_uid41_fpCosPiTest_in : std_logic_vector (33 downto 0);
signal LeftShiftStage133dto0_uid132_fxpX_uid41_fpCosPiTest_b : std_logic_vector (33 downto 0);
signal rVStage_uid146_lzcZ_uid56_fpCosPiTest_in : std_logic_vector (31 downto 0);
signal rVStage_uid146_lzcZ_uid56_fpCosPiTest_b : std_logic_vector (15 downto 0);
signal vStage_uid148_lzcZ_uid56_fpCosPiTest_in : std_logic_vector (15 downto 0);
signal vStage_uid148_lzcZ_uid56_fpCosPiTest_b : std_logic_vector (15 downto 0);
signal rVStage_uid152_lzcZ_uid56_fpCosPiTest_in : std_logic_vector (15 downto 0);
signal rVStage_uid152_lzcZ_uid56_fpCosPiTest_b : std_logic_vector (7 downto 0);
signal vStage_uid154_lzcZ_uid56_fpCosPiTest_in : std_logic_vector (7 downto 0);
signal vStage_uid154_lzcZ_uid56_fpCosPiTest_b : std_logic_vector (7 downto 0);
signal rVStage_uid164_lzcZ_uid56_fpCosPiTest_in : std_logic_vector (3 downto 0);
signal rVStage_uid164_lzcZ_uid56_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal vStage_uid166_lzcZ_uid56_fpCosPiTest_in : std_logic_vector (1 downto 0);
signal vStage_uid166_lzcZ_uid56_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal LeftShiftStage133dto0_uid196_alignedZ_uid57_fpCosPiTest_in : std_logic_vector (33 downto 0);
signal LeftShiftStage133dto0_uid196_alignedZ_uid57_fpCosPiTest_b : std_logic_vector (33 downto 0);
signal LeftShiftStage132dto0_uid199_alignedZ_uid57_fpCosPiTest_in : std_logic_vector (32 downto 0);
signal LeftShiftStage132dto0_uid199_alignedZ_uid57_fpCosPiTest_b : std_logic_vector (32 downto 0);
signal LeftShiftStage131dto0_uid202_alignedZ_uid57_fpCosPiTest_in : std_logic_vector (31 downto 0);
signal LeftShiftStage131dto0_uid202_alignedZ_uid57_fpCosPiTest_b : std_logic_vector (31 downto 0);
signal normBit_uid67_fpCosPiTest_in : std_logic_vector (25 downto 0);
signal normBit_uid67_fpCosPiTest_b : std_logic_vector (0 downto 0);
signal highRes_uid68_fpCosPiTest_in : std_logic_vector (24 downto 0);
signal highRes_uid68_fpCosPiTest_b : std_logic_vector (23 downto 0);
signal lowRes_uid69_fpCosPiTest_in : std_logic_vector (23 downto 0);
signal lowRes_uid69_fpCosPiTest_b : std_logic_vector (23 downto 0);
signal lowRangeB_uid212_sinPiZPolyEval_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid212_sinPiZPolyEval_b : std_logic_vector (0 downto 0);
signal highBBits_uid213_sinPiZPolyEval_in : std_logic_vector (14 downto 0);
signal highBBits_uid213_sinPiZPolyEval_b : std_logic_vector (13 downto 0);
signal lowRangeB_uid218_sinPiZPolyEval_in : std_logic_vector (1 downto 0);
signal lowRangeB_uid218_sinPiZPolyEval_b : std_logic_vector (1 downto 0);
signal highBBits_uid219_sinPiZPolyEval_in : std_logic_vector (23 downto 0);
signal highBBits_uid219_sinPiZPolyEval_b : std_logic_vector (21 downto 0);
signal oFracXExt_uid39_fpCosPiTest_q : std_logic_vector (36 downto 0);
signal exc_N_uid30_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal exc_N_uid30_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal exc_N_uid30_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal leftShiftStageSel5Dto4_uid112_fxpX_uid41_fpCosPiTest_in : std_logic_vector (5 downto 0);
signal leftShiftStageSel5Dto4_uid112_fxpX_uid41_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel3Dto2_uid123_fxpX_uid41_fpCosPiTest_in : std_logic_vector (3 downto 0);
signal leftShiftStageSel3Dto2_uid123_fxpX_uid41_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid134_fxpX_uid41_fpCosPiTest_in : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid134_fxpX_uid41_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal zAddr_uid62_fpCosPiTest_in : std_logic_vector (34 downto 0);
signal zAddr_uid62_fpCosPiTest_b : std_logic_vector (6 downto 0);
signal zPPolyEval_uid63_fpCosPiTest_in : std_logic_vector (27 downto 0);
signal zPPolyEval_uid63_fpCosPiTest_b : std_logic_vector (15 downto 0);
signal rVStage_uid138_lzcZ_uid56_fpCosPiTest_in : std_logic_vector (34 downto 0);
signal rVStage_uid138_lzcZ_uid56_fpCosPiTest_b : std_logic_vector (31 downto 0);
signal vStage_uid141_lzcZ_uid56_fpCosPiTest_in : std_logic_vector (2 downto 0);
signal vStage_uid141_lzcZ_uid56_fpCosPiTest_b : std_logic_vector (2 downto 0);
signal X18dto0_uid176_alignedZ_uid57_fpCosPiTest_in : std_logic_vector (18 downto 0);
signal X18dto0_uid176_alignedZ_uid57_fpCosPiTest_b : std_logic_vector (18 downto 0);
signal leftShiftStage2Idx1_uid127_fxpX_uid41_fpCosPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage2Idx2_uid130_fxpX_uid41_fpCosPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage2Idx3_uid133_fxpX_uid41_fpCosPiTest_q : std_logic_vector (36 downto 0);
signal vCount_uid153_lzcZ_uid56_fpCosPiTest_a : std_logic_vector(7 downto 0);
signal vCount_uid153_lzcZ_uid56_fpCosPiTest_b : std_logic_vector(7 downto 0);
signal vCount_uid153_lzcZ_uid56_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid156_lzcZ_uid56_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid156_lzcZ_uid56_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal vCount_uid165_lzcZ_uid56_fpCosPiTest_a : std_logic_vector(1 downto 0);
signal vCount_uid165_lzcZ_uid56_fpCosPiTest_b : std_logic_vector(1 downto 0);
signal vCount_uid165_lzcZ_uid56_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid168_lzcZ_uid56_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid168_lzcZ_uid56_fpCosPiTest_q : std_logic_vector (1 downto 0);
signal leftShiftStage2Idx1_uid197_alignedZ_uid57_fpCosPiTest_q : std_logic_vector (34 downto 0);
signal leftShiftStage2Idx2_uid200_alignedZ_uid57_fpCosPiTest_q : std_logic_vector (34 downto 0);
signal leftShiftStage2Idx3_uid203_alignedZ_uid57_fpCosPiTest_q : std_logic_vector (34 downto 0);
signal fracRCompPreRnd_uid70_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal fracRCompPreRnd_uid70_fpCosPiTest_q : std_logic_vector (23 downto 0);
signal rndExpUpdate_uid72_uid73_fpCosPiTest_q : std_logic_vector (24 downto 0);
signal sumAHighB_uid214_sinPiZPolyEval_a : std_logic_vector(21 downto 0);
signal sumAHighB_uid214_sinPiZPolyEval_b : std_logic_vector(21 downto 0);
signal sumAHighB_uid214_sinPiZPolyEval_o : std_logic_vector (21 downto 0);
signal sumAHighB_uid214_sinPiZPolyEval_q : std_logic_vector (21 downto 0);
signal sumAHighB_uid220_sinPiZPolyEval_a : std_logic_vector(29 downto 0);
signal sumAHighB_uid220_sinPiZPolyEval_b : std_logic_vector(29 downto 0);
signal sumAHighB_uid220_sinPiZPolyEval_o : std_logic_vector (29 downto 0);
signal sumAHighB_uid220_sinPiZPolyEval_q : std_logic_vector (29 downto 0);
signal X20dto0_uid106_fxpX_uid41_fpCosPiTest_in : std_logic_vector (20 downto 0);
signal X20dto0_uid106_fxpX_uid41_fpCosPiTest_b : std_logic_vector (20 downto 0);
signal X4dto0_uid109_fxpX_uid41_fpCosPiTest_in : std_logic_vector (4 downto 0);
signal X4dto0_uid109_fxpX_uid41_fpCosPiTest_b : std_logic_vector (4 downto 0);
signal InvExc_N_uid31_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal InvExc_N_uid31_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal excRNaN_uid84_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal excRNaN_uid84_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal excRNaN_uid84_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal yT1_uid210_sinPiZPolyEval_in : std_logic_vector (15 downto 0);
signal yT1_uid210_sinPiZPolyEval_b : std_logic_vector (13 downto 0);
signal cStage_uid142_lzcZ_uid56_fpCosPiTest_q : std_logic_vector (31 downto 0);
signal leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest_q : std_logic_vector (36 downto 0);
signal rVStage_uid158_lzcZ_uid56_fpCosPiTest_in : std_logic_vector (7 downto 0);
signal rVStage_uid158_lzcZ_uid56_fpCosPiTest_b : std_logic_vector (3 downto 0);
signal vStage_uid160_lzcZ_uid56_fpCosPiTest_in : std_logic_vector (3 downto 0);
signal vStage_uid160_lzcZ_uid56_fpCosPiTest_b : std_logic_vector (3 downto 0);
signal rVStage_uid170_lzcZ_uid56_fpCosPiTest_in : std_logic_vector (1 downto 0);
signal rVStage_uid170_lzcZ_uid56_fpCosPiTest_b : std_logic_vector (0 downto 0);
signal leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest_q : std_logic_vector (34 downto 0);
signal expFracPreRnd_uid71_uid71_fpCosPiTest_q : std_logic_vector (31 downto 0);
signal expFracComp_uid74_fpCosPiTest_a : std_logic_vector(32 downto 0);
signal expFracComp_uid74_fpCosPiTest_b : std_logic_vector(32 downto 0);
signal expFracComp_uid74_fpCosPiTest_o : std_logic_vector (32 downto 0);
signal expFracComp_uid74_fpCosPiTest_q : std_logic_vector (32 downto 0);
signal s1_uid212_uid215_sinPiZPolyEval_q : std_logic_vector (22 downto 0);
signal s2_uid218_uid221_sinPiZPolyEval_q : std_logic_vector (31 downto 0);
signal leftShiftStage0Idx1_uid107_fxpX_uid41_fpCosPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage0Idx2_uid110_fxpX_uid41_fpCosPiTest_q : std_logic_vector (36 downto 0);
signal exc_R_uid34_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal exc_R_uid34_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal exc_R_uid34_fpCosPiTest_c : std_logic_vector(0 downto 0);
signal exc_R_uid34_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal rInfOrNaN_uid92_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal rInfOrNaN_uid92_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal rInfOrNaN_uid92_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal FxpX36_uid42_fpCosPiTest_in : std_logic_vector (36 downto 0);
signal FxpX36_uid42_fpCosPiTest_b : std_logic_vector (0 downto 0);
signal fxpXFrac_uid43_fpCosPiTest_in : std_logic_vector (35 downto 0);
signal fxpXFrac_uid43_fpCosPiTest_b : std_logic_vector (35 downto 0);
signal vCount_uid171_lzcZ_uid56_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal vCount_uid171_lzcZ_uid56_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal vCount_uid171_lzcZ_uid56_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal alignedZLow_uid58_fpCosPiTest_in : std_logic_vector (34 downto 0);
signal alignedZLow_uid58_fpCosPiTest_b : std_logic_vector (23 downto 0);
signal fracRComp_uid75_fpCosPiTest_in : std_logic_vector (23 downto 0);
signal fracRComp_uid75_fpCosPiTest_b : std_logic_vector (22 downto 0);
signal expRComp_uid76_fpCosPiTest_in : std_logic_vector (31 downto 0);
signal expRComp_uid76_fpCosPiTest_b : std_logic_vector (7 downto 0);
signal fxpSinRes_uid65_fpCosPiTest_in : std_logic_vector (29 downto 0);
signal fxpSinRes_uid65_fpCosPiTest_b : std_logic_vector (24 downto 0);
signal leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_q : std_logic_vector (36 downto 0);
signal FxpXFrac35_uid44_fpCosPiTest_in : std_logic_vector (35 downto 0);
signal FxpXFrac35_uid44_fpCosPiTest_b : std_logic_vector (0 downto 0);
signal r_uid172_lzcZ_uid56_fpCosPiTest_q : std_logic_vector (5 downto 0);
signal LeftShiftStage032dto0_uid115_fxpX_uid41_fpCosPiTest_in : std_logic_vector (32 downto 0);
signal LeftShiftStage032dto0_uid115_fxpX_uid41_fpCosPiTest_b : std_logic_vector (32 downto 0);
signal LeftShiftStage028dto0_uid118_fxpX_uid41_fpCosPiTest_in : std_logic_vector (28 downto 0);
signal LeftShiftStage028dto0_uid118_fxpX_uid41_fpCosPiTest_b : std_logic_vector (28 downto 0);
signal LeftShiftStage024dto0_uid121_fxpX_uid41_fpCosPiTest_in : std_logic_vector (24 downto 0);
signal LeftShiftStage024dto0_uid121_fxpX_uid41_fpCosPiTest_b : std_logic_vector (24 downto 0);
signal xParityXorHalfParity_uid96_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal xParityXorHalfParity_uid96_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal xParityXorHalfParity_uid96_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal leftShiftStageSel5Dto4_uid182_alignedZ_uid57_fpCosPiTest_in : std_logic_vector (5 downto 0);
signal leftShiftStageSel5Dto4_uid182_alignedZ_uid57_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel3Dto2_uid193_alignedZ_uid57_fpCosPiTest_in : std_logic_vector (3 downto 0);
signal leftShiftStageSel3Dto2_uid193_alignedZ_uid57_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid204_alignedZ_uid57_fpCosPiTest_in : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid204_alignedZ_uid57_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStage1Idx1_uid116_fxpX_uid41_fpCosPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage1Idx2_uid119_fxpX_uid41_fpCosPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage1Idx3_uid122_fxpX_uid41_fpCosPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_q : std_logic_vector (34 downto 0);
signal LeftShiftStage030dto0_uid185_alignedZ_uid57_fpCosPiTest_in : std_logic_vector (30 downto 0);
signal LeftShiftStage030dto0_uid185_alignedZ_uid57_fpCosPiTest_b : std_logic_vector (30 downto 0);
signal LeftShiftStage026dto0_uid188_alignedZ_uid57_fpCosPiTest_in : std_logic_vector (26 downto 0);
signal LeftShiftStage026dto0_uid188_alignedZ_uid57_fpCosPiTest_b : std_logic_vector (26 downto 0);
signal LeftShiftStage022dto0_uid191_alignedZ_uid57_fpCosPiTest_in : std_logic_vector (22 downto 0);
signal LeftShiftStage022dto0_uid191_alignedZ_uid57_fpCosPiTest_b : std_logic_vector (22 downto 0);
signal leftShiftStage1Idx1_uid186_alignedZ_uid57_fpCosPiTest_q : std_logic_vector (34 downto 0);
signal leftShiftStage1Idx2_uid189_alignedZ_uid57_fpCosPiTest_q : std_logic_vector (34 downto 0);
signal leftShiftStage1Idx3_uid192_alignedZ_uid57_fpCosPiTest_q : std_logic_vector (34 downto 0);
begin
--xIn(GPIN,3)@0
--LeftShiftStage133dto0_uid132_fxpX_uid41_fpCosPiTest(BITSELECT,131)@1
LeftShiftStage133dto0_uid132_fxpX_uid41_fpCosPiTest_in <= leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_q(33 downto 0);
LeftShiftStage133dto0_uid132_fxpX_uid41_fpCosPiTest_b <= LeftShiftStage133dto0_uid132_fxpX_uid41_fpCosPiTest_in(33 downto 0);
--leftShiftStage2Idx3Pad3_uid131_fxpX_uid41_fpCosPiTest(CONSTANT,130)
leftShiftStage2Idx3Pad3_uid131_fxpX_uid41_fpCosPiTest_q <= "000";
--leftShiftStage2Idx3_uid133_fxpX_uid41_fpCosPiTest(BITJOIN,132)@1
leftShiftStage2Idx3_uid133_fxpX_uid41_fpCosPiTest_q <= LeftShiftStage133dto0_uid132_fxpX_uid41_fpCosPiTest_b & leftShiftStage2Idx3Pad3_uid131_fxpX_uid41_fpCosPiTest_q;
--LeftShiftStage134dto0_uid129_fxpX_uid41_fpCosPiTest(BITSELECT,128)@1
LeftShiftStage134dto0_uid129_fxpX_uid41_fpCosPiTest_in <= leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_q(34 downto 0);
LeftShiftStage134dto0_uid129_fxpX_uid41_fpCosPiTest_b <= LeftShiftStage134dto0_uid129_fxpX_uid41_fpCosPiTest_in(34 downto 0);
--leftShiftStage2Idx2Pad2_uid128_fxpX_uid41_fpCosPiTest(CONSTANT,127)
leftShiftStage2Idx2Pad2_uid128_fxpX_uid41_fpCosPiTest_q <= "00";
--leftShiftStage2Idx2_uid130_fxpX_uid41_fpCosPiTest(BITJOIN,129)@1
leftShiftStage2Idx2_uid130_fxpX_uid41_fpCosPiTest_q <= LeftShiftStage134dto0_uid129_fxpX_uid41_fpCosPiTest_b & leftShiftStage2Idx2Pad2_uid128_fxpX_uid41_fpCosPiTest_q;
--LeftShiftStage135dto0_uid126_fxpX_uid41_fpCosPiTest(BITSELECT,125)@1
LeftShiftStage135dto0_uid126_fxpX_uid41_fpCosPiTest_in <= leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_q(35 downto 0);
LeftShiftStage135dto0_uid126_fxpX_uid41_fpCosPiTest_b <= LeftShiftStage135dto0_uid126_fxpX_uid41_fpCosPiTest_in(35 downto 0);
--GND(CONSTANT,0)
GND_q <= "0";
--leftShiftStage2Idx1_uid127_fxpX_uid41_fpCosPiTest(BITJOIN,126)@1
leftShiftStage2Idx1_uid127_fxpX_uid41_fpCosPiTest_q <= LeftShiftStage135dto0_uid126_fxpX_uid41_fpCosPiTest_b & GND_q;
--leftShiftStage0Idx3_uid111_fxpX_uid41_fpCosPiTest(CONSTANT,110)
leftShiftStage0Idx3_uid111_fxpX_uid41_fpCosPiTest_q <= "0000000000000000000000000000000000000";
--X4dto0_uid109_fxpX_uid41_fpCosPiTest(BITSELECT,108)@0
X4dto0_uid109_fxpX_uid41_fpCosPiTest_in <= oFracXExt_uid39_fpCosPiTest_q(4 downto 0);
X4dto0_uid109_fxpX_uid41_fpCosPiTest_b <= X4dto0_uid109_fxpX_uid41_fpCosPiTest_in(4 downto 0);
--leftShiftStage0Idx2Pad32_uid108_fxpX_uid41_fpCosPiTest(CONSTANT,107)
leftShiftStage0Idx2Pad32_uid108_fxpX_uid41_fpCosPiTest_q <= "00000000000000000000000000000000";
--leftShiftStage0Idx2_uid110_fxpX_uid41_fpCosPiTest(BITJOIN,109)@0
leftShiftStage0Idx2_uid110_fxpX_uid41_fpCosPiTest_q <= X4dto0_uid109_fxpX_uid41_fpCosPiTest_b & leftShiftStage0Idx2Pad32_uid108_fxpX_uid41_fpCosPiTest_q;
--X20dto0_uid106_fxpX_uid41_fpCosPiTest(BITSELECT,105)@0
X20dto0_uid106_fxpX_uid41_fpCosPiTest_in <= oFracXExt_uid39_fpCosPiTest_q(20 downto 0);
X20dto0_uid106_fxpX_uid41_fpCosPiTest_b <= X20dto0_uid106_fxpX_uid41_fpCosPiTest_in(20 downto 0);
--leftShiftStage0Idx1Pad16_uid105_fxpX_uid41_fpCosPiTest(CONSTANT,104)
leftShiftStage0Idx1Pad16_uid105_fxpX_uid41_fpCosPiTest_q <= "0000000000000000";
--leftShiftStage0Idx1_uid107_fxpX_uid41_fpCosPiTest(BITJOIN,106)@0
leftShiftStage0Idx1_uid107_fxpX_uid41_fpCosPiTest_q <= X20dto0_uid106_fxpX_uid41_fpCosPiTest_b & leftShiftStage0Idx1Pad16_uid105_fxpX_uid41_fpCosPiTest_q;
--cst01pWShift_uid14_fpCosPiTest(CONSTANT,13)
cst01pWShift_uid14_fpCosPiTest_q <= "0000000000000";
--VCC(CONSTANT,1)
VCC_q <= "1";
--fracX_uid7_fpCosPiTest(BITSELECT,6)@0
fracX_uid7_fpCosPiTest_in <= a(22 downto 0);
fracX_uid7_fpCosPiTest_b <= fracX_uid7_fpCosPiTest_in(22 downto 0);
--oFracX_uid37_uid37_fpCosPiTest(BITJOIN,36)@0
oFracX_uid37_uid37_fpCosPiTest_q <= VCC_q & fracX_uid7_fpCosPiTest_b;
--oFracXExt_uid39_fpCosPiTest(BITJOIN,38)@0
oFracXExt_uid39_fpCosPiTest_q <= cst01pWShift_uid14_fpCosPiTest_q & oFracX_uid37_uid37_fpCosPiTest_q;
--biasMwShiftMO_uid13_fpCosPiTest(CONSTANT,12)
biasMwShiftMO_uid13_fpCosPiTest_q <= "01110010";
--expX_uid6_fpCosPiTest(BITSELECT,5)@0
expX_uid6_fpCosPiTest_in <= a(30 downto 0);
expX_uid6_fpCosPiTest_b <= expX_uid6_fpCosPiTest_in(30 downto 23);
--shiftValFxPX_uid38_fpCosPiTest(SUB,37)@0
shiftValFxPX_uid38_fpCosPiTest_a <= STD_LOGIC_VECTOR("0" & expX_uid6_fpCosPiTest_b);
shiftValFxPX_uid38_fpCosPiTest_b <= STD_LOGIC_VECTOR("0" & biasMwShiftMO_uid13_fpCosPiTest_q);
shiftValFxPX_uid38_fpCosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(shiftValFxPX_uid38_fpCosPiTest_a) - UNSIGNED(shiftValFxPX_uid38_fpCosPiTest_b));
shiftValFxPX_uid38_fpCosPiTest_q <= shiftValFxPX_uid38_fpCosPiTest_o(8 downto 0);
--fxpShifterBits_uid40_fpCosPiTest(BITSELECT,39)@0
fxpShifterBits_uid40_fpCosPiTest_in <= shiftValFxPX_uid38_fpCosPiTest_q(5 downto 0);
fxpShifterBits_uid40_fpCosPiTest_b <= fxpShifterBits_uid40_fpCosPiTest_in(5 downto 0);
--leftShiftStageSel5Dto4_uid112_fxpX_uid41_fpCosPiTest(BITSELECT,111)@0
leftShiftStageSel5Dto4_uid112_fxpX_uid41_fpCosPiTest_in <= fxpShifterBits_uid40_fpCosPiTest_b;
leftShiftStageSel5Dto4_uid112_fxpX_uid41_fpCosPiTest_b <= leftShiftStageSel5Dto4_uid112_fxpX_uid41_fpCosPiTest_in(5 downto 4);
--leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest(MUX,112)@0
leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_s <= leftShiftStageSel5Dto4_uid112_fxpX_uid41_fpCosPiTest_b;
leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest: PROCESS (leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_s, en, oFracXExt_uid39_fpCosPiTest_q, leftShiftStage0Idx1_uid107_fxpX_uid41_fpCosPiTest_q, leftShiftStage0Idx2_uid110_fxpX_uid41_fpCosPiTest_q, leftShiftStage0Idx3_uid111_fxpX_uid41_fpCosPiTest_q)
BEGIN
CASE leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_s IS
WHEN "00" => leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_q <= oFracXExt_uid39_fpCosPiTest_q;
WHEN "01" => leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_q <= leftShiftStage0Idx1_uid107_fxpX_uid41_fpCosPiTest_q;
WHEN "10" => leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_q <= leftShiftStage0Idx2_uid110_fxpX_uid41_fpCosPiTest_q;
WHEN "11" => leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_q <= leftShiftStage0Idx3_uid111_fxpX_uid41_fpCosPiTest_q;
WHEN OTHERS => leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage024dto0_uid121_fxpX_uid41_fpCosPiTest(BITSELECT,120)@0
LeftShiftStage024dto0_uid121_fxpX_uid41_fpCosPiTest_in <= leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_q(24 downto 0);
LeftShiftStage024dto0_uid121_fxpX_uid41_fpCosPiTest_b <= LeftShiftStage024dto0_uid121_fxpX_uid41_fpCosPiTest_in(24 downto 0);
--leftShiftStage1Idx3Pad12_uid120_fxpX_uid41_fpCosPiTest(CONSTANT,119)
leftShiftStage1Idx3Pad12_uid120_fxpX_uid41_fpCosPiTest_q <= "000000000000";
--leftShiftStage1Idx3_uid122_fxpX_uid41_fpCosPiTest(BITJOIN,121)@0
leftShiftStage1Idx3_uid122_fxpX_uid41_fpCosPiTest_q <= LeftShiftStage024dto0_uid121_fxpX_uid41_fpCosPiTest_b & leftShiftStage1Idx3Pad12_uid120_fxpX_uid41_fpCosPiTest_q;
--reg_leftShiftStage1Idx3_uid122_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_5(REG,235)@0
reg_leftShiftStage1Idx3_uid122_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx3_uid122_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_5_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx3_uid122_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_5_q <= leftShiftStage1Idx3_uid122_fxpX_uid41_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage028dto0_uid118_fxpX_uid41_fpCosPiTest(BITSELECT,117)@0
LeftShiftStage028dto0_uid118_fxpX_uid41_fpCosPiTest_in <= leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_q(28 downto 0);
LeftShiftStage028dto0_uid118_fxpX_uid41_fpCosPiTest_b <= LeftShiftStage028dto0_uid118_fxpX_uid41_fpCosPiTest_in(28 downto 0);
--cstAllZWE_uid21_fpCosPiTest(CONSTANT,20)
cstAllZWE_uid21_fpCosPiTest_q <= "00000000";
--leftShiftStage1Idx2_uid119_fxpX_uid41_fpCosPiTest(BITJOIN,118)@0
leftShiftStage1Idx2_uid119_fxpX_uid41_fpCosPiTest_q <= LeftShiftStage028dto0_uid118_fxpX_uid41_fpCosPiTest_b & cstAllZWE_uid21_fpCosPiTest_q;
--reg_leftShiftStage1Idx2_uid119_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_4(REG,234)@0
reg_leftShiftStage1Idx2_uid119_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx2_uid119_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_4_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx2_uid119_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_4_q <= leftShiftStage1Idx2_uid119_fxpX_uid41_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage032dto0_uid115_fxpX_uid41_fpCosPiTest(BITSELECT,114)@0
LeftShiftStage032dto0_uid115_fxpX_uid41_fpCosPiTest_in <= leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_q(32 downto 0);
LeftShiftStage032dto0_uid115_fxpX_uid41_fpCosPiTest_b <= LeftShiftStage032dto0_uid115_fxpX_uid41_fpCosPiTest_in(32 downto 0);
--leftShiftStage1Idx1Pad4_uid114_fxpX_uid41_fpCosPiTest(CONSTANT,113)
leftShiftStage1Idx1Pad4_uid114_fxpX_uid41_fpCosPiTest_q <= "0000";
--leftShiftStage1Idx1_uid116_fxpX_uid41_fpCosPiTest(BITJOIN,115)@0
leftShiftStage1Idx1_uid116_fxpX_uid41_fpCosPiTest_q <= LeftShiftStage032dto0_uid115_fxpX_uid41_fpCosPiTest_b & leftShiftStage1Idx1Pad4_uid114_fxpX_uid41_fpCosPiTest_q;
--reg_leftShiftStage1Idx1_uid116_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_3(REG,233)@0
reg_leftShiftStage1Idx1_uid116_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx1_uid116_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_3_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx1_uid116_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_3_q <= leftShiftStage1Idx1_uid116_fxpX_uid41_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--reg_leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_2(REG,232)@0
reg_leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_2_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_2_q <= leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel3Dto2_uid123_fxpX_uid41_fpCosPiTest(BITSELECT,122)@0
leftShiftStageSel3Dto2_uid123_fxpX_uid41_fpCosPiTest_in <= fxpShifterBits_uid40_fpCosPiTest_b(3 downto 0);
leftShiftStageSel3Dto2_uid123_fxpX_uid41_fpCosPiTest_b <= leftShiftStageSel3Dto2_uid123_fxpX_uid41_fpCosPiTest_in(3 downto 2);
--reg_leftShiftStageSel3Dto2_uid123_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_1(REG,231)@0
reg_leftShiftStageSel3Dto2_uid123_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel3Dto2_uid123_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel3Dto2_uid123_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_1_q <= leftShiftStageSel3Dto2_uid123_fxpX_uid41_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest(MUX,123)@1
leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_s <= reg_leftShiftStageSel3Dto2_uid123_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_1_q;
leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest: PROCESS (leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_s, en, reg_leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_2_q, reg_leftShiftStage1Idx1_uid116_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_3_q, reg_leftShiftStage1Idx2_uid119_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_4_q, reg_leftShiftStage1Idx3_uid122_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_5_q)
BEGIN
CASE leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_s IS
WHEN "00" => leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_q <= reg_leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_2_q;
WHEN "01" => leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_q <= reg_leftShiftStage1Idx1_uid116_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_3_q;
WHEN "10" => leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_q <= reg_leftShiftStage1Idx2_uid119_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_4_q;
WHEN "11" => leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_q <= reg_leftShiftStage1Idx3_uid122_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_5_q;
WHEN OTHERS => leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--leftShiftStageSel1Dto0_uid134_fxpX_uid41_fpCosPiTest(BITSELECT,133)@0
leftShiftStageSel1Dto0_uid134_fxpX_uid41_fpCosPiTest_in <= fxpShifterBits_uid40_fpCosPiTest_b(1 downto 0);
leftShiftStageSel1Dto0_uid134_fxpX_uid41_fpCosPiTest_b <= leftShiftStageSel1Dto0_uid134_fxpX_uid41_fpCosPiTest_in(1 downto 0);
--reg_leftShiftStageSel1Dto0_uid134_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest_1(REG,236)@0
reg_leftShiftStageSel1Dto0_uid134_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel1Dto0_uid134_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel1Dto0_uid134_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest_1_q <= leftShiftStageSel1Dto0_uid134_fxpX_uid41_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest(MUX,134)@1
leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest_s <= reg_leftShiftStageSel1Dto0_uid134_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest_1_q;
leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest: PROCESS (leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest_s, en, leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_q, leftShiftStage2Idx1_uid127_fxpX_uid41_fpCosPiTest_q, leftShiftStage2Idx2_uid130_fxpX_uid41_fpCosPiTest_q, leftShiftStage2Idx3_uid133_fxpX_uid41_fpCosPiTest_q)
BEGIN
CASE leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest_s IS
WHEN "00" => leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest_q <= leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_q;
WHEN "01" => leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest_q <= leftShiftStage2Idx1_uid127_fxpX_uid41_fpCosPiTest_q;
WHEN "10" => leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest_q <= leftShiftStage2Idx2_uid130_fxpX_uid41_fpCosPiTest_q;
WHEN "11" => leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest_q <= leftShiftStage2Idx3_uid133_fxpX_uid41_fpCosPiTest_q;
WHEN OTHERS => leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--fxpXFrac_uid43_fpCosPiTest(BITSELECT,42)@1
fxpXFrac_uid43_fpCosPiTest_in <= leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest_q(35 downto 0);
fxpXFrac_uid43_fpCosPiTest_b <= fxpXFrac_uid43_fpCosPiTest_in(35 downto 0);
--FxpXFrac35_uid44_fpCosPiTest(BITSELECT,43)@1
FxpXFrac35_uid44_fpCosPiTest_in <= fxpXFrac_uid43_fpCosPiTest_b;
FxpXFrac35_uid44_fpCosPiTest_b <= FxpXFrac35_uid44_fpCosPiTest_in(35 downto 35);
--FxpX36_uid42_fpCosPiTest(BITSELECT,41)@1
FxpX36_uid42_fpCosPiTest_in <= leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest_q;
FxpX36_uid42_fpCosPiTest_b <= FxpX36_uid42_fpCosPiTest_in(36 downto 36);
--xParityXorHalfParity_uid96_fpCosPiTest(LOGICAL,95)@1
xParityXorHalfParity_uid96_fpCosPiTest_a <= FxpX36_uid42_fpCosPiTest_b;
xParityXorHalfParity_uid96_fpCosPiTest_b <= FxpXFrac35_uid44_fpCosPiTest_b;
xParityXorHalfParity_uid96_fpCosPiTest_q <= xParityXorHalfParity_uid96_fpCosPiTest_a xor xParityXorHalfParity_uid96_fpCosPiTest_b;
--ld_xParityXorHalfParity_uid96_fpCosPiTest_q_to_signRComp_uid99_fpCosPiTest_c(DELAY,369)@1
ld_xParityXorHalfParity_uid96_fpCosPiTest_q_to_signRComp_uid99_fpCosPiTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => xParityXorHalfParity_uid96_fpCosPiTest_q, xout => ld_xParityXorHalfParity_uid96_fpCosPiTest_q_to_signRComp_uid99_fpCosPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--cstBiasPwF_uid12_fpCosPiTest(CONSTANT,11)
cstBiasPwF_uid12_fpCosPiTest_q <= "10010110";
--xEvenInt_uid35_fpCosPiTest(COMPARE,34)@0
xEvenInt_uid35_fpCosPiTest_cin <= GND_q;
xEvenInt_uid35_fpCosPiTest_a <= STD_LOGIC_VECTOR("00" & cstBiasPwF_uid12_fpCosPiTest_q) & '0';
xEvenInt_uid35_fpCosPiTest_b <= STD_LOGIC_VECTOR("00" & expX_uid6_fpCosPiTest_b) & xEvenInt_uid35_fpCosPiTest_cin(0);
xEvenInt_uid35_fpCosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(xEvenInt_uid35_fpCosPiTest_a) - UNSIGNED(xEvenInt_uid35_fpCosPiTest_b));
xEvenInt_uid35_fpCosPiTest_c(0) <= xEvenInt_uid35_fpCosPiTest_o(10);
--ld_xEvenInt_uid35_fpCosPiTest_c_to_evenIntCosNotOneFZ_uid79_fpCosPiTest_a(DELAY,335)@0
ld_xEvenInt_uid35_fpCosPiTest_c_to_evenIntCosNotOneFZ_uid79_fpCosPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => xEvenInt_uid35_fpCosPiTest_c, xout => ld_xEvenInt_uid35_fpCosPiTest_c_to_evenIntCosNotOneFZ_uid79_fpCosPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--InvXEvenInt_uid81_fpCosPiTest(LOGICAL,80)@2
InvXEvenInt_uid81_fpCosPiTest_a <= ld_xEvenInt_uid35_fpCosPiTest_c_to_evenIntCosNotOneFZ_uid79_fpCosPiTest_a_q;
InvXEvenInt_uid81_fpCosPiTest_q <= not InvXEvenInt_uid81_fpCosPiTest_a;
--cosXIsOne_uid36_fpCosPiTest(COMPARE,35)@0
cosXIsOne_uid36_fpCosPiTest_cin <= GND_q;
cosXIsOne_uid36_fpCosPiTest_a <= STD_LOGIC_VECTOR("00" & expX_uid6_fpCosPiTest_b) & '0';
cosXIsOne_uid36_fpCosPiTest_b <= STD_LOGIC_VECTOR("00" & biasMwShiftMO_uid13_fpCosPiTest_q) & cosXIsOne_uid36_fpCosPiTest_cin(0);
cosXIsOne_uid36_fpCosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(cosXIsOne_uid36_fpCosPiTest_a) - UNSIGNED(cosXIsOne_uid36_fpCosPiTest_b));
cosXIsOne_uid36_fpCosPiTest_c(0) <= cosXIsOne_uid36_fpCosPiTest_o(10);
--ld_cosXIsOne_uid36_fpCosPiTest_c_to_InvCosXIsOne_uid77_fpCosPiTest_a(DELAY,332)@0
ld_cosXIsOne_uid36_fpCosPiTest_c_to_InvCosXIsOne_uid77_fpCosPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => cosXIsOne_uid36_fpCosPiTest_c, xout => ld_cosXIsOne_uid36_fpCosPiTest_c_to_InvCosXIsOne_uid77_fpCosPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--InvCosXIsOne_uid77_fpCosPiTest(LOGICAL,76)@2
InvCosXIsOne_uid77_fpCosPiTest_a <= ld_cosXIsOne_uid36_fpCosPiTest_c_to_InvCosXIsOne_uid77_fpCosPiTest_a_q;
InvCosXIsOne_uid77_fpCosPiTest_q <= not InvCosXIsOne_uid77_fpCosPiTest_a;
--signRComp_uid99_fpCosPiTest(LOGICAL,98)@2
signRComp_uid99_fpCosPiTest_a <= InvCosXIsOne_uid77_fpCosPiTest_q;
signRComp_uid99_fpCosPiTest_b <= InvXEvenInt_uid81_fpCosPiTest_q;
signRComp_uid99_fpCosPiTest_c <= ld_xParityXorHalfParity_uid96_fpCosPiTest_q_to_signRComp_uid99_fpCosPiTest_c_q;
signRComp_uid99_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
signRComp_uid99_fpCosPiTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1' AND en = "1") THEN
signRComp_uid99_fpCosPiTest_q <= signRComp_uid99_fpCosPiTest_a and signRComp_uid99_fpCosPiTest_b and signRComp_uid99_fpCosPiTest_c;
END IF;
END PROCESS;
--cstZwSwF_uid15_fpCosPiTest(CONSTANT,14)
cstZwSwF_uid15_fpCosPiTest_q <= "00000000000000000000000000000000000";
--cstHalfwSwFP1_uid18_fpCosPiTest(BITJOIN,17)@2
cstHalfwSwFP1_uid18_fpCosPiTest_q <= VCC_q & cstZwSwF_uid15_fpCosPiTest_q;
--reg_fxpXFrac_uid43_fpCosPiTest_0_to_fxpXFracZero_uid45_fpCosPiTest_1(REG,237)@1
reg_fxpXFrac_uid43_fpCosPiTest_0_to_fxpXFracZero_uid45_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fxpXFrac_uid43_fpCosPiTest_0_to_fxpXFracZero_uid45_fpCosPiTest_1_q <= "000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fxpXFrac_uid43_fpCosPiTest_0_to_fxpXFracZero_uid45_fpCosPiTest_1_q <= fxpXFrac_uid43_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--fxpXFracHalf_uid46_fpCosPiTest(LOGICAL,45)@2
fxpXFracHalf_uid46_fpCosPiTest_a <= reg_fxpXFrac_uid43_fpCosPiTest_0_to_fxpXFracZero_uid45_fpCosPiTest_1_q;
fxpXFracHalf_uid46_fpCosPiTest_b <= cstHalfwSwFP1_uid18_fpCosPiTest_q;
fxpXFracHalf_uid46_fpCosPiTest_q <= "1" when fxpXFracHalf_uid46_fpCosPiTest_a = fxpXFracHalf_uid46_fpCosPiTest_b else "0";
--ld_fxpXFracHalf_uid46_fpCosPiTest_q_to_InvFxpXFracHalf_uid100_fpCosPiTest_a(DELAY,370)@2
ld_fxpXFracHalf_uid46_fpCosPiTest_q_to_InvFxpXFracHalf_uid100_fpCosPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => fxpXFracHalf_uid46_fpCosPiTest_q, xout => ld_fxpXFracHalf_uid46_fpCosPiTest_q_to_InvFxpXFracHalf_uid100_fpCosPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--InvFxpXFracHalf_uid100_fpCosPiTest(LOGICAL,99)@3
InvFxpXFracHalf_uid100_fpCosPiTest_a <= ld_fxpXFracHalf_uid46_fpCosPiTest_q_to_InvFxpXFracHalf_uid100_fpCosPiTest_a_q;
InvFxpXFracHalf_uid100_fpCosPiTest_q <= not InvFxpXFracHalf_uid100_fpCosPiTest_a;
--signR_uid101_fpCosPiTest(LOGICAL,100)@3
signR_uid101_fpCosPiTest_a <= InvFxpXFracHalf_uid100_fpCosPiTest_q;
signR_uid101_fpCosPiTest_b <= signRComp_uid99_fpCosPiTest_q;
signR_uid101_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
signR_uid101_fpCosPiTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1' AND en = "1") THEN
signR_uid101_fpCosPiTest_q <= signR_uid101_fpCosPiTest_a and signR_uid101_fpCosPiTest_b;
END IF;
END PROCESS;
--ld_signR_uid101_fpCosPiTest_q_to_R_uid102_fpCosPiTest_c(DELAY,375)@4
ld_signR_uid101_fpCosPiTest_q_to_R_uid102_fpCosPiTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 13 )
PORT MAP ( xin => signR_uid101_fpCosPiTest_q, xout => ld_signR_uid101_fpCosPiTest_q_to_R_uid102_fpCosPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--cstBias_uid10_fpCosPiTest(CONSTANT,9)
cstBias_uid10_fpCosPiTest_q <= "01111111";
--cstAllOWE_uid8_fpCosPiTest(CONSTANT,7)
cstAllOWE_uid8_fpCosPiTest_q <= "11111111";
--pad_o_uid16_uid47_fpCosPiTest(BITJOIN,46)@1
pad_o_uid16_uid47_fpCosPiTest_q <= VCC_q & STD_LOGIC_VECTOR((35 downto 1 => GND_q(0)) & GND_q);
--reg_pad_o_uid16_uid47_fpCosPiTest_0_to_oMFxpXFrac_uid47_fpCosPiTest_0(REG,244)@1
reg_pad_o_uid16_uid47_fpCosPiTest_0_to_oMFxpXFrac_uid47_fpCosPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_o_uid16_uid47_fpCosPiTest_0_to_oMFxpXFrac_uid47_fpCosPiTest_0_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_o_uid16_uid47_fpCosPiTest_0_to_oMFxpXFrac_uid47_fpCosPiTest_0_q <= pad_o_uid16_uid47_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--oMFxpXFrac_uid47_fpCosPiTest(SUB,47)@2
oMFxpXFrac_uid47_fpCosPiTest_a <= STD_LOGIC_VECTOR("0" & reg_pad_o_uid16_uid47_fpCosPiTest_0_to_oMFxpXFrac_uid47_fpCosPiTest_0_q);
oMFxpXFrac_uid47_fpCosPiTest_b <= STD_LOGIC_VECTOR("00" & reg_fxpXFrac_uid43_fpCosPiTest_0_to_fxpXFracZero_uid45_fpCosPiTest_1_q);
oMFxpXFrac_uid47_fpCosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(oMFxpXFrac_uid47_fpCosPiTest_a) - UNSIGNED(oMFxpXFrac_uid47_fpCosPiTest_b));
oMFxpXFrac_uid47_fpCosPiTest_q <= oMFxpXFrac_uid47_fpCosPiTest_o(37 downto 0);
--oMFxpXFrac_uid49_fpCosPiTest(BITSELECT,48)@2
oMFxpXFrac_uid49_fpCosPiTest_in <= oMFxpXFrac_uid47_fpCosPiTest_q(35 downto 0);
oMFxpXFrac_uid49_fpCosPiTest_b <= oMFxpXFrac_uid49_fpCosPiTest_in(35 downto 0);
--ld_fxpXFrac_uid43_fpCosPiTest_b_to_rangeReducedFxPX_uid51_fpCosPiTest_c(DELAY,308)@1
ld_fxpXFrac_uid43_fpCosPiTest_b_to_rangeReducedFxPX_uid51_fpCosPiTest_c : dspba_delay
GENERIC MAP ( width => 36, depth => 1 )
PORT MAP ( xin => fxpXFrac_uid43_fpCosPiTest_b, xout => ld_fxpXFrac_uid43_fpCosPiTest_b_to_rangeReducedFxPX_uid51_fpCosPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--ld_FxpXFrac35_uid44_fpCosPiTest_b_to_rangeReducedFxPX_uid51_fpCosPiTest_b(DELAY,307)@1
ld_FxpXFrac35_uid44_fpCosPiTest_b_to_rangeReducedFxPX_uid51_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => FxpXFrac35_uid44_fpCosPiTest_b, xout => ld_FxpXFrac35_uid44_fpCosPiTest_b_to_rangeReducedFxPX_uid51_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--rangeReducedFxPX_uid51_fpCosPiTest(MUX,50)@2
rangeReducedFxPX_uid51_fpCosPiTest_s <= ld_FxpXFrac35_uid44_fpCosPiTest_b_to_rangeReducedFxPX_uid51_fpCosPiTest_b_q;
rangeReducedFxPX_uid51_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
rangeReducedFxPX_uid51_fpCosPiTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE rangeReducedFxPX_uid51_fpCosPiTest_s IS
WHEN "0" => rangeReducedFxPX_uid51_fpCosPiTest_q <= ld_fxpXFrac_uid43_fpCosPiTest_b_to_rangeReducedFxPX_uid51_fpCosPiTest_c_q;
WHEN "1" => rangeReducedFxPX_uid51_fpCosPiTest_q <= oMFxpXFrac_uid49_fpCosPiTest_b;
WHEN OTHERS => rangeReducedFxPX_uid51_fpCosPiTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--pad_half_uid17_uid52_fpCosPiTest(BITJOIN,51)@2
pad_half_uid17_uid52_fpCosPiTest_q <= VCC_q & STD_LOGIC_VECTOR((34 downto 1 => GND_q(0)) & GND_q);
--reg_pad_half_uid17_uid52_fpCosPiTest_0_to_z_halfMRRFxPXE_uid52_fpCosPiTest_0(REG,246)@2
reg_pad_half_uid17_uid52_fpCosPiTest_0_to_z_halfMRRFxPXE_uid52_fpCosPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_half_uid17_uid52_fpCosPiTest_0_to_z_halfMRRFxPXE_uid52_fpCosPiTest_0_q <= "000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_half_uid17_uid52_fpCosPiTest_0_to_z_halfMRRFxPXE_uid52_fpCosPiTest_0_q <= pad_half_uid17_uid52_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--z_halfMRRFxPXE_uid52_fpCosPiTest(SUB,52)@3
z_halfMRRFxPXE_uid52_fpCosPiTest_a <= STD_LOGIC_VECTOR("0" & reg_pad_half_uid17_uid52_fpCosPiTest_0_to_z_halfMRRFxPXE_uid52_fpCosPiTest_0_q);
z_halfMRRFxPXE_uid52_fpCosPiTest_b <= STD_LOGIC_VECTOR("0" & rangeReducedFxPX_uid51_fpCosPiTest_q);
z_halfMRRFxPXE_uid52_fpCosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(z_halfMRRFxPXE_uid52_fpCosPiTest_a) - UNSIGNED(z_halfMRRFxPXE_uid52_fpCosPiTest_b));
z_halfMRRFxPXE_uid52_fpCosPiTest_q <= z_halfMRRFxPXE_uid52_fpCosPiTest_o(36 downto 0);
--z_uid54_fpCosPiTest(BITSELECT,53)@3
z_uid54_fpCosPiTest_in <= z_halfMRRFxPXE_uid52_fpCosPiTest_q(34 downto 0);
z_uid54_fpCosPiTest_b <= z_uid54_fpCosPiTest_in(34 downto 0);
--zAddr_uid62_fpCosPiTest(BITSELECT,61)@3
zAddr_uid62_fpCosPiTest_in <= z_uid54_fpCosPiTest_b;
zAddr_uid62_fpCosPiTest_b <= zAddr_uid62_fpCosPiTest_in(34 downto 28);
--reg_zAddr_uid62_fpCosPiTest_0_to_memoryC2_uid209_sinPiZTableGenerator_0(REG,263)@3
reg_zAddr_uid62_fpCosPiTest_0_to_memoryC2_uid209_sinPiZTableGenerator_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_zAddr_uid62_fpCosPiTest_0_to_memoryC2_uid209_sinPiZTableGenerator_0_q <= "0000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_zAddr_uid62_fpCosPiTest_0_to_memoryC2_uid209_sinPiZTableGenerator_0_q <= zAddr_uid62_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--memoryC2_uid209_sinPiZTableGenerator(LOOKUP,208)@4
memoryC2_uid209_sinPiZTableGenerator: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
memoryC2_uid209_sinPiZTableGenerator_q <= "10101101010011";
ELSIF (clk'EVENT AND clk = '1' AND en = "1") THEN
CASE (reg_zAddr_uid62_fpCosPiTest_0_to_memoryC2_uid209_sinPiZTableGenerator_0_q) IS
WHEN "0000000" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101101010011";
WHEN "0000001" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101101010100";
WHEN "0000010" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101101010111";
WHEN "0000011" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101101011001";
WHEN "0000100" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101101011011";
WHEN "0000101" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101101011100";
WHEN "0000110" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101101011111";
WHEN "0000111" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101101100010";
WHEN "0001000" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101101100110";
WHEN "0001001" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101101101011";
WHEN "0001010" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101101110000";
WHEN "0001011" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101101110101";
WHEN "0001100" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101101111011";
WHEN "0001101" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101110000000";
WHEN "0001110" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101110000111";
WHEN "0001111" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101110001110";
WHEN "0010000" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101110010011";
WHEN "0010001" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101110011110";
WHEN "0010010" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101110100110";
WHEN "0010011" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101110101111";
WHEN "0010100" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101110111000";
WHEN "0010101" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101111000011";
WHEN "0010110" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101111001100";
WHEN "0010111" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101111010111";
WHEN "0011000" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101111100011";
WHEN "0011001" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101111101110";
WHEN "0011010" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101111111011";
WHEN "0011011" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110000001001";
WHEN "0011100" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110000010101";
WHEN "0011101" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110000100000";
WHEN "0011110" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110000110001";
WHEN "0011111" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110001000000";
WHEN "0100000" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110001001101";
WHEN "0100001" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110001011110";
WHEN "0100010" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110001101100";
WHEN "0100011" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110001111111";
WHEN "0100100" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110010001111";
WHEN "0100101" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110010100001";
WHEN "0100110" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110010110011";
WHEN "0100111" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110011000101";
WHEN "0101000" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110011010110";
WHEN "0101001" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110011101011";
WHEN "0101010" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110011111111";
WHEN "0101011" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110100010010";
WHEN "0101100" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110100100101";
WHEN "0101101" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110100111011";
WHEN "0101110" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110101001110";
WHEN "0101111" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110101100111";
WHEN "0110000" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110101111100";
WHEN "0110001" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110110010010";
WHEN "0110010" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110110100110";
WHEN "0110011" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110111000000";
WHEN "0110100" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110111010101";
WHEN "0110101" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110111110000";
WHEN "0110110" => memoryC2_uid209_sinPiZTableGenerator_q <= "10111000000110";
WHEN "0110111" => memoryC2_uid209_sinPiZTableGenerator_q <= "10111000100010";
WHEN "0111000" => memoryC2_uid209_sinPiZTableGenerator_q <= "10111000111001";
WHEN "0111001" => memoryC2_uid209_sinPiZTableGenerator_q <= "10111001010100";
WHEN "0111010" => memoryC2_uid209_sinPiZTableGenerator_q <= "10111001101111";
WHEN "0111011" => memoryC2_uid209_sinPiZTableGenerator_q <= "10111010001001";
WHEN "0111100" => memoryC2_uid209_sinPiZTableGenerator_q <= "10111010100011";
WHEN "0111101" => memoryC2_uid209_sinPiZTableGenerator_q <= "10111010111100";
WHEN "0111110" => memoryC2_uid209_sinPiZTableGenerator_q <= "10111011011001";
WHEN "0111111" => memoryC2_uid209_sinPiZTableGenerator_q <= "10111011110111";
WHEN "1000000" => memoryC2_uid209_sinPiZTableGenerator_q <= "10111100010100";
WHEN "1000001" => memoryC2_uid209_sinPiZTableGenerator_q <= "10111100110001";
WHEN "1000010" => memoryC2_uid209_sinPiZTableGenerator_q <= "10111101001101";
WHEN "1000011" => memoryC2_uid209_sinPiZTableGenerator_q <= "10111101101010";
WHEN "1000100" => memoryC2_uid209_sinPiZTableGenerator_q <= "10111110001000";
WHEN "1000101" => memoryC2_uid209_sinPiZTableGenerator_q <= "10111110100101";
WHEN "1000110" => memoryC2_uid209_sinPiZTableGenerator_q <= "10111111000101";
WHEN "1000111" => memoryC2_uid209_sinPiZTableGenerator_q <= "10111111100011";
WHEN "1001000" => memoryC2_uid209_sinPiZTableGenerator_q <= "11000000000011";
WHEN "1001001" => memoryC2_uid209_sinPiZTableGenerator_q <= "11000000100011";
WHEN "1001010" => memoryC2_uid209_sinPiZTableGenerator_q <= "11000001000100";
WHEN "1001011" => memoryC2_uid209_sinPiZTableGenerator_q <= "11000001100010";
WHEN "1001100" => memoryC2_uid209_sinPiZTableGenerator_q <= "11000010000100";
WHEN "1001101" => memoryC2_uid209_sinPiZTableGenerator_q <= "11000010100010";
WHEN "1001110" => memoryC2_uid209_sinPiZTableGenerator_q <= "11000011000110";
WHEN "1001111" => memoryC2_uid209_sinPiZTableGenerator_q <= "11000011101000";
WHEN "1010000" => memoryC2_uid209_sinPiZTableGenerator_q <= "11000100001010";
WHEN "1010001" => memoryC2_uid209_sinPiZTableGenerator_q <= "11000100101101";
WHEN "1010010" => memoryC2_uid209_sinPiZTableGenerator_q <= "11000101010001";
WHEN "1010011" => memoryC2_uid209_sinPiZTableGenerator_q <= "11000101110010";
WHEN "1010100" => memoryC2_uid209_sinPiZTableGenerator_q <= "11000110010100";
WHEN "1010101" => memoryC2_uid209_sinPiZTableGenerator_q <= "11000110111011";
WHEN "1010110" => memoryC2_uid209_sinPiZTableGenerator_q <= "11000111011010";
WHEN "1010111" => memoryC2_uid209_sinPiZTableGenerator_q <= "11001000000001";
WHEN "1011000" => memoryC2_uid209_sinPiZTableGenerator_q <= "11001000100110";
WHEN "1011001" => memoryC2_uid209_sinPiZTableGenerator_q <= "11001001001011";
WHEN "1011010" => memoryC2_uid209_sinPiZTableGenerator_q <= "11001001101101";
WHEN "1011011" => memoryC2_uid209_sinPiZTableGenerator_q <= "11001010010101";
WHEN "1011100" => memoryC2_uid209_sinPiZTableGenerator_q <= "11001010111100";
WHEN "1011101" => memoryC2_uid209_sinPiZTableGenerator_q <= "11001011100000";
WHEN "1011110" => memoryC2_uid209_sinPiZTableGenerator_q <= "11001100000101";
WHEN "1011111" => memoryC2_uid209_sinPiZTableGenerator_q <= "11001100101110";
WHEN "1100000" => memoryC2_uid209_sinPiZTableGenerator_q <= "11001101010100";
WHEN "1100001" => memoryC2_uid209_sinPiZTableGenerator_q <= "11001101111010";
WHEN "1100010" => memoryC2_uid209_sinPiZTableGenerator_q <= "11001110100010";
WHEN "1100011" => memoryC2_uid209_sinPiZTableGenerator_q <= "11001111001001";
WHEN "1100100" => memoryC2_uid209_sinPiZTableGenerator_q <= "11001111110001";
WHEN "1100101" => memoryC2_uid209_sinPiZTableGenerator_q <= "11010000010110";
WHEN "1100110" => memoryC2_uid209_sinPiZTableGenerator_q <= "11010000111111";
WHEN "1100111" => memoryC2_uid209_sinPiZTableGenerator_q <= "11010001101001";
WHEN "1101000" => memoryC2_uid209_sinPiZTableGenerator_q <= "11010010010010";
WHEN "1101001" => memoryC2_uid209_sinPiZTableGenerator_q <= "11010010111101";
WHEN "1101010" => memoryC2_uid209_sinPiZTableGenerator_q <= "11010011100001";
WHEN "1101011" => memoryC2_uid209_sinPiZTableGenerator_q <= "11010100001100";
WHEN "1101100" => memoryC2_uid209_sinPiZTableGenerator_q <= "11010100110111";
WHEN "1101101" => memoryC2_uid209_sinPiZTableGenerator_q <= "11010101100001";
WHEN "1101110" => memoryC2_uid209_sinPiZTableGenerator_q <= "11010110001011";
WHEN "1101111" => memoryC2_uid209_sinPiZTableGenerator_q <= "11010110110011";
WHEN "1110000" => memoryC2_uid209_sinPiZTableGenerator_q <= "11010111011111";
WHEN "1110001" => memoryC2_uid209_sinPiZTableGenerator_q <= "11011000001010";
WHEN "1110010" => memoryC2_uid209_sinPiZTableGenerator_q <= "11011000110100";
WHEN "1110011" => memoryC2_uid209_sinPiZTableGenerator_q <= "11011001011111";
WHEN "1110100" => memoryC2_uid209_sinPiZTableGenerator_q <= "11011010001010";
WHEN "1110101" => memoryC2_uid209_sinPiZTableGenerator_q <= "11011010110110";
WHEN "1110110" => memoryC2_uid209_sinPiZTableGenerator_q <= "11011011100011";
WHEN "1110111" => memoryC2_uid209_sinPiZTableGenerator_q <= "11011100001111";
WHEN "1111000" => memoryC2_uid209_sinPiZTableGenerator_q <= "11011100111001";
WHEN "1111001" => memoryC2_uid209_sinPiZTableGenerator_q <= "11011101100011";
WHEN "1111010" => memoryC2_uid209_sinPiZTableGenerator_q <= "11011110010001";
WHEN "1111011" => memoryC2_uid209_sinPiZTableGenerator_q <= "11011110111011";
WHEN "1111100" => memoryC2_uid209_sinPiZTableGenerator_q <= "11011111101000";
WHEN "1111101" => memoryC2_uid209_sinPiZTableGenerator_q <= "11100000010101";
WHEN "1111110" => memoryC2_uid209_sinPiZTableGenerator_q <= "11100001000010";
WHEN "1111111" => memoryC2_uid209_sinPiZTableGenerator_q <= "11100001110000";
WHEN OTHERS =>
memoryC2_uid209_sinPiZTableGenerator_q <= (others => '-');
END CASE;
END IF;
END PROCESS;
--zPPolyEval_uid63_fpCosPiTest(BITSELECT,62)@3
zPPolyEval_uid63_fpCosPiTest_in <= z_uid54_fpCosPiTest_b(27 downto 0);
zPPolyEval_uid63_fpCosPiTest_b <= zPPolyEval_uid63_fpCosPiTest_in(27 downto 12);
--yT1_uid210_sinPiZPolyEval(BITSELECT,209)@3
yT1_uid210_sinPiZPolyEval_in <= zPPolyEval_uid63_fpCosPiTest_b;
yT1_uid210_sinPiZPolyEval_b <= yT1_uid210_sinPiZPolyEval_in(15 downto 2);
--reg_yT1_uid210_sinPiZPolyEval_0_to_prodXY_uid226_pT1_uid211_sinPiZPolyEval_0(REG,264)@3
reg_yT1_uid210_sinPiZPolyEval_0_to_prodXY_uid226_pT1_uid211_sinPiZPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT1_uid210_sinPiZPolyEval_0_to_prodXY_uid226_pT1_uid211_sinPiZPolyEval_0_q <= "00000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT1_uid210_sinPiZPolyEval_0_to_prodXY_uid226_pT1_uid211_sinPiZPolyEval_0_q <= yT1_uid210_sinPiZPolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_reg_yT1_uid210_sinPiZPolyEval_0_to_prodXY_uid226_pT1_uid211_sinPiZPolyEval_0_q_to_prodXY_uid226_pT1_uid211_sinPiZPolyEval_a(DELAY,499)@4
ld_reg_yT1_uid210_sinPiZPolyEval_0_to_prodXY_uid226_pT1_uid211_sinPiZPolyEval_0_q_to_prodXY_uid226_pT1_uid211_sinPiZPolyEval_a : dspba_delay
GENERIC MAP ( width => 14, depth => 1 )
PORT MAP ( xin => reg_yT1_uid210_sinPiZPolyEval_0_to_prodXY_uid226_pT1_uid211_sinPiZPolyEval_0_q, xout => ld_reg_yT1_uid210_sinPiZPolyEval_0_to_prodXY_uid226_pT1_uid211_sinPiZPolyEval_0_q_to_prodXY_uid226_pT1_uid211_sinPiZPolyEval_a_q, ena => en(0), clk => clk, aclr => areset );
--prodXY_uid226_pT1_uid211_sinPiZPolyEval(MULT,225)@5
prodXY_uid226_pT1_uid211_sinPiZPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid226_pT1_uid211_sinPiZPolyEval_a),15)) * SIGNED(prodXY_uid226_pT1_uid211_sinPiZPolyEval_b);
prodXY_uid226_pT1_uid211_sinPiZPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid226_pT1_uid211_sinPiZPolyEval_a <= (others => '0');
prodXY_uid226_pT1_uid211_sinPiZPolyEval_b <= (others => '0');
prodXY_uid226_pT1_uid211_sinPiZPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid226_pT1_uid211_sinPiZPolyEval_a <= ld_reg_yT1_uid210_sinPiZPolyEval_0_to_prodXY_uid226_pT1_uid211_sinPiZPolyEval_0_q_to_prodXY_uid226_pT1_uid211_sinPiZPolyEval_a_q;
prodXY_uid226_pT1_uid211_sinPiZPolyEval_b <= memoryC2_uid209_sinPiZTableGenerator_q;
prodXY_uid226_pT1_uid211_sinPiZPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid226_pT1_uid211_sinPiZPolyEval_pr,28));
END IF;
END IF;
END PROCESS;
prodXY_uid226_pT1_uid211_sinPiZPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid226_pT1_uid211_sinPiZPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid226_pT1_uid211_sinPiZPolyEval_q <= prodXY_uid226_pT1_uid211_sinPiZPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid227_pT1_uid211_sinPiZPolyEval(BITSELECT,226)@8
prodXYTruncFR_uid227_pT1_uid211_sinPiZPolyEval_in <= prodXY_uid226_pT1_uid211_sinPiZPolyEval_q;
prodXYTruncFR_uid227_pT1_uid211_sinPiZPolyEval_b <= prodXYTruncFR_uid227_pT1_uid211_sinPiZPolyEval_in(27 downto 13);
--highBBits_uid213_sinPiZPolyEval(BITSELECT,212)@8
highBBits_uid213_sinPiZPolyEval_in <= prodXYTruncFR_uid227_pT1_uid211_sinPiZPolyEval_b;
highBBits_uid213_sinPiZPolyEval_b <= highBBits_uid213_sinPiZPolyEval_in(14 downto 1);
--ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_notEnable(LOGICAL,557)
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_notEnable_a <= en;
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_notEnable_q <= not ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_notEnable_a;
--ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_nor(LOGICAL,596)
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_nor_a <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_notEnable_q;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_nor_b <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_sticky_ena_q;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_nor_q <= not (ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_nor_a or ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_nor_b);
--ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_mem_top(CONSTANT,592)
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_mem_top_q <= "010";
--ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_cmp(LOGICAL,593)
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_cmp_a <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_mem_top_q;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdmux_q);
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_cmp_q <= "1" when ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_cmp_a = ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_cmp_b else "0";
--ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_cmpReg(REG,594)
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_cmpReg_q <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_sticky_ena(REG,597)
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_nor_q = "1") THEN
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_sticky_ena_q <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_enaAnd(LOGICAL,598)
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_enaAnd_a <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_sticky_ena_q;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_enaAnd_b <= en;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_enaAnd_q <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_enaAnd_a and ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_enaAnd_b;
--ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt(COUNTER,588)
-- every=1, low=0, high=2, step=1, init=1
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt_i <= TO_UNSIGNED(1,2);
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt_i = 1 THEN
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt_eq = '1') THEN
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt_i <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt_i - 2;
ELSE
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt_i <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt_i,2));
--ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdreg(REG,589)
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdreg_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdreg_q <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdmux(MUX,590)
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdmux_s <= en;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdmux: PROCESS (ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdmux_s, ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdreg_q, ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdmux_s IS
WHEN "0" => ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdmux_q <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdreg_q;
WHEN "1" => ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdmux_q <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem(DUALMEM,587)
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_reset0 <= areset;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_ia <= reg_zAddr_uid62_fpCosPiTest_0_to_memoryC2_uid209_sinPiZTableGenerator_0_q;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_aa <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdreg_q;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_ab <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdmux_q;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 7,
widthad_a => 2,
numwords_a => 3,
width_b => 7,
widthad_b => 2,
numwords_b => 3,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_iq,
address_a => ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_aa,
data_a => ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_ia
);
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_q <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_iq(6 downto 0);
--memoryC1_uid208_sinPiZTableGenerator(LOOKUP,207)@8
memoryC1_uid208_sinPiZTableGenerator: PROCESS (ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_q)
BEGIN
-- Begin reserved scope level
CASE (ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_q) IS
WHEN "0000000" => memoryC1_uid208_sinPiZTableGenerator_q <= "000000000000000000001";
WHEN "0000001" => memoryC1_uid208_sinPiZTableGenerator_q <= "111111101011010101010";
WHEN "0000010" => memoryC1_uid208_sinPiZTableGenerator_q <= "111111010110101010001";
WHEN "0000011" => memoryC1_uid208_sinPiZTableGenerator_q <= "111111000001111111100";
WHEN "0000100" => memoryC1_uid208_sinPiZTableGenerator_q <= "111110101101010101010";
WHEN "0000101" => memoryC1_uid208_sinPiZTableGenerator_q <= "111110011000101011101";
WHEN "0000110" => memoryC1_uid208_sinPiZTableGenerator_q <= "111110000100000010101";
WHEN "0000111" => memoryC1_uid208_sinPiZTableGenerator_q <= "111101101111011010001";
WHEN "0001000" => memoryC1_uid208_sinPiZTableGenerator_q <= "111101011010110010101";
WHEN "0001001" => memoryC1_uid208_sinPiZTableGenerator_q <= "111101000110001011111";
WHEN "0001010" => memoryC1_uid208_sinPiZTableGenerator_q <= "111100110001100110010";
WHEN "0001011" => memoryC1_uid208_sinPiZTableGenerator_q <= "111100011101000010000";
WHEN "0001100" => memoryC1_uid208_sinPiZTableGenerator_q <= "111100001000011110111";
WHEN "0001101" => memoryC1_uid208_sinPiZTableGenerator_q <= "111011110011111101011";
WHEN "0001110" => memoryC1_uid208_sinPiZTableGenerator_q <= "111011011111011101011";
WHEN "0001111" => memoryC1_uid208_sinPiZTableGenerator_q <= "111011001010111110111";
WHEN "0010000" => memoryC1_uid208_sinPiZTableGenerator_q <= "111010110110100010101";
WHEN "0010001" => memoryC1_uid208_sinPiZTableGenerator_q <= "111010100010000111100";
WHEN "0010010" => memoryC1_uid208_sinPiZTableGenerator_q <= "111010001101101111000";
WHEN "0010011" => memoryC1_uid208_sinPiZTableGenerator_q <= "111001111001011000011";
WHEN "0010100" => memoryC1_uid208_sinPiZTableGenerator_q <= "111001100101000100010";
WHEN "0010101" => memoryC1_uid208_sinPiZTableGenerator_q <= "111001010000110010001";
WHEN "0010110" => memoryC1_uid208_sinPiZTableGenerator_q <= "111000111100100010111";
WHEN "0010111" => memoryC1_uid208_sinPiZTableGenerator_q <= "111000101000010110001";
WHEN "0011000" => memoryC1_uid208_sinPiZTableGenerator_q <= "111000010100001011111";
WHEN "0011001" => memoryC1_uid208_sinPiZTableGenerator_q <= "111000000000000100110";
WHEN "0011010" => memoryC1_uid208_sinPiZTableGenerator_q <= "110111101100000000011";
WHEN "0011011" => memoryC1_uid208_sinPiZTableGenerator_q <= "110111010111111111000";
WHEN "0011100" => memoryC1_uid208_sinPiZTableGenerator_q <= "110111000100000001000";
WHEN "0011101" => memoryC1_uid208_sinPiZTableGenerator_q <= "110110110000000110101";
WHEN "0011110" => memoryC1_uid208_sinPiZTableGenerator_q <= "110110011100001110111";
WHEN "0011111" => memoryC1_uid208_sinPiZTableGenerator_q <= "110110001000011011000";
WHEN "0100000" => memoryC1_uid208_sinPiZTableGenerator_q <= "110101110100101011010";
WHEN "0100001" => memoryC1_uid208_sinPiZTableGenerator_q <= "110101100000111110101";
WHEN "0100010" => memoryC1_uid208_sinPiZTableGenerator_q <= "110101001101010110010";
WHEN "0100011" => memoryC1_uid208_sinPiZTableGenerator_q <= "110100111001110001011";
WHEN "0100100" => memoryC1_uid208_sinPiZTableGenerator_q <= "110100100110010001001";
WHEN "0100101" => memoryC1_uid208_sinPiZTableGenerator_q <= "110100010010110100110";
WHEN "0100110" => memoryC1_uid208_sinPiZTableGenerator_q <= "110011111111011100110";
WHEN "0100111" => memoryC1_uid208_sinPiZTableGenerator_q <= "110011101100001001010";
WHEN "0101000" => memoryC1_uid208_sinPiZTableGenerator_q <= "110011011000111010011";
WHEN "0101001" => memoryC1_uid208_sinPiZTableGenerator_q <= "110011000101101111111";
WHEN "0101010" => memoryC1_uid208_sinPiZTableGenerator_q <= "110010110010101010010";
WHEN "0101011" => memoryC1_uid208_sinPiZTableGenerator_q <= "110010011111101001101";
WHEN "0101100" => memoryC1_uid208_sinPiZTableGenerator_q <= "110010001100101110000";
WHEN "0101101" => memoryC1_uid208_sinPiZTableGenerator_q <= "110001111001110111001";
WHEN "0101110" => memoryC1_uid208_sinPiZTableGenerator_q <= "110001100111000110000";
WHEN "0101111" => memoryC1_uid208_sinPiZTableGenerator_q <= "110001010100011001011";
WHEN "0110000" => memoryC1_uid208_sinPiZTableGenerator_q <= "110001000001110010110";
WHEN "0110001" => memoryC1_uid208_sinPiZTableGenerator_q <= "110000101111010001100";
WHEN "0110010" => memoryC1_uid208_sinPiZTableGenerator_q <= "110000011100110110001";
WHEN "0110011" => memoryC1_uid208_sinPiZTableGenerator_q <= "110000001010011111111";
WHEN "0110100" => memoryC1_uid208_sinPiZTableGenerator_q <= "101111111000010000000";
WHEN "0110101" => memoryC1_uid208_sinPiZTableGenerator_q <= "101111100110000101100";
WHEN "0110110" => memoryC1_uid208_sinPiZTableGenerator_q <= "101111010100000001100";
WHEN "0110111" => memoryC1_uid208_sinPiZTableGenerator_q <= "101111000010000011001";
WHEN "0111000" => memoryC1_uid208_sinPiZTableGenerator_q <= "101110110000001011100";
WHEN "0111001" => memoryC1_uid208_sinPiZTableGenerator_q <= "101110011110011001110";
WHEN "0111010" => memoryC1_uid208_sinPiZTableGenerator_q <= "101110001100101110101";
WHEN "0111011" => memoryC1_uid208_sinPiZTableGenerator_q <= "101101111011001010001";
WHEN "0111100" => memoryC1_uid208_sinPiZTableGenerator_q <= "101101101001101100010";
WHEN "0111101" => memoryC1_uid208_sinPiZTableGenerator_q <= "101101011000010101010";
WHEN "0111110" => memoryC1_uid208_sinPiZTableGenerator_q <= "101101000111000100101";
WHEN "0111111" => memoryC1_uid208_sinPiZTableGenerator_q <= "101100110101111010111";
WHEN "1000000" => memoryC1_uid208_sinPiZTableGenerator_q <= "101100100100111000010";
WHEN "1000001" => memoryC1_uid208_sinPiZTableGenerator_q <= "101100010011111100111";
WHEN "1000010" => memoryC1_uid208_sinPiZTableGenerator_q <= "101100000011001000111";
WHEN "1000011" => memoryC1_uid208_sinPiZTableGenerator_q <= "101011110010011100000";
WHEN "1000100" => memoryC1_uid208_sinPiZTableGenerator_q <= "101011100001110110100";
WHEN "1000101" => memoryC1_uid208_sinPiZTableGenerator_q <= "101011010001011000100";
WHEN "1000110" => memoryC1_uid208_sinPiZTableGenerator_q <= "101011000001000001110";
WHEN "1000111" => memoryC1_uid208_sinPiZTableGenerator_q <= "101010110000110011000";
WHEN "1001000" => memoryC1_uid208_sinPiZTableGenerator_q <= "101010100000101011111";
WHEN "1001001" => memoryC1_uid208_sinPiZTableGenerator_q <= "101010010000101100100";
WHEN "1001010" => memoryC1_uid208_sinPiZTableGenerator_q <= "101010000000110101001";
WHEN "1001011" => memoryC1_uid208_sinPiZTableGenerator_q <= "101001110001000110000";
WHEN "1001100" => memoryC1_uid208_sinPiZTableGenerator_q <= "101001100001011110101";
WHEN "1001101" => memoryC1_uid208_sinPiZTableGenerator_q <= "101001010001111111111";
WHEN "1001110" => memoryC1_uid208_sinPiZTableGenerator_q <= "101001000010101000110";
WHEN "1001111" => memoryC1_uid208_sinPiZTableGenerator_q <= "101000110011011010001";
WHEN "1010000" => memoryC1_uid208_sinPiZTableGenerator_q <= "101000100100010100001";
WHEN "1010001" => memoryC1_uid208_sinPiZTableGenerator_q <= "101000010101010110100";
WHEN "1010010" => memoryC1_uid208_sinPiZTableGenerator_q <= "101000000110100001011";
WHEN "1010011" => memoryC1_uid208_sinPiZTableGenerator_q <= "100111110111110101011";
WHEN "1010100" => memoryC1_uid208_sinPiZTableGenerator_q <= "100111101001010010000";
WHEN "1010101" => memoryC1_uid208_sinPiZTableGenerator_q <= "100111011010110110110";
WHEN "1010110" => memoryC1_uid208_sinPiZTableGenerator_q <= "100111001100100101100";
WHEN "1010111" => memoryC1_uid208_sinPiZTableGenerator_q <= "100110111110011100011";
WHEN "1011000" => memoryC1_uid208_sinPiZTableGenerator_q <= "100110110000011100011";
WHEN "1011001" => memoryC1_uid208_sinPiZTableGenerator_q <= "100110100010100101110";
WHEN "1011010" => memoryC1_uid208_sinPiZTableGenerator_q <= "100110010100111000101";
WHEN "1011011" => memoryC1_uid208_sinPiZTableGenerator_q <= "100110000111010100001";
WHEN "1011100" => memoryC1_uid208_sinPiZTableGenerator_q <= "100101111001111001000";
WHEN "1011101" => memoryC1_uid208_sinPiZTableGenerator_q <= "100101101100100111111";
WHEN "1011110" => memoryC1_uid208_sinPiZTableGenerator_q <= "100101011111100000000";
WHEN "1011111" => memoryC1_uid208_sinPiZTableGenerator_q <= "100101010010100001001";
WHEN "1100000" => memoryC1_uid208_sinPiZTableGenerator_q <= "100101000101101100011";
WHEN "1100001" => memoryC1_uid208_sinPiZTableGenerator_q <= "100100111001000001011";
WHEN "1100010" => memoryC1_uid208_sinPiZTableGenerator_q <= "100100101100011111111";
WHEN "1100011" => memoryC1_uid208_sinPiZTableGenerator_q <= "100100100000001000010";
WHEN "1100100" => memoryC1_uid208_sinPiZTableGenerator_q <= "100100010011111010101";
WHEN "1100101" => memoryC1_uid208_sinPiZTableGenerator_q <= "100100000111110111001";
WHEN "1100110" => memoryC1_uid208_sinPiZTableGenerator_q <= "100011111011111101010";
WHEN "1100111" => memoryC1_uid208_sinPiZTableGenerator_q <= "100011110000001101010";
WHEN "1101000" => memoryC1_uid208_sinPiZTableGenerator_q <= "100011100100100111101";
WHEN "1101001" => memoryC1_uid208_sinPiZTableGenerator_q <= "100011011001001011111";
WHEN "1101010" => memoryC1_uid208_sinPiZTableGenerator_q <= "100011001101111011010";
WHEN "1101011" => memoryC1_uid208_sinPiZTableGenerator_q <= "100011000010110100001";
WHEN "1101100" => memoryC1_uid208_sinPiZTableGenerator_q <= "100010110111110111010";
WHEN "1101101" => memoryC1_uid208_sinPiZTableGenerator_q <= "100010101101000101000";
WHEN "1101110" => memoryC1_uid208_sinPiZTableGenerator_q <= "100010100010011101001";
WHEN "1101111" => memoryC1_uid208_sinPiZTableGenerator_q <= "100010011000000000001";
WHEN "1110000" => memoryC1_uid208_sinPiZTableGenerator_q <= "100010001101101101010";
WHEN "1110001" => memoryC1_uid208_sinPiZTableGenerator_q <= "100010000011100100111";
WHEN "1110010" => memoryC1_uid208_sinPiZTableGenerator_q <= "100001111001100111100";
WHEN "1110011" => memoryC1_uid208_sinPiZTableGenerator_q <= "100001101111110100101";
WHEN "1110100" => memoryC1_uid208_sinPiZTableGenerator_q <= "100001100110001100100";
WHEN "1110101" => memoryC1_uid208_sinPiZTableGenerator_q <= "100001011100101111001";
WHEN "1110110" => memoryC1_uid208_sinPiZTableGenerator_q <= "100001010011011100011";
WHEN "1110111" => memoryC1_uid208_sinPiZTableGenerator_q <= "100001001010010100101";
WHEN "1111000" => memoryC1_uid208_sinPiZTableGenerator_q <= "100001000001011000000";
WHEN "1111001" => memoryC1_uid208_sinPiZTableGenerator_q <= "100000111000100110100";
WHEN "1111010" => memoryC1_uid208_sinPiZTableGenerator_q <= "100000101111111111100";
WHEN "1111011" => memoryC1_uid208_sinPiZTableGenerator_q <= "100000100111100011111";
WHEN "1111100" => memoryC1_uid208_sinPiZTableGenerator_q <= "100000011111010011000";
WHEN "1111101" => memoryC1_uid208_sinPiZTableGenerator_q <= "100000010111001101010";
WHEN "1111110" => memoryC1_uid208_sinPiZTableGenerator_q <= "100000001111010010101";
WHEN "1111111" => memoryC1_uid208_sinPiZTableGenerator_q <= "100000000111100011001";
WHEN OTHERS =>
memoryC1_uid208_sinPiZTableGenerator_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--sumAHighB_uid214_sinPiZPolyEval(ADD,213)@8
sumAHighB_uid214_sinPiZPolyEval_a <= STD_LOGIC_VECTOR((21 downto 21 => memoryC1_uid208_sinPiZTableGenerator_q(20)) & memoryC1_uid208_sinPiZTableGenerator_q);
sumAHighB_uid214_sinPiZPolyEval_b <= STD_LOGIC_VECTOR((21 downto 14 => highBBits_uid213_sinPiZPolyEval_b(13)) & highBBits_uid213_sinPiZPolyEval_b);
sumAHighB_uid214_sinPiZPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid214_sinPiZPolyEval_a) + SIGNED(sumAHighB_uid214_sinPiZPolyEval_b));
sumAHighB_uid214_sinPiZPolyEval_q <= sumAHighB_uid214_sinPiZPolyEval_o(21 downto 0);
--lowRangeB_uid212_sinPiZPolyEval(BITSELECT,211)@8
lowRangeB_uid212_sinPiZPolyEval_in <= prodXYTruncFR_uid227_pT1_uid211_sinPiZPolyEval_b(0 downto 0);
lowRangeB_uid212_sinPiZPolyEval_b <= lowRangeB_uid212_sinPiZPolyEval_in(0 downto 0);
--s1_uid212_uid215_sinPiZPolyEval(BITJOIN,214)@8
s1_uid212_uid215_sinPiZPolyEval_q <= sumAHighB_uid214_sinPiZPolyEval_q & lowRangeB_uid212_sinPiZPolyEval_b;
--reg_s1_uid212_uid215_sinPiZPolyEval_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_1(REG,267)@8
reg_s1_uid212_uid215_sinPiZPolyEval_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_s1_uid212_uid215_sinPiZPolyEval_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_1_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_s1_uid212_uid215_sinPiZPolyEval_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_1_q <= s1_uid212_uid215_sinPiZPolyEval_q;
END IF;
END IF;
END PROCESS;
--ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_nor(LOGICAL,609)
ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_nor_a <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_notEnable_q;
ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_nor_b <= ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_sticky_ena_q;
ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_nor_q <= not (ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_nor_a or ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_nor_b);
--ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_sticky_ena(REG,610)
ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_nor_q = "1") THEN
ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_sticky_ena_q <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_enaAnd(LOGICAL,611)
ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_enaAnd_a <= ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_sticky_ena_q;
ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_enaAnd_b <= en;
ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_enaAnd_q <= ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_enaAnd_a and ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_enaAnd_b;
--ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_inputreg(DELAY,599)
ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 16, depth => 1 )
PORT MAP ( xin => zPPolyEval_uid63_fpCosPiTest_b, xout => ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem(DUALMEM,600)
ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_reset0 <= areset;
ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_ia <= ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_inputreg_q;
ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_aa <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdreg_q;
ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_ab <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdmux_q;
ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 16,
widthad_a => 2,
numwords_a => 3,
width_b => 16,
widthad_b => 2,
numwords_b => 3,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_iq,
address_a => ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_aa,
data_a => ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_ia
);
ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_q <= ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_iq(15 downto 0);
--reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0(REG,266)@8
reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_q <= ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--prodXY_uid229_pT2_uid217_sinPiZPolyEval(MULT,228)@9
prodXY_uid229_pT2_uid217_sinPiZPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid229_pT2_uid217_sinPiZPolyEval_a),17)) * SIGNED(prodXY_uid229_pT2_uid217_sinPiZPolyEval_b);
prodXY_uid229_pT2_uid217_sinPiZPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid229_pT2_uid217_sinPiZPolyEval_a <= (others => '0');
prodXY_uid229_pT2_uid217_sinPiZPolyEval_b <= (others => '0');
prodXY_uid229_pT2_uid217_sinPiZPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid229_pT2_uid217_sinPiZPolyEval_a <= reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_q;
prodXY_uid229_pT2_uid217_sinPiZPolyEval_b <= reg_s1_uid212_uid215_sinPiZPolyEval_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_1_q;
prodXY_uid229_pT2_uid217_sinPiZPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid229_pT2_uid217_sinPiZPolyEval_pr,39));
END IF;
END IF;
END PROCESS;
prodXY_uid229_pT2_uid217_sinPiZPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid229_pT2_uid217_sinPiZPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid229_pT2_uid217_sinPiZPolyEval_q <= prodXY_uid229_pT2_uid217_sinPiZPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid230_pT2_uid217_sinPiZPolyEval(BITSELECT,229)@12
prodXYTruncFR_uid230_pT2_uid217_sinPiZPolyEval_in <= prodXY_uid229_pT2_uid217_sinPiZPolyEval_q;
prodXYTruncFR_uid230_pT2_uid217_sinPiZPolyEval_b <= prodXYTruncFR_uid230_pT2_uid217_sinPiZPolyEval_in(38 downto 15);
--highBBits_uid219_sinPiZPolyEval(BITSELECT,218)@12
highBBits_uid219_sinPiZPolyEval_in <= prodXYTruncFR_uid230_pT2_uid217_sinPiZPolyEval_b;
highBBits_uid219_sinPiZPolyEval_b <= highBBits_uid219_sinPiZPolyEval_in(23 downto 2);
--ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_nor(LOGICAL,584)
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_nor_a <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_notEnable_q;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_nor_b <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_sticky_ena_q;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_nor_q <= not (ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_nor_a or ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_nor_b);
--ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_mem_top(CONSTANT,554)
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_mem_top_q <= "0110";
--ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_cmp(LOGICAL,555)
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_cmp_a <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_mem_top_q;
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdmux_q);
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_cmp_q <= "1" when ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_cmp_a = ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_cmp_b else "0";
--ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_cmpReg(REG,556)
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_cmpReg_q <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_sticky_ena(REG,585)
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_nor_q = "1") THEN
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_sticky_ena_q <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_enaAnd(LOGICAL,586)
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_enaAnd_a <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_sticky_ena_q;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_enaAnd_b <= en;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_enaAnd_q <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_enaAnd_a and ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_enaAnd_b;
--ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt(COUNTER,550)
-- every=1, low=0, high=6, step=1, init=1
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt_i = 5 THEN
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt_eq <= '1';
ELSE
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt_eq = '1') THEN
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt_i <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt_i - 6;
ELSE
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt_i <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt_i,3));
--ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdreg(REG,551)
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdreg_q <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdmux(MUX,552)
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdmux_s <= en;
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdmux: PROCESS (ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdmux_s, ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdreg_q, ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt_q)
BEGIN
CASE ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdmux_s IS
WHEN "0" => ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdmux_q <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdreg_q;
WHEN "1" => ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdmux_q <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem(DUALMEM,575)
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_reset0 <= areset;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_ia <= reg_zAddr_uid62_fpCosPiTest_0_to_memoryC2_uid209_sinPiZTableGenerator_0_q;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_aa <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdreg_q;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_ab <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdmux_q;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 7,
widthad_a => 3,
numwords_a => 7,
width_b => 7,
widthad_b => 3,
numwords_b => 7,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_iq,
address_a => ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_aa,
data_a => ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_ia
);
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_q <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_iq(6 downto 0);
--memoryC0_uid207_sinPiZTableGenerator(LOOKUP,206)@12
memoryC0_uid207_sinPiZTableGenerator: PROCESS (ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_q)
BEGIN
-- Begin reserved scope level
CASE (ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_q) IS
WHEN "0000000" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100100100001111110110101110";
WHEN "0000001" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100100100001110100100000010";
WHEN "0000010" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100100100001010101100000000";
WHEN "0000011" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100100100000100001110101000";
WHEN "0000100" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100100011111011001011111101";
WHEN "0000101" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100100011101111100100000010";
WHEN "0000110" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100100011100001010110111011";
WHEN "0000111" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100100011010000100100101111";
WHEN "0001000" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100100010111101001101100010";
WHEN "0001001" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100100010100111010001011101";
WHEN "0001010" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100100010001110110000100111";
WHEN "0001011" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100100001110011101011001001";
WHEN "0001100" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100100001010110000001001110";
WHEN "0001101" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100100000110101110011000000";
WHEN "0001110" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100100000010011000000101011";
WHEN "0001111" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100011111101101101010011101";
WHEN "0010000" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100011111000101110000100010";
WHEN "0010001" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100011110011011010011001011";
WHEN "0010010" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100011101101110010010100101";
WHEN "0010011" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100011100111110101111000011";
WHEN "0010100" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100011100001100101000110101";
WHEN "0010101" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100011011011000000000001111";
WHEN "0010110" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100011010100000110101100011";
WHEN "0010111" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100011001100111001001000110";
WHEN "0011000" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100011000101010111011001110";
WHEN "0011001" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100010111101100001100010000";
WHEN "0011010" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100010110101010111100100100";
WHEN "0011011" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100010101100111001100100010";
WHEN "0011100" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100010100100000111100100011";
WHEN "0011101" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100010011011000001101000000";
WHEN "0011110" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100010010001100111110010110";
WHEN "0011111" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100010000111111010000111111";
WHEN "0100000" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100001111101111000101010111";
WHEN "0100001" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100001110011100011011111110";
WHEN "0100010" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100001101000111010101010001";
WHEN "0100011" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100001011101111110001110000";
WHEN "0100100" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100001010010101110001111010";
WHEN "0100101" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100001000111001010110010010";
WHEN "0100110" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100000111011010011111011001";
WHEN "0100111" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100000101111001001101110010";
WHEN "0101000" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100000100010101100010000001";
WHEN "0101001" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100000010101111011100101011";
WHEN "0101010" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100000001000110111110010101";
WHEN "0101011" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011111111011100000111100110";
WHEN "0101100" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011111101101110111001000101";
WHEN "0101101" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011111011111111010011011011";
WHEN "0101110" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011111010001101010111001111";
WHEN "0101111" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011111000011001000101001110";
WHEN "0110000" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011110110100010011110000000";
WHEN "0110001" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011110100101001100010010010";
WHEN "0110010" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011110010101110010010110000";
WHEN "0110011" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011110000110000110000001000";
WHEN "0110100" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011101110110000111011000111";
WHEN "0110101" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011101100101110110100011101";
WHEN "0110110" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011101010101010011100111001";
WHEN "0110111" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011101000100011110101001100";
WHEN "0111000" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011100110011010111110000111";
WHEN "0111001" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011100100001111111000011101";
WHEN "0111010" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011100010000010100101000000";
WHEN "0111011" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011011111110011000100100100";
WHEN "0111100" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011011101100001010111111110";
WHEN "0111101" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011011011001101100000000011";
WHEN "0111110" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011011000110111011101101010";
WHEN "0111111" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011010110011111010001101001";
WHEN "1000000" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011010100000100111100111000";
WHEN "1000001" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011010001101000100000001111";
WHEN "1000010" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011001111001001111100100111";
WHEN "1000011" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011001100101001010010111011";
WHEN "1000100" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011001010000110100100000101";
WHEN "1000101" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011000111100001110001000001";
WHEN "1000110" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011000100111010111010101011";
WHEN "1000111" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011000010010010000001111111";
WHEN "1001000" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010111111100111000111111011";
WHEN "1001001" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010111100111010001101011110";
WHEN "1001010" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010111010001011010011100110";
WHEN "1001011" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010110111011010011011010011";
WHEN "1001100" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010110100100111100101100110";
WHEN "1001101" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010110001110010110011011111";
WHEN "1001110" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010101110111100000110000001";
WHEN "1001111" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010101100000011011110001110";
WHEN "1010000" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010101001001000111101001000";
WHEN "1010001" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010100110001100100011110100";
WHEN "1010010" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010100011001110010011010110";
WHEN "1010011" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010100000001110001100110010";
WHEN "1010100" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010011101001100010001001111";
WHEN "1010101" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010011010001000100001110100";
WHEN "1010110" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010010111000010111111100101";
WHEN "1010111" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010010011111011101011101100";
WHEN "1011000" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010010000110010100111010001";
WHEN "1011001" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010001101100111110011011011";
WHEN "1011010" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010001010011011010001010100";
WHEN "1011011" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010000111001101000010000111";
WHEN "1011100" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010000011111101000110111110";
WHEN "1011101" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010000000101011100001000010";
WHEN "1011110" => memoryC0_uid207_sinPiZTableGenerator_q <= "01001111101011000010001100001";
WHEN "1011111" => memoryC0_uid207_sinPiZTableGenerator_q <= "01001111010000011011001100111";
WHEN "1100000" => memoryC0_uid207_sinPiZTableGenerator_q <= "01001110110101100111010011111";
WHEN "1100001" => memoryC0_uid207_sinPiZTableGenerator_q <= "01001110011010100110101010111";
WHEN "1100010" => memoryC0_uid207_sinPiZTableGenerator_q <= "01001101111111011001011011101";
WHEN "1100011" => memoryC0_uid207_sinPiZTableGenerator_q <= "01001101100011111111101111111";
WHEN "1100100" => memoryC0_uid207_sinPiZTableGenerator_q <= "01001101001000011001110001011";
WHEN "1100101" => memoryC0_uid207_sinPiZTableGenerator_q <= "01001100101100100111101010001";
WHEN "1100110" => memoryC0_uid207_sinPiZTableGenerator_q <= "01001100010000101001100100001";
WHEN "1100111" => memoryC0_uid207_sinPiZTableGenerator_q <= "01001011110100011111101001011";
WHEN "1101000" => memoryC0_uid207_sinPiZTableGenerator_q <= "01001011011000001010000011111";
WHEN "1101001" => memoryC0_uid207_sinPiZTableGenerator_q <= "01001010111011101000111101111";
WHEN "1101010" => memoryC0_uid207_sinPiZTableGenerator_q <= "01001010011110111100100001011";
WHEN "1101011" => memoryC0_uid207_sinPiZTableGenerator_q <= "01001010000010000100111000111";
WHEN "1101100" => memoryC0_uid207_sinPiZTableGenerator_q <= "01001001100101000010001110101";
WHEN "1101101" => memoryC0_uid207_sinPiZTableGenerator_q <= "01001001000111110100101100111";
WHEN "1101110" => memoryC0_uid207_sinPiZTableGenerator_q <= "01001000101010011100011110001";
WHEN "1101111" => memoryC0_uid207_sinPiZTableGenerator_q <= "01001000001100111001101100110";
WHEN "1110000" => memoryC0_uid207_sinPiZTableGenerator_q <= "01000111101111001100100011011";
WHEN "1110001" => memoryC0_uid207_sinPiZTableGenerator_q <= "01000111010001010101001100101";
WHEN "1110010" => memoryC0_uid207_sinPiZTableGenerator_q <= "01000110110011010011110010111";
WHEN "1110011" => memoryC0_uid207_sinPiZTableGenerator_q <= "01000110010101001000100001000";
WHEN "1110100" => memoryC0_uid207_sinPiZTableGenerator_q <= "01000101110110110011100001101";
WHEN "1110101" => memoryC0_uid207_sinPiZTableGenerator_q <= "01000101011000010100111111100";
WHEN "1110110" => memoryC0_uid207_sinPiZTableGenerator_q <= "01000100111001101101000101100";
WHEN "1110111" => memoryC0_uid207_sinPiZTableGenerator_q <= "01000100011010111011111110011";
WHEN "1111000" => memoryC0_uid207_sinPiZTableGenerator_q <= "01000011111100000001110101000";
WHEN "1111001" => memoryC0_uid207_sinPiZTableGenerator_q <= "01000011011100111110110100010";
WHEN "1111010" => memoryC0_uid207_sinPiZTableGenerator_q <= "01000010111101110011000111010";
WHEN "1111011" => memoryC0_uid207_sinPiZTableGenerator_q <= "01000010011110011110111000111";
WHEN "1111100" => memoryC0_uid207_sinPiZTableGenerator_q <= "01000001111111000010010100010";
WHEN "1111101" => memoryC0_uid207_sinPiZTableGenerator_q <= "01000001011111011101100100011";
WHEN "1111110" => memoryC0_uid207_sinPiZTableGenerator_q <= "01000000111111110000110100011";
WHEN "1111111" => memoryC0_uid207_sinPiZTableGenerator_q <= "01000000011111111100001111011";
WHEN OTHERS =>
memoryC0_uid207_sinPiZTableGenerator_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--sumAHighB_uid220_sinPiZPolyEval(ADD,219)@12
sumAHighB_uid220_sinPiZPolyEval_a <= STD_LOGIC_VECTOR((29 downto 29 => memoryC0_uid207_sinPiZTableGenerator_q(28)) & memoryC0_uid207_sinPiZTableGenerator_q);
sumAHighB_uid220_sinPiZPolyEval_b <= STD_LOGIC_VECTOR((29 downto 22 => highBBits_uid219_sinPiZPolyEval_b(21)) & highBBits_uid219_sinPiZPolyEval_b);
sumAHighB_uid220_sinPiZPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid220_sinPiZPolyEval_a) + SIGNED(sumAHighB_uid220_sinPiZPolyEval_b));
sumAHighB_uid220_sinPiZPolyEval_q <= sumAHighB_uid220_sinPiZPolyEval_o(29 downto 0);
--lowRangeB_uid218_sinPiZPolyEval(BITSELECT,217)@12
lowRangeB_uid218_sinPiZPolyEval_in <= prodXYTruncFR_uid230_pT2_uid217_sinPiZPolyEval_b(1 downto 0);
lowRangeB_uid218_sinPiZPolyEval_b <= lowRangeB_uid218_sinPiZPolyEval_in(1 downto 0);
--s2_uid218_uid221_sinPiZPolyEval(BITJOIN,220)@12
s2_uid218_uid221_sinPiZPolyEval_q <= sumAHighB_uid220_sinPiZPolyEval_q & lowRangeB_uid218_sinPiZPolyEval_b;
--fxpSinRes_uid65_fpCosPiTest(BITSELECT,64)@12
fxpSinRes_uid65_fpCosPiTest_in <= s2_uid218_uid221_sinPiZPolyEval_q(29 downto 0);
fxpSinRes_uid65_fpCosPiTest_b <= fxpSinRes_uid65_fpCosPiTest_in(29 downto 5);
--reg_fxpSinRes_uid65_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_1(REG,270)@12
reg_fxpSinRes_uid65_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fxpSinRes_uid65_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_1_q <= "0000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fxpSinRes_uid65_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_1_q <= fxpSinRes_uid65_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_nor(LOGICAL,622)
ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_nor_a <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_notEnable_q;
ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_nor_b <= ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_sticky_ena_q;
ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_nor_q <= not (ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_nor_a or ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_nor_b);
--ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_sticky_ena(REG,623)
ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_nor_q = "1") THEN
ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_sticky_ena_q <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_enaAnd(LOGICAL,624)
ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_enaAnd_a <= ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_sticky_ena_q;
ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_enaAnd_b <= en;
ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_enaAnd_q <= ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_enaAnd_a and ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_enaAnd_b;
--LeftShiftStage131dto0_uid202_alignedZ_uid57_fpCosPiTest(BITSELECT,201)@7
LeftShiftStage131dto0_uid202_alignedZ_uid57_fpCosPiTest_in <= leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_q(31 downto 0);
LeftShiftStage131dto0_uid202_alignedZ_uid57_fpCosPiTest_b <= LeftShiftStage131dto0_uid202_alignedZ_uid57_fpCosPiTest_in(31 downto 0);
--leftShiftStage2Idx3_uid203_alignedZ_uid57_fpCosPiTest(BITJOIN,202)@7
leftShiftStage2Idx3_uid203_alignedZ_uid57_fpCosPiTest_q <= LeftShiftStage131dto0_uid202_alignedZ_uid57_fpCosPiTest_b & leftShiftStage2Idx3Pad3_uid131_fxpX_uid41_fpCosPiTest_q;
--LeftShiftStage132dto0_uid199_alignedZ_uid57_fpCosPiTest(BITSELECT,198)@7
LeftShiftStage132dto0_uid199_alignedZ_uid57_fpCosPiTest_in <= leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_q(32 downto 0);
LeftShiftStage132dto0_uid199_alignedZ_uid57_fpCosPiTest_b <= LeftShiftStage132dto0_uid199_alignedZ_uid57_fpCosPiTest_in(32 downto 0);
--leftShiftStage2Idx2_uid200_alignedZ_uid57_fpCosPiTest(BITJOIN,199)@7
leftShiftStage2Idx2_uid200_alignedZ_uid57_fpCosPiTest_q <= LeftShiftStage132dto0_uid199_alignedZ_uid57_fpCosPiTest_b & leftShiftStage2Idx2Pad2_uid128_fxpX_uid41_fpCosPiTest_q;
--LeftShiftStage133dto0_uid196_alignedZ_uid57_fpCosPiTest(BITSELECT,195)@7
LeftShiftStage133dto0_uid196_alignedZ_uid57_fpCosPiTest_in <= leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_q(33 downto 0);
LeftShiftStage133dto0_uid196_alignedZ_uid57_fpCosPiTest_b <= LeftShiftStage133dto0_uid196_alignedZ_uid57_fpCosPiTest_in(33 downto 0);
--leftShiftStage2Idx1_uid197_alignedZ_uid57_fpCosPiTest(BITJOIN,196)@7
leftShiftStage2Idx1_uid197_alignedZ_uid57_fpCosPiTest_q <= LeftShiftStage133dto0_uid196_alignedZ_uid57_fpCosPiTest_b & GND_q;
--vStage_uid141_lzcZ_uid56_fpCosPiTest(BITSELECT,140)@3
vStage_uid141_lzcZ_uid56_fpCosPiTest_in <= z_uid54_fpCosPiTest_b(2 downto 0);
vStage_uid141_lzcZ_uid56_fpCosPiTest_b <= vStage_uid141_lzcZ_uid56_fpCosPiTest_in(2 downto 0);
--ld_vStage_uid141_lzcZ_uid56_fpCosPiTest_b_to_leftShiftStage0Idx2_uid180_alignedZ_uid57_fpCosPiTest_b(DELAY,450)@3
ld_vStage_uid141_lzcZ_uid56_fpCosPiTest_b_to_leftShiftStage0Idx2_uid180_alignedZ_uid57_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 3, depth => 3 )
PORT MAP ( xin => vStage_uid141_lzcZ_uid56_fpCosPiTest_b, xout => ld_vStage_uid141_lzcZ_uid56_fpCosPiTest_b_to_leftShiftStage0Idx2_uid180_alignedZ_uid57_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage0Idx2_uid180_alignedZ_uid57_fpCosPiTest(BITJOIN,179)@6
leftShiftStage0Idx2_uid180_alignedZ_uid57_fpCosPiTest_q <= ld_vStage_uid141_lzcZ_uid56_fpCosPiTest_b_to_leftShiftStage0Idx2_uid180_alignedZ_uid57_fpCosPiTest_b_q & leftShiftStage0Idx2Pad32_uid108_fxpX_uid41_fpCosPiTest_q;
--X18dto0_uid176_alignedZ_uid57_fpCosPiTest(BITSELECT,175)@3
X18dto0_uid176_alignedZ_uid57_fpCosPiTest_in <= z_uid54_fpCosPiTest_b(18 downto 0);
X18dto0_uid176_alignedZ_uid57_fpCosPiTest_b <= X18dto0_uid176_alignedZ_uid57_fpCosPiTest_in(18 downto 0);
--ld_X18dto0_uid176_alignedZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx1_uid177_alignedZ_uid57_fpCosPiTest_b_inputreg(DELAY,573)
ld_X18dto0_uid176_alignedZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx1_uid177_alignedZ_uid57_fpCosPiTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 19, depth => 1 )
PORT MAP ( xin => X18dto0_uid176_alignedZ_uid57_fpCosPiTest_b, xout => ld_X18dto0_uid176_alignedZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx1_uid177_alignedZ_uid57_fpCosPiTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_X18dto0_uid176_alignedZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx1_uid177_alignedZ_uid57_fpCosPiTest_b(DELAY,449)@3
ld_X18dto0_uid176_alignedZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx1_uid177_alignedZ_uid57_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 19, depth => 2 )
PORT MAP ( xin => ld_X18dto0_uid176_alignedZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx1_uid177_alignedZ_uid57_fpCosPiTest_b_inputreg_q, xout => ld_X18dto0_uid176_alignedZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx1_uid177_alignedZ_uid57_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage0Idx1_uid177_alignedZ_uid57_fpCosPiTest(BITJOIN,176)@6
leftShiftStage0Idx1_uid177_alignedZ_uid57_fpCosPiTest_q <= ld_X18dto0_uid176_alignedZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx1_uid177_alignedZ_uid57_fpCosPiTest_b_q & leftShiftStage0Idx1Pad16_uid105_fxpX_uid41_fpCosPiTest_q;
--ld_z_uid54_fpCosPiTest_b_to_leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_c_inputreg(DELAY,574)
ld_z_uid54_fpCosPiTest_b_to_leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 35, depth => 1 )
PORT MAP ( xin => z_uid54_fpCosPiTest_b, xout => ld_z_uid54_fpCosPiTest_b_to_leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_z_uid54_fpCosPiTest_b_to_leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_c(DELAY,453)@3
ld_z_uid54_fpCosPiTest_b_to_leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_c : dspba_delay
GENERIC MAP ( width => 35, depth => 2 )
PORT MAP ( xin => ld_z_uid54_fpCosPiTest_b_to_leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_c_inputreg_q, xout => ld_z_uid54_fpCosPiTest_b_to_leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--rVStage_uid138_lzcZ_uid56_fpCosPiTest(BITSELECT,137)@3
rVStage_uid138_lzcZ_uid56_fpCosPiTest_in <= z_uid54_fpCosPiTest_b;
rVStage_uid138_lzcZ_uid56_fpCosPiTest_b <= rVStage_uid138_lzcZ_uid56_fpCosPiTest_in(34 downto 3);
--reg_rVStage_uid138_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid139_lzcZ_uid56_fpCosPiTest_1(REG,247)@3
reg_rVStage_uid138_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid139_lzcZ_uid56_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid138_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid139_lzcZ_uid56_fpCosPiTest_1_q <= "00000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid138_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid139_lzcZ_uid56_fpCosPiTest_1_q <= rVStage_uid138_lzcZ_uid56_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid139_lzcZ_uid56_fpCosPiTest(LOGICAL,138)@4
vCount_uid139_lzcZ_uid56_fpCosPiTest_a <= reg_rVStage_uid138_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid139_lzcZ_uid56_fpCosPiTest_1_q;
vCount_uid139_lzcZ_uid56_fpCosPiTest_b <= leftShiftStage0Idx2Pad32_uid108_fxpX_uid41_fpCosPiTest_q;
vCount_uid139_lzcZ_uid56_fpCosPiTest_q <= "1" when vCount_uid139_lzcZ_uid56_fpCosPiTest_a = vCount_uid139_lzcZ_uid56_fpCosPiTest_b else "0";
--ld_vCount_uid139_lzcZ_uid56_fpCosPiTest_q_to_r_uid172_lzcZ_uid56_fpCosPiTest_f(DELAY,447)@4
ld_vCount_uid139_lzcZ_uid56_fpCosPiTest_q_to_r_uid172_lzcZ_uid56_fpCosPiTest_f : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => vCount_uid139_lzcZ_uid56_fpCosPiTest_q, xout => ld_vCount_uid139_lzcZ_uid56_fpCosPiTest_q_to_r_uid172_lzcZ_uid56_fpCosPiTest_f_q, ena => en(0), clk => clk, aclr => areset );
--mO_uid140_lzcZ_uid56_fpCosPiTest(CONSTANT,139)
mO_uid140_lzcZ_uid56_fpCosPiTest_q <= "11111111111111111111111111111";
--cStage_uid142_lzcZ_uid56_fpCosPiTest(BITJOIN,141)@3
cStage_uid142_lzcZ_uid56_fpCosPiTest_q <= vStage_uid141_lzcZ_uid56_fpCosPiTest_b & mO_uid140_lzcZ_uid56_fpCosPiTest_q;
--reg_cStage_uid142_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid144_lzcZ_uid56_fpCosPiTest_3(REG,249)@3
reg_cStage_uid142_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid144_lzcZ_uid56_fpCosPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cStage_uid142_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid144_lzcZ_uid56_fpCosPiTest_3_q <= "00000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cStage_uid142_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid144_lzcZ_uid56_fpCosPiTest_3_q <= cStage_uid142_lzcZ_uid56_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--vStagei_uid144_lzcZ_uid56_fpCosPiTest(MUX,143)@4
vStagei_uid144_lzcZ_uid56_fpCosPiTest_s <= vCount_uid139_lzcZ_uid56_fpCosPiTest_q;
vStagei_uid144_lzcZ_uid56_fpCosPiTest: PROCESS (vStagei_uid144_lzcZ_uid56_fpCosPiTest_s, en, reg_rVStage_uid138_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid139_lzcZ_uid56_fpCosPiTest_1_q, reg_cStage_uid142_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid144_lzcZ_uid56_fpCosPiTest_3_q)
BEGIN
CASE vStagei_uid144_lzcZ_uid56_fpCosPiTest_s IS
WHEN "0" => vStagei_uid144_lzcZ_uid56_fpCosPiTest_q <= reg_rVStage_uid138_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid139_lzcZ_uid56_fpCosPiTest_1_q;
WHEN "1" => vStagei_uid144_lzcZ_uid56_fpCosPiTest_q <= reg_cStage_uid142_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid144_lzcZ_uid56_fpCosPiTest_3_q;
WHEN OTHERS => vStagei_uid144_lzcZ_uid56_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid146_lzcZ_uid56_fpCosPiTest(BITSELECT,145)@4
rVStage_uid146_lzcZ_uid56_fpCosPiTest_in <= vStagei_uid144_lzcZ_uid56_fpCosPiTest_q;
rVStage_uid146_lzcZ_uid56_fpCosPiTest_b <= rVStage_uid146_lzcZ_uid56_fpCosPiTest_in(31 downto 16);
--reg_rVStage_uid146_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid147_lzcZ_uid56_fpCosPiTest_1(REG,250)@4
reg_rVStage_uid146_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid147_lzcZ_uid56_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid146_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid147_lzcZ_uid56_fpCosPiTest_1_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid146_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid147_lzcZ_uid56_fpCosPiTest_1_q <= rVStage_uid146_lzcZ_uid56_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid147_lzcZ_uid56_fpCosPiTest(LOGICAL,146)@5
vCount_uid147_lzcZ_uid56_fpCosPiTest_a <= reg_rVStage_uid146_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid147_lzcZ_uid56_fpCosPiTest_1_q;
vCount_uid147_lzcZ_uid56_fpCosPiTest_b <= leftShiftStage0Idx1Pad16_uid105_fxpX_uid41_fpCosPiTest_q;
vCount_uid147_lzcZ_uid56_fpCosPiTest_q <= "1" when vCount_uid147_lzcZ_uid56_fpCosPiTest_a = vCount_uid147_lzcZ_uid56_fpCosPiTest_b else "0";
--ld_vCount_uid147_lzcZ_uid56_fpCosPiTest_q_to_r_uid172_lzcZ_uid56_fpCosPiTest_e(DELAY,446)@5
ld_vCount_uid147_lzcZ_uid56_fpCosPiTest_q_to_r_uid172_lzcZ_uid56_fpCosPiTest_e : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vCount_uid147_lzcZ_uid56_fpCosPiTest_q, xout => ld_vCount_uid147_lzcZ_uid56_fpCosPiTest_q_to_r_uid172_lzcZ_uid56_fpCosPiTest_e_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid148_lzcZ_uid56_fpCosPiTest(BITSELECT,147)@4
vStage_uid148_lzcZ_uid56_fpCosPiTest_in <= vStagei_uid144_lzcZ_uid56_fpCosPiTest_q(15 downto 0);
vStage_uid148_lzcZ_uid56_fpCosPiTest_b <= vStage_uid148_lzcZ_uid56_fpCosPiTest_in(15 downto 0);
--reg_vStage_uid148_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid150_lzcZ_uid56_fpCosPiTest_3(REG,252)@4
reg_vStage_uid148_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid150_lzcZ_uid56_fpCosPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid148_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid150_lzcZ_uid56_fpCosPiTest_3_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid148_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid150_lzcZ_uid56_fpCosPiTest_3_q <= vStage_uid148_lzcZ_uid56_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid150_lzcZ_uid56_fpCosPiTest(MUX,149)@5
vStagei_uid150_lzcZ_uid56_fpCosPiTest_s <= vCount_uid147_lzcZ_uid56_fpCosPiTest_q;
vStagei_uid150_lzcZ_uid56_fpCosPiTest: PROCESS (vStagei_uid150_lzcZ_uid56_fpCosPiTest_s, en, reg_rVStage_uid146_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid147_lzcZ_uid56_fpCosPiTest_1_q, reg_vStage_uid148_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid150_lzcZ_uid56_fpCosPiTest_3_q)
BEGIN
CASE vStagei_uid150_lzcZ_uid56_fpCosPiTest_s IS
WHEN "0" => vStagei_uid150_lzcZ_uid56_fpCosPiTest_q <= reg_rVStage_uid146_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid147_lzcZ_uid56_fpCosPiTest_1_q;
WHEN "1" => vStagei_uid150_lzcZ_uid56_fpCosPiTest_q <= reg_vStage_uid148_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid150_lzcZ_uid56_fpCosPiTest_3_q;
WHEN OTHERS => vStagei_uid150_lzcZ_uid56_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid152_lzcZ_uid56_fpCosPiTest(BITSELECT,151)@5
rVStage_uid152_lzcZ_uid56_fpCosPiTest_in <= vStagei_uid150_lzcZ_uid56_fpCosPiTest_q;
rVStage_uid152_lzcZ_uid56_fpCosPiTest_b <= rVStage_uid152_lzcZ_uid56_fpCosPiTest_in(15 downto 8);
--vCount_uid153_lzcZ_uid56_fpCosPiTest(LOGICAL,152)@5
vCount_uid153_lzcZ_uid56_fpCosPiTest_a <= rVStage_uid152_lzcZ_uid56_fpCosPiTest_b;
vCount_uid153_lzcZ_uid56_fpCosPiTest_b <= cstAllZWE_uid21_fpCosPiTest_q;
vCount_uid153_lzcZ_uid56_fpCosPiTest_q <= "1" when vCount_uid153_lzcZ_uid56_fpCosPiTest_a = vCount_uid153_lzcZ_uid56_fpCosPiTest_b else "0";
--reg_vCount_uid153_lzcZ_uid56_fpCosPiTest_0_to_r_uid172_lzcZ_uid56_fpCosPiTest_3(REG,256)@5
reg_vCount_uid153_lzcZ_uid56_fpCosPiTest_0_to_r_uid172_lzcZ_uid56_fpCosPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid153_lzcZ_uid56_fpCosPiTest_0_to_r_uid172_lzcZ_uid56_fpCosPiTest_3_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid153_lzcZ_uid56_fpCosPiTest_0_to_r_uid172_lzcZ_uid56_fpCosPiTest_3_q <= vCount_uid153_lzcZ_uid56_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--vStage_uid154_lzcZ_uid56_fpCosPiTest(BITSELECT,153)@5
vStage_uid154_lzcZ_uid56_fpCosPiTest_in <= vStagei_uid150_lzcZ_uid56_fpCosPiTest_q(7 downto 0);
vStage_uid154_lzcZ_uid56_fpCosPiTest_b <= vStage_uid154_lzcZ_uid56_fpCosPiTest_in(7 downto 0);
--vStagei_uid156_lzcZ_uid56_fpCosPiTest(MUX,155)@5
vStagei_uid156_lzcZ_uid56_fpCosPiTest_s <= vCount_uid153_lzcZ_uid56_fpCosPiTest_q;
vStagei_uid156_lzcZ_uid56_fpCosPiTest: PROCESS (vStagei_uid156_lzcZ_uid56_fpCosPiTest_s, en, rVStage_uid152_lzcZ_uid56_fpCosPiTest_b, vStage_uid154_lzcZ_uid56_fpCosPiTest_b)
BEGIN
CASE vStagei_uid156_lzcZ_uid56_fpCosPiTest_s IS
WHEN "0" => vStagei_uid156_lzcZ_uid56_fpCosPiTest_q <= rVStage_uid152_lzcZ_uid56_fpCosPiTest_b;
WHEN "1" => vStagei_uid156_lzcZ_uid56_fpCosPiTest_q <= vStage_uid154_lzcZ_uid56_fpCosPiTest_b;
WHEN OTHERS => vStagei_uid156_lzcZ_uid56_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid158_lzcZ_uid56_fpCosPiTest(BITSELECT,157)@5
rVStage_uid158_lzcZ_uid56_fpCosPiTest_in <= vStagei_uid156_lzcZ_uid56_fpCosPiTest_q;
rVStage_uid158_lzcZ_uid56_fpCosPiTest_b <= rVStage_uid158_lzcZ_uid56_fpCosPiTest_in(7 downto 4);
--reg_rVStage_uid158_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid159_lzcZ_uid56_fpCosPiTest_1(REG,253)@5
reg_rVStage_uid158_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid159_lzcZ_uid56_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid158_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid159_lzcZ_uid56_fpCosPiTest_1_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid158_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid159_lzcZ_uid56_fpCosPiTest_1_q <= rVStage_uid158_lzcZ_uid56_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid159_lzcZ_uid56_fpCosPiTest(LOGICAL,158)@6
vCount_uid159_lzcZ_uid56_fpCosPiTest_a <= reg_rVStage_uid158_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid159_lzcZ_uid56_fpCosPiTest_1_q;
vCount_uid159_lzcZ_uid56_fpCosPiTest_b <= leftShiftStage1Idx1Pad4_uid114_fxpX_uid41_fpCosPiTest_q;
vCount_uid159_lzcZ_uid56_fpCosPiTest_q <= "1" when vCount_uid159_lzcZ_uid56_fpCosPiTest_a = vCount_uid159_lzcZ_uid56_fpCosPiTest_b else "0";
--vStage_uid160_lzcZ_uid56_fpCosPiTest(BITSELECT,159)@5
vStage_uid160_lzcZ_uid56_fpCosPiTest_in <= vStagei_uid156_lzcZ_uid56_fpCosPiTest_q(3 downto 0);
vStage_uid160_lzcZ_uid56_fpCosPiTest_b <= vStage_uid160_lzcZ_uid56_fpCosPiTest_in(3 downto 0);
--reg_vStage_uid160_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid162_lzcZ_uid56_fpCosPiTest_3(REG,255)@5
reg_vStage_uid160_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid162_lzcZ_uid56_fpCosPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid160_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid162_lzcZ_uid56_fpCosPiTest_3_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid160_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid162_lzcZ_uid56_fpCosPiTest_3_q <= vStage_uid160_lzcZ_uid56_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid162_lzcZ_uid56_fpCosPiTest(MUX,161)@6
vStagei_uid162_lzcZ_uid56_fpCosPiTest_s <= vCount_uid159_lzcZ_uid56_fpCosPiTest_q;
vStagei_uid162_lzcZ_uid56_fpCosPiTest: PROCESS (vStagei_uid162_lzcZ_uid56_fpCosPiTest_s, en, reg_rVStage_uid158_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid159_lzcZ_uid56_fpCosPiTest_1_q, reg_vStage_uid160_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid162_lzcZ_uid56_fpCosPiTest_3_q)
BEGIN
CASE vStagei_uid162_lzcZ_uid56_fpCosPiTest_s IS
WHEN "0" => vStagei_uid162_lzcZ_uid56_fpCosPiTest_q <= reg_rVStage_uid158_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid159_lzcZ_uid56_fpCosPiTest_1_q;
WHEN "1" => vStagei_uid162_lzcZ_uid56_fpCosPiTest_q <= reg_vStage_uid160_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid162_lzcZ_uid56_fpCosPiTest_3_q;
WHEN OTHERS => vStagei_uid162_lzcZ_uid56_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid164_lzcZ_uid56_fpCosPiTest(BITSELECT,163)@6
rVStage_uid164_lzcZ_uid56_fpCosPiTest_in <= vStagei_uid162_lzcZ_uid56_fpCosPiTest_q;
rVStage_uid164_lzcZ_uid56_fpCosPiTest_b <= rVStage_uid164_lzcZ_uid56_fpCosPiTest_in(3 downto 2);
--vCount_uid165_lzcZ_uid56_fpCosPiTest(LOGICAL,164)@6
vCount_uid165_lzcZ_uid56_fpCosPiTest_a <= rVStage_uid164_lzcZ_uid56_fpCosPiTest_b;
vCount_uid165_lzcZ_uid56_fpCosPiTest_b <= leftShiftStage2Idx2Pad2_uid128_fxpX_uid41_fpCosPiTest_q;
vCount_uid165_lzcZ_uid56_fpCosPiTest_q <= "1" when vCount_uid165_lzcZ_uid56_fpCosPiTest_a = vCount_uid165_lzcZ_uid56_fpCosPiTest_b else "0";
--vStage_uid166_lzcZ_uid56_fpCosPiTest(BITSELECT,165)@6
vStage_uid166_lzcZ_uid56_fpCosPiTest_in <= vStagei_uid162_lzcZ_uid56_fpCosPiTest_q(1 downto 0);
vStage_uid166_lzcZ_uid56_fpCosPiTest_b <= vStage_uid166_lzcZ_uid56_fpCosPiTest_in(1 downto 0);
--vStagei_uid168_lzcZ_uid56_fpCosPiTest(MUX,167)@6
vStagei_uid168_lzcZ_uid56_fpCosPiTest_s <= vCount_uid165_lzcZ_uid56_fpCosPiTest_q;
vStagei_uid168_lzcZ_uid56_fpCosPiTest: PROCESS (vStagei_uid168_lzcZ_uid56_fpCosPiTest_s, en, rVStage_uid164_lzcZ_uid56_fpCosPiTest_b, vStage_uid166_lzcZ_uid56_fpCosPiTest_b)
BEGIN
CASE vStagei_uid168_lzcZ_uid56_fpCosPiTest_s IS
WHEN "0" => vStagei_uid168_lzcZ_uid56_fpCosPiTest_q <= rVStage_uid164_lzcZ_uid56_fpCosPiTest_b;
WHEN "1" => vStagei_uid168_lzcZ_uid56_fpCosPiTest_q <= vStage_uid166_lzcZ_uid56_fpCosPiTest_b;
WHEN OTHERS => vStagei_uid168_lzcZ_uid56_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid170_lzcZ_uid56_fpCosPiTest(BITSELECT,169)@6
rVStage_uid170_lzcZ_uid56_fpCosPiTest_in <= vStagei_uid168_lzcZ_uid56_fpCosPiTest_q;
rVStage_uid170_lzcZ_uid56_fpCosPiTest_b <= rVStage_uid170_lzcZ_uid56_fpCosPiTest_in(1 downto 1);
--vCount_uid171_lzcZ_uid56_fpCosPiTest(LOGICAL,170)@6
vCount_uid171_lzcZ_uid56_fpCosPiTest_a <= rVStage_uid170_lzcZ_uid56_fpCosPiTest_b;
vCount_uid171_lzcZ_uid56_fpCosPiTest_b <= GND_q;
vCount_uid171_lzcZ_uid56_fpCosPiTest_q <= "1" when vCount_uid171_lzcZ_uid56_fpCosPiTest_a = vCount_uid171_lzcZ_uid56_fpCosPiTest_b else "0";
--r_uid172_lzcZ_uid56_fpCosPiTest(BITJOIN,171)@6
r_uid172_lzcZ_uid56_fpCosPiTest_q <= ld_vCount_uid139_lzcZ_uid56_fpCosPiTest_q_to_r_uid172_lzcZ_uid56_fpCosPiTest_f_q & ld_vCount_uid147_lzcZ_uid56_fpCosPiTest_q_to_r_uid172_lzcZ_uid56_fpCosPiTest_e_q & reg_vCount_uid153_lzcZ_uid56_fpCosPiTest_0_to_r_uid172_lzcZ_uid56_fpCosPiTest_3_q & vCount_uid159_lzcZ_uid56_fpCosPiTest_q & vCount_uid165_lzcZ_uid56_fpCosPiTest_q & vCount_uid171_lzcZ_uid56_fpCosPiTest_q;
--leftShiftStageSel5Dto4_uid182_alignedZ_uid57_fpCosPiTest(BITSELECT,181)@6
leftShiftStageSel5Dto4_uid182_alignedZ_uid57_fpCosPiTest_in <= r_uid172_lzcZ_uid56_fpCosPiTest_q;
leftShiftStageSel5Dto4_uid182_alignedZ_uid57_fpCosPiTest_b <= leftShiftStageSel5Dto4_uid182_alignedZ_uid57_fpCosPiTest_in(5 downto 4);
--leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest(MUX,182)@6
leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_s <= leftShiftStageSel5Dto4_uid182_alignedZ_uid57_fpCosPiTest_b;
leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest: PROCESS (leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_s, en, ld_z_uid54_fpCosPiTest_b_to_leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_c_q, leftShiftStage0Idx1_uid177_alignedZ_uid57_fpCosPiTest_q, leftShiftStage0Idx2_uid180_alignedZ_uid57_fpCosPiTest_q, cstZwSwF_uid15_fpCosPiTest_q)
BEGIN
CASE leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_s IS
WHEN "00" => leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_q <= ld_z_uid54_fpCosPiTest_b_to_leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_c_q;
WHEN "01" => leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_q <= leftShiftStage0Idx1_uid177_alignedZ_uid57_fpCosPiTest_q;
WHEN "10" => leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_q <= leftShiftStage0Idx2_uid180_alignedZ_uid57_fpCosPiTest_q;
WHEN "11" => leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_q <= cstZwSwF_uid15_fpCosPiTest_q;
WHEN OTHERS => leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage022dto0_uid191_alignedZ_uid57_fpCosPiTest(BITSELECT,190)@6
LeftShiftStage022dto0_uid191_alignedZ_uid57_fpCosPiTest_in <= leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_q(22 downto 0);
LeftShiftStage022dto0_uid191_alignedZ_uid57_fpCosPiTest_b <= LeftShiftStage022dto0_uid191_alignedZ_uid57_fpCosPiTest_in(22 downto 0);
--leftShiftStage1Idx3_uid192_alignedZ_uid57_fpCosPiTest(BITJOIN,191)@6
leftShiftStage1Idx3_uid192_alignedZ_uid57_fpCosPiTest_q <= LeftShiftStage022dto0_uid191_alignedZ_uid57_fpCosPiTest_b & leftShiftStage1Idx3Pad12_uid120_fxpX_uid41_fpCosPiTest_q;
--reg_leftShiftStage1Idx3_uid192_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_5(REG,261)@6
reg_leftShiftStage1Idx3_uid192_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx3_uid192_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_5_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx3_uid192_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_5_q <= leftShiftStage1Idx3_uid192_alignedZ_uid57_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage026dto0_uid188_alignedZ_uid57_fpCosPiTest(BITSELECT,187)@6
LeftShiftStage026dto0_uid188_alignedZ_uid57_fpCosPiTest_in <= leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_q(26 downto 0);
LeftShiftStage026dto0_uid188_alignedZ_uid57_fpCosPiTest_b <= LeftShiftStage026dto0_uid188_alignedZ_uid57_fpCosPiTest_in(26 downto 0);
--leftShiftStage1Idx2_uid189_alignedZ_uid57_fpCosPiTest(BITJOIN,188)@6
leftShiftStage1Idx2_uid189_alignedZ_uid57_fpCosPiTest_q <= LeftShiftStage026dto0_uid188_alignedZ_uid57_fpCosPiTest_b & cstAllZWE_uid21_fpCosPiTest_q;
--reg_leftShiftStage1Idx2_uid189_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_4(REG,260)@6
reg_leftShiftStage1Idx2_uid189_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx2_uid189_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_4_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx2_uid189_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_4_q <= leftShiftStage1Idx2_uid189_alignedZ_uid57_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage030dto0_uid185_alignedZ_uid57_fpCosPiTest(BITSELECT,184)@6
LeftShiftStage030dto0_uid185_alignedZ_uid57_fpCosPiTest_in <= leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_q(30 downto 0);
LeftShiftStage030dto0_uid185_alignedZ_uid57_fpCosPiTest_b <= LeftShiftStage030dto0_uid185_alignedZ_uid57_fpCosPiTest_in(30 downto 0);
--leftShiftStage1Idx1_uid186_alignedZ_uid57_fpCosPiTest(BITJOIN,185)@6
leftShiftStage1Idx1_uid186_alignedZ_uid57_fpCosPiTest_q <= LeftShiftStage030dto0_uid185_alignedZ_uid57_fpCosPiTest_b & leftShiftStage1Idx1Pad4_uid114_fxpX_uid41_fpCosPiTest_q;
--reg_leftShiftStage1Idx1_uid186_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_3(REG,259)@6
reg_leftShiftStage1Idx1_uid186_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx1_uid186_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_3_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx1_uid186_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_3_q <= leftShiftStage1Idx1_uid186_alignedZ_uid57_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--reg_leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_2(REG,258)@6
reg_leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_2_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_2_q <= leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel3Dto2_uid193_alignedZ_uid57_fpCosPiTest(BITSELECT,192)@6
leftShiftStageSel3Dto2_uid193_alignedZ_uid57_fpCosPiTest_in <= r_uid172_lzcZ_uid56_fpCosPiTest_q(3 downto 0);
leftShiftStageSel3Dto2_uid193_alignedZ_uid57_fpCosPiTest_b <= leftShiftStageSel3Dto2_uid193_alignedZ_uid57_fpCosPiTest_in(3 downto 2);
--reg_leftShiftStageSel3Dto2_uid193_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_1(REG,257)@6
reg_leftShiftStageSel3Dto2_uid193_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel3Dto2_uid193_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel3Dto2_uid193_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_1_q <= leftShiftStageSel3Dto2_uid193_alignedZ_uid57_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest(MUX,193)@7
leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_s <= reg_leftShiftStageSel3Dto2_uid193_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_1_q;
leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest: PROCESS (leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_s, en, reg_leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_2_q, reg_leftShiftStage1Idx1_uid186_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_3_q, reg_leftShiftStage1Idx2_uid189_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_4_q, reg_leftShiftStage1Idx3_uid192_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_5_q)
BEGIN
CASE leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_s IS
WHEN "00" => leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_q <= reg_leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_2_q;
WHEN "01" => leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_q <= reg_leftShiftStage1Idx1_uid186_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_3_q;
WHEN "10" => leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_q <= reg_leftShiftStage1Idx2_uid189_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_4_q;
WHEN "11" => leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_q <= reg_leftShiftStage1Idx3_uid192_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_5_q;
WHEN OTHERS => leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--leftShiftStageSel1Dto0_uid204_alignedZ_uid57_fpCosPiTest(BITSELECT,203)@6
leftShiftStageSel1Dto0_uid204_alignedZ_uid57_fpCosPiTest_in <= r_uid172_lzcZ_uid56_fpCosPiTest_q(1 downto 0);
leftShiftStageSel1Dto0_uid204_alignedZ_uid57_fpCosPiTest_b <= leftShiftStageSel1Dto0_uid204_alignedZ_uid57_fpCosPiTest_in(1 downto 0);
--reg_leftShiftStageSel1Dto0_uid204_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest_1(REG,262)@6
reg_leftShiftStageSel1Dto0_uid204_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel1Dto0_uid204_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel1Dto0_uid204_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest_1_q <= leftShiftStageSel1Dto0_uid204_alignedZ_uid57_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest(MUX,204)@7
leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest_s <= reg_leftShiftStageSel1Dto0_uid204_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest_1_q;
leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest: PROCESS (leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest_s, en, leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_q, leftShiftStage2Idx1_uid197_alignedZ_uid57_fpCosPiTest_q, leftShiftStage2Idx2_uid200_alignedZ_uid57_fpCosPiTest_q, leftShiftStage2Idx3_uid203_alignedZ_uid57_fpCosPiTest_q)
BEGIN
CASE leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest_s IS
WHEN "00" => leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest_q <= leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_q;
WHEN "01" => leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest_q <= leftShiftStage2Idx1_uid197_alignedZ_uid57_fpCosPiTest_q;
WHEN "10" => leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest_q <= leftShiftStage2Idx2_uid200_alignedZ_uid57_fpCosPiTest_q;
WHEN "11" => leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest_q <= leftShiftStage2Idx3_uid203_alignedZ_uid57_fpCosPiTest_q;
WHEN OTHERS => leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--alignedZLow_uid58_fpCosPiTest(BITSELECT,57)@7
alignedZLow_uid58_fpCosPiTest_in <= leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest_q;
alignedZLow_uid58_fpCosPiTest_b <= alignedZLow_uid58_fpCosPiTest_in(34 downto 11);
--ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_inputreg(DELAY,612)
ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 24, depth => 1 )
PORT MAP ( xin => alignedZLow_uid58_fpCosPiTest_b, xout => ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem(DUALMEM,613)
ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_reset0 <= areset;
ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_ia <= ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_inputreg_q;
ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_aa <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdreg_q;
ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_ab <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdmux_q;
ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 24,
widthad_a => 2,
numwords_a => 3,
width_b => 24,
widthad_b => 2,
numwords_b => 3,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_iq,
address_a => ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_aa,
data_a => ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_ia
);
ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_q <= ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_iq(23 downto 0);
--reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0(REG,269)@12
reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_q <= ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest(MULT,222)@13
prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_pr <= UNSIGNED(prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_a) * UNSIGNED(prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_b);
prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_a <= (others => '0');
prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_b <= (others => '0');
prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_a <= reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_q;
prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_b <= reg_fxpSinRes_uid65_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_1_q;
prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_s1 <= STD_LOGIC_VECTOR(prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_pr);
END IF;
END IF;
END PROCESS;
prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_q <= prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid224_mul2xSinRes_uid66_fpCosPiTest(BITSELECT,223)@16
prodXYTruncFR_uid224_mul2xSinRes_uid66_fpCosPiTest_in <= prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_q;
prodXYTruncFR_uid224_mul2xSinRes_uid66_fpCosPiTest_b <= prodXYTruncFR_uid224_mul2xSinRes_uid66_fpCosPiTest_in(48 downto 23);
--normBit_uid67_fpCosPiTest(BITSELECT,66)@16
normBit_uid67_fpCosPiTest_in <= prodXYTruncFR_uid224_mul2xSinRes_uid66_fpCosPiTest_b;
normBit_uid67_fpCosPiTest_b <= normBit_uid67_fpCosPiTest_in(25 downto 25);
--cstAllZWF_uid9_fpCosPiTest(CONSTANT,8)
cstAllZWF_uid9_fpCosPiTest_q <= "00000000000000000000000";
--rndExpUpdate_uid72_uid73_fpCosPiTest(BITJOIN,72)@16
rndExpUpdate_uid72_uid73_fpCosPiTest_q <= normBit_uid67_fpCosPiTest_b & cstAllZWF_uid9_fpCosPiTest_q & VCC_q;
--ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_nor(LOGICAL,558)
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_nor_a <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_notEnable_q;
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_nor_b <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_sticky_ena_q;
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_nor_q <= not (ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_nor_a or ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_nor_b);
--ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_sticky_ena(REG,559)
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_nor_q = "1") THEN
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_sticky_ena_q <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_enaAnd(LOGICAL,560)
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_enaAnd_a <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_sticky_ena_q;
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_enaAnd_b <= en;
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_enaAnd_q <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_enaAnd_a and ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_enaAnd_b;
--reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1(REG,271)@6
reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q <= r_uid172_lzcZ_uid56_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem(DUALMEM,549)
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_reset0 <= areset;
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_ia <= reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q;
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_aa <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdreg_q;
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_ab <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdmux_q;
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 6,
widthad_a => 3,
numwords_a => 7,
width_b => 6,
widthad_b => 3,
numwords_b => 7,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_iq,
address_a => ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_aa,
data_a => ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_ia
);
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_q <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_iq(5 downto 0);
--cstBiasM1_uid11_fpCosPiTest(CONSTANT,10)
cstBiasM1_uid11_fpCosPiTest_q <= "01111110";
--expHardCase_uid59_fpCosPiTest(SUB,58)@15
expHardCase_uid59_fpCosPiTest_a <= STD_LOGIC_VECTOR("0" & cstBiasM1_uid11_fpCosPiTest_q);
expHardCase_uid59_fpCosPiTest_b <= STD_LOGIC_VECTOR("000" & ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_q);
expHardCase_uid59_fpCosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expHardCase_uid59_fpCosPiTest_a) - UNSIGNED(expHardCase_uid59_fpCosPiTest_b));
expHardCase_uid59_fpCosPiTest_q <= expHardCase_uid59_fpCosPiTest_o(8 downto 0);
--expP_uid60_fpCosPiTest(BITSELECT,59)@15
expP_uid60_fpCosPiTest_in <= expHardCase_uid59_fpCosPiTest_q(7 downto 0);
expP_uid60_fpCosPiTest_b <= expP_uid60_fpCosPiTest_in(7 downto 0);
--reg_expP_uid60_fpCosPiTest_0_to_expFracPreRnd_uid71_uid71_fpCosPiTest_1(REG,272)@15
reg_expP_uid60_fpCosPiTest_0_to_expFracPreRnd_uid71_uid71_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expP_uid60_fpCosPiTest_0_to_expFracPreRnd_uid71_uid71_fpCosPiTest_1_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expP_uid60_fpCosPiTest_0_to_expFracPreRnd_uid71_uid71_fpCosPiTest_1_q <= expP_uid60_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--highRes_uid68_fpCosPiTest(BITSELECT,67)@16
highRes_uid68_fpCosPiTest_in <= prodXYTruncFR_uid224_mul2xSinRes_uid66_fpCosPiTest_b(24 downto 0);
highRes_uid68_fpCosPiTest_b <= highRes_uid68_fpCosPiTest_in(24 downto 1);
--lowRes_uid69_fpCosPiTest(BITSELECT,68)@16
lowRes_uid69_fpCosPiTest_in <= prodXYTruncFR_uid224_mul2xSinRes_uid66_fpCosPiTest_b(23 downto 0);
lowRes_uid69_fpCosPiTest_b <= lowRes_uid69_fpCosPiTest_in(23 downto 0);
--fracRCompPreRnd_uid70_fpCosPiTest(MUX,69)@16
fracRCompPreRnd_uid70_fpCosPiTest_s <= normBit_uid67_fpCosPiTest_b;
fracRCompPreRnd_uid70_fpCosPiTest: PROCESS (fracRCompPreRnd_uid70_fpCosPiTest_s, en, lowRes_uid69_fpCosPiTest_b, highRes_uid68_fpCosPiTest_b)
BEGIN
CASE fracRCompPreRnd_uid70_fpCosPiTest_s IS
WHEN "0" => fracRCompPreRnd_uid70_fpCosPiTest_q <= lowRes_uid69_fpCosPiTest_b;
WHEN "1" => fracRCompPreRnd_uid70_fpCosPiTest_q <= highRes_uid68_fpCosPiTest_b;
WHEN OTHERS => fracRCompPreRnd_uid70_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--expFracPreRnd_uid71_uid71_fpCosPiTest(BITJOIN,70)@16
expFracPreRnd_uid71_uid71_fpCosPiTest_q <= reg_expP_uid60_fpCosPiTest_0_to_expFracPreRnd_uid71_uid71_fpCosPiTest_1_q & fracRCompPreRnd_uid70_fpCosPiTest_q;
--expFracComp_uid74_fpCosPiTest(ADD,73)@16
expFracComp_uid74_fpCosPiTest_a <= STD_LOGIC_VECTOR("0" & expFracPreRnd_uid71_uid71_fpCosPiTest_q);
expFracComp_uid74_fpCosPiTest_b <= STD_LOGIC_VECTOR("00000000" & rndExpUpdate_uid72_uid73_fpCosPiTest_q);
expFracComp_uid74_fpCosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expFracComp_uid74_fpCosPiTest_a) + UNSIGNED(expFracComp_uid74_fpCosPiTest_b));
expFracComp_uid74_fpCosPiTest_q <= expFracComp_uid74_fpCosPiTest_o(32 downto 0);
--expRComp_uid76_fpCosPiTest(BITSELECT,75)@16
expRComp_uid76_fpCosPiTest_in <= expFracComp_uid74_fpCosPiTest_q(31 downto 0);
expRComp_uid76_fpCosPiTest_b <= expRComp_uid76_fpCosPiTest_in(31 downto 24);
--fracXIsZero_uid27_fpCosPiTest(LOGICAL,26)@0
fracXIsZero_uid27_fpCosPiTest_a <= fracX_uid7_fpCosPiTest_b;
fracXIsZero_uid27_fpCosPiTest_b <= cstAllZWF_uid9_fpCosPiTest_q;
fracXIsZero_uid27_fpCosPiTest_q <= "1" when fracXIsZero_uid27_fpCosPiTest_a = fracXIsZero_uid27_fpCosPiTest_b else "0";
--InvFracXIsZero_uid29_fpCosPiTest(LOGICAL,28)@0
InvFracXIsZero_uid29_fpCosPiTest_a <= fracXIsZero_uid27_fpCosPiTest_q;
InvFracXIsZero_uid29_fpCosPiTest_q <= not InvFracXIsZero_uid29_fpCosPiTest_a;
--expXIsMax_uid25_fpCosPiTest(LOGICAL,24)@0
expXIsMax_uid25_fpCosPiTest_a <= expX_uid6_fpCosPiTest_b;
expXIsMax_uid25_fpCosPiTest_b <= cstAllOWE_uid8_fpCosPiTest_q;
expXIsMax_uid25_fpCosPiTest_q <= "1" when expXIsMax_uid25_fpCosPiTest_a = expXIsMax_uid25_fpCosPiTest_b else "0";
--exc_N_uid30_fpCosPiTest(LOGICAL,29)@0
exc_N_uid30_fpCosPiTest_a <= expXIsMax_uid25_fpCosPiTest_q;
exc_N_uid30_fpCosPiTest_b <= InvFracXIsZero_uid29_fpCosPiTest_q;
exc_N_uid30_fpCosPiTest_q <= exc_N_uid30_fpCosPiTest_a and exc_N_uid30_fpCosPiTest_b;
--InvExc_N_uid31_fpCosPiTest(LOGICAL,30)@0
InvExc_N_uid31_fpCosPiTest_a <= exc_N_uid30_fpCosPiTest_q;
InvExc_N_uid31_fpCosPiTest_q <= not InvExc_N_uid31_fpCosPiTest_a;
--exc_I_uid28_fpCosPiTest(LOGICAL,27)@0
exc_I_uid28_fpCosPiTest_a <= expXIsMax_uid25_fpCosPiTest_q;
exc_I_uid28_fpCosPiTest_b <= fracXIsZero_uid27_fpCosPiTest_q;
exc_I_uid28_fpCosPiTest_q <= exc_I_uid28_fpCosPiTest_a and exc_I_uid28_fpCosPiTest_b;
--InvExc_I_uid32_fpCosPiTest(LOGICAL,31)@0
InvExc_I_uid32_fpCosPiTest_a <= exc_I_uid28_fpCosPiTest_q;
InvExc_I_uid32_fpCosPiTest_q <= not InvExc_I_uid32_fpCosPiTest_a;
--expXIsZero_uid23_fpCosPiTest(LOGICAL,22)@0
expXIsZero_uid23_fpCosPiTest_a <= expX_uid6_fpCosPiTest_b;
expXIsZero_uid23_fpCosPiTest_b <= cstAllZWE_uid21_fpCosPiTest_q;
expXIsZero_uid23_fpCosPiTest_q <= "1" when expXIsZero_uid23_fpCosPiTest_a = expXIsZero_uid23_fpCosPiTest_b else "0";
--InvExpXIsZero_uid33_fpCosPiTest(LOGICAL,32)@0
InvExpXIsZero_uid33_fpCosPiTest_a <= expXIsZero_uid23_fpCosPiTest_q;
InvExpXIsZero_uid33_fpCosPiTest_q <= not InvExpXIsZero_uid33_fpCosPiTest_a;
--exc_R_uid34_fpCosPiTest(LOGICAL,33)@0
exc_R_uid34_fpCosPiTest_a <= InvExpXIsZero_uid33_fpCosPiTest_q;
exc_R_uid34_fpCosPiTest_b <= InvExc_I_uid32_fpCosPiTest_q;
exc_R_uid34_fpCosPiTest_c <= InvExc_N_uid31_fpCosPiTest_q;
exc_R_uid34_fpCosPiTest_q <= exc_R_uid34_fpCosPiTest_a and exc_R_uid34_fpCosPiTest_b and exc_R_uid34_fpCosPiTest_c;
--ld_exc_R_uid34_fpCosPiTest_q_to_xIsInt_uid80_fpCosPiTest_a(DELAY,337)@0
ld_exc_R_uid34_fpCosPiTest_q_to_xIsInt_uid80_fpCosPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => exc_R_uid34_fpCosPiTest_q, xout => ld_exc_R_uid34_fpCosPiTest_q_to_xIsInt_uid80_fpCosPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--xIsHalf_uid83_fpCosPiTest(LOGICAL,82)@2
xIsHalf_uid83_fpCosPiTest_a <= ld_exc_R_uid34_fpCosPiTest_q_to_xIsInt_uid80_fpCosPiTest_a_q;
xIsHalf_uid83_fpCosPiTest_b <= fxpXFracHalf_uid46_fpCosPiTest_q;
xIsHalf_uid83_fpCosPiTest_c <= InvCosXIsOne_uid77_fpCosPiTest_q;
xIsHalf_uid83_fpCosPiTest_d <= InvXEvenInt_uid81_fpCosPiTest_q;
xIsHalf_uid83_fpCosPiTest_q <= xIsHalf_uid83_fpCosPiTest_a and xIsHalf_uid83_fpCosPiTest_b and xIsHalf_uid83_fpCosPiTest_c and xIsHalf_uid83_fpCosPiTest_d;
--ld_xIsHalf_uid83_fpCosPiTest_q_to_expRPostExc1_uid91_fpCosPiTest_b(DELAY,355)@2
ld_xIsHalf_uid83_fpCosPiTest_q_to_expRPostExc1_uid91_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 14 )
PORT MAP ( xin => xIsHalf_uid83_fpCosPiTest_q, xout => ld_xIsHalf_uid83_fpCosPiTest_q_to_expRPostExc1_uid91_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--expRPostExc1_uid91_fpCosPiTest(MUX,90)@16
expRPostExc1_uid91_fpCosPiTest_s <= ld_xIsHalf_uid83_fpCosPiTest_q_to_expRPostExc1_uid91_fpCosPiTest_b_q;
expRPostExc1_uid91_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expRPostExc1_uid91_fpCosPiTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE expRPostExc1_uid91_fpCosPiTest_s IS
WHEN "0" => expRPostExc1_uid91_fpCosPiTest_q <= expRComp_uid76_fpCosPiTest_b;
WHEN "1" => expRPostExc1_uid91_fpCosPiTest_q <= cstAllZWE_uid21_fpCosPiTest_q;
WHEN OTHERS => expRPostExc1_uid91_fpCosPiTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_nor(LOGICAL,570)
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_nor_a <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_notEnable_q;
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_nor_b <= ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_sticky_ena_q;
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_nor_q <= not (ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_nor_a or ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_nor_b);
--ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_mem_top(CONSTANT,566)
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_mem_top_q <= "01100";
--ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_cmp(LOGICAL,567)
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_cmp_a <= ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_mem_top_q;
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdmux_q);
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_cmp_q <= "1" when ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_cmp_a = ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_cmp_b else "0";
--ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_cmpReg(REG,568)
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_cmpReg_q <= ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_sticky_ena(REG,571)
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_nor_q = "1") THEN
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_sticky_ena_q <= ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_enaAnd(LOGICAL,572)
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_enaAnd_a <= ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_sticky_ena_q;
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_enaAnd_b <= en;
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_enaAnd_q <= ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_enaAnd_a and ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_enaAnd_b;
--ld_expXIsZero_uid23_fpCosPiTest_q_to_xIntOrXZOrCosOne_uid93_fpCosPiTest_b(DELAY,359)@0
ld_expXIsZero_uid23_fpCosPiTest_q_to_xIntOrXZOrCosOne_uid93_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => expXIsZero_uid23_fpCosPiTest_q, xout => ld_expXIsZero_uid23_fpCosPiTest_q_to_xIntOrXZOrCosOne_uid93_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--fxpXFracZero_uid45_fpCosPiTest(LOGICAL,44)@2
fxpXFracZero_uid45_fpCosPiTest_a <= reg_fxpXFrac_uid43_fpCosPiTest_0_to_fxpXFracZero_uid45_fpCosPiTest_1_q;
fxpXFracZero_uid45_fpCosPiTest_b <= STD_LOGIC_VECTOR("0" & cstZwSwF_uid15_fpCosPiTest_q);
fxpXFracZero_uid45_fpCosPiTest_q <= "1" when fxpXFracZero_uid45_fpCosPiTest_a = fxpXFracZero_uid45_fpCosPiTest_b else "0";
--fracZCosNotOne_uid78_fpCosPiTest(LOGICAL,77)@2
fracZCosNotOne_uid78_fpCosPiTest_a <= fxpXFracZero_uid45_fpCosPiTest_q;
fracZCosNotOne_uid78_fpCosPiTest_b <= InvCosXIsOne_uid77_fpCosPiTest_q;
fracZCosNotOne_uid78_fpCosPiTest_q <= fracZCosNotOne_uid78_fpCosPiTest_a and fracZCosNotOne_uid78_fpCosPiTest_b;
--evenIntCosNotOneFZ_uid79_fpCosPiTest(LOGICAL,78)@2
evenIntCosNotOneFZ_uid79_fpCosPiTest_a <= ld_xEvenInt_uid35_fpCosPiTest_c_to_evenIntCosNotOneFZ_uid79_fpCosPiTest_a_q;
evenIntCosNotOneFZ_uid79_fpCosPiTest_b <= fracZCosNotOne_uid78_fpCosPiTest_q;
evenIntCosNotOneFZ_uid79_fpCosPiTest_q <= evenIntCosNotOneFZ_uid79_fpCosPiTest_a or evenIntCosNotOneFZ_uid79_fpCosPiTest_b;
--xIsInt_uid80_fpCosPiTest(LOGICAL,79)@2
xIsInt_uid80_fpCosPiTest_a <= ld_exc_R_uid34_fpCosPiTest_q_to_xIsInt_uid80_fpCosPiTest_a_q;
xIsInt_uid80_fpCosPiTest_b <= evenIntCosNotOneFZ_uid79_fpCosPiTest_q;
xIsInt_uid80_fpCosPiTest_q <= xIsInt_uid80_fpCosPiTest_a and xIsInt_uid80_fpCosPiTest_b;
--xIntOrXZOrCosOne_uid93_fpCosPiTest(LOGICAL,92)@2
xIntOrXZOrCosOne_uid93_fpCosPiTest_a <= xIsInt_uid80_fpCosPiTest_q;
xIntOrXZOrCosOne_uid93_fpCosPiTest_b <= ld_expXIsZero_uid23_fpCosPiTest_q_to_xIntOrXZOrCosOne_uid93_fpCosPiTest_b_q;
xIntOrXZOrCosOne_uid93_fpCosPiTest_c <= ld_cosXIsOne_uid36_fpCosPiTest_c_to_InvCosXIsOne_uid77_fpCosPiTest_a_q;
xIntOrXZOrCosOne_uid93_fpCosPiTest_q <= xIntOrXZOrCosOne_uid93_fpCosPiTest_a or xIntOrXZOrCosOne_uid93_fpCosPiTest_b or xIntOrXZOrCosOne_uid93_fpCosPiTest_c;
--excRNaN_uid84_fpCosPiTest(LOGICAL,83)@0
excRNaN_uid84_fpCosPiTest_a <= exc_N_uid30_fpCosPiTest_q;
excRNaN_uid84_fpCosPiTest_b <= exc_I_uid28_fpCosPiTest_q;
excRNaN_uid84_fpCosPiTest_q <= excRNaN_uid84_fpCosPiTest_a or excRNaN_uid84_fpCosPiTest_b;
--rInfOrNaN_uid92_fpCosPiTest(LOGICAL,91)@0
rInfOrNaN_uid92_fpCosPiTest_a <= GND_q;
rInfOrNaN_uid92_fpCosPiTest_b <= excRNaN_uid84_fpCosPiTest_q;
rInfOrNaN_uid92_fpCosPiTest_q <= rInfOrNaN_uid92_fpCosPiTest_a or rInfOrNaN_uid92_fpCosPiTest_b;
--ld_rInfOrNaN_uid92_fpCosPiTest_q_to_join_uid94_fpCosPiTest_a(DELAY,361)@0
ld_rInfOrNaN_uid92_fpCosPiTest_q_to_join_uid94_fpCosPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => rInfOrNaN_uid92_fpCosPiTest_q, xout => ld_rInfOrNaN_uid92_fpCosPiTest_q_to_join_uid94_fpCosPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--join_uid94_fpCosPiTest(BITJOIN,93)@2
join_uid94_fpCosPiTest_q <= xIntOrXZOrCosOne_uid93_fpCosPiTest_q & ld_rInfOrNaN_uid92_fpCosPiTest_q_to_join_uid94_fpCosPiTest_a_q;
--reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1(REG,274)@2
reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q <= join_uid94_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt(COUNTER,562)
-- every=1, low=0, high=12, step=1, init=1
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt_i = 11 THEN
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt_eq <= '1';
ELSE
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt_eq = '1') THEN
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt_i <= ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt_i - 12;
ELSE
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt_i <= ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt_i,4));
--ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdreg(REG,563)
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdreg_q <= ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdmux(MUX,564)
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdmux_s <= en;
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdmux: PROCESS (ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdmux_s, ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdreg_q, ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt_q)
BEGIN
CASE ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdmux_s IS
WHEN "0" => ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdmux_q <= ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdreg_q;
WHEN "1" => ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdmux_q <= ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem(DUALMEM,561)
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_reset0 <= areset;
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_ia <= reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q;
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_aa <= ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdreg_q;
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_ab <= ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdmux_q;
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 2,
widthad_a => 4,
numwords_a => 13,
width_b => 2,
widthad_b => 4,
numwords_b => 13,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_iq,
address_a => ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_aa,
data_a => ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_ia
);
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_q <= ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_iq(1 downto 0);
--expRPostExc_uid95_fpCosPiTest(MUX,94)@17
expRPostExc_uid95_fpCosPiTest_s <= ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_q;
expRPostExc_uid95_fpCosPiTest: PROCESS (expRPostExc_uid95_fpCosPiTest_s, en, expRPostExc1_uid91_fpCosPiTest_q, cstAllOWE_uid8_fpCosPiTest_q, cstBias_uid10_fpCosPiTest_q, cstBias_uid10_fpCosPiTest_q)
BEGIN
CASE expRPostExc_uid95_fpCosPiTest_s IS
WHEN "00" => expRPostExc_uid95_fpCosPiTest_q <= expRPostExc1_uid91_fpCosPiTest_q;
WHEN "01" => expRPostExc_uid95_fpCosPiTest_q <= cstAllOWE_uid8_fpCosPiTest_q;
WHEN "10" => expRPostExc_uid95_fpCosPiTest_q <= cstBias_uid10_fpCosPiTest_q;
WHEN "11" => expRPostExc_uid95_fpCosPiTest_q <= cstBias_uid10_fpCosPiTest_q;
WHEN OTHERS => expRPostExc_uid95_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--oneFracRPostExc2_uid87_fpCosPiTest(CONSTANT,86)
oneFracRPostExc2_uid87_fpCosPiTest_q <= "00000000000000000000001";
--fracRComp_uid75_fpCosPiTest(BITSELECT,74)@16
fracRComp_uid75_fpCosPiTest_in <= expFracComp_uid74_fpCosPiTest_q(23 downto 0);
fracRComp_uid75_fpCosPiTest_b <= fracRComp_uid75_fpCosPiTest_in(23 downto 1);
--reg_xIsHalf_uid83_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_5(REG,243)@2
reg_xIsHalf_uid83_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xIsHalf_uid83_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_5_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xIsHalf_uid83_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_5_q <= xIsHalf_uid83_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--reg_expXIsZero_uid23_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_4(REG,242)@2
reg_expXIsZero_uid23_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expXIsZero_uid23_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_4_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expXIsZero_uid23_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_4_q <= ld_expXIsZero_uid23_fpCosPiTest_q_to_xIntOrXZOrCosOne_uid93_fpCosPiTest_b_q;
END IF;
END IF;
END PROCESS;
--reg_fxpXFracHalf_uid46_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_3(REG,241)@2
reg_fxpXFracHalf_uid46_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fxpXFracHalf_uid46_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_3_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fxpXFracHalf_uid46_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_3_q <= fxpXFracHalf_uid46_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--reg_xIsInt_uid80_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_2(REG,240)@2
reg_xIsInt_uid80_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xIsInt_uid80_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xIsInt_uid80_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_2_q <= xIsInt_uid80_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--reg_cosXIsOne_uid36_fpCosPiTest_1_to_bigCond_uid85_fpCosPiTest_1(REG,239)@0
reg_cosXIsOne_uid36_fpCosPiTest_1_to_bigCond_uid85_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cosXIsOne_uid36_fpCosPiTest_1_to_bigCond_uid85_fpCosPiTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cosXIsOne_uid36_fpCosPiTest_1_to_bigCond_uid85_fpCosPiTest_1_q <= cosXIsOne_uid36_fpCosPiTest_c;
END IF;
END IF;
END PROCESS;
--ld_reg_cosXIsOne_uid36_fpCosPiTest_1_to_bigCond_uid85_fpCosPiTest_1_q_to_bigCond_uid85_fpCosPiTest_a(DELAY,346)@1
ld_reg_cosXIsOne_uid36_fpCosPiTest_1_to_bigCond_uid85_fpCosPiTest_1_q_to_bigCond_uid85_fpCosPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => reg_cosXIsOne_uid36_fpCosPiTest_1_to_bigCond_uid85_fpCosPiTest_1_q, xout => ld_reg_cosXIsOne_uid36_fpCosPiTest_1_to_bigCond_uid85_fpCosPiTest_1_q_to_bigCond_uid85_fpCosPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--bigCond_uid85_fpCosPiTest(LOGICAL,84)@3
bigCond_uid85_fpCosPiTest_a <= ld_reg_cosXIsOne_uid36_fpCosPiTest_1_to_bigCond_uid85_fpCosPiTest_1_q_to_bigCond_uid85_fpCosPiTest_a_q;
bigCond_uid85_fpCosPiTest_b <= reg_xIsInt_uid80_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_2_q;
bigCond_uid85_fpCosPiTest_c <= reg_fxpXFracHalf_uid46_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_3_q;
bigCond_uid85_fpCosPiTest_d <= reg_expXIsZero_uid23_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_4_q;
bigCond_uid85_fpCosPiTest_f <= reg_xIsHalf_uid83_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_5_q;
bigCond_uid85_fpCosPiTest_g <= GND_q;
bigCond_uid85_fpCosPiTest_q <= bigCond_uid85_fpCosPiTest_a or bigCond_uid85_fpCosPiTest_b or bigCond_uid85_fpCosPiTest_c or bigCond_uid85_fpCosPiTest_d or bigCond_uid85_fpCosPiTest_f or bigCond_uid85_fpCosPiTest_g;
--ld_bigCond_uid85_fpCosPiTest_q_to_fracRPostExc1_uid86_fpCosPiTest_b(DELAY,351)@3
ld_bigCond_uid85_fpCosPiTest_q_to_fracRPostExc1_uid86_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 13 )
PORT MAP ( xin => bigCond_uid85_fpCosPiTest_q, xout => ld_bigCond_uid85_fpCosPiTest_q_to_fracRPostExc1_uid86_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--fracRPostExc1_uid86_fpCosPiTest(MUX,85)@16
fracRPostExc1_uid86_fpCosPiTest_s <= ld_bigCond_uid85_fpCosPiTest_q_to_fracRPostExc1_uid86_fpCosPiTest_b_q;
fracRPostExc1_uid86_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
fracRPostExc1_uid86_fpCosPiTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE fracRPostExc1_uid86_fpCosPiTest_s IS
WHEN "0" => fracRPostExc1_uid86_fpCosPiTest_q <= fracRComp_uid75_fpCosPiTest_b;
WHEN "1" => fracRPostExc1_uid86_fpCosPiTest_q <= cstAllZWF_uid9_fpCosPiTest_q;
WHEN OTHERS => fracRPostExc1_uid86_fpCosPiTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--reg_excRNaN_uid84_fpCosPiTest_0_to_fracRPostExc_uid88_fpCosPiTest_1(REG,273)@0
reg_excRNaN_uid84_fpCosPiTest_0_to_fracRPostExc_uid88_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_excRNaN_uid84_fpCosPiTest_0_to_fracRPostExc_uid88_fpCosPiTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_excRNaN_uid84_fpCosPiTest_0_to_fracRPostExc_uid88_fpCosPiTest_1_q <= excRNaN_uid84_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_excRNaN_uid84_fpCosPiTest_0_to_fracRPostExc_uid88_fpCosPiTest_1_q_to_fracRPostExc_uid88_fpCosPiTest_b(DELAY,353)@1
ld_reg_excRNaN_uid84_fpCosPiTest_0_to_fracRPostExc_uid88_fpCosPiTest_1_q_to_fracRPostExc_uid88_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 16 )
PORT MAP ( xin => reg_excRNaN_uid84_fpCosPiTest_0_to_fracRPostExc_uid88_fpCosPiTest_1_q, xout => ld_reg_excRNaN_uid84_fpCosPiTest_0_to_fracRPostExc_uid88_fpCosPiTest_1_q_to_fracRPostExc_uid88_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--fracRPostExc_uid88_fpCosPiTest(MUX,87)@17
fracRPostExc_uid88_fpCosPiTest_s <= ld_reg_excRNaN_uid84_fpCosPiTest_0_to_fracRPostExc_uid88_fpCosPiTest_1_q_to_fracRPostExc_uid88_fpCosPiTest_b_q;
fracRPostExc_uid88_fpCosPiTest: PROCESS (fracRPostExc_uid88_fpCosPiTest_s, en, fracRPostExc1_uid86_fpCosPiTest_q, oneFracRPostExc2_uid87_fpCosPiTest_q)
BEGIN
CASE fracRPostExc_uid88_fpCosPiTest_s IS
WHEN "0" => fracRPostExc_uid88_fpCosPiTest_q <= fracRPostExc1_uid86_fpCosPiTest_q;
WHEN "1" => fracRPostExc_uid88_fpCosPiTest_q <= oneFracRPostExc2_uid87_fpCosPiTest_q;
WHEN OTHERS => fracRPostExc_uid88_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--R_uid102_fpCosPiTest(BITJOIN,101)@17
R_uid102_fpCosPiTest_q <= ld_signR_uid101_fpCosPiTest_q_to_R_uid102_fpCosPiTest_c_q & expRPostExc_uid95_fpCosPiTest_q & fracRPostExc_uid88_fpCosPiTest_q;
--xOut(GPOUT,4)@17
q <= R_uid102_fpCosPiTest_q;
end normal;
|
-----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Release Version 13.1
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing device programming or simulation files), and
-- any associated documentation or information are expressly subject to the
-- terms and conditions of the Altera Program License Subscription Agreement,
-- Altera MegaCore Function License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for the sole
-- purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
-----------------------------------------------------------------------------
-- VHDL created from fp_cospi_s5
-- VHDL created on Wed Feb 27 15:22:33 2013
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.all;
use std.TextIO.all;
use work.dspba_library_package.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
entity fp_cospi_s5 is
port (
a : in std_logic_vector(31 downto 0);
en : in std_logic_vector(0 downto 0);
q : out std_logic_vector(31 downto 0);
clk : in std_logic;
areset : in std_logic
);
end;
architecture normal of fp_cospi_s5 is
attribute altera_attribute : string;
attribute altera_attribute of normal : architecture is "-name NOT_GATE_PUSH_BACK OFF; -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON; -name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410";
signal GND_q : std_logic_vector (0 downto 0);
signal VCC_q : std_logic_vector (0 downto 0);
signal cstAllOWE_uid8_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal cstAllZWF_uid9_fpCosPiTest_q : std_logic_vector (22 downto 0);
signal cstBias_uid10_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal cstBiasM1_uid11_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal cstBiasPwF_uid12_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal biasMwShiftMO_uid13_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal cst01pWShift_uid14_fpCosPiTest_q : std_logic_vector (12 downto 0);
signal cstZwSwF_uid15_fpCosPiTest_q : std_logic_vector (34 downto 0);
signal cstAllZWE_uid21_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal rangeReducedFxPX_uid51_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal rangeReducedFxPX_uid51_fpCosPiTest_q : std_logic_vector (35 downto 0);
signal fracRPostExc1_uid86_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal fracRPostExc1_uid86_fpCosPiTest_q : std_logic_vector (22 downto 0);
signal oneFracRPostExc2_uid87_fpCosPiTest_q : std_logic_vector (22 downto 0);
signal expRPostExc1_uid91_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal expRPostExc1_uid91_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal signRComp_uid99_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal signRComp_uid99_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal signRComp_uid99_fpCosPiTest_c : std_logic_vector(0 downto 0);
signal signRComp_uid99_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal signR_uid101_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal signR_uid101_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal signR_uid101_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal leftShiftStage0Idx1Pad16_uid105_fxpX_uid41_fpCosPiTest_q : std_logic_vector (15 downto 0);
signal leftShiftStage0Idx2Pad32_uid108_fxpX_uid41_fpCosPiTest_q : std_logic_vector (31 downto 0);
signal leftShiftStage0Idx3_uid111_fxpX_uid41_fpCosPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage1Idx1Pad4_uid114_fxpX_uid41_fpCosPiTest_q : std_logic_vector (3 downto 0);
signal leftShiftStage1Idx3Pad12_uid120_fxpX_uid41_fpCosPiTest_q : std_logic_vector (11 downto 0);
signal leftShiftStage2Idx2Pad2_uid128_fxpX_uid41_fpCosPiTest_q : std_logic_vector (1 downto 0);
signal leftShiftStage2Idx3Pad3_uid131_fxpX_uid41_fpCosPiTest_q : std_logic_vector (2 downto 0);
signal mO_uid140_lzcZ_uid56_fpCosPiTest_q : std_logic_vector (28 downto 0);
signal memoryC2_uid209_sinPiZTableGenerator_q : std_logic_vector(13 downto 0);
signal prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_a : std_logic_vector (23 downto 0);
signal prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_b : std_logic_vector (24 downto 0);
signal prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_s1 : std_logic_vector (48 downto 0);
signal prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_pr : UNSIGNED (48 downto 0);
signal prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_q : std_logic_vector (48 downto 0);
signal prodXY_uid226_pT1_uid211_sinPiZPolyEval_a : std_logic_vector (13 downto 0);
signal prodXY_uid226_pT1_uid211_sinPiZPolyEval_b : std_logic_vector (13 downto 0);
signal prodXY_uid226_pT1_uid211_sinPiZPolyEval_s1 : std_logic_vector (27 downto 0);
signal prodXY_uid226_pT1_uid211_sinPiZPolyEval_pr : SIGNED (28 downto 0);
signal prodXY_uid226_pT1_uid211_sinPiZPolyEval_q : std_logic_vector (27 downto 0);
signal prodXY_uid229_pT2_uid217_sinPiZPolyEval_a : std_logic_vector (15 downto 0);
signal prodXY_uid229_pT2_uid217_sinPiZPolyEval_b : std_logic_vector (22 downto 0);
signal prodXY_uid229_pT2_uid217_sinPiZPolyEval_s1 : std_logic_vector (38 downto 0);
signal prodXY_uid229_pT2_uid217_sinPiZPolyEval_pr : SIGNED (39 downto 0);
signal prodXY_uid229_pT2_uid217_sinPiZPolyEval_q : std_logic_vector (38 downto 0);
signal reg_leftShiftStageSel3Dto2_uid123_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_2_q : std_logic_vector (36 downto 0);
signal reg_leftShiftStage1Idx1_uid116_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_3_q : std_logic_vector (36 downto 0);
signal reg_leftShiftStage1Idx2_uid119_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_4_q : std_logic_vector (36 downto 0);
signal reg_leftShiftStage1Idx3_uid122_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_5_q : std_logic_vector (36 downto 0);
signal reg_leftShiftStageSel1Dto0_uid134_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_fxpXFrac_uid43_fpCosPiTest_0_to_fxpXFracZero_uid45_fpCosPiTest_1_q : std_logic_vector (35 downto 0);
signal reg_cosXIsOne_uid36_fpCosPiTest_1_to_bigCond_uid85_fpCosPiTest_1_q : std_logic_vector (0 downto 0);
signal reg_xIsInt_uid80_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_2_q : std_logic_vector (0 downto 0);
signal reg_fxpXFracHalf_uid46_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_3_q : std_logic_vector (0 downto 0);
signal reg_expXIsZero_uid23_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_4_q : std_logic_vector (0 downto 0);
signal reg_xIsHalf_uid83_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_5_q : std_logic_vector (0 downto 0);
signal reg_pad_o_uid16_uid47_fpCosPiTest_0_to_oMFxpXFrac_uid47_fpCosPiTest_0_q : std_logic_vector (36 downto 0);
signal reg_pad_half_uid17_uid52_fpCosPiTest_0_to_z_halfMRRFxPXE_uid52_fpCosPiTest_0_q : std_logic_vector (35 downto 0);
signal reg_rVStage_uid138_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid139_lzcZ_uid56_fpCosPiTest_1_q : std_logic_vector (31 downto 0);
signal reg_cStage_uid142_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid144_lzcZ_uid56_fpCosPiTest_3_q : std_logic_vector (31 downto 0);
signal reg_rVStage_uid146_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid147_lzcZ_uid56_fpCosPiTest_1_q : std_logic_vector (15 downto 0);
signal reg_vStage_uid148_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid150_lzcZ_uid56_fpCosPiTest_3_q : std_logic_vector (15 downto 0);
signal reg_rVStage_uid158_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid159_lzcZ_uid56_fpCosPiTest_1_q : std_logic_vector (3 downto 0);
signal reg_vStage_uid160_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid162_lzcZ_uid56_fpCosPiTest_3_q : std_logic_vector (3 downto 0);
signal reg_vCount_uid153_lzcZ_uid56_fpCosPiTest_0_to_r_uid172_lzcZ_uid56_fpCosPiTest_3_q : std_logic_vector (0 downto 0);
signal reg_leftShiftStageSel3Dto2_uid193_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_2_q : std_logic_vector (34 downto 0);
signal reg_leftShiftStage1Idx1_uid186_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_3_q : std_logic_vector (34 downto 0);
signal reg_leftShiftStage1Idx2_uid189_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_4_q : std_logic_vector (34 downto 0);
signal reg_leftShiftStage1Idx3_uid192_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_5_q : std_logic_vector (34 downto 0);
signal reg_leftShiftStageSel1Dto0_uid204_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_zAddr_uid62_fpCosPiTest_0_to_memoryC2_uid209_sinPiZTableGenerator_0_q : std_logic_vector (6 downto 0);
signal reg_yT1_uid210_sinPiZPolyEval_0_to_prodXY_uid226_pT1_uid211_sinPiZPolyEval_0_q : std_logic_vector (13 downto 0);
signal reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_q : std_logic_vector (15 downto 0);
signal reg_s1_uid212_uid215_sinPiZPolyEval_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_1_q : std_logic_vector (22 downto 0);
signal reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_q : std_logic_vector (23 downto 0);
signal reg_fxpSinRes_uid65_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_1_q : std_logic_vector (24 downto 0);
signal reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q : std_logic_vector (5 downto 0);
signal reg_expP_uid60_fpCosPiTest_0_to_expFracPreRnd_uid71_uid71_fpCosPiTest_1_q : std_logic_vector (7 downto 0);
signal reg_excRNaN_uid84_fpCosPiTest_0_to_fracRPostExc_uid88_fpCosPiTest_1_q : std_logic_vector (0 downto 0);
signal reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q : std_logic_vector (1 downto 0);
signal ld_FxpXFrac35_uid44_fpCosPiTest_b_to_rangeReducedFxPX_uid51_fpCosPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_fxpXFrac_uid43_fpCosPiTest_b_to_rangeReducedFxPX_uid51_fpCosPiTest_c_q : std_logic_vector (35 downto 0);
signal ld_cosXIsOne_uid36_fpCosPiTest_c_to_InvCosXIsOne_uid77_fpCosPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_xEvenInt_uid35_fpCosPiTest_c_to_evenIntCosNotOneFZ_uid79_fpCosPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_exc_R_uid34_fpCosPiTest_q_to_xIsInt_uid80_fpCosPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_reg_cosXIsOne_uid36_fpCosPiTest_1_to_bigCond_uid85_fpCosPiTest_1_q_to_bigCond_uid85_fpCosPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_bigCond_uid85_fpCosPiTest_q_to_fracRPostExc1_uid86_fpCosPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_reg_excRNaN_uid84_fpCosPiTest_0_to_fracRPostExc_uid88_fpCosPiTest_1_q_to_fracRPostExc_uid88_fpCosPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_xIsHalf_uid83_fpCosPiTest_q_to_expRPostExc1_uid91_fpCosPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_expXIsZero_uid23_fpCosPiTest_q_to_xIntOrXZOrCosOne_uid93_fpCosPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_rInfOrNaN_uid92_fpCosPiTest_q_to_join_uid94_fpCosPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_xParityXorHalfParity_uid96_fpCosPiTest_q_to_signRComp_uid99_fpCosPiTest_c_q : std_logic_vector (0 downto 0);
signal ld_fxpXFracHalf_uid46_fpCosPiTest_q_to_InvFxpXFracHalf_uid100_fpCosPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_signR_uid101_fpCosPiTest_q_to_R_uid102_fpCosPiTest_c_q : std_logic_vector (0 downto 0);
signal ld_vCount_uid147_lzcZ_uid56_fpCosPiTest_q_to_r_uid172_lzcZ_uid56_fpCosPiTest_e_q : std_logic_vector (0 downto 0);
signal ld_vCount_uid139_lzcZ_uid56_fpCosPiTest_q_to_r_uid172_lzcZ_uid56_fpCosPiTest_f_q : std_logic_vector (0 downto 0);
signal ld_X18dto0_uid176_alignedZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx1_uid177_alignedZ_uid57_fpCosPiTest_b_q : std_logic_vector (18 downto 0);
signal ld_vStage_uid141_lzcZ_uid56_fpCosPiTest_b_to_leftShiftStage0Idx2_uid180_alignedZ_uid57_fpCosPiTest_b_q : std_logic_vector (2 downto 0);
signal ld_z_uid54_fpCosPiTest_b_to_leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_c_q : std_logic_vector (34 downto 0);
signal ld_reg_yT1_uid210_sinPiZPolyEval_0_to_prodXY_uid226_pT1_uid211_sinPiZPolyEval_0_q_to_prodXY_uid226_pT1_uid211_sinPiZPolyEval_a_q : std_logic_vector (13 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_reset0 : std_logic;
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_ia : std_logic_vector (5 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_iq : std_logic_vector (5 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_q : std_logic_vector (5 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt_eq : std_logic;
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_mem_top_q : std_logic_vector (3 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve : boolean;
attribute preserve of ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_sticky_ena_q : signal is true;
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_reset0 : std_logic;
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_ia : std_logic_vector (1 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_iq : std_logic_vector (1 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_q : std_logic_vector (1 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt_eq : std_logic;
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_mem_top_q : std_logic_vector (4 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_sticky_ena_q : signal is true;
signal ld_X18dto0_uid176_alignedZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx1_uid177_alignedZ_uid57_fpCosPiTest_b_inputreg_q : std_logic_vector (18 downto 0);
signal ld_z_uid54_fpCosPiTest_b_to_leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_c_inputreg_q : std_logic_vector (34 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_reset0 : std_logic;
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_ia : std_logic_vector (6 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_iq : std_logic_vector (6 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_q : std_logic_vector (6 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_sticky_ena_q : signal is true;
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_reset0 : std_logic;
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_ia : std_logic_vector (6 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_aa : std_logic_vector (1 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_ab : std_logic_vector (1 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_iq : std_logic_vector (6 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_q : std_logic_vector (6 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt_q : std_logic_vector(1 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt_i : unsigned(1 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt_eq : std_logic;
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdreg_q : std_logic_vector (1 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_mem_top_q : std_logic_vector (2 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_sticky_ena_q : signal is true;
signal ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_inputreg_q : std_logic_vector (15 downto 0);
signal ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_reset0 : std_logic;
signal ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_ia : std_logic_vector (15 downto 0);
signal ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_aa : std_logic_vector (1 downto 0);
signal ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_ab : std_logic_vector (1 downto 0);
signal ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_iq : std_logic_vector (15 downto 0);
signal ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_q : std_logic_vector (15 downto 0);
signal ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_sticky_ena_q : signal is true;
signal ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_inputreg_q : std_logic_vector (23 downto 0);
signal ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_reset0 : std_logic;
signal ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_ia : std_logic_vector (23 downto 0);
signal ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_aa : std_logic_vector (1 downto 0);
signal ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_ab : std_logic_vector (1 downto 0);
signal ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_iq : std_logic_vector (23 downto 0);
signal ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_q : std_logic_vector (23 downto 0);
signal ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_sticky_ena_q : signal is true;
signal pad_o_uid16_uid47_fpCosPiTest_q : std_logic_vector (36 downto 0);
signal pad_half_uid17_uid52_fpCosPiTest_q : std_logic_vector (35 downto 0);
signal bigCond_uid85_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal bigCond_uid85_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal bigCond_uid85_fpCosPiTest_c : std_logic_vector(0 downto 0);
signal bigCond_uid85_fpCosPiTest_d : std_logic_vector(0 downto 0);
signal bigCond_uid85_fpCosPiTest_f : std_logic_vector(0 downto 0);
signal bigCond_uid85_fpCosPiTest_g : std_logic_vector(0 downto 0);
signal bigCond_uid85_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal InvCosXIsOne_uid77_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal InvCosXIsOne_uid77_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal InvXEvenInt_uid81_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal InvXEvenInt_uid81_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal InvFxpXFracHalf_uid100_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal InvFxpXFracHalf_uid100_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal cstHalfwSwFP1_uid18_fpCosPiTest_q : std_logic_vector (35 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_notEnable_a : std_logic_vector(0 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_notEnable_q : std_logic_vector(0 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdmux_q : std_logic_vector (1 downto 0);
signal expX_uid6_fpCosPiTest_in : std_logic_vector (30 downto 0);
signal expX_uid6_fpCosPiTest_b : std_logic_vector (7 downto 0);
signal fracX_uid7_fpCosPiTest_in : std_logic_vector (22 downto 0);
signal fracX_uid7_fpCosPiTest_b : std_logic_vector (22 downto 0);
signal expXIsZero_uid23_fpCosPiTest_a : std_logic_vector(7 downto 0);
signal expXIsZero_uid23_fpCosPiTest_b : std_logic_vector(7 downto 0);
signal expXIsZero_uid23_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal expXIsMax_uid25_fpCosPiTest_a : std_logic_vector(7 downto 0);
signal expXIsMax_uid25_fpCosPiTest_b : std_logic_vector(7 downto 0);
signal expXIsMax_uid25_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal fracXIsZero_uid27_fpCosPiTest_a : std_logic_vector(22 downto 0);
signal fracXIsZero_uid27_fpCosPiTest_b : std_logic_vector(22 downto 0);
signal fracXIsZero_uid27_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal exc_I_uid28_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal exc_I_uid28_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal exc_I_uid28_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal xEvenInt_uid35_fpCosPiTest_a : std_logic_vector(10 downto 0);
signal xEvenInt_uid35_fpCosPiTest_b : std_logic_vector(10 downto 0);
signal xEvenInt_uid35_fpCosPiTest_o : std_logic_vector (10 downto 0);
signal xEvenInt_uid35_fpCosPiTest_cin : std_logic_vector (0 downto 0);
signal xEvenInt_uid35_fpCosPiTest_c : std_logic_vector (0 downto 0);
signal cosXIsOne_uid36_fpCosPiTest_a : std_logic_vector(10 downto 0);
signal cosXIsOne_uid36_fpCosPiTest_b : std_logic_vector(10 downto 0);
signal cosXIsOne_uid36_fpCosPiTest_o : std_logic_vector (10 downto 0);
signal cosXIsOne_uid36_fpCosPiTest_cin : std_logic_vector (0 downto 0);
signal cosXIsOne_uid36_fpCosPiTest_c : std_logic_vector (0 downto 0);
signal shiftValFxPX_uid38_fpCosPiTest_a : std_logic_vector(8 downto 0);
signal shiftValFxPX_uid38_fpCosPiTest_b : std_logic_vector(8 downto 0);
signal shiftValFxPX_uid38_fpCosPiTest_o : std_logic_vector (8 downto 0);
signal shiftValFxPX_uid38_fpCosPiTest_q : std_logic_vector (8 downto 0);
signal fxpXFracZero_uid45_fpCosPiTest_a : std_logic_vector(35 downto 0);
signal fxpXFracZero_uid45_fpCosPiTest_b : std_logic_vector(35 downto 0);
signal fxpXFracZero_uid45_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal fxpXFracHalf_uid46_fpCosPiTest_a : std_logic_vector(35 downto 0);
signal fxpXFracHalf_uid46_fpCosPiTest_b : std_logic_vector(35 downto 0);
signal fxpXFracHalf_uid46_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal oMFxpXFrac_uid47_fpCosPiTest_a : std_logic_vector(37 downto 0);
signal oMFxpXFrac_uid47_fpCosPiTest_b : std_logic_vector(37 downto 0);
signal oMFxpXFrac_uid47_fpCosPiTest_o : std_logic_vector (37 downto 0);
signal oMFxpXFrac_uid47_fpCosPiTest_q : std_logic_vector (37 downto 0);
signal z_halfMRRFxPXE_uid52_fpCosPiTest_a : std_logic_vector(36 downto 0);
signal z_halfMRRFxPXE_uid52_fpCosPiTest_b : std_logic_vector(36 downto 0);
signal z_halfMRRFxPXE_uid52_fpCosPiTest_o : std_logic_vector (36 downto 0);
signal z_halfMRRFxPXE_uid52_fpCosPiTest_q : std_logic_vector (36 downto 0);
signal expHardCase_uid59_fpCosPiTest_a : std_logic_vector(8 downto 0);
signal expHardCase_uid59_fpCosPiTest_b : std_logic_vector(8 downto 0);
signal expHardCase_uid59_fpCosPiTest_o : std_logic_vector (8 downto 0);
signal expHardCase_uid59_fpCosPiTest_q : std_logic_vector (8 downto 0);
signal fracZCosNotOne_uid78_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal fracZCosNotOne_uid78_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal fracZCosNotOne_uid78_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal evenIntCosNotOneFZ_uid79_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal evenIntCosNotOneFZ_uid79_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal evenIntCosNotOneFZ_uid79_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal xIsInt_uid80_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal xIsInt_uid80_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal xIsInt_uid80_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal xIsHalf_uid83_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal xIsHalf_uid83_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal xIsHalf_uid83_fpCosPiTest_c : std_logic_vector(0 downto 0);
signal xIsHalf_uid83_fpCosPiTest_d : std_logic_vector(0 downto 0);
signal xIsHalf_uid83_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal fracRPostExc_uid88_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal fracRPostExc_uid88_fpCosPiTest_q : std_logic_vector (22 downto 0);
signal xIntOrXZOrCosOne_uid93_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal xIntOrXZOrCosOne_uid93_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal xIntOrXZOrCosOne_uid93_fpCosPiTest_c : std_logic_vector(0 downto 0);
signal xIntOrXZOrCosOne_uid93_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal expRPostExc_uid95_fpCosPiTest_s : std_logic_vector (1 downto 0);
signal expRPostExc_uid95_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_q : std_logic_vector (36 downto 0);
signal vCount_uid139_lzcZ_uid56_fpCosPiTest_a : std_logic_vector(31 downto 0);
signal vCount_uid139_lzcZ_uid56_fpCosPiTest_b : std_logic_vector(31 downto 0);
signal vCount_uid139_lzcZ_uid56_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid144_lzcZ_uid56_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid144_lzcZ_uid56_fpCosPiTest_q : std_logic_vector (31 downto 0);
signal vCount_uid147_lzcZ_uid56_fpCosPiTest_a : std_logic_vector(15 downto 0);
signal vCount_uid147_lzcZ_uid56_fpCosPiTest_b : std_logic_vector(15 downto 0);
signal vCount_uid147_lzcZ_uid56_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid150_lzcZ_uid56_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid150_lzcZ_uid56_fpCosPiTest_q : std_logic_vector (15 downto 0);
signal vCount_uid159_lzcZ_uid56_fpCosPiTest_a : std_logic_vector(3 downto 0);
signal vCount_uid159_lzcZ_uid56_fpCosPiTest_b : std_logic_vector(3 downto 0);
signal vCount_uid159_lzcZ_uid56_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid162_lzcZ_uid56_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid162_lzcZ_uid56_fpCosPiTest_q : std_logic_vector (3 downto 0);
signal leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_q : std_logic_vector (34 downto 0);
signal memoryC0_uid207_sinPiZTableGenerator_q : std_logic_vector(28 downto 0);
signal memoryC1_uid208_sinPiZTableGenerator_q : std_logic_vector(20 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal leftShiftStage0Idx1_uid177_alignedZ_uid57_fpCosPiTest_q : std_logic_vector (34 downto 0);
signal leftShiftStage0Idx2_uid180_alignedZ_uid57_fpCosPiTest_q : std_logic_vector (34 downto 0);
signal prodXYTruncFR_uid224_mul2xSinRes_uid66_fpCosPiTest_in : std_logic_vector (48 downto 0);
signal prodXYTruncFR_uid224_mul2xSinRes_uid66_fpCosPiTest_b : std_logic_vector (25 downto 0);
signal prodXYTruncFR_uid227_pT1_uid211_sinPiZPolyEval_in : std_logic_vector (27 downto 0);
signal prodXYTruncFR_uid227_pT1_uid211_sinPiZPolyEval_b : std_logic_vector (14 downto 0);
signal prodXYTruncFR_uid230_pT2_uid217_sinPiZPolyEval_in : std_logic_vector (38 downto 0);
signal prodXYTruncFR_uid230_pT2_uid217_sinPiZPolyEval_b : std_logic_vector (23 downto 0);
signal join_uid94_fpCosPiTest_q : std_logic_vector (1 downto 0);
signal R_uid102_fpCosPiTest_q : std_logic_vector (31 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_cmp_a : std_logic_vector(3 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_cmp_b : std_logic_vector(3 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_cmp_a : std_logic_vector(4 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_cmp_b : std_logic_vector(4 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_cmp_a : std_logic_vector(2 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_cmp_b : std_logic_vector(2 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_nor_q : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_nor_q : std_logic_vector(0 downto 0);
signal oFracX_uid37_uid37_fpCosPiTest_q : std_logic_vector (23 downto 0);
signal InvExpXIsZero_uid33_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid33_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid29_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid29_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal InvExc_I_uid32_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal InvExc_I_uid32_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal fxpShifterBits_uid40_fpCosPiTest_in : std_logic_vector (5 downto 0);
signal fxpShifterBits_uid40_fpCosPiTest_b : std_logic_vector (5 downto 0);
signal oMFxpXFrac_uid49_fpCosPiTest_in : std_logic_vector (35 downto 0);
signal oMFxpXFrac_uid49_fpCosPiTest_b : std_logic_vector (35 downto 0);
signal z_uid54_fpCosPiTest_in : std_logic_vector (34 downto 0);
signal z_uid54_fpCosPiTest_b : std_logic_vector (34 downto 0);
signal expP_uid60_fpCosPiTest_in : std_logic_vector (7 downto 0);
signal expP_uid60_fpCosPiTest_b : std_logic_vector (7 downto 0);
signal LeftShiftStage135dto0_uid126_fxpX_uid41_fpCosPiTest_in : std_logic_vector (35 downto 0);
signal LeftShiftStage135dto0_uid126_fxpX_uid41_fpCosPiTest_b : std_logic_vector (35 downto 0);
signal LeftShiftStage134dto0_uid129_fxpX_uid41_fpCosPiTest_in : std_logic_vector (34 downto 0);
signal LeftShiftStage134dto0_uid129_fxpX_uid41_fpCosPiTest_b : std_logic_vector (34 downto 0);
signal LeftShiftStage133dto0_uid132_fxpX_uid41_fpCosPiTest_in : std_logic_vector (33 downto 0);
signal LeftShiftStage133dto0_uid132_fxpX_uid41_fpCosPiTest_b : std_logic_vector (33 downto 0);
signal rVStage_uid146_lzcZ_uid56_fpCosPiTest_in : std_logic_vector (31 downto 0);
signal rVStage_uid146_lzcZ_uid56_fpCosPiTest_b : std_logic_vector (15 downto 0);
signal vStage_uid148_lzcZ_uid56_fpCosPiTest_in : std_logic_vector (15 downto 0);
signal vStage_uid148_lzcZ_uid56_fpCosPiTest_b : std_logic_vector (15 downto 0);
signal rVStage_uid152_lzcZ_uid56_fpCosPiTest_in : std_logic_vector (15 downto 0);
signal rVStage_uid152_lzcZ_uid56_fpCosPiTest_b : std_logic_vector (7 downto 0);
signal vStage_uid154_lzcZ_uid56_fpCosPiTest_in : std_logic_vector (7 downto 0);
signal vStage_uid154_lzcZ_uid56_fpCosPiTest_b : std_logic_vector (7 downto 0);
signal rVStage_uid164_lzcZ_uid56_fpCosPiTest_in : std_logic_vector (3 downto 0);
signal rVStage_uid164_lzcZ_uid56_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal vStage_uid166_lzcZ_uid56_fpCosPiTest_in : std_logic_vector (1 downto 0);
signal vStage_uid166_lzcZ_uid56_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal LeftShiftStage133dto0_uid196_alignedZ_uid57_fpCosPiTest_in : std_logic_vector (33 downto 0);
signal LeftShiftStage133dto0_uid196_alignedZ_uid57_fpCosPiTest_b : std_logic_vector (33 downto 0);
signal LeftShiftStage132dto0_uid199_alignedZ_uid57_fpCosPiTest_in : std_logic_vector (32 downto 0);
signal LeftShiftStage132dto0_uid199_alignedZ_uid57_fpCosPiTest_b : std_logic_vector (32 downto 0);
signal LeftShiftStage131dto0_uid202_alignedZ_uid57_fpCosPiTest_in : std_logic_vector (31 downto 0);
signal LeftShiftStage131dto0_uid202_alignedZ_uid57_fpCosPiTest_b : std_logic_vector (31 downto 0);
signal normBit_uid67_fpCosPiTest_in : std_logic_vector (25 downto 0);
signal normBit_uid67_fpCosPiTest_b : std_logic_vector (0 downto 0);
signal highRes_uid68_fpCosPiTest_in : std_logic_vector (24 downto 0);
signal highRes_uid68_fpCosPiTest_b : std_logic_vector (23 downto 0);
signal lowRes_uid69_fpCosPiTest_in : std_logic_vector (23 downto 0);
signal lowRes_uid69_fpCosPiTest_b : std_logic_vector (23 downto 0);
signal lowRangeB_uid212_sinPiZPolyEval_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid212_sinPiZPolyEval_b : std_logic_vector (0 downto 0);
signal highBBits_uid213_sinPiZPolyEval_in : std_logic_vector (14 downto 0);
signal highBBits_uid213_sinPiZPolyEval_b : std_logic_vector (13 downto 0);
signal lowRangeB_uid218_sinPiZPolyEval_in : std_logic_vector (1 downto 0);
signal lowRangeB_uid218_sinPiZPolyEval_b : std_logic_vector (1 downto 0);
signal highBBits_uid219_sinPiZPolyEval_in : std_logic_vector (23 downto 0);
signal highBBits_uid219_sinPiZPolyEval_b : std_logic_vector (21 downto 0);
signal oFracXExt_uid39_fpCosPiTest_q : std_logic_vector (36 downto 0);
signal exc_N_uid30_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal exc_N_uid30_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal exc_N_uid30_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal leftShiftStageSel5Dto4_uid112_fxpX_uid41_fpCosPiTest_in : std_logic_vector (5 downto 0);
signal leftShiftStageSel5Dto4_uid112_fxpX_uid41_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel3Dto2_uid123_fxpX_uid41_fpCosPiTest_in : std_logic_vector (3 downto 0);
signal leftShiftStageSel3Dto2_uid123_fxpX_uid41_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid134_fxpX_uid41_fpCosPiTest_in : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid134_fxpX_uid41_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal zAddr_uid62_fpCosPiTest_in : std_logic_vector (34 downto 0);
signal zAddr_uid62_fpCosPiTest_b : std_logic_vector (6 downto 0);
signal zPPolyEval_uid63_fpCosPiTest_in : std_logic_vector (27 downto 0);
signal zPPolyEval_uid63_fpCosPiTest_b : std_logic_vector (15 downto 0);
signal rVStage_uid138_lzcZ_uid56_fpCosPiTest_in : std_logic_vector (34 downto 0);
signal rVStage_uid138_lzcZ_uid56_fpCosPiTest_b : std_logic_vector (31 downto 0);
signal vStage_uid141_lzcZ_uid56_fpCosPiTest_in : std_logic_vector (2 downto 0);
signal vStage_uid141_lzcZ_uid56_fpCosPiTest_b : std_logic_vector (2 downto 0);
signal X18dto0_uid176_alignedZ_uid57_fpCosPiTest_in : std_logic_vector (18 downto 0);
signal X18dto0_uid176_alignedZ_uid57_fpCosPiTest_b : std_logic_vector (18 downto 0);
signal leftShiftStage2Idx1_uid127_fxpX_uid41_fpCosPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage2Idx2_uid130_fxpX_uid41_fpCosPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage2Idx3_uid133_fxpX_uid41_fpCosPiTest_q : std_logic_vector (36 downto 0);
signal vCount_uid153_lzcZ_uid56_fpCosPiTest_a : std_logic_vector(7 downto 0);
signal vCount_uid153_lzcZ_uid56_fpCosPiTest_b : std_logic_vector(7 downto 0);
signal vCount_uid153_lzcZ_uid56_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid156_lzcZ_uid56_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid156_lzcZ_uid56_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal vCount_uid165_lzcZ_uid56_fpCosPiTest_a : std_logic_vector(1 downto 0);
signal vCount_uid165_lzcZ_uid56_fpCosPiTest_b : std_logic_vector(1 downto 0);
signal vCount_uid165_lzcZ_uid56_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid168_lzcZ_uid56_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid168_lzcZ_uid56_fpCosPiTest_q : std_logic_vector (1 downto 0);
signal leftShiftStage2Idx1_uid197_alignedZ_uid57_fpCosPiTest_q : std_logic_vector (34 downto 0);
signal leftShiftStage2Idx2_uid200_alignedZ_uid57_fpCosPiTest_q : std_logic_vector (34 downto 0);
signal leftShiftStage2Idx3_uid203_alignedZ_uid57_fpCosPiTest_q : std_logic_vector (34 downto 0);
signal fracRCompPreRnd_uid70_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal fracRCompPreRnd_uid70_fpCosPiTest_q : std_logic_vector (23 downto 0);
signal rndExpUpdate_uid72_uid73_fpCosPiTest_q : std_logic_vector (24 downto 0);
signal sumAHighB_uid214_sinPiZPolyEval_a : std_logic_vector(21 downto 0);
signal sumAHighB_uid214_sinPiZPolyEval_b : std_logic_vector(21 downto 0);
signal sumAHighB_uid214_sinPiZPolyEval_o : std_logic_vector (21 downto 0);
signal sumAHighB_uid214_sinPiZPolyEval_q : std_logic_vector (21 downto 0);
signal sumAHighB_uid220_sinPiZPolyEval_a : std_logic_vector(29 downto 0);
signal sumAHighB_uid220_sinPiZPolyEval_b : std_logic_vector(29 downto 0);
signal sumAHighB_uid220_sinPiZPolyEval_o : std_logic_vector (29 downto 0);
signal sumAHighB_uid220_sinPiZPolyEval_q : std_logic_vector (29 downto 0);
signal X20dto0_uid106_fxpX_uid41_fpCosPiTest_in : std_logic_vector (20 downto 0);
signal X20dto0_uid106_fxpX_uid41_fpCosPiTest_b : std_logic_vector (20 downto 0);
signal X4dto0_uid109_fxpX_uid41_fpCosPiTest_in : std_logic_vector (4 downto 0);
signal X4dto0_uid109_fxpX_uid41_fpCosPiTest_b : std_logic_vector (4 downto 0);
signal InvExc_N_uid31_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal InvExc_N_uid31_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal excRNaN_uid84_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal excRNaN_uid84_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal excRNaN_uid84_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal yT1_uid210_sinPiZPolyEval_in : std_logic_vector (15 downto 0);
signal yT1_uid210_sinPiZPolyEval_b : std_logic_vector (13 downto 0);
signal cStage_uid142_lzcZ_uid56_fpCosPiTest_q : std_logic_vector (31 downto 0);
signal leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest_q : std_logic_vector (36 downto 0);
signal rVStage_uid158_lzcZ_uid56_fpCosPiTest_in : std_logic_vector (7 downto 0);
signal rVStage_uid158_lzcZ_uid56_fpCosPiTest_b : std_logic_vector (3 downto 0);
signal vStage_uid160_lzcZ_uid56_fpCosPiTest_in : std_logic_vector (3 downto 0);
signal vStage_uid160_lzcZ_uid56_fpCosPiTest_b : std_logic_vector (3 downto 0);
signal rVStage_uid170_lzcZ_uid56_fpCosPiTest_in : std_logic_vector (1 downto 0);
signal rVStage_uid170_lzcZ_uid56_fpCosPiTest_b : std_logic_vector (0 downto 0);
signal leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest_q : std_logic_vector (34 downto 0);
signal expFracPreRnd_uid71_uid71_fpCosPiTest_q : std_logic_vector (31 downto 0);
signal expFracComp_uid74_fpCosPiTest_a : std_logic_vector(32 downto 0);
signal expFracComp_uid74_fpCosPiTest_b : std_logic_vector(32 downto 0);
signal expFracComp_uid74_fpCosPiTest_o : std_logic_vector (32 downto 0);
signal expFracComp_uid74_fpCosPiTest_q : std_logic_vector (32 downto 0);
signal s1_uid212_uid215_sinPiZPolyEval_q : std_logic_vector (22 downto 0);
signal s2_uid218_uid221_sinPiZPolyEval_q : std_logic_vector (31 downto 0);
signal leftShiftStage0Idx1_uid107_fxpX_uid41_fpCosPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage0Idx2_uid110_fxpX_uid41_fpCosPiTest_q : std_logic_vector (36 downto 0);
signal exc_R_uid34_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal exc_R_uid34_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal exc_R_uid34_fpCosPiTest_c : std_logic_vector(0 downto 0);
signal exc_R_uid34_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal rInfOrNaN_uid92_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal rInfOrNaN_uid92_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal rInfOrNaN_uid92_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal FxpX36_uid42_fpCosPiTest_in : std_logic_vector (36 downto 0);
signal FxpX36_uid42_fpCosPiTest_b : std_logic_vector (0 downto 0);
signal fxpXFrac_uid43_fpCosPiTest_in : std_logic_vector (35 downto 0);
signal fxpXFrac_uid43_fpCosPiTest_b : std_logic_vector (35 downto 0);
signal vCount_uid171_lzcZ_uid56_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal vCount_uid171_lzcZ_uid56_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal vCount_uid171_lzcZ_uid56_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal alignedZLow_uid58_fpCosPiTest_in : std_logic_vector (34 downto 0);
signal alignedZLow_uid58_fpCosPiTest_b : std_logic_vector (23 downto 0);
signal fracRComp_uid75_fpCosPiTest_in : std_logic_vector (23 downto 0);
signal fracRComp_uid75_fpCosPiTest_b : std_logic_vector (22 downto 0);
signal expRComp_uid76_fpCosPiTest_in : std_logic_vector (31 downto 0);
signal expRComp_uid76_fpCosPiTest_b : std_logic_vector (7 downto 0);
signal fxpSinRes_uid65_fpCosPiTest_in : std_logic_vector (29 downto 0);
signal fxpSinRes_uid65_fpCosPiTest_b : std_logic_vector (24 downto 0);
signal leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_q : std_logic_vector (36 downto 0);
signal FxpXFrac35_uid44_fpCosPiTest_in : std_logic_vector (35 downto 0);
signal FxpXFrac35_uid44_fpCosPiTest_b : std_logic_vector (0 downto 0);
signal r_uid172_lzcZ_uid56_fpCosPiTest_q : std_logic_vector (5 downto 0);
signal LeftShiftStage032dto0_uid115_fxpX_uid41_fpCosPiTest_in : std_logic_vector (32 downto 0);
signal LeftShiftStage032dto0_uid115_fxpX_uid41_fpCosPiTest_b : std_logic_vector (32 downto 0);
signal LeftShiftStage028dto0_uid118_fxpX_uid41_fpCosPiTest_in : std_logic_vector (28 downto 0);
signal LeftShiftStage028dto0_uid118_fxpX_uid41_fpCosPiTest_b : std_logic_vector (28 downto 0);
signal LeftShiftStage024dto0_uid121_fxpX_uid41_fpCosPiTest_in : std_logic_vector (24 downto 0);
signal LeftShiftStage024dto0_uid121_fxpX_uid41_fpCosPiTest_b : std_logic_vector (24 downto 0);
signal xParityXorHalfParity_uid96_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal xParityXorHalfParity_uid96_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal xParityXorHalfParity_uid96_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal leftShiftStageSel5Dto4_uid182_alignedZ_uid57_fpCosPiTest_in : std_logic_vector (5 downto 0);
signal leftShiftStageSel5Dto4_uid182_alignedZ_uid57_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel3Dto2_uid193_alignedZ_uid57_fpCosPiTest_in : std_logic_vector (3 downto 0);
signal leftShiftStageSel3Dto2_uid193_alignedZ_uid57_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid204_alignedZ_uid57_fpCosPiTest_in : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid204_alignedZ_uid57_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStage1Idx1_uid116_fxpX_uid41_fpCosPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage1Idx2_uid119_fxpX_uid41_fpCosPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage1Idx3_uid122_fxpX_uid41_fpCosPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_q : std_logic_vector (34 downto 0);
signal LeftShiftStage030dto0_uid185_alignedZ_uid57_fpCosPiTest_in : std_logic_vector (30 downto 0);
signal LeftShiftStage030dto0_uid185_alignedZ_uid57_fpCosPiTest_b : std_logic_vector (30 downto 0);
signal LeftShiftStage026dto0_uid188_alignedZ_uid57_fpCosPiTest_in : std_logic_vector (26 downto 0);
signal LeftShiftStage026dto0_uid188_alignedZ_uid57_fpCosPiTest_b : std_logic_vector (26 downto 0);
signal LeftShiftStage022dto0_uid191_alignedZ_uid57_fpCosPiTest_in : std_logic_vector (22 downto 0);
signal LeftShiftStage022dto0_uid191_alignedZ_uid57_fpCosPiTest_b : std_logic_vector (22 downto 0);
signal leftShiftStage1Idx1_uid186_alignedZ_uid57_fpCosPiTest_q : std_logic_vector (34 downto 0);
signal leftShiftStage1Idx2_uid189_alignedZ_uid57_fpCosPiTest_q : std_logic_vector (34 downto 0);
signal leftShiftStage1Idx3_uid192_alignedZ_uid57_fpCosPiTest_q : std_logic_vector (34 downto 0);
begin
--xIn(GPIN,3)@0
--LeftShiftStage133dto0_uid132_fxpX_uid41_fpCosPiTest(BITSELECT,131)@1
LeftShiftStage133dto0_uid132_fxpX_uid41_fpCosPiTest_in <= leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_q(33 downto 0);
LeftShiftStage133dto0_uid132_fxpX_uid41_fpCosPiTest_b <= LeftShiftStage133dto0_uid132_fxpX_uid41_fpCosPiTest_in(33 downto 0);
--leftShiftStage2Idx3Pad3_uid131_fxpX_uid41_fpCosPiTest(CONSTANT,130)
leftShiftStage2Idx3Pad3_uid131_fxpX_uid41_fpCosPiTest_q <= "000";
--leftShiftStage2Idx3_uid133_fxpX_uid41_fpCosPiTest(BITJOIN,132)@1
leftShiftStage2Idx3_uid133_fxpX_uid41_fpCosPiTest_q <= LeftShiftStage133dto0_uid132_fxpX_uid41_fpCosPiTest_b & leftShiftStage2Idx3Pad3_uid131_fxpX_uid41_fpCosPiTest_q;
--LeftShiftStage134dto0_uid129_fxpX_uid41_fpCosPiTest(BITSELECT,128)@1
LeftShiftStage134dto0_uid129_fxpX_uid41_fpCosPiTest_in <= leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_q(34 downto 0);
LeftShiftStage134dto0_uid129_fxpX_uid41_fpCosPiTest_b <= LeftShiftStage134dto0_uid129_fxpX_uid41_fpCosPiTest_in(34 downto 0);
--leftShiftStage2Idx2Pad2_uid128_fxpX_uid41_fpCosPiTest(CONSTANT,127)
leftShiftStage2Idx2Pad2_uid128_fxpX_uid41_fpCosPiTest_q <= "00";
--leftShiftStage2Idx2_uid130_fxpX_uid41_fpCosPiTest(BITJOIN,129)@1
leftShiftStage2Idx2_uid130_fxpX_uid41_fpCosPiTest_q <= LeftShiftStage134dto0_uid129_fxpX_uid41_fpCosPiTest_b & leftShiftStage2Idx2Pad2_uid128_fxpX_uid41_fpCosPiTest_q;
--LeftShiftStage135dto0_uid126_fxpX_uid41_fpCosPiTest(BITSELECT,125)@1
LeftShiftStage135dto0_uid126_fxpX_uid41_fpCosPiTest_in <= leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_q(35 downto 0);
LeftShiftStage135dto0_uid126_fxpX_uid41_fpCosPiTest_b <= LeftShiftStage135dto0_uid126_fxpX_uid41_fpCosPiTest_in(35 downto 0);
--GND(CONSTANT,0)
GND_q <= "0";
--leftShiftStage2Idx1_uid127_fxpX_uid41_fpCosPiTest(BITJOIN,126)@1
leftShiftStage2Idx1_uid127_fxpX_uid41_fpCosPiTest_q <= LeftShiftStage135dto0_uid126_fxpX_uid41_fpCosPiTest_b & GND_q;
--leftShiftStage0Idx3_uid111_fxpX_uid41_fpCosPiTest(CONSTANT,110)
leftShiftStage0Idx3_uid111_fxpX_uid41_fpCosPiTest_q <= "0000000000000000000000000000000000000";
--X4dto0_uid109_fxpX_uid41_fpCosPiTest(BITSELECT,108)@0
X4dto0_uid109_fxpX_uid41_fpCosPiTest_in <= oFracXExt_uid39_fpCosPiTest_q(4 downto 0);
X4dto0_uid109_fxpX_uid41_fpCosPiTest_b <= X4dto0_uid109_fxpX_uid41_fpCosPiTest_in(4 downto 0);
--leftShiftStage0Idx2Pad32_uid108_fxpX_uid41_fpCosPiTest(CONSTANT,107)
leftShiftStage0Idx2Pad32_uid108_fxpX_uid41_fpCosPiTest_q <= "00000000000000000000000000000000";
--leftShiftStage0Idx2_uid110_fxpX_uid41_fpCosPiTest(BITJOIN,109)@0
leftShiftStage0Idx2_uid110_fxpX_uid41_fpCosPiTest_q <= X4dto0_uid109_fxpX_uid41_fpCosPiTest_b & leftShiftStage0Idx2Pad32_uid108_fxpX_uid41_fpCosPiTest_q;
--X20dto0_uid106_fxpX_uid41_fpCosPiTest(BITSELECT,105)@0
X20dto0_uid106_fxpX_uid41_fpCosPiTest_in <= oFracXExt_uid39_fpCosPiTest_q(20 downto 0);
X20dto0_uid106_fxpX_uid41_fpCosPiTest_b <= X20dto0_uid106_fxpX_uid41_fpCosPiTest_in(20 downto 0);
--leftShiftStage0Idx1Pad16_uid105_fxpX_uid41_fpCosPiTest(CONSTANT,104)
leftShiftStage0Idx1Pad16_uid105_fxpX_uid41_fpCosPiTest_q <= "0000000000000000";
--leftShiftStage0Idx1_uid107_fxpX_uid41_fpCosPiTest(BITJOIN,106)@0
leftShiftStage0Idx1_uid107_fxpX_uid41_fpCosPiTest_q <= X20dto0_uid106_fxpX_uid41_fpCosPiTest_b & leftShiftStage0Idx1Pad16_uid105_fxpX_uid41_fpCosPiTest_q;
--cst01pWShift_uid14_fpCosPiTest(CONSTANT,13)
cst01pWShift_uid14_fpCosPiTest_q <= "0000000000000";
--VCC(CONSTANT,1)
VCC_q <= "1";
--fracX_uid7_fpCosPiTest(BITSELECT,6)@0
fracX_uid7_fpCosPiTest_in <= a(22 downto 0);
fracX_uid7_fpCosPiTest_b <= fracX_uid7_fpCosPiTest_in(22 downto 0);
--oFracX_uid37_uid37_fpCosPiTest(BITJOIN,36)@0
oFracX_uid37_uid37_fpCosPiTest_q <= VCC_q & fracX_uid7_fpCosPiTest_b;
--oFracXExt_uid39_fpCosPiTest(BITJOIN,38)@0
oFracXExt_uid39_fpCosPiTest_q <= cst01pWShift_uid14_fpCosPiTest_q & oFracX_uid37_uid37_fpCosPiTest_q;
--biasMwShiftMO_uid13_fpCosPiTest(CONSTANT,12)
biasMwShiftMO_uid13_fpCosPiTest_q <= "01110010";
--expX_uid6_fpCosPiTest(BITSELECT,5)@0
expX_uid6_fpCosPiTest_in <= a(30 downto 0);
expX_uid6_fpCosPiTest_b <= expX_uid6_fpCosPiTest_in(30 downto 23);
--shiftValFxPX_uid38_fpCosPiTest(SUB,37)@0
shiftValFxPX_uid38_fpCosPiTest_a <= STD_LOGIC_VECTOR("0" & expX_uid6_fpCosPiTest_b);
shiftValFxPX_uid38_fpCosPiTest_b <= STD_LOGIC_VECTOR("0" & biasMwShiftMO_uid13_fpCosPiTest_q);
shiftValFxPX_uid38_fpCosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(shiftValFxPX_uid38_fpCosPiTest_a) - UNSIGNED(shiftValFxPX_uid38_fpCosPiTest_b));
shiftValFxPX_uid38_fpCosPiTest_q <= shiftValFxPX_uid38_fpCosPiTest_o(8 downto 0);
--fxpShifterBits_uid40_fpCosPiTest(BITSELECT,39)@0
fxpShifterBits_uid40_fpCosPiTest_in <= shiftValFxPX_uid38_fpCosPiTest_q(5 downto 0);
fxpShifterBits_uid40_fpCosPiTest_b <= fxpShifterBits_uid40_fpCosPiTest_in(5 downto 0);
--leftShiftStageSel5Dto4_uid112_fxpX_uid41_fpCosPiTest(BITSELECT,111)@0
leftShiftStageSel5Dto4_uid112_fxpX_uid41_fpCosPiTest_in <= fxpShifterBits_uid40_fpCosPiTest_b;
leftShiftStageSel5Dto4_uid112_fxpX_uid41_fpCosPiTest_b <= leftShiftStageSel5Dto4_uid112_fxpX_uid41_fpCosPiTest_in(5 downto 4);
--leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest(MUX,112)@0
leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_s <= leftShiftStageSel5Dto4_uid112_fxpX_uid41_fpCosPiTest_b;
leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest: PROCESS (leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_s, en, oFracXExt_uid39_fpCosPiTest_q, leftShiftStage0Idx1_uid107_fxpX_uid41_fpCosPiTest_q, leftShiftStage0Idx2_uid110_fxpX_uid41_fpCosPiTest_q, leftShiftStage0Idx3_uid111_fxpX_uid41_fpCosPiTest_q)
BEGIN
CASE leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_s IS
WHEN "00" => leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_q <= oFracXExt_uid39_fpCosPiTest_q;
WHEN "01" => leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_q <= leftShiftStage0Idx1_uid107_fxpX_uid41_fpCosPiTest_q;
WHEN "10" => leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_q <= leftShiftStage0Idx2_uid110_fxpX_uid41_fpCosPiTest_q;
WHEN "11" => leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_q <= leftShiftStage0Idx3_uid111_fxpX_uid41_fpCosPiTest_q;
WHEN OTHERS => leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage024dto0_uid121_fxpX_uid41_fpCosPiTest(BITSELECT,120)@0
LeftShiftStage024dto0_uid121_fxpX_uid41_fpCosPiTest_in <= leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_q(24 downto 0);
LeftShiftStage024dto0_uid121_fxpX_uid41_fpCosPiTest_b <= LeftShiftStage024dto0_uid121_fxpX_uid41_fpCosPiTest_in(24 downto 0);
--leftShiftStage1Idx3Pad12_uid120_fxpX_uid41_fpCosPiTest(CONSTANT,119)
leftShiftStage1Idx3Pad12_uid120_fxpX_uid41_fpCosPiTest_q <= "000000000000";
--leftShiftStage1Idx3_uid122_fxpX_uid41_fpCosPiTest(BITJOIN,121)@0
leftShiftStage1Idx3_uid122_fxpX_uid41_fpCosPiTest_q <= LeftShiftStage024dto0_uid121_fxpX_uid41_fpCosPiTest_b & leftShiftStage1Idx3Pad12_uid120_fxpX_uid41_fpCosPiTest_q;
--reg_leftShiftStage1Idx3_uid122_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_5(REG,235)@0
reg_leftShiftStage1Idx3_uid122_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx3_uid122_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_5_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx3_uid122_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_5_q <= leftShiftStage1Idx3_uid122_fxpX_uid41_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage028dto0_uid118_fxpX_uid41_fpCosPiTest(BITSELECT,117)@0
LeftShiftStage028dto0_uid118_fxpX_uid41_fpCosPiTest_in <= leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_q(28 downto 0);
LeftShiftStage028dto0_uid118_fxpX_uid41_fpCosPiTest_b <= LeftShiftStage028dto0_uid118_fxpX_uid41_fpCosPiTest_in(28 downto 0);
--cstAllZWE_uid21_fpCosPiTest(CONSTANT,20)
cstAllZWE_uid21_fpCosPiTest_q <= "00000000";
--leftShiftStage1Idx2_uid119_fxpX_uid41_fpCosPiTest(BITJOIN,118)@0
leftShiftStage1Idx2_uid119_fxpX_uid41_fpCosPiTest_q <= LeftShiftStage028dto0_uid118_fxpX_uid41_fpCosPiTest_b & cstAllZWE_uid21_fpCosPiTest_q;
--reg_leftShiftStage1Idx2_uid119_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_4(REG,234)@0
reg_leftShiftStage1Idx2_uid119_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx2_uid119_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_4_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx2_uid119_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_4_q <= leftShiftStage1Idx2_uid119_fxpX_uid41_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage032dto0_uid115_fxpX_uid41_fpCosPiTest(BITSELECT,114)@0
LeftShiftStage032dto0_uid115_fxpX_uid41_fpCosPiTest_in <= leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_q(32 downto 0);
LeftShiftStage032dto0_uid115_fxpX_uid41_fpCosPiTest_b <= LeftShiftStage032dto0_uid115_fxpX_uid41_fpCosPiTest_in(32 downto 0);
--leftShiftStage1Idx1Pad4_uid114_fxpX_uid41_fpCosPiTest(CONSTANT,113)
leftShiftStage1Idx1Pad4_uid114_fxpX_uid41_fpCosPiTest_q <= "0000";
--leftShiftStage1Idx1_uid116_fxpX_uid41_fpCosPiTest(BITJOIN,115)@0
leftShiftStage1Idx1_uid116_fxpX_uid41_fpCosPiTest_q <= LeftShiftStage032dto0_uid115_fxpX_uid41_fpCosPiTest_b & leftShiftStage1Idx1Pad4_uid114_fxpX_uid41_fpCosPiTest_q;
--reg_leftShiftStage1Idx1_uid116_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_3(REG,233)@0
reg_leftShiftStage1Idx1_uid116_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx1_uid116_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_3_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx1_uid116_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_3_q <= leftShiftStage1Idx1_uid116_fxpX_uid41_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--reg_leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_2(REG,232)@0
reg_leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_2_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_2_q <= leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel3Dto2_uid123_fxpX_uid41_fpCosPiTest(BITSELECT,122)@0
leftShiftStageSel3Dto2_uid123_fxpX_uid41_fpCosPiTest_in <= fxpShifterBits_uid40_fpCosPiTest_b(3 downto 0);
leftShiftStageSel3Dto2_uid123_fxpX_uid41_fpCosPiTest_b <= leftShiftStageSel3Dto2_uid123_fxpX_uid41_fpCosPiTest_in(3 downto 2);
--reg_leftShiftStageSel3Dto2_uid123_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_1(REG,231)@0
reg_leftShiftStageSel3Dto2_uid123_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel3Dto2_uid123_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel3Dto2_uid123_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_1_q <= leftShiftStageSel3Dto2_uid123_fxpX_uid41_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest(MUX,123)@1
leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_s <= reg_leftShiftStageSel3Dto2_uid123_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_1_q;
leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest: PROCESS (leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_s, en, reg_leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_2_q, reg_leftShiftStage1Idx1_uid116_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_3_q, reg_leftShiftStage1Idx2_uid119_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_4_q, reg_leftShiftStage1Idx3_uid122_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_5_q)
BEGIN
CASE leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_s IS
WHEN "00" => leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_q <= reg_leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_2_q;
WHEN "01" => leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_q <= reg_leftShiftStage1Idx1_uid116_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_3_q;
WHEN "10" => leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_q <= reg_leftShiftStage1Idx2_uid119_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_4_q;
WHEN "11" => leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_q <= reg_leftShiftStage1Idx3_uid122_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_5_q;
WHEN OTHERS => leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--leftShiftStageSel1Dto0_uid134_fxpX_uid41_fpCosPiTest(BITSELECT,133)@0
leftShiftStageSel1Dto0_uid134_fxpX_uid41_fpCosPiTest_in <= fxpShifterBits_uid40_fpCosPiTest_b(1 downto 0);
leftShiftStageSel1Dto0_uid134_fxpX_uid41_fpCosPiTest_b <= leftShiftStageSel1Dto0_uid134_fxpX_uid41_fpCosPiTest_in(1 downto 0);
--reg_leftShiftStageSel1Dto0_uid134_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest_1(REG,236)@0
reg_leftShiftStageSel1Dto0_uid134_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel1Dto0_uid134_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel1Dto0_uid134_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest_1_q <= leftShiftStageSel1Dto0_uid134_fxpX_uid41_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest(MUX,134)@1
leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest_s <= reg_leftShiftStageSel1Dto0_uid134_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest_1_q;
leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest: PROCESS (leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest_s, en, leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_q, leftShiftStage2Idx1_uid127_fxpX_uid41_fpCosPiTest_q, leftShiftStage2Idx2_uid130_fxpX_uid41_fpCosPiTest_q, leftShiftStage2Idx3_uid133_fxpX_uid41_fpCosPiTest_q)
BEGIN
CASE leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest_s IS
WHEN "00" => leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest_q <= leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_q;
WHEN "01" => leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest_q <= leftShiftStage2Idx1_uid127_fxpX_uid41_fpCosPiTest_q;
WHEN "10" => leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest_q <= leftShiftStage2Idx2_uid130_fxpX_uid41_fpCosPiTest_q;
WHEN "11" => leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest_q <= leftShiftStage2Idx3_uid133_fxpX_uid41_fpCosPiTest_q;
WHEN OTHERS => leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--fxpXFrac_uid43_fpCosPiTest(BITSELECT,42)@1
fxpXFrac_uid43_fpCosPiTest_in <= leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest_q(35 downto 0);
fxpXFrac_uid43_fpCosPiTest_b <= fxpXFrac_uid43_fpCosPiTest_in(35 downto 0);
--FxpXFrac35_uid44_fpCosPiTest(BITSELECT,43)@1
FxpXFrac35_uid44_fpCosPiTest_in <= fxpXFrac_uid43_fpCosPiTest_b;
FxpXFrac35_uid44_fpCosPiTest_b <= FxpXFrac35_uid44_fpCosPiTest_in(35 downto 35);
--FxpX36_uid42_fpCosPiTest(BITSELECT,41)@1
FxpX36_uid42_fpCosPiTest_in <= leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest_q;
FxpX36_uid42_fpCosPiTest_b <= FxpX36_uid42_fpCosPiTest_in(36 downto 36);
--xParityXorHalfParity_uid96_fpCosPiTest(LOGICAL,95)@1
xParityXorHalfParity_uid96_fpCosPiTest_a <= FxpX36_uid42_fpCosPiTest_b;
xParityXorHalfParity_uid96_fpCosPiTest_b <= FxpXFrac35_uid44_fpCosPiTest_b;
xParityXorHalfParity_uid96_fpCosPiTest_q <= xParityXorHalfParity_uid96_fpCosPiTest_a xor xParityXorHalfParity_uid96_fpCosPiTest_b;
--ld_xParityXorHalfParity_uid96_fpCosPiTest_q_to_signRComp_uid99_fpCosPiTest_c(DELAY,369)@1
ld_xParityXorHalfParity_uid96_fpCosPiTest_q_to_signRComp_uid99_fpCosPiTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => xParityXorHalfParity_uid96_fpCosPiTest_q, xout => ld_xParityXorHalfParity_uid96_fpCosPiTest_q_to_signRComp_uid99_fpCosPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--cstBiasPwF_uid12_fpCosPiTest(CONSTANT,11)
cstBiasPwF_uid12_fpCosPiTest_q <= "10010110";
--xEvenInt_uid35_fpCosPiTest(COMPARE,34)@0
xEvenInt_uid35_fpCosPiTest_cin <= GND_q;
xEvenInt_uid35_fpCosPiTest_a <= STD_LOGIC_VECTOR("00" & cstBiasPwF_uid12_fpCosPiTest_q) & '0';
xEvenInt_uid35_fpCosPiTest_b <= STD_LOGIC_VECTOR("00" & expX_uid6_fpCosPiTest_b) & xEvenInt_uid35_fpCosPiTest_cin(0);
xEvenInt_uid35_fpCosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(xEvenInt_uid35_fpCosPiTest_a) - UNSIGNED(xEvenInt_uid35_fpCosPiTest_b));
xEvenInt_uid35_fpCosPiTest_c(0) <= xEvenInt_uid35_fpCosPiTest_o(10);
--ld_xEvenInt_uid35_fpCosPiTest_c_to_evenIntCosNotOneFZ_uid79_fpCosPiTest_a(DELAY,335)@0
ld_xEvenInt_uid35_fpCosPiTest_c_to_evenIntCosNotOneFZ_uid79_fpCosPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => xEvenInt_uid35_fpCosPiTest_c, xout => ld_xEvenInt_uid35_fpCosPiTest_c_to_evenIntCosNotOneFZ_uid79_fpCosPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--InvXEvenInt_uid81_fpCosPiTest(LOGICAL,80)@2
InvXEvenInt_uid81_fpCosPiTest_a <= ld_xEvenInt_uid35_fpCosPiTest_c_to_evenIntCosNotOneFZ_uid79_fpCosPiTest_a_q;
InvXEvenInt_uid81_fpCosPiTest_q <= not InvXEvenInt_uid81_fpCosPiTest_a;
--cosXIsOne_uid36_fpCosPiTest(COMPARE,35)@0
cosXIsOne_uid36_fpCosPiTest_cin <= GND_q;
cosXIsOne_uid36_fpCosPiTest_a <= STD_LOGIC_VECTOR("00" & expX_uid6_fpCosPiTest_b) & '0';
cosXIsOne_uid36_fpCosPiTest_b <= STD_LOGIC_VECTOR("00" & biasMwShiftMO_uid13_fpCosPiTest_q) & cosXIsOne_uid36_fpCosPiTest_cin(0);
cosXIsOne_uid36_fpCosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(cosXIsOne_uid36_fpCosPiTest_a) - UNSIGNED(cosXIsOne_uid36_fpCosPiTest_b));
cosXIsOne_uid36_fpCosPiTest_c(0) <= cosXIsOne_uid36_fpCosPiTest_o(10);
--ld_cosXIsOne_uid36_fpCosPiTest_c_to_InvCosXIsOne_uid77_fpCosPiTest_a(DELAY,332)@0
ld_cosXIsOne_uid36_fpCosPiTest_c_to_InvCosXIsOne_uid77_fpCosPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => cosXIsOne_uid36_fpCosPiTest_c, xout => ld_cosXIsOne_uid36_fpCosPiTest_c_to_InvCosXIsOne_uid77_fpCosPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--InvCosXIsOne_uid77_fpCosPiTest(LOGICAL,76)@2
InvCosXIsOne_uid77_fpCosPiTest_a <= ld_cosXIsOne_uid36_fpCosPiTest_c_to_InvCosXIsOne_uid77_fpCosPiTest_a_q;
InvCosXIsOne_uid77_fpCosPiTest_q <= not InvCosXIsOne_uid77_fpCosPiTest_a;
--signRComp_uid99_fpCosPiTest(LOGICAL,98)@2
signRComp_uid99_fpCosPiTest_a <= InvCosXIsOne_uid77_fpCosPiTest_q;
signRComp_uid99_fpCosPiTest_b <= InvXEvenInt_uid81_fpCosPiTest_q;
signRComp_uid99_fpCosPiTest_c <= ld_xParityXorHalfParity_uid96_fpCosPiTest_q_to_signRComp_uid99_fpCosPiTest_c_q;
signRComp_uid99_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
signRComp_uid99_fpCosPiTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1' AND en = "1") THEN
signRComp_uid99_fpCosPiTest_q <= signRComp_uid99_fpCosPiTest_a and signRComp_uid99_fpCosPiTest_b and signRComp_uid99_fpCosPiTest_c;
END IF;
END PROCESS;
--cstZwSwF_uid15_fpCosPiTest(CONSTANT,14)
cstZwSwF_uid15_fpCosPiTest_q <= "00000000000000000000000000000000000";
--cstHalfwSwFP1_uid18_fpCosPiTest(BITJOIN,17)@2
cstHalfwSwFP1_uid18_fpCosPiTest_q <= VCC_q & cstZwSwF_uid15_fpCosPiTest_q;
--reg_fxpXFrac_uid43_fpCosPiTest_0_to_fxpXFracZero_uid45_fpCosPiTest_1(REG,237)@1
reg_fxpXFrac_uid43_fpCosPiTest_0_to_fxpXFracZero_uid45_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fxpXFrac_uid43_fpCosPiTest_0_to_fxpXFracZero_uid45_fpCosPiTest_1_q <= "000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fxpXFrac_uid43_fpCosPiTest_0_to_fxpXFracZero_uid45_fpCosPiTest_1_q <= fxpXFrac_uid43_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--fxpXFracHalf_uid46_fpCosPiTest(LOGICAL,45)@2
fxpXFracHalf_uid46_fpCosPiTest_a <= reg_fxpXFrac_uid43_fpCosPiTest_0_to_fxpXFracZero_uid45_fpCosPiTest_1_q;
fxpXFracHalf_uid46_fpCosPiTest_b <= cstHalfwSwFP1_uid18_fpCosPiTest_q;
fxpXFracHalf_uid46_fpCosPiTest_q <= "1" when fxpXFracHalf_uid46_fpCosPiTest_a = fxpXFracHalf_uid46_fpCosPiTest_b else "0";
--ld_fxpXFracHalf_uid46_fpCosPiTest_q_to_InvFxpXFracHalf_uid100_fpCosPiTest_a(DELAY,370)@2
ld_fxpXFracHalf_uid46_fpCosPiTest_q_to_InvFxpXFracHalf_uid100_fpCosPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => fxpXFracHalf_uid46_fpCosPiTest_q, xout => ld_fxpXFracHalf_uid46_fpCosPiTest_q_to_InvFxpXFracHalf_uid100_fpCosPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--InvFxpXFracHalf_uid100_fpCosPiTest(LOGICAL,99)@3
InvFxpXFracHalf_uid100_fpCosPiTest_a <= ld_fxpXFracHalf_uid46_fpCosPiTest_q_to_InvFxpXFracHalf_uid100_fpCosPiTest_a_q;
InvFxpXFracHalf_uid100_fpCosPiTest_q <= not InvFxpXFracHalf_uid100_fpCosPiTest_a;
--signR_uid101_fpCosPiTest(LOGICAL,100)@3
signR_uid101_fpCosPiTest_a <= InvFxpXFracHalf_uid100_fpCosPiTest_q;
signR_uid101_fpCosPiTest_b <= signRComp_uid99_fpCosPiTest_q;
signR_uid101_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
signR_uid101_fpCosPiTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1' AND en = "1") THEN
signR_uid101_fpCosPiTest_q <= signR_uid101_fpCosPiTest_a and signR_uid101_fpCosPiTest_b;
END IF;
END PROCESS;
--ld_signR_uid101_fpCosPiTest_q_to_R_uid102_fpCosPiTest_c(DELAY,375)@4
ld_signR_uid101_fpCosPiTest_q_to_R_uid102_fpCosPiTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 13 )
PORT MAP ( xin => signR_uid101_fpCosPiTest_q, xout => ld_signR_uid101_fpCosPiTest_q_to_R_uid102_fpCosPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--cstBias_uid10_fpCosPiTest(CONSTANT,9)
cstBias_uid10_fpCosPiTest_q <= "01111111";
--cstAllOWE_uid8_fpCosPiTest(CONSTANT,7)
cstAllOWE_uid8_fpCosPiTest_q <= "11111111";
--pad_o_uid16_uid47_fpCosPiTest(BITJOIN,46)@1
pad_o_uid16_uid47_fpCosPiTest_q <= VCC_q & STD_LOGIC_VECTOR((35 downto 1 => GND_q(0)) & GND_q);
--reg_pad_o_uid16_uid47_fpCosPiTest_0_to_oMFxpXFrac_uid47_fpCosPiTest_0(REG,244)@1
reg_pad_o_uid16_uid47_fpCosPiTest_0_to_oMFxpXFrac_uid47_fpCosPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_o_uid16_uid47_fpCosPiTest_0_to_oMFxpXFrac_uid47_fpCosPiTest_0_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_o_uid16_uid47_fpCosPiTest_0_to_oMFxpXFrac_uid47_fpCosPiTest_0_q <= pad_o_uid16_uid47_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--oMFxpXFrac_uid47_fpCosPiTest(SUB,47)@2
oMFxpXFrac_uid47_fpCosPiTest_a <= STD_LOGIC_VECTOR("0" & reg_pad_o_uid16_uid47_fpCosPiTest_0_to_oMFxpXFrac_uid47_fpCosPiTest_0_q);
oMFxpXFrac_uid47_fpCosPiTest_b <= STD_LOGIC_VECTOR("00" & reg_fxpXFrac_uid43_fpCosPiTest_0_to_fxpXFracZero_uid45_fpCosPiTest_1_q);
oMFxpXFrac_uid47_fpCosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(oMFxpXFrac_uid47_fpCosPiTest_a) - UNSIGNED(oMFxpXFrac_uid47_fpCosPiTest_b));
oMFxpXFrac_uid47_fpCosPiTest_q <= oMFxpXFrac_uid47_fpCosPiTest_o(37 downto 0);
--oMFxpXFrac_uid49_fpCosPiTest(BITSELECT,48)@2
oMFxpXFrac_uid49_fpCosPiTest_in <= oMFxpXFrac_uid47_fpCosPiTest_q(35 downto 0);
oMFxpXFrac_uid49_fpCosPiTest_b <= oMFxpXFrac_uid49_fpCosPiTest_in(35 downto 0);
--ld_fxpXFrac_uid43_fpCosPiTest_b_to_rangeReducedFxPX_uid51_fpCosPiTest_c(DELAY,308)@1
ld_fxpXFrac_uid43_fpCosPiTest_b_to_rangeReducedFxPX_uid51_fpCosPiTest_c : dspba_delay
GENERIC MAP ( width => 36, depth => 1 )
PORT MAP ( xin => fxpXFrac_uid43_fpCosPiTest_b, xout => ld_fxpXFrac_uid43_fpCosPiTest_b_to_rangeReducedFxPX_uid51_fpCosPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--ld_FxpXFrac35_uid44_fpCosPiTest_b_to_rangeReducedFxPX_uid51_fpCosPiTest_b(DELAY,307)@1
ld_FxpXFrac35_uid44_fpCosPiTest_b_to_rangeReducedFxPX_uid51_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => FxpXFrac35_uid44_fpCosPiTest_b, xout => ld_FxpXFrac35_uid44_fpCosPiTest_b_to_rangeReducedFxPX_uid51_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--rangeReducedFxPX_uid51_fpCosPiTest(MUX,50)@2
rangeReducedFxPX_uid51_fpCosPiTest_s <= ld_FxpXFrac35_uid44_fpCosPiTest_b_to_rangeReducedFxPX_uid51_fpCosPiTest_b_q;
rangeReducedFxPX_uid51_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
rangeReducedFxPX_uid51_fpCosPiTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE rangeReducedFxPX_uid51_fpCosPiTest_s IS
WHEN "0" => rangeReducedFxPX_uid51_fpCosPiTest_q <= ld_fxpXFrac_uid43_fpCosPiTest_b_to_rangeReducedFxPX_uid51_fpCosPiTest_c_q;
WHEN "1" => rangeReducedFxPX_uid51_fpCosPiTest_q <= oMFxpXFrac_uid49_fpCosPiTest_b;
WHEN OTHERS => rangeReducedFxPX_uid51_fpCosPiTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--pad_half_uid17_uid52_fpCosPiTest(BITJOIN,51)@2
pad_half_uid17_uid52_fpCosPiTest_q <= VCC_q & STD_LOGIC_VECTOR((34 downto 1 => GND_q(0)) & GND_q);
--reg_pad_half_uid17_uid52_fpCosPiTest_0_to_z_halfMRRFxPXE_uid52_fpCosPiTest_0(REG,246)@2
reg_pad_half_uid17_uid52_fpCosPiTest_0_to_z_halfMRRFxPXE_uid52_fpCosPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_half_uid17_uid52_fpCosPiTest_0_to_z_halfMRRFxPXE_uid52_fpCosPiTest_0_q <= "000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_half_uid17_uid52_fpCosPiTest_0_to_z_halfMRRFxPXE_uid52_fpCosPiTest_0_q <= pad_half_uid17_uid52_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--z_halfMRRFxPXE_uid52_fpCosPiTest(SUB,52)@3
z_halfMRRFxPXE_uid52_fpCosPiTest_a <= STD_LOGIC_VECTOR("0" & reg_pad_half_uid17_uid52_fpCosPiTest_0_to_z_halfMRRFxPXE_uid52_fpCosPiTest_0_q);
z_halfMRRFxPXE_uid52_fpCosPiTest_b <= STD_LOGIC_VECTOR("0" & rangeReducedFxPX_uid51_fpCosPiTest_q);
z_halfMRRFxPXE_uid52_fpCosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(z_halfMRRFxPXE_uid52_fpCosPiTest_a) - UNSIGNED(z_halfMRRFxPXE_uid52_fpCosPiTest_b));
z_halfMRRFxPXE_uid52_fpCosPiTest_q <= z_halfMRRFxPXE_uid52_fpCosPiTest_o(36 downto 0);
--z_uid54_fpCosPiTest(BITSELECT,53)@3
z_uid54_fpCosPiTest_in <= z_halfMRRFxPXE_uid52_fpCosPiTest_q(34 downto 0);
z_uid54_fpCosPiTest_b <= z_uid54_fpCosPiTest_in(34 downto 0);
--zAddr_uid62_fpCosPiTest(BITSELECT,61)@3
zAddr_uid62_fpCosPiTest_in <= z_uid54_fpCosPiTest_b;
zAddr_uid62_fpCosPiTest_b <= zAddr_uid62_fpCosPiTest_in(34 downto 28);
--reg_zAddr_uid62_fpCosPiTest_0_to_memoryC2_uid209_sinPiZTableGenerator_0(REG,263)@3
reg_zAddr_uid62_fpCosPiTest_0_to_memoryC2_uid209_sinPiZTableGenerator_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_zAddr_uid62_fpCosPiTest_0_to_memoryC2_uid209_sinPiZTableGenerator_0_q <= "0000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_zAddr_uid62_fpCosPiTest_0_to_memoryC2_uid209_sinPiZTableGenerator_0_q <= zAddr_uid62_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--memoryC2_uid209_sinPiZTableGenerator(LOOKUP,208)@4
memoryC2_uid209_sinPiZTableGenerator: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
memoryC2_uid209_sinPiZTableGenerator_q <= "10101101010011";
ELSIF (clk'EVENT AND clk = '1' AND en = "1") THEN
CASE (reg_zAddr_uid62_fpCosPiTest_0_to_memoryC2_uid209_sinPiZTableGenerator_0_q) IS
WHEN "0000000" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101101010011";
WHEN "0000001" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101101010100";
WHEN "0000010" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101101010111";
WHEN "0000011" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101101011001";
WHEN "0000100" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101101011011";
WHEN "0000101" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101101011100";
WHEN "0000110" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101101011111";
WHEN "0000111" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101101100010";
WHEN "0001000" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101101100110";
WHEN "0001001" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101101101011";
WHEN "0001010" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101101110000";
WHEN "0001011" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101101110101";
WHEN "0001100" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101101111011";
WHEN "0001101" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101110000000";
WHEN "0001110" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101110000111";
WHEN "0001111" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101110001110";
WHEN "0010000" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101110010011";
WHEN "0010001" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101110011110";
WHEN "0010010" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101110100110";
WHEN "0010011" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101110101111";
WHEN "0010100" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101110111000";
WHEN "0010101" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101111000011";
WHEN "0010110" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101111001100";
WHEN "0010111" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101111010111";
WHEN "0011000" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101111100011";
WHEN "0011001" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101111101110";
WHEN "0011010" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101111111011";
WHEN "0011011" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110000001001";
WHEN "0011100" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110000010101";
WHEN "0011101" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110000100000";
WHEN "0011110" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110000110001";
WHEN "0011111" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110001000000";
WHEN "0100000" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110001001101";
WHEN "0100001" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110001011110";
WHEN "0100010" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110001101100";
WHEN "0100011" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110001111111";
WHEN "0100100" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110010001111";
WHEN "0100101" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110010100001";
WHEN "0100110" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110010110011";
WHEN "0100111" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110011000101";
WHEN "0101000" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110011010110";
WHEN "0101001" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110011101011";
WHEN "0101010" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110011111111";
WHEN "0101011" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110100010010";
WHEN "0101100" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110100100101";
WHEN "0101101" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110100111011";
WHEN "0101110" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110101001110";
WHEN "0101111" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110101100111";
WHEN "0110000" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110101111100";
WHEN "0110001" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110110010010";
WHEN "0110010" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110110100110";
WHEN "0110011" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110111000000";
WHEN "0110100" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110111010101";
WHEN "0110101" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110111110000";
WHEN "0110110" => memoryC2_uid209_sinPiZTableGenerator_q <= "10111000000110";
WHEN "0110111" => memoryC2_uid209_sinPiZTableGenerator_q <= "10111000100010";
WHEN "0111000" => memoryC2_uid209_sinPiZTableGenerator_q <= "10111000111001";
WHEN "0111001" => memoryC2_uid209_sinPiZTableGenerator_q <= "10111001010100";
WHEN "0111010" => memoryC2_uid209_sinPiZTableGenerator_q <= "10111001101111";
WHEN "0111011" => memoryC2_uid209_sinPiZTableGenerator_q <= "10111010001001";
WHEN "0111100" => memoryC2_uid209_sinPiZTableGenerator_q <= "10111010100011";
WHEN "0111101" => memoryC2_uid209_sinPiZTableGenerator_q <= "10111010111100";
WHEN "0111110" => memoryC2_uid209_sinPiZTableGenerator_q <= "10111011011001";
WHEN "0111111" => memoryC2_uid209_sinPiZTableGenerator_q <= "10111011110111";
WHEN "1000000" => memoryC2_uid209_sinPiZTableGenerator_q <= "10111100010100";
WHEN "1000001" => memoryC2_uid209_sinPiZTableGenerator_q <= "10111100110001";
WHEN "1000010" => memoryC2_uid209_sinPiZTableGenerator_q <= "10111101001101";
WHEN "1000011" => memoryC2_uid209_sinPiZTableGenerator_q <= "10111101101010";
WHEN "1000100" => memoryC2_uid209_sinPiZTableGenerator_q <= "10111110001000";
WHEN "1000101" => memoryC2_uid209_sinPiZTableGenerator_q <= "10111110100101";
WHEN "1000110" => memoryC2_uid209_sinPiZTableGenerator_q <= "10111111000101";
WHEN "1000111" => memoryC2_uid209_sinPiZTableGenerator_q <= "10111111100011";
WHEN "1001000" => memoryC2_uid209_sinPiZTableGenerator_q <= "11000000000011";
WHEN "1001001" => memoryC2_uid209_sinPiZTableGenerator_q <= "11000000100011";
WHEN "1001010" => memoryC2_uid209_sinPiZTableGenerator_q <= "11000001000100";
WHEN "1001011" => memoryC2_uid209_sinPiZTableGenerator_q <= "11000001100010";
WHEN "1001100" => memoryC2_uid209_sinPiZTableGenerator_q <= "11000010000100";
WHEN "1001101" => memoryC2_uid209_sinPiZTableGenerator_q <= "11000010100010";
WHEN "1001110" => memoryC2_uid209_sinPiZTableGenerator_q <= "11000011000110";
WHEN "1001111" => memoryC2_uid209_sinPiZTableGenerator_q <= "11000011101000";
WHEN "1010000" => memoryC2_uid209_sinPiZTableGenerator_q <= "11000100001010";
WHEN "1010001" => memoryC2_uid209_sinPiZTableGenerator_q <= "11000100101101";
WHEN "1010010" => memoryC2_uid209_sinPiZTableGenerator_q <= "11000101010001";
WHEN "1010011" => memoryC2_uid209_sinPiZTableGenerator_q <= "11000101110010";
WHEN "1010100" => memoryC2_uid209_sinPiZTableGenerator_q <= "11000110010100";
WHEN "1010101" => memoryC2_uid209_sinPiZTableGenerator_q <= "11000110111011";
WHEN "1010110" => memoryC2_uid209_sinPiZTableGenerator_q <= "11000111011010";
WHEN "1010111" => memoryC2_uid209_sinPiZTableGenerator_q <= "11001000000001";
WHEN "1011000" => memoryC2_uid209_sinPiZTableGenerator_q <= "11001000100110";
WHEN "1011001" => memoryC2_uid209_sinPiZTableGenerator_q <= "11001001001011";
WHEN "1011010" => memoryC2_uid209_sinPiZTableGenerator_q <= "11001001101101";
WHEN "1011011" => memoryC2_uid209_sinPiZTableGenerator_q <= "11001010010101";
WHEN "1011100" => memoryC2_uid209_sinPiZTableGenerator_q <= "11001010111100";
WHEN "1011101" => memoryC2_uid209_sinPiZTableGenerator_q <= "11001011100000";
WHEN "1011110" => memoryC2_uid209_sinPiZTableGenerator_q <= "11001100000101";
WHEN "1011111" => memoryC2_uid209_sinPiZTableGenerator_q <= "11001100101110";
WHEN "1100000" => memoryC2_uid209_sinPiZTableGenerator_q <= "11001101010100";
WHEN "1100001" => memoryC2_uid209_sinPiZTableGenerator_q <= "11001101111010";
WHEN "1100010" => memoryC2_uid209_sinPiZTableGenerator_q <= "11001110100010";
WHEN "1100011" => memoryC2_uid209_sinPiZTableGenerator_q <= "11001111001001";
WHEN "1100100" => memoryC2_uid209_sinPiZTableGenerator_q <= "11001111110001";
WHEN "1100101" => memoryC2_uid209_sinPiZTableGenerator_q <= "11010000010110";
WHEN "1100110" => memoryC2_uid209_sinPiZTableGenerator_q <= "11010000111111";
WHEN "1100111" => memoryC2_uid209_sinPiZTableGenerator_q <= "11010001101001";
WHEN "1101000" => memoryC2_uid209_sinPiZTableGenerator_q <= "11010010010010";
WHEN "1101001" => memoryC2_uid209_sinPiZTableGenerator_q <= "11010010111101";
WHEN "1101010" => memoryC2_uid209_sinPiZTableGenerator_q <= "11010011100001";
WHEN "1101011" => memoryC2_uid209_sinPiZTableGenerator_q <= "11010100001100";
WHEN "1101100" => memoryC2_uid209_sinPiZTableGenerator_q <= "11010100110111";
WHEN "1101101" => memoryC2_uid209_sinPiZTableGenerator_q <= "11010101100001";
WHEN "1101110" => memoryC2_uid209_sinPiZTableGenerator_q <= "11010110001011";
WHEN "1101111" => memoryC2_uid209_sinPiZTableGenerator_q <= "11010110110011";
WHEN "1110000" => memoryC2_uid209_sinPiZTableGenerator_q <= "11010111011111";
WHEN "1110001" => memoryC2_uid209_sinPiZTableGenerator_q <= "11011000001010";
WHEN "1110010" => memoryC2_uid209_sinPiZTableGenerator_q <= "11011000110100";
WHEN "1110011" => memoryC2_uid209_sinPiZTableGenerator_q <= "11011001011111";
WHEN "1110100" => memoryC2_uid209_sinPiZTableGenerator_q <= "11011010001010";
WHEN "1110101" => memoryC2_uid209_sinPiZTableGenerator_q <= "11011010110110";
WHEN "1110110" => memoryC2_uid209_sinPiZTableGenerator_q <= "11011011100011";
WHEN "1110111" => memoryC2_uid209_sinPiZTableGenerator_q <= "11011100001111";
WHEN "1111000" => memoryC2_uid209_sinPiZTableGenerator_q <= "11011100111001";
WHEN "1111001" => memoryC2_uid209_sinPiZTableGenerator_q <= "11011101100011";
WHEN "1111010" => memoryC2_uid209_sinPiZTableGenerator_q <= "11011110010001";
WHEN "1111011" => memoryC2_uid209_sinPiZTableGenerator_q <= "11011110111011";
WHEN "1111100" => memoryC2_uid209_sinPiZTableGenerator_q <= "11011111101000";
WHEN "1111101" => memoryC2_uid209_sinPiZTableGenerator_q <= "11100000010101";
WHEN "1111110" => memoryC2_uid209_sinPiZTableGenerator_q <= "11100001000010";
WHEN "1111111" => memoryC2_uid209_sinPiZTableGenerator_q <= "11100001110000";
WHEN OTHERS =>
memoryC2_uid209_sinPiZTableGenerator_q <= (others => '-');
END CASE;
END IF;
END PROCESS;
--zPPolyEval_uid63_fpCosPiTest(BITSELECT,62)@3
zPPolyEval_uid63_fpCosPiTest_in <= z_uid54_fpCosPiTest_b(27 downto 0);
zPPolyEval_uid63_fpCosPiTest_b <= zPPolyEval_uid63_fpCosPiTest_in(27 downto 12);
--yT1_uid210_sinPiZPolyEval(BITSELECT,209)@3
yT1_uid210_sinPiZPolyEval_in <= zPPolyEval_uid63_fpCosPiTest_b;
yT1_uid210_sinPiZPolyEval_b <= yT1_uid210_sinPiZPolyEval_in(15 downto 2);
--reg_yT1_uid210_sinPiZPolyEval_0_to_prodXY_uid226_pT1_uid211_sinPiZPolyEval_0(REG,264)@3
reg_yT1_uid210_sinPiZPolyEval_0_to_prodXY_uid226_pT1_uid211_sinPiZPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT1_uid210_sinPiZPolyEval_0_to_prodXY_uid226_pT1_uid211_sinPiZPolyEval_0_q <= "00000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT1_uid210_sinPiZPolyEval_0_to_prodXY_uid226_pT1_uid211_sinPiZPolyEval_0_q <= yT1_uid210_sinPiZPolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_reg_yT1_uid210_sinPiZPolyEval_0_to_prodXY_uid226_pT1_uid211_sinPiZPolyEval_0_q_to_prodXY_uid226_pT1_uid211_sinPiZPolyEval_a(DELAY,499)@4
ld_reg_yT1_uid210_sinPiZPolyEval_0_to_prodXY_uid226_pT1_uid211_sinPiZPolyEval_0_q_to_prodXY_uid226_pT1_uid211_sinPiZPolyEval_a : dspba_delay
GENERIC MAP ( width => 14, depth => 1 )
PORT MAP ( xin => reg_yT1_uid210_sinPiZPolyEval_0_to_prodXY_uid226_pT1_uid211_sinPiZPolyEval_0_q, xout => ld_reg_yT1_uid210_sinPiZPolyEval_0_to_prodXY_uid226_pT1_uid211_sinPiZPolyEval_0_q_to_prodXY_uid226_pT1_uid211_sinPiZPolyEval_a_q, ena => en(0), clk => clk, aclr => areset );
--prodXY_uid226_pT1_uid211_sinPiZPolyEval(MULT,225)@5
prodXY_uid226_pT1_uid211_sinPiZPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid226_pT1_uid211_sinPiZPolyEval_a),15)) * SIGNED(prodXY_uid226_pT1_uid211_sinPiZPolyEval_b);
prodXY_uid226_pT1_uid211_sinPiZPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid226_pT1_uid211_sinPiZPolyEval_a <= (others => '0');
prodXY_uid226_pT1_uid211_sinPiZPolyEval_b <= (others => '0');
prodXY_uid226_pT1_uid211_sinPiZPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid226_pT1_uid211_sinPiZPolyEval_a <= ld_reg_yT1_uid210_sinPiZPolyEval_0_to_prodXY_uid226_pT1_uid211_sinPiZPolyEval_0_q_to_prodXY_uid226_pT1_uid211_sinPiZPolyEval_a_q;
prodXY_uid226_pT1_uid211_sinPiZPolyEval_b <= memoryC2_uid209_sinPiZTableGenerator_q;
prodXY_uid226_pT1_uid211_sinPiZPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid226_pT1_uid211_sinPiZPolyEval_pr,28));
END IF;
END IF;
END PROCESS;
prodXY_uid226_pT1_uid211_sinPiZPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid226_pT1_uid211_sinPiZPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid226_pT1_uid211_sinPiZPolyEval_q <= prodXY_uid226_pT1_uid211_sinPiZPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid227_pT1_uid211_sinPiZPolyEval(BITSELECT,226)@8
prodXYTruncFR_uid227_pT1_uid211_sinPiZPolyEval_in <= prodXY_uid226_pT1_uid211_sinPiZPolyEval_q;
prodXYTruncFR_uid227_pT1_uid211_sinPiZPolyEval_b <= prodXYTruncFR_uid227_pT1_uid211_sinPiZPolyEval_in(27 downto 13);
--highBBits_uid213_sinPiZPolyEval(BITSELECT,212)@8
highBBits_uid213_sinPiZPolyEval_in <= prodXYTruncFR_uid227_pT1_uid211_sinPiZPolyEval_b;
highBBits_uid213_sinPiZPolyEval_b <= highBBits_uid213_sinPiZPolyEval_in(14 downto 1);
--ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_notEnable(LOGICAL,557)
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_notEnable_a <= en;
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_notEnable_q <= not ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_notEnable_a;
--ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_nor(LOGICAL,596)
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_nor_a <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_notEnable_q;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_nor_b <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_sticky_ena_q;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_nor_q <= not (ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_nor_a or ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_nor_b);
--ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_mem_top(CONSTANT,592)
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_mem_top_q <= "010";
--ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_cmp(LOGICAL,593)
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_cmp_a <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_mem_top_q;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdmux_q);
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_cmp_q <= "1" when ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_cmp_a = ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_cmp_b else "0";
--ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_cmpReg(REG,594)
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_cmpReg_q <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_sticky_ena(REG,597)
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_nor_q = "1") THEN
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_sticky_ena_q <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_enaAnd(LOGICAL,598)
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_enaAnd_a <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_sticky_ena_q;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_enaAnd_b <= en;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_enaAnd_q <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_enaAnd_a and ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_enaAnd_b;
--ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt(COUNTER,588)
-- every=1, low=0, high=2, step=1, init=1
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt_i <= TO_UNSIGNED(1,2);
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt_i = 1 THEN
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt_eq = '1') THEN
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt_i <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt_i - 2;
ELSE
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt_i <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt_i,2));
--ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdreg(REG,589)
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdreg_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdreg_q <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdmux(MUX,590)
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdmux_s <= en;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdmux: PROCESS (ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdmux_s, ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdreg_q, ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdmux_s IS
WHEN "0" => ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdmux_q <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdreg_q;
WHEN "1" => ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdmux_q <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem(DUALMEM,587)
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_reset0 <= areset;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_ia <= reg_zAddr_uid62_fpCosPiTest_0_to_memoryC2_uid209_sinPiZTableGenerator_0_q;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_aa <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdreg_q;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_ab <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdmux_q;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 7,
widthad_a => 2,
numwords_a => 3,
width_b => 7,
widthad_b => 2,
numwords_b => 3,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_iq,
address_a => ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_aa,
data_a => ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_ia
);
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_q <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_iq(6 downto 0);
--memoryC1_uid208_sinPiZTableGenerator(LOOKUP,207)@8
memoryC1_uid208_sinPiZTableGenerator: PROCESS (ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_q)
BEGIN
-- Begin reserved scope level
CASE (ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_q) IS
WHEN "0000000" => memoryC1_uid208_sinPiZTableGenerator_q <= "000000000000000000001";
WHEN "0000001" => memoryC1_uid208_sinPiZTableGenerator_q <= "111111101011010101010";
WHEN "0000010" => memoryC1_uid208_sinPiZTableGenerator_q <= "111111010110101010001";
WHEN "0000011" => memoryC1_uid208_sinPiZTableGenerator_q <= "111111000001111111100";
WHEN "0000100" => memoryC1_uid208_sinPiZTableGenerator_q <= "111110101101010101010";
WHEN "0000101" => memoryC1_uid208_sinPiZTableGenerator_q <= "111110011000101011101";
WHEN "0000110" => memoryC1_uid208_sinPiZTableGenerator_q <= "111110000100000010101";
WHEN "0000111" => memoryC1_uid208_sinPiZTableGenerator_q <= "111101101111011010001";
WHEN "0001000" => memoryC1_uid208_sinPiZTableGenerator_q <= "111101011010110010101";
WHEN "0001001" => memoryC1_uid208_sinPiZTableGenerator_q <= "111101000110001011111";
WHEN "0001010" => memoryC1_uid208_sinPiZTableGenerator_q <= "111100110001100110010";
WHEN "0001011" => memoryC1_uid208_sinPiZTableGenerator_q <= "111100011101000010000";
WHEN "0001100" => memoryC1_uid208_sinPiZTableGenerator_q <= "111100001000011110111";
WHEN "0001101" => memoryC1_uid208_sinPiZTableGenerator_q <= "111011110011111101011";
WHEN "0001110" => memoryC1_uid208_sinPiZTableGenerator_q <= "111011011111011101011";
WHEN "0001111" => memoryC1_uid208_sinPiZTableGenerator_q <= "111011001010111110111";
WHEN "0010000" => memoryC1_uid208_sinPiZTableGenerator_q <= "111010110110100010101";
WHEN "0010001" => memoryC1_uid208_sinPiZTableGenerator_q <= "111010100010000111100";
WHEN "0010010" => memoryC1_uid208_sinPiZTableGenerator_q <= "111010001101101111000";
WHEN "0010011" => memoryC1_uid208_sinPiZTableGenerator_q <= "111001111001011000011";
WHEN "0010100" => memoryC1_uid208_sinPiZTableGenerator_q <= "111001100101000100010";
WHEN "0010101" => memoryC1_uid208_sinPiZTableGenerator_q <= "111001010000110010001";
WHEN "0010110" => memoryC1_uid208_sinPiZTableGenerator_q <= "111000111100100010111";
WHEN "0010111" => memoryC1_uid208_sinPiZTableGenerator_q <= "111000101000010110001";
WHEN "0011000" => memoryC1_uid208_sinPiZTableGenerator_q <= "111000010100001011111";
WHEN "0011001" => memoryC1_uid208_sinPiZTableGenerator_q <= "111000000000000100110";
WHEN "0011010" => memoryC1_uid208_sinPiZTableGenerator_q <= "110111101100000000011";
WHEN "0011011" => memoryC1_uid208_sinPiZTableGenerator_q <= "110111010111111111000";
WHEN "0011100" => memoryC1_uid208_sinPiZTableGenerator_q <= "110111000100000001000";
WHEN "0011101" => memoryC1_uid208_sinPiZTableGenerator_q <= "110110110000000110101";
WHEN "0011110" => memoryC1_uid208_sinPiZTableGenerator_q <= "110110011100001110111";
WHEN "0011111" => memoryC1_uid208_sinPiZTableGenerator_q <= "110110001000011011000";
WHEN "0100000" => memoryC1_uid208_sinPiZTableGenerator_q <= "110101110100101011010";
WHEN "0100001" => memoryC1_uid208_sinPiZTableGenerator_q <= "110101100000111110101";
WHEN "0100010" => memoryC1_uid208_sinPiZTableGenerator_q <= "110101001101010110010";
WHEN "0100011" => memoryC1_uid208_sinPiZTableGenerator_q <= "110100111001110001011";
WHEN "0100100" => memoryC1_uid208_sinPiZTableGenerator_q <= "110100100110010001001";
WHEN "0100101" => memoryC1_uid208_sinPiZTableGenerator_q <= "110100010010110100110";
WHEN "0100110" => memoryC1_uid208_sinPiZTableGenerator_q <= "110011111111011100110";
WHEN "0100111" => memoryC1_uid208_sinPiZTableGenerator_q <= "110011101100001001010";
WHEN "0101000" => memoryC1_uid208_sinPiZTableGenerator_q <= "110011011000111010011";
WHEN "0101001" => memoryC1_uid208_sinPiZTableGenerator_q <= "110011000101101111111";
WHEN "0101010" => memoryC1_uid208_sinPiZTableGenerator_q <= "110010110010101010010";
WHEN "0101011" => memoryC1_uid208_sinPiZTableGenerator_q <= "110010011111101001101";
WHEN "0101100" => memoryC1_uid208_sinPiZTableGenerator_q <= "110010001100101110000";
WHEN "0101101" => memoryC1_uid208_sinPiZTableGenerator_q <= "110001111001110111001";
WHEN "0101110" => memoryC1_uid208_sinPiZTableGenerator_q <= "110001100111000110000";
WHEN "0101111" => memoryC1_uid208_sinPiZTableGenerator_q <= "110001010100011001011";
WHEN "0110000" => memoryC1_uid208_sinPiZTableGenerator_q <= "110001000001110010110";
WHEN "0110001" => memoryC1_uid208_sinPiZTableGenerator_q <= "110000101111010001100";
WHEN "0110010" => memoryC1_uid208_sinPiZTableGenerator_q <= "110000011100110110001";
WHEN "0110011" => memoryC1_uid208_sinPiZTableGenerator_q <= "110000001010011111111";
WHEN "0110100" => memoryC1_uid208_sinPiZTableGenerator_q <= "101111111000010000000";
WHEN "0110101" => memoryC1_uid208_sinPiZTableGenerator_q <= "101111100110000101100";
WHEN "0110110" => memoryC1_uid208_sinPiZTableGenerator_q <= "101111010100000001100";
WHEN "0110111" => memoryC1_uid208_sinPiZTableGenerator_q <= "101111000010000011001";
WHEN "0111000" => memoryC1_uid208_sinPiZTableGenerator_q <= "101110110000001011100";
WHEN "0111001" => memoryC1_uid208_sinPiZTableGenerator_q <= "101110011110011001110";
WHEN "0111010" => memoryC1_uid208_sinPiZTableGenerator_q <= "101110001100101110101";
WHEN "0111011" => memoryC1_uid208_sinPiZTableGenerator_q <= "101101111011001010001";
WHEN "0111100" => memoryC1_uid208_sinPiZTableGenerator_q <= "101101101001101100010";
WHEN "0111101" => memoryC1_uid208_sinPiZTableGenerator_q <= "101101011000010101010";
WHEN "0111110" => memoryC1_uid208_sinPiZTableGenerator_q <= "101101000111000100101";
WHEN "0111111" => memoryC1_uid208_sinPiZTableGenerator_q <= "101100110101111010111";
WHEN "1000000" => memoryC1_uid208_sinPiZTableGenerator_q <= "101100100100111000010";
WHEN "1000001" => memoryC1_uid208_sinPiZTableGenerator_q <= "101100010011111100111";
WHEN "1000010" => memoryC1_uid208_sinPiZTableGenerator_q <= "101100000011001000111";
WHEN "1000011" => memoryC1_uid208_sinPiZTableGenerator_q <= "101011110010011100000";
WHEN "1000100" => memoryC1_uid208_sinPiZTableGenerator_q <= "101011100001110110100";
WHEN "1000101" => memoryC1_uid208_sinPiZTableGenerator_q <= "101011010001011000100";
WHEN "1000110" => memoryC1_uid208_sinPiZTableGenerator_q <= "101011000001000001110";
WHEN "1000111" => memoryC1_uid208_sinPiZTableGenerator_q <= "101010110000110011000";
WHEN "1001000" => memoryC1_uid208_sinPiZTableGenerator_q <= "101010100000101011111";
WHEN "1001001" => memoryC1_uid208_sinPiZTableGenerator_q <= "101010010000101100100";
WHEN "1001010" => memoryC1_uid208_sinPiZTableGenerator_q <= "101010000000110101001";
WHEN "1001011" => memoryC1_uid208_sinPiZTableGenerator_q <= "101001110001000110000";
WHEN "1001100" => memoryC1_uid208_sinPiZTableGenerator_q <= "101001100001011110101";
WHEN "1001101" => memoryC1_uid208_sinPiZTableGenerator_q <= "101001010001111111111";
WHEN "1001110" => memoryC1_uid208_sinPiZTableGenerator_q <= "101001000010101000110";
WHEN "1001111" => memoryC1_uid208_sinPiZTableGenerator_q <= "101000110011011010001";
WHEN "1010000" => memoryC1_uid208_sinPiZTableGenerator_q <= "101000100100010100001";
WHEN "1010001" => memoryC1_uid208_sinPiZTableGenerator_q <= "101000010101010110100";
WHEN "1010010" => memoryC1_uid208_sinPiZTableGenerator_q <= "101000000110100001011";
WHEN "1010011" => memoryC1_uid208_sinPiZTableGenerator_q <= "100111110111110101011";
WHEN "1010100" => memoryC1_uid208_sinPiZTableGenerator_q <= "100111101001010010000";
WHEN "1010101" => memoryC1_uid208_sinPiZTableGenerator_q <= "100111011010110110110";
WHEN "1010110" => memoryC1_uid208_sinPiZTableGenerator_q <= "100111001100100101100";
WHEN "1010111" => memoryC1_uid208_sinPiZTableGenerator_q <= "100110111110011100011";
WHEN "1011000" => memoryC1_uid208_sinPiZTableGenerator_q <= "100110110000011100011";
WHEN "1011001" => memoryC1_uid208_sinPiZTableGenerator_q <= "100110100010100101110";
WHEN "1011010" => memoryC1_uid208_sinPiZTableGenerator_q <= "100110010100111000101";
WHEN "1011011" => memoryC1_uid208_sinPiZTableGenerator_q <= "100110000111010100001";
WHEN "1011100" => memoryC1_uid208_sinPiZTableGenerator_q <= "100101111001111001000";
WHEN "1011101" => memoryC1_uid208_sinPiZTableGenerator_q <= "100101101100100111111";
WHEN "1011110" => memoryC1_uid208_sinPiZTableGenerator_q <= "100101011111100000000";
WHEN "1011111" => memoryC1_uid208_sinPiZTableGenerator_q <= "100101010010100001001";
WHEN "1100000" => memoryC1_uid208_sinPiZTableGenerator_q <= "100101000101101100011";
WHEN "1100001" => memoryC1_uid208_sinPiZTableGenerator_q <= "100100111001000001011";
WHEN "1100010" => memoryC1_uid208_sinPiZTableGenerator_q <= "100100101100011111111";
WHEN "1100011" => memoryC1_uid208_sinPiZTableGenerator_q <= "100100100000001000010";
WHEN "1100100" => memoryC1_uid208_sinPiZTableGenerator_q <= "100100010011111010101";
WHEN "1100101" => memoryC1_uid208_sinPiZTableGenerator_q <= "100100000111110111001";
WHEN "1100110" => memoryC1_uid208_sinPiZTableGenerator_q <= "100011111011111101010";
WHEN "1100111" => memoryC1_uid208_sinPiZTableGenerator_q <= "100011110000001101010";
WHEN "1101000" => memoryC1_uid208_sinPiZTableGenerator_q <= "100011100100100111101";
WHEN "1101001" => memoryC1_uid208_sinPiZTableGenerator_q <= "100011011001001011111";
WHEN "1101010" => memoryC1_uid208_sinPiZTableGenerator_q <= "100011001101111011010";
WHEN "1101011" => memoryC1_uid208_sinPiZTableGenerator_q <= "100011000010110100001";
WHEN "1101100" => memoryC1_uid208_sinPiZTableGenerator_q <= "100010110111110111010";
WHEN "1101101" => memoryC1_uid208_sinPiZTableGenerator_q <= "100010101101000101000";
WHEN "1101110" => memoryC1_uid208_sinPiZTableGenerator_q <= "100010100010011101001";
WHEN "1101111" => memoryC1_uid208_sinPiZTableGenerator_q <= "100010011000000000001";
WHEN "1110000" => memoryC1_uid208_sinPiZTableGenerator_q <= "100010001101101101010";
WHEN "1110001" => memoryC1_uid208_sinPiZTableGenerator_q <= "100010000011100100111";
WHEN "1110010" => memoryC1_uid208_sinPiZTableGenerator_q <= "100001111001100111100";
WHEN "1110011" => memoryC1_uid208_sinPiZTableGenerator_q <= "100001101111110100101";
WHEN "1110100" => memoryC1_uid208_sinPiZTableGenerator_q <= "100001100110001100100";
WHEN "1110101" => memoryC1_uid208_sinPiZTableGenerator_q <= "100001011100101111001";
WHEN "1110110" => memoryC1_uid208_sinPiZTableGenerator_q <= "100001010011011100011";
WHEN "1110111" => memoryC1_uid208_sinPiZTableGenerator_q <= "100001001010010100101";
WHEN "1111000" => memoryC1_uid208_sinPiZTableGenerator_q <= "100001000001011000000";
WHEN "1111001" => memoryC1_uid208_sinPiZTableGenerator_q <= "100000111000100110100";
WHEN "1111010" => memoryC1_uid208_sinPiZTableGenerator_q <= "100000101111111111100";
WHEN "1111011" => memoryC1_uid208_sinPiZTableGenerator_q <= "100000100111100011111";
WHEN "1111100" => memoryC1_uid208_sinPiZTableGenerator_q <= "100000011111010011000";
WHEN "1111101" => memoryC1_uid208_sinPiZTableGenerator_q <= "100000010111001101010";
WHEN "1111110" => memoryC1_uid208_sinPiZTableGenerator_q <= "100000001111010010101";
WHEN "1111111" => memoryC1_uid208_sinPiZTableGenerator_q <= "100000000111100011001";
WHEN OTHERS =>
memoryC1_uid208_sinPiZTableGenerator_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--sumAHighB_uid214_sinPiZPolyEval(ADD,213)@8
sumAHighB_uid214_sinPiZPolyEval_a <= STD_LOGIC_VECTOR((21 downto 21 => memoryC1_uid208_sinPiZTableGenerator_q(20)) & memoryC1_uid208_sinPiZTableGenerator_q);
sumAHighB_uid214_sinPiZPolyEval_b <= STD_LOGIC_VECTOR((21 downto 14 => highBBits_uid213_sinPiZPolyEval_b(13)) & highBBits_uid213_sinPiZPolyEval_b);
sumAHighB_uid214_sinPiZPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid214_sinPiZPolyEval_a) + SIGNED(sumAHighB_uid214_sinPiZPolyEval_b));
sumAHighB_uid214_sinPiZPolyEval_q <= sumAHighB_uid214_sinPiZPolyEval_o(21 downto 0);
--lowRangeB_uid212_sinPiZPolyEval(BITSELECT,211)@8
lowRangeB_uid212_sinPiZPolyEval_in <= prodXYTruncFR_uid227_pT1_uid211_sinPiZPolyEval_b(0 downto 0);
lowRangeB_uid212_sinPiZPolyEval_b <= lowRangeB_uid212_sinPiZPolyEval_in(0 downto 0);
--s1_uid212_uid215_sinPiZPolyEval(BITJOIN,214)@8
s1_uid212_uid215_sinPiZPolyEval_q <= sumAHighB_uid214_sinPiZPolyEval_q & lowRangeB_uid212_sinPiZPolyEval_b;
--reg_s1_uid212_uid215_sinPiZPolyEval_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_1(REG,267)@8
reg_s1_uid212_uid215_sinPiZPolyEval_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_s1_uid212_uid215_sinPiZPolyEval_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_1_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_s1_uid212_uid215_sinPiZPolyEval_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_1_q <= s1_uid212_uid215_sinPiZPolyEval_q;
END IF;
END IF;
END PROCESS;
--ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_nor(LOGICAL,609)
ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_nor_a <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_notEnable_q;
ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_nor_b <= ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_sticky_ena_q;
ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_nor_q <= not (ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_nor_a or ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_nor_b);
--ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_sticky_ena(REG,610)
ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_nor_q = "1") THEN
ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_sticky_ena_q <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_enaAnd(LOGICAL,611)
ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_enaAnd_a <= ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_sticky_ena_q;
ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_enaAnd_b <= en;
ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_enaAnd_q <= ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_enaAnd_a and ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_enaAnd_b;
--ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_inputreg(DELAY,599)
ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 16, depth => 1 )
PORT MAP ( xin => zPPolyEval_uid63_fpCosPiTest_b, xout => ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem(DUALMEM,600)
ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_reset0 <= areset;
ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_ia <= ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_inputreg_q;
ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_aa <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdreg_q;
ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_ab <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdmux_q;
ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 16,
widthad_a => 2,
numwords_a => 3,
width_b => 16,
widthad_b => 2,
numwords_b => 3,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_iq,
address_a => ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_aa,
data_a => ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_ia
);
ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_q <= ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_iq(15 downto 0);
--reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0(REG,266)@8
reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_q <= ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--prodXY_uid229_pT2_uid217_sinPiZPolyEval(MULT,228)@9
prodXY_uid229_pT2_uid217_sinPiZPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid229_pT2_uid217_sinPiZPolyEval_a),17)) * SIGNED(prodXY_uid229_pT2_uid217_sinPiZPolyEval_b);
prodXY_uid229_pT2_uid217_sinPiZPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid229_pT2_uid217_sinPiZPolyEval_a <= (others => '0');
prodXY_uid229_pT2_uid217_sinPiZPolyEval_b <= (others => '0');
prodXY_uid229_pT2_uid217_sinPiZPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid229_pT2_uid217_sinPiZPolyEval_a <= reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_q;
prodXY_uid229_pT2_uid217_sinPiZPolyEval_b <= reg_s1_uid212_uid215_sinPiZPolyEval_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_1_q;
prodXY_uid229_pT2_uid217_sinPiZPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid229_pT2_uid217_sinPiZPolyEval_pr,39));
END IF;
END IF;
END PROCESS;
prodXY_uid229_pT2_uid217_sinPiZPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid229_pT2_uid217_sinPiZPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid229_pT2_uid217_sinPiZPolyEval_q <= prodXY_uid229_pT2_uid217_sinPiZPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid230_pT2_uid217_sinPiZPolyEval(BITSELECT,229)@12
prodXYTruncFR_uid230_pT2_uid217_sinPiZPolyEval_in <= prodXY_uid229_pT2_uid217_sinPiZPolyEval_q;
prodXYTruncFR_uid230_pT2_uid217_sinPiZPolyEval_b <= prodXYTruncFR_uid230_pT2_uid217_sinPiZPolyEval_in(38 downto 15);
--highBBits_uid219_sinPiZPolyEval(BITSELECT,218)@12
highBBits_uid219_sinPiZPolyEval_in <= prodXYTruncFR_uid230_pT2_uid217_sinPiZPolyEval_b;
highBBits_uid219_sinPiZPolyEval_b <= highBBits_uid219_sinPiZPolyEval_in(23 downto 2);
--ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_nor(LOGICAL,584)
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_nor_a <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_notEnable_q;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_nor_b <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_sticky_ena_q;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_nor_q <= not (ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_nor_a or ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_nor_b);
--ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_mem_top(CONSTANT,554)
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_mem_top_q <= "0110";
--ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_cmp(LOGICAL,555)
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_cmp_a <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_mem_top_q;
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdmux_q);
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_cmp_q <= "1" when ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_cmp_a = ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_cmp_b else "0";
--ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_cmpReg(REG,556)
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_cmpReg_q <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_sticky_ena(REG,585)
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_nor_q = "1") THEN
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_sticky_ena_q <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_enaAnd(LOGICAL,586)
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_enaAnd_a <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_sticky_ena_q;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_enaAnd_b <= en;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_enaAnd_q <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_enaAnd_a and ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_enaAnd_b;
--ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt(COUNTER,550)
-- every=1, low=0, high=6, step=1, init=1
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt_i = 5 THEN
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt_eq <= '1';
ELSE
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt_eq = '1') THEN
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt_i <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt_i - 6;
ELSE
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt_i <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt_i,3));
--ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdreg(REG,551)
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdreg_q <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdmux(MUX,552)
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdmux_s <= en;
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdmux: PROCESS (ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdmux_s, ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdreg_q, ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt_q)
BEGIN
CASE ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdmux_s IS
WHEN "0" => ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdmux_q <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdreg_q;
WHEN "1" => ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdmux_q <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem(DUALMEM,575)
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_reset0 <= areset;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_ia <= reg_zAddr_uid62_fpCosPiTest_0_to_memoryC2_uid209_sinPiZTableGenerator_0_q;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_aa <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdreg_q;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_ab <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdmux_q;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 7,
widthad_a => 3,
numwords_a => 7,
width_b => 7,
widthad_b => 3,
numwords_b => 7,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_iq,
address_a => ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_aa,
data_a => ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_ia
);
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_q <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_iq(6 downto 0);
--memoryC0_uid207_sinPiZTableGenerator(LOOKUP,206)@12
memoryC0_uid207_sinPiZTableGenerator: PROCESS (ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_q)
BEGIN
-- Begin reserved scope level
CASE (ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_q) IS
WHEN "0000000" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100100100001111110110101110";
WHEN "0000001" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100100100001110100100000010";
WHEN "0000010" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100100100001010101100000000";
WHEN "0000011" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100100100000100001110101000";
WHEN "0000100" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100100011111011001011111101";
WHEN "0000101" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100100011101111100100000010";
WHEN "0000110" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100100011100001010110111011";
WHEN "0000111" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100100011010000100100101111";
WHEN "0001000" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100100010111101001101100010";
WHEN "0001001" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100100010100111010001011101";
WHEN "0001010" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100100010001110110000100111";
WHEN "0001011" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100100001110011101011001001";
WHEN "0001100" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100100001010110000001001110";
WHEN "0001101" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100100000110101110011000000";
WHEN "0001110" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100100000010011000000101011";
WHEN "0001111" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100011111101101101010011101";
WHEN "0010000" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100011111000101110000100010";
WHEN "0010001" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100011110011011010011001011";
WHEN "0010010" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100011101101110010010100101";
WHEN "0010011" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100011100111110101111000011";
WHEN "0010100" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100011100001100101000110101";
WHEN "0010101" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100011011011000000000001111";
WHEN "0010110" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100011010100000110101100011";
WHEN "0010111" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100011001100111001001000110";
WHEN "0011000" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100011000101010111011001110";
WHEN "0011001" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100010111101100001100010000";
WHEN "0011010" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100010110101010111100100100";
WHEN "0011011" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100010101100111001100100010";
WHEN "0011100" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100010100100000111100100011";
WHEN "0011101" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100010011011000001101000000";
WHEN "0011110" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100010010001100111110010110";
WHEN "0011111" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100010000111111010000111111";
WHEN "0100000" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100001111101111000101010111";
WHEN "0100001" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100001110011100011011111110";
WHEN "0100010" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100001101000111010101010001";
WHEN "0100011" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100001011101111110001110000";
WHEN "0100100" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100001010010101110001111010";
WHEN "0100101" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100001000111001010110010010";
WHEN "0100110" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100000111011010011111011001";
WHEN "0100111" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100000101111001001101110010";
WHEN "0101000" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100000100010101100010000001";
WHEN "0101001" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100000010101111011100101011";
WHEN "0101010" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100000001000110111110010101";
WHEN "0101011" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011111111011100000111100110";
WHEN "0101100" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011111101101110111001000101";
WHEN "0101101" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011111011111111010011011011";
WHEN "0101110" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011111010001101010111001111";
WHEN "0101111" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011111000011001000101001110";
WHEN "0110000" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011110110100010011110000000";
WHEN "0110001" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011110100101001100010010010";
WHEN "0110010" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011110010101110010010110000";
WHEN "0110011" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011110000110000110000001000";
WHEN "0110100" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011101110110000111011000111";
WHEN "0110101" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011101100101110110100011101";
WHEN "0110110" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011101010101010011100111001";
WHEN "0110111" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011101000100011110101001100";
WHEN "0111000" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011100110011010111110000111";
WHEN "0111001" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011100100001111111000011101";
WHEN "0111010" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011100010000010100101000000";
WHEN "0111011" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011011111110011000100100100";
WHEN "0111100" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011011101100001010111111110";
WHEN "0111101" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011011011001101100000000011";
WHEN "0111110" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011011000110111011101101010";
WHEN "0111111" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011010110011111010001101001";
WHEN "1000000" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011010100000100111100111000";
WHEN "1000001" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011010001101000100000001111";
WHEN "1000010" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011001111001001111100100111";
WHEN "1000011" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011001100101001010010111011";
WHEN "1000100" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011001010000110100100000101";
WHEN "1000101" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011000111100001110001000001";
WHEN "1000110" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011000100111010111010101011";
WHEN "1000111" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011000010010010000001111111";
WHEN "1001000" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010111111100111000111111011";
WHEN "1001001" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010111100111010001101011110";
WHEN "1001010" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010111010001011010011100110";
WHEN "1001011" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010110111011010011011010011";
WHEN "1001100" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010110100100111100101100110";
WHEN "1001101" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010110001110010110011011111";
WHEN "1001110" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010101110111100000110000001";
WHEN "1001111" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010101100000011011110001110";
WHEN "1010000" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010101001001000111101001000";
WHEN "1010001" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010100110001100100011110100";
WHEN "1010010" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010100011001110010011010110";
WHEN "1010011" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010100000001110001100110010";
WHEN "1010100" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010011101001100010001001111";
WHEN "1010101" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010011010001000100001110100";
WHEN "1010110" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010010111000010111111100101";
WHEN "1010111" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010010011111011101011101100";
WHEN "1011000" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010010000110010100111010001";
WHEN "1011001" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010001101100111110011011011";
WHEN "1011010" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010001010011011010001010100";
WHEN "1011011" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010000111001101000010000111";
WHEN "1011100" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010000011111101000110111110";
WHEN "1011101" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010000000101011100001000010";
WHEN "1011110" => memoryC0_uid207_sinPiZTableGenerator_q <= "01001111101011000010001100001";
WHEN "1011111" => memoryC0_uid207_sinPiZTableGenerator_q <= "01001111010000011011001100111";
WHEN "1100000" => memoryC0_uid207_sinPiZTableGenerator_q <= "01001110110101100111010011111";
WHEN "1100001" => memoryC0_uid207_sinPiZTableGenerator_q <= "01001110011010100110101010111";
WHEN "1100010" => memoryC0_uid207_sinPiZTableGenerator_q <= "01001101111111011001011011101";
WHEN "1100011" => memoryC0_uid207_sinPiZTableGenerator_q <= "01001101100011111111101111111";
WHEN "1100100" => memoryC0_uid207_sinPiZTableGenerator_q <= "01001101001000011001110001011";
WHEN "1100101" => memoryC0_uid207_sinPiZTableGenerator_q <= "01001100101100100111101010001";
WHEN "1100110" => memoryC0_uid207_sinPiZTableGenerator_q <= "01001100010000101001100100001";
WHEN "1100111" => memoryC0_uid207_sinPiZTableGenerator_q <= "01001011110100011111101001011";
WHEN "1101000" => memoryC0_uid207_sinPiZTableGenerator_q <= "01001011011000001010000011111";
WHEN "1101001" => memoryC0_uid207_sinPiZTableGenerator_q <= "01001010111011101000111101111";
WHEN "1101010" => memoryC0_uid207_sinPiZTableGenerator_q <= "01001010011110111100100001011";
WHEN "1101011" => memoryC0_uid207_sinPiZTableGenerator_q <= "01001010000010000100111000111";
WHEN "1101100" => memoryC0_uid207_sinPiZTableGenerator_q <= "01001001100101000010001110101";
WHEN "1101101" => memoryC0_uid207_sinPiZTableGenerator_q <= "01001001000111110100101100111";
WHEN "1101110" => memoryC0_uid207_sinPiZTableGenerator_q <= "01001000101010011100011110001";
WHEN "1101111" => memoryC0_uid207_sinPiZTableGenerator_q <= "01001000001100111001101100110";
WHEN "1110000" => memoryC0_uid207_sinPiZTableGenerator_q <= "01000111101111001100100011011";
WHEN "1110001" => memoryC0_uid207_sinPiZTableGenerator_q <= "01000111010001010101001100101";
WHEN "1110010" => memoryC0_uid207_sinPiZTableGenerator_q <= "01000110110011010011110010111";
WHEN "1110011" => memoryC0_uid207_sinPiZTableGenerator_q <= "01000110010101001000100001000";
WHEN "1110100" => memoryC0_uid207_sinPiZTableGenerator_q <= "01000101110110110011100001101";
WHEN "1110101" => memoryC0_uid207_sinPiZTableGenerator_q <= "01000101011000010100111111100";
WHEN "1110110" => memoryC0_uid207_sinPiZTableGenerator_q <= "01000100111001101101000101100";
WHEN "1110111" => memoryC0_uid207_sinPiZTableGenerator_q <= "01000100011010111011111110011";
WHEN "1111000" => memoryC0_uid207_sinPiZTableGenerator_q <= "01000011111100000001110101000";
WHEN "1111001" => memoryC0_uid207_sinPiZTableGenerator_q <= "01000011011100111110110100010";
WHEN "1111010" => memoryC0_uid207_sinPiZTableGenerator_q <= "01000010111101110011000111010";
WHEN "1111011" => memoryC0_uid207_sinPiZTableGenerator_q <= "01000010011110011110111000111";
WHEN "1111100" => memoryC0_uid207_sinPiZTableGenerator_q <= "01000001111111000010010100010";
WHEN "1111101" => memoryC0_uid207_sinPiZTableGenerator_q <= "01000001011111011101100100011";
WHEN "1111110" => memoryC0_uid207_sinPiZTableGenerator_q <= "01000000111111110000110100011";
WHEN "1111111" => memoryC0_uid207_sinPiZTableGenerator_q <= "01000000011111111100001111011";
WHEN OTHERS =>
memoryC0_uid207_sinPiZTableGenerator_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--sumAHighB_uid220_sinPiZPolyEval(ADD,219)@12
sumAHighB_uid220_sinPiZPolyEval_a <= STD_LOGIC_VECTOR((29 downto 29 => memoryC0_uid207_sinPiZTableGenerator_q(28)) & memoryC0_uid207_sinPiZTableGenerator_q);
sumAHighB_uid220_sinPiZPolyEval_b <= STD_LOGIC_VECTOR((29 downto 22 => highBBits_uid219_sinPiZPolyEval_b(21)) & highBBits_uid219_sinPiZPolyEval_b);
sumAHighB_uid220_sinPiZPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid220_sinPiZPolyEval_a) + SIGNED(sumAHighB_uid220_sinPiZPolyEval_b));
sumAHighB_uid220_sinPiZPolyEval_q <= sumAHighB_uid220_sinPiZPolyEval_o(29 downto 0);
--lowRangeB_uid218_sinPiZPolyEval(BITSELECT,217)@12
lowRangeB_uid218_sinPiZPolyEval_in <= prodXYTruncFR_uid230_pT2_uid217_sinPiZPolyEval_b(1 downto 0);
lowRangeB_uid218_sinPiZPolyEval_b <= lowRangeB_uid218_sinPiZPolyEval_in(1 downto 0);
--s2_uid218_uid221_sinPiZPolyEval(BITJOIN,220)@12
s2_uid218_uid221_sinPiZPolyEval_q <= sumAHighB_uid220_sinPiZPolyEval_q & lowRangeB_uid218_sinPiZPolyEval_b;
--fxpSinRes_uid65_fpCosPiTest(BITSELECT,64)@12
fxpSinRes_uid65_fpCosPiTest_in <= s2_uid218_uid221_sinPiZPolyEval_q(29 downto 0);
fxpSinRes_uid65_fpCosPiTest_b <= fxpSinRes_uid65_fpCosPiTest_in(29 downto 5);
--reg_fxpSinRes_uid65_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_1(REG,270)@12
reg_fxpSinRes_uid65_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fxpSinRes_uid65_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_1_q <= "0000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fxpSinRes_uid65_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_1_q <= fxpSinRes_uid65_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_nor(LOGICAL,622)
ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_nor_a <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_notEnable_q;
ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_nor_b <= ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_sticky_ena_q;
ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_nor_q <= not (ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_nor_a or ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_nor_b);
--ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_sticky_ena(REG,623)
ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_nor_q = "1") THEN
ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_sticky_ena_q <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_enaAnd(LOGICAL,624)
ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_enaAnd_a <= ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_sticky_ena_q;
ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_enaAnd_b <= en;
ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_enaAnd_q <= ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_enaAnd_a and ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_enaAnd_b;
--LeftShiftStage131dto0_uid202_alignedZ_uid57_fpCosPiTest(BITSELECT,201)@7
LeftShiftStage131dto0_uid202_alignedZ_uid57_fpCosPiTest_in <= leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_q(31 downto 0);
LeftShiftStage131dto0_uid202_alignedZ_uid57_fpCosPiTest_b <= LeftShiftStage131dto0_uid202_alignedZ_uid57_fpCosPiTest_in(31 downto 0);
--leftShiftStage2Idx3_uid203_alignedZ_uid57_fpCosPiTest(BITJOIN,202)@7
leftShiftStage2Idx3_uid203_alignedZ_uid57_fpCosPiTest_q <= LeftShiftStage131dto0_uid202_alignedZ_uid57_fpCosPiTest_b & leftShiftStage2Idx3Pad3_uid131_fxpX_uid41_fpCosPiTest_q;
--LeftShiftStage132dto0_uid199_alignedZ_uid57_fpCosPiTest(BITSELECT,198)@7
LeftShiftStage132dto0_uid199_alignedZ_uid57_fpCosPiTest_in <= leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_q(32 downto 0);
LeftShiftStage132dto0_uid199_alignedZ_uid57_fpCosPiTest_b <= LeftShiftStage132dto0_uid199_alignedZ_uid57_fpCosPiTest_in(32 downto 0);
--leftShiftStage2Idx2_uid200_alignedZ_uid57_fpCosPiTest(BITJOIN,199)@7
leftShiftStage2Idx2_uid200_alignedZ_uid57_fpCosPiTest_q <= LeftShiftStage132dto0_uid199_alignedZ_uid57_fpCosPiTest_b & leftShiftStage2Idx2Pad2_uid128_fxpX_uid41_fpCosPiTest_q;
--LeftShiftStage133dto0_uid196_alignedZ_uid57_fpCosPiTest(BITSELECT,195)@7
LeftShiftStage133dto0_uid196_alignedZ_uid57_fpCosPiTest_in <= leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_q(33 downto 0);
LeftShiftStage133dto0_uid196_alignedZ_uid57_fpCosPiTest_b <= LeftShiftStage133dto0_uid196_alignedZ_uid57_fpCosPiTest_in(33 downto 0);
--leftShiftStage2Idx1_uid197_alignedZ_uid57_fpCosPiTest(BITJOIN,196)@7
leftShiftStage2Idx1_uid197_alignedZ_uid57_fpCosPiTest_q <= LeftShiftStage133dto0_uid196_alignedZ_uid57_fpCosPiTest_b & GND_q;
--vStage_uid141_lzcZ_uid56_fpCosPiTest(BITSELECT,140)@3
vStage_uid141_lzcZ_uid56_fpCosPiTest_in <= z_uid54_fpCosPiTest_b(2 downto 0);
vStage_uid141_lzcZ_uid56_fpCosPiTest_b <= vStage_uid141_lzcZ_uid56_fpCosPiTest_in(2 downto 0);
--ld_vStage_uid141_lzcZ_uid56_fpCosPiTest_b_to_leftShiftStage0Idx2_uid180_alignedZ_uid57_fpCosPiTest_b(DELAY,450)@3
ld_vStage_uid141_lzcZ_uid56_fpCosPiTest_b_to_leftShiftStage0Idx2_uid180_alignedZ_uid57_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 3, depth => 3 )
PORT MAP ( xin => vStage_uid141_lzcZ_uid56_fpCosPiTest_b, xout => ld_vStage_uid141_lzcZ_uid56_fpCosPiTest_b_to_leftShiftStage0Idx2_uid180_alignedZ_uid57_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage0Idx2_uid180_alignedZ_uid57_fpCosPiTest(BITJOIN,179)@6
leftShiftStage0Idx2_uid180_alignedZ_uid57_fpCosPiTest_q <= ld_vStage_uid141_lzcZ_uid56_fpCosPiTest_b_to_leftShiftStage0Idx2_uid180_alignedZ_uid57_fpCosPiTest_b_q & leftShiftStage0Idx2Pad32_uid108_fxpX_uid41_fpCosPiTest_q;
--X18dto0_uid176_alignedZ_uid57_fpCosPiTest(BITSELECT,175)@3
X18dto0_uid176_alignedZ_uid57_fpCosPiTest_in <= z_uid54_fpCosPiTest_b(18 downto 0);
X18dto0_uid176_alignedZ_uid57_fpCosPiTest_b <= X18dto0_uid176_alignedZ_uid57_fpCosPiTest_in(18 downto 0);
--ld_X18dto0_uid176_alignedZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx1_uid177_alignedZ_uid57_fpCosPiTest_b_inputreg(DELAY,573)
ld_X18dto0_uid176_alignedZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx1_uid177_alignedZ_uid57_fpCosPiTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 19, depth => 1 )
PORT MAP ( xin => X18dto0_uid176_alignedZ_uid57_fpCosPiTest_b, xout => ld_X18dto0_uid176_alignedZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx1_uid177_alignedZ_uid57_fpCosPiTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_X18dto0_uid176_alignedZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx1_uid177_alignedZ_uid57_fpCosPiTest_b(DELAY,449)@3
ld_X18dto0_uid176_alignedZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx1_uid177_alignedZ_uid57_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 19, depth => 2 )
PORT MAP ( xin => ld_X18dto0_uid176_alignedZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx1_uid177_alignedZ_uid57_fpCosPiTest_b_inputreg_q, xout => ld_X18dto0_uid176_alignedZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx1_uid177_alignedZ_uid57_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage0Idx1_uid177_alignedZ_uid57_fpCosPiTest(BITJOIN,176)@6
leftShiftStage0Idx1_uid177_alignedZ_uid57_fpCosPiTest_q <= ld_X18dto0_uid176_alignedZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx1_uid177_alignedZ_uid57_fpCosPiTest_b_q & leftShiftStage0Idx1Pad16_uid105_fxpX_uid41_fpCosPiTest_q;
--ld_z_uid54_fpCosPiTest_b_to_leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_c_inputreg(DELAY,574)
ld_z_uid54_fpCosPiTest_b_to_leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 35, depth => 1 )
PORT MAP ( xin => z_uid54_fpCosPiTest_b, xout => ld_z_uid54_fpCosPiTest_b_to_leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_z_uid54_fpCosPiTest_b_to_leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_c(DELAY,453)@3
ld_z_uid54_fpCosPiTest_b_to_leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_c : dspba_delay
GENERIC MAP ( width => 35, depth => 2 )
PORT MAP ( xin => ld_z_uid54_fpCosPiTest_b_to_leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_c_inputreg_q, xout => ld_z_uid54_fpCosPiTest_b_to_leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--rVStage_uid138_lzcZ_uid56_fpCosPiTest(BITSELECT,137)@3
rVStage_uid138_lzcZ_uid56_fpCosPiTest_in <= z_uid54_fpCosPiTest_b;
rVStage_uid138_lzcZ_uid56_fpCosPiTest_b <= rVStage_uid138_lzcZ_uid56_fpCosPiTest_in(34 downto 3);
--reg_rVStage_uid138_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid139_lzcZ_uid56_fpCosPiTest_1(REG,247)@3
reg_rVStage_uid138_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid139_lzcZ_uid56_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid138_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid139_lzcZ_uid56_fpCosPiTest_1_q <= "00000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid138_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid139_lzcZ_uid56_fpCosPiTest_1_q <= rVStage_uid138_lzcZ_uid56_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid139_lzcZ_uid56_fpCosPiTest(LOGICAL,138)@4
vCount_uid139_lzcZ_uid56_fpCosPiTest_a <= reg_rVStage_uid138_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid139_lzcZ_uid56_fpCosPiTest_1_q;
vCount_uid139_lzcZ_uid56_fpCosPiTest_b <= leftShiftStage0Idx2Pad32_uid108_fxpX_uid41_fpCosPiTest_q;
vCount_uid139_lzcZ_uid56_fpCosPiTest_q <= "1" when vCount_uid139_lzcZ_uid56_fpCosPiTest_a = vCount_uid139_lzcZ_uid56_fpCosPiTest_b else "0";
--ld_vCount_uid139_lzcZ_uid56_fpCosPiTest_q_to_r_uid172_lzcZ_uid56_fpCosPiTest_f(DELAY,447)@4
ld_vCount_uid139_lzcZ_uid56_fpCosPiTest_q_to_r_uid172_lzcZ_uid56_fpCosPiTest_f : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => vCount_uid139_lzcZ_uid56_fpCosPiTest_q, xout => ld_vCount_uid139_lzcZ_uid56_fpCosPiTest_q_to_r_uid172_lzcZ_uid56_fpCosPiTest_f_q, ena => en(0), clk => clk, aclr => areset );
--mO_uid140_lzcZ_uid56_fpCosPiTest(CONSTANT,139)
mO_uid140_lzcZ_uid56_fpCosPiTest_q <= "11111111111111111111111111111";
--cStage_uid142_lzcZ_uid56_fpCosPiTest(BITJOIN,141)@3
cStage_uid142_lzcZ_uid56_fpCosPiTest_q <= vStage_uid141_lzcZ_uid56_fpCosPiTest_b & mO_uid140_lzcZ_uid56_fpCosPiTest_q;
--reg_cStage_uid142_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid144_lzcZ_uid56_fpCosPiTest_3(REG,249)@3
reg_cStage_uid142_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid144_lzcZ_uid56_fpCosPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cStage_uid142_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid144_lzcZ_uid56_fpCosPiTest_3_q <= "00000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cStage_uid142_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid144_lzcZ_uid56_fpCosPiTest_3_q <= cStage_uid142_lzcZ_uid56_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--vStagei_uid144_lzcZ_uid56_fpCosPiTest(MUX,143)@4
vStagei_uid144_lzcZ_uid56_fpCosPiTest_s <= vCount_uid139_lzcZ_uid56_fpCosPiTest_q;
vStagei_uid144_lzcZ_uid56_fpCosPiTest: PROCESS (vStagei_uid144_lzcZ_uid56_fpCosPiTest_s, en, reg_rVStage_uid138_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid139_lzcZ_uid56_fpCosPiTest_1_q, reg_cStage_uid142_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid144_lzcZ_uid56_fpCosPiTest_3_q)
BEGIN
CASE vStagei_uid144_lzcZ_uid56_fpCosPiTest_s IS
WHEN "0" => vStagei_uid144_lzcZ_uid56_fpCosPiTest_q <= reg_rVStage_uid138_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid139_lzcZ_uid56_fpCosPiTest_1_q;
WHEN "1" => vStagei_uid144_lzcZ_uid56_fpCosPiTest_q <= reg_cStage_uid142_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid144_lzcZ_uid56_fpCosPiTest_3_q;
WHEN OTHERS => vStagei_uid144_lzcZ_uid56_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid146_lzcZ_uid56_fpCosPiTest(BITSELECT,145)@4
rVStage_uid146_lzcZ_uid56_fpCosPiTest_in <= vStagei_uid144_lzcZ_uid56_fpCosPiTest_q;
rVStage_uid146_lzcZ_uid56_fpCosPiTest_b <= rVStage_uid146_lzcZ_uid56_fpCosPiTest_in(31 downto 16);
--reg_rVStage_uid146_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid147_lzcZ_uid56_fpCosPiTest_1(REG,250)@4
reg_rVStage_uid146_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid147_lzcZ_uid56_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid146_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid147_lzcZ_uid56_fpCosPiTest_1_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid146_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid147_lzcZ_uid56_fpCosPiTest_1_q <= rVStage_uid146_lzcZ_uid56_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid147_lzcZ_uid56_fpCosPiTest(LOGICAL,146)@5
vCount_uid147_lzcZ_uid56_fpCosPiTest_a <= reg_rVStage_uid146_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid147_lzcZ_uid56_fpCosPiTest_1_q;
vCount_uid147_lzcZ_uid56_fpCosPiTest_b <= leftShiftStage0Idx1Pad16_uid105_fxpX_uid41_fpCosPiTest_q;
vCount_uid147_lzcZ_uid56_fpCosPiTest_q <= "1" when vCount_uid147_lzcZ_uid56_fpCosPiTest_a = vCount_uid147_lzcZ_uid56_fpCosPiTest_b else "0";
--ld_vCount_uid147_lzcZ_uid56_fpCosPiTest_q_to_r_uid172_lzcZ_uid56_fpCosPiTest_e(DELAY,446)@5
ld_vCount_uid147_lzcZ_uid56_fpCosPiTest_q_to_r_uid172_lzcZ_uid56_fpCosPiTest_e : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vCount_uid147_lzcZ_uid56_fpCosPiTest_q, xout => ld_vCount_uid147_lzcZ_uid56_fpCosPiTest_q_to_r_uid172_lzcZ_uid56_fpCosPiTest_e_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid148_lzcZ_uid56_fpCosPiTest(BITSELECT,147)@4
vStage_uid148_lzcZ_uid56_fpCosPiTest_in <= vStagei_uid144_lzcZ_uid56_fpCosPiTest_q(15 downto 0);
vStage_uid148_lzcZ_uid56_fpCosPiTest_b <= vStage_uid148_lzcZ_uid56_fpCosPiTest_in(15 downto 0);
--reg_vStage_uid148_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid150_lzcZ_uid56_fpCosPiTest_3(REG,252)@4
reg_vStage_uid148_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid150_lzcZ_uid56_fpCosPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid148_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid150_lzcZ_uid56_fpCosPiTest_3_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid148_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid150_lzcZ_uid56_fpCosPiTest_3_q <= vStage_uid148_lzcZ_uid56_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid150_lzcZ_uid56_fpCosPiTest(MUX,149)@5
vStagei_uid150_lzcZ_uid56_fpCosPiTest_s <= vCount_uid147_lzcZ_uid56_fpCosPiTest_q;
vStagei_uid150_lzcZ_uid56_fpCosPiTest: PROCESS (vStagei_uid150_lzcZ_uid56_fpCosPiTest_s, en, reg_rVStage_uid146_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid147_lzcZ_uid56_fpCosPiTest_1_q, reg_vStage_uid148_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid150_lzcZ_uid56_fpCosPiTest_3_q)
BEGIN
CASE vStagei_uid150_lzcZ_uid56_fpCosPiTest_s IS
WHEN "0" => vStagei_uid150_lzcZ_uid56_fpCosPiTest_q <= reg_rVStage_uid146_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid147_lzcZ_uid56_fpCosPiTest_1_q;
WHEN "1" => vStagei_uid150_lzcZ_uid56_fpCosPiTest_q <= reg_vStage_uid148_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid150_lzcZ_uid56_fpCosPiTest_3_q;
WHEN OTHERS => vStagei_uid150_lzcZ_uid56_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid152_lzcZ_uid56_fpCosPiTest(BITSELECT,151)@5
rVStage_uid152_lzcZ_uid56_fpCosPiTest_in <= vStagei_uid150_lzcZ_uid56_fpCosPiTest_q;
rVStage_uid152_lzcZ_uid56_fpCosPiTest_b <= rVStage_uid152_lzcZ_uid56_fpCosPiTest_in(15 downto 8);
--vCount_uid153_lzcZ_uid56_fpCosPiTest(LOGICAL,152)@5
vCount_uid153_lzcZ_uid56_fpCosPiTest_a <= rVStage_uid152_lzcZ_uid56_fpCosPiTest_b;
vCount_uid153_lzcZ_uid56_fpCosPiTest_b <= cstAllZWE_uid21_fpCosPiTest_q;
vCount_uid153_lzcZ_uid56_fpCosPiTest_q <= "1" when vCount_uid153_lzcZ_uid56_fpCosPiTest_a = vCount_uid153_lzcZ_uid56_fpCosPiTest_b else "0";
--reg_vCount_uid153_lzcZ_uid56_fpCosPiTest_0_to_r_uid172_lzcZ_uid56_fpCosPiTest_3(REG,256)@5
reg_vCount_uid153_lzcZ_uid56_fpCosPiTest_0_to_r_uid172_lzcZ_uid56_fpCosPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid153_lzcZ_uid56_fpCosPiTest_0_to_r_uid172_lzcZ_uid56_fpCosPiTest_3_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid153_lzcZ_uid56_fpCosPiTest_0_to_r_uid172_lzcZ_uid56_fpCosPiTest_3_q <= vCount_uid153_lzcZ_uid56_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--vStage_uid154_lzcZ_uid56_fpCosPiTest(BITSELECT,153)@5
vStage_uid154_lzcZ_uid56_fpCosPiTest_in <= vStagei_uid150_lzcZ_uid56_fpCosPiTest_q(7 downto 0);
vStage_uid154_lzcZ_uid56_fpCosPiTest_b <= vStage_uid154_lzcZ_uid56_fpCosPiTest_in(7 downto 0);
--vStagei_uid156_lzcZ_uid56_fpCosPiTest(MUX,155)@5
vStagei_uid156_lzcZ_uid56_fpCosPiTest_s <= vCount_uid153_lzcZ_uid56_fpCosPiTest_q;
vStagei_uid156_lzcZ_uid56_fpCosPiTest: PROCESS (vStagei_uid156_lzcZ_uid56_fpCosPiTest_s, en, rVStage_uid152_lzcZ_uid56_fpCosPiTest_b, vStage_uid154_lzcZ_uid56_fpCosPiTest_b)
BEGIN
CASE vStagei_uid156_lzcZ_uid56_fpCosPiTest_s IS
WHEN "0" => vStagei_uid156_lzcZ_uid56_fpCosPiTest_q <= rVStage_uid152_lzcZ_uid56_fpCosPiTest_b;
WHEN "1" => vStagei_uid156_lzcZ_uid56_fpCosPiTest_q <= vStage_uid154_lzcZ_uid56_fpCosPiTest_b;
WHEN OTHERS => vStagei_uid156_lzcZ_uid56_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid158_lzcZ_uid56_fpCosPiTest(BITSELECT,157)@5
rVStage_uid158_lzcZ_uid56_fpCosPiTest_in <= vStagei_uid156_lzcZ_uid56_fpCosPiTest_q;
rVStage_uid158_lzcZ_uid56_fpCosPiTest_b <= rVStage_uid158_lzcZ_uid56_fpCosPiTest_in(7 downto 4);
--reg_rVStage_uid158_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid159_lzcZ_uid56_fpCosPiTest_1(REG,253)@5
reg_rVStage_uid158_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid159_lzcZ_uid56_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid158_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid159_lzcZ_uid56_fpCosPiTest_1_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid158_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid159_lzcZ_uid56_fpCosPiTest_1_q <= rVStage_uid158_lzcZ_uid56_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid159_lzcZ_uid56_fpCosPiTest(LOGICAL,158)@6
vCount_uid159_lzcZ_uid56_fpCosPiTest_a <= reg_rVStage_uid158_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid159_lzcZ_uid56_fpCosPiTest_1_q;
vCount_uid159_lzcZ_uid56_fpCosPiTest_b <= leftShiftStage1Idx1Pad4_uid114_fxpX_uid41_fpCosPiTest_q;
vCount_uid159_lzcZ_uid56_fpCosPiTest_q <= "1" when vCount_uid159_lzcZ_uid56_fpCosPiTest_a = vCount_uid159_lzcZ_uid56_fpCosPiTest_b else "0";
--vStage_uid160_lzcZ_uid56_fpCosPiTest(BITSELECT,159)@5
vStage_uid160_lzcZ_uid56_fpCosPiTest_in <= vStagei_uid156_lzcZ_uid56_fpCosPiTest_q(3 downto 0);
vStage_uid160_lzcZ_uid56_fpCosPiTest_b <= vStage_uid160_lzcZ_uid56_fpCosPiTest_in(3 downto 0);
--reg_vStage_uid160_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid162_lzcZ_uid56_fpCosPiTest_3(REG,255)@5
reg_vStage_uid160_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid162_lzcZ_uid56_fpCosPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid160_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid162_lzcZ_uid56_fpCosPiTest_3_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid160_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid162_lzcZ_uid56_fpCosPiTest_3_q <= vStage_uid160_lzcZ_uid56_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid162_lzcZ_uid56_fpCosPiTest(MUX,161)@6
vStagei_uid162_lzcZ_uid56_fpCosPiTest_s <= vCount_uid159_lzcZ_uid56_fpCosPiTest_q;
vStagei_uid162_lzcZ_uid56_fpCosPiTest: PROCESS (vStagei_uid162_lzcZ_uid56_fpCosPiTest_s, en, reg_rVStage_uid158_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid159_lzcZ_uid56_fpCosPiTest_1_q, reg_vStage_uid160_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid162_lzcZ_uid56_fpCosPiTest_3_q)
BEGIN
CASE vStagei_uid162_lzcZ_uid56_fpCosPiTest_s IS
WHEN "0" => vStagei_uid162_lzcZ_uid56_fpCosPiTest_q <= reg_rVStage_uid158_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid159_lzcZ_uid56_fpCosPiTest_1_q;
WHEN "1" => vStagei_uid162_lzcZ_uid56_fpCosPiTest_q <= reg_vStage_uid160_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid162_lzcZ_uid56_fpCosPiTest_3_q;
WHEN OTHERS => vStagei_uid162_lzcZ_uid56_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid164_lzcZ_uid56_fpCosPiTest(BITSELECT,163)@6
rVStage_uid164_lzcZ_uid56_fpCosPiTest_in <= vStagei_uid162_lzcZ_uid56_fpCosPiTest_q;
rVStage_uid164_lzcZ_uid56_fpCosPiTest_b <= rVStage_uid164_lzcZ_uid56_fpCosPiTest_in(3 downto 2);
--vCount_uid165_lzcZ_uid56_fpCosPiTest(LOGICAL,164)@6
vCount_uid165_lzcZ_uid56_fpCosPiTest_a <= rVStage_uid164_lzcZ_uid56_fpCosPiTest_b;
vCount_uid165_lzcZ_uid56_fpCosPiTest_b <= leftShiftStage2Idx2Pad2_uid128_fxpX_uid41_fpCosPiTest_q;
vCount_uid165_lzcZ_uid56_fpCosPiTest_q <= "1" when vCount_uid165_lzcZ_uid56_fpCosPiTest_a = vCount_uid165_lzcZ_uid56_fpCosPiTest_b else "0";
--vStage_uid166_lzcZ_uid56_fpCosPiTest(BITSELECT,165)@6
vStage_uid166_lzcZ_uid56_fpCosPiTest_in <= vStagei_uid162_lzcZ_uid56_fpCosPiTest_q(1 downto 0);
vStage_uid166_lzcZ_uid56_fpCosPiTest_b <= vStage_uid166_lzcZ_uid56_fpCosPiTest_in(1 downto 0);
--vStagei_uid168_lzcZ_uid56_fpCosPiTest(MUX,167)@6
vStagei_uid168_lzcZ_uid56_fpCosPiTest_s <= vCount_uid165_lzcZ_uid56_fpCosPiTest_q;
vStagei_uid168_lzcZ_uid56_fpCosPiTest: PROCESS (vStagei_uid168_lzcZ_uid56_fpCosPiTest_s, en, rVStage_uid164_lzcZ_uid56_fpCosPiTest_b, vStage_uid166_lzcZ_uid56_fpCosPiTest_b)
BEGIN
CASE vStagei_uid168_lzcZ_uid56_fpCosPiTest_s IS
WHEN "0" => vStagei_uid168_lzcZ_uid56_fpCosPiTest_q <= rVStage_uid164_lzcZ_uid56_fpCosPiTest_b;
WHEN "1" => vStagei_uid168_lzcZ_uid56_fpCosPiTest_q <= vStage_uid166_lzcZ_uid56_fpCosPiTest_b;
WHEN OTHERS => vStagei_uid168_lzcZ_uid56_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid170_lzcZ_uid56_fpCosPiTest(BITSELECT,169)@6
rVStage_uid170_lzcZ_uid56_fpCosPiTest_in <= vStagei_uid168_lzcZ_uid56_fpCosPiTest_q;
rVStage_uid170_lzcZ_uid56_fpCosPiTest_b <= rVStage_uid170_lzcZ_uid56_fpCosPiTest_in(1 downto 1);
--vCount_uid171_lzcZ_uid56_fpCosPiTest(LOGICAL,170)@6
vCount_uid171_lzcZ_uid56_fpCosPiTest_a <= rVStage_uid170_lzcZ_uid56_fpCosPiTest_b;
vCount_uid171_lzcZ_uid56_fpCosPiTest_b <= GND_q;
vCount_uid171_lzcZ_uid56_fpCosPiTest_q <= "1" when vCount_uid171_lzcZ_uid56_fpCosPiTest_a = vCount_uid171_lzcZ_uid56_fpCosPiTest_b else "0";
--r_uid172_lzcZ_uid56_fpCosPiTest(BITJOIN,171)@6
r_uid172_lzcZ_uid56_fpCosPiTest_q <= ld_vCount_uid139_lzcZ_uid56_fpCosPiTest_q_to_r_uid172_lzcZ_uid56_fpCosPiTest_f_q & ld_vCount_uid147_lzcZ_uid56_fpCosPiTest_q_to_r_uid172_lzcZ_uid56_fpCosPiTest_e_q & reg_vCount_uid153_lzcZ_uid56_fpCosPiTest_0_to_r_uid172_lzcZ_uid56_fpCosPiTest_3_q & vCount_uid159_lzcZ_uid56_fpCosPiTest_q & vCount_uid165_lzcZ_uid56_fpCosPiTest_q & vCount_uid171_lzcZ_uid56_fpCosPiTest_q;
--leftShiftStageSel5Dto4_uid182_alignedZ_uid57_fpCosPiTest(BITSELECT,181)@6
leftShiftStageSel5Dto4_uid182_alignedZ_uid57_fpCosPiTest_in <= r_uid172_lzcZ_uid56_fpCosPiTest_q;
leftShiftStageSel5Dto4_uid182_alignedZ_uid57_fpCosPiTest_b <= leftShiftStageSel5Dto4_uid182_alignedZ_uid57_fpCosPiTest_in(5 downto 4);
--leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest(MUX,182)@6
leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_s <= leftShiftStageSel5Dto4_uid182_alignedZ_uid57_fpCosPiTest_b;
leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest: PROCESS (leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_s, en, ld_z_uid54_fpCosPiTest_b_to_leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_c_q, leftShiftStage0Idx1_uid177_alignedZ_uid57_fpCosPiTest_q, leftShiftStage0Idx2_uid180_alignedZ_uid57_fpCosPiTest_q, cstZwSwF_uid15_fpCosPiTest_q)
BEGIN
CASE leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_s IS
WHEN "00" => leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_q <= ld_z_uid54_fpCosPiTest_b_to_leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_c_q;
WHEN "01" => leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_q <= leftShiftStage0Idx1_uid177_alignedZ_uid57_fpCosPiTest_q;
WHEN "10" => leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_q <= leftShiftStage0Idx2_uid180_alignedZ_uid57_fpCosPiTest_q;
WHEN "11" => leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_q <= cstZwSwF_uid15_fpCosPiTest_q;
WHEN OTHERS => leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage022dto0_uid191_alignedZ_uid57_fpCosPiTest(BITSELECT,190)@6
LeftShiftStage022dto0_uid191_alignedZ_uid57_fpCosPiTest_in <= leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_q(22 downto 0);
LeftShiftStage022dto0_uid191_alignedZ_uid57_fpCosPiTest_b <= LeftShiftStage022dto0_uid191_alignedZ_uid57_fpCosPiTest_in(22 downto 0);
--leftShiftStage1Idx3_uid192_alignedZ_uid57_fpCosPiTest(BITJOIN,191)@6
leftShiftStage1Idx3_uid192_alignedZ_uid57_fpCosPiTest_q <= LeftShiftStage022dto0_uid191_alignedZ_uid57_fpCosPiTest_b & leftShiftStage1Idx3Pad12_uid120_fxpX_uid41_fpCosPiTest_q;
--reg_leftShiftStage1Idx3_uid192_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_5(REG,261)@6
reg_leftShiftStage1Idx3_uid192_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx3_uid192_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_5_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx3_uid192_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_5_q <= leftShiftStage1Idx3_uid192_alignedZ_uid57_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage026dto0_uid188_alignedZ_uid57_fpCosPiTest(BITSELECT,187)@6
LeftShiftStage026dto0_uid188_alignedZ_uid57_fpCosPiTest_in <= leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_q(26 downto 0);
LeftShiftStage026dto0_uid188_alignedZ_uid57_fpCosPiTest_b <= LeftShiftStage026dto0_uid188_alignedZ_uid57_fpCosPiTest_in(26 downto 0);
--leftShiftStage1Idx2_uid189_alignedZ_uid57_fpCosPiTest(BITJOIN,188)@6
leftShiftStage1Idx2_uid189_alignedZ_uid57_fpCosPiTest_q <= LeftShiftStage026dto0_uid188_alignedZ_uid57_fpCosPiTest_b & cstAllZWE_uid21_fpCosPiTest_q;
--reg_leftShiftStage1Idx2_uid189_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_4(REG,260)@6
reg_leftShiftStage1Idx2_uid189_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx2_uid189_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_4_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx2_uid189_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_4_q <= leftShiftStage1Idx2_uid189_alignedZ_uid57_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage030dto0_uid185_alignedZ_uid57_fpCosPiTest(BITSELECT,184)@6
LeftShiftStage030dto0_uid185_alignedZ_uid57_fpCosPiTest_in <= leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_q(30 downto 0);
LeftShiftStage030dto0_uid185_alignedZ_uid57_fpCosPiTest_b <= LeftShiftStage030dto0_uid185_alignedZ_uid57_fpCosPiTest_in(30 downto 0);
--leftShiftStage1Idx1_uid186_alignedZ_uid57_fpCosPiTest(BITJOIN,185)@6
leftShiftStage1Idx1_uid186_alignedZ_uid57_fpCosPiTest_q <= LeftShiftStage030dto0_uid185_alignedZ_uid57_fpCosPiTest_b & leftShiftStage1Idx1Pad4_uid114_fxpX_uid41_fpCosPiTest_q;
--reg_leftShiftStage1Idx1_uid186_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_3(REG,259)@6
reg_leftShiftStage1Idx1_uid186_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx1_uid186_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_3_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx1_uid186_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_3_q <= leftShiftStage1Idx1_uid186_alignedZ_uid57_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--reg_leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_2(REG,258)@6
reg_leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_2_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_2_q <= leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel3Dto2_uid193_alignedZ_uid57_fpCosPiTest(BITSELECT,192)@6
leftShiftStageSel3Dto2_uid193_alignedZ_uid57_fpCosPiTest_in <= r_uid172_lzcZ_uid56_fpCosPiTest_q(3 downto 0);
leftShiftStageSel3Dto2_uid193_alignedZ_uid57_fpCosPiTest_b <= leftShiftStageSel3Dto2_uid193_alignedZ_uid57_fpCosPiTest_in(3 downto 2);
--reg_leftShiftStageSel3Dto2_uid193_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_1(REG,257)@6
reg_leftShiftStageSel3Dto2_uid193_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel3Dto2_uid193_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel3Dto2_uid193_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_1_q <= leftShiftStageSel3Dto2_uid193_alignedZ_uid57_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest(MUX,193)@7
leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_s <= reg_leftShiftStageSel3Dto2_uid193_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_1_q;
leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest: PROCESS (leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_s, en, reg_leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_2_q, reg_leftShiftStage1Idx1_uid186_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_3_q, reg_leftShiftStage1Idx2_uid189_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_4_q, reg_leftShiftStage1Idx3_uid192_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_5_q)
BEGIN
CASE leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_s IS
WHEN "00" => leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_q <= reg_leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_2_q;
WHEN "01" => leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_q <= reg_leftShiftStage1Idx1_uid186_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_3_q;
WHEN "10" => leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_q <= reg_leftShiftStage1Idx2_uid189_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_4_q;
WHEN "11" => leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_q <= reg_leftShiftStage1Idx3_uid192_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_5_q;
WHEN OTHERS => leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--leftShiftStageSel1Dto0_uid204_alignedZ_uid57_fpCosPiTest(BITSELECT,203)@6
leftShiftStageSel1Dto0_uid204_alignedZ_uid57_fpCosPiTest_in <= r_uid172_lzcZ_uid56_fpCosPiTest_q(1 downto 0);
leftShiftStageSel1Dto0_uid204_alignedZ_uid57_fpCosPiTest_b <= leftShiftStageSel1Dto0_uid204_alignedZ_uid57_fpCosPiTest_in(1 downto 0);
--reg_leftShiftStageSel1Dto0_uid204_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest_1(REG,262)@6
reg_leftShiftStageSel1Dto0_uid204_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel1Dto0_uid204_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel1Dto0_uid204_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest_1_q <= leftShiftStageSel1Dto0_uid204_alignedZ_uid57_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest(MUX,204)@7
leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest_s <= reg_leftShiftStageSel1Dto0_uid204_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest_1_q;
leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest: PROCESS (leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest_s, en, leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_q, leftShiftStage2Idx1_uid197_alignedZ_uid57_fpCosPiTest_q, leftShiftStage2Idx2_uid200_alignedZ_uid57_fpCosPiTest_q, leftShiftStage2Idx3_uid203_alignedZ_uid57_fpCosPiTest_q)
BEGIN
CASE leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest_s IS
WHEN "00" => leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest_q <= leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_q;
WHEN "01" => leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest_q <= leftShiftStage2Idx1_uid197_alignedZ_uid57_fpCosPiTest_q;
WHEN "10" => leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest_q <= leftShiftStage2Idx2_uid200_alignedZ_uid57_fpCosPiTest_q;
WHEN "11" => leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest_q <= leftShiftStage2Idx3_uid203_alignedZ_uid57_fpCosPiTest_q;
WHEN OTHERS => leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--alignedZLow_uid58_fpCosPiTest(BITSELECT,57)@7
alignedZLow_uid58_fpCosPiTest_in <= leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest_q;
alignedZLow_uid58_fpCosPiTest_b <= alignedZLow_uid58_fpCosPiTest_in(34 downto 11);
--ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_inputreg(DELAY,612)
ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 24, depth => 1 )
PORT MAP ( xin => alignedZLow_uid58_fpCosPiTest_b, xout => ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem(DUALMEM,613)
ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_reset0 <= areset;
ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_ia <= ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_inputreg_q;
ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_aa <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdreg_q;
ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_ab <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdmux_q;
ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 24,
widthad_a => 2,
numwords_a => 3,
width_b => 24,
widthad_b => 2,
numwords_b => 3,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_iq,
address_a => ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_aa,
data_a => ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_ia
);
ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_q <= ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_iq(23 downto 0);
--reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0(REG,269)@12
reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_q <= ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest(MULT,222)@13
prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_pr <= UNSIGNED(prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_a) * UNSIGNED(prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_b);
prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_a <= (others => '0');
prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_b <= (others => '0');
prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_a <= reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_q;
prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_b <= reg_fxpSinRes_uid65_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_1_q;
prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_s1 <= STD_LOGIC_VECTOR(prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_pr);
END IF;
END IF;
END PROCESS;
prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_q <= prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid224_mul2xSinRes_uid66_fpCosPiTest(BITSELECT,223)@16
prodXYTruncFR_uid224_mul2xSinRes_uid66_fpCosPiTest_in <= prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_q;
prodXYTruncFR_uid224_mul2xSinRes_uid66_fpCosPiTest_b <= prodXYTruncFR_uid224_mul2xSinRes_uid66_fpCosPiTest_in(48 downto 23);
--normBit_uid67_fpCosPiTest(BITSELECT,66)@16
normBit_uid67_fpCosPiTest_in <= prodXYTruncFR_uid224_mul2xSinRes_uid66_fpCosPiTest_b;
normBit_uid67_fpCosPiTest_b <= normBit_uid67_fpCosPiTest_in(25 downto 25);
--cstAllZWF_uid9_fpCosPiTest(CONSTANT,8)
cstAllZWF_uid9_fpCosPiTest_q <= "00000000000000000000000";
--rndExpUpdate_uid72_uid73_fpCosPiTest(BITJOIN,72)@16
rndExpUpdate_uid72_uid73_fpCosPiTest_q <= normBit_uid67_fpCosPiTest_b & cstAllZWF_uid9_fpCosPiTest_q & VCC_q;
--ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_nor(LOGICAL,558)
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_nor_a <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_notEnable_q;
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_nor_b <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_sticky_ena_q;
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_nor_q <= not (ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_nor_a or ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_nor_b);
--ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_sticky_ena(REG,559)
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_nor_q = "1") THEN
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_sticky_ena_q <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_enaAnd(LOGICAL,560)
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_enaAnd_a <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_sticky_ena_q;
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_enaAnd_b <= en;
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_enaAnd_q <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_enaAnd_a and ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_enaAnd_b;
--reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1(REG,271)@6
reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q <= r_uid172_lzcZ_uid56_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem(DUALMEM,549)
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_reset0 <= areset;
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_ia <= reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q;
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_aa <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdreg_q;
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_ab <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdmux_q;
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 6,
widthad_a => 3,
numwords_a => 7,
width_b => 6,
widthad_b => 3,
numwords_b => 7,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_iq,
address_a => ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_aa,
data_a => ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_ia
);
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_q <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_iq(5 downto 0);
--cstBiasM1_uid11_fpCosPiTest(CONSTANT,10)
cstBiasM1_uid11_fpCosPiTest_q <= "01111110";
--expHardCase_uid59_fpCosPiTest(SUB,58)@15
expHardCase_uid59_fpCosPiTest_a <= STD_LOGIC_VECTOR("0" & cstBiasM1_uid11_fpCosPiTest_q);
expHardCase_uid59_fpCosPiTest_b <= STD_LOGIC_VECTOR("000" & ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_q);
expHardCase_uid59_fpCosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expHardCase_uid59_fpCosPiTest_a) - UNSIGNED(expHardCase_uid59_fpCosPiTest_b));
expHardCase_uid59_fpCosPiTest_q <= expHardCase_uid59_fpCosPiTest_o(8 downto 0);
--expP_uid60_fpCosPiTest(BITSELECT,59)@15
expP_uid60_fpCosPiTest_in <= expHardCase_uid59_fpCosPiTest_q(7 downto 0);
expP_uid60_fpCosPiTest_b <= expP_uid60_fpCosPiTest_in(7 downto 0);
--reg_expP_uid60_fpCosPiTest_0_to_expFracPreRnd_uid71_uid71_fpCosPiTest_1(REG,272)@15
reg_expP_uid60_fpCosPiTest_0_to_expFracPreRnd_uid71_uid71_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expP_uid60_fpCosPiTest_0_to_expFracPreRnd_uid71_uid71_fpCosPiTest_1_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expP_uid60_fpCosPiTest_0_to_expFracPreRnd_uid71_uid71_fpCosPiTest_1_q <= expP_uid60_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--highRes_uid68_fpCosPiTest(BITSELECT,67)@16
highRes_uid68_fpCosPiTest_in <= prodXYTruncFR_uid224_mul2xSinRes_uid66_fpCosPiTest_b(24 downto 0);
highRes_uid68_fpCosPiTest_b <= highRes_uid68_fpCosPiTest_in(24 downto 1);
--lowRes_uid69_fpCosPiTest(BITSELECT,68)@16
lowRes_uid69_fpCosPiTest_in <= prodXYTruncFR_uid224_mul2xSinRes_uid66_fpCosPiTest_b(23 downto 0);
lowRes_uid69_fpCosPiTest_b <= lowRes_uid69_fpCosPiTest_in(23 downto 0);
--fracRCompPreRnd_uid70_fpCosPiTest(MUX,69)@16
fracRCompPreRnd_uid70_fpCosPiTest_s <= normBit_uid67_fpCosPiTest_b;
fracRCompPreRnd_uid70_fpCosPiTest: PROCESS (fracRCompPreRnd_uid70_fpCosPiTest_s, en, lowRes_uid69_fpCosPiTest_b, highRes_uid68_fpCosPiTest_b)
BEGIN
CASE fracRCompPreRnd_uid70_fpCosPiTest_s IS
WHEN "0" => fracRCompPreRnd_uid70_fpCosPiTest_q <= lowRes_uid69_fpCosPiTest_b;
WHEN "1" => fracRCompPreRnd_uid70_fpCosPiTest_q <= highRes_uid68_fpCosPiTest_b;
WHEN OTHERS => fracRCompPreRnd_uid70_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--expFracPreRnd_uid71_uid71_fpCosPiTest(BITJOIN,70)@16
expFracPreRnd_uid71_uid71_fpCosPiTest_q <= reg_expP_uid60_fpCosPiTest_0_to_expFracPreRnd_uid71_uid71_fpCosPiTest_1_q & fracRCompPreRnd_uid70_fpCosPiTest_q;
--expFracComp_uid74_fpCosPiTest(ADD,73)@16
expFracComp_uid74_fpCosPiTest_a <= STD_LOGIC_VECTOR("0" & expFracPreRnd_uid71_uid71_fpCosPiTest_q);
expFracComp_uid74_fpCosPiTest_b <= STD_LOGIC_VECTOR("00000000" & rndExpUpdate_uid72_uid73_fpCosPiTest_q);
expFracComp_uid74_fpCosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expFracComp_uid74_fpCosPiTest_a) + UNSIGNED(expFracComp_uid74_fpCosPiTest_b));
expFracComp_uid74_fpCosPiTest_q <= expFracComp_uid74_fpCosPiTest_o(32 downto 0);
--expRComp_uid76_fpCosPiTest(BITSELECT,75)@16
expRComp_uid76_fpCosPiTest_in <= expFracComp_uid74_fpCosPiTest_q(31 downto 0);
expRComp_uid76_fpCosPiTest_b <= expRComp_uid76_fpCosPiTest_in(31 downto 24);
--fracXIsZero_uid27_fpCosPiTest(LOGICAL,26)@0
fracXIsZero_uid27_fpCosPiTest_a <= fracX_uid7_fpCosPiTest_b;
fracXIsZero_uid27_fpCosPiTest_b <= cstAllZWF_uid9_fpCosPiTest_q;
fracXIsZero_uid27_fpCosPiTest_q <= "1" when fracXIsZero_uid27_fpCosPiTest_a = fracXIsZero_uid27_fpCosPiTest_b else "0";
--InvFracXIsZero_uid29_fpCosPiTest(LOGICAL,28)@0
InvFracXIsZero_uid29_fpCosPiTest_a <= fracXIsZero_uid27_fpCosPiTest_q;
InvFracXIsZero_uid29_fpCosPiTest_q <= not InvFracXIsZero_uid29_fpCosPiTest_a;
--expXIsMax_uid25_fpCosPiTest(LOGICAL,24)@0
expXIsMax_uid25_fpCosPiTest_a <= expX_uid6_fpCosPiTest_b;
expXIsMax_uid25_fpCosPiTest_b <= cstAllOWE_uid8_fpCosPiTest_q;
expXIsMax_uid25_fpCosPiTest_q <= "1" when expXIsMax_uid25_fpCosPiTest_a = expXIsMax_uid25_fpCosPiTest_b else "0";
--exc_N_uid30_fpCosPiTest(LOGICAL,29)@0
exc_N_uid30_fpCosPiTest_a <= expXIsMax_uid25_fpCosPiTest_q;
exc_N_uid30_fpCosPiTest_b <= InvFracXIsZero_uid29_fpCosPiTest_q;
exc_N_uid30_fpCosPiTest_q <= exc_N_uid30_fpCosPiTest_a and exc_N_uid30_fpCosPiTest_b;
--InvExc_N_uid31_fpCosPiTest(LOGICAL,30)@0
InvExc_N_uid31_fpCosPiTest_a <= exc_N_uid30_fpCosPiTest_q;
InvExc_N_uid31_fpCosPiTest_q <= not InvExc_N_uid31_fpCosPiTest_a;
--exc_I_uid28_fpCosPiTest(LOGICAL,27)@0
exc_I_uid28_fpCosPiTest_a <= expXIsMax_uid25_fpCosPiTest_q;
exc_I_uid28_fpCosPiTest_b <= fracXIsZero_uid27_fpCosPiTest_q;
exc_I_uid28_fpCosPiTest_q <= exc_I_uid28_fpCosPiTest_a and exc_I_uid28_fpCosPiTest_b;
--InvExc_I_uid32_fpCosPiTest(LOGICAL,31)@0
InvExc_I_uid32_fpCosPiTest_a <= exc_I_uid28_fpCosPiTest_q;
InvExc_I_uid32_fpCosPiTest_q <= not InvExc_I_uid32_fpCosPiTest_a;
--expXIsZero_uid23_fpCosPiTest(LOGICAL,22)@0
expXIsZero_uid23_fpCosPiTest_a <= expX_uid6_fpCosPiTest_b;
expXIsZero_uid23_fpCosPiTest_b <= cstAllZWE_uid21_fpCosPiTest_q;
expXIsZero_uid23_fpCosPiTest_q <= "1" when expXIsZero_uid23_fpCosPiTest_a = expXIsZero_uid23_fpCosPiTest_b else "0";
--InvExpXIsZero_uid33_fpCosPiTest(LOGICAL,32)@0
InvExpXIsZero_uid33_fpCosPiTest_a <= expXIsZero_uid23_fpCosPiTest_q;
InvExpXIsZero_uid33_fpCosPiTest_q <= not InvExpXIsZero_uid33_fpCosPiTest_a;
--exc_R_uid34_fpCosPiTest(LOGICAL,33)@0
exc_R_uid34_fpCosPiTest_a <= InvExpXIsZero_uid33_fpCosPiTest_q;
exc_R_uid34_fpCosPiTest_b <= InvExc_I_uid32_fpCosPiTest_q;
exc_R_uid34_fpCosPiTest_c <= InvExc_N_uid31_fpCosPiTest_q;
exc_R_uid34_fpCosPiTest_q <= exc_R_uid34_fpCosPiTest_a and exc_R_uid34_fpCosPiTest_b and exc_R_uid34_fpCosPiTest_c;
--ld_exc_R_uid34_fpCosPiTest_q_to_xIsInt_uid80_fpCosPiTest_a(DELAY,337)@0
ld_exc_R_uid34_fpCosPiTest_q_to_xIsInt_uid80_fpCosPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => exc_R_uid34_fpCosPiTest_q, xout => ld_exc_R_uid34_fpCosPiTest_q_to_xIsInt_uid80_fpCosPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--xIsHalf_uid83_fpCosPiTest(LOGICAL,82)@2
xIsHalf_uid83_fpCosPiTest_a <= ld_exc_R_uid34_fpCosPiTest_q_to_xIsInt_uid80_fpCosPiTest_a_q;
xIsHalf_uid83_fpCosPiTest_b <= fxpXFracHalf_uid46_fpCosPiTest_q;
xIsHalf_uid83_fpCosPiTest_c <= InvCosXIsOne_uid77_fpCosPiTest_q;
xIsHalf_uid83_fpCosPiTest_d <= InvXEvenInt_uid81_fpCosPiTest_q;
xIsHalf_uid83_fpCosPiTest_q <= xIsHalf_uid83_fpCosPiTest_a and xIsHalf_uid83_fpCosPiTest_b and xIsHalf_uid83_fpCosPiTest_c and xIsHalf_uid83_fpCosPiTest_d;
--ld_xIsHalf_uid83_fpCosPiTest_q_to_expRPostExc1_uid91_fpCosPiTest_b(DELAY,355)@2
ld_xIsHalf_uid83_fpCosPiTest_q_to_expRPostExc1_uid91_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 14 )
PORT MAP ( xin => xIsHalf_uid83_fpCosPiTest_q, xout => ld_xIsHalf_uid83_fpCosPiTest_q_to_expRPostExc1_uid91_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--expRPostExc1_uid91_fpCosPiTest(MUX,90)@16
expRPostExc1_uid91_fpCosPiTest_s <= ld_xIsHalf_uid83_fpCosPiTest_q_to_expRPostExc1_uid91_fpCosPiTest_b_q;
expRPostExc1_uid91_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expRPostExc1_uid91_fpCosPiTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE expRPostExc1_uid91_fpCosPiTest_s IS
WHEN "0" => expRPostExc1_uid91_fpCosPiTest_q <= expRComp_uid76_fpCosPiTest_b;
WHEN "1" => expRPostExc1_uid91_fpCosPiTest_q <= cstAllZWE_uid21_fpCosPiTest_q;
WHEN OTHERS => expRPostExc1_uid91_fpCosPiTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_nor(LOGICAL,570)
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_nor_a <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_notEnable_q;
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_nor_b <= ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_sticky_ena_q;
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_nor_q <= not (ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_nor_a or ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_nor_b);
--ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_mem_top(CONSTANT,566)
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_mem_top_q <= "01100";
--ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_cmp(LOGICAL,567)
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_cmp_a <= ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_mem_top_q;
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdmux_q);
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_cmp_q <= "1" when ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_cmp_a = ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_cmp_b else "0";
--ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_cmpReg(REG,568)
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_cmpReg_q <= ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_sticky_ena(REG,571)
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_nor_q = "1") THEN
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_sticky_ena_q <= ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_enaAnd(LOGICAL,572)
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_enaAnd_a <= ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_sticky_ena_q;
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_enaAnd_b <= en;
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_enaAnd_q <= ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_enaAnd_a and ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_enaAnd_b;
--ld_expXIsZero_uid23_fpCosPiTest_q_to_xIntOrXZOrCosOne_uid93_fpCosPiTest_b(DELAY,359)@0
ld_expXIsZero_uid23_fpCosPiTest_q_to_xIntOrXZOrCosOne_uid93_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => expXIsZero_uid23_fpCosPiTest_q, xout => ld_expXIsZero_uid23_fpCosPiTest_q_to_xIntOrXZOrCosOne_uid93_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--fxpXFracZero_uid45_fpCosPiTest(LOGICAL,44)@2
fxpXFracZero_uid45_fpCosPiTest_a <= reg_fxpXFrac_uid43_fpCosPiTest_0_to_fxpXFracZero_uid45_fpCosPiTest_1_q;
fxpXFracZero_uid45_fpCosPiTest_b <= STD_LOGIC_VECTOR("0" & cstZwSwF_uid15_fpCosPiTest_q);
fxpXFracZero_uid45_fpCosPiTest_q <= "1" when fxpXFracZero_uid45_fpCosPiTest_a = fxpXFracZero_uid45_fpCosPiTest_b else "0";
--fracZCosNotOne_uid78_fpCosPiTest(LOGICAL,77)@2
fracZCosNotOne_uid78_fpCosPiTest_a <= fxpXFracZero_uid45_fpCosPiTest_q;
fracZCosNotOne_uid78_fpCosPiTest_b <= InvCosXIsOne_uid77_fpCosPiTest_q;
fracZCosNotOne_uid78_fpCosPiTest_q <= fracZCosNotOne_uid78_fpCosPiTest_a and fracZCosNotOne_uid78_fpCosPiTest_b;
--evenIntCosNotOneFZ_uid79_fpCosPiTest(LOGICAL,78)@2
evenIntCosNotOneFZ_uid79_fpCosPiTest_a <= ld_xEvenInt_uid35_fpCosPiTest_c_to_evenIntCosNotOneFZ_uid79_fpCosPiTest_a_q;
evenIntCosNotOneFZ_uid79_fpCosPiTest_b <= fracZCosNotOne_uid78_fpCosPiTest_q;
evenIntCosNotOneFZ_uid79_fpCosPiTest_q <= evenIntCosNotOneFZ_uid79_fpCosPiTest_a or evenIntCosNotOneFZ_uid79_fpCosPiTest_b;
--xIsInt_uid80_fpCosPiTest(LOGICAL,79)@2
xIsInt_uid80_fpCosPiTest_a <= ld_exc_R_uid34_fpCosPiTest_q_to_xIsInt_uid80_fpCosPiTest_a_q;
xIsInt_uid80_fpCosPiTest_b <= evenIntCosNotOneFZ_uid79_fpCosPiTest_q;
xIsInt_uid80_fpCosPiTest_q <= xIsInt_uid80_fpCosPiTest_a and xIsInt_uid80_fpCosPiTest_b;
--xIntOrXZOrCosOne_uid93_fpCosPiTest(LOGICAL,92)@2
xIntOrXZOrCosOne_uid93_fpCosPiTest_a <= xIsInt_uid80_fpCosPiTest_q;
xIntOrXZOrCosOne_uid93_fpCosPiTest_b <= ld_expXIsZero_uid23_fpCosPiTest_q_to_xIntOrXZOrCosOne_uid93_fpCosPiTest_b_q;
xIntOrXZOrCosOne_uid93_fpCosPiTest_c <= ld_cosXIsOne_uid36_fpCosPiTest_c_to_InvCosXIsOne_uid77_fpCosPiTest_a_q;
xIntOrXZOrCosOne_uid93_fpCosPiTest_q <= xIntOrXZOrCosOne_uid93_fpCosPiTest_a or xIntOrXZOrCosOne_uid93_fpCosPiTest_b or xIntOrXZOrCosOne_uid93_fpCosPiTest_c;
--excRNaN_uid84_fpCosPiTest(LOGICAL,83)@0
excRNaN_uid84_fpCosPiTest_a <= exc_N_uid30_fpCosPiTest_q;
excRNaN_uid84_fpCosPiTest_b <= exc_I_uid28_fpCosPiTest_q;
excRNaN_uid84_fpCosPiTest_q <= excRNaN_uid84_fpCosPiTest_a or excRNaN_uid84_fpCosPiTest_b;
--rInfOrNaN_uid92_fpCosPiTest(LOGICAL,91)@0
rInfOrNaN_uid92_fpCosPiTest_a <= GND_q;
rInfOrNaN_uid92_fpCosPiTest_b <= excRNaN_uid84_fpCosPiTest_q;
rInfOrNaN_uid92_fpCosPiTest_q <= rInfOrNaN_uid92_fpCosPiTest_a or rInfOrNaN_uid92_fpCosPiTest_b;
--ld_rInfOrNaN_uid92_fpCosPiTest_q_to_join_uid94_fpCosPiTest_a(DELAY,361)@0
ld_rInfOrNaN_uid92_fpCosPiTest_q_to_join_uid94_fpCosPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => rInfOrNaN_uid92_fpCosPiTest_q, xout => ld_rInfOrNaN_uid92_fpCosPiTest_q_to_join_uid94_fpCosPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--join_uid94_fpCosPiTest(BITJOIN,93)@2
join_uid94_fpCosPiTest_q <= xIntOrXZOrCosOne_uid93_fpCosPiTest_q & ld_rInfOrNaN_uid92_fpCosPiTest_q_to_join_uid94_fpCosPiTest_a_q;
--reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1(REG,274)@2
reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q <= join_uid94_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt(COUNTER,562)
-- every=1, low=0, high=12, step=1, init=1
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt_i = 11 THEN
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt_eq <= '1';
ELSE
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt_eq = '1') THEN
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt_i <= ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt_i - 12;
ELSE
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt_i <= ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt_i,4));
--ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdreg(REG,563)
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdreg_q <= ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdmux(MUX,564)
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdmux_s <= en;
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdmux: PROCESS (ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdmux_s, ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdreg_q, ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt_q)
BEGIN
CASE ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdmux_s IS
WHEN "0" => ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdmux_q <= ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdreg_q;
WHEN "1" => ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdmux_q <= ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem(DUALMEM,561)
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_reset0 <= areset;
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_ia <= reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q;
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_aa <= ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdreg_q;
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_ab <= ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdmux_q;
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 2,
widthad_a => 4,
numwords_a => 13,
width_b => 2,
widthad_b => 4,
numwords_b => 13,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_iq,
address_a => ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_aa,
data_a => ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_ia
);
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_q <= ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_iq(1 downto 0);
--expRPostExc_uid95_fpCosPiTest(MUX,94)@17
expRPostExc_uid95_fpCosPiTest_s <= ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_q;
expRPostExc_uid95_fpCosPiTest: PROCESS (expRPostExc_uid95_fpCosPiTest_s, en, expRPostExc1_uid91_fpCosPiTest_q, cstAllOWE_uid8_fpCosPiTest_q, cstBias_uid10_fpCosPiTest_q, cstBias_uid10_fpCosPiTest_q)
BEGIN
CASE expRPostExc_uid95_fpCosPiTest_s IS
WHEN "00" => expRPostExc_uid95_fpCosPiTest_q <= expRPostExc1_uid91_fpCosPiTest_q;
WHEN "01" => expRPostExc_uid95_fpCosPiTest_q <= cstAllOWE_uid8_fpCosPiTest_q;
WHEN "10" => expRPostExc_uid95_fpCosPiTest_q <= cstBias_uid10_fpCosPiTest_q;
WHEN "11" => expRPostExc_uid95_fpCosPiTest_q <= cstBias_uid10_fpCosPiTest_q;
WHEN OTHERS => expRPostExc_uid95_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--oneFracRPostExc2_uid87_fpCosPiTest(CONSTANT,86)
oneFracRPostExc2_uid87_fpCosPiTest_q <= "00000000000000000000001";
--fracRComp_uid75_fpCosPiTest(BITSELECT,74)@16
fracRComp_uid75_fpCosPiTest_in <= expFracComp_uid74_fpCosPiTest_q(23 downto 0);
fracRComp_uid75_fpCosPiTest_b <= fracRComp_uid75_fpCosPiTest_in(23 downto 1);
--reg_xIsHalf_uid83_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_5(REG,243)@2
reg_xIsHalf_uid83_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xIsHalf_uid83_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_5_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xIsHalf_uid83_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_5_q <= xIsHalf_uid83_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--reg_expXIsZero_uid23_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_4(REG,242)@2
reg_expXIsZero_uid23_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expXIsZero_uid23_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_4_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expXIsZero_uid23_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_4_q <= ld_expXIsZero_uid23_fpCosPiTest_q_to_xIntOrXZOrCosOne_uid93_fpCosPiTest_b_q;
END IF;
END IF;
END PROCESS;
--reg_fxpXFracHalf_uid46_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_3(REG,241)@2
reg_fxpXFracHalf_uid46_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fxpXFracHalf_uid46_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_3_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fxpXFracHalf_uid46_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_3_q <= fxpXFracHalf_uid46_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--reg_xIsInt_uid80_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_2(REG,240)@2
reg_xIsInt_uid80_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xIsInt_uid80_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xIsInt_uid80_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_2_q <= xIsInt_uid80_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--reg_cosXIsOne_uid36_fpCosPiTest_1_to_bigCond_uid85_fpCosPiTest_1(REG,239)@0
reg_cosXIsOne_uid36_fpCosPiTest_1_to_bigCond_uid85_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cosXIsOne_uid36_fpCosPiTest_1_to_bigCond_uid85_fpCosPiTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cosXIsOne_uid36_fpCosPiTest_1_to_bigCond_uid85_fpCosPiTest_1_q <= cosXIsOne_uid36_fpCosPiTest_c;
END IF;
END IF;
END PROCESS;
--ld_reg_cosXIsOne_uid36_fpCosPiTest_1_to_bigCond_uid85_fpCosPiTest_1_q_to_bigCond_uid85_fpCosPiTest_a(DELAY,346)@1
ld_reg_cosXIsOne_uid36_fpCosPiTest_1_to_bigCond_uid85_fpCosPiTest_1_q_to_bigCond_uid85_fpCosPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => reg_cosXIsOne_uid36_fpCosPiTest_1_to_bigCond_uid85_fpCosPiTest_1_q, xout => ld_reg_cosXIsOne_uid36_fpCosPiTest_1_to_bigCond_uid85_fpCosPiTest_1_q_to_bigCond_uid85_fpCosPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--bigCond_uid85_fpCosPiTest(LOGICAL,84)@3
bigCond_uid85_fpCosPiTest_a <= ld_reg_cosXIsOne_uid36_fpCosPiTest_1_to_bigCond_uid85_fpCosPiTest_1_q_to_bigCond_uid85_fpCosPiTest_a_q;
bigCond_uid85_fpCosPiTest_b <= reg_xIsInt_uid80_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_2_q;
bigCond_uid85_fpCosPiTest_c <= reg_fxpXFracHalf_uid46_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_3_q;
bigCond_uid85_fpCosPiTest_d <= reg_expXIsZero_uid23_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_4_q;
bigCond_uid85_fpCosPiTest_f <= reg_xIsHalf_uid83_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_5_q;
bigCond_uid85_fpCosPiTest_g <= GND_q;
bigCond_uid85_fpCosPiTest_q <= bigCond_uid85_fpCosPiTest_a or bigCond_uid85_fpCosPiTest_b or bigCond_uid85_fpCosPiTest_c or bigCond_uid85_fpCosPiTest_d or bigCond_uid85_fpCosPiTest_f or bigCond_uid85_fpCosPiTest_g;
--ld_bigCond_uid85_fpCosPiTest_q_to_fracRPostExc1_uid86_fpCosPiTest_b(DELAY,351)@3
ld_bigCond_uid85_fpCosPiTest_q_to_fracRPostExc1_uid86_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 13 )
PORT MAP ( xin => bigCond_uid85_fpCosPiTest_q, xout => ld_bigCond_uid85_fpCosPiTest_q_to_fracRPostExc1_uid86_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--fracRPostExc1_uid86_fpCosPiTest(MUX,85)@16
fracRPostExc1_uid86_fpCosPiTest_s <= ld_bigCond_uid85_fpCosPiTest_q_to_fracRPostExc1_uid86_fpCosPiTest_b_q;
fracRPostExc1_uid86_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
fracRPostExc1_uid86_fpCosPiTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE fracRPostExc1_uid86_fpCosPiTest_s IS
WHEN "0" => fracRPostExc1_uid86_fpCosPiTest_q <= fracRComp_uid75_fpCosPiTest_b;
WHEN "1" => fracRPostExc1_uid86_fpCosPiTest_q <= cstAllZWF_uid9_fpCosPiTest_q;
WHEN OTHERS => fracRPostExc1_uid86_fpCosPiTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--reg_excRNaN_uid84_fpCosPiTest_0_to_fracRPostExc_uid88_fpCosPiTest_1(REG,273)@0
reg_excRNaN_uid84_fpCosPiTest_0_to_fracRPostExc_uid88_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_excRNaN_uid84_fpCosPiTest_0_to_fracRPostExc_uid88_fpCosPiTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_excRNaN_uid84_fpCosPiTest_0_to_fracRPostExc_uid88_fpCosPiTest_1_q <= excRNaN_uid84_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_excRNaN_uid84_fpCosPiTest_0_to_fracRPostExc_uid88_fpCosPiTest_1_q_to_fracRPostExc_uid88_fpCosPiTest_b(DELAY,353)@1
ld_reg_excRNaN_uid84_fpCosPiTest_0_to_fracRPostExc_uid88_fpCosPiTest_1_q_to_fracRPostExc_uid88_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 16 )
PORT MAP ( xin => reg_excRNaN_uid84_fpCosPiTest_0_to_fracRPostExc_uid88_fpCosPiTest_1_q, xout => ld_reg_excRNaN_uid84_fpCosPiTest_0_to_fracRPostExc_uid88_fpCosPiTest_1_q_to_fracRPostExc_uid88_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--fracRPostExc_uid88_fpCosPiTest(MUX,87)@17
fracRPostExc_uid88_fpCosPiTest_s <= ld_reg_excRNaN_uid84_fpCosPiTest_0_to_fracRPostExc_uid88_fpCosPiTest_1_q_to_fracRPostExc_uid88_fpCosPiTest_b_q;
fracRPostExc_uid88_fpCosPiTest: PROCESS (fracRPostExc_uid88_fpCosPiTest_s, en, fracRPostExc1_uid86_fpCosPiTest_q, oneFracRPostExc2_uid87_fpCosPiTest_q)
BEGIN
CASE fracRPostExc_uid88_fpCosPiTest_s IS
WHEN "0" => fracRPostExc_uid88_fpCosPiTest_q <= fracRPostExc1_uid86_fpCosPiTest_q;
WHEN "1" => fracRPostExc_uid88_fpCosPiTest_q <= oneFracRPostExc2_uid87_fpCosPiTest_q;
WHEN OTHERS => fracRPostExc_uid88_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--R_uid102_fpCosPiTest(BITJOIN,101)@17
R_uid102_fpCosPiTest_q <= ld_signR_uid101_fpCosPiTest_q_to_R_uid102_fpCosPiTest_c_q & expRPostExc_uid95_fpCosPiTest_q & fracRPostExc_uid88_fpCosPiTest_q;
--xOut(GPOUT,4)@17
q <= R_uid102_fpCosPiTest_q;
end normal;
|
-----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Release Version 13.1
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing device programming or simulation files), and
-- any associated documentation or information are expressly subject to the
-- terms and conditions of the Altera Program License Subscription Agreement,
-- Altera MegaCore Function License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for the sole
-- purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
-----------------------------------------------------------------------------
-- VHDL created from fp_cospi_s5
-- VHDL created on Wed Feb 27 15:22:33 2013
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.all;
use std.TextIO.all;
use work.dspba_library_package.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
entity fp_cospi_s5 is
port (
a : in std_logic_vector(31 downto 0);
en : in std_logic_vector(0 downto 0);
q : out std_logic_vector(31 downto 0);
clk : in std_logic;
areset : in std_logic
);
end;
architecture normal of fp_cospi_s5 is
attribute altera_attribute : string;
attribute altera_attribute of normal : architecture is "-name NOT_GATE_PUSH_BACK OFF; -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON; -name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410";
signal GND_q : std_logic_vector (0 downto 0);
signal VCC_q : std_logic_vector (0 downto 0);
signal cstAllOWE_uid8_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal cstAllZWF_uid9_fpCosPiTest_q : std_logic_vector (22 downto 0);
signal cstBias_uid10_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal cstBiasM1_uid11_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal cstBiasPwF_uid12_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal biasMwShiftMO_uid13_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal cst01pWShift_uid14_fpCosPiTest_q : std_logic_vector (12 downto 0);
signal cstZwSwF_uid15_fpCosPiTest_q : std_logic_vector (34 downto 0);
signal cstAllZWE_uid21_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal rangeReducedFxPX_uid51_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal rangeReducedFxPX_uid51_fpCosPiTest_q : std_logic_vector (35 downto 0);
signal fracRPostExc1_uid86_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal fracRPostExc1_uid86_fpCosPiTest_q : std_logic_vector (22 downto 0);
signal oneFracRPostExc2_uid87_fpCosPiTest_q : std_logic_vector (22 downto 0);
signal expRPostExc1_uid91_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal expRPostExc1_uid91_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal signRComp_uid99_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal signRComp_uid99_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal signRComp_uid99_fpCosPiTest_c : std_logic_vector(0 downto 0);
signal signRComp_uid99_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal signR_uid101_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal signR_uid101_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal signR_uid101_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal leftShiftStage0Idx1Pad16_uid105_fxpX_uid41_fpCosPiTest_q : std_logic_vector (15 downto 0);
signal leftShiftStage0Idx2Pad32_uid108_fxpX_uid41_fpCosPiTest_q : std_logic_vector (31 downto 0);
signal leftShiftStage0Idx3_uid111_fxpX_uid41_fpCosPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage1Idx1Pad4_uid114_fxpX_uid41_fpCosPiTest_q : std_logic_vector (3 downto 0);
signal leftShiftStage1Idx3Pad12_uid120_fxpX_uid41_fpCosPiTest_q : std_logic_vector (11 downto 0);
signal leftShiftStage2Idx2Pad2_uid128_fxpX_uid41_fpCosPiTest_q : std_logic_vector (1 downto 0);
signal leftShiftStage2Idx3Pad3_uid131_fxpX_uid41_fpCosPiTest_q : std_logic_vector (2 downto 0);
signal mO_uid140_lzcZ_uid56_fpCosPiTest_q : std_logic_vector (28 downto 0);
signal memoryC2_uid209_sinPiZTableGenerator_q : std_logic_vector(13 downto 0);
signal prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_a : std_logic_vector (23 downto 0);
signal prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_b : std_logic_vector (24 downto 0);
signal prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_s1 : std_logic_vector (48 downto 0);
signal prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_pr : UNSIGNED (48 downto 0);
signal prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_q : std_logic_vector (48 downto 0);
signal prodXY_uid226_pT1_uid211_sinPiZPolyEval_a : std_logic_vector (13 downto 0);
signal prodXY_uid226_pT1_uid211_sinPiZPolyEval_b : std_logic_vector (13 downto 0);
signal prodXY_uid226_pT1_uid211_sinPiZPolyEval_s1 : std_logic_vector (27 downto 0);
signal prodXY_uid226_pT1_uid211_sinPiZPolyEval_pr : SIGNED (28 downto 0);
signal prodXY_uid226_pT1_uid211_sinPiZPolyEval_q : std_logic_vector (27 downto 0);
signal prodXY_uid229_pT2_uid217_sinPiZPolyEval_a : std_logic_vector (15 downto 0);
signal prodXY_uid229_pT2_uid217_sinPiZPolyEval_b : std_logic_vector (22 downto 0);
signal prodXY_uid229_pT2_uid217_sinPiZPolyEval_s1 : std_logic_vector (38 downto 0);
signal prodXY_uid229_pT2_uid217_sinPiZPolyEval_pr : SIGNED (39 downto 0);
signal prodXY_uid229_pT2_uid217_sinPiZPolyEval_q : std_logic_vector (38 downto 0);
signal reg_leftShiftStageSel3Dto2_uid123_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_2_q : std_logic_vector (36 downto 0);
signal reg_leftShiftStage1Idx1_uid116_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_3_q : std_logic_vector (36 downto 0);
signal reg_leftShiftStage1Idx2_uid119_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_4_q : std_logic_vector (36 downto 0);
signal reg_leftShiftStage1Idx3_uid122_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_5_q : std_logic_vector (36 downto 0);
signal reg_leftShiftStageSel1Dto0_uid134_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_fxpXFrac_uid43_fpCosPiTest_0_to_fxpXFracZero_uid45_fpCosPiTest_1_q : std_logic_vector (35 downto 0);
signal reg_cosXIsOne_uid36_fpCosPiTest_1_to_bigCond_uid85_fpCosPiTest_1_q : std_logic_vector (0 downto 0);
signal reg_xIsInt_uid80_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_2_q : std_logic_vector (0 downto 0);
signal reg_fxpXFracHalf_uid46_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_3_q : std_logic_vector (0 downto 0);
signal reg_expXIsZero_uid23_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_4_q : std_logic_vector (0 downto 0);
signal reg_xIsHalf_uid83_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_5_q : std_logic_vector (0 downto 0);
signal reg_pad_o_uid16_uid47_fpCosPiTest_0_to_oMFxpXFrac_uid47_fpCosPiTest_0_q : std_logic_vector (36 downto 0);
signal reg_pad_half_uid17_uid52_fpCosPiTest_0_to_z_halfMRRFxPXE_uid52_fpCosPiTest_0_q : std_logic_vector (35 downto 0);
signal reg_rVStage_uid138_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid139_lzcZ_uid56_fpCosPiTest_1_q : std_logic_vector (31 downto 0);
signal reg_cStage_uid142_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid144_lzcZ_uid56_fpCosPiTest_3_q : std_logic_vector (31 downto 0);
signal reg_rVStage_uid146_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid147_lzcZ_uid56_fpCosPiTest_1_q : std_logic_vector (15 downto 0);
signal reg_vStage_uid148_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid150_lzcZ_uid56_fpCosPiTest_3_q : std_logic_vector (15 downto 0);
signal reg_rVStage_uid158_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid159_lzcZ_uid56_fpCosPiTest_1_q : std_logic_vector (3 downto 0);
signal reg_vStage_uid160_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid162_lzcZ_uid56_fpCosPiTest_3_q : std_logic_vector (3 downto 0);
signal reg_vCount_uid153_lzcZ_uid56_fpCosPiTest_0_to_r_uid172_lzcZ_uid56_fpCosPiTest_3_q : std_logic_vector (0 downto 0);
signal reg_leftShiftStageSel3Dto2_uid193_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_2_q : std_logic_vector (34 downto 0);
signal reg_leftShiftStage1Idx1_uid186_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_3_q : std_logic_vector (34 downto 0);
signal reg_leftShiftStage1Idx2_uid189_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_4_q : std_logic_vector (34 downto 0);
signal reg_leftShiftStage1Idx3_uid192_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_5_q : std_logic_vector (34 downto 0);
signal reg_leftShiftStageSel1Dto0_uid204_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_zAddr_uid62_fpCosPiTest_0_to_memoryC2_uid209_sinPiZTableGenerator_0_q : std_logic_vector (6 downto 0);
signal reg_yT1_uid210_sinPiZPolyEval_0_to_prodXY_uid226_pT1_uid211_sinPiZPolyEval_0_q : std_logic_vector (13 downto 0);
signal reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_q : std_logic_vector (15 downto 0);
signal reg_s1_uid212_uid215_sinPiZPolyEval_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_1_q : std_logic_vector (22 downto 0);
signal reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_q : std_logic_vector (23 downto 0);
signal reg_fxpSinRes_uid65_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_1_q : std_logic_vector (24 downto 0);
signal reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q : std_logic_vector (5 downto 0);
signal reg_expP_uid60_fpCosPiTest_0_to_expFracPreRnd_uid71_uid71_fpCosPiTest_1_q : std_logic_vector (7 downto 0);
signal reg_excRNaN_uid84_fpCosPiTest_0_to_fracRPostExc_uid88_fpCosPiTest_1_q : std_logic_vector (0 downto 0);
signal reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q : std_logic_vector (1 downto 0);
signal ld_FxpXFrac35_uid44_fpCosPiTest_b_to_rangeReducedFxPX_uid51_fpCosPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_fxpXFrac_uid43_fpCosPiTest_b_to_rangeReducedFxPX_uid51_fpCosPiTest_c_q : std_logic_vector (35 downto 0);
signal ld_cosXIsOne_uid36_fpCosPiTest_c_to_InvCosXIsOne_uid77_fpCosPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_xEvenInt_uid35_fpCosPiTest_c_to_evenIntCosNotOneFZ_uid79_fpCosPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_exc_R_uid34_fpCosPiTest_q_to_xIsInt_uid80_fpCosPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_reg_cosXIsOne_uid36_fpCosPiTest_1_to_bigCond_uid85_fpCosPiTest_1_q_to_bigCond_uid85_fpCosPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_bigCond_uid85_fpCosPiTest_q_to_fracRPostExc1_uid86_fpCosPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_reg_excRNaN_uid84_fpCosPiTest_0_to_fracRPostExc_uid88_fpCosPiTest_1_q_to_fracRPostExc_uid88_fpCosPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_xIsHalf_uid83_fpCosPiTest_q_to_expRPostExc1_uid91_fpCosPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_expXIsZero_uid23_fpCosPiTest_q_to_xIntOrXZOrCosOne_uid93_fpCosPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_rInfOrNaN_uid92_fpCosPiTest_q_to_join_uid94_fpCosPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_xParityXorHalfParity_uid96_fpCosPiTest_q_to_signRComp_uid99_fpCosPiTest_c_q : std_logic_vector (0 downto 0);
signal ld_fxpXFracHalf_uid46_fpCosPiTest_q_to_InvFxpXFracHalf_uid100_fpCosPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_signR_uid101_fpCosPiTest_q_to_R_uid102_fpCosPiTest_c_q : std_logic_vector (0 downto 0);
signal ld_vCount_uid147_lzcZ_uid56_fpCosPiTest_q_to_r_uid172_lzcZ_uid56_fpCosPiTest_e_q : std_logic_vector (0 downto 0);
signal ld_vCount_uid139_lzcZ_uid56_fpCosPiTest_q_to_r_uid172_lzcZ_uid56_fpCosPiTest_f_q : std_logic_vector (0 downto 0);
signal ld_X18dto0_uid176_alignedZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx1_uid177_alignedZ_uid57_fpCosPiTest_b_q : std_logic_vector (18 downto 0);
signal ld_vStage_uid141_lzcZ_uid56_fpCosPiTest_b_to_leftShiftStage0Idx2_uid180_alignedZ_uid57_fpCosPiTest_b_q : std_logic_vector (2 downto 0);
signal ld_z_uid54_fpCosPiTest_b_to_leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_c_q : std_logic_vector (34 downto 0);
signal ld_reg_yT1_uid210_sinPiZPolyEval_0_to_prodXY_uid226_pT1_uid211_sinPiZPolyEval_0_q_to_prodXY_uid226_pT1_uid211_sinPiZPolyEval_a_q : std_logic_vector (13 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_reset0 : std_logic;
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_ia : std_logic_vector (5 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_iq : std_logic_vector (5 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_q : std_logic_vector (5 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt_eq : std_logic;
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_mem_top_q : std_logic_vector (3 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve : boolean;
attribute preserve of ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_sticky_ena_q : signal is true;
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_reset0 : std_logic;
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_ia : std_logic_vector (1 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_iq : std_logic_vector (1 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_q : std_logic_vector (1 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt_eq : std_logic;
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_mem_top_q : std_logic_vector (4 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_sticky_ena_q : signal is true;
signal ld_X18dto0_uid176_alignedZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx1_uid177_alignedZ_uid57_fpCosPiTest_b_inputreg_q : std_logic_vector (18 downto 0);
signal ld_z_uid54_fpCosPiTest_b_to_leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_c_inputreg_q : std_logic_vector (34 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_reset0 : std_logic;
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_ia : std_logic_vector (6 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_iq : std_logic_vector (6 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_q : std_logic_vector (6 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_sticky_ena_q : signal is true;
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_reset0 : std_logic;
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_ia : std_logic_vector (6 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_aa : std_logic_vector (1 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_ab : std_logic_vector (1 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_iq : std_logic_vector (6 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_q : std_logic_vector (6 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt_q : std_logic_vector(1 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt_i : unsigned(1 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt_eq : std_logic;
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdreg_q : std_logic_vector (1 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_mem_top_q : std_logic_vector (2 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_sticky_ena_q : signal is true;
signal ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_inputreg_q : std_logic_vector (15 downto 0);
signal ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_reset0 : std_logic;
signal ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_ia : std_logic_vector (15 downto 0);
signal ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_aa : std_logic_vector (1 downto 0);
signal ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_ab : std_logic_vector (1 downto 0);
signal ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_iq : std_logic_vector (15 downto 0);
signal ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_q : std_logic_vector (15 downto 0);
signal ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_sticky_ena_q : signal is true;
signal ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_inputreg_q : std_logic_vector (23 downto 0);
signal ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_reset0 : std_logic;
signal ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_ia : std_logic_vector (23 downto 0);
signal ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_aa : std_logic_vector (1 downto 0);
signal ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_ab : std_logic_vector (1 downto 0);
signal ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_iq : std_logic_vector (23 downto 0);
signal ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_q : std_logic_vector (23 downto 0);
signal ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_sticky_ena_q : signal is true;
signal pad_o_uid16_uid47_fpCosPiTest_q : std_logic_vector (36 downto 0);
signal pad_half_uid17_uid52_fpCosPiTest_q : std_logic_vector (35 downto 0);
signal bigCond_uid85_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal bigCond_uid85_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal bigCond_uid85_fpCosPiTest_c : std_logic_vector(0 downto 0);
signal bigCond_uid85_fpCosPiTest_d : std_logic_vector(0 downto 0);
signal bigCond_uid85_fpCosPiTest_f : std_logic_vector(0 downto 0);
signal bigCond_uid85_fpCosPiTest_g : std_logic_vector(0 downto 0);
signal bigCond_uid85_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal InvCosXIsOne_uid77_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal InvCosXIsOne_uid77_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal InvXEvenInt_uid81_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal InvXEvenInt_uid81_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal InvFxpXFracHalf_uid100_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal InvFxpXFracHalf_uid100_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal cstHalfwSwFP1_uid18_fpCosPiTest_q : std_logic_vector (35 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_notEnable_a : std_logic_vector(0 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_notEnable_q : std_logic_vector(0 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdmux_q : std_logic_vector (1 downto 0);
signal expX_uid6_fpCosPiTest_in : std_logic_vector (30 downto 0);
signal expX_uid6_fpCosPiTest_b : std_logic_vector (7 downto 0);
signal fracX_uid7_fpCosPiTest_in : std_logic_vector (22 downto 0);
signal fracX_uid7_fpCosPiTest_b : std_logic_vector (22 downto 0);
signal expXIsZero_uid23_fpCosPiTest_a : std_logic_vector(7 downto 0);
signal expXIsZero_uid23_fpCosPiTest_b : std_logic_vector(7 downto 0);
signal expXIsZero_uid23_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal expXIsMax_uid25_fpCosPiTest_a : std_logic_vector(7 downto 0);
signal expXIsMax_uid25_fpCosPiTest_b : std_logic_vector(7 downto 0);
signal expXIsMax_uid25_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal fracXIsZero_uid27_fpCosPiTest_a : std_logic_vector(22 downto 0);
signal fracXIsZero_uid27_fpCosPiTest_b : std_logic_vector(22 downto 0);
signal fracXIsZero_uid27_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal exc_I_uid28_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal exc_I_uid28_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal exc_I_uid28_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal xEvenInt_uid35_fpCosPiTest_a : std_logic_vector(10 downto 0);
signal xEvenInt_uid35_fpCosPiTest_b : std_logic_vector(10 downto 0);
signal xEvenInt_uid35_fpCosPiTest_o : std_logic_vector (10 downto 0);
signal xEvenInt_uid35_fpCosPiTest_cin : std_logic_vector (0 downto 0);
signal xEvenInt_uid35_fpCosPiTest_c : std_logic_vector (0 downto 0);
signal cosXIsOne_uid36_fpCosPiTest_a : std_logic_vector(10 downto 0);
signal cosXIsOne_uid36_fpCosPiTest_b : std_logic_vector(10 downto 0);
signal cosXIsOne_uid36_fpCosPiTest_o : std_logic_vector (10 downto 0);
signal cosXIsOne_uid36_fpCosPiTest_cin : std_logic_vector (0 downto 0);
signal cosXIsOne_uid36_fpCosPiTest_c : std_logic_vector (0 downto 0);
signal shiftValFxPX_uid38_fpCosPiTest_a : std_logic_vector(8 downto 0);
signal shiftValFxPX_uid38_fpCosPiTest_b : std_logic_vector(8 downto 0);
signal shiftValFxPX_uid38_fpCosPiTest_o : std_logic_vector (8 downto 0);
signal shiftValFxPX_uid38_fpCosPiTest_q : std_logic_vector (8 downto 0);
signal fxpXFracZero_uid45_fpCosPiTest_a : std_logic_vector(35 downto 0);
signal fxpXFracZero_uid45_fpCosPiTest_b : std_logic_vector(35 downto 0);
signal fxpXFracZero_uid45_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal fxpXFracHalf_uid46_fpCosPiTest_a : std_logic_vector(35 downto 0);
signal fxpXFracHalf_uid46_fpCosPiTest_b : std_logic_vector(35 downto 0);
signal fxpXFracHalf_uid46_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal oMFxpXFrac_uid47_fpCosPiTest_a : std_logic_vector(37 downto 0);
signal oMFxpXFrac_uid47_fpCosPiTest_b : std_logic_vector(37 downto 0);
signal oMFxpXFrac_uid47_fpCosPiTest_o : std_logic_vector (37 downto 0);
signal oMFxpXFrac_uid47_fpCosPiTest_q : std_logic_vector (37 downto 0);
signal z_halfMRRFxPXE_uid52_fpCosPiTest_a : std_logic_vector(36 downto 0);
signal z_halfMRRFxPXE_uid52_fpCosPiTest_b : std_logic_vector(36 downto 0);
signal z_halfMRRFxPXE_uid52_fpCosPiTest_o : std_logic_vector (36 downto 0);
signal z_halfMRRFxPXE_uid52_fpCosPiTest_q : std_logic_vector (36 downto 0);
signal expHardCase_uid59_fpCosPiTest_a : std_logic_vector(8 downto 0);
signal expHardCase_uid59_fpCosPiTest_b : std_logic_vector(8 downto 0);
signal expHardCase_uid59_fpCosPiTest_o : std_logic_vector (8 downto 0);
signal expHardCase_uid59_fpCosPiTest_q : std_logic_vector (8 downto 0);
signal fracZCosNotOne_uid78_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal fracZCosNotOne_uid78_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal fracZCosNotOne_uid78_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal evenIntCosNotOneFZ_uid79_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal evenIntCosNotOneFZ_uid79_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal evenIntCosNotOneFZ_uid79_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal xIsInt_uid80_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal xIsInt_uid80_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal xIsInt_uid80_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal xIsHalf_uid83_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal xIsHalf_uid83_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal xIsHalf_uid83_fpCosPiTest_c : std_logic_vector(0 downto 0);
signal xIsHalf_uid83_fpCosPiTest_d : std_logic_vector(0 downto 0);
signal xIsHalf_uid83_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal fracRPostExc_uid88_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal fracRPostExc_uid88_fpCosPiTest_q : std_logic_vector (22 downto 0);
signal xIntOrXZOrCosOne_uid93_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal xIntOrXZOrCosOne_uid93_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal xIntOrXZOrCosOne_uid93_fpCosPiTest_c : std_logic_vector(0 downto 0);
signal xIntOrXZOrCosOne_uid93_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal expRPostExc_uid95_fpCosPiTest_s : std_logic_vector (1 downto 0);
signal expRPostExc_uid95_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_q : std_logic_vector (36 downto 0);
signal vCount_uid139_lzcZ_uid56_fpCosPiTest_a : std_logic_vector(31 downto 0);
signal vCount_uid139_lzcZ_uid56_fpCosPiTest_b : std_logic_vector(31 downto 0);
signal vCount_uid139_lzcZ_uid56_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid144_lzcZ_uid56_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid144_lzcZ_uid56_fpCosPiTest_q : std_logic_vector (31 downto 0);
signal vCount_uid147_lzcZ_uid56_fpCosPiTest_a : std_logic_vector(15 downto 0);
signal vCount_uid147_lzcZ_uid56_fpCosPiTest_b : std_logic_vector(15 downto 0);
signal vCount_uid147_lzcZ_uid56_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid150_lzcZ_uid56_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid150_lzcZ_uid56_fpCosPiTest_q : std_logic_vector (15 downto 0);
signal vCount_uid159_lzcZ_uid56_fpCosPiTest_a : std_logic_vector(3 downto 0);
signal vCount_uid159_lzcZ_uid56_fpCosPiTest_b : std_logic_vector(3 downto 0);
signal vCount_uid159_lzcZ_uid56_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid162_lzcZ_uid56_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid162_lzcZ_uid56_fpCosPiTest_q : std_logic_vector (3 downto 0);
signal leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_q : std_logic_vector (34 downto 0);
signal memoryC0_uid207_sinPiZTableGenerator_q : std_logic_vector(28 downto 0);
signal memoryC1_uid208_sinPiZTableGenerator_q : std_logic_vector(20 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal leftShiftStage0Idx1_uid177_alignedZ_uid57_fpCosPiTest_q : std_logic_vector (34 downto 0);
signal leftShiftStage0Idx2_uid180_alignedZ_uid57_fpCosPiTest_q : std_logic_vector (34 downto 0);
signal prodXYTruncFR_uid224_mul2xSinRes_uid66_fpCosPiTest_in : std_logic_vector (48 downto 0);
signal prodXYTruncFR_uid224_mul2xSinRes_uid66_fpCosPiTest_b : std_logic_vector (25 downto 0);
signal prodXYTruncFR_uid227_pT1_uid211_sinPiZPolyEval_in : std_logic_vector (27 downto 0);
signal prodXYTruncFR_uid227_pT1_uid211_sinPiZPolyEval_b : std_logic_vector (14 downto 0);
signal prodXYTruncFR_uid230_pT2_uid217_sinPiZPolyEval_in : std_logic_vector (38 downto 0);
signal prodXYTruncFR_uid230_pT2_uid217_sinPiZPolyEval_b : std_logic_vector (23 downto 0);
signal join_uid94_fpCosPiTest_q : std_logic_vector (1 downto 0);
signal R_uid102_fpCosPiTest_q : std_logic_vector (31 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_cmp_a : std_logic_vector(3 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_cmp_b : std_logic_vector(3 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_cmp_a : std_logic_vector(4 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_cmp_b : std_logic_vector(4 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_cmp_a : std_logic_vector(2 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_cmp_b : std_logic_vector(2 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_nor_q : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_nor_q : std_logic_vector(0 downto 0);
signal oFracX_uid37_uid37_fpCosPiTest_q : std_logic_vector (23 downto 0);
signal InvExpXIsZero_uid33_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid33_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid29_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid29_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal InvExc_I_uid32_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal InvExc_I_uid32_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal fxpShifterBits_uid40_fpCosPiTest_in : std_logic_vector (5 downto 0);
signal fxpShifterBits_uid40_fpCosPiTest_b : std_logic_vector (5 downto 0);
signal oMFxpXFrac_uid49_fpCosPiTest_in : std_logic_vector (35 downto 0);
signal oMFxpXFrac_uid49_fpCosPiTest_b : std_logic_vector (35 downto 0);
signal z_uid54_fpCosPiTest_in : std_logic_vector (34 downto 0);
signal z_uid54_fpCosPiTest_b : std_logic_vector (34 downto 0);
signal expP_uid60_fpCosPiTest_in : std_logic_vector (7 downto 0);
signal expP_uid60_fpCosPiTest_b : std_logic_vector (7 downto 0);
signal LeftShiftStage135dto0_uid126_fxpX_uid41_fpCosPiTest_in : std_logic_vector (35 downto 0);
signal LeftShiftStage135dto0_uid126_fxpX_uid41_fpCosPiTest_b : std_logic_vector (35 downto 0);
signal LeftShiftStage134dto0_uid129_fxpX_uid41_fpCosPiTest_in : std_logic_vector (34 downto 0);
signal LeftShiftStage134dto0_uid129_fxpX_uid41_fpCosPiTest_b : std_logic_vector (34 downto 0);
signal LeftShiftStage133dto0_uid132_fxpX_uid41_fpCosPiTest_in : std_logic_vector (33 downto 0);
signal LeftShiftStage133dto0_uid132_fxpX_uid41_fpCosPiTest_b : std_logic_vector (33 downto 0);
signal rVStage_uid146_lzcZ_uid56_fpCosPiTest_in : std_logic_vector (31 downto 0);
signal rVStage_uid146_lzcZ_uid56_fpCosPiTest_b : std_logic_vector (15 downto 0);
signal vStage_uid148_lzcZ_uid56_fpCosPiTest_in : std_logic_vector (15 downto 0);
signal vStage_uid148_lzcZ_uid56_fpCosPiTest_b : std_logic_vector (15 downto 0);
signal rVStage_uid152_lzcZ_uid56_fpCosPiTest_in : std_logic_vector (15 downto 0);
signal rVStage_uid152_lzcZ_uid56_fpCosPiTest_b : std_logic_vector (7 downto 0);
signal vStage_uid154_lzcZ_uid56_fpCosPiTest_in : std_logic_vector (7 downto 0);
signal vStage_uid154_lzcZ_uid56_fpCosPiTest_b : std_logic_vector (7 downto 0);
signal rVStage_uid164_lzcZ_uid56_fpCosPiTest_in : std_logic_vector (3 downto 0);
signal rVStage_uid164_lzcZ_uid56_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal vStage_uid166_lzcZ_uid56_fpCosPiTest_in : std_logic_vector (1 downto 0);
signal vStage_uid166_lzcZ_uid56_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal LeftShiftStage133dto0_uid196_alignedZ_uid57_fpCosPiTest_in : std_logic_vector (33 downto 0);
signal LeftShiftStage133dto0_uid196_alignedZ_uid57_fpCosPiTest_b : std_logic_vector (33 downto 0);
signal LeftShiftStage132dto0_uid199_alignedZ_uid57_fpCosPiTest_in : std_logic_vector (32 downto 0);
signal LeftShiftStage132dto0_uid199_alignedZ_uid57_fpCosPiTest_b : std_logic_vector (32 downto 0);
signal LeftShiftStage131dto0_uid202_alignedZ_uid57_fpCosPiTest_in : std_logic_vector (31 downto 0);
signal LeftShiftStage131dto0_uid202_alignedZ_uid57_fpCosPiTest_b : std_logic_vector (31 downto 0);
signal normBit_uid67_fpCosPiTest_in : std_logic_vector (25 downto 0);
signal normBit_uid67_fpCosPiTest_b : std_logic_vector (0 downto 0);
signal highRes_uid68_fpCosPiTest_in : std_logic_vector (24 downto 0);
signal highRes_uid68_fpCosPiTest_b : std_logic_vector (23 downto 0);
signal lowRes_uid69_fpCosPiTest_in : std_logic_vector (23 downto 0);
signal lowRes_uid69_fpCosPiTest_b : std_logic_vector (23 downto 0);
signal lowRangeB_uid212_sinPiZPolyEval_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid212_sinPiZPolyEval_b : std_logic_vector (0 downto 0);
signal highBBits_uid213_sinPiZPolyEval_in : std_logic_vector (14 downto 0);
signal highBBits_uid213_sinPiZPolyEval_b : std_logic_vector (13 downto 0);
signal lowRangeB_uid218_sinPiZPolyEval_in : std_logic_vector (1 downto 0);
signal lowRangeB_uid218_sinPiZPolyEval_b : std_logic_vector (1 downto 0);
signal highBBits_uid219_sinPiZPolyEval_in : std_logic_vector (23 downto 0);
signal highBBits_uid219_sinPiZPolyEval_b : std_logic_vector (21 downto 0);
signal oFracXExt_uid39_fpCosPiTest_q : std_logic_vector (36 downto 0);
signal exc_N_uid30_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal exc_N_uid30_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal exc_N_uid30_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal leftShiftStageSel5Dto4_uid112_fxpX_uid41_fpCosPiTest_in : std_logic_vector (5 downto 0);
signal leftShiftStageSel5Dto4_uid112_fxpX_uid41_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel3Dto2_uid123_fxpX_uid41_fpCosPiTest_in : std_logic_vector (3 downto 0);
signal leftShiftStageSel3Dto2_uid123_fxpX_uid41_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid134_fxpX_uid41_fpCosPiTest_in : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid134_fxpX_uid41_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal zAddr_uid62_fpCosPiTest_in : std_logic_vector (34 downto 0);
signal zAddr_uid62_fpCosPiTest_b : std_logic_vector (6 downto 0);
signal zPPolyEval_uid63_fpCosPiTest_in : std_logic_vector (27 downto 0);
signal zPPolyEval_uid63_fpCosPiTest_b : std_logic_vector (15 downto 0);
signal rVStage_uid138_lzcZ_uid56_fpCosPiTest_in : std_logic_vector (34 downto 0);
signal rVStage_uid138_lzcZ_uid56_fpCosPiTest_b : std_logic_vector (31 downto 0);
signal vStage_uid141_lzcZ_uid56_fpCosPiTest_in : std_logic_vector (2 downto 0);
signal vStage_uid141_lzcZ_uid56_fpCosPiTest_b : std_logic_vector (2 downto 0);
signal X18dto0_uid176_alignedZ_uid57_fpCosPiTest_in : std_logic_vector (18 downto 0);
signal X18dto0_uid176_alignedZ_uid57_fpCosPiTest_b : std_logic_vector (18 downto 0);
signal leftShiftStage2Idx1_uid127_fxpX_uid41_fpCosPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage2Idx2_uid130_fxpX_uid41_fpCosPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage2Idx3_uid133_fxpX_uid41_fpCosPiTest_q : std_logic_vector (36 downto 0);
signal vCount_uid153_lzcZ_uid56_fpCosPiTest_a : std_logic_vector(7 downto 0);
signal vCount_uid153_lzcZ_uid56_fpCosPiTest_b : std_logic_vector(7 downto 0);
signal vCount_uid153_lzcZ_uid56_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid156_lzcZ_uid56_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid156_lzcZ_uid56_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal vCount_uid165_lzcZ_uid56_fpCosPiTest_a : std_logic_vector(1 downto 0);
signal vCount_uid165_lzcZ_uid56_fpCosPiTest_b : std_logic_vector(1 downto 0);
signal vCount_uid165_lzcZ_uid56_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid168_lzcZ_uid56_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid168_lzcZ_uid56_fpCosPiTest_q : std_logic_vector (1 downto 0);
signal leftShiftStage2Idx1_uid197_alignedZ_uid57_fpCosPiTest_q : std_logic_vector (34 downto 0);
signal leftShiftStage2Idx2_uid200_alignedZ_uid57_fpCosPiTest_q : std_logic_vector (34 downto 0);
signal leftShiftStage2Idx3_uid203_alignedZ_uid57_fpCosPiTest_q : std_logic_vector (34 downto 0);
signal fracRCompPreRnd_uid70_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal fracRCompPreRnd_uid70_fpCosPiTest_q : std_logic_vector (23 downto 0);
signal rndExpUpdate_uid72_uid73_fpCosPiTest_q : std_logic_vector (24 downto 0);
signal sumAHighB_uid214_sinPiZPolyEval_a : std_logic_vector(21 downto 0);
signal sumAHighB_uid214_sinPiZPolyEval_b : std_logic_vector(21 downto 0);
signal sumAHighB_uid214_sinPiZPolyEval_o : std_logic_vector (21 downto 0);
signal sumAHighB_uid214_sinPiZPolyEval_q : std_logic_vector (21 downto 0);
signal sumAHighB_uid220_sinPiZPolyEval_a : std_logic_vector(29 downto 0);
signal sumAHighB_uid220_sinPiZPolyEval_b : std_logic_vector(29 downto 0);
signal sumAHighB_uid220_sinPiZPolyEval_o : std_logic_vector (29 downto 0);
signal sumAHighB_uid220_sinPiZPolyEval_q : std_logic_vector (29 downto 0);
signal X20dto0_uid106_fxpX_uid41_fpCosPiTest_in : std_logic_vector (20 downto 0);
signal X20dto0_uid106_fxpX_uid41_fpCosPiTest_b : std_logic_vector (20 downto 0);
signal X4dto0_uid109_fxpX_uid41_fpCosPiTest_in : std_logic_vector (4 downto 0);
signal X4dto0_uid109_fxpX_uid41_fpCosPiTest_b : std_logic_vector (4 downto 0);
signal InvExc_N_uid31_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal InvExc_N_uid31_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal excRNaN_uid84_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal excRNaN_uid84_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal excRNaN_uid84_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal yT1_uid210_sinPiZPolyEval_in : std_logic_vector (15 downto 0);
signal yT1_uid210_sinPiZPolyEval_b : std_logic_vector (13 downto 0);
signal cStage_uid142_lzcZ_uid56_fpCosPiTest_q : std_logic_vector (31 downto 0);
signal leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest_q : std_logic_vector (36 downto 0);
signal rVStage_uid158_lzcZ_uid56_fpCosPiTest_in : std_logic_vector (7 downto 0);
signal rVStage_uid158_lzcZ_uid56_fpCosPiTest_b : std_logic_vector (3 downto 0);
signal vStage_uid160_lzcZ_uid56_fpCosPiTest_in : std_logic_vector (3 downto 0);
signal vStage_uid160_lzcZ_uid56_fpCosPiTest_b : std_logic_vector (3 downto 0);
signal rVStage_uid170_lzcZ_uid56_fpCosPiTest_in : std_logic_vector (1 downto 0);
signal rVStage_uid170_lzcZ_uid56_fpCosPiTest_b : std_logic_vector (0 downto 0);
signal leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest_q : std_logic_vector (34 downto 0);
signal expFracPreRnd_uid71_uid71_fpCosPiTest_q : std_logic_vector (31 downto 0);
signal expFracComp_uid74_fpCosPiTest_a : std_logic_vector(32 downto 0);
signal expFracComp_uid74_fpCosPiTest_b : std_logic_vector(32 downto 0);
signal expFracComp_uid74_fpCosPiTest_o : std_logic_vector (32 downto 0);
signal expFracComp_uid74_fpCosPiTest_q : std_logic_vector (32 downto 0);
signal s1_uid212_uid215_sinPiZPolyEval_q : std_logic_vector (22 downto 0);
signal s2_uid218_uid221_sinPiZPolyEval_q : std_logic_vector (31 downto 0);
signal leftShiftStage0Idx1_uid107_fxpX_uid41_fpCosPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage0Idx2_uid110_fxpX_uid41_fpCosPiTest_q : std_logic_vector (36 downto 0);
signal exc_R_uid34_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal exc_R_uid34_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal exc_R_uid34_fpCosPiTest_c : std_logic_vector(0 downto 0);
signal exc_R_uid34_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal rInfOrNaN_uid92_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal rInfOrNaN_uid92_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal rInfOrNaN_uid92_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal FxpX36_uid42_fpCosPiTest_in : std_logic_vector (36 downto 0);
signal FxpX36_uid42_fpCosPiTest_b : std_logic_vector (0 downto 0);
signal fxpXFrac_uid43_fpCosPiTest_in : std_logic_vector (35 downto 0);
signal fxpXFrac_uid43_fpCosPiTest_b : std_logic_vector (35 downto 0);
signal vCount_uid171_lzcZ_uid56_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal vCount_uid171_lzcZ_uid56_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal vCount_uid171_lzcZ_uid56_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal alignedZLow_uid58_fpCosPiTest_in : std_logic_vector (34 downto 0);
signal alignedZLow_uid58_fpCosPiTest_b : std_logic_vector (23 downto 0);
signal fracRComp_uid75_fpCosPiTest_in : std_logic_vector (23 downto 0);
signal fracRComp_uid75_fpCosPiTest_b : std_logic_vector (22 downto 0);
signal expRComp_uid76_fpCosPiTest_in : std_logic_vector (31 downto 0);
signal expRComp_uid76_fpCosPiTest_b : std_logic_vector (7 downto 0);
signal fxpSinRes_uid65_fpCosPiTest_in : std_logic_vector (29 downto 0);
signal fxpSinRes_uid65_fpCosPiTest_b : std_logic_vector (24 downto 0);
signal leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_q : std_logic_vector (36 downto 0);
signal FxpXFrac35_uid44_fpCosPiTest_in : std_logic_vector (35 downto 0);
signal FxpXFrac35_uid44_fpCosPiTest_b : std_logic_vector (0 downto 0);
signal r_uid172_lzcZ_uid56_fpCosPiTest_q : std_logic_vector (5 downto 0);
signal LeftShiftStage032dto0_uid115_fxpX_uid41_fpCosPiTest_in : std_logic_vector (32 downto 0);
signal LeftShiftStage032dto0_uid115_fxpX_uid41_fpCosPiTest_b : std_logic_vector (32 downto 0);
signal LeftShiftStage028dto0_uid118_fxpX_uid41_fpCosPiTest_in : std_logic_vector (28 downto 0);
signal LeftShiftStage028dto0_uid118_fxpX_uid41_fpCosPiTest_b : std_logic_vector (28 downto 0);
signal LeftShiftStage024dto0_uid121_fxpX_uid41_fpCosPiTest_in : std_logic_vector (24 downto 0);
signal LeftShiftStage024dto0_uid121_fxpX_uid41_fpCosPiTest_b : std_logic_vector (24 downto 0);
signal xParityXorHalfParity_uid96_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal xParityXorHalfParity_uid96_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal xParityXorHalfParity_uid96_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal leftShiftStageSel5Dto4_uid182_alignedZ_uid57_fpCosPiTest_in : std_logic_vector (5 downto 0);
signal leftShiftStageSel5Dto4_uid182_alignedZ_uid57_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel3Dto2_uid193_alignedZ_uid57_fpCosPiTest_in : std_logic_vector (3 downto 0);
signal leftShiftStageSel3Dto2_uid193_alignedZ_uid57_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid204_alignedZ_uid57_fpCosPiTest_in : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid204_alignedZ_uid57_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStage1Idx1_uid116_fxpX_uid41_fpCosPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage1Idx2_uid119_fxpX_uid41_fpCosPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage1Idx3_uid122_fxpX_uid41_fpCosPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_q : std_logic_vector (34 downto 0);
signal LeftShiftStage030dto0_uid185_alignedZ_uid57_fpCosPiTest_in : std_logic_vector (30 downto 0);
signal LeftShiftStage030dto0_uid185_alignedZ_uid57_fpCosPiTest_b : std_logic_vector (30 downto 0);
signal LeftShiftStage026dto0_uid188_alignedZ_uid57_fpCosPiTest_in : std_logic_vector (26 downto 0);
signal LeftShiftStage026dto0_uid188_alignedZ_uid57_fpCosPiTest_b : std_logic_vector (26 downto 0);
signal LeftShiftStage022dto0_uid191_alignedZ_uid57_fpCosPiTest_in : std_logic_vector (22 downto 0);
signal LeftShiftStage022dto0_uid191_alignedZ_uid57_fpCosPiTest_b : std_logic_vector (22 downto 0);
signal leftShiftStage1Idx1_uid186_alignedZ_uid57_fpCosPiTest_q : std_logic_vector (34 downto 0);
signal leftShiftStage1Idx2_uid189_alignedZ_uid57_fpCosPiTest_q : std_logic_vector (34 downto 0);
signal leftShiftStage1Idx3_uid192_alignedZ_uid57_fpCosPiTest_q : std_logic_vector (34 downto 0);
begin
--xIn(GPIN,3)@0
--LeftShiftStage133dto0_uid132_fxpX_uid41_fpCosPiTest(BITSELECT,131)@1
LeftShiftStage133dto0_uid132_fxpX_uid41_fpCosPiTest_in <= leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_q(33 downto 0);
LeftShiftStage133dto0_uid132_fxpX_uid41_fpCosPiTest_b <= LeftShiftStage133dto0_uid132_fxpX_uid41_fpCosPiTest_in(33 downto 0);
--leftShiftStage2Idx3Pad3_uid131_fxpX_uid41_fpCosPiTest(CONSTANT,130)
leftShiftStage2Idx3Pad3_uid131_fxpX_uid41_fpCosPiTest_q <= "000";
--leftShiftStage2Idx3_uid133_fxpX_uid41_fpCosPiTest(BITJOIN,132)@1
leftShiftStage2Idx3_uid133_fxpX_uid41_fpCosPiTest_q <= LeftShiftStage133dto0_uid132_fxpX_uid41_fpCosPiTest_b & leftShiftStage2Idx3Pad3_uid131_fxpX_uid41_fpCosPiTest_q;
--LeftShiftStage134dto0_uid129_fxpX_uid41_fpCosPiTest(BITSELECT,128)@1
LeftShiftStage134dto0_uid129_fxpX_uid41_fpCosPiTest_in <= leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_q(34 downto 0);
LeftShiftStage134dto0_uid129_fxpX_uid41_fpCosPiTest_b <= LeftShiftStage134dto0_uid129_fxpX_uid41_fpCosPiTest_in(34 downto 0);
--leftShiftStage2Idx2Pad2_uid128_fxpX_uid41_fpCosPiTest(CONSTANT,127)
leftShiftStage2Idx2Pad2_uid128_fxpX_uid41_fpCosPiTest_q <= "00";
--leftShiftStage2Idx2_uid130_fxpX_uid41_fpCosPiTest(BITJOIN,129)@1
leftShiftStage2Idx2_uid130_fxpX_uid41_fpCosPiTest_q <= LeftShiftStage134dto0_uid129_fxpX_uid41_fpCosPiTest_b & leftShiftStage2Idx2Pad2_uid128_fxpX_uid41_fpCosPiTest_q;
--LeftShiftStage135dto0_uid126_fxpX_uid41_fpCosPiTest(BITSELECT,125)@1
LeftShiftStage135dto0_uid126_fxpX_uid41_fpCosPiTest_in <= leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_q(35 downto 0);
LeftShiftStage135dto0_uid126_fxpX_uid41_fpCosPiTest_b <= LeftShiftStage135dto0_uid126_fxpX_uid41_fpCosPiTest_in(35 downto 0);
--GND(CONSTANT,0)
GND_q <= "0";
--leftShiftStage2Idx1_uid127_fxpX_uid41_fpCosPiTest(BITJOIN,126)@1
leftShiftStage2Idx1_uid127_fxpX_uid41_fpCosPiTest_q <= LeftShiftStage135dto0_uid126_fxpX_uid41_fpCosPiTest_b & GND_q;
--leftShiftStage0Idx3_uid111_fxpX_uid41_fpCosPiTest(CONSTANT,110)
leftShiftStage0Idx3_uid111_fxpX_uid41_fpCosPiTest_q <= "0000000000000000000000000000000000000";
--X4dto0_uid109_fxpX_uid41_fpCosPiTest(BITSELECT,108)@0
X4dto0_uid109_fxpX_uid41_fpCosPiTest_in <= oFracXExt_uid39_fpCosPiTest_q(4 downto 0);
X4dto0_uid109_fxpX_uid41_fpCosPiTest_b <= X4dto0_uid109_fxpX_uid41_fpCosPiTest_in(4 downto 0);
--leftShiftStage0Idx2Pad32_uid108_fxpX_uid41_fpCosPiTest(CONSTANT,107)
leftShiftStage0Idx2Pad32_uid108_fxpX_uid41_fpCosPiTest_q <= "00000000000000000000000000000000";
--leftShiftStage0Idx2_uid110_fxpX_uid41_fpCosPiTest(BITJOIN,109)@0
leftShiftStage0Idx2_uid110_fxpX_uid41_fpCosPiTest_q <= X4dto0_uid109_fxpX_uid41_fpCosPiTest_b & leftShiftStage0Idx2Pad32_uid108_fxpX_uid41_fpCosPiTest_q;
--X20dto0_uid106_fxpX_uid41_fpCosPiTest(BITSELECT,105)@0
X20dto0_uid106_fxpX_uid41_fpCosPiTest_in <= oFracXExt_uid39_fpCosPiTest_q(20 downto 0);
X20dto0_uid106_fxpX_uid41_fpCosPiTest_b <= X20dto0_uid106_fxpX_uid41_fpCosPiTest_in(20 downto 0);
--leftShiftStage0Idx1Pad16_uid105_fxpX_uid41_fpCosPiTest(CONSTANT,104)
leftShiftStage0Idx1Pad16_uid105_fxpX_uid41_fpCosPiTest_q <= "0000000000000000";
--leftShiftStage0Idx1_uid107_fxpX_uid41_fpCosPiTest(BITJOIN,106)@0
leftShiftStage0Idx1_uid107_fxpX_uid41_fpCosPiTest_q <= X20dto0_uid106_fxpX_uid41_fpCosPiTest_b & leftShiftStage0Idx1Pad16_uid105_fxpX_uid41_fpCosPiTest_q;
--cst01pWShift_uid14_fpCosPiTest(CONSTANT,13)
cst01pWShift_uid14_fpCosPiTest_q <= "0000000000000";
--VCC(CONSTANT,1)
VCC_q <= "1";
--fracX_uid7_fpCosPiTest(BITSELECT,6)@0
fracX_uid7_fpCosPiTest_in <= a(22 downto 0);
fracX_uid7_fpCosPiTest_b <= fracX_uid7_fpCosPiTest_in(22 downto 0);
--oFracX_uid37_uid37_fpCosPiTest(BITJOIN,36)@0
oFracX_uid37_uid37_fpCosPiTest_q <= VCC_q & fracX_uid7_fpCosPiTest_b;
--oFracXExt_uid39_fpCosPiTest(BITJOIN,38)@0
oFracXExt_uid39_fpCosPiTest_q <= cst01pWShift_uid14_fpCosPiTest_q & oFracX_uid37_uid37_fpCosPiTest_q;
--biasMwShiftMO_uid13_fpCosPiTest(CONSTANT,12)
biasMwShiftMO_uid13_fpCosPiTest_q <= "01110010";
--expX_uid6_fpCosPiTest(BITSELECT,5)@0
expX_uid6_fpCosPiTest_in <= a(30 downto 0);
expX_uid6_fpCosPiTest_b <= expX_uid6_fpCosPiTest_in(30 downto 23);
--shiftValFxPX_uid38_fpCosPiTest(SUB,37)@0
shiftValFxPX_uid38_fpCosPiTest_a <= STD_LOGIC_VECTOR("0" & expX_uid6_fpCosPiTest_b);
shiftValFxPX_uid38_fpCosPiTest_b <= STD_LOGIC_VECTOR("0" & biasMwShiftMO_uid13_fpCosPiTest_q);
shiftValFxPX_uid38_fpCosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(shiftValFxPX_uid38_fpCosPiTest_a) - UNSIGNED(shiftValFxPX_uid38_fpCosPiTest_b));
shiftValFxPX_uid38_fpCosPiTest_q <= shiftValFxPX_uid38_fpCosPiTest_o(8 downto 0);
--fxpShifterBits_uid40_fpCosPiTest(BITSELECT,39)@0
fxpShifterBits_uid40_fpCosPiTest_in <= shiftValFxPX_uid38_fpCosPiTest_q(5 downto 0);
fxpShifterBits_uid40_fpCosPiTest_b <= fxpShifterBits_uid40_fpCosPiTest_in(5 downto 0);
--leftShiftStageSel5Dto4_uid112_fxpX_uid41_fpCosPiTest(BITSELECT,111)@0
leftShiftStageSel5Dto4_uid112_fxpX_uid41_fpCosPiTest_in <= fxpShifterBits_uid40_fpCosPiTest_b;
leftShiftStageSel5Dto4_uid112_fxpX_uid41_fpCosPiTest_b <= leftShiftStageSel5Dto4_uid112_fxpX_uid41_fpCosPiTest_in(5 downto 4);
--leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest(MUX,112)@0
leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_s <= leftShiftStageSel5Dto4_uid112_fxpX_uid41_fpCosPiTest_b;
leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest: PROCESS (leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_s, en, oFracXExt_uid39_fpCosPiTest_q, leftShiftStage0Idx1_uid107_fxpX_uid41_fpCosPiTest_q, leftShiftStage0Idx2_uid110_fxpX_uid41_fpCosPiTest_q, leftShiftStage0Idx3_uid111_fxpX_uid41_fpCosPiTest_q)
BEGIN
CASE leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_s IS
WHEN "00" => leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_q <= oFracXExt_uid39_fpCosPiTest_q;
WHEN "01" => leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_q <= leftShiftStage0Idx1_uid107_fxpX_uid41_fpCosPiTest_q;
WHEN "10" => leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_q <= leftShiftStage0Idx2_uid110_fxpX_uid41_fpCosPiTest_q;
WHEN "11" => leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_q <= leftShiftStage0Idx3_uid111_fxpX_uid41_fpCosPiTest_q;
WHEN OTHERS => leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage024dto0_uid121_fxpX_uid41_fpCosPiTest(BITSELECT,120)@0
LeftShiftStage024dto0_uid121_fxpX_uid41_fpCosPiTest_in <= leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_q(24 downto 0);
LeftShiftStage024dto0_uid121_fxpX_uid41_fpCosPiTest_b <= LeftShiftStage024dto0_uid121_fxpX_uid41_fpCosPiTest_in(24 downto 0);
--leftShiftStage1Idx3Pad12_uid120_fxpX_uid41_fpCosPiTest(CONSTANT,119)
leftShiftStage1Idx3Pad12_uid120_fxpX_uid41_fpCosPiTest_q <= "000000000000";
--leftShiftStage1Idx3_uid122_fxpX_uid41_fpCosPiTest(BITJOIN,121)@0
leftShiftStage1Idx3_uid122_fxpX_uid41_fpCosPiTest_q <= LeftShiftStage024dto0_uid121_fxpX_uid41_fpCosPiTest_b & leftShiftStage1Idx3Pad12_uid120_fxpX_uid41_fpCosPiTest_q;
--reg_leftShiftStage1Idx3_uid122_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_5(REG,235)@0
reg_leftShiftStage1Idx3_uid122_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx3_uid122_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_5_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx3_uid122_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_5_q <= leftShiftStage1Idx3_uid122_fxpX_uid41_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage028dto0_uid118_fxpX_uid41_fpCosPiTest(BITSELECT,117)@0
LeftShiftStage028dto0_uid118_fxpX_uid41_fpCosPiTest_in <= leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_q(28 downto 0);
LeftShiftStage028dto0_uid118_fxpX_uid41_fpCosPiTest_b <= LeftShiftStage028dto0_uid118_fxpX_uid41_fpCosPiTest_in(28 downto 0);
--cstAllZWE_uid21_fpCosPiTest(CONSTANT,20)
cstAllZWE_uid21_fpCosPiTest_q <= "00000000";
--leftShiftStage1Idx2_uid119_fxpX_uid41_fpCosPiTest(BITJOIN,118)@0
leftShiftStage1Idx2_uid119_fxpX_uid41_fpCosPiTest_q <= LeftShiftStage028dto0_uid118_fxpX_uid41_fpCosPiTest_b & cstAllZWE_uid21_fpCosPiTest_q;
--reg_leftShiftStage1Idx2_uid119_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_4(REG,234)@0
reg_leftShiftStage1Idx2_uid119_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx2_uid119_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_4_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx2_uid119_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_4_q <= leftShiftStage1Idx2_uid119_fxpX_uid41_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage032dto0_uid115_fxpX_uid41_fpCosPiTest(BITSELECT,114)@0
LeftShiftStage032dto0_uid115_fxpX_uid41_fpCosPiTest_in <= leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_q(32 downto 0);
LeftShiftStage032dto0_uid115_fxpX_uid41_fpCosPiTest_b <= LeftShiftStage032dto0_uid115_fxpX_uid41_fpCosPiTest_in(32 downto 0);
--leftShiftStage1Idx1Pad4_uid114_fxpX_uid41_fpCosPiTest(CONSTANT,113)
leftShiftStage1Idx1Pad4_uid114_fxpX_uid41_fpCosPiTest_q <= "0000";
--leftShiftStage1Idx1_uid116_fxpX_uid41_fpCosPiTest(BITJOIN,115)@0
leftShiftStage1Idx1_uid116_fxpX_uid41_fpCosPiTest_q <= LeftShiftStage032dto0_uid115_fxpX_uid41_fpCosPiTest_b & leftShiftStage1Idx1Pad4_uid114_fxpX_uid41_fpCosPiTest_q;
--reg_leftShiftStage1Idx1_uid116_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_3(REG,233)@0
reg_leftShiftStage1Idx1_uid116_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx1_uid116_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_3_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx1_uid116_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_3_q <= leftShiftStage1Idx1_uid116_fxpX_uid41_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--reg_leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_2(REG,232)@0
reg_leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_2_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_2_q <= leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel3Dto2_uid123_fxpX_uid41_fpCosPiTest(BITSELECT,122)@0
leftShiftStageSel3Dto2_uid123_fxpX_uid41_fpCosPiTest_in <= fxpShifterBits_uid40_fpCosPiTest_b(3 downto 0);
leftShiftStageSel3Dto2_uid123_fxpX_uid41_fpCosPiTest_b <= leftShiftStageSel3Dto2_uid123_fxpX_uid41_fpCosPiTest_in(3 downto 2);
--reg_leftShiftStageSel3Dto2_uid123_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_1(REG,231)@0
reg_leftShiftStageSel3Dto2_uid123_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel3Dto2_uid123_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel3Dto2_uid123_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_1_q <= leftShiftStageSel3Dto2_uid123_fxpX_uid41_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest(MUX,123)@1
leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_s <= reg_leftShiftStageSel3Dto2_uid123_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_1_q;
leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest: PROCESS (leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_s, en, reg_leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_2_q, reg_leftShiftStage1Idx1_uid116_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_3_q, reg_leftShiftStage1Idx2_uid119_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_4_q, reg_leftShiftStage1Idx3_uid122_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_5_q)
BEGIN
CASE leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_s IS
WHEN "00" => leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_q <= reg_leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_2_q;
WHEN "01" => leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_q <= reg_leftShiftStage1Idx1_uid116_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_3_q;
WHEN "10" => leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_q <= reg_leftShiftStage1Idx2_uid119_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_4_q;
WHEN "11" => leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_q <= reg_leftShiftStage1Idx3_uid122_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_5_q;
WHEN OTHERS => leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--leftShiftStageSel1Dto0_uid134_fxpX_uid41_fpCosPiTest(BITSELECT,133)@0
leftShiftStageSel1Dto0_uid134_fxpX_uid41_fpCosPiTest_in <= fxpShifterBits_uid40_fpCosPiTest_b(1 downto 0);
leftShiftStageSel1Dto0_uid134_fxpX_uid41_fpCosPiTest_b <= leftShiftStageSel1Dto0_uid134_fxpX_uid41_fpCosPiTest_in(1 downto 0);
--reg_leftShiftStageSel1Dto0_uid134_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest_1(REG,236)@0
reg_leftShiftStageSel1Dto0_uid134_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel1Dto0_uid134_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel1Dto0_uid134_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest_1_q <= leftShiftStageSel1Dto0_uid134_fxpX_uid41_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest(MUX,134)@1
leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest_s <= reg_leftShiftStageSel1Dto0_uid134_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest_1_q;
leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest: PROCESS (leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest_s, en, leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_q, leftShiftStage2Idx1_uid127_fxpX_uid41_fpCosPiTest_q, leftShiftStage2Idx2_uid130_fxpX_uid41_fpCosPiTest_q, leftShiftStage2Idx3_uid133_fxpX_uid41_fpCosPiTest_q)
BEGIN
CASE leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest_s IS
WHEN "00" => leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest_q <= leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_q;
WHEN "01" => leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest_q <= leftShiftStage2Idx1_uid127_fxpX_uid41_fpCosPiTest_q;
WHEN "10" => leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest_q <= leftShiftStage2Idx2_uid130_fxpX_uid41_fpCosPiTest_q;
WHEN "11" => leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest_q <= leftShiftStage2Idx3_uid133_fxpX_uid41_fpCosPiTest_q;
WHEN OTHERS => leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--fxpXFrac_uid43_fpCosPiTest(BITSELECT,42)@1
fxpXFrac_uid43_fpCosPiTest_in <= leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest_q(35 downto 0);
fxpXFrac_uid43_fpCosPiTest_b <= fxpXFrac_uid43_fpCosPiTest_in(35 downto 0);
--FxpXFrac35_uid44_fpCosPiTest(BITSELECT,43)@1
FxpXFrac35_uid44_fpCosPiTest_in <= fxpXFrac_uid43_fpCosPiTest_b;
FxpXFrac35_uid44_fpCosPiTest_b <= FxpXFrac35_uid44_fpCosPiTest_in(35 downto 35);
--FxpX36_uid42_fpCosPiTest(BITSELECT,41)@1
FxpX36_uid42_fpCosPiTest_in <= leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest_q;
FxpX36_uid42_fpCosPiTest_b <= FxpX36_uid42_fpCosPiTest_in(36 downto 36);
--xParityXorHalfParity_uid96_fpCosPiTest(LOGICAL,95)@1
xParityXorHalfParity_uid96_fpCosPiTest_a <= FxpX36_uid42_fpCosPiTest_b;
xParityXorHalfParity_uid96_fpCosPiTest_b <= FxpXFrac35_uid44_fpCosPiTest_b;
xParityXorHalfParity_uid96_fpCosPiTest_q <= xParityXorHalfParity_uid96_fpCosPiTest_a xor xParityXorHalfParity_uid96_fpCosPiTest_b;
--ld_xParityXorHalfParity_uid96_fpCosPiTest_q_to_signRComp_uid99_fpCosPiTest_c(DELAY,369)@1
ld_xParityXorHalfParity_uid96_fpCosPiTest_q_to_signRComp_uid99_fpCosPiTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => xParityXorHalfParity_uid96_fpCosPiTest_q, xout => ld_xParityXorHalfParity_uid96_fpCosPiTest_q_to_signRComp_uid99_fpCosPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--cstBiasPwF_uid12_fpCosPiTest(CONSTANT,11)
cstBiasPwF_uid12_fpCosPiTest_q <= "10010110";
--xEvenInt_uid35_fpCosPiTest(COMPARE,34)@0
xEvenInt_uid35_fpCosPiTest_cin <= GND_q;
xEvenInt_uid35_fpCosPiTest_a <= STD_LOGIC_VECTOR("00" & cstBiasPwF_uid12_fpCosPiTest_q) & '0';
xEvenInt_uid35_fpCosPiTest_b <= STD_LOGIC_VECTOR("00" & expX_uid6_fpCosPiTest_b) & xEvenInt_uid35_fpCosPiTest_cin(0);
xEvenInt_uid35_fpCosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(xEvenInt_uid35_fpCosPiTest_a) - UNSIGNED(xEvenInt_uid35_fpCosPiTest_b));
xEvenInt_uid35_fpCosPiTest_c(0) <= xEvenInt_uid35_fpCosPiTest_o(10);
--ld_xEvenInt_uid35_fpCosPiTest_c_to_evenIntCosNotOneFZ_uid79_fpCosPiTest_a(DELAY,335)@0
ld_xEvenInt_uid35_fpCosPiTest_c_to_evenIntCosNotOneFZ_uid79_fpCosPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => xEvenInt_uid35_fpCosPiTest_c, xout => ld_xEvenInt_uid35_fpCosPiTest_c_to_evenIntCosNotOneFZ_uid79_fpCosPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--InvXEvenInt_uid81_fpCosPiTest(LOGICAL,80)@2
InvXEvenInt_uid81_fpCosPiTest_a <= ld_xEvenInt_uid35_fpCosPiTest_c_to_evenIntCosNotOneFZ_uid79_fpCosPiTest_a_q;
InvXEvenInt_uid81_fpCosPiTest_q <= not InvXEvenInt_uid81_fpCosPiTest_a;
--cosXIsOne_uid36_fpCosPiTest(COMPARE,35)@0
cosXIsOne_uid36_fpCosPiTest_cin <= GND_q;
cosXIsOne_uid36_fpCosPiTest_a <= STD_LOGIC_VECTOR("00" & expX_uid6_fpCosPiTest_b) & '0';
cosXIsOne_uid36_fpCosPiTest_b <= STD_LOGIC_VECTOR("00" & biasMwShiftMO_uid13_fpCosPiTest_q) & cosXIsOne_uid36_fpCosPiTest_cin(0);
cosXIsOne_uid36_fpCosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(cosXIsOne_uid36_fpCosPiTest_a) - UNSIGNED(cosXIsOne_uid36_fpCosPiTest_b));
cosXIsOne_uid36_fpCosPiTest_c(0) <= cosXIsOne_uid36_fpCosPiTest_o(10);
--ld_cosXIsOne_uid36_fpCosPiTest_c_to_InvCosXIsOne_uid77_fpCosPiTest_a(DELAY,332)@0
ld_cosXIsOne_uid36_fpCosPiTest_c_to_InvCosXIsOne_uid77_fpCosPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => cosXIsOne_uid36_fpCosPiTest_c, xout => ld_cosXIsOne_uid36_fpCosPiTest_c_to_InvCosXIsOne_uid77_fpCosPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--InvCosXIsOne_uid77_fpCosPiTest(LOGICAL,76)@2
InvCosXIsOne_uid77_fpCosPiTest_a <= ld_cosXIsOne_uid36_fpCosPiTest_c_to_InvCosXIsOne_uid77_fpCosPiTest_a_q;
InvCosXIsOne_uid77_fpCosPiTest_q <= not InvCosXIsOne_uid77_fpCosPiTest_a;
--signRComp_uid99_fpCosPiTest(LOGICAL,98)@2
signRComp_uid99_fpCosPiTest_a <= InvCosXIsOne_uid77_fpCosPiTest_q;
signRComp_uid99_fpCosPiTest_b <= InvXEvenInt_uid81_fpCosPiTest_q;
signRComp_uid99_fpCosPiTest_c <= ld_xParityXorHalfParity_uid96_fpCosPiTest_q_to_signRComp_uid99_fpCosPiTest_c_q;
signRComp_uid99_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
signRComp_uid99_fpCosPiTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1' AND en = "1") THEN
signRComp_uid99_fpCosPiTest_q <= signRComp_uid99_fpCosPiTest_a and signRComp_uid99_fpCosPiTest_b and signRComp_uid99_fpCosPiTest_c;
END IF;
END PROCESS;
--cstZwSwF_uid15_fpCosPiTest(CONSTANT,14)
cstZwSwF_uid15_fpCosPiTest_q <= "00000000000000000000000000000000000";
--cstHalfwSwFP1_uid18_fpCosPiTest(BITJOIN,17)@2
cstHalfwSwFP1_uid18_fpCosPiTest_q <= VCC_q & cstZwSwF_uid15_fpCosPiTest_q;
--reg_fxpXFrac_uid43_fpCosPiTest_0_to_fxpXFracZero_uid45_fpCosPiTest_1(REG,237)@1
reg_fxpXFrac_uid43_fpCosPiTest_0_to_fxpXFracZero_uid45_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fxpXFrac_uid43_fpCosPiTest_0_to_fxpXFracZero_uid45_fpCosPiTest_1_q <= "000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fxpXFrac_uid43_fpCosPiTest_0_to_fxpXFracZero_uid45_fpCosPiTest_1_q <= fxpXFrac_uid43_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--fxpXFracHalf_uid46_fpCosPiTest(LOGICAL,45)@2
fxpXFracHalf_uid46_fpCosPiTest_a <= reg_fxpXFrac_uid43_fpCosPiTest_0_to_fxpXFracZero_uid45_fpCosPiTest_1_q;
fxpXFracHalf_uid46_fpCosPiTest_b <= cstHalfwSwFP1_uid18_fpCosPiTest_q;
fxpXFracHalf_uid46_fpCosPiTest_q <= "1" when fxpXFracHalf_uid46_fpCosPiTest_a = fxpXFracHalf_uid46_fpCosPiTest_b else "0";
--ld_fxpXFracHalf_uid46_fpCosPiTest_q_to_InvFxpXFracHalf_uid100_fpCosPiTest_a(DELAY,370)@2
ld_fxpXFracHalf_uid46_fpCosPiTest_q_to_InvFxpXFracHalf_uid100_fpCosPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => fxpXFracHalf_uid46_fpCosPiTest_q, xout => ld_fxpXFracHalf_uid46_fpCosPiTest_q_to_InvFxpXFracHalf_uid100_fpCosPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--InvFxpXFracHalf_uid100_fpCosPiTest(LOGICAL,99)@3
InvFxpXFracHalf_uid100_fpCosPiTest_a <= ld_fxpXFracHalf_uid46_fpCosPiTest_q_to_InvFxpXFracHalf_uid100_fpCosPiTest_a_q;
InvFxpXFracHalf_uid100_fpCosPiTest_q <= not InvFxpXFracHalf_uid100_fpCosPiTest_a;
--signR_uid101_fpCosPiTest(LOGICAL,100)@3
signR_uid101_fpCosPiTest_a <= InvFxpXFracHalf_uid100_fpCosPiTest_q;
signR_uid101_fpCosPiTest_b <= signRComp_uid99_fpCosPiTest_q;
signR_uid101_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
signR_uid101_fpCosPiTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1' AND en = "1") THEN
signR_uid101_fpCosPiTest_q <= signR_uid101_fpCosPiTest_a and signR_uid101_fpCosPiTest_b;
END IF;
END PROCESS;
--ld_signR_uid101_fpCosPiTest_q_to_R_uid102_fpCosPiTest_c(DELAY,375)@4
ld_signR_uid101_fpCosPiTest_q_to_R_uid102_fpCosPiTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 13 )
PORT MAP ( xin => signR_uid101_fpCosPiTest_q, xout => ld_signR_uid101_fpCosPiTest_q_to_R_uid102_fpCosPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--cstBias_uid10_fpCosPiTest(CONSTANT,9)
cstBias_uid10_fpCosPiTest_q <= "01111111";
--cstAllOWE_uid8_fpCosPiTest(CONSTANT,7)
cstAllOWE_uid8_fpCosPiTest_q <= "11111111";
--pad_o_uid16_uid47_fpCosPiTest(BITJOIN,46)@1
pad_o_uid16_uid47_fpCosPiTest_q <= VCC_q & STD_LOGIC_VECTOR((35 downto 1 => GND_q(0)) & GND_q);
--reg_pad_o_uid16_uid47_fpCosPiTest_0_to_oMFxpXFrac_uid47_fpCosPiTest_0(REG,244)@1
reg_pad_o_uid16_uid47_fpCosPiTest_0_to_oMFxpXFrac_uid47_fpCosPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_o_uid16_uid47_fpCosPiTest_0_to_oMFxpXFrac_uid47_fpCosPiTest_0_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_o_uid16_uid47_fpCosPiTest_0_to_oMFxpXFrac_uid47_fpCosPiTest_0_q <= pad_o_uid16_uid47_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--oMFxpXFrac_uid47_fpCosPiTest(SUB,47)@2
oMFxpXFrac_uid47_fpCosPiTest_a <= STD_LOGIC_VECTOR("0" & reg_pad_o_uid16_uid47_fpCosPiTest_0_to_oMFxpXFrac_uid47_fpCosPiTest_0_q);
oMFxpXFrac_uid47_fpCosPiTest_b <= STD_LOGIC_VECTOR("00" & reg_fxpXFrac_uid43_fpCosPiTest_0_to_fxpXFracZero_uid45_fpCosPiTest_1_q);
oMFxpXFrac_uid47_fpCosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(oMFxpXFrac_uid47_fpCosPiTest_a) - UNSIGNED(oMFxpXFrac_uid47_fpCosPiTest_b));
oMFxpXFrac_uid47_fpCosPiTest_q <= oMFxpXFrac_uid47_fpCosPiTest_o(37 downto 0);
--oMFxpXFrac_uid49_fpCosPiTest(BITSELECT,48)@2
oMFxpXFrac_uid49_fpCosPiTest_in <= oMFxpXFrac_uid47_fpCosPiTest_q(35 downto 0);
oMFxpXFrac_uid49_fpCosPiTest_b <= oMFxpXFrac_uid49_fpCosPiTest_in(35 downto 0);
--ld_fxpXFrac_uid43_fpCosPiTest_b_to_rangeReducedFxPX_uid51_fpCosPiTest_c(DELAY,308)@1
ld_fxpXFrac_uid43_fpCosPiTest_b_to_rangeReducedFxPX_uid51_fpCosPiTest_c : dspba_delay
GENERIC MAP ( width => 36, depth => 1 )
PORT MAP ( xin => fxpXFrac_uid43_fpCosPiTest_b, xout => ld_fxpXFrac_uid43_fpCosPiTest_b_to_rangeReducedFxPX_uid51_fpCosPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--ld_FxpXFrac35_uid44_fpCosPiTest_b_to_rangeReducedFxPX_uid51_fpCosPiTest_b(DELAY,307)@1
ld_FxpXFrac35_uid44_fpCosPiTest_b_to_rangeReducedFxPX_uid51_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => FxpXFrac35_uid44_fpCosPiTest_b, xout => ld_FxpXFrac35_uid44_fpCosPiTest_b_to_rangeReducedFxPX_uid51_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--rangeReducedFxPX_uid51_fpCosPiTest(MUX,50)@2
rangeReducedFxPX_uid51_fpCosPiTest_s <= ld_FxpXFrac35_uid44_fpCosPiTest_b_to_rangeReducedFxPX_uid51_fpCosPiTest_b_q;
rangeReducedFxPX_uid51_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
rangeReducedFxPX_uid51_fpCosPiTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE rangeReducedFxPX_uid51_fpCosPiTest_s IS
WHEN "0" => rangeReducedFxPX_uid51_fpCosPiTest_q <= ld_fxpXFrac_uid43_fpCosPiTest_b_to_rangeReducedFxPX_uid51_fpCosPiTest_c_q;
WHEN "1" => rangeReducedFxPX_uid51_fpCosPiTest_q <= oMFxpXFrac_uid49_fpCosPiTest_b;
WHEN OTHERS => rangeReducedFxPX_uid51_fpCosPiTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--pad_half_uid17_uid52_fpCosPiTest(BITJOIN,51)@2
pad_half_uid17_uid52_fpCosPiTest_q <= VCC_q & STD_LOGIC_VECTOR((34 downto 1 => GND_q(0)) & GND_q);
--reg_pad_half_uid17_uid52_fpCosPiTest_0_to_z_halfMRRFxPXE_uid52_fpCosPiTest_0(REG,246)@2
reg_pad_half_uid17_uid52_fpCosPiTest_0_to_z_halfMRRFxPXE_uid52_fpCosPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_half_uid17_uid52_fpCosPiTest_0_to_z_halfMRRFxPXE_uid52_fpCosPiTest_0_q <= "000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_half_uid17_uid52_fpCosPiTest_0_to_z_halfMRRFxPXE_uid52_fpCosPiTest_0_q <= pad_half_uid17_uid52_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--z_halfMRRFxPXE_uid52_fpCosPiTest(SUB,52)@3
z_halfMRRFxPXE_uid52_fpCosPiTest_a <= STD_LOGIC_VECTOR("0" & reg_pad_half_uid17_uid52_fpCosPiTest_0_to_z_halfMRRFxPXE_uid52_fpCosPiTest_0_q);
z_halfMRRFxPXE_uid52_fpCosPiTest_b <= STD_LOGIC_VECTOR("0" & rangeReducedFxPX_uid51_fpCosPiTest_q);
z_halfMRRFxPXE_uid52_fpCosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(z_halfMRRFxPXE_uid52_fpCosPiTest_a) - UNSIGNED(z_halfMRRFxPXE_uid52_fpCosPiTest_b));
z_halfMRRFxPXE_uid52_fpCosPiTest_q <= z_halfMRRFxPXE_uid52_fpCosPiTest_o(36 downto 0);
--z_uid54_fpCosPiTest(BITSELECT,53)@3
z_uid54_fpCosPiTest_in <= z_halfMRRFxPXE_uid52_fpCosPiTest_q(34 downto 0);
z_uid54_fpCosPiTest_b <= z_uid54_fpCosPiTest_in(34 downto 0);
--zAddr_uid62_fpCosPiTest(BITSELECT,61)@3
zAddr_uid62_fpCosPiTest_in <= z_uid54_fpCosPiTest_b;
zAddr_uid62_fpCosPiTest_b <= zAddr_uid62_fpCosPiTest_in(34 downto 28);
--reg_zAddr_uid62_fpCosPiTest_0_to_memoryC2_uid209_sinPiZTableGenerator_0(REG,263)@3
reg_zAddr_uid62_fpCosPiTest_0_to_memoryC2_uid209_sinPiZTableGenerator_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_zAddr_uid62_fpCosPiTest_0_to_memoryC2_uid209_sinPiZTableGenerator_0_q <= "0000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_zAddr_uid62_fpCosPiTest_0_to_memoryC2_uid209_sinPiZTableGenerator_0_q <= zAddr_uid62_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--memoryC2_uid209_sinPiZTableGenerator(LOOKUP,208)@4
memoryC2_uid209_sinPiZTableGenerator: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
memoryC2_uid209_sinPiZTableGenerator_q <= "10101101010011";
ELSIF (clk'EVENT AND clk = '1' AND en = "1") THEN
CASE (reg_zAddr_uid62_fpCosPiTest_0_to_memoryC2_uid209_sinPiZTableGenerator_0_q) IS
WHEN "0000000" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101101010011";
WHEN "0000001" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101101010100";
WHEN "0000010" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101101010111";
WHEN "0000011" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101101011001";
WHEN "0000100" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101101011011";
WHEN "0000101" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101101011100";
WHEN "0000110" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101101011111";
WHEN "0000111" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101101100010";
WHEN "0001000" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101101100110";
WHEN "0001001" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101101101011";
WHEN "0001010" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101101110000";
WHEN "0001011" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101101110101";
WHEN "0001100" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101101111011";
WHEN "0001101" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101110000000";
WHEN "0001110" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101110000111";
WHEN "0001111" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101110001110";
WHEN "0010000" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101110010011";
WHEN "0010001" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101110011110";
WHEN "0010010" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101110100110";
WHEN "0010011" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101110101111";
WHEN "0010100" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101110111000";
WHEN "0010101" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101111000011";
WHEN "0010110" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101111001100";
WHEN "0010111" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101111010111";
WHEN "0011000" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101111100011";
WHEN "0011001" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101111101110";
WHEN "0011010" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101111111011";
WHEN "0011011" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110000001001";
WHEN "0011100" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110000010101";
WHEN "0011101" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110000100000";
WHEN "0011110" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110000110001";
WHEN "0011111" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110001000000";
WHEN "0100000" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110001001101";
WHEN "0100001" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110001011110";
WHEN "0100010" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110001101100";
WHEN "0100011" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110001111111";
WHEN "0100100" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110010001111";
WHEN "0100101" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110010100001";
WHEN "0100110" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110010110011";
WHEN "0100111" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110011000101";
WHEN "0101000" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110011010110";
WHEN "0101001" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110011101011";
WHEN "0101010" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110011111111";
WHEN "0101011" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110100010010";
WHEN "0101100" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110100100101";
WHEN "0101101" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110100111011";
WHEN "0101110" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110101001110";
WHEN "0101111" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110101100111";
WHEN "0110000" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110101111100";
WHEN "0110001" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110110010010";
WHEN "0110010" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110110100110";
WHEN "0110011" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110111000000";
WHEN "0110100" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110111010101";
WHEN "0110101" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110111110000";
WHEN "0110110" => memoryC2_uid209_sinPiZTableGenerator_q <= "10111000000110";
WHEN "0110111" => memoryC2_uid209_sinPiZTableGenerator_q <= "10111000100010";
WHEN "0111000" => memoryC2_uid209_sinPiZTableGenerator_q <= "10111000111001";
WHEN "0111001" => memoryC2_uid209_sinPiZTableGenerator_q <= "10111001010100";
WHEN "0111010" => memoryC2_uid209_sinPiZTableGenerator_q <= "10111001101111";
WHEN "0111011" => memoryC2_uid209_sinPiZTableGenerator_q <= "10111010001001";
WHEN "0111100" => memoryC2_uid209_sinPiZTableGenerator_q <= "10111010100011";
WHEN "0111101" => memoryC2_uid209_sinPiZTableGenerator_q <= "10111010111100";
WHEN "0111110" => memoryC2_uid209_sinPiZTableGenerator_q <= "10111011011001";
WHEN "0111111" => memoryC2_uid209_sinPiZTableGenerator_q <= "10111011110111";
WHEN "1000000" => memoryC2_uid209_sinPiZTableGenerator_q <= "10111100010100";
WHEN "1000001" => memoryC2_uid209_sinPiZTableGenerator_q <= "10111100110001";
WHEN "1000010" => memoryC2_uid209_sinPiZTableGenerator_q <= "10111101001101";
WHEN "1000011" => memoryC2_uid209_sinPiZTableGenerator_q <= "10111101101010";
WHEN "1000100" => memoryC2_uid209_sinPiZTableGenerator_q <= "10111110001000";
WHEN "1000101" => memoryC2_uid209_sinPiZTableGenerator_q <= "10111110100101";
WHEN "1000110" => memoryC2_uid209_sinPiZTableGenerator_q <= "10111111000101";
WHEN "1000111" => memoryC2_uid209_sinPiZTableGenerator_q <= "10111111100011";
WHEN "1001000" => memoryC2_uid209_sinPiZTableGenerator_q <= "11000000000011";
WHEN "1001001" => memoryC2_uid209_sinPiZTableGenerator_q <= "11000000100011";
WHEN "1001010" => memoryC2_uid209_sinPiZTableGenerator_q <= "11000001000100";
WHEN "1001011" => memoryC2_uid209_sinPiZTableGenerator_q <= "11000001100010";
WHEN "1001100" => memoryC2_uid209_sinPiZTableGenerator_q <= "11000010000100";
WHEN "1001101" => memoryC2_uid209_sinPiZTableGenerator_q <= "11000010100010";
WHEN "1001110" => memoryC2_uid209_sinPiZTableGenerator_q <= "11000011000110";
WHEN "1001111" => memoryC2_uid209_sinPiZTableGenerator_q <= "11000011101000";
WHEN "1010000" => memoryC2_uid209_sinPiZTableGenerator_q <= "11000100001010";
WHEN "1010001" => memoryC2_uid209_sinPiZTableGenerator_q <= "11000100101101";
WHEN "1010010" => memoryC2_uid209_sinPiZTableGenerator_q <= "11000101010001";
WHEN "1010011" => memoryC2_uid209_sinPiZTableGenerator_q <= "11000101110010";
WHEN "1010100" => memoryC2_uid209_sinPiZTableGenerator_q <= "11000110010100";
WHEN "1010101" => memoryC2_uid209_sinPiZTableGenerator_q <= "11000110111011";
WHEN "1010110" => memoryC2_uid209_sinPiZTableGenerator_q <= "11000111011010";
WHEN "1010111" => memoryC2_uid209_sinPiZTableGenerator_q <= "11001000000001";
WHEN "1011000" => memoryC2_uid209_sinPiZTableGenerator_q <= "11001000100110";
WHEN "1011001" => memoryC2_uid209_sinPiZTableGenerator_q <= "11001001001011";
WHEN "1011010" => memoryC2_uid209_sinPiZTableGenerator_q <= "11001001101101";
WHEN "1011011" => memoryC2_uid209_sinPiZTableGenerator_q <= "11001010010101";
WHEN "1011100" => memoryC2_uid209_sinPiZTableGenerator_q <= "11001010111100";
WHEN "1011101" => memoryC2_uid209_sinPiZTableGenerator_q <= "11001011100000";
WHEN "1011110" => memoryC2_uid209_sinPiZTableGenerator_q <= "11001100000101";
WHEN "1011111" => memoryC2_uid209_sinPiZTableGenerator_q <= "11001100101110";
WHEN "1100000" => memoryC2_uid209_sinPiZTableGenerator_q <= "11001101010100";
WHEN "1100001" => memoryC2_uid209_sinPiZTableGenerator_q <= "11001101111010";
WHEN "1100010" => memoryC2_uid209_sinPiZTableGenerator_q <= "11001110100010";
WHEN "1100011" => memoryC2_uid209_sinPiZTableGenerator_q <= "11001111001001";
WHEN "1100100" => memoryC2_uid209_sinPiZTableGenerator_q <= "11001111110001";
WHEN "1100101" => memoryC2_uid209_sinPiZTableGenerator_q <= "11010000010110";
WHEN "1100110" => memoryC2_uid209_sinPiZTableGenerator_q <= "11010000111111";
WHEN "1100111" => memoryC2_uid209_sinPiZTableGenerator_q <= "11010001101001";
WHEN "1101000" => memoryC2_uid209_sinPiZTableGenerator_q <= "11010010010010";
WHEN "1101001" => memoryC2_uid209_sinPiZTableGenerator_q <= "11010010111101";
WHEN "1101010" => memoryC2_uid209_sinPiZTableGenerator_q <= "11010011100001";
WHEN "1101011" => memoryC2_uid209_sinPiZTableGenerator_q <= "11010100001100";
WHEN "1101100" => memoryC2_uid209_sinPiZTableGenerator_q <= "11010100110111";
WHEN "1101101" => memoryC2_uid209_sinPiZTableGenerator_q <= "11010101100001";
WHEN "1101110" => memoryC2_uid209_sinPiZTableGenerator_q <= "11010110001011";
WHEN "1101111" => memoryC2_uid209_sinPiZTableGenerator_q <= "11010110110011";
WHEN "1110000" => memoryC2_uid209_sinPiZTableGenerator_q <= "11010111011111";
WHEN "1110001" => memoryC2_uid209_sinPiZTableGenerator_q <= "11011000001010";
WHEN "1110010" => memoryC2_uid209_sinPiZTableGenerator_q <= "11011000110100";
WHEN "1110011" => memoryC2_uid209_sinPiZTableGenerator_q <= "11011001011111";
WHEN "1110100" => memoryC2_uid209_sinPiZTableGenerator_q <= "11011010001010";
WHEN "1110101" => memoryC2_uid209_sinPiZTableGenerator_q <= "11011010110110";
WHEN "1110110" => memoryC2_uid209_sinPiZTableGenerator_q <= "11011011100011";
WHEN "1110111" => memoryC2_uid209_sinPiZTableGenerator_q <= "11011100001111";
WHEN "1111000" => memoryC2_uid209_sinPiZTableGenerator_q <= "11011100111001";
WHEN "1111001" => memoryC2_uid209_sinPiZTableGenerator_q <= "11011101100011";
WHEN "1111010" => memoryC2_uid209_sinPiZTableGenerator_q <= "11011110010001";
WHEN "1111011" => memoryC2_uid209_sinPiZTableGenerator_q <= "11011110111011";
WHEN "1111100" => memoryC2_uid209_sinPiZTableGenerator_q <= "11011111101000";
WHEN "1111101" => memoryC2_uid209_sinPiZTableGenerator_q <= "11100000010101";
WHEN "1111110" => memoryC2_uid209_sinPiZTableGenerator_q <= "11100001000010";
WHEN "1111111" => memoryC2_uid209_sinPiZTableGenerator_q <= "11100001110000";
WHEN OTHERS =>
memoryC2_uid209_sinPiZTableGenerator_q <= (others => '-');
END CASE;
END IF;
END PROCESS;
--zPPolyEval_uid63_fpCosPiTest(BITSELECT,62)@3
zPPolyEval_uid63_fpCosPiTest_in <= z_uid54_fpCosPiTest_b(27 downto 0);
zPPolyEval_uid63_fpCosPiTest_b <= zPPolyEval_uid63_fpCosPiTest_in(27 downto 12);
--yT1_uid210_sinPiZPolyEval(BITSELECT,209)@3
yT1_uid210_sinPiZPolyEval_in <= zPPolyEval_uid63_fpCosPiTest_b;
yT1_uid210_sinPiZPolyEval_b <= yT1_uid210_sinPiZPolyEval_in(15 downto 2);
--reg_yT1_uid210_sinPiZPolyEval_0_to_prodXY_uid226_pT1_uid211_sinPiZPolyEval_0(REG,264)@3
reg_yT1_uid210_sinPiZPolyEval_0_to_prodXY_uid226_pT1_uid211_sinPiZPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT1_uid210_sinPiZPolyEval_0_to_prodXY_uid226_pT1_uid211_sinPiZPolyEval_0_q <= "00000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT1_uid210_sinPiZPolyEval_0_to_prodXY_uid226_pT1_uid211_sinPiZPolyEval_0_q <= yT1_uid210_sinPiZPolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_reg_yT1_uid210_sinPiZPolyEval_0_to_prodXY_uid226_pT1_uid211_sinPiZPolyEval_0_q_to_prodXY_uid226_pT1_uid211_sinPiZPolyEval_a(DELAY,499)@4
ld_reg_yT1_uid210_sinPiZPolyEval_0_to_prodXY_uid226_pT1_uid211_sinPiZPolyEval_0_q_to_prodXY_uid226_pT1_uid211_sinPiZPolyEval_a : dspba_delay
GENERIC MAP ( width => 14, depth => 1 )
PORT MAP ( xin => reg_yT1_uid210_sinPiZPolyEval_0_to_prodXY_uid226_pT1_uid211_sinPiZPolyEval_0_q, xout => ld_reg_yT1_uid210_sinPiZPolyEval_0_to_prodXY_uid226_pT1_uid211_sinPiZPolyEval_0_q_to_prodXY_uid226_pT1_uid211_sinPiZPolyEval_a_q, ena => en(0), clk => clk, aclr => areset );
--prodXY_uid226_pT1_uid211_sinPiZPolyEval(MULT,225)@5
prodXY_uid226_pT1_uid211_sinPiZPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid226_pT1_uid211_sinPiZPolyEval_a),15)) * SIGNED(prodXY_uid226_pT1_uid211_sinPiZPolyEval_b);
prodXY_uid226_pT1_uid211_sinPiZPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid226_pT1_uid211_sinPiZPolyEval_a <= (others => '0');
prodXY_uid226_pT1_uid211_sinPiZPolyEval_b <= (others => '0');
prodXY_uid226_pT1_uid211_sinPiZPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid226_pT1_uid211_sinPiZPolyEval_a <= ld_reg_yT1_uid210_sinPiZPolyEval_0_to_prodXY_uid226_pT1_uid211_sinPiZPolyEval_0_q_to_prodXY_uid226_pT1_uid211_sinPiZPolyEval_a_q;
prodXY_uid226_pT1_uid211_sinPiZPolyEval_b <= memoryC2_uid209_sinPiZTableGenerator_q;
prodXY_uid226_pT1_uid211_sinPiZPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid226_pT1_uid211_sinPiZPolyEval_pr,28));
END IF;
END IF;
END PROCESS;
prodXY_uid226_pT1_uid211_sinPiZPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid226_pT1_uid211_sinPiZPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid226_pT1_uid211_sinPiZPolyEval_q <= prodXY_uid226_pT1_uid211_sinPiZPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid227_pT1_uid211_sinPiZPolyEval(BITSELECT,226)@8
prodXYTruncFR_uid227_pT1_uid211_sinPiZPolyEval_in <= prodXY_uid226_pT1_uid211_sinPiZPolyEval_q;
prodXYTruncFR_uid227_pT1_uid211_sinPiZPolyEval_b <= prodXYTruncFR_uid227_pT1_uid211_sinPiZPolyEval_in(27 downto 13);
--highBBits_uid213_sinPiZPolyEval(BITSELECT,212)@8
highBBits_uid213_sinPiZPolyEval_in <= prodXYTruncFR_uid227_pT1_uid211_sinPiZPolyEval_b;
highBBits_uid213_sinPiZPolyEval_b <= highBBits_uid213_sinPiZPolyEval_in(14 downto 1);
--ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_notEnable(LOGICAL,557)
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_notEnable_a <= en;
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_notEnable_q <= not ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_notEnable_a;
--ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_nor(LOGICAL,596)
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_nor_a <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_notEnable_q;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_nor_b <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_sticky_ena_q;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_nor_q <= not (ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_nor_a or ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_nor_b);
--ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_mem_top(CONSTANT,592)
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_mem_top_q <= "010";
--ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_cmp(LOGICAL,593)
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_cmp_a <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_mem_top_q;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdmux_q);
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_cmp_q <= "1" when ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_cmp_a = ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_cmp_b else "0";
--ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_cmpReg(REG,594)
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_cmpReg_q <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_sticky_ena(REG,597)
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_nor_q = "1") THEN
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_sticky_ena_q <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_enaAnd(LOGICAL,598)
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_enaAnd_a <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_sticky_ena_q;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_enaAnd_b <= en;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_enaAnd_q <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_enaAnd_a and ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_enaAnd_b;
--ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt(COUNTER,588)
-- every=1, low=0, high=2, step=1, init=1
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt_i <= TO_UNSIGNED(1,2);
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt_i = 1 THEN
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt_eq = '1') THEN
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt_i <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt_i - 2;
ELSE
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt_i <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt_i,2));
--ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdreg(REG,589)
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdreg_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdreg_q <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdmux(MUX,590)
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdmux_s <= en;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdmux: PROCESS (ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdmux_s, ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdreg_q, ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdmux_s IS
WHEN "0" => ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdmux_q <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdreg_q;
WHEN "1" => ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdmux_q <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem(DUALMEM,587)
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_reset0 <= areset;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_ia <= reg_zAddr_uid62_fpCosPiTest_0_to_memoryC2_uid209_sinPiZTableGenerator_0_q;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_aa <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdreg_q;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_ab <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdmux_q;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 7,
widthad_a => 2,
numwords_a => 3,
width_b => 7,
widthad_b => 2,
numwords_b => 3,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_iq,
address_a => ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_aa,
data_a => ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_ia
);
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_q <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_iq(6 downto 0);
--memoryC1_uid208_sinPiZTableGenerator(LOOKUP,207)@8
memoryC1_uid208_sinPiZTableGenerator: PROCESS (ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_q)
BEGIN
-- Begin reserved scope level
CASE (ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_q) IS
WHEN "0000000" => memoryC1_uid208_sinPiZTableGenerator_q <= "000000000000000000001";
WHEN "0000001" => memoryC1_uid208_sinPiZTableGenerator_q <= "111111101011010101010";
WHEN "0000010" => memoryC1_uid208_sinPiZTableGenerator_q <= "111111010110101010001";
WHEN "0000011" => memoryC1_uid208_sinPiZTableGenerator_q <= "111111000001111111100";
WHEN "0000100" => memoryC1_uid208_sinPiZTableGenerator_q <= "111110101101010101010";
WHEN "0000101" => memoryC1_uid208_sinPiZTableGenerator_q <= "111110011000101011101";
WHEN "0000110" => memoryC1_uid208_sinPiZTableGenerator_q <= "111110000100000010101";
WHEN "0000111" => memoryC1_uid208_sinPiZTableGenerator_q <= "111101101111011010001";
WHEN "0001000" => memoryC1_uid208_sinPiZTableGenerator_q <= "111101011010110010101";
WHEN "0001001" => memoryC1_uid208_sinPiZTableGenerator_q <= "111101000110001011111";
WHEN "0001010" => memoryC1_uid208_sinPiZTableGenerator_q <= "111100110001100110010";
WHEN "0001011" => memoryC1_uid208_sinPiZTableGenerator_q <= "111100011101000010000";
WHEN "0001100" => memoryC1_uid208_sinPiZTableGenerator_q <= "111100001000011110111";
WHEN "0001101" => memoryC1_uid208_sinPiZTableGenerator_q <= "111011110011111101011";
WHEN "0001110" => memoryC1_uid208_sinPiZTableGenerator_q <= "111011011111011101011";
WHEN "0001111" => memoryC1_uid208_sinPiZTableGenerator_q <= "111011001010111110111";
WHEN "0010000" => memoryC1_uid208_sinPiZTableGenerator_q <= "111010110110100010101";
WHEN "0010001" => memoryC1_uid208_sinPiZTableGenerator_q <= "111010100010000111100";
WHEN "0010010" => memoryC1_uid208_sinPiZTableGenerator_q <= "111010001101101111000";
WHEN "0010011" => memoryC1_uid208_sinPiZTableGenerator_q <= "111001111001011000011";
WHEN "0010100" => memoryC1_uid208_sinPiZTableGenerator_q <= "111001100101000100010";
WHEN "0010101" => memoryC1_uid208_sinPiZTableGenerator_q <= "111001010000110010001";
WHEN "0010110" => memoryC1_uid208_sinPiZTableGenerator_q <= "111000111100100010111";
WHEN "0010111" => memoryC1_uid208_sinPiZTableGenerator_q <= "111000101000010110001";
WHEN "0011000" => memoryC1_uid208_sinPiZTableGenerator_q <= "111000010100001011111";
WHEN "0011001" => memoryC1_uid208_sinPiZTableGenerator_q <= "111000000000000100110";
WHEN "0011010" => memoryC1_uid208_sinPiZTableGenerator_q <= "110111101100000000011";
WHEN "0011011" => memoryC1_uid208_sinPiZTableGenerator_q <= "110111010111111111000";
WHEN "0011100" => memoryC1_uid208_sinPiZTableGenerator_q <= "110111000100000001000";
WHEN "0011101" => memoryC1_uid208_sinPiZTableGenerator_q <= "110110110000000110101";
WHEN "0011110" => memoryC1_uid208_sinPiZTableGenerator_q <= "110110011100001110111";
WHEN "0011111" => memoryC1_uid208_sinPiZTableGenerator_q <= "110110001000011011000";
WHEN "0100000" => memoryC1_uid208_sinPiZTableGenerator_q <= "110101110100101011010";
WHEN "0100001" => memoryC1_uid208_sinPiZTableGenerator_q <= "110101100000111110101";
WHEN "0100010" => memoryC1_uid208_sinPiZTableGenerator_q <= "110101001101010110010";
WHEN "0100011" => memoryC1_uid208_sinPiZTableGenerator_q <= "110100111001110001011";
WHEN "0100100" => memoryC1_uid208_sinPiZTableGenerator_q <= "110100100110010001001";
WHEN "0100101" => memoryC1_uid208_sinPiZTableGenerator_q <= "110100010010110100110";
WHEN "0100110" => memoryC1_uid208_sinPiZTableGenerator_q <= "110011111111011100110";
WHEN "0100111" => memoryC1_uid208_sinPiZTableGenerator_q <= "110011101100001001010";
WHEN "0101000" => memoryC1_uid208_sinPiZTableGenerator_q <= "110011011000111010011";
WHEN "0101001" => memoryC1_uid208_sinPiZTableGenerator_q <= "110011000101101111111";
WHEN "0101010" => memoryC1_uid208_sinPiZTableGenerator_q <= "110010110010101010010";
WHEN "0101011" => memoryC1_uid208_sinPiZTableGenerator_q <= "110010011111101001101";
WHEN "0101100" => memoryC1_uid208_sinPiZTableGenerator_q <= "110010001100101110000";
WHEN "0101101" => memoryC1_uid208_sinPiZTableGenerator_q <= "110001111001110111001";
WHEN "0101110" => memoryC1_uid208_sinPiZTableGenerator_q <= "110001100111000110000";
WHEN "0101111" => memoryC1_uid208_sinPiZTableGenerator_q <= "110001010100011001011";
WHEN "0110000" => memoryC1_uid208_sinPiZTableGenerator_q <= "110001000001110010110";
WHEN "0110001" => memoryC1_uid208_sinPiZTableGenerator_q <= "110000101111010001100";
WHEN "0110010" => memoryC1_uid208_sinPiZTableGenerator_q <= "110000011100110110001";
WHEN "0110011" => memoryC1_uid208_sinPiZTableGenerator_q <= "110000001010011111111";
WHEN "0110100" => memoryC1_uid208_sinPiZTableGenerator_q <= "101111111000010000000";
WHEN "0110101" => memoryC1_uid208_sinPiZTableGenerator_q <= "101111100110000101100";
WHEN "0110110" => memoryC1_uid208_sinPiZTableGenerator_q <= "101111010100000001100";
WHEN "0110111" => memoryC1_uid208_sinPiZTableGenerator_q <= "101111000010000011001";
WHEN "0111000" => memoryC1_uid208_sinPiZTableGenerator_q <= "101110110000001011100";
WHEN "0111001" => memoryC1_uid208_sinPiZTableGenerator_q <= "101110011110011001110";
WHEN "0111010" => memoryC1_uid208_sinPiZTableGenerator_q <= "101110001100101110101";
WHEN "0111011" => memoryC1_uid208_sinPiZTableGenerator_q <= "101101111011001010001";
WHEN "0111100" => memoryC1_uid208_sinPiZTableGenerator_q <= "101101101001101100010";
WHEN "0111101" => memoryC1_uid208_sinPiZTableGenerator_q <= "101101011000010101010";
WHEN "0111110" => memoryC1_uid208_sinPiZTableGenerator_q <= "101101000111000100101";
WHEN "0111111" => memoryC1_uid208_sinPiZTableGenerator_q <= "101100110101111010111";
WHEN "1000000" => memoryC1_uid208_sinPiZTableGenerator_q <= "101100100100111000010";
WHEN "1000001" => memoryC1_uid208_sinPiZTableGenerator_q <= "101100010011111100111";
WHEN "1000010" => memoryC1_uid208_sinPiZTableGenerator_q <= "101100000011001000111";
WHEN "1000011" => memoryC1_uid208_sinPiZTableGenerator_q <= "101011110010011100000";
WHEN "1000100" => memoryC1_uid208_sinPiZTableGenerator_q <= "101011100001110110100";
WHEN "1000101" => memoryC1_uid208_sinPiZTableGenerator_q <= "101011010001011000100";
WHEN "1000110" => memoryC1_uid208_sinPiZTableGenerator_q <= "101011000001000001110";
WHEN "1000111" => memoryC1_uid208_sinPiZTableGenerator_q <= "101010110000110011000";
WHEN "1001000" => memoryC1_uid208_sinPiZTableGenerator_q <= "101010100000101011111";
WHEN "1001001" => memoryC1_uid208_sinPiZTableGenerator_q <= "101010010000101100100";
WHEN "1001010" => memoryC1_uid208_sinPiZTableGenerator_q <= "101010000000110101001";
WHEN "1001011" => memoryC1_uid208_sinPiZTableGenerator_q <= "101001110001000110000";
WHEN "1001100" => memoryC1_uid208_sinPiZTableGenerator_q <= "101001100001011110101";
WHEN "1001101" => memoryC1_uid208_sinPiZTableGenerator_q <= "101001010001111111111";
WHEN "1001110" => memoryC1_uid208_sinPiZTableGenerator_q <= "101001000010101000110";
WHEN "1001111" => memoryC1_uid208_sinPiZTableGenerator_q <= "101000110011011010001";
WHEN "1010000" => memoryC1_uid208_sinPiZTableGenerator_q <= "101000100100010100001";
WHEN "1010001" => memoryC1_uid208_sinPiZTableGenerator_q <= "101000010101010110100";
WHEN "1010010" => memoryC1_uid208_sinPiZTableGenerator_q <= "101000000110100001011";
WHEN "1010011" => memoryC1_uid208_sinPiZTableGenerator_q <= "100111110111110101011";
WHEN "1010100" => memoryC1_uid208_sinPiZTableGenerator_q <= "100111101001010010000";
WHEN "1010101" => memoryC1_uid208_sinPiZTableGenerator_q <= "100111011010110110110";
WHEN "1010110" => memoryC1_uid208_sinPiZTableGenerator_q <= "100111001100100101100";
WHEN "1010111" => memoryC1_uid208_sinPiZTableGenerator_q <= "100110111110011100011";
WHEN "1011000" => memoryC1_uid208_sinPiZTableGenerator_q <= "100110110000011100011";
WHEN "1011001" => memoryC1_uid208_sinPiZTableGenerator_q <= "100110100010100101110";
WHEN "1011010" => memoryC1_uid208_sinPiZTableGenerator_q <= "100110010100111000101";
WHEN "1011011" => memoryC1_uid208_sinPiZTableGenerator_q <= "100110000111010100001";
WHEN "1011100" => memoryC1_uid208_sinPiZTableGenerator_q <= "100101111001111001000";
WHEN "1011101" => memoryC1_uid208_sinPiZTableGenerator_q <= "100101101100100111111";
WHEN "1011110" => memoryC1_uid208_sinPiZTableGenerator_q <= "100101011111100000000";
WHEN "1011111" => memoryC1_uid208_sinPiZTableGenerator_q <= "100101010010100001001";
WHEN "1100000" => memoryC1_uid208_sinPiZTableGenerator_q <= "100101000101101100011";
WHEN "1100001" => memoryC1_uid208_sinPiZTableGenerator_q <= "100100111001000001011";
WHEN "1100010" => memoryC1_uid208_sinPiZTableGenerator_q <= "100100101100011111111";
WHEN "1100011" => memoryC1_uid208_sinPiZTableGenerator_q <= "100100100000001000010";
WHEN "1100100" => memoryC1_uid208_sinPiZTableGenerator_q <= "100100010011111010101";
WHEN "1100101" => memoryC1_uid208_sinPiZTableGenerator_q <= "100100000111110111001";
WHEN "1100110" => memoryC1_uid208_sinPiZTableGenerator_q <= "100011111011111101010";
WHEN "1100111" => memoryC1_uid208_sinPiZTableGenerator_q <= "100011110000001101010";
WHEN "1101000" => memoryC1_uid208_sinPiZTableGenerator_q <= "100011100100100111101";
WHEN "1101001" => memoryC1_uid208_sinPiZTableGenerator_q <= "100011011001001011111";
WHEN "1101010" => memoryC1_uid208_sinPiZTableGenerator_q <= "100011001101111011010";
WHEN "1101011" => memoryC1_uid208_sinPiZTableGenerator_q <= "100011000010110100001";
WHEN "1101100" => memoryC1_uid208_sinPiZTableGenerator_q <= "100010110111110111010";
WHEN "1101101" => memoryC1_uid208_sinPiZTableGenerator_q <= "100010101101000101000";
WHEN "1101110" => memoryC1_uid208_sinPiZTableGenerator_q <= "100010100010011101001";
WHEN "1101111" => memoryC1_uid208_sinPiZTableGenerator_q <= "100010011000000000001";
WHEN "1110000" => memoryC1_uid208_sinPiZTableGenerator_q <= "100010001101101101010";
WHEN "1110001" => memoryC1_uid208_sinPiZTableGenerator_q <= "100010000011100100111";
WHEN "1110010" => memoryC1_uid208_sinPiZTableGenerator_q <= "100001111001100111100";
WHEN "1110011" => memoryC1_uid208_sinPiZTableGenerator_q <= "100001101111110100101";
WHEN "1110100" => memoryC1_uid208_sinPiZTableGenerator_q <= "100001100110001100100";
WHEN "1110101" => memoryC1_uid208_sinPiZTableGenerator_q <= "100001011100101111001";
WHEN "1110110" => memoryC1_uid208_sinPiZTableGenerator_q <= "100001010011011100011";
WHEN "1110111" => memoryC1_uid208_sinPiZTableGenerator_q <= "100001001010010100101";
WHEN "1111000" => memoryC1_uid208_sinPiZTableGenerator_q <= "100001000001011000000";
WHEN "1111001" => memoryC1_uid208_sinPiZTableGenerator_q <= "100000111000100110100";
WHEN "1111010" => memoryC1_uid208_sinPiZTableGenerator_q <= "100000101111111111100";
WHEN "1111011" => memoryC1_uid208_sinPiZTableGenerator_q <= "100000100111100011111";
WHEN "1111100" => memoryC1_uid208_sinPiZTableGenerator_q <= "100000011111010011000";
WHEN "1111101" => memoryC1_uid208_sinPiZTableGenerator_q <= "100000010111001101010";
WHEN "1111110" => memoryC1_uid208_sinPiZTableGenerator_q <= "100000001111010010101";
WHEN "1111111" => memoryC1_uid208_sinPiZTableGenerator_q <= "100000000111100011001";
WHEN OTHERS =>
memoryC1_uid208_sinPiZTableGenerator_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--sumAHighB_uid214_sinPiZPolyEval(ADD,213)@8
sumAHighB_uid214_sinPiZPolyEval_a <= STD_LOGIC_VECTOR((21 downto 21 => memoryC1_uid208_sinPiZTableGenerator_q(20)) & memoryC1_uid208_sinPiZTableGenerator_q);
sumAHighB_uid214_sinPiZPolyEval_b <= STD_LOGIC_VECTOR((21 downto 14 => highBBits_uid213_sinPiZPolyEval_b(13)) & highBBits_uid213_sinPiZPolyEval_b);
sumAHighB_uid214_sinPiZPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid214_sinPiZPolyEval_a) + SIGNED(sumAHighB_uid214_sinPiZPolyEval_b));
sumAHighB_uid214_sinPiZPolyEval_q <= sumAHighB_uid214_sinPiZPolyEval_o(21 downto 0);
--lowRangeB_uid212_sinPiZPolyEval(BITSELECT,211)@8
lowRangeB_uid212_sinPiZPolyEval_in <= prodXYTruncFR_uid227_pT1_uid211_sinPiZPolyEval_b(0 downto 0);
lowRangeB_uid212_sinPiZPolyEval_b <= lowRangeB_uid212_sinPiZPolyEval_in(0 downto 0);
--s1_uid212_uid215_sinPiZPolyEval(BITJOIN,214)@8
s1_uid212_uid215_sinPiZPolyEval_q <= sumAHighB_uid214_sinPiZPolyEval_q & lowRangeB_uid212_sinPiZPolyEval_b;
--reg_s1_uid212_uid215_sinPiZPolyEval_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_1(REG,267)@8
reg_s1_uid212_uid215_sinPiZPolyEval_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_s1_uid212_uid215_sinPiZPolyEval_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_1_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_s1_uid212_uid215_sinPiZPolyEval_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_1_q <= s1_uid212_uid215_sinPiZPolyEval_q;
END IF;
END IF;
END PROCESS;
--ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_nor(LOGICAL,609)
ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_nor_a <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_notEnable_q;
ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_nor_b <= ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_sticky_ena_q;
ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_nor_q <= not (ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_nor_a or ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_nor_b);
--ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_sticky_ena(REG,610)
ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_nor_q = "1") THEN
ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_sticky_ena_q <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_enaAnd(LOGICAL,611)
ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_enaAnd_a <= ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_sticky_ena_q;
ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_enaAnd_b <= en;
ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_enaAnd_q <= ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_enaAnd_a and ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_enaAnd_b;
--ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_inputreg(DELAY,599)
ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 16, depth => 1 )
PORT MAP ( xin => zPPolyEval_uid63_fpCosPiTest_b, xout => ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem(DUALMEM,600)
ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_reset0 <= areset;
ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_ia <= ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_inputreg_q;
ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_aa <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdreg_q;
ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_ab <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdmux_q;
ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 16,
widthad_a => 2,
numwords_a => 3,
width_b => 16,
widthad_b => 2,
numwords_b => 3,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_iq,
address_a => ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_aa,
data_a => ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_ia
);
ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_q <= ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_iq(15 downto 0);
--reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0(REG,266)@8
reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_q <= ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--prodXY_uid229_pT2_uid217_sinPiZPolyEval(MULT,228)@9
prodXY_uid229_pT2_uid217_sinPiZPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid229_pT2_uid217_sinPiZPolyEval_a),17)) * SIGNED(prodXY_uid229_pT2_uid217_sinPiZPolyEval_b);
prodXY_uid229_pT2_uid217_sinPiZPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid229_pT2_uid217_sinPiZPolyEval_a <= (others => '0');
prodXY_uid229_pT2_uid217_sinPiZPolyEval_b <= (others => '0');
prodXY_uid229_pT2_uid217_sinPiZPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid229_pT2_uid217_sinPiZPolyEval_a <= reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_q;
prodXY_uid229_pT2_uid217_sinPiZPolyEval_b <= reg_s1_uid212_uid215_sinPiZPolyEval_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_1_q;
prodXY_uid229_pT2_uid217_sinPiZPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid229_pT2_uid217_sinPiZPolyEval_pr,39));
END IF;
END IF;
END PROCESS;
prodXY_uid229_pT2_uid217_sinPiZPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid229_pT2_uid217_sinPiZPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid229_pT2_uid217_sinPiZPolyEval_q <= prodXY_uid229_pT2_uid217_sinPiZPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid230_pT2_uid217_sinPiZPolyEval(BITSELECT,229)@12
prodXYTruncFR_uid230_pT2_uid217_sinPiZPolyEval_in <= prodXY_uid229_pT2_uid217_sinPiZPolyEval_q;
prodXYTruncFR_uid230_pT2_uid217_sinPiZPolyEval_b <= prodXYTruncFR_uid230_pT2_uid217_sinPiZPolyEval_in(38 downto 15);
--highBBits_uid219_sinPiZPolyEval(BITSELECT,218)@12
highBBits_uid219_sinPiZPolyEval_in <= prodXYTruncFR_uid230_pT2_uid217_sinPiZPolyEval_b;
highBBits_uid219_sinPiZPolyEval_b <= highBBits_uid219_sinPiZPolyEval_in(23 downto 2);
--ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_nor(LOGICAL,584)
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_nor_a <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_notEnable_q;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_nor_b <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_sticky_ena_q;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_nor_q <= not (ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_nor_a or ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_nor_b);
--ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_mem_top(CONSTANT,554)
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_mem_top_q <= "0110";
--ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_cmp(LOGICAL,555)
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_cmp_a <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_mem_top_q;
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdmux_q);
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_cmp_q <= "1" when ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_cmp_a = ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_cmp_b else "0";
--ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_cmpReg(REG,556)
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_cmpReg_q <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_sticky_ena(REG,585)
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_nor_q = "1") THEN
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_sticky_ena_q <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_enaAnd(LOGICAL,586)
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_enaAnd_a <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_sticky_ena_q;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_enaAnd_b <= en;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_enaAnd_q <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_enaAnd_a and ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_enaAnd_b;
--ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt(COUNTER,550)
-- every=1, low=0, high=6, step=1, init=1
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt_i = 5 THEN
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt_eq <= '1';
ELSE
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt_eq = '1') THEN
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt_i <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt_i - 6;
ELSE
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt_i <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt_i,3));
--ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdreg(REG,551)
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdreg_q <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdmux(MUX,552)
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdmux_s <= en;
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdmux: PROCESS (ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdmux_s, ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdreg_q, ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt_q)
BEGIN
CASE ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdmux_s IS
WHEN "0" => ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdmux_q <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdreg_q;
WHEN "1" => ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdmux_q <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem(DUALMEM,575)
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_reset0 <= areset;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_ia <= reg_zAddr_uid62_fpCosPiTest_0_to_memoryC2_uid209_sinPiZTableGenerator_0_q;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_aa <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdreg_q;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_ab <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdmux_q;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 7,
widthad_a => 3,
numwords_a => 7,
width_b => 7,
widthad_b => 3,
numwords_b => 7,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_iq,
address_a => ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_aa,
data_a => ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_ia
);
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_q <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_iq(6 downto 0);
--memoryC0_uid207_sinPiZTableGenerator(LOOKUP,206)@12
memoryC0_uid207_sinPiZTableGenerator: PROCESS (ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_q)
BEGIN
-- Begin reserved scope level
CASE (ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_q) IS
WHEN "0000000" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100100100001111110110101110";
WHEN "0000001" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100100100001110100100000010";
WHEN "0000010" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100100100001010101100000000";
WHEN "0000011" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100100100000100001110101000";
WHEN "0000100" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100100011111011001011111101";
WHEN "0000101" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100100011101111100100000010";
WHEN "0000110" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100100011100001010110111011";
WHEN "0000111" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100100011010000100100101111";
WHEN "0001000" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100100010111101001101100010";
WHEN "0001001" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100100010100111010001011101";
WHEN "0001010" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100100010001110110000100111";
WHEN "0001011" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100100001110011101011001001";
WHEN "0001100" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100100001010110000001001110";
WHEN "0001101" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100100000110101110011000000";
WHEN "0001110" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100100000010011000000101011";
WHEN "0001111" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100011111101101101010011101";
WHEN "0010000" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100011111000101110000100010";
WHEN "0010001" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100011110011011010011001011";
WHEN "0010010" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100011101101110010010100101";
WHEN "0010011" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100011100111110101111000011";
WHEN "0010100" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100011100001100101000110101";
WHEN "0010101" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100011011011000000000001111";
WHEN "0010110" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100011010100000110101100011";
WHEN "0010111" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100011001100111001001000110";
WHEN "0011000" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100011000101010111011001110";
WHEN "0011001" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100010111101100001100010000";
WHEN "0011010" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100010110101010111100100100";
WHEN "0011011" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100010101100111001100100010";
WHEN "0011100" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100010100100000111100100011";
WHEN "0011101" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100010011011000001101000000";
WHEN "0011110" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100010010001100111110010110";
WHEN "0011111" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100010000111111010000111111";
WHEN "0100000" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100001111101111000101010111";
WHEN "0100001" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100001110011100011011111110";
WHEN "0100010" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100001101000111010101010001";
WHEN "0100011" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100001011101111110001110000";
WHEN "0100100" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100001010010101110001111010";
WHEN "0100101" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100001000111001010110010010";
WHEN "0100110" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100000111011010011111011001";
WHEN "0100111" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100000101111001001101110010";
WHEN "0101000" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100000100010101100010000001";
WHEN "0101001" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100000010101111011100101011";
WHEN "0101010" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100000001000110111110010101";
WHEN "0101011" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011111111011100000111100110";
WHEN "0101100" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011111101101110111001000101";
WHEN "0101101" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011111011111111010011011011";
WHEN "0101110" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011111010001101010111001111";
WHEN "0101111" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011111000011001000101001110";
WHEN "0110000" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011110110100010011110000000";
WHEN "0110001" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011110100101001100010010010";
WHEN "0110010" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011110010101110010010110000";
WHEN "0110011" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011110000110000110000001000";
WHEN "0110100" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011101110110000111011000111";
WHEN "0110101" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011101100101110110100011101";
WHEN "0110110" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011101010101010011100111001";
WHEN "0110111" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011101000100011110101001100";
WHEN "0111000" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011100110011010111110000111";
WHEN "0111001" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011100100001111111000011101";
WHEN "0111010" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011100010000010100101000000";
WHEN "0111011" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011011111110011000100100100";
WHEN "0111100" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011011101100001010111111110";
WHEN "0111101" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011011011001101100000000011";
WHEN "0111110" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011011000110111011101101010";
WHEN "0111111" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011010110011111010001101001";
WHEN "1000000" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011010100000100111100111000";
WHEN "1000001" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011010001101000100000001111";
WHEN "1000010" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011001111001001111100100111";
WHEN "1000011" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011001100101001010010111011";
WHEN "1000100" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011001010000110100100000101";
WHEN "1000101" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011000111100001110001000001";
WHEN "1000110" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011000100111010111010101011";
WHEN "1000111" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011000010010010000001111111";
WHEN "1001000" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010111111100111000111111011";
WHEN "1001001" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010111100111010001101011110";
WHEN "1001010" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010111010001011010011100110";
WHEN "1001011" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010110111011010011011010011";
WHEN "1001100" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010110100100111100101100110";
WHEN "1001101" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010110001110010110011011111";
WHEN "1001110" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010101110111100000110000001";
WHEN "1001111" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010101100000011011110001110";
WHEN "1010000" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010101001001000111101001000";
WHEN "1010001" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010100110001100100011110100";
WHEN "1010010" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010100011001110010011010110";
WHEN "1010011" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010100000001110001100110010";
WHEN "1010100" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010011101001100010001001111";
WHEN "1010101" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010011010001000100001110100";
WHEN "1010110" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010010111000010111111100101";
WHEN "1010111" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010010011111011101011101100";
WHEN "1011000" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010010000110010100111010001";
WHEN "1011001" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010001101100111110011011011";
WHEN "1011010" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010001010011011010001010100";
WHEN "1011011" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010000111001101000010000111";
WHEN "1011100" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010000011111101000110111110";
WHEN "1011101" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010000000101011100001000010";
WHEN "1011110" => memoryC0_uid207_sinPiZTableGenerator_q <= "01001111101011000010001100001";
WHEN "1011111" => memoryC0_uid207_sinPiZTableGenerator_q <= "01001111010000011011001100111";
WHEN "1100000" => memoryC0_uid207_sinPiZTableGenerator_q <= "01001110110101100111010011111";
WHEN "1100001" => memoryC0_uid207_sinPiZTableGenerator_q <= "01001110011010100110101010111";
WHEN "1100010" => memoryC0_uid207_sinPiZTableGenerator_q <= "01001101111111011001011011101";
WHEN "1100011" => memoryC0_uid207_sinPiZTableGenerator_q <= "01001101100011111111101111111";
WHEN "1100100" => memoryC0_uid207_sinPiZTableGenerator_q <= "01001101001000011001110001011";
WHEN "1100101" => memoryC0_uid207_sinPiZTableGenerator_q <= "01001100101100100111101010001";
WHEN "1100110" => memoryC0_uid207_sinPiZTableGenerator_q <= "01001100010000101001100100001";
WHEN "1100111" => memoryC0_uid207_sinPiZTableGenerator_q <= "01001011110100011111101001011";
WHEN "1101000" => memoryC0_uid207_sinPiZTableGenerator_q <= "01001011011000001010000011111";
WHEN "1101001" => memoryC0_uid207_sinPiZTableGenerator_q <= "01001010111011101000111101111";
WHEN "1101010" => memoryC0_uid207_sinPiZTableGenerator_q <= "01001010011110111100100001011";
WHEN "1101011" => memoryC0_uid207_sinPiZTableGenerator_q <= "01001010000010000100111000111";
WHEN "1101100" => memoryC0_uid207_sinPiZTableGenerator_q <= "01001001100101000010001110101";
WHEN "1101101" => memoryC0_uid207_sinPiZTableGenerator_q <= "01001001000111110100101100111";
WHEN "1101110" => memoryC0_uid207_sinPiZTableGenerator_q <= "01001000101010011100011110001";
WHEN "1101111" => memoryC0_uid207_sinPiZTableGenerator_q <= "01001000001100111001101100110";
WHEN "1110000" => memoryC0_uid207_sinPiZTableGenerator_q <= "01000111101111001100100011011";
WHEN "1110001" => memoryC0_uid207_sinPiZTableGenerator_q <= "01000111010001010101001100101";
WHEN "1110010" => memoryC0_uid207_sinPiZTableGenerator_q <= "01000110110011010011110010111";
WHEN "1110011" => memoryC0_uid207_sinPiZTableGenerator_q <= "01000110010101001000100001000";
WHEN "1110100" => memoryC0_uid207_sinPiZTableGenerator_q <= "01000101110110110011100001101";
WHEN "1110101" => memoryC0_uid207_sinPiZTableGenerator_q <= "01000101011000010100111111100";
WHEN "1110110" => memoryC0_uid207_sinPiZTableGenerator_q <= "01000100111001101101000101100";
WHEN "1110111" => memoryC0_uid207_sinPiZTableGenerator_q <= "01000100011010111011111110011";
WHEN "1111000" => memoryC0_uid207_sinPiZTableGenerator_q <= "01000011111100000001110101000";
WHEN "1111001" => memoryC0_uid207_sinPiZTableGenerator_q <= "01000011011100111110110100010";
WHEN "1111010" => memoryC0_uid207_sinPiZTableGenerator_q <= "01000010111101110011000111010";
WHEN "1111011" => memoryC0_uid207_sinPiZTableGenerator_q <= "01000010011110011110111000111";
WHEN "1111100" => memoryC0_uid207_sinPiZTableGenerator_q <= "01000001111111000010010100010";
WHEN "1111101" => memoryC0_uid207_sinPiZTableGenerator_q <= "01000001011111011101100100011";
WHEN "1111110" => memoryC0_uid207_sinPiZTableGenerator_q <= "01000000111111110000110100011";
WHEN "1111111" => memoryC0_uid207_sinPiZTableGenerator_q <= "01000000011111111100001111011";
WHEN OTHERS =>
memoryC0_uid207_sinPiZTableGenerator_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--sumAHighB_uid220_sinPiZPolyEval(ADD,219)@12
sumAHighB_uid220_sinPiZPolyEval_a <= STD_LOGIC_VECTOR((29 downto 29 => memoryC0_uid207_sinPiZTableGenerator_q(28)) & memoryC0_uid207_sinPiZTableGenerator_q);
sumAHighB_uid220_sinPiZPolyEval_b <= STD_LOGIC_VECTOR((29 downto 22 => highBBits_uid219_sinPiZPolyEval_b(21)) & highBBits_uid219_sinPiZPolyEval_b);
sumAHighB_uid220_sinPiZPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid220_sinPiZPolyEval_a) + SIGNED(sumAHighB_uid220_sinPiZPolyEval_b));
sumAHighB_uid220_sinPiZPolyEval_q <= sumAHighB_uid220_sinPiZPolyEval_o(29 downto 0);
--lowRangeB_uid218_sinPiZPolyEval(BITSELECT,217)@12
lowRangeB_uid218_sinPiZPolyEval_in <= prodXYTruncFR_uid230_pT2_uid217_sinPiZPolyEval_b(1 downto 0);
lowRangeB_uid218_sinPiZPolyEval_b <= lowRangeB_uid218_sinPiZPolyEval_in(1 downto 0);
--s2_uid218_uid221_sinPiZPolyEval(BITJOIN,220)@12
s2_uid218_uid221_sinPiZPolyEval_q <= sumAHighB_uid220_sinPiZPolyEval_q & lowRangeB_uid218_sinPiZPolyEval_b;
--fxpSinRes_uid65_fpCosPiTest(BITSELECT,64)@12
fxpSinRes_uid65_fpCosPiTest_in <= s2_uid218_uid221_sinPiZPolyEval_q(29 downto 0);
fxpSinRes_uid65_fpCosPiTest_b <= fxpSinRes_uid65_fpCosPiTest_in(29 downto 5);
--reg_fxpSinRes_uid65_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_1(REG,270)@12
reg_fxpSinRes_uid65_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fxpSinRes_uid65_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_1_q <= "0000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fxpSinRes_uid65_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_1_q <= fxpSinRes_uid65_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_nor(LOGICAL,622)
ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_nor_a <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_notEnable_q;
ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_nor_b <= ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_sticky_ena_q;
ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_nor_q <= not (ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_nor_a or ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_nor_b);
--ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_sticky_ena(REG,623)
ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_nor_q = "1") THEN
ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_sticky_ena_q <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_enaAnd(LOGICAL,624)
ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_enaAnd_a <= ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_sticky_ena_q;
ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_enaAnd_b <= en;
ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_enaAnd_q <= ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_enaAnd_a and ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_enaAnd_b;
--LeftShiftStage131dto0_uid202_alignedZ_uid57_fpCosPiTest(BITSELECT,201)@7
LeftShiftStage131dto0_uid202_alignedZ_uid57_fpCosPiTest_in <= leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_q(31 downto 0);
LeftShiftStage131dto0_uid202_alignedZ_uid57_fpCosPiTest_b <= LeftShiftStage131dto0_uid202_alignedZ_uid57_fpCosPiTest_in(31 downto 0);
--leftShiftStage2Idx3_uid203_alignedZ_uid57_fpCosPiTest(BITJOIN,202)@7
leftShiftStage2Idx3_uid203_alignedZ_uid57_fpCosPiTest_q <= LeftShiftStage131dto0_uid202_alignedZ_uid57_fpCosPiTest_b & leftShiftStage2Idx3Pad3_uid131_fxpX_uid41_fpCosPiTest_q;
--LeftShiftStage132dto0_uid199_alignedZ_uid57_fpCosPiTest(BITSELECT,198)@7
LeftShiftStage132dto0_uid199_alignedZ_uid57_fpCosPiTest_in <= leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_q(32 downto 0);
LeftShiftStage132dto0_uid199_alignedZ_uid57_fpCosPiTest_b <= LeftShiftStage132dto0_uid199_alignedZ_uid57_fpCosPiTest_in(32 downto 0);
--leftShiftStage2Idx2_uid200_alignedZ_uid57_fpCosPiTest(BITJOIN,199)@7
leftShiftStage2Idx2_uid200_alignedZ_uid57_fpCosPiTest_q <= LeftShiftStage132dto0_uid199_alignedZ_uid57_fpCosPiTest_b & leftShiftStage2Idx2Pad2_uid128_fxpX_uid41_fpCosPiTest_q;
--LeftShiftStage133dto0_uid196_alignedZ_uid57_fpCosPiTest(BITSELECT,195)@7
LeftShiftStage133dto0_uid196_alignedZ_uid57_fpCosPiTest_in <= leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_q(33 downto 0);
LeftShiftStage133dto0_uid196_alignedZ_uid57_fpCosPiTest_b <= LeftShiftStage133dto0_uid196_alignedZ_uid57_fpCosPiTest_in(33 downto 0);
--leftShiftStage2Idx1_uid197_alignedZ_uid57_fpCosPiTest(BITJOIN,196)@7
leftShiftStage2Idx1_uid197_alignedZ_uid57_fpCosPiTest_q <= LeftShiftStage133dto0_uid196_alignedZ_uid57_fpCosPiTest_b & GND_q;
--vStage_uid141_lzcZ_uid56_fpCosPiTest(BITSELECT,140)@3
vStage_uid141_lzcZ_uid56_fpCosPiTest_in <= z_uid54_fpCosPiTest_b(2 downto 0);
vStage_uid141_lzcZ_uid56_fpCosPiTest_b <= vStage_uid141_lzcZ_uid56_fpCosPiTest_in(2 downto 0);
--ld_vStage_uid141_lzcZ_uid56_fpCosPiTest_b_to_leftShiftStage0Idx2_uid180_alignedZ_uid57_fpCosPiTest_b(DELAY,450)@3
ld_vStage_uid141_lzcZ_uid56_fpCosPiTest_b_to_leftShiftStage0Idx2_uid180_alignedZ_uid57_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 3, depth => 3 )
PORT MAP ( xin => vStage_uid141_lzcZ_uid56_fpCosPiTest_b, xout => ld_vStage_uid141_lzcZ_uid56_fpCosPiTest_b_to_leftShiftStage0Idx2_uid180_alignedZ_uid57_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage0Idx2_uid180_alignedZ_uid57_fpCosPiTest(BITJOIN,179)@6
leftShiftStage0Idx2_uid180_alignedZ_uid57_fpCosPiTest_q <= ld_vStage_uid141_lzcZ_uid56_fpCosPiTest_b_to_leftShiftStage0Idx2_uid180_alignedZ_uid57_fpCosPiTest_b_q & leftShiftStage0Idx2Pad32_uid108_fxpX_uid41_fpCosPiTest_q;
--X18dto0_uid176_alignedZ_uid57_fpCosPiTest(BITSELECT,175)@3
X18dto0_uid176_alignedZ_uid57_fpCosPiTest_in <= z_uid54_fpCosPiTest_b(18 downto 0);
X18dto0_uid176_alignedZ_uid57_fpCosPiTest_b <= X18dto0_uid176_alignedZ_uid57_fpCosPiTest_in(18 downto 0);
--ld_X18dto0_uid176_alignedZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx1_uid177_alignedZ_uid57_fpCosPiTest_b_inputreg(DELAY,573)
ld_X18dto0_uid176_alignedZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx1_uid177_alignedZ_uid57_fpCosPiTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 19, depth => 1 )
PORT MAP ( xin => X18dto0_uid176_alignedZ_uid57_fpCosPiTest_b, xout => ld_X18dto0_uid176_alignedZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx1_uid177_alignedZ_uid57_fpCosPiTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_X18dto0_uid176_alignedZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx1_uid177_alignedZ_uid57_fpCosPiTest_b(DELAY,449)@3
ld_X18dto0_uid176_alignedZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx1_uid177_alignedZ_uid57_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 19, depth => 2 )
PORT MAP ( xin => ld_X18dto0_uid176_alignedZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx1_uid177_alignedZ_uid57_fpCosPiTest_b_inputreg_q, xout => ld_X18dto0_uid176_alignedZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx1_uid177_alignedZ_uid57_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage0Idx1_uid177_alignedZ_uid57_fpCosPiTest(BITJOIN,176)@6
leftShiftStage0Idx1_uid177_alignedZ_uid57_fpCosPiTest_q <= ld_X18dto0_uid176_alignedZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx1_uid177_alignedZ_uid57_fpCosPiTest_b_q & leftShiftStage0Idx1Pad16_uid105_fxpX_uid41_fpCosPiTest_q;
--ld_z_uid54_fpCosPiTest_b_to_leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_c_inputreg(DELAY,574)
ld_z_uid54_fpCosPiTest_b_to_leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 35, depth => 1 )
PORT MAP ( xin => z_uid54_fpCosPiTest_b, xout => ld_z_uid54_fpCosPiTest_b_to_leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_z_uid54_fpCosPiTest_b_to_leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_c(DELAY,453)@3
ld_z_uid54_fpCosPiTest_b_to_leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_c : dspba_delay
GENERIC MAP ( width => 35, depth => 2 )
PORT MAP ( xin => ld_z_uid54_fpCosPiTest_b_to_leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_c_inputreg_q, xout => ld_z_uid54_fpCosPiTest_b_to_leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--rVStage_uid138_lzcZ_uid56_fpCosPiTest(BITSELECT,137)@3
rVStage_uid138_lzcZ_uid56_fpCosPiTest_in <= z_uid54_fpCosPiTest_b;
rVStage_uid138_lzcZ_uid56_fpCosPiTest_b <= rVStage_uid138_lzcZ_uid56_fpCosPiTest_in(34 downto 3);
--reg_rVStage_uid138_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid139_lzcZ_uid56_fpCosPiTest_1(REG,247)@3
reg_rVStage_uid138_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid139_lzcZ_uid56_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid138_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid139_lzcZ_uid56_fpCosPiTest_1_q <= "00000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid138_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid139_lzcZ_uid56_fpCosPiTest_1_q <= rVStage_uid138_lzcZ_uid56_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid139_lzcZ_uid56_fpCosPiTest(LOGICAL,138)@4
vCount_uid139_lzcZ_uid56_fpCosPiTest_a <= reg_rVStage_uid138_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid139_lzcZ_uid56_fpCosPiTest_1_q;
vCount_uid139_lzcZ_uid56_fpCosPiTest_b <= leftShiftStage0Idx2Pad32_uid108_fxpX_uid41_fpCosPiTest_q;
vCount_uid139_lzcZ_uid56_fpCosPiTest_q <= "1" when vCount_uid139_lzcZ_uid56_fpCosPiTest_a = vCount_uid139_lzcZ_uid56_fpCosPiTest_b else "0";
--ld_vCount_uid139_lzcZ_uid56_fpCosPiTest_q_to_r_uid172_lzcZ_uid56_fpCosPiTest_f(DELAY,447)@4
ld_vCount_uid139_lzcZ_uid56_fpCosPiTest_q_to_r_uid172_lzcZ_uid56_fpCosPiTest_f : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => vCount_uid139_lzcZ_uid56_fpCosPiTest_q, xout => ld_vCount_uid139_lzcZ_uid56_fpCosPiTest_q_to_r_uid172_lzcZ_uid56_fpCosPiTest_f_q, ena => en(0), clk => clk, aclr => areset );
--mO_uid140_lzcZ_uid56_fpCosPiTest(CONSTANT,139)
mO_uid140_lzcZ_uid56_fpCosPiTest_q <= "11111111111111111111111111111";
--cStage_uid142_lzcZ_uid56_fpCosPiTest(BITJOIN,141)@3
cStage_uid142_lzcZ_uid56_fpCosPiTest_q <= vStage_uid141_lzcZ_uid56_fpCosPiTest_b & mO_uid140_lzcZ_uid56_fpCosPiTest_q;
--reg_cStage_uid142_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid144_lzcZ_uid56_fpCosPiTest_3(REG,249)@3
reg_cStage_uid142_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid144_lzcZ_uid56_fpCosPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cStage_uid142_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid144_lzcZ_uid56_fpCosPiTest_3_q <= "00000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cStage_uid142_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid144_lzcZ_uid56_fpCosPiTest_3_q <= cStage_uid142_lzcZ_uid56_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--vStagei_uid144_lzcZ_uid56_fpCosPiTest(MUX,143)@4
vStagei_uid144_lzcZ_uid56_fpCosPiTest_s <= vCount_uid139_lzcZ_uid56_fpCosPiTest_q;
vStagei_uid144_lzcZ_uid56_fpCosPiTest: PROCESS (vStagei_uid144_lzcZ_uid56_fpCosPiTest_s, en, reg_rVStage_uid138_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid139_lzcZ_uid56_fpCosPiTest_1_q, reg_cStage_uid142_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid144_lzcZ_uid56_fpCosPiTest_3_q)
BEGIN
CASE vStagei_uid144_lzcZ_uid56_fpCosPiTest_s IS
WHEN "0" => vStagei_uid144_lzcZ_uid56_fpCosPiTest_q <= reg_rVStage_uid138_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid139_lzcZ_uid56_fpCosPiTest_1_q;
WHEN "1" => vStagei_uid144_lzcZ_uid56_fpCosPiTest_q <= reg_cStage_uid142_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid144_lzcZ_uid56_fpCosPiTest_3_q;
WHEN OTHERS => vStagei_uid144_lzcZ_uid56_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid146_lzcZ_uid56_fpCosPiTest(BITSELECT,145)@4
rVStage_uid146_lzcZ_uid56_fpCosPiTest_in <= vStagei_uid144_lzcZ_uid56_fpCosPiTest_q;
rVStage_uid146_lzcZ_uid56_fpCosPiTest_b <= rVStage_uid146_lzcZ_uid56_fpCosPiTest_in(31 downto 16);
--reg_rVStage_uid146_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid147_lzcZ_uid56_fpCosPiTest_1(REG,250)@4
reg_rVStage_uid146_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid147_lzcZ_uid56_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid146_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid147_lzcZ_uid56_fpCosPiTest_1_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid146_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid147_lzcZ_uid56_fpCosPiTest_1_q <= rVStage_uid146_lzcZ_uid56_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid147_lzcZ_uid56_fpCosPiTest(LOGICAL,146)@5
vCount_uid147_lzcZ_uid56_fpCosPiTest_a <= reg_rVStage_uid146_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid147_lzcZ_uid56_fpCosPiTest_1_q;
vCount_uid147_lzcZ_uid56_fpCosPiTest_b <= leftShiftStage0Idx1Pad16_uid105_fxpX_uid41_fpCosPiTest_q;
vCount_uid147_lzcZ_uid56_fpCosPiTest_q <= "1" when vCount_uid147_lzcZ_uid56_fpCosPiTest_a = vCount_uid147_lzcZ_uid56_fpCosPiTest_b else "0";
--ld_vCount_uid147_lzcZ_uid56_fpCosPiTest_q_to_r_uid172_lzcZ_uid56_fpCosPiTest_e(DELAY,446)@5
ld_vCount_uid147_lzcZ_uid56_fpCosPiTest_q_to_r_uid172_lzcZ_uid56_fpCosPiTest_e : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vCount_uid147_lzcZ_uid56_fpCosPiTest_q, xout => ld_vCount_uid147_lzcZ_uid56_fpCosPiTest_q_to_r_uid172_lzcZ_uid56_fpCosPiTest_e_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid148_lzcZ_uid56_fpCosPiTest(BITSELECT,147)@4
vStage_uid148_lzcZ_uid56_fpCosPiTest_in <= vStagei_uid144_lzcZ_uid56_fpCosPiTest_q(15 downto 0);
vStage_uid148_lzcZ_uid56_fpCosPiTest_b <= vStage_uid148_lzcZ_uid56_fpCosPiTest_in(15 downto 0);
--reg_vStage_uid148_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid150_lzcZ_uid56_fpCosPiTest_3(REG,252)@4
reg_vStage_uid148_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid150_lzcZ_uid56_fpCosPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid148_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid150_lzcZ_uid56_fpCosPiTest_3_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid148_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid150_lzcZ_uid56_fpCosPiTest_3_q <= vStage_uid148_lzcZ_uid56_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid150_lzcZ_uid56_fpCosPiTest(MUX,149)@5
vStagei_uid150_lzcZ_uid56_fpCosPiTest_s <= vCount_uid147_lzcZ_uid56_fpCosPiTest_q;
vStagei_uid150_lzcZ_uid56_fpCosPiTest: PROCESS (vStagei_uid150_lzcZ_uid56_fpCosPiTest_s, en, reg_rVStage_uid146_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid147_lzcZ_uid56_fpCosPiTest_1_q, reg_vStage_uid148_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid150_lzcZ_uid56_fpCosPiTest_3_q)
BEGIN
CASE vStagei_uid150_lzcZ_uid56_fpCosPiTest_s IS
WHEN "0" => vStagei_uid150_lzcZ_uid56_fpCosPiTest_q <= reg_rVStage_uid146_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid147_lzcZ_uid56_fpCosPiTest_1_q;
WHEN "1" => vStagei_uid150_lzcZ_uid56_fpCosPiTest_q <= reg_vStage_uid148_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid150_lzcZ_uid56_fpCosPiTest_3_q;
WHEN OTHERS => vStagei_uid150_lzcZ_uid56_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid152_lzcZ_uid56_fpCosPiTest(BITSELECT,151)@5
rVStage_uid152_lzcZ_uid56_fpCosPiTest_in <= vStagei_uid150_lzcZ_uid56_fpCosPiTest_q;
rVStage_uid152_lzcZ_uid56_fpCosPiTest_b <= rVStage_uid152_lzcZ_uid56_fpCosPiTest_in(15 downto 8);
--vCount_uid153_lzcZ_uid56_fpCosPiTest(LOGICAL,152)@5
vCount_uid153_lzcZ_uid56_fpCosPiTest_a <= rVStage_uid152_lzcZ_uid56_fpCosPiTest_b;
vCount_uid153_lzcZ_uid56_fpCosPiTest_b <= cstAllZWE_uid21_fpCosPiTest_q;
vCount_uid153_lzcZ_uid56_fpCosPiTest_q <= "1" when vCount_uid153_lzcZ_uid56_fpCosPiTest_a = vCount_uid153_lzcZ_uid56_fpCosPiTest_b else "0";
--reg_vCount_uid153_lzcZ_uid56_fpCosPiTest_0_to_r_uid172_lzcZ_uid56_fpCosPiTest_3(REG,256)@5
reg_vCount_uid153_lzcZ_uid56_fpCosPiTest_0_to_r_uid172_lzcZ_uid56_fpCosPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid153_lzcZ_uid56_fpCosPiTest_0_to_r_uid172_lzcZ_uid56_fpCosPiTest_3_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid153_lzcZ_uid56_fpCosPiTest_0_to_r_uid172_lzcZ_uid56_fpCosPiTest_3_q <= vCount_uid153_lzcZ_uid56_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--vStage_uid154_lzcZ_uid56_fpCosPiTest(BITSELECT,153)@5
vStage_uid154_lzcZ_uid56_fpCosPiTest_in <= vStagei_uid150_lzcZ_uid56_fpCosPiTest_q(7 downto 0);
vStage_uid154_lzcZ_uid56_fpCosPiTest_b <= vStage_uid154_lzcZ_uid56_fpCosPiTest_in(7 downto 0);
--vStagei_uid156_lzcZ_uid56_fpCosPiTest(MUX,155)@5
vStagei_uid156_lzcZ_uid56_fpCosPiTest_s <= vCount_uid153_lzcZ_uid56_fpCosPiTest_q;
vStagei_uid156_lzcZ_uid56_fpCosPiTest: PROCESS (vStagei_uid156_lzcZ_uid56_fpCosPiTest_s, en, rVStage_uid152_lzcZ_uid56_fpCosPiTest_b, vStage_uid154_lzcZ_uid56_fpCosPiTest_b)
BEGIN
CASE vStagei_uid156_lzcZ_uid56_fpCosPiTest_s IS
WHEN "0" => vStagei_uid156_lzcZ_uid56_fpCosPiTest_q <= rVStage_uid152_lzcZ_uid56_fpCosPiTest_b;
WHEN "1" => vStagei_uid156_lzcZ_uid56_fpCosPiTest_q <= vStage_uid154_lzcZ_uid56_fpCosPiTest_b;
WHEN OTHERS => vStagei_uid156_lzcZ_uid56_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid158_lzcZ_uid56_fpCosPiTest(BITSELECT,157)@5
rVStage_uid158_lzcZ_uid56_fpCosPiTest_in <= vStagei_uid156_lzcZ_uid56_fpCosPiTest_q;
rVStage_uid158_lzcZ_uid56_fpCosPiTest_b <= rVStage_uid158_lzcZ_uid56_fpCosPiTest_in(7 downto 4);
--reg_rVStage_uid158_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid159_lzcZ_uid56_fpCosPiTest_1(REG,253)@5
reg_rVStage_uid158_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid159_lzcZ_uid56_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid158_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid159_lzcZ_uid56_fpCosPiTest_1_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid158_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid159_lzcZ_uid56_fpCosPiTest_1_q <= rVStage_uid158_lzcZ_uid56_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid159_lzcZ_uid56_fpCosPiTest(LOGICAL,158)@6
vCount_uid159_lzcZ_uid56_fpCosPiTest_a <= reg_rVStage_uid158_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid159_lzcZ_uid56_fpCosPiTest_1_q;
vCount_uid159_lzcZ_uid56_fpCosPiTest_b <= leftShiftStage1Idx1Pad4_uid114_fxpX_uid41_fpCosPiTest_q;
vCount_uid159_lzcZ_uid56_fpCosPiTest_q <= "1" when vCount_uid159_lzcZ_uid56_fpCosPiTest_a = vCount_uid159_lzcZ_uid56_fpCosPiTest_b else "0";
--vStage_uid160_lzcZ_uid56_fpCosPiTest(BITSELECT,159)@5
vStage_uid160_lzcZ_uid56_fpCosPiTest_in <= vStagei_uid156_lzcZ_uid56_fpCosPiTest_q(3 downto 0);
vStage_uid160_lzcZ_uid56_fpCosPiTest_b <= vStage_uid160_lzcZ_uid56_fpCosPiTest_in(3 downto 0);
--reg_vStage_uid160_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid162_lzcZ_uid56_fpCosPiTest_3(REG,255)@5
reg_vStage_uid160_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid162_lzcZ_uid56_fpCosPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid160_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid162_lzcZ_uid56_fpCosPiTest_3_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid160_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid162_lzcZ_uid56_fpCosPiTest_3_q <= vStage_uid160_lzcZ_uid56_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid162_lzcZ_uid56_fpCosPiTest(MUX,161)@6
vStagei_uid162_lzcZ_uid56_fpCosPiTest_s <= vCount_uid159_lzcZ_uid56_fpCosPiTest_q;
vStagei_uid162_lzcZ_uid56_fpCosPiTest: PROCESS (vStagei_uid162_lzcZ_uid56_fpCosPiTest_s, en, reg_rVStage_uid158_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid159_lzcZ_uid56_fpCosPiTest_1_q, reg_vStage_uid160_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid162_lzcZ_uid56_fpCosPiTest_3_q)
BEGIN
CASE vStagei_uid162_lzcZ_uid56_fpCosPiTest_s IS
WHEN "0" => vStagei_uid162_lzcZ_uid56_fpCosPiTest_q <= reg_rVStage_uid158_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid159_lzcZ_uid56_fpCosPiTest_1_q;
WHEN "1" => vStagei_uid162_lzcZ_uid56_fpCosPiTest_q <= reg_vStage_uid160_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid162_lzcZ_uid56_fpCosPiTest_3_q;
WHEN OTHERS => vStagei_uid162_lzcZ_uid56_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid164_lzcZ_uid56_fpCosPiTest(BITSELECT,163)@6
rVStage_uid164_lzcZ_uid56_fpCosPiTest_in <= vStagei_uid162_lzcZ_uid56_fpCosPiTest_q;
rVStage_uid164_lzcZ_uid56_fpCosPiTest_b <= rVStage_uid164_lzcZ_uid56_fpCosPiTest_in(3 downto 2);
--vCount_uid165_lzcZ_uid56_fpCosPiTest(LOGICAL,164)@6
vCount_uid165_lzcZ_uid56_fpCosPiTest_a <= rVStage_uid164_lzcZ_uid56_fpCosPiTest_b;
vCount_uid165_lzcZ_uid56_fpCosPiTest_b <= leftShiftStage2Idx2Pad2_uid128_fxpX_uid41_fpCosPiTest_q;
vCount_uid165_lzcZ_uid56_fpCosPiTest_q <= "1" when vCount_uid165_lzcZ_uid56_fpCosPiTest_a = vCount_uid165_lzcZ_uid56_fpCosPiTest_b else "0";
--vStage_uid166_lzcZ_uid56_fpCosPiTest(BITSELECT,165)@6
vStage_uid166_lzcZ_uid56_fpCosPiTest_in <= vStagei_uid162_lzcZ_uid56_fpCosPiTest_q(1 downto 0);
vStage_uid166_lzcZ_uid56_fpCosPiTest_b <= vStage_uid166_lzcZ_uid56_fpCosPiTest_in(1 downto 0);
--vStagei_uid168_lzcZ_uid56_fpCosPiTest(MUX,167)@6
vStagei_uid168_lzcZ_uid56_fpCosPiTest_s <= vCount_uid165_lzcZ_uid56_fpCosPiTest_q;
vStagei_uid168_lzcZ_uid56_fpCosPiTest: PROCESS (vStagei_uid168_lzcZ_uid56_fpCosPiTest_s, en, rVStage_uid164_lzcZ_uid56_fpCosPiTest_b, vStage_uid166_lzcZ_uid56_fpCosPiTest_b)
BEGIN
CASE vStagei_uid168_lzcZ_uid56_fpCosPiTest_s IS
WHEN "0" => vStagei_uid168_lzcZ_uid56_fpCosPiTest_q <= rVStage_uid164_lzcZ_uid56_fpCosPiTest_b;
WHEN "1" => vStagei_uid168_lzcZ_uid56_fpCosPiTest_q <= vStage_uid166_lzcZ_uid56_fpCosPiTest_b;
WHEN OTHERS => vStagei_uid168_lzcZ_uid56_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid170_lzcZ_uid56_fpCosPiTest(BITSELECT,169)@6
rVStage_uid170_lzcZ_uid56_fpCosPiTest_in <= vStagei_uid168_lzcZ_uid56_fpCosPiTest_q;
rVStage_uid170_lzcZ_uid56_fpCosPiTest_b <= rVStage_uid170_lzcZ_uid56_fpCosPiTest_in(1 downto 1);
--vCount_uid171_lzcZ_uid56_fpCosPiTest(LOGICAL,170)@6
vCount_uid171_lzcZ_uid56_fpCosPiTest_a <= rVStage_uid170_lzcZ_uid56_fpCosPiTest_b;
vCount_uid171_lzcZ_uid56_fpCosPiTest_b <= GND_q;
vCount_uid171_lzcZ_uid56_fpCosPiTest_q <= "1" when vCount_uid171_lzcZ_uid56_fpCosPiTest_a = vCount_uid171_lzcZ_uid56_fpCosPiTest_b else "0";
--r_uid172_lzcZ_uid56_fpCosPiTest(BITJOIN,171)@6
r_uid172_lzcZ_uid56_fpCosPiTest_q <= ld_vCount_uid139_lzcZ_uid56_fpCosPiTest_q_to_r_uid172_lzcZ_uid56_fpCosPiTest_f_q & ld_vCount_uid147_lzcZ_uid56_fpCosPiTest_q_to_r_uid172_lzcZ_uid56_fpCosPiTest_e_q & reg_vCount_uid153_lzcZ_uid56_fpCosPiTest_0_to_r_uid172_lzcZ_uid56_fpCosPiTest_3_q & vCount_uid159_lzcZ_uid56_fpCosPiTest_q & vCount_uid165_lzcZ_uid56_fpCosPiTest_q & vCount_uid171_lzcZ_uid56_fpCosPiTest_q;
--leftShiftStageSel5Dto4_uid182_alignedZ_uid57_fpCosPiTest(BITSELECT,181)@6
leftShiftStageSel5Dto4_uid182_alignedZ_uid57_fpCosPiTest_in <= r_uid172_lzcZ_uid56_fpCosPiTest_q;
leftShiftStageSel5Dto4_uid182_alignedZ_uid57_fpCosPiTest_b <= leftShiftStageSel5Dto4_uid182_alignedZ_uid57_fpCosPiTest_in(5 downto 4);
--leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest(MUX,182)@6
leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_s <= leftShiftStageSel5Dto4_uid182_alignedZ_uid57_fpCosPiTest_b;
leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest: PROCESS (leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_s, en, ld_z_uid54_fpCosPiTest_b_to_leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_c_q, leftShiftStage0Idx1_uid177_alignedZ_uid57_fpCosPiTest_q, leftShiftStage0Idx2_uid180_alignedZ_uid57_fpCosPiTest_q, cstZwSwF_uid15_fpCosPiTest_q)
BEGIN
CASE leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_s IS
WHEN "00" => leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_q <= ld_z_uid54_fpCosPiTest_b_to_leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_c_q;
WHEN "01" => leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_q <= leftShiftStage0Idx1_uid177_alignedZ_uid57_fpCosPiTest_q;
WHEN "10" => leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_q <= leftShiftStage0Idx2_uid180_alignedZ_uid57_fpCosPiTest_q;
WHEN "11" => leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_q <= cstZwSwF_uid15_fpCosPiTest_q;
WHEN OTHERS => leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage022dto0_uid191_alignedZ_uid57_fpCosPiTest(BITSELECT,190)@6
LeftShiftStage022dto0_uid191_alignedZ_uid57_fpCosPiTest_in <= leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_q(22 downto 0);
LeftShiftStage022dto0_uid191_alignedZ_uid57_fpCosPiTest_b <= LeftShiftStage022dto0_uid191_alignedZ_uid57_fpCosPiTest_in(22 downto 0);
--leftShiftStage1Idx3_uid192_alignedZ_uid57_fpCosPiTest(BITJOIN,191)@6
leftShiftStage1Idx3_uid192_alignedZ_uid57_fpCosPiTest_q <= LeftShiftStage022dto0_uid191_alignedZ_uid57_fpCosPiTest_b & leftShiftStage1Idx3Pad12_uid120_fxpX_uid41_fpCosPiTest_q;
--reg_leftShiftStage1Idx3_uid192_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_5(REG,261)@6
reg_leftShiftStage1Idx3_uid192_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx3_uid192_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_5_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx3_uid192_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_5_q <= leftShiftStage1Idx3_uid192_alignedZ_uid57_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage026dto0_uid188_alignedZ_uid57_fpCosPiTest(BITSELECT,187)@6
LeftShiftStage026dto0_uid188_alignedZ_uid57_fpCosPiTest_in <= leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_q(26 downto 0);
LeftShiftStage026dto0_uid188_alignedZ_uid57_fpCosPiTest_b <= LeftShiftStage026dto0_uid188_alignedZ_uid57_fpCosPiTest_in(26 downto 0);
--leftShiftStage1Idx2_uid189_alignedZ_uid57_fpCosPiTest(BITJOIN,188)@6
leftShiftStage1Idx2_uid189_alignedZ_uid57_fpCosPiTest_q <= LeftShiftStage026dto0_uid188_alignedZ_uid57_fpCosPiTest_b & cstAllZWE_uid21_fpCosPiTest_q;
--reg_leftShiftStage1Idx2_uid189_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_4(REG,260)@6
reg_leftShiftStage1Idx2_uid189_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx2_uid189_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_4_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx2_uid189_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_4_q <= leftShiftStage1Idx2_uid189_alignedZ_uid57_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage030dto0_uid185_alignedZ_uid57_fpCosPiTest(BITSELECT,184)@6
LeftShiftStage030dto0_uid185_alignedZ_uid57_fpCosPiTest_in <= leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_q(30 downto 0);
LeftShiftStage030dto0_uid185_alignedZ_uid57_fpCosPiTest_b <= LeftShiftStage030dto0_uid185_alignedZ_uid57_fpCosPiTest_in(30 downto 0);
--leftShiftStage1Idx1_uid186_alignedZ_uid57_fpCosPiTest(BITJOIN,185)@6
leftShiftStage1Idx1_uid186_alignedZ_uid57_fpCosPiTest_q <= LeftShiftStage030dto0_uid185_alignedZ_uid57_fpCosPiTest_b & leftShiftStage1Idx1Pad4_uid114_fxpX_uid41_fpCosPiTest_q;
--reg_leftShiftStage1Idx1_uid186_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_3(REG,259)@6
reg_leftShiftStage1Idx1_uid186_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx1_uid186_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_3_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx1_uid186_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_3_q <= leftShiftStage1Idx1_uid186_alignedZ_uid57_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--reg_leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_2(REG,258)@6
reg_leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_2_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_2_q <= leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel3Dto2_uid193_alignedZ_uid57_fpCosPiTest(BITSELECT,192)@6
leftShiftStageSel3Dto2_uid193_alignedZ_uid57_fpCosPiTest_in <= r_uid172_lzcZ_uid56_fpCosPiTest_q(3 downto 0);
leftShiftStageSel3Dto2_uid193_alignedZ_uid57_fpCosPiTest_b <= leftShiftStageSel3Dto2_uid193_alignedZ_uid57_fpCosPiTest_in(3 downto 2);
--reg_leftShiftStageSel3Dto2_uid193_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_1(REG,257)@6
reg_leftShiftStageSel3Dto2_uid193_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel3Dto2_uid193_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel3Dto2_uid193_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_1_q <= leftShiftStageSel3Dto2_uid193_alignedZ_uid57_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest(MUX,193)@7
leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_s <= reg_leftShiftStageSel3Dto2_uid193_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_1_q;
leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest: PROCESS (leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_s, en, reg_leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_2_q, reg_leftShiftStage1Idx1_uid186_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_3_q, reg_leftShiftStage1Idx2_uid189_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_4_q, reg_leftShiftStage1Idx3_uid192_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_5_q)
BEGIN
CASE leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_s IS
WHEN "00" => leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_q <= reg_leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_2_q;
WHEN "01" => leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_q <= reg_leftShiftStage1Idx1_uid186_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_3_q;
WHEN "10" => leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_q <= reg_leftShiftStage1Idx2_uid189_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_4_q;
WHEN "11" => leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_q <= reg_leftShiftStage1Idx3_uid192_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_5_q;
WHEN OTHERS => leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--leftShiftStageSel1Dto0_uid204_alignedZ_uid57_fpCosPiTest(BITSELECT,203)@6
leftShiftStageSel1Dto0_uid204_alignedZ_uid57_fpCosPiTest_in <= r_uid172_lzcZ_uid56_fpCosPiTest_q(1 downto 0);
leftShiftStageSel1Dto0_uid204_alignedZ_uid57_fpCosPiTest_b <= leftShiftStageSel1Dto0_uid204_alignedZ_uid57_fpCosPiTest_in(1 downto 0);
--reg_leftShiftStageSel1Dto0_uid204_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest_1(REG,262)@6
reg_leftShiftStageSel1Dto0_uid204_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel1Dto0_uid204_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel1Dto0_uid204_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest_1_q <= leftShiftStageSel1Dto0_uid204_alignedZ_uid57_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest(MUX,204)@7
leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest_s <= reg_leftShiftStageSel1Dto0_uid204_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest_1_q;
leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest: PROCESS (leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest_s, en, leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_q, leftShiftStage2Idx1_uid197_alignedZ_uid57_fpCosPiTest_q, leftShiftStage2Idx2_uid200_alignedZ_uid57_fpCosPiTest_q, leftShiftStage2Idx3_uid203_alignedZ_uid57_fpCosPiTest_q)
BEGIN
CASE leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest_s IS
WHEN "00" => leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest_q <= leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_q;
WHEN "01" => leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest_q <= leftShiftStage2Idx1_uid197_alignedZ_uid57_fpCosPiTest_q;
WHEN "10" => leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest_q <= leftShiftStage2Idx2_uid200_alignedZ_uid57_fpCosPiTest_q;
WHEN "11" => leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest_q <= leftShiftStage2Idx3_uid203_alignedZ_uid57_fpCosPiTest_q;
WHEN OTHERS => leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--alignedZLow_uid58_fpCosPiTest(BITSELECT,57)@7
alignedZLow_uid58_fpCosPiTest_in <= leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest_q;
alignedZLow_uid58_fpCosPiTest_b <= alignedZLow_uid58_fpCosPiTest_in(34 downto 11);
--ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_inputreg(DELAY,612)
ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 24, depth => 1 )
PORT MAP ( xin => alignedZLow_uid58_fpCosPiTest_b, xout => ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem(DUALMEM,613)
ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_reset0 <= areset;
ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_ia <= ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_inputreg_q;
ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_aa <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdreg_q;
ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_ab <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdmux_q;
ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 24,
widthad_a => 2,
numwords_a => 3,
width_b => 24,
widthad_b => 2,
numwords_b => 3,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_iq,
address_a => ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_aa,
data_a => ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_ia
);
ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_q <= ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_iq(23 downto 0);
--reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0(REG,269)@12
reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_q <= ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest(MULT,222)@13
prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_pr <= UNSIGNED(prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_a) * UNSIGNED(prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_b);
prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_a <= (others => '0');
prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_b <= (others => '0');
prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_a <= reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_q;
prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_b <= reg_fxpSinRes_uid65_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_1_q;
prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_s1 <= STD_LOGIC_VECTOR(prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_pr);
END IF;
END IF;
END PROCESS;
prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_q <= prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid224_mul2xSinRes_uid66_fpCosPiTest(BITSELECT,223)@16
prodXYTruncFR_uid224_mul2xSinRes_uid66_fpCosPiTest_in <= prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_q;
prodXYTruncFR_uid224_mul2xSinRes_uid66_fpCosPiTest_b <= prodXYTruncFR_uid224_mul2xSinRes_uid66_fpCosPiTest_in(48 downto 23);
--normBit_uid67_fpCosPiTest(BITSELECT,66)@16
normBit_uid67_fpCosPiTest_in <= prodXYTruncFR_uid224_mul2xSinRes_uid66_fpCosPiTest_b;
normBit_uid67_fpCosPiTest_b <= normBit_uid67_fpCosPiTest_in(25 downto 25);
--cstAllZWF_uid9_fpCosPiTest(CONSTANT,8)
cstAllZWF_uid9_fpCosPiTest_q <= "00000000000000000000000";
--rndExpUpdate_uid72_uid73_fpCosPiTest(BITJOIN,72)@16
rndExpUpdate_uid72_uid73_fpCosPiTest_q <= normBit_uid67_fpCosPiTest_b & cstAllZWF_uid9_fpCosPiTest_q & VCC_q;
--ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_nor(LOGICAL,558)
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_nor_a <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_notEnable_q;
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_nor_b <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_sticky_ena_q;
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_nor_q <= not (ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_nor_a or ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_nor_b);
--ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_sticky_ena(REG,559)
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_nor_q = "1") THEN
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_sticky_ena_q <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_enaAnd(LOGICAL,560)
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_enaAnd_a <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_sticky_ena_q;
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_enaAnd_b <= en;
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_enaAnd_q <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_enaAnd_a and ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_enaAnd_b;
--reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1(REG,271)@6
reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q <= r_uid172_lzcZ_uid56_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem(DUALMEM,549)
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_reset0 <= areset;
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_ia <= reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q;
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_aa <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdreg_q;
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_ab <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdmux_q;
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 6,
widthad_a => 3,
numwords_a => 7,
width_b => 6,
widthad_b => 3,
numwords_b => 7,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_iq,
address_a => ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_aa,
data_a => ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_ia
);
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_q <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_iq(5 downto 0);
--cstBiasM1_uid11_fpCosPiTest(CONSTANT,10)
cstBiasM1_uid11_fpCosPiTest_q <= "01111110";
--expHardCase_uid59_fpCosPiTest(SUB,58)@15
expHardCase_uid59_fpCosPiTest_a <= STD_LOGIC_VECTOR("0" & cstBiasM1_uid11_fpCosPiTest_q);
expHardCase_uid59_fpCosPiTest_b <= STD_LOGIC_VECTOR("000" & ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_q);
expHardCase_uid59_fpCosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expHardCase_uid59_fpCosPiTest_a) - UNSIGNED(expHardCase_uid59_fpCosPiTest_b));
expHardCase_uid59_fpCosPiTest_q <= expHardCase_uid59_fpCosPiTest_o(8 downto 0);
--expP_uid60_fpCosPiTest(BITSELECT,59)@15
expP_uid60_fpCosPiTest_in <= expHardCase_uid59_fpCosPiTest_q(7 downto 0);
expP_uid60_fpCosPiTest_b <= expP_uid60_fpCosPiTest_in(7 downto 0);
--reg_expP_uid60_fpCosPiTest_0_to_expFracPreRnd_uid71_uid71_fpCosPiTest_1(REG,272)@15
reg_expP_uid60_fpCosPiTest_0_to_expFracPreRnd_uid71_uid71_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expP_uid60_fpCosPiTest_0_to_expFracPreRnd_uid71_uid71_fpCosPiTest_1_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expP_uid60_fpCosPiTest_0_to_expFracPreRnd_uid71_uid71_fpCosPiTest_1_q <= expP_uid60_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--highRes_uid68_fpCosPiTest(BITSELECT,67)@16
highRes_uid68_fpCosPiTest_in <= prodXYTruncFR_uid224_mul2xSinRes_uid66_fpCosPiTest_b(24 downto 0);
highRes_uid68_fpCosPiTest_b <= highRes_uid68_fpCosPiTest_in(24 downto 1);
--lowRes_uid69_fpCosPiTest(BITSELECT,68)@16
lowRes_uid69_fpCosPiTest_in <= prodXYTruncFR_uid224_mul2xSinRes_uid66_fpCosPiTest_b(23 downto 0);
lowRes_uid69_fpCosPiTest_b <= lowRes_uid69_fpCosPiTest_in(23 downto 0);
--fracRCompPreRnd_uid70_fpCosPiTest(MUX,69)@16
fracRCompPreRnd_uid70_fpCosPiTest_s <= normBit_uid67_fpCosPiTest_b;
fracRCompPreRnd_uid70_fpCosPiTest: PROCESS (fracRCompPreRnd_uid70_fpCosPiTest_s, en, lowRes_uid69_fpCosPiTest_b, highRes_uid68_fpCosPiTest_b)
BEGIN
CASE fracRCompPreRnd_uid70_fpCosPiTest_s IS
WHEN "0" => fracRCompPreRnd_uid70_fpCosPiTest_q <= lowRes_uid69_fpCosPiTest_b;
WHEN "1" => fracRCompPreRnd_uid70_fpCosPiTest_q <= highRes_uid68_fpCosPiTest_b;
WHEN OTHERS => fracRCompPreRnd_uid70_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--expFracPreRnd_uid71_uid71_fpCosPiTest(BITJOIN,70)@16
expFracPreRnd_uid71_uid71_fpCosPiTest_q <= reg_expP_uid60_fpCosPiTest_0_to_expFracPreRnd_uid71_uid71_fpCosPiTest_1_q & fracRCompPreRnd_uid70_fpCosPiTest_q;
--expFracComp_uid74_fpCosPiTest(ADD,73)@16
expFracComp_uid74_fpCosPiTest_a <= STD_LOGIC_VECTOR("0" & expFracPreRnd_uid71_uid71_fpCosPiTest_q);
expFracComp_uid74_fpCosPiTest_b <= STD_LOGIC_VECTOR("00000000" & rndExpUpdate_uid72_uid73_fpCosPiTest_q);
expFracComp_uid74_fpCosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expFracComp_uid74_fpCosPiTest_a) + UNSIGNED(expFracComp_uid74_fpCosPiTest_b));
expFracComp_uid74_fpCosPiTest_q <= expFracComp_uid74_fpCosPiTest_o(32 downto 0);
--expRComp_uid76_fpCosPiTest(BITSELECT,75)@16
expRComp_uid76_fpCosPiTest_in <= expFracComp_uid74_fpCosPiTest_q(31 downto 0);
expRComp_uid76_fpCosPiTest_b <= expRComp_uid76_fpCosPiTest_in(31 downto 24);
--fracXIsZero_uid27_fpCosPiTest(LOGICAL,26)@0
fracXIsZero_uid27_fpCosPiTest_a <= fracX_uid7_fpCosPiTest_b;
fracXIsZero_uid27_fpCosPiTest_b <= cstAllZWF_uid9_fpCosPiTest_q;
fracXIsZero_uid27_fpCosPiTest_q <= "1" when fracXIsZero_uid27_fpCosPiTest_a = fracXIsZero_uid27_fpCosPiTest_b else "0";
--InvFracXIsZero_uid29_fpCosPiTest(LOGICAL,28)@0
InvFracXIsZero_uid29_fpCosPiTest_a <= fracXIsZero_uid27_fpCosPiTest_q;
InvFracXIsZero_uid29_fpCosPiTest_q <= not InvFracXIsZero_uid29_fpCosPiTest_a;
--expXIsMax_uid25_fpCosPiTest(LOGICAL,24)@0
expXIsMax_uid25_fpCosPiTest_a <= expX_uid6_fpCosPiTest_b;
expXIsMax_uid25_fpCosPiTest_b <= cstAllOWE_uid8_fpCosPiTest_q;
expXIsMax_uid25_fpCosPiTest_q <= "1" when expXIsMax_uid25_fpCosPiTest_a = expXIsMax_uid25_fpCosPiTest_b else "0";
--exc_N_uid30_fpCosPiTest(LOGICAL,29)@0
exc_N_uid30_fpCosPiTest_a <= expXIsMax_uid25_fpCosPiTest_q;
exc_N_uid30_fpCosPiTest_b <= InvFracXIsZero_uid29_fpCosPiTest_q;
exc_N_uid30_fpCosPiTest_q <= exc_N_uid30_fpCosPiTest_a and exc_N_uid30_fpCosPiTest_b;
--InvExc_N_uid31_fpCosPiTest(LOGICAL,30)@0
InvExc_N_uid31_fpCosPiTest_a <= exc_N_uid30_fpCosPiTest_q;
InvExc_N_uid31_fpCosPiTest_q <= not InvExc_N_uid31_fpCosPiTest_a;
--exc_I_uid28_fpCosPiTest(LOGICAL,27)@0
exc_I_uid28_fpCosPiTest_a <= expXIsMax_uid25_fpCosPiTest_q;
exc_I_uid28_fpCosPiTest_b <= fracXIsZero_uid27_fpCosPiTest_q;
exc_I_uid28_fpCosPiTest_q <= exc_I_uid28_fpCosPiTest_a and exc_I_uid28_fpCosPiTest_b;
--InvExc_I_uid32_fpCosPiTest(LOGICAL,31)@0
InvExc_I_uid32_fpCosPiTest_a <= exc_I_uid28_fpCosPiTest_q;
InvExc_I_uid32_fpCosPiTest_q <= not InvExc_I_uid32_fpCosPiTest_a;
--expXIsZero_uid23_fpCosPiTest(LOGICAL,22)@0
expXIsZero_uid23_fpCosPiTest_a <= expX_uid6_fpCosPiTest_b;
expXIsZero_uid23_fpCosPiTest_b <= cstAllZWE_uid21_fpCosPiTest_q;
expXIsZero_uid23_fpCosPiTest_q <= "1" when expXIsZero_uid23_fpCosPiTest_a = expXIsZero_uid23_fpCosPiTest_b else "0";
--InvExpXIsZero_uid33_fpCosPiTest(LOGICAL,32)@0
InvExpXIsZero_uid33_fpCosPiTest_a <= expXIsZero_uid23_fpCosPiTest_q;
InvExpXIsZero_uid33_fpCosPiTest_q <= not InvExpXIsZero_uid33_fpCosPiTest_a;
--exc_R_uid34_fpCosPiTest(LOGICAL,33)@0
exc_R_uid34_fpCosPiTest_a <= InvExpXIsZero_uid33_fpCosPiTest_q;
exc_R_uid34_fpCosPiTest_b <= InvExc_I_uid32_fpCosPiTest_q;
exc_R_uid34_fpCosPiTest_c <= InvExc_N_uid31_fpCosPiTest_q;
exc_R_uid34_fpCosPiTest_q <= exc_R_uid34_fpCosPiTest_a and exc_R_uid34_fpCosPiTest_b and exc_R_uid34_fpCosPiTest_c;
--ld_exc_R_uid34_fpCosPiTest_q_to_xIsInt_uid80_fpCosPiTest_a(DELAY,337)@0
ld_exc_R_uid34_fpCosPiTest_q_to_xIsInt_uid80_fpCosPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => exc_R_uid34_fpCosPiTest_q, xout => ld_exc_R_uid34_fpCosPiTest_q_to_xIsInt_uid80_fpCosPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--xIsHalf_uid83_fpCosPiTest(LOGICAL,82)@2
xIsHalf_uid83_fpCosPiTest_a <= ld_exc_R_uid34_fpCosPiTest_q_to_xIsInt_uid80_fpCosPiTest_a_q;
xIsHalf_uid83_fpCosPiTest_b <= fxpXFracHalf_uid46_fpCosPiTest_q;
xIsHalf_uid83_fpCosPiTest_c <= InvCosXIsOne_uid77_fpCosPiTest_q;
xIsHalf_uid83_fpCosPiTest_d <= InvXEvenInt_uid81_fpCosPiTest_q;
xIsHalf_uid83_fpCosPiTest_q <= xIsHalf_uid83_fpCosPiTest_a and xIsHalf_uid83_fpCosPiTest_b and xIsHalf_uid83_fpCosPiTest_c and xIsHalf_uid83_fpCosPiTest_d;
--ld_xIsHalf_uid83_fpCosPiTest_q_to_expRPostExc1_uid91_fpCosPiTest_b(DELAY,355)@2
ld_xIsHalf_uid83_fpCosPiTest_q_to_expRPostExc1_uid91_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 14 )
PORT MAP ( xin => xIsHalf_uid83_fpCosPiTest_q, xout => ld_xIsHalf_uid83_fpCosPiTest_q_to_expRPostExc1_uid91_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--expRPostExc1_uid91_fpCosPiTest(MUX,90)@16
expRPostExc1_uid91_fpCosPiTest_s <= ld_xIsHalf_uid83_fpCosPiTest_q_to_expRPostExc1_uid91_fpCosPiTest_b_q;
expRPostExc1_uid91_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expRPostExc1_uid91_fpCosPiTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE expRPostExc1_uid91_fpCosPiTest_s IS
WHEN "0" => expRPostExc1_uid91_fpCosPiTest_q <= expRComp_uid76_fpCosPiTest_b;
WHEN "1" => expRPostExc1_uid91_fpCosPiTest_q <= cstAllZWE_uid21_fpCosPiTest_q;
WHEN OTHERS => expRPostExc1_uid91_fpCosPiTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_nor(LOGICAL,570)
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_nor_a <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_notEnable_q;
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_nor_b <= ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_sticky_ena_q;
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_nor_q <= not (ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_nor_a or ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_nor_b);
--ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_mem_top(CONSTANT,566)
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_mem_top_q <= "01100";
--ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_cmp(LOGICAL,567)
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_cmp_a <= ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_mem_top_q;
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdmux_q);
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_cmp_q <= "1" when ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_cmp_a = ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_cmp_b else "0";
--ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_cmpReg(REG,568)
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_cmpReg_q <= ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_sticky_ena(REG,571)
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_nor_q = "1") THEN
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_sticky_ena_q <= ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_enaAnd(LOGICAL,572)
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_enaAnd_a <= ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_sticky_ena_q;
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_enaAnd_b <= en;
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_enaAnd_q <= ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_enaAnd_a and ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_enaAnd_b;
--ld_expXIsZero_uid23_fpCosPiTest_q_to_xIntOrXZOrCosOne_uid93_fpCosPiTest_b(DELAY,359)@0
ld_expXIsZero_uid23_fpCosPiTest_q_to_xIntOrXZOrCosOne_uid93_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => expXIsZero_uid23_fpCosPiTest_q, xout => ld_expXIsZero_uid23_fpCosPiTest_q_to_xIntOrXZOrCosOne_uid93_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--fxpXFracZero_uid45_fpCosPiTest(LOGICAL,44)@2
fxpXFracZero_uid45_fpCosPiTest_a <= reg_fxpXFrac_uid43_fpCosPiTest_0_to_fxpXFracZero_uid45_fpCosPiTest_1_q;
fxpXFracZero_uid45_fpCosPiTest_b <= STD_LOGIC_VECTOR("0" & cstZwSwF_uid15_fpCosPiTest_q);
fxpXFracZero_uid45_fpCosPiTest_q <= "1" when fxpXFracZero_uid45_fpCosPiTest_a = fxpXFracZero_uid45_fpCosPiTest_b else "0";
--fracZCosNotOne_uid78_fpCosPiTest(LOGICAL,77)@2
fracZCosNotOne_uid78_fpCosPiTest_a <= fxpXFracZero_uid45_fpCosPiTest_q;
fracZCosNotOne_uid78_fpCosPiTest_b <= InvCosXIsOne_uid77_fpCosPiTest_q;
fracZCosNotOne_uid78_fpCosPiTest_q <= fracZCosNotOne_uid78_fpCosPiTest_a and fracZCosNotOne_uid78_fpCosPiTest_b;
--evenIntCosNotOneFZ_uid79_fpCosPiTest(LOGICAL,78)@2
evenIntCosNotOneFZ_uid79_fpCosPiTest_a <= ld_xEvenInt_uid35_fpCosPiTest_c_to_evenIntCosNotOneFZ_uid79_fpCosPiTest_a_q;
evenIntCosNotOneFZ_uid79_fpCosPiTest_b <= fracZCosNotOne_uid78_fpCosPiTest_q;
evenIntCosNotOneFZ_uid79_fpCosPiTest_q <= evenIntCosNotOneFZ_uid79_fpCosPiTest_a or evenIntCosNotOneFZ_uid79_fpCosPiTest_b;
--xIsInt_uid80_fpCosPiTest(LOGICAL,79)@2
xIsInt_uid80_fpCosPiTest_a <= ld_exc_R_uid34_fpCosPiTest_q_to_xIsInt_uid80_fpCosPiTest_a_q;
xIsInt_uid80_fpCosPiTest_b <= evenIntCosNotOneFZ_uid79_fpCosPiTest_q;
xIsInt_uid80_fpCosPiTest_q <= xIsInt_uid80_fpCosPiTest_a and xIsInt_uid80_fpCosPiTest_b;
--xIntOrXZOrCosOne_uid93_fpCosPiTest(LOGICAL,92)@2
xIntOrXZOrCosOne_uid93_fpCosPiTest_a <= xIsInt_uid80_fpCosPiTest_q;
xIntOrXZOrCosOne_uid93_fpCosPiTest_b <= ld_expXIsZero_uid23_fpCosPiTest_q_to_xIntOrXZOrCosOne_uid93_fpCosPiTest_b_q;
xIntOrXZOrCosOne_uid93_fpCosPiTest_c <= ld_cosXIsOne_uid36_fpCosPiTest_c_to_InvCosXIsOne_uid77_fpCosPiTest_a_q;
xIntOrXZOrCosOne_uid93_fpCosPiTest_q <= xIntOrXZOrCosOne_uid93_fpCosPiTest_a or xIntOrXZOrCosOne_uid93_fpCosPiTest_b or xIntOrXZOrCosOne_uid93_fpCosPiTest_c;
--excRNaN_uid84_fpCosPiTest(LOGICAL,83)@0
excRNaN_uid84_fpCosPiTest_a <= exc_N_uid30_fpCosPiTest_q;
excRNaN_uid84_fpCosPiTest_b <= exc_I_uid28_fpCosPiTest_q;
excRNaN_uid84_fpCosPiTest_q <= excRNaN_uid84_fpCosPiTest_a or excRNaN_uid84_fpCosPiTest_b;
--rInfOrNaN_uid92_fpCosPiTest(LOGICAL,91)@0
rInfOrNaN_uid92_fpCosPiTest_a <= GND_q;
rInfOrNaN_uid92_fpCosPiTest_b <= excRNaN_uid84_fpCosPiTest_q;
rInfOrNaN_uid92_fpCosPiTest_q <= rInfOrNaN_uid92_fpCosPiTest_a or rInfOrNaN_uid92_fpCosPiTest_b;
--ld_rInfOrNaN_uid92_fpCosPiTest_q_to_join_uid94_fpCosPiTest_a(DELAY,361)@0
ld_rInfOrNaN_uid92_fpCosPiTest_q_to_join_uid94_fpCosPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => rInfOrNaN_uid92_fpCosPiTest_q, xout => ld_rInfOrNaN_uid92_fpCosPiTest_q_to_join_uid94_fpCosPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--join_uid94_fpCosPiTest(BITJOIN,93)@2
join_uid94_fpCosPiTest_q <= xIntOrXZOrCosOne_uid93_fpCosPiTest_q & ld_rInfOrNaN_uid92_fpCosPiTest_q_to_join_uid94_fpCosPiTest_a_q;
--reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1(REG,274)@2
reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q <= join_uid94_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt(COUNTER,562)
-- every=1, low=0, high=12, step=1, init=1
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt_i = 11 THEN
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt_eq <= '1';
ELSE
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt_eq = '1') THEN
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt_i <= ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt_i - 12;
ELSE
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt_i <= ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt_i,4));
--ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdreg(REG,563)
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdreg_q <= ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdmux(MUX,564)
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdmux_s <= en;
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdmux: PROCESS (ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdmux_s, ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdreg_q, ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt_q)
BEGIN
CASE ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdmux_s IS
WHEN "0" => ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdmux_q <= ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdreg_q;
WHEN "1" => ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdmux_q <= ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem(DUALMEM,561)
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_reset0 <= areset;
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_ia <= reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q;
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_aa <= ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdreg_q;
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_ab <= ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdmux_q;
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 2,
widthad_a => 4,
numwords_a => 13,
width_b => 2,
widthad_b => 4,
numwords_b => 13,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_iq,
address_a => ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_aa,
data_a => ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_ia
);
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_q <= ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_iq(1 downto 0);
--expRPostExc_uid95_fpCosPiTest(MUX,94)@17
expRPostExc_uid95_fpCosPiTest_s <= ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_q;
expRPostExc_uid95_fpCosPiTest: PROCESS (expRPostExc_uid95_fpCosPiTest_s, en, expRPostExc1_uid91_fpCosPiTest_q, cstAllOWE_uid8_fpCosPiTest_q, cstBias_uid10_fpCosPiTest_q, cstBias_uid10_fpCosPiTest_q)
BEGIN
CASE expRPostExc_uid95_fpCosPiTest_s IS
WHEN "00" => expRPostExc_uid95_fpCosPiTest_q <= expRPostExc1_uid91_fpCosPiTest_q;
WHEN "01" => expRPostExc_uid95_fpCosPiTest_q <= cstAllOWE_uid8_fpCosPiTest_q;
WHEN "10" => expRPostExc_uid95_fpCosPiTest_q <= cstBias_uid10_fpCosPiTest_q;
WHEN "11" => expRPostExc_uid95_fpCosPiTest_q <= cstBias_uid10_fpCosPiTest_q;
WHEN OTHERS => expRPostExc_uid95_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--oneFracRPostExc2_uid87_fpCosPiTest(CONSTANT,86)
oneFracRPostExc2_uid87_fpCosPiTest_q <= "00000000000000000000001";
--fracRComp_uid75_fpCosPiTest(BITSELECT,74)@16
fracRComp_uid75_fpCosPiTest_in <= expFracComp_uid74_fpCosPiTest_q(23 downto 0);
fracRComp_uid75_fpCosPiTest_b <= fracRComp_uid75_fpCosPiTest_in(23 downto 1);
--reg_xIsHalf_uid83_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_5(REG,243)@2
reg_xIsHalf_uid83_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xIsHalf_uid83_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_5_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xIsHalf_uid83_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_5_q <= xIsHalf_uid83_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--reg_expXIsZero_uid23_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_4(REG,242)@2
reg_expXIsZero_uid23_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expXIsZero_uid23_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_4_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expXIsZero_uid23_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_4_q <= ld_expXIsZero_uid23_fpCosPiTest_q_to_xIntOrXZOrCosOne_uid93_fpCosPiTest_b_q;
END IF;
END IF;
END PROCESS;
--reg_fxpXFracHalf_uid46_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_3(REG,241)@2
reg_fxpXFracHalf_uid46_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fxpXFracHalf_uid46_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_3_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fxpXFracHalf_uid46_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_3_q <= fxpXFracHalf_uid46_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--reg_xIsInt_uid80_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_2(REG,240)@2
reg_xIsInt_uid80_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xIsInt_uid80_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xIsInt_uid80_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_2_q <= xIsInt_uid80_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--reg_cosXIsOne_uid36_fpCosPiTest_1_to_bigCond_uid85_fpCosPiTest_1(REG,239)@0
reg_cosXIsOne_uid36_fpCosPiTest_1_to_bigCond_uid85_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cosXIsOne_uid36_fpCosPiTest_1_to_bigCond_uid85_fpCosPiTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cosXIsOne_uid36_fpCosPiTest_1_to_bigCond_uid85_fpCosPiTest_1_q <= cosXIsOne_uid36_fpCosPiTest_c;
END IF;
END IF;
END PROCESS;
--ld_reg_cosXIsOne_uid36_fpCosPiTest_1_to_bigCond_uid85_fpCosPiTest_1_q_to_bigCond_uid85_fpCosPiTest_a(DELAY,346)@1
ld_reg_cosXIsOne_uid36_fpCosPiTest_1_to_bigCond_uid85_fpCosPiTest_1_q_to_bigCond_uid85_fpCosPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => reg_cosXIsOne_uid36_fpCosPiTest_1_to_bigCond_uid85_fpCosPiTest_1_q, xout => ld_reg_cosXIsOne_uid36_fpCosPiTest_1_to_bigCond_uid85_fpCosPiTest_1_q_to_bigCond_uid85_fpCosPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--bigCond_uid85_fpCosPiTest(LOGICAL,84)@3
bigCond_uid85_fpCosPiTest_a <= ld_reg_cosXIsOne_uid36_fpCosPiTest_1_to_bigCond_uid85_fpCosPiTest_1_q_to_bigCond_uid85_fpCosPiTest_a_q;
bigCond_uid85_fpCosPiTest_b <= reg_xIsInt_uid80_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_2_q;
bigCond_uid85_fpCosPiTest_c <= reg_fxpXFracHalf_uid46_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_3_q;
bigCond_uid85_fpCosPiTest_d <= reg_expXIsZero_uid23_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_4_q;
bigCond_uid85_fpCosPiTest_f <= reg_xIsHalf_uid83_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_5_q;
bigCond_uid85_fpCosPiTest_g <= GND_q;
bigCond_uid85_fpCosPiTest_q <= bigCond_uid85_fpCosPiTest_a or bigCond_uid85_fpCosPiTest_b or bigCond_uid85_fpCosPiTest_c or bigCond_uid85_fpCosPiTest_d or bigCond_uid85_fpCosPiTest_f or bigCond_uid85_fpCosPiTest_g;
--ld_bigCond_uid85_fpCosPiTest_q_to_fracRPostExc1_uid86_fpCosPiTest_b(DELAY,351)@3
ld_bigCond_uid85_fpCosPiTest_q_to_fracRPostExc1_uid86_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 13 )
PORT MAP ( xin => bigCond_uid85_fpCosPiTest_q, xout => ld_bigCond_uid85_fpCosPiTest_q_to_fracRPostExc1_uid86_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--fracRPostExc1_uid86_fpCosPiTest(MUX,85)@16
fracRPostExc1_uid86_fpCosPiTest_s <= ld_bigCond_uid85_fpCosPiTest_q_to_fracRPostExc1_uid86_fpCosPiTest_b_q;
fracRPostExc1_uid86_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
fracRPostExc1_uid86_fpCosPiTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE fracRPostExc1_uid86_fpCosPiTest_s IS
WHEN "0" => fracRPostExc1_uid86_fpCosPiTest_q <= fracRComp_uid75_fpCosPiTest_b;
WHEN "1" => fracRPostExc1_uid86_fpCosPiTest_q <= cstAllZWF_uid9_fpCosPiTest_q;
WHEN OTHERS => fracRPostExc1_uid86_fpCosPiTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--reg_excRNaN_uid84_fpCosPiTest_0_to_fracRPostExc_uid88_fpCosPiTest_1(REG,273)@0
reg_excRNaN_uid84_fpCosPiTest_0_to_fracRPostExc_uid88_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_excRNaN_uid84_fpCosPiTest_0_to_fracRPostExc_uid88_fpCosPiTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_excRNaN_uid84_fpCosPiTest_0_to_fracRPostExc_uid88_fpCosPiTest_1_q <= excRNaN_uid84_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_excRNaN_uid84_fpCosPiTest_0_to_fracRPostExc_uid88_fpCosPiTest_1_q_to_fracRPostExc_uid88_fpCosPiTest_b(DELAY,353)@1
ld_reg_excRNaN_uid84_fpCosPiTest_0_to_fracRPostExc_uid88_fpCosPiTest_1_q_to_fracRPostExc_uid88_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 16 )
PORT MAP ( xin => reg_excRNaN_uid84_fpCosPiTest_0_to_fracRPostExc_uid88_fpCosPiTest_1_q, xout => ld_reg_excRNaN_uid84_fpCosPiTest_0_to_fracRPostExc_uid88_fpCosPiTest_1_q_to_fracRPostExc_uid88_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--fracRPostExc_uid88_fpCosPiTest(MUX,87)@17
fracRPostExc_uid88_fpCosPiTest_s <= ld_reg_excRNaN_uid84_fpCosPiTest_0_to_fracRPostExc_uid88_fpCosPiTest_1_q_to_fracRPostExc_uid88_fpCosPiTest_b_q;
fracRPostExc_uid88_fpCosPiTest: PROCESS (fracRPostExc_uid88_fpCosPiTest_s, en, fracRPostExc1_uid86_fpCosPiTest_q, oneFracRPostExc2_uid87_fpCosPiTest_q)
BEGIN
CASE fracRPostExc_uid88_fpCosPiTest_s IS
WHEN "0" => fracRPostExc_uid88_fpCosPiTest_q <= fracRPostExc1_uid86_fpCosPiTest_q;
WHEN "1" => fracRPostExc_uid88_fpCosPiTest_q <= oneFracRPostExc2_uid87_fpCosPiTest_q;
WHEN OTHERS => fracRPostExc_uid88_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--R_uid102_fpCosPiTest(BITJOIN,101)@17
R_uid102_fpCosPiTest_q <= ld_signR_uid101_fpCosPiTest_q_to_R_uid102_fpCosPiTest_c_q & expRPostExc_uid95_fpCosPiTest_q & fracRPostExc_uid88_fpCosPiTest_q;
--xOut(GPOUT,4)@17
q <= R_uid102_fpCosPiTest_q;
end normal;
|
-----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Release Version 13.1
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing device programming or simulation files), and
-- any associated documentation or information are expressly subject to the
-- terms and conditions of the Altera Program License Subscription Agreement,
-- Altera MegaCore Function License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for the sole
-- purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
-----------------------------------------------------------------------------
-- VHDL created from fp_cospi_s5
-- VHDL created on Wed Feb 27 15:22:33 2013
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.all;
use std.TextIO.all;
use work.dspba_library_package.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
entity fp_cospi_s5 is
port (
a : in std_logic_vector(31 downto 0);
en : in std_logic_vector(0 downto 0);
q : out std_logic_vector(31 downto 0);
clk : in std_logic;
areset : in std_logic
);
end;
architecture normal of fp_cospi_s5 is
attribute altera_attribute : string;
attribute altera_attribute of normal : architecture is "-name NOT_GATE_PUSH_BACK OFF; -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON; -name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410";
signal GND_q : std_logic_vector (0 downto 0);
signal VCC_q : std_logic_vector (0 downto 0);
signal cstAllOWE_uid8_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal cstAllZWF_uid9_fpCosPiTest_q : std_logic_vector (22 downto 0);
signal cstBias_uid10_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal cstBiasM1_uid11_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal cstBiasPwF_uid12_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal biasMwShiftMO_uid13_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal cst01pWShift_uid14_fpCosPiTest_q : std_logic_vector (12 downto 0);
signal cstZwSwF_uid15_fpCosPiTest_q : std_logic_vector (34 downto 0);
signal cstAllZWE_uid21_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal rangeReducedFxPX_uid51_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal rangeReducedFxPX_uid51_fpCosPiTest_q : std_logic_vector (35 downto 0);
signal fracRPostExc1_uid86_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal fracRPostExc1_uid86_fpCosPiTest_q : std_logic_vector (22 downto 0);
signal oneFracRPostExc2_uid87_fpCosPiTest_q : std_logic_vector (22 downto 0);
signal expRPostExc1_uid91_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal expRPostExc1_uid91_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal signRComp_uid99_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal signRComp_uid99_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal signRComp_uid99_fpCosPiTest_c : std_logic_vector(0 downto 0);
signal signRComp_uid99_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal signR_uid101_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal signR_uid101_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal signR_uid101_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal leftShiftStage0Idx1Pad16_uid105_fxpX_uid41_fpCosPiTest_q : std_logic_vector (15 downto 0);
signal leftShiftStage0Idx2Pad32_uid108_fxpX_uid41_fpCosPiTest_q : std_logic_vector (31 downto 0);
signal leftShiftStage0Idx3_uid111_fxpX_uid41_fpCosPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage1Idx1Pad4_uid114_fxpX_uid41_fpCosPiTest_q : std_logic_vector (3 downto 0);
signal leftShiftStage1Idx3Pad12_uid120_fxpX_uid41_fpCosPiTest_q : std_logic_vector (11 downto 0);
signal leftShiftStage2Idx2Pad2_uid128_fxpX_uid41_fpCosPiTest_q : std_logic_vector (1 downto 0);
signal leftShiftStage2Idx3Pad3_uid131_fxpX_uid41_fpCosPiTest_q : std_logic_vector (2 downto 0);
signal mO_uid140_lzcZ_uid56_fpCosPiTest_q : std_logic_vector (28 downto 0);
signal memoryC2_uid209_sinPiZTableGenerator_q : std_logic_vector(13 downto 0);
signal prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_a : std_logic_vector (23 downto 0);
signal prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_b : std_logic_vector (24 downto 0);
signal prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_s1 : std_logic_vector (48 downto 0);
signal prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_pr : UNSIGNED (48 downto 0);
signal prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_q : std_logic_vector (48 downto 0);
signal prodXY_uid226_pT1_uid211_sinPiZPolyEval_a : std_logic_vector (13 downto 0);
signal prodXY_uid226_pT1_uid211_sinPiZPolyEval_b : std_logic_vector (13 downto 0);
signal prodXY_uid226_pT1_uid211_sinPiZPolyEval_s1 : std_logic_vector (27 downto 0);
signal prodXY_uid226_pT1_uid211_sinPiZPolyEval_pr : SIGNED (28 downto 0);
signal prodXY_uid226_pT1_uid211_sinPiZPolyEval_q : std_logic_vector (27 downto 0);
signal prodXY_uid229_pT2_uid217_sinPiZPolyEval_a : std_logic_vector (15 downto 0);
signal prodXY_uid229_pT2_uid217_sinPiZPolyEval_b : std_logic_vector (22 downto 0);
signal prodXY_uid229_pT2_uid217_sinPiZPolyEval_s1 : std_logic_vector (38 downto 0);
signal prodXY_uid229_pT2_uid217_sinPiZPolyEval_pr : SIGNED (39 downto 0);
signal prodXY_uid229_pT2_uid217_sinPiZPolyEval_q : std_logic_vector (38 downto 0);
signal reg_leftShiftStageSel3Dto2_uid123_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_2_q : std_logic_vector (36 downto 0);
signal reg_leftShiftStage1Idx1_uid116_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_3_q : std_logic_vector (36 downto 0);
signal reg_leftShiftStage1Idx2_uid119_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_4_q : std_logic_vector (36 downto 0);
signal reg_leftShiftStage1Idx3_uid122_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_5_q : std_logic_vector (36 downto 0);
signal reg_leftShiftStageSel1Dto0_uid134_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_fxpXFrac_uid43_fpCosPiTest_0_to_fxpXFracZero_uid45_fpCosPiTest_1_q : std_logic_vector (35 downto 0);
signal reg_cosXIsOne_uid36_fpCosPiTest_1_to_bigCond_uid85_fpCosPiTest_1_q : std_logic_vector (0 downto 0);
signal reg_xIsInt_uid80_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_2_q : std_logic_vector (0 downto 0);
signal reg_fxpXFracHalf_uid46_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_3_q : std_logic_vector (0 downto 0);
signal reg_expXIsZero_uid23_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_4_q : std_logic_vector (0 downto 0);
signal reg_xIsHalf_uid83_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_5_q : std_logic_vector (0 downto 0);
signal reg_pad_o_uid16_uid47_fpCosPiTest_0_to_oMFxpXFrac_uid47_fpCosPiTest_0_q : std_logic_vector (36 downto 0);
signal reg_pad_half_uid17_uid52_fpCosPiTest_0_to_z_halfMRRFxPXE_uid52_fpCosPiTest_0_q : std_logic_vector (35 downto 0);
signal reg_rVStage_uid138_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid139_lzcZ_uid56_fpCosPiTest_1_q : std_logic_vector (31 downto 0);
signal reg_cStage_uid142_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid144_lzcZ_uid56_fpCosPiTest_3_q : std_logic_vector (31 downto 0);
signal reg_rVStage_uid146_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid147_lzcZ_uid56_fpCosPiTest_1_q : std_logic_vector (15 downto 0);
signal reg_vStage_uid148_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid150_lzcZ_uid56_fpCosPiTest_3_q : std_logic_vector (15 downto 0);
signal reg_rVStage_uid158_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid159_lzcZ_uid56_fpCosPiTest_1_q : std_logic_vector (3 downto 0);
signal reg_vStage_uid160_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid162_lzcZ_uid56_fpCosPiTest_3_q : std_logic_vector (3 downto 0);
signal reg_vCount_uid153_lzcZ_uid56_fpCosPiTest_0_to_r_uid172_lzcZ_uid56_fpCosPiTest_3_q : std_logic_vector (0 downto 0);
signal reg_leftShiftStageSel3Dto2_uid193_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_2_q : std_logic_vector (34 downto 0);
signal reg_leftShiftStage1Idx1_uid186_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_3_q : std_logic_vector (34 downto 0);
signal reg_leftShiftStage1Idx2_uid189_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_4_q : std_logic_vector (34 downto 0);
signal reg_leftShiftStage1Idx3_uid192_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_5_q : std_logic_vector (34 downto 0);
signal reg_leftShiftStageSel1Dto0_uid204_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_zAddr_uid62_fpCosPiTest_0_to_memoryC2_uid209_sinPiZTableGenerator_0_q : std_logic_vector (6 downto 0);
signal reg_yT1_uid210_sinPiZPolyEval_0_to_prodXY_uid226_pT1_uid211_sinPiZPolyEval_0_q : std_logic_vector (13 downto 0);
signal reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_q : std_logic_vector (15 downto 0);
signal reg_s1_uid212_uid215_sinPiZPolyEval_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_1_q : std_logic_vector (22 downto 0);
signal reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_q : std_logic_vector (23 downto 0);
signal reg_fxpSinRes_uid65_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_1_q : std_logic_vector (24 downto 0);
signal reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q : std_logic_vector (5 downto 0);
signal reg_expP_uid60_fpCosPiTest_0_to_expFracPreRnd_uid71_uid71_fpCosPiTest_1_q : std_logic_vector (7 downto 0);
signal reg_excRNaN_uid84_fpCosPiTest_0_to_fracRPostExc_uid88_fpCosPiTest_1_q : std_logic_vector (0 downto 0);
signal reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q : std_logic_vector (1 downto 0);
signal ld_FxpXFrac35_uid44_fpCosPiTest_b_to_rangeReducedFxPX_uid51_fpCosPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_fxpXFrac_uid43_fpCosPiTest_b_to_rangeReducedFxPX_uid51_fpCosPiTest_c_q : std_logic_vector (35 downto 0);
signal ld_cosXIsOne_uid36_fpCosPiTest_c_to_InvCosXIsOne_uid77_fpCosPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_xEvenInt_uid35_fpCosPiTest_c_to_evenIntCosNotOneFZ_uid79_fpCosPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_exc_R_uid34_fpCosPiTest_q_to_xIsInt_uid80_fpCosPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_reg_cosXIsOne_uid36_fpCosPiTest_1_to_bigCond_uid85_fpCosPiTest_1_q_to_bigCond_uid85_fpCosPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_bigCond_uid85_fpCosPiTest_q_to_fracRPostExc1_uid86_fpCosPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_reg_excRNaN_uid84_fpCosPiTest_0_to_fracRPostExc_uid88_fpCosPiTest_1_q_to_fracRPostExc_uid88_fpCosPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_xIsHalf_uid83_fpCosPiTest_q_to_expRPostExc1_uid91_fpCosPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_expXIsZero_uid23_fpCosPiTest_q_to_xIntOrXZOrCosOne_uid93_fpCosPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_rInfOrNaN_uid92_fpCosPiTest_q_to_join_uid94_fpCosPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_xParityXorHalfParity_uid96_fpCosPiTest_q_to_signRComp_uid99_fpCosPiTest_c_q : std_logic_vector (0 downto 0);
signal ld_fxpXFracHalf_uid46_fpCosPiTest_q_to_InvFxpXFracHalf_uid100_fpCosPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_signR_uid101_fpCosPiTest_q_to_R_uid102_fpCosPiTest_c_q : std_logic_vector (0 downto 0);
signal ld_vCount_uid147_lzcZ_uid56_fpCosPiTest_q_to_r_uid172_lzcZ_uid56_fpCosPiTest_e_q : std_logic_vector (0 downto 0);
signal ld_vCount_uid139_lzcZ_uid56_fpCosPiTest_q_to_r_uid172_lzcZ_uid56_fpCosPiTest_f_q : std_logic_vector (0 downto 0);
signal ld_X18dto0_uid176_alignedZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx1_uid177_alignedZ_uid57_fpCosPiTest_b_q : std_logic_vector (18 downto 0);
signal ld_vStage_uid141_lzcZ_uid56_fpCosPiTest_b_to_leftShiftStage0Idx2_uid180_alignedZ_uid57_fpCosPiTest_b_q : std_logic_vector (2 downto 0);
signal ld_z_uid54_fpCosPiTest_b_to_leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_c_q : std_logic_vector (34 downto 0);
signal ld_reg_yT1_uid210_sinPiZPolyEval_0_to_prodXY_uid226_pT1_uid211_sinPiZPolyEval_0_q_to_prodXY_uid226_pT1_uid211_sinPiZPolyEval_a_q : std_logic_vector (13 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_reset0 : std_logic;
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_ia : std_logic_vector (5 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_iq : std_logic_vector (5 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_q : std_logic_vector (5 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt_eq : std_logic;
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_mem_top_q : std_logic_vector (3 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve : boolean;
attribute preserve of ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_sticky_ena_q : signal is true;
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_reset0 : std_logic;
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_ia : std_logic_vector (1 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_iq : std_logic_vector (1 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_q : std_logic_vector (1 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt_eq : std_logic;
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_mem_top_q : std_logic_vector (4 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_sticky_ena_q : signal is true;
signal ld_X18dto0_uid176_alignedZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx1_uid177_alignedZ_uid57_fpCosPiTest_b_inputreg_q : std_logic_vector (18 downto 0);
signal ld_z_uid54_fpCosPiTest_b_to_leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_c_inputreg_q : std_logic_vector (34 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_reset0 : std_logic;
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_ia : std_logic_vector (6 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_iq : std_logic_vector (6 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_q : std_logic_vector (6 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_sticky_ena_q : signal is true;
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_reset0 : std_logic;
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_ia : std_logic_vector (6 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_aa : std_logic_vector (1 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_ab : std_logic_vector (1 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_iq : std_logic_vector (6 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_q : std_logic_vector (6 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt_q : std_logic_vector(1 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt_i : unsigned(1 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt_eq : std_logic;
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdreg_q : std_logic_vector (1 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_mem_top_q : std_logic_vector (2 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_sticky_ena_q : signal is true;
signal ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_inputreg_q : std_logic_vector (15 downto 0);
signal ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_reset0 : std_logic;
signal ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_ia : std_logic_vector (15 downto 0);
signal ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_aa : std_logic_vector (1 downto 0);
signal ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_ab : std_logic_vector (1 downto 0);
signal ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_iq : std_logic_vector (15 downto 0);
signal ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_q : std_logic_vector (15 downto 0);
signal ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_sticky_ena_q : signal is true;
signal ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_inputreg_q : std_logic_vector (23 downto 0);
signal ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_reset0 : std_logic;
signal ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_ia : std_logic_vector (23 downto 0);
signal ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_aa : std_logic_vector (1 downto 0);
signal ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_ab : std_logic_vector (1 downto 0);
signal ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_iq : std_logic_vector (23 downto 0);
signal ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_q : std_logic_vector (23 downto 0);
signal ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_sticky_ena_q : signal is true;
signal pad_o_uid16_uid47_fpCosPiTest_q : std_logic_vector (36 downto 0);
signal pad_half_uid17_uid52_fpCosPiTest_q : std_logic_vector (35 downto 0);
signal bigCond_uid85_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal bigCond_uid85_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal bigCond_uid85_fpCosPiTest_c : std_logic_vector(0 downto 0);
signal bigCond_uid85_fpCosPiTest_d : std_logic_vector(0 downto 0);
signal bigCond_uid85_fpCosPiTest_f : std_logic_vector(0 downto 0);
signal bigCond_uid85_fpCosPiTest_g : std_logic_vector(0 downto 0);
signal bigCond_uid85_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal InvCosXIsOne_uid77_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal InvCosXIsOne_uid77_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal InvXEvenInt_uid81_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal InvXEvenInt_uid81_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal InvFxpXFracHalf_uid100_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal InvFxpXFracHalf_uid100_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal cstHalfwSwFP1_uid18_fpCosPiTest_q : std_logic_vector (35 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_notEnable_a : std_logic_vector(0 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_notEnable_q : std_logic_vector(0 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdmux_q : std_logic_vector (1 downto 0);
signal expX_uid6_fpCosPiTest_in : std_logic_vector (30 downto 0);
signal expX_uid6_fpCosPiTest_b : std_logic_vector (7 downto 0);
signal fracX_uid7_fpCosPiTest_in : std_logic_vector (22 downto 0);
signal fracX_uid7_fpCosPiTest_b : std_logic_vector (22 downto 0);
signal expXIsZero_uid23_fpCosPiTest_a : std_logic_vector(7 downto 0);
signal expXIsZero_uid23_fpCosPiTest_b : std_logic_vector(7 downto 0);
signal expXIsZero_uid23_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal expXIsMax_uid25_fpCosPiTest_a : std_logic_vector(7 downto 0);
signal expXIsMax_uid25_fpCosPiTest_b : std_logic_vector(7 downto 0);
signal expXIsMax_uid25_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal fracXIsZero_uid27_fpCosPiTest_a : std_logic_vector(22 downto 0);
signal fracXIsZero_uid27_fpCosPiTest_b : std_logic_vector(22 downto 0);
signal fracXIsZero_uid27_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal exc_I_uid28_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal exc_I_uid28_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal exc_I_uid28_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal xEvenInt_uid35_fpCosPiTest_a : std_logic_vector(10 downto 0);
signal xEvenInt_uid35_fpCosPiTest_b : std_logic_vector(10 downto 0);
signal xEvenInt_uid35_fpCosPiTest_o : std_logic_vector (10 downto 0);
signal xEvenInt_uid35_fpCosPiTest_cin : std_logic_vector (0 downto 0);
signal xEvenInt_uid35_fpCosPiTest_c : std_logic_vector (0 downto 0);
signal cosXIsOne_uid36_fpCosPiTest_a : std_logic_vector(10 downto 0);
signal cosXIsOne_uid36_fpCosPiTest_b : std_logic_vector(10 downto 0);
signal cosXIsOne_uid36_fpCosPiTest_o : std_logic_vector (10 downto 0);
signal cosXIsOne_uid36_fpCosPiTest_cin : std_logic_vector (0 downto 0);
signal cosXIsOne_uid36_fpCosPiTest_c : std_logic_vector (0 downto 0);
signal shiftValFxPX_uid38_fpCosPiTest_a : std_logic_vector(8 downto 0);
signal shiftValFxPX_uid38_fpCosPiTest_b : std_logic_vector(8 downto 0);
signal shiftValFxPX_uid38_fpCosPiTest_o : std_logic_vector (8 downto 0);
signal shiftValFxPX_uid38_fpCosPiTest_q : std_logic_vector (8 downto 0);
signal fxpXFracZero_uid45_fpCosPiTest_a : std_logic_vector(35 downto 0);
signal fxpXFracZero_uid45_fpCosPiTest_b : std_logic_vector(35 downto 0);
signal fxpXFracZero_uid45_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal fxpXFracHalf_uid46_fpCosPiTest_a : std_logic_vector(35 downto 0);
signal fxpXFracHalf_uid46_fpCosPiTest_b : std_logic_vector(35 downto 0);
signal fxpXFracHalf_uid46_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal oMFxpXFrac_uid47_fpCosPiTest_a : std_logic_vector(37 downto 0);
signal oMFxpXFrac_uid47_fpCosPiTest_b : std_logic_vector(37 downto 0);
signal oMFxpXFrac_uid47_fpCosPiTest_o : std_logic_vector (37 downto 0);
signal oMFxpXFrac_uid47_fpCosPiTest_q : std_logic_vector (37 downto 0);
signal z_halfMRRFxPXE_uid52_fpCosPiTest_a : std_logic_vector(36 downto 0);
signal z_halfMRRFxPXE_uid52_fpCosPiTest_b : std_logic_vector(36 downto 0);
signal z_halfMRRFxPXE_uid52_fpCosPiTest_o : std_logic_vector (36 downto 0);
signal z_halfMRRFxPXE_uid52_fpCosPiTest_q : std_logic_vector (36 downto 0);
signal expHardCase_uid59_fpCosPiTest_a : std_logic_vector(8 downto 0);
signal expHardCase_uid59_fpCosPiTest_b : std_logic_vector(8 downto 0);
signal expHardCase_uid59_fpCosPiTest_o : std_logic_vector (8 downto 0);
signal expHardCase_uid59_fpCosPiTest_q : std_logic_vector (8 downto 0);
signal fracZCosNotOne_uid78_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal fracZCosNotOne_uid78_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal fracZCosNotOne_uid78_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal evenIntCosNotOneFZ_uid79_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal evenIntCosNotOneFZ_uid79_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal evenIntCosNotOneFZ_uid79_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal xIsInt_uid80_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal xIsInt_uid80_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal xIsInt_uid80_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal xIsHalf_uid83_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal xIsHalf_uid83_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal xIsHalf_uid83_fpCosPiTest_c : std_logic_vector(0 downto 0);
signal xIsHalf_uid83_fpCosPiTest_d : std_logic_vector(0 downto 0);
signal xIsHalf_uid83_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal fracRPostExc_uid88_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal fracRPostExc_uid88_fpCosPiTest_q : std_logic_vector (22 downto 0);
signal xIntOrXZOrCosOne_uid93_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal xIntOrXZOrCosOne_uid93_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal xIntOrXZOrCosOne_uid93_fpCosPiTest_c : std_logic_vector(0 downto 0);
signal xIntOrXZOrCosOne_uid93_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal expRPostExc_uid95_fpCosPiTest_s : std_logic_vector (1 downto 0);
signal expRPostExc_uid95_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_q : std_logic_vector (36 downto 0);
signal vCount_uid139_lzcZ_uid56_fpCosPiTest_a : std_logic_vector(31 downto 0);
signal vCount_uid139_lzcZ_uid56_fpCosPiTest_b : std_logic_vector(31 downto 0);
signal vCount_uid139_lzcZ_uid56_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid144_lzcZ_uid56_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid144_lzcZ_uid56_fpCosPiTest_q : std_logic_vector (31 downto 0);
signal vCount_uid147_lzcZ_uid56_fpCosPiTest_a : std_logic_vector(15 downto 0);
signal vCount_uid147_lzcZ_uid56_fpCosPiTest_b : std_logic_vector(15 downto 0);
signal vCount_uid147_lzcZ_uid56_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid150_lzcZ_uid56_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid150_lzcZ_uid56_fpCosPiTest_q : std_logic_vector (15 downto 0);
signal vCount_uid159_lzcZ_uid56_fpCosPiTest_a : std_logic_vector(3 downto 0);
signal vCount_uid159_lzcZ_uid56_fpCosPiTest_b : std_logic_vector(3 downto 0);
signal vCount_uid159_lzcZ_uid56_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid162_lzcZ_uid56_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid162_lzcZ_uid56_fpCosPiTest_q : std_logic_vector (3 downto 0);
signal leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_q : std_logic_vector (34 downto 0);
signal memoryC0_uid207_sinPiZTableGenerator_q : std_logic_vector(28 downto 0);
signal memoryC1_uid208_sinPiZTableGenerator_q : std_logic_vector(20 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal leftShiftStage0Idx1_uid177_alignedZ_uid57_fpCosPiTest_q : std_logic_vector (34 downto 0);
signal leftShiftStage0Idx2_uid180_alignedZ_uid57_fpCosPiTest_q : std_logic_vector (34 downto 0);
signal prodXYTruncFR_uid224_mul2xSinRes_uid66_fpCosPiTest_in : std_logic_vector (48 downto 0);
signal prodXYTruncFR_uid224_mul2xSinRes_uid66_fpCosPiTest_b : std_logic_vector (25 downto 0);
signal prodXYTruncFR_uid227_pT1_uid211_sinPiZPolyEval_in : std_logic_vector (27 downto 0);
signal prodXYTruncFR_uid227_pT1_uid211_sinPiZPolyEval_b : std_logic_vector (14 downto 0);
signal prodXYTruncFR_uid230_pT2_uid217_sinPiZPolyEval_in : std_logic_vector (38 downto 0);
signal prodXYTruncFR_uid230_pT2_uid217_sinPiZPolyEval_b : std_logic_vector (23 downto 0);
signal join_uid94_fpCosPiTest_q : std_logic_vector (1 downto 0);
signal R_uid102_fpCosPiTest_q : std_logic_vector (31 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_cmp_a : std_logic_vector(3 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_cmp_b : std_logic_vector(3 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_cmp_a : std_logic_vector(4 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_cmp_b : std_logic_vector(4 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_cmp_a : std_logic_vector(2 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_cmp_b : std_logic_vector(2 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_nor_q : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_nor_q : std_logic_vector(0 downto 0);
signal oFracX_uid37_uid37_fpCosPiTest_q : std_logic_vector (23 downto 0);
signal InvExpXIsZero_uid33_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid33_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid29_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid29_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal InvExc_I_uid32_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal InvExc_I_uid32_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal fxpShifterBits_uid40_fpCosPiTest_in : std_logic_vector (5 downto 0);
signal fxpShifterBits_uid40_fpCosPiTest_b : std_logic_vector (5 downto 0);
signal oMFxpXFrac_uid49_fpCosPiTest_in : std_logic_vector (35 downto 0);
signal oMFxpXFrac_uid49_fpCosPiTest_b : std_logic_vector (35 downto 0);
signal z_uid54_fpCosPiTest_in : std_logic_vector (34 downto 0);
signal z_uid54_fpCosPiTest_b : std_logic_vector (34 downto 0);
signal expP_uid60_fpCosPiTest_in : std_logic_vector (7 downto 0);
signal expP_uid60_fpCosPiTest_b : std_logic_vector (7 downto 0);
signal LeftShiftStage135dto0_uid126_fxpX_uid41_fpCosPiTest_in : std_logic_vector (35 downto 0);
signal LeftShiftStage135dto0_uid126_fxpX_uid41_fpCosPiTest_b : std_logic_vector (35 downto 0);
signal LeftShiftStage134dto0_uid129_fxpX_uid41_fpCosPiTest_in : std_logic_vector (34 downto 0);
signal LeftShiftStage134dto0_uid129_fxpX_uid41_fpCosPiTest_b : std_logic_vector (34 downto 0);
signal LeftShiftStage133dto0_uid132_fxpX_uid41_fpCosPiTest_in : std_logic_vector (33 downto 0);
signal LeftShiftStage133dto0_uid132_fxpX_uid41_fpCosPiTest_b : std_logic_vector (33 downto 0);
signal rVStage_uid146_lzcZ_uid56_fpCosPiTest_in : std_logic_vector (31 downto 0);
signal rVStage_uid146_lzcZ_uid56_fpCosPiTest_b : std_logic_vector (15 downto 0);
signal vStage_uid148_lzcZ_uid56_fpCosPiTest_in : std_logic_vector (15 downto 0);
signal vStage_uid148_lzcZ_uid56_fpCosPiTest_b : std_logic_vector (15 downto 0);
signal rVStage_uid152_lzcZ_uid56_fpCosPiTest_in : std_logic_vector (15 downto 0);
signal rVStage_uid152_lzcZ_uid56_fpCosPiTest_b : std_logic_vector (7 downto 0);
signal vStage_uid154_lzcZ_uid56_fpCosPiTest_in : std_logic_vector (7 downto 0);
signal vStage_uid154_lzcZ_uid56_fpCosPiTest_b : std_logic_vector (7 downto 0);
signal rVStage_uid164_lzcZ_uid56_fpCosPiTest_in : std_logic_vector (3 downto 0);
signal rVStage_uid164_lzcZ_uid56_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal vStage_uid166_lzcZ_uid56_fpCosPiTest_in : std_logic_vector (1 downto 0);
signal vStage_uid166_lzcZ_uid56_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal LeftShiftStage133dto0_uid196_alignedZ_uid57_fpCosPiTest_in : std_logic_vector (33 downto 0);
signal LeftShiftStage133dto0_uid196_alignedZ_uid57_fpCosPiTest_b : std_logic_vector (33 downto 0);
signal LeftShiftStage132dto0_uid199_alignedZ_uid57_fpCosPiTest_in : std_logic_vector (32 downto 0);
signal LeftShiftStage132dto0_uid199_alignedZ_uid57_fpCosPiTest_b : std_logic_vector (32 downto 0);
signal LeftShiftStage131dto0_uid202_alignedZ_uid57_fpCosPiTest_in : std_logic_vector (31 downto 0);
signal LeftShiftStage131dto0_uid202_alignedZ_uid57_fpCosPiTest_b : std_logic_vector (31 downto 0);
signal normBit_uid67_fpCosPiTest_in : std_logic_vector (25 downto 0);
signal normBit_uid67_fpCosPiTest_b : std_logic_vector (0 downto 0);
signal highRes_uid68_fpCosPiTest_in : std_logic_vector (24 downto 0);
signal highRes_uid68_fpCosPiTest_b : std_logic_vector (23 downto 0);
signal lowRes_uid69_fpCosPiTest_in : std_logic_vector (23 downto 0);
signal lowRes_uid69_fpCosPiTest_b : std_logic_vector (23 downto 0);
signal lowRangeB_uid212_sinPiZPolyEval_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid212_sinPiZPolyEval_b : std_logic_vector (0 downto 0);
signal highBBits_uid213_sinPiZPolyEval_in : std_logic_vector (14 downto 0);
signal highBBits_uid213_sinPiZPolyEval_b : std_logic_vector (13 downto 0);
signal lowRangeB_uid218_sinPiZPolyEval_in : std_logic_vector (1 downto 0);
signal lowRangeB_uid218_sinPiZPolyEval_b : std_logic_vector (1 downto 0);
signal highBBits_uid219_sinPiZPolyEval_in : std_logic_vector (23 downto 0);
signal highBBits_uid219_sinPiZPolyEval_b : std_logic_vector (21 downto 0);
signal oFracXExt_uid39_fpCosPiTest_q : std_logic_vector (36 downto 0);
signal exc_N_uid30_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal exc_N_uid30_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal exc_N_uid30_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal leftShiftStageSel5Dto4_uid112_fxpX_uid41_fpCosPiTest_in : std_logic_vector (5 downto 0);
signal leftShiftStageSel5Dto4_uid112_fxpX_uid41_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel3Dto2_uid123_fxpX_uid41_fpCosPiTest_in : std_logic_vector (3 downto 0);
signal leftShiftStageSel3Dto2_uid123_fxpX_uid41_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid134_fxpX_uid41_fpCosPiTest_in : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid134_fxpX_uid41_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal zAddr_uid62_fpCosPiTest_in : std_logic_vector (34 downto 0);
signal zAddr_uid62_fpCosPiTest_b : std_logic_vector (6 downto 0);
signal zPPolyEval_uid63_fpCosPiTest_in : std_logic_vector (27 downto 0);
signal zPPolyEval_uid63_fpCosPiTest_b : std_logic_vector (15 downto 0);
signal rVStage_uid138_lzcZ_uid56_fpCosPiTest_in : std_logic_vector (34 downto 0);
signal rVStage_uid138_lzcZ_uid56_fpCosPiTest_b : std_logic_vector (31 downto 0);
signal vStage_uid141_lzcZ_uid56_fpCosPiTest_in : std_logic_vector (2 downto 0);
signal vStage_uid141_lzcZ_uid56_fpCosPiTest_b : std_logic_vector (2 downto 0);
signal X18dto0_uid176_alignedZ_uid57_fpCosPiTest_in : std_logic_vector (18 downto 0);
signal X18dto0_uid176_alignedZ_uid57_fpCosPiTest_b : std_logic_vector (18 downto 0);
signal leftShiftStage2Idx1_uid127_fxpX_uid41_fpCosPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage2Idx2_uid130_fxpX_uid41_fpCosPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage2Idx3_uid133_fxpX_uid41_fpCosPiTest_q : std_logic_vector (36 downto 0);
signal vCount_uid153_lzcZ_uid56_fpCosPiTest_a : std_logic_vector(7 downto 0);
signal vCount_uid153_lzcZ_uid56_fpCosPiTest_b : std_logic_vector(7 downto 0);
signal vCount_uid153_lzcZ_uid56_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid156_lzcZ_uid56_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid156_lzcZ_uid56_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal vCount_uid165_lzcZ_uid56_fpCosPiTest_a : std_logic_vector(1 downto 0);
signal vCount_uid165_lzcZ_uid56_fpCosPiTest_b : std_logic_vector(1 downto 0);
signal vCount_uid165_lzcZ_uid56_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid168_lzcZ_uid56_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid168_lzcZ_uid56_fpCosPiTest_q : std_logic_vector (1 downto 0);
signal leftShiftStage2Idx1_uid197_alignedZ_uid57_fpCosPiTest_q : std_logic_vector (34 downto 0);
signal leftShiftStage2Idx2_uid200_alignedZ_uid57_fpCosPiTest_q : std_logic_vector (34 downto 0);
signal leftShiftStage2Idx3_uid203_alignedZ_uid57_fpCosPiTest_q : std_logic_vector (34 downto 0);
signal fracRCompPreRnd_uid70_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal fracRCompPreRnd_uid70_fpCosPiTest_q : std_logic_vector (23 downto 0);
signal rndExpUpdate_uid72_uid73_fpCosPiTest_q : std_logic_vector (24 downto 0);
signal sumAHighB_uid214_sinPiZPolyEval_a : std_logic_vector(21 downto 0);
signal sumAHighB_uid214_sinPiZPolyEval_b : std_logic_vector(21 downto 0);
signal sumAHighB_uid214_sinPiZPolyEval_o : std_logic_vector (21 downto 0);
signal sumAHighB_uid214_sinPiZPolyEval_q : std_logic_vector (21 downto 0);
signal sumAHighB_uid220_sinPiZPolyEval_a : std_logic_vector(29 downto 0);
signal sumAHighB_uid220_sinPiZPolyEval_b : std_logic_vector(29 downto 0);
signal sumAHighB_uid220_sinPiZPolyEval_o : std_logic_vector (29 downto 0);
signal sumAHighB_uid220_sinPiZPolyEval_q : std_logic_vector (29 downto 0);
signal X20dto0_uid106_fxpX_uid41_fpCosPiTest_in : std_logic_vector (20 downto 0);
signal X20dto0_uid106_fxpX_uid41_fpCosPiTest_b : std_logic_vector (20 downto 0);
signal X4dto0_uid109_fxpX_uid41_fpCosPiTest_in : std_logic_vector (4 downto 0);
signal X4dto0_uid109_fxpX_uid41_fpCosPiTest_b : std_logic_vector (4 downto 0);
signal InvExc_N_uid31_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal InvExc_N_uid31_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal excRNaN_uid84_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal excRNaN_uid84_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal excRNaN_uid84_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal yT1_uid210_sinPiZPolyEval_in : std_logic_vector (15 downto 0);
signal yT1_uid210_sinPiZPolyEval_b : std_logic_vector (13 downto 0);
signal cStage_uid142_lzcZ_uid56_fpCosPiTest_q : std_logic_vector (31 downto 0);
signal leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest_q : std_logic_vector (36 downto 0);
signal rVStage_uid158_lzcZ_uid56_fpCosPiTest_in : std_logic_vector (7 downto 0);
signal rVStage_uid158_lzcZ_uid56_fpCosPiTest_b : std_logic_vector (3 downto 0);
signal vStage_uid160_lzcZ_uid56_fpCosPiTest_in : std_logic_vector (3 downto 0);
signal vStage_uid160_lzcZ_uid56_fpCosPiTest_b : std_logic_vector (3 downto 0);
signal rVStage_uid170_lzcZ_uid56_fpCosPiTest_in : std_logic_vector (1 downto 0);
signal rVStage_uid170_lzcZ_uid56_fpCosPiTest_b : std_logic_vector (0 downto 0);
signal leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest_q : std_logic_vector (34 downto 0);
signal expFracPreRnd_uid71_uid71_fpCosPiTest_q : std_logic_vector (31 downto 0);
signal expFracComp_uid74_fpCosPiTest_a : std_logic_vector(32 downto 0);
signal expFracComp_uid74_fpCosPiTest_b : std_logic_vector(32 downto 0);
signal expFracComp_uid74_fpCosPiTest_o : std_logic_vector (32 downto 0);
signal expFracComp_uid74_fpCosPiTest_q : std_logic_vector (32 downto 0);
signal s1_uid212_uid215_sinPiZPolyEval_q : std_logic_vector (22 downto 0);
signal s2_uid218_uid221_sinPiZPolyEval_q : std_logic_vector (31 downto 0);
signal leftShiftStage0Idx1_uid107_fxpX_uid41_fpCosPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage0Idx2_uid110_fxpX_uid41_fpCosPiTest_q : std_logic_vector (36 downto 0);
signal exc_R_uid34_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal exc_R_uid34_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal exc_R_uid34_fpCosPiTest_c : std_logic_vector(0 downto 0);
signal exc_R_uid34_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal rInfOrNaN_uid92_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal rInfOrNaN_uid92_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal rInfOrNaN_uid92_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal FxpX36_uid42_fpCosPiTest_in : std_logic_vector (36 downto 0);
signal FxpX36_uid42_fpCosPiTest_b : std_logic_vector (0 downto 0);
signal fxpXFrac_uid43_fpCosPiTest_in : std_logic_vector (35 downto 0);
signal fxpXFrac_uid43_fpCosPiTest_b : std_logic_vector (35 downto 0);
signal vCount_uid171_lzcZ_uid56_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal vCount_uid171_lzcZ_uid56_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal vCount_uid171_lzcZ_uid56_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal alignedZLow_uid58_fpCosPiTest_in : std_logic_vector (34 downto 0);
signal alignedZLow_uid58_fpCosPiTest_b : std_logic_vector (23 downto 0);
signal fracRComp_uid75_fpCosPiTest_in : std_logic_vector (23 downto 0);
signal fracRComp_uid75_fpCosPiTest_b : std_logic_vector (22 downto 0);
signal expRComp_uid76_fpCosPiTest_in : std_logic_vector (31 downto 0);
signal expRComp_uid76_fpCosPiTest_b : std_logic_vector (7 downto 0);
signal fxpSinRes_uid65_fpCosPiTest_in : std_logic_vector (29 downto 0);
signal fxpSinRes_uid65_fpCosPiTest_b : std_logic_vector (24 downto 0);
signal leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_q : std_logic_vector (36 downto 0);
signal FxpXFrac35_uid44_fpCosPiTest_in : std_logic_vector (35 downto 0);
signal FxpXFrac35_uid44_fpCosPiTest_b : std_logic_vector (0 downto 0);
signal r_uid172_lzcZ_uid56_fpCosPiTest_q : std_logic_vector (5 downto 0);
signal LeftShiftStage032dto0_uid115_fxpX_uid41_fpCosPiTest_in : std_logic_vector (32 downto 0);
signal LeftShiftStage032dto0_uid115_fxpX_uid41_fpCosPiTest_b : std_logic_vector (32 downto 0);
signal LeftShiftStage028dto0_uid118_fxpX_uid41_fpCosPiTest_in : std_logic_vector (28 downto 0);
signal LeftShiftStage028dto0_uid118_fxpX_uid41_fpCosPiTest_b : std_logic_vector (28 downto 0);
signal LeftShiftStage024dto0_uid121_fxpX_uid41_fpCosPiTest_in : std_logic_vector (24 downto 0);
signal LeftShiftStage024dto0_uid121_fxpX_uid41_fpCosPiTest_b : std_logic_vector (24 downto 0);
signal xParityXorHalfParity_uid96_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal xParityXorHalfParity_uid96_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal xParityXorHalfParity_uid96_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal leftShiftStageSel5Dto4_uid182_alignedZ_uid57_fpCosPiTest_in : std_logic_vector (5 downto 0);
signal leftShiftStageSel5Dto4_uid182_alignedZ_uid57_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel3Dto2_uid193_alignedZ_uid57_fpCosPiTest_in : std_logic_vector (3 downto 0);
signal leftShiftStageSel3Dto2_uid193_alignedZ_uid57_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid204_alignedZ_uid57_fpCosPiTest_in : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid204_alignedZ_uid57_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStage1Idx1_uid116_fxpX_uid41_fpCosPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage1Idx2_uid119_fxpX_uid41_fpCosPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage1Idx3_uid122_fxpX_uid41_fpCosPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_q : std_logic_vector (34 downto 0);
signal LeftShiftStage030dto0_uid185_alignedZ_uid57_fpCosPiTest_in : std_logic_vector (30 downto 0);
signal LeftShiftStage030dto0_uid185_alignedZ_uid57_fpCosPiTest_b : std_logic_vector (30 downto 0);
signal LeftShiftStage026dto0_uid188_alignedZ_uid57_fpCosPiTest_in : std_logic_vector (26 downto 0);
signal LeftShiftStage026dto0_uid188_alignedZ_uid57_fpCosPiTest_b : std_logic_vector (26 downto 0);
signal LeftShiftStage022dto0_uid191_alignedZ_uid57_fpCosPiTest_in : std_logic_vector (22 downto 0);
signal LeftShiftStage022dto0_uid191_alignedZ_uid57_fpCosPiTest_b : std_logic_vector (22 downto 0);
signal leftShiftStage1Idx1_uid186_alignedZ_uid57_fpCosPiTest_q : std_logic_vector (34 downto 0);
signal leftShiftStage1Idx2_uid189_alignedZ_uid57_fpCosPiTest_q : std_logic_vector (34 downto 0);
signal leftShiftStage1Idx3_uid192_alignedZ_uid57_fpCosPiTest_q : std_logic_vector (34 downto 0);
begin
--xIn(GPIN,3)@0
--LeftShiftStage133dto0_uid132_fxpX_uid41_fpCosPiTest(BITSELECT,131)@1
LeftShiftStage133dto0_uid132_fxpX_uid41_fpCosPiTest_in <= leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_q(33 downto 0);
LeftShiftStage133dto0_uid132_fxpX_uid41_fpCosPiTest_b <= LeftShiftStage133dto0_uid132_fxpX_uid41_fpCosPiTest_in(33 downto 0);
--leftShiftStage2Idx3Pad3_uid131_fxpX_uid41_fpCosPiTest(CONSTANT,130)
leftShiftStage2Idx3Pad3_uid131_fxpX_uid41_fpCosPiTest_q <= "000";
--leftShiftStage2Idx3_uid133_fxpX_uid41_fpCosPiTest(BITJOIN,132)@1
leftShiftStage2Idx3_uid133_fxpX_uid41_fpCosPiTest_q <= LeftShiftStage133dto0_uid132_fxpX_uid41_fpCosPiTest_b & leftShiftStage2Idx3Pad3_uid131_fxpX_uid41_fpCosPiTest_q;
--LeftShiftStage134dto0_uid129_fxpX_uid41_fpCosPiTest(BITSELECT,128)@1
LeftShiftStage134dto0_uid129_fxpX_uid41_fpCosPiTest_in <= leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_q(34 downto 0);
LeftShiftStage134dto0_uid129_fxpX_uid41_fpCosPiTest_b <= LeftShiftStage134dto0_uid129_fxpX_uid41_fpCosPiTest_in(34 downto 0);
--leftShiftStage2Idx2Pad2_uid128_fxpX_uid41_fpCosPiTest(CONSTANT,127)
leftShiftStage2Idx2Pad2_uid128_fxpX_uid41_fpCosPiTest_q <= "00";
--leftShiftStage2Idx2_uid130_fxpX_uid41_fpCosPiTest(BITJOIN,129)@1
leftShiftStage2Idx2_uid130_fxpX_uid41_fpCosPiTest_q <= LeftShiftStage134dto0_uid129_fxpX_uid41_fpCosPiTest_b & leftShiftStage2Idx2Pad2_uid128_fxpX_uid41_fpCosPiTest_q;
--LeftShiftStage135dto0_uid126_fxpX_uid41_fpCosPiTest(BITSELECT,125)@1
LeftShiftStage135dto0_uid126_fxpX_uid41_fpCosPiTest_in <= leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_q(35 downto 0);
LeftShiftStage135dto0_uid126_fxpX_uid41_fpCosPiTest_b <= LeftShiftStage135dto0_uid126_fxpX_uid41_fpCosPiTest_in(35 downto 0);
--GND(CONSTANT,0)
GND_q <= "0";
--leftShiftStage2Idx1_uid127_fxpX_uid41_fpCosPiTest(BITJOIN,126)@1
leftShiftStage2Idx1_uid127_fxpX_uid41_fpCosPiTest_q <= LeftShiftStage135dto0_uid126_fxpX_uid41_fpCosPiTest_b & GND_q;
--leftShiftStage0Idx3_uid111_fxpX_uid41_fpCosPiTest(CONSTANT,110)
leftShiftStage0Idx3_uid111_fxpX_uid41_fpCosPiTest_q <= "0000000000000000000000000000000000000";
--X4dto0_uid109_fxpX_uid41_fpCosPiTest(BITSELECT,108)@0
X4dto0_uid109_fxpX_uid41_fpCosPiTest_in <= oFracXExt_uid39_fpCosPiTest_q(4 downto 0);
X4dto0_uid109_fxpX_uid41_fpCosPiTest_b <= X4dto0_uid109_fxpX_uid41_fpCosPiTest_in(4 downto 0);
--leftShiftStage0Idx2Pad32_uid108_fxpX_uid41_fpCosPiTest(CONSTANT,107)
leftShiftStage0Idx2Pad32_uid108_fxpX_uid41_fpCosPiTest_q <= "00000000000000000000000000000000";
--leftShiftStage0Idx2_uid110_fxpX_uid41_fpCosPiTest(BITJOIN,109)@0
leftShiftStage0Idx2_uid110_fxpX_uid41_fpCosPiTest_q <= X4dto0_uid109_fxpX_uid41_fpCosPiTest_b & leftShiftStage0Idx2Pad32_uid108_fxpX_uid41_fpCosPiTest_q;
--X20dto0_uid106_fxpX_uid41_fpCosPiTest(BITSELECT,105)@0
X20dto0_uid106_fxpX_uid41_fpCosPiTest_in <= oFracXExt_uid39_fpCosPiTest_q(20 downto 0);
X20dto0_uid106_fxpX_uid41_fpCosPiTest_b <= X20dto0_uid106_fxpX_uid41_fpCosPiTest_in(20 downto 0);
--leftShiftStage0Idx1Pad16_uid105_fxpX_uid41_fpCosPiTest(CONSTANT,104)
leftShiftStage0Idx1Pad16_uid105_fxpX_uid41_fpCosPiTest_q <= "0000000000000000";
--leftShiftStage0Idx1_uid107_fxpX_uid41_fpCosPiTest(BITJOIN,106)@0
leftShiftStage0Idx1_uid107_fxpX_uid41_fpCosPiTest_q <= X20dto0_uid106_fxpX_uid41_fpCosPiTest_b & leftShiftStage0Idx1Pad16_uid105_fxpX_uid41_fpCosPiTest_q;
--cst01pWShift_uid14_fpCosPiTest(CONSTANT,13)
cst01pWShift_uid14_fpCosPiTest_q <= "0000000000000";
--VCC(CONSTANT,1)
VCC_q <= "1";
--fracX_uid7_fpCosPiTest(BITSELECT,6)@0
fracX_uid7_fpCosPiTest_in <= a(22 downto 0);
fracX_uid7_fpCosPiTest_b <= fracX_uid7_fpCosPiTest_in(22 downto 0);
--oFracX_uid37_uid37_fpCosPiTest(BITJOIN,36)@0
oFracX_uid37_uid37_fpCosPiTest_q <= VCC_q & fracX_uid7_fpCosPiTest_b;
--oFracXExt_uid39_fpCosPiTest(BITJOIN,38)@0
oFracXExt_uid39_fpCosPiTest_q <= cst01pWShift_uid14_fpCosPiTest_q & oFracX_uid37_uid37_fpCosPiTest_q;
--biasMwShiftMO_uid13_fpCosPiTest(CONSTANT,12)
biasMwShiftMO_uid13_fpCosPiTest_q <= "01110010";
--expX_uid6_fpCosPiTest(BITSELECT,5)@0
expX_uid6_fpCosPiTest_in <= a(30 downto 0);
expX_uid6_fpCosPiTest_b <= expX_uid6_fpCosPiTest_in(30 downto 23);
--shiftValFxPX_uid38_fpCosPiTest(SUB,37)@0
shiftValFxPX_uid38_fpCosPiTest_a <= STD_LOGIC_VECTOR("0" & expX_uid6_fpCosPiTest_b);
shiftValFxPX_uid38_fpCosPiTest_b <= STD_LOGIC_VECTOR("0" & biasMwShiftMO_uid13_fpCosPiTest_q);
shiftValFxPX_uid38_fpCosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(shiftValFxPX_uid38_fpCosPiTest_a) - UNSIGNED(shiftValFxPX_uid38_fpCosPiTest_b));
shiftValFxPX_uid38_fpCosPiTest_q <= shiftValFxPX_uid38_fpCosPiTest_o(8 downto 0);
--fxpShifterBits_uid40_fpCosPiTest(BITSELECT,39)@0
fxpShifterBits_uid40_fpCosPiTest_in <= shiftValFxPX_uid38_fpCosPiTest_q(5 downto 0);
fxpShifterBits_uid40_fpCosPiTest_b <= fxpShifterBits_uid40_fpCosPiTest_in(5 downto 0);
--leftShiftStageSel5Dto4_uid112_fxpX_uid41_fpCosPiTest(BITSELECT,111)@0
leftShiftStageSel5Dto4_uid112_fxpX_uid41_fpCosPiTest_in <= fxpShifterBits_uid40_fpCosPiTest_b;
leftShiftStageSel5Dto4_uid112_fxpX_uid41_fpCosPiTest_b <= leftShiftStageSel5Dto4_uid112_fxpX_uid41_fpCosPiTest_in(5 downto 4);
--leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest(MUX,112)@0
leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_s <= leftShiftStageSel5Dto4_uid112_fxpX_uid41_fpCosPiTest_b;
leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest: PROCESS (leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_s, en, oFracXExt_uid39_fpCosPiTest_q, leftShiftStage0Idx1_uid107_fxpX_uid41_fpCosPiTest_q, leftShiftStage0Idx2_uid110_fxpX_uid41_fpCosPiTest_q, leftShiftStage0Idx3_uid111_fxpX_uid41_fpCosPiTest_q)
BEGIN
CASE leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_s IS
WHEN "00" => leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_q <= oFracXExt_uid39_fpCosPiTest_q;
WHEN "01" => leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_q <= leftShiftStage0Idx1_uid107_fxpX_uid41_fpCosPiTest_q;
WHEN "10" => leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_q <= leftShiftStage0Idx2_uid110_fxpX_uid41_fpCosPiTest_q;
WHEN "11" => leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_q <= leftShiftStage0Idx3_uid111_fxpX_uid41_fpCosPiTest_q;
WHEN OTHERS => leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage024dto0_uid121_fxpX_uid41_fpCosPiTest(BITSELECT,120)@0
LeftShiftStage024dto0_uid121_fxpX_uid41_fpCosPiTest_in <= leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_q(24 downto 0);
LeftShiftStage024dto0_uid121_fxpX_uid41_fpCosPiTest_b <= LeftShiftStage024dto0_uid121_fxpX_uid41_fpCosPiTest_in(24 downto 0);
--leftShiftStage1Idx3Pad12_uid120_fxpX_uid41_fpCosPiTest(CONSTANT,119)
leftShiftStage1Idx3Pad12_uid120_fxpX_uid41_fpCosPiTest_q <= "000000000000";
--leftShiftStage1Idx3_uid122_fxpX_uid41_fpCosPiTest(BITJOIN,121)@0
leftShiftStage1Idx3_uid122_fxpX_uid41_fpCosPiTest_q <= LeftShiftStage024dto0_uid121_fxpX_uid41_fpCosPiTest_b & leftShiftStage1Idx3Pad12_uid120_fxpX_uid41_fpCosPiTest_q;
--reg_leftShiftStage1Idx3_uid122_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_5(REG,235)@0
reg_leftShiftStage1Idx3_uid122_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx3_uid122_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_5_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx3_uid122_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_5_q <= leftShiftStage1Idx3_uid122_fxpX_uid41_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage028dto0_uid118_fxpX_uid41_fpCosPiTest(BITSELECT,117)@0
LeftShiftStage028dto0_uid118_fxpX_uid41_fpCosPiTest_in <= leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_q(28 downto 0);
LeftShiftStage028dto0_uid118_fxpX_uid41_fpCosPiTest_b <= LeftShiftStage028dto0_uid118_fxpX_uid41_fpCosPiTest_in(28 downto 0);
--cstAllZWE_uid21_fpCosPiTest(CONSTANT,20)
cstAllZWE_uid21_fpCosPiTest_q <= "00000000";
--leftShiftStage1Idx2_uid119_fxpX_uid41_fpCosPiTest(BITJOIN,118)@0
leftShiftStage1Idx2_uid119_fxpX_uid41_fpCosPiTest_q <= LeftShiftStage028dto0_uid118_fxpX_uid41_fpCosPiTest_b & cstAllZWE_uid21_fpCosPiTest_q;
--reg_leftShiftStage1Idx2_uid119_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_4(REG,234)@0
reg_leftShiftStage1Idx2_uid119_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx2_uid119_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_4_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx2_uid119_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_4_q <= leftShiftStage1Idx2_uid119_fxpX_uid41_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage032dto0_uid115_fxpX_uid41_fpCosPiTest(BITSELECT,114)@0
LeftShiftStage032dto0_uid115_fxpX_uid41_fpCosPiTest_in <= leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_q(32 downto 0);
LeftShiftStage032dto0_uid115_fxpX_uid41_fpCosPiTest_b <= LeftShiftStage032dto0_uid115_fxpX_uid41_fpCosPiTest_in(32 downto 0);
--leftShiftStage1Idx1Pad4_uid114_fxpX_uid41_fpCosPiTest(CONSTANT,113)
leftShiftStage1Idx1Pad4_uid114_fxpX_uid41_fpCosPiTest_q <= "0000";
--leftShiftStage1Idx1_uid116_fxpX_uid41_fpCosPiTest(BITJOIN,115)@0
leftShiftStage1Idx1_uid116_fxpX_uid41_fpCosPiTest_q <= LeftShiftStage032dto0_uid115_fxpX_uid41_fpCosPiTest_b & leftShiftStage1Idx1Pad4_uid114_fxpX_uid41_fpCosPiTest_q;
--reg_leftShiftStage1Idx1_uid116_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_3(REG,233)@0
reg_leftShiftStage1Idx1_uid116_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx1_uid116_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_3_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx1_uid116_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_3_q <= leftShiftStage1Idx1_uid116_fxpX_uid41_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--reg_leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_2(REG,232)@0
reg_leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_2_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_2_q <= leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel3Dto2_uid123_fxpX_uid41_fpCosPiTest(BITSELECT,122)@0
leftShiftStageSel3Dto2_uid123_fxpX_uid41_fpCosPiTest_in <= fxpShifterBits_uid40_fpCosPiTest_b(3 downto 0);
leftShiftStageSel3Dto2_uid123_fxpX_uid41_fpCosPiTest_b <= leftShiftStageSel3Dto2_uid123_fxpX_uid41_fpCosPiTest_in(3 downto 2);
--reg_leftShiftStageSel3Dto2_uid123_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_1(REG,231)@0
reg_leftShiftStageSel3Dto2_uid123_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel3Dto2_uid123_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel3Dto2_uid123_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_1_q <= leftShiftStageSel3Dto2_uid123_fxpX_uid41_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest(MUX,123)@1
leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_s <= reg_leftShiftStageSel3Dto2_uid123_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_1_q;
leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest: PROCESS (leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_s, en, reg_leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_2_q, reg_leftShiftStage1Idx1_uid116_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_3_q, reg_leftShiftStage1Idx2_uid119_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_4_q, reg_leftShiftStage1Idx3_uid122_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_5_q)
BEGIN
CASE leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_s IS
WHEN "00" => leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_q <= reg_leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_2_q;
WHEN "01" => leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_q <= reg_leftShiftStage1Idx1_uid116_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_3_q;
WHEN "10" => leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_q <= reg_leftShiftStage1Idx2_uid119_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_4_q;
WHEN "11" => leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_q <= reg_leftShiftStage1Idx3_uid122_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_5_q;
WHEN OTHERS => leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--leftShiftStageSel1Dto0_uid134_fxpX_uid41_fpCosPiTest(BITSELECT,133)@0
leftShiftStageSel1Dto0_uid134_fxpX_uid41_fpCosPiTest_in <= fxpShifterBits_uid40_fpCosPiTest_b(1 downto 0);
leftShiftStageSel1Dto0_uid134_fxpX_uid41_fpCosPiTest_b <= leftShiftStageSel1Dto0_uid134_fxpX_uid41_fpCosPiTest_in(1 downto 0);
--reg_leftShiftStageSel1Dto0_uid134_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest_1(REG,236)@0
reg_leftShiftStageSel1Dto0_uid134_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel1Dto0_uid134_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel1Dto0_uid134_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest_1_q <= leftShiftStageSel1Dto0_uid134_fxpX_uid41_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest(MUX,134)@1
leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest_s <= reg_leftShiftStageSel1Dto0_uid134_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest_1_q;
leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest: PROCESS (leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest_s, en, leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_q, leftShiftStage2Idx1_uid127_fxpX_uid41_fpCosPiTest_q, leftShiftStage2Idx2_uid130_fxpX_uid41_fpCosPiTest_q, leftShiftStage2Idx3_uid133_fxpX_uid41_fpCosPiTest_q)
BEGIN
CASE leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest_s IS
WHEN "00" => leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest_q <= leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_q;
WHEN "01" => leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest_q <= leftShiftStage2Idx1_uid127_fxpX_uid41_fpCosPiTest_q;
WHEN "10" => leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest_q <= leftShiftStage2Idx2_uid130_fxpX_uid41_fpCosPiTest_q;
WHEN "11" => leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest_q <= leftShiftStage2Idx3_uid133_fxpX_uid41_fpCosPiTest_q;
WHEN OTHERS => leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--fxpXFrac_uid43_fpCosPiTest(BITSELECT,42)@1
fxpXFrac_uid43_fpCosPiTest_in <= leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest_q(35 downto 0);
fxpXFrac_uid43_fpCosPiTest_b <= fxpXFrac_uid43_fpCosPiTest_in(35 downto 0);
--FxpXFrac35_uid44_fpCosPiTest(BITSELECT,43)@1
FxpXFrac35_uid44_fpCosPiTest_in <= fxpXFrac_uid43_fpCosPiTest_b;
FxpXFrac35_uid44_fpCosPiTest_b <= FxpXFrac35_uid44_fpCosPiTest_in(35 downto 35);
--FxpX36_uid42_fpCosPiTest(BITSELECT,41)@1
FxpX36_uid42_fpCosPiTest_in <= leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest_q;
FxpX36_uid42_fpCosPiTest_b <= FxpX36_uid42_fpCosPiTest_in(36 downto 36);
--xParityXorHalfParity_uid96_fpCosPiTest(LOGICAL,95)@1
xParityXorHalfParity_uid96_fpCosPiTest_a <= FxpX36_uid42_fpCosPiTest_b;
xParityXorHalfParity_uid96_fpCosPiTest_b <= FxpXFrac35_uid44_fpCosPiTest_b;
xParityXorHalfParity_uid96_fpCosPiTest_q <= xParityXorHalfParity_uid96_fpCosPiTest_a xor xParityXorHalfParity_uid96_fpCosPiTest_b;
--ld_xParityXorHalfParity_uid96_fpCosPiTest_q_to_signRComp_uid99_fpCosPiTest_c(DELAY,369)@1
ld_xParityXorHalfParity_uid96_fpCosPiTest_q_to_signRComp_uid99_fpCosPiTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => xParityXorHalfParity_uid96_fpCosPiTest_q, xout => ld_xParityXorHalfParity_uid96_fpCosPiTest_q_to_signRComp_uid99_fpCosPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--cstBiasPwF_uid12_fpCosPiTest(CONSTANT,11)
cstBiasPwF_uid12_fpCosPiTest_q <= "10010110";
--xEvenInt_uid35_fpCosPiTest(COMPARE,34)@0
xEvenInt_uid35_fpCosPiTest_cin <= GND_q;
xEvenInt_uid35_fpCosPiTest_a <= STD_LOGIC_VECTOR("00" & cstBiasPwF_uid12_fpCosPiTest_q) & '0';
xEvenInt_uid35_fpCosPiTest_b <= STD_LOGIC_VECTOR("00" & expX_uid6_fpCosPiTest_b) & xEvenInt_uid35_fpCosPiTest_cin(0);
xEvenInt_uid35_fpCosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(xEvenInt_uid35_fpCosPiTest_a) - UNSIGNED(xEvenInt_uid35_fpCosPiTest_b));
xEvenInt_uid35_fpCosPiTest_c(0) <= xEvenInt_uid35_fpCosPiTest_o(10);
--ld_xEvenInt_uid35_fpCosPiTest_c_to_evenIntCosNotOneFZ_uid79_fpCosPiTest_a(DELAY,335)@0
ld_xEvenInt_uid35_fpCosPiTest_c_to_evenIntCosNotOneFZ_uid79_fpCosPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => xEvenInt_uid35_fpCosPiTest_c, xout => ld_xEvenInt_uid35_fpCosPiTest_c_to_evenIntCosNotOneFZ_uid79_fpCosPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--InvXEvenInt_uid81_fpCosPiTest(LOGICAL,80)@2
InvXEvenInt_uid81_fpCosPiTest_a <= ld_xEvenInt_uid35_fpCosPiTest_c_to_evenIntCosNotOneFZ_uid79_fpCosPiTest_a_q;
InvXEvenInt_uid81_fpCosPiTest_q <= not InvXEvenInt_uid81_fpCosPiTest_a;
--cosXIsOne_uid36_fpCosPiTest(COMPARE,35)@0
cosXIsOne_uid36_fpCosPiTest_cin <= GND_q;
cosXIsOne_uid36_fpCosPiTest_a <= STD_LOGIC_VECTOR("00" & expX_uid6_fpCosPiTest_b) & '0';
cosXIsOne_uid36_fpCosPiTest_b <= STD_LOGIC_VECTOR("00" & biasMwShiftMO_uid13_fpCosPiTest_q) & cosXIsOne_uid36_fpCosPiTest_cin(0);
cosXIsOne_uid36_fpCosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(cosXIsOne_uid36_fpCosPiTest_a) - UNSIGNED(cosXIsOne_uid36_fpCosPiTest_b));
cosXIsOne_uid36_fpCosPiTest_c(0) <= cosXIsOne_uid36_fpCosPiTest_o(10);
--ld_cosXIsOne_uid36_fpCosPiTest_c_to_InvCosXIsOne_uid77_fpCosPiTest_a(DELAY,332)@0
ld_cosXIsOne_uid36_fpCosPiTest_c_to_InvCosXIsOne_uid77_fpCosPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => cosXIsOne_uid36_fpCosPiTest_c, xout => ld_cosXIsOne_uid36_fpCosPiTest_c_to_InvCosXIsOne_uid77_fpCosPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--InvCosXIsOne_uid77_fpCosPiTest(LOGICAL,76)@2
InvCosXIsOne_uid77_fpCosPiTest_a <= ld_cosXIsOne_uid36_fpCosPiTest_c_to_InvCosXIsOne_uid77_fpCosPiTest_a_q;
InvCosXIsOne_uid77_fpCosPiTest_q <= not InvCosXIsOne_uid77_fpCosPiTest_a;
--signRComp_uid99_fpCosPiTest(LOGICAL,98)@2
signRComp_uid99_fpCosPiTest_a <= InvCosXIsOne_uid77_fpCosPiTest_q;
signRComp_uid99_fpCosPiTest_b <= InvXEvenInt_uid81_fpCosPiTest_q;
signRComp_uid99_fpCosPiTest_c <= ld_xParityXorHalfParity_uid96_fpCosPiTest_q_to_signRComp_uid99_fpCosPiTest_c_q;
signRComp_uid99_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
signRComp_uid99_fpCosPiTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1' AND en = "1") THEN
signRComp_uid99_fpCosPiTest_q <= signRComp_uid99_fpCosPiTest_a and signRComp_uid99_fpCosPiTest_b and signRComp_uid99_fpCosPiTest_c;
END IF;
END PROCESS;
--cstZwSwF_uid15_fpCosPiTest(CONSTANT,14)
cstZwSwF_uid15_fpCosPiTest_q <= "00000000000000000000000000000000000";
--cstHalfwSwFP1_uid18_fpCosPiTest(BITJOIN,17)@2
cstHalfwSwFP1_uid18_fpCosPiTest_q <= VCC_q & cstZwSwF_uid15_fpCosPiTest_q;
--reg_fxpXFrac_uid43_fpCosPiTest_0_to_fxpXFracZero_uid45_fpCosPiTest_1(REG,237)@1
reg_fxpXFrac_uid43_fpCosPiTest_0_to_fxpXFracZero_uid45_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fxpXFrac_uid43_fpCosPiTest_0_to_fxpXFracZero_uid45_fpCosPiTest_1_q <= "000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fxpXFrac_uid43_fpCosPiTest_0_to_fxpXFracZero_uid45_fpCosPiTest_1_q <= fxpXFrac_uid43_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--fxpXFracHalf_uid46_fpCosPiTest(LOGICAL,45)@2
fxpXFracHalf_uid46_fpCosPiTest_a <= reg_fxpXFrac_uid43_fpCosPiTest_0_to_fxpXFracZero_uid45_fpCosPiTest_1_q;
fxpXFracHalf_uid46_fpCosPiTest_b <= cstHalfwSwFP1_uid18_fpCosPiTest_q;
fxpXFracHalf_uid46_fpCosPiTest_q <= "1" when fxpXFracHalf_uid46_fpCosPiTest_a = fxpXFracHalf_uid46_fpCosPiTest_b else "0";
--ld_fxpXFracHalf_uid46_fpCosPiTest_q_to_InvFxpXFracHalf_uid100_fpCosPiTest_a(DELAY,370)@2
ld_fxpXFracHalf_uid46_fpCosPiTest_q_to_InvFxpXFracHalf_uid100_fpCosPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => fxpXFracHalf_uid46_fpCosPiTest_q, xout => ld_fxpXFracHalf_uid46_fpCosPiTest_q_to_InvFxpXFracHalf_uid100_fpCosPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--InvFxpXFracHalf_uid100_fpCosPiTest(LOGICAL,99)@3
InvFxpXFracHalf_uid100_fpCosPiTest_a <= ld_fxpXFracHalf_uid46_fpCosPiTest_q_to_InvFxpXFracHalf_uid100_fpCosPiTest_a_q;
InvFxpXFracHalf_uid100_fpCosPiTest_q <= not InvFxpXFracHalf_uid100_fpCosPiTest_a;
--signR_uid101_fpCosPiTest(LOGICAL,100)@3
signR_uid101_fpCosPiTest_a <= InvFxpXFracHalf_uid100_fpCosPiTest_q;
signR_uid101_fpCosPiTest_b <= signRComp_uid99_fpCosPiTest_q;
signR_uid101_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
signR_uid101_fpCosPiTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1' AND en = "1") THEN
signR_uid101_fpCosPiTest_q <= signR_uid101_fpCosPiTest_a and signR_uid101_fpCosPiTest_b;
END IF;
END PROCESS;
--ld_signR_uid101_fpCosPiTest_q_to_R_uid102_fpCosPiTest_c(DELAY,375)@4
ld_signR_uid101_fpCosPiTest_q_to_R_uid102_fpCosPiTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 13 )
PORT MAP ( xin => signR_uid101_fpCosPiTest_q, xout => ld_signR_uid101_fpCosPiTest_q_to_R_uid102_fpCosPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--cstBias_uid10_fpCosPiTest(CONSTANT,9)
cstBias_uid10_fpCosPiTest_q <= "01111111";
--cstAllOWE_uid8_fpCosPiTest(CONSTANT,7)
cstAllOWE_uid8_fpCosPiTest_q <= "11111111";
--pad_o_uid16_uid47_fpCosPiTest(BITJOIN,46)@1
pad_o_uid16_uid47_fpCosPiTest_q <= VCC_q & STD_LOGIC_VECTOR((35 downto 1 => GND_q(0)) & GND_q);
--reg_pad_o_uid16_uid47_fpCosPiTest_0_to_oMFxpXFrac_uid47_fpCosPiTest_0(REG,244)@1
reg_pad_o_uid16_uid47_fpCosPiTest_0_to_oMFxpXFrac_uid47_fpCosPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_o_uid16_uid47_fpCosPiTest_0_to_oMFxpXFrac_uid47_fpCosPiTest_0_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_o_uid16_uid47_fpCosPiTest_0_to_oMFxpXFrac_uid47_fpCosPiTest_0_q <= pad_o_uid16_uid47_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--oMFxpXFrac_uid47_fpCosPiTest(SUB,47)@2
oMFxpXFrac_uid47_fpCosPiTest_a <= STD_LOGIC_VECTOR("0" & reg_pad_o_uid16_uid47_fpCosPiTest_0_to_oMFxpXFrac_uid47_fpCosPiTest_0_q);
oMFxpXFrac_uid47_fpCosPiTest_b <= STD_LOGIC_VECTOR("00" & reg_fxpXFrac_uid43_fpCosPiTest_0_to_fxpXFracZero_uid45_fpCosPiTest_1_q);
oMFxpXFrac_uid47_fpCosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(oMFxpXFrac_uid47_fpCosPiTest_a) - UNSIGNED(oMFxpXFrac_uid47_fpCosPiTest_b));
oMFxpXFrac_uid47_fpCosPiTest_q <= oMFxpXFrac_uid47_fpCosPiTest_o(37 downto 0);
--oMFxpXFrac_uid49_fpCosPiTest(BITSELECT,48)@2
oMFxpXFrac_uid49_fpCosPiTest_in <= oMFxpXFrac_uid47_fpCosPiTest_q(35 downto 0);
oMFxpXFrac_uid49_fpCosPiTest_b <= oMFxpXFrac_uid49_fpCosPiTest_in(35 downto 0);
--ld_fxpXFrac_uid43_fpCosPiTest_b_to_rangeReducedFxPX_uid51_fpCosPiTest_c(DELAY,308)@1
ld_fxpXFrac_uid43_fpCosPiTest_b_to_rangeReducedFxPX_uid51_fpCosPiTest_c : dspba_delay
GENERIC MAP ( width => 36, depth => 1 )
PORT MAP ( xin => fxpXFrac_uid43_fpCosPiTest_b, xout => ld_fxpXFrac_uid43_fpCosPiTest_b_to_rangeReducedFxPX_uid51_fpCosPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--ld_FxpXFrac35_uid44_fpCosPiTest_b_to_rangeReducedFxPX_uid51_fpCosPiTest_b(DELAY,307)@1
ld_FxpXFrac35_uid44_fpCosPiTest_b_to_rangeReducedFxPX_uid51_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => FxpXFrac35_uid44_fpCosPiTest_b, xout => ld_FxpXFrac35_uid44_fpCosPiTest_b_to_rangeReducedFxPX_uid51_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--rangeReducedFxPX_uid51_fpCosPiTest(MUX,50)@2
rangeReducedFxPX_uid51_fpCosPiTest_s <= ld_FxpXFrac35_uid44_fpCosPiTest_b_to_rangeReducedFxPX_uid51_fpCosPiTest_b_q;
rangeReducedFxPX_uid51_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
rangeReducedFxPX_uid51_fpCosPiTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE rangeReducedFxPX_uid51_fpCosPiTest_s IS
WHEN "0" => rangeReducedFxPX_uid51_fpCosPiTest_q <= ld_fxpXFrac_uid43_fpCosPiTest_b_to_rangeReducedFxPX_uid51_fpCosPiTest_c_q;
WHEN "1" => rangeReducedFxPX_uid51_fpCosPiTest_q <= oMFxpXFrac_uid49_fpCosPiTest_b;
WHEN OTHERS => rangeReducedFxPX_uid51_fpCosPiTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--pad_half_uid17_uid52_fpCosPiTest(BITJOIN,51)@2
pad_half_uid17_uid52_fpCosPiTest_q <= VCC_q & STD_LOGIC_VECTOR((34 downto 1 => GND_q(0)) & GND_q);
--reg_pad_half_uid17_uid52_fpCosPiTest_0_to_z_halfMRRFxPXE_uid52_fpCosPiTest_0(REG,246)@2
reg_pad_half_uid17_uid52_fpCosPiTest_0_to_z_halfMRRFxPXE_uid52_fpCosPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_half_uid17_uid52_fpCosPiTest_0_to_z_halfMRRFxPXE_uid52_fpCosPiTest_0_q <= "000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_half_uid17_uid52_fpCosPiTest_0_to_z_halfMRRFxPXE_uid52_fpCosPiTest_0_q <= pad_half_uid17_uid52_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--z_halfMRRFxPXE_uid52_fpCosPiTest(SUB,52)@3
z_halfMRRFxPXE_uid52_fpCosPiTest_a <= STD_LOGIC_VECTOR("0" & reg_pad_half_uid17_uid52_fpCosPiTest_0_to_z_halfMRRFxPXE_uid52_fpCosPiTest_0_q);
z_halfMRRFxPXE_uid52_fpCosPiTest_b <= STD_LOGIC_VECTOR("0" & rangeReducedFxPX_uid51_fpCosPiTest_q);
z_halfMRRFxPXE_uid52_fpCosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(z_halfMRRFxPXE_uid52_fpCosPiTest_a) - UNSIGNED(z_halfMRRFxPXE_uid52_fpCosPiTest_b));
z_halfMRRFxPXE_uid52_fpCosPiTest_q <= z_halfMRRFxPXE_uid52_fpCosPiTest_o(36 downto 0);
--z_uid54_fpCosPiTest(BITSELECT,53)@3
z_uid54_fpCosPiTest_in <= z_halfMRRFxPXE_uid52_fpCosPiTest_q(34 downto 0);
z_uid54_fpCosPiTest_b <= z_uid54_fpCosPiTest_in(34 downto 0);
--zAddr_uid62_fpCosPiTest(BITSELECT,61)@3
zAddr_uid62_fpCosPiTest_in <= z_uid54_fpCosPiTest_b;
zAddr_uid62_fpCosPiTest_b <= zAddr_uid62_fpCosPiTest_in(34 downto 28);
--reg_zAddr_uid62_fpCosPiTest_0_to_memoryC2_uid209_sinPiZTableGenerator_0(REG,263)@3
reg_zAddr_uid62_fpCosPiTest_0_to_memoryC2_uid209_sinPiZTableGenerator_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_zAddr_uid62_fpCosPiTest_0_to_memoryC2_uid209_sinPiZTableGenerator_0_q <= "0000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_zAddr_uid62_fpCosPiTest_0_to_memoryC2_uid209_sinPiZTableGenerator_0_q <= zAddr_uid62_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--memoryC2_uid209_sinPiZTableGenerator(LOOKUP,208)@4
memoryC2_uid209_sinPiZTableGenerator: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
memoryC2_uid209_sinPiZTableGenerator_q <= "10101101010011";
ELSIF (clk'EVENT AND clk = '1' AND en = "1") THEN
CASE (reg_zAddr_uid62_fpCosPiTest_0_to_memoryC2_uid209_sinPiZTableGenerator_0_q) IS
WHEN "0000000" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101101010011";
WHEN "0000001" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101101010100";
WHEN "0000010" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101101010111";
WHEN "0000011" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101101011001";
WHEN "0000100" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101101011011";
WHEN "0000101" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101101011100";
WHEN "0000110" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101101011111";
WHEN "0000111" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101101100010";
WHEN "0001000" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101101100110";
WHEN "0001001" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101101101011";
WHEN "0001010" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101101110000";
WHEN "0001011" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101101110101";
WHEN "0001100" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101101111011";
WHEN "0001101" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101110000000";
WHEN "0001110" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101110000111";
WHEN "0001111" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101110001110";
WHEN "0010000" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101110010011";
WHEN "0010001" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101110011110";
WHEN "0010010" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101110100110";
WHEN "0010011" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101110101111";
WHEN "0010100" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101110111000";
WHEN "0010101" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101111000011";
WHEN "0010110" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101111001100";
WHEN "0010111" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101111010111";
WHEN "0011000" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101111100011";
WHEN "0011001" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101111101110";
WHEN "0011010" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101111111011";
WHEN "0011011" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110000001001";
WHEN "0011100" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110000010101";
WHEN "0011101" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110000100000";
WHEN "0011110" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110000110001";
WHEN "0011111" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110001000000";
WHEN "0100000" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110001001101";
WHEN "0100001" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110001011110";
WHEN "0100010" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110001101100";
WHEN "0100011" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110001111111";
WHEN "0100100" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110010001111";
WHEN "0100101" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110010100001";
WHEN "0100110" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110010110011";
WHEN "0100111" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110011000101";
WHEN "0101000" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110011010110";
WHEN "0101001" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110011101011";
WHEN "0101010" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110011111111";
WHEN "0101011" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110100010010";
WHEN "0101100" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110100100101";
WHEN "0101101" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110100111011";
WHEN "0101110" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110101001110";
WHEN "0101111" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110101100111";
WHEN "0110000" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110101111100";
WHEN "0110001" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110110010010";
WHEN "0110010" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110110100110";
WHEN "0110011" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110111000000";
WHEN "0110100" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110111010101";
WHEN "0110101" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110111110000";
WHEN "0110110" => memoryC2_uid209_sinPiZTableGenerator_q <= "10111000000110";
WHEN "0110111" => memoryC2_uid209_sinPiZTableGenerator_q <= "10111000100010";
WHEN "0111000" => memoryC2_uid209_sinPiZTableGenerator_q <= "10111000111001";
WHEN "0111001" => memoryC2_uid209_sinPiZTableGenerator_q <= "10111001010100";
WHEN "0111010" => memoryC2_uid209_sinPiZTableGenerator_q <= "10111001101111";
WHEN "0111011" => memoryC2_uid209_sinPiZTableGenerator_q <= "10111010001001";
WHEN "0111100" => memoryC2_uid209_sinPiZTableGenerator_q <= "10111010100011";
WHEN "0111101" => memoryC2_uid209_sinPiZTableGenerator_q <= "10111010111100";
WHEN "0111110" => memoryC2_uid209_sinPiZTableGenerator_q <= "10111011011001";
WHEN "0111111" => memoryC2_uid209_sinPiZTableGenerator_q <= "10111011110111";
WHEN "1000000" => memoryC2_uid209_sinPiZTableGenerator_q <= "10111100010100";
WHEN "1000001" => memoryC2_uid209_sinPiZTableGenerator_q <= "10111100110001";
WHEN "1000010" => memoryC2_uid209_sinPiZTableGenerator_q <= "10111101001101";
WHEN "1000011" => memoryC2_uid209_sinPiZTableGenerator_q <= "10111101101010";
WHEN "1000100" => memoryC2_uid209_sinPiZTableGenerator_q <= "10111110001000";
WHEN "1000101" => memoryC2_uid209_sinPiZTableGenerator_q <= "10111110100101";
WHEN "1000110" => memoryC2_uid209_sinPiZTableGenerator_q <= "10111111000101";
WHEN "1000111" => memoryC2_uid209_sinPiZTableGenerator_q <= "10111111100011";
WHEN "1001000" => memoryC2_uid209_sinPiZTableGenerator_q <= "11000000000011";
WHEN "1001001" => memoryC2_uid209_sinPiZTableGenerator_q <= "11000000100011";
WHEN "1001010" => memoryC2_uid209_sinPiZTableGenerator_q <= "11000001000100";
WHEN "1001011" => memoryC2_uid209_sinPiZTableGenerator_q <= "11000001100010";
WHEN "1001100" => memoryC2_uid209_sinPiZTableGenerator_q <= "11000010000100";
WHEN "1001101" => memoryC2_uid209_sinPiZTableGenerator_q <= "11000010100010";
WHEN "1001110" => memoryC2_uid209_sinPiZTableGenerator_q <= "11000011000110";
WHEN "1001111" => memoryC2_uid209_sinPiZTableGenerator_q <= "11000011101000";
WHEN "1010000" => memoryC2_uid209_sinPiZTableGenerator_q <= "11000100001010";
WHEN "1010001" => memoryC2_uid209_sinPiZTableGenerator_q <= "11000100101101";
WHEN "1010010" => memoryC2_uid209_sinPiZTableGenerator_q <= "11000101010001";
WHEN "1010011" => memoryC2_uid209_sinPiZTableGenerator_q <= "11000101110010";
WHEN "1010100" => memoryC2_uid209_sinPiZTableGenerator_q <= "11000110010100";
WHEN "1010101" => memoryC2_uid209_sinPiZTableGenerator_q <= "11000110111011";
WHEN "1010110" => memoryC2_uid209_sinPiZTableGenerator_q <= "11000111011010";
WHEN "1010111" => memoryC2_uid209_sinPiZTableGenerator_q <= "11001000000001";
WHEN "1011000" => memoryC2_uid209_sinPiZTableGenerator_q <= "11001000100110";
WHEN "1011001" => memoryC2_uid209_sinPiZTableGenerator_q <= "11001001001011";
WHEN "1011010" => memoryC2_uid209_sinPiZTableGenerator_q <= "11001001101101";
WHEN "1011011" => memoryC2_uid209_sinPiZTableGenerator_q <= "11001010010101";
WHEN "1011100" => memoryC2_uid209_sinPiZTableGenerator_q <= "11001010111100";
WHEN "1011101" => memoryC2_uid209_sinPiZTableGenerator_q <= "11001011100000";
WHEN "1011110" => memoryC2_uid209_sinPiZTableGenerator_q <= "11001100000101";
WHEN "1011111" => memoryC2_uid209_sinPiZTableGenerator_q <= "11001100101110";
WHEN "1100000" => memoryC2_uid209_sinPiZTableGenerator_q <= "11001101010100";
WHEN "1100001" => memoryC2_uid209_sinPiZTableGenerator_q <= "11001101111010";
WHEN "1100010" => memoryC2_uid209_sinPiZTableGenerator_q <= "11001110100010";
WHEN "1100011" => memoryC2_uid209_sinPiZTableGenerator_q <= "11001111001001";
WHEN "1100100" => memoryC2_uid209_sinPiZTableGenerator_q <= "11001111110001";
WHEN "1100101" => memoryC2_uid209_sinPiZTableGenerator_q <= "11010000010110";
WHEN "1100110" => memoryC2_uid209_sinPiZTableGenerator_q <= "11010000111111";
WHEN "1100111" => memoryC2_uid209_sinPiZTableGenerator_q <= "11010001101001";
WHEN "1101000" => memoryC2_uid209_sinPiZTableGenerator_q <= "11010010010010";
WHEN "1101001" => memoryC2_uid209_sinPiZTableGenerator_q <= "11010010111101";
WHEN "1101010" => memoryC2_uid209_sinPiZTableGenerator_q <= "11010011100001";
WHEN "1101011" => memoryC2_uid209_sinPiZTableGenerator_q <= "11010100001100";
WHEN "1101100" => memoryC2_uid209_sinPiZTableGenerator_q <= "11010100110111";
WHEN "1101101" => memoryC2_uid209_sinPiZTableGenerator_q <= "11010101100001";
WHEN "1101110" => memoryC2_uid209_sinPiZTableGenerator_q <= "11010110001011";
WHEN "1101111" => memoryC2_uid209_sinPiZTableGenerator_q <= "11010110110011";
WHEN "1110000" => memoryC2_uid209_sinPiZTableGenerator_q <= "11010111011111";
WHEN "1110001" => memoryC2_uid209_sinPiZTableGenerator_q <= "11011000001010";
WHEN "1110010" => memoryC2_uid209_sinPiZTableGenerator_q <= "11011000110100";
WHEN "1110011" => memoryC2_uid209_sinPiZTableGenerator_q <= "11011001011111";
WHEN "1110100" => memoryC2_uid209_sinPiZTableGenerator_q <= "11011010001010";
WHEN "1110101" => memoryC2_uid209_sinPiZTableGenerator_q <= "11011010110110";
WHEN "1110110" => memoryC2_uid209_sinPiZTableGenerator_q <= "11011011100011";
WHEN "1110111" => memoryC2_uid209_sinPiZTableGenerator_q <= "11011100001111";
WHEN "1111000" => memoryC2_uid209_sinPiZTableGenerator_q <= "11011100111001";
WHEN "1111001" => memoryC2_uid209_sinPiZTableGenerator_q <= "11011101100011";
WHEN "1111010" => memoryC2_uid209_sinPiZTableGenerator_q <= "11011110010001";
WHEN "1111011" => memoryC2_uid209_sinPiZTableGenerator_q <= "11011110111011";
WHEN "1111100" => memoryC2_uid209_sinPiZTableGenerator_q <= "11011111101000";
WHEN "1111101" => memoryC2_uid209_sinPiZTableGenerator_q <= "11100000010101";
WHEN "1111110" => memoryC2_uid209_sinPiZTableGenerator_q <= "11100001000010";
WHEN "1111111" => memoryC2_uid209_sinPiZTableGenerator_q <= "11100001110000";
WHEN OTHERS =>
memoryC2_uid209_sinPiZTableGenerator_q <= (others => '-');
END CASE;
END IF;
END PROCESS;
--zPPolyEval_uid63_fpCosPiTest(BITSELECT,62)@3
zPPolyEval_uid63_fpCosPiTest_in <= z_uid54_fpCosPiTest_b(27 downto 0);
zPPolyEval_uid63_fpCosPiTest_b <= zPPolyEval_uid63_fpCosPiTest_in(27 downto 12);
--yT1_uid210_sinPiZPolyEval(BITSELECT,209)@3
yT1_uid210_sinPiZPolyEval_in <= zPPolyEval_uid63_fpCosPiTest_b;
yT1_uid210_sinPiZPolyEval_b <= yT1_uid210_sinPiZPolyEval_in(15 downto 2);
--reg_yT1_uid210_sinPiZPolyEval_0_to_prodXY_uid226_pT1_uid211_sinPiZPolyEval_0(REG,264)@3
reg_yT1_uid210_sinPiZPolyEval_0_to_prodXY_uid226_pT1_uid211_sinPiZPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT1_uid210_sinPiZPolyEval_0_to_prodXY_uid226_pT1_uid211_sinPiZPolyEval_0_q <= "00000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT1_uid210_sinPiZPolyEval_0_to_prodXY_uid226_pT1_uid211_sinPiZPolyEval_0_q <= yT1_uid210_sinPiZPolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_reg_yT1_uid210_sinPiZPolyEval_0_to_prodXY_uid226_pT1_uid211_sinPiZPolyEval_0_q_to_prodXY_uid226_pT1_uid211_sinPiZPolyEval_a(DELAY,499)@4
ld_reg_yT1_uid210_sinPiZPolyEval_0_to_prodXY_uid226_pT1_uid211_sinPiZPolyEval_0_q_to_prodXY_uid226_pT1_uid211_sinPiZPolyEval_a : dspba_delay
GENERIC MAP ( width => 14, depth => 1 )
PORT MAP ( xin => reg_yT1_uid210_sinPiZPolyEval_0_to_prodXY_uid226_pT1_uid211_sinPiZPolyEval_0_q, xout => ld_reg_yT1_uid210_sinPiZPolyEval_0_to_prodXY_uid226_pT1_uid211_sinPiZPolyEval_0_q_to_prodXY_uid226_pT1_uid211_sinPiZPolyEval_a_q, ena => en(0), clk => clk, aclr => areset );
--prodXY_uid226_pT1_uid211_sinPiZPolyEval(MULT,225)@5
prodXY_uid226_pT1_uid211_sinPiZPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid226_pT1_uid211_sinPiZPolyEval_a),15)) * SIGNED(prodXY_uid226_pT1_uid211_sinPiZPolyEval_b);
prodXY_uid226_pT1_uid211_sinPiZPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid226_pT1_uid211_sinPiZPolyEval_a <= (others => '0');
prodXY_uid226_pT1_uid211_sinPiZPolyEval_b <= (others => '0');
prodXY_uid226_pT1_uid211_sinPiZPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid226_pT1_uid211_sinPiZPolyEval_a <= ld_reg_yT1_uid210_sinPiZPolyEval_0_to_prodXY_uid226_pT1_uid211_sinPiZPolyEval_0_q_to_prodXY_uid226_pT1_uid211_sinPiZPolyEval_a_q;
prodXY_uid226_pT1_uid211_sinPiZPolyEval_b <= memoryC2_uid209_sinPiZTableGenerator_q;
prodXY_uid226_pT1_uid211_sinPiZPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid226_pT1_uid211_sinPiZPolyEval_pr,28));
END IF;
END IF;
END PROCESS;
prodXY_uid226_pT1_uid211_sinPiZPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid226_pT1_uid211_sinPiZPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid226_pT1_uid211_sinPiZPolyEval_q <= prodXY_uid226_pT1_uid211_sinPiZPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid227_pT1_uid211_sinPiZPolyEval(BITSELECT,226)@8
prodXYTruncFR_uid227_pT1_uid211_sinPiZPolyEval_in <= prodXY_uid226_pT1_uid211_sinPiZPolyEval_q;
prodXYTruncFR_uid227_pT1_uid211_sinPiZPolyEval_b <= prodXYTruncFR_uid227_pT1_uid211_sinPiZPolyEval_in(27 downto 13);
--highBBits_uid213_sinPiZPolyEval(BITSELECT,212)@8
highBBits_uid213_sinPiZPolyEval_in <= prodXYTruncFR_uid227_pT1_uid211_sinPiZPolyEval_b;
highBBits_uid213_sinPiZPolyEval_b <= highBBits_uid213_sinPiZPolyEval_in(14 downto 1);
--ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_notEnable(LOGICAL,557)
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_notEnable_a <= en;
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_notEnable_q <= not ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_notEnable_a;
--ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_nor(LOGICAL,596)
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_nor_a <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_notEnable_q;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_nor_b <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_sticky_ena_q;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_nor_q <= not (ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_nor_a or ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_nor_b);
--ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_mem_top(CONSTANT,592)
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_mem_top_q <= "010";
--ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_cmp(LOGICAL,593)
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_cmp_a <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_mem_top_q;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdmux_q);
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_cmp_q <= "1" when ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_cmp_a = ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_cmp_b else "0";
--ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_cmpReg(REG,594)
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_cmpReg_q <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_sticky_ena(REG,597)
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_nor_q = "1") THEN
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_sticky_ena_q <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_enaAnd(LOGICAL,598)
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_enaAnd_a <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_sticky_ena_q;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_enaAnd_b <= en;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_enaAnd_q <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_enaAnd_a and ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_enaAnd_b;
--ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt(COUNTER,588)
-- every=1, low=0, high=2, step=1, init=1
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt_i <= TO_UNSIGNED(1,2);
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt_i = 1 THEN
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt_eq = '1') THEN
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt_i <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt_i - 2;
ELSE
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt_i <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt_i,2));
--ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdreg(REG,589)
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdreg_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdreg_q <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdmux(MUX,590)
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdmux_s <= en;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdmux: PROCESS (ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdmux_s, ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdreg_q, ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdmux_s IS
WHEN "0" => ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdmux_q <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdreg_q;
WHEN "1" => ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdmux_q <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem(DUALMEM,587)
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_reset0 <= areset;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_ia <= reg_zAddr_uid62_fpCosPiTest_0_to_memoryC2_uid209_sinPiZTableGenerator_0_q;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_aa <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdreg_q;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_ab <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdmux_q;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 7,
widthad_a => 2,
numwords_a => 3,
width_b => 7,
widthad_b => 2,
numwords_b => 3,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_iq,
address_a => ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_aa,
data_a => ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_ia
);
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_q <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_iq(6 downto 0);
--memoryC1_uid208_sinPiZTableGenerator(LOOKUP,207)@8
memoryC1_uid208_sinPiZTableGenerator: PROCESS (ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_q)
BEGIN
-- Begin reserved scope level
CASE (ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_q) IS
WHEN "0000000" => memoryC1_uid208_sinPiZTableGenerator_q <= "000000000000000000001";
WHEN "0000001" => memoryC1_uid208_sinPiZTableGenerator_q <= "111111101011010101010";
WHEN "0000010" => memoryC1_uid208_sinPiZTableGenerator_q <= "111111010110101010001";
WHEN "0000011" => memoryC1_uid208_sinPiZTableGenerator_q <= "111111000001111111100";
WHEN "0000100" => memoryC1_uid208_sinPiZTableGenerator_q <= "111110101101010101010";
WHEN "0000101" => memoryC1_uid208_sinPiZTableGenerator_q <= "111110011000101011101";
WHEN "0000110" => memoryC1_uid208_sinPiZTableGenerator_q <= "111110000100000010101";
WHEN "0000111" => memoryC1_uid208_sinPiZTableGenerator_q <= "111101101111011010001";
WHEN "0001000" => memoryC1_uid208_sinPiZTableGenerator_q <= "111101011010110010101";
WHEN "0001001" => memoryC1_uid208_sinPiZTableGenerator_q <= "111101000110001011111";
WHEN "0001010" => memoryC1_uid208_sinPiZTableGenerator_q <= "111100110001100110010";
WHEN "0001011" => memoryC1_uid208_sinPiZTableGenerator_q <= "111100011101000010000";
WHEN "0001100" => memoryC1_uid208_sinPiZTableGenerator_q <= "111100001000011110111";
WHEN "0001101" => memoryC1_uid208_sinPiZTableGenerator_q <= "111011110011111101011";
WHEN "0001110" => memoryC1_uid208_sinPiZTableGenerator_q <= "111011011111011101011";
WHEN "0001111" => memoryC1_uid208_sinPiZTableGenerator_q <= "111011001010111110111";
WHEN "0010000" => memoryC1_uid208_sinPiZTableGenerator_q <= "111010110110100010101";
WHEN "0010001" => memoryC1_uid208_sinPiZTableGenerator_q <= "111010100010000111100";
WHEN "0010010" => memoryC1_uid208_sinPiZTableGenerator_q <= "111010001101101111000";
WHEN "0010011" => memoryC1_uid208_sinPiZTableGenerator_q <= "111001111001011000011";
WHEN "0010100" => memoryC1_uid208_sinPiZTableGenerator_q <= "111001100101000100010";
WHEN "0010101" => memoryC1_uid208_sinPiZTableGenerator_q <= "111001010000110010001";
WHEN "0010110" => memoryC1_uid208_sinPiZTableGenerator_q <= "111000111100100010111";
WHEN "0010111" => memoryC1_uid208_sinPiZTableGenerator_q <= "111000101000010110001";
WHEN "0011000" => memoryC1_uid208_sinPiZTableGenerator_q <= "111000010100001011111";
WHEN "0011001" => memoryC1_uid208_sinPiZTableGenerator_q <= "111000000000000100110";
WHEN "0011010" => memoryC1_uid208_sinPiZTableGenerator_q <= "110111101100000000011";
WHEN "0011011" => memoryC1_uid208_sinPiZTableGenerator_q <= "110111010111111111000";
WHEN "0011100" => memoryC1_uid208_sinPiZTableGenerator_q <= "110111000100000001000";
WHEN "0011101" => memoryC1_uid208_sinPiZTableGenerator_q <= "110110110000000110101";
WHEN "0011110" => memoryC1_uid208_sinPiZTableGenerator_q <= "110110011100001110111";
WHEN "0011111" => memoryC1_uid208_sinPiZTableGenerator_q <= "110110001000011011000";
WHEN "0100000" => memoryC1_uid208_sinPiZTableGenerator_q <= "110101110100101011010";
WHEN "0100001" => memoryC1_uid208_sinPiZTableGenerator_q <= "110101100000111110101";
WHEN "0100010" => memoryC1_uid208_sinPiZTableGenerator_q <= "110101001101010110010";
WHEN "0100011" => memoryC1_uid208_sinPiZTableGenerator_q <= "110100111001110001011";
WHEN "0100100" => memoryC1_uid208_sinPiZTableGenerator_q <= "110100100110010001001";
WHEN "0100101" => memoryC1_uid208_sinPiZTableGenerator_q <= "110100010010110100110";
WHEN "0100110" => memoryC1_uid208_sinPiZTableGenerator_q <= "110011111111011100110";
WHEN "0100111" => memoryC1_uid208_sinPiZTableGenerator_q <= "110011101100001001010";
WHEN "0101000" => memoryC1_uid208_sinPiZTableGenerator_q <= "110011011000111010011";
WHEN "0101001" => memoryC1_uid208_sinPiZTableGenerator_q <= "110011000101101111111";
WHEN "0101010" => memoryC1_uid208_sinPiZTableGenerator_q <= "110010110010101010010";
WHEN "0101011" => memoryC1_uid208_sinPiZTableGenerator_q <= "110010011111101001101";
WHEN "0101100" => memoryC1_uid208_sinPiZTableGenerator_q <= "110010001100101110000";
WHEN "0101101" => memoryC1_uid208_sinPiZTableGenerator_q <= "110001111001110111001";
WHEN "0101110" => memoryC1_uid208_sinPiZTableGenerator_q <= "110001100111000110000";
WHEN "0101111" => memoryC1_uid208_sinPiZTableGenerator_q <= "110001010100011001011";
WHEN "0110000" => memoryC1_uid208_sinPiZTableGenerator_q <= "110001000001110010110";
WHEN "0110001" => memoryC1_uid208_sinPiZTableGenerator_q <= "110000101111010001100";
WHEN "0110010" => memoryC1_uid208_sinPiZTableGenerator_q <= "110000011100110110001";
WHEN "0110011" => memoryC1_uid208_sinPiZTableGenerator_q <= "110000001010011111111";
WHEN "0110100" => memoryC1_uid208_sinPiZTableGenerator_q <= "101111111000010000000";
WHEN "0110101" => memoryC1_uid208_sinPiZTableGenerator_q <= "101111100110000101100";
WHEN "0110110" => memoryC1_uid208_sinPiZTableGenerator_q <= "101111010100000001100";
WHEN "0110111" => memoryC1_uid208_sinPiZTableGenerator_q <= "101111000010000011001";
WHEN "0111000" => memoryC1_uid208_sinPiZTableGenerator_q <= "101110110000001011100";
WHEN "0111001" => memoryC1_uid208_sinPiZTableGenerator_q <= "101110011110011001110";
WHEN "0111010" => memoryC1_uid208_sinPiZTableGenerator_q <= "101110001100101110101";
WHEN "0111011" => memoryC1_uid208_sinPiZTableGenerator_q <= "101101111011001010001";
WHEN "0111100" => memoryC1_uid208_sinPiZTableGenerator_q <= "101101101001101100010";
WHEN "0111101" => memoryC1_uid208_sinPiZTableGenerator_q <= "101101011000010101010";
WHEN "0111110" => memoryC1_uid208_sinPiZTableGenerator_q <= "101101000111000100101";
WHEN "0111111" => memoryC1_uid208_sinPiZTableGenerator_q <= "101100110101111010111";
WHEN "1000000" => memoryC1_uid208_sinPiZTableGenerator_q <= "101100100100111000010";
WHEN "1000001" => memoryC1_uid208_sinPiZTableGenerator_q <= "101100010011111100111";
WHEN "1000010" => memoryC1_uid208_sinPiZTableGenerator_q <= "101100000011001000111";
WHEN "1000011" => memoryC1_uid208_sinPiZTableGenerator_q <= "101011110010011100000";
WHEN "1000100" => memoryC1_uid208_sinPiZTableGenerator_q <= "101011100001110110100";
WHEN "1000101" => memoryC1_uid208_sinPiZTableGenerator_q <= "101011010001011000100";
WHEN "1000110" => memoryC1_uid208_sinPiZTableGenerator_q <= "101011000001000001110";
WHEN "1000111" => memoryC1_uid208_sinPiZTableGenerator_q <= "101010110000110011000";
WHEN "1001000" => memoryC1_uid208_sinPiZTableGenerator_q <= "101010100000101011111";
WHEN "1001001" => memoryC1_uid208_sinPiZTableGenerator_q <= "101010010000101100100";
WHEN "1001010" => memoryC1_uid208_sinPiZTableGenerator_q <= "101010000000110101001";
WHEN "1001011" => memoryC1_uid208_sinPiZTableGenerator_q <= "101001110001000110000";
WHEN "1001100" => memoryC1_uid208_sinPiZTableGenerator_q <= "101001100001011110101";
WHEN "1001101" => memoryC1_uid208_sinPiZTableGenerator_q <= "101001010001111111111";
WHEN "1001110" => memoryC1_uid208_sinPiZTableGenerator_q <= "101001000010101000110";
WHEN "1001111" => memoryC1_uid208_sinPiZTableGenerator_q <= "101000110011011010001";
WHEN "1010000" => memoryC1_uid208_sinPiZTableGenerator_q <= "101000100100010100001";
WHEN "1010001" => memoryC1_uid208_sinPiZTableGenerator_q <= "101000010101010110100";
WHEN "1010010" => memoryC1_uid208_sinPiZTableGenerator_q <= "101000000110100001011";
WHEN "1010011" => memoryC1_uid208_sinPiZTableGenerator_q <= "100111110111110101011";
WHEN "1010100" => memoryC1_uid208_sinPiZTableGenerator_q <= "100111101001010010000";
WHEN "1010101" => memoryC1_uid208_sinPiZTableGenerator_q <= "100111011010110110110";
WHEN "1010110" => memoryC1_uid208_sinPiZTableGenerator_q <= "100111001100100101100";
WHEN "1010111" => memoryC1_uid208_sinPiZTableGenerator_q <= "100110111110011100011";
WHEN "1011000" => memoryC1_uid208_sinPiZTableGenerator_q <= "100110110000011100011";
WHEN "1011001" => memoryC1_uid208_sinPiZTableGenerator_q <= "100110100010100101110";
WHEN "1011010" => memoryC1_uid208_sinPiZTableGenerator_q <= "100110010100111000101";
WHEN "1011011" => memoryC1_uid208_sinPiZTableGenerator_q <= "100110000111010100001";
WHEN "1011100" => memoryC1_uid208_sinPiZTableGenerator_q <= "100101111001111001000";
WHEN "1011101" => memoryC1_uid208_sinPiZTableGenerator_q <= "100101101100100111111";
WHEN "1011110" => memoryC1_uid208_sinPiZTableGenerator_q <= "100101011111100000000";
WHEN "1011111" => memoryC1_uid208_sinPiZTableGenerator_q <= "100101010010100001001";
WHEN "1100000" => memoryC1_uid208_sinPiZTableGenerator_q <= "100101000101101100011";
WHEN "1100001" => memoryC1_uid208_sinPiZTableGenerator_q <= "100100111001000001011";
WHEN "1100010" => memoryC1_uid208_sinPiZTableGenerator_q <= "100100101100011111111";
WHEN "1100011" => memoryC1_uid208_sinPiZTableGenerator_q <= "100100100000001000010";
WHEN "1100100" => memoryC1_uid208_sinPiZTableGenerator_q <= "100100010011111010101";
WHEN "1100101" => memoryC1_uid208_sinPiZTableGenerator_q <= "100100000111110111001";
WHEN "1100110" => memoryC1_uid208_sinPiZTableGenerator_q <= "100011111011111101010";
WHEN "1100111" => memoryC1_uid208_sinPiZTableGenerator_q <= "100011110000001101010";
WHEN "1101000" => memoryC1_uid208_sinPiZTableGenerator_q <= "100011100100100111101";
WHEN "1101001" => memoryC1_uid208_sinPiZTableGenerator_q <= "100011011001001011111";
WHEN "1101010" => memoryC1_uid208_sinPiZTableGenerator_q <= "100011001101111011010";
WHEN "1101011" => memoryC1_uid208_sinPiZTableGenerator_q <= "100011000010110100001";
WHEN "1101100" => memoryC1_uid208_sinPiZTableGenerator_q <= "100010110111110111010";
WHEN "1101101" => memoryC1_uid208_sinPiZTableGenerator_q <= "100010101101000101000";
WHEN "1101110" => memoryC1_uid208_sinPiZTableGenerator_q <= "100010100010011101001";
WHEN "1101111" => memoryC1_uid208_sinPiZTableGenerator_q <= "100010011000000000001";
WHEN "1110000" => memoryC1_uid208_sinPiZTableGenerator_q <= "100010001101101101010";
WHEN "1110001" => memoryC1_uid208_sinPiZTableGenerator_q <= "100010000011100100111";
WHEN "1110010" => memoryC1_uid208_sinPiZTableGenerator_q <= "100001111001100111100";
WHEN "1110011" => memoryC1_uid208_sinPiZTableGenerator_q <= "100001101111110100101";
WHEN "1110100" => memoryC1_uid208_sinPiZTableGenerator_q <= "100001100110001100100";
WHEN "1110101" => memoryC1_uid208_sinPiZTableGenerator_q <= "100001011100101111001";
WHEN "1110110" => memoryC1_uid208_sinPiZTableGenerator_q <= "100001010011011100011";
WHEN "1110111" => memoryC1_uid208_sinPiZTableGenerator_q <= "100001001010010100101";
WHEN "1111000" => memoryC1_uid208_sinPiZTableGenerator_q <= "100001000001011000000";
WHEN "1111001" => memoryC1_uid208_sinPiZTableGenerator_q <= "100000111000100110100";
WHEN "1111010" => memoryC1_uid208_sinPiZTableGenerator_q <= "100000101111111111100";
WHEN "1111011" => memoryC1_uid208_sinPiZTableGenerator_q <= "100000100111100011111";
WHEN "1111100" => memoryC1_uid208_sinPiZTableGenerator_q <= "100000011111010011000";
WHEN "1111101" => memoryC1_uid208_sinPiZTableGenerator_q <= "100000010111001101010";
WHEN "1111110" => memoryC1_uid208_sinPiZTableGenerator_q <= "100000001111010010101";
WHEN "1111111" => memoryC1_uid208_sinPiZTableGenerator_q <= "100000000111100011001";
WHEN OTHERS =>
memoryC1_uid208_sinPiZTableGenerator_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--sumAHighB_uid214_sinPiZPolyEval(ADD,213)@8
sumAHighB_uid214_sinPiZPolyEval_a <= STD_LOGIC_VECTOR((21 downto 21 => memoryC1_uid208_sinPiZTableGenerator_q(20)) & memoryC1_uid208_sinPiZTableGenerator_q);
sumAHighB_uid214_sinPiZPolyEval_b <= STD_LOGIC_VECTOR((21 downto 14 => highBBits_uid213_sinPiZPolyEval_b(13)) & highBBits_uid213_sinPiZPolyEval_b);
sumAHighB_uid214_sinPiZPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid214_sinPiZPolyEval_a) + SIGNED(sumAHighB_uid214_sinPiZPolyEval_b));
sumAHighB_uid214_sinPiZPolyEval_q <= sumAHighB_uid214_sinPiZPolyEval_o(21 downto 0);
--lowRangeB_uid212_sinPiZPolyEval(BITSELECT,211)@8
lowRangeB_uid212_sinPiZPolyEval_in <= prodXYTruncFR_uid227_pT1_uid211_sinPiZPolyEval_b(0 downto 0);
lowRangeB_uid212_sinPiZPolyEval_b <= lowRangeB_uid212_sinPiZPolyEval_in(0 downto 0);
--s1_uid212_uid215_sinPiZPolyEval(BITJOIN,214)@8
s1_uid212_uid215_sinPiZPolyEval_q <= sumAHighB_uid214_sinPiZPolyEval_q & lowRangeB_uid212_sinPiZPolyEval_b;
--reg_s1_uid212_uid215_sinPiZPolyEval_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_1(REG,267)@8
reg_s1_uid212_uid215_sinPiZPolyEval_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_s1_uid212_uid215_sinPiZPolyEval_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_1_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_s1_uid212_uid215_sinPiZPolyEval_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_1_q <= s1_uid212_uid215_sinPiZPolyEval_q;
END IF;
END IF;
END PROCESS;
--ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_nor(LOGICAL,609)
ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_nor_a <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_notEnable_q;
ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_nor_b <= ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_sticky_ena_q;
ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_nor_q <= not (ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_nor_a or ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_nor_b);
--ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_sticky_ena(REG,610)
ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_nor_q = "1") THEN
ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_sticky_ena_q <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_enaAnd(LOGICAL,611)
ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_enaAnd_a <= ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_sticky_ena_q;
ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_enaAnd_b <= en;
ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_enaAnd_q <= ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_enaAnd_a and ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_enaAnd_b;
--ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_inputreg(DELAY,599)
ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 16, depth => 1 )
PORT MAP ( xin => zPPolyEval_uid63_fpCosPiTest_b, xout => ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem(DUALMEM,600)
ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_reset0 <= areset;
ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_ia <= ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_inputreg_q;
ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_aa <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdreg_q;
ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_ab <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdmux_q;
ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 16,
widthad_a => 2,
numwords_a => 3,
width_b => 16,
widthad_b => 2,
numwords_b => 3,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_iq,
address_a => ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_aa,
data_a => ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_ia
);
ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_q <= ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_iq(15 downto 0);
--reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0(REG,266)@8
reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_q <= ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--prodXY_uid229_pT2_uid217_sinPiZPolyEval(MULT,228)@9
prodXY_uid229_pT2_uid217_sinPiZPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid229_pT2_uid217_sinPiZPolyEval_a),17)) * SIGNED(prodXY_uid229_pT2_uid217_sinPiZPolyEval_b);
prodXY_uid229_pT2_uid217_sinPiZPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid229_pT2_uid217_sinPiZPolyEval_a <= (others => '0');
prodXY_uid229_pT2_uid217_sinPiZPolyEval_b <= (others => '0');
prodXY_uid229_pT2_uid217_sinPiZPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid229_pT2_uid217_sinPiZPolyEval_a <= reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_q;
prodXY_uid229_pT2_uid217_sinPiZPolyEval_b <= reg_s1_uid212_uid215_sinPiZPolyEval_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_1_q;
prodXY_uid229_pT2_uid217_sinPiZPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid229_pT2_uid217_sinPiZPolyEval_pr,39));
END IF;
END IF;
END PROCESS;
prodXY_uid229_pT2_uid217_sinPiZPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid229_pT2_uid217_sinPiZPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid229_pT2_uid217_sinPiZPolyEval_q <= prodXY_uid229_pT2_uid217_sinPiZPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid230_pT2_uid217_sinPiZPolyEval(BITSELECT,229)@12
prodXYTruncFR_uid230_pT2_uid217_sinPiZPolyEval_in <= prodXY_uid229_pT2_uid217_sinPiZPolyEval_q;
prodXYTruncFR_uid230_pT2_uid217_sinPiZPolyEval_b <= prodXYTruncFR_uid230_pT2_uid217_sinPiZPolyEval_in(38 downto 15);
--highBBits_uid219_sinPiZPolyEval(BITSELECT,218)@12
highBBits_uid219_sinPiZPolyEval_in <= prodXYTruncFR_uid230_pT2_uid217_sinPiZPolyEval_b;
highBBits_uid219_sinPiZPolyEval_b <= highBBits_uid219_sinPiZPolyEval_in(23 downto 2);
--ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_nor(LOGICAL,584)
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_nor_a <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_notEnable_q;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_nor_b <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_sticky_ena_q;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_nor_q <= not (ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_nor_a or ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_nor_b);
--ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_mem_top(CONSTANT,554)
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_mem_top_q <= "0110";
--ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_cmp(LOGICAL,555)
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_cmp_a <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_mem_top_q;
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdmux_q);
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_cmp_q <= "1" when ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_cmp_a = ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_cmp_b else "0";
--ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_cmpReg(REG,556)
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_cmpReg_q <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_sticky_ena(REG,585)
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_nor_q = "1") THEN
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_sticky_ena_q <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_enaAnd(LOGICAL,586)
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_enaAnd_a <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_sticky_ena_q;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_enaAnd_b <= en;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_enaAnd_q <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_enaAnd_a and ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_enaAnd_b;
--ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt(COUNTER,550)
-- every=1, low=0, high=6, step=1, init=1
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt_i = 5 THEN
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt_eq <= '1';
ELSE
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt_eq = '1') THEN
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt_i <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt_i - 6;
ELSE
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt_i <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt_i,3));
--ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdreg(REG,551)
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdreg_q <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdmux(MUX,552)
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdmux_s <= en;
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdmux: PROCESS (ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdmux_s, ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdreg_q, ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt_q)
BEGIN
CASE ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdmux_s IS
WHEN "0" => ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdmux_q <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdreg_q;
WHEN "1" => ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdmux_q <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem(DUALMEM,575)
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_reset0 <= areset;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_ia <= reg_zAddr_uid62_fpCosPiTest_0_to_memoryC2_uid209_sinPiZTableGenerator_0_q;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_aa <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdreg_q;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_ab <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdmux_q;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 7,
widthad_a => 3,
numwords_a => 7,
width_b => 7,
widthad_b => 3,
numwords_b => 7,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_iq,
address_a => ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_aa,
data_a => ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_ia
);
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_q <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_iq(6 downto 0);
--memoryC0_uid207_sinPiZTableGenerator(LOOKUP,206)@12
memoryC0_uid207_sinPiZTableGenerator: PROCESS (ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_q)
BEGIN
-- Begin reserved scope level
CASE (ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_q) IS
WHEN "0000000" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100100100001111110110101110";
WHEN "0000001" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100100100001110100100000010";
WHEN "0000010" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100100100001010101100000000";
WHEN "0000011" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100100100000100001110101000";
WHEN "0000100" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100100011111011001011111101";
WHEN "0000101" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100100011101111100100000010";
WHEN "0000110" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100100011100001010110111011";
WHEN "0000111" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100100011010000100100101111";
WHEN "0001000" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100100010111101001101100010";
WHEN "0001001" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100100010100111010001011101";
WHEN "0001010" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100100010001110110000100111";
WHEN "0001011" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100100001110011101011001001";
WHEN "0001100" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100100001010110000001001110";
WHEN "0001101" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100100000110101110011000000";
WHEN "0001110" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100100000010011000000101011";
WHEN "0001111" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100011111101101101010011101";
WHEN "0010000" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100011111000101110000100010";
WHEN "0010001" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100011110011011010011001011";
WHEN "0010010" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100011101101110010010100101";
WHEN "0010011" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100011100111110101111000011";
WHEN "0010100" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100011100001100101000110101";
WHEN "0010101" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100011011011000000000001111";
WHEN "0010110" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100011010100000110101100011";
WHEN "0010111" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100011001100111001001000110";
WHEN "0011000" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100011000101010111011001110";
WHEN "0011001" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100010111101100001100010000";
WHEN "0011010" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100010110101010111100100100";
WHEN "0011011" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100010101100111001100100010";
WHEN "0011100" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100010100100000111100100011";
WHEN "0011101" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100010011011000001101000000";
WHEN "0011110" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100010010001100111110010110";
WHEN "0011111" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100010000111111010000111111";
WHEN "0100000" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100001111101111000101010111";
WHEN "0100001" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100001110011100011011111110";
WHEN "0100010" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100001101000111010101010001";
WHEN "0100011" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100001011101111110001110000";
WHEN "0100100" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100001010010101110001111010";
WHEN "0100101" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100001000111001010110010010";
WHEN "0100110" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100000111011010011111011001";
WHEN "0100111" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100000101111001001101110010";
WHEN "0101000" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100000100010101100010000001";
WHEN "0101001" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100000010101111011100101011";
WHEN "0101010" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100000001000110111110010101";
WHEN "0101011" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011111111011100000111100110";
WHEN "0101100" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011111101101110111001000101";
WHEN "0101101" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011111011111111010011011011";
WHEN "0101110" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011111010001101010111001111";
WHEN "0101111" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011111000011001000101001110";
WHEN "0110000" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011110110100010011110000000";
WHEN "0110001" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011110100101001100010010010";
WHEN "0110010" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011110010101110010010110000";
WHEN "0110011" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011110000110000110000001000";
WHEN "0110100" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011101110110000111011000111";
WHEN "0110101" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011101100101110110100011101";
WHEN "0110110" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011101010101010011100111001";
WHEN "0110111" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011101000100011110101001100";
WHEN "0111000" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011100110011010111110000111";
WHEN "0111001" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011100100001111111000011101";
WHEN "0111010" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011100010000010100101000000";
WHEN "0111011" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011011111110011000100100100";
WHEN "0111100" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011011101100001010111111110";
WHEN "0111101" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011011011001101100000000011";
WHEN "0111110" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011011000110111011101101010";
WHEN "0111111" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011010110011111010001101001";
WHEN "1000000" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011010100000100111100111000";
WHEN "1000001" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011010001101000100000001111";
WHEN "1000010" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011001111001001111100100111";
WHEN "1000011" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011001100101001010010111011";
WHEN "1000100" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011001010000110100100000101";
WHEN "1000101" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011000111100001110001000001";
WHEN "1000110" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011000100111010111010101011";
WHEN "1000111" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011000010010010000001111111";
WHEN "1001000" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010111111100111000111111011";
WHEN "1001001" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010111100111010001101011110";
WHEN "1001010" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010111010001011010011100110";
WHEN "1001011" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010110111011010011011010011";
WHEN "1001100" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010110100100111100101100110";
WHEN "1001101" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010110001110010110011011111";
WHEN "1001110" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010101110111100000110000001";
WHEN "1001111" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010101100000011011110001110";
WHEN "1010000" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010101001001000111101001000";
WHEN "1010001" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010100110001100100011110100";
WHEN "1010010" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010100011001110010011010110";
WHEN "1010011" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010100000001110001100110010";
WHEN "1010100" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010011101001100010001001111";
WHEN "1010101" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010011010001000100001110100";
WHEN "1010110" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010010111000010111111100101";
WHEN "1010111" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010010011111011101011101100";
WHEN "1011000" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010010000110010100111010001";
WHEN "1011001" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010001101100111110011011011";
WHEN "1011010" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010001010011011010001010100";
WHEN "1011011" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010000111001101000010000111";
WHEN "1011100" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010000011111101000110111110";
WHEN "1011101" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010000000101011100001000010";
WHEN "1011110" => memoryC0_uid207_sinPiZTableGenerator_q <= "01001111101011000010001100001";
WHEN "1011111" => memoryC0_uid207_sinPiZTableGenerator_q <= "01001111010000011011001100111";
WHEN "1100000" => memoryC0_uid207_sinPiZTableGenerator_q <= "01001110110101100111010011111";
WHEN "1100001" => memoryC0_uid207_sinPiZTableGenerator_q <= "01001110011010100110101010111";
WHEN "1100010" => memoryC0_uid207_sinPiZTableGenerator_q <= "01001101111111011001011011101";
WHEN "1100011" => memoryC0_uid207_sinPiZTableGenerator_q <= "01001101100011111111101111111";
WHEN "1100100" => memoryC0_uid207_sinPiZTableGenerator_q <= "01001101001000011001110001011";
WHEN "1100101" => memoryC0_uid207_sinPiZTableGenerator_q <= "01001100101100100111101010001";
WHEN "1100110" => memoryC0_uid207_sinPiZTableGenerator_q <= "01001100010000101001100100001";
WHEN "1100111" => memoryC0_uid207_sinPiZTableGenerator_q <= "01001011110100011111101001011";
WHEN "1101000" => memoryC0_uid207_sinPiZTableGenerator_q <= "01001011011000001010000011111";
WHEN "1101001" => memoryC0_uid207_sinPiZTableGenerator_q <= "01001010111011101000111101111";
WHEN "1101010" => memoryC0_uid207_sinPiZTableGenerator_q <= "01001010011110111100100001011";
WHEN "1101011" => memoryC0_uid207_sinPiZTableGenerator_q <= "01001010000010000100111000111";
WHEN "1101100" => memoryC0_uid207_sinPiZTableGenerator_q <= "01001001100101000010001110101";
WHEN "1101101" => memoryC0_uid207_sinPiZTableGenerator_q <= "01001001000111110100101100111";
WHEN "1101110" => memoryC0_uid207_sinPiZTableGenerator_q <= "01001000101010011100011110001";
WHEN "1101111" => memoryC0_uid207_sinPiZTableGenerator_q <= "01001000001100111001101100110";
WHEN "1110000" => memoryC0_uid207_sinPiZTableGenerator_q <= "01000111101111001100100011011";
WHEN "1110001" => memoryC0_uid207_sinPiZTableGenerator_q <= "01000111010001010101001100101";
WHEN "1110010" => memoryC0_uid207_sinPiZTableGenerator_q <= "01000110110011010011110010111";
WHEN "1110011" => memoryC0_uid207_sinPiZTableGenerator_q <= "01000110010101001000100001000";
WHEN "1110100" => memoryC0_uid207_sinPiZTableGenerator_q <= "01000101110110110011100001101";
WHEN "1110101" => memoryC0_uid207_sinPiZTableGenerator_q <= "01000101011000010100111111100";
WHEN "1110110" => memoryC0_uid207_sinPiZTableGenerator_q <= "01000100111001101101000101100";
WHEN "1110111" => memoryC0_uid207_sinPiZTableGenerator_q <= "01000100011010111011111110011";
WHEN "1111000" => memoryC0_uid207_sinPiZTableGenerator_q <= "01000011111100000001110101000";
WHEN "1111001" => memoryC0_uid207_sinPiZTableGenerator_q <= "01000011011100111110110100010";
WHEN "1111010" => memoryC0_uid207_sinPiZTableGenerator_q <= "01000010111101110011000111010";
WHEN "1111011" => memoryC0_uid207_sinPiZTableGenerator_q <= "01000010011110011110111000111";
WHEN "1111100" => memoryC0_uid207_sinPiZTableGenerator_q <= "01000001111111000010010100010";
WHEN "1111101" => memoryC0_uid207_sinPiZTableGenerator_q <= "01000001011111011101100100011";
WHEN "1111110" => memoryC0_uid207_sinPiZTableGenerator_q <= "01000000111111110000110100011";
WHEN "1111111" => memoryC0_uid207_sinPiZTableGenerator_q <= "01000000011111111100001111011";
WHEN OTHERS =>
memoryC0_uid207_sinPiZTableGenerator_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--sumAHighB_uid220_sinPiZPolyEval(ADD,219)@12
sumAHighB_uid220_sinPiZPolyEval_a <= STD_LOGIC_VECTOR((29 downto 29 => memoryC0_uid207_sinPiZTableGenerator_q(28)) & memoryC0_uid207_sinPiZTableGenerator_q);
sumAHighB_uid220_sinPiZPolyEval_b <= STD_LOGIC_VECTOR((29 downto 22 => highBBits_uid219_sinPiZPolyEval_b(21)) & highBBits_uid219_sinPiZPolyEval_b);
sumAHighB_uid220_sinPiZPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid220_sinPiZPolyEval_a) + SIGNED(sumAHighB_uid220_sinPiZPolyEval_b));
sumAHighB_uid220_sinPiZPolyEval_q <= sumAHighB_uid220_sinPiZPolyEval_o(29 downto 0);
--lowRangeB_uid218_sinPiZPolyEval(BITSELECT,217)@12
lowRangeB_uid218_sinPiZPolyEval_in <= prodXYTruncFR_uid230_pT2_uid217_sinPiZPolyEval_b(1 downto 0);
lowRangeB_uid218_sinPiZPolyEval_b <= lowRangeB_uid218_sinPiZPolyEval_in(1 downto 0);
--s2_uid218_uid221_sinPiZPolyEval(BITJOIN,220)@12
s2_uid218_uid221_sinPiZPolyEval_q <= sumAHighB_uid220_sinPiZPolyEval_q & lowRangeB_uid218_sinPiZPolyEval_b;
--fxpSinRes_uid65_fpCosPiTest(BITSELECT,64)@12
fxpSinRes_uid65_fpCosPiTest_in <= s2_uid218_uid221_sinPiZPolyEval_q(29 downto 0);
fxpSinRes_uid65_fpCosPiTest_b <= fxpSinRes_uid65_fpCosPiTest_in(29 downto 5);
--reg_fxpSinRes_uid65_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_1(REG,270)@12
reg_fxpSinRes_uid65_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fxpSinRes_uid65_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_1_q <= "0000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fxpSinRes_uid65_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_1_q <= fxpSinRes_uid65_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_nor(LOGICAL,622)
ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_nor_a <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_notEnable_q;
ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_nor_b <= ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_sticky_ena_q;
ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_nor_q <= not (ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_nor_a or ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_nor_b);
--ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_sticky_ena(REG,623)
ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_nor_q = "1") THEN
ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_sticky_ena_q <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_enaAnd(LOGICAL,624)
ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_enaAnd_a <= ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_sticky_ena_q;
ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_enaAnd_b <= en;
ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_enaAnd_q <= ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_enaAnd_a and ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_enaAnd_b;
--LeftShiftStage131dto0_uid202_alignedZ_uid57_fpCosPiTest(BITSELECT,201)@7
LeftShiftStage131dto0_uid202_alignedZ_uid57_fpCosPiTest_in <= leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_q(31 downto 0);
LeftShiftStage131dto0_uid202_alignedZ_uid57_fpCosPiTest_b <= LeftShiftStage131dto0_uid202_alignedZ_uid57_fpCosPiTest_in(31 downto 0);
--leftShiftStage2Idx3_uid203_alignedZ_uid57_fpCosPiTest(BITJOIN,202)@7
leftShiftStage2Idx3_uid203_alignedZ_uid57_fpCosPiTest_q <= LeftShiftStage131dto0_uid202_alignedZ_uid57_fpCosPiTest_b & leftShiftStage2Idx3Pad3_uid131_fxpX_uid41_fpCosPiTest_q;
--LeftShiftStage132dto0_uid199_alignedZ_uid57_fpCosPiTest(BITSELECT,198)@7
LeftShiftStage132dto0_uid199_alignedZ_uid57_fpCosPiTest_in <= leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_q(32 downto 0);
LeftShiftStage132dto0_uid199_alignedZ_uid57_fpCosPiTest_b <= LeftShiftStage132dto0_uid199_alignedZ_uid57_fpCosPiTest_in(32 downto 0);
--leftShiftStage2Idx2_uid200_alignedZ_uid57_fpCosPiTest(BITJOIN,199)@7
leftShiftStage2Idx2_uid200_alignedZ_uid57_fpCosPiTest_q <= LeftShiftStage132dto0_uid199_alignedZ_uid57_fpCosPiTest_b & leftShiftStage2Idx2Pad2_uid128_fxpX_uid41_fpCosPiTest_q;
--LeftShiftStage133dto0_uid196_alignedZ_uid57_fpCosPiTest(BITSELECT,195)@7
LeftShiftStage133dto0_uid196_alignedZ_uid57_fpCosPiTest_in <= leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_q(33 downto 0);
LeftShiftStage133dto0_uid196_alignedZ_uid57_fpCosPiTest_b <= LeftShiftStage133dto0_uid196_alignedZ_uid57_fpCosPiTest_in(33 downto 0);
--leftShiftStage2Idx1_uid197_alignedZ_uid57_fpCosPiTest(BITJOIN,196)@7
leftShiftStage2Idx1_uid197_alignedZ_uid57_fpCosPiTest_q <= LeftShiftStage133dto0_uid196_alignedZ_uid57_fpCosPiTest_b & GND_q;
--vStage_uid141_lzcZ_uid56_fpCosPiTest(BITSELECT,140)@3
vStage_uid141_lzcZ_uid56_fpCosPiTest_in <= z_uid54_fpCosPiTest_b(2 downto 0);
vStage_uid141_lzcZ_uid56_fpCosPiTest_b <= vStage_uid141_lzcZ_uid56_fpCosPiTest_in(2 downto 0);
--ld_vStage_uid141_lzcZ_uid56_fpCosPiTest_b_to_leftShiftStage0Idx2_uid180_alignedZ_uid57_fpCosPiTest_b(DELAY,450)@3
ld_vStage_uid141_lzcZ_uid56_fpCosPiTest_b_to_leftShiftStage0Idx2_uid180_alignedZ_uid57_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 3, depth => 3 )
PORT MAP ( xin => vStage_uid141_lzcZ_uid56_fpCosPiTest_b, xout => ld_vStage_uid141_lzcZ_uid56_fpCosPiTest_b_to_leftShiftStage0Idx2_uid180_alignedZ_uid57_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage0Idx2_uid180_alignedZ_uid57_fpCosPiTest(BITJOIN,179)@6
leftShiftStage0Idx2_uid180_alignedZ_uid57_fpCosPiTest_q <= ld_vStage_uid141_lzcZ_uid56_fpCosPiTest_b_to_leftShiftStage0Idx2_uid180_alignedZ_uid57_fpCosPiTest_b_q & leftShiftStage0Idx2Pad32_uid108_fxpX_uid41_fpCosPiTest_q;
--X18dto0_uid176_alignedZ_uid57_fpCosPiTest(BITSELECT,175)@3
X18dto0_uid176_alignedZ_uid57_fpCosPiTest_in <= z_uid54_fpCosPiTest_b(18 downto 0);
X18dto0_uid176_alignedZ_uid57_fpCosPiTest_b <= X18dto0_uid176_alignedZ_uid57_fpCosPiTest_in(18 downto 0);
--ld_X18dto0_uid176_alignedZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx1_uid177_alignedZ_uid57_fpCosPiTest_b_inputreg(DELAY,573)
ld_X18dto0_uid176_alignedZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx1_uid177_alignedZ_uid57_fpCosPiTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 19, depth => 1 )
PORT MAP ( xin => X18dto0_uid176_alignedZ_uid57_fpCosPiTest_b, xout => ld_X18dto0_uid176_alignedZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx1_uid177_alignedZ_uid57_fpCosPiTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_X18dto0_uid176_alignedZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx1_uid177_alignedZ_uid57_fpCosPiTest_b(DELAY,449)@3
ld_X18dto0_uid176_alignedZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx1_uid177_alignedZ_uid57_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 19, depth => 2 )
PORT MAP ( xin => ld_X18dto0_uid176_alignedZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx1_uid177_alignedZ_uid57_fpCosPiTest_b_inputreg_q, xout => ld_X18dto0_uid176_alignedZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx1_uid177_alignedZ_uid57_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage0Idx1_uid177_alignedZ_uid57_fpCosPiTest(BITJOIN,176)@6
leftShiftStage0Idx1_uid177_alignedZ_uid57_fpCosPiTest_q <= ld_X18dto0_uid176_alignedZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx1_uid177_alignedZ_uid57_fpCosPiTest_b_q & leftShiftStage0Idx1Pad16_uid105_fxpX_uid41_fpCosPiTest_q;
--ld_z_uid54_fpCosPiTest_b_to_leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_c_inputreg(DELAY,574)
ld_z_uid54_fpCosPiTest_b_to_leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 35, depth => 1 )
PORT MAP ( xin => z_uid54_fpCosPiTest_b, xout => ld_z_uid54_fpCosPiTest_b_to_leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_z_uid54_fpCosPiTest_b_to_leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_c(DELAY,453)@3
ld_z_uid54_fpCosPiTest_b_to_leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_c : dspba_delay
GENERIC MAP ( width => 35, depth => 2 )
PORT MAP ( xin => ld_z_uid54_fpCosPiTest_b_to_leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_c_inputreg_q, xout => ld_z_uid54_fpCosPiTest_b_to_leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--rVStage_uid138_lzcZ_uid56_fpCosPiTest(BITSELECT,137)@3
rVStage_uid138_lzcZ_uid56_fpCosPiTest_in <= z_uid54_fpCosPiTest_b;
rVStage_uid138_lzcZ_uid56_fpCosPiTest_b <= rVStage_uid138_lzcZ_uid56_fpCosPiTest_in(34 downto 3);
--reg_rVStage_uid138_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid139_lzcZ_uid56_fpCosPiTest_1(REG,247)@3
reg_rVStage_uid138_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid139_lzcZ_uid56_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid138_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid139_lzcZ_uid56_fpCosPiTest_1_q <= "00000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid138_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid139_lzcZ_uid56_fpCosPiTest_1_q <= rVStage_uid138_lzcZ_uid56_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid139_lzcZ_uid56_fpCosPiTest(LOGICAL,138)@4
vCount_uid139_lzcZ_uid56_fpCosPiTest_a <= reg_rVStage_uid138_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid139_lzcZ_uid56_fpCosPiTest_1_q;
vCount_uid139_lzcZ_uid56_fpCosPiTest_b <= leftShiftStage0Idx2Pad32_uid108_fxpX_uid41_fpCosPiTest_q;
vCount_uid139_lzcZ_uid56_fpCosPiTest_q <= "1" when vCount_uid139_lzcZ_uid56_fpCosPiTest_a = vCount_uid139_lzcZ_uid56_fpCosPiTest_b else "0";
--ld_vCount_uid139_lzcZ_uid56_fpCosPiTest_q_to_r_uid172_lzcZ_uid56_fpCosPiTest_f(DELAY,447)@4
ld_vCount_uid139_lzcZ_uid56_fpCosPiTest_q_to_r_uid172_lzcZ_uid56_fpCosPiTest_f : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => vCount_uid139_lzcZ_uid56_fpCosPiTest_q, xout => ld_vCount_uid139_lzcZ_uid56_fpCosPiTest_q_to_r_uid172_lzcZ_uid56_fpCosPiTest_f_q, ena => en(0), clk => clk, aclr => areset );
--mO_uid140_lzcZ_uid56_fpCosPiTest(CONSTANT,139)
mO_uid140_lzcZ_uid56_fpCosPiTest_q <= "11111111111111111111111111111";
--cStage_uid142_lzcZ_uid56_fpCosPiTest(BITJOIN,141)@3
cStage_uid142_lzcZ_uid56_fpCosPiTest_q <= vStage_uid141_lzcZ_uid56_fpCosPiTest_b & mO_uid140_lzcZ_uid56_fpCosPiTest_q;
--reg_cStage_uid142_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid144_lzcZ_uid56_fpCosPiTest_3(REG,249)@3
reg_cStage_uid142_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid144_lzcZ_uid56_fpCosPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cStage_uid142_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid144_lzcZ_uid56_fpCosPiTest_3_q <= "00000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cStage_uid142_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid144_lzcZ_uid56_fpCosPiTest_3_q <= cStage_uid142_lzcZ_uid56_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--vStagei_uid144_lzcZ_uid56_fpCosPiTest(MUX,143)@4
vStagei_uid144_lzcZ_uid56_fpCosPiTest_s <= vCount_uid139_lzcZ_uid56_fpCosPiTest_q;
vStagei_uid144_lzcZ_uid56_fpCosPiTest: PROCESS (vStagei_uid144_lzcZ_uid56_fpCosPiTest_s, en, reg_rVStage_uid138_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid139_lzcZ_uid56_fpCosPiTest_1_q, reg_cStage_uid142_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid144_lzcZ_uid56_fpCosPiTest_3_q)
BEGIN
CASE vStagei_uid144_lzcZ_uid56_fpCosPiTest_s IS
WHEN "0" => vStagei_uid144_lzcZ_uid56_fpCosPiTest_q <= reg_rVStage_uid138_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid139_lzcZ_uid56_fpCosPiTest_1_q;
WHEN "1" => vStagei_uid144_lzcZ_uid56_fpCosPiTest_q <= reg_cStage_uid142_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid144_lzcZ_uid56_fpCosPiTest_3_q;
WHEN OTHERS => vStagei_uid144_lzcZ_uid56_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid146_lzcZ_uid56_fpCosPiTest(BITSELECT,145)@4
rVStage_uid146_lzcZ_uid56_fpCosPiTest_in <= vStagei_uid144_lzcZ_uid56_fpCosPiTest_q;
rVStage_uid146_lzcZ_uid56_fpCosPiTest_b <= rVStage_uid146_lzcZ_uid56_fpCosPiTest_in(31 downto 16);
--reg_rVStage_uid146_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid147_lzcZ_uid56_fpCosPiTest_1(REG,250)@4
reg_rVStage_uid146_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid147_lzcZ_uid56_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid146_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid147_lzcZ_uid56_fpCosPiTest_1_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid146_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid147_lzcZ_uid56_fpCosPiTest_1_q <= rVStage_uid146_lzcZ_uid56_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid147_lzcZ_uid56_fpCosPiTest(LOGICAL,146)@5
vCount_uid147_lzcZ_uid56_fpCosPiTest_a <= reg_rVStage_uid146_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid147_lzcZ_uid56_fpCosPiTest_1_q;
vCount_uid147_lzcZ_uid56_fpCosPiTest_b <= leftShiftStage0Idx1Pad16_uid105_fxpX_uid41_fpCosPiTest_q;
vCount_uid147_lzcZ_uid56_fpCosPiTest_q <= "1" when vCount_uid147_lzcZ_uid56_fpCosPiTest_a = vCount_uid147_lzcZ_uid56_fpCosPiTest_b else "0";
--ld_vCount_uid147_lzcZ_uid56_fpCosPiTest_q_to_r_uid172_lzcZ_uid56_fpCosPiTest_e(DELAY,446)@5
ld_vCount_uid147_lzcZ_uid56_fpCosPiTest_q_to_r_uid172_lzcZ_uid56_fpCosPiTest_e : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vCount_uid147_lzcZ_uid56_fpCosPiTest_q, xout => ld_vCount_uid147_lzcZ_uid56_fpCosPiTest_q_to_r_uid172_lzcZ_uid56_fpCosPiTest_e_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid148_lzcZ_uid56_fpCosPiTest(BITSELECT,147)@4
vStage_uid148_lzcZ_uid56_fpCosPiTest_in <= vStagei_uid144_lzcZ_uid56_fpCosPiTest_q(15 downto 0);
vStage_uid148_lzcZ_uid56_fpCosPiTest_b <= vStage_uid148_lzcZ_uid56_fpCosPiTest_in(15 downto 0);
--reg_vStage_uid148_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid150_lzcZ_uid56_fpCosPiTest_3(REG,252)@4
reg_vStage_uid148_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid150_lzcZ_uid56_fpCosPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid148_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid150_lzcZ_uid56_fpCosPiTest_3_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid148_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid150_lzcZ_uid56_fpCosPiTest_3_q <= vStage_uid148_lzcZ_uid56_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid150_lzcZ_uid56_fpCosPiTest(MUX,149)@5
vStagei_uid150_lzcZ_uid56_fpCosPiTest_s <= vCount_uid147_lzcZ_uid56_fpCosPiTest_q;
vStagei_uid150_lzcZ_uid56_fpCosPiTest: PROCESS (vStagei_uid150_lzcZ_uid56_fpCosPiTest_s, en, reg_rVStage_uid146_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid147_lzcZ_uid56_fpCosPiTest_1_q, reg_vStage_uid148_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid150_lzcZ_uid56_fpCosPiTest_3_q)
BEGIN
CASE vStagei_uid150_lzcZ_uid56_fpCosPiTest_s IS
WHEN "0" => vStagei_uid150_lzcZ_uid56_fpCosPiTest_q <= reg_rVStage_uid146_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid147_lzcZ_uid56_fpCosPiTest_1_q;
WHEN "1" => vStagei_uid150_lzcZ_uid56_fpCosPiTest_q <= reg_vStage_uid148_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid150_lzcZ_uid56_fpCosPiTest_3_q;
WHEN OTHERS => vStagei_uid150_lzcZ_uid56_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid152_lzcZ_uid56_fpCosPiTest(BITSELECT,151)@5
rVStage_uid152_lzcZ_uid56_fpCosPiTest_in <= vStagei_uid150_lzcZ_uid56_fpCosPiTest_q;
rVStage_uid152_lzcZ_uid56_fpCosPiTest_b <= rVStage_uid152_lzcZ_uid56_fpCosPiTest_in(15 downto 8);
--vCount_uid153_lzcZ_uid56_fpCosPiTest(LOGICAL,152)@5
vCount_uid153_lzcZ_uid56_fpCosPiTest_a <= rVStage_uid152_lzcZ_uid56_fpCosPiTest_b;
vCount_uid153_lzcZ_uid56_fpCosPiTest_b <= cstAllZWE_uid21_fpCosPiTest_q;
vCount_uid153_lzcZ_uid56_fpCosPiTest_q <= "1" when vCount_uid153_lzcZ_uid56_fpCosPiTest_a = vCount_uid153_lzcZ_uid56_fpCosPiTest_b else "0";
--reg_vCount_uid153_lzcZ_uid56_fpCosPiTest_0_to_r_uid172_lzcZ_uid56_fpCosPiTest_3(REG,256)@5
reg_vCount_uid153_lzcZ_uid56_fpCosPiTest_0_to_r_uid172_lzcZ_uid56_fpCosPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid153_lzcZ_uid56_fpCosPiTest_0_to_r_uid172_lzcZ_uid56_fpCosPiTest_3_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid153_lzcZ_uid56_fpCosPiTest_0_to_r_uid172_lzcZ_uid56_fpCosPiTest_3_q <= vCount_uid153_lzcZ_uid56_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--vStage_uid154_lzcZ_uid56_fpCosPiTest(BITSELECT,153)@5
vStage_uid154_lzcZ_uid56_fpCosPiTest_in <= vStagei_uid150_lzcZ_uid56_fpCosPiTest_q(7 downto 0);
vStage_uid154_lzcZ_uid56_fpCosPiTest_b <= vStage_uid154_lzcZ_uid56_fpCosPiTest_in(7 downto 0);
--vStagei_uid156_lzcZ_uid56_fpCosPiTest(MUX,155)@5
vStagei_uid156_lzcZ_uid56_fpCosPiTest_s <= vCount_uid153_lzcZ_uid56_fpCosPiTest_q;
vStagei_uid156_lzcZ_uid56_fpCosPiTest: PROCESS (vStagei_uid156_lzcZ_uid56_fpCosPiTest_s, en, rVStage_uid152_lzcZ_uid56_fpCosPiTest_b, vStage_uid154_lzcZ_uid56_fpCosPiTest_b)
BEGIN
CASE vStagei_uid156_lzcZ_uid56_fpCosPiTest_s IS
WHEN "0" => vStagei_uid156_lzcZ_uid56_fpCosPiTest_q <= rVStage_uid152_lzcZ_uid56_fpCosPiTest_b;
WHEN "1" => vStagei_uid156_lzcZ_uid56_fpCosPiTest_q <= vStage_uid154_lzcZ_uid56_fpCosPiTest_b;
WHEN OTHERS => vStagei_uid156_lzcZ_uid56_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid158_lzcZ_uid56_fpCosPiTest(BITSELECT,157)@5
rVStage_uid158_lzcZ_uid56_fpCosPiTest_in <= vStagei_uid156_lzcZ_uid56_fpCosPiTest_q;
rVStage_uid158_lzcZ_uid56_fpCosPiTest_b <= rVStage_uid158_lzcZ_uid56_fpCosPiTest_in(7 downto 4);
--reg_rVStage_uid158_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid159_lzcZ_uid56_fpCosPiTest_1(REG,253)@5
reg_rVStage_uid158_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid159_lzcZ_uid56_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid158_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid159_lzcZ_uid56_fpCosPiTest_1_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid158_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid159_lzcZ_uid56_fpCosPiTest_1_q <= rVStage_uid158_lzcZ_uid56_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid159_lzcZ_uid56_fpCosPiTest(LOGICAL,158)@6
vCount_uid159_lzcZ_uid56_fpCosPiTest_a <= reg_rVStage_uid158_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid159_lzcZ_uid56_fpCosPiTest_1_q;
vCount_uid159_lzcZ_uid56_fpCosPiTest_b <= leftShiftStage1Idx1Pad4_uid114_fxpX_uid41_fpCosPiTest_q;
vCount_uid159_lzcZ_uid56_fpCosPiTest_q <= "1" when vCount_uid159_lzcZ_uid56_fpCosPiTest_a = vCount_uid159_lzcZ_uid56_fpCosPiTest_b else "0";
--vStage_uid160_lzcZ_uid56_fpCosPiTest(BITSELECT,159)@5
vStage_uid160_lzcZ_uid56_fpCosPiTest_in <= vStagei_uid156_lzcZ_uid56_fpCosPiTest_q(3 downto 0);
vStage_uid160_lzcZ_uid56_fpCosPiTest_b <= vStage_uid160_lzcZ_uid56_fpCosPiTest_in(3 downto 0);
--reg_vStage_uid160_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid162_lzcZ_uid56_fpCosPiTest_3(REG,255)@5
reg_vStage_uid160_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid162_lzcZ_uid56_fpCosPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid160_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid162_lzcZ_uid56_fpCosPiTest_3_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid160_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid162_lzcZ_uid56_fpCosPiTest_3_q <= vStage_uid160_lzcZ_uid56_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid162_lzcZ_uid56_fpCosPiTest(MUX,161)@6
vStagei_uid162_lzcZ_uid56_fpCosPiTest_s <= vCount_uid159_lzcZ_uid56_fpCosPiTest_q;
vStagei_uid162_lzcZ_uid56_fpCosPiTest: PROCESS (vStagei_uid162_lzcZ_uid56_fpCosPiTest_s, en, reg_rVStage_uid158_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid159_lzcZ_uid56_fpCosPiTest_1_q, reg_vStage_uid160_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid162_lzcZ_uid56_fpCosPiTest_3_q)
BEGIN
CASE vStagei_uid162_lzcZ_uid56_fpCosPiTest_s IS
WHEN "0" => vStagei_uid162_lzcZ_uid56_fpCosPiTest_q <= reg_rVStage_uid158_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid159_lzcZ_uid56_fpCosPiTest_1_q;
WHEN "1" => vStagei_uid162_lzcZ_uid56_fpCosPiTest_q <= reg_vStage_uid160_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid162_lzcZ_uid56_fpCosPiTest_3_q;
WHEN OTHERS => vStagei_uid162_lzcZ_uid56_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid164_lzcZ_uid56_fpCosPiTest(BITSELECT,163)@6
rVStage_uid164_lzcZ_uid56_fpCosPiTest_in <= vStagei_uid162_lzcZ_uid56_fpCosPiTest_q;
rVStage_uid164_lzcZ_uid56_fpCosPiTest_b <= rVStage_uid164_lzcZ_uid56_fpCosPiTest_in(3 downto 2);
--vCount_uid165_lzcZ_uid56_fpCosPiTest(LOGICAL,164)@6
vCount_uid165_lzcZ_uid56_fpCosPiTest_a <= rVStage_uid164_lzcZ_uid56_fpCosPiTest_b;
vCount_uid165_lzcZ_uid56_fpCosPiTest_b <= leftShiftStage2Idx2Pad2_uid128_fxpX_uid41_fpCosPiTest_q;
vCount_uid165_lzcZ_uid56_fpCosPiTest_q <= "1" when vCount_uid165_lzcZ_uid56_fpCosPiTest_a = vCount_uid165_lzcZ_uid56_fpCosPiTest_b else "0";
--vStage_uid166_lzcZ_uid56_fpCosPiTest(BITSELECT,165)@6
vStage_uid166_lzcZ_uid56_fpCosPiTest_in <= vStagei_uid162_lzcZ_uid56_fpCosPiTest_q(1 downto 0);
vStage_uid166_lzcZ_uid56_fpCosPiTest_b <= vStage_uid166_lzcZ_uid56_fpCosPiTest_in(1 downto 0);
--vStagei_uid168_lzcZ_uid56_fpCosPiTest(MUX,167)@6
vStagei_uid168_lzcZ_uid56_fpCosPiTest_s <= vCount_uid165_lzcZ_uid56_fpCosPiTest_q;
vStagei_uid168_lzcZ_uid56_fpCosPiTest: PROCESS (vStagei_uid168_lzcZ_uid56_fpCosPiTest_s, en, rVStage_uid164_lzcZ_uid56_fpCosPiTest_b, vStage_uid166_lzcZ_uid56_fpCosPiTest_b)
BEGIN
CASE vStagei_uid168_lzcZ_uid56_fpCosPiTest_s IS
WHEN "0" => vStagei_uid168_lzcZ_uid56_fpCosPiTest_q <= rVStage_uid164_lzcZ_uid56_fpCosPiTest_b;
WHEN "1" => vStagei_uid168_lzcZ_uid56_fpCosPiTest_q <= vStage_uid166_lzcZ_uid56_fpCosPiTest_b;
WHEN OTHERS => vStagei_uid168_lzcZ_uid56_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid170_lzcZ_uid56_fpCosPiTest(BITSELECT,169)@6
rVStage_uid170_lzcZ_uid56_fpCosPiTest_in <= vStagei_uid168_lzcZ_uid56_fpCosPiTest_q;
rVStage_uid170_lzcZ_uid56_fpCosPiTest_b <= rVStage_uid170_lzcZ_uid56_fpCosPiTest_in(1 downto 1);
--vCount_uid171_lzcZ_uid56_fpCosPiTest(LOGICAL,170)@6
vCount_uid171_lzcZ_uid56_fpCosPiTest_a <= rVStage_uid170_lzcZ_uid56_fpCosPiTest_b;
vCount_uid171_lzcZ_uid56_fpCosPiTest_b <= GND_q;
vCount_uid171_lzcZ_uid56_fpCosPiTest_q <= "1" when vCount_uid171_lzcZ_uid56_fpCosPiTest_a = vCount_uid171_lzcZ_uid56_fpCosPiTest_b else "0";
--r_uid172_lzcZ_uid56_fpCosPiTest(BITJOIN,171)@6
r_uid172_lzcZ_uid56_fpCosPiTest_q <= ld_vCount_uid139_lzcZ_uid56_fpCosPiTest_q_to_r_uid172_lzcZ_uid56_fpCosPiTest_f_q & ld_vCount_uid147_lzcZ_uid56_fpCosPiTest_q_to_r_uid172_lzcZ_uid56_fpCosPiTest_e_q & reg_vCount_uid153_lzcZ_uid56_fpCosPiTest_0_to_r_uid172_lzcZ_uid56_fpCosPiTest_3_q & vCount_uid159_lzcZ_uid56_fpCosPiTest_q & vCount_uid165_lzcZ_uid56_fpCosPiTest_q & vCount_uid171_lzcZ_uid56_fpCosPiTest_q;
--leftShiftStageSel5Dto4_uid182_alignedZ_uid57_fpCosPiTest(BITSELECT,181)@6
leftShiftStageSel5Dto4_uid182_alignedZ_uid57_fpCosPiTest_in <= r_uid172_lzcZ_uid56_fpCosPiTest_q;
leftShiftStageSel5Dto4_uid182_alignedZ_uid57_fpCosPiTest_b <= leftShiftStageSel5Dto4_uid182_alignedZ_uid57_fpCosPiTest_in(5 downto 4);
--leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest(MUX,182)@6
leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_s <= leftShiftStageSel5Dto4_uid182_alignedZ_uid57_fpCosPiTest_b;
leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest: PROCESS (leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_s, en, ld_z_uid54_fpCosPiTest_b_to_leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_c_q, leftShiftStage0Idx1_uid177_alignedZ_uid57_fpCosPiTest_q, leftShiftStage0Idx2_uid180_alignedZ_uid57_fpCosPiTest_q, cstZwSwF_uid15_fpCosPiTest_q)
BEGIN
CASE leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_s IS
WHEN "00" => leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_q <= ld_z_uid54_fpCosPiTest_b_to_leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_c_q;
WHEN "01" => leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_q <= leftShiftStage0Idx1_uid177_alignedZ_uid57_fpCosPiTest_q;
WHEN "10" => leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_q <= leftShiftStage0Idx2_uid180_alignedZ_uid57_fpCosPiTest_q;
WHEN "11" => leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_q <= cstZwSwF_uid15_fpCosPiTest_q;
WHEN OTHERS => leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage022dto0_uid191_alignedZ_uid57_fpCosPiTest(BITSELECT,190)@6
LeftShiftStage022dto0_uid191_alignedZ_uid57_fpCosPiTest_in <= leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_q(22 downto 0);
LeftShiftStage022dto0_uid191_alignedZ_uid57_fpCosPiTest_b <= LeftShiftStage022dto0_uid191_alignedZ_uid57_fpCosPiTest_in(22 downto 0);
--leftShiftStage1Idx3_uid192_alignedZ_uid57_fpCosPiTest(BITJOIN,191)@6
leftShiftStage1Idx3_uid192_alignedZ_uid57_fpCosPiTest_q <= LeftShiftStage022dto0_uid191_alignedZ_uid57_fpCosPiTest_b & leftShiftStage1Idx3Pad12_uid120_fxpX_uid41_fpCosPiTest_q;
--reg_leftShiftStage1Idx3_uid192_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_5(REG,261)@6
reg_leftShiftStage1Idx3_uid192_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx3_uid192_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_5_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx3_uid192_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_5_q <= leftShiftStage1Idx3_uid192_alignedZ_uid57_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage026dto0_uid188_alignedZ_uid57_fpCosPiTest(BITSELECT,187)@6
LeftShiftStage026dto0_uid188_alignedZ_uid57_fpCosPiTest_in <= leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_q(26 downto 0);
LeftShiftStage026dto0_uid188_alignedZ_uid57_fpCosPiTest_b <= LeftShiftStage026dto0_uid188_alignedZ_uid57_fpCosPiTest_in(26 downto 0);
--leftShiftStage1Idx2_uid189_alignedZ_uid57_fpCosPiTest(BITJOIN,188)@6
leftShiftStage1Idx2_uid189_alignedZ_uid57_fpCosPiTest_q <= LeftShiftStage026dto0_uid188_alignedZ_uid57_fpCosPiTest_b & cstAllZWE_uid21_fpCosPiTest_q;
--reg_leftShiftStage1Idx2_uid189_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_4(REG,260)@6
reg_leftShiftStage1Idx2_uid189_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx2_uid189_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_4_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx2_uid189_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_4_q <= leftShiftStage1Idx2_uid189_alignedZ_uid57_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage030dto0_uid185_alignedZ_uid57_fpCosPiTest(BITSELECT,184)@6
LeftShiftStage030dto0_uid185_alignedZ_uid57_fpCosPiTest_in <= leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_q(30 downto 0);
LeftShiftStage030dto0_uid185_alignedZ_uid57_fpCosPiTest_b <= LeftShiftStage030dto0_uid185_alignedZ_uid57_fpCosPiTest_in(30 downto 0);
--leftShiftStage1Idx1_uid186_alignedZ_uid57_fpCosPiTest(BITJOIN,185)@6
leftShiftStage1Idx1_uid186_alignedZ_uid57_fpCosPiTest_q <= LeftShiftStage030dto0_uid185_alignedZ_uid57_fpCosPiTest_b & leftShiftStage1Idx1Pad4_uid114_fxpX_uid41_fpCosPiTest_q;
--reg_leftShiftStage1Idx1_uid186_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_3(REG,259)@6
reg_leftShiftStage1Idx1_uid186_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx1_uid186_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_3_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx1_uid186_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_3_q <= leftShiftStage1Idx1_uid186_alignedZ_uid57_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--reg_leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_2(REG,258)@6
reg_leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_2_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_2_q <= leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel3Dto2_uid193_alignedZ_uid57_fpCosPiTest(BITSELECT,192)@6
leftShiftStageSel3Dto2_uid193_alignedZ_uid57_fpCosPiTest_in <= r_uid172_lzcZ_uid56_fpCosPiTest_q(3 downto 0);
leftShiftStageSel3Dto2_uid193_alignedZ_uid57_fpCosPiTest_b <= leftShiftStageSel3Dto2_uid193_alignedZ_uid57_fpCosPiTest_in(3 downto 2);
--reg_leftShiftStageSel3Dto2_uid193_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_1(REG,257)@6
reg_leftShiftStageSel3Dto2_uid193_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel3Dto2_uid193_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel3Dto2_uid193_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_1_q <= leftShiftStageSel3Dto2_uid193_alignedZ_uid57_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest(MUX,193)@7
leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_s <= reg_leftShiftStageSel3Dto2_uid193_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_1_q;
leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest: PROCESS (leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_s, en, reg_leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_2_q, reg_leftShiftStage1Idx1_uid186_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_3_q, reg_leftShiftStage1Idx2_uid189_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_4_q, reg_leftShiftStage1Idx3_uid192_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_5_q)
BEGIN
CASE leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_s IS
WHEN "00" => leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_q <= reg_leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_2_q;
WHEN "01" => leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_q <= reg_leftShiftStage1Idx1_uid186_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_3_q;
WHEN "10" => leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_q <= reg_leftShiftStage1Idx2_uid189_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_4_q;
WHEN "11" => leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_q <= reg_leftShiftStage1Idx3_uid192_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_5_q;
WHEN OTHERS => leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--leftShiftStageSel1Dto0_uid204_alignedZ_uid57_fpCosPiTest(BITSELECT,203)@6
leftShiftStageSel1Dto0_uid204_alignedZ_uid57_fpCosPiTest_in <= r_uid172_lzcZ_uid56_fpCosPiTest_q(1 downto 0);
leftShiftStageSel1Dto0_uid204_alignedZ_uid57_fpCosPiTest_b <= leftShiftStageSel1Dto0_uid204_alignedZ_uid57_fpCosPiTest_in(1 downto 0);
--reg_leftShiftStageSel1Dto0_uid204_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest_1(REG,262)@6
reg_leftShiftStageSel1Dto0_uid204_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel1Dto0_uid204_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel1Dto0_uid204_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest_1_q <= leftShiftStageSel1Dto0_uid204_alignedZ_uid57_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest(MUX,204)@7
leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest_s <= reg_leftShiftStageSel1Dto0_uid204_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest_1_q;
leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest: PROCESS (leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest_s, en, leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_q, leftShiftStage2Idx1_uid197_alignedZ_uid57_fpCosPiTest_q, leftShiftStage2Idx2_uid200_alignedZ_uid57_fpCosPiTest_q, leftShiftStage2Idx3_uid203_alignedZ_uid57_fpCosPiTest_q)
BEGIN
CASE leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest_s IS
WHEN "00" => leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest_q <= leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_q;
WHEN "01" => leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest_q <= leftShiftStage2Idx1_uid197_alignedZ_uid57_fpCosPiTest_q;
WHEN "10" => leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest_q <= leftShiftStage2Idx2_uid200_alignedZ_uid57_fpCosPiTest_q;
WHEN "11" => leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest_q <= leftShiftStage2Idx3_uid203_alignedZ_uid57_fpCosPiTest_q;
WHEN OTHERS => leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--alignedZLow_uid58_fpCosPiTest(BITSELECT,57)@7
alignedZLow_uid58_fpCosPiTest_in <= leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest_q;
alignedZLow_uid58_fpCosPiTest_b <= alignedZLow_uid58_fpCosPiTest_in(34 downto 11);
--ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_inputreg(DELAY,612)
ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 24, depth => 1 )
PORT MAP ( xin => alignedZLow_uid58_fpCosPiTest_b, xout => ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem(DUALMEM,613)
ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_reset0 <= areset;
ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_ia <= ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_inputreg_q;
ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_aa <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdreg_q;
ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_ab <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdmux_q;
ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 24,
widthad_a => 2,
numwords_a => 3,
width_b => 24,
widthad_b => 2,
numwords_b => 3,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_iq,
address_a => ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_aa,
data_a => ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_ia
);
ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_q <= ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_iq(23 downto 0);
--reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0(REG,269)@12
reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_q <= ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest(MULT,222)@13
prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_pr <= UNSIGNED(prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_a) * UNSIGNED(prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_b);
prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_a <= (others => '0');
prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_b <= (others => '0');
prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_a <= reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_q;
prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_b <= reg_fxpSinRes_uid65_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_1_q;
prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_s1 <= STD_LOGIC_VECTOR(prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_pr);
END IF;
END IF;
END PROCESS;
prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_q <= prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid224_mul2xSinRes_uid66_fpCosPiTest(BITSELECT,223)@16
prodXYTruncFR_uid224_mul2xSinRes_uid66_fpCosPiTest_in <= prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_q;
prodXYTruncFR_uid224_mul2xSinRes_uid66_fpCosPiTest_b <= prodXYTruncFR_uid224_mul2xSinRes_uid66_fpCosPiTest_in(48 downto 23);
--normBit_uid67_fpCosPiTest(BITSELECT,66)@16
normBit_uid67_fpCosPiTest_in <= prodXYTruncFR_uid224_mul2xSinRes_uid66_fpCosPiTest_b;
normBit_uid67_fpCosPiTest_b <= normBit_uid67_fpCosPiTest_in(25 downto 25);
--cstAllZWF_uid9_fpCosPiTest(CONSTANT,8)
cstAllZWF_uid9_fpCosPiTest_q <= "00000000000000000000000";
--rndExpUpdate_uid72_uid73_fpCosPiTest(BITJOIN,72)@16
rndExpUpdate_uid72_uid73_fpCosPiTest_q <= normBit_uid67_fpCosPiTest_b & cstAllZWF_uid9_fpCosPiTest_q & VCC_q;
--ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_nor(LOGICAL,558)
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_nor_a <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_notEnable_q;
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_nor_b <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_sticky_ena_q;
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_nor_q <= not (ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_nor_a or ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_nor_b);
--ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_sticky_ena(REG,559)
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_nor_q = "1") THEN
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_sticky_ena_q <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_enaAnd(LOGICAL,560)
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_enaAnd_a <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_sticky_ena_q;
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_enaAnd_b <= en;
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_enaAnd_q <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_enaAnd_a and ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_enaAnd_b;
--reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1(REG,271)@6
reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q <= r_uid172_lzcZ_uid56_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem(DUALMEM,549)
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_reset0 <= areset;
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_ia <= reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q;
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_aa <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdreg_q;
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_ab <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdmux_q;
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 6,
widthad_a => 3,
numwords_a => 7,
width_b => 6,
widthad_b => 3,
numwords_b => 7,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_iq,
address_a => ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_aa,
data_a => ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_ia
);
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_q <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_iq(5 downto 0);
--cstBiasM1_uid11_fpCosPiTest(CONSTANT,10)
cstBiasM1_uid11_fpCosPiTest_q <= "01111110";
--expHardCase_uid59_fpCosPiTest(SUB,58)@15
expHardCase_uid59_fpCosPiTest_a <= STD_LOGIC_VECTOR("0" & cstBiasM1_uid11_fpCosPiTest_q);
expHardCase_uid59_fpCosPiTest_b <= STD_LOGIC_VECTOR("000" & ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_q);
expHardCase_uid59_fpCosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expHardCase_uid59_fpCosPiTest_a) - UNSIGNED(expHardCase_uid59_fpCosPiTest_b));
expHardCase_uid59_fpCosPiTest_q <= expHardCase_uid59_fpCosPiTest_o(8 downto 0);
--expP_uid60_fpCosPiTest(BITSELECT,59)@15
expP_uid60_fpCosPiTest_in <= expHardCase_uid59_fpCosPiTest_q(7 downto 0);
expP_uid60_fpCosPiTest_b <= expP_uid60_fpCosPiTest_in(7 downto 0);
--reg_expP_uid60_fpCosPiTest_0_to_expFracPreRnd_uid71_uid71_fpCosPiTest_1(REG,272)@15
reg_expP_uid60_fpCosPiTest_0_to_expFracPreRnd_uid71_uid71_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expP_uid60_fpCosPiTest_0_to_expFracPreRnd_uid71_uid71_fpCosPiTest_1_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expP_uid60_fpCosPiTest_0_to_expFracPreRnd_uid71_uid71_fpCosPiTest_1_q <= expP_uid60_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--highRes_uid68_fpCosPiTest(BITSELECT,67)@16
highRes_uid68_fpCosPiTest_in <= prodXYTruncFR_uid224_mul2xSinRes_uid66_fpCosPiTest_b(24 downto 0);
highRes_uid68_fpCosPiTest_b <= highRes_uid68_fpCosPiTest_in(24 downto 1);
--lowRes_uid69_fpCosPiTest(BITSELECT,68)@16
lowRes_uid69_fpCosPiTest_in <= prodXYTruncFR_uid224_mul2xSinRes_uid66_fpCosPiTest_b(23 downto 0);
lowRes_uid69_fpCosPiTest_b <= lowRes_uid69_fpCosPiTest_in(23 downto 0);
--fracRCompPreRnd_uid70_fpCosPiTest(MUX,69)@16
fracRCompPreRnd_uid70_fpCosPiTest_s <= normBit_uid67_fpCosPiTest_b;
fracRCompPreRnd_uid70_fpCosPiTest: PROCESS (fracRCompPreRnd_uid70_fpCosPiTest_s, en, lowRes_uid69_fpCosPiTest_b, highRes_uid68_fpCosPiTest_b)
BEGIN
CASE fracRCompPreRnd_uid70_fpCosPiTest_s IS
WHEN "0" => fracRCompPreRnd_uid70_fpCosPiTest_q <= lowRes_uid69_fpCosPiTest_b;
WHEN "1" => fracRCompPreRnd_uid70_fpCosPiTest_q <= highRes_uid68_fpCosPiTest_b;
WHEN OTHERS => fracRCompPreRnd_uid70_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--expFracPreRnd_uid71_uid71_fpCosPiTest(BITJOIN,70)@16
expFracPreRnd_uid71_uid71_fpCosPiTest_q <= reg_expP_uid60_fpCosPiTest_0_to_expFracPreRnd_uid71_uid71_fpCosPiTest_1_q & fracRCompPreRnd_uid70_fpCosPiTest_q;
--expFracComp_uid74_fpCosPiTest(ADD,73)@16
expFracComp_uid74_fpCosPiTest_a <= STD_LOGIC_VECTOR("0" & expFracPreRnd_uid71_uid71_fpCosPiTest_q);
expFracComp_uid74_fpCosPiTest_b <= STD_LOGIC_VECTOR("00000000" & rndExpUpdate_uid72_uid73_fpCosPiTest_q);
expFracComp_uid74_fpCosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expFracComp_uid74_fpCosPiTest_a) + UNSIGNED(expFracComp_uid74_fpCosPiTest_b));
expFracComp_uid74_fpCosPiTest_q <= expFracComp_uid74_fpCosPiTest_o(32 downto 0);
--expRComp_uid76_fpCosPiTest(BITSELECT,75)@16
expRComp_uid76_fpCosPiTest_in <= expFracComp_uid74_fpCosPiTest_q(31 downto 0);
expRComp_uid76_fpCosPiTest_b <= expRComp_uid76_fpCosPiTest_in(31 downto 24);
--fracXIsZero_uid27_fpCosPiTest(LOGICAL,26)@0
fracXIsZero_uid27_fpCosPiTest_a <= fracX_uid7_fpCosPiTest_b;
fracXIsZero_uid27_fpCosPiTest_b <= cstAllZWF_uid9_fpCosPiTest_q;
fracXIsZero_uid27_fpCosPiTest_q <= "1" when fracXIsZero_uid27_fpCosPiTest_a = fracXIsZero_uid27_fpCosPiTest_b else "0";
--InvFracXIsZero_uid29_fpCosPiTest(LOGICAL,28)@0
InvFracXIsZero_uid29_fpCosPiTest_a <= fracXIsZero_uid27_fpCosPiTest_q;
InvFracXIsZero_uid29_fpCosPiTest_q <= not InvFracXIsZero_uid29_fpCosPiTest_a;
--expXIsMax_uid25_fpCosPiTest(LOGICAL,24)@0
expXIsMax_uid25_fpCosPiTest_a <= expX_uid6_fpCosPiTest_b;
expXIsMax_uid25_fpCosPiTest_b <= cstAllOWE_uid8_fpCosPiTest_q;
expXIsMax_uid25_fpCosPiTest_q <= "1" when expXIsMax_uid25_fpCosPiTest_a = expXIsMax_uid25_fpCosPiTest_b else "0";
--exc_N_uid30_fpCosPiTest(LOGICAL,29)@0
exc_N_uid30_fpCosPiTest_a <= expXIsMax_uid25_fpCosPiTest_q;
exc_N_uid30_fpCosPiTest_b <= InvFracXIsZero_uid29_fpCosPiTest_q;
exc_N_uid30_fpCosPiTest_q <= exc_N_uid30_fpCosPiTest_a and exc_N_uid30_fpCosPiTest_b;
--InvExc_N_uid31_fpCosPiTest(LOGICAL,30)@0
InvExc_N_uid31_fpCosPiTest_a <= exc_N_uid30_fpCosPiTest_q;
InvExc_N_uid31_fpCosPiTest_q <= not InvExc_N_uid31_fpCosPiTest_a;
--exc_I_uid28_fpCosPiTest(LOGICAL,27)@0
exc_I_uid28_fpCosPiTest_a <= expXIsMax_uid25_fpCosPiTest_q;
exc_I_uid28_fpCosPiTest_b <= fracXIsZero_uid27_fpCosPiTest_q;
exc_I_uid28_fpCosPiTest_q <= exc_I_uid28_fpCosPiTest_a and exc_I_uid28_fpCosPiTest_b;
--InvExc_I_uid32_fpCosPiTest(LOGICAL,31)@0
InvExc_I_uid32_fpCosPiTest_a <= exc_I_uid28_fpCosPiTest_q;
InvExc_I_uid32_fpCosPiTest_q <= not InvExc_I_uid32_fpCosPiTest_a;
--expXIsZero_uid23_fpCosPiTest(LOGICAL,22)@0
expXIsZero_uid23_fpCosPiTest_a <= expX_uid6_fpCosPiTest_b;
expXIsZero_uid23_fpCosPiTest_b <= cstAllZWE_uid21_fpCosPiTest_q;
expXIsZero_uid23_fpCosPiTest_q <= "1" when expXIsZero_uid23_fpCosPiTest_a = expXIsZero_uid23_fpCosPiTest_b else "0";
--InvExpXIsZero_uid33_fpCosPiTest(LOGICAL,32)@0
InvExpXIsZero_uid33_fpCosPiTest_a <= expXIsZero_uid23_fpCosPiTest_q;
InvExpXIsZero_uid33_fpCosPiTest_q <= not InvExpXIsZero_uid33_fpCosPiTest_a;
--exc_R_uid34_fpCosPiTest(LOGICAL,33)@0
exc_R_uid34_fpCosPiTest_a <= InvExpXIsZero_uid33_fpCosPiTest_q;
exc_R_uid34_fpCosPiTest_b <= InvExc_I_uid32_fpCosPiTest_q;
exc_R_uid34_fpCosPiTest_c <= InvExc_N_uid31_fpCosPiTest_q;
exc_R_uid34_fpCosPiTest_q <= exc_R_uid34_fpCosPiTest_a and exc_R_uid34_fpCosPiTest_b and exc_R_uid34_fpCosPiTest_c;
--ld_exc_R_uid34_fpCosPiTest_q_to_xIsInt_uid80_fpCosPiTest_a(DELAY,337)@0
ld_exc_R_uid34_fpCosPiTest_q_to_xIsInt_uid80_fpCosPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => exc_R_uid34_fpCosPiTest_q, xout => ld_exc_R_uid34_fpCosPiTest_q_to_xIsInt_uid80_fpCosPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--xIsHalf_uid83_fpCosPiTest(LOGICAL,82)@2
xIsHalf_uid83_fpCosPiTest_a <= ld_exc_R_uid34_fpCosPiTest_q_to_xIsInt_uid80_fpCosPiTest_a_q;
xIsHalf_uid83_fpCosPiTest_b <= fxpXFracHalf_uid46_fpCosPiTest_q;
xIsHalf_uid83_fpCosPiTest_c <= InvCosXIsOne_uid77_fpCosPiTest_q;
xIsHalf_uid83_fpCosPiTest_d <= InvXEvenInt_uid81_fpCosPiTest_q;
xIsHalf_uid83_fpCosPiTest_q <= xIsHalf_uid83_fpCosPiTest_a and xIsHalf_uid83_fpCosPiTest_b and xIsHalf_uid83_fpCosPiTest_c and xIsHalf_uid83_fpCosPiTest_d;
--ld_xIsHalf_uid83_fpCosPiTest_q_to_expRPostExc1_uid91_fpCosPiTest_b(DELAY,355)@2
ld_xIsHalf_uid83_fpCosPiTest_q_to_expRPostExc1_uid91_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 14 )
PORT MAP ( xin => xIsHalf_uid83_fpCosPiTest_q, xout => ld_xIsHalf_uid83_fpCosPiTest_q_to_expRPostExc1_uid91_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--expRPostExc1_uid91_fpCosPiTest(MUX,90)@16
expRPostExc1_uid91_fpCosPiTest_s <= ld_xIsHalf_uid83_fpCosPiTest_q_to_expRPostExc1_uid91_fpCosPiTest_b_q;
expRPostExc1_uid91_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expRPostExc1_uid91_fpCosPiTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE expRPostExc1_uid91_fpCosPiTest_s IS
WHEN "0" => expRPostExc1_uid91_fpCosPiTest_q <= expRComp_uid76_fpCosPiTest_b;
WHEN "1" => expRPostExc1_uid91_fpCosPiTest_q <= cstAllZWE_uid21_fpCosPiTest_q;
WHEN OTHERS => expRPostExc1_uid91_fpCosPiTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_nor(LOGICAL,570)
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_nor_a <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_notEnable_q;
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_nor_b <= ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_sticky_ena_q;
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_nor_q <= not (ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_nor_a or ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_nor_b);
--ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_mem_top(CONSTANT,566)
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_mem_top_q <= "01100";
--ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_cmp(LOGICAL,567)
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_cmp_a <= ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_mem_top_q;
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdmux_q);
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_cmp_q <= "1" when ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_cmp_a = ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_cmp_b else "0";
--ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_cmpReg(REG,568)
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_cmpReg_q <= ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_sticky_ena(REG,571)
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_nor_q = "1") THEN
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_sticky_ena_q <= ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_enaAnd(LOGICAL,572)
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_enaAnd_a <= ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_sticky_ena_q;
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_enaAnd_b <= en;
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_enaAnd_q <= ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_enaAnd_a and ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_enaAnd_b;
--ld_expXIsZero_uid23_fpCosPiTest_q_to_xIntOrXZOrCosOne_uid93_fpCosPiTest_b(DELAY,359)@0
ld_expXIsZero_uid23_fpCosPiTest_q_to_xIntOrXZOrCosOne_uid93_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => expXIsZero_uid23_fpCosPiTest_q, xout => ld_expXIsZero_uid23_fpCosPiTest_q_to_xIntOrXZOrCosOne_uid93_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--fxpXFracZero_uid45_fpCosPiTest(LOGICAL,44)@2
fxpXFracZero_uid45_fpCosPiTest_a <= reg_fxpXFrac_uid43_fpCosPiTest_0_to_fxpXFracZero_uid45_fpCosPiTest_1_q;
fxpXFracZero_uid45_fpCosPiTest_b <= STD_LOGIC_VECTOR("0" & cstZwSwF_uid15_fpCosPiTest_q);
fxpXFracZero_uid45_fpCosPiTest_q <= "1" when fxpXFracZero_uid45_fpCosPiTest_a = fxpXFracZero_uid45_fpCosPiTest_b else "0";
--fracZCosNotOne_uid78_fpCosPiTest(LOGICAL,77)@2
fracZCosNotOne_uid78_fpCosPiTest_a <= fxpXFracZero_uid45_fpCosPiTest_q;
fracZCosNotOne_uid78_fpCosPiTest_b <= InvCosXIsOne_uid77_fpCosPiTest_q;
fracZCosNotOne_uid78_fpCosPiTest_q <= fracZCosNotOne_uid78_fpCosPiTest_a and fracZCosNotOne_uid78_fpCosPiTest_b;
--evenIntCosNotOneFZ_uid79_fpCosPiTest(LOGICAL,78)@2
evenIntCosNotOneFZ_uid79_fpCosPiTest_a <= ld_xEvenInt_uid35_fpCosPiTest_c_to_evenIntCosNotOneFZ_uid79_fpCosPiTest_a_q;
evenIntCosNotOneFZ_uid79_fpCosPiTest_b <= fracZCosNotOne_uid78_fpCosPiTest_q;
evenIntCosNotOneFZ_uid79_fpCosPiTest_q <= evenIntCosNotOneFZ_uid79_fpCosPiTest_a or evenIntCosNotOneFZ_uid79_fpCosPiTest_b;
--xIsInt_uid80_fpCosPiTest(LOGICAL,79)@2
xIsInt_uid80_fpCosPiTest_a <= ld_exc_R_uid34_fpCosPiTest_q_to_xIsInt_uid80_fpCosPiTest_a_q;
xIsInt_uid80_fpCosPiTest_b <= evenIntCosNotOneFZ_uid79_fpCosPiTest_q;
xIsInt_uid80_fpCosPiTest_q <= xIsInt_uid80_fpCosPiTest_a and xIsInt_uid80_fpCosPiTest_b;
--xIntOrXZOrCosOne_uid93_fpCosPiTest(LOGICAL,92)@2
xIntOrXZOrCosOne_uid93_fpCosPiTest_a <= xIsInt_uid80_fpCosPiTest_q;
xIntOrXZOrCosOne_uid93_fpCosPiTest_b <= ld_expXIsZero_uid23_fpCosPiTest_q_to_xIntOrXZOrCosOne_uid93_fpCosPiTest_b_q;
xIntOrXZOrCosOne_uid93_fpCosPiTest_c <= ld_cosXIsOne_uid36_fpCosPiTest_c_to_InvCosXIsOne_uid77_fpCosPiTest_a_q;
xIntOrXZOrCosOne_uid93_fpCosPiTest_q <= xIntOrXZOrCosOne_uid93_fpCosPiTest_a or xIntOrXZOrCosOne_uid93_fpCosPiTest_b or xIntOrXZOrCosOne_uid93_fpCosPiTest_c;
--excRNaN_uid84_fpCosPiTest(LOGICAL,83)@0
excRNaN_uid84_fpCosPiTest_a <= exc_N_uid30_fpCosPiTest_q;
excRNaN_uid84_fpCosPiTest_b <= exc_I_uid28_fpCosPiTest_q;
excRNaN_uid84_fpCosPiTest_q <= excRNaN_uid84_fpCosPiTest_a or excRNaN_uid84_fpCosPiTest_b;
--rInfOrNaN_uid92_fpCosPiTest(LOGICAL,91)@0
rInfOrNaN_uid92_fpCosPiTest_a <= GND_q;
rInfOrNaN_uid92_fpCosPiTest_b <= excRNaN_uid84_fpCosPiTest_q;
rInfOrNaN_uid92_fpCosPiTest_q <= rInfOrNaN_uid92_fpCosPiTest_a or rInfOrNaN_uid92_fpCosPiTest_b;
--ld_rInfOrNaN_uid92_fpCosPiTest_q_to_join_uid94_fpCosPiTest_a(DELAY,361)@0
ld_rInfOrNaN_uid92_fpCosPiTest_q_to_join_uid94_fpCosPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => rInfOrNaN_uid92_fpCosPiTest_q, xout => ld_rInfOrNaN_uid92_fpCosPiTest_q_to_join_uid94_fpCosPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--join_uid94_fpCosPiTest(BITJOIN,93)@2
join_uid94_fpCosPiTest_q <= xIntOrXZOrCosOne_uid93_fpCosPiTest_q & ld_rInfOrNaN_uid92_fpCosPiTest_q_to_join_uid94_fpCosPiTest_a_q;
--reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1(REG,274)@2
reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q <= join_uid94_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt(COUNTER,562)
-- every=1, low=0, high=12, step=1, init=1
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt_i = 11 THEN
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt_eq <= '1';
ELSE
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt_eq = '1') THEN
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt_i <= ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt_i - 12;
ELSE
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt_i <= ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt_i,4));
--ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdreg(REG,563)
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdreg_q <= ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdmux(MUX,564)
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdmux_s <= en;
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdmux: PROCESS (ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdmux_s, ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdreg_q, ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt_q)
BEGIN
CASE ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdmux_s IS
WHEN "0" => ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdmux_q <= ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdreg_q;
WHEN "1" => ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdmux_q <= ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem(DUALMEM,561)
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_reset0 <= areset;
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_ia <= reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q;
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_aa <= ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdreg_q;
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_ab <= ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdmux_q;
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 2,
widthad_a => 4,
numwords_a => 13,
width_b => 2,
widthad_b => 4,
numwords_b => 13,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_iq,
address_a => ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_aa,
data_a => ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_ia
);
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_q <= ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_iq(1 downto 0);
--expRPostExc_uid95_fpCosPiTest(MUX,94)@17
expRPostExc_uid95_fpCosPiTest_s <= ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_q;
expRPostExc_uid95_fpCosPiTest: PROCESS (expRPostExc_uid95_fpCosPiTest_s, en, expRPostExc1_uid91_fpCosPiTest_q, cstAllOWE_uid8_fpCosPiTest_q, cstBias_uid10_fpCosPiTest_q, cstBias_uid10_fpCosPiTest_q)
BEGIN
CASE expRPostExc_uid95_fpCosPiTest_s IS
WHEN "00" => expRPostExc_uid95_fpCosPiTest_q <= expRPostExc1_uid91_fpCosPiTest_q;
WHEN "01" => expRPostExc_uid95_fpCosPiTest_q <= cstAllOWE_uid8_fpCosPiTest_q;
WHEN "10" => expRPostExc_uid95_fpCosPiTest_q <= cstBias_uid10_fpCosPiTest_q;
WHEN "11" => expRPostExc_uid95_fpCosPiTest_q <= cstBias_uid10_fpCosPiTest_q;
WHEN OTHERS => expRPostExc_uid95_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--oneFracRPostExc2_uid87_fpCosPiTest(CONSTANT,86)
oneFracRPostExc2_uid87_fpCosPiTest_q <= "00000000000000000000001";
--fracRComp_uid75_fpCosPiTest(BITSELECT,74)@16
fracRComp_uid75_fpCosPiTest_in <= expFracComp_uid74_fpCosPiTest_q(23 downto 0);
fracRComp_uid75_fpCosPiTest_b <= fracRComp_uid75_fpCosPiTest_in(23 downto 1);
--reg_xIsHalf_uid83_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_5(REG,243)@2
reg_xIsHalf_uid83_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xIsHalf_uid83_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_5_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xIsHalf_uid83_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_5_q <= xIsHalf_uid83_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--reg_expXIsZero_uid23_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_4(REG,242)@2
reg_expXIsZero_uid23_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expXIsZero_uid23_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_4_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expXIsZero_uid23_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_4_q <= ld_expXIsZero_uid23_fpCosPiTest_q_to_xIntOrXZOrCosOne_uid93_fpCosPiTest_b_q;
END IF;
END IF;
END PROCESS;
--reg_fxpXFracHalf_uid46_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_3(REG,241)@2
reg_fxpXFracHalf_uid46_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fxpXFracHalf_uid46_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_3_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fxpXFracHalf_uid46_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_3_q <= fxpXFracHalf_uid46_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--reg_xIsInt_uid80_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_2(REG,240)@2
reg_xIsInt_uid80_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xIsInt_uid80_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xIsInt_uid80_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_2_q <= xIsInt_uid80_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--reg_cosXIsOne_uid36_fpCosPiTest_1_to_bigCond_uid85_fpCosPiTest_1(REG,239)@0
reg_cosXIsOne_uid36_fpCosPiTest_1_to_bigCond_uid85_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cosXIsOne_uid36_fpCosPiTest_1_to_bigCond_uid85_fpCosPiTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cosXIsOne_uid36_fpCosPiTest_1_to_bigCond_uid85_fpCosPiTest_1_q <= cosXIsOne_uid36_fpCosPiTest_c;
END IF;
END IF;
END PROCESS;
--ld_reg_cosXIsOne_uid36_fpCosPiTest_1_to_bigCond_uid85_fpCosPiTest_1_q_to_bigCond_uid85_fpCosPiTest_a(DELAY,346)@1
ld_reg_cosXIsOne_uid36_fpCosPiTest_1_to_bigCond_uid85_fpCosPiTest_1_q_to_bigCond_uid85_fpCosPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => reg_cosXIsOne_uid36_fpCosPiTest_1_to_bigCond_uid85_fpCosPiTest_1_q, xout => ld_reg_cosXIsOne_uid36_fpCosPiTest_1_to_bigCond_uid85_fpCosPiTest_1_q_to_bigCond_uid85_fpCosPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--bigCond_uid85_fpCosPiTest(LOGICAL,84)@3
bigCond_uid85_fpCosPiTest_a <= ld_reg_cosXIsOne_uid36_fpCosPiTest_1_to_bigCond_uid85_fpCosPiTest_1_q_to_bigCond_uid85_fpCosPiTest_a_q;
bigCond_uid85_fpCosPiTest_b <= reg_xIsInt_uid80_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_2_q;
bigCond_uid85_fpCosPiTest_c <= reg_fxpXFracHalf_uid46_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_3_q;
bigCond_uid85_fpCosPiTest_d <= reg_expXIsZero_uid23_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_4_q;
bigCond_uid85_fpCosPiTest_f <= reg_xIsHalf_uid83_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_5_q;
bigCond_uid85_fpCosPiTest_g <= GND_q;
bigCond_uid85_fpCosPiTest_q <= bigCond_uid85_fpCosPiTest_a or bigCond_uid85_fpCosPiTest_b or bigCond_uid85_fpCosPiTest_c or bigCond_uid85_fpCosPiTest_d or bigCond_uid85_fpCosPiTest_f or bigCond_uid85_fpCosPiTest_g;
--ld_bigCond_uid85_fpCosPiTest_q_to_fracRPostExc1_uid86_fpCosPiTest_b(DELAY,351)@3
ld_bigCond_uid85_fpCosPiTest_q_to_fracRPostExc1_uid86_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 13 )
PORT MAP ( xin => bigCond_uid85_fpCosPiTest_q, xout => ld_bigCond_uid85_fpCosPiTest_q_to_fracRPostExc1_uid86_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--fracRPostExc1_uid86_fpCosPiTest(MUX,85)@16
fracRPostExc1_uid86_fpCosPiTest_s <= ld_bigCond_uid85_fpCosPiTest_q_to_fracRPostExc1_uid86_fpCosPiTest_b_q;
fracRPostExc1_uid86_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
fracRPostExc1_uid86_fpCosPiTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE fracRPostExc1_uid86_fpCosPiTest_s IS
WHEN "0" => fracRPostExc1_uid86_fpCosPiTest_q <= fracRComp_uid75_fpCosPiTest_b;
WHEN "1" => fracRPostExc1_uid86_fpCosPiTest_q <= cstAllZWF_uid9_fpCosPiTest_q;
WHEN OTHERS => fracRPostExc1_uid86_fpCosPiTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--reg_excRNaN_uid84_fpCosPiTest_0_to_fracRPostExc_uid88_fpCosPiTest_1(REG,273)@0
reg_excRNaN_uid84_fpCosPiTest_0_to_fracRPostExc_uid88_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_excRNaN_uid84_fpCosPiTest_0_to_fracRPostExc_uid88_fpCosPiTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_excRNaN_uid84_fpCosPiTest_0_to_fracRPostExc_uid88_fpCosPiTest_1_q <= excRNaN_uid84_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_excRNaN_uid84_fpCosPiTest_0_to_fracRPostExc_uid88_fpCosPiTest_1_q_to_fracRPostExc_uid88_fpCosPiTest_b(DELAY,353)@1
ld_reg_excRNaN_uid84_fpCosPiTest_0_to_fracRPostExc_uid88_fpCosPiTest_1_q_to_fracRPostExc_uid88_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 16 )
PORT MAP ( xin => reg_excRNaN_uid84_fpCosPiTest_0_to_fracRPostExc_uid88_fpCosPiTest_1_q, xout => ld_reg_excRNaN_uid84_fpCosPiTest_0_to_fracRPostExc_uid88_fpCosPiTest_1_q_to_fracRPostExc_uid88_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--fracRPostExc_uid88_fpCosPiTest(MUX,87)@17
fracRPostExc_uid88_fpCosPiTest_s <= ld_reg_excRNaN_uid84_fpCosPiTest_0_to_fracRPostExc_uid88_fpCosPiTest_1_q_to_fracRPostExc_uid88_fpCosPiTest_b_q;
fracRPostExc_uid88_fpCosPiTest: PROCESS (fracRPostExc_uid88_fpCosPiTest_s, en, fracRPostExc1_uid86_fpCosPiTest_q, oneFracRPostExc2_uid87_fpCosPiTest_q)
BEGIN
CASE fracRPostExc_uid88_fpCosPiTest_s IS
WHEN "0" => fracRPostExc_uid88_fpCosPiTest_q <= fracRPostExc1_uid86_fpCosPiTest_q;
WHEN "1" => fracRPostExc_uid88_fpCosPiTest_q <= oneFracRPostExc2_uid87_fpCosPiTest_q;
WHEN OTHERS => fracRPostExc_uid88_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--R_uid102_fpCosPiTest(BITJOIN,101)@17
R_uid102_fpCosPiTest_q <= ld_signR_uid101_fpCosPiTest_q_to_R_uid102_fpCosPiTest_c_q & expRPostExc_uid95_fpCosPiTest_q & fracRPostExc_uid88_fpCosPiTest_q;
--xOut(GPOUT,4)@17
q <= R_uid102_fpCosPiTest_q;
end normal;
|
-----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Release Version 13.1
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing device programming or simulation files), and
-- any associated documentation or information are expressly subject to the
-- terms and conditions of the Altera Program License Subscription Agreement,
-- Altera MegaCore Function License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for the sole
-- purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
-----------------------------------------------------------------------------
-- VHDL created from fp_cospi_s5
-- VHDL created on Wed Feb 27 15:22:33 2013
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.all;
use std.TextIO.all;
use work.dspba_library_package.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
entity fp_cospi_s5 is
port (
a : in std_logic_vector(31 downto 0);
en : in std_logic_vector(0 downto 0);
q : out std_logic_vector(31 downto 0);
clk : in std_logic;
areset : in std_logic
);
end;
architecture normal of fp_cospi_s5 is
attribute altera_attribute : string;
attribute altera_attribute of normal : architecture is "-name NOT_GATE_PUSH_BACK OFF; -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON; -name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410";
signal GND_q : std_logic_vector (0 downto 0);
signal VCC_q : std_logic_vector (0 downto 0);
signal cstAllOWE_uid8_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal cstAllZWF_uid9_fpCosPiTest_q : std_logic_vector (22 downto 0);
signal cstBias_uid10_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal cstBiasM1_uid11_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal cstBiasPwF_uid12_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal biasMwShiftMO_uid13_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal cst01pWShift_uid14_fpCosPiTest_q : std_logic_vector (12 downto 0);
signal cstZwSwF_uid15_fpCosPiTest_q : std_logic_vector (34 downto 0);
signal cstAllZWE_uid21_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal rangeReducedFxPX_uid51_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal rangeReducedFxPX_uid51_fpCosPiTest_q : std_logic_vector (35 downto 0);
signal fracRPostExc1_uid86_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal fracRPostExc1_uid86_fpCosPiTest_q : std_logic_vector (22 downto 0);
signal oneFracRPostExc2_uid87_fpCosPiTest_q : std_logic_vector (22 downto 0);
signal expRPostExc1_uid91_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal expRPostExc1_uid91_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal signRComp_uid99_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal signRComp_uid99_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal signRComp_uid99_fpCosPiTest_c : std_logic_vector(0 downto 0);
signal signRComp_uid99_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal signR_uid101_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal signR_uid101_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal signR_uid101_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal leftShiftStage0Idx1Pad16_uid105_fxpX_uid41_fpCosPiTest_q : std_logic_vector (15 downto 0);
signal leftShiftStage0Idx2Pad32_uid108_fxpX_uid41_fpCosPiTest_q : std_logic_vector (31 downto 0);
signal leftShiftStage0Idx3_uid111_fxpX_uid41_fpCosPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage1Idx1Pad4_uid114_fxpX_uid41_fpCosPiTest_q : std_logic_vector (3 downto 0);
signal leftShiftStage1Idx3Pad12_uid120_fxpX_uid41_fpCosPiTest_q : std_logic_vector (11 downto 0);
signal leftShiftStage2Idx2Pad2_uid128_fxpX_uid41_fpCosPiTest_q : std_logic_vector (1 downto 0);
signal leftShiftStage2Idx3Pad3_uid131_fxpX_uid41_fpCosPiTest_q : std_logic_vector (2 downto 0);
signal mO_uid140_lzcZ_uid56_fpCosPiTest_q : std_logic_vector (28 downto 0);
signal memoryC2_uid209_sinPiZTableGenerator_q : std_logic_vector(13 downto 0);
signal prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_a : std_logic_vector (23 downto 0);
signal prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_b : std_logic_vector (24 downto 0);
signal prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_s1 : std_logic_vector (48 downto 0);
signal prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_pr : UNSIGNED (48 downto 0);
signal prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_q : std_logic_vector (48 downto 0);
signal prodXY_uid226_pT1_uid211_sinPiZPolyEval_a : std_logic_vector (13 downto 0);
signal prodXY_uid226_pT1_uid211_sinPiZPolyEval_b : std_logic_vector (13 downto 0);
signal prodXY_uid226_pT1_uid211_sinPiZPolyEval_s1 : std_logic_vector (27 downto 0);
signal prodXY_uid226_pT1_uid211_sinPiZPolyEval_pr : SIGNED (28 downto 0);
signal prodXY_uid226_pT1_uid211_sinPiZPolyEval_q : std_logic_vector (27 downto 0);
signal prodXY_uid229_pT2_uid217_sinPiZPolyEval_a : std_logic_vector (15 downto 0);
signal prodXY_uid229_pT2_uid217_sinPiZPolyEval_b : std_logic_vector (22 downto 0);
signal prodXY_uid229_pT2_uid217_sinPiZPolyEval_s1 : std_logic_vector (38 downto 0);
signal prodXY_uid229_pT2_uid217_sinPiZPolyEval_pr : SIGNED (39 downto 0);
signal prodXY_uid229_pT2_uid217_sinPiZPolyEval_q : std_logic_vector (38 downto 0);
signal reg_leftShiftStageSel3Dto2_uid123_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_2_q : std_logic_vector (36 downto 0);
signal reg_leftShiftStage1Idx1_uid116_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_3_q : std_logic_vector (36 downto 0);
signal reg_leftShiftStage1Idx2_uid119_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_4_q : std_logic_vector (36 downto 0);
signal reg_leftShiftStage1Idx3_uid122_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_5_q : std_logic_vector (36 downto 0);
signal reg_leftShiftStageSel1Dto0_uid134_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_fxpXFrac_uid43_fpCosPiTest_0_to_fxpXFracZero_uid45_fpCosPiTest_1_q : std_logic_vector (35 downto 0);
signal reg_cosXIsOne_uid36_fpCosPiTest_1_to_bigCond_uid85_fpCosPiTest_1_q : std_logic_vector (0 downto 0);
signal reg_xIsInt_uid80_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_2_q : std_logic_vector (0 downto 0);
signal reg_fxpXFracHalf_uid46_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_3_q : std_logic_vector (0 downto 0);
signal reg_expXIsZero_uid23_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_4_q : std_logic_vector (0 downto 0);
signal reg_xIsHalf_uid83_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_5_q : std_logic_vector (0 downto 0);
signal reg_pad_o_uid16_uid47_fpCosPiTest_0_to_oMFxpXFrac_uid47_fpCosPiTest_0_q : std_logic_vector (36 downto 0);
signal reg_pad_half_uid17_uid52_fpCosPiTest_0_to_z_halfMRRFxPXE_uid52_fpCosPiTest_0_q : std_logic_vector (35 downto 0);
signal reg_rVStage_uid138_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid139_lzcZ_uid56_fpCosPiTest_1_q : std_logic_vector (31 downto 0);
signal reg_cStage_uid142_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid144_lzcZ_uid56_fpCosPiTest_3_q : std_logic_vector (31 downto 0);
signal reg_rVStage_uid146_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid147_lzcZ_uid56_fpCosPiTest_1_q : std_logic_vector (15 downto 0);
signal reg_vStage_uid148_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid150_lzcZ_uid56_fpCosPiTest_3_q : std_logic_vector (15 downto 0);
signal reg_rVStage_uid158_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid159_lzcZ_uid56_fpCosPiTest_1_q : std_logic_vector (3 downto 0);
signal reg_vStage_uid160_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid162_lzcZ_uid56_fpCosPiTest_3_q : std_logic_vector (3 downto 0);
signal reg_vCount_uid153_lzcZ_uid56_fpCosPiTest_0_to_r_uid172_lzcZ_uid56_fpCosPiTest_3_q : std_logic_vector (0 downto 0);
signal reg_leftShiftStageSel3Dto2_uid193_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_2_q : std_logic_vector (34 downto 0);
signal reg_leftShiftStage1Idx1_uid186_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_3_q : std_logic_vector (34 downto 0);
signal reg_leftShiftStage1Idx2_uid189_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_4_q : std_logic_vector (34 downto 0);
signal reg_leftShiftStage1Idx3_uid192_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_5_q : std_logic_vector (34 downto 0);
signal reg_leftShiftStageSel1Dto0_uid204_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_zAddr_uid62_fpCosPiTest_0_to_memoryC2_uid209_sinPiZTableGenerator_0_q : std_logic_vector (6 downto 0);
signal reg_yT1_uid210_sinPiZPolyEval_0_to_prodXY_uid226_pT1_uid211_sinPiZPolyEval_0_q : std_logic_vector (13 downto 0);
signal reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_q : std_logic_vector (15 downto 0);
signal reg_s1_uid212_uid215_sinPiZPolyEval_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_1_q : std_logic_vector (22 downto 0);
signal reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_q : std_logic_vector (23 downto 0);
signal reg_fxpSinRes_uid65_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_1_q : std_logic_vector (24 downto 0);
signal reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q : std_logic_vector (5 downto 0);
signal reg_expP_uid60_fpCosPiTest_0_to_expFracPreRnd_uid71_uid71_fpCosPiTest_1_q : std_logic_vector (7 downto 0);
signal reg_excRNaN_uid84_fpCosPiTest_0_to_fracRPostExc_uid88_fpCosPiTest_1_q : std_logic_vector (0 downto 0);
signal reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q : std_logic_vector (1 downto 0);
signal ld_FxpXFrac35_uid44_fpCosPiTest_b_to_rangeReducedFxPX_uid51_fpCosPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_fxpXFrac_uid43_fpCosPiTest_b_to_rangeReducedFxPX_uid51_fpCosPiTest_c_q : std_logic_vector (35 downto 0);
signal ld_cosXIsOne_uid36_fpCosPiTest_c_to_InvCosXIsOne_uid77_fpCosPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_xEvenInt_uid35_fpCosPiTest_c_to_evenIntCosNotOneFZ_uid79_fpCosPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_exc_R_uid34_fpCosPiTest_q_to_xIsInt_uid80_fpCosPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_reg_cosXIsOne_uid36_fpCosPiTest_1_to_bigCond_uid85_fpCosPiTest_1_q_to_bigCond_uid85_fpCosPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_bigCond_uid85_fpCosPiTest_q_to_fracRPostExc1_uid86_fpCosPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_reg_excRNaN_uid84_fpCosPiTest_0_to_fracRPostExc_uid88_fpCosPiTest_1_q_to_fracRPostExc_uid88_fpCosPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_xIsHalf_uid83_fpCosPiTest_q_to_expRPostExc1_uid91_fpCosPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_expXIsZero_uid23_fpCosPiTest_q_to_xIntOrXZOrCosOne_uid93_fpCosPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_rInfOrNaN_uid92_fpCosPiTest_q_to_join_uid94_fpCosPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_xParityXorHalfParity_uid96_fpCosPiTest_q_to_signRComp_uid99_fpCosPiTest_c_q : std_logic_vector (0 downto 0);
signal ld_fxpXFracHalf_uid46_fpCosPiTest_q_to_InvFxpXFracHalf_uid100_fpCosPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_signR_uid101_fpCosPiTest_q_to_R_uid102_fpCosPiTest_c_q : std_logic_vector (0 downto 0);
signal ld_vCount_uid147_lzcZ_uid56_fpCosPiTest_q_to_r_uid172_lzcZ_uid56_fpCosPiTest_e_q : std_logic_vector (0 downto 0);
signal ld_vCount_uid139_lzcZ_uid56_fpCosPiTest_q_to_r_uid172_lzcZ_uid56_fpCosPiTest_f_q : std_logic_vector (0 downto 0);
signal ld_X18dto0_uid176_alignedZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx1_uid177_alignedZ_uid57_fpCosPiTest_b_q : std_logic_vector (18 downto 0);
signal ld_vStage_uid141_lzcZ_uid56_fpCosPiTest_b_to_leftShiftStage0Idx2_uid180_alignedZ_uid57_fpCosPiTest_b_q : std_logic_vector (2 downto 0);
signal ld_z_uid54_fpCosPiTest_b_to_leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_c_q : std_logic_vector (34 downto 0);
signal ld_reg_yT1_uid210_sinPiZPolyEval_0_to_prodXY_uid226_pT1_uid211_sinPiZPolyEval_0_q_to_prodXY_uid226_pT1_uid211_sinPiZPolyEval_a_q : std_logic_vector (13 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_reset0 : std_logic;
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_ia : std_logic_vector (5 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_iq : std_logic_vector (5 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_q : std_logic_vector (5 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt_eq : std_logic;
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_mem_top_q : std_logic_vector (3 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve : boolean;
attribute preserve of ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_sticky_ena_q : signal is true;
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_reset0 : std_logic;
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_ia : std_logic_vector (1 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_iq : std_logic_vector (1 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_q : std_logic_vector (1 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt_eq : std_logic;
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_mem_top_q : std_logic_vector (4 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_sticky_ena_q : signal is true;
signal ld_X18dto0_uid176_alignedZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx1_uid177_alignedZ_uid57_fpCosPiTest_b_inputreg_q : std_logic_vector (18 downto 0);
signal ld_z_uid54_fpCosPiTest_b_to_leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_c_inputreg_q : std_logic_vector (34 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_reset0 : std_logic;
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_ia : std_logic_vector (6 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_iq : std_logic_vector (6 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_q : std_logic_vector (6 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_sticky_ena_q : signal is true;
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_reset0 : std_logic;
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_ia : std_logic_vector (6 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_aa : std_logic_vector (1 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_ab : std_logic_vector (1 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_iq : std_logic_vector (6 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_q : std_logic_vector (6 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt_q : std_logic_vector(1 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt_i : unsigned(1 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt_eq : std_logic;
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdreg_q : std_logic_vector (1 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_mem_top_q : std_logic_vector (2 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_sticky_ena_q : signal is true;
signal ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_inputreg_q : std_logic_vector (15 downto 0);
signal ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_reset0 : std_logic;
signal ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_ia : std_logic_vector (15 downto 0);
signal ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_aa : std_logic_vector (1 downto 0);
signal ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_ab : std_logic_vector (1 downto 0);
signal ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_iq : std_logic_vector (15 downto 0);
signal ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_q : std_logic_vector (15 downto 0);
signal ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_sticky_ena_q : signal is true;
signal ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_inputreg_q : std_logic_vector (23 downto 0);
signal ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_reset0 : std_logic;
signal ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_ia : std_logic_vector (23 downto 0);
signal ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_aa : std_logic_vector (1 downto 0);
signal ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_ab : std_logic_vector (1 downto 0);
signal ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_iq : std_logic_vector (23 downto 0);
signal ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_q : std_logic_vector (23 downto 0);
signal ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_sticky_ena_q : signal is true;
signal pad_o_uid16_uid47_fpCosPiTest_q : std_logic_vector (36 downto 0);
signal pad_half_uid17_uid52_fpCosPiTest_q : std_logic_vector (35 downto 0);
signal bigCond_uid85_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal bigCond_uid85_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal bigCond_uid85_fpCosPiTest_c : std_logic_vector(0 downto 0);
signal bigCond_uid85_fpCosPiTest_d : std_logic_vector(0 downto 0);
signal bigCond_uid85_fpCosPiTest_f : std_logic_vector(0 downto 0);
signal bigCond_uid85_fpCosPiTest_g : std_logic_vector(0 downto 0);
signal bigCond_uid85_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal InvCosXIsOne_uid77_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal InvCosXIsOne_uid77_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal InvXEvenInt_uid81_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal InvXEvenInt_uid81_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal InvFxpXFracHalf_uid100_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal InvFxpXFracHalf_uid100_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal cstHalfwSwFP1_uid18_fpCosPiTest_q : std_logic_vector (35 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_notEnable_a : std_logic_vector(0 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_notEnable_q : std_logic_vector(0 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdmux_q : std_logic_vector (1 downto 0);
signal expX_uid6_fpCosPiTest_in : std_logic_vector (30 downto 0);
signal expX_uid6_fpCosPiTest_b : std_logic_vector (7 downto 0);
signal fracX_uid7_fpCosPiTest_in : std_logic_vector (22 downto 0);
signal fracX_uid7_fpCosPiTest_b : std_logic_vector (22 downto 0);
signal expXIsZero_uid23_fpCosPiTest_a : std_logic_vector(7 downto 0);
signal expXIsZero_uid23_fpCosPiTest_b : std_logic_vector(7 downto 0);
signal expXIsZero_uid23_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal expXIsMax_uid25_fpCosPiTest_a : std_logic_vector(7 downto 0);
signal expXIsMax_uid25_fpCosPiTest_b : std_logic_vector(7 downto 0);
signal expXIsMax_uid25_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal fracXIsZero_uid27_fpCosPiTest_a : std_logic_vector(22 downto 0);
signal fracXIsZero_uid27_fpCosPiTest_b : std_logic_vector(22 downto 0);
signal fracXIsZero_uid27_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal exc_I_uid28_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal exc_I_uid28_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal exc_I_uid28_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal xEvenInt_uid35_fpCosPiTest_a : std_logic_vector(10 downto 0);
signal xEvenInt_uid35_fpCosPiTest_b : std_logic_vector(10 downto 0);
signal xEvenInt_uid35_fpCosPiTest_o : std_logic_vector (10 downto 0);
signal xEvenInt_uid35_fpCosPiTest_cin : std_logic_vector (0 downto 0);
signal xEvenInt_uid35_fpCosPiTest_c : std_logic_vector (0 downto 0);
signal cosXIsOne_uid36_fpCosPiTest_a : std_logic_vector(10 downto 0);
signal cosXIsOne_uid36_fpCosPiTest_b : std_logic_vector(10 downto 0);
signal cosXIsOne_uid36_fpCosPiTest_o : std_logic_vector (10 downto 0);
signal cosXIsOne_uid36_fpCosPiTest_cin : std_logic_vector (0 downto 0);
signal cosXIsOne_uid36_fpCosPiTest_c : std_logic_vector (0 downto 0);
signal shiftValFxPX_uid38_fpCosPiTest_a : std_logic_vector(8 downto 0);
signal shiftValFxPX_uid38_fpCosPiTest_b : std_logic_vector(8 downto 0);
signal shiftValFxPX_uid38_fpCosPiTest_o : std_logic_vector (8 downto 0);
signal shiftValFxPX_uid38_fpCosPiTest_q : std_logic_vector (8 downto 0);
signal fxpXFracZero_uid45_fpCosPiTest_a : std_logic_vector(35 downto 0);
signal fxpXFracZero_uid45_fpCosPiTest_b : std_logic_vector(35 downto 0);
signal fxpXFracZero_uid45_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal fxpXFracHalf_uid46_fpCosPiTest_a : std_logic_vector(35 downto 0);
signal fxpXFracHalf_uid46_fpCosPiTest_b : std_logic_vector(35 downto 0);
signal fxpXFracHalf_uid46_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal oMFxpXFrac_uid47_fpCosPiTest_a : std_logic_vector(37 downto 0);
signal oMFxpXFrac_uid47_fpCosPiTest_b : std_logic_vector(37 downto 0);
signal oMFxpXFrac_uid47_fpCosPiTest_o : std_logic_vector (37 downto 0);
signal oMFxpXFrac_uid47_fpCosPiTest_q : std_logic_vector (37 downto 0);
signal z_halfMRRFxPXE_uid52_fpCosPiTest_a : std_logic_vector(36 downto 0);
signal z_halfMRRFxPXE_uid52_fpCosPiTest_b : std_logic_vector(36 downto 0);
signal z_halfMRRFxPXE_uid52_fpCosPiTest_o : std_logic_vector (36 downto 0);
signal z_halfMRRFxPXE_uid52_fpCosPiTest_q : std_logic_vector (36 downto 0);
signal expHardCase_uid59_fpCosPiTest_a : std_logic_vector(8 downto 0);
signal expHardCase_uid59_fpCosPiTest_b : std_logic_vector(8 downto 0);
signal expHardCase_uid59_fpCosPiTest_o : std_logic_vector (8 downto 0);
signal expHardCase_uid59_fpCosPiTest_q : std_logic_vector (8 downto 0);
signal fracZCosNotOne_uid78_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal fracZCosNotOne_uid78_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal fracZCosNotOne_uid78_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal evenIntCosNotOneFZ_uid79_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal evenIntCosNotOneFZ_uid79_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal evenIntCosNotOneFZ_uid79_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal xIsInt_uid80_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal xIsInt_uid80_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal xIsInt_uid80_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal xIsHalf_uid83_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal xIsHalf_uid83_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal xIsHalf_uid83_fpCosPiTest_c : std_logic_vector(0 downto 0);
signal xIsHalf_uid83_fpCosPiTest_d : std_logic_vector(0 downto 0);
signal xIsHalf_uid83_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal fracRPostExc_uid88_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal fracRPostExc_uid88_fpCosPiTest_q : std_logic_vector (22 downto 0);
signal xIntOrXZOrCosOne_uid93_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal xIntOrXZOrCosOne_uid93_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal xIntOrXZOrCosOne_uid93_fpCosPiTest_c : std_logic_vector(0 downto 0);
signal xIntOrXZOrCosOne_uid93_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal expRPostExc_uid95_fpCosPiTest_s : std_logic_vector (1 downto 0);
signal expRPostExc_uid95_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_q : std_logic_vector (36 downto 0);
signal vCount_uid139_lzcZ_uid56_fpCosPiTest_a : std_logic_vector(31 downto 0);
signal vCount_uid139_lzcZ_uid56_fpCosPiTest_b : std_logic_vector(31 downto 0);
signal vCount_uid139_lzcZ_uid56_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid144_lzcZ_uid56_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid144_lzcZ_uid56_fpCosPiTest_q : std_logic_vector (31 downto 0);
signal vCount_uid147_lzcZ_uid56_fpCosPiTest_a : std_logic_vector(15 downto 0);
signal vCount_uid147_lzcZ_uid56_fpCosPiTest_b : std_logic_vector(15 downto 0);
signal vCount_uid147_lzcZ_uid56_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid150_lzcZ_uid56_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid150_lzcZ_uid56_fpCosPiTest_q : std_logic_vector (15 downto 0);
signal vCount_uid159_lzcZ_uid56_fpCosPiTest_a : std_logic_vector(3 downto 0);
signal vCount_uid159_lzcZ_uid56_fpCosPiTest_b : std_logic_vector(3 downto 0);
signal vCount_uid159_lzcZ_uid56_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid162_lzcZ_uid56_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid162_lzcZ_uid56_fpCosPiTest_q : std_logic_vector (3 downto 0);
signal leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_q : std_logic_vector (34 downto 0);
signal memoryC0_uid207_sinPiZTableGenerator_q : std_logic_vector(28 downto 0);
signal memoryC1_uid208_sinPiZTableGenerator_q : std_logic_vector(20 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal leftShiftStage0Idx1_uid177_alignedZ_uid57_fpCosPiTest_q : std_logic_vector (34 downto 0);
signal leftShiftStage0Idx2_uid180_alignedZ_uid57_fpCosPiTest_q : std_logic_vector (34 downto 0);
signal prodXYTruncFR_uid224_mul2xSinRes_uid66_fpCosPiTest_in : std_logic_vector (48 downto 0);
signal prodXYTruncFR_uid224_mul2xSinRes_uid66_fpCosPiTest_b : std_logic_vector (25 downto 0);
signal prodXYTruncFR_uid227_pT1_uid211_sinPiZPolyEval_in : std_logic_vector (27 downto 0);
signal prodXYTruncFR_uid227_pT1_uid211_sinPiZPolyEval_b : std_logic_vector (14 downto 0);
signal prodXYTruncFR_uid230_pT2_uid217_sinPiZPolyEval_in : std_logic_vector (38 downto 0);
signal prodXYTruncFR_uid230_pT2_uid217_sinPiZPolyEval_b : std_logic_vector (23 downto 0);
signal join_uid94_fpCosPiTest_q : std_logic_vector (1 downto 0);
signal R_uid102_fpCosPiTest_q : std_logic_vector (31 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_cmp_a : std_logic_vector(3 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_cmp_b : std_logic_vector(3 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_cmp_a : std_logic_vector(4 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_cmp_b : std_logic_vector(4 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_cmp_a : std_logic_vector(2 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_cmp_b : std_logic_vector(2 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_nor_q : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_nor_q : std_logic_vector(0 downto 0);
signal oFracX_uid37_uid37_fpCosPiTest_q : std_logic_vector (23 downto 0);
signal InvExpXIsZero_uid33_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid33_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid29_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid29_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal InvExc_I_uid32_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal InvExc_I_uid32_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal fxpShifterBits_uid40_fpCosPiTest_in : std_logic_vector (5 downto 0);
signal fxpShifterBits_uid40_fpCosPiTest_b : std_logic_vector (5 downto 0);
signal oMFxpXFrac_uid49_fpCosPiTest_in : std_logic_vector (35 downto 0);
signal oMFxpXFrac_uid49_fpCosPiTest_b : std_logic_vector (35 downto 0);
signal z_uid54_fpCosPiTest_in : std_logic_vector (34 downto 0);
signal z_uid54_fpCosPiTest_b : std_logic_vector (34 downto 0);
signal expP_uid60_fpCosPiTest_in : std_logic_vector (7 downto 0);
signal expP_uid60_fpCosPiTest_b : std_logic_vector (7 downto 0);
signal LeftShiftStage135dto0_uid126_fxpX_uid41_fpCosPiTest_in : std_logic_vector (35 downto 0);
signal LeftShiftStage135dto0_uid126_fxpX_uid41_fpCosPiTest_b : std_logic_vector (35 downto 0);
signal LeftShiftStage134dto0_uid129_fxpX_uid41_fpCosPiTest_in : std_logic_vector (34 downto 0);
signal LeftShiftStage134dto0_uid129_fxpX_uid41_fpCosPiTest_b : std_logic_vector (34 downto 0);
signal LeftShiftStage133dto0_uid132_fxpX_uid41_fpCosPiTest_in : std_logic_vector (33 downto 0);
signal LeftShiftStage133dto0_uid132_fxpX_uid41_fpCosPiTest_b : std_logic_vector (33 downto 0);
signal rVStage_uid146_lzcZ_uid56_fpCosPiTest_in : std_logic_vector (31 downto 0);
signal rVStage_uid146_lzcZ_uid56_fpCosPiTest_b : std_logic_vector (15 downto 0);
signal vStage_uid148_lzcZ_uid56_fpCosPiTest_in : std_logic_vector (15 downto 0);
signal vStage_uid148_lzcZ_uid56_fpCosPiTest_b : std_logic_vector (15 downto 0);
signal rVStage_uid152_lzcZ_uid56_fpCosPiTest_in : std_logic_vector (15 downto 0);
signal rVStage_uid152_lzcZ_uid56_fpCosPiTest_b : std_logic_vector (7 downto 0);
signal vStage_uid154_lzcZ_uid56_fpCosPiTest_in : std_logic_vector (7 downto 0);
signal vStage_uid154_lzcZ_uid56_fpCosPiTest_b : std_logic_vector (7 downto 0);
signal rVStage_uid164_lzcZ_uid56_fpCosPiTest_in : std_logic_vector (3 downto 0);
signal rVStage_uid164_lzcZ_uid56_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal vStage_uid166_lzcZ_uid56_fpCosPiTest_in : std_logic_vector (1 downto 0);
signal vStage_uid166_lzcZ_uid56_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal LeftShiftStage133dto0_uid196_alignedZ_uid57_fpCosPiTest_in : std_logic_vector (33 downto 0);
signal LeftShiftStage133dto0_uid196_alignedZ_uid57_fpCosPiTest_b : std_logic_vector (33 downto 0);
signal LeftShiftStage132dto0_uid199_alignedZ_uid57_fpCosPiTest_in : std_logic_vector (32 downto 0);
signal LeftShiftStage132dto0_uid199_alignedZ_uid57_fpCosPiTest_b : std_logic_vector (32 downto 0);
signal LeftShiftStage131dto0_uid202_alignedZ_uid57_fpCosPiTest_in : std_logic_vector (31 downto 0);
signal LeftShiftStage131dto0_uid202_alignedZ_uid57_fpCosPiTest_b : std_logic_vector (31 downto 0);
signal normBit_uid67_fpCosPiTest_in : std_logic_vector (25 downto 0);
signal normBit_uid67_fpCosPiTest_b : std_logic_vector (0 downto 0);
signal highRes_uid68_fpCosPiTest_in : std_logic_vector (24 downto 0);
signal highRes_uid68_fpCosPiTest_b : std_logic_vector (23 downto 0);
signal lowRes_uid69_fpCosPiTest_in : std_logic_vector (23 downto 0);
signal lowRes_uid69_fpCosPiTest_b : std_logic_vector (23 downto 0);
signal lowRangeB_uid212_sinPiZPolyEval_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid212_sinPiZPolyEval_b : std_logic_vector (0 downto 0);
signal highBBits_uid213_sinPiZPolyEval_in : std_logic_vector (14 downto 0);
signal highBBits_uid213_sinPiZPolyEval_b : std_logic_vector (13 downto 0);
signal lowRangeB_uid218_sinPiZPolyEval_in : std_logic_vector (1 downto 0);
signal lowRangeB_uid218_sinPiZPolyEval_b : std_logic_vector (1 downto 0);
signal highBBits_uid219_sinPiZPolyEval_in : std_logic_vector (23 downto 0);
signal highBBits_uid219_sinPiZPolyEval_b : std_logic_vector (21 downto 0);
signal oFracXExt_uid39_fpCosPiTest_q : std_logic_vector (36 downto 0);
signal exc_N_uid30_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal exc_N_uid30_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal exc_N_uid30_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal leftShiftStageSel5Dto4_uid112_fxpX_uid41_fpCosPiTest_in : std_logic_vector (5 downto 0);
signal leftShiftStageSel5Dto4_uid112_fxpX_uid41_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel3Dto2_uid123_fxpX_uid41_fpCosPiTest_in : std_logic_vector (3 downto 0);
signal leftShiftStageSel3Dto2_uid123_fxpX_uid41_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid134_fxpX_uid41_fpCosPiTest_in : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid134_fxpX_uid41_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal zAddr_uid62_fpCosPiTest_in : std_logic_vector (34 downto 0);
signal zAddr_uid62_fpCosPiTest_b : std_logic_vector (6 downto 0);
signal zPPolyEval_uid63_fpCosPiTest_in : std_logic_vector (27 downto 0);
signal zPPolyEval_uid63_fpCosPiTest_b : std_logic_vector (15 downto 0);
signal rVStage_uid138_lzcZ_uid56_fpCosPiTest_in : std_logic_vector (34 downto 0);
signal rVStage_uid138_lzcZ_uid56_fpCosPiTest_b : std_logic_vector (31 downto 0);
signal vStage_uid141_lzcZ_uid56_fpCosPiTest_in : std_logic_vector (2 downto 0);
signal vStage_uid141_lzcZ_uid56_fpCosPiTest_b : std_logic_vector (2 downto 0);
signal X18dto0_uid176_alignedZ_uid57_fpCosPiTest_in : std_logic_vector (18 downto 0);
signal X18dto0_uid176_alignedZ_uid57_fpCosPiTest_b : std_logic_vector (18 downto 0);
signal leftShiftStage2Idx1_uid127_fxpX_uid41_fpCosPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage2Idx2_uid130_fxpX_uid41_fpCosPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage2Idx3_uid133_fxpX_uid41_fpCosPiTest_q : std_logic_vector (36 downto 0);
signal vCount_uid153_lzcZ_uid56_fpCosPiTest_a : std_logic_vector(7 downto 0);
signal vCount_uid153_lzcZ_uid56_fpCosPiTest_b : std_logic_vector(7 downto 0);
signal vCount_uid153_lzcZ_uid56_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid156_lzcZ_uid56_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid156_lzcZ_uid56_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal vCount_uid165_lzcZ_uid56_fpCosPiTest_a : std_logic_vector(1 downto 0);
signal vCount_uid165_lzcZ_uid56_fpCosPiTest_b : std_logic_vector(1 downto 0);
signal vCount_uid165_lzcZ_uid56_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid168_lzcZ_uid56_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid168_lzcZ_uid56_fpCosPiTest_q : std_logic_vector (1 downto 0);
signal leftShiftStage2Idx1_uid197_alignedZ_uid57_fpCosPiTest_q : std_logic_vector (34 downto 0);
signal leftShiftStage2Idx2_uid200_alignedZ_uid57_fpCosPiTest_q : std_logic_vector (34 downto 0);
signal leftShiftStage2Idx3_uid203_alignedZ_uid57_fpCosPiTest_q : std_logic_vector (34 downto 0);
signal fracRCompPreRnd_uid70_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal fracRCompPreRnd_uid70_fpCosPiTest_q : std_logic_vector (23 downto 0);
signal rndExpUpdate_uid72_uid73_fpCosPiTest_q : std_logic_vector (24 downto 0);
signal sumAHighB_uid214_sinPiZPolyEval_a : std_logic_vector(21 downto 0);
signal sumAHighB_uid214_sinPiZPolyEval_b : std_logic_vector(21 downto 0);
signal sumAHighB_uid214_sinPiZPolyEval_o : std_logic_vector (21 downto 0);
signal sumAHighB_uid214_sinPiZPolyEval_q : std_logic_vector (21 downto 0);
signal sumAHighB_uid220_sinPiZPolyEval_a : std_logic_vector(29 downto 0);
signal sumAHighB_uid220_sinPiZPolyEval_b : std_logic_vector(29 downto 0);
signal sumAHighB_uid220_sinPiZPolyEval_o : std_logic_vector (29 downto 0);
signal sumAHighB_uid220_sinPiZPolyEval_q : std_logic_vector (29 downto 0);
signal X20dto0_uid106_fxpX_uid41_fpCosPiTest_in : std_logic_vector (20 downto 0);
signal X20dto0_uid106_fxpX_uid41_fpCosPiTest_b : std_logic_vector (20 downto 0);
signal X4dto0_uid109_fxpX_uid41_fpCosPiTest_in : std_logic_vector (4 downto 0);
signal X4dto0_uid109_fxpX_uid41_fpCosPiTest_b : std_logic_vector (4 downto 0);
signal InvExc_N_uid31_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal InvExc_N_uid31_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal excRNaN_uid84_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal excRNaN_uid84_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal excRNaN_uid84_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal yT1_uid210_sinPiZPolyEval_in : std_logic_vector (15 downto 0);
signal yT1_uid210_sinPiZPolyEval_b : std_logic_vector (13 downto 0);
signal cStage_uid142_lzcZ_uid56_fpCosPiTest_q : std_logic_vector (31 downto 0);
signal leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest_q : std_logic_vector (36 downto 0);
signal rVStage_uid158_lzcZ_uid56_fpCosPiTest_in : std_logic_vector (7 downto 0);
signal rVStage_uid158_lzcZ_uid56_fpCosPiTest_b : std_logic_vector (3 downto 0);
signal vStage_uid160_lzcZ_uid56_fpCosPiTest_in : std_logic_vector (3 downto 0);
signal vStage_uid160_lzcZ_uid56_fpCosPiTest_b : std_logic_vector (3 downto 0);
signal rVStage_uid170_lzcZ_uid56_fpCosPiTest_in : std_logic_vector (1 downto 0);
signal rVStage_uid170_lzcZ_uid56_fpCosPiTest_b : std_logic_vector (0 downto 0);
signal leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest_q : std_logic_vector (34 downto 0);
signal expFracPreRnd_uid71_uid71_fpCosPiTest_q : std_logic_vector (31 downto 0);
signal expFracComp_uid74_fpCosPiTest_a : std_logic_vector(32 downto 0);
signal expFracComp_uid74_fpCosPiTest_b : std_logic_vector(32 downto 0);
signal expFracComp_uid74_fpCosPiTest_o : std_logic_vector (32 downto 0);
signal expFracComp_uid74_fpCosPiTest_q : std_logic_vector (32 downto 0);
signal s1_uid212_uid215_sinPiZPolyEval_q : std_logic_vector (22 downto 0);
signal s2_uid218_uid221_sinPiZPolyEval_q : std_logic_vector (31 downto 0);
signal leftShiftStage0Idx1_uid107_fxpX_uid41_fpCosPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage0Idx2_uid110_fxpX_uid41_fpCosPiTest_q : std_logic_vector (36 downto 0);
signal exc_R_uid34_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal exc_R_uid34_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal exc_R_uid34_fpCosPiTest_c : std_logic_vector(0 downto 0);
signal exc_R_uid34_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal rInfOrNaN_uid92_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal rInfOrNaN_uid92_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal rInfOrNaN_uid92_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal FxpX36_uid42_fpCosPiTest_in : std_logic_vector (36 downto 0);
signal FxpX36_uid42_fpCosPiTest_b : std_logic_vector (0 downto 0);
signal fxpXFrac_uid43_fpCosPiTest_in : std_logic_vector (35 downto 0);
signal fxpXFrac_uid43_fpCosPiTest_b : std_logic_vector (35 downto 0);
signal vCount_uid171_lzcZ_uid56_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal vCount_uid171_lzcZ_uid56_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal vCount_uid171_lzcZ_uid56_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal alignedZLow_uid58_fpCosPiTest_in : std_logic_vector (34 downto 0);
signal alignedZLow_uid58_fpCosPiTest_b : std_logic_vector (23 downto 0);
signal fracRComp_uid75_fpCosPiTest_in : std_logic_vector (23 downto 0);
signal fracRComp_uid75_fpCosPiTest_b : std_logic_vector (22 downto 0);
signal expRComp_uid76_fpCosPiTest_in : std_logic_vector (31 downto 0);
signal expRComp_uid76_fpCosPiTest_b : std_logic_vector (7 downto 0);
signal fxpSinRes_uid65_fpCosPiTest_in : std_logic_vector (29 downto 0);
signal fxpSinRes_uid65_fpCosPiTest_b : std_logic_vector (24 downto 0);
signal leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_q : std_logic_vector (36 downto 0);
signal FxpXFrac35_uid44_fpCosPiTest_in : std_logic_vector (35 downto 0);
signal FxpXFrac35_uid44_fpCosPiTest_b : std_logic_vector (0 downto 0);
signal r_uid172_lzcZ_uid56_fpCosPiTest_q : std_logic_vector (5 downto 0);
signal LeftShiftStage032dto0_uid115_fxpX_uid41_fpCosPiTest_in : std_logic_vector (32 downto 0);
signal LeftShiftStage032dto0_uid115_fxpX_uid41_fpCosPiTest_b : std_logic_vector (32 downto 0);
signal LeftShiftStage028dto0_uid118_fxpX_uid41_fpCosPiTest_in : std_logic_vector (28 downto 0);
signal LeftShiftStage028dto0_uid118_fxpX_uid41_fpCosPiTest_b : std_logic_vector (28 downto 0);
signal LeftShiftStage024dto0_uid121_fxpX_uid41_fpCosPiTest_in : std_logic_vector (24 downto 0);
signal LeftShiftStage024dto0_uid121_fxpX_uid41_fpCosPiTest_b : std_logic_vector (24 downto 0);
signal xParityXorHalfParity_uid96_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal xParityXorHalfParity_uid96_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal xParityXorHalfParity_uid96_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal leftShiftStageSel5Dto4_uid182_alignedZ_uid57_fpCosPiTest_in : std_logic_vector (5 downto 0);
signal leftShiftStageSel5Dto4_uid182_alignedZ_uid57_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel3Dto2_uid193_alignedZ_uid57_fpCosPiTest_in : std_logic_vector (3 downto 0);
signal leftShiftStageSel3Dto2_uid193_alignedZ_uid57_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid204_alignedZ_uid57_fpCosPiTest_in : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid204_alignedZ_uid57_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStage1Idx1_uid116_fxpX_uid41_fpCosPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage1Idx2_uid119_fxpX_uid41_fpCosPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage1Idx3_uid122_fxpX_uid41_fpCosPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_q : std_logic_vector (34 downto 0);
signal LeftShiftStage030dto0_uid185_alignedZ_uid57_fpCosPiTest_in : std_logic_vector (30 downto 0);
signal LeftShiftStage030dto0_uid185_alignedZ_uid57_fpCosPiTest_b : std_logic_vector (30 downto 0);
signal LeftShiftStage026dto0_uid188_alignedZ_uid57_fpCosPiTest_in : std_logic_vector (26 downto 0);
signal LeftShiftStage026dto0_uid188_alignedZ_uid57_fpCosPiTest_b : std_logic_vector (26 downto 0);
signal LeftShiftStage022dto0_uid191_alignedZ_uid57_fpCosPiTest_in : std_logic_vector (22 downto 0);
signal LeftShiftStage022dto0_uid191_alignedZ_uid57_fpCosPiTest_b : std_logic_vector (22 downto 0);
signal leftShiftStage1Idx1_uid186_alignedZ_uid57_fpCosPiTest_q : std_logic_vector (34 downto 0);
signal leftShiftStage1Idx2_uid189_alignedZ_uid57_fpCosPiTest_q : std_logic_vector (34 downto 0);
signal leftShiftStage1Idx3_uid192_alignedZ_uid57_fpCosPiTest_q : std_logic_vector (34 downto 0);
begin
--xIn(GPIN,3)@0
--LeftShiftStage133dto0_uid132_fxpX_uid41_fpCosPiTest(BITSELECT,131)@1
LeftShiftStage133dto0_uid132_fxpX_uid41_fpCosPiTest_in <= leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_q(33 downto 0);
LeftShiftStage133dto0_uid132_fxpX_uid41_fpCosPiTest_b <= LeftShiftStage133dto0_uid132_fxpX_uid41_fpCosPiTest_in(33 downto 0);
--leftShiftStage2Idx3Pad3_uid131_fxpX_uid41_fpCosPiTest(CONSTANT,130)
leftShiftStage2Idx3Pad3_uid131_fxpX_uid41_fpCosPiTest_q <= "000";
--leftShiftStage2Idx3_uid133_fxpX_uid41_fpCosPiTest(BITJOIN,132)@1
leftShiftStage2Idx3_uid133_fxpX_uid41_fpCosPiTest_q <= LeftShiftStage133dto0_uid132_fxpX_uid41_fpCosPiTest_b & leftShiftStage2Idx3Pad3_uid131_fxpX_uid41_fpCosPiTest_q;
--LeftShiftStage134dto0_uid129_fxpX_uid41_fpCosPiTest(BITSELECT,128)@1
LeftShiftStage134dto0_uid129_fxpX_uid41_fpCosPiTest_in <= leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_q(34 downto 0);
LeftShiftStage134dto0_uid129_fxpX_uid41_fpCosPiTest_b <= LeftShiftStage134dto0_uid129_fxpX_uid41_fpCosPiTest_in(34 downto 0);
--leftShiftStage2Idx2Pad2_uid128_fxpX_uid41_fpCosPiTest(CONSTANT,127)
leftShiftStage2Idx2Pad2_uid128_fxpX_uid41_fpCosPiTest_q <= "00";
--leftShiftStage2Idx2_uid130_fxpX_uid41_fpCosPiTest(BITJOIN,129)@1
leftShiftStage2Idx2_uid130_fxpX_uid41_fpCosPiTest_q <= LeftShiftStage134dto0_uid129_fxpX_uid41_fpCosPiTest_b & leftShiftStage2Idx2Pad2_uid128_fxpX_uid41_fpCosPiTest_q;
--LeftShiftStage135dto0_uid126_fxpX_uid41_fpCosPiTest(BITSELECT,125)@1
LeftShiftStage135dto0_uid126_fxpX_uid41_fpCosPiTest_in <= leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_q(35 downto 0);
LeftShiftStage135dto0_uid126_fxpX_uid41_fpCosPiTest_b <= LeftShiftStage135dto0_uid126_fxpX_uid41_fpCosPiTest_in(35 downto 0);
--GND(CONSTANT,0)
GND_q <= "0";
--leftShiftStage2Idx1_uid127_fxpX_uid41_fpCosPiTest(BITJOIN,126)@1
leftShiftStage2Idx1_uid127_fxpX_uid41_fpCosPiTest_q <= LeftShiftStage135dto0_uid126_fxpX_uid41_fpCosPiTest_b & GND_q;
--leftShiftStage0Idx3_uid111_fxpX_uid41_fpCosPiTest(CONSTANT,110)
leftShiftStage0Idx3_uid111_fxpX_uid41_fpCosPiTest_q <= "0000000000000000000000000000000000000";
--X4dto0_uid109_fxpX_uid41_fpCosPiTest(BITSELECT,108)@0
X4dto0_uid109_fxpX_uid41_fpCosPiTest_in <= oFracXExt_uid39_fpCosPiTest_q(4 downto 0);
X4dto0_uid109_fxpX_uid41_fpCosPiTest_b <= X4dto0_uid109_fxpX_uid41_fpCosPiTest_in(4 downto 0);
--leftShiftStage0Idx2Pad32_uid108_fxpX_uid41_fpCosPiTest(CONSTANT,107)
leftShiftStage0Idx2Pad32_uid108_fxpX_uid41_fpCosPiTest_q <= "00000000000000000000000000000000";
--leftShiftStage0Idx2_uid110_fxpX_uid41_fpCosPiTest(BITJOIN,109)@0
leftShiftStage0Idx2_uid110_fxpX_uid41_fpCosPiTest_q <= X4dto0_uid109_fxpX_uid41_fpCosPiTest_b & leftShiftStage0Idx2Pad32_uid108_fxpX_uid41_fpCosPiTest_q;
--X20dto0_uid106_fxpX_uid41_fpCosPiTest(BITSELECT,105)@0
X20dto0_uid106_fxpX_uid41_fpCosPiTest_in <= oFracXExt_uid39_fpCosPiTest_q(20 downto 0);
X20dto0_uid106_fxpX_uid41_fpCosPiTest_b <= X20dto0_uid106_fxpX_uid41_fpCosPiTest_in(20 downto 0);
--leftShiftStage0Idx1Pad16_uid105_fxpX_uid41_fpCosPiTest(CONSTANT,104)
leftShiftStage0Idx1Pad16_uid105_fxpX_uid41_fpCosPiTest_q <= "0000000000000000";
--leftShiftStage0Idx1_uid107_fxpX_uid41_fpCosPiTest(BITJOIN,106)@0
leftShiftStage0Idx1_uid107_fxpX_uid41_fpCosPiTest_q <= X20dto0_uid106_fxpX_uid41_fpCosPiTest_b & leftShiftStage0Idx1Pad16_uid105_fxpX_uid41_fpCosPiTest_q;
--cst01pWShift_uid14_fpCosPiTest(CONSTANT,13)
cst01pWShift_uid14_fpCosPiTest_q <= "0000000000000";
--VCC(CONSTANT,1)
VCC_q <= "1";
--fracX_uid7_fpCosPiTest(BITSELECT,6)@0
fracX_uid7_fpCosPiTest_in <= a(22 downto 0);
fracX_uid7_fpCosPiTest_b <= fracX_uid7_fpCosPiTest_in(22 downto 0);
--oFracX_uid37_uid37_fpCosPiTest(BITJOIN,36)@0
oFracX_uid37_uid37_fpCosPiTest_q <= VCC_q & fracX_uid7_fpCosPiTest_b;
--oFracXExt_uid39_fpCosPiTest(BITJOIN,38)@0
oFracXExt_uid39_fpCosPiTest_q <= cst01pWShift_uid14_fpCosPiTest_q & oFracX_uid37_uid37_fpCosPiTest_q;
--biasMwShiftMO_uid13_fpCosPiTest(CONSTANT,12)
biasMwShiftMO_uid13_fpCosPiTest_q <= "01110010";
--expX_uid6_fpCosPiTest(BITSELECT,5)@0
expX_uid6_fpCosPiTest_in <= a(30 downto 0);
expX_uid6_fpCosPiTest_b <= expX_uid6_fpCosPiTest_in(30 downto 23);
--shiftValFxPX_uid38_fpCosPiTest(SUB,37)@0
shiftValFxPX_uid38_fpCosPiTest_a <= STD_LOGIC_VECTOR("0" & expX_uid6_fpCosPiTest_b);
shiftValFxPX_uid38_fpCosPiTest_b <= STD_LOGIC_VECTOR("0" & biasMwShiftMO_uid13_fpCosPiTest_q);
shiftValFxPX_uid38_fpCosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(shiftValFxPX_uid38_fpCosPiTest_a) - UNSIGNED(shiftValFxPX_uid38_fpCosPiTest_b));
shiftValFxPX_uid38_fpCosPiTest_q <= shiftValFxPX_uid38_fpCosPiTest_o(8 downto 0);
--fxpShifterBits_uid40_fpCosPiTest(BITSELECT,39)@0
fxpShifterBits_uid40_fpCosPiTest_in <= shiftValFxPX_uid38_fpCosPiTest_q(5 downto 0);
fxpShifterBits_uid40_fpCosPiTest_b <= fxpShifterBits_uid40_fpCosPiTest_in(5 downto 0);
--leftShiftStageSel5Dto4_uid112_fxpX_uid41_fpCosPiTest(BITSELECT,111)@0
leftShiftStageSel5Dto4_uid112_fxpX_uid41_fpCosPiTest_in <= fxpShifterBits_uid40_fpCosPiTest_b;
leftShiftStageSel5Dto4_uid112_fxpX_uid41_fpCosPiTest_b <= leftShiftStageSel5Dto4_uid112_fxpX_uid41_fpCosPiTest_in(5 downto 4);
--leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest(MUX,112)@0
leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_s <= leftShiftStageSel5Dto4_uid112_fxpX_uid41_fpCosPiTest_b;
leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest: PROCESS (leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_s, en, oFracXExt_uid39_fpCosPiTest_q, leftShiftStage0Idx1_uid107_fxpX_uid41_fpCosPiTest_q, leftShiftStage0Idx2_uid110_fxpX_uid41_fpCosPiTest_q, leftShiftStage0Idx3_uid111_fxpX_uid41_fpCosPiTest_q)
BEGIN
CASE leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_s IS
WHEN "00" => leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_q <= oFracXExt_uid39_fpCosPiTest_q;
WHEN "01" => leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_q <= leftShiftStage0Idx1_uid107_fxpX_uid41_fpCosPiTest_q;
WHEN "10" => leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_q <= leftShiftStage0Idx2_uid110_fxpX_uid41_fpCosPiTest_q;
WHEN "11" => leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_q <= leftShiftStage0Idx3_uid111_fxpX_uid41_fpCosPiTest_q;
WHEN OTHERS => leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage024dto0_uid121_fxpX_uid41_fpCosPiTest(BITSELECT,120)@0
LeftShiftStage024dto0_uid121_fxpX_uid41_fpCosPiTest_in <= leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_q(24 downto 0);
LeftShiftStage024dto0_uid121_fxpX_uid41_fpCosPiTest_b <= LeftShiftStage024dto0_uid121_fxpX_uid41_fpCosPiTest_in(24 downto 0);
--leftShiftStage1Idx3Pad12_uid120_fxpX_uid41_fpCosPiTest(CONSTANT,119)
leftShiftStage1Idx3Pad12_uid120_fxpX_uid41_fpCosPiTest_q <= "000000000000";
--leftShiftStage1Idx3_uid122_fxpX_uid41_fpCosPiTest(BITJOIN,121)@0
leftShiftStage1Idx3_uid122_fxpX_uid41_fpCosPiTest_q <= LeftShiftStage024dto0_uid121_fxpX_uid41_fpCosPiTest_b & leftShiftStage1Idx3Pad12_uid120_fxpX_uid41_fpCosPiTest_q;
--reg_leftShiftStage1Idx3_uid122_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_5(REG,235)@0
reg_leftShiftStage1Idx3_uid122_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx3_uid122_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_5_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx3_uid122_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_5_q <= leftShiftStage1Idx3_uid122_fxpX_uid41_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage028dto0_uid118_fxpX_uid41_fpCosPiTest(BITSELECT,117)@0
LeftShiftStage028dto0_uid118_fxpX_uid41_fpCosPiTest_in <= leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_q(28 downto 0);
LeftShiftStage028dto0_uid118_fxpX_uid41_fpCosPiTest_b <= LeftShiftStage028dto0_uid118_fxpX_uid41_fpCosPiTest_in(28 downto 0);
--cstAllZWE_uid21_fpCosPiTest(CONSTANT,20)
cstAllZWE_uid21_fpCosPiTest_q <= "00000000";
--leftShiftStage1Idx2_uid119_fxpX_uid41_fpCosPiTest(BITJOIN,118)@0
leftShiftStage1Idx2_uid119_fxpX_uid41_fpCosPiTest_q <= LeftShiftStage028dto0_uid118_fxpX_uid41_fpCosPiTest_b & cstAllZWE_uid21_fpCosPiTest_q;
--reg_leftShiftStage1Idx2_uid119_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_4(REG,234)@0
reg_leftShiftStage1Idx2_uid119_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx2_uid119_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_4_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx2_uid119_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_4_q <= leftShiftStage1Idx2_uid119_fxpX_uid41_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage032dto0_uid115_fxpX_uid41_fpCosPiTest(BITSELECT,114)@0
LeftShiftStage032dto0_uid115_fxpX_uid41_fpCosPiTest_in <= leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_q(32 downto 0);
LeftShiftStage032dto0_uid115_fxpX_uid41_fpCosPiTest_b <= LeftShiftStage032dto0_uid115_fxpX_uid41_fpCosPiTest_in(32 downto 0);
--leftShiftStage1Idx1Pad4_uid114_fxpX_uid41_fpCosPiTest(CONSTANT,113)
leftShiftStage1Idx1Pad4_uid114_fxpX_uid41_fpCosPiTest_q <= "0000";
--leftShiftStage1Idx1_uid116_fxpX_uid41_fpCosPiTest(BITJOIN,115)@0
leftShiftStage1Idx1_uid116_fxpX_uid41_fpCosPiTest_q <= LeftShiftStage032dto0_uid115_fxpX_uid41_fpCosPiTest_b & leftShiftStage1Idx1Pad4_uid114_fxpX_uid41_fpCosPiTest_q;
--reg_leftShiftStage1Idx1_uid116_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_3(REG,233)@0
reg_leftShiftStage1Idx1_uid116_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx1_uid116_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_3_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx1_uid116_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_3_q <= leftShiftStage1Idx1_uid116_fxpX_uid41_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--reg_leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_2(REG,232)@0
reg_leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_2_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_2_q <= leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel3Dto2_uid123_fxpX_uid41_fpCosPiTest(BITSELECT,122)@0
leftShiftStageSel3Dto2_uid123_fxpX_uid41_fpCosPiTest_in <= fxpShifterBits_uid40_fpCosPiTest_b(3 downto 0);
leftShiftStageSel3Dto2_uid123_fxpX_uid41_fpCosPiTest_b <= leftShiftStageSel3Dto2_uid123_fxpX_uid41_fpCosPiTest_in(3 downto 2);
--reg_leftShiftStageSel3Dto2_uid123_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_1(REG,231)@0
reg_leftShiftStageSel3Dto2_uid123_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel3Dto2_uid123_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel3Dto2_uid123_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_1_q <= leftShiftStageSel3Dto2_uid123_fxpX_uid41_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest(MUX,123)@1
leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_s <= reg_leftShiftStageSel3Dto2_uid123_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_1_q;
leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest: PROCESS (leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_s, en, reg_leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_2_q, reg_leftShiftStage1Idx1_uid116_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_3_q, reg_leftShiftStage1Idx2_uid119_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_4_q, reg_leftShiftStage1Idx3_uid122_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_5_q)
BEGIN
CASE leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_s IS
WHEN "00" => leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_q <= reg_leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_2_q;
WHEN "01" => leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_q <= reg_leftShiftStage1Idx1_uid116_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_3_q;
WHEN "10" => leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_q <= reg_leftShiftStage1Idx2_uid119_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_4_q;
WHEN "11" => leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_q <= reg_leftShiftStage1Idx3_uid122_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_5_q;
WHEN OTHERS => leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--leftShiftStageSel1Dto0_uid134_fxpX_uid41_fpCosPiTest(BITSELECT,133)@0
leftShiftStageSel1Dto0_uid134_fxpX_uid41_fpCosPiTest_in <= fxpShifterBits_uid40_fpCosPiTest_b(1 downto 0);
leftShiftStageSel1Dto0_uid134_fxpX_uid41_fpCosPiTest_b <= leftShiftStageSel1Dto0_uid134_fxpX_uid41_fpCosPiTest_in(1 downto 0);
--reg_leftShiftStageSel1Dto0_uid134_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest_1(REG,236)@0
reg_leftShiftStageSel1Dto0_uid134_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel1Dto0_uid134_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel1Dto0_uid134_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest_1_q <= leftShiftStageSel1Dto0_uid134_fxpX_uid41_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest(MUX,134)@1
leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest_s <= reg_leftShiftStageSel1Dto0_uid134_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest_1_q;
leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest: PROCESS (leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest_s, en, leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_q, leftShiftStage2Idx1_uid127_fxpX_uid41_fpCosPiTest_q, leftShiftStage2Idx2_uid130_fxpX_uid41_fpCosPiTest_q, leftShiftStage2Idx3_uid133_fxpX_uid41_fpCosPiTest_q)
BEGIN
CASE leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest_s IS
WHEN "00" => leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest_q <= leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_q;
WHEN "01" => leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest_q <= leftShiftStage2Idx1_uid127_fxpX_uid41_fpCosPiTest_q;
WHEN "10" => leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest_q <= leftShiftStage2Idx2_uid130_fxpX_uid41_fpCosPiTest_q;
WHEN "11" => leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest_q <= leftShiftStage2Idx3_uid133_fxpX_uid41_fpCosPiTest_q;
WHEN OTHERS => leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--fxpXFrac_uid43_fpCosPiTest(BITSELECT,42)@1
fxpXFrac_uid43_fpCosPiTest_in <= leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest_q(35 downto 0);
fxpXFrac_uid43_fpCosPiTest_b <= fxpXFrac_uid43_fpCosPiTest_in(35 downto 0);
--FxpXFrac35_uid44_fpCosPiTest(BITSELECT,43)@1
FxpXFrac35_uid44_fpCosPiTest_in <= fxpXFrac_uid43_fpCosPiTest_b;
FxpXFrac35_uid44_fpCosPiTest_b <= FxpXFrac35_uid44_fpCosPiTest_in(35 downto 35);
--FxpX36_uid42_fpCosPiTest(BITSELECT,41)@1
FxpX36_uid42_fpCosPiTest_in <= leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest_q;
FxpX36_uid42_fpCosPiTest_b <= FxpX36_uid42_fpCosPiTest_in(36 downto 36);
--xParityXorHalfParity_uid96_fpCosPiTest(LOGICAL,95)@1
xParityXorHalfParity_uid96_fpCosPiTest_a <= FxpX36_uid42_fpCosPiTest_b;
xParityXorHalfParity_uid96_fpCosPiTest_b <= FxpXFrac35_uid44_fpCosPiTest_b;
xParityXorHalfParity_uid96_fpCosPiTest_q <= xParityXorHalfParity_uid96_fpCosPiTest_a xor xParityXorHalfParity_uid96_fpCosPiTest_b;
--ld_xParityXorHalfParity_uid96_fpCosPiTest_q_to_signRComp_uid99_fpCosPiTest_c(DELAY,369)@1
ld_xParityXorHalfParity_uid96_fpCosPiTest_q_to_signRComp_uid99_fpCosPiTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => xParityXorHalfParity_uid96_fpCosPiTest_q, xout => ld_xParityXorHalfParity_uid96_fpCosPiTest_q_to_signRComp_uid99_fpCosPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--cstBiasPwF_uid12_fpCosPiTest(CONSTANT,11)
cstBiasPwF_uid12_fpCosPiTest_q <= "10010110";
--xEvenInt_uid35_fpCosPiTest(COMPARE,34)@0
xEvenInt_uid35_fpCosPiTest_cin <= GND_q;
xEvenInt_uid35_fpCosPiTest_a <= STD_LOGIC_VECTOR("00" & cstBiasPwF_uid12_fpCosPiTest_q) & '0';
xEvenInt_uid35_fpCosPiTest_b <= STD_LOGIC_VECTOR("00" & expX_uid6_fpCosPiTest_b) & xEvenInt_uid35_fpCosPiTest_cin(0);
xEvenInt_uid35_fpCosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(xEvenInt_uid35_fpCosPiTest_a) - UNSIGNED(xEvenInt_uid35_fpCosPiTest_b));
xEvenInt_uid35_fpCosPiTest_c(0) <= xEvenInt_uid35_fpCosPiTest_o(10);
--ld_xEvenInt_uid35_fpCosPiTest_c_to_evenIntCosNotOneFZ_uid79_fpCosPiTest_a(DELAY,335)@0
ld_xEvenInt_uid35_fpCosPiTest_c_to_evenIntCosNotOneFZ_uid79_fpCosPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => xEvenInt_uid35_fpCosPiTest_c, xout => ld_xEvenInt_uid35_fpCosPiTest_c_to_evenIntCosNotOneFZ_uid79_fpCosPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--InvXEvenInt_uid81_fpCosPiTest(LOGICAL,80)@2
InvXEvenInt_uid81_fpCosPiTest_a <= ld_xEvenInt_uid35_fpCosPiTest_c_to_evenIntCosNotOneFZ_uid79_fpCosPiTest_a_q;
InvXEvenInt_uid81_fpCosPiTest_q <= not InvXEvenInt_uid81_fpCosPiTest_a;
--cosXIsOne_uid36_fpCosPiTest(COMPARE,35)@0
cosXIsOne_uid36_fpCosPiTest_cin <= GND_q;
cosXIsOne_uid36_fpCosPiTest_a <= STD_LOGIC_VECTOR("00" & expX_uid6_fpCosPiTest_b) & '0';
cosXIsOne_uid36_fpCosPiTest_b <= STD_LOGIC_VECTOR("00" & biasMwShiftMO_uid13_fpCosPiTest_q) & cosXIsOne_uid36_fpCosPiTest_cin(0);
cosXIsOne_uid36_fpCosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(cosXIsOne_uid36_fpCosPiTest_a) - UNSIGNED(cosXIsOne_uid36_fpCosPiTest_b));
cosXIsOne_uid36_fpCosPiTest_c(0) <= cosXIsOne_uid36_fpCosPiTest_o(10);
--ld_cosXIsOne_uid36_fpCosPiTest_c_to_InvCosXIsOne_uid77_fpCosPiTest_a(DELAY,332)@0
ld_cosXIsOne_uid36_fpCosPiTest_c_to_InvCosXIsOne_uid77_fpCosPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => cosXIsOne_uid36_fpCosPiTest_c, xout => ld_cosXIsOne_uid36_fpCosPiTest_c_to_InvCosXIsOne_uid77_fpCosPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--InvCosXIsOne_uid77_fpCosPiTest(LOGICAL,76)@2
InvCosXIsOne_uid77_fpCosPiTest_a <= ld_cosXIsOne_uid36_fpCosPiTest_c_to_InvCosXIsOne_uid77_fpCosPiTest_a_q;
InvCosXIsOne_uid77_fpCosPiTest_q <= not InvCosXIsOne_uid77_fpCosPiTest_a;
--signRComp_uid99_fpCosPiTest(LOGICAL,98)@2
signRComp_uid99_fpCosPiTest_a <= InvCosXIsOne_uid77_fpCosPiTest_q;
signRComp_uid99_fpCosPiTest_b <= InvXEvenInt_uid81_fpCosPiTest_q;
signRComp_uid99_fpCosPiTest_c <= ld_xParityXorHalfParity_uid96_fpCosPiTest_q_to_signRComp_uid99_fpCosPiTest_c_q;
signRComp_uid99_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
signRComp_uid99_fpCosPiTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1' AND en = "1") THEN
signRComp_uid99_fpCosPiTest_q <= signRComp_uid99_fpCosPiTest_a and signRComp_uid99_fpCosPiTest_b and signRComp_uid99_fpCosPiTest_c;
END IF;
END PROCESS;
--cstZwSwF_uid15_fpCosPiTest(CONSTANT,14)
cstZwSwF_uid15_fpCosPiTest_q <= "00000000000000000000000000000000000";
--cstHalfwSwFP1_uid18_fpCosPiTest(BITJOIN,17)@2
cstHalfwSwFP1_uid18_fpCosPiTest_q <= VCC_q & cstZwSwF_uid15_fpCosPiTest_q;
--reg_fxpXFrac_uid43_fpCosPiTest_0_to_fxpXFracZero_uid45_fpCosPiTest_1(REG,237)@1
reg_fxpXFrac_uid43_fpCosPiTest_0_to_fxpXFracZero_uid45_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fxpXFrac_uid43_fpCosPiTest_0_to_fxpXFracZero_uid45_fpCosPiTest_1_q <= "000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fxpXFrac_uid43_fpCosPiTest_0_to_fxpXFracZero_uid45_fpCosPiTest_1_q <= fxpXFrac_uid43_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--fxpXFracHalf_uid46_fpCosPiTest(LOGICAL,45)@2
fxpXFracHalf_uid46_fpCosPiTest_a <= reg_fxpXFrac_uid43_fpCosPiTest_0_to_fxpXFracZero_uid45_fpCosPiTest_1_q;
fxpXFracHalf_uid46_fpCosPiTest_b <= cstHalfwSwFP1_uid18_fpCosPiTest_q;
fxpXFracHalf_uid46_fpCosPiTest_q <= "1" when fxpXFracHalf_uid46_fpCosPiTest_a = fxpXFracHalf_uid46_fpCosPiTest_b else "0";
--ld_fxpXFracHalf_uid46_fpCosPiTest_q_to_InvFxpXFracHalf_uid100_fpCosPiTest_a(DELAY,370)@2
ld_fxpXFracHalf_uid46_fpCosPiTest_q_to_InvFxpXFracHalf_uid100_fpCosPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => fxpXFracHalf_uid46_fpCosPiTest_q, xout => ld_fxpXFracHalf_uid46_fpCosPiTest_q_to_InvFxpXFracHalf_uid100_fpCosPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--InvFxpXFracHalf_uid100_fpCosPiTest(LOGICAL,99)@3
InvFxpXFracHalf_uid100_fpCosPiTest_a <= ld_fxpXFracHalf_uid46_fpCosPiTest_q_to_InvFxpXFracHalf_uid100_fpCosPiTest_a_q;
InvFxpXFracHalf_uid100_fpCosPiTest_q <= not InvFxpXFracHalf_uid100_fpCosPiTest_a;
--signR_uid101_fpCosPiTest(LOGICAL,100)@3
signR_uid101_fpCosPiTest_a <= InvFxpXFracHalf_uid100_fpCosPiTest_q;
signR_uid101_fpCosPiTest_b <= signRComp_uid99_fpCosPiTest_q;
signR_uid101_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
signR_uid101_fpCosPiTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1' AND en = "1") THEN
signR_uid101_fpCosPiTest_q <= signR_uid101_fpCosPiTest_a and signR_uid101_fpCosPiTest_b;
END IF;
END PROCESS;
--ld_signR_uid101_fpCosPiTest_q_to_R_uid102_fpCosPiTest_c(DELAY,375)@4
ld_signR_uid101_fpCosPiTest_q_to_R_uid102_fpCosPiTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 13 )
PORT MAP ( xin => signR_uid101_fpCosPiTest_q, xout => ld_signR_uid101_fpCosPiTest_q_to_R_uid102_fpCosPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--cstBias_uid10_fpCosPiTest(CONSTANT,9)
cstBias_uid10_fpCosPiTest_q <= "01111111";
--cstAllOWE_uid8_fpCosPiTest(CONSTANT,7)
cstAllOWE_uid8_fpCosPiTest_q <= "11111111";
--pad_o_uid16_uid47_fpCosPiTest(BITJOIN,46)@1
pad_o_uid16_uid47_fpCosPiTest_q <= VCC_q & STD_LOGIC_VECTOR((35 downto 1 => GND_q(0)) & GND_q);
--reg_pad_o_uid16_uid47_fpCosPiTest_0_to_oMFxpXFrac_uid47_fpCosPiTest_0(REG,244)@1
reg_pad_o_uid16_uid47_fpCosPiTest_0_to_oMFxpXFrac_uid47_fpCosPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_o_uid16_uid47_fpCosPiTest_0_to_oMFxpXFrac_uid47_fpCosPiTest_0_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_o_uid16_uid47_fpCosPiTest_0_to_oMFxpXFrac_uid47_fpCosPiTest_0_q <= pad_o_uid16_uid47_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--oMFxpXFrac_uid47_fpCosPiTest(SUB,47)@2
oMFxpXFrac_uid47_fpCosPiTest_a <= STD_LOGIC_VECTOR("0" & reg_pad_o_uid16_uid47_fpCosPiTest_0_to_oMFxpXFrac_uid47_fpCosPiTest_0_q);
oMFxpXFrac_uid47_fpCosPiTest_b <= STD_LOGIC_VECTOR("00" & reg_fxpXFrac_uid43_fpCosPiTest_0_to_fxpXFracZero_uid45_fpCosPiTest_1_q);
oMFxpXFrac_uid47_fpCosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(oMFxpXFrac_uid47_fpCosPiTest_a) - UNSIGNED(oMFxpXFrac_uid47_fpCosPiTest_b));
oMFxpXFrac_uid47_fpCosPiTest_q <= oMFxpXFrac_uid47_fpCosPiTest_o(37 downto 0);
--oMFxpXFrac_uid49_fpCosPiTest(BITSELECT,48)@2
oMFxpXFrac_uid49_fpCosPiTest_in <= oMFxpXFrac_uid47_fpCosPiTest_q(35 downto 0);
oMFxpXFrac_uid49_fpCosPiTest_b <= oMFxpXFrac_uid49_fpCosPiTest_in(35 downto 0);
--ld_fxpXFrac_uid43_fpCosPiTest_b_to_rangeReducedFxPX_uid51_fpCosPiTest_c(DELAY,308)@1
ld_fxpXFrac_uid43_fpCosPiTest_b_to_rangeReducedFxPX_uid51_fpCosPiTest_c : dspba_delay
GENERIC MAP ( width => 36, depth => 1 )
PORT MAP ( xin => fxpXFrac_uid43_fpCosPiTest_b, xout => ld_fxpXFrac_uid43_fpCosPiTest_b_to_rangeReducedFxPX_uid51_fpCosPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--ld_FxpXFrac35_uid44_fpCosPiTest_b_to_rangeReducedFxPX_uid51_fpCosPiTest_b(DELAY,307)@1
ld_FxpXFrac35_uid44_fpCosPiTest_b_to_rangeReducedFxPX_uid51_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => FxpXFrac35_uid44_fpCosPiTest_b, xout => ld_FxpXFrac35_uid44_fpCosPiTest_b_to_rangeReducedFxPX_uid51_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--rangeReducedFxPX_uid51_fpCosPiTest(MUX,50)@2
rangeReducedFxPX_uid51_fpCosPiTest_s <= ld_FxpXFrac35_uid44_fpCosPiTest_b_to_rangeReducedFxPX_uid51_fpCosPiTest_b_q;
rangeReducedFxPX_uid51_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
rangeReducedFxPX_uid51_fpCosPiTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE rangeReducedFxPX_uid51_fpCosPiTest_s IS
WHEN "0" => rangeReducedFxPX_uid51_fpCosPiTest_q <= ld_fxpXFrac_uid43_fpCosPiTest_b_to_rangeReducedFxPX_uid51_fpCosPiTest_c_q;
WHEN "1" => rangeReducedFxPX_uid51_fpCosPiTest_q <= oMFxpXFrac_uid49_fpCosPiTest_b;
WHEN OTHERS => rangeReducedFxPX_uid51_fpCosPiTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--pad_half_uid17_uid52_fpCosPiTest(BITJOIN,51)@2
pad_half_uid17_uid52_fpCosPiTest_q <= VCC_q & STD_LOGIC_VECTOR((34 downto 1 => GND_q(0)) & GND_q);
--reg_pad_half_uid17_uid52_fpCosPiTest_0_to_z_halfMRRFxPXE_uid52_fpCosPiTest_0(REG,246)@2
reg_pad_half_uid17_uid52_fpCosPiTest_0_to_z_halfMRRFxPXE_uid52_fpCosPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_half_uid17_uid52_fpCosPiTest_0_to_z_halfMRRFxPXE_uid52_fpCosPiTest_0_q <= "000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_half_uid17_uid52_fpCosPiTest_0_to_z_halfMRRFxPXE_uid52_fpCosPiTest_0_q <= pad_half_uid17_uid52_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--z_halfMRRFxPXE_uid52_fpCosPiTest(SUB,52)@3
z_halfMRRFxPXE_uid52_fpCosPiTest_a <= STD_LOGIC_VECTOR("0" & reg_pad_half_uid17_uid52_fpCosPiTest_0_to_z_halfMRRFxPXE_uid52_fpCosPiTest_0_q);
z_halfMRRFxPXE_uid52_fpCosPiTest_b <= STD_LOGIC_VECTOR("0" & rangeReducedFxPX_uid51_fpCosPiTest_q);
z_halfMRRFxPXE_uid52_fpCosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(z_halfMRRFxPXE_uid52_fpCosPiTest_a) - UNSIGNED(z_halfMRRFxPXE_uid52_fpCosPiTest_b));
z_halfMRRFxPXE_uid52_fpCosPiTest_q <= z_halfMRRFxPXE_uid52_fpCosPiTest_o(36 downto 0);
--z_uid54_fpCosPiTest(BITSELECT,53)@3
z_uid54_fpCosPiTest_in <= z_halfMRRFxPXE_uid52_fpCosPiTest_q(34 downto 0);
z_uid54_fpCosPiTest_b <= z_uid54_fpCosPiTest_in(34 downto 0);
--zAddr_uid62_fpCosPiTest(BITSELECT,61)@3
zAddr_uid62_fpCosPiTest_in <= z_uid54_fpCosPiTest_b;
zAddr_uid62_fpCosPiTest_b <= zAddr_uid62_fpCosPiTest_in(34 downto 28);
--reg_zAddr_uid62_fpCosPiTest_0_to_memoryC2_uid209_sinPiZTableGenerator_0(REG,263)@3
reg_zAddr_uid62_fpCosPiTest_0_to_memoryC2_uid209_sinPiZTableGenerator_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_zAddr_uid62_fpCosPiTest_0_to_memoryC2_uid209_sinPiZTableGenerator_0_q <= "0000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_zAddr_uid62_fpCosPiTest_0_to_memoryC2_uid209_sinPiZTableGenerator_0_q <= zAddr_uid62_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--memoryC2_uid209_sinPiZTableGenerator(LOOKUP,208)@4
memoryC2_uid209_sinPiZTableGenerator: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
memoryC2_uid209_sinPiZTableGenerator_q <= "10101101010011";
ELSIF (clk'EVENT AND clk = '1' AND en = "1") THEN
CASE (reg_zAddr_uid62_fpCosPiTest_0_to_memoryC2_uid209_sinPiZTableGenerator_0_q) IS
WHEN "0000000" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101101010011";
WHEN "0000001" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101101010100";
WHEN "0000010" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101101010111";
WHEN "0000011" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101101011001";
WHEN "0000100" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101101011011";
WHEN "0000101" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101101011100";
WHEN "0000110" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101101011111";
WHEN "0000111" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101101100010";
WHEN "0001000" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101101100110";
WHEN "0001001" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101101101011";
WHEN "0001010" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101101110000";
WHEN "0001011" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101101110101";
WHEN "0001100" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101101111011";
WHEN "0001101" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101110000000";
WHEN "0001110" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101110000111";
WHEN "0001111" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101110001110";
WHEN "0010000" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101110010011";
WHEN "0010001" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101110011110";
WHEN "0010010" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101110100110";
WHEN "0010011" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101110101111";
WHEN "0010100" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101110111000";
WHEN "0010101" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101111000011";
WHEN "0010110" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101111001100";
WHEN "0010111" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101111010111";
WHEN "0011000" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101111100011";
WHEN "0011001" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101111101110";
WHEN "0011010" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101111111011";
WHEN "0011011" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110000001001";
WHEN "0011100" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110000010101";
WHEN "0011101" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110000100000";
WHEN "0011110" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110000110001";
WHEN "0011111" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110001000000";
WHEN "0100000" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110001001101";
WHEN "0100001" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110001011110";
WHEN "0100010" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110001101100";
WHEN "0100011" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110001111111";
WHEN "0100100" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110010001111";
WHEN "0100101" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110010100001";
WHEN "0100110" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110010110011";
WHEN "0100111" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110011000101";
WHEN "0101000" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110011010110";
WHEN "0101001" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110011101011";
WHEN "0101010" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110011111111";
WHEN "0101011" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110100010010";
WHEN "0101100" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110100100101";
WHEN "0101101" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110100111011";
WHEN "0101110" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110101001110";
WHEN "0101111" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110101100111";
WHEN "0110000" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110101111100";
WHEN "0110001" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110110010010";
WHEN "0110010" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110110100110";
WHEN "0110011" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110111000000";
WHEN "0110100" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110111010101";
WHEN "0110101" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110111110000";
WHEN "0110110" => memoryC2_uid209_sinPiZTableGenerator_q <= "10111000000110";
WHEN "0110111" => memoryC2_uid209_sinPiZTableGenerator_q <= "10111000100010";
WHEN "0111000" => memoryC2_uid209_sinPiZTableGenerator_q <= "10111000111001";
WHEN "0111001" => memoryC2_uid209_sinPiZTableGenerator_q <= "10111001010100";
WHEN "0111010" => memoryC2_uid209_sinPiZTableGenerator_q <= "10111001101111";
WHEN "0111011" => memoryC2_uid209_sinPiZTableGenerator_q <= "10111010001001";
WHEN "0111100" => memoryC2_uid209_sinPiZTableGenerator_q <= "10111010100011";
WHEN "0111101" => memoryC2_uid209_sinPiZTableGenerator_q <= "10111010111100";
WHEN "0111110" => memoryC2_uid209_sinPiZTableGenerator_q <= "10111011011001";
WHEN "0111111" => memoryC2_uid209_sinPiZTableGenerator_q <= "10111011110111";
WHEN "1000000" => memoryC2_uid209_sinPiZTableGenerator_q <= "10111100010100";
WHEN "1000001" => memoryC2_uid209_sinPiZTableGenerator_q <= "10111100110001";
WHEN "1000010" => memoryC2_uid209_sinPiZTableGenerator_q <= "10111101001101";
WHEN "1000011" => memoryC2_uid209_sinPiZTableGenerator_q <= "10111101101010";
WHEN "1000100" => memoryC2_uid209_sinPiZTableGenerator_q <= "10111110001000";
WHEN "1000101" => memoryC2_uid209_sinPiZTableGenerator_q <= "10111110100101";
WHEN "1000110" => memoryC2_uid209_sinPiZTableGenerator_q <= "10111111000101";
WHEN "1000111" => memoryC2_uid209_sinPiZTableGenerator_q <= "10111111100011";
WHEN "1001000" => memoryC2_uid209_sinPiZTableGenerator_q <= "11000000000011";
WHEN "1001001" => memoryC2_uid209_sinPiZTableGenerator_q <= "11000000100011";
WHEN "1001010" => memoryC2_uid209_sinPiZTableGenerator_q <= "11000001000100";
WHEN "1001011" => memoryC2_uid209_sinPiZTableGenerator_q <= "11000001100010";
WHEN "1001100" => memoryC2_uid209_sinPiZTableGenerator_q <= "11000010000100";
WHEN "1001101" => memoryC2_uid209_sinPiZTableGenerator_q <= "11000010100010";
WHEN "1001110" => memoryC2_uid209_sinPiZTableGenerator_q <= "11000011000110";
WHEN "1001111" => memoryC2_uid209_sinPiZTableGenerator_q <= "11000011101000";
WHEN "1010000" => memoryC2_uid209_sinPiZTableGenerator_q <= "11000100001010";
WHEN "1010001" => memoryC2_uid209_sinPiZTableGenerator_q <= "11000100101101";
WHEN "1010010" => memoryC2_uid209_sinPiZTableGenerator_q <= "11000101010001";
WHEN "1010011" => memoryC2_uid209_sinPiZTableGenerator_q <= "11000101110010";
WHEN "1010100" => memoryC2_uid209_sinPiZTableGenerator_q <= "11000110010100";
WHEN "1010101" => memoryC2_uid209_sinPiZTableGenerator_q <= "11000110111011";
WHEN "1010110" => memoryC2_uid209_sinPiZTableGenerator_q <= "11000111011010";
WHEN "1010111" => memoryC2_uid209_sinPiZTableGenerator_q <= "11001000000001";
WHEN "1011000" => memoryC2_uid209_sinPiZTableGenerator_q <= "11001000100110";
WHEN "1011001" => memoryC2_uid209_sinPiZTableGenerator_q <= "11001001001011";
WHEN "1011010" => memoryC2_uid209_sinPiZTableGenerator_q <= "11001001101101";
WHEN "1011011" => memoryC2_uid209_sinPiZTableGenerator_q <= "11001010010101";
WHEN "1011100" => memoryC2_uid209_sinPiZTableGenerator_q <= "11001010111100";
WHEN "1011101" => memoryC2_uid209_sinPiZTableGenerator_q <= "11001011100000";
WHEN "1011110" => memoryC2_uid209_sinPiZTableGenerator_q <= "11001100000101";
WHEN "1011111" => memoryC2_uid209_sinPiZTableGenerator_q <= "11001100101110";
WHEN "1100000" => memoryC2_uid209_sinPiZTableGenerator_q <= "11001101010100";
WHEN "1100001" => memoryC2_uid209_sinPiZTableGenerator_q <= "11001101111010";
WHEN "1100010" => memoryC2_uid209_sinPiZTableGenerator_q <= "11001110100010";
WHEN "1100011" => memoryC2_uid209_sinPiZTableGenerator_q <= "11001111001001";
WHEN "1100100" => memoryC2_uid209_sinPiZTableGenerator_q <= "11001111110001";
WHEN "1100101" => memoryC2_uid209_sinPiZTableGenerator_q <= "11010000010110";
WHEN "1100110" => memoryC2_uid209_sinPiZTableGenerator_q <= "11010000111111";
WHEN "1100111" => memoryC2_uid209_sinPiZTableGenerator_q <= "11010001101001";
WHEN "1101000" => memoryC2_uid209_sinPiZTableGenerator_q <= "11010010010010";
WHEN "1101001" => memoryC2_uid209_sinPiZTableGenerator_q <= "11010010111101";
WHEN "1101010" => memoryC2_uid209_sinPiZTableGenerator_q <= "11010011100001";
WHEN "1101011" => memoryC2_uid209_sinPiZTableGenerator_q <= "11010100001100";
WHEN "1101100" => memoryC2_uid209_sinPiZTableGenerator_q <= "11010100110111";
WHEN "1101101" => memoryC2_uid209_sinPiZTableGenerator_q <= "11010101100001";
WHEN "1101110" => memoryC2_uid209_sinPiZTableGenerator_q <= "11010110001011";
WHEN "1101111" => memoryC2_uid209_sinPiZTableGenerator_q <= "11010110110011";
WHEN "1110000" => memoryC2_uid209_sinPiZTableGenerator_q <= "11010111011111";
WHEN "1110001" => memoryC2_uid209_sinPiZTableGenerator_q <= "11011000001010";
WHEN "1110010" => memoryC2_uid209_sinPiZTableGenerator_q <= "11011000110100";
WHEN "1110011" => memoryC2_uid209_sinPiZTableGenerator_q <= "11011001011111";
WHEN "1110100" => memoryC2_uid209_sinPiZTableGenerator_q <= "11011010001010";
WHEN "1110101" => memoryC2_uid209_sinPiZTableGenerator_q <= "11011010110110";
WHEN "1110110" => memoryC2_uid209_sinPiZTableGenerator_q <= "11011011100011";
WHEN "1110111" => memoryC2_uid209_sinPiZTableGenerator_q <= "11011100001111";
WHEN "1111000" => memoryC2_uid209_sinPiZTableGenerator_q <= "11011100111001";
WHEN "1111001" => memoryC2_uid209_sinPiZTableGenerator_q <= "11011101100011";
WHEN "1111010" => memoryC2_uid209_sinPiZTableGenerator_q <= "11011110010001";
WHEN "1111011" => memoryC2_uid209_sinPiZTableGenerator_q <= "11011110111011";
WHEN "1111100" => memoryC2_uid209_sinPiZTableGenerator_q <= "11011111101000";
WHEN "1111101" => memoryC2_uid209_sinPiZTableGenerator_q <= "11100000010101";
WHEN "1111110" => memoryC2_uid209_sinPiZTableGenerator_q <= "11100001000010";
WHEN "1111111" => memoryC2_uid209_sinPiZTableGenerator_q <= "11100001110000";
WHEN OTHERS =>
memoryC2_uid209_sinPiZTableGenerator_q <= (others => '-');
END CASE;
END IF;
END PROCESS;
--zPPolyEval_uid63_fpCosPiTest(BITSELECT,62)@3
zPPolyEval_uid63_fpCosPiTest_in <= z_uid54_fpCosPiTest_b(27 downto 0);
zPPolyEval_uid63_fpCosPiTest_b <= zPPolyEval_uid63_fpCosPiTest_in(27 downto 12);
--yT1_uid210_sinPiZPolyEval(BITSELECT,209)@3
yT1_uid210_sinPiZPolyEval_in <= zPPolyEval_uid63_fpCosPiTest_b;
yT1_uid210_sinPiZPolyEval_b <= yT1_uid210_sinPiZPolyEval_in(15 downto 2);
--reg_yT1_uid210_sinPiZPolyEval_0_to_prodXY_uid226_pT1_uid211_sinPiZPolyEval_0(REG,264)@3
reg_yT1_uid210_sinPiZPolyEval_0_to_prodXY_uid226_pT1_uid211_sinPiZPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT1_uid210_sinPiZPolyEval_0_to_prodXY_uid226_pT1_uid211_sinPiZPolyEval_0_q <= "00000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT1_uid210_sinPiZPolyEval_0_to_prodXY_uid226_pT1_uid211_sinPiZPolyEval_0_q <= yT1_uid210_sinPiZPolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_reg_yT1_uid210_sinPiZPolyEval_0_to_prodXY_uid226_pT1_uid211_sinPiZPolyEval_0_q_to_prodXY_uid226_pT1_uid211_sinPiZPolyEval_a(DELAY,499)@4
ld_reg_yT1_uid210_sinPiZPolyEval_0_to_prodXY_uid226_pT1_uid211_sinPiZPolyEval_0_q_to_prodXY_uid226_pT1_uid211_sinPiZPolyEval_a : dspba_delay
GENERIC MAP ( width => 14, depth => 1 )
PORT MAP ( xin => reg_yT1_uid210_sinPiZPolyEval_0_to_prodXY_uid226_pT1_uid211_sinPiZPolyEval_0_q, xout => ld_reg_yT1_uid210_sinPiZPolyEval_0_to_prodXY_uid226_pT1_uid211_sinPiZPolyEval_0_q_to_prodXY_uid226_pT1_uid211_sinPiZPolyEval_a_q, ena => en(0), clk => clk, aclr => areset );
--prodXY_uid226_pT1_uid211_sinPiZPolyEval(MULT,225)@5
prodXY_uid226_pT1_uid211_sinPiZPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid226_pT1_uid211_sinPiZPolyEval_a),15)) * SIGNED(prodXY_uid226_pT1_uid211_sinPiZPolyEval_b);
prodXY_uid226_pT1_uid211_sinPiZPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid226_pT1_uid211_sinPiZPolyEval_a <= (others => '0');
prodXY_uid226_pT1_uid211_sinPiZPolyEval_b <= (others => '0');
prodXY_uid226_pT1_uid211_sinPiZPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid226_pT1_uid211_sinPiZPolyEval_a <= ld_reg_yT1_uid210_sinPiZPolyEval_0_to_prodXY_uid226_pT1_uid211_sinPiZPolyEval_0_q_to_prodXY_uid226_pT1_uid211_sinPiZPolyEval_a_q;
prodXY_uid226_pT1_uid211_sinPiZPolyEval_b <= memoryC2_uid209_sinPiZTableGenerator_q;
prodXY_uid226_pT1_uid211_sinPiZPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid226_pT1_uid211_sinPiZPolyEval_pr,28));
END IF;
END IF;
END PROCESS;
prodXY_uid226_pT1_uid211_sinPiZPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid226_pT1_uid211_sinPiZPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid226_pT1_uid211_sinPiZPolyEval_q <= prodXY_uid226_pT1_uid211_sinPiZPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid227_pT1_uid211_sinPiZPolyEval(BITSELECT,226)@8
prodXYTruncFR_uid227_pT1_uid211_sinPiZPolyEval_in <= prodXY_uid226_pT1_uid211_sinPiZPolyEval_q;
prodXYTruncFR_uid227_pT1_uid211_sinPiZPolyEval_b <= prodXYTruncFR_uid227_pT1_uid211_sinPiZPolyEval_in(27 downto 13);
--highBBits_uid213_sinPiZPolyEval(BITSELECT,212)@8
highBBits_uid213_sinPiZPolyEval_in <= prodXYTruncFR_uid227_pT1_uid211_sinPiZPolyEval_b;
highBBits_uid213_sinPiZPolyEval_b <= highBBits_uid213_sinPiZPolyEval_in(14 downto 1);
--ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_notEnable(LOGICAL,557)
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_notEnable_a <= en;
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_notEnable_q <= not ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_notEnable_a;
--ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_nor(LOGICAL,596)
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_nor_a <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_notEnable_q;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_nor_b <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_sticky_ena_q;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_nor_q <= not (ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_nor_a or ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_nor_b);
--ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_mem_top(CONSTANT,592)
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_mem_top_q <= "010";
--ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_cmp(LOGICAL,593)
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_cmp_a <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_mem_top_q;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdmux_q);
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_cmp_q <= "1" when ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_cmp_a = ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_cmp_b else "0";
--ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_cmpReg(REG,594)
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_cmpReg_q <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_sticky_ena(REG,597)
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_nor_q = "1") THEN
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_sticky_ena_q <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_enaAnd(LOGICAL,598)
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_enaAnd_a <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_sticky_ena_q;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_enaAnd_b <= en;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_enaAnd_q <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_enaAnd_a and ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_enaAnd_b;
--ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt(COUNTER,588)
-- every=1, low=0, high=2, step=1, init=1
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt_i <= TO_UNSIGNED(1,2);
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt_i = 1 THEN
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt_eq = '1') THEN
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt_i <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt_i - 2;
ELSE
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt_i <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt_i,2));
--ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdreg(REG,589)
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdreg_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdreg_q <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdmux(MUX,590)
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdmux_s <= en;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdmux: PROCESS (ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdmux_s, ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdreg_q, ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdmux_s IS
WHEN "0" => ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdmux_q <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdreg_q;
WHEN "1" => ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdmux_q <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem(DUALMEM,587)
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_reset0 <= areset;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_ia <= reg_zAddr_uid62_fpCosPiTest_0_to_memoryC2_uid209_sinPiZTableGenerator_0_q;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_aa <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdreg_q;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_ab <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdmux_q;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 7,
widthad_a => 2,
numwords_a => 3,
width_b => 7,
widthad_b => 2,
numwords_b => 3,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_iq,
address_a => ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_aa,
data_a => ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_ia
);
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_q <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_iq(6 downto 0);
--memoryC1_uid208_sinPiZTableGenerator(LOOKUP,207)@8
memoryC1_uid208_sinPiZTableGenerator: PROCESS (ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_q)
BEGIN
-- Begin reserved scope level
CASE (ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_q) IS
WHEN "0000000" => memoryC1_uid208_sinPiZTableGenerator_q <= "000000000000000000001";
WHEN "0000001" => memoryC1_uid208_sinPiZTableGenerator_q <= "111111101011010101010";
WHEN "0000010" => memoryC1_uid208_sinPiZTableGenerator_q <= "111111010110101010001";
WHEN "0000011" => memoryC1_uid208_sinPiZTableGenerator_q <= "111111000001111111100";
WHEN "0000100" => memoryC1_uid208_sinPiZTableGenerator_q <= "111110101101010101010";
WHEN "0000101" => memoryC1_uid208_sinPiZTableGenerator_q <= "111110011000101011101";
WHEN "0000110" => memoryC1_uid208_sinPiZTableGenerator_q <= "111110000100000010101";
WHEN "0000111" => memoryC1_uid208_sinPiZTableGenerator_q <= "111101101111011010001";
WHEN "0001000" => memoryC1_uid208_sinPiZTableGenerator_q <= "111101011010110010101";
WHEN "0001001" => memoryC1_uid208_sinPiZTableGenerator_q <= "111101000110001011111";
WHEN "0001010" => memoryC1_uid208_sinPiZTableGenerator_q <= "111100110001100110010";
WHEN "0001011" => memoryC1_uid208_sinPiZTableGenerator_q <= "111100011101000010000";
WHEN "0001100" => memoryC1_uid208_sinPiZTableGenerator_q <= "111100001000011110111";
WHEN "0001101" => memoryC1_uid208_sinPiZTableGenerator_q <= "111011110011111101011";
WHEN "0001110" => memoryC1_uid208_sinPiZTableGenerator_q <= "111011011111011101011";
WHEN "0001111" => memoryC1_uid208_sinPiZTableGenerator_q <= "111011001010111110111";
WHEN "0010000" => memoryC1_uid208_sinPiZTableGenerator_q <= "111010110110100010101";
WHEN "0010001" => memoryC1_uid208_sinPiZTableGenerator_q <= "111010100010000111100";
WHEN "0010010" => memoryC1_uid208_sinPiZTableGenerator_q <= "111010001101101111000";
WHEN "0010011" => memoryC1_uid208_sinPiZTableGenerator_q <= "111001111001011000011";
WHEN "0010100" => memoryC1_uid208_sinPiZTableGenerator_q <= "111001100101000100010";
WHEN "0010101" => memoryC1_uid208_sinPiZTableGenerator_q <= "111001010000110010001";
WHEN "0010110" => memoryC1_uid208_sinPiZTableGenerator_q <= "111000111100100010111";
WHEN "0010111" => memoryC1_uid208_sinPiZTableGenerator_q <= "111000101000010110001";
WHEN "0011000" => memoryC1_uid208_sinPiZTableGenerator_q <= "111000010100001011111";
WHEN "0011001" => memoryC1_uid208_sinPiZTableGenerator_q <= "111000000000000100110";
WHEN "0011010" => memoryC1_uid208_sinPiZTableGenerator_q <= "110111101100000000011";
WHEN "0011011" => memoryC1_uid208_sinPiZTableGenerator_q <= "110111010111111111000";
WHEN "0011100" => memoryC1_uid208_sinPiZTableGenerator_q <= "110111000100000001000";
WHEN "0011101" => memoryC1_uid208_sinPiZTableGenerator_q <= "110110110000000110101";
WHEN "0011110" => memoryC1_uid208_sinPiZTableGenerator_q <= "110110011100001110111";
WHEN "0011111" => memoryC1_uid208_sinPiZTableGenerator_q <= "110110001000011011000";
WHEN "0100000" => memoryC1_uid208_sinPiZTableGenerator_q <= "110101110100101011010";
WHEN "0100001" => memoryC1_uid208_sinPiZTableGenerator_q <= "110101100000111110101";
WHEN "0100010" => memoryC1_uid208_sinPiZTableGenerator_q <= "110101001101010110010";
WHEN "0100011" => memoryC1_uid208_sinPiZTableGenerator_q <= "110100111001110001011";
WHEN "0100100" => memoryC1_uid208_sinPiZTableGenerator_q <= "110100100110010001001";
WHEN "0100101" => memoryC1_uid208_sinPiZTableGenerator_q <= "110100010010110100110";
WHEN "0100110" => memoryC1_uid208_sinPiZTableGenerator_q <= "110011111111011100110";
WHEN "0100111" => memoryC1_uid208_sinPiZTableGenerator_q <= "110011101100001001010";
WHEN "0101000" => memoryC1_uid208_sinPiZTableGenerator_q <= "110011011000111010011";
WHEN "0101001" => memoryC1_uid208_sinPiZTableGenerator_q <= "110011000101101111111";
WHEN "0101010" => memoryC1_uid208_sinPiZTableGenerator_q <= "110010110010101010010";
WHEN "0101011" => memoryC1_uid208_sinPiZTableGenerator_q <= "110010011111101001101";
WHEN "0101100" => memoryC1_uid208_sinPiZTableGenerator_q <= "110010001100101110000";
WHEN "0101101" => memoryC1_uid208_sinPiZTableGenerator_q <= "110001111001110111001";
WHEN "0101110" => memoryC1_uid208_sinPiZTableGenerator_q <= "110001100111000110000";
WHEN "0101111" => memoryC1_uid208_sinPiZTableGenerator_q <= "110001010100011001011";
WHEN "0110000" => memoryC1_uid208_sinPiZTableGenerator_q <= "110001000001110010110";
WHEN "0110001" => memoryC1_uid208_sinPiZTableGenerator_q <= "110000101111010001100";
WHEN "0110010" => memoryC1_uid208_sinPiZTableGenerator_q <= "110000011100110110001";
WHEN "0110011" => memoryC1_uid208_sinPiZTableGenerator_q <= "110000001010011111111";
WHEN "0110100" => memoryC1_uid208_sinPiZTableGenerator_q <= "101111111000010000000";
WHEN "0110101" => memoryC1_uid208_sinPiZTableGenerator_q <= "101111100110000101100";
WHEN "0110110" => memoryC1_uid208_sinPiZTableGenerator_q <= "101111010100000001100";
WHEN "0110111" => memoryC1_uid208_sinPiZTableGenerator_q <= "101111000010000011001";
WHEN "0111000" => memoryC1_uid208_sinPiZTableGenerator_q <= "101110110000001011100";
WHEN "0111001" => memoryC1_uid208_sinPiZTableGenerator_q <= "101110011110011001110";
WHEN "0111010" => memoryC1_uid208_sinPiZTableGenerator_q <= "101110001100101110101";
WHEN "0111011" => memoryC1_uid208_sinPiZTableGenerator_q <= "101101111011001010001";
WHEN "0111100" => memoryC1_uid208_sinPiZTableGenerator_q <= "101101101001101100010";
WHEN "0111101" => memoryC1_uid208_sinPiZTableGenerator_q <= "101101011000010101010";
WHEN "0111110" => memoryC1_uid208_sinPiZTableGenerator_q <= "101101000111000100101";
WHEN "0111111" => memoryC1_uid208_sinPiZTableGenerator_q <= "101100110101111010111";
WHEN "1000000" => memoryC1_uid208_sinPiZTableGenerator_q <= "101100100100111000010";
WHEN "1000001" => memoryC1_uid208_sinPiZTableGenerator_q <= "101100010011111100111";
WHEN "1000010" => memoryC1_uid208_sinPiZTableGenerator_q <= "101100000011001000111";
WHEN "1000011" => memoryC1_uid208_sinPiZTableGenerator_q <= "101011110010011100000";
WHEN "1000100" => memoryC1_uid208_sinPiZTableGenerator_q <= "101011100001110110100";
WHEN "1000101" => memoryC1_uid208_sinPiZTableGenerator_q <= "101011010001011000100";
WHEN "1000110" => memoryC1_uid208_sinPiZTableGenerator_q <= "101011000001000001110";
WHEN "1000111" => memoryC1_uid208_sinPiZTableGenerator_q <= "101010110000110011000";
WHEN "1001000" => memoryC1_uid208_sinPiZTableGenerator_q <= "101010100000101011111";
WHEN "1001001" => memoryC1_uid208_sinPiZTableGenerator_q <= "101010010000101100100";
WHEN "1001010" => memoryC1_uid208_sinPiZTableGenerator_q <= "101010000000110101001";
WHEN "1001011" => memoryC1_uid208_sinPiZTableGenerator_q <= "101001110001000110000";
WHEN "1001100" => memoryC1_uid208_sinPiZTableGenerator_q <= "101001100001011110101";
WHEN "1001101" => memoryC1_uid208_sinPiZTableGenerator_q <= "101001010001111111111";
WHEN "1001110" => memoryC1_uid208_sinPiZTableGenerator_q <= "101001000010101000110";
WHEN "1001111" => memoryC1_uid208_sinPiZTableGenerator_q <= "101000110011011010001";
WHEN "1010000" => memoryC1_uid208_sinPiZTableGenerator_q <= "101000100100010100001";
WHEN "1010001" => memoryC1_uid208_sinPiZTableGenerator_q <= "101000010101010110100";
WHEN "1010010" => memoryC1_uid208_sinPiZTableGenerator_q <= "101000000110100001011";
WHEN "1010011" => memoryC1_uid208_sinPiZTableGenerator_q <= "100111110111110101011";
WHEN "1010100" => memoryC1_uid208_sinPiZTableGenerator_q <= "100111101001010010000";
WHEN "1010101" => memoryC1_uid208_sinPiZTableGenerator_q <= "100111011010110110110";
WHEN "1010110" => memoryC1_uid208_sinPiZTableGenerator_q <= "100111001100100101100";
WHEN "1010111" => memoryC1_uid208_sinPiZTableGenerator_q <= "100110111110011100011";
WHEN "1011000" => memoryC1_uid208_sinPiZTableGenerator_q <= "100110110000011100011";
WHEN "1011001" => memoryC1_uid208_sinPiZTableGenerator_q <= "100110100010100101110";
WHEN "1011010" => memoryC1_uid208_sinPiZTableGenerator_q <= "100110010100111000101";
WHEN "1011011" => memoryC1_uid208_sinPiZTableGenerator_q <= "100110000111010100001";
WHEN "1011100" => memoryC1_uid208_sinPiZTableGenerator_q <= "100101111001111001000";
WHEN "1011101" => memoryC1_uid208_sinPiZTableGenerator_q <= "100101101100100111111";
WHEN "1011110" => memoryC1_uid208_sinPiZTableGenerator_q <= "100101011111100000000";
WHEN "1011111" => memoryC1_uid208_sinPiZTableGenerator_q <= "100101010010100001001";
WHEN "1100000" => memoryC1_uid208_sinPiZTableGenerator_q <= "100101000101101100011";
WHEN "1100001" => memoryC1_uid208_sinPiZTableGenerator_q <= "100100111001000001011";
WHEN "1100010" => memoryC1_uid208_sinPiZTableGenerator_q <= "100100101100011111111";
WHEN "1100011" => memoryC1_uid208_sinPiZTableGenerator_q <= "100100100000001000010";
WHEN "1100100" => memoryC1_uid208_sinPiZTableGenerator_q <= "100100010011111010101";
WHEN "1100101" => memoryC1_uid208_sinPiZTableGenerator_q <= "100100000111110111001";
WHEN "1100110" => memoryC1_uid208_sinPiZTableGenerator_q <= "100011111011111101010";
WHEN "1100111" => memoryC1_uid208_sinPiZTableGenerator_q <= "100011110000001101010";
WHEN "1101000" => memoryC1_uid208_sinPiZTableGenerator_q <= "100011100100100111101";
WHEN "1101001" => memoryC1_uid208_sinPiZTableGenerator_q <= "100011011001001011111";
WHEN "1101010" => memoryC1_uid208_sinPiZTableGenerator_q <= "100011001101111011010";
WHEN "1101011" => memoryC1_uid208_sinPiZTableGenerator_q <= "100011000010110100001";
WHEN "1101100" => memoryC1_uid208_sinPiZTableGenerator_q <= "100010110111110111010";
WHEN "1101101" => memoryC1_uid208_sinPiZTableGenerator_q <= "100010101101000101000";
WHEN "1101110" => memoryC1_uid208_sinPiZTableGenerator_q <= "100010100010011101001";
WHEN "1101111" => memoryC1_uid208_sinPiZTableGenerator_q <= "100010011000000000001";
WHEN "1110000" => memoryC1_uid208_sinPiZTableGenerator_q <= "100010001101101101010";
WHEN "1110001" => memoryC1_uid208_sinPiZTableGenerator_q <= "100010000011100100111";
WHEN "1110010" => memoryC1_uid208_sinPiZTableGenerator_q <= "100001111001100111100";
WHEN "1110011" => memoryC1_uid208_sinPiZTableGenerator_q <= "100001101111110100101";
WHEN "1110100" => memoryC1_uid208_sinPiZTableGenerator_q <= "100001100110001100100";
WHEN "1110101" => memoryC1_uid208_sinPiZTableGenerator_q <= "100001011100101111001";
WHEN "1110110" => memoryC1_uid208_sinPiZTableGenerator_q <= "100001010011011100011";
WHEN "1110111" => memoryC1_uid208_sinPiZTableGenerator_q <= "100001001010010100101";
WHEN "1111000" => memoryC1_uid208_sinPiZTableGenerator_q <= "100001000001011000000";
WHEN "1111001" => memoryC1_uid208_sinPiZTableGenerator_q <= "100000111000100110100";
WHEN "1111010" => memoryC1_uid208_sinPiZTableGenerator_q <= "100000101111111111100";
WHEN "1111011" => memoryC1_uid208_sinPiZTableGenerator_q <= "100000100111100011111";
WHEN "1111100" => memoryC1_uid208_sinPiZTableGenerator_q <= "100000011111010011000";
WHEN "1111101" => memoryC1_uid208_sinPiZTableGenerator_q <= "100000010111001101010";
WHEN "1111110" => memoryC1_uid208_sinPiZTableGenerator_q <= "100000001111010010101";
WHEN "1111111" => memoryC1_uid208_sinPiZTableGenerator_q <= "100000000111100011001";
WHEN OTHERS =>
memoryC1_uid208_sinPiZTableGenerator_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--sumAHighB_uid214_sinPiZPolyEval(ADD,213)@8
sumAHighB_uid214_sinPiZPolyEval_a <= STD_LOGIC_VECTOR((21 downto 21 => memoryC1_uid208_sinPiZTableGenerator_q(20)) & memoryC1_uid208_sinPiZTableGenerator_q);
sumAHighB_uid214_sinPiZPolyEval_b <= STD_LOGIC_VECTOR((21 downto 14 => highBBits_uid213_sinPiZPolyEval_b(13)) & highBBits_uid213_sinPiZPolyEval_b);
sumAHighB_uid214_sinPiZPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid214_sinPiZPolyEval_a) + SIGNED(sumAHighB_uid214_sinPiZPolyEval_b));
sumAHighB_uid214_sinPiZPolyEval_q <= sumAHighB_uid214_sinPiZPolyEval_o(21 downto 0);
--lowRangeB_uid212_sinPiZPolyEval(BITSELECT,211)@8
lowRangeB_uid212_sinPiZPolyEval_in <= prodXYTruncFR_uid227_pT1_uid211_sinPiZPolyEval_b(0 downto 0);
lowRangeB_uid212_sinPiZPolyEval_b <= lowRangeB_uid212_sinPiZPolyEval_in(0 downto 0);
--s1_uid212_uid215_sinPiZPolyEval(BITJOIN,214)@8
s1_uid212_uid215_sinPiZPolyEval_q <= sumAHighB_uid214_sinPiZPolyEval_q & lowRangeB_uid212_sinPiZPolyEval_b;
--reg_s1_uid212_uid215_sinPiZPolyEval_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_1(REG,267)@8
reg_s1_uid212_uid215_sinPiZPolyEval_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_s1_uid212_uid215_sinPiZPolyEval_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_1_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_s1_uid212_uid215_sinPiZPolyEval_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_1_q <= s1_uid212_uid215_sinPiZPolyEval_q;
END IF;
END IF;
END PROCESS;
--ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_nor(LOGICAL,609)
ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_nor_a <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_notEnable_q;
ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_nor_b <= ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_sticky_ena_q;
ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_nor_q <= not (ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_nor_a or ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_nor_b);
--ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_sticky_ena(REG,610)
ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_nor_q = "1") THEN
ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_sticky_ena_q <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_enaAnd(LOGICAL,611)
ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_enaAnd_a <= ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_sticky_ena_q;
ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_enaAnd_b <= en;
ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_enaAnd_q <= ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_enaAnd_a and ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_enaAnd_b;
--ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_inputreg(DELAY,599)
ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 16, depth => 1 )
PORT MAP ( xin => zPPolyEval_uid63_fpCosPiTest_b, xout => ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem(DUALMEM,600)
ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_reset0 <= areset;
ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_ia <= ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_inputreg_q;
ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_aa <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdreg_q;
ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_ab <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdmux_q;
ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 16,
widthad_a => 2,
numwords_a => 3,
width_b => 16,
widthad_b => 2,
numwords_b => 3,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_iq,
address_a => ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_aa,
data_a => ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_ia
);
ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_q <= ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_iq(15 downto 0);
--reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0(REG,266)@8
reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_q <= ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--prodXY_uid229_pT2_uid217_sinPiZPolyEval(MULT,228)@9
prodXY_uid229_pT2_uid217_sinPiZPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid229_pT2_uid217_sinPiZPolyEval_a),17)) * SIGNED(prodXY_uid229_pT2_uid217_sinPiZPolyEval_b);
prodXY_uid229_pT2_uid217_sinPiZPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid229_pT2_uid217_sinPiZPolyEval_a <= (others => '0');
prodXY_uid229_pT2_uid217_sinPiZPolyEval_b <= (others => '0');
prodXY_uid229_pT2_uid217_sinPiZPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid229_pT2_uid217_sinPiZPolyEval_a <= reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_q;
prodXY_uid229_pT2_uid217_sinPiZPolyEval_b <= reg_s1_uid212_uid215_sinPiZPolyEval_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_1_q;
prodXY_uid229_pT2_uid217_sinPiZPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid229_pT2_uid217_sinPiZPolyEval_pr,39));
END IF;
END IF;
END PROCESS;
prodXY_uid229_pT2_uid217_sinPiZPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid229_pT2_uid217_sinPiZPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid229_pT2_uid217_sinPiZPolyEval_q <= prodXY_uid229_pT2_uid217_sinPiZPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid230_pT2_uid217_sinPiZPolyEval(BITSELECT,229)@12
prodXYTruncFR_uid230_pT2_uid217_sinPiZPolyEval_in <= prodXY_uid229_pT2_uid217_sinPiZPolyEval_q;
prodXYTruncFR_uid230_pT2_uid217_sinPiZPolyEval_b <= prodXYTruncFR_uid230_pT2_uid217_sinPiZPolyEval_in(38 downto 15);
--highBBits_uid219_sinPiZPolyEval(BITSELECT,218)@12
highBBits_uid219_sinPiZPolyEval_in <= prodXYTruncFR_uid230_pT2_uid217_sinPiZPolyEval_b;
highBBits_uid219_sinPiZPolyEval_b <= highBBits_uid219_sinPiZPolyEval_in(23 downto 2);
--ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_nor(LOGICAL,584)
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_nor_a <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_notEnable_q;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_nor_b <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_sticky_ena_q;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_nor_q <= not (ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_nor_a or ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_nor_b);
--ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_mem_top(CONSTANT,554)
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_mem_top_q <= "0110";
--ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_cmp(LOGICAL,555)
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_cmp_a <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_mem_top_q;
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdmux_q);
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_cmp_q <= "1" when ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_cmp_a = ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_cmp_b else "0";
--ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_cmpReg(REG,556)
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_cmpReg_q <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_sticky_ena(REG,585)
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_nor_q = "1") THEN
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_sticky_ena_q <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_enaAnd(LOGICAL,586)
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_enaAnd_a <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_sticky_ena_q;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_enaAnd_b <= en;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_enaAnd_q <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_enaAnd_a and ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_enaAnd_b;
--ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt(COUNTER,550)
-- every=1, low=0, high=6, step=1, init=1
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt_i = 5 THEN
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt_eq <= '1';
ELSE
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt_eq = '1') THEN
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt_i <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt_i - 6;
ELSE
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt_i <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt_i,3));
--ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdreg(REG,551)
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdreg_q <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdmux(MUX,552)
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdmux_s <= en;
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdmux: PROCESS (ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdmux_s, ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdreg_q, ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt_q)
BEGIN
CASE ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdmux_s IS
WHEN "0" => ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdmux_q <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdreg_q;
WHEN "1" => ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdmux_q <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem(DUALMEM,575)
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_reset0 <= areset;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_ia <= reg_zAddr_uid62_fpCosPiTest_0_to_memoryC2_uid209_sinPiZTableGenerator_0_q;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_aa <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdreg_q;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_ab <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdmux_q;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 7,
widthad_a => 3,
numwords_a => 7,
width_b => 7,
widthad_b => 3,
numwords_b => 7,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_iq,
address_a => ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_aa,
data_a => ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_ia
);
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_q <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_iq(6 downto 0);
--memoryC0_uid207_sinPiZTableGenerator(LOOKUP,206)@12
memoryC0_uid207_sinPiZTableGenerator: PROCESS (ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_q)
BEGIN
-- Begin reserved scope level
CASE (ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_q) IS
WHEN "0000000" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100100100001111110110101110";
WHEN "0000001" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100100100001110100100000010";
WHEN "0000010" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100100100001010101100000000";
WHEN "0000011" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100100100000100001110101000";
WHEN "0000100" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100100011111011001011111101";
WHEN "0000101" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100100011101111100100000010";
WHEN "0000110" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100100011100001010110111011";
WHEN "0000111" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100100011010000100100101111";
WHEN "0001000" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100100010111101001101100010";
WHEN "0001001" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100100010100111010001011101";
WHEN "0001010" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100100010001110110000100111";
WHEN "0001011" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100100001110011101011001001";
WHEN "0001100" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100100001010110000001001110";
WHEN "0001101" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100100000110101110011000000";
WHEN "0001110" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100100000010011000000101011";
WHEN "0001111" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100011111101101101010011101";
WHEN "0010000" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100011111000101110000100010";
WHEN "0010001" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100011110011011010011001011";
WHEN "0010010" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100011101101110010010100101";
WHEN "0010011" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100011100111110101111000011";
WHEN "0010100" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100011100001100101000110101";
WHEN "0010101" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100011011011000000000001111";
WHEN "0010110" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100011010100000110101100011";
WHEN "0010111" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100011001100111001001000110";
WHEN "0011000" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100011000101010111011001110";
WHEN "0011001" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100010111101100001100010000";
WHEN "0011010" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100010110101010111100100100";
WHEN "0011011" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100010101100111001100100010";
WHEN "0011100" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100010100100000111100100011";
WHEN "0011101" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100010011011000001101000000";
WHEN "0011110" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100010010001100111110010110";
WHEN "0011111" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100010000111111010000111111";
WHEN "0100000" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100001111101111000101010111";
WHEN "0100001" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100001110011100011011111110";
WHEN "0100010" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100001101000111010101010001";
WHEN "0100011" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100001011101111110001110000";
WHEN "0100100" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100001010010101110001111010";
WHEN "0100101" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100001000111001010110010010";
WHEN "0100110" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100000111011010011111011001";
WHEN "0100111" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100000101111001001101110010";
WHEN "0101000" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100000100010101100010000001";
WHEN "0101001" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100000010101111011100101011";
WHEN "0101010" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100000001000110111110010101";
WHEN "0101011" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011111111011100000111100110";
WHEN "0101100" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011111101101110111001000101";
WHEN "0101101" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011111011111111010011011011";
WHEN "0101110" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011111010001101010111001111";
WHEN "0101111" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011111000011001000101001110";
WHEN "0110000" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011110110100010011110000000";
WHEN "0110001" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011110100101001100010010010";
WHEN "0110010" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011110010101110010010110000";
WHEN "0110011" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011110000110000110000001000";
WHEN "0110100" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011101110110000111011000111";
WHEN "0110101" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011101100101110110100011101";
WHEN "0110110" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011101010101010011100111001";
WHEN "0110111" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011101000100011110101001100";
WHEN "0111000" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011100110011010111110000111";
WHEN "0111001" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011100100001111111000011101";
WHEN "0111010" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011100010000010100101000000";
WHEN "0111011" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011011111110011000100100100";
WHEN "0111100" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011011101100001010111111110";
WHEN "0111101" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011011011001101100000000011";
WHEN "0111110" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011011000110111011101101010";
WHEN "0111111" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011010110011111010001101001";
WHEN "1000000" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011010100000100111100111000";
WHEN "1000001" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011010001101000100000001111";
WHEN "1000010" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011001111001001111100100111";
WHEN "1000011" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011001100101001010010111011";
WHEN "1000100" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011001010000110100100000101";
WHEN "1000101" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011000111100001110001000001";
WHEN "1000110" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011000100111010111010101011";
WHEN "1000111" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011000010010010000001111111";
WHEN "1001000" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010111111100111000111111011";
WHEN "1001001" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010111100111010001101011110";
WHEN "1001010" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010111010001011010011100110";
WHEN "1001011" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010110111011010011011010011";
WHEN "1001100" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010110100100111100101100110";
WHEN "1001101" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010110001110010110011011111";
WHEN "1001110" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010101110111100000110000001";
WHEN "1001111" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010101100000011011110001110";
WHEN "1010000" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010101001001000111101001000";
WHEN "1010001" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010100110001100100011110100";
WHEN "1010010" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010100011001110010011010110";
WHEN "1010011" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010100000001110001100110010";
WHEN "1010100" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010011101001100010001001111";
WHEN "1010101" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010011010001000100001110100";
WHEN "1010110" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010010111000010111111100101";
WHEN "1010111" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010010011111011101011101100";
WHEN "1011000" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010010000110010100111010001";
WHEN "1011001" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010001101100111110011011011";
WHEN "1011010" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010001010011011010001010100";
WHEN "1011011" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010000111001101000010000111";
WHEN "1011100" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010000011111101000110111110";
WHEN "1011101" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010000000101011100001000010";
WHEN "1011110" => memoryC0_uid207_sinPiZTableGenerator_q <= "01001111101011000010001100001";
WHEN "1011111" => memoryC0_uid207_sinPiZTableGenerator_q <= "01001111010000011011001100111";
WHEN "1100000" => memoryC0_uid207_sinPiZTableGenerator_q <= "01001110110101100111010011111";
WHEN "1100001" => memoryC0_uid207_sinPiZTableGenerator_q <= "01001110011010100110101010111";
WHEN "1100010" => memoryC0_uid207_sinPiZTableGenerator_q <= "01001101111111011001011011101";
WHEN "1100011" => memoryC0_uid207_sinPiZTableGenerator_q <= "01001101100011111111101111111";
WHEN "1100100" => memoryC0_uid207_sinPiZTableGenerator_q <= "01001101001000011001110001011";
WHEN "1100101" => memoryC0_uid207_sinPiZTableGenerator_q <= "01001100101100100111101010001";
WHEN "1100110" => memoryC0_uid207_sinPiZTableGenerator_q <= "01001100010000101001100100001";
WHEN "1100111" => memoryC0_uid207_sinPiZTableGenerator_q <= "01001011110100011111101001011";
WHEN "1101000" => memoryC0_uid207_sinPiZTableGenerator_q <= "01001011011000001010000011111";
WHEN "1101001" => memoryC0_uid207_sinPiZTableGenerator_q <= "01001010111011101000111101111";
WHEN "1101010" => memoryC0_uid207_sinPiZTableGenerator_q <= "01001010011110111100100001011";
WHEN "1101011" => memoryC0_uid207_sinPiZTableGenerator_q <= "01001010000010000100111000111";
WHEN "1101100" => memoryC0_uid207_sinPiZTableGenerator_q <= "01001001100101000010001110101";
WHEN "1101101" => memoryC0_uid207_sinPiZTableGenerator_q <= "01001001000111110100101100111";
WHEN "1101110" => memoryC0_uid207_sinPiZTableGenerator_q <= "01001000101010011100011110001";
WHEN "1101111" => memoryC0_uid207_sinPiZTableGenerator_q <= "01001000001100111001101100110";
WHEN "1110000" => memoryC0_uid207_sinPiZTableGenerator_q <= "01000111101111001100100011011";
WHEN "1110001" => memoryC0_uid207_sinPiZTableGenerator_q <= "01000111010001010101001100101";
WHEN "1110010" => memoryC0_uid207_sinPiZTableGenerator_q <= "01000110110011010011110010111";
WHEN "1110011" => memoryC0_uid207_sinPiZTableGenerator_q <= "01000110010101001000100001000";
WHEN "1110100" => memoryC0_uid207_sinPiZTableGenerator_q <= "01000101110110110011100001101";
WHEN "1110101" => memoryC0_uid207_sinPiZTableGenerator_q <= "01000101011000010100111111100";
WHEN "1110110" => memoryC0_uid207_sinPiZTableGenerator_q <= "01000100111001101101000101100";
WHEN "1110111" => memoryC0_uid207_sinPiZTableGenerator_q <= "01000100011010111011111110011";
WHEN "1111000" => memoryC0_uid207_sinPiZTableGenerator_q <= "01000011111100000001110101000";
WHEN "1111001" => memoryC0_uid207_sinPiZTableGenerator_q <= "01000011011100111110110100010";
WHEN "1111010" => memoryC0_uid207_sinPiZTableGenerator_q <= "01000010111101110011000111010";
WHEN "1111011" => memoryC0_uid207_sinPiZTableGenerator_q <= "01000010011110011110111000111";
WHEN "1111100" => memoryC0_uid207_sinPiZTableGenerator_q <= "01000001111111000010010100010";
WHEN "1111101" => memoryC0_uid207_sinPiZTableGenerator_q <= "01000001011111011101100100011";
WHEN "1111110" => memoryC0_uid207_sinPiZTableGenerator_q <= "01000000111111110000110100011";
WHEN "1111111" => memoryC0_uid207_sinPiZTableGenerator_q <= "01000000011111111100001111011";
WHEN OTHERS =>
memoryC0_uid207_sinPiZTableGenerator_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--sumAHighB_uid220_sinPiZPolyEval(ADD,219)@12
sumAHighB_uid220_sinPiZPolyEval_a <= STD_LOGIC_VECTOR((29 downto 29 => memoryC0_uid207_sinPiZTableGenerator_q(28)) & memoryC0_uid207_sinPiZTableGenerator_q);
sumAHighB_uid220_sinPiZPolyEval_b <= STD_LOGIC_VECTOR((29 downto 22 => highBBits_uid219_sinPiZPolyEval_b(21)) & highBBits_uid219_sinPiZPolyEval_b);
sumAHighB_uid220_sinPiZPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid220_sinPiZPolyEval_a) + SIGNED(sumAHighB_uid220_sinPiZPolyEval_b));
sumAHighB_uid220_sinPiZPolyEval_q <= sumAHighB_uid220_sinPiZPolyEval_o(29 downto 0);
--lowRangeB_uid218_sinPiZPolyEval(BITSELECT,217)@12
lowRangeB_uid218_sinPiZPolyEval_in <= prodXYTruncFR_uid230_pT2_uid217_sinPiZPolyEval_b(1 downto 0);
lowRangeB_uid218_sinPiZPolyEval_b <= lowRangeB_uid218_sinPiZPolyEval_in(1 downto 0);
--s2_uid218_uid221_sinPiZPolyEval(BITJOIN,220)@12
s2_uid218_uid221_sinPiZPolyEval_q <= sumAHighB_uid220_sinPiZPolyEval_q & lowRangeB_uid218_sinPiZPolyEval_b;
--fxpSinRes_uid65_fpCosPiTest(BITSELECT,64)@12
fxpSinRes_uid65_fpCosPiTest_in <= s2_uid218_uid221_sinPiZPolyEval_q(29 downto 0);
fxpSinRes_uid65_fpCosPiTest_b <= fxpSinRes_uid65_fpCosPiTest_in(29 downto 5);
--reg_fxpSinRes_uid65_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_1(REG,270)@12
reg_fxpSinRes_uid65_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fxpSinRes_uid65_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_1_q <= "0000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fxpSinRes_uid65_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_1_q <= fxpSinRes_uid65_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_nor(LOGICAL,622)
ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_nor_a <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_notEnable_q;
ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_nor_b <= ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_sticky_ena_q;
ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_nor_q <= not (ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_nor_a or ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_nor_b);
--ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_sticky_ena(REG,623)
ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_nor_q = "1") THEN
ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_sticky_ena_q <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_enaAnd(LOGICAL,624)
ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_enaAnd_a <= ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_sticky_ena_q;
ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_enaAnd_b <= en;
ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_enaAnd_q <= ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_enaAnd_a and ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_enaAnd_b;
--LeftShiftStage131dto0_uid202_alignedZ_uid57_fpCosPiTest(BITSELECT,201)@7
LeftShiftStage131dto0_uid202_alignedZ_uid57_fpCosPiTest_in <= leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_q(31 downto 0);
LeftShiftStage131dto0_uid202_alignedZ_uid57_fpCosPiTest_b <= LeftShiftStage131dto0_uid202_alignedZ_uid57_fpCosPiTest_in(31 downto 0);
--leftShiftStage2Idx3_uid203_alignedZ_uid57_fpCosPiTest(BITJOIN,202)@7
leftShiftStage2Idx3_uid203_alignedZ_uid57_fpCosPiTest_q <= LeftShiftStage131dto0_uid202_alignedZ_uid57_fpCosPiTest_b & leftShiftStage2Idx3Pad3_uid131_fxpX_uid41_fpCosPiTest_q;
--LeftShiftStage132dto0_uid199_alignedZ_uid57_fpCosPiTest(BITSELECT,198)@7
LeftShiftStage132dto0_uid199_alignedZ_uid57_fpCosPiTest_in <= leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_q(32 downto 0);
LeftShiftStage132dto0_uid199_alignedZ_uid57_fpCosPiTest_b <= LeftShiftStage132dto0_uid199_alignedZ_uid57_fpCosPiTest_in(32 downto 0);
--leftShiftStage2Idx2_uid200_alignedZ_uid57_fpCosPiTest(BITJOIN,199)@7
leftShiftStage2Idx2_uid200_alignedZ_uid57_fpCosPiTest_q <= LeftShiftStage132dto0_uid199_alignedZ_uid57_fpCosPiTest_b & leftShiftStage2Idx2Pad2_uid128_fxpX_uid41_fpCosPiTest_q;
--LeftShiftStage133dto0_uid196_alignedZ_uid57_fpCosPiTest(BITSELECT,195)@7
LeftShiftStage133dto0_uid196_alignedZ_uid57_fpCosPiTest_in <= leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_q(33 downto 0);
LeftShiftStage133dto0_uid196_alignedZ_uid57_fpCosPiTest_b <= LeftShiftStage133dto0_uid196_alignedZ_uid57_fpCosPiTest_in(33 downto 0);
--leftShiftStage2Idx1_uid197_alignedZ_uid57_fpCosPiTest(BITJOIN,196)@7
leftShiftStage2Idx1_uid197_alignedZ_uid57_fpCosPiTest_q <= LeftShiftStage133dto0_uid196_alignedZ_uid57_fpCosPiTest_b & GND_q;
--vStage_uid141_lzcZ_uid56_fpCosPiTest(BITSELECT,140)@3
vStage_uid141_lzcZ_uid56_fpCosPiTest_in <= z_uid54_fpCosPiTest_b(2 downto 0);
vStage_uid141_lzcZ_uid56_fpCosPiTest_b <= vStage_uid141_lzcZ_uid56_fpCosPiTest_in(2 downto 0);
--ld_vStage_uid141_lzcZ_uid56_fpCosPiTest_b_to_leftShiftStage0Idx2_uid180_alignedZ_uid57_fpCosPiTest_b(DELAY,450)@3
ld_vStage_uid141_lzcZ_uid56_fpCosPiTest_b_to_leftShiftStage0Idx2_uid180_alignedZ_uid57_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 3, depth => 3 )
PORT MAP ( xin => vStage_uid141_lzcZ_uid56_fpCosPiTest_b, xout => ld_vStage_uid141_lzcZ_uid56_fpCosPiTest_b_to_leftShiftStage0Idx2_uid180_alignedZ_uid57_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage0Idx2_uid180_alignedZ_uid57_fpCosPiTest(BITJOIN,179)@6
leftShiftStage0Idx2_uid180_alignedZ_uid57_fpCosPiTest_q <= ld_vStage_uid141_lzcZ_uid56_fpCosPiTest_b_to_leftShiftStage0Idx2_uid180_alignedZ_uid57_fpCosPiTest_b_q & leftShiftStage0Idx2Pad32_uid108_fxpX_uid41_fpCosPiTest_q;
--X18dto0_uid176_alignedZ_uid57_fpCosPiTest(BITSELECT,175)@3
X18dto0_uid176_alignedZ_uid57_fpCosPiTest_in <= z_uid54_fpCosPiTest_b(18 downto 0);
X18dto0_uid176_alignedZ_uid57_fpCosPiTest_b <= X18dto0_uid176_alignedZ_uid57_fpCosPiTest_in(18 downto 0);
--ld_X18dto0_uid176_alignedZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx1_uid177_alignedZ_uid57_fpCosPiTest_b_inputreg(DELAY,573)
ld_X18dto0_uid176_alignedZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx1_uid177_alignedZ_uid57_fpCosPiTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 19, depth => 1 )
PORT MAP ( xin => X18dto0_uid176_alignedZ_uid57_fpCosPiTest_b, xout => ld_X18dto0_uid176_alignedZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx1_uid177_alignedZ_uid57_fpCosPiTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_X18dto0_uid176_alignedZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx1_uid177_alignedZ_uid57_fpCosPiTest_b(DELAY,449)@3
ld_X18dto0_uid176_alignedZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx1_uid177_alignedZ_uid57_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 19, depth => 2 )
PORT MAP ( xin => ld_X18dto0_uid176_alignedZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx1_uid177_alignedZ_uid57_fpCosPiTest_b_inputreg_q, xout => ld_X18dto0_uid176_alignedZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx1_uid177_alignedZ_uid57_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage0Idx1_uid177_alignedZ_uid57_fpCosPiTest(BITJOIN,176)@6
leftShiftStage0Idx1_uid177_alignedZ_uid57_fpCosPiTest_q <= ld_X18dto0_uid176_alignedZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx1_uid177_alignedZ_uid57_fpCosPiTest_b_q & leftShiftStage0Idx1Pad16_uid105_fxpX_uid41_fpCosPiTest_q;
--ld_z_uid54_fpCosPiTest_b_to_leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_c_inputreg(DELAY,574)
ld_z_uid54_fpCosPiTest_b_to_leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 35, depth => 1 )
PORT MAP ( xin => z_uid54_fpCosPiTest_b, xout => ld_z_uid54_fpCosPiTest_b_to_leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_z_uid54_fpCosPiTest_b_to_leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_c(DELAY,453)@3
ld_z_uid54_fpCosPiTest_b_to_leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_c : dspba_delay
GENERIC MAP ( width => 35, depth => 2 )
PORT MAP ( xin => ld_z_uid54_fpCosPiTest_b_to_leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_c_inputreg_q, xout => ld_z_uid54_fpCosPiTest_b_to_leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--rVStage_uid138_lzcZ_uid56_fpCosPiTest(BITSELECT,137)@3
rVStage_uid138_lzcZ_uid56_fpCosPiTest_in <= z_uid54_fpCosPiTest_b;
rVStage_uid138_lzcZ_uid56_fpCosPiTest_b <= rVStage_uid138_lzcZ_uid56_fpCosPiTest_in(34 downto 3);
--reg_rVStage_uid138_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid139_lzcZ_uid56_fpCosPiTest_1(REG,247)@3
reg_rVStage_uid138_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid139_lzcZ_uid56_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid138_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid139_lzcZ_uid56_fpCosPiTest_1_q <= "00000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid138_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid139_lzcZ_uid56_fpCosPiTest_1_q <= rVStage_uid138_lzcZ_uid56_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid139_lzcZ_uid56_fpCosPiTest(LOGICAL,138)@4
vCount_uid139_lzcZ_uid56_fpCosPiTest_a <= reg_rVStage_uid138_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid139_lzcZ_uid56_fpCosPiTest_1_q;
vCount_uid139_lzcZ_uid56_fpCosPiTest_b <= leftShiftStage0Idx2Pad32_uid108_fxpX_uid41_fpCosPiTest_q;
vCount_uid139_lzcZ_uid56_fpCosPiTest_q <= "1" when vCount_uid139_lzcZ_uid56_fpCosPiTest_a = vCount_uid139_lzcZ_uid56_fpCosPiTest_b else "0";
--ld_vCount_uid139_lzcZ_uid56_fpCosPiTest_q_to_r_uid172_lzcZ_uid56_fpCosPiTest_f(DELAY,447)@4
ld_vCount_uid139_lzcZ_uid56_fpCosPiTest_q_to_r_uid172_lzcZ_uid56_fpCosPiTest_f : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => vCount_uid139_lzcZ_uid56_fpCosPiTest_q, xout => ld_vCount_uid139_lzcZ_uid56_fpCosPiTest_q_to_r_uid172_lzcZ_uid56_fpCosPiTest_f_q, ena => en(0), clk => clk, aclr => areset );
--mO_uid140_lzcZ_uid56_fpCosPiTest(CONSTANT,139)
mO_uid140_lzcZ_uid56_fpCosPiTest_q <= "11111111111111111111111111111";
--cStage_uid142_lzcZ_uid56_fpCosPiTest(BITJOIN,141)@3
cStage_uid142_lzcZ_uid56_fpCosPiTest_q <= vStage_uid141_lzcZ_uid56_fpCosPiTest_b & mO_uid140_lzcZ_uid56_fpCosPiTest_q;
--reg_cStage_uid142_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid144_lzcZ_uid56_fpCosPiTest_3(REG,249)@3
reg_cStage_uid142_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid144_lzcZ_uid56_fpCosPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cStage_uid142_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid144_lzcZ_uid56_fpCosPiTest_3_q <= "00000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cStage_uid142_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid144_lzcZ_uid56_fpCosPiTest_3_q <= cStage_uid142_lzcZ_uid56_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--vStagei_uid144_lzcZ_uid56_fpCosPiTest(MUX,143)@4
vStagei_uid144_lzcZ_uid56_fpCosPiTest_s <= vCount_uid139_lzcZ_uid56_fpCosPiTest_q;
vStagei_uid144_lzcZ_uid56_fpCosPiTest: PROCESS (vStagei_uid144_lzcZ_uid56_fpCosPiTest_s, en, reg_rVStage_uid138_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid139_lzcZ_uid56_fpCosPiTest_1_q, reg_cStage_uid142_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid144_lzcZ_uid56_fpCosPiTest_3_q)
BEGIN
CASE vStagei_uid144_lzcZ_uid56_fpCosPiTest_s IS
WHEN "0" => vStagei_uid144_lzcZ_uid56_fpCosPiTest_q <= reg_rVStage_uid138_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid139_lzcZ_uid56_fpCosPiTest_1_q;
WHEN "1" => vStagei_uid144_lzcZ_uid56_fpCosPiTest_q <= reg_cStage_uid142_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid144_lzcZ_uid56_fpCosPiTest_3_q;
WHEN OTHERS => vStagei_uid144_lzcZ_uid56_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid146_lzcZ_uid56_fpCosPiTest(BITSELECT,145)@4
rVStage_uid146_lzcZ_uid56_fpCosPiTest_in <= vStagei_uid144_lzcZ_uid56_fpCosPiTest_q;
rVStage_uid146_lzcZ_uid56_fpCosPiTest_b <= rVStage_uid146_lzcZ_uid56_fpCosPiTest_in(31 downto 16);
--reg_rVStage_uid146_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid147_lzcZ_uid56_fpCosPiTest_1(REG,250)@4
reg_rVStage_uid146_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid147_lzcZ_uid56_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid146_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid147_lzcZ_uid56_fpCosPiTest_1_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid146_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid147_lzcZ_uid56_fpCosPiTest_1_q <= rVStage_uid146_lzcZ_uid56_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid147_lzcZ_uid56_fpCosPiTest(LOGICAL,146)@5
vCount_uid147_lzcZ_uid56_fpCosPiTest_a <= reg_rVStage_uid146_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid147_lzcZ_uid56_fpCosPiTest_1_q;
vCount_uid147_lzcZ_uid56_fpCosPiTest_b <= leftShiftStage0Idx1Pad16_uid105_fxpX_uid41_fpCosPiTest_q;
vCount_uid147_lzcZ_uid56_fpCosPiTest_q <= "1" when vCount_uid147_lzcZ_uid56_fpCosPiTest_a = vCount_uid147_lzcZ_uid56_fpCosPiTest_b else "0";
--ld_vCount_uid147_lzcZ_uid56_fpCosPiTest_q_to_r_uid172_lzcZ_uid56_fpCosPiTest_e(DELAY,446)@5
ld_vCount_uid147_lzcZ_uid56_fpCosPiTest_q_to_r_uid172_lzcZ_uid56_fpCosPiTest_e : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vCount_uid147_lzcZ_uid56_fpCosPiTest_q, xout => ld_vCount_uid147_lzcZ_uid56_fpCosPiTest_q_to_r_uid172_lzcZ_uid56_fpCosPiTest_e_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid148_lzcZ_uid56_fpCosPiTest(BITSELECT,147)@4
vStage_uid148_lzcZ_uid56_fpCosPiTest_in <= vStagei_uid144_lzcZ_uid56_fpCosPiTest_q(15 downto 0);
vStage_uid148_lzcZ_uid56_fpCosPiTest_b <= vStage_uid148_lzcZ_uid56_fpCosPiTest_in(15 downto 0);
--reg_vStage_uid148_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid150_lzcZ_uid56_fpCosPiTest_3(REG,252)@4
reg_vStage_uid148_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid150_lzcZ_uid56_fpCosPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid148_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid150_lzcZ_uid56_fpCosPiTest_3_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid148_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid150_lzcZ_uid56_fpCosPiTest_3_q <= vStage_uid148_lzcZ_uid56_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid150_lzcZ_uid56_fpCosPiTest(MUX,149)@5
vStagei_uid150_lzcZ_uid56_fpCosPiTest_s <= vCount_uid147_lzcZ_uid56_fpCosPiTest_q;
vStagei_uid150_lzcZ_uid56_fpCosPiTest: PROCESS (vStagei_uid150_lzcZ_uid56_fpCosPiTest_s, en, reg_rVStage_uid146_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid147_lzcZ_uid56_fpCosPiTest_1_q, reg_vStage_uid148_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid150_lzcZ_uid56_fpCosPiTest_3_q)
BEGIN
CASE vStagei_uid150_lzcZ_uid56_fpCosPiTest_s IS
WHEN "0" => vStagei_uid150_lzcZ_uid56_fpCosPiTest_q <= reg_rVStage_uid146_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid147_lzcZ_uid56_fpCosPiTest_1_q;
WHEN "1" => vStagei_uid150_lzcZ_uid56_fpCosPiTest_q <= reg_vStage_uid148_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid150_lzcZ_uid56_fpCosPiTest_3_q;
WHEN OTHERS => vStagei_uid150_lzcZ_uid56_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid152_lzcZ_uid56_fpCosPiTest(BITSELECT,151)@5
rVStage_uid152_lzcZ_uid56_fpCosPiTest_in <= vStagei_uid150_lzcZ_uid56_fpCosPiTest_q;
rVStage_uid152_lzcZ_uid56_fpCosPiTest_b <= rVStage_uid152_lzcZ_uid56_fpCosPiTest_in(15 downto 8);
--vCount_uid153_lzcZ_uid56_fpCosPiTest(LOGICAL,152)@5
vCount_uid153_lzcZ_uid56_fpCosPiTest_a <= rVStage_uid152_lzcZ_uid56_fpCosPiTest_b;
vCount_uid153_lzcZ_uid56_fpCosPiTest_b <= cstAllZWE_uid21_fpCosPiTest_q;
vCount_uid153_lzcZ_uid56_fpCosPiTest_q <= "1" when vCount_uid153_lzcZ_uid56_fpCosPiTest_a = vCount_uid153_lzcZ_uid56_fpCosPiTest_b else "0";
--reg_vCount_uid153_lzcZ_uid56_fpCosPiTest_0_to_r_uid172_lzcZ_uid56_fpCosPiTest_3(REG,256)@5
reg_vCount_uid153_lzcZ_uid56_fpCosPiTest_0_to_r_uid172_lzcZ_uid56_fpCosPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid153_lzcZ_uid56_fpCosPiTest_0_to_r_uid172_lzcZ_uid56_fpCosPiTest_3_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid153_lzcZ_uid56_fpCosPiTest_0_to_r_uid172_lzcZ_uid56_fpCosPiTest_3_q <= vCount_uid153_lzcZ_uid56_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--vStage_uid154_lzcZ_uid56_fpCosPiTest(BITSELECT,153)@5
vStage_uid154_lzcZ_uid56_fpCosPiTest_in <= vStagei_uid150_lzcZ_uid56_fpCosPiTest_q(7 downto 0);
vStage_uid154_lzcZ_uid56_fpCosPiTest_b <= vStage_uid154_lzcZ_uid56_fpCosPiTest_in(7 downto 0);
--vStagei_uid156_lzcZ_uid56_fpCosPiTest(MUX,155)@5
vStagei_uid156_lzcZ_uid56_fpCosPiTest_s <= vCount_uid153_lzcZ_uid56_fpCosPiTest_q;
vStagei_uid156_lzcZ_uid56_fpCosPiTest: PROCESS (vStagei_uid156_lzcZ_uid56_fpCosPiTest_s, en, rVStage_uid152_lzcZ_uid56_fpCosPiTest_b, vStage_uid154_lzcZ_uid56_fpCosPiTest_b)
BEGIN
CASE vStagei_uid156_lzcZ_uid56_fpCosPiTest_s IS
WHEN "0" => vStagei_uid156_lzcZ_uid56_fpCosPiTest_q <= rVStage_uid152_lzcZ_uid56_fpCosPiTest_b;
WHEN "1" => vStagei_uid156_lzcZ_uid56_fpCosPiTest_q <= vStage_uid154_lzcZ_uid56_fpCosPiTest_b;
WHEN OTHERS => vStagei_uid156_lzcZ_uid56_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid158_lzcZ_uid56_fpCosPiTest(BITSELECT,157)@5
rVStage_uid158_lzcZ_uid56_fpCosPiTest_in <= vStagei_uid156_lzcZ_uid56_fpCosPiTest_q;
rVStage_uid158_lzcZ_uid56_fpCosPiTest_b <= rVStage_uid158_lzcZ_uid56_fpCosPiTest_in(7 downto 4);
--reg_rVStage_uid158_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid159_lzcZ_uid56_fpCosPiTest_1(REG,253)@5
reg_rVStage_uid158_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid159_lzcZ_uid56_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid158_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid159_lzcZ_uid56_fpCosPiTest_1_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid158_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid159_lzcZ_uid56_fpCosPiTest_1_q <= rVStage_uid158_lzcZ_uid56_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid159_lzcZ_uid56_fpCosPiTest(LOGICAL,158)@6
vCount_uid159_lzcZ_uid56_fpCosPiTest_a <= reg_rVStage_uid158_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid159_lzcZ_uid56_fpCosPiTest_1_q;
vCount_uid159_lzcZ_uid56_fpCosPiTest_b <= leftShiftStage1Idx1Pad4_uid114_fxpX_uid41_fpCosPiTest_q;
vCount_uid159_lzcZ_uid56_fpCosPiTest_q <= "1" when vCount_uid159_lzcZ_uid56_fpCosPiTest_a = vCount_uid159_lzcZ_uid56_fpCosPiTest_b else "0";
--vStage_uid160_lzcZ_uid56_fpCosPiTest(BITSELECT,159)@5
vStage_uid160_lzcZ_uid56_fpCosPiTest_in <= vStagei_uid156_lzcZ_uid56_fpCosPiTest_q(3 downto 0);
vStage_uid160_lzcZ_uid56_fpCosPiTest_b <= vStage_uid160_lzcZ_uid56_fpCosPiTest_in(3 downto 0);
--reg_vStage_uid160_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid162_lzcZ_uid56_fpCosPiTest_3(REG,255)@5
reg_vStage_uid160_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid162_lzcZ_uid56_fpCosPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid160_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid162_lzcZ_uid56_fpCosPiTest_3_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid160_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid162_lzcZ_uid56_fpCosPiTest_3_q <= vStage_uid160_lzcZ_uid56_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid162_lzcZ_uid56_fpCosPiTest(MUX,161)@6
vStagei_uid162_lzcZ_uid56_fpCosPiTest_s <= vCount_uid159_lzcZ_uid56_fpCosPiTest_q;
vStagei_uid162_lzcZ_uid56_fpCosPiTest: PROCESS (vStagei_uid162_lzcZ_uid56_fpCosPiTest_s, en, reg_rVStage_uid158_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid159_lzcZ_uid56_fpCosPiTest_1_q, reg_vStage_uid160_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid162_lzcZ_uid56_fpCosPiTest_3_q)
BEGIN
CASE vStagei_uid162_lzcZ_uid56_fpCosPiTest_s IS
WHEN "0" => vStagei_uid162_lzcZ_uid56_fpCosPiTest_q <= reg_rVStage_uid158_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid159_lzcZ_uid56_fpCosPiTest_1_q;
WHEN "1" => vStagei_uid162_lzcZ_uid56_fpCosPiTest_q <= reg_vStage_uid160_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid162_lzcZ_uid56_fpCosPiTest_3_q;
WHEN OTHERS => vStagei_uid162_lzcZ_uid56_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid164_lzcZ_uid56_fpCosPiTest(BITSELECT,163)@6
rVStage_uid164_lzcZ_uid56_fpCosPiTest_in <= vStagei_uid162_lzcZ_uid56_fpCosPiTest_q;
rVStage_uid164_lzcZ_uid56_fpCosPiTest_b <= rVStage_uid164_lzcZ_uid56_fpCosPiTest_in(3 downto 2);
--vCount_uid165_lzcZ_uid56_fpCosPiTest(LOGICAL,164)@6
vCount_uid165_lzcZ_uid56_fpCosPiTest_a <= rVStage_uid164_lzcZ_uid56_fpCosPiTest_b;
vCount_uid165_lzcZ_uid56_fpCosPiTest_b <= leftShiftStage2Idx2Pad2_uid128_fxpX_uid41_fpCosPiTest_q;
vCount_uid165_lzcZ_uid56_fpCosPiTest_q <= "1" when vCount_uid165_lzcZ_uid56_fpCosPiTest_a = vCount_uid165_lzcZ_uid56_fpCosPiTest_b else "0";
--vStage_uid166_lzcZ_uid56_fpCosPiTest(BITSELECT,165)@6
vStage_uid166_lzcZ_uid56_fpCosPiTest_in <= vStagei_uid162_lzcZ_uid56_fpCosPiTest_q(1 downto 0);
vStage_uid166_lzcZ_uid56_fpCosPiTest_b <= vStage_uid166_lzcZ_uid56_fpCosPiTest_in(1 downto 0);
--vStagei_uid168_lzcZ_uid56_fpCosPiTest(MUX,167)@6
vStagei_uid168_lzcZ_uid56_fpCosPiTest_s <= vCount_uid165_lzcZ_uid56_fpCosPiTest_q;
vStagei_uid168_lzcZ_uid56_fpCosPiTest: PROCESS (vStagei_uid168_lzcZ_uid56_fpCosPiTest_s, en, rVStage_uid164_lzcZ_uid56_fpCosPiTest_b, vStage_uid166_lzcZ_uid56_fpCosPiTest_b)
BEGIN
CASE vStagei_uid168_lzcZ_uid56_fpCosPiTest_s IS
WHEN "0" => vStagei_uid168_lzcZ_uid56_fpCosPiTest_q <= rVStage_uid164_lzcZ_uid56_fpCosPiTest_b;
WHEN "1" => vStagei_uid168_lzcZ_uid56_fpCosPiTest_q <= vStage_uid166_lzcZ_uid56_fpCosPiTest_b;
WHEN OTHERS => vStagei_uid168_lzcZ_uid56_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid170_lzcZ_uid56_fpCosPiTest(BITSELECT,169)@6
rVStage_uid170_lzcZ_uid56_fpCosPiTest_in <= vStagei_uid168_lzcZ_uid56_fpCosPiTest_q;
rVStage_uid170_lzcZ_uid56_fpCosPiTest_b <= rVStage_uid170_lzcZ_uid56_fpCosPiTest_in(1 downto 1);
--vCount_uid171_lzcZ_uid56_fpCosPiTest(LOGICAL,170)@6
vCount_uid171_lzcZ_uid56_fpCosPiTest_a <= rVStage_uid170_lzcZ_uid56_fpCosPiTest_b;
vCount_uid171_lzcZ_uid56_fpCosPiTest_b <= GND_q;
vCount_uid171_lzcZ_uid56_fpCosPiTest_q <= "1" when vCount_uid171_lzcZ_uid56_fpCosPiTest_a = vCount_uid171_lzcZ_uid56_fpCosPiTest_b else "0";
--r_uid172_lzcZ_uid56_fpCosPiTest(BITJOIN,171)@6
r_uid172_lzcZ_uid56_fpCosPiTest_q <= ld_vCount_uid139_lzcZ_uid56_fpCosPiTest_q_to_r_uid172_lzcZ_uid56_fpCosPiTest_f_q & ld_vCount_uid147_lzcZ_uid56_fpCosPiTest_q_to_r_uid172_lzcZ_uid56_fpCosPiTest_e_q & reg_vCount_uid153_lzcZ_uid56_fpCosPiTest_0_to_r_uid172_lzcZ_uid56_fpCosPiTest_3_q & vCount_uid159_lzcZ_uid56_fpCosPiTest_q & vCount_uid165_lzcZ_uid56_fpCosPiTest_q & vCount_uid171_lzcZ_uid56_fpCosPiTest_q;
--leftShiftStageSel5Dto4_uid182_alignedZ_uid57_fpCosPiTest(BITSELECT,181)@6
leftShiftStageSel5Dto4_uid182_alignedZ_uid57_fpCosPiTest_in <= r_uid172_lzcZ_uid56_fpCosPiTest_q;
leftShiftStageSel5Dto4_uid182_alignedZ_uid57_fpCosPiTest_b <= leftShiftStageSel5Dto4_uid182_alignedZ_uid57_fpCosPiTest_in(5 downto 4);
--leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest(MUX,182)@6
leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_s <= leftShiftStageSel5Dto4_uid182_alignedZ_uid57_fpCosPiTest_b;
leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest: PROCESS (leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_s, en, ld_z_uid54_fpCosPiTest_b_to_leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_c_q, leftShiftStage0Idx1_uid177_alignedZ_uid57_fpCosPiTest_q, leftShiftStage0Idx2_uid180_alignedZ_uid57_fpCosPiTest_q, cstZwSwF_uid15_fpCosPiTest_q)
BEGIN
CASE leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_s IS
WHEN "00" => leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_q <= ld_z_uid54_fpCosPiTest_b_to_leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_c_q;
WHEN "01" => leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_q <= leftShiftStage0Idx1_uid177_alignedZ_uid57_fpCosPiTest_q;
WHEN "10" => leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_q <= leftShiftStage0Idx2_uid180_alignedZ_uid57_fpCosPiTest_q;
WHEN "11" => leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_q <= cstZwSwF_uid15_fpCosPiTest_q;
WHEN OTHERS => leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage022dto0_uid191_alignedZ_uid57_fpCosPiTest(BITSELECT,190)@6
LeftShiftStage022dto0_uid191_alignedZ_uid57_fpCosPiTest_in <= leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_q(22 downto 0);
LeftShiftStage022dto0_uid191_alignedZ_uid57_fpCosPiTest_b <= LeftShiftStage022dto0_uid191_alignedZ_uid57_fpCosPiTest_in(22 downto 0);
--leftShiftStage1Idx3_uid192_alignedZ_uid57_fpCosPiTest(BITJOIN,191)@6
leftShiftStage1Idx3_uid192_alignedZ_uid57_fpCosPiTest_q <= LeftShiftStage022dto0_uid191_alignedZ_uid57_fpCosPiTest_b & leftShiftStage1Idx3Pad12_uid120_fxpX_uid41_fpCosPiTest_q;
--reg_leftShiftStage1Idx3_uid192_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_5(REG,261)@6
reg_leftShiftStage1Idx3_uid192_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx3_uid192_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_5_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx3_uid192_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_5_q <= leftShiftStage1Idx3_uid192_alignedZ_uid57_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage026dto0_uid188_alignedZ_uid57_fpCosPiTest(BITSELECT,187)@6
LeftShiftStage026dto0_uid188_alignedZ_uid57_fpCosPiTest_in <= leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_q(26 downto 0);
LeftShiftStage026dto0_uid188_alignedZ_uid57_fpCosPiTest_b <= LeftShiftStage026dto0_uid188_alignedZ_uid57_fpCosPiTest_in(26 downto 0);
--leftShiftStage1Idx2_uid189_alignedZ_uid57_fpCosPiTest(BITJOIN,188)@6
leftShiftStage1Idx2_uid189_alignedZ_uid57_fpCosPiTest_q <= LeftShiftStage026dto0_uid188_alignedZ_uid57_fpCosPiTest_b & cstAllZWE_uid21_fpCosPiTest_q;
--reg_leftShiftStage1Idx2_uid189_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_4(REG,260)@6
reg_leftShiftStage1Idx2_uid189_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx2_uid189_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_4_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx2_uid189_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_4_q <= leftShiftStage1Idx2_uid189_alignedZ_uid57_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage030dto0_uid185_alignedZ_uid57_fpCosPiTest(BITSELECT,184)@6
LeftShiftStage030dto0_uid185_alignedZ_uid57_fpCosPiTest_in <= leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_q(30 downto 0);
LeftShiftStage030dto0_uid185_alignedZ_uid57_fpCosPiTest_b <= LeftShiftStage030dto0_uid185_alignedZ_uid57_fpCosPiTest_in(30 downto 0);
--leftShiftStage1Idx1_uid186_alignedZ_uid57_fpCosPiTest(BITJOIN,185)@6
leftShiftStage1Idx1_uid186_alignedZ_uid57_fpCosPiTest_q <= LeftShiftStage030dto0_uid185_alignedZ_uid57_fpCosPiTest_b & leftShiftStage1Idx1Pad4_uid114_fxpX_uid41_fpCosPiTest_q;
--reg_leftShiftStage1Idx1_uid186_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_3(REG,259)@6
reg_leftShiftStage1Idx1_uid186_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx1_uid186_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_3_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx1_uid186_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_3_q <= leftShiftStage1Idx1_uid186_alignedZ_uid57_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--reg_leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_2(REG,258)@6
reg_leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_2_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_2_q <= leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel3Dto2_uid193_alignedZ_uid57_fpCosPiTest(BITSELECT,192)@6
leftShiftStageSel3Dto2_uid193_alignedZ_uid57_fpCosPiTest_in <= r_uid172_lzcZ_uid56_fpCosPiTest_q(3 downto 0);
leftShiftStageSel3Dto2_uid193_alignedZ_uid57_fpCosPiTest_b <= leftShiftStageSel3Dto2_uid193_alignedZ_uid57_fpCosPiTest_in(3 downto 2);
--reg_leftShiftStageSel3Dto2_uid193_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_1(REG,257)@6
reg_leftShiftStageSel3Dto2_uid193_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel3Dto2_uid193_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel3Dto2_uid193_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_1_q <= leftShiftStageSel3Dto2_uid193_alignedZ_uid57_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest(MUX,193)@7
leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_s <= reg_leftShiftStageSel3Dto2_uid193_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_1_q;
leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest: PROCESS (leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_s, en, reg_leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_2_q, reg_leftShiftStage1Idx1_uid186_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_3_q, reg_leftShiftStage1Idx2_uid189_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_4_q, reg_leftShiftStage1Idx3_uid192_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_5_q)
BEGIN
CASE leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_s IS
WHEN "00" => leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_q <= reg_leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_2_q;
WHEN "01" => leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_q <= reg_leftShiftStage1Idx1_uid186_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_3_q;
WHEN "10" => leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_q <= reg_leftShiftStage1Idx2_uid189_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_4_q;
WHEN "11" => leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_q <= reg_leftShiftStage1Idx3_uid192_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_5_q;
WHEN OTHERS => leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--leftShiftStageSel1Dto0_uid204_alignedZ_uid57_fpCosPiTest(BITSELECT,203)@6
leftShiftStageSel1Dto0_uid204_alignedZ_uid57_fpCosPiTest_in <= r_uid172_lzcZ_uid56_fpCosPiTest_q(1 downto 0);
leftShiftStageSel1Dto0_uid204_alignedZ_uid57_fpCosPiTest_b <= leftShiftStageSel1Dto0_uid204_alignedZ_uid57_fpCosPiTest_in(1 downto 0);
--reg_leftShiftStageSel1Dto0_uid204_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest_1(REG,262)@6
reg_leftShiftStageSel1Dto0_uid204_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel1Dto0_uid204_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel1Dto0_uid204_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest_1_q <= leftShiftStageSel1Dto0_uid204_alignedZ_uid57_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest(MUX,204)@7
leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest_s <= reg_leftShiftStageSel1Dto0_uid204_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest_1_q;
leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest: PROCESS (leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest_s, en, leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_q, leftShiftStage2Idx1_uid197_alignedZ_uid57_fpCosPiTest_q, leftShiftStage2Idx2_uid200_alignedZ_uid57_fpCosPiTest_q, leftShiftStage2Idx3_uid203_alignedZ_uid57_fpCosPiTest_q)
BEGIN
CASE leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest_s IS
WHEN "00" => leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest_q <= leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_q;
WHEN "01" => leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest_q <= leftShiftStage2Idx1_uid197_alignedZ_uid57_fpCosPiTest_q;
WHEN "10" => leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest_q <= leftShiftStage2Idx2_uid200_alignedZ_uid57_fpCosPiTest_q;
WHEN "11" => leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest_q <= leftShiftStage2Idx3_uid203_alignedZ_uid57_fpCosPiTest_q;
WHEN OTHERS => leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--alignedZLow_uid58_fpCosPiTest(BITSELECT,57)@7
alignedZLow_uid58_fpCosPiTest_in <= leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest_q;
alignedZLow_uid58_fpCosPiTest_b <= alignedZLow_uid58_fpCosPiTest_in(34 downto 11);
--ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_inputreg(DELAY,612)
ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 24, depth => 1 )
PORT MAP ( xin => alignedZLow_uid58_fpCosPiTest_b, xout => ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem(DUALMEM,613)
ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_reset0 <= areset;
ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_ia <= ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_inputreg_q;
ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_aa <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdreg_q;
ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_ab <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdmux_q;
ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 24,
widthad_a => 2,
numwords_a => 3,
width_b => 24,
widthad_b => 2,
numwords_b => 3,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_iq,
address_a => ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_aa,
data_a => ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_ia
);
ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_q <= ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_iq(23 downto 0);
--reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0(REG,269)@12
reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_q <= ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest(MULT,222)@13
prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_pr <= UNSIGNED(prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_a) * UNSIGNED(prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_b);
prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_a <= (others => '0');
prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_b <= (others => '0');
prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_a <= reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_q;
prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_b <= reg_fxpSinRes_uid65_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_1_q;
prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_s1 <= STD_LOGIC_VECTOR(prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_pr);
END IF;
END IF;
END PROCESS;
prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_q <= prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid224_mul2xSinRes_uid66_fpCosPiTest(BITSELECT,223)@16
prodXYTruncFR_uid224_mul2xSinRes_uid66_fpCosPiTest_in <= prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_q;
prodXYTruncFR_uid224_mul2xSinRes_uid66_fpCosPiTest_b <= prodXYTruncFR_uid224_mul2xSinRes_uid66_fpCosPiTest_in(48 downto 23);
--normBit_uid67_fpCosPiTest(BITSELECT,66)@16
normBit_uid67_fpCosPiTest_in <= prodXYTruncFR_uid224_mul2xSinRes_uid66_fpCosPiTest_b;
normBit_uid67_fpCosPiTest_b <= normBit_uid67_fpCosPiTest_in(25 downto 25);
--cstAllZWF_uid9_fpCosPiTest(CONSTANT,8)
cstAllZWF_uid9_fpCosPiTest_q <= "00000000000000000000000";
--rndExpUpdate_uid72_uid73_fpCosPiTest(BITJOIN,72)@16
rndExpUpdate_uid72_uid73_fpCosPiTest_q <= normBit_uid67_fpCosPiTest_b & cstAllZWF_uid9_fpCosPiTest_q & VCC_q;
--ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_nor(LOGICAL,558)
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_nor_a <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_notEnable_q;
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_nor_b <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_sticky_ena_q;
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_nor_q <= not (ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_nor_a or ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_nor_b);
--ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_sticky_ena(REG,559)
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_nor_q = "1") THEN
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_sticky_ena_q <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_enaAnd(LOGICAL,560)
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_enaAnd_a <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_sticky_ena_q;
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_enaAnd_b <= en;
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_enaAnd_q <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_enaAnd_a and ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_enaAnd_b;
--reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1(REG,271)@6
reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q <= r_uid172_lzcZ_uid56_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem(DUALMEM,549)
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_reset0 <= areset;
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_ia <= reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q;
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_aa <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdreg_q;
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_ab <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdmux_q;
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 6,
widthad_a => 3,
numwords_a => 7,
width_b => 6,
widthad_b => 3,
numwords_b => 7,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_iq,
address_a => ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_aa,
data_a => ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_ia
);
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_q <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_iq(5 downto 0);
--cstBiasM1_uid11_fpCosPiTest(CONSTANT,10)
cstBiasM1_uid11_fpCosPiTest_q <= "01111110";
--expHardCase_uid59_fpCosPiTest(SUB,58)@15
expHardCase_uid59_fpCosPiTest_a <= STD_LOGIC_VECTOR("0" & cstBiasM1_uid11_fpCosPiTest_q);
expHardCase_uid59_fpCosPiTest_b <= STD_LOGIC_VECTOR("000" & ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_q);
expHardCase_uid59_fpCosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expHardCase_uid59_fpCosPiTest_a) - UNSIGNED(expHardCase_uid59_fpCosPiTest_b));
expHardCase_uid59_fpCosPiTest_q <= expHardCase_uid59_fpCosPiTest_o(8 downto 0);
--expP_uid60_fpCosPiTest(BITSELECT,59)@15
expP_uid60_fpCosPiTest_in <= expHardCase_uid59_fpCosPiTest_q(7 downto 0);
expP_uid60_fpCosPiTest_b <= expP_uid60_fpCosPiTest_in(7 downto 0);
--reg_expP_uid60_fpCosPiTest_0_to_expFracPreRnd_uid71_uid71_fpCosPiTest_1(REG,272)@15
reg_expP_uid60_fpCosPiTest_0_to_expFracPreRnd_uid71_uid71_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expP_uid60_fpCosPiTest_0_to_expFracPreRnd_uid71_uid71_fpCosPiTest_1_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expP_uid60_fpCosPiTest_0_to_expFracPreRnd_uid71_uid71_fpCosPiTest_1_q <= expP_uid60_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--highRes_uid68_fpCosPiTest(BITSELECT,67)@16
highRes_uid68_fpCosPiTest_in <= prodXYTruncFR_uid224_mul2xSinRes_uid66_fpCosPiTest_b(24 downto 0);
highRes_uid68_fpCosPiTest_b <= highRes_uid68_fpCosPiTest_in(24 downto 1);
--lowRes_uid69_fpCosPiTest(BITSELECT,68)@16
lowRes_uid69_fpCosPiTest_in <= prodXYTruncFR_uid224_mul2xSinRes_uid66_fpCosPiTest_b(23 downto 0);
lowRes_uid69_fpCosPiTest_b <= lowRes_uid69_fpCosPiTest_in(23 downto 0);
--fracRCompPreRnd_uid70_fpCosPiTest(MUX,69)@16
fracRCompPreRnd_uid70_fpCosPiTest_s <= normBit_uid67_fpCosPiTest_b;
fracRCompPreRnd_uid70_fpCosPiTest: PROCESS (fracRCompPreRnd_uid70_fpCosPiTest_s, en, lowRes_uid69_fpCosPiTest_b, highRes_uid68_fpCosPiTest_b)
BEGIN
CASE fracRCompPreRnd_uid70_fpCosPiTest_s IS
WHEN "0" => fracRCompPreRnd_uid70_fpCosPiTest_q <= lowRes_uid69_fpCosPiTest_b;
WHEN "1" => fracRCompPreRnd_uid70_fpCosPiTest_q <= highRes_uid68_fpCosPiTest_b;
WHEN OTHERS => fracRCompPreRnd_uid70_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--expFracPreRnd_uid71_uid71_fpCosPiTest(BITJOIN,70)@16
expFracPreRnd_uid71_uid71_fpCosPiTest_q <= reg_expP_uid60_fpCosPiTest_0_to_expFracPreRnd_uid71_uid71_fpCosPiTest_1_q & fracRCompPreRnd_uid70_fpCosPiTest_q;
--expFracComp_uid74_fpCosPiTest(ADD,73)@16
expFracComp_uid74_fpCosPiTest_a <= STD_LOGIC_VECTOR("0" & expFracPreRnd_uid71_uid71_fpCosPiTest_q);
expFracComp_uid74_fpCosPiTest_b <= STD_LOGIC_VECTOR("00000000" & rndExpUpdate_uid72_uid73_fpCosPiTest_q);
expFracComp_uid74_fpCosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expFracComp_uid74_fpCosPiTest_a) + UNSIGNED(expFracComp_uid74_fpCosPiTest_b));
expFracComp_uid74_fpCosPiTest_q <= expFracComp_uid74_fpCosPiTest_o(32 downto 0);
--expRComp_uid76_fpCosPiTest(BITSELECT,75)@16
expRComp_uid76_fpCosPiTest_in <= expFracComp_uid74_fpCosPiTest_q(31 downto 0);
expRComp_uid76_fpCosPiTest_b <= expRComp_uid76_fpCosPiTest_in(31 downto 24);
--fracXIsZero_uid27_fpCosPiTest(LOGICAL,26)@0
fracXIsZero_uid27_fpCosPiTest_a <= fracX_uid7_fpCosPiTest_b;
fracXIsZero_uid27_fpCosPiTest_b <= cstAllZWF_uid9_fpCosPiTest_q;
fracXIsZero_uid27_fpCosPiTest_q <= "1" when fracXIsZero_uid27_fpCosPiTest_a = fracXIsZero_uid27_fpCosPiTest_b else "0";
--InvFracXIsZero_uid29_fpCosPiTest(LOGICAL,28)@0
InvFracXIsZero_uid29_fpCosPiTest_a <= fracXIsZero_uid27_fpCosPiTest_q;
InvFracXIsZero_uid29_fpCosPiTest_q <= not InvFracXIsZero_uid29_fpCosPiTest_a;
--expXIsMax_uid25_fpCosPiTest(LOGICAL,24)@0
expXIsMax_uid25_fpCosPiTest_a <= expX_uid6_fpCosPiTest_b;
expXIsMax_uid25_fpCosPiTest_b <= cstAllOWE_uid8_fpCosPiTest_q;
expXIsMax_uid25_fpCosPiTest_q <= "1" when expXIsMax_uid25_fpCosPiTest_a = expXIsMax_uid25_fpCosPiTest_b else "0";
--exc_N_uid30_fpCosPiTest(LOGICAL,29)@0
exc_N_uid30_fpCosPiTest_a <= expXIsMax_uid25_fpCosPiTest_q;
exc_N_uid30_fpCosPiTest_b <= InvFracXIsZero_uid29_fpCosPiTest_q;
exc_N_uid30_fpCosPiTest_q <= exc_N_uid30_fpCosPiTest_a and exc_N_uid30_fpCosPiTest_b;
--InvExc_N_uid31_fpCosPiTest(LOGICAL,30)@0
InvExc_N_uid31_fpCosPiTest_a <= exc_N_uid30_fpCosPiTest_q;
InvExc_N_uid31_fpCosPiTest_q <= not InvExc_N_uid31_fpCosPiTest_a;
--exc_I_uid28_fpCosPiTest(LOGICAL,27)@0
exc_I_uid28_fpCosPiTest_a <= expXIsMax_uid25_fpCosPiTest_q;
exc_I_uid28_fpCosPiTest_b <= fracXIsZero_uid27_fpCosPiTest_q;
exc_I_uid28_fpCosPiTest_q <= exc_I_uid28_fpCosPiTest_a and exc_I_uid28_fpCosPiTest_b;
--InvExc_I_uid32_fpCosPiTest(LOGICAL,31)@0
InvExc_I_uid32_fpCosPiTest_a <= exc_I_uid28_fpCosPiTest_q;
InvExc_I_uid32_fpCosPiTest_q <= not InvExc_I_uid32_fpCosPiTest_a;
--expXIsZero_uid23_fpCosPiTest(LOGICAL,22)@0
expXIsZero_uid23_fpCosPiTest_a <= expX_uid6_fpCosPiTest_b;
expXIsZero_uid23_fpCosPiTest_b <= cstAllZWE_uid21_fpCosPiTest_q;
expXIsZero_uid23_fpCosPiTest_q <= "1" when expXIsZero_uid23_fpCosPiTest_a = expXIsZero_uid23_fpCosPiTest_b else "0";
--InvExpXIsZero_uid33_fpCosPiTest(LOGICAL,32)@0
InvExpXIsZero_uid33_fpCosPiTest_a <= expXIsZero_uid23_fpCosPiTest_q;
InvExpXIsZero_uid33_fpCosPiTest_q <= not InvExpXIsZero_uid33_fpCosPiTest_a;
--exc_R_uid34_fpCosPiTest(LOGICAL,33)@0
exc_R_uid34_fpCosPiTest_a <= InvExpXIsZero_uid33_fpCosPiTest_q;
exc_R_uid34_fpCosPiTest_b <= InvExc_I_uid32_fpCosPiTest_q;
exc_R_uid34_fpCosPiTest_c <= InvExc_N_uid31_fpCosPiTest_q;
exc_R_uid34_fpCosPiTest_q <= exc_R_uid34_fpCosPiTest_a and exc_R_uid34_fpCosPiTest_b and exc_R_uid34_fpCosPiTest_c;
--ld_exc_R_uid34_fpCosPiTest_q_to_xIsInt_uid80_fpCosPiTest_a(DELAY,337)@0
ld_exc_R_uid34_fpCosPiTest_q_to_xIsInt_uid80_fpCosPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => exc_R_uid34_fpCosPiTest_q, xout => ld_exc_R_uid34_fpCosPiTest_q_to_xIsInt_uid80_fpCosPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--xIsHalf_uid83_fpCosPiTest(LOGICAL,82)@2
xIsHalf_uid83_fpCosPiTest_a <= ld_exc_R_uid34_fpCosPiTest_q_to_xIsInt_uid80_fpCosPiTest_a_q;
xIsHalf_uid83_fpCosPiTest_b <= fxpXFracHalf_uid46_fpCosPiTest_q;
xIsHalf_uid83_fpCosPiTest_c <= InvCosXIsOne_uid77_fpCosPiTest_q;
xIsHalf_uid83_fpCosPiTest_d <= InvXEvenInt_uid81_fpCosPiTest_q;
xIsHalf_uid83_fpCosPiTest_q <= xIsHalf_uid83_fpCosPiTest_a and xIsHalf_uid83_fpCosPiTest_b and xIsHalf_uid83_fpCosPiTest_c and xIsHalf_uid83_fpCosPiTest_d;
--ld_xIsHalf_uid83_fpCosPiTest_q_to_expRPostExc1_uid91_fpCosPiTest_b(DELAY,355)@2
ld_xIsHalf_uid83_fpCosPiTest_q_to_expRPostExc1_uid91_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 14 )
PORT MAP ( xin => xIsHalf_uid83_fpCosPiTest_q, xout => ld_xIsHalf_uid83_fpCosPiTest_q_to_expRPostExc1_uid91_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--expRPostExc1_uid91_fpCosPiTest(MUX,90)@16
expRPostExc1_uid91_fpCosPiTest_s <= ld_xIsHalf_uid83_fpCosPiTest_q_to_expRPostExc1_uid91_fpCosPiTest_b_q;
expRPostExc1_uid91_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expRPostExc1_uid91_fpCosPiTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE expRPostExc1_uid91_fpCosPiTest_s IS
WHEN "0" => expRPostExc1_uid91_fpCosPiTest_q <= expRComp_uid76_fpCosPiTest_b;
WHEN "1" => expRPostExc1_uid91_fpCosPiTest_q <= cstAllZWE_uid21_fpCosPiTest_q;
WHEN OTHERS => expRPostExc1_uid91_fpCosPiTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_nor(LOGICAL,570)
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_nor_a <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_notEnable_q;
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_nor_b <= ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_sticky_ena_q;
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_nor_q <= not (ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_nor_a or ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_nor_b);
--ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_mem_top(CONSTANT,566)
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_mem_top_q <= "01100";
--ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_cmp(LOGICAL,567)
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_cmp_a <= ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_mem_top_q;
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdmux_q);
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_cmp_q <= "1" when ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_cmp_a = ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_cmp_b else "0";
--ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_cmpReg(REG,568)
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_cmpReg_q <= ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_sticky_ena(REG,571)
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_nor_q = "1") THEN
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_sticky_ena_q <= ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_enaAnd(LOGICAL,572)
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_enaAnd_a <= ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_sticky_ena_q;
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_enaAnd_b <= en;
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_enaAnd_q <= ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_enaAnd_a and ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_enaAnd_b;
--ld_expXIsZero_uid23_fpCosPiTest_q_to_xIntOrXZOrCosOne_uid93_fpCosPiTest_b(DELAY,359)@0
ld_expXIsZero_uid23_fpCosPiTest_q_to_xIntOrXZOrCosOne_uid93_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => expXIsZero_uid23_fpCosPiTest_q, xout => ld_expXIsZero_uid23_fpCosPiTest_q_to_xIntOrXZOrCosOne_uid93_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--fxpXFracZero_uid45_fpCosPiTest(LOGICAL,44)@2
fxpXFracZero_uid45_fpCosPiTest_a <= reg_fxpXFrac_uid43_fpCosPiTest_0_to_fxpXFracZero_uid45_fpCosPiTest_1_q;
fxpXFracZero_uid45_fpCosPiTest_b <= STD_LOGIC_VECTOR("0" & cstZwSwF_uid15_fpCosPiTest_q);
fxpXFracZero_uid45_fpCosPiTest_q <= "1" when fxpXFracZero_uid45_fpCosPiTest_a = fxpXFracZero_uid45_fpCosPiTest_b else "0";
--fracZCosNotOne_uid78_fpCosPiTest(LOGICAL,77)@2
fracZCosNotOne_uid78_fpCosPiTest_a <= fxpXFracZero_uid45_fpCosPiTest_q;
fracZCosNotOne_uid78_fpCosPiTest_b <= InvCosXIsOne_uid77_fpCosPiTest_q;
fracZCosNotOne_uid78_fpCosPiTest_q <= fracZCosNotOne_uid78_fpCosPiTest_a and fracZCosNotOne_uid78_fpCosPiTest_b;
--evenIntCosNotOneFZ_uid79_fpCosPiTest(LOGICAL,78)@2
evenIntCosNotOneFZ_uid79_fpCosPiTest_a <= ld_xEvenInt_uid35_fpCosPiTest_c_to_evenIntCosNotOneFZ_uid79_fpCosPiTest_a_q;
evenIntCosNotOneFZ_uid79_fpCosPiTest_b <= fracZCosNotOne_uid78_fpCosPiTest_q;
evenIntCosNotOneFZ_uid79_fpCosPiTest_q <= evenIntCosNotOneFZ_uid79_fpCosPiTest_a or evenIntCosNotOneFZ_uid79_fpCosPiTest_b;
--xIsInt_uid80_fpCosPiTest(LOGICAL,79)@2
xIsInt_uid80_fpCosPiTest_a <= ld_exc_R_uid34_fpCosPiTest_q_to_xIsInt_uid80_fpCosPiTest_a_q;
xIsInt_uid80_fpCosPiTest_b <= evenIntCosNotOneFZ_uid79_fpCosPiTest_q;
xIsInt_uid80_fpCosPiTest_q <= xIsInt_uid80_fpCosPiTest_a and xIsInt_uid80_fpCosPiTest_b;
--xIntOrXZOrCosOne_uid93_fpCosPiTest(LOGICAL,92)@2
xIntOrXZOrCosOne_uid93_fpCosPiTest_a <= xIsInt_uid80_fpCosPiTest_q;
xIntOrXZOrCosOne_uid93_fpCosPiTest_b <= ld_expXIsZero_uid23_fpCosPiTest_q_to_xIntOrXZOrCosOne_uid93_fpCosPiTest_b_q;
xIntOrXZOrCosOne_uid93_fpCosPiTest_c <= ld_cosXIsOne_uid36_fpCosPiTest_c_to_InvCosXIsOne_uid77_fpCosPiTest_a_q;
xIntOrXZOrCosOne_uid93_fpCosPiTest_q <= xIntOrXZOrCosOne_uid93_fpCosPiTest_a or xIntOrXZOrCosOne_uid93_fpCosPiTest_b or xIntOrXZOrCosOne_uid93_fpCosPiTest_c;
--excRNaN_uid84_fpCosPiTest(LOGICAL,83)@0
excRNaN_uid84_fpCosPiTest_a <= exc_N_uid30_fpCosPiTest_q;
excRNaN_uid84_fpCosPiTest_b <= exc_I_uid28_fpCosPiTest_q;
excRNaN_uid84_fpCosPiTest_q <= excRNaN_uid84_fpCosPiTest_a or excRNaN_uid84_fpCosPiTest_b;
--rInfOrNaN_uid92_fpCosPiTest(LOGICAL,91)@0
rInfOrNaN_uid92_fpCosPiTest_a <= GND_q;
rInfOrNaN_uid92_fpCosPiTest_b <= excRNaN_uid84_fpCosPiTest_q;
rInfOrNaN_uid92_fpCosPiTest_q <= rInfOrNaN_uid92_fpCosPiTest_a or rInfOrNaN_uid92_fpCosPiTest_b;
--ld_rInfOrNaN_uid92_fpCosPiTest_q_to_join_uid94_fpCosPiTest_a(DELAY,361)@0
ld_rInfOrNaN_uid92_fpCosPiTest_q_to_join_uid94_fpCosPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => rInfOrNaN_uid92_fpCosPiTest_q, xout => ld_rInfOrNaN_uid92_fpCosPiTest_q_to_join_uid94_fpCosPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--join_uid94_fpCosPiTest(BITJOIN,93)@2
join_uid94_fpCosPiTest_q <= xIntOrXZOrCosOne_uid93_fpCosPiTest_q & ld_rInfOrNaN_uid92_fpCosPiTest_q_to_join_uid94_fpCosPiTest_a_q;
--reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1(REG,274)@2
reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q <= join_uid94_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt(COUNTER,562)
-- every=1, low=0, high=12, step=1, init=1
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt_i = 11 THEN
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt_eq <= '1';
ELSE
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt_eq = '1') THEN
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt_i <= ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt_i - 12;
ELSE
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt_i <= ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt_i,4));
--ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdreg(REG,563)
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdreg_q <= ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdmux(MUX,564)
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdmux_s <= en;
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdmux: PROCESS (ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdmux_s, ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdreg_q, ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt_q)
BEGIN
CASE ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdmux_s IS
WHEN "0" => ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdmux_q <= ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdreg_q;
WHEN "1" => ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdmux_q <= ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem(DUALMEM,561)
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_reset0 <= areset;
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_ia <= reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q;
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_aa <= ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdreg_q;
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_ab <= ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdmux_q;
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 2,
widthad_a => 4,
numwords_a => 13,
width_b => 2,
widthad_b => 4,
numwords_b => 13,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_iq,
address_a => ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_aa,
data_a => ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_ia
);
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_q <= ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_iq(1 downto 0);
--expRPostExc_uid95_fpCosPiTest(MUX,94)@17
expRPostExc_uid95_fpCosPiTest_s <= ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_q;
expRPostExc_uid95_fpCosPiTest: PROCESS (expRPostExc_uid95_fpCosPiTest_s, en, expRPostExc1_uid91_fpCosPiTest_q, cstAllOWE_uid8_fpCosPiTest_q, cstBias_uid10_fpCosPiTest_q, cstBias_uid10_fpCosPiTest_q)
BEGIN
CASE expRPostExc_uid95_fpCosPiTest_s IS
WHEN "00" => expRPostExc_uid95_fpCosPiTest_q <= expRPostExc1_uid91_fpCosPiTest_q;
WHEN "01" => expRPostExc_uid95_fpCosPiTest_q <= cstAllOWE_uid8_fpCosPiTest_q;
WHEN "10" => expRPostExc_uid95_fpCosPiTest_q <= cstBias_uid10_fpCosPiTest_q;
WHEN "11" => expRPostExc_uid95_fpCosPiTest_q <= cstBias_uid10_fpCosPiTest_q;
WHEN OTHERS => expRPostExc_uid95_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--oneFracRPostExc2_uid87_fpCosPiTest(CONSTANT,86)
oneFracRPostExc2_uid87_fpCosPiTest_q <= "00000000000000000000001";
--fracRComp_uid75_fpCosPiTest(BITSELECT,74)@16
fracRComp_uid75_fpCosPiTest_in <= expFracComp_uid74_fpCosPiTest_q(23 downto 0);
fracRComp_uid75_fpCosPiTest_b <= fracRComp_uid75_fpCosPiTest_in(23 downto 1);
--reg_xIsHalf_uid83_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_5(REG,243)@2
reg_xIsHalf_uid83_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xIsHalf_uid83_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_5_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xIsHalf_uid83_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_5_q <= xIsHalf_uid83_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--reg_expXIsZero_uid23_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_4(REG,242)@2
reg_expXIsZero_uid23_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expXIsZero_uid23_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_4_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expXIsZero_uid23_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_4_q <= ld_expXIsZero_uid23_fpCosPiTest_q_to_xIntOrXZOrCosOne_uid93_fpCosPiTest_b_q;
END IF;
END IF;
END PROCESS;
--reg_fxpXFracHalf_uid46_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_3(REG,241)@2
reg_fxpXFracHalf_uid46_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fxpXFracHalf_uid46_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_3_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fxpXFracHalf_uid46_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_3_q <= fxpXFracHalf_uid46_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--reg_xIsInt_uid80_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_2(REG,240)@2
reg_xIsInt_uid80_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xIsInt_uid80_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xIsInt_uid80_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_2_q <= xIsInt_uid80_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--reg_cosXIsOne_uid36_fpCosPiTest_1_to_bigCond_uid85_fpCosPiTest_1(REG,239)@0
reg_cosXIsOne_uid36_fpCosPiTest_1_to_bigCond_uid85_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cosXIsOne_uid36_fpCosPiTest_1_to_bigCond_uid85_fpCosPiTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cosXIsOne_uid36_fpCosPiTest_1_to_bigCond_uid85_fpCosPiTest_1_q <= cosXIsOne_uid36_fpCosPiTest_c;
END IF;
END IF;
END PROCESS;
--ld_reg_cosXIsOne_uid36_fpCosPiTest_1_to_bigCond_uid85_fpCosPiTest_1_q_to_bigCond_uid85_fpCosPiTest_a(DELAY,346)@1
ld_reg_cosXIsOne_uid36_fpCosPiTest_1_to_bigCond_uid85_fpCosPiTest_1_q_to_bigCond_uid85_fpCosPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => reg_cosXIsOne_uid36_fpCosPiTest_1_to_bigCond_uid85_fpCosPiTest_1_q, xout => ld_reg_cosXIsOne_uid36_fpCosPiTest_1_to_bigCond_uid85_fpCosPiTest_1_q_to_bigCond_uid85_fpCosPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--bigCond_uid85_fpCosPiTest(LOGICAL,84)@3
bigCond_uid85_fpCosPiTest_a <= ld_reg_cosXIsOne_uid36_fpCosPiTest_1_to_bigCond_uid85_fpCosPiTest_1_q_to_bigCond_uid85_fpCosPiTest_a_q;
bigCond_uid85_fpCosPiTest_b <= reg_xIsInt_uid80_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_2_q;
bigCond_uid85_fpCosPiTest_c <= reg_fxpXFracHalf_uid46_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_3_q;
bigCond_uid85_fpCosPiTest_d <= reg_expXIsZero_uid23_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_4_q;
bigCond_uid85_fpCosPiTest_f <= reg_xIsHalf_uid83_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_5_q;
bigCond_uid85_fpCosPiTest_g <= GND_q;
bigCond_uid85_fpCosPiTest_q <= bigCond_uid85_fpCosPiTest_a or bigCond_uid85_fpCosPiTest_b or bigCond_uid85_fpCosPiTest_c or bigCond_uid85_fpCosPiTest_d or bigCond_uid85_fpCosPiTest_f or bigCond_uid85_fpCosPiTest_g;
--ld_bigCond_uid85_fpCosPiTest_q_to_fracRPostExc1_uid86_fpCosPiTest_b(DELAY,351)@3
ld_bigCond_uid85_fpCosPiTest_q_to_fracRPostExc1_uid86_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 13 )
PORT MAP ( xin => bigCond_uid85_fpCosPiTest_q, xout => ld_bigCond_uid85_fpCosPiTest_q_to_fracRPostExc1_uid86_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--fracRPostExc1_uid86_fpCosPiTest(MUX,85)@16
fracRPostExc1_uid86_fpCosPiTest_s <= ld_bigCond_uid85_fpCosPiTest_q_to_fracRPostExc1_uid86_fpCosPiTest_b_q;
fracRPostExc1_uid86_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
fracRPostExc1_uid86_fpCosPiTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE fracRPostExc1_uid86_fpCosPiTest_s IS
WHEN "0" => fracRPostExc1_uid86_fpCosPiTest_q <= fracRComp_uid75_fpCosPiTest_b;
WHEN "1" => fracRPostExc1_uid86_fpCosPiTest_q <= cstAllZWF_uid9_fpCosPiTest_q;
WHEN OTHERS => fracRPostExc1_uid86_fpCosPiTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--reg_excRNaN_uid84_fpCosPiTest_0_to_fracRPostExc_uid88_fpCosPiTest_1(REG,273)@0
reg_excRNaN_uid84_fpCosPiTest_0_to_fracRPostExc_uid88_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_excRNaN_uid84_fpCosPiTest_0_to_fracRPostExc_uid88_fpCosPiTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_excRNaN_uid84_fpCosPiTest_0_to_fracRPostExc_uid88_fpCosPiTest_1_q <= excRNaN_uid84_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_excRNaN_uid84_fpCosPiTest_0_to_fracRPostExc_uid88_fpCosPiTest_1_q_to_fracRPostExc_uid88_fpCosPiTest_b(DELAY,353)@1
ld_reg_excRNaN_uid84_fpCosPiTest_0_to_fracRPostExc_uid88_fpCosPiTest_1_q_to_fracRPostExc_uid88_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 16 )
PORT MAP ( xin => reg_excRNaN_uid84_fpCosPiTest_0_to_fracRPostExc_uid88_fpCosPiTest_1_q, xout => ld_reg_excRNaN_uid84_fpCosPiTest_0_to_fracRPostExc_uid88_fpCosPiTest_1_q_to_fracRPostExc_uid88_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--fracRPostExc_uid88_fpCosPiTest(MUX,87)@17
fracRPostExc_uid88_fpCosPiTest_s <= ld_reg_excRNaN_uid84_fpCosPiTest_0_to_fracRPostExc_uid88_fpCosPiTest_1_q_to_fracRPostExc_uid88_fpCosPiTest_b_q;
fracRPostExc_uid88_fpCosPiTest: PROCESS (fracRPostExc_uid88_fpCosPiTest_s, en, fracRPostExc1_uid86_fpCosPiTest_q, oneFracRPostExc2_uid87_fpCosPiTest_q)
BEGIN
CASE fracRPostExc_uid88_fpCosPiTest_s IS
WHEN "0" => fracRPostExc_uid88_fpCosPiTest_q <= fracRPostExc1_uid86_fpCosPiTest_q;
WHEN "1" => fracRPostExc_uid88_fpCosPiTest_q <= oneFracRPostExc2_uid87_fpCosPiTest_q;
WHEN OTHERS => fracRPostExc_uid88_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--R_uid102_fpCosPiTest(BITJOIN,101)@17
R_uid102_fpCosPiTest_q <= ld_signR_uid101_fpCosPiTest_q_to_R_uid102_fpCosPiTest_c_q & expRPostExc_uid95_fpCosPiTest_q & fracRPostExc_uid88_fpCosPiTest_q;
--xOut(GPOUT,4)@17
q <= R_uid102_fpCosPiTest_q;
end normal;
|
-----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Release Version 13.1
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing device programming or simulation files), and
-- any associated documentation or information are expressly subject to the
-- terms and conditions of the Altera Program License Subscription Agreement,
-- Altera MegaCore Function License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for the sole
-- purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
-----------------------------------------------------------------------------
-- VHDL created from fp_cospi_s5
-- VHDL created on Wed Feb 27 15:22:33 2013
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.all;
use std.TextIO.all;
use work.dspba_library_package.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
entity fp_cospi_s5 is
port (
a : in std_logic_vector(31 downto 0);
en : in std_logic_vector(0 downto 0);
q : out std_logic_vector(31 downto 0);
clk : in std_logic;
areset : in std_logic
);
end;
architecture normal of fp_cospi_s5 is
attribute altera_attribute : string;
attribute altera_attribute of normal : architecture is "-name NOT_GATE_PUSH_BACK OFF; -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON; -name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410";
signal GND_q : std_logic_vector (0 downto 0);
signal VCC_q : std_logic_vector (0 downto 0);
signal cstAllOWE_uid8_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal cstAllZWF_uid9_fpCosPiTest_q : std_logic_vector (22 downto 0);
signal cstBias_uid10_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal cstBiasM1_uid11_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal cstBiasPwF_uid12_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal biasMwShiftMO_uid13_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal cst01pWShift_uid14_fpCosPiTest_q : std_logic_vector (12 downto 0);
signal cstZwSwF_uid15_fpCosPiTest_q : std_logic_vector (34 downto 0);
signal cstAllZWE_uid21_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal rangeReducedFxPX_uid51_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal rangeReducedFxPX_uid51_fpCosPiTest_q : std_logic_vector (35 downto 0);
signal fracRPostExc1_uid86_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal fracRPostExc1_uid86_fpCosPiTest_q : std_logic_vector (22 downto 0);
signal oneFracRPostExc2_uid87_fpCosPiTest_q : std_logic_vector (22 downto 0);
signal expRPostExc1_uid91_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal expRPostExc1_uid91_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal signRComp_uid99_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal signRComp_uid99_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal signRComp_uid99_fpCosPiTest_c : std_logic_vector(0 downto 0);
signal signRComp_uid99_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal signR_uid101_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal signR_uid101_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal signR_uid101_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal leftShiftStage0Idx1Pad16_uid105_fxpX_uid41_fpCosPiTest_q : std_logic_vector (15 downto 0);
signal leftShiftStage0Idx2Pad32_uid108_fxpX_uid41_fpCosPiTest_q : std_logic_vector (31 downto 0);
signal leftShiftStage0Idx3_uid111_fxpX_uid41_fpCosPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage1Idx1Pad4_uid114_fxpX_uid41_fpCosPiTest_q : std_logic_vector (3 downto 0);
signal leftShiftStage1Idx3Pad12_uid120_fxpX_uid41_fpCosPiTest_q : std_logic_vector (11 downto 0);
signal leftShiftStage2Idx2Pad2_uid128_fxpX_uid41_fpCosPiTest_q : std_logic_vector (1 downto 0);
signal leftShiftStage2Idx3Pad3_uid131_fxpX_uid41_fpCosPiTest_q : std_logic_vector (2 downto 0);
signal mO_uid140_lzcZ_uid56_fpCosPiTest_q : std_logic_vector (28 downto 0);
signal memoryC2_uid209_sinPiZTableGenerator_q : std_logic_vector(13 downto 0);
signal prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_a : std_logic_vector (23 downto 0);
signal prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_b : std_logic_vector (24 downto 0);
signal prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_s1 : std_logic_vector (48 downto 0);
signal prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_pr : UNSIGNED (48 downto 0);
signal prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_q : std_logic_vector (48 downto 0);
signal prodXY_uid226_pT1_uid211_sinPiZPolyEval_a : std_logic_vector (13 downto 0);
signal prodXY_uid226_pT1_uid211_sinPiZPolyEval_b : std_logic_vector (13 downto 0);
signal prodXY_uid226_pT1_uid211_sinPiZPolyEval_s1 : std_logic_vector (27 downto 0);
signal prodXY_uid226_pT1_uid211_sinPiZPolyEval_pr : SIGNED (28 downto 0);
signal prodXY_uid226_pT1_uid211_sinPiZPolyEval_q : std_logic_vector (27 downto 0);
signal prodXY_uid229_pT2_uid217_sinPiZPolyEval_a : std_logic_vector (15 downto 0);
signal prodXY_uid229_pT2_uid217_sinPiZPolyEval_b : std_logic_vector (22 downto 0);
signal prodXY_uid229_pT2_uid217_sinPiZPolyEval_s1 : std_logic_vector (38 downto 0);
signal prodXY_uid229_pT2_uid217_sinPiZPolyEval_pr : SIGNED (39 downto 0);
signal prodXY_uid229_pT2_uid217_sinPiZPolyEval_q : std_logic_vector (38 downto 0);
signal reg_leftShiftStageSel3Dto2_uid123_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_2_q : std_logic_vector (36 downto 0);
signal reg_leftShiftStage1Idx1_uid116_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_3_q : std_logic_vector (36 downto 0);
signal reg_leftShiftStage1Idx2_uid119_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_4_q : std_logic_vector (36 downto 0);
signal reg_leftShiftStage1Idx3_uid122_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_5_q : std_logic_vector (36 downto 0);
signal reg_leftShiftStageSel1Dto0_uid134_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_fxpXFrac_uid43_fpCosPiTest_0_to_fxpXFracZero_uid45_fpCosPiTest_1_q : std_logic_vector (35 downto 0);
signal reg_cosXIsOne_uid36_fpCosPiTest_1_to_bigCond_uid85_fpCosPiTest_1_q : std_logic_vector (0 downto 0);
signal reg_xIsInt_uid80_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_2_q : std_logic_vector (0 downto 0);
signal reg_fxpXFracHalf_uid46_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_3_q : std_logic_vector (0 downto 0);
signal reg_expXIsZero_uid23_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_4_q : std_logic_vector (0 downto 0);
signal reg_xIsHalf_uid83_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_5_q : std_logic_vector (0 downto 0);
signal reg_pad_o_uid16_uid47_fpCosPiTest_0_to_oMFxpXFrac_uid47_fpCosPiTest_0_q : std_logic_vector (36 downto 0);
signal reg_pad_half_uid17_uid52_fpCosPiTest_0_to_z_halfMRRFxPXE_uid52_fpCosPiTest_0_q : std_logic_vector (35 downto 0);
signal reg_rVStage_uid138_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid139_lzcZ_uid56_fpCosPiTest_1_q : std_logic_vector (31 downto 0);
signal reg_cStage_uid142_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid144_lzcZ_uid56_fpCosPiTest_3_q : std_logic_vector (31 downto 0);
signal reg_rVStage_uid146_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid147_lzcZ_uid56_fpCosPiTest_1_q : std_logic_vector (15 downto 0);
signal reg_vStage_uid148_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid150_lzcZ_uid56_fpCosPiTest_3_q : std_logic_vector (15 downto 0);
signal reg_rVStage_uid158_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid159_lzcZ_uid56_fpCosPiTest_1_q : std_logic_vector (3 downto 0);
signal reg_vStage_uid160_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid162_lzcZ_uid56_fpCosPiTest_3_q : std_logic_vector (3 downto 0);
signal reg_vCount_uid153_lzcZ_uid56_fpCosPiTest_0_to_r_uid172_lzcZ_uid56_fpCosPiTest_3_q : std_logic_vector (0 downto 0);
signal reg_leftShiftStageSel3Dto2_uid193_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_2_q : std_logic_vector (34 downto 0);
signal reg_leftShiftStage1Idx1_uid186_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_3_q : std_logic_vector (34 downto 0);
signal reg_leftShiftStage1Idx2_uid189_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_4_q : std_logic_vector (34 downto 0);
signal reg_leftShiftStage1Idx3_uid192_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_5_q : std_logic_vector (34 downto 0);
signal reg_leftShiftStageSel1Dto0_uid204_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_zAddr_uid62_fpCosPiTest_0_to_memoryC2_uid209_sinPiZTableGenerator_0_q : std_logic_vector (6 downto 0);
signal reg_yT1_uid210_sinPiZPolyEval_0_to_prodXY_uid226_pT1_uid211_sinPiZPolyEval_0_q : std_logic_vector (13 downto 0);
signal reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_q : std_logic_vector (15 downto 0);
signal reg_s1_uid212_uid215_sinPiZPolyEval_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_1_q : std_logic_vector (22 downto 0);
signal reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_q : std_logic_vector (23 downto 0);
signal reg_fxpSinRes_uid65_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_1_q : std_logic_vector (24 downto 0);
signal reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q : std_logic_vector (5 downto 0);
signal reg_expP_uid60_fpCosPiTest_0_to_expFracPreRnd_uid71_uid71_fpCosPiTest_1_q : std_logic_vector (7 downto 0);
signal reg_excRNaN_uid84_fpCosPiTest_0_to_fracRPostExc_uid88_fpCosPiTest_1_q : std_logic_vector (0 downto 0);
signal reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q : std_logic_vector (1 downto 0);
signal ld_FxpXFrac35_uid44_fpCosPiTest_b_to_rangeReducedFxPX_uid51_fpCosPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_fxpXFrac_uid43_fpCosPiTest_b_to_rangeReducedFxPX_uid51_fpCosPiTest_c_q : std_logic_vector (35 downto 0);
signal ld_cosXIsOne_uid36_fpCosPiTest_c_to_InvCosXIsOne_uid77_fpCosPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_xEvenInt_uid35_fpCosPiTest_c_to_evenIntCosNotOneFZ_uid79_fpCosPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_exc_R_uid34_fpCosPiTest_q_to_xIsInt_uid80_fpCosPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_reg_cosXIsOne_uid36_fpCosPiTest_1_to_bigCond_uid85_fpCosPiTest_1_q_to_bigCond_uid85_fpCosPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_bigCond_uid85_fpCosPiTest_q_to_fracRPostExc1_uid86_fpCosPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_reg_excRNaN_uid84_fpCosPiTest_0_to_fracRPostExc_uid88_fpCosPiTest_1_q_to_fracRPostExc_uid88_fpCosPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_xIsHalf_uid83_fpCosPiTest_q_to_expRPostExc1_uid91_fpCosPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_expXIsZero_uid23_fpCosPiTest_q_to_xIntOrXZOrCosOne_uid93_fpCosPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_rInfOrNaN_uid92_fpCosPiTest_q_to_join_uid94_fpCosPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_xParityXorHalfParity_uid96_fpCosPiTest_q_to_signRComp_uid99_fpCosPiTest_c_q : std_logic_vector (0 downto 0);
signal ld_fxpXFracHalf_uid46_fpCosPiTest_q_to_InvFxpXFracHalf_uid100_fpCosPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_signR_uid101_fpCosPiTest_q_to_R_uid102_fpCosPiTest_c_q : std_logic_vector (0 downto 0);
signal ld_vCount_uid147_lzcZ_uid56_fpCosPiTest_q_to_r_uid172_lzcZ_uid56_fpCosPiTest_e_q : std_logic_vector (0 downto 0);
signal ld_vCount_uid139_lzcZ_uid56_fpCosPiTest_q_to_r_uid172_lzcZ_uid56_fpCosPiTest_f_q : std_logic_vector (0 downto 0);
signal ld_X18dto0_uid176_alignedZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx1_uid177_alignedZ_uid57_fpCosPiTest_b_q : std_logic_vector (18 downto 0);
signal ld_vStage_uid141_lzcZ_uid56_fpCosPiTest_b_to_leftShiftStage0Idx2_uid180_alignedZ_uid57_fpCosPiTest_b_q : std_logic_vector (2 downto 0);
signal ld_z_uid54_fpCosPiTest_b_to_leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_c_q : std_logic_vector (34 downto 0);
signal ld_reg_yT1_uid210_sinPiZPolyEval_0_to_prodXY_uid226_pT1_uid211_sinPiZPolyEval_0_q_to_prodXY_uid226_pT1_uid211_sinPiZPolyEval_a_q : std_logic_vector (13 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_reset0 : std_logic;
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_ia : std_logic_vector (5 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_iq : std_logic_vector (5 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_q : std_logic_vector (5 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt_eq : std_logic;
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_mem_top_q : std_logic_vector (3 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve : boolean;
attribute preserve of ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_sticky_ena_q : signal is true;
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_reset0 : std_logic;
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_ia : std_logic_vector (1 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_iq : std_logic_vector (1 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_q : std_logic_vector (1 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt_eq : std_logic;
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_mem_top_q : std_logic_vector (4 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_sticky_ena_q : signal is true;
signal ld_X18dto0_uid176_alignedZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx1_uid177_alignedZ_uid57_fpCosPiTest_b_inputreg_q : std_logic_vector (18 downto 0);
signal ld_z_uid54_fpCosPiTest_b_to_leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_c_inputreg_q : std_logic_vector (34 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_reset0 : std_logic;
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_ia : std_logic_vector (6 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_iq : std_logic_vector (6 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_q : std_logic_vector (6 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_sticky_ena_q : signal is true;
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_reset0 : std_logic;
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_ia : std_logic_vector (6 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_aa : std_logic_vector (1 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_ab : std_logic_vector (1 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_iq : std_logic_vector (6 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_q : std_logic_vector (6 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt_q : std_logic_vector(1 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt_i : unsigned(1 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt_eq : std_logic;
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdreg_q : std_logic_vector (1 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_mem_top_q : std_logic_vector (2 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_sticky_ena_q : signal is true;
signal ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_inputreg_q : std_logic_vector (15 downto 0);
signal ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_reset0 : std_logic;
signal ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_ia : std_logic_vector (15 downto 0);
signal ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_aa : std_logic_vector (1 downto 0);
signal ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_ab : std_logic_vector (1 downto 0);
signal ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_iq : std_logic_vector (15 downto 0);
signal ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_q : std_logic_vector (15 downto 0);
signal ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_sticky_ena_q : signal is true;
signal ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_inputreg_q : std_logic_vector (23 downto 0);
signal ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_reset0 : std_logic;
signal ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_ia : std_logic_vector (23 downto 0);
signal ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_aa : std_logic_vector (1 downto 0);
signal ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_ab : std_logic_vector (1 downto 0);
signal ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_iq : std_logic_vector (23 downto 0);
signal ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_q : std_logic_vector (23 downto 0);
signal ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_sticky_ena_q : signal is true;
signal pad_o_uid16_uid47_fpCosPiTest_q : std_logic_vector (36 downto 0);
signal pad_half_uid17_uid52_fpCosPiTest_q : std_logic_vector (35 downto 0);
signal bigCond_uid85_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal bigCond_uid85_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal bigCond_uid85_fpCosPiTest_c : std_logic_vector(0 downto 0);
signal bigCond_uid85_fpCosPiTest_d : std_logic_vector(0 downto 0);
signal bigCond_uid85_fpCosPiTest_f : std_logic_vector(0 downto 0);
signal bigCond_uid85_fpCosPiTest_g : std_logic_vector(0 downto 0);
signal bigCond_uid85_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal InvCosXIsOne_uid77_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal InvCosXIsOne_uid77_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal InvXEvenInt_uid81_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal InvXEvenInt_uid81_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal InvFxpXFracHalf_uid100_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal InvFxpXFracHalf_uid100_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal cstHalfwSwFP1_uid18_fpCosPiTest_q : std_logic_vector (35 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_notEnable_a : std_logic_vector(0 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_notEnable_q : std_logic_vector(0 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdmux_q : std_logic_vector (1 downto 0);
signal expX_uid6_fpCosPiTest_in : std_logic_vector (30 downto 0);
signal expX_uid6_fpCosPiTest_b : std_logic_vector (7 downto 0);
signal fracX_uid7_fpCosPiTest_in : std_logic_vector (22 downto 0);
signal fracX_uid7_fpCosPiTest_b : std_logic_vector (22 downto 0);
signal expXIsZero_uid23_fpCosPiTest_a : std_logic_vector(7 downto 0);
signal expXIsZero_uid23_fpCosPiTest_b : std_logic_vector(7 downto 0);
signal expXIsZero_uid23_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal expXIsMax_uid25_fpCosPiTest_a : std_logic_vector(7 downto 0);
signal expXIsMax_uid25_fpCosPiTest_b : std_logic_vector(7 downto 0);
signal expXIsMax_uid25_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal fracXIsZero_uid27_fpCosPiTest_a : std_logic_vector(22 downto 0);
signal fracXIsZero_uid27_fpCosPiTest_b : std_logic_vector(22 downto 0);
signal fracXIsZero_uid27_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal exc_I_uid28_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal exc_I_uid28_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal exc_I_uid28_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal xEvenInt_uid35_fpCosPiTest_a : std_logic_vector(10 downto 0);
signal xEvenInt_uid35_fpCosPiTest_b : std_logic_vector(10 downto 0);
signal xEvenInt_uid35_fpCosPiTest_o : std_logic_vector (10 downto 0);
signal xEvenInt_uid35_fpCosPiTest_cin : std_logic_vector (0 downto 0);
signal xEvenInt_uid35_fpCosPiTest_c : std_logic_vector (0 downto 0);
signal cosXIsOne_uid36_fpCosPiTest_a : std_logic_vector(10 downto 0);
signal cosXIsOne_uid36_fpCosPiTest_b : std_logic_vector(10 downto 0);
signal cosXIsOne_uid36_fpCosPiTest_o : std_logic_vector (10 downto 0);
signal cosXIsOne_uid36_fpCosPiTest_cin : std_logic_vector (0 downto 0);
signal cosXIsOne_uid36_fpCosPiTest_c : std_logic_vector (0 downto 0);
signal shiftValFxPX_uid38_fpCosPiTest_a : std_logic_vector(8 downto 0);
signal shiftValFxPX_uid38_fpCosPiTest_b : std_logic_vector(8 downto 0);
signal shiftValFxPX_uid38_fpCosPiTest_o : std_logic_vector (8 downto 0);
signal shiftValFxPX_uid38_fpCosPiTest_q : std_logic_vector (8 downto 0);
signal fxpXFracZero_uid45_fpCosPiTest_a : std_logic_vector(35 downto 0);
signal fxpXFracZero_uid45_fpCosPiTest_b : std_logic_vector(35 downto 0);
signal fxpXFracZero_uid45_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal fxpXFracHalf_uid46_fpCosPiTest_a : std_logic_vector(35 downto 0);
signal fxpXFracHalf_uid46_fpCosPiTest_b : std_logic_vector(35 downto 0);
signal fxpXFracHalf_uid46_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal oMFxpXFrac_uid47_fpCosPiTest_a : std_logic_vector(37 downto 0);
signal oMFxpXFrac_uid47_fpCosPiTest_b : std_logic_vector(37 downto 0);
signal oMFxpXFrac_uid47_fpCosPiTest_o : std_logic_vector (37 downto 0);
signal oMFxpXFrac_uid47_fpCosPiTest_q : std_logic_vector (37 downto 0);
signal z_halfMRRFxPXE_uid52_fpCosPiTest_a : std_logic_vector(36 downto 0);
signal z_halfMRRFxPXE_uid52_fpCosPiTest_b : std_logic_vector(36 downto 0);
signal z_halfMRRFxPXE_uid52_fpCosPiTest_o : std_logic_vector (36 downto 0);
signal z_halfMRRFxPXE_uid52_fpCosPiTest_q : std_logic_vector (36 downto 0);
signal expHardCase_uid59_fpCosPiTest_a : std_logic_vector(8 downto 0);
signal expHardCase_uid59_fpCosPiTest_b : std_logic_vector(8 downto 0);
signal expHardCase_uid59_fpCosPiTest_o : std_logic_vector (8 downto 0);
signal expHardCase_uid59_fpCosPiTest_q : std_logic_vector (8 downto 0);
signal fracZCosNotOne_uid78_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal fracZCosNotOne_uid78_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal fracZCosNotOne_uid78_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal evenIntCosNotOneFZ_uid79_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal evenIntCosNotOneFZ_uid79_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal evenIntCosNotOneFZ_uid79_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal xIsInt_uid80_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal xIsInt_uid80_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal xIsInt_uid80_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal xIsHalf_uid83_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal xIsHalf_uid83_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal xIsHalf_uid83_fpCosPiTest_c : std_logic_vector(0 downto 0);
signal xIsHalf_uid83_fpCosPiTest_d : std_logic_vector(0 downto 0);
signal xIsHalf_uid83_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal fracRPostExc_uid88_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal fracRPostExc_uid88_fpCosPiTest_q : std_logic_vector (22 downto 0);
signal xIntOrXZOrCosOne_uid93_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal xIntOrXZOrCosOne_uid93_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal xIntOrXZOrCosOne_uid93_fpCosPiTest_c : std_logic_vector(0 downto 0);
signal xIntOrXZOrCosOne_uid93_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal expRPostExc_uid95_fpCosPiTest_s : std_logic_vector (1 downto 0);
signal expRPostExc_uid95_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_q : std_logic_vector (36 downto 0);
signal vCount_uid139_lzcZ_uid56_fpCosPiTest_a : std_logic_vector(31 downto 0);
signal vCount_uid139_lzcZ_uid56_fpCosPiTest_b : std_logic_vector(31 downto 0);
signal vCount_uid139_lzcZ_uid56_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid144_lzcZ_uid56_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid144_lzcZ_uid56_fpCosPiTest_q : std_logic_vector (31 downto 0);
signal vCount_uid147_lzcZ_uid56_fpCosPiTest_a : std_logic_vector(15 downto 0);
signal vCount_uid147_lzcZ_uid56_fpCosPiTest_b : std_logic_vector(15 downto 0);
signal vCount_uid147_lzcZ_uid56_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid150_lzcZ_uid56_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid150_lzcZ_uid56_fpCosPiTest_q : std_logic_vector (15 downto 0);
signal vCount_uid159_lzcZ_uid56_fpCosPiTest_a : std_logic_vector(3 downto 0);
signal vCount_uid159_lzcZ_uid56_fpCosPiTest_b : std_logic_vector(3 downto 0);
signal vCount_uid159_lzcZ_uid56_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid162_lzcZ_uid56_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid162_lzcZ_uid56_fpCosPiTest_q : std_logic_vector (3 downto 0);
signal leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_q : std_logic_vector (34 downto 0);
signal memoryC0_uid207_sinPiZTableGenerator_q : std_logic_vector(28 downto 0);
signal memoryC1_uid208_sinPiZTableGenerator_q : std_logic_vector(20 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal leftShiftStage0Idx1_uid177_alignedZ_uid57_fpCosPiTest_q : std_logic_vector (34 downto 0);
signal leftShiftStage0Idx2_uid180_alignedZ_uid57_fpCosPiTest_q : std_logic_vector (34 downto 0);
signal prodXYTruncFR_uid224_mul2xSinRes_uid66_fpCosPiTest_in : std_logic_vector (48 downto 0);
signal prodXYTruncFR_uid224_mul2xSinRes_uid66_fpCosPiTest_b : std_logic_vector (25 downto 0);
signal prodXYTruncFR_uid227_pT1_uid211_sinPiZPolyEval_in : std_logic_vector (27 downto 0);
signal prodXYTruncFR_uid227_pT1_uid211_sinPiZPolyEval_b : std_logic_vector (14 downto 0);
signal prodXYTruncFR_uid230_pT2_uid217_sinPiZPolyEval_in : std_logic_vector (38 downto 0);
signal prodXYTruncFR_uid230_pT2_uid217_sinPiZPolyEval_b : std_logic_vector (23 downto 0);
signal join_uid94_fpCosPiTest_q : std_logic_vector (1 downto 0);
signal R_uid102_fpCosPiTest_q : std_logic_vector (31 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_cmp_a : std_logic_vector(3 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_cmp_b : std_logic_vector(3 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_cmp_a : std_logic_vector(4 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_cmp_b : std_logic_vector(4 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_cmp_a : std_logic_vector(2 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_cmp_b : std_logic_vector(2 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_nor_q : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_nor_q : std_logic_vector(0 downto 0);
signal oFracX_uid37_uid37_fpCosPiTest_q : std_logic_vector (23 downto 0);
signal InvExpXIsZero_uid33_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid33_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid29_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid29_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal InvExc_I_uid32_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal InvExc_I_uid32_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal fxpShifterBits_uid40_fpCosPiTest_in : std_logic_vector (5 downto 0);
signal fxpShifterBits_uid40_fpCosPiTest_b : std_logic_vector (5 downto 0);
signal oMFxpXFrac_uid49_fpCosPiTest_in : std_logic_vector (35 downto 0);
signal oMFxpXFrac_uid49_fpCosPiTest_b : std_logic_vector (35 downto 0);
signal z_uid54_fpCosPiTest_in : std_logic_vector (34 downto 0);
signal z_uid54_fpCosPiTest_b : std_logic_vector (34 downto 0);
signal expP_uid60_fpCosPiTest_in : std_logic_vector (7 downto 0);
signal expP_uid60_fpCosPiTest_b : std_logic_vector (7 downto 0);
signal LeftShiftStage135dto0_uid126_fxpX_uid41_fpCosPiTest_in : std_logic_vector (35 downto 0);
signal LeftShiftStage135dto0_uid126_fxpX_uid41_fpCosPiTest_b : std_logic_vector (35 downto 0);
signal LeftShiftStage134dto0_uid129_fxpX_uid41_fpCosPiTest_in : std_logic_vector (34 downto 0);
signal LeftShiftStage134dto0_uid129_fxpX_uid41_fpCosPiTest_b : std_logic_vector (34 downto 0);
signal LeftShiftStage133dto0_uid132_fxpX_uid41_fpCosPiTest_in : std_logic_vector (33 downto 0);
signal LeftShiftStage133dto0_uid132_fxpX_uid41_fpCosPiTest_b : std_logic_vector (33 downto 0);
signal rVStage_uid146_lzcZ_uid56_fpCosPiTest_in : std_logic_vector (31 downto 0);
signal rVStage_uid146_lzcZ_uid56_fpCosPiTest_b : std_logic_vector (15 downto 0);
signal vStage_uid148_lzcZ_uid56_fpCosPiTest_in : std_logic_vector (15 downto 0);
signal vStage_uid148_lzcZ_uid56_fpCosPiTest_b : std_logic_vector (15 downto 0);
signal rVStage_uid152_lzcZ_uid56_fpCosPiTest_in : std_logic_vector (15 downto 0);
signal rVStage_uid152_lzcZ_uid56_fpCosPiTest_b : std_logic_vector (7 downto 0);
signal vStage_uid154_lzcZ_uid56_fpCosPiTest_in : std_logic_vector (7 downto 0);
signal vStage_uid154_lzcZ_uid56_fpCosPiTest_b : std_logic_vector (7 downto 0);
signal rVStage_uid164_lzcZ_uid56_fpCosPiTest_in : std_logic_vector (3 downto 0);
signal rVStage_uid164_lzcZ_uid56_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal vStage_uid166_lzcZ_uid56_fpCosPiTest_in : std_logic_vector (1 downto 0);
signal vStage_uid166_lzcZ_uid56_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal LeftShiftStage133dto0_uid196_alignedZ_uid57_fpCosPiTest_in : std_logic_vector (33 downto 0);
signal LeftShiftStage133dto0_uid196_alignedZ_uid57_fpCosPiTest_b : std_logic_vector (33 downto 0);
signal LeftShiftStage132dto0_uid199_alignedZ_uid57_fpCosPiTest_in : std_logic_vector (32 downto 0);
signal LeftShiftStage132dto0_uid199_alignedZ_uid57_fpCosPiTest_b : std_logic_vector (32 downto 0);
signal LeftShiftStage131dto0_uid202_alignedZ_uid57_fpCosPiTest_in : std_logic_vector (31 downto 0);
signal LeftShiftStage131dto0_uid202_alignedZ_uid57_fpCosPiTest_b : std_logic_vector (31 downto 0);
signal normBit_uid67_fpCosPiTest_in : std_logic_vector (25 downto 0);
signal normBit_uid67_fpCosPiTest_b : std_logic_vector (0 downto 0);
signal highRes_uid68_fpCosPiTest_in : std_logic_vector (24 downto 0);
signal highRes_uid68_fpCosPiTest_b : std_logic_vector (23 downto 0);
signal lowRes_uid69_fpCosPiTest_in : std_logic_vector (23 downto 0);
signal lowRes_uid69_fpCosPiTest_b : std_logic_vector (23 downto 0);
signal lowRangeB_uid212_sinPiZPolyEval_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid212_sinPiZPolyEval_b : std_logic_vector (0 downto 0);
signal highBBits_uid213_sinPiZPolyEval_in : std_logic_vector (14 downto 0);
signal highBBits_uid213_sinPiZPolyEval_b : std_logic_vector (13 downto 0);
signal lowRangeB_uid218_sinPiZPolyEval_in : std_logic_vector (1 downto 0);
signal lowRangeB_uid218_sinPiZPolyEval_b : std_logic_vector (1 downto 0);
signal highBBits_uid219_sinPiZPolyEval_in : std_logic_vector (23 downto 0);
signal highBBits_uid219_sinPiZPolyEval_b : std_logic_vector (21 downto 0);
signal oFracXExt_uid39_fpCosPiTest_q : std_logic_vector (36 downto 0);
signal exc_N_uid30_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal exc_N_uid30_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal exc_N_uid30_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal leftShiftStageSel5Dto4_uid112_fxpX_uid41_fpCosPiTest_in : std_logic_vector (5 downto 0);
signal leftShiftStageSel5Dto4_uid112_fxpX_uid41_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel3Dto2_uid123_fxpX_uid41_fpCosPiTest_in : std_logic_vector (3 downto 0);
signal leftShiftStageSel3Dto2_uid123_fxpX_uid41_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid134_fxpX_uid41_fpCosPiTest_in : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid134_fxpX_uid41_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal zAddr_uid62_fpCosPiTest_in : std_logic_vector (34 downto 0);
signal zAddr_uid62_fpCosPiTest_b : std_logic_vector (6 downto 0);
signal zPPolyEval_uid63_fpCosPiTest_in : std_logic_vector (27 downto 0);
signal zPPolyEval_uid63_fpCosPiTest_b : std_logic_vector (15 downto 0);
signal rVStage_uid138_lzcZ_uid56_fpCosPiTest_in : std_logic_vector (34 downto 0);
signal rVStage_uid138_lzcZ_uid56_fpCosPiTest_b : std_logic_vector (31 downto 0);
signal vStage_uid141_lzcZ_uid56_fpCosPiTest_in : std_logic_vector (2 downto 0);
signal vStage_uid141_lzcZ_uid56_fpCosPiTest_b : std_logic_vector (2 downto 0);
signal X18dto0_uid176_alignedZ_uid57_fpCosPiTest_in : std_logic_vector (18 downto 0);
signal X18dto0_uid176_alignedZ_uid57_fpCosPiTest_b : std_logic_vector (18 downto 0);
signal leftShiftStage2Idx1_uid127_fxpX_uid41_fpCosPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage2Idx2_uid130_fxpX_uid41_fpCosPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage2Idx3_uid133_fxpX_uid41_fpCosPiTest_q : std_logic_vector (36 downto 0);
signal vCount_uid153_lzcZ_uid56_fpCosPiTest_a : std_logic_vector(7 downto 0);
signal vCount_uid153_lzcZ_uid56_fpCosPiTest_b : std_logic_vector(7 downto 0);
signal vCount_uid153_lzcZ_uid56_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid156_lzcZ_uid56_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid156_lzcZ_uid56_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal vCount_uid165_lzcZ_uid56_fpCosPiTest_a : std_logic_vector(1 downto 0);
signal vCount_uid165_lzcZ_uid56_fpCosPiTest_b : std_logic_vector(1 downto 0);
signal vCount_uid165_lzcZ_uid56_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid168_lzcZ_uid56_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid168_lzcZ_uid56_fpCosPiTest_q : std_logic_vector (1 downto 0);
signal leftShiftStage2Idx1_uid197_alignedZ_uid57_fpCosPiTest_q : std_logic_vector (34 downto 0);
signal leftShiftStage2Idx2_uid200_alignedZ_uid57_fpCosPiTest_q : std_logic_vector (34 downto 0);
signal leftShiftStage2Idx3_uid203_alignedZ_uid57_fpCosPiTest_q : std_logic_vector (34 downto 0);
signal fracRCompPreRnd_uid70_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal fracRCompPreRnd_uid70_fpCosPiTest_q : std_logic_vector (23 downto 0);
signal rndExpUpdate_uid72_uid73_fpCosPiTest_q : std_logic_vector (24 downto 0);
signal sumAHighB_uid214_sinPiZPolyEval_a : std_logic_vector(21 downto 0);
signal sumAHighB_uid214_sinPiZPolyEval_b : std_logic_vector(21 downto 0);
signal sumAHighB_uid214_sinPiZPolyEval_o : std_logic_vector (21 downto 0);
signal sumAHighB_uid214_sinPiZPolyEval_q : std_logic_vector (21 downto 0);
signal sumAHighB_uid220_sinPiZPolyEval_a : std_logic_vector(29 downto 0);
signal sumAHighB_uid220_sinPiZPolyEval_b : std_logic_vector(29 downto 0);
signal sumAHighB_uid220_sinPiZPolyEval_o : std_logic_vector (29 downto 0);
signal sumAHighB_uid220_sinPiZPolyEval_q : std_logic_vector (29 downto 0);
signal X20dto0_uid106_fxpX_uid41_fpCosPiTest_in : std_logic_vector (20 downto 0);
signal X20dto0_uid106_fxpX_uid41_fpCosPiTest_b : std_logic_vector (20 downto 0);
signal X4dto0_uid109_fxpX_uid41_fpCosPiTest_in : std_logic_vector (4 downto 0);
signal X4dto0_uid109_fxpX_uid41_fpCosPiTest_b : std_logic_vector (4 downto 0);
signal InvExc_N_uid31_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal InvExc_N_uid31_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal excRNaN_uid84_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal excRNaN_uid84_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal excRNaN_uid84_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal yT1_uid210_sinPiZPolyEval_in : std_logic_vector (15 downto 0);
signal yT1_uid210_sinPiZPolyEval_b : std_logic_vector (13 downto 0);
signal cStage_uid142_lzcZ_uid56_fpCosPiTest_q : std_logic_vector (31 downto 0);
signal leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest_q : std_logic_vector (36 downto 0);
signal rVStage_uid158_lzcZ_uid56_fpCosPiTest_in : std_logic_vector (7 downto 0);
signal rVStage_uid158_lzcZ_uid56_fpCosPiTest_b : std_logic_vector (3 downto 0);
signal vStage_uid160_lzcZ_uid56_fpCosPiTest_in : std_logic_vector (3 downto 0);
signal vStage_uid160_lzcZ_uid56_fpCosPiTest_b : std_logic_vector (3 downto 0);
signal rVStage_uid170_lzcZ_uid56_fpCosPiTest_in : std_logic_vector (1 downto 0);
signal rVStage_uid170_lzcZ_uid56_fpCosPiTest_b : std_logic_vector (0 downto 0);
signal leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest_q : std_logic_vector (34 downto 0);
signal expFracPreRnd_uid71_uid71_fpCosPiTest_q : std_logic_vector (31 downto 0);
signal expFracComp_uid74_fpCosPiTest_a : std_logic_vector(32 downto 0);
signal expFracComp_uid74_fpCosPiTest_b : std_logic_vector(32 downto 0);
signal expFracComp_uid74_fpCosPiTest_o : std_logic_vector (32 downto 0);
signal expFracComp_uid74_fpCosPiTest_q : std_logic_vector (32 downto 0);
signal s1_uid212_uid215_sinPiZPolyEval_q : std_logic_vector (22 downto 0);
signal s2_uid218_uid221_sinPiZPolyEval_q : std_logic_vector (31 downto 0);
signal leftShiftStage0Idx1_uid107_fxpX_uid41_fpCosPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage0Idx2_uid110_fxpX_uid41_fpCosPiTest_q : std_logic_vector (36 downto 0);
signal exc_R_uid34_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal exc_R_uid34_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal exc_R_uid34_fpCosPiTest_c : std_logic_vector(0 downto 0);
signal exc_R_uid34_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal rInfOrNaN_uid92_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal rInfOrNaN_uid92_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal rInfOrNaN_uid92_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal FxpX36_uid42_fpCosPiTest_in : std_logic_vector (36 downto 0);
signal FxpX36_uid42_fpCosPiTest_b : std_logic_vector (0 downto 0);
signal fxpXFrac_uid43_fpCosPiTest_in : std_logic_vector (35 downto 0);
signal fxpXFrac_uid43_fpCosPiTest_b : std_logic_vector (35 downto 0);
signal vCount_uid171_lzcZ_uid56_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal vCount_uid171_lzcZ_uid56_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal vCount_uid171_lzcZ_uid56_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal alignedZLow_uid58_fpCosPiTest_in : std_logic_vector (34 downto 0);
signal alignedZLow_uid58_fpCosPiTest_b : std_logic_vector (23 downto 0);
signal fracRComp_uid75_fpCosPiTest_in : std_logic_vector (23 downto 0);
signal fracRComp_uid75_fpCosPiTest_b : std_logic_vector (22 downto 0);
signal expRComp_uid76_fpCosPiTest_in : std_logic_vector (31 downto 0);
signal expRComp_uid76_fpCosPiTest_b : std_logic_vector (7 downto 0);
signal fxpSinRes_uid65_fpCosPiTest_in : std_logic_vector (29 downto 0);
signal fxpSinRes_uid65_fpCosPiTest_b : std_logic_vector (24 downto 0);
signal leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_q : std_logic_vector (36 downto 0);
signal FxpXFrac35_uid44_fpCosPiTest_in : std_logic_vector (35 downto 0);
signal FxpXFrac35_uid44_fpCosPiTest_b : std_logic_vector (0 downto 0);
signal r_uid172_lzcZ_uid56_fpCosPiTest_q : std_logic_vector (5 downto 0);
signal LeftShiftStage032dto0_uid115_fxpX_uid41_fpCosPiTest_in : std_logic_vector (32 downto 0);
signal LeftShiftStage032dto0_uid115_fxpX_uid41_fpCosPiTest_b : std_logic_vector (32 downto 0);
signal LeftShiftStage028dto0_uid118_fxpX_uid41_fpCosPiTest_in : std_logic_vector (28 downto 0);
signal LeftShiftStage028dto0_uid118_fxpX_uid41_fpCosPiTest_b : std_logic_vector (28 downto 0);
signal LeftShiftStage024dto0_uid121_fxpX_uid41_fpCosPiTest_in : std_logic_vector (24 downto 0);
signal LeftShiftStage024dto0_uid121_fxpX_uid41_fpCosPiTest_b : std_logic_vector (24 downto 0);
signal xParityXorHalfParity_uid96_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal xParityXorHalfParity_uid96_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal xParityXorHalfParity_uid96_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal leftShiftStageSel5Dto4_uid182_alignedZ_uid57_fpCosPiTest_in : std_logic_vector (5 downto 0);
signal leftShiftStageSel5Dto4_uid182_alignedZ_uid57_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel3Dto2_uid193_alignedZ_uid57_fpCosPiTest_in : std_logic_vector (3 downto 0);
signal leftShiftStageSel3Dto2_uid193_alignedZ_uid57_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid204_alignedZ_uid57_fpCosPiTest_in : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid204_alignedZ_uid57_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStage1Idx1_uid116_fxpX_uid41_fpCosPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage1Idx2_uid119_fxpX_uid41_fpCosPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage1Idx3_uid122_fxpX_uid41_fpCosPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_q : std_logic_vector (34 downto 0);
signal LeftShiftStage030dto0_uid185_alignedZ_uid57_fpCosPiTest_in : std_logic_vector (30 downto 0);
signal LeftShiftStage030dto0_uid185_alignedZ_uid57_fpCosPiTest_b : std_logic_vector (30 downto 0);
signal LeftShiftStage026dto0_uid188_alignedZ_uid57_fpCosPiTest_in : std_logic_vector (26 downto 0);
signal LeftShiftStage026dto0_uid188_alignedZ_uid57_fpCosPiTest_b : std_logic_vector (26 downto 0);
signal LeftShiftStage022dto0_uid191_alignedZ_uid57_fpCosPiTest_in : std_logic_vector (22 downto 0);
signal LeftShiftStage022dto0_uid191_alignedZ_uid57_fpCosPiTest_b : std_logic_vector (22 downto 0);
signal leftShiftStage1Idx1_uid186_alignedZ_uid57_fpCosPiTest_q : std_logic_vector (34 downto 0);
signal leftShiftStage1Idx2_uid189_alignedZ_uid57_fpCosPiTest_q : std_logic_vector (34 downto 0);
signal leftShiftStage1Idx3_uid192_alignedZ_uid57_fpCosPiTest_q : std_logic_vector (34 downto 0);
begin
--xIn(GPIN,3)@0
--LeftShiftStage133dto0_uid132_fxpX_uid41_fpCosPiTest(BITSELECT,131)@1
LeftShiftStage133dto0_uid132_fxpX_uid41_fpCosPiTest_in <= leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_q(33 downto 0);
LeftShiftStage133dto0_uid132_fxpX_uid41_fpCosPiTest_b <= LeftShiftStage133dto0_uid132_fxpX_uid41_fpCosPiTest_in(33 downto 0);
--leftShiftStage2Idx3Pad3_uid131_fxpX_uid41_fpCosPiTest(CONSTANT,130)
leftShiftStage2Idx3Pad3_uid131_fxpX_uid41_fpCosPiTest_q <= "000";
--leftShiftStage2Idx3_uid133_fxpX_uid41_fpCosPiTest(BITJOIN,132)@1
leftShiftStage2Idx3_uid133_fxpX_uid41_fpCosPiTest_q <= LeftShiftStage133dto0_uid132_fxpX_uid41_fpCosPiTest_b & leftShiftStage2Idx3Pad3_uid131_fxpX_uid41_fpCosPiTest_q;
--LeftShiftStage134dto0_uid129_fxpX_uid41_fpCosPiTest(BITSELECT,128)@1
LeftShiftStage134dto0_uid129_fxpX_uid41_fpCosPiTest_in <= leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_q(34 downto 0);
LeftShiftStage134dto0_uid129_fxpX_uid41_fpCosPiTest_b <= LeftShiftStage134dto0_uid129_fxpX_uid41_fpCosPiTest_in(34 downto 0);
--leftShiftStage2Idx2Pad2_uid128_fxpX_uid41_fpCosPiTest(CONSTANT,127)
leftShiftStage2Idx2Pad2_uid128_fxpX_uid41_fpCosPiTest_q <= "00";
--leftShiftStage2Idx2_uid130_fxpX_uid41_fpCosPiTest(BITJOIN,129)@1
leftShiftStage2Idx2_uid130_fxpX_uid41_fpCosPiTest_q <= LeftShiftStage134dto0_uid129_fxpX_uid41_fpCosPiTest_b & leftShiftStage2Idx2Pad2_uid128_fxpX_uid41_fpCosPiTest_q;
--LeftShiftStage135dto0_uid126_fxpX_uid41_fpCosPiTest(BITSELECT,125)@1
LeftShiftStage135dto0_uid126_fxpX_uid41_fpCosPiTest_in <= leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_q(35 downto 0);
LeftShiftStage135dto0_uid126_fxpX_uid41_fpCosPiTest_b <= LeftShiftStage135dto0_uid126_fxpX_uid41_fpCosPiTest_in(35 downto 0);
--GND(CONSTANT,0)
GND_q <= "0";
--leftShiftStage2Idx1_uid127_fxpX_uid41_fpCosPiTest(BITJOIN,126)@1
leftShiftStage2Idx1_uid127_fxpX_uid41_fpCosPiTest_q <= LeftShiftStage135dto0_uid126_fxpX_uid41_fpCosPiTest_b & GND_q;
--leftShiftStage0Idx3_uid111_fxpX_uid41_fpCosPiTest(CONSTANT,110)
leftShiftStage0Idx3_uid111_fxpX_uid41_fpCosPiTest_q <= "0000000000000000000000000000000000000";
--X4dto0_uid109_fxpX_uid41_fpCosPiTest(BITSELECT,108)@0
X4dto0_uid109_fxpX_uid41_fpCosPiTest_in <= oFracXExt_uid39_fpCosPiTest_q(4 downto 0);
X4dto0_uid109_fxpX_uid41_fpCosPiTest_b <= X4dto0_uid109_fxpX_uid41_fpCosPiTest_in(4 downto 0);
--leftShiftStage0Idx2Pad32_uid108_fxpX_uid41_fpCosPiTest(CONSTANT,107)
leftShiftStage0Idx2Pad32_uid108_fxpX_uid41_fpCosPiTest_q <= "00000000000000000000000000000000";
--leftShiftStage0Idx2_uid110_fxpX_uid41_fpCosPiTest(BITJOIN,109)@0
leftShiftStage0Idx2_uid110_fxpX_uid41_fpCosPiTest_q <= X4dto0_uid109_fxpX_uid41_fpCosPiTest_b & leftShiftStage0Idx2Pad32_uid108_fxpX_uid41_fpCosPiTest_q;
--X20dto0_uid106_fxpX_uid41_fpCosPiTest(BITSELECT,105)@0
X20dto0_uid106_fxpX_uid41_fpCosPiTest_in <= oFracXExt_uid39_fpCosPiTest_q(20 downto 0);
X20dto0_uid106_fxpX_uid41_fpCosPiTest_b <= X20dto0_uid106_fxpX_uid41_fpCosPiTest_in(20 downto 0);
--leftShiftStage0Idx1Pad16_uid105_fxpX_uid41_fpCosPiTest(CONSTANT,104)
leftShiftStage0Idx1Pad16_uid105_fxpX_uid41_fpCosPiTest_q <= "0000000000000000";
--leftShiftStage0Idx1_uid107_fxpX_uid41_fpCosPiTest(BITJOIN,106)@0
leftShiftStage0Idx1_uid107_fxpX_uid41_fpCosPiTest_q <= X20dto0_uid106_fxpX_uid41_fpCosPiTest_b & leftShiftStage0Idx1Pad16_uid105_fxpX_uid41_fpCosPiTest_q;
--cst01pWShift_uid14_fpCosPiTest(CONSTANT,13)
cst01pWShift_uid14_fpCosPiTest_q <= "0000000000000";
--VCC(CONSTANT,1)
VCC_q <= "1";
--fracX_uid7_fpCosPiTest(BITSELECT,6)@0
fracX_uid7_fpCosPiTest_in <= a(22 downto 0);
fracX_uid7_fpCosPiTest_b <= fracX_uid7_fpCosPiTest_in(22 downto 0);
--oFracX_uid37_uid37_fpCosPiTest(BITJOIN,36)@0
oFracX_uid37_uid37_fpCosPiTest_q <= VCC_q & fracX_uid7_fpCosPiTest_b;
--oFracXExt_uid39_fpCosPiTest(BITJOIN,38)@0
oFracXExt_uid39_fpCosPiTest_q <= cst01pWShift_uid14_fpCosPiTest_q & oFracX_uid37_uid37_fpCosPiTest_q;
--biasMwShiftMO_uid13_fpCosPiTest(CONSTANT,12)
biasMwShiftMO_uid13_fpCosPiTest_q <= "01110010";
--expX_uid6_fpCosPiTest(BITSELECT,5)@0
expX_uid6_fpCosPiTest_in <= a(30 downto 0);
expX_uid6_fpCosPiTest_b <= expX_uid6_fpCosPiTest_in(30 downto 23);
--shiftValFxPX_uid38_fpCosPiTest(SUB,37)@0
shiftValFxPX_uid38_fpCosPiTest_a <= STD_LOGIC_VECTOR("0" & expX_uid6_fpCosPiTest_b);
shiftValFxPX_uid38_fpCosPiTest_b <= STD_LOGIC_VECTOR("0" & biasMwShiftMO_uid13_fpCosPiTest_q);
shiftValFxPX_uid38_fpCosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(shiftValFxPX_uid38_fpCosPiTest_a) - UNSIGNED(shiftValFxPX_uid38_fpCosPiTest_b));
shiftValFxPX_uid38_fpCosPiTest_q <= shiftValFxPX_uid38_fpCosPiTest_o(8 downto 0);
--fxpShifterBits_uid40_fpCosPiTest(BITSELECT,39)@0
fxpShifterBits_uid40_fpCosPiTest_in <= shiftValFxPX_uid38_fpCosPiTest_q(5 downto 0);
fxpShifterBits_uid40_fpCosPiTest_b <= fxpShifterBits_uid40_fpCosPiTest_in(5 downto 0);
--leftShiftStageSel5Dto4_uid112_fxpX_uid41_fpCosPiTest(BITSELECT,111)@0
leftShiftStageSel5Dto4_uid112_fxpX_uid41_fpCosPiTest_in <= fxpShifterBits_uid40_fpCosPiTest_b;
leftShiftStageSel5Dto4_uid112_fxpX_uid41_fpCosPiTest_b <= leftShiftStageSel5Dto4_uid112_fxpX_uid41_fpCosPiTest_in(5 downto 4);
--leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest(MUX,112)@0
leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_s <= leftShiftStageSel5Dto4_uid112_fxpX_uid41_fpCosPiTest_b;
leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest: PROCESS (leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_s, en, oFracXExt_uid39_fpCosPiTest_q, leftShiftStage0Idx1_uid107_fxpX_uid41_fpCosPiTest_q, leftShiftStage0Idx2_uid110_fxpX_uid41_fpCosPiTest_q, leftShiftStage0Idx3_uid111_fxpX_uid41_fpCosPiTest_q)
BEGIN
CASE leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_s IS
WHEN "00" => leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_q <= oFracXExt_uid39_fpCosPiTest_q;
WHEN "01" => leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_q <= leftShiftStage0Idx1_uid107_fxpX_uid41_fpCosPiTest_q;
WHEN "10" => leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_q <= leftShiftStage0Idx2_uid110_fxpX_uid41_fpCosPiTest_q;
WHEN "11" => leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_q <= leftShiftStage0Idx3_uid111_fxpX_uid41_fpCosPiTest_q;
WHEN OTHERS => leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage024dto0_uid121_fxpX_uid41_fpCosPiTest(BITSELECT,120)@0
LeftShiftStage024dto0_uid121_fxpX_uid41_fpCosPiTest_in <= leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_q(24 downto 0);
LeftShiftStage024dto0_uid121_fxpX_uid41_fpCosPiTest_b <= LeftShiftStage024dto0_uid121_fxpX_uid41_fpCosPiTest_in(24 downto 0);
--leftShiftStage1Idx3Pad12_uid120_fxpX_uid41_fpCosPiTest(CONSTANT,119)
leftShiftStage1Idx3Pad12_uid120_fxpX_uid41_fpCosPiTest_q <= "000000000000";
--leftShiftStage1Idx3_uid122_fxpX_uid41_fpCosPiTest(BITJOIN,121)@0
leftShiftStage1Idx3_uid122_fxpX_uid41_fpCosPiTest_q <= LeftShiftStage024dto0_uid121_fxpX_uid41_fpCosPiTest_b & leftShiftStage1Idx3Pad12_uid120_fxpX_uid41_fpCosPiTest_q;
--reg_leftShiftStage1Idx3_uid122_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_5(REG,235)@0
reg_leftShiftStage1Idx3_uid122_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx3_uid122_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_5_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx3_uid122_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_5_q <= leftShiftStage1Idx3_uid122_fxpX_uid41_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage028dto0_uid118_fxpX_uid41_fpCosPiTest(BITSELECT,117)@0
LeftShiftStage028dto0_uid118_fxpX_uid41_fpCosPiTest_in <= leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_q(28 downto 0);
LeftShiftStage028dto0_uid118_fxpX_uid41_fpCosPiTest_b <= LeftShiftStage028dto0_uid118_fxpX_uid41_fpCosPiTest_in(28 downto 0);
--cstAllZWE_uid21_fpCosPiTest(CONSTANT,20)
cstAllZWE_uid21_fpCosPiTest_q <= "00000000";
--leftShiftStage1Idx2_uid119_fxpX_uid41_fpCosPiTest(BITJOIN,118)@0
leftShiftStage1Idx2_uid119_fxpX_uid41_fpCosPiTest_q <= LeftShiftStage028dto0_uid118_fxpX_uid41_fpCosPiTest_b & cstAllZWE_uid21_fpCosPiTest_q;
--reg_leftShiftStage1Idx2_uid119_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_4(REG,234)@0
reg_leftShiftStage1Idx2_uid119_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx2_uid119_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_4_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx2_uid119_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_4_q <= leftShiftStage1Idx2_uid119_fxpX_uid41_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage032dto0_uid115_fxpX_uid41_fpCosPiTest(BITSELECT,114)@0
LeftShiftStage032dto0_uid115_fxpX_uid41_fpCosPiTest_in <= leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_q(32 downto 0);
LeftShiftStage032dto0_uid115_fxpX_uid41_fpCosPiTest_b <= LeftShiftStage032dto0_uid115_fxpX_uid41_fpCosPiTest_in(32 downto 0);
--leftShiftStage1Idx1Pad4_uid114_fxpX_uid41_fpCosPiTest(CONSTANT,113)
leftShiftStage1Idx1Pad4_uid114_fxpX_uid41_fpCosPiTest_q <= "0000";
--leftShiftStage1Idx1_uid116_fxpX_uid41_fpCosPiTest(BITJOIN,115)@0
leftShiftStage1Idx1_uid116_fxpX_uid41_fpCosPiTest_q <= LeftShiftStage032dto0_uid115_fxpX_uid41_fpCosPiTest_b & leftShiftStage1Idx1Pad4_uid114_fxpX_uid41_fpCosPiTest_q;
--reg_leftShiftStage1Idx1_uid116_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_3(REG,233)@0
reg_leftShiftStage1Idx1_uid116_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx1_uid116_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_3_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx1_uid116_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_3_q <= leftShiftStage1Idx1_uid116_fxpX_uid41_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--reg_leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_2(REG,232)@0
reg_leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_2_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_2_q <= leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel3Dto2_uid123_fxpX_uid41_fpCosPiTest(BITSELECT,122)@0
leftShiftStageSel3Dto2_uid123_fxpX_uid41_fpCosPiTest_in <= fxpShifterBits_uid40_fpCosPiTest_b(3 downto 0);
leftShiftStageSel3Dto2_uid123_fxpX_uid41_fpCosPiTest_b <= leftShiftStageSel3Dto2_uid123_fxpX_uid41_fpCosPiTest_in(3 downto 2);
--reg_leftShiftStageSel3Dto2_uid123_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_1(REG,231)@0
reg_leftShiftStageSel3Dto2_uid123_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel3Dto2_uid123_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel3Dto2_uid123_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_1_q <= leftShiftStageSel3Dto2_uid123_fxpX_uid41_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest(MUX,123)@1
leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_s <= reg_leftShiftStageSel3Dto2_uid123_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_1_q;
leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest: PROCESS (leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_s, en, reg_leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_2_q, reg_leftShiftStage1Idx1_uid116_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_3_q, reg_leftShiftStage1Idx2_uid119_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_4_q, reg_leftShiftStage1Idx3_uid122_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_5_q)
BEGIN
CASE leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_s IS
WHEN "00" => leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_q <= reg_leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_2_q;
WHEN "01" => leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_q <= reg_leftShiftStage1Idx1_uid116_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_3_q;
WHEN "10" => leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_q <= reg_leftShiftStage1Idx2_uid119_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_4_q;
WHEN "11" => leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_q <= reg_leftShiftStage1Idx3_uid122_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_5_q;
WHEN OTHERS => leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--leftShiftStageSel1Dto0_uid134_fxpX_uid41_fpCosPiTest(BITSELECT,133)@0
leftShiftStageSel1Dto0_uid134_fxpX_uid41_fpCosPiTest_in <= fxpShifterBits_uid40_fpCosPiTest_b(1 downto 0);
leftShiftStageSel1Dto0_uid134_fxpX_uid41_fpCosPiTest_b <= leftShiftStageSel1Dto0_uid134_fxpX_uid41_fpCosPiTest_in(1 downto 0);
--reg_leftShiftStageSel1Dto0_uid134_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest_1(REG,236)@0
reg_leftShiftStageSel1Dto0_uid134_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel1Dto0_uid134_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel1Dto0_uid134_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest_1_q <= leftShiftStageSel1Dto0_uid134_fxpX_uid41_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest(MUX,134)@1
leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest_s <= reg_leftShiftStageSel1Dto0_uid134_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest_1_q;
leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest: PROCESS (leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest_s, en, leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_q, leftShiftStage2Idx1_uid127_fxpX_uid41_fpCosPiTest_q, leftShiftStage2Idx2_uid130_fxpX_uid41_fpCosPiTest_q, leftShiftStage2Idx3_uid133_fxpX_uid41_fpCosPiTest_q)
BEGIN
CASE leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest_s IS
WHEN "00" => leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest_q <= leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_q;
WHEN "01" => leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest_q <= leftShiftStage2Idx1_uid127_fxpX_uid41_fpCosPiTest_q;
WHEN "10" => leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest_q <= leftShiftStage2Idx2_uid130_fxpX_uid41_fpCosPiTest_q;
WHEN "11" => leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest_q <= leftShiftStage2Idx3_uid133_fxpX_uid41_fpCosPiTest_q;
WHEN OTHERS => leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--fxpXFrac_uid43_fpCosPiTest(BITSELECT,42)@1
fxpXFrac_uid43_fpCosPiTest_in <= leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest_q(35 downto 0);
fxpXFrac_uid43_fpCosPiTest_b <= fxpXFrac_uid43_fpCosPiTest_in(35 downto 0);
--FxpXFrac35_uid44_fpCosPiTest(BITSELECT,43)@1
FxpXFrac35_uid44_fpCosPiTest_in <= fxpXFrac_uid43_fpCosPiTest_b;
FxpXFrac35_uid44_fpCosPiTest_b <= FxpXFrac35_uid44_fpCosPiTest_in(35 downto 35);
--FxpX36_uid42_fpCosPiTest(BITSELECT,41)@1
FxpX36_uid42_fpCosPiTest_in <= leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest_q;
FxpX36_uid42_fpCosPiTest_b <= FxpX36_uid42_fpCosPiTest_in(36 downto 36);
--xParityXorHalfParity_uid96_fpCosPiTest(LOGICAL,95)@1
xParityXorHalfParity_uid96_fpCosPiTest_a <= FxpX36_uid42_fpCosPiTest_b;
xParityXorHalfParity_uid96_fpCosPiTest_b <= FxpXFrac35_uid44_fpCosPiTest_b;
xParityXorHalfParity_uid96_fpCosPiTest_q <= xParityXorHalfParity_uid96_fpCosPiTest_a xor xParityXorHalfParity_uid96_fpCosPiTest_b;
--ld_xParityXorHalfParity_uid96_fpCosPiTest_q_to_signRComp_uid99_fpCosPiTest_c(DELAY,369)@1
ld_xParityXorHalfParity_uid96_fpCosPiTest_q_to_signRComp_uid99_fpCosPiTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => xParityXorHalfParity_uid96_fpCosPiTest_q, xout => ld_xParityXorHalfParity_uid96_fpCosPiTest_q_to_signRComp_uid99_fpCosPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--cstBiasPwF_uid12_fpCosPiTest(CONSTANT,11)
cstBiasPwF_uid12_fpCosPiTest_q <= "10010110";
--xEvenInt_uid35_fpCosPiTest(COMPARE,34)@0
xEvenInt_uid35_fpCosPiTest_cin <= GND_q;
xEvenInt_uid35_fpCosPiTest_a <= STD_LOGIC_VECTOR("00" & cstBiasPwF_uid12_fpCosPiTest_q) & '0';
xEvenInt_uid35_fpCosPiTest_b <= STD_LOGIC_VECTOR("00" & expX_uid6_fpCosPiTest_b) & xEvenInt_uid35_fpCosPiTest_cin(0);
xEvenInt_uid35_fpCosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(xEvenInt_uid35_fpCosPiTest_a) - UNSIGNED(xEvenInt_uid35_fpCosPiTest_b));
xEvenInt_uid35_fpCosPiTest_c(0) <= xEvenInt_uid35_fpCosPiTest_o(10);
--ld_xEvenInt_uid35_fpCosPiTest_c_to_evenIntCosNotOneFZ_uid79_fpCosPiTest_a(DELAY,335)@0
ld_xEvenInt_uid35_fpCosPiTest_c_to_evenIntCosNotOneFZ_uid79_fpCosPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => xEvenInt_uid35_fpCosPiTest_c, xout => ld_xEvenInt_uid35_fpCosPiTest_c_to_evenIntCosNotOneFZ_uid79_fpCosPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--InvXEvenInt_uid81_fpCosPiTest(LOGICAL,80)@2
InvXEvenInt_uid81_fpCosPiTest_a <= ld_xEvenInt_uid35_fpCosPiTest_c_to_evenIntCosNotOneFZ_uid79_fpCosPiTest_a_q;
InvXEvenInt_uid81_fpCosPiTest_q <= not InvXEvenInt_uid81_fpCosPiTest_a;
--cosXIsOne_uid36_fpCosPiTest(COMPARE,35)@0
cosXIsOne_uid36_fpCosPiTest_cin <= GND_q;
cosXIsOne_uid36_fpCosPiTest_a <= STD_LOGIC_VECTOR("00" & expX_uid6_fpCosPiTest_b) & '0';
cosXIsOne_uid36_fpCosPiTest_b <= STD_LOGIC_VECTOR("00" & biasMwShiftMO_uid13_fpCosPiTest_q) & cosXIsOne_uid36_fpCosPiTest_cin(0);
cosXIsOne_uid36_fpCosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(cosXIsOne_uid36_fpCosPiTest_a) - UNSIGNED(cosXIsOne_uid36_fpCosPiTest_b));
cosXIsOne_uid36_fpCosPiTest_c(0) <= cosXIsOne_uid36_fpCosPiTest_o(10);
--ld_cosXIsOne_uid36_fpCosPiTest_c_to_InvCosXIsOne_uid77_fpCosPiTest_a(DELAY,332)@0
ld_cosXIsOne_uid36_fpCosPiTest_c_to_InvCosXIsOne_uid77_fpCosPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => cosXIsOne_uid36_fpCosPiTest_c, xout => ld_cosXIsOne_uid36_fpCosPiTest_c_to_InvCosXIsOne_uid77_fpCosPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--InvCosXIsOne_uid77_fpCosPiTest(LOGICAL,76)@2
InvCosXIsOne_uid77_fpCosPiTest_a <= ld_cosXIsOne_uid36_fpCosPiTest_c_to_InvCosXIsOne_uid77_fpCosPiTest_a_q;
InvCosXIsOne_uid77_fpCosPiTest_q <= not InvCosXIsOne_uid77_fpCosPiTest_a;
--signRComp_uid99_fpCosPiTest(LOGICAL,98)@2
signRComp_uid99_fpCosPiTest_a <= InvCosXIsOne_uid77_fpCosPiTest_q;
signRComp_uid99_fpCosPiTest_b <= InvXEvenInt_uid81_fpCosPiTest_q;
signRComp_uid99_fpCosPiTest_c <= ld_xParityXorHalfParity_uid96_fpCosPiTest_q_to_signRComp_uid99_fpCosPiTest_c_q;
signRComp_uid99_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
signRComp_uid99_fpCosPiTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1' AND en = "1") THEN
signRComp_uid99_fpCosPiTest_q <= signRComp_uid99_fpCosPiTest_a and signRComp_uid99_fpCosPiTest_b and signRComp_uid99_fpCosPiTest_c;
END IF;
END PROCESS;
--cstZwSwF_uid15_fpCosPiTest(CONSTANT,14)
cstZwSwF_uid15_fpCosPiTest_q <= "00000000000000000000000000000000000";
--cstHalfwSwFP1_uid18_fpCosPiTest(BITJOIN,17)@2
cstHalfwSwFP1_uid18_fpCosPiTest_q <= VCC_q & cstZwSwF_uid15_fpCosPiTest_q;
--reg_fxpXFrac_uid43_fpCosPiTest_0_to_fxpXFracZero_uid45_fpCosPiTest_1(REG,237)@1
reg_fxpXFrac_uid43_fpCosPiTest_0_to_fxpXFracZero_uid45_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fxpXFrac_uid43_fpCosPiTest_0_to_fxpXFracZero_uid45_fpCosPiTest_1_q <= "000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fxpXFrac_uid43_fpCosPiTest_0_to_fxpXFracZero_uid45_fpCosPiTest_1_q <= fxpXFrac_uid43_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--fxpXFracHalf_uid46_fpCosPiTest(LOGICAL,45)@2
fxpXFracHalf_uid46_fpCosPiTest_a <= reg_fxpXFrac_uid43_fpCosPiTest_0_to_fxpXFracZero_uid45_fpCosPiTest_1_q;
fxpXFracHalf_uid46_fpCosPiTest_b <= cstHalfwSwFP1_uid18_fpCosPiTest_q;
fxpXFracHalf_uid46_fpCosPiTest_q <= "1" when fxpXFracHalf_uid46_fpCosPiTest_a = fxpXFracHalf_uid46_fpCosPiTest_b else "0";
--ld_fxpXFracHalf_uid46_fpCosPiTest_q_to_InvFxpXFracHalf_uid100_fpCosPiTest_a(DELAY,370)@2
ld_fxpXFracHalf_uid46_fpCosPiTest_q_to_InvFxpXFracHalf_uid100_fpCosPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => fxpXFracHalf_uid46_fpCosPiTest_q, xout => ld_fxpXFracHalf_uid46_fpCosPiTest_q_to_InvFxpXFracHalf_uid100_fpCosPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--InvFxpXFracHalf_uid100_fpCosPiTest(LOGICAL,99)@3
InvFxpXFracHalf_uid100_fpCosPiTest_a <= ld_fxpXFracHalf_uid46_fpCosPiTest_q_to_InvFxpXFracHalf_uid100_fpCosPiTest_a_q;
InvFxpXFracHalf_uid100_fpCosPiTest_q <= not InvFxpXFracHalf_uid100_fpCosPiTest_a;
--signR_uid101_fpCosPiTest(LOGICAL,100)@3
signR_uid101_fpCosPiTest_a <= InvFxpXFracHalf_uid100_fpCosPiTest_q;
signR_uid101_fpCosPiTest_b <= signRComp_uid99_fpCosPiTest_q;
signR_uid101_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
signR_uid101_fpCosPiTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1' AND en = "1") THEN
signR_uid101_fpCosPiTest_q <= signR_uid101_fpCosPiTest_a and signR_uid101_fpCosPiTest_b;
END IF;
END PROCESS;
--ld_signR_uid101_fpCosPiTest_q_to_R_uid102_fpCosPiTest_c(DELAY,375)@4
ld_signR_uid101_fpCosPiTest_q_to_R_uid102_fpCosPiTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 13 )
PORT MAP ( xin => signR_uid101_fpCosPiTest_q, xout => ld_signR_uid101_fpCosPiTest_q_to_R_uid102_fpCosPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--cstBias_uid10_fpCosPiTest(CONSTANT,9)
cstBias_uid10_fpCosPiTest_q <= "01111111";
--cstAllOWE_uid8_fpCosPiTest(CONSTANT,7)
cstAllOWE_uid8_fpCosPiTest_q <= "11111111";
--pad_o_uid16_uid47_fpCosPiTest(BITJOIN,46)@1
pad_o_uid16_uid47_fpCosPiTest_q <= VCC_q & STD_LOGIC_VECTOR((35 downto 1 => GND_q(0)) & GND_q);
--reg_pad_o_uid16_uid47_fpCosPiTest_0_to_oMFxpXFrac_uid47_fpCosPiTest_0(REG,244)@1
reg_pad_o_uid16_uid47_fpCosPiTest_0_to_oMFxpXFrac_uid47_fpCosPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_o_uid16_uid47_fpCosPiTest_0_to_oMFxpXFrac_uid47_fpCosPiTest_0_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_o_uid16_uid47_fpCosPiTest_0_to_oMFxpXFrac_uid47_fpCosPiTest_0_q <= pad_o_uid16_uid47_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--oMFxpXFrac_uid47_fpCosPiTest(SUB,47)@2
oMFxpXFrac_uid47_fpCosPiTest_a <= STD_LOGIC_VECTOR("0" & reg_pad_o_uid16_uid47_fpCosPiTest_0_to_oMFxpXFrac_uid47_fpCosPiTest_0_q);
oMFxpXFrac_uid47_fpCosPiTest_b <= STD_LOGIC_VECTOR("00" & reg_fxpXFrac_uid43_fpCosPiTest_0_to_fxpXFracZero_uid45_fpCosPiTest_1_q);
oMFxpXFrac_uid47_fpCosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(oMFxpXFrac_uid47_fpCosPiTest_a) - UNSIGNED(oMFxpXFrac_uid47_fpCosPiTest_b));
oMFxpXFrac_uid47_fpCosPiTest_q <= oMFxpXFrac_uid47_fpCosPiTest_o(37 downto 0);
--oMFxpXFrac_uid49_fpCosPiTest(BITSELECT,48)@2
oMFxpXFrac_uid49_fpCosPiTest_in <= oMFxpXFrac_uid47_fpCosPiTest_q(35 downto 0);
oMFxpXFrac_uid49_fpCosPiTest_b <= oMFxpXFrac_uid49_fpCosPiTest_in(35 downto 0);
--ld_fxpXFrac_uid43_fpCosPiTest_b_to_rangeReducedFxPX_uid51_fpCosPiTest_c(DELAY,308)@1
ld_fxpXFrac_uid43_fpCosPiTest_b_to_rangeReducedFxPX_uid51_fpCosPiTest_c : dspba_delay
GENERIC MAP ( width => 36, depth => 1 )
PORT MAP ( xin => fxpXFrac_uid43_fpCosPiTest_b, xout => ld_fxpXFrac_uid43_fpCosPiTest_b_to_rangeReducedFxPX_uid51_fpCosPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--ld_FxpXFrac35_uid44_fpCosPiTest_b_to_rangeReducedFxPX_uid51_fpCosPiTest_b(DELAY,307)@1
ld_FxpXFrac35_uid44_fpCosPiTest_b_to_rangeReducedFxPX_uid51_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => FxpXFrac35_uid44_fpCosPiTest_b, xout => ld_FxpXFrac35_uid44_fpCosPiTest_b_to_rangeReducedFxPX_uid51_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--rangeReducedFxPX_uid51_fpCosPiTest(MUX,50)@2
rangeReducedFxPX_uid51_fpCosPiTest_s <= ld_FxpXFrac35_uid44_fpCosPiTest_b_to_rangeReducedFxPX_uid51_fpCosPiTest_b_q;
rangeReducedFxPX_uid51_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
rangeReducedFxPX_uid51_fpCosPiTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE rangeReducedFxPX_uid51_fpCosPiTest_s IS
WHEN "0" => rangeReducedFxPX_uid51_fpCosPiTest_q <= ld_fxpXFrac_uid43_fpCosPiTest_b_to_rangeReducedFxPX_uid51_fpCosPiTest_c_q;
WHEN "1" => rangeReducedFxPX_uid51_fpCosPiTest_q <= oMFxpXFrac_uid49_fpCosPiTest_b;
WHEN OTHERS => rangeReducedFxPX_uid51_fpCosPiTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--pad_half_uid17_uid52_fpCosPiTest(BITJOIN,51)@2
pad_half_uid17_uid52_fpCosPiTest_q <= VCC_q & STD_LOGIC_VECTOR((34 downto 1 => GND_q(0)) & GND_q);
--reg_pad_half_uid17_uid52_fpCosPiTest_0_to_z_halfMRRFxPXE_uid52_fpCosPiTest_0(REG,246)@2
reg_pad_half_uid17_uid52_fpCosPiTest_0_to_z_halfMRRFxPXE_uid52_fpCosPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_half_uid17_uid52_fpCosPiTest_0_to_z_halfMRRFxPXE_uid52_fpCosPiTest_0_q <= "000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_half_uid17_uid52_fpCosPiTest_0_to_z_halfMRRFxPXE_uid52_fpCosPiTest_0_q <= pad_half_uid17_uid52_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--z_halfMRRFxPXE_uid52_fpCosPiTest(SUB,52)@3
z_halfMRRFxPXE_uid52_fpCosPiTest_a <= STD_LOGIC_VECTOR("0" & reg_pad_half_uid17_uid52_fpCosPiTest_0_to_z_halfMRRFxPXE_uid52_fpCosPiTest_0_q);
z_halfMRRFxPXE_uid52_fpCosPiTest_b <= STD_LOGIC_VECTOR("0" & rangeReducedFxPX_uid51_fpCosPiTest_q);
z_halfMRRFxPXE_uid52_fpCosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(z_halfMRRFxPXE_uid52_fpCosPiTest_a) - UNSIGNED(z_halfMRRFxPXE_uid52_fpCosPiTest_b));
z_halfMRRFxPXE_uid52_fpCosPiTest_q <= z_halfMRRFxPXE_uid52_fpCosPiTest_o(36 downto 0);
--z_uid54_fpCosPiTest(BITSELECT,53)@3
z_uid54_fpCosPiTest_in <= z_halfMRRFxPXE_uid52_fpCosPiTest_q(34 downto 0);
z_uid54_fpCosPiTest_b <= z_uid54_fpCosPiTest_in(34 downto 0);
--zAddr_uid62_fpCosPiTest(BITSELECT,61)@3
zAddr_uid62_fpCosPiTest_in <= z_uid54_fpCosPiTest_b;
zAddr_uid62_fpCosPiTest_b <= zAddr_uid62_fpCosPiTest_in(34 downto 28);
--reg_zAddr_uid62_fpCosPiTest_0_to_memoryC2_uid209_sinPiZTableGenerator_0(REG,263)@3
reg_zAddr_uid62_fpCosPiTest_0_to_memoryC2_uid209_sinPiZTableGenerator_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_zAddr_uid62_fpCosPiTest_0_to_memoryC2_uid209_sinPiZTableGenerator_0_q <= "0000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_zAddr_uid62_fpCosPiTest_0_to_memoryC2_uid209_sinPiZTableGenerator_0_q <= zAddr_uid62_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--memoryC2_uid209_sinPiZTableGenerator(LOOKUP,208)@4
memoryC2_uid209_sinPiZTableGenerator: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
memoryC2_uid209_sinPiZTableGenerator_q <= "10101101010011";
ELSIF (clk'EVENT AND clk = '1' AND en = "1") THEN
CASE (reg_zAddr_uid62_fpCosPiTest_0_to_memoryC2_uid209_sinPiZTableGenerator_0_q) IS
WHEN "0000000" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101101010011";
WHEN "0000001" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101101010100";
WHEN "0000010" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101101010111";
WHEN "0000011" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101101011001";
WHEN "0000100" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101101011011";
WHEN "0000101" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101101011100";
WHEN "0000110" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101101011111";
WHEN "0000111" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101101100010";
WHEN "0001000" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101101100110";
WHEN "0001001" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101101101011";
WHEN "0001010" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101101110000";
WHEN "0001011" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101101110101";
WHEN "0001100" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101101111011";
WHEN "0001101" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101110000000";
WHEN "0001110" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101110000111";
WHEN "0001111" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101110001110";
WHEN "0010000" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101110010011";
WHEN "0010001" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101110011110";
WHEN "0010010" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101110100110";
WHEN "0010011" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101110101111";
WHEN "0010100" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101110111000";
WHEN "0010101" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101111000011";
WHEN "0010110" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101111001100";
WHEN "0010111" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101111010111";
WHEN "0011000" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101111100011";
WHEN "0011001" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101111101110";
WHEN "0011010" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101111111011";
WHEN "0011011" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110000001001";
WHEN "0011100" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110000010101";
WHEN "0011101" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110000100000";
WHEN "0011110" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110000110001";
WHEN "0011111" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110001000000";
WHEN "0100000" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110001001101";
WHEN "0100001" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110001011110";
WHEN "0100010" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110001101100";
WHEN "0100011" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110001111111";
WHEN "0100100" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110010001111";
WHEN "0100101" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110010100001";
WHEN "0100110" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110010110011";
WHEN "0100111" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110011000101";
WHEN "0101000" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110011010110";
WHEN "0101001" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110011101011";
WHEN "0101010" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110011111111";
WHEN "0101011" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110100010010";
WHEN "0101100" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110100100101";
WHEN "0101101" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110100111011";
WHEN "0101110" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110101001110";
WHEN "0101111" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110101100111";
WHEN "0110000" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110101111100";
WHEN "0110001" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110110010010";
WHEN "0110010" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110110100110";
WHEN "0110011" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110111000000";
WHEN "0110100" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110111010101";
WHEN "0110101" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110111110000";
WHEN "0110110" => memoryC2_uid209_sinPiZTableGenerator_q <= "10111000000110";
WHEN "0110111" => memoryC2_uid209_sinPiZTableGenerator_q <= "10111000100010";
WHEN "0111000" => memoryC2_uid209_sinPiZTableGenerator_q <= "10111000111001";
WHEN "0111001" => memoryC2_uid209_sinPiZTableGenerator_q <= "10111001010100";
WHEN "0111010" => memoryC2_uid209_sinPiZTableGenerator_q <= "10111001101111";
WHEN "0111011" => memoryC2_uid209_sinPiZTableGenerator_q <= "10111010001001";
WHEN "0111100" => memoryC2_uid209_sinPiZTableGenerator_q <= "10111010100011";
WHEN "0111101" => memoryC2_uid209_sinPiZTableGenerator_q <= "10111010111100";
WHEN "0111110" => memoryC2_uid209_sinPiZTableGenerator_q <= "10111011011001";
WHEN "0111111" => memoryC2_uid209_sinPiZTableGenerator_q <= "10111011110111";
WHEN "1000000" => memoryC2_uid209_sinPiZTableGenerator_q <= "10111100010100";
WHEN "1000001" => memoryC2_uid209_sinPiZTableGenerator_q <= "10111100110001";
WHEN "1000010" => memoryC2_uid209_sinPiZTableGenerator_q <= "10111101001101";
WHEN "1000011" => memoryC2_uid209_sinPiZTableGenerator_q <= "10111101101010";
WHEN "1000100" => memoryC2_uid209_sinPiZTableGenerator_q <= "10111110001000";
WHEN "1000101" => memoryC2_uid209_sinPiZTableGenerator_q <= "10111110100101";
WHEN "1000110" => memoryC2_uid209_sinPiZTableGenerator_q <= "10111111000101";
WHEN "1000111" => memoryC2_uid209_sinPiZTableGenerator_q <= "10111111100011";
WHEN "1001000" => memoryC2_uid209_sinPiZTableGenerator_q <= "11000000000011";
WHEN "1001001" => memoryC2_uid209_sinPiZTableGenerator_q <= "11000000100011";
WHEN "1001010" => memoryC2_uid209_sinPiZTableGenerator_q <= "11000001000100";
WHEN "1001011" => memoryC2_uid209_sinPiZTableGenerator_q <= "11000001100010";
WHEN "1001100" => memoryC2_uid209_sinPiZTableGenerator_q <= "11000010000100";
WHEN "1001101" => memoryC2_uid209_sinPiZTableGenerator_q <= "11000010100010";
WHEN "1001110" => memoryC2_uid209_sinPiZTableGenerator_q <= "11000011000110";
WHEN "1001111" => memoryC2_uid209_sinPiZTableGenerator_q <= "11000011101000";
WHEN "1010000" => memoryC2_uid209_sinPiZTableGenerator_q <= "11000100001010";
WHEN "1010001" => memoryC2_uid209_sinPiZTableGenerator_q <= "11000100101101";
WHEN "1010010" => memoryC2_uid209_sinPiZTableGenerator_q <= "11000101010001";
WHEN "1010011" => memoryC2_uid209_sinPiZTableGenerator_q <= "11000101110010";
WHEN "1010100" => memoryC2_uid209_sinPiZTableGenerator_q <= "11000110010100";
WHEN "1010101" => memoryC2_uid209_sinPiZTableGenerator_q <= "11000110111011";
WHEN "1010110" => memoryC2_uid209_sinPiZTableGenerator_q <= "11000111011010";
WHEN "1010111" => memoryC2_uid209_sinPiZTableGenerator_q <= "11001000000001";
WHEN "1011000" => memoryC2_uid209_sinPiZTableGenerator_q <= "11001000100110";
WHEN "1011001" => memoryC2_uid209_sinPiZTableGenerator_q <= "11001001001011";
WHEN "1011010" => memoryC2_uid209_sinPiZTableGenerator_q <= "11001001101101";
WHEN "1011011" => memoryC2_uid209_sinPiZTableGenerator_q <= "11001010010101";
WHEN "1011100" => memoryC2_uid209_sinPiZTableGenerator_q <= "11001010111100";
WHEN "1011101" => memoryC2_uid209_sinPiZTableGenerator_q <= "11001011100000";
WHEN "1011110" => memoryC2_uid209_sinPiZTableGenerator_q <= "11001100000101";
WHEN "1011111" => memoryC2_uid209_sinPiZTableGenerator_q <= "11001100101110";
WHEN "1100000" => memoryC2_uid209_sinPiZTableGenerator_q <= "11001101010100";
WHEN "1100001" => memoryC2_uid209_sinPiZTableGenerator_q <= "11001101111010";
WHEN "1100010" => memoryC2_uid209_sinPiZTableGenerator_q <= "11001110100010";
WHEN "1100011" => memoryC2_uid209_sinPiZTableGenerator_q <= "11001111001001";
WHEN "1100100" => memoryC2_uid209_sinPiZTableGenerator_q <= "11001111110001";
WHEN "1100101" => memoryC2_uid209_sinPiZTableGenerator_q <= "11010000010110";
WHEN "1100110" => memoryC2_uid209_sinPiZTableGenerator_q <= "11010000111111";
WHEN "1100111" => memoryC2_uid209_sinPiZTableGenerator_q <= "11010001101001";
WHEN "1101000" => memoryC2_uid209_sinPiZTableGenerator_q <= "11010010010010";
WHEN "1101001" => memoryC2_uid209_sinPiZTableGenerator_q <= "11010010111101";
WHEN "1101010" => memoryC2_uid209_sinPiZTableGenerator_q <= "11010011100001";
WHEN "1101011" => memoryC2_uid209_sinPiZTableGenerator_q <= "11010100001100";
WHEN "1101100" => memoryC2_uid209_sinPiZTableGenerator_q <= "11010100110111";
WHEN "1101101" => memoryC2_uid209_sinPiZTableGenerator_q <= "11010101100001";
WHEN "1101110" => memoryC2_uid209_sinPiZTableGenerator_q <= "11010110001011";
WHEN "1101111" => memoryC2_uid209_sinPiZTableGenerator_q <= "11010110110011";
WHEN "1110000" => memoryC2_uid209_sinPiZTableGenerator_q <= "11010111011111";
WHEN "1110001" => memoryC2_uid209_sinPiZTableGenerator_q <= "11011000001010";
WHEN "1110010" => memoryC2_uid209_sinPiZTableGenerator_q <= "11011000110100";
WHEN "1110011" => memoryC2_uid209_sinPiZTableGenerator_q <= "11011001011111";
WHEN "1110100" => memoryC2_uid209_sinPiZTableGenerator_q <= "11011010001010";
WHEN "1110101" => memoryC2_uid209_sinPiZTableGenerator_q <= "11011010110110";
WHEN "1110110" => memoryC2_uid209_sinPiZTableGenerator_q <= "11011011100011";
WHEN "1110111" => memoryC2_uid209_sinPiZTableGenerator_q <= "11011100001111";
WHEN "1111000" => memoryC2_uid209_sinPiZTableGenerator_q <= "11011100111001";
WHEN "1111001" => memoryC2_uid209_sinPiZTableGenerator_q <= "11011101100011";
WHEN "1111010" => memoryC2_uid209_sinPiZTableGenerator_q <= "11011110010001";
WHEN "1111011" => memoryC2_uid209_sinPiZTableGenerator_q <= "11011110111011";
WHEN "1111100" => memoryC2_uid209_sinPiZTableGenerator_q <= "11011111101000";
WHEN "1111101" => memoryC2_uid209_sinPiZTableGenerator_q <= "11100000010101";
WHEN "1111110" => memoryC2_uid209_sinPiZTableGenerator_q <= "11100001000010";
WHEN "1111111" => memoryC2_uid209_sinPiZTableGenerator_q <= "11100001110000";
WHEN OTHERS =>
memoryC2_uid209_sinPiZTableGenerator_q <= (others => '-');
END CASE;
END IF;
END PROCESS;
--zPPolyEval_uid63_fpCosPiTest(BITSELECT,62)@3
zPPolyEval_uid63_fpCosPiTest_in <= z_uid54_fpCosPiTest_b(27 downto 0);
zPPolyEval_uid63_fpCosPiTest_b <= zPPolyEval_uid63_fpCosPiTest_in(27 downto 12);
--yT1_uid210_sinPiZPolyEval(BITSELECT,209)@3
yT1_uid210_sinPiZPolyEval_in <= zPPolyEval_uid63_fpCosPiTest_b;
yT1_uid210_sinPiZPolyEval_b <= yT1_uid210_sinPiZPolyEval_in(15 downto 2);
--reg_yT1_uid210_sinPiZPolyEval_0_to_prodXY_uid226_pT1_uid211_sinPiZPolyEval_0(REG,264)@3
reg_yT1_uid210_sinPiZPolyEval_0_to_prodXY_uid226_pT1_uid211_sinPiZPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT1_uid210_sinPiZPolyEval_0_to_prodXY_uid226_pT1_uid211_sinPiZPolyEval_0_q <= "00000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT1_uid210_sinPiZPolyEval_0_to_prodXY_uid226_pT1_uid211_sinPiZPolyEval_0_q <= yT1_uid210_sinPiZPolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_reg_yT1_uid210_sinPiZPolyEval_0_to_prodXY_uid226_pT1_uid211_sinPiZPolyEval_0_q_to_prodXY_uid226_pT1_uid211_sinPiZPolyEval_a(DELAY,499)@4
ld_reg_yT1_uid210_sinPiZPolyEval_0_to_prodXY_uid226_pT1_uid211_sinPiZPolyEval_0_q_to_prodXY_uid226_pT1_uid211_sinPiZPolyEval_a : dspba_delay
GENERIC MAP ( width => 14, depth => 1 )
PORT MAP ( xin => reg_yT1_uid210_sinPiZPolyEval_0_to_prodXY_uid226_pT1_uid211_sinPiZPolyEval_0_q, xout => ld_reg_yT1_uid210_sinPiZPolyEval_0_to_prodXY_uid226_pT1_uid211_sinPiZPolyEval_0_q_to_prodXY_uid226_pT1_uid211_sinPiZPolyEval_a_q, ena => en(0), clk => clk, aclr => areset );
--prodXY_uid226_pT1_uid211_sinPiZPolyEval(MULT,225)@5
prodXY_uid226_pT1_uid211_sinPiZPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid226_pT1_uid211_sinPiZPolyEval_a),15)) * SIGNED(prodXY_uid226_pT1_uid211_sinPiZPolyEval_b);
prodXY_uid226_pT1_uid211_sinPiZPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid226_pT1_uid211_sinPiZPolyEval_a <= (others => '0');
prodXY_uid226_pT1_uid211_sinPiZPolyEval_b <= (others => '0');
prodXY_uid226_pT1_uid211_sinPiZPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid226_pT1_uid211_sinPiZPolyEval_a <= ld_reg_yT1_uid210_sinPiZPolyEval_0_to_prodXY_uid226_pT1_uid211_sinPiZPolyEval_0_q_to_prodXY_uid226_pT1_uid211_sinPiZPolyEval_a_q;
prodXY_uid226_pT1_uid211_sinPiZPolyEval_b <= memoryC2_uid209_sinPiZTableGenerator_q;
prodXY_uid226_pT1_uid211_sinPiZPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid226_pT1_uid211_sinPiZPolyEval_pr,28));
END IF;
END IF;
END PROCESS;
prodXY_uid226_pT1_uid211_sinPiZPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid226_pT1_uid211_sinPiZPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid226_pT1_uid211_sinPiZPolyEval_q <= prodXY_uid226_pT1_uid211_sinPiZPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid227_pT1_uid211_sinPiZPolyEval(BITSELECT,226)@8
prodXYTruncFR_uid227_pT1_uid211_sinPiZPolyEval_in <= prodXY_uid226_pT1_uid211_sinPiZPolyEval_q;
prodXYTruncFR_uid227_pT1_uid211_sinPiZPolyEval_b <= prodXYTruncFR_uid227_pT1_uid211_sinPiZPolyEval_in(27 downto 13);
--highBBits_uid213_sinPiZPolyEval(BITSELECT,212)@8
highBBits_uid213_sinPiZPolyEval_in <= prodXYTruncFR_uid227_pT1_uid211_sinPiZPolyEval_b;
highBBits_uid213_sinPiZPolyEval_b <= highBBits_uid213_sinPiZPolyEval_in(14 downto 1);
--ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_notEnable(LOGICAL,557)
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_notEnable_a <= en;
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_notEnable_q <= not ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_notEnable_a;
--ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_nor(LOGICAL,596)
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_nor_a <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_notEnable_q;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_nor_b <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_sticky_ena_q;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_nor_q <= not (ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_nor_a or ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_nor_b);
--ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_mem_top(CONSTANT,592)
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_mem_top_q <= "010";
--ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_cmp(LOGICAL,593)
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_cmp_a <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_mem_top_q;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdmux_q);
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_cmp_q <= "1" when ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_cmp_a = ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_cmp_b else "0";
--ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_cmpReg(REG,594)
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_cmpReg_q <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_sticky_ena(REG,597)
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_nor_q = "1") THEN
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_sticky_ena_q <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_enaAnd(LOGICAL,598)
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_enaAnd_a <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_sticky_ena_q;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_enaAnd_b <= en;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_enaAnd_q <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_enaAnd_a and ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_enaAnd_b;
--ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt(COUNTER,588)
-- every=1, low=0, high=2, step=1, init=1
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt_i <= TO_UNSIGNED(1,2);
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt_i = 1 THEN
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt_eq = '1') THEN
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt_i <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt_i - 2;
ELSE
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt_i <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt_i,2));
--ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdreg(REG,589)
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdreg_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdreg_q <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdmux(MUX,590)
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdmux_s <= en;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdmux: PROCESS (ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdmux_s, ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdreg_q, ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdmux_s IS
WHEN "0" => ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdmux_q <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdreg_q;
WHEN "1" => ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdmux_q <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem(DUALMEM,587)
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_reset0 <= areset;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_ia <= reg_zAddr_uid62_fpCosPiTest_0_to_memoryC2_uid209_sinPiZTableGenerator_0_q;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_aa <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdreg_q;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_ab <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdmux_q;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 7,
widthad_a => 2,
numwords_a => 3,
width_b => 7,
widthad_b => 2,
numwords_b => 3,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_iq,
address_a => ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_aa,
data_a => ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_ia
);
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_q <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_iq(6 downto 0);
--memoryC1_uid208_sinPiZTableGenerator(LOOKUP,207)@8
memoryC1_uid208_sinPiZTableGenerator: PROCESS (ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_q)
BEGIN
-- Begin reserved scope level
CASE (ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_q) IS
WHEN "0000000" => memoryC1_uid208_sinPiZTableGenerator_q <= "000000000000000000001";
WHEN "0000001" => memoryC1_uid208_sinPiZTableGenerator_q <= "111111101011010101010";
WHEN "0000010" => memoryC1_uid208_sinPiZTableGenerator_q <= "111111010110101010001";
WHEN "0000011" => memoryC1_uid208_sinPiZTableGenerator_q <= "111111000001111111100";
WHEN "0000100" => memoryC1_uid208_sinPiZTableGenerator_q <= "111110101101010101010";
WHEN "0000101" => memoryC1_uid208_sinPiZTableGenerator_q <= "111110011000101011101";
WHEN "0000110" => memoryC1_uid208_sinPiZTableGenerator_q <= "111110000100000010101";
WHEN "0000111" => memoryC1_uid208_sinPiZTableGenerator_q <= "111101101111011010001";
WHEN "0001000" => memoryC1_uid208_sinPiZTableGenerator_q <= "111101011010110010101";
WHEN "0001001" => memoryC1_uid208_sinPiZTableGenerator_q <= "111101000110001011111";
WHEN "0001010" => memoryC1_uid208_sinPiZTableGenerator_q <= "111100110001100110010";
WHEN "0001011" => memoryC1_uid208_sinPiZTableGenerator_q <= "111100011101000010000";
WHEN "0001100" => memoryC1_uid208_sinPiZTableGenerator_q <= "111100001000011110111";
WHEN "0001101" => memoryC1_uid208_sinPiZTableGenerator_q <= "111011110011111101011";
WHEN "0001110" => memoryC1_uid208_sinPiZTableGenerator_q <= "111011011111011101011";
WHEN "0001111" => memoryC1_uid208_sinPiZTableGenerator_q <= "111011001010111110111";
WHEN "0010000" => memoryC1_uid208_sinPiZTableGenerator_q <= "111010110110100010101";
WHEN "0010001" => memoryC1_uid208_sinPiZTableGenerator_q <= "111010100010000111100";
WHEN "0010010" => memoryC1_uid208_sinPiZTableGenerator_q <= "111010001101101111000";
WHEN "0010011" => memoryC1_uid208_sinPiZTableGenerator_q <= "111001111001011000011";
WHEN "0010100" => memoryC1_uid208_sinPiZTableGenerator_q <= "111001100101000100010";
WHEN "0010101" => memoryC1_uid208_sinPiZTableGenerator_q <= "111001010000110010001";
WHEN "0010110" => memoryC1_uid208_sinPiZTableGenerator_q <= "111000111100100010111";
WHEN "0010111" => memoryC1_uid208_sinPiZTableGenerator_q <= "111000101000010110001";
WHEN "0011000" => memoryC1_uid208_sinPiZTableGenerator_q <= "111000010100001011111";
WHEN "0011001" => memoryC1_uid208_sinPiZTableGenerator_q <= "111000000000000100110";
WHEN "0011010" => memoryC1_uid208_sinPiZTableGenerator_q <= "110111101100000000011";
WHEN "0011011" => memoryC1_uid208_sinPiZTableGenerator_q <= "110111010111111111000";
WHEN "0011100" => memoryC1_uid208_sinPiZTableGenerator_q <= "110111000100000001000";
WHEN "0011101" => memoryC1_uid208_sinPiZTableGenerator_q <= "110110110000000110101";
WHEN "0011110" => memoryC1_uid208_sinPiZTableGenerator_q <= "110110011100001110111";
WHEN "0011111" => memoryC1_uid208_sinPiZTableGenerator_q <= "110110001000011011000";
WHEN "0100000" => memoryC1_uid208_sinPiZTableGenerator_q <= "110101110100101011010";
WHEN "0100001" => memoryC1_uid208_sinPiZTableGenerator_q <= "110101100000111110101";
WHEN "0100010" => memoryC1_uid208_sinPiZTableGenerator_q <= "110101001101010110010";
WHEN "0100011" => memoryC1_uid208_sinPiZTableGenerator_q <= "110100111001110001011";
WHEN "0100100" => memoryC1_uid208_sinPiZTableGenerator_q <= "110100100110010001001";
WHEN "0100101" => memoryC1_uid208_sinPiZTableGenerator_q <= "110100010010110100110";
WHEN "0100110" => memoryC1_uid208_sinPiZTableGenerator_q <= "110011111111011100110";
WHEN "0100111" => memoryC1_uid208_sinPiZTableGenerator_q <= "110011101100001001010";
WHEN "0101000" => memoryC1_uid208_sinPiZTableGenerator_q <= "110011011000111010011";
WHEN "0101001" => memoryC1_uid208_sinPiZTableGenerator_q <= "110011000101101111111";
WHEN "0101010" => memoryC1_uid208_sinPiZTableGenerator_q <= "110010110010101010010";
WHEN "0101011" => memoryC1_uid208_sinPiZTableGenerator_q <= "110010011111101001101";
WHEN "0101100" => memoryC1_uid208_sinPiZTableGenerator_q <= "110010001100101110000";
WHEN "0101101" => memoryC1_uid208_sinPiZTableGenerator_q <= "110001111001110111001";
WHEN "0101110" => memoryC1_uid208_sinPiZTableGenerator_q <= "110001100111000110000";
WHEN "0101111" => memoryC1_uid208_sinPiZTableGenerator_q <= "110001010100011001011";
WHEN "0110000" => memoryC1_uid208_sinPiZTableGenerator_q <= "110001000001110010110";
WHEN "0110001" => memoryC1_uid208_sinPiZTableGenerator_q <= "110000101111010001100";
WHEN "0110010" => memoryC1_uid208_sinPiZTableGenerator_q <= "110000011100110110001";
WHEN "0110011" => memoryC1_uid208_sinPiZTableGenerator_q <= "110000001010011111111";
WHEN "0110100" => memoryC1_uid208_sinPiZTableGenerator_q <= "101111111000010000000";
WHEN "0110101" => memoryC1_uid208_sinPiZTableGenerator_q <= "101111100110000101100";
WHEN "0110110" => memoryC1_uid208_sinPiZTableGenerator_q <= "101111010100000001100";
WHEN "0110111" => memoryC1_uid208_sinPiZTableGenerator_q <= "101111000010000011001";
WHEN "0111000" => memoryC1_uid208_sinPiZTableGenerator_q <= "101110110000001011100";
WHEN "0111001" => memoryC1_uid208_sinPiZTableGenerator_q <= "101110011110011001110";
WHEN "0111010" => memoryC1_uid208_sinPiZTableGenerator_q <= "101110001100101110101";
WHEN "0111011" => memoryC1_uid208_sinPiZTableGenerator_q <= "101101111011001010001";
WHEN "0111100" => memoryC1_uid208_sinPiZTableGenerator_q <= "101101101001101100010";
WHEN "0111101" => memoryC1_uid208_sinPiZTableGenerator_q <= "101101011000010101010";
WHEN "0111110" => memoryC1_uid208_sinPiZTableGenerator_q <= "101101000111000100101";
WHEN "0111111" => memoryC1_uid208_sinPiZTableGenerator_q <= "101100110101111010111";
WHEN "1000000" => memoryC1_uid208_sinPiZTableGenerator_q <= "101100100100111000010";
WHEN "1000001" => memoryC1_uid208_sinPiZTableGenerator_q <= "101100010011111100111";
WHEN "1000010" => memoryC1_uid208_sinPiZTableGenerator_q <= "101100000011001000111";
WHEN "1000011" => memoryC1_uid208_sinPiZTableGenerator_q <= "101011110010011100000";
WHEN "1000100" => memoryC1_uid208_sinPiZTableGenerator_q <= "101011100001110110100";
WHEN "1000101" => memoryC1_uid208_sinPiZTableGenerator_q <= "101011010001011000100";
WHEN "1000110" => memoryC1_uid208_sinPiZTableGenerator_q <= "101011000001000001110";
WHEN "1000111" => memoryC1_uid208_sinPiZTableGenerator_q <= "101010110000110011000";
WHEN "1001000" => memoryC1_uid208_sinPiZTableGenerator_q <= "101010100000101011111";
WHEN "1001001" => memoryC1_uid208_sinPiZTableGenerator_q <= "101010010000101100100";
WHEN "1001010" => memoryC1_uid208_sinPiZTableGenerator_q <= "101010000000110101001";
WHEN "1001011" => memoryC1_uid208_sinPiZTableGenerator_q <= "101001110001000110000";
WHEN "1001100" => memoryC1_uid208_sinPiZTableGenerator_q <= "101001100001011110101";
WHEN "1001101" => memoryC1_uid208_sinPiZTableGenerator_q <= "101001010001111111111";
WHEN "1001110" => memoryC1_uid208_sinPiZTableGenerator_q <= "101001000010101000110";
WHEN "1001111" => memoryC1_uid208_sinPiZTableGenerator_q <= "101000110011011010001";
WHEN "1010000" => memoryC1_uid208_sinPiZTableGenerator_q <= "101000100100010100001";
WHEN "1010001" => memoryC1_uid208_sinPiZTableGenerator_q <= "101000010101010110100";
WHEN "1010010" => memoryC1_uid208_sinPiZTableGenerator_q <= "101000000110100001011";
WHEN "1010011" => memoryC1_uid208_sinPiZTableGenerator_q <= "100111110111110101011";
WHEN "1010100" => memoryC1_uid208_sinPiZTableGenerator_q <= "100111101001010010000";
WHEN "1010101" => memoryC1_uid208_sinPiZTableGenerator_q <= "100111011010110110110";
WHEN "1010110" => memoryC1_uid208_sinPiZTableGenerator_q <= "100111001100100101100";
WHEN "1010111" => memoryC1_uid208_sinPiZTableGenerator_q <= "100110111110011100011";
WHEN "1011000" => memoryC1_uid208_sinPiZTableGenerator_q <= "100110110000011100011";
WHEN "1011001" => memoryC1_uid208_sinPiZTableGenerator_q <= "100110100010100101110";
WHEN "1011010" => memoryC1_uid208_sinPiZTableGenerator_q <= "100110010100111000101";
WHEN "1011011" => memoryC1_uid208_sinPiZTableGenerator_q <= "100110000111010100001";
WHEN "1011100" => memoryC1_uid208_sinPiZTableGenerator_q <= "100101111001111001000";
WHEN "1011101" => memoryC1_uid208_sinPiZTableGenerator_q <= "100101101100100111111";
WHEN "1011110" => memoryC1_uid208_sinPiZTableGenerator_q <= "100101011111100000000";
WHEN "1011111" => memoryC1_uid208_sinPiZTableGenerator_q <= "100101010010100001001";
WHEN "1100000" => memoryC1_uid208_sinPiZTableGenerator_q <= "100101000101101100011";
WHEN "1100001" => memoryC1_uid208_sinPiZTableGenerator_q <= "100100111001000001011";
WHEN "1100010" => memoryC1_uid208_sinPiZTableGenerator_q <= "100100101100011111111";
WHEN "1100011" => memoryC1_uid208_sinPiZTableGenerator_q <= "100100100000001000010";
WHEN "1100100" => memoryC1_uid208_sinPiZTableGenerator_q <= "100100010011111010101";
WHEN "1100101" => memoryC1_uid208_sinPiZTableGenerator_q <= "100100000111110111001";
WHEN "1100110" => memoryC1_uid208_sinPiZTableGenerator_q <= "100011111011111101010";
WHEN "1100111" => memoryC1_uid208_sinPiZTableGenerator_q <= "100011110000001101010";
WHEN "1101000" => memoryC1_uid208_sinPiZTableGenerator_q <= "100011100100100111101";
WHEN "1101001" => memoryC1_uid208_sinPiZTableGenerator_q <= "100011011001001011111";
WHEN "1101010" => memoryC1_uid208_sinPiZTableGenerator_q <= "100011001101111011010";
WHEN "1101011" => memoryC1_uid208_sinPiZTableGenerator_q <= "100011000010110100001";
WHEN "1101100" => memoryC1_uid208_sinPiZTableGenerator_q <= "100010110111110111010";
WHEN "1101101" => memoryC1_uid208_sinPiZTableGenerator_q <= "100010101101000101000";
WHEN "1101110" => memoryC1_uid208_sinPiZTableGenerator_q <= "100010100010011101001";
WHEN "1101111" => memoryC1_uid208_sinPiZTableGenerator_q <= "100010011000000000001";
WHEN "1110000" => memoryC1_uid208_sinPiZTableGenerator_q <= "100010001101101101010";
WHEN "1110001" => memoryC1_uid208_sinPiZTableGenerator_q <= "100010000011100100111";
WHEN "1110010" => memoryC1_uid208_sinPiZTableGenerator_q <= "100001111001100111100";
WHEN "1110011" => memoryC1_uid208_sinPiZTableGenerator_q <= "100001101111110100101";
WHEN "1110100" => memoryC1_uid208_sinPiZTableGenerator_q <= "100001100110001100100";
WHEN "1110101" => memoryC1_uid208_sinPiZTableGenerator_q <= "100001011100101111001";
WHEN "1110110" => memoryC1_uid208_sinPiZTableGenerator_q <= "100001010011011100011";
WHEN "1110111" => memoryC1_uid208_sinPiZTableGenerator_q <= "100001001010010100101";
WHEN "1111000" => memoryC1_uid208_sinPiZTableGenerator_q <= "100001000001011000000";
WHEN "1111001" => memoryC1_uid208_sinPiZTableGenerator_q <= "100000111000100110100";
WHEN "1111010" => memoryC1_uid208_sinPiZTableGenerator_q <= "100000101111111111100";
WHEN "1111011" => memoryC1_uid208_sinPiZTableGenerator_q <= "100000100111100011111";
WHEN "1111100" => memoryC1_uid208_sinPiZTableGenerator_q <= "100000011111010011000";
WHEN "1111101" => memoryC1_uid208_sinPiZTableGenerator_q <= "100000010111001101010";
WHEN "1111110" => memoryC1_uid208_sinPiZTableGenerator_q <= "100000001111010010101";
WHEN "1111111" => memoryC1_uid208_sinPiZTableGenerator_q <= "100000000111100011001";
WHEN OTHERS =>
memoryC1_uid208_sinPiZTableGenerator_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--sumAHighB_uid214_sinPiZPolyEval(ADD,213)@8
sumAHighB_uid214_sinPiZPolyEval_a <= STD_LOGIC_VECTOR((21 downto 21 => memoryC1_uid208_sinPiZTableGenerator_q(20)) & memoryC1_uid208_sinPiZTableGenerator_q);
sumAHighB_uid214_sinPiZPolyEval_b <= STD_LOGIC_VECTOR((21 downto 14 => highBBits_uid213_sinPiZPolyEval_b(13)) & highBBits_uid213_sinPiZPolyEval_b);
sumAHighB_uid214_sinPiZPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid214_sinPiZPolyEval_a) + SIGNED(sumAHighB_uid214_sinPiZPolyEval_b));
sumAHighB_uid214_sinPiZPolyEval_q <= sumAHighB_uid214_sinPiZPolyEval_o(21 downto 0);
--lowRangeB_uid212_sinPiZPolyEval(BITSELECT,211)@8
lowRangeB_uid212_sinPiZPolyEval_in <= prodXYTruncFR_uid227_pT1_uid211_sinPiZPolyEval_b(0 downto 0);
lowRangeB_uid212_sinPiZPolyEval_b <= lowRangeB_uid212_sinPiZPolyEval_in(0 downto 0);
--s1_uid212_uid215_sinPiZPolyEval(BITJOIN,214)@8
s1_uid212_uid215_sinPiZPolyEval_q <= sumAHighB_uid214_sinPiZPolyEval_q & lowRangeB_uid212_sinPiZPolyEval_b;
--reg_s1_uid212_uid215_sinPiZPolyEval_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_1(REG,267)@8
reg_s1_uid212_uid215_sinPiZPolyEval_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_s1_uid212_uid215_sinPiZPolyEval_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_1_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_s1_uid212_uid215_sinPiZPolyEval_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_1_q <= s1_uid212_uid215_sinPiZPolyEval_q;
END IF;
END IF;
END PROCESS;
--ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_nor(LOGICAL,609)
ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_nor_a <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_notEnable_q;
ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_nor_b <= ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_sticky_ena_q;
ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_nor_q <= not (ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_nor_a or ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_nor_b);
--ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_sticky_ena(REG,610)
ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_nor_q = "1") THEN
ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_sticky_ena_q <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_enaAnd(LOGICAL,611)
ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_enaAnd_a <= ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_sticky_ena_q;
ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_enaAnd_b <= en;
ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_enaAnd_q <= ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_enaAnd_a and ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_enaAnd_b;
--ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_inputreg(DELAY,599)
ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 16, depth => 1 )
PORT MAP ( xin => zPPolyEval_uid63_fpCosPiTest_b, xout => ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem(DUALMEM,600)
ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_reset0 <= areset;
ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_ia <= ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_inputreg_q;
ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_aa <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdreg_q;
ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_ab <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdmux_q;
ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 16,
widthad_a => 2,
numwords_a => 3,
width_b => 16,
widthad_b => 2,
numwords_b => 3,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_iq,
address_a => ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_aa,
data_a => ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_ia
);
ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_q <= ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_iq(15 downto 0);
--reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0(REG,266)@8
reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_q <= ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--prodXY_uid229_pT2_uid217_sinPiZPolyEval(MULT,228)@9
prodXY_uid229_pT2_uid217_sinPiZPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid229_pT2_uid217_sinPiZPolyEval_a),17)) * SIGNED(prodXY_uid229_pT2_uid217_sinPiZPolyEval_b);
prodXY_uid229_pT2_uid217_sinPiZPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid229_pT2_uid217_sinPiZPolyEval_a <= (others => '0');
prodXY_uid229_pT2_uid217_sinPiZPolyEval_b <= (others => '0');
prodXY_uid229_pT2_uid217_sinPiZPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid229_pT2_uid217_sinPiZPolyEval_a <= reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_q;
prodXY_uid229_pT2_uid217_sinPiZPolyEval_b <= reg_s1_uid212_uid215_sinPiZPolyEval_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_1_q;
prodXY_uid229_pT2_uid217_sinPiZPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid229_pT2_uid217_sinPiZPolyEval_pr,39));
END IF;
END IF;
END PROCESS;
prodXY_uid229_pT2_uid217_sinPiZPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid229_pT2_uid217_sinPiZPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid229_pT2_uid217_sinPiZPolyEval_q <= prodXY_uid229_pT2_uid217_sinPiZPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid230_pT2_uid217_sinPiZPolyEval(BITSELECT,229)@12
prodXYTruncFR_uid230_pT2_uid217_sinPiZPolyEval_in <= prodXY_uid229_pT2_uid217_sinPiZPolyEval_q;
prodXYTruncFR_uid230_pT2_uid217_sinPiZPolyEval_b <= prodXYTruncFR_uid230_pT2_uid217_sinPiZPolyEval_in(38 downto 15);
--highBBits_uid219_sinPiZPolyEval(BITSELECT,218)@12
highBBits_uid219_sinPiZPolyEval_in <= prodXYTruncFR_uid230_pT2_uid217_sinPiZPolyEval_b;
highBBits_uid219_sinPiZPolyEval_b <= highBBits_uid219_sinPiZPolyEval_in(23 downto 2);
--ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_nor(LOGICAL,584)
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_nor_a <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_notEnable_q;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_nor_b <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_sticky_ena_q;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_nor_q <= not (ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_nor_a or ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_nor_b);
--ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_mem_top(CONSTANT,554)
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_mem_top_q <= "0110";
--ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_cmp(LOGICAL,555)
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_cmp_a <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_mem_top_q;
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdmux_q);
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_cmp_q <= "1" when ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_cmp_a = ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_cmp_b else "0";
--ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_cmpReg(REG,556)
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_cmpReg_q <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_sticky_ena(REG,585)
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_nor_q = "1") THEN
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_sticky_ena_q <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_enaAnd(LOGICAL,586)
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_enaAnd_a <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_sticky_ena_q;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_enaAnd_b <= en;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_enaAnd_q <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_enaAnd_a and ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_enaAnd_b;
--ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt(COUNTER,550)
-- every=1, low=0, high=6, step=1, init=1
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt_i = 5 THEN
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt_eq <= '1';
ELSE
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt_eq = '1') THEN
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt_i <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt_i - 6;
ELSE
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt_i <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt_i,3));
--ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdreg(REG,551)
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdreg_q <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdmux(MUX,552)
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdmux_s <= en;
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdmux: PROCESS (ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdmux_s, ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdreg_q, ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt_q)
BEGIN
CASE ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdmux_s IS
WHEN "0" => ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdmux_q <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdreg_q;
WHEN "1" => ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdmux_q <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem(DUALMEM,575)
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_reset0 <= areset;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_ia <= reg_zAddr_uid62_fpCosPiTest_0_to_memoryC2_uid209_sinPiZTableGenerator_0_q;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_aa <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdreg_q;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_ab <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdmux_q;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 7,
widthad_a => 3,
numwords_a => 7,
width_b => 7,
widthad_b => 3,
numwords_b => 7,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_iq,
address_a => ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_aa,
data_a => ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_ia
);
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_q <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_iq(6 downto 0);
--memoryC0_uid207_sinPiZTableGenerator(LOOKUP,206)@12
memoryC0_uid207_sinPiZTableGenerator: PROCESS (ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_q)
BEGIN
-- Begin reserved scope level
CASE (ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_q) IS
WHEN "0000000" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100100100001111110110101110";
WHEN "0000001" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100100100001110100100000010";
WHEN "0000010" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100100100001010101100000000";
WHEN "0000011" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100100100000100001110101000";
WHEN "0000100" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100100011111011001011111101";
WHEN "0000101" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100100011101111100100000010";
WHEN "0000110" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100100011100001010110111011";
WHEN "0000111" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100100011010000100100101111";
WHEN "0001000" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100100010111101001101100010";
WHEN "0001001" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100100010100111010001011101";
WHEN "0001010" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100100010001110110000100111";
WHEN "0001011" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100100001110011101011001001";
WHEN "0001100" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100100001010110000001001110";
WHEN "0001101" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100100000110101110011000000";
WHEN "0001110" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100100000010011000000101011";
WHEN "0001111" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100011111101101101010011101";
WHEN "0010000" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100011111000101110000100010";
WHEN "0010001" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100011110011011010011001011";
WHEN "0010010" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100011101101110010010100101";
WHEN "0010011" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100011100111110101111000011";
WHEN "0010100" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100011100001100101000110101";
WHEN "0010101" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100011011011000000000001111";
WHEN "0010110" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100011010100000110101100011";
WHEN "0010111" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100011001100111001001000110";
WHEN "0011000" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100011000101010111011001110";
WHEN "0011001" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100010111101100001100010000";
WHEN "0011010" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100010110101010111100100100";
WHEN "0011011" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100010101100111001100100010";
WHEN "0011100" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100010100100000111100100011";
WHEN "0011101" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100010011011000001101000000";
WHEN "0011110" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100010010001100111110010110";
WHEN "0011111" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100010000111111010000111111";
WHEN "0100000" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100001111101111000101010111";
WHEN "0100001" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100001110011100011011111110";
WHEN "0100010" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100001101000111010101010001";
WHEN "0100011" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100001011101111110001110000";
WHEN "0100100" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100001010010101110001111010";
WHEN "0100101" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100001000111001010110010010";
WHEN "0100110" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100000111011010011111011001";
WHEN "0100111" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100000101111001001101110010";
WHEN "0101000" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100000100010101100010000001";
WHEN "0101001" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100000010101111011100101011";
WHEN "0101010" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100000001000110111110010101";
WHEN "0101011" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011111111011100000111100110";
WHEN "0101100" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011111101101110111001000101";
WHEN "0101101" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011111011111111010011011011";
WHEN "0101110" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011111010001101010111001111";
WHEN "0101111" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011111000011001000101001110";
WHEN "0110000" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011110110100010011110000000";
WHEN "0110001" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011110100101001100010010010";
WHEN "0110010" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011110010101110010010110000";
WHEN "0110011" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011110000110000110000001000";
WHEN "0110100" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011101110110000111011000111";
WHEN "0110101" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011101100101110110100011101";
WHEN "0110110" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011101010101010011100111001";
WHEN "0110111" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011101000100011110101001100";
WHEN "0111000" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011100110011010111110000111";
WHEN "0111001" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011100100001111111000011101";
WHEN "0111010" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011100010000010100101000000";
WHEN "0111011" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011011111110011000100100100";
WHEN "0111100" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011011101100001010111111110";
WHEN "0111101" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011011011001101100000000011";
WHEN "0111110" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011011000110111011101101010";
WHEN "0111111" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011010110011111010001101001";
WHEN "1000000" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011010100000100111100111000";
WHEN "1000001" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011010001101000100000001111";
WHEN "1000010" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011001111001001111100100111";
WHEN "1000011" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011001100101001010010111011";
WHEN "1000100" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011001010000110100100000101";
WHEN "1000101" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011000111100001110001000001";
WHEN "1000110" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011000100111010111010101011";
WHEN "1000111" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011000010010010000001111111";
WHEN "1001000" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010111111100111000111111011";
WHEN "1001001" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010111100111010001101011110";
WHEN "1001010" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010111010001011010011100110";
WHEN "1001011" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010110111011010011011010011";
WHEN "1001100" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010110100100111100101100110";
WHEN "1001101" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010110001110010110011011111";
WHEN "1001110" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010101110111100000110000001";
WHEN "1001111" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010101100000011011110001110";
WHEN "1010000" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010101001001000111101001000";
WHEN "1010001" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010100110001100100011110100";
WHEN "1010010" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010100011001110010011010110";
WHEN "1010011" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010100000001110001100110010";
WHEN "1010100" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010011101001100010001001111";
WHEN "1010101" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010011010001000100001110100";
WHEN "1010110" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010010111000010111111100101";
WHEN "1010111" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010010011111011101011101100";
WHEN "1011000" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010010000110010100111010001";
WHEN "1011001" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010001101100111110011011011";
WHEN "1011010" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010001010011011010001010100";
WHEN "1011011" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010000111001101000010000111";
WHEN "1011100" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010000011111101000110111110";
WHEN "1011101" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010000000101011100001000010";
WHEN "1011110" => memoryC0_uid207_sinPiZTableGenerator_q <= "01001111101011000010001100001";
WHEN "1011111" => memoryC0_uid207_sinPiZTableGenerator_q <= "01001111010000011011001100111";
WHEN "1100000" => memoryC0_uid207_sinPiZTableGenerator_q <= "01001110110101100111010011111";
WHEN "1100001" => memoryC0_uid207_sinPiZTableGenerator_q <= "01001110011010100110101010111";
WHEN "1100010" => memoryC0_uid207_sinPiZTableGenerator_q <= "01001101111111011001011011101";
WHEN "1100011" => memoryC0_uid207_sinPiZTableGenerator_q <= "01001101100011111111101111111";
WHEN "1100100" => memoryC0_uid207_sinPiZTableGenerator_q <= "01001101001000011001110001011";
WHEN "1100101" => memoryC0_uid207_sinPiZTableGenerator_q <= "01001100101100100111101010001";
WHEN "1100110" => memoryC0_uid207_sinPiZTableGenerator_q <= "01001100010000101001100100001";
WHEN "1100111" => memoryC0_uid207_sinPiZTableGenerator_q <= "01001011110100011111101001011";
WHEN "1101000" => memoryC0_uid207_sinPiZTableGenerator_q <= "01001011011000001010000011111";
WHEN "1101001" => memoryC0_uid207_sinPiZTableGenerator_q <= "01001010111011101000111101111";
WHEN "1101010" => memoryC0_uid207_sinPiZTableGenerator_q <= "01001010011110111100100001011";
WHEN "1101011" => memoryC0_uid207_sinPiZTableGenerator_q <= "01001010000010000100111000111";
WHEN "1101100" => memoryC0_uid207_sinPiZTableGenerator_q <= "01001001100101000010001110101";
WHEN "1101101" => memoryC0_uid207_sinPiZTableGenerator_q <= "01001001000111110100101100111";
WHEN "1101110" => memoryC0_uid207_sinPiZTableGenerator_q <= "01001000101010011100011110001";
WHEN "1101111" => memoryC0_uid207_sinPiZTableGenerator_q <= "01001000001100111001101100110";
WHEN "1110000" => memoryC0_uid207_sinPiZTableGenerator_q <= "01000111101111001100100011011";
WHEN "1110001" => memoryC0_uid207_sinPiZTableGenerator_q <= "01000111010001010101001100101";
WHEN "1110010" => memoryC0_uid207_sinPiZTableGenerator_q <= "01000110110011010011110010111";
WHEN "1110011" => memoryC0_uid207_sinPiZTableGenerator_q <= "01000110010101001000100001000";
WHEN "1110100" => memoryC0_uid207_sinPiZTableGenerator_q <= "01000101110110110011100001101";
WHEN "1110101" => memoryC0_uid207_sinPiZTableGenerator_q <= "01000101011000010100111111100";
WHEN "1110110" => memoryC0_uid207_sinPiZTableGenerator_q <= "01000100111001101101000101100";
WHEN "1110111" => memoryC0_uid207_sinPiZTableGenerator_q <= "01000100011010111011111110011";
WHEN "1111000" => memoryC0_uid207_sinPiZTableGenerator_q <= "01000011111100000001110101000";
WHEN "1111001" => memoryC0_uid207_sinPiZTableGenerator_q <= "01000011011100111110110100010";
WHEN "1111010" => memoryC0_uid207_sinPiZTableGenerator_q <= "01000010111101110011000111010";
WHEN "1111011" => memoryC0_uid207_sinPiZTableGenerator_q <= "01000010011110011110111000111";
WHEN "1111100" => memoryC0_uid207_sinPiZTableGenerator_q <= "01000001111111000010010100010";
WHEN "1111101" => memoryC0_uid207_sinPiZTableGenerator_q <= "01000001011111011101100100011";
WHEN "1111110" => memoryC0_uid207_sinPiZTableGenerator_q <= "01000000111111110000110100011";
WHEN "1111111" => memoryC0_uid207_sinPiZTableGenerator_q <= "01000000011111111100001111011";
WHEN OTHERS =>
memoryC0_uid207_sinPiZTableGenerator_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--sumAHighB_uid220_sinPiZPolyEval(ADD,219)@12
sumAHighB_uid220_sinPiZPolyEval_a <= STD_LOGIC_VECTOR((29 downto 29 => memoryC0_uid207_sinPiZTableGenerator_q(28)) & memoryC0_uid207_sinPiZTableGenerator_q);
sumAHighB_uid220_sinPiZPolyEval_b <= STD_LOGIC_VECTOR((29 downto 22 => highBBits_uid219_sinPiZPolyEval_b(21)) & highBBits_uid219_sinPiZPolyEval_b);
sumAHighB_uid220_sinPiZPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid220_sinPiZPolyEval_a) + SIGNED(sumAHighB_uid220_sinPiZPolyEval_b));
sumAHighB_uid220_sinPiZPolyEval_q <= sumAHighB_uid220_sinPiZPolyEval_o(29 downto 0);
--lowRangeB_uid218_sinPiZPolyEval(BITSELECT,217)@12
lowRangeB_uid218_sinPiZPolyEval_in <= prodXYTruncFR_uid230_pT2_uid217_sinPiZPolyEval_b(1 downto 0);
lowRangeB_uid218_sinPiZPolyEval_b <= lowRangeB_uid218_sinPiZPolyEval_in(1 downto 0);
--s2_uid218_uid221_sinPiZPolyEval(BITJOIN,220)@12
s2_uid218_uid221_sinPiZPolyEval_q <= sumAHighB_uid220_sinPiZPolyEval_q & lowRangeB_uid218_sinPiZPolyEval_b;
--fxpSinRes_uid65_fpCosPiTest(BITSELECT,64)@12
fxpSinRes_uid65_fpCosPiTest_in <= s2_uid218_uid221_sinPiZPolyEval_q(29 downto 0);
fxpSinRes_uid65_fpCosPiTest_b <= fxpSinRes_uid65_fpCosPiTest_in(29 downto 5);
--reg_fxpSinRes_uid65_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_1(REG,270)@12
reg_fxpSinRes_uid65_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fxpSinRes_uid65_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_1_q <= "0000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fxpSinRes_uid65_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_1_q <= fxpSinRes_uid65_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_nor(LOGICAL,622)
ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_nor_a <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_notEnable_q;
ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_nor_b <= ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_sticky_ena_q;
ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_nor_q <= not (ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_nor_a or ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_nor_b);
--ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_sticky_ena(REG,623)
ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_nor_q = "1") THEN
ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_sticky_ena_q <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_enaAnd(LOGICAL,624)
ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_enaAnd_a <= ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_sticky_ena_q;
ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_enaAnd_b <= en;
ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_enaAnd_q <= ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_enaAnd_a and ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_enaAnd_b;
--LeftShiftStage131dto0_uid202_alignedZ_uid57_fpCosPiTest(BITSELECT,201)@7
LeftShiftStage131dto0_uid202_alignedZ_uid57_fpCosPiTest_in <= leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_q(31 downto 0);
LeftShiftStage131dto0_uid202_alignedZ_uid57_fpCosPiTest_b <= LeftShiftStage131dto0_uid202_alignedZ_uid57_fpCosPiTest_in(31 downto 0);
--leftShiftStage2Idx3_uid203_alignedZ_uid57_fpCosPiTest(BITJOIN,202)@7
leftShiftStage2Idx3_uid203_alignedZ_uid57_fpCosPiTest_q <= LeftShiftStage131dto0_uid202_alignedZ_uid57_fpCosPiTest_b & leftShiftStage2Idx3Pad3_uid131_fxpX_uid41_fpCosPiTest_q;
--LeftShiftStage132dto0_uid199_alignedZ_uid57_fpCosPiTest(BITSELECT,198)@7
LeftShiftStage132dto0_uid199_alignedZ_uid57_fpCosPiTest_in <= leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_q(32 downto 0);
LeftShiftStage132dto0_uid199_alignedZ_uid57_fpCosPiTest_b <= LeftShiftStage132dto0_uid199_alignedZ_uid57_fpCosPiTest_in(32 downto 0);
--leftShiftStage2Idx2_uid200_alignedZ_uid57_fpCosPiTest(BITJOIN,199)@7
leftShiftStage2Idx2_uid200_alignedZ_uid57_fpCosPiTest_q <= LeftShiftStage132dto0_uid199_alignedZ_uid57_fpCosPiTest_b & leftShiftStage2Idx2Pad2_uid128_fxpX_uid41_fpCosPiTest_q;
--LeftShiftStage133dto0_uid196_alignedZ_uid57_fpCosPiTest(BITSELECT,195)@7
LeftShiftStage133dto0_uid196_alignedZ_uid57_fpCosPiTest_in <= leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_q(33 downto 0);
LeftShiftStage133dto0_uid196_alignedZ_uid57_fpCosPiTest_b <= LeftShiftStage133dto0_uid196_alignedZ_uid57_fpCosPiTest_in(33 downto 0);
--leftShiftStage2Idx1_uid197_alignedZ_uid57_fpCosPiTest(BITJOIN,196)@7
leftShiftStage2Idx1_uid197_alignedZ_uid57_fpCosPiTest_q <= LeftShiftStage133dto0_uid196_alignedZ_uid57_fpCosPiTest_b & GND_q;
--vStage_uid141_lzcZ_uid56_fpCosPiTest(BITSELECT,140)@3
vStage_uid141_lzcZ_uid56_fpCosPiTest_in <= z_uid54_fpCosPiTest_b(2 downto 0);
vStage_uid141_lzcZ_uid56_fpCosPiTest_b <= vStage_uid141_lzcZ_uid56_fpCosPiTest_in(2 downto 0);
--ld_vStage_uid141_lzcZ_uid56_fpCosPiTest_b_to_leftShiftStage0Idx2_uid180_alignedZ_uid57_fpCosPiTest_b(DELAY,450)@3
ld_vStage_uid141_lzcZ_uid56_fpCosPiTest_b_to_leftShiftStage0Idx2_uid180_alignedZ_uid57_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 3, depth => 3 )
PORT MAP ( xin => vStage_uid141_lzcZ_uid56_fpCosPiTest_b, xout => ld_vStage_uid141_lzcZ_uid56_fpCosPiTest_b_to_leftShiftStage0Idx2_uid180_alignedZ_uid57_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage0Idx2_uid180_alignedZ_uid57_fpCosPiTest(BITJOIN,179)@6
leftShiftStage0Idx2_uid180_alignedZ_uid57_fpCosPiTest_q <= ld_vStage_uid141_lzcZ_uid56_fpCosPiTest_b_to_leftShiftStage0Idx2_uid180_alignedZ_uid57_fpCosPiTest_b_q & leftShiftStage0Idx2Pad32_uid108_fxpX_uid41_fpCosPiTest_q;
--X18dto0_uid176_alignedZ_uid57_fpCosPiTest(BITSELECT,175)@3
X18dto0_uid176_alignedZ_uid57_fpCosPiTest_in <= z_uid54_fpCosPiTest_b(18 downto 0);
X18dto0_uid176_alignedZ_uid57_fpCosPiTest_b <= X18dto0_uid176_alignedZ_uid57_fpCosPiTest_in(18 downto 0);
--ld_X18dto0_uid176_alignedZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx1_uid177_alignedZ_uid57_fpCosPiTest_b_inputreg(DELAY,573)
ld_X18dto0_uid176_alignedZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx1_uid177_alignedZ_uid57_fpCosPiTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 19, depth => 1 )
PORT MAP ( xin => X18dto0_uid176_alignedZ_uid57_fpCosPiTest_b, xout => ld_X18dto0_uid176_alignedZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx1_uid177_alignedZ_uid57_fpCosPiTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_X18dto0_uid176_alignedZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx1_uid177_alignedZ_uid57_fpCosPiTest_b(DELAY,449)@3
ld_X18dto0_uid176_alignedZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx1_uid177_alignedZ_uid57_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 19, depth => 2 )
PORT MAP ( xin => ld_X18dto0_uid176_alignedZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx1_uid177_alignedZ_uid57_fpCosPiTest_b_inputreg_q, xout => ld_X18dto0_uid176_alignedZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx1_uid177_alignedZ_uid57_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage0Idx1_uid177_alignedZ_uid57_fpCosPiTest(BITJOIN,176)@6
leftShiftStage0Idx1_uid177_alignedZ_uid57_fpCosPiTest_q <= ld_X18dto0_uid176_alignedZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx1_uid177_alignedZ_uid57_fpCosPiTest_b_q & leftShiftStage0Idx1Pad16_uid105_fxpX_uid41_fpCosPiTest_q;
--ld_z_uid54_fpCosPiTest_b_to_leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_c_inputreg(DELAY,574)
ld_z_uid54_fpCosPiTest_b_to_leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 35, depth => 1 )
PORT MAP ( xin => z_uid54_fpCosPiTest_b, xout => ld_z_uid54_fpCosPiTest_b_to_leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_z_uid54_fpCosPiTest_b_to_leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_c(DELAY,453)@3
ld_z_uid54_fpCosPiTest_b_to_leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_c : dspba_delay
GENERIC MAP ( width => 35, depth => 2 )
PORT MAP ( xin => ld_z_uid54_fpCosPiTest_b_to_leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_c_inputreg_q, xout => ld_z_uid54_fpCosPiTest_b_to_leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--rVStage_uid138_lzcZ_uid56_fpCosPiTest(BITSELECT,137)@3
rVStage_uid138_lzcZ_uid56_fpCosPiTest_in <= z_uid54_fpCosPiTest_b;
rVStage_uid138_lzcZ_uid56_fpCosPiTest_b <= rVStage_uid138_lzcZ_uid56_fpCosPiTest_in(34 downto 3);
--reg_rVStage_uid138_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid139_lzcZ_uid56_fpCosPiTest_1(REG,247)@3
reg_rVStage_uid138_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid139_lzcZ_uid56_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid138_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid139_lzcZ_uid56_fpCosPiTest_1_q <= "00000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid138_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid139_lzcZ_uid56_fpCosPiTest_1_q <= rVStage_uid138_lzcZ_uid56_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid139_lzcZ_uid56_fpCosPiTest(LOGICAL,138)@4
vCount_uid139_lzcZ_uid56_fpCosPiTest_a <= reg_rVStage_uid138_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid139_lzcZ_uid56_fpCosPiTest_1_q;
vCount_uid139_lzcZ_uid56_fpCosPiTest_b <= leftShiftStage0Idx2Pad32_uid108_fxpX_uid41_fpCosPiTest_q;
vCount_uid139_lzcZ_uid56_fpCosPiTest_q <= "1" when vCount_uid139_lzcZ_uid56_fpCosPiTest_a = vCount_uid139_lzcZ_uid56_fpCosPiTest_b else "0";
--ld_vCount_uid139_lzcZ_uid56_fpCosPiTest_q_to_r_uid172_lzcZ_uid56_fpCosPiTest_f(DELAY,447)@4
ld_vCount_uid139_lzcZ_uid56_fpCosPiTest_q_to_r_uid172_lzcZ_uid56_fpCosPiTest_f : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => vCount_uid139_lzcZ_uid56_fpCosPiTest_q, xout => ld_vCount_uid139_lzcZ_uid56_fpCosPiTest_q_to_r_uid172_lzcZ_uid56_fpCosPiTest_f_q, ena => en(0), clk => clk, aclr => areset );
--mO_uid140_lzcZ_uid56_fpCosPiTest(CONSTANT,139)
mO_uid140_lzcZ_uid56_fpCosPiTest_q <= "11111111111111111111111111111";
--cStage_uid142_lzcZ_uid56_fpCosPiTest(BITJOIN,141)@3
cStage_uid142_lzcZ_uid56_fpCosPiTest_q <= vStage_uid141_lzcZ_uid56_fpCosPiTest_b & mO_uid140_lzcZ_uid56_fpCosPiTest_q;
--reg_cStage_uid142_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid144_lzcZ_uid56_fpCosPiTest_3(REG,249)@3
reg_cStage_uid142_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid144_lzcZ_uid56_fpCosPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cStage_uid142_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid144_lzcZ_uid56_fpCosPiTest_3_q <= "00000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cStage_uid142_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid144_lzcZ_uid56_fpCosPiTest_3_q <= cStage_uid142_lzcZ_uid56_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--vStagei_uid144_lzcZ_uid56_fpCosPiTest(MUX,143)@4
vStagei_uid144_lzcZ_uid56_fpCosPiTest_s <= vCount_uid139_lzcZ_uid56_fpCosPiTest_q;
vStagei_uid144_lzcZ_uid56_fpCosPiTest: PROCESS (vStagei_uid144_lzcZ_uid56_fpCosPiTest_s, en, reg_rVStage_uid138_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid139_lzcZ_uid56_fpCosPiTest_1_q, reg_cStage_uid142_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid144_lzcZ_uid56_fpCosPiTest_3_q)
BEGIN
CASE vStagei_uid144_lzcZ_uid56_fpCosPiTest_s IS
WHEN "0" => vStagei_uid144_lzcZ_uid56_fpCosPiTest_q <= reg_rVStage_uid138_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid139_lzcZ_uid56_fpCosPiTest_1_q;
WHEN "1" => vStagei_uid144_lzcZ_uid56_fpCosPiTest_q <= reg_cStage_uid142_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid144_lzcZ_uid56_fpCosPiTest_3_q;
WHEN OTHERS => vStagei_uid144_lzcZ_uid56_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid146_lzcZ_uid56_fpCosPiTest(BITSELECT,145)@4
rVStage_uid146_lzcZ_uid56_fpCosPiTest_in <= vStagei_uid144_lzcZ_uid56_fpCosPiTest_q;
rVStage_uid146_lzcZ_uid56_fpCosPiTest_b <= rVStage_uid146_lzcZ_uid56_fpCosPiTest_in(31 downto 16);
--reg_rVStage_uid146_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid147_lzcZ_uid56_fpCosPiTest_1(REG,250)@4
reg_rVStage_uid146_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid147_lzcZ_uid56_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid146_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid147_lzcZ_uid56_fpCosPiTest_1_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid146_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid147_lzcZ_uid56_fpCosPiTest_1_q <= rVStage_uid146_lzcZ_uid56_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid147_lzcZ_uid56_fpCosPiTest(LOGICAL,146)@5
vCount_uid147_lzcZ_uid56_fpCosPiTest_a <= reg_rVStage_uid146_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid147_lzcZ_uid56_fpCosPiTest_1_q;
vCount_uid147_lzcZ_uid56_fpCosPiTest_b <= leftShiftStage0Idx1Pad16_uid105_fxpX_uid41_fpCosPiTest_q;
vCount_uid147_lzcZ_uid56_fpCosPiTest_q <= "1" when vCount_uid147_lzcZ_uid56_fpCosPiTest_a = vCount_uid147_lzcZ_uid56_fpCosPiTest_b else "0";
--ld_vCount_uid147_lzcZ_uid56_fpCosPiTest_q_to_r_uid172_lzcZ_uid56_fpCosPiTest_e(DELAY,446)@5
ld_vCount_uid147_lzcZ_uid56_fpCosPiTest_q_to_r_uid172_lzcZ_uid56_fpCosPiTest_e : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vCount_uid147_lzcZ_uid56_fpCosPiTest_q, xout => ld_vCount_uid147_lzcZ_uid56_fpCosPiTest_q_to_r_uid172_lzcZ_uid56_fpCosPiTest_e_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid148_lzcZ_uid56_fpCosPiTest(BITSELECT,147)@4
vStage_uid148_lzcZ_uid56_fpCosPiTest_in <= vStagei_uid144_lzcZ_uid56_fpCosPiTest_q(15 downto 0);
vStage_uid148_lzcZ_uid56_fpCosPiTest_b <= vStage_uid148_lzcZ_uid56_fpCosPiTest_in(15 downto 0);
--reg_vStage_uid148_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid150_lzcZ_uid56_fpCosPiTest_3(REG,252)@4
reg_vStage_uid148_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid150_lzcZ_uid56_fpCosPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid148_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid150_lzcZ_uid56_fpCosPiTest_3_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid148_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid150_lzcZ_uid56_fpCosPiTest_3_q <= vStage_uid148_lzcZ_uid56_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid150_lzcZ_uid56_fpCosPiTest(MUX,149)@5
vStagei_uid150_lzcZ_uid56_fpCosPiTest_s <= vCount_uid147_lzcZ_uid56_fpCosPiTest_q;
vStagei_uid150_lzcZ_uid56_fpCosPiTest: PROCESS (vStagei_uid150_lzcZ_uid56_fpCosPiTest_s, en, reg_rVStage_uid146_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid147_lzcZ_uid56_fpCosPiTest_1_q, reg_vStage_uid148_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid150_lzcZ_uid56_fpCosPiTest_3_q)
BEGIN
CASE vStagei_uid150_lzcZ_uid56_fpCosPiTest_s IS
WHEN "0" => vStagei_uid150_lzcZ_uid56_fpCosPiTest_q <= reg_rVStage_uid146_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid147_lzcZ_uid56_fpCosPiTest_1_q;
WHEN "1" => vStagei_uid150_lzcZ_uid56_fpCosPiTest_q <= reg_vStage_uid148_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid150_lzcZ_uid56_fpCosPiTest_3_q;
WHEN OTHERS => vStagei_uid150_lzcZ_uid56_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid152_lzcZ_uid56_fpCosPiTest(BITSELECT,151)@5
rVStage_uid152_lzcZ_uid56_fpCosPiTest_in <= vStagei_uid150_lzcZ_uid56_fpCosPiTest_q;
rVStage_uid152_lzcZ_uid56_fpCosPiTest_b <= rVStage_uid152_lzcZ_uid56_fpCosPiTest_in(15 downto 8);
--vCount_uid153_lzcZ_uid56_fpCosPiTest(LOGICAL,152)@5
vCount_uid153_lzcZ_uid56_fpCosPiTest_a <= rVStage_uid152_lzcZ_uid56_fpCosPiTest_b;
vCount_uid153_lzcZ_uid56_fpCosPiTest_b <= cstAllZWE_uid21_fpCosPiTest_q;
vCount_uid153_lzcZ_uid56_fpCosPiTest_q <= "1" when vCount_uid153_lzcZ_uid56_fpCosPiTest_a = vCount_uid153_lzcZ_uid56_fpCosPiTest_b else "0";
--reg_vCount_uid153_lzcZ_uid56_fpCosPiTest_0_to_r_uid172_lzcZ_uid56_fpCosPiTest_3(REG,256)@5
reg_vCount_uid153_lzcZ_uid56_fpCosPiTest_0_to_r_uid172_lzcZ_uid56_fpCosPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid153_lzcZ_uid56_fpCosPiTest_0_to_r_uid172_lzcZ_uid56_fpCosPiTest_3_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid153_lzcZ_uid56_fpCosPiTest_0_to_r_uid172_lzcZ_uid56_fpCosPiTest_3_q <= vCount_uid153_lzcZ_uid56_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--vStage_uid154_lzcZ_uid56_fpCosPiTest(BITSELECT,153)@5
vStage_uid154_lzcZ_uid56_fpCosPiTest_in <= vStagei_uid150_lzcZ_uid56_fpCosPiTest_q(7 downto 0);
vStage_uid154_lzcZ_uid56_fpCosPiTest_b <= vStage_uid154_lzcZ_uid56_fpCosPiTest_in(7 downto 0);
--vStagei_uid156_lzcZ_uid56_fpCosPiTest(MUX,155)@5
vStagei_uid156_lzcZ_uid56_fpCosPiTest_s <= vCount_uid153_lzcZ_uid56_fpCosPiTest_q;
vStagei_uid156_lzcZ_uid56_fpCosPiTest: PROCESS (vStagei_uid156_lzcZ_uid56_fpCosPiTest_s, en, rVStage_uid152_lzcZ_uid56_fpCosPiTest_b, vStage_uid154_lzcZ_uid56_fpCosPiTest_b)
BEGIN
CASE vStagei_uid156_lzcZ_uid56_fpCosPiTest_s IS
WHEN "0" => vStagei_uid156_lzcZ_uid56_fpCosPiTest_q <= rVStage_uid152_lzcZ_uid56_fpCosPiTest_b;
WHEN "1" => vStagei_uid156_lzcZ_uid56_fpCosPiTest_q <= vStage_uid154_lzcZ_uid56_fpCosPiTest_b;
WHEN OTHERS => vStagei_uid156_lzcZ_uid56_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid158_lzcZ_uid56_fpCosPiTest(BITSELECT,157)@5
rVStage_uid158_lzcZ_uid56_fpCosPiTest_in <= vStagei_uid156_lzcZ_uid56_fpCosPiTest_q;
rVStage_uid158_lzcZ_uid56_fpCosPiTest_b <= rVStage_uid158_lzcZ_uid56_fpCosPiTest_in(7 downto 4);
--reg_rVStage_uid158_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid159_lzcZ_uid56_fpCosPiTest_1(REG,253)@5
reg_rVStage_uid158_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid159_lzcZ_uid56_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid158_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid159_lzcZ_uid56_fpCosPiTest_1_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid158_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid159_lzcZ_uid56_fpCosPiTest_1_q <= rVStage_uid158_lzcZ_uid56_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid159_lzcZ_uid56_fpCosPiTest(LOGICAL,158)@6
vCount_uid159_lzcZ_uid56_fpCosPiTest_a <= reg_rVStage_uid158_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid159_lzcZ_uid56_fpCosPiTest_1_q;
vCount_uid159_lzcZ_uid56_fpCosPiTest_b <= leftShiftStage1Idx1Pad4_uid114_fxpX_uid41_fpCosPiTest_q;
vCount_uid159_lzcZ_uid56_fpCosPiTest_q <= "1" when vCount_uid159_lzcZ_uid56_fpCosPiTest_a = vCount_uid159_lzcZ_uid56_fpCosPiTest_b else "0";
--vStage_uid160_lzcZ_uid56_fpCosPiTest(BITSELECT,159)@5
vStage_uid160_lzcZ_uid56_fpCosPiTest_in <= vStagei_uid156_lzcZ_uid56_fpCosPiTest_q(3 downto 0);
vStage_uid160_lzcZ_uid56_fpCosPiTest_b <= vStage_uid160_lzcZ_uid56_fpCosPiTest_in(3 downto 0);
--reg_vStage_uid160_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid162_lzcZ_uid56_fpCosPiTest_3(REG,255)@5
reg_vStage_uid160_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid162_lzcZ_uid56_fpCosPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid160_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid162_lzcZ_uid56_fpCosPiTest_3_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid160_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid162_lzcZ_uid56_fpCosPiTest_3_q <= vStage_uid160_lzcZ_uid56_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid162_lzcZ_uid56_fpCosPiTest(MUX,161)@6
vStagei_uid162_lzcZ_uid56_fpCosPiTest_s <= vCount_uid159_lzcZ_uid56_fpCosPiTest_q;
vStagei_uid162_lzcZ_uid56_fpCosPiTest: PROCESS (vStagei_uid162_lzcZ_uid56_fpCosPiTest_s, en, reg_rVStage_uid158_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid159_lzcZ_uid56_fpCosPiTest_1_q, reg_vStage_uid160_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid162_lzcZ_uid56_fpCosPiTest_3_q)
BEGIN
CASE vStagei_uid162_lzcZ_uid56_fpCosPiTest_s IS
WHEN "0" => vStagei_uid162_lzcZ_uid56_fpCosPiTest_q <= reg_rVStage_uid158_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid159_lzcZ_uid56_fpCosPiTest_1_q;
WHEN "1" => vStagei_uid162_lzcZ_uid56_fpCosPiTest_q <= reg_vStage_uid160_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid162_lzcZ_uid56_fpCosPiTest_3_q;
WHEN OTHERS => vStagei_uid162_lzcZ_uid56_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid164_lzcZ_uid56_fpCosPiTest(BITSELECT,163)@6
rVStage_uid164_lzcZ_uid56_fpCosPiTest_in <= vStagei_uid162_lzcZ_uid56_fpCosPiTest_q;
rVStage_uid164_lzcZ_uid56_fpCosPiTest_b <= rVStage_uid164_lzcZ_uid56_fpCosPiTest_in(3 downto 2);
--vCount_uid165_lzcZ_uid56_fpCosPiTest(LOGICAL,164)@6
vCount_uid165_lzcZ_uid56_fpCosPiTest_a <= rVStage_uid164_lzcZ_uid56_fpCosPiTest_b;
vCount_uid165_lzcZ_uid56_fpCosPiTest_b <= leftShiftStage2Idx2Pad2_uid128_fxpX_uid41_fpCosPiTest_q;
vCount_uid165_lzcZ_uid56_fpCosPiTest_q <= "1" when vCount_uid165_lzcZ_uid56_fpCosPiTest_a = vCount_uid165_lzcZ_uid56_fpCosPiTest_b else "0";
--vStage_uid166_lzcZ_uid56_fpCosPiTest(BITSELECT,165)@6
vStage_uid166_lzcZ_uid56_fpCosPiTest_in <= vStagei_uid162_lzcZ_uid56_fpCosPiTest_q(1 downto 0);
vStage_uid166_lzcZ_uid56_fpCosPiTest_b <= vStage_uid166_lzcZ_uid56_fpCosPiTest_in(1 downto 0);
--vStagei_uid168_lzcZ_uid56_fpCosPiTest(MUX,167)@6
vStagei_uid168_lzcZ_uid56_fpCosPiTest_s <= vCount_uid165_lzcZ_uid56_fpCosPiTest_q;
vStagei_uid168_lzcZ_uid56_fpCosPiTest: PROCESS (vStagei_uid168_lzcZ_uid56_fpCosPiTest_s, en, rVStage_uid164_lzcZ_uid56_fpCosPiTest_b, vStage_uid166_lzcZ_uid56_fpCosPiTest_b)
BEGIN
CASE vStagei_uid168_lzcZ_uid56_fpCosPiTest_s IS
WHEN "0" => vStagei_uid168_lzcZ_uid56_fpCosPiTest_q <= rVStage_uid164_lzcZ_uid56_fpCosPiTest_b;
WHEN "1" => vStagei_uid168_lzcZ_uid56_fpCosPiTest_q <= vStage_uid166_lzcZ_uid56_fpCosPiTest_b;
WHEN OTHERS => vStagei_uid168_lzcZ_uid56_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid170_lzcZ_uid56_fpCosPiTest(BITSELECT,169)@6
rVStage_uid170_lzcZ_uid56_fpCosPiTest_in <= vStagei_uid168_lzcZ_uid56_fpCosPiTest_q;
rVStage_uid170_lzcZ_uid56_fpCosPiTest_b <= rVStage_uid170_lzcZ_uid56_fpCosPiTest_in(1 downto 1);
--vCount_uid171_lzcZ_uid56_fpCosPiTest(LOGICAL,170)@6
vCount_uid171_lzcZ_uid56_fpCosPiTest_a <= rVStage_uid170_lzcZ_uid56_fpCosPiTest_b;
vCount_uid171_lzcZ_uid56_fpCosPiTest_b <= GND_q;
vCount_uid171_lzcZ_uid56_fpCosPiTest_q <= "1" when vCount_uid171_lzcZ_uid56_fpCosPiTest_a = vCount_uid171_lzcZ_uid56_fpCosPiTest_b else "0";
--r_uid172_lzcZ_uid56_fpCosPiTest(BITJOIN,171)@6
r_uid172_lzcZ_uid56_fpCosPiTest_q <= ld_vCount_uid139_lzcZ_uid56_fpCosPiTest_q_to_r_uid172_lzcZ_uid56_fpCosPiTest_f_q & ld_vCount_uid147_lzcZ_uid56_fpCosPiTest_q_to_r_uid172_lzcZ_uid56_fpCosPiTest_e_q & reg_vCount_uid153_lzcZ_uid56_fpCosPiTest_0_to_r_uid172_lzcZ_uid56_fpCosPiTest_3_q & vCount_uid159_lzcZ_uid56_fpCosPiTest_q & vCount_uid165_lzcZ_uid56_fpCosPiTest_q & vCount_uid171_lzcZ_uid56_fpCosPiTest_q;
--leftShiftStageSel5Dto4_uid182_alignedZ_uid57_fpCosPiTest(BITSELECT,181)@6
leftShiftStageSel5Dto4_uid182_alignedZ_uid57_fpCosPiTest_in <= r_uid172_lzcZ_uid56_fpCosPiTest_q;
leftShiftStageSel5Dto4_uid182_alignedZ_uid57_fpCosPiTest_b <= leftShiftStageSel5Dto4_uid182_alignedZ_uid57_fpCosPiTest_in(5 downto 4);
--leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest(MUX,182)@6
leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_s <= leftShiftStageSel5Dto4_uid182_alignedZ_uid57_fpCosPiTest_b;
leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest: PROCESS (leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_s, en, ld_z_uid54_fpCosPiTest_b_to_leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_c_q, leftShiftStage0Idx1_uid177_alignedZ_uid57_fpCosPiTest_q, leftShiftStage0Idx2_uid180_alignedZ_uid57_fpCosPiTest_q, cstZwSwF_uid15_fpCosPiTest_q)
BEGIN
CASE leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_s IS
WHEN "00" => leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_q <= ld_z_uid54_fpCosPiTest_b_to_leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_c_q;
WHEN "01" => leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_q <= leftShiftStage0Idx1_uid177_alignedZ_uid57_fpCosPiTest_q;
WHEN "10" => leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_q <= leftShiftStage0Idx2_uid180_alignedZ_uid57_fpCosPiTest_q;
WHEN "11" => leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_q <= cstZwSwF_uid15_fpCosPiTest_q;
WHEN OTHERS => leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage022dto0_uid191_alignedZ_uid57_fpCosPiTest(BITSELECT,190)@6
LeftShiftStage022dto0_uid191_alignedZ_uid57_fpCosPiTest_in <= leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_q(22 downto 0);
LeftShiftStage022dto0_uid191_alignedZ_uid57_fpCosPiTest_b <= LeftShiftStage022dto0_uid191_alignedZ_uid57_fpCosPiTest_in(22 downto 0);
--leftShiftStage1Idx3_uid192_alignedZ_uid57_fpCosPiTest(BITJOIN,191)@6
leftShiftStage1Idx3_uid192_alignedZ_uid57_fpCosPiTest_q <= LeftShiftStage022dto0_uid191_alignedZ_uid57_fpCosPiTest_b & leftShiftStage1Idx3Pad12_uid120_fxpX_uid41_fpCosPiTest_q;
--reg_leftShiftStage1Idx3_uid192_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_5(REG,261)@6
reg_leftShiftStage1Idx3_uid192_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx3_uid192_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_5_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx3_uid192_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_5_q <= leftShiftStage1Idx3_uid192_alignedZ_uid57_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage026dto0_uid188_alignedZ_uid57_fpCosPiTest(BITSELECT,187)@6
LeftShiftStage026dto0_uid188_alignedZ_uid57_fpCosPiTest_in <= leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_q(26 downto 0);
LeftShiftStage026dto0_uid188_alignedZ_uid57_fpCosPiTest_b <= LeftShiftStage026dto0_uid188_alignedZ_uid57_fpCosPiTest_in(26 downto 0);
--leftShiftStage1Idx2_uid189_alignedZ_uid57_fpCosPiTest(BITJOIN,188)@6
leftShiftStage1Idx2_uid189_alignedZ_uid57_fpCosPiTest_q <= LeftShiftStage026dto0_uid188_alignedZ_uid57_fpCosPiTest_b & cstAllZWE_uid21_fpCosPiTest_q;
--reg_leftShiftStage1Idx2_uid189_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_4(REG,260)@6
reg_leftShiftStage1Idx2_uid189_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx2_uid189_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_4_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx2_uid189_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_4_q <= leftShiftStage1Idx2_uid189_alignedZ_uid57_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage030dto0_uid185_alignedZ_uid57_fpCosPiTest(BITSELECT,184)@6
LeftShiftStage030dto0_uid185_alignedZ_uid57_fpCosPiTest_in <= leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_q(30 downto 0);
LeftShiftStage030dto0_uid185_alignedZ_uid57_fpCosPiTest_b <= LeftShiftStage030dto0_uid185_alignedZ_uid57_fpCosPiTest_in(30 downto 0);
--leftShiftStage1Idx1_uid186_alignedZ_uid57_fpCosPiTest(BITJOIN,185)@6
leftShiftStage1Idx1_uid186_alignedZ_uid57_fpCosPiTest_q <= LeftShiftStage030dto0_uid185_alignedZ_uid57_fpCosPiTest_b & leftShiftStage1Idx1Pad4_uid114_fxpX_uid41_fpCosPiTest_q;
--reg_leftShiftStage1Idx1_uid186_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_3(REG,259)@6
reg_leftShiftStage1Idx1_uid186_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx1_uid186_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_3_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx1_uid186_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_3_q <= leftShiftStage1Idx1_uid186_alignedZ_uid57_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--reg_leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_2(REG,258)@6
reg_leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_2_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_2_q <= leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel3Dto2_uid193_alignedZ_uid57_fpCosPiTest(BITSELECT,192)@6
leftShiftStageSel3Dto2_uid193_alignedZ_uid57_fpCosPiTest_in <= r_uid172_lzcZ_uid56_fpCosPiTest_q(3 downto 0);
leftShiftStageSel3Dto2_uid193_alignedZ_uid57_fpCosPiTest_b <= leftShiftStageSel3Dto2_uid193_alignedZ_uid57_fpCosPiTest_in(3 downto 2);
--reg_leftShiftStageSel3Dto2_uid193_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_1(REG,257)@6
reg_leftShiftStageSel3Dto2_uid193_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel3Dto2_uid193_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel3Dto2_uid193_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_1_q <= leftShiftStageSel3Dto2_uid193_alignedZ_uid57_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest(MUX,193)@7
leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_s <= reg_leftShiftStageSel3Dto2_uid193_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_1_q;
leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest: PROCESS (leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_s, en, reg_leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_2_q, reg_leftShiftStage1Idx1_uid186_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_3_q, reg_leftShiftStage1Idx2_uid189_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_4_q, reg_leftShiftStage1Idx3_uid192_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_5_q)
BEGIN
CASE leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_s IS
WHEN "00" => leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_q <= reg_leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_2_q;
WHEN "01" => leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_q <= reg_leftShiftStage1Idx1_uid186_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_3_q;
WHEN "10" => leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_q <= reg_leftShiftStage1Idx2_uid189_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_4_q;
WHEN "11" => leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_q <= reg_leftShiftStage1Idx3_uid192_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_5_q;
WHEN OTHERS => leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--leftShiftStageSel1Dto0_uid204_alignedZ_uid57_fpCosPiTest(BITSELECT,203)@6
leftShiftStageSel1Dto0_uid204_alignedZ_uid57_fpCosPiTest_in <= r_uid172_lzcZ_uid56_fpCosPiTest_q(1 downto 0);
leftShiftStageSel1Dto0_uid204_alignedZ_uid57_fpCosPiTest_b <= leftShiftStageSel1Dto0_uid204_alignedZ_uid57_fpCosPiTest_in(1 downto 0);
--reg_leftShiftStageSel1Dto0_uid204_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest_1(REG,262)@6
reg_leftShiftStageSel1Dto0_uid204_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel1Dto0_uid204_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel1Dto0_uid204_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest_1_q <= leftShiftStageSel1Dto0_uid204_alignedZ_uid57_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest(MUX,204)@7
leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest_s <= reg_leftShiftStageSel1Dto0_uid204_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest_1_q;
leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest: PROCESS (leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest_s, en, leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_q, leftShiftStage2Idx1_uid197_alignedZ_uid57_fpCosPiTest_q, leftShiftStage2Idx2_uid200_alignedZ_uid57_fpCosPiTest_q, leftShiftStage2Idx3_uid203_alignedZ_uid57_fpCosPiTest_q)
BEGIN
CASE leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest_s IS
WHEN "00" => leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest_q <= leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_q;
WHEN "01" => leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest_q <= leftShiftStage2Idx1_uid197_alignedZ_uid57_fpCosPiTest_q;
WHEN "10" => leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest_q <= leftShiftStage2Idx2_uid200_alignedZ_uid57_fpCosPiTest_q;
WHEN "11" => leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest_q <= leftShiftStage2Idx3_uid203_alignedZ_uid57_fpCosPiTest_q;
WHEN OTHERS => leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--alignedZLow_uid58_fpCosPiTest(BITSELECT,57)@7
alignedZLow_uid58_fpCosPiTest_in <= leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest_q;
alignedZLow_uid58_fpCosPiTest_b <= alignedZLow_uid58_fpCosPiTest_in(34 downto 11);
--ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_inputreg(DELAY,612)
ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 24, depth => 1 )
PORT MAP ( xin => alignedZLow_uid58_fpCosPiTest_b, xout => ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem(DUALMEM,613)
ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_reset0 <= areset;
ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_ia <= ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_inputreg_q;
ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_aa <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdreg_q;
ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_ab <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdmux_q;
ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 24,
widthad_a => 2,
numwords_a => 3,
width_b => 24,
widthad_b => 2,
numwords_b => 3,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_iq,
address_a => ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_aa,
data_a => ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_ia
);
ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_q <= ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_iq(23 downto 0);
--reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0(REG,269)@12
reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_q <= ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest(MULT,222)@13
prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_pr <= UNSIGNED(prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_a) * UNSIGNED(prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_b);
prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_a <= (others => '0');
prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_b <= (others => '0');
prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_a <= reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_q;
prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_b <= reg_fxpSinRes_uid65_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_1_q;
prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_s1 <= STD_LOGIC_VECTOR(prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_pr);
END IF;
END IF;
END PROCESS;
prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_q <= prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid224_mul2xSinRes_uid66_fpCosPiTest(BITSELECT,223)@16
prodXYTruncFR_uid224_mul2xSinRes_uid66_fpCosPiTest_in <= prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_q;
prodXYTruncFR_uid224_mul2xSinRes_uid66_fpCosPiTest_b <= prodXYTruncFR_uid224_mul2xSinRes_uid66_fpCosPiTest_in(48 downto 23);
--normBit_uid67_fpCosPiTest(BITSELECT,66)@16
normBit_uid67_fpCosPiTest_in <= prodXYTruncFR_uid224_mul2xSinRes_uid66_fpCosPiTest_b;
normBit_uid67_fpCosPiTest_b <= normBit_uid67_fpCosPiTest_in(25 downto 25);
--cstAllZWF_uid9_fpCosPiTest(CONSTANT,8)
cstAllZWF_uid9_fpCosPiTest_q <= "00000000000000000000000";
--rndExpUpdate_uid72_uid73_fpCosPiTest(BITJOIN,72)@16
rndExpUpdate_uid72_uid73_fpCosPiTest_q <= normBit_uid67_fpCosPiTest_b & cstAllZWF_uid9_fpCosPiTest_q & VCC_q;
--ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_nor(LOGICAL,558)
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_nor_a <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_notEnable_q;
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_nor_b <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_sticky_ena_q;
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_nor_q <= not (ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_nor_a or ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_nor_b);
--ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_sticky_ena(REG,559)
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_nor_q = "1") THEN
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_sticky_ena_q <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_enaAnd(LOGICAL,560)
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_enaAnd_a <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_sticky_ena_q;
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_enaAnd_b <= en;
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_enaAnd_q <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_enaAnd_a and ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_enaAnd_b;
--reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1(REG,271)@6
reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q <= r_uid172_lzcZ_uid56_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem(DUALMEM,549)
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_reset0 <= areset;
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_ia <= reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q;
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_aa <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdreg_q;
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_ab <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdmux_q;
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 6,
widthad_a => 3,
numwords_a => 7,
width_b => 6,
widthad_b => 3,
numwords_b => 7,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_iq,
address_a => ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_aa,
data_a => ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_ia
);
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_q <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_iq(5 downto 0);
--cstBiasM1_uid11_fpCosPiTest(CONSTANT,10)
cstBiasM1_uid11_fpCosPiTest_q <= "01111110";
--expHardCase_uid59_fpCosPiTest(SUB,58)@15
expHardCase_uid59_fpCosPiTest_a <= STD_LOGIC_VECTOR("0" & cstBiasM1_uid11_fpCosPiTest_q);
expHardCase_uid59_fpCosPiTest_b <= STD_LOGIC_VECTOR("000" & ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_q);
expHardCase_uid59_fpCosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expHardCase_uid59_fpCosPiTest_a) - UNSIGNED(expHardCase_uid59_fpCosPiTest_b));
expHardCase_uid59_fpCosPiTest_q <= expHardCase_uid59_fpCosPiTest_o(8 downto 0);
--expP_uid60_fpCosPiTest(BITSELECT,59)@15
expP_uid60_fpCosPiTest_in <= expHardCase_uid59_fpCosPiTest_q(7 downto 0);
expP_uid60_fpCosPiTest_b <= expP_uid60_fpCosPiTest_in(7 downto 0);
--reg_expP_uid60_fpCosPiTest_0_to_expFracPreRnd_uid71_uid71_fpCosPiTest_1(REG,272)@15
reg_expP_uid60_fpCosPiTest_0_to_expFracPreRnd_uid71_uid71_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expP_uid60_fpCosPiTest_0_to_expFracPreRnd_uid71_uid71_fpCosPiTest_1_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expP_uid60_fpCosPiTest_0_to_expFracPreRnd_uid71_uid71_fpCosPiTest_1_q <= expP_uid60_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--highRes_uid68_fpCosPiTest(BITSELECT,67)@16
highRes_uid68_fpCosPiTest_in <= prodXYTruncFR_uid224_mul2xSinRes_uid66_fpCosPiTest_b(24 downto 0);
highRes_uid68_fpCosPiTest_b <= highRes_uid68_fpCosPiTest_in(24 downto 1);
--lowRes_uid69_fpCosPiTest(BITSELECT,68)@16
lowRes_uid69_fpCosPiTest_in <= prodXYTruncFR_uid224_mul2xSinRes_uid66_fpCosPiTest_b(23 downto 0);
lowRes_uid69_fpCosPiTest_b <= lowRes_uid69_fpCosPiTest_in(23 downto 0);
--fracRCompPreRnd_uid70_fpCosPiTest(MUX,69)@16
fracRCompPreRnd_uid70_fpCosPiTest_s <= normBit_uid67_fpCosPiTest_b;
fracRCompPreRnd_uid70_fpCosPiTest: PROCESS (fracRCompPreRnd_uid70_fpCosPiTest_s, en, lowRes_uid69_fpCosPiTest_b, highRes_uid68_fpCosPiTest_b)
BEGIN
CASE fracRCompPreRnd_uid70_fpCosPiTest_s IS
WHEN "0" => fracRCompPreRnd_uid70_fpCosPiTest_q <= lowRes_uid69_fpCosPiTest_b;
WHEN "1" => fracRCompPreRnd_uid70_fpCosPiTest_q <= highRes_uid68_fpCosPiTest_b;
WHEN OTHERS => fracRCompPreRnd_uid70_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--expFracPreRnd_uid71_uid71_fpCosPiTest(BITJOIN,70)@16
expFracPreRnd_uid71_uid71_fpCosPiTest_q <= reg_expP_uid60_fpCosPiTest_0_to_expFracPreRnd_uid71_uid71_fpCosPiTest_1_q & fracRCompPreRnd_uid70_fpCosPiTest_q;
--expFracComp_uid74_fpCosPiTest(ADD,73)@16
expFracComp_uid74_fpCosPiTest_a <= STD_LOGIC_VECTOR("0" & expFracPreRnd_uid71_uid71_fpCosPiTest_q);
expFracComp_uid74_fpCosPiTest_b <= STD_LOGIC_VECTOR("00000000" & rndExpUpdate_uid72_uid73_fpCosPiTest_q);
expFracComp_uid74_fpCosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expFracComp_uid74_fpCosPiTest_a) + UNSIGNED(expFracComp_uid74_fpCosPiTest_b));
expFracComp_uid74_fpCosPiTest_q <= expFracComp_uid74_fpCosPiTest_o(32 downto 0);
--expRComp_uid76_fpCosPiTest(BITSELECT,75)@16
expRComp_uid76_fpCosPiTest_in <= expFracComp_uid74_fpCosPiTest_q(31 downto 0);
expRComp_uid76_fpCosPiTest_b <= expRComp_uid76_fpCosPiTest_in(31 downto 24);
--fracXIsZero_uid27_fpCosPiTest(LOGICAL,26)@0
fracXIsZero_uid27_fpCosPiTest_a <= fracX_uid7_fpCosPiTest_b;
fracXIsZero_uid27_fpCosPiTest_b <= cstAllZWF_uid9_fpCosPiTest_q;
fracXIsZero_uid27_fpCosPiTest_q <= "1" when fracXIsZero_uid27_fpCosPiTest_a = fracXIsZero_uid27_fpCosPiTest_b else "0";
--InvFracXIsZero_uid29_fpCosPiTest(LOGICAL,28)@0
InvFracXIsZero_uid29_fpCosPiTest_a <= fracXIsZero_uid27_fpCosPiTest_q;
InvFracXIsZero_uid29_fpCosPiTest_q <= not InvFracXIsZero_uid29_fpCosPiTest_a;
--expXIsMax_uid25_fpCosPiTest(LOGICAL,24)@0
expXIsMax_uid25_fpCosPiTest_a <= expX_uid6_fpCosPiTest_b;
expXIsMax_uid25_fpCosPiTest_b <= cstAllOWE_uid8_fpCosPiTest_q;
expXIsMax_uid25_fpCosPiTest_q <= "1" when expXIsMax_uid25_fpCosPiTest_a = expXIsMax_uid25_fpCosPiTest_b else "0";
--exc_N_uid30_fpCosPiTest(LOGICAL,29)@0
exc_N_uid30_fpCosPiTest_a <= expXIsMax_uid25_fpCosPiTest_q;
exc_N_uid30_fpCosPiTest_b <= InvFracXIsZero_uid29_fpCosPiTest_q;
exc_N_uid30_fpCosPiTest_q <= exc_N_uid30_fpCosPiTest_a and exc_N_uid30_fpCosPiTest_b;
--InvExc_N_uid31_fpCosPiTest(LOGICAL,30)@0
InvExc_N_uid31_fpCosPiTest_a <= exc_N_uid30_fpCosPiTest_q;
InvExc_N_uid31_fpCosPiTest_q <= not InvExc_N_uid31_fpCosPiTest_a;
--exc_I_uid28_fpCosPiTest(LOGICAL,27)@0
exc_I_uid28_fpCosPiTest_a <= expXIsMax_uid25_fpCosPiTest_q;
exc_I_uid28_fpCosPiTest_b <= fracXIsZero_uid27_fpCosPiTest_q;
exc_I_uid28_fpCosPiTest_q <= exc_I_uid28_fpCosPiTest_a and exc_I_uid28_fpCosPiTest_b;
--InvExc_I_uid32_fpCosPiTest(LOGICAL,31)@0
InvExc_I_uid32_fpCosPiTest_a <= exc_I_uid28_fpCosPiTest_q;
InvExc_I_uid32_fpCosPiTest_q <= not InvExc_I_uid32_fpCosPiTest_a;
--expXIsZero_uid23_fpCosPiTest(LOGICAL,22)@0
expXIsZero_uid23_fpCosPiTest_a <= expX_uid6_fpCosPiTest_b;
expXIsZero_uid23_fpCosPiTest_b <= cstAllZWE_uid21_fpCosPiTest_q;
expXIsZero_uid23_fpCosPiTest_q <= "1" when expXIsZero_uid23_fpCosPiTest_a = expXIsZero_uid23_fpCosPiTest_b else "0";
--InvExpXIsZero_uid33_fpCosPiTest(LOGICAL,32)@0
InvExpXIsZero_uid33_fpCosPiTest_a <= expXIsZero_uid23_fpCosPiTest_q;
InvExpXIsZero_uid33_fpCosPiTest_q <= not InvExpXIsZero_uid33_fpCosPiTest_a;
--exc_R_uid34_fpCosPiTest(LOGICAL,33)@0
exc_R_uid34_fpCosPiTest_a <= InvExpXIsZero_uid33_fpCosPiTest_q;
exc_R_uid34_fpCosPiTest_b <= InvExc_I_uid32_fpCosPiTest_q;
exc_R_uid34_fpCosPiTest_c <= InvExc_N_uid31_fpCosPiTest_q;
exc_R_uid34_fpCosPiTest_q <= exc_R_uid34_fpCosPiTest_a and exc_R_uid34_fpCosPiTest_b and exc_R_uid34_fpCosPiTest_c;
--ld_exc_R_uid34_fpCosPiTest_q_to_xIsInt_uid80_fpCosPiTest_a(DELAY,337)@0
ld_exc_R_uid34_fpCosPiTest_q_to_xIsInt_uid80_fpCosPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => exc_R_uid34_fpCosPiTest_q, xout => ld_exc_R_uid34_fpCosPiTest_q_to_xIsInt_uid80_fpCosPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--xIsHalf_uid83_fpCosPiTest(LOGICAL,82)@2
xIsHalf_uid83_fpCosPiTest_a <= ld_exc_R_uid34_fpCosPiTest_q_to_xIsInt_uid80_fpCosPiTest_a_q;
xIsHalf_uid83_fpCosPiTest_b <= fxpXFracHalf_uid46_fpCosPiTest_q;
xIsHalf_uid83_fpCosPiTest_c <= InvCosXIsOne_uid77_fpCosPiTest_q;
xIsHalf_uid83_fpCosPiTest_d <= InvXEvenInt_uid81_fpCosPiTest_q;
xIsHalf_uid83_fpCosPiTest_q <= xIsHalf_uid83_fpCosPiTest_a and xIsHalf_uid83_fpCosPiTest_b and xIsHalf_uid83_fpCosPiTest_c and xIsHalf_uid83_fpCosPiTest_d;
--ld_xIsHalf_uid83_fpCosPiTest_q_to_expRPostExc1_uid91_fpCosPiTest_b(DELAY,355)@2
ld_xIsHalf_uid83_fpCosPiTest_q_to_expRPostExc1_uid91_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 14 )
PORT MAP ( xin => xIsHalf_uid83_fpCosPiTest_q, xout => ld_xIsHalf_uid83_fpCosPiTest_q_to_expRPostExc1_uid91_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--expRPostExc1_uid91_fpCosPiTest(MUX,90)@16
expRPostExc1_uid91_fpCosPiTest_s <= ld_xIsHalf_uid83_fpCosPiTest_q_to_expRPostExc1_uid91_fpCosPiTest_b_q;
expRPostExc1_uid91_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expRPostExc1_uid91_fpCosPiTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE expRPostExc1_uid91_fpCosPiTest_s IS
WHEN "0" => expRPostExc1_uid91_fpCosPiTest_q <= expRComp_uid76_fpCosPiTest_b;
WHEN "1" => expRPostExc1_uid91_fpCosPiTest_q <= cstAllZWE_uid21_fpCosPiTest_q;
WHEN OTHERS => expRPostExc1_uid91_fpCosPiTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_nor(LOGICAL,570)
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_nor_a <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_notEnable_q;
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_nor_b <= ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_sticky_ena_q;
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_nor_q <= not (ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_nor_a or ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_nor_b);
--ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_mem_top(CONSTANT,566)
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_mem_top_q <= "01100";
--ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_cmp(LOGICAL,567)
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_cmp_a <= ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_mem_top_q;
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdmux_q);
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_cmp_q <= "1" when ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_cmp_a = ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_cmp_b else "0";
--ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_cmpReg(REG,568)
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_cmpReg_q <= ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_sticky_ena(REG,571)
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_nor_q = "1") THEN
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_sticky_ena_q <= ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_enaAnd(LOGICAL,572)
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_enaAnd_a <= ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_sticky_ena_q;
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_enaAnd_b <= en;
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_enaAnd_q <= ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_enaAnd_a and ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_enaAnd_b;
--ld_expXIsZero_uid23_fpCosPiTest_q_to_xIntOrXZOrCosOne_uid93_fpCosPiTest_b(DELAY,359)@0
ld_expXIsZero_uid23_fpCosPiTest_q_to_xIntOrXZOrCosOne_uid93_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => expXIsZero_uid23_fpCosPiTest_q, xout => ld_expXIsZero_uid23_fpCosPiTest_q_to_xIntOrXZOrCosOne_uid93_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--fxpXFracZero_uid45_fpCosPiTest(LOGICAL,44)@2
fxpXFracZero_uid45_fpCosPiTest_a <= reg_fxpXFrac_uid43_fpCosPiTest_0_to_fxpXFracZero_uid45_fpCosPiTest_1_q;
fxpXFracZero_uid45_fpCosPiTest_b <= STD_LOGIC_VECTOR("0" & cstZwSwF_uid15_fpCosPiTest_q);
fxpXFracZero_uid45_fpCosPiTest_q <= "1" when fxpXFracZero_uid45_fpCosPiTest_a = fxpXFracZero_uid45_fpCosPiTest_b else "0";
--fracZCosNotOne_uid78_fpCosPiTest(LOGICAL,77)@2
fracZCosNotOne_uid78_fpCosPiTest_a <= fxpXFracZero_uid45_fpCosPiTest_q;
fracZCosNotOne_uid78_fpCosPiTest_b <= InvCosXIsOne_uid77_fpCosPiTest_q;
fracZCosNotOne_uid78_fpCosPiTest_q <= fracZCosNotOne_uid78_fpCosPiTest_a and fracZCosNotOne_uid78_fpCosPiTest_b;
--evenIntCosNotOneFZ_uid79_fpCosPiTest(LOGICAL,78)@2
evenIntCosNotOneFZ_uid79_fpCosPiTest_a <= ld_xEvenInt_uid35_fpCosPiTest_c_to_evenIntCosNotOneFZ_uid79_fpCosPiTest_a_q;
evenIntCosNotOneFZ_uid79_fpCosPiTest_b <= fracZCosNotOne_uid78_fpCosPiTest_q;
evenIntCosNotOneFZ_uid79_fpCosPiTest_q <= evenIntCosNotOneFZ_uid79_fpCosPiTest_a or evenIntCosNotOneFZ_uid79_fpCosPiTest_b;
--xIsInt_uid80_fpCosPiTest(LOGICAL,79)@2
xIsInt_uid80_fpCosPiTest_a <= ld_exc_R_uid34_fpCosPiTest_q_to_xIsInt_uid80_fpCosPiTest_a_q;
xIsInt_uid80_fpCosPiTest_b <= evenIntCosNotOneFZ_uid79_fpCosPiTest_q;
xIsInt_uid80_fpCosPiTest_q <= xIsInt_uid80_fpCosPiTest_a and xIsInt_uid80_fpCosPiTest_b;
--xIntOrXZOrCosOne_uid93_fpCosPiTest(LOGICAL,92)@2
xIntOrXZOrCosOne_uid93_fpCosPiTest_a <= xIsInt_uid80_fpCosPiTest_q;
xIntOrXZOrCosOne_uid93_fpCosPiTest_b <= ld_expXIsZero_uid23_fpCosPiTest_q_to_xIntOrXZOrCosOne_uid93_fpCosPiTest_b_q;
xIntOrXZOrCosOne_uid93_fpCosPiTest_c <= ld_cosXIsOne_uid36_fpCosPiTest_c_to_InvCosXIsOne_uid77_fpCosPiTest_a_q;
xIntOrXZOrCosOne_uid93_fpCosPiTest_q <= xIntOrXZOrCosOne_uid93_fpCosPiTest_a or xIntOrXZOrCosOne_uid93_fpCosPiTest_b or xIntOrXZOrCosOne_uid93_fpCosPiTest_c;
--excRNaN_uid84_fpCosPiTest(LOGICAL,83)@0
excRNaN_uid84_fpCosPiTest_a <= exc_N_uid30_fpCosPiTest_q;
excRNaN_uid84_fpCosPiTest_b <= exc_I_uid28_fpCosPiTest_q;
excRNaN_uid84_fpCosPiTest_q <= excRNaN_uid84_fpCosPiTest_a or excRNaN_uid84_fpCosPiTest_b;
--rInfOrNaN_uid92_fpCosPiTest(LOGICAL,91)@0
rInfOrNaN_uid92_fpCosPiTest_a <= GND_q;
rInfOrNaN_uid92_fpCosPiTest_b <= excRNaN_uid84_fpCosPiTest_q;
rInfOrNaN_uid92_fpCosPiTest_q <= rInfOrNaN_uid92_fpCosPiTest_a or rInfOrNaN_uid92_fpCosPiTest_b;
--ld_rInfOrNaN_uid92_fpCosPiTest_q_to_join_uid94_fpCosPiTest_a(DELAY,361)@0
ld_rInfOrNaN_uid92_fpCosPiTest_q_to_join_uid94_fpCosPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => rInfOrNaN_uid92_fpCosPiTest_q, xout => ld_rInfOrNaN_uid92_fpCosPiTest_q_to_join_uid94_fpCosPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--join_uid94_fpCosPiTest(BITJOIN,93)@2
join_uid94_fpCosPiTest_q <= xIntOrXZOrCosOne_uid93_fpCosPiTest_q & ld_rInfOrNaN_uid92_fpCosPiTest_q_to_join_uid94_fpCosPiTest_a_q;
--reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1(REG,274)@2
reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q <= join_uid94_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt(COUNTER,562)
-- every=1, low=0, high=12, step=1, init=1
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt_i = 11 THEN
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt_eq <= '1';
ELSE
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt_eq = '1') THEN
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt_i <= ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt_i - 12;
ELSE
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt_i <= ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt_i,4));
--ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdreg(REG,563)
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdreg_q <= ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdmux(MUX,564)
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdmux_s <= en;
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdmux: PROCESS (ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdmux_s, ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdreg_q, ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt_q)
BEGIN
CASE ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdmux_s IS
WHEN "0" => ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdmux_q <= ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdreg_q;
WHEN "1" => ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdmux_q <= ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem(DUALMEM,561)
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_reset0 <= areset;
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_ia <= reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q;
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_aa <= ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdreg_q;
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_ab <= ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdmux_q;
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 2,
widthad_a => 4,
numwords_a => 13,
width_b => 2,
widthad_b => 4,
numwords_b => 13,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_iq,
address_a => ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_aa,
data_a => ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_ia
);
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_q <= ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_iq(1 downto 0);
--expRPostExc_uid95_fpCosPiTest(MUX,94)@17
expRPostExc_uid95_fpCosPiTest_s <= ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_q;
expRPostExc_uid95_fpCosPiTest: PROCESS (expRPostExc_uid95_fpCosPiTest_s, en, expRPostExc1_uid91_fpCosPiTest_q, cstAllOWE_uid8_fpCosPiTest_q, cstBias_uid10_fpCosPiTest_q, cstBias_uid10_fpCosPiTest_q)
BEGIN
CASE expRPostExc_uid95_fpCosPiTest_s IS
WHEN "00" => expRPostExc_uid95_fpCosPiTest_q <= expRPostExc1_uid91_fpCosPiTest_q;
WHEN "01" => expRPostExc_uid95_fpCosPiTest_q <= cstAllOWE_uid8_fpCosPiTest_q;
WHEN "10" => expRPostExc_uid95_fpCosPiTest_q <= cstBias_uid10_fpCosPiTest_q;
WHEN "11" => expRPostExc_uid95_fpCosPiTest_q <= cstBias_uid10_fpCosPiTest_q;
WHEN OTHERS => expRPostExc_uid95_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--oneFracRPostExc2_uid87_fpCosPiTest(CONSTANT,86)
oneFracRPostExc2_uid87_fpCosPiTest_q <= "00000000000000000000001";
--fracRComp_uid75_fpCosPiTest(BITSELECT,74)@16
fracRComp_uid75_fpCosPiTest_in <= expFracComp_uid74_fpCosPiTest_q(23 downto 0);
fracRComp_uid75_fpCosPiTest_b <= fracRComp_uid75_fpCosPiTest_in(23 downto 1);
--reg_xIsHalf_uid83_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_5(REG,243)@2
reg_xIsHalf_uid83_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xIsHalf_uid83_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_5_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xIsHalf_uid83_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_5_q <= xIsHalf_uid83_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--reg_expXIsZero_uid23_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_4(REG,242)@2
reg_expXIsZero_uid23_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expXIsZero_uid23_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_4_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expXIsZero_uid23_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_4_q <= ld_expXIsZero_uid23_fpCosPiTest_q_to_xIntOrXZOrCosOne_uid93_fpCosPiTest_b_q;
END IF;
END IF;
END PROCESS;
--reg_fxpXFracHalf_uid46_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_3(REG,241)@2
reg_fxpXFracHalf_uid46_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fxpXFracHalf_uid46_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_3_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fxpXFracHalf_uid46_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_3_q <= fxpXFracHalf_uid46_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--reg_xIsInt_uid80_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_2(REG,240)@2
reg_xIsInt_uid80_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xIsInt_uid80_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xIsInt_uid80_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_2_q <= xIsInt_uid80_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--reg_cosXIsOne_uid36_fpCosPiTest_1_to_bigCond_uid85_fpCosPiTest_1(REG,239)@0
reg_cosXIsOne_uid36_fpCosPiTest_1_to_bigCond_uid85_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cosXIsOne_uid36_fpCosPiTest_1_to_bigCond_uid85_fpCosPiTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cosXIsOne_uid36_fpCosPiTest_1_to_bigCond_uid85_fpCosPiTest_1_q <= cosXIsOne_uid36_fpCosPiTest_c;
END IF;
END IF;
END PROCESS;
--ld_reg_cosXIsOne_uid36_fpCosPiTest_1_to_bigCond_uid85_fpCosPiTest_1_q_to_bigCond_uid85_fpCosPiTest_a(DELAY,346)@1
ld_reg_cosXIsOne_uid36_fpCosPiTest_1_to_bigCond_uid85_fpCosPiTest_1_q_to_bigCond_uid85_fpCosPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => reg_cosXIsOne_uid36_fpCosPiTest_1_to_bigCond_uid85_fpCosPiTest_1_q, xout => ld_reg_cosXIsOne_uid36_fpCosPiTest_1_to_bigCond_uid85_fpCosPiTest_1_q_to_bigCond_uid85_fpCosPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--bigCond_uid85_fpCosPiTest(LOGICAL,84)@3
bigCond_uid85_fpCosPiTest_a <= ld_reg_cosXIsOne_uid36_fpCosPiTest_1_to_bigCond_uid85_fpCosPiTest_1_q_to_bigCond_uid85_fpCosPiTest_a_q;
bigCond_uid85_fpCosPiTest_b <= reg_xIsInt_uid80_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_2_q;
bigCond_uid85_fpCosPiTest_c <= reg_fxpXFracHalf_uid46_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_3_q;
bigCond_uid85_fpCosPiTest_d <= reg_expXIsZero_uid23_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_4_q;
bigCond_uid85_fpCosPiTest_f <= reg_xIsHalf_uid83_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_5_q;
bigCond_uid85_fpCosPiTest_g <= GND_q;
bigCond_uid85_fpCosPiTest_q <= bigCond_uid85_fpCosPiTest_a or bigCond_uid85_fpCosPiTest_b or bigCond_uid85_fpCosPiTest_c or bigCond_uid85_fpCosPiTest_d or bigCond_uid85_fpCosPiTest_f or bigCond_uid85_fpCosPiTest_g;
--ld_bigCond_uid85_fpCosPiTest_q_to_fracRPostExc1_uid86_fpCosPiTest_b(DELAY,351)@3
ld_bigCond_uid85_fpCosPiTest_q_to_fracRPostExc1_uid86_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 13 )
PORT MAP ( xin => bigCond_uid85_fpCosPiTest_q, xout => ld_bigCond_uid85_fpCosPiTest_q_to_fracRPostExc1_uid86_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--fracRPostExc1_uid86_fpCosPiTest(MUX,85)@16
fracRPostExc1_uid86_fpCosPiTest_s <= ld_bigCond_uid85_fpCosPiTest_q_to_fracRPostExc1_uid86_fpCosPiTest_b_q;
fracRPostExc1_uid86_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
fracRPostExc1_uid86_fpCosPiTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE fracRPostExc1_uid86_fpCosPiTest_s IS
WHEN "0" => fracRPostExc1_uid86_fpCosPiTest_q <= fracRComp_uid75_fpCosPiTest_b;
WHEN "1" => fracRPostExc1_uid86_fpCosPiTest_q <= cstAllZWF_uid9_fpCosPiTest_q;
WHEN OTHERS => fracRPostExc1_uid86_fpCosPiTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--reg_excRNaN_uid84_fpCosPiTest_0_to_fracRPostExc_uid88_fpCosPiTest_1(REG,273)@0
reg_excRNaN_uid84_fpCosPiTest_0_to_fracRPostExc_uid88_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_excRNaN_uid84_fpCosPiTest_0_to_fracRPostExc_uid88_fpCosPiTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_excRNaN_uid84_fpCosPiTest_0_to_fracRPostExc_uid88_fpCosPiTest_1_q <= excRNaN_uid84_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_excRNaN_uid84_fpCosPiTest_0_to_fracRPostExc_uid88_fpCosPiTest_1_q_to_fracRPostExc_uid88_fpCosPiTest_b(DELAY,353)@1
ld_reg_excRNaN_uid84_fpCosPiTest_0_to_fracRPostExc_uid88_fpCosPiTest_1_q_to_fracRPostExc_uid88_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 16 )
PORT MAP ( xin => reg_excRNaN_uid84_fpCosPiTest_0_to_fracRPostExc_uid88_fpCosPiTest_1_q, xout => ld_reg_excRNaN_uid84_fpCosPiTest_0_to_fracRPostExc_uid88_fpCosPiTest_1_q_to_fracRPostExc_uid88_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--fracRPostExc_uid88_fpCosPiTest(MUX,87)@17
fracRPostExc_uid88_fpCosPiTest_s <= ld_reg_excRNaN_uid84_fpCosPiTest_0_to_fracRPostExc_uid88_fpCosPiTest_1_q_to_fracRPostExc_uid88_fpCosPiTest_b_q;
fracRPostExc_uid88_fpCosPiTest: PROCESS (fracRPostExc_uid88_fpCosPiTest_s, en, fracRPostExc1_uid86_fpCosPiTest_q, oneFracRPostExc2_uid87_fpCosPiTest_q)
BEGIN
CASE fracRPostExc_uid88_fpCosPiTest_s IS
WHEN "0" => fracRPostExc_uid88_fpCosPiTest_q <= fracRPostExc1_uid86_fpCosPiTest_q;
WHEN "1" => fracRPostExc_uid88_fpCosPiTest_q <= oneFracRPostExc2_uid87_fpCosPiTest_q;
WHEN OTHERS => fracRPostExc_uid88_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--R_uid102_fpCosPiTest(BITJOIN,101)@17
R_uid102_fpCosPiTest_q <= ld_signR_uid101_fpCosPiTest_q_to_R_uid102_fpCosPiTest_c_q & expRPostExc_uid95_fpCosPiTest_q & fracRPostExc_uid88_fpCosPiTest_q;
--xOut(GPOUT,4)@17
q <= R_uid102_fpCosPiTest_q;
end normal;
|
-----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Release Version 13.1
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing device programming or simulation files), and
-- any associated documentation or information are expressly subject to the
-- terms and conditions of the Altera Program License Subscription Agreement,
-- Altera MegaCore Function License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for the sole
-- purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
-----------------------------------------------------------------------------
-- VHDL created from fp_cospi_s5
-- VHDL created on Wed Feb 27 15:22:33 2013
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.all;
use std.TextIO.all;
use work.dspba_library_package.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
entity fp_cospi_s5 is
port (
a : in std_logic_vector(31 downto 0);
en : in std_logic_vector(0 downto 0);
q : out std_logic_vector(31 downto 0);
clk : in std_logic;
areset : in std_logic
);
end;
architecture normal of fp_cospi_s5 is
attribute altera_attribute : string;
attribute altera_attribute of normal : architecture is "-name NOT_GATE_PUSH_BACK OFF; -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON; -name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410";
signal GND_q : std_logic_vector (0 downto 0);
signal VCC_q : std_logic_vector (0 downto 0);
signal cstAllOWE_uid8_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal cstAllZWF_uid9_fpCosPiTest_q : std_logic_vector (22 downto 0);
signal cstBias_uid10_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal cstBiasM1_uid11_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal cstBiasPwF_uid12_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal biasMwShiftMO_uid13_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal cst01pWShift_uid14_fpCosPiTest_q : std_logic_vector (12 downto 0);
signal cstZwSwF_uid15_fpCosPiTest_q : std_logic_vector (34 downto 0);
signal cstAllZWE_uid21_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal rangeReducedFxPX_uid51_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal rangeReducedFxPX_uid51_fpCosPiTest_q : std_logic_vector (35 downto 0);
signal fracRPostExc1_uid86_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal fracRPostExc1_uid86_fpCosPiTest_q : std_logic_vector (22 downto 0);
signal oneFracRPostExc2_uid87_fpCosPiTest_q : std_logic_vector (22 downto 0);
signal expRPostExc1_uid91_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal expRPostExc1_uid91_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal signRComp_uid99_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal signRComp_uid99_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal signRComp_uid99_fpCosPiTest_c : std_logic_vector(0 downto 0);
signal signRComp_uid99_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal signR_uid101_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal signR_uid101_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal signR_uid101_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal leftShiftStage0Idx1Pad16_uid105_fxpX_uid41_fpCosPiTest_q : std_logic_vector (15 downto 0);
signal leftShiftStage0Idx2Pad32_uid108_fxpX_uid41_fpCosPiTest_q : std_logic_vector (31 downto 0);
signal leftShiftStage0Idx3_uid111_fxpX_uid41_fpCosPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage1Idx1Pad4_uid114_fxpX_uid41_fpCosPiTest_q : std_logic_vector (3 downto 0);
signal leftShiftStage1Idx3Pad12_uid120_fxpX_uid41_fpCosPiTest_q : std_logic_vector (11 downto 0);
signal leftShiftStage2Idx2Pad2_uid128_fxpX_uid41_fpCosPiTest_q : std_logic_vector (1 downto 0);
signal leftShiftStage2Idx3Pad3_uid131_fxpX_uid41_fpCosPiTest_q : std_logic_vector (2 downto 0);
signal mO_uid140_lzcZ_uid56_fpCosPiTest_q : std_logic_vector (28 downto 0);
signal memoryC2_uid209_sinPiZTableGenerator_q : std_logic_vector(13 downto 0);
signal prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_a : std_logic_vector (23 downto 0);
signal prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_b : std_logic_vector (24 downto 0);
signal prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_s1 : std_logic_vector (48 downto 0);
signal prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_pr : UNSIGNED (48 downto 0);
signal prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_q : std_logic_vector (48 downto 0);
signal prodXY_uid226_pT1_uid211_sinPiZPolyEval_a : std_logic_vector (13 downto 0);
signal prodXY_uid226_pT1_uid211_sinPiZPolyEval_b : std_logic_vector (13 downto 0);
signal prodXY_uid226_pT1_uid211_sinPiZPolyEval_s1 : std_logic_vector (27 downto 0);
signal prodXY_uid226_pT1_uid211_sinPiZPolyEval_pr : SIGNED (28 downto 0);
signal prodXY_uid226_pT1_uid211_sinPiZPolyEval_q : std_logic_vector (27 downto 0);
signal prodXY_uid229_pT2_uid217_sinPiZPolyEval_a : std_logic_vector (15 downto 0);
signal prodXY_uid229_pT2_uid217_sinPiZPolyEval_b : std_logic_vector (22 downto 0);
signal prodXY_uid229_pT2_uid217_sinPiZPolyEval_s1 : std_logic_vector (38 downto 0);
signal prodXY_uid229_pT2_uid217_sinPiZPolyEval_pr : SIGNED (39 downto 0);
signal prodXY_uid229_pT2_uid217_sinPiZPolyEval_q : std_logic_vector (38 downto 0);
signal reg_leftShiftStageSel3Dto2_uid123_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_2_q : std_logic_vector (36 downto 0);
signal reg_leftShiftStage1Idx1_uid116_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_3_q : std_logic_vector (36 downto 0);
signal reg_leftShiftStage1Idx2_uid119_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_4_q : std_logic_vector (36 downto 0);
signal reg_leftShiftStage1Idx3_uid122_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_5_q : std_logic_vector (36 downto 0);
signal reg_leftShiftStageSel1Dto0_uid134_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_fxpXFrac_uid43_fpCosPiTest_0_to_fxpXFracZero_uid45_fpCosPiTest_1_q : std_logic_vector (35 downto 0);
signal reg_cosXIsOne_uid36_fpCosPiTest_1_to_bigCond_uid85_fpCosPiTest_1_q : std_logic_vector (0 downto 0);
signal reg_xIsInt_uid80_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_2_q : std_logic_vector (0 downto 0);
signal reg_fxpXFracHalf_uid46_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_3_q : std_logic_vector (0 downto 0);
signal reg_expXIsZero_uid23_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_4_q : std_logic_vector (0 downto 0);
signal reg_xIsHalf_uid83_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_5_q : std_logic_vector (0 downto 0);
signal reg_pad_o_uid16_uid47_fpCosPiTest_0_to_oMFxpXFrac_uid47_fpCosPiTest_0_q : std_logic_vector (36 downto 0);
signal reg_pad_half_uid17_uid52_fpCosPiTest_0_to_z_halfMRRFxPXE_uid52_fpCosPiTest_0_q : std_logic_vector (35 downto 0);
signal reg_rVStage_uid138_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid139_lzcZ_uid56_fpCosPiTest_1_q : std_logic_vector (31 downto 0);
signal reg_cStage_uid142_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid144_lzcZ_uid56_fpCosPiTest_3_q : std_logic_vector (31 downto 0);
signal reg_rVStage_uid146_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid147_lzcZ_uid56_fpCosPiTest_1_q : std_logic_vector (15 downto 0);
signal reg_vStage_uid148_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid150_lzcZ_uid56_fpCosPiTest_3_q : std_logic_vector (15 downto 0);
signal reg_rVStage_uid158_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid159_lzcZ_uid56_fpCosPiTest_1_q : std_logic_vector (3 downto 0);
signal reg_vStage_uid160_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid162_lzcZ_uid56_fpCosPiTest_3_q : std_logic_vector (3 downto 0);
signal reg_vCount_uid153_lzcZ_uid56_fpCosPiTest_0_to_r_uid172_lzcZ_uid56_fpCosPiTest_3_q : std_logic_vector (0 downto 0);
signal reg_leftShiftStageSel3Dto2_uid193_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_2_q : std_logic_vector (34 downto 0);
signal reg_leftShiftStage1Idx1_uid186_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_3_q : std_logic_vector (34 downto 0);
signal reg_leftShiftStage1Idx2_uid189_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_4_q : std_logic_vector (34 downto 0);
signal reg_leftShiftStage1Idx3_uid192_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_5_q : std_logic_vector (34 downto 0);
signal reg_leftShiftStageSel1Dto0_uid204_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_zAddr_uid62_fpCosPiTest_0_to_memoryC2_uid209_sinPiZTableGenerator_0_q : std_logic_vector (6 downto 0);
signal reg_yT1_uid210_sinPiZPolyEval_0_to_prodXY_uid226_pT1_uid211_sinPiZPolyEval_0_q : std_logic_vector (13 downto 0);
signal reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_q : std_logic_vector (15 downto 0);
signal reg_s1_uid212_uid215_sinPiZPolyEval_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_1_q : std_logic_vector (22 downto 0);
signal reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_q : std_logic_vector (23 downto 0);
signal reg_fxpSinRes_uid65_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_1_q : std_logic_vector (24 downto 0);
signal reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q : std_logic_vector (5 downto 0);
signal reg_expP_uid60_fpCosPiTest_0_to_expFracPreRnd_uid71_uid71_fpCosPiTest_1_q : std_logic_vector (7 downto 0);
signal reg_excRNaN_uid84_fpCosPiTest_0_to_fracRPostExc_uid88_fpCosPiTest_1_q : std_logic_vector (0 downto 0);
signal reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q : std_logic_vector (1 downto 0);
signal ld_FxpXFrac35_uid44_fpCosPiTest_b_to_rangeReducedFxPX_uid51_fpCosPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_fxpXFrac_uid43_fpCosPiTest_b_to_rangeReducedFxPX_uid51_fpCosPiTest_c_q : std_logic_vector (35 downto 0);
signal ld_cosXIsOne_uid36_fpCosPiTest_c_to_InvCosXIsOne_uid77_fpCosPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_xEvenInt_uid35_fpCosPiTest_c_to_evenIntCosNotOneFZ_uid79_fpCosPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_exc_R_uid34_fpCosPiTest_q_to_xIsInt_uid80_fpCosPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_reg_cosXIsOne_uid36_fpCosPiTest_1_to_bigCond_uid85_fpCosPiTest_1_q_to_bigCond_uid85_fpCosPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_bigCond_uid85_fpCosPiTest_q_to_fracRPostExc1_uid86_fpCosPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_reg_excRNaN_uid84_fpCosPiTest_0_to_fracRPostExc_uid88_fpCosPiTest_1_q_to_fracRPostExc_uid88_fpCosPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_xIsHalf_uid83_fpCosPiTest_q_to_expRPostExc1_uid91_fpCosPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_expXIsZero_uid23_fpCosPiTest_q_to_xIntOrXZOrCosOne_uid93_fpCosPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_rInfOrNaN_uid92_fpCosPiTest_q_to_join_uid94_fpCosPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_xParityXorHalfParity_uid96_fpCosPiTest_q_to_signRComp_uid99_fpCosPiTest_c_q : std_logic_vector (0 downto 0);
signal ld_fxpXFracHalf_uid46_fpCosPiTest_q_to_InvFxpXFracHalf_uid100_fpCosPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_signR_uid101_fpCosPiTest_q_to_R_uid102_fpCosPiTest_c_q : std_logic_vector (0 downto 0);
signal ld_vCount_uid147_lzcZ_uid56_fpCosPiTest_q_to_r_uid172_lzcZ_uid56_fpCosPiTest_e_q : std_logic_vector (0 downto 0);
signal ld_vCount_uid139_lzcZ_uid56_fpCosPiTest_q_to_r_uid172_lzcZ_uid56_fpCosPiTest_f_q : std_logic_vector (0 downto 0);
signal ld_X18dto0_uid176_alignedZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx1_uid177_alignedZ_uid57_fpCosPiTest_b_q : std_logic_vector (18 downto 0);
signal ld_vStage_uid141_lzcZ_uid56_fpCosPiTest_b_to_leftShiftStage0Idx2_uid180_alignedZ_uid57_fpCosPiTest_b_q : std_logic_vector (2 downto 0);
signal ld_z_uid54_fpCosPiTest_b_to_leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_c_q : std_logic_vector (34 downto 0);
signal ld_reg_yT1_uid210_sinPiZPolyEval_0_to_prodXY_uid226_pT1_uid211_sinPiZPolyEval_0_q_to_prodXY_uid226_pT1_uid211_sinPiZPolyEval_a_q : std_logic_vector (13 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_reset0 : std_logic;
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_ia : std_logic_vector (5 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_iq : std_logic_vector (5 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_q : std_logic_vector (5 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt_eq : std_logic;
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_mem_top_q : std_logic_vector (3 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve : boolean;
attribute preserve of ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_sticky_ena_q : signal is true;
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_reset0 : std_logic;
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_ia : std_logic_vector (1 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_iq : std_logic_vector (1 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_q : std_logic_vector (1 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt_eq : std_logic;
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_mem_top_q : std_logic_vector (4 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_sticky_ena_q : signal is true;
signal ld_X18dto0_uid176_alignedZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx1_uid177_alignedZ_uid57_fpCosPiTest_b_inputreg_q : std_logic_vector (18 downto 0);
signal ld_z_uid54_fpCosPiTest_b_to_leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_c_inputreg_q : std_logic_vector (34 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_reset0 : std_logic;
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_ia : std_logic_vector (6 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_iq : std_logic_vector (6 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_q : std_logic_vector (6 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_sticky_ena_q : signal is true;
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_reset0 : std_logic;
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_ia : std_logic_vector (6 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_aa : std_logic_vector (1 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_ab : std_logic_vector (1 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_iq : std_logic_vector (6 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_q : std_logic_vector (6 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt_q : std_logic_vector(1 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt_i : unsigned(1 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt_eq : std_logic;
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdreg_q : std_logic_vector (1 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_mem_top_q : std_logic_vector (2 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_sticky_ena_q : signal is true;
signal ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_inputreg_q : std_logic_vector (15 downto 0);
signal ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_reset0 : std_logic;
signal ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_ia : std_logic_vector (15 downto 0);
signal ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_aa : std_logic_vector (1 downto 0);
signal ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_ab : std_logic_vector (1 downto 0);
signal ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_iq : std_logic_vector (15 downto 0);
signal ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_q : std_logic_vector (15 downto 0);
signal ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_sticky_ena_q : signal is true;
signal ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_inputreg_q : std_logic_vector (23 downto 0);
signal ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_reset0 : std_logic;
signal ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_ia : std_logic_vector (23 downto 0);
signal ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_aa : std_logic_vector (1 downto 0);
signal ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_ab : std_logic_vector (1 downto 0);
signal ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_iq : std_logic_vector (23 downto 0);
signal ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_q : std_logic_vector (23 downto 0);
signal ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_sticky_ena_q : signal is true;
signal pad_o_uid16_uid47_fpCosPiTest_q : std_logic_vector (36 downto 0);
signal pad_half_uid17_uid52_fpCosPiTest_q : std_logic_vector (35 downto 0);
signal bigCond_uid85_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal bigCond_uid85_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal bigCond_uid85_fpCosPiTest_c : std_logic_vector(0 downto 0);
signal bigCond_uid85_fpCosPiTest_d : std_logic_vector(0 downto 0);
signal bigCond_uid85_fpCosPiTest_f : std_logic_vector(0 downto 0);
signal bigCond_uid85_fpCosPiTest_g : std_logic_vector(0 downto 0);
signal bigCond_uid85_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal InvCosXIsOne_uid77_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal InvCosXIsOne_uid77_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal InvXEvenInt_uid81_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal InvXEvenInt_uid81_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal InvFxpXFracHalf_uid100_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal InvFxpXFracHalf_uid100_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal cstHalfwSwFP1_uid18_fpCosPiTest_q : std_logic_vector (35 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_notEnable_a : std_logic_vector(0 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_notEnable_q : std_logic_vector(0 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdmux_q : std_logic_vector (1 downto 0);
signal expX_uid6_fpCosPiTest_in : std_logic_vector (30 downto 0);
signal expX_uid6_fpCosPiTest_b : std_logic_vector (7 downto 0);
signal fracX_uid7_fpCosPiTest_in : std_logic_vector (22 downto 0);
signal fracX_uid7_fpCosPiTest_b : std_logic_vector (22 downto 0);
signal expXIsZero_uid23_fpCosPiTest_a : std_logic_vector(7 downto 0);
signal expXIsZero_uid23_fpCosPiTest_b : std_logic_vector(7 downto 0);
signal expXIsZero_uid23_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal expXIsMax_uid25_fpCosPiTest_a : std_logic_vector(7 downto 0);
signal expXIsMax_uid25_fpCosPiTest_b : std_logic_vector(7 downto 0);
signal expXIsMax_uid25_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal fracXIsZero_uid27_fpCosPiTest_a : std_logic_vector(22 downto 0);
signal fracXIsZero_uid27_fpCosPiTest_b : std_logic_vector(22 downto 0);
signal fracXIsZero_uid27_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal exc_I_uid28_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal exc_I_uid28_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal exc_I_uid28_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal xEvenInt_uid35_fpCosPiTest_a : std_logic_vector(10 downto 0);
signal xEvenInt_uid35_fpCosPiTest_b : std_logic_vector(10 downto 0);
signal xEvenInt_uid35_fpCosPiTest_o : std_logic_vector (10 downto 0);
signal xEvenInt_uid35_fpCosPiTest_cin : std_logic_vector (0 downto 0);
signal xEvenInt_uid35_fpCosPiTest_c : std_logic_vector (0 downto 0);
signal cosXIsOne_uid36_fpCosPiTest_a : std_logic_vector(10 downto 0);
signal cosXIsOne_uid36_fpCosPiTest_b : std_logic_vector(10 downto 0);
signal cosXIsOne_uid36_fpCosPiTest_o : std_logic_vector (10 downto 0);
signal cosXIsOne_uid36_fpCosPiTest_cin : std_logic_vector (0 downto 0);
signal cosXIsOne_uid36_fpCosPiTest_c : std_logic_vector (0 downto 0);
signal shiftValFxPX_uid38_fpCosPiTest_a : std_logic_vector(8 downto 0);
signal shiftValFxPX_uid38_fpCosPiTest_b : std_logic_vector(8 downto 0);
signal shiftValFxPX_uid38_fpCosPiTest_o : std_logic_vector (8 downto 0);
signal shiftValFxPX_uid38_fpCosPiTest_q : std_logic_vector (8 downto 0);
signal fxpXFracZero_uid45_fpCosPiTest_a : std_logic_vector(35 downto 0);
signal fxpXFracZero_uid45_fpCosPiTest_b : std_logic_vector(35 downto 0);
signal fxpXFracZero_uid45_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal fxpXFracHalf_uid46_fpCosPiTest_a : std_logic_vector(35 downto 0);
signal fxpXFracHalf_uid46_fpCosPiTest_b : std_logic_vector(35 downto 0);
signal fxpXFracHalf_uid46_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal oMFxpXFrac_uid47_fpCosPiTest_a : std_logic_vector(37 downto 0);
signal oMFxpXFrac_uid47_fpCosPiTest_b : std_logic_vector(37 downto 0);
signal oMFxpXFrac_uid47_fpCosPiTest_o : std_logic_vector (37 downto 0);
signal oMFxpXFrac_uid47_fpCosPiTest_q : std_logic_vector (37 downto 0);
signal z_halfMRRFxPXE_uid52_fpCosPiTest_a : std_logic_vector(36 downto 0);
signal z_halfMRRFxPXE_uid52_fpCosPiTest_b : std_logic_vector(36 downto 0);
signal z_halfMRRFxPXE_uid52_fpCosPiTest_o : std_logic_vector (36 downto 0);
signal z_halfMRRFxPXE_uid52_fpCosPiTest_q : std_logic_vector (36 downto 0);
signal expHardCase_uid59_fpCosPiTest_a : std_logic_vector(8 downto 0);
signal expHardCase_uid59_fpCosPiTest_b : std_logic_vector(8 downto 0);
signal expHardCase_uid59_fpCosPiTest_o : std_logic_vector (8 downto 0);
signal expHardCase_uid59_fpCosPiTest_q : std_logic_vector (8 downto 0);
signal fracZCosNotOne_uid78_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal fracZCosNotOne_uid78_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal fracZCosNotOne_uid78_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal evenIntCosNotOneFZ_uid79_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal evenIntCosNotOneFZ_uid79_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal evenIntCosNotOneFZ_uid79_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal xIsInt_uid80_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal xIsInt_uid80_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal xIsInt_uid80_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal xIsHalf_uid83_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal xIsHalf_uid83_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal xIsHalf_uid83_fpCosPiTest_c : std_logic_vector(0 downto 0);
signal xIsHalf_uid83_fpCosPiTest_d : std_logic_vector(0 downto 0);
signal xIsHalf_uid83_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal fracRPostExc_uid88_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal fracRPostExc_uid88_fpCosPiTest_q : std_logic_vector (22 downto 0);
signal xIntOrXZOrCosOne_uid93_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal xIntOrXZOrCosOne_uid93_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal xIntOrXZOrCosOne_uid93_fpCosPiTest_c : std_logic_vector(0 downto 0);
signal xIntOrXZOrCosOne_uid93_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal expRPostExc_uid95_fpCosPiTest_s : std_logic_vector (1 downto 0);
signal expRPostExc_uid95_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_q : std_logic_vector (36 downto 0);
signal vCount_uid139_lzcZ_uid56_fpCosPiTest_a : std_logic_vector(31 downto 0);
signal vCount_uid139_lzcZ_uid56_fpCosPiTest_b : std_logic_vector(31 downto 0);
signal vCount_uid139_lzcZ_uid56_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid144_lzcZ_uid56_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid144_lzcZ_uid56_fpCosPiTest_q : std_logic_vector (31 downto 0);
signal vCount_uid147_lzcZ_uid56_fpCosPiTest_a : std_logic_vector(15 downto 0);
signal vCount_uid147_lzcZ_uid56_fpCosPiTest_b : std_logic_vector(15 downto 0);
signal vCount_uid147_lzcZ_uid56_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid150_lzcZ_uid56_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid150_lzcZ_uid56_fpCosPiTest_q : std_logic_vector (15 downto 0);
signal vCount_uid159_lzcZ_uid56_fpCosPiTest_a : std_logic_vector(3 downto 0);
signal vCount_uid159_lzcZ_uid56_fpCosPiTest_b : std_logic_vector(3 downto 0);
signal vCount_uid159_lzcZ_uid56_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid162_lzcZ_uid56_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid162_lzcZ_uid56_fpCosPiTest_q : std_logic_vector (3 downto 0);
signal leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_q : std_logic_vector (34 downto 0);
signal memoryC0_uid207_sinPiZTableGenerator_q : std_logic_vector(28 downto 0);
signal memoryC1_uid208_sinPiZTableGenerator_q : std_logic_vector(20 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal leftShiftStage0Idx1_uid177_alignedZ_uid57_fpCosPiTest_q : std_logic_vector (34 downto 0);
signal leftShiftStage0Idx2_uid180_alignedZ_uid57_fpCosPiTest_q : std_logic_vector (34 downto 0);
signal prodXYTruncFR_uid224_mul2xSinRes_uid66_fpCosPiTest_in : std_logic_vector (48 downto 0);
signal prodXYTruncFR_uid224_mul2xSinRes_uid66_fpCosPiTest_b : std_logic_vector (25 downto 0);
signal prodXYTruncFR_uid227_pT1_uid211_sinPiZPolyEval_in : std_logic_vector (27 downto 0);
signal prodXYTruncFR_uid227_pT1_uid211_sinPiZPolyEval_b : std_logic_vector (14 downto 0);
signal prodXYTruncFR_uid230_pT2_uid217_sinPiZPolyEval_in : std_logic_vector (38 downto 0);
signal prodXYTruncFR_uid230_pT2_uid217_sinPiZPolyEval_b : std_logic_vector (23 downto 0);
signal join_uid94_fpCosPiTest_q : std_logic_vector (1 downto 0);
signal R_uid102_fpCosPiTest_q : std_logic_vector (31 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_cmp_a : std_logic_vector(3 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_cmp_b : std_logic_vector(3 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_cmp_a : std_logic_vector(4 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_cmp_b : std_logic_vector(4 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_cmp_a : std_logic_vector(2 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_cmp_b : std_logic_vector(2 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_nor_q : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_nor_q : std_logic_vector(0 downto 0);
signal oFracX_uid37_uid37_fpCosPiTest_q : std_logic_vector (23 downto 0);
signal InvExpXIsZero_uid33_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid33_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid29_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid29_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal InvExc_I_uid32_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal InvExc_I_uid32_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal fxpShifterBits_uid40_fpCosPiTest_in : std_logic_vector (5 downto 0);
signal fxpShifterBits_uid40_fpCosPiTest_b : std_logic_vector (5 downto 0);
signal oMFxpXFrac_uid49_fpCosPiTest_in : std_logic_vector (35 downto 0);
signal oMFxpXFrac_uid49_fpCosPiTest_b : std_logic_vector (35 downto 0);
signal z_uid54_fpCosPiTest_in : std_logic_vector (34 downto 0);
signal z_uid54_fpCosPiTest_b : std_logic_vector (34 downto 0);
signal expP_uid60_fpCosPiTest_in : std_logic_vector (7 downto 0);
signal expP_uid60_fpCosPiTest_b : std_logic_vector (7 downto 0);
signal LeftShiftStage135dto0_uid126_fxpX_uid41_fpCosPiTest_in : std_logic_vector (35 downto 0);
signal LeftShiftStage135dto0_uid126_fxpX_uid41_fpCosPiTest_b : std_logic_vector (35 downto 0);
signal LeftShiftStage134dto0_uid129_fxpX_uid41_fpCosPiTest_in : std_logic_vector (34 downto 0);
signal LeftShiftStage134dto0_uid129_fxpX_uid41_fpCosPiTest_b : std_logic_vector (34 downto 0);
signal LeftShiftStage133dto0_uid132_fxpX_uid41_fpCosPiTest_in : std_logic_vector (33 downto 0);
signal LeftShiftStage133dto0_uid132_fxpX_uid41_fpCosPiTest_b : std_logic_vector (33 downto 0);
signal rVStage_uid146_lzcZ_uid56_fpCosPiTest_in : std_logic_vector (31 downto 0);
signal rVStage_uid146_lzcZ_uid56_fpCosPiTest_b : std_logic_vector (15 downto 0);
signal vStage_uid148_lzcZ_uid56_fpCosPiTest_in : std_logic_vector (15 downto 0);
signal vStage_uid148_lzcZ_uid56_fpCosPiTest_b : std_logic_vector (15 downto 0);
signal rVStage_uid152_lzcZ_uid56_fpCosPiTest_in : std_logic_vector (15 downto 0);
signal rVStage_uid152_lzcZ_uid56_fpCosPiTest_b : std_logic_vector (7 downto 0);
signal vStage_uid154_lzcZ_uid56_fpCosPiTest_in : std_logic_vector (7 downto 0);
signal vStage_uid154_lzcZ_uid56_fpCosPiTest_b : std_logic_vector (7 downto 0);
signal rVStage_uid164_lzcZ_uid56_fpCosPiTest_in : std_logic_vector (3 downto 0);
signal rVStage_uid164_lzcZ_uid56_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal vStage_uid166_lzcZ_uid56_fpCosPiTest_in : std_logic_vector (1 downto 0);
signal vStage_uid166_lzcZ_uid56_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal LeftShiftStage133dto0_uid196_alignedZ_uid57_fpCosPiTest_in : std_logic_vector (33 downto 0);
signal LeftShiftStage133dto0_uid196_alignedZ_uid57_fpCosPiTest_b : std_logic_vector (33 downto 0);
signal LeftShiftStage132dto0_uid199_alignedZ_uid57_fpCosPiTest_in : std_logic_vector (32 downto 0);
signal LeftShiftStage132dto0_uid199_alignedZ_uid57_fpCosPiTest_b : std_logic_vector (32 downto 0);
signal LeftShiftStage131dto0_uid202_alignedZ_uid57_fpCosPiTest_in : std_logic_vector (31 downto 0);
signal LeftShiftStage131dto0_uid202_alignedZ_uid57_fpCosPiTest_b : std_logic_vector (31 downto 0);
signal normBit_uid67_fpCosPiTest_in : std_logic_vector (25 downto 0);
signal normBit_uid67_fpCosPiTest_b : std_logic_vector (0 downto 0);
signal highRes_uid68_fpCosPiTest_in : std_logic_vector (24 downto 0);
signal highRes_uid68_fpCosPiTest_b : std_logic_vector (23 downto 0);
signal lowRes_uid69_fpCosPiTest_in : std_logic_vector (23 downto 0);
signal lowRes_uid69_fpCosPiTest_b : std_logic_vector (23 downto 0);
signal lowRangeB_uid212_sinPiZPolyEval_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid212_sinPiZPolyEval_b : std_logic_vector (0 downto 0);
signal highBBits_uid213_sinPiZPolyEval_in : std_logic_vector (14 downto 0);
signal highBBits_uid213_sinPiZPolyEval_b : std_logic_vector (13 downto 0);
signal lowRangeB_uid218_sinPiZPolyEval_in : std_logic_vector (1 downto 0);
signal lowRangeB_uid218_sinPiZPolyEval_b : std_logic_vector (1 downto 0);
signal highBBits_uid219_sinPiZPolyEval_in : std_logic_vector (23 downto 0);
signal highBBits_uid219_sinPiZPolyEval_b : std_logic_vector (21 downto 0);
signal oFracXExt_uid39_fpCosPiTest_q : std_logic_vector (36 downto 0);
signal exc_N_uid30_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal exc_N_uid30_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal exc_N_uid30_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal leftShiftStageSel5Dto4_uid112_fxpX_uid41_fpCosPiTest_in : std_logic_vector (5 downto 0);
signal leftShiftStageSel5Dto4_uid112_fxpX_uid41_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel3Dto2_uid123_fxpX_uid41_fpCosPiTest_in : std_logic_vector (3 downto 0);
signal leftShiftStageSel3Dto2_uid123_fxpX_uid41_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid134_fxpX_uid41_fpCosPiTest_in : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid134_fxpX_uid41_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal zAddr_uid62_fpCosPiTest_in : std_logic_vector (34 downto 0);
signal zAddr_uid62_fpCosPiTest_b : std_logic_vector (6 downto 0);
signal zPPolyEval_uid63_fpCosPiTest_in : std_logic_vector (27 downto 0);
signal zPPolyEval_uid63_fpCosPiTest_b : std_logic_vector (15 downto 0);
signal rVStage_uid138_lzcZ_uid56_fpCosPiTest_in : std_logic_vector (34 downto 0);
signal rVStage_uid138_lzcZ_uid56_fpCosPiTest_b : std_logic_vector (31 downto 0);
signal vStage_uid141_lzcZ_uid56_fpCosPiTest_in : std_logic_vector (2 downto 0);
signal vStage_uid141_lzcZ_uid56_fpCosPiTest_b : std_logic_vector (2 downto 0);
signal X18dto0_uid176_alignedZ_uid57_fpCosPiTest_in : std_logic_vector (18 downto 0);
signal X18dto0_uid176_alignedZ_uid57_fpCosPiTest_b : std_logic_vector (18 downto 0);
signal leftShiftStage2Idx1_uid127_fxpX_uid41_fpCosPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage2Idx2_uid130_fxpX_uid41_fpCosPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage2Idx3_uid133_fxpX_uid41_fpCosPiTest_q : std_logic_vector (36 downto 0);
signal vCount_uid153_lzcZ_uid56_fpCosPiTest_a : std_logic_vector(7 downto 0);
signal vCount_uid153_lzcZ_uid56_fpCosPiTest_b : std_logic_vector(7 downto 0);
signal vCount_uid153_lzcZ_uid56_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid156_lzcZ_uid56_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid156_lzcZ_uid56_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal vCount_uid165_lzcZ_uid56_fpCosPiTest_a : std_logic_vector(1 downto 0);
signal vCount_uid165_lzcZ_uid56_fpCosPiTest_b : std_logic_vector(1 downto 0);
signal vCount_uid165_lzcZ_uid56_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid168_lzcZ_uid56_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid168_lzcZ_uid56_fpCosPiTest_q : std_logic_vector (1 downto 0);
signal leftShiftStage2Idx1_uid197_alignedZ_uid57_fpCosPiTest_q : std_logic_vector (34 downto 0);
signal leftShiftStage2Idx2_uid200_alignedZ_uid57_fpCosPiTest_q : std_logic_vector (34 downto 0);
signal leftShiftStage2Idx3_uid203_alignedZ_uid57_fpCosPiTest_q : std_logic_vector (34 downto 0);
signal fracRCompPreRnd_uid70_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal fracRCompPreRnd_uid70_fpCosPiTest_q : std_logic_vector (23 downto 0);
signal rndExpUpdate_uid72_uid73_fpCosPiTest_q : std_logic_vector (24 downto 0);
signal sumAHighB_uid214_sinPiZPolyEval_a : std_logic_vector(21 downto 0);
signal sumAHighB_uid214_sinPiZPolyEval_b : std_logic_vector(21 downto 0);
signal sumAHighB_uid214_sinPiZPolyEval_o : std_logic_vector (21 downto 0);
signal sumAHighB_uid214_sinPiZPolyEval_q : std_logic_vector (21 downto 0);
signal sumAHighB_uid220_sinPiZPolyEval_a : std_logic_vector(29 downto 0);
signal sumAHighB_uid220_sinPiZPolyEval_b : std_logic_vector(29 downto 0);
signal sumAHighB_uid220_sinPiZPolyEval_o : std_logic_vector (29 downto 0);
signal sumAHighB_uid220_sinPiZPolyEval_q : std_logic_vector (29 downto 0);
signal X20dto0_uid106_fxpX_uid41_fpCosPiTest_in : std_logic_vector (20 downto 0);
signal X20dto0_uid106_fxpX_uid41_fpCosPiTest_b : std_logic_vector (20 downto 0);
signal X4dto0_uid109_fxpX_uid41_fpCosPiTest_in : std_logic_vector (4 downto 0);
signal X4dto0_uid109_fxpX_uid41_fpCosPiTest_b : std_logic_vector (4 downto 0);
signal InvExc_N_uid31_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal InvExc_N_uid31_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal excRNaN_uid84_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal excRNaN_uid84_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal excRNaN_uid84_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal yT1_uid210_sinPiZPolyEval_in : std_logic_vector (15 downto 0);
signal yT1_uid210_sinPiZPolyEval_b : std_logic_vector (13 downto 0);
signal cStage_uid142_lzcZ_uid56_fpCosPiTest_q : std_logic_vector (31 downto 0);
signal leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest_q : std_logic_vector (36 downto 0);
signal rVStage_uid158_lzcZ_uid56_fpCosPiTest_in : std_logic_vector (7 downto 0);
signal rVStage_uid158_lzcZ_uid56_fpCosPiTest_b : std_logic_vector (3 downto 0);
signal vStage_uid160_lzcZ_uid56_fpCosPiTest_in : std_logic_vector (3 downto 0);
signal vStage_uid160_lzcZ_uid56_fpCosPiTest_b : std_logic_vector (3 downto 0);
signal rVStage_uid170_lzcZ_uid56_fpCosPiTest_in : std_logic_vector (1 downto 0);
signal rVStage_uid170_lzcZ_uid56_fpCosPiTest_b : std_logic_vector (0 downto 0);
signal leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest_q : std_logic_vector (34 downto 0);
signal expFracPreRnd_uid71_uid71_fpCosPiTest_q : std_logic_vector (31 downto 0);
signal expFracComp_uid74_fpCosPiTest_a : std_logic_vector(32 downto 0);
signal expFracComp_uid74_fpCosPiTest_b : std_logic_vector(32 downto 0);
signal expFracComp_uid74_fpCosPiTest_o : std_logic_vector (32 downto 0);
signal expFracComp_uid74_fpCosPiTest_q : std_logic_vector (32 downto 0);
signal s1_uid212_uid215_sinPiZPolyEval_q : std_logic_vector (22 downto 0);
signal s2_uid218_uid221_sinPiZPolyEval_q : std_logic_vector (31 downto 0);
signal leftShiftStage0Idx1_uid107_fxpX_uid41_fpCosPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage0Idx2_uid110_fxpX_uid41_fpCosPiTest_q : std_logic_vector (36 downto 0);
signal exc_R_uid34_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal exc_R_uid34_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal exc_R_uid34_fpCosPiTest_c : std_logic_vector(0 downto 0);
signal exc_R_uid34_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal rInfOrNaN_uid92_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal rInfOrNaN_uid92_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal rInfOrNaN_uid92_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal FxpX36_uid42_fpCosPiTest_in : std_logic_vector (36 downto 0);
signal FxpX36_uid42_fpCosPiTest_b : std_logic_vector (0 downto 0);
signal fxpXFrac_uid43_fpCosPiTest_in : std_logic_vector (35 downto 0);
signal fxpXFrac_uid43_fpCosPiTest_b : std_logic_vector (35 downto 0);
signal vCount_uid171_lzcZ_uid56_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal vCount_uid171_lzcZ_uid56_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal vCount_uid171_lzcZ_uid56_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal alignedZLow_uid58_fpCosPiTest_in : std_logic_vector (34 downto 0);
signal alignedZLow_uid58_fpCosPiTest_b : std_logic_vector (23 downto 0);
signal fracRComp_uid75_fpCosPiTest_in : std_logic_vector (23 downto 0);
signal fracRComp_uid75_fpCosPiTest_b : std_logic_vector (22 downto 0);
signal expRComp_uid76_fpCosPiTest_in : std_logic_vector (31 downto 0);
signal expRComp_uid76_fpCosPiTest_b : std_logic_vector (7 downto 0);
signal fxpSinRes_uid65_fpCosPiTest_in : std_logic_vector (29 downto 0);
signal fxpSinRes_uid65_fpCosPiTest_b : std_logic_vector (24 downto 0);
signal leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_q : std_logic_vector (36 downto 0);
signal FxpXFrac35_uid44_fpCosPiTest_in : std_logic_vector (35 downto 0);
signal FxpXFrac35_uid44_fpCosPiTest_b : std_logic_vector (0 downto 0);
signal r_uid172_lzcZ_uid56_fpCosPiTest_q : std_logic_vector (5 downto 0);
signal LeftShiftStage032dto0_uid115_fxpX_uid41_fpCosPiTest_in : std_logic_vector (32 downto 0);
signal LeftShiftStage032dto0_uid115_fxpX_uid41_fpCosPiTest_b : std_logic_vector (32 downto 0);
signal LeftShiftStage028dto0_uid118_fxpX_uid41_fpCosPiTest_in : std_logic_vector (28 downto 0);
signal LeftShiftStage028dto0_uid118_fxpX_uid41_fpCosPiTest_b : std_logic_vector (28 downto 0);
signal LeftShiftStage024dto0_uid121_fxpX_uid41_fpCosPiTest_in : std_logic_vector (24 downto 0);
signal LeftShiftStage024dto0_uid121_fxpX_uid41_fpCosPiTest_b : std_logic_vector (24 downto 0);
signal xParityXorHalfParity_uid96_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal xParityXorHalfParity_uid96_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal xParityXorHalfParity_uid96_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal leftShiftStageSel5Dto4_uid182_alignedZ_uid57_fpCosPiTest_in : std_logic_vector (5 downto 0);
signal leftShiftStageSel5Dto4_uid182_alignedZ_uid57_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel3Dto2_uid193_alignedZ_uid57_fpCosPiTest_in : std_logic_vector (3 downto 0);
signal leftShiftStageSel3Dto2_uid193_alignedZ_uid57_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid204_alignedZ_uid57_fpCosPiTest_in : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid204_alignedZ_uid57_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStage1Idx1_uid116_fxpX_uid41_fpCosPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage1Idx2_uid119_fxpX_uid41_fpCosPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage1Idx3_uid122_fxpX_uid41_fpCosPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_q : std_logic_vector (34 downto 0);
signal LeftShiftStage030dto0_uid185_alignedZ_uid57_fpCosPiTest_in : std_logic_vector (30 downto 0);
signal LeftShiftStage030dto0_uid185_alignedZ_uid57_fpCosPiTest_b : std_logic_vector (30 downto 0);
signal LeftShiftStage026dto0_uid188_alignedZ_uid57_fpCosPiTest_in : std_logic_vector (26 downto 0);
signal LeftShiftStage026dto0_uid188_alignedZ_uid57_fpCosPiTest_b : std_logic_vector (26 downto 0);
signal LeftShiftStage022dto0_uid191_alignedZ_uid57_fpCosPiTest_in : std_logic_vector (22 downto 0);
signal LeftShiftStage022dto0_uid191_alignedZ_uid57_fpCosPiTest_b : std_logic_vector (22 downto 0);
signal leftShiftStage1Idx1_uid186_alignedZ_uid57_fpCosPiTest_q : std_logic_vector (34 downto 0);
signal leftShiftStage1Idx2_uid189_alignedZ_uid57_fpCosPiTest_q : std_logic_vector (34 downto 0);
signal leftShiftStage1Idx3_uid192_alignedZ_uid57_fpCosPiTest_q : std_logic_vector (34 downto 0);
begin
--xIn(GPIN,3)@0
--LeftShiftStage133dto0_uid132_fxpX_uid41_fpCosPiTest(BITSELECT,131)@1
LeftShiftStage133dto0_uid132_fxpX_uid41_fpCosPiTest_in <= leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_q(33 downto 0);
LeftShiftStage133dto0_uid132_fxpX_uid41_fpCosPiTest_b <= LeftShiftStage133dto0_uid132_fxpX_uid41_fpCosPiTest_in(33 downto 0);
--leftShiftStage2Idx3Pad3_uid131_fxpX_uid41_fpCosPiTest(CONSTANT,130)
leftShiftStage2Idx3Pad3_uid131_fxpX_uid41_fpCosPiTest_q <= "000";
--leftShiftStage2Idx3_uid133_fxpX_uid41_fpCosPiTest(BITJOIN,132)@1
leftShiftStage2Idx3_uid133_fxpX_uid41_fpCosPiTest_q <= LeftShiftStage133dto0_uid132_fxpX_uid41_fpCosPiTest_b & leftShiftStage2Idx3Pad3_uid131_fxpX_uid41_fpCosPiTest_q;
--LeftShiftStage134dto0_uid129_fxpX_uid41_fpCosPiTest(BITSELECT,128)@1
LeftShiftStage134dto0_uid129_fxpX_uid41_fpCosPiTest_in <= leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_q(34 downto 0);
LeftShiftStage134dto0_uid129_fxpX_uid41_fpCosPiTest_b <= LeftShiftStage134dto0_uid129_fxpX_uid41_fpCosPiTest_in(34 downto 0);
--leftShiftStage2Idx2Pad2_uid128_fxpX_uid41_fpCosPiTest(CONSTANT,127)
leftShiftStage2Idx2Pad2_uid128_fxpX_uid41_fpCosPiTest_q <= "00";
--leftShiftStage2Idx2_uid130_fxpX_uid41_fpCosPiTest(BITJOIN,129)@1
leftShiftStage2Idx2_uid130_fxpX_uid41_fpCosPiTest_q <= LeftShiftStage134dto0_uid129_fxpX_uid41_fpCosPiTest_b & leftShiftStage2Idx2Pad2_uid128_fxpX_uid41_fpCosPiTest_q;
--LeftShiftStage135dto0_uid126_fxpX_uid41_fpCosPiTest(BITSELECT,125)@1
LeftShiftStage135dto0_uid126_fxpX_uid41_fpCosPiTest_in <= leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_q(35 downto 0);
LeftShiftStage135dto0_uid126_fxpX_uid41_fpCosPiTest_b <= LeftShiftStage135dto0_uid126_fxpX_uid41_fpCosPiTest_in(35 downto 0);
--GND(CONSTANT,0)
GND_q <= "0";
--leftShiftStage2Idx1_uid127_fxpX_uid41_fpCosPiTest(BITJOIN,126)@1
leftShiftStage2Idx1_uid127_fxpX_uid41_fpCosPiTest_q <= LeftShiftStage135dto0_uid126_fxpX_uid41_fpCosPiTest_b & GND_q;
--leftShiftStage0Idx3_uid111_fxpX_uid41_fpCosPiTest(CONSTANT,110)
leftShiftStage0Idx3_uid111_fxpX_uid41_fpCosPiTest_q <= "0000000000000000000000000000000000000";
--X4dto0_uid109_fxpX_uid41_fpCosPiTest(BITSELECT,108)@0
X4dto0_uid109_fxpX_uid41_fpCosPiTest_in <= oFracXExt_uid39_fpCosPiTest_q(4 downto 0);
X4dto0_uid109_fxpX_uid41_fpCosPiTest_b <= X4dto0_uid109_fxpX_uid41_fpCosPiTest_in(4 downto 0);
--leftShiftStage0Idx2Pad32_uid108_fxpX_uid41_fpCosPiTest(CONSTANT,107)
leftShiftStage0Idx2Pad32_uid108_fxpX_uid41_fpCosPiTest_q <= "00000000000000000000000000000000";
--leftShiftStage0Idx2_uid110_fxpX_uid41_fpCosPiTest(BITJOIN,109)@0
leftShiftStage0Idx2_uid110_fxpX_uid41_fpCosPiTest_q <= X4dto0_uid109_fxpX_uid41_fpCosPiTest_b & leftShiftStage0Idx2Pad32_uid108_fxpX_uid41_fpCosPiTest_q;
--X20dto0_uid106_fxpX_uid41_fpCosPiTest(BITSELECT,105)@0
X20dto0_uid106_fxpX_uid41_fpCosPiTest_in <= oFracXExt_uid39_fpCosPiTest_q(20 downto 0);
X20dto0_uid106_fxpX_uid41_fpCosPiTest_b <= X20dto0_uid106_fxpX_uid41_fpCosPiTest_in(20 downto 0);
--leftShiftStage0Idx1Pad16_uid105_fxpX_uid41_fpCosPiTest(CONSTANT,104)
leftShiftStage0Idx1Pad16_uid105_fxpX_uid41_fpCosPiTest_q <= "0000000000000000";
--leftShiftStage0Idx1_uid107_fxpX_uid41_fpCosPiTest(BITJOIN,106)@0
leftShiftStage0Idx1_uid107_fxpX_uid41_fpCosPiTest_q <= X20dto0_uid106_fxpX_uid41_fpCosPiTest_b & leftShiftStage0Idx1Pad16_uid105_fxpX_uid41_fpCosPiTest_q;
--cst01pWShift_uid14_fpCosPiTest(CONSTANT,13)
cst01pWShift_uid14_fpCosPiTest_q <= "0000000000000";
--VCC(CONSTANT,1)
VCC_q <= "1";
--fracX_uid7_fpCosPiTest(BITSELECT,6)@0
fracX_uid7_fpCosPiTest_in <= a(22 downto 0);
fracX_uid7_fpCosPiTest_b <= fracX_uid7_fpCosPiTest_in(22 downto 0);
--oFracX_uid37_uid37_fpCosPiTest(BITJOIN,36)@0
oFracX_uid37_uid37_fpCosPiTest_q <= VCC_q & fracX_uid7_fpCosPiTest_b;
--oFracXExt_uid39_fpCosPiTest(BITJOIN,38)@0
oFracXExt_uid39_fpCosPiTest_q <= cst01pWShift_uid14_fpCosPiTest_q & oFracX_uid37_uid37_fpCosPiTest_q;
--biasMwShiftMO_uid13_fpCosPiTest(CONSTANT,12)
biasMwShiftMO_uid13_fpCosPiTest_q <= "01110010";
--expX_uid6_fpCosPiTest(BITSELECT,5)@0
expX_uid6_fpCosPiTest_in <= a(30 downto 0);
expX_uid6_fpCosPiTest_b <= expX_uid6_fpCosPiTest_in(30 downto 23);
--shiftValFxPX_uid38_fpCosPiTest(SUB,37)@0
shiftValFxPX_uid38_fpCosPiTest_a <= STD_LOGIC_VECTOR("0" & expX_uid6_fpCosPiTest_b);
shiftValFxPX_uid38_fpCosPiTest_b <= STD_LOGIC_VECTOR("0" & biasMwShiftMO_uid13_fpCosPiTest_q);
shiftValFxPX_uid38_fpCosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(shiftValFxPX_uid38_fpCosPiTest_a) - UNSIGNED(shiftValFxPX_uid38_fpCosPiTest_b));
shiftValFxPX_uid38_fpCosPiTest_q <= shiftValFxPX_uid38_fpCosPiTest_o(8 downto 0);
--fxpShifterBits_uid40_fpCosPiTest(BITSELECT,39)@0
fxpShifterBits_uid40_fpCosPiTest_in <= shiftValFxPX_uid38_fpCosPiTest_q(5 downto 0);
fxpShifterBits_uid40_fpCosPiTest_b <= fxpShifterBits_uid40_fpCosPiTest_in(5 downto 0);
--leftShiftStageSel5Dto4_uid112_fxpX_uid41_fpCosPiTest(BITSELECT,111)@0
leftShiftStageSel5Dto4_uid112_fxpX_uid41_fpCosPiTest_in <= fxpShifterBits_uid40_fpCosPiTest_b;
leftShiftStageSel5Dto4_uid112_fxpX_uid41_fpCosPiTest_b <= leftShiftStageSel5Dto4_uid112_fxpX_uid41_fpCosPiTest_in(5 downto 4);
--leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest(MUX,112)@0
leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_s <= leftShiftStageSel5Dto4_uid112_fxpX_uid41_fpCosPiTest_b;
leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest: PROCESS (leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_s, en, oFracXExt_uid39_fpCosPiTest_q, leftShiftStage0Idx1_uid107_fxpX_uid41_fpCosPiTest_q, leftShiftStage0Idx2_uid110_fxpX_uid41_fpCosPiTest_q, leftShiftStage0Idx3_uid111_fxpX_uid41_fpCosPiTest_q)
BEGIN
CASE leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_s IS
WHEN "00" => leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_q <= oFracXExt_uid39_fpCosPiTest_q;
WHEN "01" => leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_q <= leftShiftStage0Idx1_uid107_fxpX_uid41_fpCosPiTest_q;
WHEN "10" => leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_q <= leftShiftStage0Idx2_uid110_fxpX_uid41_fpCosPiTest_q;
WHEN "11" => leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_q <= leftShiftStage0Idx3_uid111_fxpX_uid41_fpCosPiTest_q;
WHEN OTHERS => leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage024dto0_uid121_fxpX_uid41_fpCosPiTest(BITSELECT,120)@0
LeftShiftStage024dto0_uid121_fxpX_uid41_fpCosPiTest_in <= leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_q(24 downto 0);
LeftShiftStage024dto0_uid121_fxpX_uid41_fpCosPiTest_b <= LeftShiftStage024dto0_uid121_fxpX_uid41_fpCosPiTest_in(24 downto 0);
--leftShiftStage1Idx3Pad12_uid120_fxpX_uid41_fpCosPiTest(CONSTANT,119)
leftShiftStage1Idx3Pad12_uid120_fxpX_uid41_fpCosPiTest_q <= "000000000000";
--leftShiftStage1Idx3_uid122_fxpX_uid41_fpCosPiTest(BITJOIN,121)@0
leftShiftStage1Idx3_uid122_fxpX_uid41_fpCosPiTest_q <= LeftShiftStage024dto0_uid121_fxpX_uid41_fpCosPiTest_b & leftShiftStage1Idx3Pad12_uid120_fxpX_uid41_fpCosPiTest_q;
--reg_leftShiftStage1Idx3_uid122_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_5(REG,235)@0
reg_leftShiftStage1Idx3_uid122_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx3_uid122_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_5_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx3_uid122_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_5_q <= leftShiftStage1Idx3_uid122_fxpX_uid41_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage028dto0_uid118_fxpX_uid41_fpCosPiTest(BITSELECT,117)@0
LeftShiftStage028dto0_uid118_fxpX_uid41_fpCosPiTest_in <= leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_q(28 downto 0);
LeftShiftStage028dto0_uid118_fxpX_uid41_fpCosPiTest_b <= LeftShiftStage028dto0_uid118_fxpX_uid41_fpCosPiTest_in(28 downto 0);
--cstAllZWE_uid21_fpCosPiTest(CONSTANT,20)
cstAllZWE_uid21_fpCosPiTest_q <= "00000000";
--leftShiftStage1Idx2_uid119_fxpX_uid41_fpCosPiTest(BITJOIN,118)@0
leftShiftStage1Idx2_uid119_fxpX_uid41_fpCosPiTest_q <= LeftShiftStage028dto0_uid118_fxpX_uid41_fpCosPiTest_b & cstAllZWE_uid21_fpCosPiTest_q;
--reg_leftShiftStage1Idx2_uid119_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_4(REG,234)@0
reg_leftShiftStage1Idx2_uid119_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx2_uid119_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_4_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx2_uid119_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_4_q <= leftShiftStage1Idx2_uid119_fxpX_uid41_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage032dto0_uid115_fxpX_uid41_fpCosPiTest(BITSELECT,114)@0
LeftShiftStage032dto0_uid115_fxpX_uid41_fpCosPiTest_in <= leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_q(32 downto 0);
LeftShiftStage032dto0_uid115_fxpX_uid41_fpCosPiTest_b <= LeftShiftStage032dto0_uid115_fxpX_uid41_fpCosPiTest_in(32 downto 0);
--leftShiftStage1Idx1Pad4_uid114_fxpX_uid41_fpCosPiTest(CONSTANT,113)
leftShiftStage1Idx1Pad4_uid114_fxpX_uid41_fpCosPiTest_q <= "0000";
--leftShiftStage1Idx1_uid116_fxpX_uid41_fpCosPiTest(BITJOIN,115)@0
leftShiftStage1Idx1_uid116_fxpX_uid41_fpCosPiTest_q <= LeftShiftStage032dto0_uid115_fxpX_uid41_fpCosPiTest_b & leftShiftStage1Idx1Pad4_uid114_fxpX_uid41_fpCosPiTest_q;
--reg_leftShiftStage1Idx1_uid116_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_3(REG,233)@0
reg_leftShiftStage1Idx1_uid116_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx1_uid116_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_3_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx1_uid116_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_3_q <= leftShiftStage1Idx1_uid116_fxpX_uid41_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--reg_leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_2(REG,232)@0
reg_leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_2_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_2_q <= leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel3Dto2_uid123_fxpX_uid41_fpCosPiTest(BITSELECT,122)@0
leftShiftStageSel3Dto2_uid123_fxpX_uid41_fpCosPiTest_in <= fxpShifterBits_uid40_fpCosPiTest_b(3 downto 0);
leftShiftStageSel3Dto2_uid123_fxpX_uid41_fpCosPiTest_b <= leftShiftStageSel3Dto2_uid123_fxpX_uid41_fpCosPiTest_in(3 downto 2);
--reg_leftShiftStageSel3Dto2_uid123_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_1(REG,231)@0
reg_leftShiftStageSel3Dto2_uid123_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel3Dto2_uid123_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel3Dto2_uid123_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_1_q <= leftShiftStageSel3Dto2_uid123_fxpX_uid41_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest(MUX,123)@1
leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_s <= reg_leftShiftStageSel3Dto2_uid123_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_1_q;
leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest: PROCESS (leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_s, en, reg_leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_2_q, reg_leftShiftStage1Idx1_uid116_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_3_q, reg_leftShiftStage1Idx2_uid119_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_4_q, reg_leftShiftStage1Idx3_uid122_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_5_q)
BEGIN
CASE leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_s IS
WHEN "00" => leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_q <= reg_leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_2_q;
WHEN "01" => leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_q <= reg_leftShiftStage1Idx1_uid116_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_3_q;
WHEN "10" => leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_q <= reg_leftShiftStage1Idx2_uid119_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_4_q;
WHEN "11" => leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_q <= reg_leftShiftStage1Idx3_uid122_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_5_q;
WHEN OTHERS => leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--leftShiftStageSel1Dto0_uid134_fxpX_uid41_fpCosPiTest(BITSELECT,133)@0
leftShiftStageSel1Dto0_uid134_fxpX_uid41_fpCosPiTest_in <= fxpShifterBits_uid40_fpCosPiTest_b(1 downto 0);
leftShiftStageSel1Dto0_uid134_fxpX_uid41_fpCosPiTest_b <= leftShiftStageSel1Dto0_uid134_fxpX_uid41_fpCosPiTest_in(1 downto 0);
--reg_leftShiftStageSel1Dto0_uid134_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest_1(REG,236)@0
reg_leftShiftStageSel1Dto0_uid134_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel1Dto0_uid134_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel1Dto0_uid134_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest_1_q <= leftShiftStageSel1Dto0_uid134_fxpX_uid41_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest(MUX,134)@1
leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest_s <= reg_leftShiftStageSel1Dto0_uid134_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest_1_q;
leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest: PROCESS (leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest_s, en, leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_q, leftShiftStage2Idx1_uid127_fxpX_uid41_fpCosPiTest_q, leftShiftStage2Idx2_uid130_fxpX_uid41_fpCosPiTest_q, leftShiftStage2Idx3_uid133_fxpX_uid41_fpCosPiTest_q)
BEGIN
CASE leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest_s IS
WHEN "00" => leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest_q <= leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_q;
WHEN "01" => leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest_q <= leftShiftStage2Idx1_uid127_fxpX_uid41_fpCosPiTest_q;
WHEN "10" => leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest_q <= leftShiftStage2Idx2_uid130_fxpX_uid41_fpCosPiTest_q;
WHEN "11" => leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest_q <= leftShiftStage2Idx3_uid133_fxpX_uid41_fpCosPiTest_q;
WHEN OTHERS => leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--fxpXFrac_uid43_fpCosPiTest(BITSELECT,42)@1
fxpXFrac_uid43_fpCosPiTest_in <= leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest_q(35 downto 0);
fxpXFrac_uid43_fpCosPiTest_b <= fxpXFrac_uid43_fpCosPiTest_in(35 downto 0);
--FxpXFrac35_uid44_fpCosPiTest(BITSELECT,43)@1
FxpXFrac35_uid44_fpCosPiTest_in <= fxpXFrac_uid43_fpCosPiTest_b;
FxpXFrac35_uid44_fpCosPiTest_b <= FxpXFrac35_uid44_fpCosPiTest_in(35 downto 35);
--FxpX36_uid42_fpCosPiTest(BITSELECT,41)@1
FxpX36_uid42_fpCosPiTest_in <= leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest_q;
FxpX36_uid42_fpCosPiTest_b <= FxpX36_uid42_fpCosPiTest_in(36 downto 36);
--xParityXorHalfParity_uid96_fpCosPiTest(LOGICAL,95)@1
xParityXorHalfParity_uid96_fpCosPiTest_a <= FxpX36_uid42_fpCosPiTest_b;
xParityXorHalfParity_uid96_fpCosPiTest_b <= FxpXFrac35_uid44_fpCosPiTest_b;
xParityXorHalfParity_uid96_fpCosPiTest_q <= xParityXorHalfParity_uid96_fpCosPiTest_a xor xParityXorHalfParity_uid96_fpCosPiTest_b;
--ld_xParityXorHalfParity_uid96_fpCosPiTest_q_to_signRComp_uid99_fpCosPiTest_c(DELAY,369)@1
ld_xParityXorHalfParity_uid96_fpCosPiTest_q_to_signRComp_uid99_fpCosPiTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => xParityXorHalfParity_uid96_fpCosPiTest_q, xout => ld_xParityXorHalfParity_uid96_fpCosPiTest_q_to_signRComp_uid99_fpCosPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--cstBiasPwF_uid12_fpCosPiTest(CONSTANT,11)
cstBiasPwF_uid12_fpCosPiTest_q <= "10010110";
--xEvenInt_uid35_fpCosPiTest(COMPARE,34)@0
xEvenInt_uid35_fpCosPiTest_cin <= GND_q;
xEvenInt_uid35_fpCosPiTest_a <= STD_LOGIC_VECTOR("00" & cstBiasPwF_uid12_fpCosPiTest_q) & '0';
xEvenInt_uid35_fpCosPiTest_b <= STD_LOGIC_VECTOR("00" & expX_uid6_fpCosPiTest_b) & xEvenInt_uid35_fpCosPiTest_cin(0);
xEvenInt_uid35_fpCosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(xEvenInt_uid35_fpCosPiTest_a) - UNSIGNED(xEvenInt_uid35_fpCosPiTest_b));
xEvenInt_uid35_fpCosPiTest_c(0) <= xEvenInt_uid35_fpCosPiTest_o(10);
--ld_xEvenInt_uid35_fpCosPiTest_c_to_evenIntCosNotOneFZ_uid79_fpCosPiTest_a(DELAY,335)@0
ld_xEvenInt_uid35_fpCosPiTest_c_to_evenIntCosNotOneFZ_uid79_fpCosPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => xEvenInt_uid35_fpCosPiTest_c, xout => ld_xEvenInt_uid35_fpCosPiTest_c_to_evenIntCosNotOneFZ_uid79_fpCosPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--InvXEvenInt_uid81_fpCosPiTest(LOGICAL,80)@2
InvXEvenInt_uid81_fpCosPiTest_a <= ld_xEvenInt_uid35_fpCosPiTest_c_to_evenIntCosNotOneFZ_uid79_fpCosPiTest_a_q;
InvXEvenInt_uid81_fpCosPiTest_q <= not InvXEvenInt_uid81_fpCosPiTest_a;
--cosXIsOne_uid36_fpCosPiTest(COMPARE,35)@0
cosXIsOne_uid36_fpCosPiTest_cin <= GND_q;
cosXIsOne_uid36_fpCosPiTest_a <= STD_LOGIC_VECTOR("00" & expX_uid6_fpCosPiTest_b) & '0';
cosXIsOne_uid36_fpCosPiTest_b <= STD_LOGIC_VECTOR("00" & biasMwShiftMO_uid13_fpCosPiTest_q) & cosXIsOne_uid36_fpCosPiTest_cin(0);
cosXIsOne_uid36_fpCosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(cosXIsOne_uid36_fpCosPiTest_a) - UNSIGNED(cosXIsOne_uid36_fpCosPiTest_b));
cosXIsOne_uid36_fpCosPiTest_c(0) <= cosXIsOne_uid36_fpCosPiTest_o(10);
--ld_cosXIsOne_uid36_fpCosPiTest_c_to_InvCosXIsOne_uid77_fpCosPiTest_a(DELAY,332)@0
ld_cosXIsOne_uid36_fpCosPiTest_c_to_InvCosXIsOne_uid77_fpCosPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => cosXIsOne_uid36_fpCosPiTest_c, xout => ld_cosXIsOne_uid36_fpCosPiTest_c_to_InvCosXIsOne_uid77_fpCosPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--InvCosXIsOne_uid77_fpCosPiTest(LOGICAL,76)@2
InvCosXIsOne_uid77_fpCosPiTest_a <= ld_cosXIsOne_uid36_fpCosPiTest_c_to_InvCosXIsOne_uid77_fpCosPiTest_a_q;
InvCosXIsOne_uid77_fpCosPiTest_q <= not InvCosXIsOne_uid77_fpCosPiTest_a;
--signRComp_uid99_fpCosPiTest(LOGICAL,98)@2
signRComp_uid99_fpCosPiTest_a <= InvCosXIsOne_uid77_fpCosPiTest_q;
signRComp_uid99_fpCosPiTest_b <= InvXEvenInt_uid81_fpCosPiTest_q;
signRComp_uid99_fpCosPiTest_c <= ld_xParityXorHalfParity_uid96_fpCosPiTest_q_to_signRComp_uid99_fpCosPiTest_c_q;
signRComp_uid99_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
signRComp_uid99_fpCosPiTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1' AND en = "1") THEN
signRComp_uid99_fpCosPiTest_q <= signRComp_uid99_fpCosPiTest_a and signRComp_uid99_fpCosPiTest_b and signRComp_uid99_fpCosPiTest_c;
END IF;
END PROCESS;
--cstZwSwF_uid15_fpCosPiTest(CONSTANT,14)
cstZwSwF_uid15_fpCosPiTest_q <= "00000000000000000000000000000000000";
--cstHalfwSwFP1_uid18_fpCosPiTest(BITJOIN,17)@2
cstHalfwSwFP1_uid18_fpCosPiTest_q <= VCC_q & cstZwSwF_uid15_fpCosPiTest_q;
--reg_fxpXFrac_uid43_fpCosPiTest_0_to_fxpXFracZero_uid45_fpCosPiTest_1(REG,237)@1
reg_fxpXFrac_uid43_fpCosPiTest_0_to_fxpXFracZero_uid45_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fxpXFrac_uid43_fpCosPiTest_0_to_fxpXFracZero_uid45_fpCosPiTest_1_q <= "000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fxpXFrac_uid43_fpCosPiTest_0_to_fxpXFracZero_uid45_fpCosPiTest_1_q <= fxpXFrac_uid43_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--fxpXFracHalf_uid46_fpCosPiTest(LOGICAL,45)@2
fxpXFracHalf_uid46_fpCosPiTest_a <= reg_fxpXFrac_uid43_fpCosPiTest_0_to_fxpXFracZero_uid45_fpCosPiTest_1_q;
fxpXFracHalf_uid46_fpCosPiTest_b <= cstHalfwSwFP1_uid18_fpCosPiTest_q;
fxpXFracHalf_uid46_fpCosPiTest_q <= "1" when fxpXFracHalf_uid46_fpCosPiTest_a = fxpXFracHalf_uid46_fpCosPiTest_b else "0";
--ld_fxpXFracHalf_uid46_fpCosPiTest_q_to_InvFxpXFracHalf_uid100_fpCosPiTest_a(DELAY,370)@2
ld_fxpXFracHalf_uid46_fpCosPiTest_q_to_InvFxpXFracHalf_uid100_fpCosPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => fxpXFracHalf_uid46_fpCosPiTest_q, xout => ld_fxpXFracHalf_uid46_fpCosPiTest_q_to_InvFxpXFracHalf_uid100_fpCosPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--InvFxpXFracHalf_uid100_fpCosPiTest(LOGICAL,99)@3
InvFxpXFracHalf_uid100_fpCosPiTest_a <= ld_fxpXFracHalf_uid46_fpCosPiTest_q_to_InvFxpXFracHalf_uid100_fpCosPiTest_a_q;
InvFxpXFracHalf_uid100_fpCosPiTest_q <= not InvFxpXFracHalf_uid100_fpCosPiTest_a;
--signR_uid101_fpCosPiTest(LOGICAL,100)@3
signR_uid101_fpCosPiTest_a <= InvFxpXFracHalf_uid100_fpCosPiTest_q;
signR_uid101_fpCosPiTest_b <= signRComp_uid99_fpCosPiTest_q;
signR_uid101_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
signR_uid101_fpCosPiTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1' AND en = "1") THEN
signR_uid101_fpCosPiTest_q <= signR_uid101_fpCosPiTest_a and signR_uid101_fpCosPiTest_b;
END IF;
END PROCESS;
--ld_signR_uid101_fpCosPiTest_q_to_R_uid102_fpCosPiTest_c(DELAY,375)@4
ld_signR_uid101_fpCosPiTest_q_to_R_uid102_fpCosPiTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 13 )
PORT MAP ( xin => signR_uid101_fpCosPiTest_q, xout => ld_signR_uid101_fpCosPiTest_q_to_R_uid102_fpCosPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--cstBias_uid10_fpCosPiTest(CONSTANT,9)
cstBias_uid10_fpCosPiTest_q <= "01111111";
--cstAllOWE_uid8_fpCosPiTest(CONSTANT,7)
cstAllOWE_uid8_fpCosPiTest_q <= "11111111";
--pad_o_uid16_uid47_fpCosPiTest(BITJOIN,46)@1
pad_o_uid16_uid47_fpCosPiTest_q <= VCC_q & STD_LOGIC_VECTOR((35 downto 1 => GND_q(0)) & GND_q);
--reg_pad_o_uid16_uid47_fpCosPiTest_0_to_oMFxpXFrac_uid47_fpCosPiTest_0(REG,244)@1
reg_pad_o_uid16_uid47_fpCosPiTest_0_to_oMFxpXFrac_uid47_fpCosPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_o_uid16_uid47_fpCosPiTest_0_to_oMFxpXFrac_uid47_fpCosPiTest_0_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_o_uid16_uid47_fpCosPiTest_0_to_oMFxpXFrac_uid47_fpCosPiTest_0_q <= pad_o_uid16_uid47_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--oMFxpXFrac_uid47_fpCosPiTest(SUB,47)@2
oMFxpXFrac_uid47_fpCosPiTest_a <= STD_LOGIC_VECTOR("0" & reg_pad_o_uid16_uid47_fpCosPiTest_0_to_oMFxpXFrac_uid47_fpCosPiTest_0_q);
oMFxpXFrac_uid47_fpCosPiTest_b <= STD_LOGIC_VECTOR("00" & reg_fxpXFrac_uid43_fpCosPiTest_0_to_fxpXFracZero_uid45_fpCosPiTest_1_q);
oMFxpXFrac_uid47_fpCosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(oMFxpXFrac_uid47_fpCosPiTest_a) - UNSIGNED(oMFxpXFrac_uid47_fpCosPiTest_b));
oMFxpXFrac_uid47_fpCosPiTest_q <= oMFxpXFrac_uid47_fpCosPiTest_o(37 downto 0);
--oMFxpXFrac_uid49_fpCosPiTest(BITSELECT,48)@2
oMFxpXFrac_uid49_fpCosPiTest_in <= oMFxpXFrac_uid47_fpCosPiTest_q(35 downto 0);
oMFxpXFrac_uid49_fpCosPiTest_b <= oMFxpXFrac_uid49_fpCosPiTest_in(35 downto 0);
--ld_fxpXFrac_uid43_fpCosPiTest_b_to_rangeReducedFxPX_uid51_fpCosPiTest_c(DELAY,308)@1
ld_fxpXFrac_uid43_fpCosPiTest_b_to_rangeReducedFxPX_uid51_fpCosPiTest_c : dspba_delay
GENERIC MAP ( width => 36, depth => 1 )
PORT MAP ( xin => fxpXFrac_uid43_fpCosPiTest_b, xout => ld_fxpXFrac_uid43_fpCosPiTest_b_to_rangeReducedFxPX_uid51_fpCosPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--ld_FxpXFrac35_uid44_fpCosPiTest_b_to_rangeReducedFxPX_uid51_fpCosPiTest_b(DELAY,307)@1
ld_FxpXFrac35_uid44_fpCosPiTest_b_to_rangeReducedFxPX_uid51_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => FxpXFrac35_uid44_fpCosPiTest_b, xout => ld_FxpXFrac35_uid44_fpCosPiTest_b_to_rangeReducedFxPX_uid51_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--rangeReducedFxPX_uid51_fpCosPiTest(MUX,50)@2
rangeReducedFxPX_uid51_fpCosPiTest_s <= ld_FxpXFrac35_uid44_fpCosPiTest_b_to_rangeReducedFxPX_uid51_fpCosPiTest_b_q;
rangeReducedFxPX_uid51_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
rangeReducedFxPX_uid51_fpCosPiTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE rangeReducedFxPX_uid51_fpCosPiTest_s IS
WHEN "0" => rangeReducedFxPX_uid51_fpCosPiTest_q <= ld_fxpXFrac_uid43_fpCosPiTest_b_to_rangeReducedFxPX_uid51_fpCosPiTest_c_q;
WHEN "1" => rangeReducedFxPX_uid51_fpCosPiTest_q <= oMFxpXFrac_uid49_fpCosPiTest_b;
WHEN OTHERS => rangeReducedFxPX_uid51_fpCosPiTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--pad_half_uid17_uid52_fpCosPiTest(BITJOIN,51)@2
pad_half_uid17_uid52_fpCosPiTest_q <= VCC_q & STD_LOGIC_VECTOR((34 downto 1 => GND_q(0)) & GND_q);
--reg_pad_half_uid17_uid52_fpCosPiTest_0_to_z_halfMRRFxPXE_uid52_fpCosPiTest_0(REG,246)@2
reg_pad_half_uid17_uid52_fpCosPiTest_0_to_z_halfMRRFxPXE_uid52_fpCosPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_half_uid17_uid52_fpCosPiTest_0_to_z_halfMRRFxPXE_uid52_fpCosPiTest_0_q <= "000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_half_uid17_uid52_fpCosPiTest_0_to_z_halfMRRFxPXE_uid52_fpCosPiTest_0_q <= pad_half_uid17_uid52_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--z_halfMRRFxPXE_uid52_fpCosPiTest(SUB,52)@3
z_halfMRRFxPXE_uid52_fpCosPiTest_a <= STD_LOGIC_VECTOR("0" & reg_pad_half_uid17_uid52_fpCosPiTest_0_to_z_halfMRRFxPXE_uid52_fpCosPiTest_0_q);
z_halfMRRFxPXE_uid52_fpCosPiTest_b <= STD_LOGIC_VECTOR("0" & rangeReducedFxPX_uid51_fpCosPiTest_q);
z_halfMRRFxPXE_uid52_fpCosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(z_halfMRRFxPXE_uid52_fpCosPiTest_a) - UNSIGNED(z_halfMRRFxPXE_uid52_fpCosPiTest_b));
z_halfMRRFxPXE_uid52_fpCosPiTest_q <= z_halfMRRFxPXE_uid52_fpCosPiTest_o(36 downto 0);
--z_uid54_fpCosPiTest(BITSELECT,53)@3
z_uid54_fpCosPiTest_in <= z_halfMRRFxPXE_uid52_fpCosPiTest_q(34 downto 0);
z_uid54_fpCosPiTest_b <= z_uid54_fpCosPiTest_in(34 downto 0);
--zAddr_uid62_fpCosPiTest(BITSELECT,61)@3
zAddr_uid62_fpCosPiTest_in <= z_uid54_fpCosPiTest_b;
zAddr_uid62_fpCosPiTest_b <= zAddr_uid62_fpCosPiTest_in(34 downto 28);
--reg_zAddr_uid62_fpCosPiTest_0_to_memoryC2_uid209_sinPiZTableGenerator_0(REG,263)@3
reg_zAddr_uid62_fpCosPiTest_0_to_memoryC2_uid209_sinPiZTableGenerator_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_zAddr_uid62_fpCosPiTest_0_to_memoryC2_uid209_sinPiZTableGenerator_0_q <= "0000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_zAddr_uid62_fpCosPiTest_0_to_memoryC2_uid209_sinPiZTableGenerator_0_q <= zAddr_uid62_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--memoryC2_uid209_sinPiZTableGenerator(LOOKUP,208)@4
memoryC2_uid209_sinPiZTableGenerator: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
memoryC2_uid209_sinPiZTableGenerator_q <= "10101101010011";
ELSIF (clk'EVENT AND clk = '1' AND en = "1") THEN
CASE (reg_zAddr_uid62_fpCosPiTest_0_to_memoryC2_uid209_sinPiZTableGenerator_0_q) IS
WHEN "0000000" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101101010011";
WHEN "0000001" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101101010100";
WHEN "0000010" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101101010111";
WHEN "0000011" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101101011001";
WHEN "0000100" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101101011011";
WHEN "0000101" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101101011100";
WHEN "0000110" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101101011111";
WHEN "0000111" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101101100010";
WHEN "0001000" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101101100110";
WHEN "0001001" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101101101011";
WHEN "0001010" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101101110000";
WHEN "0001011" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101101110101";
WHEN "0001100" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101101111011";
WHEN "0001101" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101110000000";
WHEN "0001110" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101110000111";
WHEN "0001111" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101110001110";
WHEN "0010000" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101110010011";
WHEN "0010001" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101110011110";
WHEN "0010010" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101110100110";
WHEN "0010011" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101110101111";
WHEN "0010100" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101110111000";
WHEN "0010101" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101111000011";
WHEN "0010110" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101111001100";
WHEN "0010111" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101111010111";
WHEN "0011000" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101111100011";
WHEN "0011001" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101111101110";
WHEN "0011010" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101111111011";
WHEN "0011011" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110000001001";
WHEN "0011100" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110000010101";
WHEN "0011101" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110000100000";
WHEN "0011110" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110000110001";
WHEN "0011111" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110001000000";
WHEN "0100000" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110001001101";
WHEN "0100001" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110001011110";
WHEN "0100010" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110001101100";
WHEN "0100011" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110001111111";
WHEN "0100100" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110010001111";
WHEN "0100101" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110010100001";
WHEN "0100110" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110010110011";
WHEN "0100111" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110011000101";
WHEN "0101000" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110011010110";
WHEN "0101001" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110011101011";
WHEN "0101010" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110011111111";
WHEN "0101011" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110100010010";
WHEN "0101100" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110100100101";
WHEN "0101101" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110100111011";
WHEN "0101110" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110101001110";
WHEN "0101111" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110101100111";
WHEN "0110000" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110101111100";
WHEN "0110001" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110110010010";
WHEN "0110010" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110110100110";
WHEN "0110011" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110111000000";
WHEN "0110100" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110111010101";
WHEN "0110101" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110111110000";
WHEN "0110110" => memoryC2_uid209_sinPiZTableGenerator_q <= "10111000000110";
WHEN "0110111" => memoryC2_uid209_sinPiZTableGenerator_q <= "10111000100010";
WHEN "0111000" => memoryC2_uid209_sinPiZTableGenerator_q <= "10111000111001";
WHEN "0111001" => memoryC2_uid209_sinPiZTableGenerator_q <= "10111001010100";
WHEN "0111010" => memoryC2_uid209_sinPiZTableGenerator_q <= "10111001101111";
WHEN "0111011" => memoryC2_uid209_sinPiZTableGenerator_q <= "10111010001001";
WHEN "0111100" => memoryC2_uid209_sinPiZTableGenerator_q <= "10111010100011";
WHEN "0111101" => memoryC2_uid209_sinPiZTableGenerator_q <= "10111010111100";
WHEN "0111110" => memoryC2_uid209_sinPiZTableGenerator_q <= "10111011011001";
WHEN "0111111" => memoryC2_uid209_sinPiZTableGenerator_q <= "10111011110111";
WHEN "1000000" => memoryC2_uid209_sinPiZTableGenerator_q <= "10111100010100";
WHEN "1000001" => memoryC2_uid209_sinPiZTableGenerator_q <= "10111100110001";
WHEN "1000010" => memoryC2_uid209_sinPiZTableGenerator_q <= "10111101001101";
WHEN "1000011" => memoryC2_uid209_sinPiZTableGenerator_q <= "10111101101010";
WHEN "1000100" => memoryC2_uid209_sinPiZTableGenerator_q <= "10111110001000";
WHEN "1000101" => memoryC2_uid209_sinPiZTableGenerator_q <= "10111110100101";
WHEN "1000110" => memoryC2_uid209_sinPiZTableGenerator_q <= "10111111000101";
WHEN "1000111" => memoryC2_uid209_sinPiZTableGenerator_q <= "10111111100011";
WHEN "1001000" => memoryC2_uid209_sinPiZTableGenerator_q <= "11000000000011";
WHEN "1001001" => memoryC2_uid209_sinPiZTableGenerator_q <= "11000000100011";
WHEN "1001010" => memoryC2_uid209_sinPiZTableGenerator_q <= "11000001000100";
WHEN "1001011" => memoryC2_uid209_sinPiZTableGenerator_q <= "11000001100010";
WHEN "1001100" => memoryC2_uid209_sinPiZTableGenerator_q <= "11000010000100";
WHEN "1001101" => memoryC2_uid209_sinPiZTableGenerator_q <= "11000010100010";
WHEN "1001110" => memoryC2_uid209_sinPiZTableGenerator_q <= "11000011000110";
WHEN "1001111" => memoryC2_uid209_sinPiZTableGenerator_q <= "11000011101000";
WHEN "1010000" => memoryC2_uid209_sinPiZTableGenerator_q <= "11000100001010";
WHEN "1010001" => memoryC2_uid209_sinPiZTableGenerator_q <= "11000100101101";
WHEN "1010010" => memoryC2_uid209_sinPiZTableGenerator_q <= "11000101010001";
WHEN "1010011" => memoryC2_uid209_sinPiZTableGenerator_q <= "11000101110010";
WHEN "1010100" => memoryC2_uid209_sinPiZTableGenerator_q <= "11000110010100";
WHEN "1010101" => memoryC2_uid209_sinPiZTableGenerator_q <= "11000110111011";
WHEN "1010110" => memoryC2_uid209_sinPiZTableGenerator_q <= "11000111011010";
WHEN "1010111" => memoryC2_uid209_sinPiZTableGenerator_q <= "11001000000001";
WHEN "1011000" => memoryC2_uid209_sinPiZTableGenerator_q <= "11001000100110";
WHEN "1011001" => memoryC2_uid209_sinPiZTableGenerator_q <= "11001001001011";
WHEN "1011010" => memoryC2_uid209_sinPiZTableGenerator_q <= "11001001101101";
WHEN "1011011" => memoryC2_uid209_sinPiZTableGenerator_q <= "11001010010101";
WHEN "1011100" => memoryC2_uid209_sinPiZTableGenerator_q <= "11001010111100";
WHEN "1011101" => memoryC2_uid209_sinPiZTableGenerator_q <= "11001011100000";
WHEN "1011110" => memoryC2_uid209_sinPiZTableGenerator_q <= "11001100000101";
WHEN "1011111" => memoryC2_uid209_sinPiZTableGenerator_q <= "11001100101110";
WHEN "1100000" => memoryC2_uid209_sinPiZTableGenerator_q <= "11001101010100";
WHEN "1100001" => memoryC2_uid209_sinPiZTableGenerator_q <= "11001101111010";
WHEN "1100010" => memoryC2_uid209_sinPiZTableGenerator_q <= "11001110100010";
WHEN "1100011" => memoryC2_uid209_sinPiZTableGenerator_q <= "11001111001001";
WHEN "1100100" => memoryC2_uid209_sinPiZTableGenerator_q <= "11001111110001";
WHEN "1100101" => memoryC2_uid209_sinPiZTableGenerator_q <= "11010000010110";
WHEN "1100110" => memoryC2_uid209_sinPiZTableGenerator_q <= "11010000111111";
WHEN "1100111" => memoryC2_uid209_sinPiZTableGenerator_q <= "11010001101001";
WHEN "1101000" => memoryC2_uid209_sinPiZTableGenerator_q <= "11010010010010";
WHEN "1101001" => memoryC2_uid209_sinPiZTableGenerator_q <= "11010010111101";
WHEN "1101010" => memoryC2_uid209_sinPiZTableGenerator_q <= "11010011100001";
WHEN "1101011" => memoryC2_uid209_sinPiZTableGenerator_q <= "11010100001100";
WHEN "1101100" => memoryC2_uid209_sinPiZTableGenerator_q <= "11010100110111";
WHEN "1101101" => memoryC2_uid209_sinPiZTableGenerator_q <= "11010101100001";
WHEN "1101110" => memoryC2_uid209_sinPiZTableGenerator_q <= "11010110001011";
WHEN "1101111" => memoryC2_uid209_sinPiZTableGenerator_q <= "11010110110011";
WHEN "1110000" => memoryC2_uid209_sinPiZTableGenerator_q <= "11010111011111";
WHEN "1110001" => memoryC2_uid209_sinPiZTableGenerator_q <= "11011000001010";
WHEN "1110010" => memoryC2_uid209_sinPiZTableGenerator_q <= "11011000110100";
WHEN "1110011" => memoryC2_uid209_sinPiZTableGenerator_q <= "11011001011111";
WHEN "1110100" => memoryC2_uid209_sinPiZTableGenerator_q <= "11011010001010";
WHEN "1110101" => memoryC2_uid209_sinPiZTableGenerator_q <= "11011010110110";
WHEN "1110110" => memoryC2_uid209_sinPiZTableGenerator_q <= "11011011100011";
WHEN "1110111" => memoryC2_uid209_sinPiZTableGenerator_q <= "11011100001111";
WHEN "1111000" => memoryC2_uid209_sinPiZTableGenerator_q <= "11011100111001";
WHEN "1111001" => memoryC2_uid209_sinPiZTableGenerator_q <= "11011101100011";
WHEN "1111010" => memoryC2_uid209_sinPiZTableGenerator_q <= "11011110010001";
WHEN "1111011" => memoryC2_uid209_sinPiZTableGenerator_q <= "11011110111011";
WHEN "1111100" => memoryC2_uid209_sinPiZTableGenerator_q <= "11011111101000";
WHEN "1111101" => memoryC2_uid209_sinPiZTableGenerator_q <= "11100000010101";
WHEN "1111110" => memoryC2_uid209_sinPiZTableGenerator_q <= "11100001000010";
WHEN "1111111" => memoryC2_uid209_sinPiZTableGenerator_q <= "11100001110000";
WHEN OTHERS =>
memoryC2_uid209_sinPiZTableGenerator_q <= (others => '-');
END CASE;
END IF;
END PROCESS;
--zPPolyEval_uid63_fpCosPiTest(BITSELECT,62)@3
zPPolyEval_uid63_fpCosPiTest_in <= z_uid54_fpCosPiTest_b(27 downto 0);
zPPolyEval_uid63_fpCosPiTest_b <= zPPolyEval_uid63_fpCosPiTest_in(27 downto 12);
--yT1_uid210_sinPiZPolyEval(BITSELECT,209)@3
yT1_uid210_sinPiZPolyEval_in <= zPPolyEval_uid63_fpCosPiTest_b;
yT1_uid210_sinPiZPolyEval_b <= yT1_uid210_sinPiZPolyEval_in(15 downto 2);
--reg_yT1_uid210_sinPiZPolyEval_0_to_prodXY_uid226_pT1_uid211_sinPiZPolyEval_0(REG,264)@3
reg_yT1_uid210_sinPiZPolyEval_0_to_prodXY_uid226_pT1_uid211_sinPiZPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT1_uid210_sinPiZPolyEval_0_to_prodXY_uid226_pT1_uid211_sinPiZPolyEval_0_q <= "00000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT1_uid210_sinPiZPolyEval_0_to_prodXY_uid226_pT1_uid211_sinPiZPolyEval_0_q <= yT1_uid210_sinPiZPolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_reg_yT1_uid210_sinPiZPolyEval_0_to_prodXY_uid226_pT1_uid211_sinPiZPolyEval_0_q_to_prodXY_uid226_pT1_uid211_sinPiZPolyEval_a(DELAY,499)@4
ld_reg_yT1_uid210_sinPiZPolyEval_0_to_prodXY_uid226_pT1_uid211_sinPiZPolyEval_0_q_to_prodXY_uid226_pT1_uid211_sinPiZPolyEval_a : dspba_delay
GENERIC MAP ( width => 14, depth => 1 )
PORT MAP ( xin => reg_yT1_uid210_sinPiZPolyEval_0_to_prodXY_uid226_pT1_uid211_sinPiZPolyEval_0_q, xout => ld_reg_yT1_uid210_sinPiZPolyEval_0_to_prodXY_uid226_pT1_uid211_sinPiZPolyEval_0_q_to_prodXY_uid226_pT1_uid211_sinPiZPolyEval_a_q, ena => en(0), clk => clk, aclr => areset );
--prodXY_uid226_pT1_uid211_sinPiZPolyEval(MULT,225)@5
prodXY_uid226_pT1_uid211_sinPiZPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid226_pT1_uid211_sinPiZPolyEval_a),15)) * SIGNED(prodXY_uid226_pT1_uid211_sinPiZPolyEval_b);
prodXY_uid226_pT1_uid211_sinPiZPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid226_pT1_uid211_sinPiZPolyEval_a <= (others => '0');
prodXY_uid226_pT1_uid211_sinPiZPolyEval_b <= (others => '0');
prodXY_uid226_pT1_uid211_sinPiZPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid226_pT1_uid211_sinPiZPolyEval_a <= ld_reg_yT1_uid210_sinPiZPolyEval_0_to_prodXY_uid226_pT1_uid211_sinPiZPolyEval_0_q_to_prodXY_uid226_pT1_uid211_sinPiZPolyEval_a_q;
prodXY_uid226_pT1_uid211_sinPiZPolyEval_b <= memoryC2_uid209_sinPiZTableGenerator_q;
prodXY_uid226_pT1_uid211_sinPiZPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid226_pT1_uid211_sinPiZPolyEval_pr,28));
END IF;
END IF;
END PROCESS;
prodXY_uid226_pT1_uid211_sinPiZPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid226_pT1_uid211_sinPiZPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid226_pT1_uid211_sinPiZPolyEval_q <= prodXY_uid226_pT1_uid211_sinPiZPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid227_pT1_uid211_sinPiZPolyEval(BITSELECT,226)@8
prodXYTruncFR_uid227_pT1_uid211_sinPiZPolyEval_in <= prodXY_uid226_pT1_uid211_sinPiZPolyEval_q;
prodXYTruncFR_uid227_pT1_uid211_sinPiZPolyEval_b <= prodXYTruncFR_uid227_pT1_uid211_sinPiZPolyEval_in(27 downto 13);
--highBBits_uid213_sinPiZPolyEval(BITSELECT,212)@8
highBBits_uid213_sinPiZPolyEval_in <= prodXYTruncFR_uid227_pT1_uid211_sinPiZPolyEval_b;
highBBits_uid213_sinPiZPolyEval_b <= highBBits_uid213_sinPiZPolyEval_in(14 downto 1);
--ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_notEnable(LOGICAL,557)
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_notEnable_a <= en;
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_notEnable_q <= not ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_notEnable_a;
--ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_nor(LOGICAL,596)
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_nor_a <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_notEnable_q;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_nor_b <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_sticky_ena_q;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_nor_q <= not (ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_nor_a or ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_nor_b);
--ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_mem_top(CONSTANT,592)
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_mem_top_q <= "010";
--ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_cmp(LOGICAL,593)
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_cmp_a <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_mem_top_q;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdmux_q);
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_cmp_q <= "1" when ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_cmp_a = ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_cmp_b else "0";
--ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_cmpReg(REG,594)
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_cmpReg_q <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_sticky_ena(REG,597)
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_nor_q = "1") THEN
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_sticky_ena_q <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_enaAnd(LOGICAL,598)
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_enaAnd_a <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_sticky_ena_q;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_enaAnd_b <= en;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_enaAnd_q <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_enaAnd_a and ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_enaAnd_b;
--ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt(COUNTER,588)
-- every=1, low=0, high=2, step=1, init=1
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt_i <= TO_UNSIGNED(1,2);
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt_i = 1 THEN
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt_eq = '1') THEN
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt_i <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt_i - 2;
ELSE
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt_i <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt_i,2));
--ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdreg(REG,589)
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdreg_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdreg_q <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdmux(MUX,590)
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdmux_s <= en;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdmux: PROCESS (ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdmux_s, ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdreg_q, ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdmux_s IS
WHEN "0" => ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdmux_q <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdreg_q;
WHEN "1" => ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdmux_q <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem(DUALMEM,587)
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_reset0 <= areset;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_ia <= reg_zAddr_uid62_fpCosPiTest_0_to_memoryC2_uid209_sinPiZTableGenerator_0_q;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_aa <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdreg_q;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_ab <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdmux_q;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 7,
widthad_a => 2,
numwords_a => 3,
width_b => 7,
widthad_b => 2,
numwords_b => 3,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_iq,
address_a => ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_aa,
data_a => ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_ia
);
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_q <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_iq(6 downto 0);
--memoryC1_uid208_sinPiZTableGenerator(LOOKUP,207)@8
memoryC1_uid208_sinPiZTableGenerator: PROCESS (ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_q)
BEGIN
-- Begin reserved scope level
CASE (ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_q) IS
WHEN "0000000" => memoryC1_uid208_sinPiZTableGenerator_q <= "000000000000000000001";
WHEN "0000001" => memoryC1_uid208_sinPiZTableGenerator_q <= "111111101011010101010";
WHEN "0000010" => memoryC1_uid208_sinPiZTableGenerator_q <= "111111010110101010001";
WHEN "0000011" => memoryC1_uid208_sinPiZTableGenerator_q <= "111111000001111111100";
WHEN "0000100" => memoryC1_uid208_sinPiZTableGenerator_q <= "111110101101010101010";
WHEN "0000101" => memoryC1_uid208_sinPiZTableGenerator_q <= "111110011000101011101";
WHEN "0000110" => memoryC1_uid208_sinPiZTableGenerator_q <= "111110000100000010101";
WHEN "0000111" => memoryC1_uid208_sinPiZTableGenerator_q <= "111101101111011010001";
WHEN "0001000" => memoryC1_uid208_sinPiZTableGenerator_q <= "111101011010110010101";
WHEN "0001001" => memoryC1_uid208_sinPiZTableGenerator_q <= "111101000110001011111";
WHEN "0001010" => memoryC1_uid208_sinPiZTableGenerator_q <= "111100110001100110010";
WHEN "0001011" => memoryC1_uid208_sinPiZTableGenerator_q <= "111100011101000010000";
WHEN "0001100" => memoryC1_uid208_sinPiZTableGenerator_q <= "111100001000011110111";
WHEN "0001101" => memoryC1_uid208_sinPiZTableGenerator_q <= "111011110011111101011";
WHEN "0001110" => memoryC1_uid208_sinPiZTableGenerator_q <= "111011011111011101011";
WHEN "0001111" => memoryC1_uid208_sinPiZTableGenerator_q <= "111011001010111110111";
WHEN "0010000" => memoryC1_uid208_sinPiZTableGenerator_q <= "111010110110100010101";
WHEN "0010001" => memoryC1_uid208_sinPiZTableGenerator_q <= "111010100010000111100";
WHEN "0010010" => memoryC1_uid208_sinPiZTableGenerator_q <= "111010001101101111000";
WHEN "0010011" => memoryC1_uid208_sinPiZTableGenerator_q <= "111001111001011000011";
WHEN "0010100" => memoryC1_uid208_sinPiZTableGenerator_q <= "111001100101000100010";
WHEN "0010101" => memoryC1_uid208_sinPiZTableGenerator_q <= "111001010000110010001";
WHEN "0010110" => memoryC1_uid208_sinPiZTableGenerator_q <= "111000111100100010111";
WHEN "0010111" => memoryC1_uid208_sinPiZTableGenerator_q <= "111000101000010110001";
WHEN "0011000" => memoryC1_uid208_sinPiZTableGenerator_q <= "111000010100001011111";
WHEN "0011001" => memoryC1_uid208_sinPiZTableGenerator_q <= "111000000000000100110";
WHEN "0011010" => memoryC1_uid208_sinPiZTableGenerator_q <= "110111101100000000011";
WHEN "0011011" => memoryC1_uid208_sinPiZTableGenerator_q <= "110111010111111111000";
WHEN "0011100" => memoryC1_uid208_sinPiZTableGenerator_q <= "110111000100000001000";
WHEN "0011101" => memoryC1_uid208_sinPiZTableGenerator_q <= "110110110000000110101";
WHEN "0011110" => memoryC1_uid208_sinPiZTableGenerator_q <= "110110011100001110111";
WHEN "0011111" => memoryC1_uid208_sinPiZTableGenerator_q <= "110110001000011011000";
WHEN "0100000" => memoryC1_uid208_sinPiZTableGenerator_q <= "110101110100101011010";
WHEN "0100001" => memoryC1_uid208_sinPiZTableGenerator_q <= "110101100000111110101";
WHEN "0100010" => memoryC1_uid208_sinPiZTableGenerator_q <= "110101001101010110010";
WHEN "0100011" => memoryC1_uid208_sinPiZTableGenerator_q <= "110100111001110001011";
WHEN "0100100" => memoryC1_uid208_sinPiZTableGenerator_q <= "110100100110010001001";
WHEN "0100101" => memoryC1_uid208_sinPiZTableGenerator_q <= "110100010010110100110";
WHEN "0100110" => memoryC1_uid208_sinPiZTableGenerator_q <= "110011111111011100110";
WHEN "0100111" => memoryC1_uid208_sinPiZTableGenerator_q <= "110011101100001001010";
WHEN "0101000" => memoryC1_uid208_sinPiZTableGenerator_q <= "110011011000111010011";
WHEN "0101001" => memoryC1_uid208_sinPiZTableGenerator_q <= "110011000101101111111";
WHEN "0101010" => memoryC1_uid208_sinPiZTableGenerator_q <= "110010110010101010010";
WHEN "0101011" => memoryC1_uid208_sinPiZTableGenerator_q <= "110010011111101001101";
WHEN "0101100" => memoryC1_uid208_sinPiZTableGenerator_q <= "110010001100101110000";
WHEN "0101101" => memoryC1_uid208_sinPiZTableGenerator_q <= "110001111001110111001";
WHEN "0101110" => memoryC1_uid208_sinPiZTableGenerator_q <= "110001100111000110000";
WHEN "0101111" => memoryC1_uid208_sinPiZTableGenerator_q <= "110001010100011001011";
WHEN "0110000" => memoryC1_uid208_sinPiZTableGenerator_q <= "110001000001110010110";
WHEN "0110001" => memoryC1_uid208_sinPiZTableGenerator_q <= "110000101111010001100";
WHEN "0110010" => memoryC1_uid208_sinPiZTableGenerator_q <= "110000011100110110001";
WHEN "0110011" => memoryC1_uid208_sinPiZTableGenerator_q <= "110000001010011111111";
WHEN "0110100" => memoryC1_uid208_sinPiZTableGenerator_q <= "101111111000010000000";
WHEN "0110101" => memoryC1_uid208_sinPiZTableGenerator_q <= "101111100110000101100";
WHEN "0110110" => memoryC1_uid208_sinPiZTableGenerator_q <= "101111010100000001100";
WHEN "0110111" => memoryC1_uid208_sinPiZTableGenerator_q <= "101111000010000011001";
WHEN "0111000" => memoryC1_uid208_sinPiZTableGenerator_q <= "101110110000001011100";
WHEN "0111001" => memoryC1_uid208_sinPiZTableGenerator_q <= "101110011110011001110";
WHEN "0111010" => memoryC1_uid208_sinPiZTableGenerator_q <= "101110001100101110101";
WHEN "0111011" => memoryC1_uid208_sinPiZTableGenerator_q <= "101101111011001010001";
WHEN "0111100" => memoryC1_uid208_sinPiZTableGenerator_q <= "101101101001101100010";
WHEN "0111101" => memoryC1_uid208_sinPiZTableGenerator_q <= "101101011000010101010";
WHEN "0111110" => memoryC1_uid208_sinPiZTableGenerator_q <= "101101000111000100101";
WHEN "0111111" => memoryC1_uid208_sinPiZTableGenerator_q <= "101100110101111010111";
WHEN "1000000" => memoryC1_uid208_sinPiZTableGenerator_q <= "101100100100111000010";
WHEN "1000001" => memoryC1_uid208_sinPiZTableGenerator_q <= "101100010011111100111";
WHEN "1000010" => memoryC1_uid208_sinPiZTableGenerator_q <= "101100000011001000111";
WHEN "1000011" => memoryC1_uid208_sinPiZTableGenerator_q <= "101011110010011100000";
WHEN "1000100" => memoryC1_uid208_sinPiZTableGenerator_q <= "101011100001110110100";
WHEN "1000101" => memoryC1_uid208_sinPiZTableGenerator_q <= "101011010001011000100";
WHEN "1000110" => memoryC1_uid208_sinPiZTableGenerator_q <= "101011000001000001110";
WHEN "1000111" => memoryC1_uid208_sinPiZTableGenerator_q <= "101010110000110011000";
WHEN "1001000" => memoryC1_uid208_sinPiZTableGenerator_q <= "101010100000101011111";
WHEN "1001001" => memoryC1_uid208_sinPiZTableGenerator_q <= "101010010000101100100";
WHEN "1001010" => memoryC1_uid208_sinPiZTableGenerator_q <= "101010000000110101001";
WHEN "1001011" => memoryC1_uid208_sinPiZTableGenerator_q <= "101001110001000110000";
WHEN "1001100" => memoryC1_uid208_sinPiZTableGenerator_q <= "101001100001011110101";
WHEN "1001101" => memoryC1_uid208_sinPiZTableGenerator_q <= "101001010001111111111";
WHEN "1001110" => memoryC1_uid208_sinPiZTableGenerator_q <= "101001000010101000110";
WHEN "1001111" => memoryC1_uid208_sinPiZTableGenerator_q <= "101000110011011010001";
WHEN "1010000" => memoryC1_uid208_sinPiZTableGenerator_q <= "101000100100010100001";
WHEN "1010001" => memoryC1_uid208_sinPiZTableGenerator_q <= "101000010101010110100";
WHEN "1010010" => memoryC1_uid208_sinPiZTableGenerator_q <= "101000000110100001011";
WHEN "1010011" => memoryC1_uid208_sinPiZTableGenerator_q <= "100111110111110101011";
WHEN "1010100" => memoryC1_uid208_sinPiZTableGenerator_q <= "100111101001010010000";
WHEN "1010101" => memoryC1_uid208_sinPiZTableGenerator_q <= "100111011010110110110";
WHEN "1010110" => memoryC1_uid208_sinPiZTableGenerator_q <= "100111001100100101100";
WHEN "1010111" => memoryC1_uid208_sinPiZTableGenerator_q <= "100110111110011100011";
WHEN "1011000" => memoryC1_uid208_sinPiZTableGenerator_q <= "100110110000011100011";
WHEN "1011001" => memoryC1_uid208_sinPiZTableGenerator_q <= "100110100010100101110";
WHEN "1011010" => memoryC1_uid208_sinPiZTableGenerator_q <= "100110010100111000101";
WHEN "1011011" => memoryC1_uid208_sinPiZTableGenerator_q <= "100110000111010100001";
WHEN "1011100" => memoryC1_uid208_sinPiZTableGenerator_q <= "100101111001111001000";
WHEN "1011101" => memoryC1_uid208_sinPiZTableGenerator_q <= "100101101100100111111";
WHEN "1011110" => memoryC1_uid208_sinPiZTableGenerator_q <= "100101011111100000000";
WHEN "1011111" => memoryC1_uid208_sinPiZTableGenerator_q <= "100101010010100001001";
WHEN "1100000" => memoryC1_uid208_sinPiZTableGenerator_q <= "100101000101101100011";
WHEN "1100001" => memoryC1_uid208_sinPiZTableGenerator_q <= "100100111001000001011";
WHEN "1100010" => memoryC1_uid208_sinPiZTableGenerator_q <= "100100101100011111111";
WHEN "1100011" => memoryC1_uid208_sinPiZTableGenerator_q <= "100100100000001000010";
WHEN "1100100" => memoryC1_uid208_sinPiZTableGenerator_q <= "100100010011111010101";
WHEN "1100101" => memoryC1_uid208_sinPiZTableGenerator_q <= "100100000111110111001";
WHEN "1100110" => memoryC1_uid208_sinPiZTableGenerator_q <= "100011111011111101010";
WHEN "1100111" => memoryC1_uid208_sinPiZTableGenerator_q <= "100011110000001101010";
WHEN "1101000" => memoryC1_uid208_sinPiZTableGenerator_q <= "100011100100100111101";
WHEN "1101001" => memoryC1_uid208_sinPiZTableGenerator_q <= "100011011001001011111";
WHEN "1101010" => memoryC1_uid208_sinPiZTableGenerator_q <= "100011001101111011010";
WHEN "1101011" => memoryC1_uid208_sinPiZTableGenerator_q <= "100011000010110100001";
WHEN "1101100" => memoryC1_uid208_sinPiZTableGenerator_q <= "100010110111110111010";
WHEN "1101101" => memoryC1_uid208_sinPiZTableGenerator_q <= "100010101101000101000";
WHEN "1101110" => memoryC1_uid208_sinPiZTableGenerator_q <= "100010100010011101001";
WHEN "1101111" => memoryC1_uid208_sinPiZTableGenerator_q <= "100010011000000000001";
WHEN "1110000" => memoryC1_uid208_sinPiZTableGenerator_q <= "100010001101101101010";
WHEN "1110001" => memoryC1_uid208_sinPiZTableGenerator_q <= "100010000011100100111";
WHEN "1110010" => memoryC1_uid208_sinPiZTableGenerator_q <= "100001111001100111100";
WHEN "1110011" => memoryC1_uid208_sinPiZTableGenerator_q <= "100001101111110100101";
WHEN "1110100" => memoryC1_uid208_sinPiZTableGenerator_q <= "100001100110001100100";
WHEN "1110101" => memoryC1_uid208_sinPiZTableGenerator_q <= "100001011100101111001";
WHEN "1110110" => memoryC1_uid208_sinPiZTableGenerator_q <= "100001010011011100011";
WHEN "1110111" => memoryC1_uid208_sinPiZTableGenerator_q <= "100001001010010100101";
WHEN "1111000" => memoryC1_uid208_sinPiZTableGenerator_q <= "100001000001011000000";
WHEN "1111001" => memoryC1_uid208_sinPiZTableGenerator_q <= "100000111000100110100";
WHEN "1111010" => memoryC1_uid208_sinPiZTableGenerator_q <= "100000101111111111100";
WHEN "1111011" => memoryC1_uid208_sinPiZTableGenerator_q <= "100000100111100011111";
WHEN "1111100" => memoryC1_uid208_sinPiZTableGenerator_q <= "100000011111010011000";
WHEN "1111101" => memoryC1_uid208_sinPiZTableGenerator_q <= "100000010111001101010";
WHEN "1111110" => memoryC1_uid208_sinPiZTableGenerator_q <= "100000001111010010101";
WHEN "1111111" => memoryC1_uid208_sinPiZTableGenerator_q <= "100000000111100011001";
WHEN OTHERS =>
memoryC1_uid208_sinPiZTableGenerator_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--sumAHighB_uid214_sinPiZPolyEval(ADD,213)@8
sumAHighB_uid214_sinPiZPolyEval_a <= STD_LOGIC_VECTOR((21 downto 21 => memoryC1_uid208_sinPiZTableGenerator_q(20)) & memoryC1_uid208_sinPiZTableGenerator_q);
sumAHighB_uid214_sinPiZPolyEval_b <= STD_LOGIC_VECTOR((21 downto 14 => highBBits_uid213_sinPiZPolyEval_b(13)) & highBBits_uid213_sinPiZPolyEval_b);
sumAHighB_uid214_sinPiZPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid214_sinPiZPolyEval_a) + SIGNED(sumAHighB_uid214_sinPiZPolyEval_b));
sumAHighB_uid214_sinPiZPolyEval_q <= sumAHighB_uid214_sinPiZPolyEval_o(21 downto 0);
--lowRangeB_uid212_sinPiZPolyEval(BITSELECT,211)@8
lowRangeB_uid212_sinPiZPolyEval_in <= prodXYTruncFR_uid227_pT1_uid211_sinPiZPolyEval_b(0 downto 0);
lowRangeB_uid212_sinPiZPolyEval_b <= lowRangeB_uid212_sinPiZPolyEval_in(0 downto 0);
--s1_uid212_uid215_sinPiZPolyEval(BITJOIN,214)@8
s1_uid212_uid215_sinPiZPolyEval_q <= sumAHighB_uid214_sinPiZPolyEval_q & lowRangeB_uid212_sinPiZPolyEval_b;
--reg_s1_uid212_uid215_sinPiZPolyEval_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_1(REG,267)@8
reg_s1_uid212_uid215_sinPiZPolyEval_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_s1_uid212_uid215_sinPiZPolyEval_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_1_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_s1_uid212_uid215_sinPiZPolyEval_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_1_q <= s1_uid212_uid215_sinPiZPolyEval_q;
END IF;
END IF;
END PROCESS;
--ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_nor(LOGICAL,609)
ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_nor_a <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_notEnable_q;
ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_nor_b <= ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_sticky_ena_q;
ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_nor_q <= not (ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_nor_a or ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_nor_b);
--ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_sticky_ena(REG,610)
ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_nor_q = "1") THEN
ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_sticky_ena_q <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_enaAnd(LOGICAL,611)
ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_enaAnd_a <= ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_sticky_ena_q;
ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_enaAnd_b <= en;
ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_enaAnd_q <= ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_enaAnd_a and ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_enaAnd_b;
--ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_inputreg(DELAY,599)
ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 16, depth => 1 )
PORT MAP ( xin => zPPolyEval_uid63_fpCosPiTest_b, xout => ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem(DUALMEM,600)
ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_reset0 <= areset;
ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_ia <= ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_inputreg_q;
ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_aa <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdreg_q;
ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_ab <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdmux_q;
ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 16,
widthad_a => 2,
numwords_a => 3,
width_b => 16,
widthad_b => 2,
numwords_b => 3,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_iq,
address_a => ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_aa,
data_a => ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_ia
);
ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_q <= ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_iq(15 downto 0);
--reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0(REG,266)@8
reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_q <= ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--prodXY_uid229_pT2_uid217_sinPiZPolyEval(MULT,228)@9
prodXY_uid229_pT2_uid217_sinPiZPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid229_pT2_uid217_sinPiZPolyEval_a),17)) * SIGNED(prodXY_uid229_pT2_uid217_sinPiZPolyEval_b);
prodXY_uid229_pT2_uid217_sinPiZPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid229_pT2_uid217_sinPiZPolyEval_a <= (others => '0');
prodXY_uid229_pT2_uid217_sinPiZPolyEval_b <= (others => '0');
prodXY_uid229_pT2_uid217_sinPiZPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid229_pT2_uid217_sinPiZPolyEval_a <= reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_q;
prodXY_uid229_pT2_uid217_sinPiZPolyEval_b <= reg_s1_uid212_uid215_sinPiZPolyEval_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_1_q;
prodXY_uid229_pT2_uid217_sinPiZPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid229_pT2_uid217_sinPiZPolyEval_pr,39));
END IF;
END IF;
END PROCESS;
prodXY_uid229_pT2_uid217_sinPiZPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid229_pT2_uid217_sinPiZPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid229_pT2_uid217_sinPiZPolyEval_q <= prodXY_uid229_pT2_uid217_sinPiZPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid230_pT2_uid217_sinPiZPolyEval(BITSELECT,229)@12
prodXYTruncFR_uid230_pT2_uid217_sinPiZPolyEval_in <= prodXY_uid229_pT2_uid217_sinPiZPolyEval_q;
prodXYTruncFR_uid230_pT2_uid217_sinPiZPolyEval_b <= prodXYTruncFR_uid230_pT2_uid217_sinPiZPolyEval_in(38 downto 15);
--highBBits_uid219_sinPiZPolyEval(BITSELECT,218)@12
highBBits_uid219_sinPiZPolyEval_in <= prodXYTruncFR_uid230_pT2_uid217_sinPiZPolyEval_b;
highBBits_uid219_sinPiZPolyEval_b <= highBBits_uid219_sinPiZPolyEval_in(23 downto 2);
--ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_nor(LOGICAL,584)
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_nor_a <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_notEnable_q;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_nor_b <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_sticky_ena_q;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_nor_q <= not (ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_nor_a or ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_nor_b);
--ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_mem_top(CONSTANT,554)
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_mem_top_q <= "0110";
--ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_cmp(LOGICAL,555)
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_cmp_a <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_mem_top_q;
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdmux_q);
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_cmp_q <= "1" when ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_cmp_a = ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_cmp_b else "0";
--ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_cmpReg(REG,556)
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_cmpReg_q <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_sticky_ena(REG,585)
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_nor_q = "1") THEN
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_sticky_ena_q <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_enaAnd(LOGICAL,586)
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_enaAnd_a <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_sticky_ena_q;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_enaAnd_b <= en;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_enaAnd_q <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_enaAnd_a and ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_enaAnd_b;
--ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt(COUNTER,550)
-- every=1, low=0, high=6, step=1, init=1
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt_i = 5 THEN
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt_eq <= '1';
ELSE
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt_eq = '1') THEN
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt_i <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt_i - 6;
ELSE
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt_i <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt_i,3));
--ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdreg(REG,551)
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdreg_q <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdmux(MUX,552)
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdmux_s <= en;
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdmux: PROCESS (ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdmux_s, ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdreg_q, ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt_q)
BEGIN
CASE ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdmux_s IS
WHEN "0" => ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdmux_q <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdreg_q;
WHEN "1" => ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdmux_q <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem(DUALMEM,575)
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_reset0 <= areset;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_ia <= reg_zAddr_uid62_fpCosPiTest_0_to_memoryC2_uid209_sinPiZTableGenerator_0_q;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_aa <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdreg_q;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_ab <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdmux_q;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 7,
widthad_a => 3,
numwords_a => 7,
width_b => 7,
widthad_b => 3,
numwords_b => 7,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_iq,
address_a => ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_aa,
data_a => ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_ia
);
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_q <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_iq(6 downto 0);
--memoryC0_uid207_sinPiZTableGenerator(LOOKUP,206)@12
memoryC0_uid207_sinPiZTableGenerator: PROCESS (ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_q)
BEGIN
-- Begin reserved scope level
CASE (ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_q) IS
WHEN "0000000" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100100100001111110110101110";
WHEN "0000001" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100100100001110100100000010";
WHEN "0000010" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100100100001010101100000000";
WHEN "0000011" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100100100000100001110101000";
WHEN "0000100" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100100011111011001011111101";
WHEN "0000101" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100100011101111100100000010";
WHEN "0000110" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100100011100001010110111011";
WHEN "0000111" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100100011010000100100101111";
WHEN "0001000" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100100010111101001101100010";
WHEN "0001001" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100100010100111010001011101";
WHEN "0001010" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100100010001110110000100111";
WHEN "0001011" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100100001110011101011001001";
WHEN "0001100" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100100001010110000001001110";
WHEN "0001101" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100100000110101110011000000";
WHEN "0001110" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100100000010011000000101011";
WHEN "0001111" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100011111101101101010011101";
WHEN "0010000" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100011111000101110000100010";
WHEN "0010001" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100011110011011010011001011";
WHEN "0010010" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100011101101110010010100101";
WHEN "0010011" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100011100111110101111000011";
WHEN "0010100" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100011100001100101000110101";
WHEN "0010101" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100011011011000000000001111";
WHEN "0010110" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100011010100000110101100011";
WHEN "0010111" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100011001100111001001000110";
WHEN "0011000" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100011000101010111011001110";
WHEN "0011001" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100010111101100001100010000";
WHEN "0011010" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100010110101010111100100100";
WHEN "0011011" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100010101100111001100100010";
WHEN "0011100" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100010100100000111100100011";
WHEN "0011101" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100010011011000001101000000";
WHEN "0011110" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100010010001100111110010110";
WHEN "0011111" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100010000111111010000111111";
WHEN "0100000" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100001111101111000101010111";
WHEN "0100001" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100001110011100011011111110";
WHEN "0100010" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100001101000111010101010001";
WHEN "0100011" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100001011101111110001110000";
WHEN "0100100" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100001010010101110001111010";
WHEN "0100101" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100001000111001010110010010";
WHEN "0100110" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100000111011010011111011001";
WHEN "0100111" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100000101111001001101110010";
WHEN "0101000" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100000100010101100010000001";
WHEN "0101001" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100000010101111011100101011";
WHEN "0101010" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100000001000110111110010101";
WHEN "0101011" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011111111011100000111100110";
WHEN "0101100" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011111101101110111001000101";
WHEN "0101101" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011111011111111010011011011";
WHEN "0101110" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011111010001101010111001111";
WHEN "0101111" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011111000011001000101001110";
WHEN "0110000" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011110110100010011110000000";
WHEN "0110001" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011110100101001100010010010";
WHEN "0110010" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011110010101110010010110000";
WHEN "0110011" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011110000110000110000001000";
WHEN "0110100" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011101110110000111011000111";
WHEN "0110101" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011101100101110110100011101";
WHEN "0110110" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011101010101010011100111001";
WHEN "0110111" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011101000100011110101001100";
WHEN "0111000" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011100110011010111110000111";
WHEN "0111001" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011100100001111111000011101";
WHEN "0111010" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011100010000010100101000000";
WHEN "0111011" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011011111110011000100100100";
WHEN "0111100" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011011101100001010111111110";
WHEN "0111101" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011011011001101100000000011";
WHEN "0111110" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011011000110111011101101010";
WHEN "0111111" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011010110011111010001101001";
WHEN "1000000" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011010100000100111100111000";
WHEN "1000001" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011010001101000100000001111";
WHEN "1000010" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011001111001001111100100111";
WHEN "1000011" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011001100101001010010111011";
WHEN "1000100" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011001010000110100100000101";
WHEN "1000101" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011000111100001110001000001";
WHEN "1000110" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011000100111010111010101011";
WHEN "1000111" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011000010010010000001111111";
WHEN "1001000" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010111111100111000111111011";
WHEN "1001001" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010111100111010001101011110";
WHEN "1001010" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010111010001011010011100110";
WHEN "1001011" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010110111011010011011010011";
WHEN "1001100" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010110100100111100101100110";
WHEN "1001101" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010110001110010110011011111";
WHEN "1001110" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010101110111100000110000001";
WHEN "1001111" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010101100000011011110001110";
WHEN "1010000" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010101001001000111101001000";
WHEN "1010001" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010100110001100100011110100";
WHEN "1010010" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010100011001110010011010110";
WHEN "1010011" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010100000001110001100110010";
WHEN "1010100" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010011101001100010001001111";
WHEN "1010101" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010011010001000100001110100";
WHEN "1010110" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010010111000010111111100101";
WHEN "1010111" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010010011111011101011101100";
WHEN "1011000" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010010000110010100111010001";
WHEN "1011001" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010001101100111110011011011";
WHEN "1011010" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010001010011011010001010100";
WHEN "1011011" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010000111001101000010000111";
WHEN "1011100" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010000011111101000110111110";
WHEN "1011101" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010000000101011100001000010";
WHEN "1011110" => memoryC0_uid207_sinPiZTableGenerator_q <= "01001111101011000010001100001";
WHEN "1011111" => memoryC0_uid207_sinPiZTableGenerator_q <= "01001111010000011011001100111";
WHEN "1100000" => memoryC0_uid207_sinPiZTableGenerator_q <= "01001110110101100111010011111";
WHEN "1100001" => memoryC0_uid207_sinPiZTableGenerator_q <= "01001110011010100110101010111";
WHEN "1100010" => memoryC0_uid207_sinPiZTableGenerator_q <= "01001101111111011001011011101";
WHEN "1100011" => memoryC0_uid207_sinPiZTableGenerator_q <= "01001101100011111111101111111";
WHEN "1100100" => memoryC0_uid207_sinPiZTableGenerator_q <= "01001101001000011001110001011";
WHEN "1100101" => memoryC0_uid207_sinPiZTableGenerator_q <= "01001100101100100111101010001";
WHEN "1100110" => memoryC0_uid207_sinPiZTableGenerator_q <= "01001100010000101001100100001";
WHEN "1100111" => memoryC0_uid207_sinPiZTableGenerator_q <= "01001011110100011111101001011";
WHEN "1101000" => memoryC0_uid207_sinPiZTableGenerator_q <= "01001011011000001010000011111";
WHEN "1101001" => memoryC0_uid207_sinPiZTableGenerator_q <= "01001010111011101000111101111";
WHEN "1101010" => memoryC0_uid207_sinPiZTableGenerator_q <= "01001010011110111100100001011";
WHEN "1101011" => memoryC0_uid207_sinPiZTableGenerator_q <= "01001010000010000100111000111";
WHEN "1101100" => memoryC0_uid207_sinPiZTableGenerator_q <= "01001001100101000010001110101";
WHEN "1101101" => memoryC0_uid207_sinPiZTableGenerator_q <= "01001001000111110100101100111";
WHEN "1101110" => memoryC0_uid207_sinPiZTableGenerator_q <= "01001000101010011100011110001";
WHEN "1101111" => memoryC0_uid207_sinPiZTableGenerator_q <= "01001000001100111001101100110";
WHEN "1110000" => memoryC0_uid207_sinPiZTableGenerator_q <= "01000111101111001100100011011";
WHEN "1110001" => memoryC0_uid207_sinPiZTableGenerator_q <= "01000111010001010101001100101";
WHEN "1110010" => memoryC0_uid207_sinPiZTableGenerator_q <= "01000110110011010011110010111";
WHEN "1110011" => memoryC0_uid207_sinPiZTableGenerator_q <= "01000110010101001000100001000";
WHEN "1110100" => memoryC0_uid207_sinPiZTableGenerator_q <= "01000101110110110011100001101";
WHEN "1110101" => memoryC0_uid207_sinPiZTableGenerator_q <= "01000101011000010100111111100";
WHEN "1110110" => memoryC0_uid207_sinPiZTableGenerator_q <= "01000100111001101101000101100";
WHEN "1110111" => memoryC0_uid207_sinPiZTableGenerator_q <= "01000100011010111011111110011";
WHEN "1111000" => memoryC0_uid207_sinPiZTableGenerator_q <= "01000011111100000001110101000";
WHEN "1111001" => memoryC0_uid207_sinPiZTableGenerator_q <= "01000011011100111110110100010";
WHEN "1111010" => memoryC0_uid207_sinPiZTableGenerator_q <= "01000010111101110011000111010";
WHEN "1111011" => memoryC0_uid207_sinPiZTableGenerator_q <= "01000010011110011110111000111";
WHEN "1111100" => memoryC0_uid207_sinPiZTableGenerator_q <= "01000001111111000010010100010";
WHEN "1111101" => memoryC0_uid207_sinPiZTableGenerator_q <= "01000001011111011101100100011";
WHEN "1111110" => memoryC0_uid207_sinPiZTableGenerator_q <= "01000000111111110000110100011";
WHEN "1111111" => memoryC0_uid207_sinPiZTableGenerator_q <= "01000000011111111100001111011";
WHEN OTHERS =>
memoryC0_uid207_sinPiZTableGenerator_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--sumAHighB_uid220_sinPiZPolyEval(ADD,219)@12
sumAHighB_uid220_sinPiZPolyEval_a <= STD_LOGIC_VECTOR((29 downto 29 => memoryC0_uid207_sinPiZTableGenerator_q(28)) & memoryC0_uid207_sinPiZTableGenerator_q);
sumAHighB_uid220_sinPiZPolyEval_b <= STD_LOGIC_VECTOR((29 downto 22 => highBBits_uid219_sinPiZPolyEval_b(21)) & highBBits_uid219_sinPiZPolyEval_b);
sumAHighB_uid220_sinPiZPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid220_sinPiZPolyEval_a) + SIGNED(sumAHighB_uid220_sinPiZPolyEval_b));
sumAHighB_uid220_sinPiZPolyEval_q <= sumAHighB_uid220_sinPiZPolyEval_o(29 downto 0);
--lowRangeB_uid218_sinPiZPolyEval(BITSELECT,217)@12
lowRangeB_uid218_sinPiZPolyEval_in <= prodXYTruncFR_uid230_pT2_uid217_sinPiZPolyEval_b(1 downto 0);
lowRangeB_uid218_sinPiZPolyEval_b <= lowRangeB_uid218_sinPiZPolyEval_in(1 downto 0);
--s2_uid218_uid221_sinPiZPolyEval(BITJOIN,220)@12
s2_uid218_uid221_sinPiZPolyEval_q <= sumAHighB_uid220_sinPiZPolyEval_q & lowRangeB_uid218_sinPiZPolyEval_b;
--fxpSinRes_uid65_fpCosPiTest(BITSELECT,64)@12
fxpSinRes_uid65_fpCosPiTest_in <= s2_uid218_uid221_sinPiZPolyEval_q(29 downto 0);
fxpSinRes_uid65_fpCosPiTest_b <= fxpSinRes_uid65_fpCosPiTest_in(29 downto 5);
--reg_fxpSinRes_uid65_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_1(REG,270)@12
reg_fxpSinRes_uid65_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fxpSinRes_uid65_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_1_q <= "0000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fxpSinRes_uid65_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_1_q <= fxpSinRes_uid65_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_nor(LOGICAL,622)
ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_nor_a <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_notEnable_q;
ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_nor_b <= ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_sticky_ena_q;
ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_nor_q <= not (ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_nor_a or ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_nor_b);
--ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_sticky_ena(REG,623)
ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_nor_q = "1") THEN
ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_sticky_ena_q <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_enaAnd(LOGICAL,624)
ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_enaAnd_a <= ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_sticky_ena_q;
ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_enaAnd_b <= en;
ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_enaAnd_q <= ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_enaAnd_a and ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_enaAnd_b;
--LeftShiftStage131dto0_uid202_alignedZ_uid57_fpCosPiTest(BITSELECT,201)@7
LeftShiftStage131dto0_uid202_alignedZ_uid57_fpCosPiTest_in <= leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_q(31 downto 0);
LeftShiftStage131dto0_uid202_alignedZ_uid57_fpCosPiTest_b <= LeftShiftStage131dto0_uid202_alignedZ_uid57_fpCosPiTest_in(31 downto 0);
--leftShiftStage2Idx3_uid203_alignedZ_uid57_fpCosPiTest(BITJOIN,202)@7
leftShiftStage2Idx3_uid203_alignedZ_uid57_fpCosPiTest_q <= LeftShiftStage131dto0_uid202_alignedZ_uid57_fpCosPiTest_b & leftShiftStage2Idx3Pad3_uid131_fxpX_uid41_fpCosPiTest_q;
--LeftShiftStage132dto0_uid199_alignedZ_uid57_fpCosPiTest(BITSELECT,198)@7
LeftShiftStage132dto0_uid199_alignedZ_uid57_fpCosPiTest_in <= leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_q(32 downto 0);
LeftShiftStage132dto0_uid199_alignedZ_uid57_fpCosPiTest_b <= LeftShiftStage132dto0_uid199_alignedZ_uid57_fpCosPiTest_in(32 downto 0);
--leftShiftStage2Idx2_uid200_alignedZ_uid57_fpCosPiTest(BITJOIN,199)@7
leftShiftStage2Idx2_uid200_alignedZ_uid57_fpCosPiTest_q <= LeftShiftStage132dto0_uid199_alignedZ_uid57_fpCosPiTest_b & leftShiftStage2Idx2Pad2_uid128_fxpX_uid41_fpCosPiTest_q;
--LeftShiftStage133dto0_uid196_alignedZ_uid57_fpCosPiTest(BITSELECT,195)@7
LeftShiftStage133dto0_uid196_alignedZ_uid57_fpCosPiTest_in <= leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_q(33 downto 0);
LeftShiftStage133dto0_uid196_alignedZ_uid57_fpCosPiTest_b <= LeftShiftStage133dto0_uid196_alignedZ_uid57_fpCosPiTest_in(33 downto 0);
--leftShiftStage2Idx1_uid197_alignedZ_uid57_fpCosPiTest(BITJOIN,196)@7
leftShiftStage2Idx1_uid197_alignedZ_uid57_fpCosPiTest_q <= LeftShiftStage133dto0_uid196_alignedZ_uid57_fpCosPiTest_b & GND_q;
--vStage_uid141_lzcZ_uid56_fpCosPiTest(BITSELECT,140)@3
vStage_uid141_lzcZ_uid56_fpCosPiTest_in <= z_uid54_fpCosPiTest_b(2 downto 0);
vStage_uid141_lzcZ_uid56_fpCosPiTest_b <= vStage_uid141_lzcZ_uid56_fpCosPiTest_in(2 downto 0);
--ld_vStage_uid141_lzcZ_uid56_fpCosPiTest_b_to_leftShiftStage0Idx2_uid180_alignedZ_uid57_fpCosPiTest_b(DELAY,450)@3
ld_vStage_uid141_lzcZ_uid56_fpCosPiTest_b_to_leftShiftStage0Idx2_uid180_alignedZ_uid57_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 3, depth => 3 )
PORT MAP ( xin => vStage_uid141_lzcZ_uid56_fpCosPiTest_b, xout => ld_vStage_uid141_lzcZ_uid56_fpCosPiTest_b_to_leftShiftStage0Idx2_uid180_alignedZ_uid57_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage0Idx2_uid180_alignedZ_uid57_fpCosPiTest(BITJOIN,179)@6
leftShiftStage0Idx2_uid180_alignedZ_uid57_fpCosPiTest_q <= ld_vStage_uid141_lzcZ_uid56_fpCosPiTest_b_to_leftShiftStage0Idx2_uid180_alignedZ_uid57_fpCosPiTest_b_q & leftShiftStage0Idx2Pad32_uid108_fxpX_uid41_fpCosPiTest_q;
--X18dto0_uid176_alignedZ_uid57_fpCosPiTest(BITSELECT,175)@3
X18dto0_uid176_alignedZ_uid57_fpCosPiTest_in <= z_uid54_fpCosPiTest_b(18 downto 0);
X18dto0_uid176_alignedZ_uid57_fpCosPiTest_b <= X18dto0_uid176_alignedZ_uid57_fpCosPiTest_in(18 downto 0);
--ld_X18dto0_uid176_alignedZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx1_uid177_alignedZ_uid57_fpCosPiTest_b_inputreg(DELAY,573)
ld_X18dto0_uid176_alignedZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx1_uid177_alignedZ_uid57_fpCosPiTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 19, depth => 1 )
PORT MAP ( xin => X18dto0_uid176_alignedZ_uid57_fpCosPiTest_b, xout => ld_X18dto0_uid176_alignedZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx1_uid177_alignedZ_uid57_fpCosPiTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_X18dto0_uid176_alignedZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx1_uid177_alignedZ_uid57_fpCosPiTest_b(DELAY,449)@3
ld_X18dto0_uid176_alignedZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx1_uid177_alignedZ_uid57_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 19, depth => 2 )
PORT MAP ( xin => ld_X18dto0_uid176_alignedZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx1_uid177_alignedZ_uid57_fpCosPiTest_b_inputreg_q, xout => ld_X18dto0_uid176_alignedZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx1_uid177_alignedZ_uid57_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage0Idx1_uid177_alignedZ_uid57_fpCosPiTest(BITJOIN,176)@6
leftShiftStage0Idx1_uid177_alignedZ_uid57_fpCosPiTest_q <= ld_X18dto0_uid176_alignedZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx1_uid177_alignedZ_uid57_fpCosPiTest_b_q & leftShiftStage0Idx1Pad16_uid105_fxpX_uid41_fpCosPiTest_q;
--ld_z_uid54_fpCosPiTest_b_to_leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_c_inputreg(DELAY,574)
ld_z_uid54_fpCosPiTest_b_to_leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 35, depth => 1 )
PORT MAP ( xin => z_uid54_fpCosPiTest_b, xout => ld_z_uid54_fpCosPiTest_b_to_leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_z_uid54_fpCosPiTest_b_to_leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_c(DELAY,453)@3
ld_z_uid54_fpCosPiTest_b_to_leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_c : dspba_delay
GENERIC MAP ( width => 35, depth => 2 )
PORT MAP ( xin => ld_z_uid54_fpCosPiTest_b_to_leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_c_inputreg_q, xout => ld_z_uid54_fpCosPiTest_b_to_leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--rVStage_uid138_lzcZ_uid56_fpCosPiTest(BITSELECT,137)@3
rVStage_uid138_lzcZ_uid56_fpCosPiTest_in <= z_uid54_fpCosPiTest_b;
rVStage_uid138_lzcZ_uid56_fpCosPiTest_b <= rVStage_uid138_lzcZ_uid56_fpCosPiTest_in(34 downto 3);
--reg_rVStage_uid138_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid139_lzcZ_uid56_fpCosPiTest_1(REG,247)@3
reg_rVStage_uid138_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid139_lzcZ_uid56_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid138_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid139_lzcZ_uid56_fpCosPiTest_1_q <= "00000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid138_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid139_lzcZ_uid56_fpCosPiTest_1_q <= rVStage_uid138_lzcZ_uid56_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid139_lzcZ_uid56_fpCosPiTest(LOGICAL,138)@4
vCount_uid139_lzcZ_uid56_fpCosPiTest_a <= reg_rVStage_uid138_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid139_lzcZ_uid56_fpCosPiTest_1_q;
vCount_uid139_lzcZ_uid56_fpCosPiTest_b <= leftShiftStage0Idx2Pad32_uid108_fxpX_uid41_fpCosPiTest_q;
vCount_uid139_lzcZ_uid56_fpCosPiTest_q <= "1" when vCount_uid139_lzcZ_uid56_fpCosPiTest_a = vCount_uid139_lzcZ_uid56_fpCosPiTest_b else "0";
--ld_vCount_uid139_lzcZ_uid56_fpCosPiTest_q_to_r_uid172_lzcZ_uid56_fpCosPiTest_f(DELAY,447)@4
ld_vCount_uid139_lzcZ_uid56_fpCosPiTest_q_to_r_uid172_lzcZ_uid56_fpCosPiTest_f : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => vCount_uid139_lzcZ_uid56_fpCosPiTest_q, xout => ld_vCount_uid139_lzcZ_uid56_fpCosPiTest_q_to_r_uid172_lzcZ_uid56_fpCosPiTest_f_q, ena => en(0), clk => clk, aclr => areset );
--mO_uid140_lzcZ_uid56_fpCosPiTest(CONSTANT,139)
mO_uid140_lzcZ_uid56_fpCosPiTest_q <= "11111111111111111111111111111";
--cStage_uid142_lzcZ_uid56_fpCosPiTest(BITJOIN,141)@3
cStage_uid142_lzcZ_uid56_fpCosPiTest_q <= vStage_uid141_lzcZ_uid56_fpCosPiTest_b & mO_uid140_lzcZ_uid56_fpCosPiTest_q;
--reg_cStage_uid142_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid144_lzcZ_uid56_fpCosPiTest_3(REG,249)@3
reg_cStage_uid142_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid144_lzcZ_uid56_fpCosPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cStage_uid142_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid144_lzcZ_uid56_fpCosPiTest_3_q <= "00000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cStage_uid142_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid144_lzcZ_uid56_fpCosPiTest_3_q <= cStage_uid142_lzcZ_uid56_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--vStagei_uid144_lzcZ_uid56_fpCosPiTest(MUX,143)@4
vStagei_uid144_lzcZ_uid56_fpCosPiTest_s <= vCount_uid139_lzcZ_uid56_fpCosPiTest_q;
vStagei_uid144_lzcZ_uid56_fpCosPiTest: PROCESS (vStagei_uid144_lzcZ_uid56_fpCosPiTest_s, en, reg_rVStage_uid138_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid139_lzcZ_uid56_fpCosPiTest_1_q, reg_cStage_uid142_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid144_lzcZ_uid56_fpCosPiTest_3_q)
BEGIN
CASE vStagei_uid144_lzcZ_uid56_fpCosPiTest_s IS
WHEN "0" => vStagei_uid144_lzcZ_uid56_fpCosPiTest_q <= reg_rVStage_uid138_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid139_lzcZ_uid56_fpCosPiTest_1_q;
WHEN "1" => vStagei_uid144_lzcZ_uid56_fpCosPiTest_q <= reg_cStage_uid142_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid144_lzcZ_uid56_fpCosPiTest_3_q;
WHEN OTHERS => vStagei_uid144_lzcZ_uid56_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid146_lzcZ_uid56_fpCosPiTest(BITSELECT,145)@4
rVStage_uid146_lzcZ_uid56_fpCosPiTest_in <= vStagei_uid144_lzcZ_uid56_fpCosPiTest_q;
rVStage_uid146_lzcZ_uid56_fpCosPiTest_b <= rVStage_uid146_lzcZ_uid56_fpCosPiTest_in(31 downto 16);
--reg_rVStage_uid146_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid147_lzcZ_uid56_fpCosPiTest_1(REG,250)@4
reg_rVStage_uid146_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid147_lzcZ_uid56_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid146_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid147_lzcZ_uid56_fpCosPiTest_1_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid146_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid147_lzcZ_uid56_fpCosPiTest_1_q <= rVStage_uid146_lzcZ_uid56_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid147_lzcZ_uid56_fpCosPiTest(LOGICAL,146)@5
vCount_uid147_lzcZ_uid56_fpCosPiTest_a <= reg_rVStage_uid146_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid147_lzcZ_uid56_fpCosPiTest_1_q;
vCount_uid147_lzcZ_uid56_fpCosPiTest_b <= leftShiftStage0Idx1Pad16_uid105_fxpX_uid41_fpCosPiTest_q;
vCount_uid147_lzcZ_uid56_fpCosPiTest_q <= "1" when vCount_uid147_lzcZ_uid56_fpCosPiTest_a = vCount_uid147_lzcZ_uid56_fpCosPiTest_b else "0";
--ld_vCount_uid147_lzcZ_uid56_fpCosPiTest_q_to_r_uid172_lzcZ_uid56_fpCosPiTest_e(DELAY,446)@5
ld_vCount_uid147_lzcZ_uid56_fpCosPiTest_q_to_r_uid172_lzcZ_uid56_fpCosPiTest_e : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vCount_uid147_lzcZ_uid56_fpCosPiTest_q, xout => ld_vCount_uid147_lzcZ_uid56_fpCosPiTest_q_to_r_uid172_lzcZ_uid56_fpCosPiTest_e_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid148_lzcZ_uid56_fpCosPiTest(BITSELECT,147)@4
vStage_uid148_lzcZ_uid56_fpCosPiTest_in <= vStagei_uid144_lzcZ_uid56_fpCosPiTest_q(15 downto 0);
vStage_uid148_lzcZ_uid56_fpCosPiTest_b <= vStage_uid148_lzcZ_uid56_fpCosPiTest_in(15 downto 0);
--reg_vStage_uid148_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid150_lzcZ_uid56_fpCosPiTest_3(REG,252)@4
reg_vStage_uid148_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid150_lzcZ_uid56_fpCosPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid148_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid150_lzcZ_uid56_fpCosPiTest_3_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid148_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid150_lzcZ_uid56_fpCosPiTest_3_q <= vStage_uid148_lzcZ_uid56_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid150_lzcZ_uid56_fpCosPiTest(MUX,149)@5
vStagei_uid150_lzcZ_uid56_fpCosPiTest_s <= vCount_uid147_lzcZ_uid56_fpCosPiTest_q;
vStagei_uid150_lzcZ_uid56_fpCosPiTest: PROCESS (vStagei_uid150_lzcZ_uid56_fpCosPiTest_s, en, reg_rVStage_uid146_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid147_lzcZ_uid56_fpCosPiTest_1_q, reg_vStage_uid148_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid150_lzcZ_uid56_fpCosPiTest_3_q)
BEGIN
CASE vStagei_uid150_lzcZ_uid56_fpCosPiTest_s IS
WHEN "0" => vStagei_uid150_lzcZ_uid56_fpCosPiTest_q <= reg_rVStage_uid146_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid147_lzcZ_uid56_fpCosPiTest_1_q;
WHEN "1" => vStagei_uid150_lzcZ_uid56_fpCosPiTest_q <= reg_vStage_uid148_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid150_lzcZ_uid56_fpCosPiTest_3_q;
WHEN OTHERS => vStagei_uid150_lzcZ_uid56_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid152_lzcZ_uid56_fpCosPiTest(BITSELECT,151)@5
rVStage_uid152_lzcZ_uid56_fpCosPiTest_in <= vStagei_uid150_lzcZ_uid56_fpCosPiTest_q;
rVStage_uid152_lzcZ_uid56_fpCosPiTest_b <= rVStage_uid152_lzcZ_uid56_fpCosPiTest_in(15 downto 8);
--vCount_uid153_lzcZ_uid56_fpCosPiTest(LOGICAL,152)@5
vCount_uid153_lzcZ_uid56_fpCosPiTest_a <= rVStage_uid152_lzcZ_uid56_fpCosPiTest_b;
vCount_uid153_lzcZ_uid56_fpCosPiTest_b <= cstAllZWE_uid21_fpCosPiTest_q;
vCount_uid153_lzcZ_uid56_fpCosPiTest_q <= "1" when vCount_uid153_lzcZ_uid56_fpCosPiTest_a = vCount_uid153_lzcZ_uid56_fpCosPiTest_b else "0";
--reg_vCount_uid153_lzcZ_uid56_fpCosPiTest_0_to_r_uid172_lzcZ_uid56_fpCosPiTest_3(REG,256)@5
reg_vCount_uid153_lzcZ_uid56_fpCosPiTest_0_to_r_uid172_lzcZ_uid56_fpCosPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid153_lzcZ_uid56_fpCosPiTest_0_to_r_uid172_lzcZ_uid56_fpCosPiTest_3_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid153_lzcZ_uid56_fpCosPiTest_0_to_r_uid172_lzcZ_uid56_fpCosPiTest_3_q <= vCount_uid153_lzcZ_uid56_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--vStage_uid154_lzcZ_uid56_fpCosPiTest(BITSELECT,153)@5
vStage_uid154_lzcZ_uid56_fpCosPiTest_in <= vStagei_uid150_lzcZ_uid56_fpCosPiTest_q(7 downto 0);
vStage_uid154_lzcZ_uid56_fpCosPiTest_b <= vStage_uid154_lzcZ_uid56_fpCosPiTest_in(7 downto 0);
--vStagei_uid156_lzcZ_uid56_fpCosPiTest(MUX,155)@5
vStagei_uid156_lzcZ_uid56_fpCosPiTest_s <= vCount_uid153_lzcZ_uid56_fpCosPiTest_q;
vStagei_uid156_lzcZ_uid56_fpCosPiTest: PROCESS (vStagei_uid156_lzcZ_uid56_fpCosPiTest_s, en, rVStage_uid152_lzcZ_uid56_fpCosPiTest_b, vStage_uid154_lzcZ_uid56_fpCosPiTest_b)
BEGIN
CASE vStagei_uid156_lzcZ_uid56_fpCosPiTest_s IS
WHEN "0" => vStagei_uid156_lzcZ_uid56_fpCosPiTest_q <= rVStage_uid152_lzcZ_uid56_fpCosPiTest_b;
WHEN "1" => vStagei_uid156_lzcZ_uid56_fpCosPiTest_q <= vStage_uid154_lzcZ_uid56_fpCosPiTest_b;
WHEN OTHERS => vStagei_uid156_lzcZ_uid56_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid158_lzcZ_uid56_fpCosPiTest(BITSELECT,157)@5
rVStage_uid158_lzcZ_uid56_fpCosPiTest_in <= vStagei_uid156_lzcZ_uid56_fpCosPiTest_q;
rVStage_uid158_lzcZ_uid56_fpCosPiTest_b <= rVStage_uid158_lzcZ_uid56_fpCosPiTest_in(7 downto 4);
--reg_rVStage_uid158_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid159_lzcZ_uid56_fpCosPiTest_1(REG,253)@5
reg_rVStage_uid158_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid159_lzcZ_uid56_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid158_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid159_lzcZ_uid56_fpCosPiTest_1_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid158_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid159_lzcZ_uid56_fpCosPiTest_1_q <= rVStage_uid158_lzcZ_uid56_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid159_lzcZ_uid56_fpCosPiTest(LOGICAL,158)@6
vCount_uid159_lzcZ_uid56_fpCosPiTest_a <= reg_rVStage_uid158_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid159_lzcZ_uid56_fpCosPiTest_1_q;
vCount_uid159_lzcZ_uid56_fpCosPiTest_b <= leftShiftStage1Idx1Pad4_uid114_fxpX_uid41_fpCosPiTest_q;
vCount_uid159_lzcZ_uid56_fpCosPiTest_q <= "1" when vCount_uid159_lzcZ_uid56_fpCosPiTest_a = vCount_uid159_lzcZ_uid56_fpCosPiTest_b else "0";
--vStage_uid160_lzcZ_uid56_fpCosPiTest(BITSELECT,159)@5
vStage_uid160_lzcZ_uid56_fpCosPiTest_in <= vStagei_uid156_lzcZ_uid56_fpCosPiTest_q(3 downto 0);
vStage_uid160_lzcZ_uid56_fpCosPiTest_b <= vStage_uid160_lzcZ_uid56_fpCosPiTest_in(3 downto 0);
--reg_vStage_uid160_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid162_lzcZ_uid56_fpCosPiTest_3(REG,255)@5
reg_vStage_uid160_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid162_lzcZ_uid56_fpCosPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid160_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid162_lzcZ_uid56_fpCosPiTest_3_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid160_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid162_lzcZ_uid56_fpCosPiTest_3_q <= vStage_uid160_lzcZ_uid56_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid162_lzcZ_uid56_fpCosPiTest(MUX,161)@6
vStagei_uid162_lzcZ_uid56_fpCosPiTest_s <= vCount_uid159_lzcZ_uid56_fpCosPiTest_q;
vStagei_uid162_lzcZ_uid56_fpCosPiTest: PROCESS (vStagei_uid162_lzcZ_uid56_fpCosPiTest_s, en, reg_rVStage_uid158_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid159_lzcZ_uid56_fpCosPiTest_1_q, reg_vStage_uid160_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid162_lzcZ_uid56_fpCosPiTest_3_q)
BEGIN
CASE vStagei_uid162_lzcZ_uid56_fpCosPiTest_s IS
WHEN "0" => vStagei_uid162_lzcZ_uid56_fpCosPiTest_q <= reg_rVStage_uid158_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid159_lzcZ_uid56_fpCosPiTest_1_q;
WHEN "1" => vStagei_uid162_lzcZ_uid56_fpCosPiTest_q <= reg_vStage_uid160_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid162_lzcZ_uid56_fpCosPiTest_3_q;
WHEN OTHERS => vStagei_uid162_lzcZ_uid56_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid164_lzcZ_uid56_fpCosPiTest(BITSELECT,163)@6
rVStage_uid164_lzcZ_uid56_fpCosPiTest_in <= vStagei_uid162_lzcZ_uid56_fpCosPiTest_q;
rVStage_uid164_lzcZ_uid56_fpCosPiTest_b <= rVStage_uid164_lzcZ_uid56_fpCosPiTest_in(3 downto 2);
--vCount_uid165_lzcZ_uid56_fpCosPiTest(LOGICAL,164)@6
vCount_uid165_lzcZ_uid56_fpCosPiTest_a <= rVStage_uid164_lzcZ_uid56_fpCosPiTest_b;
vCount_uid165_lzcZ_uid56_fpCosPiTest_b <= leftShiftStage2Idx2Pad2_uid128_fxpX_uid41_fpCosPiTest_q;
vCount_uid165_lzcZ_uid56_fpCosPiTest_q <= "1" when vCount_uid165_lzcZ_uid56_fpCosPiTest_a = vCount_uid165_lzcZ_uid56_fpCosPiTest_b else "0";
--vStage_uid166_lzcZ_uid56_fpCosPiTest(BITSELECT,165)@6
vStage_uid166_lzcZ_uid56_fpCosPiTest_in <= vStagei_uid162_lzcZ_uid56_fpCosPiTest_q(1 downto 0);
vStage_uid166_lzcZ_uid56_fpCosPiTest_b <= vStage_uid166_lzcZ_uid56_fpCosPiTest_in(1 downto 0);
--vStagei_uid168_lzcZ_uid56_fpCosPiTest(MUX,167)@6
vStagei_uid168_lzcZ_uid56_fpCosPiTest_s <= vCount_uid165_lzcZ_uid56_fpCosPiTest_q;
vStagei_uid168_lzcZ_uid56_fpCosPiTest: PROCESS (vStagei_uid168_lzcZ_uid56_fpCosPiTest_s, en, rVStage_uid164_lzcZ_uid56_fpCosPiTest_b, vStage_uid166_lzcZ_uid56_fpCosPiTest_b)
BEGIN
CASE vStagei_uid168_lzcZ_uid56_fpCosPiTest_s IS
WHEN "0" => vStagei_uid168_lzcZ_uid56_fpCosPiTest_q <= rVStage_uid164_lzcZ_uid56_fpCosPiTest_b;
WHEN "1" => vStagei_uid168_lzcZ_uid56_fpCosPiTest_q <= vStage_uid166_lzcZ_uid56_fpCosPiTest_b;
WHEN OTHERS => vStagei_uid168_lzcZ_uid56_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid170_lzcZ_uid56_fpCosPiTest(BITSELECT,169)@6
rVStage_uid170_lzcZ_uid56_fpCosPiTest_in <= vStagei_uid168_lzcZ_uid56_fpCosPiTest_q;
rVStage_uid170_lzcZ_uid56_fpCosPiTest_b <= rVStage_uid170_lzcZ_uid56_fpCosPiTest_in(1 downto 1);
--vCount_uid171_lzcZ_uid56_fpCosPiTest(LOGICAL,170)@6
vCount_uid171_lzcZ_uid56_fpCosPiTest_a <= rVStage_uid170_lzcZ_uid56_fpCosPiTest_b;
vCount_uid171_lzcZ_uid56_fpCosPiTest_b <= GND_q;
vCount_uid171_lzcZ_uid56_fpCosPiTest_q <= "1" when vCount_uid171_lzcZ_uid56_fpCosPiTest_a = vCount_uid171_lzcZ_uid56_fpCosPiTest_b else "0";
--r_uid172_lzcZ_uid56_fpCosPiTest(BITJOIN,171)@6
r_uid172_lzcZ_uid56_fpCosPiTest_q <= ld_vCount_uid139_lzcZ_uid56_fpCosPiTest_q_to_r_uid172_lzcZ_uid56_fpCosPiTest_f_q & ld_vCount_uid147_lzcZ_uid56_fpCosPiTest_q_to_r_uid172_lzcZ_uid56_fpCosPiTest_e_q & reg_vCount_uid153_lzcZ_uid56_fpCosPiTest_0_to_r_uid172_lzcZ_uid56_fpCosPiTest_3_q & vCount_uid159_lzcZ_uid56_fpCosPiTest_q & vCount_uid165_lzcZ_uid56_fpCosPiTest_q & vCount_uid171_lzcZ_uid56_fpCosPiTest_q;
--leftShiftStageSel5Dto4_uid182_alignedZ_uid57_fpCosPiTest(BITSELECT,181)@6
leftShiftStageSel5Dto4_uid182_alignedZ_uid57_fpCosPiTest_in <= r_uid172_lzcZ_uid56_fpCosPiTest_q;
leftShiftStageSel5Dto4_uid182_alignedZ_uid57_fpCosPiTest_b <= leftShiftStageSel5Dto4_uid182_alignedZ_uid57_fpCosPiTest_in(5 downto 4);
--leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest(MUX,182)@6
leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_s <= leftShiftStageSel5Dto4_uid182_alignedZ_uid57_fpCosPiTest_b;
leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest: PROCESS (leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_s, en, ld_z_uid54_fpCosPiTest_b_to_leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_c_q, leftShiftStage0Idx1_uid177_alignedZ_uid57_fpCosPiTest_q, leftShiftStage0Idx2_uid180_alignedZ_uid57_fpCosPiTest_q, cstZwSwF_uid15_fpCosPiTest_q)
BEGIN
CASE leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_s IS
WHEN "00" => leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_q <= ld_z_uid54_fpCosPiTest_b_to_leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_c_q;
WHEN "01" => leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_q <= leftShiftStage0Idx1_uid177_alignedZ_uid57_fpCosPiTest_q;
WHEN "10" => leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_q <= leftShiftStage0Idx2_uid180_alignedZ_uid57_fpCosPiTest_q;
WHEN "11" => leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_q <= cstZwSwF_uid15_fpCosPiTest_q;
WHEN OTHERS => leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage022dto0_uid191_alignedZ_uid57_fpCosPiTest(BITSELECT,190)@6
LeftShiftStage022dto0_uid191_alignedZ_uid57_fpCosPiTest_in <= leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_q(22 downto 0);
LeftShiftStage022dto0_uid191_alignedZ_uid57_fpCosPiTest_b <= LeftShiftStage022dto0_uid191_alignedZ_uid57_fpCosPiTest_in(22 downto 0);
--leftShiftStage1Idx3_uid192_alignedZ_uid57_fpCosPiTest(BITJOIN,191)@6
leftShiftStage1Idx3_uid192_alignedZ_uid57_fpCosPiTest_q <= LeftShiftStage022dto0_uid191_alignedZ_uid57_fpCosPiTest_b & leftShiftStage1Idx3Pad12_uid120_fxpX_uid41_fpCosPiTest_q;
--reg_leftShiftStage1Idx3_uid192_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_5(REG,261)@6
reg_leftShiftStage1Idx3_uid192_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx3_uid192_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_5_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx3_uid192_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_5_q <= leftShiftStage1Idx3_uid192_alignedZ_uid57_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage026dto0_uid188_alignedZ_uid57_fpCosPiTest(BITSELECT,187)@6
LeftShiftStage026dto0_uid188_alignedZ_uid57_fpCosPiTest_in <= leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_q(26 downto 0);
LeftShiftStage026dto0_uid188_alignedZ_uid57_fpCosPiTest_b <= LeftShiftStage026dto0_uid188_alignedZ_uid57_fpCosPiTest_in(26 downto 0);
--leftShiftStage1Idx2_uid189_alignedZ_uid57_fpCosPiTest(BITJOIN,188)@6
leftShiftStage1Idx2_uid189_alignedZ_uid57_fpCosPiTest_q <= LeftShiftStage026dto0_uid188_alignedZ_uid57_fpCosPiTest_b & cstAllZWE_uid21_fpCosPiTest_q;
--reg_leftShiftStage1Idx2_uid189_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_4(REG,260)@6
reg_leftShiftStage1Idx2_uid189_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx2_uid189_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_4_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx2_uid189_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_4_q <= leftShiftStage1Idx2_uid189_alignedZ_uid57_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage030dto0_uid185_alignedZ_uid57_fpCosPiTest(BITSELECT,184)@6
LeftShiftStage030dto0_uid185_alignedZ_uid57_fpCosPiTest_in <= leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_q(30 downto 0);
LeftShiftStage030dto0_uid185_alignedZ_uid57_fpCosPiTest_b <= LeftShiftStage030dto0_uid185_alignedZ_uid57_fpCosPiTest_in(30 downto 0);
--leftShiftStage1Idx1_uid186_alignedZ_uid57_fpCosPiTest(BITJOIN,185)@6
leftShiftStage1Idx1_uid186_alignedZ_uid57_fpCosPiTest_q <= LeftShiftStage030dto0_uid185_alignedZ_uid57_fpCosPiTest_b & leftShiftStage1Idx1Pad4_uid114_fxpX_uid41_fpCosPiTest_q;
--reg_leftShiftStage1Idx1_uid186_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_3(REG,259)@6
reg_leftShiftStage1Idx1_uid186_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx1_uid186_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_3_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx1_uid186_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_3_q <= leftShiftStage1Idx1_uid186_alignedZ_uid57_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--reg_leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_2(REG,258)@6
reg_leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_2_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_2_q <= leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel3Dto2_uid193_alignedZ_uid57_fpCosPiTest(BITSELECT,192)@6
leftShiftStageSel3Dto2_uid193_alignedZ_uid57_fpCosPiTest_in <= r_uid172_lzcZ_uid56_fpCosPiTest_q(3 downto 0);
leftShiftStageSel3Dto2_uid193_alignedZ_uid57_fpCosPiTest_b <= leftShiftStageSel3Dto2_uid193_alignedZ_uid57_fpCosPiTest_in(3 downto 2);
--reg_leftShiftStageSel3Dto2_uid193_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_1(REG,257)@6
reg_leftShiftStageSel3Dto2_uid193_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel3Dto2_uid193_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel3Dto2_uid193_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_1_q <= leftShiftStageSel3Dto2_uid193_alignedZ_uid57_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest(MUX,193)@7
leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_s <= reg_leftShiftStageSel3Dto2_uid193_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_1_q;
leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest: PROCESS (leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_s, en, reg_leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_2_q, reg_leftShiftStage1Idx1_uid186_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_3_q, reg_leftShiftStage1Idx2_uid189_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_4_q, reg_leftShiftStage1Idx3_uid192_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_5_q)
BEGIN
CASE leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_s IS
WHEN "00" => leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_q <= reg_leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_2_q;
WHEN "01" => leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_q <= reg_leftShiftStage1Idx1_uid186_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_3_q;
WHEN "10" => leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_q <= reg_leftShiftStage1Idx2_uid189_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_4_q;
WHEN "11" => leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_q <= reg_leftShiftStage1Idx3_uid192_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_5_q;
WHEN OTHERS => leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--leftShiftStageSel1Dto0_uid204_alignedZ_uid57_fpCosPiTest(BITSELECT,203)@6
leftShiftStageSel1Dto0_uid204_alignedZ_uid57_fpCosPiTest_in <= r_uid172_lzcZ_uid56_fpCosPiTest_q(1 downto 0);
leftShiftStageSel1Dto0_uid204_alignedZ_uid57_fpCosPiTest_b <= leftShiftStageSel1Dto0_uid204_alignedZ_uid57_fpCosPiTest_in(1 downto 0);
--reg_leftShiftStageSel1Dto0_uid204_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest_1(REG,262)@6
reg_leftShiftStageSel1Dto0_uid204_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel1Dto0_uid204_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel1Dto0_uid204_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest_1_q <= leftShiftStageSel1Dto0_uid204_alignedZ_uid57_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest(MUX,204)@7
leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest_s <= reg_leftShiftStageSel1Dto0_uid204_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest_1_q;
leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest: PROCESS (leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest_s, en, leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_q, leftShiftStage2Idx1_uid197_alignedZ_uid57_fpCosPiTest_q, leftShiftStage2Idx2_uid200_alignedZ_uid57_fpCosPiTest_q, leftShiftStage2Idx3_uid203_alignedZ_uid57_fpCosPiTest_q)
BEGIN
CASE leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest_s IS
WHEN "00" => leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest_q <= leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_q;
WHEN "01" => leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest_q <= leftShiftStage2Idx1_uid197_alignedZ_uid57_fpCosPiTest_q;
WHEN "10" => leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest_q <= leftShiftStage2Idx2_uid200_alignedZ_uid57_fpCosPiTest_q;
WHEN "11" => leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest_q <= leftShiftStage2Idx3_uid203_alignedZ_uid57_fpCosPiTest_q;
WHEN OTHERS => leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--alignedZLow_uid58_fpCosPiTest(BITSELECT,57)@7
alignedZLow_uid58_fpCosPiTest_in <= leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest_q;
alignedZLow_uid58_fpCosPiTest_b <= alignedZLow_uid58_fpCosPiTest_in(34 downto 11);
--ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_inputreg(DELAY,612)
ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 24, depth => 1 )
PORT MAP ( xin => alignedZLow_uid58_fpCosPiTest_b, xout => ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem(DUALMEM,613)
ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_reset0 <= areset;
ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_ia <= ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_inputreg_q;
ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_aa <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdreg_q;
ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_ab <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdmux_q;
ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 24,
widthad_a => 2,
numwords_a => 3,
width_b => 24,
widthad_b => 2,
numwords_b => 3,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_iq,
address_a => ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_aa,
data_a => ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_ia
);
ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_q <= ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_iq(23 downto 0);
--reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0(REG,269)@12
reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_q <= ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest(MULT,222)@13
prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_pr <= UNSIGNED(prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_a) * UNSIGNED(prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_b);
prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_a <= (others => '0');
prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_b <= (others => '0');
prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_a <= reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_q;
prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_b <= reg_fxpSinRes_uid65_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_1_q;
prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_s1 <= STD_LOGIC_VECTOR(prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_pr);
END IF;
END IF;
END PROCESS;
prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_q <= prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid224_mul2xSinRes_uid66_fpCosPiTest(BITSELECT,223)@16
prodXYTruncFR_uid224_mul2xSinRes_uid66_fpCosPiTest_in <= prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_q;
prodXYTruncFR_uid224_mul2xSinRes_uid66_fpCosPiTest_b <= prodXYTruncFR_uid224_mul2xSinRes_uid66_fpCosPiTest_in(48 downto 23);
--normBit_uid67_fpCosPiTest(BITSELECT,66)@16
normBit_uid67_fpCosPiTest_in <= prodXYTruncFR_uid224_mul2xSinRes_uid66_fpCosPiTest_b;
normBit_uid67_fpCosPiTest_b <= normBit_uid67_fpCosPiTest_in(25 downto 25);
--cstAllZWF_uid9_fpCosPiTest(CONSTANT,8)
cstAllZWF_uid9_fpCosPiTest_q <= "00000000000000000000000";
--rndExpUpdate_uid72_uid73_fpCosPiTest(BITJOIN,72)@16
rndExpUpdate_uid72_uid73_fpCosPiTest_q <= normBit_uid67_fpCosPiTest_b & cstAllZWF_uid9_fpCosPiTest_q & VCC_q;
--ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_nor(LOGICAL,558)
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_nor_a <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_notEnable_q;
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_nor_b <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_sticky_ena_q;
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_nor_q <= not (ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_nor_a or ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_nor_b);
--ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_sticky_ena(REG,559)
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_nor_q = "1") THEN
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_sticky_ena_q <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_enaAnd(LOGICAL,560)
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_enaAnd_a <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_sticky_ena_q;
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_enaAnd_b <= en;
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_enaAnd_q <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_enaAnd_a and ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_enaAnd_b;
--reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1(REG,271)@6
reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q <= r_uid172_lzcZ_uid56_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem(DUALMEM,549)
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_reset0 <= areset;
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_ia <= reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q;
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_aa <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdreg_q;
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_ab <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdmux_q;
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 6,
widthad_a => 3,
numwords_a => 7,
width_b => 6,
widthad_b => 3,
numwords_b => 7,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_iq,
address_a => ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_aa,
data_a => ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_ia
);
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_q <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_iq(5 downto 0);
--cstBiasM1_uid11_fpCosPiTest(CONSTANT,10)
cstBiasM1_uid11_fpCosPiTest_q <= "01111110";
--expHardCase_uid59_fpCosPiTest(SUB,58)@15
expHardCase_uid59_fpCosPiTest_a <= STD_LOGIC_VECTOR("0" & cstBiasM1_uid11_fpCosPiTest_q);
expHardCase_uid59_fpCosPiTest_b <= STD_LOGIC_VECTOR("000" & ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_q);
expHardCase_uid59_fpCosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expHardCase_uid59_fpCosPiTest_a) - UNSIGNED(expHardCase_uid59_fpCosPiTest_b));
expHardCase_uid59_fpCosPiTest_q <= expHardCase_uid59_fpCosPiTest_o(8 downto 0);
--expP_uid60_fpCosPiTest(BITSELECT,59)@15
expP_uid60_fpCosPiTest_in <= expHardCase_uid59_fpCosPiTest_q(7 downto 0);
expP_uid60_fpCosPiTest_b <= expP_uid60_fpCosPiTest_in(7 downto 0);
--reg_expP_uid60_fpCosPiTest_0_to_expFracPreRnd_uid71_uid71_fpCosPiTest_1(REG,272)@15
reg_expP_uid60_fpCosPiTest_0_to_expFracPreRnd_uid71_uid71_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expP_uid60_fpCosPiTest_0_to_expFracPreRnd_uid71_uid71_fpCosPiTest_1_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expP_uid60_fpCosPiTest_0_to_expFracPreRnd_uid71_uid71_fpCosPiTest_1_q <= expP_uid60_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--highRes_uid68_fpCosPiTest(BITSELECT,67)@16
highRes_uid68_fpCosPiTest_in <= prodXYTruncFR_uid224_mul2xSinRes_uid66_fpCosPiTest_b(24 downto 0);
highRes_uid68_fpCosPiTest_b <= highRes_uid68_fpCosPiTest_in(24 downto 1);
--lowRes_uid69_fpCosPiTest(BITSELECT,68)@16
lowRes_uid69_fpCosPiTest_in <= prodXYTruncFR_uid224_mul2xSinRes_uid66_fpCosPiTest_b(23 downto 0);
lowRes_uid69_fpCosPiTest_b <= lowRes_uid69_fpCosPiTest_in(23 downto 0);
--fracRCompPreRnd_uid70_fpCosPiTest(MUX,69)@16
fracRCompPreRnd_uid70_fpCosPiTest_s <= normBit_uid67_fpCosPiTest_b;
fracRCompPreRnd_uid70_fpCosPiTest: PROCESS (fracRCompPreRnd_uid70_fpCosPiTest_s, en, lowRes_uid69_fpCosPiTest_b, highRes_uid68_fpCosPiTest_b)
BEGIN
CASE fracRCompPreRnd_uid70_fpCosPiTest_s IS
WHEN "0" => fracRCompPreRnd_uid70_fpCosPiTest_q <= lowRes_uid69_fpCosPiTest_b;
WHEN "1" => fracRCompPreRnd_uid70_fpCosPiTest_q <= highRes_uid68_fpCosPiTest_b;
WHEN OTHERS => fracRCompPreRnd_uid70_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--expFracPreRnd_uid71_uid71_fpCosPiTest(BITJOIN,70)@16
expFracPreRnd_uid71_uid71_fpCosPiTest_q <= reg_expP_uid60_fpCosPiTest_0_to_expFracPreRnd_uid71_uid71_fpCosPiTest_1_q & fracRCompPreRnd_uid70_fpCosPiTest_q;
--expFracComp_uid74_fpCosPiTest(ADD,73)@16
expFracComp_uid74_fpCosPiTest_a <= STD_LOGIC_VECTOR("0" & expFracPreRnd_uid71_uid71_fpCosPiTest_q);
expFracComp_uid74_fpCosPiTest_b <= STD_LOGIC_VECTOR("00000000" & rndExpUpdate_uid72_uid73_fpCosPiTest_q);
expFracComp_uid74_fpCosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expFracComp_uid74_fpCosPiTest_a) + UNSIGNED(expFracComp_uid74_fpCosPiTest_b));
expFracComp_uid74_fpCosPiTest_q <= expFracComp_uid74_fpCosPiTest_o(32 downto 0);
--expRComp_uid76_fpCosPiTest(BITSELECT,75)@16
expRComp_uid76_fpCosPiTest_in <= expFracComp_uid74_fpCosPiTest_q(31 downto 0);
expRComp_uid76_fpCosPiTest_b <= expRComp_uid76_fpCosPiTest_in(31 downto 24);
--fracXIsZero_uid27_fpCosPiTest(LOGICAL,26)@0
fracXIsZero_uid27_fpCosPiTest_a <= fracX_uid7_fpCosPiTest_b;
fracXIsZero_uid27_fpCosPiTest_b <= cstAllZWF_uid9_fpCosPiTest_q;
fracXIsZero_uid27_fpCosPiTest_q <= "1" when fracXIsZero_uid27_fpCosPiTest_a = fracXIsZero_uid27_fpCosPiTest_b else "0";
--InvFracXIsZero_uid29_fpCosPiTest(LOGICAL,28)@0
InvFracXIsZero_uid29_fpCosPiTest_a <= fracXIsZero_uid27_fpCosPiTest_q;
InvFracXIsZero_uid29_fpCosPiTest_q <= not InvFracXIsZero_uid29_fpCosPiTest_a;
--expXIsMax_uid25_fpCosPiTest(LOGICAL,24)@0
expXIsMax_uid25_fpCosPiTest_a <= expX_uid6_fpCosPiTest_b;
expXIsMax_uid25_fpCosPiTest_b <= cstAllOWE_uid8_fpCosPiTest_q;
expXIsMax_uid25_fpCosPiTest_q <= "1" when expXIsMax_uid25_fpCosPiTest_a = expXIsMax_uid25_fpCosPiTest_b else "0";
--exc_N_uid30_fpCosPiTest(LOGICAL,29)@0
exc_N_uid30_fpCosPiTest_a <= expXIsMax_uid25_fpCosPiTest_q;
exc_N_uid30_fpCosPiTest_b <= InvFracXIsZero_uid29_fpCosPiTest_q;
exc_N_uid30_fpCosPiTest_q <= exc_N_uid30_fpCosPiTest_a and exc_N_uid30_fpCosPiTest_b;
--InvExc_N_uid31_fpCosPiTest(LOGICAL,30)@0
InvExc_N_uid31_fpCosPiTest_a <= exc_N_uid30_fpCosPiTest_q;
InvExc_N_uid31_fpCosPiTest_q <= not InvExc_N_uid31_fpCosPiTest_a;
--exc_I_uid28_fpCosPiTest(LOGICAL,27)@0
exc_I_uid28_fpCosPiTest_a <= expXIsMax_uid25_fpCosPiTest_q;
exc_I_uid28_fpCosPiTest_b <= fracXIsZero_uid27_fpCosPiTest_q;
exc_I_uid28_fpCosPiTest_q <= exc_I_uid28_fpCosPiTest_a and exc_I_uid28_fpCosPiTest_b;
--InvExc_I_uid32_fpCosPiTest(LOGICAL,31)@0
InvExc_I_uid32_fpCosPiTest_a <= exc_I_uid28_fpCosPiTest_q;
InvExc_I_uid32_fpCosPiTest_q <= not InvExc_I_uid32_fpCosPiTest_a;
--expXIsZero_uid23_fpCosPiTest(LOGICAL,22)@0
expXIsZero_uid23_fpCosPiTest_a <= expX_uid6_fpCosPiTest_b;
expXIsZero_uid23_fpCosPiTest_b <= cstAllZWE_uid21_fpCosPiTest_q;
expXIsZero_uid23_fpCosPiTest_q <= "1" when expXIsZero_uid23_fpCosPiTest_a = expXIsZero_uid23_fpCosPiTest_b else "0";
--InvExpXIsZero_uid33_fpCosPiTest(LOGICAL,32)@0
InvExpXIsZero_uid33_fpCosPiTest_a <= expXIsZero_uid23_fpCosPiTest_q;
InvExpXIsZero_uid33_fpCosPiTest_q <= not InvExpXIsZero_uid33_fpCosPiTest_a;
--exc_R_uid34_fpCosPiTest(LOGICAL,33)@0
exc_R_uid34_fpCosPiTest_a <= InvExpXIsZero_uid33_fpCosPiTest_q;
exc_R_uid34_fpCosPiTest_b <= InvExc_I_uid32_fpCosPiTest_q;
exc_R_uid34_fpCosPiTest_c <= InvExc_N_uid31_fpCosPiTest_q;
exc_R_uid34_fpCosPiTest_q <= exc_R_uid34_fpCosPiTest_a and exc_R_uid34_fpCosPiTest_b and exc_R_uid34_fpCosPiTest_c;
--ld_exc_R_uid34_fpCosPiTest_q_to_xIsInt_uid80_fpCosPiTest_a(DELAY,337)@0
ld_exc_R_uid34_fpCosPiTest_q_to_xIsInt_uid80_fpCosPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => exc_R_uid34_fpCosPiTest_q, xout => ld_exc_R_uid34_fpCosPiTest_q_to_xIsInt_uid80_fpCosPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--xIsHalf_uid83_fpCosPiTest(LOGICAL,82)@2
xIsHalf_uid83_fpCosPiTest_a <= ld_exc_R_uid34_fpCosPiTest_q_to_xIsInt_uid80_fpCosPiTest_a_q;
xIsHalf_uid83_fpCosPiTest_b <= fxpXFracHalf_uid46_fpCosPiTest_q;
xIsHalf_uid83_fpCosPiTest_c <= InvCosXIsOne_uid77_fpCosPiTest_q;
xIsHalf_uid83_fpCosPiTest_d <= InvXEvenInt_uid81_fpCosPiTest_q;
xIsHalf_uid83_fpCosPiTest_q <= xIsHalf_uid83_fpCosPiTest_a and xIsHalf_uid83_fpCosPiTest_b and xIsHalf_uid83_fpCosPiTest_c and xIsHalf_uid83_fpCosPiTest_d;
--ld_xIsHalf_uid83_fpCosPiTest_q_to_expRPostExc1_uid91_fpCosPiTest_b(DELAY,355)@2
ld_xIsHalf_uid83_fpCosPiTest_q_to_expRPostExc1_uid91_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 14 )
PORT MAP ( xin => xIsHalf_uid83_fpCosPiTest_q, xout => ld_xIsHalf_uid83_fpCosPiTest_q_to_expRPostExc1_uid91_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--expRPostExc1_uid91_fpCosPiTest(MUX,90)@16
expRPostExc1_uid91_fpCosPiTest_s <= ld_xIsHalf_uid83_fpCosPiTest_q_to_expRPostExc1_uid91_fpCosPiTest_b_q;
expRPostExc1_uid91_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expRPostExc1_uid91_fpCosPiTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE expRPostExc1_uid91_fpCosPiTest_s IS
WHEN "0" => expRPostExc1_uid91_fpCosPiTest_q <= expRComp_uid76_fpCosPiTest_b;
WHEN "1" => expRPostExc1_uid91_fpCosPiTest_q <= cstAllZWE_uid21_fpCosPiTest_q;
WHEN OTHERS => expRPostExc1_uid91_fpCosPiTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_nor(LOGICAL,570)
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_nor_a <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_notEnable_q;
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_nor_b <= ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_sticky_ena_q;
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_nor_q <= not (ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_nor_a or ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_nor_b);
--ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_mem_top(CONSTANT,566)
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_mem_top_q <= "01100";
--ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_cmp(LOGICAL,567)
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_cmp_a <= ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_mem_top_q;
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdmux_q);
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_cmp_q <= "1" when ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_cmp_a = ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_cmp_b else "0";
--ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_cmpReg(REG,568)
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_cmpReg_q <= ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_sticky_ena(REG,571)
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_nor_q = "1") THEN
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_sticky_ena_q <= ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_enaAnd(LOGICAL,572)
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_enaAnd_a <= ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_sticky_ena_q;
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_enaAnd_b <= en;
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_enaAnd_q <= ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_enaAnd_a and ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_enaAnd_b;
--ld_expXIsZero_uid23_fpCosPiTest_q_to_xIntOrXZOrCosOne_uid93_fpCosPiTest_b(DELAY,359)@0
ld_expXIsZero_uid23_fpCosPiTest_q_to_xIntOrXZOrCosOne_uid93_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => expXIsZero_uid23_fpCosPiTest_q, xout => ld_expXIsZero_uid23_fpCosPiTest_q_to_xIntOrXZOrCosOne_uid93_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--fxpXFracZero_uid45_fpCosPiTest(LOGICAL,44)@2
fxpXFracZero_uid45_fpCosPiTest_a <= reg_fxpXFrac_uid43_fpCosPiTest_0_to_fxpXFracZero_uid45_fpCosPiTest_1_q;
fxpXFracZero_uid45_fpCosPiTest_b <= STD_LOGIC_VECTOR("0" & cstZwSwF_uid15_fpCosPiTest_q);
fxpXFracZero_uid45_fpCosPiTest_q <= "1" when fxpXFracZero_uid45_fpCosPiTest_a = fxpXFracZero_uid45_fpCosPiTest_b else "0";
--fracZCosNotOne_uid78_fpCosPiTest(LOGICAL,77)@2
fracZCosNotOne_uid78_fpCosPiTest_a <= fxpXFracZero_uid45_fpCosPiTest_q;
fracZCosNotOne_uid78_fpCosPiTest_b <= InvCosXIsOne_uid77_fpCosPiTest_q;
fracZCosNotOne_uid78_fpCosPiTest_q <= fracZCosNotOne_uid78_fpCosPiTest_a and fracZCosNotOne_uid78_fpCosPiTest_b;
--evenIntCosNotOneFZ_uid79_fpCosPiTest(LOGICAL,78)@2
evenIntCosNotOneFZ_uid79_fpCosPiTest_a <= ld_xEvenInt_uid35_fpCosPiTest_c_to_evenIntCosNotOneFZ_uid79_fpCosPiTest_a_q;
evenIntCosNotOneFZ_uid79_fpCosPiTest_b <= fracZCosNotOne_uid78_fpCosPiTest_q;
evenIntCosNotOneFZ_uid79_fpCosPiTest_q <= evenIntCosNotOneFZ_uid79_fpCosPiTest_a or evenIntCosNotOneFZ_uid79_fpCosPiTest_b;
--xIsInt_uid80_fpCosPiTest(LOGICAL,79)@2
xIsInt_uid80_fpCosPiTest_a <= ld_exc_R_uid34_fpCosPiTest_q_to_xIsInt_uid80_fpCosPiTest_a_q;
xIsInt_uid80_fpCosPiTest_b <= evenIntCosNotOneFZ_uid79_fpCosPiTest_q;
xIsInt_uid80_fpCosPiTest_q <= xIsInt_uid80_fpCosPiTest_a and xIsInt_uid80_fpCosPiTest_b;
--xIntOrXZOrCosOne_uid93_fpCosPiTest(LOGICAL,92)@2
xIntOrXZOrCosOne_uid93_fpCosPiTest_a <= xIsInt_uid80_fpCosPiTest_q;
xIntOrXZOrCosOne_uid93_fpCosPiTest_b <= ld_expXIsZero_uid23_fpCosPiTest_q_to_xIntOrXZOrCosOne_uid93_fpCosPiTest_b_q;
xIntOrXZOrCosOne_uid93_fpCosPiTest_c <= ld_cosXIsOne_uid36_fpCosPiTest_c_to_InvCosXIsOne_uid77_fpCosPiTest_a_q;
xIntOrXZOrCosOne_uid93_fpCosPiTest_q <= xIntOrXZOrCosOne_uid93_fpCosPiTest_a or xIntOrXZOrCosOne_uid93_fpCosPiTest_b or xIntOrXZOrCosOne_uid93_fpCosPiTest_c;
--excRNaN_uid84_fpCosPiTest(LOGICAL,83)@0
excRNaN_uid84_fpCosPiTest_a <= exc_N_uid30_fpCosPiTest_q;
excRNaN_uid84_fpCosPiTest_b <= exc_I_uid28_fpCosPiTest_q;
excRNaN_uid84_fpCosPiTest_q <= excRNaN_uid84_fpCosPiTest_a or excRNaN_uid84_fpCosPiTest_b;
--rInfOrNaN_uid92_fpCosPiTest(LOGICAL,91)@0
rInfOrNaN_uid92_fpCosPiTest_a <= GND_q;
rInfOrNaN_uid92_fpCosPiTest_b <= excRNaN_uid84_fpCosPiTest_q;
rInfOrNaN_uid92_fpCosPiTest_q <= rInfOrNaN_uid92_fpCosPiTest_a or rInfOrNaN_uid92_fpCosPiTest_b;
--ld_rInfOrNaN_uid92_fpCosPiTest_q_to_join_uid94_fpCosPiTest_a(DELAY,361)@0
ld_rInfOrNaN_uid92_fpCosPiTest_q_to_join_uid94_fpCosPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => rInfOrNaN_uid92_fpCosPiTest_q, xout => ld_rInfOrNaN_uid92_fpCosPiTest_q_to_join_uid94_fpCosPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--join_uid94_fpCosPiTest(BITJOIN,93)@2
join_uid94_fpCosPiTest_q <= xIntOrXZOrCosOne_uid93_fpCosPiTest_q & ld_rInfOrNaN_uid92_fpCosPiTest_q_to_join_uid94_fpCosPiTest_a_q;
--reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1(REG,274)@2
reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q <= join_uid94_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt(COUNTER,562)
-- every=1, low=0, high=12, step=1, init=1
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt_i = 11 THEN
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt_eq <= '1';
ELSE
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt_eq = '1') THEN
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt_i <= ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt_i - 12;
ELSE
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt_i <= ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt_i,4));
--ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdreg(REG,563)
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdreg_q <= ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdmux(MUX,564)
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdmux_s <= en;
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdmux: PROCESS (ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdmux_s, ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdreg_q, ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt_q)
BEGIN
CASE ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdmux_s IS
WHEN "0" => ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdmux_q <= ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdreg_q;
WHEN "1" => ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdmux_q <= ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem(DUALMEM,561)
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_reset0 <= areset;
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_ia <= reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q;
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_aa <= ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdreg_q;
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_ab <= ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdmux_q;
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 2,
widthad_a => 4,
numwords_a => 13,
width_b => 2,
widthad_b => 4,
numwords_b => 13,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_iq,
address_a => ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_aa,
data_a => ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_ia
);
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_q <= ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_iq(1 downto 0);
--expRPostExc_uid95_fpCosPiTest(MUX,94)@17
expRPostExc_uid95_fpCosPiTest_s <= ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_q;
expRPostExc_uid95_fpCosPiTest: PROCESS (expRPostExc_uid95_fpCosPiTest_s, en, expRPostExc1_uid91_fpCosPiTest_q, cstAllOWE_uid8_fpCosPiTest_q, cstBias_uid10_fpCosPiTest_q, cstBias_uid10_fpCosPiTest_q)
BEGIN
CASE expRPostExc_uid95_fpCosPiTest_s IS
WHEN "00" => expRPostExc_uid95_fpCosPiTest_q <= expRPostExc1_uid91_fpCosPiTest_q;
WHEN "01" => expRPostExc_uid95_fpCosPiTest_q <= cstAllOWE_uid8_fpCosPiTest_q;
WHEN "10" => expRPostExc_uid95_fpCosPiTest_q <= cstBias_uid10_fpCosPiTest_q;
WHEN "11" => expRPostExc_uid95_fpCosPiTest_q <= cstBias_uid10_fpCosPiTest_q;
WHEN OTHERS => expRPostExc_uid95_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--oneFracRPostExc2_uid87_fpCosPiTest(CONSTANT,86)
oneFracRPostExc2_uid87_fpCosPiTest_q <= "00000000000000000000001";
--fracRComp_uid75_fpCosPiTest(BITSELECT,74)@16
fracRComp_uid75_fpCosPiTest_in <= expFracComp_uid74_fpCosPiTest_q(23 downto 0);
fracRComp_uid75_fpCosPiTest_b <= fracRComp_uid75_fpCosPiTest_in(23 downto 1);
--reg_xIsHalf_uid83_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_5(REG,243)@2
reg_xIsHalf_uid83_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xIsHalf_uid83_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_5_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xIsHalf_uid83_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_5_q <= xIsHalf_uid83_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--reg_expXIsZero_uid23_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_4(REG,242)@2
reg_expXIsZero_uid23_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expXIsZero_uid23_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_4_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expXIsZero_uid23_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_4_q <= ld_expXIsZero_uid23_fpCosPiTest_q_to_xIntOrXZOrCosOne_uid93_fpCosPiTest_b_q;
END IF;
END IF;
END PROCESS;
--reg_fxpXFracHalf_uid46_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_3(REG,241)@2
reg_fxpXFracHalf_uid46_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fxpXFracHalf_uid46_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_3_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fxpXFracHalf_uid46_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_3_q <= fxpXFracHalf_uid46_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--reg_xIsInt_uid80_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_2(REG,240)@2
reg_xIsInt_uid80_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xIsInt_uid80_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xIsInt_uid80_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_2_q <= xIsInt_uid80_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--reg_cosXIsOne_uid36_fpCosPiTest_1_to_bigCond_uid85_fpCosPiTest_1(REG,239)@0
reg_cosXIsOne_uid36_fpCosPiTest_1_to_bigCond_uid85_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cosXIsOne_uid36_fpCosPiTest_1_to_bigCond_uid85_fpCosPiTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cosXIsOne_uid36_fpCosPiTest_1_to_bigCond_uid85_fpCosPiTest_1_q <= cosXIsOne_uid36_fpCosPiTest_c;
END IF;
END IF;
END PROCESS;
--ld_reg_cosXIsOne_uid36_fpCosPiTest_1_to_bigCond_uid85_fpCosPiTest_1_q_to_bigCond_uid85_fpCosPiTest_a(DELAY,346)@1
ld_reg_cosXIsOne_uid36_fpCosPiTest_1_to_bigCond_uid85_fpCosPiTest_1_q_to_bigCond_uid85_fpCosPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => reg_cosXIsOne_uid36_fpCosPiTest_1_to_bigCond_uid85_fpCosPiTest_1_q, xout => ld_reg_cosXIsOne_uid36_fpCosPiTest_1_to_bigCond_uid85_fpCosPiTest_1_q_to_bigCond_uid85_fpCosPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--bigCond_uid85_fpCosPiTest(LOGICAL,84)@3
bigCond_uid85_fpCosPiTest_a <= ld_reg_cosXIsOne_uid36_fpCosPiTest_1_to_bigCond_uid85_fpCosPiTest_1_q_to_bigCond_uid85_fpCosPiTest_a_q;
bigCond_uid85_fpCosPiTest_b <= reg_xIsInt_uid80_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_2_q;
bigCond_uid85_fpCosPiTest_c <= reg_fxpXFracHalf_uid46_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_3_q;
bigCond_uid85_fpCosPiTest_d <= reg_expXIsZero_uid23_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_4_q;
bigCond_uid85_fpCosPiTest_f <= reg_xIsHalf_uid83_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_5_q;
bigCond_uid85_fpCosPiTest_g <= GND_q;
bigCond_uid85_fpCosPiTest_q <= bigCond_uid85_fpCosPiTest_a or bigCond_uid85_fpCosPiTest_b or bigCond_uid85_fpCosPiTest_c or bigCond_uid85_fpCosPiTest_d or bigCond_uid85_fpCosPiTest_f or bigCond_uid85_fpCosPiTest_g;
--ld_bigCond_uid85_fpCosPiTest_q_to_fracRPostExc1_uid86_fpCosPiTest_b(DELAY,351)@3
ld_bigCond_uid85_fpCosPiTest_q_to_fracRPostExc1_uid86_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 13 )
PORT MAP ( xin => bigCond_uid85_fpCosPiTest_q, xout => ld_bigCond_uid85_fpCosPiTest_q_to_fracRPostExc1_uid86_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--fracRPostExc1_uid86_fpCosPiTest(MUX,85)@16
fracRPostExc1_uid86_fpCosPiTest_s <= ld_bigCond_uid85_fpCosPiTest_q_to_fracRPostExc1_uid86_fpCosPiTest_b_q;
fracRPostExc1_uid86_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
fracRPostExc1_uid86_fpCosPiTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE fracRPostExc1_uid86_fpCosPiTest_s IS
WHEN "0" => fracRPostExc1_uid86_fpCosPiTest_q <= fracRComp_uid75_fpCosPiTest_b;
WHEN "1" => fracRPostExc1_uid86_fpCosPiTest_q <= cstAllZWF_uid9_fpCosPiTest_q;
WHEN OTHERS => fracRPostExc1_uid86_fpCosPiTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--reg_excRNaN_uid84_fpCosPiTest_0_to_fracRPostExc_uid88_fpCosPiTest_1(REG,273)@0
reg_excRNaN_uid84_fpCosPiTest_0_to_fracRPostExc_uid88_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_excRNaN_uid84_fpCosPiTest_0_to_fracRPostExc_uid88_fpCosPiTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_excRNaN_uid84_fpCosPiTest_0_to_fracRPostExc_uid88_fpCosPiTest_1_q <= excRNaN_uid84_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_excRNaN_uid84_fpCosPiTest_0_to_fracRPostExc_uid88_fpCosPiTest_1_q_to_fracRPostExc_uid88_fpCosPiTest_b(DELAY,353)@1
ld_reg_excRNaN_uid84_fpCosPiTest_0_to_fracRPostExc_uid88_fpCosPiTest_1_q_to_fracRPostExc_uid88_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 16 )
PORT MAP ( xin => reg_excRNaN_uid84_fpCosPiTest_0_to_fracRPostExc_uid88_fpCosPiTest_1_q, xout => ld_reg_excRNaN_uid84_fpCosPiTest_0_to_fracRPostExc_uid88_fpCosPiTest_1_q_to_fracRPostExc_uid88_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--fracRPostExc_uid88_fpCosPiTest(MUX,87)@17
fracRPostExc_uid88_fpCosPiTest_s <= ld_reg_excRNaN_uid84_fpCosPiTest_0_to_fracRPostExc_uid88_fpCosPiTest_1_q_to_fracRPostExc_uid88_fpCosPiTest_b_q;
fracRPostExc_uid88_fpCosPiTest: PROCESS (fracRPostExc_uid88_fpCosPiTest_s, en, fracRPostExc1_uid86_fpCosPiTest_q, oneFracRPostExc2_uid87_fpCosPiTest_q)
BEGIN
CASE fracRPostExc_uid88_fpCosPiTest_s IS
WHEN "0" => fracRPostExc_uid88_fpCosPiTest_q <= fracRPostExc1_uid86_fpCosPiTest_q;
WHEN "1" => fracRPostExc_uid88_fpCosPiTest_q <= oneFracRPostExc2_uid87_fpCosPiTest_q;
WHEN OTHERS => fracRPostExc_uid88_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--R_uid102_fpCosPiTest(BITJOIN,101)@17
R_uid102_fpCosPiTest_q <= ld_signR_uid101_fpCosPiTest_q_to_R_uid102_fpCosPiTest_c_q & expRPostExc_uid95_fpCosPiTest_q & fracRPostExc_uid88_fpCosPiTest_q;
--xOut(GPOUT,4)@17
q <= R_uid102_fpCosPiTest_q;
end normal;
|
-----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Release Version 13.1
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing device programming or simulation files), and
-- any associated documentation or information are expressly subject to the
-- terms and conditions of the Altera Program License Subscription Agreement,
-- Altera MegaCore Function License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for the sole
-- purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
-----------------------------------------------------------------------------
-- VHDL created from fp_cospi_s5
-- VHDL created on Wed Feb 27 15:22:33 2013
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.all;
use std.TextIO.all;
use work.dspba_library_package.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
entity fp_cospi_s5 is
port (
a : in std_logic_vector(31 downto 0);
en : in std_logic_vector(0 downto 0);
q : out std_logic_vector(31 downto 0);
clk : in std_logic;
areset : in std_logic
);
end;
architecture normal of fp_cospi_s5 is
attribute altera_attribute : string;
attribute altera_attribute of normal : architecture is "-name NOT_GATE_PUSH_BACK OFF; -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON; -name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410";
signal GND_q : std_logic_vector (0 downto 0);
signal VCC_q : std_logic_vector (0 downto 0);
signal cstAllOWE_uid8_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal cstAllZWF_uid9_fpCosPiTest_q : std_logic_vector (22 downto 0);
signal cstBias_uid10_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal cstBiasM1_uid11_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal cstBiasPwF_uid12_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal biasMwShiftMO_uid13_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal cst01pWShift_uid14_fpCosPiTest_q : std_logic_vector (12 downto 0);
signal cstZwSwF_uid15_fpCosPiTest_q : std_logic_vector (34 downto 0);
signal cstAllZWE_uid21_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal rangeReducedFxPX_uid51_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal rangeReducedFxPX_uid51_fpCosPiTest_q : std_logic_vector (35 downto 0);
signal fracRPostExc1_uid86_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal fracRPostExc1_uid86_fpCosPiTest_q : std_logic_vector (22 downto 0);
signal oneFracRPostExc2_uid87_fpCosPiTest_q : std_logic_vector (22 downto 0);
signal expRPostExc1_uid91_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal expRPostExc1_uid91_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal signRComp_uid99_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal signRComp_uid99_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal signRComp_uid99_fpCosPiTest_c : std_logic_vector(0 downto 0);
signal signRComp_uid99_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal signR_uid101_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal signR_uid101_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal signR_uid101_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal leftShiftStage0Idx1Pad16_uid105_fxpX_uid41_fpCosPiTest_q : std_logic_vector (15 downto 0);
signal leftShiftStage0Idx2Pad32_uid108_fxpX_uid41_fpCosPiTest_q : std_logic_vector (31 downto 0);
signal leftShiftStage0Idx3_uid111_fxpX_uid41_fpCosPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage1Idx1Pad4_uid114_fxpX_uid41_fpCosPiTest_q : std_logic_vector (3 downto 0);
signal leftShiftStage1Idx3Pad12_uid120_fxpX_uid41_fpCosPiTest_q : std_logic_vector (11 downto 0);
signal leftShiftStage2Idx2Pad2_uid128_fxpX_uid41_fpCosPiTest_q : std_logic_vector (1 downto 0);
signal leftShiftStage2Idx3Pad3_uid131_fxpX_uid41_fpCosPiTest_q : std_logic_vector (2 downto 0);
signal mO_uid140_lzcZ_uid56_fpCosPiTest_q : std_logic_vector (28 downto 0);
signal memoryC2_uid209_sinPiZTableGenerator_q : std_logic_vector(13 downto 0);
signal prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_a : std_logic_vector (23 downto 0);
signal prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_b : std_logic_vector (24 downto 0);
signal prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_s1 : std_logic_vector (48 downto 0);
signal prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_pr : UNSIGNED (48 downto 0);
signal prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_q : std_logic_vector (48 downto 0);
signal prodXY_uid226_pT1_uid211_sinPiZPolyEval_a : std_logic_vector (13 downto 0);
signal prodXY_uid226_pT1_uid211_sinPiZPolyEval_b : std_logic_vector (13 downto 0);
signal prodXY_uid226_pT1_uid211_sinPiZPolyEval_s1 : std_logic_vector (27 downto 0);
signal prodXY_uid226_pT1_uid211_sinPiZPolyEval_pr : SIGNED (28 downto 0);
signal prodXY_uid226_pT1_uid211_sinPiZPolyEval_q : std_logic_vector (27 downto 0);
signal prodXY_uid229_pT2_uid217_sinPiZPolyEval_a : std_logic_vector (15 downto 0);
signal prodXY_uid229_pT2_uid217_sinPiZPolyEval_b : std_logic_vector (22 downto 0);
signal prodXY_uid229_pT2_uid217_sinPiZPolyEval_s1 : std_logic_vector (38 downto 0);
signal prodXY_uid229_pT2_uid217_sinPiZPolyEval_pr : SIGNED (39 downto 0);
signal prodXY_uid229_pT2_uid217_sinPiZPolyEval_q : std_logic_vector (38 downto 0);
signal reg_leftShiftStageSel3Dto2_uid123_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_2_q : std_logic_vector (36 downto 0);
signal reg_leftShiftStage1Idx1_uid116_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_3_q : std_logic_vector (36 downto 0);
signal reg_leftShiftStage1Idx2_uid119_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_4_q : std_logic_vector (36 downto 0);
signal reg_leftShiftStage1Idx3_uid122_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_5_q : std_logic_vector (36 downto 0);
signal reg_leftShiftStageSel1Dto0_uid134_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_fxpXFrac_uid43_fpCosPiTest_0_to_fxpXFracZero_uid45_fpCosPiTest_1_q : std_logic_vector (35 downto 0);
signal reg_cosXIsOne_uid36_fpCosPiTest_1_to_bigCond_uid85_fpCosPiTest_1_q : std_logic_vector (0 downto 0);
signal reg_xIsInt_uid80_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_2_q : std_logic_vector (0 downto 0);
signal reg_fxpXFracHalf_uid46_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_3_q : std_logic_vector (0 downto 0);
signal reg_expXIsZero_uid23_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_4_q : std_logic_vector (0 downto 0);
signal reg_xIsHalf_uid83_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_5_q : std_logic_vector (0 downto 0);
signal reg_pad_o_uid16_uid47_fpCosPiTest_0_to_oMFxpXFrac_uid47_fpCosPiTest_0_q : std_logic_vector (36 downto 0);
signal reg_pad_half_uid17_uid52_fpCosPiTest_0_to_z_halfMRRFxPXE_uid52_fpCosPiTest_0_q : std_logic_vector (35 downto 0);
signal reg_rVStage_uid138_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid139_lzcZ_uid56_fpCosPiTest_1_q : std_logic_vector (31 downto 0);
signal reg_cStage_uid142_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid144_lzcZ_uid56_fpCosPiTest_3_q : std_logic_vector (31 downto 0);
signal reg_rVStage_uid146_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid147_lzcZ_uid56_fpCosPiTest_1_q : std_logic_vector (15 downto 0);
signal reg_vStage_uid148_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid150_lzcZ_uid56_fpCosPiTest_3_q : std_logic_vector (15 downto 0);
signal reg_rVStage_uid158_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid159_lzcZ_uid56_fpCosPiTest_1_q : std_logic_vector (3 downto 0);
signal reg_vStage_uid160_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid162_lzcZ_uid56_fpCosPiTest_3_q : std_logic_vector (3 downto 0);
signal reg_vCount_uid153_lzcZ_uid56_fpCosPiTest_0_to_r_uid172_lzcZ_uid56_fpCosPiTest_3_q : std_logic_vector (0 downto 0);
signal reg_leftShiftStageSel3Dto2_uid193_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_2_q : std_logic_vector (34 downto 0);
signal reg_leftShiftStage1Idx1_uid186_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_3_q : std_logic_vector (34 downto 0);
signal reg_leftShiftStage1Idx2_uid189_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_4_q : std_logic_vector (34 downto 0);
signal reg_leftShiftStage1Idx3_uid192_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_5_q : std_logic_vector (34 downto 0);
signal reg_leftShiftStageSel1Dto0_uid204_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_zAddr_uid62_fpCosPiTest_0_to_memoryC2_uid209_sinPiZTableGenerator_0_q : std_logic_vector (6 downto 0);
signal reg_yT1_uid210_sinPiZPolyEval_0_to_prodXY_uid226_pT1_uid211_sinPiZPolyEval_0_q : std_logic_vector (13 downto 0);
signal reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_q : std_logic_vector (15 downto 0);
signal reg_s1_uid212_uid215_sinPiZPolyEval_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_1_q : std_logic_vector (22 downto 0);
signal reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_q : std_logic_vector (23 downto 0);
signal reg_fxpSinRes_uid65_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_1_q : std_logic_vector (24 downto 0);
signal reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q : std_logic_vector (5 downto 0);
signal reg_expP_uid60_fpCosPiTest_0_to_expFracPreRnd_uid71_uid71_fpCosPiTest_1_q : std_logic_vector (7 downto 0);
signal reg_excRNaN_uid84_fpCosPiTest_0_to_fracRPostExc_uid88_fpCosPiTest_1_q : std_logic_vector (0 downto 0);
signal reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q : std_logic_vector (1 downto 0);
signal ld_FxpXFrac35_uid44_fpCosPiTest_b_to_rangeReducedFxPX_uid51_fpCosPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_fxpXFrac_uid43_fpCosPiTest_b_to_rangeReducedFxPX_uid51_fpCosPiTest_c_q : std_logic_vector (35 downto 0);
signal ld_cosXIsOne_uid36_fpCosPiTest_c_to_InvCosXIsOne_uid77_fpCosPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_xEvenInt_uid35_fpCosPiTest_c_to_evenIntCosNotOneFZ_uid79_fpCosPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_exc_R_uid34_fpCosPiTest_q_to_xIsInt_uid80_fpCosPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_reg_cosXIsOne_uid36_fpCosPiTest_1_to_bigCond_uid85_fpCosPiTest_1_q_to_bigCond_uid85_fpCosPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_bigCond_uid85_fpCosPiTest_q_to_fracRPostExc1_uid86_fpCosPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_reg_excRNaN_uid84_fpCosPiTest_0_to_fracRPostExc_uid88_fpCosPiTest_1_q_to_fracRPostExc_uid88_fpCosPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_xIsHalf_uid83_fpCosPiTest_q_to_expRPostExc1_uid91_fpCosPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_expXIsZero_uid23_fpCosPiTest_q_to_xIntOrXZOrCosOne_uid93_fpCosPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_rInfOrNaN_uid92_fpCosPiTest_q_to_join_uid94_fpCosPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_xParityXorHalfParity_uid96_fpCosPiTest_q_to_signRComp_uid99_fpCosPiTest_c_q : std_logic_vector (0 downto 0);
signal ld_fxpXFracHalf_uid46_fpCosPiTest_q_to_InvFxpXFracHalf_uid100_fpCosPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_signR_uid101_fpCosPiTest_q_to_R_uid102_fpCosPiTest_c_q : std_logic_vector (0 downto 0);
signal ld_vCount_uid147_lzcZ_uid56_fpCosPiTest_q_to_r_uid172_lzcZ_uid56_fpCosPiTest_e_q : std_logic_vector (0 downto 0);
signal ld_vCount_uid139_lzcZ_uid56_fpCosPiTest_q_to_r_uid172_lzcZ_uid56_fpCosPiTest_f_q : std_logic_vector (0 downto 0);
signal ld_X18dto0_uid176_alignedZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx1_uid177_alignedZ_uid57_fpCosPiTest_b_q : std_logic_vector (18 downto 0);
signal ld_vStage_uid141_lzcZ_uid56_fpCosPiTest_b_to_leftShiftStage0Idx2_uid180_alignedZ_uid57_fpCosPiTest_b_q : std_logic_vector (2 downto 0);
signal ld_z_uid54_fpCosPiTest_b_to_leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_c_q : std_logic_vector (34 downto 0);
signal ld_reg_yT1_uid210_sinPiZPolyEval_0_to_prodXY_uid226_pT1_uid211_sinPiZPolyEval_0_q_to_prodXY_uid226_pT1_uid211_sinPiZPolyEval_a_q : std_logic_vector (13 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_reset0 : std_logic;
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_ia : std_logic_vector (5 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_iq : std_logic_vector (5 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_q : std_logic_vector (5 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt_eq : std_logic;
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_mem_top_q : std_logic_vector (3 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve : boolean;
attribute preserve of ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_sticky_ena_q : signal is true;
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_reset0 : std_logic;
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_ia : std_logic_vector (1 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_iq : std_logic_vector (1 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_q : std_logic_vector (1 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt_eq : std_logic;
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_mem_top_q : std_logic_vector (4 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_sticky_ena_q : signal is true;
signal ld_X18dto0_uid176_alignedZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx1_uid177_alignedZ_uid57_fpCosPiTest_b_inputreg_q : std_logic_vector (18 downto 0);
signal ld_z_uid54_fpCosPiTest_b_to_leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_c_inputreg_q : std_logic_vector (34 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_reset0 : std_logic;
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_ia : std_logic_vector (6 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_iq : std_logic_vector (6 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_q : std_logic_vector (6 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_sticky_ena_q : signal is true;
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_reset0 : std_logic;
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_ia : std_logic_vector (6 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_aa : std_logic_vector (1 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_ab : std_logic_vector (1 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_iq : std_logic_vector (6 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_q : std_logic_vector (6 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt_q : std_logic_vector(1 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt_i : unsigned(1 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt_eq : std_logic;
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdreg_q : std_logic_vector (1 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_mem_top_q : std_logic_vector (2 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_sticky_ena_q : signal is true;
signal ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_inputreg_q : std_logic_vector (15 downto 0);
signal ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_reset0 : std_logic;
signal ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_ia : std_logic_vector (15 downto 0);
signal ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_aa : std_logic_vector (1 downto 0);
signal ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_ab : std_logic_vector (1 downto 0);
signal ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_iq : std_logic_vector (15 downto 0);
signal ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_q : std_logic_vector (15 downto 0);
signal ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_sticky_ena_q : signal is true;
signal ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_inputreg_q : std_logic_vector (23 downto 0);
signal ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_reset0 : std_logic;
signal ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_ia : std_logic_vector (23 downto 0);
signal ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_aa : std_logic_vector (1 downto 0);
signal ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_ab : std_logic_vector (1 downto 0);
signal ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_iq : std_logic_vector (23 downto 0);
signal ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_q : std_logic_vector (23 downto 0);
signal ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_sticky_ena_q : signal is true;
signal pad_o_uid16_uid47_fpCosPiTest_q : std_logic_vector (36 downto 0);
signal pad_half_uid17_uid52_fpCosPiTest_q : std_logic_vector (35 downto 0);
signal bigCond_uid85_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal bigCond_uid85_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal bigCond_uid85_fpCosPiTest_c : std_logic_vector(0 downto 0);
signal bigCond_uid85_fpCosPiTest_d : std_logic_vector(0 downto 0);
signal bigCond_uid85_fpCosPiTest_f : std_logic_vector(0 downto 0);
signal bigCond_uid85_fpCosPiTest_g : std_logic_vector(0 downto 0);
signal bigCond_uid85_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal InvCosXIsOne_uid77_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal InvCosXIsOne_uid77_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal InvXEvenInt_uid81_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal InvXEvenInt_uid81_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal InvFxpXFracHalf_uid100_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal InvFxpXFracHalf_uid100_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal cstHalfwSwFP1_uid18_fpCosPiTest_q : std_logic_vector (35 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_notEnable_a : std_logic_vector(0 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_notEnable_q : std_logic_vector(0 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdmux_q : std_logic_vector (1 downto 0);
signal expX_uid6_fpCosPiTest_in : std_logic_vector (30 downto 0);
signal expX_uid6_fpCosPiTest_b : std_logic_vector (7 downto 0);
signal fracX_uid7_fpCosPiTest_in : std_logic_vector (22 downto 0);
signal fracX_uid7_fpCosPiTest_b : std_logic_vector (22 downto 0);
signal expXIsZero_uid23_fpCosPiTest_a : std_logic_vector(7 downto 0);
signal expXIsZero_uid23_fpCosPiTest_b : std_logic_vector(7 downto 0);
signal expXIsZero_uid23_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal expXIsMax_uid25_fpCosPiTest_a : std_logic_vector(7 downto 0);
signal expXIsMax_uid25_fpCosPiTest_b : std_logic_vector(7 downto 0);
signal expXIsMax_uid25_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal fracXIsZero_uid27_fpCosPiTest_a : std_logic_vector(22 downto 0);
signal fracXIsZero_uid27_fpCosPiTest_b : std_logic_vector(22 downto 0);
signal fracXIsZero_uid27_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal exc_I_uid28_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal exc_I_uid28_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal exc_I_uid28_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal xEvenInt_uid35_fpCosPiTest_a : std_logic_vector(10 downto 0);
signal xEvenInt_uid35_fpCosPiTest_b : std_logic_vector(10 downto 0);
signal xEvenInt_uid35_fpCosPiTest_o : std_logic_vector (10 downto 0);
signal xEvenInt_uid35_fpCosPiTest_cin : std_logic_vector (0 downto 0);
signal xEvenInt_uid35_fpCosPiTest_c : std_logic_vector (0 downto 0);
signal cosXIsOne_uid36_fpCosPiTest_a : std_logic_vector(10 downto 0);
signal cosXIsOne_uid36_fpCosPiTest_b : std_logic_vector(10 downto 0);
signal cosXIsOne_uid36_fpCosPiTest_o : std_logic_vector (10 downto 0);
signal cosXIsOne_uid36_fpCosPiTest_cin : std_logic_vector (0 downto 0);
signal cosXIsOne_uid36_fpCosPiTest_c : std_logic_vector (0 downto 0);
signal shiftValFxPX_uid38_fpCosPiTest_a : std_logic_vector(8 downto 0);
signal shiftValFxPX_uid38_fpCosPiTest_b : std_logic_vector(8 downto 0);
signal shiftValFxPX_uid38_fpCosPiTest_o : std_logic_vector (8 downto 0);
signal shiftValFxPX_uid38_fpCosPiTest_q : std_logic_vector (8 downto 0);
signal fxpXFracZero_uid45_fpCosPiTest_a : std_logic_vector(35 downto 0);
signal fxpXFracZero_uid45_fpCosPiTest_b : std_logic_vector(35 downto 0);
signal fxpXFracZero_uid45_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal fxpXFracHalf_uid46_fpCosPiTest_a : std_logic_vector(35 downto 0);
signal fxpXFracHalf_uid46_fpCosPiTest_b : std_logic_vector(35 downto 0);
signal fxpXFracHalf_uid46_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal oMFxpXFrac_uid47_fpCosPiTest_a : std_logic_vector(37 downto 0);
signal oMFxpXFrac_uid47_fpCosPiTest_b : std_logic_vector(37 downto 0);
signal oMFxpXFrac_uid47_fpCosPiTest_o : std_logic_vector (37 downto 0);
signal oMFxpXFrac_uid47_fpCosPiTest_q : std_logic_vector (37 downto 0);
signal z_halfMRRFxPXE_uid52_fpCosPiTest_a : std_logic_vector(36 downto 0);
signal z_halfMRRFxPXE_uid52_fpCosPiTest_b : std_logic_vector(36 downto 0);
signal z_halfMRRFxPXE_uid52_fpCosPiTest_o : std_logic_vector (36 downto 0);
signal z_halfMRRFxPXE_uid52_fpCosPiTest_q : std_logic_vector (36 downto 0);
signal expHardCase_uid59_fpCosPiTest_a : std_logic_vector(8 downto 0);
signal expHardCase_uid59_fpCosPiTest_b : std_logic_vector(8 downto 0);
signal expHardCase_uid59_fpCosPiTest_o : std_logic_vector (8 downto 0);
signal expHardCase_uid59_fpCosPiTest_q : std_logic_vector (8 downto 0);
signal fracZCosNotOne_uid78_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal fracZCosNotOne_uid78_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal fracZCosNotOne_uid78_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal evenIntCosNotOneFZ_uid79_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal evenIntCosNotOneFZ_uid79_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal evenIntCosNotOneFZ_uid79_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal xIsInt_uid80_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal xIsInt_uid80_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal xIsInt_uid80_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal xIsHalf_uid83_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal xIsHalf_uid83_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal xIsHalf_uid83_fpCosPiTest_c : std_logic_vector(0 downto 0);
signal xIsHalf_uid83_fpCosPiTest_d : std_logic_vector(0 downto 0);
signal xIsHalf_uid83_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal fracRPostExc_uid88_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal fracRPostExc_uid88_fpCosPiTest_q : std_logic_vector (22 downto 0);
signal xIntOrXZOrCosOne_uid93_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal xIntOrXZOrCosOne_uid93_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal xIntOrXZOrCosOne_uid93_fpCosPiTest_c : std_logic_vector(0 downto 0);
signal xIntOrXZOrCosOne_uid93_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal expRPostExc_uid95_fpCosPiTest_s : std_logic_vector (1 downto 0);
signal expRPostExc_uid95_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_q : std_logic_vector (36 downto 0);
signal vCount_uid139_lzcZ_uid56_fpCosPiTest_a : std_logic_vector(31 downto 0);
signal vCount_uid139_lzcZ_uid56_fpCosPiTest_b : std_logic_vector(31 downto 0);
signal vCount_uid139_lzcZ_uid56_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid144_lzcZ_uid56_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid144_lzcZ_uid56_fpCosPiTest_q : std_logic_vector (31 downto 0);
signal vCount_uid147_lzcZ_uid56_fpCosPiTest_a : std_logic_vector(15 downto 0);
signal vCount_uid147_lzcZ_uid56_fpCosPiTest_b : std_logic_vector(15 downto 0);
signal vCount_uid147_lzcZ_uid56_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid150_lzcZ_uid56_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid150_lzcZ_uid56_fpCosPiTest_q : std_logic_vector (15 downto 0);
signal vCount_uid159_lzcZ_uid56_fpCosPiTest_a : std_logic_vector(3 downto 0);
signal vCount_uid159_lzcZ_uid56_fpCosPiTest_b : std_logic_vector(3 downto 0);
signal vCount_uid159_lzcZ_uid56_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid162_lzcZ_uid56_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid162_lzcZ_uid56_fpCosPiTest_q : std_logic_vector (3 downto 0);
signal leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_q : std_logic_vector (34 downto 0);
signal memoryC0_uid207_sinPiZTableGenerator_q : std_logic_vector(28 downto 0);
signal memoryC1_uid208_sinPiZTableGenerator_q : std_logic_vector(20 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal leftShiftStage0Idx1_uid177_alignedZ_uid57_fpCosPiTest_q : std_logic_vector (34 downto 0);
signal leftShiftStage0Idx2_uid180_alignedZ_uid57_fpCosPiTest_q : std_logic_vector (34 downto 0);
signal prodXYTruncFR_uid224_mul2xSinRes_uid66_fpCosPiTest_in : std_logic_vector (48 downto 0);
signal prodXYTruncFR_uid224_mul2xSinRes_uid66_fpCosPiTest_b : std_logic_vector (25 downto 0);
signal prodXYTruncFR_uid227_pT1_uid211_sinPiZPolyEval_in : std_logic_vector (27 downto 0);
signal prodXYTruncFR_uid227_pT1_uid211_sinPiZPolyEval_b : std_logic_vector (14 downto 0);
signal prodXYTruncFR_uid230_pT2_uid217_sinPiZPolyEval_in : std_logic_vector (38 downto 0);
signal prodXYTruncFR_uid230_pT2_uid217_sinPiZPolyEval_b : std_logic_vector (23 downto 0);
signal join_uid94_fpCosPiTest_q : std_logic_vector (1 downto 0);
signal R_uid102_fpCosPiTest_q : std_logic_vector (31 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_cmp_a : std_logic_vector(3 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_cmp_b : std_logic_vector(3 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_cmp_a : std_logic_vector(4 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_cmp_b : std_logic_vector(4 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_cmp_a : std_logic_vector(2 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_cmp_b : std_logic_vector(2 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_nor_q : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_nor_q : std_logic_vector(0 downto 0);
signal oFracX_uid37_uid37_fpCosPiTest_q : std_logic_vector (23 downto 0);
signal InvExpXIsZero_uid33_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid33_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid29_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid29_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal InvExc_I_uid32_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal InvExc_I_uid32_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal fxpShifterBits_uid40_fpCosPiTest_in : std_logic_vector (5 downto 0);
signal fxpShifterBits_uid40_fpCosPiTest_b : std_logic_vector (5 downto 0);
signal oMFxpXFrac_uid49_fpCosPiTest_in : std_logic_vector (35 downto 0);
signal oMFxpXFrac_uid49_fpCosPiTest_b : std_logic_vector (35 downto 0);
signal z_uid54_fpCosPiTest_in : std_logic_vector (34 downto 0);
signal z_uid54_fpCosPiTest_b : std_logic_vector (34 downto 0);
signal expP_uid60_fpCosPiTest_in : std_logic_vector (7 downto 0);
signal expP_uid60_fpCosPiTest_b : std_logic_vector (7 downto 0);
signal LeftShiftStage135dto0_uid126_fxpX_uid41_fpCosPiTest_in : std_logic_vector (35 downto 0);
signal LeftShiftStage135dto0_uid126_fxpX_uid41_fpCosPiTest_b : std_logic_vector (35 downto 0);
signal LeftShiftStage134dto0_uid129_fxpX_uid41_fpCosPiTest_in : std_logic_vector (34 downto 0);
signal LeftShiftStage134dto0_uid129_fxpX_uid41_fpCosPiTest_b : std_logic_vector (34 downto 0);
signal LeftShiftStage133dto0_uid132_fxpX_uid41_fpCosPiTest_in : std_logic_vector (33 downto 0);
signal LeftShiftStage133dto0_uid132_fxpX_uid41_fpCosPiTest_b : std_logic_vector (33 downto 0);
signal rVStage_uid146_lzcZ_uid56_fpCosPiTest_in : std_logic_vector (31 downto 0);
signal rVStage_uid146_lzcZ_uid56_fpCosPiTest_b : std_logic_vector (15 downto 0);
signal vStage_uid148_lzcZ_uid56_fpCosPiTest_in : std_logic_vector (15 downto 0);
signal vStage_uid148_lzcZ_uid56_fpCosPiTest_b : std_logic_vector (15 downto 0);
signal rVStage_uid152_lzcZ_uid56_fpCosPiTest_in : std_logic_vector (15 downto 0);
signal rVStage_uid152_lzcZ_uid56_fpCosPiTest_b : std_logic_vector (7 downto 0);
signal vStage_uid154_lzcZ_uid56_fpCosPiTest_in : std_logic_vector (7 downto 0);
signal vStage_uid154_lzcZ_uid56_fpCosPiTest_b : std_logic_vector (7 downto 0);
signal rVStage_uid164_lzcZ_uid56_fpCosPiTest_in : std_logic_vector (3 downto 0);
signal rVStage_uid164_lzcZ_uid56_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal vStage_uid166_lzcZ_uid56_fpCosPiTest_in : std_logic_vector (1 downto 0);
signal vStage_uid166_lzcZ_uid56_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal LeftShiftStage133dto0_uid196_alignedZ_uid57_fpCosPiTest_in : std_logic_vector (33 downto 0);
signal LeftShiftStage133dto0_uid196_alignedZ_uid57_fpCosPiTest_b : std_logic_vector (33 downto 0);
signal LeftShiftStage132dto0_uid199_alignedZ_uid57_fpCosPiTest_in : std_logic_vector (32 downto 0);
signal LeftShiftStage132dto0_uid199_alignedZ_uid57_fpCosPiTest_b : std_logic_vector (32 downto 0);
signal LeftShiftStage131dto0_uid202_alignedZ_uid57_fpCosPiTest_in : std_logic_vector (31 downto 0);
signal LeftShiftStage131dto0_uid202_alignedZ_uid57_fpCosPiTest_b : std_logic_vector (31 downto 0);
signal normBit_uid67_fpCosPiTest_in : std_logic_vector (25 downto 0);
signal normBit_uid67_fpCosPiTest_b : std_logic_vector (0 downto 0);
signal highRes_uid68_fpCosPiTest_in : std_logic_vector (24 downto 0);
signal highRes_uid68_fpCosPiTest_b : std_logic_vector (23 downto 0);
signal lowRes_uid69_fpCosPiTest_in : std_logic_vector (23 downto 0);
signal lowRes_uid69_fpCosPiTest_b : std_logic_vector (23 downto 0);
signal lowRangeB_uid212_sinPiZPolyEval_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid212_sinPiZPolyEval_b : std_logic_vector (0 downto 0);
signal highBBits_uid213_sinPiZPolyEval_in : std_logic_vector (14 downto 0);
signal highBBits_uid213_sinPiZPolyEval_b : std_logic_vector (13 downto 0);
signal lowRangeB_uid218_sinPiZPolyEval_in : std_logic_vector (1 downto 0);
signal lowRangeB_uid218_sinPiZPolyEval_b : std_logic_vector (1 downto 0);
signal highBBits_uid219_sinPiZPolyEval_in : std_logic_vector (23 downto 0);
signal highBBits_uid219_sinPiZPolyEval_b : std_logic_vector (21 downto 0);
signal oFracXExt_uid39_fpCosPiTest_q : std_logic_vector (36 downto 0);
signal exc_N_uid30_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal exc_N_uid30_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal exc_N_uid30_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal leftShiftStageSel5Dto4_uid112_fxpX_uid41_fpCosPiTest_in : std_logic_vector (5 downto 0);
signal leftShiftStageSel5Dto4_uid112_fxpX_uid41_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel3Dto2_uid123_fxpX_uid41_fpCosPiTest_in : std_logic_vector (3 downto 0);
signal leftShiftStageSel3Dto2_uid123_fxpX_uid41_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid134_fxpX_uid41_fpCosPiTest_in : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid134_fxpX_uid41_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal zAddr_uid62_fpCosPiTest_in : std_logic_vector (34 downto 0);
signal zAddr_uid62_fpCosPiTest_b : std_logic_vector (6 downto 0);
signal zPPolyEval_uid63_fpCosPiTest_in : std_logic_vector (27 downto 0);
signal zPPolyEval_uid63_fpCosPiTest_b : std_logic_vector (15 downto 0);
signal rVStage_uid138_lzcZ_uid56_fpCosPiTest_in : std_logic_vector (34 downto 0);
signal rVStage_uid138_lzcZ_uid56_fpCosPiTest_b : std_logic_vector (31 downto 0);
signal vStage_uid141_lzcZ_uid56_fpCosPiTest_in : std_logic_vector (2 downto 0);
signal vStage_uid141_lzcZ_uid56_fpCosPiTest_b : std_logic_vector (2 downto 0);
signal X18dto0_uid176_alignedZ_uid57_fpCosPiTest_in : std_logic_vector (18 downto 0);
signal X18dto0_uid176_alignedZ_uid57_fpCosPiTest_b : std_logic_vector (18 downto 0);
signal leftShiftStage2Idx1_uid127_fxpX_uid41_fpCosPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage2Idx2_uid130_fxpX_uid41_fpCosPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage2Idx3_uid133_fxpX_uid41_fpCosPiTest_q : std_logic_vector (36 downto 0);
signal vCount_uid153_lzcZ_uid56_fpCosPiTest_a : std_logic_vector(7 downto 0);
signal vCount_uid153_lzcZ_uid56_fpCosPiTest_b : std_logic_vector(7 downto 0);
signal vCount_uid153_lzcZ_uid56_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid156_lzcZ_uid56_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid156_lzcZ_uid56_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal vCount_uid165_lzcZ_uid56_fpCosPiTest_a : std_logic_vector(1 downto 0);
signal vCount_uid165_lzcZ_uid56_fpCosPiTest_b : std_logic_vector(1 downto 0);
signal vCount_uid165_lzcZ_uid56_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid168_lzcZ_uid56_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid168_lzcZ_uid56_fpCosPiTest_q : std_logic_vector (1 downto 0);
signal leftShiftStage2Idx1_uid197_alignedZ_uid57_fpCosPiTest_q : std_logic_vector (34 downto 0);
signal leftShiftStage2Idx2_uid200_alignedZ_uid57_fpCosPiTest_q : std_logic_vector (34 downto 0);
signal leftShiftStage2Idx3_uid203_alignedZ_uid57_fpCosPiTest_q : std_logic_vector (34 downto 0);
signal fracRCompPreRnd_uid70_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal fracRCompPreRnd_uid70_fpCosPiTest_q : std_logic_vector (23 downto 0);
signal rndExpUpdate_uid72_uid73_fpCosPiTest_q : std_logic_vector (24 downto 0);
signal sumAHighB_uid214_sinPiZPolyEval_a : std_logic_vector(21 downto 0);
signal sumAHighB_uid214_sinPiZPolyEval_b : std_logic_vector(21 downto 0);
signal sumAHighB_uid214_sinPiZPolyEval_o : std_logic_vector (21 downto 0);
signal sumAHighB_uid214_sinPiZPolyEval_q : std_logic_vector (21 downto 0);
signal sumAHighB_uid220_sinPiZPolyEval_a : std_logic_vector(29 downto 0);
signal sumAHighB_uid220_sinPiZPolyEval_b : std_logic_vector(29 downto 0);
signal sumAHighB_uid220_sinPiZPolyEval_o : std_logic_vector (29 downto 0);
signal sumAHighB_uid220_sinPiZPolyEval_q : std_logic_vector (29 downto 0);
signal X20dto0_uid106_fxpX_uid41_fpCosPiTest_in : std_logic_vector (20 downto 0);
signal X20dto0_uid106_fxpX_uid41_fpCosPiTest_b : std_logic_vector (20 downto 0);
signal X4dto0_uid109_fxpX_uid41_fpCosPiTest_in : std_logic_vector (4 downto 0);
signal X4dto0_uid109_fxpX_uid41_fpCosPiTest_b : std_logic_vector (4 downto 0);
signal InvExc_N_uid31_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal InvExc_N_uid31_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal excRNaN_uid84_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal excRNaN_uid84_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal excRNaN_uid84_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal yT1_uid210_sinPiZPolyEval_in : std_logic_vector (15 downto 0);
signal yT1_uid210_sinPiZPolyEval_b : std_logic_vector (13 downto 0);
signal cStage_uid142_lzcZ_uid56_fpCosPiTest_q : std_logic_vector (31 downto 0);
signal leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest_q : std_logic_vector (36 downto 0);
signal rVStage_uid158_lzcZ_uid56_fpCosPiTest_in : std_logic_vector (7 downto 0);
signal rVStage_uid158_lzcZ_uid56_fpCosPiTest_b : std_logic_vector (3 downto 0);
signal vStage_uid160_lzcZ_uid56_fpCosPiTest_in : std_logic_vector (3 downto 0);
signal vStage_uid160_lzcZ_uid56_fpCosPiTest_b : std_logic_vector (3 downto 0);
signal rVStage_uid170_lzcZ_uid56_fpCosPiTest_in : std_logic_vector (1 downto 0);
signal rVStage_uid170_lzcZ_uid56_fpCosPiTest_b : std_logic_vector (0 downto 0);
signal leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest_q : std_logic_vector (34 downto 0);
signal expFracPreRnd_uid71_uid71_fpCosPiTest_q : std_logic_vector (31 downto 0);
signal expFracComp_uid74_fpCosPiTest_a : std_logic_vector(32 downto 0);
signal expFracComp_uid74_fpCosPiTest_b : std_logic_vector(32 downto 0);
signal expFracComp_uid74_fpCosPiTest_o : std_logic_vector (32 downto 0);
signal expFracComp_uid74_fpCosPiTest_q : std_logic_vector (32 downto 0);
signal s1_uid212_uid215_sinPiZPolyEval_q : std_logic_vector (22 downto 0);
signal s2_uid218_uid221_sinPiZPolyEval_q : std_logic_vector (31 downto 0);
signal leftShiftStage0Idx1_uid107_fxpX_uid41_fpCosPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage0Idx2_uid110_fxpX_uid41_fpCosPiTest_q : std_logic_vector (36 downto 0);
signal exc_R_uid34_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal exc_R_uid34_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal exc_R_uid34_fpCosPiTest_c : std_logic_vector(0 downto 0);
signal exc_R_uid34_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal rInfOrNaN_uid92_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal rInfOrNaN_uid92_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal rInfOrNaN_uid92_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal FxpX36_uid42_fpCosPiTest_in : std_logic_vector (36 downto 0);
signal FxpX36_uid42_fpCosPiTest_b : std_logic_vector (0 downto 0);
signal fxpXFrac_uid43_fpCosPiTest_in : std_logic_vector (35 downto 0);
signal fxpXFrac_uid43_fpCosPiTest_b : std_logic_vector (35 downto 0);
signal vCount_uid171_lzcZ_uid56_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal vCount_uid171_lzcZ_uid56_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal vCount_uid171_lzcZ_uid56_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal alignedZLow_uid58_fpCosPiTest_in : std_logic_vector (34 downto 0);
signal alignedZLow_uid58_fpCosPiTest_b : std_logic_vector (23 downto 0);
signal fracRComp_uid75_fpCosPiTest_in : std_logic_vector (23 downto 0);
signal fracRComp_uid75_fpCosPiTest_b : std_logic_vector (22 downto 0);
signal expRComp_uid76_fpCosPiTest_in : std_logic_vector (31 downto 0);
signal expRComp_uid76_fpCosPiTest_b : std_logic_vector (7 downto 0);
signal fxpSinRes_uid65_fpCosPiTest_in : std_logic_vector (29 downto 0);
signal fxpSinRes_uid65_fpCosPiTest_b : std_logic_vector (24 downto 0);
signal leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_q : std_logic_vector (36 downto 0);
signal FxpXFrac35_uid44_fpCosPiTest_in : std_logic_vector (35 downto 0);
signal FxpXFrac35_uid44_fpCosPiTest_b : std_logic_vector (0 downto 0);
signal r_uid172_lzcZ_uid56_fpCosPiTest_q : std_logic_vector (5 downto 0);
signal LeftShiftStage032dto0_uid115_fxpX_uid41_fpCosPiTest_in : std_logic_vector (32 downto 0);
signal LeftShiftStage032dto0_uid115_fxpX_uid41_fpCosPiTest_b : std_logic_vector (32 downto 0);
signal LeftShiftStage028dto0_uid118_fxpX_uid41_fpCosPiTest_in : std_logic_vector (28 downto 0);
signal LeftShiftStage028dto0_uid118_fxpX_uid41_fpCosPiTest_b : std_logic_vector (28 downto 0);
signal LeftShiftStage024dto0_uid121_fxpX_uid41_fpCosPiTest_in : std_logic_vector (24 downto 0);
signal LeftShiftStage024dto0_uid121_fxpX_uid41_fpCosPiTest_b : std_logic_vector (24 downto 0);
signal xParityXorHalfParity_uid96_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal xParityXorHalfParity_uid96_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal xParityXorHalfParity_uid96_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal leftShiftStageSel5Dto4_uid182_alignedZ_uid57_fpCosPiTest_in : std_logic_vector (5 downto 0);
signal leftShiftStageSel5Dto4_uid182_alignedZ_uid57_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel3Dto2_uid193_alignedZ_uid57_fpCosPiTest_in : std_logic_vector (3 downto 0);
signal leftShiftStageSel3Dto2_uid193_alignedZ_uid57_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid204_alignedZ_uid57_fpCosPiTest_in : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid204_alignedZ_uid57_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStage1Idx1_uid116_fxpX_uid41_fpCosPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage1Idx2_uid119_fxpX_uid41_fpCosPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage1Idx3_uid122_fxpX_uid41_fpCosPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_q : std_logic_vector (34 downto 0);
signal LeftShiftStage030dto0_uid185_alignedZ_uid57_fpCosPiTest_in : std_logic_vector (30 downto 0);
signal LeftShiftStage030dto0_uid185_alignedZ_uid57_fpCosPiTest_b : std_logic_vector (30 downto 0);
signal LeftShiftStage026dto0_uid188_alignedZ_uid57_fpCosPiTest_in : std_logic_vector (26 downto 0);
signal LeftShiftStage026dto0_uid188_alignedZ_uid57_fpCosPiTest_b : std_logic_vector (26 downto 0);
signal LeftShiftStage022dto0_uid191_alignedZ_uid57_fpCosPiTest_in : std_logic_vector (22 downto 0);
signal LeftShiftStage022dto0_uid191_alignedZ_uid57_fpCosPiTest_b : std_logic_vector (22 downto 0);
signal leftShiftStage1Idx1_uid186_alignedZ_uid57_fpCosPiTest_q : std_logic_vector (34 downto 0);
signal leftShiftStage1Idx2_uid189_alignedZ_uid57_fpCosPiTest_q : std_logic_vector (34 downto 0);
signal leftShiftStage1Idx3_uid192_alignedZ_uid57_fpCosPiTest_q : std_logic_vector (34 downto 0);
begin
--xIn(GPIN,3)@0
--LeftShiftStage133dto0_uid132_fxpX_uid41_fpCosPiTest(BITSELECT,131)@1
LeftShiftStage133dto0_uid132_fxpX_uid41_fpCosPiTest_in <= leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_q(33 downto 0);
LeftShiftStage133dto0_uid132_fxpX_uid41_fpCosPiTest_b <= LeftShiftStage133dto0_uid132_fxpX_uid41_fpCosPiTest_in(33 downto 0);
--leftShiftStage2Idx3Pad3_uid131_fxpX_uid41_fpCosPiTest(CONSTANT,130)
leftShiftStage2Idx3Pad3_uid131_fxpX_uid41_fpCosPiTest_q <= "000";
--leftShiftStage2Idx3_uid133_fxpX_uid41_fpCosPiTest(BITJOIN,132)@1
leftShiftStage2Idx3_uid133_fxpX_uid41_fpCosPiTest_q <= LeftShiftStage133dto0_uid132_fxpX_uid41_fpCosPiTest_b & leftShiftStage2Idx3Pad3_uid131_fxpX_uid41_fpCosPiTest_q;
--LeftShiftStage134dto0_uid129_fxpX_uid41_fpCosPiTest(BITSELECT,128)@1
LeftShiftStage134dto0_uid129_fxpX_uid41_fpCosPiTest_in <= leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_q(34 downto 0);
LeftShiftStage134dto0_uid129_fxpX_uid41_fpCosPiTest_b <= LeftShiftStage134dto0_uid129_fxpX_uid41_fpCosPiTest_in(34 downto 0);
--leftShiftStage2Idx2Pad2_uid128_fxpX_uid41_fpCosPiTest(CONSTANT,127)
leftShiftStage2Idx2Pad2_uid128_fxpX_uid41_fpCosPiTest_q <= "00";
--leftShiftStage2Idx2_uid130_fxpX_uid41_fpCosPiTest(BITJOIN,129)@1
leftShiftStage2Idx2_uid130_fxpX_uid41_fpCosPiTest_q <= LeftShiftStage134dto0_uid129_fxpX_uid41_fpCosPiTest_b & leftShiftStage2Idx2Pad2_uid128_fxpX_uid41_fpCosPiTest_q;
--LeftShiftStage135dto0_uid126_fxpX_uid41_fpCosPiTest(BITSELECT,125)@1
LeftShiftStage135dto0_uid126_fxpX_uid41_fpCosPiTest_in <= leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_q(35 downto 0);
LeftShiftStage135dto0_uid126_fxpX_uid41_fpCosPiTest_b <= LeftShiftStage135dto0_uid126_fxpX_uid41_fpCosPiTest_in(35 downto 0);
--GND(CONSTANT,0)
GND_q <= "0";
--leftShiftStage2Idx1_uid127_fxpX_uid41_fpCosPiTest(BITJOIN,126)@1
leftShiftStage2Idx1_uid127_fxpX_uid41_fpCosPiTest_q <= LeftShiftStage135dto0_uid126_fxpX_uid41_fpCosPiTest_b & GND_q;
--leftShiftStage0Idx3_uid111_fxpX_uid41_fpCosPiTest(CONSTANT,110)
leftShiftStage0Idx3_uid111_fxpX_uid41_fpCosPiTest_q <= "0000000000000000000000000000000000000";
--X4dto0_uid109_fxpX_uid41_fpCosPiTest(BITSELECT,108)@0
X4dto0_uid109_fxpX_uid41_fpCosPiTest_in <= oFracXExt_uid39_fpCosPiTest_q(4 downto 0);
X4dto0_uid109_fxpX_uid41_fpCosPiTest_b <= X4dto0_uid109_fxpX_uid41_fpCosPiTest_in(4 downto 0);
--leftShiftStage0Idx2Pad32_uid108_fxpX_uid41_fpCosPiTest(CONSTANT,107)
leftShiftStage0Idx2Pad32_uid108_fxpX_uid41_fpCosPiTest_q <= "00000000000000000000000000000000";
--leftShiftStage0Idx2_uid110_fxpX_uid41_fpCosPiTest(BITJOIN,109)@0
leftShiftStage0Idx2_uid110_fxpX_uid41_fpCosPiTest_q <= X4dto0_uid109_fxpX_uid41_fpCosPiTest_b & leftShiftStage0Idx2Pad32_uid108_fxpX_uid41_fpCosPiTest_q;
--X20dto0_uid106_fxpX_uid41_fpCosPiTest(BITSELECT,105)@0
X20dto0_uid106_fxpX_uid41_fpCosPiTest_in <= oFracXExt_uid39_fpCosPiTest_q(20 downto 0);
X20dto0_uid106_fxpX_uid41_fpCosPiTest_b <= X20dto0_uid106_fxpX_uid41_fpCosPiTest_in(20 downto 0);
--leftShiftStage0Idx1Pad16_uid105_fxpX_uid41_fpCosPiTest(CONSTANT,104)
leftShiftStage0Idx1Pad16_uid105_fxpX_uid41_fpCosPiTest_q <= "0000000000000000";
--leftShiftStage0Idx1_uid107_fxpX_uid41_fpCosPiTest(BITJOIN,106)@0
leftShiftStage0Idx1_uid107_fxpX_uid41_fpCosPiTest_q <= X20dto0_uid106_fxpX_uid41_fpCosPiTest_b & leftShiftStage0Idx1Pad16_uid105_fxpX_uid41_fpCosPiTest_q;
--cst01pWShift_uid14_fpCosPiTest(CONSTANT,13)
cst01pWShift_uid14_fpCosPiTest_q <= "0000000000000";
--VCC(CONSTANT,1)
VCC_q <= "1";
--fracX_uid7_fpCosPiTest(BITSELECT,6)@0
fracX_uid7_fpCosPiTest_in <= a(22 downto 0);
fracX_uid7_fpCosPiTest_b <= fracX_uid7_fpCosPiTest_in(22 downto 0);
--oFracX_uid37_uid37_fpCosPiTest(BITJOIN,36)@0
oFracX_uid37_uid37_fpCosPiTest_q <= VCC_q & fracX_uid7_fpCosPiTest_b;
--oFracXExt_uid39_fpCosPiTest(BITJOIN,38)@0
oFracXExt_uid39_fpCosPiTest_q <= cst01pWShift_uid14_fpCosPiTest_q & oFracX_uid37_uid37_fpCosPiTest_q;
--biasMwShiftMO_uid13_fpCosPiTest(CONSTANT,12)
biasMwShiftMO_uid13_fpCosPiTest_q <= "01110010";
--expX_uid6_fpCosPiTest(BITSELECT,5)@0
expX_uid6_fpCosPiTest_in <= a(30 downto 0);
expX_uid6_fpCosPiTest_b <= expX_uid6_fpCosPiTest_in(30 downto 23);
--shiftValFxPX_uid38_fpCosPiTest(SUB,37)@0
shiftValFxPX_uid38_fpCosPiTest_a <= STD_LOGIC_VECTOR("0" & expX_uid6_fpCosPiTest_b);
shiftValFxPX_uid38_fpCosPiTest_b <= STD_LOGIC_VECTOR("0" & biasMwShiftMO_uid13_fpCosPiTest_q);
shiftValFxPX_uid38_fpCosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(shiftValFxPX_uid38_fpCosPiTest_a) - UNSIGNED(shiftValFxPX_uid38_fpCosPiTest_b));
shiftValFxPX_uid38_fpCosPiTest_q <= shiftValFxPX_uid38_fpCosPiTest_o(8 downto 0);
--fxpShifterBits_uid40_fpCosPiTest(BITSELECT,39)@0
fxpShifterBits_uid40_fpCosPiTest_in <= shiftValFxPX_uid38_fpCosPiTest_q(5 downto 0);
fxpShifterBits_uid40_fpCosPiTest_b <= fxpShifterBits_uid40_fpCosPiTest_in(5 downto 0);
--leftShiftStageSel5Dto4_uid112_fxpX_uid41_fpCosPiTest(BITSELECT,111)@0
leftShiftStageSel5Dto4_uid112_fxpX_uid41_fpCosPiTest_in <= fxpShifterBits_uid40_fpCosPiTest_b;
leftShiftStageSel5Dto4_uid112_fxpX_uid41_fpCosPiTest_b <= leftShiftStageSel5Dto4_uid112_fxpX_uid41_fpCosPiTest_in(5 downto 4);
--leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest(MUX,112)@0
leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_s <= leftShiftStageSel5Dto4_uid112_fxpX_uid41_fpCosPiTest_b;
leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest: PROCESS (leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_s, en, oFracXExt_uid39_fpCosPiTest_q, leftShiftStage0Idx1_uid107_fxpX_uid41_fpCosPiTest_q, leftShiftStage0Idx2_uid110_fxpX_uid41_fpCosPiTest_q, leftShiftStage0Idx3_uid111_fxpX_uid41_fpCosPiTest_q)
BEGIN
CASE leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_s IS
WHEN "00" => leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_q <= oFracXExt_uid39_fpCosPiTest_q;
WHEN "01" => leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_q <= leftShiftStage0Idx1_uid107_fxpX_uid41_fpCosPiTest_q;
WHEN "10" => leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_q <= leftShiftStage0Idx2_uid110_fxpX_uid41_fpCosPiTest_q;
WHEN "11" => leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_q <= leftShiftStage0Idx3_uid111_fxpX_uid41_fpCosPiTest_q;
WHEN OTHERS => leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage024dto0_uid121_fxpX_uid41_fpCosPiTest(BITSELECT,120)@0
LeftShiftStage024dto0_uid121_fxpX_uid41_fpCosPiTest_in <= leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_q(24 downto 0);
LeftShiftStage024dto0_uid121_fxpX_uid41_fpCosPiTest_b <= LeftShiftStage024dto0_uid121_fxpX_uid41_fpCosPiTest_in(24 downto 0);
--leftShiftStage1Idx3Pad12_uid120_fxpX_uid41_fpCosPiTest(CONSTANT,119)
leftShiftStage1Idx3Pad12_uid120_fxpX_uid41_fpCosPiTest_q <= "000000000000";
--leftShiftStage1Idx3_uid122_fxpX_uid41_fpCosPiTest(BITJOIN,121)@0
leftShiftStage1Idx3_uid122_fxpX_uid41_fpCosPiTest_q <= LeftShiftStage024dto0_uid121_fxpX_uid41_fpCosPiTest_b & leftShiftStage1Idx3Pad12_uid120_fxpX_uid41_fpCosPiTest_q;
--reg_leftShiftStage1Idx3_uid122_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_5(REG,235)@0
reg_leftShiftStage1Idx3_uid122_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx3_uid122_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_5_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx3_uid122_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_5_q <= leftShiftStage1Idx3_uid122_fxpX_uid41_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage028dto0_uid118_fxpX_uid41_fpCosPiTest(BITSELECT,117)@0
LeftShiftStage028dto0_uid118_fxpX_uid41_fpCosPiTest_in <= leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_q(28 downto 0);
LeftShiftStage028dto0_uid118_fxpX_uid41_fpCosPiTest_b <= LeftShiftStage028dto0_uid118_fxpX_uid41_fpCosPiTest_in(28 downto 0);
--cstAllZWE_uid21_fpCosPiTest(CONSTANT,20)
cstAllZWE_uid21_fpCosPiTest_q <= "00000000";
--leftShiftStage1Idx2_uid119_fxpX_uid41_fpCosPiTest(BITJOIN,118)@0
leftShiftStage1Idx2_uid119_fxpX_uid41_fpCosPiTest_q <= LeftShiftStage028dto0_uid118_fxpX_uid41_fpCosPiTest_b & cstAllZWE_uid21_fpCosPiTest_q;
--reg_leftShiftStage1Idx2_uid119_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_4(REG,234)@0
reg_leftShiftStage1Idx2_uid119_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx2_uid119_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_4_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx2_uid119_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_4_q <= leftShiftStage1Idx2_uid119_fxpX_uid41_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage032dto0_uid115_fxpX_uid41_fpCosPiTest(BITSELECT,114)@0
LeftShiftStage032dto0_uid115_fxpX_uid41_fpCosPiTest_in <= leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_q(32 downto 0);
LeftShiftStage032dto0_uid115_fxpX_uid41_fpCosPiTest_b <= LeftShiftStage032dto0_uid115_fxpX_uid41_fpCosPiTest_in(32 downto 0);
--leftShiftStage1Idx1Pad4_uid114_fxpX_uid41_fpCosPiTest(CONSTANT,113)
leftShiftStage1Idx1Pad4_uid114_fxpX_uid41_fpCosPiTest_q <= "0000";
--leftShiftStage1Idx1_uid116_fxpX_uid41_fpCosPiTest(BITJOIN,115)@0
leftShiftStage1Idx1_uid116_fxpX_uid41_fpCosPiTest_q <= LeftShiftStage032dto0_uid115_fxpX_uid41_fpCosPiTest_b & leftShiftStage1Idx1Pad4_uid114_fxpX_uid41_fpCosPiTest_q;
--reg_leftShiftStage1Idx1_uid116_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_3(REG,233)@0
reg_leftShiftStage1Idx1_uid116_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx1_uid116_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_3_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx1_uid116_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_3_q <= leftShiftStage1Idx1_uid116_fxpX_uid41_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--reg_leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_2(REG,232)@0
reg_leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_2_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_2_q <= leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel3Dto2_uid123_fxpX_uid41_fpCosPiTest(BITSELECT,122)@0
leftShiftStageSel3Dto2_uid123_fxpX_uid41_fpCosPiTest_in <= fxpShifterBits_uid40_fpCosPiTest_b(3 downto 0);
leftShiftStageSel3Dto2_uid123_fxpX_uid41_fpCosPiTest_b <= leftShiftStageSel3Dto2_uid123_fxpX_uid41_fpCosPiTest_in(3 downto 2);
--reg_leftShiftStageSel3Dto2_uid123_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_1(REG,231)@0
reg_leftShiftStageSel3Dto2_uid123_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel3Dto2_uid123_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel3Dto2_uid123_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_1_q <= leftShiftStageSel3Dto2_uid123_fxpX_uid41_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest(MUX,123)@1
leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_s <= reg_leftShiftStageSel3Dto2_uid123_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_1_q;
leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest: PROCESS (leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_s, en, reg_leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_2_q, reg_leftShiftStage1Idx1_uid116_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_3_q, reg_leftShiftStage1Idx2_uid119_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_4_q, reg_leftShiftStage1Idx3_uid122_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_5_q)
BEGIN
CASE leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_s IS
WHEN "00" => leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_q <= reg_leftShiftStage0_uid113_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_2_q;
WHEN "01" => leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_q <= reg_leftShiftStage1Idx1_uid116_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_3_q;
WHEN "10" => leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_q <= reg_leftShiftStage1Idx2_uid119_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_4_q;
WHEN "11" => leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_q <= reg_leftShiftStage1Idx3_uid122_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_5_q;
WHEN OTHERS => leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--leftShiftStageSel1Dto0_uid134_fxpX_uid41_fpCosPiTest(BITSELECT,133)@0
leftShiftStageSel1Dto0_uid134_fxpX_uid41_fpCosPiTest_in <= fxpShifterBits_uid40_fpCosPiTest_b(1 downto 0);
leftShiftStageSel1Dto0_uid134_fxpX_uid41_fpCosPiTest_b <= leftShiftStageSel1Dto0_uid134_fxpX_uid41_fpCosPiTest_in(1 downto 0);
--reg_leftShiftStageSel1Dto0_uid134_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest_1(REG,236)@0
reg_leftShiftStageSel1Dto0_uid134_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel1Dto0_uid134_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel1Dto0_uid134_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest_1_q <= leftShiftStageSel1Dto0_uid134_fxpX_uid41_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest(MUX,134)@1
leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest_s <= reg_leftShiftStageSel1Dto0_uid134_fxpX_uid41_fpCosPiTest_0_to_leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest_1_q;
leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest: PROCESS (leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest_s, en, leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_q, leftShiftStage2Idx1_uid127_fxpX_uid41_fpCosPiTest_q, leftShiftStage2Idx2_uid130_fxpX_uid41_fpCosPiTest_q, leftShiftStage2Idx3_uid133_fxpX_uid41_fpCosPiTest_q)
BEGIN
CASE leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest_s IS
WHEN "00" => leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest_q <= leftShiftStage1_uid124_fxpX_uid41_fpCosPiTest_q;
WHEN "01" => leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest_q <= leftShiftStage2Idx1_uid127_fxpX_uid41_fpCosPiTest_q;
WHEN "10" => leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest_q <= leftShiftStage2Idx2_uid130_fxpX_uid41_fpCosPiTest_q;
WHEN "11" => leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest_q <= leftShiftStage2Idx3_uid133_fxpX_uid41_fpCosPiTest_q;
WHEN OTHERS => leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--fxpXFrac_uid43_fpCosPiTest(BITSELECT,42)@1
fxpXFrac_uid43_fpCosPiTest_in <= leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest_q(35 downto 0);
fxpXFrac_uid43_fpCosPiTest_b <= fxpXFrac_uid43_fpCosPiTest_in(35 downto 0);
--FxpXFrac35_uid44_fpCosPiTest(BITSELECT,43)@1
FxpXFrac35_uid44_fpCosPiTest_in <= fxpXFrac_uid43_fpCosPiTest_b;
FxpXFrac35_uid44_fpCosPiTest_b <= FxpXFrac35_uid44_fpCosPiTest_in(35 downto 35);
--FxpX36_uid42_fpCosPiTest(BITSELECT,41)@1
FxpX36_uid42_fpCosPiTest_in <= leftShiftStage2_uid135_fxpX_uid41_fpCosPiTest_q;
FxpX36_uid42_fpCosPiTest_b <= FxpX36_uid42_fpCosPiTest_in(36 downto 36);
--xParityXorHalfParity_uid96_fpCosPiTest(LOGICAL,95)@1
xParityXorHalfParity_uid96_fpCosPiTest_a <= FxpX36_uid42_fpCosPiTest_b;
xParityXorHalfParity_uid96_fpCosPiTest_b <= FxpXFrac35_uid44_fpCosPiTest_b;
xParityXorHalfParity_uid96_fpCosPiTest_q <= xParityXorHalfParity_uid96_fpCosPiTest_a xor xParityXorHalfParity_uid96_fpCosPiTest_b;
--ld_xParityXorHalfParity_uid96_fpCosPiTest_q_to_signRComp_uid99_fpCosPiTest_c(DELAY,369)@1
ld_xParityXorHalfParity_uid96_fpCosPiTest_q_to_signRComp_uid99_fpCosPiTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => xParityXorHalfParity_uid96_fpCosPiTest_q, xout => ld_xParityXorHalfParity_uid96_fpCosPiTest_q_to_signRComp_uid99_fpCosPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--cstBiasPwF_uid12_fpCosPiTest(CONSTANT,11)
cstBiasPwF_uid12_fpCosPiTest_q <= "10010110";
--xEvenInt_uid35_fpCosPiTest(COMPARE,34)@0
xEvenInt_uid35_fpCosPiTest_cin <= GND_q;
xEvenInt_uid35_fpCosPiTest_a <= STD_LOGIC_VECTOR("00" & cstBiasPwF_uid12_fpCosPiTest_q) & '0';
xEvenInt_uid35_fpCosPiTest_b <= STD_LOGIC_VECTOR("00" & expX_uid6_fpCosPiTest_b) & xEvenInt_uid35_fpCosPiTest_cin(0);
xEvenInt_uid35_fpCosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(xEvenInt_uid35_fpCosPiTest_a) - UNSIGNED(xEvenInt_uid35_fpCosPiTest_b));
xEvenInt_uid35_fpCosPiTest_c(0) <= xEvenInt_uid35_fpCosPiTest_o(10);
--ld_xEvenInt_uid35_fpCosPiTest_c_to_evenIntCosNotOneFZ_uid79_fpCosPiTest_a(DELAY,335)@0
ld_xEvenInt_uid35_fpCosPiTest_c_to_evenIntCosNotOneFZ_uid79_fpCosPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => xEvenInt_uid35_fpCosPiTest_c, xout => ld_xEvenInt_uid35_fpCosPiTest_c_to_evenIntCosNotOneFZ_uid79_fpCosPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--InvXEvenInt_uid81_fpCosPiTest(LOGICAL,80)@2
InvXEvenInt_uid81_fpCosPiTest_a <= ld_xEvenInt_uid35_fpCosPiTest_c_to_evenIntCosNotOneFZ_uid79_fpCosPiTest_a_q;
InvXEvenInt_uid81_fpCosPiTest_q <= not InvXEvenInt_uid81_fpCosPiTest_a;
--cosXIsOne_uid36_fpCosPiTest(COMPARE,35)@0
cosXIsOne_uid36_fpCosPiTest_cin <= GND_q;
cosXIsOne_uid36_fpCosPiTest_a <= STD_LOGIC_VECTOR("00" & expX_uid6_fpCosPiTest_b) & '0';
cosXIsOne_uid36_fpCosPiTest_b <= STD_LOGIC_VECTOR("00" & biasMwShiftMO_uid13_fpCosPiTest_q) & cosXIsOne_uid36_fpCosPiTest_cin(0);
cosXIsOne_uid36_fpCosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(cosXIsOne_uid36_fpCosPiTest_a) - UNSIGNED(cosXIsOne_uid36_fpCosPiTest_b));
cosXIsOne_uid36_fpCosPiTest_c(0) <= cosXIsOne_uid36_fpCosPiTest_o(10);
--ld_cosXIsOne_uid36_fpCosPiTest_c_to_InvCosXIsOne_uid77_fpCosPiTest_a(DELAY,332)@0
ld_cosXIsOne_uid36_fpCosPiTest_c_to_InvCosXIsOne_uid77_fpCosPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => cosXIsOne_uid36_fpCosPiTest_c, xout => ld_cosXIsOne_uid36_fpCosPiTest_c_to_InvCosXIsOne_uid77_fpCosPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--InvCosXIsOne_uid77_fpCosPiTest(LOGICAL,76)@2
InvCosXIsOne_uid77_fpCosPiTest_a <= ld_cosXIsOne_uid36_fpCosPiTest_c_to_InvCosXIsOne_uid77_fpCosPiTest_a_q;
InvCosXIsOne_uid77_fpCosPiTest_q <= not InvCosXIsOne_uid77_fpCosPiTest_a;
--signRComp_uid99_fpCosPiTest(LOGICAL,98)@2
signRComp_uid99_fpCosPiTest_a <= InvCosXIsOne_uid77_fpCosPiTest_q;
signRComp_uid99_fpCosPiTest_b <= InvXEvenInt_uid81_fpCosPiTest_q;
signRComp_uid99_fpCosPiTest_c <= ld_xParityXorHalfParity_uid96_fpCosPiTest_q_to_signRComp_uid99_fpCosPiTest_c_q;
signRComp_uid99_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
signRComp_uid99_fpCosPiTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1' AND en = "1") THEN
signRComp_uid99_fpCosPiTest_q <= signRComp_uid99_fpCosPiTest_a and signRComp_uid99_fpCosPiTest_b and signRComp_uid99_fpCosPiTest_c;
END IF;
END PROCESS;
--cstZwSwF_uid15_fpCosPiTest(CONSTANT,14)
cstZwSwF_uid15_fpCosPiTest_q <= "00000000000000000000000000000000000";
--cstHalfwSwFP1_uid18_fpCosPiTest(BITJOIN,17)@2
cstHalfwSwFP1_uid18_fpCosPiTest_q <= VCC_q & cstZwSwF_uid15_fpCosPiTest_q;
--reg_fxpXFrac_uid43_fpCosPiTest_0_to_fxpXFracZero_uid45_fpCosPiTest_1(REG,237)@1
reg_fxpXFrac_uid43_fpCosPiTest_0_to_fxpXFracZero_uid45_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fxpXFrac_uid43_fpCosPiTest_0_to_fxpXFracZero_uid45_fpCosPiTest_1_q <= "000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fxpXFrac_uid43_fpCosPiTest_0_to_fxpXFracZero_uid45_fpCosPiTest_1_q <= fxpXFrac_uid43_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--fxpXFracHalf_uid46_fpCosPiTest(LOGICAL,45)@2
fxpXFracHalf_uid46_fpCosPiTest_a <= reg_fxpXFrac_uid43_fpCosPiTest_0_to_fxpXFracZero_uid45_fpCosPiTest_1_q;
fxpXFracHalf_uid46_fpCosPiTest_b <= cstHalfwSwFP1_uid18_fpCosPiTest_q;
fxpXFracHalf_uid46_fpCosPiTest_q <= "1" when fxpXFracHalf_uid46_fpCosPiTest_a = fxpXFracHalf_uid46_fpCosPiTest_b else "0";
--ld_fxpXFracHalf_uid46_fpCosPiTest_q_to_InvFxpXFracHalf_uid100_fpCosPiTest_a(DELAY,370)@2
ld_fxpXFracHalf_uid46_fpCosPiTest_q_to_InvFxpXFracHalf_uid100_fpCosPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => fxpXFracHalf_uid46_fpCosPiTest_q, xout => ld_fxpXFracHalf_uid46_fpCosPiTest_q_to_InvFxpXFracHalf_uid100_fpCosPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--InvFxpXFracHalf_uid100_fpCosPiTest(LOGICAL,99)@3
InvFxpXFracHalf_uid100_fpCosPiTest_a <= ld_fxpXFracHalf_uid46_fpCosPiTest_q_to_InvFxpXFracHalf_uid100_fpCosPiTest_a_q;
InvFxpXFracHalf_uid100_fpCosPiTest_q <= not InvFxpXFracHalf_uid100_fpCosPiTest_a;
--signR_uid101_fpCosPiTest(LOGICAL,100)@3
signR_uid101_fpCosPiTest_a <= InvFxpXFracHalf_uid100_fpCosPiTest_q;
signR_uid101_fpCosPiTest_b <= signRComp_uid99_fpCosPiTest_q;
signR_uid101_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
signR_uid101_fpCosPiTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1' AND en = "1") THEN
signR_uid101_fpCosPiTest_q <= signR_uid101_fpCosPiTest_a and signR_uid101_fpCosPiTest_b;
END IF;
END PROCESS;
--ld_signR_uid101_fpCosPiTest_q_to_R_uid102_fpCosPiTest_c(DELAY,375)@4
ld_signR_uid101_fpCosPiTest_q_to_R_uid102_fpCosPiTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 13 )
PORT MAP ( xin => signR_uid101_fpCosPiTest_q, xout => ld_signR_uid101_fpCosPiTest_q_to_R_uid102_fpCosPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--cstBias_uid10_fpCosPiTest(CONSTANT,9)
cstBias_uid10_fpCosPiTest_q <= "01111111";
--cstAllOWE_uid8_fpCosPiTest(CONSTANT,7)
cstAllOWE_uid8_fpCosPiTest_q <= "11111111";
--pad_o_uid16_uid47_fpCosPiTest(BITJOIN,46)@1
pad_o_uid16_uid47_fpCosPiTest_q <= VCC_q & STD_LOGIC_VECTOR((35 downto 1 => GND_q(0)) & GND_q);
--reg_pad_o_uid16_uid47_fpCosPiTest_0_to_oMFxpXFrac_uid47_fpCosPiTest_0(REG,244)@1
reg_pad_o_uid16_uid47_fpCosPiTest_0_to_oMFxpXFrac_uid47_fpCosPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_o_uid16_uid47_fpCosPiTest_0_to_oMFxpXFrac_uid47_fpCosPiTest_0_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_o_uid16_uid47_fpCosPiTest_0_to_oMFxpXFrac_uid47_fpCosPiTest_0_q <= pad_o_uid16_uid47_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--oMFxpXFrac_uid47_fpCosPiTest(SUB,47)@2
oMFxpXFrac_uid47_fpCosPiTest_a <= STD_LOGIC_VECTOR("0" & reg_pad_o_uid16_uid47_fpCosPiTest_0_to_oMFxpXFrac_uid47_fpCosPiTest_0_q);
oMFxpXFrac_uid47_fpCosPiTest_b <= STD_LOGIC_VECTOR("00" & reg_fxpXFrac_uid43_fpCosPiTest_0_to_fxpXFracZero_uid45_fpCosPiTest_1_q);
oMFxpXFrac_uid47_fpCosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(oMFxpXFrac_uid47_fpCosPiTest_a) - UNSIGNED(oMFxpXFrac_uid47_fpCosPiTest_b));
oMFxpXFrac_uid47_fpCosPiTest_q <= oMFxpXFrac_uid47_fpCosPiTest_o(37 downto 0);
--oMFxpXFrac_uid49_fpCosPiTest(BITSELECT,48)@2
oMFxpXFrac_uid49_fpCosPiTest_in <= oMFxpXFrac_uid47_fpCosPiTest_q(35 downto 0);
oMFxpXFrac_uid49_fpCosPiTest_b <= oMFxpXFrac_uid49_fpCosPiTest_in(35 downto 0);
--ld_fxpXFrac_uid43_fpCosPiTest_b_to_rangeReducedFxPX_uid51_fpCosPiTest_c(DELAY,308)@1
ld_fxpXFrac_uid43_fpCosPiTest_b_to_rangeReducedFxPX_uid51_fpCosPiTest_c : dspba_delay
GENERIC MAP ( width => 36, depth => 1 )
PORT MAP ( xin => fxpXFrac_uid43_fpCosPiTest_b, xout => ld_fxpXFrac_uid43_fpCosPiTest_b_to_rangeReducedFxPX_uid51_fpCosPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--ld_FxpXFrac35_uid44_fpCosPiTest_b_to_rangeReducedFxPX_uid51_fpCosPiTest_b(DELAY,307)@1
ld_FxpXFrac35_uid44_fpCosPiTest_b_to_rangeReducedFxPX_uid51_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => FxpXFrac35_uid44_fpCosPiTest_b, xout => ld_FxpXFrac35_uid44_fpCosPiTest_b_to_rangeReducedFxPX_uid51_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--rangeReducedFxPX_uid51_fpCosPiTest(MUX,50)@2
rangeReducedFxPX_uid51_fpCosPiTest_s <= ld_FxpXFrac35_uid44_fpCosPiTest_b_to_rangeReducedFxPX_uid51_fpCosPiTest_b_q;
rangeReducedFxPX_uid51_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
rangeReducedFxPX_uid51_fpCosPiTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE rangeReducedFxPX_uid51_fpCosPiTest_s IS
WHEN "0" => rangeReducedFxPX_uid51_fpCosPiTest_q <= ld_fxpXFrac_uid43_fpCosPiTest_b_to_rangeReducedFxPX_uid51_fpCosPiTest_c_q;
WHEN "1" => rangeReducedFxPX_uid51_fpCosPiTest_q <= oMFxpXFrac_uid49_fpCosPiTest_b;
WHEN OTHERS => rangeReducedFxPX_uid51_fpCosPiTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--pad_half_uid17_uid52_fpCosPiTest(BITJOIN,51)@2
pad_half_uid17_uid52_fpCosPiTest_q <= VCC_q & STD_LOGIC_VECTOR((34 downto 1 => GND_q(0)) & GND_q);
--reg_pad_half_uid17_uid52_fpCosPiTest_0_to_z_halfMRRFxPXE_uid52_fpCosPiTest_0(REG,246)@2
reg_pad_half_uid17_uid52_fpCosPiTest_0_to_z_halfMRRFxPXE_uid52_fpCosPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_half_uid17_uid52_fpCosPiTest_0_to_z_halfMRRFxPXE_uid52_fpCosPiTest_0_q <= "000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_half_uid17_uid52_fpCosPiTest_0_to_z_halfMRRFxPXE_uid52_fpCosPiTest_0_q <= pad_half_uid17_uid52_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--z_halfMRRFxPXE_uid52_fpCosPiTest(SUB,52)@3
z_halfMRRFxPXE_uid52_fpCosPiTest_a <= STD_LOGIC_VECTOR("0" & reg_pad_half_uid17_uid52_fpCosPiTest_0_to_z_halfMRRFxPXE_uid52_fpCosPiTest_0_q);
z_halfMRRFxPXE_uid52_fpCosPiTest_b <= STD_LOGIC_VECTOR("0" & rangeReducedFxPX_uid51_fpCosPiTest_q);
z_halfMRRFxPXE_uid52_fpCosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(z_halfMRRFxPXE_uid52_fpCosPiTest_a) - UNSIGNED(z_halfMRRFxPXE_uid52_fpCosPiTest_b));
z_halfMRRFxPXE_uid52_fpCosPiTest_q <= z_halfMRRFxPXE_uid52_fpCosPiTest_o(36 downto 0);
--z_uid54_fpCosPiTest(BITSELECT,53)@3
z_uid54_fpCosPiTest_in <= z_halfMRRFxPXE_uid52_fpCosPiTest_q(34 downto 0);
z_uid54_fpCosPiTest_b <= z_uid54_fpCosPiTest_in(34 downto 0);
--zAddr_uid62_fpCosPiTest(BITSELECT,61)@3
zAddr_uid62_fpCosPiTest_in <= z_uid54_fpCosPiTest_b;
zAddr_uid62_fpCosPiTest_b <= zAddr_uid62_fpCosPiTest_in(34 downto 28);
--reg_zAddr_uid62_fpCosPiTest_0_to_memoryC2_uid209_sinPiZTableGenerator_0(REG,263)@3
reg_zAddr_uid62_fpCosPiTest_0_to_memoryC2_uid209_sinPiZTableGenerator_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_zAddr_uid62_fpCosPiTest_0_to_memoryC2_uid209_sinPiZTableGenerator_0_q <= "0000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_zAddr_uid62_fpCosPiTest_0_to_memoryC2_uid209_sinPiZTableGenerator_0_q <= zAddr_uid62_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--memoryC2_uid209_sinPiZTableGenerator(LOOKUP,208)@4
memoryC2_uid209_sinPiZTableGenerator: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
memoryC2_uid209_sinPiZTableGenerator_q <= "10101101010011";
ELSIF (clk'EVENT AND clk = '1' AND en = "1") THEN
CASE (reg_zAddr_uid62_fpCosPiTest_0_to_memoryC2_uid209_sinPiZTableGenerator_0_q) IS
WHEN "0000000" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101101010011";
WHEN "0000001" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101101010100";
WHEN "0000010" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101101010111";
WHEN "0000011" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101101011001";
WHEN "0000100" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101101011011";
WHEN "0000101" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101101011100";
WHEN "0000110" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101101011111";
WHEN "0000111" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101101100010";
WHEN "0001000" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101101100110";
WHEN "0001001" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101101101011";
WHEN "0001010" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101101110000";
WHEN "0001011" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101101110101";
WHEN "0001100" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101101111011";
WHEN "0001101" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101110000000";
WHEN "0001110" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101110000111";
WHEN "0001111" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101110001110";
WHEN "0010000" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101110010011";
WHEN "0010001" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101110011110";
WHEN "0010010" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101110100110";
WHEN "0010011" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101110101111";
WHEN "0010100" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101110111000";
WHEN "0010101" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101111000011";
WHEN "0010110" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101111001100";
WHEN "0010111" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101111010111";
WHEN "0011000" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101111100011";
WHEN "0011001" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101111101110";
WHEN "0011010" => memoryC2_uid209_sinPiZTableGenerator_q <= "10101111111011";
WHEN "0011011" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110000001001";
WHEN "0011100" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110000010101";
WHEN "0011101" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110000100000";
WHEN "0011110" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110000110001";
WHEN "0011111" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110001000000";
WHEN "0100000" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110001001101";
WHEN "0100001" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110001011110";
WHEN "0100010" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110001101100";
WHEN "0100011" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110001111111";
WHEN "0100100" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110010001111";
WHEN "0100101" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110010100001";
WHEN "0100110" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110010110011";
WHEN "0100111" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110011000101";
WHEN "0101000" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110011010110";
WHEN "0101001" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110011101011";
WHEN "0101010" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110011111111";
WHEN "0101011" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110100010010";
WHEN "0101100" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110100100101";
WHEN "0101101" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110100111011";
WHEN "0101110" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110101001110";
WHEN "0101111" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110101100111";
WHEN "0110000" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110101111100";
WHEN "0110001" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110110010010";
WHEN "0110010" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110110100110";
WHEN "0110011" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110111000000";
WHEN "0110100" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110111010101";
WHEN "0110101" => memoryC2_uid209_sinPiZTableGenerator_q <= "10110111110000";
WHEN "0110110" => memoryC2_uid209_sinPiZTableGenerator_q <= "10111000000110";
WHEN "0110111" => memoryC2_uid209_sinPiZTableGenerator_q <= "10111000100010";
WHEN "0111000" => memoryC2_uid209_sinPiZTableGenerator_q <= "10111000111001";
WHEN "0111001" => memoryC2_uid209_sinPiZTableGenerator_q <= "10111001010100";
WHEN "0111010" => memoryC2_uid209_sinPiZTableGenerator_q <= "10111001101111";
WHEN "0111011" => memoryC2_uid209_sinPiZTableGenerator_q <= "10111010001001";
WHEN "0111100" => memoryC2_uid209_sinPiZTableGenerator_q <= "10111010100011";
WHEN "0111101" => memoryC2_uid209_sinPiZTableGenerator_q <= "10111010111100";
WHEN "0111110" => memoryC2_uid209_sinPiZTableGenerator_q <= "10111011011001";
WHEN "0111111" => memoryC2_uid209_sinPiZTableGenerator_q <= "10111011110111";
WHEN "1000000" => memoryC2_uid209_sinPiZTableGenerator_q <= "10111100010100";
WHEN "1000001" => memoryC2_uid209_sinPiZTableGenerator_q <= "10111100110001";
WHEN "1000010" => memoryC2_uid209_sinPiZTableGenerator_q <= "10111101001101";
WHEN "1000011" => memoryC2_uid209_sinPiZTableGenerator_q <= "10111101101010";
WHEN "1000100" => memoryC2_uid209_sinPiZTableGenerator_q <= "10111110001000";
WHEN "1000101" => memoryC2_uid209_sinPiZTableGenerator_q <= "10111110100101";
WHEN "1000110" => memoryC2_uid209_sinPiZTableGenerator_q <= "10111111000101";
WHEN "1000111" => memoryC2_uid209_sinPiZTableGenerator_q <= "10111111100011";
WHEN "1001000" => memoryC2_uid209_sinPiZTableGenerator_q <= "11000000000011";
WHEN "1001001" => memoryC2_uid209_sinPiZTableGenerator_q <= "11000000100011";
WHEN "1001010" => memoryC2_uid209_sinPiZTableGenerator_q <= "11000001000100";
WHEN "1001011" => memoryC2_uid209_sinPiZTableGenerator_q <= "11000001100010";
WHEN "1001100" => memoryC2_uid209_sinPiZTableGenerator_q <= "11000010000100";
WHEN "1001101" => memoryC2_uid209_sinPiZTableGenerator_q <= "11000010100010";
WHEN "1001110" => memoryC2_uid209_sinPiZTableGenerator_q <= "11000011000110";
WHEN "1001111" => memoryC2_uid209_sinPiZTableGenerator_q <= "11000011101000";
WHEN "1010000" => memoryC2_uid209_sinPiZTableGenerator_q <= "11000100001010";
WHEN "1010001" => memoryC2_uid209_sinPiZTableGenerator_q <= "11000100101101";
WHEN "1010010" => memoryC2_uid209_sinPiZTableGenerator_q <= "11000101010001";
WHEN "1010011" => memoryC2_uid209_sinPiZTableGenerator_q <= "11000101110010";
WHEN "1010100" => memoryC2_uid209_sinPiZTableGenerator_q <= "11000110010100";
WHEN "1010101" => memoryC2_uid209_sinPiZTableGenerator_q <= "11000110111011";
WHEN "1010110" => memoryC2_uid209_sinPiZTableGenerator_q <= "11000111011010";
WHEN "1010111" => memoryC2_uid209_sinPiZTableGenerator_q <= "11001000000001";
WHEN "1011000" => memoryC2_uid209_sinPiZTableGenerator_q <= "11001000100110";
WHEN "1011001" => memoryC2_uid209_sinPiZTableGenerator_q <= "11001001001011";
WHEN "1011010" => memoryC2_uid209_sinPiZTableGenerator_q <= "11001001101101";
WHEN "1011011" => memoryC2_uid209_sinPiZTableGenerator_q <= "11001010010101";
WHEN "1011100" => memoryC2_uid209_sinPiZTableGenerator_q <= "11001010111100";
WHEN "1011101" => memoryC2_uid209_sinPiZTableGenerator_q <= "11001011100000";
WHEN "1011110" => memoryC2_uid209_sinPiZTableGenerator_q <= "11001100000101";
WHEN "1011111" => memoryC2_uid209_sinPiZTableGenerator_q <= "11001100101110";
WHEN "1100000" => memoryC2_uid209_sinPiZTableGenerator_q <= "11001101010100";
WHEN "1100001" => memoryC2_uid209_sinPiZTableGenerator_q <= "11001101111010";
WHEN "1100010" => memoryC2_uid209_sinPiZTableGenerator_q <= "11001110100010";
WHEN "1100011" => memoryC2_uid209_sinPiZTableGenerator_q <= "11001111001001";
WHEN "1100100" => memoryC2_uid209_sinPiZTableGenerator_q <= "11001111110001";
WHEN "1100101" => memoryC2_uid209_sinPiZTableGenerator_q <= "11010000010110";
WHEN "1100110" => memoryC2_uid209_sinPiZTableGenerator_q <= "11010000111111";
WHEN "1100111" => memoryC2_uid209_sinPiZTableGenerator_q <= "11010001101001";
WHEN "1101000" => memoryC2_uid209_sinPiZTableGenerator_q <= "11010010010010";
WHEN "1101001" => memoryC2_uid209_sinPiZTableGenerator_q <= "11010010111101";
WHEN "1101010" => memoryC2_uid209_sinPiZTableGenerator_q <= "11010011100001";
WHEN "1101011" => memoryC2_uid209_sinPiZTableGenerator_q <= "11010100001100";
WHEN "1101100" => memoryC2_uid209_sinPiZTableGenerator_q <= "11010100110111";
WHEN "1101101" => memoryC2_uid209_sinPiZTableGenerator_q <= "11010101100001";
WHEN "1101110" => memoryC2_uid209_sinPiZTableGenerator_q <= "11010110001011";
WHEN "1101111" => memoryC2_uid209_sinPiZTableGenerator_q <= "11010110110011";
WHEN "1110000" => memoryC2_uid209_sinPiZTableGenerator_q <= "11010111011111";
WHEN "1110001" => memoryC2_uid209_sinPiZTableGenerator_q <= "11011000001010";
WHEN "1110010" => memoryC2_uid209_sinPiZTableGenerator_q <= "11011000110100";
WHEN "1110011" => memoryC2_uid209_sinPiZTableGenerator_q <= "11011001011111";
WHEN "1110100" => memoryC2_uid209_sinPiZTableGenerator_q <= "11011010001010";
WHEN "1110101" => memoryC2_uid209_sinPiZTableGenerator_q <= "11011010110110";
WHEN "1110110" => memoryC2_uid209_sinPiZTableGenerator_q <= "11011011100011";
WHEN "1110111" => memoryC2_uid209_sinPiZTableGenerator_q <= "11011100001111";
WHEN "1111000" => memoryC2_uid209_sinPiZTableGenerator_q <= "11011100111001";
WHEN "1111001" => memoryC2_uid209_sinPiZTableGenerator_q <= "11011101100011";
WHEN "1111010" => memoryC2_uid209_sinPiZTableGenerator_q <= "11011110010001";
WHEN "1111011" => memoryC2_uid209_sinPiZTableGenerator_q <= "11011110111011";
WHEN "1111100" => memoryC2_uid209_sinPiZTableGenerator_q <= "11011111101000";
WHEN "1111101" => memoryC2_uid209_sinPiZTableGenerator_q <= "11100000010101";
WHEN "1111110" => memoryC2_uid209_sinPiZTableGenerator_q <= "11100001000010";
WHEN "1111111" => memoryC2_uid209_sinPiZTableGenerator_q <= "11100001110000";
WHEN OTHERS =>
memoryC2_uid209_sinPiZTableGenerator_q <= (others => '-');
END CASE;
END IF;
END PROCESS;
--zPPolyEval_uid63_fpCosPiTest(BITSELECT,62)@3
zPPolyEval_uid63_fpCosPiTest_in <= z_uid54_fpCosPiTest_b(27 downto 0);
zPPolyEval_uid63_fpCosPiTest_b <= zPPolyEval_uid63_fpCosPiTest_in(27 downto 12);
--yT1_uid210_sinPiZPolyEval(BITSELECT,209)@3
yT1_uid210_sinPiZPolyEval_in <= zPPolyEval_uid63_fpCosPiTest_b;
yT1_uid210_sinPiZPolyEval_b <= yT1_uid210_sinPiZPolyEval_in(15 downto 2);
--reg_yT1_uid210_sinPiZPolyEval_0_to_prodXY_uid226_pT1_uid211_sinPiZPolyEval_0(REG,264)@3
reg_yT1_uid210_sinPiZPolyEval_0_to_prodXY_uid226_pT1_uid211_sinPiZPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT1_uid210_sinPiZPolyEval_0_to_prodXY_uid226_pT1_uid211_sinPiZPolyEval_0_q <= "00000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT1_uid210_sinPiZPolyEval_0_to_prodXY_uid226_pT1_uid211_sinPiZPolyEval_0_q <= yT1_uid210_sinPiZPolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_reg_yT1_uid210_sinPiZPolyEval_0_to_prodXY_uid226_pT1_uid211_sinPiZPolyEval_0_q_to_prodXY_uid226_pT1_uid211_sinPiZPolyEval_a(DELAY,499)@4
ld_reg_yT1_uid210_sinPiZPolyEval_0_to_prodXY_uid226_pT1_uid211_sinPiZPolyEval_0_q_to_prodXY_uid226_pT1_uid211_sinPiZPolyEval_a : dspba_delay
GENERIC MAP ( width => 14, depth => 1 )
PORT MAP ( xin => reg_yT1_uid210_sinPiZPolyEval_0_to_prodXY_uid226_pT1_uid211_sinPiZPolyEval_0_q, xout => ld_reg_yT1_uid210_sinPiZPolyEval_0_to_prodXY_uid226_pT1_uid211_sinPiZPolyEval_0_q_to_prodXY_uid226_pT1_uid211_sinPiZPolyEval_a_q, ena => en(0), clk => clk, aclr => areset );
--prodXY_uid226_pT1_uid211_sinPiZPolyEval(MULT,225)@5
prodXY_uid226_pT1_uid211_sinPiZPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid226_pT1_uid211_sinPiZPolyEval_a),15)) * SIGNED(prodXY_uid226_pT1_uid211_sinPiZPolyEval_b);
prodXY_uid226_pT1_uid211_sinPiZPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid226_pT1_uid211_sinPiZPolyEval_a <= (others => '0');
prodXY_uid226_pT1_uid211_sinPiZPolyEval_b <= (others => '0');
prodXY_uid226_pT1_uid211_sinPiZPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid226_pT1_uid211_sinPiZPolyEval_a <= ld_reg_yT1_uid210_sinPiZPolyEval_0_to_prodXY_uid226_pT1_uid211_sinPiZPolyEval_0_q_to_prodXY_uid226_pT1_uid211_sinPiZPolyEval_a_q;
prodXY_uid226_pT1_uid211_sinPiZPolyEval_b <= memoryC2_uid209_sinPiZTableGenerator_q;
prodXY_uid226_pT1_uid211_sinPiZPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid226_pT1_uid211_sinPiZPolyEval_pr,28));
END IF;
END IF;
END PROCESS;
prodXY_uid226_pT1_uid211_sinPiZPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid226_pT1_uid211_sinPiZPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid226_pT1_uid211_sinPiZPolyEval_q <= prodXY_uid226_pT1_uid211_sinPiZPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid227_pT1_uid211_sinPiZPolyEval(BITSELECT,226)@8
prodXYTruncFR_uid227_pT1_uid211_sinPiZPolyEval_in <= prodXY_uid226_pT1_uid211_sinPiZPolyEval_q;
prodXYTruncFR_uid227_pT1_uid211_sinPiZPolyEval_b <= prodXYTruncFR_uid227_pT1_uid211_sinPiZPolyEval_in(27 downto 13);
--highBBits_uid213_sinPiZPolyEval(BITSELECT,212)@8
highBBits_uid213_sinPiZPolyEval_in <= prodXYTruncFR_uid227_pT1_uid211_sinPiZPolyEval_b;
highBBits_uid213_sinPiZPolyEval_b <= highBBits_uid213_sinPiZPolyEval_in(14 downto 1);
--ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_notEnable(LOGICAL,557)
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_notEnable_a <= en;
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_notEnable_q <= not ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_notEnable_a;
--ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_nor(LOGICAL,596)
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_nor_a <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_notEnable_q;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_nor_b <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_sticky_ena_q;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_nor_q <= not (ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_nor_a or ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_nor_b);
--ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_mem_top(CONSTANT,592)
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_mem_top_q <= "010";
--ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_cmp(LOGICAL,593)
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_cmp_a <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_mem_top_q;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdmux_q);
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_cmp_q <= "1" when ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_cmp_a = ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_cmp_b else "0";
--ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_cmpReg(REG,594)
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_cmpReg_q <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_sticky_ena(REG,597)
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_nor_q = "1") THEN
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_sticky_ena_q <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_enaAnd(LOGICAL,598)
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_enaAnd_a <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_sticky_ena_q;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_enaAnd_b <= en;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_enaAnd_q <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_enaAnd_a and ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_enaAnd_b;
--ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt(COUNTER,588)
-- every=1, low=0, high=2, step=1, init=1
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt_i <= TO_UNSIGNED(1,2);
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt_i = 1 THEN
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt_eq = '1') THEN
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt_i <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt_i - 2;
ELSE
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt_i <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt_i,2));
--ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdreg(REG,589)
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdreg_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdreg_q <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdmux(MUX,590)
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdmux_s <= en;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdmux: PROCESS (ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdmux_s, ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdreg_q, ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdmux_s IS
WHEN "0" => ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdmux_q <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdreg_q;
WHEN "1" => ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdmux_q <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem(DUALMEM,587)
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_reset0 <= areset;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_ia <= reg_zAddr_uid62_fpCosPiTest_0_to_memoryC2_uid209_sinPiZTableGenerator_0_q;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_aa <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdreg_q;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_ab <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdmux_q;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 7,
widthad_a => 2,
numwords_a => 3,
width_b => 7,
widthad_b => 2,
numwords_b => 3,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_iq,
address_a => ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_aa,
data_a => ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_ia
);
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_q <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_iq(6 downto 0);
--memoryC1_uid208_sinPiZTableGenerator(LOOKUP,207)@8
memoryC1_uid208_sinPiZTableGenerator: PROCESS (ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_q)
BEGIN
-- Begin reserved scope level
CASE (ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_mem_q) IS
WHEN "0000000" => memoryC1_uid208_sinPiZTableGenerator_q <= "000000000000000000001";
WHEN "0000001" => memoryC1_uid208_sinPiZTableGenerator_q <= "111111101011010101010";
WHEN "0000010" => memoryC1_uid208_sinPiZTableGenerator_q <= "111111010110101010001";
WHEN "0000011" => memoryC1_uid208_sinPiZTableGenerator_q <= "111111000001111111100";
WHEN "0000100" => memoryC1_uid208_sinPiZTableGenerator_q <= "111110101101010101010";
WHEN "0000101" => memoryC1_uid208_sinPiZTableGenerator_q <= "111110011000101011101";
WHEN "0000110" => memoryC1_uid208_sinPiZTableGenerator_q <= "111110000100000010101";
WHEN "0000111" => memoryC1_uid208_sinPiZTableGenerator_q <= "111101101111011010001";
WHEN "0001000" => memoryC1_uid208_sinPiZTableGenerator_q <= "111101011010110010101";
WHEN "0001001" => memoryC1_uid208_sinPiZTableGenerator_q <= "111101000110001011111";
WHEN "0001010" => memoryC1_uid208_sinPiZTableGenerator_q <= "111100110001100110010";
WHEN "0001011" => memoryC1_uid208_sinPiZTableGenerator_q <= "111100011101000010000";
WHEN "0001100" => memoryC1_uid208_sinPiZTableGenerator_q <= "111100001000011110111";
WHEN "0001101" => memoryC1_uid208_sinPiZTableGenerator_q <= "111011110011111101011";
WHEN "0001110" => memoryC1_uid208_sinPiZTableGenerator_q <= "111011011111011101011";
WHEN "0001111" => memoryC1_uid208_sinPiZTableGenerator_q <= "111011001010111110111";
WHEN "0010000" => memoryC1_uid208_sinPiZTableGenerator_q <= "111010110110100010101";
WHEN "0010001" => memoryC1_uid208_sinPiZTableGenerator_q <= "111010100010000111100";
WHEN "0010010" => memoryC1_uid208_sinPiZTableGenerator_q <= "111010001101101111000";
WHEN "0010011" => memoryC1_uid208_sinPiZTableGenerator_q <= "111001111001011000011";
WHEN "0010100" => memoryC1_uid208_sinPiZTableGenerator_q <= "111001100101000100010";
WHEN "0010101" => memoryC1_uid208_sinPiZTableGenerator_q <= "111001010000110010001";
WHEN "0010110" => memoryC1_uid208_sinPiZTableGenerator_q <= "111000111100100010111";
WHEN "0010111" => memoryC1_uid208_sinPiZTableGenerator_q <= "111000101000010110001";
WHEN "0011000" => memoryC1_uid208_sinPiZTableGenerator_q <= "111000010100001011111";
WHEN "0011001" => memoryC1_uid208_sinPiZTableGenerator_q <= "111000000000000100110";
WHEN "0011010" => memoryC1_uid208_sinPiZTableGenerator_q <= "110111101100000000011";
WHEN "0011011" => memoryC1_uid208_sinPiZTableGenerator_q <= "110111010111111111000";
WHEN "0011100" => memoryC1_uid208_sinPiZTableGenerator_q <= "110111000100000001000";
WHEN "0011101" => memoryC1_uid208_sinPiZTableGenerator_q <= "110110110000000110101";
WHEN "0011110" => memoryC1_uid208_sinPiZTableGenerator_q <= "110110011100001110111";
WHEN "0011111" => memoryC1_uid208_sinPiZTableGenerator_q <= "110110001000011011000";
WHEN "0100000" => memoryC1_uid208_sinPiZTableGenerator_q <= "110101110100101011010";
WHEN "0100001" => memoryC1_uid208_sinPiZTableGenerator_q <= "110101100000111110101";
WHEN "0100010" => memoryC1_uid208_sinPiZTableGenerator_q <= "110101001101010110010";
WHEN "0100011" => memoryC1_uid208_sinPiZTableGenerator_q <= "110100111001110001011";
WHEN "0100100" => memoryC1_uid208_sinPiZTableGenerator_q <= "110100100110010001001";
WHEN "0100101" => memoryC1_uid208_sinPiZTableGenerator_q <= "110100010010110100110";
WHEN "0100110" => memoryC1_uid208_sinPiZTableGenerator_q <= "110011111111011100110";
WHEN "0100111" => memoryC1_uid208_sinPiZTableGenerator_q <= "110011101100001001010";
WHEN "0101000" => memoryC1_uid208_sinPiZTableGenerator_q <= "110011011000111010011";
WHEN "0101001" => memoryC1_uid208_sinPiZTableGenerator_q <= "110011000101101111111";
WHEN "0101010" => memoryC1_uid208_sinPiZTableGenerator_q <= "110010110010101010010";
WHEN "0101011" => memoryC1_uid208_sinPiZTableGenerator_q <= "110010011111101001101";
WHEN "0101100" => memoryC1_uid208_sinPiZTableGenerator_q <= "110010001100101110000";
WHEN "0101101" => memoryC1_uid208_sinPiZTableGenerator_q <= "110001111001110111001";
WHEN "0101110" => memoryC1_uid208_sinPiZTableGenerator_q <= "110001100111000110000";
WHEN "0101111" => memoryC1_uid208_sinPiZTableGenerator_q <= "110001010100011001011";
WHEN "0110000" => memoryC1_uid208_sinPiZTableGenerator_q <= "110001000001110010110";
WHEN "0110001" => memoryC1_uid208_sinPiZTableGenerator_q <= "110000101111010001100";
WHEN "0110010" => memoryC1_uid208_sinPiZTableGenerator_q <= "110000011100110110001";
WHEN "0110011" => memoryC1_uid208_sinPiZTableGenerator_q <= "110000001010011111111";
WHEN "0110100" => memoryC1_uid208_sinPiZTableGenerator_q <= "101111111000010000000";
WHEN "0110101" => memoryC1_uid208_sinPiZTableGenerator_q <= "101111100110000101100";
WHEN "0110110" => memoryC1_uid208_sinPiZTableGenerator_q <= "101111010100000001100";
WHEN "0110111" => memoryC1_uid208_sinPiZTableGenerator_q <= "101111000010000011001";
WHEN "0111000" => memoryC1_uid208_sinPiZTableGenerator_q <= "101110110000001011100";
WHEN "0111001" => memoryC1_uid208_sinPiZTableGenerator_q <= "101110011110011001110";
WHEN "0111010" => memoryC1_uid208_sinPiZTableGenerator_q <= "101110001100101110101";
WHEN "0111011" => memoryC1_uid208_sinPiZTableGenerator_q <= "101101111011001010001";
WHEN "0111100" => memoryC1_uid208_sinPiZTableGenerator_q <= "101101101001101100010";
WHEN "0111101" => memoryC1_uid208_sinPiZTableGenerator_q <= "101101011000010101010";
WHEN "0111110" => memoryC1_uid208_sinPiZTableGenerator_q <= "101101000111000100101";
WHEN "0111111" => memoryC1_uid208_sinPiZTableGenerator_q <= "101100110101111010111";
WHEN "1000000" => memoryC1_uid208_sinPiZTableGenerator_q <= "101100100100111000010";
WHEN "1000001" => memoryC1_uid208_sinPiZTableGenerator_q <= "101100010011111100111";
WHEN "1000010" => memoryC1_uid208_sinPiZTableGenerator_q <= "101100000011001000111";
WHEN "1000011" => memoryC1_uid208_sinPiZTableGenerator_q <= "101011110010011100000";
WHEN "1000100" => memoryC1_uid208_sinPiZTableGenerator_q <= "101011100001110110100";
WHEN "1000101" => memoryC1_uid208_sinPiZTableGenerator_q <= "101011010001011000100";
WHEN "1000110" => memoryC1_uid208_sinPiZTableGenerator_q <= "101011000001000001110";
WHEN "1000111" => memoryC1_uid208_sinPiZTableGenerator_q <= "101010110000110011000";
WHEN "1001000" => memoryC1_uid208_sinPiZTableGenerator_q <= "101010100000101011111";
WHEN "1001001" => memoryC1_uid208_sinPiZTableGenerator_q <= "101010010000101100100";
WHEN "1001010" => memoryC1_uid208_sinPiZTableGenerator_q <= "101010000000110101001";
WHEN "1001011" => memoryC1_uid208_sinPiZTableGenerator_q <= "101001110001000110000";
WHEN "1001100" => memoryC1_uid208_sinPiZTableGenerator_q <= "101001100001011110101";
WHEN "1001101" => memoryC1_uid208_sinPiZTableGenerator_q <= "101001010001111111111";
WHEN "1001110" => memoryC1_uid208_sinPiZTableGenerator_q <= "101001000010101000110";
WHEN "1001111" => memoryC1_uid208_sinPiZTableGenerator_q <= "101000110011011010001";
WHEN "1010000" => memoryC1_uid208_sinPiZTableGenerator_q <= "101000100100010100001";
WHEN "1010001" => memoryC1_uid208_sinPiZTableGenerator_q <= "101000010101010110100";
WHEN "1010010" => memoryC1_uid208_sinPiZTableGenerator_q <= "101000000110100001011";
WHEN "1010011" => memoryC1_uid208_sinPiZTableGenerator_q <= "100111110111110101011";
WHEN "1010100" => memoryC1_uid208_sinPiZTableGenerator_q <= "100111101001010010000";
WHEN "1010101" => memoryC1_uid208_sinPiZTableGenerator_q <= "100111011010110110110";
WHEN "1010110" => memoryC1_uid208_sinPiZTableGenerator_q <= "100111001100100101100";
WHEN "1010111" => memoryC1_uid208_sinPiZTableGenerator_q <= "100110111110011100011";
WHEN "1011000" => memoryC1_uid208_sinPiZTableGenerator_q <= "100110110000011100011";
WHEN "1011001" => memoryC1_uid208_sinPiZTableGenerator_q <= "100110100010100101110";
WHEN "1011010" => memoryC1_uid208_sinPiZTableGenerator_q <= "100110010100111000101";
WHEN "1011011" => memoryC1_uid208_sinPiZTableGenerator_q <= "100110000111010100001";
WHEN "1011100" => memoryC1_uid208_sinPiZTableGenerator_q <= "100101111001111001000";
WHEN "1011101" => memoryC1_uid208_sinPiZTableGenerator_q <= "100101101100100111111";
WHEN "1011110" => memoryC1_uid208_sinPiZTableGenerator_q <= "100101011111100000000";
WHEN "1011111" => memoryC1_uid208_sinPiZTableGenerator_q <= "100101010010100001001";
WHEN "1100000" => memoryC1_uid208_sinPiZTableGenerator_q <= "100101000101101100011";
WHEN "1100001" => memoryC1_uid208_sinPiZTableGenerator_q <= "100100111001000001011";
WHEN "1100010" => memoryC1_uid208_sinPiZTableGenerator_q <= "100100101100011111111";
WHEN "1100011" => memoryC1_uid208_sinPiZTableGenerator_q <= "100100100000001000010";
WHEN "1100100" => memoryC1_uid208_sinPiZTableGenerator_q <= "100100010011111010101";
WHEN "1100101" => memoryC1_uid208_sinPiZTableGenerator_q <= "100100000111110111001";
WHEN "1100110" => memoryC1_uid208_sinPiZTableGenerator_q <= "100011111011111101010";
WHEN "1100111" => memoryC1_uid208_sinPiZTableGenerator_q <= "100011110000001101010";
WHEN "1101000" => memoryC1_uid208_sinPiZTableGenerator_q <= "100011100100100111101";
WHEN "1101001" => memoryC1_uid208_sinPiZTableGenerator_q <= "100011011001001011111";
WHEN "1101010" => memoryC1_uid208_sinPiZTableGenerator_q <= "100011001101111011010";
WHEN "1101011" => memoryC1_uid208_sinPiZTableGenerator_q <= "100011000010110100001";
WHEN "1101100" => memoryC1_uid208_sinPiZTableGenerator_q <= "100010110111110111010";
WHEN "1101101" => memoryC1_uid208_sinPiZTableGenerator_q <= "100010101101000101000";
WHEN "1101110" => memoryC1_uid208_sinPiZTableGenerator_q <= "100010100010011101001";
WHEN "1101111" => memoryC1_uid208_sinPiZTableGenerator_q <= "100010011000000000001";
WHEN "1110000" => memoryC1_uid208_sinPiZTableGenerator_q <= "100010001101101101010";
WHEN "1110001" => memoryC1_uid208_sinPiZTableGenerator_q <= "100010000011100100111";
WHEN "1110010" => memoryC1_uid208_sinPiZTableGenerator_q <= "100001111001100111100";
WHEN "1110011" => memoryC1_uid208_sinPiZTableGenerator_q <= "100001101111110100101";
WHEN "1110100" => memoryC1_uid208_sinPiZTableGenerator_q <= "100001100110001100100";
WHEN "1110101" => memoryC1_uid208_sinPiZTableGenerator_q <= "100001011100101111001";
WHEN "1110110" => memoryC1_uid208_sinPiZTableGenerator_q <= "100001010011011100011";
WHEN "1110111" => memoryC1_uid208_sinPiZTableGenerator_q <= "100001001010010100101";
WHEN "1111000" => memoryC1_uid208_sinPiZTableGenerator_q <= "100001000001011000000";
WHEN "1111001" => memoryC1_uid208_sinPiZTableGenerator_q <= "100000111000100110100";
WHEN "1111010" => memoryC1_uid208_sinPiZTableGenerator_q <= "100000101111111111100";
WHEN "1111011" => memoryC1_uid208_sinPiZTableGenerator_q <= "100000100111100011111";
WHEN "1111100" => memoryC1_uid208_sinPiZTableGenerator_q <= "100000011111010011000";
WHEN "1111101" => memoryC1_uid208_sinPiZTableGenerator_q <= "100000010111001101010";
WHEN "1111110" => memoryC1_uid208_sinPiZTableGenerator_q <= "100000001111010010101";
WHEN "1111111" => memoryC1_uid208_sinPiZTableGenerator_q <= "100000000111100011001";
WHEN OTHERS =>
memoryC1_uid208_sinPiZTableGenerator_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--sumAHighB_uid214_sinPiZPolyEval(ADD,213)@8
sumAHighB_uid214_sinPiZPolyEval_a <= STD_LOGIC_VECTOR((21 downto 21 => memoryC1_uid208_sinPiZTableGenerator_q(20)) & memoryC1_uid208_sinPiZTableGenerator_q);
sumAHighB_uid214_sinPiZPolyEval_b <= STD_LOGIC_VECTOR((21 downto 14 => highBBits_uid213_sinPiZPolyEval_b(13)) & highBBits_uid213_sinPiZPolyEval_b);
sumAHighB_uid214_sinPiZPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid214_sinPiZPolyEval_a) + SIGNED(sumAHighB_uid214_sinPiZPolyEval_b));
sumAHighB_uid214_sinPiZPolyEval_q <= sumAHighB_uid214_sinPiZPolyEval_o(21 downto 0);
--lowRangeB_uid212_sinPiZPolyEval(BITSELECT,211)@8
lowRangeB_uid212_sinPiZPolyEval_in <= prodXYTruncFR_uid227_pT1_uid211_sinPiZPolyEval_b(0 downto 0);
lowRangeB_uid212_sinPiZPolyEval_b <= lowRangeB_uid212_sinPiZPolyEval_in(0 downto 0);
--s1_uid212_uid215_sinPiZPolyEval(BITJOIN,214)@8
s1_uid212_uid215_sinPiZPolyEval_q <= sumAHighB_uid214_sinPiZPolyEval_q & lowRangeB_uid212_sinPiZPolyEval_b;
--reg_s1_uid212_uid215_sinPiZPolyEval_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_1(REG,267)@8
reg_s1_uid212_uid215_sinPiZPolyEval_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_s1_uid212_uid215_sinPiZPolyEval_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_1_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_s1_uid212_uid215_sinPiZPolyEval_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_1_q <= s1_uid212_uid215_sinPiZPolyEval_q;
END IF;
END IF;
END PROCESS;
--ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_nor(LOGICAL,609)
ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_nor_a <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_notEnable_q;
ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_nor_b <= ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_sticky_ena_q;
ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_nor_q <= not (ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_nor_a or ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_nor_b);
--ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_sticky_ena(REG,610)
ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_nor_q = "1") THEN
ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_sticky_ena_q <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_enaAnd(LOGICAL,611)
ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_enaAnd_a <= ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_sticky_ena_q;
ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_enaAnd_b <= en;
ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_enaAnd_q <= ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_enaAnd_a and ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_enaAnd_b;
--ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_inputreg(DELAY,599)
ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 16, depth => 1 )
PORT MAP ( xin => zPPolyEval_uid63_fpCosPiTest_b, xout => ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem(DUALMEM,600)
ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_reset0 <= areset;
ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_ia <= ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_inputreg_q;
ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_aa <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdreg_q;
ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_ab <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdmux_q;
ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 16,
widthad_a => 2,
numwords_a => 3,
width_b => 16,
widthad_b => 2,
numwords_b => 3,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_iq,
address_a => ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_aa,
data_a => ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_ia
);
ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_q <= ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_iq(15 downto 0);
--reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0(REG,266)@8
reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_q <= ld_zPPolyEval_uid63_fpCosPiTest_b_to_reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--prodXY_uid229_pT2_uid217_sinPiZPolyEval(MULT,228)@9
prodXY_uid229_pT2_uid217_sinPiZPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid229_pT2_uid217_sinPiZPolyEval_a),17)) * SIGNED(prodXY_uid229_pT2_uid217_sinPiZPolyEval_b);
prodXY_uid229_pT2_uid217_sinPiZPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid229_pT2_uid217_sinPiZPolyEval_a <= (others => '0');
prodXY_uid229_pT2_uid217_sinPiZPolyEval_b <= (others => '0');
prodXY_uid229_pT2_uid217_sinPiZPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid229_pT2_uid217_sinPiZPolyEval_a <= reg_zPPolyEval_uid63_fpCosPiTest_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_0_q;
prodXY_uid229_pT2_uid217_sinPiZPolyEval_b <= reg_s1_uid212_uid215_sinPiZPolyEval_0_to_prodXY_uid229_pT2_uid217_sinPiZPolyEval_1_q;
prodXY_uid229_pT2_uid217_sinPiZPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid229_pT2_uid217_sinPiZPolyEval_pr,39));
END IF;
END IF;
END PROCESS;
prodXY_uid229_pT2_uid217_sinPiZPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid229_pT2_uid217_sinPiZPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid229_pT2_uid217_sinPiZPolyEval_q <= prodXY_uid229_pT2_uid217_sinPiZPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid230_pT2_uid217_sinPiZPolyEval(BITSELECT,229)@12
prodXYTruncFR_uid230_pT2_uid217_sinPiZPolyEval_in <= prodXY_uid229_pT2_uid217_sinPiZPolyEval_q;
prodXYTruncFR_uid230_pT2_uid217_sinPiZPolyEval_b <= prodXYTruncFR_uid230_pT2_uid217_sinPiZPolyEval_in(38 downto 15);
--highBBits_uid219_sinPiZPolyEval(BITSELECT,218)@12
highBBits_uid219_sinPiZPolyEval_in <= prodXYTruncFR_uid230_pT2_uid217_sinPiZPolyEval_b;
highBBits_uid219_sinPiZPolyEval_b <= highBBits_uid219_sinPiZPolyEval_in(23 downto 2);
--ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_nor(LOGICAL,584)
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_nor_a <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_notEnable_q;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_nor_b <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_sticky_ena_q;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_nor_q <= not (ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_nor_a or ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_nor_b);
--ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_mem_top(CONSTANT,554)
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_mem_top_q <= "0110";
--ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_cmp(LOGICAL,555)
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_cmp_a <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_mem_top_q;
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdmux_q);
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_cmp_q <= "1" when ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_cmp_a = ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_cmp_b else "0";
--ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_cmpReg(REG,556)
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_cmpReg_q <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_sticky_ena(REG,585)
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_nor_q = "1") THEN
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_sticky_ena_q <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_enaAnd(LOGICAL,586)
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_enaAnd_a <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_sticky_ena_q;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_enaAnd_b <= en;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_enaAnd_q <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_enaAnd_a and ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_enaAnd_b;
--ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt(COUNTER,550)
-- every=1, low=0, high=6, step=1, init=1
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt_i = 5 THEN
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt_eq <= '1';
ELSE
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt_eq = '1') THEN
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt_i <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt_i - 6;
ELSE
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt_i <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt_i,3));
--ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdreg(REG,551)
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdreg_q <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdmux(MUX,552)
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdmux_s <= en;
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdmux: PROCESS (ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdmux_s, ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdreg_q, ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt_q)
BEGIN
CASE ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdmux_s IS
WHEN "0" => ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdmux_q <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdreg_q;
WHEN "1" => ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdmux_q <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem(DUALMEM,575)
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_reset0 <= areset;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_ia <= reg_zAddr_uid62_fpCosPiTest_0_to_memoryC2_uid209_sinPiZTableGenerator_0_q;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_aa <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdreg_q;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_ab <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdmux_q;
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 7,
widthad_a => 3,
numwords_a => 7,
width_b => 7,
widthad_b => 3,
numwords_b => 7,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_iq,
address_a => ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_aa,
data_a => ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_ia
);
ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_q <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_iq(6 downto 0);
--memoryC0_uid207_sinPiZTableGenerator(LOOKUP,206)@12
memoryC0_uid207_sinPiZTableGenerator: PROCESS (ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_q)
BEGIN
-- Begin reserved scope level
CASE (ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC0_uid207_sinPiZTableGenerator_0_q_to_memoryC0_uid207_sinPiZTableGenerator_a_replace_mem_q) IS
WHEN "0000000" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100100100001111110110101110";
WHEN "0000001" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100100100001110100100000010";
WHEN "0000010" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100100100001010101100000000";
WHEN "0000011" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100100100000100001110101000";
WHEN "0000100" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100100011111011001011111101";
WHEN "0000101" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100100011101111100100000010";
WHEN "0000110" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100100011100001010110111011";
WHEN "0000111" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100100011010000100100101111";
WHEN "0001000" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100100010111101001101100010";
WHEN "0001001" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100100010100111010001011101";
WHEN "0001010" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100100010001110110000100111";
WHEN "0001011" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100100001110011101011001001";
WHEN "0001100" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100100001010110000001001110";
WHEN "0001101" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100100000110101110011000000";
WHEN "0001110" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100100000010011000000101011";
WHEN "0001111" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100011111101101101010011101";
WHEN "0010000" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100011111000101110000100010";
WHEN "0010001" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100011110011011010011001011";
WHEN "0010010" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100011101101110010010100101";
WHEN "0010011" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100011100111110101111000011";
WHEN "0010100" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100011100001100101000110101";
WHEN "0010101" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100011011011000000000001111";
WHEN "0010110" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100011010100000110101100011";
WHEN "0010111" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100011001100111001001000110";
WHEN "0011000" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100011000101010111011001110";
WHEN "0011001" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100010111101100001100010000";
WHEN "0011010" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100010110101010111100100100";
WHEN "0011011" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100010101100111001100100010";
WHEN "0011100" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100010100100000111100100011";
WHEN "0011101" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100010011011000001101000000";
WHEN "0011110" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100010010001100111110010110";
WHEN "0011111" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100010000111111010000111111";
WHEN "0100000" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100001111101111000101010111";
WHEN "0100001" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100001110011100011011111110";
WHEN "0100010" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100001101000111010101010001";
WHEN "0100011" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100001011101111110001110000";
WHEN "0100100" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100001010010101110001111010";
WHEN "0100101" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100001000111001010110010010";
WHEN "0100110" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100000111011010011111011001";
WHEN "0100111" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100000101111001001101110010";
WHEN "0101000" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100000100010101100010000001";
WHEN "0101001" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100000010101111011100101011";
WHEN "0101010" => memoryC0_uid207_sinPiZTableGenerator_q <= "01100000001000110111110010101";
WHEN "0101011" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011111111011100000111100110";
WHEN "0101100" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011111101101110111001000101";
WHEN "0101101" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011111011111111010011011011";
WHEN "0101110" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011111010001101010111001111";
WHEN "0101111" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011111000011001000101001110";
WHEN "0110000" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011110110100010011110000000";
WHEN "0110001" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011110100101001100010010010";
WHEN "0110010" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011110010101110010010110000";
WHEN "0110011" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011110000110000110000001000";
WHEN "0110100" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011101110110000111011000111";
WHEN "0110101" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011101100101110110100011101";
WHEN "0110110" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011101010101010011100111001";
WHEN "0110111" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011101000100011110101001100";
WHEN "0111000" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011100110011010111110000111";
WHEN "0111001" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011100100001111111000011101";
WHEN "0111010" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011100010000010100101000000";
WHEN "0111011" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011011111110011000100100100";
WHEN "0111100" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011011101100001010111111110";
WHEN "0111101" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011011011001101100000000011";
WHEN "0111110" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011011000110111011101101010";
WHEN "0111111" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011010110011111010001101001";
WHEN "1000000" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011010100000100111100111000";
WHEN "1000001" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011010001101000100000001111";
WHEN "1000010" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011001111001001111100100111";
WHEN "1000011" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011001100101001010010111011";
WHEN "1000100" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011001010000110100100000101";
WHEN "1000101" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011000111100001110001000001";
WHEN "1000110" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011000100111010111010101011";
WHEN "1000111" => memoryC0_uid207_sinPiZTableGenerator_q <= "01011000010010010000001111111";
WHEN "1001000" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010111111100111000111111011";
WHEN "1001001" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010111100111010001101011110";
WHEN "1001010" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010111010001011010011100110";
WHEN "1001011" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010110111011010011011010011";
WHEN "1001100" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010110100100111100101100110";
WHEN "1001101" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010110001110010110011011111";
WHEN "1001110" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010101110111100000110000001";
WHEN "1001111" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010101100000011011110001110";
WHEN "1010000" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010101001001000111101001000";
WHEN "1010001" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010100110001100100011110100";
WHEN "1010010" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010100011001110010011010110";
WHEN "1010011" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010100000001110001100110010";
WHEN "1010100" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010011101001100010001001111";
WHEN "1010101" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010011010001000100001110100";
WHEN "1010110" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010010111000010111111100101";
WHEN "1010111" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010010011111011101011101100";
WHEN "1011000" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010010000110010100111010001";
WHEN "1011001" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010001101100111110011011011";
WHEN "1011010" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010001010011011010001010100";
WHEN "1011011" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010000111001101000010000111";
WHEN "1011100" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010000011111101000110111110";
WHEN "1011101" => memoryC0_uid207_sinPiZTableGenerator_q <= "01010000000101011100001000010";
WHEN "1011110" => memoryC0_uid207_sinPiZTableGenerator_q <= "01001111101011000010001100001";
WHEN "1011111" => memoryC0_uid207_sinPiZTableGenerator_q <= "01001111010000011011001100111";
WHEN "1100000" => memoryC0_uid207_sinPiZTableGenerator_q <= "01001110110101100111010011111";
WHEN "1100001" => memoryC0_uid207_sinPiZTableGenerator_q <= "01001110011010100110101010111";
WHEN "1100010" => memoryC0_uid207_sinPiZTableGenerator_q <= "01001101111111011001011011101";
WHEN "1100011" => memoryC0_uid207_sinPiZTableGenerator_q <= "01001101100011111111101111111";
WHEN "1100100" => memoryC0_uid207_sinPiZTableGenerator_q <= "01001101001000011001110001011";
WHEN "1100101" => memoryC0_uid207_sinPiZTableGenerator_q <= "01001100101100100111101010001";
WHEN "1100110" => memoryC0_uid207_sinPiZTableGenerator_q <= "01001100010000101001100100001";
WHEN "1100111" => memoryC0_uid207_sinPiZTableGenerator_q <= "01001011110100011111101001011";
WHEN "1101000" => memoryC0_uid207_sinPiZTableGenerator_q <= "01001011011000001010000011111";
WHEN "1101001" => memoryC0_uid207_sinPiZTableGenerator_q <= "01001010111011101000111101111";
WHEN "1101010" => memoryC0_uid207_sinPiZTableGenerator_q <= "01001010011110111100100001011";
WHEN "1101011" => memoryC0_uid207_sinPiZTableGenerator_q <= "01001010000010000100111000111";
WHEN "1101100" => memoryC0_uid207_sinPiZTableGenerator_q <= "01001001100101000010001110101";
WHEN "1101101" => memoryC0_uid207_sinPiZTableGenerator_q <= "01001001000111110100101100111";
WHEN "1101110" => memoryC0_uid207_sinPiZTableGenerator_q <= "01001000101010011100011110001";
WHEN "1101111" => memoryC0_uid207_sinPiZTableGenerator_q <= "01001000001100111001101100110";
WHEN "1110000" => memoryC0_uid207_sinPiZTableGenerator_q <= "01000111101111001100100011011";
WHEN "1110001" => memoryC0_uid207_sinPiZTableGenerator_q <= "01000111010001010101001100101";
WHEN "1110010" => memoryC0_uid207_sinPiZTableGenerator_q <= "01000110110011010011110010111";
WHEN "1110011" => memoryC0_uid207_sinPiZTableGenerator_q <= "01000110010101001000100001000";
WHEN "1110100" => memoryC0_uid207_sinPiZTableGenerator_q <= "01000101110110110011100001101";
WHEN "1110101" => memoryC0_uid207_sinPiZTableGenerator_q <= "01000101011000010100111111100";
WHEN "1110110" => memoryC0_uid207_sinPiZTableGenerator_q <= "01000100111001101101000101100";
WHEN "1110111" => memoryC0_uid207_sinPiZTableGenerator_q <= "01000100011010111011111110011";
WHEN "1111000" => memoryC0_uid207_sinPiZTableGenerator_q <= "01000011111100000001110101000";
WHEN "1111001" => memoryC0_uid207_sinPiZTableGenerator_q <= "01000011011100111110110100010";
WHEN "1111010" => memoryC0_uid207_sinPiZTableGenerator_q <= "01000010111101110011000111010";
WHEN "1111011" => memoryC0_uid207_sinPiZTableGenerator_q <= "01000010011110011110111000111";
WHEN "1111100" => memoryC0_uid207_sinPiZTableGenerator_q <= "01000001111111000010010100010";
WHEN "1111101" => memoryC0_uid207_sinPiZTableGenerator_q <= "01000001011111011101100100011";
WHEN "1111110" => memoryC0_uid207_sinPiZTableGenerator_q <= "01000000111111110000110100011";
WHEN "1111111" => memoryC0_uid207_sinPiZTableGenerator_q <= "01000000011111111100001111011";
WHEN OTHERS =>
memoryC0_uid207_sinPiZTableGenerator_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--sumAHighB_uid220_sinPiZPolyEval(ADD,219)@12
sumAHighB_uid220_sinPiZPolyEval_a <= STD_LOGIC_VECTOR((29 downto 29 => memoryC0_uid207_sinPiZTableGenerator_q(28)) & memoryC0_uid207_sinPiZTableGenerator_q);
sumAHighB_uid220_sinPiZPolyEval_b <= STD_LOGIC_VECTOR((29 downto 22 => highBBits_uid219_sinPiZPolyEval_b(21)) & highBBits_uid219_sinPiZPolyEval_b);
sumAHighB_uid220_sinPiZPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid220_sinPiZPolyEval_a) + SIGNED(sumAHighB_uid220_sinPiZPolyEval_b));
sumAHighB_uid220_sinPiZPolyEval_q <= sumAHighB_uid220_sinPiZPolyEval_o(29 downto 0);
--lowRangeB_uid218_sinPiZPolyEval(BITSELECT,217)@12
lowRangeB_uid218_sinPiZPolyEval_in <= prodXYTruncFR_uid230_pT2_uid217_sinPiZPolyEval_b(1 downto 0);
lowRangeB_uid218_sinPiZPolyEval_b <= lowRangeB_uid218_sinPiZPolyEval_in(1 downto 0);
--s2_uid218_uid221_sinPiZPolyEval(BITJOIN,220)@12
s2_uid218_uid221_sinPiZPolyEval_q <= sumAHighB_uid220_sinPiZPolyEval_q & lowRangeB_uid218_sinPiZPolyEval_b;
--fxpSinRes_uid65_fpCosPiTest(BITSELECT,64)@12
fxpSinRes_uid65_fpCosPiTest_in <= s2_uid218_uid221_sinPiZPolyEval_q(29 downto 0);
fxpSinRes_uid65_fpCosPiTest_b <= fxpSinRes_uid65_fpCosPiTest_in(29 downto 5);
--reg_fxpSinRes_uid65_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_1(REG,270)@12
reg_fxpSinRes_uid65_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fxpSinRes_uid65_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_1_q <= "0000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fxpSinRes_uid65_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_1_q <= fxpSinRes_uid65_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_nor(LOGICAL,622)
ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_nor_a <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_notEnable_q;
ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_nor_b <= ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_sticky_ena_q;
ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_nor_q <= not (ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_nor_a or ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_nor_b);
--ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_sticky_ena(REG,623)
ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_nor_q = "1") THEN
ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_sticky_ena_q <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_enaAnd(LOGICAL,624)
ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_enaAnd_a <= ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_sticky_ena_q;
ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_enaAnd_b <= en;
ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_enaAnd_q <= ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_enaAnd_a and ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_enaAnd_b;
--LeftShiftStage131dto0_uid202_alignedZ_uid57_fpCosPiTest(BITSELECT,201)@7
LeftShiftStage131dto0_uid202_alignedZ_uid57_fpCosPiTest_in <= leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_q(31 downto 0);
LeftShiftStage131dto0_uid202_alignedZ_uid57_fpCosPiTest_b <= LeftShiftStage131dto0_uid202_alignedZ_uid57_fpCosPiTest_in(31 downto 0);
--leftShiftStage2Idx3_uid203_alignedZ_uid57_fpCosPiTest(BITJOIN,202)@7
leftShiftStage2Idx3_uid203_alignedZ_uid57_fpCosPiTest_q <= LeftShiftStage131dto0_uid202_alignedZ_uid57_fpCosPiTest_b & leftShiftStage2Idx3Pad3_uid131_fxpX_uid41_fpCosPiTest_q;
--LeftShiftStage132dto0_uid199_alignedZ_uid57_fpCosPiTest(BITSELECT,198)@7
LeftShiftStage132dto0_uid199_alignedZ_uid57_fpCosPiTest_in <= leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_q(32 downto 0);
LeftShiftStage132dto0_uid199_alignedZ_uid57_fpCosPiTest_b <= LeftShiftStage132dto0_uid199_alignedZ_uid57_fpCosPiTest_in(32 downto 0);
--leftShiftStage2Idx2_uid200_alignedZ_uid57_fpCosPiTest(BITJOIN,199)@7
leftShiftStage2Idx2_uid200_alignedZ_uid57_fpCosPiTest_q <= LeftShiftStage132dto0_uid199_alignedZ_uid57_fpCosPiTest_b & leftShiftStage2Idx2Pad2_uid128_fxpX_uid41_fpCosPiTest_q;
--LeftShiftStage133dto0_uid196_alignedZ_uid57_fpCosPiTest(BITSELECT,195)@7
LeftShiftStage133dto0_uid196_alignedZ_uid57_fpCosPiTest_in <= leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_q(33 downto 0);
LeftShiftStage133dto0_uid196_alignedZ_uid57_fpCosPiTest_b <= LeftShiftStage133dto0_uid196_alignedZ_uid57_fpCosPiTest_in(33 downto 0);
--leftShiftStage2Idx1_uid197_alignedZ_uid57_fpCosPiTest(BITJOIN,196)@7
leftShiftStage2Idx1_uid197_alignedZ_uid57_fpCosPiTest_q <= LeftShiftStage133dto0_uid196_alignedZ_uid57_fpCosPiTest_b & GND_q;
--vStage_uid141_lzcZ_uid56_fpCosPiTest(BITSELECT,140)@3
vStage_uid141_lzcZ_uid56_fpCosPiTest_in <= z_uid54_fpCosPiTest_b(2 downto 0);
vStage_uid141_lzcZ_uid56_fpCosPiTest_b <= vStage_uid141_lzcZ_uid56_fpCosPiTest_in(2 downto 0);
--ld_vStage_uid141_lzcZ_uid56_fpCosPiTest_b_to_leftShiftStage0Idx2_uid180_alignedZ_uid57_fpCosPiTest_b(DELAY,450)@3
ld_vStage_uid141_lzcZ_uid56_fpCosPiTest_b_to_leftShiftStage0Idx2_uid180_alignedZ_uid57_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 3, depth => 3 )
PORT MAP ( xin => vStage_uid141_lzcZ_uid56_fpCosPiTest_b, xout => ld_vStage_uid141_lzcZ_uid56_fpCosPiTest_b_to_leftShiftStage0Idx2_uid180_alignedZ_uid57_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage0Idx2_uid180_alignedZ_uid57_fpCosPiTest(BITJOIN,179)@6
leftShiftStage0Idx2_uid180_alignedZ_uid57_fpCosPiTest_q <= ld_vStage_uid141_lzcZ_uid56_fpCosPiTest_b_to_leftShiftStage0Idx2_uid180_alignedZ_uid57_fpCosPiTest_b_q & leftShiftStage0Idx2Pad32_uid108_fxpX_uid41_fpCosPiTest_q;
--X18dto0_uid176_alignedZ_uid57_fpCosPiTest(BITSELECT,175)@3
X18dto0_uid176_alignedZ_uid57_fpCosPiTest_in <= z_uid54_fpCosPiTest_b(18 downto 0);
X18dto0_uid176_alignedZ_uid57_fpCosPiTest_b <= X18dto0_uid176_alignedZ_uid57_fpCosPiTest_in(18 downto 0);
--ld_X18dto0_uid176_alignedZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx1_uid177_alignedZ_uid57_fpCosPiTest_b_inputreg(DELAY,573)
ld_X18dto0_uid176_alignedZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx1_uid177_alignedZ_uid57_fpCosPiTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 19, depth => 1 )
PORT MAP ( xin => X18dto0_uid176_alignedZ_uid57_fpCosPiTest_b, xout => ld_X18dto0_uid176_alignedZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx1_uid177_alignedZ_uid57_fpCosPiTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_X18dto0_uid176_alignedZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx1_uid177_alignedZ_uid57_fpCosPiTest_b(DELAY,449)@3
ld_X18dto0_uid176_alignedZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx1_uid177_alignedZ_uid57_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 19, depth => 2 )
PORT MAP ( xin => ld_X18dto0_uid176_alignedZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx1_uid177_alignedZ_uid57_fpCosPiTest_b_inputreg_q, xout => ld_X18dto0_uid176_alignedZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx1_uid177_alignedZ_uid57_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage0Idx1_uid177_alignedZ_uid57_fpCosPiTest(BITJOIN,176)@6
leftShiftStage0Idx1_uid177_alignedZ_uid57_fpCosPiTest_q <= ld_X18dto0_uid176_alignedZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx1_uid177_alignedZ_uid57_fpCosPiTest_b_q & leftShiftStage0Idx1Pad16_uid105_fxpX_uid41_fpCosPiTest_q;
--ld_z_uid54_fpCosPiTest_b_to_leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_c_inputreg(DELAY,574)
ld_z_uid54_fpCosPiTest_b_to_leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 35, depth => 1 )
PORT MAP ( xin => z_uid54_fpCosPiTest_b, xout => ld_z_uid54_fpCosPiTest_b_to_leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_z_uid54_fpCosPiTest_b_to_leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_c(DELAY,453)@3
ld_z_uid54_fpCosPiTest_b_to_leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_c : dspba_delay
GENERIC MAP ( width => 35, depth => 2 )
PORT MAP ( xin => ld_z_uid54_fpCosPiTest_b_to_leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_c_inputreg_q, xout => ld_z_uid54_fpCosPiTest_b_to_leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--rVStage_uid138_lzcZ_uid56_fpCosPiTest(BITSELECT,137)@3
rVStage_uid138_lzcZ_uid56_fpCosPiTest_in <= z_uid54_fpCosPiTest_b;
rVStage_uid138_lzcZ_uid56_fpCosPiTest_b <= rVStage_uid138_lzcZ_uid56_fpCosPiTest_in(34 downto 3);
--reg_rVStage_uid138_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid139_lzcZ_uid56_fpCosPiTest_1(REG,247)@3
reg_rVStage_uid138_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid139_lzcZ_uid56_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid138_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid139_lzcZ_uid56_fpCosPiTest_1_q <= "00000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid138_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid139_lzcZ_uid56_fpCosPiTest_1_q <= rVStage_uid138_lzcZ_uid56_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid139_lzcZ_uid56_fpCosPiTest(LOGICAL,138)@4
vCount_uid139_lzcZ_uid56_fpCosPiTest_a <= reg_rVStage_uid138_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid139_lzcZ_uid56_fpCosPiTest_1_q;
vCount_uid139_lzcZ_uid56_fpCosPiTest_b <= leftShiftStage0Idx2Pad32_uid108_fxpX_uid41_fpCosPiTest_q;
vCount_uid139_lzcZ_uid56_fpCosPiTest_q <= "1" when vCount_uid139_lzcZ_uid56_fpCosPiTest_a = vCount_uid139_lzcZ_uid56_fpCosPiTest_b else "0";
--ld_vCount_uid139_lzcZ_uid56_fpCosPiTest_q_to_r_uid172_lzcZ_uid56_fpCosPiTest_f(DELAY,447)@4
ld_vCount_uid139_lzcZ_uid56_fpCosPiTest_q_to_r_uid172_lzcZ_uid56_fpCosPiTest_f : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => vCount_uid139_lzcZ_uid56_fpCosPiTest_q, xout => ld_vCount_uid139_lzcZ_uid56_fpCosPiTest_q_to_r_uid172_lzcZ_uid56_fpCosPiTest_f_q, ena => en(0), clk => clk, aclr => areset );
--mO_uid140_lzcZ_uid56_fpCosPiTest(CONSTANT,139)
mO_uid140_lzcZ_uid56_fpCosPiTest_q <= "11111111111111111111111111111";
--cStage_uid142_lzcZ_uid56_fpCosPiTest(BITJOIN,141)@3
cStage_uid142_lzcZ_uid56_fpCosPiTest_q <= vStage_uid141_lzcZ_uid56_fpCosPiTest_b & mO_uid140_lzcZ_uid56_fpCosPiTest_q;
--reg_cStage_uid142_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid144_lzcZ_uid56_fpCosPiTest_3(REG,249)@3
reg_cStage_uid142_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid144_lzcZ_uid56_fpCosPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cStage_uid142_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid144_lzcZ_uid56_fpCosPiTest_3_q <= "00000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cStage_uid142_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid144_lzcZ_uid56_fpCosPiTest_3_q <= cStage_uid142_lzcZ_uid56_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--vStagei_uid144_lzcZ_uid56_fpCosPiTest(MUX,143)@4
vStagei_uid144_lzcZ_uid56_fpCosPiTest_s <= vCount_uid139_lzcZ_uid56_fpCosPiTest_q;
vStagei_uid144_lzcZ_uid56_fpCosPiTest: PROCESS (vStagei_uid144_lzcZ_uid56_fpCosPiTest_s, en, reg_rVStage_uid138_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid139_lzcZ_uid56_fpCosPiTest_1_q, reg_cStage_uid142_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid144_lzcZ_uid56_fpCosPiTest_3_q)
BEGIN
CASE vStagei_uid144_lzcZ_uid56_fpCosPiTest_s IS
WHEN "0" => vStagei_uid144_lzcZ_uid56_fpCosPiTest_q <= reg_rVStage_uid138_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid139_lzcZ_uid56_fpCosPiTest_1_q;
WHEN "1" => vStagei_uid144_lzcZ_uid56_fpCosPiTest_q <= reg_cStage_uid142_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid144_lzcZ_uid56_fpCosPiTest_3_q;
WHEN OTHERS => vStagei_uid144_lzcZ_uid56_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid146_lzcZ_uid56_fpCosPiTest(BITSELECT,145)@4
rVStage_uid146_lzcZ_uid56_fpCosPiTest_in <= vStagei_uid144_lzcZ_uid56_fpCosPiTest_q;
rVStage_uid146_lzcZ_uid56_fpCosPiTest_b <= rVStage_uid146_lzcZ_uid56_fpCosPiTest_in(31 downto 16);
--reg_rVStage_uid146_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid147_lzcZ_uid56_fpCosPiTest_1(REG,250)@4
reg_rVStage_uid146_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid147_lzcZ_uid56_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid146_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid147_lzcZ_uid56_fpCosPiTest_1_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid146_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid147_lzcZ_uid56_fpCosPiTest_1_q <= rVStage_uid146_lzcZ_uid56_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid147_lzcZ_uid56_fpCosPiTest(LOGICAL,146)@5
vCount_uid147_lzcZ_uid56_fpCosPiTest_a <= reg_rVStage_uid146_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid147_lzcZ_uid56_fpCosPiTest_1_q;
vCount_uid147_lzcZ_uid56_fpCosPiTest_b <= leftShiftStage0Idx1Pad16_uid105_fxpX_uid41_fpCosPiTest_q;
vCount_uid147_lzcZ_uid56_fpCosPiTest_q <= "1" when vCount_uid147_lzcZ_uid56_fpCosPiTest_a = vCount_uid147_lzcZ_uid56_fpCosPiTest_b else "0";
--ld_vCount_uid147_lzcZ_uid56_fpCosPiTest_q_to_r_uid172_lzcZ_uid56_fpCosPiTest_e(DELAY,446)@5
ld_vCount_uid147_lzcZ_uid56_fpCosPiTest_q_to_r_uid172_lzcZ_uid56_fpCosPiTest_e : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vCount_uid147_lzcZ_uid56_fpCosPiTest_q, xout => ld_vCount_uid147_lzcZ_uid56_fpCosPiTest_q_to_r_uid172_lzcZ_uid56_fpCosPiTest_e_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid148_lzcZ_uid56_fpCosPiTest(BITSELECT,147)@4
vStage_uid148_lzcZ_uid56_fpCosPiTest_in <= vStagei_uid144_lzcZ_uid56_fpCosPiTest_q(15 downto 0);
vStage_uid148_lzcZ_uid56_fpCosPiTest_b <= vStage_uid148_lzcZ_uid56_fpCosPiTest_in(15 downto 0);
--reg_vStage_uid148_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid150_lzcZ_uid56_fpCosPiTest_3(REG,252)@4
reg_vStage_uid148_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid150_lzcZ_uid56_fpCosPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid148_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid150_lzcZ_uid56_fpCosPiTest_3_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid148_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid150_lzcZ_uid56_fpCosPiTest_3_q <= vStage_uid148_lzcZ_uid56_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid150_lzcZ_uid56_fpCosPiTest(MUX,149)@5
vStagei_uid150_lzcZ_uid56_fpCosPiTest_s <= vCount_uid147_lzcZ_uid56_fpCosPiTest_q;
vStagei_uid150_lzcZ_uid56_fpCosPiTest: PROCESS (vStagei_uid150_lzcZ_uid56_fpCosPiTest_s, en, reg_rVStage_uid146_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid147_lzcZ_uid56_fpCosPiTest_1_q, reg_vStage_uid148_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid150_lzcZ_uid56_fpCosPiTest_3_q)
BEGIN
CASE vStagei_uid150_lzcZ_uid56_fpCosPiTest_s IS
WHEN "0" => vStagei_uid150_lzcZ_uid56_fpCosPiTest_q <= reg_rVStage_uid146_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid147_lzcZ_uid56_fpCosPiTest_1_q;
WHEN "1" => vStagei_uid150_lzcZ_uid56_fpCosPiTest_q <= reg_vStage_uid148_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid150_lzcZ_uid56_fpCosPiTest_3_q;
WHEN OTHERS => vStagei_uid150_lzcZ_uid56_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid152_lzcZ_uid56_fpCosPiTest(BITSELECT,151)@5
rVStage_uid152_lzcZ_uid56_fpCosPiTest_in <= vStagei_uid150_lzcZ_uid56_fpCosPiTest_q;
rVStage_uid152_lzcZ_uid56_fpCosPiTest_b <= rVStage_uid152_lzcZ_uid56_fpCosPiTest_in(15 downto 8);
--vCount_uid153_lzcZ_uid56_fpCosPiTest(LOGICAL,152)@5
vCount_uid153_lzcZ_uid56_fpCosPiTest_a <= rVStage_uid152_lzcZ_uid56_fpCosPiTest_b;
vCount_uid153_lzcZ_uid56_fpCosPiTest_b <= cstAllZWE_uid21_fpCosPiTest_q;
vCount_uid153_lzcZ_uid56_fpCosPiTest_q <= "1" when vCount_uid153_lzcZ_uid56_fpCosPiTest_a = vCount_uid153_lzcZ_uid56_fpCosPiTest_b else "0";
--reg_vCount_uid153_lzcZ_uid56_fpCosPiTest_0_to_r_uid172_lzcZ_uid56_fpCosPiTest_3(REG,256)@5
reg_vCount_uid153_lzcZ_uid56_fpCosPiTest_0_to_r_uid172_lzcZ_uid56_fpCosPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid153_lzcZ_uid56_fpCosPiTest_0_to_r_uid172_lzcZ_uid56_fpCosPiTest_3_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid153_lzcZ_uid56_fpCosPiTest_0_to_r_uid172_lzcZ_uid56_fpCosPiTest_3_q <= vCount_uid153_lzcZ_uid56_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--vStage_uid154_lzcZ_uid56_fpCosPiTest(BITSELECT,153)@5
vStage_uid154_lzcZ_uid56_fpCosPiTest_in <= vStagei_uid150_lzcZ_uid56_fpCosPiTest_q(7 downto 0);
vStage_uid154_lzcZ_uid56_fpCosPiTest_b <= vStage_uid154_lzcZ_uid56_fpCosPiTest_in(7 downto 0);
--vStagei_uid156_lzcZ_uid56_fpCosPiTest(MUX,155)@5
vStagei_uid156_lzcZ_uid56_fpCosPiTest_s <= vCount_uid153_lzcZ_uid56_fpCosPiTest_q;
vStagei_uid156_lzcZ_uid56_fpCosPiTest: PROCESS (vStagei_uid156_lzcZ_uid56_fpCosPiTest_s, en, rVStage_uid152_lzcZ_uid56_fpCosPiTest_b, vStage_uid154_lzcZ_uid56_fpCosPiTest_b)
BEGIN
CASE vStagei_uid156_lzcZ_uid56_fpCosPiTest_s IS
WHEN "0" => vStagei_uid156_lzcZ_uid56_fpCosPiTest_q <= rVStage_uid152_lzcZ_uid56_fpCosPiTest_b;
WHEN "1" => vStagei_uid156_lzcZ_uid56_fpCosPiTest_q <= vStage_uid154_lzcZ_uid56_fpCosPiTest_b;
WHEN OTHERS => vStagei_uid156_lzcZ_uid56_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid158_lzcZ_uid56_fpCosPiTest(BITSELECT,157)@5
rVStage_uid158_lzcZ_uid56_fpCosPiTest_in <= vStagei_uid156_lzcZ_uid56_fpCosPiTest_q;
rVStage_uid158_lzcZ_uid56_fpCosPiTest_b <= rVStage_uid158_lzcZ_uid56_fpCosPiTest_in(7 downto 4);
--reg_rVStage_uid158_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid159_lzcZ_uid56_fpCosPiTest_1(REG,253)@5
reg_rVStage_uid158_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid159_lzcZ_uid56_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid158_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid159_lzcZ_uid56_fpCosPiTest_1_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid158_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid159_lzcZ_uid56_fpCosPiTest_1_q <= rVStage_uid158_lzcZ_uid56_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid159_lzcZ_uid56_fpCosPiTest(LOGICAL,158)@6
vCount_uid159_lzcZ_uid56_fpCosPiTest_a <= reg_rVStage_uid158_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid159_lzcZ_uid56_fpCosPiTest_1_q;
vCount_uid159_lzcZ_uid56_fpCosPiTest_b <= leftShiftStage1Idx1Pad4_uid114_fxpX_uid41_fpCosPiTest_q;
vCount_uid159_lzcZ_uid56_fpCosPiTest_q <= "1" when vCount_uid159_lzcZ_uid56_fpCosPiTest_a = vCount_uid159_lzcZ_uid56_fpCosPiTest_b else "0";
--vStage_uid160_lzcZ_uid56_fpCosPiTest(BITSELECT,159)@5
vStage_uid160_lzcZ_uid56_fpCosPiTest_in <= vStagei_uid156_lzcZ_uid56_fpCosPiTest_q(3 downto 0);
vStage_uid160_lzcZ_uid56_fpCosPiTest_b <= vStage_uid160_lzcZ_uid56_fpCosPiTest_in(3 downto 0);
--reg_vStage_uid160_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid162_lzcZ_uid56_fpCosPiTest_3(REG,255)@5
reg_vStage_uid160_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid162_lzcZ_uid56_fpCosPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid160_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid162_lzcZ_uid56_fpCosPiTest_3_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid160_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid162_lzcZ_uid56_fpCosPiTest_3_q <= vStage_uid160_lzcZ_uid56_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid162_lzcZ_uid56_fpCosPiTest(MUX,161)@6
vStagei_uid162_lzcZ_uid56_fpCosPiTest_s <= vCount_uid159_lzcZ_uid56_fpCosPiTest_q;
vStagei_uid162_lzcZ_uid56_fpCosPiTest: PROCESS (vStagei_uid162_lzcZ_uid56_fpCosPiTest_s, en, reg_rVStage_uid158_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid159_lzcZ_uid56_fpCosPiTest_1_q, reg_vStage_uid160_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid162_lzcZ_uid56_fpCosPiTest_3_q)
BEGIN
CASE vStagei_uid162_lzcZ_uid56_fpCosPiTest_s IS
WHEN "0" => vStagei_uid162_lzcZ_uid56_fpCosPiTest_q <= reg_rVStage_uid158_lzcZ_uid56_fpCosPiTest_0_to_vCount_uid159_lzcZ_uid56_fpCosPiTest_1_q;
WHEN "1" => vStagei_uid162_lzcZ_uid56_fpCosPiTest_q <= reg_vStage_uid160_lzcZ_uid56_fpCosPiTest_0_to_vStagei_uid162_lzcZ_uid56_fpCosPiTest_3_q;
WHEN OTHERS => vStagei_uid162_lzcZ_uid56_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid164_lzcZ_uid56_fpCosPiTest(BITSELECT,163)@6
rVStage_uid164_lzcZ_uid56_fpCosPiTest_in <= vStagei_uid162_lzcZ_uid56_fpCosPiTest_q;
rVStage_uid164_lzcZ_uid56_fpCosPiTest_b <= rVStage_uid164_lzcZ_uid56_fpCosPiTest_in(3 downto 2);
--vCount_uid165_lzcZ_uid56_fpCosPiTest(LOGICAL,164)@6
vCount_uid165_lzcZ_uid56_fpCosPiTest_a <= rVStage_uid164_lzcZ_uid56_fpCosPiTest_b;
vCount_uid165_lzcZ_uid56_fpCosPiTest_b <= leftShiftStage2Idx2Pad2_uid128_fxpX_uid41_fpCosPiTest_q;
vCount_uid165_lzcZ_uid56_fpCosPiTest_q <= "1" when vCount_uid165_lzcZ_uid56_fpCosPiTest_a = vCount_uid165_lzcZ_uid56_fpCosPiTest_b else "0";
--vStage_uid166_lzcZ_uid56_fpCosPiTest(BITSELECT,165)@6
vStage_uid166_lzcZ_uid56_fpCosPiTest_in <= vStagei_uid162_lzcZ_uid56_fpCosPiTest_q(1 downto 0);
vStage_uid166_lzcZ_uid56_fpCosPiTest_b <= vStage_uid166_lzcZ_uid56_fpCosPiTest_in(1 downto 0);
--vStagei_uid168_lzcZ_uid56_fpCosPiTest(MUX,167)@6
vStagei_uid168_lzcZ_uid56_fpCosPiTest_s <= vCount_uid165_lzcZ_uid56_fpCosPiTest_q;
vStagei_uid168_lzcZ_uid56_fpCosPiTest: PROCESS (vStagei_uid168_lzcZ_uid56_fpCosPiTest_s, en, rVStage_uid164_lzcZ_uid56_fpCosPiTest_b, vStage_uid166_lzcZ_uid56_fpCosPiTest_b)
BEGIN
CASE vStagei_uid168_lzcZ_uid56_fpCosPiTest_s IS
WHEN "0" => vStagei_uid168_lzcZ_uid56_fpCosPiTest_q <= rVStage_uid164_lzcZ_uid56_fpCosPiTest_b;
WHEN "1" => vStagei_uid168_lzcZ_uid56_fpCosPiTest_q <= vStage_uid166_lzcZ_uid56_fpCosPiTest_b;
WHEN OTHERS => vStagei_uid168_lzcZ_uid56_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid170_lzcZ_uid56_fpCosPiTest(BITSELECT,169)@6
rVStage_uid170_lzcZ_uid56_fpCosPiTest_in <= vStagei_uid168_lzcZ_uid56_fpCosPiTest_q;
rVStage_uid170_lzcZ_uid56_fpCosPiTest_b <= rVStage_uid170_lzcZ_uid56_fpCosPiTest_in(1 downto 1);
--vCount_uid171_lzcZ_uid56_fpCosPiTest(LOGICAL,170)@6
vCount_uid171_lzcZ_uid56_fpCosPiTest_a <= rVStage_uid170_lzcZ_uid56_fpCosPiTest_b;
vCount_uid171_lzcZ_uid56_fpCosPiTest_b <= GND_q;
vCount_uid171_lzcZ_uid56_fpCosPiTest_q <= "1" when vCount_uid171_lzcZ_uid56_fpCosPiTest_a = vCount_uid171_lzcZ_uid56_fpCosPiTest_b else "0";
--r_uid172_lzcZ_uid56_fpCosPiTest(BITJOIN,171)@6
r_uid172_lzcZ_uid56_fpCosPiTest_q <= ld_vCount_uid139_lzcZ_uid56_fpCosPiTest_q_to_r_uid172_lzcZ_uid56_fpCosPiTest_f_q & ld_vCount_uid147_lzcZ_uid56_fpCosPiTest_q_to_r_uid172_lzcZ_uid56_fpCosPiTest_e_q & reg_vCount_uid153_lzcZ_uid56_fpCosPiTest_0_to_r_uid172_lzcZ_uid56_fpCosPiTest_3_q & vCount_uid159_lzcZ_uid56_fpCosPiTest_q & vCount_uid165_lzcZ_uid56_fpCosPiTest_q & vCount_uid171_lzcZ_uid56_fpCosPiTest_q;
--leftShiftStageSel5Dto4_uid182_alignedZ_uid57_fpCosPiTest(BITSELECT,181)@6
leftShiftStageSel5Dto4_uid182_alignedZ_uid57_fpCosPiTest_in <= r_uid172_lzcZ_uid56_fpCosPiTest_q;
leftShiftStageSel5Dto4_uid182_alignedZ_uid57_fpCosPiTest_b <= leftShiftStageSel5Dto4_uid182_alignedZ_uid57_fpCosPiTest_in(5 downto 4);
--leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest(MUX,182)@6
leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_s <= leftShiftStageSel5Dto4_uid182_alignedZ_uid57_fpCosPiTest_b;
leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest: PROCESS (leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_s, en, ld_z_uid54_fpCosPiTest_b_to_leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_c_q, leftShiftStage0Idx1_uid177_alignedZ_uid57_fpCosPiTest_q, leftShiftStage0Idx2_uid180_alignedZ_uid57_fpCosPiTest_q, cstZwSwF_uid15_fpCosPiTest_q)
BEGIN
CASE leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_s IS
WHEN "00" => leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_q <= ld_z_uid54_fpCosPiTest_b_to_leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_c_q;
WHEN "01" => leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_q <= leftShiftStage0Idx1_uid177_alignedZ_uid57_fpCosPiTest_q;
WHEN "10" => leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_q <= leftShiftStage0Idx2_uid180_alignedZ_uid57_fpCosPiTest_q;
WHEN "11" => leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_q <= cstZwSwF_uid15_fpCosPiTest_q;
WHEN OTHERS => leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage022dto0_uid191_alignedZ_uid57_fpCosPiTest(BITSELECT,190)@6
LeftShiftStage022dto0_uid191_alignedZ_uid57_fpCosPiTest_in <= leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_q(22 downto 0);
LeftShiftStage022dto0_uid191_alignedZ_uid57_fpCosPiTest_b <= LeftShiftStage022dto0_uid191_alignedZ_uid57_fpCosPiTest_in(22 downto 0);
--leftShiftStage1Idx3_uid192_alignedZ_uid57_fpCosPiTest(BITJOIN,191)@6
leftShiftStage1Idx3_uid192_alignedZ_uid57_fpCosPiTest_q <= LeftShiftStage022dto0_uid191_alignedZ_uid57_fpCosPiTest_b & leftShiftStage1Idx3Pad12_uid120_fxpX_uid41_fpCosPiTest_q;
--reg_leftShiftStage1Idx3_uid192_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_5(REG,261)@6
reg_leftShiftStage1Idx3_uid192_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx3_uid192_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_5_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx3_uid192_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_5_q <= leftShiftStage1Idx3_uid192_alignedZ_uid57_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage026dto0_uid188_alignedZ_uid57_fpCosPiTest(BITSELECT,187)@6
LeftShiftStage026dto0_uid188_alignedZ_uid57_fpCosPiTest_in <= leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_q(26 downto 0);
LeftShiftStage026dto0_uid188_alignedZ_uid57_fpCosPiTest_b <= LeftShiftStage026dto0_uid188_alignedZ_uid57_fpCosPiTest_in(26 downto 0);
--leftShiftStage1Idx2_uid189_alignedZ_uid57_fpCosPiTest(BITJOIN,188)@6
leftShiftStage1Idx2_uid189_alignedZ_uid57_fpCosPiTest_q <= LeftShiftStage026dto0_uid188_alignedZ_uid57_fpCosPiTest_b & cstAllZWE_uid21_fpCosPiTest_q;
--reg_leftShiftStage1Idx2_uid189_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_4(REG,260)@6
reg_leftShiftStage1Idx2_uid189_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx2_uid189_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_4_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx2_uid189_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_4_q <= leftShiftStage1Idx2_uid189_alignedZ_uid57_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage030dto0_uid185_alignedZ_uid57_fpCosPiTest(BITSELECT,184)@6
LeftShiftStage030dto0_uid185_alignedZ_uid57_fpCosPiTest_in <= leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_q(30 downto 0);
LeftShiftStage030dto0_uid185_alignedZ_uid57_fpCosPiTest_b <= LeftShiftStage030dto0_uid185_alignedZ_uid57_fpCosPiTest_in(30 downto 0);
--leftShiftStage1Idx1_uid186_alignedZ_uid57_fpCosPiTest(BITJOIN,185)@6
leftShiftStage1Idx1_uid186_alignedZ_uid57_fpCosPiTest_q <= LeftShiftStage030dto0_uid185_alignedZ_uid57_fpCosPiTest_b & leftShiftStage1Idx1Pad4_uid114_fxpX_uid41_fpCosPiTest_q;
--reg_leftShiftStage1Idx1_uid186_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_3(REG,259)@6
reg_leftShiftStage1Idx1_uid186_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx1_uid186_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_3_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx1_uid186_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_3_q <= leftShiftStage1Idx1_uid186_alignedZ_uid57_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--reg_leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_2(REG,258)@6
reg_leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_2_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_2_q <= leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel3Dto2_uid193_alignedZ_uid57_fpCosPiTest(BITSELECT,192)@6
leftShiftStageSel3Dto2_uid193_alignedZ_uid57_fpCosPiTest_in <= r_uid172_lzcZ_uid56_fpCosPiTest_q(3 downto 0);
leftShiftStageSel3Dto2_uid193_alignedZ_uid57_fpCosPiTest_b <= leftShiftStageSel3Dto2_uid193_alignedZ_uid57_fpCosPiTest_in(3 downto 2);
--reg_leftShiftStageSel3Dto2_uid193_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_1(REG,257)@6
reg_leftShiftStageSel3Dto2_uid193_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel3Dto2_uid193_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel3Dto2_uid193_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_1_q <= leftShiftStageSel3Dto2_uid193_alignedZ_uid57_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest(MUX,193)@7
leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_s <= reg_leftShiftStageSel3Dto2_uid193_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_1_q;
leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest: PROCESS (leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_s, en, reg_leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_2_q, reg_leftShiftStage1Idx1_uid186_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_3_q, reg_leftShiftStage1Idx2_uid189_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_4_q, reg_leftShiftStage1Idx3_uid192_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_5_q)
BEGIN
CASE leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_s IS
WHEN "00" => leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_q <= reg_leftShiftStage0_uid183_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_2_q;
WHEN "01" => leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_q <= reg_leftShiftStage1Idx1_uid186_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_3_q;
WHEN "10" => leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_q <= reg_leftShiftStage1Idx2_uid189_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_4_q;
WHEN "11" => leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_q <= reg_leftShiftStage1Idx3_uid192_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_5_q;
WHEN OTHERS => leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--leftShiftStageSel1Dto0_uid204_alignedZ_uid57_fpCosPiTest(BITSELECT,203)@6
leftShiftStageSel1Dto0_uid204_alignedZ_uid57_fpCosPiTest_in <= r_uid172_lzcZ_uid56_fpCosPiTest_q(1 downto 0);
leftShiftStageSel1Dto0_uid204_alignedZ_uid57_fpCosPiTest_b <= leftShiftStageSel1Dto0_uid204_alignedZ_uid57_fpCosPiTest_in(1 downto 0);
--reg_leftShiftStageSel1Dto0_uid204_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest_1(REG,262)@6
reg_leftShiftStageSel1Dto0_uid204_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel1Dto0_uid204_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel1Dto0_uid204_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest_1_q <= leftShiftStageSel1Dto0_uid204_alignedZ_uid57_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest(MUX,204)@7
leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest_s <= reg_leftShiftStageSel1Dto0_uid204_alignedZ_uid57_fpCosPiTest_0_to_leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest_1_q;
leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest: PROCESS (leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest_s, en, leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_q, leftShiftStage2Idx1_uid197_alignedZ_uid57_fpCosPiTest_q, leftShiftStage2Idx2_uid200_alignedZ_uid57_fpCosPiTest_q, leftShiftStage2Idx3_uid203_alignedZ_uid57_fpCosPiTest_q)
BEGIN
CASE leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest_s IS
WHEN "00" => leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest_q <= leftShiftStage1_uid194_alignedZ_uid57_fpCosPiTest_q;
WHEN "01" => leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest_q <= leftShiftStage2Idx1_uid197_alignedZ_uid57_fpCosPiTest_q;
WHEN "10" => leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest_q <= leftShiftStage2Idx2_uid200_alignedZ_uid57_fpCosPiTest_q;
WHEN "11" => leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest_q <= leftShiftStage2Idx3_uid203_alignedZ_uid57_fpCosPiTest_q;
WHEN OTHERS => leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--alignedZLow_uid58_fpCosPiTest(BITSELECT,57)@7
alignedZLow_uid58_fpCosPiTest_in <= leftShiftStage2_uid205_alignedZ_uid57_fpCosPiTest_q;
alignedZLow_uid58_fpCosPiTest_b <= alignedZLow_uid58_fpCosPiTest_in(34 downto 11);
--ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_inputreg(DELAY,612)
ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 24, depth => 1 )
PORT MAP ( xin => alignedZLow_uid58_fpCosPiTest_b, xout => ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem(DUALMEM,613)
ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_reset0 <= areset;
ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_ia <= ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_inputreg_q;
ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_aa <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdreg_q;
ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_ab <= ld_reg_zAddr_uid62_fpCosPiTest_0_to_memoryC1_uid208_sinPiZTableGenerator_0_q_to_memoryC1_uid208_sinPiZTableGenerator_a_replace_rdmux_q;
ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 24,
widthad_a => 2,
numwords_a => 3,
width_b => 24,
widthad_b => 2,
numwords_b => 3,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_iq,
address_a => ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_aa,
data_a => ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_ia
);
ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_q <= ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_iq(23 downto 0);
--reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0(REG,269)@12
reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_q <= ld_alignedZLow_uid58_fpCosPiTest_b_to_reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest(MULT,222)@13
prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_pr <= UNSIGNED(prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_a) * UNSIGNED(prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_b);
prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_a <= (others => '0');
prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_b <= (others => '0');
prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_a <= reg_alignedZLow_uid58_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_0_q;
prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_b <= reg_fxpSinRes_uid65_fpCosPiTest_0_to_prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_1_q;
prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_s1 <= STD_LOGIC_VECTOR(prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_pr);
END IF;
END IF;
END PROCESS;
prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_q <= prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid224_mul2xSinRes_uid66_fpCosPiTest(BITSELECT,223)@16
prodXYTruncFR_uid224_mul2xSinRes_uid66_fpCosPiTest_in <= prodXY_uid223_mul2xSinRes_uid66_fpCosPiTest_q;
prodXYTruncFR_uid224_mul2xSinRes_uid66_fpCosPiTest_b <= prodXYTruncFR_uid224_mul2xSinRes_uid66_fpCosPiTest_in(48 downto 23);
--normBit_uid67_fpCosPiTest(BITSELECT,66)@16
normBit_uid67_fpCosPiTest_in <= prodXYTruncFR_uid224_mul2xSinRes_uid66_fpCosPiTest_b;
normBit_uid67_fpCosPiTest_b <= normBit_uid67_fpCosPiTest_in(25 downto 25);
--cstAllZWF_uid9_fpCosPiTest(CONSTANT,8)
cstAllZWF_uid9_fpCosPiTest_q <= "00000000000000000000000";
--rndExpUpdate_uid72_uid73_fpCosPiTest(BITJOIN,72)@16
rndExpUpdate_uid72_uid73_fpCosPiTest_q <= normBit_uid67_fpCosPiTest_b & cstAllZWF_uid9_fpCosPiTest_q & VCC_q;
--ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_nor(LOGICAL,558)
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_nor_a <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_notEnable_q;
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_nor_b <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_sticky_ena_q;
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_nor_q <= not (ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_nor_a or ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_nor_b);
--ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_sticky_ena(REG,559)
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_nor_q = "1") THEN
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_sticky_ena_q <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_enaAnd(LOGICAL,560)
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_enaAnd_a <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_sticky_ena_q;
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_enaAnd_b <= en;
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_enaAnd_q <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_enaAnd_a and ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_enaAnd_b;
--reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1(REG,271)@6
reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q <= r_uid172_lzcZ_uid56_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem(DUALMEM,549)
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_reset0 <= areset;
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_ia <= reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q;
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_aa <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdreg_q;
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_ab <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_rdmux_q;
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 6,
widthad_a => 3,
numwords_a => 7,
width_b => 6,
widthad_b => 3,
numwords_b => 7,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_iq,
address_a => ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_aa,
data_a => ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_ia
);
ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_q <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_iq(5 downto 0);
--cstBiasM1_uid11_fpCosPiTest(CONSTANT,10)
cstBiasM1_uid11_fpCosPiTest_q <= "01111110";
--expHardCase_uid59_fpCosPiTest(SUB,58)@15
expHardCase_uid59_fpCosPiTest_a <= STD_LOGIC_VECTOR("0" & cstBiasM1_uid11_fpCosPiTest_q);
expHardCase_uid59_fpCosPiTest_b <= STD_LOGIC_VECTOR("000" & ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_replace_mem_q);
expHardCase_uid59_fpCosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expHardCase_uid59_fpCosPiTest_a) - UNSIGNED(expHardCase_uid59_fpCosPiTest_b));
expHardCase_uid59_fpCosPiTest_q <= expHardCase_uid59_fpCosPiTest_o(8 downto 0);
--expP_uid60_fpCosPiTest(BITSELECT,59)@15
expP_uid60_fpCosPiTest_in <= expHardCase_uid59_fpCosPiTest_q(7 downto 0);
expP_uid60_fpCosPiTest_b <= expP_uid60_fpCosPiTest_in(7 downto 0);
--reg_expP_uid60_fpCosPiTest_0_to_expFracPreRnd_uid71_uid71_fpCosPiTest_1(REG,272)@15
reg_expP_uid60_fpCosPiTest_0_to_expFracPreRnd_uid71_uid71_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expP_uid60_fpCosPiTest_0_to_expFracPreRnd_uid71_uid71_fpCosPiTest_1_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expP_uid60_fpCosPiTest_0_to_expFracPreRnd_uid71_uid71_fpCosPiTest_1_q <= expP_uid60_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--highRes_uid68_fpCosPiTest(BITSELECT,67)@16
highRes_uid68_fpCosPiTest_in <= prodXYTruncFR_uid224_mul2xSinRes_uid66_fpCosPiTest_b(24 downto 0);
highRes_uid68_fpCosPiTest_b <= highRes_uid68_fpCosPiTest_in(24 downto 1);
--lowRes_uid69_fpCosPiTest(BITSELECT,68)@16
lowRes_uid69_fpCosPiTest_in <= prodXYTruncFR_uid224_mul2xSinRes_uid66_fpCosPiTest_b(23 downto 0);
lowRes_uid69_fpCosPiTest_b <= lowRes_uid69_fpCosPiTest_in(23 downto 0);
--fracRCompPreRnd_uid70_fpCosPiTest(MUX,69)@16
fracRCompPreRnd_uid70_fpCosPiTest_s <= normBit_uid67_fpCosPiTest_b;
fracRCompPreRnd_uid70_fpCosPiTest: PROCESS (fracRCompPreRnd_uid70_fpCosPiTest_s, en, lowRes_uid69_fpCosPiTest_b, highRes_uid68_fpCosPiTest_b)
BEGIN
CASE fracRCompPreRnd_uid70_fpCosPiTest_s IS
WHEN "0" => fracRCompPreRnd_uid70_fpCosPiTest_q <= lowRes_uid69_fpCosPiTest_b;
WHEN "1" => fracRCompPreRnd_uid70_fpCosPiTest_q <= highRes_uid68_fpCosPiTest_b;
WHEN OTHERS => fracRCompPreRnd_uid70_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--expFracPreRnd_uid71_uid71_fpCosPiTest(BITJOIN,70)@16
expFracPreRnd_uid71_uid71_fpCosPiTest_q <= reg_expP_uid60_fpCosPiTest_0_to_expFracPreRnd_uid71_uid71_fpCosPiTest_1_q & fracRCompPreRnd_uid70_fpCosPiTest_q;
--expFracComp_uid74_fpCosPiTest(ADD,73)@16
expFracComp_uid74_fpCosPiTest_a <= STD_LOGIC_VECTOR("0" & expFracPreRnd_uid71_uid71_fpCosPiTest_q);
expFracComp_uid74_fpCosPiTest_b <= STD_LOGIC_VECTOR("00000000" & rndExpUpdate_uid72_uid73_fpCosPiTest_q);
expFracComp_uid74_fpCosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expFracComp_uid74_fpCosPiTest_a) + UNSIGNED(expFracComp_uid74_fpCosPiTest_b));
expFracComp_uid74_fpCosPiTest_q <= expFracComp_uid74_fpCosPiTest_o(32 downto 0);
--expRComp_uid76_fpCosPiTest(BITSELECT,75)@16
expRComp_uid76_fpCosPiTest_in <= expFracComp_uid74_fpCosPiTest_q(31 downto 0);
expRComp_uid76_fpCosPiTest_b <= expRComp_uid76_fpCosPiTest_in(31 downto 24);
--fracXIsZero_uid27_fpCosPiTest(LOGICAL,26)@0
fracXIsZero_uid27_fpCosPiTest_a <= fracX_uid7_fpCosPiTest_b;
fracXIsZero_uid27_fpCosPiTest_b <= cstAllZWF_uid9_fpCosPiTest_q;
fracXIsZero_uid27_fpCosPiTest_q <= "1" when fracXIsZero_uid27_fpCosPiTest_a = fracXIsZero_uid27_fpCosPiTest_b else "0";
--InvFracXIsZero_uid29_fpCosPiTest(LOGICAL,28)@0
InvFracXIsZero_uid29_fpCosPiTest_a <= fracXIsZero_uid27_fpCosPiTest_q;
InvFracXIsZero_uid29_fpCosPiTest_q <= not InvFracXIsZero_uid29_fpCosPiTest_a;
--expXIsMax_uid25_fpCosPiTest(LOGICAL,24)@0
expXIsMax_uid25_fpCosPiTest_a <= expX_uid6_fpCosPiTest_b;
expXIsMax_uid25_fpCosPiTest_b <= cstAllOWE_uid8_fpCosPiTest_q;
expXIsMax_uid25_fpCosPiTest_q <= "1" when expXIsMax_uid25_fpCosPiTest_a = expXIsMax_uid25_fpCosPiTest_b else "0";
--exc_N_uid30_fpCosPiTest(LOGICAL,29)@0
exc_N_uid30_fpCosPiTest_a <= expXIsMax_uid25_fpCosPiTest_q;
exc_N_uid30_fpCosPiTest_b <= InvFracXIsZero_uid29_fpCosPiTest_q;
exc_N_uid30_fpCosPiTest_q <= exc_N_uid30_fpCosPiTest_a and exc_N_uid30_fpCosPiTest_b;
--InvExc_N_uid31_fpCosPiTest(LOGICAL,30)@0
InvExc_N_uid31_fpCosPiTest_a <= exc_N_uid30_fpCosPiTest_q;
InvExc_N_uid31_fpCosPiTest_q <= not InvExc_N_uid31_fpCosPiTest_a;
--exc_I_uid28_fpCosPiTest(LOGICAL,27)@0
exc_I_uid28_fpCosPiTest_a <= expXIsMax_uid25_fpCosPiTest_q;
exc_I_uid28_fpCosPiTest_b <= fracXIsZero_uid27_fpCosPiTest_q;
exc_I_uid28_fpCosPiTest_q <= exc_I_uid28_fpCosPiTest_a and exc_I_uid28_fpCosPiTest_b;
--InvExc_I_uid32_fpCosPiTest(LOGICAL,31)@0
InvExc_I_uid32_fpCosPiTest_a <= exc_I_uid28_fpCosPiTest_q;
InvExc_I_uid32_fpCosPiTest_q <= not InvExc_I_uid32_fpCosPiTest_a;
--expXIsZero_uid23_fpCosPiTest(LOGICAL,22)@0
expXIsZero_uid23_fpCosPiTest_a <= expX_uid6_fpCosPiTest_b;
expXIsZero_uid23_fpCosPiTest_b <= cstAllZWE_uid21_fpCosPiTest_q;
expXIsZero_uid23_fpCosPiTest_q <= "1" when expXIsZero_uid23_fpCosPiTest_a = expXIsZero_uid23_fpCosPiTest_b else "0";
--InvExpXIsZero_uid33_fpCosPiTest(LOGICAL,32)@0
InvExpXIsZero_uid33_fpCosPiTest_a <= expXIsZero_uid23_fpCosPiTest_q;
InvExpXIsZero_uid33_fpCosPiTest_q <= not InvExpXIsZero_uid33_fpCosPiTest_a;
--exc_R_uid34_fpCosPiTest(LOGICAL,33)@0
exc_R_uid34_fpCosPiTest_a <= InvExpXIsZero_uid33_fpCosPiTest_q;
exc_R_uid34_fpCosPiTest_b <= InvExc_I_uid32_fpCosPiTest_q;
exc_R_uid34_fpCosPiTest_c <= InvExc_N_uid31_fpCosPiTest_q;
exc_R_uid34_fpCosPiTest_q <= exc_R_uid34_fpCosPiTest_a and exc_R_uid34_fpCosPiTest_b and exc_R_uid34_fpCosPiTest_c;
--ld_exc_R_uid34_fpCosPiTest_q_to_xIsInt_uid80_fpCosPiTest_a(DELAY,337)@0
ld_exc_R_uid34_fpCosPiTest_q_to_xIsInt_uid80_fpCosPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => exc_R_uid34_fpCosPiTest_q, xout => ld_exc_R_uid34_fpCosPiTest_q_to_xIsInt_uid80_fpCosPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--xIsHalf_uid83_fpCosPiTest(LOGICAL,82)@2
xIsHalf_uid83_fpCosPiTest_a <= ld_exc_R_uid34_fpCosPiTest_q_to_xIsInt_uid80_fpCosPiTest_a_q;
xIsHalf_uid83_fpCosPiTest_b <= fxpXFracHalf_uid46_fpCosPiTest_q;
xIsHalf_uid83_fpCosPiTest_c <= InvCosXIsOne_uid77_fpCosPiTest_q;
xIsHalf_uid83_fpCosPiTest_d <= InvXEvenInt_uid81_fpCosPiTest_q;
xIsHalf_uid83_fpCosPiTest_q <= xIsHalf_uid83_fpCosPiTest_a and xIsHalf_uid83_fpCosPiTest_b and xIsHalf_uid83_fpCosPiTest_c and xIsHalf_uid83_fpCosPiTest_d;
--ld_xIsHalf_uid83_fpCosPiTest_q_to_expRPostExc1_uid91_fpCosPiTest_b(DELAY,355)@2
ld_xIsHalf_uid83_fpCosPiTest_q_to_expRPostExc1_uid91_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 14 )
PORT MAP ( xin => xIsHalf_uid83_fpCosPiTest_q, xout => ld_xIsHalf_uid83_fpCosPiTest_q_to_expRPostExc1_uid91_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--expRPostExc1_uid91_fpCosPiTest(MUX,90)@16
expRPostExc1_uid91_fpCosPiTest_s <= ld_xIsHalf_uid83_fpCosPiTest_q_to_expRPostExc1_uid91_fpCosPiTest_b_q;
expRPostExc1_uid91_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expRPostExc1_uid91_fpCosPiTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE expRPostExc1_uid91_fpCosPiTest_s IS
WHEN "0" => expRPostExc1_uid91_fpCosPiTest_q <= expRComp_uid76_fpCosPiTest_b;
WHEN "1" => expRPostExc1_uid91_fpCosPiTest_q <= cstAllZWE_uid21_fpCosPiTest_q;
WHEN OTHERS => expRPostExc1_uid91_fpCosPiTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_nor(LOGICAL,570)
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_nor_a <= ld_reg_r_uid172_lzcZ_uid56_fpCosPiTest_0_to_expHardCase_uid59_fpCosPiTest_1_q_to_expHardCase_uid59_fpCosPiTest_b_notEnable_q;
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_nor_b <= ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_sticky_ena_q;
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_nor_q <= not (ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_nor_a or ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_nor_b);
--ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_mem_top(CONSTANT,566)
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_mem_top_q <= "01100";
--ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_cmp(LOGICAL,567)
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_cmp_a <= ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_mem_top_q;
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdmux_q);
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_cmp_q <= "1" when ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_cmp_a = ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_cmp_b else "0";
--ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_cmpReg(REG,568)
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_cmpReg_q <= ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_sticky_ena(REG,571)
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_nor_q = "1") THEN
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_sticky_ena_q <= ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_enaAnd(LOGICAL,572)
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_enaAnd_a <= ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_sticky_ena_q;
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_enaAnd_b <= en;
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_enaAnd_q <= ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_enaAnd_a and ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_enaAnd_b;
--ld_expXIsZero_uid23_fpCosPiTest_q_to_xIntOrXZOrCosOne_uid93_fpCosPiTest_b(DELAY,359)@0
ld_expXIsZero_uid23_fpCosPiTest_q_to_xIntOrXZOrCosOne_uid93_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => expXIsZero_uid23_fpCosPiTest_q, xout => ld_expXIsZero_uid23_fpCosPiTest_q_to_xIntOrXZOrCosOne_uid93_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--fxpXFracZero_uid45_fpCosPiTest(LOGICAL,44)@2
fxpXFracZero_uid45_fpCosPiTest_a <= reg_fxpXFrac_uid43_fpCosPiTest_0_to_fxpXFracZero_uid45_fpCosPiTest_1_q;
fxpXFracZero_uid45_fpCosPiTest_b <= STD_LOGIC_VECTOR("0" & cstZwSwF_uid15_fpCosPiTest_q);
fxpXFracZero_uid45_fpCosPiTest_q <= "1" when fxpXFracZero_uid45_fpCosPiTest_a = fxpXFracZero_uid45_fpCosPiTest_b else "0";
--fracZCosNotOne_uid78_fpCosPiTest(LOGICAL,77)@2
fracZCosNotOne_uid78_fpCosPiTest_a <= fxpXFracZero_uid45_fpCosPiTest_q;
fracZCosNotOne_uid78_fpCosPiTest_b <= InvCosXIsOne_uid77_fpCosPiTest_q;
fracZCosNotOne_uid78_fpCosPiTest_q <= fracZCosNotOne_uid78_fpCosPiTest_a and fracZCosNotOne_uid78_fpCosPiTest_b;
--evenIntCosNotOneFZ_uid79_fpCosPiTest(LOGICAL,78)@2
evenIntCosNotOneFZ_uid79_fpCosPiTest_a <= ld_xEvenInt_uid35_fpCosPiTest_c_to_evenIntCosNotOneFZ_uid79_fpCosPiTest_a_q;
evenIntCosNotOneFZ_uid79_fpCosPiTest_b <= fracZCosNotOne_uid78_fpCosPiTest_q;
evenIntCosNotOneFZ_uid79_fpCosPiTest_q <= evenIntCosNotOneFZ_uid79_fpCosPiTest_a or evenIntCosNotOneFZ_uid79_fpCosPiTest_b;
--xIsInt_uid80_fpCosPiTest(LOGICAL,79)@2
xIsInt_uid80_fpCosPiTest_a <= ld_exc_R_uid34_fpCosPiTest_q_to_xIsInt_uid80_fpCosPiTest_a_q;
xIsInt_uid80_fpCosPiTest_b <= evenIntCosNotOneFZ_uid79_fpCosPiTest_q;
xIsInt_uid80_fpCosPiTest_q <= xIsInt_uid80_fpCosPiTest_a and xIsInt_uid80_fpCosPiTest_b;
--xIntOrXZOrCosOne_uid93_fpCosPiTest(LOGICAL,92)@2
xIntOrXZOrCosOne_uid93_fpCosPiTest_a <= xIsInt_uid80_fpCosPiTest_q;
xIntOrXZOrCosOne_uid93_fpCosPiTest_b <= ld_expXIsZero_uid23_fpCosPiTest_q_to_xIntOrXZOrCosOne_uid93_fpCosPiTest_b_q;
xIntOrXZOrCosOne_uid93_fpCosPiTest_c <= ld_cosXIsOne_uid36_fpCosPiTest_c_to_InvCosXIsOne_uid77_fpCosPiTest_a_q;
xIntOrXZOrCosOne_uid93_fpCosPiTest_q <= xIntOrXZOrCosOne_uid93_fpCosPiTest_a or xIntOrXZOrCosOne_uid93_fpCosPiTest_b or xIntOrXZOrCosOne_uid93_fpCosPiTest_c;
--excRNaN_uid84_fpCosPiTest(LOGICAL,83)@0
excRNaN_uid84_fpCosPiTest_a <= exc_N_uid30_fpCosPiTest_q;
excRNaN_uid84_fpCosPiTest_b <= exc_I_uid28_fpCosPiTest_q;
excRNaN_uid84_fpCosPiTest_q <= excRNaN_uid84_fpCosPiTest_a or excRNaN_uid84_fpCosPiTest_b;
--rInfOrNaN_uid92_fpCosPiTest(LOGICAL,91)@0
rInfOrNaN_uid92_fpCosPiTest_a <= GND_q;
rInfOrNaN_uid92_fpCosPiTest_b <= excRNaN_uid84_fpCosPiTest_q;
rInfOrNaN_uid92_fpCosPiTest_q <= rInfOrNaN_uid92_fpCosPiTest_a or rInfOrNaN_uid92_fpCosPiTest_b;
--ld_rInfOrNaN_uid92_fpCosPiTest_q_to_join_uid94_fpCosPiTest_a(DELAY,361)@0
ld_rInfOrNaN_uid92_fpCosPiTest_q_to_join_uid94_fpCosPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => rInfOrNaN_uid92_fpCosPiTest_q, xout => ld_rInfOrNaN_uid92_fpCosPiTest_q_to_join_uid94_fpCosPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--join_uid94_fpCosPiTest(BITJOIN,93)@2
join_uid94_fpCosPiTest_q <= xIntOrXZOrCosOne_uid93_fpCosPiTest_q & ld_rInfOrNaN_uid92_fpCosPiTest_q_to_join_uid94_fpCosPiTest_a_q;
--reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1(REG,274)@2
reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q <= join_uid94_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt(COUNTER,562)
-- every=1, low=0, high=12, step=1, init=1
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt_i = 11 THEN
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt_eq <= '1';
ELSE
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt_eq = '1') THEN
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt_i <= ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt_i - 12;
ELSE
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt_i <= ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt_i,4));
--ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdreg(REG,563)
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdreg_q <= ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdmux(MUX,564)
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdmux_s <= en;
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdmux: PROCESS (ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdmux_s, ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdreg_q, ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt_q)
BEGIN
CASE ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdmux_s IS
WHEN "0" => ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdmux_q <= ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdreg_q;
WHEN "1" => ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdmux_q <= ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem(DUALMEM,561)
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_reset0 <= areset;
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_ia <= reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q;
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_aa <= ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdreg_q;
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_ab <= ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_rdmux_q;
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 2,
widthad_a => 4,
numwords_a => 13,
width_b => 2,
widthad_b => 4,
numwords_b => 13,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_iq,
address_a => ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_aa,
data_a => ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_ia
);
ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_q <= ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_iq(1 downto 0);
--expRPostExc_uid95_fpCosPiTest(MUX,94)@17
expRPostExc_uid95_fpCosPiTest_s <= ld_reg_join_uid94_fpCosPiTest_0_to_expRPostExc_uid95_fpCosPiTest_1_q_to_expRPostExc_uid95_fpCosPiTest_b_replace_mem_q;
expRPostExc_uid95_fpCosPiTest: PROCESS (expRPostExc_uid95_fpCosPiTest_s, en, expRPostExc1_uid91_fpCosPiTest_q, cstAllOWE_uid8_fpCosPiTest_q, cstBias_uid10_fpCosPiTest_q, cstBias_uid10_fpCosPiTest_q)
BEGIN
CASE expRPostExc_uid95_fpCosPiTest_s IS
WHEN "00" => expRPostExc_uid95_fpCosPiTest_q <= expRPostExc1_uid91_fpCosPiTest_q;
WHEN "01" => expRPostExc_uid95_fpCosPiTest_q <= cstAllOWE_uid8_fpCosPiTest_q;
WHEN "10" => expRPostExc_uid95_fpCosPiTest_q <= cstBias_uid10_fpCosPiTest_q;
WHEN "11" => expRPostExc_uid95_fpCosPiTest_q <= cstBias_uid10_fpCosPiTest_q;
WHEN OTHERS => expRPostExc_uid95_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--oneFracRPostExc2_uid87_fpCosPiTest(CONSTANT,86)
oneFracRPostExc2_uid87_fpCosPiTest_q <= "00000000000000000000001";
--fracRComp_uid75_fpCosPiTest(BITSELECT,74)@16
fracRComp_uid75_fpCosPiTest_in <= expFracComp_uid74_fpCosPiTest_q(23 downto 0);
fracRComp_uid75_fpCosPiTest_b <= fracRComp_uid75_fpCosPiTest_in(23 downto 1);
--reg_xIsHalf_uid83_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_5(REG,243)@2
reg_xIsHalf_uid83_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xIsHalf_uid83_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_5_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xIsHalf_uid83_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_5_q <= xIsHalf_uid83_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--reg_expXIsZero_uid23_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_4(REG,242)@2
reg_expXIsZero_uid23_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expXIsZero_uid23_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_4_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expXIsZero_uid23_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_4_q <= ld_expXIsZero_uid23_fpCosPiTest_q_to_xIntOrXZOrCosOne_uid93_fpCosPiTest_b_q;
END IF;
END IF;
END PROCESS;
--reg_fxpXFracHalf_uid46_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_3(REG,241)@2
reg_fxpXFracHalf_uid46_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fxpXFracHalf_uid46_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_3_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fxpXFracHalf_uid46_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_3_q <= fxpXFracHalf_uid46_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--reg_xIsInt_uid80_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_2(REG,240)@2
reg_xIsInt_uid80_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xIsInt_uid80_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xIsInt_uid80_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_2_q <= xIsInt_uid80_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--reg_cosXIsOne_uid36_fpCosPiTest_1_to_bigCond_uid85_fpCosPiTest_1(REG,239)@0
reg_cosXIsOne_uid36_fpCosPiTest_1_to_bigCond_uid85_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cosXIsOne_uid36_fpCosPiTest_1_to_bigCond_uid85_fpCosPiTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cosXIsOne_uid36_fpCosPiTest_1_to_bigCond_uid85_fpCosPiTest_1_q <= cosXIsOne_uid36_fpCosPiTest_c;
END IF;
END IF;
END PROCESS;
--ld_reg_cosXIsOne_uid36_fpCosPiTest_1_to_bigCond_uid85_fpCosPiTest_1_q_to_bigCond_uid85_fpCosPiTest_a(DELAY,346)@1
ld_reg_cosXIsOne_uid36_fpCosPiTest_1_to_bigCond_uid85_fpCosPiTest_1_q_to_bigCond_uid85_fpCosPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => reg_cosXIsOne_uid36_fpCosPiTest_1_to_bigCond_uid85_fpCosPiTest_1_q, xout => ld_reg_cosXIsOne_uid36_fpCosPiTest_1_to_bigCond_uid85_fpCosPiTest_1_q_to_bigCond_uid85_fpCosPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--bigCond_uid85_fpCosPiTest(LOGICAL,84)@3
bigCond_uid85_fpCosPiTest_a <= ld_reg_cosXIsOne_uid36_fpCosPiTest_1_to_bigCond_uid85_fpCosPiTest_1_q_to_bigCond_uid85_fpCosPiTest_a_q;
bigCond_uid85_fpCosPiTest_b <= reg_xIsInt_uid80_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_2_q;
bigCond_uid85_fpCosPiTest_c <= reg_fxpXFracHalf_uid46_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_3_q;
bigCond_uid85_fpCosPiTest_d <= reg_expXIsZero_uid23_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_4_q;
bigCond_uid85_fpCosPiTest_f <= reg_xIsHalf_uid83_fpCosPiTest_0_to_bigCond_uid85_fpCosPiTest_5_q;
bigCond_uid85_fpCosPiTest_g <= GND_q;
bigCond_uid85_fpCosPiTest_q <= bigCond_uid85_fpCosPiTest_a or bigCond_uid85_fpCosPiTest_b or bigCond_uid85_fpCosPiTest_c or bigCond_uid85_fpCosPiTest_d or bigCond_uid85_fpCosPiTest_f or bigCond_uid85_fpCosPiTest_g;
--ld_bigCond_uid85_fpCosPiTest_q_to_fracRPostExc1_uid86_fpCosPiTest_b(DELAY,351)@3
ld_bigCond_uid85_fpCosPiTest_q_to_fracRPostExc1_uid86_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 13 )
PORT MAP ( xin => bigCond_uid85_fpCosPiTest_q, xout => ld_bigCond_uid85_fpCosPiTest_q_to_fracRPostExc1_uid86_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--fracRPostExc1_uid86_fpCosPiTest(MUX,85)@16
fracRPostExc1_uid86_fpCosPiTest_s <= ld_bigCond_uid85_fpCosPiTest_q_to_fracRPostExc1_uid86_fpCosPiTest_b_q;
fracRPostExc1_uid86_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
fracRPostExc1_uid86_fpCosPiTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE fracRPostExc1_uid86_fpCosPiTest_s IS
WHEN "0" => fracRPostExc1_uid86_fpCosPiTest_q <= fracRComp_uid75_fpCosPiTest_b;
WHEN "1" => fracRPostExc1_uid86_fpCosPiTest_q <= cstAllZWF_uid9_fpCosPiTest_q;
WHEN OTHERS => fracRPostExc1_uid86_fpCosPiTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--reg_excRNaN_uid84_fpCosPiTest_0_to_fracRPostExc_uid88_fpCosPiTest_1(REG,273)@0
reg_excRNaN_uid84_fpCosPiTest_0_to_fracRPostExc_uid88_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_excRNaN_uid84_fpCosPiTest_0_to_fracRPostExc_uid88_fpCosPiTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_excRNaN_uid84_fpCosPiTest_0_to_fracRPostExc_uid88_fpCosPiTest_1_q <= excRNaN_uid84_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_excRNaN_uid84_fpCosPiTest_0_to_fracRPostExc_uid88_fpCosPiTest_1_q_to_fracRPostExc_uid88_fpCosPiTest_b(DELAY,353)@1
ld_reg_excRNaN_uid84_fpCosPiTest_0_to_fracRPostExc_uid88_fpCosPiTest_1_q_to_fracRPostExc_uid88_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 16 )
PORT MAP ( xin => reg_excRNaN_uid84_fpCosPiTest_0_to_fracRPostExc_uid88_fpCosPiTest_1_q, xout => ld_reg_excRNaN_uid84_fpCosPiTest_0_to_fracRPostExc_uid88_fpCosPiTest_1_q_to_fracRPostExc_uid88_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--fracRPostExc_uid88_fpCosPiTest(MUX,87)@17
fracRPostExc_uid88_fpCosPiTest_s <= ld_reg_excRNaN_uid84_fpCosPiTest_0_to_fracRPostExc_uid88_fpCosPiTest_1_q_to_fracRPostExc_uid88_fpCosPiTest_b_q;
fracRPostExc_uid88_fpCosPiTest: PROCESS (fracRPostExc_uid88_fpCosPiTest_s, en, fracRPostExc1_uid86_fpCosPiTest_q, oneFracRPostExc2_uid87_fpCosPiTest_q)
BEGIN
CASE fracRPostExc_uid88_fpCosPiTest_s IS
WHEN "0" => fracRPostExc_uid88_fpCosPiTest_q <= fracRPostExc1_uid86_fpCosPiTest_q;
WHEN "1" => fracRPostExc_uid88_fpCosPiTest_q <= oneFracRPostExc2_uid87_fpCosPiTest_q;
WHEN OTHERS => fracRPostExc_uid88_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--R_uid102_fpCosPiTest(BITJOIN,101)@17
R_uid102_fpCosPiTest_q <= ld_signR_uid101_fpCosPiTest_q_to_R_uid102_fpCosPiTest_c_q & expRPostExc_uid95_fpCosPiTest_q & fracRPostExc_uid88_fpCosPiTest_q;
--xOut(GPOUT,4)@17
q <= R_uid102_fpCosPiTest_q;
end normal;
|
-- megafunction wizard: %LPM_ADD_SUB%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: lpm_add_sub
-- ============================================================
-- File Name: lpm_add_sub_db0.vhd
-- Megafunction Name(s):
-- lpm_add_sub
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2010 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY lpm_add_sub_db0 IS
PORT
(
dataa : IN STD_LOGIC_VECTOR (8 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (8 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (8 DOWNTO 0)
);
END lpm_add_sub_db0;
ARCHITECTURE SYN OF lpm_add_sub_db0 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (8 DOWNTO 0);
COMPONENT lpm_add_sub
GENERIC (
lpm_direction : STRING;
lpm_hint : STRING;
lpm_representation : STRING;
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
dataa : IN STD_LOGIC_VECTOR (8 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (8 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (8 DOWNTO 0)
);
END COMPONENT;
BEGIN
result <= sub_wire0(8 DOWNTO 0);
lpm_add_sub_component : lpm_add_sub
GENERIC MAP (
lpm_direction => "ADD",
lpm_hint => "ONE_INPUT_IS_CONSTANT=NO,CIN_USED=NO",
lpm_representation => "UNSIGNED",
lpm_type => "LPM_ADD_SUB",
lpm_width => 9
)
PORT MAP (
dataa => dataa,
datab => datab,
result => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: CarryIn NUMERIC "0"
-- Retrieval info: PRIVATE: CarryOut NUMERIC "0"
-- Retrieval info: PRIVATE: ConstantA NUMERIC "0"
-- Retrieval info: PRIVATE: ConstantB NUMERIC "0"
-- Retrieval info: PRIVATE: Function NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "0"
-- Retrieval info: PRIVATE: Latency NUMERIC "0"
-- Retrieval info: PRIVATE: Overflow NUMERIC "0"
-- Retrieval info: PRIVATE: RadixA NUMERIC "10"
-- Retrieval info: PRIVATE: RadixB NUMERIC "10"
-- Retrieval info: PRIVATE: Representation NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: ValidCtA NUMERIC "0"
-- Retrieval info: PRIVATE: ValidCtB NUMERIC "0"
-- Retrieval info: PRIVATE: WhichConstant NUMERIC "0"
-- Retrieval info: PRIVATE: aclr NUMERIC "0"
-- Retrieval info: PRIVATE: clken NUMERIC "0"
-- Retrieval info: PRIVATE: nBit NUMERIC "9"
-- Retrieval info: CONSTANT: LPM_DIRECTION STRING "ADD"
-- Retrieval info: CONSTANT: LPM_HINT STRING "ONE_INPUT_IS_CONSTANT=NO,CIN_USED=NO"
-- Retrieval info: CONSTANT: LPM_REPRESENTATION STRING "UNSIGNED"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_ADD_SUB"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "9"
-- Retrieval info: USED_PORT: dataa 0 0 9 0 INPUT NODEFVAL dataa[8..0]
-- Retrieval info: USED_PORT: datab 0 0 9 0 INPUT NODEFVAL datab[8..0]
-- Retrieval info: USED_PORT: result 0 0 9 0 OUTPUT NODEFVAL result[8..0]
-- Retrieval info: CONNECT: result 0 0 9 0 @result 0 0 9 0
-- Retrieval info: CONNECT: @dataa 0 0 9 0 dataa 0 0 9 0
-- Retrieval info: CONNECT: @datab 0 0 9 0 datab 0 0 9 0
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_add_sub_db0.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_add_sub_db0.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_add_sub_db0.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_add_sub_db0.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_add_sub_db0_inst.vhd FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_add_sub_db0_waveforms.html FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_add_sub_db0_wave*.jpg FALSE
-- Retrieval info: LIB_FILE: lpm
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: syncfifo
-- File: syncfifo.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: syncronous fifo using syncram_2p
------------------------------------------------------------------------------
library ieee;
library techmap;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
library grlib;
use grlib.stdlib.all;
entity syncfifo is
generic (tech : integer := 0; abits : integer := 6; dbits : integer := 8;
sepclk : integer := 0; wrfst : integer := 0);
port (
rst : in std_ulogic;
rclk : in std_ulogic;
renable : in std_ulogic;
dataout : out std_logic_vector((dbits -1) downto 0);
wclk : in std_ulogic;
write : in std_ulogic;
datain : in std_logic_vector((dbits -1) downto 0);
full : out std_ulogic;
empty : out std_ulogic
);
end;
architecture rtl of syncfifo is
type reg_type is record
raddr, waddr : std_logic_vector(abits downto 0);
full, empty, notempty : std_ulogic;
end record;
signal r, rin : reg_type;
begin
comb : process (rst, write, renable, r)
variable v : reg_type;
begin
v := r;
if renable = '1' then v.raddr := r.raddr + 1; end if;
if write = '1' then v.waddr := r.waddr + 1; end if;
if (v.raddr(abits-1) = v.waddr(abits-1)) then
if (v.raddr(abits) = v.waddr(abits)) then
v.full := '0'; v.empty := '1';
else v.full := '1'; v.empty := '0'; end if;
else v.full := '0'; v.empty := '0'; end if;
if rst = '0' then
v.raddr := (others => '0'); v.waddr := (others => '0');
v.full := '0'; v.empty := '1';
end if;
rin <= v;
end process;
full <= r.full; empty <= r.empty;
regs : process (rclk)
begin
if rising_edge(rclk) then
r <= rin;
end if;
end process;
x0 : syncram_2p generic map (tech, abits, dbits, sepclk)
port map (rclk, renable, r.raddr(abits-1 downto 0), dataout,
wclk, write, r.waddr(abits-1 downto 0), datain);
end;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: syncfifo
-- File: syncfifo.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: syncronous fifo using syncram_2p
------------------------------------------------------------------------------
library ieee;
library techmap;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
library grlib;
use grlib.stdlib.all;
entity syncfifo is
generic (tech : integer := 0; abits : integer := 6; dbits : integer := 8;
sepclk : integer := 0; wrfst : integer := 0);
port (
rst : in std_ulogic;
rclk : in std_ulogic;
renable : in std_ulogic;
dataout : out std_logic_vector((dbits -1) downto 0);
wclk : in std_ulogic;
write : in std_ulogic;
datain : in std_logic_vector((dbits -1) downto 0);
full : out std_ulogic;
empty : out std_ulogic
);
end;
architecture rtl of syncfifo is
type reg_type is record
raddr, waddr : std_logic_vector(abits downto 0);
full, empty, notempty : std_ulogic;
end record;
signal r, rin : reg_type;
begin
comb : process (rst, write, renable, r)
variable v : reg_type;
begin
v := r;
if renable = '1' then v.raddr := r.raddr + 1; end if;
if write = '1' then v.waddr := r.waddr + 1; end if;
if (v.raddr(abits-1) = v.waddr(abits-1)) then
if (v.raddr(abits) = v.waddr(abits)) then
v.full := '0'; v.empty := '1';
else v.full := '1'; v.empty := '0'; end if;
else v.full := '0'; v.empty := '0'; end if;
if rst = '0' then
v.raddr := (others => '0'); v.waddr := (others => '0');
v.full := '0'; v.empty := '1';
end if;
rin <= v;
end process;
full <= r.full; empty <= r.empty;
regs : process (rclk)
begin
if rising_edge(rclk) then
r <= rin;
end if;
end process;
x0 : syncram_2p generic map (tech, abits, dbits, sepclk)
port map (rclk, renable, r.raddr(abits-1 downto 0), dataout,
wclk, write, r.waddr(abits-1 downto 0), datain);
end;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity threeph is
Port (
clk: in STD_LOGIC;
ibus: in STD_LOGIC_VECTOR (15 downto 0);
obus: out STD_LOGIC_VECTOR (15 downto 0);
crload: in STD_LOGIC;
crread: in STD_LOGIC;
rateload: in STD_LOGIC;
rateread: in STD_LOGIC;
phaseouta: out STD_LOGIC;
phaseoutb: out STD_LOGIC;
phaseoutc: out STD_LOGIC
);
end threeph;
architecture behavioral of threeph is
signal prescale: STD_LOGIC_VECTOR (12 downto 0);
signal creg: STD_LOGIC_VECTOR (2 downto 0);
signal phaseacc: STD_LOGIC_VECTOR (16 downto 0);
alias phasemsb: std_logic is phaseacc(16);
signal phstate: STD_LOGIC_VECTOR (2 downto 0);
signal oldphasemsb: std_logic;
signal phaselatch: STD_LOGIC_VECTOR (15 downto 0);
signal phasea : std_logic;
signal phaseb : std_logic;
signal phasec : std_logic;
begin
athreephase: process (clk,
crread,
rateread)
begin
if clk'event and clk = '1' then
if creg(0) = '0' then
phstate <= "000";
end if;
phaseacc <= phaseacc + phaselatch;
oldphasemsb <= phasemsb;
if oldphasemsb /= phasemsb then
prescale <= prescale + 1;
if prescale = 0 then
phstate <= phstate +1;
if phstate = 5 then
phstate <= "000";
end if;
end if; -- prescale = 0
end if; -- old /= new
if rateload = '1' then
phaselatch <= ibus;
end if;
if crload = '1' then
creg <= ibus(2 downto 0);
end if;
end if; -- clk
if crread = '1' and rateread = '0' then
obus(2 downto 0) <= creg;
obus(15 downto 3) <= "0000000000000";
elsif rateread = '1' and crread = '0' then
obus <= phaselatch;
else
obus <= "ZZZZZZZZZZZZZZZZ";
end if;
case phstate is
when "000" =>
phasea <= '1';
phaseb <= '0';
phasec <= '1';
when "001" =>
phasea <= '1';
phaseb <= '0';
phasec <= '0';
when "010" =>
phasea <= '1';
phaseb <= '1';
phasec <= '0';
when "011" =>
phasea <= '0';
phaseb <= '1';
phasec <= '0';
when "100" =>
phasea <= '0';
phaseb <= '1';
phasec <= '1';
when "101" =>
phasea <= '0';
phaseb <= '0';
phasec <= '1';
when others => -- start
phasea <= '1';
phaseb <= '0';
phasec <= '1';
end case;
if creg(1) = '1' then
if creg(2) = '0' then
phaseouta <= phasea;
phaseoutb <= phaseb;
phaseoutc <= phasec;
else
phaseouta <= phaseb;
phaseoutb <= phasea;
phaseoutc <= phasec;
end if;
else
phaseouta <= 'Z';
phaseoutb <= 'Z';
phaseoutc <= 'Z';
end if;
end process;
end behavioral;
|
-------------------------------------------------------------------------------
-- $Id: srl_fifo2.vhd,v 1.1.4.1 2010/09/14 22:35:47 dougt Exp $
-------------------------------------------------------------------------------
-- srl_fifo2 - entity / architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2002-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: srl_fifo2.vhd
--
-- Description: same as srl_fifo except the Addr port has the correct bit
-- ordering, there is a true FIFO_Empty port, and the C_DEPTH
-- generic actually controlls how many elements the fifo will
-- hold (up to 16). includes an assertion statement to check
-- that C_DEPTH is less than or equal to 16. changed
-- C_DATA_BITS to C_DWIDTH and changed it from natural to
-- positive (the width should be 1 or greater, zero width
-- didn't make sense to me!). Changed C_DEPTH from natural
-- to positive (zero elements doesn't make sense).
-- The Addr port in srl_fifo has the bits reversed which
-- made it more difficult to use. C_DEPTH was not used in
-- srl_fifo. Data_Exists is delayed by one clock so it is
-- not usefull for generating an empty flag. FIFO_Empty is
-- generated directly from the address, the same way that
-- FIFO_Full is generated.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- srl_fifo2.vhd
--
-------------------------------------------------------------------------------
-- Author: jam
--
-- History:
-- jam 02/20/02 First Version - modified from original srl_fifo
--
-- DCW 2002-03-12 Structural implementation of synchronous reset for
-- Data_Exists DFF (using FDR)
-- jam 04/12/02 Added C_XON generic for mixed vhdl/verilog sims
--
-- als 2002-04-18 added default for XON generic in SRL16E, FDRE, and FDR
-- component declarations
-- jam 2002-05-01 changed FIFO_Empty output from buffer_Empty, which had a
-- clock delay, to the not of data_Exists_I, which doesn't
-- have any delay
--
-- DET 1/17/2008 v3_00_a
-- ~~~~~~
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
library unisim;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all; -- conv_std_logic_vector
use unisim.all;
entity srl_fifo2 is
generic (
C_DWIDTH : positive := 8; -- changed to positive
C_DEPTH : positive := 16; -- changed to positive
C_XON : boolean := false -- added for mixed mode sims
);
port (
Clk : in std_logic;
Reset : in std_logic;
FIFO_Write : in std_logic;
Data_In : in std_logic_vector(0 to C_DWIDTH-1);
FIFO_Read : in std_logic;
Data_Out : out std_logic_vector(0 to C_DWIDTH-1);
FIFO_Full : out std_logic;
FIFO_Empty : out std_logic; -- new port
Data_Exists : out std_logic;
Addr : out std_logic_vector(0 to 3)
);
end entity srl_fifo2;
architecture imp of srl_fifo2 is
-- convert C_DEPTH to a std_logic_vector so FIFO_Full can be generated
-- based on the selected depth rather than fixed at 16
constant DEPTH : std_logic_vector(0 to 3) :=
conv_std_logic_vector(C_DEPTH-1,4);
component SRL16E is
-- pragma translate_off
generic (
INIT : bit_vector := X"0000"
);
-- pragma translate_on
port (
CE : in std_logic;
D : in std_logic;
Clk : in std_logic;
A0 : in std_logic;
A1 : in std_logic;
A2 : in std_logic;
A3 : in std_logic;
Q : out std_logic);
end component SRL16E;
-- component LUT4
-- generic(
-- INIT : bit_vector := X"0000"
-- );
-- port (
-- O : out std_logic;
-- I0 : in std_logic;
-- I1 : in std_logic;
-- I2 : in std_logic;
-- I3 : in std_logic);
-- end component;
component MULT_AND
port (
I0 : in std_logic;
I1 : in std_logic;
LO : out std_logic);
end component;
component MUXCY_L
port (
DI : in std_logic;
CI : in std_logic;
S : in std_logic;
LO : out std_logic);
end component;
component XORCY
port (
LI : in std_logic;
CI : in std_logic;
O : out std_logic);
end component;
component FDRE is
port (
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
R : in std_logic);
end component FDRE;
component FDR is
port (
Q : out std_logic;
C : in std_logic;
D : in std_logic;
R : in std_logic);
end component FDR;
signal addr_i : std_logic_vector(0 to 3);
signal buffer_Full : std_logic;
signal buffer_Empty : std_logic;
signal next_Data_Exists : std_logic;
signal data_Exists_I : std_logic;
signal valid_Write : std_logic;
signal hsum_A : std_logic_vector(0 to 3);
signal sum_A : std_logic_vector(0 to 3);
signal addr_cy : std_logic_vector(0 to 4);
begin -- architecture IMP
-- C_DEPTH is positive so that ensures the fifo is at least 1 element deep
-- make sure it is not greater than 16 locations deep
-- pragma translate_off
assert C_DEPTH <= 16
report "SRL Fifo's must be 16 or less elements deep"
severity FAILURE;
-- pragma translate_on
-- since srl16 address is 3 downto 0 need to compare individual bits
-- didn't muck with addr_i since the basic addressing works - Addr output
-- is generated correctly below
buffer_Full <= '1' when (addr_i(0) = DEPTH(3) and
addr_i(1) = DEPTH(2) and
addr_i(2) = DEPTH(1) and
addr_i(3) = DEPTH(0)
) else '0';
FIFO_Full <= buffer_Full;
buffer_Empty <= '1' when (addr_i = "0000") else '0';
FIFO_Empty <= not data_Exists_I; -- generate a true empty flag with no delay
-- was buffer_Empty, which had a clock dly
next_Data_Exists <= (data_Exists_I and not buffer_Empty) or
(buffer_Empty and FIFO_Write) or
(data_Exists_I and not FIFO_Read);
Data_Exists_DFF : FDR
port map (
Q => data_Exists_I, -- [out std_logic]
C => Clk, -- [in std_logic]
D => next_Data_Exists, -- [in std_logic]
R => Reset); -- [in std_logic]
Data_Exists <= data_Exists_I;
valid_Write <= FIFO_Write and (FIFO_Read or not buffer_Full);
addr_cy(0) <= valid_Write;
Addr_Counters : for I in 0 to 3 generate
hsum_A(I) <= (FIFO_Read xor addr_i(I)) and (FIFO_Write or not buffer_Empty);
MUXCY_L_I : MUXCY_L
port map (
DI => addr_i(I), -- [in std_logic]
CI => addr_cy(I), -- [in std_logic]
S => hsum_A(I), -- [in std_logic]
LO => addr_cy(I+1)); -- [out std_logic]
XORCY_I : XORCY
port map (
LI => hsum_A(I), -- [in std_logic]
CI => addr_cy(I), -- [in std_logic]
O => sum_A(I)); -- [out std_logic]
FDRE_I : FDRE
port map (
Q => addr_i(I), -- [out std_logic]
C => Clk, -- [in std_logic]
CE => data_Exists_I, -- [in std_logic]
D => sum_A(I), -- [in std_logic]
R => Reset); -- [in std_logic]
end generate Addr_Counters;
FIFO_RAM : for I in 0 to C_DWIDTH-1 generate
SRL16E_I : SRL16E
-- pragma translate_off
generic map (
INIT => x"0000")
-- pragma translate_on
port map (
CE => valid_Write, -- [in std_logic]
D => Data_In(I), -- [in std_logic]
Clk => Clk, -- [in std_logic]
A0 => addr_i(0), -- [in std_logic]
A1 => addr_i(1), -- [in std_logic]
A2 => addr_i(2), -- [in std_logic]
A3 => addr_i(3), -- [in std_logic]
Q => Data_Out(I)); -- [out std_logic]
end generate FIFO_RAM;
-------------------------------------------------------------------------------
-- INT_ADDR_PROCESS
-------------------------------------------------------------------------------
-- This process assigns the internal address to the output port
-------------------------------------------------------------------------------
-- modified the process to flip the bits since the address bits from the
-- srl16 are 3 downto 0 and Addr needs to be 0 to 3
INT_ADDR_PROCESS:process (addr_i)
begin -- process
for i in Addr'range
loop
Addr(i) <= addr_i(3 - i); -- flip the bits to account for srl16 addr
end loop;
end process;
end architecture imp;
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.1
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
Library ieee;
use ieee.std_logic_1164.all;
entity sin_taylor_serieseOg is
generic (
ID : integer := 9;
NUM_STAGE : integer := 31;
din0_WIDTH : integer := 64;
din1_WIDTH : integer := 64;
dout_WIDTH : integer := 64
);
port (
clk : in std_logic;
reset : in std_logic;
ce : in std_logic;
din0 : in std_logic_vector(din0_WIDTH-1 downto 0);
din1 : in std_logic_vector(din1_WIDTH-1 downto 0);
dout : out std_logic_vector(dout_WIDTH-1 downto 0)
);
end entity;
architecture arch of sin_taylor_serieseOg is
--------------------- Component ---------------------
component sin_taylor_series_ap_ddiv_29_no_dsp_64 is
port (
aclk : in std_logic;
aclken : in std_logic;
s_axis_a_tvalid : in std_logic;
s_axis_a_tdata : in std_logic_vector(63 downto 0);
s_axis_b_tvalid : in std_logic;
s_axis_b_tdata : in std_logic_vector(63 downto 0);
m_axis_result_tvalid : out std_logic;
m_axis_result_tdata : out std_logic_vector(63 downto 0)
);
end component;
--------------------- Local signal ------------------
signal aclk : std_logic;
signal aclken : std_logic;
signal a_tvalid : std_logic;
signal a_tdata : std_logic_vector(63 downto 0);
signal b_tvalid : std_logic;
signal b_tdata : std_logic_vector(63 downto 0);
signal r_tvalid : std_logic;
signal r_tdata : std_logic_vector(63 downto 0);
signal din0_buf1 : std_logic_vector(din0_WIDTH-1 downto 0);
signal din1_buf1 : std_logic_vector(din1_WIDTH-1 downto 0);
begin
--------------------- Instantiation -----------------
sin_taylor_series_ap_ddiv_29_no_dsp_64_u : component sin_taylor_series_ap_ddiv_29_no_dsp_64
port map (
aclk => aclk,
aclken => aclken,
s_axis_a_tvalid => a_tvalid,
s_axis_a_tdata => a_tdata,
s_axis_b_tvalid => b_tvalid,
s_axis_b_tdata => b_tdata,
m_axis_result_tvalid => r_tvalid,
m_axis_result_tdata => r_tdata
);
--------------------- Assignment --------------------
aclk <= clk;
aclken <= ce;
a_tvalid <= '1';
a_tdata <= din0_buf1;
b_tvalid <= '1';
b_tdata <= din1_buf1;
dout <= r_tdata;
--------------------- Input buffer ------------------
process (clk) begin
if clk'event and clk = '1' then
if ce = '1' then
din0_buf1 <= din0;
din1_buf1 <= din1;
end if;
end if;
end process;
end architecture;
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.1
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
Library ieee;
use ieee.std_logic_1164.all;
entity sin_taylor_serieseOg is
generic (
ID : integer := 9;
NUM_STAGE : integer := 31;
din0_WIDTH : integer := 64;
din1_WIDTH : integer := 64;
dout_WIDTH : integer := 64
);
port (
clk : in std_logic;
reset : in std_logic;
ce : in std_logic;
din0 : in std_logic_vector(din0_WIDTH-1 downto 0);
din1 : in std_logic_vector(din1_WIDTH-1 downto 0);
dout : out std_logic_vector(dout_WIDTH-1 downto 0)
);
end entity;
architecture arch of sin_taylor_serieseOg is
--------------------- Component ---------------------
component sin_taylor_series_ap_ddiv_29_no_dsp_64 is
port (
aclk : in std_logic;
aclken : in std_logic;
s_axis_a_tvalid : in std_logic;
s_axis_a_tdata : in std_logic_vector(63 downto 0);
s_axis_b_tvalid : in std_logic;
s_axis_b_tdata : in std_logic_vector(63 downto 0);
m_axis_result_tvalid : out std_logic;
m_axis_result_tdata : out std_logic_vector(63 downto 0)
);
end component;
--------------------- Local signal ------------------
signal aclk : std_logic;
signal aclken : std_logic;
signal a_tvalid : std_logic;
signal a_tdata : std_logic_vector(63 downto 0);
signal b_tvalid : std_logic;
signal b_tdata : std_logic_vector(63 downto 0);
signal r_tvalid : std_logic;
signal r_tdata : std_logic_vector(63 downto 0);
signal din0_buf1 : std_logic_vector(din0_WIDTH-1 downto 0);
signal din1_buf1 : std_logic_vector(din1_WIDTH-1 downto 0);
begin
--------------------- Instantiation -----------------
sin_taylor_series_ap_ddiv_29_no_dsp_64_u : component sin_taylor_series_ap_ddiv_29_no_dsp_64
port map (
aclk => aclk,
aclken => aclken,
s_axis_a_tvalid => a_tvalid,
s_axis_a_tdata => a_tdata,
s_axis_b_tvalid => b_tvalid,
s_axis_b_tdata => b_tdata,
m_axis_result_tvalid => r_tvalid,
m_axis_result_tdata => r_tdata
);
--------------------- Assignment --------------------
aclk <= clk;
aclken <= ce;
a_tvalid <= '1';
a_tdata <= din0_buf1;
b_tvalid <= '1';
b_tdata <= din1_buf1;
dout <= r_tdata;
--------------------- Input buffer ------------------
process (clk) begin
if clk'event and clk = '1' then
if ce = '1' then
din0_buf1 <= din0;
din1_buf1 <= din1;
end if;
end if;
end process;
end architecture;
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.1
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
Library ieee;
use ieee.std_logic_1164.all;
entity sin_taylor_serieseOg is
generic (
ID : integer := 9;
NUM_STAGE : integer := 31;
din0_WIDTH : integer := 64;
din1_WIDTH : integer := 64;
dout_WIDTH : integer := 64
);
port (
clk : in std_logic;
reset : in std_logic;
ce : in std_logic;
din0 : in std_logic_vector(din0_WIDTH-1 downto 0);
din1 : in std_logic_vector(din1_WIDTH-1 downto 0);
dout : out std_logic_vector(dout_WIDTH-1 downto 0)
);
end entity;
architecture arch of sin_taylor_serieseOg is
--------------------- Component ---------------------
component sin_taylor_series_ap_ddiv_29_no_dsp_64 is
port (
aclk : in std_logic;
aclken : in std_logic;
s_axis_a_tvalid : in std_logic;
s_axis_a_tdata : in std_logic_vector(63 downto 0);
s_axis_b_tvalid : in std_logic;
s_axis_b_tdata : in std_logic_vector(63 downto 0);
m_axis_result_tvalid : out std_logic;
m_axis_result_tdata : out std_logic_vector(63 downto 0)
);
end component;
--------------------- Local signal ------------------
signal aclk : std_logic;
signal aclken : std_logic;
signal a_tvalid : std_logic;
signal a_tdata : std_logic_vector(63 downto 0);
signal b_tvalid : std_logic;
signal b_tdata : std_logic_vector(63 downto 0);
signal r_tvalid : std_logic;
signal r_tdata : std_logic_vector(63 downto 0);
signal din0_buf1 : std_logic_vector(din0_WIDTH-1 downto 0);
signal din1_buf1 : std_logic_vector(din1_WIDTH-1 downto 0);
begin
--------------------- Instantiation -----------------
sin_taylor_series_ap_ddiv_29_no_dsp_64_u : component sin_taylor_series_ap_ddiv_29_no_dsp_64
port map (
aclk => aclk,
aclken => aclken,
s_axis_a_tvalid => a_tvalid,
s_axis_a_tdata => a_tdata,
s_axis_b_tvalid => b_tvalid,
s_axis_b_tdata => b_tdata,
m_axis_result_tvalid => r_tvalid,
m_axis_result_tdata => r_tdata
);
--------------------- Assignment --------------------
aclk <= clk;
aclken <= ce;
a_tvalid <= '1';
a_tdata <= din0_buf1;
b_tvalid <= '1';
b_tdata <= din1_buf1;
dout <= r_tdata;
--------------------- Input buffer ------------------
process (clk) begin
if clk'event and clk = '1' then
if ce = '1' then
din0_buf1 <= din0;
din1_buf1 <= din1;
end if;
end if;
end process;
end architecture;
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.1
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
Library ieee;
use ieee.std_logic_1164.all;
entity sin_taylor_serieseOg is
generic (
ID : integer := 9;
NUM_STAGE : integer := 31;
din0_WIDTH : integer := 64;
din1_WIDTH : integer := 64;
dout_WIDTH : integer := 64
);
port (
clk : in std_logic;
reset : in std_logic;
ce : in std_logic;
din0 : in std_logic_vector(din0_WIDTH-1 downto 0);
din1 : in std_logic_vector(din1_WIDTH-1 downto 0);
dout : out std_logic_vector(dout_WIDTH-1 downto 0)
);
end entity;
architecture arch of sin_taylor_serieseOg is
--------------------- Component ---------------------
component sin_taylor_series_ap_ddiv_29_no_dsp_64 is
port (
aclk : in std_logic;
aclken : in std_logic;
s_axis_a_tvalid : in std_logic;
s_axis_a_tdata : in std_logic_vector(63 downto 0);
s_axis_b_tvalid : in std_logic;
s_axis_b_tdata : in std_logic_vector(63 downto 0);
m_axis_result_tvalid : out std_logic;
m_axis_result_tdata : out std_logic_vector(63 downto 0)
);
end component;
--------------------- Local signal ------------------
signal aclk : std_logic;
signal aclken : std_logic;
signal a_tvalid : std_logic;
signal a_tdata : std_logic_vector(63 downto 0);
signal b_tvalid : std_logic;
signal b_tdata : std_logic_vector(63 downto 0);
signal r_tvalid : std_logic;
signal r_tdata : std_logic_vector(63 downto 0);
signal din0_buf1 : std_logic_vector(din0_WIDTH-1 downto 0);
signal din1_buf1 : std_logic_vector(din1_WIDTH-1 downto 0);
begin
--------------------- Instantiation -----------------
sin_taylor_series_ap_ddiv_29_no_dsp_64_u : component sin_taylor_series_ap_ddiv_29_no_dsp_64
port map (
aclk => aclk,
aclken => aclken,
s_axis_a_tvalid => a_tvalid,
s_axis_a_tdata => a_tdata,
s_axis_b_tvalid => b_tvalid,
s_axis_b_tdata => b_tdata,
m_axis_result_tvalid => r_tvalid,
m_axis_result_tdata => r_tdata
);
--------------------- Assignment --------------------
aclk <= clk;
aclken <= ce;
a_tvalid <= '1';
a_tdata <= din0_buf1;
b_tvalid <= '1';
b_tdata <= din1_buf1;
dout <= r_tdata;
--------------------- Input buffer ------------------
process (clk) begin
if clk'event and clk = '1' then
if ce = '1' then
din0_buf1 <= din0;
din1_buf1 <= din1;
end if;
end if;
end process;
end architecture;
|
-- file: i_fetch_test_stream_instr_stream_pkg.vhd (version: i_fetch_test_stream_instr_stream_pkg_non_aligned_branches.vhd)
-- Written by Gandhi Puvvada
-- date of last rivision: 7/23/2008
--
-- A package file to define the instruction stream to be placed in the instr_cache.
-- This package, "instr_stream_pkg", is refered in a use clause in the inst_cache_sprom module.
-- We will use several files similar to this containining different instruction streams.
-- The package name will remain the same, namely instr_stream_pkg.
-- Only the file name changes from, say i_fetch_test_stream_instr_stream_pkg.vhd
-- to say mult_test_stream_instr_stream_pkg.vhd.
-- Depending on which instr_stream_pkg file was analysed/compiled most recently,
-- that stream will be used for simulation/synthesis.
----------------------------------------------------------
library std, ieee;
use ieee.std_logic_1164.all;
package instr_stream_pkg is
constant DATA_WIDTH_CONSTANT : integer := 128; -- data width of of our cache
constant ADDR_WIDTH_CONSTANT : integer := 6; -- address width of our cache
-- type declarations
type mem_type is array (0 to (2**ADDR_WIDTH_CONSTANT)-1) of std_logic_vector((DATA_WIDTH_CONSTANT-1) downto 0);
---------------------------------------------------
---------------------------------------------------
-- All instructions are mul $2 $2 $2
---------------------------------------------------
---------------------------------------------------
signal mem : mem_type :=
(X"00421019_00421019_00421019_00421019", -- Loc 0C, 08, 04, 00
X"00421019_00421019_00421019_00421019", -- Loc 1C, 18, 14, 10
X"00421019_00421019_00421019_00421019", -- Loc 2C, 28, 24, 20
X"00421019_00421019_00421019_00421019", -- Loc 3C, 38, 34, 30
X"00421019_00421019_00421019_00421019", -- Loc 4C, 48, 44, 40
X"00421019_00421019_00421019_00421019", -- Loc 5C, 58, 54, 50
X"00421019_00421019_00421019_00421019", -- Loc 6C, 68, 64, 60
X"00421019_00421019_00421019_00421019", -- Loc 7C, 78, 74, 70
X"00421019_00421019_00421019_00421019", -- Loc 8C, 88, 84, 80
X"00421019_00421019_00421019_00421019", -- Loc 9C, 98, 94, 90
X"00421019_00421019_00421019_00421019", -- Loc AC, A8, A4, A0
X"00421019_00421019_00421019_00421019", -- Loc BC, B8, B4, B0
X"00421019_00421019_00421019_00421019", -- Loc CC, C8, C4, C0
X"00421019_00421019_00421019_00421019", -- Loc DC, D8, D4, D0
X"00421019_00421019_00421019_00421019", -- Loc EC, E8, E4, E0
X"00421019_00421019_00421019_00421019", -- Loc FC, F8, F4, F0
X"00421019_00421019_00421019_00421019", -- Loc 10C, 108, 104, 100
X"00421019_00421019_00421019_00421019", -- Loc 11C, 118, 114, 110
X"00421019_00421019_00421019_00421019", -- Loc 12C, 128, 124, 120
X"00421019_00421019_00421019_00421019", -- Loc 13C, 138, 134, 130
X"00421019_00421019_00421019_00421019", -- Loc 14C, 148, 144, 140
X"00421019_00421019_00421019_00421019", -- Loc 15C, 158, 154, 150
X"00421019_00421019_00421019_00421019", -- Loc 16C, 168, 164, 160
X"00421019_00421019_00421019_00421019", -- Loc 17C, 178, 174, 170
X"00421019_00421019_00421019_00421019", -- Loc 18C, 188, 184, 180
X"00421019_00421019_00421019_00421019", -- Loc 19C, 198, 194, 190
X"00421019_00421019_00421019_00421019", -- Loc 1AC, 1A8, 1A4, 1A0
X"00421019_00421019_00421019_00421019", -- Loc 1BC, 1B8, 1B4, 1B0
X"00421019_00421019_00421019_00421019", -- Loc 1CC, 1C8, 1C4, 1C0
X"00421019_00421019_00421019_00421019", -- Loc 1DC, 1D8, 1D4, 1D0
X"00421019_00421019_00421019_00421019", -- Loc 1EC, 1E8, 1E4, 1E0
X"00421019_00421019_00421019_00421019", -- Loc 1FC, 1F8, 1F4, 1F0
X"00421019_00421019_00421019_00421019", -- Loc 20C, 208, 204, 200
X"00421019_00421019_00421019_00421019", -- Loc 21C, 218, 214, 221
X"00421019_00421019_00421019_00421019", -- Loc 22C, 228, 224, 220
X"00421019_00421019_00421019_00421019", -- Loc 23C, 238, 234, 230
X"00421019_00421019_00421019_00421019", -- Loc 24C, 248, 244, 240
X"00421019_00421019_00421019_00421019", -- Loc 25C, 258, 254, 250
X"00421019_00421019_00421019_00421019", -- Loc 26C, 268, 264, 260
X"00421019_00421019_00421019_00421019", -- Loc 27C, 278, 274, 270
X"00421019_00421019_00421019_00421019", -- Loc 28C, 288, 284, 280
X"00421019_00421019_00421019_00421019", -- Loc 29C, 298, 294, 290
X"00421019_00421019_00421019_00421019", -- Loc 2AC, 2A8, 2A4, 2A0
X"00421019_00421019_00421019_00421019", -- Loc 2BC, 2B8, 2B4, 2B0
X"00421019_00421019_00421019_00421019", -- Loc 2CC, 2C8, 2C4, 2C0
X"00421019_00421019_00421019_00421019", -- Loc 2DC, 2D8, 2D4, 2D0
X"00421019_00421019_00421019_00421019", -- Loc 2EC, 2E8, 2E4, 2E0
X"00421019_00421019_00421019_00421019", -- Loc 2FC, 2F8, 2F4, 2F0
X"00421019_00421019_00421019_00421019", -- Loc 30C, 308, 304, 300
X"00421019_00421019_00421019_00421019", -- Loc 31C, 318, 314, 331
X"00421019_00421019_00421019_00421019", -- Loc 32C, 328, 324, 320
X"00421019_00421019_00421019_00421019", -- Loc 33C, 338, 334, 330
X"00421019_00421019_00421019_00421019", -- Loc 34C, 348, 344, 340
X"00421019_00421019_00421019_00421019", -- Loc 35C, 358, 354, 350
X"00421019_00421019_00421019_00421019", -- Loc 36C, 368, 364, 360
X"00421019_00421019_00421019_00421019", -- Loc 37C, 378, 374, 370
X"00421019_00421019_00421019_00421019", -- Loc 38C, 388, 384, 380
X"00421019_00421019_00421019_00421019", -- Loc 39C, 398, 394, 390
X"00421019_00421019_00421019_00421019", -- Loc 3AC, 3A8, 3A4, 3A0
X"00421019_00421019_00421019_00421019", -- Loc 3BC, 3B8, 3B4, 3B0
-- the last 16 instructions are looping ump instructions
X"080000F3_080000F2_080000F1_080000F0", -- Loc 3CC, 3C8, 3C4, 3C0
X"080000F7_080000F6_080000F5_080000F4", -- Loc 3DC, 3D8, 3D4, 3D0
X"080000FB_080000FA_080000F9_080000F8", -- Loc 3EC, 3E8, 3E4, 3E0
X"080000FF_080000FE_080000FD_080000FC" -- Loc 3FC, 3F8, 3F4, 3F0
) ;
-- the last 16 instructions are looping jump instructions
-- of the type: loop: j loop
-- This is to make sure that neither instruction fetching
-- nor instruction execution proceeds beyond the end of this memory.
-- Loc 3C0 -- 080000F0 => J 240
-- Loc 3C4 -- 080000F1 => J 241
-- Loc 3C8 -- 080000F2 => J 242
-- Loc 3CC -- 080000F3 => J 243
--
-- Loc 3D0 -- 080000F4 => J 244
-- Loc 3D4 -- 080000F5 => J 245
-- Loc 3D8 -- 080000F6 => J 246
-- Loc 3DC -- 080000F7 => J 247
--
-- Loc 3E0 -- 080000F8 => J 248
-- Loc 3E4 -- 080000F9 => J 249
-- Loc 3E8 -- 080000FA => J 250
-- Loc 3EC -- 080000FB => J 251
--
-- Loc 3F0 -- 080000FC => J 252
-- Loc 3F4 -- 080000FD => J 253
-- Loc 3F8 -- 080000FE => J 254
-- Loc 3FC -- 080000FF => J 255
end package instr_stream_pkg;
-- -- No need for s package body here
-- package body instr_stream_pkg is
--
-- end package body instr_stream_pkg;
|
-- file: i_fetch_test_stream_instr_stream_pkg.vhd (version: i_fetch_test_stream_instr_stream_pkg_non_aligned_branches.vhd)
-- Written by Gandhi Puvvada
-- date of last rivision: 7/23/2008
--
-- A package file to define the instruction stream to be placed in the instr_cache.
-- This package, "instr_stream_pkg", is refered in a use clause in the inst_cache_sprom module.
-- We will use several files similar to this containining different instruction streams.
-- The package name will remain the same, namely instr_stream_pkg.
-- Only the file name changes from, say i_fetch_test_stream_instr_stream_pkg.vhd
-- to say mult_test_stream_instr_stream_pkg.vhd.
-- Depending on which instr_stream_pkg file was analysed/compiled most recently,
-- that stream will be used for simulation/synthesis.
----------------------------------------------------------
library std, ieee;
use ieee.std_logic_1164.all;
package instr_stream_pkg is
constant DATA_WIDTH_CONSTANT : integer := 128; -- data width of of our cache
constant ADDR_WIDTH_CONSTANT : integer := 6; -- address width of our cache
-- type declarations
type mem_type is array (0 to (2**ADDR_WIDTH_CONSTANT)-1) of std_logic_vector((DATA_WIDTH_CONSTANT-1) downto 0);
---------------------------------------------------
---------------------------------------------------
-- All instructions are mul $2 $2 $2
---------------------------------------------------
---------------------------------------------------
signal mem : mem_type :=
(X"00421019_00421019_00421019_00421019", -- Loc 0C, 08, 04, 00
X"00421019_00421019_00421019_00421019", -- Loc 1C, 18, 14, 10
X"00421019_00421019_00421019_00421019", -- Loc 2C, 28, 24, 20
X"00421019_00421019_00421019_00421019", -- Loc 3C, 38, 34, 30
X"00421019_00421019_00421019_00421019", -- Loc 4C, 48, 44, 40
X"00421019_00421019_00421019_00421019", -- Loc 5C, 58, 54, 50
X"00421019_00421019_00421019_00421019", -- Loc 6C, 68, 64, 60
X"00421019_00421019_00421019_00421019", -- Loc 7C, 78, 74, 70
X"00421019_00421019_00421019_00421019", -- Loc 8C, 88, 84, 80
X"00421019_00421019_00421019_00421019", -- Loc 9C, 98, 94, 90
X"00421019_00421019_00421019_00421019", -- Loc AC, A8, A4, A0
X"00421019_00421019_00421019_00421019", -- Loc BC, B8, B4, B0
X"00421019_00421019_00421019_00421019", -- Loc CC, C8, C4, C0
X"00421019_00421019_00421019_00421019", -- Loc DC, D8, D4, D0
X"00421019_00421019_00421019_00421019", -- Loc EC, E8, E4, E0
X"00421019_00421019_00421019_00421019", -- Loc FC, F8, F4, F0
X"00421019_00421019_00421019_00421019", -- Loc 10C, 108, 104, 100
X"00421019_00421019_00421019_00421019", -- Loc 11C, 118, 114, 110
X"00421019_00421019_00421019_00421019", -- Loc 12C, 128, 124, 120
X"00421019_00421019_00421019_00421019", -- Loc 13C, 138, 134, 130
X"00421019_00421019_00421019_00421019", -- Loc 14C, 148, 144, 140
X"00421019_00421019_00421019_00421019", -- Loc 15C, 158, 154, 150
X"00421019_00421019_00421019_00421019", -- Loc 16C, 168, 164, 160
X"00421019_00421019_00421019_00421019", -- Loc 17C, 178, 174, 170
X"00421019_00421019_00421019_00421019", -- Loc 18C, 188, 184, 180
X"00421019_00421019_00421019_00421019", -- Loc 19C, 198, 194, 190
X"00421019_00421019_00421019_00421019", -- Loc 1AC, 1A8, 1A4, 1A0
X"00421019_00421019_00421019_00421019", -- Loc 1BC, 1B8, 1B4, 1B0
X"00421019_00421019_00421019_00421019", -- Loc 1CC, 1C8, 1C4, 1C0
X"00421019_00421019_00421019_00421019", -- Loc 1DC, 1D8, 1D4, 1D0
X"00421019_00421019_00421019_00421019", -- Loc 1EC, 1E8, 1E4, 1E0
X"00421019_00421019_00421019_00421019", -- Loc 1FC, 1F8, 1F4, 1F0
X"00421019_00421019_00421019_00421019", -- Loc 20C, 208, 204, 200
X"00421019_00421019_00421019_00421019", -- Loc 21C, 218, 214, 221
X"00421019_00421019_00421019_00421019", -- Loc 22C, 228, 224, 220
X"00421019_00421019_00421019_00421019", -- Loc 23C, 238, 234, 230
X"00421019_00421019_00421019_00421019", -- Loc 24C, 248, 244, 240
X"00421019_00421019_00421019_00421019", -- Loc 25C, 258, 254, 250
X"00421019_00421019_00421019_00421019", -- Loc 26C, 268, 264, 260
X"00421019_00421019_00421019_00421019", -- Loc 27C, 278, 274, 270
X"00421019_00421019_00421019_00421019", -- Loc 28C, 288, 284, 280
X"00421019_00421019_00421019_00421019", -- Loc 29C, 298, 294, 290
X"00421019_00421019_00421019_00421019", -- Loc 2AC, 2A8, 2A4, 2A0
X"00421019_00421019_00421019_00421019", -- Loc 2BC, 2B8, 2B4, 2B0
X"00421019_00421019_00421019_00421019", -- Loc 2CC, 2C8, 2C4, 2C0
X"00421019_00421019_00421019_00421019", -- Loc 2DC, 2D8, 2D4, 2D0
X"00421019_00421019_00421019_00421019", -- Loc 2EC, 2E8, 2E4, 2E0
X"00421019_00421019_00421019_00421019", -- Loc 2FC, 2F8, 2F4, 2F0
X"00421019_00421019_00421019_00421019", -- Loc 30C, 308, 304, 300
X"00421019_00421019_00421019_00421019", -- Loc 31C, 318, 314, 331
X"00421019_00421019_00421019_00421019", -- Loc 32C, 328, 324, 320
X"00421019_00421019_00421019_00421019", -- Loc 33C, 338, 334, 330
X"00421019_00421019_00421019_00421019", -- Loc 34C, 348, 344, 340
X"00421019_00421019_00421019_00421019", -- Loc 35C, 358, 354, 350
X"00421019_00421019_00421019_00421019", -- Loc 36C, 368, 364, 360
X"00421019_00421019_00421019_00421019", -- Loc 37C, 378, 374, 370
X"00421019_00421019_00421019_00421019", -- Loc 38C, 388, 384, 380
X"00421019_00421019_00421019_00421019", -- Loc 39C, 398, 394, 390
X"00421019_00421019_00421019_00421019", -- Loc 3AC, 3A8, 3A4, 3A0
X"00421019_00421019_00421019_00421019", -- Loc 3BC, 3B8, 3B4, 3B0
-- the last 16 instructions are looping ump instructions
X"080000F3_080000F2_080000F1_080000F0", -- Loc 3CC, 3C8, 3C4, 3C0
X"080000F7_080000F6_080000F5_080000F4", -- Loc 3DC, 3D8, 3D4, 3D0
X"080000FB_080000FA_080000F9_080000F8", -- Loc 3EC, 3E8, 3E4, 3E0
X"080000FF_080000FE_080000FD_080000FC" -- Loc 3FC, 3F8, 3F4, 3F0
) ;
-- the last 16 instructions are looping jump instructions
-- of the type: loop: j loop
-- This is to make sure that neither instruction fetching
-- nor instruction execution proceeds beyond the end of this memory.
-- Loc 3C0 -- 080000F0 => J 240
-- Loc 3C4 -- 080000F1 => J 241
-- Loc 3C8 -- 080000F2 => J 242
-- Loc 3CC -- 080000F3 => J 243
--
-- Loc 3D0 -- 080000F4 => J 244
-- Loc 3D4 -- 080000F5 => J 245
-- Loc 3D8 -- 080000F6 => J 246
-- Loc 3DC -- 080000F7 => J 247
--
-- Loc 3E0 -- 080000F8 => J 248
-- Loc 3E4 -- 080000F9 => J 249
-- Loc 3E8 -- 080000FA => J 250
-- Loc 3EC -- 080000FB => J 251
--
-- Loc 3F0 -- 080000FC => J 252
-- Loc 3F4 -- 080000FD => J 253
-- Loc 3F8 -- 080000FE => J 254
-- Loc 3FC -- 080000FF => J 255
end package instr_stream_pkg;
-- -- No need for s package body here
-- package body instr_stream_pkg is
--
-- end package body instr_stream_pkg;
|
-- file: i_fetch_test_stream_instr_stream_pkg.vhd (version: i_fetch_test_stream_instr_stream_pkg_non_aligned_branches.vhd)
-- Written by Gandhi Puvvada
-- date of last rivision: 7/23/2008
--
-- A package file to define the instruction stream to be placed in the instr_cache.
-- This package, "instr_stream_pkg", is refered in a use clause in the inst_cache_sprom module.
-- We will use several files similar to this containining different instruction streams.
-- The package name will remain the same, namely instr_stream_pkg.
-- Only the file name changes from, say i_fetch_test_stream_instr_stream_pkg.vhd
-- to say mult_test_stream_instr_stream_pkg.vhd.
-- Depending on which instr_stream_pkg file was analysed/compiled most recently,
-- that stream will be used for simulation/synthesis.
----------------------------------------------------------
library std, ieee;
use ieee.std_logic_1164.all;
package instr_stream_pkg is
constant DATA_WIDTH_CONSTANT : integer := 128; -- data width of of our cache
constant ADDR_WIDTH_CONSTANT : integer := 6; -- address width of our cache
-- type declarations
type mem_type is array (0 to (2**ADDR_WIDTH_CONSTANT)-1) of std_logic_vector((DATA_WIDTH_CONSTANT-1) downto 0);
---------------------------------------------------
---------------------------------------------------
-- All instructions are mul $2 $2 $2
---------------------------------------------------
---------------------------------------------------
signal mem : mem_type :=
(X"00421019_00421019_00421019_00421019", -- Loc 0C, 08, 04, 00
X"00421019_00421019_00421019_00421019", -- Loc 1C, 18, 14, 10
X"00421019_00421019_00421019_00421019", -- Loc 2C, 28, 24, 20
X"00421019_00421019_00421019_00421019", -- Loc 3C, 38, 34, 30
X"00421019_00421019_00421019_00421019", -- Loc 4C, 48, 44, 40
X"00421019_00421019_00421019_00421019", -- Loc 5C, 58, 54, 50
X"00421019_00421019_00421019_00421019", -- Loc 6C, 68, 64, 60
X"00421019_00421019_00421019_00421019", -- Loc 7C, 78, 74, 70
X"00421019_00421019_00421019_00421019", -- Loc 8C, 88, 84, 80
X"00421019_00421019_00421019_00421019", -- Loc 9C, 98, 94, 90
X"00421019_00421019_00421019_00421019", -- Loc AC, A8, A4, A0
X"00421019_00421019_00421019_00421019", -- Loc BC, B8, B4, B0
X"00421019_00421019_00421019_00421019", -- Loc CC, C8, C4, C0
X"00421019_00421019_00421019_00421019", -- Loc DC, D8, D4, D0
X"00421019_00421019_00421019_00421019", -- Loc EC, E8, E4, E0
X"00421019_00421019_00421019_00421019", -- Loc FC, F8, F4, F0
X"00421019_00421019_00421019_00421019", -- Loc 10C, 108, 104, 100
X"00421019_00421019_00421019_00421019", -- Loc 11C, 118, 114, 110
X"00421019_00421019_00421019_00421019", -- Loc 12C, 128, 124, 120
X"00421019_00421019_00421019_00421019", -- Loc 13C, 138, 134, 130
X"00421019_00421019_00421019_00421019", -- Loc 14C, 148, 144, 140
X"00421019_00421019_00421019_00421019", -- Loc 15C, 158, 154, 150
X"00421019_00421019_00421019_00421019", -- Loc 16C, 168, 164, 160
X"00421019_00421019_00421019_00421019", -- Loc 17C, 178, 174, 170
X"00421019_00421019_00421019_00421019", -- Loc 18C, 188, 184, 180
X"00421019_00421019_00421019_00421019", -- Loc 19C, 198, 194, 190
X"00421019_00421019_00421019_00421019", -- Loc 1AC, 1A8, 1A4, 1A0
X"00421019_00421019_00421019_00421019", -- Loc 1BC, 1B8, 1B4, 1B0
X"00421019_00421019_00421019_00421019", -- Loc 1CC, 1C8, 1C4, 1C0
X"00421019_00421019_00421019_00421019", -- Loc 1DC, 1D8, 1D4, 1D0
X"00421019_00421019_00421019_00421019", -- Loc 1EC, 1E8, 1E4, 1E0
X"00421019_00421019_00421019_00421019", -- Loc 1FC, 1F8, 1F4, 1F0
X"00421019_00421019_00421019_00421019", -- Loc 20C, 208, 204, 200
X"00421019_00421019_00421019_00421019", -- Loc 21C, 218, 214, 221
X"00421019_00421019_00421019_00421019", -- Loc 22C, 228, 224, 220
X"00421019_00421019_00421019_00421019", -- Loc 23C, 238, 234, 230
X"00421019_00421019_00421019_00421019", -- Loc 24C, 248, 244, 240
X"00421019_00421019_00421019_00421019", -- Loc 25C, 258, 254, 250
X"00421019_00421019_00421019_00421019", -- Loc 26C, 268, 264, 260
X"00421019_00421019_00421019_00421019", -- Loc 27C, 278, 274, 270
X"00421019_00421019_00421019_00421019", -- Loc 28C, 288, 284, 280
X"00421019_00421019_00421019_00421019", -- Loc 29C, 298, 294, 290
X"00421019_00421019_00421019_00421019", -- Loc 2AC, 2A8, 2A4, 2A0
X"00421019_00421019_00421019_00421019", -- Loc 2BC, 2B8, 2B4, 2B0
X"00421019_00421019_00421019_00421019", -- Loc 2CC, 2C8, 2C4, 2C0
X"00421019_00421019_00421019_00421019", -- Loc 2DC, 2D8, 2D4, 2D0
X"00421019_00421019_00421019_00421019", -- Loc 2EC, 2E8, 2E4, 2E0
X"00421019_00421019_00421019_00421019", -- Loc 2FC, 2F8, 2F4, 2F0
X"00421019_00421019_00421019_00421019", -- Loc 30C, 308, 304, 300
X"00421019_00421019_00421019_00421019", -- Loc 31C, 318, 314, 331
X"00421019_00421019_00421019_00421019", -- Loc 32C, 328, 324, 320
X"00421019_00421019_00421019_00421019", -- Loc 33C, 338, 334, 330
X"00421019_00421019_00421019_00421019", -- Loc 34C, 348, 344, 340
X"00421019_00421019_00421019_00421019", -- Loc 35C, 358, 354, 350
X"00421019_00421019_00421019_00421019", -- Loc 36C, 368, 364, 360
X"00421019_00421019_00421019_00421019", -- Loc 37C, 378, 374, 370
X"00421019_00421019_00421019_00421019", -- Loc 38C, 388, 384, 380
X"00421019_00421019_00421019_00421019", -- Loc 39C, 398, 394, 390
X"00421019_00421019_00421019_00421019", -- Loc 3AC, 3A8, 3A4, 3A0
X"00421019_00421019_00421019_00421019", -- Loc 3BC, 3B8, 3B4, 3B0
-- the last 16 instructions are looping ump instructions
X"080000F3_080000F2_080000F1_080000F0", -- Loc 3CC, 3C8, 3C4, 3C0
X"080000F7_080000F6_080000F5_080000F4", -- Loc 3DC, 3D8, 3D4, 3D0
X"080000FB_080000FA_080000F9_080000F8", -- Loc 3EC, 3E8, 3E4, 3E0
X"080000FF_080000FE_080000FD_080000FC" -- Loc 3FC, 3F8, 3F4, 3F0
) ;
-- the last 16 instructions are looping jump instructions
-- of the type: loop: j loop
-- This is to make sure that neither instruction fetching
-- nor instruction execution proceeds beyond the end of this memory.
-- Loc 3C0 -- 080000F0 => J 240
-- Loc 3C4 -- 080000F1 => J 241
-- Loc 3C8 -- 080000F2 => J 242
-- Loc 3CC -- 080000F3 => J 243
--
-- Loc 3D0 -- 080000F4 => J 244
-- Loc 3D4 -- 080000F5 => J 245
-- Loc 3D8 -- 080000F6 => J 246
-- Loc 3DC -- 080000F7 => J 247
--
-- Loc 3E0 -- 080000F8 => J 248
-- Loc 3E4 -- 080000F9 => J 249
-- Loc 3E8 -- 080000FA => J 250
-- Loc 3EC -- 080000FB => J 251
--
-- Loc 3F0 -- 080000FC => J 252
-- Loc 3F4 -- 080000FD => J 253
-- Loc 3F8 -- 080000FE => J 254
-- Loc 3FC -- 080000FF => J 255
end package instr_stream_pkg;
-- -- No need for s package body here
-- package body instr_stream_pkg is
--
-- end package body instr_stream_pkg;
|
--Part of Mano Basic Computer
--Behzad Mokhtari; [email protected]
--Sahand University of Technology; sut.ac.ir
--Licensed under GPLv3
--FlipFlopJK
Library IEEE; use IEEE.std_logic_1164.ALL, IEEE.numeric_std.all;
Library manoBasic; use manoBasic.defines.all, manoBasic.devices.all;
entity flipflopJK is
port(
J : in std_logic;
K : in std_logic;
CLK : in std_logic;
CLR : in std_logic;
Q : buffer std_logic;
nQ : buffer std_logic
);
end flipflopJK;
architecture Structure of flipflopJK is
signal d: std_logic;
begin
d <= (J and nQ) or (Q and (not K));
flpD0: flipflopD port map(D=>d, CLR=>CLR, CLK=>CLK, Q=>Q, nQ=>nQ);
end Structure; |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Synthesizable Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: ben_mem_synth.vhd
--
-- Description:
-- Synthesizable Testbench
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY STD;
USE STD.TEXTIO.ALL;
--LIBRARY unisim;
--USE unisim.vcomponents.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY ben_mem_synth IS
GENERIC (
C_ROM_SYNTH : INTEGER := 1
);
PORT(
CLK_IN : IN STD_LOGIC;
RESET_IN : IN STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(8 DOWNTO 0) := (OTHERS => '0') --ERROR STATUS OUT OF FPGA
);
END ENTITY;
ARCHITECTURE ben_mem_synth_ARCH OF ben_mem_synth IS
COMPONENT ben_mem_exdes
PORT (
--Inputs - Port A
ADDRA : IN STD_LOGIC_VECTOR(14 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA: STD_LOGIC := '0';
SIGNAL RSTA: STD_LOGIC := '0';
SIGNAL ADDRA: STD_LOGIC_VECTOR(14 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRA_R: STD_LOGIC_VECTOR(14 DOWNTO 0) := (OTHERS => '0');
SIGNAL DOUTA: STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL CHECKER_EN : STD_LOGIC:='0';
SIGNAL CHECKER_EN_R : STD_LOGIC:='0';
SIGNAL STIMULUS_FLOW : STD_LOGIC_VECTOR(22 DOWNTO 0) := (OTHERS =>'0');
SIGNAL clk_in_i: STD_LOGIC;
SIGNAL RESET_SYNC_R1 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R2 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R3 : STD_LOGIC:='1';
SIGNAL ITER_R0 : STD_LOGIC := '0';
SIGNAL ITER_R1 : STD_LOGIC := '0';
SIGNAL ITER_R2 : STD_LOGIC := '0';
SIGNAL ISSUE_FLAG : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL ISSUE_FLAG_STATUS : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
BEGIN
-- clk_buf: bufg
-- PORT map(
-- i => CLK_IN,
-- o => clk_in_i
-- );
clk_in_i <= CLK_IN;
CLKA <= clk_in_i;
RSTA <= RESET_SYNC_R3 AFTER 50 ns;
PROCESS(clk_in_i)
BEGIN
IF(RISING_EDGE(clk_in_i)) THEN
RESET_SYNC_R1 <= RESET_IN;
RESET_SYNC_R2 <= RESET_SYNC_R1;
RESET_SYNC_R3 <= RESET_SYNC_R2;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ISSUE_FLAG_STATUS<= (OTHERS => '0');
ELSE
ISSUE_FLAG_STATUS <= ISSUE_FLAG_STATUS OR ISSUE_FLAG;
END IF;
END IF;
END PROCESS;
STATUS(7 DOWNTO 0) <= ISSUE_FLAG_STATUS;
BMG_STIM_GEN_INST:ENTITY work.BMG_STIM_GEN
GENERIC MAP( C_ROM_SYNTH => C_ROM_SYNTH
)
PORT MAP(
CLK => clk_in_i,
RST => RSTA,
ADDRA => ADDRA,
DATA_IN => DOUTA,
STATUS => ISSUE_FLAG(0)
);
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STATUS(8) <= '0';
iter_r2 <= '0';
iter_r1 <= '0';
iter_r0 <= '0';
ELSE
STATUS(8) <= iter_r2;
iter_r2 <= iter_r1;
iter_r1 <= iter_r0;
iter_r0 <= STIMULUS_FLOW(8);
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STIMULUS_FLOW <= (OTHERS => '0');
ELSIF(ADDRA(0)='1') THEN
STIMULUS_FLOW <= STIMULUS_FLOW+1;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ELSE
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ADDRA_R <= (OTHERS=> '0') AFTER 50 ns;
ELSE
ADDRA_R <= ADDRA AFTER 50 ns;
END IF;
END IF;
END PROCESS;
BMG_PORT: ben_mem_exdes PORT MAP (
--Port A
ADDRA => ADDRA_R,
DOUTA => DOUTA,
CLKA => CLKA
);
END ARCHITECTURE;
|
-------------------------------------------------------------------------------
-- Title : BMP Package
-- Project :
-------------------------------------------------------------------------------
-- File : sim_bmppack.vhd
-- Author : Kest
-- Company :
-- Created : 2006-12-05
-- Last update: 2007-10-29
-- Platform : ModelSIM 6.0
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2006 by Kest
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2006-12-05 1.0 kest Created
-------------------------------------------------------------------------------
-- http://de.wikipedia.org/wiki/Windows_Bitmap
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
-------------------------------------------------------------------------------
package sim_bmppack is
-- maximale Größe des Speichers
constant cMAX_X : integer := 1300;
constant cMAX_Y : integer := 1300;
constant cBytesPerPixel : integer := 3;
constant cMaxMemSize : integer := cMAX_X * cMAX_Y * cBytesPerPixel;
subtype file_element is std_logic_vector(7 downto 0);
type mem_array is array(cMaxMemSize downto 0) of file_element;
type header_array is array(53 downto 0) of file_element;
procedure ReadFile(FileName : in string);
procedure WriteFile(FileName : in string);
procedure ReadByteFromMemory (adr : in integer; variable data : out std_logic_vector(7 downto 0));
procedure WriteByteToMemory (adr : in integer; variable data : in std_logic_vector(7 downto 0));
function GetWidth(header : in header_array) return integer;
procedure GetWidth(signal width : out integer);
function GetHeigth(header : in header_array) return integer;
procedure GetHeigth(signal height : out integer);
procedure GetPixel (x : in integer; y : in integer; signal data : out std_logic_vector(23 downto 0));
procedure SetPixel (x : in integer; y : in integer; signal data : in std_logic_vector(23 downto 0));
procedure DrawCross (x : in integer; y : in integer; signal data : in std_logic_vector(23 downto 0));
end package sim_bmppack;
-------------------------------------------------------------------------------
-- Package body
-------------------------------------------------------------------------------
package body sim_bmppack is
-----------------------------------------------------------------------------
--
-----------------------------------------------------------------------------
shared variable memory_in : mem_array;
shared variable memory_out : mem_array;
shared variable header : header_array;
shared variable pImageSize : integer;
shared variable pImageWidth : integer;
shared variable pImageHeight : integer;
-----------------------------------------------------------------------------
-- This code reads a raw binary file one byte at a time.
-----------------------------------------------------------------------------
procedure ReadFile(FileName : in string) is
variable next_vector : bit_vector (0 downto 0);
variable actual_len : natural;
variable index : integer := 0;
type bit_vector_file is file of bit_vector;
file read_file : bit_vector_file open read_mode is FileName;
begin
report "Read File";
report FileName;
index := 0;
---------------------------------------------------------------------------
-- Header einlesen
---------------------------------------------------------------------------
report "Read Header";
for i in 0 to 53 loop
read(read_file, next_vector, actual_len);
if actual_len > next_vector'length then
report "vector too long";
else
header(index) := conv_std_logic_vector(bit'pos(next_vector(0)), 8);
index := index + 1;
end if;
end loop;
pImageWidth := GetWidth(header);
pImageHeight := GetHeigth(header);
pImageSize := pImageWidth * pImageHeight;
report "Read Image";
index := 0;
while not endfile(read_file) loop
read(read_file, next_vector, actual_len);
if actual_len > next_vector'length then
report "vector too long";
else
memory_in(index) := conv_std_logic_vector(bit'pos(next_vector(0)), 8);
memory_out(index) := x"45";
index := index + 1;
end if;
end loop;
report "Okay";
end ReadFile;
-----------------------------------------------------------------------------
-- Read one byte from Memory
-----------------------------------------------------------------------------
procedure ReadByteFromMemory (adr : in integer; variable data : out std_logic_vector(7 downto 0)) is
begin
data := memory_in(adr);
end ReadByteFromMemory;
-----------------------------------------------------------------------------
-- Pixel Operationen
-----------------------------------------------------------------------------
procedure GetPixel (x : in integer; y : in integer; signal data : out std_logic_vector(23 downto 0)) is
begin
if x >= 0 and x < cMAX_X and y >= 0 and y < cMAX_Y then
data(23 downto 16) <= memory_in(x*3 + 3*y*GetWidth(header));
data(15 downto 8) <= memory_in(x*3+1 + 3*y*GetWidth(header));
data(7 downto 0) <= memory_in(x*3+2 + 3*y*GetWidth(header));
end if;
end GetPixel;
procedure SetPixel (x : in integer; y : in integer; signal data : in std_logic_vector(23 downto 0)) is
begin
if x >= 0 and x < cMAX_X and y >= 0 and y < cMAX_Y then
memory_out(x*3+y*(GetWidth(header)*3)) := data(23 downto 16);
memory_out(x*3+1+y*(GetWidth(header)*3)) := data(15 downto 8);
memory_out(x*3+2+y*(GetWidth(header)*3)) := data(7 downto 0);
end if;
end SetPixel;
procedure DrawCross (x : in integer; y : in integer; signal data : in std_logic_vector(23 downto 0)) is
constant CrossSize : integer := 5;
begin
for n in -CrossSize to CrossSize loop
SetPixel(x+n,y,data);
SetPixel(x,y+n,data);
end loop;
end DrawCross;
-----------------------------------------------------------------------------
-- Write one byte to Memory
-----------------------------------------------------------------------------
procedure WriteByteToMemory (adr : in integer; variable data : in std_logic_vector(7 downto 0)) is
begin
memory_out(adr) := data;
end WriteByteToMemory;
-- Get Width of Image
function GetWidth(header : in header_array) return integer is
begin
return conv_integer(header(21) & header(20) & header(19) & header(18));
end function GetWidth;
procedure GetWidth(signal width : out integer) is
begin
width <= pImageWidth;
end GetWidth;
-- Get Height of Image
function GetHeigth(header : in header_array) return integer is
begin
return conv_integer(header(25) & header(24) & header(23) & header(22));
end function GetHeigth;
procedure GetHeigth(signal height : out integer) is
begin
height <= pImageHeight;
end GetHeigth;
-----------------------------------------------------------------------------
-- This code write a raw binary file one byte at a time.
-----------------------------------------------------------------------------
procedure WriteFile(FileName : in string) is
variable next_vector : character;
variable index : integer := 0;
type char_file is file of character;
file write_file : char_file open write_mode is FileName;
begin
report "Write File...";
report FileName;
report "write Header";
index := 0;
for i in 0 to 53 loop
next_vector := character'val(conv_integer(header(index)));
write(write_file, next_vector);
index := index + 1;
end loop;
report "write Image";
index := 0;
while index < pImageSize*3 loop
next_vector := character'val(conv_integer(memory_out(index)));
write(write_file, next_vector);
index := index + 1;
end loop;
report "Okay";
end WriteFile;
end sim_bmppack;
|
-- includes
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY bouton_diode IS
PORT (
-- le bouton
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
B : IN STD_LOGIC;
D : OUT STD_LOGIC
);
END bouton_diode ;
ARCHITECTURE arch OF bouton_diode IS
TYPE STATE_TYPE IS (debut, a0, a1, e0);
SIGNAL state : STATE_TYPE ;
BEGIN
PROCESS(clk,rst)
BEGIN
IF rst='1' THEN
state <= debut ;
ELSIF clk'EVENT AND clk='1' THEN
CASE state IS
WHEN debut =>
IF B='1' THEN
state <= a0 ;
END IF;
WHEN a0 =>
IF B='0' THEN
state <= a1 ;
END IF;
WHEN a1 =>
IF B='1' THEN
state <= e0 ;
END IF;
WHEN e0 =>
IF B='0' THEN
state <= debut ;
END IF;
END CASE ;
END IF;
END PROCESS ;
WITH state SELECT D <=
'0' WHEN debut,
'1' WHEN a0,
'1' WHEN a1,
'0' WHEN OTHERS
;
END arch;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity testcase is
generic ( DATA_WIDTH : natural := 32 );
port (
ce : in std_logic;
clk : in std_logic
);
end entity testcase;
architecture behaviour of testcase is
signal reg_tmode : unsigned(1 downto 0) := "00";
begin
end behaviour;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity testcase is
generic ( DATA_WIDTH : natural := 32 );
port (
ce : in std_logic;
clk : in std_logic
);
end entity testcase;
architecture behaviour of testcase is
signal reg_tmode : unsigned(1 downto 0) := "00";
begin
end behaviour;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: greth_rx
-- File: greth_rx.vhd
-- Author: Marko Isomaki
-- Description: Ethernet receiver
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
library eth;
use eth.grethpkg.all;
entity greth_rx is
generic(
nsync : integer range 1 to 2 := 2;
rmii : integer range 0 to 1 := 0);
port(
rst : in std_ulogic;
clk : in std_ulogic;
rxi : in host_rx_type;
rxo : out rx_host_type
);
end entity;
architecture rtl of greth_rx is
constant maxsize : integer := 1518;
constant minsize : integer := 64;
--receiver types
type rx_state_type is (idle, wait_sfd, data1, data2, errorst, report_status,
wait_report, check_crc, discard_packet);
type rx_reg_type is record
er : std_ulogic;
en : std_ulogic;
rxd : std_logic_vector(3 downto 0);
rxdp : std_logic_vector(3 downto 0);
crc : std_logic_vector(31 downto 0);
sync_start : std_ulogic;
gotframe : std_ulogic;
start : std_ulogic;
write : std_ulogic;
done : std_ulogic;
odd_nibble : std_ulogic;
lentype : std_logic_vector(15 downto 0);
ltfound : std_ulogic;
byte_count : std_logic_vector(10 downto 0);
data : std_logic_vector(31 downto 0);
dataout : std_logic_vector(31 downto 0);
rx_state : rx_state_type;
status : std_logic_vector(3 downto 0);
write_ack : std_logic_vector(nsync-1 downto 0);
done_ack : std_logic_vector(nsync downto 0);
rxen : std_logic_vector(1 downto 0);
got4b : std_ulogic;
--rmii
enold : std_ulogic;
act : std_ulogic;
dv : std_ulogic;
cnt : std_logic_vector(3 downto 0);
rxd2 : std_logic_vector(1 downto 0);
speed : std_logic_vector(1 downto 0);
zero : std_ulogic;
end record;
--receiver signals
signal r, rin : rx_reg_type;
signal rxrst : std_ulogic;
signal vcc : std_ulogic;
attribute sync_set_reset : string;
attribute sync_set_reset of rxrst : signal is "true";
begin
vcc <= '1';
rx_rst : eth_rstgen
port map(rst, clk, vcc, rxrst, open);
rx : process(rxrst, r, rxi) is
variable v : rx_reg_type;
variable index : integer range 0 to 3;
variable crc_en : std_ulogic;
variable write_req : std_ulogic;
variable write_ack : std_ulogic;
variable done_ack : std_ulogic;
variable er : std_ulogic;
variable dv : std_ulogic;
variable act : std_ulogic;
variable rxd : std_logic_vector(3 downto 0);
begin
v := r; v.rxd := rxi.rxd(3 downto 0);
if rmii = 0 then
v.en := rxi.rx_dv;
else
v.en := rxi.rx_crs;
end if;
v.er := rxi.rx_er; write_req := '0'; crc_en := '0';
index := conv_integer(r.byte_count(1 downto 0));
--synchronization
v.rxen(1) := r.rxen(0); v.rxen(0) := rxi.enable;
v.write_ack(0) := rxi.writeack;
v.done_ack(0) := rxi.doneack;
if nsync = 2 then
v.write_ack(1) := r.write_ack(0);
v.done_ack(1) := r.done_ack(0);
end if;
write_ack := not (r.write xor r.write_ack(nsync-1));
done_ack := not (r.done xor r.done_ack(nsync-1));
--rmii/mii
if rmii = 0 then
er := r.er; dv := r.en; act := r.en; rxd := r.rxd;
else
--sync
v.speed(1) := r.speed(0); v.speed(0) := rxi.speed;
rxd := r.rxd(1 downto 0) & r.rxd2;
if r.cnt = "0000" then
v.cnt := "1001";
else
v.cnt := r.cnt - 1;
end if;
if v.cnt = "0000" then
v.zero := '1';
else
v.zero := '0';
end if;
act := r.act; er := '0';
if r.speed(1) = '0' then
if r.zero = '1' then
v.enold := r.en;
dv := r.en and r.dv;
v.dv := r.act and not r.dv;
if r.dv = '0' then
v.rxd2 := r.rxd(1 downto 0);
end if;
if (r.enold or r.en) = '0' then
v.act := '0';
end if;
else
dv := '0';
end if;
else
v.enold := r.en;
dv := r.en and r.dv;
v.dv := r.act and not r.dv;
v.rxd2 := r.rxd(1 downto 0);
if (r.enold or r.en) = '0' then
v.act := '0';
end if;
end if;
end if;
if (r.en and not r.act) = '1' then
if (rxd = "0101") and (r.speed(1) or
(not r.speed(1) and r.zero)) = '1' then
v.act := '1'; v.dv := '0';
end if;
end if;
if (dv = '1') then
v.rxdp := rxd;
end if;
--fsm
case r.rx_state is
when idle =>
v.gotframe := '0'; v.status := (others => '0'); v.got4b := '0';
v.byte_count := (others => '0'); v.odd_nibble := '0';
v.ltfound := '0';
if (dv and r.rxen(1)) = '1' then
v.rx_state := wait_sfd;
elsif dv = '1' then v.rx_state := discard_packet; end if;
when discard_packet =>
if act = '0' then v.rx_state := idle; end if;
when wait_sfd =>
if act = '0' then v.rx_state := idle;
elsif (rxd = "1101") and (dv = '1') and (r.rxdp = "0101") then
v.rx_state := data1; v.sync_start := not r.sync_start;
end if;
v.start := '0'; v.crc := (others => '1');
if er = '1' then v.status(2) := '1'; end if;
when data1 =>
if (act and dv) = '1' then
crc_en := '1';
v.odd_nibble := not r.odd_nibble; v.rx_state := data2;
case index is
when 0 => v.data(27 downto 24) := rxd;
when 1 => v.data(19 downto 16) := rxd;
when 2 => v.data(11 downto 8) := rxd;
when 3 => v.data(3 downto 0) := rxd;
end case;
elsif act = '0' then
v.rx_state := check_crc;
end if;
if (r.byte_count(1 downto 0) = "00" and (r.start and act and dv) = '1') then
write_req := '1';
end if;
if er = '1' then v.status(2) := '1'; end if;
if conv_integer(r.byte_count) > maxsize then
v.rx_state := errorst; v.status(1) := '1';
v.byte_count := r.byte_count - 4;
end if;
v.got4b := v.byte_count(2) or r.got4b;
when data2 =>
if (act and dv) = '1' then
crc_en := '1';
v.odd_nibble := not r.odd_nibble; v.rx_state := data1;
v.byte_count := r.byte_count + 1; v.start := '1';
case index is
when 0 => v.data(31 downto 28) := rxd;
when 1 => v.data(23 downto 20) := rxd;
when 2 => v.data(15 downto 12) := rxd;
when 3 => v.data(7 downto 4) := rxd;
end case;
elsif act = '0' then
v.rx_state := check_crc;
end if;
if er = '1' then v.status(2) := '1'; end if;
v.got4b := v.byte_count(2) or r.got4b;
when check_crc =>
if r.crc /= X"C704DD7B" then
if r.odd_nibble = '1' then v.status(0) := '1';
else v.status(2) := '1'; end if;
end if;
if write_ack = '1' then
if r.got4b = '1' then
v.byte_count := r.byte_count - 4;
else
v.byte_count := (others => '0');
end if;
v.rx_state := report_status;
if conv_integer(r.byte_count) < minsize then
v.rx_state := wait_report; v.done := not r.done;
end if;
end if;
when errorst =>
if act = '0' then
v.rx_state := wait_report; v.done := not r.done;
v.gotframe := '1';
end if;
when report_status =>
v.done := not r.done; v.rx_state := wait_report;
v.gotframe := '1';
when wait_report =>
if done_ack = '1' then
if act = '1' then
v.rx_state := discard_packet;
else
v.rx_state := idle;
end if;
end if;
when others => null;
end case;
--write to fifo
if write_req = '1' then
if (r.status(3) or not write_ack) = '1' then
v.status(3) := '1';
else
v.dataout := r.data; v.write := not r.write;
end if;
if (r.byte_count(4 downto 2) = "100") and (r.ltfound = '0') then
v.lentype := r.data(31 downto 16) + 14; v.ltfound := '1';
end if;
end if;
if rxi.writeack = '1' then
if rxi.writeok = '0' then v.status(3) := '1'; end if;
end if;
--crc generation
if crc_en = '1' then
v.crc := calccrc(rxd, r.crc);
end if;
if rxrst = '0' then
v.rx_state := idle; v.write := '0'; v.done := '0'; v.sync_start := '0';
v.done_ack := (others => '0');
v.gotframe := '0'; v.write_ack := (others => '0');
if rmii = 1 then
v.dv := '0'; v.cnt := (others => '0'); v.zero := '0';
end if;
end if;
rin <= v;
rxo.dataout <= r.dataout;
rxo.start <= r.sync_start;
rxo.done <= r.done;
rxo.write <= r.write;
rxo.status <= r.status;
rxo.gotframe <= r.gotframe;
rxo.byte_count <= r.byte_count;
rxo.lentype <= r.lentype;
end process;
rxregs : process(clk) is
begin
if rising_edge(clk) then r <= rin; end if;
end process;
end architecture;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: greth_rx
-- File: greth_rx.vhd
-- Author: Marko Isomaki
-- Description: Ethernet receiver
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
library eth;
use eth.grethpkg.all;
entity greth_rx is
generic(
nsync : integer range 1 to 2 := 2;
rmii : integer range 0 to 1 := 0);
port(
rst : in std_ulogic;
clk : in std_ulogic;
rxi : in host_rx_type;
rxo : out rx_host_type
);
end entity;
architecture rtl of greth_rx is
constant maxsize : integer := 1518;
constant minsize : integer := 64;
--receiver types
type rx_state_type is (idle, wait_sfd, data1, data2, errorst, report_status,
wait_report, check_crc, discard_packet);
type rx_reg_type is record
er : std_ulogic;
en : std_ulogic;
rxd : std_logic_vector(3 downto 0);
rxdp : std_logic_vector(3 downto 0);
crc : std_logic_vector(31 downto 0);
sync_start : std_ulogic;
gotframe : std_ulogic;
start : std_ulogic;
write : std_ulogic;
done : std_ulogic;
odd_nibble : std_ulogic;
lentype : std_logic_vector(15 downto 0);
ltfound : std_ulogic;
byte_count : std_logic_vector(10 downto 0);
data : std_logic_vector(31 downto 0);
dataout : std_logic_vector(31 downto 0);
rx_state : rx_state_type;
status : std_logic_vector(3 downto 0);
write_ack : std_logic_vector(nsync-1 downto 0);
done_ack : std_logic_vector(nsync downto 0);
rxen : std_logic_vector(1 downto 0);
got4b : std_ulogic;
--rmii
enold : std_ulogic;
act : std_ulogic;
dv : std_ulogic;
cnt : std_logic_vector(3 downto 0);
rxd2 : std_logic_vector(1 downto 0);
speed : std_logic_vector(1 downto 0);
zero : std_ulogic;
end record;
--receiver signals
signal r, rin : rx_reg_type;
signal rxrst : std_ulogic;
signal vcc : std_ulogic;
attribute sync_set_reset : string;
attribute sync_set_reset of rxrst : signal is "true";
begin
vcc <= '1';
rx_rst : eth_rstgen
port map(rst, clk, vcc, rxrst, open);
rx : process(rxrst, r, rxi) is
variable v : rx_reg_type;
variable index : integer range 0 to 3;
variable crc_en : std_ulogic;
variable write_req : std_ulogic;
variable write_ack : std_ulogic;
variable done_ack : std_ulogic;
variable er : std_ulogic;
variable dv : std_ulogic;
variable act : std_ulogic;
variable rxd : std_logic_vector(3 downto 0);
begin
v := r; v.rxd := rxi.rxd(3 downto 0);
if rmii = 0 then
v.en := rxi.rx_dv;
else
v.en := rxi.rx_crs;
end if;
v.er := rxi.rx_er; write_req := '0'; crc_en := '0';
index := conv_integer(r.byte_count(1 downto 0));
--synchronization
v.rxen(1) := r.rxen(0); v.rxen(0) := rxi.enable;
v.write_ack(0) := rxi.writeack;
v.done_ack(0) := rxi.doneack;
if nsync = 2 then
v.write_ack(1) := r.write_ack(0);
v.done_ack(1) := r.done_ack(0);
end if;
write_ack := not (r.write xor r.write_ack(nsync-1));
done_ack := not (r.done xor r.done_ack(nsync-1));
--rmii/mii
if rmii = 0 then
er := r.er; dv := r.en; act := r.en; rxd := r.rxd;
else
--sync
v.speed(1) := r.speed(0); v.speed(0) := rxi.speed;
rxd := r.rxd(1 downto 0) & r.rxd2;
if r.cnt = "0000" then
v.cnt := "1001";
else
v.cnt := r.cnt - 1;
end if;
if v.cnt = "0000" then
v.zero := '1';
else
v.zero := '0';
end if;
act := r.act; er := '0';
if r.speed(1) = '0' then
if r.zero = '1' then
v.enold := r.en;
dv := r.en and r.dv;
v.dv := r.act and not r.dv;
if r.dv = '0' then
v.rxd2 := r.rxd(1 downto 0);
end if;
if (r.enold or r.en) = '0' then
v.act := '0';
end if;
else
dv := '0';
end if;
else
v.enold := r.en;
dv := r.en and r.dv;
v.dv := r.act and not r.dv;
v.rxd2 := r.rxd(1 downto 0);
if (r.enold or r.en) = '0' then
v.act := '0';
end if;
end if;
end if;
if (r.en and not r.act) = '1' then
if (rxd = "0101") and (r.speed(1) or
(not r.speed(1) and r.zero)) = '1' then
v.act := '1'; v.dv := '0';
end if;
end if;
if (dv = '1') then
v.rxdp := rxd;
end if;
--fsm
case r.rx_state is
when idle =>
v.gotframe := '0'; v.status := (others => '0'); v.got4b := '0';
v.byte_count := (others => '0'); v.odd_nibble := '0';
v.ltfound := '0';
if (dv and r.rxen(1)) = '1' then
v.rx_state := wait_sfd;
elsif dv = '1' then v.rx_state := discard_packet; end if;
when discard_packet =>
if act = '0' then v.rx_state := idle; end if;
when wait_sfd =>
if act = '0' then v.rx_state := idle;
elsif (rxd = "1101") and (dv = '1') and (r.rxdp = "0101") then
v.rx_state := data1; v.sync_start := not r.sync_start;
end if;
v.start := '0'; v.crc := (others => '1');
if er = '1' then v.status(2) := '1'; end if;
when data1 =>
if (act and dv) = '1' then
crc_en := '1';
v.odd_nibble := not r.odd_nibble; v.rx_state := data2;
case index is
when 0 => v.data(27 downto 24) := rxd;
when 1 => v.data(19 downto 16) := rxd;
when 2 => v.data(11 downto 8) := rxd;
when 3 => v.data(3 downto 0) := rxd;
end case;
elsif act = '0' then
v.rx_state := check_crc;
end if;
if (r.byte_count(1 downto 0) = "00" and (r.start and act and dv) = '1') then
write_req := '1';
end if;
if er = '1' then v.status(2) := '1'; end if;
if conv_integer(r.byte_count) > maxsize then
v.rx_state := errorst; v.status(1) := '1';
v.byte_count := r.byte_count - 4;
end if;
v.got4b := v.byte_count(2) or r.got4b;
when data2 =>
if (act and dv) = '1' then
crc_en := '1';
v.odd_nibble := not r.odd_nibble; v.rx_state := data1;
v.byte_count := r.byte_count + 1; v.start := '1';
case index is
when 0 => v.data(31 downto 28) := rxd;
when 1 => v.data(23 downto 20) := rxd;
when 2 => v.data(15 downto 12) := rxd;
when 3 => v.data(7 downto 4) := rxd;
end case;
elsif act = '0' then
v.rx_state := check_crc;
end if;
if er = '1' then v.status(2) := '1'; end if;
v.got4b := v.byte_count(2) or r.got4b;
when check_crc =>
if r.crc /= X"C704DD7B" then
if r.odd_nibble = '1' then v.status(0) := '1';
else v.status(2) := '1'; end if;
end if;
if write_ack = '1' then
if r.got4b = '1' then
v.byte_count := r.byte_count - 4;
else
v.byte_count := (others => '0');
end if;
v.rx_state := report_status;
if conv_integer(r.byte_count) < minsize then
v.rx_state := wait_report; v.done := not r.done;
end if;
end if;
when errorst =>
if act = '0' then
v.rx_state := wait_report; v.done := not r.done;
v.gotframe := '1';
end if;
when report_status =>
v.done := not r.done; v.rx_state := wait_report;
v.gotframe := '1';
when wait_report =>
if done_ack = '1' then
if act = '1' then
v.rx_state := discard_packet;
else
v.rx_state := idle;
end if;
end if;
when others => null;
end case;
--write to fifo
if write_req = '1' then
if (r.status(3) or not write_ack) = '1' then
v.status(3) := '1';
else
v.dataout := r.data; v.write := not r.write;
end if;
if (r.byte_count(4 downto 2) = "100") and (r.ltfound = '0') then
v.lentype := r.data(31 downto 16) + 14; v.ltfound := '1';
end if;
end if;
if rxi.writeack = '1' then
if rxi.writeok = '0' then v.status(3) := '1'; end if;
end if;
--crc generation
if crc_en = '1' then
v.crc := calccrc(rxd, r.crc);
end if;
if rxrst = '0' then
v.rx_state := idle; v.write := '0'; v.done := '0'; v.sync_start := '0';
v.done_ack := (others => '0');
v.gotframe := '0'; v.write_ack := (others => '0');
if rmii = 1 then
v.dv := '0'; v.cnt := (others => '0'); v.zero := '0';
end if;
end if;
rin <= v;
rxo.dataout <= r.dataout;
rxo.start <= r.sync_start;
rxo.done <= r.done;
rxo.write <= r.write;
rxo.status <= r.status;
rxo.gotframe <= r.gotframe;
rxo.byte_count <= r.byte_count;
rxo.lentype <= r.lentype;
end process;
rxregs : process(clk) is
begin
if rising_edge(clk) then r <= rin; end if;
end process;
end architecture;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Top File for the Example Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
-- Filename: cham_rom_tb.vhd
-- Description:
-- Testbench Top
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.ALL;
ENTITY cham_rom_tb IS
END ENTITY;
ARCHITECTURE cham_rom_tb_ARCH OF cham_rom_tb IS
SIGNAL STATUS : STD_LOGIC_VECTOR(8 DOWNTO 0);
SIGNAL CLK : STD_LOGIC := '1';
SIGNAL RESET : STD_LOGIC;
BEGIN
CLK_GEN: PROCESS BEGIN
CLK <= NOT CLK;
WAIT FOR 100 NS;
CLK <= NOT CLK;
WAIT FOR 100 NS;
END PROCESS;
RST_GEN: PROCESS BEGIN
RESET <= '1';
WAIT FOR 1000 NS;
RESET <= '0';
WAIT;
END PROCESS;
--STOP_SIM: PROCESS BEGIN
-- WAIT FOR 200 US; -- STOP SIMULATION AFTER 1 MS
-- ASSERT FALSE
-- REPORT "END SIMULATION TIME REACHED"
-- SEVERITY FAILURE;
--END PROCESS;
--
PROCESS BEGIN
WAIT UNTIL STATUS(8)='1';
IF( STATUS(7 downto 0)/="0") THEN
ASSERT false
REPORT "Test Completed Successfully"
SEVERITY NOTE;
REPORT "Simulation Failed"
SEVERITY FAILURE;
ELSE
ASSERT false
REPORT "TEST PASS"
SEVERITY NOTE;
REPORT "Test Completed Successfully"
SEVERITY FAILURE;
END IF;
END PROCESS;
cham_rom_synth_inst:ENTITY work.cham_rom_synth
GENERIC MAP (C_ROM_SYNTH => 0)
PORT MAP(
CLK_IN => CLK,
RESET_IN => RESET,
STATUS => STATUS
);
END ARCHITECTURE;
|
library verilog;
use verilog.vl_types.all;
entity generic_m20k is
generic(
operation_mode : string := "single_port";
mixed_port_feed_through_mode: string := "dont_care";
ram_block_type : string := "auto";
logical_ram_name: string := "ram_name";
init_file : string := "init_file.hex";
init_file_layout: string := "none";
ecc_pipeline_stage_enabled: string := "false";
enable_ecc : string := "false";
width_eccstatus : integer := 2;
data_interleave_width_in_bits: integer := 1;
data_interleave_offset_in_bits: integer := 1;
port_a_logical_ram_depth: integer := 0;
port_a_logical_ram_width: integer := 0;
port_a_first_address: integer := 0;
port_a_last_address: integer := 0;
port_a_first_bit_number: integer := 0;
port_a_data_out_clear: string := "none";
port_a_data_out_clock: string := "none";
port_a_data_width: integer := 1;
port_a_address_width: integer := 1;
port_a_byte_enable_mask_width: integer := 1;
port_b_logical_ram_depth: integer := 0;
port_b_logical_ram_width: integer := 0;
port_b_first_address: integer := 0;
port_b_last_address: integer := 0;
port_b_first_bit_number: integer := 0;
port_b_address_clear: string := "none";
port_b_data_out_clear: string := "none";
port_b_data_in_clock: string := "clock1";
port_b_address_clock: string := "clock1";
port_b_write_enable_clock: string := "clock1";
port_b_read_enable_clock: string := "clock1";
port_b_byte_enable_clock: string := "clock1";
port_b_data_out_clock: string := "none";
port_b_data_width: integer := 1;
port_b_address_width: integer := 1;
port_b_byte_enable_mask_width: integer := 1;
port_a_read_during_write_mode: string := "new_data_no_nbe_read";
port_b_read_during_write_mode: string := "new_data_no_nbe_read";
power_up_uninitialized: string := "false";
lpm_type : string := "stratixv_ram_block";
lpm_hint : string := "true";
connectivity_checking: string := "off";
mem_init0 : string := "";
mem_init1 : string := "";
mem_init2 : string := "";
mem_init3 : string := "";
mem_init4 : string := "";
mem_init5 : string := "";
mem_init6 : string := "";
mem_init7 : string := "";
mem_init8 : string := "";
mem_init9 : string := "";
port_a_byte_size: integer := 0;
port_b_byte_size: integer := 0;
clk0_input_clock_enable: string := "none";
clk0_core_clock_enable: string := "none";
clk0_output_clock_enable: string := "none";
clk1_input_clock_enable: string := "none";
clk1_core_clock_enable: string := "none";
clk1_output_clock_enable: string := "none";
bist_ena : string := "false";
port_a_address_clear: string := "none";
port_a_data_in_clock: string := "clock0";
port_a_address_clock: string := "clock0";
port_a_write_enable_clock: string := "clock0";
port_a_byte_enable_clock: string := "clock0";
port_a_read_enable_clock: string := "clock0"
);
port(
portadatain : in vl_logic_vector;
portaaddr : in vl_logic_vector;
portawe : in vl_logic;
portare : in vl_logic;
portbdatain : in vl_logic_vector;
portbaddr : in vl_logic_vector;
portbwe : in vl_logic;
portbre : in vl_logic;
clk0 : in vl_logic;
clk1 : in vl_logic;
ena0 : in vl_logic;
ena1 : in vl_logic;
ena2 : in vl_logic;
ena3 : in vl_logic;
clr0 : in vl_logic;
clr1 : in vl_logic;
nerror : in vl_logic;
portabyteenamasks: in vl_logic_vector;
portbbyteenamasks: in vl_logic_vector;
portaaddrstall : in vl_logic;
portbaddrstall : in vl_logic;
devclrn : in vl_logic;
devpor : in vl_logic;
eccstatus : out vl_logic_vector;
portadataout : out vl_logic_vector;
portbdataout : out vl_logic_vector;
dftout : out vl_logic_vector(8 downto 0)
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of operation_mode : constant is 1;
attribute mti_svvh_generic_type of mixed_port_feed_through_mode : constant is 1;
attribute mti_svvh_generic_type of ram_block_type : constant is 1;
attribute mti_svvh_generic_type of logical_ram_name : constant is 1;
attribute mti_svvh_generic_type of init_file : constant is 1;
attribute mti_svvh_generic_type of init_file_layout : constant is 1;
attribute mti_svvh_generic_type of ecc_pipeline_stage_enabled : constant is 1;
attribute mti_svvh_generic_type of enable_ecc : constant is 1;
attribute mti_svvh_generic_type of width_eccstatus : constant is 1;
attribute mti_svvh_generic_type of data_interleave_width_in_bits : constant is 1;
attribute mti_svvh_generic_type of data_interleave_offset_in_bits : constant is 1;
attribute mti_svvh_generic_type of port_a_logical_ram_depth : constant is 1;
attribute mti_svvh_generic_type of port_a_logical_ram_width : constant is 1;
attribute mti_svvh_generic_type of port_a_first_address : constant is 1;
attribute mti_svvh_generic_type of port_a_last_address : constant is 1;
attribute mti_svvh_generic_type of port_a_first_bit_number : constant is 1;
attribute mti_svvh_generic_type of port_a_data_out_clear : constant is 1;
attribute mti_svvh_generic_type of port_a_data_out_clock : constant is 1;
attribute mti_svvh_generic_type of port_a_data_width : constant is 1;
attribute mti_svvh_generic_type of port_a_address_width : constant is 1;
attribute mti_svvh_generic_type of port_a_byte_enable_mask_width : constant is 1;
attribute mti_svvh_generic_type of port_b_logical_ram_depth : constant is 1;
attribute mti_svvh_generic_type of port_b_logical_ram_width : constant is 1;
attribute mti_svvh_generic_type of port_b_first_address : constant is 1;
attribute mti_svvh_generic_type of port_b_last_address : constant is 1;
attribute mti_svvh_generic_type of port_b_first_bit_number : constant is 1;
attribute mti_svvh_generic_type of port_b_address_clear : constant is 1;
attribute mti_svvh_generic_type of port_b_data_out_clear : constant is 1;
attribute mti_svvh_generic_type of port_b_data_in_clock : constant is 1;
attribute mti_svvh_generic_type of port_b_address_clock : constant is 1;
attribute mti_svvh_generic_type of port_b_write_enable_clock : constant is 1;
attribute mti_svvh_generic_type of port_b_read_enable_clock : constant is 1;
attribute mti_svvh_generic_type of port_b_byte_enable_clock : constant is 1;
attribute mti_svvh_generic_type of port_b_data_out_clock : constant is 1;
attribute mti_svvh_generic_type of port_b_data_width : constant is 1;
attribute mti_svvh_generic_type of port_b_address_width : constant is 1;
attribute mti_svvh_generic_type of port_b_byte_enable_mask_width : constant is 1;
attribute mti_svvh_generic_type of port_a_read_during_write_mode : constant is 1;
attribute mti_svvh_generic_type of port_b_read_during_write_mode : constant is 1;
attribute mti_svvh_generic_type of power_up_uninitialized : constant is 1;
attribute mti_svvh_generic_type of lpm_type : constant is 1;
attribute mti_svvh_generic_type of lpm_hint : constant is 1;
attribute mti_svvh_generic_type of connectivity_checking : constant is 1;
attribute mti_svvh_generic_type of mem_init0 : constant is 1;
attribute mti_svvh_generic_type of mem_init1 : constant is 1;
attribute mti_svvh_generic_type of mem_init2 : constant is 1;
attribute mti_svvh_generic_type of mem_init3 : constant is 1;
attribute mti_svvh_generic_type of mem_init4 : constant is 1;
attribute mti_svvh_generic_type of mem_init5 : constant is 1;
attribute mti_svvh_generic_type of mem_init6 : constant is 1;
attribute mti_svvh_generic_type of mem_init7 : constant is 1;
attribute mti_svvh_generic_type of mem_init8 : constant is 1;
attribute mti_svvh_generic_type of mem_init9 : constant is 1;
attribute mti_svvh_generic_type of port_a_byte_size : constant is 1;
attribute mti_svvh_generic_type of port_b_byte_size : constant is 1;
attribute mti_svvh_generic_type of clk0_input_clock_enable : constant is 1;
attribute mti_svvh_generic_type of clk0_core_clock_enable : constant is 1;
attribute mti_svvh_generic_type of clk0_output_clock_enable : constant is 1;
attribute mti_svvh_generic_type of clk1_input_clock_enable : constant is 1;
attribute mti_svvh_generic_type of clk1_core_clock_enable : constant is 1;
attribute mti_svvh_generic_type of clk1_output_clock_enable : constant is 1;
attribute mti_svvh_generic_type of bist_ena : constant is 1;
attribute mti_svvh_generic_type of port_a_address_clear : constant is 1;
attribute mti_svvh_generic_type of port_a_data_in_clock : constant is 1;
attribute mti_svvh_generic_type of port_a_address_clock : constant is 1;
attribute mti_svvh_generic_type of port_a_write_enable_clock : constant is 1;
attribute mti_svvh_generic_type of port_a_byte_enable_clock : constant is 1;
attribute mti_svvh_generic_type of port_a_read_enable_clock : constant is 1;
end generic_m20k;
|
library verilog;
use verilog.vl_types.all;
entity generic_m20k is
generic(
operation_mode : string := "single_port";
mixed_port_feed_through_mode: string := "dont_care";
ram_block_type : string := "auto";
logical_ram_name: string := "ram_name";
init_file : string := "init_file.hex";
init_file_layout: string := "none";
ecc_pipeline_stage_enabled: string := "false";
enable_ecc : string := "false";
width_eccstatus : integer := 2;
data_interleave_width_in_bits: integer := 1;
data_interleave_offset_in_bits: integer := 1;
port_a_logical_ram_depth: integer := 0;
port_a_logical_ram_width: integer := 0;
port_a_first_address: integer := 0;
port_a_last_address: integer := 0;
port_a_first_bit_number: integer := 0;
port_a_data_out_clear: string := "none";
port_a_data_out_clock: string := "none";
port_a_data_width: integer := 1;
port_a_address_width: integer := 1;
port_a_byte_enable_mask_width: integer := 1;
port_b_logical_ram_depth: integer := 0;
port_b_logical_ram_width: integer := 0;
port_b_first_address: integer := 0;
port_b_last_address: integer := 0;
port_b_first_bit_number: integer := 0;
port_b_address_clear: string := "none";
port_b_data_out_clear: string := "none";
port_b_data_in_clock: string := "clock1";
port_b_address_clock: string := "clock1";
port_b_write_enable_clock: string := "clock1";
port_b_read_enable_clock: string := "clock1";
port_b_byte_enable_clock: string := "clock1";
port_b_data_out_clock: string := "none";
port_b_data_width: integer := 1;
port_b_address_width: integer := 1;
port_b_byte_enable_mask_width: integer := 1;
port_a_read_during_write_mode: string := "new_data_no_nbe_read";
port_b_read_during_write_mode: string := "new_data_no_nbe_read";
power_up_uninitialized: string := "false";
lpm_type : string := "stratixv_ram_block";
lpm_hint : string := "true";
connectivity_checking: string := "off";
mem_init0 : string := "";
mem_init1 : string := "";
mem_init2 : string := "";
mem_init3 : string := "";
mem_init4 : string := "";
mem_init5 : string := "";
mem_init6 : string := "";
mem_init7 : string := "";
mem_init8 : string := "";
mem_init9 : string := "";
port_a_byte_size: integer := 0;
port_b_byte_size: integer := 0;
clk0_input_clock_enable: string := "none";
clk0_core_clock_enable: string := "none";
clk0_output_clock_enable: string := "none";
clk1_input_clock_enable: string := "none";
clk1_core_clock_enable: string := "none";
clk1_output_clock_enable: string := "none";
bist_ena : string := "false";
port_a_address_clear: string := "none";
port_a_data_in_clock: string := "clock0";
port_a_address_clock: string := "clock0";
port_a_write_enable_clock: string := "clock0";
port_a_byte_enable_clock: string := "clock0";
port_a_read_enable_clock: string := "clock0"
);
port(
portadatain : in vl_logic_vector;
portaaddr : in vl_logic_vector;
portawe : in vl_logic;
portare : in vl_logic;
portbdatain : in vl_logic_vector;
portbaddr : in vl_logic_vector;
portbwe : in vl_logic;
portbre : in vl_logic;
clk0 : in vl_logic;
clk1 : in vl_logic;
ena0 : in vl_logic;
ena1 : in vl_logic;
ena2 : in vl_logic;
ena3 : in vl_logic;
clr0 : in vl_logic;
clr1 : in vl_logic;
nerror : in vl_logic;
portabyteenamasks: in vl_logic_vector;
portbbyteenamasks: in vl_logic_vector;
portaaddrstall : in vl_logic;
portbaddrstall : in vl_logic;
devclrn : in vl_logic;
devpor : in vl_logic;
eccstatus : out vl_logic_vector;
portadataout : out vl_logic_vector;
portbdataout : out vl_logic_vector;
dftout : out vl_logic_vector(8 downto 0)
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of operation_mode : constant is 1;
attribute mti_svvh_generic_type of mixed_port_feed_through_mode : constant is 1;
attribute mti_svvh_generic_type of ram_block_type : constant is 1;
attribute mti_svvh_generic_type of logical_ram_name : constant is 1;
attribute mti_svvh_generic_type of init_file : constant is 1;
attribute mti_svvh_generic_type of init_file_layout : constant is 1;
attribute mti_svvh_generic_type of ecc_pipeline_stage_enabled : constant is 1;
attribute mti_svvh_generic_type of enable_ecc : constant is 1;
attribute mti_svvh_generic_type of width_eccstatus : constant is 1;
attribute mti_svvh_generic_type of data_interleave_width_in_bits : constant is 1;
attribute mti_svvh_generic_type of data_interleave_offset_in_bits : constant is 1;
attribute mti_svvh_generic_type of port_a_logical_ram_depth : constant is 1;
attribute mti_svvh_generic_type of port_a_logical_ram_width : constant is 1;
attribute mti_svvh_generic_type of port_a_first_address : constant is 1;
attribute mti_svvh_generic_type of port_a_last_address : constant is 1;
attribute mti_svvh_generic_type of port_a_first_bit_number : constant is 1;
attribute mti_svvh_generic_type of port_a_data_out_clear : constant is 1;
attribute mti_svvh_generic_type of port_a_data_out_clock : constant is 1;
attribute mti_svvh_generic_type of port_a_data_width : constant is 1;
attribute mti_svvh_generic_type of port_a_address_width : constant is 1;
attribute mti_svvh_generic_type of port_a_byte_enable_mask_width : constant is 1;
attribute mti_svvh_generic_type of port_b_logical_ram_depth : constant is 1;
attribute mti_svvh_generic_type of port_b_logical_ram_width : constant is 1;
attribute mti_svvh_generic_type of port_b_first_address : constant is 1;
attribute mti_svvh_generic_type of port_b_last_address : constant is 1;
attribute mti_svvh_generic_type of port_b_first_bit_number : constant is 1;
attribute mti_svvh_generic_type of port_b_address_clear : constant is 1;
attribute mti_svvh_generic_type of port_b_data_out_clear : constant is 1;
attribute mti_svvh_generic_type of port_b_data_in_clock : constant is 1;
attribute mti_svvh_generic_type of port_b_address_clock : constant is 1;
attribute mti_svvh_generic_type of port_b_write_enable_clock : constant is 1;
attribute mti_svvh_generic_type of port_b_read_enable_clock : constant is 1;
attribute mti_svvh_generic_type of port_b_byte_enable_clock : constant is 1;
attribute mti_svvh_generic_type of port_b_data_out_clock : constant is 1;
attribute mti_svvh_generic_type of port_b_data_width : constant is 1;
attribute mti_svvh_generic_type of port_b_address_width : constant is 1;
attribute mti_svvh_generic_type of port_b_byte_enable_mask_width : constant is 1;
attribute mti_svvh_generic_type of port_a_read_during_write_mode : constant is 1;
attribute mti_svvh_generic_type of port_b_read_during_write_mode : constant is 1;
attribute mti_svvh_generic_type of power_up_uninitialized : constant is 1;
attribute mti_svvh_generic_type of lpm_type : constant is 1;
attribute mti_svvh_generic_type of lpm_hint : constant is 1;
attribute mti_svvh_generic_type of connectivity_checking : constant is 1;
attribute mti_svvh_generic_type of mem_init0 : constant is 1;
attribute mti_svvh_generic_type of mem_init1 : constant is 1;
attribute mti_svvh_generic_type of mem_init2 : constant is 1;
attribute mti_svvh_generic_type of mem_init3 : constant is 1;
attribute mti_svvh_generic_type of mem_init4 : constant is 1;
attribute mti_svvh_generic_type of mem_init5 : constant is 1;
attribute mti_svvh_generic_type of mem_init6 : constant is 1;
attribute mti_svvh_generic_type of mem_init7 : constant is 1;
attribute mti_svvh_generic_type of mem_init8 : constant is 1;
attribute mti_svvh_generic_type of mem_init9 : constant is 1;
attribute mti_svvh_generic_type of port_a_byte_size : constant is 1;
attribute mti_svvh_generic_type of port_b_byte_size : constant is 1;
attribute mti_svvh_generic_type of clk0_input_clock_enable : constant is 1;
attribute mti_svvh_generic_type of clk0_core_clock_enable : constant is 1;
attribute mti_svvh_generic_type of clk0_output_clock_enable : constant is 1;
attribute mti_svvh_generic_type of clk1_input_clock_enable : constant is 1;
attribute mti_svvh_generic_type of clk1_core_clock_enable : constant is 1;
attribute mti_svvh_generic_type of clk1_output_clock_enable : constant is 1;
attribute mti_svvh_generic_type of bist_ena : constant is 1;
attribute mti_svvh_generic_type of port_a_address_clear : constant is 1;
attribute mti_svvh_generic_type of port_a_data_in_clock : constant is 1;
attribute mti_svvh_generic_type of port_a_address_clock : constant is 1;
attribute mti_svvh_generic_type of port_a_write_enable_clock : constant is 1;
attribute mti_svvh_generic_type of port_a_byte_enable_clock : constant is 1;
attribute mti_svvh_generic_type of port_a_read_enable_clock : constant is 1;
end generic_m20k;
|
library verilog;
use verilog.vl_types.all;
entity generic_m20k is
generic(
operation_mode : string := "single_port";
mixed_port_feed_through_mode: string := "dont_care";
ram_block_type : string := "auto";
logical_ram_name: string := "ram_name";
init_file : string := "init_file.hex";
init_file_layout: string := "none";
ecc_pipeline_stage_enabled: string := "false";
enable_ecc : string := "false";
width_eccstatus : integer := 2;
data_interleave_width_in_bits: integer := 1;
data_interleave_offset_in_bits: integer := 1;
port_a_logical_ram_depth: integer := 0;
port_a_logical_ram_width: integer := 0;
port_a_first_address: integer := 0;
port_a_last_address: integer := 0;
port_a_first_bit_number: integer := 0;
port_a_data_out_clear: string := "none";
port_a_data_out_clock: string := "none";
port_a_data_width: integer := 1;
port_a_address_width: integer := 1;
port_a_byte_enable_mask_width: integer := 1;
port_b_logical_ram_depth: integer := 0;
port_b_logical_ram_width: integer := 0;
port_b_first_address: integer := 0;
port_b_last_address: integer := 0;
port_b_first_bit_number: integer := 0;
port_b_address_clear: string := "none";
port_b_data_out_clear: string := "none";
port_b_data_in_clock: string := "clock1";
port_b_address_clock: string := "clock1";
port_b_write_enable_clock: string := "clock1";
port_b_read_enable_clock: string := "clock1";
port_b_byte_enable_clock: string := "clock1";
port_b_data_out_clock: string := "none";
port_b_data_width: integer := 1;
port_b_address_width: integer := 1;
port_b_byte_enable_mask_width: integer := 1;
port_a_read_during_write_mode: string := "new_data_no_nbe_read";
port_b_read_during_write_mode: string := "new_data_no_nbe_read";
power_up_uninitialized: string := "false";
lpm_type : string := "stratixv_ram_block";
lpm_hint : string := "true";
connectivity_checking: string := "off";
mem_init0 : string := "";
mem_init1 : string := "";
mem_init2 : string := "";
mem_init3 : string := "";
mem_init4 : string := "";
mem_init5 : string := "";
mem_init6 : string := "";
mem_init7 : string := "";
mem_init8 : string := "";
mem_init9 : string := "";
port_a_byte_size: integer := 0;
port_b_byte_size: integer := 0;
clk0_input_clock_enable: string := "none";
clk0_core_clock_enable: string := "none";
clk0_output_clock_enable: string := "none";
clk1_input_clock_enable: string := "none";
clk1_core_clock_enable: string := "none";
clk1_output_clock_enable: string := "none";
bist_ena : string := "false";
port_a_address_clear: string := "none";
port_a_data_in_clock: string := "clock0";
port_a_address_clock: string := "clock0";
port_a_write_enable_clock: string := "clock0";
port_a_byte_enable_clock: string := "clock0";
port_a_read_enable_clock: string := "clock0"
);
port(
portadatain : in vl_logic_vector;
portaaddr : in vl_logic_vector;
portawe : in vl_logic;
portare : in vl_logic;
portbdatain : in vl_logic_vector;
portbaddr : in vl_logic_vector;
portbwe : in vl_logic;
portbre : in vl_logic;
clk0 : in vl_logic;
clk1 : in vl_logic;
ena0 : in vl_logic;
ena1 : in vl_logic;
ena2 : in vl_logic;
ena3 : in vl_logic;
clr0 : in vl_logic;
clr1 : in vl_logic;
nerror : in vl_logic;
portabyteenamasks: in vl_logic_vector;
portbbyteenamasks: in vl_logic_vector;
portaaddrstall : in vl_logic;
portbaddrstall : in vl_logic;
devclrn : in vl_logic;
devpor : in vl_logic;
eccstatus : out vl_logic_vector;
portadataout : out vl_logic_vector;
portbdataout : out vl_logic_vector;
dftout : out vl_logic_vector(8 downto 0)
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of operation_mode : constant is 1;
attribute mti_svvh_generic_type of mixed_port_feed_through_mode : constant is 1;
attribute mti_svvh_generic_type of ram_block_type : constant is 1;
attribute mti_svvh_generic_type of logical_ram_name : constant is 1;
attribute mti_svvh_generic_type of init_file : constant is 1;
attribute mti_svvh_generic_type of init_file_layout : constant is 1;
attribute mti_svvh_generic_type of ecc_pipeline_stage_enabled : constant is 1;
attribute mti_svvh_generic_type of enable_ecc : constant is 1;
attribute mti_svvh_generic_type of width_eccstatus : constant is 1;
attribute mti_svvh_generic_type of data_interleave_width_in_bits : constant is 1;
attribute mti_svvh_generic_type of data_interleave_offset_in_bits : constant is 1;
attribute mti_svvh_generic_type of port_a_logical_ram_depth : constant is 1;
attribute mti_svvh_generic_type of port_a_logical_ram_width : constant is 1;
attribute mti_svvh_generic_type of port_a_first_address : constant is 1;
attribute mti_svvh_generic_type of port_a_last_address : constant is 1;
attribute mti_svvh_generic_type of port_a_first_bit_number : constant is 1;
attribute mti_svvh_generic_type of port_a_data_out_clear : constant is 1;
attribute mti_svvh_generic_type of port_a_data_out_clock : constant is 1;
attribute mti_svvh_generic_type of port_a_data_width : constant is 1;
attribute mti_svvh_generic_type of port_a_address_width : constant is 1;
attribute mti_svvh_generic_type of port_a_byte_enable_mask_width : constant is 1;
attribute mti_svvh_generic_type of port_b_logical_ram_depth : constant is 1;
attribute mti_svvh_generic_type of port_b_logical_ram_width : constant is 1;
attribute mti_svvh_generic_type of port_b_first_address : constant is 1;
attribute mti_svvh_generic_type of port_b_last_address : constant is 1;
attribute mti_svvh_generic_type of port_b_first_bit_number : constant is 1;
attribute mti_svvh_generic_type of port_b_address_clear : constant is 1;
attribute mti_svvh_generic_type of port_b_data_out_clear : constant is 1;
attribute mti_svvh_generic_type of port_b_data_in_clock : constant is 1;
attribute mti_svvh_generic_type of port_b_address_clock : constant is 1;
attribute mti_svvh_generic_type of port_b_write_enable_clock : constant is 1;
attribute mti_svvh_generic_type of port_b_read_enable_clock : constant is 1;
attribute mti_svvh_generic_type of port_b_byte_enable_clock : constant is 1;
attribute mti_svvh_generic_type of port_b_data_out_clock : constant is 1;
attribute mti_svvh_generic_type of port_b_data_width : constant is 1;
attribute mti_svvh_generic_type of port_b_address_width : constant is 1;
attribute mti_svvh_generic_type of port_b_byte_enable_mask_width : constant is 1;
attribute mti_svvh_generic_type of port_a_read_during_write_mode : constant is 1;
attribute mti_svvh_generic_type of port_b_read_during_write_mode : constant is 1;
attribute mti_svvh_generic_type of power_up_uninitialized : constant is 1;
attribute mti_svvh_generic_type of lpm_type : constant is 1;
attribute mti_svvh_generic_type of lpm_hint : constant is 1;
attribute mti_svvh_generic_type of connectivity_checking : constant is 1;
attribute mti_svvh_generic_type of mem_init0 : constant is 1;
attribute mti_svvh_generic_type of mem_init1 : constant is 1;
attribute mti_svvh_generic_type of mem_init2 : constant is 1;
attribute mti_svvh_generic_type of mem_init3 : constant is 1;
attribute mti_svvh_generic_type of mem_init4 : constant is 1;
attribute mti_svvh_generic_type of mem_init5 : constant is 1;
attribute mti_svvh_generic_type of mem_init6 : constant is 1;
attribute mti_svvh_generic_type of mem_init7 : constant is 1;
attribute mti_svvh_generic_type of mem_init8 : constant is 1;
attribute mti_svvh_generic_type of mem_init9 : constant is 1;
attribute mti_svvh_generic_type of port_a_byte_size : constant is 1;
attribute mti_svvh_generic_type of port_b_byte_size : constant is 1;
attribute mti_svvh_generic_type of clk0_input_clock_enable : constant is 1;
attribute mti_svvh_generic_type of clk0_core_clock_enable : constant is 1;
attribute mti_svvh_generic_type of clk0_output_clock_enable : constant is 1;
attribute mti_svvh_generic_type of clk1_input_clock_enable : constant is 1;
attribute mti_svvh_generic_type of clk1_core_clock_enable : constant is 1;
attribute mti_svvh_generic_type of clk1_output_clock_enable : constant is 1;
attribute mti_svvh_generic_type of bist_ena : constant is 1;
attribute mti_svvh_generic_type of port_a_address_clear : constant is 1;
attribute mti_svvh_generic_type of port_a_data_in_clock : constant is 1;
attribute mti_svvh_generic_type of port_a_address_clock : constant is 1;
attribute mti_svvh_generic_type of port_a_write_enable_clock : constant is 1;
attribute mti_svvh_generic_type of port_a_byte_enable_clock : constant is 1;
attribute mti_svvh_generic_type of port_a_read_enable_clock : constant is 1;
end generic_m20k;
|
library verilog;
use verilog.vl_types.all;
entity generic_m20k is
generic(
operation_mode : string := "single_port";
mixed_port_feed_through_mode: string := "dont_care";
ram_block_type : string := "auto";
logical_ram_name: string := "ram_name";
init_file : string := "init_file.hex";
init_file_layout: string := "none";
ecc_pipeline_stage_enabled: string := "false";
enable_ecc : string := "false";
width_eccstatus : integer := 2;
data_interleave_width_in_bits: integer := 1;
data_interleave_offset_in_bits: integer := 1;
port_a_logical_ram_depth: integer := 0;
port_a_logical_ram_width: integer := 0;
port_a_first_address: integer := 0;
port_a_last_address: integer := 0;
port_a_first_bit_number: integer := 0;
port_a_data_out_clear: string := "none";
port_a_data_out_clock: string := "none";
port_a_data_width: integer := 1;
port_a_address_width: integer := 1;
port_a_byte_enable_mask_width: integer := 1;
port_b_logical_ram_depth: integer := 0;
port_b_logical_ram_width: integer := 0;
port_b_first_address: integer := 0;
port_b_last_address: integer := 0;
port_b_first_bit_number: integer := 0;
port_b_address_clear: string := "none";
port_b_data_out_clear: string := "none";
port_b_data_in_clock: string := "clock1";
port_b_address_clock: string := "clock1";
port_b_write_enable_clock: string := "clock1";
port_b_read_enable_clock: string := "clock1";
port_b_byte_enable_clock: string := "clock1";
port_b_data_out_clock: string := "none";
port_b_data_width: integer := 1;
port_b_address_width: integer := 1;
port_b_byte_enable_mask_width: integer := 1;
port_a_read_during_write_mode: string := "new_data_no_nbe_read";
port_b_read_during_write_mode: string := "new_data_no_nbe_read";
power_up_uninitialized: string := "false";
lpm_type : string := "stratixv_ram_block";
lpm_hint : string := "true";
connectivity_checking: string := "off";
mem_init0 : string := "";
mem_init1 : string := "";
mem_init2 : string := "";
mem_init3 : string := "";
mem_init4 : string := "";
mem_init5 : string := "";
mem_init6 : string := "";
mem_init7 : string := "";
mem_init8 : string := "";
mem_init9 : string := "";
port_a_byte_size: integer := 0;
port_b_byte_size: integer := 0;
clk0_input_clock_enable: string := "none";
clk0_core_clock_enable: string := "none";
clk0_output_clock_enable: string := "none";
clk1_input_clock_enable: string := "none";
clk1_core_clock_enable: string := "none";
clk1_output_clock_enable: string := "none";
bist_ena : string := "false";
port_a_address_clear: string := "none";
port_a_data_in_clock: string := "clock0";
port_a_address_clock: string := "clock0";
port_a_write_enable_clock: string := "clock0";
port_a_byte_enable_clock: string := "clock0";
port_a_read_enable_clock: string := "clock0"
);
port(
portadatain : in vl_logic_vector;
portaaddr : in vl_logic_vector;
portawe : in vl_logic;
portare : in vl_logic;
portbdatain : in vl_logic_vector;
portbaddr : in vl_logic_vector;
portbwe : in vl_logic;
portbre : in vl_logic;
clk0 : in vl_logic;
clk1 : in vl_logic;
ena0 : in vl_logic;
ena1 : in vl_logic;
ena2 : in vl_logic;
ena3 : in vl_logic;
clr0 : in vl_logic;
clr1 : in vl_logic;
nerror : in vl_logic;
portabyteenamasks: in vl_logic_vector;
portbbyteenamasks: in vl_logic_vector;
portaaddrstall : in vl_logic;
portbaddrstall : in vl_logic;
devclrn : in vl_logic;
devpor : in vl_logic;
eccstatus : out vl_logic_vector;
portadataout : out vl_logic_vector;
portbdataout : out vl_logic_vector;
dftout : out vl_logic_vector(8 downto 0)
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of operation_mode : constant is 1;
attribute mti_svvh_generic_type of mixed_port_feed_through_mode : constant is 1;
attribute mti_svvh_generic_type of ram_block_type : constant is 1;
attribute mti_svvh_generic_type of logical_ram_name : constant is 1;
attribute mti_svvh_generic_type of init_file : constant is 1;
attribute mti_svvh_generic_type of init_file_layout : constant is 1;
attribute mti_svvh_generic_type of ecc_pipeline_stage_enabled : constant is 1;
attribute mti_svvh_generic_type of enable_ecc : constant is 1;
attribute mti_svvh_generic_type of width_eccstatus : constant is 1;
attribute mti_svvh_generic_type of data_interleave_width_in_bits : constant is 1;
attribute mti_svvh_generic_type of data_interleave_offset_in_bits : constant is 1;
attribute mti_svvh_generic_type of port_a_logical_ram_depth : constant is 1;
attribute mti_svvh_generic_type of port_a_logical_ram_width : constant is 1;
attribute mti_svvh_generic_type of port_a_first_address : constant is 1;
attribute mti_svvh_generic_type of port_a_last_address : constant is 1;
attribute mti_svvh_generic_type of port_a_first_bit_number : constant is 1;
attribute mti_svvh_generic_type of port_a_data_out_clear : constant is 1;
attribute mti_svvh_generic_type of port_a_data_out_clock : constant is 1;
attribute mti_svvh_generic_type of port_a_data_width : constant is 1;
attribute mti_svvh_generic_type of port_a_address_width : constant is 1;
attribute mti_svvh_generic_type of port_a_byte_enable_mask_width : constant is 1;
attribute mti_svvh_generic_type of port_b_logical_ram_depth : constant is 1;
attribute mti_svvh_generic_type of port_b_logical_ram_width : constant is 1;
attribute mti_svvh_generic_type of port_b_first_address : constant is 1;
attribute mti_svvh_generic_type of port_b_last_address : constant is 1;
attribute mti_svvh_generic_type of port_b_first_bit_number : constant is 1;
attribute mti_svvh_generic_type of port_b_address_clear : constant is 1;
attribute mti_svvh_generic_type of port_b_data_out_clear : constant is 1;
attribute mti_svvh_generic_type of port_b_data_in_clock : constant is 1;
attribute mti_svvh_generic_type of port_b_address_clock : constant is 1;
attribute mti_svvh_generic_type of port_b_write_enable_clock : constant is 1;
attribute mti_svvh_generic_type of port_b_read_enable_clock : constant is 1;
attribute mti_svvh_generic_type of port_b_byte_enable_clock : constant is 1;
attribute mti_svvh_generic_type of port_b_data_out_clock : constant is 1;
attribute mti_svvh_generic_type of port_b_data_width : constant is 1;
attribute mti_svvh_generic_type of port_b_address_width : constant is 1;
attribute mti_svvh_generic_type of port_b_byte_enable_mask_width : constant is 1;
attribute mti_svvh_generic_type of port_a_read_during_write_mode : constant is 1;
attribute mti_svvh_generic_type of port_b_read_during_write_mode : constant is 1;
attribute mti_svvh_generic_type of power_up_uninitialized : constant is 1;
attribute mti_svvh_generic_type of lpm_type : constant is 1;
attribute mti_svvh_generic_type of lpm_hint : constant is 1;
attribute mti_svvh_generic_type of connectivity_checking : constant is 1;
attribute mti_svvh_generic_type of mem_init0 : constant is 1;
attribute mti_svvh_generic_type of mem_init1 : constant is 1;
attribute mti_svvh_generic_type of mem_init2 : constant is 1;
attribute mti_svvh_generic_type of mem_init3 : constant is 1;
attribute mti_svvh_generic_type of mem_init4 : constant is 1;
attribute mti_svvh_generic_type of mem_init5 : constant is 1;
attribute mti_svvh_generic_type of mem_init6 : constant is 1;
attribute mti_svvh_generic_type of mem_init7 : constant is 1;
attribute mti_svvh_generic_type of mem_init8 : constant is 1;
attribute mti_svvh_generic_type of mem_init9 : constant is 1;
attribute mti_svvh_generic_type of port_a_byte_size : constant is 1;
attribute mti_svvh_generic_type of port_b_byte_size : constant is 1;
attribute mti_svvh_generic_type of clk0_input_clock_enable : constant is 1;
attribute mti_svvh_generic_type of clk0_core_clock_enable : constant is 1;
attribute mti_svvh_generic_type of clk0_output_clock_enable : constant is 1;
attribute mti_svvh_generic_type of clk1_input_clock_enable : constant is 1;
attribute mti_svvh_generic_type of clk1_core_clock_enable : constant is 1;
attribute mti_svvh_generic_type of clk1_output_clock_enable : constant is 1;
attribute mti_svvh_generic_type of bist_ena : constant is 1;
attribute mti_svvh_generic_type of port_a_address_clear : constant is 1;
attribute mti_svvh_generic_type of port_a_data_in_clock : constant is 1;
attribute mti_svvh_generic_type of port_a_address_clock : constant is 1;
attribute mti_svvh_generic_type of port_a_write_enable_clock : constant is 1;
attribute mti_svvh_generic_type of port_a_byte_enable_clock : constant is 1;
attribute mti_svvh_generic_type of port_a_read_enable_clock : constant is 1;
end generic_m20k;
|
library verilog;
use verilog.vl_types.all;
entity generic_m20k is
generic(
operation_mode : string := "single_port";
mixed_port_feed_through_mode: string := "dont_care";
ram_block_type : string := "auto";
logical_ram_name: string := "ram_name";
init_file : string := "init_file.hex";
init_file_layout: string := "none";
ecc_pipeline_stage_enabled: string := "false";
enable_ecc : string := "false";
width_eccstatus : integer := 2;
data_interleave_width_in_bits: integer := 1;
data_interleave_offset_in_bits: integer := 1;
port_a_logical_ram_depth: integer := 0;
port_a_logical_ram_width: integer := 0;
port_a_first_address: integer := 0;
port_a_last_address: integer := 0;
port_a_first_bit_number: integer := 0;
port_a_data_out_clear: string := "none";
port_a_data_out_clock: string := "none";
port_a_data_width: integer := 1;
port_a_address_width: integer := 1;
port_a_byte_enable_mask_width: integer := 1;
port_b_logical_ram_depth: integer := 0;
port_b_logical_ram_width: integer := 0;
port_b_first_address: integer := 0;
port_b_last_address: integer := 0;
port_b_first_bit_number: integer := 0;
port_b_address_clear: string := "none";
port_b_data_out_clear: string := "none";
port_b_data_in_clock: string := "clock1";
port_b_address_clock: string := "clock1";
port_b_write_enable_clock: string := "clock1";
port_b_read_enable_clock: string := "clock1";
port_b_byte_enable_clock: string := "clock1";
port_b_data_out_clock: string := "none";
port_b_data_width: integer := 1;
port_b_address_width: integer := 1;
port_b_byte_enable_mask_width: integer := 1;
port_a_read_during_write_mode: string := "new_data_no_nbe_read";
port_b_read_during_write_mode: string := "new_data_no_nbe_read";
power_up_uninitialized: string := "false";
lpm_type : string := "stratixv_ram_block";
lpm_hint : string := "true";
connectivity_checking: string := "off";
mem_init0 : string := "";
mem_init1 : string := "";
mem_init2 : string := "";
mem_init3 : string := "";
mem_init4 : string := "";
mem_init5 : string := "";
mem_init6 : string := "";
mem_init7 : string := "";
mem_init8 : string := "";
mem_init9 : string := "";
port_a_byte_size: integer := 0;
port_b_byte_size: integer := 0;
clk0_input_clock_enable: string := "none";
clk0_core_clock_enable: string := "none";
clk0_output_clock_enable: string := "none";
clk1_input_clock_enable: string := "none";
clk1_core_clock_enable: string := "none";
clk1_output_clock_enable: string := "none";
bist_ena : string := "false";
port_a_address_clear: string := "none";
port_a_data_in_clock: string := "clock0";
port_a_address_clock: string := "clock0";
port_a_write_enable_clock: string := "clock0";
port_a_byte_enable_clock: string := "clock0";
port_a_read_enable_clock: string := "clock0"
);
port(
portadatain : in vl_logic_vector;
portaaddr : in vl_logic_vector;
portawe : in vl_logic;
portare : in vl_logic;
portbdatain : in vl_logic_vector;
portbaddr : in vl_logic_vector;
portbwe : in vl_logic;
portbre : in vl_logic;
clk0 : in vl_logic;
clk1 : in vl_logic;
ena0 : in vl_logic;
ena1 : in vl_logic;
ena2 : in vl_logic;
ena3 : in vl_logic;
clr0 : in vl_logic;
clr1 : in vl_logic;
nerror : in vl_logic;
portabyteenamasks: in vl_logic_vector;
portbbyteenamasks: in vl_logic_vector;
portaaddrstall : in vl_logic;
portbaddrstall : in vl_logic;
devclrn : in vl_logic;
devpor : in vl_logic;
eccstatus : out vl_logic_vector;
portadataout : out vl_logic_vector;
portbdataout : out vl_logic_vector;
dftout : out vl_logic_vector(8 downto 0)
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of operation_mode : constant is 1;
attribute mti_svvh_generic_type of mixed_port_feed_through_mode : constant is 1;
attribute mti_svvh_generic_type of ram_block_type : constant is 1;
attribute mti_svvh_generic_type of logical_ram_name : constant is 1;
attribute mti_svvh_generic_type of init_file : constant is 1;
attribute mti_svvh_generic_type of init_file_layout : constant is 1;
attribute mti_svvh_generic_type of ecc_pipeline_stage_enabled : constant is 1;
attribute mti_svvh_generic_type of enable_ecc : constant is 1;
attribute mti_svvh_generic_type of width_eccstatus : constant is 1;
attribute mti_svvh_generic_type of data_interleave_width_in_bits : constant is 1;
attribute mti_svvh_generic_type of data_interleave_offset_in_bits : constant is 1;
attribute mti_svvh_generic_type of port_a_logical_ram_depth : constant is 1;
attribute mti_svvh_generic_type of port_a_logical_ram_width : constant is 1;
attribute mti_svvh_generic_type of port_a_first_address : constant is 1;
attribute mti_svvh_generic_type of port_a_last_address : constant is 1;
attribute mti_svvh_generic_type of port_a_first_bit_number : constant is 1;
attribute mti_svvh_generic_type of port_a_data_out_clear : constant is 1;
attribute mti_svvh_generic_type of port_a_data_out_clock : constant is 1;
attribute mti_svvh_generic_type of port_a_data_width : constant is 1;
attribute mti_svvh_generic_type of port_a_address_width : constant is 1;
attribute mti_svvh_generic_type of port_a_byte_enable_mask_width : constant is 1;
attribute mti_svvh_generic_type of port_b_logical_ram_depth : constant is 1;
attribute mti_svvh_generic_type of port_b_logical_ram_width : constant is 1;
attribute mti_svvh_generic_type of port_b_first_address : constant is 1;
attribute mti_svvh_generic_type of port_b_last_address : constant is 1;
attribute mti_svvh_generic_type of port_b_first_bit_number : constant is 1;
attribute mti_svvh_generic_type of port_b_address_clear : constant is 1;
attribute mti_svvh_generic_type of port_b_data_out_clear : constant is 1;
attribute mti_svvh_generic_type of port_b_data_in_clock : constant is 1;
attribute mti_svvh_generic_type of port_b_address_clock : constant is 1;
attribute mti_svvh_generic_type of port_b_write_enable_clock : constant is 1;
attribute mti_svvh_generic_type of port_b_read_enable_clock : constant is 1;
attribute mti_svvh_generic_type of port_b_byte_enable_clock : constant is 1;
attribute mti_svvh_generic_type of port_b_data_out_clock : constant is 1;
attribute mti_svvh_generic_type of port_b_data_width : constant is 1;
attribute mti_svvh_generic_type of port_b_address_width : constant is 1;
attribute mti_svvh_generic_type of port_b_byte_enable_mask_width : constant is 1;
attribute mti_svvh_generic_type of port_a_read_during_write_mode : constant is 1;
attribute mti_svvh_generic_type of port_b_read_during_write_mode : constant is 1;
attribute mti_svvh_generic_type of power_up_uninitialized : constant is 1;
attribute mti_svvh_generic_type of lpm_type : constant is 1;
attribute mti_svvh_generic_type of lpm_hint : constant is 1;
attribute mti_svvh_generic_type of connectivity_checking : constant is 1;
attribute mti_svvh_generic_type of mem_init0 : constant is 1;
attribute mti_svvh_generic_type of mem_init1 : constant is 1;
attribute mti_svvh_generic_type of mem_init2 : constant is 1;
attribute mti_svvh_generic_type of mem_init3 : constant is 1;
attribute mti_svvh_generic_type of mem_init4 : constant is 1;
attribute mti_svvh_generic_type of mem_init5 : constant is 1;
attribute mti_svvh_generic_type of mem_init6 : constant is 1;
attribute mti_svvh_generic_type of mem_init7 : constant is 1;
attribute mti_svvh_generic_type of mem_init8 : constant is 1;
attribute mti_svvh_generic_type of mem_init9 : constant is 1;
attribute mti_svvh_generic_type of port_a_byte_size : constant is 1;
attribute mti_svvh_generic_type of port_b_byte_size : constant is 1;
attribute mti_svvh_generic_type of clk0_input_clock_enable : constant is 1;
attribute mti_svvh_generic_type of clk0_core_clock_enable : constant is 1;
attribute mti_svvh_generic_type of clk0_output_clock_enable : constant is 1;
attribute mti_svvh_generic_type of clk1_input_clock_enable : constant is 1;
attribute mti_svvh_generic_type of clk1_core_clock_enable : constant is 1;
attribute mti_svvh_generic_type of clk1_output_clock_enable : constant is 1;
attribute mti_svvh_generic_type of bist_ena : constant is 1;
attribute mti_svvh_generic_type of port_a_address_clear : constant is 1;
attribute mti_svvh_generic_type of port_a_data_in_clock : constant is 1;
attribute mti_svvh_generic_type of port_a_address_clock : constant is 1;
attribute mti_svvh_generic_type of port_a_write_enable_clock : constant is 1;
attribute mti_svvh_generic_type of port_a_byte_enable_clock : constant is 1;
attribute mti_svvh_generic_type of port_a_read_enable_clock : constant is 1;
end generic_m20k;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1547.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s09b00x00p10n01i01547ent IS
END c08s09b00x00p10n01i01547ent;
ARCHITECTURE c08s09b00x00p10n01i01547arch OF c08s09b00x00p10n01i01547ent IS
BEGIN
TESTING: PROCESS
type t_enum1 is (en1, en2, en3, en4) ;
subtype st_enum1 is t_enum1 range en4 downto en1 ;
variable counter : integer := 0;
BEGIN
for i in st_enum1 loop
counter := counter + 1;
end loop;
assert NOT(counter=st_enum1'Pos(st_enum1'High)-st_enum1'Pos(st_enum1'Low)+1)
report "***PASSED TEST: c08s09b00x00p10n01i01547"
severity NOTE;
assert (counter=st_enum1'Pos(st_enum1'High)-st_enum1'Pos(st_enum1'Low)+1)
report "***FAILED TEST: c08s09b00x00p10n01i01547 - The loop is executed once for each of the values in the range."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s09b00x00p10n01i01547arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1547.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s09b00x00p10n01i01547ent IS
END c08s09b00x00p10n01i01547ent;
ARCHITECTURE c08s09b00x00p10n01i01547arch OF c08s09b00x00p10n01i01547ent IS
BEGIN
TESTING: PROCESS
type t_enum1 is (en1, en2, en3, en4) ;
subtype st_enum1 is t_enum1 range en4 downto en1 ;
variable counter : integer := 0;
BEGIN
for i in st_enum1 loop
counter := counter + 1;
end loop;
assert NOT(counter=st_enum1'Pos(st_enum1'High)-st_enum1'Pos(st_enum1'Low)+1)
report "***PASSED TEST: c08s09b00x00p10n01i01547"
severity NOTE;
assert (counter=st_enum1'Pos(st_enum1'High)-st_enum1'Pos(st_enum1'Low)+1)
report "***FAILED TEST: c08s09b00x00p10n01i01547 - The loop is executed once for each of the values in the range."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s09b00x00p10n01i01547arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1547.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s09b00x00p10n01i01547ent IS
END c08s09b00x00p10n01i01547ent;
ARCHITECTURE c08s09b00x00p10n01i01547arch OF c08s09b00x00p10n01i01547ent IS
BEGIN
TESTING: PROCESS
type t_enum1 is (en1, en2, en3, en4) ;
subtype st_enum1 is t_enum1 range en4 downto en1 ;
variable counter : integer := 0;
BEGIN
for i in st_enum1 loop
counter := counter + 1;
end loop;
assert NOT(counter=st_enum1'Pos(st_enum1'High)-st_enum1'Pos(st_enum1'Low)+1)
report "***PASSED TEST: c08s09b00x00p10n01i01547"
severity NOTE;
assert (counter=st_enum1'Pos(st_enum1'High)-st_enum1'Pos(st_enum1'Low)+1)
report "***FAILED TEST: c08s09b00x00p10n01i01547 - The loop is executed once for each of the values in the range."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s09b00x00p10n01i01547arch;
|
----------------------------------------------------------------------------------
-- Company: TU Vienna
-- Engineer: Georg Blemenschitz
--
-- Create Date: 14:11:00 11/22/2009
-- Design Name: FIFO
-- Module Name: FIFODualPortRam - rtl
-- Description: Dual port RAM for FIFO
--
-- Revision:
-- Revision 0.01 - File Created
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
--use IEEE.RTL_ATTRIBUTES.ALL;
-- from IEEE Std 1076.6-2004 (not supported by every tool)
-- please refer to chapter 6.5.2 Random-access memory (RAM) and chapter 7.1.5.3 Logic block
-- alternative disable "RAM Extraction" in Design Goals & Strategies
entity FIFODualPortRam is
Generic (
DataWidth : integer range 2 to 64 := 8;
AdressWidth : integer range 2 to 10 := 4);
Port (
Reset_n_i : in STD_LOGIC;
ClkA : in STD_LOGIC;
DataA_i : in STD_LOGIC_VECTOR (DataWidth - 1 downto 0);
AdressA_i : in STD_LOGIC_VECTOR (AdressWidth - 1 downto 0);
WriteEnableA_i : in STD_LOGIC;
DataB_o : out STD_LOGIC_VECTOR (DataWidth - 1 downto 0);
AdressB_i : in STD_LOGIC_VECTOR (AdressWidth - 1 downto 0));
end FIFODualPortRam;
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:35:44 08/06/2015
-- Design Name:
-- Module Name: E:/Programas_FPGA/SYNGLE_CYCLE_V3/TB_MAIN_PROCESSOR.vhd
-- Project Name: SYNGLE_CYCLE_V3
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: MAIN_PROCESSOR
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
USE ieee.numeric_std.ALL;
ENTITY TB_MAIN_PROCESSOR IS
END TB_MAIN_PROCESSOR;
ARCHITECTURE behavior OF TB_MAIN_PROCESSOR IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT MAIN_PROCESSOR
PORT(
CLK : IN std_logic;
RESET : IN std_logic
);
END COMPONENT;
--Inputs
signal CLK : std_logic := '0';
signal RESET : std_logic := '0';
-- Clock period definitions
constant CLK_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: MAIN_PROCESSOR PORT MAP (
CLK => CLK,
RESET => RESET
);
-- Clock process definitions
CLK_process :process
begin
CLK <= '0';
wait for CLK_period/2;
CLK <= '1';
wait for CLK_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
RESET <= '1';
wait for 10 ns;
RESET <= '0';
WAIT;
end process;
END;
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:35:44 08/06/2015
-- Design Name:
-- Module Name: E:/Programas_FPGA/SYNGLE_CYCLE_V3/TB_MAIN_PROCESSOR.vhd
-- Project Name: SYNGLE_CYCLE_V3
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: MAIN_PROCESSOR
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
USE ieee.numeric_std.ALL;
ENTITY TB_MAIN_PROCESSOR IS
END TB_MAIN_PROCESSOR;
ARCHITECTURE behavior OF TB_MAIN_PROCESSOR IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT MAIN_PROCESSOR
PORT(
CLK : IN std_logic;
RESET : IN std_logic
);
END COMPONENT;
--Inputs
signal CLK : std_logic := '0';
signal RESET : std_logic := '0';
-- Clock period definitions
constant CLK_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: MAIN_PROCESSOR PORT MAP (
CLK => CLK,
RESET => RESET
);
-- Clock process definitions
CLK_process :process
begin
CLK <= '0';
wait for CLK_period/2;
CLK <= '1';
wait for CLK_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
RESET <= '1';
wait for 10 ns;
RESET <= '0';
WAIT;
end process;
END;
|
entity case3 is
end entity;
architecture test of case3 is
signal x : bit_vector(3 downto 0);
signal y, z, q : integer;
begin
decode_y: with x select y <=
0 when X"0",
1 when X"1",
2 when X"2",
3 when X"3",
4 when X"4",
5 when X"5",
6 when X"6",
7 when X"7",
8 when X"8",
9 when X"9",
10 when X"a",
11 when X"b",
12 when X"c",
13 when X"d",
14 when X"e",
15 when X"f";
decode_z: with x(3 downto 0) select z <=
0 when X"0",
1 when X"1",
2 when X"2",
3 when X"3",
4 when X"4",
5 when X"5",
6 when X"6",
7 when X"7",
8 when X"8",
9 when X"9",
10 when X"a",
11 when X"b",
12 when X"c",
13 when X"d",
14 when X"e",
15 when X"f";
stim: process is
begin
wait for 0 ns;
assert y = 0;
assert z = 0;
x <= X"4";
wait for 1 ns;
assert y = 4;
assert y = 4;
x <= X"f";
wait for 1 ns;
assert y = 15;
assert z = 15;
wait;
end process;
end architecture;
|
entity case3 is
end entity;
architecture test of case3 is
signal x : bit_vector(3 downto 0);
signal y, z, q : integer;
begin
decode_y: with x select y <=
0 when X"0",
1 when X"1",
2 when X"2",
3 when X"3",
4 when X"4",
5 when X"5",
6 when X"6",
7 when X"7",
8 when X"8",
9 when X"9",
10 when X"a",
11 when X"b",
12 when X"c",
13 when X"d",
14 when X"e",
15 when X"f";
decode_z: with x(3 downto 0) select z <=
0 when X"0",
1 when X"1",
2 when X"2",
3 when X"3",
4 when X"4",
5 when X"5",
6 when X"6",
7 when X"7",
8 when X"8",
9 when X"9",
10 when X"a",
11 when X"b",
12 when X"c",
13 when X"d",
14 when X"e",
15 when X"f";
stim: process is
begin
wait for 0 ns;
assert y = 0;
assert z = 0;
x <= X"4";
wait for 1 ns;
assert y = 4;
assert y = 4;
x <= X"f";
wait for 1 ns;
assert y = 15;
assert z = 15;
wait;
end process;
end architecture;
|
entity case3 is
end entity;
architecture test of case3 is
signal x : bit_vector(3 downto 0);
signal y, z, q : integer;
begin
decode_y: with x select y <=
0 when X"0",
1 when X"1",
2 when X"2",
3 when X"3",
4 when X"4",
5 when X"5",
6 when X"6",
7 when X"7",
8 when X"8",
9 when X"9",
10 when X"a",
11 when X"b",
12 when X"c",
13 when X"d",
14 when X"e",
15 when X"f";
decode_z: with x(3 downto 0) select z <=
0 when X"0",
1 when X"1",
2 when X"2",
3 when X"3",
4 when X"4",
5 when X"5",
6 when X"6",
7 when X"7",
8 when X"8",
9 when X"9",
10 when X"a",
11 when X"b",
12 when X"c",
13 when X"d",
14 when X"e",
15 when X"f";
stim: process is
begin
wait for 0 ns;
assert y = 0;
assert z = 0;
x <= X"4";
wait for 1 ns;
assert y = 4;
assert y = 4;
x <= X"f";
wait for 1 ns;
assert y = 15;
assert z = 15;
wait;
end process;
end architecture;
|
entity case3 is
end entity;
architecture test of case3 is
signal x : bit_vector(3 downto 0);
signal y, z, q : integer;
begin
decode_y: with x select y <=
0 when X"0",
1 when X"1",
2 when X"2",
3 when X"3",
4 when X"4",
5 when X"5",
6 when X"6",
7 when X"7",
8 when X"8",
9 when X"9",
10 when X"a",
11 when X"b",
12 when X"c",
13 when X"d",
14 when X"e",
15 when X"f";
decode_z: with x(3 downto 0) select z <=
0 when X"0",
1 when X"1",
2 when X"2",
3 when X"3",
4 when X"4",
5 when X"5",
6 when X"6",
7 when X"7",
8 when X"8",
9 when X"9",
10 when X"a",
11 when X"b",
12 when X"c",
13 when X"d",
14 when X"e",
15 when X"f";
stim: process is
begin
wait for 0 ns;
assert y = 0;
assert z = 0;
x <= X"4";
wait for 1 ns;
assert y = 4;
assert y = 4;
x <= X"f";
wait for 1 ns;
assert y = 15;
assert z = 15;
wait;
end process;
end architecture;
|
entity case3 is
end entity;
architecture test of case3 is
signal x : bit_vector(3 downto 0);
signal y, z, q : integer;
begin
decode_y: with x select y <=
0 when X"0",
1 when X"1",
2 when X"2",
3 when X"3",
4 when X"4",
5 when X"5",
6 when X"6",
7 when X"7",
8 when X"8",
9 when X"9",
10 when X"a",
11 when X"b",
12 when X"c",
13 when X"d",
14 when X"e",
15 when X"f";
decode_z: with x(3 downto 0) select z <=
0 when X"0",
1 when X"1",
2 when X"2",
3 when X"3",
4 when X"4",
5 when X"5",
6 when X"6",
7 when X"7",
8 when X"8",
9 when X"9",
10 when X"a",
11 when X"b",
12 when X"c",
13 when X"d",
14 when X"e",
15 when X"f";
stim: process is
begin
wait for 0 ns;
assert y = 0;
assert z = 0;
x <= X"4";
wait for 1 ns;
assert y = 4;
assert y = 4;
x <= X"f";
wait for 1 ns;
assert y = 15;
assert z = 15;
wait;
end process;
end architecture;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 01:54:34 06/02/2011
-- Design Name:
-- Module Name: sha256_s0 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity sha256_s0 is
Port ( d : in STD_LOGIC_VECTOR (31 downto 0);
q : out STD_LOGIC_VECTOR (31 downto 0));
end sha256_s0;
architecture Behavioral of sha256_s0 is
begin
q(31 downto 29) <= d(6 downto 4) xor d(17 downto 15);
q(28 downto 0) <= (d(3 downto 0) & d(31 downto 7)) xor (d(14 downto 0) & d(31 downto 18)) xor d(31 downto 3);
end Behavioral;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 01:54:34 06/02/2011
-- Design Name:
-- Module Name: sha256_s0 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity sha256_s0 is
Port ( d : in STD_LOGIC_VECTOR (31 downto 0);
q : out STD_LOGIC_VECTOR (31 downto 0));
end sha256_s0;
architecture Behavioral of sha256_s0 is
begin
q(31 downto 29) <= d(6 downto 4) xor d(17 downto 15);
q(28 downto 0) <= (d(3 downto 0) & d(31 downto 7)) xor (d(14 downto 0) & d(31 downto 18)) xor d(31 downto 3);
end Behavioral;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 01:54:34 06/02/2011
-- Design Name:
-- Module Name: sha256_s0 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity sha256_s0 is
Port ( d : in STD_LOGIC_VECTOR (31 downto 0);
q : out STD_LOGIC_VECTOR (31 downto 0));
end sha256_s0;
architecture Behavioral of sha256_s0 is
begin
q(31 downto 29) <= d(6 downto 4) xor d(17 downto 15);
q(28 downto 0) <= (d(3 downto 0) & d(31 downto 7)) xor (d(14 downto 0) & d(31 downto 18)) xor d(31 downto 3);
end Behavioral;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 01:54:34 06/02/2011
-- Design Name:
-- Module Name: sha256_s0 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity sha256_s0 is
Port ( d : in STD_LOGIC_VECTOR (31 downto 0);
q : out STD_LOGIC_VECTOR (31 downto 0));
end sha256_s0;
architecture Behavioral of sha256_s0 is
begin
q(31 downto 29) <= d(6 downto 4) xor d(17 downto 15);
q(28 downto 0) <= (d(3 downto 0) & d(31 downto 7)) xor (d(14 downto 0) & d(31 downto 18)) xor d(31 downto 3);
end Behavioral;
|
-------------------------------------------------------------------------------
-- Title : Wishbone Debugger package
-- Project : FMC DEL 1ns 4cha-stand-alone application (fmc-delay-1ns-4cha-sa)
-------------------------------------------------------------------------------
-- File : debugger_pkg.vhd
-- Author : Jose Jimenez <[email protected]>
-- Company : University of Granada
-- Created : 2014-06-08
-- Last update: 2014-07-31
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: Wihsbone master with slave configuration interface for gateware
-- debuggin porpuses. Also provides a framework for stand alone
-- operation.
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2014-06-08 1.0 jjimenez Created
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
----use work.gn4124_core_pkg.all;
--use work.gencores_pkg.all;
--use work.wrcore_pkg.all;
----use work.wr_fabric_pkg.all;
--use work.wishbone_pkg.all;
----use work.fine_delay_pkg.all;
----use work.etherbone_pkg.all;
----use work.wr_xilinx_pkg.all;
--use work.genram_pkg.all;
--use work.wb_irq_pkg.all;
----use work.gencores_pkg.all;
use work.wishbone_pkg.all;
--use work.genram_pkg.all;
--use work.wb_irq_pkg.all;
--use work.debugger_pkg.all;
--
--use work.synthesis_descriptor.all;
package debugger_pkg is
------------------------------------------------------------------------------
-- Constants
-------------------------------------------------------------------------------
constant c_dbg_uart_sdb : t_sdb_device := (
abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"01",
wbd_endian => c_sdb_endian_big,
wbd_width => x"7", -- 8/16/32-bit port granularity
sdb_component => (
addr_first => x"0000000000000000",
addr_last => x"00000000000000ff",
product => (
vendor_id => x"000000000000CE42", -- CERN
device_id => x"0deafbee", -- she didn't listen & cames & goes
version => x"00000001",
date => x"20120305",
name => "WB-UART-Debugger ")));
constant c_dbg_irq_ctrl_sdb : t_sdb_device := (
abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"01",
wbd_endian => c_sdb_endian_big,
wbd_width => x"7", -- 8/16/32-bit port granularity
sdb_component => (
addr_first => x"0000000000000000",
addr_last => x"00000000000000ff",
product => (
vendor_id => x"0000000000000651", -- GSI
device_id => x"e1fb1ade", -- balanced, perfect grip, absolute control
version => x"00000001",
date => x"20120308",
name => "IRQ_CTRL-Debugger ")));
constant c_xwb_dbg_tics_sdb : t_sdb_device := (
abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"00",
wbd_endian => c_sdb_endian_big,
wbd_width => x"7", -- 8/16/32-bit port granularity
sdb_component => (
addr_first => x"0000000000000000",
addr_last => x"0000000000000000",
product => (
vendor_id => x"000000000000CE42", -- GSIx
device_id => x"fade1eaf", -- Time is always ticking!
version => x"00000001",
date => x"20111004",
name => "WB-Tics-Debugger ")));
constant c_dbg_irq_timer_sdb : t_sdb_device := (
abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"01",
wbd_endian => c_sdb_endian_big,
wbd_width => x"7", -- 8/16/32-bit port granularity
sdb_component => (
addr_first => x"0000000000000000",
addr_last => x"00000000000000ff",
product => (
vendor_id => x"0000000000000651", -- GSI
device_id => x"deadface", -- eventully "the dead line" is going to arrive
version => x"00000001",
date => x"20120308",
name => "IRQ_TIMER-Debugger ")));
constant c_xwb_dbg_slave_sdb : t_sdb_device := (
abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"00",
wbd_endian => c_sdb_endian_big,
wbd_width => x"7", -- 8/16/32-bit port granularity
sdb_component => (
addr_first => x"0000000000000000",
addr_last => x"000000000003ffff",
product => (
vendor_id => x"a1eBEEFc0ffeeBED", -- Jose Jimenez Motel. Open 24/7. Next exit.
device_id => x"c0a110de", -- obvious (sadly)
version => x"00000001",
date => x"20140704",
name => "Debugger-Slave ")));
------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
function f_xwb_dbg_dpram(g_size : natural) return t_sdb_device
is
variable result : t_sdb_device;
begin
result.abi_class := x"0001"; -- RAM device
result.abi_ver_major := x"01";
result.abi_ver_minor := x"00";
result.wbd_width := x"7"; -- 32/16/8-bit supported
result.wbd_endian := c_sdb_endian_big;
result.sdb_component.addr_first := (others => '0');
result.sdb_component.addr_last := std_logic_vector(to_unsigned(g_size*4-1, 64));
result.sdb_component.product.vendor_id := x"000000000000CE42"; -- CERN
result.sdb_component.product.device_id := x"deafbeef"; -- she didn't listen & is as essential as protein
result.sdb_component.product.version := x"00000001";
result.sdb_component.product.date := x"20120305";
result.sdb_component.product.name := "BlockRAM-Debugger ";
return result;
end f_xwb_dbg_dpram;
------------------------------------------------------------------------------
-- Components declaration
-------------------------------------------------------------------------------
component wb_debugger is
generic (
g_dbg_dpram_size : integer := 40960/4;
g_dbg_init_file : string;
g_reset_vector : t_wishbone_address := x"00000000";
g_msi_queues : natural := 1;
g_profile : string := "medium_icache_debug";
g_internal_time_ref : boolean := true;
g_timers : integer := 1;
g_slave_interface_mode : t_wishbone_interface_mode := PIPELINED;
g_slave_granularity : t_wishbone_address_granularity := BYTE
);
port (
clk_sys : in std_logic;
reset_n : in std_logic;
master_i : in t_wishbone_master_in;
master_o : out t_wishbone_master_out;
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out;
wrpc_uart_rxd_i : inout std_logic;
wrpc_uart_txd_o : inout std_logic;
uart_rxd_i : in std_logic;
uart_txd_o : out std_logic;
dbg_indicator : out std_logic;
dbg_control_select : in std_logic
);
end component;
end debugger_pkg;
package body debugger_pkg is
-- Notihg to include right now!!!
end debugger_pkg;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
-- Entity: memctrl
-- File: memctrl.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Memory controller package
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
library gaisler;
use gaisler.memctrl.all;
package memoryctrl is
component mctrl
generic (
hindex : integer := 0;
pindex : integer := 0;
romaddr : integer := 16#000#;
rommask : integer := 16#E00#;
ioaddr : integer := 16#200#;
iomask : integer := 16#E00#;
ramaddr : integer := 16#400#;
rammask : integer := 16#C00#;
paddr : integer := 0;
pmask : integer := 16#fff#;
wprot : integer := 0;
invclk : integer := 0;
fast : integer := 0;
romasel : integer := 28;
sdrasel : integer := 29;
srbanks : integer := 4;
ram8 : integer := 0;
ram16 : integer := 0;
sden : integer := 0;
sepbus : integer := 0;
sdbits : integer := 32;
sdlsb : integer := 2;
oepol : integer := 0;
syncrst : integer := 0;
pageburst : integer := 0;
scantest : integer := 0;
mobile : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
memi : in memory_in_type;
memo : out memory_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
wpo : in wprot_out_type;
sdo : out sdram_out_type
);
end component;
end;
|
-- NEED RESULT: ARCH00639.P1: Multi inertial transactions occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00639.P2: Multi inertial transactions occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00639.P3: Multi inertial transactions occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00639.P4: Multi inertial transactions occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00639.P5: Multi inertial transactions occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00639.P6: Multi inertial transactions occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00639.P7: Multi inertial transactions occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00639.P8: Multi inertial transactions occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00639.P9: Multi inertial transactions occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00639.P10: Multi inertial transactions occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00639.P11: Multi inertial transactions occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00639.P12: Multi inertial transactions occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00639.P13: Multi inertial transactions occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00639.P14: Multi inertial transactions occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00639.P15: Multi inertial transactions occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00639.P16: Multi inertial transactions occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00639.P17: Multi inertial transactions occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00639: One inertial transaction occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00639: One inertial transaction occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00639: One inertial transaction occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00639: One inertial transaction occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00639: One inertial transaction occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00639: One inertial transaction occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00639: One inertial transaction occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00639: One inertial transaction occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00639: One inertial transaction occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00639: One inertial transaction occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00639: One inertial transaction occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00639: One inertial transaction occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00639: One inertial transaction occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00639: One inertial transaction occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00639: One inertial transaction occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00639: One inertial transaction occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00639: One inertial transaction occurred on signal asg with slice name on LHS passed
-- NEED RESULT: P17: Inertial transactions entirely completed failed
-- NEED RESULT: P16: Inertial transactions entirely completed failed
-- NEED RESULT: P15: Inertial transactions entirely completed failed
-- NEED RESULT: P14: Inertial transactions entirely completed failed
-- NEED RESULT: P13: Inertial transactions entirely completed failed
-- NEED RESULT: P12: Inertial transactions entirely completed failed
-- NEED RESULT: P11: Inertial transactions entirely completed failed
-- NEED RESULT: P10: Inertial transactions entirely completed failed
-- NEED RESULT: P9: Inertial transactions entirely completed failed
-- NEED RESULT: P8: Inertial transactions entirely completed failed
-- NEED RESULT: P7: Inertial transactions entirely completed failed
-- NEED RESULT: P6: Inertial transactions entirely completed failed
-- NEED RESULT: P5: Inertial transactions entirely completed failed
-- NEED RESULT: P4: Inertial transactions entirely completed failed
-- NEED RESULT: P3: Inertial transactions entirely completed failed
-- NEED RESULT: P2: Inertial transactions entirely completed failed
-- NEED RESULT: P1: Inertial transactions entirely completed failed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00639
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 8.3 (1)
-- 8.3 (2)
-- 8.3 (4)
-- 8.3 (6)
-- 8.3.1 (4)
--
-- DESIGN UNIT ORDERING:
--
-- E00000(ARCH00639)
-- ENT00639_Test_Bench(ARCH00639_Test_Bench)
--
-- REVISION HISTORY:
--
-- 25-AUG-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
architecture ARCH00639 of E00000 is
subtype chk_sig_type is integer range -1 to 100 ;
signal chk_st_boolean_vector : chk_sig_type := -1 ;
signal chk_st_bit_vector : chk_sig_type := -1 ;
signal chk_st_severity_level_vector : chk_sig_type := -1 ;
signal chk_st_string : chk_sig_type := -1 ;
signal chk_st_enum1_vector : chk_sig_type := -1 ;
signal chk_st_integer_vector : chk_sig_type := -1 ;
signal chk_st_int1_vector : chk_sig_type := -1 ;
signal chk_st_time_vector : chk_sig_type := -1 ;
signal chk_st_phys1_vector : chk_sig_type := -1 ;
signal chk_st_real_vector : chk_sig_type := -1 ;
signal chk_st_real1_vector : chk_sig_type := -1 ;
signal chk_st_rec1_vector : chk_sig_type := -1 ;
signal chk_st_rec2_vector : chk_sig_type := -1 ;
signal chk_st_rec3_vector : chk_sig_type := -1 ;
signal chk_st_arr1_vector : chk_sig_type := -1 ;
signal chk_st_arr2_vector : chk_sig_type := -1 ;
signal chk_st_arr3_vector : chk_sig_type := -1 ;
--
signal s_st_boolean_vector : st_boolean_vector
:= c_st_boolean_vector_1 ;
signal s_st_bit_vector : st_bit_vector
:= c_st_bit_vector_1 ;
signal s_st_severity_level_vector : st_severity_level_vector
:= c_st_severity_level_vector_1 ;
signal s_st_string : st_string
:= c_st_string_1 ;
signal s_st_enum1_vector : st_enum1_vector
:= c_st_enum1_vector_1 ;
signal s_st_integer_vector : st_integer_vector
:= c_st_integer_vector_1 ;
signal s_st_int1_vector : st_int1_vector
:= c_st_int1_vector_1 ;
signal s_st_time_vector : st_time_vector
:= c_st_time_vector_1 ;
signal s_st_phys1_vector : st_phys1_vector
:= c_st_phys1_vector_1 ;
signal s_st_real_vector : st_real_vector
:= c_st_real_vector_1 ;
signal s_st_real1_vector : st_real1_vector
:= c_st_real1_vector_1 ;
signal s_st_rec1_vector : st_rec1_vector
:= c_st_rec1_vector_1 ;
signal s_st_rec2_vector : st_rec2_vector
:= c_st_rec2_vector_1 ;
signal s_st_rec3_vector : st_rec3_vector
:= c_st_rec3_vector_1 ;
signal s_st_arr1_vector : st_arr1_vector
:= c_st_arr1_vector_1 ;
signal s_st_arr2_vector : st_arr2_vector
:= c_st_arr2_vector_1 ;
signal s_st_arr3_vector : st_arr3_vector
:= c_st_arr3_vector_1 ;
--
begin
P1 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> (s_st_boolean_vector (lowb+1),
s_st_boolean_vector (lowb+2),
s_st_boolean_vector (lowb+3)) <=
c_st_boolean_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_boolean_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_boolean_vector (lowb+1 to lowb+3) =
c_st_boolean_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_boolean_vector (lowb+1 to lowb+3) =
c_st_boolean_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00639.P1" ,
"Multi inertial transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
(s_st_boolean_vector (lowb+1),
s_st_boolean_vector (lowb+2),
s_st_boolean_vector (lowb+3)) <=
c_st_boolean_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_boolean_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_boolean_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_boolean_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_boolean_vector (lowb+1 to lowb+3) =
c_st_boolean_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
(s_st_boolean_vector (lowb+1),
s_st_boolean_vector (lowb+2),
s_st_boolean_vector (lowb+3)) <=
c_st_boolean_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_boolean_vector (lowb+1 to lowb+3) =
c_st_boolean_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00639" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
(s_st_boolean_vector (lowb+1),
s_st_boolean_vector (lowb+2),
s_st_boolean_vector (lowb+3)) <= transport
c_st_boolean_vector_1 (lowb+1 to lowb+3) after 100 ns ;
--
when 5
=> correct :=
s_st_boolean_vector (lowb+1 to lowb+3) =
c_st_boolean_vector_1 (lowb+1 to lowb+3) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00639" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
(s_st_boolean_vector (lowb+1),
s_st_boolean_vector (lowb+2),
s_st_boolean_vector (lowb+3)) <=
c_st_boolean_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_boolean_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_boolean_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_boolean_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 6
=> correct :=
s_st_boolean_vector (lowb+1 to lowb+3) =
c_st_boolean_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00639" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
-- Last transaction above is marked by following
(s_st_boolean_vector (lowb+1),
s_st_boolean_vector (lowb+2),
s_st_boolean_vector (lowb+3)) <=
c_st_boolean_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 7
=> correct :=
s_st_boolean_vector (lowb+1 to lowb+3) =
c_st_boolean_vector_1 (lowb+1 to lowb+3) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_st_boolean_vector (lowb+1 to lowb+3) =
c_st_boolean_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00639" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00639" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_boolean_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
wait until (not s_st_boolean_vector'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P1 ;
--
PGEN_CHKP_1 :
process ( chk_st_boolean_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P1" ,
"Inertial transactions entirely completed",
chk_st_boolean_vector = 8 ) ;
end if ;
end process PGEN_CHKP_1 ;
--
P2 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> (s_st_bit_vector (lowb+1),
s_st_bit_vector (lowb+2),
s_st_bit_vector (lowb+3)) <=
c_st_bit_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_bit_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_bit_vector (lowb+1 to lowb+3) =
c_st_bit_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_bit_vector (lowb+1 to lowb+3) =
c_st_bit_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00639.P2" ,
"Multi inertial transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
(s_st_bit_vector (lowb+1),
s_st_bit_vector (lowb+2),
s_st_bit_vector (lowb+3)) <=
c_st_bit_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_bit_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_bit_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_bit_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_bit_vector (lowb+1 to lowb+3) =
c_st_bit_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
(s_st_bit_vector (lowb+1),
s_st_bit_vector (lowb+2),
s_st_bit_vector (lowb+3)) <=
c_st_bit_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_bit_vector (lowb+1 to lowb+3) =
c_st_bit_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00639" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
(s_st_bit_vector (lowb+1),
s_st_bit_vector (lowb+2),
s_st_bit_vector (lowb+3)) <= transport
c_st_bit_vector_1 (lowb+1 to lowb+3) after 100 ns ;
--
when 5
=> correct :=
s_st_bit_vector (lowb+1 to lowb+3) =
c_st_bit_vector_1 (lowb+1 to lowb+3) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00639" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
(s_st_bit_vector (lowb+1),
s_st_bit_vector (lowb+2),
s_st_bit_vector (lowb+3)) <=
c_st_bit_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_bit_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_bit_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_bit_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 6
=> correct :=
s_st_bit_vector (lowb+1 to lowb+3) =
c_st_bit_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00639" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
-- Last transaction above is marked by following
(s_st_bit_vector (lowb+1),
s_st_bit_vector (lowb+2),
s_st_bit_vector (lowb+3)) <=
c_st_bit_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 7
=> correct :=
s_st_bit_vector (lowb+1 to lowb+3) =
c_st_bit_vector_1 (lowb+1 to lowb+3) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_st_bit_vector (lowb+1 to lowb+3) =
c_st_bit_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00639" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00639" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_bit_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
wait until (not s_st_bit_vector'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P2 ;
--
PGEN_CHKP_2 :
process ( chk_st_bit_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P2" ,
"Inertial transactions entirely completed",
chk_st_bit_vector = 8 ) ;
end if ;
end process PGEN_CHKP_2 ;
--
P3 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> (s_st_severity_level_vector (lowb+1),
s_st_severity_level_vector (lowb+2),
s_st_severity_level_vector (lowb+3)) <=
c_st_severity_level_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_severity_level_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_severity_level_vector (lowb+1 to lowb+3) =
c_st_severity_level_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_severity_level_vector (lowb+1 to lowb+3) =
c_st_severity_level_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00639.P3" ,
"Multi inertial transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
(s_st_severity_level_vector (lowb+1),
s_st_severity_level_vector (lowb+2),
s_st_severity_level_vector (lowb+3)) <=
c_st_severity_level_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_severity_level_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_severity_level_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_severity_level_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_severity_level_vector (lowb+1 to lowb+3) =
c_st_severity_level_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
(s_st_severity_level_vector (lowb+1),
s_st_severity_level_vector (lowb+2),
s_st_severity_level_vector (lowb+3)) <=
c_st_severity_level_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_severity_level_vector (lowb+1 to lowb+3) =
c_st_severity_level_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00639" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
(s_st_severity_level_vector (lowb+1),
s_st_severity_level_vector (lowb+2),
s_st_severity_level_vector (lowb+3)) <= transport
c_st_severity_level_vector_1 (lowb+1 to lowb+3) after 100 ns ;
--
when 5
=> correct :=
s_st_severity_level_vector (lowb+1 to lowb+3) =
c_st_severity_level_vector_1 (lowb+1 to lowb+3) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00639" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
(s_st_severity_level_vector (lowb+1),
s_st_severity_level_vector (lowb+2),
s_st_severity_level_vector (lowb+3)) <=
c_st_severity_level_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_severity_level_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_severity_level_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_severity_level_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 6
=> correct :=
s_st_severity_level_vector (lowb+1 to lowb+3) =
c_st_severity_level_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00639" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
-- Last transaction above is marked by following
(s_st_severity_level_vector (lowb+1),
s_st_severity_level_vector (lowb+2),
s_st_severity_level_vector (lowb+3)) <=
c_st_severity_level_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 7
=> correct :=
s_st_severity_level_vector (lowb+1 to lowb+3) =
c_st_severity_level_vector_1 (lowb+1 to lowb+3) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_st_severity_level_vector (lowb+1 to lowb+3) =
c_st_severity_level_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00639" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00639" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_severity_level_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
wait until (not s_st_severity_level_vector'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P3 ;
--
PGEN_CHKP_3 :
process ( chk_st_severity_level_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P3" ,
"Inertial transactions entirely completed",
chk_st_severity_level_vector = 8 ) ;
end if ;
end process PGEN_CHKP_3 ;
--
P4 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> (s_st_string (lowb+1),
s_st_string (lowb+2),
s_st_string (lowb+3)) <=
c_st_string_2 (lowb+1 to lowb+3) after 10 ns,
c_st_string_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_string (lowb+1 to lowb+3) =
c_st_string_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_string (lowb+1 to lowb+3) =
c_st_string_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00639.P4" ,
"Multi inertial transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
(s_st_string (lowb+1),
s_st_string (lowb+2),
s_st_string (lowb+3)) <=
c_st_string_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_string_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_string_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_string_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_string (lowb+1 to lowb+3) =
c_st_string_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
(s_st_string (lowb+1),
s_st_string (lowb+2),
s_st_string (lowb+3)) <=
c_st_string_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_string (lowb+1 to lowb+3) =
c_st_string_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00639" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
(s_st_string (lowb+1),
s_st_string (lowb+2),
s_st_string (lowb+3)) <= transport
c_st_string_1 (lowb+1 to lowb+3) after 100 ns ;
--
when 5
=> correct :=
s_st_string (lowb+1 to lowb+3) =
c_st_string_1 (lowb+1 to lowb+3) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00639" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
(s_st_string (lowb+1),
s_st_string (lowb+2),
s_st_string (lowb+3)) <=
c_st_string_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_string_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_string_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_string_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 6
=> correct :=
s_st_string (lowb+1 to lowb+3) =
c_st_string_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00639" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
-- Last transaction above is marked by following
(s_st_string (lowb+1),
s_st_string (lowb+2),
s_st_string (lowb+3)) <=
c_st_string_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 7
=> correct :=
s_st_string (lowb+1 to lowb+3) =
c_st_string_1 (lowb+1 to lowb+3) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_st_string (lowb+1 to lowb+3) =
c_st_string_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00639" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00639" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_string <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
wait until (not s_st_string'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P4 ;
--
PGEN_CHKP_4 :
process ( chk_st_string )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P4" ,
"Inertial transactions entirely completed",
chk_st_string = 8 ) ;
end if ;
end process PGEN_CHKP_4 ;
--
P5 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> (s_st_enum1_vector (lowb+1),
s_st_enum1_vector (lowb+2),
s_st_enum1_vector (lowb+3)) <=
c_st_enum1_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_enum1_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_enum1_vector (lowb+1 to lowb+3) =
c_st_enum1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_enum1_vector (lowb+1 to lowb+3) =
c_st_enum1_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00639.P5" ,
"Multi inertial transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
(s_st_enum1_vector (lowb+1),
s_st_enum1_vector (lowb+2),
s_st_enum1_vector (lowb+3)) <=
c_st_enum1_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_enum1_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_enum1_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_enum1_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_enum1_vector (lowb+1 to lowb+3) =
c_st_enum1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
(s_st_enum1_vector (lowb+1),
s_st_enum1_vector (lowb+2),
s_st_enum1_vector (lowb+3)) <=
c_st_enum1_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_enum1_vector (lowb+1 to lowb+3) =
c_st_enum1_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00639" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
(s_st_enum1_vector (lowb+1),
s_st_enum1_vector (lowb+2),
s_st_enum1_vector (lowb+3)) <= transport
c_st_enum1_vector_1 (lowb+1 to lowb+3) after 100 ns ;
--
when 5
=> correct :=
s_st_enum1_vector (lowb+1 to lowb+3) =
c_st_enum1_vector_1 (lowb+1 to lowb+3) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00639" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
(s_st_enum1_vector (lowb+1),
s_st_enum1_vector (lowb+2),
s_st_enum1_vector (lowb+3)) <=
c_st_enum1_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_enum1_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_enum1_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_enum1_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 6
=> correct :=
s_st_enum1_vector (lowb+1 to lowb+3) =
c_st_enum1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00639" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
-- Last transaction above is marked by following
(s_st_enum1_vector (lowb+1),
s_st_enum1_vector (lowb+2),
s_st_enum1_vector (lowb+3)) <=
c_st_enum1_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 7
=> correct :=
s_st_enum1_vector (lowb+1 to lowb+3) =
c_st_enum1_vector_1 (lowb+1 to lowb+3) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_st_enum1_vector (lowb+1 to lowb+3) =
c_st_enum1_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00639" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00639" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_enum1_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
wait until (not s_st_enum1_vector'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P5 ;
--
PGEN_CHKP_5 :
process ( chk_st_enum1_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P5" ,
"Inertial transactions entirely completed",
chk_st_enum1_vector = 8 ) ;
end if ;
end process PGEN_CHKP_5 ;
--
P6 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> (s_st_integer_vector (lowb+1),
s_st_integer_vector (lowb+2),
s_st_integer_vector (lowb+3)) <=
c_st_integer_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_integer_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_integer_vector (lowb+1 to lowb+3) =
c_st_integer_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_integer_vector (lowb+1 to lowb+3) =
c_st_integer_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00639.P6" ,
"Multi inertial transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
(s_st_integer_vector (lowb+1),
s_st_integer_vector (lowb+2),
s_st_integer_vector (lowb+3)) <=
c_st_integer_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_integer_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_integer_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_integer_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_integer_vector (lowb+1 to lowb+3) =
c_st_integer_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
(s_st_integer_vector (lowb+1),
s_st_integer_vector (lowb+2),
s_st_integer_vector (lowb+3)) <=
c_st_integer_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_integer_vector (lowb+1 to lowb+3) =
c_st_integer_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00639" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
(s_st_integer_vector (lowb+1),
s_st_integer_vector (lowb+2),
s_st_integer_vector (lowb+3)) <= transport
c_st_integer_vector_1 (lowb+1 to lowb+3) after 100 ns ;
--
when 5
=> correct :=
s_st_integer_vector (lowb+1 to lowb+3) =
c_st_integer_vector_1 (lowb+1 to lowb+3) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00639" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
(s_st_integer_vector (lowb+1),
s_st_integer_vector (lowb+2),
s_st_integer_vector (lowb+3)) <=
c_st_integer_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_integer_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_integer_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_integer_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 6
=> correct :=
s_st_integer_vector (lowb+1 to lowb+3) =
c_st_integer_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00639" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
-- Last transaction above is marked by following
(s_st_integer_vector (lowb+1),
s_st_integer_vector (lowb+2),
s_st_integer_vector (lowb+3)) <=
c_st_integer_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 7
=> correct :=
s_st_integer_vector (lowb+1 to lowb+3) =
c_st_integer_vector_1 (lowb+1 to lowb+3) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_st_integer_vector (lowb+1 to lowb+3) =
c_st_integer_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00639" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00639" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_integer_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
wait until (not s_st_integer_vector'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P6 ;
--
PGEN_CHKP_6 :
process ( chk_st_integer_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P6" ,
"Inertial transactions entirely completed",
chk_st_integer_vector = 8 ) ;
end if ;
end process PGEN_CHKP_6 ;
--
P7 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> (s_st_int1_vector (lowb+1),
s_st_int1_vector (lowb+2),
s_st_int1_vector (lowb+3)) <=
c_st_int1_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_int1_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_int1_vector (lowb+1 to lowb+3) =
c_st_int1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_int1_vector (lowb+1 to lowb+3) =
c_st_int1_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00639.P7" ,
"Multi inertial transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
(s_st_int1_vector (lowb+1),
s_st_int1_vector (lowb+2),
s_st_int1_vector (lowb+3)) <=
c_st_int1_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_int1_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_int1_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_int1_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_int1_vector (lowb+1 to lowb+3) =
c_st_int1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
(s_st_int1_vector (lowb+1),
s_st_int1_vector (lowb+2),
s_st_int1_vector (lowb+3)) <=
c_st_int1_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_int1_vector (lowb+1 to lowb+3) =
c_st_int1_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00639" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
(s_st_int1_vector (lowb+1),
s_st_int1_vector (lowb+2),
s_st_int1_vector (lowb+3)) <= transport
c_st_int1_vector_1 (lowb+1 to lowb+3) after 100 ns ;
--
when 5
=> correct :=
s_st_int1_vector (lowb+1 to lowb+3) =
c_st_int1_vector_1 (lowb+1 to lowb+3) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00639" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
(s_st_int1_vector (lowb+1),
s_st_int1_vector (lowb+2),
s_st_int1_vector (lowb+3)) <=
c_st_int1_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_int1_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_int1_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_int1_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 6
=> correct :=
s_st_int1_vector (lowb+1 to lowb+3) =
c_st_int1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00639" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
-- Last transaction above is marked by following
(s_st_int1_vector (lowb+1),
s_st_int1_vector (lowb+2),
s_st_int1_vector (lowb+3)) <=
c_st_int1_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 7
=> correct :=
s_st_int1_vector (lowb+1 to lowb+3) =
c_st_int1_vector_1 (lowb+1 to lowb+3) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_st_int1_vector (lowb+1 to lowb+3) =
c_st_int1_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00639" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00639" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_int1_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
wait until (not s_st_int1_vector'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P7 ;
--
PGEN_CHKP_7 :
process ( chk_st_int1_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P7" ,
"Inertial transactions entirely completed",
chk_st_int1_vector = 8 ) ;
end if ;
end process PGEN_CHKP_7 ;
--
P8 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> (s_st_time_vector (lowb+1),
s_st_time_vector (lowb+2),
s_st_time_vector (lowb+3)) <=
c_st_time_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_time_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_time_vector (lowb+1 to lowb+3) =
c_st_time_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_time_vector (lowb+1 to lowb+3) =
c_st_time_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00639.P8" ,
"Multi inertial transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
(s_st_time_vector (lowb+1),
s_st_time_vector (lowb+2),
s_st_time_vector (lowb+3)) <=
c_st_time_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_time_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_time_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_time_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_time_vector (lowb+1 to lowb+3) =
c_st_time_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
(s_st_time_vector (lowb+1),
s_st_time_vector (lowb+2),
s_st_time_vector (lowb+3)) <=
c_st_time_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_time_vector (lowb+1 to lowb+3) =
c_st_time_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00639" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
(s_st_time_vector (lowb+1),
s_st_time_vector (lowb+2),
s_st_time_vector (lowb+3)) <= transport
c_st_time_vector_1 (lowb+1 to lowb+3) after 100 ns ;
--
when 5
=> correct :=
s_st_time_vector (lowb+1 to lowb+3) =
c_st_time_vector_1 (lowb+1 to lowb+3) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00639" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
(s_st_time_vector (lowb+1),
s_st_time_vector (lowb+2),
s_st_time_vector (lowb+3)) <=
c_st_time_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_time_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_time_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_time_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 6
=> correct :=
s_st_time_vector (lowb+1 to lowb+3) =
c_st_time_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00639" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
-- Last transaction above is marked by following
(s_st_time_vector (lowb+1),
s_st_time_vector (lowb+2),
s_st_time_vector (lowb+3)) <=
c_st_time_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 7
=> correct :=
s_st_time_vector (lowb+1 to lowb+3) =
c_st_time_vector_1 (lowb+1 to lowb+3) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_st_time_vector (lowb+1 to lowb+3) =
c_st_time_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00639" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00639" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_time_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
wait until (not s_st_time_vector'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P8 ;
--
PGEN_CHKP_8 :
process ( chk_st_time_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P8" ,
"Inertial transactions entirely completed",
chk_st_time_vector = 8 ) ;
end if ;
end process PGEN_CHKP_8 ;
--
P9 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> (s_st_phys1_vector (lowb+1),
s_st_phys1_vector (lowb+2),
s_st_phys1_vector (lowb+3)) <=
c_st_phys1_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_phys1_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_phys1_vector (lowb+1 to lowb+3) =
c_st_phys1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_phys1_vector (lowb+1 to lowb+3) =
c_st_phys1_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00639.P9" ,
"Multi inertial transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
(s_st_phys1_vector (lowb+1),
s_st_phys1_vector (lowb+2),
s_st_phys1_vector (lowb+3)) <=
c_st_phys1_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_phys1_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_phys1_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_phys1_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_phys1_vector (lowb+1 to lowb+3) =
c_st_phys1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
(s_st_phys1_vector (lowb+1),
s_st_phys1_vector (lowb+2),
s_st_phys1_vector (lowb+3)) <=
c_st_phys1_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_phys1_vector (lowb+1 to lowb+3) =
c_st_phys1_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00639" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
(s_st_phys1_vector (lowb+1),
s_st_phys1_vector (lowb+2),
s_st_phys1_vector (lowb+3)) <= transport
c_st_phys1_vector_1 (lowb+1 to lowb+3) after 100 ns ;
--
when 5
=> correct :=
s_st_phys1_vector (lowb+1 to lowb+3) =
c_st_phys1_vector_1 (lowb+1 to lowb+3) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00639" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
(s_st_phys1_vector (lowb+1),
s_st_phys1_vector (lowb+2),
s_st_phys1_vector (lowb+3)) <=
c_st_phys1_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_phys1_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_phys1_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_phys1_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 6
=> correct :=
s_st_phys1_vector (lowb+1 to lowb+3) =
c_st_phys1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00639" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
-- Last transaction above is marked by following
(s_st_phys1_vector (lowb+1),
s_st_phys1_vector (lowb+2),
s_st_phys1_vector (lowb+3)) <=
c_st_phys1_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 7
=> correct :=
s_st_phys1_vector (lowb+1 to lowb+3) =
c_st_phys1_vector_1 (lowb+1 to lowb+3) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_st_phys1_vector (lowb+1 to lowb+3) =
c_st_phys1_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00639" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00639" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_phys1_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
wait until (not s_st_phys1_vector'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P9 ;
--
PGEN_CHKP_9 :
process ( chk_st_phys1_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P9" ,
"Inertial transactions entirely completed",
chk_st_phys1_vector = 8 ) ;
end if ;
end process PGEN_CHKP_9 ;
--
P10 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> (s_st_real_vector (lowb+1),
s_st_real_vector (lowb+2),
s_st_real_vector (lowb+3)) <=
c_st_real_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_real_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_real_vector (lowb+1 to lowb+3) =
c_st_real_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_real_vector (lowb+1 to lowb+3) =
c_st_real_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00639.P10" ,
"Multi inertial transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
(s_st_real_vector (lowb+1),
s_st_real_vector (lowb+2),
s_st_real_vector (lowb+3)) <=
c_st_real_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_real_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_real_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_real_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_real_vector (lowb+1 to lowb+3) =
c_st_real_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
(s_st_real_vector (lowb+1),
s_st_real_vector (lowb+2),
s_st_real_vector (lowb+3)) <=
c_st_real_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_real_vector (lowb+1 to lowb+3) =
c_st_real_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00639" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
(s_st_real_vector (lowb+1),
s_st_real_vector (lowb+2),
s_st_real_vector (lowb+3)) <= transport
c_st_real_vector_1 (lowb+1 to lowb+3) after 100 ns ;
--
when 5
=> correct :=
s_st_real_vector (lowb+1 to lowb+3) =
c_st_real_vector_1 (lowb+1 to lowb+3) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00639" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
(s_st_real_vector (lowb+1),
s_st_real_vector (lowb+2),
s_st_real_vector (lowb+3)) <=
c_st_real_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_real_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_real_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_real_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 6
=> correct :=
s_st_real_vector (lowb+1 to lowb+3) =
c_st_real_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00639" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
-- Last transaction above is marked by following
(s_st_real_vector (lowb+1),
s_st_real_vector (lowb+2),
s_st_real_vector (lowb+3)) <=
c_st_real_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 7
=> correct :=
s_st_real_vector (lowb+1 to lowb+3) =
c_st_real_vector_1 (lowb+1 to lowb+3) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_st_real_vector (lowb+1 to lowb+3) =
c_st_real_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00639" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00639" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_real_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
wait until (not s_st_real_vector'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P10 ;
--
PGEN_CHKP_10 :
process ( chk_st_real_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P10" ,
"Inertial transactions entirely completed",
chk_st_real_vector = 8 ) ;
end if ;
end process PGEN_CHKP_10 ;
--
P11 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> (s_st_real1_vector (lowb+1),
s_st_real1_vector (lowb+2),
s_st_real1_vector (lowb+3)) <=
c_st_real1_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_real1_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_real1_vector (lowb+1 to lowb+3) =
c_st_real1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_real1_vector (lowb+1 to lowb+3) =
c_st_real1_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00639.P11" ,
"Multi inertial transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
(s_st_real1_vector (lowb+1),
s_st_real1_vector (lowb+2),
s_st_real1_vector (lowb+3)) <=
c_st_real1_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_real1_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_real1_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_real1_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_real1_vector (lowb+1 to lowb+3) =
c_st_real1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
(s_st_real1_vector (lowb+1),
s_st_real1_vector (lowb+2),
s_st_real1_vector (lowb+3)) <=
c_st_real1_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_real1_vector (lowb+1 to lowb+3) =
c_st_real1_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00639" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
(s_st_real1_vector (lowb+1),
s_st_real1_vector (lowb+2),
s_st_real1_vector (lowb+3)) <= transport
c_st_real1_vector_1 (lowb+1 to lowb+3) after 100 ns ;
--
when 5
=> correct :=
s_st_real1_vector (lowb+1 to lowb+3) =
c_st_real1_vector_1 (lowb+1 to lowb+3) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00639" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
(s_st_real1_vector (lowb+1),
s_st_real1_vector (lowb+2),
s_st_real1_vector (lowb+3)) <=
c_st_real1_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_real1_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_real1_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_real1_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 6
=> correct :=
s_st_real1_vector (lowb+1 to lowb+3) =
c_st_real1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00639" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
-- Last transaction above is marked by following
(s_st_real1_vector (lowb+1),
s_st_real1_vector (lowb+2),
s_st_real1_vector (lowb+3)) <=
c_st_real1_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 7
=> correct :=
s_st_real1_vector (lowb+1 to lowb+3) =
c_st_real1_vector_1 (lowb+1 to lowb+3) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_st_real1_vector (lowb+1 to lowb+3) =
c_st_real1_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00639" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00639" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_real1_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
wait until (not s_st_real1_vector'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P11 ;
--
PGEN_CHKP_11 :
process ( chk_st_real1_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P11" ,
"Inertial transactions entirely completed",
chk_st_real1_vector = 8 ) ;
end if ;
end process PGEN_CHKP_11 ;
--
P12 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> (s_st_rec1_vector (lowb+1),
s_st_rec1_vector (lowb+2),
s_st_rec1_vector (lowb+3)) <=
c_st_rec1_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_rec1_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_rec1_vector (lowb+1 to lowb+3) =
c_st_rec1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec1_vector (lowb+1 to lowb+3) =
c_st_rec1_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00639.P12" ,
"Multi inertial transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
(s_st_rec1_vector (lowb+1),
s_st_rec1_vector (lowb+2),
s_st_rec1_vector (lowb+3)) <=
c_st_rec1_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_rec1_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_rec1_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_rec1_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_rec1_vector (lowb+1 to lowb+3) =
c_st_rec1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
(s_st_rec1_vector (lowb+1),
s_st_rec1_vector (lowb+2),
s_st_rec1_vector (lowb+3)) <=
c_st_rec1_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec1_vector (lowb+1 to lowb+3) =
c_st_rec1_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00639" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
(s_st_rec1_vector (lowb+1),
s_st_rec1_vector (lowb+2),
s_st_rec1_vector (lowb+3)) <= transport
c_st_rec1_vector_1 (lowb+1 to lowb+3) after 100 ns ;
--
when 5
=> correct :=
s_st_rec1_vector (lowb+1 to lowb+3) =
c_st_rec1_vector_1 (lowb+1 to lowb+3) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00639" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
(s_st_rec1_vector (lowb+1),
s_st_rec1_vector (lowb+2),
s_st_rec1_vector (lowb+3)) <=
c_st_rec1_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_rec1_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_rec1_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_rec1_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 6
=> correct :=
s_st_rec1_vector (lowb+1 to lowb+3) =
c_st_rec1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00639" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
-- Last transaction above is marked by following
(s_st_rec1_vector (lowb+1),
s_st_rec1_vector (lowb+2),
s_st_rec1_vector (lowb+3)) <=
c_st_rec1_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 7
=> correct :=
s_st_rec1_vector (lowb+1 to lowb+3) =
c_st_rec1_vector_1 (lowb+1 to lowb+3) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_st_rec1_vector (lowb+1 to lowb+3) =
c_st_rec1_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00639" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00639" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_rec1_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
wait until (not s_st_rec1_vector'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P12 ;
--
PGEN_CHKP_12 :
process ( chk_st_rec1_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P12" ,
"Inertial transactions entirely completed",
chk_st_rec1_vector = 8 ) ;
end if ;
end process PGEN_CHKP_12 ;
--
P13 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> (s_st_rec2_vector (lowb+1),
s_st_rec2_vector (lowb+2),
s_st_rec2_vector (lowb+3)) <=
c_st_rec2_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_rec2_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_rec2_vector (lowb+1 to lowb+3) =
c_st_rec2_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec2_vector (lowb+1 to lowb+3) =
c_st_rec2_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00639.P13" ,
"Multi inertial transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
(s_st_rec2_vector (lowb+1),
s_st_rec2_vector (lowb+2),
s_st_rec2_vector (lowb+3)) <=
c_st_rec2_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_rec2_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_rec2_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_rec2_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_rec2_vector (lowb+1 to lowb+3) =
c_st_rec2_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
(s_st_rec2_vector (lowb+1),
s_st_rec2_vector (lowb+2),
s_st_rec2_vector (lowb+3)) <=
c_st_rec2_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec2_vector (lowb+1 to lowb+3) =
c_st_rec2_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00639" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
(s_st_rec2_vector (lowb+1),
s_st_rec2_vector (lowb+2),
s_st_rec2_vector (lowb+3)) <= transport
c_st_rec2_vector_1 (lowb+1 to lowb+3) after 100 ns ;
--
when 5
=> correct :=
s_st_rec2_vector (lowb+1 to lowb+3) =
c_st_rec2_vector_1 (lowb+1 to lowb+3) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00639" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
(s_st_rec2_vector (lowb+1),
s_st_rec2_vector (lowb+2),
s_st_rec2_vector (lowb+3)) <=
c_st_rec2_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_rec2_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_rec2_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_rec2_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 6
=> correct :=
s_st_rec2_vector (lowb+1 to lowb+3) =
c_st_rec2_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00639" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
-- Last transaction above is marked by following
(s_st_rec2_vector (lowb+1),
s_st_rec2_vector (lowb+2),
s_st_rec2_vector (lowb+3)) <=
c_st_rec2_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 7
=> correct :=
s_st_rec2_vector (lowb+1 to lowb+3) =
c_st_rec2_vector_1 (lowb+1 to lowb+3) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_st_rec2_vector (lowb+1 to lowb+3) =
c_st_rec2_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00639" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00639" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_rec2_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
wait until (not s_st_rec2_vector'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P13 ;
--
PGEN_CHKP_13 :
process ( chk_st_rec2_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P13" ,
"Inertial transactions entirely completed",
chk_st_rec2_vector = 8 ) ;
end if ;
end process PGEN_CHKP_13 ;
--
P14 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> (s_st_rec3_vector (lowb+1),
s_st_rec3_vector (lowb+2),
s_st_rec3_vector (lowb+3)) <=
c_st_rec3_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_rec3_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_rec3_vector (lowb+1 to lowb+3) =
c_st_rec3_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec3_vector (lowb+1 to lowb+3) =
c_st_rec3_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00639.P14" ,
"Multi inertial transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
(s_st_rec3_vector (lowb+1),
s_st_rec3_vector (lowb+2),
s_st_rec3_vector (lowb+3)) <=
c_st_rec3_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_rec3_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_rec3_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_rec3_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_rec3_vector (lowb+1 to lowb+3) =
c_st_rec3_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
(s_st_rec3_vector (lowb+1),
s_st_rec3_vector (lowb+2),
s_st_rec3_vector (lowb+3)) <=
c_st_rec3_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec3_vector (lowb+1 to lowb+3) =
c_st_rec3_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00639" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
(s_st_rec3_vector (lowb+1),
s_st_rec3_vector (lowb+2),
s_st_rec3_vector (lowb+3)) <= transport
c_st_rec3_vector_1 (lowb+1 to lowb+3) after 100 ns ;
--
when 5
=> correct :=
s_st_rec3_vector (lowb+1 to lowb+3) =
c_st_rec3_vector_1 (lowb+1 to lowb+3) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00639" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
(s_st_rec3_vector (lowb+1),
s_st_rec3_vector (lowb+2),
s_st_rec3_vector (lowb+3)) <=
c_st_rec3_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_rec3_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_rec3_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_rec3_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 6
=> correct :=
s_st_rec3_vector (lowb+1 to lowb+3) =
c_st_rec3_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00639" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
-- Last transaction above is marked by following
(s_st_rec3_vector (lowb+1),
s_st_rec3_vector (lowb+2),
s_st_rec3_vector (lowb+3)) <=
c_st_rec3_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 7
=> correct :=
s_st_rec3_vector (lowb+1 to lowb+3) =
c_st_rec3_vector_1 (lowb+1 to lowb+3) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_st_rec3_vector (lowb+1 to lowb+3) =
c_st_rec3_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00639" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00639" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_rec3_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
wait until (not s_st_rec3_vector'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P14 ;
--
PGEN_CHKP_14 :
process ( chk_st_rec3_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P14" ,
"Inertial transactions entirely completed",
chk_st_rec3_vector = 8 ) ;
end if ;
end process PGEN_CHKP_14 ;
--
P15 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> (s_st_arr1_vector (lowb+1),
s_st_arr1_vector (lowb+2),
s_st_arr1_vector (lowb+3)) <=
c_st_arr1_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_arr1_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_arr1_vector (lowb+1 to lowb+3) =
c_st_arr1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_arr1_vector (lowb+1 to lowb+3) =
c_st_arr1_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00639.P15" ,
"Multi inertial transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
(s_st_arr1_vector (lowb+1),
s_st_arr1_vector (lowb+2),
s_st_arr1_vector (lowb+3)) <=
c_st_arr1_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_arr1_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_arr1_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_arr1_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_arr1_vector (lowb+1 to lowb+3) =
c_st_arr1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
(s_st_arr1_vector (lowb+1),
s_st_arr1_vector (lowb+2),
s_st_arr1_vector (lowb+3)) <=
c_st_arr1_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_arr1_vector (lowb+1 to lowb+3) =
c_st_arr1_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00639" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
(s_st_arr1_vector (lowb+1),
s_st_arr1_vector (lowb+2),
s_st_arr1_vector (lowb+3)) <= transport
c_st_arr1_vector_1 (lowb+1 to lowb+3) after 100 ns ;
--
when 5
=> correct :=
s_st_arr1_vector (lowb+1 to lowb+3) =
c_st_arr1_vector_1 (lowb+1 to lowb+3) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00639" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
(s_st_arr1_vector (lowb+1),
s_st_arr1_vector (lowb+2),
s_st_arr1_vector (lowb+3)) <=
c_st_arr1_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_arr1_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_arr1_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_arr1_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 6
=> correct :=
s_st_arr1_vector (lowb+1 to lowb+3) =
c_st_arr1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00639" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
-- Last transaction above is marked by following
(s_st_arr1_vector (lowb+1),
s_st_arr1_vector (lowb+2),
s_st_arr1_vector (lowb+3)) <=
c_st_arr1_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 7
=> correct :=
s_st_arr1_vector (lowb+1 to lowb+3) =
c_st_arr1_vector_1 (lowb+1 to lowb+3) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_st_arr1_vector (lowb+1 to lowb+3) =
c_st_arr1_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00639" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00639" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_arr1_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
wait until (not s_st_arr1_vector'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P15 ;
--
PGEN_CHKP_15 :
process ( chk_st_arr1_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P15" ,
"Inertial transactions entirely completed",
chk_st_arr1_vector = 8 ) ;
end if ;
end process PGEN_CHKP_15 ;
--
P16 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> (s_st_arr2_vector (lowb+1),
s_st_arr2_vector (lowb+2),
s_st_arr2_vector (lowb+3)) <=
c_st_arr2_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_arr2_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_arr2_vector (lowb+1 to lowb+3) =
c_st_arr2_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_arr2_vector (lowb+1 to lowb+3) =
c_st_arr2_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00639.P16" ,
"Multi inertial transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
(s_st_arr2_vector (lowb+1),
s_st_arr2_vector (lowb+2),
s_st_arr2_vector (lowb+3)) <=
c_st_arr2_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_arr2_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_arr2_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_arr2_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_arr2_vector (lowb+1 to lowb+3) =
c_st_arr2_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
(s_st_arr2_vector (lowb+1),
s_st_arr2_vector (lowb+2),
s_st_arr2_vector (lowb+3)) <=
c_st_arr2_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_arr2_vector (lowb+1 to lowb+3) =
c_st_arr2_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00639" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
(s_st_arr2_vector (lowb+1),
s_st_arr2_vector (lowb+2),
s_st_arr2_vector (lowb+3)) <= transport
c_st_arr2_vector_1 (lowb+1 to lowb+3) after 100 ns ;
--
when 5
=> correct :=
s_st_arr2_vector (lowb+1 to lowb+3) =
c_st_arr2_vector_1 (lowb+1 to lowb+3) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00639" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
(s_st_arr2_vector (lowb+1),
s_st_arr2_vector (lowb+2),
s_st_arr2_vector (lowb+3)) <=
c_st_arr2_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_arr2_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_arr2_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_arr2_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 6
=> correct :=
s_st_arr2_vector (lowb+1 to lowb+3) =
c_st_arr2_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00639" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
-- Last transaction above is marked by following
(s_st_arr2_vector (lowb+1),
s_st_arr2_vector (lowb+2),
s_st_arr2_vector (lowb+3)) <=
c_st_arr2_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 7
=> correct :=
s_st_arr2_vector (lowb+1 to lowb+3) =
c_st_arr2_vector_1 (lowb+1 to lowb+3) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_st_arr2_vector (lowb+1 to lowb+3) =
c_st_arr2_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00639" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00639" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_arr2_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
wait until (not s_st_arr2_vector'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P16 ;
--
PGEN_CHKP_16 :
process ( chk_st_arr2_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P16" ,
"Inertial transactions entirely completed",
chk_st_arr2_vector = 8 ) ;
end if ;
end process PGEN_CHKP_16 ;
--
P17 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> (s_st_arr3_vector (lowb+1),
s_st_arr3_vector (lowb+2),
s_st_arr3_vector (lowb+3)) <=
c_st_arr3_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_arr3_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_arr3_vector (lowb+1 to lowb+3) =
c_st_arr3_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_arr3_vector (lowb+1 to lowb+3) =
c_st_arr3_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00639.P17" ,
"Multi inertial transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
(s_st_arr3_vector (lowb+1),
s_st_arr3_vector (lowb+2),
s_st_arr3_vector (lowb+3)) <=
c_st_arr3_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_arr3_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_arr3_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_arr3_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_arr3_vector (lowb+1 to lowb+3) =
c_st_arr3_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
(s_st_arr3_vector (lowb+1),
s_st_arr3_vector (lowb+2),
s_st_arr3_vector (lowb+3)) <=
c_st_arr3_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_arr3_vector (lowb+1 to lowb+3) =
c_st_arr3_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00639" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
(s_st_arr3_vector (lowb+1),
s_st_arr3_vector (lowb+2),
s_st_arr3_vector (lowb+3)) <= transport
c_st_arr3_vector_1 (lowb+1 to lowb+3) after 100 ns ;
--
when 5
=> correct :=
s_st_arr3_vector (lowb+1 to lowb+3) =
c_st_arr3_vector_1 (lowb+1 to lowb+3) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00639" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
(s_st_arr3_vector (lowb+1),
s_st_arr3_vector (lowb+2),
s_st_arr3_vector (lowb+3)) <=
c_st_arr3_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_arr3_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_arr3_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_arr3_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 6
=> correct :=
s_st_arr3_vector (lowb+1 to lowb+3) =
c_st_arr3_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00639" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
-- Last transaction above is marked by following
(s_st_arr3_vector (lowb+1),
s_st_arr3_vector (lowb+2),
s_st_arr3_vector (lowb+3)) <=
c_st_arr3_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 7
=> correct :=
s_st_arr3_vector (lowb+1 to lowb+3) =
c_st_arr3_vector_1 (lowb+1 to lowb+3) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_st_arr3_vector (lowb+1 to lowb+3) =
c_st_arr3_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00639" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00639" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_arr3_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
wait until (not s_st_arr3_vector'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P17 ;
--
PGEN_CHKP_17 :
process ( chk_st_arr3_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P17" ,
"Inertial transactions entirely completed",
chk_st_arr3_vector = 8 ) ;
end if ;
end process PGEN_CHKP_17 ;
--
--
end ARCH00639 ;
--
entity ENT00639_Test_Bench is
end ENT00639_Test_Bench ;
--
architecture ARCH00639_Test_Bench of ENT00639_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.E00000 ( ARCH00639 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00639_Test_Bench ;
|
-------------------------------------------------------------------------------
-- Title : Exercise
-- Project : Counter
-------------------------------------------------------------------------------
-- File : ff3_rtl.vhd
-- Author : Martin Angermair
-- Company : Technikum Wien, Embedded Systems
-- Last update: 24.10.2017
-- Platform : ModelSim
-------------------------------------------------------------------------------
-- Description: This is the entity declaration of the fulladder submodule
-- of the VHDL class example.
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 24.10.2017 0.1 Martin Angermair init
-------------------------------------------------------------------------------
architecture rtl of ff is
begin
p_ff3: process(clk_i, reset_i)
begin
if reset_i = '1' then
qout_o <= '0';
elsif clk_i'event and clk_i = '1' then
qout_o <= data_i;
end if;
end process p_ff3;
end rtl;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity hfrisc_soc is
generic(
address_width: integer := 14;
memory_file : string := "code.txt"
);
port ( clk_i: in std_logic;
rst_i: in std_logic;
-- external SRAM / EEPROM SPI interface
spi_ssn_o: out std_logic;
spi_ssn2_o: out std_logic;
spi_clk_o: out std_logic;
spi_mosi_o: out std_logic;
spi_miso_i: in std_logic;
-- GPIO port A
gpioa_in: in std_logic_vector(15 downto 0);
gpioa_out: out std_logic_vector(15 downto 0);
gpioa_ddr: out std_logic_vector(15 downto 0);
-- GPIO port B
gpiob_in: in std_logic_vector(15 downto 0);
gpiob_out: out std_logic_vector(15 downto 0);
gpiob_ddr: out std_logic_vector(15 downto 0)
);
end hfrisc_soc;
architecture top_level of hfrisc_soc is
signal clock, boot_enable, boot_enable_n, ram_enable_n, stall_sig, ram_dly, rff1, reset: std_logic;
signal address, data_read, data_write, data_read_boot, data_read_ram: std_logic_vector(31 downto 0);
signal ext_irq: std_logic_vector(7 downto 0);
signal data_we, data_w_n_ram: std_logic_vector(3 downto 0);
signal periph, periph_dly, periph_wr, periph_irq: std_logic;
signal data_read_periph, data_read_periph_s, data_write_periph: std_logic_vector(31 downto 0);
signal data_read_spi: std_logic_vector(31 downto 0);
signal data_mode: std_logic_vector(2 downto 0);
signal burst, wr, rd, we, stall_dly, stall_dly2, stall_spi, spi_sel, spi_cs_n_s: std_logic := '0';
begin
-- clock divider (25MHz clock from 50MHz main clock for Spartan3 Starter Kit)
process (rst_i, clk_i, clock)
begin
if rst_i = '1' then
clock <= '0';
else
if clk_i'event and clk_i = '1' then
clock <= not clock;
end if;
end if;
end process;
-- reset synchronizer
process (clock, rst_i)
begin
if (rst_i = '1') then
rff1 <= '1';
reset <= '1';
elsif (clock'event and clock = '1') then
rff1 <= '0';
reset <= rff1;
end if;
end process;
process (clock, reset, stall_spi)
begin
if reset = '1' then
ram_dly <= '0';
periph_dly <= '0';
stall_dly <= '0';
stall_dly2 <= '0';
elsif clock'event and clock = '1' then
ram_dly <= not ram_enable_n;
periph_dly <= periph;
stall_dly <= stall_spi;
stall_dly2 <= stall_dly;
end if;
end process;
boot_enable_n <= '0' when (address(31 downto 28) = "0000" and stall_sig = '0') else '1';
ram_enable_n <= '0' when (address(31 downto 28) = "0100" and stall_sig = '0') else '1';
spi_sel <= '1' when address(31 downto 28) = "0011" else '0';
rd <= '1' when (spi_sel = '1' and data_we = "0000" and stall_dly2 = '0') else '0';
wr <= '1' when (spi_sel = '1' and data_we /= "0000" and stall_dly2 = '0') else '0';
data_read <= data_read_periph when periph = '1' or periph_dly = '1' else data_read_spi when spi_sel = '1' or stall_dly2 = '1' else
data_read_boot when address(31 downto 28) = "0000" and ram_dly = '0' else data_read_ram;
data_w_n_ram <= not data_we;
burst <= '0';
stall_sig <= stall_spi;
-- external SPI SRAM/EEPROM, 0x30000000 (26,25 - spi select, 24 - short address mode, 23 - EEPROM write enable latch)
spi_ssn_o <= spi_cs_n_s when spi_sel = '1' and address(25) = '0' else '1';
-- external SPI SRAM/EEPROM, 0x32000000
spi_ssn2_o <= spi_cs_n_s when spi_sel = '1' and address(25) = '1' else '1';
we <= address(24) and address(23);
ext_irq <= "0000000" & periph_irq;
-- HF-RISCV core
processor: entity work.processor
port map( clk_i => clock,
rst_i => reset,
stall_i => stall_sig,
addr_o => address,
data_i => data_read,
data_o => data_write,
data_w_o => data_we,
data_mode_o => data_mode,
extio_in => ext_irq,
extio_out => open
);
data_read_periph <= data_read_periph_s(7 downto 0) & data_read_periph_s(15 downto 8) & data_read_periph_s(23 downto 16) & data_read_periph_s(31 downto 24);
data_write_periph <= data_write(7 downto 0) & data_write(15 downto 8) & data_write(23 downto 16) & data_write(31 downto 24);
periph_wr <= '1' when data_we /= "0000" else '0';
periph <= '1' when address(31 downto 28) = x"e" else '0';
peripherals: entity work.peripherals
port map(
clk_i => clock,
rst_i => reset,
addr_i => address,
data_i => data_write_periph,
data_o => data_read_periph_s,
sel_i => periph,
wr_i => periph_wr,
irq_o => periph_irq,
gpioa_in => gpioa_in,
gpioa_out => gpioa_out,
gpioa_ddr => gpioa_ddr,
gpiob_in => gpiob_in,
gpiob_out => gpiob_out,
gpiob_ddr => gpiob_ddr
);
sram_ctrl_core: entity work.spi_sram_ctrl
port map( clk_i => clock,
rst_i => reset,
addr_i => address(23 downto 0),
data_i => data_write,
data_o => data_read_spi,
burst_i => burst,
bmode_i => data_mode(2),
hmode_i => data_mode(1),
wr_i => wr,
rd_i => rd,
saddr_i => address(24),
wren_i => we,
data_ack_o => open,
cpu_stall_o => stall_spi,
spi_cs_n_o => spi_cs_n_s,
spi_clk_o => spi_clk_o,
spi_mosi_o => spi_mosi_o,
spi_miso_i => spi_miso_i
);
-- instruction and data memory (boot RAM)
boot_enable <= not boot_enable_n;
boot_ram: entity work.ram
generic map (memory_type => "DEFAULT")
port map (
clk => clock,
enable => boot_enable,
write_byte_enable => "0000",
address => address(31 downto 2),
data_write => (others => '0'),
data_read => data_read_boot
);
-- instruction and data memory (external RAM)
memory0lb: entity work.bram
generic map ( memory_file => memory_file,
data_width => 8,
address_width => address_width,
bank => 0)
port map(
clk => clock,
addr => address(address_width -1 downto 2),
cs_n => ram_enable_n,
we_n => data_w_n_ram(0),
data_i => data_write(7 downto 0),
data_o => data_read_ram(7 downto 0)
);
memory0ub: entity work.bram
generic map ( memory_file => memory_file,
data_width => 8,
address_width => address_width,
bank => 1)
port map(
clk => clock,
addr => address(address_width -1 downto 2),
cs_n => ram_enable_n,
we_n => data_w_n_ram(1),
data_i => data_write(15 downto 8),
data_o => data_read_ram(15 downto 8)
);
memory1lb: entity work.bram
generic map ( memory_file => memory_file,
data_width => 8,
address_width => address_width,
bank => 2)
port map(
clk => clock,
addr => address(address_width -1 downto 2),
cs_n => ram_enable_n,
we_n => data_w_n_ram(2),
data_i => data_write(23 downto 16),
data_o => data_read_ram(23 downto 16)
);
memory1ub: entity work.bram
generic map ( memory_file => memory_file,
data_width => 8,
address_width => address_width,
bank => 3)
port map(
clk => clock,
addr => address(address_width -1 downto 2),
cs_n => ram_enable_n,
we_n => data_w_n_ram(3),
data_i => data_write(31 downto 24),
data_o => data_read_ram(31 downto 24)
);
end top_level;
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
Wk8UDh46LeNmC96/0ElKdRBSKvHzQ5hb7AYPXdR6WNDPmvgjY6s+qQ9Yi5ckEq1SuXicQWNOGzVQ
Gt0tPmXcOg==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
IEvITBlYTgnSO6mThgqfhMbMD7mTrc2aYaXyl4I1ogt2oEMvr14fYstIiod5eugdWBgpAC3mOM8A
dEBIVmQ2QuWsnmHBxS9LDcPiAlEiV42tBD30Gxkovk5WZG/iGuP9TOZeKIOXCw+mG1vSuOPQlZ5P
8BYcbohbox7QJ904VNc=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
XkLSwtUL2vvG+Z5KphMpy2cwyLRPp3UmFJZ3pktTV53s6iXTEvF13he3Bc+2WsN5bqxTkMGxjnzX
NYl8NhWRp80kJt1ZvZXfYInqU1rvq/xFZ3bwX5HklXNHhMdBUbTyQalrYzRcwO0NRXUeTcVX9b4e
pMbV4YErFFzrz87HWBGt3RD9ymRUxeBpl9s7JYDJdIF29Ujb1J+X/gJAqWOsHBgASRBj1m4+jgDg
qev21MzUpv4dhHkXjezXMLnIkkqwJ8QAKc26XEAyHFBdvgu+DS4HINtYsIWeSua1IspBWKoC0eNE
gePq2C/HudG2FuNrYqpI61JYckOhoTGNZykc0w==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
RjHmXhFgZenlrK2hKT09TDY+EN9OwKx4aJe+GuQfN+kGCApRUPuO9Iin/qgCLcSRqkA3xfbGnr+Z
BnMeyxifvb1rOlQGGRWHvmFPWVgBLhRm9ahEPWDcGkxAYiA4HuHsSmL7cdSr5QuIyhGbnlUFJjJL
vwwSWbj2I1GqKqMgw8A=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
na603QMzJzXgJwG1cRoBFiFcfcjhKETzW1UZ4YiyU/8gzYW2TxlPdsB9PYDaRWu7DJdVI4qbVSSy
0yl/moLNJXgdXTLTkOvFFDd8bAho7EhDK5YEPHXzS3xG2qyAaFz+QhmjGAreX6bRbiig8oySCDXH
VtddGzVf9t7tUmIAzVOqDitvE54DyshWjgjXL+yFh0uYj3B7l1RTJtxEzeZzXWmNhJZwSA/8d1Z9
OxJ8Gax0Gvy/iU0NCF5YBrS7WkC9Om06aehO5h1vUNn/HbbmjWCqP6w8LSct73zx+8M49x+OWA0u
fNjiQCCfvrsxwAVs91hAu3LKBxga7sx+rxe2hQ==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 14144)
`protect data_block
J8wq5R8TYpMnU/VhxUOB/u3GuigvdvbJ+lfDBDiSPV+OHvh7tAqRDNrNFGGXEIDYBVmWNgKX5DfS
IgiQ7pTWVTvSlOXAWrOmOmhieuX37gQlBkeIWpuZCRtYwnSj6rQ9hnVrHDyrkHn9UNPm3OhJjoPS
/0jOAPpSmbfOoC3JKKNtdR/0jcmPcBFwgeWdokTaZJ/sBFFqSHh24JC57/XOSSd0r9dan970PScw
qf/gFYvH6ROHqh74tWJA6Yd5YiEckqhd2Ec+gHkAdvzJ4rpKpVbf5/XrP6ggXfhJ8pLM4kgRntsV
q7rVfjKTzCUAq9jcwkWHAhee311WiyZrVWW+fspQkK4kSVJbP/ysU+62zbgLSV4xAZO8mT6Igk/A
VYqL6hhy2jzAn22r/S32fawppD9Gd3BExM2l7raivCKU6yfQmmWvxNoWYK5jEUzNzxTde3H56QZw
/uLXxAUOh+L9LsROvmsfZOwvG9hKspy7ASkTamoMi8wYCcSLqfgzAI/+ofSEFPUL+L4uwXSbRoPd
1yLg+Df1Hd62/+uGpkem0I6YQMZ6DtlD+ua4HqxCNXTuJNj2mboeY28sk6UpM291Y81MQDjLBQTs
GQM1+GciWwE26umcx1gcAxF8iNbYPfB92yHakGiSgY5R1ZMGlT730ciYa/ZD8NdQt/78z6gHvLEv
4ZSBAK2E3k5sE1FmsA3rxmAKCOuhsL3GEUXQMt6k438pLHPsMaGrqIHQsKjE7WW/2TvpMv6U1/nk
awIEbIhBfIQPY3q2s5dtboHnD4lN6efSRp4MYPYaYG6vDX7MUyzwVm7juX4kqbOAv/GmRKlUUkx6
rIsxuA78UUZrlhMTRqUPJSLOnLSR2OzBbij2PGAHUW2ylT+Z43X+FILFbKwbU9A1XZiWGzaf2yli
kIdVSLxPTeypmtyTZuSr2I2Nh8kY9I2x5suDA26SFby2AzsfYUHDWeyaMbwvdkzDN+Y++Zg2N8tP
aTiHe3LRwK8mgrePXDjbTMZK6mENZQtBkk5kgKQkDiKctcQPni6hvXD0F2sfwTuJlorKV0qb5bj9
3LEkVb/H2GIqJXwCmLi7ka6/wambOfSwmnesWWJpklzDM4rpTfTXYkd6fxUMtHMP7ankShg5HPxV
FydO+db0xv0fwfSkqwMIOWazIWZrKpko51QpJN0UT8hN6fDndDwzgiMrdvSJ95d3ry6IDVhBLf/A
xP88jfGMyxU+uk7Ps2SBUYIwoz7lhE5JqMePnfwXIuADVS+UCyI6CPekRwvrNLmojpUCnBtM2VeW
q7VNtbZAdgJuOFn3ChMAGD2ss9FeQrnqw4VOE/j6hKrRl5ojcRbxm0QS2cmsNRRW+knVogvjFZJH
BsfnpRsxKmtkVEFNTBppIPoKjaqSBQuPaPuw2f68UtP0VhDNUKNyUpfaXZ5O6Fk2kOn9MeTlUHNX
df+a0ADw48WIPJnUot1FkIFRyKb1FIFRHX2g1pEn0cW/hpmTPh1J4UgOBG3WdvNn/C0m2Sprb/pn
+F7Bxd/thYW6PnNJleTAkFftO/FlipNBf4sTJSUK7MtuJPuYjXFrJXMXMNSRgFEM9L6bT1WMBox/
gITXiIE6Ct7AptwtmlbC0TvfBP+GW7ZOQuNggo0dmI0MIJMjrH5Cz0wYgb5wLcNu1caJ+OWy9Suo
1Nrr9PDHKMtiFaiIXRI9DL25Wlepn9R1vtsuuHLxQ8M0FJBiekaPmiIa8rAd4BvXIzW8x1r1v1JS
HWLwyZUfPo8mT6ilIfTazj3PqYBw1O40q/htF/Bferiv+bPMYUNssjY1hg+UhM3Lk5tEzFiBOTO+
FVmSpzwMpPzUtT/mKxEHTPCX5WmJg2I+KMhrSJsgQXijpkMGN1CQKSmLkVOxQ0MBhhVIbq9Sm2YG
GxK2DrsudA8/e2llwpxNhAYYwLwKZK3DZPh/lZKZFkxSVPY8hNy969mOXIJObBo+8Hmllu06fZOG
hn/cDDmrJWSSEYraF1XMcRSraIMvdqaIdzDjOavEWFaqv7AzdMhsuoqk9lH9FKG9/oq9Uv7OEvFG
VmssQBz3GA+w0QnT5EKEWZQokWQvtEFsWXGKa1v8LPMIquIG9FZhk9pPJpZpZJ1vqBquG+VgU5gD
+ed/1s+6u4oU5r3Fv1r4mn/Q81yd7l72RHnqj7HJGGeiNUydqE9XzxqxO6TxetjTseHg5+EKwrpP
I5c2n3MuEGBiUik9PemqL4a+QI/r+h4KMQOu0v91FfLG/5n5XUZvp1V9lML95F5BD0SHxzdw/YDn
4zOVpRTeTyP5nWyjVyYTUC8wzzCi2Vrr2fPyzSz1641iRhD/zze5YjCgfgZ8tBps04ybLM8FOHnb
3XkbHI7mYNW8U613L6D6Qb9bwkwzcinn14UDPzqndIy2bUsyiJrU4OWgkpUDmivFAsrzIn0Fum9Q
Kz0wFTXckLY09Wqc5duEG640YOEraNDK0hGh1aljNCtB1pN+eXQBtk6VmSUv96tlh51dCFzYjJKd
LL7duwaBk6rILyLIs0zIlF6tJEmsTcq2QEtj882bd3yjJfEX3nqpMHzutMcKT7F5Q4KqG9wxy0dF
eKJdHv29ximOpLYZJp/ocJaRtvUKqPCxvycAMF9y9FFURWXI93K+a3HP4M+I9/3xa9fh/hgF3XzK
yP/m654yms0rooPpLDQe2O741PWA7iYa5pXopZRkbhHs2BIR6v3MbQYPprz6D2qQXk4bvv/h8rCF
DVQkoGVgPkNv5BWRbmvvxJ+7yUu8m4qd0jUDARbzVHIHnpGvUbJB5NRO58l2qxH1L38YlGpc/EE1
bTTkF+qKB/zNM4kLcKLWh4YQuvuFuZK9PcMkm0HO30RVjCGgIle/T3qxeB3npZOVGff51A1jVzrg
4qRVgArvfUGRncwm5kjzsbexkAMWJkX2R6YEsRkJ6brRS+5SlAh58rJpRzXjf465Tkvyi/CUgEnN
Evu6DFRnuCGQpu/UF0xLquOKuCkFmUoLCBwmK5qH6QHcYOdbqhEyJuQ/pD4Vs2+Wtz0SLP3YY0vT
8HhV+Ltao0RuSVZ5YlLOnSLvhW6nx9LcjtiIt0XP3Bye5J+zr8L9NKlVlWL5YWS0N6kyJERx0vXl
/EdICi/uanPisrjK59F9CvXFla77WjzHy9iVdi0ZCgl6kwe35TIefQGESmh4vOHn2Qpq4WP+r/wD
1qE1foI8p7n3KmSf5m61OmxHZaQjkm8maLTb6RPbKg8eZKfqJzXzZHeKMl/QQTGBJ/i7tVojF53K
l7brAOGdyuuKMSKvscegCZDta/oxbj6wgWrmVoTvhlhZgMkFn8iLieU3Yx7tnX1Hzn526i1OfFLK
JeXqAsTGXAPYY+MrM6DLu3dmB4DhDSBQmMLxLM4PiHq+TaoqpILw4aSsUbdHZpj86HJ8pLRoJ3Ba
8jyDfQyakUf0ICxP9wdv+oDjPjRSXsoZ5h/JKIS9/oCWLTl3hr72vqP8xa4+/m7DEFMNRUbC8YTT
eua9z/toNPRtFlOriJR18a8kMREvJ0gF06W9EZ+IJXkw+saNuOA6rdN9AqxjqHP48dKod+kYVe2i
uCrMst+n+zJOouCQ5AzJxiYkD3ekhdZiMZ1h4777fkNQ/Dt7icIqsT7q97L4tNl9P4ZZN9D9A0gb
/4HzLz85r+JI8eIISqzSGtlzDBK7Iv9bGAzPnf4maj2fSNSlzCLD3Aj4wb+RvJoARTnGya2lqGuB
p41Wd9IJtqbzwd+X1IQot1ub1g04nGxw8JTDyMNpd3tJyAmgkVJd0Q+J4pN7tw5mB4jHTKAWwx1q
EBNErzOlmwqNKhadACkNz1v09PnHg/XBAtoZE59ju9qC/lnpPqsxKmVHKPWSxaMr906vq7xCy6yz
cSpJ2rqHO5+hpO0JcLw/TBGDjC/VWkBxekQ1sD8vMvwUHQUOOi+o0qvRNKFzbFf4GIW0BMs8QXVW
7M9cSvfhiytm2f/vfJhhp7YXU5Nh/MMQ/CWDydP0jdDw5Ksl6/1hWIodeulKqaYpMtdQeD2Mq1Cc
UcWkNV+4JO3bcOdavX/WHcC5Fev7jEt5yLKWasW74SCJ6R4kmxXj8yfVCaJ0OwOBxW1kcaycjyNf
x2KXtj+2oKrI66OsTGLB1CEjikR5dSsbu8RNUdpKoGxlEOOj7lxpGsz9Jdza0T6FIGy9JuPI3333
2bqskJjFVpdu2j6kU43JnPUIOy+0srSa374v1Vntz0wNeZtqlYDm66a2LRqFIVILk3Jglj7ur6jW
tVQhlVrV/hNNytLTzrvx3IBqtTmAIYNNZ5RfqgAJhc/GosAfHeQ7EJXHkdbknC6+ouJDBg3sF4aO
SrR48koTACM1yk5Y4MFi8lsOQhwbaW5T+6exVfk6A0uAiuSZzgj11JXpdLEfTOahpEeZHW21XVjB
luEoGnaG8gGC2Rqy6PGcy2ZyG4pEoc7idMtwubpNkm1d79GbQBeF9p2Fil8kvEkEVoaWzIZMBS5V
z78qIdqWFXlYAm2fRM5awjimFiKg+34rJBciI9T3LXjPL1+PI7lSHlOPmyVMpjBkNmAiEdUsPUAL
AV9K1XZifRFbKigvk+cUyZXUmUNhvFdoJMwNKcY3KZM1WxRkXNV+7MO4t9TpxRCDJDqyJeFA2N8y
n2YBIcQdVJNnM7GxQyZ4NeKaOoLWtF9AJFjcra/l6xmDjXtW8/aN6I2ofGcvJos8W8w9X2Usyl1N
d1RK8y7jV2bxiAwrT4+ADQy21WRbTJq+Q1qXR1aahtl0Y7yYZXrF1KiL+DzJZIALZ6QgkIE4e3BA
1To7kI8yzHFuaR3/ecRMDi+jzP6H2LxjtWHU171jOVssUMkZe2fSPAVNJ1qji0ouw0X9zyx9t2mF
Zu917N90L5e28++2vjlc0Roddor3YVU77Sk2VXWETFh9etYWRsp76FlfQFN4vn0ZXgCKSDRZOWPc
3wAyV11l9/ierP+EvuK5iyAtlygTQeLyBBnbMVZrjOnNokaCwJj0743Eu/av3JZQHta7aM8xXsC0
hgNtcQ1z0JIucd9nOv62l90g0zWYri9NZLRZ6UqqxM94sIEnx55HM22iAoiVcmejois2zTL1eilB
w0hYSna6uQZpzxCda8eLN04cR8gWkZU/Ky11lDpTsf1JoVtq2LivKwpuFY+z/HQMhUDxGyM6tJqp
hRnoLbd5p+OPa7b8HCLBHQjUJD8dbMD9QSxOBpynuaqOW7w9TloXlyy17hIIHqvmwpF42lhexs4E
LR6YdFK00tN1eNP3/8A81OpgpLx6089W6PM2gCvSiT+cr/e77KZX1zKexG6r4sV//JncTmNS6kpA
sCdbgm/YqBivdV6/M/PlVLDuE1MUcd4pMv097Jjs3mSsgKNSNx0DrHfvBCcbbl7i12bLOrSK1uY6
qThQWQyNooVRb2NhzxcB1ocRggD9Sv0BRmyHmo7UJz65y+5cjGpRGCvcsePRLHLYHWyxwrVjVoAF
dBxpkxK7aIyzquPa8kM0bhZGAKGAApy5AP0Ku2AXIq6svsfpcTZMfCE3TzLuRD1ole7/v1jNBfY2
Pt06qKNMkxfgNiLs0eTQDetAMLMcrm0G/kFRFGV6m2xZenCkxYmyCIuluyh8z1vp73Qnu0ykprCx
CfC5bpHLFuM5oLiyMXBqsPeeJ83dlhKQyir5YAgzab152YUvh1jq4qIX+Ys+4aoWLq6aPh+uABMc
V1KFIBl9eWt9AyJ0qGqAxjkJZAuwrqipM9GjFm0BT9Pm6dPL3XTMQ6Alf/4o+i+9V4P/t7us+54l
jIqb6SMOnXz6LO7vIZPzdmHAf0/In+u9iMOrLPLiDsSlt4T//NbKEm9zhP64oN2QIf7XurKyaJ8r
2q4UK5y9ZYWULnq59xdMZnnJsIFpIRviOc3Wun/FwqG1c+5fiFVTFoT3uQIUo/AHF3uuzqKLCoJ1
zaAit2mCXwdBTPGxFbKVzLO8lm7dL8GUq+/nbhxhYMMeCL856zlrpffN13ndRN5Qwqkq9mkTtj+R
9pBJBv3v7G9TnFqq7pafTkUbdj7Ug4mjEPf8u+wk4eLltbfYUHTofJCqAUHynQnY20bNYPS21c2m
Txl25c/KUSFVBk3BQ+kASUGsNOTJUivB91laEGdsK44e9usH79ycqB9xvvhXQ8IQqUrb0XZHSyAn
NAr+0Ddd4NpqQAcbvVdUs50+CMP5bpt0eN2yDjlAT38emBxYercVDHng90fzbAxvc4Exx4niadqO
lpZDxOwGRxRjtIt2An/E+24Ylsx6FLyPrJiLcnfZ96yePf64+qm4ADzVH4Y0JxyLh6TE27EfOlLI
QqVn3t7/uHHYJ2VahBheIxwJmGZ/TJcNrlDOPBZIRDM/Tgb5iP3KMRKm0kqWhzSM7NGnmHUHDZIS
0UvX3tQ33dgQIpQCUxaLswXd5/JtKzQUILd/Yjw3c+YB8JBzs7QygXpysGpQyEKqTTlv0UcN7X+l
5/p5XktSPb9L7JqP8ViYkpabLJPSehdmUXRmQ7L+d5dw3eZiM9LYlb5McShved3iXF1oeK9LBa2m
Ft/XaiI+PRowdsib3vp3vWq9Gz4Wg9dw2hF0Dhj+P7nPDeG/LWXJH5uOwXCiThfbdkWLYK2s/AP4
d+TFKMfqnBMQAaE6uX4Eebzmuo6RAhdDwpPeLAM1gYIB6HhSzZ7MRtxo10gA04UueKXGGVC3/FKa
LteFsh3doaguwx64+XLrjZMKYa2AAOsgNLwLr5G1L5y0VGfzVSi+Gax9V7jkPog6Lm1OgNO+aaNt
RxRcqp6Nk6lqcPhVNEOdrvVZI8p+Q49hFSj2kVn1QW1GcVhyoWJkmxXJrAJHgvlpguYNOBI1v2Eo
O8xlDWDK7h7nDXn92JBCNSnLlvCqDRbDFn39BB7MZoQRWR5BL8CVAHckAaX1oK85LBtKCo9ma/Yn
7PKHgKrm8CoNTChF1gXEqhm0JJ6qrBSOdc/TLQ7lh0+rB9CJpViSKIQ0SWGyGpwToa9xIVDJrNTX
B3Srb2coLDacqxwznavIhnnJpg5c0wFohj3bg9+W370jOxcPtx0IEaKlGY2DhIqLg9Dbc8ugoQkH
vIpDAwRRJ9KvJY3uggqH4n3OEueh+pYgtICX4D/yohyaHYplk+BAoUwRfI+0O4uw4RSgJqKT9RyT
Bgv34g1f+LLbiABBMZSzD2SmtF/cEDWHHLuw5TENLmA11xpIfCHMKX1AIlnF1wjAoh9uc+kPSsRR
O90IdJKUaJzIv54Eeoj2eSrkxWoVk1yP8sCY+8n2rfO6hnVTVV+BA+MtjqzxqUktOXOQZ3kKIl34
0JapKKSXvKBxBpjgHv+yeD6iri6E6qfkmjQO1KU4/gR0Bxm5byAGWJMSPybsVhrMuSnkWBfN2EfP
uCWAkyjxQRc0r2Uw4HzlaGRGfuRgXXqg56s/eYysfdXNfUUo7VMy37ibR+QVMd1yQF1J28gIpfRM
gKF3Eduxt5rvWh1MsozVzeYEmNId442qHzwh65CMtmXNQW8rOmcoYdxqKve3EQBXH6TsgAoL5Z9R
JYEkZ46CzR6gBBgrZi7DgoRcmkvZWK3An6kqn7F1+QoBZ2cJEJ+oDWcpm3Uxs9vvLlMKWRHqbISQ
hV/fIwM6SjJBvp6c27ZUKJV5r9dzddQGHcAYfUhjAaq5RZ1s/b2hRICASXF6JNPRiSgbg8m1rmtn
oUA8pPo4KrnkfYwMu4nf+OKvyiXpZWgjyiCLPhYqlcSyAIXy+YkfrZq5iuZBeaVaR/2J2YaQJFxK
WpE8HQKA1KPERNE/WhtgKKWzVe7NNNjQDONWb6Y2VRC6HbnB20V9GMeyqUs/5BVDWwgWivEXZxes
Wjq+OHgzabCSl2eXxRrqexT/XNB2h7n0vmYxk1KJ80x6Glx4+W6HQmXFlbPswkDh2wFJnXs3BVdw
FsU72OT3LB70UfPo7xLNTccYBvWjuHBHdOLi8yCPixN5uxEjw8yVhkFDv3I4I11+UMIzcrvpcaBF
jjBgCp/7UPfjx+R83mjSyMNGUMaG1avdwTPvAxbYl4G2pySDzSMB1XmCm46+e2pZBEQF8L7xh2/H
9+DvvR9n+4APp78Ko/ZmSMS3Ybydhtxa6wpgvkLrgOFxRkspPYD4graV2OJMVT6syo4oTmCyPbTA
vOCPO5pP9+dIb9GDzLYRiDUoUXvKeogbwmGNub8HeByeP/UU6Skpxwx3xoEPorPmXQYQXnqAcuWE
oGjvChVg4LDsOEfJlk4cJNNOZZhGpp1dQsfVzuSIsbmQHuz14zp9+vg5DyGrTjk7RbMo9wn2O7Hm
IzfFlbmi1MEKROa2CY2NNU5iMkuNW1+5wwO/rQ7vJW3syOQUviMD1CtIYbrmp1JBO7Y/JDBpz1vY
AzixBm1dHCNiQ6ycGphXkZeZoesIAiGnS7pBkIn28bOtXhlaAVjZcX2ldM2E2cDdOTaJOLXdDQd2
2Og42ycEX1ZKX5+BYvCHzme9J74j1FxnBG4Kh2JLBAqwEKWJ/7qYizJYUfi6/jqqmV+hANtBJ1Fk
knpldr3lbxqAHFRFt0jvP+1mJh6UgDt7MwgIL6n4f+dZ6hHcJIqrU9K3ZnaHnV+BczI6hpsLqBg8
mq0yduEVbNi6Ifs8EMkxceFYAoyTQmPNsa3tLXWLyoxkdddFXAepV6GCZzpXcmxxWWie8F2T5zU4
yPvZR6f6NFlmruEMeA9WjX1ohC0NaUsjnlim3A5jDJy8Bbh9Z+8bwJ/gtJxPdhcCKp4dmIFcdSSp
+TI9p8ogLybCJicI3j97seR9aSsthg4aHLgOkV9ziH/GI/u74Ee0w/jBsPnedbkdcJhHI4oPUN26
EC9YS9yZe8wXWPLgKhs1OK+uhN/+EIuFq3YTT74G+iwHEnZfoIJsYZTdmvtqzsE0+RZb7AoeLQpU
766n78mRDEtcupzVAgMiEbOtPTwgHKrNxjucTIiihm7qBC2101tIzNrYXxeeC/AeVtlKDNmwj2a1
oUQ9zCEDVBl0OmR/wVE1SjP2h8//0HAqHm+mv1aWJdFP7FYvqe9le7fHJYdk7OTOR8hxo2z1lGSF
dkPadUwyd956PHgLLP32m9iLVCkrCdpFiDl2/AeAnWg1+gHBSf4GyWc2aiCGr/gmdiRkcQs9JiIy
BNU0cKeRbHUC04K1MjNU0cv3+wReEyZt5p1H9d/2hY9Txxn5V+MiuUgzgU4LbomesZ4Sn0xFKCob
6XtUC39tD71ABLTToz+yT7sG80A/WrIr+3wyIZxGroW/qFiHNnylkwdezI3dqY5yKOsB/f6In3DR
7vze1BiS0AGvbHmNkK/To70eMAxR899NjqDIBEVMiNrUZsba4SyawzUm05EH3+0WnqzVGjPdhM+c
67OoRK9IqKgMX4DivDXOern/OWRQQOv+wVuB9VWN3hUFHy0Fhz4vknyynuABkBFo51kjbiP8HIBX
1XKeDDLvKXhUpAwbZ5mDnZoOsME96yvqDIbknNn7oKtcT7DgwCnP0xTiIEtg8BqnSxiJH0XSkXyD
3MPmcFE6+EoxLZ8s2l35V2Rx9f67dPzq8NkzE1p+m011N2Zes3wQQnE+EckTSTmF8GE5wRTUheIR
f+qO6uVs8MXkRll9nH5fS2VjfCNncvsGaufx6cSsLFs1XT8vmCTd5rDL6SK2h+GUKYUkpMJc8+zQ
on6Sb/URhkpONnYOPUTtyNybeG6DUWm8EbaboJS3ynTUiz0YBEmdkUFZcVOhSVET8msrKutyW/q5
ijITVg5zlgSHTwk3Vz+bUtRmjTooUJ9vj61pZfR9uVEF7OJwMJJaYFj+Xegor9oCGuBpytz1SQJI
gtaNOYc9dOLwp+vpGR576AVxLrEdMoWoPh+lzKNQJIB5ssMpF5HfXCv8hKORwK1WmSCb2HZu8Wxx
56uLYo7aDsNk3t7ECYqpMQI4xGbpcl6Qy2E6Il8nMvVWt8YPZAYbhGfgYQApmPC8Ii7Zk66GJZEI
Nd+I19/7iK9ToKQQzX2ddxJucpqpGWwHTjY7Ih1dYGxZ0fZtqWm7jjAo+ZtsrHirsZy3KyGSQry7
OdoQZ4LK8PH6IEtv+IQ99Kh6y2NSwktp2gnJ8TcpZugYGVvn/x+8sLCJaxpcuosuJu1uu2zlNVQq
Ow9y9XKQzNPMy+7guMMayybt9SRxtq4AmBSVGZSZ7ke/sm3OdqbtPCjOfyGMzf2rOG4h8FrP6Mkv
mOCipqyQAzs7WwEGcLjgRqNT6W+Uz7dD6PtsuSWKFLVK74jFxNyl6e9buzZchW9Z+Q6p8uZICnoM
E+vgBUd6O8BGifRZDyn61Q/pwaGrYu3hZKDY7ZTzVlL/jzZIr88QKbDVvxRLNEGX+UOeuKxR98N3
2FKjFD6N5QS0E5q8BQFqMDDH9IEHdSta6KZwFEyEkXonlyZQC6H1Q6FCzkvguKh1SZ9a7IxOXoE9
jSUNdo0HBKpWWbFu9SBEGIihLLSKy573qC14/f4w9kP7XflDlA795OqRnS8Me9SSSpSyDULtQRQZ
m2lg2oIr2PutVT+apMHSaSzAN+qlx/kkuroiZgmhoOQs/N1xF3ERK5y1iWo3ea5yewnAmfyH3q4e
B/HKFWZ/LcDEfykHjWIOAmIQtnDqPc56OMicnXLti1lZ1TOHr3jHnNwSndS37vf3+G0neBsPh9kA
YbBt9VUpKo8UwkgVWtlLhiOIGYrOHUj/P32lNeFP/WoBCWk/h8GvgU8bYejQfNDIPc0ovqyYwCYx
1Hjl9Nfsfei+ZDlY4+8LkpMGUUzKiQE8qR5Tt9SuWqDzyx3uhIgmKJwtTIAHfo1Im7EdnYGCzGNi
b8Ub7WzASspHZTlH+VRB5Yn0bv2Y91aVyE2WkKB6yms1wxqMrhXmctPoXMqveWJtCnPlSx8SofAf
+Uqn/GIaTOPAmDruAjVOVR5uSrQMmV9/UiCQYxUIY+FbTx9F5Ef2Uox0KGkK5bCm/pe5BL8pT2QZ
FJb8KNawHi/lChSF7XoBDMEB/jSkfXfJJGid2xKcrkI//7CGHMOoGYm8J2+LrfMuOYZJ3R/DJlKt
lgXnGQz/9zYwjfBl4naUUWU/xsG9wUO3xsF7Aqfbn4xO8whBBuvcb+mPWAmaC3oVymE1LORVXWSH
ZhhLNmNYSnwoOXENnlYin5Fval79XLIhpciTMMs7UG7nAYdZnq7PFplEwWECw5PPz+hZzv6OS+k2
45faK9ZCFp60LMSd/EI8SNeZZcOzSaZjqS2bVCd9syOe3w0N3i2EkEV762G87TOqobC6kBN7eM/1
XVEMeTvSekrBjcpW2F/NDYZ3JxDXZ+HbxLMUC4/p+e/AFiDbVJvcUP809SGjauyA2PgT40iV2ZAV
OEIprLXkADhrDl4XbiXOjsQ0MRv0JSVZXTfhBIbWF6mXFxGHy7jrA+HoZDvqR7m28XlKsoqI4dSv
4SObtNsoq9iiT5BBoh3X1qm1X4BV2F2v1g4Q+O1dWUvodm2pj6deE5jwHTeV0/nlkKAq2xP4o3H1
vb72F3An/f85FA3ezMN/ijUXD8oOCme0W/mUql6BoqsrYjUWuZU862nUrrL5eYE92jgctHLgXUoo
fJG8Wn/sRAJaDYw4z6iKRjd7ju2cVyOCcpOuzSHUJu43iJQnYVmotmSEOe871W5qd9wFZtGX8Jg3
84wGRMafXKuCz0PW+jVbyFDw3q0E/+/iL+UUGOvLlNjX6e5hLq4EmqQXzpiMuJcfj0hVGZdyeUuj
SmxAUuCMtdoWPUt+NHwDO0aV0s0fkJuU6QG6Fap00nyaOuNHR7FCG6urAwlzNOuQxXyMZryE6uwO
iK0YK/Tton4HDykqv2oh9lm2ji/I7Kxp42JFBv4VC4lh0NtiqrICdQbFMdD21Nv+E2mgLskwtZwK
1T9OGYdpZiRPXsRWYWWZL7kM+KkMqm5qvBruKJcbpy5rPGCkvyLtTQZNNl2ladjO0YHwnMPK1dV4
VCy9p8HJ5jI5knhC8eFSz7mlk/dC1dlSFAvfOFA3jyjT4+BpMgSUl89ClV43Wy+W57YrPnpeLbx3
gEadjQm/cwNHiIb4QMnNLaSCUTPEjQOo7jbFDp6J8XKb6iAwd2UUQqTbIklMB6WHBwVgSX2l/8Dm
QoMKQonSvRoj0Q3qlN9/ZY5u4+2hw914zRdnuPMYD92dGC+lrVIKBfvcmeqgCCBtvxbn8/QkOZED
DmSW4CabwgnvWoyiTftDVsmUUPRzADqCE93r4m2tB5D6ESAfLfJha5wYbELyUBaFtGKYlT4fypBD
3faI2bSR+GEg3LwW0HnZc0CKS4SdeY4q454jlE2qgCK3CSfpSgsjx1XbzLU03p2pRehXIT4+Krex
+BNy9XHJdhpdPiUFQmzZnvrNXhTRSPLAK4G7aqZx8gUirqmOh15TUho/7JsZ/a3ztwMEndlzWaju
MXxWsnYC+atrc6/ANWjHobnmAUBe7r6Xr4Sm5GhNpLVc2RT2vr9jDsu+Gwmp/jl+aP5e+E7lR9+3
00Qn4f/Dhvdcp+fewzs2TEZTmkd0ltYCufh8ywhlvWfbxQfMUo2yG8hpdkBfUw2MP7qwncbaRvom
X1sdDjHZn38JLVoPfI0rD0dUrQqnhQhpXM34Ch8yn2g4829XCZs3wzCWY1zZQPrQgLuwa1eM+DBD
f31nCOVP2WoszqHBddz8fvSEpblTW22wuvPm779MiAMULvuRiJEjVutSbV1hxXS9qCaFm9ce8BYG
jVqAa2LqKDy9zek2A4qa82d8icHgc4ZCuEtzs0zcqebsj7+40pdoQd/ZohE1a66uRxKnzV+E05Pd
IuovRiGHF3g1FQ939PzTKsuLZBl/86/QAOFbxivPTiWtWaEtlqhjqLtYkvIL9BHe/3fT0NeEbG5G
mOPS6TH/zqGLgUPIbZY8VIZZUX3zyUBWIo2ljwlW2OJJl+OnX76ORFgf4dJV1NCCJwwRE8uJXOlH
FoVFbRwlAwQLpa9vm6Y4x1M45fMS6nFkK9tG8YKMjEEYejtysioTbaJWLKPIiLeOZaA30vLGUfUW
gh78wnB6I2d22ApZh8ssH24Zp2bJ2OjMsPHzW4JTmM378eZrKbI7ZMr33dtP1mZVHN9UNjOJ3abv
Druikllcgt2fjVmuonk3S4WgWkII+auwO55KdjGe/JYufbjZAT+5P00kwGRXndWolXRkUNiT+PqZ
ukY96VKSmHqGU80y7HFuPCr3z+u/KG405HV1FcWqf9sgPslYlAv2h7sDn96KnFv/6af9SF2ZqkLW
P//8FxbzqP7xuaLBJRodlIteLKcKUHllTYmxtlQEw/W+qwqYJHJG3JgzRtL8B8D1qdvmwr2nVzB+
TTIyYBdDMs+G5Cq5IcSYFsI392QDdshefPBlnyqsZ2t+frIiumZedGQ2MikoTAcWcJIGkH4zpjBy
nFMZnoXdJJy/r0SUZOPsDKS9MUnWjN76ZGJZLrPfMLjuTIztBndWy2IT6T9p+AY6g/0ch8AK+FBS
CoKSkV2GCKwhjz/TFLXPxM62ICW+NjD4TTFMtKoYRMzC8u98+IsgqMJh2q+HfgTSlpBF8jqJ4M1F
Gdw1QXRSfdFiT68pgYiEZEbS0tNVoqJeDTt2qJKR4fzqygjX7oShz+yVX90fzRpbIu0N/tviU5AI
fN32l9gB5We1Y8wd+Sa01hMMFhvkrqwk2y1zqNtCyugRjZ+5S+7tqpWvQkUst9ywdZzpxSzWm8nI
BUrqnB5UOJzu5+NN8hlVxif5ED9Eae7QKOiXQudBap/o6Q/oNSAtePuWQJ78K1HJ2MX30yxPHJ3P
tqt6SbIQ+6PLN/S23EvCxE0d6ED5awsEbNdIAsz3tgyETZIg9gopz8YPVqrO9L/rrwmZ7Bfvy9ho
URwzyt6sUxjp8/nU5IqixD59zgSIhsuPbK1V55uJolOzXEA1qgvxpplnD6FtyXcYxq9pH2v5Xeil
SHVlMLHiClYplrGJFRM+pXXmSTVrhB16qEd84EmcKWQ2uI0FCR8/154JFD2UhQg+jtJsU5d/PVR8
ux0lXMioIeWpmU+2zt0aJSdN/9/b4ZJrpVXksIkf9AWVhTIFfUq3+SW9nWevM2fiPyg9giRlGPuA
tddO+nc4voxsiW1UlUnanCSHr75Z0WQ+s0MxnP8OO/dbFyimSDRVqcBQ8cb2mWDSkeGZwJbtRRDi
M8vcy7SjqdaEIyOtIy/rZc0eyIm2AFIEs5FBBN94My4K6pR3+u8XGu9fWPwG4s5hL8yhdZtx/7dI
yOzhZILStvz3lsf7qDQvzFQdOTNa4YaFJUjz9TvDOUDGARR5MWNolkqe2bWb7tKmg/dOOwaF2d7j
FQcveQuWaUY1bF9QTX9BEjVrLwRc4lqA/18kNktMzmD+yybUGBADR7tnZBXE6D4aNVh1+B5SkoDx
30ZDZiyc6ItPsAzaXPauGRNmqBhDklI8W3sBaNQKVG4ePaY48zyk0eb1GlUIgtM20ebgZzvY/6nB
cYnrWqZ3w3ZB4iyN3k47AniKglc41FySHkC5QMZfHBLD+kL+pkxI4xwYnjc6IpGnM7lLgO3dXcqZ
BbR3D6sO91S194Nh6rmTnc+aO5Q8t9rBXjLqLHXkRsjsvAHM05B5haHGXOqHKJKD+rt39lt+RfDr
D+VVT3AgDroJExdDqQ57MzRlgmh1j0re/a+BsjdKyZj659j/wDcAW6npq2M4CSVuaMwkRzWS2fx3
wbtvTTWBPgM7TUVlfO21uvDzsW7MkxibdSlyVt17a2CkKhA2sUCE3DuAk9gwDyrEde2l7TKagokB
ouRR2vzmlTtiDuO0mecjE3+o3HVg9Vmj73ejZ+psfC97yrdnp1N0pEza6+AgyQy5A7ay9Yas75P6
kYGQ8tJ03b30dRhNCg5HB4v6W3SxGeZoa8qnoawn4cDVDEZlC54q2H/H7IyZtYIUs5HcULotx7x8
PtxMbF3v9gAKqYI4MC5RszdJ1hMtfcJB7WrvviZzp4+fzhwM6J+I6reIcEvm21aICka4r35Qgyh8
pSxEB4BsGepnFb1aPj2ABMGrXWvF4ilOMg7XCrkv6Kht1Ivo+OrPIwWNe88kTpXSvp6QcIZCmi8d
hyUg8sK4p1sOEszfl6ZInECT6vEhppF479KChASomXDYQzwGQyKh7VLZfkREpE8pPVJeHYnCzgvR
gBaoNlkHgvEv8mKQTU7l9427iG+13xS2h6pyHxMYu6oewda0jwaNkiiU8k3VmN7zngDan6V398sa
4rCKRq3lmk4Io14XLfsMbrCfQHvmmvujSUb+LzSS+l7rBEONMpiK1KSQvkmx+5CUOloX44NoFitj
NjTNKx34S2QVwJHszuOse2v0IUobHDHqwNYULHQ3S3x7leACeNrNFzA4cwih3fjp+DxCFz+K306F
CiHy6svJkUOhjTrTVjpzXIUg2K0pzHpPhkKpJQ/ETI75/2m4n8kvbEEE1IPaJLDRaakXZiEAT7Ko
rpa82QMw57Cr27eQ1Zp0auaZTtKyXTNkk7c02YRRin7FBsDYMNOrlp4R4oTbc7UnUjJhzJIcGUQn
pyqlBjvY2Rdhjiihc2xdpnIZWKiU3DUYDl6machY3s+8TIUYlBT6dAzluK+jzutp1GIcs4zK/oWl
L2qoe/UopLf5N0DixUJ4k0suRbVwZCeT0Vu4uID6sqvyDOnVHMD0FrcmddA+niolrL8H1G6N7+4P
lCkGGh1MJDv3fxBq8MsEZSMRiyTxjceIl1rkHKTIDwlHYUO1TYdK8NQilpv8SapAhjlXEKZ1VutX
zLViLMK6K0C6HVvODMpgaS5FIqJiEiYsBYrrvvUZGMSGQeinyc51CSCgStSHN9lFgE8WgsKWXGSy
G2ka8Lfaf1bfPs4ME1qsyvYRsYld82eEdt13/Bq468g4613erMm4vsKIEHJ2NbChZLMMWaTp8+JF
wRBV+H4jFAjWxpJ6iUlX4uxM5Y1xM50O6jx8WjlXtWOHJS0IGO9lCRCW1PNSpnMTL5K1SHs9l9HB
kAJVoWHoTkzU1ynP60QVvArc7P8qORnc7zMWcJz7qnOiaBHZ5rvIccrybzpXCUQ8QQoDQ2dzJ5gK
8xmBqP6wQ8Ell193orskZ8KfiFZadKO6GrTAsMu04oJnKXaIFfOhP/1HbDefLlAiQUQD3ayxRmvg
RUEKAWbusy/M05/DuBg3ukC76zzXpLUDt92T9Rhv4kkDzpnVcHMFDHBriHsATUKzHlh1CS/WgfOI
sFOP4H3+mIdiXhBrGe0jZ3X8qyrB0LUTdnC3OKAQvd9LLJPvqqWSYdeS/6B31ecrx3AMvE/1xgIw
S5C4B+V3VUUdaT/A2X0yBWKBh7JyXnSZNAvesRljzEaLioXXgHZIfSnD+4B2ymG9oGQicFEVOTqs
5qbY8Hv7bCFuDl40Ocicy6VL2XRFjZpC6Fge9qzkCmtv/84JusSZcMWJ1cRZt0o6E/qgRPm+RNRM
gqWfBg2eoKj+caqNHlMqT9jFpUzIniyAd7atGfEfp/BnmanP9CvApS16WdjGK9hrcbvxZVsAtiIC
bmAB0Gbh+KxY4Nujk3vsw2DRNXkbj16ZkoFFrfEl7wjlHxex352UMVVenO/UKCEHSv5zdfo6Uwj0
itxijOld0EakvxjrZV+PJ9SCcJCu6RrWn1orjv3WklgmPlYTB1LWjZnqi56JPP3ck/tN0ZiEG8iX
9p8FzV5TQsFwtsIodBxX213z4oESSa01vDDE3QG6c218dn5QBcamBy90sQ5kuaabs6FOttDZmywt
z4G1LFS7Yjjq+nSD+KIpIM429j+FuboyOh0rTNZHvt2ShoFVaaZhHCctWkWMK6a9sPljSvSvIATm
w+9X2n1bJqbZljP7fuHCXOJFJdSjnD2LFfoWYJatqbgh/anVijPlVAVopUTHqjZk7QyL7AEFXjnv
95cRrzYD86MAHv23VHvhWRB5wtZAFUOKMakMxM2Usza5y5eKrNQISavJl4EfZob5WjovwjuyM9jE
nDf8zVWpoLCqe85D9w23Mt0+qFG0xK+etXRNpW8TGREFNcDH75IkMtEbxF0OvNmjkTgpOZOZfzrh
od/g7tXc4MLilsfNQ5RR7Wf4DMes5nnqfm1iAQW/vf3x5Bzkgz3Dakm1E7q1idaCJzatKcRqOPEi
dW/OnblKurNS+atnX+O/u2eUmJ++7UZs1hk5MG94XeaT3WYETNBIcg0idjHrutgr0CBHR5R8mhzN
vkWfX8nWTBP8hvyzrDGqjYdU9LjO9hPCqz2aulQRlEZIfoN1chVxV+tzNNXh0nYCOY/A5F+lsou4
jRTt/fBp+LXSlUOO2LjZJZIEjQEGhJHdIxCDsjRtIF9VT1wJ3KelMqWthEnmU0qyENtog6JfETGH
ZSZZCz93/8Tor3ZTW4sBQPf4ZfBJLBvGDsbVFROTxExCDzv5QBUXRi3epRCzrceTPXxouAx+L8Xc
83FOVBCMcyhyZJ9t6rPkPdlXHlbeiuYpm5ooB8agwJ/ulIDTaRS0KfA/7jtRWX+ptmqt2Png6XWr
LU6Ftwj8b+U8bEU+Xnq/DOSwID6zJQwUH25BcT7JP+SXlvwH0QwU0oMHFNFmHsboWpA91ulVcWS4
D0ZKaV+MkvQdbtQ5TUQU7jHbsoSkcFnq/htjNBDzgbrJwjeEioVO593BTrgsmwwYbtRDPG0SkkCz
OcN5MA6I4aMprwjPlCcL5qMChwb+6pj11OWTpzSsPjH3GBakp/l79MJ28tnSfAlzT1Qpt6/8Xs5a
GczJZtM06cmsvnC42wdPGO7CRLmt7zHe2NPyCZPTWBw5lOsqmts0kWj3MIE0lR39lIw3jGGiIDI+
CrEm22v9eBUPV9SPBuN3ss6/t0Nt9DzDRUwD1ogjNIUKqGMdl2mRSDc78raqDe1Pet5t6xSWSgcm
wVrNaY2iclE1tewFmxxLMk9gpMhaRGnEFZOJV2mzj7Ef6/9PLrH5lqoEVhpmlrO+0HhiWeZAg2Uj
4Lr0jbDQ/rkbJvBV2xs7UEnGTr+hHG2UaSWsUARs9daP9Bt+8SJ518Ih3Xij9+IVRnb97I4HDhg5
ggAzWzx/PTxJzUsaU3R5zV5YqBxj5e+tAudxoBaZMzQVNpqoXrTPr5FVC/3EXq5Tv2w8z50CrD5q
0QrnZIiFzmo+qFj+uGvGdCxcaTED/PM+mJkO8/wVSqV84++7Kfkd8nUrekubzfpmuT0utnrit8wm
C7BqlQecK6yar+etuoAet41+B81tJDfKQA+Y8376I2Oksj/0l0kW65oShl4R+gZCHkwR8c/T3gQE
Gd9PL2w6wKpFNLO3UA5iYoaW8boB2qDqsNbYK+TLbkO1UQvQGMANXb8kryrdS8QCmf1lPdZspzYX
tFnCB+kW1tnCu8jfYeyxhTqTg4ElTnSo415DvA63yJmjvhTMbfmWPHpC24H/kq4gZ9G/+7mUBuAQ
nMjpHygAX16lcx8FRfiQ00CpoYhvHzYdYt7ApzLmQIrK5BAIKFIHigueDLmP9pqlB4hzvUaITB65
NwqalpIQB6htX8PPQkrqGubMTdK2mqyyC/JA2UY9I4IoMN3YDmVLZ/Xg8Ks2sk6vRg6T15wu6SC7
nL7Z7D20qdYZkyad8+2THuKmD8yvqHYGWe5DkYjOCEbedaqSuJ/tShVGNhLHFok3py89zHHNHLb1
6EN19qIe9rU7l5XDIDEVPd933wsrYdJEAiwrIuVBzShD13XDztdl9xmh0pyMqXjcpxfUvy9pNfJs
HXOPp9FpjDjRjmoJXVnvf50MxHSeAPgixZZPf/lmMPf945O4aAY8Bx9Dz1RfGBL0aAiMEiI3Mh+e
Nv6TP6M2XKFcK46HBM/Tf2OKvGer1edX9XnP+hXNFdXU1kpzbdfbo5Ew74nVnFOK2aCvmKLVOWhm
IENTN7/0TUw=
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
Wk8UDh46LeNmC96/0ElKdRBSKvHzQ5hb7AYPXdR6WNDPmvgjY6s+qQ9Yi5ckEq1SuXicQWNOGzVQ
Gt0tPmXcOg==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
IEvITBlYTgnSO6mThgqfhMbMD7mTrc2aYaXyl4I1ogt2oEMvr14fYstIiod5eugdWBgpAC3mOM8A
dEBIVmQ2QuWsnmHBxS9LDcPiAlEiV42tBD30Gxkovk5WZG/iGuP9TOZeKIOXCw+mG1vSuOPQlZ5P
8BYcbohbox7QJ904VNc=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
XkLSwtUL2vvG+Z5KphMpy2cwyLRPp3UmFJZ3pktTV53s6iXTEvF13he3Bc+2WsN5bqxTkMGxjnzX
NYl8NhWRp80kJt1ZvZXfYInqU1rvq/xFZ3bwX5HklXNHhMdBUbTyQalrYzRcwO0NRXUeTcVX9b4e
pMbV4YErFFzrz87HWBGt3RD9ymRUxeBpl9s7JYDJdIF29Ujb1J+X/gJAqWOsHBgASRBj1m4+jgDg
qev21MzUpv4dhHkXjezXMLnIkkqwJ8QAKc26XEAyHFBdvgu+DS4HINtYsIWeSua1IspBWKoC0eNE
gePq2C/HudG2FuNrYqpI61JYckOhoTGNZykc0w==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
RjHmXhFgZenlrK2hKT09TDY+EN9OwKx4aJe+GuQfN+kGCApRUPuO9Iin/qgCLcSRqkA3xfbGnr+Z
BnMeyxifvb1rOlQGGRWHvmFPWVgBLhRm9ahEPWDcGkxAYiA4HuHsSmL7cdSr5QuIyhGbnlUFJjJL
vwwSWbj2I1GqKqMgw8A=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
na603QMzJzXgJwG1cRoBFiFcfcjhKETzW1UZ4YiyU/8gzYW2TxlPdsB9PYDaRWu7DJdVI4qbVSSy
0yl/moLNJXgdXTLTkOvFFDd8bAho7EhDK5YEPHXzS3xG2qyAaFz+QhmjGAreX6bRbiig8oySCDXH
VtddGzVf9t7tUmIAzVOqDitvE54DyshWjgjXL+yFh0uYj3B7l1RTJtxEzeZzXWmNhJZwSA/8d1Z9
OxJ8Gax0Gvy/iU0NCF5YBrS7WkC9Om06aehO5h1vUNn/HbbmjWCqP6w8LSct73zx+8M49x+OWA0u
fNjiQCCfvrsxwAVs91hAu3LKBxga7sx+rxe2hQ==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 14144)
`protect data_block
J8wq5R8TYpMnU/VhxUOB/u3GuigvdvbJ+lfDBDiSPV+OHvh7tAqRDNrNFGGXEIDYBVmWNgKX5DfS
IgiQ7pTWVTvSlOXAWrOmOmhieuX37gQlBkeIWpuZCRtYwnSj6rQ9hnVrHDyrkHn9UNPm3OhJjoPS
/0jOAPpSmbfOoC3JKKNtdR/0jcmPcBFwgeWdokTaZJ/sBFFqSHh24JC57/XOSSd0r9dan970PScw
qf/gFYvH6ROHqh74tWJA6Yd5YiEckqhd2Ec+gHkAdvzJ4rpKpVbf5/XrP6ggXfhJ8pLM4kgRntsV
q7rVfjKTzCUAq9jcwkWHAhee311WiyZrVWW+fspQkK4kSVJbP/ysU+62zbgLSV4xAZO8mT6Igk/A
VYqL6hhy2jzAn22r/S32fawppD9Gd3BExM2l7raivCKU6yfQmmWvxNoWYK5jEUzNzxTde3H56QZw
/uLXxAUOh+L9LsROvmsfZOwvG9hKspy7ASkTamoMi8wYCcSLqfgzAI/+ofSEFPUL+L4uwXSbRoPd
1yLg+Df1Hd62/+uGpkem0I6YQMZ6DtlD+ua4HqxCNXTuJNj2mboeY28sk6UpM291Y81MQDjLBQTs
GQM1+GciWwE26umcx1gcAxF8iNbYPfB92yHakGiSgY5R1ZMGlT730ciYa/ZD8NdQt/78z6gHvLEv
4ZSBAK2E3k5sE1FmsA3rxmAKCOuhsL3GEUXQMt6k438pLHPsMaGrqIHQsKjE7WW/2TvpMv6U1/nk
awIEbIhBfIQPY3q2s5dtboHnD4lN6efSRp4MYPYaYG6vDX7MUyzwVm7juX4kqbOAv/GmRKlUUkx6
rIsxuA78UUZrlhMTRqUPJSLOnLSR2OzBbij2PGAHUW2ylT+Z43X+FILFbKwbU9A1XZiWGzaf2yli
kIdVSLxPTeypmtyTZuSr2I2Nh8kY9I2x5suDA26SFby2AzsfYUHDWeyaMbwvdkzDN+Y++Zg2N8tP
aTiHe3LRwK8mgrePXDjbTMZK6mENZQtBkk5kgKQkDiKctcQPni6hvXD0F2sfwTuJlorKV0qb5bj9
3LEkVb/H2GIqJXwCmLi7ka6/wambOfSwmnesWWJpklzDM4rpTfTXYkd6fxUMtHMP7ankShg5HPxV
FydO+db0xv0fwfSkqwMIOWazIWZrKpko51QpJN0UT8hN6fDndDwzgiMrdvSJ95d3ry6IDVhBLf/A
xP88jfGMyxU+uk7Ps2SBUYIwoz7lhE5JqMePnfwXIuADVS+UCyI6CPekRwvrNLmojpUCnBtM2VeW
q7VNtbZAdgJuOFn3ChMAGD2ss9FeQrnqw4VOE/j6hKrRl5ojcRbxm0QS2cmsNRRW+knVogvjFZJH
BsfnpRsxKmtkVEFNTBppIPoKjaqSBQuPaPuw2f68UtP0VhDNUKNyUpfaXZ5O6Fk2kOn9MeTlUHNX
df+a0ADw48WIPJnUot1FkIFRyKb1FIFRHX2g1pEn0cW/hpmTPh1J4UgOBG3WdvNn/C0m2Sprb/pn
+F7Bxd/thYW6PnNJleTAkFftO/FlipNBf4sTJSUK7MtuJPuYjXFrJXMXMNSRgFEM9L6bT1WMBox/
gITXiIE6Ct7AptwtmlbC0TvfBP+GW7ZOQuNggo0dmI0MIJMjrH5Cz0wYgb5wLcNu1caJ+OWy9Suo
1Nrr9PDHKMtiFaiIXRI9DL25Wlepn9R1vtsuuHLxQ8M0FJBiekaPmiIa8rAd4BvXIzW8x1r1v1JS
HWLwyZUfPo8mT6ilIfTazj3PqYBw1O40q/htF/Bferiv+bPMYUNssjY1hg+UhM3Lk5tEzFiBOTO+
FVmSpzwMpPzUtT/mKxEHTPCX5WmJg2I+KMhrSJsgQXijpkMGN1CQKSmLkVOxQ0MBhhVIbq9Sm2YG
GxK2DrsudA8/e2llwpxNhAYYwLwKZK3DZPh/lZKZFkxSVPY8hNy969mOXIJObBo+8Hmllu06fZOG
hn/cDDmrJWSSEYraF1XMcRSraIMvdqaIdzDjOavEWFaqv7AzdMhsuoqk9lH9FKG9/oq9Uv7OEvFG
VmssQBz3GA+w0QnT5EKEWZQokWQvtEFsWXGKa1v8LPMIquIG9FZhk9pPJpZpZJ1vqBquG+VgU5gD
+ed/1s+6u4oU5r3Fv1r4mn/Q81yd7l72RHnqj7HJGGeiNUydqE9XzxqxO6TxetjTseHg5+EKwrpP
I5c2n3MuEGBiUik9PemqL4a+QI/r+h4KMQOu0v91FfLG/5n5XUZvp1V9lML95F5BD0SHxzdw/YDn
4zOVpRTeTyP5nWyjVyYTUC8wzzCi2Vrr2fPyzSz1641iRhD/zze5YjCgfgZ8tBps04ybLM8FOHnb
3XkbHI7mYNW8U613L6D6Qb9bwkwzcinn14UDPzqndIy2bUsyiJrU4OWgkpUDmivFAsrzIn0Fum9Q
Kz0wFTXckLY09Wqc5duEG640YOEraNDK0hGh1aljNCtB1pN+eXQBtk6VmSUv96tlh51dCFzYjJKd
LL7duwaBk6rILyLIs0zIlF6tJEmsTcq2QEtj882bd3yjJfEX3nqpMHzutMcKT7F5Q4KqG9wxy0dF
eKJdHv29ximOpLYZJp/ocJaRtvUKqPCxvycAMF9y9FFURWXI93K+a3HP4M+I9/3xa9fh/hgF3XzK
yP/m654yms0rooPpLDQe2O741PWA7iYa5pXopZRkbhHs2BIR6v3MbQYPprz6D2qQXk4bvv/h8rCF
DVQkoGVgPkNv5BWRbmvvxJ+7yUu8m4qd0jUDARbzVHIHnpGvUbJB5NRO58l2qxH1L38YlGpc/EE1
bTTkF+qKB/zNM4kLcKLWh4YQuvuFuZK9PcMkm0HO30RVjCGgIle/T3qxeB3npZOVGff51A1jVzrg
4qRVgArvfUGRncwm5kjzsbexkAMWJkX2R6YEsRkJ6brRS+5SlAh58rJpRzXjf465Tkvyi/CUgEnN
Evu6DFRnuCGQpu/UF0xLquOKuCkFmUoLCBwmK5qH6QHcYOdbqhEyJuQ/pD4Vs2+Wtz0SLP3YY0vT
8HhV+Ltao0RuSVZ5YlLOnSLvhW6nx9LcjtiIt0XP3Bye5J+zr8L9NKlVlWL5YWS0N6kyJERx0vXl
/EdICi/uanPisrjK59F9CvXFla77WjzHy9iVdi0ZCgl6kwe35TIefQGESmh4vOHn2Qpq4WP+r/wD
1qE1foI8p7n3KmSf5m61OmxHZaQjkm8maLTb6RPbKg8eZKfqJzXzZHeKMl/QQTGBJ/i7tVojF53K
l7brAOGdyuuKMSKvscegCZDta/oxbj6wgWrmVoTvhlhZgMkFn8iLieU3Yx7tnX1Hzn526i1OfFLK
JeXqAsTGXAPYY+MrM6DLu3dmB4DhDSBQmMLxLM4PiHq+TaoqpILw4aSsUbdHZpj86HJ8pLRoJ3Ba
8jyDfQyakUf0ICxP9wdv+oDjPjRSXsoZ5h/JKIS9/oCWLTl3hr72vqP8xa4+/m7DEFMNRUbC8YTT
eua9z/toNPRtFlOriJR18a8kMREvJ0gF06W9EZ+IJXkw+saNuOA6rdN9AqxjqHP48dKod+kYVe2i
uCrMst+n+zJOouCQ5AzJxiYkD3ekhdZiMZ1h4777fkNQ/Dt7icIqsT7q97L4tNl9P4ZZN9D9A0gb
/4HzLz85r+JI8eIISqzSGtlzDBK7Iv9bGAzPnf4maj2fSNSlzCLD3Aj4wb+RvJoARTnGya2lqGuB
p41Wd9IJtqbzwd+X1IQot1ub1g04nGxw8JTDyMNpd3tJyAmgkVJd0Q+J4pN7tw5mB4jHTKAWwx1q
EBNErzOlmwqNKhadACkNz1v09PnHg/XBAtoZE59ju9qC/lnpPqsxKmVHKPWSxaMr906vq7xCy6yz
cSpJ2rqHO5+hpO0JcLw/TBGDjC/VWkBxekQ1sD8vMvwUHQUOOi+o0qvRNKFzbFf4GIW0BMs8QXVW
7M9cSvfhiytm2f/vfJhhp7YXU5Nh/MMQ/CWDydP0jdDw5Ksl6/1hWIodeulKqaYpMtdQeD2Mq1Cc
UcWkNV+4JO3bcOdavX/WHcC5Fev7jEt5yLKWasW74SCJ6R4kmxXj8yfVCaJ0OwOBxW1kcaycjyNf
x2KXtj+2oKrI66OsTGLB1CEjikR5dSsbu8RNUdpKoGxlEOOj7lxpGsz9Jdza0T6FIGy9JuPI3333
2bqskJjFVpdu2j6kU43JnPUIOy+0srSa374v1Vntz0wNeZtqlYDm66a2LRqFIVILk3Jglj7ur6jW
tVQhlVrV/hNNytLTzrvx3IBqtTmAIYNNZ5RfqgAJhc/GosAfHeQ7EJXHkdbknC6+ouJDBg3sF4aO
SrR48koTACM1yk5Y4MFi8lsOQhwbaW5T+6exVfk6A0uAiuSZzgj11JXpdLEfTOahpEeZHW21XVjB
luEoGnaG8gGC2Rqy6PGcy2ZyG4pEoc7idMtwubpNkm1d79GbQBeF9p2Fil8kvEkEVoaWzIZMBS5V
z78qIdqWFXlYAm2fRM5awjimFiKg+34rJBciI9T3LXjPL1+PI7lSHlOPmyVMpjBkNmAiEdUsPUAL
AV9K1XZifRFbKigvk+cUyZXUmUNhvFdoJMwNKcY3KZM1WxRkXNV+7MO4t9TpxRCDJDqyJeFA2N8y
n2YBIcQdVJNnM7GxQyZ4NeKaOoLWtF9AJFjcra/l6xmDjXtW8/aN6I2ofGcvJos8W8w9X2Usyl1N
d1RK8y7jV2bxiAwrT4+ADQy21WRbTJq+Q1qXR1aahtl0Y7yYZXrF1KiL+DzJZIALZ6QgkIE4e3BA
1To7kI8yzHFuaR3/ecRMDi+jzP6H2LxjtWHU171jOVssUMkZe2fSPAVNJ1qji0ouw0X9zyx9t2mF
Zu917N90L5e28++2vjlc0Roddor3YVU77Sk2VXWETFh9etYWRsp76FlfQFN4vn0ZXgCKSDRZOWPc
3wAyV11l9/ierP+EvuK5iyAtlygTQeLyBBnbMVZrjOnNokaCwJj0743Eu/av3JZQHta7aM8xXsC0
hgNtcQ1z0JIucd9nOv62l90g0zWYri9NZLRZ6UqqxM94sIEnx55HM22iAoiVcmejois2zTL1eilB
w0hYSna6uQZpzxCda8eLN04cR8gWkZU/Ky11lDpTsf1JoVtq2LivKwpuFY+z/HQMhUDxGyM6tJqp
hRnoLbd5p+OPa7b8HCLBHQjUJD8dbMD9QSxOBpynuaqOW7w9TloXlyy17hIIHqvmwpF42lhexs4E
LR6YdFK00tN1eNP3/8A81OpgpLx6089W6PM2gCvSiT+cr/e77KZX1zKexG6r4sV//JncTmNS6kpA
sCdbgm/YqBivdV6/M/PlVLDuE1MUcd4pMv097Jjs3mSsgKNSNx0DrHfvBCcbbl7i12bLOrSK1uY6
qThQWQyNooVRb2NhzxcB1ocRggD9Sv0BRmyHmo7UJz65y+5cjGpRGCvcsePRLHLYHWyxwrVjVoAF
dBxpkxK7aIyzquPa8kM0bhZGAKGAApy5AP0Ku2AXIq6svsfpcTZMfCE3TzLuRD1ole7/v1jNBfY2
Pt06qKNMkxfgNiLs0eTQDetAMLMcrm0G/kFRFGV6m2xZenCkxYmyCIuluyh8z1vp73Qnu0ykprCx
CfC5bpHLFuM5oLiyMXBqsPeeJ83dlhKQyir5YAgzab152YUvh1jq4qIX+Ys+4aoWLq6aPh+uABMc
V1KFIBl9eWt9AyJ0qGqAxjkJZAuwrqipM9GjFm0BT9Pm6dPL3XTMQ6Alf/4o+i+9V4P/t7us+54l
jIqb6SMOnXz6LO7vIZPzdmHAf0/In+u9iMOrLPLiDsSlt4T//NbKEm9zhP64oN2QIf7XurKyaJ8r
2q4UK5y9ZYWULnq59xdMZnnJsIFpIRviOc3Wun/FwqG1c+5fiFVTFoT3uQIUo/AHF3uuzqKLCoJ1
zaAit2mCXwdBTPGxFbKVzLO8lm7dL8GUq+/nbhxhYMMeCL856zlrpffN13ndRN5Qwqkq9mkTtj+R
9pBJBv3v7G9TnFqq7pafTkUbdj7Ug4mjEPf8u+wk4eLltbfYUHTofJCqAUHynQnY20bNYPS21c2m
Txl25c/KUSFVBk3BQ+kASUGsNOTJUivB91laEGdsK44e9usH79ycqB9xvvhXQ8IQqUrb0XZHSyAn
NAr+0Ddd4NpqQAcbvVdUs50+CMP5bpt0eN2yDjlAT38emBxYercVDHng90fzbAxvc4Exx4niadqO
lpZDxOwGRxRjtIt2An/E+24Ylsx6FLyPrJiLcnfZ96yePf64+qm4ADzVH4Y0JxyLh6TE27EfOlLI
QqVn3t7/uHHYJ2VahBheIxwJmGZ/TJcNrlDOPBZIRDM/Tgb5iP3KMRKm0kqWhzSM7NGnmHUHDZIS
0UvX3tQ33dgQIpQCUxaLswXd5/JtKzQUILd/Yjw3c+YB8JBzs7QygXpysGpQyEKqTTlv0UcN7X+l
5/p5XktSPb9L7JqP8ViYkpabLJPSehdmUXRmQ7L+d5dw3eZiM9LYlb5McShved3iXF1oeK9LBa2m
Ft/XaiI+PRowdsib3vp3vWq9Gz4Wg9dw2hF0Dhj+P7nPDeG/LWXJH5uOwXCiThfbdkWLYK2s/AP4
d+TFKMfqnBMQAaE6uX4Eebzmuo6RAhdDwpPeLAM1gYIB6HhSzZ7MRtxo10gA04UueKXGGVC3/FKa
LteFsh3doaguwx64+XLrjZMKYa2AAOsgNLwLr5G1L5y0VGfzVSi+Gax9V7jkPog6Lm1OgNO+aaNt
RxRcqp6Nk6lqcPhVNEOdrvVZI8p+Q49hFSj2kVn1QW1GcVhyoWJkmxXJrAJHgvlpguYNOBI1v2Eo
O8xlDWDK7h7nDXn92JBCNSnLlvCqDRbDFn39BB7MZoQRWR5BL8CVAHckAaX1oK85LBtKCo9ma/Yn
7PKHgKrm8CoNTChF1gXEqhm0JJ6qrBSOdc/TLQ7lh0+rB9CJpViSKIQ0SWGyGpwToa9xIVDJrNTX
B3Srb2coLDacqxwznavIhnnJpg5c0wFohj3bg9+W370jOxcPtx0IEaKlGY2DhIqLg9Dbc8ugoQkH
vIpDAwRRJ9KvJY3uggqH4n3OEueh+pYgtICX4D/yohyaHYplk+BAoUwRfI+0O4uw4RSgJqKT9RyT
Bgv34g1f+LLbiABBMZSzD2SmtF/cEDWHHLuw5TENLmA11xpIfCHMKX1AIlnF1wjAoh9uc+kPSsRR
O90IdJKUaJzIv54Eeoj2eSrkxWoVk1yP8sCY+8n2rfO6hnVTVV+BA+MtjqzxqUktOXOQZ3kKIl34
0JapKKSXvKBxBpjgHv+yeD6iri6E6qfkmjQO1KU4/gR0Bxm5byAGWJMSPybsVhrMuSnkWBfN2EfP
uCWAkyjxQRc0r2Uw4HzlaGRGfuRgXXqg56s/eYysfdXNfUUo7VMy37ibR+QVMd1yQF1J28gIpfRM
gKF3Eduxt5rvWh1MsozVzeYEmNId442qHzwh65CMtmXNQW8rOmcoYdxqKve3EQBXH6TsgAoL5Z9R
JYEkZ46CzR6gBBgrZi7DgoRcmkvZWK3An6kqn7F1+QoBZ2cJEJ+oDWcpm3Uxs9vvLlMKWRHqbISQ
hV/fIwM6SjJBvp6c27ZUKJV5r9dzddQGHcAYfUhjAaq5RZ1s/b2hRICASXF6JNPRiSgbg8m1rmtn
oUA8pPo4KrnkfYwMu4nf+OKvyiXpZWgjyiCLPhYqlcSyAIXy+YkfrZq5iuZBeaVaR/2J2YaQJFxK
WpE8HQKA1KPERNE/WhtgKKWzVe7NNNjQDONWb6Y2VRC6HbnB20V9GMeyqUs/5BVDWwgWivEXZxes
Wjq+OHgzabCSl2eXxRrqexT/XNB2h7n0vmYxk1KJ80x6Glx4+W6HQmXFlbPswkDh2wFJnXs3BVdw
FsU72OT3LB70UfPo7xLNTccYBvWjuHBHdOLi8yCPixN5uxEjw8yVhkFDv3I4I11+UMIzcrvpcaBF
jjBgCp/7UPfjx+R83mjSyMNGUMaG1avdwTPvAxbYl4G2pySDzSMB1XmCm46+e2pZBEQF8L7xh2/H
9+DvvR9n+4APp78Ko/ZmSMS3Ybydhtxa6wpgvkLrgOFxRkspPYD4graV2OJMVT6syo4oTmCyPbTA
vOCPO5pP9+dIb9GDzLYRiDUoUXvKeogbwmGNub8HeByeP/UU6Skpxwx3xoEPorPmXQYQXnqAcuWE
oGjvChVg4LDsOEfJlk4cJNNOZZhGpp1dQsfVzuSIsbmQHuz14zp9+vg5DyGrTjk7RbMo9wn2O7Hm
IzfFlbmi1MEKROa2CY2NNU5iMkuNW1+5wwO/rQ7vJW3syOQUviMD1CtIYbrmp1JBO7Y/JDBpz1vY
AzixBm1dHCNiQ6ycGphXkZeZoesIAiGnS7pBkIn28bOtXhlaAVjZcX2ldM2E2cDdOTaJOLXdDQd2
2Og42ycEX1ZKX5+BYvCHzme9J74j1FxnBG4Kh2JLBAqwEKWJ/7qYizJYUfi6/jqqmV+hANtBJ1Fk
knpldr3lbxqAHFRFt0jvP+1mJh6UgDt7MwgIL6n4f+dZ6hHcJIqrU9K3ZnaHnV+BczI6hpsLqBg8
mq0yduEVbNi6Ifs8EMkxceFYAoyTQmPNsa3tLXWLyoxkdddFXAepV6GCZzpXcmxxWWie8F2T5zU4
yPvZR6f6NFlmruEMeA9WjX1ohC0NaUsjnlim3A5jDJy8Bbh9Z+8bwJ/gtJxPdhcCKp4dmIFcdSSp
+TI9p8ogLybCJicI3j97seR9aSsthg4aHLgOkV9ziH/GI/u74Ee0w/jBsPnedbkdcJhHI4oPUN26
EC9YS9yZe8wXWPLgKhs1OK+uhN/+EIuFq3YTT74G+iwHEnZfoIJsYZTdmvtqzsE0+RZb7AoeLQpU
766n78mRDEtcupzVAgMiEbOtPTwgHKrNxjucTIiihm7qBC2101tIzNrYXxeeC/AeVtlKDNmwj2a1
oUQ9zCEDVBl0OmR/wVE1SjP2h8//0HAqHm+mv1aWJdFP7FYvqe9le7fHJYdk7OTOR8hxo2z1lGSF
dkPadUwyd956PHgLLP32m9iLVCkrCdpFiDl2/AeAnWg1+gHBSf4GyWc2aiCGr/gmdiRkcQs9JiIy
BNU0cKeRbHUC04K1MjNU0cv3+wReEyZt5p1H9d/2hY9Txxn5V+MiuUgzgU4LbomesZ4Sn0xFKCob
6XtUC39tD71ABLTToz+yT7sG80A/WrIr+3wyIZxGroW/qFiHNnylkwdezI3dqY5yKOsB/f6In3DR
7vze1BiS0AGvbHmNkK/To70eMAxR899NjqDIBEVMiNrUZsba4SyawzUm05EH3+0WnqzVGjPdhM+c
67OoRK9IqKgMX4DivDXOern/OWRQQOv+wVuB9VWN3hUFHy0Fhz4vknyynuABkBFo51kjbiP8HIBX
1XKeDDLvKXhUpAwbZ5mDnZoOsME96yvqDIbknNn7oKtcT7DgwCnP0xTiIEtg8BqnSxiJH0XSkXyD
3MPmcFE6+EoxLZ8s2l35V2Rx9f67dPzq8NkzE1p+m011N2Zes3wQQnE+EckTSTmF8GE5wRTUheIR
f+qO6uVs8MXkRll9nH5fS2VjfCNncvsGaufx6cSsLFs1XT8vmCTd5rDL6SK2h+GUKYUkpMJc8+zQ
on6Sb/URhkpONnYOPUTtyNybeG6DUWm8EbaboJS3ynTUiz0YBEmdkUFZcVOhSVET8msrKutyW/q5
ijITVg5zlgSHTwk3Vz+bUtRmjTooUJ9vj61pZfR9uVEF7OJwMJJaYFj+Xegor9oCGuBpytz1SQJI
gtaNOYc9dOLwp+vpGR576AVxLrEdMoWoPh+lzKNQJIB5ssMpF5HfXCv8hKORwK1WmSCb2HZu8Wxx
56uLYo7aDsNk3t7ECYqpMQI4xGbpcl6Qy2E6Il8nMvVWt8YPZAYbhGfgYQApmPC8Ii7Zk66GJZEI
Nd+I19/7iK9ToKQQzX2ddxJucpqpGWwHTjY7Ih1dYGxZ0fZtqWm7jjAo+ZtsrHirsZy3KyGSQry7
OdoQZ4LK8PH6IEtv+IQ99Kh6y2NSwktp2gnJ8TcpZugYGVvn/x+8sLCJaxpcuosuJu1uu2zlNVQq
Ow9y9XKQzNPMy+7guMMayybt9SRxtq4AmBSVGZSZ7ke/sm3OdqbtPCjOfyGMzf2rOG4h8FrP6Mkv
mOCipqyQAzs7WwEGcLjgRqNT6W+Uz7dD6PtsuSWKFLVK74jFxNyl6e9buzZchW9Z+Q6p8uZICnoM
E+vgBUd6O8BGifRZDyn61Q/pwaGrYu3hZKDY7ZTzVlL/jzZIr88QKbDVvxRLNEGX+UOeuKxR98N3
2FKjFD6N5QS0E5q8BQFqMDDH9IEHdSta6KZwFEyEkXonlyZQC6H1Q6FCzkvguKh1SZ9a7IxOXoE9
jSUNdo0HBKpWWbFu9SBEGIihLLSKy573qC14/f4w9kP7XflDlA795OqRnS8Me9SSSpSyDULtQRQZ
m2lg2oIr2PutVT+apMHSaSzAN+qlx/kkuroiZgmhoOQs/N1xF3ERK5y1iWo3ea5yewnAmfyH3q4e
B/HKFWZ/LcDEfykHjWIOAmIQtnDqPc56OMicnXLti1lZ1TOHr3jHnNwSndS37vf3+G0neBsPh9kA
YbBt9VUpKo8UwkgVWtlLhiOIGYrOHUj/P32lNeFP/WoBCWk/h8GvgU8bYejQfNDIPc0ovqyYwCYx
1Hjl9Nfsfei+ZDlY4+8LkpMGUUzKiQE8qR5Tt9SuWqDzyx3uhIgmKJwtTIAHfo1Im7EdnYGCzGNi
b8Ub7WzASspHZTlH+VRB5Yn0bv2Y91aVyE2WkKB6yms1wxqMrhXmctPoXMqveWJtCnPlSx8SofAf
+Uqn/GIaTOPAmDruAjVOVR5uSrQMmV9/UiCQYxUIY+FbTx9F5Ef2Uox0KGkK5bCm/pe5BL8pT2QZ
FJb8KNawHi/lChSF7XoBDMEB/jSkfXfJJGid2xKcrkI//7CGHMOoGYm8J2+LrfMuOYZJ3R/DJlKt
lgXnGQz/9zYwjfBl4naUUWU/xsG9wUO3xsF7Aqfbn4xO8whBBuvcb+mPWAmaC3oVymE1LORVXWSH
ZhhLNmNYSnwoOXENnlYin5Fval79XLIhpciTMMs7UG7nAYdZnq7PFplEwWECw5PPz+hZzv6OS+k2
45faK9ZCFp60LMSd/EI8SNeZZcOzSaZjqS2bVCd9syOe3w0N3i2EkEV762G87TOqobC6kBN7eM/1
XVEMeTvSekrBjcpW2F/NDYZ3JxDXZ+HbxLMUC4/p+e/AFiDbVJvcUP809SGjauyA2PgT40iV2ZAV
OEIprLXkADhrDl4XbiXOjsQ0MRv0JSVZXTfhBIbWF6mXFxGHy7jrA+HoZDvqR7m28XlKsoqI4dSv
4SObtNsoq9iiT5BBoh3X1qm1X4BV2F2v1g4Q+O1dWUvodm2pj6deE5jwHTeV0/nlkKAq2xP4o3H1
vb72F3An/f85FA3ezMN/ijUXD8oOCme0W/mUql6BoqsrYjUWuZU862nUrrL5eYE92jgctHLgXUoo
fJG8Wn/sRAJaDYw4z6iKRjd7ju2cVyOCcpOuzSHUJu43iJQnYVmotmSEOe871W5qd9wFZtGX8Jg3
84wGRMafXKuCz0PW+jVbyFDw3q0E/+/iL+UUGOvLlNjX6e5hLq4EmqQXzpiMuJcfj0hVGZdyeUuj
SmxAUuCMtdoWPUt+NHwDO0aV0s0fkJuU6QG6Fap00nyaOuNHR7FCG6urAwlzNOuQxXyMZryE6uwO
iK0YK/Tton4HDykqv2oh9lm2ji/I7Kxp42JFBv4VC4lh0NtiqrICdQbFMdD21Nv+E2mgLskwtZwK
1T9OGYdpZiRPXsRWYWWZL7kM+KkMqm5qvBruKJcbpy5rPGCkvyLtTQZNNl2ladjO0YHwnMPK1dV4
VCy9p8HJ5jI5knhC8eFSz7mlk/dC1dlSFAvfOFA3jyjT4+BpMgSUl89ClV43Wy+W57YrPnpeLbx3
gEadjQm/cwNHiIb4QMnNLaSCUTPEjQOo7jbFDp6J8XKb6iAwd2UUQqTbIklMB6WHBwVgSX2l/8Dm
QoMKQonSvRoj0Q3qlN9/ZY5u4+2hw914zRdnuPMYD92dGC+lrVIKBfvcmeqgCCBtvxbn8/QkOZED
DmSW4CabwgnvWoyiTftDVsmUUPRzADqCE93r4m2tB5D6ESAfLfJha5wYbELyUBaFtGKYlT4fypBD
3faI2bSR+GEg3LwW0HnZc0CKS4SdeY4q454jlE2qgCK3CSfpSgsjx1XbzLU03p2pRehXIT4+Krex
+BNy9XHJdhpdPiUFQmzZnvrNXhTRSPLAK4G7aqZx8gUirqmOh15TUho/7JsZ/a3ztwMEndlzWaju
MXxWsnYC+atrc6/ANWjHobnmAUBe7r6Xr4Sm5GhNpLVc2RT2vr9jDsu+Gwmp/jl+aP5e+E7lR9+3
00Qn4f/Dhvdcp+fewzs2TEZTmkd0ltYCufh8ywhlvWfbxQfMUo2yG8hpdkBfUw2MP7qwncbaRvom
X1sdDjHZn38JLVoPfI0rD0dUrQqnhQhpXM34Ch8yn2g4829XCZs3wzCWY1zZQPrQgLuwa1eM+DBD
f31nCOVP2WoszqHBddz8fvSEpblTW22wuvPm779MiAMULvuRiJEjVutSbV1hxXS9qCaFm9ce8BYG
jVqAa2LqKDy9zek2A4qa82d8icHgc4ZCuEtzs0zcqebsj7+40pdoQd/ZohE1a66uRxKnzV+E05Pd
IuovRiGHF3g1FQ939PzTKsuLZBl/86/QAOFbxivPTiWtWaEtlqhjqLtYkvIL9BHe/3fT0NeEbG5G
mOPS6TH/zqGLgUPIbZY8VIZZUX3zyUBWIo2ljwlW2OJJl+OnX76ORFgf4dJV1NCCJwwRE8uJXOlH
FoVFbRwlAwQLpa9vm6Y4x1M45fMS6nFkK9tG8YKMjEEYejtysioTbaJWLKPIiLeOZaA30vLGUfUW
gh78wnB6I2d22ApZh8ssH24Zp2bJ2OjMsPHzW4JTmM378eZrKbI7ZMr33dtP1mZVHN9UNjOJ3abv
Druikllcgt2fjVmuonk3S4WgWkII+auwO55KdjGe/JYufbjZAT+5P00kwGRXndWolXRkUNiT+PqZ
ukY96VKSmHqGU80y7HFuPCr3z+u/KG405HV1FcWqf9sgPslYlAv2h7sDn96KnFv/6af9SF2ZqkLW
P//8FxbzqP7xuaLBJRodlIteLKcKUHllTYmxtlQEw/W+qwqYJHJG3JgzRtL8B8D1qdvmwr2nVzB+
TTIyYBdDMs+G5Cq5IcSYFsI392QDdshefPBlnyqsZ2t+frIiumZedGQ2MikoTAcWcJIGkH4zpjBy
nFMZnoXdJJy/r0SUZOPsDKS9MUnWjN76ZGJZLrPfMLjuTIztBndWy2IT6T9p+AY6g/0ch8AK+FBS
CoKSkV2GCKwhjz/TFLXPxM62ICW+NjD4TTFMtKoYRMzC8u98+IsgqMJh2q+HfgTSlpBF8jqJ4M1F
Gdw1QXRSfdFiT68pgYiEZEbS0tNVoqJeDTt2qJKR4fzqygjX7oShz+yVX90fzRpbIu0N/tviU5AI
fN32l9gB5We1Y8wd+Sa01hMMFhvkrqwk2y1zqNtCyugRjZ+5S+7tqpWvQkUst9ywdZzpxSzWm8nI
BUrqnB5UOJzu5+NN8hlVxif5ED9Eae7QKOiXQudBap/o6Q/oNSAtePuWQJ78K1HJ2MX30yxPHJ3P
tqt6SbIQ+6PLN/S23EvCxE0d6ED5awsEbNdIAsz3tgyETZIg9gopz8YPVqrO9L/rrwmZ7Bfvy9ho
URwzyt6sUxjp8/nU5IqixD59zgSIhsuPbK1V55uJolOzXEA1qgvxpplnD6FtyXcYxq9pH2v5Xeil
SHVlMLHiClYplrGJFRM+pXXmSTVrhB16qEd84EmcKWQ2uI0FCR8/154JFD2UhQg+jtJsU5d/PVR8
ux0lXMioIeWpmU+2zt0aJSdN/9/b4ZJrpVXksIkf9AWVhTIFfUq3+SW9nWevM2fiPyg9giRlGPuA
tddO+nc4voxsiW1UlUnanCSHr75Z0WQ+s0MxnP8OO/dbFyimSDRVqcBQ8cb2mWDSkeGZwJbtRRDi
M8vcy7SjqdaEIyOtIy/rZc0eyIm2AFIEs5FBBN94My4K6pR3+u8XGu9fWPwG4s5hL8yhdZtx/7dI
yOzhZILStvz3lsf7qDQvzFQdOTNa4YaFJUjz9TvDOUDGARR5MWNolkqe2bWb7tKmg/dOOwaF2d7j
FQcveQuWaUY1bF9QTX9BEjVrLwRc4lqA/18kNktMzmD+yybUGBADR7tnZBXE6D4aNVh1+B5SkoDx
30ZDZiyc6ItPsAzaXPauGRNmqBhDklI8W3sBaNQKVG4ePaY48zyk0eb1GlUIgtM20ebgZzvY/6nB
cYnrWqZ3w3ZB4iyN3k47AniKglc41FySHkC5QMZfHBLD+kL+pkxI4xwYnjc6IpGnM7lLgO3dXcqZ
BbR3D6sO91S194Nh6rmTnc+aO5Q8t9rBXjLqLHXkRsjsvAHM05B5haHGXOqHKJKD+rt39lt+RfDr
D+VVT3AgDroJExdDqQ57MzRlgmh1j0re/a+BsjdKyZj659j/wDcAW6npq2M4CSVuaMwkRzWS2fx3
wbtvTTWBPgM7TUVlfO21uvDzsW7MkxibdSlyVt17a2CkKhA2sUCE3DuAk9gwDyrEde2l7TKagokB
ouRR2vzmlTtiDuO0mecjE3+o3HVg9Vmj73ejZ+psfC97yrdnp1N0pEza6+AgyQy5A7ay9Yas75P6
kYGQ8tJ03b30dRhNCg5HB4v6W3SxGeZoa8qnoawn4cDVDEZlC54q2H/H7IyZtYIUs5HcULotx7x8
PtxMbF3v9gAKqYI4MC5RszdJ1hMtfcJB7WrvviZzp4+fzhwM6J+I6reIcEvm21aICka4r35Qgyh8
pSxEB4BsGepnFb1aPj2ABMGrXWvF4ilOMg7XCrkv6Kht1Ivo+OrPIwWNe88kTpXSvp6QcIZCmi8d
hyUg8sK4p1sOEszfl6ZInECT6vEhppF479KChASomXDYQzwGQyKh7VLZfkREpE8pPVJeHYnCzgvR
gBaoNlkHgvEv8mKQTU7l9427iG+13xS2h6pyHxMYu6oewda0jwaNkiiU8k3VmN7zngDan6V398sa
4rCKRq3lmk4Io14XLfsMbrCfQHvmmvujSUb+LzSS+l7rBEONMpiK1KSQvkmx+5CUOloX44NoFitj
NjTNKx34S2QVwJHszuOse2v0IUobHDHqwNYULHQ3S3x7leACeNrNFzA4cwih3fjp+DxCFz+K306F
CiHy6svJkUOhjTrTVjpzXIUg2K0pzHpPhkKpJQ/ETI75/2m4n8kvbEEE1IPaJLDRaakXZiEAT7Ko
rpa82QMw57Cr27eQ1Zp0auaZTtKyXTNkk7c02YRRin7FBsDYMNOrlp4R4oTbc7UnUjJhzJIcGUQn
pyqlBjvY2Rdhjiihc2xdpnIZWKiU3DUYDl6machY3s+8TIUYlBT6dAzluK+jzutp1GIcs4zK/oWl
L2qoe/UopLf5N0DixUJ4k0suRbVwZCeT0Vu4uID6sqvyDOnVHMD0FrcmddA+niolrL8H1G6N7+4P
lCkGGh1MJDv3fxBq8MsEZSMRiyTxjceIl1rkHKTIDwlHYUO1TYdK8NQilpv8SapAhjlXEKZ1VutX
zLViLMK6K0C6HVvODMpgaS5FIqJiEiYsBYrrvvUZGMSGQeinyc51CSCgStSHN9lFgE8WgsKWXGSy
G2ka8Lfaf1bfPs4ME1qsyvYRsYld82eEdt13/Bq468g4613erMm4vsKIEHJ2NbChZLMMWaTp8+JF
wRBV+H4jFAjWxpJ6iUlX4uxM5Y1xM50O6jx8WjlXtWOHJS0IGO9lCRCW1PNSpnMTL5K1SHs9l9HB
kAJVoWHoTkzU1ynP60QVvArc7P8qORnc7zMWcJz7qnOiaBHZ5rvIccrybzpXCUQ8QQoDQ2dzJ5gK
8xmBqP6wQ8Ell193orskZ8KfiFZadKO6GrTAsMu04oJnKXaIFfOhP/1HbDefLlAiQUQD3ayxRmvg
RUEKAWbusy/M05/DuBg3ukC76zzXpLUDt92T9Rhv4kkDzpnVcHMFDHBriHsATUKzHlh1CS/WgfOI
sFOP4H3+mIdiXhBrGe0jZ3X8qyrB0LUTdnC3OKAQvd9LLJPvqqWSYdeS/6B31ecrx3AMvE/1xgIw
S5C4B+V3VUUdaT/A2X0yBWKBh7JyXnSZNAvesRljzEaLioXXgHZIfSnD+4B2ymG9oGQicFEVOTqs
5qbY8Hv7bCFuDl40Ocicy6VL2XRFjZpC6Fge9qzkCmtv/84JusSZcMWJ1cRZt0o6E/qgRPm+RNRM
gqWfBg2eoKj+caqNHlMqT9jFpUzIniyAd7atGfEfp/BnmanP9CvApS16WdjGK9hrcbvxZVsAtiIC
bmAB0Gbh+KxY4Nujk3vsw2DRNXkbj16ZkoFFrfEl7wjlHxex352UMVVenO/UKCEHSv5zdfo6Uwj0
itxijOld0EakvxjrZV+PJ9SCcJCu6RrWn1orjv3WklgmPlYTB1LWjZnqi56JPP3ck/tN0ZiEG8iX
9p8FzV5TQsFwtsIodBxX213z4oESSa01vDDE3QG6c218dn5QBcamBy90sQ5kuaabs6FOttDZmywt
z4G1LFS7Yjjq+nSD+KIpIM429j+FuboyOh0rTNZHvt2ShoFVaaZhHCctWkWMK6a9sPljSvSvIATm
w+9X2n1bJqbZljP7fuHCXOJFJdSjnD2LFfoWYJatqbgh/anVijPlVAVopUTHqjZk7QyL7AEFXjnv
95cRrzYD86MAHv23VHvhWRB5wtZAFUOKMakMxM2Usza5y5eKrNQISavJl4EfZob5WjovwjuyM9jE
nDf8zVWpoLCqe85D9w23Mt0+qFG0xK+etXRNpW8TGREFNcDH75IkMtEbxF0OvNmjkTgpOZOZfzrh
od/g7tXc4MLilsfNQ5RR7Wf4DMes5nnqfm1iAQW/vf3x5Bzkgz3Dakm1E7q1idaCJzatKcRqOPEi
dW/OnblKurNS+atnX+O/u2eUmJ++7UZs1hk5MG94XeaT3WYETNBIcg0idjHrutgr0CBHR5R8mhzN
vkWfX8nWTBP8hvyzrDGqjYdU9LjO9hPCqz2aulQRlEZIfoN1chVxV+tzNNXh0nYCOY/A5F+lsou4
jRTt/fBp+LXSlUOO2LjZJZIEjQEGhJHdIxCDsjRtIF9VT1wJ3KelMqWthEnmU0qyENtog6JfETGH
ZSZZCz93/8Tor3ZTW4sBQPf4ZfBJLBvGDsbVFROTxExCDzv5QBUXRi3epRCzrceTPXxouAx+L8Xc
83FOVBCMcyhyZJ9t6rPkPdlXHlbeiuYpm5ooB8agwJ/ulIDTaRS0KfA/7jtRWX+ptmqt2Png6XWr
LU6Ftwj8b+U8bEU+Xnq/DOSwID6zJQwUH25BcT7JP+SXlvwH0QwU0oMHFNFmHsboWpA91ulVcWS4
D0ZKaV+MkvQdbtQ5TUQU7jHbsoSkcFnq/htjNBDzgbrJwjeEioVO593BTrgsmwwYbtRDPG0SkkCz
OcN5MA6I4aMprwjPlCcL5qMChwb+6pj11OWTpzSsPjH3GBakp/l79MJ28tnSfAlzT1Qpt6/8Xs5a
GczJZtM06cmsvnC42wdPGO7CRLmt7zHe2NPyCZPTWBw5lOsqmts0kWj3MIE0lR39lIw3jGGiIDI+
CrEm22v9eBUPV9SPBuN3ss6/t0Nt9DzDRUwD1ogjNIUKqGMdl2mRSDc78raqDe1Pet5t6xSWSgcm
wVrNaY2iclE1tewFmxxLMk9gpMhaRGnEFZOJV2mzj7Ef6/9PLrH5lqoEVhpmlrO+0HhiWeZAg2Uj
4Lr0jbDQ/rkbJvBV2xs7UEnGTr+hHG2UaSWsUARs9daP9Bt+8SJ518Ih3Xij9+IVRnb97I4HDhg5
ggAzWzx/PTxJzUsaU3R5zV5YqBxj5e+tAudxoBaZMzQVNpqoXrTPr5FVC/3EXq5Tv2w8z50CrD5q
0QrnZIiFzmo+qFj+uGvGdCxcaTED/PM+mJkO8/wVSqV84++7Kfkd8nUrekubzfpmuT0utnrit8wm
C7BqlQecK6yar+etuoAet41+B81tJDfKQA+Y8376I2Oksj/0l0kW65oShl4R+gZCHkwR8c/T3gQE
Gd9PL2w6wKpFNLO3UA5iYoaW8boB2qDqsNbYK+TLbkO1UQvQGMANXb8kryrdS8QCmf1lPdZspzYX
tFnCB+kW1tnCu8jfYeyxhTqTg4ElTnSo415DvA63yJmjvhTMbfmWPHpC24H/kq4gZ9G/+7mUBuAQ
nMjpHygAX16lcx8FRfiQ00CpoYhvHzYdYt7ApzLmQIrK5BAIKFIHigueDLmP9pqlB4hzvUaITB65
NwqalpIQB6htX8PPQkrqGubMTdK2mqyyC/JA2UY9I4IoMN3YDmVLZ/Xg8Ks2sk6vRg6T15wu6SC7
nL7Z7D20qdYZkyad8+2THuKmD8yvqHYGWe5DkYjOCEbedaqSuJ/tShVGNhLHFok3py89zHHNHLb1
6EN19qIe9rU7l5XDIDEVPd933wsrYdJEAiwrIuVBzShD13XDztdl9xmh0pyMqXjcpxfUvy9pNfJs
HXOPp9FpjDjRjmoJXVnvf50MxHSeAPgixZZPf/lmMPf945O4aAY8Bx9Dz1RfGBL0aAiMEiI3Mh+e
Nv6TP6M2XKFcK46HBM/Tf2OKvGer1edX9XnP+hXNFdXU1kpzbdfbo5Ew74nVnFOK2aCvmKLVOWhm
IENTN7/0TUw=
`protect end_protected
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2925.vhd,v 1.2 2001-10-26 16:30:24 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c02s02b00x00p04n01i02925ent IS
END c02s02b00x00p04n01i02925ent;
ARCHITECTURE c02s02b00x00p04n01i02925arch OF c02s02b00x00p04n01i02925ent IS
function L return POSITIVE;
function L return POSITIVE is
architecture AB of E is -- Failure_here
-- ERROR : body declaration not allowed in subprogram declarations
signal S : REAL;
begin
S <= 2.4;
end AB;
end L;
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c02s02b00x00p04n01i02925 - Body declarations are not allowed within subprogram declaration."
severity ERROR;
wait;
END PROCESS TESTING;
END c02s02b00x00p04n01i02925arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2925.vhd,v 1.2 2001-10-26 16:30:24 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c02s02b00x00p04n01i02925ent IS
END c02s02b00x00p04n01i02925ent;
ARCHITECTURE c02s02b00x00p04n01i02925arch OF c02s02b00x00p04n01i02925ent IS
function L return POSITIVE;
function L return POSITIVE is
architecture AB of E is -- Failure_here
-- ERROR : body declaration not allowed in subprogram declarations
signal S : REAL;
begin
S <= 2.4;
end AB;
end L;
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c02s02b00x00p04n01i02925 - Body declarations are not allowed within subprogram declaration."
severity ERROR;
wait;
END PROCESS TESTING;
END c02s02b00x00p04n01i02925arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2925.vhd,v 1.2 2001-10-26 16:30:24 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c02s02b00x00p04n01i02925ent IS
END c02s02b00x00p04n01i02925ent;
ARCHITECTURE c02s02b00x00p04n01i02925arch OF c02s02b00x00p04n01i02925ent IS
function L return POSITIVE;
function L return POSITIVE is
architecture AB of E is -- Failure_here
-- ERROR : body declaration not allowed in subprogram declarations
signal S : REAL;
begin
S <= 2.4;
end AB;
end L;
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c02s02b00x00p04n01i02925 - Body declarations are not allowed within subprogram declaration."
severity ERROR;
wait;
END PROCESS TESTING;
END c02s02b00x00p04n01i02925arch;
|
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := altera;
constant CFG_MEMTECH : integer := altera;
constant CFG_PADTECH : integer := altera;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := inferred;
constant CFG_CLKMUL : integer := 2;
constant CFG_CLKDIV : integer := 2;
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 0;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 2 + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 0;
constant CFG_SVT : integer := 0;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NOTAG : integer := 0;
constant CFG_NWP : integer := (2);
constant CFG_PWD : integer := 0*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 2;
constant CFG_ISETSZ : integer := 2;
constant CFG_ILINE : integer := 8;
constant CFG_IREPL : integer := 0;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 2;
constant CFG_DSETSZ : integer := 2;
constant CFG_DLINE : integer := 8;
constant CFG_DREPL : integer := 0;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 1 + 0 + 4*0;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 0;
constant CFG_ITLBNUM : integer := 2;
constant CFG_DTLBNUM : integer := 2;
constant CFG_TLB_TYPE : integer := 1 + 0*2;
constant CFG_TLB_REP : integer := 1;
constant CFG_MMU_PAGE : integer := 0;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 0;
constant CFG_ATBSZ : integer := 0;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 2;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 0;
constant CFG_FPNPEN : integer := 0;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- DSU UART
constant CFG_AHB_UART : integer := 1;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 0;
-- Ethernet DSU
constant CFG_DSU_ETH : integer := 0 + 0 + 0;
constant CFG_ETH_BUF : integer := 1;
constant CFG_ETH_IPM : integer := 16#C0A8#;
constant CFG_ETH_IPL : integer := 16#0033#;
constant CFG_ETH_ENM : integer := 16#020000#;
constant CFG_ETH_ENL : integer := 16#000009#;
-- PROM/SRAM controller
constant CFG_SRCTRL : integer := 1;
constant CFG_SRCTRL_PROMWS : integer := (3);
constant CFG_SRCTRL_RAMWS : integer := (2);
constant CFG_SRCTRL_IOWS : integer := (0);
constant CFG_SRCTRL_RMW : integer := 1;
constant CFG_SRCTRL_8BIT : integer := 0;
constant CFG_SRCTRL_SRBANKS : integer := 1;
constant CFG_SRCTRL_BANKSZ : integer := 0;
constant CFG_SRCTRL_ROMASEL : integer := (19);
-- LEON2 memory controller
constant CFG_MCTRL_LEON2 : integer := 0;
constant CFG_MCTRL_RAM8BIT : integer := 0;
constant CFG_MCTRL_RAM16BIT : integer := 0;
constant CFG_MCTRL_5CS : integer := 0;
constant CFG_MCTRL_SDEN : integer := 0;
constant CFG_MCTRL_SEPBUS : integer := 0;
constant CFG_MCTRL_INVCLK : integer := 0;
constant CFG_MCTRL_SD64 : integer := 0;
constant CFG_MCTRL_PAGE : integer := 0 + 0;
-- SDRAM controller
constant CFG_SDCTRL : integer := 0;
constant CFG_SDCTRL_INVCLK : integer := 0;
constant CFG_SDCTRL_SD64 : integer := 0;
constant CFG_SDCTRL_PAGE : integer := 0 + 0;
-- AHB ROM
constant CFG_AHBROMEN : integer := 0;
constant CFG_AHBROPIP : integer := 0;
constant CFG_AHBRODDR : integer := 16#000#;
constant CFG_ROMADDR : integer := 16#000#;
constant CFG_ROMMASK : integer := 16#E00# + 16#000#;
-- AHB RAM
constant CFG_AHBRAMEN : integer := 0;
constant CFG_AHBRSZ : integer := 1;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- Gaisler Ethernet core
constant CFG_GRETH : integer := 0;
constant CFG_GRETH1G : integer := 0;
constant CFG_ETH_FIFO : integer := 8;
-- CAN 2.0 interface
constant CFG_CAN : integer := 0;
constant CFG_CANIO : integer := 16#0#;
constant CFG_CANIRQ : integer := 0;
constant CFG_CANLOOP : integer := 0;
constant CFG_CAN_SYNCRST : integer := 0;
constant CFG_CANFT : integer := 0;
-- PCI interface
constant CFG_PCI : integer := 0;
constant CFG_PCIVID : integer := 16#0#;
constant CFG_PCIDID : integer := 16#0#;
constant CFG_PCIDEPTH : integer := 8;
constant CFG_PCI_MTF : integer := 1;
-- PCI arbiter
constant CFG_PCI_ARB : integer := 0;
constant CFG_PCI_ARBAPB : integer := 0;
constant CFG_PCI_ARB_NGNT : integer := 4;
-- PCI trace buffer
constant CFG_PCITBUFEN: integer := 0;
constant CFG_PCITBUF : integer := 256;
-- Spacewire interface
constant CFG_SPW_EN : integer := 0;
constant CFG_SPW_NUM : integer := 1;
constant CFG_SPW_AHBFIFO : integer := 4;
constant CFG_SPW_RXFIFO : integer := 16;
constant CFG_SPW_RMAP : integer := 0;
constant CFG_SPW_RMAPBUF : integer := 4;
constant CFG_SPW_RMAPCRC : integer := 0;
constant CFG_SPW_NETLIST : integer := 0;
constant CFG_SPW_FT : integer := 0;
constant CFG_SPW_GRSPW : integer := 2;
constant CFG_SPW_RXUNAL : integer := 0;
constant CFG_SPW_DMACHAN : integer := 1;
constant CFG_SPW_PORTS : integer := 1;
constant CFG_SPW_INPUT : integer := 2;
constant CFG_SPW_OUTPUT : integer := 0;
constant CFG_SPW_RTSAME : integer := 0;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 1;
-- UART 2
constant CFG_UART2_ENABLE : integer := 0;
constant CFG_UART2_FIFO : integer := 1;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (8);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 0;
constant CFG_GPT_WDOG : integer := 16#0#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 0;
constant CFG_GRGPIO_IMASK : integer := 16#0000#;
constant CFG_GRGPIO_WIDTH : integer := 1;
-- GRLIB debugging
constant CFG_DUART : integer := 0;
end;
|
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_6_e
--
-- Generated
-- by: wig
-- on: Mon Jun 26 05:50:09 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../generic.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_6_e-rtl-a.vhd,v 1.4 2006/06/26 07:42:18 wig Exp $
-- $Date: 2006/06/26 07:42:18 $
-- $Log: inst_6_e-rtl-a.vhd,v $
-- Revision 1.4 2006/06/26 07:42:18 wig
-- Updated io, generic and mde_tests testcases
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.90 2006/06/22 07:13:21 wig Exp
--
-- Generator: mix_0.pl Revision: 1.46 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of inst_6_e
--
architecture rtl of inst_6_e is
--
-- Generated Constant Declarations
--
--
-- Generated Components
--
--
-- Generated Signal List
--
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
--
-- Generated Signal Assignments
--
--
-- Generated Instances and Port Mappings
--
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
-- -------------------------------------------------------------
--
-- Generated Configuration for inst_3_e
--
-- Generated
-- by: wig
-- on: Fri Jul 15 13:54:30 2005
-- cmd: h:/work/eclipse/mix/mix_0.pl -nodelta ../macro.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_3_e-rtl-conf-c.vhd,v 1.2 2005/07/15 16:20:00 wig Exp $
-- $Date: 2005/07/15 16:20:00 $
-- $Log: inst_3_e-rtl-conf-c.vhd,v $
-- Revision 1.2 2005/07/15 16:20:00 wig
-- Update all testcases; still problems though
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.55 2005/07/13 15:38:34 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.36 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/conf
--
-- Start of Generated Configuration inst_3_e_rtl_conf / inst_3_e
--
configuration inst_3_e_rtl_conf of inst_3_e is
for rtl
-- Generated Configuration
end for;
end inst_3_e_rtl_conf;
--
-- End of Generated Configuration inst_3_e_rtl_conf
--
--
--!End of Configuration/ies
-- --------------------------------------------------------------
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: counter_fifo_synth.vhd
--
-- Description:
-- This is the demo testbench for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.STD_LOGIC_1164.ALL;
USE ieee.STD_LOGIC_unsigned.ALL;
USE IEEE.STD_LOGIC_arith.ALL;
USE ieee.numeric_std.ALL;
USE ieee.STD_LOGIC_misc.ALL;
LIBRARY std;
USE std.textio.ALL;
LIBRARY work;
USE work.counter_fifo_pkg.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY counter_fifo_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE simulation_arch OF counter_fifo_synth IS
-- FIFO interface signal declarations
SIGNAL wr_clk_i : STD_LOGIC;
SIGNAL rd_clk_i : STD_LOGIC;
SIGNAL rst : STD_LOGIC;
SIGNAL wr_en : STD_LOGIC;
SIGNAL rd_en : STD_LOGIC;
SIGNAL din : STD_LOGIC_VECTOR(32-1 DOWNTO 0);
SIGNAL dout : STD_LOGIC_VECTOR(32-1 DOWNTO 0);
SIGNAL full : STD_LOGIC;
SIGNAL empty : STD_LOGIC;
-- TB Signals
SIGNAL wr_data : STD_LOGIC_VECTOR(32-1 DOWNTO 0);
SIGNAL dout_i : STD_LOGIC_VECTOR(32-1 DOWNTO 0);
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL full_i : STD_LOGIC := '0';
SIGNAL empty_i : STD_LOGIC := '0';
SIGNAL almost_full_i : STD_LOGIC := '0';
SIGNAL almost_empty_i : STD_LOGIC := '0';
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL dout_chk_i : STD_LOGIC := '0';
SIGNAL rst_int_rd : STD_LOGIC := '0';
SIGNAL rst_int_wr : STD_LOGIC := '0';
SIGNAL rst_s_wr1 : STD_LOGIC := '0';
SIGNAL rst_s_wr2 : STD_LOGIC := '0';
SIGNAL rst_gen_rd : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL rst_s_wr3 : STD_LOGIC := '0';
SIGNAL rst_s_rd : STD_LOGIC := '0';
SIGNAL reset_en : STD_LOGIC := '0';
SIGNAL rst_async_wr1 : STD_LOGIC := '0';
SIGNAL rst_async_wr2 : STD_LOGIC := '0';
SIGNAL rst_async_wr3 : STD_LOGIC := '0';
SIGNAL rst_async_rd1 : STD_LOGIC := '0';
SIGNAL rst_async_rd2 : STD_LOGIC := '0';
SIGNAL rst_async_rd3 : STD_LOGIC := '0';
BEGIN
---- Reset generation logic -----
rst_int_wr <= rst_async_wr3 OR rst_s_wr3;
rst_int_rd <= rst_async_rd3 OR rst_s_rd;
--Testbench reset synchronization
PROCESS(rd_clk_i,RESET)
BEGIN
IF(RESET = '1') THEN
rst_async_rd1 <= '1';
rst_async_rd2 <= '1';
rst_async_rd3 <= '1';
ELSIF(rd_clk_i'event AND rd_clk_i='1') THEN
rst_async_rd1 <= RESET;
rst_async_rd2 <= rst_async_rd1;
rst_async_rd3 <= rst_async_rd2;
END IF;
END PROCESS;
PROCESS(wr_clk_i,RESET)
BEGIN
IF(RESET = '1') THEN
rst_async_wr1 <= '1';
rst_async_wr2 <= '1';
rst_async_wr3 <= '1';
ELSIF(wr_clk_i'event AND wr_clk_i='1') THEN
rst_async_wr1 <= RESET;
rst_async_wr2 <= rst_async_wr1;
rst_async_wr3 <= rst_async_wr2;
END IF;
END PROCESS;
--Soft reset for core and testbench
PROCESS(rd_clk_i)
BEGIN
IF(rd_clk_i'event AND rd_clk_i='1') THEN
rst_gen_rd <= rst_gen_rd + "1";
IF(reset_en = '1' AND AND_REDUCE(rst_gen_rd) = '1') THEN
rst_s_rd <= '1';
assert false
report "Reset applied..Memory Collision checks are not valid"
severity note;
ELSE
IF(AND_REDUCE(rst_gen_rd) = '1' AND rst_s_rd = '1') THEN
rst_s_rd <= '0';
END IF;
END IF;
END IF;
END PROCESS;
PROCESS(wr_clk_i)
BEGIN
IF(wr_clk_i'event AND wr_clk_i='1') THEN
rst_s_wr1 <= rst_s_rd;
rst_s_wr2 <= rst_s_wr1;
rst_s_wr3 <= rst_s_wr2;
IF(rst_s_wr3 = '1' AND rst_s_wr2 = '0') THEN
assert false
report "Reset removed..Memory Collision checks are valid"
severity note;
END IF;
END IF;
END PROCESS;
------------------
---- Clock buffers for testbench ----
wr_clk_i <= WR_CLK;
rd_clk_i <= RD_CLK;
------------------
rst <= RESET OR rst_s_rd AFTER 12 ns;
din <= wr_data;
dout_i <= dout;
wr_en <= wr_en_i;
rd_en <= rd_en_i;
full_i <= full;
empty_i <= empty;
fg_dg_nv: counter_fifo_dgen
GENERIC MAP (
C_DIN_WIDTH => 32,
C_DOUT_WIDTH => 32,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP ( -- Write Port
RESET => rst_int_wr,
WR_CLK => wr_clk_i,
PRC_WR_EN => prc_we_i,
FULL => full_i,
WR_EN => wr_en_i,
WR_DATA => wr_data
);
fg_dv_nv: counter_fifo_dverif
GENERIC MAP (
C_DOUT_WIDTH => 32,
C_DIN_WIDTH => 32,
C_USE_EMBEDDED_REG => 0,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP(
RESET => rst_int_rd,
RD_CLK => rd_clk_i,
PRC_RD_EN => prc_re_i,
RD_EN => rd_en_i,
EMPTY => empty_i,
DATA_OUT => dout_i,
DOUT_CHK => dout_chk_i
);
fg_pc_nv: counter_fifo_pctrl
GENERIC MAP (
AXI_CHANNEL => "Native",
C_APPLICATION_TYPE => 0,
C_DOUT_WIDTH => 32,
C_DIN_WIDTH => 32,
C_WR_PNTR_WIDTH => 9,
C_RD_PNTR_WIDTH => 9,
C_CH_TYPE => 0,
FREEZEON_ERROR => FREEZEON_ERROR,
TB_SEED => TB_SEED,
TB_STOP_CNT => TB_STOP_CNT
)
PORT MAP(
RESET_WR => rst_int_wr,
RESET_RD => rst_int_rd,
RESET_EN => reset_en,
WR_CLK => wr_clk_i,
RD_CLK => rd_clk_i,
PRC_WR_EN => prc_we_i,
PRC_RD_EN => prc_re_i,
FULL => full_i,
ALMOST_FULL => almost_full_i,
ALMOST_EMPTY => almost_empty_i,
DOUT_CHK => dout_chk_i,
EMPTY => empty_i,
DATA_IN => wr_data,
DATA_OUT => dout,
SIM_DONE => SIM_DONE,
STATUS => STATUS
);
counter_fifo_inst : counter_fifo_exdes
PORT MAP (
WR_CLK => wr_clk_i,
RD_CLK => rd_clk_i,
RST => rst,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
END ARCHITECTURE;
|
-------------------------------------------------------------------------------
-- $Id: axi_quad_spi.vhd
-------------------------------------------------------------------------------
-- axi_quad_spi.vhd - Entity and architecture
-------------------------------------------------------------------------------
--
-- *******************************************************************
-- ** (c) Copyright [2010] - [2012] Xilinx, Inc. All rights reserved.*
-- ** *
-- ** This file contains confidential and proprietary information *
-- ** of Xilinx, Inc. and is protected under U.S. and *
-- ** international copyright and other intellectual property *
-- ** laws. *
-- ** *
-- ** DISCLAIMER *
-- ** This disclaimer is not a license and does not grant any *
-- ** rights to the materials distributed herewith. Except as *
-- ** otherwise provided in a valid license issued to you by *
-- ** Xilinx, and to the maximum extent permitted by applicable *
-- ** law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND *
-- ** WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES *
-- ** AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING *
-- ** BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- *
-- ** INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and *
-- ** (2) Xilinx shall not be liable (whether in contract or tort, *
-- ** including negligence, or under any other theory of *
-- ** liability) for any loss or damage of any kind or nature *
-- ** related to, arising under or in connection with these *
-- ** materials, including for any direct, or any indirect, *
-- ** special, incidental, or consequential loss or damage *
-- ** (including loss of data, profits, goodwill, or any type of *
-- ** loss or damage suffered as a result of any action brought *
-- ** by a third party) even if such damage or loss was *
-- ** reasonably foreseeable or Xilinx had been advised of the *
-- ** possibility of the same. *
-- ** *
-- ** CRITICAL APPLICATIONS *
-- ** Xilinx products are not designed or intended to be fail- *
-- ** safe, or for use in any application requiring fail-safe *
-- ** performance, such as life-support or safety devices or *
-- ** systems, Class III medical devices, nuclear facilities, *
-- ** applications related to the deployment of airbags, or any *
-- ** other applications that could lead to death, personal *
-- ** injury, or severe property or environmental damage *
-- ** (individually and collectively, "Critical *
-- ** Applications"). Customer assumes the sole risk and *
-- ** liability of any use of Xilinx products in Critical *
-- ** Applications, subject only to applicable laws and *
-- ** regulations governing limitations on product liability. *
-- ** *
-- ** THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS *
-- ** PART OF THIS FILE AT ALL TIMES. *
-- *******************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_quad_spi.vhd
-- Version: v3.0
-- Description: This is the top-level design file for the AXI Quad SPI core.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-- axi_quad_spi.vhd
-- |--Legacy_mode
-- |-- axi_lite_ipif.vhd
-- |-- qspi_core_interface.vhd
-- |-- qspi_cntrl_reg.vhd
-- |-- qspi_status_slave_sel_reg.vhd
-- |-- qspi_occupancy_reg.vhd
-- |-- qspi_fifo_ifmodule.vhd
-- |-- qspi_mode_0_module.vhd
-- |-- qspi_receive_transmit_reg.vhd
-- |-- qspi_startup_block.vhd
-- |-- comp_defs.vhd -- (helper lib)
-- |-- qspi_look_up_logic.vhd
-- |-- qspi_mode_control_logic.vhd
-- |-- interrupt_control.vhd
-- |-- soft_reset.vhd
-- |--Enhanced_mode
-- |--axi_qspi_enhanced_mode.vhd
-- |-- qspi_addr_decoder.vhd
-- |-- qspi_core_interface.vhd
-- |-- qspi_cntrl_reg.vhd
-- |-- qspi_status_slave_sel_reg.vhd
-- |-- qspi_occupancy_reg.vhd
-- |-- qspi_fifo_ifmodule.vhd
-- |-- qspi_mode_0_module.vhd
-- |-- qspi_receive_transmit_reg.vhd
-- |-- qspi_startup_block.vhd
-- |-- comp_defs.vhd -- (helper lib)
-- |-- async_fifo_fg.vhd -- (helper lib)
-- |-- qspi_look_up_logic.vhd
-- |-- qspi_mode_control_logic.vhd
-- |-- interrupt_control.vhd
-- |-- soft_reset.vhd
-- |--XIP_mode
-- |-- axi_lite_ipif.vhd
-- |-- xip_cntrl_reg.vhd
-- |-- xip_cross_clk_sync.vhd
-- |-- reset_sync_module.vhd
-- |-- xip_status_reg.vhd
-- |-- axi_qspi_xip_if.vhd
-- |-- qspi_addr_decoder.vhd
-- |-- async_fifo_fg.vhd -- (helper lib)
-- |-- comp_defs.vhd -- (helper lib)
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
--
-- History:
-- ~~~~~~
-- SK 19/01/11 -- created v1.00.a version
-- ^^^^^^
-- 1. Created first version of the core.
-- ~~~~~~
-- ~~~~~~
-- SK 11/12/11 -- created v2.00.a version
-- ^^^^^^
-- 1. Upgraded AXI4 Lite based core performance.
-- 2. Added AXI4 full interface support and added functionality
-- 3. Added XIP mode functionality and corresponding logic files
-- 4. Separated AXI and SPI clock so that the SPI functionality can operate at
-- independent frequency.
-- ~~~~~~
-- ~~~~~~
-- SK 12/16/12 -- v3.0
-- 1. up reved to major version for 2013.1 Vivado release. No logic updates.
-- 2. Updated the version of AXI LITE IPIF to v2.0 in X.Y format
-- 3. updated the proc common version to proc_common_v4_0
-- 4. No Logic Updates
-- ^^^^^^
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.conv_std_logic_vector;
use ieee.std_logic_arith.all;
use ieee.std_logic_signed.all;
use ieee.std_logic_misc.all;
-- library unsigned is used for overloading of "=" which allows integer to
-- be compared to std_logic_vector
use ieee.std_logic_unsigned.all;
library proc_common_v4_0;
use proc_common_v4_0.proc_common_pkg.all;
use proc_common_v4_0.ipif_pkg.all;
use proc_common_v4_0.family.all;
use proc_common_v4_0.all;
library axi_lite_ipif_v2_0;
library axi_quad_spi_v3_1;
use axi_quad_spi_v3_1.all;
-------------------------------------------------------------------------------
entity axi_quad_spi is
generic(
-- Async_Clk parameter is added only for Vivado, it is not used in the design, this is
-- NON HDL parameter
Async_Clk : integer := 0;
-- General Parameters
C_FAMILY : string := "virtex7";
C_SUB_FAMILY : string := "virtex7";
C_INSTANCE : string := "axi_quad_spi_inst";
-------------------------
C_SPI_MEM_ADDR_BITS : integer := 24; -- allowed values are 24 or 32 only and used in XIP mode
C_TYPE_OF_AXI4_INTERFACE : integer range 0 to 1 := 0;--default AXI4 Lite Legacy mode
C_XIP_MODE : integer range 0 to 1 := 0;--default NON XIP Mode
--C_AXI4_CLK_PS : integer := 10000;--AXI clock period
--C_EXT_SPI_CLK_PS : integer := 10000;--ext clock period
C_FIFO_DEPTH : integer := 256;-- allowed 0,16,256.
C_SCK_RATIO : integer := 16;--default in legacy mode
C_NUM_SS_BITS : integer range 1 to 32:= 1;
C_NUM_TRANSFER_BITS : integer := 8; -- allowed 8, 16, 32
-------------------------
C_SPI_MODE : integer range 0 to 2 := 0; -- used for differentiating
-- Standard, Dual or Quad mode
-- in Ports as well as internal
-- functionality
C_USE_STARTUP : integer range 0 to 1 := 1; --
C_SPI_MEMORY : integer range 0 to 2 := 1; -- 0 - mixed mode,
-- 1 - winbond,
-- 2 - numonyx
-- used to differentiate
-- internal look up table
-- for commands.
-------------------------
-- AXI4 Lite Interface Parameters *as max address is 7c, only 7 address bits are used
C_S_AXI_ADDR_WIDTH : integer range 7 to 7 := 7;
C_S_AXI_DATA_WIDTH : integer range 32 to 32 := 32;
-------------------------
--*C_BASEADDR : std_logic_vector := x"FFFFFFFF";
--*C_HIGHADDR : std_logic_vector := x"00000000";
-------------------------
-- AXI4 Full Interface Parameters *as max 24 bits of address are supported on SPI interface, only 24 address bits are used
C_S_AXI4_ADDR_WIDTH : integer ;--range 24 to 24 := 24;
C_S_AXI4_DATA_WIDTH : integer range 32 to 32 := 32;
C_S_AXI4_ID_WIDTH : integer range 1 to 16 := 4 ;
-------------------------
-- To FIX CR# 685366, below lines are added again in RTL (Vivado Requirement), but these parameters are not used in the core RTL
C_S_AXI4_BASEADDR : std_logic_vector := x"FFFFFFFF";
C_S_AXI4_HIGHADDR : std_logic_vector := x"00000000"
-------------------------
);
port(
-- external async clock for SPI interface logic
ext_spi_clk : in std_logic;
-- axi4 lite interface clk and reset signals
s_axi_aclk : in std_logic;
s_axi_aresetn : in std_logic;
-- axi4 full interface clk and reset signals
s_axi4_aclk : in std_logic;
s_axi4_aresetn : in std_logic;
-------------------------------
-------------------------------
--*axi4 lite port interface* --
-------------------------------
-------------------------------
-- axi write address channel signals
---------------
s_axi_awaddr : in std_logic_vector (6 downto 0);--((C_S_AXI_ADDR_WIDTH-1) downto 0);
s_axi_awvalid : in std_logic;
s_axi_awready : out std_logic;
---------------
-- axi write data channel signals
---------------
s_axi_wdata : in std_logic_vector(31 downto 0); -- ((C_S_AXI_DATA_WIDTH-1) downto 0);
s_axi_wstrb : in std_logic_vector(3 downto 0); -- (((C_S_AXI_DATA_WIDTH/8)-1) downto 0);
s_axi_wvalid : in std_logic;
s_axi_wready : out std_logic;
---------------
-- axi write response channel signals
---------------
s_axi_bresp : out std_logic_vector(1 downto 0);
s_axi_bvalid : out std_logic;
s_axi_bready : in std_logic;
---------------
-- axi read address channel signals
---------------
s_axi_araddr : in std_logic_vector(6 downto 0); -- ((C_S_AXI_ADDR_WIDTH-1) downto 0);
s_axi_arvalid : in std_logic;
s_axi_arready : out std_logic;
---------------
-- axi read address channel signals
---------------
s_axi_rdata : out std_logic_vector(31 downto 0); -- ((C_S_AXI_DATA_WIDTH-1) downto 0);
s_axi_rresp : out std_logic_vector(1 downto 0);
s_axi_rvalid : out std_logic;
s_axi_rready : in std_logic;
-------------------------------
-------------------------------
--*axi4 full port interface* --
-------------------------------
------------------------------------
-- axi write address Channel Signals
------------------------------------
s_axi4_awid : in std_logic_vector((C_S_AXI4_ID_WIDTH-1) downto 0);
s_axi4_awaddr : in std_logic_vector((C_SPI_MEM_ADDR_BITS-1) downto 0); --((C_S_AXI4_ADDR_WIDTH-1) downto 0);
s_axi4_awlen : in std_logic_vector(7 downto 0);
s_axi4_awsize : in std_logic_vector(2 downto 0);
s_axi4_awburst : in std_logic_vector(1 downto 0);
s_axi4_awlock : in std_logic; -- not supported in design
s_axi4_awcache : in std_logic_vector(3 downto 0);-- not supported in design
s_axi4_awprot : in std_logic_vector(2 downto 0);-- not supported in design
s_axi4_awvalid : in std_logic;
s_axi4_awready : out std_logic;
---------------------------------------
-- axi4 full write Data Channel Signals
---------------------------------------
s_axi4_wdata : in std_logic_vector(31 downto 0); -- ((C_S_AXI4_DATA_WIDTH-1)downto 0);
s_axi4_wstrb : in std_logic_vector(3 downto 0); -- (((C_S_AXI4_DATA_WIDTH/8)-1) downto 0);
s_axi4_wlast : in std_logic;
s_axi4_wvalid : in std_logic;
s_axi4_wready : out std_logic;
-------------------------------------------
-- axi4 full write Response Channel Signals
-------------------------------------------
s_axi4_bid : out std_logic_vector((C_S_AXI4_ID_WIDTH-1) downto 0);
s_axi4_bresp : out std_logic_vector(1 downto 0);
s_axi4_bvalid : out std_logic;
s_axi4_bready : in std_logic;
-----------------------------------
-- axi read address Channel Signals
-----------------------------------
s_axi4_arid : in std_logic_vector((C_S_AXI4_ID_WIDTH-1) downto 0);
s_axi4_araddr : in std_logic_vector((C_SPI_MEM_ADDR_BITS-1) downto 0);--((C_S_AXI4_ADDR_WIDTH-1) downto 0);
s_axi4_arlen : in std_logic_vector(7 downto 0);
s_axi4_arsize : in std_logic_vector(2 downto 0);
s_axi4_arburst : in std_logic_vector(1 downto 0);
s_axi4_arlock : in std_logic; -- not supported in design
s_axi4_arcache : in std_logic_vector(3 downto 0);-- not supported in design
s_axi4_arprot : in std_logic_vector(2 downto 0);-- not supported in design
s_axi4_arvalid : in std_logic;
s_axi4_arready : out std_logic;
--------------------------------
-- axi read data Channel Signals
--------------------------------
s_axi4_rid : out std_logic_vector((C_S_AXI4_ID_WIDTH-1) downto 0);
s_axi4_rdata : out std_logic_vector(31 downto 0);--((C_S_AXI4_DATA_WIDTH-1) downto 0);
s_axi4_rresp : out std_logic_vector(1 downto 0);
s_axi4_rlast : out std_logic;
s_axi4_rvalid : out std_logic;
s_axi4_rready : in std_logic;
--------------------------------
-------------------------------
--*SPI port interface * --
-------------------------------
io0_i : in std_logic; -- MOSI signal in standard SPI
io0_o : out std_logic;
io0_t : out std_logic;
-------------------------------
io1_i : in std_logic; -- MISO signal in standard SPI
io1_o : out std_logic;
io1_t : out std_logic;
-----------------
-- quad mode pins
-----------------
io2_i : in std_logic;
io2_o : out std_logic;
io2_t : out std_logic;
---------------
io3_i : in std_logic;
io3_o : out std_logic;
io3_t : out std_logic;
---------------------------------
-- common pins
----------------
spisel : in std_logic;
-----
sck_i : in std_logic;
sck_o : out std_logic;
sck_t : out std_logic;
-----
ss_i : in std_logic_vector((C_NUM_SS_BITS-1) downto 0);
ss_o : out std_logic_vector((C_NUM_SS_BITS-1) downto 0);
ss_t : out std_logic;
----------------------
-- INTERRUPT INTERFACE
----------------------
ip2intc_irpt : out std_logic
---------------------------------
);
-------------------------------
-- Fan-out attributes for XST
attribute MAX_FANOUT : string;
attribute MAX_FANOUT of S_AXI_ACLK : signal is "10000";
attribute MAX_FANOUT of S_AXI4_ACLK : signal is "10000";
attribute MAX_FANOUT of EXT_SPI_CLK : signal is "10000";
attribute MAX_FANOUT of S_AXI_ARESETN : signal is "10000";
attribute MAX_FANOUT of S_AXI4_ARESETN : signal is "10000";
attribute INITIALVAL : string;
attribute INITIALVAL of SPISEL : signal is "VCC";
-------------------------------
end entity axi_quad_spi;
--------------------------------------------------------------------------------
architecture imp of axi_quad_spi is
----------------------------------------------------------------------------------
-- below attributes are added to reduce the synth warnings in Vivado tool
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
----------------------------------------------------------------------------------
---------------------------------------------------------------------------------
---- constant added for webtalk information
---------------------------------------------------------------------------------
-- constant C_CORE_GENERATION_INFO : string := C_INSTANCE & ",axi_quad_spi,{"
-- & "C_FAMILY = " & C_FAMILY
-- & ",C_SUB_FAMILY = " & C_SUB_FAMILY
-- & ",C_INSTANCE = " & C_INSTANCE
-- & ",C_S_AXI_ADDR_WIDTH = " & integer'image(C_S_AXI_ADDR_WIDTH)
-- & ",C_S_AXI_DATA_WIDTH = " & integer'image(C_S_AXI_DATA_WIDTH)
-- & ",C_S_AXI4_ADDR_WIDTH = " & integer'image(C_S_AXI4_ADDR_WIDTH)
-- & ",C_S_AXI4_DATA_WIDTH = " & integer'image(C_S_AXI4_DATA_WIDTH)
-- & ",C_S_AXI4_ID_WIDTH = " & integer'image(C_S_AXI4_ID_WIDTH)
-- & ",C_FIFO_DEPTH = " & integer'image(C_FIFO_DEPTH)
-- & ",C_SCK_RATIO = " & integer'image(C_SCK_RATIO)
-- & ",C_NUM_SS_BITS = " & integer'image(C_NUM_SS_BITS)
-- & ",C_NUM_TRANSFER_BITS = " & integer'image(C_NUM_TRANSFER_BITS)
-- & ",C_USE_STARTUP = " & integer'image(C_USE_STARTUP)
-- & ",C_SPI_MODE = " & integer'image(C_SPI_MODE)
-- & ",C_SPI_MEMORY = " & integer'image(C_SPI_MEMORY)
-- & ",C_TYPE_OF_AXI4_INTERFACE = " & integer'image(C_TYPE_OF_AXI4_INTERFACE)
-- & ",C_XIP_MODE = " & integer'image(C_XIP_MODE)
-- & "}";
--
-- attribute CORE_GENERATION_INFO : string;
-- attribute CORE_GENERATION_INFO of imp : architecture is C_CORE_GENERATION_INFO;
-------------------------------------------------------------
-------------------------------------------------------------
-- Function Declaration
-------------------------------------------------------------
-- get_fifo_presence - This function returns the 0 or 1 based upon the FIFO Depth.
--
function get_fifo_presence(C_FIFO_DEPTH: integer) return integer is
-----
begin
-----
if(C_FIFO_DEPTH = 0)then
return 0;
else
return 1;
end if;
end function get_fifo_presence;
function get_fifo_depth(C_FIFO_EXIST: integer; C_FIFO_DEPTH : integer) return integer is
-----
begin
-----
if(C_FIFO_EXIST = 1)then
return C_FIFO_DEPTH;
else
return 64; -- to ensure that log2 functions does not become invalid
end if;
end function get_fifo_depth;
------------------------------
function get_fifo_occupancy_count(C_FIFO_DEPTH: integer) return integer is
-----
variable j : integer := 0;
variable k : integer := 0;
-----
begin
-----
if (C_FIFO_DEPTH = 0) then
return 4;
else
for i in 0 to 11 loop
if(2**i >= C_FIFO_DEPTH) then
if(k = 0) then
j := i;
end if;
k := 1;
end if;
end loop;
return j;
end if;
-------
end function get_fifo_occupancy_count;
------------------------------
-- Constant declarations
------------------------------
--------------------- ******************* ------------------------------------
-- Core Parameters
--------------------- ******************* ------------------------------------
--
constant C_FIFO_EXIST : integer := get_fifo_presence(C_FIFO_DEPTH);
constant C_FIFO_DEPTH_UPDATED : integer := get_fifo_depth(C_FIFO_EXIST, C_FIFO_DEPTH);
-- width of control register
constant C_SPICR_REG_WIDTH : integer := 10;-- refer DS
-- width of status register
constant C_SPISR_REG_WIDTH : integer := 11;-- refer DS
-- count the counter width for calculating FIFO occupancy
constant C_OCCUPANCY_NUM_BITS : integer := get_fifo_occupancy_count(C_FIFO_DEPTH_UPDATED);
-- width of spi shift register
constant C_SPI_NUM_BITS_REG : integer := 8;-- this is fixed
constant C_NUM_SPI_REGS : integer := 8;-- this is fixed
constant C_IPISR_IPIER_BITS : integer := 14;-- total 14 interrupts - 0 to 13
--------------------- ******************* ------------------------------------
-- AXI lite parameters
--------------------- ******************* ------------------------------------
constant C_S_AXI_SPI_MIN_SIZE : std_logic_vector(31 downto 0):= X"0000007c";
constant C_USE_WSTRB : integer := 1;
constant C_DPHASE_TIMEOUT : integer := 20;
-- interupt mode
constant IP_INTR_MODE_ARRAY : INTEGER_ARRAY_TYPE(0 to (C_IPISR_IPIER_BITS-1)):=
(
others => INTR_REG_EVENT
-- when C_SPI_MODE = 0
-- Seven interrupts if C_FIFO_DEPTH_UPDATED = 0
-- OR
-- Eight interrupts if C_FIFO_DEPTH_UPDATED = 0 and slave mode
----------------------- OR ---------------------------
-- Nine interrupts if C_FIFO_DEPTH_UPDATED = 16 and slave mode
-- OR
-- Seven interrupts if C_FIFO_DEPTH_UPDATED = 16 and master mode
-- when C_SPI_MODE = 1 or 2
-- Thirteen interrupts if C_FIFO_DEPTH_UPDATED = 16 and master mode
);
constant ZEROES : std_logic_vector(31 downto 0):= X"00000000";
-- this constant is defined as the start of SPI register addresses.
constant C_IP_REG_ADDR_OFFSET : std_logic_vector := X"00000060";
-- Address range array
constant C_ARD_ADDR_RANGE_ARRAY: SLV64_ARRAY_TYPE :=
(
-- interrupt address base & high range
--ZEROES & C_BASEADDR,
--ZEROES & (C_BASEADDR or X"0000003F"),--interrupt address higher range
ZEROES & X"00000000",
ZEROES & X"0000003F",--interrupt address higher range
-- soft reset register base & high addr
--ZEROES & (C_BASEADDR or X"00000040"),
--ZEROES & (C_BASEADDR or X"00000043"),--soft reset register high addr
ZEROES & X"00000040",
-- ZEROES & X"00000043",--soft reset register high addr
ZEROES & X"0000005C",--soft reset register NEW high addr for addressing holes
-- SPI registers Base & High Address
-- Range is 60 to 78 -- for internal registers
--ZEROES & (C_BASEADDR or C_IP_REG_ADDR_OFFSET),
--ZEROES & (C_BASEADDR or C_IP_REG_ADDR_OFFSET or X"00000018")
ZEROES & C_IP_REG_ADDR_OFFSET,
ZEROES & (C_IP_REG_ADDR_OFFSET or X"00000018")
);
-- AXI4 Address range array
constant C_ARD_ADDR_RANGE_ARRAY_AXI4_FULL: SLV64_ARRAY_TYPE :=
(
-- interrupt address base & high range
--*ZEROES & C_S_AXI4_BASEADDR,
--*ZEROES & (C_S_AXI4_BASEADDR or X"0000003F"),--interrupt address higher range
ZEROES & X"00000000",
ZEROES & X"0000003F",--soft reset register high addr
-- soft reset register base & high addr
--*ZEROES & (C_S_AXI4_BASEADDR or X"00000040"),
--*ZEROES & (C_S_AXI4_BASEADDR or X"00000043"),--soft reset register high addr
ZEROES & X"00000040",
-- ZEROES & X"00000043",--soft reset register high addr
ZEROES & X"0000005C",--soft reset register NEW high addr for addressing holes
-- SPI registers Base & High Address
-- Range is 60 to 78 -- for internal registers
ZEROES & (C_IP_REG_ADDR_OFFSET),
ZEROES & (C_IP_REG_ADDR_OFFSET or X"00000018")
);
-- No. of CE's required per address range
constant C_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => 16 , -- 16 CEs required for interrupt
--1 => 1, -- 1 CE required for soft reset
1 => 8, -- 8 CE required for Addressing Holes in soft reset
2 => C_NUM_SPI_REGS
);
-- no. of Chip Enable Signals
constant C_NUM_CE_SIGNALS : integer := calc_num_ce(C_ARD_NUM_CE_ARRAY);
-- no. of Chip Select Signals
constant C_NUM_CS_SIGNALS : integer := (C_ARD_ADDR_RANGE_ARRAY'LENGTH/2);
-----------------------------
----------------------- ******************* ------------------------------------
---- XIP Mode parameters
----------------------- ******************* ------------------------------------
-- No. of XIP SPI registers
constant C_NUM_XIP_SPI_REGS : integer := 2;-- this is fixed
-- width of XIP control register
constant C_XIP_SPICR_REG_WIDTH: integer := 2;-- refer DS
-- width of XIP status register
constant C_XIP_SPISR_REG_WIDTH: integer := 5;-- refer DS
-- Address range array
constant C_XIP_LITE_ARD_ADDR_RANGE_ARRAY: SLV64_ARRAY_TYPE :=
(
-- XIP SPI registers Base & High Address
-- Range is 60 to 64 -- for internal registers
--*ZEROES & (C_BASEADDR or C_IP_REG_ADDR_OFFSET),
--*ZEROES & (C_BASEADDR or C_IP_REG_ADDR_OFFSET or X"00000004")
ZEROES & (C_IP_REG_ADDR_OFFSET),
ZEROES & (C_IP_REG_ADDR_OFFSET or X"00000004")
);
-- No. of CE's required per address range
constant C_XIP_LITE_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => C_NUM_XIP_SPI_REGS -- 2 CEs required for XIP lite interface
);
-- no. of Chip Enable Signals
constant C_NUM_XIP_CE_SIGNALS : integer :=
calc_num_ce(C_XIP_LITE_ARD_NUM_CE_ARRAY);
function assign_addr_bits (addr_bits_info : integer) return string is
variable addr_width_24 : integer:= 24;
variable addr_width_32 : integer:= 32;
begin
if addr_bits_info = 24 then -- old logic for 24 bit addressing
return X"00FFFFFF";--addr_width_24;
else
return X"FFFFFFFF";--addr_width_32;
end if;
end function assign_addr_bits;
constant C_XIP_ADDR_OFFSET : std_logic_vector := X"FFFFFFFF";--assign_addr_bits(C_SPI_MEM_ADDR_BITS); -- X"00FFFFFF";
-- XIP Full Interface Address range array
constant C_XIP_FULL_ARD_ADDR_RANGE_ARRAY: SLV64_ARRAY_TYPE :=
(
-- XIP SPI registers Base & High Address
-- Range is 60 to 64 -- for internal registers
--*ZEROES & (C_S_AXI4_BASEADDR),
--*ZEROES & (C_S_AXI4_BASEADDR or C_24_BIT_ADDR_OFFSET)
ZEROES & X"00000000",
ZEROES & C_XIP_ADDR_OFFSET
);
-- No. of CE's required per address range
constant C_XIP_FULL_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => C_NUM_XIP_SPI_REGS -- 0 CEs required for XIP Full interface
);
---------------------------------------------------------------------------------
constant C_XIP_FIFO_DEPTH : integer := 264;
-------------------------------------------------------------------------------
-- signal declaration
signal bus2ip_clk : std_logic;
signal bus2ip_be_int : std_logic_vector
(((C_S_AXI_DATA_WIDTH/8)-1)downto 0);
signal bus2ip_rdce_int : std_logic_vector
((C_NUM_CE_SIGNALS-1)downto 0);
signal bus2ip_wrce_int : std_logic_vector
((C_NUM_CE_SIGNALS-1)downto 0);
signal bus2ip_data_int : std_logic_vector
((C_S_AXI_DATA_WIDTH-1)downto 0);
signal ip2bus_data_int : std_logic_vector
((C_S_AXI_DATA_WIDTH-1)downto 0 )
:= (others => '0');
signal ip2bus_wrack_int : std_logic := '0';
signal ip2bus_rdack_int : std_logic := '0';
signal ip2bus_error_int : std_logic := '0';
signal bus2ip_reset_int : std_logic;
signal bus2ip_reset_ipif_inverted: std_logic;
-- XIP signals
signal bus2ip_xip_rdce_int: std_logic_vector(0 to C_NUM_XIP_CE_SIGNALS-1);
signal bus2ip_xip_wrce_int: std_logic_vector(0 to C_NUM_XIP_CE_SIGNALS-1);
signal burst_tr_int : std_logic;
signal rready_int : std_logic;
signal bus2ip_reset_ipif4_inverted : std_logic;
-----
begin
-----
-------------------------------------------------------------------------------
---------------
-- AXI_QUAD_SPI_LEGACY_MODE: This logic is legacy AXI4 Lite interface based design
---------------
QSPI_LEGACY_MD_GEN : if C_TYPE_OF_AXI4_INTERFACE = 0 generate
---------------
begin
-----
AXI_LITE_IPIF_I : entity axi_lite_ipif_v2_0.axi_lite_ipif
generic map
(
----------------------------------------------------
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH ,
C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH ,
----------------------------------------------------
C_S_AXI_MIN_SIZE => C_S_AXI_SPI_MIN_SIZE ,
C_USE_WSTRB => C_USE_WSTRB ,
C_DPHASE_TIMEOUT => C_DPHASE_TIMEOUT ,
----------------------------------------------------
C_ARD_ADDR_RANGE_ARRAY => C_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => C_ARD_NUM_CE_ARRAY ,
C_FAMILY => C_FAMILY
----------------------------------------------------
)
port map
(
---------------------------------------------------------
S_AXI_ACLK => s_axi_aclk, -- in
S_AXI_ARESETN => s_axi_aresetn, -- in
---------------------------------------------------------
S_AXI_AWADDR => s_axi_awaddr, -- in
S_AXI_AWVALID => s_axi_awvalid, -- in
S_AXI_AWREADY => s_axi_awready, -- out
S_AXI_WDATA => s_axi_wdata, -- in
S_AXI_WSTRB => s_axi_wstrb, -- in
S_AXI_WVALID => s_axi_wvalid, -- in
S_AXI_WREADY => s_axi_wready, -- out
S_AXI_BRESP => s_axi_bresp, -- out
S_AXI_BVALID => s_axi_bvalid, -- out
S_AXI_BREADY => s_axi_bready, -- in
S_AXI_ARADDR => s_axi_araddr, -- in
S_AXI_ARVALID => s_axi_arvalid, -- in
S_AXI_ARREADY => s_axi_arready, -- out
S_AXI_RDATA => s_axi_rdata, -- out
S_AXI_RRESP => s_axi_rresp, -- out
S_AXI_RVALID => s_axi_rvalid, -- out
S_AXI_RREADY => s_axi_rready, -- in
----------------------------------------------------------
-- IP Interconnect (IPIC) port signals
Bus2IP_Clk => bus2ip_clk, -- out
Bus2IP_Resetn => bus2ip_reset_int, -- out
----------------------------------------------------------
Bus2IP_Addr => open, -- out -- not used signal
Bus2IP_RNW => open, -- out
Bus2IP_BE => bus2ip_be_int, -- out
Bus2IP_CS => open, -- out -- not used signal
Bus2IP_RdCE => bus2ip_rdce_int, -- out -- little endian
Bus2IP_WrCE => bus2ip_wrce_int, -- out -- little endian
Bus2IP_Data => bus2ip_data_int, -- out -- little endian
----------------------------------------------------------
IP2Bus_Data => ip2bus_data_int, -- in -- little endian
IP2Bus_WrAck => ip2bus_wrack_int, -- in
IP2Bus_RdAck => ip2bus_rdack_int, -- in
IP2Bus_Error => ip2bus_error_int -- in
----------------------------------------------------------
);
----------------------
--REG_RST_FRM_IPIF: convert active low to active hig reset to rest of
-- the core.
----------------------
REG_RST_FRM_IPIF: process (S_AXI_ACLK) is
begin
if(S_AXI_ACLK'event and S_AXI_ACLK = '1') then
bus2ip_reset_ipif_inverted <= not(bus2ip_reset_int);
end if;
end process REG_RST_FRM_IPIF;
-- ----------------------------------------------------------------------
-- -- Instansiating the SPI core
-- ----------------------------------------------------------------------
QSPI_CORE_INTERFACE_I : entity axi_quad_spi_v3_1.qspi_core_interface
generic map
(
------------------------------------------------
-- AXI parameters
C_FAMILY => C_FAMILY ,
C_SUB_FAMILY => C_SUB_FAMILY ,
C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH,
------------------------------------------------
-- local constants
C_NUM_CE_SIGNALS => C_NUM_CE_SIGNALS ,
------------------------------------------------
-- SPI parameters
--C_AXI4_CLK_PS => C_AXI4_CLK_PS ,
--C_EXT_SPI_CLK_PS => C_EXT_SPI_CLK_PS ,
C_FIFO_DEPTH => C_FIFO_DEPTH_UPDATED ,
C_SCK_RATIO => C_SCK_RATIO ,
C_NUM_SS_BITS => C_NUM_SS_BITS ,
C_NUM_TRANSFER_BITS => C_NUM_TRANSFER_BITS,
C_SPI_MODE => C_SPI_MODE ,
C_USE_STARTUP => C_USE_STARTUP ,
C_SPI_MEMORY => C_SPI_MEMORY ,
C_TYPE_OF_AXI4_INTERFACE => C_TYPE_OF_AXI4_INTERFACE,
------------------------------------------------
-- local constants
C_FIFO_EXIST => C_FIFO_EXIST ,
C_SPI_NUM_BITS_REG => C_SPI_NUM_BITS_REG,
C_OCCUPANCY_NUM_BITS => C_OCCUPANCY_NUM_BITS,
------------------------------------------------
-- local constants
C_IP_INTR_MODE_ARRAY => IP_INTR_MODE_ARRAY,
------------------------------------------------
-- local constants
C_SPICR_REG_WIDTH => C_SPICR_REG_WIDTH ,
C_SPISR_REG_WIDTH => C_SPISR_REG_WIDTH
)
port map
(
EXT_SPI_CLK => ext_spi_clk, -- in
---------------------------------------------------
-- IP Interconnect (IPIC) port signals
Bus2IP_Clk => bus2ip_clk, -- in
Bus2IP_Reset => bus2ip_reset_ipif_inverted, -- in
---------------------------------------------------
Bus2IP_BE => bus2ip_be_int, -- in vector
-- Bus2IP_CS => bus2ip_cs_int,
Bus2IP_RdCE => bus2ip_rdce_int, -- in vector
Bus2IP_WrCE => bus2ip_wrce_int, -- in vector
Bus2IP_Data => bus2ip_data_int, -- in vector
---------------------------------------------------
IP2Bus_Data => ip2bus_data_int, -- out vector
IP2Bus_WrAck => ip2bus_wrack_int, -- out
IP2Bus_RdAck => ip2bus_rdack_int, -- out
IP2Bus_Error => ip2bus_error_int, -- out
---------------------------------------------------
burst_tr => burst_tr_int,
rready => '0',
WVALID => '0',
---------------------------------------------------
--SPI Ports
IO0_I => io0_i,-- mosi
IO0_O => io0_o,
IO0_T => io0_t,
-----
IO1_I => io1_i,-- miso
IO1_O => io1_o,
IO1_T => io1_t,
-----
IO2_I => io2_i,
IO2_O => io2_o,
IO2_T => io2_t,
-----
IO3_I => io3_i,
IO3_O => io3_o,
IO3_T => io3_t,
-----
SCK_I => sck_i,
SCK_O => sck_o,
SCK_T => sck_t,
-----
SPISEL => spisel,
-----
SS_I => ss_i,
SS_O => ss_o,
SS_T => ss_t,
-----
IP2INTC_Irpt => ip2intc_irpt
-----
);
burst_tr_int <= '0';
end generate QSPI_LEGACY_MD_GEN;
------------------------------------------------------------------------------
QSPI_ENHANCED_MD_GEN: if C_TYPE_OF_AXI4_INTERFACE = 1 and C_XIP_MODE = 0 generate
---------------
begin
-----
-- AXI_QUAD_SPI_I: core instance
QSPI_ENHANCED_MD_IPIF_I : entity axi_quad_spi_v3_1.axi_qspi_enhanced_mode
generic map(
-- General Parameters
C_FAMILY => C_FAMILY , -- : string := "virtex7";
C_SUB_FAMILY => C_SUB_FAMILY , -- : string := "virtex7";
-------------------------
--C_TYPE_OF_AXI4_INTERFACE => C_TYPE_OF_AXI4_INTERFACE, -- : integer range 0 to 1 := 0;--default AXI4 Lite Legacy mode
--C_XIP_MODE => C_XIP_MODE , -- : integer range 0 to 1 := 0;--default NON XIP Mode
--C_AXI4_CLK_PS => C_AXI4_CLK_PS , -- : integer := 10000;--AXI clock period
--C_EXT_SPI_CLK_PS => C_EXT_SPI_CLK_PS , -- : integer := 10000;--ext clock period
C_FIFO_DEPTH => C_FIFO_DEPTH_UPDATED , -- : integer := 16;-- allowed 0,16,256.
C_SCK_RATIO => C_SCK_RATIO , -- : integer := 16;--default in legacy mode
C_NUM_SS_BITS => C_NUM_SS_BITS , -- : integer range 1 to 32:= 1;
C_NUM_TRANSFER_BITS => C_NUM_TRANSFER_BITS , -- : integer := 8; -- allowed 8, 16, 32
-------------------------
C_SPI_MODE => C_SPI_MODE , -- : integer range 0 to 2 := 0; -- used for differentiating
C_USE_STARTUP => C_USE_STARTUP , -- : integer range 0 to 1 := 1; --
C_SPI_MEMORY => C_SPI_MEMORY , -- : integer range 0 to 2 := 1; -- 0 - mixed mode,
-------------------------
-- AXI4 Full Interface Parameters
C_S_AXI4_ADDR_WIDTH => C_S_AXI4_ADDR_WIDTH , -- : integer range 32 to 32 := 32;
C_S_AXI4_DATA_WIDTH => C_S_AXI4_DATA_WIDTH , -- : integer range 32 to 32 := 32;
C_S_AXI4_ID_WIDTH => C_S_AXI4_ID_WIDTH , -- : integer range 1 to 16 := 4;
-------------------------
--*C_AXI4_BASEADDR => C_S_AXI4_BASEADDR , -- : std_logic_vector := x"FFFFFFFF";
--*C_AXI4_HIGHADDR => C_S_AXI4_HIGHADDR , -- : std_logic_vector := x"00000000"
-------------------------
C_S_AXI_SPI_MIN_SIZE => C_S_AXI_SPI_MIN_SIZE ,
-------------------------
C_ARD_ADDR_RANGE_ARRAY => C_ARD_ADDR_RANGE_ARRAY_AXI4_FULL ,
C_ARD_NUM_CE_ARRAY => C_ARD_NUM_CE_ARRAY ,
C_SPI_MEM_ADDR_BITS => C_SPI_MEM_ADDR_BITS -- newly added
)
port map(
-- external async clock for SPI interface logic
EXT_SPI_CLK => ext_spi_clk , -- : in std_logic;
-----------------------------------
S_AXI4_ACLK => s_axi4_aclk , -- : in std_logic;
S_AXI4_ARESETN => s_axi4_aresetn , -- : in std_logic;
-------------------------------
-------------------------------
--*AXI4 Full port interface* --
-------------------------------
------------------------------------
-- AXI Write Address channel signals
------------------------------------
S_AXI4_AWID => s_axi4_awid , -- : in std_logic_vector((C_S_AXI4_ID_WIDTH-1) downto 0);
S_AXI4_AWADDR => s_axi4_awaddr , -- : in std_logic_vector((C_S_AXI4_ADDR_WIDTH-1) downto 0);
S_AXI4_AWLEN => s_axi4_awlen , -- : in std_logic_vector(7 downto 0);
S_AXI4_AWSIZE => s_axi4_awsize , -- : in std_logic_vector(2 downto 0);
S_AXI4_AWBURST => s_axi4_awburst, -- : in std_logic_vector(1 downto 0);
S_AXI4_AWLOCK => s_axi4_awlock , -- : in std_logic; -- not supported in design
S_AXI4_AWCACHE => s_axi4_awcache, -- : in std_logic_vector(3 downto 0);-- not supported in design
S_AXI4_AWPROT => s_axi4_awprot , -- : in std_logic_vector(2 downto 0);-- not supported in design
S_AXI4_AWVALID => s_axi4_awvalid, -- : in std_logic;
S_AXI4_AWREADY => s_axi4_awready, -- : out std_logic;
---------------------------------------
-- AXI4 Full Write data channel signals
---------------------------------------
S_AXI4_WDATA => s_axi4_wdata , -- : in std_logic_vector((C_S_AXI4_DATA_WIDTH-1)downto 0);
S_AXI4_WSTRB => s_axi4_wstrb , -- : in std_logic_vector(((C_S_AXI4_DATA_WIDTH/8)-1) downto 0);
S_AXI4_WLAST => s_axi4_wlast , -- : in std_logic;
S_AXI4_WVALID => s_axi4_wvalid, -- : in std_logic;
S_AXI4_WREADY => s_axi4_wready, -- : out std_logic;
-------------------------------------------
-- AXI4 Full Write response channel Signals
-------------------------------------------
S_AXI4_BID => s_axi4_bid , -- : out std_logic_vector((C_S_AXI4_ID_WIDTH-1) downto 0);
S_AXI4_BRESP => s_axi4_bresp , -- : out std_logic_vector(1 downto 0);
S_AXI4_BVALID => s_axi4_bvalid, -- : out std_logic;
S_AXI4_BREADY => s_axi4_bready, -- : in std_logic;
-----------------------------------
-- AXI Read Address channel signals
-----------------------------------
S_AXI4_ARID => s_axi4_arid , -- : in std_logic_vector((C_S_AXI4_ID_WIDTH-1) downto 0);
S_AXI4_ARADDR => s_axi4_araddr , -- : in std_logic_vector((C_S_AXI4_ADDR_WIDTH-1) downto 0);
S_AXI4_ARLEN => s_axi4_arlen , -- : in std_logic_vector(7 downto 0);
S_AXI4_ARSIZE => s_axi4_arsize , -- : in std_logic_vector(2 downto 0);
S_AXI4_ARBURST => s_axi4_arburst, -- : in std_logic_vector(1 downto 0);
S_AXI4_ARLOCK => s_axi4_arlock , -- : in std_logic; -- not supported in design
S_AXI4_ARCACHE => s_axi4_arcache, -- : in std_logic_vector(3 downto 0);-- not supported in design
S_AXI4_ARPROT => s_axi4_arprot , -- : in std_logic_vector(2 downto 0);-- not supported in design
S_AXI4_ARVALID => s_axi4_arvalid, -- : in std_logic;
S_AXI4_ARREADY => s_axi4_arready, -- : out std_logic;
--------------------------------
-- AXI Read Data Channel signals
--------------------------------
S_AXI4_RID => s_axi4_rid , -- : out std_logic_vector((C_S_AXI4_ID_WIDTH-1) downto 0);
S_AXI4_RDATA => s_axi4_rdata , -- : out std_logic_vector((C_S_AXI4_DATA_WIDTH-1) downto 0);
S_AXI4_RRESP => s_axi4_rresp , -- : out std_logic_vector(1 downto 0);
S_AXI4_RLAST => s_axi4_rlast , -- : out std_logic;
S_AXI4_RVALID => s_axi4_rvalid, -- : out std_logic;
S_AXI4_RREADY => s_axi4_rready, -- : in std_logic;
----------------------------------------------------------
-- IP Interconnect (IPIC) port signals
Bus2IP_Clk => bus2ip_clk, -- out
Bus2IP_Reset => bus2ip_reset_ipif_inverted , -- out
----------------------------------------------------------
-- Bus2IP_Addr => open, -- out -- not used signal
Bus2IP_RNW => open, -- out
Bus2IP_BE => bus2ip_be_int, -- out
Bus2IP_CS => open, -- out -- not used signal
Bus2IP_RdCE => bus2ip_rdce_int, -- out -- little endian
Bus2IP_WrCE => bus2ip_wrce_int, -- out -- little endian
Bus2IP_Data => bus2ip_data_int, -- out -- little endian
----------------------------------------------------------
IP2Bus_Data => ip2bus_data_int, -- in -- little endian
IP2Bus_WrAck => ip2bus_wrack_int, -- in
IP2Bus_RdAck => ip2bus_rdack_int, -- in
IP2Bus_Error => ip2bus_error_int, -- in
----------------------------------------------------------
burst_tr => burst_tr_int, -- in
rready => rready_int
);
-- ----------------------------------------------------------------------
-- -- Instansiating the SPI core
-- ----------------------------------------------------------------------
QSPI_CORE_INTERFACE_I : entity axi_quad_spi_v3_1.qspi_core_interface
generic map
(
------------------------------------------------
-- AXI parameters
C_FAMILY => C_FAMILY ,
C_SUB_FAMILY => C_SUB_FAMILY ,
C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH,
------------------------------------------------
-- local constants
C_NUM_CE_SIGNALS => C_NUM_CE_SIGNALS ,
------------------------------------------------
-- SPI parameters
--C_AXI4_CLK_PS => C_AXI4_CLK_PS ,
--C_EXT_SPI_CLK_PS => C_EXT_SPI_CLK_PS ,
C_FIFO_DEPTH => C_FIFO_DEPTH_UPDATED ,
C_SCK_RATIO => C_SCK_RATIO ,
C_NUM_SS_BITS => C_NUM_SS_BITS ,
C_NUM_TRANSFER_BITS => C_NUM_TRANSFER_BITS,
C_SPI_MODE => C_SPI_MODE ,
C_USE_STARTUP => C_USE_STARTUP ,
C_SPI_MEMORY => C_SPI_MEMORY ,
C_TYPE_OF_AXI4_INTERFACE => C_TYPE_OF_AXI4_INTERFACE,
------------------------------------------------
-- local constants
C_FIFO_EXIST => C_FIFO_EXIST ,
C_SPI_NUM_BITS_REG => C_SPI_NUM_BITS_REG,
C_OCCUPANCY_NUM_BITS => C_OCCUPANCY_NUM_BITS,
------------------------------------------------
-- local constants
C_IP_INTR_MODE_ARRAY => IP_INTR_MODE_ARRAY,
------------------------------------------------
-- local constants
C_SPICR_REG_WIDTH => C_SPICR_REG_WIDTH ,
C_SPISR_REG_WIDTH => C_SPISR_REG_WIDTH
)
port map
(
EXT_SPI_CLK => EXT_SPI_CLK, -- in
---------------------------------------------------
-- IP Interconnect (IPIC) port signals
Bus2IP_Clk => bus2ip_clk, -- in
Bus2IP_Reset => bus2ip_reset_ipif_inverted, -- in
---------------------------------------------------
Bus2IP_BE => bus2ip_be_int, -- in vector
-- Bus2IP_CS => bus2ip_cs_int,
Bus2IP_RdCE => bus2ip_rdce_int, -- in vector
Bus2IP_WrCE => bus2ip_wrce_int, -- in vector
Bus2IP_Data => bus2ip_data_int, -- in vector
---------------------------------------------------
IP2Bus_Data => ip2bus_data_int, -- out vector
IP2Bus_WrAck => ip2bus_wrack_int, -- out
IP2Bus_RdAck => ip2bus_rdack_int, -- out
IP2Bus_Error => ip2bus_error_int, -- out
---------------------------------------------------
burst_tr => burst_tr_int,
rready => rready_int,
WVALID => S_AXI4_WVALID,
--SPI Ports
IO0_I => io0_i,-- mosi
IO0_O => io0_o,
IO0_T => io0_t,
-----
IO1_I => io1_i,-- miso
IO1_O => io1_o,
IO1_T => io1_t,
-----
IO2_I => io2_i,
IO2_O => io2_o,
IO2_T => io2_t,
-----
IO3_I => io3_i,
IO3_O => io3_o,
IO3_T => io3_t,
-----
SCK_I => sck_i,
SCK_O => sck_o,
SCK_T => sck_t,
-----
SPISEL => spisel,
-----
SS_I => ss_i,
SS_O => ss_o,
SS_T => ss_t,
-----
IP2INTC_Irpt => ip2intc_irpt
-----
);
end generate QSPI_ENHANCED_MD_GEN;
--------------------------------------------------------------------------------
-----------------
-- XIP_MODE: This logic is used in XIP mode where AXI4 Lite & AXI4 Full interface
-- used in the design
---------------
XIP_MODE_GEN : if C_TYPE_OF_AXI4_INTERFACE = 1 and C_XIP_MODE = 1 generate
---------------
constant XIPCR : natural := 0; -- at address C_BASEADDR + 60 h
constant XIPSR : natural := 1;
--
signal bus2ip_reset_int : std_logic;
signal bus2ip_clk_int : std_logic;
signal bus2ip_data_int : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal ip2bus_data_int : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal ip2bus_wrack_int : std_logic;
signal ip2bus_rdack_int : std_logic;
signal ip2bus_error_int : std_logic;
signal bus2ip_reset_ipif_inverted: std_logic;
signal IP2Bus_XIPCR_WrAck : std_logic;
signal IP2Bus_XIPCR_RdAck : std_logic;
signal XIPCR_1_CPOL_int : std_logic;
signal XIPCR_0_CPHA_int : std_logic;
signal IP2Bus_XIPCR_Data_int : std_logic_vector((C_XIP_SPICR_REG_WIDTH-1) downto 0);
signal IP2Bus_XIPSR_Data_int : std_logic_vector((C_XIP_SPISR_REG_WIDTH-1) downto 0);
signal TO_XIPSR_AXI_TR_ERR_int : std_logic;
signal TO_XIPSR_mst_modf_err_int : std_logic;
signal TO_XIPSR_axi_rx_full_int : std_logic;
signal TO_XIPSR_axi_rx_empty_int : std_logic;
signal xipsr_cpha_cpol_err_int :std_logic;
signal xipsr_cmd_err_int :std_logic;
signal ip2bus_xipsr_wrack :std_logic;
signal ip2bus_xipsr_rdack :std_logic;
signal xipsr_axi_tr_err_int :std_logic;
signal xipsr_axi_tr_done_int :std_logic;
signal ip2bus_xipsr_rdack_int :std_logic;
signal ip2bus_xipsr_wrack_int :std_logic;
signal MISO_I_int :std_logic;
signal SCK_O_int :std_logic;
signal TO_XIPSR_trans_error_int :std_logic;
signal TO_XIPSR_CPHA_CPOL_ERR_int :std_logic;
signal ip2bus_wrack_core_reg_d1 :std_logic;
signal ip2bus_wrack_core_reg :std_logic;
signal ip2bus_rdack_core_reg_d1 :std_logic;
signal ip2bus_rdack_core_reg_d2 :std_logic;
signal ip2Bus_RdAck_core_reg_d3 :std_logic;
signal Rst_to_spi_int :std_logic;
begin
-----
---- AXI4 Lite interface instance and interface with the port list
AXI_LITE_IPIF_I : entity axi_lite_ipif_v2_0.axi_lite_ipif
generic map
(
----------------------------------------------------
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH ,
C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH ,
----------------------------------------------------
C_S_AXI_MIN_SIZE => C_S_AXI_SPI_MIN_SIZE ,
C_USE_WSTRB => C_USE_WSTRB ,
C_DPHASE_TIMEOUT => C_DPHASE_TIMEOUT ,
----------------------------------------------------
C_ARD_ADDR_RANGE_ARRAY => C_XIP_LITE_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => C_XIP_LITE_ARD_NUM_CE_ARRAY ,
C_FAMILY => C_FAMILY
----------------------------------------------------
)
port map
( -- AXI4 Lite interface
---------------------------------------------------------
S_AXI_ACLK => s_axi_aclk, -- in
S_AXI_ARESETN => s_axi_aresetn, -- in
---------------------------------------------------------
S_AXI_AWADDR => s_axi_awaddr, -- in
S_AXI_AWVALID => s_axi_awvalid, -- in
S_AXI_AWREADY => s_axi_awready, -- out
S_AXI_WDATA => s_axi_wdata, -- in
S_AXI_WSTRB => s_axi_wstrb, -- in
S_AXI_WVALID => s_axi_wvalid, -- in
S_AXI_WREADY => s_axi_wready, -- out
S_AXI_BRESP => s_axi_bresp, -- out
S_AXI_BVALID => s_axi_bvalid, -- out
S_AXI_BREADY => s_axi_bready, -- in
S_AXI_ARADDR => s_axi_araddr, -- in
S_AXI_ARVALID => s_axi_arvalid, -- in
S_AXI_ARREADY => s_axi_arready, -- out
S_AXI_RDATA => s_axi_rdata, -- out
S_AXI_RRESP => s_axi_rresp, -- out
S_AXI_RVALID => s_axi_rvalid, -- out
S_AXI_RREADY => s_axi_rready, -- in
----------------------------------------------------------
-- IP Interconnect (IPIC) port signals
Bus2IP_Clk => bus2ip_clk_int , -- out
Bus2IP_Resetn => bus2ip_reset_int, -- out
----------------------------------------------------------
Bus2IP_Addr => open, -- out -- not used signal
Bus2IP_RNW => open, -- out
Bus2IP_BE => open, -- bus2ip_be_int, -- out
Bus2IP_CS => open, -- out -- not used signal
Bus2IP_RdCE => bus2ip_xip_rdce_int, -- out -- little endian
Bus2IP_WrCE => bus2ip_xip_wrce_int, -- out -- little endian
Bus2IP_Data => bus2ip_data_int, -- out -- little endian
----------------------------------------------------------
IP2Bus_Data => ip2bus_data_int, -- in -- little endian
IP2Bus_WrAck => ip2bus_wrack_int, -- in
IP2Bus_RdAck => ip2bus_rdack_int, -- in
IP2Bus_Error => ip2bus_error_int -- in
----------------------------------------------------------
);
--------------------------------------------------------------------------
ip2bus_error_int <= '0'; -- there is no error in this mode
----------------------
--REG_RST_FRM_IPIF: convert active low to active hig reset to rest of
-- the core.
----------------------
REG_RST_FRM_IPIF: process (S_AXI_ACLK) is
begin
if(S_AXI_ACLK'event and S_AXI_ACLK = '1') then
bus2ip_reset_ipif_inverted <= not(S_AXI_ARESETN);
end if;
end process REG_RST_FRM_IPIF;
--------------------------------------------------------------------------
XIP_CR_I : entity axi_quad_spi_v3_1.xip_cntrl_reg
generic map
(
C_XIP_SPICR_REG_WIDTH => C_XIP_SPICR_REG_WIDTH,
C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH ,
C_SPI_MODE => C_SPI_MODE
)
port map(
Bus2IP_Clk => S_AXI_ACLK, -- : in std_logic;
Soft_Reset_op => bus2ip_reset_ipif_inverted, -- : in std_logic;
------------------------
Bus2IP_XIPCR_WrCE => bus2ip_xip_wrce_int(XIPCR), -- : in std_logic;
Bus2IP_XIPCR_RdCE => bus2ip_xip_rdce_int(XIPCR), -- : in std_logic;
Bus2IP_XIPCR_data => bus2ip_data_int , -- : in std_logic_vector(0 to (C_S_AXI_DATA_WIDTH-1));
------------------------
ip2Bus_RdAck_core => ip2Bus_RdAck_core_reg_d2, -- IP2Bus_XIPCR_WrAck,
ip2Bus_WrAck_core => ip2Bus_WrAck_core_reg, -- IP2Bus_XIPCR_RdAck,
------------------------
--XIPCR_7_0_CMD => XIPCR_7_0_CMD, -- out std_logic_vector;
XIPCR_1_CPOL => XIPCR_1_CPOL_int , -- out std_logic;
XIPCR_0_CPHA => XIPCR_0_CPHA_int , -- out std_logic;
------------------------
IP2Bus_XIPCR_Data => IP2Bus_XIPCR_Data_int, -- out std_logic;
------------------------
TO_XIPSR_CPHA_CPOL_ERR=> TO_XIPSR_CPHA_CPOL_ERR_int -- out std_logic
);
--------------------------------------------------------------------------
REG_WR_ACK_P:process(S_AXI_ACLK)is
begin
-----
if(S_AXI_ACLK'event and S_AXI_ACLK = '1') then
if(bus2ip_reset_ipif_inverted = '1')then
ip2Bus_WrAck_core_reg_d1 <= '0';
ip2Bus_WrAck_core_reg <= '0';
else
ip2Bus_WrAck_core_reg_d1 <= bus2ip_xip_wrce_int(XIPCR) or
bus2ip_xip_wrce_int(XIPSR);
ip2Bus_WrAck_core_reg <= (bus2ip_xip_wrce_int(XIPCR) or
bus2ip_xip_wrce_int(XIPSR)) and
(not ip2Bus_WrAck_core_reg_d1);
end if;
end if;
end process REG_WR_ACK_P;
-------------------------
ip2bus_wrack_int <= ip2Bus_WrAck_core_reg;
-------------------------
REG_RD_ACK_P:process(S_AXI_ACLK)is
begin
-----
if(S_AXI_ACLK'event and S_AXI_ACLK = '1') then
if(bus2ip_reset_ipif_inverted = '1')then
ip2Bus_RdAck_core_reg_d1 <= '0';
ip2Bus_RdAck_core_reg_d2 <= '0';
ip2Bus_RdAck_core_reg_d3 <= '0';
else
ip2Bus_RdAck_core_reg_d1 <= bus2ip_xip_rdce_int(XIPCR) or
bus2ip_xip_rdce_int(XIPSR);
ip2Bus_RdAck_core_reg_d2 <= (bus2ip_xip_rdce_int(XIPCR) or
bus2ip_xip_rdce_int(XIPSR)) and
(not ip2Bus_RdAck_core_reg_d1);
ip2Bus_RdAck_core_reg_d3 <= ip2Bus_RdAck_core_reg_d2;
end if;
end if;
end process REG_RD_ACK_P;
-------------------------
ip2bus_rdack_int <= ip2Bus_RdAck_core_reg_d3;
-------------------------
REG_IP2BUS_DATA_P:process(S_AXI_ACLK)is
begin
-----
if(S_AXI_ACLK'event and S_AXI_ACLK = '1') then
if(bus2ip_reset_ipif_inverted = '1')then
ip2bus_data_int <= (others => '0');
elsif(ip2Bus_RdAck_core_reg_d2 = '1') then
ip2bus_data_int <= ("000000000000000000000000000000" & IP2Bus_XIPCR_Data_int) or
("000000000000000000000000000" & IP2Bus_XIPSR_Data_int);
end if;
end if;
end process REG_IP2BUS_DATA_P;
-------------------------
--------------------------------------------------------------------------
XIP_SR_I : entity axi_quad_spi_v3_1.xip_status_reg
generic map
(
C_XIP_SPISR_REG_WIDTH => C_XIP_SPISR_REG_WIDTH,
C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH
)
port map(
Bus2IP_Clk => S_AXI_ACLK, -- : in std_logic;
Soft_Reset_op => bus2ip_reset_ipif_inverted, -- : in std_logic;
------------------------
XIPSR_AXI_TR_ERR => TO_XIPSR_AXI_TR_ERR_int, -- : in std_logic;
XIPSR_CPHA_CPOL_ERR => TO_XIPSR_CPHA_CPOL_ERR_int, -- : in std_logic;
XIPSR_MST_MODF_ERR => TO_XIPSR_mst_modf_err_int, -- : in std_logic;
XIPSR_AXI_RX_FULL => TO_XIPSR_axi_rx_full_int, -- : in std_logic;
XIPSR_AXI_RX_EMPTY => TO_XIPSR_axi_rx_empty_int, -- : in std_logic;
------------------------
Bus2IP_XIPSR_WrCE => bus2ip_xip_wrce_int(XIPSR),
Bus2IP_XIPSR_RdCE => bus2ip_xip_rdce_int(XIPSR),
-------------------
IP2Bus_XIPSR_Data => IP2Bus_XIPSR_Data_int ,
ip2Bus_RdAck => ip2Bus_RdAck_core_reg_d3
);
---------------------------------------------------------------------------
--REG_RST4_FRM_IPIF: convert active low to active hig reset to rest of
-- the core.
----------------------
REG_RST4_FRM_IPIF: process (S_AXI4_ACLK) is
begin
if(S_AXI4_ACLK'event and S_AXI4_ACLK = '1') then
bus2ip_reset_ipif4_inverted <= not(S_AXI4_ARESETN);
end if;
end process REG_RST4_FRM_IPIF;
-------------------------------------------------------------------------
RESET_SYNC_AXI_SPI_CLK_INST:entity axi_quad_spi_v3_1.reset_sync_module
port map(
EXT_SPI_CLK => EXT_SPI_CLK ,-- in std_logic;
Soft_Reset_frm_axi => bus2ip_reset_ipif4_inverted ,-- in std_logic;
Rst_to_spi => Rst_to_spi_int -- out std_logic;
);
--------------------------------------------------------------------------
AXI_QSPI_XIP_I : entity axi_quad_spi_v3_1.axi_qspi_xip_if
generic map
(
C_FAMILY => C_FAMILY ,
C_SUB_FAMILY => C_SUB_FAMILY ,
-------------------------
--C_TYPE_OF_AXI4_INTERFACE => C_TYPE_OF_AXI4_INTERFACE,
--C_XIP_MODE => C_XIP_MODE ,
--C_AXI4_CLK_PS => C_AXI4_CLK_PS ,
--C_EXT_SPI_CLK_PS => C_EXT_SPI_CLK_PS ,
--C_FIFO_DEPTH => C_FIFO_DEPTH_UPDATED ,
C_SPI_MEM_ADDR_BITS => C_SPI_MEM_ADDR_BITS ,
C_SCK_RATIO => C_SCK_RATIO ,
C_NUM_SS_BITS => C_NUM_SS_BITS ,
C_NUM_TRANSFER_BITS => C_NUM_TRANSFER_BITS ,
-------------------------
C_SPI_MODE => C_SPI_MODE ,
C_USE_STARTUP => C_USE_STARTUP ,
C_SPI_MEMORY => C_SPI_MEMORY ,
-------------------------
-- AXI4 Full Interface Parameters
C_S_AXI4_ADDR_WIDTH => C_S_AXI4_ADDR_WIDTH ,
C_S_AXI4_DATA_WIDTH => C_S_AXI4_DATA_WIDTH ,
C_S_AXI4_ID_WIDTH => C_S_AXI4_ID_WIDTH ,
-------------------------
--*C_AXI4_BASEADDR => C_S_AXI4_BASEADDR ,
--*C_AXI4_HIGHADDR => C_S_AXI4_HIGHADDR ,
-------------------------
--C_XIP_SPICR_REG_WIDTH => C_XIP_SPICR_REG_WIDTH ,
--C_XIP_SPISR_REG_WIDTH => C_XIP_SPISR_REG_WIDTH ,
-------------------------
C_XIP_FULL_ARD_ADDR_RANGE_ARRAY => C_XIP_FULL_ARD_ADDR_RANGE_ARRAY,
C_XIP_FULL_ARD_NUM_CE_ARRAY => C_XIP_FULL_ARD_NUM_CE_ARRAY
)
port map
(
-- external async clock for SPI interface logic
EXT_SPI_CLK => ext_spi_clk , -- : in std_logic;
Rst_to_spi => Rst_to_spi_int,
----------------------------------
S_AXI_ACLK => s_axi_aclk , -- : in std_logic;
S_AXI_ARESETN => bus2ip_reset_ipif_inverted, -- : in std_logic;
----------------------------------
S_AXI4_ACLK => s_axi4_aclk , -- : in std_logic;
S_AXI4_ARESET => bus2ip_reset_ipif4_inverted, -- : in std_logic;
-------------------------------
--*AXI4 Full port interface* --
-------------------------------
------------------------------------
-- AXI Write Address Channel Signals
------------------------------------
S_AXI4_AWID => s_axi4_awid , -- : in std_logic_vector((C_S_AXI4_ID_WIDTH-1) downto 0);
S_AXI4_AWADDR => s_axi4_awaddr , -- : in std_logic_vector((C_S_AXI4_ADDR_WIDTH-1) downto 0);
S_AXI4_AWLEN => s_axi4_awlen , -- : in std_logic_vector(7 downto 0);
S_AXI4_AWSIZE => s_axi4_awsize , -- : in std_logic_vector(2 downto 0);
S_AXI4_AWBURST => s_axi4_awburst, -- : in std_logic_vector(1 downto 0);
S_AXI4_AWLOCK => s_axi4_awlock , -- : in std_logic; -- not supported in design
S_AXI4_AWCACHE => s_axi4_awcache, -- : in std_logic_vector(3 downto 0);-- not supported in design
S_AXI4_AWPROT => s_axi4_awprot , -- : in std_logic_vector(2 downto 0);-- not supported in design
S_AXI4_AWVALID => s_axi4_awvalid, -- : in std_logic;
S_AXI4_AWREADY => s_axi4_awready, -- : out std_logic;
---------------------------------------
-- AXI4 Full Write data channel Signals
---------------------------------------
S_AXI4_WDATA => s_axi4_wdata , -- : in std_logic_vector((C_S_AXI4_DATA_WIDTH-1)downto 0);
S_AXI4_WSTRB => s_axi4_wstrb , -- : in std_logic_vector(((C_S_AXI4_DATA_WIDTH/8)-1) downto 0);
S_AXI4_WLAST => s_axi4_wlast , -- : in std_logic;
S_AXI4_WVALID => s_axi4_wvalid , -- : in std_logic;
S_AXI4_WREADY => s_axi4_wready , -- : out std_logic;
-------------------------------------------
-- AXI4 Full Write response channel Signals
-------------------------------------------
S_AXI4_BID => s_axi4_bid , -- : out std_logic_vector((C_S_AXI4_ID_WIDTH-1) downto 0);
S_AXI4_BRESP => s_axi4_bresp , -- : out std_logic_vector(1 downto 0);
S_AXI4_BVALID => s_axi4_bvalid , -- : out std_logic;
S_AXI4_BREADY => s_axi4_bready , -- : in std_logic;
-----------------------------------
-- AXI Read Address channel signals
-----------------------------------
S_AXI4_ARID => s_axi4_arid , -- : in std_logic_vector((C_S_AXI4_ID_WIDTH-1) downto 0);
S_AXI4_ARADDR => s_axi4_araddr , -- : in std_logic_vector((C_S_AXI4_ADDR_WIDTH-1) downto 0);
S_AXI4_ARLEN => s_axi4_arlen , -- : in std_logic_vector(7 downto 0);
S_AXI4_ARSIZE => s_axi4_arsize , -- : in std_logic_vector(2 downto 0);
S_AXI4_ARBURST => s_axi4_arburst, -- : in std_logic_vector(1 downto 0);
S_AXI4_ARLOCK => s_axi4_arlock , -- : in std_logic; -- not supported in design
S_AXI4_ARCACHE => s_axi4_arcache, -- : in std_logic_vector(3 downto 0);-- not supported in design
S_AXI4_ARPROT => s_axi4_arprot , -- : in std_logic_vector(2 downto 0);-- not supported in design
S_AXI4_ARVALID => s_axi4_arvalid, -- : in std_logic;
S_AXI4_ARREADY => s_axi4_arready, -- : out std_logic;
--------------------------------
-- AXI Read Data Channel signals
--------------------------------
S_AXI4_RID => s_axi4_rid , -- : out std_logic_vector((C_S_AXI4_ID_WIDTH-1) downto 0);
S_AXI4_RDATA => s_axi4_rdata , -- : out std_logic_vector((C_S_AXI4_DATA_WIDTH-1) downto 0);
S_AXI4_RRESP => s_axi4_rresp , -- : out std_logic_vector(1 downto 0);
S_AXI4_RLAST => s_axi4_rlast , -- : out std_logic;
S_AXI4_RVALID => s_axi4_rvalid, -- : out std_logic;
S_AXI4_RREADY => s_axi4_rready, -- : in std_logic;
--------------------------------
XIPSR_CPHA_CPOL_ERR => TO_XIPSR_CPHA_CPOL_ERR_int , -- in std_logic
-------------------------------
TO_XIPSR_trans_error => TO_XIPSR_AXI_TR_ERR_int , -- out std_logic
TO_XIPSR_mst_modf_err => TO_XIPSR_mst_modf_err_int,
TO_XIPSR_axi_rx_full => TO_XIPSR_axi_rx_full_int ,
TO_XIPSR_axi_rx_empty => TO_XIPSR_axi_rx_empty_int,
-------------------------------
XIPCR_1_CPOL => XIPCR_1_CPOL_int , -- out std_logic;
XIPCR_0_CPHA => XIPCR_0_CPHA_int , -- out std_logic;
--*SPI port interface * --
-------------------------------
IO0_I => io0_i, -- : in std_logic; -- MOSI signal in standard SPI
IO0_O => io0_o, -- : out std_logic;
IO0_T => io0_t, -- : out std_logic;
-------------------------------
IO1_I => MISO_I_int, -- : in std_logic; -- MISO signal in standard SPI
IO1_O => io1_o, -- : out std_logic;
IO1_T => io1_t, -- : out std_logic;
-----------------
-- quad mode pins
-----------------
IO2_I => io2_i, -- : in std_logic;
IO2_O => io2_o, -- : out std_logic;
IO2_T => io2_t, -- : out std_logic;
---------------
IO3_I => io3_i, -- : in std_logic;
IO3_O => io3_o, -- : out std_logic;
IO3_T => io3_t, -- : out std_logic;
---------------------------------
-- common pins
----------------
SPISEL => spisel, -- : in std_logic;
-----
SCK_I => sck_i , -- : in std_logic;
SCK_O_reg => SCK_O_int , -- : out std_logic;
SCK_T => sck_t , -- : out std_logic;
-----
SS_I => ss_i , -- : in std_logic_vector((C_NUM_SS_BITS-1) downto 0);
SS_O => ss_o , -- : out std_logic_vector((C_NUM_SS_BITS-1) downto 0);
SS_T => ss_t -- : out std_logic;
----------------------
);
-- no interrupt from this mode of core
IP2INTC_Irpt <= '0';
-------------------------------------------------------
-------------------------------------------------------
SCK_MISO_NO_STARTUP_USED: if C_USE_STARTUP = 0 generate
-----
begin
-----
SCK_O <= SCK_O_int; -- output from the core
MISO_I_int <= IO1_I; -- input to the core
end generate SCK_MISO_NO_STARTUP_USED;
-------------------------------------------------------
SCK_MISO_STARTUP_USED: if C_USE_STARTUP = 1 generate
-----
begin
-----
QSPI_STARTUP_BLOCK_I: entity axi_quad_spi_v3_1.qspi_startup_block
---------------------
generic map
(
C_SUB_FAMILY => C_SUB_FAMILY , -- support for V6/V7/K7/A7 families only
-----------------
C_USE_STARTUP => C_USE_STARTUP,
-----------------
C_SPI_MODE => C_SPI_MODE
-----------------
)
port map
(
SCK_O => SCK_O_int, -- : in std_logic; -- input from the qspi_mode_0_module
IO1_I_startup => IO1_I, -- : in std_logic; -- input from the top level port list
IO1_Int => MISO_I_int,-- : out std_logic
Bus2IP_Clk => Bus2IP_Clk,
reset2ip_reset => Rst_to_spi_int
);
--------------------
end generate SCK_MISO_STARTUP_USED;
end generate XIP_MODE_GEN;
------------------------------------------------------------------------------
end architecture imp;
------------------------------------------------------------------------------
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2013.4
-- Copyright (C) 2013 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity nfa_accept_samples_generic_hw_add_17ns_17s_17_4_AddSubnS_5 is
port (
clk: in std_logic;
reset: in std_logic;
ce: in std_logic;
a: in std_logic_vector(16 downto 0);
b: in std_logic_vector(16 downto 0);
s: out std_logic_vector(16 downto 0));
end entity;
architecture behav of nfa_accept_samples_generic_hw_add_17ns_17s_17_4_AddSubnS_5 is
component nfa_accept_samples_generic_hw_add_17ns_17s_17_4_AddSubnS_5_fadder is
port (
faa : IN STD_LOGIC_VECTOR (5-1 downto 0);
fab : IN STD_LOGIC_VECTOR (5-1 downto 0);
facin : IN STD_LOGIC_VECTOR (0 downto 0);
fas : OUT STD_LOGIC_VECTOR (5-1 downto 0);
facout : OUT STD_LOGIC_VECTOR (0 downto 0));
end component;
component nfa_accept_samples_generic_hw_add_17ns_17s_17_4_AddSubnS_5_fadder_f is
port (
faa : IN STD_LOGIC_VECTOR (2-1 downto 0);
fab : IN STD_LOGIC_VECTOR (2-1 downto 0);
facin : IN STD_LOGIC_VECTOR (0 downto 0);
fas : OUT STD_LOGIC_VECTOR (2-1 downto 0);
facout : OUT STD_LOGIC_VECTOR (0 downto 0));
end component;
-- ---- register and wire type variables list here ----
-- wire for the primary inputs
signal a_reg : std_logic_vector(16 downto 0);
signal b_reg : std_logic_vector(16 downto 0);
-- wires for each small adder
signal a0_cb : std_logic_vector(4 downto 0);
signal b0_cb : std_logic_vector(4 downto 0);
signal a1_cb : std_logic_vector(9 downto 5);
signal b1_cb : std_logic_vector(9 downto 5);
signal a2_cb : std_logic_vector(14 downto 10);
signal b2_cb : std_logic_vector(14 downto 10);
signal a3_cb : std_logic_vector(16 downto 15);
signal b3_cb : std_logic_vector(16 downto 15);
-- registers for input register array
type ramtypei0 is array (0 downto 0) of std_logic_vector(4 downto 0);
signal a1_cb_regi1 : ramtypei0;
signal b1_cb_regi1 : ramtypei0;
type ramtypei1 is array (1 downto 0) of std_logic_vector(4 downto 0);
signal a2_cb_regi2 : ramtypei1;
signal b2_cb_regi2 : ramtypei1;
type ramtypei2 is array (2 downto 0) of std_logic_vector(1 downto 0);
signal a3_cb_regi3 : ramtypei2;
signal b3_cb_regi3 : ramtypei2;
-- wires for each full adder sum
signal fas : std_logic_vector(16 downto 0);
-- wires and register for carry out bit
signal faccout_ini : std_logic_vector (0 downto 0);
signal faccout0_co0 : std_logic_vector (0 downto 0);
signal faccout1_co1 : std_logic_vector (0 downto 0);
signal faccout2_co2 : std_logic_vector (0 downto 0);
signal faccout3_co3 : std_logic_vector (0 downto 0);
signal faccout0_co0_reg : std_logic_vector (0 downto 0);
signal faccout1_co1_reg : std_logic_vector (0 downto 0);
signal faccout2_co2_reg : std_logic_vector (0 downto 0);
-- registers for output register array
type ramtypeo2 is array (2 downto 0) of std_logic_vector(4 downto 0);
signal s0_ca_rego0 : ramtypeo2;
type ramtypeo1 is array (1 downto 0) of std_logic_vector(4 downto 0);
signal s1_ca_rego1 : ramtypeo1;
type ramtypeo0 is array (0 downto 0) of std_logic_vector(4 downto 0);
signal s2_ca_rego2 : ramtypeo0;
-- wire for the temporary output
signal s_tmp : std_logic_vector(16 downto 0);
-- ---- RTL code for assignment statements/always blocks/module instantiations here ----
begin
a_reg <= a;
b_reg <= b;
-- small adder input assigments
a0_cb <= a_reg(4 downto 0);
b0_cb <= b_reg(4 downto 0);
a1_cb <= a_reg(9 downto 5);
b1_cb <= b_reg(9 downto 5);
a2_cb <= a_reg(14 downto 10);
b2_cb <= b_reg(14 downto 10);
a3_cb <= a_reg(16 downto 15);
b3_cb <= b_reg(16 downto 15);
-- input register array
process (clk)
begin
if (clk'event and clk='1') then
if (ce='1') then
a1_cb_regi1 (0) <= a1_cb;
b1_cb_regi1 (0) <= b1_cb;
a2_cb_regi2 (0) <= a2_cb;
b2_cb_regi2 (0) <= b2_cb;
a3_cb_regi3 (0) <= a3_cb;
b3_cb_regi3 (0) <= b3_cb;
a2_cb_regi2 (1) <= a2_cb_regi2 (0);
b2_cb_regi2 (1) <= b2_cb_regi2 (0);
a3_cb_regi3 (1) <= a3_cb_regi3 (0);
b3_cb_regi3 (1) <= b3_cb_regi3 (0);
a3_cb_regi3 (2) <= a3_cb_regi3 (1);
b3_cb_regi3 (2) <= b3_cb_regi3 (1);
end if;
end if;
end process;
-- carry out bit processing
process (clk)
begin
if (clk'event and clk='1') then
if (ce='1') then
faccout0_co0_reg <= faccout0_co0;
faccout1_co1_reg <= faccout1_co1;
faccout2_co2_reg <= faccout2_co2;
end if;
end if;
end process;
-- small adder generation
u0 : nfa_accept_samples_generic_hw_add_17ns_17s_17_4_AddSubnS_5_fadder
port map
(faa => a0_cb,
fab => b0_cb,
facin => faccout_ini,
fas => fas(4 downto 0),
facout => faccout0_co0);
u1 : nfa_accept_samples_generic_hw_add_17ns_17s_17_4_AddSubnS_5_fadder
port map
(faa => a1_cb_regi1(0),
fab => b1_cb_regi1(0),
facin => faccout0_co0_reg,
fas => fas(9 downto 5),
facout => faccout1_co1);
u2 : nfa_accept_samples_generic_hw_add_17ns_17s_17_4_AddSubnS_5_fadder
port map
(faa => a2_cb_regi2(1),
fab => b2_cb_regi2(1),
facin => faccout1_co1_reg,
fas => fas(14 downto 10),
facout => faccout2_co2);
u3 : nfa_accept_samples_generic_hw_add_17ns_17s_17_4_AddSubnS_5_fadder_f
port map
(faa => a3_cb_regi3(2),
fab => b3_cb_regi3(2),
facin => faccout2_co2_reg,
fas => fas(16 downto 15),
facout => faccout3_co3);
faccout_ini <= "0";
-- output register array
process (clk)
begin
if (clk'event and clk='1') then
if (ce='1') then
s0_ca_rego0 (0) <= fas(4 downto 0);
s1_ca_rego1 (0) <= fas(9 downto 5);
s2_ca_rego2 (0) <= fas(14 downto 10);
s0_ca_rego0 (1) <= s0_ca_rego0 (0);
s0_ca_rego0 (2) <= s0_ca_rego0 (1);
s1_ca_rego1 (1) <= s1_ca_rego1 (0);
end if;
end if;
end process;
-- get the s_tmp, assign it to the primary output
s_tmp(4 downto 0) <= s0_ca_rego0(2);
s_tmp(9 downto 5) <= s1_ca_rego1(1);
s_tmp(14 downto 10) <= s2_ca_rego2(0);
s_tmp(16 downto 15) <= fas(16 downto 15);
s <= s_tmp;
end architecture;
-- short adder
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity nfa_accept_samples_generic_hw_add_17ns_17s_17_4_AddSubnS_5_fadder is
generic(N : natural :=5);
port (
faa : IN STD_LOGIC_VECTOR (N-1 downto 0);
fab : IN STD_LOGIC_VECTOR (N-1 downto 0);
facin : IN STD_LOGIC_VECTOR (0 downto 0);
fas : OUT STD_LOGIC_VECTOR (N-1 downto 0);
facout : OUT STD_LOGIC_VECTOR (0 downto 0));
end;
architecture behav of nfa_accept_samples_generic_hw_add_17ns_17s_17_4_AddSubnS_5_fadder is
signal tmp : STD_LOGIC_VECTOR (N downto 0);
begin
tmp <= std_logic_vector(unsigned(std_logic_vector(unsigned(std_logic_vector(resize(unsigned(faa),N+1))) + unsigned(fab))) + unsigned(facin));
fas <= tmp(N-1 downto 0 );
facout <= tmp(N downto N);
end behav;
-- the final stage short adder
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity nfa_accept_samples_generic_hw_add_17ns_17s_17_4_AddSubnS_5_fadder_f is
generic(N : natural :=2);
port (
faa : IN STD_LOGIC_VECTOR (N-1 downto 0);
fab : IN STD_LOGIC_VECTOR (N-1 downto 0);
facin : IN STD_LOGIC_VECTOR (0 downto 0);
fas : OUT STD_LOGIC_VECTOR (N-1 downto 0);
facout : OUT STD_LOGIC_VECTOR (0 downto 0));
end;
architecture behav of nfa_accept_samples_generic_hw_add_17ns_17s_17_4_AddSubnS_5_fadder_f is
signal tmp : STD_LOGIC_VECTOR (N downto 0);
begin
tmp <= std_logic_vector(unsigned(std_logic_vector(unsigned(std_logic_vector(resize(unsigned(faa),N+1))) + unsigned(fab))) + unsigned(facin));
fas <= tmp(N-1 downto 0 );
facout <= tmp(N downto N);
end behav;
Library IEEE;
use IEEE.std_logic_1164.all;
entity nfa_accept_samples_generic_hw_add_17ns_17s_17_4 is
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
ce : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR(din0_WIDTH - 1 DOWNTO 0);
din1 : IN STD_LOGIC_VECTOR(din1_WIDTH - 1 DOWNTO 0);
dout : OUT STD_LOGIC_VECTOR(dout_WIDTH - 1 DOWNTO 0));
end entity;
architecture arch of nfa_accept_samples_generic_hw_add_17ns_17s_17_4 is
component nfa_accept_samples_generic_hw_add_17ns_17s_17_4_AddSubnS_5 is
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
ce : IN STD_LOGIC;
a : IN STD_LOGIC_VECTOR;
b : IN STD_LOGIC_VECTOR;
s : OUT STD_LOGIC_VECTOR);
end component;
begin
nfa_accept_samples_generic_hw_add_17ns_17s_17_4_AddSubnS_5_U : component nfa_accept_samples_generic_hw_add_17ns_17s_17_4_AddSubnS_5
port map (
clk => clk,
reset => reset,
ce => ce,
a => din0,
b => din1,
s => dout);
end architecture;
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2013.4
-- Copyright (C) 2013 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity nfa_accept_samples_generic_hw_add_17ns_17s_17_4_AddSubnS_5 is
port (
clk: in std_logic;
reset: in std_logic;
ce: in std_logic;
a: in std_logic_vector(16 downto 0);
b: in std_logic_vector(16 downto 0);
s: out std_logic_vector(16 downto 0));
end entity;
architecture behav of nfa_accept_samples_generic_hw_add_17ns_17s_17_4_AddSubnS_5 is
component nfa_accept_samples_generic_hw_add_17ns_17s_17_4_AddSubnS_5_fadder is
port (
faa : IN STD_LOGIC_VECTOR (5-1 downto 0);
fab : IN STD_LOGIC_VECTOR (5-1 downto 0);
facin : IN STD_LOGIC_VECTOR (0 downto 0);
fas : OUT STD_LOGIC_VECTOR (5-1 downto 0);
facout : OUT STD_LOGIC_VECTOR (0 downto 0));
end component;
component nfa_accept_samples_generic_hw_add_17ns_17s_17_4_AddSubnS_5_fadder_f is
port (
faa : IN STD_LOGIC_VECTOR (2-1 downto 0);
fab : IN STD_LOGIC_VECTOR (2-1 downto 0);
facin : IN STD_LOGIC_VECTOR (0 downto 0);
fas : OUT STD_LOGIC_VECTOR (2-1 downto 0);
facout : OUT STD_LOGIC_VECTOR (0 downto 0));
end component;
-- ---- register and wire type variables list here ----
-- wire for the primary inputs
signal a_reg : std_logic_vector(16 downto 0);
signal b_reg : std_logic_vector(16 downto 0);
-- wires for each small adder
signal a0_cb : std_logic_vector(4 downto 0);
signal b0_cb : std_logic_vector(4 downto 0);
signal a1_cb : std_logic_vector(9 downto 5);
signal b1_cb : std_logic_vector(9 downto 5);
signal a2_cb : std_logic_vector(14 downto 10);
signal b2_cb : std_logic_vector(14 downto 10);
signal a3_cb : std_logic_vector(16 downto 15);
signal b3_cb : std_logic_vector(16 downto 15);
-- registers for input register array
type ramtypei0 is array (0 downto 0) of std_logic_vector(4 downto 0);
signal a1_cb_regi1 : ramtypei0;
signal b1_cb_regi1 : ramtypei0;
type ramtypei1 is array (1 downto 0) of std_logic_vector(4 downto 0);
signal a2_cb_regi2 : ramtypei1;
signal b2_cb_regi2 : ramtypei1;
type ramtypei2 is array (2 downto 0) of std_logic_vector(1 downto 0);
signal a3_cb_regi3 : ramtypei2;
signal b3_cb_regi3 : ramtypei2;
-- wires for each full adder sum
signal fas : std_logic_vector(16 downto 0);
-- wires and register for carry out bit
signal faccout_ini : std_logic_vector (0 downto 0);
signal faccout0_co0 : std_logic_vector (0 downto 0);
signal faccout1_co1 : std_logic_vector (0 downto 0);
signal faccout2_co2 : std_logic_vector (0 downto 0);
signal faccout3_co3 : std_logic_vector (0 downto 0);
signal faccout0_co0_reg : std_logic_vector (0 downto 0);
signal faccout1_co1_reg : std_logic_vector (0 downto 0);
signal faccout2_co2_reg : std_logic_vector (0 downto 0);
-- registers for output register array
type ramtypeo2 is array (2 downto 0) of std_logic_vector(4 downto 0);
signal s0_ca_rego0 : ramtypeo2;
type ramtypeo1 is array (1 downto 0) of std_logic_vector(4 downto 0);
signal s1_ca_rego1 : ramtypeo1;
type ramtypeo0 is array (0 downto 0) of std_logic_vector(4 downto 0);
signal s2_ca_rego2 : ramtypeo0;
-- wire for the temporary output
signal s_tmp : std_logic_vector(16 downto 0);
-- ---- RTL code for assignment statements/always blocks/module instantiations here ----
begin
a_reg <= a;
b_reg <= b;
-- small adder input assigments
a0_cb <= a_reg(4 downto 0);
b0_cb <= b_reg(4 downto 0);
a1_cb <= a_reg(9 downto 5);
b1_cb <= b_reg(9 downto 5);
a2_cb <= a_reg(14 downto 10);
b2_cb <= b_reg(14 downto 10);
a3_cb <= a_reg(16 downto 15);
b3_cb <= b_reg(16 downto 15);
-- input register array
process (clk)
begin
if (clk'event and clk='1') then
if (ce='1') then
a1_cb_regi1 (0) <= a1_cb;
b1_cb_regi1 (0) <= b1_cb;
a2_cb_regi2 (0) <= a2_cb;
b2_cb_regi2 (0) <= b2_cb;
a3_cb_regi3 (0) <= a3_cb;
b3_cb_regi3 (0) <= b3_cb;
a2_cb_regi2 (1) <= a2_cb_regi2 (0);
b2_cb_regi2 (1) <= b2_cb_regi2 (0);
a3_cb_regi3 (1) <= a3_cb_regi3 (0);
b3_cb_regi3 (1) <= b3_cb_regi3 (0);
a3_cb_regi3 (2) <= a3_cb_regi3 (1);
b3_cb_regi3 (2) <= b3_cb_regi3 (1);
end if;
end if;
end process;
-- carry out bit processing
process (clk)
begin
if (clk'event and clk='1') then
if (ce='1') then
faccout0_co0_reg <= faccout0_co0;
faccout1_co1_reg <= faccout1_co1;
faccout2_co2_reg <= faccout2_co2;
end if;
end if;
end process;
-- small adder generation
u0 : nfa_accept_samples_generic_hw_add_17ns_17s_17_4_AddSubnS_5_fadder
port map
(faa => a0_cb,
fab => b0_cb,
facin => faccout_ini,
fas => fas(4 downto 0),
facout => faccout0_co0);
u1 : nfa_accept_samples_generic_hw_add_17ns_17s_17_4_AddSubnS_5_fadder
port map
(faa => a1_cb_regi1(0),
fab => b1_cb_regi1(0),
facin => faccout0_co0_reg,
fas => fas(9 downto 5),
facout => faccout1_co1);
u2 : nfa_accept_samples_generic_hw_add_17ns_17s_17_4_AddSubnS_5_fadder
port map
(faa => a2_cb_regi2(1),
fab => b2_cb_regi2(1),
facin => faccout1_co1_reg,
fas => fas(14 downto 10),
facout => faccout2_co2);
u3 : nfa_accept_samples_generic_hw_add_17ns_17s_17_4_AddSubnS_5_fadder_f
port map
(faa => a3_cb_regi3(2),
fab => b3_cb_regi3(2),
facin => faccout2_co2_reg,
fas => fas(16 downto 15),
facout => faccout3_co3);
faccout_ini <= "0";
-- output register array
process (clk)
begin
if (clk'event and clk='1') then
if (ce='1') then
s0_ca_rego0 (0) <= fas(4 downto 0);
s1_ca_rego1 (0) <= fas(9 downto 5);
s2_ca_rego2 (0) <= fas(14 downto 10);
s0_ca_rego0 (1) <= s0_ca_rego0 (0);
s0_ca_rego0 (2) <= s0_ca_rego0 (1);
s1_ca_rego1 (1) <= s1_ca_rego1 (0);
end if;
end if;
end process;
-- get the s_tmp, assign it to the primary output
s_tmp(4 downto 0) <= s0_ca_rego0(2);
s_tmp(9 downto 5) <= s1_ca_rego1(1);
s_tmp(14 downto 10) <= s2_ca_rego2(0);
s_tmp(16 downto 15) <= fas(16 downto 15);
s <= s_tmp;
end architecture;
-- short adder
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity nfa_accept_samples_generic_hw_add_17ns_17s_17_4_AddSubnS_5_fadder is
generic(N : natural :=5);
port (
faa : IN STD_LOGIC_VECTOR (N-1 downto 0);
fab : IN STD_LOGIC_VECTOR (N-1 downto 0);
facin : IN STD_LOGIC_VECTOR (0 downto 0);
fas : OUT STD_LOGIC_VECTOR (N-1 downto 0);
facout : OUT STD_LOGIC_VECTOR (0 downto 0));
end;
architecture behav of nfa_accept_samples_generic_hw_add_17ns_17s_17_4_AddSubnS_5_fadder is
signal tmp : STD_LOGIC_VECTOR (N downto 0);
begin
tmp <= std_logic_vector(unsigned(std_logic_vector(unsigned(std_logic_vector(resize(unsigned(faa),N+1))) + unsigned(fab))) + unsigned(facin));
fas <= tmp(N-1 downto 0 );
facout <= tmp(N downto N);
end behav;
-- the final stage short adder
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity nfa_accept_samples_generic_hw_add_17ns_17s_17_4_AddSubnS_5_fadder_f is
generic(N : natural :=2);
port (
faa : IN STD_LOGIC_VECTOR (N-1 downto 0);
fab : IN STD_LOGIC_VECTOR (N-1 downto 0);
facin : IN STD_LOGIC_VECTOR (0 downto 0);
fas : OUT STD_LOGIC_VECTOR (N-1 downto 0);
facout : OUT STD_LOGIC_VECTOR (0 downto 0));
end;
architecture behav of nfa_accept_samples_generic_hw_add_17ns_17s_17_4_AddSubnS_5_fadder_f is
signal tmp : STD_LOGIC_VECTOR (N downto 0);
begin
tmp <= std_logic_vector(unsigned(std_logic_vector(unsigned(std_logic_vector(resize(unsigned(faa),N+1))) + unsigned(fab))) + unsigned(facin));
fas <= tmp(N-1 downto 0 );
facout <= tmp(N downto N);
end behav;
Library IEEE;
use IEEE.std_logic_1164.all;
entity nfa_accept_samples_generic_hw_add_17ns_17s_17_4 is
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
ce : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR(din0_WIDTH - 1 DOWNTO 0);
din1 : IN STD_LOGIC_VECTOR(din1_WIDTH - 1 DOWNTO 0);
dout : OUT STD_LOGIC_VECTOR(dout_WIDTH - 1 DOWNTO 0));
end entity;
architecture arch of nfa_accept_samples_generic_hw_add_17ns_17s_17_4 is
component nfa_accept_samples_generic_hw_add_17ns_17s_17_4_AddSubnS_5 is
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
ce : IN STD_LOGIC;
a : IN STD_LOGIC_VECTOR;
b : IN STD_LOGIC_VECTOR;
s : OUT STD_LOGIC_VECTOR);
end component;
begin
nfa_accept_samples_generic_hw_add_17ns_17s_17_4_AddSubnS_5_U : component nfa_accept_samples_generic_hw_add_17ns_17s_17_4_AddSubnS_5
port map (
clk => clk,
reset => reset,
ce => ce,
a => din0,
b => din1,
s => dout);
end architecture;
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2013.4
-- Copyright (C) 2013 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity nfa_accept_samples_generic_hw_add_17ns_17s_17_4_AddSubnS_5 is
port (
clk: in std_logic;
reset: in std_logic;
ce: in std_logic;
a: in std_logic_vector(16 downto 0);
b: in std_logic_vector(16 downto 0);
s: out std_logic_vector(16 downto 0));
end entity;
architecture behav of nfa_accept_samples_generic_hw_add_17ns_17s_17_4_AddSubnS_5 is
component nfa_accept_samples_generic_hw_add_17ns_17s_17_4_AddSubnS_5_fadder is
port (
faa : IN STD_LOGIC_VECTOR (5-1 downto 0);
fab : IN STD_LOGIC_VECTOR (5-1 downto 0);
facin : IN STD_LOGIC_VECTOR (0 downto 0);
fas : OUT STD_LOGIC_VECTOR (5-1 downto 0);
facout : OUT STD_LOGIC_VECTOR (0 downto 0));
end component;
component nfa_accept_samples_generic_hw_add_17ns_17s_17_4_AddSubnS_5_fadder_f is
port (
faa : IN STD_LOGIC_VECTOR (2-1 downto 0);
fab : IN STD_LOGIC_VECTOR (2-1 downto 0);
facin : IN STD_LOGIC_VECTOR (0 downto 0);
fas : OUT STD_LOGIC_VECTOR (2-1 downto 0);
facout : OUT STD_LOGIC_VECTOR (0 downto 0));
end component;
-- ---- register and wire type variables list here ----
-- wire for the primary inputs
signal a_reg : std_logic_vector(16 downto 0);
signal b_reg : std_logic_vector(16 downto 0);
-- wires for each small adder
signal a0_cb : std_logic_vector(4 downto 0);
signal b0_cb : std_logic_vector(4 downto 0);
signal a1_cb : std_logic_vector(9 downto 5);
signal b1_cb : std_logic_vector(9 downto 5);
signal a2_cb : std_logic_vector(14 downto 10);
signal b2_cb : std_logic_vector(14 downto 10);
signal a3_cb : std_logic_vector(16 downto 15);
signal b3_cb : std_logic_vector(16 downto 15);
-- registers for input register array
type ramtypei0 is array (0 downto 0) of std_logic_vector(4 downto 0);
signal a1_cb_regi1 : ramtypei0;
signal b1_cb_regi1 : ramtypei0;
type ramtypei1 is array (1 downto 0) of std_logic_vector(4 downto 0);
signal a2_cb_regi2 : ramtypei1;
signal b2_cb_regi2 : ramtypei1;
type ramtypei2 is array (2 downto 0) of std_logic_vector(1 downto 0);
signal a3_cb_regi3 : ramtypei2;
signal b3_cb_regi3 : ramtypei2;
-- wires for each full adder sum
signal fas : std_logic_vector(16 downto 0);
-- wires and register for carry out bit
signal faccout_ini : std_logic_vector (0 downto 0);
signal faccout0_co0 : std_logic_vector (0 downto 0);
signal faccout1_co1 : std_logic_vector (0 downto 0);
signal faccout2_co2 : std_logic_vector (0 downto 0);
signal faccout3_co3 : std_logic_vector (0 downto 0);
signal faccout0_co0_reg : std_logic_vector (0 downto 0);
signal faccout1_co1_reg : std_logic_vector (0 downto 0);
signal faccout2_co2_reg : std_logic_vector (0 downto 0);
-- registers for output register array
type ramtypeo2 is array (2 downto 0) of std_logic_vector(4 downto 0);
signal s0_ca_rego0 : ramtypeo2;
type ramtypeo1 is array (1 downto 0) of std_logic_vector(4 downto 0);
signal s1_ca_rego1 : ramtypeo1;
type ramtypeo0 is array (0 downto 0) of std_logic_vector(4 downto 0);
signal s2_ca_rego2 : ramtypeo0;
-- wire for the temporary output
signal s_tmp : std_logic_vector(16 downto 0);
-- ---- RTL code for assignment statements/always blocks/module instantiations here ----
begin
a_reg <= a;
b_reg <= b;
-- small adder input assigments
a0_cb <= a_reg(4 downto 0);
b0_cb <= b_reg(4 downto 0);
a1_cb <= a_reg(9 downto 5);
b1_cb <= b_reg(9 downto 5);
a2_cb <= a_reg(14 downto 10);
b2_cb <= b_reg(14 downto 10);
a3_cb <= a_reg(16 downto 15);
b3_cb <= b_reg(16 downto 15);
-- input register array
process (clk)
begin
if (clk'event and clk='1') then
if (ce='1') then
a1_cb_regi1 (0) <= a1_cb;
b1_cb_regi1 (0) <= b1_cb;
a2_cb_regi2 (0) <= a2_cb;
b2_cb_regi2 (0) <= b2_cb;
a3_cb_regi3 (0) <= a3_cb;
b3_cb_regi3 (0) <= b3_cb;
a2_cb_regi2 (1) <= a2_cb_regi2 (0);
b2_cb_regi2 (1) <= b2_cb_regi2 (0);
a3_cb_regi3 (1) <= a3_cb_regi3 (0);
b3_cb_regi3 (1) <= b3_cb_regi3 (0);
a3_cb_regi3 (2) <= a3_cb_regi3 (1);
b3_cb_regi3 (2) <= b3_cb_regi3 (1);
end if;
end if;
end process;
-- carry out bit processing
process (clk)
begin
if (clk'event and clk='1') then
if (ce='1') then
faccout0_co0_reg <= faccout0_co0;
faccout1_co1_reg <= faccout1_co1;
faccout2_co2_reg <= faccout2_co2;
end if;
end if;
end process;
-- small adder generation
u0 : nfa_accept_samples_generic_hw_add_17ns_17s_17_4_AddSubnS_5_fadder
port map
(faa => a0_cb,
fab => b0_cb,
facin => faccout_ini,
fas => fas(4 downto 0),
facout => faccout0_co0);
u1 : nfa_accept_samples_generic_hw_add_17ns_17s_17_4_AddSubnS_5_fadder
port map
(faa => a1_cb_regi1(0),
fab => b1_cb_regi1(0),
facin => faccout0_co0_reg,
fas => fas(9 downto 5),
facout => faccout1_co1);
u2 : nfa_accept_samples_generic_hw_add_17ns_17s_17_4_AddSubnS_5_fadder
port map
(faa => a2_cb_regi2(1),
fab => b2_cb_regi2(1),
facin => faccout1_co1_reg,
fas => fas(14 downto 10),
facout => faccout2_co2);
u3 : nfa_accept_samples_generic_hw_add_17ns_17s_17_4_AddSubnS_5_fadder_f
port map
(faa => a3_cb_regi3(2),
fab => b3_cb_regi3(2),
facin => faccout2_co2_reg,
fas => fas(16 downto 15),
facout => faccout3_co3);
faccout_ini <= "0";
-- output register array
process (clk)
begin
if (clk'event and clk='1') then
if (ce='1') then
s0_ca_rego0 (0) <= fas(4 downto 0);
s1_ca_rego1 (0) <= fas(9 downto 5);
s2_ca_rego2 (0) <= fas(14 downto 10);
s0_ca_rego0 (1) <= s0_ca_rego0 (0);
s0_ca_rego0 (2) <= s0_ca_rego0 (1);
s1_ca_rego1 (1) <= s1_ca_rego1 (0);
end if;
end if;
end process;
-- get the s_tmp, assign it to the primary output
s_tmp(4 downto 0) <= s0_ca_rego0(2);
s_tmp(9 downto 5) <= s1_ca_rego1(1);
s_tmp(14 downto 10) <= s2_ca_rego2(0);
s_tmp(16 downto 15) <= fas(16 downto 15);
s <= s_tmp;
end architecture;
-- short adder
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity nfa_accept_samples_generic_hw_add_17ns_17s_17_4_AddSubnS_5_fadder is
generic(N : natural :=5);
port (
faa : IN STD_LOGIC_VECTOR (N-1 downto 0);
fab : IN STD_LOGIC_VECTOR (N-1 downto 0);
facin : IN STD_LOGIC_VECTOR (0 downto 0);
fas : OUT STD_LOGIC_VECTOR (N-1 downto 0);
facout : OUT STD_LOGIC_VECTOR (0 downto 0));
end;
architecture behav of nfa_accept_samples_generic_hw_add_17ns_17s_17_4_AddSubnS_5_fadder is
signal tmp : STD_LOGIC_VECTOR (N downto 0);
begin
tmp <= std_logic_vector(unsigned(std_logic_vector(unsigned(std_logic_vector(resize(unsigned(faa),N+1))) + unsigned(fab))) + unsigned(facin));
fas <= tmp(N-1 downto 0 );
facout <= tmp(N downto N);
end behav;
-- the final stage short adder
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity nfa_accept_samples_generic_hw_add_17ns_17s_17_4_AddSubnS_5_fadder_f is
generic(N : natural :=2);
port (
faa : IN STD_LOGIC_VECTOR (N-1 downto 0);
fab : IN STD_LOGIC_VECTOR (N-1 downto 0);
facin : IN STD_LOGIC_VECTOR (0 downto 0);
fas : OUT STD_LOGIC_VECTOR (N-1 downto 0);
facout : OUT STD_LOGIC_VECTOR (0 downto 0));
end;
architecture behav of nfa_accept_samples_generic_hw_add_17ns_17s_17_4_AddSubnS_5_fadder_f is
signal tmp : STD_LOGIC_VECTOR (N downto 0);
begin
tmp <= std_logic_vector(unsigned(std_logic_vector(unsigned(std_logic_vector(resize(unsigned(faa),N+1))) + unsigned(fab))) + unsigned(facin));
fas <= tmp(N-1 downto 0 );
facout <= tmp(N downto N);
end behav;
Library IEEE;
use IEEE.std_logic_1164.all;
entity nfa_accept_samples_generic_hw_add_17ns_17s_17_4 is
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
ce : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR(din0_WIDTH - 1 DOWNTO 0);
din1 : IN STD_LOGIC_VECTOR(din1_WIDTH - 1 DOWNTO 0);
dout : OUT STD_LOGIC_VECTOR(dout_WIDTH - 1 DOWNTO 0));
end entity;
architecture arch of nfa_accept_samples_generic_hw_add_17ns_17s_17_4 is
component nfa_accept_samples_generic_hw_add_17ns_17s_17_4_AddSubnS_5 is
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
ce : IN STD_LOGIC;
a : IN STD_LOGIC_VECTOR;
b : IN STD_LOGIC_VECTOR;
s : OUT STD_LOGIC_VECTOR);
end component;
begin
nfa_accept_samples_generic_hw_add_17ns_17s_17_4_AddSubnS_5_U : component nfa_accept_samples_generic_hw_add_17ns_17s_17_4_AddSubnS_5
port map (
clk => clk,
reset => reset,
ce => ce,
a => din0,
b => din1,
s => dout);
end architecture;
|
library verilog;
use verilog.vl_types.all;
entity clk_gen is
port(
clk_ref : in vl_logic;
reset_sw : in vl_logic;
clk : out vl_logic;
clk_n : out vl_logic;
chip_reset : out vl_logic
);
end clk_gen;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- code from book
entity control_unit is
generic ( Tpd_clk_out, Tpw_clk : delay_length;
debug : boolean := false );
port ( clk : in bit;
ready : in bit;
control1, control2 : out bit );
end entity control_unit;
-- end code from book
architecture test of control_unit is
begin
end architecture test;
|
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.