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--
-- 65xx compatible microprocessor core
--
-- Version : 0246
--
-- Copyright (c) 2002 Daniel Wallner ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t65/
--
-- Limitations :
--
-- File history :
--
library IEEE;
use IEEE.std_logic_1164.all;
package T65_Pack is
constant Flag_C : integer := 0;
constant Flag_Z : integer := 1;
constant Flag_I : integer := 2;
constant Flag_D : integer := 3;
constant Flag_B : integer := 4;
constant Flag_1 : integer := 5;
constant Flag_V : integer := 6;
constant Flag_N : integer := 7;
component T65
port(
Mode : in std_logic_vector(1 downto 0); -- "00" => 6502, "01" => 65C02, "10" => 65816
Res_n : in std_logic;
Clk : in std_logic;
Rdy : in std_logic;
Abort_n : in std_logic;
IRQ_n : in std_logic;
NMI_n : in std_logic;
SO_n : in std_logic;
R_W_n : out std_logic;
Sync : out std_logic;
EF : out std_logic;
MF : out std_logic;
XF : out std_logic;
ML_n : out std_logic;
VP_n : out std_logic;
VDA : out std_logic;
VPA : out std_logic;
A : out std_logic_vector(23 downto 0);
DI : in std_logic_vector(7 downto 0);
DO : out std_logic_vector(7 downto 0)
);
end component;
component T65_MCode
port(
Mode : in std_logic_vector(1 downto 0); -- "00" => 6502, "01" => 65C02, "10" => 65816
IR : in std_logic_vector(7 downto 0);
MCycle : in std_logic_vector(2 downto 0);
P : in std_logic_vector(7 downto 0);
LCycle : out std_logic_vector(2 downto 0);
ALU_Op : out std_logic_vector(3 downto 0);
Set_BusA_To : out std_logic_vector(2 downto 0); -- DI,A,X,Y,S,P
Set_Addr_To : out std_logic_vector(1 downto 0); -- PC Adder,S,AD,BA
Write_Data : out std_logic_vector(2 downto 0); -- DL,A,X,Y,S,P,PCL,PCH
Jump : out std_logic_vector(1 downto 0); -- PC,++,DIDL,Rel
BAAdd : out std_logic_vector(1 downto 0); -- None,DB Inc,BA Add,BA Adj
BreakAtNA : out std_logic;
ADAdd : out std_logic;
PCAdd : out std_logic;
Inc_S : out std_logic;
Dec_S : out std_logic;
LDA : out std_logic;
LDP : out std_logic;
LDX : out std_logic;
LDY : out std_logic;
LDS : out std_logic;
LDDI : out std_logic;
LDALU : out std_logic;
LDAD : out std_logic;
LDBAL : out std_logic;
LDBAH : out std_logic;
SaveP : out std_logic;
Write : out std_logic
);
end component;
component T65_ALU
port(
Mode : in std_logic_vector(1 downto 0); -- "00" => 6502, "01" => 65C02, "10" => 65C816
Op : in std_logic_vector(3 downto 0);
BusA : in std_logic_vector(7 downto 0);
BusB : in std_logic_vector(7 downto 0);
P_In : in std_logic_vector(7 downto 0);
P_Out : out std_logic_vector(7 downto 0);
Q : out std_logic_vector(7 downto 0)
);
end component;
end;
|
library ieee;
use ieee.std_logic_1164.all;
entity cmp_962 is
port (
ne : out std_logic;
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0)
);
end cmp_962;
architecture augh of cmp_962 is
signal tmp : std_logic;
begin
-- Compute the result
tmp <=
'0' when in1 /= in0 else
'1';
-- Set the outputs
ne <= not(tmp);
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
entity cmp_962 is
port (
ne : out std_logic;
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0)
);
end cmp_962;
architecture augh of cmp_962 is
signal tmp : std_logic;
begin
-- Compute the result
tmp <=
'0' when in1 /= in0 else
'1';
-- Set the outputs
ne <= not(tmp);
end architecture;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_pkg.vhd
--
-- Description:
-- This is the demo testbench package file for fifo_generator_v8.4 core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
PACKAGE fg_tb_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME;
------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector;
------------------------
COMPONENT fg_tb_rng IS
GENERIC (WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_dverif IS
GENERIC(
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_USE_EMBEDDED_REG : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT(
RESET : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
PRC_RD_EN : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
RD_EN : OUT STD_LOGIC;
DOUT_CHK : OUT STD_LOGIC
);
END COMPONENT;
------------------------
COMPONENT fg_tb_pctrl IS
GENERIC(
AXI_CHANNEL : STRING := "NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT pcie_command_rec_fifo_top IS
PORT (
WR_CLK : IN std_logic;
RD_CLK : IN std_logic;
WR_DATA_COUNT : OUT std_logic_vector(9-1 DOWNTO 0);
RD_DATA_COUNT : OUT std_logic_vector(9-1 DOWNTO 0);
ALMOST_FULL : OUT std_logic;
ALMOST_EMPTY : OUT std_logic;
RST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(128-1 DOWNTO 0);
DOUT : OUT std_logic_vector(128-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
END COMPONENT;
------------------------
END fg_tb_pkg;
PACKAGE BODY fg_tb_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER IS
VARIABLE div : INTEGER;
BEGIN
div := data_value/divisor;
IF ( (data_value MOD divisor) /= 0) THEN
div := div+1;
END IF;
RETURN div;
END divroundup;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
VARIABLE retval : INTEGER := 0;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC IS
VARIABLE retval : STD_LOGIC := '0';
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME IS
VARIABLE retval : TIME := 0 ps;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
-------------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := 1;
BEGIN
IF (data_value <= 1) THEN
width := 1;
ELSE
WHILE (cnt < data_value) LOOP
width := width + 1;
cnt := cnt *2;
END LOOP;
END IF;
RETURN width;
END log2roundup;
------------------------------------------------------------------------------
-- hexstr_to_std_logic_vec
-- This function converts a hex string to a std_logic_vector
------------------------------------------------------------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector IS
VARIABLE result : std_logic_vector(size-1 DOWNTO 0) := (OTHERS => '0');
VARIABLE bin : std_logic_vector(3 DOWNTO 0);
VARIABLE index : integer := 0;
BEGIN
FOR i IN arg1'reverse_range LOOP
CASE arg1(i) IS
WHEN '0' => bin := (OTHERS => '0');
WHEN '1' => bin := (0 => '1', OTHERS => '0');
WHEN '2' => bin := (1 => '1', OTHERS => '0');
WHEN '3' => bin := (0 => '1', 1 => '1', OTHERS => '0');
WHEN '4' => bin := (2 => '1', OTHERS => '0');
WHEN '5' => bin := (0 => '1', 2 => '1', OTHERS => '0');
WHEN '6' => bin := (1 => '1', 2 => '1', OTHERS => '0');
WHEN '7' => bin := (3 => '0', OTHERS => '1');
WHEN '8' => bin := (3 => '1', OTHERS => '0');
WHEN '9' => bin := (0 => '1', 3 => '1', OTHERS => '0');
WHEN 'A' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'a' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'B' => bin := (2 => '0', OTHERS => '1');
WHEN 'b' => bin := (2 => '0', OTHERS => '1');
WHEN 'C' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'c' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'D' => bin := (1 => '0', OTHERS => '1');
WHEN 'd' => bin := (1 => '0', OTHERS => '1');
WHEN 'E' => bin := (0 => '0', OTHERS => '1');
WHEN 'e' => bin := (0 => '0', OTHERS => '1');
WHEN 'F' => bin := (OTHERS => '1');
WHEN 'f' => bin := (OTHERS => '1');
WHEN OTHERS =>
FOR j IN 0 TO 3 LOOP
bin(j) := 'X';
END LOOP;
END CASE;
FOR j IN 0 TO 3 LOOP
IF (index*4)+j < size THEN
result((index*4)+j) := bin(j);
END IF;
END LOOP;
index := index + 1;
END LOOP;
RETURN result;
END hexstr_to_std_logic_vec;
END fg_tb_pkg;
|
architecture rtl of fifo is
signal sig8 : record_type_3(
element1(7 downto 0),
element2(4 downto 0)(7 downto 0)
(
elementA(7 downto 0)
,
elementB(3 downto 0)),
element3(3 downto 0)(elementC(4 downto 1), elementD(1 downto 0)),
element5(
elementE
(3 downto
0)
(6
downto 0)
,
elementF(7 downto 0)),
element6(4 downto
0),
element7(7 downto 0));
signal sig9 : t_data_struct(data(7 downto 0));
signal sig9 : t_data_struct(
data(7 downto 0));
begin
end architecture rtl;
|
entity issue101 is
end entity;
architecture SIGN of issue101 is
signal TRIGGER, RESULT: integer := 0;
signal signal1: integer :=1;
signal signal2: integer :=2;
signal signal3: integer :=3;
begin
process (signal1, signal2, signal3)
begin
-- wait on TRIGGER;
signal1 <= signal2;
signal2 <= signal1 + signal3;
signal3 <= signal2;
RESULT <= signal1 + signal2 + signal3;
end process;
monitor:
process(RESULT)
begin
report "RESULT = " & integer'image(RESULT);
end process;
end SIGN;
|
----------------------------------------------------------------------
-- brdLexSwx (for SCS Kit)
----------------------------------------------------------------------
-- (c) 2016 by Anton Mause
--
-- board/kit dependency : LEDs & SW polarity
--
----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
----------------------------------------------------------------------
entity brdLexSwx is
port ( o_lex, o_pbx : out std_logic );
end brdLexSwx;
----------------------------------------------------------------------
architecture rtl of brdLexSwx is
begin
-- polarity of LED driver output
-- '0' = low idle, high active
-- '1' = high idle, low active
o_lex <= '0';
-- polarity of push button switch
-- '0' = low idle, high active (pressed)
-- '1' = high idle, low active (pressed)
o_pbx <= '0';
end rtl; |
----------------------------------------------------------------------------------
-- Company:
-- Engineer: Justin Nguyen
--
-- Create Date: 11:24:03 09/18/2017
-- Design Name:
-- Module Name: Mux4x1
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description: This is a generic 4x1 10 bit mux with 2 bit select.
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
--------------------------------------------------------------------------------
-----------------------------------------------------------------------
-----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Mux2x1_10 is
Port ( A : in STD_LOGIC_VECTOR (9 downto 0);
B : in STD_LOGIC_VECTOR (9 downto 0);
SEL : in STD_LOGIC;
X : out STD_LOGIC_VECTOR (9 downto 0));
end Mux2x1_10;
architecture Behavioral of Mux2x1_10 is
begin
with SEL select X <=
A when '0',
B when '1',
A when others;
end Behavioral;
|
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 3.9
-- \ \ Application : MIG
-- / / Filename : sim_tb_top.vhd
-- /___/ /\ Date Last Modified : $Date: 2011/06/02 07:16:58 $
-- \ \ / \ Date Created : Jul 03 2009
-- \___\/\___\
--
-- Device : Spartan-6
-- Design Name : DDR/DDR2/DDR3/LPDDR
-- Purpose : This is the simulation testbench which is used to verify the
-- design. The basic clocks and resets to the interface are
-- generated here. This also connects the memory interface to the
-- memory model.
--*****************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity sim_tb_top is
end entity sim_tb_top;
architecture arch of sim_tb_top is
-- ========================================================================== --
-- Parameters --
-- ========================================================================== --
constant DEBUG_EN : integer :=0;
constant C3_HW_TESTING : string := "FALSE";
function c3_sim_hw (val1:std_logic_vector( 31 downto 0); val2: std_logic_vector( 31 downto 0) ) return std_logic_vector is
begin
if (C3_HW_TESTING = "FALSE") then
return val1;
else
return val2;
end if;
end function;
constant C3_MEMCLK_PERIOD : integer := 3000;
constant C3_RST_ACT_LOW : integer := 0;
constant C3_INPUT_CLK_TYPE : string := "SINGLE_ENDED";
constant C3_CLK_PERIOD_NS : real := 3000.0 / 1000.0;
constant C3_TCYC_SYS : real := C3_CLK_PERIOD_NS/2.0;
constant C3_TCYC_SYS_DIV2 : time := C3_TCYC_SYS * 1 ns;
constant C3_NUM_DQ_PINS : integer := 16;
constant C3_MEM_ADDR_WIDTH : integer := 14;
constant C3_MEM_BANKADDR_WIDTH : integer := 3;
constant C3_MEM_ADDR_ORDER : string := "ROW_BANK_COLUMN";
constant C3_P0_MASK_SIZE : integer := 4;
constant C3_P0_DATA_PORT_SIZE : integer := 32;
constant C3_P1_MASK_SIZE : integer := 4;
constant C3_P1_DATA_PORT_SIZE : integer := 32;
constant C3_MEM_BURST_LEN : integer := 8;
constant C3_MEM_NUM_COL_BITS : integer := 10;
constant C3_SIMULATION : string := "TRUE";
constant C3_CALIB_SOFT_IP : string := "TRUE";
constant C3_p0_BEGIN_ADDRESS : std_logic_vector(31 downto 0) := c3_sim_hw (x"00000100", x"01000000");
constant C3_p0_DATA_MODE : std_logic_vector(3 downto 0) := "0010";
constant C3_p0_END_ADDRESS : std_logic_vector(31 downto 0) := c3_sim_hw (x"000002ff", x"02ffffff");
constant C3_p0_PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := c3_sim_hw (x"fffffc00", x"fc000000");
constant C3_p0_PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := c3_sim_hw (x"00000100", x"01000000");
constant C3_p1_BEGIN_ADDRESS : std_logic_vector(31 downto 0) := c3_sim_hw (x"00000300", x"03000000");
constant C3_p1_DATA_MODE : std_logic_vector(3 downto 0) := "0010";
constant C3_p1_END_ADDRESS : std_logic_vector(31 downto 0) := c3_sim_hw (x"000004ff", x"04ffffff");
constant C3_p1_PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := c3_sim_hw (x"fffff800", x"f8000000");
constant C3_p1_PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := c3_sim_hw (x"00000300", x"03000000");
-- ========================================================================== --
-- Component Declarations
-- ========================================================================== --
component ddr3_ctrl_spec_bank3_32b_32b is
generic
(
C3_P0_MASK_SIZE : integer;
C3_P0_DATA_PORT_SIZE : integer;
C3_P1_MASK_SIZE : integer;
C3_P1_DATA_PORT_SIZE : integer;
C3_MEMCLK_PERIOD : integer;
C3_RST_ACT_LOW : integer;
C3_INPUT_CLK_TYPE : string;
DEBUG_EN : integer;
C3_CALIB_SOFT_IP : string;
C3_SIMULATION : string;
C3_MEM_ADDR_ORDER : string;
C3_NUM_DQ_PINS : integer;
C3_MEM_ADDR_WIDTH : integer;
C3_MEM_BANKADDR_WIDTH : integer
);
port
(
mcb3_dram_dq : inout std_logic_vector(C3_NUM_DQ_PINS-1 downto 0);
mcb3_dram_a : out std_logic_vector(C3_MEM_ADDR_WIDTH-1 downto 0);
mcb3_dram_ba : out std_logic_vector(C3_MEM_BANKADDR_WIDTH-1 downto 0);
mcb3_dram_ras_n : out std_logic;
mcb3_dram_cas_n : out std_logic;
mcb3_dram_we_n : out std_logic;
mcb3_dram_odt : out std_logic;
mcb3_dram_cke : out std_logic;
mcb3_dram_dm : out std_logic;
mcb3_rzq : inout std_logic;
c3_sys_clk : in std_logic;
c3_sys_rst_i : in std_logic;
c3_calib_done : out std_logic;
c3_clk0 : out std_logic;
c3_rst0 : out std_logic;
mcb3_dram_dqs : inout std_logic;
mcb3_dram_dqs_n : inout std_logic;
mcb3_dram_ck : out std_logic;
mcb3_dram_udqs : inout std_logic;
mcb3_dram_udqs_n : inout std_logic;
mcb3_dram_udm : out std_logic;
mcb3_dram_ck_n : out std_logic;
mcb3_dram_reset_n : out std_logic; c3_p0_cmd_clk : in std_logic;
c3_p0_cmd_en : in std_logic;
c3_p0_cmd_instr : in std_logic_vector(2 downto 0);
c3_p0_cmd_bl : in std_logic_vector(5 downto 0);
c3_p0_cmd_byte_addr : in std_logic_vector(29 downto 0);
c3_p0_cmd_empty : out std_logic;
c3_p0_cmd_full : out std_logic;
c3_p0_wr_clk : in std_logic;
c3_p0_wr_en : in std_logic;
c3_p0_wr_mask : in std_logic_vector(C3_P0_MASK_SIZE - 1 downto 0);
c3_p0_wr_data : in std_logic_vector(C3_P0_DATA_PORT_SIZE - 1 downto 0);
c3_p0_wr_full : out std_logic;
c3_p0_wr_empty : out std_logic;
c3_p0_wr_count : out std_logic_vector(6 downto 0);
c3_p0_wr_underrun : out std_logic;
c3_p0_wr_error : out std_logic;
c3_p0_rd_clk : in std_logic;
c3_p0_rd_en : in std_logic;
c3_p0_rd_data : out std_logic_vector(C3_P0_DATA_PORT_SIZE - 1 downto 0);
c3_p0_rd_full : out std_logic;
c3_p0_rd_empty : out std_logic;
c3_p0_rd_count : out std_logic_vector(6 downto 0);
c3_p0_rd_overflow : out std_logic;
c3_p0_rd_error : out std_logic;
c3_p1_cmd_clk : in std_logic;
c3_p1_cmd_en : in std_logic;
c3_p1_cmd_instr : in std_logic_vector(2 downto 0);
c3_p1_cmd_bl : in std_logic_vector(5 downto 0);
c3_p1_cmd_byte_addr : in std_logic_vector(29 downto 0);
c3_p1_cmd_empty : out std_logic;
c3_p1_cmd_full : out std_logic;
c3_p1_wr_clk : in std_logic;
c3_p1_wr_en : in std_logic;
c3_p1_wr_mask : in std_logic_vector(C3_P1_MASK_SIZE - 1 downto 0);
c3_p1_wr_data : in std_logic_vector(C3_P1_DATA_PORT_SIZE - 1 downto 0);
c3_p1_wr_full : out std_logic;
c3_p1_wr_empty : out std_logic;
c3_p1_wr_count : out std_logic_vector(6 downto 0);
c3_p1_wr_underrun : out std_logic;
c3_p1_wr_error : out std_logic;
c3_p1_rd_clk : in std_logic;
c3_p1_rd_en : in std_logic;
c3_p1_rd_data : out std_logic_vector(C3_P1_DATA_PORT_SIZE - 1 downto 0);
c3_p1_rd_full : out std_logic;
c3_p1_rd_empty : out std_logic;
c3_p1_rd_count : out std_logic_vector(6 downto 0);
c3_p1_rd_overflow : out std_logic;
c3_p1_rd_error : out std_logic
);
end component;
component ddr3_model_c3 is
port (
ck : in std_logic;
ck_n : in std_logic;
cke : in std_logic;
cs_n : in std_logic;
ras_n : in std_logic;
cas_n : in std_logic;
we_n : in std_logic;
dm_tdqs : inout std_logic_vector((C3_NUM_DQ_PINS/16) downto 0);
ba : in std_logic_vector((C3_MEM_BANKADDR_WIDTH - 1) downto 0);
addr : in std_logic_vector((C3_MEM_ADDR_WIDTH - 1) downto 0);
dq : inout std_logic_vector((C3_NUM_DQ_PINS - 1) downto 0);
dqs : inout std_logic_vector((C3_NUM_DQ_PINS/16) downto 0);
dqs_n : inout std_logic_vector((C3_NUM_DQ_PINS/16) downto 0);
tdqs_n : out std_logic_vector((C3_NUM_DQ_PINS/16) downto 0);
odt : in std_logic;
rst_n : in std_logic
);
end component;
component memc3_tb_top is
generic
(
C_P0_MASK_SIZE : integer := 4;
C_P0_DATA_PORT_SIZE : integer := 32;
C_P1_MASK_SIZE : integer := 4;
C_P1_DATA_PORT_SIZE : integer := 32;
C_MEM_BURST_LEN : integer := 8;
C_MEM_NUM_COL_BITS : integer := 11;
C_NUM_DQ_PINS : integer := 8;
C_p0_BEGIN_ADDRESS : std_logic_vector(31 downto 0) := X"00000100";
C_p0_DATA_MODE : std_logic_vector(3 downto 0) := "0010";
C_p0_END_ADDRESS : std_logic_vector(31 downto 0) := X"000002ff";
C_p0_PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := X"fffffc00";
C_p0_PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := X"00000100";
C_p1_BEGIN_ADDRESS : std_logic_vector(31 downto 0) := X"00000300";
C_p1_DATA_MODE : std_logic_vector(3 downto 0) := "0010";
C_p1_END_ADDRESS : std_logic_vector(31 downto 0) := X"000004ff";
C_p1_PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := X"fffff800";
C_p1_PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := X"00000300"
);
port
(
clk0 : in std_logic;
rst0 : in std_logic;
calib_done : in std_logic;
p0_mcb_cmd_en_o : out std_logic;
p0_mcb_cmd_instr_o : out std_logic_vector(2 downto 0);
p0_mcb_cmd_bl_o : out std_logic_vector(5 downto 0);
p0_mcb_cmd_addr_o : out std_logic_vector(29 downto 0);
p0_mcb_cmd_full_i : in std_logic;
p0_mcb_wr_en_o : out std_logic;
p0_mcb_wr_mask_o : out std_logic_vector(C_P0_MASK_SIZE - 1 downto 0);
p0_mcb_wr_data_o : out std_logic_vector(C_P0_DATA_PORT_SIZE - 1 downto 0);
p0_mcb_wr_full_i : in std_logic;
p0_mcb_wr_fifo_counts : in std_logic_vector(6 downto 0);
p0_mcb_rd_en_o : out std_logic;
p0_mcb_rd_data_i : in std_logic_vector(C_P0_DATA_PORT_SIZE - 1 downto 0);
p0_mcb_rd_empty_i : in std_logic;
p0_mcb_rd_fifo_counts : in std_logic_vector(6 downto 0);
p1_mcb_cmd_en_o : out std_logic;
p1_mcb_cmd_instr_o : out std_logic_vector(2 downto 0);
p1_mcb_cmd_bl_o : out std_logic_vector(5 downto 0);
p1_mcb_cmd_addr_o : out std_logic_vector(29 downto 0);
p1_mcb_cmd_full_i : in std_logic;
p1_mcb_wr_en_o : out std_logic;
p1_mcb_wr_mask_o : out std_logic_vector(C_P1_MASK_SIZE - 1 downto 0);
p1_mcb_wr_data_o : out std_logic_vector(C_P1_DATA_PORT_SIZE - 1 downto 0);
p1_mcb_wr_full_i : in std_logic;
p1_mcb_wr_fifo_counts : in std_logic_vector(6 downto 0);
p1_mcb_rd_en_o : out std_logic;
p1_mcb_rd_data_i : in std_logic_vector(C_P1_DATA_PORT_SIZE - 1 downto 0);
p1_mcb_rd_empty_i : in std_logic;
p1_mcb_rd_fifo_counts : in std_logic_vector(6 downto 0);
vio_modify_enable : in std_logic;
vio_data_mode_value : in std_logic_vector(2 downto 0);
vio_addr_mode_value : in std_logic_vector(2 downto 0);
cmp_error : out std_logic;
error : out std_logic;
error_status : out std_logic_vector(127 downto 0)
);
end component;
-- ========================================================================== --
-- Signal Declarations --
-- ========================================================================== --
-- Clocks
-- Clocks
signal c3_sys_clk : std_logic := '0';
signal c3_sys_clk_p : std_logic;
signal c3_sys_clk_n : std_logic;
-- System Reset
signal c3_sys_rst : std_logic := '0';
signal c3_sys_rst_i : std_logic;
-- Design-Top Port Map
signal c3_error : std_logic;
signal c3_calib_done : std_logic;
signal c3_error_status : std_logic_vector(127 downto 0);
signal mcb3_dram_a : std_logic_vector(C3_MEM_ADDR_WIDTH-1 downto 0);
signal mcb3_dram_ba : std_logic_vector(C3_MEM_BANKADDR_WIDTH-1 downto 0);
signal mcb3_dram_ck : std_logic;
signal mcb3_dram_ck_n : std_logic;
signal mcb3_dram_dq : std_logic_vector(C3_NUM_DQ_PINS-1 downto 0);
signal mcb3_dram_dqs : std_logic;
signal mcb3_dram_dqs_n : std_logic;
signal mcb3_dram_dm : std_logic;
signal mcb3_dram_ras_n : std_logic;
signal mcb3_dram_cas_n : std_logic;
signal mcb3_dram_we_n : std_logic;
signal mcb3_dram_cke : std_logic;
signal mcb3_dram_odt : std_logic;
signal mcb3_dram_reset_n : std_logic;
signal mcb3_dram_udqs : std_logic;
signal mcb3_dram_udqs_n : std_logic;
signal mcb3_dram_dqs_vector : std_logic_vector(1 downto 0);
signal mcb3_dram_dqs_n_vector : std_logic_vector(1 downto 0);
signal mcb3_dram_udm :std_logic; -- for X16 parts
signal mcb3_dram_dm_vector : std_logic_vector(1 downto 0);
-- User design Sim
signal c3_clk0 : std_logic;
signal c3_rst0 : std_logic;
signal c3_cmp_error : std_logic;
signal c3_vio_modify_enable : std_logic;
signal c3_vio_data_mode_value : std_logic_vector(2 downto 0);
signal c3_vio_addr_mode_value : std_logic_vector(2 downto 0);
signal mcb3_command : std_logic_vector(2 downto 0);
signal mcb3_enable1 : std_logic;
signal mcb3_enable2 : std_logic;
signal c3_p0_cmd_en : std_logic;
signal c3_p0_cmd_instr : std_logic_vector(2 downto 0);
signal c3_p0_cmd_bl : std_logic_vector(5 downto 0);
signal c3_p0_cmd_byte_addr : std_logic_vector(29 downto 0);
signal c3_p0_cmd_empty : std_logic;
signal c3_p0_cmd_full : std_logic;
signal c3_p0_wr_en : std_logic;
signal c3_p0_wr_mask : std_logic_vector(C3_P0_MASK_SIZE - 1 downto 0);
signal c3_p0_wr_data : std_logic_vector(C3_P0_DATA_PORT_SIZE - 1 downto 0);
signal c3_p0_wr_full : std_logic;
signal c3_p0_wr_empty : std_logic;
signal c3_p0_wr_count : std_logic_vector(6 downto 0);
signal c3_p0_wr_underrun : std_logic;
signal c3_p0_wr_error : std_logic;
signal c3_p0_rd_en : std_logic;
signal c3_p0_rd_data : std_logic_vector(C3_P0_DATA_PORT_SIZE - 1 downto 0);
signal c3_p0_rd_full : std_logic;
signal c3_p0_rd_empty : std_logic;
signal c3_p0_rd_count : std_logic_vector(6 downto 0);
signal c3_p0_rd_overflow : std_logic;
signal c3_p0_rd_error : std_logic;
signal c3_p1_cmd_en : std_logic;
signal c3_p1_cmd_instr : std_logic_vector(2 downto 0);
signal c3_p1_cmd_bl : std_logic_vector(5 downto 0);
signal c3_p1_cmd_byte_addr : std_logic_vector(29 downto 0);
signal c3_p1_cmd_empty : std_logic;
signal c3_p1_cmd_full : std_logic;
signal c3_p1_wr_en : std_logic;
signal c3_p1_wr_mask : std_logic_vector(C3_P1_MASK_SIZE - 1 downto 0);
signal c3_p1_wr_data : std_logic_vector(C3_P1_DATA_PORT_SIZE - 1 downto 0);
signal c3_p1_wr_full : std_logic;
signal c3_p1_wr_empty : std_logic;
signal c3_p1_wr_count : std_logic_vector(6 downto 0);
signal c3_p1_wr_underrun : std_logic;
signal c3_p1_wr_error : std_logic;
signal c3_p1_rd_en : std_logic;
signal c3_p1_rd_data : std_logic_vector(C3_P1_DATA_PORT_SIZE - 1 downto 0);
signal c3_p1_rd_full : std_logic;
signal c3_p1_rd_empty : std_logic;
signal c3_p1_rd_count : std_logic_vector(6 downto 0);
signal c3_p1_rd_overflow : std_logic;
signal c3_p1_rd_error : std_logic;
signal c3_selfrefresh_enter : std_logic;
signal c3_selfrefresh_mode : std_logic;
signal rzq3 : std_logic;
signal calib_done : std_logic;
signal error : std_logic;
function vector (asi:std_logic) return std_logic_vector is
variable v : std_logic_vector(0 downto 0) ;
begin
v(0) := asi;
return(v);
end function vector;
begin
-- ========================================================================== --
-- Clocks Generation --
-- ========================================================================== --
process
begin
c3_sys_clk <= not c3_sys_clk;
wait for (C3_TCYC_SYS_DIV2);
end process;
c3_sys_clk_p <= c3_sys_clk;
c3_sys_clk_n <= not c3_sys_clk;
-- ========================================================================== --
-- Reset Generation --
-- ========================================================================== --
process
begin
c3_sys_rst <= '0';
wait for 200 ns;
c3_sys_rst <= '1';
wait;
end process;
c3_sys_rst_i <= c3_sys_rst when (C3_RST_ACT_LOW = 1) else (not c3_sys_rst);
error <= c3_error;
calib_done <= c3_calib_done;
rzq_pulldown3 : PULLDOWN port map(O => rzq3);
-- ========================================================================== --
-- DESIGN TOP INSTANTIATION --
-- ========================================================================== --
design_top : ddr3_ctrl_spec_bank3_32b_32b generic map
(
C3_P0_MASK_SIZE => C3_P0_MASK_SIZE,
C3_P0_DATA_PORT_SIZE => C3_P0_DATA_PORT_SIZE,
C3_P1_MASK_SIZE => C3_P1_MASK_SIZE,
C3_P1_DATA_PORT_SIZE => C3_P1_DATA_PORT_SIZE,
C3_MEMCLK_PERIOD => C3_MEMCLK_PERIOD,
C3_RST_ACT_LOW => C3_RST_ACT_LOW,
C3_INPUT_CLK_TYPE => C3_INPUT_CLK_TYPE,
DEBUG_EN => DEBUG_EN,
C3_MEM_ADDR_ORDER => C3_MEM_ADDR_ORDER,
C3_NUM_DQ_PINS => C3_NUM_DQ_PINS,
C3_MEM_ADDR_WIDTH => C3_MEM_ADDR_WIDTH,
C3_MEM_BANKADDR_WIDTH => C3_MEM_BANKADDR_WIDTH,
C3_SIMULATION => C3_SIMULATION,
C3_CALIB_SOFT_IP => C3_CALIB_SOFT_IP
)
port map (
c3_sys_clk => c3_sys_clk,
c3_sys_rst_i => c3_sys_rst_i,
mcb3_dram_dq => mcb3_dram_dq,
mcb3_dram_a => mcb3_dram_a,
mcb3_dram_ba => mcb3_dram_ba,
mcb3_dram_ras_n => mcb3_dram_ras_n,
mcb3_dram_cas_n => mcb3_dram_cas_n,
mcb3_dram_we_n => mcb3_dram_we_n,
mcb3_dram_odt => mcb3_dram_odt,
mcb3_dram_cke => mcb3_dram_cke,
mcb3_dram_ck => mcb3_dram_ck,
mcb3_dram_ck_n => mcb3_dram_ck_n,
mcb3_dram_dqs => mcb3_dram_dqs,
mcb3_dram_dqs_n => mcb3_dram_dqs_n,
mcb3_dram_reset_n => mcb3_dram_reset_n,
mcb3_dram_udqs => mcb3_dram_udqs, -- for X16 parts
mcb3_dram_udqs_n => mcb3_dram_udqs_n, -- for X16 parts
mcb3_dram_udm => mcb3_dram_udm, -- for X16 parts
mcb3_dram_dm => mcb3_dram_dm,
c3_clk0 => c3_clk0,
c3_rst0 => c3_rst0,
c3_calib_done => c3_calib_done,
mcb3_rzq => rzq3,
c3_p0_cmd_clk => (c3_clk0),
c3_p0_cmd_en => c3_p0_cmd_en,
c3_p0_cmd_instr => c3_p0_cmd_instr,
c3_p0_cmd_bl => c3_p0_cmd_bl,
c3_p0_cmd_byte_addr => c3_p0_cmd_byte_addr,
c3_p0_cmd_empty => c3_p0_cmd_empty,
c3_p0_cmd_full => c3_p0_cmd_full,
c3_p0_wr_clk => (c3_clk0),
c3_p0_wr_en => c3_p0_wr_en,
c3_p0_wr_mask => c3_p0_wr_mask,
c3_p0_wr_data => c3_p0_wr_data,
c3_p0_wr_full => c3_p0_wr_full,
c3_p0_wr_empty => c3_p0_wr_empty,
c3_p0_wr_count => c3_p0_wr_count,
c3_p0_wr_underrun => c3_p0_wr_underrun,
c3_p0_wr_error => c3_p0_wr_error,
c3_p0_rd_clk => (c3_clk0),
c3_p0_rd_en => c3_p0_rd_en,
c3_p0_rd_data => c3_p0_rd_data,
c3_p0_rd_full => c3_p0_rd_full,
c3_p0_rd_empty => c3_p0_rd_empty,
c3_p0_rd_count => c3_p0_rd_count,
c3_p0_rd_overflow => c3_p0_rd_overflow,
c3_p0_rd_error => c3_p0_rd_error,
c3_p1_cmd_clk => (c3_clk0),
c3_p1_cmd_en => c3_p1_cmd_en,
c3_p1_cmd_instr => c3_p1_cmd_instr,
c3_p1_cmd_bl => c3_p1_cmd_bl,
c3_p1_cmd_byte_addr => c3_p1_cmd_byte_addr,
c3_p1_cmd_empty => c3_p1_cmd_empty,
c3_p1_cmd_full => c3_p1_cmd_full,
c3_p1_wr_clk => (c3_clk0),
c3_p1_wr_en => c3_p1_wr_en,
c3_p1_wr_mask => c3_p1_wr_mask,
c3_p1_wr_data => c3_p1_wr_data,
c3_p1_wr_full => c3_p1_wr_full,
c3_p1_wr_empty => c3_p1_wr_empty,
c3_p1_wr_count => c3_p1_wr_count,
c3_p1_wr_underrun => c3_p1_wr_underrun,
c3_p1_wr_error => c3_p1_wr_error,
c3_p1_rd_clk => (c3_clk0),
c3_p1_rd_en => c3_p1_rd_en,
c3_p1_rd_data => c3_p1_rd_data,
c3_p1_rd_full => c3_p1_rd_full,
c3_p1_rd_empty => c3_p1_rd_empty,
c3_p1_rd_count => c3_p1_rd_count,
c3_p1_rd_overflow => c3_p1_rd_overflow,
c3_p1_rd_error => c3_p1_rd_error
);
-- user interface
memc3_tb_top_inst : memc3_tb_top generic map
(
C_NUM_DQ_PINS => C3_NUM_DQ_PINS,
C_MEM_BURST_LEN => C3_MEM_BURST_LEN,
C_MEM_NUM_COL_BITS => C3_MEM_NUM_COL_BITS,
C_P0_MASK_SIZE => C3_P0_MASK_SIZE,
C_P0_DATA_PORT_SIZE => C3_P0_DATA_PORT_SIZE,
C_P1_MASK_SIZE => C3_P1_MASK_SIZE,
C_P1_DATA_PORT_SIZE => C3_P1_DATA_PORT_SIZE,
C_p0_BEGIN_ADDRESS => C3_p0_BEGIN_ADDRESS,
C_p0_DATA_MODE => C3_p0_DATA_MODE,
C_p0_END_ADDRESS => C3_p0_END_ADDRESS,
C_p0_PRBS_EADDR_MASK_POS => C3_p0_PRBS_EADDR_MASK_POS,
C_p0_PRBS_SADDR_MASK_POS => C3_p0_PRBS_SADDR_MASK_POS,
C_p1_BEGIN_ADDRESS => C3_p1_BEGIN_ADDRESS,
C_p1_DATA_MODE => C3_p1_DATA_MODE,
C_p1_END_ADDRESS => C3_p1_END_ADDRESS,
C_p1_PRBS_EADDR_MASK_POS => C3_p1_PRBS_EADDR_MASK_POS,
C_p1_PRBS_SADDR_MASK_POS => C3_p1_PRBS_SADDR_MASK_POS
)
port map
(
clk0 => c3_clk0,
rst0 => c3_rst0,
calib_done => c3_calib_done,
cmp_error => c3_cmp_error,
error => c3_error,
error_status => c3_error_status,
vio_modify_enable => c3_vio_modify_enable,
vio_data_mode_value => c3_vio_data_mode_value,
vio_addr_mode_value => c3_vio_addr_mode_value,
p0_mcb_cmd_en_o => c3_p0_cmd_en,
p0_mcb_cmd_instr_o => c3_p0_cmd_instr,
p0_mcb_cmd_bl_o => c3_p0_cmd_bl,
p0_mcb_cmd_addr_o => c3_p0_cmd_byte_addr,
p0_mcb_cmd_full_i => c3_p0_cmd_full,
p0_mcb_wr_en_o => c3_p0_wr_en,
p0_mcb_wr_mask_o => c3_p0_wr_mask,
p0_mcb_wr_data_o => c3_p0_wr_data,
p0_mcb_wr_full_i => c3_p0_wr_full,
p0_mcb_wr_fifo_counts => c3_p0_wr_count,
p0_mcb_rd_en_o => c3_p0_rd_en,
p0_mcb_rd_data_i => c3_p0_rd_data,
p0_mcb_rd_empty_i => c3_p0_rd_empty,
p0_mcb_rd_fifo_counts => c3_p0_rd_count,
p1_mcb_cmd_en_o => c3_p1_cmd_en,
p1_mcb_cmd_instr_o => c3_p1_cmd_instr,
p1_mcb_cmd_bl_o => c3_p1_cmd_bl,
p1_mcb_cmd_addr_o => c3_p1_cmd_byte_addr,
p1_mcb_cmd_full_i => c3_p1_cmd_full,
p1_mcb_wr_en_o => c3_p1_wr_en,
p1_mcb_wr_mask_o => c3_p1_wr_mask,
p1_mcb_wr_data_o => c3_p1_wr_data,
p1_mcb_wr_full_i => c3_p1_wr_full,
p1_mcb_wr_fifo_counts => c3_p1_wr_count,
p1_mcb_rd_en_o => c3_p1_rd_en,
p1_mcb_rd_data_i => c3_p1_rd_data,
p1_mcb_rd_empty_i => c3_p1_rd_empty,
p1_mcb_rd_fifo_counts => c3_p1_rd_count
);
-- ========================================================================== --
-- Memory model instances --
-- ========================================================================== --
mcb3_command <= (mcb3_dram_ras_n & mcb3_dram_cas_n & mcb3_dram_we_n);
process(mcb3_dram_ck)
begin
if (rising_edge(mcb3_dram_ck)) then
if (c3_sys_rst = '0') then
mcb3_enable1 <= '0';
mcb3_enable2 <= '0';
elsif (mcb3_command = "100") then
mcb3_enable2 <= '0';
elsif (mcb3_command = "101") then
mcb3_enable2 <= '1';
else
mcb3_enable2 <= mcb3_enable2;
end if;
mcb3_enable1 <= mcb3_enable2;
end if;
end process;
-----------------------------------------------------------------------------
--read
-----------------------------------------------------------------------------
mcb3_dram_dqs_vector(1 downto 0) <= (mcb3_dram_udqs & mcb3_dram_dqs)
when (mcb3_enable2 = '0' and mcb3_enable1 = '0')
else "ZZ";
mcb3_dram_dqs_n_vector(1 downto 0) <= (mcb3_dram_udqs_n & mcb3_dram_dqs_n)
when (mcb3_enable2 = '0' and mcb3_enable1 = '0')
else "ZZ";
-----------------------------------------------------------------------------
--write
-----------------------------------------------------------------------------
mcb3_dram_dqs <= mcb3_dram_dqs_vector(0)
when ( mcb3_enable1 = '1') else 'Z';
mcb3_dram_udqs <= mcb3_dram_dqs_vector(1)
when (mcb3_enable1 = '1') else 'Z';
mcb3_dram_dqs_n <= mcb3_dram_dqs_n_vector(0)
when (mcb3_enable1 = '1') else 'Z';
mcb3_dram_udqs_n <= mcb3_dram_dqs_n_vector(1)
when (mcb3_enable1 = '1') else 'Z';
mcb3_dram_dm_vector <= (mcb3_dram_udm & mcb3_dram_dm);
u_mem_c3 : ddr3_model_c3 port map
(
ck => mcb3_dram_ck,
ck_n => mcb3_dram_ck_n,
cke => mcb3_dram_cke,
cs_n => '0',
ras_n => mcb3_dram_ras_n,
cas_n => mcb3_dram_cas_n,
we_n => mcb3_dram_we_n,
dm_tdqs => mcb3_dram_dm_vector,
ba => mcb3_dram_ba,
addr => mcb3_dram_a,
dq => mcb3_dram_dq,
dqs => mcb3_dram_dqs_vector,
dqs_n => mcb3_dram_dqs_n_vector,
tdqs_n => open,
odt => mcb3_dram_odt,
rst_n => mcb3_dram_reset_n
);
-----------------------------------------------------------------------------
-- Reporting the test case status
-----------------------------------------------------------------------------
Logging: process
begin
wait for 200 us;
if (calib_done = '1') then
if (error = '0') then
report ("****TEST PASSED****");
else
report ("****TEST FAILED: DATA ERROR****");
end if;
else
report ("****TEST FAILED: INITIALIZATION DID NOT COMPLETE****");
end if;
end process;
end architecture;
|
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 3.9
-- \ \ Application : MIG
-- / / Filename : sim_tb_top.vhd
-- /___/ /\ Date Last Modified : $Date: 2011/06/02 07:16:58 $
-- \ \ / \ Date Created : Jul 03 2009
-- \___\/\___\
--
-- Device : Spartan-6
-- Design Name : DDR/DDR2/DDR3/LPDDR
-- Purpose : This is the simulation testbench which is used to verify the
-- design. The basic clocks and resets to the interface are
-- generated here. This also connects the memory interface to the
-- memory model.
--*****************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity sim_tb_top is
end entity sim_tb_top;
architecture arch of sim_tb_top is
-- ========================================================================== --
-- Parameters --
-- ========================================================================== --
constant DEBUG_EN : integer :=0;
constant C3_HW_TESTING : string := "FALSE";
function c3_sim_hw (val1:std_logic_vector( 31 downto 0); val2: std_logic_vector( 31 downto 0) ) return std_logic_vector is
begin
if (C3_HW_TESTING = "FALSE") then
return val1;
else
return val2;
end if;
end function;
constant C3_MEMCLK_PERIOD : integer := 3000;
constant C3_RST_ACT_LOW : integer := 0;
constant C3_INPUT_CLK_TYPE : string := "SINGLE_ENDED";
constant C3_CLK_PERIOD_NS : real := 3000.0 / 1000.0;
constant C3_TCYC_SYS : real := C3_CLK_PERIOD_NS/2.0;
constant C3_TCYC_SYS_DIV2 : time := C3_TCYC_SYS * 1 ns;
constant C3_NUM_DQ_PINS : integer := 16;
constant C3_MEM_ADDR_WIDTH : integer := 14;
constant C3_MEM_BANKADDR_WIDTH : integer := 3;
constant C3_MEM_ADDR_ORDER : string := "ROW_BANK_COLUMN";
constant C3_P0_MASK_SIZE : integer := 4;
constant C3_P0_DATA_PORT_SIZE : integer := 32;
constant C3_P1_MASK_SIZE : integer := 4;
constant C3_P1_DATA_PORT_SIZE : integer := 32;
constant C3_MEM_BURST_LEN : integer := 8;
constant C3_MEM_NUM_COL_BITS : integer := 10;
constant C3_SIMULATION : string := "TRUE";
constant C3_CALIB_SOFT_IP : string := "TRUE";
constant C3_p0_BEGIN_ADDRESS : std_logic_vector(31 downto 0) := c3_sim_hw (x"00000100", x"01000000");
constant C3_p0_DATA_MODE : std_logic_vector(3 downto 0) := "0010";
constant C3_p0_END_ADDRESS : std_logic_vector(31 downto 0) := c3_sim_hw (x"000002ff", x"02ffffff");
constant C3_p0_PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := c3_sim_hw (x"fffffc00", x"fc000000");
constant C3_p0_PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := c3_sim_hw (x"00000100", x"01000000");
constant C3_p1_BEGIN_ADDRESS : std_logic_vector(31 downto 0) := c3_sim_hw (x"00000300", x"03000000");
constant C3_p1_DATA_MODE : std_logic_vector(3 downto 0) := "0010";
constant C3_p1_END_ADDRESS : std_logic_vector(31 downto 0) := c3_sim_hw (x"000004ff", x"04ffffff");
constant C3_p1_PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := c3_sim_hw (x"fffff800", x"f8000000");
constant C3_p1_PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := c3_sim_hw (x"00000300", x"03000000");
-- ========================================================================== --
-- Component Declarations
-- ========================================================================== --
component ddr3_ctrl_spec_bank3_32b_32b is
generic
(
C3_P0_MASK_SIZE : integer;
C3_P0_DATA_PORT_SIZE : integer;
C3_P1_MASK_SIZE : integer;
C3_P1_DATA_PORT_SIZE : integer;
C3_MEMCLK_PERIOD : integer;
C3_RST_ACT_LOW : integer;
C3_INPUT_CLK_TYPE : string;
DEBUG_EN : integer;
C3_CALIB_SOFT_IP : string;
C3_SIMULATION : string;
C3_MEM_ADDR_ORDER : string;
C3_NUM_DQ_PINS : integer;
C3_MEM_ADDR_WIDTH : integer;
C3_MEM_BANKADDR_WIDTH : integer
);
port
(
mcb3_dram_dq : inout std_logic_vector(C3_NUM_DQ_PINS-1 downto 0);
mcb3_dram_a : out std_logic_vector(C3_MEM_ADDR_WIDTH-1 downto 0);
mcb3_dram_ba : out std_logic_vector(C3_MEM_BANKADDR_WIDTH-1 downto 0);
mcb3_dram_ras_n : out std_logic;
mcb3_dram_cas_n : out std_logic;
mcb3_dram_we_n : out std_logic;
mcb3_dram_odt : out std_logic;
mcb3_dram_cke : out std_logic;
mcb3_dram_dm : out std_logic;
mcb3_rzq : inout std_logic;
c3_sys_clk : in std_logic;
c3_sys_rst_i : in std_logic;
c3_calib_done : out std_logic;
c3_clk0 : out std_logic;
c3_rst0 : out std_logic;
mcb3_dram_dqs : inout std_logic;
mcb3_dram_dqs_n : inout std_logic;
mcb3_dram_ck : out std_logic;
mcb3_dram_udqs : inout std_logic;
mcb3_dram_udqs_n : inout std_logic;
mcb3_dram_udm : out std_logic;
mcb3_dram_ck_n : out std_logic;
mcb3_dram_reset_n : out std_logic; c3_p0_cmd_clk : in std_logic;
c3_p0_cmd_en : in std_logic;
c3_p0_cmd_instr : in std_logic_vector(2 downto 0);
c3_p0_cmd_bl : in std_logic_vector(5 downto 0);
c3_p0_cmd_byte_addr : in std_logic_vector(29 downto 0);
c3_p0_cmd_empty : out std_logic;
c3_p0_cmd_full : out std_logic;
c3_p0_wr_clk : in std_logic;
c3_p0_wr_en : in std_logic;
c3_p0_wr_mask : in std_logic_vector(C3_P0_MASK_SIZE - 1 downto 0);
c3_p0_wr_data : in std_logic_vector(C3_P0_DATA_PORT_SIZE - 1 downto 0);
c3_p0_wr_full : out std_logic;
c3_p0_wr_empty : out std_logic;
c3_p0_wr_count : out std_logic_vector(6 downto 0);
c3_p0_wr_underrun : out std_logic;
c3_p0_wr_error : out std_logic;
c3_p0_rd_clk : in std_logic;
c3_p0_rd_en : in std_logic;
c3_p0_rd_data : out std_logic_vector(C3_P0_DATA_PORT_SIZE - 1 downto 0);
c3_p0_rd_full : out std_logic;
c3_p0_rd_empty : out std_logic;
c3_p0_rd_count : out std_logic_vector(6 downto 0);
c3_p0_rd_overflow : out std_logic;
c3_p0_rd_error : out std_logic;
c3_p1_cmd_clk : in std_logic;
c3_p1_cmd_en : in std_logic;
c3_p1_cmd_instr : in std_logic_vector(2 downto 0);
c3_p1_cmd_bl : in std_logic_vector(5 downto 0);
c3_p1_cmd_byte_addr : in std_logic_vector(29 downto 0);
c3_p1_cmd_empty : out std_logic;
c3_p1_cmd_full : out std_logic;
c3_p1_wr_clk : in std_logic;
c3_p1_wr_en : in std_logic;
c3_p1_wr_mask : in std_logic_vector(C3_P1_MASK_SIZE - 1 downto 0);
c3_p1_wr_data : in std_logic_vector(C3_P1_DATA_PORT_SIZE - 1 downto 0);
c3_p1_wr_full : out std_logic;
c3_p1_wr_empty : out std_logic;
c3_p1_wr_count : out std_logic_vector(6 downto 0);
c3_p1_wr_underrun : out std_logic;
c3_p1_wr_error : out std_logic;
c3_p1_rd_clk : in std_logic;
c3_p1_rd_en : in std_logic;
c3_p1_rd_data : out std_logic_vector(C3_P1_DATA_PORT_SIZE - 1 downto 0);
c3_p1_rd_full : out std_logic;
c3_p1_rd_empty : out std_logic;
c3_p1_rd_count : out std_logic_vector(6 downto 0);
c3_p1_rd_overflow : out std_logic;
c3_p1_rd_error : out std_logic
);
end component;
component ddr3_model_c3 is
port (
ck : in std_logic;
ck_n : in std_logic;
cke : in std_logic;
cs_n : in std_logic;
ras_n : in std_logic;
cas_n : in std_logic;
we_n : in std_logic;
dm_tdqs : inout std_logic_vector((C3_NUM_DQ_PINS/16) downto 0);
ba : in std_logic_vector((C3_MEM_BANKADDR_WIDTH - 1) downto 0);
addr : in std_logic_vector((C3_MEM_ADDR_WIDTH - 1) downto 0);
dq : inout std_logic_vector((C3_NUM_DQ_PINS - 1) downto 0);
dqs : inout std_logic_vector((C3_NUM_DQ_PINS/16) downto 0);
dqs_n : inout std_logic_vector((C3_NUM_DQ_PINS/16) downto 0);
tdqs_n : out std_logic_vector((C3_NUM_DQ_PINS/16) downto 0);
odt : in std_logic;
rst_n : in std_logic
);
end component;
component memc3_tb_top is
generic
(
C_P0_MASK_SIZE : integer := 4;
C_P0_DATA_PORT_SIZE : integer := 32;
C_P1_MASK_SIZE : integer := 4;
C_P1_DATA_PORT_SIZE : integer := 32;
C_MEM_BURST_LEN : integer := 8;
C_MEM_NUM_COL_BITS : integer := 11;
C_NUM_DQ_PINS : integer := 8;
C_p0_BEGIN_ADDRESS : std_logic_vector(31 downto 0) := X"00000100";
C_p0_DATA_MODE : std_logic_vector(3 downto 0) := "0010";
C_p0_END_ADDRESS : std_logic_vector(31 downto 0) := X"000002ff";
C_p0_PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := X"fffffc00";
C_p0_PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := X"00000100";
C_p1_BEGIN_ADDRESS : std_logic_vector(31 downto 0) := X"00000300";
C_p1_DATA_MODE : std_logic_vector(3 downto 0) := "0010";
C_p1_END_ADDRESS : std_logic_vector(31 downto 0) := X"000004ff";
C_p1_PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := X"fffff800";
C_p1_PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := X"00000300"
);
port
(
clk0 : in std_logic;
rst0 : in std_logic;
calib_done : in std_logic;
p0_mcb_cmd_en_o : out std_logic;
p0_mcb_cmd_instr_o : out std_logic_vector(2 downto 0);
p0_mcb_cmd_bl_o : out std_logic_vector(5 downto 0);
p0_mcb_cmd_addr_o : out std_logic_vector(29 downto 0);
p0_mcb_cmd_full_i : in std_logic;
p0_mcb_wr_en_o : out std_logic;
p0_mcb_wr_mask_o : out std_logic_vector(C_P0_MASK_SIZE - 1 downto 0);
p0_mcb_wr_data_o : out std_logic_vector(C_P0_DATA_PORT_SIZE - 1 downto 0);
p0_mcb_wr_full_i : in std_logic;
p0_mcb_wr_fifo_counts : in std_logic_vector(6 downto 0);
p0_mcb_rd_en_o : out std_logic;
p0_mcb_rd_data_i : in std_logic_vector(C_P0_DATA_PORT_SIZE - 1 downto 0);
p0_mcb_rd_empty_i : in std_logic;
p0_mcb_rd_fifo_counts : in std_logic_vector(6 downto 0);
p1_mcb_cmd_en_o : out std_logic;
p1_mcb_cmd_instr_o : out std_logic_vector(2 downto 0);
p1_mcb_cmd_bl_o : out std_logic_vector(5 downto 0);
p1_mcb_cmd_addr_o : out std_logic_vector(29 downto 0);
p1_mcb_cmd_full_i : in std_logic;
p1_mcb_wr_en_o : out std_logic;
p1_mcb_wr_mask_o : out std_logic_vector(C_P1_MASK_SIZE - 1 downto 0);
p1_mcb_wr_data_o : out std_logic_vector(C_P1_DATA_PORT_SIZE - 1 downto 0);
p1_mcb_wr_full_i : in std_logic;
p1_mcb_wr_fifo_counts : in std_logic_vector(6 downto 0);
p1_mcb_rd_en_o : out std_logic;
p1_mcb_rd_data_i : in std_logic_vector(C_P1_DATA_PORT_SIZE - 1 downto 0);
p1_mcb_rd_empty_i : in std_logic;
p1_mcb_rd_fifo_counts : in std_logic_vector(6 downto 0);
vio_modify_enable : in std_logic;
vio_data_mode_value : in std_logic_vector(2 downto 0);
vio_addr_mode_value : in std_logic_vector(2 downto 0);
cmp_error : out std_logic;
error : out std_logic;
error_status : out std_logic_vector(127 downto 0)
);
end component;
-- ========================================================================== --
-- Signal Declarations --
-- ========================================================================== --
-- Clocks
-- Clocks
signal c3_sys_clk : std_logic := '0';
signal c3_sys_clk_p : std_logic;
signal c3_sys_clk_n : std_logic;
-- System Reset
signal c3_sys_rst : std_logic := '0';
signal c3_sys_rst_i : std_logic;
-- Design-Top Port Map
signal c3_error : std_logic;
signal c3_calib_done : std_logic;
signal c3_error_status : std_logic_vector(127 downto 0);
signal mcb3_dram_a : std_logic_vector(C3_MEM_ADDR_WIDTH-1 downto 0);
signal mcb3_dram_ba : std_logic_vector(C3_MEM_BANKADDR_WIDTH-1 downto 0);
signal mcb3_dram_ck : std_logic;
signal mcb3_dram_ck_n : std_logic;
signal mcb3_dram_dq : std_logic_vector(C3_NUM_DQ_PINS-1 downto 0);
signal mcb3_dram_dqs : std_logic;
signal mcb3_dram_dqs_n : std_logic;
signal mcb3_dram_dm : std_logic;
signal mcb3_dram_ras_n : std_logic;
signal mcb3_dram_cas_n : std_logic;
signal mcb3_dram_we_n : std_logic;
signal mcb3_dram_cke : std_logic;
signal mcb3_dram_odt : std_logic;
signal mcb3_dram_reset_n : std_logic;
signal mcb3_dram_udqs : std_logic;
signal mcb3_dram_udqs_n : std_logic;
signal mcb3_dram_dqs_vector : std_logic_vector(1 downto 0);
signal mcb3_dram_dqs_n_vector : std_logic_vector(1 downto 0);
signal mcb3_dram_udm :std_logic; -- for X16 parts
signal mcb3_dram_dm_vector : std_logic_vector(1 downto 0);
-- User design Sim
signal c3_clk0 : std_logic;
signal c3_rst0 : std_logic;
signal c3_cmp_error : std_logic;
signal c3_vio_modify_enable : std_logic;
signal c3_vio_data_mode_value : std_logic_vector(2 downto 0);
signal c3_vio_addr_mode_value : std_logic_vector(2 downto 0);
signal mcb3_command : std_logic_vector(2 downto 0);
signal mcb3_enable1 : std_logic;
signal mcb3_enable2 : std_logic;
signal c3_p0_cmd_en : std_logic;
signal c3_p0_cmd_instr : std_logic_vector(2 downto 0);
signal c3_p0_cmd_bl : std_logic_vector(5 downto 0);
signal c3_p0_cmd_byte_addr : std_logic_vector(29 downto 0);
signal c3_p0_cmd_empty : std_logic;
signal c3_p0_cmd_full : std_logic;
signal c3_p0_wr_en : std_logic;
signal c3_p0_wr_mask : std_logic_vector(C3_P0_MASK_SIZE - 1 downto 0);
signal c3_p0_wr_data : std_logic_vector(C3_P0_DATA_PORT_SIZE - 1 downto 0);
signal c3_p0_wr_full : std_logic;
signal c3_p0_wr_empty : std_logic;
signal c3_p0_wr_count : std_logic_vector(6 downto 0);
signal c3_p0_wr_underrun : std_logic;
signal c3_p0_wr_error : std_logic;
signal c3_p0_rd_en : std_logic;
signal c3_p0_rd_data : std_logic_vector(C3_P0_DATA_PORT_SIZE - 1 downto 0);
signal c3_p0_rd_full : std_logic;
signal c3_p0_rd_empty : std_logic;
signal c3_p0_rd_count : std_logic_vector(6 downto 0);
signal c3_p0_rd_overflow : std_logic;
signal c3_p0_rd_error : std_logic;
signal c3_p1_cmd_en : std_logic;
signal c3_p1_cmd_instr : std_logic_vector(2 downto 0);
signal c3_p1_cmd_bl : std_logic_vector(5 downto 0);
signal c3_p1_cmd_byte_addr : std_logic_vector(29 downto 0);
signal c3_p1_cmd_empty : std_logic;
signal c3_p1_cmd_full : std_logic;
signal c3_p1_wr_en : std_logic;
signal c3_p1_wr_mask : std_logic_vector(C3_P1_MASK_SIZE - 1 downto 0);
signal c3_p1_wr_data : std_logic_vector(C3_P1_DATA_PORT_SIZE - 1 downto 0);
signal c3_p1_wr_full : std_logic;
signal c3_p1_wr_empty : std_logic;
signal c3_p1_wr_count : std_logic_vector(6 downto 0);
signal c3_p1_wr_underrun : std_logic;
signal c3_p1_wr_error : std_logic;
signal c3_p1_rd_en : std_logic;
signal c3_p1_rd_data : std_logic_vector(C3_P1_DATA_PORT_SIZE - 1 downto 0);
signal c3_p1_rd_full : std_logic;
signal c3_p1_rd_empty : std_logic;
signal c3_p1_rd_count : std_logic_vector(6 downto 0);
signal c3_p1_rd_overflow : std_logic;
signal c3_p1_rd_error : std_logic;
signal c3_selfrefresh_enter : std_logic;
signal c3_selfrefresh_mode : std_logic;
signal rzq3 : std_logic;
signal calib_done : std_logic;
signal error : std_logic;
function vector (asi:std_logic) return std_logic_vector is
variable v : std_logic_vector(0 downto 0) ;
begin
v(0) := asi;
return(v);
end function vector;
begin
-- ========================================================================== --
-- Clocks Generation --
-- ========================================================================== --
process
begin
c3_sys_clk <= not c3_sys_clk;
wait for (C3_TCYC_SYS_DIV2);
end process;
c3_sys_clk_p <= c3_sys_clk;
c3_sys_clk_n <= not c3_sys_clk;
-- ========================================================================== --
-- Reset Generation --
-- ========================================================================== --
process
begin
c3_sys_rst <= '0';
wait for 200 ns;
c3_sys_rst <= '1';
wait;
end process;
c3_sys_rst_i <= c3_sys_rst when (C3_RST_ACT_LOW = 1) else (not c3_sys_rst);
error <= c3_error;
calib_done <= c3_calib_done;
rzq_pulldown3 : PULLDOWN port map(O => rzq3);
-- ========================================================================== --
-- DESIGN TOP INSTANTIATION --
-- ========================================================================== --
design_top : ddr3_ctrl_spec_bank3_32b_32b generic map
(
C3_P0_MASK_SIZE => C3_P0_MASK_SIZE,
C3_P0_DATA_PORT_SIZE => C3_P0_DATA_PORT_SIZE,
C3_P1_MASK_SIZE => C3_P1_MASK_SIZE,
C3_P1_DATA_PORT_SIZE => C3_P1_DATA_PORT_SIZE,
C3_MEMCLK_PERIOD => C3_MEMCLK_PERIOD,
C3_RST_ACT_LOW => C3_RST_ACT_LOW,
C3_INPUT_CLK_TYPE => C3_INPUT_CLK_TYPE,
DEBUG_EN => DEBUG_EN,
C3_MEM_ADDR_ORDER => C3_MEM_ADDR_ORDER,
C3_NUM_DQ_PINS => C3_NUM_DQ_PINS,
C3_MEM_ADDR_WIDTH => C3_MEM_ADDR_WIDTH,
C3_MEM_BANKADDR_WIDTH => C3_MEM_BANKADDR_WIDTH,
C3_SIMULATION => C3_SIMULATION,
C3_CALIB_SOFT_IP => C3_CALIB_SOFT_IP
)
port map (
c3_sys_clk => c3_sys_clk,
c3_sys_rst_i => c3_sys_rst_i,
mcb3_dram_dq => mcb3_dram_dq,
mcb3_dram_a => mcb3_dram_a,
mcb3_dram_ba => mcb3_dram_ba,
mcb3_dram_ras_n => mcb3_dram_ras_n,
mcb3_dram_cas_n => mcb3_dram_cas_n,
mcb3_dram_we_n => mcb3_dram_we_n,
mcb3_dram_odt => mcb3_dram_odt,
mcb3_dram_cke => mcb3_dram_cke,
mcb3_dram_ck => mcb3_dram_ck,
mcb3_dram_ck_n => mcb3_dram_ck_n,
mcb3_dram_dqs => mcb3_dram_dqs,
mcb3_dram_dqs_n => mcb3_dram_dqs_n,
mcb3_dram_reset_n => mcb3_dram_reset_n,
mcb3_dram_udqs => mcb3_dram_udqs, -- for X16 parts
mcb3_dram_udqs_n => mcb3_dram_udqs_n, -- for X16 parts
mcb3_dram_udm => mcb3_dram_udm, -- for X16 parts
mcb3_dram_dm => mcb3_dram_dm,
c3_clk0 => c3_clk0,
c3_rst0 => c3_rst0,
c3_calib_done => c3_calib_done,
mcb3_rzq => rzq3,
c3_p0_cmd_clk => (c3_clk0),
c3_p0_cmd_en => c3_p0_cmd_en,
c3_p0_cmd_instr => c3_p0_cmd_instr,
c3_p0_cmd_bl => c3_p0_cmd_bl,
c3_p0_cmd_byte_addr => c3_p0_cmd_byte_addr,
c3_p0_cmd_empty => c3_p0_cmd_empty,
c3_p0_cmd_full => c3_p0_cmd_full,
c3_p0_wr_clk => (c3_clk0),
c3_p0_wr_en => c3_p0_wr_en,
c3_p0_wr_mask => c3_p0_wr_mask,
c3_p0_wr_data => c3_p0_wr_data,
c3_p0_wr_full => c3_p0_wr_full,
c3_p0_wr_empty => c3_p0_wr_empty,
c3_p0_wr_count => c3_p0_wr_count,
c3_p0_wr_underrun => c3_p0_wr_underrun,
c3_p0_wr_error => c3_p0_wr_error,
c3_p0_rd_clk => (c3_clk0),
c3_p0_rd_en => c3_p0_rd_en,
c3_p0_rd_data => c3_p0_rd_data,
c3_p0_rd_full => c3_p0_rd_full,
c3_p0_rd_empty => c3_p0_rd_empty,
c3_p0_rd_count => c3_p0_rd_count,
c3_p0_rd_overflow => c3_p0_rd_overflow,
c3_p0_rd_error => c3_p0_rd_error,
c3_p1_cmd_clk => (c3_clk0),
c3_p1_cmd_en => c3_p1_cmd_en,
c3_p1_cmd_instr => c3_p1_cmd_instr,
c3_p1_cmd_bl => c3_p1_cmd_bl,
c3_p1_cmd_byte_addr => c3_p1_cmd_byte_addr,
c3_p1_cmd_empty => c3_p1_cmd_empty,
c3_p1_cmd_full => c3_p1_cmd_full,
c3_p1_wr_clk => (c3_clk0),
c3_p1_wr_en => c3_p1_wr_en,
c3_p1_wr_mask => c3_p1_wr_mask,
c3_p1_wr_data => c3_p1_wr_data,
c3_p1_wr_full => c3_p1_wr_full,
c3_p1_wr_empty => c3_p1_wr_empty,
c3_p1_wr_count => c3_p1_wr_count,
c3_p1_wr_underrun => c3_p1_wr_underrun,
c3_p1_wr_error => c3_p1_wr_error,
c3_p1_rd_clk => (c3_clk0),
c3_p1_rd_en => c3_p1_rd_en,
c3_p1_rd_data => c3_p1_rd_data,
c3_p1_rd_full => c3_p1_rd_full,
c3_p1_rd_empty => c3_p1_rd_empty,
c3_p1_rd_count => c3_p1_rd_count,
c3_p1_rd_overflow => c3_p1_rd_overflow,
c3_p1_rd_error => c3_p1_rd_error
);
-- user interface
memc3_tb_top_inst : memc3_tb_top generic map
(
C_NUM_DQ_PINS => C3_NUM_DQ_PINS,
C_MEM_BURST_LEN => C3_MEM_BURST_LEN,
C_MEM_NUM_COL_BITS => C3_MEM_NUM_COL_BITS,
C_P0_MASK_SIZE => C3_P0_MASK_SIZE,
C_P0_DATA_PORT_SIZE => C3_P0_DATA_PORT_SIZE,
C_P1_MASK_SIZE => C3_P1_MASK_SIZE,
C_P1_DATA_PORT_SIZE => C3_P1_DATA_PORT_SIZE,
C_p0_BEGIN_ADDRESS => C3_p0_BEGIN_ADDRESS,
C_p0_DATA_MODE => C3_p0_DATA_MODE,
C_p0_END_ADDRESS => C3_p0_END_ADDRESS,
C_p0_PRBS_EADDR_MASK_POS => C3_p0_PRBS_EADDR_MASK_POS,
C_p0_PRBS_SADDR_MASK_POS => C3_p0_PRBS_SADDR_MASK_POS,
C_p1_BEGIN_ADDRESS => C3_p1_BEGIN_ADDRESS,
C_p1_DATA_MODE => C3_p1_DATA_MODE,
C_p1_END_ADDRESS => C3_p1_END_ADDRESS,
C_p1_PRBS_EADDR_MASK_POS => C3_p1_PRBS_EADDR_MASK_POS,
C_p1_PRBS_SADDR_MASK_POS => C3_p1_PRBS_SADDR_MASK_POS
)
port map
(
clk0 => c3_clk0,
rst0 => c3_rst0,
calib_done => c3_calib_done,
cmp_error => c3_cmp_error,
error => c3_error,
error_status => c3_error_status,
vio_modify_enable => c3_vio_modify_enable,
vio_data_mode_value => c3_vio_data_mode_value,
vio_addr_mode_value => c3_vio_addr_mode_value,
p0_mcb_cmd_en_o => c3_p0_cmd_en,
p0_mcb_cmd_instr_o => c3_p0_cmd_instr,
p0_mcb_cmd_bl_o => c3_p0_cmd_bl,
p0_mcb_cmd_addr_o => c3_p0_cmd_byte_addr,
p0_mcb_cmd_full_i => c3_p0_cmd_full,
p0_mcb_wr_en_o => c3_p0_wr_en,
p0_mcb_wr_mask_o => c3_p0_wr_mask,
p0_mcb_wr_data_o => c3_p0_wr_data,
p0_mcb_wr_full_i => c3_p0_wr_full,
p0_mcb_wr_fifo_counts => c3_p0_wr_count,
p0_mcb_rd_en_o => c3_p0_rd_en,
p0_mcb_rd_data_i => c3_p0_rd_data,
p0_mcb_rd_empty_i => c3_p0_rd_empty,
p0_mcb_rd_fifo_counts => c3_p0_rd_count,
p1_mcb_cmd_en_o => c3_p1_cmd_en,
p1_mcb_cmd_instr_o => c3_p1_cmd_instr,
p1_mcb_cmd_bl_o => c3_p1_cmd_bl,
p1_mcb_cmd_addr_o => c3_p1_cmd_byte_addr,
p1_mcb_cmd_full_i => c3_p1_cmd_full,
p1_mcb_wr_en_o => c3_p1_wr_en,
p1_mcb_wr_mask_o => c3_p1_wr_mask,
p1_mcb_wr_data_o => c3_p1_wr_data,
p1_mcb_wr_full_i => c3_p1_wr_full,
p1_mcb_wr_fifo_counts => c3_p1_wr_count,
p1_mcb_rd_en_o => c3_p1_rd_en,
p1_mcb_rd_data_i => c3_p1_rd_data,
p1_mcb_rd_empty_i => c3_p1_rd_empty,
p1_mcb_rd_fifo_counts => c3_p1_rd_count
);
-- ========================================================================== --
-- Memory model instances --
-- ========================================================================== --
mcb3_command <= (mcb3_dram_ras_n & mcb3_dram_cas_n & mcb3_dram_we_n);
process(mcb3_dram_ck)
begin
if (rising_edge(mcb3_dram_ck)) then
if (c3_sys_rst = '0') then
mcb3_enable1 <= '0';
mcb3_enable2 <= '0';
elsif (mcb3_command = "100") then
mcb3_enable2 <= '0';
elsif (mcb3_command = "101") then
mcb3_enable2 <= '1';
else
mcb3_enable2 <= mcb3_enable2;
end if;
mcb3_enable1 <= mcb3_enable2;
end if;
end process;
-----------------------------------------------------------------------------
--read
-----------------------------------------------------------------------------
mcb3_dram_dqs_vector(1 downto 0) <= (mcb3_dram_udqs & mcb3_dram_dqs)
when (mcb3_enable2 = '0' and mcb3_enable1 = '0')
else "ZZ";
mcb3_dram_dqs_n_vector(1 downto 0) <= (mcb3_dram_udqs_n & mcb3_dram_dqs_n)
when (mcb3_enable2 = '0' and mcb3_enable1 = '0')
else "ZZ";
-----------------------------------------------------------------------------
--write
-----------------------------------------------------------------------------
mcb3_dram_dqs <= mcb3_dram_dqs_vector(0)
when ( mcb3_enable1 = '1') else 'Z';
mcb3_dram_udqs <= mcb3_dram_dqs_vector(1)
when (mcb3_enable1 = '1') else 'Z';
mcb3_dram_dqs_n <= mcb3_dram_dqs_n_vector(0)
when (mcb3_enable1 = '1') else 'Z';
mcb3_dram_udqs_n <= mcb3_dram_dqs_n_vector(1)
when (mcb3_enable1 = '1') else 'Z';
mcb3_dram_dm_vector <= (mcb3_dram_udm & mcb3_dram_dm);
u_mem_c3 : ddr3_model_c3 port map
(
ck => mcb3_dram_ck,
ck_n => mcb3_dram_ck_n,
cke => mcb3_dram_cke,
cs_n => '0',
ras_n => mcb3_dram_ras_n,
cas_n => mcb3_dram_cas_n,
we_n => mcb3_dram_we_n,
dm_tdqs => mcb3_dram_dm_vector,
ba => mcb3_dram_ba,
addr => mcb3_dram_a,
dq => mcb3_dram_dq,
dqs => mcb3_dram_dqs_vector,
dqs_n => mcb3_dram_dqs_n_vector,
tdqs_n => open,
odt => mcb3_dram_odt,
rst_n => mcb3_dram_reset_n
);
-----------------------------------------------------------------------------
-- Reporting the test case status
-----------------------------------------------------------------------------
Logging: process
begin
wait for 200 us;
if (calib_done = '1') then
if (error = '0') then
report ("****TEST PASSED****");
else
report ("****TEST FAILED: DATA ERROR****");
end if;
else
report ("****TEST FAILED: INITIALIZATION DID NOT COMPLETE****");
end if;
end process;
end architecture;
|
--
-------------------------------------------------------------------------------------------
-- Copyright © 2010-2014, Xilinx, Inc.
-- This file contains confidential and proprietary information of Xilinx, Inc. and is
-- protected under U.S. and international copyright and other intellectual property laws.
-------------------------------------------------------------------------------------------
--
-- Disclaimer:
-- This disclaimer is not a license and does not grant any rights to the materials
-- distributed herewith. Except as otherwise provided in a valid license issued to
-- you by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE
-- MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY
-- DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY,
-- INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT,
-- OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable
-- (whether in contract or tort, including negligence, or under any other theory
-- of liability) for any loss or damage of any kind or nature related to, arising
-- under or in connection with these materials, including for any direct, or any
-- indirect, special, incidental, or consequential loss or damage (including loss
-- of data, profits, goodwill, or any type of loss or damage suffered as a result
-- of any action brought by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-safe, or for use in any
-- application requiring fail-safe performance, such as life-support or safety
-- devices or systems, Class III medical devices, nuclear facilities, applications
-- related to the deployment of airbags, or any other applications that could lead
-- to death, personal injury, or severe property or environmental damage
-- (individually and collectively, "Critical Applications"). Customer assumes the
-- sole risk and liability of any use of Xilinx products in Critical Applications,
-- subject only to applicable laws and regulations governing limitations on product
-- liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------------------
--
ROM_form.vhd
Template for a KCPSM6 program memory. This template is primarily for use during code
development including generic parameters for the convenient selection of device family,
program memory size and the ability to include the JTAG Loader hardware for rapid
software development.
Kris Chaplin and Ken Chapman (Xilinx Ltd)
17th September 2010 - First Release
4th February 2011 - Correction to definition of 'we_b' in V6/1K/JTAG instance.
3rd March 2011 - Minor adjustments to comments only.
16th August 2011 - Additions and adjustments for support of 7-Series in ISE v13.2.
Simplification of JTAG Loader definition.
23rd November 2012 - 4K program for Spartan-6.
14th March 2013 - Unused address inputs on Virtex-6 and 7-Series BRAMs connected
High to reflect descriptions in UG363 and UG473.
2nd June 2014 - Template for use with Vivado 2014.1 (and later).
Removal of Spartan-6 and Virtex-6 memories not supported by Vivado.
Addition of UltraScale memories which are only supported by Vivado.
Additional attributes for 7-Series BRAMs to reflect Vivado library.
This is a VHDL template file for the KCPSM6 assembler.
This VHDL file is not valid as input directly into a synthesis or a simulation tool.
The assembler will read this template and insert the information required to complete
the definition of program ROM and write it out to a new '.vhd' file that is ready for
synthesis and simulation.
This template can be modified to define alternative memory definitions. However, you are
responsible for ensuring the template is correct as the assembler does not perform any
checking of the VHDL.
The assembler identifies all text enclosed by {} characters, and replaces these
character strings. All templates should include these {} character strings for
the assembler to work correctly.
The next line is used to determine where the template actually starts.
{begin template}
--
-------------------------------------------------------------------------------------------
-- Copyright © 2010-2014, Xilinx, Inc.
-- This file contains confidential and proprietary information of Xilinx, Inc. and is
-- protected under U.S. and international copyright and other intellectual property laws.
-------------------------------------------------------------------------------------------
--
-- Disclaimer:
-- This disclaimer is not a license and does not grant any rights to the materials
-- distributed herewith. Except as otherwise provided in a valid license issued to
-- you by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE
-- MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY
-- DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY,
-- INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT,
-- OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable
-- (whether in contract or tort, including negligence, or under any other theory
-- of liability) for any loss or damage of any kind or nature related to, arising
-- under or in connection with these materials, including for any direct, or any
-- indirect, special, incidental, or consequential loss or damage (including loss
-- of data, profits, goodwill, or any type of loss or damage suffered as a result
-- of any action brought by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-safe, or for use in any
-- application requiring fail-safe performance, such as life-support or safety
-- devices or systems, Class III medical devices, nuclear facilities, applications
-- related to the deployment of airbags, or any other applications that could lead
-- to death, personal injury, or severe property or environmental damage
-- (individually and collectively, "Critical Applications"). Customer assumes the
-- sole risk and liability of any use of Xilinx products in Critical Applications,
-- subject only to applicable laws and regulations governing limitations on product
-- liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------------------
--
--
-- Definition of a program memory for KCPSM6 including generic parameters for the
-- convenient selection of device family, program memory size and the ability to include
-- the JTAG Loader hardware for rapid software development.
--
-- This file is primarily for use during code development and it is recommended that the
-- appropriate simplified program memory definition be used in a final production design.
--
-- Generic Values Comments
-- Parameter Supported
--
-- C_FAMILY "7S" 7-Series device
-- (Artix-7, Kintex-7, Virtex-7 or Zynq)
-- "US" UltraScale device
-- (Kintex UltraScale and Virtex UltraScale)
--
-- C_RAM_SIZE_KWORDS 1, 2 or 4 Size of program memory in K-instructions
--
-- C_JTAG_LOADER_ENABLE 0 or 1 Set to '1' to include JTAG Loader
--
-- Notes
--
-- If your design contains MULTIPLE KCPSM6 instances then only one should have the
-- JTAG Loader enabled at a time (i.e. make sure that C_JTAG_LOADER_ENABLE is only set to
-- '1' on one instance of the program memory). Advanced users may be interested to know
-- that it is possible to connect JTAG Loader to multiple memories and then to use the
-- JTAG Loader utility to specify which memory contents are to be modified. However,
-- this scheme does require some effort to set up and the additional connectivity of the
-- multiple BRAMs can impact the placement, routing and performance of the complete
-- design. Please contact the author at Xilinx for more detailed information.
--
-- Regardless of the size of program memory specified by C_RAM_SIZE_KWORDS, the complete
-- 12-bit address bus is connected to KCPSM6. This enables the generic to be modified
-- without requiring changes to the fundamental hardware definition. However, when the
-- program memory is 1K then only the lower 10-bits of the address are actually used and
-- the valid address range is 000 to 3FF hex. Likewise, for a 2K program only the lower
-- 11-bits of the address are actually used and the valid address range is 000 to 7FF hex.
--
-- Programs are stored in Block Memory (BRAM) and the number of BRAM used depends on the
-- size of the program and the device family.
--
-- In any 7-Series or UltraScale device a BRAM is capable of holding 2K instructions so
-- obviously a 2K program requires only a single BRAM. Each BRAM can also be divided into
-- 2 smaller memories supporting programs of 1K in half of a 36k-bit BRAM (generally
-- reported as being an 18k-bit BRAM). For a program of 4K instructions, 2 BRAMs are used.
--
--
-- Program defined by '{psmname}.psm'.
--
-- Generated by KCPSM6 Assembler: {timestamp}.
--
-- Assembler used ROM_form template: ROM_form_JTAGLoader_Vivado_2June14.vhd
--
-- Standard IEEE libraries
--
--
package jtag_loader_pkg is
function addr_width_calc (size_in_k: integer) return integer;
end jtag_loader_pkg;
--
package body jtag_loader_pkg is
function addr_width_calc (size_in_k: integer) return integer is
begin
if (size_in_k = 1) then return 10;
elsif (size_in_k = 2) then return 11;
elsif (size_in_k = 4) then return 12;
else report "Invalid BlockRAM size. Please set to 1, 2 or 4 K words." severity FAILURE;
end if;
return 0;
end function addr_width_calc;
end package body;
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.jtag_loader_pkg.ALL;
--
-- The Unisim Library is used to define Xilinx primitives. It is also used during
-- simulation. The source can be viewed at %XILINX%\vhdl\src\unisims\unisim_VCOMP.vhd
--
library unisim;
use unisim.vcomponents.all;
--
--
entity {name} is
generic( C_FAMILY : string := "7S";
C_RAM_SIZE_KWORDS : integer := 2;
C_JTAG_LOADER_ENABLE : integer := 0);
Port ( address : in std_logic_vector(11 downto 0);
instruction : out std_logic_vector(17 downto 0);
enable : in std_logic;
rdl : out std_logic;
clk : in std_logic);
end {name};
--
architecture low_level_definition of {name} is
--
signal address_a : std_logic_vector(15 downto 0);
signal data_in_a : std_logic_vector(35 downto 0);
signal data_out_a : std_logic_vector(35 downto 0);
signal data_out_a_l : std_logic_vector(35 downto 0);
signal data_out_a_h : std_logic_vector(35 downto 0);
signal address_b : std_logic_vector(15 downto 0);
signal data_in_b : std_logic_vector(35 downto 0);
signal data_in_b_l : std_logic_vector(35 downto 0);
signal data_out_b : std_logic_vector(35 downto 0);
signal data_out_b_l : std_logic_vector(35 downto 0);
signal data_in_b_h : std_logic_vector(35 downto 0);
signal data_out_b_h : std_logic_vector(35 downto 0);
signal enable_b : std_logic;
signal clk_b : std_logic;
signal we_b : std_logic_vector(7 downto 0);
--
signal jtag_addr : std_logic_vector(11 downto 0);
signal jtag_we : std_logic;
signal jtag_we_l : std_logic;
signal jtag_we_h : std_logic;
signal jtag_clk : std_logic;
signal jtag_din : std_logic_vector(17 downto 0);
signal jtag_dout : std_logic_vector(17 downto 0);
signal jtag_dout_1 : std_logic_vector(17 downto 0);
signal jtag_en : std_logic_vector(0 downto 0);
--
signal picoblaze_reset : std_logic_vector(0 downto 0);
signal rdl_bus : std_logic_vector(0 downto 0);
--
constant BRAM_ADDRESS_WIDTH : integer := addr_width_calc(C_RAM_SIZE_KWORDS);
--
--
component jtag_loader_6
generic( C_JTAG_LOADER_ENABLE : integer := 1;
C_FAMILY : string := "7S";
C_NUM_PICOBLAZE : integer := 1;
C_BRAM_MAX_ADDR_WIDTH : integer := 10;
C_PICOBLAZE_INSTRUCTION_DATA_WIDTH : integer := 18;
C_JTAG_CHAIN : integer := 2;
C_ADDR_WIDTH_0 : integer := 10;
C_ADDR_WIDTH_1 : integer := 10;
C_ADDR_WIDTH_2 : integer := 10;
C_ADDR_WIDTH_3 : integer := 10;
C_ADDR_WIDTH_4 : integer := 10;
C_ADDR_WIDTH_5 : integer := 10;
C_ADDR_WIDTH_6 : integer := 10;
C_ADDR_WIDTH_7 : integer := 10);
port( picoblaze_reset : out std_logic_vector(C_NUM_PICOBLAZE-1 downto 0);
jtag_en : out std_logic_vector(C_NUM_PICOBLAZE-1 downto 0);
jtag_din : out STD_LOGIC_VECTOR(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
jtag_addr : out STD_LOGIC_VECTOR(C_BRAM_MAX_ADDR_WIDTH-1 downto 0);
jtag_clk : out std_logic;
jtag_we : out std_logic;
jtag_dout_0 : in STD_LOGIC_VECTOR(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
jtag_dout_1 : in STD_LOGIC_VECTOR(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
jtag_dout_2 : in STD_LOGIC_VECTOR(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
jtag_dout_3 : in STD_LOGIC_VECTOR(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
jtag_dout_4 : in STD_LOGIC_VECTOR(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
jtag_dout_5 : in STD_LOGIC_VECTOR(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
jtag_dout_6 : in STD_LOGIC_VECTOR(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
jtag_dout_7 : in STD_LOGIC_VECTOR(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0));
end component;
--
begin
--
--
ram_1k_generate : if (C_RAM_SIZE_KWORDS = 1) generate
--
akv7 : if (C_FAMILY = "7S") generate
--
address_a(13 downto 0) <= address(9 downto 0) & "1111";
instruction <= data_out_a(17 downto 0);
data_in_a(17 downto 0) <= "0000000000000000" & address(11 downto 10);
jtag_dout <= data_out_b(17 downto 0);
--
no_loader : if (C_JTAG_LOADER_ENABLE = 0) generate
data_in_b(17 downto 0) <= data_out_b(17 downto 0);
address_b(13 downto 0) <= "11111111111111";
we_b(3 downto 0) <= "0000";
enable_b <= '0';
rdl <= '0';
clk_b <= '0';
end generate no_loader;
--
loader : if (C_JTAG_LOADER_ENABLE = 1) generate
data_in_b(17 downto 0) <= jtag_din(17 downto 0);
address_b(13 downto 0) <= jtag_addr(9 downto 0) & "1111";
we_b(3 downto 0) <= jtag_we & jtag_we & jtag_we & jtag_we;
enable_b <= jtag_en(0);
rdl <= rdl_bus(0);
clk_b <= jtag_clk;
end generate loader;
--
kcpsm6_rom: RAMB18E1
generic map ( READ_WIDTH_A => 18,
WRITE_WIDTH_A => 18,
DOA_REG => 0,
INIT_A => "000000000000000000",
RSTREG_PRIORITY_A => "REGCE",
SRVAL_A => "000000000000000000",
WRITE_MODE_A => "WRITE_FIRST",
READ_WIDTH_B => 18,
WRITE_WIDTH_B => 18,
DOB_REG => 0,
INIT_B => "000000000000000000",
RSTREG_PRIORITY_B => "REGCE",
SRVAL_B => "000000000000000000",
WRITE_MODE_B => "WRITE_FIRST",
INIT_FILE => "NONE",
SIM_COLLISION_CHECK => "ALL",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
SIM_DEVICE => "7SERIES",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
INIT_00 => X"{INIT_00}",
INIT_01 => X"{INIT_01}",
INIT_02 => X"{INIT_02}",
INIT_03 => X"{INIT_03}",
INIT_04 => X"{INIT_04}",
INIT_05 => X"{INIT_05}",
INIT_06 => X"{INIT_06}",
INIT_07 => X"{INIT_07}",
INIT_08 => X"{INIT_08}",
INIT_09 => X"{INIT_09}",
INIT_0A => X"{INIT_0A}",
INIT_0B => X"{INIT_0B}",
INIT_0C => X"{INIT_0C}",
INIT_0D => X"{INIT_0D}",
INIT_0E => X"{INIT_0E}",
INIT_0F => X"{INIT_0F}",
INIT_10 => X"{INIT_10}",
INIT_11 => X"{INIT_11}",
INIT_12 => X"{INIT_12}",
INIT_13 => X"{INIT_13}",
INIT_14 => X"{INIT_14}",
INIT_15 => X"{INIT_15}",
INIT_16 => X"{INIT_16}",
INIT_17 => X"{INIT_17}",
INIT_18 => X"{INIT_18}",
INIT_19 => X"{INIT_19}",
INIT_1A => X"{INIT_1A}",
INIT_1B => X"{INIT_1B}",
INIT_1C => X"{INIT_1C}",
INIT_1D => X"{INIT_1D}",
INIT_1E => X"{INIT_1E}",
INIT_1F => X"{INIT_1F}",
INIT_20 => X"{INIT_20}",
INIT_21 => X"{INIT_21}",
INIT_22 => X"{INIT_22}",
INIT_23 => X"{INIT_23}",
INIT_24 => X"{INIT_24}",
INIT_25 => X"{INIT_25}",
INIT_26 => X"{INIT_26}",
INIT_27 => X"{INIT_27}",
INIT_28 => X"{INIT_28}",
INIT_29 => X"{INIT_29}",
INIT_2A => X"{INIT_2A}",
INIT_2B => X"{INIT_2B}",
INIT_2C => X"{INIT_2C}",
INIT_2D => X"{INIT_2D}",
INIT_2E => X"{INIT_2E}",
INIT_2F => X"{INIT_2F}",
INIT_30 => X"{INIT_30}",
INIT_31 => X"{INIT_31}",
INIT_32 => X"{INIT_32}",
INIT_33 => X"{INIT_33}",
INIT_34 => X"{INIT_34}",
INIT_35 => X"{INIT_35}",
INIT_36 => X"{INIT_36}",
INIT_37 => X"{INIT_37}",
INIT_38 => X"{INIT_38}",
INIT_39 => X"{INIT_39}",
INIT_3A => X"{INIT_3A}",
INIT_3B => X"{INIT_3B}",
INIT_3C => X"{INIT_3C}",
INIT_3D => X"{INIT_3D}",
INIT_3E => X"{INIT_3E}",
INIT_3F => X"{INIT_3F}",
INITP_00 => X"{INITP_00}",
INITP_01 => X"{INITP_01}",
INITP_02 => X"{INITP_02}",
INITP_03 => X"{INITP_03}",
INITP_04 => X"{INITP_04}",
INITP_05 => X"{INITP_05}",
INITP_06 => X"{INITP_06}",
INITP_07 => X"{INITP_07}")
port map( ADDRARDADDR => address_a(13 downto 0),
ENARDEN => enable,
CLKARDCLK => clk,
DOADO => data_out_a(15 downto 0),
DOPADOP => data_out_a(17 downto 16),
DIADI => data_in_a(15 downto 0),
DIPADIP => data_in_a(17 downto 16),
WEA => "00",
REGCEAREGCE => '0',
RSTRAMARSTRAM => '0',
RSTREGARSTREG => '0',
ADDRBWRADDR => address_b(13 downto 0),
ENBWREN => enable_b,
CLKBWRCLK => clk_b,
DOBDO => data_out_b(15 downto 0),
DOPBDOP => data_out_b(17 downto 16),
DIBDI => data_in_b(15 downto 0),
DIPBDIP => data_in_b(17 downto 16),
WEBWE => we_b(3 downto 0),
REGCEB => '0',
RSTRAMB => '0',
RSTREGB => '0');
--
end generate akv7;
--
--
us : if (C_FAMILY = "US") generate
--
address_a(13 downto 0) <= address(9 downto 0) & "1111";
instruction <= data_out_a(17 downto 0);
data_in_a(17 downto 0) <= "0000000000000000" & address(11 downto 10);
jtag_dout <= data_out_b(17 downto 0);
--
no_loader : if (C_JTAG_LOADER_ENABLE = 0) generate
data_in_b(17 downto 0) <= data_out_b(17 downto 0);
address_b(13 downto 0) <= "11111111111111";
we_b(3 downto 0) <= "0000";
enable_b <= '0';
rdl <= '0';
clk_b <= '0';
end generate no_loader;
--
loader : if (C_JTAG_LOADER_ENABLE = 1) generate
data_in_b(17 downto 0) <= jtag_din(17 downto 0);
address_b(13 downto 0) <= jtag_addr(9 downto 0) & "1111";
we_b(3 downto 0) <= jtag_we & jtag_we & jtag_we & jtag_we;
enable_b <= jtag_en(0);
rdl <= rdl_bus(0);
clk_b <= jtag_clk;
end generate loader;
--
kcpsm6_rom: RAMB18E2
generic map ( READ_WIDTH_A => 18,
WRITE_WIDTH_A => 18,
DOA_REG => 0,
INIT_A => "000000000000000000",
RSTREG_PRIORITY_A => "REGCE",
SRVAL_A => "000000000000000000",
WRITE_MODE_A => "WRITE_FIRST",
READ_WIDTH_B => 18,
WRITE_WIDTH_B => 18,
DOB_REG => 0,
INIT_B => "000000000000000000",
RSTREG_PRIORITY_B => "REGCE",
SRVAL_B => "000000000000000000",
WRITE_MODE_B => "WRITE_FIRST",
INIT_FILE => "NONE",
SIM_COLLISION_CHECK => "ALL",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
CASCADE_ORDER_A => "NONE",
CASCADE_ORDER_B => "NONE",
CLOCK_DOMAINS => "INDEPENDENT",
ENADDRENA => "FALSE",
ENADDRENB => "FALSE",
RDADDRCHANGEA => "FALSE",
RDADDRCHANGEB => "FALSE",
SLEEP_ASYNC => "FALSE",
INIT_00 => X"{INIT_00}",
INIT_01 => X"{INIT_01}",
INIT_02 => X"{INIT_02}",
INIT_03 => X"{INIT_03}",
INIT_04 => X"{INIT_04}",
INIT_05 => X"{INIT_05}",
INIT_06 => X"{INIT_06}",
INIT_07 => X"{INIT_07}",
INIT_08 => X"{INIT_08}",
INIT_09 => X"{INIT_09}",
INIT_0A => X"{INIT_0A}",
INIT_0B => X"{INIT_0B}",
INIT_0C => X"{INIT_0C}",
INIT_0D => X"{INIT_0D}",
INIT_0E => X"{INIT_0E}",
INIT_0F => X"{INIT_0F}",
INIT_10 => X"{INIT_10}",
INIT_11 => X"{INIT_11}",
INIT_12 => X"{INIT_12}",
INIT_13 => X"{INIT_13}",
INIT_14 => X"{INIT_14}",
INIT_15 => X"{INIT_15}",
INIT_16 => X"{INIT_16}",
INIT_17 => X"{INIT_17}",
INIT_18 => X"{INIT_18}",
INIT_19 => X"{INIT_19}",
INIT_1A => X"{INIT_1A}",
INIT_1B => X"{INIT_1B}",
INIT_1C => X"{INIT_1C}",
INIT_1D => X"{INIT_1D}",
INIT_1E => X"{INIT_1E}",
INIT_1F => X"{INIT_1F}",
INIT_20 => X"{INIT_20}",
INIT_21 => X"{INIT_21}",
INIT_22 => X"{INIT_22}",
INIT_23 => X"{INIT_23}",
INIT_24 => X"{INIT_24}",
INIT_25 => X"{INIT_25}",
INIT_26 => X"{INIT_26}",
INIT_27 => X"{INIT_27}",
INIT_28 => X"{INIT_28}",
INIT_29 => X"{INIT_29}",
INIT_2A => X"{INIT_2A}",
INIT_2B => X"{INIT_2B}",
INIT_2C => X"{INIT_2C}",
INIT_2D => X"{INIT_2D}",
INIT_2E => X"{INIT_2E}",
INIT_2F => X"{INIT_2F}",
INIT_30 => X"{INIT_30}",
INIT_31 => X"{INIT_31}",
INIT_32 => X"{INIT_32}",
INIT_33 => X"{INIT_33}",
INIT_34 => X"{INIT_34}",
INIT_35 => X"{INIT_35}",
INIT_36 => X"{INIT_36}",
INIT_37 => X"{INIT_37}",
INIT_38 => X"{INIT_38}",
INIT_39 => X"{INIT_39}",
INIT_3A => X"{INIT_3A}",
INIT_3B => X"{INIT_3B}",
INIT_3C => X"{INIT_3C}",
INIT_3D => X"{INIT_3D}",
INIT_3E => X"{INIT_3E}",
INIT_3F => X"{INIT_3F}",
INITP_00 => X"{INITP_00}",
INITP_01 => X"{INITP_01}",
INITP_02 => X"{INITP_02}",
INITP_03 => X"{INITP_03}",
INITP_04 => X"{INITP_04}",
INITP_05 => X"{INITP_05}",
INITP_06 => X"{INITP_06}",
INITP_07 => X"{INITP_07}")
port map( ADDRARDADDR => address_a(13 downto 0),
ENARDEN => enable,
CLKARDCLK => clk,
DOUTADOUT => data_out_a(15 downto 0),
DOUTPADOUTP => data_out_a(17 downto 16),
DINADIN => data_in_a(15 downto 0),
DINPADINP => data_in_a(17 downto 16),
WEA => "00",
REGCEAREGCE => '0',
RSTRAMARSTRAM => '0',
RSTREGARSTREG => '0',
ADDRBWRADDR => address_b(13 downto 0),
ENBWREN => enable_b,
CLKBWRCLK => clk_b,
DOUTBDOUT => data_out_b(15 downto 0),
DOUTPBDOUTP => data_out_b(17 downto 16),
DINBDIN => data_in_b(15 downto 0),
DINPBDINP => data_in_b(17 downto 16),
WEBWE => we_b(3 downto 0),
REGCEB => '0',
RSTRAMB => '0',
RSTREGB => '0',
ADDRENA => '1',
ADDRENB => '1',
CASDIMUXA => '0',
CASDIMUXB => '0',
CASDINA => "0000000000000000",
CASDINB => "0000000000000000",
CASDINPA => "00",
CASDINPB => "00",
CASDOMUXA => '0',
CASDOMUXB => '0',
CASDOMUXEN_A => '1',
CASDOMUXEN_B => '1',
CASOREGIMUXA => '0',
CASOREGIMUXB => '0',
CASOREGIMUXEN_A => '0',
CASOREGIMUXEN_B => '0',
SLEEP => '0');
--
end generate us;
--
end generate ram_1k_generate;
--
--
--
ram_2k_generate : if (C_RAM_SIZE_KWORDS = 2) generate
--
--
akv7 : if (C_FAMILY = "7S") generate
--
address_a <= '1' & address(10 downto 0) & "1111";
instruction <= data_out_a(33 downto 32) & data_out_a(15 downto 0);
data_in_a <= "00000000000000000000000000000000000" & address(11);
jtag_dout <= data_out_b(33 downto 32) & data_out_b(15 downto 0);
--
no_loader : if (C_JTAG_LOADER_ENABLE = 0) generate
data_in_b <= "00" & data_out_b(33 downto 32) & "0000000000000000" & data_out_b(15 downto 0);
address_b <= "1111111111111111";
we_b <= "00000000";
enable_b <= '0';
rdl <= '0';
clk_b <= '0';
end generate no_loader;
--
loader : if (C_JTAG_LOADER_ENABLE = 1) generate
data_in_b <= "00" & jtag_din(17 downto 16) & "0000000000000000" & jtag_din(15 downto 0);
address_b <= '1' & jtag_addr(10 downto 0) & "1111";
we_b <= jtag_we & jtag_we & jtag_we & jtag_we & jtag_we & jtag_we & jtag_we & jtag_we;
enable_b <= jtag_en(0);
rdl <= rdl_bus(0);
clk_b <= jtag_clk;
end generate loader;
--
kcpsm6_rom: RAMB36E1
generic map ( READ_WIDTH_A => 18,
WRITE_WIDTH_A => 18,
DOA_REG => 0,
INIT_A => X"000000000",
RSTREG_PRIORITY_A => "REGCE",
SRVAL_A => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
READ_WIDTH_B => 18,
WRITE_WIDTH_B => 18,
DOB_REG => 0,
INIT_B => X"000000000",
RSTREG_PRIORITY_B => "REGCE",
SRVAL_B => X"000000000",
WRITE_MODE_B => "WRITE_FIRST",
INIT_FILE => "NONE",
SIM_COLLISION_CHECK => "ALL",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
EN_ECC_READ => FALSE,
EN_ECC_WRITE => FALSE,
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
SIM_DEVICE => "7SERIES",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
INIT_00 => X"{INIT_00}",
INIT_01 => X"{INIT_01}",
INIT_02 => X"{INIT_02}",
INIT_03 => X"{INIT_03}",
INIT_04 => X"{INIT_04}",
INIT_05 => X"{INIT_05}",
INIT_06 => X"{INIT_06}",
INIT_07 => X"{INIT_07}",
INIT_08 => X"{INIT_08}",
INIT_09 => X"{INIT_09}",
INIT_0A => X"{INIT_0A}",
INIT_0B => X"{INIT_0B}",
INIT_0C => X"{INIT_0C}",
INIT_0D => X"{INIT_0D}",
INIT_0E => X"{INIT_0E}",
INIT_0F => X"{INIT_0F}",
INIT_10 => X"{INIT_10}",
INIT_11 => X"{INIT_11}",
INIT_12 => X"{INIT_12}",
INIT_13 => X"{INIT_13}",
INIT_14 => X"{INIT_14}",
INIT_15 => X"{INIT_15}",
INIT_16 => X"{INIT_16}",
INIT_17 => X"{INIT_17}",
INIT_18 => X"{INIT_18}",
INIT_19 => X"{INIT_19}",
INIT_1A => X"{INIT_1A}",
INIT_1B => X"{INIT_1B}",
INIT_1C => X"{INIT_1C}",
INIT_1D => X"{INIT_1D}",
INIT_1E => X"{INIT_1E}",
INIT_1F => X"{INIT_1F}",
INIT_20 => X"{INIT_20}",
INIT_21 => X"{INIT_21}",
INIT_22 => X"{INIT_22}",
INIT_23 => X"{INIT_23}",
INIT_24 => X"{INIT_24}",
INIT_25 => X"{INIT_25}",
INIT_26 => X"{INIT_26}",
INIT_27 => X"{INIT_27}",
INIT_28 => X"{INIT_28}",
INIT_29 => X"{INIT_29}",
INIT_2A => X"{INIT_2A}",
INIT_2B => X"{INIT_2B}",
INIT_2C => X"{INIT_2C}",
INIT_2D => X"{INIT_2D}",
INIT_2E => X"{INIT_2E}",
INIT_2F => X"{INIT_2F}",
INIT_30 => X"{INIT_30}",
INIT_31 => X"{INIT_31}",
INIT_32 => X"{INIT_32}",
INIT_33 => X"{INIT_33}",
INIT_34 => X"{INIT_34}",
INIT_35 => X"{INIT_35}",
INIT_36 => X"{INIT_36}",
INIT_37 => X"{INIT_37}",
INIT_38 => X"{INIT_38}",
INIT_39 => X"{INIT_39}",
INIT_3A => X"{INIT_3A}",
INIT_3B => X"{INIT_3B}",
INIT_3C => X"{INIT_3C}",
INIT_3D => X"{INIT_3D}",
INIT_3E => X"{INIT_3E}",
INIT_3F => X"{INIT_3F}",
INIT_40 => X"{INIT_40}",
INIT_41 => X"{INIT_41}",
INIT_42 => X"{INIT_42}",
INIT_43 => X"{INIT_43}",
INIT_44 => X"{INIT_44}",
INIT_45 => X"{INIT_45}",
INIT_46 => X"{INIT_46}",
INIT_47 => X"{INIT_47}",
INIT_48 => X"{INIT_48}",
INIT_49 => X"{INIT_49}",
INIT_4A => X"{INIT_4A}",
INIT_4B => X"{INIT_4B}",
INIT_4C => X"{INIT_4C}",
INIT_4D => X"{INIT_4D}",
INIT_4E => X"{INIT_4E}",
INIT_4F => X"{INIT_4F}",
INIT_50 => X"{INIT_50}",
INIT_51 => X"{INIT_51}",
INIT_52 => X"{INIT_52}",
INIT_53 => X"{INIT_53}",
INIT_54 => X"{INIT_54}",
INIT_55 => X"{INIT_55}",
INIT_56 => X"{INIT_56}",
INIT_57 => X"{INIT_57}",
INIT_58 => X"{INIT_58}",
INIT_59 => X"{INIT_59}",
INIT_5A => X"{INIT_5A}",
INIT_5B => X"{INIT_5B}",
INIT_5C => X"{INIT_5C}",
INIT_5D => X"{INIT_5D}",
INIT_5E => X"{INIT_5E}",
INIT_5F => X"{INIT_5F}",
INIT_60 => X"{INIT_60}",
INIT_61 => X"{INIT_61}",
INIT_62 => X"{INIT_62}",
INIT_63 => X"{INIT_63}",
INIT_64 => X"{INIT_64}",
INIT_65 => X"{INIT_65}",
INIT_66 => X"{INIT_66}",
INIT_67 => X"{INIT_67}",
INIT_68 => X"{INIT_68}",
INIT_69 => X"{INIT_69}",
INIT_6A => X"{INIT_6A}",
INIT_6B => X"{INIT_6B}",
INIT_6C => X"{INIT_6C}",
INIT_6D => X"{INIT_6D}",
INIT_6E => X"{INIT_6E}",
INIT_6F => X"{INIT_6F}",
INIT_70 => X"{INIT_70}",
INIT_71 => X"{INIT_71}",
INIT_72 => X"{INIT_72}",
INIT_73 => X"{INIT_73}",
INIT_74 => X"{INIT_74}",
INIT_75 => X"{INIT_75}",
INIT_76 => X"{INIT_76}",
INIT_77 => X"{INIT_77}",
INIT_78 => X"{INIT_78}",
INIT_79 => X"{INIT_79}",
INIT_7A => X"{INIT_7A}",
INIT_7B => X"{INIT_7B}",
INIT_7C => X"{INIT_7C}",
INIT_7D => X"{INIT_7D}",
INIT_7E => X"{INIT_7E}",
INIT_7F => X"{INIT_7F}",
INITP_00 => X"{INITP_00}",
INITP_01 => X"{INITP_01}",
INITP_02 => X"{INITP_02}",
INITP_03 => X"{INITP_03}",
INITP_04 => X"{INITP_04}",
INITP_05 => X"{INITP_05}",
INITP_06 => X"{INITP_06}",
INITP_07 => X"{INITP_07}",
INITP_08 => X"{INITP_08}",
INITP_09 => X"{INITP_09}",
INITP_0A => X"{INITP_0A}",
INITP_0B => X"{INITP_0B}",
INITP_0C => X"{INITP_0C}",
INITP_0D => X"{INITP_0D}",
INITP_0E => X"{INITP_0E}",
INITP_0F => X"{INITP_0F}")
port map( ADDRARDADDR => address_a,
ENARDEN => enable,
CLKARDCLK => clk,
DOADO => data_out_a(31 downto 0),
DOPADOP => data_out_a(35 downto 32),
DIADI => data_in_a(31 downto 0),
DIPADIP => data_in_a(35 downto 32),
WEA => "0000",
REGCEAREGCE => '0',
RSTRAMARSTRAM => '0',
RSTREGARSTREG => '0',
ADDRBWRADDR => address_b,
ENBWREN => enable_b,
CLKBWRCLK => clk_b,
DOBDO => data_out_b(31 downto 0),
DOPBDOP => data_out_b(35 downto 32),
DIBDI => data_in_b(31 downto 0),
DIPBDIP => data_in_b(35 downto 32),
WEBWE => we_b,
REGCEB => '0',
RSTRAMB => '0',
RSTREGB => '0',
CASCADEINA => '0',
CASCADEINB => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0');
--
end generate akv7;
--
--
us : if (C_FAMILY = "US") generate
--
address_a(14 downto 0) <= address(10 downto 0) & "1111";
instruction <= data_out_a(33 downto 32) & data_out_a(15 downto 0);
data_in_a <= "00000000000000000000000000000000000" & address(11);
jtag_dout <= data_out_b(33 downto 32) & data_out_b(15 downto 0);
--
no_loader : if (C_JTAG_LOADER_ENABLE = 0) generate
data_in_b <= "00" & data_out_b(33 downto 32) & "0000000000000000" & data_out_b(15 downto 0);
address_b(14 downto 0) <= "111111111111111";
we_b <= "00000000";
enable_b <= '0';
rdl <= '0';
clk_b <= '0';
end generate no_loader;
--
loader : if (C_JTAG_LOADER_ENABLE = 1) generate
data_in_b <= "00" & jtag_din(17 downto 16) & "0000000000000000" & jtag_din(15 downto 0);
address_b(14 downto 0) <= jtag_addr(10 downto 0) & "1111";
we_b <= jtag_we & jtag_we & jtag_we & jtag_we & jtag_we & jtag_we & jtag_we & jtag_we;
enable_b <= jtag_en(0);
rdl <= rdl_bus(0);
clk_b <= jtag_clk;
end generate loader;
--
kcpsm6_rom: RAMB36E2
generic map ( READ_WIDTH_A => 18,
WRITE_WIDTH_A => 18,
DOA_REG => 0,
INIT_A => X"000000000",
RSTREG_PRIORITY_A => "REGCE",
SRVAL_A => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
READ_WIDTH_B => 18,
WRITE_WIDTH_B => 18,
DOB_REG => 0,
INIT_B => X"000000000",
RSTREG_PRIORITY_B => "REGCE",
SRVAL_B => X"000000000",
WRITE_MODE_B => "WRITE_FIRST",
INIT_FILE => "NONE",
SIM_COLLISION_CHECK => "ALL",
EN_ECC_READ => "FALSE",
EN_ECC_WRITE => "FALSE",
CASCADE_ORDER_A => "NONE",
CASCADE_ORDER_B => "NONE",
CLOCK_DOMAINS => "INDEPENDENT",
ENADDRENA => "FALSE",
ENADDRENB => "FALSE",
EN_ECC_PIPE => "FALSE",
RDADDRCHANGEA => "FALSE",
RDADDRCHANGEB => "FALSE",
SLEEP_ASYNC => "FALSE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
INIT_00 => X"{INIT_00}",
INIT_01 => X"{INIT_01}",
INIT_02 => X"{INIT_02}",
INIT_03 => X"{INIT_03}",
INIT_04 => X"{INIT_04}",
INIT_05 => X"{INIT_05}",
INIT_06 => X"{INIT_06}",
INIT_07 => X"{INIT_07}",
INIT_08 => X"{INIT_08}",
INIT_09 => X"{INIT_09}",
INIT_0A => X"{INIT_0A}",
INIT_0B => X"{INIT_0B}",
INIT_0C => X"{INIT_0C}",
INIT_0D => X"{INIT_0D}",
INIT_0E => X"{INIT_0E}",
INIT_0F => X"{INIT_0F}",
INIT_10 => X"{INIT_10}",
INIT_11 => X"{INIT_11}",
INIT_12 => X"{INIT_12}",
INIT_13 => X"{INIT_13}",
INIT_14 => X"{INIT_14}",
INIT_15 => X"{INIT_15}",
INIT_16 => X"{INIT_16}",
INIT_17 => X"{INIT_17}",
INIT_18 => X"{INIT_18}",
INIT_19 => X"{INIT_19}",
INIT_1A => X"{INIT_1A}",
INIT_1B => X"{INIT_1B}",
INIT_1C => X"{INIT_1C}",
INIT_1D => X"{INIT_1D}",
INIT_1E => X"{INIT_1E}",
INIT_1F => X"{INIT_1F}",
INIT_20 => X"{INIT_20}",
INIT_21 => X"{INIT_21}",
INIT_22 => X"{INIT_22}",
INIT_23 => X"{INIT_23}",
INIT_24 => X"{INIT_24}",
INIT_25 => X"{INIT_25}",
INIT_26 => X"{INIT_26}",
INIT_27 => X"{INIT_27}",
INIT_28 => X"{INIT_28}",
INIT_29 => X"{INIT_29}",
INIT_2A => X"{INIT_2A}",
INIT_2B => X"{INIT_2B}",
INIT_2C => X"{INIT_2C}",
INIT_2D => X"{INIT_2D}",
INIT_2E => X"{INIT_2E}",
INIT_2F => X"{INIT_2F}",
INIT_30 => X"{INIT_30}",
INIT_31 => X"{INIT_31}",
INIT_32 => X"{INIT_32}",
INIT_33 => X"{INIT_33}",
INIT_34 => X"{INIT_34}",
INIT_35 => X"{INIT_35}",
INIT_36 => X"{INIT_36}",
INIT_37 => X"{INIT_37}",
INIT_38 => X"{INIT_38}",
INIT_39 => X"{INIT_39}",
INIT_3A => X"{INIT_3A}",
INIT_3B => X"{INIT_3B}",
INIT_3C => X"{INIT_3C}",
INIT_3D => X"{INIT_3D}",
INIT_3E => X"{INIT_3E}",
INIT_3F => X"{INIT_3F}",
INIT_40 => X"{INIT_40}",
INIT_41 => X"{INIT_41}",
INIT_42 => X"{INIT_42}",
INIT_43 => X"{INIT_43}",
INIT_44 => X"{INIT_44}",
INIT_45 => X"{INIT_45}",
INIT_46 => X"{INIT_46}",
INIT_47 => X"{INIT_47}",
INIT_48 => X"{INIT_48}",
INIT_49 => X"{INIT_49}",
INIT_4A => X"{INIT_4A}",
INIT_4B => X"{INIT_4B}",
INIT_4C => X"{INIT_4C}",
INIT_4D => X"{INIT_4D}",
INIT_4E => X"{INIT_4E}",
INIT_4F => X"{INIT_4F}",
INIT_50 => X"{INIT_50}",
INIT_51 => X"{INIT_51}",
INIT_52 => X"{INIT_52}",
INIT_53 => X"{INIT_53}",
INIT_54 => X"{INIT_54}",
INIT_55 => X"{INIT_55}",
INIT_56 => X"{INIT_56}",
INIT_57 => X"{INIT_57}",
INIT_58 => X"{INIT_58}",
INIT_59 => X"{INIT_59}",
INIT_5A => X"{INIT_5A}",
INIT_5B => X"{INIT_5B}",
INIT_5C => X"{INIT_5C}",
INIT_5D => X"{INIT_5D}",
INIT_5E => X"{INIT_5E}",
INIT_5F => X"{INIT_5F}",
INIT_60 => X"{INIT_60}",
INIT_61 => X"{INIT_61}",
INIT_62 => X"{INIT_62}",
INIT_63 => X"{INIT_63}",
INIT_64 => X"{INIT_64}",
INIT_65 => X"{INIT_65}",
INIT_66 => X"{INIT_66}",
INIT_67 => X"{INIT_67}",
INIT_68 => X"{INIT_68}",
INIT_69 => X"{INIT_69}",
INIT_6A => X"{INIT_6A}",
INIT_6B => X"{INIT_6B}",
INIT_6C => X"{INIT_6C}",
INIT_6D => X"{INIT_6D}",
INIT_6E => X"{INIT_6E}",
INIT_6F => X"{INIT_6F}",
INIT_70 => X"{INIT_70}",
INIT_71 => X"{INIT_71}",
INIT_72 => X"{INIT_72}",
INIT_73 => X"{INIT_73}",
INIT_74 => X"{INIT_74}",
INIT_75 => X"{INIT_75}",
INIT_76 => X"{INIT_76}",
INIT_77 => X"{INIT_77}",
INIT_78 => X"{INIT_78}",
INIT_79 => X"{INIT_79}",
INIT_7A => X"{INIT_7A}",
INIT_7B => X"{INIT_7B}",
INIT_7C => X"{INIT_7C}",
INIT_7D => X"{INIT_7D}",
INIT_7E => X"{INIT_7E}",
INIT_7F => X"{INIT_7F}",
INITP_00 => X"{INITP_00}",
INITP_01 => X"{INITP_01}",
INITP_02 => X"{INITP_02}",
INITP_03 => X"{INITP_03}",
INITP_04 => X"{INITP_04}",
INITP_05 => X"{INITP_05}",
INITP_06 => X"{INITP_06}",
INITP_07 => X"{INITP_07}",
INITP_08 => X"{INITP_08}",
INITP_09 => X"{INITP_09}",
INITP_0A => X"{INITP_0A}",
INITP_0B => X"{INITP_0B}",
INITP_0C => X"{INITP_0C}",
INITP_0D => X"{INITP_0D}",
INITP_0E => X"{INITP_0E}",
INITP_0F => X"{INITP_0F}")
port map( ADDRARDADDR => address_a(14 downto 0),
ENARDEN => enable,
CLKARDCLK => clk,
DOUTADOUT => data_out_a(31 downto 0),
DOUTPADOUTP => data_out_a(35 downto 32),
DINADIN => data_in_a(31 downto 0),
DINPADINP => data_in_a(35 downto 32),
WEA => "0000",
REGCEAREGCE => '0',
RSTRAMARSTRAM => '0',
RSTREGARSTREG => '0',
ADDRBWRADDR => address_b(14 downto 0),
ENBWREN => enable_b,
CLKBWRCLK => clk_b,
DOUTBDOUT => data_out_b(31 downto 0),
DOUTPBDOUTP => data_out_b(35 downto 32),
DINBDIN => data_in_b(31 downto 0),
DINPBDINP => data_in_b(35 downto 32),
WEBWE => we_b,
REGCEB => '0',
RSTRAMB => '0',
RSTREGB => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
ADDRENA => '1',
ADDRENB => '1',
CASDIMUXA => '0',
CASDIMUXB => '0',
CASDINA => "00000000000000000000000000000000",
CASDINB => "00000000000000000000000000000000",
CASDINPA => "0000",
CASDINPB => "0000",
CASDOMUXA => '0',
CASDOMUXB => '0',
CASDOMUXEN_A => '1',
CASDOMUXEN_B => '1',
CASINDBITERR => '0',
CASINSBITERR => '0',
CASOREGIMUXA => '0',
CASOREGIMUXB => '0',
CASOREGIMUXEN_A => '0',
CASOREGIMUXEN_B => '0',
ECCPIPECE => '0',
SLEEP => '0');
--
end generate us;
--
end generate ram_2k_generate;
--
--
ram_4k_generate : if (C_RAM_SIZE_KWORDS = 4) generate
--
--
akv7 : if (C_FAMILY = "7S") generate
--
address_a <= '1' & address(11 downto 0) & "111";
instruction <= data_out_a_h(32) & data_out_a_h(7 downto 0) & data_out_a_l(32) & data_out_a_l(7 downto 0);
data_in_a <= "000000000000000000000000000000000000";
jtag_dout <= data_out_b_h(32) & data_out_b_h(7 downto 0) & data_out_b_l(32) & data_out_b_l(7 downto 0);
--
no_loader : if (C_JTAG_LOADER_ENABLE = 0) generate
data_in_b_l <= "000" & data_out_b_l(32) & "000000000000000000000000" & data_out_b_l(7 downto 0);
data_in_b_h <= "000" & data_out_b_h(32) & "000000000000000000000000" & data_out_b_h(7 downto 0);
address_b <= "1111111111111111";
we_b <= "00000000";
enable_b <= '0';
rdl <= '0';
clk_b <= '0';
end generate no_loader;
--
loader : if (C_JTAG_LOADER_ENABLE = 1) generate
data_in_b_h <= "000" & jtag_din(17) & "000000000000000000000000" & jtag_din(16 downto 9);
data_in_b_l <= "000" & jtag_din(8) & "000000000000000000000000" & jtag_din(7 downto 0);
address_b <= '1' & jtag_addr(11 downto 0) & "111";
we_b <= jtag_we & jtag_we & jtag_we & jtag_we & jtag_we & jtag_we & jtag_we & jtag_we;
enable_b <= jtag_en(0);
rdl <= rdl_bus(0);
clk_b <= jtag_clk;
end generate loader;
--
kcpsm6_rom_l: RAMB36E1
generic map ( READ_WIDTH_A => 9,
WRITE_WIDTH_A => 9,
DOA_REG => 0,
INIT_A => X"000000000",
RSTREG_PRIORITY_A => "REGCE",
SRVAL_A => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
READ_WIDTH_B => 9,
WRITE_WIDTH_B => 9,
DOB_REG => 0,
INIT_B => X"000000000",
RSTREG_PRIORITY_B => "REGCE",
SRVAL_B => X"000000000",
WRITE_MODE_B => "WRITE_FIRST",
INIT_FILE => "NONE",
SIM_COLLISION_CHECK => "ALL",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
EN_ECC_READ => FALSE,
EN_ECC_WRITE => FALSE,
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
SIM_DEVICE => "7SERIES",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
INIT_00 => X"{[8:0]_INIT_00}",
INIT_01 => X"{[8:0]_INIT_01}",
INIT_02 => X"{[8:0]_INIT_02}",
INIT_03 => X"{[8:0]_INIT_03}",
INIT_04 => X"{[8:0]_INIT_04}",
INIT_05 => X"{[8:0]_INIT_05}",
INIT_06 => X"{[8:0]_INIT_06}",
INIT_07 => X"{[8:0]_INIT_07}",
INIT_08 => X"{[8:0]_INIT_08}",
INIT_09 => X"{[8:0]_INIT_09}",
INIT_0A => X"{[8:0]_INIT_0A}",
INIT_0B => X"{[8:0]_INIT_0B}",
INIT_0C => X"{[8:0]_INIT_0C}",
INIT_0D => X"{[8:0]_INIT_0D}",
INIT_0E => X"{[8:0]_INIT_0E}",
INIT_0F => X"{[8:0]_INIT_0F}",
INIT_10 => X"{[8:0]_INIT_10}",
INIT_11 => X"{[8:0]_INIT_11}",
INIT_12 => X"{[8:0]_INIT_12}",
INIT_13 => X"{[8:0]_INIT_13}",
INIT_14 => X"{[8:0]_INIT_14}",
INIT_15 => X"{[8:0]_INIT_15}",
INIT_16 => X"{[8:0]_INIT_16}",
INIT_17 => X"{[8:0]_INIT_17}",
INIT_18 => X"{[8:0]_INIT_18}",
INIT_19 => X"{[8:0]_INIT_19}",
INIT_1A => X"{[8:0]_INIT_1A}",
INIT_1B => X"{[8:0]_INIT_1B}",
INIT_1C => X"{[8:0]_INIT_1C}",
INIT_1D => X"{[8:0]_INIT_1D}",
INIT_1E => X"{[8:0]_INIT_1E}",
INIT_1F => X"{[8:0]_INIT_1F}",
INIT_20 => X"{[8:0]_INIT_20}",
INIT_21 => X"{[8:0]_INIT_21}",
INIT_22 => X"{[8:0]_INIT_22}",
INIT_23 => X"{[8:0]_INIT_23}",
INIT_24 => X"{[8:0]_INIT_24}",
INIT_25 => X"{[8:0]_INIT_25}",
INIT_26 => X"{[8:0]_INIT_26}",
INIT_27 => X"{[8:0]_INIT_27}",
INIT_28 => X"{[8:0]_INIT_28}",
INIT_29 => X"{[8:0]_INIT_29}",
INIT_2A => X"{[8:0]_INIT_2A}",
INIT_2B => X"{[8:0]_INIT_2B}",
INIT_2C => X"{[8:0]_INIT_2C}",
INIT_2D => X"{[8:0]_INIT_2D}",
INIT_2E => X"{[8:0]_INIT_2E}",
INIT_2F => X"{[8:0]_INIT_2F}",
INIT_30 => X"{[8:0]_INIT_30}",
INIT_31 => X"{[8:0]_INIT_31}",
INIT_32 => X"{[8:0]_INIT_32}",
INIT_33 => X"{[8:0]_INIT_33}",
INIT_34 => X"{[8:0]_INIT_34}",
INIT_35 => X"{[8:0]_INIT_35}",
INIT_36 => X"{[8:0]_INIT_36}",
INIT_37 => X"{[8:0]_INIT_37}",
INIT_38 => X"{[8:0]_INIT_38}",
INIT_39 => X"{[8:0]_INIT_39}",
INIT_3A => X"{[8:0]_INIT_3A}",
INIT_3B => X"{[8:0]_INIT_3B}",
INIT_3C => X"{[8:0]_INIT_3C}",
INIT_3D => X"{[8:0]_INIT_3D}",
INIT_3E => X"{[8:0]_INIT_3E}",
INIT_3F => X"{[8:0]_INIT_3F}",
INIT_40 => X"{[8:0]_INIT_40}",
INIT_41 => X"{[8:0]_INIT_41}",
INIT_42 => X"{[8:0]_INIT_42}",
INIT_43 => X"{[8:0]_INIT_43}",
INIT_44 => X"{[8:0]_INIT_44}",
INIT_45 => X"{[8:0]_INIT_45}",
INIT_46 => X"{[8:0]_INIT_46}",
INIT_47 => X"{[8:0]_INIT_47}",
INIT_48 => X"{[8:0]_INIT_48}",
INIT_49 => X"{[8:0]_INIT_49}",
INIT_4A => X"{[8:0]_INIT_4A}",
INIT_4B => X"{[8:0]_INIT_4B}",
INIT_4C => X"{[8:0]_INIT_4C}",
INIT_4D => X"{[8:0]_INIT_4D}",
INIT_4E => X"{[8:0]_INIT_4E}",
INIT_4F => X"{[8:0]_INIT_4F}",
INIT_50 => X"{[8:0]_INIT_50}",
INIT_51 => X"{[8:0]_INIT_51}",
INIT_52 => X"{[8:0]_INIT_52}",
INIT_53 => X"{[8:0]_INIT_53}",
INIT_54 => X"{[8:0]_INIT_54}",
INIT_55 => X"{[8:0]_INIT_55}",
INIT_56 => X"{[8:0]_INIT_56}",
INIT_57 => X"{[8:0]_INIT_57}",
INIT_58 => X"{[8:0]_INIT_58}",
INIT_59 => X"{[8:0]_INIT_59}",
INIT_5A => X"{[8:0]_INIT_5A}",
INIT_5B => X"{[8:0]_INIT_5B}",
INIT_5C => X"{[8:0]_INIT_5C}",
INIT_5D => X"{[8:0]_INIT_5D}",
INIT_5E => X"{[8:0]_INIT_5E}",
INIT_5F => X"{[8:0]_INIT_5F}",
INIT_60 => X"{[8:0]_INIT_60}",
INIT_61 => X"{[8:0]_INIT_61}",
INIT_62 => X"{[8:0]_INIT_62}",
INIT_63 => X"{[8:0]_INIT_63}",
INIT_64 => X"{[8:0]_INIT_64}",
INIT_65 => X"{[8:0]_INIT_65}",
INIT_66 => X"{[8:0]_INIT_66}",
INIT_67 => X"{[8:0]_INIT_67}",
INIT_68 => X"{[8:0]_INIT_68}",
INIT_69 => X"{[8:0]_INIT_69}",
INIT_6A => X"{[8:0]_INIT_6A}",
INIT_6B => X"{[8:0]_INIT_6B}",
INIT_6C => X"{[8:0]_INIT_6C}",
INIT_6D => X"{[8:0]_INIT_6D}",
INIT_6E => X"{[8:0]_INIT_6E}",
INIT_6F => X"{[8:0]_INIT_6F}",
INIT_70 => X"{[8:0]_INIT_70}",
INIT_71 => X"{[8:0]_INIT_71}",
INIT_72 => X"{[8:0]_INIT_72}",
INIT_73 => X"{[8:0]_INIT_73}",
INIT_74 => X"{[8:0]_INIT_74}",
INIT_75 => X"{[8:0]_INIT_75}",
INIT_76 => X"{[8:0]_INIT_76}",
INIT_77 => X"{[8:0]_INIT_77}",
INIT_78 => X"{[8:0]_INIT_78}",
INIT_79 => X"{[8:0]_INIT_79}",
INIT_7A => X"{[8:0]_INIT_7A}",
INIT_7B => X"{[8:0]_INIT_7B}",
INIT_7C => X"{[8:0]_INIT_7C}",
INIT_7D => X"{[8:0]_INIT_7D}",
INIT_7E => X"{[8:0]_INIT_7E}",
INIT_7F => X"{[8:0]_INIT_7F}",
INITP_00 => X"{[8:0]_INITP_00}",
INITP_01 => X"{[8:0]_INITP_01}",
INITP_02 => X"{[8:0]_INITP_02}",
INITP_03 => X"{[8:0]_INITP_03}",
INITP_04 => X"{[8:0]_INITP_04}",
INITP_05 => X"{[8:0]_INITP_05}",
INITP_06 => X"{[8:0]_INITP_06}",
INITP_07 => X"{[8:0]_INITP_07}",
INITP_08 => X"{[8:0]_INITP_08}",
INITP_09 => X"{[8:0]_INITP_09}",
INITP_0A => X"{[8:0]_INITP_0A}",
INITP_0B => X"{[8:0]_INITP_0B}",
INITP_0C => X"{[8:0]_INITP_0C}",
INITP_0D => X"{[8:0]_INITP_0D}",
INITP_0E => X"{[8:0]_INITP_0E}",
INITP_0F => X"{[8:0]_INITP_0F}")
port map( ADDRARDADDR => address_a,
ENARDEN => enable,
CLKARDCLK => clk,
DOADO => data_out_a_l(31 downto 0),
DOPADOP => data_out_a_l(35 downto 32),
DIADI => data_in_a(31 downto 0),
DIPADIP => data_in_a(35 downto 32),
WEA => "0000",
REGCEAREGCE => '0',
RSTRAMARSTRAM => '0',
RSTREGARSTREG => '0',
ADDRBWRADDR => address_b,
ENBWREN => enable_b,
CLKBWRCLK => clk_b,
DOBDO => data_out_b_l(31 downto 0),
DOPBDOP => data_out_b_l(35 downto 32),
DIBDI => data_in_b_l(31 downto 0),
DIPBDIP => data_in_b_l(35 downto 32),
WEBWE => we_b,
REGCEB => '0',
RSTRAMB => '0',
RSTREGB => '0',
CASCADEINA => '0',
CASCADEINB => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0');
--
kcpsm6_rom_h: RAMB36E1
generic map ( READ_WIDTH_A => 9,
WRITE_WIDTH_A => 9,
DOA_REG => 0,
INIT_A => X"000000000",
RSTREG_PRIORITY_A => "REGCE",
SRVAL_A => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
READ_WIDTH_B => 9,
WRITE_WIDTH_B => 9,
DOB_REG => 0,
INIT_B => X"000000000",
RSTREG_PRIORITY_B => "REGCE",
SRVAL_B => X"000000000",
WRITE_MODE_B => "WRITE_FIRST",
INIT_FILE => "NONE",
SIM_COLLISION_CHECK => "ALL",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
EN_ECC_READ => FALSE,
EN_ECC_WRITE => FALSE,
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
SIM_DEVICE => "7SERIES",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
INIT_00 => X"{[17:9]_INIT_00}",
INIT_01 => X"{[17:9]_INIT_01}",
INIT_02 => X"{[17:9]_INIT_02}",
INIT_03 => X"{[17:9]_INIT_03}",
INIT_04 => X"{[17:9]_INIT_04}",
INIT_05 => X"{[17:9]_INIT_05}",
INIT_06 => X"{[17:9]_INIT_06}",
INIT_07 => X"{[17:9]_INIT_07}",
INIT_08 => X"{[17:9]_INIT_08}",
INIT_09 => X"{[17:9]_INIT_09}",
INIT_0A => X"{[17:9]_INIT_0A}",
INIT_0B => X"{[17:9]_INIT_0B}",
INIT_0C => X"{[17:9]_INIT_0C}",
INIT_0D => X"{[17:9]_INIT_0D}",
INIT_0E => X"{[17:9]_INIT_0E}",
INIT_0F => X"{[17:9]_INIT_0F}",
INIT_10 => X"{[17:9]_INIT_10}",
INIT_11 => X"{[17:9]_INIT_11}",
INIT_12 => X"{[17:9]_INIT_12}",
INIT_13 => X"{[17:9]_INIT_13}",
INIT_14 => X"{[17:9]_INIT_14}",
INIT_15 => X"{[17:9]_INIT_15}",
INIT_16 => X"{[17:9]_INIT_16}",
INIT_17 => X"{[17:9]_INIT_17}",
INIT_18 => X"{[17:9]_INIT_18}",
INIT_19 => X"{[17:9]_INIT_19}",
INIT_1A => X"{[17:9]_INIT_1A}",
INIT_1B => X"{[17:9]_INIT_1B}",
INIT_1C => X"{[17:9]_INIT_1C}",
INIT_1D => X"{[17:9]_INIT_1D}",
INIT_1E => X"{[17:9]_INIT_1E}",
INIT_1F => X"{[17:9]_INIT_1F}",
INIT_20 => X"{[17:9]_INIT_20}",
INIT_21 => X"{[17:9]_INIT_21}",
INIT_22 => X"{[17:9]_INIT_22}",
INIT_23 => X"{[17:9]_INIT_23}",
INIT_24 => X"{[17:9]_INIT_24}",
INIT_25 => X"{[17:9]_INIT_25}",
INIT_26 => X"{[17:9]_INIT_26}",
INIT_27 => X"{[17:9]_INIT_27}",
INIT_28 => X"{[17:9]_INIT_28}",
INIT_29 => X"{[17:9]_INIT_29}",
INIT_2A => X"{[17:9]_INIT_2A}",
INIT_2B => X"{[17:9]_INIT_2B}",
INIT_2C => X"{[17:9]_INIT_2C}",
INIT_2D => X"{[17:9]_INIT_2D}",
INIT_2E => X"{[17:9]_INIT_2E}",
INIT_2F => X"{[17:9]_INIT_2F}",
INIT_30 => X"{[17:9]_INIT_30}",
INIT_31 => X"{[17:9]_INIT_31}",
INIT_32 => X"{[17:9]_INIT_32}",
INIT_33 => X"{[17:9]_INIT_33}",
INIT_34 => X"{[17:9]_INIT_34}",
INIT_35 => X"{[17:9]_INIT_35}",
INIT_36 => X"{[17:9]_INIT_36}",
INIT_37 => X"{[17:9]_INIT_37}",
INIT_38 => X"{[17:9]_INIT_38}",
INIT_39 => X"{[17:9]_INIT_39}",
INIT_3A => X"{[17:9]_INIT_3A}",
INIT_3B => X"{[17:9]_INIT_3B}",
INIT_3C => X"{[17:9]_INIT_3C}",
INIT_3D => X"{[17:9]_INIT_3D}",
INIT_3E => X"{[17:9]_INIT_3E}",
INIT_3F => X"{[17:9]_INIT_3F}",
INIT_40 => X"{[17:9]_INIT_40}",
INIT_41 => X"{[17:9]_INIT_41}",
INIT_42 => X"{[17:9]_INIT_42}",
INIT_43 => X"{[17:9]_INIT_43}",
INIT_44 => X"{[17:9]_INIT_44}",
INIT_45 => X"{[17:9]_INIT_45}",
INIT_46 => X"{[17:9]_INIT_46}",
INIT_47 => X"{[17:9]_INIT_47}",
INIT_48 => X"{[17:9]_INIT_48}",
INIT_49 => X"{[17:9]_INIT_49}",
INIT_4A => X"{[17:9]_INIT_4A}",
INIT_4B => X"{[17:9]_INIT_4B}",
INIT_4C => X"{[17:9]_INIT_4C}",
INIT_4D => X"{[17:9]_INIT_4D}",
INIT_4E => X"{[17:9]_INIT_4E}",
INIT_4F => X"{[17:9]_INIT_4F}",
INIT_50 => X"{[17:9]_INIT_50}",
INIT_51 => X"{[17:9]_INIT_51}",
INIT_52 => X"{[17:9]_INIT_52}",
INIT_53 => X"{[17:9]_INIT_53}",
INIT_54 => X"{[17:9]_INIT_54}",
INIT_55 => X"{[17:9]_INIT_55}",
INIT_56 => X"{[17:9]_INIT_56}",
INIT_57 => X"{[17:9]_INIT_57}",
INIT_58 => X"{[17:9]_INIT_58}",
INIT_59 => X"{[17:9]_INIT_59}",
INIT_5A => X"{[17:9]_INIT_5A}",
INIT_5B => X"{[17:9]_INIT_5B}",
INIT_5C => X"{[17:9]_INIT_5C}",
INIT_5D => X"{[17:9]_INIT_5D}",
INIT_5E => X"{[17:9]_INIT_5E}",
INIT_5F => X"{[17:9]_INIT_5F}",
INIT_60 => X"{[17:9]_INIT_60}",
INIT_61 => X"{[17:9]_INIT_61}",
INIT_62 => X"{[17:9]_INIT_62}",
INIT_63 => X"{[17:9]_INIT_63}",
INIT_64 => X"{[17:9]_INIT_64}",
INIT_65 => X"{[17:9]_INIT_65}",
INIT_66 => X"{[17:9]_INIT_66}",
INIT_67 => X"{[17:9]_INIT_67}",
INIT_68 => X"{[17:9]_INIT_68}",
INIT_69 => X"{[17:9]_INIT_69}",
INIT_6A => X"{[17:9]_INIT_6A}",
INIT_6B => X"{[17:9]_INIT_6B}",
INIT_6C => X"{[17:9]_INIT_6C}",
INIT_6D => X"{[17:9]_INIT_6D}",
INIT_6E => X"{[17:9]_INIT_6E}",
INIT_6F => X"{[17:9]_INIT_6F}",
INIT_70 => X"{[17:9]_INIT_70}",
INIT_71 => X"{[17:9]_INIT_71}",
INIT_72 => X"{[17:9]_INIT_72}",
INIT_73 => X"{[17:9]_INIT_73}",
INIT_74 => X"{[17:9]_INIT_74}",
INIT_75 => X"{[17:9]_INIT_75}",
INIT_76 => X"{[17:9]_INIT_76}",
INIT_77 => X"{[17:9]_INIT_77}",
INIT_78 => X"{[17:9]_INIT_78}",
INIT_79 => X"{[17:9]_INIT_79}",
INIT_7A => X"{[17:9]_INIT_7A}",
INIT_7B => X"{[17:9]_INIT_7B}",
INIT_7C => X"{[17:9]_INIT_7C}",
INIT_7D => X"{[17:9]_INIT_7D}",
INIT_7E => X"{[17:9]_INIT_7E}",
INIT_7F => X"{[17:9]_INIT_7F}",
INITP_00 => X"{[17:9]_INITP_00}",
INITP_01 => X"{[17:9]_INITP_01}",
INITP_02 => X"{[17:9]_INITP_02}",
INITP_03 => X"{[17:9]_INITP_03}",
INITP_04 => X"{[17:9]_INITP_04}",
INITP_05 => X"{[17:9]_INITP_05}",
INITP_06 => X"{[17:9]_INITP_06}",
INITP_07 => X"{[17:9]_INITP_07}",
INITP_08 => X"{[17:9]_INITP_08}",
INITP_09 => X"{[17:9]_INITP_09}",
INITP_0A => X"{[17:9]_INITP_0A}",
INITP_0B => X"{[17:9]_INITP_0B}",
INITP_0C => X"{[17:9]_INITP_0C}",
INITP_0D => X"{[17:9]_INITP_0D}",
INITP_0E => X"{[17:9]_INITP_0E}",
INITP_0F => X"{[17:9]_INITP_0F}")
port map( ADDRARDADDR => address_a,
ENARDEN => enable,
CLKARDCLK => clk,
DOADO => data_out_a_h(31 downto 0),
DOPADOP => data_out_a_h(35 downto 32),
DIADI => data_in_a(31 downto 0),
DIPADIP => data_in_a(35 downto 32),
WEA => "0000",
REGCEAREGCE => '0',
RSTRAMARSTRAM => '0',
RSTREGARSTREG => '0',
ADDRBWRADDR => address_b,
ENBWREN => enable_b,
CLKBWRCLK => clk_b,
DOBDO => data_out_b_h(31 downto 0),
DOPBDOP => data_out_b_h(35 downto 32),
DIBDI => data_in_b_h(31 downto 0),
DIPBDIP => data_in_b_h(35 downto 32),
WEBWE => we_b,
REGCEB => '0',
RSTRAMB => '0',
RSTREGB => '0',
CASCADEINA => '0',
CASCADEINB => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0');
--
end generate akv7;
--
--
us : if (C_FAMILY = "US") generate
--
address_a(14 downto 0) <= address(11 downto 0) & "111";
instruction <= data_out_a_h(32) & data_out_a_h(7 downto 0) & data_out_a_l(32) & data_out_a_l(7 downto 0);
data_in_a <= "000000000000000000000000000000000000";
jtag_dout <= data_out_b_h(32) & data_out_b_h(7 downto 0) & data_out_b_l(32) & data_out_b_l(7 downto 0);
--
no_loader : if (C_JTAG_LOADER_ENABLE = 0) generate
data_in_b_l <= "000" & data_out_b_l(32) & "000000000000000000000000" & data_out_b_l(7 downto 0);
data_in_b_h <= "000" & data_out_b_h(32) & "000000000000000000000000" & data_out_b_h(7 downto 0);
address_b(14 downto 0) <= "111111111111111";
we_b <= "00000000";
enable_b <= '0';
rdl <= '0';
clk_b <= '0';
end generate no_loader;
--
loader : if (C_JTAG_LOADER_ENABLE = 1) generate
data_in_b_h <= "000" & jtag_din(17) & "000000000000000000000000" & jtag_din(16 downto 9);
data_in_b_l <= "000" & jtag_din(8) & "000000000000000000000000" & jtag_din(7 downto 0);
address_b(14 downto 0) <= jtag_addr(11 downto 0) & "111";
we_b <= jtag_we & jtag_we & jtag_we & jtag_we & jtag_we & jtag_we & jtag_we & jtag_we;
enable_b <= jtag_en(0);
rdl <= rdl_bus(0);
clk_b <= jtag_clk;
end generate loader;
--
kcpsm6_rom_l: RAMB36E2
generic map ( READ_WIDTH_A => 9,
WRITE_WIDTH_A => 9,
DOA_REG => 0,
INIT_A => X"000000000",
RSTREG_PRIORITY_A => "REGCE",
SRVAL_A => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
READ_WIDTH_B => 9,
WRITE_WIDTH_B => 9,
DOB_REG => 0,
INIT_B => X"000000000",
RSTREG_PRIORITY_B => "REGCE",
SRVAL_B => X"000000000",
WRITE_MODE_B => "WRITE_FIRST",
INIT_FILE => "NONE",
SIM_COLLISION_CHECK => "ALL",
EN_ECC_READ => "FALSE",
EN_ECC_WRITE => "FALSE",
CASCADE_ORDER_A => "NONE",
CASCADE_ORDER_B => "NONE",
CLOCK_DOMAINS => "INDEPENDENT",
ENADDRENA => "FALSE",
ENADDRENB => "FALSE",
EN_ECC_PIPE => "FALSE",
RDADDRCHANGEA => "FALSE",
RDADDRCHANGEB => "FALSE",
SLEEP_ASYNC => "FALSE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
INIT_00 => X"{[8:0]_INIT_00}",
INIT_01 => X"{[8:0]_INIT_01}",
INIT_02 => X"{[8:0]_INIT_02}",
INIT_03 => X"{[8:0]_INIT_03}",
INIT_04 => X"{[8:0]_INIT_04}",
INIT_05 => X"{[8:0]_INIT_05}",
INIT_06 => X"{[8:0]_INIT_06}",
INIT_07 => X"{[8:0]_INIT_07}",
INIT_08 => X"{[8:0]_INIT_08}",
INIT_09 => X"{[8:0]_INIT_09}",
INIT_0A => X"{[8:0]_INIT_0A}",
INIT_0B => X"{[8:0]_INIT_0B}",
INIT_0C => X"{[8:0]_INIT_0C}",
INIT_0D => X"{[8:0]_INIT_0D}",
INIT_0E => X"{[8:0]_INIT_0E}",
INIT_0F => X"{[8:0]_INIT_0F}",
INIT_10 => X"{[8:0]_INIT_10}",
INIT_11 => X"{[8:0]_INIT_11}",
INIT_12 => X"{[8:0]_INIT_12}",
INIT_13 => X"{[8:0]_INIT_13}",
INIT_14 => X"{[8:0]_INIT_14}",
INIT_15 => X"{[8:0]_INIT_15}",
INIT_16 => X"{[8:0]_INIT_16}",
INIT_17 => X"{[8:0]_INIT_17}",
INIT_18 => X"{[8:0]_INIT_18}",
INIT_19 => X"{[8:0]_INIT_19}",
INIT_1A => X"{[8:0]_INIT_1A}",
INIT_1B => X"{[8:0]_INIT_1B}",
INIT_1C => X"{[8:0]_INIT_1C}",
INIT_1D => X"{[8:0]_INIT_1D}",
INIT_1E => X"{[8:0]_INIT_1E}",
INIT_1F => X"{[8:0]_INIT_1F}",
INIT_20 => X"{[8:0]_INIT_20}",
INIT_21 => X"{[8:0]_INIT_21}",
INIT_22 => X"{[8:0]_INIT_22}",
INIT_23 => X"{[8:0]_INIT_23}",
INIT_24 => X"{[8:0]_INIT_24}",
INIT_25 => X"{[8:0]_INIT_25}",
INIT_26 => X"{[8:0]_INIT_26}",
INIT_27 => X"{[8:0]_INIT_27}",
INIT_28 => X"{[8:0]_INIT_28}",
INIT_29 => X"{[8:0]_INIT_29}",
INIT_2A => X"{[8:0]_INIT_2A}",
INIT_2B => X"{[8:0]_INIT_2B}",
INIT_2C => X"{[8:0]_INIT_2C}",
INIT_2D => X"{[8:0]_INIT_2D}",
INIT_2E => X"{[8:0]_INIT_2E}",
INIT_2F => X"{[8:0]_INIT_2F}",
INIT_30 => X"{[8:0]_INIT_30}",
INIT_31 => X"{[8:0]_INIT_31}",
INIT_32 => X"{[8:0]_INIT_32}",
INIT_33 => X"{[8:0]_INIT_33}",
INIT_34 => X"{[8:0]_INIT_34}",
INIT_35 => X"{[8:0]_INIT_35}",
INIT_36 => X"{[8:0]_INIT_36}",
INIT_37 => X"{[8:0]_INIT_37}",
INIT_38 => X"{[8:0]_INIT_38}",
INIT_39 => X"{[8:0]_INIT_39}",
INIT_3A => X"{[8:0]_INIT_3A}",
INIT_3B => X"{[8:0]_INIT_3B}",
INIT_3C => X"{[8:0]_INIT_3C}",
INIT_3D => X"{[8:0]_INIT_3D}",
INIT_3E => X"{[8:0]_INIT_3E}",
INIT_3F => X"{[8:0]_INIT_3F}",
INIT_40 => X"{[8:0]_INIT_40}",
INIT_41 => X"{[8:0]_INIT_41}",
INIT_42 => X"{[8:0]_INIT_42}",
INIT_43 => X"{[8:0]_INIT_43}",
INIT_44 => X"{[8:0]_INIT_44}",
INIT_45 => X"{[8:0]_INIT_45}",
INIT_46 => X"{[8:0]_INIT_46}",
INIT_47 => X"{[8:0]_INIT_47}",
INIT_48 => X"{[8:0]_INIT_48}",
INIT_49 => X"{[8:0]_INIT_49}",
INIT_4A => X"{[8:0]_INIT_4A}",
INIT_4B => X"{[8:0]_INIT_4B}",
INIT_4C => X"{[8:0]_INIT_4C}",
INIT_4D => X"{[8:0]_INIT_4D}",
INIT_4E => X"{[8:0]_INIT_4E}",
INIT_4F => X"{[8:0]_INIT_4F}",
INIT_50 => X"{[8:0]_INIT_50}",
INIT_51 => X"{[8:0]_INIT_51}",
INIT_52 => X"{[8:0]_INIT_52}",
INIT_53 => X"{[8:0]_INIT_53}",
INIT_54 => X"{[8:0]_INIT_54}",
INIT_55 => X"{[8:0]_INIT_55}",
INIT_56 => X"{[8:0]_INIT_56}",
INIT_57 => X"{[8:0]_INIT_57}",
INIT_58 => X"{[8:0]_INIT_58}",
INIT_59 => X"{[8:0]_INIT_59}",
INIT_5A => X"{[8:0]_INIT_5A}",
INIT_5B => X"{[8:0]_INIT_5B}",
INIT_5C => X"{[8:0]_INIT_5C}",
INIT_5D => X"{[8:0]_INIT_5D}",
INIT_5E => X"{[8:0]_INIT_5E}",
INIT_5F => X"{[8:0]_INIT_5F}",
INIT_60 => X"{[8:0]_INIT_60}",
INIT_61 => X"{[8:0]_INIT_61}",
INIT_62 => X"{[8:0]_INIT_62}",
INIT_63 => X"{[8:0]_INIT_63}",
INIT_64 => X"{[8:0]_INIT_64}",
INIT_65 => X"{[8:0]_INIT_65}",
INIT_66 => X"{[8:0]_INIT_66}",
INIT_67 => X"{[8:0]_INIT_67}",
INIT_68 => X"{[8:0]_INIT_68}",
INIT_69 => X"{[8:0]_INIT_69}",
INIT_6A => X"{[8:0]_INIT_6A}",
INIT_6B => X"{[8:0]_INIT_6B}",
INIT_6C => X"{[8:0]_INIT_6C}",
INIT_6D => X"{[8:0]_INIT_6D}",
INIT_6E => X"{[8:0]_INIT_6E}",
INIT_6F => X"{[8:0]_INIT_6F}",
INIT_70 => X"{[8:0]_INIT_70}",
INIT_71 => X"{[8:0]_INIT_71}",
INIT_72 => X"{[8:0]_INIT_72}",
INIT_73 => X"{[8:0]_INIT_73}",
INIT_74 => X"{[8:0]_INIT_74}",
INIT_75 => X"{[8:0]_INIT_75}",
INIT_76 => X"{[8:0]_INIT_76}",
INIT_77 => X"{[8:0]_INIT_77}",
INIT_78 => X"{[8:0]_INIT_78}",
INIT_79 => X"{[8:0]_INIT_79}",
INIT_7A => X"{[8:0]_INIT_7A}",
INIT_7B => X"{[8:0]_INIT_7B}",
INIT_7C => X"{[8:0]_INIT_7C}",
INIT_7D => X"{[8:0]_INIT_7D}",
INIT_7E => X"{[8:0]_INIT_7E}",
INIT_7F => X"{[8:0]_INIT_7F}",
INITP_00 => X"{[8:0]_INITP_00}",
INITP_01 => X"{[8:0]_INITP_01}",
INITP_02 => X"{[8:0]_INITP_02}",
INITP_03 => X"{[8:0]_INITP_03}",
INITP_04 => X"{[8:0]_INITP_04}",
INITP_05 => X"{[8:0]_INITP_05}",
INITP_06 => X"{[8:0]_INITP_06}",
INITP_07 => X"{[8:0]_INITP_07}",
INITP_08 => X"{[8:0]_INITP_08}",
INITP_09 => X"{[8:0]_INITP_09}",
INITP_0A => X"{[8:0]_INITP_0A}",
INITP_0B => X"{[8:0]_INITP_0B}",
INITP_0C => X"{[8:0]_INITP_0C}",
INITP_0D => X"{[8:0]_INITP_0D}",
INITP_0E => X"{[8:0]_INITP_0E}",
INITP_0F => X"{[8:0]_INITP_0F}")
port map( ADDRARDADDR => address_a(14 downto 0),
ENARDEN => enable,
CLKARDCLK => clk,
DOUTADOUT => data_out_a_l(31 downto 0),
DOUTPADOUTP => data_out_a_l(35 downto 32),
DINADIN => data_in_a(31 downto 0),
DINPADINP => data_in_a(35 downto 32),
WEA => "0000",
REGCEAREGCE => '0',
RSTRAMARSTRAM => '0',
RSTREGARSTREG => '0',
ADDRBWRADDR => address_b(14 downto 0),
ENBWREN => enable_b,
CLKBWRCLK => clk_b,
DOUTBDOUT => data_out_b_l(31 downto 0),
DOUTPBDOUTP => data_out_b_l(35 downto 32),
DINBDIN => data_in_b_l(31 downto 0),
DINPBDINP => data_in_b_l(35 downto 32),
WEBWE => we_b,
REGCEB => '0',
RSTRAMB => '0',
RSTREGB => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
ADDRENA => '1',
ADDRENB => '1',
CASDIMUXA => '0',
CASDIMUXB => '0',
CASDINA => "00000000000000000000000000000000",
CASDINB => "00000000000000000000000000000000",
CASDINPA => "0000",
CASDINPB => "0000",
CASDOMUXA => '0',
CASDOMUXB => '0',
CASDOMUXEN_A => '1',
CASDOMUXEN_B => '1',
CASINDBITERR => '0',
CASINSBITERR => '0',
CASOREGIMUXA => '0',
CASOREGIMUXB => '0',
CASOREGIMUXEN_A => '0',
CASOREGIMUXEN_B => '0',
ECCPIPECE => '0',
SLEEP => '0');
--
kcpsm6_rom_h: RAMB36E2
generic map ( READ_WIDTH_A => 9,
WRITE_WIDTH_A => 9,
DOA_REG => 0,
INIT_A => X"000000000",
RSTREG_PRIORITY_A => "REGCE",
SRVAL_A => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
READ_WIDTH_B => 9,
WRITE_WIDTH_B => 9,
DOB_REG => 0,
INIT_B => X"000000000",
RSTREG_PRIORITY_B => "REGCE",
SRVAL_B => X"000000000",
WRITE_MODE_B => "WRITE_FIRST",
INIT_FILE => "NONE",
SIM_COLLISION_CHECK => "ALL",
EN_ECC_READ => "FALSE",
EN_ECC_WRITE => "FALSE",
CASCADE_ORDER_A => "NONE",
CASCADE_ORDER_B => "NONE",
CLOCK_DOMAINS => "INDEPENDENT",
ENADDRENA => "FALSE",
ENADDRENB => "FALSE",
EN_ECC_PIPE => "FALSE",
RDADDRCHANGEA => "FALSE",
RDADDRCHANGEB => "FALSE",
SLEEP_ASYNC => "FALSE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
INIT_00 => X"{[17:9]_INIT_00}",
INIT_01 => X"{[17:9]_INIT_01}",
INIT_02 => X"{[17:9]_INIT_02}",
INIT_03 => X"{[17:9]_INIT_03}",
INIT_04 => X"{[17:9]_INIT_04}",
INIT_05 => X"{[17:9]_INIT_05}",
INIT_06 => X"{[17:9]_INIT_06}",
INIT_07 => X"{[17:9]_INIT_07}",
INIT_08 => X"{[17:9]_INIT_08}",
INIT_09 => X"{[17:9]_INIT_09}",
INIT_0A => X"{[17:9]_INIT_0A}",
INIT_0B => X"{[17:9]_INIT_0B}",
INIT_0C => X"{[17:9]_INIT_0C}",
INIT_0D => X"{[17:9]_INIT_0D}",
INIT_0E => X"{[17:9]_INIT_0E}",
INIT_0F => X"{[17:9]_INIT_0F}",
INIT_10 => X"{[17:9]_INIT_10}",
INIT_11 => X"{[17:9]_INIT_11}",
INIT_12 => X"{[17:9]_INIT_12}",
INIT_13 => X"{[17:9]_INIT_13}",
INIT_14 => X"{[17:9]_INIT_14}",
INIT_15 => X"{[17:9]_INIT_15}",
INIT_16 => X"{[17:9]_INIT_16}",
INIT_17 => X"{[17:9]_INIT_17}",
INIT_18 => X"{[17:9]_INIT_18}",
INIT_19 => X"{[17:9]_INIT_19}",
INIT_1A => X"{[17:9]_INIT_1A}",
INIT_1B => X"{[17:9]_INIT_1B}",
INIT_1C => X"{[17:9]_INIT_1C}",
INIT_1D => X"{[17:9]_INIT_1D}",
INIT_1E => X"{[17:9]_INIT_1E}",
INIT_1F => X"{[17:9]_INIT_1F}",
INIT_20 => X"{[17:9]_INIT_20}",
INIT_21 => X"{[17:9]_INIT_21}",
INIT_22 => X"{[17:9]_INIT_22}",
INIT_23 => X"{[17:9]_INIT_23}",
INIT_24 => X"{[17:9]_INIT_24}",
INIT_25 => X"{[17:9]_INIT_25}",
INIT_26 => X"{[17:9]_INIT_26}",
INIT_27 => X"{[17:9]_INIT_27}",
INIT_28 => X"{[17:9]_INIT_28}",
INIT_29 => X"{[17:9]_INIT_29}",
INIT_2A => X"{[17:9]_INIT_2A}",
INIT_2B => X"{[17:9]_INIT_2B}",
INIT_2C => X"{[17:9]_INIT_2C}",
INIT_2D => X"{[17:9]_INIT_2D}",
INIT_2E => X"{[17:9]_INIT_2E}",
INIT_2F => X"{[17:9]_INIT_2F}",
INIT_30 => X"{[17:9]_INIT_30}",
INIT_31 => X"{[17:9]_INIT_31}",
INIT_32 => X"{[17:9]_INIT_32}",
INIT_33 => X"{[17:9]_INIT_33}",
INIT_34 => X"{[17:9]_INIT_34}",
INIT_35 => X"{[17:9]_INIT_35}",
INIT_36 => X"{[17:9]_INIT_36}",
INIT_37 => X"{[17:9]_INIT_37}",
INIT_38 => X"{[17:9]_INIT_38}",
INIT_39 => X"{[17:9]_INIT_39}",
INIT_3A => X"{[17:9]_INIT_3A}",
INIT_3B => X"{[17:9]_INIT_3B}",
INIT_3C => X"{[17:9]_INIT_3C}",
INIT_3D => X"{[17:9]_INIT_3D}",
INIT_3E => X"{[17:9]_INIT_3E}",
INIT_3F => X"{[17:9]_INIT_3F}",
INIT_40 => X"{[17:9]_INIT_40}",
INIT_41 => X"{[17:9]_INIT_41}",
INIT_42 => X"{[17:9]_INIT_42}",
INIT_43 => X"{[17:9]_INIT_43}",
INIT_44 => X"{[17:9]_INIT_44}",
INIT_45 => X"{[17:9]_INIT_45}",
INIT_46 => X"{[17:9]_INIT_46}",
INIT_47 => X"{[17:9]_INIT_47}",
INIT_48 => X"{[17:9]_INIT_48}",
INIT_49 => X"{[17:9]_INIT_49}",
INIT_4A => X"{[17:9]_INIT_4A}",
INIT_4B => X"{[17:9]_INIT_4B}",
INIT_4C => X"{[17:9]_INIT_4C}",
INIT_4D => X"{[17:9]_INIT_4D}",
INIT_4E => X"{[17:9]_INIT_4E}",
INIT_4F => X"{[17:9]_INIT_4F}",
INIT_50 => X"{[17:9]_INIT_50}",
INIT_51 => X"{[17:9]_INIT_51}",
INIT_52 => X"{[17:9]_INIT_52}",
INIT_53 => X"{[17:9]_INIT_53}",
INIT_54 => X"{[17:9]_INIT_54}",
INIT_55 => X"{[17:9]_INIT_55}",
INIT_56 => X"{[17:9]_INIT_56}",
INIT_57 => X"{[17:9]_INIT_57}",
INIT_58 => X"{[17:9]_INIT_58}",
INIT_59 => X"{[17:9]_INIT_59}",
INIT_5A => X"{[17:9]_INIT_5A}",
INIT_5B => X"{[17:9]_INIT_5B}",
INIT_5C => X"{[17:9]_INIT_5C}",
INIT_5D => X"{[17:9]_INIT_5D}",
INIT_5E => X"{[17:9]_INIT_5E}",
INIT_5F => X"{[17:9]_INIT_5F}",
INIT_60 => X"{[17:9]_INIT_60}",
INIT_61 => X"{[17:9]_INIT_61}",
INIT_62 => X"{[17:9]_INIT_62}",
INIT_63 => X"{[17:9]_INIT_63}",
INIT_64 => X"{[17:9]_INIT_64}",
INIT_65 => X"{[17:9]_INIT_65}",
INIT_66 => X"{[17:9]_INIT_66}",
INIT_67 => X"{[17:9]_INIT_67}",
INIT_68 => X"{[17:9]_INIT_68}",
INIT_69 => X"{[17:9]_INIT_69}",
INIT_6A => X"{[17:9]_INIT_6A}",
INIT_6B => X"{[17:9]_INIT_6B}",
INIT_6C => X"{[17:9]_INIT_6C}",
INIT_6D => X"{[17:9]_INIT_6D}",
INIT_6E => X"{[17:9]_INIT_6E}",
INIT_6F => X"{[17:9]_INIT_6F}",
INIT_70 => X"{[17:9]_INIT_70}",
INIT_71 => X"{[17:9]_INIT_71}",
INIT_72 => X"{[17:9]_INIT_72}",
INIT_73 => X"{[17:9]_INIT_73}",
INIT_74 => X"{[17:9]_INIT_74}",
INIT_75 => X"{[17:9]_INIT_75}",
INIT_76 => X"{[17:9]_INIT_76}",
INIT_77 => X"{[17:9]_INIT_77}",
INIT_78 => X"{[17:9]_INIT_78}",
INIT_79 => X"{[17:9]_INIT_79}",
INIT_7A => X"{[17:9]_INIT_7A}",
INIT_7B => X"{[17:9]_INIT_7B}",
INIT_7C => X"{[17:9]_INIT_7C}",
INIT_7D => X"{[17:9]_INIT_7D}",
INIT_7E => X"{[17:9]_INIT_7E}",
INIT_7F => X"{[17:9]_INIT_7F}",
INITP_00 => X"{[17:9]_INITP_00}",
INITP_01 => X"{[17:9]_INITP_01}",
INITP_02 => X"{[17:9]_INITP_02}",
INITP_03 => X"{[17:9]_INITP_03}",
INITP_04 => X"{[17:9]_INITP_04}",
INITP_05 => X"{[17:9]_INITP_05}",
INITP_06 => X"{[17:9]_INITP_06}",
INITP_07 => X"{[17:9]_INITP_07}",
INITP_08 => X"{[17:9]_INITP_08}",
INITP_09 => X"{[17:9]_INITP_09}",
INITP_0A => X"{[17:9]_INITP_0A}",
INITP_0B => X"{[17:9]_INITP_0B}",
INITP_0C => X"{[17:9]_INITP_0C}",
INITP_0D => X"{[17:9]_INITP_0D}",
INITP_0E => X"{[17:9]_INITP_0E}",
INITP_0F => X"{[17:9]_INITP_0F}")
port map( ADDRARDADDR => address_a(14 downto 0),
ENARDEN => enable,
CLKARDCLK => clk,
DOUTADOUT => data_out_a_h(31 downto 0),
DOUTPADOUTP => data_out_a_h(35 downto 32),
DINADIN => data_in_a(31 downto 0),
DINPADINP => data_in_a(35 downto 32),
WEA => "0000",
REGCEAREGCE => '0',
RSTRAMARSTRAM => '0',
RSTREGARSTREG => '0',
ADDRBWRADDR => address_b(14 downto 0),
ENBWREN => enable_b,
CLKBWRCLK => clk_b,
DOUTBDOUT => data_out_b_h(31 downto 0),
DOUTPBDOUTP => data_out_b_h(35 downto 32),
DINBDIN => data_in_b_h(31 downto 0),
DINPBDINP => data_in_b_h(35 downto 32),
WEBWE => we_b,
REGCEB => '0',
RSTRAMB => '0',
RSTREGB => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
ADDRENA => '1',
ADDRENB => '1',
CASDIMUXA => '0',
CASDIMUXB => '0',
CASDINA => "00000000000000000000000000000000",
CASDINB => "00000000000000000000000000000000",
CASDINPA => "0000",
CASDINPB => "0000",
CASDOMUXA => '0',
CASDOMUXB => '0',
CASDOMUXEN_A => '1',
CASDOMUXEN_B => '1',
CASINDBITERR => '0',
CASINSBITERR => '0',
CASOREGIMUXA => '0',
CASOREGIMUXB => '0',
CASOREGIMUXEN_A => '0',
CASOREGIMUXEN_B => '0',
ECCPIPECE => '0',
SLEEP => '0');
--
end generate us;
--
end generate ram_4k_generate;
--
--
--
--
-- JTAG Loader
--
instantiate_loader : if (C_JTAG_LOADER_ENABLE = 1) generate
--
jtag_loader_6_inst : jtag_loader_6
generic map( C_FAMILY => C_FAMILY,
C_NUM_PICOBLAZE => 1,
C_JTAG_LOADER_ENABLE => C_JTAG_LOADER_ENABLE,
C_BRAM_MAX_ADDR_WIDTH => BRAM_ADDRESS_WIDTH,
C_ADDR_WIDTH_0 => BRAM_ADDRESS_WIDTH)
port map( picoblaze_reset => rdl_bus,
jtag_en => jtag_en,
jtag_din => jtag_din,
jtag_addr => jtag_addr(BRAM_ADDRESS_WIDTH-1 downto 0),
jtag_clk => jtag_clk,
jtag_we => jtag_we,
jtag_dout_0 => jtag_dout,
jtag_dout_1 => jtag_dout, -- ports 1-7 are not used
jtag_dout_2 => jtag_dout, -- in a 1 device debug
jtag_dout_3 => jtag_dout, -- session. However, Synplify
jtag_dout_4 => jtag_dout, -- etc require all ports to
jtag_dout_5 => jtag_dout, -- be connected
jtag_dout_6 => jtag_dout,
jtag_dout_7 => jtag_dout);
--
end generate instantiate_loader;
--
end low_level_definition;
--
--
-------------------------------------------------------------------------------------------
--
-- JTAG Loader
--
-------------------------------------------------------------------------------------------
--
--
-- JTAG Loader 6 - Version 6.00
-- Kris Chaplin 4 February 2010
-- Ken Chapman 15 August 2011 - Revised coding style
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--
library unisim;
use unisim.vcomponents.all;
--
entity jtag_loader_6 is
generic( C_JTAG_LOADER_ENABLE : integer := 1;
C_FAMILY : string := "7S";
C_NUM_PICOBLAZE : integer := 1;
C_BRAM_MAX_ADDR_WIDTH : integer := 10;
C_PICOBLAZE_INSTRUCTION_DATA_WIDTH : integer := 18;
C_JTAG_CHAIN : integer := 2;
C_ADDR_WIDTH_0 : integer := 10;
C_ADDR_WIDTH_1 : integer := 10;
C_ADDR_WIDTH_2 : integer := 10;
C_ADDR_WIDTH_3 : integer := 10;
C_ADDR_WIDTH_4 : integer := 10;
C_ADDR_WIDTH_5 : integer := 10;
C_ADDR_WIDTH_6 : integer := 10;
C_ADDR_WIDTH_7 : integer := 10);
port( picoblaze_reset : out std_logic_vector(C_NUM_PICOBLAZE-1 downto 0);
jtag_en : out std_logic_vector(C_NUM_PICOBLAZE-1 downto 0) := (others => '0');
jtag_din : out std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0) := (others => '0');
jtag_addr : out std_logic_vector(C_BRAM_MAX_ADDR_WIDTH-1 downto 0) := (others => '0');
jtag_clk : out std_logic := '0';
jtag_we : out std_logic := '0';
jtag_dout_0 : in std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
jtag_dout_1 : in std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
jtag_dout_2 : in std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
jtag_dout_3 : in std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
jtag_dout_4 : in std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
jtag_dout_5 : in std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
jtag_dout_6 : in std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
jtag_dout_7 : in std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0));
end jtag_loader_6;
--
architecture Behavioral of jtag_loader_6 is
--
signal num_picoblaze : std_logic_vector(2 downto 0);
signal picoblaze_instruction_data_width : std_logic_vector(4 downto 0);
--
signal drck : std_logic;
signal shift_clk : std_logic;
signal shift_din : std_logic;
signal shift_dout : std_logic;
signal shift : std_logic;
signal capture : std_logic;
--
signal control_reg_ce : std_logic;
signal bram_ce : std_logic_vector(C_NUM_PICOBLAZE-1 downto 0);
signal bus_zero : std_logic_vector(C_NUM_PICOBLAZE-1 downto 0) := (others => '0');
signal jtag_en_int : std_logic_vector(C_NUM_PICOBLAZE-1 downto 0);
signal jtag_en_expanded : std_logic_vector(7 downto 0) := (others => '0');
signal jtag_addr_int : std_logic_vector(C_BRAM_MAX_ADDR_WIDTH-1 downto 0);
signal jtag_din_int : std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
signal control_din : std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0):= (others => '0');
signal control_dout : std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0):= (others => '0');
signal control_dout_int : std_logic_vector(7 downto 0):= (others => '0');
signal bram_dout_int : std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0) := (others => '0');
signal jtag_we_int : std_logic;
signal jtag_clk_int : std_logic;
signal bram_ce_valid : std_logic;
signal din_load : std_logic;
--
signal jtag_dout_0_masked : std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
signal jtag_dout_1_masked : std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
signal jtag_dout_2_masked : std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
signal jtag_dout_3_masked : std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
signal jtag_dout_4_masked : std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
signal jtag_dout_5_masked : std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
signal jtag_dout_6_masked : std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
signal jtag_dout_7_masked : std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
signal picoblaze_reset_int : std_logic_vector(C_NUM_PICOBLAZE-1 downto 0) := (others => '0');
--
begin
bus_zero <= (others => '0');
--
jtag_loader_gen: if (C_JTAG_LOADER_ENABLE = 1) generate
--
-- Insert BSCAN primitive for target device architecture.
--
BSCAN_7SERIES_gen: if (C_FAMILY="7S") generate
begin
BSCAN_BLOCK_inst: BSCANE2
generic map( JTAG_CHAIN => C_JTAG_CHAIN,
DISABLE_JTAG => "FALSE")
port map( CAPTURE => capture,
DRCK => drck,
RESET => open,
RUNTEST => open,
SEL => bram_ce_valid,
SHIFT => shift,
TCK => open,
TDI => shift_din,
TMS => open,
UPDATE => jtag_clk_int,
TDO => shift_dout);
end generate BSCAN_7SERIES_gen;
--
BSCAN_UltraScale_gen: if (C_FAMILY="US") generate
begin
BSCAN_BLOCK_inst: BSCANE2
generic map( JTAG_CHAIN => C_JTAG_CHAIN,
DISABLE_JTAG => "FALSE")
port map( CAPTURE => capture,
DRCK => drck,
RESET => open,
RUNTEST => open,
SEL => bram_ce_valid,
SHIFT => shift,
TCK => open,
TDI => shift_din,
TMS => open,
UPDATE => jtag_clk_int,
TDO => shift_dout);
end generate BSCAN_UltraScale_gen;
--
--
-- Insert clock buffer to ensure reliable shift operations.
--
upload_clock: BUFG
port map( I => drck,
O => shift_clk);
--
--
-- Shift Register
--
--
control_reg_ce_shift: process (shift_clk)
begin
if shift_clk'event and shift_clk = '1' then
if (shift = '1') then
control_reg_ce <= shift_din;
end if;
end if;
end process control_reg_ce_shift;
--
bram_ce_shift: process (shift_clk)
begin
if shift_clk'event and shift_clk='1' then
if (shift = '1') then
if(C_NUM_PICOBLAZE > 1) then
for i in 0 to C_NUM_PICOBLAZE-2 loop
bram_ce(i+1) <= bram_ce(i);
end loop;
end if;
bram_ce(0) <= control_reg_ce;
end if;
end if;
end process bram_ce_shift;
--
bram_we_shift: process (shift_clk)
begin
if shift_clk'event and shift_clk='1' then
if (shift = '1') then
jtag_we_int <= bram_ce(C_NUM_PICOBLAZE-1);
end if;
end if;
end process bram_we_shift;
--
bram_a_shift: process (shift_clk)
begin
if shift_clk'event and shift_clk='1' then
if (shift = '1') then
for i in 0 to C_BRAM_MAX_ADDR_WIDTH-2 loop
jtag_addr_int(i+1) <= jtag_addr_int(i);
end loop;
jtag_addr_int(0) <= jtag_we_int;
end if;
end if;
end process bram_a_shift;
--
bram_d_shift: process (shift_clk)
begin
if shift_clk'event and shift_clk='1' then
if (din_load = '1') then
jtag_din_int <= bram_dout_int;
elsif (shift = '1') then
for i in 0 to C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-2 loop
jtag_din_int(i+1) <= jtag_din_int(i);
end loop;
jtag_din_int(0) <= jtag_addr_int(C_BRAM_MAX_ADDR_WIDTH-1);
end if;
end if;
end process bram_d_shift;
--
shift_dout <= jtag_din_int(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1);
--
--
din_load_select:process (bram_ce, din_load, capture, bus_zero, control_reg_ce)
begin
if ( bram_ce = bus_zero ) then
din_load <= capture and control_reg_ce;
else
din_load <= capture;
end if;
end process din_load_select;
--
--
-- Control Registers
--
num_picoblaze <= conv_std_logic_vector(C_NUM_PICOBLAZE-1,3);
picoblaze_instruction_data_width <= conv_std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1,5);
--
control_registers: process(jtag_clk_int)
begin
if (jtag_clk_int'event and jtag_clk_int = '1') then
if (bram_ce_valid = '1') and (jtag_we_int = '0') and (control_reg_ce = '1') then
case (jtag_addr_int(3 downto 0)) is
when "0000" => -- 0 = version - returns (7 downto 4) illustrating number of PB
-- and (3 downto 0) picoblaze instruction data width
control_dout_int <= num_picoblaze & picoblaze_instruction_data_width;
when "0001" => -- 1 = PicoBlaze 0 reset / status
if (C_NUM_PICOBLAZE >= 1) then
control_dout_int <= picoblaze_reset_int(0) & "00" & (conv_std_logic_vector(C_ADDR_WIDTH_0-1,5) );
else
control_dout_int <= (others => '0');
end if;
when "0010" => -- 2 = PicoBlaze 1 reset / status
if (C_NUM_PICOBLAZE >= 2) then
control_dout_int <= picoblaze_reset_int(1) & "00" & (conv_std_logic_vector(C_ADDR_WIDTH_1-1,5) );
else
control_dout_int <= (others => '0');
end if;
when "0011" => -- 3 = PicoBlaze 2 reset / status
if (C_NUM_PICOBLAZE >= 3) then
control_dout_int <= picoblaze_reset_int(2) & "00" & (conv_std_logic_vector(C_ADDR_WIDTH_2-1,5) );
else
control_dout_int <= (others => '0');
end if;
when "0100" => -- 4 = PicoBlaze 3 reset / status
if (C_NUM_PICOBLAZE >= 4) then
control_dout_int <= picoblaze_reset_int(3) & "00" & (conv_std_logic_vector(C_ADDR_WIDTH_3-1,5) );
else
control_dout_int <= (others => '0');
end if;
when "0101" => -- 5 = PicoBlaze 4 reset / status
if (C_NUM_PICOBLAZE >= 5) then
control_dout_int <= picoblaze_reset_int(4) & "00" & (conv_std_logic_vector(C_ADDR_WIDTH_4-1,5) );
else
control_dout_int <= (others => '0');
end if;
when "0110" => -- 6 = PicoBlaze 5 reset / status
if (C_NUM_PICOBLAZE >= 6) then
control_dout_int <= picoblaze_reset_int(5) & "00" & (conv_std_logic_vector(C_ADDR_WIDTH_5-1,5) );
else
control_dout_int <= (others => '0');
end if;
when "0111" => -- 7 = PicoBlaze 6 reset / status
if (C_NUM_PICOBLAZE >= 7) then
control_dout_int <= picoblaze_reset_int(6) & "00" & (conv_std_logic_vector(C_ADDR_WIDTH_6-1,5) );
else
control_dout_int <= (others => '0');
end if;
when "1000" => -- 8 = PicoBlaze 7 reset / status
if (C_NUM_PICOBLAZE >= 8) then
control_dout_int <= picoblaze_reset_int(7) & "00" & (conv_std_logic_vector(C_ADDR_WIDTH_7-1,5) );
else
control_dout_int <= (others => '0');
end if;
when "1111" => control_dout_int <= conv_std_logic_vector(C_BRAM_MAX_ADDR_WIDTH -1,8);
when others => control_dout_int <= (others => '1');
end case;
else
control_dout_int <= (others => '0');
end if;
end if;
end process control_registers;
--
control_dout(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-8) <= control_dout_int;
--
pb_reset: process(jtag_clk_int)
begin
if (jtag_clk_int'event and jtag_clk_int = '1') then
if (bram_ce_valid = '1') and (jtag_we_int = '1') and (control_reg_ce = '1') then
picoblaze_reset_int(C_NUM_PICOBLAZE-1 downto 0) <= control_din(C_NUM_PICOBLAZE-1 downto 0);
end if;
end if;
end process pb_reset;
--
--
-- Assignments
--
control_dout (C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-9 downto 0) <= (others => '0') when (C_PICOBLAZE_INSTRUCTION_DATA_WIDTH > 8);
--
-- Qualify the blockram CS signal with bscan select output
jtag_en_int <= bram_ce when bram_ce_valid = '1' else (others => '0');
--
jtag_en_expanded(C_NUM_PICOBLAZE-1 downto 0) <= jtag_en_int;
jtag_en_expanded(7 downto C_NUM_PICOBLAZE) <= (others => '0') when (C_NUM_PICOBLAZE < 8);
--
bram_dout_int <= control_dout or jtag_dout_0_masked or jtag_dout_1_masked or jtag_dout_2_masked or jtag_dout_3_masked or jtag_dout_4_masked or jtag_dout_5_masked or jtag_dout_6_masked or jtag_dout_7_masked;
--
control_din <= jtag_din_int;
--
jtag_dout_0_masked <= jtag_dout_0 when jtag_en_expanded(0) = '1' else (others => '0');
jtag_dout_1_masked <= jtag_dout_1 when jtag_en_expanded(1) = '1' else (others => '0');
jtag_dout_2_masked <= jtag_dout_2 when jtag_en_expanded(2) = '1' else (others => '0');
jtag_dout_3_masked <= jtag_dout_3 when jtag_en_expanded(3) = '1' else (others => '0');
jtag_dout_4_masked <= jtag_dout_4 when jtag_en_expanded(4) = '1' else (others => '0');
jtag_dout_5_masked <= jtag_dout_5 when jtag_en_expanded(5) = '1' else (others => '0');
jtag_dout_6_masked <= jtag_dout_6 when jtag_en_expanded(6) = '1' else (others => '0');
jtag_dout_7_masked <= jtag_dout_7 when jtag_en_expanded(7) = '1' else (others => '0');
--
jtag_en <= jtag_en_int;
jtag_din <= jtag_din_int;
jtag_addr <= jtag_addr_int;
jtag_clk <= jtag_clk_int;
jtag_we <= jtag_we_int;
picoblaze_reset <= picoblaze_reset_int;
--
end generate jtag_loader_gen;
--
end Behavioral;
--
--
------------------------------------------------------------------------------------
--
-- END OF FILE {name}.vhd
--
------------------------------------------------------------------------------------
|
----------------------------------------------------------------------------------
-- Nicolas Primeau
--
-- Create Date: 13:24:12 03/15/2014
-- Design Name: Asynchronous Generic Memory
-- Module Name: Mem_Async - Behavioral
-- Description:
--
-- Asynchronous generic memory. CAREFUL, Do not write until the address has been
-- stablized or else you might write to an unpredictable place! This component is
-- much better when you only want to read from it with STABLE address bus. STABLE.
-- ADDRESS. BUS.
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
use ieee.math_real.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Mem_Async is
generic(memSize: integer:=8;
numAdr: integer:=512);
port(
dataIn: in std_logic_vector(memSize -1 downto 0);
dataOut: out std_logic_vector(memSize-1 downto 0);
addr: in std_logic_vector((integer(log2(real(numAdr))))-1 downto 0);
rd_wr: in std_logic; -- rd low, wr high
reset: in std_logic
);
end Mem_Async;
architecture Behavioral of Mem_Async is
type RAM is array (numAdr-1 downto 0) of std_logic_vector(memSize -1);
signal memory: RAM;
begin
if(reset = '1') then
for i in 0 to numAdr-1 loop
memory(i) <= std_logic_vector(to_unsigned(0,memSize));
end loop;
dataOut <= (others => '0');
elsif(rd_wr = '0') then
dataOut <= memory(to_integer(unsigned(addr)));
elsif(rd_wr = '1') then
memory(to_integer(unsigned(addr))) <= dataIn;
dataOut <= (others => '0');
else
dataOut <= (others=>'0');
end if;
end Behavioral;
|
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg.vhd
-- Description: This entity is the top level entity for the AXI Scatter Gather
-- Engine.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_sg_v4_1;
use axi_sg_v4_1.axi_sg_pkg.all;
library lib_pkg_v1_0;
use lib_pkg_v1_0.lib_pkg.max2;
-------------------------------------------------------------------------------
entity axi_sg is
generic (
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32;
-- Master AXI Memory Map Address Width for Scatter Gather R/W Port
C_M_AXI_SG_DATA_WIDTH : integer range 32 to 32 := 32;
-- Master AXI Memory Map Data Width for Scatter Gather R/W Port
C_M_AXIS_SG_TDATA_WIDTH : integer range 32 to 32 := 32;
-- AXI Master Stream out for descriptor fetch
C_S_AXIS_UPDPTR_TDATA_WIDTH : integer range 32 to 32 := 32;
-- 32 Update Status Bits
C_S_AXIS_UPDSTS_TDATA_WIDTH : integer range 33 to 33 := 33;
-- 1 IOC bit + 32 Update Status Bits
C_SG_FTCH_DESC2QUEUE : integer range 0 to 8 := 0;
-- Number of descriptors to fetch and queue for each channel.
-- A value of zero excludes the fetch queues.
C_SG_UPDT_DESC2QUEUE : integer range 0 to 8 := 0;
-- Number of descriptors to fetch and queue for each channel.
-- A value of zero excludes the fetch queues.
C_SG_CH1_WORDS_TO_FETCH : integer range 4 to 16 := 8;
-- Number of words to fetch
C_SG_CH1_WORDS_TO_UPDATE : integer range 1 to 16 := 8;
-- Number of words to update
C_SG_CH1_FIRST_UPDATE_WORD : integer range 0 to 15 := 0;
-- Starting update word offset
C_SG_CH1_ENBL_STALE_ERROR : integer range 0 to 1 := 1;
-- Enable or disable stale descriptor check
-- 0 = Disable stale descriptor error check
-- 1 = Enable stale descriptor error check
C_SG_CH2_WORDS_TO_FETCH : integer range 4 to 16 := 8;
-- Number of words to fetch
C_SG_CH2_WORDS_TO_UPDATE : integer range 1 to 16 := 8;
-- Number of words to update
C_SG_CH2_FIRST_UPDATE_WORD : integer range 0 to 15 := 0;
-- Starting update word offset
C_SG_CH2_ENBL_STALE_ERROR : integer range 0 to 1 := 1;
-- Enable or disable stale descriptor check
-- 0 = Disable stale descriptor error check
-- 1 = Enable stale descriptor error check
C_INCLUDE_CH1 : integer range 0 to 1 := 1;
-- Include or Exclude channel 1 scatter gather engine
-- 0 = Exclude Channel 1 SG Engine
-- 1 = Include Channel 1 SG Engine
C_INCLUDE_CH2 : integer range 0 to 1 := 1;
-- Include or Exclude channel 2 scatter gather engine
-- 0 = Exclude Channel 2 SG Engine
-- 1 = Include Channel 2 SG Engine
C_AXIS_IS_ASYNC : integer range 0 to 1 := 0;
-- Channel 1 is async to sg_aclk
-- 0 = Synchronous to SG ACLK
-- 1 = Asynchronous to SG ACLK
C_ASYNC : integer range 0 to 1 := 0;
-- Channel 1 is async to sg_aclk
-- 0 = Synchronous to SG ACLK
-- 1 = Asynchronous to SG ACLK
C_INCLUDE_DESC_UPDATE : integer range 0 to 1 := 1;
-- Include or Exclude Scatter Gather Descriptor Update
-- 0 = Exclude Descriptor Update
-- 1 = Include Descriptor Update
C_INCLUDE_INTRPT : integer range 0 to 1 := 1;
-- Include/Exclude interrupt logic coalescing
-- 0 = Exclude Delay timer
-- 1 = Include Delay timer
C_INCLUDE_DLYTMR : integer range 0 to 1 := 1;
-- Include/Exclude interrupt delay timer
-- 0 = Exclude Delay timer
-- 1 = Include Delay timer
C_DLYTMR_RESOLUTION : integer range 1 to 100000 := 125;
-- Interrupt Delay Timer resolution in usec
C_ENABLE_MULTI_CHANNEL : integer range 0 to 1 := 0;
C_ENABLE_CDMA : integer range 0 to 1 := 0;
C_ENABLE_EXTRA_FIELD : integer range 0 to 1 := 0;
C_NUM_S2MM_CHANNELS : integer range 1 to 16 := 1;
C_NUM_MM2S_CHANNELS : integer range 1 to 16 := 1;
C_ACTUAL_ADDR : integer range 32 to 64 := 32;
C_FAMILY : string := "virtex7"
-- Device family used for proper BRAM selection
);
port (
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk : in std_logic ; --
m_axi_mm2s_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
p_reset_n : in std_logic ;
--
dm_resetn : in std_logic ; --
sg_ctl : in std_logic_vector (7 downto 0) ;
--
-- Scatter Gather Write Address Channel --
m_axi_sg_awaddr : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
m_axi_sg_awlen : out std_logic_vector(7 downto 0) ; --
m_axi_sg_awsize : out std_logic_vector(2 downto 0) ; --
m_axi_sg_awburst : out std_logic_vector(1 downto 0) ; --
m_axi_sg_awprot : out std_logic_vector(2 downto 0) ; --
m_axi_sg_awcache : out std_logic_vector(3 downto 0) ; --
m_axi_sg_awuser : out std_logic_vector(3 downto 0) ; --
m_axi_sg_awvalid : out std_logic ; --
m_axi_sg_awready : in std_logic ; --
--
-- Scatter Gather Write Data Channel --
m_axi_sg_wdata : out std_logic_vector --
(C_M_AXI_SG_DATA_WIDTH-1 downto 0) ; --
m_axi_sg_wstrb : out std_logic_vector --
((C_M_AXI_SG_DATA_WIDTH/8)-1 downto 0); --
m_axi_sg_wlast : out std_logic ; --
m_axi_sg_wvalid : out std_logic ; --
m_axi_sg_wready : in std_logic ; --
--
-- Scatter Gather Write Response Channel --
m_axi_sg_bresp : in std_logic_vector(1 downto 0) ; --
m_axi_sg_bvalid : in std_logic ; --
m_axi_sg_bready : out std_logic ; --
--
-- Scatter Gather Read Address Channel --
m_axi_sg_araddr : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
m_axi_sg_arlen : out std_logic_vector(7 downto 0) ; --
m_axi_sg_arsize : out std_logic_vector(2 downto 0) ; --
m_axi_sg_arburst : out std_logic_vector(1 downto 0) ; --
m_axi_sg_arcache : out std_logic_vector(3 downto 0) ; --
m_axi_sg_aruser : out std_logic_vector(3 downto 0) ; --
m_axi_sg_arprot : out std_logic_vector(2 downto 0) ; --
m_axi_sg_arvalid : out std_logic ; --
m_axi_sg_arready : in std_logic ; --
--
-- Memory Map to Stream Scatter Gather Read Data Channel --
m_axi_sg_rdata : in std_logic_vector --
(C_M_AXI_SG_DATA_WIDTH-1 downto 0) ; --
m_axi_sg_rresp : in std_logic_vector(1 downto 0) ; --
m_axi_sg_rlast : in std_logic ; --
m_axi_sg_rvalid : in std_logic ; --
m_axi_sg_rready : out std_logic ; --
--
-- Channel 1 Control and Status --
ch1_run_stop : in std_logic ; --
ch1_cyclic : in std_logic ; --
ch1_desc_flush : in std_logic ; --
ch1_cntrl_strm_stop : in std_logic ;
ch1_tailpntr_enabled : in std_logic ; --
ch1_taildesc_wren : in std_logic ; --
ch1_taildesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
ch1_curdesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
ch1_ftch_idle : out std_logic ; --
ch1_ftch_interr_set : out std_logic ; --
ch1_ftch_slverr_set : out std_logic ; --
ch1_ftch_decerr_set : out std_logic ; --
ch1_ftch_err_early : out std_logic ; --
ch1_ftch_stale_desc : out std_logic ; --
ch1_updt_idle : out std_logic ; --
ch1_updt_ioc_irq_set : out std_logic ; --
ch1_updt_interr_set : out std_logic ; --
ch1_updt_slverr_set : out std_logic ; --
ch1_updt_decerr_set : out std_logic ; --
ch1_dma_interr_set : out std_logic ; --
ch1_dma_slverr_set : out std_logic ; --
ch1_dma_decerr_set : out std_logic ; --
--
--
-- Channel 1 Interrupt Coalescing Signals --
ch1_irqthresh_rstdsbl : in std_logic ;-- CR572013 --
ch1_dlyirq_dsble : in std_logic ; --
ch1_irqdelay_wren : in std_logic ; --
ch1_irqdelay : in std_logic_vector(7 downto 0) ; --
ch1_irqthresh_wren : in std_logic ; --
ch1_irqthresh : in std_logic_vector(7 downto 0) ; --
ch1_packet_sof : in std_logic ; --
ch1_packet_eof : in std_logic ; --
ch1_ioc_irq_set : out std_logic ; --
ch1_dly_irq_set : out std_logic ; --
ch1_irqdelay_status : out std_logic_vector(7 downto 0) ; --
ch1_irqthresh_status : out std_logic_vector(7 downto 0) ; --
--
-- Channel 1 AXI Fetch Stream Out --
m_axis_ch1_ftch_aclk : in std_logic ; --
m_axis_ch1_ftch_tdata : out std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0); --
m_axis_ch1_ftch_tvalid : out std_logic ; --
m_axis_ch1_ftch_tready : in std_logic ; --
m_axis_ch1_ftch_tlast : out std_logic ; --
m_axis_ch1_ftch_tdata_new : out std_logic_vector --
(96+31*C_ENABLE_CDMA+(2+C_ENABLE_CDMA)*(C_M_AXI_SG_ADDR_WIDTH-32) downto 0); --
m_axis_ch1_ftch_tdata_mcdma_new : out std_logic_vector --
(63 downto 0); --
m_axis_ch1_ftch_tvalid_new : out std_logic ; --
m_axis_ftch1_desc_available : out std_logic;
--
--
-- Channel 1 AXI Update Stream In --
s_axis_ch1_updt_aclk : in std_logic ; --
s_axis_ch1_updtptr_tdata : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0); --
s_axis_ch1_updtptr_tvalid : in std_logic ; --
s_axis_ch1_updtptr_tready : out std_logic ; --
s_axis_ch1_updtptr_tlast : in std_logic ; --
--
s_axis_ch1_updtsts_tdata : in std_logic_vector --
(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0); --
s_axis_ch1_updtsts_tvalid : in std_logic ; --
s_axis_ch1_updtsts_tready : out std_logic ; --
s_axis_ch1_updtsts_tlast : in std_logic ; --
--
-- Channel 2 Control and Status --
ch2_run_stop : in std_logic ; --
ch2_cyclic : in std_logic ; --
ch2_desc_flush : in std_logic ; --
ch2_tailpntr_enabled : in std_logic ; --
ch2_taildesc_wren : in std_logic ; --
ch2_taildesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
ch2_curdesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
ch2_ftch_idle : out std_logic ; --
ch2_ftch_interr_set : out std_logic ; --
ch2_ftch_slverr_set : out std_logic ; --
ch2_ftch_decerr_set : out std_logic ; --
ch2_ftch_err_early : out std_logic ; --
ch2_ftch_stale_desc : out std_logic ; --
ch2_updt_idle : out std_logic ; --
ch2_updt_ioc_irq_set : out std_logic ; --
ch2_updt_interr_set : out std_logic ; --
ch2_updt_slverr_set : out std_logic ; --
ch2_updt_decerr_set : out std_logic ; --
ch2_dma_interr_set : out std_logic ; --
ch2_dma_slverr_set : out std_logic ; --
ch2_dma_decerr_set : out std_logic ; --
--
-- Channel 2 Interrupt Coalescing Signals --
ch2_irqthresh_rstdsbl : in std_logic ;-- CR572013 --
ch2_dlyirq_dsble : in std_logic ; --
ch2_irqdelay_wren : in std_logic ; --
ch2_irqdelay : in std_logic_vector(7 downto 0) ; --
ch2_irqthresh_wren : in std_logic ; --
ch2_irqthresh : in std_logic_vector(7 downto 0) ; --
ch2_packet_sof : in std_logic ; --
ch2_packet_eof : in std_logic ; --
ch2_ioc_irq_set : out std_logic ; --
ch2_dly_irq_set : out std_logic ; --
ch2_irqdelay_status : out std_logic_vector(7 downto 0) ; --
ch2_irqthresh_status : out std_logic_vector(7 downto 0) ; --
ch2_update_active : out std_logic ;
--
-- Channel 2 AXI Fetch Stream Out --
m_axis_ch2_ftch_aclk : in std_logic ; --
m_axis_ch2_ftch_tdata : out std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0); --
m_axis_ch2_ftch_tvalid : out std_logic ; --
m_axis_ch2_ftch_tready : in std_logic ; --
m_axis_ch2_ftch_tlast : out std_logic ; --
--
m_axis_ch2_ftch_tdata_new : out std_logic_vector --
(96+31*C_ENABLE_CDMA+(2+C_ENABLE_CDMA)*(C_M_AXI_SG_ADDR_WIDTH-32) downto 0); --
m_axis_ch2_ftch_tdata_mcdma_new : out std_logic_vector --
(63 downto 0); --
m_axis_ch2_ftch_tdata_mcdma_nxt : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0); --
m_axis_ch2_ftch_tvalid_new : out std_logic ; --
m_axis_ftch2_desc_available : out std_logic;
-- Channel 2 AXI Update Stream In --
s_axis_ch2_updt_aclk : in std_logic ; --
s_axis_ch2_updtptr_tdata : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0); --
s_axis_ch2_updtptr_tvalid : in std_logic ; --
s_axis_ch2_updtptr_tready : out std_logic ; --
s_axis_ch2_updtptr_tlast : in std_logic ; --
--
--
s_axis_ch2_updtsts_tdata : in std_logic_vector --
(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0); --
s_axis_ch2_updtsts_tvalid : in std_logic ; --
s_axis_ch2_updtsts_tready : out std_logic ; --
s_axis_ch2_updtsts_tlast : in std_logic ; --
--
--
-- Error addresses --
ftch_error : out std_logic ; --
ftch_error_addr : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
updt_error : out std_logic ; --
updt_error_addr : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
m_axis_mm2s_cntrl_tdata : out std_logic_vector --
(31 downto 0); --
m_axis_mm2s_cntrl_tkeep : out std_logic_vector --
(3 downto 0); --
m_axis_mm2s_cntrl_tvalid : out std_logic ; --
m_axis_mm2s_cntrl_tready : in std_logic := '0'; --
m_axis_mm2s_cntrl_tlast : out std_logic ;
bd_eq : out std_logic
);
end axi_sg;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_sg is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
constant AXI_LITE_MODE : integer := 2; -- DataMover Lite Mode
constant EXCLUDE : integer := 0; -- Define Exclude as 0
constant NEVER_HALT : std_logic := '0'; -- Never halt sg datamover
-- Always include descriptor fetch (use lite datamover)
constant INCLUDE_DESC_FETCH : integer := AXI_LITE_MODE;
-- Selectable include descriptor update (use lite datamover)
constant INCLUDE_DESC_UPDATE : integer := AXI_LITE_MODE * C_INCLUDE_DESC_UPDATE;
-- Always allow address requests
constant ALWAYS_ALLOW : std_logic := '1';
-- If async mode and number of descriptors to fetch is zero then set number
-- of descriptors to fetch as 1.
constant SG_FTCH_DESC2QUEUE : integer := max2(C_SG_FTCH_DESC2QUEUE,C_AXIS_IS_ASYNC);
constant SG_UPDT_DESC2QUEUE : integer := max2(C_SG_UPDT_DESC2QUEUE,C_AXIS_IS_ASYNC);
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
-- DataMover MM2S Fetch Command Stream Signals
signal s_axis_ftch_cmd_tvalid : std_logic := '0';
signal s_axis_ftch_cmd_tready : std_logic := '0';
signal s_axis_ftch_cmd_tdata : std_logic_vector
(((1+C_ENABLE_MULTI_CHANNEL)*C_M_AXI_SG_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0) := (others => '0');
-- DataMover MM2S Fetch Status Stream Signals
signal m_axis_ftch_sts_tvalid : std_logic := '0';
signal m_axis_ftch_sts_tready : std_logic := '0';
signal m_axis_ftch_sts_tdata : std_logic_vector(7 downto 0) := (others => '0');
signal m_axis_ftch_sts_tkeep : std_logic_vector(0 downto 0) := (others => '0');
signal mm2s_err : std_logic := '0';
-- DataMover MM2S Fetch Stream Signals
signal m_axis_mm2s_tdata : std_logic_vector
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0');
signal m_axis_mm2s_tkeep : std_logic_vector
((C_M_AXIS_SG_TDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal m_axis_mm2s_tlast : std_logic := '0';
signal m_axis_mm2s_tvalid : std_logic := '0';
signal m_axis_mm2s_tready : std_logic := '0';
-- DataMover S2MM Update Command Stream Signals
signal s_axis_updt_cmd_tvalid : std_logic := '0';
signal s_axis_updt_cmd_tready : std_logic := '0';
signal s_axis_updt_cmd_tdata : std_logic_vector
(((1+C_ENABLE_MULTI_CHANNEL)*C_M_AXI_SG_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0) := (others => '0');
-- DataMover S2MM Update Status Stream Signals
signal m_axis_updt_sts_tvalid : std_logic := '0';
signal m_axis_updt_sts_tready : std_logic := '0';
signal m_axis_updt_sts_tdata : std_logic_vector(7 downto 0) := (others => '0');
signal m_axis_updt_sts_tkeep : std_logic_vector(0 downto 0) := (others => '0');
signal s2mm_err : std_logic := '0';
-- DataMover S2MM Update Stream Signals
signal s_axis_s2mm_tdata : std_logic_vector
(C_M_AXI_SG_DATA_WIDTH-1 downto 0) := (others => '0');
signal s_axis_s2mm_tkeep : std_logic_vector
((C_M_AXI_SG_DATA_WIDTH/8)-1 downto 0) := (others => '1');
signal s_axis_s2mm_tlast : std_logic := '0';
signal s_axis_s2mm_tvalid : std_logic := '0';
signal s_axis_s2mm_tready : std_logic := '0';
-- Channel 1 internals
signal ch1_ftch_active : std_logic := '0';
signal ch1_ftch_queue_empty : std_logic := '0';
signal ch1_ftch_queue_full : std_logic := '0';
signal ch1_nxtdesc_wren : std_logic := '0';
signal ch1_updt_active : std_logic := '0';
signal ch1_updt_queue_empty : std_logic := '0';
signal ch1_updt_curdesc_wren : std_logic := '0';
signal ch1_updt_curdesc : std_logic_vector
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0');
signal ch1_updt_ioc : std_logic := '0';
signal ch1_updt_ioc_irq_set_i : std_logic := '0';
signal ch1_dma_interr : std_logic := '0';
signal ch1_dma_slverr : std_logic := '0';
signal ch1_dma_decerr : std_logic := '0';
signal ch1_dma_interr_set_i : std_logic := '0';
signal ch1_dma_slverr_set_i : std_logic := '0';
signal ch1_dma_decerr_set_i : std_logic := '0';
signal ch1_updt_done : std_logic := '0';
signal ch1_ftch_pause : std_logic := '0';
-- Channel 2 internals
signal ch2_ftch_active : std_logic := '0';
signal ch2_ftch_queue_empty : std_logic := '0';
signal ch2_ftch_queue_full : std_logic := '0';
signal ch2_nxtdesc_wren : std_logic := '0';
signal ch2_updt_active : std_logic := '0';
signal ch2_updt_queue_empty : std_logic := '0';
signal ch2_updt_curdesc_wren : std_logic := '0';
signal ch2_updt_curdesc : std_logic_vector
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0');
signal ch2_updt_ioc : std_logic := '0';
signal ch2_updt_ioc_irq_set_i : std_logic := '0';
signal ch2_dma_interr : std_logic := '0';
signal ch2_dma_slverr : std_logic := '0';
signal ch2_dma_decerr : std_logic := '0';
signal ch2_dma_interr_set_i : std_logic := '0';
signal ch2_dma_slverr_set_i : std_logic := '0';
signal ch2_dma_decerr_set_i : std_logic := '0';
signal ch2_updt_done : std_logic := '0';
signal ch2_ftch_pause : std_logic := '0';
signal nxtdesc : std_logic_vector
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0');
signal ftch_cmnd_wr : std_logic := '0';
signal ftch_cmnd_data : std_logic_vector
((C_M_AXI_SG_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0) := (others => '0');
signal ftch_stale_desc : std_logic := '0';
signal ftch_error_i : std_logic := '0';
signal updt_error_i : std_logic := '0';
signal ch1_irqthresh_decr : std_logic := '0'; --CR567661
signal ch2_irqthresh_decr : std_logic := '0'; --CR567661
signal m_axi_sg_awaddr_int : std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
signal m_axi_sg_awlen_int : std_logic_vector(7 downto 0) ; --
signal m_axi_sg_awsize_int : std_logic_vector(2 downto 0) ; --
signal m_axi_sg_awburst_int : std_logic_vector(1 downto 0) ; --
signal m_axi_sg_awprot_int : std_logic_vector(2 downto 0) ; --
signal m_axi_sg_awcache_int : std_logic_vector(3 downto 0) ; --
signal m_axi_sg_awuser_int : std_logic_vector(3 downto 0) ; --
signal m_axi_sg_awvalid_int : std_logic ; --
signal m_axi_sg_awready_int : std_logic ; --
--
-- Scatter Gather Write Data Channel --
signal m_axi_sg_wdata_int : std_logic_vector --
(C_M_AXI_SG_DATA_WIDTH-1 downto 0) ; --
signal m_axi_sg_wstrb_int : std_logic_vector --
((C_M_AXI_SG_DATA_WIDTH/8)-1 downto 0); --
signal m_axi_sg_wlast_int : std_logic ; --
signal m_axi_sg_wvalid_int : std_logic ; --
signal m_axi_sg_wready_int : std_logic ; --
signal m_axi_sg_bresp_int : std_logic_vector (1 downto 0);
signal m_axi_sg_bvalid_int : std_logic;
signal m_axi_sg_bready_int : std_logic;
signal m_axi_sg_bvalid_int_del : std_logic;
signal ch2_eof_detected : std_logic;
signal s_axis_ch2_updtsts_tready_i : std_logic;
signal ch2_sg_idle, tail_updt_latch : std_logic;
signal tail_updt : std_logic;
signal ch2_taildesc_wren_int : std_logic;
signal ch2_sg_idle_int : std_logic;
signal ftch_error_addr_1 : std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ;
signal updt_error_addr_1 : std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ;
signal ch1_ftch_interr_set_i : std_logic := '0';
signal ch1_ftch_slverr_set_i : std_logic := '0';
signal ch1_ftch_decerr_set_i : std_logic := '0';
signal ch2_ftch_interr_set_i : std_logic := '0';
signal ch2_ftch_slverr_set_i : std_logic := '0';
signal ch2_ftch_decerr_set_i : std_logic := '0';
signal ch1_updt_interr_set_i : std_logic := '0';
signal ch1_updt_slverr_set_i : std_logic := '0';
signal ch1_updt_decerr_set_i : std_logic := '0';
signal ch2_updt_interr_set_i : std_logic := '0';
signal ch2_updt_slverr_set_i : std_logic := '0';
signal ch2_updt_decerr_set_i : std_logic := '0';
signal ftch_error_capture : std_logic := '0';
signal updt_error_capture : std_logic := '0';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
updt_error <= updt_error_i;
ftch_error <= ftch_error_i;
ftch_error_capture <= ch1_ftch_interr_set_i or
ch1_ftch_slverr_set_i or
ch1_ftch_decerr_set_i or
ch2_ftch_interr_set_i or
ch2_ftch_slverr_set_i or
ch2_ftch_decerr_set_i;
ch1_ftch_interr_set <= ch1_ftch_interr_set_i;
ch1_ftch_slverr_set <= ch1_ftch_slverr_set_i;
ch1_ftch_decerr_set <= ch1_ftch_decerr_set_i;
ch2_ftch_interr_set <= ch2_ftch_interr_set_i;
ch2_ftch_slverr_set <= ch2_ftch_slverr_set_i;
ch2_ftch_decerr_set <= ch2_ftch_decerr_set_i;
updt_error_capture <= ch1_updt_interr_set_i or
ch1_updt_slverr_set_i or
ch1_updt_decerr_set_i or
ch2_updt_interr_set_i or
ch2_updt_slverr_set_i or
ch2_updt_decerr_set_i or
ch2_dma_interr_set_i or
ch2_dma_slverr_set_i or
ch2_dma_decerr_set_i or
ch1_dma_interr_set_i or
ch1_dma_slverr_set_i or
ch1_dma_decerr_set_i;
ch1_updt_interr_set <= ch1_updt_interr_set_i;
ch1_updt_slverr_set <= ch1_updt_slverr_set_i;
ch1_updt_decerr_set <= ch1_updt_decerr_set_i;
ch2_updt_interr_set <= ch2_updt_interr_set_i;
ch2_updt_slverr_set <= ch2_updt_slverr_set_i;
ch2_updt_decerr_set <= ch2_updt_decerr_set_i;
process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (m_axi_sg_aresetn = '0') then
ftch_error_addr (31 downto 6) <= (others => '0');
elsif (ftch_error_capture = '1') then -- or updt_error_i = '1') then
ftch_error_addr (31 downto 6)<= ftch_error_addr_1(31 downto 6);
elsif (updt_error_capture = '1') then
ftch_error_addr (31 downto 6)<= updt_error_addr_1(31 downto 6);
end if;
end if;
end process;
ADDR_64 : if (C_M_AXI_SG_ADDR_WIDTH > 32) generate
begin
process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (m_axi_sg_aresetn = '0') then
ftch_error_addr (63 downto 32) <= (others => '0');
elsif (ftch_error_capture = '1') then -- or updt_error_i = '1') then
ftch_error_addr (63 downto 32)<= ftch_error_addr_1(63 downto 32);
elsif (updt_error_capture = '1') then
ftch_error_addr (63 downto 32)<= updt_error_addr_1(63 downto 32);
end if;
end if;
end process;
end generate ADDR_64;
updt_error_addr <= (others => '0');
ftch_error_addr (5 downto 0) <= (others => '0');
-- Always valid therefore fix to '1'
s_axis_s2mm_tkeep <= (others => '1');
-- Drive interrupt on complete set out
--ch1_updt_ioc_irq_set <= ch1_updt_ioc_irq_set_i; -- CR567661
--ch2_updt_ioc_irq_set <= ch2_updt_ioc_irq_set_i; -- CR567661
ch1_dma_interr_set <= ch1_dma_interr_set_i;
ch1_dma_slverr_set <= ch1_dma_slverr_set_i;
ch1_dma_decerr_set <= ch1_dma_decerr_set_i;
ch2_dma_interr_set <= ch2_dma_interr_set_i;
ch2_dma_slverr_set <= ch2_dma_slverr_set_i;
ch2_dma_decerr_set <= ch2_dma_decerr_set_i;
s_axis_ch2_updtsts_tready <= s_axis_ch2_updtsts_tready_i;
EOF_DET : if (C_ENABLE_MULTI_CHANNEL = 1) generate
ch2_eof_detected <= s_axis_ch2_updtsts_tdata (26)
and s_axis_ch2_updtsts_tready_i
and s_axis_ch2_updtsts_tvalid
and s_axis_ch2_updtsts_tlast;
-- ch2_eof_detected <= '0';
ch2_sg_idle_int <= ch2_sg_idle;
-- ch2_sg_idle_int <= '0'; --ch2_sg_idle;
TAILUPDT_LATCH : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or tail_updt = '1' ) then -- nned to have some reset condition here
tail_updt <= '0';
elsif(ch2_sg_idle = '1' and tail_updt_latch = '1' and tail_updt = '0')then
tail_updt <= '1';
end if;
end if;
end process TAILUPDT_LATCH;
ch2_taildesc_wren_int <= ch2_taildesc_wren or tail_updt;
--ch2_taildesc_wren_int <= ch2_taildesc_wren;
end generate EOF_DET;
NOEOF_DET : if (C_ENABLE_MULTI_CHANNEL = 0) generate
tail_updt <= '0';
ch2_eof_detected <= '0';
ch2_taildesc_wren_int <= ch2_taildesc_wren;
ch2_sg_idle_int <= '0'; --ch2_sg_idle;
end generate NOEOF_DET;
-------------------------------------------------------------------------------
-- Scatter Gather Fetch Manager
-------------------------------------------------------------------------------
I_SG_FETCH_MNGR : entity axi_sg_v4_1.axi_sg_ftch_mngr
generic map(
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH ,
C_ENABLE_MULTI_CHANNEL => C_ENABLE_MULTI_CHANNEL ,
C_INCLUDE_CH1 => C_INCLUDE_CH1 ,
C_INCLUDE_CH2 => C_INCLUDE_CH2 ,
C_SG_CH1_WORDS_TO_FETCH => C_SG_CH1_WORDS_TO_FETCH ,
C_SG_CH2_WORDS_TO_FETCH => C_SG_CH2_WORDS_TO_FETCH ,
C_SG_CH1_ENBL_STALE_ERROR => C_SG_CH1_ENBL_STALE_ERROR ,
C_SG_CH2_ENBL_STALE_ERROR => C_SG_CH2_ENBL_STALE_ERROR ,
C_SG_FTCH_DESC2QUEUE => SG_FTCH_DESC2QUEUE
)
port map(
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
-- Channel 1 Control and Status
ch1_run_stop => ch1_run_stop ,
ch1_desc_flush => ch1_desc_flush ,
ch1_updt_done => ch1_updt_done ,
ch1_ftch_idle => ch1_ftch_idle ,
ch1_ftch_active => ch1_ftch_active ,
ch1_ftch_interr_set => ch1_ftch_interr_set_i ,
ch1_ftch_slverr_set => ch1_ftch_slverr_set_i ,
ch1_ftch_decerr_set => ch1_ftch_decerr_set_i ,
ch1_ftch_err_early => ch1_ftch_err_early ,
ch1_ftch_stale_desc => ch1_ftch_stale_desc ,
ch1_tailpntr_enabled => ch1_tailpntr_enabled ,
ch1_taildesc_wren => ch1_taildesc_wren ,
ch1_taildesc => ch1_taildesc ,
ch1_nxtdesc_wren => ch1_nxtdesc_wren ,
ch1_curdesc => ch1_curdesc ,
ch1_ftch_queue_empty => ch1_ftch_queue_empty ,
ch1_ftch_queue_full => ch1_ftch_queue_full ,
ch1_ftch_pause => ch1_ftch_pause ,
-- Channel 2 Control and Status
ch2_run_stop => ch2_run_stop ,
ch2_desc_flush => ch2_desc_flush ,
ch2_updt_done => ch2_updt_done ,
ch2_ftch_idle => ch2_ftch_idle ,
ch2_ftch_active => ch2_ftch_active ,
ch2_ftch_interr_set => ch2_ftch_interr_set_i ,
ch2_ftch_slverr_set => ch2_ftch_slverr_set_i ,
ch2_ftch_decerr_set => ch2_ftch_decerr_set_i ,
ch2_ftch_err_early => ch2_ftch_err_early ,
ch2_ftch_stale_desc => ch2_ftch_stale_desc ,
ch2_tailpntr_enabled => ch2_tailpntr_enabled ,
ch2_taildesc_wren => ch2_taildesc_wren_int ,
ch2_taildesc => ch2_taildesc ,
ch2_nxtdesc_wren => ch2_nxtdesc_wren ,
ch2_curdesc => ch2_curdesc ,
ch2_ftch_queue_empty => ch2_ftch_queue_empty ,
ch2_ftch_queue_full => ch2_ftch_queue_full ,
ch2_ftch_pause => ch2_ftch_pause ,
ch2_eof_detected => ch2_eof_detected ,
tail_updt => tail_updt ,
tail_updt_latch => tail_updt_latch ,
ch2_sg_idle => ch2_sg_idle ,
nxtdesc => nxtdesc ,
-- Read response for detecting slverr, decerr early
m_axi_sg_rresp => m_axi_sg_rresp ,
m_axi_sg_rvalid => m_axi_sg_rvalid ,
-- User Command Interface Ports (AXI Stream)
s_axis_ftch_cmd_tvalid => s_axis_ftch_cmd_tvalid ,
s_axis_ftch_cmd_tready => s_axis_ftch_cmd_tready ,
s_axis_ftch_cmd_tdata => s_axis_ftch_cmd_tdata ((C_M_AXI_SG_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0) ,
-- User Status Interface Ports (AXI Stream)
m_axis_ftch_sts_tvalid => m_axis_ftch_sts_tvalid ,
m_axis_ftch_sts_tready => m_axis_ftch_sts_tready ,
m_axis_ftch_sts_tdata => m_axis_ftch_sts_tdata ,
m_axis_ftch_sts_tkeep => m_axis_ftch_sts_tkeep ,
mm2s_err => mm2s_err ,
-- DataMover Command
ftch_cmnd_wr => ftch_cmnd_wr ,
ftch_cmnd_data => ftch_cmnd_data ,
ftch_stale_desc => ftch_stale_desc ,
updt_error => updt_error_i ,
ftch_error => ftch_error_i ,
ftch_error_addr => ftch_error_addr_1 ,
bd_eq => bd_eq
);
-------------------------------------------------------------------------------
-- Scatter Gather Fetch Queue
-------------------------------------------------------------------------------
I_SG_FETCH_QUEUE : entity axi_sg_v4_1.axi_sg_ftch_q_mngr
generic map(
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH ,
C_M_AXIS_SG_TDATA_WIDTH => C_M_AXIS_SG_TDATA_WIDTH ,
C_SG_FTCH_DESC2QUEUE => SG_FTCH_DESC2QUEUE ,
C_SG_CH1_WORDS_TO_FETCH => C_SG_CH1_WORDS_TO_FETCH ,
C_SG_CH2_WORDS_TO_FETCH => C_SG_CH2_WORDS_TO_FETCH ,
C_SG_CH1_ENBL_STALE_ERROR => C_SG_CH1_ENBL_STALE_ERROR ,
C_SG_CH2_ENBL_STALE_ERROR => C_SG_CH2_ENBL_STALE_ERROR ,
C_ENABLE_MULTI_CHANNEL => C_ENABLE_MULTI_CHANNEL ,
C_INCLUDE_CH1 => C_INCLUDE_CH1 ,
C_INCLUDE_CH2 => C_INCLUDE_CH2 ,
C_AXIS_IS_ASYNC => C_AXIS_IS_ASYNC ,
C_ASYNC => C_ASYNC ,
C_ENABLE_CDMA => C_ENABLE_CDMA,
C_ACTUAL_ADDR => C_ACTUAL_ADDR,
C_FAMILY => C_FAMILY
)
port map(
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_mm2s_aclk => m_axi_mm2s_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
p_reset_n => p_reset_n ,
ch2_sg_idle => ch2_sg_idle_int ,
-- Channel 1 Control
ch1_desc_flush => ch1_desc_flush ,
ch1_cyclic => ch1_cyclic ,
ch1_cntrl_strm_stop => ch1_cntrl_strm_stop ,
ch1_ftch_active => ch1_ftch_active ,
ch1_nxtdesc_wren => ch1_nxtdesc_wren ,
ch1_ftch_queue_empty => ch1_ftch_queue_empty ,
ch1_ftch_queue_full => ch1_ftch_queue_full ,
ch1_ftch_pause => ch1_ftch_pause ,
-- Channel 2 Control
ch2_ftch_active => ch2_ftch_active ,
ch2_cyclic => ch2_cyclic ,
ch2_desc_flush => ch2_desc_flush ,
ch2_nxtdesc_wren => ch2_nxtdesc_wren ,
ch2_ftch_queue_empty => ch2_ftch_queue_empty ,
ch2_ftch_queue_full => ch2_ftch_queue_full ,
ch2_ftch_pause => ch2_ftch_pause ,
nxtdesc => nxtdesc ,
-- DataMover Command
ftch_cmnd_wr => ftch_cmnd_wr ,
ftch_cmnd_data => ftch_cmnd_data ,
ftch_stale_desc => ftch_stale_desc ,
-- MM2S Stream In from DataMover
m_axis_mm2s_tdata => m_axis_mm2s_tdata ,
m_axis_mm2s_tkeep => m_axis_mm2s_tkeep ,
m_axis_mm2s_tlast => m_axis_mm2s_tlast ,
m_axis_mm2s_tvalid => m_axis_mm2s_tvalid ,
m_axis_mm2s_tready => m_axis_mm2s_tready ,
-- Channel 1 AXI Fetch Stream Out
m_axis_ch1_ftch_aclk => m_axis_ch1_ftch_aclk ,
m_axis_ch1_ftch_tdata => m_axis_ch1_ftch_tdata ,
m_axis_ch1_ftch_tvalid => m_axis_ch1_ftch_tvalid ,
m_axis_ch1_ftch_tready => m_axis_ch1_ftch_tready ,
m_axis_ch1_ftch_tlast => m_axis_ch1_ftch_tlast ,
m_axis_ch1_ftch_tdata_new => m_axis_ch1_ftch_tdata_new ,
m_axis_ch1_ftch_tdata_mcdma_new => m_axis_ch1_ftch_tdata_mcdma_new ,
m_axis_ch1_ftch_tvalid_new => m_axis_ch1_ftch_tvalid_new ,
m_axis_ftch1_desc_available => m_axis_ftch1_desc_available,
m_axis_ch2_ftch_tdata_new => m_axis_ch2_ftch_tdata_new ,
m_axis_ch2_ftch_tdata_mcdma_new => m_axis_ch2_ftch_tdata_mcdma_new ,
m_axis_ch2_ftch_tdata_mcdma_nxt => m_axis_ch2_ftch_tdata_mcdma_nxt ,
m_axis_ch2_ftch_tvalid_new => m_axis_ch2_ftch_tvalid_new ,
m_axis_ftch2_desc_available => m_axis_ftch2_desc_available,
-- Channel 2 AXI Fetch Stream Out
m_axis_ch2_ftch_aclk => m_axis_ch2_ftch_aclk ,
m_axis_ch2_ftch_tdata => m_axis_ch2_ftch_tdata ,
m_axis_ch2_ftch_tvalid => m_axis_ch2_ftch_tvalid ,
m_axis_ch2_ftch_tready => m_axis_ch2_ftch_tready ,
m_axis_ch2_ftch_tlast => m_axis_ch2_ftch_tlast ,
m_axis_mm2s_cntrl_tdata => m_axis_mm2s_cntrl_tdata ,
m_axis_mm2s_cntrl_tkeep => m_axis_mm2s_cntrl_tkeep ,
m_axis_mm2s_cntrl_tvalid => m_axis_mm2s_cntrl_tvalid ,
m_axis_mm2s_cntrl_tready => m_axis_mm2s_cntrl_tready ,
m_axis_mm2s_cntrl_tlast => m_axis_mm2s_cntrl_tlast
);
-- Include Scatter Gather Descriptor Update logic
GEN_DESC_UPDATE : if C_INCLUDE_DESC_UPDATE = 1 generate
begin
-- CR567661
-- Route update version of IOC set to threshold
-- counter decrement control
ch1_irqthresh_decr <= ch1_updt_ioc_irq_set_i;
ch2_irqthresh_decr <= ch2_updt_ioc_irq_set_i;
-- Drive interrupt on complete set out
ch1_updt_ioc_irq_set <= ch1_updt_ioc_irq_set_i;
ch2_updt_ioc_irq_set <= ch2_updt_ioc_irq_set_i;
-------------------------------------------------------------------------------
-- Scatter Gather Update Manager
-------------------------------------------------------------------------------
I_SG_UPDATE_MNGR : entity axi_sg_v4_1.axi_sg_updt_mngr
generic map(
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH ,
C_INCLUDE_CH1 => C_INCLUDE_CH1 ,
C_INCLUDE_CH2 => C_INCLUDE_CH2 ,
C_SG_CH1_WORDS_TO_UPDATE => C_SG_CH1_WORDS_TO_UPDATE ,
C_SG_CH1_FIRST_UPDATE_WORD => C_SG_CH1_FIRST_UPDATE_WORD ,
C_SG_CH2_WORDS_TO_UPDATE => C_SG_CH2_WORDS_TO_UPDATE ,
C_SG_CH2_FIRST_UPDATE_WORD => C_SG_CH2_FIRST_UPDATE_WORD
)
port map(
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
-- Channel 1 Control and Status
ch1_updt_idle => ch1_updt_idle ,
ch1_updt_active => ch1_updt_active ,
ch1_updt_ioc => ch1_updt_ioc ,
ch1_updt_ioc_irq_set => ch1_updt_ioc_irq_set_i ,
-- Update Descriptor Status
ch1_dma_interr => ch1_dma_interr ,
ch1_dma_slverr => ch1_dma_slverr ,
ch1_dma_decerr => ch1_dma_decerr ,
ch1_dma_interr_set => ch1_dma_interr_set_i ,
ch1_dma_slverr_set => ch1_dma_slverr_set_i ,
ch1_dma_decerr_set => ch1_dma_decerr_set_i ,
ch1_updt_interr_set => ch1_updt_interr_set_i ,
ch1_updt_slverr_set => ch1_updt_slverr_set_i ,
ch1_updt_decerr_set => ch1_updt_decerr_set_i ,
ch1_updt_queue_empty => ch1_updt_queue_empty ,
ch1_updt_curdesc_wren => ch1_updt_curdesc_wren ,
ch1_updt_curdesc => ch1_updt_curdesc ,
ch1_updt_done => ch1_updt_done ,
-- Channel 2 Control and Status
ch2_dma_interr => ch2_dma_interr ,
ch2_dma_slverr => ch2_dma_slverr ,
ch2_dma_decerr => ch2_dma_decerr ,
ch2_updt_idle => ch2_updt_idle ,
ch2_updt_active => ch2_updt_active ,
ch2_updt_ioc => ch2_updt_ioc ,
ch2_updt_ioc_irq_set => ch2_updt_ioc_irq_set_i ,
ch2_dma_interr_set => ch2_dma_interr_set_i ,
ch2_dma_slverr_set => ch2_dma_slverr_set_i ,
ch2_dma_decerr_set => ch2_dma_decerr_set_i ,
ch2_updt_interr_set => ch2_updt_interr_set_i ,
ch2_updt_slverr_set => ch2_updt_slverr_set_i ,
ch2_updt_decerr_set => ch2_updt_decerr_set_i ,
ch2_updt_queue_empty => ch2_updt_queue_empty ,
-- ch2_updt_curdesc_wren => ch2_updt_curdesc_wren ,
-- ch2_updt_curdesc => ch2_updt_curdesc ,
ch2_updt_done => ch2_updt_done ,
-- User Command Interface Ports (AXI Stream)
s_axis_updt_cmd_tvalid => s_axis_updt_cmd_tvalid ,
s_axis_updt_cmd_tready => s_axis_updt_cmd_tready ,
s_axis_updt_cmd_tdata => s_axis_updt_cmd_tdata ((C_M_AXI_SG_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0) ,
-- User Status Interface Ports (AXI Stream)
m_axis_updt_sts_tvalid => m_axis_updt_sts_tvalid ,
m_axis_updt_sts_tready => m_axis_updt_sts_tready ,
m_axis_updt_sts_tdata => m_axis_updt_sts_tdata ,
m_axis_updt_sts_tkeep => m_axis_updt_sts_tkeep ,
s2mm_err => s2mm_err ,
ftch_error => ftch_error_i ,
updt_error => updt_error_i ,
updt_error_addr => updt_error_addr_1
);
-------------------------------------------------------------------------------
-- Scatter Gather Update Queue
-------------------------------------------------------------------------------
I_SG_UPDATE_QUEUE : entity axi_sg_v4_1.axi_sg_updt_q_mngr
generic map(
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH ,
C_M_AXI_SG_DATA_WIDTH => C_M_AXI_SG_DATA_WIDTH ,
C_S_AXIS_UPDPTR_TDATA_WIDTH => C_S_AXIS_UPDPTR_TDATA_WIDTH ,
C_S_AXIS_UPDSTS_TDATA_WIDTH => C_S_AXIS_UPDSTS_TDATA_WIDTH ,
C_SG_UPDT_DESC2QUEUE => SG_UPDT_DESC2QUEUE ,
C_SG_CH1_WORDS_TO_UPDATE => C_SG_CH1_WORDS_TO_UPDATE ,
C_SG_CH2_WORDS_TO_UPDATE => C_SG_CH2_WORDS_TO_UPDATE ,
C_INCLUDE_CH1 => C_INCLUDE_CH1 ,
C_INCLUDE_CH2 => C_INCLUDE_CH2 ,
C_AXIS_IS_ASYNC => C_AXIS_IS_ASYNC ,
C_FAMILY => C_FAMILY
)
port map(
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
-- Channel 1 Control
ch1_updt_curdesc_wren => ch1_updt_curdesc_wren ,
ch1_updt_curdesc => ch1_updt_curdesc ,
ch1_updt_active => ch1_updt_active ,
ch1_updt_queue_empty => ch1_updt_queue_empty ,
ch1_updt_ioc => ch1_updt_ioc ,
ch1_updt_ioc_irq_set => ch1_updt_ioc_irq_set_i ,
-- Channel 1 Update Descriptor Status
ch1_dma_interr => ch1_dma_interr ,
ch1_dma_slverr => ch1_dma_slverr ,
ch1_dma_decerr => ch1_dma_decerr ,
ch1_dma_interr_set => ch1_dma_interr_set_i ,
ch1_dma_slverr_set => ch1_dma_slverr_set_i ,
ch1_dma_decerr_set => ch1_dma_decerr_set_i ,
-- Channel 2 Control
ch2_updt_active => ch2_updt_active ,
-- ch2_updt_curdesc_wren => ch2_updt_curdesc_wren ,
-- ch2_updt_curdesc => ch2_updt_curdesc ,
ch2_updt_queue_empty => ch2_updt_queue_empty ,
ch2_updt_ioc => ch2_updt_ioc ,
ch2_updt_ioc_irq_set => ch2_updt_ioc_irq_set_i ,
-- Channel 2 Update Descriptor Status
ch2_dma_interr => ch2_dma_interr ,
ch2_dma_slverr => ch2_dma_slverr ,
ch2_dma_decerr => ch2_dma_decerr ,
ch2_dma_interr_set => ch2_dma_interr_set_i ,
ch2_dma_slverr_set => ch2_dma_slverr_set_i ,
ch2_dma_decerr_set => ch2_dma_decerr_set_i ,
-- S2MM Stream Out To DataMover
s_axis_s2mm_tdata => s_axis_s2mm_tdata ,
s_axis_s2mm_tlast => s_axis_s2mm_tlast ,
s_axis_s2mm_tvalid => s_axis_s2mm_tvalid ,
s_axis_s2mm_tready => s_axis_s2mm_tready ,
-- Channel 1 AXI Update Stream In
s_axis_ch1_updt_aclk => s_axis_ch1_updt_aclk ,
s_axis_ch1_updtptr_tdata => s_axis_ch1_updtptr_tdata ,
s_axis_ch1_updtptr_tvalid => s_axis_ch1_updtptr_tvalid ,
s_axis_ch1_updtptr_tready => s_axis_ch1_updtptr_tready ,
s_axis_ch1_updtptr_tlast => s_axis_ch1_updtptr_tlast ,
s_axis_ch1_updtsts_tdata => s_axis_ch1_updtsts_tdata ,
s_axis_ch1_updtsts_tvalid => s_axis_ch1_updtsts_tvalid ,
s_axis_ch1_updtsts_tready => s_axis_ch1_updtsts_tready ,
s_axis_ch1_updtsts_tlast => s_axis_ch1_updtsts_tlast ,
-- Channel 2 AXI Update Stream In
s_axis_ch2_updt_aclk => s_axis_ch2_updt_aclk ,
s_axis_ch2_updtptr_tdata => s_axis_ch2_updtptr_tdata ,
s_axis_ch2_updtptr_tvalid => s_axis_ch2_updtptr_tvalid ,
s_axis_ch2_updtptr_tready => s_axis_ch2_updtptr_tready ,
s_axis_ch2_updtptr_tlast => s_axis_ch2_updtptr_tlast ,
s_axis_ch2_updtsts_tdata => s_axis_ch2_updtsts_tdata ,
s_axis_ch2_updtsts_tvalid => s_axis_ch2_updtsts_tvalid ,
s_axis_ch2_updtsts_tready => s_axis_ch2_updtsts_tready_i ,
s_axis_ch2_updtsts_tlast => s_axis_ch2_updtsts_tlast
);
end generate GEN_DESC_UPDATE;
-- Exclude Scatter Gather Descriptor Update logic
GEN_NO_DESC_UPDATE : if C_INCLUDE_DESC_UPDATE = 0 generate
begin
ch1_updt_idle <= '1';
ch1_updt_active <= '0';
-- ch1_updt_ioc_irq_set <= '0';--CR#569609
ch1_updt_interr_set <= '0';
ch1_updt_slverr_set <= '0';
ch1_updt_decerr_set <= '0';
ch1_dma_interr_set_i <= '0';
ch1_dma_slverr_set_i <= '0';
ch1_dma_decerr_set_i <= '0';
ch1_updt_done <= '1'; -- Always done
ch2_updt_idle <= '1';
ch2_updt_active <= '0';
-- ch2_updt_ioc_irq_set <= '0'; --CR#569609
ch2_updt_interr_set <= '0';
ch2_updt_slverr_set <= '0';
ch2_updt_decerr_set <= '0';
ch2_dma_interr_set_i <= '0';
ch2_dma_slverr_set_i <= '0';
ch2_dma_decerr_set_i <= '0';
ch2_updt_done <= '1'; -- Always done
s_axis_updt_cmd_tvalid <= '0';
s_axis_updt_cmd_tdata <= (others => '0');
m_axis_updt_sts_tready <= '0';
updt_error_i <= '0';
updt_error_addr <= (others => '0');
ch1_updt_curdesc_wren <= '0';
ch1_updt_curdesc <= (others => '0');
ch1_updt_queue_empty <= '0';
ch1_updt_ioc <= '0';
ch1_dma_interr <= '0';
ch1_dma_slverr <= '0';
ch1_dma_decerr <= '0';
ch2_updt_curdesc_wren <= '0';
ch2_updt_curdesc <= (others => '0');
ch2_updt_queue_empty <= '0';
ch2_updt_ioc <= '0';
ch2_dma_interr <= '0';
ch2_dma_slverr <= '0';
ch2_dma_decerr <= '0';
s_axis_s2mm_tdata <= (others => '0');
s_axis_s2mm_tlast <= '0';
s_axis_s2mm_tvalid <= '0';
s_axis_ch1_updtptr_tready <= '0';
s_axis_ch2_updtptr_tready <= '0';
s_axis_ch1_updtsts_tready <= '0';
s_axis_ch2_updtsts_tready <= '0';
-- CR567661
-- Route packet eof to threshold counter decrement control
ch1_irqthresh_decr <= ch1_packet_eof;
ch2_irqthresh_decr <= ch2_packet_eof;
-- Drive interrupt on complete set out
ch1_updt_ioc_irq_set <= ch1_packet_eof;
ch2_updt_ioc_irq_set <= ch2_packet_eof;
end generate GEN_NO_DESC_UPDATE;
-------------------------------------------------------------------------------
-- Scatter Gather Interrupt Coalescing
-------------------------------------------------------------------------------
GEN_INTERRUPT_LOGIC : if C_INCLUDE_INTRPT = 1 generate
begin
I_AXI_SG_INTRPT : entity axi_sg_v4_1.axi_sg_intrpt
generic map(
C_INCLUDE_CH1 => C_INCLUDE_CH1 ,
C_INCLUDE_CH2 => C_INCLUDE_CH2 ,
C_INCLUDE_DLYTMR => C_INCLUDE_DLYTMR ,
C_DLYTMR_RESOLUTION => C_DLYTMR_RESOLUTION
)
port map(
-- Secondary Clock and Reset
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
ch1_irqthresh_decr => ch1_irqthresh_decr , -- CR567661
ch1_irqthresh_rstdsbl => ch1_irqthresh_rstdsbl , -- CR572013
ch1_dlyirq_dsble => ch1_dlyirq_dsble ,
ch1_irqdelay_wren => ch1_irqdelay_wren ,
ch1_irqdelay => ch1_irqdelay ,
ch1_irqthresh_wren => ch1_irqthresh_wren ,
ch1_irqthresh => ch1_irqthresh ,
ch1_packet_sof => ch1_packet_sof ,
ch1_packet_eof => ch1_packet_eof ,
ch1_ioc_irq_set => ch1_ioc_irq_set ,
ch1_dly_irq_set => ch1_dly_irq_set ,
ch1_irqdelay_status => ch1_irqdelay_status ,
ch1_irqthresh_status => ch1_irqthresh_status ,
ch2_irqthresh_decr => ch2_irqthresh_decr , -- CR567661
ch2_irqthresh_rstdsbl => ch2_irqthresh_rstdsbl , -- CR572013
ch2_dlyirq_dsble => ch2_dlyirq_dsble ,
ch2_irqdelay_wren => ch2_irqdelay_wren ,
ch2_irqdelay => ch2_irqdelay ,
ch2_irqthresh_wren => ch2_irqthresh_wren ,
ch2_irqthresh => ch2_irqthresh ,
ch2_packet_sof => ch2_packet_sof ,
ch2_packet_eof => ch2_packet_eof ,
ch2_ioc_irq_set => ch2_ioc_irq_set ,
ch2_dly_irq_set => ch2_dly_irq_set ,
ch2_irqdelay_status => ch2_irqdelay_status ,
ch2_irqthresh_status => ch2_irqthresh_status
);
end generate GEN_INTERRUPT_LOGIC;
GEN_NO_INTRPT_LOGIC : if C_INCLUDE_INTRPT = 0 generate
begin
ch1_ioc_irq_set <= '0';
ch1_dly_irq_set <= '0';
ch1_irqdelay_status <= (others => '0');
ch1_irqthresh_status <= (others => '0');
ch2_ioc_irq_set <= '0';
ch2_dly_irq_set <= '0';
ch2_irqdelay_status <= (others => '0');
ch2_irqthresh_status <= (others => '0');
end generate GEN_NO_INTRPT_LOGIC;
-------------------------------------------------------------------------------
-- Scatter Gather DataMover Lite
-------------------------------------------------------------------------------
I_SG_AXI_DATAMOVER : entity axi_sg_v4_1.axi_sg_datamover
generic map(
C_INCLUDE_MM2S => 2, --INCLUDE_DESC_FETCH, -- Lite
C_M_AXI_MM2S_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH, -- 32 or 64
C_M_AXI_MM2S_DATA_WIDTH => C_M_AXI_SG_DATA_WIDTH, -- Fixed at 32
C_M_AXIS_MM2S_TDATA_WIDTH => C_M_AXI_SG_DATA_WIDTH, -- Fixed at 32
C_INCLUDE_MM2S_STSFIFO => 0, -- Exclude
C_MM2S_STSCMD_FIFO_DEPTH => 1, -- Set to Min
C_MM2S_STSCMD_IS_ASYNC => 0, -- Synchronous
C_INCLUDE_MM2S_DRE => 0, -- No DRE
C_MM2S_BURST_SIZE => 16, -- Set to Min
C_MM2S_ADDR_PIPE_DEPTH => 1, -- Only 1 outstanding request
C_MM2S_INCLUDE_SF => 0, -- Exclude Store-and-Forward
C_ENABLE_MULTI_CHANNEL => C_ENABLE_MULTI_CHANNEL, --
C_ENABLE_EXTRA_FIELD => C_ENABLE_EXTRA_FIELD,
C_INCLUDE_S2MM => 2, --INCLUDE_DESC_UPDATE, -- Lite
C_M_AXI_S2MM_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH, -- 32 or 64
C_M_AXI_S2MM_DATA_WIDTH => C_M_AXI_SG_DATA_WIDTH, -- Fixed at 32
C_S_AXIS_S2MM_TDATA_WIDTH => C_M_AXI_SG_DATA_WIDTH, -- Fixed at 32
C_INCLUDE_S2MM_STSFIFO => 0, -- Exclude
C_S2MM_STSCMD_FIFO_DEPTH => 1, -- Set to Min
C_S2MM_STSCMD_IS_ASYNC => 0, -- Synchronous
C_INCLUDE_S2MM_DRE => 0, -- No DRE
C_S2MM_BURST_SIZE => 16, -- Set to Min;
C_S2MM_ADDR_PIPE_DEPTH => 1, -- Only 1 outstanding request
C_S2MM_INCLUDE_SF => 0, -- Exclude Store-and-Forward
C_FAMILY => C_FAMILY
)
port map(
-- MM2S Primary Clock / Reset input
m_axi_mm2s_aclk => m_axi_sg_aclk ,
m_axi_mm2s_aresetn => dm_resetn ,
mm2s_halt => NEVER_HALT ,
mm2s_halt_cmplt => open ,
mm2s_err => mm2s_err ,
mm2s_allow_addr_req => ALWAYS_ALLOW ,
mm2s_addr_req_posted => open ,
mm2s_rd_xfer_cmplt => open ,
sg_ctl => sg_ctl ,
-- Memory Map to Stream Command FIFO and Status FIFO I/O --------------
m_axis_mm2s_cmdsts_aclk => m_axi_sg_aclk ,
m_axis_mm2s_cmdsts_aresetn => dm_resetn ,
-- User Command Interface Ports (AXI Stream)
s_axis_mm2s_cmd_tvalid => s_axis_ftch_cmd_tvalid ,
s_axis_mm2s_cmd_tready => s_axis_ftch_cmd_tready ,
s_axis_mm2s_cmd_tdata => s_axis_ftch_cmd_tdata ,
-- User Status Interface Ports (AXI Stream)
m_axis_mm2s_sts_tvalid => m_axis_ftch_sts_tvalid ,
m_axis_mm2s_sts_tready => m_axis_ftch_sts_tready ,
m_axis_mm2s_sts_tdata => m_axis_ftch_sts_tdata ,
m_axis_mm2s_sts_tkeep => m_axis_ftch_sts_tkeep ,
-- MM2S AXI Address Channel I/O --------------------------------------
m_axi_mm2s_arid => open ,
m_axi_mm2s_araddr => m_axi_sg_araddr ,
m_axi_mm2s_arlen => m_axi_sg_arlen ,
m_axi_mm2s_arsize => m_axi_sg_arsize ,
m_axi_mm2s_arburst => m_axi_sg_arburst ,
m_axi_mm2s_arprot => m_axi_sg_arprot ,
m_axi_mm2s_arcache => m_axi_sg_arcache ,
m_axi_mm2s_aruser => m_axi_sg_aruser ,
m_axi_mm2s_arvalid => m_axi_sg_arvalid ,
m_axi_mm2s_arready => m_axi_sg_arready ,
-- MM2S AXI MMap Read Data Channel I/O -------------------------------
m_axi_mm2s_rdata => m_axi_sg_rdata ,
m_axi_mm2s_rresp => m_axi_sg_rresp ,
m_axi_mm2s_rlast => m_axi_sg_rlast ,
m_axi_mm2s_rvalid => m_axi_sg_rvalid ,
m_axi_mm2s_rready => m_axi_sg_rready ,
-- MM2S AXI Master Stream Channel I/O --------------------------------
m_axis_mm2s_tdata => m_axis_mm2s_tdata ,
m_axis_mm2s_tkeep => m_axis_mm2s_tkeep ,
m_axis_mm2s_tlast => m_axis_mm2s_tlast ,
m_axis_mm2s_tvalid => m_axis_mm2s_tvalid ,
m_axis_mm2s_tready => m_axis_mm2s_tready ,
-- Testing Support I/O
mm2s_dbg_sel => (others => '0') ,
mm2s_dbg_data => open ,
-- S2MM Primary Clock/Reset input
m_axi_s2mm_aclk => m_axi_sg_aclk ,
m_axi_s2mm_aresetn => dm_resetn ,
s2mm_halt => NEVER_HALT ,
s2mm_halt_cmplt => open ,
s2mm_err => s2mm_err ,
s2mm_allow_addr_req => ALWAYS_ALLOW ,
s2mm_addr_req_posted => open ,
s2mm_wr_xfer_cmplt => open ,
s2mm_ld_nxt_len => open ,
s2mm_wr_len => open ,
-- Stream to Memory Map Command FIFO and Status FIFO I/O --------------
m_axis_s2mm_cmdsts_awclk => m_axi_sg_aclk ,
m_axis_s2mm_cmdsts_aresetn => dm_resetn ,
-- User Command Interface Ports (AXI Stream)
s_axis_s2mm_cmd_tvalid => s_axis_updt_cmd_tvalid ,
s_axis_s2mm_cmd_tready => s_axis_updt_cmd_tready ,
s_axis_s2mm_cmd_tdata => s_axis_updt_cmd_tdata ,
-- User Status Interface Ports (AXI Stream)
m_axis_s2mm_sts_tvalid => m_axis_updt_sts_tvalid ,
m_axis_s2mm_sts_tready => m_axis_updt_sts_tready ,
m_axis_s2mm_sts_tdata => m_axis_updt_sts_tdata ,
m_axis_s2mm_sts_tkeep => m_axis_updt_sts_tkeep ,
-- S2MM AXI Address Channel I/O --------------------------------------
m_axi_s2mm_awid => open ,
m_axi_s2mm_awaddr => m_axi_sg_awaddr_int ,
m_axi_s2mm_awlen => m_axi_sg_awlen_int ,
m_axi_s2mm_awsize => m_axi_sg_awsize_int ,
m_axi_s2mm_awburst => m_axi_sg_awburst_int ,
m_axi_s2mm_awprot => m_axi_sg_awprot_int ,
m_axi_s2mm_awcache => m_axi_sg_awcache_int ,
m_axi_s2mm_awuser => m_axi_sg_awuser_int ,
m_axi_s2mm_awvalid => m_axi_sg_awvalid_int ,
m_axi_s2mm_awready => m_axi_sg_awready_int ,
-- S2MM AXI MMap Write Data Channel I/O ------------------------------
m_axi_s2mm_wdata => m_axi_sg_wdata ,
m_axi_s2mm_wstrb => m_axi_sg_wstrb ,
m_axi_s2mm_wlast => m_axi_sg_wlast ,
m_axi_s2mm_wvalid => m_axi_sg_wvalid_int ,
m_axi_s2mm_wready => m_axi_sg_wready_int ,
-- S2MM AXI MMap Write response Channel I/O --------------------------
m_axi_s2mm_bresp => m_axi_sg_bresp_int ,
m_axi_s2mm_bvalid => m_axi_sg_bvalid_int ,
m_axi_s2mm_bready => m_axi_sg_bready_int ,
-- S2MM AXI Slave Stream Channel I/O ---------------------------------
s_axis_s2mm_tdata => s_axis_s2mm_tdata ,
s_axis_s2mm_tkeep => s_axis_s2mm_tkeep ,
s_axis_s2mm_tlast => s_axis_s2mm_tlast ,
s_axis_s2mm_tvalid => s_axis_s2mm_tvalid ,
s_axis_s2mm_tready => s_axis_s2mm_tready ,
-- Testing Support I/O
s2mm_dbg_sel => (others => '0') ,
s2mm_dbg_data => open
);
--ENABLE_MM2S_STATUS: if (C_NUM_MM2S_CHANNELS = 1) generate
-- begin
m_axi_sg_awaddr <= m_axi_sg_awaddr_int ;
m_axi_sg_awlen <= m_axi_sg_awlen_int ;
m_axi_sg_awsize <= m_axi_sg_awsize_int ;
m_axi_sg_awburst <= m_axi_sg_awburst_int;
m_axi_sg_awprot <= m_axi_sg_awprot_int ;
m_axi_sg_awcache <= m_axi_sg_awcache_int;
m_axi_sg_awuser <= m_axi_sg_awuser_int ;
m_axi_sg_awvalid <= m_axi_sg_awvalid_int;
m_axi_sg_awready_int <= m_axi_sg_awready;
m_axi_sg_wvalid <= m_axi_sg_wvalid_int;
m_axi_sg_wready_int <= m_axi_sg_wready;
m_axi_sg_bresp_int <= m_axi_sg_bresp;
m_axi_sg_bvalid_int <= m_axi_sg_bvalid;
m_axi_sg_bready <= m_axi_sg_bready_int;
-- end generate ENABLE_MM2S_STATUS;
--DISABLE_MM2S_STATUS: if (C_NUM_MM2S_CHANNELS > 1) generate
--
-- m_axi_sg_awaddr <= (others => '0') when ch1_updt_active = '1' else m_axi_sg_awaddr_int;
-- m_axi_sg_awlen <= (others => '0') when ch1_updt_active = '1' else m_axi_sg_awlen_int;
-- m_axi_sg_awsize <= (others => '0') when ch1_updt_active = '1' else m_axi_sg_awsize_int;
-- m_axi_sg_awburst <= (others => '0') when ch1_updt_active = '1' else m_axi_sg_awburst_int;
-- m_axi_sg_awprot <= (others => '0') when ch1_updt_active = '1' else m_axi_sg_awprot_int;
-- m_axi_sg_awcache <= (others => '0') when ch1_updt_active = '1' else m_axi_sg_awcache_int;
-- m_axi_sg_awuser <= (others => '0') when ch1_updt_active = '1' else m_axi_sg_awuser_int;
-- m_axi_sg_awvalid <= '0' when ch1_updt_active = '1' else m_axi_sg_awvalid_int;
-- m_axi_sg_awready_int <= m_axi_sg_awvalid_int when ch1_updt_active = '1' else m_axi_sg_awready; -- to make sure that AXI logic is fine.
--
-- m_axi_sg_wvalid <= '0' when ch1_updt_active = '1' else m_axi_sg_wvalid_int;
-- m_axi_sg_wready_int <= m_axi_sg_wvalid_int when ch1_updt_active = '1' else m_axi_sg_wready; -- to make sure that AXI logic is fine
--
-- m_axi_sg_bresp_int <= m_axi_sg_bresp;
-- m_axi_sg_bvalid_int <= m_axi_sg_bvalid_int_del when ch1_updt_active = '1' else m_axi_sg_bvalid;
-- m_axi_sg_bready <= m_axi_sg_bready_int;
--
ch2_update_active <= ch2_updt_active;
--
---- A dummy response is needed to keep things running on DMA side
-- PROC_DUMMY_RESP : process (m_axi_sg_aclk)
-- begin
-- if (dm_resetn = '0') then
-- m_axi_sg_bvalid_int_del <= '0';
-- elsif (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
-- m_axi_sg_bvalid_int_del <= m_axi_sg_wvalid_int;
-- end if;
-- end process PROC_DUMMY_RESP;
--
-- end generate DISABLE_MM2S_STATUS;
end implementation;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_if_statement_GNURIZNNI4 is
generic ( use_else_output : natural := 0;
bwr : natural := 0;
use_else_input : natural := 0;
signed : natural := 0;
HDLTYPE : string := "STD_LOGIC_VECTOR";
if_expression : string := "(a<b)";
number_inputs : integer := 2;
width : natural := 3);
port(
true : out std_logic;
a : in std_logic_vector(2 downto 0);
b : in std_logic_vector(2 downto 0));
end entity;
architecture rtl of alt_dspbuilder_if_statement_GNURIZNNI4 is
signal result : std_logic;
constant zero : STD_LOGIC_VECTOR(2 DOWNTO 0) := (others=>'0');
constant one : STD_LOGIC_VECTOR(2 DOWNTO 0) := (0 => '1', others => '0');
function myFunc ( Value: boolean )
return std_logic is
variable func_result : std_logic;
begin
if (Value) then
func_result := '1';
else
func_result := '0';
end if;
return func_result;
end;
function myFunc ( Value: std_logic )
return std_logic is
begin
return Value;
end;
Begin
-- DSP Builder Block - Simulink Block "IfStatement"
result <= myFunc((a<b)) ;
true <= result;
end architecture;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_if_statement_GNURIZNNI4 is
generic ( use_else_output : natural := 0;
bwr : natural := 0;
use_else_input : natural := 0;
signed : natural := 0;
HDLTYPE : string := "STD_LOGIC_VECTOR";
if_expression : string := "(a<b)";
number_inputs : integer := 2;
width : natural := 3);
port(
true : out std_logic;
a : in std_logic_vector(2 downto 0);
b : in std_logic_vector(2 downto 0));
end entity;
architecture rtl of alt_dspbuilder_if_statement_GNURIZNNI4 is
signal result : std_logic;
constant zero : STD_LOGIC_VECTOR(2 DOWNTO 0) := (others=>'0');
constant one : STD_LOGIC_VECTOR(2 DOWNTO 0) := (0 => '1', others => '0');
function myFunc ( Value: boolean )
return std_logic is
variable func_result : std_logic;
begin
if (Value) then
func_result := '1';
else
func_result := '0';
end if;
return func_result;
end;
function myFunc ( Value: std_logic )
return std_logic is
begin
return Value;
end;
Begin
-- DSP Builder Block - Simulink Block "IfStatement"
result <= myFunc((a<b)) ;
true <= result;
end architecture;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_if_statement_GNURIZNNI4 is
generic ( use_else_output : natural := 0;
bwr : natural := 0;
use_else_input : natural := 0;
signed : natural := 0;
HDLTYPE : string := "STD_LOGIC_VECTOR";
if_expression : string := "(a<b)";
number_inputs : integer := 2;
width : natural := 3);
port(
true : out std_logic;
a : in std_logic_vector(2 downto 0);
b : in std_logic_vector(2 downto 0));
end entity;
architecture rtl of alt_dspbuilder_if_statement_GNURIZNNI4 is
signal result : std_logic;
constant zero : STD_LOGIC_VECTOR(2 DOWNTO 0) := (others=>'0');
constant one : STD_LOGIC_VECTOR(2 DOWNTO 0) := (0 => '1', others => '0');
function myFunc ( Value: boolean )
return std_logic is
variable func_result : std_logic;
begin
if (Value) then
func_result := '1';
else
func_result := '0';
end if;
return func_result;
end;
function myFunc ( Value: std_logic )
return std_logic is
begin
return Value;
end;
Begin
-- DSP Builder Block - Simulink Block "IfStatement"
result <= myFunc((a<b)) ;
true <= result;
end architecture;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_if_statement_GNURIZNNI4 is
generic ( use_else_output : natural := 0;
bwr : natural := 0;
use_else_input : natural := 0;
signed : natural := 0;
HDLTYPE : string := "STD_LOGIC_VECTOR";
if_expression : string := "(a<b)";
number_inputs : integer := 2;
width : natural := 3);
port(
true : out std_logic;
a : in std_logic_vector(2 downto 0);
b : in std_logic_vector(2 downto 0));
end entity;
architecture rtl of alt_dspbuilder_if_statement_GNURIZNNI4 is
signal result : std_logic;
constant zero : STD_LOGIC_VECTOR(2 DOWNTO 0) := (others=>'0');
constant one : STD_LOGIC_VECTOR(2 DOWNTO 0) := (0 => '1', others => '0');
function myFunc ( Value: boolean )
return std_logic is
variable func_result : std_logic;
begin
if (Value) then
func_result := '1';
else
func_result := '0';
end if;
return func_result;
end;
function myFunc ( Value: std_logic )
return std_logic is
begin
return Value;
end;
Begin
-- DSP Builder Block - Simulink Block "IfStatement"
result <= myFunc((a<b)) ;
true <= result;
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
use ieee.math_real.all;
entity inverse_quant is
generic(
in_sample_width : integer := 8;
out_sample_width : integer := 16;
qp_width : integer := 8;
wo_dc_width : integer := 8
);
port(
quantized_samples : in std_logic_vector((16*in_sample_width)-1 downto 0);
quant_param : in std_logic_vector(qp_width-1 downto 0);
without_dc : in std_logic_vector(wo_dc_width-1 downto 0);
dequant_samples : out std_logic_vector((16*out_sample_width)-1 downto 0)
);
end entity inverse_quant;
architecture initial of inverse_quant is
--- TYPES -----------------------------------------------------------------
type block_type is array(15 downto 0) of integer;
--- CONSTANTS -------------------------------------------------------------
constant factor_table_entry_0 : block_type := (10,13,10,13,13,16,13,16,10,13,10,13,13,16,13,16);
constant factor_table_entry_1 : block_type := (11,14,11,14,14,18,14,18,11,14,11,14,14,18,14,18);
constant factor_table_entry_2 : block_type := (13,16,13,16,16,20,16,20,13,16,13,16,16,20,16,20);
constant factor_table_entry_3 : block_type := (14,18,14,18,18,23,18,23,14,18,14,18,18,23,18,23);
constant factor_table_entry_4 : block_type := (16,20,16,20,20,25,20,25,16,20,16,20,20,25,20,25);
constant factor_table_entry_5 : block_type := (18,23,18,23,23,29,23,29,18,23,18,23,23,29,23,29);
--- SIGNALS ---------------------------------------------------------------
signal quantization_bits : integer;
signal quantized_block : block_type;
signal dequantized_block : block_type;
signal block_item_signs : block_type;
signal the_factors : block_type;
signal factor_selector : integer;
signal quant_shift : signed(31 downto 0);
begin
-- determine correct factor table entry to use
factor_selector <= to_integer(unsigned( quant_param )) mod 6;
the_factors <= factor_table_entry_0 when factor_selector = 0 else
factor_table_entry_1 when factor_selector = 1 else
factor_table_entry_2 when factor_selector = 2 else
factor_table_entry_3 when factor_selector = 3 else
factor_table_entry_4 when factor_selector = 4 else
factor_table_entry_5;
-- parse the input into integers
-- and find the signs
signs: for i in 15 downto 0 generate
constant lower_index : integer := i * in_sample_width;
constant upper_index : integer := lower_index + in_sample_width - 1;
begin
quantized_block(i) <= to_integer(signed( quantized_samples(upper_index downto lower_index) ));
block_item_signs(i) <= -1 when quantized_block(i) < 0 else 1;
end generate;
--perform the algorithm on samples 15..1
quantization_bits <= to_integer(signed(quant_param))/6;
quant_shift <= shift_left(to_signed(1,32), quantization_bits);
alg: for i in 15 downto 1 generate
begin
dequantized_block(i) <= block_item_signs(i) *
(abs(quantized_block(i)) * the_factors(15-i) * to_integer(quant_shift)
);
end generate;
--perform the algorithm on the special case of 0
dequantized_block(0) <= quantized_block(0) when or_reduce(without_dc) = '1' else
block_item_signs(0) *
(abs(quantized_block(0)) *
the_factors(15) *
to_integer(quant_shift)
);
--format the output
output: for i in 15 downto 0 generate
constant lower_index : integer := i * out_sample_width;
constant upper_index : integer := lower_index + out_sample_width - 1;
begin
dequant_samples(upper_index downto lower_index) <= std_logic_vector(to_signed(dequantized_block(i), out_sample_width));
end generate;
end architecture initial; |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
use ieee.math_real.all;
entity inverse_quant is
generic(
in_sample_width : integer := 8;
out_sample_width : integer := 16;
qp_width : integer := 8;
wo_dc_width : integer := 8
);
port(
quantized_samples : in std_logic_vector((16*in_sample_width)-1 downto 0);
quant_param : in std_logic_vector(qp_width-1 downto 0);
without_dc : in std_logic_vector(wo_dc_width-1 downto 0);
dequant_samples : out std_logic_vector((16*out_sample_width)-1 downto 0)
);
end entity inverse_quant;
architecture initial of inverse_quant is
--- TYPES -----------------------------------------------------------------
type block_type is array(15 downto 0) of integer;
--- CONSTANTS -------------------------------------------------------------
constant factor_table_entry_0 : block_type := (10,13,10,13,13,16,13,16,10,13,10,13,13,16,13,16);
constant factor_table_entry_1 : block_type := (11,14,11,14,14,18,14,18,11,14,11,14,14,18,14,18);
constant factor_table_entry_2 : block_type := (13,16,13,16,16,20,16,20,13,16,13,16,16,20,16,20);
constant factor_table_entry_3 : block_type := (14,18,14,18,18,23,18,23,14,18,14,18,18,23,18,23);
constant factor_table_entry_4 : block_type := (16,20,16,20,20,25,20,25,16,20,16,20,20,25,20,25);
constant factor_table_entry_5 : block_type := (18,23,18,23,23,29,23,29,18,23,18,23,23,29,23,29);
--- SIGNALS ---------------------------------------------------------------
signal quantization_bits : integer;
signal quantized_block : block_type;
signal dequantized_block : block_type;
signal block_item_signs : block_type;
signal the_factors : block_type;
signal factor_selector : integer;
signal quant_shift : signed(31 downto 0);
begin
-- determine correct factor table entry to use
factor_selector <= to_integer(unsigned( quant_param )) mod 6;
the_factors <= factor_table_entry_0 when factor_selector = 0 else
factor_table_entry_1 when factor_selector = 1 else
factor_table_entry_2 when factor_selector = 2 else
factor_table_entry_3 when factor_selector = 3 else
factor_table_entry_4 when factor_selector = 4 else
factor_table_entry_5;
-- parse the input into integers
-- and find the signs
signs: for i in 15 downto 0 generate
constant lower_index : integer := i * in_sample_width;
constant upper_index : integer := lower_index + in_sample_width - 1;
begin
quantized_block(i) <= to_integer(signed( quantized_samples(upper_index downto lower_index) ));
block_item_signs(i) <= -1 when quantized_block(i) < 0 else 1;
end generate;
--perform the algorithm on samples 15..1
quantization_bits <= to_integer(signed(quant_param))/6;
quant_shift <= shift_left(to_signed(1,32), quantization_bits);
alg: for i in 15 downto 1 generate
begin
dequantized_block(i) <= block_item_signs(i) *
(abs(quantized_block(i)) * the_factors(15-i) * to_integer(quant_shift)
);
end generate;
--perform the algorithm on the special case of 0
dequantized_block(0) <= quantized_block(0) when or_reduce(without_dc) = '1' else
block_item_signs(0) *
(abs(quantized_block(0)) *
the_factors(15) *
to_integer(quant_shift)
);
--format the output
output: for i in 15 downto 0 generate
constant lower_index : integer := i * out_sample_width;
constant upper_index : integer := lower_index + out_sample_width - 1;
begin
dequant_samples(upper_index downto lower_index) <= std_logic_vector(to_signed(dequantized_block(i), out_sample_width));
end generate;
end architecture initial; |
architecture RTl of FIFO is
component fifo is
end component fifo;
-- Failures below
component fifo is
end component fifo;
component fifo is
end component fifo;
begin
end architecture RTL;
|
--========================================================================================================================
-- Copyright (c) 2017 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <[email protected]>.
--
-- UVVM AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
-- WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS
-- OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
-- OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH UVVM OR THE USE OR OTHER DEALINGS IN UVVM.
--========================================================================================================================
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library std;
use std.textio.all;
library uvvm_util;
context uvvm_util.uvvm_util_context;
--=================================================================================================
package spi_bfm_pkg is
--===============================================================================================
-- Types and constants for SPI BFMs
--===============================================================================================
constant C_SCOPE : string := "SPI BFM";
type t_spi_if is record
ss_n : std_logic; -- master to slave
sclk : std_logic; -- master to slave
mosi : std_logic; -- master to slave
miso : std_logic; -- slave to master
end record;
-- Configuration record to be assigned in the test harness.
type t_spi_bfm_config is
record
CPOL : std_logic; -- sclk polarity, i.e. the base value of the clock.
-- If CPOL is '0', the clock will be set to '0' when inactive, i.e., ordinary positive polarity.
CPHA : std_logic; -- sclk phase, i.e. when data is sampled and transmitted w.r.t. sclk.
-- If '0', sampling occurs on the first sclk edge and data is transmitted on the sclk active to idle state.
-- If '1', data is sampled on the second sclk edge and transmitted on sclk idle to active state.
spi_bit_time : time; -- Used in master for dictating sclk period
ss_n_to_sclk : time; -- Time from SS active until SCLK active
sclk_to_ss_n : time; -- Last SCLK until SS off
inter_word_delay : time; -- Minimum time between words, from ss_n inactive to ss_n active
id_for_bfm : t_msg_id; -- The message ID used as a general message ID in the SPI BFM
id_for_bfm_wait : t_msg_id; -- The message ID used for logging waits in the SPI BFM
id_for_bfm_poll : t_msg_id; -- The message ID used for logging polling in the SPI BFM
end record;
constant C_SPI_BFM_CONFIG_DEFAULT : t_spi_bfm_config := (
CPOL => '0',
CPHA => '0',
spi_bit_time => -1 ns, -- Make sure we notice if we forget to set bit time.
ss_n_to_sclk => 20 ns,
sclk_to_ss_n => 20 ns,
inter_word_delay => 0 ns,
id_for_bfm => ID_BFM,
id_for_bfm_wait => ID_BFM_WAIT,
id_for_bfm_poll => ID_BFM_POLL
);
--===============================================================================================
-- BFM procedures
--===============================================================================================
------------------------------------------
-- init_spi_if_signals
------------------------------------------
-- - This function returns an SPI interface with initialized signals.
-- - master_mode = true:
-- - ss_n initialized to 'H'
-- - if config.CPOL = '1', sclk initialized to 'H',
-- otherwise sclk initialized to 'L'
-- - miso and mosi initialized to 'Z'
-- - master_mode = false:
-- - all signals initialized to 'Z'
function init_spi_if_signals (
constant config : in t_spi_bfm_config;
constant master_mode : in boolean := true
) return t_spi_if;
------------------------------------------
-- spi_master_transmit_and_receive
------------------------------------------
-- This procedure transmits data 'tx_data' to the SPI slave DUT
-- and receives 'rx_data' from the SPI slave DUT.
procedure spi_master_transmit_and_receive (
constant tx_data : in std_logic_vector;
variable rx_data : out std_logic_vector;
constant msg : in string;
signal sclk : inout std_logic;
signal ss_n : inout std_logic;
signal mosi : inout std_logic;
signal miso : inout std_logic;
constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_spi_bfm_config := C_SPI_BFM_CONFIG_DEFAULT;
constant ext_proc_call : in string := "" -- External proc_call; overwrite if called from other BFM procedure like spi_*_check
);
------------------------------------------
-- spi_master_transmit_and_receive
------------------------------------------
-- This procedure transmits data 'tx_data' to the SPI slave DUT
-- and receives 'rx_data' from the SPI slave DUT.
-- The SPI interface in this procedure is given as a t_spi_if signal record
procedure spi_master_transmit_and_receive (
constant tx_data : in std_logic_vector;
variable rx_data : out std_logic_vector;
constant msg : in string;
signal spi_if : inout t_spi_if;
constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_spi_bfm_config := C_SPI_BFM_CONFIG_DEFAULT;
constant ext_proc_call : in string := "" -- External proc_call; overwrite if called from other BFM procedure like spi_*_check
);
-- Multi-word
procedure spi_master_transmit_and_receive (
constant tx_data : in t_slv_array;
variable rx_data : out t_slv_array;
constant msg : in string;
signal spi_if : inout t_spi_if;
constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER;
constant action_between_words : in t_action_between_words := HOLD_LINE_BETWEEN_WORDS;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_spi_bfm_config := C_SPI_BFM_CONFIG_DEFAULT;
constant ext_proc_call : in string := "" -- External proc_call; overwrite if called from other BFM procedure like spi_*_check
);
------------------------------------------
-- spi_master_transmit_and_check
------------------------------------------
-- This procedure ...
-- The SPI interface in this procedure is given as a t_spi_if signal record
procedure spi_master_transmit_and_check(
constant tx_data : in std_logic_vector;
constant data_exp : in std_logic_vector;
constant msg : in string;
signal spi_if : inout t_spi_if;
constant alert_level : in t_alert_level := error;
constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_spi_bfm_config := C_SPI_BFM_CONFIG_DEFAULT
);
-- Multi-word
procedure spi_master_transmit_and_check(
constant tx_data : in t_slv_array;
constant data_exp : in t_slv_array;
constant msg : in string;
signal spi_if : inout t_spi_if;
constant alert_level : in t_alert_level := error;
constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER;
constant action_between_words : in t_action_between_words := HOLD_LINE_BETWEEN_WORDS;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_spi_bfm_config := C_SPI_BFM_CONFIG_DEFAULT
);
------------------------------------------
-- spi_master_transmit
------------------------------------------
-- This procedure transmits data 'tx_data' to the SPI DUT
-- The SPI interface in this procedure is given as a t_spi_if signal record
procedure spi_master_transmit(
constant tx_data : in std_logic_vector;
constant msg : in string;
signal spi_if : inout t_spi_if;
constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_spi_bfm_config := C_SPI_BFM_CONFIG_DEFAULT
);
-- Multi-word
procedure spi_master_transmit(
constant tx_data : in t_slv_array;
constant msg : in string;
signal spi_if : inout t_spi_if;
constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER;
constant action_between_words : in t_action_between_words := HOLD_LINE_BETWEEN_WORDS;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_spi_bfm_config := C_SPI_BFM_CONFIG_DEFAULT
);
------------------------------------------
-- spi_master_receive
------------------------------------------
-- This procedure receives data 'rx_data' from the SPI DUT
-- The SPI interface in this procedure is given as a t_spi_if signal record
procedure spi_master_receive(
variable rx_data : out std_logic_vector;
constant msg : in string;
signal spi_if : inout t_spi_if;
constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_spi_bfm_config := C_SPI_BFM_CONFIG_DEFAULT
);
-- Multi-word
procedure spi_master_receive(
variable rx_data : out t_slv_array;
constant msg : in string;
signal spi_if : inout t_spi_if;
constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER;
constant action_between_words : in t_action_between_words := HOLD_LINE_BETWEEN_WORDS;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_spi_bfm_config := C_SPI_BFM_CONFIG_DEFAULT
);
------------------------------------------
-- spi_master_check
------------------------------------------
-- This procedure receives an SPI transaction, and compares the read data
-- to the expected data in 'data_exp'.
-- If the read data is inconsistent with the expected data, an alert with
-- severity 'alert_level' is triggered.
-- The SPI interface in this procedure is given as a t_spi_if signal record
procedure spi_master_check(
constant data_exp : in std_logic_vector;
constant msg : in string;
signal spi_if : inout t_spi_if;
constant alert_level : in t_alert_level := error;
constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_spi_bfm_config := C_SPI_BFM_CONFIG_DEFAULT
);
-- Multi-word
procedure spi_master_check(
constant data_exp : in t_slv_array;
constant msg : in string;
signal spi_if : inout t_spi_if;
constant alert_level : in t_alert_level := error;
constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER;
constant action_between_words : in t_action_between_words := HOLD_LINE_BETWEEN_WORDS;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_spi_bfm_config := C_SPI_BFM_CONFIG_DEFAULT
);
------------------------------------------
-- spi_slave_transmit_and_receive
------------------------------------------
-- This procedure transmits data 'tx_data' to the SPI master DUT
-- and receives 'rx_data' from the SPI master DUT.
procedure spi_slave_transmit_and_receive (
constant tx_data : in std_logic_vector;
variable rx_data : out std_logic_vector;
constant msg : in string;
signal sclk : inout std_logic;
signal ss_n : inout std_logic;
signal mosi : inout std_logic;
signal miso : inout std_logic;
constant when_to_start_transfer : in t_when_to_start_transfer := START_TRANSFER_ON_NEXT_SS;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_spi_bfm_config := C_SPI_BFM_CONFIG_DEFAULT;
constant ext_proc_call : in string := "" -- External proc_call; overwrite if called from other BFM procedure like spi_*_check
);
------------------------------------------
-- spi_slave_transmit_and_receive
------------------------------------------
-- This procedure transmits data 'tx_data' to the SPI master DUT
-- and receives 'rx_data' from the SPI master DUT.
-- The SPI interface in this procedure is given as a t_spi_if signal record
procedure spi_slave_transmit_and_receive (
constant tx_data : in std_logic_vector;
variable rx_data : out std_logic_vector;
constant msg : in string;
signal spi_if : inout t_spi_if;
constant when_to_start_transfer : in t_when_to_start_transfer := START_TRANSFER_ON_NEXT_SS;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_spi_bfm_config := C_SPI_BFM_CONFIG_DEFAULT;
constant ext_proc_call : in string := "" -- External proc_call; overwrite if called from other BFM procedure like spi_*_check
);
-- Multi-word
procedure spi_slave_transmit_and_receive (
constant tx_data : in t_slv_array;
variable rx_data : out t_slv_array;
constant msg : in string;
signal spi_if : inout t_spi_if;
constant when_to_start_transfer : in t_when_to_start_transfer := START_TRANSFER_ON_NEXT_SS;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_spi_bfm_config := C_SPI_BFM_CONFIG_DEFAULT;
constant ext_proc_call : in string := "" -- External proc_call; overwrite if called from other BFM procedure like spi_*_check
);
------------------------------------------
-- spi_slave_transmit_and_check
------------------------------------------
-- This procedure ...
-- The SPI interface in this procedure is given as a t_spi_if signal record
procedure spi_slave_transmit_and_check(
constant tx_data : in std_logic_vector;
constant data_exp : in std_logic_vector;
constant msg : in string;
signal spi_if : inout t_spi_if;
constant alert_level : in t_alert_level := error;
constant when_to_start_transfer : in t_when_to_start_transfer := START_TRANSFER_ON_NEXT_SS;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_spi_bfm_config := C_SPI_BFM_CONFIG_DEFAULT
);
-- Multi-word
procedure spi_slave_transmit_and_check(
constant tx_data : in t_slv_array;
constant data_exp : in t_slv_array;
constant msg : in string;
signal spi_if : inout t_spi_if;
constant alert_level : in t_alert_level := error;
constant when_to_start_transfer : in t_when_to_start_transfer := START_TRANSFER_ON_NEXT_SS;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_spi_bfm_config := C_SPI_BFM_CONFIG_DEFAULT
);
------------------------------------------
-- spi_slave_transmit
------------------------------------------
-- This procedure transmits data 'tx_data' to the SPI DUT
-- The SPI interface in this procedure is given as a t_spi_if signal record
procedure spi_slave_transmit (
constant tx_data : in std_logic_vector;
constant msg : in string;
signal spi_if : inout t_spi_if;
constant when_to_start_transfer : in t_when_to_start_transfer := START_TRANSFER_ON_NEXT_SS;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_spi_bfm_config := C_SPI_BFM_CONFIG_DEFAULT
);
-- Multi-word
procedure spi_slave_transmit (
constant tx_data : in t_slv_array;
constant msg : in string;
signal spi_if : inout t_spi_if;
constant when_to_start_transfer : in t_when_to_start_transfer := START_TRANSFER_ON_NEXT_SS;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_spi_bfm_config := C_SPI_BFM_CONFIG_DEFAULT
);
------------------------------------------
-- spi_slave_receive
------------------------------------------
-- This procedure receives data 'rx_data' from the SPI DUT
-- The SPI interface in this procedure is given as a t_spi_if signal record
procedure spi_slave_receive (
variable rx_data : out std_logic_vector;
constant msg : in string;
signal spi_if : inout t_spi_if;
constant when_to_start_transfer : in t_when_to_start_transfer := START_TRANSFER_ON_NEXT_SS;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_spi_bfm_config := C_SPI_BFM_CONFIG_DEFAULT
);
-- Multi-word
procedure spi_slave_receive (
variable rx_data : out t_slv_array;
constant msg : in string;
signal spi_if : inout t_spi_if;
constant when_to_start_transfer : in t_when_to_start_transfer := START_TRANSFER_ON_NEXT_SS;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_spi_bfm_config := C_SPI_BFM_CONFIG_DEFAULT
);
------------------------------------------
-- spi_slave_check
------------------------------------------
-- This procedure receives an SPI transaction, and compares the read data
-- to the expected data in 'data_exp'.
-- If the read data is inconsistent with the expected data, an alert with
-- severity 'alert_level' is triggered.
-- The SPI interface in this procedure is given as a t_spi_if signal record
procedure spi_slave_check (
constant data_exp : in std_logic_vector;
constant msg : in string;
signal spi_if : inout t_spi_if;
constant alert_level : in t_alert_level := error;
constant when_to_start_transfer : in t_when_to_start_transfer := START_TRANSFER_ON_NEXT_SS;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_spi_bfm_config := C_SPI_BFM_CONFIG_DEFAULT
);
-- Multi-word
procedure spi_slave_check (
constant data_exp : in t_slv_array;
constant msg : in string;
signal spi_if : inout t_spi_if;
constant alert_level : in t_alert_level := error;
constant when_to_start_transfer : in t_when_to_start_transfer := START_TRANSFER_ON_NEXT_SS;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_spi_bfm_config := C_SPI_BFM_CONFIG_DEFAULT
);
end package spi_bfm_pkg;
--=================================================================================================
--=================================================================================================
package body spi_bfm_pkg is
---------------------------------------------------------------------------------
-- initialize spi to dut signals
---------------------------------------------------------------------------------
function init_spi_if_signals (
constant config : in t_spi_bfm_config;
constant master_mode : in boolean := true
) return t_spi_if is
variable result : t_spi_if;
begin
if master_mode then
result.ss_n := 'H';
if (config.CPOL) then
result.sclk := 'H';
else
result.sclk := 'L';
end if;
else
result.ss_n := 'Z';
result.sclk := 'Z';
end if;
result.mosi := 'Z';
result.miso := 'Z';
return result;
end function;
---------------------------------------------------------------------------------
-- spi_master_transmit_and_receive
--
-- alert if size of tx_data or rx_data doesn't
-- match with how long ss_n is kept low
---------------------------------------------------------------------------------
procedure spi_master_transmit_and_receive (
constant tx_data : in std_logic_vector;
variable rx_data : out std_logic_vector;
constant msg : in string;
signal sclk : inout std_logic;
signal ss_n : inout std_logic;
signal mosi : inout std_logic;
signal miso : inout std_logic;
constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_spi_bfm_config := C_SPI_BFM_CONFIG_DEFAULT;
constant ext_proc_call : in string := "" -- External proc_call; overwrite if called from other BFM procedure like spi_*_check
) is
constant local_proc_name : string := "spi_master_transmit_and_receive";
constant local_proc_call : string := local_proc_name;
constant C_ACCESS_SIZE : integer := tx_data'length;
-- Helper variables
variable v_access_done : boolean := false;
variable v_tx_count : integer := 0;
variable v_tx_data : std_logic_vector(tx_data'length-1 downto 0) := tx_data;
variable v_rx_data : std_logic_vector(rx_data'length-1 downto 0) := (others => 'X');
variable v_rx_count : integer := 1;
variable v_proc_call : line;
variable v_multi_word_transfer_in_progress : boolean := false;
begin
-- check whether config.spi_bit_time was set
check_value(config.spi_bit_time /= -1 ns, TB_ERROR, "SPI Bit time was not set in config. " & add_msg_delimiter(msg), C_SCOPE, ID_NEVER, msg_id_panel);
if ext_proc_call = "" then
-- Called directly from sequencer/VVC. Include 'spi_master_transmit_and_receive' when logging
write(v_proc_call, local_proc_call);
else
-- Called from other BFM procedure like spi_*_check. Include 'spi_*_check(..) while executing spi_master_transmit_and_receive' when logging
write(v_proc_call, ext_proc_call & " while executing " & local_proc_name);
end if;
-- Detect if we have an ongoing multi-word transfer
if ss_n = '0' then
v_multi_word_transfer_in_progress := true;
end if;
sclk <= config.CPOL;
ss_n <= '0';
wait for 0 ns; -- wait a delta cycle
if ss_n = '0' then
-- set MOSI together with SS_N when CPHA=0
if not config.CPHA then
mosi <= v_tx_data(C_ACCESS_SIZE- v_tx_count - 1);
v_tx_count := v_tx_count + 1;
end if;
-- Decide delay before initial SCLK edge
if not v_multi_word_transfer_in_progress then
wait for config.ss_n_to_sclk;
else
wait for config.spi_bit_time/2;
end if;
sclk <= not config.CPOL;
-- serially shift out v_tx_data to mosi
-- serially shift in v_rx_data from miso
while ss_n = '0' and not v_access_done loop
if not config.CPHA then
v_rx_data(C_ACCESS_SIZE-v_rx_count) := miso;
wait for config.spi_bit_time/2;
sclk <= config.CPOL;
mosi <= v_tx_data(C_ACCESS_SIZE-v_tx_count-1);
else -- config.CPHA
mosi <= v_tx_data(C_ACCESS_SIZE-v_tx_count-1);
wait for config.spi_bit_time/2;
sclk <= config.CPOL;
v_rx_data(C_ACCESS_SIZE-v_rx_count) := miso;
end if;
if v_tx_count < C_ACCESS_SIZE-1 then -- Not done
v_rx_count := v_rx_count + 1;
v_tx_count := v_tx_count + 1;
wait for config.spi_bit_time/2;
sclk <= not config.CPOL;
else -- Final bit
if not config.CPHA then
v_rx_count := v_rx_count + 1;
-- Sample Last bit on the second to last edge of SCLK (CPOL=0: last rising. CPOL=1: last falling)
wait for config.spi_bit_time/2;
v_rx_data(C_ACCESS_SIZE-v_rx_count) := miso;
sclk <= not config.CPOL;
end if;
log(config.id_for_bfm, v_proc_call.all & "=> " & to_string(v_tx_data, HEX, SKIP_LEADING_0, INCL_RADIX) & " completed. " & add_msg_delimiter(msg), scope, msg_id_panel);
v_access_done := true;
end if;
end loop;
-- Clock the last bit
if not config.CPHA then
wait for config.spi_bit_time/2;
sclk <= config.CPOL;
end if;
-- Determine if single- or multi-word transfer
if action_when_transfer_is_done = RELEASE_LINE_AFTER_TRANSFER then
wait for config.sclk_to_ss_n;
mosi <= 'Z';
ss_n <= '1';
wait for config.inter_word_delay;
else -- action_when_transfer_is_done = HOLD_LINE_AFTER_TRANSFER
ss_n <= '0';
end if;
wait for 0 ns; -- delta cycle
if (v_tx_count /= C_ACCESS_SIZE-1) or (v_rx_count /= C_ACCESS_SIZE) then
alert(note, " v_tx_count /= C_ACCESS_SIZE-1 or v_rx_count /= C_ACCESS_SIZE then");
alert(note, to_string(v_tx_count) & " /= " & to_string(C_ACCESS_SIZE-1) & " or" &to_string(v_rx_count) & " /= " & to_string(C_ACCESS_SIZE));
alert(note, local_proc_name & " ss_n not kept low for v_tx_data size duration");
else
rx_data := v_rx_data;
end if;
else
alert(error, local_proc_name & " ss_n not low when expected.");
end if;
if ext_proc_call = "" then -- proc_name = "spi_master_transmit_and_receive"
log(config.id_for_bfm, v_proc_call.all & "=> Transmitted: " & to_string(v_tx_data, HEX, SKIP_LEADING_0, INCL_RADIX) & ". Received: " & to_string(v_rx_data, HEX, SKIP_LEADING_0, INCL_RADIX) & ". " & add_msg_delimiter(msg), scope, msg_id_panel);
end if;
end procedure;
-- Single-word
procedure spi_master_transmit_and_receive (
constant tx_data : in std_logic_vector;
variable rx_data : out std_logic_vector;
constant msg : in string;
signal spi_if : inout t_spi_if;
constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_spi_bfm_config := C_SPI_BFM_CONFIG_DEFAULT;
constant ext_proc_call : in string := "" -- External proc_call; overwrite if called from other BFM procedure like spi_*_check
) is
begin
spi_master_transmit_and_receive(tx_data, rx_data, msg,
spi_if.sclk, spi_if.ss_n, spi_if.mosi, spi_if.miso,
action_when_transfer_is_done, scope, msg_id_panel, config, ext_proc_call);
end procedure;
-- Multi-word
procedure spi_master_transmit_and_receive (
constant tx_data : in t_slv_array;
variable rx_data : out t_slv_array;
constant msg : in string;
signal spi_if : inout t_spi_if;
constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER;
constant action_between_words : in t_action_between_words := HOLD_LINE_BETWEEN_WORDS;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_spi_bfm_config := C_SPI_BFM_CONFIG_DEFAULT;
constant ext_proc_call : in string := "" -- External proc_call; overwrite if called from other BFM procedure like spi_*_check
) is
variable v_action_when_transfer_is_done : t_action_when_transfer_is_done; -- between words and after transfer
begin
-- Check length of tx_data and rx_data
if tx_data'length /= rx_data'length then
alert(error, ext_proc_call & " tx_data and rx_data have different sizes.");
end if;
for idx in 0 to (tx_data'length-1) loop
case action_between_words is
when RELEASE_LINE_BETWEEN_WORDS =>
if idx < tx_data'length-1 then
v_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER;
else
v_action_when_transfer_is_done := action_when_transfer_is_done;
end if;
when others => -- HOLD_LINE_BETWEEN_WORDS
if idx < tx_data'length-1 then
v_action_when_transfer_is_done := HOLD_LINE_AFTER_TRANSFER;
else
v_action_when_transfer_is_done := action_when_transfer_is_done;
end if;
end case;
-- call single-word procedure
spi_master_transmit_and_receive(tx_data(idx), rx_data(idx), msg, spi_if, v_action_when_transfer_is_done, scope, msg_id_panel, config, ext_proc_call);
end loop;
end procedure;
---------------------------------------------------------------------------------
-- spi_master_transmit_and_check
---------------------------------------------------------------------------------
procedure spi_master_transmit_and_check(
constant tx_data : in std_logic_vector;
constant data_exp : in std_logic_vector;
constant msg : in string;
signal spi_if : inout t_spi_if;
constant alert_level : in t_alert_level := error;
constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_spi_bfm_config := C_SPI_BFM_CONFIG_DEFAULT
) is
constant local_proc_name : string := "spi_master_transmit_and_check";
constant local_proc_call : string := local_proc_name;
-- Helper variables
variable v_rx_data : std_logic_vector(data_exp'length-1 downto 0);
variable v_check_ok : boolean;
begin
spi_master_transmit_and_receive(tx_data, v_rx_data, msg, spi_if, action_when_transfer_is_done, scope, msg_id_panel, config, local_proc_call);
-- Compare values, but ignore any leading zero's if widths are different.
-- Use ID_NEVER so that check_value method does not log when check is OK,
-- log it here instead.
v_check_ok := check_value(v_rx_data, data_exp, alert_level, msg, scope, HEX_BIN_IF_INVALID, SKIP_LEADING_0, ID_NEVER, msg_id_panel, local_proc_call);
if v_check_ok then
log(config.id_for_bfm, local_proc_call & "=> OK, read data = " & to_string(v_rx_data, HEX, SKIP_LEADING_0, INCL_RADIX) & ". " & add_msg_delimiter(msg), scope, msg_id_panel);
end if;
end procedure;
-- Multi-word
procedure spi_master_transmit_and_check(
constant tx_data : in t_slv_array;
constant data_exp : in t_slv_array;
constant msg : in string;
signal spi_if : inout t_spi_if;
constant alert_level : in t_alert_level := error;
constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER;
constant action_between_words : in t_action_between_words := HOLD_LINE_BETWEEN_WORDS;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_spi_bfm_config := C_SPI_BFM_CONFIG_DEFAULT
) is
constant local_proc_name : string := "spi_master_transmit_and_check";
constant local_proc_call : string := local_proc_name;
variable v_action_when_transfer_is_done : t_action_when_transfer_is_done; -- between words and after transfer
begin
-- Check length of tx_data and data_exp
if tx_data'length /= data_exp'length then
alert(error, local_proc_call & " tx_data and data_exp have different sizes.");
end if;
for idx in 0 to (tx_data'length-1) loop
case action_between_words is
when RELEASE_LINE_BETWEEN_WORDS =>
if idx < tx_data'length-1 then
v_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER;
else
v_action_when_transfer_is_done := action_when_transfer_is_done;
end if;
when others => -- HOLD_LINE_BETWEEN_WORDS
if idx < tx_data'length-1 then
v_action_when_transfer_is_done := HOLD_LINE_AFTER_TRANSFER;
else
v_action_when_transfer_is_done := action_when_transfer_is_done;
end if;
end case;
-- call single-word procedure
spi_master_transmit_and_check(tx_data(idx), data_exp(idx), msg, spi_if, alert_level, v_action_when_transfer_is_done, scope, msg_id_panel, config);
end loop;
end procedure;
---------------------------------------------------------------------------------
-- spi_master_transmit
---------------------------------------------------------------------------------
procedure spi_master_transmit(
constant tx_data : in std_logic_vector;
constant msg : in string;
signal spi_if : inout t_spi_if;
constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_spi_bfm_config := C_SPI_BFM_CONFIG_DEFAULT
) is
constant local_proc_name : string := "spi_master_transmit";
constant local_proc_call : string := local_proc_name;
-- Helper variables
variable v_rx_data : std_logic_vector(tx_data'length - 1 downto 0);
begin
spi_master_transmit_and_receive(tx_data, v_rx_data, msg, spi_if, action_when_transfer_is_done, scope, msg_id_panel, config, local_proc_call);
end procedure;
-- Multi-word
procedure spi_master_transmit(
constant tx_data : in t_slv_array;
constant msg : in string;
signal spi_if : inout t_spi_if;
constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER;
constant action_between_words : in t_action_between_words := HOLD_LINE_BETWEEN_WORDS;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_spi_bfm_config := C_SPI_BFM_CONFIG_DEFAULT
) is
variable v_action_when_transfer_is_done : t_action_when_transfer_is_done; -- between words and after transfer
begin
for idx in 0 to (tx_data'length-1) loop
case action_between_words is
when RELEASE_LINE_BETWEEN_WORDS =>
if idx < tx_data'length-1 then
v_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER;
else
v_action_when_transfer_is_done := action_when_transfer_is_done;
end if;
when others => -- HOLD_LINE_BETWEEN_WORDS
if idx < tx_data'length-1 then
v_action_when_transfer_is_done := HOLD_LINE_AFTER_TRANSFER;
else
v_action_when_transfer_is_done := action_when_transfer_is_done;
end if;
end case;
-- call single-word procedure
spi_master_transmit(tx_data(idx), msg, spi_if, v_action_when_transfer_is_done, scope, msg_id_panel, config);
end loop;
end procedure;
---------------------------------------------------------------------------------
-- spi_master_receive
---------------------------------------------------------------------------------
procedure spi_master_receive(
variable rx_data : out std_logic_vector;
constant msg : in string;
signal spi_if : inout t_spi_if;
constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_spi_bfm_config := C_SPI_BFM_CONFIG_DEFAULT
) is
constant local_proc_name : string := "spi_master_receive";
constant local_proc_call : string := local_proc_name;
-- Helper variables
variable v_tx_data : std_logic_vector(rx_data'length - 1 downto 0) := (others => '0');
begin
spi_master_transmit_and_receive(v_tx_data, rx_data, msg, spi_if, action_when_transfer_is_done, scope, msg_id_panel, config, local_proc_call);
end procedure;
-- Multi-word
procedure spi_master_receive(
variable rx_data : out t_slv_array;
constant msg : in string;
signal spi_if : inout t_spi_if;
constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER;
constant action_between_words : in t_action_between_words := HOLD_LINE_BETWEEN_WORDS;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_spi_bfm_config := C_SPI_BFM_CONFIG_DEFAULT
) is
variable v_action_when_transfer_is_done : t_action_when_transfer_is_done; -- between words and after transfer
begin
for idx in 0 to (rx_data'length-1) loop
case action_between_words is
when RELEASE_LINE_BETWEEN_WORDS =>
if idx < rx_data'length-1 then
v_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER;
else
v_action_when_transfer_is_done := action_when_transfer_is_done;
end if;
when others => -- HOLD_LINE_BETWEEN_WORDS
if idx < rx_data'length-1 then
v_action_when_transfer_is_done := HOLD_LINE_AFTER_TRANSFER;
else
v_action_when_transfer_is_done := action_when_transfer_is_done;
end if;
end case;
-- call single-word procedure
spi_master_receive(rx_data(idx), msg, spi_if, v_action_when_transfer_is_done, scope, msg_id_panel, config);
end loop;
end procedure;
---------------------------------------------------------------------------------
-- spi_master_check
---------------------------------------------------------------------------------
procedure spi_master_check(
constant data_exp : in std_logic_vector;
constant msg : in string;
signal spi_if : inout t_spi_if;
constant alert_level : in t_alert_level := error;
constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_spi_bfm_config := C_SPI_BFM_CONFIG_DEFAULT
) is
constant local_proc_name : string := "spi_master_check";
constant local_proc_call : string := local_proc_name;
-- Helper variables
variable v_tx_data : std_logic_vector(data_exp'length - 1 downto 0) := (others => '0');
variable v_rx_data : std_logic_vector(data_exp'length-1 downto 0);
variable v_check_ok : boolean;
begin
spi_master_transmit_and_receive(v_tx_data, v_rx_data, msg, spi_if, action_when_transfer_is_done, scope, msg_id_panel, config, local_proc_call);
-- Compare values, but ignore any leading zero's if widths are different.
-- Use ID_NEVER so that check_value method does not log when check is OK,
-- log it here instead.
v_check_ok := check_value(v_rx_data, data_exp, alert_level, msg, scope, HEX_BIN_IF_INVALID, SKIP_LEADING_0, ID_NEVER, msg_id_panel, local_proc_call);
if v_check_ok then
log(config.id_for_bfm, local_proc_call & "=> OK, read data = " & to_string(v_rx_data, HEX, SKIP_LEADING_0, INCL_RADIX) & ". " & add_msg_delimiter(msg), scope, msg_id_panel);
end if;
end procedure;
-- Multi-word
procedure spi_master_check(
constant data_exp : in t_slv_array;
constant msg : in string;
signal spi_if : inout t_spi_if;
constant alert_level : in t_alert_level := error;
constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER;
constant action_between_words : in t_action_between_words := HOLD_LINE_BETWEEN_WORDS;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_spi_bfm_config := C_SPI_BFM_CONFIG_DEFAULT
) is
variable v_action_when_transfer_is_done : t_action_when_transfer_is_done; -- between words and after transfer
begin
for idx in 0 to (data_exp'length-1) loop
case action_between_words is
when RELEASE_LINE_BETWEEN_WORDS =>
if idx < data_exp'length-1 then
v_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER;
else
v_action_when_transfer_is_done := action_when_transfer_is_done;
end if;
when others => -- HOLD_LINE_BETWEEN_WORDS
if idx < data_exp'length-1 then
v_action_when_transfer_is_done := HOLD_LINE_AFTER_TRANSFER;
else
v_action_when_transfer_is_done := action_when_transfer_is_done;
end if;
end case;
-- call single-word procedure
spi_master_check(data_exp(idx), msg, spi_if, alert_level, v_action_when_transfer_is_done, scope, msg_id_panel, config);
end loop;
end procedure;
---------------------------------------------------------------------------------
-- spi_slave_transmit_and_receive
--
---------------------------------------------------------------------------------
procedure spi_slave_transmit_and_receive (
constant tx_data : in std_logic_vector;
variable rx_data : out std_logic_vector;
constant msg : in string;
signal sclk : inout std_logic;
signal ss_n : inout std_logic;
signal mosi : inout std_logic;
signal miso : inout std_logic;
constant when_to_start_transfer : in t_when_to_start_transfer := START_TRANSFER_ON_NEXT_SS;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_spi_bfm_config := C_SPI_BFM_CONFIG_DEFAULT;
constant ext_proc_call : in string := "" -- External proc_call; overwrite if called from other BFM procedure like spi_*_check
) is
-- Local_proc_name/call used if called from sequencer or VVC
constant local_proc_name : string := "spi_slave_transmit_and_receive";
constant local_proc_call : string := local_proc_name;
constant C_ACCESS_SIZE : integer := rx_data'length;
-- Helper variables
variable v_rx_data : std_logic_vector(rx_data'range) := (others => 'X');
variable bfm_tx_data : std_logic_vector(tx_data'length-1 downto 0) := tx_data;
variable v_access_done : boolean := false;
variable v_tx_count : integer := 0;
variable v_rx_count : integer := 1;
variable v_proc_call : line;
begin
-- check whether config.spi_bit_time was set
check_value(config.spi_bit_time /= -1 ns, TB_ERROR, "SPI Bit time was not set in config. " & add_msg_delimiter(msg), C_SCOPE, ID_NEVER, msg_id_panel);
if ext_proc_call = "" then
-- Called directly from sequencer/VVC. Include 'spi_slave_receive...' when logging
write(v_proc_call, local_proc_call);
else
-- Called from other BFM procedure like spi_*_check. Include 'spi_*_check(..) while executing spi_*_receive.. when logging'
write(v_proc_call, ext_proc_call & " while executing " & local_proc_name);
end if;
-- Await for master to drive SS_N and SCLK
if (ss_n /= '0') then -- master not acvtive
wait until (ss_n = '0');
elsif (ss_n = '0') then -- master active
case when_to_start_transfer is
when START_TRANSFER_ON_NEXT_SS =>
if (ss_n = '0') and (ss_n'last_active > 0 ns) then
wait until (ss_n = '0') and (ss_n'last_active <= 0 ns);
end if;
when others => -- START_TRANSFER_IMMEDIATE
null;
end case;
end if;
if ss_n = '0' then
-- set MISO together with SS_N when CPHA=0
if not config.CPHA then
miso <= bfm_tx_data(C_ACCESS_SIZE - v_tx_count - 1);
v_tx_count := v_tx_count + 1;
end if;
-- Await first clock edge
if sclk = config.CPOL then
wait until sclk = not(config.CPOL);
end if;
-- Receive bits
while (ss_n = '0') and not(v_access_done) loop
if not config.CPHA then
v_rx_data(C_ACCESS_SIZE - v_rx_count) := mosi;
wait until sclk'event and sclk = config.CPOL;
miso <= bfm_tx_data(C_ACCESS_SIZE - v_tx_count - 1);
else -- config.CPHA
miso <= bfm_tx_data(C_ACCESS_SIZE - v_tx_count - 1);
wait until sclk'event and sclk = config.CPOL;
v_rx_data(C_ACCESS_SIZE - v_rx_count) := mosi;
end if;
if (v_tx_count < (C_ACCESS_SIZE-1)) and (v_rx_count < C_ACCESS_SIZE) then
wait until sclk'event and sclk = not(config.CPOL);
v_tx_count := v_tx_count + 1;
v_rx_count := v_rx_count + 1;
else
if not config.CPHA then
wait until sclk'event and sclk = not(config.CPOL);
end if;
v_access_done := true;
end if;
end loop;
end if;
-- Sample last bit
if not config.CPHA then
v_rx_count := v_rx_count + 1;
v_rx_data(C_ACCESS_SIZE - v_rx_count) := mosi;
wait until sclk'event and sclk = config.CPOL;
end if;
if (v_tx_count < C_ACCESS_SIZE-1) then
alert(error, v_proc_call.all & " ss_n not kept active for tx_data size duration " & add_msg_delimiter(msg), scope);
elsif (v_rx_count < C_ACCESS_SIZE) then
alert(error, v_proc_call.all & " ss_n not kept active for rx_data size duration " & add_msg_delimiter(msg), scope);
else
rx_data := v_rx_data;
end if;
-- Await for master to finish
wait until (mosi = 'Z')
for config.ss_n_to_sclk;
miso <= 'Z';
if ext_proc_call = "" then
log(config.id_for_bfm, local_proc_call & "=> " & to_string(v_rx_data, HEX, SKIP_LEADING_0, INCL_RADIX) & " rx completed. " & add_msg_delimiter(msg), scope, msg_id_panel);
log(config.id_for_bfm, local_proc_call & "=> " & to_string(bfm_tx_data, HEX, SKIP_LEADING_0, INCL_RADIX) & " tx completed. " & add_msg_delimiter(msg), scope, msg_id_panel);
else
-- Log will be handled by calling procedure (e.g. spi_*_check)
end if;
end procedure;
procedure spi_slave_transmit_and_receive (
constant tx_data : in std_logic_vector;
variable rx_data : out std_logic_vector;
constant msg : in string;
signal spi_if : inout t_spi_if;
constant when_to_start_transfer : in t_when_to_start_transfer := START_TRANSFER_ON_NEXT_SS;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_spi_bfm_config := C_SPI_BFM_CONFIG_DEFAULT;
constant ext_proc_call : in string := "" -- External proc_call; overwrite if called from other BFM procedure like spi_*_check
) is
begin
spi_slave_transmit_and_receive(tx_data, rx_data, msg,
spi_if.sclk, spi_if.ss_n, spi_if.mosi, spi_if.miso,
when_to_start_transfer, scope, msg_id_panel, config, ext_proc_call);
end procedure;
-- Multi-word
procedure spi_slave_transmit_and_receive (
constant tx_data : in t_slv_array;
variable rx_data : out t_slv_array;
constant msg : in string;
signal spi_if : inout t_spi_if;
constant when_to_start_transfer : in t_when_to_start_transfer := START_TRANSFER_ON_NEXT_SS;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_spi_bfm_config := C_SPI_BFM_CONFIG_DEFAULT;
constant ext_proc_call : in string := "" -- External proc_call; overwrite if called from other BFM procedure like spi_*_check
) is
begin
-- Check length of tx_data and rx_data
if tx_data'length /= rx_data'length then
alert(error, ext_proc_call & "tx_data and rx_data have different sizes.");
end if;
for idx in 0 to (tx_data'length-1) loop
spi_slave_transmit_and_receive(tx_data(idx), rx_data(idx), msg, spi_if, when_to_start_transfer, scope, msg_id_panel, config, ext_proc_call);
end loop;
end procedure;
------------------------------------------
-- spi_slave_transmit_and_check
------------------------------------------
procedure spi_slave_transmit_and_check(
constant tx_data : in std_logic_vector;
constant data_exp : in std_logic_vector;
constant msg : in string;
signal spi_if : inout t_spi_if;
constant alert_level : in t_alert_level := error;
constant when_to_start_transfer : in t_when_to_start_transfer := START_TRANSFER_ON_NEXT_SS;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_spi_bfm_config := C_SPI_BFM_CONFIG_DEFAULT
) is
constant local_proc_name : string := "spi_slave_transmit_and_check";
constant local_proc_call : string := local_proc_name & "(" & to_string(data_exp, HEX, AS_IS, INCL_RADIX) & ")";
-- Helper variables
variable v_rx_data : std_logic_vector(data_exp'length-1 downto 0);
variable v_check_ok : boolean;
begin
spi_slave_transmit_and_receive(tx_data, v_rx_data, msg, spi_if, when_to_start_transfer, scope, msg_id_panel, config, local_proc_call);
-- Compare values, but ignore any leading zero's if widths are different.
-- Use ID_NEVER so that check_value method does not log when check is OK,
-- log it here instead.
v_check_ok := check_value(v_rx_data, data_exp, alert_level, msg, scope, HEX_BIN_IF_INVALID, SKIP_LEADING_0, ID_NEVER, msg_id_panel, local_proc_call);
if v_check_ok then
log(config.id_for_bfm, local_proc_call & "=> OK, read data = " & to_string(v_rx_data, HEX, SKIP_LEADING_0, INCL_RADIX) & ". " & add_msg_delimiter(msg), scope, msg_id_panel);
end if;
end;
-- Multi-word
procedure spi_slave_transmit_and_check(
constant tx_data : in t_slv_array;
constant data_exp : in t_slv_array;
constant msg : in string;
signal spi_if : inout t_spi_if;
constant alert_level : in t_alert_level := error;
constant when_to_start_transfer : in t_when_to_start_transfer := START_TRANSFER_ON_NEXT_SS;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_spi_bfm_config := C_SPI_BFM_CONFIG_DEFAULT
) is
constant loc_proc_call : string := "spi_slave_transmit_and_check"; -- External proc_call; overwrite if called from other BFM procedure like spi_*_check
begin
-- Check length of tx_data and rx_data
if tx_data'length /= data_exp'length then
alert(error, loc_proc_call & " tx_data and data_exp have different sizes.");
end if;
for idx in 0 to (tx_data'length-1) loop
-- call single-word procedure - will handle error checking
spi_slave_transmit_and_check(tx_data(idx), data_exp(idx), msg, spi_if, alert_level, when_to_start_transfer, scope, msg_id_panel, config);
end loop;
end;
---------------------------------------------------------------------------------
-- spi_slave_transmit
---------------------------------------------------------------------------------
procedure spi_slave_transmit(
constant tx_data : in std_logic_vector;
constant msg : in string;
signal spi_if : inout t_spi_if;
constant when_to_start_transfer : in t_when_to_start_transfer := START_TRANSFER_ON_NEXT_SS;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_spi_bfm_config := C_SPI_BFM_CONFIG_DEFAULT
) is
constant local_proc_name : string := "spi_slave_transmit";
constant local_proc_call : string := local_proc_name & "(" & to_string(tx_data, HEX, AS_IS, INCL_RADIX) & ")";
-- Helper variables
variable v_rx_data : std_logic_vector(tx_data'length-1 downto 0); -- := (others => '0');
begin
spi_slave_transmit_and_receive(tx_data, v_rx_data, msg, spi_if, when_to_start_transfer, scope, msg_id_panel, config, local_proc_call);
end procedure;
-- Multi-word
procedure spi_slave_transmit(
constant tx_data : in t_slv_array;
constant msg : in string;
signal spi_if : inout t_spi_if;
constant when_to_start_transfer : in t_when_to_start_transfer := START_TRANSFER_ON_NEXT_SS;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_spi_bfm_config := C_SPI_BFM_CONFIG_DEFAULT
) is
constant local_proc_name : string := "spi_slave_transmit";
constant local_proc_call : string := local_proc_name & "(" & to_string(tx_data, HEX, AS_IS, INCL_RADIX) & ")";
-- Helper variables
variable v_tx_data : t_slv_array(tx_data'length-1 downto 0)(tx_data(0)'length-1 downto 0) := (others => (others => '0'));
begin
-- call multi-word procedure
spi_slave_transmit_and_receive(tx_data, v_tx_data, msg, spi_if, when_to_start_transfer, scope, msg_id_panel, config, local_proc_call);
end procedure;
---------------------------------------------------------------------------------
-- spi_slave_receive
---------------------------------------------------------------------------------
procedure spi_slave_receive (
variable rx_data : out std_logic_vector;
constant msg : in string;
signal spi_if : inout t_spi_if;
constant when_to_start_transfer : in t_when_to_start_transfer := START_TRANSFER_ON_NEXT_SS;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_spi_bfm_config := C_SPI_BFM_CONFIG_DEFAULT
) is
constant local_proc_name : string := "spi_slave_receive";
constant local_proc_call : string := local_proc_name & "(" & to_string(rx_data, HEX, AS_IS, INCL_RADIX) & ")";
-- Helper variables
variable v_tx_data : std_logic_vector(rx_data'length-1 downto 0) := (others => '0');
begin
spi_slave_transmit_and_receive(v_tx_data, rx_data, msg, spi_if, when_to_start_transfer, scope, msg_id_panel, config, local_proc_call);
end;
-- Multi-word
procedure spi_slave_receive (
variable rx_data : out t_slv_array;
constant msg : in string;
signal spi_if : inout t_spi_if;
constant when_to_start_transfer : in t_when_to_start_transfer := START_TRANSFER_ON_NEXT_SS;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_spi_bfm_config := C_SPI_BFM_CONFIG_DEFAULT
) is
constant local_proc_name : string := "spi_slave_receive";
constant local_proc_call : string := local_proc_name & "(" & to_string(rx_data, HEX, AS_IS, INCL_RADIX) & ")";
-- Helper variables
variable v_rx_data : t_slv_array(rx_data'length-1 downto 0)(rx_data(0)'length-1 downto 0) := (others => (others => '0'));
begin
-- call multi-word procedure
spi_slave_transmit_and_receive(v_rx_data, rx_data, msg, spi_if, when_to_start_transfer, scope, msg_id_panel, config, local_proc_call);
end;
---------------------------------------------------------------------------------
-- spi_slave_check
---------------------------------------------------------------------------------
procedure spi_slave_check (
constant data_exp : in std_logic_vector;
constant msg : in string;
signal spi_if : inout t_spi_if;
constant alert_level : in t_alert_level := error;
constant when_to_start_transfer : in t_when_to_start_transfer := START_TRANSFER_ON_NEXT_SS;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_spi_bfm_config := C_SPI_BFM_CONFIG_DEFAULT
) is
constant local_proc_name : string := "spi_slave_check";
constant local_proc_call : string := local_proc_name & "(" & to_string(data_exp, HEX, AS_IS, INCL_RADIX) & ")";
-- Helper variables
variable v_rx_data : std_logic_vector(data_exp'length-1 downto 0) := (others => 'X');
variable v_tx_data : std_logic_vector(data_exp'length-1 downto 0) := (others => '0');
variable v_check_ok : boolean;
begin
spi_slave_transmit_and_receive(v_tx_data, v_rx_data, msg, spi_if, when_to_start_transfer, scope, msg_id_panel, config, local_proc_call);
-- Compare values, but ignore any leading zero's if widths are different.
-- Use ID_NEVER so that check_value method does not log when check is OK,
-- log it here instead.
v_check_ok := check_value(v_rx_data, data_exp, alert_level, msg, scope, HEX_BIN_IF_INVALID, SKIP_LEADING_0, ID_NEVER, msg_id_panel, local_proc_call);
if v_check_ok then
log(config.id_for_bfm, local_proc_call & "=> OK, read data = " & to_string(v_rx_data, HEX, SKIP_LEADING_0, INCL_RADIX) & ". " & add_msg_delimiter(msg), scope, msg_id_panel);
end if;
end procedure;
-- Multi-word
procedure spi_slave_check (
constant data_exp : in t_slv_array;
constant msg : in string;
signal spi_if : inout t_spi_if;
constant alert_level : in t_alert_level := error;
constant when_to_start_transfer : in t_when_to_start_transfer := START_TRANSFER_ON_NEXT_SS;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_spi_bfm_config := C_SPI_BFM_CONFIG_DEFAULT
) is
begin
for idx in 0 to (data_exp'length-1) loop
-- call singl-word procedure - will handle error check
spi_slave_check(data_exp(idx), msg, spi_if, alert_level, when_to_start_transfer, scope, msg_id_panel, config);
end loop;
end procedure;
end package body spi_bfm_pkg;
|
--========================================================================================================================
-- Copyright (c) 2017 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <[email protected]>.
--
-- UVVM AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
-- WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS
-- OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
-- OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH UVVM OR THE USE OR OTHER DEALINGS IN UVVM.
--========================================================================================================================
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library std;
use std.textio.all;
library uvvm_util;
context uvvm_util.uvvm_util_context;
--=================================================================================================
package spi_bfm_pkg is
--===============================================================================================
-- Types and constants for SPI BFMs
--===============================================================================================
constant C_SCOPE : string := "SPI BFM";
type t_spi_if is record
ss_n : std_logic; -- master to slave
sclk : std_logic; -- master to slave
mosi : std_logic; -- master to slave
miso : std_logic; -- slave to master
end record;
-- Configuration record to be assigned in the test harness.
type t_spi_bfm_config is
record
CPOL : std_logic; -- sclk polarity, i.e. the base value of the clock.
-- If CPOL is '0', the clock will be set to '0' when inactive, i.e., ordinary positive polarity.
CPHA : std_logic; -- sclk phase, i.e. when data is sampled and transmitted w.r.t. sclk.
-- If '0', sampling occurs on the first sclk edge and data is transmitted on the sclk active to idle state.
-- If '1', data is sampled on the second sclk edge and transmitted on sclk idle to active state.
spi_bit_time : time; -- Used in master for dictating sclk period
ss_n_to_sclk : time; -- Time from SS active until SCLK active
sclk_to_ss_n : time; -- Last SCLK until SS off
inter_word_delay : time; -- Minimum time between words, from ss_n inactive to ss_n active
id_for_bfm : t_msg_id; -- The message ID used as a general message ID in the SPI BFM
id_for_bfm_wait : t_msg_id; -- The message ID used for logging waits in the SPI BFM
id_for_bfm_poll : t_msg_id; -- The message ID used for logging polling in the SPI BFM
end record;
constant C_SPI_BFM_CONFIG_DEFAULT : t_spi_bfm_config := (
CPOL => '0',
CPHA => '0',
spi_bit_time => -1 ns, -- Make sure we notice if we forget to set bit time.
ss_n_to_sclk => 20 ns,
sclk_to_ss_n => 20 ns,
inter_word_delay => 0 ns,
id_for_bfm => ID_BFM,
id_for_bfm_wait => ID_BFM_WAIT,
id_for_bfm_poll => ID_BFM_POLL
);
--===============================================================================================
-- BFM procedures
--===============================================================================================
------------------------------------------
-- init_spi_if_signals
------------------------------------------
-- - This function returns an SPI interface with initialized signals.
-- - master_mode = true:
-- - ss_n initialized to 'H'
-- - if config.CPOL = '1', sclk initialized to 'H',
-- otherwise sclk initialized to 'L'
-- - miso and mosi initialized to 'Z'
-- - master_mode = false:
-- - all signals initialized to 'Z'
function init_spi_if_signals (
constant config : in t_spi_bfm_config;
constant master_mode : in boolean := true
) return t_spi_if;
------------------------------------------
-- spi_master_transmit_and_receive
------------------------------------------
-- This procedure transmits data 'tx_data' to the SPI slave DUT
-- and receives 'rx_data' from the SPI slave DUT.
procedure spi_master_transmit_and_receive (
constant tx_data : in std_logic_vector;
variable rx_data : out std_logic_vector;
constant msg : in string;
signal sclk : inout std_logic;
signal ss_n : inout std_logic;
signal mosi : inout std_logic;
signal miso : inout std_logic;
constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_spi_bfm_config := C_SPI_BFM_CONFIG_DEFAULT;
constant ext_proc_call : in string := "" -- External proc_call; overwrite if called from other BFM procedure like spi_*_check
);
------------------------------------------
-- spi_master_transmit_and_receive
------------------------------------------
-- This procedure transmits data 'tx_data' to the SPI slave DUT
-- and receives 'rx_data' from the SPI slave DUT.
-- The SPI interface in this procedure is given as a t_spi_if signal record
procedure spi_master_transmit_and_receive (
constant tx_data : in std_logic_vector;
variable rx_data : out std_logic_vector;
constant msg : in string;
signal spi_if : inout t_spi_if;
constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_spi_bfm_config := C_SPI_BFM_CONFIG_DEFAULT;
constant ext_proc_call : in string := "" -- External proc_call; overwrite if called from other BFM procedure like spi_*_check
);
-- Multi-word
procedure spi_master_transmit_and_receive (
constant tx_data : in t_slv_array;
variable rx_data : out t_slv_array;
constant msg : in string;
signal spi_if : inout t_spi_if;
constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER;
constant action_between_words : in t_action_between_words := HOLD_LINE_BETWEEN_WORDS;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_spi_bfm_config := C_SPI_BFM_CONFIG_DEFAULT;
constant ext_proc_call : in string := "" -- External proc_call; overwrite if called from other BFM procedure like spi_*_check
);
------------------------------------------
-- spi_master_transmit_and_check
------------------------------------------
-- This procedure ...
-- The SPI interface in this procedure is given as a t_spi_if signal record
procedure spi_master_transmit_and_check(
constant tx_data : in std_logic_vector;
constant data_exp : in std_logic_vector;
constant msg : in string;
signal spi_if : inout t_spi_if;
constant alert_level : in t_alert_level := error;
constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_spi_bfm_config := C_SPI_BFM_CONFIG_DEFAULT
);
-- Multi-word
procedure spi_master_transmit_and_check(
constant tx_data : in t_slv_array;
constant data_exp : in t_slv_array;
constant msg : in string;
signal spi_if : inout t_spi_if;
constant alert_level : in t_alert_level := error;
constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER;
constant action_between_words : in t_action_between_words := HOLD_LINE_BETWEEN_WORDS;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_spi_bfm_config := C_SPI_BFM_CONFIG_DEFAULT
);
------------------------------------------
-- spi_master_transmit
------------------------------------------
-- This procedure transmits data 'tx_data' to the SPI DUT
-- The SPI interface in this procedure is given as a t_spi_if signal record
procedure spi_master_transmit(
constant tx_data : in std_logic_vector;
constant msg : in string;
signal spi_if : inout t_spi_if;
constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_spi_bfm_config := C_SPI_BFM_CONFIG_DEFAULT
);
-- Multi-word
procedure spi_master_transmit(
constant tx_data : in t_slv_array;
constant msg : in string;
signal spi_if : inout t_spi_if;
constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER;
constant action_between_words : in t_action_between_words := HOLD_LINE_BETWEEN_WORDS;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_spi_bfm_config := C_SPI_BFM_CONFIG_DEFAULT
);
------------------------------------------
-- spi_master_receive
------------------------------------------
-- This procedure receives data 'rx_data' from the SPI DUT
-- The SPI interface in this procedure is given as a t_spi_if signal record
procedure spi_master_receive(
variable rx_data : out std_logic_vector;
constant msg : in string;
signal spi_if : inout t_spi_if;
constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_spi_bfm_config := C_SPI_BFM_CONFIG_DEFAULT
);
-- Multi-word
procedure spi_master_receive(
variable rx_data : out t_slv_array;
constant msg : in string;
signal spi_if : inout t_spi_if;
constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER;
constant action_between_words : in t_action_between_words := HOLD_LINE_BETWEEN_WORDS;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_spi_bfm_config := C_SPI_BFM_CONFIG_DEFAULT
);
------------------------------------------
-- spi_master_check
------------------------------------------
-- This procedure receives an SPI transaction, and compares the read data
-- to the expected data in 'data_exp'.
-- If the read data is inconsistent with the expected data, an alert with
-- severity 'alert_level' is triggered.
-- The SPI interface in this procedure is given as a t_spi_if signal record
procedure spi_master_check(
constant data_exp : in std_logic_vector;
constant msg : in string;
signal spi_if : inout t_spi_if;
constant alert_level : in t_alert_level := error;
constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_spi_bfm_config := C_SPI_BFM_CONFIG_DEFAULT
);
-- Multi-word
procedure spi_master_check(
constant data_exp : in t_slv_array;
constant msg : in string;
signal spi_if : inout t_spi_if;
constant alert_level : in t_alert_level := error;
constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER;
constant action_between_words : in t_action_between_words := HOLD_LINE_BETWEEN_WORDS;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_spi_bfm_config := C_SPI_BFM_CONFIG_DEFAULT
);
------------------------------------------
-- spi_slave_transmit_and_receive
------------------------------------------
-- This procedure transmits data 'tx_data' to the SPI master DUT
-- and receives 'rx_data' from the SPI master DUT.
procedure spi_slave_transmit_and_receive (
constant tx_data : in std_logic_vector;
variable rx_data : out std_logic_vector;
constant msg : in string;
signal sclk : inout std_logic;
signal ss_n : inout std_logic;
signal mosi : inout std_logic;
signal miso : inout std_logic;
constant when_to_start_transfer : in t_when_to_start_transfer := START_TRANSFER_ON_NEXT_SS;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_spi_bfm_config := C_SPI_BFM_CONFIG_DEFAULT;
constant ext_proc_call : in string := "" -- External proc_call; overwrite if called from other BFM procedure like spi_*_check
);
------------------------------------------
-- spi_slave_transmit_and_receive
------------------------------------------
-- This procedure transmits data 'tx_data' to the SPI master DUT
-- and receives 'rx_data' from the SPI master DUT.
-- The SPI interface in this procedure is given as a t_spi_if signal record
procedure spi_slave_transmit_and_receive (
constant tx_data : in std_logic_vector;
variable rx_data : out std_logic_vector;
constant msg : in string;
signal spi_if : inout t_spi_if;
constant when_to_start_transfer : in t_when_to_start_transfer := START_TRANSFER_ON_NEXT_SS;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_spi_bfm_config := C_SPI_BFM_CONFIG_DEFAULT;
constant ext_proc_call : in string := "" -- External proc_call; overwrite if called from other BFM procedure like spi_*_check
);
-- Multi-word
procedure spi_slave_transmit_and_receive (
constant tx_data : in t_slv_array;
variable rx_data : out t_slv_array;
constant msg : in string;
signal spi_if : inout t_spi_if;
constant when_to_start_transfer : in t_when_to_start_transfer := START_TRANSFER_ON_NEXT_SS;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_spi_bfm_config := C_SPI_BFM_CONFIG_DEFAULT;
constant ext_proc_call : in string := "" -- External proc_call; overwrite if called from other BFM procedure like spi_*_check
);
------------------------------------------
-- spi_slave_transmit_and_check
------------------------------------------
-- This procedure ...
-- The SPI interface in this procedure is given as a t_spi_if signal record
procedure spi_slave_transmit_and_check(
constant tx_data : in std_logic_vector;
constant data_exp : in std_logic_vector;
constant msg : in string;
signal spi_if : inout t_spi_if;
constant alert_level : in t_alert_level := error;
constant when_to_start_transfer : in t_when_to_start_transfer := START_TRANSFER_ON_NEXT_SS;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_spi_bfm_config := C_SPI_BFM_CONFIG_DEFAULT
);
-- Multi-word
procedure spi_slave_transmit_and_check(
constant tx_data : in t_slv_array;
constant data_exp : in t_slv_array;
constant msg : in string;
signal spi_if : inout t_spi_if;
constant alert_level : in t_alert_level := error;
constant when_to_start_transfer : in t_when_to_start_transfer := START_TRANSFER_ON_NEXT_SS;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_spi_bfm_config := C_SPI_BFM_CONFIG_DEFAULT
);
------------------------------------------
-- spi_slave_transmit
------------------------------------------
-- This procedure transmits data 'tx_data' to the SPI DUT
-- The SPI interface in this procedure is given as a t_spi_if signal record
procedure spi_slave_transmit (
constant tx_data : in std_logic_vector;
constant msg : in string;
signal spi_if : inout t_spi_if;
constant when_to_start_transfer : in t_when_to_start_transfer := START_TRANSFER_ON_NEXT_SS;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_spi_bfm_config := C_SPI_BFM_CONFIG_DEFAULT
);
-- Multi-word
procedure spi_slave_transmit (
constant tx_data : in t_slv_array;
constant msg : in string;
signal spi_if : inout t_spi_if;
constant when_to_start_transfer : in t_when_to_start_transfer := START_TRANSFER_ON_NEXT_SS;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_spi_bfm_config := C_SPI_BFM_CONFIG_DEFAULT
);
------------------------------------------
-- spi_slave_receive
------------------------------------------
-- This procedure receives data 'rx_data' from the SPI DUT
-- The SPI interface in this procedure is given as a t_spi_if signal record
procedure spi_slave_receive (
variable rx_data : out std_logic_vector;
constant msg : in string;
signal spi_if : inout t_spi_if;
constant when_to_start_transfer : in t_when_to_start_transfer := START_TRANSFER_ON_NEXT_SS;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_spi_bfm_config := C_SPI_BFM_CONFIG_DEFAULT
);
-- Multi-word
procedure spi_slave_receive (
variable rx_data : out t_slv_array;
constant msg : in string;
signal spi_if : inout t_spi_if;
constant when_to_start_transfer : in t_when_to_start_transfer := START_TRANSFER_ON_NEXT_SS;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_spi_bfm_config := C_SPI_BFM_CONFIG_DEFAULT
);
------------------------------------------
-- spi_slave_check
------------------------------------------
-- This procedure receives an SPI transaction, and compares the read data
-- to the expected data in 'data_exp'.
-- If the read data is inconsistent with the expected data, an alert with
-- severity 'alert_level' is triggered.
-- The SPI interface in this procedure is given as a t_spi_if signal record
procedure spi_slave_check (
constant data_exp : in std_logic_vector;
constant msg : in string;
signal spi_if : inout t_spi_if;
constant alert_level : in t_alert_level := error;
constant when_to_start_transfer : in t_when_to_start_transfer := START_TRANSFER_ON_NEXT_SS;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_spi_bfm_config := C_SPI_BFM_CONFIG_DEFAULT
);
-- Multi-word
procedure spi_slave_check (
constant data_exp : in t_slv_array;
constant msg : in string;
signal spi_if : inout t_spi_if;
constant alert_level : in t_alert_level := error;
constant when_to_start_transfer : in t_when_to_start_transfer := START_TRANSFER_ON_NEXT_SS;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_spi_bfm_config := C_SPI_BFM_CONFIG_DEFAULT
);
end package spi_bfm_pkg;
--=================================================================================================
--=================================================================================================
package body spi_bfm_pkg is
---------------------------------------------------------------------------------
-- initialize spi to dut signals
---------------------------------------------------------------------------------
function init_spi_if_signals (
constant config : in t_spi_bfm_config;
constant master_mode : in boolean := true
) return t_spi_if is
variable result : t_spi_if;
begin
if master_mode then
result.ss_n := 'H';
if (config.CPOL) then
result.sclk := 'H';
else
result.sclk := 'L';
end if;
else
result.ss_n := 'Z';
result.sclk := 'Z';
end if;
result.mosi := 'Z';
result.miso := 'Z';
return result;
end function;
---------------------------------------------------------------------------------
-- spi_master_transmit_and_receive
--
-- alert if size of tx_data or rx_data doesn't
-- match with how long ss_n is kept low
---------------------------------------------------------------------------------
procedure spi_master_transmit_and_receive (
constant tx_data : in std_logic_vector;
variable rx_data : out std_logic_vector;
constant msg : in string;
signal sclk : inout std_logic;
signal ss_n : inout std_logic;
signal mosi : inout std_logic;
signal miso : inout std_logic;
constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_spi_bfm_config := C_SPI_BFM_CONFIG_DEFAULT;
constant ext_proc_call : in string := "" -- External proc_call; overwrite if called from other BFM procedure like spi_*_check
) is
constant local_proc_name : string := "spi_master_transmit_and_receive";
constant local_proc_call : string := local_proc_name;
constant C_ACCESS_SIZE : integer := tx_data'length;
-- Helper variables
variable v_access_done : boolean := false;
variable v_tx_count : integer := 0;
variable v_tx_data : std_logic_vector(tx_data'length-1 downto 0) := tx_data;
variable v_rx_data : std_logic_vector(rx_data'length-1 downto 0) := (others => 'X');
variable v_rx_count : integer := 1;
variable v_proc_call : line;
variable v_multi_word_transfer_in_progress : boolean := false;
begin
-- check whether config.spi_bit_time was set
check_value(config.spi_bit_time /= -1 ns, TB_ERROR, "SPI Bit time was not set in config. " & add_msg_delimiter(msg), C_SCOPE, ID_NEVER, msg_id_panel);
if ext_proc_call = "" then
-- Called directly from sequencer/VVC. Include 'spi_master_transmit_and_receive' when logging
write(v_proc_call, local_proc_call);
else
-- Called from other BFM procedure like spi_*_check. Include 'spi_*_check(..) while executing spi_master_transmit_and_receive' when logging
write(v_proc_call, ext_proc_call & " while executing " & local_proc_name);
end if;
-- Detect if we have an ongoing multi-word transfer
if ss_n = '0' then
v_multi_word_transfer_in_progress := true;
end if;
sclk <= config.CPOL;
ss_n <= '0';
wait for 0 ns; -- wait a delta cycle
if ss_n = '0' then
-- set MOSI together with SS_N when CPHA=0
if not config.CPHA then
mosi <= v_tx_data(C_ACCESS_SIZE- v_tx_count - 1);
v_tx_count := v_tx_count + 1;
end if;
-- Decide delay before initial SCLK edge
if not v_multi_word_transfer_in_progress then
wait for config.ss_n_to_sclk;
else
wait for config.spi_bit_time/2;
end if;
sclk <= not config.CPOL;
-- serially shift out v_tx_data to mosi
-- serially shift in v_rx_data from miso
while ss_n = '0' and not v_access_done loop
if not config.CPHA then
v_rx_data(C_ACCESS_SIZE-v_rx_count) := miso;
wait for config.spi_bit_time/2;
sclk <= config.CPOL;
mosi <= v_tx_data(C_ACCESS_SIZE-v_tx_count-1);
else -- config.CPHA
mosi <= v_tx_data(C_ACCESS_SIZE-v_tx_count-1);
wait for config.spi_bit_time/2;
sclk <= config.CPOL;
v_rx_data(C_ACCESS_SIZE-v_rx_count) := miso;
end if;
if v_tx_count < C_ACCESS_SIZE-1 then -- Not done
v_rx_count := v_rx_count + 1;
v_tx_count := v_tx_count + 1;
wait for config.spi_bit_time/2;
sclk <= not config.CPOL;
else -- Final bit
if not config.CPHA then
v_rx_count := v_rx_count + 1;
-- Sample Last bit on the second to last edge of SCLK (CPOL=0: last rising. CPOL=1: last falling)
wait for config.spi_bit_time/2;
v_rx_data(C_ACCESS_SIZE-v_rx_count) := miso;
sclk <= not config.CPOL;
end if;
log(config.id_for_bfm, v_proc_call.all & "=> " & to_string(v_tx_data, HEX, SKIP_LEADING_0, INCL_RADIX) & " completed. " & add_msg_delimiter(msg), scope, msg_id_panel);
v_access_done := true;
end if;
end loop;
-- Clock the last bit
if not config.CPHA then
wait for config.spi_bit_time/2;
sclk <= config.CPOL;
end if;
-- Determine if single- or multi-word transfer
if action_when_transfer_is_done = RELEASE_LINE_AFTER_TRANSFER then
wait for config.sclk_to_ss_n;
mosi <= 'Z';
ss_n <= '1';
wait for config.inter_word_delay;
else -- action_when_transfer_is_done = HOLD_LINE_AFTER_TRANSFER
ss_n <= '0';
end if;
wait for 0 ns; -- delta cycle
if (v_tx_count /= C_ACCESS_SIZE-1) or (v_rx_count /= C_ACCESS_SIZE) then
alert(note, " v_tx_count /= C_ACCESS_SIZE-1 or v_rx_count /= C_ACCESS_SIZE then");
alert(note, to_string(v_tx_count) & " /= " & to_string(C_ACCESS_SIZE-1) & " or" &to_string(v_rx_count) & " /= " & to_string(C_ACCESS_SIZE));
alert(note, local_proc_name & " ss_n not kept low for v_tx_data size duration");
else
rx_data := v_rx_data;
end if;
else
alert(error, local_proc_name & " ss_n not low when expected.");
end if;
if ext_proc_call = "" then -- proc_name = "spi_master_transmit_and_receive"
log(config.id_for_bfm, v_proc_call.all & "=> Transmitted: " & to_string(v_tx_data, HEX, SKIP_LEADING_0, INCL_RADIX) & ". Received: " & to_string(v_rx_data, HEX, SKIP_LEADING_0, INCL_RADIX) & ". " & add_msg_delimiter(msg), scope, msg_id_panel);
end if;
end procedure;
-- Single-word
procedure spi_master_transmit_and_receive (
constant tx_data : in std_logic_vector;
variable rx_data : out std_logic_vector;
constant msg : in string;
signal spi_if : inout t_spi_if;
constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_spi_bfm_config := C_SPI_BFM_CONFIG_DEFAULT;
constant ext_proc_call : in string := "" -- External proc_call; overwrite if called from other BFM procedure like spi_*_check
) is
begin
spi_master_transmit_and_receive(tx_data, rx_data, msg,
spi_if.sclk, spi_if.ss_n, spi_if.mosi, spi_if.miso,
action_when_transfer_is_done, scope, msg_id_panel, config, ext_proc_call);
end procedure;
-- Multi-word
procedure spi_master_transmit_and_receive (
constant tx_data : in t_slv_array;
variable rx_data : out t_slv_array;
constant msg : in string;
signal spi_if : inout t_spi_if;
constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER;
constant action_between_words : in t_action_between_words := HOLD_LINE_BETWEEN_WORDS;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_spi_bfm_config := C_SPI_BFM_CONFIG_DEFAULT;
constant ext_proc_call : in string := "" -- External proc_call; overwrite if called from other BFM procedure like spi_*_check
) is
variable v_action_when_transfer_is_done : t_action_when_transfer_is_done; -- between words and after transfer
begin
-- Check length of tx_data and rx_data
if tx_data'length /= rx_data'length then
alert(error, ext_proc_call & " tx_data and rx_data have different sizes.");
end if;
for idx in 0 to (tx_data'length-1) loop
case action_between_words is
when RELEASE_LINE_BETWEEN_WORDS =>
if idx < tx_data'length-1 then
v_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER;
else
v_action_when_transfer_is_done := action_when_transfer_is_done;
end if;
when others => -- HOLD_LINE_BETWEEN_WORDS
if idx < tx_data'length-1 then
v_action_when_transfer_is_done := HOLD_LINE_AFTER_TRANSFER;
else
v_action_when_transfer_is_done := action_when_transfer_is_done;
end if;
end case;
-- call single-word procedure
spi_master_transmit_and_receive(tx_data(idx), rx_data(idx), msg, spi_if, v_action_when_transfer_is_done, scope, msg_id_panel, config, ext_proc_call);
end loop;
end procedure;
---------------------------------------------------------------------------------
-- spi_master_transmit_and_check
---------------------------------------------------------------------------------
procedure spi_master_transmit_and_check(
constant tx_data : in std_logic_vector;
constant data_exp : in std_logic_vector;
constant msg : in string;
signal spi_if : inout t_spi_if;
constant alert_level : in t_alert_level := error;
constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_spi_bfm_config := C_SPI_BFM_CONFIG_DEFAULT
) is
constant local_proc_name : string := "spi_master_transmit_and_check";
constant local_proc_call : string := local_proc_name;
-- Helper variables
variable v_rx_data : std_logic_vector(data_exp'length-1 downto 0);
variable v_check_ok : boolean;
begin
spi_master_transmit_and_receive(tx_data, v_rx_data, msg, spi_if, action_when_transfer_is_done, scope, msg_id_panel, config, local_proc_call);
-- Compare values, but ignore any leading zero's if widths are different.
-- Use ID_NEVER so that check_value method does not log when check is OK,
-- log it here instead.
v_check_ok := check_value(v_rx_data, data_exp, alert_level, msg, scope, HEX_BIN_IF_INVALID, SKIP_LEADING_0, ID_NEVER, msg_id_panel, local_proc_call);
if v_check_ok then
log(config.id_for_bfm, local_proc_call & "=> OK, read data = " & to_string(v_rx_data, HEX, SKIP_LEADING_0, INCL_RADIX) & ". " & add_msg_delimiter(msg), scope, msg_id_panel);
end if;
end procedure;
-- Multi-word
procedure spi_master_transmit_and_check(
constant tx_data : in t_slv_array;
constant data_exp : in t_slv_array;
constant msg : in string;
signal spi_if : inout t_spi_if;
constant alert_level : in t_alert_level := error;
constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER;
constant action_between_words : in t_action_between_words := HOLD_LINE_BETWEEN_WORDS;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_spi_bfm_config := C_SPI_BFM_CONFIG_DEFAULT
) is
constant local_proc_name : string := "spi_master_transmit_and_check";
constant local_proc_call : string := local_proc_name;
variable v_action_when_transfer_is_done : t_action_when_transfer_is_done; -- between words and after transfer
begin
-- Check length of tx_data and data_exp
if tx_data'length /= data_exp'length then
alert(error, local_proc_call & " tx_data and data_exp have different sizes.");
end if;
for idx in 0 to (tx_data'length-1) loop
case action_between_words is
when RELEASE_LINE_BETWEEN_WORDS =>
if idx < tx_data'length-1 then
v_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER;
else
v_action_when_transfer_is_done := action_when_transfer_is_done;
end if;
when others => -- HOLD_LINE_BETWEEN_WORDS
if idx < tx_data'length-1 then
v_action_when_transfer_is_done := HOLD_LINE_AFTER_TRANSFER;
else
v_action_when_transfer_is_done := action_when_transfer_is_done;
end if;
end case;
-- call single-word procedure
spi_master_transmit_and_check(tx_data(idx), data_exp(idx), msg, spi_if, alert_level, v_action_when_transfer_is_done, scope, msg_id_panel, config);
end loop;
end procedure;
---------------------------------------------------------------------------------
-- spi_master_transmit
---------------------------------------------------------------------------------
procedure spi_master_transmit(
constant tx_data : in std_logic_vector;
constant msg : in string;
signal spi_if : inout t_spi_if;
constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_spi_bfm_config := C_SPI_BFM_CONFIG_DEFAULT
) is
constant local_proc_name : string := "spi_master_transmit";
constant local_proc_call : string := local_proc_name;
-- Helper variables
variable v_rx_data : std_logic_vector(tx_data'length - 1 downto 0);
begin
spi_master_transmit_and_receive(tx_data, v_rx_data, msg, spi_if, action_when_transfer_is_done, scope, msg_id_panel, config, local_proc_call);
end procedure;
-- Multi-word
procedure spi_master_transmit(
constant tx_data : in t_slv_array;
constant msg : in string;
signal spi_if : inout t_spi_if;
constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER;
constant action_between_words : in t_action_between_words := HOLD_LINE_BETWEEN_WORDS;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_spi_bfm_config := C_SPI_BFM_CONFIG_DEFAULT
) is
variable v_action_when_transfer_is_done : t_action_when_transfer_is_done; -- between words and after transfer
begin
for idx in 0 to (tx_data'length-1) loop
case action_between_words is
when RELEASE_LINE_BETWEEN_WORDS =>
if idx < tx_data'length-1 then
v_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER;
else
v_action_when_transfer_is_done := action_when_transfer_is_done;
end if;
when others => -- HOLD_LINE_BETWEEN_WORDS
if idx < tx_data'length-1 then
v_action_when_transfer_is_done := HOLD_LINE_AFTER_TRANSFER;
else
v_action_when_transfer_is_done := action_when_transfer_is_done;
end if;
end case;
-- call single-word procedure
spi_master_transmit(tx_data(idx), msg, spi_if, v_action_when_transfer_is_done, scope, msg_id_panel, config);
end loop;
end procedure;
---------------------------------------------------------------------------------
-- spi_master_receive
---------------------------------------------------------------------------------
procedure spi_master_receive(
variable rx_data : out std_logic_vector;
constant msg : in string;
signal spi_if : inout t_spi_if;
constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_spi_bfm_config := C_SPI_BFM_CONFIG_DEFAULT
) is
constant local_proc_name : string := "spi_master_receive";
constant local_proc_call : string := local_proc_name;
-- Helper variables
variable v_tx_data : std_logic_vector(rx_data'length - 1 downto 0) := (others => '0');
begin
spi_master_transmit_and_receive(v_tx_data, rx_data, msg, spi_if, action_when_transfer_is_done, scope, msg_id_panel, config, local_proc_call);
end procedure;
-- Multi-word
procedure spi_master_receive(
variable rx_data : out t_slv_array;
constant msg : in string;
signal spi_if : inout t_spi_if;
constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER;
constant action_between_words : in t_action_between_words := HOLD_LINE_BETWEEN_WORDS;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_spi_bfm_config := C_SPI_BFM_CONFIG_DEFAULT
) is
variable v_action_when_transfer_is_done : t_action_when_transfer_is_done; -- between words and after transfer
begin
for idx in 0 to (rx_data'length-1) loop
case action_between_words is
when RELEASE_LINE_BETWEEN_WORDS =>
if idx < rx_data'length-1 then
v_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER;
else
v_action_when_transfer_is_done := action_when_transfer_is_done;
end if;
when others => -- HOLD_LINE_BETWEEN_WORDS
if idx < rx_data'length-1 then
v_action_when_transfer_is_done := HOLD_LINE_AFTER_TRANSFER;
else
v_action_when_transfer_is_done := action_when_transfer_is_done;
end if;
end case;
-- call single-word procedure
spi_master_receive(rx_data(idx), msg, spi_if, v_action_when_transfer_is_done, scope, msg_id_panel, config);
end loop;
end procedure;
---------------------------------------------------------------------------------
-- spi_master_check
---------------------------------------------------------------------------------
procedure spi_master_check(
constant data_exp : in std_logic_vector;
constant msg : in string;
signal spi_if : inout t_spi_if;
constant alert_level : in t_alert_level := error;
constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_spi_bfm_config := C_SPI_BFM_CONFIG_DEFAULT
) is
constant local_proc_name : string := "spi_master_check";
constant local_proc_call : string := local_proc_name;
-- Helper variables
variable v_tx_data : std_logic_vector(data_exp'length - 1 downto 0) := (others => '0');
variable v_rx_data : std_logic_vector(data_exp'length-1 downto 0);
variable v_check_ok : boolean;
begin
spi_master_transmit_and_receive(v_tx_data, v_rx_data, msg, spi_if, action_when_transfer_is_done, scope, msg_id_panel, config, local_proc_call);
-- Compare values, but ignore any leading zero's if widths are different.
-- Use ID_NEVER so that check_value method does not log when check is OK,
-- log it here instead.
v_check_ok := check_value(v_rx_data, data_exp, alert_level, msg, scope, HEX_BIN_IF_INVALID, SKIP_LEADING_0, ID_NEVER, msg_id_panel, local_proc_call);
if v_check_ok then
log(config.id_for_bfm, local_proc_call & "=> OK, read data = " & to_string(v_rx_data, HEX, SKIP_LEADING_0, INCL_RADIX) & ". " & add_msg_delimiter(msg), scope, msg_id_panel);
end if;
end procedure;
-- Multi-word
procedure spi_master_check(
constant data_exp : in t_slv_array;
constant msg : in string;
signal spi_if : inout t_spi_if;
constant alert_level : in t_alert_level := error;
constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER;
constant action_between_words : in t_action_between_words := HOLD_LINE_BETWEEN_WORDS;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_spi_bfm_config := C_SPI_BFM_CONFIG_DEFAULT
) is
variable v_action_when_transfer_is_done : t_action_when_transfer_is_done; -- between words and after transfer
begin
for idx in 0 to (data_exp'length-1) loop
case action_between_words is
when RELEASE_LINE_BETWEEN_WORDS =>
if idx < data_exp'length-1 then
v_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER;
else
v_action_when_transfer_is_done := action_when_transfer_is_done;
end if;
when others => -- HOLD_LINE_BETWEEN_WORDS
if idx < data_exp'length-1 then
v_action_when_transfer_is_done := HOLD_LINE_AFTER_TRANSFER;
else
v_action_when_transfer_is_done := action_when_transfer_is_done;
end if;
end case;
-- call single-word procedure
spi_master_check(data_exp(idx), msg, spi_if, alert_level, v_action_when_transfer_is_done, scope, msg_id_panel, config);
end loop;
end procedure;
---------------------------------------------------------------------------------
-- spi_slave_transmit_and_receive
--
---------------------------------------------------------------------------------
procedure spi_slave_transmit_and_receive (
constant tx_data : in std_logic_vector;
variable rx_data : out std_logic_vector;
constant msg : in string;
signal sclk : inout std_logic;
signal ss_n : inout std_logic;
signal mosi : inout std_logic;
signal miso : inout std_logic;
constant when_to_start_transfer : in t_when_to_start_transfer := START_TRANSFER_ON_NEXT_SS;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_spi_bfm_config := C_SPI_BFM_CONFIG_DEFAULT;
constant ext_proc_call : in string := "" -- External proc_call; overwrite if called from other BFM procedure like spi_*_check
) is
-- Local_proc_name/call used if called from sequencer or VVC
constant local_proc_name : string := "spi_slave_transmit_and_receive";
constant local_proc_call : string := local_proc_name;
constant C_ACCESS_SIZE : integer := rx_data'length;
-- Helper variables
variable v_rx_data : std_logic_vector(rx_data'range) := (others => 'X');
variable bfm_tx_data : std_logic_vector(tx_data'length-1 downto 0) := tx_data;
variable v_access_done : boolean := false;
variable v_tx_count : integer := 0;
variable v_rx_count : integer := 1;
variable v_proc_call : line;
begin
-- check whether config.spi_bit_time was set
check_value(config.spi_bit_time /= -1 ns, TB_ERROR, "SPI Bit time was not set in config. " & add_msg_delimiter(msg), C_SCOPE, ID_NEVER, msg_id_panel);
if ext_proc_call = "" then
-- Called directly from sequencer/VVC. Include 'spi_slave_receive...' when logging
write(v_proc_call, local_proc_call);
else
-- Called from other BFM procedure like spi_*_check. Include 'spi_*_check(..) while executing spi_*_receive.. when logging'
write(v_proc_call, ext_proc_call & " while executing " & local_proc_name);
end if;
-- Await for master to drive SS_N and SCLK
if (ss_n /= '0') then -- master not acvtive
wait until (ss_n = '0');
elsif (ss_n = '0') then -- master active
case when_to_start_transfer is
when START_TRANSFER_ON_NEXT_SS =>
if (ss_n = '0') and (ss_n'last_active > 0 ns) then
wait until (ss_n = '0') and (ss_n'last_active <= 0 ns);
end if;
when others => -- START_TRANSFER_IMMEDIATE
null;
end case;
end if;
if ss_n = '0' then
-- set MISO together with SS_N when CPHA=0
if not config.CPHA then
miso <= bfm_tx_data(C_ACCESS_SIZE - v_tx_count - 1);
v_tx_count := v_tx_count + 1;
end if;
-- Await first clock edge
if sclk = config.CPOL then
wait until sclk = not(config.CPOL);
end if;
-- Receive bits
while (ss_n = '0') and not(v_access_done) loop
if not config.CPHA then
v_rx_data(C_ACCESS_SIZE - v_rx_count) := mosi;
wait until sclk'event and sclk = config.CPOL;
miso <= bfm_tx_data(C_ACCESS_SIZE - v_tx_count - 1);
else -- config.CPHA
miso <= bfm_tx_data(C_ACCESS_SIZE - v_tx_count - 1);
wait until sclk'event and sclk = config.CPOL;
v_rx_data(C_ACCESS_SIZE - v_rx_count) := mosi;
end if;
if (v_tx_count < (C_ACCESS_SIZE-1)) and (v_rx_count < C_ACCESS_SIZE) then
wait until sclk'event and sclk = not(config.CPOL);
v_tx_count := v_tx_count + 1;
v_rx_count := v_rx_count + 1;
else
if not config.CPHA then
wait until sclk'event and sclk = not(config.CPOL);
end if;
v_access_done := true;
end if;
end loop;
end if;
-- Sample last bit
if not config.CPHA then
v_rx_count := v_rx_count + 1;
v_rx_data(C_ACCESS_SIZE - v_rx_count) := mosi;
wait until sclk'event and sclk = config.CPOL;
end if;
if (v_tx_count < C_ACCESS_SIZE-1) then
alert(error, v_proc_call.all & " ss_n not kept active for tx_data size duration " & add_msg_delimiter(msg), scope);
elsif (v_rx_count < C_ACCESS_SIZE) then
alert(error, v_proc_call.all & " ss_n not kept active for rx_data size duration " & add_msg_delimiter(msg), scope);
else
rx_data := v_rx_data;
end if;
-- Await for master to finish
wait until (mosi = 'Z')
for config.ss_n_to_sclk;
miso <= 'Z';
if ext_proc_call = "" then
log(config.id_for_bfm, local_proc_call & "=> " & to_string(v_rx_data, HEX, SKIP_LEADING_0, INCL_RADIX) & " rx completed. " & add_msg_delimiter(msg), scope, msg_id_panel);
log(config.id_for_bfm, local_proc_call & "=> " & to_string(bfm_tx_data, HEX, SKIP_LEADING_0, INCL_RADIX) & " tx completed. " & add_msg_delimiter(msg), scope, msg_id_panel);
else
-- Log will be handled by calling procedure (e.g. spi_*_check)
end if;
end procedure;
procedure spi_slave_transmit_and_receive (
constant tx_data : in std_logic_vector;
variable rx_data : out std_logic_vector;
constant msg : in string;
signal spi_if : inout t_spi_if;
constant when_to_start_transfer : in t_when_to_start_transfer := START_TRANSFER_ON_NEXT_SS;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_spi_bfm_config := C_SPI_BFM_CONFIG_DEFAULT;
constant ext_proc_call : in string := "" -- External proc_call; overwrite if called from other BFM procedure like spi_*_check
) is
begin
spi_slave_transmit_and_receive(tx_data, rx_data, msg,
spi_if.sclk, spi_if.ss_n, spi_if.mosi, spi_if.miso,
when_to_start_transfer, scope, msg_id_panel, config, ext_proc_call);
end procedure;
-- Multi-word
procedure spi_slave_transmit_and_receive (
constant tx_data : in t_slv_array;
variable rx_data : out t_slv_array;
constant msg : in string;
signal spi_if : inout t_spi_if;
constant when_to_start_transfer : in t_when_to_start_transfer := START_TRANSFER_ON_NEXT_SS;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_spi_bfm_config := C_SPI_BFM_CONFIG_DEFAULT;
constant ext_proc_call : in string := "" -- External proc_call; overwrite if called from other BFM procedure like spi_*_check
) is
begin
-- Check length of tx_data and rx_data
if tx_data'length /= rx_data'length then
alert(error, ext_proc_call & "tx_data and rx_data have different sizes.");
end if;
for idx in 0 to (tx_data'length-1) loop
spi_slave_transmit_and_receive(tx_data(idx), rx_data(idx), msg, spi_if, when_to_start_transfer, scope, msg_id_panel, config, ext_proc_call);
end loop;
end procedure;
------------------------------------------
-- spi_slave_transmit_and_check
------------------------------------------
procedure spi_slave_transmit_and_check(
constant tx_data : in std_logic_vector;
constant data_exp : in std_logic_vector;
constant msg : in string;
signal spi_if : inout t_spi_if;
constant alert_level : in t_alert_level := error;
constant when_to_start_transfer : in t_when_to_start_transfer := START_TRANSFER_ON_NEXT_SS;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_spi_bfm_config := C_SPI_BFM_CONFIG_DEFAULT
) is
constant local_proc_name : string := "spi_slave_transmit_and_check";
constant local_proc_call : string := local_proc_name & "(" & to_string(data_exp, HEX, AS_IS, INCL_RADIX) & ")";
-- Helper variables
variable v_rx_data : std_logic_vector(data_exp'length-1 downto 0);
variable v_check_ok : boolean;
begin
spi_slave_transmit_and_receive(tx_data, v_rx_data, msg, spi_if, when_to_start_transfer, scope, msg_id_panel, config, local_proc_call);
-- Compare values, but ignore any leading zero's if widths are different.
-- Use ID_NEVER so that check_value method does not log when check is OK,
-- log it here instead.
v_check_ok := check_value(v_rx_data, data_exp, alert_level, msg, scope, HEX_BIN_IF_INVALID, SKIP_LEADING_0, ID_NEVER, msg_id_panel, local_proc_call);
if v_check_ok then
log(config.id_for_bfm, local_proc_call & "=> OK, read data = " & to_string(v_rx_data, HEX, SKIP_LEADING_0, INCL_RADIX) & ". " & add_msg_delimiter(msg), scope, msg_id_panel);
end if;
end;
-- Multi-word
procedure spi_slave_transmit_and_check(
constant tx_data : in t_slv_array;
constant data_exp : in t_slv_array;
constant msg : in string;
signal spi_if : inout t_spi_if;
constant alert_level : in t_alert_level := error;
constant when_to_start_transfer : in t_when_to_start_transfer := START_TRANSFER_ON_NEXT_SS;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_spi_bfm_config := C_SPI_BFM_CONFIG_DEFAULT
) is
constant loc_proc_call : string := "spi_slave_transmit_and_check"; -- External proc_call; overwrite if called from other BFM procedure like spi_*_check
begin
-- Check length of tx_data and rx_data
if tx_data'length /= data_exp'length then
alert(error, loc_proc_call & " tx_data and data_exp have different sizes.");
end if;
for idx in 0 to (tx_data'length-1) loop
-- call single-word procedure - will handle error checking
spi_slave_transmit_and_check(tx_data(idx), data_exp(idx), msg, spi_if, alert_level, when_to_start_transfer, scope, msg_id_panel, config);
end loop;
end;
---------------------------------------------------------------------------------
-- spi_slave_transmit
---------------------------------------------------------------------------------
procedure spi_slave_transmit(
constant tx_data : in std_logic_vector;
constant msg : in string;
signal spi_if : inout t_spi_if;
constant when_to_start_transfer : in t_when_to_start_transfer := START_TRANSFER_ON_NEXT_SS;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_spi_bfm_config := C_SPI_BFM_CONFIG_DEFAULT
) is
constant local_proc_name : string := "spi_slave_transmit";
constant local_proc_call : string := local_proc_name & "(" & to_string(tx_data, HEX, AS_IS, INCL_RADIX) & ")";
-- Helper variables
variable v_rx_data : std_logic_vector(tx_data'length-1 downto 0); -- := (others => '0');
begin
spi_slave_transmit_and_receive(tx_data, v_rx_data, msg, spi_if, when_to_start_transfer, scope, msg_id_panel, config, local_proc_call);
end procedure;
-- Multi-word
procedure spi_slave_transmit(
constant tx_data : in t_slv_array;
constant msg : in string;
signal spi_if : inout t_spi_if;
constant when_to_start_transfer : in t_when_to_start_transfer := START_TRANSFER_ON_NEXT_SS;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_spi_bfm_config := C_SPI_BFM_CONFIG_DEFAULT
) is
constant local_proc_name : string := "spi_slave_transmit";
constant local_proc_call : string := local_proc_name & "(" & to_string(tx_data, HEX, AS_IS, INCL_RADIX) & ")";
-- Helper variables
variable v_tx_data : t_slv_array(tx_data'length-1 downto 0)(tx_data(0)'length-1 downto 0) := (others => (others => '0'));
begin
-- call multi-word procedure
spi_slave_transmit_and_receive(tx_data, v_tx_data, msg, spi_if, when_to_start_transfer, scope, msg_id_panel, config, local_proc_call);
end procedure;
---------------------------------------------------------------------------------
-- spi_slave_receive
---------------------------------------------------------------------------------
procedure spi_slave_receive (
variable rx_data : out std_logic_vector;
constant msg : in string;
signal spi_if : inout t_spi_if;
constant when_to_start_transfer : in t_when_to_start_transfer := START_TRANSFER_ON_NEXT_SS;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_spi_bfm_config := C_SPI_BFM_CONFIG_DEFAULT
) is
constant local_proc_name : string := "spi_slave_receive";
constant local_proc_call : string := local_proc_name & "(" & to_string(rx_data, HEX, AS_IS, INCL_RADIX) & ")";
-- Helper variables
variable v_tx_data : std_logic_vector(rx_data'length-1 downto 0) := (others => '0');
begin
spi_slave_transmit_and_receive(v_tx_data, rx_data, msg, spi_if, when_to_start_transfer, scope, msg_id_panel, config, local_proc_call);
end;
-- Multi-word
procedure spi_slave_receive (
variable rx_data : out t_slv_array;
constant msg : in string;
signal spi_if : inout t_spi_if;
constant when_to_start_transfer : in t_when_to_start_transfer := START_TRANSFER_ON_NEXT_SS;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_spi_bfm_config := C_SPI_BFM_CONFIG_DEFAULT
) is
constant local_proc_name : string := "spi_slave_receive";
constant local_proc_call : string := local_proc_name & "(" & to_string(rx_data, HEX, AS_IS, INCL_RADIX) & ")";
-- Helper variables
variable v_rx_data : t_slv_array(rx_data'length-1 downto 0)(rx_data(0)'length-1 downto 0) := (others => (others => '0'));
begin
-- call multi-word procedure
spi_slave_transmit_and_receive(v_rx_data, rx_data, msg, spi_if, when_to_start_transfer, scope, msg_id_panel, config, local_proc_call);
end;
---------------------------------------------------------------------------------
-- spi_slave_check
---------------------------------------------------------------------------------
procedure spi_slave_check (
constant data_exp : in std_logic_vector;
constant msg : in string;
signal spi_if : inout t_spi_if;
constant alert_level : in t_alert_level := error;
constant when_to_start_transfer : in t_when_to_start_transfer := START_TRANSFER_ON_NEXT_SS;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_spi_bfm_config := C_SPI_BFM_CONFIG_DEFAULT
) is
constant local_proc_name : string := "spi_slave_check";
constant local_proc_call : string := local_proc_name & "(" & to_string(data_exp, HEX, AS_IS, INCL_RADIX) & ")";
-- Helper variables
variable v_rx_data : std_logic_vector(data_exp'length-1 downto 0) := (others => 'X');
variable v_tx_data : std_logic_vector(data_exp'length-1 downto 0) := (others => '0');
variable v_check_ok : boolean;
begin
spi_slave_transmit_and_receive(v_tx_data, v_rx_data, msg, spi_if, when_to_start_transfer, scope, msg_id_panel, config, local_proc_call);
-- Compare values, but ignore any leading zero's if widths are different.
-- Use ID_NEVER so that check_value method does not log when check is OK,
-- log it here instead.
v_check_ok := check_value(v_rx_data, data_exp, alert_level, msg, scope, HEX_BIN_IF_INVALID, SKIP_LEADING_0, ID_NEVER, msg_id_panel, local_proc_call);
if v_check_ok then
log(config.id_for_bfm, local_proc_call & "=> OK, read data = " & to_string(v_rx_data, HEX, SKIP_LEADING_0, INCL_RADIX) & ". " & add_msg_delimiter(msg), scope, msg_id_panel);
end if;
end procedure;
-- Multi-word
procedure spi_slave_check (
constant data_exp : in t_slv_array;
constant msg : in string;
signal spi_if : inout t_spi_if;
constant alert_level : in t_alert_level := error;
constant when_to_start_transfer : in t_when_to_start_transfer := START_TRANSFER_ON_NEXT_SS;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_spi_bfm_config := C_SPI_BFM_CONFIG_DEFAULT
) is
begin
for idx in 0 to (data_exp'length-1) loop
-- call singl-word procedure - will handle error check
spi_slave_check(data_exp(idx), msg, spi_if, alert_level, when_to_start_transfer, scope, msg_id_panel, config);
end loop;
end procedure;
end package body spi_bfm_pkg;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_05_ch_05_07.vhd,v 1.2 2001-10-26 16:29:33 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity ch_05_07 is
end entity ch_05_07;
----------------------------------------------------------------
library ieee; use ieee.std_logic_1164.all;
architecture test of ch_05_07 is
signal clk, d : std_ulogic;
constant Tpw_clk : delay_length := 10 ns;
constant Tsu : delay_length := 4 ns;
begin
process_05_3_c : process (clk, d) is
begin
-- code from book:
if clk'event and (clk = '1' or clk = 'H')
and (clk'last_value = '0' or clk'last_value = 'L')
then
assert d'last_event >= Tsu
report "Timing error: d changed within setup time of clk";
end if;
-- end of code from book
end process process_05_3_c;
----------------
process_05_3_d : process (clk, d) is
begin
-- code from book:
assert (not clk'event) or clk'delayed'last_event >= Tpw_clk
report "Clock frequency too high";
-- end of code from book
end process process_05_3_d;
----------------
process_05_3_e : process is
begin
-- code from book:
wait until clk = '1';
-- end of code from book
report "clk changed to '1'";
end process process_05_3_e;
----------------
stimulus_05_3_c_d : process is
begin
clk <= '1' after 15 ns,
'0' after 30 ns,
'1' after 40 ns,
'0' after 50 ns,
'H' after 60 ns,
'0' after 70 ns,
'1' after 80 ns,
'L' after 90 ns,
'H' after 100 ns,
'L' after 120 ns,
'1' after 125 ns, -- should cause error
'0' after 130 ns; -- should cause error
d <= '1' after 35 ns,
'0' after 77 ns, -- should cause error
'1' after 102 ns;
wait;
end process stimulus_05_3_c_d;
end architecture test;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_05_ch_05_07.vhd,v 1.2 2001-10-26 16:29:33 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity ch_05_07 is
end entity ch_05_07;
----------------------------------------------------------------
library ieee; use ieee.std_logic_1164.all;
architecture test of ch_05_07 is
signal clk, d : std_ulogic;
constant Tpw_clk : delay_length := 10 ns;
constant Tsu : delay_length := 4 ns;
begin
process_05_3_c : process (clk, d) is
begin
-- code from book:
if clk'event and (clk = '1' or clk = 'H')
and (clk'last_value = '0' or clk'last_value = 'L')
then
assert d'last_event >= Tsu
report "Timing error: d changed within setup time of clk";
end if;
-- end of code from book
end process process_05_3_c;
----------------
process_05_3_d : process (clk, d) is
begin
-- code from book:
assert (not clk'event) or clk'delayed'last_event >= Tpw_clk
report "Clock frequency too high";
-- end of code from book
end process process_05_3_d;
----------------
process_05_3_e : process is
begin
-- code from book:
wait until clk = '1';
-- end of code from book
report "clk changed to '1'";
end process process_05_3_e;
----------------
stimulus_05_3_c_d : process is
begin
clk <= '1' after 15 ns,
'0' after 30 ns,
'1' after 40 ns,
'0' after 50 ns,
'H' after 60 ns,
'0' after 70 ns,
'1' after 80 ns,
'L' after 90 ns,
'H' after 100 ns,
'L' after 120 ns,
'1' after 125 ns, -- should cause error
'0' after 130 ns; -- should cause error
d <= '1' after 35 ns,
'0' after 77 ns, -- should cause error
'1' after 102 ns;
wait;
end process stimulus_05_3_c_d;
end architecture test;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_05_ch_05_07.vhd,v 1.2 2001-10-26 16:29:33 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity ch_05_07 is
end entity ch_05_07;
----------------------------------------------------------------
library ieee; use ieee.std_logic_1164.all;
architecture test of ch_05_07 is
signal clk, d : std_ulogic;
constant Tpw_clk : delay_length := 10 ns;
constant Tsu : delay_length := 4 ns;
begin
process_05_3_c : process (clk, d) is
begin
-- code from book:
if clk'event and (clk = '1' or clk = 'H')
and (clk'last_value = '0' or clk'last_value = 'L')
then
assert d'last_event >= Tsu
report "Timing error: d changed within setup time of clk";
end if;
-- end of code from book
end process process_05_3_c;
----------------
process_05_3_d : process (clk, d) is
begin
-- code from book:
assert (not clk'event) or clk'delayed'last_event >= Tpw_clk
report "Clock frequency too high";
-- end of code from book
end process process_05_3_d;
----------------
process_05_3_e : process is
begin
-- code from book:
wait until clk = '1';
-- end of code from book
report "clk changed to '1'";
end process process_05_3_e;
----------------
stimulus_05_3_c_d : process is
begin
clk <= '1' after 15 ns,
'0' after 30 ns,
'1' after 40 ns,
'0' after 50 ns,
'H' after 60 ns,
'0' after 70 ns,
'1' after 80 ns,
'L' after 90 ns,
'H' after 100 ns,
'L' after 120 ns,
'1' after 125 ns, -- should cause error
'0' after 130 ns; -- should cause error
d <= '1' after 35 ns,
'0' after 77 ns, -- should cause error
'1' after 102 ns;
wait;
end process stimulus_05_3_c_d;
end architecture test;
|
-- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:proc_sys_reset:5.0
-- IP Revision: 6
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY proc_sys_reset_v5_0;
USE proc_sys_reset_v5_0.proc_sys_reset;
ENTITY base_zynq_design_rst_processing_system7_0_100M_0 IS
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END base_zynq_design_rst_processing_system7_0_100M_0;
ARCHITECTURE base_zynq_design_rst_processing_system7_0_100M_0_arch OF base_zynq_design_rst_processing_system7_0_100M_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF base_zynq_design_rst_processing_system7_0_100M_0_arch: ARCHITECTURE IS "yes";
COMPONENT proc_sys_reset IS
GENERIC (
C_FAMILY : STRING;
C_EXT_RST_WIDTH : INTEGER;
C_AUX_RST_WIDTH : INTEGER;
C_EXT_RESET_HIGH : STD_LOGIC;
C_AUX_RESET_HIGH : STD_LOGIC;
C_NUM_BUS_RST : INTEGER;
C_NUM_PERP_RST : INTEGER;
C_NUM_INTERCONNECT_ARESETN : INTEGER;
C_NUM_PERP_ARESETN : INTEGER
);
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT proc_sys_reset;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF slowest_sync_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clock CLK";
ATTRIBUTE X_INTERFACE_INFO OF ext_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 ext_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF aux_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 aux_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_debug_sys_rst: SIGNAL IS "xilinx.com:signal:reset:1.0 dbg_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 mb_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF bus_struct_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 bus_struct_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_high_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF interconnect_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 interconnect_low_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_low_rst RST";
BEGIN
U0 : proc_sys_reset
GENERIC MAP (
C_FAMILY => "zynq",
C_EXT_RST_WIDTH => 4,
C_AUX_RST_WIDTH => 4,
C_EXT_RESET_HIGH => '0',
C_AUX_RESET_HIGH => '0',
C_NUM_BUS_RST => 1,
C_NUM_PERP_RST => 1,
C_NUM_INTERCONNECT_ARESETN => 1,
C_NUM_PERP_ARESETN => 1
)
PORT MAP (
slowest_sync_clk => slowest_sync_clk,
ext_reset_in => ext_reset_in,
aux_reset_in => aux_reset_in,
mb_debug_sys_rst => mb_debug_sys_rst,
dcm_locked => dcm_locked,
mb_reset => mb_reset,
bus_struct_reset => bus_struct_reset,
peripheral_reset => peripheral_reset,
interconnect_aresetn => interconnect_aresetn,
peripheral_aresetn => peripheral_aresetn
);
END base_zynq_design_rst_processing_system7_0_100M_0_arch;
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 21:15:21 08/06/2014
-- Design Name:
-- Module Name: C:/Xilinx/14.7/workspace/prac1_beta/test_and2gate.vhd
-- Project Name: prac1_beta
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: and2gate
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
ENTITY test_and2gate IS
END test_and2gate;
ARCHITECTURE behavior OF test_and2gate IS
COMPONENT and2gate
PORT(
in1 : IN std_logic;
in2 : IN std_logic;
outAnd : OUT std_logic
);
END COMPONENT;
signal inputs : std_logic_vector(1 downto 0) := "00";
signal outAnd : std_logic;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: and2gate PORT MAP (
in1 => inputs(0),
in2 => inputs(1),
outAnd => outAnd
);
input_gen : process
begin
inputs <= "00";
--this loop will walk the truth table for the and gate
for I in 1 to 4 loop
wait for 100ps;
if (inputs = "00") then
assert (outAnd = '0') report "bad gate - stuck at 1" severity error;
elsif (inputs = "10") then
assert (outAnd = '0') report "bad gate - stuck at 1 " severity error;
elsif (inputs = "01") then
assert (outAnd = '0') report "bad gate- stuck at 1" severity error;
elsif (inputs = "11") then
assert (outAnd = '1') report "bad gate - stuck at 0" severity error ;
end if;
inputs <= inputs + '1';
end loop;
wait;
end process;
END;
|
library verilog;
use verilog.vl_types.all;
entity lab50 is
port(
reset : in vl_logic;
rb : in vl_logic;
clk_50m : in vl_logic;
clk_28m : in vl_logic;
win : out vl_logic;
lose : out vl_logic;
led1 : out vl_logic_vector(7 downto 0);
led2 : out vl_logic_vector(7 downto 0)
);
end lab50;
|
library verilog;
use verilog.vl_types.all;
entity lab50 is
port(
reset : in vl_logic;
rb : in vl_logic;
clk_50m : in vl_logic;
clk_28m : in vl_logic;
win : out vl_logic;
lose : out vl_logic;
led1 : out vl_logic_vector(7 downto 0);
led2 : out vl_logic_vector(7 downto 0)
);
end lab50;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity div00 is
port(
clkdiv: in std_logic ;
indiv: in std_logic_vector ( 3 downto 0 );
outdiv: inout std_logic );
end;
architecture div0 of div00 is
signal sdiv: std_logic_vector(11 downto 0);
begin
pdiv: process (clkdiv)
begin
if (clkdiv'event and clkdiv = '1') then
case indiv is
when "0000" =>
if (sdiv > "000001000000") then
outdiv <= not(outdiv);
sdiv <= (others => '0');
else
sdiv <= sdiv + 1;
end if;
when "0001" =>
if (sdiv > "000010000000") then
outdiv <= not(outdiv);
sdiv <= (others => '0');
else
sdiv <= sdiv + 1;
end if;
when "0011" =>
if (sdiv > "000100000000") then
outdiv <= not(outdiv);
sdiv <= (others => '0');
else
sdiv <= sdiv + 1;
end if;
when "0111" =>
if (sdiv > "001000000000") then
outdiv <= not(outdiv);
sdiv <= (others => '0');
else
sdiv <= sdiv + 1;
end if;
when "1111" =>
if (sdiv > "010000000000") then
outdiv <= not(outdiv);
sdiv <= (others => '0');
else
sdiv <= sdiv + 1;
end if;
when "1110" =>
if (sdiv > "100000000000") then
outdiv <= not(outdiv);
sdiv <= (others => '0');
else
sdiv <= sdiv + 1;
end if;
when others => null;
end case;
end if;
end process pdiv;
end div0;
|
----------------------------------------------------------------------
-- FsmPatGen
----------------------------------------------------------------------
-- (c) 2016 by Anton Mause
--
-- Blink some LEDs to show results of initialisation attempts.
--
-- Result :
-- -assignments at declaration time will not work
-- -Asynch Reset will work and come for free (no etra resources)
-- -Sync Reset will work too, but may cost extra LUT resources
--
-- SRAM FPGA may support initialisation at declaration.
-- Watch your step when migrating from SRAM to FLASH FPGAs
--
----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use IEEE.numeric_std.all;
----------------------------------------------------------------------
entity FsmPatGen is
port( OSC_CLK : in std_logic;
DEVRST_N : in std_logic;
PB1 : in std_logic;
PB2 : in std_logic;
LED0 : out std_logic;
LED1 : out std_logic;
LED2 : out std_logic;
LED3 : out std_logic;
LED4 : out std_logic;
LED5 : out std_logic;
LED6 : out std_logic;
LED7 : out std_logic;
UART_RXD : in std_logic;
UART_TXD : out std_logic );
end FsmPatGen;
architecture RTL of FsmPatGen is
----------------------------------------------------------------------
component brdLexSwx is
port ( o_lex, o_pbx : out std_logic );
end component;
component brdRstClk
port ( i_rst_n, i_clk : in std_logic;
o_rst_n, o_clk : out std_logic );
end component;
component myDffCnt
generic (N : Integer);
port ( i_rst_n, i_clk : in std_logic;
o_q : out std_logic_vector(N-1 downto 0) );
end component;
----------------------------------------------------------------------
-- Signal declarations
----------------------------------------------------------------------
signal s_clk, s_clk2, s_rst_n, s_lex, s_pbx : std_logic;
signal s_cnt : std_logic_vector(26 downto 0);
signal s_led : std_logic_vector(7 downto 0);
begin
----------------------------------------------------------------------
brdRstClk_0 : brdRstClk
port map(
i_rst_n => DEVRST_N,
i_clk => OSC_CLK,
o_rst_n => s_rst_n,
o_clk => s_clk );
brdLexSwx_0 : brdLexSwx
port map(
o_lex => s_lex,
o_pbx => s_pbx );
myDffCnt_0 : myDffCnt
generic map( N => s_cnt'high+1 )
port map(
i_rst_n => s_rst_n,
i_clk => s_clk,
o_q => s_cnt );
s_clk2 <= s_led(4);
LED6 <= s_clk2;
noReset : process(s_clk2, s_rst_n)
variable v_sft : std_logic_vector(25 downto 0) := "00001010100001011000011100";
begin
if (s_clk2'event and s_clk2 = '1') then
v_sft := v_sft(0) & v_sft(v_sft'length-1 downto 1);
end if;
LED0 <= v_sft(0) xor s_lex;
end process;
asyncReset : process(s_clk2, s_rst_n)
variable v_sft : std_logic_vector(25 downto 0);
begin
if (s_rst_n = '0') then
v_sft := "00001010100001011000011100";
elsif (s_clk2'event and s_clk2 = '1') then
v_sft := v_sft(0) & v_sft(v_sft'length-1 downto 1);
end if;
LED2 <= v_sft(0) xor s_lex;
end process;
process(s_clk2, s_rst_n)
variable v_cnt : unsigned(2 downto 0);
begin
if (s_rst_n = '0') then
v_cnt := to_unsigned(3,v_cnt'length);
elsif (s_clk2'event and s_clk2 = '1') then
if (v_cnt(2) = '1') then
v_cnt := to_unsigned(3,v_cnt'length);
else
v_cnt := v_cnt -1;
end if;
end if;
LED4 <= v_cnt(2) xor s_lex;
end process;
UART_TXD <= UART_RXD;
s_led <= s_cnt(s_cnt'high downto s_cnt'high-7);
--LED0 <= s_led(0);
--LED1 <= s_led(1);
--LED2 <= s_led(2);
--LED3 <= s_led(3);
--LED4 <= s_led(4);
--LED5 <= s_led(5);
--LED6 <= s_led(6) xor PB2;
--LED7 <= s_led(7) xor PB1;
LED5 <= PB2;
LED7 <= PB1;
end RTL; |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
package phasedet_comp is
component phasedet
Port ( ref : in STD_LOGIC;
vco : in STD_LOGIC;
mclk : in STD_LOGIC;
rst : in std_logic;
phase : out signed (15 downto 0));
end component;
end package;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity phasedet is
Port ( ref : in STD_LOGIC;
vco : in STD_LOGIC;
mclk : in STD_LOGIC;
rst : in std_logic;
phase : out signed (15 downto 0));
end phasedet;
architecture Behavioral of phasedet is
signal pre, pre_new, post, post_new : std_logic;
signal last, last_new, count, count_new : signed(15 downto 0);
signal synref, synvco : std_logic_vector(2 downto 0);
begin
phase <= last;
process(rst, mclk)
begin
if rst = '1' then
last <= (others => '0');
count <= (others => '0');
pre <= '0';
post <= '0';
synref <= (others => '0');
synvco <= (others => '0');
elsif rising_edge(mclk) then
last <= last_new;
count <= count_new;
pre <= pre_new;
post <= post_new;
synref <= synref(1 downto 0) & ref;
synvco <= synvco(1 downto 0) & vco;
end if;
end process;
process(synref, synvco, last, count, pre, post)
variable last_next, count_next : signed(15 downto 0);
variable pre_next, post_next : std_logic;
begin
last_next := last;
count_next := count;
pre_next := pre;
post_next := post;
if pre = '0' and post = '0' then
-- reference clock rising edge is first
if synref(2) = '0' and synref(1) = '1' then
if synvco(2) = '0' and synvco(1) = '1' then
last_next := (others => '0');
else
post_next := '1';
count_next := (others => '0');
end if;
-- VCO rising edge is first
elsif synvco(2) = '0' and synvco(1) = '1' then
if synref(2) = '0' and synref(1) = '1' then
last_next := (others => '0');
else
pre_next := '1';
count_next := (others => '0');
end if;
end if;
else
-- If waiting for VCO edge and get REF edge, reset the count
if post = '1' and synref(2) = '0' and synref(1) = '1' then
count_next := (others => '0');
-- If waiting for REF edge and get VCO edge, reset the count
elsif pre = '1' and synvco(2) = '0' and synvco(1) = '1' then
count_next := (others => '0');
-- If waiting for edge and get edge, store phase
elsif (post = '1' and synvco(2) = '0' and synvco(1) = '1') or (pre = '1' and synref(2) = '0' and synref(1) = '1') then
pre_next := '0';
post_next := '0';
last_next := count_next;
-- waiting for VCO edge, count up
elsif post = '1' then
count_next := count + "1";
-- waiting for REF edge, count down
elsif pre = '1' then
count_next := count - "1";
end if;
end if;
last_new <= last_next;
count_new <= count_next;
pre_new <= pre_next;
post_new <= post_next;
end process;
end Behavioral;
|
--------------------------------------------------------------------------------
-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version : 14.3
-- \ \ Application :
-- / / Filename : xil_10080_19
-- /___/ /\ Timestamp : 02/08/2013 16:21:11
-- \ \ / \
-- \___\/\___\
--
--Command:
--Design Name:
-- The Papilio Default Pinout device defines the pins for a Papilio board that does not have a MegaWing attached to it.
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
library UNISIM;
use UNISIM.Vcomponents.ALL;
library board;
use board.zpupkg.all;
use board.zpuinopkg.all;
use board.zpuino_config.all;
use board.zpu_config.all;
library zpuino;
use zpuino.pad.all;
use zpuino.papilio_pkg.all;
-- Unfortunately the Xilinx Schematic Editor does not support records, so we have to put all wishbone signals into one array.
-- This is a little cumbersome but is better then dealing with all the signals in the schematic editor.
-- This is what the original record base approach looked like:
--
-- type gpio_bus_in_type is record
-- gpio_i: std_logic_vector(48 downto 0);
-- gpio_spp_data: std_logic_vector(48 downto 0);
-- end record;
--
-- type gpio_bus_out_type is record
-- gpio_clk: std_logic;
-- gpio_o: std_logic_vector(48 downto 0);
-- gpio_t: std_logic_vector(48 downto 0);
-- gpio_spp_read: std_logic_vector(48 downto 0);
-- end record;
--
-- Turning them into an array looks like this:
--
-- gpio_bus_in : in std_logic_vector(97 downto 0);
--
-- gpio_bus_in(97 downto 49) <= gpio_i;
-- gpio_bus_in(48 downto 0) <= gpio_bus_in_record.gpio_spp_data;
--
-- gpio_bus_out : out std_logic_vector(146 downto 0);
--
-- gpio_o <= gpio_bus_out(146 downto 98);
-- gpio_t <= gpio_bus_out(97 downto 49);
-- gpio_bus_out_record.gpio_spp_read <= gpio_bus_out(48 downto 0);
entity Papilio_Default_Pinout is
port (
-- gpio_clk: in std_logic;
-- gpio_o: in std_logic_vector(48 downto 0);
-- gpio_t: in std_logic_vector(48 downto 0);
-- gpio_i: out std_logic_vector(48 downto 0);
--
-- gpio_spp_data: out std_logic_vector(48 downto 0);
-- gpio_spp_read: in std_logic_vector(48 downto 0);
gpio_bus_in : out std_logic_vector(97 downto 0);
gpio_bus_out : in std_logic_vector(147 downto 0);
WING_AH0 : inout std_logic;
WING_AH1 : inout std_logic;
WING_AH2 : inout std_logic;
WING_AH3 : inout std_logic;
WING_AH4 : inout std_logic;
WING_AH5 : inout std_logic;
WING_AH6 : inout std_logic;
WING_AH7 : inout std_logic;
WING_AL0 : inout std_logic;
WING_AL1 : inout std_logic;
WING_AL2 : inout std_logic;
WING_AL3 : inout std_logic;
WING_AL4 : inout std_logic;
WING_AL5 : inout std_logic;
WING_AL6 : inout std_logic;
WING_AL7 : inout std_logic;
WING_BH0 : inout std_logic;
WING_BH1 : inout std_logic;
WING_BH2 : inout std_logic;
WING_BH3 : inout std_logic;
WING_BH4 : inout std_logic;
WING_BH5 : inout std_logic;
WING_BH6 : inout std_logic;
WING_BH7 : inout std_logic;
WING_BL0 : inout std_logic;
WING_BL1 : inout std_logic;
WING_BL2 : inout std_logic;
WING_BL3 : inout std_logic;
WING_BL4 : inout std_logic;
WING_BL5 : inout std_logic;
WING_BL6 : inout std_logic;
WING_BL7 : inout std_logic;
WING_CH0 : inout std_logic;
WING_CH1 : inout std_logic;
WING_CH2 : inout std_logic;
WING_CH3 : inout std_logic;
WING_CH4 : inout std_logic;
WING_CH5 : inout std_logic;
WING_CH6 : inout std_logic;
WING_CH7 : inout std_logic;
WING_CL0 : inout std_logic;
WING_CL1 : inout std_logic;
WING_CL2 : inout std_logic;
WING_CL3 : inout std_logic;
WING_CL4 : inout std_logic;
WING_CL5 : inout std_logic;
WING_CL6 : inout std_logic;
WING_CL7 : inout std_logic
);
end Papilio_Default_Pinout;
architecture BEHAVIORAL of Papilio_Default_Pinout is
-- signal gpio_bus_out.gpio_o: std_logic_vector(zpuino_gpio_count-1 downto 0);
-- signal gpio_bus_out.gpio_t: std_logic_vector(zpuino_gpio_count-1 downto 0);
-- signal gpio_bus_in.gpio_i: std_logic_vector(zpuino_gpio_count-1 downto 0);
--
-- -- SPP signal is one more than GPIO count
-- signal gpio_bus_in.gpio_spp_data: std_logic_vector(zpuino_gpio_count-1 downto 0);
-- signal gpio_bus_out.gpio_spp_read: std_logic_vector(zpuino_gpio_count-1 downto 0);
--
-- constant spp_cap_in: std_logic_vector(zpuino_gpio_count-1 downto 0) :=
-- "0" &
-- "1111111111111111" &
-- "1111111111111111" &
-- "1111111111111111";
-- constant spp_cap_out: std_logic_vector(zpuino_gpio_count-1 downto 0) :=
-- "0" &
-- "1111111111111111" &
-- "1111111111111111" &
-- "1111111111111111";
-- signal gpio_bus_in_record : gpio_bus_in_type;
-- signal gpio_bus_out_record : gpio_bus_out_type;
signal gpio_o: std_logic_vector(48 downto 0);
signal gpio_t: std_logic_vector(48 downto 0);
signal gpio_i: std_logic_vector(48 downto 0);
signal gpio_spp_data: std_logic_vector(48 downto 0);
signal gpio_spp_read: std_logic_vector(48 downto 0);
signal gpio_clk: std_logic;
begin
--Unpack the signal array into a record so the modules code is easier to understand.
--gpio_bus_in(97 downto 49) <= gpio_spp_data;
--gpio_bus_in(48 downto 0) <= gpio_i;
gpio_clk <= gpio_bus_out(147);
gpio_o <= gpio_bus_out(146 downto 98);
gpio_t <= gpio_bus_out(97 downto 49);
gpio_spp_read <= gpio_bus_out(48 downto 0);
-- gpio_bus_in(97 downto 49) <= gpio_i;
-- gpio_bus_in(48 downto 0) <= gpio_bus_in_record.gpio_spp_data;
-- gpio_clk <= gpio_bus_out(147);
-- gpio_o <= gpio_bus_out(146 downto 98);
-- gpio_t <= gpio_bus_out(97 downto 49);
-- gpio_bus_out_record.gpio_spp_read <= gpio_bus_out(48 downto 0);
-- gpio_bus_in.gpio_inst: zpuino_gpio
-- generic map (
-- gpio_count => zpuino_gpio_count
-- )
-- port map (
-- gpio_bus_out.gpio_clk => gpio_bus_out.gpio_clk,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => wb_dat_o,
-- wb_dat_i => wb_dat_i,
-- wb_adr_i => wb_adr_i,
-- wb_we_i => wb_we_i,
-- wb_cyc_i => wb_cyc_i,
-- wb_stb_i => wb_stb_i,
-- wb_ack_o => wb_ack_o,
-- wb_inta_o => wb_inta_o,
--
-- spp_data => gpio_bus_in.gpio_spp_data,
-- spp_read => gpio_bus_out.gpio_spp_read,
--
-- gpio_bus_in.gpio_i => gpio_bus_in.gpio_i,
-- gpio_bus_out.gpio_t => gpio_bus_out.gpio_t,
-- gpio_bus_out.gpio_o => gpio_bus_out.gpio_o,
-- spp_cap_in => spp_cap_in,
-- spp_cap_out => spp_cap_out
-- );
pin00: IOPAD port map(I => gpio_o(0), O => gpio_bus_in(0), T => gpio_t(0), C => gpio_clk,PAD => WING_AL0 );
pin01: IOPAD port map(I => gpio_o(1), O => gpio_bus_in(1), T => gpio_t(1), C => gpio_clk,PAD => WING_AL1 );
pin02: IOPAD port map(I => gpio_o(2), O => gpio_bus_in(2), T => gpio_t(2), C => gpio_clk,PAD => WING_AL2 );
pin03: IOPAD port map(I => gpio_o(3), O => gpio_bus_in(3), T => gpio_t(3), C => gpio_clk,PAD => WING_AL3 );
pin04: IOPAD port map(I => gpio_o(4), O => gpio_bus_in(4), T => gpio_t(4), C => gpio_clk,PAD => WING_AL4 );
pin05: IOPAD port map(I => gpio_o(5), O => gpio_bus_in(5), T => gpio_t(5), C => gpio_clk,PAD => WING_AL5 );
pin06: IOPAD port map(I => gpio_o(6), O => gpio_bus_in(6), T => gpio_t(6), C => gpio_clk,PAD => WING_AL6 );
pin07: IOPAD port map(I => gpio_o(7), O => gpio_bus_in(7), T => gpio_t(7), C => gpio_clk,PAD => WING_AL7 );
pin08: IOPAD port map(I => gpio_o(8), O => gpio_bus_in(8), T => gpio_t(8), C => gpio_clk,PAD => WING_AH0 );
pin09: IOPAD port map(I => gpio_o(9), O => gpio_bus_in(9), T => gpio_t(9), C => gpio_clk,PAD => WING_AH1 );
pin10: IOPAD port map(I => gpio_o(10),O => gpio_bus_in(10),T => gpio_t(10),C => gpio_clk,PAD => WING_AH2 );
pin11: IOPAD port map(I => gpio_o(11),O => gpio_bus_in(11),T => gpio_t(11),C => gpio_clk,PAD => WING_AH3 );
pin12: IOPAD port map(I => gpio_o(12),O => gpio_bus_in(12),T => gpio_t(12),C => gpio_clk,PAD => WING_AH4 );
pin13: IOPAD port map(I => gpio_o(13),O => gpio_bus_in(13),T => gpio_t(13),C => gpio_clk,PAD => WING_AH5 );
pin14: IOPAD port map(I => gpio_o(14),O => gpio_bus_in(14),T => gpio_t(14),C => gpio_clk,PAD => WING_AH6 );
pin15: IOPAD port map(I => gpio_o(15),O => gpio_bus_in(15),T => gpio_t(15),C => gpio_clk,PAD => WING_AH7 );
pin16: IOPAD port map(I => gpio_o(16),O => gpio_bus_in(16),T => gpio_t(16),C => gpio_clk,PAD => WING_BL0 );
pin17: IOPAD port map(I => gpio_o(17),O => gpio_bus_in(17),T => gpio_t(17),C => gpio_clk,PAD => WING_BL1 );
pin18: IOPAD port map(I => gpio_o(18),O => gpio_bus_in(18),T => gpio_t(18),C => gpio_clk,PAD => WING_BL2 );
pin19: IOPAD port map(I => gpio_o(19),O => gpio_bus_in(19),T => gpio_t(19),C => gpio_clk,PAD => WING_BL3 );
pin20: IOPAD port map(I => gpio_o(20),O => gpio_bus_in(20),T => gpio_t(20),C => gpio_clk,PAD => WING_BL4 );
pin21: IOPAD port map(I => gpio_o(21),O => gpio_bus_in(21),T => gpio_t(21),C => gpio_clk,PAD => WING_BL5 );
pin22: IOPAD port map(I => gpio_o(22),O => gpio_bus_in(22),T => gpio_t(22),C => gpio_clk,PAD => WING_BL6 );
pin23: IOPAD port map(I => gpio_o(23),O => gpio_bus_in(23),T => gpio_t(23),C => gpio_clk,PAD => WING_BL7 );
pin24: IOPAD port map(I => gpio_o(24),O => gpio_bus_in(24),T => gpio_t(24),C => gpio_clk,PAD => WING_BH0 );
pin25: IOPAD port map(I => gpio_o(25),O => gpio_bus_in(25),T => gpio_t(25),C => gpio_clk,PAD => WING_BH1 );
pin26: IOPAD port map(I => gpio_o(26),O => gpio_bus_in(26),T => gpio_t(26),C => gpio_clk,PAD => WING_BH2 );
pin27: IOPAD port map(I => gpio_o(27),O => gpio_bus_in(27),T => gpio_t(27),C => gpio_clk,PAD => WING_BH3 );
pin28: IOPAD port map(I => gpio_o(28),O => gpio_bus_in(28),T => gpio_t(28),C => gpio_clk,PAD => WING_BH4 );
pin29: IOPAD port map(I => gpio_o(29),O => gpio_bus_in(29),T => gpio_t(29),C => gpio_clk,PAD => WING_BH5 );
pin30: IOPAD port map(I => gpio_o(30),O => gpio_bus_in(30),T => gpio_t(30),C => gpio_clk,PAD => WING_BH6 );
pin31: IOPAD port map(I => gpio_o(31),O => gpio_bus_in(31),T => gpio_t(31),C => gpio_clk,PAD => WING_BH7 );
pin32: IOPAD port map(I => gpio_o(32),O => gpio_bus_in(32),T => gpio_t(32),C => gpio_clk,PAD => WING_CL0 );
pin33: IOPAD port map(I => gpio_o(33),O => gpio_bus_in(33),T => gpio_t(33),C => gpio_clk,PAD => WING_CL1 );
pin34: IOPAD port map(I => gpio_o(34),O => gpio_bus_in(34),T => gpio_t(34),C => gpio_clk,PAD => WING_CL2 );
pin35: IOPAD port map(I => gpio_o(35),O => gpio_bus_in(35),T => gpio_t(35),C => gpio_clk,PAD => WING_CL3 );
pin36: IOPAD port map(I => gpio_o(36),O => gpio_bus_in(36),T => gpio_t(36),C => gpio_clk,PAD => WING_CL4 );
pin37: IOPAD port map(I => gpio_o(37),O => gpio_bus_in(37),T => gpio_t(37),C => gpio_clk,PAD => WING_CL5 );
pin38: IOPAD port map(I => gpio_o(38),O => gpio_bus_in(38),T => gpio_t(38),C => gpio_clk,PAD => WING_CL6 );
pin39: IOPAD port map(I => gpio_o(39),O => gpio_bus_in(39),T => gpio_t(39),C => gpio_clk,PAD => WING_CL7 );
pin40: IOPAD port map(I => gpio_o(40),O => gpio_bus_in(40),T => gpio_t(40),C => gpio_clk,PAD => WING_CH0 );
pin41: IOPAD port map(I => gpio_o(41),O => gpio_bus_in(41),T => gpio_t(41),C => gpio_clk,PAD => WING_CH1 );
pin42: IOPAD port map(I => gpio_o(42),O => gpio_bus_in(42),T => gpio_t(42),C => gpio_clk,PAD => WING_CH2 );
pin43: IOPAD port map(I => gpio_o(43),O => gpio_bus_in(43),T => gpio_t(43),C => gpio_clk,PAD => WING_CH3 );
pin44: IOPAD port map(I => gpio_o(44),O => gpio_bus_in(44),T => gpio_t(44),C => gpio_clk,PAD => WING_CH4 );
pin45: IOPAD port map(I => gpio_o(45),O => gpio_bus_in(45),T => gpio_t(45),C => gpio_clk,PAD => WING_CH5 );
pin46: IOPAD port map(I => gpio_o(46),O => gpio_bus_in(46),T => gpio_t(46),C => gpio_clk,PAD => WING_CH6 );
pin47: IOPAD port map(I => gpio_o(47),O => gpio_bus_in(47),T => gpio_t(47),C => gpio_clk,PAD => WING_CH7 );
-- ospics: OPAD port map ( I => gpio_bus_out.gpio_o(48), PAD => SPI_CS );
process(gpio_spp_read)
-- sigmadelta_spp_data,
-- timers_pwm,
-- spi2_mosi,spi2_sck)
begin
--gpio_spp_data <= (others => DontCareValue);
gpio_bus_in(97 downto 49) <= (others => DontCareValue);
-- gpio_bus_in.gpio_spp_data(0) <= platform_audio_sd; -- PPS0 : SIGMADELTA DATA
-- gpio_bus_in.gpio_spp_data(1) <= timers_pwm(0); -- PPS1 : TIMER0
-- gpio_bus_in.gpio_spp_data(2) <= timers_pwm(1); -- PPS2 : TIMER1
-- gpio_bus_in.gpio_spp_data(3) <= spi2_mosi; -- PPS3 : USPI MOSI
-- gpio_bus_in.gpio_spp_data(4) <= spi2_sck; -- PPS4 : USPI SCK
-- gpio_bus_in.gpio_spp_data(5) <= platform_audio_sd; -- PPS5 : SIGMADELTA1 DATA
-- gpio_bus_in.gpio_spp_data(6) <= uart2_tx; -- PPS6 : UART2 DATA
-- gpio_bus_in.gpio_spp_data(8) <= platform_audio_sd;
-- spi2_miso <= gpio_bus_out_record.gpio_spp_read(0); -- PPS0 : USPI MISO
-- uart2_rx <= gpio_bus_out_record.gpio_spp_read(1); -- PPS0 : USPI MISO
end process;
end BEHAVIORAL;
|
--------------------------------------------------------------------------------
-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version : 14.3
-- \ \ Application :
-- / / Filename : xil_10080_19
-- /___/ /\ Timestamp : 02/08/2013 16:21:11
-- \ \ / \
-- \___\/\___\
--
--Command:
--Design Name:
-- The Papilio Default Pinout device defines the pins for a Papilio board that does not have a MegaWing attached to it.
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
library UNISIM;
use UNISIM.Vcomponents.ALL;
library board;
use board.zpupkg.all;
use board.zpuinopkg.all;
use board.zpuino_config.all;
use board.zpu_config.all;
library zpuino;
use zpuino.pad.all;
use zpuino.papilio_pkg.all;
-- Unfortunately the Xilinx Schematic Editor does not support records, so we have to put all wishbone signals into one array.
-- This is a little cumbersome but is better then dealing with all the signals in the schematic editor.
-- This is what the original record base approach looked like:
--
-- type gpio_bus_in_type is record
-- gpio_i: std_logic_vector(48 downto 0);
-- gpio_spp_data: std_logic_vector(48 downto 0);
-- end record;
--
-- type gpio_bus_out_type is record
-- gpio_clk: std_logic;
-- gpio_o: std_logic_vector(48 downto 0);
-- gpio_t: std_logic_vector(48 downto 0);
-- gpio_spp_read: std_logic_vector(48 downto 0);
-- end record;
--
-- Turning them into an array looks like this:
--
-- gpio_bus_in : in std_logic_vector(97 downto 0);
--
-- gpio_bus_in(97 downto 49) <= gpio_i;
-- gpio_bus_in(48 downto 0) <= gpio_bus_in_record.gpio_spp_data;
--
-- gpio_bus_out : out std_logic_vector(146 downto 0);
--
-- gpio_o <= gpio_bus_out(146 downto 98);
-- gpio_t <= gpio_bus_out(97 downto 49);
-- gpio_bus_out_record.gpio_spp_read <= gpio_bus_out(48 downto 0);
entity Papilio_Default_Pinout is
port (
-- gpio_clk: in std_logic;
-- gpio_o: in std_logic_vector(48 downto 0);
-- gpio_t: in std_logic_vector(48 downto 0);
-- gpio_i: out std_logic_vector(48 downto 0);
--
-- gpio_spp_data: out std_logic_vector(48 downto 0);
-- gpio_spp_read: in std_logic_vector(48 downto 0);
gpio_bus_in : out std_logic_vector(97 downto 0);
gpio_bus_out : in std_logic_vector(147 downto 0);
WING_AH0 : inout std_logic;
WING_AH1 : inout std_logic;
WING_AH2 : inout std_logic;
WING_AH3 : inout std_logic;
WING_AH4 : inout std_logic;
WING_AH5 : inout std_logic;
WING_AH6 : inout std_logic;
WING_AH7 : inout std_logic;
WING_AL0 : inout std_logic;
WING_AL1 : inout std_logic;
WING_AL2 : inout std_logic;
WING_AL3 : inout std_logic;
WING_AL4 : inout std_logic;
WING_AL5 : inout std_logic;
WING_AL6 : inout std_logic;
WING_AL7 : inout std_logic;
WING_BH0 : inout std_logic;
WING_BH1 : inout std_logic;
WING_BH2 : inout std_logic;
WING_BH3 : inout std_logic;
WING_BH4 : inout std_logic;
WING_BH5 : inout std_logic;
WING_BH6 : inout std_logic;
WING_BH7 : inout std_logic;
WING_BL0 : inout std_logic;
WING_BL1 : inout std_logic;
WING_BL2 : inout std_logic;
WING_BL3 : inout std_logic;
WING_BL4 : inout std_logic;
WING_BL5 : inout std_logic;
WING_BL6 : inout std_logic;
WING_BL7 : inout std_logic;
WING_CH0 : inout std_logic;
WING_CH1 : inout std_logic;
WING_CH2 : inout std_logic;
WING_CH3 : inout std_logic;
WING_CH4 : inout std_logic;
WING_CH5 : inout std_logic;
WING_CH6 : inout std_logic;
WING_CH7 : inout std_logic;
WING_CL0 : inout std_logic;
WING_CL1 : inout std_logic;
WING_CL2 : inout std_logic;
WING_CL3 : inout std_logic;
WING_CL4 : inout std_logic;
WING_CL5 : inout std_logic;
WING_CL6 : inout std_logic;
WING_CL7 : inout std_logic
);
end Papilio_Default_Pinout;
architecture BEHAVIORAL of Papilio_Default_Pinout is
-- signal gpio_bus_out.gpio_o: std_logic_vector(zpuino_gpio_count-1 downto 0);
-- signal gpio_bus_out.gpio_t: std_logic_vector(zpuino_gpio_count-1 downto 0);
-- signal gpio_bus_in.gpio_i: std_logic_vector(zpuino_gpio_count-1 downto 0);
--
-- -- SPP signal is one more than GPIO count
-- signal gpio_bus_in.gpio_spp_data: std_logic_vector(zpuino_gpio_count-1 downto 0);
-- signal gpio_bus_out.gpio_spp_read: std_logic_vector(zpuino_gpio_count-1 downto 0);
--
-- constant spp_cap_in: std_logic_vector(zpuino_gpio_count-1 downto 0) :=
-- "0" &
-- "1111111111111111" &
-- "1111111111111111" &
-- "1111111111111111";
-- constant spp_cap_out: std_logic_vector(zpuino_gpio_count-1 downto 0) :=
-- "0" &
-- "1111111111111111" &
-- "1111111111111111" &
-- "1111111111111111";
-- signal gpio_bus_in_record : gpio_bus_in_type;
-- signal gpio_bus_out_record : gpio_bus_out_type;
signal gpio_o: std_logic_vector(48 downto 0);
signal gpio_t: std_logic_vector(48 downto 0);
signal gpio_i: std_logic_vector(48 downto 0);
signal gpio_spp_data: std_logic_vector(48 downto 0);
signal gpio_spp_read: std_logic_vector(48 downto 0);
signal gpio_clk: std_logic;
begin
--Unpack the signal array into a record so the modules code is easier to understand.
--gpio_bus_in(97 downto 49) <= gpio_spp_data;
--gpio_bus_in(48 downto 0) <= gpio_i;
gpio_clk <= gpio_bus_out(147);
gpio_o <= gpio_bus_out(146 downto 98);
gpio_t <= gpio_bus_out(97 downto 49);
gpio_spp_read <= gpio_bus_out(48 downto 0);
-- gpio_bus_in(97 downto 49) <= gpio_i;
-- gpio_bus_in(48 downto 0) <= gpio_bus_in_record.gpio_spp_data;
-- gpio_clk <= gpio_bus_out(147);
-- gpio_o <= gpio_bus_out(146 downto 98);
-- gpio_t <= gpio_bus_out(97 downto 49);
-- gpio_bus_out_record.gpio_spp_read <= gpio_bus_out(48 downto 0);
-- gpio_bus_in.gpio_inst: zpuino_gpio
-- generic map (
-- gpio_count => zpuino_gpio_count
-- )
-- port map (
-- gpio_bus_out.gpio_clk => gpio_bus_out.gpio_clk,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => wb_dat_o,
-- wb_dat_i => wb_dat_i,
-- wb_adr_i => wb_adr_i,
-- wb_we_i => wb_we_i,
-- wb_cyc_i => wb_cyc_i,
-- wb_stb_i => wb_stb_i,
-- wb_ack_o => wb_ack_o,
-- wb_inta_o => wb_inta_o,
--
-- spp_data => gpio_bus_in.gpio_spp_data,
-- spp_read => gpio_bus_out.gpio_spp_read,
--
-- gpio_bus_in.gpio_i => gpio_bus_in.gpio_i,
-- gpio_bus_out.gpio_t => gpio_bus_out.gpio_t,
-- gpio_bus_out.gpio_o => gpio_bus_out.gpio_o,
-- spp_cap_in => spp_cap_in,
-- spp_cap_out => spp_cap_out
-- );
pin00: IOPAD port map(I => gpio_o(0), O => gpio_bus_in(0), T => gpio_t(0), C => gpio_clk,PAD => WING_AL0 );
pin01: IOPAD port map(I => gpio_o(1), O => gpio_bus_in(1), T => gpio_t(1), C => gpio_clk,PAD => WING_AL1 );
pin02: IOPAD port map(I => gpio_o(2), O => gpio_bus_in(2), T => gpio_t(2), C => gpio_clk,PAD => WING_AL2 );
pin03: IOPAD port map(I => gpio_o(3), O => gpio_bus_in(3), T => gpio_t(3), C => gpio_clk,PAD => WING_AL3 );
pin04: IOPAD port map(I => gpio_o(4), O => gpio_bus_in(4), T => gpio_t(4), C => gpio_clk,PAD => WING_AL4 );
pin05: IOPAD port map(I => gpio_o(5), O => gpio_bus_in(5), T => gpio_t(5), C => gpio_clk,PAD => WING_AL5 );
pin06: IOPAD port map(I => gpio_o(6), O => gpio_bus_in(6), T => gpio_t(6), C => gpio_clk,PAD => WING_AL6 );
pin07: IOPAD port map(I => gpio_o(7), O => gpio_bus_in(7), T => gpio_t(7), C => gpio_clk,PAD => WING_AL7 );
pin08: IOPAD port map(I => gpio_o(8), O => gpio_bus_in(8), T => gpio_t(8), C => gpio_clk,PAD => WING_AH0 );
pin09: IOPAD port map(I => gpio_o(9), O => gpio_bus_in(9), T => gpio_t(9), C => gpio_clk,PAD => WING_AH1 );
pin10: IOPAD port map(I => gpio_o(10),O => gpio_bus_in(10),T => gpio_t(10),C => gpio_clk,PAD => WING_AH2 );
pin11: IOPAD port map(I => gpio_o(11),O => gpio_bus_in(11),T => gpio_t(11),C => gpio_clk,PAD => WING_AH3 );
pin12: IOPAD port map(I => gpio_o(12),O => gpio_bus_in(12),T => gpio_t(12),C => gpio_clk,PAD => WING_AH4 );
pin13: IOPAD port map(I => gpio_o(13),O => gpio_bus_in(13),T => gpio_t(13),C => gpio_clk,PAD => WING_AH5 );
pin14: IOPAD port map(I => gpio_o(14),O => gpio_bus_in(14),T => gpio_t(14),C => gpio_clk,PAD => WING_AH6 );
pin15: IOPAD port map(I => gpio_o(15),O => gpio_bus_in(15),T => gpio_t(15),C => gpio_clk,PAD => WING_AH7 );
pin16: IOPAD port map(I => gpio_o(16),O => gpio_bus_in(16),T => gpio_t(16),C => gpio_clk,PAD => WING_BL0 );
pin17: IOPAD port map(I => gpio_o(17),O => gpio_bus_in(17),T => gpio_t(17),C => gpio_clk,PAD => WING_BL1 );
pin18: IOPAD port map(I => gpio_o(18),O => gpio_bus_in(18),T => gpio_t(18),C => gpio_clk,PAD => WING_BL2 );
pin19: IOPAD port map(I => gpio_o(19),O => gpio_bus_in(19),T => gpio_t(19),C => gpio_clk,PAD => WING_BL3 );
pin20: IOPAD port map(I => gpio_o(20),O => gpio_bus_in(20),T => gpio_t(20),C => gpio_clk,PAD => WING_BL4 );
pin21: IOPAD port map(I => gpio_o(21),O => gpio_bus_in(21),T => gpio_t(21),C => gpio_clk,PAD => WING_BL5 );
pin22: IOPAD port map(I => gpio_o(22),O => gpio_bus_in(22),T => gpio_t(22),C => gpio_clk,PAD => WING_BL6 );
pin23: IOPAD port map(I => gpio_o(23),O => gpio_bus_in(23),T => gpio_t(23),C => gpio_clk,PAD => WING_BL7 );
pin24: IOPAD port map(I => gpio_o(24),O => gpio_bus_in(24),T => gpio_t(24),C => gpio_clk,PAD => WING_BH0 );
pin25: IOPAD port map(I => gpio_o(25),O => gpio_bus_in(25),T => gpio_t(25),C => gpio_clk,PAD => WING_BH1 );
pin26: IOPAD port map(I => gpio_o(26),O => gpio_bus_in(26),T => gpio_t(26),C => gpio_clk,PAD => WING_BH2 );
pin27: IOPAD port map(I => gpio_o(27),O => gpio_bus_in(27),T => gpio_t(27),C => gpio_clk,PAD => WING_BH3 );
pin28: IOPAD port map(I => gpio_o(28),O => gpio_bus_in(28),T => gpio_t(28),C => gpio_clk,PAD => WING_BH4 );
pin29: IOPAD port map(I => gpio_o(29),O => gpio_bus_in(29),T => gpio_t(29),C => gpio_clk,PAD => WING_BH5 );
pin30: IOPAD port map(I => gpio_o(30),O => gpio_bus_in(30),T => gpio_t(30),C => gpio_clk,PAD => WING_BH6 );
pin31: IOPAD port map(I => gpio_o(31),O => gpio_bus_in(31),T => gpio_t(31),C => gpio_clk,PAD => WING_BH7 );
pin32: IOPAD port map(I => gpio_o(32),O => gpio_bus_in(32),T => gpio_t(32),C => gpio_clk,PAD => WING_CL0 );
pin33: IOPAD port map(I => gpio_o(33),O => gpio_bus_in(33),T => gpio_t(33),C => gpio_clk,PAD => WING_CL1 );
pin34: IOPAD port map(I => gpio_o(34),O => gpio_bus_in(34),T => gpio_t(34),C => gpio_clk,PAD => WING_CL2 );
pin35: IOPAD port map(I => gpio_o(35),O => gpio_bus_in(35),T => gpio_t(35),C => gpio_clk,PAD => WING_CL3 );
pin36: IOPAD port map(I => gpio_o(36),O => gpio_bus_in(36),T => gpio_t(36),C => gpio_clk,PAD => WING_CL4 );
pin37: IOPAD port map(I => gpio_o(37),O => gpio_bus_in(37),T => gpio_t(37),C => gpio_clk,PAD => WING_CL5 );
pin38: IOPAD port map(I => gpio_o(38),O => gpio_bus_in(38),T => gpio_t(38),C => gpio_clk,PAD => WING_CL6 );
pin39: IOPAD port map(I => gpio_o(39),O => gpio_bus_in(39),T => gpio_t(39),C => gpio_clk,PAD => WING_CL7 );
pin40: IOPAD port map(I => gpio_o(40),O => gpio_bus_in(40),T => gpio_t(40),C => gpio_clk,PAD => WING_CH0 );
pin41: IOPAD port map(I => gpio_o(41),O => gpio_bus_in(41),T => gpio_t(41),C => gpio_clk,PAD => WING_CH1 );
pin42: IOPAD port map(I => gpio_o(42),O => gpio_bus_in(42),T => gpio_t(42),C => gpio_clk,PAD => WING_CH2 );
pin43: IOPAD port map(I => gpio_o(43),O => gpio_bus_in(43),T => gpio_t(43),C => gpio_clk,PAD => WING_CH3 );
pin44: IOPAD port map(I => gpio_o(44),O => gpio_bus_in(44),T => gpio_t(44),C => gpio_clk,PAD => WING_CH4 );
pin45: IOPAD port map(I => gpio_o(45),O => gpio_bus_in(45),T => gpio_t(45),C => gpio_clk,PAD => WING_CH5 );
pin46: IOPAD port map(I => gpio_o(46),O => gpio_bus_in(46),T => gpio_t(46),C => gpio_clk,PAD => WING_CH6 );
pin47: IOPAD port map(I => gpio_o(47),O => gpio_bus_in(47),T => gpio_t(47),C => gpio_clk,PAD => WING_CH7 );
-- ospics: OPAD port map ( I => gpio_bus_out.gpio_o(48), PAD => SPI_CS );
process(gpio_spp_read)
-- sigmadelta_spp_data,
-- timers_pwm,
-- spi2_mosi,spi2_sck)
begin
--gpio_spp_data <= (others => DontCareValue);
gpio_bus_in(97 downto 49) <= (others => DontCareValue);
-- gpio_bus_in.gpio_spp_data(0) <= platform_audio_sd; -- PPS0 : SIGMADELTA DATA
-- gpio_bus_in.gpio_spp_data(1) <= timers_pwm(0); -- PPS1 : TIMER0
-- gpio_bus_in.gpio_spp_data(2) <= timers_pwm(1); -- PPS2 : TIMER1
-- gpio_bus_in.gpio_spp_data(3) <= spi2_mosi; -- PPS3 : USPI MOSI
-- gpio_bus_in.gpio_spp_data(4) <= spi2_sck; -- PPS4 : USPI SCK
-- gpio_bus_in.gpio_spp_data(5) <= platform_audio_sd; -- PPS5 : SIGMADELTA1 DATA
-- gpio_bus_in.gpio_spp_data(6) <= uart2_tx; -- PPS6 : UART2 DATA
-- gpio_bus_in.gpio_spp_data(8) <= platform_audio_sd;
-- spi2_miso <= gpio_bus_out_record.gpio_spp_read(0); -- PPS0 : USPI MISO
-- uart2_rx <= gpio_bus_out_record.gpio_spp_read(1); -- PPS0 : USPI MISO
end process;
end BEHAVIORAL;
|
--------------------------------------------------------------------------------
-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version : 14.3
-- \ \ Application :
-- / / Filename : xil_10080_19
-- /___/ /\ Timestamp : 02/08/2013 16:21:11
-- \ \ / \
-- \___\/\___\
--
--Command:
--Design Name:
-- The Papilio Default Pinout device defines the pins for a Papilio board that does not have a MegaWing attached to it.
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
library UNISIM;
use UNISIM.Vcomponents.ALL;
library board;
use board.zpupkg.all;
use board.zpuinopkg.all;
use board.zpuino_config.all;
use board.zpu_config.all;
library zpuino;
use zpuino.pad.all;
use zpuino.papilio_pkg.all;
-- Unfortunately the Xilinx Schematic Editor does not support records, so we have to put all wishbone signals into one array.
-- This is a little cumbersome but is better then dealing with all the signals in the schematic editor.
-- This is what the original record base approach looked like:
--
-- type gpio_bus_in_type is record
-- gpio_i: std_logic_vector(48 downto 0);
-- gpio_spp_data: std_logic_vector(48 downto 0);
-- end record;
--
-- type gpio_bus_out_type is record
-- gpio_clk: std_logic;
-- gpio_o: std_logic_vector(48 downto 0);
-- gpio_t: std_logic_vector(48 downto 0);
-- gpio_spp_read: std_logic_vector(48 downto 0);
-- end record;
--
-- Turning them into an array looks like this:
--
-- gpio_bus_in : in std_logic_vector(97 downto 0);
--
-- gpio_bus_in(97 downto 49) <= gpio_i;
-- gpio_bus_in(48 downto 0) <= gpio_bus_in_record.gpio_spp_data;
--
-- gpio_bus_out : out std_logic_vector(146 downto 0);
--
-- gpio_o <= gpio_bus_out(146 downto 98);
-- gpio_t <= gpio_bus_out(97 downto 49);
-- gpio_bus_out_record.gpio_spp_read <= gpio_bus_out(48 downto 0);
entity Papilio_Default_Pinout is
port (
-- gpio_clk: in std_logic;
-- gpio_o: in std_logic_vector(48 downto 0);
-- gpio_t: in std_logic_vector(48 downto 0);
-- gpio_i: out std_logic_vector(48 downto 0);
--
-- gpio_spp_data: out std_logic_vector(48 downto 0);
-- gpio_spp_read: in std_logic_vector(48 downto 0);
gpio_bus_in : out std_logic_vector(97 downto 0);
gpio_bus_out : in std_logic_vector(147 downto 0);
WING_AH0 : inout std_logic;
WING_AH1 : inout std_logic;
WING_AH2 : inout std_logic;
WING_AH3 : inout std_logic;
WING_AH4 : inout std_logic;
WING_AH5 : inout std_logic;
WING_AH6 : inout std_logic;
WING_AH7 : inout std_logic;
WING_AL0 : inout std_logic;
WING_AL1 : inout std_logic;
WING_AL2 : inout std_logic;
WING_AL3 : inout std_logic;
WING_AL4 : inout std_logic;
WING_AL5 : inout std_logic;
WING_AL6 : inout std_logic;
WING_AL7 : inout std_logic;
WING_BH0 : inout std_logic;
WING_BH1 : inout std_logic;
WING_BH2 : inout std_logic;
WING_BH3 : inout std_logic;
WING_BH4 : inout std_logic;
WING_BH5 : inout std_logic;
WING_BH6 : inout std_logic;
WING_BH7 : inout std_logic;
WING_BL0 : inout std_logic;
WING_BL1 : inout std_logic;
WING_BL2 : inout std_logic;
WING_BL3 : inout std_logic;
WING_BL4 : inout std_logic;
WING_BL5 : inout std_logic;
WING_BL6 : inout std_logic;
WING_BL7 : inout std_logic;
WING_CH0 : inout std_logic;
WING_CH1 : inout std_logic;
WING_CH2 : inout std_logic;
WING_CH3 : inout std_logic;
WING_CH4 : inout std_logic;
WING_CH5 : inout std_logic;
WING_CH6 : inout std_logic;
WING_CH7 : inout std_logic;
WING_CL0 : inout std_logic;
WING_CL1 : inout std_logic;
WING_CL2 : inout std_logic;
WING_CL3 : inout std_logic;
WING_CL4 : inout std_logic;
WING_CL5 : inout std_logic;
WING_CL6 : inout std_logic;
WING_CL7 : inout std_logic
);
end Papilio_Default_Pinout;
architecture BEHAVIORAL of Papilio_Default_Pinout is
-- signal gpio_bus_out.gpio_o: std_logic_vector(zpuino_gpio_count-1 downto 0);
-- signal gpio_bus_out.gpio_t: std_logic_vector(zpuino_gpio_count-1 downto 0);
-- signal gpio_bus_in.gpio_i: std_logic_vector(zpuino_gpio_count-1 downto 0);
--
-- -- SPP signal is one more than GPIO count
-- signal gpio_bus_in.gpio_spp_data: std_logic_vector(zpuino_gpio_count-1 downto 0);
-- signal gpio_bus_out.gpio_spp_read: std_logic_vector(zpuino_gpio_count-1 downto 0);
--
-- constant spp_cap_in: std_logic_vector(zpuino_gpio_count-1 downto 0) :=
-- "0" &
-- "1111111111111111" &
-- "1111111111111111" &
-- "1111111111111111";
-- constant spp_cap_out: std_logic_vector(zpuino_gpio_count-1 downto 0) :=
-- "0" &
-- "1111111111111111" &
-- "1111111111111111" &
-- "1111111111111111";
-- signal gpio_bus_in_record : gpio_bus_in_type;
-- signal gpio_bus_out_record : gpio_bus_out_type;
signal gpio_o: std_logic_vector(48 downto 0);
signal gpio_t: std_logic_vector(48 downto 0);
signal gpio_i: std_logic_vector(48 downto 0);
signal gpio_spp_data: std_logic_vector(48 downto 0);
signal gpio_spp_read: std_logic_vector(48 downto 0);
signal gpio_clk: std_logic;
begin
--Unpack the signal array into a record so the modules code is easier to understand.
--gpio_bus_in(97 downto 49) <= gpio_spp_data;
--gpio_bus_in(48 downto 0) <= gpio_i;
gpio_clk <= gpio_bus_out(147);
gpio_o <= gpio_bus_out(146 downto 98);
gpio_t <= gpio_bus_out(97 downto 49);
gpio_spp_read <= gpio_bus_out(48 downto 0);
-- gpio_bus_in(97 downto 49) <= gpio_i;
-- gpio_bus_in(48 downto 0) <= gpio_bus_in_record.gpio_spp_data;
-- gpio_clk <= gpio_bus_out(147);
-- gpio_o <= gpio_bus_out(146 downto 98);
-- gpio_t <= gpio_bus_out(97 downto 49);
-- gpio_bus_out_record.gpio_spp_read <= gpio_bus_out(48 downto 0);
-- gpio_bus_in.gpio_inst: zpuino_gpio
-- generic map (
-- gpio_count => zpuino_gpio_count
-- )
-- port map (
-- gpio_bus_out.gpio_clk => gpio_bus_out.gpio_clk,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => wb_dat_o,
-- wb_dat_i => wb_dat_i,
-- wb_adr_i => wb_adr_i,
-- wb_we_i => wb_we_i,
-- wb_cyc_i => wb_cyc_i,
-- wb_stb_i => wb_stb_i,
-- wb_ack_o => wb_ack_o,
-- wb_inta_o => wb_inta_o,
--
-- spp_data => gpio_bus_in.gpio_spp_data,
-- spp_read => gpio_bus_out.gpio_spp_read,
--
-- gpio_bus_in.gpio_i => gpio_bus_in.gpio_i,
-- gpio_bus_out.gpio_t => gpio_bus_out.gpio_t,
-- gpio_bus_out.gpio_o => gpio_bus_out.gpio_o,
-- spp_cap_in => spp_cap_in,
-- spp_cap_out => spp_cap_out
-- );
pin00: IOPAD port map(I => gpio_o(0), O => gpio_bus_in(0), T => gpio_t(0), C => gpio_clk,PAD => WING_AL0 );
pin01: IOPAD port map(I => gpio_o(1), O => gpio_bus_in(1), T => gpio_t(1), C => gpio_clk,PAD => WING_AL1 );
pin02: IOPAD port map(I => gpio_o(2), O => gpio_bus_in(2), T => gpio_t(2), C => gpio_clk,PAD => WING_AL2 );
pin03: IOPAD port map(I => gpio_o(3), O => gpio_bus_in(3), T => gpio_t(3), C => gpio_clk,PAD => WING_AL3 );
pin04: IOPAD port map(I => gpio_o(4), O => gpio_bus_in(4), T => gpio_t(4), C => gpio_clk,PAD => WING_AL4 );
pin05: IOPAD port map(I => gpio_o(5), O => gpio_bus_in(5), T => gpio_t(5), C => gpio_clk,PAD => WING_AL5 );
pin06: IOPAD port map(I => gpio_o(6), O => gpio_bus_in(6), T => gpio_t(6), C => gpio_clk,PAD => WING_AL6 );
pin07: IOPAD port map(I => gpio_o(7), O => gpio_bus_in(7), T => gpio_t(7), C => gpio_clk,PAD => WING_AL7 );
pin08: IOPAD port map(I => gpio_o(8), O => gpio_bus_in(8), T => gpio_t(8), C => gpio_clk,PAD => WING_AH0 );
pin09: IOPAD port map(I => gpio_o(9), O => gpio_bus_in(9), T => gpio_t(9), C => gpio_clk,PAD => WING_AH1 );
pin10: IOPAD port map(I => gpio_o(10),O => gpio_bus_in(10),T => gpio_t(10),C => gpio_clk,PAD => WING_AH2 );
pin11: IOPAD port map(I => gpio_o(11),O => gpio_bus_in(11),T => gpio_t(11),C => gpio_clk,PAD => WING_AH3 );
pin12: IOPAD port map(I => gpio_o(12),O => gpio_bus_in(12),T => gpio_t(12),C => gpio_clk,PAD => WING_AH4 );
pin13: IOPAD port map(I => gpio_o(13),O => gpio_bus_in(13),T => gpio_t(13),C => gpio_clk,PAD => WING_AH5 );
pin14: IOPAD port map(I => gpio_o(14),O => gpio_bus_in(14),T => gpio_t(14),C => gpio_clk,PAD => WING_AH6 );
pin15: IOPAD port map(I => gpio_o(15),O => gpio_bus_in(15),T => gpio_t(15),C => gpio_clk,PAD => WING_AH7 );
pin16: IOPAD port map(I => gpio_o(16),O => gpio_bus_in(16),T => gpio_t(16),C => gpio_clk,PAD => WING_BL0 );
pin17: IOPAD port map(I => gpio_o(17),O => gpio_bus_in(17),T => gpio_t(17),C => gpio_clk,PAD => WING_BL1 );
pin18: IOPAD port map(I => gpio_o(18),O => gpio_bus_in(18),T => gpio_t(18),C => gpio_clk,PAD => WING_BL2 );
pin19: IOPAD port map(I => gpio_o(19),O => gpio_bus_in(19),T => gpio_t(19),C => gpio_clk,PAD => WING_BL3 );
pin20: IOPAD port map(I => gpio_o(20),O => gpio_bus_in(20),T => gpio_t(20),C => gpio_clk,PAD => WING_BL4 );
pin21: IOPAD port map(I => gpio_o(21),O => gpio_bus_in(21),T => gpio_t(21),C => gpio_clk,PAD => WING_BL5 );
pin22: IOPAD port map(I => gpio_o(22),O => gpio_bus_in(22),T => gpio_t(22),C => gpio_clk,PAD => WING_BL6 );
pin23: IOPAD port map(I => gpio_o(23),O => gpio_bus_in(23),T => gpio_t(23),C => gpio_clk,PAD => WING_BL7 );
pin24: IOPAD port map(I => gpio_o(24),O => gpio_bus_in(24),T => gpio_t(24),C => gpio_clk,PAD => WING_BH0 );
pin25: IOPAD port map(I => gpio_o(25),O => gpio_bus_in(25),T => gpio_t(25),C => gpio_clk,PAD => WING_BH1 );
pin26: IOPAD port map(I => gpio_o(26),O => gpio_bus_in(26),T => gpio_t(26),C => gpio_clk,PAD => WING_BH2 );
pin27: IOPAD port map(I => gpio_o(27),O => gpio_bus_in(27),T => gpio_t(27),C => gpio_clk,PAD => WING_BH3 );
pin28: IOPAD port map(I => gpio_o(28),O => gpio_bus_in(28),T => gpio_t(28),C => gpio_clk,PAD => WING_BH4 );
pin29: IOPAD port map(I => gpio_o(29),O => gpio_bus_in(29),T => gpio_t(29),C => gpio_clk,PAD => WING_BH5 );
pin30: IOPAD port map(I => gpio_o(30),O => gpio_bus_in(30),T => gpio_t(30),C => gpio_clk,PAD => WING_BH6 );
pin31: IOPAD port map(I => gpio_o(31),O => gpio_bus_in(31),T => gpio_t(31),C => gpio_clk,PAD => WING_BH7 );
pin32: IOPAD port map(I => gpio_o(32),O => gpio_bus_in(32),T => gpio_t(32),C => gpio_clk,PAD => WING_CL0 );
pin33: IOPAD port map(I => gpio_o(33),O => gpio_bus_in(33),T => gpio_t(33),C => gpio_clk,PAD => WING_CL1 );
pin34: IOPAD port map(I => gpio_o(34),O => gpio_bus_in(34),T => gpio_t(34),C => gpio_clk,PAD => WING_CL2 );
pin35: IOPAD port map(I => gpio_o(35),O => gpio_bus_in(35),T => gpio_t(35),C => gpio_clk,PAD => WING_CL3 );
pin36: IOPAD port map(I => gpio_o(36),O => gpio_bus_in(36),T => gpio_t(36),C => gpio_clk,PAD => WING_CL4 );
pin37: IOPAD port map(I => gpio_o(37),O => gpio_bus_in(37),T => gpio_t(37),C => gpio_clk,PAD => WING_CL5 );
pin38: IOPAD port map(I => gpio_o(38),O => gpio_bus_in(38),T => gpio_t(38),C => gpio_clk,PAD => WING_CL6 );
pin39: IOPAD port map(I => gpio_o(39),O => gpio_bus_in(39),T => gpio_t(39),C => gpio_clk,PAD => WING_CL7 );
pin40: IOPAD port map(I => gpio_o(40),O => gpio_bus_in(40),T => gpio_t(40),C => gpio_clk,PAD => WING_CH0 );
pin41: IOPAD port map(I => gpio_o(41),O => gpio_bus_in(41),T => gpio_t(41),C => gpio_clk,PAD => WING_CH1 );
pin42: IOPAD port map(I => gpio_o(42),O => gpio_bus_in(42),T => gpio_t(42),C => gpio_clk,PAD => WING_CH2 );
pin43: IOPAD port map(I => gpio_o(43),O => gpio_bus_in(43),T => gpio_t(43),C => gpio_clk,PAD => WING_CH3 );
pin44: IOPAD port map(I => gpio_o(44),O => gpio_bus_in(44),T => gpio_t(44),C => gpio_clk,PAD => WING_CH4 );
pin45: IOPAD port map(I => gpio_o(45),O => gpio_bus_in(45),T => gpio_t(45),C => gpio_clk,PAD => WING_CH5 );
pin46: IOPAD port map(I => gpio_o(46),O => gpio_bus_in(46),T => gpio_t(46),C => gpio_clk,PAD => WING_CH6 );
pin47: IOPAD port map(I => gpio_o(47),O => gpio_bus_in(47),T => gpio_t(47),C => gpio_clk,PAD => WING_CH7 );
-- ospics: OPAD port map ( I => gpio_bus_out.gpio_o(48), PAD => SPI_CS );
process(gpio_spp_read)
-- sigmadelta_spp_data,
-- timers_pwm,
-- spi2_mosi,spi2_sck)
begin
--gpio_spp_data <= (others => DontCareValue);
gpio_bus_in(97 downto 49) <= (others => DontCareValue);
-- gpio_bus_in.gpio_spp_data(0) <= platform_audio_sd; -- PPS0 : SIGMADELTA DATA
-- gpio_bus_in.gpio_spp_data(1) <= timers_pwm(0); -- PPS1 : TIMER0
-- gpio_bus_in.gpio_spp_data(2) <= timers_pwm(1); -- PPS2 : TIMER1
-- gpio_bus_in.gpio_spp_data(3) <= spi2_mosi; -- PPS3 : USPI MOSI
-- gpio_bus_in.gpio_spp_data(4) <= spi2_sck; -- PPS4 : USPI SCK
-- gpio_bus_in.gpio_spp_data(5) <= platform_audio_sd; -- PPS5 : SIGMADELTA1 DATA
-- gpio_bus_in.gpio_spp_data(6) <= uart2_tx; -- PPS6 : UART2 DATA
-- gpio_bus_in.gpio_spp_data(8) <= platform_audio_sd;
-- spi2_miso <= gpio_bus_out_record.gpio_spp_read(0); -- PPS0 : USPI MISO
-- uart2_rx <= gpio_bus_out_record.gpio_spp_read(1); -- PPS0 : USPI MISO
end process;
end BEHAVIORAL;
|
--------------------------------------------------------------------------------
-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version : 14.3
-- \ \ Application :
-- / / Filename : xil_10080_19
-- /___/ /\ Timestamp : 02/08/2013 16:21:11
-- \ \ / \
-- \___\/\___\
--
--Command:
--Design Name:
-- The Papilio Default Pinout device defines the pins for a Papilio board that does not have a MegaWing attached to it.
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
library UNISIM;
use UNISIM.Vcomponents.ALL;
library board;
use board.zpupkg.all;
use board.zpuinopkg.all;
use board.zpuino_config.all;
use board.zpu_config.all;
library zpuino;
use zpuino.pad.all;
use zpuino.papilio_pkg.all;
-- Unfortunately the Xilinx Schematic Editor does not support records, so we have to put all wishbone signals into one array.
-- This is a little cumbersome but is better then dealing with all the signals in the schematic editor.
-- This is what the original record base approach looked like:
--
-- type gpio_bus_in_type is record
-- gpio_i: std_logic_vector(48 downto 0);
-- gpio_spp_data: std_logic_vector(48 downto 0);
-- end record;
--
-- type gpio_bus_out_type is record
-- gpio_clk: std_logic;
-- gpio_o: std_logic_vector(48 downto 0);
-- gpio_t: std_logic_vector(48 downto 0);
-- gpio_spp_read: std_logic_vector(48 downto 0);
-- end record;
--
-- Turning them into an array looks like this:
--
-- gpio_bus_in : in std_logic_vector(97 downto 0);
--
-- gpio_bus_in(97 downto 49) <= gpio_i;
-- gpio_bus_in(48 downto 0) <= gpio_bus_in_record.gpio_spp_data;
--
-- gpio_bus_out : out std_logic_vector(146 downto 0);
--
-- gpio_o <= gpio_bus_out(146 downto 98);
-- gpio_t <= gpio_bus_out(97 downto 49);
-- gpio_bus_out_record.gpio_spp_read <= gpio_bus_out(48 downto 0);
entity Papilio_Default_Pinout is
port (
-- gpio_clk: in std_logic;
-- gpio_o: in std_logic_vector(48 downto 0);
-- gpio_t: in std_logic_vector(48 downto 0);
-- gpio_i: out std_logic_vector(48 downto 0);
--
-- gpio_spp_data: out std_logic_vector(48 downto 0);
-- gpio_spp_read: in std_logic_vector(48 downto 0);
gpio_bus_in : out std_logic_vector(97 downto 0);
gpio_bus_out : in std_logic_vector(147 downto 0);
WING_AH0 : inout std_logic;
WING_AH1 : inout std_logic;
WING_AH2 : inout std_logic;
WING_AH3 : inout std_logic;
WING_AH4 : inout std_logic;
WING_AH5 : inout std_logic;
WING_AH6 : inout std_logic;
WING_AH7 : inout std_logic;
WING_AL0 : inout std_logic;
WING_AL1 : inout std_logic;
WING_AL2 : inout std_logic;
WING_AL3 : inout std_logic;
WING_AL4 : inout std_logic;
WING_AL5 : inout std_logic;
WING_AL6 : inout std_logic;
WING_AL7 : inout std_logic;
WING_BH0 : inout std_logic;
WING_BH1 : inout std_logic;
WING_BH2 : inout std_logic;
WING_BH3 : inout std_logic;
WING_BH4 : inout std_logic;
WING_BH5 : inout std_logic;
WING_BH6 : inout std_logic;
WING_BH7 : inout std_logic;
WING_BL0 : inout std_logic;
WING_BL1 : inout std_logic;
WING_BL2 : inout std_logic;
WING_BL3 : inout std_logic;
WING_BL4 : inout std_logic;
WING_BL5 : inout std_logic;
WING_BL6 : inout std_logic;
WING_BL7 : inout std_logic;
WING_CH0 : inout std_logic;
WING_CH1 : inout std_logic;
WING_CH2 : inout std_logic;
WING_CH3 : inout std_logic;
WING_CH4 : inout std_logic;
WING_CH5 : inout std_logic;
WING_CH6 : inout std_logic;
WING_CH7 : inout std_logic;
WING_CL0 : inout std_logic;
WING_CL1 : inout std_logic;
WING_CL2 : inout std_logic;
WING_CL3 : inout std_logic;
WING_CL4 : inout std_logic;
WING_CL5 : inout std_logic;
WING_CL6 : inout std_logic;
WING_CL7 : inout std_logic
);
end Papilio_Default_Pinout;
architecture BEHAVIORAL of Papilio_Default_Pinout is
-- signal gpio_bus_out.gpio_o: std_logic_vector(zpuino_gpio_count-1 downto 0);
-- signal gpio_bus_out.gpio_t: std_logic_vector(zpuino_gpio_count-1 downto 0);
-- signal gpio_bus_in.gpio_i: std_logic_vector(zpuino_gpio_count-1 downto 0);
--
-- -- SPP signal is one more than GPIO count
-- signal gpio_bus_in.gpio_spp_data: std_logic_vector(zpuino_gpio_count-1 downto 0);
-- signal gpio_bus_out.gpio_spp_read: std_logic_vector(zpuino_gpio_count-1 downto 0);
--
-- constant spp_cap_in: std_logic_vector(zpuino_gpio_count-1 downto 0) :=
-- "0" &
-- "1111111111111111" &
-- "1111111111111111" &
-- "1111111111111111";
-- constant spp_cap_out: std_logic_vector(zpuino_gpio_count-1 downto 0) :=
-- "0" &
-- "1111111111111111" &
-- "1111111111111111" &
-- "1111111111111111";
-- signal gpio_bus_in_record : gpio_bus_in_type;
-- signal gpio_bus_out_record : gpio_bus_out_type;
signal gpio_o: std_logic_vector(48 downto 0);
signal gpio_t: std_logic_vector(48 downto 0);
signal gpio_i: std_logic_vector(48 downto 0);
signal gpio_spp_data: std_logic_vector(48 downto 0);
signal gpio_spp_read: std_logic_vector(48 downto 0);
signal gpio_clk: std_logic;
begin
--Unpack the signal array into a record so the modules code is easier to understand.
--gpio_bus_in(97 downto 49) <= gpio_spp_data;
--gpio_bus_in(48 downto 0) <= gpio_i;
gpio_clk <= gpio_bus_out(147);
gpio_o <= gpio_bus_out(146 downto 98);
gpio_t <= gpio_bus_out(97 downto 49);
gpio_spp_read <= gpio_bus_out(48 downto 0);
-- gpio_bus_in(97 downto 49) <= gpio_i;
-- gpio_bus_in(48 downto 0) <= gpio_bus_in_record.gpio_spp_data;
-- gpio_clk <= gpio_bus_out(147);
-- gpio_o <= gpio_bus_out(146 downto 98);
-- gpio_t <= gpio_bus_out(97 downto 49);
-- gpio_bus_out_record.gpio_spp_read <= gpio_bus_out(48 downto 0);
-- gpio_bus_in.gpio_inst: zpuino_gpio
-- generic map (
-- gpio_count => zpuino_gpio_count
-- )
-- port map (
-- gpio_bus_out.gpio_clk => gpio_bus_out.gpio_clk,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => wb_dat_o,
-- wb_dat_i => wb_dat_i,
-- wb_adr_i => wb_adr_i,
-- wb_we_i => wb_we_i,
-- wb_cyc_i => wb_cyc_i,
-- wb_stb_i => wb_stb_i,
-- wb_ack_o => wb_ack_o,
-- wb_inta_o => wb_inta_o,
--
-- spp_data => gpio_bus_in.gpio_spp_data,
-- spp_read => gpio_bus_out.gpio_spp_read,
--
-- gpio_bus_in.gpio_i => gpio_bus_in.gpio_i,
-- gpio_bus_out.gpio_t => gpio_bus_out.gpio_t,
-- gpio_bus_out.gpio_o => gpio_bus_out.gpio_o,
-- spp_cap_in => spp_cap_in,
-- spp_cap_out => spp_cap_out
-- );
pin00: IOPAD port map(I => gpio_o(0), O => gpio_bus_in(0), T => gpio_t(0), C => gpio_clk,PAD => WING_AL0 );
pin01: IOPAD port map(I => gpio_o(1), O => gpio_bus_in(1), T => gpio_t(1), C => gpio_clk,PAD => WING_AL1 );
pin02: IOPAD port map(I => gpio_o(2), O => gpio_bus_in(2), T => gpio_t(2), C => gpio_clk,PAD => WING_AL2 );
pin03: IOPAD port map(I => gpio_o(3), O => gpio_bus_in(3), T => gpio_t(3), C => gpio_clk,PAD => WING_AL3 );
pin04: IOPAD port map(I => gpio_o(4), O => gpio_bus_in(4), T => gpio_t(4), C => gpio_clk,PAD => WING_AL4 );
pin05: IOPAD port map(I => gpio_o(5), O => gpio_bus_in(5), T => gpio_t(5), C => gpio_clk,PAD => WING_AL5 );
pin06: IOPAD port map(I => gpio_o(6), O => gpio_bus_in(6), T => gpio_t(6), C => gpio_clk,PAD => WING_AL6 );
pin07: IOPAD port map(I => gpio_o(7), O => gpio_bus_in(7), T => gpio_t(7), C => gpio_clk,PAD => WING_AL7 );
pin08: IOPAD port map(I => gpio_o(8), O => gpio_bus_in(8), T => gpio_t(8), C => gpio_clk,PAD => WING_AH0 );
pin09: IOPAD port map(I => gpio_o(9), O => gpio_bus_in(9), T => gpio_t(9), C => gpio_clk,PAD => WING_AH1 );
pin10: IOPAD port map(I => gpio_o(10),O => gpio_bus_in(10),T => gpio_t(10),C => gpio_clk,PAD => WING_AH2 );
pin11: IOPAD port map(I => gpio_o(11),O => gpio_bus_in(11),T => gpio_t(11),C => gpio_clk,PAD => WING_AH3 );
pin12: IOPAD port map(I => gpio_o(12),O => gpio_bus_in(12),T => gpio_t(12),C => gpio_clk,PAD => WING_AH4 );
pin13: IOPAD port map(I => gpio_o(13),O => gpio_bus_in(13),T => gpio_t(13),C => gpio_clk,PAD => WING_AH5 );
pin14: IOPAD port map(I => gpio_o(14),O => gpio_bus_in(14),T => gpio_t(14),C => gpio_clk,PAD => WING_AH6 );
pin15: IOPAD port map(I => gpio_o(15),O => gpio_bus_in(15),T => gpio_t(15),C => gpio_clk,PAD => WING_AH7 );
pin16: IOPAD port map(I => gpio_o(16),O => gpio_bus_in(16),T => gpio_t(16),C => gpio_clk,PAD => WING_BL0 );
pin17: IOPAD port map(I => gpio_o(17),O => gpio_bus_in(17),T => gpio_t(17),C => gpio_clk,PAD => WING_BL1 );
pin18: IOPAD port map(I => gpio_o(18),O => gpio_bus_in(18),T => gpio_t(18),C => gpio_clk,PAD => WING_BL2 );
pin19: IOPAD port map(I => gpio_o(19),O => gpio_bus_in(19),T => gpio_t(19),C => gpio_clk,PAD => WING_BL3 );
pin20: IOPAD port map(I => gpio_o(20),O => gpio_bus_in(20),T => gpio_t(20),C => gpio_clk,PAD => WING_BL4 );
pin21: IOPAD port map(I => gpio_o(21),O => gpio_bus_in(21),T => gpio_t(21),C => gpio_clk,PAD => WING_BL5 );
pin22: IOPAD port map(I => gpio_o(22),O => gpio_bus_in(22),T => gpio_t(22),C => gpio_clk,PAD => WING_BL6 );
pin23: IOPAD port map(I => gpio_o(23),O => gpio_bus_in(23),T => gpio_t(23),C => gpio_clk,PAD => WING_BL7 );
pin24: IOPAD port map(I => gpio_o(24),O => gpio_bus_in(24),T => gpio_t(24),C => gpio_clk,PAD => WING_BH0 );
pin25: IOPAD port map(I => gpio_o(25),O => gpio_bus_in(25),T => gpio_t(25),C => gpio_clk,PAD => WING_BH1 );
pin26: IOPAD port map(I => gpio_o(26),O => gpio_bus_in(26),T => gpio_t(26),C => gpio_clk,PAD => WING_BH2 );
pin27: IOPAD port map(I => gpio_o(27),O => gpio_bus_in(27),T => gpio_t(27),C => gpio_clk,PAD => WING_BH3 );
pin28: IOPAD port map(I => gpio_o(28),O => gpio_bus_in(28),T => gpio_t(28),C => gpio_clk,PAD => WING_BH4 );
pin29: IOPAD port map(I => gpio_o(29),O => gpio_bus_in(29),T => gpio_t(29),C => gpio_clk,PAD => WING_BH5 );
pin30: IOPAD port map(I => gpio_o(30),O => gpio_bus_in(30),T => gpio_t(30),C => gpio_clk,PAD => WING_BH6 );
pin31: IOPAD port map(I => gpio_o(31),O => gpio_bus_in(31),T => gpio_t(31),C => gpio_clk,PAD => WING_BH7 );
pin32: IOPAD port map(I => gpio_o(32),O => gpio_bus_in(32),T => gpio_t(32),C => gpio_clk,PAD => WING_CL0 );
pin33: IOPAD port map(I => gpio_o(33),O => gpio_bus_in(33),T => gpio_t(33),C => gpio_clk,PAD => WING_CL1 );
pin34: IOPAD port map(I => gpio_o(34),O => gpio_bus_in(34),T => gpio_t(34),C => gpio_clk,PAD => WING_CL2 );
pin35: IOPAD port map(I => gpio_o(35),O => gpio_bus_in(35),T => gpio_t(35),C => gpio_clk,PAD => WING_CL3 );
pin36: IOPAD port map(I => gpio_o(36),O => gpio_bus_in(36),T => gpio_t(36),C => gpio_clk,PAD => WING_CL4 );
pin37: IOPAD port map(I => gpio_o(37),O => gpio_bus_in(37),T => gpio_t(37),C => gpio_clk,PAD => WING_CL5 );
pin38: IOPAD port map(I => gpio_o(38),O => gpio_bus_in(38),T => gpio_t(38),C => gpio_clk,PAD => WING_CL6 );
pin39: IOPAD port map(I => gpio_o(39),O => gpio_bus_in(39),T => gpio_t(39),C => gpio_clk,PAD => WING_CL7 );
pin40: IOPAD port map(I => gpio_o(40),O => gpio_bus_in(40),T => gpio_t(40),C => gpio_clk,PAD => WING_CH0 );
pin41: IOPAD port map(I => gpio_o(41),O => gpio_bus_in(41),T => gpio_t(41),C => gpio_clk,PAD => WING_CH1 );
pin42: IOPAD port map(I => gpio_o(42),O => gpio_bus_in(42),T => gpio_t(42),C => gpio_clk,PAD => WING_CH2 );
pin43: IOPAD port map(I => gpio_o(43),O => gpio_bus_in(43),T => gpio_t(43),C => gpio_clk,PAD => WING_CH3 );
pin44: IOPAD port map(I => gpio_o(44),O => gpio_bus_in(44),T => gpio_t(44),C => gpio_clk,PAD => WING_CH4 );
pin45: IOPAD port map(I => gpio_o(45),O => gpio_bus_in(45),T => gpio_t(45),C => gpio_clk,PAD => WING_CH5 );
pin46: IOPAD port map(I => gpio_o(46),O => gpio_bus_in(46),T => gpio_t(46),C => gpio_clk,PAD => WING_CH6 );
pin47: IOPAD port map(I => gpio_o(47),O => gpio_bus_in(47),T => gpio_t(47),C => gpio_clk,PAD => WING_CH7 );
-- ospics: OPAD port map ( I => gpio_bus_out.gpio_o(48), PAD => SPI_CS );
process(gpio_spp_read)
-- sigmadelta_spp_data,
-- timers_pwm,
-- spi2_mosi,spi2_sck)
begin
--gpio_spp_data <= (others => DontCareValue);
gpio_bus_in(97 downto 49) <= (others => DontCareValue);
-- gpio_bus_in.gpio_spp_data(0) <= platform_audio_sd; -- PPS0 : SIGMADELTA DATA
-- gpio_bus_in.gpio_spp_data(1) <= timers_pwm(0); -- PPS1 : TIMER0
-- gpio_bus_in.gpio_spp_data(2) <= timers_pwm(1); -- PPS2 : TIMER1
-- gpio_bus_in.gpio_spp_data(3) <= spi2_mosi; -- PPS3 : USPI MOSI
-- gpio_bus_in.gpio_spp_data(4) <= spi2_sck; -- PPS4 : USPI SCK
-- gpio_bus_in.gpio_spp_data(5) <= platform_audio_sd; -- PPS5 : SIGMADELTA1 DATA
-- gpio_bus_in.gpio_spp_data(6) <= uart2_tx; -- PPS6 : UART2 DATA
-- gpio_bus_in.gpio_spp_data(8) <= platform_audio_sd;
-- spi2_miso <= gpio_bus_out_record.gpio_spp_read(0); -- PPS0 : USPI MISO
-- uart2_rx <= gpio_bus_out_record.gpio_spp_read(1); -- PPS0 : USPI MISO
end process;
end BEHAVIORAL;
|
--------------------------------------------------------------------------------
-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version : 14.3
-- \ \ Application :
-- / / Filename : xil_10080_19
-- /___/ /\ Timestamp : 02/08/2013 16:21:11
-- \ \ / \
-- \___\/\___\
--
--Command:
--Design Name:
-- The Papilio Default Pinout device defines the pins for a Papilio board that does not have a MegaWing attached to it.
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
library UNISIM;
use UNISIM.Vcomponents.ALL;
library board;
use board.zpupkg.all;
use board.zpuinopkg.all;
use board.zpuino_config.all;
use board.zpu_config.all;
library zpuino;
use zpuino.pad.all;
use zpuino.papilio_pkg.all;
-- Unfortunately the Xilinx Schematic Editor does not support records, so we have to put all wishbone signals into one array.
-- This is a little cumbersome but is better then dealing with all the signals in the schematic editor.
-- This is what the original record base approach looked like:
--
-- type gpio_bus_in_type is record
-- gpio_i: std_logic_vector(48 downto 0);
-- gpio_spp_data: std_logic_vector(48 downto 0);
-- end record;
--
-- type gpio_bus_out_type is record
-- gpio_clk: std_logic;
-- gpio_o: std_logic_vector(48 downto 0);
-- gpio_t: std_logic_vector(48 downto 0);
-- gpio_spp_read: std_logic_vector(48 downto 0);
-- end record;
--
-- Turning them into an array looks like this:
--
-- gpio_bus_in : in std_logic_vector(97 downto 0);
--
-- gpio_bus_in(97 downto 49) <= gpio_i;
-- gpio_bus_in(48 downto 0) <= gpio_bus_in_record.gpio_spp_data;
--
-- gpio_bus_out : out std_logic_vector(146 downto 0);
--
-- gpio_o <= gpio_bus_out(146 downto 98);
-- gpio_t <= gpio_bus_out(97 downto 49);
-- gpio_bus_out_record.gpio_spp_read <= gpio_bus_out(48 downto 0);
entity Papilio_Default_Pinout is
port (
-- gpio_clk: in std_logic;
-- gpio_o: in std_logic_vector(48 downto 0);
-- gpio_t: in std_logic_vector(48 downto 0);
-- gpio_i: out std_logic_vector(48 downto 0);
--
-- gpio_spp_data: out std_logic_vector(48 downto 0);
-- gpio_spp_read: in std_logic_vector(48 downto 0);
gpio_bus_in : out std_logic_vector(97 downto 0);
gpio_bus_out : in std_logic_vector(147 downto 0);
WING_AH0 : inout std_logic;
WING_AH1 : inout std_logic;
WING_AH2 : inout std_logic;
WING_AH3 : inout std_logic;
WING_AH4 : inout std_logic;
WING_AH5 : inout std_logic;
WING_AH6 : inout std_logic;
WING_AH7 : inout std_logic;
WING_AL0 : inout std_logic;
WING_AL1 : inout std_logic;
WING_AL2 : inout std_logic;
WING_AL3 : inout std_logic;
WING_AL4 : inout std_logic;
WING_AL5 : inout std_logic;
WING_AL6 : inout std_logic;
WING_AL7 : inout std_logic;
WING_BH0 : inout std_logic;
WING_BH1 : inout std_logic;
WING_BH2 : inout std_logic;
WING_BH3 : inout std_logic;
WING_BH4 : inout std_logic;
WING_BH5 : inout std_logic;
WING_BH6 : inout std_logic;
WING_BH7 : inout std_logic;
WING_BL0 : inout std_logic;
WING_BL1 : inout std_logic;
WING_BL2 : inout std_logic;
WING_BL3 : inout std_logic;
WING_BL4 : inout std_logic;
WING_BL5 : inout std_logic;
WING_BL6 : inout std_logic;
WING_BL7 : inout std_logic;
WING_CH0 : inout std_logic;
WING_CH1 : inout std_logic;
WING_CH2 : inout std_logic;
WING_CH3 : inout std_logic;
WING_CH4 : inout std_logic;
WING_CH5 : inout std_logic;
WING_CH6 : inout std_logic;
WING_CH7 : inout std_logic;
WING_CL0 : inout std_logic;
WING_CL1 : inout std_logic;
WING_CL2 : inout std_logic;
WING_CL3 : inout std_logic;
WING_CL4 : inout std_logic;
WING_CL5 : inout std_logic;
WING_CL6 : inout std_logic;
WING_CL7 : inout std_logic
);
end Papilio_Default_Pinout;
architecture BEHAVIORAL of Papilio_Default_Pinout is
-- signal gpio_bus_out.gpio_o: std_logic_vector(zpuino_gpio_count-1 downto 0);
-- signal gpio_bus_out.gpio_t: std_logic_vector(zpuino_gpio_count-1 downto 0);
-- signal gpio_bus_in.gpio_i: std_logic_vector(zpuino_gpio_count-1 downto 0);
--
-- -- SPP signal is one more than GPIO count
-- signal gpio_bus_in.gpio_spp_data: std_logic_vector(zpuino_gpio_count-1 downto 0);
-- signal gpio_bus_out.gpio_spp_read: std_logic_vector(zpuino_gpio_count-1 downto 0);
--
-- constant spp_cap_in: std_logic_vector(zpuino_gpio_count-1 downto 0) :=
-- "0" &
-- "1111111111111111" &
-- "1111111111111111" &
-- "1111111111111111";
-- constant spp_cap_out: std_logic_vector(zpuino_gpio_count-1 downto 0) :=
-- "0" &
-- "1111111111111111" &
-- "1111111111111111" &
-- "1111111111111111";
-- signal gpio_bus_in_record : gpio_bus_in_type;
-- signal gpio_bus_out_record : gpio_bus_out_type;
signal gpio_o: std_logic_vector(48 downto 0);
signal gpio_t: std_logic_vector(48 downto 0);
signal gpio_i: std_logic_vector(48 downto 0);
signal gpio_spp_data: std_logic_vector(48 downto 0);
signal gpio_spp_read: std_logic_vector(48 downto 0);
signal gpio_clk: std_logic;
begin
--Unpack the signal array into a record so the modules code is easier to understand.
--gpio_bus_in(97 downto 49) <= gpio_spp_data;
--gpio_bus_in(48 downto 0) <= gpio_i;
gpio_clk <= gpio_bus_out(147);
gpio_o <= gpio_bus_out(146 downto 98);
gpio_t <= gpio_bus_out(97 downto 49);
gpio_spp_read <= gpio_bus_out(48 downto 0);
-- gpio_bus_in(97 downto 49) <= gpio_i;
-- gpio_bus_in(48 downto 0) <= gpio_bus_in_record.gpio_spp_data;
-- gpio_clk <= gpio_bus_out(147);
-- gpio_o <= gpio_bus_out(146 downto 98);
-- gpio_t <= gpio_bus_out(97 downto 49);
-- gpio_bus_out_record.gpio_spp_read <= gpio_bus_out(48 downto 0);
-- gpio_bus_in.gpio_inst: zpuino_gpio
-- generic map (
-- gpio_count => zpuino_gpio_count
-- )
-- port map (
-- gpio_bus_out.gpio_clk => gpio_bus_out.gpio_clk,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => wb_dat_o,
-- wb_dat_i => wb_dat_i,
-- wb_adr_i => wb_adr_i,
-- wb_we_i => wb_we_i,
-- wb_cyc_i => wb_cyc_i,
-- wb_stb_i => wb_stb_i,
-- wb_ack_o => wb_ack_o,
-- wb_inta_o => wb_inta_o,
--
-- spp_data => gpio_bus_in.gpio_spp_data,
-- spp_read => gpio_bus_out.gpio_spp_read,
--
-- gpio_bus_in.gpio_i => gpio_bus_in.gpio_i,
-- gpio_bus_out.gpio_t => gpio_bus_out.gpio_t,
-- gpio_bus_out.gpio_o => gpio_bus_out.gpio_o,
-- spp_cap_in => spp_cap_in,
-- spp_cap_out => spp_cap_out
-- );
pin00: IOPAD port map(I => gpio_o(0), O => gpio_bus_in(0), T => gpio_t(0), C => gpio_clk,PAD => WING_AL0 );
pin01: IOPAD port map(I => gpio_o(1), O => gpio_bus_in(1), T => gpio_t(1), C => gpio_clk,PAD => WING_AL1 );
pin02: IOPAD port map(I => gpio_o(2), O => gpio_bus_in(2), T => gpio_t(2), C => gpio_clk,PAD => WING_AL2 );
pin03: IOPAD port map(I => gpio_o(3), O => gpio_bus_in(3), T => gpio_t(3), C => gpio_clk,PAD => WING_AL3 );
pin04: IOPAD port map(I => gpio_o(4), O => gpio_bus_in(4), T => gpio_t(4), C => gpio_clk,PAD => WING_AL4 );
pin05: IOPAD port map(I => gpio_o(5), O => gpio_bus_in(5), T => gpio_t(5), C => gpio_clk,PAD => WING_AL5 );
pin06: IOPAD port map(I => gpio_o(6), O => gpio_bus_in(6), T => gpio_t(6), C => gpio_clk,PAD => WING_AL6 );
pin07: IOPAD port map(I => gpio_o(7), O => gpio_bus_in(7), T => gpio_t(7), C => gpio_clk,PAD => WING_AL7 );
pin08: IOPAD port map(I => gpio_o(8), O => gpio_bus_in(8), T => gpio_t(8), C => gpio_clk,PAD => WING_AH0 );
pin09: IOPAD port map(I => gpio_o(9), O => gpio_bus_in(9), T => gpio_t(9), C => gpio_clk,PAD => WING_AH1 );
pin10: IOPAD port map(I => gpio_o(10),O => gpio_bus_in(10),T => gpio_t(10),C => gpio_clk,PAD => WING_AH2 );
pin11: IOPAD port map(I => gpio_o(11),O => gpio_bus_in(11),T => gpio_t(11),C => gpio_clk,PAD => WING_AH3 );
pin12: IOPAD port map(I => gpio_o(12),O => gpio_bus_in(12),T => gpio_t(12),C => gpio_clk,PAD => WING_AH4 );
pin13: IOPAD port map(I => gpio_o(13),O => gpio_bus_in(13),T => gpio_t(13),C => gpio_clk,PAD => WING_AH5 );
pin14: IOPAD port map(I => gpio_o(14),O => gpio_bus_in(14),T => gpio_t(14),C => gpio_clk,PAD => WING_AH6 );
pin15: IOPAD port map(I => gpio_o(15),O => gpio_bus_in(15),T => gpio_t(15),C => gpio_clk,PAD => WING_AH7 );
pin16: IOPAD port map(I => gpio_o(16),O => gpio_bus_in(16),T => gpio_t(16),C => gpio_clk,PAD => WING_BL0 );
pin17: IOPAD port map(I => gpio_o(17),O => gpio_bus_in(17),T => gpio_t(17),C => gpio_clk,PAD => WING_BL1 );
pin18: IOPAD port map(I => gpio_o(18),O => gpio_bus_in(18),T => gpio_t(18),C => gpio_clk,PAD => WING_BL2 );
pin19: IOPAD port map(I => gpio_o(19),O => gpio_bus_in(19),T => gpio_t(19),C => gpio_clk,PAD => WING_BL3 );
pin20: IOPAD port map(I => gpio_o(20),O => gpio_bus_in(20),T => gpio_t(20),C => gpio_clk,PAD => WING_BL4 );
pin21: IOPAD port map(I => gpio_o(21),O => gpio_bus_in(21),T => gpio_t(21),C => gpio_clk,PAD => WING_BL5 );
pin22: IOPAD port map(I => gpio_o(22),O => gpio_bus_in(22),T => gpio_t(22),C => gpio_clk,PAD => WING_BL6 );
pin23: IOPAD port map(I => gpio_o(23),O => gpio_bus_in(23),T => gpio_t(23),C => gpio_clk,PAD => WING_BL7 );
pin24: IOPAD port map(I => gpio_o(24),O => gpio_bus_in(24),T => gpio_t(24),C => gpio_clk,PAD => WING_BH0 );
pin25: IOPAD port map(I => gpio_o(25),O => gpio_bus_in(25),T => gpio_t(25),C => gpio_clk,PAD => WING_BH1 );
pin26: IOPAD port map(I => gpio_o(26),O => gpio_bus_in(26),T => gpio_t(26),C => gpio_clk,PAD => WING_BH2 );
pin27: IOPAD port map(I => gpio_o(27),O => gpio_bus_in(27),T => gpio_t(27),C => gpio_clk,PAD => WING_BH3 );
pin28: IOPAD port map(I => gpio_o(28),O => gpio_bus_in(28),T => gpio_t(28),C => gpio_clk,PAD => WING_BH4 );
pin29: IOPAD port map(I => gpio_o(29),O => gpio_bus_in(29),T => gpio_t(29),C => gpio_clk,PAD => WING_BH5 );
pin30: IOPAD port map(I => gpio_o(30),O => gpio_bus_in(30),T => gpio_t(30),C => gpio_clk,PAD => WING_BH6 );
pin31: IOPAD port map(I => gpio_o(31),O => gpio_bus_in(31),T => gpio_t(31),C => gpio_clk,PAD => WING_BH7 );
pin32: IOPAD port map(I => gpio_o(32),O => gpio_bus_in(32),T => gpio_t(32),C => gpio_clk,PAD => WING_CL0 );
pin33: IOPAD port map(I => gpio_o(33),O => gpio_bus_in(33),T => gpio_t(33),C => gpio_clk,PAD => WING_CL1 );
pin34: IOPAD port map(I => gpio_o(34),O => gpio_bus_in(34),T => gpio_t(34),C => gpio_clk,PAD => WING_CL2 );
pin35: IOPAD port map(I => gpio_o(35),O => gpio_bus_in(35),T => gpio_t(35),C => gpio_clk,PAD => WING_CL3 );
pin36: IOPAD port map(I => gpio_o(36),O => gpio_bus_in(36),T => gpio_t(36),C => gpio_clk,PAD => WING_CL4 );
pin37: IOPAD port map(I => gpio_o(37),O => gpio_bus_in(37),T => gpio_t(37),C => gpio_clk,PAD => WING_CL5 );
pin38: IOPAD port map(I => gpio_o(38),O => gpio_bus_in(38),T => gpio_t(38),C => gpio_clk,PAD => WING_CL6 );
pin39: IOPAD port map(I => gpio_o(39),O => gpio_bus_in(39),T => gpio_t(39),C => gpio_clk,PAD => WING_CL7 );
pin40: IOPAD port map(I => gpio_o(40),O => gpio_bus_in(40),T => gpio_t(40),C => gpio_clk,PAD => WING_CH0 );
pin41: IOPAD port map(I => gpio_o(41),O => gpio_bus_in(41),T => gpio_t(41),C => gpio_clk,PAD => WING_CH1 );
pin42: IOPAD port map(I => gpio_o(42),O => gpio_bus_in(42),T => gpio_t(42),C => gpio_clk,PAD => WING_CH2 );
pin43: IOPAD port map(I => gpio_o(43),O => gpio_bus_in(43),T => gpio_t(43),C => gpio_clk,PAD => WING_CH3 );
pin44: IOPAD port map(I => gpio_o(44),O => gpio_bus_in(44),T => gpio_t(44),C => gpio_clk,PAD => WING_CH4 );
pin45: IOPAD port map(I => gpio_o(45),O => gpio_bus_in(45),T => gpio_t(45),C => gpio_clk,PAD => WING_CH5 );
pin46: IOPAD port map(I => gpio_o(46),O => gpio_bus_in(46),T => gpio_t(46),C => gpio_clk,PAD => WING_CH6 );
pin47: IOPAD port map(I => gpio_o(47),O => gpio_bus_in(47),T => gpio_t(47),C => gpio_clk,PAD => WING_CH7 );
-- ospics: OPAD port map ( I => gpio_bus_out.gpio_o(48), PAD => SPI_CS );
process(gpio_spp_read)
-- sigmadelta_spp_data,
-- timers_pwm,
-- spi2_mosi,spi2_sck)
begin
--gpio_spp_data <= (others => DontCareValue);
gpio_bus_in(97 downto 49) <= (others => DontCareValue);
-- gpio_bus_in.gpio_spp_data(0) <= platform_audio_sd; -- PPS0 : SIGMADELTA DATA
-- gpio_bus_in.gpio_spp_data(1) <= timers_pwm(0); -- PPS1 : TIMER0
-- gpio_bus_in.gpio_spp_data(2) <= timers_pwm(1); -- PPS2 : TIMER1
-- gpio_bus_in.gpio_spp_data(3) <= spi2_mosi; -- PPS3 : USPI MOSI
-- gpio_bus_in.gpio_spp_data(4) <= spi2_sck; -- PPS4 : USPI SCK
-- gpio_bus_in.gpio_spp_data(5) <= platform_audio_sd; -- PPS5 : SIGMADELTA1 DATA
-- gpio_bus_in.gpio_spp_data(6) <= uart2_tx; -- PPS6 : UART2 DATA
-- gpio_bus_in.gpio_spp_data(8) <= platform_audio_sd;
-- spi2_miso <= gpio_bus_out_record.gpio_spp_read(0); -- PPS0 : USPI MISO
-- uart2_rx <= gpio_bus_out_record.gpio_spp_read(1); -- PPS0 : USPI MISO
end process;
end BEHAVIORAL;
|
--------------------------------------------------------------------------------
-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version : 14.3
-- \ \ Application :
-- / / Filename : xil_10080_19
-- /___/ /\ Timestamp : 02/08/2013 16:21:11
-- \ \ / \
-- \___\/\___\
--
--Command:
--Design Name:
-- The Papilio Default Pinout device defines the pins for a Papilio board that does not have a MegaWing attached to it.
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
library UNISIM;
use UNISIM.Vcomponents.ALL;
library board;
use board.zpupkg.all;
use board.zpuinopkg.all;
use board.zpuino_config.all;
use board.zpu_config.all;
library zpuino;
use zpuino.pad.all;
use zpuino.papilio_pkg.all;
-- Unfortunately the Xilinx Schematic Editor does not support records, so we have to put all wishbone signals into one array.
-- This is a little cumbersome but is better then dealing with all the signals in the schematic editor.
-- This is what the original record base approach looked like:
--
-- type gpio_bus_in_type is record
-- gpio_i: std_logic_vector(48 downto 0);
-- gpio_spp_data: std_logic_vector(48 downto 0);
-- end record;
--
-- type gpio_bus_out_type is record
-- gpio_clk: std_logic;
-- gpio_o: std_logic_vector(48 downto 0);
-- gpio_t: std_logic_vector(48 downto 0);
-- gpio_spp_read: std_logic_vector(48 downto 0);
-- end record;
--
-- Turning them into an array looks like this:
--
-- gpio_bus_in : in std_logic_vector(97 downto 0);
--
-- gpio_bus_in(97 downto 49) <= gpio_i;
-- gpio_bus_in(48 downto 0) <= gpio_bus_in_record.gpio_spp_data;
--
-- gpio_bus_out : out std_logic_vector(146 downto 0);
--
-- gpio_o <= gpio_bus_out(146 downto 98);
-- gpio_t <= gpio_bus_out(97 downto 49);
-- gpio_bus_out_record.gpio_spp_read <= gpio_bus_out(48 downto 0);
entity Papilio_Default_Pinout is
port (
-- gpio_clk: in std_logic;
-- gpio_o: in std_logic_vector(48 downto 0);
-- gpio_t: in std_logic_vector(48 downto 0);
-- gpio_i: out std_logic_vector(48 downto 0);
--
-- gpio_spp_data: out std_logic_vector(48 downto 0);
-- gpio_spp_read: in std_logic_vector(48 downto 0);
gpio_bus_in : out std_logic_vector(97 downto 0);
gpio_bus_out : in std_logic_vector(147 downto 0);
WING_AH0 : inout std_logic;
WING_AH1 : inout std_logic;
WING_AH2 : inout std_logic;
WING_AH3 : inout std_logic;
WING_AH4 : inout std_logic;
WING_AH5 : inout std_logic;
WING_AH6 : inout std_logic;
WING_AH7 : inout std_logic;
WING_AL0 : inout std_logic;
WING_AL1 : inout std_logic;
WING_AL2 : inout std_logic;
WING_AL3 : inout std_logic;
WING_AL4 : inout std_logic;
WING_AL5 : inout std_logic;
WING_AL6 : inout std_logic;
WING_AL7 : inout std_logic;
WING_BH0 : inout std_logic;
WING_BH1 : inout std_logic;
WING_BH2 : inout std_logic;
WING_BH3 : inout std_logic;
WING_BH4 : inout std_logic;
WING_BH5 : inout std_logic;
WING_BH6 : inout std_logic;
WING_BH7 : inout std_logic;
WING_BL0 : inout std_logic;
WING_BL1 : inout std_logic;
WING_BL2 : inout std_logic;
WING_BL3 : inout std_logic;
WING_BL4 : inout std_logic;
WING_BL5 : inout std_logic;
WING_BL6 : inout std_logic;
WING_BL7 : inout std_logic;
WING_CH0 : inout std_logic;
WING_CH1 : inout std_logic;
WING_CH2 : inout std_logic;
WING_CH3 : inout std_logic;
WING_CH4 : inout std_logic;
WING_CH5 : inout std_logic;
WING_CH6 : inout std_logic;
WING_CH7 : inout std_logic;
WING_CL0 : inout std_logic;
WING_CL1 : inout std_logic;
WING_CL2 : inout std_logic;
WING_CL3 : inout std_logic;
WING_CL4 : inout std_logic;
WING_CL5 : inout std_logic;
WING_CL6 : inout std_logic;
WING_CL7 : inout std_logic
);
end Papilio_Default_Pinout;
architecture BEHAVIORAL of Papilio_Default_Pinout is
-- signal gpio_bus_out.gpio_o: std_logic_vector(zpuino_gpio_count-1 downto 0);
-- signal gpio_bus_out.gpio_t: std_logic_vector(zpuino_gpio_count-1 downto 0);
-- signal gpio_bus_in.gpio_i: std_logic_vector(zpuino_gpio_count-1 downto 0);
--
-- -- SPP signal is one more than GPIO count
-- signal gpio_bus_in.gpio_spp_data: std_logic_vector(zpuino_gpio_count-1 downto 0);
-- signal gpio_bus_out.gpio_spp_read: std_logic_vector(zpuino_gpio_count-1 downto 0);
--
-- constant spp_cap_in: std_logic_vector(zpuino_gpio_count-1 downto 0) :=
-- "0" &
-- "1111111111111111" &
-- "1111111111111111" &
-- "1111111111111111";
-- constant spp_cap_out: std_logic_vector(zpuino_gpio_count-1 downto 0) :=
-- "0" &
-- "1111111111111111" &
-- "1111111111111111" &
-- "1111111111111111";
-- signal gpio_bus_in_record : gpio_bus_in_type;
-- signal gpio_bus_out_record : gpio_bus_out_type;
signal gpio_o: std_logic_vector(48 downto 0);
signal gpio_t: std_logic_vector(48 downto 0);
signal gpio_i: std_logic_vector(48 downto 0);
signal gpio_spp_data: std_logic_vector(48 downto 0);
signal gpio_spp_read: std_logic_vector(48 downto 0);
signal gpio_clk: std_logic;
begin
--Unpack the signal array into a record so the modules code is easier to understand.
--gpio_bus_in(97 downto 49) <= gpio_spp_data;
--gpio_bus_in(48 downto 0) <= gpio_i;
gpio_clk <= gpio_bus_out(147);
gpio_o <= gpio_bus_out(146 downto 98);
gpio_t <= gpio_bus_out(97 downto 49);
gpio_spp_read <= gpio_bus_out(48 downto 0);
-- gpio_bus_in(97 downto 49) <= gpio_i;
-- gpio_bus_in(48 downto 0) <= gpio_bus_in_record.gpio_spp_data;
-- gpio_clk <= gpio_bus_out(147);
-- gpio_o <= gpio_bus_out(146 downto 98);
-- gpio_t <= gpio_bus_out(97 downto 49);
-- gpio_bus_out_record.gpio_spp_read <= gpio_bus_out(48 downto 0);
-- gpio_bus_in.gpio_inst: zpuino_gpio
-- generic map (
-- gpio_count => zpuino_gpio_count
-- )
-- port map (
-- gpio_bus_out.gpio_clk => gpio_bus_out.gpio_clk,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => wb_dat_o,
-- wb_dat_i => wb_dat_i,
-- wb_adr_i => wb_adr_i,
-- wb_we_i => wb_we_i,
-- wb_cyc_i => wb_cyc_i,
-- wb_stb_i => wb_stb_i,
-- wb_ack_o => wb_ack_o,
-- wb_inta_o => wb_inta_o,
--
-- spp_data => gpio_bus_in.gpio_spp_data,
-- spp_read => gpio_bus_out.gpio_spp_read,
--
-- gpio_bus_in.gpio_i => gpio_bus_in.gpio_i,
-- gpio_bus_out.gpio_t => gpio_bus_out.gpio_t,
-- gpio_bus_out.gpio_o => gpio_bus_out.gpio_o,
-- spp_cap_in => spp_cap_in,
-- spp_cap_out => spp_cap_out
-- );
pin00: IOPAD port map(I => gpio_o(0), O => gpio_bus_in(0), T => gpio_t(0), C => gpio_clk,PAD => WING_AL0 );
pin01: IOPAD port map(I => gpio_o(1), O => gpio_bus_in(1), T => gpio_t(1), C => gpio_clk,PAD => WING_AL1 );
pin02: IOPAD port map(I => gpio_o(2), O => gpio_bus_in(2), T => gpio_t(2), C => gpio_clk,PAD => WING_AL2 );
pin03: IOPAD port map(I => gpio_o(3), O => gpio_bus_in(3), T => gpio_t(3), C => gpio_clk,PAD => WING_AL3 );
pin04: IOPAD port map(I => gpio_o(4), O => gpio_bus_in(4), T => gpio_t(4), C => gpio_clk,PAD => WING_AL4 );
pin05: IOPAD port map(I => gpio_o(5), O => gpio_bus_in(5), T => gpio_t(5), C => gpio_clk,PAD => WING_AL5 );
pin06: IOPAD port map(I => gpio_o(6), O => gpio_bus_in(6), T => gpio_t(6), C => gpio_clk,PAD => WING_AL6 );
pin07: IOPAD port map(I => gpio_o(7), O => gpio_bus_in(7), T => gpio_t(7), C => gpio_clk,PAD => WING_AL7 );
pin08: IOPAD port map(I => gpio_o(8), O => gpio_bus_in(8), T => gpio_t(8), C => gpio_clk,PAD => WING_AH0 );
pin09: IOPAD port map(I => gpio_o(9), O => gpio_bus_in(9), T => gpio_t(9), C => gpio_clk,PAD => WING_AH1 );
pin10: IOPAD port map(I => gpio_o(10),O => gpio_bus_in(10),T => gpio_t(10),C => gpio_clk,PAD => WING_AH2 );
pin11: IOPAD port map(I => gpio_o(11),O => gpio_bus_in(11),T => gpio_t(11),C => gpio_clk,PAD => WING_AH3 );
pin12: IOPAD port map(I => gpio_o(12),O => gpio_bus_in(12),T => gpio_t(12),C => gpio_clk,PAD => WING_AH4 );
pin13: IOPAD port map(I => gpio_o(13),O => gpio_bus_in(13),T => gpio_t(13),C => gpio_clk,PAD => WING_AH5 );
pin14: IOPAD port map(I => gpio_o(14),O => gpio_bus_in(14),T => gpio_t(14),C => gpio_clk,PAD => WING_AH6 );
pin15: IOPAD port map(I => gpio_o(15),O => gpio_bus_in(15),T => gpio_t(15),C => gpio_clk,PAD => WING_AH7 );
pin16: IOPAD port map(I => gpio_o(16),O => gpio_bus_in(16),T => gpio_t(16),C => gpio_clk,PAD => WING_BL0 );
pin17: IOPAD port map(I => gpio_o(17),O => gpio_bus_in(17),T => gpio_t(17),C => gpio_clk,PAD => WING_BL1 );
pin18: IOPAD port map(I => gpio_o(18),O => gpio_bus_in(18),T => gpio_t(18),C => gpio_clk,PAD => WING_BL2 );
pin19: IOPAD port map(I => gpio_o(19),O => gpio_bus_in(19),T => gpio_t(19),C => gpio_clk,PAD => WING_BL3 );
pin20: IOPAD port map(I => gpio_o(20),O => gpio_bus_in(20),T => gpio_t(20),C => gpio_clk,PAD => WING_BL4 );
pin21: IOPAD port map(I => gpio_o(21),O => gpio_bus_in(21),T => gpio_t(21),C => gpio_clk,PAD => WING_BL5 );
pin22: IOPAD port map(I => gpio_o(22),O => gpio_bus_in(22),T => gpio_t(22),C => gpio_clk,PAD => WING_BL6 );
pin23: IOPAD port map(I => gpio_o(23),O => gpio_bus_in(23),T => gpio_t(23),C => gpio_clk,PAD => WING_BL7 );
pin24: IOPAD port map(I => gpio_o(24),O => gpio_bus_in(24),T => gpio_t(24),C => gpio_clk,PAD => WING_BH0 );
pin25: IOPAD port map(I => gpio_o(25),O => gpio_bus_in(25),T => gpio_t(25),C => gpio_clk,PAD => WING_BH1 );
pin26: IOPAD port map(I => gpio_o(26),O => gpio_bus_in(26),T => gpio_t(26),C => gpio_clk,PAD => WING_BH2 );
pin27: IOPAD port map(I => gpio_o(27),O => gpio_bus_in(27),T => gpio_t(27),C => gpio_clk,PAD => WING_BH3 );
pin28: IOPAD port map(I => gpio_o(28),O => gpio_bus_in(28),T => gpio_t(28),C => gpio_clk,PAD => WING_BH4 );
pin29: IOPAD port map(I => gpio_o(29),O => gpio_bus_in(29),T => gpio_t(29),C => gpio_clk,PAD => WING_BH5 );
pin30: IOPAD port map(I => gpio_o(30),O => gpio_bus_in(30),T => gpio_t(30),C => gpio_clk,PAD => WING_BH6 );
pin31: IOPAD port map(I => gpio_o(31),O => gpio_bus_in(31),T => gpio_t(31),C => gpio_clk,PAD => WING_BH7 );
pin32: IOPAD port map(I => gpio_o(32),O => gpio_bus_in(32),T => gpio_t(32),C => gpio_clk,PAD => WING_CL0 );
pin33: IOPAD port map(I => gpio_o(33),O => gpio_bus_in(33),T => gpio_t(33),C => gpio_clk,PAD => WING_CL1 );
pin34: IOPAD port map(I => gpio_o(34),O => gpio_bus_in(34),T => gpio_t(34),C => gpio_clk,PAD => WING_CL2 );
pin35: IOPAD port map(I => gpio_o(35),O => gpio_bus_in(35),T => gpio_t(35),C => gpio_clk,PAD => WING_CL3 );
pin36: IOPAD port map(I => gpio_o(36),O => gpio_bus_in(36),T => gpio_t(36),C => gpio_clk,PAD => WING_CL4 );
pin37: IOPAD port map(I => gpio_o(37),O => gpio_bus_in(37),T => gpio_t(37),C => gpio_clk,PAD => WING_CL5 );
pin38: IOPAD port map(I => gpio_o(38),O => gpio_bus_in(38),T => gpio_t(38),C => gpio_clk,PAD => WING_CL6 );
pin39: IOPAD port map(I => gpio_o(39),O => gpio_bus_in(39),T => gpio_t(39),C => gpio_clk,PAD => WING_CL7 );
pin40: IOPAD port map(I => gpio_o(40),O => gpio_bus_in(40),T => gpio_t(40),C => gpio_clk,PAD => WING_CH0 );
pin41: IOPAD port map(I => gpio_o(41),O => gpio_bus_in(41),T => gpio_t(41),C => gpio_clk,PAD => WING_CH1 );
pin42: IOPAD port map(I => gpio_o(42),O => gpio_bus_in(42),T => gpio_t(42),C => gpio_clk,PAD => WING_CH2 );
pin43: IOPAD port map(I => gpio_o(43),O => gpio_bus_in(43),T => gpio_t(43),C => gpio_clk,PAD => WING_CH3 );
pin44: IOPAD port map(I => gpio_o(44),O => gpio_bus_in(44),T => gpio_t(44),C => gpio_clk,PAD => WING_CH4 );
pin45: IOPAD port map(I => gpio_o(45),O => gpio_bus_in(45),T => gpio_t(45),C => gpio_clk,PAD => WING_CH5 );
pin46: IOPAD port map(I => gpio_o(46),O => gpio_bus_in(46),T => gpio_t(46),C => gpio_clk,PAD => WING_CH6 );
pin47: IOPAD port map(I => gpio_o(47),O => gpio_bus_in(47),T => gpio_t(47),C => gpio_clk,PAD => WING_CH7 );
-- ospics: OPAD port map ( I => gpio_bus_out.gpio_o(48), PAD => SPI_CS );
process(gpio_spp_read)
-- sigmadelta_spp_data,
-- timers_pwm,
-- spi2_mosi,spi2_sck)
begin
--gpio_spp_data <= (others => DontCareValue);
gpio_bus_in(97 downto 49) <= (others => DontCareValue);
-- gpio_bus_in.gpio_spp_data(0) <= platform_audio_sd; -- PPS0 : SIGMADELTA DATA
-- gpio_bus_in.gpio_spp_data(1) <= timers_pwm(0); -- PPS1 : TIMER0
-- gpio_bus_in.gpio_spp_data(2) <= timers_pwm(1); -- PPS2 : TIMER1
-- gpio_bus_in.gpio_spp_data(3) <= spi2_mosi; -- PPS3 : USPI MOSI
-- gpio_bus_in.gpio_spp_data(4) <= spi2_sck; -- PPS4 : USPI SCK
-- gpio_bus_in.gpio_spp_data(5) <= platform_audio_sd; -- PPS5 : SIGMADELTA1 DATA
-- gpio_bus_in.gpio_spp_data(6) <= uart2_tx; -- PPS6 : UART2 DATA
-- gpio_bus_in.gpio_spp_data(8) <= platform_audio_sd;
-- spi2_miso <= gpio_bus_out_record.gpio_spp_read(0); -- PPS0 : USPI MISO
-- uart2_rx <= gpio_bus_out_record.gpio_spp_read(1); -- PPS0 : USPI MISO
end process;
end BEHAVIORAL;
|
--------------------------------------------------------------------------------
-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version : 14.3
-- \ \ Application :
-- / / Filename : xil_10080_19
-- /___/ /\ Timestamp : 02/08/2013 16:21:11
-- \ \ / \
-- \___\/\___\
--
--Command:
--Design Name:
-- The Papilio Default Pinout device defines the pins for a Papilio board that does not have a MegaWing attached to it.
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
library UNISIM;
use UNISIM.Vcomponents.ALL;
library board;
use board.zpupkg.all;
use board.zpuinopkg.all;
use board.zpuino_config.all;
use board.zpu_config.all;
library zpuino;
use zpuino.pad.all;
use zpuino.papilio_pkg.all;
-- Unfortunately the Xilinx Schematic Editor does not support records, so we have to put all wishbone signals into one array.
-- This is a little cumbersome but is better then dealing with all the signals in the schematic editor.
-- This is what the original record base approach looked like:
--
-- type gpio_bus_in_type is record
-- gpio_i: std_logic_vector(48 downto 0);
-- gpio_spp_data: std_logic_vector(48 downto 0);
-- end record;
--
-- type gpio_bus_out_type is record
-- gpio_clk: std_logic;
-- gpio_o: std_logic_vector(48 downto 0);
-- gpio_t: std_logic_vector(48 downto 0);
-- gpio_spp_read: std_logic_vector(48 downto 0);
-- end record;
--
-- Turning them into an array looks like this:
--
-- gpio_bus_in : in std_logic_vector(97 downto 0);
--
-- gpio_bus_in(97 downto 49) <= gpio_i;
-- gpio_bus_in(48 downto 0) <= gpio_bus_in_record.gpio_spp_data;
--
-- gpio_bus_out : out std_logic_vector(146 downto 0);
--
-- gpio_o <= gpio_bus_out(146 downto 98);
-- gpio_t <= gpio_bus_out(97 downto 49);
-- gpio_bus_out_record.gpio_spp_read <= gpio_bus_out(48 downto 0);
entity Papilio_Default_Pinout is
port (
-- gpio_clk: in std_logic;
-- gpio_o: in std_logic_vector(48 downto 0);
-- gpio_t: in std_logic_vector(48 downto 0);
-- gpio_i: out std_logic_vector(48 downto 0);
--
-- gpio_spp_data: out std_logic_vector(48 downto 0);
-- gpio_spp_read: in std_logic_vector(48 downto 0);
gpio_bus_in : out std_logic_vector(97 downto 0);
gpio_bus_out : in std_logic_vector(147 downto 0);
WING_AH0 : inout std_logic;
WING_AH1 : inout std_logic;
WING_AH2 : inout std_logic;
WING_AH3 : inout std_logic;
WING_AH4 : inout std_logic;
WING_AH5 : inout std_logic;
WING_AH6 : inout std_logic;
WING_AH7 : inout std_logic;
WING_AL0 : inout std_logic;
WING_AL1 : inout std_logic;
WING_AL2 : inout std_logic;
WING_AL3 : inout std_logic;
WING_AL4 : inout std_logic;
WING_AL5 : inout std_logic;
WING_AL6 : inout std_logic;
WING_AL7 : inout std_logic;
WING_BH0 : inout std_logic;
WING_BH1 : inout std_logic;
WING_BH2 : inout std_logic;
WING_BH3 : inout std_logic;
WING_BH4 : inout std_logic;
WING_BH5 : inout std_logic;
WING_BH6 : inout std_logic;
WING_BH7 : inout std_logic;
WING_BL0 : inout std_logic;
WING_BL1 : inout std_logic;
WING_BL2 : inout std_logic;
WING_BL3 : inout std_logic;
WING_BL4 : inout std_logic;
WING_BL5 : inout std_logic;
WING_BL6 : inout std_logic;
WING_BL7 : inout std_logic;
WING_CH0 : inout std_logic;
WING_CH1 : inout std_logic;
WING_CH2 : inout std_logic;
WING_CH3 : inout std_logic;
WING_CH4 : inout std_logic;
WING_CH5 : inout std_logic;
WING_CH6 : inout std_logic;
WING_CH7 : inout std_logic;
WING_CL0 : inout std_logic;
WING_CL1 : inout std_logic;
WING_CL2 : inout std_logic;
WING_CL3 : inout std_logic;
WING_CL4 : inout std_logic;
WING_CL5 : inout std_logic;
WING_CL6 : inout std_logic;
WING_CL7 : inout std_logic
);
end Papilio_Default_Pinout;
architecture BEHAVIORAL of Papilio_Default_Pinout is
-- signal gpio_bus_out.gpio_o: std_logic_vector(zpuino_gpio_count-1 downto 0);
-- signal gpio_bus_out.gpio_t: std_logic_vector(zpuino_gpio_count-1 downto 0);
-- signal gpio_bus_in.gpio_i: std_logic_vector(zpuino_gpio_count-1 downto 0);
--
-- -- SPP signal is one more than GPIO count
-- signal gpio_bus_in.gpio_spp_data: std_logic_vector(zpuino_gpio_count-1 downto 0);
-- signal gpio_bus_out.gpio_spp_read: std_logic_vector(zpuino_gpio_count-1 downto 0);
--
-- constant spp_cap_in: std_logic_vector(zpuino_gpio_count-1 downto 0) :=
-- "0" &
-- "1111111111111111" &
-- "1111111111111111" &
-- "1111111111111111";
-- constant spp_cap_out: std_logic_vector(zpuino_gpio_count-1 downto 0) :=
-- "0" &
-- "1111111111111111" &
-- "1111111111111111" &
-- "1111111111111111";
-- signal gpio_bus_in_record : gpio_bus_in_type;
-- signal gpio_bus_out_record : gpio_bus_out_type;
signal gpio_o: std_logic_vector(48 downto 0);
signal gpio_t: std_logic_vector(48 downto 0);
signal gpio_i: std_logic_vector(48 downto 0);
signal gpio_spp_data: std_logic_vector(48 downto 0);
signal gpio_spp_read: std_logic_vector(48 downto 0);
signal gpio_clk: std_logic;
begin
--Unpack the signal array into a record so the modules code is easier to understand.
--gpio_bus_in(97 downto 49) <= gpio_spp_data;
--gpio_bus_in(48 downto 0) <= gpio_i;
gpio_clk <= gpio_bus_out(147);
gpio_o <= gpio_bus_out(146 downto 98);
gpio_t <= gpio_bus_out(97 downto 49);
gpio_spp_read <= gpio_bus_out(48 downto 0);
-- gpio_bus_in(97 downto 49) <= gpio_i;
-- gpio_bus_in(48 downto 0) <= gpio_bus_in_record.gpio_spp_data;
-- gpio_clk <= gpio_bus_out(147);
-- gpio_o <= gpio_bus_out(146 downto 98);
-- gpio_t <= gpio_bus_out(97 downto 49);
-- gpio_bus_out_record.gpio_spp_read <= gpio_bus_out(48 downto 0);
-- gpio_bus_in.gpio_inst: zpuino_gpio
-- generic map (
-- gpio_count => zpuino_gpio_count
-- )
-- port map (
-- gpio_bus_out.gpio_clk => gpio_bus_out.gpio_clk,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => wb_dat_o,
-- wb_dat_i => wb_dat_i,
-- wb_adr_i => wb_adr_i,
-- wb_we_i => wb_we_i,
-- wb_cyc_i => wb_cyc_i,
-- wb_stb_i => wb_stb_i,
-- wb_ack_o => wb_ack_o,
-- wb_inta_o => wb_inta_o,
--
-- spp_data => gpio_bus_in.gpio_spp_data,
-- spp_read => gpio_bus_out.gpio_spp_read,
--
-- gpio_bus_in.gpio_i => gpio_bus_in.gpio_i,
-- gpio_bus_out.gpio_t => gpio_bus_out.gpio_t,
-- gpio_bus_out.gpio_o => gpio_bus_out.gpio_o,
-- spp_cap_in => spp_cap_in,
-- spp_cap_out => spp_cap_out
-- );
pin00: IOPAD port map(I => gpio_o(0), O => gpio_bus_in(0), T => gpio_t(0), C => gpio_clk,PAD => WING_AL0 );
pin01: IOPAD port map(I => gpio_o(1), O => gpio_bus_in(1), T => gpio_t(1), C => gpio_clk,PAD => WING_AL1 );
pin02: IOPAD port map(I => gpio_o(2), O => gpio_bus_in(2), T => gpio_t(2), C => gpio_clk,PAD => WING_AL2 );
pin03: IOPAD port map(I => gpio_o(3), O => gpio_bus_in(3), T => gpio_t(3), C => gpio_clk,PAD => WING_AL3 );
pin04: IOPAD port map(I => gpio_o(4), O => gpio_bus_in(4), T => gpio_t(4), C => gpio_clk,PAD => WING_AL4 );
pin05: IOPAD port map(I => gpio_o(5), O => gpio_bus_in(5), T => gpio_t(5), C => gpio_clk,PAD => WING_AL5 );
pin06: IOPAD port map(I => gpio_o(6), O => gpio_bus_in(6), T => gpio_t(6), C => gpio_clk,PAD => WING_AL6 );
pin07: IOPAD port map(I => gpio_o(7), O => gpio_bus_in(7), T => gpio_t(7), C => gpio_clk,PAD => WING_AL7 );
pin08: IOPAD port map(I => gpio_o(8), O => gpio_bus_in(8), T => gpio_t(8), C => gpio_clk,PAD => WING_AH0 );
pin09: IOPAD port map(I => gpio_o(9), O => gpio_bus_in(9), T => gpio_t(9), C => gpio_clk,PAD => WING_AH1 );
pin10: IOPAD port map(I => gpio_o(10),O => gpio_bus_in(10),T => gpio_t(10),C => gpio_clk,PAD => WING_AH2 );
pin11: IOPAD port map(I => gpio_o(11),O => gpio_bus_in(11),T => gpio_t(11),C => gpio_clk,PAD => WING_AH3 );
pin12: IOPAD port map(I => gpio_o(12),O => gpio_bus_in(12),T => gpio_t(12),C => gpio_clk,PAD => WING_AH4 );
pin13: IOPAD port map(I => gpio_o(13),O => gpio_bus_in(13),T => gpio_t(13),C => gpio_clk,PAD => WING_AH5 );
pin14: IOPAD port map(I => gpio_o(14),O => gpio_bus_in(14),T => gpio_t(14),C => gpio_clk,PAD => WING_AH6 );
pin15: IOPAD port map(I => gpio_o(15),O => gpio_bus_in(15),T => gpio_t(15),C => gpio_clk,PAD => WING_AH7 );
pin16: IOPAD port map(I => gpio_o(16),O => gpio_bus_in(16),T => gpio_t(16),C => gpio_clk,PAD => WING_BL0 );
pin17: IOPAD port map(I => gpio_o(17),O => gpio_bus_in(17),T => gpio_t(17),C => gpio_clk,PAD => WING_BL1 );
pin18: IOPAD port map(I => gpio_o(18),O => gpio_bus_in(18),T => gpio_t(18),C => gpio_clk,PAD => WING_BL2 );
pin19: IOPAD port map(I => gpio_o(19),O => gpio_bus_in(19),T => gpio_t(19),C => gpio_clk,PAD => WING_BL3 );
pin20: IOPAD port map(I => gpio_o(20),O => gpio_bus_in(20),T => gpio_t(20),C => gpio_clk,PAD => WING_BL4 );
pin21: IOPAD port map(I => gpio_o(21),O => gpio_bus_in(21),T => gpio_t(21),C => gpio_clk,PAD => WING_BL5 );
pin22: IOPAD port map(I => gpio_o(22),O => gpio_bus_in(22),T => gpio_t(22),C => gpio_clk,PAD => WING_BL6 );
pin23: IOPAD port map(I => gpio_o(23),O => gpio_bus_in(23),T => gpio_t(23),C => gpio_clk,PAD => WING_BL7 );
pin24: IOPAD port map(I => gpio_o(24),O => gpio_bus_in(24),T => gpio_t(24),C => gpio_clk,PAD => WING_BH0 );
pin25: IOPAD port map(I => gpio_o(25),O => gpio_bus_in(25),T => gpio_t(25),C => gpio_clk,PAD => WING_BH1 );
pin26: IOPAD port map(I => gpio_o(26),O => gpio_bus_in(26),T => gpio_t(26),C => gpio_clk,PAD => WING_BH2 );
pin27: IOPAD port map(I => gpio_o(27),O => gpio_bus_in(27),T => gpio_t(27),C => gpio_clk,PAD => WING_BH3 );
pin28: IOPAD port map(I => gpio_o(28),O => gpio_bus_in(28),T => gpio_t(28),C => gpio_clk,PAD => WING_BH4 );
pin29: IOPAD port map(I => gpio_o(29),O => gpio_bus_in(29),T => gpio_t(29),C => gpio_clk,PAD => WING_BH5 );
pin30: IOPAD port map(I => gpio_o(30),O => gpio_bus_in(30),T => gpio_t(30),C => gpio_clk,PAD => WING_BH6 );
pin31: IOPAD port map(I => gpio_o(31),O => gpio_bus_in(31),T => gpio_t(31),C => gpio_clk,PAD => WING_BH7 );
pin32: IOPAD port map(I => gpio_o(32),O => gpio_bus_in(32),T => gpio_t(32),C => gpio_clk,PAD => WING_CL0 );
pin33: IOPAD port map(I => gpio_o(33),O => gpio_bus_in(33),T => gpio_t(33),C => gpio_clk,PAD => WING_CL1 );
pin34: IOPAD port map(I => gpio_o(34),O => gpio_bus_in(34),T => gpio_t(34),C => gpio_clk,PAD => WING_CL2 );
pin35: IOPAD port map(I => gpio_o(35),O => gpio_bus_in(35),T => gpio_t(35),C => gpio_clk,PAD => WING_CL3 );
pin36: IOPAD port map(I => gpio_o(36),O => gpio_bus_in(36),T => gpio_t(36),C => gpio_clk,PAD => WING_CL4 );
pin37: IOPAD port map(I => gpio_o(37),O => gpio_bus_in(37),T => gpio_t(37),C => gpio_clk,PAD => WING_CL5 );
pin38: IOPAD port map(I => gpio_o(38),O => gpio_bus_in(38),T => gpio_t(38),C => gpio_clk,PAD => WING_CL6 );
pin39: IOPAD port map(I => gpio_o(39),O => gpio_bus_in(39),T => gpio_t(39),C => gpio_clk,PAD => WING_CL7 );
pin40: IOPAD port map(I => gpio_o(40),O => gpio_bus_in(40),T => gpio_t(40),C => gpio_clk,PAD => WING_CH0 );
pin41: IOPAD port map(I => gpio_o(41),O => gpio_bus_in(41),T => gpio_t(41),C => gpio_clk,PAD => WING_CH1 );
pin42: IOPAD port map(I => gpio_o(42),O => gpio_bus_in(42),T => gpio_t(42),C => gpio_clk,PAD => WING_CH2 );
pin43: IOPAD port map(I => gpio_o(43),O => gpio_bus_in(43),T => gpio_t(43),C => gpio_clk,PAD => WING_CH3 );
pin44: IOPAD port map(I => gpio_o(44),O => gpio_bus_in(44),T => gpio_t(44),C => gpio_clk,PAD => WING_CH4 );
pin45: IOPAD port map(I => gpio_o(45),O => gpio_bus_in(45),T => gpio_t(45),C => gpio_clk,PAD => WING_CH5 );
pin46: IOPAD port map(I => gpio_o(46),O => gpio_bus_in(46),T => gpio_t(46),C => gpio_clk,PAD => WING_CH6 );
pin47: IOPAD port map(I => gpio_o(47),O => gpio_bus_in(47),T => gpio_t(47),C => gpio_clk,PAD => WING_CH7 );
-- ospics: OPAD port map ( I => gpio_bus_out.gpio_o(48), PAD => SPI_CS );
process(gpio_spp_read)
-- sigmadelta_spp_data,
-- timers_pwm,
-- spi2_mosi,spi2_sck)
begin
--gpio_spp_data <= (others => DontCareValue);
gpio_bus_in(97 downto 49) <= (others => DontCareValue);
-- gpio_bus_in.gpio_spp_data(0) <= platform_audio_sd; -- PPS0 : SIGMADELTA DATA
-- gpio_bus_in.gpio_spp_data(1) <= timers_pwm(0); -- PPS1 : TIMER0
-- gpio_bus_in.gpio_spp_data(2) <= timers_pwm(1); -- PPS2 : TIMER1
-- gpio_bus_in.gpio_spp_data(3) <= spi2_mosi; -- PPS3 : USPI MOSI
-- gpio_bus_in.gpio_spp_data(4) <= spi2_sck; -- PPS4 : USPI SCK
-- gpio_bus_in.gpio_spp_data(5) <= platform_audio_sd; -- PPS5 : SIGMADELTA1 DATA
-- gpio_bus_in.gpio_spp_data(6) <= uart2_tx; -- PPS6 : UART2 DATA
-- gpio_bus_in.gpio_spp_data(8) <= platform_audio_sd;
-- spi2_miso <= gpio_bus_out_record.gpio_spp_read(0); -- PPS0 : USPI MISO
-- uart2_rx <= gpio_bus_out_record.gpio_spp_read(1); -- PPS0 : USPI MISO
end process;
end BEHAVIORAL;
|
--------------------------------------------------------------------------------
-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version : 14.3
-- \ \ Application :
-- / / Filename : xil_10080_19
-- /___/ /\ Timestamp : 02/08/2013 16:21:11
-- \ \ / \
-- \___\/\___\
--
--Command:
--Design Name:
-- The Papilio Default Pinout device defines the pins for a Papilio board that does not have a MegaWing attached to it.
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
library UNISIM;
use UNISIM.Vcomponents.ALL;
library board;
use board.zpupkg.all;
use board.zpuinopkg.all;
use board.zpuino_config.all;
use board.zpu_config.all;
library zpuino;
use zpuino.pad.all;
use zpuino.papilio_pkg.all;
-- Unfortunately the Xilinx Schematic Editor does not support records, so we have to put all wishbone signals into one array.
-- This is a little cumbersome but is better then dealing with all the signals in the schematic editor.
-- This is what the original record base approach looked like:
--
-- type gpio_bus_in_type is record
-- gpio_i: std_logic_vector(48 downto 0);
-- gpio_spp_data: std_logic_vector(48 downto 0);
-- end record;
--
-- type gpio_bus_out_type is record
-- gpio_clk: std_logic;
-- gpio_o: std_logic_vector(48 downto 0);
-- gpio_t: std_logic_vector(48 downto 0);
-- gpio_spp_read: std_logic_vector(48 downto 0);
-- end record;
--
-- Turning them into an array looks like this:
--
-- gpio_bus_in : in std_logic_vector(97 downto 0);
--
-- gpio_bus_in(97 downto 49) <= gpio_i;
-- gpio_bus_in(48 downto 0) <= gpio_bus_in_record.gpio_spp_data;
--
-- gpio_bus_out : out std_logic_vector(146 downto 0);
--
-- gpio_o <= gpio_bus_out(146 downto 98);
-- gpio_t <= gpio_bus_out(97 downto 49);
-- gpio_bus_out_record.gpio_spp_read <= gpio_bus_out(48 downto 0);
entity Papilio_Default_Pinout is
port (
-- gpio_clk: in std_logic;
-- gpio_o: in std_logic_vector(48 downto 0);
-- gpio_t: in std_logic_vector(48 downto 0);
-- gpio_i: out std_logic_vector(48 downto 0);
--
-- gpio_spp_data: out std_logic_vector(48 downto 0);
-- gpio_spp_read: in std_logic_vector(48 downto 0);
gpio_bus_in : out std_logic_vector(97 downto 0);
gpio_bus_out : in std_logic_vector(147 downto 0);
WING_AH0 : inout std_logic;
WING_AH1 : inout std_logic;
WING_AH2 : inout std_logic;
WING_AH3 : inout std_logic;
WING_AH4 : inout std_logic;
WING_AH5 : inout std_logic;
WING_AH6 : inout std_logic;
WING_AH7 : inout std_logic;
WING_AL0 : inout std_logic;
WING_AL1 : inout std_logic;
WING_AL2 : inout std_logic;
WING_AL3 : inout std_logic;
WING_AL4 : inout std_logic;
WING_AL5 : inout std_logic;
WING_AL6 : inout std_logic;
WING_AL7 : inout std_logic;
WING_BH0 : inout std_logic;
WING_BH1 : inout std_logic;
WING_BH2 : inout std_logic;
WING_BH3 : inout std_logic;
WING_BH4 : inout std_logic;
WING_BH5 : inout std_logic;
WING_BH6 : inout std_logic;
WING_BH7 : inout std_logic;
WING_BL0 : inout std_logic;
WING_BL1 : inout std_logic;
WING_BL2 : inout std_logic;
WING_BL3 : inout std_logic;
WING_BL4 : inout std_logic;
WING_BL5 : inout std_logic;
WING_BL6 : inout std_logic;
WING_BL7 : inout std_logic;
WING_CH0 : inout std_logic;
WING_CH1 : inout std_logic;
WING_CH2 : inout std_logic;
WING_CH3 : inout std_logic;
WING_CH4 : inout std_logic;
WING_CH5 : inout std_logic;
WING_CH6 : inout std_logic;
WING_CH7 : inout std_logic;
WING_CL0 : inout std_logic;
WING_CL1 : inout std_logic;
WING_CL2 : inout std_logic;
WING_CL3 : inout std_logic;
WING_CL4 : inout std_logic;
WING_CL5 : inout std_logic;
WING_CL6 : inout std_logic;
WING_CL7 : inout std_logic
);
end Papilio_Default_Pinout;
architecture BEHAVIORAL of Papilio_Default_Pinout is
-- signal gpio_bus_out.gpio_o: std_logic_vector(zpuino_gpio_count-1 downto 0);
-- signal gpio_bus_out.gpio_t: std_logic_vector(zpuino_gpio_count-1 downto 0);
-- signal gpio_bus_in.gpio_i: std_logic_vector(zpuino_gpio_count-1 downto 0);
--
-- -- SPP signal is one more than GPIO count
-- signal gpio_bus_in.gpio_spp_data: std_logic_vector(zpuino_gpio_count-1 downto 0);
-- signal gpio_bus_out.gpio_spp_read: std_logic_vector(zpuino_gpio_count-1 downto 0);
--
-- constant spp_cap_in: std_logic_vector(zpuino_gpio_count-1 downto 0) :=
-- "0" &
-- "1111111111111111" &
-- "1111111111111111" &
-- "1111111111111111";
-- constant spp_cap_out: std_logic_vector(zpuino_gpio_count-1 downto 0) :=
-- "0" &
-- "1111111111111111" &
-- "1111111111111111" &
-- "1111111111111111";
-- signal gpio_bus_in_record : gpio_bus_in_type;
-- signal gpio_bus_out_record : gpio_bus_out_type;
signal gpio_o: std_logic_vector(48 downto 0);
signal gpio_t: std_logic_vector(48 downto 0);
signal gpio_i: std_logic_vector(48 downto 0);
signal gpio_spp_data: std_logic_vector(48 downto 0);
signal gpio_spp_read: std_logic_vector(48 downto 0);
signal gpio_clk: std_logic;
begin
--Unpack the signal array into a record so the modules code is easier to understand.
--gpio_bus_in(97 downto 49) <= gpio_spp_data;
--gpio_bus_in(48 downto 0) <= gpio_i;
gpio_clk <= gpio_bus_out(147);
gpio_o <= gpio_bus_out(146 downto 98);
gpio_t <= gpio_bus_out(97 downto 49);
gpio_spp_read <= gpio_bus_out(48 downto 0);
-- gpio_bus_in(97 downto 49) <= gpio_i;
-- gpio_bus_in(48 downto 0) <= gpio_bus_in_record.gpio_spp_data;
-- gpio_clk <= gpio_bus_out(147);
-- gpio_o <= gpio_bus_out(146 downto 98);
-- gpio_t <= gpio_bus_out(97 downto 49);
-- gpio_bus_out_record.gpio_spp_read <= gpio_bus_out(48 downto 0);
-- gpio_bus_in.gpio_inst: zpuino_gpio
-- generic map (
-- gpio_count => zpuino_gpio_count
-- )
-- port map (
-- gpio_bus_out.gpio_clk => gpio_bus_out.gpio_clk,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => wb_dat_o,
-- wb_dat_i => wb_dat_i,
-- wb_adr_i => wb_adr_i,
-- wb_we_i => wb_we_i,
-- wb_cyc_i => wb_cyc_i,
-- wb_stb_i => wb_stb_i,
-- wb_ack_o => wb_ack_o,
-- wb_inta_o => wb_inta_o,
--
-- spp_data => gpio_bus_in.gpio_spp_data,
-- spp_read => gpio_bus_out.gpio_spp_read,
--
-- gpio_bus_in.gpio_i => gpio_bus_in.gpio_i,
-- gpio_bus_out.gpio_t => gpio_bus_out.gpio_t,
-- gpio_bus_out.gpio_o => gpio_bus_out.gpio_o,
-- spp_cap_in => spp_cap_in,
-- spp_cap_out => spp_cap_out
-- );
pin00: IOPAD port map(I => gpio_o(0), O => gpio_bus_in(0), T => gpio_t(0), C => gpio_clk,PAD => WING_AL0 );
pin01: IOPAD port map(I => gpio_o(1), O => gpio_bus_in(1), T => gpio_t(1), C => gpio_clk,PAD => WING_AL1 );
pin02: IOPAD port map(I => gpio_o(2), O => gpio_bus_in(2), T => gpio_t(2), C => gpio_clk,PAD => WING_AL2 );
pin03: IOPAD port map(I => gpio_o(3), O => gpio_bus_in(3), T => gpio_t(3), C => gpio_clk,PAD => WING_AL3 );
pin04: IOPAD port map(I => gpio_o(4), O => gpio_bus_in(4), T => gpio_t(4), C => gpio_clk,PAD => WING_AL4 );
pin05: IOPAD port map(I => gpio_o(5), O => gpio_bus_in(5), T => gpio_t(5), C => gpio_clk,PAD => WING_AL5 );
pin06: IOPAD port map(I => gpio_o(6), O => gpio_bus_in(6), T => gpio_t(6), C => gpio_clk,PAD => WING_AL6 );
pin07: IOPAD port map(I => gpio_o(7), O => gpio_bus_in(7), T => gpio_t(7), C => gpio_clk,PAD => WING_AL7 );
pin08: IOPAD port map(I => gpio_o(8), O => gpio_bus_in(8), T => gpio_t(8), C => gpio_clk,PAD => WING_AH0 );
pin09: IOPAD port map(I => gpio_o(9), O => gpio_bus_in(9), T => gpio_t(9), C => gpio_clk,PAD => WING_AH1 );
pin10: IOPAD port map(I => gpio_o(10),O => gpio_bus_in(10),T => gpio_t(10),C => gpio_clk,PAD => WING_AH2 );
pin11: IOPAD port map(I => gpio_o(11),O => gpio_bus_in(11),T => gpio_t(11),C => gpio_clk,PAD => WING_AH3 );
pin12: IOPAD port map(I => gpio_o(12),O => gpio_bus_in(12),T => gpio_t(12),C => gpio_clk,PAD => WING_AH4 );
pin13: IOPAD port map(I => gpio_o(13),O => gpio_bus_in(13),T => gpio_t(13),C => gpio_clk,PAD => WING_AH5 );
pin14: IOPAD port map(I => gpio_o(14),O => gpio_bus_in(14),T => gpio_t(14),C => gpio_clk,PAD => WING_AH6 );
pin15: IOPAD port map(I => gpio_o(15),O => gpio_bus_in(15),T => gpio_t(15),C => gpio_clk,PAD => WING_AH7 );
pin16: IOPAD port map(I => gpio_o(16),O => gpio_bus_in(16),T => gpio_t(16),C => gpio_clk,PAD => WING_BL0 );
pin17: IOPAD port map(I => gpio_o(17),O => gpio_bus_in(17),T => gpio_t(17),C => gpio_clk,PAD => WING_BL1 );
pin18: IOPAD port map(I => gpio_o(18),O => gpio_bus_in(18),T => gpio_t(18),C => gpio_clk,PAD => WING_BL2 );
pin19: IOPAD port map(I => gpio_o(19),O => gpio_bus_in(19),T => gpio_t(19),C => gpio_clk,PAD => WING_BL3 );
pin20: IOPAD port map(I => gpio_o(20),O => gpio_bus_in(20),T => gpio_t(20),C => gpio_clk,PAD => WING_BL4 );
pin21: IOPAD port map(I => gpio_o(21),O => gpio_bus_in(21),T => gpio_t(21),C => gpio_clk,PAD => WING_BL5 );
pin22: IOPAD port map(I => gpio_o(22),O => gpio_bus_in(22),T => gpio_t(22),C => gpio_clk,PAD => WING_BL6 );
pin23: IOPAD port map(I => gpio_o(23),O => gpio_bus_in(23),T => gpio_t(23),C => gpio_clk,PAD => WING_BL7 );
pin24: IOPAD port map(I => gpio_o(24),O => gpio_bus_in(24),T => gpio_t(24),C => gpio_clk,PAD => WING_BH0 );
pin25: IOPAD port map(I => gpio_o(25),O => gpio_bus_in(25),T => gpio_t(25),C => gpio_clk,PAD => WING_BH1 );
pin26: IOPAD port map(I => gpio_o(26),O => gpio_bus_in(26),T => gpio_t(26),C => gpio_clk,PAD => WING_BH2 );
pin27: IOPAD port map(I => gpio_o(27),O => gpio_bus_in(27),T => gpio_t(27),C => gpio_clk,PAD => WING_BH3 );
pin28: IOPAD port map(I => gpio_o(28),O => gpio_bus_in(28),T => gpio_t(28),C => gpio_clk,PAD => WING_BH4 );
pin29: IOPAD port map(I => gpio_o(29),O => gpio_bus_in(29),T => gpio_t(29),C => gpio_clk,PAD => WING_BH5 );
pin30: IOPAD port map(I => gpio_o(30),O => gpio_bus_in(30),T => gpio_t(30),C => gpio_clk,PAD => WING_BH6 );
pin31: IOPAD port map(I => gpio_o(31),O => gpio_bus_in(31),T => gpio_t(31),C => gpio_clk,PAD => WING_BH7 );
pin32: IOPAD port map(I => gpio_o(32),O => gpio_bus_in(32),T => gpio_t(32),C => gpio_clk,PAD => WING_CL0 );
pin33: IOPAD port map(I => gpio_o(33),O => gpio_bus_in(33),T => gpio_t(33),C => gpio_clk,PAD => WING_CL1 );
pin34: IOPAD port map(I => gpio_o(34),O => gpio_bus_in(34),T => gpio_t(34),C => gpio_clk,PAD => WING_CL2 );
pin35: IOPAD port map(I => gpio_o(35),O => gpio_bus_in(35),T => gpio_t(35),C => gpio_clk,PAD => WING_CL3 );
pin36: IOPAD port map(I => gpio_o(36),O => gpio_bus_in(36),T => gpio_t(36),C => gpio_clk,PAD => WING_CL4 );
pin37: IOPAD port map(I => gpio_o(37),O => gpio_bus_in(37),T => gpio_t(37),C => gpio_clk,PAD => WING_CL5 );
pin38: IOPAD port map(I => gpio_o(38),O => gpio_bus_in(38),T => gpio_t(38),C => gpio_clk,PAD => WING_CL6 );
pin39: IOPAD port map(I => gpio_o(39),O => gpio_bus_in(39),T => gpio_t(39),C => gpio_clk,PAD => WING_CL7 );
pin40: IOPAD port map(I => gpio_o(40),O => gpio_bus_in(40),T => gpio_t(40),C => gpio_clk,PAD => WING_CH0 );
pin41: IOPAD port map(I => gpio_o(41),O => gpio_bus_in(41),T => gpio_t(41),C => gpio_clk,PAD => WING_CH1 );
pin42: IOPAD port map(I => gpio_o(42),O => gpio_bus_in(42),T => gpio_t(42),C => gpio_clk,PAD => WING_CH2 );
pin43: IOPAD port map(I => gpio_o(43),O => gpio_bus_in(43),T => gpio_t(43),C => gpio_clk,PAD => WING_CH3 );
pin44: IOPAD port map(I => gpio_o(44),O => gpio_bus_in(44),T => gpio_t(44),C => gpio_clk,PAD => WING_CH4 );
pin45: IOPAD port map(I => gpio_o(45),O => gpio_bus_in(45),T => gpio_t(45),C => gpio_clk,PAD => WING_CH5 );
pin46: IOPAD port map(I => gpio_o(46),O => gpio_bus_in(46),T => gpio_t(46),C => gpio_clk,PAD => WING_CH6 );
pin47: IOPAD port map(I => gpio_o(47),O => gpio_bus_in(47),T => gpio_t(47),C => gpio_clk,PAD => WING_CH7 );
-- ospics: OPAD port map ( I => gpio_bus_out.gpio_o(48), PAD => SPI_CS );
process(gpio_spp_read)
-- sigmadelta_spp_data,
-- timers_pwm,
-- spi2_mosi,spi2_sck)
begin
--gpio_spp_data <= (others => DontCareValue);
gpio_bus_in(97 downto 49) <= (others => DontCareValue);
-- gpio_bus_in.gpio_spp_data(0) <= platform_audio_sd; -- PPS0 : SIGMADELTA DATA
-- gpio_bus_in.gpio_spp_data(1) <= timers_pwm(0); -- PPS1 : TIMER0
-- gpio_bus_in.gpio_spp_data(2) <= timers_pwm(1); -- PPS2 : TIMER1
-- gpio_bus_in.gpio_spp_data(3) <= spi2_mosi; -- PPS3 : USPI MOSI
-- gpio_bus_in.gpio_spp_data(4) <= spi2_sck; -- PPS4 : USPI SCK
-- gpio_bus_in.gpio_spp_data(5) <= platform_audio_sd; -- PPS5 : SIGMADELTA1 DATA
-- gpio_bus_in.gpio_spp_data(6) <= uart2_tx; -- PPS6 : UART2 DATA
-- gpio_bus_in.gpio_spp_data(8) <= platform_audio_sd;
-- spi2_miso <= gpio_bus_out_record.gpio_spp_read(0); -- PPS0 : USPI MISO
-- uart2_rx <= gpio_bus_out_record.gpio_spp_read(1); -- PPS0 : USPI MISO
end process;
end BEHAVIORAL;
|
--------------------------------------------------------------------------------
-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version : 14.3
-- \ \ Application :
-- / / Filename : xil_10080_19
-- /___/ /\ Timestamp : 02/08/2013 16:21:11
-- \ \ / \
-- \___\/\___\
--
--Command:
--Design Name:
-- The Papilio Default Pinout device defines the pins for a Papilio board that does not have a MegaWing attached to it.
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
library UNISIM;
use UNISIM.Vcomponents.ALL;
library board;
use board.zpupkg.all;
use board.zpuinopkg.all;
use board.zpuino_config.all;
use board.zpu_config.all;
library zpuino;
use zpuino.pad.all;
use zpuino.papilio_pkg.all;
-- Unfortunately the Xilinx Schematic Editor does not support records, so we have to put all wishbone signals into one array.
-- This is a little cumbersome but is better then dealing with all the signals in the schematic editor.
-- This is what the original record base approach looked like:
--
-- type gpio_bus_in_type is record
-- gpio_i: std_logic_vector(48 downto 0);
-- gpio_spp_data: std_logic_vector(48 downto 0);
-- end record;
--
-- type gpio_bus_out_type is record
-- gpio_clk: std_logic;
-- gpio_o: std_logic_vector(48 downto 0);
-- gpio_t: std_logic_vector(48 downto 0);
-- gpio_spp_read: std_logic_vector(48 downto 0);
-- end record;
--
-- Turning them into an array looks like this:
--
-- gpio_bus_in : in std_logic_vector(97 downto 0);
--
-- gpio_bus_in(97 downto 49) <= gpio_i;
-- gpio_bus_in(48 downto 0) <= gpio_bus_in_record.gpio_spp_data;
--
-- gpio_bus_out : out std_logic_vector(146 downto 0);
--
-- gpio_o <= gpio_bus_out(146 downto 98);
-- gpio_t <= gpio_bus_out(97 downto 49);
-- gpio_bus_out_record.gpio_spp_read <= gpio_bus_out(48 downto 0);
entity Papilio_Default_Pinout is
port (
-- gpio_clk: in std_logic;
-- gpio_o: in std_logic_vector(48 downto 0);
-- gpio_t: in std_logic_vector(48 downto 0);
-- gpio_i: out std_logic_vector(48 downto 0);
--
-- gpio_spp_data: out std_logic_vector(48 downto 0);
-- gpio_spp_read: in std_logic_vector(48 downto 0);
gpio_bus_in : out std_logic_vector(97 downto 0);
gpio_bus_out : in std_logic_vector(147 downto 0);
WING_AH0 : inout std_logic;
WING_AH1 : inout std_logic;
WING_AH2 : inout std_logic;
WING_AH3 : inout std_logic;
WING_AH4 : inout std_logic;
WING_AH5 : inout std_logic;
WING_AH6 : inout std_logic;
WING_AH7 : inout std_logic;
WING_AL0 : inout std_logic;
WING_AL1 : inout std_logic;
WING_AL2 : inout std_logic;
WING_AL3 : inout std_logic;
WING_AL4 : inout std_logic;
WING_AL5 : inout std_logic;
WING_AL6 : inout std_logic;
WING_AL7 : inout std_logic;
WING_BH0 : inout std_logic;
WING_BH1 : inout std_logic;
WING_BH2 : inout std_logic;
WING_BH3 : inout std_logic;
WING_BH4 : inout std_logic;
WING_BH5 : inout std_logic;
WING_BH6 : inout std_logic;
WING_BH7 : inout std_logic;
WING_BL0 : inout std_logic;
WING_BL1 : inout std_logic;
WING_BL2 : inout std_logic;
WING_BL3 : inout std_logic;
WING_BL4 : inout std_logic;
WING_BL5 : inout std_logic;
WING_BL6 : inout std_logic;
WING_BL7 : inout std_logic;
WING_CH0 : inout std_logic;
WING_CH1 : inout std_logic;
WING_CH2 : inout std_logic;
WING_CH3 : inout std_logic;
WING_CH4 : inout std_logic;
WING_CH5 : inout std_logic;
WING_CH6 : inout std_logic;
WING_CH7 : inout std_logic;
WING_CL0 : inout std_logic;
WING_CL1 : inout std_logic;
WING_CL2 : inout std_logic;
WING_CL3 : inout std_logic;
WING_CL4 : inout std_logic;
WING_CL5 : inout std_logic;
WING_CL6 : inout std_logic;
WING_CL7 : inout std_logic
);
end Papilio_Default_Pinout;
architecture BEHAVIORAL of Papilio_Default_Pinout is
-- signal gpio_bus_out.gpio_o: std_logic_vector(zpuino_gpio_count-1 downto 0);
-- signal gpio_bus_out.gpio_t: std_logic_vector(zpuino_gpio_count-1 downto 0);
-- signal gpio_bus_in.gpio_i: std_logic_vector(zpuino_gpio_count-1 downto 0);
--
-- -- SPP signal is one more than GPIO count
-- signal gpio_bus_in.gpio_spp_data: std_logic_vector(zpuino_gpio_count-1 downto 0);
-- signal gpio_bus_out.gpio_spp_read: std_logic_vector(zpuino_gpio_count-1 downto 0);
--
-- constant spp_cap_in: std_logic_vector(zpuino_gpio_count-1 downto 0) :=
-- "0" &
-- "1111111111111111" &
-- "1111111111111111" &
-- "1111111111111111";
-- constant spp_cap_out: std_logic_vector(zpuino_gpio_count-1 downto 0) :=
-- "0" &
-- "1111111111111111" &
-- "1111111111111111" &
-- "1111111111111111";
-- signal gpio_bus_in_record : gpio_bus_in_type;
-- signal gpio_bus_out_record : gpio_bus_out_type;
signal gpio_o: std_logic_vector(48 downto 0);
signal gpio_t: std_logic_vector(48 downto 0);
signal gpio_i: std_logic_vector(48 downto 0);
signal gpio_spp_data: std_logic_vector(48 downto 0);
signal gpio_spp_read: std_logic_vector(48 downto 0);
signal gpio_clk: std_logic;
begin
--Unpack the signal array into a record so the modules code is easier to understand.
--gpio_bus_in(97 downto 49) <= gpio_spp_data;
--gpio_bus_in(48 downto 0) <= gpio_i;
gpio_clk <= gpio_bus_out(147);
gpio_o <= gpio_bus_out(146 downto 98);
gpio_t <= gpio_bus_out(97 downto 49);
gpio_spp_read <= gpio_bus_out(48 downto 0);
-- gpio_bus_in(97 downto 49) <= gpio_i;
-- gpio_bus_in(48 downto 0) <= gpio_bus_in_record.gpio_spp_data;
-- gpio_clk <= gpio_bus_out(147);
-- gpio_o <= gpio_bus_out(146 downto 98);
-- gpio_t <= gpio_bus_out(97 downto 49);
-- gpio_bus_out_record.gpio_spp_read <= gpio_bus_out(48 downto 0);
-- gpio_bus_in.gpio_inst: zpuino_gpio
-- generic map (
-- gpio_count => zpuino_gpio_count
-- )
-- port map (
-- gpio_bus_out.gpio_clk => gpio_bus_out.gpio_clk,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => wb_dat_o,
-- wb_dat_i => wb_dat_i,
-- wb_adr_i => wb_adr_i,
-- wb_we_i => wb_we_i,
-- wb_cyc_i => wb_cyc_i,
-- wb_stb_i => wb_stb_i,
-- wb_ack_o => wb_ack_o,
-- wb_inta_o => wb_inta_o,
--
-- spp_data => gpio_bus_in.gpio_spp_data,
-- spp_read => gpio_bus_out.gpio_spp_read,
--
-- gpio_bus_in.gpio_i => gpio_bus_in.gpio_i,
-- gpio_bus_out.gpio_t => gpio_bus_out.gpio_t,
-- gpio_bus_out.gpio_o => gpio_bus_out.gpio_o,
-- spp_cap_in => spp_cap_in,
-- spp_cap_out => spp_cap_out
-- );
pin00: IOPAD port map(I => gpio_o(0), O => gpio_bus_in(0), T => gpio_t(0), C => gpio_clk,PAD => WING_AL0 );
pin01: IOPAD port map(I => gpio_o(1), O => gpio_bus_in(1), T => gpio_t(1), C => gpio_clk,PAD => WING_AL1 );
pin02: IOPAD port map(I => gpio_o(2), O => gpio_bus_in(2), T => gpio_t(2), C => gpio_clk,PAD => WING_AL2 );
pin03: IOPAD port map(I => gpio_o(3), O => gpio_bus_in(3), T => gpio_t(3), C => gpio_clk,PAD => WING_AL3 );
pin04: IOPAD port map(I => gpio_o(4), O => gpio_bus_in(4), T => gpio_t(4), C => gpio_clk,PAD => WING_AL4 );
pin05: IOPAD port map(I => gpio_o(5), O => gpio_bus_in(5), T => gpio_t(5), C => gpio_clk,PAD => WING_AL5 );
pin06: IOPAD port map(I => gpio_o(6), O => gpio_bus_in(6), T => gpio_t(6), C => gpio_clk,PAD => WING_AL6 );
pin07: IOPAD port map(I => gpio_o(7), O => gpio_bus_in(7), T => gpio_t(7), C => gpio_clk,PAD => WING_AL7 );
pin08: IOPAD port map(I => gpio_o(8), O => gpio_bus_in(8), T => gpio_t(8), C => gpio_clk,PAD => WING_AH0 );
pin09: IOPAD port map(I => gpio_o(9), O => gpio_bus_in(9), T => gpio_t(9), C => gpio_clk,PAD => WING_AH1 );
pin10: IOPAD port map(I => gpio_o(10),O => gpio_bus_in(10),T => gpio_t(10),C => gpio_clk,PAD => WING_AH2 );
pin11: IOPAD port map(I => gpio_o(11),O => gpio_bus_in(11),T => gpio_t(11),C => gpio_clk,PAD => WING_AH3 );
pin12: IOPAD port map(I => gpio_o(12),O => gpio_bus_in(12),T => gpio_t(12),C => gpio_clk,PAD => WING_AH4 );
pin13: IOPAD port map(I => gpio_o(13),O => gpio_bus_in(13),T => gpio_t(13),C => gpio_clk,PAD => WING_AH5 );
pin14: IOPAD port map(I => gpio_o(14),O => gpio_bus_in(14),T => gpio_t(14),C => gpio_clk,PAD => WING_AH6 );
pin15: IOPAD port map(I => gpio_o(15),O => gpio_bus_in(15),T => gpio_t(15),C => gpio_clk,PAD => WING_AH7 );
pin16: IOPAD port map(I => gpio_o(16),O => gpio_bus_in(16),T => gpio_t(16),C => gpio_clk,PAD => WING_BL0 );
pin17: IOPAD port map(I => gpio_o(17),O => gpio_bus_in(17),T => gpio_t(17),C => gpio_clk,PAD => WING_BL1 );
pin18: IOPAD port map(I => gpio_o(18),O => gpio_bus_in(18),T => gpio_t(18),C => gpio_clk,PAD => WING_BL2 );
pin19: IOPAD port map(I => gpio_o(19),O => gpio_bus_in(19),T => gpio_t(19),C => gpio_clk,PAD => WING_BL3 );
pin20: IOPAD port map(I => gpio_o(20),O => gpio_bus_in(20),T => gpio_t(20),C => gpio_clk,PAD => WING_BL4 );
pin21: IOPAD port map(I => gpio_o(21),O => gpio_bus_in(21),T => gpio_t(21),C => gpio_clk,PAD => WING_BL5 );
pin22: IOPAD port map(I => gpio_o(22),O => gpio_bus_in(22),T => gpio_t(22),C => gpio_clk,PAD => WING_BL6 );
pin23: IOPAD port map(I => gpio_o(23),O => gpio_bus_in(23),T => gpio_t(23),C => gpio_clk,PAD => WING_BL7 );
pin24: IOPAD port map(I => gpio_o(24),O => gpio_bus_in(24),T => gpio_t(24),C => gpio_clk,PAD => WING_BH0 );
pin25: IOPAD port map(I => gpio_o(25),O => gpio_bus_in(25),T => gpio_t(25),C => gpio_clk,PAD => WING_BH1 );
pin26: IOPAD port map(I => gpio_o(26),O => gpio_bus_in(26),T => gpio_t(26),C => gpio_clk,PAD => WING_BH2 );
pin27: IOPAD port map(I => gpio_o(27),O => gpio_bus_in(27),T => gpio_t(27),C => gpio_clk,PAD => WING_BH3 );
pin28: IOPAD port map(I => gpio_o(28),O => gpio_bus_in(28),T => gpio_t(28),C => gpio_clk,PAD => WING_BH4 );
pin29: IOPAD port map(I => gpio_o(29),O => gpio_bus_in(29),T => gpio_t(29),C => gpio_clk,PAD => WING_BH5 );
pin30: IOPAD port map(I => gpio_o(30),O => gpio_bus_in(30),T => gpio_t(30),C => gpio_clk,PAD => WING_BH6 );
pin31: IOPAD port map(I => gpio_o(31),O => gpio_bus_in(31),T => gpio_t(31),C => gpio_clk,PAD => WING_BH7 );
pin32: IOPAD port map(I => gpio_o(32),O => gpio_bus_in(32),T => gpio_t(32),C => gpio_clk,PAD => WING_CL0 );
pin33: IOPAD port map(I => gpio_o(33),O => gpio_bus_in(33),T => gpio_t(33),C => gpio_clk,PAD => WING_CL1 );
pin34: IOPAD port map(I => gpio_o(34),O => gpio_bus_in(34),T => gpio_t(34),C => gpio_clk,PAD => WING_CL2 );
pin35: IOPAD port map(I => gpio_o(35),O => gpio_bus_in(35),T => gpio_t(35),C => gpio_clk,PAD => WING_CL3 );
pin36: IOPAD port map(I => gpio_o(36),O => gpio_bus_in(36),T => gpio_t(36),C => gpio_clk,PAD => WING_CL4 );
pin37: IOPAD port map(I => gpio_o(37),O => gpio_bus_in(37),T => gpio_t(37),C => gpio_clk,PAD => WING_CL5 );
pin38: IOPAD port map(I => gpio_o(38),O => gpio_bus_in(38),T => gpio_t(38),C => gpio_clk,PAD => WING_CL6 );
pin39: IOPAD port map(I => gpio_o(39),O => gpio_bus_in(39),T => gpio_t(39),C => gpio_clk,PAD => WING_CL7 );
pin40: IOPAD port map(I => gpio_o(40),O => gpio_bus_in(40),T => gpio_t(40),C => gpio_clk,PAD => WING_CH0 );
pin41: IOPAD port map(I => gpio_o(41),O => gpio_bus_in(41),T => gpio_t(41),C => gpio_clk,PAD => WING_CH1 );
pin42: IOPAD port map(I => gpio_o(42),O => gpio_bus_in(42),T => gpio_t(42),C => gpio_clk,PAD => WING_CH2 );
pin43: IOPAD port map(I => gpio_o(43),O => gpio_bus_in(43),T => gpio_t(43),C => gpio_clk,PAD => WING_CH3 );
pin44: IOPAD port map(I => gpio_o(44),O => gpio_bus_in(44),T => gpio_t(44),C => gpio_clk,PAD => WING_CH4 );
pin45: IOPAD port map(I => gpio_o(45),O => gpio_bus_in(45),T => gpio_t(45),C => gpio_clk,PAD => WING_CH5 );
pin46: IOPAD port map(I => gpio_o(46),O => gpio_bus_in(46),T => gpio_t(46),C => gpio_clk,PAD => WING_CH6 );
pin47: IOPAD port map(I => gpio_o(47),O => gpio_bus_in(47),T => gpio_t(47),C => gpio_clk,PAD => WING_CH7 );
-- ospics: OPAD port map ( I => gpio_bus_out.gpio_o(48), PAD => SPI_CS );
process(gpio_spp_read)
-- sigmadelta_spp_data,
-- timers_pwm,
-- spi2_mosi,spi2_sck)
begin
--gpio_spp_data <= (others => DontCareValue);
gpio_bus_in(97 downto 49) <= (others => DontCareValue);
-- gpio_bus_in.gpio_spp_data(0) <= platform_audio_sd; -- PPS0 : SIGMADELTA DATA
-- gpio_bus_in.gpio_spp_data(1) <= timers_pwm(0); -- PPS1 : TIMER0
-- gpio_bus_in.gpio_spp_data(2) <= timers_pwm(1); -- PPS2 : TIMER1
-- gpio_bus_in.gpio_spp_data(3) <= spi2_mosi; -- PPS3 : USPI MOSI
-- gpio_bus_in.gpio_spp_data(4) <= spi2_sck; -- PPS4 : USPI SCK
-- gpio_bus_in.gpio_spp_data(5) <= platform_audio_sd; -- PPS5 : SIGMADELTA1 DATA
-- gpio_bus_in.gpio_spp_data(6) <= uart2_tx; -- PPS6 : UART2 DATA
-- gpio_bus_in.gpio_spp_data(8) <= platform_audio_sd;
-- spi2_miso <= gpio_bus_out_record.gpio_spp_read(0); -- PPS0 : USPI MISO
-- uart2_rx <= gpio_bus_out_record.gpio_spp_read(1); -- PPS0 : USPI MISO
end process;
end BEHAVIORAL;
|
--------------------------------------------------------------------------------
-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version : 14.3
-- \ \ Application :
-- / / Filename : xil_10080_19
-- /___/ /\ Timestamp : 02/08/2013 16:21:11
-- \ \ / \
-- \___\/\___\
--
--Command:
--Design Name:
-- The Papilio Default Pinout device defines the pins for a Papilio board that does not have a MegaWing attached to it.
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
library UNISIM;
use UNISIM.Vcomponents.ALL;
library board;
use board.zpupkg.all;
use board.zpuinopkg.all;
use board.zpuino_config.all;
use board.zpu_config.all;
library zpuino;
use zpuino.pad.all;
use zpuino.papilio_pkg.all;
-- Unfortunately the Xilinx Schematic Editor does not support records, so we have to put all wishbone signals into one array.
-- This is a little cumbersome but is better then dealing with all the signals in the schematic editor.
-- This is what the original record base approach looked like:
--
-- type gpio_bus_in_type is record
-- gpio_i: std_logic_vector(48 downto 0);
-- gpio_spp_data: std_logic_vector(48 downto 0);
-- end record;
--
-- type gpio_bus_out_type is record
-- gpio_clk: std_logic;
-- gpio_o: std_logic_vector(48 downto 0);
-- gpio_t: std_logic_vector(48 downto 0);
-- gpio_spp_read: std_logic_vector(48 downto 0);
-- end record;
--
-- Turning them into an array looks like this:
--
-- gpio_bus_in : in std_logic_vector(97 downto 0);
--
-- gpio_bus_in(97 downto 49) <= gpio_i;
-- gpio_bus_in(48 downto 0) <= gpio_bus_in_record.gpio_spp_data;
--
-- gpio_bus_out : out std_logic_vector(146 downto 0);
--
-- gpio_o <= gpio_bus_out(146 downto 98);
-- gpio_t <= gpio_bus_out(97 downto 49);
-- gpio_bus_out_record.gpio_spp_read <= gpio_bus_out(48 downto 0);
entity Papilio_Default_Pinout is
port (
-- gpio_clk: in std_logic;
-- gpio_o: in std_logic_vector(48 downto 0);
-- gpio_t: in std_logic_vector(48 downto 0);
-- gpio_i: out std_logic_vector(48 downto 0);
--
-- gpio_spp_data: out std_logic_vector(48 downto 0);
-- gpio_spp_read: in std_logic_vector(48 downto 0);
gpio_bus_in : out std_logic_vector(97 downto 0);
gpio_bus_out : in std_logic_vector(147 downto 0);
WING_AH0 : inout std_logic;
WING_AH1 : inout std_logic;
WING_AH2 : inout std_logic;
WING_AH3 : inout std_logic;
WING_AH4 : inout std_logic;
WING_AH5 : inout std_logic;
WING_AH6 : inout std_logic;
WING_AH7 : inout std_logic;
WING_AL0 : inout std_logic;
WING_AL1 : inout std_logic;
WING_AL2 : inout std_logic;
WING_AL3 : inout std_logic;
WING_AL4 : inout std_logic;
WING_AL5 : inout std_logic;
WING_AL6 : inout std_logic;
WING_AL7 : inout std_logic;
WING_BH0 : inout std_logic;
WING_BH1 : inout std_logic;
WING_BH2 : inout std_logic;
WING_BH3 : inout std_logic;
WING_BH4 : inout std_logic;
WING_BH5 : inout std_logic;
WING_BH6 : inout std_logic;
WING_BH7 : inout std_logic;
WING_BL0 : inout std_logic;
WING_BL1 : inout std_logic;
WING_BL2 : inout std_logic;
WING_BL3 : inout std_logic;
WING_BL4 : inout std_logic;
WING_BL5 : inout std_logic;
WING_BL6 : inout std_logic;
WING_BL7 : inout std_logic;
WING_CH0 : inout std_logic;
WING_CH1 : inout std_logic;
WING_CH2 : inout std_logic;
WING_CH3 : inout std_logic;
WING_CH4 : inout std_logic;
WING_CH5 : inout std_logic;
WING_CH6 : inout std_logic;
WING_CH7 : inout std_logic;
WING_CL0 : inout std_logic;
WING_CL1 : inout std_logic;
WING_CL2 : inout std_logic;
WING_CL3 : inout std_logic;
WING_CL4 : inout std_logic;
WING_CL5 : inout std_logic;
WING_CL6 : inout std_logic;
WING_CL7 : inout std_logic
);
end Papilio_Default_Pinout;
architecture BEHAVIORAL of Papilio_Default_Pinout is
-- signal gpio_bus_out.gpio_o: std_logic_vector(zpuino_gpio_count-1 downto 0);
-- signal gpio_bus_out.gpio_t: std_logic_vector(zpuino_gpio_count-1 downto 0);
-- signal gpio_bus_in.gpio_i: std_logic_vector(zpuino_gpio_count-1 downto 0);
--
-- -- SPP signal is one more than GPIO count
-- signal gpio_bus_in.gpio_spp_data: std_logic_vector(zpuino_gpio_count-1 downto 0);
-- signal gpio_bus_out.gpio_spp_read: std_logic_vector(zpuino_gpio_count-1 downto 0);
--
-- constant spp_cap_in: std_logic_vector(zpuino_gpio_count-1 downto 0) :=
-- "0" &
-- "1111111111111111" &
-- "1111111111111111" &
-- "1111111111111111";
-- constant spp_cap_out: std_logic_vector(zpuino_gpio_count-1 downto 0) :=
-- "0" &
-- "1111111111111111" &
-- "1111111111111111" &
-- "1111111111111111";
-- signal gpio_bus_in_record : gpio_bus_in_type;
-- signal gpio_bus_out_record : gpio_bus_out_type;
signal gpio_o: std_logic_vector(48 downto 0);
signal gpio_t: std_logic_vector(48 downto 0);
signal gpio_i: std_logic_vector(48 downto 0);
signal gpio_spp_data: std_logic_vector(48 downto 0);
signal gpio_spp_read: std_logic_vector(48 downto 0);
signal gpio_clk: std_logic;
begin
--Unpack the signal array into a record so the modules code is easier to understand.
--gpio_bus_in(97 downto 49) <= gpio_spp_data;
--gpio_bus_in(48 downto 0) <= gpio_i;
gpio_clk <= gpio_bus_out(147);
gpio_o <= gpio_bus_out(146 downto 98);
gpio_t <= gpio_bus_out(97 downto 49);
gpio_spp_read <= gpio_bus_out(48 downto 0);
-- gpio_bus_in(97 downto 49) <= gpio_i;
-- gpio_bus_in(48 downto 0) <= gpio_bus_in_record.gpio_spp_data;
-- gpio_clk <= gpio_bus_out(147);
-- gpio_o <= gpio_bus_out(146 downto 98);
-- gpio_t <= gpio_bus_out(97 downto 49);
-- gpio_bus_out_record.gpio_spp_read <= gpio_bus_out(48 downto 0);
-- gpio_bus_in.gpio_inst: zpuino_gpio
-- generic map (
-- gpio_count => zpuino_gpio_count
-- )
-- port map (
-- gpio_bus_out.gpio_clk => gpio_bus_out.gpio_clk,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => wb_dat_o,
-- wb_dat_i => wb_dat_i,
-- wb_adr_i => wb_adr_i,
-- wb_we_i => wb_we_i,
-- wb_cyc_i => wb_cyc_i,
-- wb_stb_i => wb_stb_i,
-- wb_ack_o => wb_ack_o,
-- wb_inta_o => wb_inta_o,
--
-- spp_data => gpio_bus_in.gpio_spp_data,
-- spp_read => gpio_bus_out.gpio_spp_read,
--
-- gpio_bus_in.gpio_i => gpio_bus_in.gpio_i,
-- gpio_bus_out.gpio_t => gpio_bus_out.gpio_t,
-- gpio_bus_out.gpio_o => gpio_bus_out.gpio_o,
-- spp_cap_in => spp_cap_in,
-- spp_cap_out => spp_cap_out
-- );
pin00: IOPAD port map(I => gpio_o(0), O => gpio_bus_in(0), T => gpio_t(0), C => gpio_clk,PAD => WING_AL0 );
pin01: IOPAD port map(I => gpio_o(1), O => gpio_bus_in(1), T => gpio_t(1), C => gpio_clk,PAD => WING_AL1 );
pin02: IOPAD port map(I => gpio_o(2), O => gpio_bus_in(2), T => gpio_t(2), C => gpio_clk,PAD => WING_AL2 );
pin03: IOPAD port map(I => gpio_o(3), O => gpio_bus_in(3), T => gpio_t(3), C => gpio_clk,PAD => WING_AL3 );
pin04: IOPAD port map(I => gpio_o(4), O => gpio_bus_in(4), T => gpio_t(4), C => gpio_clk,PAD => WING_AL4 );
pin05: IOPAD port map(I => gpio_o(5), O => gpio_bus_in(5), T => gpio_t(5), C => gpio_clk,PAD => WING_AL5 );
pin06: IOPAD port map(I => gpio_o(6), O => gpio_bus_in(6), T => gpio_t(6), C => gpio_clk,PAD => WING_AL6 );
pin07: IOPAD port map(I => gpio_o(7), O => gpio_bus_in(7), T => gpio_t(7), C => gpio_clk,PAD => WING_AL7 );
pin08: IOPAD port map(I => gpio_o(8), O => gpio_bus_in(8), T => gpio_t(8), C => gpio_clk,PAD => WING_AH0 );
pin09: IOPAD port map(I => gpio_o(9), O => gpio_bus_in(9), T => gpio_t(9), C => gpio_clk,PAD => WING_AH1 );
pin10: IOPAD port map(I => gpio_o(10),O => gpio_bus_in(10),T => gpio_t(10),C => gpio_clk,PAD => WING_AH2 );
pin11: IOPAD port map(I => gpio_o(11),O => gpio_bus_in(11),T => gpio_t(11),C => gpio_clk,PAD => WING_AH3 );
pin12: IOPAD port map(I => gpio_o(12),O => gpio_bus_in(12),T => gpio_t(12),C => gpio_clk,PAD => WING_AH4 );
pin13: IOPAD port map(I => gpio_o(13),O => gpio_bus_in(13),T => gpio_t(13),C => gpio_clk,PAD => WING_AH5 );
pin14: IOPAD port map(I => gpio_o(14),O => gpio_bus_in(14),T => gpio_t(14),C => gpio_clk,PAD => WING_AH6 );
pin15: IOPAD port map(I => gpio_o(15),O => gpio_bus_in(15),T => gpio_t(15),C => gpio_clk,PAD => WING_AH7 );
pin16: IOPAD port map(I => gpio_o(16),O => gpio_bus_in(16),T => gpio_t(16),C => gpio_clk,PAD => WING_BL0 );
pin17: IOPAD port map(I => gpio_o(17),O => gpio_bus_in(17),T => gpio_t(17),C => gpio_clk,PAD => WING_BL1 );
pin18: IOPAD port map(I => gpio_o(18),O => gpio_bus_in(18),T => gpio_t(18),C => gpio_clk,PAD => WING_BL2 );
pin19: IOPAD port map(I => gpio_o(19),O => gpio_bus_in(19),T => gpio_t(19),C => gpio_clk,PAD => WING_BL3 );
pin20: IOPAD port map(I => gpio_o(20),O => gpio_bus_in(20),T => gpio_t(20),C => gpio_clk,PAD => WING_BL4 );
pin21: IOPAD port map(I => gpio_o(21),O => gpio_bus_in(21),T => gpio_t(21),C => gpio_clk,PAD => WING_BL5 );
pin22: IOPAD port map(I => gpio_o(22),O => gpio_bus_in(22),T => gpio_t(22),C => gpio_clk,PAD => WING_BL6 );
pin23: IOPAD port map(I => gpio_o(23),O => gpio_bus_in(23),T => gpio_t(23),C => gpio_clk,PAD => WING_BL7 );
pin24: IOPAD port map(I => gpio_o(24),O => gpio_bus_in(24),T => gpio_t(24),C => gpio_clk,PAD => WING_BH0 );
pin25: IOPAD port map(I => gpio_o(25),O => gpio_bus_in(25),T => gpio_t(25),C => gpio_clk,PAD => WING_BH1 );
pin26: IOPAD port map(I => gpio_o(26),O => gpio_bus_in(26),T => gpio_t(26),C => gpio_clk,PAD => WING_BH2 );
pin27: IOPAD port map(I => gpio_o(27),O => gpio_bus_in(27),T => gpio_t(27),C => gpio_clk,PAD => WING_BH3 );
pin28: IOPAD port map(I => gpio_o(28),O => gpio_bus_in(28),T => gpio_t(28),C => gpio_clk,PAD => WING_BH4 );
pin29: IOPAD port map(I => gpio_o(29),O => gpio_bus_in(29),T => gpio_t(29),C => gpio_clk,PAD => WING_BH5 );
pin30: IOPAD port map(I => gpio_o(30),O => gpio_bus_in(30),T => gpio_t(30),C => gpio_clk,PAD => WING_BH6 );
pin31: IOPAD port map(I => gpio_o(31),O => gpio_bus_in(31),T => gpio_t(31),C => gpio_clk,PAD => WING_BH7 );
pin32: IOPAD port map(I => gpio_o(32),O => gpio_bus_in(32),T => gpio_t(32),C => gpio_clk,PAD => WING_CL0 );
pin33: IOPAD port map(I => gpio_o(33),O => gpio_bus_in(33),T => gpio_t(33),C => gpio_clk,PAD => WING_CL1 );
pin34: IOPAD port map(I => gpio_o(34),O => gpio_bus_in(34),T => gpio_t(34),C => gpio_clk,PAD => WING_CL2 );
pin35: IOPAD port map(I => gpio_o(35),O => gpio_bus_in(35),T => gpio_t(35),C => gpio_clk,PAD => WING_CL3 );
pin36: IOPAD port map(I => gpio_o(36),O => gpio_bus_in(36),T => gpio_t(36),C => gpio_clk,PAD => WING_CL4 );
pin37: IOPAD port map(I => gpio_o(37),O => gpio_bus_in(37),T => gpio_t(37),C => gpio_clk,PAD => WING_CL5 );
pin38: IOPAD port map(I => gpio_o(38),O => gpio_bus_in(38),T => gpio_t(38),C => gpio_clk,PAD => WING_CL6 );
pin39: IOPAD port map(I => gpio_o(39),O => gpio_bus_in(39),T => gpio_t(39),C => gpio_clk,PAD => WING_CL7 );
pin40: IOPAD port map(I => gpio_o(40),O => gpio_bus_in(40),T => gpio_t(40),C => gpio_clk,PAD => WING_CH0 );
pin41: IOPAD port map(I => gpio_o(41),O => gpio_bus_in(41),T => gpio_t(41),C => gpio_clk,PAD => WING_CH1 );
pin42: IOPAD port map(I => gpio_o(42),O => gpio_bus_in(42),T => gpio_t(42),C => gpio_clk,PAD => WING_CH2 );
pin43: IOPAD port map(I => gpio_o(43),O => gpio_bus_in(43),T => gpio_t(43),C => gpio_clk,PAD => WING_CH3 );
pin44: IOPAD port map(I => gpio_o(44),O => gpio_bus_in(44),T => gpio_t(44),C => gpio_clk,PAD => WING_CH4 );
pin45: IOPAD port map(I => gpio_o(45),O => gpio_bus_in(45),T => gpio_t(45),C => gpio_clk,PAD => WING_CH5 );
pin46: IOPAD port map(I => gpio_o(46),O => gpio_bus_in(46),T => gpio_t(46),C => gpio_clk,PAD => WING_CH6 );
pin47: IOPAD port map(I => gpio_o(47),O => gpio_bus_in(47),T => gpio_t(47),C => gpio_clk,PAD => WING_CH7 );
-- ospics: OPAD port map ( I => gpio_bus_out.gpio_o(48), PAD => SPI_CS );
process(gpio_spp_read)
-- sigmadelta_spp_data,
-- timers_pwm,
-- spi2_mosi,spi2_sck)
begin
--gpio_spp_data <= (others => DontCareValue);
gpio_bus_in(97 downto 49) <= (others => DontCareValue);
-- gpio_bus_in.gpio_spp_data(0) <= platform_audio_sd; -- PPS0 : SIGMADELTA DATA
-- gpio_bus_in.gpio_spp_data(1) <= timers_pwm(0); -- PPS1 : TIMER0
-- gpio_bus_in.gpio_spp_data(2) <= timers_pwm(1); -- PPS2 : TIMER1
-- gpio_bus_in.gpio_spp_data(3) <= spi2_mosi; -- PPS3 : USPI MOSI
-- gpio_bus_in.gpio_spp_data(4) <= spi2_sck; -- PPS4 : USPI SCK
-- gpio_bus_in.gpio_spp_data(5) <= platform_audio_sd; -- PPS5 : SIGMADELTA1 DATA
-- gpio_bus_in.gpio_spp_data(6) <= uart2_tx; -- PPS6 : UART2 DATA
-- gpio_bus_in.gpio_spp_data(8) <= platform_audio_sd;
-- spi2_miso <= gpio_bus_out_record.gpio_spp_read(0); -- PPS0 : USPI MISO
-- uart2_rx <= gpio_bus_out_record.gpio_spp_read(1); -- PPS0 : USPI MISO
end process;
end BEHAVIORAL;
|
--------------------------------------------------------------------------------
-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version : 14.3
-- \ \ Application :
-- / / Filename : xil_10080_19
-- /___/ /\ Timestamp : 02/08/2013 16:21:11
-- \ \ / \
-- \___\/\___\
--
--Command:
--Design Name:
-- The Papilio Default Pinout device defines the pins for a Papilio board that does not have a MegaWing attached to it.
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
library UNISIM;
use UNISIM.Vcomponents.ALL;
library board;
use board.zpupkg.all;
use board.zpuinopkg.all;
use board.zpuino_config.all;
use board.zpu_config.all;
library zpuino;
use zpuino.pad.all;
use zpuino.papilio_pkg.all;
-- Unfortunately the Xilinx Schematic Editor does not support records, so we have to put all wishbone signals into one array.
-- This is a little cumbersome but is better then dealing with all the signals in the schematic editor.
-- This is what the original record base approach looked like:
--
-- type gpio_bus_in_type is record
-- gpio_i: std_logic_vector(48 downto 0);
-- gpio_spp_data: std_logic_vector(48 downto 0);
-- end record;
--
-- type gpio_bus_out_type is record
-- gpio_clk: std_logic;
-- gpio_o: std_logic_vector(48 downto 0);
-- gpio_t: std_logic_vector(48 downto 0);
-- gpio_spp_read: std_logic_vector(48 downto 0);
-- end record;
--
-- Turning them into an array looks like this:
--
-- gpio_bus_in : in std_logic_vector(97 downto 0);
--
-- gpio_bus_in(97 downto 49) <= gpio_i;
-- gpio_bus_in(48 downto 0) <= gpio_bus_in_record.gpio_spp_data;
--
-- gpio_bus_out : out std_logic_vector(146 downto 0);
--
-- gpio_o <= gpio_bus_out(146 downto 98);
-- gpio_t <= gpio_bus_out(97 downto 49);
-- gpio_bus_out_record.gpio_spp_read <= gpio_bus_out(48 downto 0);
entity Papilio_Default_Pinout is
port (
-- gpio_clk: in std_logic;
-- gpio_o: in std_logic_vector(48 downto 0);
-- gpio_t: in std_logic_vector(48 downto 0);
-- gpio_i: out std_logic_vector(48 downto 0);
--
-- gpio_spp_data: out std_logic_vector(48 downto 0);
-- gpio_spp_read: in std_logic_vector(48 downto 0);
gpio_bus_in : out std_logic_vector(97 downto 0);
gpio_bus_out : in std_logic_vector(147 downto 0);
WING_AH0 : inout std_logic;
WING_AH1 : inout std_logic;
WING_AH2 : inout std_logic;
WING_AH3 : inout std_logic;
WING_AH4 : inout std_logic;
WING_AH5 : inout std_logic;
WING_AH6 : inout std_logic;
WING_AH7 : inout std_logic;
WING_AL0 : inout std_logic;
WING_AL1 : inout std_logic;
WING_AL2 : inout std_logic;
WING_AL3 : inout std_logic;
WING_AL4 : inout std_logic;
WING_AL5 : inout std_logic;
WING_AL6 : inout std_logic;
WING_AL7 : inout std_logic;
WING_BH0 : inout std_logic;
WING_BH1 : inout std_logic;
WING_BH2 : inout std_logic;
WING_BH3 : inout std_logic;
WING_BH4 : inout std_logic;
WING_BH5 : inout std_logic;
WING_BH6 : inout std_logic;
WING_BH7 : inout std_logic;
WING_BL0 : inout std_logic;
WING_BL1 : inout std_logic;
WING_BL2 : inout std_logic;
WING_BL3 : inout std_logic;
WING_BL4 : inout std_logic;
WING_BL5 : inout std_logic;
WING_BL6 : inout std_logic;
WING_BL7 : inout std_logic;
WING_CH0 : inout std_logic;
WING_CH1 : inout std_logic;
WING_CH2 : inout std_logic;
WING_CH3 : inout std_logic;
WING_CH4 : inout std_logic;
WING_CH5 : inout std_logic;
WING_CH6 : inout std_logic;
WING_CH7 : inout std_logic;
WING_CL0 : inout std_logic;
WING_CL1 : inout std_logic;
WING_CL2 : inout std_logic;
WING_CL3 : inout std_logic;
WING_CL4 : inout std_logic;
WING_CL5 : inout std_logic;
WING_CL6 : inout std_logic;
WING_CL7 : inout std_logic
);
end Papilio_Default_Pinout;
architecture BEHAVIORAL of Papilio_Default_Pinout is
-- signal gpio_bus_out.gpio_o: std_logic_vector(zpuino_gpio_count-1 downto 0);
-- signal gpio_bus_out.gpio_t: std_logic_vector(zpuino_gpio_count-1 downto 0);
-- signal gpio_bus_in.gpio_i: std_logic_vector(zpuino_gpio_count-1 downto 0);
--
-- -- SPP signal is one more than GPIO count
-- signal gpio_bus_in.gpio_spp_data: std_logic_vector(zpuino_gpio_count-1 downto 0);
-- signal gpio_bus_out.gpio_spp_read: std_logic_vector(zpuino_gpio_count-1 downto 0);
--
-- constant spp_cap_in: std_logic_vector(zpuino_gpio_count-1 downto 0) :=
-- "0" &
-- "1111111111111111" &
-- "1111111111111111" &
-- "1111111111111111";
-- constant spp_cap_out: std_logic_vector(zpuino_gpio_count-1 downto 0) :=
-- "0" &
-- "1111111111111111" &
-- "1111111111111111" &
-- "1111111111111111";
-- signal gpio_bus_in_record : gpio_bus_in_type;
-- signal gpio_bus_out_record : gpio_bus_out_type;
signal gpio_o: std_logic_vector(48 downto 0);
signal gpio_t: std_logic_vector(48 downto 0);
signal gpio_i: std_logic_vector(48 downto 0);
signal gpio_spp_data: std_logic_vector(48 downto 0);
signal gpio_spp_read: std_logic_vector(48 downto 0);
signal gpio_clk: std_logic;
begin
--Unpack the signal array into a record so the modules code is easier to understand.
--gpio_bus_in(97 downto 49) <= gpio_spp_data;
--gpio_bus_in(48 downto 0) <= gpio_i;
gpio_clk <= gpio_bus_out(147);
gpio_o <= gpio_bus_out(146 downto 98);
gpio_t <= gpio_bus_out(97 downto 49);
gpio_spp_read <= gpio_bus_out(48 downto 0);
-- gpio_bus_in(97 downto 49) <= gpio_i;
-- gpio_bus_in(48 downto 0) <= gpio_bus_in_record.gpio_spp_data;
-- gpio_clk <= gpio_bus_out(147);
-- gpio_o <= gpio_bus_out(146 downto 98);
-- gpio_t <= gpio_bus_out(97 downto 49);
-- gpio_bus_out_record.gpio_spp_read <= gpio_bus_out(48 downto 0);
-- gpio_bus_in.gpio_inst: zpuino_gpio
-- generic map (
-- gpio_count => zpuino_gpio_count
-- )
-- port map (
-- gpio_bus_out.gpio_clk => gpio_bus_out.gpio_clk,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => wb_dat_o,
-- wb_dat_i => wb_dat_i,
-- wb_adr_i => wb_adr_i,
-- wb_we_i => wb_we_i,
-- wb_cyc_i => wb_cyc_i,
-- wb_stb_i => wb_stb_i,
-- wb_ack_o => wb_ack_o,
-- wb_inta_o => wb_inta_o,
--
-- spp_data => gpio_bus_in.gpio_spp_data,
-- spp_read => gpio_bus_out.gpio_spp_read,
--
-- gpio_bus_in.gpio_i => gpio_bus_in.gpio_i,
-- gpio_bus_out.gpio_t => gpio_bus_out.gpio_t,
-- gpio_bus_out.gpio_o => gpio_bus_out.gpio_o,
-- spp_cap_in => spp_cap_in,
-- spp_cap_out => spp_cap_out
-- );
pin00: IOPAD port map(I => gpio_o(0), O => gpio_bus_in(0), T => gpio_t(0), C => gpio_clk,PAD => WING_AL0 );
pin01: IOPAD port map(I => gpio_o(1), O => gpio_bus_in(1), T => gpio_t(1), C => gpio_clk,PAD => WING_AL1 );
pin02: IOPAD port map(I => gpio_o(2), O => gpio_bus_in(2), T => gpio_t(2), C => gpio_clk,PAD => WING_AL2 );
pin03: IOPAD port map(I => gpio_o(3), O => gpio_bus_in(3), T => gpio_t(3), C => gpio_clk,PAD => WING_AL3 );
pin04: IOPAD port map(I => gpio_o(4), O => gpio_bus_in(4), T => gpio_t(4), C => gpio_clk,PAD => WING_AL4 );
pin05: IOPAD port map(I => gpio_o(5), O => gpio_bus_in(5), T => gpio_t(5), C => gpio_clk,PAD => WING_AL5 );
pin06: IOPAD port map(I => gpio_o(6), O => gpio_bus_in(6), T => gpio_t(6), C => gpio_clk,PAD => WING_AL6 );
pin07: IOPAD port map(I => gpio_o(7), O => gpio_bus_in(7), T => gpio_t(7), C => gpio_clk,PAD => WING_AL7 );
pin08: IOPAD port map(I => gpio_o(8), O => gpio_bus_in(8), T => gpio_t(8), C => gpio_clk,PAD => WING_AH0 );
pin09: IOPAD port map(I => gpio_o(9), O => gpio_bus_in(9), T => gpio_t(9), C => gpio_clk,PAD => WING_AH1 );
pin10: IOPAD port map(I => gpio_o(10),O => gpio_bus_in(10),T => gpio_t(10),C => gpio_clk,PAD => WING_AH2 );
pin11: IOPAD port map(I => gpio_o(11),O => gpio_bus_in(11),T => gpio_t(11),C => gpio_clk,PAD => WING_AH3 );
pin12: IOPAD port map(I => gpio_o(12),O => gpio_bus_in(12),T => gpio_t(12),C => gpio_clk,PAD => WING_AH4 );
pin13: IOPAD port map(I => gpio_o(13),O => gpio_bus_in(13),T => gpio_t(13),C => gpio_clk,PAD => WING_AH5 );
pin14: IOPAD port map(I => gpio_o(14),O => gpio_bus_in(14),T => gpio_t(14),C => gpio_clk,PAD => WING_AH6 );
pin15: IOPAD port map(I => gpio_o(15),O => gpio_bus_in(15),T => gpio_t(15),C => gpio_clk,PAD => WING_AH7 );
pin16: IOPAD port map(I => gpio_o(16),O => gpio_bus_in(16),T => gpio_t(16),C => gpio_clk,PAD => WING_BL0 );
pin17: IOPAD port map(I => gpio_o(17),O => gpio_bus_in(17),T => gpio_t(17),C => gpio_clk,PAD => WING_BL1 );
pin18: IOPAD port map(I => gpio_o(18),O => gpio_bus_in(18),T => gpio_t(18),C => gpio_clk,PAD => WING_BL2 );
pin19: IOPAD port map(I => gpio_o(19),O => gpio_bus_in(19),T => gpio_t(19),C => gpio_clk,PAD => WING_BL3 );
pin20: IOPAD port map(I => gpio_o(20),O => gpio_bus_in(20),T => gpio_t(20),C => gpio_clk,PAD => WING_BL4 );
pin21: IOPAD port map(I => gpio_o(21),O => gpio_bus_in(21),T => gpio_t(21),C => gpio_clk,PAD => WING_BL5 );
pin22: IOPAD port map(I => gpio_o(22),O => gpio_bus_in(22),T => gpio_t(22),C => gpio_clk,PAD => WING_BL6 );
pin23: IOPAD port map(I => gpio_o(23),O => gpio_bus_in(23),T => gpio_t(23),C => gpio_clk,PAD => WING_BL7 );
pin24: IOPAD port map(I => gpio_o(24),O => gpio_bus_in(24),T => gpio_t(24),C => gpio_clk,PAD => WING_BH0 );
pin25: IOPAD port map(I => gpio_o(25),O => gpio_bus_in(25),T => gpio_t(25),C => gpio_clk,PAD => WING_BH1 );
pin26: IOPAD port map(I => gpio_o(26),O => gpio_bus_in(26),T => gpio_t(26),C => gpio_clk,PAD => WING_BH2 );
pin27: IOPAD port map(I => gpio_o(27),O => gpio_bus_in(27),T => gpio_t(27),C => gpio_clk,PAD => WING_BH3 );
pin28: IOPAD port map(I => gpio_o(28),O => gpio_bus_in(28),T => gpio_t(28),C => gpio_clk,PAD => WING_BH4 );
pin29: IOPAD port map(I => gpio_o(29),O => gpio_bus_in(29),T => gpio_t(29),C => gpio_clk,PAD => WING_BH5 );
pin30: IOPAD port map(I => gpio_o(30),O => gpio_bus_in(30),T => gpio_t(30),C => gpio_clk,PAD => WING_BH6 );
pin31: IOPAD port map(I => gpio_o(31),O => gpio_bus_in(31),T => gpio_t(31),C => gpio_clk,PAD => WING_BH7 );
pin32: IOPAD port map(I => gpio_o(32),O => gpio_bus_in(32),T => gpio_t(32),C => gpio_clk,PAD => WING_CL0 );
pin33: IOPAD port map(I => gpio_o(33),O => gpio_bus_in(33),T => gpio_t(33),C => gpio_clk,PAD => WING_CL1 );
pin34: IOPAD port map(I => gpio_o(34),O => gpio_bus_in(34),T => gpio_t(34),C => gpio_clk,PAD => WING_CL2 );
pin35: IOPAD port map(I => gpio_o(35),O => gpio_bus_in(35),T => gpio_t(35),C => gpio_clk,PAD => WING_CL3 );
pin36: IOPAD port map(I => gpio_o(36),O => gpio_bus_in(36),T => gpio_t(36),C => gpio_clk,PAD => WING_CL4 );
pin37: IOPAD port map(I => gpio_o(37),O => gpio_bus_in(37),T => gpio_t(37),C => gpio_clk,PAD => WING_CL5 );
pin38: IOPAD port map(I => gpio_o(38),O => gpio_bus_in(38),T => gpio_t(38),C => gpio_clk,PAD => WING_CL6 );
pin39: IOPAD port map(I => gpio_o(39),O => gpio_bus_in(39),T => gpio_t(39),C => gpio_clk,PAD => WING_CL7 );
pin40: IOPAD port map(I => gpio_o(40),O => gpio_bus_in(40),T => gpio_t(40),C => gpio_clk,PAD => WING_CH0 );
pin41: IOPAD port map(I => gpio_o(41),O => gpio_bus_in(41),T => gpio_t(41),C => gpio_clk,PAD => WING_CH1 );
pin42: IOPAD port map(I => gpio_o(42),O => gpio_bus_in(42),T => gpio_t(42),C => gpio_clk,PAD => WING_CH2 );
pin43: IOPAD port map(I => gpio_o(43),O => gpio_bus_in(43),T => gpio_t(43),C => gpio_clk,PAD => WING_CH3 );
pin44: IOPAD port map(I => gpio_o(44),O => gpio_bus_in(44),T => gpio_t(44),C => gpio_clk,PAD => WING_CH4 );
pin45: IOPAD port map(I => gpio_o(45),O => gpio_bus_in(45),T => gpio_t(45),C => gpio_clk,PAD => WING_CH5 );
pin46: IOPAD port map(I => gpio_o(46),O => gpio_bus_in(46),T => gpio_t(46),C => gpio_clk,PAD => WING_CH6 );
pin47: IOPAD port map(I => gpio_o(47),O => gpio_bus_in(47),T => gpio_t(47),C => gpio_clk,PAD => WING_CH7 );
-- ospics: OPAD port map ( I => gpio_bus_out.gpio_o(48), PAD => SPI_CS );
process(gpio_spp_read)
-- sigmadelta_spp_data,
-- timers_pwm,
-- spi2_mosi,spi2_sck)
begin
--gpio_spp_data <= (others => DontCareValue);
gpio_bus_in(97 downto 49) <= (others => DontCareValue);
-- gpio_bus_in.gpio_spp_data(0) <= platform_audio_sd; -- PPS0 : SIGMADELTA DATA
-- gpio_bus_in.gpio_spp_data(1) <= timers_pwm(0); -- PPS1 : TIMER0
-- gpio_bus_in.gpio_spp_data(2) <= timers_pwm(1); -- PPS2 : TIMER1
-- gpio_bus_in.gpio_spp_data(3) <= spi2_mosi; -- PPS3 : USPI MOSI
-- gpio_bus_in.gpio_spp_data(4) <= spi2_sck; -- PPS4 : USPI SCK
-- gpio_bus_in.gpio_spp_data(5) <= platform_audio_sd; -- PPS5 : SIGMADELTA1 DATA
-- gpio_bus_in.gpio_spp_data(6) <= uart2_tx; -- PPS6 : UART2 DATA
-- gpio_bus_in.gpio_spp_data(8) <= platform_audio_sd;
-- spi2_miso <= gpio_bus_out_record.gpio_spp_read(0); -- PPS0 : USPI MISO
-- uart2_rx <= gpio_bus_out_record.gpio_spp_read(1); -- PPS0 : USPI MISO
end process;
end BEHAVIORAL;
|
--------------------------------------------------------------------------------
-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version : 14.3
-- \ \ Application :
-- / / Filename : xil_10080_19
-- /___/ /\ Timestamp : 02/08/2013 16:21:11
-- \ \ / \
-- \___\/\___\
--
--Command:
--Design Name:
-- The Papilio Default Pinout device defines the pins for a Papilio board that does not have a MegaWing attached to it.
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
library UNISIM;
use UNISIM.Vcomponents.ALL;
library board;
use board.zpupkg.all;
use board.zpuinopkg.all;
use board.zpuino_config.all;
use board.zpu_config.all;
library zpuino;
use zpuino.pad.all;
use zpuino.papilio_pkg.all;
-- Unfortunately the Xilinx Schematic Editor does not support records, so we have to put all wishbone signals into one array.
-- This is a little cumbersome but is better then dealing with all the signals in the schematic editor.
-- This is what the original record base approach looked like:
--
-- type gpio_bus_in_type is record
-- gpio_i: std_logic_vector(48 downto 0);
-- gpio_spp_data: std_logic_vector(48 downto 0);
-- end record;
--
-- type gpio_bus_out_type is record
-- gpio_clk: std_logic;
-- gpio_o: std_logic_vector(48 downto 0);
-- gpio_t: std_logic_vector(48 downto 0);
-- gpio_spp_read: std_logic_vector(48 downto 0);
-- end record;
--
-- Turning them into an array looks like this:
--
-- gpio_bus_in : in std_logic_vector(97 downto 0);
--
-- gpio_bus_in(97 downto 49) <= gpio_i;
-- gpio_bus_in(48 downto 0) <= gpio_bus_in_record.gpio_spp_data;
--
-- gpio_bus_out : out std_logic_vector(146 downto 0);
--
-- gpio_o <= gpio_bus_out(146 downto 98);
-- gpio_t <= gpio_bus_out(97 downto 49);
-- gpio_bus_out_record.gpio_spp_read <= gpio_bus_out(48 downto 0);
entity Papilio_Default_Pinout is
port (
-- gpio_clk: in std_logic;
-- gpio_o: in std_logic_vector(48 downto 0);
-- gpio_t: in std_logic_vector(48 downto 0);
-- gpio_i: out std_logic_vector(48 downto 0);
--
-- gpio_spp_data: out std_logic_vector(48 downto 0);
-- gpio_spp_read: in std_logic_vector(48 downto 0);
gpio_bus_in : out std_logic_vector(97 downto 0);
gpio_bus_out : in std_logic_vector(147 downto 0);
WING_AH0 : inout std_logic;
WING_AH1 : inout std_logic;
WING_AH2 : inout std_logic;
WING_AH3 : inout std_logic;
WING_AH4 : inout std_logic;
WING_AH5 : inout std_logic;
WING_AH6 : inout std_logic;
WING_AH7 : inout std_logic;
WING_AL0 : inout std_logic;
WING_AL1 : inout std_logic;
WING_AL2 : inout std_logic;
WING_AL3 : inout std_logic;
WING_AL4 : inout std_logic;
WING_AL5 : inout std_logic;
WING_AL6 : inout std_logic;
WING_AL7 : inout std_logic;
WING_BH0 : inout std_logic;
WING_BH1 : inout std_logic;
WING_BH2 : inout std_logic;
WING_BH3 : inout std_logic;
WING_BH4 : inout std_logic;
WING_BH5 : inout std_logic;
WING_BH6 : inout std_logic;
WING_BH7 : inout std_logic;
WING_BL0 : inout std_logic;
WING_BL1 : inout std_logic;
WING_BL2 : inout std_logic;
WING_BL3 : inout std_logic;
WING_BL4 : inout std_logic;
WING_BL5 : inout std_logic;
WING_BL6 : inout std_logic;
WING_BL7 : inout std_logic;
WING_CH0 : inout std_logic;
WING_CH1 : inout std_logic;
WING_CH2 : inout std_logic;
WING_CH3 : inout std_logic;
WING_CH4 : inout std_logic;
WING_CH5 : inout std_logic;
WING_CH6 : inout std_logic;
WING_CH7 : inout std_logic;
WING_CL0 : inout std_logic;
WING_CL1 : inout std_logic;
WING_CL2 : inout std_logic;
WING_CL3 : inout std_logic;
WING_CL4 : inout std_logic;
WING_CL5 : inout std_logic;
WING_CL6 : inout std_logic;
WING_CL7 : inout std_logic
);
end Papilio_Default_Pinout;
architecture BEHAVIORAL of Papilio_Default_Pinout is
-- signal gpio_bus_out.gpio_o: std_logic_vector(zpuino_gpio_count-1 downto 0);
-- signal gpio_bus_out.gpio_t: std_logic_vector(zpuino_gpio_count-1 downto 0);
-- signal gpio_bus_in.gpio_i: std_logic_vector(zpuino_gpio_count-1 downto 0);
--
-- -- SPP signal is one more than GPIO count
-- signal gpio_bus_in.gpio_spp_data: std_logic_vector(zpuino_gpio_count-1 downto 0);
-- signal gpio_bus_out.gpio_spp_read: std_logic_vector(zpuino_gpio_count-1 downto 0);
--
-- constant spp_cap_in: std_logic_vector(zpuino_gpio_count-1 downto 0) :=
-- "0" &
-- "1111111111111111" &
-- "1111111111111111" &
-- "1111111111111111";
-- constant spp_cap_out: std_logic_vector(zpuino_gpio_count-1 downto 0) :=
-- "0" &
-- "1111111111111111" &
-- "1111111111111111" &
-- "1111111111111111";
-- signal gpio_bus_in_record : gpio_bus_in_type;
-- signal gpio_bus_out_record : gpio_bus_out_type;
signal gpio_o: std_logic_vector(48 downto 0);
signal gpio_t: std_logic_vector(48 downto 0);
signal gpio_i: std_logic_vector(48 downto 0);
signal gpio_spp_data: std_logic_vector(48 downto 0);
signal gpio_spp_read: std_logic_vector(48 downto 0);
signal gpio_clk: std_logic;
begin
--Unpack the signal array into a record so the modules code is easier to understand.
--gpio_bus_in(97 downto 49) <= gpio_spp_data;
--gpio_bus_in(48 downto 0) <= gpio_i;
gpio_clk <= gpio_bus_out(147);
gpio_o <= gpio_bus_out(146 downto 98);
gpio_t <= gpio_bus_out(97 downto 49);
gpio_spp_read <= gpio_bus_out(48 downto 0);
-- gpio_bus_in(97 downto 49) <= gpio_i;
-- gpio_bus_in(48 downto 0) <= gpio_bus_in_record.gpio_spp_data;
-- gpio_clk <= gpio_bus_out(147);
-- gpio_o <= gpio_bus_out(146 downto 98);
-- gpio_t <= gpio_bus_out(97 downto 49);
-- gpio_bus_out_record.gpio_spp_read <= gpio_bus_out(48 downto 0);
-- gpio_bus_in.gpio_inst: zpuino_gpio
-- generic map (
-- gpio_count => zpuino_gpio_count
-- )
-- port map (
-- gpio_bus_out.gpio_clk => gpio_bus_out.gpio_clk,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => wb_dat_o,
-- wb_dat_i => wb_dat_i,
-- wb_adr_i => wb_adr_i,
-- wb_we_i => wb_we_i,
-- wb_cyc_i => wb_cyc_i,
-- wb_stb_i => wb_stb_i,
-- wb_ack_o => wb_ack_o,
-- wb_inta_o => wb_inta_o,
--
-- spp_data => gpio_bus_in.gpio_spp_data,
-- spp_read => gpio_bus_out.gpio_spp_read,
--
-- gpio_bus_in.gpio_i => gpio_bus_in.gpio_i,
-- gpio_bus_out.gpio_t => gpio_bus_out.gpio_t,
-- gpio_bus_out.gpio_o => gpio_bus_out.gpio_o,
-- spp_cap_in => spp_cap_in,
-- spp_cap_out => spp_cap_out
-- );
pin00: IOPAD port map(I => gpio_o(0), O => gpio_bus_in(0), T => gpio_t(0), C => gpio_clk,PAD => WING_AL0 );
pin01: IOPAD port map(I => gpio_o(1), O => gpio_bus_in(1), T => gpio_t(1), C => gpio_clk,PAD => WING_AL1 );
pin02: IOPAD port map(I => gpio_o(2), O => gpio_bus_in(2), T => gpio_t(2), C => gpio_clk,PAD => WING_AL2 );
pin03: IOPAD port map(I => gpio_o(3), O => gpio_bus_in(3), T => gpio_t(3), C => gpio_clk,PAD => WING_AL3 );
pin04: IOPAD port map(I => gpio_o(4), O => gpio_bus_in(4), T => gpio_t(4), C => gpio_clk,PAD => WING_AL4 );
pin05: IOPAD port map(I => gpio_o(5), O => gpio_bus_in(5), T => gpio_t(5), C => gpio_clk,PAD => WING_AL5 );
pin06: IOPAD port map(I => gpio_o(6), O => gpio_bus_in(6), T => gpio_t(6), C => gpio_clk,PAD => WING_AL6 );
pin07: IOPAD port map(I => gpio_o(7), O => gpio_bus_in(7), T => gpio_t(7), C => gpio_clk,PAD => WING_AL7 );
pin08: IOPAD port map(I => gpio_o(8), O => gpio_bus_in(8), T => gpio_t(8), C => gpio_clk,PAD => WING_AH0 );
pin09: IOPAD port map(I => gpio_o(9), O => gpio_bus_in(9), T => gpio_t(9), C => gpio_clk,PAD => WING_AH1 );
pin10: IOPAD port map(I => gpio_o(10),O => gpio_bus_in(10),T => gpio_t(10),C => gpio_clk,PAD => WING_AH2 );
pin11: IOPAD port map(I => gpio_o(11),O => gpio_bus_in(11),T => gpio_t(11),C => gpio_clk,PAD => WING_AH3 );
pin12: IOPAD port map(I => gpio_o(12),O => gpio_bus_in(12),T => gpio_t(12),C => gpio_clk,PAD => WING_AH4 );
pin13: IOPAD port map(I => gpio_o(13),O => gpio_bus_in(13),T => gpio_t(13),C => gpio_clk,PAD => WING_AH5 );
pin14: IOPAD port map(I => gpio_o(14),O => gpio_bus_in(14),T => gpio_t(14),C => gpio_clk,PAD => WING_AH6 );
pin15: IOPAD port map(I => gpio_o(15),O => gpio_bus_in(15),T => gpio_t(15),C => gpio_clk,PAD => WING_AH7 );
pin16: IOPAD port map(I => gpio_o(16),O => gpio_bus_in(16),T => gpio_t(16),C => gpio_clk,PAD => WING_BL0 );
pin17: IOPAD port map(I => gpio_o(17),O => gpio_bus_in(17),T => gpio_t(17),C => gpio_clk,PAD => WING_BL1 );
pin18: IOPAD port map(I => gpio_o(18),O => gpio_bus_in(18),T => gpio_t(18),C => gpio_clk,PAD => WING_BL2 );
pin19: IOPAD port map(I => gpio_o(19),O => gpio_bus_in(19),T => gpio_t(19),C => gpio_clk,PAD => WING_BL3 );
pin20: IOPAD port map(I => gpio_o(20),O => gpio_bus_in(20),T => gpio_t(20),C => gpio_clk,PAD => WING_BL4 );
pin21: IOPAD port map(I => gpio_o(21),O => gpio_bus_in(21),T => gpio_t(21),C => gpio_clk,PAD => WING_BL5 );
pin22: IOPAD port map(I => gpio_o(22),O => gpio_bus_in(22),T => gpio_t(22),C => gpio_clk,PAD => WING_BL6 );
pin23: IOPAD port map(I => gpio_o(23),O => gpio_bus_in(23),T => gpio_t(23),C => gpio_clk,PAD => WING_BL7 );
pin24: IOPAD port map(I => gpio_o(24),O => gpio_bus_in(24),T => gpio_t(24),C => gpio_clk,PAD => WING_BH0 );
pin25: IOPAD port map(I => gpio_o(25),O => gpio_bus_in(25),T => gpio_t(25),C => gpio_clk,PAD => WING_BH1 );
pin26: IOPAD port map(I => gpio_o(26),O => gpio_bus_in(26),T => gpio_t(26),C => gpio_clk,PAD => WING_BH2 );
pin27: IOPAD port map(I => gpio_o(27),O => gpio_bus_in(27),T => gpio_t(27),C => gpio_clk,PAD => WING_BH3 );
pin28: IOPAD port map(I => gpio_o(28),O => gpio_bus_in(28),T => gpio_t(28),C => gpio_clk,PAD => WING_BH4 );
pin29: IOPAD port map(I => gpio_o(29),O => gpio_bus_in(29),T => gpio_t(29),C => gpio_clk,PAD => WING_BH5 );
pin30: IOPAD port map(I => gpio_o(30),O => gpio_bus_in(30),T => gpio_t(30),C => gpio_clk,PAD => WING_BH6 );
pin31: IOPAD port map(I => gpio_o(31),O => gpio_bus_in(31),T => gpio_t(31),C => gpio_clk,PAD => WING_BH7 );
pin32: IOPAD port map(I => gpio_o(32),O => gpio_bus_in(32),T => gpio_t(32),C => gpio_clk,PAD => WING_CL0 );
pin33: IOPAD port map(I => gpio_o(33),O => gpio_bus_in(33),T => gpio_t(33),C => gpio_clk,PAD => WING_CL1 );
pin34: IOPAD port map(I => gpio_o(34),O => gpio_bus_in(34),T => gpio_t(34),C => gpio_clk,PAD => WING_CL2 );
pin35: IOPAD port map(I => gpio_o(35),O => gpio_bus_in(35),T => gpio_t(35),C => gpio_clk,PAD => WING_CL3 );
pin36: IOPAD port map(I => gpio_o(36),O => gpio_bus_in(36),T => gpio_t(36),C => gpio_clk,PAD => WING_CL4 );
pin37: IOPAD port map(I => gpio_o(37),O => gpio_bus_in(37),T => gpio_t(37),C => gpio_clk,PAD => WING_CL5 );
pin38: IOPAD port map(I => gpio_o(38),O => gpio_bus_in(38),T => gpio_t(38),C => gpio_clk,PAD => WING_CL6 );
pin39: IOPAD port map(I => gpio_o(39),O => gpio_bus_in(39),T => gpio_t(39),C => gpio_clk,PAD => WING_CL7 );
pin40: IOPAD port map(I => gpio_o(40),O => gpio_bus_in(40),T => gpio_t(40),C => gpio_clk,PAD => WING_CH0 );
pin41: IOPAD port map(I => gpio_o(41),O => gpio_bus_in(41),T => gpio_t(41),C => gpio_clk,PAD => WING_CH1 );
pin42: IOPAD port map(I => gpio_o(42),O => gpio_bus_in(42),T => gpio_t(42),C => gpio_clk,PAD => WING_CH2 );
pin43: IOPAD port map(I => gpio_o(43),O => gpio_bus_in(43),T => gpio_t(43),C => gpio_clk,PAD => WING_CH3 );
pin44: IOPAD port map(I => gpio_o(44),O => gpio_bus_in(44),T => gpio_t(44),C => gpio_clk,PAD => WING_CH4 );
pin45: IOPAD port map(I => gpio_o(45),O => gpio_bus_in(45),T => gpio_t(45),C => gpio_clk,PAD => WING_CH5 );
pin46: IOPAD port map(I => gpio_o(46),O => gpio_bus_in(46),T => gpio_t(46),C => gpio_clk,PAD => WING_CH6 );
pin47: IOPAD port map(I => gpio_o(47),O => gpio_bus_in(47),T => gpio_t(47),C => gpio_clk,PAD => WING_CH7 );
-- ospics: OPAD port map ( I => gpio_bus_out.gpio_o(48), PAD => SPI_CS );
process(gpio_spp_read)
-- sigmadelta_spp_data,
-- timers_pwm,
-- spi2_mosi,spi2_sck)
begin
--gpio_spp_data <= (others => DontCareValue);
gpio_bus_in(97 downto 49) <= (others => DontCareValue);
-- gpio_bus_in.gpio_spp_data(0) <= platform_audio_sd; -- PPS0 : SIGMADELTA DATA
-- gpio_bus_in.gpio_spp_data(1) <= timers_pwm(0); -- PPS1 : TIMER0
-- gpio_bus_in.gpio_spp_data(2) <= timers_pwm(1); -- PPS2 : TIMER1
-- gpio_bus_in.gpio_spp_data(3) <= spi2_mosi; -- PPS3 : USPI MOSI
-- gpio_bus_in.gpio_spp_data(4) <= spi2_sck; -- PPS4 : USPI SCK
-- gpio_bus_in.gpio_spp_data(5) <= platform_audio_sd; -- PPS5 : SIGMADELTA1 DATA
-- gpio_bus_in.gpio_spp_data(6) <= uart2_tx; -- PPS6 : UART2 DATA
-- gpio_bus_in.gpio_spp_data(8) <= platform_audio_sd;
-- spi2_miso <= gpio_bus_out_record.gpio_spp_read(0); -- PPS0 : USPI MISO
-- uart2_rx <= gpio_bus_out_record.gpio_spp_read(1); -- PPS0 : USPI MISO
end process;
end BEHAVIORAL;
|
--------------------------------------------------------------------------------
-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version : 14.3
-- \ \ Application :
-- / / Filename : xil_10080_19
-- /___/ /\ Timestamp : 02/08/2013 16:21:11
-- \ \ / \
-- \___\/\___\
--
--Command:
--Design Name:
-- The Papilio Default Pinout device defines the pins for a Papilio board that does not have a MegaWing attached to it.
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
library UNISIM;
use UNISIM.Vcomponents.ALL;
library board;
use board.zpupkg.all;
use board.zpuinopkg.all;
use board.zpuino_config.all;
use board.zpu_config.all;
library zpuino;
use zpuino.pad.all;
use zpuino.papilio_pkg.all;
-- Unfortunately the Xilinx Schematic Editor does not support records, so we have to put all wishbone signals into one array.
-- This is a little cumbersome but is better then dealing with all the signals in the schematic editor.
-- This is what the original record base approach looked like:
--
-- type gpio_bus_in_type is record
-- gpio_i: std_logic_vector(48 downto 0);
-- gpio_spp_data: std_logic_vector(48 downto 0);
-- end record;
--
-- type gpio_bus_out_type is record
-- gpio_clk: std_logic;
-- gpio_o: std_logic_vector(48 downto 0);
-- gpio_t: std_logic_vector(48 downto 0);
-- gpio_spp_read: std_logic_vector(48 downto 0);
-- end record;
--
-- Turning them into an array looks like this:
--
-- gpio_bus_in : in std_logic_vector(97 downto 0);
--
-- gpio_bus_in(97 downto 49) <= gpio_i;
-- gpio_bus_in(48 downto 0) <= gpio_bus_in_record.gpio_spp_data;
--
-- gpio_bus_out : out std_logic_vector(146 downto 0);
--
-- gpio_o <= gpio_bus_out(146 downto 98);
-- gpio_t <= gpio_bus_out(97 downto 49);
-- gpio_bus_out_record.gpio_spp_read <= gpio_bus_out(48 downto 0);
entity Papilio_Default_Pinout is
port (
-- gpio_clk: in std_logic;
-- gpio_o: in std_logic_vector(48 downto 0);
-- gpio_t: in std_logic_vector(48 downto 0);
-- gpio_i: out std_logic_vector(48 downto 0);
--
-- gpio_spp_data: out std_logic_vector(48 downto 0);
-- gpio_spp_read: in std_logic_vector(48 downto 0);
gpio_bus_in : out std_logic_vector(97 downto 0);
gpio_bus_out : in std_logic_vector(147 downto 0);
WING_AH0 : inout std_logic;
WING_AH1 : inout std_logic;
WING_AH2 : inout std_logic;
WING_AH3 : inout std_logic;
WING_AH4 : inout std_logic;
WING_AH5 : inout std_logic;
WING_AH6 : inout std_logic;
WING_AH7 : inout std_logic;
WING_AL0 : inout std_logic;
WING_AL1 : inout std_logic;
WING_AL2 : inout std_logic;
WING_AL3 : inout std_logic;
WING_AL4 : inout std_logic;
WING_AL5 : inout std_logic;
WING_AL6 : inout std_logic;
WING_AL7 : inout std_logic;
WING_BH0 : inout std_logic;
WING_BH1 : inout std_logic;
WING_BH2 : inout std_logic;
WING_BH3 : inout std_logic;
WING_BH4 : inout std_logic;
WING_BH5 : inout std_logic;
WING_BH6 : inout std_logic;
WING_BH7 : inout std_logic;
WING_BL0 : inout std_logic;
WING_BL1 : inout std_logic;
WING_BL2 : inout std_logic;
WING_BL3 : inout std_logic;
WING_BL4 : inout std_logic;
WING_BL5 : inout std_logic;
WING_BL6 : inout std_logic;
WING_BL7 : inout std_logic;
WING_CH0 : inout std_logic;
WING_CH1 : inout std_logic;
WING_CH2 : inout std_logic;
WING_CH3 : inout std_logic;
WING_CH4 : inout std_logic;
WING_CH5 : inout std_logic;
WING_CH6 : inout std_logic;
WING_CH7 : inout std_logic;
WING_CL0 : inout std_logic;
WING_CL1 : inout std_logic;
WING_CL2 : inout std_logic;
WING_CL3 : inout std_logic;
WING_CL4 : inout std_logic;
WING_CL5 : inout std_logic;
WING_CL6 : inout std_logic;
WING_CL7 : inout std_logic
);
end Papilio_Default_Pinout;
architecture BEHAVIORAL of Papilio_Default_Pinout is
-- signal gpio_bus_out.gpio_o: std_logic_vector(zpuino_gpio_count-1 downto 0);
-- signal gpio_bus_out.gpio_t: std_logic_vector(zpuino_gpio_count-1 downto 0);
-- signal gpio_bus_in.gpio_i: std_logic_vector(zpuino_gpio_count-1 downto 0);
--
-- -- SPP signal is one more than GPIO count
-- signal gpio_bus_in.gpio_spp_data: std_logic_vector(zpuino_gpio_count-1 downto 0);
-- signal gpio_bus_out.gpio_spp_read: std_logic_vector(zpuino_gpio_count-1 downto 0);
--
-- constant spp_cap_in: std_logic_vector(zpuino_gpio_count-1 downto 0) :=
-- "0" &
-- "1111111111111111" &
-- "1111111111111111" &
-- "1111111111111111";
-- constant spp_cap_out: std_logic_vector(zpuino_gpio_count-1 downto 0) :=
-- "0" &
-- "1111111111111111" &
-- "1111111111111111" &
-- "1111111111111111";
-- signal gpio_bus_in_record : gpio_bus_in_type;
-- signal gpio_bus_out_record : gpio_bus_out_type;
signal gpio_o: std_logic_vector(48 downto 0);
signal gpio_t: std_logic_vector(48 downto 0);
signal gpio_i: std_logic_vector(48 downto 0);
signal gpio_spp_data: std_logic_vector(48 downto 0);
signal gpio_spp_read: std_logic_vector(48 downto 0);
signal gpio_clk: std_logic;
begin
--Unpack the signal array into a record so the modules code is easier to understand.
--gpio_bus_in(97 downto 49) <= gpio_spp_data;
--gpio_bus_in(48 downto 0) <= gpio_i;
gpio_clk <= gpio_bus_out(147);
gpio_o <= gpio_bus_out(146 downto 98);
gpio_t <= gpio_bus_out(97 downto 49);
gpio_spp_read <= gpio_bus_out(48 downto 0);
-- gpio_bus_in(97 downto 49) <= gpio_i;
-- gpio_bus_in(48 downto 0) <= gpio_bus_in_record.gpio_spp_data;
-- gpio_clk <= gpio_bus_out(147);
-- gpio_o <= gpio_bus_out(146 downto 98);
-- gpio_t <= gpio_bus_out(97 downto 49);
-- gpio_bus_out_record.gpio_spp_read <= gpio_bus_out(48 downto 0);
-- gpio_bus_in.gpio_inst: zpuino_gpio
-- generic map (
-- gpio_count => zpuino_gpio_count
-- )
-- port map (
-- gpio_bus_out.gpio_clk => gpio_bus_out.gpio_clk,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => wb_dat_o,
-- wb_dat_i => wb_dat_i,
-- wb_adr_i => wb_adr_i,
-- wb_we_i => wb_we_i,
-- wb_cyc_i => wb_cyc_i,
-- wb_stb_i => wb_stb_i,
-- wb_ack_o => wb_ack_o,
-- wb_inta_o => wb_inta_o,
--
-- spp_data => gpio_bus_in.gpio_spp_data,
-- spp_read => gpio_bus_out.gpio_spp_read,
--
-- gpio_bus_in.gpio_i => gpio_bus_in.gpio_i,
-- gpio_bus_out.gpio_t => gpio_bus_out.gpio_t,
-- gpio_bus_out.gpio_o => gpio_bus_out.gpio_o,
-- spp_cap_in => spp_cap_in,
-- spp_cap_out => spp_cap_out
-- );
pin00: IOPAD port map(I => gpio_o(0), O => gpio_bus_in(0), T => gpio_t(0), C => gpio_clk,PAD => WING_AL0 );
pin01: IOPAD port map(I => gpio_o(1), O => gpio_bus_in(1), T => gpio_t(1), C => gpio_clk,PAD => WING_AL1 );
pin02: IOPAD port map(I => gpio_o(2), O => gpio_bus_in(2), T => gpio_t(2), C => gpio_clk,PAD => WING_AL2 );
pin03: IOPAD port map(I => gpio_o(3), O => gpio_bus_in(3), T => gpio_t(3), C => gpio_clk,PAD => WING_AL3 );
pin04: IOPAD port map(I => gpio_o(4), O => gpio_bus_in(4), T => gpio_t(4), C => gpio_clk,PAD => WING_AL4 );
pin05: IOPAD port map(I => gpio_o(5), O => gpio_bus_in(5), T => gpio_t(5), C => gpio_clk,PAD => WING_AL5 );
pin06: IOPAD port map(I => gpio_o(6), O => gpio_bus_in(6), T => gpio_t(6), C => gpio_clk,PAD => WING_AL6 );
pin07: IOPAD port map(I => gpio_o(7), O => gpio_bus_in(7), T => gpio_t(7), C => gpio_clk,PAD => WING_AL7 );
pin08: IOPAD port map(I => gpio_o(8), O => gpio_bus_in(8), T => gpio_t(8), C => gpio_clk,PAD => WING_AH0 );
pin09: IOPAD port map(I => gpio_o(9), O => gpio_bus_in(9), T => gpio_t(9), C => gpio_clk,PAD => WING_AH1 );
pin10: IOPAD port map(I => gpio_o(10),O => gpio_bus_in(10),T => gpio_t(10),C => gpio_clk,PAD => WING_AH2 );
pin11: IOPAD port map(I => gpio_o(11),O => gpio_bus_in(11),T => gpio_t(11),C => gpio_clk,PAD => WING_AH3 );
pin12: IOPAD port map(I => gpio_o(12),O => gpio_bus_in(12),T => gpio_t(12),C => gpio_clk,PAD => WING_AH4 );
pin13: IOPAD port map(I => gpio_o(13),O => gpio_bus_in(13),T => gpio_t(13),C => gpio_clk,PAD => WING_AH5 );
pin14: IOPAD port map(I => gpio_o(14),O => gpio_bus_in(14),T => gpio_t(14),C => gpio_clk,PAD => WING_AH6 );
pin15: IOPAD port map(I => gpio_o(15),O => gpio_bus_in(15),T => gpio_t(15),C => gpio_clk,PAD => WING_AH7 );
pin16: IOPAD port map(I => gpio_o(16),O => gpio_bus_in(16),T => gpio_t(16),C => gpio_clk,PAD => WING_BL0 );
pin17: IOPAD port map(I => gpio_o(17),O => gpio_bus_in(17),T => gpio_t(17),C => gpio_clk,PAD => WING_BL1 );
pin18: IOPAD port map(I => gpio_o(18),O => gpio_bus_in(18),T => gpio_t(18),C => gpio_clk,PAD => WING_BL2 );
pin19: IOPAD port map(I => gpio_o(19),O => gpio_bus_in(19),T => gpio_t(19),C => gpio_clk,PAD => WING_BL3 );
pin20: IOPAD port map(I => gpio_o(20),O => gpio_bus_in(20),T => gpio_t(20),C => gpio_clk,PAD => WING_BL4 );
pin21: IOPAD port map(I => gpio_o(21),O => gpio_bus_in(21),T => gpio_t(21),C => gpio_clk,PAD => WING_BL5 );
pin22: IOPAD port map(I => gpio_o(22),O => gpio_bus_in(22),T => gpio_t(22),C => gpio_clk,PAD => WING_BL6 );
pin23: IOPAD port map(I => gpio_o(23),O => gpio_bus_in(23),T => gpio_t(23),C => gpio_clk,PAD => WING_BL7 );
pin24: IOPAD port map(I => gpio_o(24),O => gpio_bus_in(24),T => gpio_t(24),C => gpio_clk,PAD => WING_BH0 );
pin25: IOPAD port map(I => gpio_o(25),O => gpio_bus_in(25),T => gpio_t(25),C => gpio_clk,PAD => WING_BH1 );
pin26: IOPAD port map(I => gpio_o(26),O => gpio_bus_in(26),T => gpio_t(26),C => gpio_clk,PAD => WING_BH2 );
pin27: IOPAD port map(I => gpio_o(27),O => gpio_bus_in(27),T => gpio_t(27),C => gpio_clk,PAD => WING_BH3 );
pin28: IOPAD port map(I => gpio_o(28),O => gpio_bus_in(28),T => gpio_t(28),C => gpio_clk,PAD => WING_BH4 );
pin29: IOPAD port map(I => gpio_o(29),O => gpio_bus_in(29),T => gpio_t(29),C => gpio_clk,PAD => WING_BH5 );
pin30: IOPAD port map(I => gpio_o(30),O => gpio_bus_in(30),T => gpio_t(30),C => gpio_clk,PAD => WING_BH6 );
pin31: IOPAD port map(I => gpio_o(31),O => gpio_bus_in(31),T => gpio_t(31),C => gpio_clk,PAD => WING_BH7 );
pin32: IOPAD port map(I => gpio_o(32),O => gpio_bus_in(32),T => gpio_t(32),C => gpio_clk,PAD => WING_CL0 );
pin33: IOPAD port map(I => gpio_o(33),O => gpio_bus_in(33),T => gpio_t(33),C => gpio_clk,PAD => WING_CL1 );
pin34: IOPAD port map(I => gpio_o(34),O => gpio_bus_in(34),T => gpio_t(34),C => gpio_clk,PAD => WING_CL2 );
pin35: IOPAD port map(I => gpio_o(35),O => gpio_bus_in(35),T => gpio_t(35),C => gpio_clk,PAD => WING_CL3 );
pin36: IOPAD port map(I => gpio_o(36),O => gpio_bus_in(36),T => gpio_t(36),C => gpio_clk,PAD => WING_CL4 );
pin37: IOPAD port map(I => gpio_o(37),O => gpio_bus_in(37),T => gpio_t(37),C => gpio_clk,PAD => WING_CL5 );
pin38: IOPAD port map(I => gpio_o(38),O => gpio_bus_in(38),T => gpio_t(38),C => gpio_clk,PAD => WING_CL6 );
pin39: IOPAD port map(I => gpio_o(39),O => gpio_bus_in(39),T => gpio_t(39),C => gpio_clk,PAD => WING_CL7 );
pin40: IOPAD port map(I => gpio_o(40),O => gpio_bus_in(40),T => gpio_t(40),C => gpio_clk,PAD => WING_CH0 );
pin41: IOPAD port map(I => gpio_o(41),O => gpio_bus_in(41),T => gpio_t(41),C => gpio_clk,PAD => WING_CH1 );
pin42: IOPAD port map(I => gpio_o(42),O => gpio_bus_in(42),T => gpio_t(42),C => gpio_clk,PAD => WING_CH2 );
pin43: IOPAD port map(I => gpio_o(43),O => gpio_bus_in(43),T => gpio_t(43),C => gpio_clk,PAD => WING_CH3 );
pin44: IOPAD port map(I => gpio_o(44),O => gpio_bus_in(44),T => gpio_t(44),C => gpio_clk,PAD => WING_CH4 );
pin45: IOPAD port map(I => gpio_o(45),O => gpio_bus_in(45),T => gpio_t(45),C => gpio_clk,PAD => WING_CH5 );
pin46: IOPAD port map(I => gpio_o(46),O => gpio_bus_in(46),T => gpio_t(46),C => gpio_clk,PAD => WING_CH6 );
pin47: IOPAD port map(I => gpio_o(47),O => gpio_bus_in(47),T => gpio_t(47),C => gpio_clk,PAD => WING_CH7 );
-- ospics: OPAD port map ( I => gpio_bus_out.gpio_o(48), PAD => SPI_CS );
process(gpio_spp_read)
-- sigmadelta_spp_data,
-- timers_pwm,
-- spi2_mosi,spi2_sck)
begin
--gpio_spp_data <= (others => DontCareValue);
gpio_bus_in(97 downto 49) <= (others => DontCareValue);
-- gpio_bus_in.gpio_spp_data(0) <= platform_audio_sd; -- PPS0 : SIGMADELTA DATA
-- gpio_bus_in.gpio_spp_data(1) <= timers_pwm(0); -- PPS1 : TIMER0
-- gpio_bus_in.gpio_spp_data(2) <= timers_pwm(1); -- PPS2 : TIMER1
-- gpio_bus_in.gpio_spp_data(3) <= spi2_mosi; -- PPS3 : USPI MOSI
-- gpio_bus_in.gpio_spp_data(4) <= spi2_sck; -- PPS4 : USPI SCK
-- gpio_bus_in.gpio_spp_data(5) <= platform_audio_sd; -- PPS5 : SIGMADELTA1 DATA
-- gpio_bus_in.gpio_spp_data(6) <= uart2_tx; -- PPS6 : UART2 DATA
-- gpio_bus_in.gpio_spp_data(8) <= platform_audio_sd;
-- spi2_miso <= gpio_bus_out_record.gpio_spp_read(0); -- PPS0 : USPI MISO
-- uart2_rx <= gpio_bus_out_record.gpio_spp_read(1); -- PPS0 : USPI MISO
end process;
end BEHAVIORAL;
|
-- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity alt_dspbuilder_decoder is
generic (
DECODE : string := "00000000";
PIPELINE : natural := 0;
WIDTH : natural := 8
);
port (
dec : out std_logic;
clock : in std_logic;
sclr : in std_logic;
data : in std_logic_vector(width-1 downto 0);
aclr : in std_logic;
ena : in std_logic
);
end entity alt_dspbuilder_decoder;
architecture rtl of alt_dspbuilder_decoder is
component alt_dspbuilder_decoder_GNSCEXJCJK is
generic (
DECODE : string := "000000000000000000001111";
PIPELINE : natural := 0;
WIDTH : natural := 24
);
port (
aclr : in std_logic;
clock : in std_logic;
data : in std_logic_vector(24-1 downto 0);
dec : out std_logic;
ena : in std_logic;
sclr : in std_logic
);
end component alt_dspbuilder_decoder_GNSCEXJCJK;
begin
alt_dspbuilder_decoder_GNSCEXJCJK_0: if ((DECODE = "000000000000000000001111") and (PIPELINE = 0) and (WIDTH = 24)) generate
inst_alt_dspbuilder_decoder_GNSCEXJCJK_0: alt_dspbuilder_decoder_GNSCEXJCJK
generic map(DECODE => "000000000000000000001111", PIPELINE => 0, WIDTH => 24)
port map(aclr => aclr, clock => clock, data => data, dec => dec, ena => ena, sclr => sclr);
end generate;
assert not (((DECODE = "000000000000000000001111") and (PIPELINE = 0) and (WIDTH = 24)))
report "Please run generate again" severity error;
end architecture rtl;
|
-- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity alt_dspbuilder_decoder is
generic (
DECODE : string := "00000000";
PIPELINE : natural := 0;
WIDTH : natural := 8
);
port (
dec : out std_logic;
clock : in std_logic;
sclr : in std_logic;
data : in std_logic_vector(width-1 downto 0);
aclr : in std_logic;
ena : in std_logic
);
end entity alt_dspbuilder_decoder;
architecture rtl of alt_dspbuilder_decoder is
component alt_dspbuilder_decoder_GNSCEXJCJK is
generic (
DECODE : string := "000000000000000000001111";
PIPELINE : natural := 0;
WIDTH : natural := 24
);
port (
aclr : in std_logic;
clock : in std_logic;
data : in std_logic_vector(24-1 downto 0);
dec : out std_logic;
ena : in std_logic;
sclr : in std_logic
);
end component alt_dspbuilder_decoder_GNSCEXJCJK;
begin
alt_dspbuilder_decoder_GNSCEXJCJK_0: if ((DECODE = "000000000000000000001111") and (PIPELINE = 0) and (WIDTH = 24)) generate
inst_alt_dspbuilder_decoder_GNSCEXJCJK_0: alt_dspbuilder_decoder_GNSCEXJCJK
generic map(DECODE => "000000000000000000001111", PIPELINE => 0, WIDTH => 24)
port map(aclr => aclr, clock => clock, data => data, dec => dec, ena => ena, sclr => sclr);
end generate;
assert not (((DECODE = "000000000000000000001111") and (PIPELINE = 0) and (WIDTH = 24)))
report "Please run generate again" severity error;
end architecture rtl;
|
-- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity alt_dspbuilder_decoder is
generic (
DECODE : string := "00000000";
PIPELINE : natural := 0;
WIDTH : natural := 8
);
port (
dec : out std_logic;
clock : in std_logic;
sclr : in std_logic;
data : in std_logic_vector(width-1 downto 0);
aclr : in std_logic;
ena : in std_logic
);
end entity alt_dspbuilder_decoder;
architecture rtl of alt_dspbuilder_decoder is
component alt_dspbuilder_decoder_GNSCEXJCJK is
generic (
DECODE : string := "000000000000000000001111";
PIPELINE : natural := 0;
WIDTH : natural := 24
);
port (
aclr : in std_logic;
clock : in std_logic;
data : in std_logic_vector(24-1 downto 0);
dec : out std_logic;
ena : in std_logic;
sclr : in std_logic
);
end component alt_dspbuilder_decoder_GNSCEXJCJK;
begin
alt_dspbuilder_decoder_GNSCEXJCJK_0: if ((DECODE = "000000000000000000001111") and (PIPELINE = 0) and (WIDTH = 24)) generate
inst_alt_dspbuilder_decoder_GNSCEXJCJK_0: alt_dspbuilder_decoder_GNSCEXJCJK
generic map(DECODE => "000000000000000000001111", PIPELINE => 0, WIDTH => 24)
port map(aclr => aclr, clock => clock, data => data, dec => dec, ena => ena, sclr => sclr);
end generate;
assert not (((DECODE = "000000000000000000001111") and (PIPELINE = 0) and (WIDTH = 24)))
report "Please run generate again" severity error;
end architecture rtl;
|
-- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity alt_dspbuilder_decoder is
generic (
DECODE : string := "00000000";
PIPELINE : natural := 0;
WIDTH : natural := 8
);
port (
dec : out std_logic;
clock : in std_logic;
sclr : in std_logic;
data : in std_logic_vector(width-1 downto 0);
aclr : in std_logic;
ena : in std_logic
);
end entity alt_dspbuilder_decoder;
architecture rtl of alt_dspbuilder_decoder is
component alt_dspbuilder_decoder_GNSCEXJCJK is
generic (
DECODE : string := "000000000000000000001111";
PIPELINE : natural := 0;
WIDTH : natural := 24
);
port (
aclr : in std_logic;
clock : in std_logic;
data : in std_logic_vector(24-1 downto 0);
dec : out std_logic;
ena : in std_logic;
sclr : in std_logic
);
end component alt_dspbuilder_decoder_GNSCEXJCJK;
begin
alt_dspbuilder_decoder_GNSCEXJCJK_0: if ((DECODE = "000000000000000000001111") and (PIPELINE = 0) and (WIDTH = 24)) generate
inst_alt_dspbuilder_decoder_GNSCEXJCJK_0: alt_dspbuilder_decoder_GNSCEXJCJK
generic map(DECODE => "000000000000000000001111", PIPELINE => 0, WIDTH => 24)
port map(aclr => aclr, clock => clock, data => data, dec => dec, ena => ena, sclr => sclr);
end generate;
assert not (((DECODE = "000000000000000000001111") and (PIPELINE = 0) and (WIDTH = 24)))
report "Please run generate again" severity error;
end architecture rtl;
|
-- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity alt_dspbuilder_decoder is
generic (
DECODE : string := "00000000";
PIPELINE : natural := 0;
WIDTH : natural := 8
);
port (
dec : out std_logic;
clock : in std_logic;
sclr : in std_logic;
data : in std_logic_vector(width-1 downto 0);
aclr : in std_logic;
ena : in std_logic
);
end entity alt_dspbuilder_decoder;
architecture rtl of alt_dspbuilder_decoder is
component alt_dspbuilder_decoder_GNSCEXJCJK is
generic (
DECODE : string := "000000000000000000001111";
PIPELINE : natural := 0;
WIDTH : natural := 24
);
port (
aclr : in std_logic;
clock : in std_logic;
data : in std_logic_vector(24-1 downto 0);
dec : out std_logic;
ena : in std_logic;
sclr : in std_logic
);
end component alt_dspbuilder_decoder_GNSCEXJCJK;
begin
alt_dspbuilder_decoder_GNSCEXJCJK_0: if ((DECODE = "000000000000000000001111") and (PIPELINE = 0) and (WIDTH = 24)) generate
inst_alt_dspbuilder_decoder_GNSCEXJCJK_0: alt_dspbuilder_decoder_GNSCEXJCJK
generic map(DECODE => "000000000000000000001111", PIPELINE => 0, WIDTH => 24)
port map(aclr => aclr, clock => clock, data => data, dec => dec, ena => ena, sclr => sclr);
end generate;
assert not (((DECODE = "000000000000000000001111") and (PIPELINE = 0) and (WIDTH = 24)))
report "Please run generate again" severity error;
end architecture rtl;
|
-- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity alt_dspbuilder_decoder is
generic (
DECODE : string := "00000000";
PIPELINE : natural := 0;
WIDTH : natural := 8
);
port (
dec : out std_logic;
clock : in std_logic;
sclr : in std_logic;
data : in std_logic_vector(width-1 downto 0);
aclr : in std_logic;
ena : in std_logic
);
end entity alt_dspbuilder_decoder;
architecture rtl of alt_dspbuilder_decoder is
component alt_dspbuilder_decoder_GNSCEXJCJK is
generic (
DECODE : string := "000000000000000000001111";
PIPELINE : natural := 0;
WIDTH : natural := 24
);
port (
aclr : in std_logic;
clock : in std_logic;
data : in std_logic_vector(24-1 downto 0);
dec : out std_logic;
ena : in std_logic;
sclr : in std_logic
);
end component alt_dspbuilder_decoder_GNSCEXJCJK;
begin
alt_dspbuilder_decoder_GNSCEXJCJK_0: if ((DECODE = "000000000000000000001111") and (PIPELINE = 0) and (WIDTH = 24)) generate
inst_alt_dspbuilder_decoder_GNSCEXJCJK_0: alt_dspbuilder_decoder_GNSCEXJCJK
generic map(DECODE => "000000000000000000001111", PIPELINE => 0, WIDTH => 24)
port map(aclr => aclr, clock => clock, data => data, dec => dec, ena => ena, sclr => sclr);
end generate;
assert not (((DECODE = "000000000000000000001111") and (PIPELINE = 0) and (WIDTH = 24)))
report "Please run generate again" severity error;
end architecture rtl;
|
-- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity alt_dspbuilder_decoder is
generic (
DECODE : string := "00000000";
PIPELINE : natural := 0;
WIDTH : natural := 8
);
port (
dec : out std_logic;
clock : in std_logic;
sclr : in std_logic;
data : in std_logic_vector(width-1 downto 0);
aclr : in std_logic;
ena : in std_logic
);
end entity alt_dspbuilder_decoder;
architecture rtl of alt_dspbuilder_decoder is
component alt_dspbuilder_decoder_GNSCEXJCJK is
generic (
DECODE : string := "000000000000000000001111";
PIPELINE : natural := 0;
WIDTH : natural := 24
);
port (
aclr : in std_logic;
clock : in std_logic;
data : in std_logic_vector(24-1 downto 0);
dec : out std_logic;
ena : in std_logic;
sclr : in std_logic
);
end component alt_dspbuilder_decoder_GNSCEXJCJK;
begin
alt_dspbuilder_decoder_GNSCEXJCJK_0: if ((DECODE = "000000000000000000001111") and (PIPELINE = 0) and (WIDTH = 24)) generate
inst_alt_dspbuilder_decoder_GNSCEXJCJK_0: alt_dspbuilder_decoder_GNSCEXJCJK
generic map(DECODE => "000000000000000000001111", PIPELINE => 0, WIDTH => 24)
port map(aclr => aclr, clock => clock, data => data, dec => dec, ena => ena, sclr => sclr);
end generate;
assert not (((DECODE = "000000000000000000001111") and (PIPELINE = 0) and (WIDTH = 24)))
report "Please run generate again" severity error;
end architecture rtl;
|
----------------------------------------------------------------------------------------------
--
-- Input file : mem.vhd
-- Design name : mem
-- Author : Tamar Kranenburg
-- Company : Delft University of Technology
-- : Faculty EEMCS, Department ME&CE
-- : Systems and Circuits group
--
-- Description : Memory retrieves data words from a data memory. Memory file
-- access of byte, halfword and word sizes is supported. The sel_o
-- signal indicates which bytes should be read or written. The
-- responsibility for writing the right memory address is not within
-- this integer unit but should be handled by the external memory
-- device. This facilitates the addition of devices with different
-- bus sizes.
--
-- The dmem_i signals are directly connected to the decode and
-- execute components.
--
----------------------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
LIBRARY work;
USE work.config_Pkg.ALL;
USE work.core_Pkg.ALL;
USE work.std_Pkg.ALL;
ENTITY mem IS PORT
(
mem_o : OUT mem_out_type;
dmem_dat_o : OUT std_ulogic_vector(CFG_DMEM_WIDTH - 1 DOWNTO 0);
dmem_adr_o : OUT std_ulogic_vector(CFG_DMEM_SIZE - 1 DOWNTO 0);
dmem_sel_o : OUT std_ulogic_vector(3 DOWNTO 0);
dmem_we_o : OUT std_ulogic;
dmem_ena_o : OUT std_ulogic;
mem_i : IN mem_in_type;
ena_i : IN std_ulogic;
rst_i : IN std_ulogic;
clk_i : IN std_ulogic
);
END mem;
ARCHITECTURE arch OF mem IS
SIGNAL r, rin : mem_out_type;
SIGNAL mem_result : std_ulogic_vector(CFG_DMEM_WIDTH - 1 DOWNTO 0);
BEGIN
-- connect pipline signals
mem_o.ctrl_wb <= r.ctrl_wb;
mem_o.ctrl_mem_wb <= r.ctrl_mem_wb;
mem_o.alu_result <= r.alu_result;
-- connect memory interface signals
dmem_dat_o <= mem_result;
dmem_sel_o <= decode_mem_store(mem_i.alu_result(1 DOWNTO 0), mem_i.ctrl_mem.transfer_size);
dmem_we_o <= mem_i.ctrl_mem.mem_write;
dmem_adr_o <= mem_i.alu_result(CFG_DMEM_SIZE - 1 DOWNTO 0);
dmem_ena_o <= mem_i.ctrl_mem.mem_read OR mem_i.ctrl_mem.mem_write;
mem_comb: PROCESS(mem_i, mem_i.ctrl_wb, mem_i.ctrl_mem, r, r.ctrl_wb, r.ctrl_mem_wb)
VARIABLE v : mem_out_type;
VARIABLE intermediate : std_ulogic_vector(CFG_DMEM_WIDTH - 1 DOWNTO 0);
BEGIN
v := r;
v.ctrl_wb := mem_i.ctrl_wb;
IF mem_i.branch = '1' THEN
-- set alu result for branch and load instructions
v.alu_result := sign_extend(mem_i.program_counter, '0', 32);
ELSE
v.alu_result := mem_i.alu_result;
END IF;
-- Forward memory result
IF CFG_MEM_FWD_WB = true AND ( r.ctrl_mem_wb.mem_read AND compare(mem_i.ctrl_wb.reg_d, r.ctrl_wb.reg_d)) = '1' THEN
intermediate := align_mem_load(mem_i.mem_result, r.ctrl_mem_wb.transfer_size, r.alu_result(1 DOWNTO 0));
mem_result <= align_mem_store(intermediate, mem_i.ctrl_mem.transfer_size);
ELSE
mem_result <= mem_i.dat_d;
END IF;
v.ctrl_mem_wb.mem_read := mem_i.ctrl_mem.mem_read;
v.ctrl_mem_wb.transfer_size := mem_i.ctrl_mem.transfer_size;
rin <= v;
END PROCESS;
mem_seq: PROCESS(clk_i)
PROCEDURE proc_mem_reset IS
BEGIN
r.alu_result <= (OTHERS => '0');
r.ctrl_wb.reg_d <= (OTHERS => '0');
r.ctrl_wb.reg_write <= '0';
r.ctrl_mem_wb.mem_read <= '0';
r.ctrl_mem_wb.transfer_size <= WORD;
END PROCEDURE proc_mem_reset;
BEGIN
IF rising_edge(clk_i) THEN
IF rst_i = '1' THEN
proc_mem_reset;
ELSIF ena_i = '1' THEN
r <= rin;
END IF;
END IF;
END PROCESS;
END arch;
|
----------------------------------------------------------------------------------------------
--
-- Input file : mem.vhd
-- Design name : mem
-- Author : Tamar Kranenburg
-- Company : Delft University of Technology
-- : Faculty EEMCS, Department ME&CE
-- : Systems and Circuits group
--
-- Description : Memory retrieves data words from a data memory. Memory file
-- access of byte, halfword and word sizes is supported. The sel_o
-- signal indicates which bytes should be read or written. The
-- responsibility for writing the right memory address is not within
-- this integer unit but should be handled by the external memory
-- device. This facilitates the addition of devices with different
-- bus sizes.
--
-- The dmem_i signals are directly connected to the decode and
-- execute components.
--
----------------------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
LIBRARY work;
USE work.config_Pkg.ALL;
USE work.core_Pkg.ALL;
USE work.std_Pkg.ALL;
ENTITY mem IS PORT
(
mem_o : OUT mem_out_type;
dmem_dat_o : OUT std_ulogic_vector(CFG_DMEM_WIDTH - 1 DOWNTO 0);
dmem_adr_o : OUT std_ulogic_vector(CFG_DMEM_SIZE - 1 DOWNTO 0);
dmem_sel_o : OUT std_ulogic_vector(3 DOWNTO 0);
dmem_we_o : OUT std_ulogic;
dmem_ena_o : OUT std_ulogic;
mem_i : IN mem_in_type;
ena_i : IN std_ulogic;
rst_i : IN std_ulogic;
clk_i : IN std_ulogic
);
END mem;
ARCHITECTURE arch OF mem IS
SIGNAL r, rin : mem_out_type;
SIGNAL mem_result : std_ulogic_vector(CFG_DMEM_WIDTH - 1 DOWNTO 0);
BEGIN
-- connect pipline signals
mem_o.ctrl_wb <= r.ctrl_wb;
mem_o.ctrl_mem_wb <= r.ctrl_mem_wb;
mem_o.alu_result <= r.alu_result;
-- connect memory interface signals
dmem_dat_o <= mem_result;
dmem_sel_o <= decode_mem_store(mem_i.alu_result(1 DOWNTO 0), mem_i.ctrl_mem.transfer_size);
dmem_we_o <= mem_i.ctrl_mem.mem_write;
dmem_adr_o <= mem_i.alu_result(CFG_DMEM_SIZE - 1 DOWNTO 0);
dmem_ena_o <= mem_i.ctrl_mem.mem_read OR mem_i.ctrl_mem.mem_write;
mem_comb: PROCESS(mem_i, mem_i.ctrl_wb, mem_i.ctrl_mem, r, r.ctrl_wb, r.ctrl_mem_wb)
VARIABLE v : mem_out_type;
VARIABLE intermediate : std_ulogic_vector(CFG_DMEM_WIDTH - 1 DOWNTO 0);
BEGIN
v := r;
v.ctrl_wb := mem_i.ctrl_wb;
IF mem_i.branch = '1' THEN
-- set alu result for branch and load instructions
v.alu_result := sign_extend(mem_i.program_counter, '0', 32);
ELSE
v.alu_result := mem_i.alu_result;
END IF;
-- Forward memory result
IF CFG_MEM_FWD_WB = true AND ( r.ctrl_mem_wb.mem_read AND compare(mem_i.ctrl_wb.reg_d, r.ctrl_wb.reg_d)) = '1' THEN
intermediate := align_mem_load(mem_i.mem_result, r.ctrl_mem_wb.transfer_size, r.alu_result(1 DOWNTO 0));
mem_result <= align_mem_store(intermediate, mem_i.ctrl_mem.transfer_size);
ELSE
mem_result <= mem_i.dat_d;
END IF;
v.ctrl_mem_wb.mem_read := mem_i.ctrl_mem.mem_read;
v.ctrl_mem_wb.transfer_size := mem_i.ctrl_mem.transfer_size;
rin <= v;
END PROCESS;
mem_seq: PROCESS(clk_i)
PROCEDURE proc_mem_reset IS
BEGIN
r.alu_result <= (OTHERS => '0');
r.ctrl_wb.reg_d <= (OTHERS => '0');
r.ctrl_wb.reg_write <= '0';
r.ctrl_mem_wb.mem_read <= '0';
r.ctrl_mem_wb.transfer_size <= WORD;
END PROCEDURE proc_mem_reset;
BEGIN
IF rising_edge(clk_i) THEN
IF rst_i = '1' THEN
proc_mem_reset;
ELSIF ena_i = '1' THEN
r <= rin;
END IF;
END IF;
END PROCESS;
END arch;
|
----------------------------------------------------------------------------------------------
--
-- Input file : mem.vhd
-- Design name : mem
-- Author : Tamar Kranenburg
-- Company : Delft University of Technology
-- : Faculty EEMCS, Department ME&CE
-- : Systems and Circuits group
--
-- Description : Memory retrieves data words from a data memory. Memory file
-- access of byte, halfword and word sizes is supported. The sel_o
-- signal indicates which bytes should be read or written. The
-- responsibility for writing the right memory address is not within
-- this integer unit but should be handled by the external memory
-- device. This facilitates the addition of devices with different
-- bus sizes.
--
-- The dmem_i signals are directly connected to the decode and
-- execute components.
--
----------------------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
LIBRARY work;
USE work.config_Pkg.ALL;
USE work.core_Pkg.ALL;
USE work.std_Pkg.ALL;
ENTITY mem IS PORT
(
mem_o : OUT mem_out_type;
dmem_dat_o : OUT std_ulogic_vector(CFG_DMEM_WIDTH - 1 DOWNTO 0);
dmem_adr_o : OUT std_ulogic_vector(CFG_DMEM_SIZE - 1 DOWNTO 0);
dmem_sel_o : OUT std_ulogic_vector(3 DOWNTO 0);
dmem_we_o : OUT std_ulogic;
dmem_ena_o : OUT std_ulogic;
mem_i : IN mem_in_type;
ena_i : IN std_ulogic;
rst_i : IN std_ulogic;
clk_i : IN std_ulogic
);
END mem;
ARCHITECTURE arch OF mem IS
SIGNAL r, rin : mem_out_type;
SIGNAL mem_result : std_ulogic_vector(CFG_DMEM_WIDTH - 1 DOWNTO 0);
BEGIN
-- connect pipline signals
mem_o.ctrl_wb <= r.ctrl_wb;
mem_o.ctrl_mem_wb <= r.ctrl_mem_wb;
mem_o.alu_result <= r.alu_result;
-- connect memory interface signals
dmem_dat_o <= mem_result;
dmem_sel_o <= decode_mem_store(mem_i.alu_result(1 DOWNTO 0), mem_i.ctrl_mem.transfer_size);
dmem_we_o <= mem_i.ctrl_mem.mem_write;
dmem_adr_o <= mem_i.alu_result(CFG_DMEM_SIZE - 1 DOWNTO 0);
dmem_ena_o <= mem_i.ctrl_mem.mem_read OR mem_i.ctrl_mem.mem_write;
mem_comb: PROCESS(mem_i, mem_i.ctrl_wb, mem_i.ctrl_mem, r, r.ctrl_wb, r.ctrl_mem_wb)
VARIABLE v : mem_out_type;
VARIABLE intermediate : std_ulogic_vector(CFG_DMEM_WIDTH - 1 DOWNTO 0);
BEGIN
v := r;
v.ctrl_wb := mem_i.ctrl_wb;
IF mem_i.branch = '1' THEN
-- set alu result for branch and load instructions
v.alu_result := sign_extend(mem_i.program_counter, '0', 32);
ELSE
v.alu_result := mem_i.alu_result;
END IF;
-- Forward memory result
IF CFG_MEM_FWD_WB = true AND ( r.ctrl_mem_wb.mem_read AND compare(mem_i.ctrl_wb.reg_d, r.ctrl_wb.reg_d)) = '1' THEN
intermediate := align_mem_load(mem_i.mem_result, r.ctrl_mem_wb.transfer_size, r.alu_result(1 DOWNTO 0));
mem_result <= align_mem_store(intermediate, mem_i.ctrl_mem.transfer_size);
ELSE
mem_result <= mem_i.dat_d;
END IF;
v.ctrl_mem_wb.mem_read := mem_i.ctrl_mem.mem_read;
v.ctrl_mem_wb.transfer_size := mem_i.ctrl_mem.transfer_size;
rin <= v;
END PROCESS;
mem_seq: PROCESS(clk_i)
PROCEDURE proc_mem_reset IS
BEGIN
r.alu_result <= (OTHERS => '0');
r.ctrl_wb.reg_d <= (OTHERS => '0');
r.ctrl_wb.reg_write <= '0';
r.ctrl_mem_wb.mem_read <= '0';
r.ctrl_mem_wb.transfer_size <= WORD;
END PROCEDURE proc_mem_reset;
BEGIN
IF rising_edge(clk_i) THEN
IF rst_i = '1' THEN
proc_mem_reset;
ELSIF ena_i = '1' THEN
r <= rin;
END IF;
END IF;
END PROCESS;
END arch;
|
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- ____ _ ____ _ _ _ _
-- | _ \(_) ___ ___ | __ )| | __ _ _______ | | (_) |__ _ __ __ _ _ __ _ _
-- | |_) | |/ __/ _ \| _ \| |/ _` |_ / _ \ | | | | '_ \| '__/ _` | '__| | | |
-- | __/| | (_| (_) | |_) | | (_| |/ / __/ | |___| | |_) | | | (_| | | | |_| |
-- |_| |_|\___\___/|____/|_|\__,_/___\___| |_____|_|_.__/|_| \__,_|_| \__, |
-- |___/
-- =============================================================================
-- Authors: Patrick Lehmann
--
-- Module: Binary to BCD converter (24 bit) for PicoBlaze
--
-- Description:
-- ------------------------------------
-- TODO
--
--
-- License:
-- ============================================================================
-- Copyright 2007-2015 Patrick Lehmann - Dresden, Germany
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ============================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library PoC;
use PoC.utils.all;
use PoC.vectors.all;
use PoC.strings.all;
library L_PicoBlaze;
use L_PicoBlaze.pb.all;
entity pb_ConverterBCD24_Device is
generic (
DEVICE_INSTANCE : T_PB_DEVICE_INSTANCE
);
port (
Clock : in STD_LOGIC;
Reset : in STD_LOGIC;
-- PicoBlaze interface
Address : in T_SLV_8;
WriteStrobe : in STD_LOGIC;
WriteStrobe_K : in STD_LOGIC;
ReadStrobe : in STD_LOGIC;
DataIn : in T_SLV_8;
DataOut : out T_SLV_8;
Interrupt : out STD_LOGIC;
Interrupt_Ack : in STD_LOGIC;
Message : out T_SLV_8
);
end entity;
architecture rtl of pb_ConverterBCD24_Device is
constant REG_WO_A0 : STD_LOGIC_VECTOR(1 downto 0) := "00";
constant REG_WO_A1 : STD_LOGIC_VECTOR(1 downto 0) := "01";
constant REG_WO_A2 : STD_LOGIC_VECTOR(1 downto 0) := "10";
constant REG_RO_R0 : STD_LOGIC_VECTOR(1 downto 0) := "00";
constant REG_RO_R1 : STD_LOGIC_VECTOR(1 downto 0) := "01";
constant REG_RO_R2 : STD_LOGIC_VECTOR(1 downto 0) := "10";
constant REG_RO_STATUS : STD_LOGIC_VECTOR(1 downto 0) := "11";
signal AdrDec_we : STD_LOGIC;
signal AdrDec_re : STD_LOGIC;
signal AdrDec_WriteAddress : T_SLV_8;
signal AdrDec_ReadAddress : T_SLV_8;
signal AdrDec_Data : T_SLV_8;
signal Reg_Start : STD_LOGIC := '0';
signal Flag_IsSigned : STD_LOGIC := '0';
signal Reg_Operand_a : T_SLV_24 := (OTHERS => '0');
signal Reg_Result : T_SLV_32 := (OTHERS => '0');
signal Conv_Busy : STD_LOGIC;
signal Conv_Busy_d : STD_LOGIC := '0';
signal Conv_Busy_fe : STD_LOGIC;
signal Conv_Sign : STD_LOGIC;
signal Conv_Result : T_BCD_VECTOR(6 downto 0);
begin
AdrDec : entity L_PicoBlaze.PicoBlaze_AddressDecoder
generic map (
DEVICE_NAME => str_trim(DEVICE_INSTANCE.DeviceShort),
BUS_NAME => str_trim(DEVICE_INSTANCE.BusShort),
READ_MAPPINGS => pb_FilterMappings(DEVICE_INSTANCE, PB_MAPPING_KIND_READ),
WRITE_MAPPINGS => pb_FilterMappings(DEVICE_INSTANCE, PB_MAPPING_KIND_WRITE),
WRITEK_MAPPINGS => pb_FilterMappings(DEVICE_INSTANCE, PB_MAPPING_KIND_WRITEK)
)
port map (
Clock => Clock,
Reset => Reset,
-- PicoBlaze interface
In_WriteStrobe => WriteStrobe,
In_WriteStrobe_K => WriteStrobe_K,
In_ReadStrobe => ReadStrobe,
In_Address => Address,
In_Data => DataIn,
Out_WriteStrobe => AdrDec_we,
Out_ReadStrobe => AdrDec_re,
Out_WriteAddress => AdrDec_WriteAddress,
Out_ReadAddress => AdrDec_ReadAddress,
Out_Data => AdrDec_Data
);
process(Clock)
begin
if rising_edge(Clock) then
Reg_Start <= '0';
Flag_IsSigned <= '0';
if (Reset = '1') then
Reg_Operand_A <= (others => '0');
Reg_Result <= (others => '0');
else
if (AdrDec_we = '1') then
case AdrDec_WriteAddress(1 downto 0) IS
when REG_WO_A0 => Reg_Operand_A(7 downto 0) <= AdrDec_Data;
when REG_WO_A1 => Reg_Operand_A(15 downto 8) <= AdrDec_Data;
when REG_WO_A2 => Reg_Operand_A(23 downto 16) <= AdrDec_Data;
Reg_Start <= '1';
when others => null;
end case;
elsif (Conv_Busy_fe = '1') then
Reg_Result(31 downto 28) <= "0000";
for i in 0 to 6 loop
Reg_Result((i * 4) + 3 downto (i * 4)) <= std_logic_vector(Conv_Result(i));
end loop;
end if;
end if;
end if;
end process;
process(AdrDec_re, AdrDec_ReadAddress, Reg_Result, Conv_Sign, Conv_Busy)
variable Reg_Result_slvv : T_SLVV_8(3 downto 0);
begin
Reg_Result_slvv := to_slvv_8(Reg_Result);
DataOut <= Reg_Result_slvv(to_index(AdrDec_ReadAddress(1 downto 0), Reg_Result_slvv'length - 1));
if (AdrDec_ReadAddress(1 downto 0) = REG_RO_STATUS) then
DataOut <= (not Conv_Busy) & "00" & Conv_Sign & Reg_Result_slvv(Reg_Result_slvv'high)(3 downto 0);
end if;
end process;
Interrupt <= Conv_Busy_fe;
Message <= to_slv(0, Message'length);
Conv : entity PoC.arith_convert_bin2bcd
generic map (
BITS => 24,
DIGITS => 7,
RADIX => 4
)
port map (
Clock => Clock,
Reset => Reset,
Start => Reg_Start,
Busy => Conv_Busy,
Binary => Reg_Operand_A,
IsSigned => Flag_IsSigned,
BCDDigits => Conv_Result,
Sign => Conv_Sign
);
Conv_Busy_d <= Conv_Busy when rising_edge(Clock);
Conv_Busy_fe <= Conv_Busy_d and not Conv_Busy;
end;
|
entity arith2 is
end entity;
architecture test of arith2 is
begin
process is
variable x, y : integer;
begin
x := 5;
y := 0;
wait for 1 ns;
x := x / y;
wait;
end process;
end architecture;
|
entity arith2 is
end entity;
architecture test of arith2 is
begin
process is
variable x, y : integer;
begin
x := 5;
y := 0;
wait for 1 ns;
x := x / y;
wait;
end process;
end architecture;
|
entity arith2 is
end entity;
architecture test of arith2 is
begin
process is
variable x, y : integer;
begin
x := 5;
y := 0;
wait for 1 ns;
x := x / y;
wait;
end process;
end architecture;
|
entity arith2 is
end entity;
architecture test of arith2 is
begin
process is
variable x, y : integer;
begin
x := 5;
y := 0;
wait for 1 ns;
x := x / y;
wait;
end process;
end architecture;
|
entity arith2 is
end entity;
architecture test of arith2 is
begin
process is
variable x, y : integer;
begin
x := 5;
y := 0;
wait for 1 ns;
x := x / y;
wait;
end process;
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.dfir_types.all;
package dfir_coeff_lib is
constant dfir_order : natural := 129;
type integer_vector is array(dfir_order downto 0) of integer;
constant dfir_coeff_content : integer_vector := (
30251, 25860, 4784, -21256, -36393, -29458, -1554, 32410,
50644, 37512, -4503, -52413, -74050, -48513, 16566, 84046,
107070, 60122, -38397, -130080, -149580, -69234, 74231, 193160,
200780, 71802, -129020, -276090, -259370, -62958, 208440, 381780,
323340, 36338, -319910, -514420, -390640, 16054, 473460, 680160,
458700, -106210, -685690, -891130, -526160, 252490, 985540, 1170900,
592070, -491400, -1436600, -1577800, -662630, 904470, 2199700, 2274900,
763940, -1750000, -3862800, -3974600, -1129700, 4365600, 10902000, 16178000,
18199000, 16178000, 10902000, 4365600, -1129700, -3974600, -3862800, -1750000,
763940, 2274900, 2199700, 904470, -662630, -1577800, -1436600, -491400,
592070, 1170900, 985540, 252490, -526160, -891130, -685690, -106210,
458700, 680160, 473460, 16054, -390640, -514420, -319910, 36338,
323340, 381780, 208440, -62958, -259370, -276090, -129020, 71802,
200780, 193160, 74231, -69234, -149580, -130080, -38397, 60122,
107070, 84046, 16566, -48513, -74050, -52413, -4503, 37512,
50644, 32410, -1554, -29458, -36393, -21256, 4784, 25860, 30251, 0
);
function to_dfir_coeff_t(iv: integer_vector) return dfir_coeff_t;
end package dfir_coeff_lib;
package body dfir_coeff_lib is
function to_dfir_coeff_t(iv: integer_vector) return dfir_coeff_t is
variable ret : dfir_coeff_t(dfir_order downto 0);
begin
for i in 0 to dfir_order loop
ret(i) := to_signed(iv(i) ,27);
end loop;
return ret;
end function;
end package body dfir_coeff_lib;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.dfir_types.all;
package dfir_coeff_lib is
constant dfir_order : natural := 129;
type integer_vector is array(dfir_order downto 0) of integer;
constant dfir_coeff_content : integer_vector := (
30251, 25860, 4784, -21256, -36393, -29458, -1554, 32410,
50644, 37512, -4503, -52413, -74050, -48513, 16566, 84046,
107070, 60122, -38397, -130080, -149580, -69234, 74231, 193160,
200780, 71802, -129020, -276090, -259370, -62958, 208440, 381780,
323340, 36338, -319910, -514420, -390640, 16054, 473460, 680160,
458700, -106210, -685690, -891130, -526160, 252490, 985540, 1170900,
592070, -491400, -1436600, -1577800, -662630, 904470, 2199700, 2274900,
763940, -1750000, -3862800, -3974600, -1129700, 4365600, 10902000, 16178000,
18199000, 16178000, 10902000, 4365600, -1129700, -3974600, -3862800, -1750000,
763940, 2274900, 2199700, 904470, -662630, -1577800, -1436600, -491400,
592070, 1170900, 985540, 252490, -526160, -891130, -685690, -106210,
458700, 680160, 473460, 16054, -390640, -514420, -319910, 36338,
323340, 381780, 208440, -62958, -259370, -276090, -129020, 71802,
200780, 193160, 74231, -69234, -149580, -130080, -38397, 60122,
107070, 84046, 16566, -48513, -74050, -52413, -4503, 37512,
50644, 32410, -1554, -29458, -36393, -21256, 4784, 25860, 30251, 0
);
function to_dfir_coeff_t(iv: integer_vector) return dfir_coeff_t;
end package dfir_coeff_lib;
package body dfir_coeff_lib is
function to_dfir_coeff_t(iv: integer_vector) return dfir_coeff_t is
variable ret : dfir_coeff_t(dfir_order downto 0);
begin
for i in 0 to dfir_order loop
ret(i) := to_signed(iv(i) ,27);
end loop;
return ret;
end function;
end package body dfir_coeff_lib;
|
-- PCIEXP interface
constant CFG_PCIEXP : integer := CFG_PCIE;
constant CFG_PCIE_TYPE : integer := CFG_PCIETYPE;
constant CFG_PCIE_SIM_MAS : integer := CFG_PCIEMASTER;
constant CFG_PCIEXPVID : integer := 16#CONFIG_PCIEXP_VENDORID#;
constant CFG_PCIEXPDID : integer := 16#CONFIG_PCIEXP_DEVICEID#;
constant CFG_NO_OF_LANES : integer := CFG_LANE_WIDTH;
|
-- PCIEXP interface
constant CFG_PCIEXP : integer := CFG_PCIE;
constant CFG_PCIE_TYPE : integer := CFG_PCIETYPE;
constant CFG_PCIE_SIM_MAS : integer := CFG_PCIEMASTER;
constant CFG_PCIEXPVID : integer := 16#CONFIG_PCIEXP_VENDORID#;
constant CFG_PCIEXPDID : integer := 16#CONFIG_PCIEXP_DEVICEID#;
constant CFG_NO_OF_LANES : integer := CFG_LANE_WIDTH;
|
-- PCIEXP interface
constant CFG_PCIEXP : integer := CFG_PCIE;
constant CFG_PCIE_TYPE : integer := CFG_PCIETYPE;
constant CFG_PCIE_SIM_MAS : integer := CFG_PCIEMASTER;
constant CFG_PCIEXPVID : integer := 16#CONFIG_PCIEXP_VENDORID#;
constant CFG_PCIEXPDID : integer := 16#CONFIG_PCIEXP_DEVICEID#;
constant CFG_NO_OF_LANES : integer := CFG_LANE_WIDTH;
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 10416)
`protect data_block
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`protect end_protected
|
--================================================================================================================================
-- Copyright 2020 Bitvis
-- Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 and in the provided LICENSE.TXT.
--
-- Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on
-- an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and limitations under the License.
--================================================================================================================================
-- Note : Any functionality not explicitly described in the documentation is subject to change at any time
----------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.types_pkg.all;
use work.adaptations_pkg.all;
use work.methods_pkg.all;
use work.string_methods_pkg.all;
use work.data_queue_pkg.all;
package data_fifo_pkg is
shared variable shared_data_fifo : t_data_queue;
------------------------------------------
-- uvvm_fifo_init
------------------------------------------
-- This function allocates space in the buffer and returns an index that
-- must be used to access the FIFO.
--
-- - Parameters:
-- - buffer_size_in_bits (natural) - The size of the FIFO
--
-- - Returns: The index of the initiated FIFO (natural).
-- Returns 0 on error.
--
impure function uvvm_fifo_init(
buffer_size_in_bits : natural
) return natural;
------------------------------------------
-- uvvm_fifo_init
------------------------------------------
-- This procedure allocates space in the buffer at the given buffer_idx.
--
-- - Parameters:
-- - buffer_idx - The index of the FIFO (natural)
-- that shall be initialized.
-- - buffer_size_in_bits (natural) - The size of the FIFO
--
procedure uvvm_fifo_init(
buffer_idx : natural;
buffer_size_in_bits : natural
);
------------------------------------------
-- uvvm_fifo_put
------------------------------------------
-- This procedure puts data into a FIFO with index buffer_idx.
-- The size of the data is unconstrained, meaning that
-- it can be any size. Pushing data with a size that is
-- larger than the FIFO size results in wrapping, i.e.,
-- that when reaching the end the data remaining will over-
-- write the data that was written first.
--
-- - Parameters:
-- - buffer_idx - The index of the FIFO (natural)
-- that shall be pushed to.
-- - data - The data that shall be pushed (slv)
--
procedure uvvm_fifo_put(
buffer_idx : natural;
data : std_logic_vector
);
------------------------------------------
-- uvvm_fifo_get
------------------------------------------
-- This function returns the data from the FIFO
-- and removes the returned data from the FIFO.
--
-- - Parameters:
-- - buffer_idx - The index of the FIFO (natural)
-- that shall be read.
-- - entry_size_in_bits - The size of the returned slv (natural)
--
-- - Returns: Data from the FIFO (slv). The size of the
-- return data is given by the entry_size_in_bits parameter.
-- Attempting to get() from an empty FIFO is allowed but triggers a
-- TB_WARNING and returns garbage.
-- Attempting to get() a larger value than the FIFO size is allowed
-- but triggers a TB_WARNING.
--
--
impure function uvvm_fifo_get(
buffer_idx : natural;
entry_size_in_bits : natural
) return std_logic_vector;
------------------------------------------
-- uvvm_fifo_flush
------------------------------------------
-- This procedure empties the FIFO given
-- by buffer_idx.
--
-- - Parameters:
-- - buffer_idx - The index of the FIFO (natural)
-- that shall be flushed.
--
procedure uvvm_fifo_flush(
buffer_idx : natural
);
------------------------------------------
-- uvvm_fifo_peek
------------------------------------------
-- This function returns the data from the FIFO
-- without removing it.
--
-- - Parameters:
-- - buffer_idx - The index of the FIFO (natural)
-- that shall be read.
-- - entry_size_in_bits - The size of the returned slv (natural)
--
-- - Returns: Data from the FIFO. The size of the
-- return data is given by the entry_size_in_bits parameter.
-- Attempting to peek from an empty FIFO is allowed but triggers a
-- TB_WARNING and returns garbage.
-- Attempting to peek a larger value than the FIFO size is allowed
-- but triggers a TB_WARNING. Will wrap.
--
--
impure function uvvm_fifo_peek(
buffer_idx : natural;
entry_size_in_bits : natural
) return std_logic_vector;
------------------------------------------
-- uvvm_fifo_get_count
------------------------------------------
-- This function returns a natural indicating the number of elements
-- currently occupying the FIFO given by buffer_idx.
--
-- - Parameters:
-- - buffer_idx - The index of the FIFO (natural)
--
-- - Returns: The number of elements occupying the FIFO (natural).
--
--
impure function uvvm_fifo_get_count(
buffer_idx : natural
) return natural;
------------------------------------------
-- uvvm_fifo_get_max_count
------------------------------------------
-- This function returns a natural indicating the maximum number
-- of elements that can occupy the FIFO given by buffer_idx.
--
-- - Parameters:
-- - buffer_idx - The index of the FIFO (natural)
--
-- - Returns: The maximum number of elements that can be placed
-- in the FIFO (natural).
--
--
impure function uvvm_fifo_get_max_count(
buffer_idx : natural
) return natural;
------------------------------------------
-- uvvm_fifo_is_full
------------------------------------------
-- This function returns a boolean indicating if
-- the FIFO is full or not.
--
-- - Parameters:
-- - buffer_idx - The index of the FIFO (natural)
--
-- - Returns: TRUE if FIFO is full, else FALSE.
--
--
impure function uvvm_fifo_is_full(
buffer_idx : natural
) return boolean;
------------------------------------------
-- uvvm_fifo_deallocate
------------------------------------------
-- This procedure deallocates all the FIFOs
-- in the buffer.
--
procedure uvvm_fifo_deallocate(
dummy : t_void
);
end package data_fifo_pkg;
package body data_fifo_pkg is
impure function uvvm_fifo_init(
buffer_size_in_bits : natural
) return natural is
begin
return shared_data_fifo.init_queue(buffer_size_in_bits, "UVVM_FIFO");
end function;
procedure uvvm_fifo_init(
buffer_idx : natural;
buffer_size_in_bits : natural
) is
begin
shared_data_fifo.init_queue(buffer_idx, buffer_size_in_bits, "UVVM_FIFO");
end procedure;
procedure uvvm_fifo_put(
buffer_idx : natural;
data : std_logic_vector
) is
begin
shared_data_fifo.push_back(buffer_idx, data);
end procedure;
impure function uvvm_fifo_get(
buffer_idx : natural;
entry_size_in_bits : natural
) return std_logic_vector is
begin
return shared_data_fifo.pop_front(buffer_idx, entry_size_in_bits);
end function;
procedure uvvm_fifo_flush(
buffer_idx : natural
) is
begin
shared_data_fifo.flush(buffer_idx);
end procedure;
impure function uvvm_fifo_peek(
buffer_idx : natural;
entry_size_in_bits : natural
) return std_logic_vector is
begin
return shared_data_fifo.peek_front(buffer_idx, entry_size_in_bits);
end function;
impure function uvvm_fifo_get_count(
buffer_idx : natural
) return natural is
begin
return shared_data_fifo.get_count(buffer_idx);
end function;
impure function uvvm_fifo_get_max_count(
buffer_idx : natural
) return natural is
begin
return shared_data_fifo.get_queue_count_max(buffer_idx);
end function;
impure function uvvm_fifo_is_full(
buffer_idx : natural
) return boolean is
begin
return shared_data_fifo.get_queue_is_full(buffer_idx);
end function;
procedure uvvm_fifo_deallocate(
dummy : t_void
) is
begin
shared_data_fifo.deallocate_buffer(VOID);
end procedure;
end package body data_fifo_pkg;
|
---------------------------------------------------------------------------------------------
-- VIDEO DELAY - Slow Clock
--
-- Part of the Synkie Project: www.synkie.net
--
-- © 2013 Michael Egger, Licensed under GNU GPLv3
--
--------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity Slow_Clock is
port
(
Clk : in std_logic;
ResetN : in std_logic;
Ms1 : out std_logic; -- 1 ms clock cycle / 1000 Hz
Ms40 : out std_logic; -- 40 ms clock cycle / 25 Hz
Ms500 : out std_logic -- 2 hz
);
end entity;
--------------------------------------------------------------------------------------------
-- ARCHITECTURE
architecture Slow_Clock_Arch of Slow_Clock is
-- uncomment for real world
constant FCLK : positive := 156250000; -- clock cycles / second
constant CYC_P_MS : natural := FCLK / 2000;
-- for testing -> speed up
-- constant CYC_P_MS : natural := 10;
signal clk_int : std_logic;
signal clk2_int : std_logic;
signal clk3_int : std_logic;
begin
process(Clk, ResetN)
variable count : integer range 0 to CYC_P_MS := 0;
begin
if(ResetN = '0') then
count := 0;
elsif((Clk'event) and (Clk = '1')) then
if (count = CYC_P_MS - 1) then
count := 0;
clk_int <= not clk_int;
else
count := count + 1;
end if;
end if;
end process;
a40msclock: process(clk_int)
variable count : integer range 0 to 40 := 0;
begin
if((clk_int'event) and (clk_int = '1')) then
if (count = 39) then
count := 0;
clk2_int <= not clk2_int;
else
count := count + 1;
end if;
end if;
end process;
a500_ms_clock: process(clk_int)
variable count : integer range 0 to 500 := 0;
begin
if((clk_int'event) and (clk_int = '1')) then
if (count = 499) then
count := 0;
clk3_int <= not clk3_int;
else
count := count + 1;
end if;
end if;
end process;
Ms1 <= clk_int;
Ms40 <= clk2_int;
Ms500 <= clk3_int;
end Slow_Clock_Arch; |
entity foo is
end foo;
use std.textio.all;
architecture only of foo is
signal clock : bit;
begin -- only
process (clock)
variable x : integer := 0;
variable l : line;
begin -- process
write( l, string'( "x = " ) );
write( l, x );
writeline( output, l );
x := x + 1;
end process;
process
begin -- process
clock <= '1' after 1 ns,
'0' after 2 ns,
'1' after 3 ns;
wait;
end process;
end only;
|
entity foo is
end foo;
use std.textio.all;
architecture only of foo is
signal clock : bit;
begin -- only
process (clock)
variable x : integer := 0;
variable l : line;
begin -- process
write( l, string'( "x = " ) );
write( l, x );
writeline( output, l );
x := x + 1;
end process;
process
begin -- process
clock <= '1' after 1 ns,
'0' after 2 ns,
'1' after 3 ns;
wait;
end process;
end only;
|
entity foo is
end foo;
use std.textio.all;
architecture only of foo is
signal clock : bit;
begin -- only
process (clock)
variable x : integer := 0;
variable l : line;
begin -- process
write( l, string'( "x = " ) );
write( l, x );
writeline( output, l );
x := x + 1;
end process;
process
begin -- process
clock <= '1' after 1 ns,
'0' after 2 ns,
'1' after 3 ns;
wait;
end process;
end only;
|
--_________________________________________________________________________________________________
-- |
-- |The nanoFIP| |
-- |
-- CERN,BE/CO-HT |
--________________________________________________________________________________________________|
---------------------------------------------------------------------------------------------------
-- |
-- wf_reset_unit |
-- |
---------------------------------------------------------------------------------------------------
-- File wf_reset_unit.vhd |
-- |
-- Description The unit is responsible for the generation of the: |
-- |
-- o nanoFIP internal reset that resets all nanoFIP's logic, apart from WISHBONE. |
-- It is asserted: |
-- - after the assertion of the "nanoFIP User Interface General signal" RSTIN; |
-- in this case it stays active for 4 uclk cycles |
-- - after the reception of a var_rst with its 1st application-data byte |
-- containing the station's address; in this case as well it stays active for |
-- 4 uclk cycles |
-- - during the activation of the "nanoFIP User Interface General signal" RSTPON;|
-- in this case it stays active for as long as the RSTPON is active. |
-- __________ |
-- RSTIN | | \ \ |
-- ________| FSM |_______ \ \ |
-- | RSTIN | \ \ |
-- |__________| \ \ |
-- __________ | \ |
-- rst_nFIP_and_FD_p | | | | nFIP_rst |
-- ________| FSM |________ |OR | _______________ |
-- | var_rst | | | |
-- |__________| | / |
-- / / |
-- RSTPON / / |
-- __________________________ / / |
-- / / |
-- |
-- |
-- o FIELDRIVE reset: nanoFIP FIELDRIVE output FD_RSTN |
-- Same as the nanoFIP internal reset, it can be activated by the RSTIN, |
-- the var_rst or the RSTPON. |
-- Regarding the activation time, for the first two cases (RSTIN, var_rst) it stays|
-- asserted for 4 FD_TXCK cycles whereas in the case of the RSTPON, it stays active|
-- for as long as the RSTPON is active. |
-- |
-- __________ |
-- RSTIN | | \ \ |
-- ________| FSM |_______ \ \ |
-- | RSTIN | \ \ |
-- |__________| \ \ |
-- __________ | \ |
-- rst_nFIP_and_FD_p | | | | FD_RSTN |
-- ________| FSM |________ |OR | _______________ |
-- | var_rst | | | |
-- |__________| | / |
-- / / |
-- RSTPON / / |
-- __________________________ / / |
-- / / |
-- |
-- o reset to the external logic: "nanoFIP User Interface, General signal" RSTON |
-- It is asserted after the reception of a var_rst with its 2nd data byte |
-- containing the station's address. |
-- It stays active for 8 uclk cycles. |
-- _________ |
-- assert_RSTON_p | | RSTON |
-- ________| FSM |_________________________________ |
-- | var_rst | |
-- |__________| |
-- |
-- o nanoFIP internal reset for the WISHBONE logic: |
-- It is asserted after the assertion of the "nanoFIP User Interface, WISHBONE |
-- Slave" input RST_I or of the "nanoFIP User Interface General signal" RSTPON. |
-- It stays asserted for as long as the RST_I or RSTPON stay asserted. |
-- |
-- RSTPON |
-- __________________________ \ \ |
-- \ \ wb_rst |
-- RST_I |OR|____________________ |
-- __________________________ / / |
-- / / |
-- |
-- Notes: |
-- - The input signal RSTIN is considered only if it has been active for at least |
-- 4 uclk cycles; the functional specs define 8 uclks, but in reality we check for 4.|
-- - The pulses rst_nFIP_and_FD_p and assert_RSTON_p come from the wf_cons_outcome |
-- unit only after the sucessful validation of the frame structure and of the |
-- application-data bytes of the var_rst. |
-- - The RSTPON (Power On Reset generated with an RC circuit) removal is synchronized |
-- with both uclk and wb_clk. |
-- |
-- The unit implements 2 state machines: one for resets coming from RSTIN |
-- and one for resets coming from a var_rst. |
-- |
-- |
-- Authors Erik van der Bij ([email protected]) |
-- Pablo Alvarez Sanchez ([email protected]) |
-- Evangelia Gousiou ([email protected]) |
-- Date 11/2011 |
-- Version v0.03 |
-- Depends on wf_consumption |
---------------- |
-- Last changes |
-- 07/2009 v0.01 EB First version |
-- 08/2010 v0.02 EG checking of bytes1 and 2 of reset var added |
-- fd_rstn_o, nfip_rst_o enabled only if rstin has been active for>4 uclk |
-- 01/2011 v0.03 EG PoR added; signals assert_rston_p_i & rst_nfip_and_fd_p_i are inputs |
-- treated in the wf_cons_outcome; 2 state machines created; clean-up |
-- PoR also for internal WISHBONE resets |
-- 02/2011 v0.031 EG state nFIP_OFF_FD_OFF added |
-- 11/2011 v0.032 EG added s_rstin_c_is_full, s_var_rst_c_is_full signals that reset FSMs |
-- corrections on # cycles nFIP_rst is activated (was 6, now 4) |
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE |
-- ------------------------------------ |
-- This source file is free software; you can redistribute it and/or modify it under the terms of |
-- the GNU Lesser General Public License as published by the Free Software Foundation; either |
-- version 2.1 of the License, or (at your option) any later version. |
-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; |
-- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. |
-- See the GNU Lesser General Public License for more details. |
-- You should have received a copy of the GNU Lesser General Public License along with this |
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html |
---------------------------------------------------------------------------------------------------
--=================================================================================================
-- Libraries & Packages
--=================================================================================================
-- Standard library
library IEEE;
use IEEE.STD_LOGIC_1164.all; -- std_logic definitions
use IEEE.NUMERIC_STD.all; -- conversion functions
-- Specific library
library work;
use work.WF_PACKAGE.all; -- definitions of types, constants, entities
--=================================================================================================
-- Entity declaration for wf_reset_unit
--=================================================================================================
entity wf_reset_unit is port(
-- INPUTS
-- nanoFIP User Interface General signals
uclk_i : in std_logic; -- 40 MHz clock
rstin_a_i : in std_logic; -- initialization control, active low
rstpon_a_i : in std_logic; -- Power On Reset, active low
rate_i : in std_logic_vector (1 downto 0); -- WorldFIP bit rate
-- nanoFIP User Interface WISHBONE Slave
rst_i : in std_logic; -- WISHBONE reset
wb_clk_i : in std_logic; -- WISHBONE clock
-- Signal from the wf_consumption unit
rst_nfip_and_fd_p_i : in std_logic; -- indicates that a var_rst with its 1st byte
-- containing the station's address has been
-- correctly received
assert_rston_p_i : in std_logic; -- indicates that a var_rst with its 2nd byte
-- containing the station's address has been
-- correctly received
-- OUTPUTS
-- nanoFIP internal reset, to all the units
nfip_rst_o : out std_logic; -- nanoFIP internal reset, active high
-- resets all nanoFIP logic, apart from the WISHBONE
-- Signal to the wf_wb_controller
wb_rst_o : out std_logic; -- reset of the WISHBONE logic
-- nanoFIP User Interface General signal output
rston_o : out std_logic; -- reset output, active low
-- nanoFIP FIELDRIVE output
fd_rstn_o : out std_logic); -- FIELDRIVE reset, active low
end entity wf_reset_unit;
--=================================================================================================
-- architecture declaration
--=================================================================================================
architecture rtl of wf_reset_unit is
-- RSTIN and RSTPON synchronizers
signal s_rsti_synch : std_logic_vector (2 downto 0);
signal s_wb_por_synch, s_u_por_synch : std_logic_vector (1 downto 0);
-- FSM for RSTIN
type rstin_st_t is (IDLE, RSTIN_EVAL, nFIP_ON_FD_ON, nFIP_OFF_FD_ON, nFIP_OFF_FD_OFF);
signal rstin_st, nx_rstin_st : rstin_st_t;
-- RSTIN counter
signal s_rstin_c, s_var_rst_c : unsigned (c_2_PERIODS_COUNTER_LGTH-1 downto 0);
signal s_rstin_c_reinit, s_rstin_c_is_three : std_logic;
signal s_rstin_c_is_seven, s_rstin_c_is_4txck : std_logic;
signal s_rstin_c_is_full : std_logic;
-- resets generated after a RSTIN
signal s_rstin_nfip, s_rstin_fd : std_logic;
-- FSM for var_rst
type var_rst_st_t is (VAR_RST_IDLE, VAR_RST_RSTON_ON, VAR_RST_nFIP_ON_FD_ON_RSTON_ON,
VAR_RST_nFIP_OFF_FD_ON_RSTON_ON, VAR_RST_nFIP_ON_FD_ON,
VAR_RST_nFIP_OFF_FD_ON_RSTON_OFF);
signal var_rst_st, nx_var_rst_st : var_rst_st_t;
-- var_rst counter
signal s_var_rst_c_reinit, s_var_rst_c_is_three : std_logic;
signal s_var_rst_c_is_seven, s_var_rst_c_is_4txck : std_logic;
signal s_var_rst_c_is_full : std_logic;
-- resets generated after a var_rst
signal s_var_rst_fd, s_var_rst_nfip, s_rston : std_logic;
-- info needed to define the length of the FD_RSTN
signal s_transm_period : unsigned (c_PERIODS_COUNTER_LGTH - 1 downto 0);
signal s_txck_four_periods : unsigned (c_2_PERIODS_COUNTER_LGTH-1 downto 0);
--=================================================================================================
-- architecture begin
--=================================================================================================
begin
s_transm_period <= c_BIT_RATE_UCLK_TICKS(to_integer(unsigned(rate_i)));-- # uclk ticks of a
-- transmission period
s_txck_four_periods <= resize(s_transm_period, s_txck_four_periods'length) sll 1;-- # uclk ticks
-- of 2 transm.
-- periods = 4
-- FD_TXCK periods
---------------------------------------------------------------------------------------------------
-- Input Synchronizers --
---------------------------------------------------------------------------------------------------
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- RSTIN synchronization with the uclk, using a set of 3 registers.
RSTIN_uclk_Synchronizer: process (uclk_i)
begin
if rising_edge (uclk_i) then
s_rsti_synch <= s_rsti_synch (1 downto 0) & not rstin_a_i;
end if;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- RSTPON synchronization, with the wb_clk.
-- The second flip-flop is used to remove metastabilities.
PoR_wb_clk_Synchronizer: process (wb_clk_i, rstpon_a_i)
begin
if rstpon_a_i = '0' then
s_wb_por_synch <= (others => '1');
elsif rising_edge (wb_clk_i) then
s_wb_por_synch <= s_wb_por_synch(0) & '0';
end if;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- RSTPON synchronization, with the uclk.
-- The second flip-flop is used to remove metastabilities.
PoR_uclk_Synchronizer: process (uclk_i, rstpon_a_i)
begin
if rstpon_a_i = '0' then
s_u_por_synch <= (others => '1');
elsif rising_edge (uclk_i) then
s_u_por_synch <= s_u_por_synch(0) & '0';
end if;
end process;
---------------------------------------------------------------------------------------------------
-- RSTIN --
---------------------------------------------------------------------------------------------------
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- RSTIN FSM: the state machine is divided in three parts (a clocked process
-- to store the current state, a combinatorial process to manage state transitions and finally a
-- combinatorial process to manage the output signals), which are the three processes that follow.
-- The FSM is following the "User Interface, General signal" RSTIN and checks whether it stays
-- active for at least 4 uclk cycles; if so, it enables the nanoFIP internal reset (s_rstin_nfip)
-- and the FIELDRIVE reset (s_rstin_fd). The nanoFIP internal reset stays active for 4 uclk cycles
-- and the FIELDRIVE for 4 FD_TXCK cycles.
-- The state machine can be reset by the Power On Reset and the variable reset.
-- Note: The same counter is used for the evaluation of the RSTIN (if it is >= 4 uclk) and for the
-- generation of the two reset signals.
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Synchronous process RSTIN_FSM_Sync: Storage of the current state of the FSM.
RSTIN_FSM_Sync: process (uclk_i)
begin
if rising_edge (uclk_i) then
if s_u_por_synch(1) = '1' or rst_nfip_and_fd_p_i = '1' or s_rstin_c_is_full = '1' then
rstin_st <= IDLE;
else
rstin_st <= nx_rstin_st;
end if;
end if;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Combinatorial process RSTIN_FSM_Comb_State_Transitions: definition of the state
-- transitions of the FSM.
RSTIN_FSM_Comb_State_Transitions: process (rstin_st, s_rsti_synch(2), s_rstin_c_is_three,
s_rstin_c_is_seven, s_rstin_c_is_4txck)
begin
case rstin_st is
when IDLE =>
if s_rsti_synch(2) = '1' then -- RSTIN active
nx_rstin_st <= RSTIN_EVAL;
else
nx_rstin_st <= IDLE;
end if;
when RSTIN_EVAL =>
if s_rsti_synch(2) = '0' then -- RSTIN deactivated
nx_rstin_st <= IDLE;
else
if s_rstin_c_is_three = '1' then -- counting the uclk cycles that
nx_rstin_st <= nFIP_ON_FD_ON; -- RSTIN is active
else
nx_rstin_st <= RSTIN_EVAL;
end if;
end if;
when nFIP_ON_FD_ON =>
if s_rstin_c_is_seven = '1' then -- nanoFIP internal reset and
nx_rstin_st <= nFIP_OFF_FD_ON; -- FIELDRIVE reset active for
-- 4 uclk cycles
else
nx_rstin_st <= nFIP_ON_FD_ON;
end if;
when nFIP_OFF_FD_ON =>
-- nanoFIP internal reset deactivated
if s_rstin_c_is_4txck = '1' then -- FIELDRIVE reset continues being active
nx_rstin_st <= nFIP_OFF_FD_OFF;-- until 4 FD_TXCK cycles have passed
else
nx_rstin_st <= nFIP_OFF_FD_ON;
end if;
when nFIP_OFF_FD_OFF =>
if s_rsti_synch(2) = '1' then -- RSTIN still active
nx_rstin_st <= nFIP_OFF_FD_OFF;
else
nx_rstin_st <= IDLE;
end if;
when OTHERS =>
nx_rstin_st <= IDLE;
end case;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Combinatorial process RSTIN_FSM_Comb_Output_Signals: definition of the output signals of
-- the FSM. The process is handling the signals for the nanoFIP internal reset (s_rstin_nfip)
-- and the FIELDRIVE reset (s_rstin_fd), as well as the inputs of the RSTIN_free_counter.
RSTIN_FSM_Comb_Output_Signals: process (rstin_st)
begin
case rstin_st is
when IDLE =>
s_rstin_c_reinit <= '1'; -- counter initialized
s_rstin_nfip <= '0';
s_rstin_fd <= '0';
when RSTIN_EVAL =>
s_rstin_c_reinit <= '0'; -- counting until 4
-- if RSTIN is active
s_rstin_nfip <= '0';
s_rstin_fd <= '0';
when nFIP_ON_FD_ON =>
s_rstin_c_reinit <= '0'; -- free counter counting 4 uclk cycles
-------------------------------------
s_rstin_fd <= '1'; -- FIELDRIVE active
s_rstin_nfip <= '1'; -- nFIP internal active
-------------------------------------
when nFIP_OFF_FD_ON =>
s_rstin_c_reinit <= '0'; -- free counter counting until 4 FD_TXCK
s_rstin_nfip <= '0';
-------------------------------------
s_rstin_fd <= '1'; -- FIELDRIVE active
-------------------------------------
when nFIP_OFF_FD_OFF =>
s_rstin_c_reinit <= '1'; -- no counting
s_rstin_nfip <= '0';
s_rstin_fd <= '0';
when OTHERS =>
s_rstin_c_reinit <= '1'; -- no counting
s_rstin_fd <= '0';
s_rstin_nfip <= '0';
end case;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Instantiation of a wf_incr_counter: the counter counts from 0 to 4 FD_TXCK.
-- In case something goes wrong and the counter continues conting after the 4 FD_TXCK, the
-- s_rstin_c_is_full will be activated and the FSM will be reset.
RSTIN_free_counter: wf_incr_counter
generic map(g_counter_lgth => c_2_PERIODS_COUNTER_LGTH)
port map(
uclk_i => uclk_i,
counter_reinit_i => s_rstin_c_reinit,
counter_incr_i => '1',
----------------------------------------
counter_is_full_o => s_rstin_c_is_full,
counter_o => s_rstin_c);
----------------------------------------
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
s_rstin_c_is_three <= '1' when s_rstin_c = to_unsigned(3, s_rstin_c'length) else '0';
s_rstin_c_is_seven <= '1' when s_rstin_c = to_unsigned(7, s_rstin_c'length) else '0';
s_rstin_c_is_4txck <= '1' when s_rstin_c = s_txck_four_periods + 3 else '0';
-- +3 bc of the first 4 RSTIN evaluation cycles
---------------------------------------------------------------------------------------------------
-- var_rst --
---------------------------------------------------------------------------------------------------
-- Resets_after_a_var_rst FSM: the state machine is divided in three parts (a clocked process
-- to store the current state, a combinatorial process to manage state transitions and finally a
-- combinatorial process to manage the output signals), which are the three processes that follow.
-- If after the reception of a var_rst the signal assert_rston_p_i is asserted, the FSM
-- asserts the "nanoFIP user Interface General signal" RSTON for 8 uclk cycles.
-- If after the reception of a var_rst the signal rst_nfip_and_fd_p_i is asserted, the FSM
-- asserts the nanoFIP internal reset (s_var_rst_nfip) for 4 uclk cycles and the
-- "nanoFIP FIELDRIVE" output (s_var_rst_fd) for 4 FD_TXCK cycles.
-- If after the reception of a var_rst both assert_rston_p_i and rst_nfip_and_fd_p_i
-- are asserted, the FSM asserts the s_var_rst_nfip for 2 uclk cycles, the RSTON for 8
-- uclk cycles and the s_var_rst_fd for 4 FD_TXCK cycles.
-- The same counter is used for all the countings!
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Synchronous process Resets_after_a_var_rst_synch: Storage of the current state of the FSM
-- The state machine can be reset by the Power On Reset and the nanoFIP internal reset from RSTIN.
Resets_after_a_var_rst_synch: process (uclk_i)
begin
if rising_edge (uclk_i) then
if s_u_por_synch(1) = '1' or s_rstin_nfip = '1' or s_var_rst_c_is_full = '1' then
var_rst_st <= VAR_RST_IDLE;
else
var_rst_st <= nx_var_rst_st;
end if;
end if;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Combinatorial process Resets_after_a_var_rst_Comb_State_Transitions: definition of the
-- state transitions of the FSM.
Resets_after_a_var_rst_Comb_State_Transitions: process (var_rst_st, rst_nfip_and_fd_p_i,
assert_rston_p_i, s_var_rst_c_is_three,
s_var_rst_c_is_seven,
s_var_rst_c_is_4txck)
begin
case var_rst_st is
when VAR_RST_IDLE =>
if assert_rston_p_i = '1' and rst_nfip_and_fd_p_i = '1' then
nx_var_rst_st <= VAR_RST_nFIP_ON_FD_ON_RSTON_ON;
elsif assert_rston_p_i = '1' then
nx_var_rst_st <= VAR_RST_RSTON_ON;
elsif rst_nfip_and_fd_p_i = '1' then
nx_var_rst_st <= VAR_RST_nFIP_ON_FD_ON;
else
nx_var_rst_st <= VAR_RST_IDLE;
end if;
when VAR_RST_RSTON_ON => -- for 8 uclk cycles
if s_var_rst_c_is_seven = '1' then
nx_var_rst_st <= VAR_RST_IDLE;
else
nx_var_rst_st <= VAR_RST_RSTON_ON;
end if;
when VAR_RST_nFIP_ON_FD_ON_RSTON_ON => -- for 4 uclk cycles
if s_var_rst_c_is_three = '1' then
nx_var_rst_st <= VAR_RST_nFIP_OFF_FD_ON_RSTON_ON;
else
nx_var_rst_st <= VAR_RST_nFIP_ON_FD_ON_RSTON_ON;
end if;
when VAR_RST_nFIP_OFF_FD_ON_RSTON_ON => -- for 4 more uclk cycles
if s_var_rst_c_is_seven = '1' then
nx_var_rst_st <= VAR_RST_nFIP_OFF_FD_ON_RSTON_OFF;
else
nx_var_rst_st <= VAR_RST_nFIP_OFF_FD_ON_RSTON_ON;
end if;
when VAR_RST_nFIP_ON_FD_ON => -- for 4 uclk cycles
if s_var_rst_c_is_three = '1' then
nx_var_rst_st <= VAR_RST_nFIP_OFF_FD_ON_RSTON_OFF;
else
nx_var_rst_st <= VAR_RST_nFIP_ON_FD_ON;
end if;
when VAR_RST_nFIP_OFF_FD_ON_RSTON_OFF => -- until 4 TXCK
if s_var_rst_c_is_4txck = '1' then
nx_var_rst_st <= VAR_RST_IDLE;
else
nx_var_rst_st <= VAR_RST_nFIP_OFF_FD_ON_RSTON_OFF;
end if;
when OTHERS =>
nx_var_rst_st <= VAR_RST_IDLE;
end case;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Combinatorial process RSTIN_FSM_Comb_Output_Signals: definition of the output signals of
-- the FSM. The process is managing the signals for the nanoFIP internal reset and the FIELDRIVE
-- reset, as well as the arguments of the counter.
rst_var_FSM_Comb_Output_Signals: process (var_rst_st)
begin
case var_rst_st is
when VAR_RST_IDLE =>
s_var_rst_c_reinit <= '1'; -- counter initialized
s_rston <= '1';
s_var_rst_nfip <= '0';
s_var_rst_fd <= '0';
when VAR_RST_RSTON_ON =>
s_var_rst_c_reinit <= '0'; -- counting 8 uclk cycles
-------------------------------------
s_rston <= '0'; -- RSTON active
-------------------------------------
s_var_rst_nfip <= '0';
s_var_rst_fd <= '0';
when VAR_RST_nFIP_ON_FD_ON_RSTON_ON =>
s_var_rst_c_reinit <= '0'; -- counting 4 uclk cycles
-------------------------------------
s_rston <= '0'; -- RSTON active
s_var_rst_nfip <= '1'; -- nFIP internal active
s_var_rst_fd <= '1'; -- FIELDRIVE active
-------------------------------------
when VAR_RST_nFIP_OFF_FD_ON_RSTON_ON =>
s_var_rst_c_reinit <= '0'; -- counting 4 uclk cycles
s_var_rst_nfip <= '0';
-------------------------------------
s_rston <= '0'; -- RSTON active
s_var_rst_fd <= '1'; -- FIELDRIVE active
-------------------------------------
when VAR_RST_nFIP_ON_FD_ON =>
s_var_rst_c_reinit <= '0'; -- counting 4 uclk cycles
s_rston <= '1';
-------------------------------------
s_var_rst_nfip <= '1'; -- nFIP internal active
s_var_rst_fd <= '1'; -- FIELDRIVE active
-------------------------------------
when VAR_RST_nFIP_OFF_FD_ON_RSTON_OFF =>
s_var_rst_c_reinit <= '0'; -- counting until 4 FD_TXCK cycles
s_rston <= '1';
s_var_rst_nfip <= '0';
-------------------------------------
s_var_rst_fd <= '1'; -- FIELDRIVE active
-------------------------------------
when OTHERS =>
s_var_rst_c_reinit <= '1'; -- no counting
s_rston <= '1';
s_var_rst_nfip <= '0';
s_var_rst_fd <= '0';
end case;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Instantiation of a wf_incr_counter:
-- the counter counts from 0 to 8, if only assert_RSTON_p has been activated, or
-- from 0 to 4 * FD_TXCK, if rst_nfip_and_fd_p_i has been activated.
-- In case something goes wrong and the counter continues conting after the 4 FD_TXCK, the
-- s_var_rst_c_is_full will be activated and the FSM will be reset.
free_counter: wf_incr_counter
generic map(g_counter_lgth => c_2_PERIODS_COUNTER_LGTH)
port map(
uclk_i => uclk_i,
counter_reinit_i => s_var_rst_c_reinit,
counter_incr_i => '1',
----------------------------------------
counter_is_full_o => s_var_rst_c_is_full,
counter_o => s_var_rst_c);
----------------------------------------
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
s_var_rst_c_is_seven <= '1' when s_var_rst_c = to_unsigned(7, s_var_rst_c'length) else '0';
s_var_rst_c_is_three <= '1' when s_var_rst_c = to_unsigned(3, s_var_rst_c'length) else '0';
s_var_rst_c_is_4txck <= '1' when s_var_rst_c = s_txck_four_periods -1 else '0';
---------------------------------------------------------------------------------------------------
-- Output Signals --
---------------------------------------------------------------------------------------------------
wb_rst_o <= rst_i or s_wb_por_synch(1);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
nfip_rst_o <= s_rstin_nfip or s_var_rst_nfip or s_u_por_synch(1);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Flip-flop with asynchronous reset to be sure that whenever nanoFIP is reset the user is not
RSTON_Buffering: process (uclk_i, s_u_por_synch(1), s_rstin_nfip, s_var_rst_nfip)
begin
if s_rstin_nfip = '1' or s_var_rst_nfip = '1' or s_u_por_synch(1) = '1' then
rston_o <= '1';
elsif rising_edge (uclk_i) then
rston_o <= s_rston;
end if;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- FIELDRIVE reset
FD_RST_Buffering: process (uclk_i)
begin
if rising_edge (uclk_i) then
fd_rstn_o <= not (s_rstin_fd or s_var_rst_fd or s_u_por_synch(1));
end if;
end process;
end architecture rtl;
--=================================================================================================
-- architecture end
--=================================================================================================
---------------------------------------------------------------------------------------------------
-- E N D O F F I L E
--------------------------------------------------------------------------------------------------- |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_03_tb_03_03.vhd,v 1.3 2001-10-26 16:29:33 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
entity test_bench_03_03 is
end entity test_bench_03_03;
library ieee;
use ieee.std_logic_1164.all;
architecture test_mux4_demo of test_bench_03_03 is
signal sel : work.test_bench_03_02.sel_range := 0;
signal d0, d1, d2, d3, z : std_ulogic;
begin
dut : entity work.mux4(demo)
port map ( sel => sel,
d0 => d0, d1 => d1, d2 => d2, d3 => d3,
z => z );
stimulus : process is
begin
wait for 5 ns;
d0 <= '1'; wait for 5 ns;
d1 <= 'H'; wait for 5 ns;
sel <= 1; wait for 5 ns;
d1 <= 'L'; wait for 5 ns;
sel <= 2; wait for 5 ns;
d0 <= '0'; wait for 5 ns;
d2 <= '1'; wait for 5 ns;
d2 <= '0'; wait for 5 ns;
sel <= 3; wait for 5 ns;
d3 <= '1'; wait for 5 ns;
d3 <= '0'; wait for 5 ns;
wait;
end process stimulus;
end architecture test_mux4_demo;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_03_tb_03_03.vhd,v 1.3 2001-10-26 16:29:33 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
entity test_bench_03_03 is
end entity test_bench_03_03;
library ieee;
use ieee.std_logic_1164.all;
architecture test_mux4_demo of test_bench_03_03 is
signal sel : work.test_bench_03_02.sel_range := 0;
signal d0, d1, d2, d3, z : std_ulogic;
begin
dut : entity work.mux4(demo)
port map ( sel => sel,
d0 => d0, d1 => d1, d2 => d2, d3 => d3,
z => z );
stimulus : process is
begin
wait for 5 ns;
d0 <= '1'; wait for 5 ns;
d1 <= 'H'; wait for 5 ns;
sel <= 1; wait for 5 ns;
d1 <= 'L'; wait for 5 ns;
sel <= 2; wait for 5 ns;
d0 <= '0'; wait for 5 ns;
d2 <= '1'; wait for 5 ns;
d2 <= '0'; wait for 5 ns;
sel <= 3; wait for 5 ns;
d3 <= '1'; wait for 5 ns;
d3 <= '0'; wait for 5 ns;
wait;
end process stimulus;
end architecture test_mux4_demo;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_03_tb_03_03.vhd,v 1.3 2001-10-26 16:29:33 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
entity test_bench_03_03 is
end entity test_bench_03_03;
library ieee;
use ieee.std_logic_1164.all;
architecture test_mux4_demo of test_bench_03_03 is
signal sel : work.test_bench_03_02.sel_range := 0;
signal d0, d1, d2, d3, z : std_ulogic;
begin
dut : entity work.mux4(demo)
port map ( sel => sel,
d0 => d0, d1 => d1, d2 => d2, d3 => d3,
z => z );
stimulus : process is
begin
wait for 5 ns;
d0 <= '1'; wait for 5 ns;
d1 <= 'H'; wait for 5 ns;
sel <= 1; wait for 5 ns;
d1 <= 'L'; wait for 5 ns;
sel <= 2; wait for 5 ns;
d0 <= '0'; wait for 5 ns;
d2 <= '1'; wait for 5 ns;
d2 <= '0'; wait for 5 ns;
sel <= 3; wait for 5 ns;
d3 <= '1'; wait for 5 ns;
d3 <= '0'; wait for 5 ns;
wait;
end process stimulus;
end architecture test_mux4_demo;
|
library ieee;
use ieee.std_logic_1164.all;
entity c_not is
generic
(
width : integer := 1
);
port
(
input : std_logic_vector((width - 1) downto 0);
output : out std_logic_vector((width - 1) downto 0)
);
end c_not;
architecture behavior of c_not is
begin
P0 : process (input)
variable result : std_logic_vector(width - 1 downto 0);
begin
outer : for n in width - 1 downto 0 loop
result(n) := not input(n);
end loop outer;
output <= result;
end process P0;
end behavior; |
library ieee;
use ieee.std_logic_1164.all;
entity c_not is
generic
(
width : integer := 1
);
port
(
input : std_logic_vector((width - 1) downto 0);
output : out std_logic_vector((width - 1) downto 0)
);
end c_not;
architecture behavior of c_not is
begin
P0 : process (input)
variable result : std_logic_vector(width - 1 downto 0);
begin
outer : for n in width - 1 downto 0 loop
result(n) := not input(n);
end loop outer;
output <= result;
end process P0;
end behavior; |
-------------------------------
---- Project: EurySPACE CCSDS RX/TX with wishbone interface
---- Design Name: ccsds_rxtx_types
---- Version: 1.0.0
---- Description:
---- TO BE DONE
-------------------------------
---- Author(s):
---- Guillaume Rembert
-------------------------------
---- Licence:
---- MIT
-------------------------------
---- Changes list:
---- 2017/01/15: initial release
-------------------------------
-- libraries used
library ieee;
use ieee.std_logic_1164.all;
package ccsds_rxtx_types is
type std_logic_vector_array is array (natural range <>, natural range <>) of std_logic;
type boolean_array is array (natural range <>) of boolean;
end ccsds_rxtx_types;
|
-- Test extended identifiers
architecture foo of bar is
signal \foo bar\ : integer;
signal \a\\b\ : integer;
signal \Thing!!! \ : integer;
signal \name\ : integer;
signal name : integer;
begin
\foo.bar.baz\ <= \hello\;
end architecture;
|
-- Test extended identifiers
architecture foo of bar is
signal \foo bar\ : integer;
signal \a\\b\ : integer;
signal \Thing!!! \ : integer;
signal \name\ : integer;
signal name : integer;
begin
\foo.bar.baz\ <= \hello\;
end architecture;
|
-- Test extended identifiers
architecture foo of bar is
signal \foo bar\ : integer;
signal \a\\b\ : integer;
signal \Thing!!! \ : integer;
signal \name\ : integer;
signal name : integer;
begin
\foo.bar.baz\ <= \hello\;
end architecture;
|
-- Test extended identifiers
architecture foo of bar is
signal \foo bar\ : integer;
signal \a\\b\ : integer;
signal \Thing!!! \ : integer;
signal \name\ : integer;
signal name : integer;
begin
\foo.bar.baz\ <= \hello\;
end architecture;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: syncrambw
-- File: syncrambw.vhd
-- Author: Jan Andersson - Aeroflex Gaisler
-- Description: Synchronous 1-port ram with 8-bit write strobes
-- and tech selection
------------------------------------------------------------------------------
library ieee;
library techmap;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
use techmap.allmem.all;
library grlib;
use grlib.config.all;
use grlib.config_types.all;
use grlib.stdlib.all;
entity syncrambw is
generic (tech : integer := 0; abits : integer := 6; dbits : integer := 8;
testen : integer := 0; custombits: integer := 1);
port (
clk : in std_ulogic;
address : in std_logic_vector (abits-1 downto 0);
datain : in std_logic_vector (dbits-1 downto 0);
dataout : out std_logic_vector (dbits-1 downto 0);
enable : in std_logic_vector (dbits/8-1 downto 0);
write : in std_logic_vector (dbits/8-1 downto 0);
testin : in std_logic_vector (TESTIN_WIDTH-1 downto 0) := testin_none;
customclk: in std_ulogic := '0';
customin : in std_logic_vector((dbits/8)*custombits-1 downto 0) := (others => '0');
customout:out std_logic_vector((dbits/8)*custombits-1 downto 0));
end;
architecture rtl of syncrambw is
constant nctrl : integer := abits + (TESTIN_WIDTH-2) + 2*dbits/8;
signal dataoutx, databp, testdata : std_logic_vector((dbits -1) downto 0);
constant SCANTESTBP : boolean := (testen = 1) and (tech /= 0) and (tech /= ut90);
signal xenable, xwrite : std_logic_vector(dbits/8-1 downto 0);
signal custominx,customoutx: std_logic_vector(syncram_customif_maxwidth downto 0);
begin
xenable <= enable when testen=0 or testin(TESTIN_WIDTH-2)='0' else (others => '0');
xwrite <= write when testen=0 or testin(TESTIN_WIDTH-2)='0' else (others => '0');
sbw : if has_srambw(tech) = 1 generate
-- RAM bypass for scan
scanbp : if SCANTESTBP generate
comb : process (address, datain, enable, write, testin)
variable tmp : std_logic_vector((dbits -1) downto 0);
variable ctrlsigs : std_logic_vector((nctrl -1) downto 0);
begin
ctrlsigs := testin(TESTIN_WIDTH-3 downto 0) & write & enable & address;
tmp := datain;
for i in 0 to nctrl-1 loop
tmp(i mod dbits) := tmp(i mod dbits) xor ctrlsigs(i);
end loop;
testdata <= tmp;
end process;
reg : process (clk)
begin
if rising_edge(clk) then
databp <= testdata;
end if;
end process;
dmuxout : for i in 0 to dbits-1 generate
x0: grmux2 generic map (tech)
port map (dataoutx(i), databp(i), testin(TESTIN_WIDTH-1), dataout(i));
end generate;
end generate;
noscanbp : if not SCANTESTBP generate dataout <= dataoutx; end generate;
n2x : if tech = easic45 generate
x0 : n2x_syncram_be generic map (abits, dbits)
port map (clk, address, datain, dataout, xenable, xwrite);
end generate;
customout(customout'high downto custombits) <= (others => '0');
customout(custombits-1 downto 0) <= customoutx(custombits-1 downto 0);
-- pragma translate_off
dmsg : if GRLIB_CONFIG_ARRAY(grlib_debug_level) >= 2 generate
x : process
begin
assert false report "syncrambw: " & tost(2**abits) & "x" & tost(dbits) &
" (" & tech_table(tech) & ")"
severity note;
wait;
end process;
end generate;
-- pragma translate_on
end generate;
nosbw : if has_srambw(tech) = 0 generate
rx : for i in 0 to dbits/8-1 generate
x0 : syncram generic map (tech, abits, 8, testen, custombits)
port map (clk, address, datain(i*8+7 downto i*8),
dataoutx(i*8+7 downto i*8), enable(i), write(i), testin,
customclk, customin((i+1)*custombits-1 downto i*custombits),
customout((i+1)*custombits-1 downto i*custombits));
end generate;
dataout <= dataoutx;
end generate;
custominx(custominx'high downto (dbits/8)*custombits) <= (others => '0');
custominx((dbits/8)*custombits-1 downto 0) <= customin;
nocust: if has_srambw(tech)=0 or syncram_has_customif(tech)=0 generate
customoutx <= (others => '0');
end generate;
end;
|
-- The Potato Processor - A simple processor for FPGAs
-- (c) Kristian Klomsten Skordal 2014 - 2015 <[email protected]>
-- Report bugs and issues on <https://github.com/skordal/potato/issues>
library ieee;
use ieee.std_logic_1164.all;
use work.pp_types.all;
--! @brief Simple priority-based wishbone arbiter.
--! This module is used as an arbiter between the instruction and data caches.
entity pp_wb_arbiter is
port(
clk : in std_logic;
reset : in std_logic;
-- Wishbone input 1:
m1_inputs : out wishbone_master_inputs;
m1_outputs : in wishbone_master_outputs;
-- Wishbone input 2:
m2_inputs : out wishbone_master_inputs;
m2_outputs : in wishbone_master_outputs;
-- Wishbone interface:
wb_adr_out : out std_logic_vector(31 downto 0);
wb_sel_out : out std_logic_vector( 3 downto 0);
wb_cyc_out : out std_logic;
wb_stb_out : out std_logic;
wb_we_out : out std_logic;
wb_dat_out : out std_logic_vector(31 downto 0);
wb_dat_in : in std_logic_vector(31 downto 0);
wb_ack_in : in std_logic
);
end entity pp_wb_arbiter;
architecture behaviour of pp_wb_arbiter is
type state_type is (IDLE, M1_BUSY, M2_BUSY);
signal state : state_type := IDLE;
begin
m1_inputs <= (ack => wb_ack_in, dat => wb_dat_in) when state = M1_BUSY else (ack => '0', dat => (others => '0'));
m2_inputs <= (ack => wb_ack_in, dat => wb_dat_in) when state = M2_BUSY else (ack => '0', dat => (others => '0'));
output_mux: process(state, m1_outputs, m2_outputs)
begin
case state is
when IDLE =>
wb_adr_out <= (others => '0');
wb_sel_out <= (others => '0');
wb_dat_out <= (others => '0');
wb_cyc_out <= '0';
wb_stb_out <= '0';
wb_we_out <= '0';
when M1_BUSY =>
wb_adr_out <= m1_outputs.adr;
wb_sel_out <= m1_outputs.sel;
wb_dat_out <= m1_outputs.dat;
wb_cyc_out <= m1_outputs.cyc;
wb_stb_out <= m1_outputs.stb;
wb_we_out <= m1_outputs.we;
when M2_BUSY =>
wb_adr_out <= m2_outputs.adr;
wb_sel_out <= m2_outputs.sel;
wb_dat_out <= m2_outputs.dat;
wb_cyc_out <= m2_outputs.cyc;
wb_stb_out <= m2_outputs.stb;
wb_we_out <= m2_outputs.we;
end case;
end process output_mux;
controller: process(clk)
begin
if rising_edge(clk) then
if reset = '1' then
state <= IDLE;
else
case state is
when IDLE =>
if m1_outputs.cyc = '1' then
state <= M1_BUSY;
elsif m2_outputs.cyc = '1' then
state <= M2_BUSY;
end if;
when M1_BUSY =>
if m1_outputs.cyc = '0' then
state <= IDLE;
end if;
when M2_BUSY =>
if m2_outputs.cyc = '0' then
state <= IDLE;
end if;
end case;
end if;
end if;
end process controller;
end architecture behaviour;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: k7_mBuf_128x72_dverif.vhd
--
-- Description:
-- Used for FIFO read interface stimulus generation and data checking
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.k7_mBuf_128x72_pkg.ALL;
ENTITY k7_mBuf_128x72_dverif IS
GENERIC(
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_USE_EMBEDDED_REG : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT(
RESET : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
PRC_RD_EN : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
RD_EN : OUT STD_LOGIC;
DOUT_CHK : OUT STD_LOGIC
);
END ENTITY;
ARCHITECTURE fg_dv_arch OF k7_mBuf_128x72_dverif IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT EXTRA_WIDTH : INTEGER := if_then_else(C_CH_TYPE = 2,1,0);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH+EXTRA_WIDTH,8);
SIGNAL expected_dout : STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL data_chk : STD_LOGIC := '1';
SIGNAL rand_num : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 downto 0);
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL pr_r_en : STD_LOGIC := '0';
SIGNAL rd_en_d1 : STD_LOGIC := '0';
BEGIN
DOUT_CHK <= data_chk;
RD_EN <= rd_en_i;
rd_en_i <= PRC_RD_EN;
data_fifo_chk:IF(C_CH_TYPE /=2) GENERATE
-------------------------------------------------------
-- Expected data generation and checking for data_fifo
-------------------------------------------------------
PROCESS (RD_CLK,RESET)
BEGIN
IF (RESET = '1') THEN
rd_en_d1 <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
IF(EMPTY = '0' AND rd_en_i='1' AND rd_en_d1 = '0') THEN
rd_en_d1 <= '1';
END IF;
END IF;
END PROCESS;
pr_r_en <= rd_en_i AND NOT EMPTY AND rd_en_d1;
expected_dout <= rand_num(C_DOUT_WIDTH-1 DOWNTO 0);
gen_num:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
rd_gen_inst2:k7_mBuf_128x72_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+N
)
PORT MAP(
CLK => RD_CLK,
RESET => RESET,
RANDOM_NUM => rand_num(8*(N+1)-1 downto 8*N),
ENABLE => pr_r_en
);
END GENERATE;
PROCESS (RD_CLK,RESET)
BEGIN
IF(RESET = '1') THEN
data_chk <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
IF((EMPTY = '0') AND (rd_en_i = '1' AND rd_en_d1 = '1')) THEN
IF(DATA_OUT = expected_dout) THEN
data_chk <= '0';
ELSE
data_chk <= '1';
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE data_fifo_chk;
END ARCHITECTURE;
|
--
-- hwt_semaphore_post.vhd: measure time for semaphore_post() operation
--
-- This HW thread measures the time it takes to execute a semaphore_post()
-- operation from hardware.
-- To avoid side effects caused by activity of the delegate after returnung
-- from a sem_post() call, this thread waits a defined number of clock
-- cycles between consecutive calls to reconos_sem_post(). This number can
-- be configured using the init_data value. A typical value is 100000, which
-- is equivalent to a millisecond.
--
-- This HW thread uses the dcr_timebase core to do consistent and synchronized
-- measurements of elapsed bus clock cycles.
--
-- Author Enno Luebbers <[email protected]>
-- Date 09.02.2008
--
-- For detailed documentation of the functions, see the associated header
-- file or the documentation (if such a header exists).
--
-- This file is part of the ReconOS project <http://www.reconos.de>.
-- University of Paderborn, Computer Engineering Group
--
-- (C) Copyright University of Paderborn 2007. Permission to copy,
-- use, modify, sell and distribute this software is granted provided
-- this copyright notice appears in all copies. This software is
-- provided "as is" without express or implied warranty, and with no
-- claim as to its suitability for any purpose.
--
---------------------------------------------------------------------------
-- Major Changes:
--
-- 09.02.2008 Enno Luebbers File created
-- 11.02.2008 Enno Luebbers Modified to use timebase core
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library reconos_v2_00_a;
use reconos_v2_00_a.reconos_pkg.all;
entity hwt_semaphore_post is
generic (
C_BURST_AWIDTH : integer := 11;
C_BURST_DWIDTH : integer := 32
);
port (
clk : in std_logic;
reset : in std_logic;
i_osif : in osif_os2task_t;
o_osif : out osif_task2os_t;
-- burst ram interface
o_RAMAddr : out std_logic_vector( 0 to C_BURST_AWIDTH-1 );
o_RAMData : out std_logic_vector( 0 to C_BURST_DWIDTH-1 );
i_RAMData : in std_logic_vector( 0 to C_BURST_DWIDTH-1 );
o_RAMWE : out std_logic;
o_RAMClk : out std_logic;
-- time base
i_timeBase : in std_logic_vector( 0 to C_OSIF_DATA_WIDTH-1 )
);
end entity;
architecture Behavioral of hwt_semaphore_post is
attribute keep_hierarchy : string;
attribute keep_hierarchy of Behavioral: architecture is "true";
constant C_SEMAPHORE : std_logic_vector(31 downto 0) := X"00000000";
constant C_MBOX_RESULT : std_logic_vector(31 downto 0) := X"00000001";
type t_state is ( STATE_INIT, -- get initial data (delay in clocks)
STATE_WAIT_BEFORE, -- wait before measuring
STATE_POST_SEM, -- post semaphore
STATE_MEASURE, -- measure elapsed time
STATE_WAIT_AFTER, -- wait after measuring
STATE_PUT_RESULT_START, -- post elapsed time to software mbox
STATE_PUT_RESULT_STOP,
STATE_EXIT); -- exit
signal state : t_state;
signal counter : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
signal reset_counter : std_logic := '1';
begin
state_proc: process( clk, reset )
variable delay : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
variable result_start : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
variable result_stop : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
variable retval : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
variable done : boolean := false;
variable success : boolean := false;
begin
if reset = '1' then
reconos_reset( o_osif, i_osif );
state <= STATE_INIT;
reset_counter <= '1';
result_start := (others => '0');
result_stop := (others => '0');
retval := (others => '0');
elsif rising_edge( clk ) then
reconos_begin( o_osif, i_osif );
if reconos_ready( i_osif ) then
case state is
when STATE_INIT =>
reconos_get_init_data(done, o_osif, i_osif, delay);
if done then
reset_counter <= '1';
state <= STATE_WAIT_BEFORE;
end if;
when STATE_WAIT_BEFORE =>
reset_counter <= '0';
if counter >= delay then
reset_counter <= '1';
result_start := i_timeBase;
state <= STATE_POST_SEM;
end if;
when STATE_POST_SEM =>
reconos_sem_post(o_osif,i_osif,C_SEMAPHORE);
state <= STATE_MEASURE;
when STATE_MEASURE =>
result_stop := i_timeBase;
state <= STATE_WAIT_AFTER;
when STATE_WAIT_AFTER =>
reset_counter <= '0';
if counter >= delay then
reset_counter <= '1';
state <= STATE_PUT_RESULT_START;
end if;
when STATE_PUT_RESULT_START =>
reconos_mbox_put(done,
success,
o_osif,
i_osif,
C_MBOX_RESULT,
result_start);
if done then
if success then
state <= STATE_PUT_RESULT_STOP;
else
retval := X"0000_0001"; -- first mbox_put failed
state <= STATE_EXIT;
end if;
end if;
when STATE_PUT_RESULT_STOP =>
reconos_mbox_put(done,
success,
o_osif,
i_osif,
C_MBOX_RESULT,
result_stop);
if done then
if success then
retval := X"0000_0000"; -- all is well
state <= STATE_EXIT;
else
retval := X"0000_0002"; -- second mbox_put failed
state <= STATE_EXIT;
end if;
end if;
when STATE_EXIT =>
reconos_thread_exit(o_osif, i_osif, retval);
end case;
end if;
end if;
end process;
--
-- counter process to wait cycles
--
counter_proc : process(clk, reset)
begin
if reset = '1' then
counter <= (others => '0');
elsif rising_edge(clk) then
if reset_counter = '1' then
counter <= (others => '0');
else
counter <= counter + 1;
end if;
end if;
end process;
end architecture;
|
--------------------------------------------------------------------------------
-- Author: Parham Alvani ([email protected])
--
-- Create Date: 15-02-2016
-- Module Name: decoder_t.vhd
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity decoder_t is
end entity decoder_t;
architecture arch_decoder_t of decoder_t is
component decoder is
port (i : in std_logic_vector(1 downto 0);
o : out std_logic_vector(3 downto 0));
end component decoder;
signal i : std_logic_vector(1 downto 0);
signal o : std_logic_vector(3 downto 0);
for all:decoder use entity work.decoder(beh_arch_decoder);
begin
d : decoder port map (i, o);
i(0) <= '0', '1' after 100 ns, '0' after 200 ns, '1' after 300 ns;
i(1) <= '0', '0' after 100 ns, '1' after 200 ns, '1' after 300 ns;
end architecture arch_decoder_t;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer: Yuan Mei
--
-- Create Date: 12/13/2013 07:56:40 PM
-- Design Name:
-- Module Name: global_clock_reset - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- This module encapsulates the main clock generation and its proepr resetting.
-- It also provides a global reset signal output upon stable clock's pll lock.
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
USE ieee.numeric_std.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
LIBRARY UNISIM;
USE UNISIM.VComponents.ALL;
ENTITY global_clock_reset IS
PORT (
SYS_CLK_P : IN std_logic;
SYS_CLK_N : IN std_logic;
FORCE_RST : IN std_logic;
-- output
GLOBAL_RST : OUT std_logic;
SYS_CLK : OUT std_logic;
CLK_OUT1 : OUT std_logic;
CLK_OUT2 : OUT std_logic;
CLK_OUT3 : OUT std_logic;
CLK_OUT4 : OUT std_logic
);
END global_clock_reset;
ARCHITECTURE Behavioral OF global_clock_reset IS
COMPONENT clockwiz
PORT (
-- Clock in ports
clk_in1 : IN std_logic;
-- Clock out ports
clk_out1 : OUT std_logic;
clk_out2 : OUT std_logic;
clk_out3 : OUT std_logic;
clk_out4 : OUT std_logic;
-- Status and control signals
reset : IN std_logic;
locked : OUT std_logic
);
END COMPONENT;
COMPONENT GlobalResetter
PORT (
FORCE_RST : IN std_logic;
CLK : IN std_logic; -- system clock
DCM_LOCKED : IN std_logic;
CLK_RST : OUT std_logic;
GLOBAL_RST : OUT std_logic
);
END COMPONENT;
-- Signals
SIGNAL sys_clk_i : std_logic;
SIGNAL dcm_locked : std_logic;
SIGNAL dcm_reset : std_logic;
BEGIN
IBUFDS_inst : IBUFDS
GENERIC MAP (
DIFF_TERM => false, -- Differential Termination
IBUF_LOW_PWR => false, -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
IOSTANDARD => "DEFAULT"
)
PORT MAP (
O => sys_clk_i, -- Buffer output
I => SYS_CLK_P, -- Diff_p buffer input (connect directly to top-level port)
IB => SYS_CLK_N -- Diff_n buffer input (connect directly to top-level port)
);
BUFG_inst : BUFG
PORT MAP (
I => sys_clk_i,
O => sys_clk
);
--sys_clk <= sys_clk_i;
clockwiz_inst : clockwiz
PORT MAP (
-- Clock in ports
clk_in1 => sys_clk_i,
-- Clock out ports
clk_out1 => CLK_OUT1,
clk_out2 => CLK_OUT2,
clk_out3 => CLK_OUT3,
clk_out4 => CLK_OUT4,
-- Status and control signals
reset => dcm_reset,
locked => dcm_locked
);
globalresetter_inst : GlobalResetter
PORT MAP (
FORCE_RST => FORCE_RST,
CLK => sys_clk_i,
DCM_LOCKED => dcm_locked,
CLK_RST => dcm_reset,
GLOBAL_RST => GLOBAL_RST
);
END Behavioral;
|
-- -------------------------------------------------------------
--
-- File Name: hdlsrc/fft_16_bit/TWDLROM_3_7.vhd
-- Created: 2017-03-27 23:13:58
--
-- Generated by MATLAB 9.1 and HDL Coder 3.9
--
-- -------------------------------------------------------------
-- -------------------------------------------------------------
--
-- Module: TWDLROM_3_7
-- Source Path: fft_16_bit/FFT HDL Optimized/TWDLROM_3_7
-- Hierarchy Level: 2
--
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
USE work.fft_16_bit_pkg.ALL;
ENTITY TWDLROM_3_7 IS
PORT( clk : IN std_logic;
reset : IN std_logic;
enb : IN std_logic;
dout_2_vld : IN std_logic;
softReset : IN std_logic;
twdl_3_7_re : OUT std_logic_vector(16 DOWNTO 0); -- sfix17_En15
twdl_3_7_im : OUT std_logic_vector(16 DOWNTO 0); -- sfix17_En15
twdl_3_7_vld : OUT std_logic
);
END TWDLROM_3_7;
ARCHITECTURE rtl OF TWDLROM_3_7 IS
-- Constants
CONSTANT Twiddle_re_table_data : vector_of_signed17(0 TO 1) :=
(to_signed(16#08000#, 17), to_signed(16#07642#, 17)); -- sfix17 [2]
CONSTANT Twiddle_im_table_data : vector_of_signed17(0 TO 1) :=
(to_signed(16#00000#, 17), to_signed(-16#030FC#, 17)); -- sfix17 [2]
-- Signals
SIGNAL Radix22TwdlMapping_cnt : unsigned(1 DOWNTO 0); -- ufix2
SIGNAL Radix22TwdlMapping_phase : unsigned(1 DOWNTO 0); -- ufix2
SIGNAL Radix22TwdlMapping_octantReg1 : unsigned(2 DOWNTO 0); -- ufix3
SIGNAL Radix22TwdlMapping_twdlAddr_raw : unsigned(3 DOWNTO 0); -- ufix4
SIGNAL Radix22TwdlMapping_twdlAddrMap : std_logic; -- ufix1
SIGNAL Radix22TwdlMapping_twdl45Reg : std_logic;
SIGNAL Radix22TwdlMapping_dvldReg1 : std_logic;
SIGNAL Radix22TwdlMapping_dvldReg2 : std_logic;
SIGNAL Radix22TwdlMapping_cnt_next : unsigned(1 DOWNTO 0); -- ufix2
SIGNAL Radix22TwdlMapping_phase_next : unsigned(1 DOWNTO 0); -- ufix2
SIGNAL Radix22TwdlMapping_octantReg1_next : unsigned(2 DOWNTO 0); -- ufix3
SIGNAL Radix22TwdlMapping_twdlAddr_raw_next : unsigned(3 DOWNTO 0); -- ufix4
SIGNAL Radix22TwdlMapping_twdlAddrMap_next : std_logic; -- ufix1
SIGNAL Radix22TwdlMapping_twdl45Reg_next : std_logic;
SIGNAL Radix22TwdlMapping_dvldReg1_next : std_logic;
SIGNAL Radix22TwdlMapping_dvldReg2_next : std_logic;
SIGNAL twdlAddr : std_logic; -- ufix1
SIGNAL twdlAddrVld : std_logic;
SIGNAL twdlOctant : unsigned(2 DOWNTO 0); -- ufix3
SIGNAL twdl45 : std_logic;
SIGNAL Twiddle_re_cast : signed(31 DOWNTO 0); -- int32
SIGNAL twiddleS_re : signed(16 DOWNTO 0); -- sfix17_En15
SIGNAL twiddleReg_re : signed(16 DOWNTO 0); -- sfix17_En15
SIGNAL Twiddle_im_cast : signed(31 DOWNTO 0); -- int32
SIGNAL twiddleS_im : signed(16 DOWNTO 0); -- sfix17_En15
SIGNAL twiddleReg_im : signed(16 DOWNTO 0); -- sfix17_En15
SIGNAL twdlOctantReg : unsigned(2 DOWNTO 0); -- ufix3
SIGNAL twdl45Reg : std_logic;
SIGNAL twdl_3_7_re_tmp : signed(16 DOWNTO 0); -- sfix17_En15
SIGNAL twdl_3_7_im_tmp : signed(16 DOWNTO 0); -- sfix17_En15
BEGIN
-- Radix22TwdlMapping
Radix22TwdlMapping_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
Radix22TwdlMapping_octantReg1 <= to_unsigned(16#0#, 3);
Radix22TwdlMapping_twdlAddr_raw <= to_unsigned(16#0#, 4);
Radix22TwdlMapping_twdlAddrMap <= '0';
Radix22TwdlMapping_twdl45Reg <= '0';
Radix22TwdlMapping_dvldReg1 <= '0';
Radix22TwdlMapping_dvldReg2 <= '0';
Radix22TwdlMapping_cnt <= to_unsigned(16#2#, 2);
Radix22TwdlMapping_phase <= to_unsigned(16#1#, 2);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
Radix22TwdlMapping_cnt <= Radix22TwdlMapping_cnt_next;
Radix22TwdlMapping_phase <= Radix22TwdlMapping_phase_next;
Radix22TwdlMapping_octantReg1 <= Radix22TwdlMapping_octantReg1_next;
Radix22TwdlMapping_twdlAddr_raw <= Radix22TwdlMapping_twdlAddr_raw_next;
Radix22TwdlMapping_twdlAddrMap <= Radix22TwdlMapping_twdlAddrMap_next;
Radix22TwdlMapping_twdl45Reg <= Radix22TwdlMapping_twdl45Reg_next;
Radix22TwdlMapping_dvldReg1 <= Radix22TwdlMapping_dvldReg1_next;
Radix22TwdlMapping_dvldReg2 <= Radix22TwdlMapping_dvldReg2_next;
END IF;
END IF;
END PROCESS Radix22TwdlMapping_process;
Radix22TwdlMapping_output : PROCESS (Radix22TwdlMapping_cnt, Radix22TwdlMapping_phase,
Radix22TwdlMapping_octantReg1, Radix22TwdlMapping_twdlAddr_raw,
Radix22TwdlMapping_twdlAddrMap, Radix22TwdlMapping_twdl45Reg,
Radix22TwdlMapping_dvldReg1, Radix22TwdlMapping_dvldReg2, dout_2_vld)
VARIABLE octant : unsigned(2 DOWNTO 0);
VARIABLE cnt_cast : unsigned(3 DOWNTO 0);
VARIABLE sub_cast : signed(9 DOWNTO 0);
VARIABLE sub_temp : signed(9 DOWNTO 0);
VARIABLE sub_cast_0 : signed(5 DOWNTO 0);
VARIABLE sub_temp_0 : signed(5 DOWNTO 0);
VARIABLE sub_cast_1 : signed(5 DOWNTO 0);
VARIABLE sub_temp_1 : signed(5 DOWNTO 0);
VARIABLE sub_cast_2 : signed(9 DOWNTO 0);
VARIABLE sub_temp_2 : signed(9 DOWNTO 0);
VARIABLE sub_cast_3 : signed(9 DOWNTO 0);
VARIABLE sub_temp_3 : signed(9 DOWNTO 0);
BEGIN
Radix22TwdlMapping_twdlAddr_raw_next <= Radix22TwdlMapping_twdlAddr_raw;
Radix22TwdlMapping_twdlAddrMap_next <= Radix22TwdlMapping_twdlAddrMap;
Radix22TwdlMapping_twdl45Reg_next <= Radix22TwdlMapping_twdl45Reg;
Radix22TwdlMapping_dvldReg2_next <= Radix22TwdlMapping_dvldReg1;
Radix22TwdlMapping_dvldReg1_next <= dout_2_vld;
CASE Radix22TwdlMapping_twdlAddr_raw IS
WHEN "0010" =>
octant := to_unsigned(16#0#, 3);
Radix22TwdlMapping_twdl45Reg_next <= '1';
WHEN "0100" =>
octant := to_unsigned(16#1#, 3);
Radix22TwdlMapping_twdl45Reg_next <= '0';
WHEN "0110" =>
octant := to_unsigned(16#2#, 3);
Radix22TwdlMapping_twdl45Reg_next <= '1';
WHEN "1000" =>
octant := to_unsigned(16#3#, 3);
Radix22TwdlMapping_twdl45Reg_next <= '0';
WHEN "1010" =>
octant := to_unsigned(16#4#, 3);
Radix22TwdlMapping_twdl45Reg_next <= '1';
WHEN OTHERS =>
octant := Radix22TwdlMapping_twdlAddr_raw(3 DOWNTO 1);
Radix22TwdlMapping_twdl45Reg_next <= '0';
END CASE;
Radix22TwdlMapping_octantReg1_next <= octant;
CASE octant IS
WHEN "000" =>
Radix22TwdlMapping_twdlAddrMap_next <= Radix22TwdlMapping_twdlAddr_raw(0);
WHEN "001" =>
sub_cast_0 := signed(resize(Radix22TwdlMapping_twdlAddr_raw, 6));
sub_temp_0 := to_signed(16#04#, 6) - sub_cast_0;
Radix22TwdlMapping_twdlAddrMap_next <= sub_temp_0(0);
WHEN "010" =>
sub_cast_1 := signed(resize(Radix22TwdlMapping_twdlAddr_raw, 6));
sub_temp_1 := sub_cast_1 - to_signed(16#04#, 6);
Radix22TwdlMapping_twdlAddrMap_next <= sub_temp_1(0);
WHEN "011" =>
sub_cast_2 := signed(resize(Radix22TwdlMapping_twdlAddr_raw & '0', 10));
sub_temp_2 := to_signed(16#010#, 10) - sub_cast_2;
Radix22TwdlMapping_twdlAddrMap_next <= sub_temp_2(1);
WHEN "100" =>
sub_cast_3 := signed(resize(Radix22TwdlMapping_twdlAddr_raw & '0', 10));
sub_temp_3 := sub_cast_3 - to_signed(16#010#, 10);
Radix22TwdlMapping_twdlAddrMap_next <= sub_temp_3(1);
WHEN OTHERS =>
sub_cast := signed(resize(Radix22TwdlMapping_twdlAddr_raw & '0', 10));
sub_temp := to_signed(16#018#, 10) - sub_cast;
Radix22TwdlMapping_twdlAddrMap_next <= sub_temp(1);
END CASE;
IF Radix22TwdlMapping_phase = to_unsigned(16#0#, 2) THEN
Radix22TwdlMapping_twdlAddr_raw_next <= to_unsigned(16#0#, 4);
ELSIF Radix22TwdlMapping_phase = to_unsigned(16#1#, 2) THEN
Radix22TwdlMapping_twdlAddr_raw_next <= resize(Radix22TwdlMapping_cnt, 4) sll 1;
ELSIF Radix22TwdlMapping_phase = to_unsigned(16#2#, 2) THEN
Radix22TwdlMapping_twdlAddr_raw_next <= resize(Radix22TwdlMapping_cnt, 4);
ELSE
cnt_cast := resize(Radix22TwdlMapping_cnt, 4);
Radix22TwdlMapping_twdlAddr_raw_next <= (cnt_cast sll 1) + cnt_cast;
END IF;
Radix22TwdlMapping_phase_next <= to_unsigned(16#1#, 2);
Radix22TwdlMapping_cnt_next <= Radix22TwdlMapping_cnt + to_unsigned(16#000000010#, 2);
twdlAddr <= Radix22TwdlMapping_twdlAddrMap;
twdlAddrVld <= Radix22TwdlMapping_dvldReg2;
twdlOctant <= Radix22TwdlMapping_octantReg1;
twdl45 <= Radix22TwdlMapping_twdl45Reg;
END PROCESS Radix22TwdlMapping_output;
-- Twiddle ROM1
Twiddle_re_cast <= '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & twdlAddr;
twiddleS_re <= Twiddle_re_table_data(to_integer(Twiddle_re_cast));
TWIDDLEROM_RE_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
twiddleReg_re <= to_signed(16#00000#, 17);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
twiddleReg_re <= twiddleS_re;
END IF;
END IF;
END PROCESS TWIDDLEROM_RE_process;
-- Twiddle ROM2
Twiddle_im_cast <= '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & twdlAddr;
twiddleS_im <= Twiddle_im_table_data(to_integer(Twiddle_im_cast));
TWIDDLEROM_IM_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
twiddleReg_im <= to_signed(16#00000#, 17);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
twiddleReg_im <= twiddleS_im;
END IF;
END IF;
END PROCESS TWIDDLEROM_IM_process;
intdelay_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
twdlOctantReg <= to_unsigned(16#0#, 3);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
twdlOctantReg <= twdlOctant;
END IF;
END IF;
END PROCESS intdelay_process;
intdelay_1_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
twdl45Reg <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
twdl45Reg <= twdl45;
END IF;
END IF;
END PROCESS intdelay_1_process;
-- Radix22TwdlOctCorr
Radix22TwdlOctCorr_output : PROCESS (twiddleReg_re, twiddleReg_im, twdlOctantReg, twdl45Reg)
VARIABLE twdlIn_re : signed(16 DOWNTO 0);
VARIABLE twdlIn_im : signed(16 DOWNTO 0);
VARIABLE cast : signed(17 DOWNTO 0);
VARIABLE cast_0 : signed(17 DOWNTO 0);
VARIABLE cast_1 : signed(17 DOWNTO 0);
VARIABLE cast_2 : signed(17 DOWNTO 0);
VARIABLE cast_3 : signed(17 DOWNTO 0);
VARIABLE cast_4 : signed(17 DOWNTO 0);
VARIABLE cast_5 : signed(17 DOWNTO 0);
VARIABLE cast_6 : signed(17 DOWNTO 0);
VARIABLE cast_7 : signed(17 DOWNTO 0);
VARIABLE cast_8 : signed(17 DOWNTO 0);
VARIABLE cast_9 : signed(17 DOWNTO 0);
VARIABLE cast_10 : signed(17 DOWNTO 0);
BEGIN
twdlIn_re := twiddleReg_re;
twdlIn_im := twiddleReg_im;
IF twdl45Reg = '1' THEN
CASE twdlOctantReg IS
WHEN "000" =>
twdlIn_re := to_signed(16#05A82#, 17);
twdlIn_im := to_signed(-16#05A82#, 17);
WHEN "010" =>
twdlIn_re := to_signed(-16#05A82#, 17);
twdlIn_im := to_signed(-16#05A82#, 17);
WHEN "100" =>
twdlIn_re := to_signed(-16#05A82#, 17);
twdlIn_im := to_signed(16#05A82#, 17);
WHEN OTHERS =>
twdlIn_re := to_signed(16#05A82#, 17);
twdlIn_im := to_signed(-16#05A82#, 17);
END CASE;
ELSE
CASE twdlOctantReg IS
WHEN "000" =>
NULL;
WHEN "001" =>
cast := resize(twiddleReg_im, 18);
cast_0 := - (cast);
twdlIn_re := cast_0(16 DOWNTO 0);
cast_5 := resize(twiddleReg_re, 18);
cast_6 := - (cast_5);
twdlIn_im := cast_6(16 DOWNTO 0);
WHEN "010" =>
twdlIn_re := twiddleReg_im;
cast_7 := resize(twiddleReg_re, 18);
cast_8 := - (cast_7);
twdlIn_im := cast_8(16 DOWNTO 0);
WHEN "011" =>
cast_1 := resize(twiddleReg_re, 18);
cast_2 := - (cast_1);
twdlIn_re := cast_2(16 DOWNTO 0);
twdlIn_im := twiddleReg_im;
WHEN "100" =>
cast_3 := resize(twiddleReg_re, 18);
cast_4 := - (cast_3);
twdlIn_re := cast_4(16 DOWNTO 0);
cast_9 := resize(twiddleReg_im, 18);
cast_10 := - (cast_9);
twdlIn_im := cast_10(16 DOWNTO 0);
WHEN OTHERS =>
twdlIn_re := twiddleReg_im;
twdlIn_im := twiddleReg_re;
END CASE;
END IF;
twdl_3_7_re_tmp <= twdlIn_re;
twdl_3_7_im_tmp <= twdlIn_im;
END PROCESS Radix22TwdlOctCorr_output;
twdl_3_7_re <= std_logic_vector(twdl_3_7_re_tmp);
twdl_3_7_im <= std_logic_vector(twdl_3_7_im_tmp);
intdelay_2_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
twdl_3_7_vld <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
twdl_3_7_vld <= twdlAddrVld;
END IF;
END IF;
END PROCESS intdelay_2_process;
END rtl;
|
-- Generation properties:
-- Format : hierarchical
-- Generic mappings : exclude
-- Leaf-level entities : direct binding
-- Regular libraries : use library name
-- View name : include
--
LIBRARY lab7_lib;
CONFIGURATION fetch_stage_struct_config OF fetch_stage IS
FOR struct
FOR ALL : Fetch_FSM
USE ENTITY lab7_lib.Fetch_FSM(FSM);
END FOR;
END FOR;
END fetch_stage_struct_config;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--------------------------------------------------------------------------------
--
-- Filename: side_prod.vhd
--
-- Description:
-- This is the top-level BMG wrapper (over BMG core).
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
-- Configured Core Parameter Values:
-- (Refer to the SIM Parameters table in the datasheet for more information on
-- the these parameters.)
-- C_FAMILY : artix7
-- C_XDEVICEFAMILY : artix7
-- C_INTERFACE_TYPE : 0
-- C_ENABLE_32BIT_ADDRESS : 0
-- C_AXI_TYPE : 1
-- C_AXI_SLAVE_TYPE : 0
-- C_AXI_ID_WIDTH : 4
-- C_MEM_TYPE : 3
-- C_BYTE_SIZE : 9
-- C_ALGORITHM : 1
-- C_PRIM_TYPE : 1
-- C_LOAD_INIT_FILE : 1
-- C_INIT_FILE_NAME : side.mif
-- C_USE_DEFAULT_DATA : 0
-- C_DEFAULT_DATA : 0
-- C_RST_TYPE : SYNC
-- C_HAS_RSTA : 0
-- C_RST_PRIORITY_A : CE
-- C_RSTRAM_A : 0
-- C_INITA_VAL : 0
-- C_HAS_ENA : 0
-- C_HAS_REGCEA : 0
-- C_USE_BYTE_WEA : 0
-- C_WEA_WIDTH : 1
-- C_WRITE_MODE_A : WRITE_FIRST
-- C_WRITE_WIDTH_A : 12
-- C_READ_WIDTH_A : 12
-- C_WRITE_DEPTH_A : 76800
-- C_READ_DEPTH_A : 76800
-- C_ADDRA_WIDTH : 17
-- C_HAS_RSTB : 0
-- C_RST_PRIORITY_B : CE
-- C_RSTRAM_B : 0
-- C_INITB_VAL : 0
-- C_HAS_ENB : 0
-- C_HAS_REGCEB : 0
-- C_USE_BYTE_WEB : 0
-- C_WEB_WIDTH : 1
-- C_WRITE_MODE_B : WRITE_FIRST
-- C_WRITE_WIDTH_B : 12
-- C_READ_WIDTH_B : 12
-- C_WRITE_DEPTH_B : 76800
-- C_READ_DEPTH_B : 76800
-- C_ADDRB_WIDTH : 17
-- C_HAS_MEM_OUTPUT_REGS_A : 0
-- C_HAS_MEM_OUTPUT_REGS_B : 0
-- C_HAS_MUX_OUTPUT_REGS_A : 0
-- C_HAS_MUX_OUTPUT_REGS_B : 0
-- C_HAS_SOFTECC_INPUT_REGS_A : 0
-- C_HAS_SOFTECC_OUTPUT_REGS_B : 0
-- C_MUX_PIPELINE_STAGES : 0
-- C_USE_ECC : 0
-- C_USE_SOFTECC : 0
-- C_HAS_INJECTERR : 0
-- C_SIM_COLLISION_CHECK : ALL
-- C_COMMON_CLK : 0
-- C_DISABLE_WARN_BHV_COLL : 0
-- C_DISABLE_WARN_BHV_RANGE : 0
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY side_prod IS
PORT (
--Port A
CLKA : IN STD_LOGIC;
RSTA : IN STD_LOGIC; --opt port
ENA : IN STD_LOGIC; --optional port
REGCEA : IN STD_LOGIC; --optional port
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(16 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
--Port B
CLKB : IN STD_LOGIC;
RSTB : IN STD_LOGIC; --opt port
ENB : IN STD_LOGIC; --optional port
REGCEB : IN STD_LOGIC; --optional port
WEB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRB : IN STD_LOGIC_VECTOR(16 DOWNTO 0);
DINB : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
--ECC
INJECTSBITERR : IN STD_LOGIC; --optional port
INJECTDBITERR : IN STD_LOGIC; --optional port
SBITERR : OUT STD_LOGIC; --optional port
DBITERR : OUT STD_LOGIC; --optional port
RDADDRECC : OUT STD_LOGIC_VECTOR(16 DOWNTO 0); --optional port
-- AXI BMG Input and Output Port Declarations
-- AXI Global Signals
S_ACLK : IN STD_LOGIC;
S_AXI_AWID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_AWLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_AWVALID : IN STD_LOGIC;
S_AXI_AWREADY : OUT STD_LOGIC;
S_AXI_WDATA : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
S_AXI_WSTRB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
S_AXI_WLAST : IN STD_LOGIC;
S_AXI_WVALID : IN STD_LOGIC;
S_AXI_WREADY : OUT STD_LOGIC;
S_AXI_BID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_BVALID : OUT STD_LOGIC;
S_AXI_BREADY : IN STD_LOGIC;
-- AXI Full/Lite Slave Read (Write side)
S_AXI_ARID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_ARLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_ARVALID : IN STD_LOGIC;
S_AXI_ARREADY : OUT STD_LOGIC;
S_AXI_RID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_RDATA : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
S_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_RLAST : OUT STD_LOGIC;
S_AXI_RVALID : OUT STD_LOGIC;
S_AXI_RREADY : IN STD_LOGIC;
-- AXI Full/Lite Sideband Signals
S_AXI_INJECTSBITERR : IN STD_LOGIC;
S_AXI_INJECTDBITERR : IN STD_LOGIC;
S_AXI_SBITERR : OUT STD_LOGIC;
S_AXI_DBITERR : OUT STD_LOGIC;
S_AXI_RDADDRECC : OUT STD_LOGIC_VECTOR(16 DOWNTO 0);
S_ARESETN : IN STD_LOGIC
);
END side_prod;
ARCHITECTURE xilinx OF side_prod IS
COMPONENT side_exdes IS
PORT (
--Port A
ADDRA : IN STD_LOGIC_VECTOR(16 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
BEGIN
bmg0 : side_exdes
PORT MAP (
--Port A
ADDRA => ADDRA,
DOUTA => DOUTA,
CLKA => CLKA
);
END xilinx;
|
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY TB_Procesador IS
END TB_Procesador;
ARCHITECTURE behavior OF TB_Procesador IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT unionModulos
PORT(
clk : IN std_logic;
rst : IN std_logic;
salida : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal rst : std_logic := '0';
--Outputs
signal salida : std_logic_vector(31 downto 0);
-- Clock period definitions
constant clk_period : time := 20 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: unionModulos PORT MAP (
clk => clk,
rst => rst,
salida => salida
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
rst <= '1';
wait for 15 ns;
rst <= '0';
wait;
end process;
END;
|
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_AB_e
--
-- Generated
-- by: wig
-- on: Sat Mar 3 17:08:41 2007
-- cmd: /cygdrive/c/Documents and Settings/wig/My Documents/work/MIX/mix_0.pl -nodelta ../case.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_ab_e-rtl-a_1.vhd,v 1.1 2007/03/05 08:59:00 wig Exp $
-- $Date: 2007/03/05 08:59:00 $
-- $Log: inst_ab_e-rtl-a_1.vhd,v $
-- Revision 1.1 2007/03/05 08:59:00 wig
-- Upgraded testcases
-- case/force still not fully operational (internal names keep case).
--
-- Revision 1.1 2007/03/03 17:24:06 wig
-- Updated testcase for case matches. Added filename serialization.
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.101 2007/03/01 16:28:38 wig Exp
--
-- Generator: mix_0.pl Revision: 1.47 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of inst_AB_e
--
architecture rtl of inst_AB_e is
--
-- Generated Constant Declarations
--
--
-- Generated Components
--
--
-- Generated Signal List
--
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
--
-- Generated Signal Assignments
--
--
-- Generated Instances and Port Mappings
--
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
-- $Id: rbd_tester.vhd 427 2011-11-19 21:04:11Z mueller $
--
-- Copyright 2010-2011 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: rbd_tester - syn
-- Description: rbus dev: rbus tester
--
-- Dependencies: memlib/fifo_1c_dram_raw
--
-- Test bench: rlink/tb/tb_rlink (used as test target)
--
-- Target Devices: generic
-- Tool versions: xst 12.1, 13.1; ghdl 0.29
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2010-12-12 344 12.1 M53d xc3s1000-4 78 204 32 133 s 8.0
-- 2010-12-04 343 12.1 M53d xc3s1000-4 75 214 32 136 s 9.3
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-19 427 1.0.4 now numeric_std clean
-- 2010-12-31 352 1.0.3 simplify irb_ack logic
-- 2010-12-29 351 1.0.2 default addr 111101xx->111100xx
-- 2010-12-12 344 1.0.1 send 0101.. on busy or err; fix init and busy logic
-- 2010-12-04 343 1.0 Initial version
------------------------------------------------------------------------------
--
-- rbus registers:
--
-- Address Bits Name r/w/f Function
-- bbbbbb00 cntl r/w/- Control register
-- 15 nofifo r/w/- a 1 disables fifo, to test delayed aborts
-- 14:12 stat r/w/- echo'ed on RB_STAT
-- 11:00 nbusy r/w/- busy cycles (for data and fifo access)
-- bbbbbb01 15:00 data r/w/- Data register (just w/r reg, no function)
-- bbbbbb10 15:00 fifo r/w/- Fifo interface register
-- bbbbbb11 attn r/w/- Attn/Length register
-- 15:00 w: ping RB_LAM lines
-- 9:00 r: return cycle length of last access
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.memlib.all;
use work.rblib.all;
entity rbd_tester is -- rbus dev: rbus tester
-- complete rrirp_aif interface
generic (
RB_ADDR : slv8 := slv(to_unsigned(2#11110000#,8)));
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
RB_MREQ : in rb_mreq_type; -- rbus: request
RB_SRES : out rb_sres_type; -- rbus: response
RB_LAM : out slv16; -- rbus: look at me
RB_STAT : out slv3 -- rbus: status flags
);
end entity rbd_tester;
architecture syn of rbd_tester is
constant awidth : positive := 4; -- fifo address width
constant rbaddr_cntl : slv2 := "00"; -- cntl address offset
constant rbaddr_data : slv2 := "01"; -- data address offset
constant rbaddr_fifo : slv2 := "10"; -- fifo address offset
constant rbaddr_attn : slv2 := "11"; -- attn address offset
constant cntl_rbf_nofifo : integer := 15;
subtype cntl_rbf_stat is integer range 14 downto 12;
subtype cntl_rbf_nbusy is integer range 9 downto 0;
constant init_rbf_cntl : integer := 0;
constant init_rbf_data : integer := 1;
constant init_rbf_fifo : integer := 2;
type regs_type is record -- state registers
rbsel : slbit; -- rbus select
nofifo : slbit; -- disable fifo flag
stat : slv3; -- stat setting
nbusy : slv10; -- nbusy setting
data : slv16; -- data register
act_1 : slbit; -- rbsel and (re or we) in last cycle
ncyc : slv10; -- cycle length of last access
cntbusy : slv10; -- busy timer
cntcyc : slv10; -- cycle length counter
end record regs_type;
constant regs_init : regs_type := (
'0', -- rbsel
'0', -- nofifo
(others=>'0'), -- stat
(others=>'0'), -- nbusy
(others=>'0'), -- data
'0', -- act_1
(others=>'0'), -- ncyc
(others=>'0'), -- cntbusy
(others=>'0') -- cntcyc
);
constant cntcyc_max : slv(regs_init.cntcyc'range) := (others=>'1');
signal R_REGS : regs_type := regs_init;
signal N_REGS : regs_type := regs_init;
signal FIFO_RESET : slbit := '0';
signal FIFO_RE : slbit := '0';
signal FIFO_WE : slbit := '0';
signal FIFO_EMPTY : slbit := '0';
signal FIFO_FULL : slbit := '0';
signal FIFO_SIZE : slv(awidth-1 downto 0) := (others=>'0');
signal FIFO_DO : slv16 := (others=>'0');
begin
FIFO : fifo_1c_dram_raw
generic map (
AWIDTH => awidth,
DWIDTH => 16)
port map (
CLK => CLK,
RESET => FIFO_RESET,
RE => FIFO_RE,
WE => FIFO_WE,
DI => RB_MREQ.din,
DO => FIFO_DO,
SIZE => FIFO_SIZE,
EMPTY => FIFO_EMPTY,
FULL => FIFO_FULL
);
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
R_REGS <= regs_init;
else
R_REGS <= N_REGS;
end if;
end if;
end process proc_regs;
proc_next : process (R_REGS, RB_MREQ, FIFO_EMPTY, FIFO_FULL, FIFO_DO)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
variable irb_ack : slbit := '0';
variable irb_busy : slbit := '0';
variable irb_err : slbit := '0';
variable irb_dout : slv16 := (others=>'0');
variable irbena : slbit := '0';
variable irblam : slv16 := (others=>'0');
variable ififo_re : slbit := '0';
variable ififo_we : slbit := '0';
variable ififo_reset : slbit := '0';
variable isbusy : slbit := '0';
begin
r := R_REGS;
n := R_REGS;
irb_ack := '0';
irb_busy := '0';
irb_err := '0';
irb_dout := (others=>'0');
irblam := (others=>'0');
irbena := RB_MREQ.re or RB_MREQ.we;
ififo_re := '0';
ififo_we := '0';
ififo_reset := '0';
isbusy := '0';
if unsigned(r.cntbusy) /= 0 then
isbusy := '1';
end if;
-- rbus address decoder
n.rbsel := '0';
if RB_MREQ.aval='1' and RB_MREQ.addr(7 downto 2)=RB_ADDR(7 downto 2) then
n.rbsel := '1';
if irbena = '0' then -- addr valid and selected, but no req
n.cntbusy := r.nbusy; -- preset busy timer
n.cntcyc := (others=>'0'); -- clear cycle length counter
end if;
end if;
-- rbus transactions
if r.rbsel = '1' then
if irbena = '1' then -- if request active
if unsigned(r.cntbusy) /= 0 then -- if busy timer > 0
n.cntbusy := slv(unsigned(r.cntbusy) - 1); -- decrement busy timer
end if;
if r.cntcyc /= cntcyc_max then -- if cycle counter < max
n.cntcyc := slv(unsigned(r.cntcyc) + 1); -- increment cycle counter
end if;
end if;
irb_ack := irbena; -- ack all (some rejects later)
case RB_MREQ.addr(1 downto 0) is
when rbaddr_cntl =>
if RB_MREQ.we='1' then
n.nofifo := RB_MREQ.din(cntl_rbf_nofifo);
n.stat := RB_MREQ.din(cntl_rbf_stat);
n.nbusy := RB_MREQ.din(cntl_rbf_nbusy);
if r.nofifo='1' and RB_MREQ.din(cntl_rbf_nofifo)='0' then
ififo_reset := '1';
end if;
end if;
when rbaddr_data =>
irb_busy := irbena and isbusy;
if RB_MREQ.we='1' and isbusy='0' then
n.data := RB_MREQ.din;
end if;
when rbaddr_fifo =>
if r.nofifo = '0' then -- if fifo enabled
irb_busy := irbena and isbusy;
if RB_MREQ.re='1' and isbusy='0' then
if FIFO_EMPTY = '1' then
irb_err := '1';
else
ififo_re := '1';
end if;
end if;
if RB_MREQ.we='1' and isbusy='0' then
if FIFO_FULL = '1' then
irb_err := '1';
else
ififo_we := '1';
end if;
end if;
else -- else: if fifo disabled
irb_ack := '0'; -- nak it
if isbusy = '1' then -- or do a delayed nak
irb_ack := irbena;
irb_busy := irbena;
end if;
end if;
when rbaddr_attn =>
if RB_MREQ.we = '1' then
irblam := RB_MREQ.din;
end if;
when others => null;
end case;
end if;
-- rbus output driver
-- send a '0101...' pattern when selected and busy or err
-- send data only when busy=0 and err=0
-- this extra logic allows to debug rlink state machine
if r.rbsel = '1' then
if RB_MREQ.re='1' and irb_busy='0' and irb_err='0' then
case RB_MREQ.addr(1 downto 0) is
when rbaddr_cntl =>
irb_dout(cntl_rbf_stat) := r.stat;
irb_dout(cntl_rbf_nofifo) := r.nofifo;
irb_dout(cntl_rbf_nbusy) := r.nbusy;
when rbaddr_data =>
irb_dout := r.data;
when rbaddr_fifo =>
if r.nofifo='0' and FIFO_EMPTY = '0' then
irb_dout := FIFO_DO;
end if;
when rbaddr_attn =>
irb_dout(r.cntcyc'range) := r.ncyc;
when others => null;
end case;
else
irb_dout := "0101010101010101";
end if;
end if;
-- init transactions
if RB_MREQ.init='1' and RB_MREQ.we='1' and RB_MREQ.addr=RB_ADDR then
if RB_MREQ.din(init_rbf_cntl) = '1' then
n.nofifo := '0';
n.stat := (others=>'0');
n.nbusy := (others=>'0');
end if;
if RB_MREQ.din(init_rbf_data) = '1' then
n.data := (others=>'0');
end if;
if RB_MREQ.din(init_rbf_fifo) = '1' then
ififo_reset := '1';
end if;
end if;
-- other transactions
if irbena='0' and r.act_1='1' then
n.ncyc := r.cntcyc;
end if;
n.act_1 := irbena;
N_REGS <= n;
FIFO_RE <= ififo_re;
FIFO_WE <= ififo_we;
FIFO_RESET <= ififo_reset;
RB_SRES.dout <= irb_dout;
RB_SRES.ack <= irb_ack;
RB_SRES.err <= irb_err;
RB_SRES.busy <= irb_busy;
RB_LAM <= irblam;
RB_STAT <= r.stat;
end process proc_next;
end syn;
|
-- $Id: rbd_tester.vhd 427 2011-11-19 21:04:11Z mueller $
--
-- Copyright 2010-2011 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: rbd_tester - syn
-- Description: rbus dev: rbus tester
--
-- Dependencies: memlib/fifo_1c_dram_raw
--
-- Test bench: rlink/tb/tb_rlink (used as test target)
--
-- Target Devices: generic
-- Tool versions: xst 12.1, 13.1; ghdl 0.29
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2010-12-12 344 12.1 M53d xc3s1000-4 78 204 32 133 s 8.0
-- 2010-12-04 343 12.1 M53d xc3s1000-4 75 214 32 136 s 9.3
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-19 427 1.0.4 now numeric_std clean
-- 2010-12-31 352 1.0.3 simplify irb_ack logic
-- 2010-12-29 351 1.0.2 default addr 111101xx->111100xx
-- 2010-12-12 344 1.0.1 send 0101.. on busy or err; fix init and busy logic
-- 2010-12-04 343 1.0 Initial version
------------------------------------------------------------------------------
--
-- rbus registers:
--
-- Address Bits Name r/w/f Function
-- bbbbbb00 cntl r/w/- Control register
-- 15 nofifo r/w/- a 1 disables fifo, to test delayed aborts
-- 14:12 stat r/w/- echo'ed on RB_STAT
-- 11:00 nbusy r/w/- busy cycles (for data and fifo access)
-- bbbbbb01 15:00 data r/w/- Data register (just w/r reg, no function)
-- bbbbbb10 15:00 fifo r/w/- Fifo interface register
-- bbbbbb11 attn r/w/- Attn/Length register
-- 15:00 w: ping RB_LAM lines
-- 9:00 r: return cycle length of last access
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.memlib.all;
use work.rblib.all;
entity rbd_tester is -- rbus dev: rbus tester
-- complete rrirp_aif interface
generic (
RB_ADDR : slv8 := slv(to_unsigned(2#11110000#,8)));
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
RB_MREQ : in rb_mreq_type; -- rbus: request
RB_SRES : out rb_sres_type; -- rbus: response
RB_LAM : out slv16; -- rbus: look at me
RB_STAT : out slv3 -- rbus: status flags
);
end entity rbd_tester;
architecture syn of rbd_tester is
constant awidth : positive := 4; -- fifo address width
constant rbaddr_cntl : slv2 := "00"; -- cntl address offset
constant rbaddr_data : slv2 := "01"; -- data address offset
constant rbaddr_fifo : slv2 := "10"; -- fifo address offset
constant rbaddr_attn : slv2 := "11"; -- attn address offset
constant cntl_rbf_nofifo : integer := 15;
subtype cntl_rbf_stat is integer range 14 downto 12;
subtype cntl_rbf_nbusy is integer range 9 downto 0;
constant init_rbf_cntl : integer := 0;
constant init_rbf_data : integer := 1;
constant init_rbf_fifo : integer := 2;
type regs_type is record -- state registers
rbsel : slbit; -- rbus select
nofifo : slbit; -- disable fifo flag
stat : slv3; -- stat setting
nbusy : slv10; -- nbusy setting
data : slv16; -- data register
act_1 : slbit; -- rbsel and (re or we) in last cycle
ncyc : slv10; -- cycle length of last access
cntbusy : slv10; -- busy timer
cntcyc : slv10; -- cycle length counter
end record regs_type;
constant regs_init : regs_type := (
'0', -- rbsel
'0', -- nofifo
(others=>'0'), -- stat
(others=>'0'), -- nbusy
(others=>'0'), -- data
'0', -- act_1
(others=>'0'), -- ncyc
(others=>'0'), -- cntbusy
(others=>'0') -- cntcyc
);
constant cntcyc_max : slv(regs_init.cntcyc'range) := (others=>'1');
signal R_REGS : regs_type := regs_init;
signal N_REGS : regs_type := regs_init;
signal FIFO_RESET : slbit := '0';
signal FIFO_RE : slbit := '0';
signal FIFO_WE : slbit := '0';
signal FIFO_EMPTY : slbit := '0';
signal FIFO_FULL : slbit := '0';
signal FIFO_SIZE : slv(awidth-1 downto 0) := (others=>'0');
signal FIFO_DO : slv16 := (others=>'0');
begin
FIFO : fifo_1c_dram_raw
generic map (
AWIDTH => awidth,
DWIDTH => 16)
port map (
CLK => CLK,
RESET => FIFO_RESET,
RE => FIFO_RE,
WE => FIFO_WE,
DI => RB_MREQ.din,
DO => FIFO_DO,
SIZE => FIFO_SIZE,
EMPTY => FIFO_EMPTY,
FULL => FIFO_FULL
);
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
R_REGS <= regs_init;
else
R_REGS <= N_REGS;
end if;
end if;
end process proc_regs;
proc_next : process (R_REGS, RB_MREQ, FIFO_EMPTY, FIFO_FULL, FIFO_DO)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
variable irb_ack : slbit := '0';
variable irb_busy : slbit := '0';
variable irb_err : slbit := '0';
variable irb_dout : slv16 := (others=>'0');
variable irbena : slbit := '0';
variable irblam : slv16 := (others=>'0');
variable ififo_re : slbit := '0';
variable ififo_we : slbit := '0';
variable ififo_reset : slbit := '0';
variable isbusy : slbit := '0';
begin
r := R_REGS;
n := R_REGS;
irb_ack := '0';
irb_busy := '0';
irb_err := '0';
irb_dout := (others=>'0');
irblam := (others=>'0');
irbena := RB_MREQ.re or RB_MREQ.we;
ififo_re := '0';
ififo_we := '0';
ififo_reset := '0';
isbusy := '0';
if unsigned(r.cntbusy) /= 0 then
isbusy := '1';
end if;
-- rbus address decoder
n.rbsel := '0';
if RB_MREQ.aval='1' and RB_MREQ.addr(7 downto 2)=RB_ADDR(7 downto 2) then
n.rbsel := '1';
if irbena = '0' then -- addr valid and selected, but no req
n.cntbusy := r.nbusy; -- preset busy timer
n.cntcyc := (others=>'0'); -- clear cycle length counter
end if;
end if;
-- rbus transactions
if r.rbsel = '1' then
if irbena = '1' then -- if request active
if unsigned(r.cntbusy) /= 0 then -- if busy timer > 0
n.cntbusy := slv(unsigned(r.cntbusy) - 1); -- decrement busy timer
end if;
if r.cntcyc /= cntcyc_max then -- if cycle counter < max
n.cntcyc := slv(unsigned(r.cntcyc) + 1); -- increment cycle counter
end if;
end if;
irb_ack := irbena; -- ack all (some rejects later)
case RB_MREQ.addr(1 downto 0) is
when rbaddr_cntl =>
if RB_MREQ.we='1' then
n.nofifo := RB_MREQ.din(cntl_rbf_nofifo);
n.stat := RB_MREQ.din(cntl_rbf_stat);
n.nbusy := RB_MREQ.din(cntl_rbf_nbusy);
if r.nofifo='1' and RB_MREQ.din(cntl_rbf_nofifo)='0' then
ififo_reset := '1';
end if;
end if;
when rbaddr_data =>
irb_busy := irbena and isbusy;
if RB_MREQ.we='1' and isbusy='0' then
n.data := RB_MREQ.din;
end if;
when rbaddr_fifo =>
if r.nofifo = '0' then -- if fifo enabled
irb_busy := irbena and isbusy;
if RB_MREQ.re='1' and isbusy='0' then
if FIFO_EMPTY = '1' then
irb_err := '1';
else
ififo_re := '1';
end if;
end if;
if RB_MREQ.we='1' and isbusy='0' then
if FIFO_FULL = '1' then
irb_err := '1';
else
ififo_we := '1';
end if;
end if;
else -- else: if fifo disabled
irb_ack := '0'; -- nak it
if isbusy = '1' then -- or do a delayed nak
irb_ack := irbena;
irb_busy := irbena;
end if;
end if;
when rbaddr_attn =>
if RB_MREQ.we = '1' then
irblam := RB_MREQ.din;
end if;
when others => null;
end case;
end if;
-- rbus output driver
-- send a '0101...' pattern when selected and busy or err
-- send data only when busy=0 and err=0
-- this extra logic allows to debug rlink state machine
if r.rbsel = '1' then
if RB_MREQ.re='1' and irb_busy='0' and irb_err='0' then
case RB_MREQ.addr(1 downto 0) is
when rbaddr_cntl =>
irb_dout(cntl_rbf_stat) := r.stat;
irb_dout(cntl_rbf_nofifo) := r.nofifo;
irb_dout(cntl_rbf_nbusy) := r.nbusy;
when rbaddr_data =>
irb_dout := r.data;
when rbaddr_fifo =>
if r.nofifo='0' and FIFO_EMPTY = '0' then
irb_dout := FIFO_DO;
end if;
when rbaddr_attn =>
irb_dout(r.cntcyc'range) := r.ncyc;
when others => null;
end case;
else
irb_dout := "0101010101010101";
end if;
end if;
-- init transactions
if RB_MREQ.init='1' and RB_MREQ.we='1' and RB_MREQ.addr=RB_ADDR then
if RB_MREQ.din(init_rbf_cntl) = '1' then
n.nofifo := '0';
n.stat := (others=>'0');
n.nbusy := (others=>'0');
end if;
if RB_MREQ.din(init_rbf_data) = '1' then
n.data := (others=>'0');
end if;
if RB_MREQ.din(init_rbf_fifo) = '1' then
ififo_reset := '1';
end if;
end if;
-- other transactions
if irbena='0' and r.act_1='1' then
n.ncyc := r.cntcyc;
end if;
n.act_1 := irbena;
N_REGS <= n;
FIFO_RE <= ififo_re;
FIFO_WE <= ififo_we;
FIFO_RESET <= ififo_reset;
RB_SRES.dout <= irb_dout;
RB_SRES.ack <= irb_ack;
RB_SRES.err <= irb_err;
RB_SRES.busy <= irb_busy;
RB_LAM <= irblam;
RB_STAT <= r.stat;
end process proc_next;
end syn;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.mem_bus_pkg.all;
use work.cart_slot_pkg.all;
use work.io_bus_pkg.all;
use work.io_bus_bfm_pkg.all;
use work.command_if_pkg.all;
library std;
use std.textio.all;
entity harness_logic_32 is
end entity;
architecture tb of harness_logic_32 is
constant c_uart_divisor : natural := 10;
signal PHI2 : std_logic := '0';
signal RSTn : std_logic := 'H';
signal DOTCLK : std_logic := '1';
signal BUFFER_ENn : std_logic := '1';
signal BA : std_logic := '0';
signal DMAn : std_logic := '1';
signal EXROMn : std_logic;
signal GAMEn : std_logic;
signal ROMHn : std_logic := '1';
signal ROMLn : std_logic := '1';
signal IO1n : std_logic := '1';
signal IO2n : std_logic := '1';
signal IRQn : std_logic := '1';
signal NMIn : std_logic := '1';
signal slot_addr_o : std_logic_vector(15 downto 0);
signal slot_addr_i : std_logic_vector(15 downto 0) := (others => '1');
signal slot_addr_tl: std_logic;
signal slot_addr_th: std_logic;
signal slot_data_o : std_logic_vector(7 downto 0);
signal slot_data_i : std_logic_vector(7 downto 0) := (others => '1');
signal slot_data_t : std_logic;
-- Cassette
signal c2n_read_in : std_logic;
signal c2n_write_in : std_logic;
signal c2n_read_out : std_logic;
signal c2n_write_out : std_logic;
signal c2n_read_en : std_logic;
signal c2n_write_en : std_logic;
signal c2n_sense_in : std_logic;
signal c2n_sense_out : std_logic;
signal c2n_motor_in : std_logic;
signal c2n_motor_out : std_logic;
-- Parallel cable connection
signal drv_via1_port_a_o : std_logic_vector(7 downto 0);
signal drv_via1_port_a_i : std_logic_vector(7 downto 0);
signal drv_via1_port_a_t : std_logic_vector(7 downto 0);
signal drv_via1_ca2_o : std_logic;
signal drv_via1_ca2_i : std_logic;
signal drv_via1_ca2_t : std_logic;
signal drv_via1_cb1_o : std_logic;
signal drv_via1_cb1_i : std_logic;
signal drv_via1_cb1_t : std_logic;
signal IEC_ATN : std_logic := '1';
signal IEC_DATA : std_logic := '1';
signal IEC_CLOCK : std_logic := '1';
signal IEC_RESET : std_logic := '1';
signal IEC_SRQ_IN : std_logic := '1';
signal iec_atn_o : std_logic := '1';
signal iec_data_o : std_logic := '1';
signal iec_clock_o : std_logic := '1';
signal iec_reset_o : std_logic := '1';
signal iec_srq_o : std_logic := '1';
signal DISK_ACTn : std_logic; -- activity LED
signal CART_LEDn : std_logic;
signal SDACT_LEDn : std_logic;
signal MOTOR_LEDn : std_logic;
signal UART_TXD : std_logic;
signal UART_RXD : std_logic := '1';
signal SD_SSn : std_logic;
signal SD_CLK : std_logic;
signal SD_MOSI : std_logic;
signal SD_MISO : std_logic := '1';
signal SD_WP : std_logic := '1';
signal SD_CARDDETn : std_logic := '1';
signal SD_DATA : std_logic_vector(2 downto 1) := "HH";
signal BUTTON : std_logic_vector(2 downto 0) := "000";
signal SLOT_ADDR : std_logic_vector(15 downto 0);
signal SLOT_DATA : std_logic_vector(7 downto 0);
signal RWn : std_logic := '1';
signal CAS_MOTOR : std_logic := '1';
signal CAS_SENSE : std_logic := '0';
signal CAS_READ : std_logic := '0';
signal CAS_WRITE : std_logic := '0';
signal RTC_CS : std_logic;
signal RTC_SCK : std_logic;
signal RTC_MOSI : std_logic;
signal RTC_MISO : std_logic := '1';
signal FLASH_CSn : std_logic;
signal FLASH_SCK : std_logic;
signal FLASH_MOSI : std_logic;
signal FLASH_MISO : std_logic := '1';
signal ULPI_CLOCK : std_logic := '0';
signal ULPI_RESET : std_logic := '0';
signal ULPI_NXT : std_logic := '0';
signal ULPI_STP : std_logic;
signal ULPI_DIR : std_logic := '0';
signal ULPI_DATA : std_logic_vector(7 downto 0) := (others => 'H');
signal sys_clock : std_logic := '1';
signal sys_reset : std_logic := '1';
signal sys_clock_2x : std_logic := '1';
signal rx_char : std_logic_vector(7 downto 0);
signal rx_char_d : std_logic_vector(7 downto 0);
signal rx_ack : std_logic;
signal tx_char : std_logic_vector(7 downto 0) := X"00";
signal tx_done : std_logic;
signal do_tx : std_logic := '0';
-- memory controller interconnect
signal mem_inhibit : std_logic := '0';
signal mem_req : t_mem_req_32;
signal mem_resp : t_mem_resp_32;
signal io_req : t_io_req;
signal io_resp : t_io_resp;
signal CLOCK_50 : std_logic := '0';
signal SDRAM_CLK : std_logic;
signal SDRAM_CKE : std_logic;
signal SDRAM_CSn : std_logic := '1';
signal SDRAM_RASn : std_logic := '1';
signal SDRAM_CASn : std_logic := '1';
signal SDRAM_WEn : std_logic := '1';
signal SDRAM_DQM : std_logic := '0';
signal SDRAM_A : std_logic_vector(12 downto 0);
signal SDRAM_BA : std_logic_vector(1 downto 0);
signal SDRAM_DQ : std_logic_vector(7 downto 0) := (others => 'Z');
begin
sys_clock <= not sys_clock after 10 ns;
sys_clock_2x <= not sys_clock_2x after 5 ns;
sys_reset <= '1', '0' after 100 ns;
mut: entity work.ultimate_logic_32
generic map (
g_version => X"02",
g_simulation => true,
g_clock_freq => 50_000_000,
g_baud_rate => 1_000_000,
g_timer_rate => 200_000,
g_boot_rom => false,
g_video_overlay => false,
g_icap => false,
g_uart => true,
g_drive_1541 => true,
g_drive_1541_2 => false,
g_hardware_gcr => true,
g_cartridge => true,
g_command_intf => true,
g_stereo_sid => false,
g_ram_expansion => true,
g_extended_reu => false,
g_hardware_iec => false,
g_c2n_streamer => false,
g_c2n_recorder => false,
g_drive_sound => true,
g_rtc_chip => false,
g_rtc_timer => false,
g_usb_host => false,
g_usb_host2 => true,
g_spi_flash => true,
g_vic_copper => false,
g_sampler => false,
g_profiler => true,
g_analyzer => false )
port map (
sys_clock => sys_clock,
sys_reset => sys_reset,
ulpi_clock => ulpi_clock,
ulpi_reset => ulpi_reset,
phi2_i => PHI2,
dotclk_i => DOTCLK,
rstn_o => RSTn,
rstn_i => RSTn,
slot_addr_o => slot_addr_o,
slot_addr_i => SLOT_ADDR,
slot_addr_tl => slot_addr_tl,
slot_addr_th => slot_addr_th,
slot_data_o => slot_data_o,
slot_data_i => SLOT_DATA,
slot_data_t => slot_data_t,
rwn_i => RWn,
rwn_o => RWn,
exromn_i => EXROMn,
exromn_o => EXROMn,
gamen_i => GAMEn,
gamen_o => GAMEn,
irqn_i => IRQn,
irqn_o => IRQn,
nmin_i => NMIn,
nmin_o => NMIn,
ba_i => BA,
dman_o => DMAn,
romhn_i => ROMHn,
romln_i => ROMLn,
io1n_i => IO1n,
io2n_i => IO2n,
-- Parallel cable pins
drv_via1_port_a_o => drv_via1_port_a_o,
drv_via1_port_a_i => drv_via1_port_a_i,
drv_via1_port_a_t => drv_via1_port_a_t,
drv_via1_ca2_o => drv_via1_ca2_o,
drv_via1_ca2_i => drv_via1_ca2_i,
drv_via1_ca2_t => drv_via1_ca2_t,
drv_via1_cb1_o => drv_via1_cb1_o,
drv_via1_cb1_i => drv_via1_cb1_i,
drv_via1_cb1_t => drv_via1_cb1_t,
-- Cassette Interface
c2n_read_in => c2n_read_in,
c2n_write_in => c2n_write_in,
c2n_read_out => c2n_read_out,
c2n_write_out => c2n_write_out,
c2n_read_en => c2n_read_en,
c2n_write_en => c2n_write_en,
c2n_sense_in => c2n_sense_in,
c2n_sense_out => c2n_sense_out,
c2n_motor_in => c2n_motor_in,
c2n_motor_out => c2n_motor_out,
mem_inhibit => mem_inhibit,
mem_req => mem_req,
mem_resp => mem_resp,
iec_reset_i => IEC_RESET,
iec_atn_i => IEC_ATN,
iec_data_i => IEC_DATA,
iec_clock_i => IEC_CLOCK,
iec_srq_i => IEC_SRQ_IN,
iec_reset_o => iec_reset_o,
iec_atn_o => iec_atn_o,
iec_data_o => iec_data_o,
iec_clock_o => iec_clock_o,
iec_srq_o => iec_srq_o,
BUTTON => BUTTON,
DISK_ACTn => DISK_ACTn,
CART_LEDn => CART_LEDn,
SDACT_LEDn => SDACT_LEDn,
MOTOR_LEDn => MOTOR_LEDn,
UART_TXD => UART_TXD,
UART_RXD => UART_RXD,
SD_SSn => SD_SSn,
SD_CLK => SD_CLK,
SD_MOSI => SD_MOSI,
SD_MISO => SD_MISO,
SD_CARDDETn => SD_CARDDETn,
SD_DATA => SD_DATA,
RTC_CS => RTC_CS,
RTC_SCK => RTC_SCK,
RTC_MOSI => RTC_MOSI,
RTC_MISO => RTC_MISO,
FLASH_CSn => FLASH_CSn,
FLASH_SCK => FLASH_SCK,
FLASH_MOSI => FLASH_MOSI,
FLASH_MISO => FLASH_MISO,
ULPI_NXT => ULPI_NXT,
ULPI_STP => ULPI_STP,
ULPI_DIR => ULPI_DIR,
ULPI_DATA => ULPI_DATA,
ext_io_req => io_req,
ext_io_resp => io_resp );
SLOT_ADDR(15 downto 12) <= slot_addr_o(15 downto 12) when slot_addr_th = '1' else (others => 'H');
SLOT_ADDR(11 downto 00) <= slot_addr_o(11 downto 00) when slot_addr_tl = '1' else (others => 'H');
SLOT_DATA <= slot_data_o when slot_data_t = '1' else (others => 'H');
-- Parallel cable not implemented. This is the way to stub it...
drv_via1_port_a_i <= drv_via1_port_a_o or not drv_via1_port_a_t;
drv_via1_ca2_i <= drv_via1_ca2_o or not drv_via1_ca2_t;
drv_via1_cb1_i <= drv_via1_cb1_o or not drv_via1_cb1_t;
i_mem_ctrl: entity work.ext_mem_ctrl_v5
generic map (
g_simulation => false )
port map (
clock => sys_clock,
clk_2x => sys_clock_2x,
reset => sys_reset,
inhibit => mem_inhibit,
is_idle => open,
req => mem_req,
resp => mem_resp,
SDRAM_CLK => SDRAM_CLK,
SDRAM_CKE => SDRAM_CKE,
SDRAM_CSn => SDRAM_CSn,
SDRAM_RASn => SDRAM_RASn,
SDRAM_CASn => SDRAM_CASn,
SDRAM_WEn => SDRAM_WEn,
SDRAM_DQM => SDRAM_DQM,
SDRAM_BA => SDRAM_BA,
SDRAM_A => SDRAM_A,
SDRAM_DQ => SDRAM_DQ );
ULPI_CLOCK <= not ULPI_CLOCK after 8.333 ns; -- 60 MHz
ULPI_RESET <= '1', '0' after 100 ns;
PHI2 <= not PHI2 after 507.5 ns; -- 0.98525 MHz
RSTn <= '0', 'H' after 6 us, '0' after 100 us, 'H' after 105 us;
i_io_bfm: entity work.io_bus_bfm
generic map (
g_name => "io_bfm" )
port map (
clock => sys_clock,
req => io_req,
resp => io_resp );
SLOT_DATA <= (others => 'H');
ROMHn <= '1';
ROMLn <= not PHI2 after 50 ns;
IO1n <= '1';
IO2n <= '1';
process
begin
SLOT_ADDR <= X"7F00";
RWn <= '1';
while true loop
wait until PHI2 = '0';
--SLOT_ADDR(8 downto 0) <= std_logic_vector(unsigned(SLOT_ADDR(8 downto 0)) + 1);
SLOT_ADDR <= std_logic_vector(unsigned(SLOT_ADDR) + 1);
RWn <= '1';
wait until PHI2 = '0';
RWn <= '0';
end loop;
end process;
process
begin
BA <= '1';
for i in 0 to 100 loop
wait until PHI2='0';
end loop;
BA <= '0';
for i in 0 to 10 loop
wait until PHI2='0';
end loop;
end process;
ram: entity work.dram_8
generic map(
g_cas_latency => 3,
g_burst_len_r => 4,
g_burst_len_w => 4,
g_column_bits => 10,
g_row_bits => 13,
g_bank_bits => 2
)
port map(
CLK => SDRAM_CLK,
CKE => SDRAM_CKE,
A => SDRAM_A,
BA => SDRAM_BA,
CSn => SDRAM_CSn,
RASn => SDRAM_RASn,
CASn => SDRAM_CASn,
WEn => SDRAM_WEn,
DQM => SDRAM_DQM,
DQ => SDRAM_DQ
);
-- i_ulpi_phy: entity work.ulpi_master_bfm
-- generic map (
-- g_given_name => "device" )
--
-- port map (
-- clock => ULPI_CLOCK,
-- reset => ULPI_RESET,
-- ulpi_nxt => ulpi_nxt,
-- ulpi_stp => ulpi_stp,
-- ulpi_dir => ulpi_dir,
-- ulpi_data => ulpi_data );
--
-- i_device: entity work.usb_device_model;
i_rx: entity work.rx
generic map (c_uart_divisor)
port map (
clk => sys_clock,
reset => sys_reset,
tick => '1',
rxd => UART_TXD,
rxchar => rx_char,
rx_ack => rx_ack );
i_tx: entity work.tx
generic map (c_uart_divisor)
port map (
clk => sys_clock,
reset => sys_reset,
tick => '1',
dotx => do_tx,
txchar => tx_char,
done => tx_done,
txd => UART_RXD );
process(sys_clock)
variable s : line;
variable char : character;
begin
if rising_edge(sys_clock) then
if rx_ack='1' then
rx_char_d <= rx_char;
char := character'val(to_integer(unsigned(rx_char)));
if rx_char = X"0D" then
-- Ignore character 13
elsif rx_char = X"0A" then
-- Writeline on character 10 (newline)
writeline(output, s);
else
-- Write to buffer
write(s, char);
end if;
end if;
if mem_resp.rack = '1' and mem_req.address < 16 then
report "Access to address " & integer'image(to_integer(mem_req.address)) severity error;
end if;
end if;
end process;
process
variable io : p_io_bus_bfm_object;
begin
wait until sys_reset='0';
wait until sys_clock='1';
bind_io_bus_bfm("io_bfm", io);
io_write(io, X"40000" + c_cart_c64_mode, X"04"); -- reset
io_write(io, X"40000" + c_cart_cartridge_type, X"06"); -- retro
io_write(io, X"40000" + c_cart_c64_mode, X"08"); -- unreset
io_write(io, X"44000" + c_cif_io_slot_base, X"7E");
io_write(io, X"44000" + c_cif_io_slot_enable, X"01");
wait for 6 us;
wait until sys_clock='1';
--io_write(io, X"42002", X"42");
wait;
end process;
process
procedure send_char(i: std_logic_vector(7 downto 0)) is
begin
if tx_done /= '1' then
wait until tx_done = '1';
end if;
wait until sys_clock='1';
tx_char <= i;
do_tx <= '1';
wait until tx_done = '0';
wait until sys_clock='1';
do_tx <= '0';
end procedure;
procedure send_string(i : string) is
variable b : std_logic_vector(7 downto 0);
begin
for n in i'range loop
b := std_logic_vector(to_unsigned(character'pos(i(n)), 8));
send_char(b);
end loop;
send_char(X"0d");
send_char(X"0a");
end procedure;
begin
wait for 2 ms;
--send_string("wd 4005000 12345678");
send_string("run");
-- send_string("m 100000");
-- send_string("w 400000F 4");
wait;
end process;
-- check timing data
process(PHI2)
begin
if falling_edge(PHI2) then
assert SLOT_DATA'last_event >= 189 ns
report "Timing error on C64 bus."
severity error;
end if;
end process;
end tb;
|
/* Using vhdl 2008 comments. */
entity simple08 is
end;
architecture behav of simple08 is
begin
process
begin
assert false report "Test is running" severity note;
wait; -- Indefinite
end process;
end behav;
|
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