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----------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2004 GAISLER RESEARCH
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- See the file COPYING for the full details of the license.
--
-----------------------------------------------------------------------------
-- Entity: ahbrom
-- File: ahbrom.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: AHB rom. 0/1-waitstate read
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
entity ahbrom is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#fff#;
pipe : integer := 0;
tech : integer := 0;
kbytes : integer := 1);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type
);
end;
architecture rtl of ahbrom is
constant abits : integer := 9;
constant bytes : integer := 288;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_AHBROM, 0, 0, 0),
4 => ahb_membar(haddr, '1', '1', hmask), others => zero32);
signal romdata : std_logic_vector(31 downto 0);
signal addr : std_logic_vector(abits-1 downto 2);
signal hsel, hready : std_ulogic;
begin
ahbso.hresp <= "00";
ahbso.hsplit <= (others => '0');
ahbso.hirq <= (others => '0');
ahbso.hconfig <= hconfig;
ahbso.hindex <= hindex;
reg : process (clk)
begin
if rising_edge(clk) then
addr <= ahbsi.haddr(abits-1 downto 2);
end if;
end process;
p0 : if pipe = 0 generate
ahbso.hrdata <= ahbdrivedata(romdata);
ahbso.hready <= '1';
end generate;
p1 : if pipe = 1 generate
reg2 : process (clk)
begin
if rising_edge(clk) then
hsel <= ahbsi.hsel(hindex) and ahbsi.htrans(1);
hready <= ahbsi.hready;
ahbso.hready <= (not rst) or (hsel and hready) or
(ahbsi.hsel(hindex) and not ahbsi.htrans(1) and ahbsi.hready);
ahbso.hrdata <= ahbdrivedata(romdata);
end if;
end process;
end generate;
comb : process (addr)
begin
case conv_integer(addr) is
when 16#00000# => romdata <= X"81D82000";
when 16#00001# => romdata <= X"03000004";
when 16#00002# => romdata <= X"821060C0";
when 16#00003# => romdata <= X"81884000";
when 16#00004# => romdata <= X"81900000";
when 16#00005# => romdata <= X"81980000";
when 16#00006# => romdata <= X"81800000";
when 16#00007# => romdata <= X"01000000";
when 16#00008# => romdata <= X"03000040";
when 16#00009# => romdata <= X"8210600F";
when 16#0000A# => romdata <= X"C2A00040";
when 16#0000B# => romdata <= X"87444000";
when 16#0000C# => romdata <= X"8608E01F";
when 16#0000D# => romdata <= X"88100000";
when 16#0000E# => romdata <= X"8A100000";
when 16#0000F# => romdata <= X"8C100000";
when 16#00010# => romdata <= X"8E100000";
when 16#00011# => romdata <= X"A0100000";
when 16#00012# => romdata <= X"A2100000";
when 16#00013# => romdata <= X"A4100000";
when 16#00014# => romdata <= X"A6100000";
when 16#00015# => romdata <= X"A8100000";
when 16#00016# => romdata <= X"AA100000";
when 16#00017# => romdata <= X"AC100000";
when 16#00018# => romdata <= X"AE100000";
when 16#00019# => romdata <= X"90100000";
when 16#0001A# => romdata <= X"92100000";
when 16#0001B# => romdata <= X"94100000";
when 16#0001C# => romdata <= X"96100000";
when 16#0001D# => romdata <= X"98100000";
when 16#0001E# => romdata <= X"9A100000";
when 16#0001F# => romdata <= X"9C100000";
when 16#00020# => romdata <= X"9E100000";
when 16#00021# => romdata <= X"86A0E001";
when 16#00022# => romdata <= X"16BFFFEF";
when 16#00023# => romdata <= X"81E00000";
when 16#00024# => romdata <= X"82102002";
when 16#00025# => romdata <= X"81904000";
when 16#00026# => romdata <= X"03000004";
when 16#00027# => romdata <= X"821060E0";
when 16#00028# => romdata <= X"81884000";
when 16#00029# => romdata <= X"01000000";
when 16#0002A# => romdata <= X"01000000";
when 16#0002B# => romdata <= X"01000000";
when 16#0002C# => romdata <= X"03200000";
when 16#0002D# => romdata <= X"84102233";
when 16#0002E# => romdata <= X"C4204000";
when 16#0002F# => romdata <= X"0539AE13";
when 16#00030# => romdata <= X"8410A260";
when 16#00031# => romdata <= X"C4206004";
when 16#00032# => romdata <= X"050003FC";
when 16#00033# => romdata <= X"C4206008";
when 16#00034# => romdata <= X"3D1003FF";
when 16#00035# => romdata <= X"BC17A3E0";
when 16#00036# => romdata <= X"9C27A060";
when 16#00037# => romdata <= X"03100000";
when 16#00038# => romdata <= X"81C04000";
when 16#00039# => romdata <= X"01000000";
when 16#0003A# => romdata <= X"01000000";
when 16#0003B# => romdata <= X"01000000";
when 16#0003C# => romdata <= X"01000000";
when 16#0003D# => romdata <= X"01000000";
when 16#0003E# => romdata <= X"01000000";
when 16#0003F# => romdata <= X"01000000";
when 16#00040# => romdata <= X"00000004";
when 16#00041# => romdata <= X"00000000";
when 16#00042# => romdata <= X"00000004";
when 16#00043# => romdata <= X"00000000";
when 16#00044# => romdata <= X"FFFFFFFC";
when 16#00045# => romdata <= X"00000000";
when 16#00046# => romdata <= X"FFFFFFFC";
when 16#00047# => romdata <= X"00000000";
when 16#00048# => romdata <= X"00000000";
when others => romdata <= (others => '-');
end case;
end process;
-- pragma translate_off
bootmsg : report_version
generic map ("ahbrom" & tost(hindex) &
": 32-bit AHB ROM Module, " & tost(bytes/4) & " words, " & tost(abits-2) & " address bits" );
-- pragma translate_on
end;
|
----------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2004 GAISLER RESEARCH
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- See the file COPYING for the full details of the license.
--
-----------------------------------------------------------------------------
-- Entity: ahbrom
-- File: ahbrom.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: AHB rom. 0/1-waitstate read
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
entity ahbrom is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#fff#;
pipe : integer := 0;
tech : integer := 0;
kbytes : integer := 1);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type
);
end;
architecture rtl of ahbrom is
constant abits : integer := 9;
constant bytes : integer := 288;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_AHBROM, 0, 0, 0),
4 => ahb_membar(haddr, '1', '1', hmask), others => zero32);
signal romdata : std_logic_vector(31 downto 0);
signal addr : std_logic_vector(abits-1 downto 2);
signal hsel, hready : std_ulogic;
begin
ahbso.hresp <= "00";
ahbso.hsplit <= (others => '0');
ahbso.hirq <= (others => '0');
ahbso.hconfig <= hconfig;
ahbso.hindex <= hindex;
reg : process (clk)
begin
if rising_edge(clk) then
addr <= ahbsi.haddr(abits-1 downto 2);
end if;
end process;
p0 : if pipe = 0 generate
ahbso.hrdata <= ahbdrivedata(romdata);
ahbso.hready <= '1';
end generate;
p1 : if pipe = 1 generate
reg2 : process (clk)
begin
if rising_edge(clk) then
hsel <= ahbsi.hsel(hindex) and ahbsi.htrans(1);
hready <= ahbsi.hready;
ahbso.hready <= (not rst) or (hsel and hready) or
(ahbsi.hsel(hindex) and not ahbsi.htrans(1) and ahbsi.hready);
ahbso.hrdata <= ahbdrivedata(romdata);
end if;
end process;
end generate;
comb : process (addr)
begin
case conv_integer(addr) is
when 16#00000# => romdata <= X"81D82000";
when 16#00001# => romdata <= X"03000004";
when 16#00002# => romdata <= X"821060C0";
when 16#00003# => romdata <= X"81884000";
when 16#00004# => romdata <= X"81900000";
when 16#00005# => romdata <= X"81980000";
when 16#00006# => romdata <= X"81800000";
when 16#00007# => romdata <= X"01000000";
when 16#00008# => romdata <= X"03000040";
when 16#00009# => romdata <= X"8210600F";
when 16#0000A# => romdata <= X"C2A00040";
when 16#0000B# => romdata <= X"87444000";
when 16#0000C# => romdata <= X"8608E01F";
when 16#0000D# => romdata <= X"88100000";
when 16#0000E# => romdata <= X"8A100000";
when 16#0000F# => romdata <= X"8C100000";
when 16#00010# => romdata <= X"8E100000";
when 16#00011# => romdata <= X"A0100000";
when 16#00012# => romdata <= X"A2100000";
when 16#00013# => romdata <= X"A4100000";
when 16#00014# => romdata <= X"A6100000";
when 16#00015# => romdata <= X"A8100000";
when 16#00016# => romdata <= X"AA100000";
when 16#00017# => romdata <= X"AC100000";
when 16#00018# => romdata <= X"AE100000";
when 16#00019# => romdata <= X"90100000";
when 16#0001A# => romdata <= X"92100000";
when 16#0001B# => romdata <= X"94100000";
when 16#0001C# => romdata <= X"96100000";
when 16#0001D# => romdata <= X"98100000";
when 16#0001E# => romdata <= X"9A100000";
when 16#0001F# => romdata <= X"9C100000";
when 16#00020# => romdata <= X"9E100000";
when 16#00021# => romdata <= X"86A0E001";
when 16#00022# => romdata <= X"16BFFFEF";
when 16#00023# => romdata <= X"81E00000";
when 16#00024# => romdata <= X"82102002";
when 16#00025# => romdata <= X"81904000";
when 16#00026# => romdata <= X"03000004";
when 16#00027# => romdata <= X"821060E0";
when 16#00028# => romdata <= X"81884000";
when 16#00029# => romdata <= X"01000000";
when 16#0002A# => romdata <= X"01000000";
when 16#0002B# => romdata <= X"01000000";
when 16#0002C# => romdata <= X"03200000";
when 16#0002D# => romdata <= X"84102233";
when 16#0002E# => romdata <= X"C4204000";
when 16#0002F# => romdata <= X"0539AE13";
when 16#00030# => romdata <= X"8410A260";
when 16#00031# => romdata <= X"C4206004";
when 16#00032# => romdata <= X"050003FC";
when 16#00033# => romdata <= X"C4206008";
when 16#00034# => romdata <= X"3D1003FF";
when 16#00035# => romdata <= X"BC17A3E0";
when 16#00036# => romdata <= X"9C27A060";
when 16#00037# => romdata <= X"03100000";
when 16#00038# => romdata <= X"81C04000";
when 16#00039# => romdata <= X"01000000";
when 16#0003A# => romdata <= X"01000000";
when 16#0003B# => romdata <= X"01000000";
when 16#0003C# => romdata <= X"01000000";
when 16#0003D# => romdata <= X"01000000";
when 16#0003E# => romdata <= X"01000000";
when 16#0003F# => romdata <= X"01000000";
when 16#00040# => romdata <= X"00000004";
when 16#00041# => romdata <= X"00000000";
when 16#00042# => romdata <= X"00000004";
when 16#00043# => romdata <= X"00000000";
when 16#00044# => romdata <= X"FFFFFFFC";
when 16#00045# => romdata <= X"00000000";
when 16#00046# => romdata <= X"FFFFFFFC";
when 16#00047# => romdata <= X"00000000";
when 16#00048# => romdata <= X"00000000";
when others => romdata <= (others => '-');
end case;
end process;
-- pragma translate_off
bootmsg : report_version
generic map ("ahbrom" & tost(hindex) &
": 32-bit AHB ROM Module, " & tost(bytes/4) & " words, " & tost(abits-2) & " address bits" );
-- pragma translate_on
end;
|
----------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2004 GAISLER RESEARCH
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- See the file COPYING for the full details of the license.
--
-----------------------------------------------------------------------------
-- Entity: ahbrom
-- File: ahbrom.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: AHB rom. 0/1-waitstate read
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
entity ahbrom is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#fff#;
pipe : integer := 0;
tech : integer := 0;
kbytes : integer := 1);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type
);
end;
architecture rtl of ahbrom is
constant abits : integer := 9;
constant bytes : integer := 288;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_AHBROM, 0, 0, 0),
4 => ahb_membar(haddr, '1', '1', hmask), others => zero32);
signal romdata : std_logic_vector(31 downto 0);
signal addr : std_logic_vector(abits-1 downto 2);
signal hsel, hready : std_ulogic;
begin
ahbso.hresp <= "00";
ahbso.hsplit <= (others => '0');
ahbso.hirq <= (others => '0');
ahbso.hconfig <= hconfig;
ahbso.hindex <= hindex;
reg : process (clk)
begin
if rising_edge(clk) then
addr <= ahbsi.haddr(abits-1 downto 2);
end if;
end process;
p0 : if pipe = 0 generate
ahbso.hrdata <= ahbdrivedata(romdata);
ahbso.hready <= '1';
end generate;
p1 : if pipe = 1 generate
reg2 : process (clk)
begin
if rising_edge(clk) then
hsel <= ahbsi.hsel(hindex) and ahbsi.htrans(1);
hready <= ahbsi.hready;
ahbso.hready <= (not rst) or (hsel and hready) or
(ahbsi.hsel(hindex) and not ahbsi.htrans(1) and ahbsi.hready);
ahbso.hrdata <= ahbdrivedata(romdata);
end if;
end process;
end generate;
comb : process (addr)
begin
case conv_integer(addr) is
when 16#00000# => romdata <= X"81D82000";
when 16#00001# => romdata <= X"03000004";
when 16#00002# => romdata <= X"821060C0";
when 16#00003# => romdata <= X"81884000";
when 16#00004# => romdata <= X"81900000";
when 16#00005# => romdata <= X"81980000";
when 16#00006# => romdata <= X"81800000";
when 16#00007# => romdata <= X"01000000";
when 16#00008# => romdata <= X"03000040";
when 16#00009# => romdata <= X"8210600F";
when 16#0000A# => romdata <= X"C2A00040";
when 16#0000B# => romdata <= X"87444000";
when 16#0000C# => romdata <= X"8608E01F";
when 16#0000D# => romdata <= X"88100000";
when 16#0000E# => romdata <= X"8A100000";
when 16#0000F# => romdata <= X"8C100000";
when 16#00010# => romdata <= X"8E100000";
when 16#00011# => romdata <= X"A0100000";
when 16#00012# => romdata <= X"A2100000";
when 16#00013# => romdata <= X"A4100000";
when 16#00014# => romdata <= X"A6100000";
when 16#00015# => romdata <= X"A8100000";
when 16#00016# => romdata <= X"AA100000";
when 16#00017# => romdata <= X"AC100000";
when 16#00018# => romdata <= X"AE100000";
when 16#00019# => romdata <= X"90100000";
when 16#0001A# => romdata <= X"92100000";
when 16#0001B# => romdata <= X"94100000";
when 16#0001C# => romdata <= X"96100000";
when 16#0001D# => romdata <= X"98100000";
when 16#0001E# => romdata <= X"9A100000";
when 16#0001F# => romdata <= X"9C100000";
when 16#00020# => romdata <= X"9E100000";
when 16#00021# => romdata <= X"86A0E001";
when 16#00022# => romdata <= X"16BFFFEF";
when 16#00023# => romdata <= X"81E00000";
when 16#00024# => romdata <= X"82102002";
when 16#00025# => romdata <= X"81904000";
when 16#00026# => romdata <= X"03000004";
when 16#00027# => romdata <= X"821060E0";
when 16#00028# => romdata <= X"81884000";
when 16#00029# => romdata <= X"01000000";
when 16#0002A# => romdata <= X"01000000";
when 16#0002B# => romdata <= X"01000000";
when 16#0002C# => romdata <= X"03200000";
when 16#0002D# => romdata <= X"84102233";
when 16#0002E# => romdata <= X"C4204000";
when 16#0002F# => romdata <= X"0539AE13";
when 16#00030# => romdata <= X"8410A260";
when 16#00031# => romdata <= X"C4206004";
when 16#00032# => romdata <= X"050003FC";
when 16#00033# => romdata <= X"C4206008";
when 16#00034# => romdata <= X"3D1003FF";
when 16#00035# => romdata <= X"BC17A3E0";
when 16#00036# => romdata <= X"9C27A060";
when 16#00037# => romdata <= X"03100000";
when 16#00038# => romdata <= X"81C04000";
when 16#00039# => romdata <= X"01000000";
when 16#0003A# => romdata <= X"01000000";
when 16#0003B# => romdata <= X"01000000";
when 16#0003C# => romdata <= X"01000000";
when 16#0003D# => romdata <= X"01000000";
when 16#0003E# => romdata <= X"01000000";
when 16#0003F# => romdata <= X"01000000";
when 16#00040# => romdata <= X"00000004";
when 16#00041# => romdata <= X"00000000";
when 16#00042# => romdata <= X"00000004";
when 16#00043# => romdata <= X"00000000";
when 16#00044# => romdata <= X"FFFFFFFC";
when 16#00045# => romdata <= X"00000000";
when 16#00046# => romdata <= X"FFFFFFFC";
when 16#00047# => romdata <= X"00000000";
when 16#00048# => romdata <= X"00000000";
when others => romdata <= (others => '-');
end case;
end process;
-- pragma translate_off
bootmsg : report_version
generic map ("ahbrom" & tost(hindex) &
": 32-bit AHB ROM Module, " & tost(bytes/4) & " words, " & tost(abits-2) & " address bits" );
-- pragma translate_on
end;
|
----------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2004 GAISLER RESEARCH
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- See the file COPYING for the full details of the license.
--
-----------------------------------------------------------------------------
-- Entity: ahbrom
-- File: ahbrom.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: AHB rom. 0/1-waitstate read
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
entity ahbrom is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#fff#;
pipe : integer := 0;
tech : integer := 0;
kbytes : integer := 1);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type
);
end;
architecture rtl of ahbrom is
constant abits : integer := 9;
constant bytes : integer := 288;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_AHBROM, 0, 0, 0),
4 => ahb_membar(haddr, '1', '1', hmask), others => zero32);
signal romdata : std_logic_vector(31 downto 0);
signal addr : std_logic_vector(abits-1 downto 2);
signal hsel, hready : std_ulogic;
begin
ahbso.hresp <= "00";
ahbso.hsplit <= (others => '0');
ahbso.hirq <= (others => '0');
ahbso.hconfig <= hconfig;
ahbso.hindex <= hindex;
reg : process (clk)
begin
if rising_edge(clk) then
addr <= ahbsi.haddr(abits-1 downto 2);
end if;
end process;
p0 : if pipe = 0 generate
ahbso.hrdata <= ahbdrivedata(romdata);
ahbso.hready <= '1';
end generate;
p1 : if pipe = 1 generate
reg2 : process (clk)
begin
if rising_edge(clk) then
hsel <= ahbsi.hsel(hindex) and ahbsi.htrans(1);
hready <= ahbsi.hready;
ahbso.hready <= (not rst) or (hsel and hready) or
(ahbsi.hsel(hindex) and not ahbsi.htrans(1) and ahbsi.hready);
ahbso.hrdata <= ahbdrivedata(romdata);
end if;
end process;
end generate;
comb : process (addr)
begin
case conv_integer(addr) is
when 16#00000# => romdata <= X"81D82000";
when 16#00001# => romdata <= X"03000004";
when 16#00002# => romdata <= X"821060C0";
when 16#00003# => romdata <= X"81884000";
when 16#00004# => romdata <= X"81900000";
when 16#00005# => romdata <= X"81980000";
when 16#00006# => romdata <= X"81800000";
when 16#00007# => romdata <= X"01000000";
when 16#00008# => romdata <= X"03000040";
when 16#00009# => romdata <= X"8210600F";
when 16#0000A# => romdata <= X"C2A00040";
when 16#0000B# => romdata <= X"87444000";
when 16#0000C# => romdata <= X"8608E01F";
when 16#0000D# => romdata <= X"88100000";
when 16#0000E# => romdata <= X"8A100000";
when 16#0000F# => romdata <= X"8C100000";
when 16#00010# => romdata <= X"8E100000";
when 16#00011# => romdata <= X"A0100000";
when 16#00012# => romdata <= X"A2100000";
when 16#00013# => romdata <= X"A4100000";
when 16#00014# => romdata <= X"A6100000";
when 16#00015# => romdata <= X"A8100000";
when 16#00016# => romdata <= X"AA100000";
when 16#00017# => romdata <= X"AC100000";
when 16#00018# => romdata <= X"AE100000";
when 16#00019# => romdata <= X"90100000";
when 16#0001A# => romdata <= X"92100000";
when 16#0001B# => romdata <= X"94100000";
when 16#0001C# => romdata <= X"96100000";
when 16#0001D# => romdata <= X"98100000";
when 16#0001E# => romdata <= X"9A100000";
when 16#0001F# => romdata <= X"9C100000";
when 16#00020# => romdata <= X"9E100000";
when 16#00021# => romdata <= X"86A0E001";
when 16#00022# => romdata <= X"16BFFFEF";
when 16#00023# => romdata <= X"81E00000";
when 16#00024# => romdata <= X"82102002";
when 16#00025# => romdata <= X"81904000";
when 16#00026# => romdata <= X"03000004";
when 16#00027# => romdata <= X"821060E0";
when 16#00028# => romdata <= X"81884000";
when 16#00029# => romdata <= X"01000000";
when 16#0002A# => romdata <= X"01000000";
when 16#0002B# => romdata <= X"01000000";
when 16#0002C# => romdata <= X"03200000";
when 16#0002D# => romdata <= X"84102233";
when 16#0002E# => romdata <= X"C4204000";
when 16#0002F# => romdata <= X"0539AE13";
when 16#00030# => romdata <= X"8410A260";
when 16#00031# => romdata <= X"C4206004";
when 16#00032# => romdata <= X"050003FC";
when 16#00033# => romdata <= X"C4206008";
when 16#00034# => romdata <= X"3D1003FF";
when 16#00035# => romdata <= X"BC17A3E0";
when 16#00036# => romdata <= X"9C27A060";
when 16#00037# => romdata <= X"03100000";
when 16#00038# => romdata <= X"81C04000";
when 16#00039# => romdata <= X"01000000";
when 16#0003A# => romdata <= X"01000000";
when 16#0003B# => romdata <= X"01000000";
when 16#0003C# => romdata <= X"01000000";
when 16#0003D# => romdata <= X"01000000";
when 16#0003E# => romdata <= X"01000000";
when 16#0003F# => romdata <= X"01000000";
when 16#00040# => romdata <= X"00000004";
when 16#00041# => romdata <= X"00000000";
when 16#00042# => romdata <= X"00000004";
when 16#00043# => romdata <= X"00000000";
when 16#00044# => romdata <= X"FFFFFFFC";
when 16#00045# => romdata <= X"00000000";
when 16#00046# => romdata <= X"FFFFFFFC";
when 16#00047# => romdata <= X"00000000";
when 16#00048# => romdata <= X"00000000";
when others => romdata <= (others => '-');
end case;
end process;
-- pragma translate_off
bootmsg : report_version
generic map ("ahbrom" & tost(hindex) &
": 32-bit AHB ROM Module, " & tost(bytes/4) & " words, " & tost(abits-2) & " address bits" );
-- pragma translate_on
end;
|
----------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2004 GAISLER RESEARCH
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- See the file COPYING for the full details of the license.
--
-----------------------------------------------------------------------------
-- Entity: ahbrom
-- File: ahbrom.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: AHB rom. 0/1-waitstate read
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
entity ahbrom is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#fff#;
pipe : integer := 0;
tech : integer := 0;
kbytes : integer := 1);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type
);
end;
architecture rtl of ahbrom is
constant abits : integer := 9;
constant bytes : integer := 288;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_AHBROM, 0, 0, 0),
4 => ahb_membar(haddr, '1', '1', hmask), others => zero32);
signal romdata : std_logic_vector(31 downto 0);
signal addr : std_logic_vector(abits-1 downto 2);
signal hsel, hready : std_ulogic;
begin
ahbso.hresp <= "00";
ahbso.hsplit <= (others => '0');
ahbso.hirq <= (others => '0');
ahbso.hconfig <= hconfig;
ahbso.hindex <= hindex;
reg : process (clk)
begin
if rising_edge(clk) then
addr <= ahbsi.haddr(abits-1 downto 2);
end if;
end process;
p0 : if pipe = 0 generate
ahbso.hrdata <= ahbdrivedata(romdata);
ahbso.hready <= '1';
end generate;
p1 : if pipe = 1 generate
reg2 : process (clk)
begin
if rising_edge(clk) then
hsel <= ahbsi.hsel(hindex) and ahbsi.htrans(1);
hready <= ahbsi.hready;
ahbso.hready <= (not rst) or (hsel and hready) or
(ahbsi.hsel(hindex) and not ahbsi.htrans(1) and ahbsi.hready);
ahbso.hrdata <= ahbdrivedata(romdata);
end if;
end process;
end generate;
comb : process (addr)
begin
case conv_integer(addr) is
when 16#00000# => romdata <= X"81D82000";
when 16#00001# => romdata <= X"03000004";
when 16#00002# => romdata <= X"821060C0";
when 16#00003# => romdata <= X"81884000";
when 16#00004# => romdata <= X"81900000";
when 16#00005# => romdata <= X"81980000";
when 16#00006# => romdata <= X"81800000";
when 16#00007# => romdata <= X"01000000";
when 16#00008# => romdata <= X"03000040";
when 16#00009# => romdata <= X"8210600F";
when 16#0000A# => romdata <= X"C2A00040";
when 16#0000B# => romdata <= X"87444000";
when 16#0000C# => romdata <= X"8608E01F";
when 16#0000D# => romdata <= X"88100000";
when 16#0000E# => romdata <= X"8A100000";
when 16#0000F# => romdata <= X"8C100000";
when 16#00010# => romdata <= X"8E100000";
when 16#00011# => romdata <= X"A0100000";
when 16#00012# => romdata <= X"A2100000";
when 16#00013# => romdata <= X"A4100000";
when 16#00014# => romdata <= X"A6100000";
when 16#00015# => romdata <= X"A8100000";
when 16#00016# => romdata <= X"AA100000";
when 16#00017# => romdata <= X"AC100000";
when 16#00018# => romdata <= X"AE100000";
when 16#00019# => romdata <= X"90100000";
when 16#0001A# => romdata <= X"92100000";
when 16#0001B# => romdata <= X"94100000";
when 16#0001C# => romdata <= X"96100000";
when 16#0001D# => romdata <= X"98100000";
when 16#0001E# => romdata <= X"9A100000";
when 16#0001F# => romdata <= X"9C100000";
when 16#00020# => romdata <= X"9E100000";
when 16#00021# => romdata <= X"86A0E001";
when 16#00022# => romdata <= X"16BFFFEF";
when 16#00023# => romdata <= X"81E00000";
when 16#00024# => romdata <= X"82102002";
when 16#00025# => romdata <= X"81904000";
when 16#00026# => romdata <= X"03000004";
when 16#00027# => romdata <= X"821060E0";
when 16#00028# => romdata <= X"81884000";
when 16#00029# => romdata <= X"01000000";
when 16#0002A# => romdata <= X"01000000";
when 16#0002B# => romdata <= X"01000000";
when 16#0002C# => romdata <= X"03200000";
when 16#0002D# => romdata <= X"84102233";
when 16#0002E# => romdata <= X"C4204000";
when 16#0002F# => romdata <= X"0539AE13";
when 16#00030# => romdata <= X"8410A260";
when 16#00031# => romdata <= X"C4206004";
when 16#00032# => romdata <= X"050003FC";
when 16#00033# => romdata <= X"C4206008";
when 16#00034# => romdata <= X"3D1003FF";
when 16#00035# => romdata <= X"BC17A3E0";
when 16#00036# => romdata <= X"9C27A060";
when 16#00037# => romdata <= X"03100000";
when 16#00038# => romdata <= X"81C04000";
when 16#00039# => romdata <= X"01000000";
when 16#0003A# => romdata <= X"01000000";
when 16#0003B# => romdata <= X"01000000";
when 16#0003C# => romdata <= X"01000000";
when 16#0003D# => romdata <= X"01000000";
when 16#0003E# => romdata <= X"01000000";
when 16#0003F# => romdata <= X"01000000";
when 16#00040# => romdata <= X"00000004";
when 16#00041# => romdata <= X"00000000";
when 16#00042# => romdata <= X"00000004";
when 16#00043# => romdata <= X"00000000";
when 16#00044# => romdata <= X"FFFFFFFC";
when 16#00045# => romdata <= X"00000000";
when 16#00046# => romdata <= X"FFFFFFFC";
when 16#00047# => romdata <= X"00000000";
when 16#00048# => romdata <= X"00000000";
when others => romdata <= (others => '-');
end case;
end process;
-- pragma translate_off
bootmsg : report_version
generic map ("ahbrom" & tost(hindex) &
": 32-bit AHB ROM Module, " & tost(bytes/4) & " words, " & tost(abits-2) & " address bits" );
-- pragma translate_on
end;
|
----------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2004 GAISLER RESEARCH
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- See the file COPYING for the full details of the license.
--
-----------------------------------------------------------------------------
-- Entity: ahbrom
-- File: ahbrom.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: AHB rom. 0/1-waitstate read
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
entity ahbrom is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#fff#;
pipe : integer := 0;
tech : integer := 0;
kbytes : integer := 1);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type
);
end;
architecture rtl of ahbrom is
constant abits : integer := 9;
constant bytes : integer := 288;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_AHBROM, 0, 0, 0),
4 => ahb_membar(haddr, '1', '1', hmask), others => zero32);
signal romdata : std_logic_vector(31 downto 0);
signal addr : std_logic_vector(abits-1 downto 2);
signal hsel, hready : std_ulogic;
begin
ahbso.hresp <= "00";
ahbso.hsplit <= (others => '0');
ahbso.hirq <= (others => '0');
ahbso.hconfig <= hconfig;
ahbso.hindex <= hindex;
reg : process (clk)
begin
if rising_edge(clk) then
addr <= ahbsi.haddr(abits-1 downto 2);
end if;
end process;
p0 : if pipe = 0 generate
ahbso.hrdata <= ahbdrivedata(romdata);
ahbso.hready <= '1';
end generate;
p1 : if pipe = 1 generate
reg2 : process (clk)
begin
if rising_edge(clk) then
hsel <= ahbsi.hsel(hindex) and ahbsi.htrans(1);
hready <= ahbsi.hready;
ahbso.hready <= (not rst) or (hsel and hready) or
(ahbsi.hsel(hindex) and not ahbsi.htrans(1) and ahbsi.hready);
ahbso.hrdata <= ahbdrivedata(romdata);
end if;
end process;
end generate;
comb : process (addr)
begin
case conv_integer(addr) is
when 16#00000# => romdata <= X"81D82000";
when 16#00001# => romdata <= X"03000004";
when 16#00002# => romdata <= X"821060C0";
when 16#00003# => romdata <= X"81884000";
when 16#00004# => romdata <= X"81900000";
when 16#00005# => romdata <= X"81980000";
when 16#00006# => romdata <= X"81800000";
when 16#00007# => romdata <= X"01000000";
when 16#00008# => romdata <= X"03000040";
when 16#00009# => romdata <= X"8210600F";
when 16#0000A# => romdata <= X"C2A00040";
when 16#0000B# => romdata <= X"87444000";
when 16#0000C# => romdata <= X"8608E01F";
when 16#0000D# => romdata <= X"88100000";
when 16#0000E# => romdata <= X"8A100000";
when 16#0000F# => romdata <= X"8C100000";
when 16#00010# => romdata <= X"8E100000";
when 16#00011# => romdata <= X"A0100000";
when 16#00012# => romdata <= X"A2100000";
when 16#00013# => romdata <= X"A4100000";
when 16#00014# => romdata <= X"A6100000";
when 16#00015# => romdata <= X"A8100000";
when 16#00016# => romdata <= X"AA100000";
when 16#00017# => romdata <= X"AC100000";
when 16#00018# => romdata <= X"AE100000";
when 16#00019# => romdata <= X"90100000";
when 16#0001A# => romdata <= X"92100000";
when 16#0001B# => romdata <= X"94100000";
when 16#0001C# => romdata <= X"96100000";
when 16#0001D# => romdata <= X"98100000";
when 16#0001E# => romdata <= X"9A100000";
when 16#0001F# => romdata <= X"9C100000";
when 16#00020# => romdata <= X"9E100000";
when 16#00021# => romdata <= X"86A0E001";
when 16#00022# => romdata <= X"16BFFFEF";
when 16#00023# => romdata <= X"81E00000";
when 16#00024# => romdata <= X"82102002";
when 16#00025# => romdata <= X"81904000";
when 16#00026# => romdata <= X"03000004";
when 16#00027# => romdata <= X"821060E0";
when 16#00028# => romdata <= X"81884000";
when 16#00029# => romdata <= X"01000000";
when 16#0002A# => romdata <= X"01000000";
when 16#0002B# => romdata <= X"01000000";
when 16#0002C# => romdata <= X"03200000";
when 16#0002D# => romdata <= X"84102233";
when 16#0002E# => romdata <= X"C4204000";
when 16#0002F# => romdata <= X"0539AE13";
when 16#00030# => romdata <= X"8410A260";
when 16#00031# => romdata <= X"C4206004";
when 16#00032# => romdata <= X"050003FC";
when 16#00033# => romdata <= X"C4206008";
when 16#00034# => romdata <= X"3D1003FF";
when 16#00035# => romdata <= X"BC17A3E0";
when 16#00036# => romdata <= X"9C27A060";
when 16#00037# => romdata <= X"03100000";
when 16#00038# => romdata <= X"81C04000";
when 16#00039# => romdata <= X"01000000";
when 16#0003A# => romdata <= X"01000000";
when 16#0003B# => romdata <= X"01000000";
when 16#0003C# => romdata <= X"01000000";
when 16#0003D# => romdata <= X"01000000";
when 16#0003E# => romdata <= X"01000000";
when 16#0003F# => romdata <= X"01000000";
when 16#00040# => romdata <= X"00000004";
when 16#00041# => romdata <= X"00000000";
when 16#00042# => romdata <= X"00000004";
when 16#00043# => romdata <= X"00000000";
when 16#00044# => romdata <= X"FFFFFFFC";
when 16#00045# => romdata <= X"00000000";
when 16#00046# => romdata <= X"FFFFFFFC";
when 16#00047# => romdata <= X"00000000";
when 16#00048# => romdata <= X"00000000";
when others => romdata <= (others => '-');
end case;
end process;
-- pragma translate_off
bootmsg : report_version
generic map ("ahbrom" & tost(hindex) &
": 32-bit AHB ROM Module, " & tost(bytes/4) & " words, " & tost(abits-2) & " address bits" );
-- pragma translate_on
end;
|
----------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2004 GAISLER RESEARCH
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- See the file COPYING for the full details of the license.
--
-----------------------------------------------------------------------------
-- Entity: ahbrom
-- File: ahbrom.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: AHB rom. 0/1-waitstate read
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
entity ahbrom is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#fff#;
pipe : integer := 0;
tech : integer := 0;
kbytes : integer := 1);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type
);
end;
architecture rtl of ahbrom is
constant abits : integer := 9;
constant bytes : integer := 288;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_AHBROM, 0, 0, 0),
4 => ahb_membar(haddr, '1', '1', hmask), others => zero32);
signal romdata : std_logic_vector(31 downto 0);
signal addr : std_logic_vector(abits-1 downto 2);
signal hsel, hready : std_ulogic;
begin
ahbso.hresp <= "00";
ahbso.hsplit <= (others => '0');
ahbso.hirq <= (others => '0');
ahbso.hconfig <= hconfig;
ahbso.hindex <= hindex;
reg : process (clk)
begin
if rising_edge(clk) then
addr <= ahbsi.haddr(abits-1 downto 2);
end if;
end process;
p0 : if pipe = 0 generate
ahbso.hrdata <= ahbdrivedata(romdata);
ahbso.hready <= '1';
end generate;
p1 : if pipe = 1 generate
reg2 : process (clk)
begin
if rising_edge(clk) then
hsel <= ahbsi.hsel(hindex) and ahbsi.htrans(1);
hready <= ahbsi.hready;
ahbso.hready <= (not rst) or (hsel and hready) or
(ahbsi.hsel(hindex) and not ahbsi.htrans(1) and ahbsi.hready);
ahbso.hrdata <= ahbdrivedata(romdata);
end if;
end process;
end generate;
comb : process (addr)
begin
case conv_integer(addr) is
when 16#00000# => romdata <= X"81D82000";
when 16#00001# => romdata <= X"03000004";
when 16#00002# => romdata <= X"821060C0";
when 16#00003# => romdata <= X"81884000";
when 16#00004# => romdata <= X"81900000";
when 16#00005# => romdata <= X"81980000";
when 16#00006# => romdata <= X"81800000";
when 16#00007# => romdata <= X"01000000";
when 16#00008# => romdata <= X"03000040";
when 16#00009# => romdata <= X"8210600F";
when 16#0000A# => romdata <= X"C2A00040";
when 16#0000B# => romdata <= X"87444000";
when 16#0000C# => romdata <= X"8608E01F";
when 16#0000D# => romdata <= X"88100000";
when 16#0000E# => romdata <= X"8A100000";
when 16#0000F# => romdata <= X"8C100000";
when 16#00010# => romdata <= X"8E100000";
when 16#00011# => romdata <= X"A0100000";
when 16#00012# => romdata <= X"A2100000";
when 16#00013# => romdata <= X"A4100000";
when 16#00014# => romdata <= X"A6100000";
when 16#00015# => romdata <= X"A8100000";
when 16#00016# => romdata <= X"AA100000";
when 16#00017# => romdata <= X"AC100000";
when 16#00018# => romdata <= X"AE100000";
when 16#00019# => romdata <= X"90100000";
when 16#0001A# => romdata <= X"92100000";
when 16#0001B# => romdata <= X"94100000";
when 16#0001C# => romdata <= X"96100000";
when 16#0001D# => romdata <= X"98100000";
when 16#0001E# => romdata <= X"9A100000";
when 16#0001F# => romdata <= X"9C100000";
when 16#00020# => romdata <= X"9E100000";
when 16#00021# => romdata <= X"86A0E001";
when 16#00022# => romdata <= X"16BFFFEF";
when 16#00023# => romdata <= X"81E00000";
when 16#00024# => romdata <= X"82102002";
when 16#00025# => romdata <= X"81904000";
when 16#00026# => romdata <= X"03000004";
when 16#00027# => romdata <= X"821060E0";
when 16#00028# => romdata <= X"81884000";
when 16#00029# => romdata <= X"01000000";
when 16#0002A# => romdata <= X"01000000";
when 16#0002B# => romdata <= X"01000000";
when 16#0002C# => romdata <= X"03200000";
when 16#0002D# => romdata <= X"84102233";
when 16#0002E# => romdata <= X"C4204000";
when 16#0002F# => romdata <= X"0539AE13";
when 16#00030# => romdata <= X"8410A260";
when 16#00031# => romdata <= X"C4206004";
when 16#00032# => romdata <= X"050003FC";
when 16#00033# => romdata <= X"C4206008";
when 16#00034# => romdata <= X"3D1003FF";
when 16#00035# => romdata <= X"BC17A3E0";
when 16#00036# => romdata <= X"9C27A060";
when 16#00037# => romdata <= X"03100000";
when 16#00038# => romdata <= X"81C04000";
when 16#00039# => romdata <= X"01000000";
when 16#0003A# => romdata <= X"01000000";
when 16#0003B# => romdata <= X"01000000";
when 16#0003C# => romdata <= X"01000000";
when 16#0003D# => romdata <= X"01000000";
when 16#0003E# => romdata <= X"01000000";
when 16#0003F# => romdata <= X"01000000";
when 16#00040# => romdata <= X"00000004";
when 16#00041# => romdata <= X"00000000";
when 16#00042# => romdata <= X"00000004";
when 16#00043# => romdata <= X"00000000";
when 16#00044# => romdata <= X"FFFFFFFC";
when 16#00045# => romdata <= X"00000000";
when 16#00046# => romdata <= X"FFFFFFFC";
when 16#00047# => romdata <= X"00000000";
when 16#00048# => romdata <= X"00000000";
when others => romdata <= (others => '-');
end case;
end process;
-- pragma translate_off
bootmsg : report_version
generic map ("ahbrom" & tost(hindex) &
": 32-bit AHB ROM Module, " & tost(bytes/4) & " words, " & tost(abits-2) & " address bits" );
-- pragma translate_on
end;
|
----------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2004 GAISLER RESEARCH
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- See the file COPYING for the full details of the license.
--
-----------------------------------------------------------------------------
-- Entity: ahbrom
-- File: ahbrom.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: AHB rom. 0/1-waitstate read
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
entity ahbrom is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#fff#;
pipe : integer := 0;
tech : integer := 0;
kbytes : integer := 1);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type
);
end;
architecture rtl of ahbrom is
constant abits : integer := 9;
constant bytes : integer := 288;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_AHBROM, 0, 0, 0),
4 => ahb_membar(haddr, '1', '1', hmask), others => zero32);
signal romdata : std_logic_vector(31 downto 0);
signal addr : std_logic_vector(abits-1 downto 2);
signal hsel, hready : std_ulogic;
begin
ahbso.hresp <= "00";
ahbso.hsplit <= (others => '0');
ahbso.hirq <= (others => '0');
ahbso.hconfig <= hconfig;
ahbso.hindex <= hindex;
reg : process (clk)
begin
if rising_edge(clk) then
addr <= ahbsi.haddr(abits-1 downto 2);
end if;
end process;
p0 : if pipe = 0 generate
ahbso.hrdata <= ahbdrivedata(romdata);
ahbso.hready <= '1';
end generate;
p1 : if pipe = 1 generate
reg2 : process (clk)
begin
if rising_edge(clk) then
hsel <= ahbsi.hsel(hindex) and ahbsi.htrans(1);
hready <= ahbsi.hready;
ahbso.hready <= (not rst) or (hsel and hready) or
(ahbsi.hsel(hindex) and not ahbsi.htrans(1) and ahbsi.hready);
ahbso.hrdata <= ahbdrivedata(romdata);
end if;
end process;
end generate;
comb : process (addr)
begin
case conv_integer(addr) is
when 16#00000# => romdata <= X"81D82000";
when 16#00001# => romdata <= X"03000004";
when 16#00002# => romdata <= X"821060C0";
when 16#00003# => romdata <= X"81884000";
when 16#00004# => romdata <= X"81900000";
when 16#00005# => romdata <= X"81980000";
when 16#00006# => romdata <= X"81800000";
when 16#00007# => romdata <= X"01000000";
when 16#00008# => romdata <= X"03000040";
when 16#00009# => romdata <= X"8210600F";
when 16#0000A# => romdata <= X"C2A00040";
when 16#0000B# => romdata <= X"87444000";
when 16#0000C# => romdata <= X"8608E01F";
when 16#0000D# => romdata <= X"88100000";
when 16#0000E# => romdata <= X"8A100000";
when 16#0000F# => romdata <= X"8C100000";
when 16#00010# => romdata <= X"8E100000";
when 16#00011# => romdata <= X"A0100000";
when 16#00012# => romdata <= X"A2100000";
when 16#00013# => romdata <= X"A4100000";
when 16#00014# => romdata <= X"A6100000";
when 16#00015# => romdata <= X"A8100000";
when 16#00016# => romdata <= X"AA100000";
when 16#00017# => romdata <= X"AC100000";
when 16#00018# => romdata <= X"AE100000";
when 16#00019# => romdata <= X"90100000";
when 16#0001A# => romdata <= X"92100000";
when 16#0001B# => romdata <= X"94100000";
when 16#0001C# => romdata <= X"96100000";
when 16#0001D# => romdata <= X"98100000";
when 16#0001E# => romdata <= X"9A100000";
when 16#0001F# => romdata <= X"9C100000";
when 16#00020# => romdata <= X"9E100000";
when 16#00021# => romdata <= X"86A0E001";
when 16#00022# => romdata <= X"16BFFFEF";
when 16#00023# => romdata <= X"81E00000";
when 16#00024# => romdata <= X"82102002";
when 16#00025# => romdata <= X"81904000";
when 16#00026# => romdata <= X"03000004";
when 16#00027# => romdata <= X"821060E0";
when 16#00028# => romdata <= X"81884000";
when 16#00029# => romdata <= X"01000000";
when 16#0002A# => romdata <= X"01000000";
when 16#0002B# => romdata <= X"01000000";
when 16#0002C# => romdata <= X"03200000";
when 16#0002D# => romdata <= X"84102233";
when 16#0002E# => romdata <= X"C4204000";
when 16#0002F# => romdata <= X"0539AE13";
when 16#00030# => romdata <= X"8410A260";
when 16#00031# => romdata <= X"C4206004";
when 16#00032# => romdata <= X"050003FC";
when 16#00033# => romdata <= X"C4206008";
when 16#00034# => romdata <= X"3D1003FF";
when 16#00035# => romdata <= X"BC17A3E0";
when 16#00036# => romdata <= X"9C27A060";
when 16#00037# => romdata <= X"03100000";
when 16#00038# => romdata <= X"81C04000";
when 16#00039# => romdata <= X"01000000";
when 16#0003A# => romdata <= X"01000000";
when 16#0003B# => romdata <= X"01000000";
when 16#0003C# => romdata <= X"01000000";
when 16#0003D# => romdata <= X"01000000";
when 16#0003E# => romdata <= X"01000000";
when 16#0003F# => romdata <= X"01000000";
when 16#00040# => romdata <= X"00000004";
when 16#00041# => romdata <= X"00000000";
when 16#00042# => romdata <= X"00000004";
when 16#00043# => romdata <= X"00000000";
when 16#00044# => romdata <= X"FFFFFFFC";
when 16#00045# => romdata <= X"00000000";
when 16#00046# => romdata <= X"FFFFFFFC";
when 16#00047# => romdata <= X"00000000";
when 16#00048# => romdata <= X"00000000";
when others => romdata <= (others => '-');
end case;
end process;
-- pragma translate_off
bootmsg : report_version
generic map ("ahbrom" & tost(hindex) &
": 32-bit AHB ROM Module, " & tost(bytes/4) & " words, " & tost(abits-2) & " address bits" );
-- pragma translate_on
end;
|
----------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2004 GAISLER RESEARCH
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- See the file COPYING for the full details of the license.
--
-----------------------------------------------------------------------------
-- Entity: ahbrom
-- File: ahbrom.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: AHB rom. 0/1-waitstate read
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
entity ahbrom is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#fff#;
pipe : integer := 0;
tech : integer := 0;
kbytes : integer := 1);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type
);
end;
architecture rtl of ahbrom is
constant abits : integer := 9;
constant bytes : integer := 288;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_AHBROM, 0, 0, 0),
4 => ahb_membar(haddr, '1', '1', hmask), others => zero32);
signal romdata : std_logic_vector(31 downto 0);
signal addr : std_logic_vector(abits-1 downto 2);
signal hsel, hready : std_ulogic;
begin
ahbso.hresp <= "00";
ahbso.hsplit <= (others => '0');
ahbso.hirq <= (others => '0');
ahbso.hconfig <= hconfig;
ahbso.hindex <= hindex;
reg : process (clk)
begin
if rising_edge(clk) then
addr <= ahbsi.haddr(abits-1 downto 2);
end if;
end process;
p0 : if pipe = 0 generate
ahbso.hrdata <= ahbdrivedata(romdata);
ahbso.hready <= '1';
end generate;
p1 : if pipe = 1 generate
reg2 : process (clk)
begin
if rising_edge(clk) then
hsel <= ahbsi.hsel(hindex) and ahbsi.htrans(1);
hready <= ahbsi.hready;
ahbso.hready <= (not rst) or (hsel and hready) or
(ahbsi.hsel(hindex) and not ahbsi.htrans(1) and ahbsi.hready);
ahbso.hrdata <= ahbdrivedata(romdata);
end if;
end process;
end generate;
comb : process (addr)
begin
case conv_integer(addr) is
when 16#00000# => romdata <= X"81D82000";
when 16#00001# => romdata <= X"03000004";
when 16#00002# => romdata <= X"821060C0";
when 16#00003# => romdata <= X"81884000";
when 16#00004# => romdata <= X"81900000";
when 16#00005# => romdata <= X"81980000";
when 16#00006# => romdata <= X"81800000";
when 16#00007# => romdata <= X"01000000";
when 16#00008# => romdata <= X"03000040";
when 16#00009# => romdata <= X"8210600F";
when 16#0000A# => romdata <= X"C2A00040";
when 16#0000B# => romdata <= X"87444000";
when 16#0000C# => romdata <= X"8608E01F";
when 16#0000D# => romdata <= X"88100000";
when 16#0000E# => romdata <= X"8A100000";
when 16#0000F# => romdata <= X"8C100000";
when 16#00010# => romdata <= X"8E100000";
when 16#00011# => romdata <= X"A0100000";
when 16#00012# => romdata <= X"A2100000";
when 16#00013# => romdata <= X"A4100000";
when 16#00014# => romdata <= X"A6100000";
when 16#00015# => romdata <= X"A8100000";
when 16#00016# => romdata <= X"AA100000";
when 16#00017# => romdata <= X"AC100000";
when 16#00018# => romdata <= X"AE100000";
when 16#00019# => romdata <= X"90100000";
when 16#0001A# => romdata <= X"92100000";
when 16#0001B# => romdata <= X"94100000";
when 16#0001C# => romdata <= X"96100000";
when 16#0001D# => romdata <= X"98100000";
when 16#0001E# => romdata <= X"9A100000";
when 16#0001F# => romdata <= X"9C100000";
when 16#00020# => romdata <= X"9E100000";
when 16#00021# => romdata <= X"86A0E001";
when 16#00022# => romdata <= X"16BFFFEF";
when 16#00023# => romdata <= X"81E00000";
when 16#00024# => romdata <= X"82102002";
when 16#00025# => romdata <= X"81904000";
when 16#00026# => romdata <= X"03000004";
when 16#00027# => romdata <= X"821060E0";
when 16#00028# => romdata <= X"81884000";
when 16#00029# => romdata <= X"01000000";
when 16#0002A# => romdata <= X"01000000";
when 16#0002B# => romdata <= X"01000000";
when 16#0002C# => romdata <= X"03200000";
when 16#0002D# => romdata <= X"84102233";
when 16#0002E# => romdata <= X"C4204000";
when 16#0002F# => romdata <= X"0539AE13";
when 16#00030# => romdata <= X"8410A260";
when 16#00031# => romdata <= X"C4206004";
when 16#00032# => romdata <= X"050003FC";
when 16#00033# => romdata <= X"C4206008";
when 16#00034# => romdata <= X"3D1003FF";
when 16#00035# => romdata <= X"BC17A3E0";
when 16#00036# => romdata <= X"9C27A060";
when 16#00037# => romdata <= X"03100000";
when 16#00038# => romdata <= X"81C04000";
when 16#00039# => romdata <= X"01000000";
when 16#0003A# => romdata <= X"01000000";
when 16#0003B# => romdata <= X"01000000";
when 16#0003C# => romdata <= X"01000000";
when 16#0003D# => romdata <= X"01000000";
when 16#0003E# => romdata <= X"01000000";
when 16#0003F# => romdata <= X"01000000";
when 16#00040# => romdata <= X"00000004";
when 16#00041# => romdata <= X"00000000";
when 16#00042# => romdata <= X"00000004";
when 16#00043# => romdata <= X"00000000";
when 16#00044# => romdata <= X"FFFFFFFC";
when 16#00045# => romdata <= X"00000000";
when 16#00046# => romdata <= X"FFFFFFFC";
when 16#00047# => romdata <= X"00000000";
when 16#00048# => romdata <= X"00000000";
when others => romdata <= (others => '-');
end case;
end process;
-- pragma translate_off
bootmsg : report_version
generic map ("ahbrom" & tost(hindex) &
": 32-bit AHB ROM Module, " & tost(bytes/4) & " words, " & tost(abits-2) & " address bits" );
-- pragma translate_on
end;
|
----------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2004 GAISLER RESEARCH
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- See the file COPYING for the full details of the license.
--
-----------------------------------------------------------------------------
-- Entity: ahbrom
-- File: ahbrom.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: AHB rom. 0/1-waitstate read
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
entity ahbrom is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#fff#;
pipe : integer := 0;
tech : integer := 0;
kbytes : integer := 1);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type
);
end;
architecture rtl of ahbrom is
constant abits : integer := 9;
constant bytes : integer := 288;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_AHBROM, 0, 0, 0),
4 => ahb_membar(haddr, '1', '1', hmask), others => zero32);
signal romdata : std_logic_vector(31 downto 0);
signal addr : std_logic_vector(abits-1 downto 2);
signal hsel, hready : std_ulogic;
begin
ahbso.hresp <= "00";
ahbso.hsplit <= (others => '0');
ahbso.hirq <= (others => '0');
ahbso.hconfig <= hconfig;
ahbso.hindex <= hindex;
reg : process (clk)
begin
if rising_edge(clk) then
addr <= ahbsi.haddr(abits-1 downto 2);
end if;
end process;
p0 : if pipe = 0 generate
ahbso.hrdata <= ahbdrivedata(romdata);
ahbso.hready <= '1';
end generate;
p1 : if pipe = 1 generate
reg2 : process (clk)
begin
if rising_edge(clk) then
hsel <= ahbsi.hsel(hindex) and ahbsi.htrans(1);
hready <= ahbsi.hready;
ahbso.hready <= (not rst) or (hsel and hready) or
(ahbsi.hsel(hindex) and not ahbsi.htrans(1) and ahbsi.hready);
ahbso.hrdata <= ahbdrivedata(romdata);
end if;
end process;
end generate;
comb : process (addr)
begin
case conv_integer(addr) is
when 16#00000# => romdata <= X"81D82000";
when 16#00001# => romdata <= X"03000004";
when 16#00002# => romdata <= X"821060C0";
when 16#00003# => romdata <= X"81884000";
when 16#00004# => romdata <= X"81900000";
when 16#00005# => romdata <= X"81980000";
when 16#00006# => romdata <= X"81800000";
when 16#00007# => romdata <= X"01000000";
when 16#00008# => romdata <= X"03000040";
when 16#00009# => romdata <= X"8210600F";
when 16#0000A# => romdata <= X"C2A00040";
when 16#0000B# => romdata <= X"87444000";
when 16#0000C# => romdata <= X"8608E01F";
when 16#0000D# => romdata <= X"88100000";
when 16#0000E# => romdata <= X"8A100000";
when 16#0000F# => romdata <= X"8C100000";
when 16#00010# => romdata <= X"8E100000";
when 16#00011# => romdata <= X"A0100000";
when 16#00012# => romdata <= X"A2100000";
when 16#00013# => romdata <= X"A4100000";
when 16#00014# => romdata <= X"A6100000";
when 16#00015# => romdata <= X"A8100000";
when 16#00016# => romdata <= X"AA100000";
when 16#00017# => romdata <= X"AC100000";
when 16#00018# => romdata <= X"AE100000";
when 16#00019# => romdata <= X"90100000";
when 16#0001A# => romdata <= X"92100000";
when 16#0001B# => romdata <= X"94100000";
when 16#0001C# => romdata <= X"96100000";
when 16#0001D# => romdata <= X"98100000";
when 16#0001E# => romdata <= X"9A100000";
when 16#0001F# => romdata <= X"9C100000";
when 16#00020# => romdata <= X"9E100000";
when 16#00021# => romdata <= X"86A0E001";
when 16#00022# => romdata <= X"16BFFFEF";
when 16#00023# => romdata <= X"81E00000";
when 16#00024# => romdata <= X"82102002";
when 16#00025# => romdata <= X"81904000";
when 16#00026# => romdata <= X"03000004";
when 16#00027# => romdata <= X"821060E0";
when 16#00028# => romdata <= X"81884000";
when 16#00029# => romdata <= X"01000000";
when 16#0002A# => romdata <= X"01000000";
when 16#0002B# => romdata <= X"01000000";
when 16#0002C# => romdata <= X"03200000";
when 16#0002D# => romdata <= X"84102233";
when 16#0002E# => romdata <= X"C4204000";
when 16#0002F# => romdata <= X"0539AE13";
when 16#00030# => romdata <= X"8410A260";
when 16#00031# => romdata <= X"C4206004";
when 16#00032# => romdata <= X"050003FC";
when 16#00033# => romdata <= X"C4206008";
when 16#00034# => romdata <= X"3D1003FF";
when 16#00035# => romdata <= X"BC17A3E0";
when 16#00036# => romdata <= X"9C27A060";
when 16#00037# => romdata <= X"03100000";
when 16#00038# => romdata <= X"81C04000";
when 16#00039# => romdata <= X"01000000";
when 16#0003A# => romdata <= X"01000000";
when 16#0003B# => romdata <= X"01000000";
when 16#0003C# => romdata <= X"01000000";
when 16#0003D# => romdata <= X"01000000";
when 16#0003E# => romdata <= X"01000000";
when 16#0003F# => romdata <= X"01000000";
when 16#00040# => romdata <= X"00000004";
when 16#00041# => romdata <= X"00000000";
when 16#00042# => romdata <= X"00000004";
when 16#00043# => romdata <= X"00000000";
when 16#00044# => romdata <= X"FFFFFFFC";
when 16#00045# => romdata <= X"00000000";
when 16#00046# => romdata <= X"FFFFFFFC";
when 16#00047# => romdata <= X"00000000";
when 16#00048# => romdata <= X"00000000";
when others => romdata <= (others => '-');
end case;
end process;
-- pragma translate_off
bootmsg : report_version
generic map ("ahbrom" & tost(hindex) &
": 32-bit AHB ROM Module, " & tost(bytes/4) & " words, " & tost(abits-2) & " address bits" );
-- pragma translate_on
end;
|
----------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2004 GAISLER RESEARCH
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- See the file COPYING for the full details of the license.
--
-----------------------------------------------------------------------------
-- Entity: ahbrom
-- File: ahbrom.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: AHB rom. 0/1-waitstate read
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
entity ahbrom is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#fff#;
pipe : integer := 0;
tech : integer := 0;
kbytes : integer := 1);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type
);
end;
architecture rtl of ahbrom is
constant abits : integer := 9;
constant bytes : integer := 288;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_AHBROM, 0, 0, 0),
4 => ahb_membar(haddr, '1', '1', hmask), others => zero32);
signal romdata : std_logic_vector(31 downto 0);
signal addr : std_logic_vector(abits-1 downto 2);
signal hsel, hready : std_ulogic;
begin
ahbso.hresp <= "00";
ahbso.hsplit <= (others => '0');
ahbso.hirq <= (others => '0');
ahbso.hconfig <= hconfig;
ahbso.hindex <= hindex;
reg : process (clk)
begin
if rising_edge(clk) then
addr <= ahbsi.haddr(abits-1 downto 2);
end if;
end process;
p0 : if pipe = 0 generate
ahbso.hrdata <= ahbdrivedata(romdata);
ahbso.hready <= '1';
end generate;
p1 : if pipe = 1 generate
reg2 : process (clk)
begin
if rising_edge(clk) then
hsel <= ahbsi.hsel(hindex) and ahbsi.htrans(1);
hready <= ahbsi.hready;
ahbso.hready <= (not rst) or (hsel and hready) or
(ahbsi.hsel(hindex) and not ahbsi.htrans(1) and ahbsi.hready);
ahbso.hrdata <= ahbdrivedata(romdata);
end if;
end process;
end generate;
comb : process (addr)
begin
case conv_integer(addr) is
when 16#00000# => romdata <= X"81D82000";
when 16#00001# => romdata <= X"03000004";
when 16#00002# => romdata <= X"821060C0";
when 16#00003# => romdata <= X"81884000";
when 16#00004# => romdata <= X"81900000";
when 16#00005# => romdata <= X"81980000";
when 16#00006# => romdata <= X"81800000";
when 16#00007# => romdata <= X"01000000";
when 16#00008# => romdata <= X"03000040";
when 16#00009# => romdata <= X"8210600F";
when 16#0000A# => romdata <= X"C2A00040";
when 16#0000B# => romdata <= X"87444000";
when 16#0000C# => romdata <= X"8608E01F";
when 16#0000D# => romdata <= X"88100000";
when 16#0000E# => romdata <= X"8A100000";
when 16#0000F# => romdata <= X"8C100000";
when 16#00010# => romdata <= X"8E100000";
when 16#00011# => romdata <= X"A0100000";
when 16#00012# => romdata <= X"A2100000";
when 16#00013# => romdata <= X"A4100000";
when 16#00014# => romdata <= X"A6100000";
when 16#00015# => romdata <= X"A8100000";
when 16#00016# => romdata <= X"AA100000";
when 16#00017# => romdata <= X"AC100000";
when 16#00018# => romdata <= X"AE100000";
when 16#00019# => romdata <= X"90100000";
when 16#0001A# => romdata <= X"92100000";
when 16#0001B# => romdata <= X"94100000";
when 16#0001C# => romdata <= X"96100000";
when 16#0001D# => romdata <= X"98100000";
when 16#0001E# => romdata <= X"9A100000";
when 16#0001F# => romdata <= X"9C100000";
when 16#00020# => romdata <= X"9E100000";
when 16#00021# => romdata <= X"86A0E001";
when 16#00022# => romdata <= X"16BFFFEF";
when 16#00023# => romdata <= X"81E00000";
when 16#00024# => romdata <= X"82102002";
when 16#00025# => romdata <= X"81904000";
when 16#00026# => romdata <= X"03000004";
when 16#00027# => romdata <= X"821060E0";
when 16#00028# => romdata <= X"81884000";
when 16#00029# => romdata <= X"01000000";
when 16#0002A# => romdata <= X"01000000";
when 16#0002B# => romdata <= X"01000000";
when 16#0002C# => romdata <= X"03200000";
when 16#0002D# => romdata <= X"84102233";
when 16#0002E# => romdata <= X"C4204000";
when 16#0002F# => romdata <= X"0539AE13";
when 16#00030# => romdata <= X"8410A260";
when 16#00031# => romdata <= X"C4206004";
when 16#00032# => romdata <= X"050003FC";
when 16#00033# => romdata <= X"C4206008";
when 16#00034# => romdata <= X"3D1003FF";
when 16#00035# => romdata <= X"BC17A3E0";
when 16#00036# => romdata <= X"9C27A060";
when 16#00037# => romdata <= X"03100000";
when 16#00038# => romdata <= X"81C04000";
when 16#00039# => romdata <= X"01000000";
when 16#0003A# => romdata <= X"01000000";
when 16#0003B# => romdata <= X"01000000";
when 16#0003C# => romdata <= X"01000000";
when 16#0003D# => romdata <= X"01000000";
when 16#0003E# => romdata <= X"01000000";
when 16#0003F# => romdata <= X"01000000";
when 16#00040# => romdata <= X"00000004";
when 16#00041# => romdata <= X"00000000";
when 16#00042# => romdata <= X"00000004";
when 16#00043# => romdata <= X"00000000";
when 16#00044# => romdata <= X"FFFFFFFC";
when 16#00045# => romdata <= X"00000000";
when 16#00046# => romdata <= X"FFFFFFFC";
when 16#00047# => romdata <= X"00000000";
when 16#00048# => romdata <= X"00000000";
when others => romdata <= (others => '-');
end case;
end process;
-- pragma translate_off
bootmsg : report_version
generic map ("ahbrom" & tost(hindex) &
": 32-bit AHB ROM Module, " & tost(bytes/4) & " words, " & tost(abits-2) & " address bits" );
-- pragma translate_on
end;
|
----------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2004 GAISLER RESEARCH
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- See the file COPYING for the full details of the license.
--
-----------------------------------------------------------------------------
-- Entity: ahbrom
-- File: ahbrom.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: AHB rom. 0/1-waitstate read
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
entity ahbrom is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#fff#;
pipe : integer := 0;
tech : integer := 0;
kbytes : integer := 1);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type
);
end;
architecture rtl of ahbrom is
constant abits : integer := 9;
constant bytes : integer := 288;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_AHBROM, 0, 0, 0),
4 => ahb_membar(haddr, '1', '1', hmask), others => zero32);
signal romdata : std_logic_vector(31 downto 0);
signal addr : std_logic_vector(abits-1 downto 2);
signal hsel, hready : std_ulogic;
begin
ahbso.hresp <= "00";
ahbso.hsplit <= (others => '0');
ahbso.hirq <= (others => '0');
ahbso.hconfig <= hconfig;
ahbso.hindex <= hindex;
reg : process (clk)
begin
if rising_edge(clk) then
addr <= ahbsi.haddr(abits-1 downto 2);
end if;
end process;
p0 : if pipe = 0 generate
ahbso.hrdata <= ahbdrivedata(romdata);
ahbso.hready <= '1';
end generate;
p1 : if pipe = 1 generate
reg2 : process (clk)
begin
if rising_edge(clk) then
hsel <= ahbsi.hsel(hindex) and ahbsi.htrans(1);
hready <= ahbsi.hready;
ahbso.hready <= (not rst) or (hsel and hready) or
(ahbsi.hsel(hindex) and not ahbsi.htrans(1) and ahbsi.hready);
ahbso.hrdata <= ahbdrivedata(romdata);
end if;
end process;
end generate;
comb : process (addr)
begin
case conv_integer(addr) is
when 16#00000# => romdata <= X"81D82000";
when 16#00001# => romdata <= X"03000004";
when 16#00002# => romdata <= X"821060C0";
when 16#00003# => romdata <= X"81884000";
when 16#00004# => romdata <= X"81900000";
when 16#00005# => romdata <= X"81980000";
when 16#00006# => romdata <= X"81800000";
when 16#00007# => romdata <= X"01000000";
when 16#00008# => romdata <= X"03000040";
when 16#00009# => romdata <= X"8210600F";
when 16#0000A# => romdata <= X"C2A00040";
when 16#0000B# => romdata <= X"87444000";
when 16#0000C# => romdata <= X"8608E01F";
when 16#0000D# => romdata <= X"88100000";
when 16#0000E# => romdata <= X"8A100000";
when 16#0000F# => romdata <= X"8C100000";
when 16#00010# => romdata <= X"8E100000";
when 16#00011# => romdata <= X"A0100000";
when 16#00012# => romdata <= X"A2100000";
when 16#00013# => romdata <= X"A4100000";
when 16#00014# => romdata <= X"A6100000";
when 16#00015# => romdata <= X"A8100000";
when 16#00016# => romdata <= X"AA100000";
when 16#00017# => romdata <= X"AC100000";
when 16#00018# => romdata <= X"AE100000";
when 16#00019# => romdata <= X"90100000";
when 16#0001A# => romdata <= X"92100000";
when 16#0001B# => romdata <= X"94100000";
when 16#0001C# => romdata <= X"96100000";
when 16#0001D# => romdata <= X"98100000";
when 16#0001E# => romdata <= X"9A100000";
when 16#0001F# => romdata <= X"9C100000";
when 16#00020# => romdata <= X"9E100000";
when 16#00021# => romdata <= X"86A0E001";
when 16#00022# => romdata <= X"16BFFFEF";
when 16#00023# => romdata <= X"81E00000";
when 16#00024# => romdata <= X"82102002";
when 16#00025# => romdata <= X"81904000";
when 16#00026# => romdata <= X"03000004";
when 16#00027# => romdata <= X"821060E0";
when 16#00028# => romdata <= X"81884000";
when 16#00029# => romdata <= X"01000000";
when 16#0002A# => romdata <= X"01000000";
when 16#0002B# => romdata <= X"01000000";
when 16#0002C# => romdata <= X"03200000";
when 16#0002D# => romdata <= X"84102233";
when 16#0002E# => romdata <= X"C4204000";
when 16#0002F# => romdata <= X"0539AE13";
when 16#00030# => romdata <= X"8410A260";
when 16#00031# => romdata <= X"C4206004";
when 16#00032# => romdata <= X"050003FC";
when 16#00033# => romdata <= X"C4206008";
when 16#00034# => romdata <= X"3D1003FF";
when 16#00035# => romdata <= X"BC17A3E0";
when 16#00036# => romdata <= X"9C27A060";
when 16#00037# => romdata <= X"03100000";
when 16#00038# => romdata <= X"81C04000";
when 16#00039# => romdata <= X"01000000";
when 16#0003A# => romdata <= X"01000000";
when 16#0003B# => romdata <= X"01000000";
when 16#0003C# => romdata <= X"01000000";
when 16#0003D# => romdata <= X"01000000";
when 16#0003E# => romdata <= X"01000000";
when 16#0003F# => romdata <= X"01000000";
when 16#00040# => romdata <= X"00000004";
when 16#00041# => romdata <= X"00000000";
when 16#00042# => romdata <= X"00000004";
when 16#00043# => romdata <= X"00000000";
when 16#00044# => romdata <= X"FFFFFFFC";
when 16#00045# => romdata <= X"00000000";
when 16#00046# => romdata <= X"FFFFFFFC";
when 16#00047# => romdata <= X"00000000";
when 16#00048# => romdata <= X"00000000";
when others => romdata <= (others => '-');
end case;
end process;
-- pragma translate_off
bootmsg : report_version
generic map ("ahbrom" & tost(hindex) &
": 32-bit AHB ROM Module, " & tost(bytes/4) & " words, " & tost(abits-2) & " address bits" );
-- pragma translate_on
end;
|
----------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2004 GAISLER RESEARCH
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- See the file COPYING for the full details of the license.
--
-----------------------------------------------------------------------------
-- Entity: ahbrom
-- File: ahbrom.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: AHB rom. 0/1-waitstate read
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
entity ahbrom is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#fff#;
pipe : integer := 0;
tech : integer := 0;
kbytes : integer := 1);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type
);
end;
architecture rtl of ahbrom is
constant abits : integer := 9;
constant bytes : integer := 288;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_AHBROM, 0, 0, 0),
4 => ahb_membar(haddr, '1', '1', hmask), others => zero32);
signal romdata : std_logic_vector(31 downto 0);
signal addr : std_logic_vector(abits-1 downto 2);
signal hsel, hready : std_ulogic;
begin
ahbso.hresp <= "00";
ahbso.hsplit <= (others => '0');
ahbso.hirq <= (others => '0');
ahbso.hconfig <= hconfig;
ahbso.hindex <= hindex;
reg : process (clk)
begin
if rising_edge(clk) then
addr <= ahbsi.haddr(abits-1 downto 2);
end if;
end process;
p0 : if pipe = 0 generate
ahbso.hrdata <= ahbdrivedata(romdata);
ahbso.hready <= '1';
end generate;
p1 : if pipe = 1 generate
reg2 : process (clk)
begin
if rising_edge(clk) then
hsel <= ahbsi.hsel(hindex) and ahbsi.htrans(1);
hready <= ahbsi.hready;
ahbso.hready <= (not rst) or (hsel and hready) or
(ahbsi.hsel(hindex) and not ahbsi.htrans(1) and ahbsi.hready);
ahbso.hrdata <= ahbdrivedata(romdata);
end if;
end process;
end generate;
comb : process (addr)
begin
case conv_integer(addr) is
when 16#00000# => romdata <= X"81D82000";
when 16#00001# => romdata <= X"03000004";
when 16#00002# => romdata <= X"821060C0";
when 16#00003# => romdata <= X"81884000";
when 16#00004# => romdata <= X"81900000";
when 16#00005# => romdata <= X"81980000";
when 16#00006# => romdata <= X"81800000";
when 16#00007# => romdata <= X"01000000";
when 16#00008# => romdata <= X"03000040";
when 16#00009# => romdata <= X"8210600F";
when 16#0000A# => romdata <= X"C2A00040";
when 16#0000B# => romdata <= X"87444000";
when 16#0000C# => romdata <= X"8608E01F";
when 16#0000D# => romdata <= X"88100000";
when 16#0000E# => romdata <= X"8A100000";
when 16#0000F# => romdata <= X"8C100000";
when 16#00010# => romdata <= X"8E100000";
when 16#00011# => romdata <= X"A0100000";
when 16#00012# => romdata <= X"A2100000";
when 16#00013# => romdata <= X"A4100000";
when 16#00014# => romdata <= X"A6100000";
when 16#00015# => romdata <= X"A8100000";
when 16#00016# => romdata <= X"AA100000";
when 16#00017# => romdata <= X"AC100000";
when 16#00018# => romdata <= X"AE100000";
when 16#00019# => romdata <= X"90100000";
when 16#0001A# => romdata <= X"92100000";
when 16#0001B# => romdata <= X"94100000";
when 16#0001C# => romdata <= X"96100000";
when 16#0001D# => romdata <= X"98100000";
when 16#0001E# => romdata <= X"9A100000";
when 16#0001F# => romdata <= X"9C100000";
when 16#00020# => romdata <= X"9E100000";
when 16#00021# => romdata <= X"86A0E001";
when 16#00022# => romdata <= X"16BFFFEF";
when 16#00023# => romdata <= X"81E00000";
when 16#00024# => romdata <= X"82102002";
when 16#00025# => romdata <= X"81904000";
when 16#00026# => romdata <= X"03000004";
when 16#00027# => romdata <= X"821060E0";
when 16#00028# => romdata <= X"81884000";
when 16#00029# => romdata <= X"01000000";
when 16#0002A# => romdata <= X"01000000";
when 16#0002B# => romdata <= X"01000000";
when 16#0002C# => romdata <= X"03200000";
when 16#0002D# => romdata <= X"84102233";
when 16#0002E# => romdata <= X"C4204000";
when 16#0002F# => romdata <= X"0539AE13";
when 16#00030# => romdata <= X"8410A260";
when 16#00031# => romdata <= X"C4206004";
when 16#00032# => romdata <= X"050003FC";
when 16#00033# => romdata <= X"C4206008";
when 16#00034# => romdata <= X"3D1003FF";
when 16#00035# => romdata <= X"BC17A3E0";
when 16#00036# => romdata <= X"9C27A060";
when 16#00037# => romdata <= X"03100000";
when 16#00038# => romdata <= X"81C04000";
when 16#00039# => romdata <= X"01000000";
when 16#0003A# => romdata <= X"01000000";
when 16#0003B# => romdata <= X"01000000";
when 16#0003C# => romdata <= X"01000000";
when 16#0003D# => romdata <= X"01000000";
when 16#0003E# => romdata <= X"01000000";
when 16#0003F# => romdata <= X"01000000";
when 16#00040# => romdata <= X"00000004";
when 16#00041# => romdata <= X"00000000";
when 16#00042# => romdata <= X"00000004";
when 16#00043# => romdata <= X"00000000";
when 16#00044# => romdata <= X"FFFFFFFC";
when 16#00045# => romdata <= X"00000000";
when 16#00046# => romdata <= X"FFFFFFFC";
when 16#00047# => romdata <= X"00000000";
when 16#00048# => romdata <= X"00000000";
when others => romdata <= (others => '-');
end case;
end process;
-- pragma translate_off
bootmsg : report_version
generic map ("ahbrom" & tost(hindex) &
": 32-bit AHB ROM Module, " & tost(bytes/4) & " words, " & tost(abits-2) & " address bits" );
-- pragma translate_on
end;
|
----------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2004 GAISLER RESEARCH
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- See the file COPYING for the full details of the license.
--
-----------------------------------------------------------------------------
-- Entity: ahbrom
-- File: ahbrom.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: AHB rom. 0/1-waitstate read
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
entity ahbrom is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#fff#;
pipe : integer := 0;
tech : integer := 0;
kbytes : integer := 1);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type
);
end;
architecture rtl of ahbrom is
constant abits : integer := 9;
constant bytes : integer := 288;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_AHBROM, 0, 0, 0),
4 => ahb_membar(haddr, '1', '1', hmask), others => zero32);
signal romdata : std_logic_vector(31 downto 0);
signal addr : std_logic_vector(abits-1 downto 2);
signal hsel, hready : std_ulogic;
begin
ahbso.hresp <= "00";
ahbso.hsplit <= (others => '0');
ahbso.hirq <= (others => '0');
ahbso.hconfig <= hconfig;
ahbso.hindex <= hindex;
reg : process (clk)
begin
if rising_edge(clk) then
addr <= ahbsi.haddr(abits-1 downto 2);
end if;
end process;
p0 : if pipe = 0 generate
ahbso.hrdata <= ahbdrivedata(romdata);
ahbso.hready <= '1';
end generate;
p1 : if pipe = 1 generate
reg2 : process (clk)
begin
if rising_edge(clk) then
hsel <= ahbsi.hsel(hindex) and ahbsi.htrans(1);
hready <= ahbsi.hready;
ahbso.hready <= (not rst) or (hsel and hready) or
(ahbsi.hsel(hindex) and not ahbsi.htrans(1) and ahbsi.hready);
ahbso.hrdata <= ahbdrivedata(romdata);
end if;
end process;
end generate;
comb : process (addr)
begin
case conv_integer(addr) is
when 16#00000# => romdata <= X"81D82000";
when 16#00001# => romdata <= X"03000004";
when 16#00002# => romdata <= X"821060C0";
when 16#00003# => romdata <= X"81884000";
when 16#00004# => romdata <= X"81900000";
when 16#00005# => romdata <= X"81980000";
when 16#00006# => romdata <= X"81800000";
when 16#00007# => romdata <= X"01000000";
when 16#00008# => romdata <= X"03000040";
when 16#00009# => romdata <= X"8210600F";
when 16#0000A# => romdata <= X"C2A00040";
when 16#0000B# => romdata <= X"87444000";
when 16#0000C# => romdata <= X"8608E01F";
when 16#0000D# => romdata <= X"88100000";
when 16#0000E# => romdata <= X"8A100000";
when 16#0000F# => romdata <= X"8C100000";
when 16#00010# => romdata <= X"8E100000";
when 16#00011# => romdata <= X"A0100000";
when 16#00012# => romdata <= X"A2100000";
when 16#00013# => romdata <= X"A4100000";
when 16#00014# => romdata <= X"A6100000";
when 16#00015# => romdata <= X"A8100000";
when 16#00016# => romdata <= X"AA100000";
when 16#00017# => romdata <= X"AC100000";
when 16#00018# => romdata <= X"AE100000";
when 16#00019# => romdata <= X"90100000";
when 16#0001A# => romdata <= X"92100000";
when 16#0001B# => romdata <= X"94100000";
when 16#0001C# => romdata <= X"96100000";
when 16#0001D# => romdata <= X"98100000";
when 16#0001E# => romdata <= X"9A100000";
when 16#0001F# => romdata <= X"9C100000";
when 16#00020# => romdata <= X"9E100000";
when 16#00021# => romdata <= X"86A0E001";
when 16#00022# => romdata <= X"16BFFFEF";
when 16#00023# => romdata <= X"81E00000";
when 16#00024# => romdata <= X"82102002";
when 16#00025# => romdata <= X"81904000";
when 16#00026# => romdata <= X"03000004";
when 16#00027# => romdata <= X"821060E0";
when 16#00028# => romdata <= X"81884000";
when 16#00029# => romdata <= X"01000000";
when 16#0002A# => romdata <= X"01000000";
when 16#0002B# => romdata <= X"01000000";
when 16#0002C# => romdata <= X"03200000";
when 16#0002D# => romdata <= X"84102233";
when 16#0002E# => romdata <= X"C4204000";
when 16#0002F# => romdata <= X"0539AE13";
when 16#00030# => romdata <= X"8410A260";
when 16#00031# => romdata <= X"C4206004";
when 16#00032# => romdata <= X"050003FC";
when 16#00033# => romdata <= X"C4206008";
when 16#00034# => romdata <= X"3D1003FF";
when 16#00035# => romdata <= X"BC17A3E0";
when 16#00036# => romdata <= X"9C27A060";
when 16#00037# => romdata <= X"03100000";
when 16#00038# => romdata <= X"81C04000";
when 16#00039# => romdata <= X"01000000";
when 16#0003A# => romdata <= X"01000000";
when 16#0003B# => romdata <= X"01000000";
when 16#0003C# => romdata <= X"01000000";
when 16#0003D# => romdata <= X"01000000";
when 16#0003E# => romdata <= X"01000000";
when 16#0003F# => romdata <= X"01000000";
when 16#00040# => romdata <= X"00000004";
when 16#00041# => romdata <= X"00000000";
when 16#00042# => romdata <= X"00000004";
when 16#00043# => romdata <= X"00000000";
when 16#00044# => romdata <= X"FFFFFFFC";
when 16#00045# => romdata <= X"00000000";
when 16#00046# => romdata <= X"FFFFFFFC";
when 16#00047# => romdata <= X"00000000";
when 16#00048# => romdata <= X"00000000";
when others => romdata <= (others => '-');
end case;
end process;
-- pragma translate_off
bootmsg : report_version
generic map ("ahbrom" & tost(hindex) &
": 32-bit AHB ROM Module, " & tost(bytes/4) & " words, " & tost(abits-2) & " address bits" );
-- pragma translate_on
end;
|
----------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2004 GAISLER RESEARCH
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- See the file COPYING for the full details of the license.
--
-----------------------------------------------------------------------------
-- Entity: ahbrom
-- File: ahbrom.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: AHB rom. 0/1-waitstate read
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
entity ahbrom is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#fff#;
pipe : integer := 0;
tech : integer := 0;
kbytes : integer := 1);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type
);
end;
architecture rtl of ahbrom is
constant abits : integer := 9;
constant bytes : integer := 288;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_AHBROM, 0, 0, 0),
4 => ahb_membar(haddr, '1', '1', hmask), others => zero32);
signal romdata : std_logic_vector(31 downto 0);
signal addr : std_logic_vector(abits-1 downto 2);
signal hsel, hready : std_ulogic;
begin
ahbso.hresp <= "00";
ahbso.hsplit <= (others => '0');
ahbso.hirq <= (others => '0');
ahbso.hconfig <= hconfig;
ahbso.hindex <= hindex;
reg : process (clk)
begin
if rising_edge(clk) then
addr <= ahbsi.haddr(abits-1 downto 2);
end if;
end process;
p0 : if pipe = 0 generate
ahbso.hrdata <= ahbdrivedata(romdata);
ahbso.hready <= '1';
end generate;
p1 : if pipe = 1 generate
reg2 : process (clk)
begin
if rising_edge(clk) then
hsel <= ahbsi.hsel(hindex) and ahbsi.htrans(1);
hready <= ahbsi.hready;
ahbso.hready <= (not rst) or (hsel and hready) or
(ahbsi.hsel(hindex) and not ahbsi.htrans(1) and ahbsi.hready);
ahbso.hrdata <= ahbdrivedata(romdata);
end if;
end process;
end generate;
comb : process (addr)
begin
case conv_integer(addr) is
when 16#00000# => romdata <= X"81D82000";
when 16#00001# => romdata <= X"03000004";
when 16#00002# => romdata <= X"821060C0";
when 16#00003# => romdata <= X"81884000";
when 16#00004# => romdata <= X"81900000";
when 16#00005# => romdata <= X"81980000";
when 16#00006# => romdata <= X"81800000";
when 16#00007# => romdata <= X"01000000";
when 16#00008# => romdata <= X"03000040";
when 16#00009# => romdata <= X"8210600F";
when 16#0000A# => romdata <= X"C2A00040";
when 16#0000B# => romdata <= X"87444000";
when 16#0000C# => romdata <= X"8608E01F";
when 16#0000D# => romdata <= X"88100000";
when 16#0000E# => romdata <= X"8A100000";
when 16#0000F# => romdata <= X"8C100000";
when 16#00010# => romdata <= X"8E100000";
when 16#00011# => romdata <= X"A0100000";
when 16#00012# => romdata <= X"A2100000";
when 16#00013# => romdata <= X"A4100000";
when 16#00014# => romdata <= X"A6100000";
when 16#00015# => romdata <= X"A8100000";
when 16#00016# => romdata <= X"AA100000";
when 16#00017# => romdata <= X"AC100000";
when 16#00018# => romdata <= X"AE100000";
when 16#00019# => romdata <= X"90100000";
when 16#0001A# => romdata <= X"92100000";
when 16#0001B# => romdata <= X"94100000";
when 16#0001C# => romdata <= X"96100000";
when 16#0001D# => romdata <= X"98100000";
when 16#0001E# => romdata <= X"9A100000";
when 16#0001F# => romdata <= X"9C100000";
when 16#00020# => romdata <= X"9E100000";
when 16#00021# => romdata <= X"86A0E001";
when 16#00022# => romdata <= X"16BFFFEF";
when 16#00023# => romdata <= X"81E00000";
when 16#00024# => romdata <= X"82102002";
when 16#00025# => romdata <= X"81904000";
when 16#00026# => romdata <= X"03000004";
when 16#00027# => romdata <= X"821060E0";
when 16#00028# => romdata <= X"81884000";
when 16#00029# => romdata <= X"01000000";
when 16#0002A# => romdata <= X"01000000";
when 16#0002B# => romdata <= X"01000000";
when 16#0002C# => romdata <= X"03200000";
when 16#0002D# => romdata <= X"84102233";
when 16#0002E# => romdata <= X"C4204000";
when 16#0002F# => romdata <= X"0539AE13";
when 16#00030# => romdata <= X"8410A260";
when 16#00031# => romdata <= X"C4206004";
when 16#00032# => romdata <= X"050003FC";
when 16#00033# => romdata <= X"C4206008";
when 16#00034# => romdata <= X"3D1003FF";
when 16#00035# => romdata <= X"BC17A3E0";
when 16#00036# => romdata <= X"9C27A060";
when 16#00037# => romdata <= X"03100000";
when 16#00038# => romdata <= X"81C04000";
when 16#00039# => romdata <= X"01000000";
when 16#0003A# => romdata <= X"01000000";
when 16#0003B# => romdata <= X"01000000";
when 16#0003C# => romdata <= X"01000000";
when 16#0003D# => romdata <= X"01000000";
when 16#0003E# => romdata <= X"01000000";
when 16#0003F# => romdata <= X"01000000";
when 16#00040# => romdata <= X"00000004";
when 16#00041# => romdata <= X"00000000";
when 16#00042# => romdata <= X"00000004";
when 16#00043# => romdata <= X"00000000";
when 16#00044# => romdata <= X"FFFFFFFC";
when 16#00045# => romdata <= X"00000000";
when 16#00046# => romdata <= X"FFFFFFFC";
when 16#00047# => romdata <= X"00000000";
when 16#00048# => romdata <= X"00000000";
when others => romdata <= (others => '-');
end case;
end process;
-- pragma translate_off
bootmsg : report_version
generic map ("ahbrom" & tost(hindex) &
": 32-bit AHB ROM Module, " & tost(bytes/4) & " words, " & tost(abits-2) & " address bits" );
-- pragma translate_on
end;
|
----------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2004 GAISLER RESEARCH
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- See the file COPYING for the full details of the license.
--
-----------------------------------------------------------------------------
-- Entity: ahbrom
-- File: ahbrom.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: AHB rom. 0/1-waitstate read
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
entity ahbrom is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#fff#;
pipe : integer := 0;
tech : integer := 0;
kbytes : integer := 1);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type
);
end;
architecture rtl of ahbrom is
constant abits : integer := 9;
constant bytes : integer := 288;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_AHBROM, 0, 0, 0),
4 => ahb_membar(haddr, '1', '1', hmask), others => zero32);
signal romdata : std_logic_vector(31 downto 0);
signal addr : std_logic_vector(abits-1 downto 2);
signal hsel, hready : std_ulogic;
begin
ahbso.hresp <= "00";
ahbso.hsplit <= (others => '0');
ahbso.hirq <= (others => '0');
ahbso.hconfig <= hconfig;
ahbso.hindex <= hindex;
reg : process (clk)
begin
if rising_edge(clk) then
addr <= ahbsi.haddr(abits-1 downto 2);
end if;
end process;
p0 : if pipe = 0 generate
ahbso.hrdata <= ahbdrivedata(romdata);
ahbso.hready <= '1';
end generate;
p1 : if pipe = 1 generate
reg2 : process (clk)
begin
if rising_edge(clk) then
hsel <= ahbsi.hsel(hindex) and ahbsi.htrans(1);
hready <= ahbsi.hready;
ahbso.hready <= (not rst) or (hsel and hready) or
(ahbsi.hsel(hindex) and not ahbsi.htrans(1) and ahbsi.hready);
ahbso.hrdata <= ahbdrivedata(romdata);
end if;
end process;
end generate;
comb : process (addr)
begin
case conv_integer(addr) is
when 16#00000# => romdata <= X"81D82000";
when 16#00001# => romdata <= X"03000004";
when 16#00002# => romdata <= X"821060C0";
when 16#00003# => romdata <= X"81884000";
when 16#00004# => romdata <= X"81900000";
when 16#00005# => romdata <= X"81980000";
when 16#00006# => romdata <= X"81800000";
when 16#00007# => romdata <= X"01000000";
when 16#00008# => romdata <= X"03000040";
when 16#00009# => romdata <= X"8210600F";
when 16#0000A# => romdata <= X"C2A00040";
when 16#0000B# => romdata <= X"87444000";
when 16#0000C# => romdata <= X"8608E01F";
when 16#0000D# => romdata <= X"88100000";
when 16#0000E# => romdata <= X"8A100000";
when 16#0000F# => romdata <= X"8C100000";
when 16#00010# => romdata <= X"8E100000";
when 16#00011# => romdata <= X"A0100000";
when 16#00012# => romdata <= X"A2100000";
when 16#00013# => romdata <= X"A4100000";
when 16#00014# => romdata <= X"A6100000";
when 16#00015# => romdata <= X"A8100000";
when 16#00016# => romdata <= X"AA100000";
when 16#00017# => romdata <= X"AC100000";
when 16#00018# => romdata <= X"AE100000";
when 16#00019# => romdata <= X"90100000";
when 16#0001A# => romdata <= X"92100000";
when 16#0001B# => romdata <= X"94100000";
when 16#0001C# => romdata <= X"96100000";
when 16#0001D# => romdata <= X"98100000";
when 16#0001E# => romdata <= X"9A100000";
when 16#0001F# => romdata <= X"9C100000";
when 16#00020# => romdata <= X"9E100000";
when 16#00021# => romdata <= X"86A0E001";
when 16#00022# => romdata <= X"16BFFFEF";
when 16#00023# => romdata <= X"81E00000";
when 16#00024# => romdata <= X"82102002";
when 16#00025# => romdata <= X"81904000";
when 16#00026# => romdata <= X"03000004";
when 16#00027# => romdata <= X"821060E0";
when 16#00028# => romdata <= X"81884000";
when 16#00029# => romdata <= X"01000000";
when 16#0002A# => romdata <= X"01000000";
when 16#0002B# => romdata <= X"01000000";
when 16#0002C# => romdata <= X"03200000";
when 16#0002D# => romdata <= X"84102233";
when 16#0002E# => romdata <= X"C4204000";
when 16#0002F# => romdata <= X"0539AE13";
when 16#00030# => romdata <= X"8410A260";
when 16#00031# => romdata <= X"C4206004";
when 16#00032# => romdata <= X"050003FC";
when 16#00033# => romdata <= X"C4206008";
when 16#00034# => romdata <= X"3D1003FF";
when 16#00035# => romdata <= X"BC17A3E0";
when 16#00036# => romdata <= X"9C27A060";
when 16#00037# => romdata <= X"03100000";
when 16#00038# => romdata <= X"81C04000";
when 16#00039# => romdata <= X"01000000";
when 16#0003A# => romdata <= X"01000000";
when 16#0003B# => romdata <= X"01000000";
when 16#0003C# => romdata <= X"01000000";
when 16#0003D# => romdata <= X"01000000";
when 16#0003E# => romdata <= X"01000000";
when 16#0003F# => romdata <= X"01000000";
when 16#00040# => romdata <= X"00000004";
when 16#00041# => romdata <= X"00000000";
when 16#00042# => romdata <= X"00000004";
when 16#00043# => romdata <= X"00000000";
when 16#00044# => romdata <= X"FFFFFFFC";
when 16#00045# => romdata <= X"00000000";
when 16#00046# => romdata <= X"FFFFFFFC";
when 16#00047# => romdata <= X"00000000";
when 16#00048# => romdata <= X"00000000";
when others => romdata <= (others => '-');
end case;
end process;
-- pragma translate_off
bootmsg : report_version
generic map ("ahbrom" & tost(hindex) &
": 32-bit AHB ROM Module, " & tost(bytes/4) & " words, " & tost(abits-2) & " address bits" );
-- pragma translate_on
end;
|
----------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2004 GAISLER RESEARCH
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- See the file COPYING for the full details of the license.
--
-----------------------------------------------------------------------------
-- Entity: ahbrom
-- File: ahbrom.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: AHB rom. 0/1-waitstate read
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
entity ahbrom is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#fff#;
pipe : integer := 0;
tech : integer := 0;
kbytes : integer := 1);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type
);
end;
architecture rtl of ahbrom is
constant abits : integer := 9;
constant bytes : integer := 288;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_AHBROM, 0, 0, 0),
4 => ahb_membar(haddr, '1', '1', hmask), others => zero32);
signal romdata : std_logic_vector(31 downto 0);
signal addr : std_logic_vector(abits-1 downto 2);
signal hsel, hready : std_ulogic;
begin
ahbso.hresp <= "00";
ahbso.hsplit <= (others => '0');
ahbso.hirq <= (others => '0');
ahbso.hconfig <= hconfig;
ahbso.hindex <= hindex;
reg : process (clk)
begin
if rising_edge(clk) then
addr <= ahbsi.haddr(abits-1 downto 2);
end if;
end process;
p0 : if pipe = 0 generate
ahbso.hrdata <= ahbdrivedata(romdata);
ahbso.hready <= '1';
end generate;
p1 : if pipe = 1 generate
reg2 : process (clk)
begin
if rising_edge(clk) then
hsel <= ahbsi.hsel(hindex) and ahbsi.htrans(1);
hready <= ahbsi.hready;
ahbso.hready <= (not rst) or (hsel and hready) or
(ahbsi.hsel(hindex) and not ahbsi.htrans(1) and ahbsi.hready);
ahbso.hrdata <= ahbdrivedata(romdata);
end if;
end process;
end generate;
comb : process (addr)
begin
case conv_integer(addr) is
when 16#00000# => romdata <= X"81D82000";
when 16#00001# => romdata <= X"03000004";
when 16#00002# => romdata <= X"821060C0";
when 16#00003# => romdata <= X"81884000";
when 16#00004# => romdata <= X"81900000";
when 16#00005# => romdata <= X"81980000";
when 16#00006# => romdata <= X"81800000";
when 16#00007# => romdata <= X"01000000";
when 16#00008# => romdata <= X"03000040";
when 16#00009# => romdata <= X"8210600F";
when 16#0000A# => romdata <= X"C2A00040";
when 16#0000B# => romdata <= X"87444000";
when 16#0000C# => romdata <= X"8608E01F";
when 16#0000D# => romdata <= X"88100000";
when 16#0000E# => romdata <= X"8A100000";
when 16#0000F# => romdata <= X"8C100000";
when 16#00010# => romdata <= X"8E100000";
when 16#00011# => romdata <= X"A0100000";
when 16#00012# => romdata <= X"A2100000";
when 16#00013# => romdata <= X"A4100000";
when 16#00014# => romdata <= X"A6100000";
when 16#00015# => romdata <= X"A8100000";
when 16#00016# => romdata <= X"AA100000";
when 16#00017# => romdata <= X"AC100000";
when 16#00018# => romdata <= X"AE100000";
when 16#00019# => romdata <= X"90100000";
when 16#0001A# => romdata <= X"92100000";
when 16#0001B# => romdata <= X"94100000";
when 16#0001C# => romdata <= X"96100000";
when 16#0001D# => romdata <= X"98100000";
when 16#0001E# => romdata <= X"9A100000";
when 16#0001F# => romdata <= X"9C100000";
when 16#00020# => romdata <= X"9E100000";
when 16#00021# => romdata <= X"86A0E001";
when 16#00022# => romdata <= X"16BFFFEF";
when 16#00023# => romdata <= X"81E00000";
when 16#00024# => romdata <= X"82102002";
when 16#00025# => romdata <= X"81904000";
when 16#00026# => romdata <= X"03000004";
when 16#00027# => romdata <= X"821060E0";
when 16#00028# => romdata <= X"81884000";
when 16#00029# => romdata <= X"01000000";
when 16#0002A# => romdata <= X"01000000";
when 16#0002B# => romdata <= X"01000000";
when 16#0002C# => romdata <= X"03200000";
when 16#0002D# => romdata <= X"84102233";
when 16#0002E# => romdata <= X"C4204000";
when 16#0002F# => romdata <= X"0539AE13";
when 16#00030# => romdata <= X"8410A260";
when 16#00031# => romdata <= X"C4206004";
when 16#00032# => romdata <= X"050003FC";
when 16#00033# => romdata <= X"C4206008";
when 16#00034# => romdata <= X"3D1003FF";
when 16#00035# => romdata <= X"BC17A3E0";
when 16#00036# => romdata <= X"9C27A060";
when 16#00037# => romdata <= X"03100000";
when 16#00038# => romdata <= X"81C04000";
when 16#00039# => romdata <= X"01000000";
when 16#0003A# => romdata <= X"01000000";
when 16#0003B# => romdata <= X"01000000";
when 16#0003C# => romdata <= X"01000000";
when 16#0003D# => romdata <= X"01000000";
when 16#0003E# => romdata <= X"01000000";
when 16#0003F# => romdata <= X"01000000";
when 16#00040# => romdata <= X"00000004";
when 16#00041# => romdata <= X"00000000";
when 16#00042# => romdata <= X"00000004";
when 16#00043# => romdata <= X"00000000";
when 16#00044# => romdata <= X"FFFFFFFC";
when 16#00045# => romdata <= X"00000000";
when 16#00046# => romdata <= X"FFFFFFFC";
when 16#00047# => romdata <= X"00000000";
when 16#00048# => romdata <= X"00000000";
when others => romdata <= (others => '-');
end case;
end process;
-- pragma translate_off
bootmsg : report_version
generic map ("ahbrom" & tost(hindex) &
": 32-bit AHB ROM Module, " & tost(bytes/4) & " words, " & tost(abits-2) & " address bits" );
-- pragma translate_on
end;
|
----------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2004 GAISLER RESEARCH
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- See the file COPYING for the full details of the license.
--
-----------------------------------------------------------------------------
-- Entity: ahbrom
-- File: ahbrom.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: AHB rom. 0/1-waitstate read
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
entity ahbrom is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#fff#;
pipe : integer := 0;
tech : integer := 0;
kbytes : integer := 1);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type
);
end;
architecture rtl of ahbrom is
constant abits : integer := 9;
constant bytes : integer := 288;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_AHBROM, 0, 0, 0),
4 => ahb_membar(haddr, '1', '1', hmask), others => zero32);
signal romdata : std_logic_vector(31 downto 0);
signal addr : std_logic_vector(abits-1 downto 2);
signal hsel, hready : std_ulogic;
begin
ahbso.hresp <= "00";
ahbso.hsplit <= (others => '0');
ahbso.hirq <= (others => '0');
ahbso.hconfig <= hconfig;
ahbso.hindex <= hindex;
reg : process (clk)
begin
if rising_edge(clk) then
addr <= ahbsi.haddr(abits-1 downto 2);
end if;
end process;
p0 : if pipe = 0 generate
ahbso.hrdata <= ahbdrivedata(romdata);
ahbso.hready <= '1';
end generate;
p1 : if pipe = 1 generate
reg2 : process (clk)
begin
if rising_edge(clk) then
hsel <= ahbsi.hsel(hindex) and ahbsi.htrans(1);
hready <= ahbsi.hready;
ahbso.hready <= (not rst) or (hsel and hready) or
(ahbsi.hsel(hindex) and not ahbsi.htrans(1) and ahbsi.hready);
ahbso.hrdata <= ahbdrivedata(romdata);
end if;
end process;
end generate;
comb : process (addr)
begin
case conv_integer(addr) is
when 16#00000# => romdata <= X"81D82000";
when 16#00001# => romdata <= X"03000004";
when 16#00002# => romdata <= X"821060C0";
when 16#00003# => romdata <= X"81884000";
when 16#00004# => romdata <= X"81900000";
when 16#00005# => romdata <= X"81980000";
when 16#00006# => romdata <= X"81800000";
when 16#00007# => romdata <= X"01000000";
when 16#00008# => romdata <= X"03000040";
when 16#00009# => romdata <= X"8210600F";
when 16#0000A# => romdata <= X"C2A00040";
when 16#0000B# => romdata <= X"87444000";
when 16#0000C# => romdata <= X"8608E01F";
when 16#0000D# => romdata <= X"88100000";
when 16#0000E# => romdata <= X"8A100000";
when 16#0000F# => romdata <= X"8C100000";
when 16#00010# => romdata <= X"8E100000";
when 16#00011# => romdata <= X"A0100000";
when 16#00012# => romdata <= X"A2100000";
when 16#00013# => romdata <= X"A4100000";
when 16#00014# => romdata <= X"A6100000";
when 16#00015# => romdata <= X"A8100000";
when 16#00016# => romdata <= X"AA100000";
when 16#00017# => romdata <= X"AC100000";
when 16#00018# => romdata <= X"AE100000";
when 16#00019# => romdata <= X"90100000";
when 16#0001A# => romdata <= X"92100000";
when 16#0001B# => romdata <= X"94100000";
when 16#0001C# => romdata <= X"96100000";
when 16#0001D# => romdata <= X"98100000";
when 16#0001E# => romdata <= X"9A100000";
when 16#0001F# => romdata <= X"9C100000";
when 16#00020# => romdata <= X"9E100000";
when 16#00021# => romdata <= X"86A0E001";
when 16#00022# => romdata <= X"16BFFFEF";
when 16#00023# => romdata <= X"81E00000";
when 16#00024# => romdata <= X"82102002";
when 16#00025# => romdata <= X"81904000";
when 16#00026# => romdata <= X"03000004";
when 16#00027# => romdata <= X"821060E0";
when 16#00028# => romdata <= X"81884000";
when 16#00029# => romdata <= X"01000000";
when 16#0002A# => romdata <= X"01000000";
when 16#0002B# => romdata <= X"01000000";
when 16#0002C# => romdata <= X"03200000";
when 16#0002D# => romdata <= X"84102233";
when 16#0002E# => romdata <= X"C4204000";
when 16#0002F# => romdata <= X"0539AE13";
when 16#00030# => romdata <= X"8410A260";
when 16#00031# => romdata <= X"C4206004";
when 16#00032# => romdata <= X"050003FC";
when 16#00033# => romdata <= X"C4206008";
when 16#00034# => romdata <= X"3D1003FF";
when 16#00035# => romdata <= X"BC17A3E0";
when 16#00036# => romdata <= X"9C27A060";
when 16#00037# => romdata <= X"03100000";
when 16#00038# => romdata <= X"81C04000";
when 16#00039# => romdata <= X"01000000";
when 16#0003A# => romdata <= X"01000000";
when 16#0003B# => romdata <= X"01000000";
when 16#0003C# => romdata <= X"01000000";
when 16#0003D# => romdata <= X"01000000";
when 16#0003E# => romdata <= X"01000000";
when 16#0003F# => romdata <= X"01000000";
when 16#00040# => romdata <= X"00000004";
when 16#00041# => romdata <= X"00000000";
when 16#00042# => romdata <= X"00000004";
when 16#00043# => romdata <= X"00000000";
when 16#00044# => romdata <= X"FFFFFFFC";
when 16#00045# => romdata <= X"00000000";
when 16#00046# => romdata <= X"FFFFFFFC";
when 16#00047# => romdata <= X"00000000";
when 16#00048# => romdata <= X"00000000";
when others => romdata <= (others => '-');
end case;
end process;
-- pragma translate_off
bootmsg : report_version
generic map ("ahbrom" & tost(hindex) &
": 32-bit AHB ROM Module, " & tost(bytes/4) & " words, " & tost(abits-2) & " address bits" );
-- pragma translate_on
end;
|
----------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2004 GAISLER RESEARCH
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- See the file COPYING for the full details of the license.
--
-----------------------------------------------------------------------------
-- Entity: ahbrom
-- File: ahbrom.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: AHB rom. 0/1-waitstate read
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
entity ahbrom is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#fff#;
pipe : integer := 0;
tech : integer := 0;
kbytes : integer := 1);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type
);
end;
architecture rtl of ahbrom is
constant abits : integer := 9;
constant bytes : integer := 288;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_AHBROM, 0, 0, 0),
4 => ahb_membar(haddr, '1', '1', hmask), others => zero32);
signal romdata : std_logic_vector(31 downto 0);
signal addr : std_logic_vector(abits-1 downto 2);
signal hsel, hready : std_ulogic;
begin
ahbso.hresp <= "00";
ahbso.hsplit <= (others => '0');
ahbso.hirq <= (others => '0');
ahbso.hconfig <= hconfig;
ahbso.hindex <= hindex;
reg : process (clk)
begin
if rising_edge(clk) then
addr <= ahbsi.haddr(abits-1 downto 2);
end if;
end process;
p0 : if pipe = 0 generate
ahbso.hrdata <= ahbdrivedata(romdata);
ahbso.hready <= '1';
end generate;
p1 : if pipe = 1 generate
reg2 : process (clk)
begin
if rising_edge(clk) then
hsel <= ahbsi.hsel(hindex) and ahbsi.htrans(1);
hready <= ahbsi.hready;
ahbso.hready <= (not rst) or (hsel and hready) or
(ahbsi.hsel(hindex) and not ahbsi.htrans(1) and ahbsi.hready);
ahbso.hrdata <= ahbdrivedata(romdata);
end if;
end process;
end generate;
comb : process (addr)
begin
case conv_integer(addr) is
when 16#00000# => romdata <= X"81D82000";
when 16#00001# => romdata <= X"03000004";
when 16#00002# => romdata <= X"821060C0";
when 16#00003# => romdata <= X"81884000";
when 16#00004# => romdata <= X"81900000";
when 16#00005# => romdata <= X"81980000";
when 16#00006# => romdata <= X"81800000";
when 16#00007# => romdata <= X"01000000";
when 16#00008# => romdata <= X"03000040";
when 16#00009# => romdata <= X"8210600F";
when 16#0000A# => romdata <= X"C2A00040";
when 16#0000B# => romdata <= X"87444000";
when 16#0000C# => romdata <= X"8608E01F";
when 16#0000D# => romdata <= X"88100000";
when 16#0000E# => romdata <= X"8A100000";
when 16#0000F# => romdata <= X"8C100000";
when 16#00010# => romdata <= X"8E100000";
when 16#00011# => romdata <= X"A0100000";
when 16#00012# => romdata <= X"A2100000";
when 16#00013# => romdata <= X"A4100000";
when 16#00014# => romdata <= X"A6100000";
when 16#00015# => romdata <= X"A8100000";
when 16#00016# => romdata <= X"AA100000";
when 16#00017# => romdata <= X"AC100000";
when 16#00018# => romdata <= X"AE100000";
when 16#00019# => romdata <= X"90100000";
when 16#0001A# => romdata <= X"92100000";
when 16#0001B# => romdata <= X"94100000";
when 16#0001C# => romdata <= X"96100000";
when 16#0001D# => romdata <= X"98100000";
when 16#0001E# => romdata <= X"9A100000";
when 16#0001F# => romdata <= X"9C100000";
when 16#00020# => romdata <= X"9E100000";
when 16#00021# => romdata <= X"86A0E001";
when 16#00022# => romdata <= X"16BFFFEF";
when 16#00023# => romdata <= X"81E00000";
when 16#00024# => romdata <= X"82102002";
when 16#00025# => romdata <= X"81904000";
when 16#00026# => romdata <= X"03000004";
when 16#00027# => romdata <= X"821060E0";
when 16#00028# => romdata <= X"81884000";
when 16#00029# => romdata <= X"01000000";
when 16#0002A# => romdata <= X"01000000";
when 16#0002B# => romdata <= X"01000000";
when 16#0002C# => romdata <= X"03200000";
when 16#0002D# => romdata <= X"84102233";
when 16#0002E# => romdata <= X"C4204000";
when 16#0002F# => romdata <= X"0539AE13";
when 16#00030# => romdata <= X"8410A260";
when 16#00031# => romdata <= X"C4206004";
when 16#00032# => romdata <= X"050003FC";
when 16#00033# => romdata <= X"C4206008";
when 16#00034# => romdata <= X"3D1003FF";
when 16#00035# => romdata <= X"BC17A3E0";
when 16#00036# => romdata <= X"9C27A060";
when 16#00037# => romdata <= X"03100000";
when 16#00038# => romdata <= X"81C04000";
when 16#00039# => romdata <= X"01000000";
when 16#0003A# => romdata <= X"01000000";
when 16#0003B# => romdata <= X"01000000";
when 16#0003C# => romdata <= X"01000000";
when 16#0003D# => romdata <= X"01000000";
when 16#0003E# => romdata <= X"01000000";
when 16#0003F# => romdata <= X"01000000";
when 16#00040# => romdata <= X"00000004";
when 16#00041# => romdata <= X"00000000";
when 16#00042# => romdata <= X"00000004";
when 16#00043# => romdata <= X"00000000";
when 16#00044# => romdata <= X"FFFFFFFC";
when 16#00045# => romdata <= X"00000000";
when 16#00046# => romdata <= X"FFFFFFFC";
when 16#00047# => romdata <= X"00000000";
when 16#00048# => romdata <= X"00000000";
when others => romdata <= (others => '-');
end case;
end process;
-- pragma translate_off
bootmsg : report_version
generic map ("ahbrom" & tost(hindex) &
": 32-bit AHB ROM Module, " & tost(bytes/4) & " words, " & tost(abits-2) & " address bits" );
-- pragma translate_on
end;
|
----------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2004 GAISLER RESEARCH
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- See the file COPYING for the full details of the license.
--
-----------------------------------------------------------------------------
-- Entity: ahbrom
-- File: ahbrom.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: AHB rom. 0/1-waitstate read
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
entity ahbrom is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#fff#;
pipe : integer := 0;
tech : integer := 0;
kbytes : integer := 1);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type
);
end;
architecture rtl of ahbrom is
constant abits : integer := 9;
constant bytes : integer := 288;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_AHBROM, 0, 0, 0),
4 => ahb_membar(haddr, '1', '1', hmask), others => zero32);
signal romdata : std_logic_vector(31 downto 0);
signal addr : std_logic_vector(abits-1 downto 2);
signal hsel, hready : std_ulogic;
begin
ahbso.hresp <= "00";
ahbso.hsplit <= (others => '0');
ahbso.hirq <= (others => '0');
ahbso.hconfig <= hconfig;
ahbso.hindex <= hindex;
reg : process (clk)
begin
if rising_edge(clk) then
addr <= ahbsi.haddr(abits-1 downto 2);
end if;
end process;
p0 : if pipe = 0 generate
ahbso.hrdata <= ahbdrivedata(romdata);
ahbso.hready <= '1';
end generate;
p1 : if pipe = 1 generate
reg2 : process (clk)
begin
if rising_edge(clk) then
hsel <= ahbsi.hsel(hindex) and ahbsi.htrans(1);
hready <= ahbsi.hready;
ahbso.hready <= (not rst) or (hsel and hready) or
(ahbsi.hsel(hindex) and not ahbsi.htrans(1) and ahbsi.hready);
ahbso.hrdata <= ahbdrivedata(romdata);
end if;
end process;
end generate;
comb : process (addr)
begin
case conv_integer(addr) is
when 16#00000# => romdata <= X"81D82000";
when 16#00001# => romdata <= X"03000004";
when 16#00002# => romdata <= X"821060C0";
when 16#00003# => romdata <= X"81884000";
when 16#00004# => romdata <= X"81900000";
when 16#00005# => romdata <= X"81980000";
when 16#00006# => romdata <= X"81800000";
when 16#00007# => romdata <= X"01000000";
when 16#00008# => romdata <= X"03000040";
when 16#00009# => romdata <= X"8210600F";
when 16#0000A# => romdata <= X"C2A00040";
when 16#0000B# => romdata <= X"87444000";
when 16#0000C# => romdata <= X"8608E01F";
when 16#0000D# => romdata <= X"88100000";
when 16#0000E# => romdata <= X"8A100000";
when 16#0000F# => romdata <= X"8C100000";
when 16#00010# => romdata <= X"8E100000";
when 16#00011# => romdata <= X"A0100000";
when 16#00012# => romdata <= X"A2100000";
when 16#00013# => romdata <= X"A4100000";
when 16#00014# => romdata <= X"A6100000";
when 16#00015# => romdata <= X"A8100000";
when 16#00016# => romdata <= X"AA100000";
when 16#00017# => romdata <= X"AC100000";
when 16#00018# => romdata <= X"AE100000";
when 16#00019# => romdata <= X"90100000";
when 16#0001A# => romdata <= X"92100000";
when 16#0001B# => romdata <= X"94100000";
when 16#0001C# => romdata <= X"96100000";
when 16#0001D# => romdata <= X"98100000";
when 16#0001E# => romdata <= X"9A100000";
when 16#0001F# => romdata <= X"9C100000";
when 16#00020# => romdata <= X"9E100000";
when 16#00021# => romdata <= X"86A0E001";
when 16#00022# => romdata <= X"16BFFFEF";
when 16#00023# => romdata <= X"81E00000";
when 16#00024# => romdata <= X"82102002";
when 16#00025# => romdata <= X"81904000";
when 16#00026# => romdata <= X"03000004";
when 16#00027# => romdata <= X"821060E0";
when 16#00028# => romdata <= X"81884000";
when 16#00029# => romdata <= X"01000000";
when 16#0002A# => romdata <= X"01000000";
when 16#0002B# => romdata <= X"01000000";
when 16#0002C# => romdata <= X"03200000";
when 16#0002D# => romdata <= X"84102233";
when 16#0002E# => romdata <= X"C4204000";
when 16#0002F# => romdata <= X"0539AE13";
when 16#00030# => romdata <= X"8410A260";
when 16#00031# => romdata <= X"C4206004";
when 16#00032# => romdata <= X"050003FC";
when 16#00033# => romdata <= X"C4206008";
when 16#00034# => romdata <= X"3D1003FF";
when 16#00035# => romdata <= X"BC17A3E0";
when 16#00036# => romdata <= X"9C27A060";
when 16#00037# => romdata <= X"03100000";
when 16#00038# => romdata <= X"81C04000";
when 16#00039# => romdata <= X"01000000";
when 16#0003A# => romdata <= X"01000000";
when 16#0003B# => romdata <= X"01000000";
when 16#0003C# => romdata <= X"01000000";
when 16#0003D# => romdata <= X"01000000";
when 16#0003E# => romdata <= X"01000000";
when 16#0003F# => romdata <= X"01000000";
when 16#00040# => romdata <= X"00000004";
when 16#00041# => romdata <= X"00000000";
when 16#00042# => romdata <= X"00000004";
when 16#00043# => romdata <= X"00000000";
when 16#00044# => romdata <= X"FFFFFFFC";
when 16#00045# => romdata <= X"00000000";
when 16#00046# => romdata <= X"FFFFFFFC";
when 16#00047# => romdata <= X"00000000";
when 16#00048# => romdata <= X"00000000";
when others => romdata <= (others => '-');
end case;
end process;
-- pragma translate_off
bootmsg : report_version
generic map ("ahbrom" & tost(hindex) &
": 32-bit AHB ROM Module, " & tost(bytes/4) & " words, " & tost(abits-2) & " address bits" );
-- pragma translate_on
end;
|
----------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2004 GAISLER RESEARCH
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- See the file COPYING for the full details of the license.
--
-----------------------------------------------------------------------------
-- Entity: ahbrom
-- File: ahbrom.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: AHB rom. 0/1-waitstate read
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
entity ahbrom is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#fff#;
pipe : integer := 0;
tech : integer := 0;
kbytes : integer := 1);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type
);
end;
architecture rtl of ahbrom is
constant abits : integer := 9;
constant bytes : integer := 288;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_AHBROM, 0, 0, 0),
4 => ahb_membar(haddr, '1', '1', hmask), others => zero32);
signal romdata : std_logic_vector(31 downto 0);
signal addr : std_logic_vector(abits-1 downto 2);
signal hsel, hready : std_ulogic;
begin
ahbso.hresp <= "00";
ahbso.hsplit <= (others => '0');
ahbso.hirq <= (others => '0');
ahbso.hconfig <= hconfig;
ahbso.hindex <= hindex;
reg : process (clk)
begin
if rising_edge(clk) then
addr <= ahbsi.haddr(abits-1 downto 2);
end if;
end process;
p0 : if pipe = 0 generate
ahbso.hrdata <= ahbdrivedata(romdata);
ahbso.hready <= '1';
end generate;
p1 : if pipe = 1 generate
reg2 : process (clk)
begin
if rising_edge(clk) then
hsel <= ahbsi.hsel(hindex) and ahbsi.htrans(1);
hready <= ahbsi.hready;
ahbso.hready <= (not rst) or (hsel and hready) or
(ahbsi.hsel(hindex) and not ahbsi.htrans(1) and ahbsi.hready);
ahbso.hrdata <= ahbdrivedata(romdata);
end if;
end process;
end generate;
comb : process (addr)
begin
case conv_integer(addr) is
when 16#00000# => romdata <= X"81D82000";
when 16#00001# => romdata <= X"03000004";
when 16#00002# => romdata <= X"821060C0";
when 16#00003# => romdata <= X"81884000";
when 16#00004# => romdata <= X"81900000";
when 16#00005# => romdata <= X"81980000";
when 16#00006# => romdata <= X"81800000";
when 16#00007# => romdata <= X"01000000";
when 16#00008# => romdata <= X"03000040";
when 16#00009# => romdata <= X"8210600F";
when 16#0000A# => romdata <= X"C2A00040";
when 16#0000B# => romdata <= X"87444000";
when 16#0000C# => romdata <= X"8608E01F";
when 16#0000D# => romdata <= X"88100000";
when 16#0000E# => romdata <= X"8A100000";
when 16#0000F# => romdata <= X"8C100000";
when 16#00010# => romdata <= X"8E100000";
when 16#00011# => romdata <= X"A0100000";
when 16#00012# => romdata <= X"A2100000";
when 16#00013# => romdata <= X"A4100000";
when 16#00014# => romdata <= X"A6100000";
when 16#00015# => romdata <= X"A8100000";
when 16#00016# => romdata <= X"AA100000";
when 16#00017# => romdata <= X"AC100000";
when 16#00018# => romdata <= X"AE100000";
when 16#00019# => romdata <= X"90100000";
when 16#0001A# => romdata <= X"92100000";
when 16#0001B# => romdata <= X"94100000";
when 16#0001C# => romdata <= X"96100000";
when 16#0001D# => romdata <= X"98100000";
when 16#0001E# => romdata <= X"9A100000";
when 16#0001F# => romdata <= X"9C100000";
when 16#00020# => romdata <= X"9E100000";
when 16#00021# => romdata <= X"86A0E001";
when 16#00022# => romdata <= X"16BFFFEF";
when 16#00023# => romdata <= X"81E00000";
when 16#00024# => romdata <= X"82102002";
when 16#00025# => romdata <= X"81904000";
when 16#00026# => romdata <= X"03000004";
when 16#00027# => romdata <= X"821060E0";
when 16#00028# => romdata <= X"81884000";
when 16#00029# => romdata <= X"01000000";
when 16#0002A# => romdata <= X"01000000";
when 16#0002B# => romdata <= X"01000000";
when 16#0002C# => romdata <= X"03200000";
when 16#0002D# => romdata <= X"84102233";
when 16#0002E# => romdata <= X"C4204000";
when 16#0002F# => romdata <= X"0539AE13";
when 16#00030# => romdata <= X"8410A260";
when 16#00031# => romdata <= X"C4206004";
when 16#00032# => romdata <= X"050003FC";
when 16#00033# => romdata <= X"C4206008";
when 16#00034# => romdata <= X"3D1003FF";
when 16#00035# => romdata <= X"BC17A3E0";
when 16#00036# => romdata <= X"9C27A060";
when 16#00037# => romdata <= X"03100000";
when 16#00038# => romdata <= X"81C04000";
when 16#00039# => romdata <= X"01000000";
when 16#0003A# => romdata <= X"01000000";
when 16#0003B# => romdata <= X"01000000";
when 16#0003C# => romdata <= X"01000000";
when 16#0003D# => romdata <= X"01000000";
when 16#0003E# => romdata <= X"01000000";
when 16#0003F# => romdata <= X"01000000";
when 16#00040# => romdata <= X"00000004";
when 16#00041# => romdata <= X"00000000";
when 16#00042# => romdata <= X"00000004";
when 16#00043# => romdata <= X"00000000";
when 16#00044# => romdata <= X"FFFFFFFC";
when 16#00045# => romdata <= X"00000000";
when 16#00046# => romdata <= X"FFFFFFFC";
when 16#00047# => romdata <= X"00000000";
when 16#00048# => romdata <= X"00000000";
when others => romdata <= (others => '-');
end case;
end process;
-- pragma translate_off
bootmsg : report_version
generic map ("ahbrom" & tost(hindex) &
": 32-bit AHB ROM Module, " & tost(bytes/4) & " words, " & tost(abits-2) & " address bits" );
-- pragma translate_on
end;
|
-- Translated to vhdl from verilog module decode_8b10b.v
-- by Kurtis Nishimura, 2015
-- from source obtained at:
--
-- http://asics.chuckbenz.com/decode.v
--
-- Original copyright information:
-- // Chuck Benz, Hollis, NH Copyright (c)2002
-- //
-- // The information and description contained herein is the
-- // property of Chuck Benz.
-- //
-- // Permission is granted for any reuse of this information
-- // and description as long as this copyright notice is
-- // preserved. Modifications may be made as long as this
-- // notice is preserved.
--
-- // per Widmer and Franaszek
--
--
LIBRARY ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.UtilityPkg.all;
entity Decode8b10b is
generic (
GATE_DELAY_G : time := 1 ns
);
port (
clk : in sl;
clkEn : in sl := '1';
rst : in sl := '0';
dataIn : in slv(9 downto 0);
dispIn : in sl;
dataOut : out slv(7 downto 0);
dataKOut : out sl;
dispOut : out sl;
codeErr : out sl;
dispErr : out sl
);
end Decode8b10b;
architecture rtl of Decode8b10b is
signal ai, bi, ci, di, ei, fi, gi, hi, ii, ji : sl;
signal aeqb, ceqd, p22, p40, p04, p13, p31 : sl;
signal disp6a, disp6a2, disp6a0, disp6b : sl;
signal p22bceeqi, p22bncneeqi, p13in, p3li, p13dei : sl;
signal p22aceeqi, p22ancneeqi, p13en, anbnenin : sl;
signal abei, cdei, cndnenin : sl;
signal p22enin, p22ei, p31dnenin, p31i, p31e : sl;
signal compa, compb, compc, compd, compe : sl;
signal ao, bo, co, do, eo : sl;
signal feqg, heqj, fghj22, fghjp13, fghjp31, dispoutRaw : sl;
signal ko, alt7, k28, k28p, fo, go, ho : sl;
signal disp6p, disp6n, disp4p, disp4n : sl;
signal code_err : sl;
signal disp_err : sl;
signal dataOutRaw : slv(7 downto 0);
signal dataKOutRaw : sl;
begin
-- Combinatorial logic
ai <= dataIn(0);
bi <= dataIn(1);
ci <= dataIn(2);
di <= dataIn(3);
ei <= dataIn(4);
ii <= dataIn(5);
fi <= dataIn(6);
gi <= dataIn(7);
hi <= dataIn(8);
ji <= dataIn(9);
aeqb <= (ai and bi) or (not(ai) and not(bi));
ceqd <= (ci and di) or (not(ci) and not(di));
p22 <= (ai and bi and not(ci) and not(di)) or
(ci and di and not(ai) and not(bi)) or
(not(aeqb) and not(ceqd));
p13 <= (not(aeqb) and not(ci) and not(di)) or
(not(ceqd) and not(ai) and not(bi));
p31 <= (not(aeqb) and ci and di) or
(not(ceqd) and ai and bi);
p40 <= ai and bi and ci and di;
p04 <= not(ai) and not(bi) and not(ci) and not(di);
disp6a <= p31 or (p22 and dispin); -- pos disp if p22 and was pos, or p31.
disp6a2 <= p31 and dispin; -- disp is ++ after 4 bits
disp6a0 <= p13 and not(dispin); -- -- disp after 4 bits
disp6b <= (((ei and ii and not(disp6a0)) or (disp6a and (ei or ii)) or disp6a2 or
(ei and ii and di)) and (ei or ii or di));
-- The 5B/6B decoding special cases where ABCDE != abcde
p22bceeqi <= p22 and bi and ci when (ei = ii) else '0';
p22bncneeqi <= p22 and not(bi) and not(ci) when (ei = ii) else '0';
p13in <= p13 and not(ii);
p31i <= p31 and ii;
p13dei <= p13 and di and ei and ii;
p22aceeqi <= p22 and ai and ci when (ei = ii) else '0';
p22ancneeqi <= p22 and not(ai) and not(ci) when (ei = ii) else '0';
p13en <= p13 and not(ei);
anbnenin <= not(ai) and not(bi) and not(ei) and not(ii);
abei <= ai and bi and ei and ii;
cdei <= ci and di and ei and ii;
cndnenin <= not(ci) and not(di) and not(ei) and not(ii);
-- non-zero disparity cases:
p22enin <= p22 and not(ei) and not(ii);
p22ei <= p22 and ei and ii;
p31dnenin <= p31 and not(di) and not(ei) and not(ii);
p31e <= p31 and ei;
compa <= p22bncneeqi or p31i or p13dei or p22ancneeqi or
p13en or abei or cndnenin ;
compb <= p22bceeqi or p31i or p13dei or p22aceeqi or
p13en or abei or cndnenin ;
compc <= p22bceeqi or p31i or p13dei or p22ancneeqi or
p13en or anbnenin or cndnenin ;
compd <= p22bncneeqi or p31i or p13dei or p22aceeqi or
p13en or abei or cndnenin ;
compe <= p22bncneeqi or p13in or p13dei or p22ancneeqi or
p13en or anbnenin or cndnenin ;
ao <= ai xor compa;
bo <= bi xor compb;
co <= ci xor compc;
do <= di xor compd;
eo <= ei xor compe;
feqg <= (fi and gi) or (not(fi) and not(gi));
heqj <= (hi and ji) or (not(hi) and not(ji));
fghj22 <= (fi and gi and not(hi) and not(ji)) or
(not(fi) and not(gi) and hi and ji) or
(not(feqg) and not(heqj));
fghjp13 <= (not(feqg) and not(hi) and not(ji)) or
(not(heqj) and not(fi) and not(gi));
fghjp31 <= ( not(feqg) and hi and ji) or
(not(heqj) and fi and gi);
dispoutRaw <= (fghjp31 or (disp6b and fghj22) or (hi and ji)) and (hi or ji);
ko <= ( (ci and di and ei and ii) or (not(ci) and not(di) and not(ei) and not(ii)) or
(p13 and not(ei) and ii and gi and hi and ji) or
(p31 and ei and not(ii) and not(gi) and not(hi) and not(ji)));
alt7 <= (fi and not(gi) and not(hi) and -- 1000 cases, where disp6b is 1
((dispin and ci and di and not(ei) and not(ii)) or ko or
(dispin and not(ci) and di and not(ei) and not(ii)))) or
(not(fi) and gi and hi and -- 0111 cases, where disp6b is 0
((not(dispin) and not(ci) and not(di) and ei and ii) or ko or
(not(dispin) and ci and not(di) and ei and ii)));
k28 <= (ci and di and ei and ii) or not(ci or di or ei or ii);
-- k28 with positive disp into fghi - .1, .2, .5, and .6 special cases
k28p <= not(ci or di or ei or ii);
fo <= (ji and not(fi) and (hi or not(gi) or k28p)) or
(fi and not(ji) and (not(hi) or gi or not(k28p))) or
(k28p and gi and hi) or
(not(k28p) and not(gi) and not(hi));
go <= (ji and not(fi) and (hi or not(gi) or not(k28p))) or
(fi and not(ji) and (not(hi) or gi or k28p)) or
(not(k28p) and gi and hi) or
(k28p and not(gi) and not(hi));
ho <= ((ji xor hi) and not((not(fi) and gi and not(hi) and ji and not(k28p)) or (not(fi) and gi and hi and not(ji) and k28p) or
(fi and not(gi) and not(hi) and ji and not(k28p)) or (fi and not(gi) and hi and not(ji) and k28p))) or
(not(fi) and gi and hi and ji) or (fi and not(gi) and not(hi) and not(ji));
disp6p <= (p31 and (ei or ii)) or (p22 and ei and ii);
disp6n <= (p13 and not(ei and ii)) or (p22 and not(ei) and not(ii));
disp4p <= fghjp31;
disp4n <= fghjp13;
code_err <= p40 or p04 or (fi and gi and hi and ji) or (not(fi) and not(gi) and not(hi) and not(ji)) or
(p13 and not(ei) and not(ii)) or (p31 and ei and ii) or
(ei and ii and fi and gi and hi) or (not(ei) and not(ii) and not(fi) and not(gi) and not(hi)) or
(ei and not(ii) and gi and hi and ji) or (not(ei) and ii and not(gi) and not(hi) and not(ji)) or
(not(p31) and ei and not(ii) and not(gi) and not(hi) and not(ji)) or
(not(p13) and not(ei) and ii and gi and hi and ji) or
(((ei and ii and not(gi) and not(hi) and not(ji)) or
(not(ei) and not(ii) and gi and hi and ji)) and
not((ci and di and ei) or (not(ci) and not(di) and not(ei)))) or
(disp6p and disp4p) or (disp6n and disp4n) or
(ai and bi and ci and not(ei) and not(ii) and ((not(fi) and not(gi)) or fghjp13)) or
(not(ai) and not(bi) and not(ci) and ei and ii and ((fi and gi) or fghjp31)) or
(fi and gi and not(hi) and not(ji) and disp6p) or
(not(fi) and not(gi) and hi and ji and disp6n) or
(ci and di and ei and ii and not(fi) and not(gi) and not(hi)) or
(not(ci) and not(di) and not(ei) and not(ii) and fi and gi and hi) ;
dataKOutRaw <= ko;
dataOutRaw(7) <= ho;
dataOutRaw(6) <= go;
dataOutRaw(5) <= fo;
dataOutRaw(4) <= eo;
dataOutRaw(3) <= do;
dataOutRaw(2) <= co;
dataOutRaw(1) <= bo;
dataOutRaw(0) <= ao;
-- my disp err fires for any legal codes that violate disparity, may fire for illegal codes
disp_err <= ((dispin and disp6p) or (disp6n and not(dispin)) or
(dispin and not(disp6n) and fi and gi) or
(dispin and ai and bi and ci) or
(dispin and not(disp6n) and disp4p) or
(not(dispin) and not(disp6p) and not(fi) and not(gi)) or
(not(dispin) and not(ai) and not(bi) and not(ci)) or
(not(dispin) and not(disp6p) and disp4n) or
(disp6p and disp4p) or (disp6n and disp4n)) ;
process(clk) begin
if rising_edge(clk) then
if rst = '1' then
dataOut <= (others => '0');
dataKOut <= '0';
dispOut <= '0';
codeErr <= '0';
dispErr <= '0';
elsif clkEn = '1' then
dataOut <= dataOutRaw;
dataKOut <= dataKOutRaw;
dispOut <= dispoutRaw;
codeErr <= code_err;
dispErr <= disp_err;
end if;
end if;
end process;
end rtl;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: rgmii
-- File: rgmii.vhd
-- Author: Fredrik Ringhage - Aeroflex Gaisler
-- Description: GMII to RGMII interface
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library gaisler;
use gaisler.net.all;
use gaisler.misc.all;
library grlib;
use grlib.config_types.all;
use grlib.config.all;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
use techmap.allclkgen.all;
library eth;
use eth.grethpkg.all;
entity rgmii is
generic (
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
tech : integer := 0;
gmii : integer := 0;
debugmem : integer := 0;
abits : integer := 8;
no_clk_mux : integer := 0;
pirq : integer := 0;
use90degtxclk : integer := 0
);
port (
rstn : in std_ulogic;
gmiii : out eth_in_type;
gmiio : in eth_out_type;
rgmiii : in eth_in_type;
rgmiio : out eth_out_type;
-- APB Status bus
apb_clk : in std_logic;
apb_rstn : in std_logic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type
);
end ;
architecture rtl of rgmii is
constant REVISION : integer := 1;
constant pconfig : apb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_RGMII, 0, REVISION, pirq),
1 => apb_iobar(paddr, pmask));
type status_vector_type is array(1 downto 0) of std_logic_vector(15 downto 0);
type rgmiiregs is record
clk25_wrap : unsigned(5 downto 0);
clk25_first_edge : unsigned(5 downto 0);
clk25_second_edge : unsigned(5 downto 0);
clk2_5_wrap : unsigned(5 downto 0);
clk2_5_first_edge : unsigned(5 downto 0);
clk2_5_second_edge : unsigned(5 downto 0);
irq : std_logic_vector(15 downto 0); -- interrupt
mask : std_logic_vector(15 downto 0); -- interrupt enable
clkedge : std_logic_vector(23 downto 0);
rxctrl_q1_delay : std_logic_vector(1 downto 0);
rxctrl_q2_delay : std_logic_vector(1 downto 0);
rxctrl_q1_sel : std_logic;
rxctrl_delay : std_logic;
rxctrl_c_delay : std_logic;
status_vector : status_vector_type;
end record;
-- Global signal
signal vcc, gnd : std_ulogic;
signal tx_en, tx_ctl : std_ulogic;
signal txd : std_logic_vector(7 downto 0);
signal rxd, rxd_pre, rxd_int, rxd_int0, rxd_int1, rxd_int2,rxd_q1,rxd_q2 : std_logic_vector(7 downto 0);
signal rx_clk, nrx_clk : std_ulogic;
signal rx_dv, rx_dv_pre, rx_dv_int, rx_dv0 , rx_ctl, rx_ctl_pre, rx_ctl_int, rx_ctl0, rx_error : std_logic;
signal rx_dv_int0, rx_dv_int1, rx_dv_int2 : std_logic;
signal rx_ctl_int0, rx_ctl_int1, rx_ctl_int2 : std_logic;
signal clk25i, clk25ni, clk2_5i, clk2_5ni : std_ulogic;
signal txp, txn, txp_sync, txn_sync, tx_clk_ddr, tx_clk, tx_clki, ntx_clk : std_ulogic;
signal cnt2_5, cnt25 : unsigned(5 downto 0);
signal rsttxclkn,rsttxclk,rsttxclk90n,rsttxclk90 : std_logic;
-- RGMII Inband status signals
signal inbandopt,inbandreq : std_logic;
signal link_status : std_logic;
signal clock_speed : std_logic_vector(1 downto 0);
signal duplex_status : std_logic;
signal false_carrier_ind : std_logic;
signal carrier_ext : std_logic;
signal carrier_ext_error : std_logic;
signal carrier_sense : std_logic;
-- Status signals and Clock domain crossing
signal line_status_vector : std_logic_vector(3 downto 0);
signal status_vector : std_logic_vector(15 downto 0);
signal status_vector_sync : std_logic_vector(15 downto 0);
-- APB and RGMII control register
constant RESET_ALL : boolean := GRLIB_CONFIG_ARRAY(grlib_sync_reset_enable_all) = 1;
-- notech default settings
constant RES : rgmiiregs :=
( clk25_wrap => to_unsigned(4,6), clk25_first_edge => to_unsigned(1,6), clk25_second_edge => to_unsigned(2,6),
clk2_5_wrap => to_unsigned(49,6), clk2_5_first_edge => to_unsigned(23,6), clk2_5_second_edge => to_unsigned(24,6),
irq => (others => '0'), mask => (others => '0'), clkedge => "000000100011100000111000",
rxctrl_q1_delay => (others => '0'), rxctrl_q2_delay => (others => '0'), rxctrl_q1_sel => '0', rxctrl_delay => '0',
rxctrl_c_delay => '0', status_vector => (others => (others => '0')) );
-- Kintex7 settings for KC705 Dev Board
constant RES_kintex7 : rgmiiregs :=
( clk25_wrap => to_unsigned(4,6), clk25_first_edge => to_unsigned(1,6), clk25_second_edge => to_unsigned(2,6),
clk2_5_wrap => to_unsigned(49,6), clk2_5_first_edge => to_unsigned(23,6), clk2_5_second_edge => to_unsigned(24,6),
irq => (others => '0'), mask => (others => '0'), clkedge => "000000100011100000111000",
rxctrl_q1_delay => (others => '0'), rxctrl_q2_delay => (others => '0'), rxctrl_q1_sel => '1', rxctrl_delay => '0',
rxctrl_c_delay => '0', status_vector => (others => (others => '0')) );
-- Spartan6 settings for GR-XC6 Dev Board
constant RES_spartan6 : rgmiiregs :=
( clk25_wrap => to_unsigned(4,6), clk25_first_edge => to_unsigned(1,6), clk25_second_edge => to_unsigned(2,6),
clk2_5_wrap => to_unsigned(49,6), clk2_5_first_edge => to_unsigned(23,6), clk2_5_second_edge => to_unsigned(24,6),
irq => (others => '0'), mask => (others => '0'), clkedge => "000000100011100000111000",
rxctrl_q1_delay => (others => '0'), rxctrl_q2_delay => "01", rxctrl_q1_sel => '1', rxctrl_delay => '0',
rxctrl_c_delay => '0', status_vector => (others => (others => '0')) );
-- Artix7 settings for AC701 Dev Board
constant RES_artix7 : rgmiiregs :=
( clk25_wrap => to_unsigned(4,6), clk25_first_edge => to_unsigned(1,6), clk25_second_edge => to_unsigned(2,6),
clk2_5_wrap => to_unsigned(49,6), clk2_5_first_edge => to_unsigned(23,6), clk2_5_second_edge => to_unsigned(24,6),
irq => (others => '0'), mask => (others => '0'), clkedge => "000000100011100000111000",
rxctrl_q1_delay => (others => '0'), rxctrl_q2_delay => (others => '0'), rxctrl_q1_sel => '1', rxctrl_delay => '0',
rxctrl_c_delay => '1', status_vector => (others => (others => '0')) );
signal r, rin : rgmiiregs;
signal clk_tx_90_n : std_logic;
signal sync_gbit : std_logic;
signal sync_speed : std_logic;
signal cnt2_5_en, cnt25_en : std_logic;
signal clkedge_sync : std_logic_vector(23 downto 0);
signal sync_rxctrl_q1_delay : std_logic_vector(1 downto 0);
signal sync_rxctrl_q2_delay : std_logic_vector(1 downto 0);
signal sync_rxctrl_q1_sel : std_logic;
signal sync_rxctrl_delay : std_logic;
signal sync_rxctrl_c_delay : std_logic;
signal cnt_en : std_logic;
signal clk10_100 : std_logic;
signal clk25_wrap_sync : unsigned(5 downto 0);
signal clk25_first_edge_sync : unsigned(5 downto 0);
signal clk25_second_edge_sync : unsigned(5 downto 0);
signal clk2_5_wrap_sync : unsigned(5 downto 0);
signal clk2_5_first_edge_sync : unsigned(5 downto 0);
signal clk2_5_second_edge_sync : unsigned(5 downto 0);
-- debug signal
signal WMemRgmiioData : std_logic_vector(15 downto 0);
signal RMemRgmiioData : std_logic_vector(15 downto 0);
signal RMemRgmiioAddr : std_logic_vector(9 downto 0);
signal WMemRgmiioAddr : std_logic_vector(9 downto 0);
signal WMemRgmiioWrEn : std_logic;
signal WMemRgmiiiData : std_logic_vector(15 downto 0);
signal RMemRgmiiiData : std_logic_vector(15 downto 0);
signal RMemRgmiiiAddr : std_logic_vector(9 downto 0);
signal WMemRgmiiiAddr : std_logic_vector(9 downto 0);
signal WMemRgmiiiWrEn : std_logic;
signal RMemRgmiiiRead : std_logic;
signal RMemRgmiioRead : std_logic;
begin -- rtl
vcc <= '1'; gnd <= '0';
---------------------------------------------------------------------------------------
-- MDIO path
---------------------------------------------------------------------------------------
gmiii.mdint <= rgmiii.mdint;
gmiii.mdio_i <= rgmiii.mdio_i;
rgmiio.mdio_o <= gmiio.mdio_o;
rgmiio.mdio_oe <= gmiio.mdio_oe;
rgmiio.mdc <= gmiio.mdc;
---------------------------------------------------------------------------------------
-- TX path
---------------------------------------------------------------------------------------
useclkmux0 : if no_clk_mux = 0 generate
process (apb_clk)
begin -- process
if rising_edge(apb_clk) then
clk25i <= not clk25i;
if cnt2_5 = "001001" then cnt2_5 <= "000000"; clk2_5i <= not clk2_5i;
else cnt2_5 <= cnt2_5 + 1; end if;
if apb_rstn = '0' then clk25i <= '0'; clk2_5i <= '0'; cnt2_5 <= "000000"; end if;
end if;
end process;
notecclkmux : if (has_clkmux(tech) = 0) generate
tx_clki <= rgmiii.gtx_clk when ((gmii = 1) and (gmiio.gbit = '1')) else
clk25i when gmiio.speed = '1' else clk2_5i;
end generate;
tecclkmux : if (has_clkmux(tech) = 1) generate
-- Select 2.5 or 25 Mhz clockL
clkmux10_100 : clkmux generic map (tech => tech) port map (clk2_5i,clk25i,gmiio.speed,clk10_100);
clkmux1000 : clkmux generic map (tech => tech) port map (clk10_100,rgmiii.gtx_clk,gmiio.gbit,tx_clki);
end generate;
clkbuf0: techbuf generic map (buftype => 2, tech => tech)
port map (i => tx_clki, o => tx_clk);
end generate;
noclkmux0 : if no_clk_mux = 1 generate
-- Generate transmit clocks.
tx_clk <= rgmiii.gtx_clk;
-- CDC
syncreg7 : syncreg port map (tx_clk, gmiio.gbit , sync_gbit );
syncreg8 : syncreg port map (tx_clk, gmiio.speed, sync_speed );
syncreg_clkedge : for i in 0 to r.clkedge'length-1 generate
syncreg9 : syncreg port map (tx_clk, r.clkedge(i), clkedge_sync(i));
end generate;
syncreg_clk25_wrap_sync : for i in 0 to r.clk25_wrap'length-1 generate
syncreg_clk25_wrap_sync : syncreg port map (tx_clk, r.clk25_wrap(i), clk25_wrap_sync(i));
end generate;
syncreg_clk25_first_edge : for i in 0 to r.clk25_first_edge'length-1 generate
syncreg_clk25_first_edge : syncreg port map (tx_clk, r.clk25_first_edge(i), clk25_first_edge_sync(i));
end generate;
syncreg_clk25_second_edge : for i in 0 to r.clk25_second_edge'length-1 generate
syncreg_clk25_second_edge : syncreg port map (tx_clk, r.clk25_second_edge(i), clk25_second_edge_sync(i));
end generate;
syncreg_clk2_5_wrap_sync : for i in 0 to r.clk2_5_wrap'length-1 generate
syncreg_clk2_5_wrap_sync : syncreg port map (tx_clk, r.clk2_5_wrap(i), clk2_5_wrap_sync(i));
end generate;
syncreg_clk2_5_first_edge : for i in 0 to r.clk2_5_first_edge'length-1 generate
syncreg_clk2_5_first_edge : syncreg port map (tx_clk, r.clk2_5_first_edge(i), clk2_5_first_edge_sync(i));
end generate;
syncreg_clk2_5_second_edge : for i in 0 to r.clk2_5_second_edge'length-1 generate
syncreg_clk2_5_second_edge : syncreg port map (tx_clk, r.clk2_5_second_edge(i), clk2_5_second_edge_sync(i));
end generate;
process (tx_clk)
begin -- process
if rising_edge(tx_clk) then
if cnt25 >= clk25_wrap_sync then
cnt25 <= to_unsigned(0,cnt25'length);
cnt25_en <= '1';
else
cnt25_en <= '0';
cnt25 <= cnt25 + 1;
end if;
if (cnt25 >= clk25_wrap_sync) then
clk25ni <= clkedge_sync(0);
clk25i <= clkedge_sync(1);
elsif (cnt25 = clk25_first_edge_sync) then
clk25ni <= clkedge_sync(2);
clk25i <= clkedge_sync(3);
elsif (cnt25 = clk25_second_edge_sync) then
clk25ni <= clkedge_sync(4);
clk25i <= clkedge_sync(5);
end if;
if cnt2_5 >= clk2_5_wrap_sync then
cnt2_5 <= to_unsigned(0,cnt2_5'length);
cnt2_5_en <= '1';
else
cnt2_5 <= cnt2_5 + 1;
cnt2_5_en <= '0';
end if;
if (cnt2_5 >= clk2_5_wrap_sync) then
clk2_5ni <= clkedge_sync(8);
clk2_5i <= clkedge_sync(9);
elsif (cnt25 = clk2_5_first_edge_sync) then
clk2_5ni <= clkedge_sync(10);
clk2_5i <= clkedge_sync(11);
elsif (cnt2_5 = clk2_5_second_edge_sync) then
clk2_5ni <= clkedge_sync(12);
clk2_5i <= clkedge_sync(13);
end if;
if rsttxclkn = '0' then
cnt2_5_en <= '0'; cnt25_en <= '0'; clk25i <= '0'; clk25ni <= '0';
clk2_5i <= '0'; clk2_5ni <= '0'; cnt2_5 <= to_unsigned(0,cnt2_5'length);
cnt25 <= to_unsigned(0,cnt25'length);
end if;
end if;
end process;
end generate;
ntx_clk <= not tx_clk;
gmiii.gtx_clk <= tx_clk;
gmiii.tx_clk <= tx_clk;
noclkmux1 : if no_clk_mux = 1 generate
cnt_en <= '1' when ((gmii = 1) and (sync_gbit = '1')) else
cnt25_en when sync_speed = '1' else cnt2_5_en;
end generate;
useclkmux1 : if no_clk_mux = 0 generate
cnt_en <= '1';
end generate;
gmiii.tx_dv <= cnt_en when gmiio.tx_en = '1' else '1';
-- Generate RGMII control signal and check data rate
process (tx_clk)
begin -- process
if rising_edge(tx_clk) then
if (gmii = 1) and (sync_gbit = '1') then
txd(7 downto 0) <= gmiio.txd(7 downto 0);
else
txd(3 downto 0) <= gmiio.txd(3 downto 0);
txd(7 downto 4) <= gmiio.txd(3 downto 0);
end if;
tx_en <= gmiio.tx_en;
tx_ctl <= gmiio.tx_en xor gmiio.tx_er;
end if;
if (gmii = 1) and (sync_gbit = '1') then
txp <= clkedge_sync(17);
txn <= clkedge_sync(16);
else
if sync_speed = '1' then
txp <= clk25ni;
txn <= clk25i;
else
txp <= clk2_5ni;
txn <= clk2_5i;
end if;
end if;
end process;
clk_tx_rst : rstgen
generic map(syncin => 1, syncrst => 1)
port map(rstn, tx_clk, vcc, rsttxclkn, open);
rsttxclk <= not rsttxclkn;
-- DDR outputs
rgmii_txd : for i in 0 to 3 generate
ddr_oreg0 : ddr_oreg generic map (tech, arch => 1)
port map (q => rgmiio.txd(i), c1 => tx_clk, c2 => ntx_clk, ce => vcc,
d1 => txd(i), d2 => txd(i+4), r => rsttxclk, s => gnd);
end generate;
rgmii_tx_ctl : ddr_oreg generic map (tech, arch => 1)
port map (q => rgmiio.tx_en, c1 => tx_clk, c2 => ntx_clk, ce => vcc,
d1 => tx_en, d2 => tx_ctl, r => rsttxclk, s => gnd);
no_clk_mux1 : if no_clk_mux = 1 generate
use90degtxclk1 : if use90degtxclk = 1 generate
clk_tx90_rst : rstgen
generic map(syncin => 1, syncrst => 1)
port map(rstn, rgmiii.tx_clk_90, vcc, rsttxclk90n, open);
rsttxclk90 <= not rsttxclk90n;
clk_tx_90_n <= not rgmiii.tx_clk_90;
syncreg_txp : syncreg port map (rgmiii.tx_clk_90, txp, txp_sync);
syncreg_txn : syncreg port map (rgmiii.tx_clk_90, txn, txn_sync);
rgmii_tx_clk : ddr_oreg generic map (tech, arch => 1)
port map (q => tx_clk_ddr, c1 => rgmiii.tx_clk_90, c2 => clk_tx_90_n, ce => vcc,
d1 => txp_sync, d2 => txn_sync, r => rsttxclk90, s => gnd);
end generate;
use90degtxclk0 : if use90degtxclk = 0 generate
rgmii_tx_clk : ddr_oreg generic map (tech, arch => 1)
port map (q => tx_clk_ddr, c1 => tx_clk, c2 => ntx_clk, ce => vcc,
d1 => txp, d2 => txn, r => rsttxclk, s => gnd);
end generate;
end generate;
no_clk_mux0 : if no_clk_mux = 0 generate
rgmii_tx_clk : ddr_oreg generic map (tech, arch => 1)
port map (q => tx_clk_ddr, c1 => tx_clk, c2 => ntx_clk, ce => vcc,
d1 => '1', d2 => '0', r => rsttxclk, s => gnd);
end generate;
rgmiio.tx_er <= '0';
rgmiio.tx_clk <= tx_clk_ddr;
rgmiio.reset <= rstn;
rgmiio.gbit <= gmiio.gbit;
rgmiio.speed <= gmiio.speed when (gmii = 1) else '0';
-- Not used in RGMII mode
rgmiio.txd(7 downto 4) <= (others => '0');
---------------------------------------------------------------------------------------
-- RX path
---------------------------------------------------------------------------------------
-- CDC (RX Control signal)
syncreg_q1_delay : for i in 0 to r.rxctrl_q1_delay'length-1 generate
syncreg0 : syncreg port map (rx_clk, r.rxctrl_q1_delay(i), sync_rxctrl_q1_delay(i));
end generate;
syncreg_q2_delay : for i in 0 to r.rxctrl_q2_delay'length-1 generate
syncreg1 : syncreg port map (rx_clk, r.rxctrl_q2_delay(i) , sync_rxctrl_q2_delay(i));
end generate;
syncreg_q1_sel : syncreg port map (rx_clk, r.rxctrl_q1_sel, sync_rxctrl_q1_sel);
syncreg_delay_sel : syncreg port map (rx_clk, r.rxctrl_delay, sync_rxctrl_delay);
syncreg_delay_c_sel : syncreg port map (rx_clk, r.rxctrl_c_delay, sync_rxctrl_c_delay);
-- Rx Clocks
rx_clk <= rgmiii.rx_clk;
nrx_clk <= not rgmiii.rx_clk;
-- DDR inputs
rgmii_rxd : for i in 0 to 3 generate
ddr_ireg0 : ddr_ireg generic map (tech, arch => 1)
port map (q1 => rxd_pre(i), q2 => rxd_pre(i+4), c1 => rx_clk, c2 => nrx_clk,
ce => vcc, d => rgmiii.rxd(i), r => gnd, s => gnd);
process (rx_clk)
begin
if rising_edge(rx_clk) then
rxd_int <= rxd_pre;
rxd_int0(i) <= rxd_int(i);
rxd_int0(i+4) <= rxd_int(i+4);
rxd_int1(i) <= rxd_int0(i);
rxd_int1(i+4) <= rxd_int0(i+4);
rxd_int2(i) <= rxd_int1(i);
rxd_int2(i+4) <= rxd_int1(i+4);
end if;
end process;
end generate;
rgmii_rxd0 : for i in 0 to 3 generate
process (rx_clk)
begin
if (sync_rxctrl_q1_delay = "00") then
if (sync_rxctrl_delay = '1') then
rxd_q1(i) <= rxd_int(i+4);
else
rxd_q1(i) <= rxd_int(i);
end if;
elsif (sync_rxctrl_q1_delay = "01") then
rxd_q1(i) <= rxd_int0(i);
elsif (sync_rxctrl_q1_delay = "10") then
rxd_q1(i) <= rxd_int1(i);
else
rxd_q1(i) <= rxd_int2(i);
end if;
end process;
end generate;
rgmii_rxd1 : for i in 4 to 7 generate
process (rx_clk)
begin
if (sync_rxctrl_q2_delay = "00") then
if (sync_rxctrl_delay = '1') then
rxd_q2(i) <= rxd_int0(i-4);
else
rxd_q2(i) <= rxd_int(i);
end if;
elsif (sync_rxctrl_q2_delay = "01") then
rxd_q2(i) <= rxd_int0(i);
elsif (sync_rxctrl_q2_delay = "10") then
rxd_q2(i) <= rxd_int1(i);
else
rxd_q2(i) <= rxd_int2(i);
end if;
end process;
end generate;
rxd(3 downto 0) <= rxd_q1(3 downto 0) when (sync_rxctrl_q1_sel = '0') else rxd_q2(7 downto 4);
rxd(7 downto 4) <= rxd_q2(7 downto 4) when (sync_rxctrl_q1_sel = '0') else rxd_q1(3 downto 0);
ddr_dv0 : ddr_ireg generic map (tech, arch => 1)
port map (q1 => rx_dv_pre, q2 => rx_ctl_pre, c1 => rx_clk, c2 => nrx_clk,
ce => vcc, d => rgmiii.rx_dv, r => gnd, s => gnd);
process (rx_clk)
begin
if rising_edge(rx_clk) then
rx_ctl_int <= rx_ctl_pre;
rx_dv_int <= rx_dv_pre;
rx_ctl_int0 <= rx_ctl_int;
rx_ctl_int1 <= rx_ctl_int0;
rx_ctl_int2 <= rx_ctl_int1;
rx_dv_int0 <= rx_dv_int;
rx_dv_int1 <= rx_dv_int0;
rx_dv_int2 <= rx_dv_int2;
end if;
end process;
process (rx_clk)
begin
if (sync_rxctrl_q1_delay = "00") then
--rx_dv0 <= rx_dv_int;
if (sync_rxctrl_c_delay = '1') then
rx_dv0 <= rx_ctl_int;
else
rx_dv0 <= rx_dv_int;
end if;
elsif (sync_rxctrl_q1_delay = "01") then
rx_dv0 <= rx_dv_int0;
elsif (sync_rxctrl_q1_delay = "10") then
rx_dv0 <= rx_dv_int1;
else
rx_dv0 <= rx_dv_int2;
end if;
if (sync_rxctrl_q2_delay = "00") then
--rx_ctl0 <= rx_ctl_int;
if (sync_rxctrl_c_delay = '1') then
rx_ctl0 <= rx_dv_int0;
else
rx_ctl0 <= rx_ctl_int;
end if;
elsif (sync_rxctrl_q2_delay = "01") then
rx_ctl0 <= rx_ctl_int0;
elsif (sync_rxctrl_q2_delay = "10") then
rx_ctl0 <= rx_ctl_int1;
else
rx_ctl0 <= rx_ctl_int2;
end if;
end process;
rx_dv <= rx_dv0 when (sync_rxctrl_q1_sel = '0') else rx_ctl0;
rx_ctl <= rx_ctl0 when (sync_rxctrl_q1_sel = '0') else rx_dv0;
-- Decode GMII error signal
rx_error <= rx_dv xor rx_ctl;
-- Enable inband status registers during Interframe Gap
inbandopt <= not ( rx_dv or rx_error );
inbandreq <= rx_error and not rx_dv;
-- Sample RGMII inband information
process (rx_clk)
begin
if rising_edge(rx_clk) then
if (inbandopt = '1') then
link_status <= rxd(0);
clock_speed <= rxd(2 downto 1);
duplex_status <= rxd(3);
end if;
if (inbandreq = '1') then
if (rxd = x"0E") then false_carrier_ind <= '1'; else false_carrier_ind <= '0'; end if;
if (rxd = x"0F") then carrier_ext <= '1'; else carrier_ext <= '0'; end if;
if (rxd = x"1F") then carrier_ext_error <= '1'; else carrier_ext_error <= '0'; end if;
if (rxd = x"FF") then carrier_sense <= '1'; else carrier_sense <= '0'; end if;
end if;
end if;
end process;
-- GMII output
gmiii.rxd <= rxd;
gmiii.rx_dv <= rx_dv;
gmiii.rx_er <= rx_error;
gmiii.rx_clk <= rx_clk;
gmiii.rx_col <= '0';
gmiii.rx_crs <= rx_dv;
gmiii.rmii_clk <= '0';
gmiii.rx_en <= '1';
-- GMII output controlled via generics
gmiii.edclsepahb <= '0';
gmiii.edcldisable <= '0';
gmiii.phyrstaddr <= (others => '0');
gmiii.edcladdr <= (others => '0');
---------------------------------------------------------------------------------------
-- APB Section
---------------------------------------------------------------------------------------
apbo.pindex <= pindex;
apbo.pconfig <= pconfig;
-- Status Register
status_vector_sync(15) <= '1' when (no_clk_mux = 1) else '0';
status_vector_sync(14) <= '1' when (debugmem = 1 ) else '0';
status_vector_sync(13) <= '1' when (gmii = 1 ) else '0';
status_vector_sync(12 downto 10) <= (others => '0');
status_vector_sync(9) <= gmiio.gbit;
status_vector_sync(8) <= gmiio.speed;
status_vector_sync(7) <= carrier_sense;
status_vector_sync(6) <= carrier_ext_error;
status_vector_sync(5) <= carrier_ext;
status_vector_sync(4) <= false_carrier_ind;
status_vector_sync(3) <= duplex_status;
status_vector_sync(2) <= clock_speed(1);
status_vector_sync(1) <= clock_speed(0);
status_vector_sync(0) <= link_status;
-- CDC clock domain crossing
syncreg_status : for i in 0 to status_vector'length-1 generate
syncreg3 : syncreg port map (tx_clk, status_vector_sync(i), status_vector(i));
end generate;
rgmiiapb : process(apb_rstn, r, apbi, RMemRgmiiiData, RMemRgmiiiRead, RMemRgmiioRead, status_vector )
variable rdata : std_logic_vector(31 downto 0);
variable paddress : std_logic_vector(7 downto 2);
variable v : rgmiiregs;
begin
v := r;
paddress := (others => '0');
paddress(abits-1 downto 2) := apbi.paddr(abits-1 downto 2);
rdata := (others => '0');
v.status_vector(1) := r.status_vector(0);
v.status_vector(0) := status_vector;
-- read/write registers
if (apbi.psel(pindex) and apbi.penable and (not apbi.pwrite)) = '1' then
case paddress(7 downto 2) is
when "000000" =>
rdata(15 downto 0) := r.status_vector(0);
when "000001" =>
rdata(15 downto 0) := r.irq;
v.irq := (others => '0'); -- Interrupt is clear on read
when "000010" =>
rdata(15 downto 0) := r.mask;
when "000011" =>
rdata(5 downto 0) := std_logic_vector(r.clk25_wrap);
when "000100" =>
rdata(5 downto 0) := std_logic_vector(r.clk25_first_edge);
when "000101" =>
rdata(5 downto 0) := std_logic_vector(r.clk25_second_edge);
when "000110" =>
rdata(5 downto 0) := std_logic_vector(r.clk2_5_wrap);
when "000111" =>
rdata(5 downto 0) := std_logic_vector(r.clk2_5_first_edge);
when "001000" =>
rdata(5 downto 0) := std_logic_vector(r.clk2_5_second_edge);
when "001001" =>
rdata(23 downto 0) := r.clkedge;
when "001010" =>
rdata(1 downto 0) := v.rxctrl_q2_delay;
when "001011" =>
rdata(1 downto 0) := v.rxctrl_q1_delay;
when "001100" =>
rdata(0) := v.rxctrl_q1_sel;
when "001101" =>
rdata(0) := v.rxctrl_delay;
when "001110" =>
rdata(0) := v.rxctrl_c_delay;
when others =>
null;
end case;
end if;
if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
case paddress(7 downto 2) is
when "000000" =>
null;
when "000001" =>
null;
when "000010" =>
v.mask := apbi.pwdata(15 downto 0);
when "000011" =>
v.clk25_wrap := unsigned(apbi.pwdata(5 downto 0));
when "000100" =>
v.clk25_first_edge := unsigned(apbi.pwdata(5 downto 0));
when "000101" =>
v.clk25_second_edge := unsigned(apbi.pwdata(5 downto 0));
when "000110" =>
v.clk2_5_wrap := unsigned(apbi.pwdata(5 downto 0));
when "000111" =>
v.clk2_5_first_edge := unsigned(apbi.pwdata(5 downto 0));
when "001000" =>
v.clk2_5_second_edge := unsigned(apbi.pwdata(5 downto 0));
when "001001" =>
v.clkedge := apbi.pwdata(23 downto 0);
when "001010" =>
v.rxctrl_q2_delay := apbi.pwdata(1 downto 0);
when "001011" =>
v.rxctrl_q1_delay := apbi.pwdata(1 downto 0);
when "001100" =>
v.rxctrl_q1_sel := apbi.pwdata(0);
when "001101" =>
v.rxctrl_delay := apbi.pwdata(0);
when "001110" =>
v.rxctrl_c_delay := apbi.pwdata(0);
when others =>
null;
end case;
end if;
-- Check interrupts
for i in 0 to r.status_vector'length-1 loop
if ((r.status_vector(0)(i) xor r.status_vector(1)(i)) and r.mask(i)) = '1' then
v.irq(i) := '1';
end if;
end loop;
-- reset operation
if (not RESET_ALL) and (apb_rstn = '0') then
if (tech = kintex7) then
v := RES_kintex7;
elsif (tech = spartan6) then
v := RES_spartan6;
elsif (tech = artix7) then
v := RES_artix7;
else
v := RES;
end if;
end if;
-- update registers
rin <= v;
-- drive outputs
if apbi.psel(pindex) = '0' then
apbo.prdata <= (others => '0');
elsif RMemRgmiiiRead = '1' then
apbo.prdata(31 downto 16) <= (others => '0');
apbo.prdata(15 downto 0) <= RMemRgmiiiData;
elsif RMemRgmiioRead = '1' then
apbo.prdata(31 downto 16) <= (others => '0');
apbo.prdata(15 downto 0) <= RMemRgmiioData;
else
apbo.prdata <= rdata;
end if;
apbo.pirq <= (others => '0');
apbo.pirq(pirq) <= orv(v.irq);
end process;
regs : process(apb_clk)
begin
if rising_edge(apb_clk) then
r <= rin;
if RESET_ALL and apb_rstn = '0' then
if (tech = kintex7) then
r <= RES_kintex7;
elsif (tech = spartan6) then
r <= RES_spartan6;
else
r <= RES;
end if;
end if;
end if;
end process;
---------------------------------------------------------------------------------------
-- Debug Mem
---------------------------------------------------------------------------------------
debugmem1 : if (debugmem /= 0) generate
-- Write GMII IN data
process (tx_clk)
begin -- process
if rising_edge(tx_clk) then
WMemRgmiioData(15 downto 0) <= "000" & tx_en & "000" & tx_ctl & txd;
if (tx_en = '1') and ((WMemRgmiioAddr < "0111111110") or (WMemRgmiioAddr = "1111111111")) then
WMemRgmiioAddr <= WMemRgmiioAddr + 1;
WMemRgmiioWrEn <= '1';
else
if (tx_en = '0') then
WMemRgmiioAddr <= (others => '1');
else
WMemRgmiioAddr <= WMemRgmiioAddr;
end if;
WMemRgmiioWrEn <= '0';
end if;
end if;
end process;
-- Read
RMemRgmiioRead <= apbi.paddr(10) and apbi.psel(pindex);
RMemRgmiioAddr <= "00" & apbi.paddr(10-1 downto 2);
gmiii0 : syncram_2p generic map (tech, 10, 16, 1, 0, 0) port map(
apb_clk, RMemRgmiioRead, RMemRgmiioAddr, RMemRgmiioData,
tx_clk, WMemRgmiioWrEn, WMemRgmiioAddr(10-1 downto 0), WMemRgmiioData);
-- Write GMII IN data
process (rx_clk)
begin -- process
if rising_edge(rx_clk) then
WMemRgmiiiData(15 downto 0) <= "000" & rx_dv & "000" & rx_ctl & rxd(7 downto 4) & rxd(3 downto 0);
if ((rx_dv = '1') or (rx_ctl = '1')) and ((WMemRgmiiiAddr < "0111111110") or (WMemRgmiiiAddr = "1111111111")) then
WMemRgmiiiAddr <= WMemRgmiiiAddr + 1;
WMemRgmiiiWrEn <= '1';
else
if (rx_dv = '0') then
WMemRgmiiiAddr <= (others => '1');
else
WMemRgmiiiAddr <= WMemRgmiiiAddr;
end if;
WMemRgmiiiWrEn <= '0';
end if;
end if;
end process;
-- Read
RMemRgmiiiRead <= apbi.paddr(11) and apbi.psel(pindex);
RMemRgmiiiAddr <= "00" & apbi.paddr(10-1 downto 2);
rgmiii0 : syncram_2p generic map (tech, 10, 16, 1, 0, 0) port map(
apb_clk, RMemRgmiiiRead, RMemRgmiiiAddr, RMemRgmiiiData,
rx_clk, WMemRgmiiiWrEn, WMemRgmiiiAddr(10-1 downto 0), WMemRgmiiiData);
end generate;
-- pragma translate_off
bootmsg : report_version
generic map ("rgmii" & tost(pindex) &
": RGMII rev " & tost(REVISION) & ", irq " & tost(pirq));
-- pragma translate_on
end rtl;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity MemoryController is
Generic (
clock_frec : integer := 50 -- MHz
);
Port (
clk :in STD_LOGIC; -- 100MHz/50MHz
reset :in STD_LOGIC;
address_in :in STD_LOGIC_VECTOR (22 downto 0); -- RAM address
mem :in STD_LOGIC; -- if='1' Comienza la operacion
rw :in STD_LOGIC; -- if='0' => lectura if='1' => escritura
data_in :in STD_LOGIC_VECTOR (15 downto 0); -- data que va a ser escrita
data_out :out STD_LOGIC_VECTOR (15 downto 0); -- data que va a ser leida
read_ready_out :out STD_LOGIC; -- if='1' valida data_out
busy :out STD_LOGIC; -- if='1' RAM esta ocupada (mem no tiene efecto)
clock_out :out STD_LOGIC;
ADDRESS :out STD_LOGIC_VECTOR (22 downto 0);
ADV :out STD_LOGIC;
CRE :out STD_LOGIC;
CE :out STD_LOGIC;
OE :out STD_LOGIC;
WE :out STD_LOGIC;
LB :out STD_LOGIC;
UB :out STD_LOGIC;
DATA :inout STD_LOGIC_VECTOR (15 downto 0)
);
end entity MemoryController;
architecture Behavioral of MemoryController is
type state_t is (INIT, IDLE, WRITING, READING); --Estados en los que se encuentra el controlador
signal state : state_t := INIT;
constant clock_period_ns : integer := (1000/clock_frec); -- nanosegundos (50MHz => 20ns, 100MHz => 10ns)
constant init_period_us : integer := 151; -- microsegundos (151 us)
constant init_counter : integer := (init_period_us * 1000 / clock_period_ns); -- 151 microsegundos
constant timing_counter : integer := (80 / clock_period_ns); -- 80 nanosegundos (70ns)
signal counter : integer range 0 to init_counter := 0;
-- Controla la data de entrada a escribir en la RAM
signal writing_out : STD_LOGIC := '0';
signal address_aux : std_logic_vector(22 downto 0) := (others => '0');
signal data_in_aux : std_logic_vector(15 downto 0) := (others => '0');
begin
ADDRESS <= address_aux ;
--Estado y registro de datos
address_process: process (clk, reset)
begin
if reset = '1' then
address_aux <= (others => '0');
data_in_aux <= (others => '0');
elsif rising_edge(clk) then ---elsif (clk'event and clk = 'l') then
if mem = '1' then
address_aux <= address_in;
data_in_aux <= data_in;
end if;
end if;
end process;
--
clock_out <= '0'; -- El control opera asincronicamente
CRE <= '0'; -- El controlador usa la configuracion default
-- Señal auxiliar para poder inicializar correctamente
-- de modo que no quede indefinido su valor antes del primer mem
DATA <= data_in_aux when writing_out='1' else (others => 'Z');
--
-- Señales de control
busy <= '1' when (state = WRITING OR state = READING OR state = INIT) else '0';
ADV <= '1' when state = INIT else '0';
CE <= '0' when (state = WRITING OR state = READING) else '1'; --Habilita o deshabilita el chip
LB <= '0' when (state = WRITING OR state = READING) else '1'; --Habilita o deshabilita el lower byte del bus de datos
UB <= '0' when (state = WRITING OR state = READING) else '1'; --Habilita o deshabilita el upper byte del bus de datos
WE <= '0' when state = WRITING else '1'; --Habilita o deshabilita la operación de escritura
OE <= '0' when state = READING else '1'; --Habilita o deshabilita la salida
writing_out <= '1' when state = WRITING else '0';
-- FSM process
FSM: process (clk, reset)
begin
-- RESET
if reset = '1' then
state <= INIT;
elsif rising_edge(clk) then ---elsif (clk'event and clk = 'l') then
case state is
-- INIT
when INIT =>
read_ready_out <= '0';
data_out <= (others => '0');
if (counter >= init_counter) then
counter <= 0;
state <= IDLE;
else
counter <= counter + 1;
end if;
-- IDLE
when IDLE =>
read_ready_out <= '0';
data_out <= (others => '0');
if mem = '1' then -- Si esta habilitado el controlador, entonces entra en estado de lectura o escritura
if rw = '1' then
state <= WRITING;
else
state <= READING;
end if;
end if;
-- WRITING
when WRITING =>
if (counter >= timing_counter - 1) then
counter <= 0;
state <= IDLE;
else
counter <= counter + 1;
end if;
-- READING
when READING =>
-- En el último ciclo de la cuenta
if (counter = timing_counter - 2) then
data_out <= DATA;
counter <= counter + 1;
-- Adelanto el read_ready_out para leer en el 5to flanco
read_ready_out <= '1';
-- Cuando termina de contar
elsif (counter >= timing_counter - 1) then
counter <= 0;
state <= IDLE;
data_out <= DATA;
read_ready_out <= '0';
else
counter <= counter + 1;
end if;
when others =>
state <= IDLE;
end case;
end if;
end process; -- FSM
end;
|
------------------------------------------------------------------------------------------------------------------------
-- read controller of the fifo
--
-- Copyright (C) 2009 B&R
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Note: A general implementation of a asynchronous fifo which is
-- using a dual port ram. This file is the read controler.
--
------------------------------------------------------------------------------------------------------------------------
-- Version History
------------------------------------------------------------------------------------------------------------------------
-- 2011-09-22 V0.01 mairt first version
-- 2011-10-14 V0.02 zelenkaj element calculation buggy
------------------------------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity fifo_read_ctrl is
generic(N: natural:=4);
port(
clkr, resetr: in std_logic;
w_ptr_in: in std_logic_vector(N downto 0);
rd: in std_logic;
r_empty: out std_logic;
r_full: out std_logic;
r_ptr_out: out std_logic_vector(N downto 0);
r_addr: out std_logic_vector(N-1 downto 0);
r_elements: out std_logic_vector(N-1 downto 0)
);
end fifo_read_ctrl;
architecture gray_arch of fifo_read_ctrl is
signal r_ptr_reg, r_ptr_next: std_logic_vector(N downto 0);
signal w_ptr_reg, w_ptr_next : std_logic_vector(N downto 0) := (others => '0');
signal gray1, bin, bin1: std_logic_vector(N downto 0);
signal raddr_all: std_logic_vector(N-1 downto 0);
signal raddr_msb,waddr_msb: std_logic;
signal empty_flag, full_flag: std_logic;
signal r_elements_wr, r_elements_rd, r_elements_diff : std_logic_vector(N downto 0);
signal r_elements_reg, r_elements_next : std_logic_vector(N-1 downto 0);
begin
-- register
process(clkr,resetr)
begin
if (resetr='1') then
r_ptr_reg <= (others=>'0');
--w_ptr_reg <= (others => '0');
r_elements_reg <= (others => '0');
elsif (clkr'event and clkr='1') then
r_ptr_reg <= r_ptr_next;
--w_ptr_reg <= w_ptr_next;
r_elements_reg <= r_elements_next;
end if;
end process;
-- (N+1)-bit Gray counter
bin <= r_ptr_reg xor ('0' & bin(N downto 1));
bin1 <= std_logic_vector(unsigned(bin) + 1);
gray1 <= bin1 xor ('0' & bin1(N downto 1));
-- update read pointer
r_ptr_next <= gray1 when rd='1' and empty_flag='0' else
r_ptr_reg;
-- save write pointer
w_ptr_next <= w_ptr_in;
-- N-bit Gray counter
raddr_msb <= r_ptr_reg(N) xor r_ptr_reg(N-1);
raddr_all <= raddr_msb & r_ptr_reg(N-2 downto 0);
waddr_msb <= w_ptr_in(N) xor w_ptr_in(N-1);
-- check for FIFO read empty
empty_flag <=
'1' when w_ptr_in(N)=r_ptr_reg(N) and
w_ptr_in(N-2 downto 0)=r_ptr_reg(N-2 downto 0) and
raddr_msb = waddr_msb else
'0';
-- check for FIFO read full
full_flag <=
'1' when w_ptr_in(N)/=r_ptr_reg(N) and
w_ptr_in(N-2 downto 0)=r_ptr_reg(N-2 downto 0) and
raddr_msb = waddr_msb else
'0';
-- convert gray value to bin and obtain difference
r_elements_wr <= bin;
r_elements_rd <= w_ptr_in xor ('0' & r_elements_rd(N downto 1));
r_elements_diff <= std_logic_vector(unsigned(r_elements_rd) - unsigned(r_elements_wr));
r_elements_next <= r_elements_diff(r_elements_next'range);
-- output
r_addr <= raddr_all;
r_ptr_out <= r_ptr_reg;
r_elements <= r_elements_reg;
r_empty <= empty_flag;
r_full <= full_flag;
end gray_arch; |
------------------------------------------------------------------------------------------------------------------------
-- read controller of the fifo
--
-- Copyright (C) 2009 B&R
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Note: A general implementation of a asynchronous fifo which is
-- using a dual port ram. This file is the read controler.
--
------------------------------------------------------------------------------------------------------------------------
-- Version History
------------------------------------------------------------------------------------------------------------------------
-- 2011-09-22 V0.01 mairt first version
-- 2011-10-14 V0.02 zelenkaj element calculation buggy
------------------------------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity fifo_read_ctrl is
generic(N: natural:=4);
port(
clkr, resetr: in std_logic;
w_ptr_in: in std_logic_vector(N downto 0);
rd: in std_logic;
r_empty: out std_logic;
r_full: out std_logic;
r_ptr_out: out std_logic_vector(N downto 0);
r_addr: out std_logic_vector(N-1 downto 0);
r_elements: out std_logic_vector(N-1 downto 0)
);
end fifo_read_ctrl;
architecture gray_arch of fifo_read_ctrl is
signal r_ptr_reg, r_ptr_next: std_logic_vector(N downto 0);
signal w_ptr_reg, w_ptr_next : std_logic_vector(N downto 0) := (others => '0');
signal gray1, bin, bin1: std_logic_vector(N downto 0);
signal raddr_all: std_logic_vector(N-1 downto 0);
signal raddr_msb,waddr_msb: std_logic;
signal empty_flag, full_flag: std_logic;
signal r_elements_wr, r_elements_rd, r_elements_diff : std_logic_vector(N downto 0);
signal r_elements_reg, r_elements_next : std_logic_vector(N-1 downto 0);
begin
-- register
process(clkr,resetr)
begin
if (resetr='1') then
r_ptr_reg <= (others=>'0');
--w_ptr_reg <= (others => '0');
r_elements_reg <= (others => '0');
elsif (clkr'event and clkr='1') then
r_ptr_reg <= r_ptr_next;
--w_ptr_reg <= w_ptr_next;
r_elements_reg <= r_elements_next;
end if;
end process;
-- (N+1)-bit Gray counter
bin <= r_ptr_reg xor ('0' & bin(N downto 1));
bin1 <= std_logic_vector(unsigned(bin) + 1);
gray1 <= bin1 xor ('0' & bin1(N downto 1));
-- update read pointer
r_ptr_next <= gray1 when rd='1' and empty_flag='0' else
r_ptr_reg;
-- save write pointer
w_ptr_next <= w_ptr_in;
-- N-bit Gray counter
raddr_msb <= r_ptr_reg(N) xor r_ptr_reg(N-1);
raddr_all <= raddr_msb & r_ptr_reg(N-2 downto 0);
waddr_msb <= w_ptr_in(N) xor w_ptr_in(N-1);
-- check for FIFO read empty
empty_flag <=
'1' when w_ptr_in(N)=r_ptr_reg(N) and
w_ptr_in(N-2 downto 0)=r_ptr_reg(N-2 downto 0) and
raddr_msb = waddr_msb else
'0';
-- check for FIFO read full
full_flag <=
'1' when w_ptr_in(N)/=r_ptr_reg(N) and
w_ptr_in(N-2 downto 0)=r_ptr_reg(N-2 downto 0) and
raddr_msb = waddr_msb else
'0';
-- convert gray value to bin and obtain difference
r_elements_wr <= bin;
r_elements_rd <= w_ptr_in xor ('0' & r_elements_rd(N downto 1));
r_elements_diff <= std_logic_vector(unsigned(r_elements_rd) - unsigned(r_elements_wr));
r_elements_next <= r_elements_diff(r_elements_next'range);
-- output
r_addr <= raddr_all;
r_ptr_out <= r_ptr_reg;
r_elements <= r_elements_reg;
r_empty <= empty_flag;
r_full <= full_flag;
end gray_arch; |
----------------------------------------------------------------------------
-- This file is a part of the LEON VHDL model
-- Copyright (C) 1999 European Space Agency (ESA)
--
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2 of the License, or (at your option) any later version.
--
-- See the file COPYING.LGPL for the full details of the license.
-----------------------------------------------------------------------------
-- Entity: fp
-- File: fp.vhd
-- Author: Jiri Gaisler - ESA/ESTEC
-- Description: Parallel floating-point and co-processor interface
-- The interface allows one execution unit
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use work.config.all;
use work.iface.all;
use work.sparcv8.all;
use work.tech_map.all;
use work.fpulib.all;
-- pragma translate_off
use STD.TEXTIO.all;
use work.debug.all;
-- pragma translate_on
entity fp1eu is
port (
rst : in std_logic; -- Reset
clk : in clkgen_out_type;
xholdn : in std_logic; -- pipeline hold
cpi : in cp_in_type;
cpo : out cp_out_type
);
end;
architecture rtl of fp1eu is
type cpins_type is (none, cpop, load, store);
type pl_ctrl is record -- pipeline control record
cpins : cpins_type; -- CP instruction
rreg1 : std_logic; -- using rs1
rreg2 : std_logic; -- using rs1
rs1d : std_logic; -- rs1 is double (64-bit)
rs2d : std_logic; -- rs2 is double (64-bit)
wreg : std_logic; -- write CP regfile
rdd : std_logic; -- rd is double (64-bit)
wrcc : std_logic; -- write CP condition codes
acsr : std_logic; -- access CP control register
end record;
type unit_status_type is (free, started, ready);
type unit_ctrl is record -- execution unit control record
status : unit_status_type; -- unit status
rs1 : std_logic_vector (4 downto 0); -- destination register
rs2 : std_logic_vector (4 downto 0); -- destination register
rd : std_logic_vector (4 downto 0); -- destination register
rreg1 : std_logic; -- using rs1
rreg2 : std_logic; -- using rs1
rs1d : std_logic; -- rs1 is double (64-bit)
rs2d : std_logic; -- rs2 is double (64-bit)
wreg : std_logic; -- will write CP regfile
rdd : std_logic; -- rd is double (64-bit)
wbok : std_logic; -- ok to write result
wrcc : std_logic; -- will write CP condition codes
rst : std_logic; -- reset register
pc : std_logic_vector (31 downto PCLOW); -- program counter
inst : std_logic_vector (31 downto 0); -- instruction
end record;
type csr_type is record -- CP status register
cc : std_logic_vector (1 downto 0); -- condition codes
aexc : std_logic_vector (4 downto 0); -- exception codes
cexc : std_logic_vector (4 downto 0); -- exception codes
tem : std_logic_vector (4 downto 0); -- trap enable mask
rd : std_logic_vector (1 downto 0); -- rounding mode
tt : std_logic_vector (2 downto 0); -- trap type
end record;
type execstate is (nominal, excpend, exception);
type reg_type is record -- registers clocked with pipeline
start : std_logic; -- start EU
end record;
type regx_type is record -- registers clocked continuously
res : std_logic_vector (63 downto 0); -- write stage result
waddr : std_logic_vector (3 downto 0); -- write stage dest
wren : std_logic_vector (1 downto 0); -- write stage regfile write enable
csr : csr_type; -- co-processor status register
start : std_logic; -- start EU
starty : std_logic; -- start EU
startx : std_logic; -- start EU
holdn : std_logic;
wbok : std_logic; -- ok to write result
state : execstate; -- FP/CP state
end record;
signal vcc, gnd, wb : std_logic;
signal rfi1, rfi2 : rf_cp_in_type;
signal rfo1, rfo2 : rf_cp_out_type;
signal ex, exin, me, mein, wr, wrin : pl_ctrl;
signal r, rin : reg_type;
signal rx, rxin : regx_type;
signal eui : cp_unit_in_type;
signal euo : cp_unit_out_type;
signal eu, euin : unit_ctrl;
function ldcheck (rdin : std_logic_vector; ldd : std_logic; eu : unit_ctrl)
return std_logic is
variable lock : std_logic;
variable rd : std_logic_vector(4 downto 0);
begin
lock := '0'; rd := rdin;
if (eu.status > free) then
if (eu.rdd = '0') then
if ((eu.wreg = '1') and (rd = eu.rd)) or
((eu.rreg1 = '1') and (rd = eu.rs1)) or
((eu.rreg2 = '1') and (rd = eu.rs2))
then lock := '1'; end if;
if (ldd = '1') then
if ((eu.wreg = '1') and ((rd(4 downto 1) & '1') = eu.rd)) or
((eu.rreg1 = '1') and ((rd(4 downto 1) & '1') = eu.rs1)) or
((eu.rreg2 = '1') and ((rd(4 downto 1) & '1') = eu.rs2))
then lock := '1'; end if;
end if;
else
if ((eu.wreg = '1') and (rd(4 downto 1) = eu.rd(4 downto 1))) or
((eu.rreg1 = '1') and (rd(4 downto 1) = eu.rs1(4 downto 1))) or
((eu.rreg2 = '1') and (rd(4 downto 1) = eu.rs2(4 downto 1)))
then lock := '1'; end if;
end if;
end if;
return(lock);
end;
function stcheck (rdin : std_logic_vector; std : std_logic; eu : unit_ctrl)
return std_logic is
variable lock : std_logic;
variable rd : std_logic_vector(4 downto 0);
begin
lock := '0'; rd := rdin;
if (eu.status > free) then
if (eu.rdd = '0') then
if ((eu.wreg = '1') and (rd = eu.rd)) then lock := '1'; end if;
if (std = '1') then
if ((eu.wreg = '1') and ((rd(4 downto 1) & '1') = eu.rd))
then lock := '1'; end if;
end if;
else
if ((eu.wreg = '1') and (rd(4 downto 1) = eu.rd(4 downto 1))) or
((eu.rreg1 = '1') and (rd(4 downto 1) = eu.rs1(4 downto 1))) or
((eu.rreg2 = '1') and (rd(4 downto 1) = eu.rs2(4 downto 1)))
then lock := '1'; end if;
end if;
end if;
return(lock);
end;
function srccheck (rsin : std_logic_vector; dbl : std_logic; eu : unit_ctrl)
return std_logic is
variable lock : std_logic;
variable rs : std_logic_vector(4 downto 0);
begin
lock := '0'; rs := rsin;
if (eu.wreg = '1') and (rs(4 downto 1) = eu.rd(4 downto 1)) then
if ((dbl or eu.rdd) = '1') or (rs(0) = eu.rd(0)) then lock := '1'; end if;
end if;
return(lock);
end;
begin
vcc <= '1'; gnd <= '1';
-- instruction decoding
pipeline : process(cpi, ex, me, wr, eu, euin, r, rx, rfi1, rfi2, rfo1, rfo2,
clk.holdn, xholdn,
euo, rst, wb)
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable opc : std_logic_vector(8 downto 0);
variable stdata : std_logic_vector(31 downto 0);
variable rs1, rs2, rd : std_logic_vector(4 downto 0);
variable ctrl : pl_ctrl;
variable ldlock : std_logic;
variable wren : std_logic_vector(1 downto 0);
variable waddr : std_logic_vector(3 downto 0);
variable rtaddr : std_logic_vector(3 downto 0);
variable wrdata : std_logic_vector(63 downto 0);
variable rtdata : std_logic_vector(63 downto 0);
variable rv : reg_type;
variable rxv : regx_type;
variable euv : unit_ctrl;
variable euiv : cp_unit_in_type;
variable ddep : std_logic;
variable cpexc : std_logic;
variable fpill : std_logic;
variable ccv : std_logic;
variable qne : std_logic;
variable wbv : std_logic;
variable op1 : std_logic_vector (63 downto 0); -- operand1
variable op2 : std_logic_vector (63 downto 0); -- operand2
variable opcode : std_logic_vector (9 downto 0); -- FP opcode
begin
-------------------------------------------------------------
-- decode stage
-------------------------------------------------------------
op := cpi.dinst(31 downto 30);
op3 := cpi.dinst(24 downto 19);
opc := cpi.dinst(13 downto 5);
rs1 := cpi.dinst(18 downto 14);
rs2 := cpi.dinst(4 downto 0);
rd := cpi.dinst(29 downto 25);
rv := r; rxv := rx;
ctrl.cpins := none; ctrl.wreg := '0'; ctrl.rdd := '0';
ctrl.wrcc := '0'; ctrl.acsr := '0'; ldlock := '0';
ctrl.rreg1 := '0'; ctrl.rreg2 := '0';
ctrl.rs1d := '0'; ctrl.rs2d := '0'; fpill := '0';
stdata := (others => '-'); wren := "00"; cpexc := '0';
ccv := '0'; rv.start := '0'; rxv.wbok := '0';
rxv.start := '0';
euv := eu;
if eu.status /= free then qne := '1'; else qne := '0'; end if;
euiv.opcode := cpi.ex.inst(19) & cpi.ex.inst(13 downto 5);
euiv.start := '0'; euiv.load := '0';
euiv.flush := eu.rst or euin.rst;
wbv := '0';
euv.rst := not rst;
if (eu.status = started) and (euo.busy = '0') then
euv.status := ready;
end if;
if (eu.status > free) then ccv := ccv or eu.wrcc; end if;
-- decode CP instructions
case op is
when FMT3 =>
case op3 is
when FPOP1 =>
if rx.state = exception then rxv.state := excpend; rxv.csr.tt := "100";
elsif rx.state = nominal then
ctrl.cpins := cpop; ctrl.wreg := '1';
case opc is
when FMOVS | FABSS | FNEGS => ctrl.rreg2 := '1';
when FITOS | FSTOI => ctrl.rreg2 := '1';
when FITOD | FSTOD => ctrl.rreg2 := '1'; ctrl.rdd := '1';
when FDTOI | FDTOS => ctrl.rreg2 := '1'; ctrl.rs2d := '1';
when FSQRTS => ctrl.rreg2 := '1';
when FSQRTD => ctrl.rreg2 := '1'; ctrl.rs2d := '1'; ctrl.rdd := '1';
when FADDS | FSUBS | FMULS | FDIVS =>
ctrl.rreg1 := '1'; ctrl.rreg2 := '1';
when FADDD | FSUBD | FMULD | FDIVD =>
ctrl.rreg1 := '1'; ctrl.rreg2 := '1'; ctrl.rs1d := '1';
ctrl.rs2d := '1'; ctrl.rdd := '1';
when others => fpill := '1'; -- illegal instuction
end case;
end if;
when FPOP2 =>
if rx.state = exception then rxv.state := excpend; rxv.csr.tt := "100";
elsif rx.state = nominal then
ctrl.cpins := cpop; ctrl.wrcc := '1';
ctrl.rreg1 := '1'; ctrl.rreg2 := '1';
case opc is
when FCMPD | FCMPED =>
ctrl.rs1d := '1'; ctrl.rs2d := '1';
when others => fpill := '1'; -- illegal instuction
end case;
end if;
when others => null;
end case;
if (ex.cpins = load) and ((cpi.ex.annul or cpi.ex.trap) = '0') and
(ex.wreg = '1')
then
if (ctrl.rreg1 = '1') and
(rs1(4 downto 1) = cpi.ex.inst(29 downto 26)) and
(((ctrl.rs1d or ex.rdd) = '1') or (rs1(0) = cpi.ex.inst(25)))
then ldlock := '1'; end if;
if (ctrl.rreg2 = '1') and
(rs2(4 downto 1) = cpi.ex.inst(29 downto 26)) and
(((ctrl.rs2d or ex.rdd) = '1') or (rs2(0) = cpi.ex.inst(25)))
then ldlock := '1'; end if;
end if;
when LDST =>
case op3 is
when LDF | LDDF =>
if rx.state = exception then rxv.state := excpend; rxv.csr.tt := "100";
elsif rx.state = nominal then
ctrl.rdd := op3(1) and op3(0);
ctrl.cpins := load; ctrl.wreg := '1';
-- dst interlock
ldlock := ldlock or ldcheck(rd, ctrl.rdd, euin);
end if;
when STF | STDF =>
-- check for CP register dependencies
if (ex.cpins = load) and ((cpi.ex.annul or cpi.ex.trap) = '0') and
(cpi.ex.cnt = "00") and
((rd = cpi.ex.inst(29 downto 25)) or
((rd(4 downto 1) = cpi.ex.inst(29 downto 26)) and
(ex.rdd = '1')))
then ldlock := '1'; end if;
if rx.state = nominal then
ldlock := ldlock or stcheck(rd, (op3(1) and op3(0)), euin);
end if;
if (ldlock = '0') then ctrl.cpins := store; end if;
when STFSR | LDFSR =>
if (rx.state = exception) and (op3 = LDFSR) then
rxv.state := excpend; rxv.csr.tt := "100";
else
if (ex.cpins = load) and ((cpi.ex.annul or cpi.ex.trap) = '0') and
(cpi.ex.cnt = "00") and (op3 = STFSR) and (ex.acsr = '1')
then ldlock := '1'; end if;
if (rx.state = nominal) then
if (((cpi.ex.annul or cpi.ex.trap) = '0') and (ex.cpins = cpop))
or (eu.status > free)
then ldlock := '1'; end if;
end if;
end if;
if (ldlock = '0') then
ctrl.acsr := '1';
if op3 = STFSR then ctrl.cpins := store;
else ctrl.cpins := load; end if;
end if;
when STDFQ =>
if (rx.state = nominal) then
rxv.state := excpend; rxv.csr.tt := "100";
else ctrl.cpins := store; end if;
when others => null;
end case;
when others => null;
end case;
if ((cpi.flush or cpi.dtrap or cpi.dannul or ldlock) = '1') then
ctrl.cpins := none; ctrl.acsr := '0';
rxv.state := rx.state; rxv.csr.tt := rx.csr.tt;
end if;
if ((cpi.flush or cpi.dtrap or cpi.dannul) = '1') then
ldlock := '0';
end if;
-------------------------------------------------------------
-- execute stage
-------------------------------------------------------------
-- generate regfile addresses
if clk.holdn = '0' then
op := cpi.me.inst(31 downto 30);
rd := cpi.me.inst(29 downto 25);
op3 := cpi.me.inst(24 downto 19);
rs1 := cpi.me.inst(18 downto 14);
rs2 := cpi.me.inst(4 downto 0);
else
op := cpi.ex.inst(31 downto 30);
rd := cpi.ex.inst(29 downto 25);
op3 := cpi.ex.inst(24 downto 19);
rs1 := cpi.ex.inst(18 downto 14);
rs2 := cpi.ex.inst(4 downto 0);
end if;
if (op = LDST) and (op3(2) = '1') then rs1 := rd; end if;
rfi1.rd1addr(3 downto 0) <= rs1(4 downto 1); rfi1.rd2addr(3 downto 0) <= rs2(4 downto 1);
rfi2.rd1addr(3 downto 0) <= rs1(4 downto 1); rfi2.rd2addr(3 downto 0) <= rs2(4 downto 1);
rfi1.ren1 <= '1'; rfi1.ren2 <= '1'; rfi2.ren1 <= '1'; rfi2.ren2 <= '1';
cpo.ldlock <= ldlock;
op1 := rfo1.data1(31 downto 0) & rfo2.data1(31 downto 0);
op2 := rfo1.data2(31 downto 0) & rfo2.data2(31 downto 0);
-- generate store data
if (cpi.ex.inst(20 downto 19) = "10") then -- STDFQ
if (cpi.ex.cnt /= "10") then stdata := eu.pc(31 downto 2) & "00";
else stdata := eu.inst; end if;
elsif ((cpi.ex.inst(25) = '0') and (cpi.ex.cnt /= "10")) then -- STF/STDF
stdata := op1(63 downto 32);
else stdata := op1(31 downto 0); end if;
if (ex.cpins = store) and (ex.acsr = '1') then -- STFSR
stdata := rx.csr.rd & "00" & rx.csr.tem & "000" &
std_logic_vector(FPUVER) & rx.csr.tt & qne & '0' & rx.csr.cc &
rx.csr.aexc & rx.csr.cexc;
end if;
cpo.data <= stdata;
-- check if an execution unit is available
if (ex.cpins = cpop) and (clk.holdn = '1') and (cpi.ex.annul = '0') then
ccv := ccv or ex.wrcc;
if (eu.status = free) or ((eu.status = ready) and (wb = '1')) then
rxv.start := '1';
euiv.start := '1';
if cpi.flush = '0' then euv.status := started; end if;
euv.rd := cpi.ex.inst(29 downto 25);
euv.rs1 := cpi.ex.inst(18 downto 14);
euv.rs2 := cpi.ex.inst(4 downto 0);
euv.wreg := ex.wreg;
euv.rreg1 := ex.rreg1;
euv.rreg2 := ex.rreg2;
euv.rs1d := ex.rs1d;
euv.rs2d := ex.rs2d;
euv.rdd := ex.rdd;
euv.wrcc := ex.wrcc;
else rxv.holdn := '0'; rv.start := '1'; end if;
end if;
if cpi.flush = '1' then
rxv.start := '0'; euiv.start := '0';
end if;
-------------------------------------------------------------
-- memory stage
-------------------------------------------------------------
euiv.load := rx.start or rx.starty;
if (rx.holdn = '0') and (xholdn = '1') and (cpi.flush = '0') and
(euo.busy = '0')
then
euiv.start := not rx.startx;
euiv.opcode := cpi.me.inst(19) & cpi.me.inst(13 downto 5);
end if;
if (rx.holdn = '0') and ((eu.status <= free) or (wb = '1'))
then
euiv.load := rx.starty;
euiv.start := not (rx.starty or rx.startx);
euv.status := started;
euv.rs1 := cpi.me.inst(18 downto 14);
euv.rs2 := cpi.me.inst(4 downto 0);
euv.rd := cpi.me.inst(29 downto 25);
euv.wreg := me.wreg;
euv.rreg1 := me.rreg1;
euv.rreg2 := me.rreg2;
euv.rs1d := me.rs1d;
euv.rs2d := me.rs2d;
euv.rdd := me.rdd;
euv.wrcc := me.wrcc;
euiv.opcode := cpi.me.inst(19) & cpi.me.inst(13 downto 5);
rxv.holdn := '1';
end if;
euiv.start := euiv.start and not cpi.flush;
rxv.starty := euiv.start;
rxv.startx := (rx.startx or euiv.start) and (not clk.holdn) and not cpi.flush;
ccv := ccv or me.wrcc;
if (cpi.flush = '1') or (rx.state /= nominal) then rxv.holdn := '1'; end if;
if clk.holdn = '0' then rxv.wbok := rx.wbok; end if;
if (me.cpins = cpop) and (clk.holdn = '1') then
if ((cpi.flush and not eu.wbok) = '1') then euv.rst := '1';
else rxv.wbok := not cpi.me.annul; end if;
end if;
-- regfile bypass
if (rx.waddr = cpi.me.inst(18 downto 15)) then
if (rx.wren(0) = '1') then op1(63 downto 32) := rx.res(63 downto 32); end if;
if (rx.wren(1) = '1') then op1(31 downto 0) := rx.res(31 downto 0); end if;
end if;
if (rx.waddr = cpi.me.inst(4 downto 1)) then
if (rx.wren(0) = '1') then op2(63 downto 32) := rx.res(63 downto 32); end if;
if (rx.wren(1) = '1') then op2(31 downto 0) := rx.res(31 downto 0); end if;
end if;
-- optionally forward data from write stage
if rfi1.wren = '1' then
if cpi.me.inst(18 downto 15) = rfi1.wraddr(3 downto 0) then
op1(63 downto 32) := rfi1.wrdata(31 downto 0);
end if;
if cpi.me.inst(4 downto 1) = rfi1.wraddr(3 downto 0) then
op2(63 downto 32) := rfi1.wrdata(31 downto 0);
end if;
end if;
if rfi2.wren = '1' then
if cpi.me.inst(18 downto 15) = rfi2.wraddr(3 downto 0) then
op1(31 downto 0) := rfi2.wrdata(31 downto 0);
end if;
if cpi.me.inst(4 downto 1) = rfi2.wraddr(3 downto 0) then
op2(31 downto 0) := rfi2.wrdata(31 downto 0);
end if;
end if;
-- align single operands
if me.rs1d = '0' then
if cpi.me.inst(14) = '0' then op1 := op1(63 downto 32) & op1(63 downto 32);
else op1 := op1(31 downto 0) & op1(31 downto 0); end if;
end if;
if me.rs2d = '0' then
if cpi.me.inst(0) = '0' then op2 := op2(63 downto 32) & op2(63 downto 32);
else op2 := op2(31 downto 0) & op2(31 downto 0); end if;
end if;
-- drive EU operand inputs
euiv.op1 := op1; euiv.op2 := op2;
cpo.holdn <= rx.holdn;
-------------------------------------------------------------
-- write stage
-------------------------------------------------------------
wrdata := cpi.lddata & cpi.lddata;
if (cpi.wr.annul or cpi.flush) = '0' then
case wr.cpins is
when load =>
if (wr.wreg = '1') then
if cpi.wr.cnt = "00" then
wren(0) := not cpi.wr.inst(25);
wren(1) := cpi.wr.inst(25);
else wren(1) := '1'; end if;
end if;
if (wr.acsr and clk.holdn) = '1' then
rxv.csr.cexc := cpi.lddata(4 downto 0);
rxv.csr.aexc := cpi.lddata(9 downto 5);
rxv.csr.cc := cpi.lddata(11 downto 10);
rxv.csr.tem := cpi.lddata(27 downto 23);
rxv.csr.rd := cpi.lddata(31 downto 30);
end if;
when store =>
if wr.acsr = '1' then rxv.csr.tt := (others => '0'); end if;
if (cpi.wr.inst(20 downto 19) = "10") then -- STDFQ
if qne = '1'then
euv.status := free; euv.rst := '1'; euv.wbok := '0';
else
rxv.state := nominal;
end if;
end if;
when cpop =>
-- dont assign PC and inst until here in case previous cpop trapped
if clk.holdn = '1' then euv.wbok := rx.wbok; end if;
euv.inst := cpi.wr.inst;
euv.pc := cpi.wr.pc;
when others => null;
end case;
end if;
if (wr.cpins = cpop) and (clk.holdn = '1') and (eu.wbok = '0') and
((cpi.flush or cpi.wr.annul) = '1')
then
if rx.state = nominal then euv.status := free; end if;
euv.rst := '1'; euv.wbok := '0';
end if;
waddr := cpi.wr.inst(29 downto 26);
-------------------------------------------------------------
-- retire stage
-------------------------------------------------------------
rtaddr := eu.rd(4 downto 1);
if eu.rdd = '1' then rtdata := euo.res;
else
rtdata(63 downto 32) := euo.res(63) &
euo.res(59 downto 29);
rtdata(31 downto 0) := rtdata(63 downto 32);
end if;
wren := wren and (clk.holdn & clk.holdn);
if ((euo.exc(4 downto 0) and rx.csr.tem) /= "00000") or
(euo.exc(5) = '1')
then
cpexc := '1';
end if;
if (wren = "00") and (eu.status = ready) and (rx.state = nominal) and
((eu.wbok = '1') or ((cpi.flush = '0') and (rx.wbok = '1')))
then
waddr := rtaddr; wrdata := rtdata;
euv.wbok := '0';
if (clk.holdn = '0') then rxv.wbok := '0'; end if;
if cpexc = '0' then
if (eu.wreg) = '1' then
if (eu.rdd) = '1' then wren := "11";
else
wren(0) := not eu.rd(0);
wren(1) := eu.rd(0);
end if;
end if;
if eu.wrcc = '1' then
rxv.csr.cc := euo.cc;
end if;
rxv.csr.aexc := rx.csr.aexc or euo.exc(4 downto 0);
if euv.status = ready then
euv.status := free;
end if;
wbv := '1';
rxv.csr.cexc := euo.exc(4 downto 0);
else
rxv.state := excpend;
if (euo.exc(5) = '1') then rxv.csr.tt := "011";
else rxv.csr.tt := "001"; end if;
end if;
end if;
if cpi.exack = '1' then rxv.state := exception; end if;
if rxv.state = excpend then cpo.exc <= '1'; else cpo.exc <= '0'; end if;
cpo.ccv <= not ccv;
cpo.cc <= rx.csr.cc;
rxv.res := wrdata;
rxv.waddr := waddr;
rxv.wren := wren;
rfi1.wraddr(3 downto 0) <= waddr;
rfi2.wraddr(3 downto 0) <= waddr;
rfi1.wren <= wren(0);
rfi2.wren <= wren(1);
rfi1.wrdata(31 downto 0) <= wrdata(63 downto 32);
rfi2.wrdata(31 downto 0) <= wrdata(31 downto 0);
-- reset
if rst = '0' then
rxv.holdn := '1'; rv.start := '0';
rxv.state := nominal; rxv.csr.tt := (others => '0');
rxv.startx := '0'; euv.status := free; euv.wbok := '0';
end if;
euin <= euv;
eui <= euiv;
exin <= ctrl;
rin <= rv;
rxin <= rxv;
wb <= wbv;
end process;
-- registers
regs : process(clk)
variable pc : std_logic_vector(31 downto 0);
begin
if rising_edge(clk.clk) then
if clk.holdn = '1' then
ex <= exin; me <= ex; wr <= me; r <= rin;
end if;
rx <= rxin; eu <= euin;
-- pragma translate_off
if DEBUGFPU then
if (rfi1.wren = '1') then
print("0x" & tosth(cpi.wr.pc(31 downto 2) & "00") & ": %f" &
tostd(rfi1.wraddr(3 downto 0) & '0') &
" = " & tosth(rfi1.wrdata(31 downto 0)));
end if;
if (rfi2.wren = '1') then
print("0x" & tosth(cpi.wr.pc(31 downto 2) & "00") & ": %f" &
tostd(rfi1.wraddr(3 downto 0) & '1') &
" = " & tosth(rfi2.wrdata(31 downto 0)));
end if;
end if;
-- pragma translate_on
end if;
end process;
-- regfile
rf0: regfile_cp generic map (4, 32, 16)
port map (rst, clk.clk, rfi1, rfo1);
rf1: regfile_cp generic map (4, 32, 16)
port map (rst, clk.clk, rfi2, rfo2);
fpu0 : fpu port map (
ss_clock => clk.clk,
FpInst => eui.opcode,
FpOp => eui.start,
FpLd => eui.load,
Reset => eui.flush,
fprf_dout1 => eui.op1,
fprf_dout2 => eui.op2,
RoundingMode => rx.csr.rd,
FpBusy => euo.busy,
FracResult => euo.res(51 downto 0),
ExpResult => euo.res(62 downto 52),
SignResult => euo.res(63),
SNnotDB => open,
Excep => euo.exc,
ConditionCodes => euo.cc,
ss_scan_mode => gnd,
fp_ctl_scan_in => gnd,
fp_ctl_scan_out => open);
end;
|
----------------------------------------------------------------------------
-- This file is a part of the LEON VHDL model
-- Copyright (C) 1999 European Space Agency (ESA)
--
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2 of the License, or (at your option) any later version.
--
-- See the file COPYING.LGPL for the full details of the license.
-----------------------------------------------------------------------------
-- Entity: fp
-- File: fp.vhd
-- Author: Jiri Gaisler - ESA/ESTEC
-- Description: Parallel floating-point and co-processor interface
-- The interface allows one execution unit
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use work.config.all;
use work.iface.all;
use work.sparcv8.all;
use work.tech_map.all;
use work.fpulib.all;
-- pragma translate_off
use STD.TEXTIO.all;
use work.debug.all;
-- pragma translate_on
entity fp1eu is
port (
rst : in std_logic; -- Reset
clk : in clkgen_out_type;
xholdn : in std_logic; -- pipeline hold
cpi : in cp_in_type;
cpo : out cp_out_type
);
end;
architecture rtl of fp1eu is
type cpins_type is (none, cpop, load, store);
type pl_ctrl is record -- pipeline control record
cpins : cpins_type; -- CP instruction
rreg1 : std_logic; -- using rs1
rreg2 : std_logic; -- using rs1
rs1d : std_logic; -- rs1 is double (64-bit)
rs2d : std_logic; -- rs2 is double (64-bit)
wreg : std_logic; -- write CP regfile
rdd : std_logic; -- rd is double (64-bit)
wrcc : std_logic; -- write CP condition codes
acsr : std_logic; -- access CP control register
end record;
type unit_status_type is (free, started, ready);
type unit_ctrl is record -- execution unit control record
status : unit_status_type; -- unit status
rs1 : std_logic_vector (4 downto 0); -- destination register
rs2 : std_logic_vector (4 downto 0); -- destination register
rd : std_logic_vector (4 downto 0); -- destination register
rreg1 : std_logic; -- using rs1
rreg2 : std_logic; -- using rs1
rs1d : std_logic; -- rs1 is double (64-bit)
rs2d : std_logic; -- rs2 is double (64-bit)
wreg : std_logic; -- will write CP regfile
rdd : std_logic; -- rd is double (64-bit)
wbok : std_logic; -- ok to write result
wrcc : std_logic; -- will write CP condition codes
rst : std_logic; -- reset register
pc : std_logic_vector (31 downto PCLOW); -- program counter
inst : std_logic_vector (31 downto 0); -- instruction
end record;
type csr_type is record -- CP status register
cc : std_logic_vector (1 downto 0); -- condition codes
aexc : std_logic_vector (4 downto 0); -- exception codes
cexc : std_logic_vector (4 downto 0); -- exception codes
tem : std_logic_vector (4 downto 0); -- trap enable mask
rd : std_logic_vector (1 downto 0); -- rounding mode
tt : std_logic_vector (2 downto 0); -- trap type
end record;
type execstate is (nominal, excpend, exception);
type reg_type is record -- registers clocked with pipeline
start : std_logic; -- start EU
end record;
type regx_type is record -- registers clocked continuously
res : std_logic_vector (63 downto 0); -- write stage result
waddr : std_logic_vector (3 downto 0); -- write stage dest
wren : std_logic_vector (1 downto 0); -- write stage regfile write enable
csr : csr_type; -- co-processor status register
start : std_logic; -- start EU
starty : std_logic; -- start EU
startx : std_logic; -- start EU
holdn : std_logic;
wbok : std_logic; -- ok to write result
state : execstate; -- FP/CP state
end record;
signal vcc, gnd, wb : std_logic;
signal rfi1, rfi2 : rf_cp_in_type;
signal rfo1, rfo2 : rf_cp_out_type;
signal ex, exin, me, mein, wr, wrin : pl_ctrl;
signal r, rin : reg_type;
signal rx, rxin : regx_type;
signal eui : cp_unit_in_type;
signal euo : cp_unit_out_type;
signal eu, euin : unit_ctrl;
function ldcheck (rdin : std_logic_vector; ldd : std_logic; eu : unit_ctrl)
return std_logic is
variable lock : std_logic;
variable rd : std_logic_vector(4 downto 0);
begin
lock := '0'; rd := rdin;
if (eu.status > free) then
if (eu.rdd = '0') then
if ((eu.wreg = '1') and (rd = eu.rd)) or
((eu.rreg1 = '1') and (rd = eu.rs1)) or
((eu.rreg2 = '1') and (rd = eu.rs2))
then lock := '1'; end if;
if (ldd = '1') then
if ((eu.wreg = '1') and ((rd(4 downto 1) & '1') = eu.rd)) or
((eu.rreg1 = '1') and ((rd(4 downto 1) & '1') = eu.rs1)) or
((eu.rreg2 = '1') and ((rd(4 downto 1) & '1') = eu.rs2))
then lock := '1'; end if;
end if;
else
if ((eu.wreg = '1') and (rd(4 downto 1) = eu.rd(4 downto 1))) or
((eu.rreg1 = '1') and (rd(4 downto 1) = eu.rs1(4 downto 1))) or
((eu.rreg2 = '1') and (rd(4 downto 1) = eu.rs2(4 downto 1)))
then lock := '1'; end if;
end if;
end if;
return(lock);
end;
function stcheck (rdin : std_logic_vector; std : std_logic; eu : unit_ctrl)
return std_logic is
variable lock : std_logic;
variable rd : std_logic_vector(4 downto 0);
begin
lock := '0'; rd := rdin;
if (eu.status > free) then
if (eu.rdd = '0') then
if ((eu.wreg = '1') and (rd = eu.rd)) then lock := '1'; end if;
if (std = '1') then
if ((eu.wreg = '1') and ((rd(4 downto 1) & '1') = eu.rd))
then lock := '1'; end if;
end if;
else
if ((eu.wreg = '1') and (rd(4 downto 1) = eu.rd(4 downto 1))) or
((eu.rreg1 = '1') and (rd(4 downto 1) = eu.rs1(4 downto 1))) or
((eu.rreg2 = '1') and (rd(4 downto 1) = eu.rs2(4 downto 1)))
then lock := '1'; end if;
end if;
end if;
return(lock);
end;
function srccheck (rsin : std_logic_vector; dbl : std_logic; eu : unit_ctrl)
return std_logic is
variable lock : std_logic;
variable rs : std_logic_vector(4 downto 0);
begin
lock := '0'; rs := rsin;
if (eu.wreg = '1') and (rs(4 downto 1) = eu.rd(4 downto 1)) then
if ((dbl or eu.rdd) = '1') or (rs(0) = eu.rd(0)) then lock := '1'; end if;
end if;
return(lock);
end;
begin
vcc <= '1'; gnd <= '1';
-- instruction decoding
pipeline : process(cpi, ex, me, wr, eu, euin, r, rx, rfi1, rfi2, rfo1, rfo2,
clk.holdn, xholdn,
euo, rst, wb)
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable opc : std_logic_vector(8 downto 0);
variable stdata : std_logic_vector(31 downto 0);
variable rs1, rs2, rd : std_logic_vector(4 downto 0);
variable ctrl : pl_ctrl;
variable ldlock : std_logic;
variable wren : std_logic_vector(1 downto 0);
variable waddr : std_logic_vector(3 downto 0);
variable rtaddr : std_logic_vector(3 downto 0);
variable wrdata : std_logic_vector(63 downto 0);
variable rtdata : std_logic_vector(63 downto 0);
variable rv : reg_type;
variable rxv : regx_type;
variable euv : unit_ctrl;
variable euiv : cp_unit_in_type;
variable ddep : std_logic;
variable cpexc : std_logic;
variable fpill : std_logic;
variable ccv : std_logic;
variable qne : std_logic;
variable wbv : std_logic;
variable op1 : std_logic_vector (63 downto 0); -- operand1
variable op2 : std_logic_vector (63 downto 0); -- operand2
variable opcode : std_logic_vector (9 downto 0); -- FP opcode
begin
-------------------------------------------------------------
-- decode stage
-------------------------------------------------------------
op := cpi.dinst(31 downto 30);
op3 := cpi.dinst(24 downto 19);
opc := cpi.dinst(13 downto 5);
rs1 := cpi.dinst(18 downto 14);
rs2 := cpi.dinst(4 downto 0);
rd := cpi.dinst(29 downto 25);
rv := r; rxv := rx;
ctrl.cpins := none; ctrl.wreg := '0'; ctrl.rdd := '0';
ctrl.wrcc := '0'; ctrl.acsr := '0'; ldlock := '0';
ctrl.rreg1 := '0'; ctrl.rreg2 := '0';
ctrl.rs1d := '0'; ctrl.rs2d := '0'; fpill := '0';
stdata := (others => '-'); wren := "00"; cpexc := '0';
ccv := '0'; rv.start := '0'; rxv.wbok := '0';
rxv.start := '0';
euv := eu;
if eu.status /= free then qne := '1'; else qne := '0'; end if;
euiv.opcode := cpi.ex.inst(19) & cpi.ex.inst(13 downto 5);
euiv.start := '0'; euiv.load := '0';
euiv.flush := eu.rst or euin.rst;
wbv := '0';
euv.rst := not rst;
if (eu.status = started) and (euo.busy = '0') then
euv.status := ready;
end if;
if (eu.status > free) then ccv := ccv or eu.wrcc; end if;
-- decode CP instructions
case op is
when FMT3 =>
case op3 is
when FPOP1 =>
if rx.state = exception then rxv.state := excpend; rxv.csr.tt := "100";
elsif rx.state = nominal then
ctrl.cpins := cpop; ctrl.wreg := '1';
case opc is
when FMOVS | FABSS | FNEGS => ctrl.rreg2 := '1';
when FITOS | FSTOI => ctrl.rreg2 := '1';
when FITOD | FSTOD => ctrl.rreg2 := '1'; ctrl.rdd := '1';
when FDTOI | FDTOS => ctrl.rreg2 := '1'; ctrl.rs2d := '1';
when FSQRTS => ctrl.rreg2 := '1';
when FSQRTD => ctrl.rreg2 := '1'; ctrl.rs2d := '1'; ctrl.rdd := '1';
when FADDS | FSUBS | FMULS | FDIVS =>
ctrl.rreg1 := '1'; ctrl.rreg2 := '1';
when FADDD | FSUBD | FMULD | FDIVD =>
ctrl.rreg1 := '1'; ctrl.rreg2 := '1'; ctrl.rs1d := '1';
ctrl.rs2d := '1'; ctrl.rdd := '1';
when others => fpill := '1'; -- illegal instuction
end case;
end if;
when FPOP2 =>
if rx.state = exception then rxv.state := excpend; rxv.csr.tt := "100";
elsif rx.state = nominal then
ctrl.cpins := cpop; ctrl.wrcc := '1';
ctrl.rreg1 := '1'; ctrl.rreg2 := '1';
case opc is
when FCMPD | FCMPED =>
ctrl.rs1d := '1'; ctrl.rs2d := '1';
when others => fpill := '1'; -- illegal instuction
end case;
end if;
when others => null;
end case;
if (ex.cpins = load) and ((cpi.ex.annul or cpi.ex.trap) = '0') and
(ex.wreg = '1')
then
if (ctrl.rreg1 = '1') and
(rs1(4 downto 1) = cpi.ex.inst(29 downto 26)) and
(((ctrl.rs1d or ex.rdd) = '1') or (rs1(0) = cpi.ex.inst(25)))
then ldlock := '1'; end if;
if (ctrl.rreg2 = '1') and
(rs2(4 downto 1) = cpi.ex.inst(29 downto 26)) and
(((ctrl.rs2d or ex.rdd) = '1') or (rs2(0) = cpi.ex.inst(25)))
then ldlock := '1'; end if;
end if;
when LDST =>
case op3 is
when LDF | LDDF =>
if rx.state = exception then rxv.state := excpend; rxv.csr.tt := "100";
elsif rx.state = nominal then
ctrl.rdd := op3(1) and op3(0);
ctrl.cpins := load; ctrl.wreg := '1';
-- dst interlock
ldlock := ldlock or ldcheck(rd, ctrl.rdd, euin);
end if;
when STF | STDF =>
-- check for CP register dependencies
if (ex.cpins = load) and ((cpi.ex.annul or cpi.ex.trap) = '0') and
(cpi.ex.cnt = "00") and
((rd = cpi.ex.inst(29 downto 25)) or
((rd(4 downto 1) = cpi.ex.inst(29 downto 26)) and
(ex.rdd = '1')))
then ldlock := '1'; end if;
if rx.state = nominal then
ldlock := ldlock or stcheck(rd, (op3(1) and op3(0)), euin);
end if;
if (ldlock = '0') then ctrl.cpins := store; end if;
when STFSR | LDFSR =>
if (rx.state = exception) and (op3 = LDFSR) then
rxv.state := excpend; rxv.csr.tt := "100";
else
if (ex.cpins = load) and ((cpi.ex.annul or cpi.ex.trap) = '0') and
(cpi.ex.cnt = "00") and (op3 = STFSR) and (ex.acsr = '1')
then ldlock := '1'; end if;
if (rx.state = nominal) then
if (((cpi.ex.annul or cpi.ex.trap) = '0') and (ex.cpins = cpop))
or (eu.status > free)
then ldlock := '1'; end if;
end if;
end if;
if (ldlock = '0') then
ctrl.acsr := '1';
if op3 = STFSR then ctrl.cpins := store;
else ctrl.cpins := load; end if;
end if;
when STDFQ =>
if (rx.state = nominal) then
rxv.state := excpend; rxv.csr.tt := "100";
else ctrl.cpins := store; end if;
when others => null;
end case;
when others => null;
end case;
if ((cpi.flush or cpi.dtrap or cpi.dannul or ldlock) = '1') then
ctrl.cpins := none; ctrl.acsr := '0';
rxv.state := rx.state; rxv.csr.tt := rx.csr.tt;
end if;
if ((cpi.flush or cpi.dtrap or cpi.dannul) = '1') then
ldlock := '0';
end if;
-------------------------------------------------------------
-- execute stage
-------------------------------------------------------------
-- generate regfile addresses
if clk.holdn = '0' then
op := cpi.me.inst(31 downto 30);
rd := cpi.me.inst(29 downto 25);
op3 := cpi.me.inst(24 downto 19);
rs1 := cpi.me.inst(18 downto 14);
rs2 := cpi.me.inst(4 downto 0);
else
op := cpi.ex.inst(31 downto 30);
rd := cpi.ex.inst(29 downto 25);
op3 := cpi.ex.inst(24 downto 19);
rs1 := cpi.ex.inst(18 downto 14);
rs2 := cpi.ex.inst(4 downto 0);
end if;
if (op = LDST) and (op3(2) = '1') then rs1 := rd; end if;
rfi1.rd1addr(3 downto 0) <= rs1(4 downto 1); rfi1.rd2addr(3 downto 0) <= rs2(4 downto 1);
rfi2.rd1addr(3 downto 0) <= rs1(4 downto 1); rfi2.rd2addr(3 downto 0) <= rs2(4 downto 1);
rfi1.ren1 <= '1'; rfi1.ren2 <= '1'; rfi2.ren1 <= '1'; rfi2.ren2 <= '1';
cpo.ldlock <= ldlock;
op1 := rfo1.data1(31 downto 0) & rfo2.data1(31 downto 0);
op2 := rfo1.data2(31 downto 0) & rfo2.data2(31 downto 0);
-- generate store data
if (cpi.ex.inst(20 downto 19) = "10") then -- STDFQ
if (cpi.ex.cnt /= "10") then stdata := eu.pc(31 downto 2) & "00";
else stdata := eu.inst; end if;
elsif ((cpi.ex.inst(25) = '0') and (cpi.ex.cnt /= "10")) then -- STF/STDF
stdata := op1(63 downto 32);
else stdata := op1(31 downto 0); end if;
if (ex.cpins = store) and (ex.acsr = '1') then -- STFSR
stdata := rx.csr.rd & "00" & rx.csr.tem & "000" &
std_logic_vector(FPUVER) & rx.csr.tt & qne & '0' & rx.csr.cc &
rx.csr.aexc & rx.csr.cexc;
end if;
cpo.data <= stdata;
-- check if an execution unit is available
if (ex.cpins = cpop) and (clk.holdn = '1') and (cpi.ex.annul = '0') then
ccv := ccv or ex.wrcc;
if (eu.status = free) or ((eu.status = ready) and (wb = '1')) then
rxv.start := '1';
euiv.start := '1';
if cpi.flush = '0' then euv.status := started; end if;
euv.rd := cpi.ex.inst(29 downto 25);
euv.rs1 := cpi.ex.inst(18 downto 14);
euv.rs2 := cpi.ex.inst(4 downto 0);
euv.wreg := ex.wreg;
euv.rreg1 := ex.rreg1;
euv.rreg2 := ex.rreg2;
euv.rs1d := ex.rs1d;
euv.rs2d := ex.rs2d;
euv.rdd := ex.rdd;
euv.wrcc := ex.wrcc;
else rxv.holdn := '0'; rv.start := '1'; end if;
end if;
if cpi.flush = '1' then
rxv.start := '0'; euiv.start := '0';
end if;
-------------------------------------------------------------
-- memory stage
-------------------------------------------------------------
euiv.load := rx.start or rx.starty;
if (rx.holdn = '0') and (xholdn = '1') and (cpi.flush = '0') and
(euo.busy = '0')
then
euiv.start := not rx.startx;
euiv.opcode := cpi.me.inst(19) & cpi.me.inst(13 downto 5);
end if;
if (rx.holdn = '0') and ((eu.status <= free) or (wb = '1'))
then
euiv.load := rx.starty;
euiv.start := not (rx.starty or rx.startx);
euv.status := started;
euv.rs1 := cpi.me.inst(18 downto 14);
euv.rs2 := cpi.me.inst(4 downto 0);
euv.rd := cpi.me.inst(29 downto 25);
euv.wreg := me.wreg;
euv.rreg1 := me.rreg1;
euv.rreg2 := me.rreg2;
euv.rs1d := me.rs1d;
euv.rs2d := me.rs2d;
euv.rdd := me.rdd;
euv.wrcc := me.wrcc;
euiv.opcode := cpi.me.inst(19) & cpi.me.inst(13 downto 5);
rxv.holdn := '1';
end if;
euiv.start := euiv.start and not cpi.flush;
rxv.starty := euiv.start;
rxv.startx := (rx.startx or euiv.start) and (not clk.holdn) and not cpi.flush;
ccv := ccv or me.wrcc;
if (cpi.flush = '1') or (rx.state /= nominal) then rxv.holdn := '1'; end if;
if clk.holdn = '0' then rxv.wbok := rx.wbok; end if;
if (me.cpins = cpop) and (clk.holdn = '1') then
if ((cpi.flush and not eu.wbok) = '1') then euv.rst := '1';
else rxv.wbok := not cpi.me.annul; end if;
end if;
-- regfile bypass
if (rx.waddr = cpi.me.inst(18 downto 15)) then
if (rx.wren(0) = '1') then op1(63 downto 32) := rx.res(63 downto 32); end if;
if (rx.wren(1) = '1') then op1(31 downto 0) := rx.res(31 downto 0); end if;
end if;
if (rx.waddr = cpi.me.inst(4 downto 1)) then
if (rx.wren(0) = '1') then op2(63 downto 32) := rx.res(63 downto 32); end if;
if (rx.wren(1) = '1') then op2(31 downto 0) := rx.res(31 downto 0); end if;
end if;
-- optionally forward data from write stage
if rfi1.wren = '1' then
if cpi.me.inst(18 downto 15) = rfi1.wraddr(3 downto 0) then
op1(63 downto 32) := rfi1.wrdata(31 downto 0);
end if;
if cpi.me.inst(4 downto 1) = rfi1.wraddr(3 downto 0) then
op2(63 downto 32) := rfi1.wrdata(31 downto 0);
end if;
end if;
if rfi2.wren = '1' then
if cpi.me.inst(18 downto 15) = rfi2.wraddr(3 downto 0) then
op1(31 downto 0) := rfi2.wrdata(31 downto 0);
end if;
if cpi.me.inst(4 downto 1) = rfi2.wraddr(3 downto 0) then
op2(31 downto 0) := rfi2.wrdata(31 downto 0);
end if;
end if;
-- align single operands
if me.rs1d = '0' then
if cpi.me.inst(14) = '0' then op1 := op1(63 downto 32) & op1(63 downto 32);
else op1 := op1(31 downto 0) & op1(31 downto 0); end if;
end if;
if me.rs2d = '0' then
if cpi.me.inst(0) = '0' then op2 := op2(63 downto 32) & op2(63 downto 32);
else op2 := op2(31 downto 0) & op2(31 downto 0); end if;
end if;
-- drive EU operand inputs
euiv.op1 := op1; euiv.op2 := op2;
cpo.holdn <= rx.holdn;
-------------------------------------------------------------
-- write stage
-------------------------------------------------------------
wrdata := cpi.lddata & cpi.lddata;
if (cpi.wr.annul or cpi.flush) = '0' then
case wr.cpins is
when load =>
if (wr.wreg = '1') then
if cpi.wr.cnt = "00" then
wren(0) := not cpi.wr.inst(25);
wren(1) := cpi.wr.inst(25);
else wren(1) := '1'; end if;
end if;
if (wr.acsr and clk.holdn) = '1' then
rxv.csr.cexc := cpi.lddata(4 downto 0);
rxv.csr.aexc := cpi.lddata(9 downto 5);
rxv.csr.cc := cpi.lddata(11 downto 10);
rxv.csr.tem := cpi.lddata(27 downto 23);
rxv.csr.rd := cpi.lddata(31 downto 30);
end if;
when store =>
if wr.acsr = '1' then rxv.csr.tt := (others => '0'); end if;
if (cpi.wr.inst(20 downto 19) = "10") then -- STDFQ
if qne = '1'then
euv.status := free; euv.rst := '1'; euv.wbok := '0';
else
rxv.state := nominal;
end if;
end if;
when cpop =>
-- dont assign PC and inst until here in case previous cpop trapped
if clk.holdn = '1' then euv.wbok := rx.wbok; end if;
euv.inst := cpi.wr.inst;
euv.pc := cpi.wr.pc;
when others => null;
end case;
end if;
if (wr.cpins = cpop) and (clk.holdn = '1') and (eu.wbok = '0') and
((cpi.flush or cpi.wr.annul) = '1')
then
if rx.state = nominal then euv.status := free; end if;
euv.rst := '1'; euv.wbok := '0';
end if;
waddr := cpi.wr.inst(29 downto 26);
-------------------------------------------------------------
-- retire stage
-------------------------------------------------------------
rtaddr := eu.rd(4 downto 1);
if eu.rdd = '1' then rtdata := euo.res;
else
rtdata(63 downto 32) := euo.res(63) &
euo.res(59 downto 29);
rtdata(31 downto 0) := rtdata(63 downto 32);
end if;
wren := wren and (clk.holdn & clk.holdn);
if ((euo.exc(4 downto 0) and rx.csr.tem) /= "00000") or
(euo.exc(5) = '1')
then
cpexc := '1';
end if;
if (wren = "00") and (eu.status = ready) and (rx.state = nominal) and
((eu.wbok = '1') or ((cpi.flush = '0') and (rx.wbok = '1')))
then
waddr := rtaddr; wrdata := rtdata;
euv.wbok := '0';
if (clk.holdn = '0') then rxv.wbok := '0'; end if;
if cpexc = '0' then
if (eu.wreg) = '1' then
if (eu.rdd) = '1' then wren := "11";
else
wren(0) := not eu.rd(0);
wren(1) := eu.rd(0);
end if;
end if;
if eu.wrcc = '1' then
rxv.csr.cc := euo.cc;
end if;
rxv.csr.aexc := rx.csr.aexc or euo.exc(4 downto 0);
if euv.status = ready then
euv.status := free;
end if;
wbv := '1';
rxv.csr.cexc := euo.exc(4 downto 0);
else
rxv.state := excpend;
if (euo.exc(5) = '1') then rxv.csr.tt := "011";
else rxv.csr.tt := "001"; end if;
end if;
end if;
if cpi.exack = '1' then rxv.state := exception; end if;
if rxv.state = excpend then cpo.exc <= '1'; else cpo.exc <= '0'; end if;
cpo.ccv <= not ccv;
cpo.cc <= rx.csr.cc;
rxv.res := wrdata;
rxv.waddr := waddr;
rxv.wren := wren;
rfi1.wraddr(3 downto 0) <= waddr;
rfi2.wraddr(3 downto 0) <= waddr;
rfi1.wren <= wren(0);
rfi2.wren <= wren(1);
rfi1.wrdata(31 downto 0) <= wrdata(63 downto 32);
rfi2.wrdata(31 downto 0) <= wrdata(31 downto 0);
-- reset
if rst = '0' then
rxv.holdn := '1'; rv.start := '0';
rxv.state := nominal; rxv.csr.tt := (others => '0');
rxv.startx := '0'; euv.status := free; euv.wbok := '0';
end if;
euin <= euv;
eui <= euiv;
exin <= ctrl;
rin <= rv;
rxin <= rxv;
wb <= wbv;
end process;
-- registers
regs : process(clk)
variable pc : std_logic_vector(31 downto 0);
begin
if rising_edge(clk.clk) then
if clk.holdn = '1' then
ex <= exin; me <= ex; wr <= me; r <= rin;
end if;
rx <= rxin; eu <= euin;
-- pragma translate_off
if DEBUGFPU then
if (rfi1.wren = '1') then
print("0x" & tosth(cpi.wr.pc(31 downto 2) & "00") & ": %f" &
tostd(rfi1.wraddr(3 downto 0) & '0') &
" = " & tosth(rfi1.wrdata(31 downto 0)));
end if;
if (rfi2.wren = '1') then
print("0x" & tosth(cpi.wr.pc(31 downto 2) & "00") & ": %f" &
tostd(rfi1.wraddr(3 downto 0) & '1') &
" = " & tosth(rfi2.wrdata(31 downto 0)));
end if;
end if;
-- pragma translate_on
end if;
end process;
-- regfile
rf0: regfile_cp generic map (4, 32, 16)
port map (rst, clk.clk, rfi1, rfo1);
rf1: regfile_cp generic map (4, 32, 16)
port map (rst, clk.clk, rfi2, rfo2);
fpu0 : fpu port map (
ss_clock => clk.clk,
FpInst => eui.opcode,
FpOp => eui.start,
FpLd => eui.load,
Reset => eui.flush,
fprf_dout1 => eui.op1,
fprf_dout2 => eui.op2,
RoundingMode => rx.csr.rd,
FpBusy => euo.busy,
FracResult => euo.res(51 downto 0),
ExpResult => euo.res(62 downto 52),
SignResult => euo.res(63),
SNnotDB => open,
Excep => euo.exc,
ConditionCodes => euo.cc,
ss_scan_mode => gnd,
fp_ctl_scan_in => gnd,
fp_ctl_scan_out => open);
end;
|
---------------------------------------------------------------------
---- ----
---- Copyright (C) 2000 Richard Herveille ----
---- [email protected] ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer.----
---- ----
---- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ----
---- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ----
---- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ----
---- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ----
---- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ----
---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ----
---- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ----
---- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ----
---- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ----
---- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ----
---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ----
---- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ----
---- POSSIBILITY OF SUCH DAMAGE. ----
---- ----
---------------------------------------------------------------------
-- Package containing i2c master byte controller component. Component
-- declaration expanded and separated into this file by [email protected].
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package i2coc is
component i2c_master_byte_ctrl is
generic (filter : integer; dynfilt : integer);
port (
clk : in std_logic;
rst : in std_logic; -- active high reset
nReset : in std_logic; -- asynchornous active low reset
-- (not used in GRLIB)
ena : in std_logic; -- core enable signal
clk_cnt : in std_logic_vector(15 downto 0); -- 4x SCL
-- input signals
start,
stop,
read,
write,
ack_in : std_logic;
din : in std_logic_vector(7 downto 0);
filt : in std_logic_vector((filter-1)*dynfilt downto 0);
-- output signals
cmd_ack : out std_logic;
ack_out : out std_logic;
i2c_busy : out std_logic;
i2c_al : out std_logic;
dout : out std_logic_vector(7 downto 0);
-- i2c lines
scl_i : in std_logic; -- i2c clock line input
scl_o : out std_logic; -- i2c clock line output
scl_oen : out std_logic; -- i2c clock line output enable, active low
sda_i : in std_logic; -- i2c data line input
sda_o : out std_logic; -- i2c data line output
sda_oen : out std_logic -- i2c data line output enable, active low
);
end component i2c_master_byte_ctrl;
end;
|
---------------------------------------------------------------------
---- ----
---- Copyright (C) 2000 Richard Herveille ----
---- [email protected] ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer.----
---- ----
---- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ----
---- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ----
---- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ----
---- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ----
---- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ----
---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ----
---- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ----
---- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ----
---- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ----
---- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ----
---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ----
---- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ----
---- POSSIBILITY OF SUCH DAMAGE. ----
---- ----
---------------------------------------------------------------------
-- Package containing i2c master byte controller component. Component
-- declaration expanded and separated into this file by [email protected].
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package i2coc is
component i2c_master_byte_ctrl is
generic (filter : integer; dynfilt : integer);
port (
clk : in std_logic;
rst : in std_logic; -- active high reset
nReset : in std_logic; -- asynchornous active low reset
-- (not used in GRLIB)
ena : in std_logic; -- core enable signal
clk_cnt : in std_logic_vector(15 downto 0); -- 4x SCL
-- input signals
start,
stop,
read,
write,
ack_in : std_logic;
din : in std_logic_vector(7 downto 0);
filt : in std_logic_vector((filter-1)*dynfilt downto 0);
-- output signals
cmd_ack : out std_logic;
ack_out : out std_logic;
i2c_busy : out std_logic;
i2c_al : out std_logic;
dout : out std_logic_vector(7 downto 0);
-- i2c lines
scl_i : in std_logic; -- i2c clock line input
scl_o : out std_logic; -- i2c clock line output
scl_oen : out std_logic; -- i2c clock line output enable, active low
sda_i : in std_logic; -- i2c data line input
sda_o : out std_logic; -- i2c data line output
sda_oen : out std_logic -- i2c data line output enable, active low
);
end component i2c_master_byte_ctrl;
end;
|
---------------------------------------------------------------------
---- ----
---- Copyright (C) 2000 Richard Herveille ----
---- [email protected] ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer.----
---- ----
---- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ----
---- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ----
---- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ----
---- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ----
---- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ----
---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ----
---- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ----
---- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ----
---- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ----
---- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ----
---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ----
---- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ----
---- POSSIBILITY OF SUCH DAMAGE. ----
---- ----
---------------------------------------------------------------------
-- Package containing i2c master byte controller component. Component
-- declaration expanded and separated into this file by [email protected].
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package i2coc is
component i2c_master_byte_ctrl is
generic (filter : integer; dynfilt : integer);
port (
clk : in std_logic;
rst : in std_logic; -- active high reset
nReset : in std_logic; -- asynchornous active low reset
-- (not used in GRLIB)
ena : in std_logic; -- core enable signal
clk_cnt : in std_logic_vector(15 downto 0); -- 4x SCL
-- input signals
start,
stop,
read,
write,
ack_in : std_logic;
din : in std_logic_vector(7 downto 0);
filt : in std_logic_vector((filter-1)*dynfilt downto 0);
-- output signals
cmd_ack : out std_logic;
ack_out : out std_logic;
i2c_busy : out std_logic;
i2c_al : out std_logic;
dout : out std_logic_vector(7 downto 0);
-- i2c lines
scl_i : in std_logic; -- i2c clock line input
scl_o : out std_logic; -- i2c clock line output
scl_oen : out std_logic; -- i2c clock line output enable, active low
sda_i : in std_logic; -- i2c data line input
sda_o : out std_logic; -- i2c data line output
sda_oen : out std_logic -- i2c data line output enable, active low
);
end component i2c_master_byte_ctrl;
end;
|
architecture ARCH of ENTITY1 is
begin
U_INST1 : INST1
generic map (
G_GEN_1 => 3,
G_GEN_2 => 4,
G_GEN_3 => 5
)
port map (
PORT_1 => w_port_1,
PORT_2 => w_port_2,
PORT_3 => w_port_3
);
-- Violations below
U_INST1 : INST1
generic map(
G_GEN_1 => 3,
4,
G_GEN_3 => 5
)
port map (w_port_1,
PORT_2 => w_port_2,
w_port_3
);
U_INST1 : INST1
generic map (
3,
G_GEN_2 => 4,
5
)
port map (PORT_1 => w_port_1,
w_port_2,
w_port_3
);
end architecture ARCH;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_pkg.vhd
--
-- Description:
-- This is the demo testbench package file for fifo_generator_v8.4 core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
PACKAGE fg_tb_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME;
------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector;
------------------------
COMPONENT fg_tb_rng IS
GENERIC (WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_dverif IS
GENERIC(
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_USE_EMBEDDED_REG : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT(
RESET : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
PRC_RD_EN : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
RD_EN : OUT STD_LOGIC;
DOUT_CHK : OUT STD_LOGIC
);
END COMPONENT;
------------------------
COMPONENT fg_tb_pctrl IS
GENERIC(
AXI_CHANNEL : STRING := "NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT RD_FLASH_PRE_FIFO_top IS
PORT (
WR_CLK : IN std_logic;
RD_CLK : IN std_logic;
VALID : OUT std_logic;
RST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(8-1 DOWNTO 0);
DOUT : OUT std_logic_vector(64-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
END COMPONENT;
------------------------
END fg_tb_pkg;
PACKAGE BODY fg_tb_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER IS
VARIABLE div : INTEGER;
BEGIN
div := data_value/divisor;
IF ( (data_value MOD divisor) /= 0) THEN
div := div+1;
END IF;
RETURN div;
END divroundup;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
VARIABLE retval : INTEGER := 0;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC IS
VARIABLE retval : STD_LOGIC := '0';
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME IS
VARIABLE retval : TIME := 0 ps;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
-------------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := 1;
BEGIN
IF (data_value <= 1) THEN
width := 1;
ELSE
WHILE (cnt < data_value) LOOP
width := width + 1;
cnt := cnt *2;
END LOOP;
END IF;
RETURN width;
END log2roundup;
------------------------------------------------------------------------------
-- hexstr_to_std_logic_vec
-- This function converts a hex string to a std_logic_vector
------------------------------------------------------------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector IS
VARIABLE result : std_logic_vector(size-1 DOWNTO 0) := (OTHERS => '0');
VARIABLE bin : std_logic_vector(3 DOWNTO 0);
VARIABLE index : integer := 0;
BEGIN
FOR i IN arg1'reverse_range LOOP
CASE arg1(i) IS
WHEN '0' => bin := (OTHERS => '0');
WHEN '1' => bin := (0 => '1', OTHERS => '0');
WHEN '2' => bin := (1 => '1', OTHERS => '0');
WHEN '3' => bin := (0 => '1', 1 => '1', OTHERS => '0');
WHEN '4' => bin := (2 => '1', OTHERS => '0');
WHEN '5' => bin := (0 => '1', 2 => '1', OTHERS => '0');
WHEN '6' => bin := (1 => '1', 2 => '1', OTHERS => '0');
WHEN '7' => bin := (3 => '0', OTHERS => '1');
WHEN '8' => bin := (3 => '1', OTHERS => '0');
WHEN '9' => bin := (0 => '1', 3 => '1', OTHERS => '0');
WHEN 'A' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'a' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'B' => bin := (2 => '0', OTHERS => '1');
WHEN 'b' => bin := (2 => '0', OTHERS => '1');
WHEN 'C' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'c' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'D' => bin := (1 => '0', OTHERS => '1');
WHEN 'd' => bin := (1 => '0', OTHERS => '1');
WHEN 'E' => bin := (0 => '0', OTHERS => '1');
WHEN 'e' => bin := (0 => '0', OTHERS => '1');
WHEN 'F' => bin := (OTHERS => '1');
WHEN 'f' => bin := (OTHERS => '1');
WHEN OTHERS =>
FOR j IN 0 TO 3 LOOP
bin(j) := 'X';
END LOOP;
END CASE;
FOR j IN 0 TO 3 LOOP
IF (index*4)+j < size THEN
result((index*4)+j) := bin(j);
END IF;
END LOOP;
index := index + 1;
END LOOP;
RETURN result;
END hexstr_to_std_logic_vec;
END fg_tb_pkg;
|
-- ram.vhd : RAM memory
-- Copyright (C) 2011 Brno University of Technology,
-- Faculty of Information Technology
-- Author(s): Zdenek Vasicek <vasicek AT fit.vutbr.cz>
--
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- ----------------------------------------------------------------------------
-- Entity declaration
-- ----------------------------------------------------------------------------
entity ram is
port (
CLK : in std_logic; -- hodiny
ADDR : in std_logic_vector(9 downto 0); -- adresa bunky
WDATA : in std_logic_vector(7 downto 0); -- data pro zapis
RDATA : out std_logic_vector(7 downto 0); -- nactena data (v dalsim taktu, pokud EN=1)
RDWR : in std_logic; -- 0 - cteni, 1 - zapis
EN : in std_logic -- 1 - povoleni prace s pameti
);
end ram;
-- ----------------------------------------------------------------------------
-- Architecture declaration
-- ----------------------------------------------------------------------------
architecture behavioral of ram is
type t_ram is array (0 to 2**10-1) of std_logic_vector (7 downto 0);
signal ram: t_ram := (others => X"00");
signal rd : std_logic_vector (7 downto 0) := (others => '0');
begin
RDATA <= rd;
-- RAM rd / wr
sram_mem: process (CLK)
begin
if (CLK'event) and (CLK = '1') then
if (EN = '1') then
if (RDWR = '1') then
ram(conv_integer(ADDR)) <= WDATA;
rd <= WDATA;
else
rd <= ram(conv_integer(ADDR));
end if;
end if;
end if;
end process;
end behavioral;
|
-- -------------------------------------------------------------
--
-- Entity Declaration for pad_pads_e
--
-- Generated
-- by: wig
-- on: Mon Jul 18 15:56:34 2005
-- cmd: h:/work/eclipse/mix/mix_0.pl -strip -nodelta ../../padio.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: pad_pads_e-e.vhd,v 1.3 2005/07/19 07:13:11 wig Exp $
-- $Date: 2005/07/19 07:13:11 $
-- $Log: pad_pads_e-e.vhd,v $
-- Revision 1.3 2005/07/19 07:13:11 wig
-- Update testcases. Added highlow/nolowbus
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.57 2005/07/18 08:58:22 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.36 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/enty
--
--
-- Start of Generated Entity pad_pads_e
--
entity pad_pads_e is
-- Generics:
-- No Generated Generics for Entity pad_pads_e
-- Generated Port Declaration:
port(
-- Generated Port for Entity pad_pads_e
p_mix_pad_di_12_go : out std_ulogic;
p_mix_pad_di_13_go : out std_ulogic;
p_mix_pad_di_14_go : out std_ulogic;
p_mix_pad_di_15_go : out std_ulogic;
p_mix_pad_di_16_go : out std_ulogic;
p_mix_pad_di_17_go : out std_ulogic;
p_mix_pad_di_18_go : out std_ulogic;
p_mix_pad_di_1_go : out std_ulogic;
p_mix_pad_di_31_go : out std_ulogic;
p_mix_pad_di_32_go : out std_ulogic;
p_mix_pad_di_33_go : out std_ulogic;
p_mix_pad_di_34_go : out std_ulogic;
p_mix_pad_di_39_go : out std_ulogic;
p_mix_pad_di_40_go : out std_ulogic;
p_mix_pad_do_12_gi : in std_ulogic;
p_mix_pad_do_13_gi : in std_ulogic;
p_mix_pad_do_14_gi : in std_ulogic;
p_mix_pad_do_15_gi : in std_ulogic;
p_mix_pad_do_16_gi : in std_ulogic;
p_mix_pad_do_17_gi : in std_ulogic;
p_mix_pad_do_18_gi : in std_ulogic;
p_mix_pad_do_2_gi : in std_ulogic;
p_mix_pad_do_31_gi : in std_ulogic;
p_mix_pad_do_32_gi : in std_ulogic;
p_mix_pad_do_35_gi : in std_ulogic;
p_mix_pad_do_36_gi : in std_ulogic;
p_mix_pad_do_39_gi : in std_ulogic;
p_mix_pad_do_40_gi : in std_ulogic;
p_mix_pad_en_12_gi : in std_ulogic;
p_mix_pad_en_13_gi : in std_ulogic;
p_mix_pad_en_14_gi : in std_ulogic;
p_mix_pad_en_15_gi : in std_ulogic;
p_mix_pad_en_16_gi : in std_ulogic;
p_mix_pad_en_17_gi : in std_ulogic;
p_mix_pad_en_18_gi : in std_ulogic;
p_mix_pad_en_2_gi : in std_ulogic;
p_mix_pad_en_31_gi : in std_ulogic;
p_mix_pad_en_32_gi : in std_ulogic;
p_mix_pad_en_35_gi : in std_ulogic;
p_mix_pad_en_36_gi : in std_ulogic;
p_mix_pad_en_39_gi : in std_ulogic;
p_mix_pad_en_40_gi : in std_ulogic;
p_mix_pad_pu_31_gi : in std_ulogic;
p_mix_pad_pu_32_gi : in std_ulogic
-- End of Generated Port for Entity pad_pads_e
);
end pad_pads_e;
--
-- End of Generated Entity pad_pads_e
--
--
--!End of Entity/ies
-- --------------------------------------------------------------
|
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`protect end_protected
|
----------------------------------------------------------------------------------
-- Simple FIR filter using transposed direct form.
-- Initial version: Colm Ryan ([email protected])
-- Create Date: 05/05/2015
-- Dependencies:
--
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
library ieee_proposed;
use ieee_proposed.standard_additions.all;
use work.CoeffHelpers.all;
entity FIR_DirectTranspose is
generic(
--Default 1/4 band low-pass filter generated in Python with
-- import scipy.signal
-- br = scipy.signal.remez(16, [0,0.1,0.2,0.5], [1,0])
coeffs : real_vector := (0.01662606, -0.00696415, -0.03403663, -0.04855056, -0.01434685, 0.08048669, 0.20301046, 0.28957738, 0.28957738, 0.20301046, 0.08048669, -0.01434685, -0.04855056, -0.03403663, -0.00696415, 0.01662606);
data_in_width : natural := 16;
data_out_width : natural := 16
);
port (
rst : in std_logic;
clk : in std_logic;
data_in : in std_logic_vector(data_in_width-1 downto 0);
data_in_vld : std_logic;
data_in_last : std_logic;
data_out : out std_logic_vector(data_out_width-1 downto 0));
end FIR_DirectTranspose;
architecture Behavioral of FIR_DirectTranspose is
constant NUM_TAPS : natural := coeffs'length;
type chainedSum_t is array(0 to NUM_TAPS-1) of signed(47 downto 0);
signal chainedSum : chainedSum_t := (others => (others => '0'));
--Vivado does not infer DSP for constant multiplier so force DSP
-- see http://www.xilinx.com/support/answers/60913.html
attribute use_dsp48 : string;
attribute use_dsp48 of chainedSum : signal is "yes";
signal data_in_d : signed(data_in_width-1 downto 0) := (others => '0');
--We resize to 18 bits because the DSP slices offer 18x25 bit multipliers
constant COEFF_SCALE_BITS : integer := optimum_scaling(coeffs);
constant COEFF_SCALE : real := real(2 ** (17 - COEFF_SCALE_BITS));
constant SCALED_COEFFS : integer_vector := scale_coeffs(coeffs, COEFF_SCALE);
--we resize the sum to 48 bits because the DSP slices offer 48 bit adder accumulators
--If we assume the coefficients are normalized then we don't need to worry about overflow in the addition
constant SUM_NUM_BITS : natural := 48;
--The multiplication gives us 18 + data_in_width - 1 bits
--We also need to undo the coefficients' scaling
constant TOP_OUTPUT_BIT : natural := 18 + data_in_width - 2 - COEFF_SCALE_BITS;
constant BOTTOM_OUTPUT_BIT : natural := TOP_OUTPUT_BIT - data_out_width + 1;
begin
main : process(clk)
begin
if rising_edge(clk) then
--register input data and convert to signed for DSP slice
data_in_d <= signed(data_in);
--Multiply by coeffs and chain the sum
chainedSum(0) <= resize(data_in_d * to_signed(SCALED_COEFFS(SCALED_COEFFS'high),18), SUM_NUM_BITS);
sumLooper : for ct in 1 to NUM_TAPS-1 loop
chainedSum(ct) <= resize(data_in_d * to_signed(SCALED_COEFFS(SCALED_COEFFS'high-ct),18), SUM_NUM_BITS) + chainedSum(ct-1);
end loop;
end if;
end process;
--Slice out the appropriate portion of the output - for now just truncate LSB
data_out <= std_logic_vector(chainedSum(chainedSum'high)(TOP_OUTPUT_BIT downto BOTTOM_OUTPUT_BIT));
end Behavioral;
|
-- megafunction wizard: %FIFO%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: dcfifo_mixed_widths
-- ============================================================
-- File Name: FIFO_TO_USB.vhd
-- Megafunction Name(s):
-- dcfifo_mixed_widths
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.0.1 Build 232 06/12/2013 SP 1 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY FIFO_TO_USB IS
PORT
(
aclr : IN STD_LOGIC := '0';
data : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
rdclk : IN STD_LOGIC ;
rdreq : IN STD_LOGIC ;
wrclk : IN STD_LOGIC ;
wrreq : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
rdusedw : OUT STD_LOGIC_VECTOR (11 DOWNTO 0);
wrusedw : OUT STD_LOGIC_VECTOR (10 DOWNTO 0)
);
END FIFO_TO_USB;
ARCHITECTURE SYN OF fifo_to_usb IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (10 DOWNTO 0);
SIGNAL sub_wire2 : STD_LOGIC_VECTOR (11 DOWNTO 0);
COMPONENT dcfifo_mixed_widths
GENERIC (
add_usedw_msb_bit : STRING;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_numwords : NATURAL;
lpm_showahead : STRING;
lpm_type : STRING;
lpm_width : NATURAL;
lpm_widthu : NATURAL;
lpm_widthu_r : NATURAL;
lpm_width_r : NATURAL;
overflow_checking : STRING;
rdsync_delaypipe : NATURAL;
read_aclr_synch : STRING;
underflow_checking : STRING;
use_eab : STRING;
write_aclr_synch : STRING;
wrsync_delaypipe : NATURAL
);
PORT (
rdclk : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
wrclk : IN STD_LOGIC ;
wrreq : IN STD_LOGIC ;
wrusedw : OUT STD_LOGIC_VECTOR (10 DOWNTO 0);
aclr : IN STD_LOGIC ;
data : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
rdreq : IN STD_LOGIC ;
rdusedw : OUT STD_LOGIC_VECTOR (11 DOWNTO 0)
);
END COMPONENT;
BEGIN
q <= sub_wire0(7 DOWNTO 0);
wrusedw <= sub_wire1(10 DOWNTO 0);
rdusedw <= sub_wire2(11 DOWNTO 0);
dcfifo_mixed_widths_component : dcfifo_mixed_widths
GENERIC MAP (
add_usedw_msb_bit => "ON",
intended_device_family => "Cyclone IV E",
lpm_hint => "MAXIMUM_DEPTH=512",
lpm_numwords => 1024,
lpm_showahead => "OFF",
lpm_type => "dcfifo_mixed_widths",
lpm_width => 16,
lpm_widthu => 11,
lpm_widthu_r => 12,
lpm_width_r => 8,
overflow_checking => "ON",
rdsync_delaypipe => 5,
read_aclr_synch => "OFF",
underflow_checking => "ON",
use_eab => "ON",
write_aclr_synch => "OFF",
wrsync_delaypipe => 5
)
PORT MAP (
rdclk => rdclk,
wrclk => wrclk,
wrreq => wrreq,
aclr => aclr,
data => data,
rdreq => rdreq,
q => sub_wire0,
wrusedw => sub_wire1,
rdusedw => sub_wire2
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
-- Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
-- Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
-- Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
-- Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
-- Retrieval info: PRIVATE: Clock NUMERIC "4"
-- Retrieval info: PRIVATE: Depth NUMERIC "1024"
-- Retrieval info: PRIVATE: Empty NUMERIC "1"
-- Retrieval info: PRIVATE: Full NUMERIC "1"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
-- Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
-- Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
-- Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
-- Retrieval info: PRIVATE: Optimize NUMERIC "2"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
-- Retrieval info: PRIVATE: UsedW NUMERIC "1"
-- Retrieval info: PRIVATE: Width NUMERIC "16"
-- Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
-- Retrieval info: PRIVATE: diff_widths NUMERIC "1"
-- Retrieval info: PRIVATE: msb_usedw NUMERIC "1"
-- Retrieval info: PRIVATE: output_width NUMERIC "8"
-- Retrieval info: PRIVATE: rsEmpty NUMERIC "0"
-- Retrieval info: PRIVATE: rsFull NUMERIC "0"
-- Retrieval info: PRIVATE: rsUsedW NUMERIC "1"
-- Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
-- Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
-- Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
-- Retrieval info: PRIVATE: wsFull NUMERIC "0"
-- Retrieval info: PRIVATE: wsUsedW NUMERIC "1"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: ADD_USEDW_MSB_BIT STRING "ON"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: CONSTANT: LPM_HINT STRING "MAXIMUM_DEPTH=512"
-- Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "1024"
-- Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo_mixed_widths"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16"
-- Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "11"
-- Retrieval info: CONSTANT: LPM_WIDTHU_R NUMERIC "12"
-- Retrieval info: CONSTANT: LPM_WIDTH_R NUMERIC "8"
-- Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
-- Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "5"
-- Retrieval info: CONSTANT: READ_ACLR_SYNCH STRING "OFF"
-- Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
-- Retrieval info: CONSTANT: USE_EAB STRING "ON"
-- Retrieval info: CONSTANT: WRITE_ACLR_SYNCH STRING "OFF"
-- Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "5"
-- Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND "aclr"
-- Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL "data[15..0]"
-- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
-- Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL "rdclk"
-- Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
-- Retrieval info: USED_PORT: rdusedw 0 0 12 0 OUTPUT NODEFVAL "rdusedw[11..0]"
-- Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL "wrclk"
-- Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
-- Retrieval info: USED_PORT: wrusedw 0 0 11 0 OUTPUT NODEFVAL "wrusedw[10..0]"
-- Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
-- Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0
-- Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
-- Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
-- Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
-- Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 8 0 @q 0 0 8 0
-- Retrieval info: CONNECT: rdusedw 0 0 12 0 @rdusedw 0 0 12 0
-- Retrieval info: CONNECT: wrusedw 0 0 11 0 @wrusedw 0 0 11 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL FIFO_TO_USB.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL FIFO_TO_USB.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL FIFO_TO_USB.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL FIFO_TO_USB.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL FIFO_TO_USB_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
|
-- NEED RESULT: ARCH00291: TIME is predefined correctly passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00291
--
-- AUTHOR:
--
-- D. Hyman
--
-- TEST OBJECTIVES:
--
-- 3.1.3.1 (1)
--
-- DESIGN UNIT ORDERING:
--
-- E00000(ARCH00291)
-- ENT00291_Test_Bench(ARCH00291_Test_Bench)
--
-- REVISION HISTORY:
--
-- 22-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
--
--
use WORK.STANDARD_TYPES.all ;
architecture ARCH00291 of E00000 is
begin
P :
process
begin
test_report ( "ARCH00291" ,
"TIME is predefined correctly" ,
(time'pos(fs) = 1) and
(ps = 1000 fs) and
(ns = 1000 ps) and
(us = 1000 ns) and
(ms = 1000 us) and
(sec = 1000 ms) and
(min = 60 sec) and
(hr = 60 min)
) ;
wait ;
end process P ;
end ARCH00291 ;
entity ENT00291_Test_Bench is
end ENT00291_Test_Bench ;
architecture ARCH00291_Test_Bench of ENT00291_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.E00000 ( ARCH00291 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00291_Test_Bench ;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
entity DataPath is
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
Data_Out : out STD_LOGIC_VECTOR(31 downto 0)
);
end DataPath;
architecture Behavioral of DataPath is
component PC is
port (
DAT_in : in std_logic_vector (31 downto 0);
rst : in std_logic;
clk : in std_logic;
DAT_out : out std_logic_vector (31 downto 0)
);
end component PC;
component Sumador is
port (
Operador1 : in std_logic_vector (31 downto 0);
Operador2 : in std_logic_vector (31 downto 0);
Resultado : out std_logic_vector (31 downto 0)
);
end component Sumador;
component IM is
port (
rst : in std_logic;
addr : in std_logic_vector(31 downto 0);
data : out std_logic_vector(31 downto 0)
);
end component IM;
signal addr: std_logic_vector(31 downto 0):= "00000000000000000000000000000000";
signal mid_addr: std_logic_vector(31 downto 0):= "00000000000000000000000000000000";
signal new_addr: std_logic_vector(31 downto 0):= "00000000000000000000000000000000";
signal aumento: std_logic_vector(31 downto 0) := "00000000000000000000000000000000";
signal instruction: std_logic_vector(31 downto 0);
begin
-- Instantiate nPC
nPC : PC
port map (
rst => rst,
clk => clk,
DAT_in => new_addr,
DAT_out => mid_addr
);
-- Instantiate PC
ProgC : PC
port map (
rst => rst,
clk => clk,
DAT_in => mid_addr,
DAT_out => addr
);
-- Instantiate Sumador
Adder : Sumador
port map (
Operador1 => addr,
Operador2 => aumento,
Resultado => new_addr
);
-- Instantiate IM
Instruction_mem : IM
port map (
rst => rst,
addr => addr,
data => Data_out
);
process(clk)
begin
if rising_edge(clk) then
if (rst = '1') then
aumento <= "00000000000000000000000000000000";
else
aumento <= "00000000000000000000000000000001";
end if;
end if;
end process;
end Behavioral;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
entity DataPath is
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
Data_Out : out STD_LOGIC_VECTOR(31 downto 0)
);
end DataPath;
architecture Behavioral of DataPath is
component PC is
port (
DAT_in : in std_logic_vector (31 downto 0);
rst : in std_logic;
clk : in std_logic;
DAT_out : out std_logic_vector (31 downto 0)
);
end component PC;
component Sumador is
port (
Operador1 : in std_logic_vector (31 downto 0);
Operador2 : in std_logic_vector (31 downto 0);
Resultado : out std_logic_vector (31 downto 0)
);
end component Sumador;
component IM is
port (
rst : in std_logic;
addr : in std_logic_vector(31 downto 0);
data : out std_logic_vector(31 downto 0)
);
end component IM;
signal addr: std_logic_vector(31 downto 0):= "00000000000000000000000000000000";
signal mid_addr: std_logic_vector(31 downto 0):= "00000000000000000000000000000000";
signal new_addr: std_logic_vector(31 downto 0):= "00000000000000000000000000000000";
signal aumento: std_logic_vector(31 downto 0) := "00000000000000000000000000000000";
signal instruction: std_logic_vector(31 downto 0);
begin
-- Instantiate nPC
nPC : PC
port map (
rst => rst,
clk => clk,
DAT_in => new_addr,
DAT_out => mid_addr
);
-- Instantiate PC
ProgC : PC
port map (
rst => rst,
clk => clk,
DAT_in => mid_addr,
DAT_out => addr
);
-- Instantiate Sumador
Adder : Sumador
port map (
Operador1 => addr,
Operador2 => aumento,
Resultado => new_addr
);
-- Instantiate IM
Instruction_mem : IM
port map (
rst => rst,
addr => addr,
data => Data_out
);
process(clk)
begin
if rising_edge(clk) then
if (rst = '1') then
aumento <= "00000000000000000000000000000000";
else
aumento <= "00000000000000000000000000000001";
end if;
end if;
end process;
end Behavioral;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
entity DataPath is
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
Data_Out : out STD_LOGIC_VECTOR(31 downto 0)
);
end DataPath;
architecture Behavioral of DataPath is
component PC is
port (
DAT_in : in std_logic_vector (31 downto 0);
rst : in std_logic;
clk : in std_logic;
DAT_out : out std_logic_vector (31 downto 0)
);
end component PC;
component Sumador is
port (
Operador1 : in std_logic_vector (31 downto 0);
Operador2 : in std_logic_vector (31 downto 0);
Resultado : out std_logic_vector (31 downto 0)
);
end component Sumador;
component IM is
port (
rst : in std_logic;
addr : in std_logic_vector(31 downto 0);
data : out std_logic_vector(31 downto 0)
);
end component IM;
signal addr: std_logic_vector(31 downto 0):= "00000000000000000000000000000000";
signal mid_addr: std_logic_vector(31 downto 0):= "00000000000000000000000000000000";
signal new_addr: std_logic_vector(31 downto 0):= "00000000000000000000000000000000";
signal aumento: std_logic_vector(31 downto 0) := "00000000000000000000000000000000";
signal instruction: std_logic_vector(31 downto 0);
begin
-- Instantiate nPC
nPC : PC
port map (
rst => rst,
clk => clk,
DAT_in => new_addr,
DAT_out => mid_addr
);
-- Instantiate PC
ProgC : PC
port map (
rst => rst,
clk => clk,
DAT_in => mid_addr,
DAT_out => addr
);
-- Instantiate Sumador
Adder : Sumador
port map (
Operador1 => addr,
Operador2 => aumento,
Resultado => new_addr
);
-- Instantiate IM
Instruction_mem : IM
port map (
rst => rst,
addr => addr,
data => Data_out
);
process(clk)
begin
if rising_edge(clk) then
if (rst = '1') then
aumento <= "00000000000000000000000000000000";
else
aumento <= "00000000000000000000000000000001";
end if;
end if;
end process;
end Behavioral;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1633.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s12b00x00p05n01i01633ent IS
END c08s12b00x00p05n01i01633ent;
ARCHITECTURE c08s12b00x00p05n01i01633arch OF c08s12b00x00p05n01i01633ent IS
BEGIN
TESTING: PROCESS
type AR2 is array (0 to 2) of BIT;
function K return AR2 is
begin
return (1 => '1', others => '0');
end K;
variable kk : AR2;
BEGIN
kk := K;
assert (kk = "010")
report "***FAILED TEST: c08s12b00x00p05n01i01633 - The return type must be the same base tyep declared in the specification of the function."
severity ERROR;
assert NOT(kk = "010")
report "***PASSED TEST: c08s12b00x00p05n01i01633"
severity NOTE;
wait;
END PROCESS TESTING;
END c08s12b00x00p05n01i01633arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1633.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s12b00x00p05n01i01633ent IS
END c08s12b00x00p05n01i01633ent;
ARCHITECTURE c08s12b00x00p05n01i01633arch OF c08s12b00x00p05n01i01633ent IS
BEGIN
TESTING: PROCESS
type AR2 is array (0 to 2) of BIT;
function K return AR2 is
begin
return (1 => '1', others => '0');
end K;
variable kk : AR2;
BEGIN
kk := K;
assert (kk = "010")
report "***FAILED TEST: c08s12b00x00p05n01i01633 - The return type must be the same base tyep declared in the specification of the function."
severity ERROR;
assert NOT(kk = "010")
report "***PASSED TEST: c08s12b00x00p05n01i01633"
severity NOTE;
wait;
END PROCESS TESTING;
END c08s12b00x00p05n01i01633arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1633.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s12b00x00p05n01i01633ent IS
END c08s12b00x00p05n01i01633ent;
ARCHITECTURE c08s12b00x00p05n01i01633arch OF c08s12b00x00p05n01i01633ent IS
BEGIN
TESTING: PROCESS
type AR2 is array (0 to 2) of BIT;
function K return AR2 is
begin
return (1 => '1', others => '0');
end K;
variable kk : AR2;
BEGIN
kk := K;
assert (kk = "010")
report "***FAILED TEST: c08s12b00x00p05n01i01633 - The return type must be the same base tyep declared in the specification of the function."
severity ERROR;
assert NOT(kk = "010")
report "***PASSED TEST: c08s12b00x00p05n01i01633"
severity NOTE;
wait;
END PROCESS TESTING;
END c08s12b00x00p05n01i01633arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc763.vhd,v 1.2 2001-10-26 16:30:00 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c01s01b01x01p05n02i00763pkg is
--UNCONSTRAINED ARRAY OF TYPES FROM STANDARD PACKAGE
--Index type is natural
type boolean_vector is array (natural range <>) of boolean;
type severity_level_vector is array (natural range <>) of severity_level;
type integer_vector is array (natural range <>) of integer;
type real_vector is array (natural range <>) of real;
type time_vector is array (natural range <>) of time;
type natural_vector is array (natural range <>) of natural;
type positive_vector is array (natural range <>) of positive;
--CONSTRAINED ARRAY OF TYPES FROM STANDARD PACKAGE
--Index type is natural
subtype boolean_vector_st is boolean_vector(0 to 15);
subtype severity_level_vector_st is severity_level_vector(0 to 15);
subtype integer_vector_st is integer_vector(0 to 15);
subtype real_vector_st is real_vector(0 to 15);
subtype time_vector_st is time_vector(0 to 15);
subtype natural_vector_st is natural_vector(0 to 15);
subtype positive_vector_st is positive_vector(0 to 15);
constant C1 : boolean := true;
constant C2 : bit := '1';
constant C3 : character := 's';
constant C4 : severity_level:= note;
constant C5 : integer := 3;
constant C6 : real := 3.0;
constant C7 : time := 3 ns;
constant C8 : natural := 1;
constant C9 : positive := 1;
constant C70 : boolean_vector_st :=(others => C1);
constant C71 : severity_level_vector_st :=(others => C4);
constant C72 : integer_vector_st :=(others => C5);
constant C73 : real_vector_st :=(others => C6);
constant C74 : time_vector_st :=(others => C7);
constant C75 : natural_vector_st :=(others => C8);
constant C76 : positive_vector_st :=(others => C9);
end c01s01b01x01p05n02i00763pkg;
use work.c01s01b01x01p05n02i00763pkg.ALL;
ENTITY c01s01b01x01p05n02i00763ent IS
generic(
zero : integer := 0;
one : integer := 1;
two : integer := 2;
three : integer := 3;
four : integer := 4;
five : integer := 5;
six : integer := 6;
seven : integer := 7;
eight : integer := 8;
nine : integer := 9;
fifteen :integer:= 15;
Cgen1 : boolean := true;
Cgen2 : bit := '1';
Cgen3 : character := 's';
Cgen4 : severity_level := note;
Cgen5 : integer := 3;
Cgen6 : real := 3.0;
Cgen7 : time := 3 ns;
Cgen8 : natural := 1;
Cgen9 : positive := 1;
Cgen70 : boolean_vector_st :=(others => true);
Cgen71 : severity_level_vector_st :=(others => note);
Cgen72 : integer_vector_st :=(others => 3);
Cgen73 : real_vector_st :=(others => 3.0);
Cgen74 : time_vector_st :=(others => 3 ns);
Cgen75 : natural_vector_st :=(others => 1);
Cgen76 : positive_vector_st :=(others => 1)
);
END c01s01b01x01p05n02i00763ent;
ARCHITECTURE c01s01b01x01p05n02i00763arch OF c01s01b01x01p05n02i00763ent IS
signal Vgen1 : boolean := true;
signal Vgen2 : bit := '1';
signal Vgen3 : character := 's';
signal Vgen4 : severity_level:= note;
signal Vgen5 : integer := 3;
signal Vgen6 : real := 3.0;
signal Vgen7 : time := 3 ns;
signal Vgen8 : natural := 1;
signal Vgen9 : positive := 1;
signal Vgen70 : boolean_vector_st :=(others => Cgen1);
signal Vgen71 : severity_level_vector_st :=(others => Cgen4);
signal Vgen72 : integer_vector_st :=(others => Cgen5);
signal Vgen73 : real_vector_st :=(others => Cgen6);
signal Vgen74 : time_vector_st :=(others => Cgen7);
signal Vgen75 : natural_vector_st :=(others => Cgen8);
signal Vgen76 : positive_vector_st :=(others => Cgen9);
BEGIN
assert Vgen1 = C1 report "Initializing signal with generic Vgen1 does not work" severity error;
assert Vgen2 = C2 report "Initializing signal with generic Vgen2 does not work" severity error;
assert Vgen3 = C3 report "Initializing signal with generic Vgen3 does not work" severity error;
assert Vgen4 = C4 report "Initializing signal with generic Vgen4 does not work" severity error;
assert Vgen5 = C5 report "Initializing signal with generic Vgen5 does not work" severity error;
assert Vgen6 = C6 report "Initializing signal with generic Vgen6 does not work" severity error;
assert Vgen7 = C7 report "Initializing signal with generic Vgen7 does not work" severity error;
assert Vgen8 = C8 report "Initializing signal with generic Vgen8 does not work" severity error;
assert Vgen9 = C9 report "Initializing signal with generic Vgen9 does not work" severity error;
assert Vgen70 = C70 report "Initializing signal with generic Vgen70 does not work" severity error;
assert Vgen71 = C71 report "Initializing signal with generic Vgen71 does not work" severity error;
assert Vgen72 = C72 report "Initializing signal with generic Vgen72 does not work" severity error;
assert Vgen73 = C73 report "Initializing signal with generic Vgen73 does not work" severity error;
assert Vgen74 = C74 report "Initializing signal with generic Vgen74 does not work" severity error;
assert Vgen75 = C75 report "Initializing signal with generic Vgen75 does not work" severity error;
assert Vgen76 = C76 report "Initializing signal with generic Vgen76 does not work" severity error;
TESTING: PROCESS
BEGIN
assert NOT( Vgen1 = C1 and
Vgen2 = C2 and
Vgen3 = C3 and
Vgen4 = C4 and
Vgen5 = C5 and
Vgen6 = C6 and
Vgen7 = C7 and
Vgen8 = C8 and
Vgen9 = C9 and
Vgen70 = C70 and
Vgen71 = C71 and
Vgen72 = C72 and
Vgen73 = C73 and
Vgen74 = C74 and
Vgen75 = C75 and
Vgen76 = C76 )
report "***PASSED TEST: c01s01b01x01p05n02i00763"
severity NOTE;
assert( Vgen1 = C1 and
Vgen2 = C2 and
Vgen3 = C3 and
Vgen4 = C4 and
Vgen5 = C5 and
Vgen6 = C6 and
Vgen7 = C7 and
Vgen8 = C8 and
Vgen9 = C9 and
Vgen70 = C70 and
Vgen71 = C71 and
Vgen72 = C72 and
Vgen73 = C73 and
Vgen74 = C74 and
Vgen75 = C75 and
Vgen76 = C76 )
report "***FAILED TEST: c01s01b01x01p05n02i00763 - Generic can be used to specify the size of ports."
severity ERROR;
wait;
END PROCESS TESTING;
END c01s01b01x01p05n02i00763arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc763.vhd,v 1.2 2001-10-26 16:30:00 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c01s01b01x01p05n02i00763pkg is
--UNCONSTRAINED ARRAY OF TYPES FROM STANDARD PACKAGE
--Index type is natural
type boolean_vector is array (natural range <>) of boolean;
type severity_level_vector is array (natural range <>) of severity_level;
type integer_vector is array (natural range <>) of integer;
type real_vector is array (natural range <>) of real;
type time_vector is array (natural range <>) of time;
type natural_vector is array (natural range <>) of natural;
type positive_vector is array (natural range <>) of positive;
--CONSTRAINED ARRAY OF TYPES FROM STANDARD PACKAGE
--Index type is natural
subtype boolean_vector_st is boolean_vector(0 to 15);
subtype severity_level_vector_st is severity_level_vector(0 to 15);
subtype integer_vector_st is integer_vector(0 to 15);
subtype real_vector_st is real_vector(0 to 15);
subtype time_vector_st is time_vector(0 to 15);
subtype natural_vector_st is natural_vector(0 to 15);
subtype positive_vector_st is positive_vector(0 to 15);
constant C1 : boolean := true;
constant C2 : bit := '1';
constant C3 : character := 's';
constant C4 : severity_level:= note;
constant C5 : integer := 3;
constant C6 : real := 3.0;
constant C7 : time := 3 ns;
constant C8 : natural := 1;
constant C9 : positive := 1;
constant C70 : boolean_vector_st :=(others => C1);
constant C71 : severity_level_vector_st :=(others => C4);
constant C72 : integer_vector_st :=(others => C5);
constant C73 : real_vector_st :=(others => C6);
constant C74 : time_vector_st :=(others => C7);
constant C75 : natural_vector_st :=(others => C8);
constant C76 : positive_vector_st :=(others => C9);
end c01s01b01x01p05n02i00763pkg;
use work.c01s01b01x01p05n02i00763pkg.ALL;
ENTITY c01s01b01x01p05n02i00763ent IS
generic(
zero : integer := 0;
one : integer := 1;
two : integer := 2;
three : integer := 3;
four : integer := 4;
five : integer := 5;
six : integer := 6;
seven : integer := 7;
eight : integer := 8;
nine : integer := 9;
fifteen :integer:= 15;
Cgen1 : boolean := true;
Cgen2 : bit := '1';
Cgen3 : character := 's';
Cgen4 : severity_level := note;
Cgen5 : integer := 3;
Cgen6 : real := 3.0;
Cgen7 : time := 3 ns;
Cgen8 : natural := 1;
Cgen9 : positive := 1;
Cgen70 : boolean_vector_st :=(others => true);
Cgen71 : severity_level_vector_st :=(others => note);
Cgen72 : integer_vector_st :=(others => 3);
Cgen73 : real_vector_st :=(others => 3.0);
Cgen74 : time_vector_st :=(others => 3 ns);
Cgen75 : natural_vector_st :=(others => 1);
Cgen76 : positive_vector_st :=(others => 1)
);
END c01s01b01x01p05n02i00763ent;
ARCHITECTURE c01s01b01x01p05n02i00763arch OF c01s01b01x01p05n02i00763ent IS
signal Vgen1 : boolean := true;
signal Vgen2 : bit := '1';
signal Vgen3 : character := 's';
signal Vgen4 : severity_level:= note;
signal Vgen5 : integer := 3;
signal Vgen6 : real := 3.0;
signal Vgen7 : time := 3 ns;
signal Vgen8 : natural := 1;
signal Vgen9 : positive := 1;
signal Vgen70 : boolean_vector_st :=(others => Cgen1);
signal Vgen71 : severity_level_vector_st :=(others => Cgen4);
signal Vgen72 : integer_vector_st :=(others => Cgen5);
signal Vgen73 : real_vector_st :=(others => Cgen6);
signal Vgen74 : time_vector_st :=(others => Cgen7);
signal Vgen75 : natural_vector_st :=(others => Cgen8);
signal Vgen76 : positive_vector_st :=(others => Cgen9);
BEGIN
assert Vgen1 = C1 report "Initializing signal with generic Vgen1 does not work" severity error;
assert Vgen2 = C2 report "Initializing signal with generic Vgen2 does not work" severity error;
assert Vgen3 = C3 report "Initializing signal with generic Vgen3 does not work" severity error;
assert Vgen4 = C4 report "Initializing signal with generic Vgen4 does not work" severity error;
assert Vgen5 = C5 report "Initializing signal with generic Vgen5 does not work" severity error;
assert Vgen6 = C6 report "Initializing signal with generic Vgen6 does not work" severity error;
assert Vgen7 = C7 report "Initializing signal with generic Vgen7 does not work" severity error;
assert Vgen8 = C8 report "Initializing signal with generic Vgen8 does not work" severity error;
assert Vgen9 = C9 report "Initializing signal with generic Vgen9 does not work" severity error;
assert Vgen70 = C70 report "Initializing signal with generic Vgen70 does not work" severity error;
assert Vgen71 = C71 report "Initializing signal with generic Vgen71 does not work" severity error;
assert Vgen72 = C72 report "Initializing signal with generic Vgen72 does not work" severity error;
assert Vgen73 = C73 report "Initializing signal with generic Vgen73 does not work" severity error;
assert Vgen74 = C74 report "Initializing signal with generic Vgen74 does not work" severity error;
assert Vgen75 = C75 report "Initializing signal with generic Vgen75 does not work" severity error;
assert Vgen76 = C76 report "Initializing signal with generic Vgen76 does not work" severity error;
TESTING: PROCESS
BEGIN
assert NOT( Vgen1 = C1 and
Vgen2 = C2 and
Vgen3 = C3 and
Vgen4 = C4 and
Vgen5 = C5 and
Vgen6 = C6 and
Vgen7 = C7 and
Vgen8 = C8 and
Vgen9 = C9 and
Vgen70 = C70 and
Vgen71 = C71 and
Vgen72 = C72 and
Vgen73 = C73 and
Vgen74 = C74 and
Vgen75 = C75 and
Vgen76 = C76 )
report "***PASSED TEST: c01s01b01x01p05n02i00763"
severity NOTE;
assert( Vgen1 = C1 and
Vgen2 = C2 and
Vgen3 = C3 and
Vgen4 = C4 and
Vgen5 = C5 and
Vgen6 = C6 and
Vgen7 = C7 and
Vgen8 = C8 and
Vgen9 = C9 and
Vgen70 = C70 and
Vgen71 = C71 and
Vgen72 = C72 and
Vgen73 = C73 and
Vgen74 = C74 and
Vgen75 = C75 and
Vgen76 = C76 )
report "***FAILED TEST: c01s01b01x01p05n02i00763 - Generic can be used to specify the size of ports."
severity ERROR;
wait;
END PROCESS TESTING;
END c01s01b01x01p05n02i00763arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc763.vhd,v 1.2 2001-10-26 16:30:00 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c01s01b01x01p05n02i00763pkg is
--UNCONSTRAINED ARRAY OF TYPES FROM STANDARD PACKAGE
--Index type is natural
type boolean_vector is array (natural range <>) of boolean;
type severity_level_vector is array (natural range <>) of severity_level;
type integer_vector is array (natural range <>) of integer;
type real_vector is array (natural range <>) of real;
type time_vector is array (natural range <>) of time;
type natural_vector is array (natural range <>) of natural;
type positive_vector is array (natural range <>) of positive;
--CONSTRAINED ARRAY OF TYPES FROM STANDARD PACKAGE
--Index type is natural
subtype boolean_vector_st is boolean_vector(0 to 15);
subtype severity_level_vector_st is severity_level_vector(0 to 15);
subtype integer_vector_st is integer_vector(0 to 15);
subtype real_vector_st is real_vector(0 to 15);
subtype time_vector_st is time_vector(0 to 15);
subtype natural_vector_st is natural_vector(0 to 15);
subtype positive_vector_st is positive_vector(0 to 15);
constant C1 : boolean := true;
constant C2 : bit := '1';
constant C3 : character := 's';
constant C4 : severity_level:= note;
constant C5 : integer := 3;
constant C6 : real := 3.0;
constant C7 : time := 3 ns;
constant C8 : natural := 1;
constant C9 : positive := 1;
constant C70 : boolean_vector_st :=(others => C1);
constant C71 : severity_level_vector_st :=(others => C4);
constant C72 : integer_vector_st :=(others => C5);
constant C73 : real_vector_st :=(others => C6);
constant C74 : time_vector_st :=(others => C7);
constant C75 : natural_vector_st :=(others => C8);
constant C76 : positive_vector_st :=(others => C9);
end c01s01b01x01p05n02i00763pkg;
use work.c01s01b01x01p05n02i00763pkg.ALL;
ENTITY c01s01b01x01p05n02i00763ent IS
generic(
zero : integer := 0;
one : integer := 1;
two : integer := 2;
three : integer := 3;
four : integer := 4;
five : integer := 5;
six : integer := 6;
seven : integer := 7;
eight : integer := 8;
nine : integer := 9;
fifteen :integer:= 15;
Cgen1 : boolean := true;
Cgen2 : bit := '1';
Cgen3 : character := 's';
Cgen4 : severity_level := note;
Cgen5 : integer := 3;
Cgen6 : real := 3.0;
Cgen7 : time := 3 ns;
Cgen8 : natural := 1;
Cgen9 : positive := 1;
Cgen70 : boolean_vector_st :=(others => true);
Cgen71 : severity_level_vector_st :=(others => note);
Cgen72 : integer_vector_st :=(others => 3);
Cgen73 : real_vector_st :=(others => 3.0);
Cgen74 : time_vector_st :=(others => 3 ns);
Cgen75 : natural_vector_st :=(others => 1);
Cgen76 : positive_vector_st :=(others => 1)
);
END c01s01b01x01p05n02i00763ent;
ARCHITECTURE c01s01b01x01p05n02i00763arch OF c01s01b01x01p05n02i00763ent IS
signal Vgen1 : boolean := true;
signal Vgen2 : bit := '1';
signal Vgen3 : character := 's';
signal Vgen4 : severity_level:= note;
signal Vgen5 : integer := 3;
signal Vgen6 : real := 3.0;
signal Vgen7 : time := 3 ns;
signal Vgen8 : natural := 1;
signal Vgen9 : positive := 1;
signal Vgen70 : boolean_vector_st :=(others => Cgen1);
signal Vgen71 : severity_level_vector_st :=(others => Cgen4);
signal Vgen72 : integer_vector_st :=(others => Cgen5);
signal Vgen73 : real_vector_st :=(others => Cgen6);
signal Vgen74 : time_vector_st :=(others => Cgen7);
signal Vgen75 : natural_vector_st :=(others => Cgen8);
signal Vgen76 : positive_vector_st :=(others => Cgen9);
BEGIN
assert Vgen1 = C1 report "Initializing signal with generic Vgen1 does not work" severity error;
assert Vgen2 = C2 report "Initializing signal with generic Vgen2 does not work" severity error;
assert Vgen3 = C3 report "Initializing signal with generic Vgen3 does not work" severity error;
assert Vgen4 = C4 report "Initializing signal with generic Vgen4 does not work" severity error;
assert Vgen5 = C5 report "Initializing signal with generic Vgen5 does not work" severity error;
assert Vgen6 = C6 report "Initializing signal with generic Vgen6 does not work" severity error;
assert Vgen7 = C7 report "Initializing signal with generic Vgen7 does not work" severity error;
assert Vgen8 = C8 report "Initializing signal with generic Vgen8 does not work" severity error;
assert Vgen9 = C9 report "Initializing signal with generic Vgen9 does not work" severity error;
assert Vgen70 = C70 report "Initializing signal with generic Vgen70 does not work" severity error;
assert Vgen71 = C71 report "Initializing signal with generic Vgen71 does not work" severity error;
assert Vgen72 = C72 report "Initializing signal with generic Vgen72 does not work" severity error;
assert Vgen73 = C73 report "Initializing signal with generic Vgen73 does not work" severity error;
assert Vgen74 = C74 report "Initializing signal with generic Vgen74 does not work" severity error;
assert Vgen75 = C75 report "Initializing signal with generic Vgen75 does not work" severity error;
assert Vgen76 = C76 report "Initializing signal with generic Vgen76 does not work" severity error;
TESTING: PROCESS
BEGIN
assert NOT( Vgen1 = C1 and
Vgen2 = C2 and
Vgen3 = C3 and
Vgen4 = C4 and
Vgen5 = C5 and
Vgen6 = C6 and
Vgen7 = C7 and
Vgen8 = C8 and
Vgen9 = C9 and
Vgen70 = C70 and
Vgen71 = C71 and
Vgen72 = C72 and
Vgen73 = C73 and
Vgen74 = C74 and
Vgen75 = C75 and
Vgen76 = C76 )
report "***PASSED TEST: c01s01b01x01p05n02i00763"
severity NOTE;
assert( Vgen1 = C1 and
Vgen2 = C2 and
Vgen3 = C3 and
Vgen4 = C4 and
Vgen5 = C5 and
Vgen6 = C6 and
Vgen7 = C7 and
Vgen8 = C8 and
Vgen9 = C9 and
Vgen70 = C70 and
Vgen71 = C71 and
Vgen72 = C72 and
Vgen73 = C73 and
Vgen74 = C74 and
Vgen75 = C75 and
Vgen76 = C76 )
report "***FAILED TEST: c01s01b01x01p05n02i00763 - Generic can be used to specify the size of ports."
severity ERROR;
wait;
END PROCESS TESTING;
END c01s01b01x01p05n02i00763arch;
|
library ieee;
use ieee.std_logic_1164.all;
package subp_type_decl is
constant NBITS: natural := 6;
function mod5 (dividend: std_logic_vector) return std_logic;
end package;
package body subp_type_decl is
function mod5 (dividend: std_logic_vector) return std_logic is
type remains is (r0, r1, r2, r3, r4); -- remainder values
type remain_array is array (NBITS downto 0) of remains;
type branch is array (remains, bit) of remains;
constant br_table: branch := ( r0 => ('0' => r0, '1' => r1),
r1 => ('0' => r2, '1' => r3),
r2 => ('0' => r4, '1' => r0),
r3 => ('0' => r1, '1' => r2),
r4 => ('0' => r3, '1' => r4)
);
variable remaind: remain_array := (others => r0);
variable tbit: bit_vector (NBITS - 1 downto 0);
begin
tbit := to_bitvector(dividend); -- little endian
for i in dividend'length - 1 downto 0 loop
remaind(i) := br_table(remaind(i + 1),tbit(i));
end loop;
if remaind(0) = r0 then
return '1';
else
return '0';
end if;
end function;
end package body;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.subp_type_decl.all;
entity func_test1 is
end entity;
architecture fum of func_test1 is
signal dividend: std_logic_vector (NBITS - 1 downto 0);
begin
process
variable errors: natural;
begin
errors := 0;
for i in 0 to 2 ** NBITS - 1 loop
dividend <= std_logic_vector(to_unsigned(i, NBITS));
wait for 0 ns;
report "mod5 (" & integer'image(i) & ") = " &
std_ulogic'image(mod5(dividend));
end loop;
wait;
end process;
end architecture;
|
----------------------------------------------------------------------------------
-- Project Name: Frecuency Counter
-- Target Devices: Spartan 3
-- Engineers: Ángel Larrañaga Muro
-- Nicolás Jurado Jiménez
-- Gonzalo Matarrubia Gonzalez
-- License: All files included in this proyect are licensed under a Creative Commons Attribution-ShareAlike 4.0 International License
----------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY ConversorBinToBCD_TB IS
END ConversorBinToBCD_TB;
ARCHITECTURE behavior OF ConversorBinToBCD_TB IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT bcd
PORT(
entrada_bin : IN std_logic_vector(15 downto 0);
millares : OUT std_logic_vector(3 downto 0);
centenas : OUT std_logic_vector(3 downto 0);
decenas : OUT std_logic_vector(3 downto 0);
unidades : OUT std_logic_vector(3 downto 0)
);
END COMPONENT;
--Inputs
signal entrada_bin : std_logic_vector(15 downto 0) := (others => '0');
--Outputs
signal millares : std_logic_vector(3 downto 0);
signal centenas : std_logic_vector(3 downto 0);
signal decenas : std_logic_vector(3 downto 0);
signal unidades : std_logic_vector(3 downto 0);
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: bcd PORT MAP (
entrada_bin => entrada_bin,
millares => millares,
centenas => centenas,
decenas => decenas,
unidades => unidades
);
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
entrada_bin<="0001111100101101";
-- insert stimulus here
wait;
end process;
END;
|
----------------------------------------------------------------------------------
-- Project Name: Frecuency Counter
-- Target Devices: Spartan 3
-- Engineers: Ángel Larrañaga Muro
-- Nicolás Jurado Jiménez
-- Gonzalo Matarrubia Gonzalez
-- License: All files included in this proyect are licensed under a Creative Commons Attribution-ShareAlike 4.0 International License
----------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY ConversorBinToBCD_TB IS
END ConversorBinToBCD_TB;
ARCHITECTURE behavior OF ConversorBinToBCD_TB IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT bcd
PORT(
entrada_bin : IN std_logic_vector(15 downto 0);
millares : OUT std_logic_vector(3 downto 0);
centenas : OUT std_logic_vector(3 downto 0);
decenas : OUT std_logic_vector(3 downto 0);
unidades : OUT std_logic_vector(3 downto 0)
);
END COMPONENT;
--Inputs
signal entrada_bin : std_logic_vector(15 downto 0) := (others => '0');
--Outputs
signal millares : std_logic_vector(3 downto 0);
signal centenas : std_logic_vector(3 downto 0);
signal decenas : std_logic_vector(3 downto 0);
signal unidades : std_logic_vector(3 downto 0);
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: bcd PORT MAP (
entrada_bin => entrada_bin,
millares => millares,
centenas => centenas,
decenas => decenas,
unidades => unidades
);
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
entrada_bin<="0001111100101101";
-- insert stimulus here
wait;
end process;
END;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.package0.max;
entity ent is
port(
sig : out std_logic_vector(max(10, 20) - 1 downto 0)
);
end entity ent;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: sdrtestmod
-- File: sdrtestmod.vhd
-- Author: Magnus Hjorth - Aeroflex Gaisler
-- Description: Test report module with SDRAM interface
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
use grlib.devices.all;
library gaisler;
use gaisler.sim.all;
entity sdrtestmod is
generic (
width: integer := 32; -- 32-bit or 64-bit supported
bank: integer range 0 to 3 := 0;
row: integer := 0;
halt: integer range 0 to 1 := 1;
swwidth: integer := 32 -- Internal reportdev size, can be 32/64
);
port (
clk: in std_ulogic;
csn: in std_ulogic;
rasn: in std_ulogic;
casn: in std_ulogic;
wen: in std_ulogic;
ba: in std_logic_vector(1 downto 0);
addr: in std_logic_vector(12 downto 0);
dq: inout std_logic_vector(width-1 downto 0);
dqm: in std_logic_vector(width/8-1 downto 0)
);
end;
architecture sim of sdrtestmod is
begin
dq <= (others => 'Z');
p: process(clk)
variable modereg: std_logic_vector(12 downto 0);
variable myrow: boolean := false;
variable wrburst: integer := 0;
variable wrcol: integer;
variable i,j,k: integer;
variable d: std_logic_vector(31 downto 0);
variable errcnt, vendorid, deviceid : integer;
procedure write_main(addr: integer; d: std_logic_vector) is
variable errno, subtest : integer;
begin
case i is
when 0 =>
vendorid := conv_integer(d(31 downto 24));
deviceid := conv_integer(d(23 downto 12));
print(iptable(vendorid).device_table(deviceid));
when 1 =>
errno := conv_integer(d(15 downto 0));
if (halt = 1) then
assert false
report "test failed, error (" & tost(errno) & ")"
severity failure;
else
assert false
report "test failed, error (" & tost(errno) & ")"
severity warning;
end if;
when 2 =>
subtest := conv_integer(d(7 downto 0));
call_subtest(vendorid, deviceid, subtest);
when 4 =>
print ("");
print ("**** GRLIB system test starting ****");
errcnt := 0;
when 5 =>
if errcnt = 0 then
print ("Test passed, halting with IU error mode");
elsif errcnt = 1 then
print ("1 error detected, halting with IU error mode");
else
print (tost(errcnt) & " errors detected, halting with IU error mode");
end if;
print ("");
when 6 =>
grlib.testlib.print("Checkpoint " & tost(conv_integer(d(15 downto 0))));
when 7 =>
vendorid := 0; deviceid := 0;
print ("Basic memory test");
when others =>
end case;
end write_main;
begin
if rising_edge(clk) then
if csn='0' then
if rasn='0' and casn='0' and wen='0' then
modereg := addr;
elsif rasn='0' and casn='1' and wen='1' then
if ba=conv_std_logic_vector(bank,2) and addr=conv_std_logic_vector(row,13) then
myrow := true;
else
myrow := false;
end if;
elsif rasn='1' and casn='0' and wen='0' then
if myrow then
if modereg(9)='0' and modereg(2 downto 0)="001" then
wrburst := 2;
elsif modereg(9)='0' and modereg(2 downto 0)="010" then
wrburst := 4;
elsif modereg(9)='0' and (modereg(2 downto 0)="011" or modereg(2)='1') then
wrburst := 8;
else
wrburst := 1;
end if;
wrcol := conv_integer(addr(7 downto 0));
end if;
elsif rasn='0' and casn='1' and wen='0' then
if ba=conv_std_logic_vector(bank,2) or addr(10)='1' then
myrow := false;
wrburst := 0;
end if;
end if;
end if;
if wrburst > 0 then
for x in 0 to (width/32)-1 loop
if width=32 and swwidth=64 and (wrcol mod 2 < 1) then next; end if;
if width=64 and swwidth=64 and x=0 then next; end if;
if dqm(width/8-1-x*4 downto width/8-4-x*4) = "0000" then
i := (wrcol*width)/swwidth + (x*32)/swwidth;
d := dq(width-1-x*32 downto width-32-x*32);
if d /= x"DEADBEEF" then
write_main(i,d);
end if;
end if;
end loop;
wrburst := wrburst-1;
wrcol := wrcol+1;
end if;
end if;
end process;
end;
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Mon Feb 20 13:53:00 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub
-- c:/ZyboIP/general_ip/affine_transform/affine_transform.srcs/sources_1/bd/affine_block/ip/affine_block_ieee754_fp_multiplier_0_0/affine_block_ieee754_fp_multiplier_0_0_stub.vhdl
-- Design : affine_block_ieee754_fp_multiplier_0_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z010clg400-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity affine_block_ieee754_fp_multiplier_0_0 is
Port (
x : in STD_LOGIC_VECTOR ( 31 downto 0 );
y : in STD_LOGIC_VECTOR ( 31 downto 0 );
z : out STD_LOGIC_VECTOR ( 31 downto 0 )
);
end affine_block_ieee754_fp_multiplier_0_0;
architecture stub of affine_block_ieee754_fp_multiplier_0_0 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "x[31:0],y[31:0],z[31:0]";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "ieee754_fp_multiplier,Vivado 2016.4";
begin
end;
|
library ieee;
use ieee.std_logic_1164.all;
entity uart_peripheral is
generic (
tx_fifo : boolean := true;
divisor : natural := 417 );
port (
clock : in std_logic;
reset : in std_logic;
bus_select : in std_logic;
bus_write : in std_logic;
bus_addr : in std_logic_vector(1 downto 0);
bus_wdata : in std_logic_vector(7 downto 0);
bus_rdata : out std_logic_vector(7 downto 0);
uart_irq : out std_logic;
txd : out std_logic;
rxd : in std_logic );
end uart_peripheral;
architecture gideon of uart_peripheral is
signal dotx : std_logic;
signal done : std_logic;
signal rxchar : std_logic_vector(7 downto 0);
signal rx_ack : std_logic;
signal rxfifo_get : std_logic;
signal rxfifo_dout : std_logic_vector(7 downto 0);
signal rxfifo_full : std_logic;
signal rxfifo_dav : std_logic;
signal overflow : std_logic;
signal flags : std_logic_vector(7 downto 0);
signal imask : std_logic_vector(7 downto 6);
signal txfifo_get : std_logic;
signal txfifo_put : std_logic;
signal txfifo_dout : std_logic_vector(7 downto 0);
signal txfifo_full : std_logic := '1';
signal txfifo_dav : std_logic;
signal dotx_d : std_logic;
signal txchar : std_logic_vector(7 downto 0);
begin
my_tx: entity work.tx
generic map (divisor)
port map (
clk => clock,
reset => reset,
dotx => dotx,
txchar => txchar,
txd => txd,
done => done );
my_rx: entity work.rx
generic map (divisor)
port map (
clk => clock,
reset => reset,
rxd => rxd,
rxchar => rxchar,
rx_ack => rx_ack );
my_rxfifo: entity work.srl_fifo
generic map (
Width => 8,
Threshold => 12 )
port map (
clock => clock,
reset => reset,
GetElement => rxfifo_get,
PutElement => rx_ack,
FlushFifo => '0',
DataIn => rxchar,
DataOut => rxfifo_dout,
SpaceInFifo => open,
AlmostFull => rxfifo_full,
DataInFifo => rxfifo_dav );
gentx: if tx_fifo generate
my_txfifo: entity work.srl_fifo
generic map (
Width => 8,
Threshold => 12 )
port map (
clock => clock,
reset => reset,
GetElement => txfifo_get,
PutElement => txfifo_put,
FlushFifo => '0',
DataIn => bus_wdata,
DataOut => txfifo_dout,
SpaceInFifo => open,
AlmostFull => txfifo_full,
DataInFifo => txfifo_dav );
end generate;
process(bus_select, bus_write, bus_addr, txfifo_dav, bus_wdata, txfifo_dout, done)
begin
if not tx_fifo then
txfifo_put <= '0';
txchar <= bus_wdata;
if bus_select='1' and bus_write='1' and bus_addr="00" then
dotx <= '1';
else
dotx <= '0';
end if;
else -- there is a fifo
dotx <= txfifo_dav and done;
txchar <= txfifo_dout;
if bus_select='1' and bus_write='1' and bus_addr="00" then
txfifo_put <= '1';
else
txfifo_put <= '0';
end if;
end if;
end process;
process(clock)
begin
if rising_edge(clock) then
rxfifo_get <= '0';
dotx_d <= dotx;
txfifo_get <= dotx_d;
if rxfifo_full='1' and rx_ack='1' then
overflow <= '1';
end if;
if bus_select='1' and bus_write='1' then
case bus_addr is
when "00" => -- dout
null; -- covered by combi statement
when "01" => -- din
rxfifo_get <= '1';
when "10" => -- clear flags
overflow <= overflow and not bus_wdata(0);
when "11" => -- interrupt control
imask <= bus_wdata(7 downto 6);
when others =>
null;
end case;
end if;
if reset='1' then
overflow <= '0';
imask <= (others => '0');
end if;
end if;
end process;
flags(0) <= overflow;
flags(1) <= '0';
flags(2) <= '0';
flags(3) <= '0';
flags(4) <= txfifo_full;
flags(5) <= rxfifo_full;
flags(6) <= done;
flags(7) <= rxfifo_dav;
with bus_addr select bus_rdata <=
rxfifo_dout when "00",
flags when "10",
imask & "000000" when "11",
X"00" when others;
uart_irq <= '1' when (flags(7 downto 6) and imask) /= "00" else '0';
end gideon;
|
library ieee;
use ieee.std_logic_1164.all;
entity uart_peripheral is
generic (
tx_fifo : boolean := true;
divisor : natural := 417 );
port (
clock : in std_logic;
reset : in std_logic;
bus_select : in std_logic;
bus_write : in std_logic;
bus_addr : in std_logic_vector(1 downto 0);
bus_wdata : in std_logic_vector(7 downto 0);
bus_rdata : out std_logic_vector(7 downto 0);
uart_irq : out std_logic;
txd : out std_logic;
rxd : in std_logic );
end uart_peripheral;
architecture gideon of uart_peripheral is
signal dotx : std_logic;
signal done : std_logic;
signal rxchar : std_logic_vector(7 downto 0);
signal rx_ack : std_logic;
signal rxfifo_get : std_logic;
signal rxfifo_dout : std_logic_vector(7 downto 0);
signal rxfifo_full : std_logic;
signal rxfifo_dav : std_logic;
signal overflow : std_logic;
signal flags : std_logic_vector(7 downto 0);
signal imask : std_logic_vector(7 downto 6);
signal txfifo_get : std_logic;
signal txfifo_put : std_logic;
signal txfifo_dout : std_logic_vector(7 downto 0);
signal txfifo_full : std_logic := '1';
signal txfifo_dav : std_logic;
signal dotx_d : std_logic;
signal txchar : std_logic_vector(7 downto 0);
begin
my_tx: entity work.tx
generic map (divisor)
port map (
clk => clock,
reset => reset,
dotx => dotx,
txchar => txchar,
txd => txd,
done => done );
my_rx: entity work.rx
generic map (divisor)
port map (
clk => clock,
reset => reset,
rxd => rxd,
rxchar => rxchar,
rx_ack => rx_ack );
my_rxfifo: entity work.srl_fifo
generic map (
Width => 8,
Threshold => 12 )
port map (
clock => clock,
reset => reset,
GetElement => rxfifo_get,
PutElement => rx_ack,
FlushFifo => '0',
DataIn => rxchar,
DataOut => rxfifo_dout,
SpaceInFifo => open,
AlmostFull => rxfifo_full,
DataInFifo => rxfifo_dav );
gentx: if tx_fifo generate
my_txfifo: entity work.srl_fifo
generic map (
Width => 8,
Threshold => 12 )
port map (
clock => clock,
reset => reset,
GetElement => txfifo_get,
PutElement => txfifo_put,
FlushFifo => '0',
DataIn => bus_wdata,
DataOut => txfifo_dout,
SpaceInFifo => open,
AlmostFull => txfifo_full,
DataInFifo => txfifo_dav );
end generate;
process(bus_select, bus_write, bus_addr, txfifo_dav, bus_wdata, txfifo_dout, done)
begin
if not tx_fifo then
txfifo_put <= '0';
txchar <= bus_wdata;
if bus_select='1' and bus_write='1' and bus_addr="00" then
dotx <= '1';
else
dotx <= '0';
end if;
else -- there is a fifo
dotx <= txfifo_dav and done;
txchar <= txfifo_dout;
if bus_select='1' and bus_write='1' and bus_addr="00" then
txfifo_put <= '1';
else
txfifo_put <= '0';
end if;
end if;
end process;
process(clock)
begin
if rising_edge(clock) then
rxfifo_get <= '0';
dotx_d <= dotx;
txfifo_get <= dotx_d;
if rxfifo_full='1' and rx_ack='1' then
overflow <= '1';
end if;
if bus_select='1' and bus_write='1' then
case bus_addr is
when "00" => -- dout
null; -- covered by combi statement
when "01" => -- din
rxfifo_get <= '1';
when "10" => -- clear flags
overflow <= overflow and not bus_wdata(0);
when "11" => -- interrupt control
imask <= bus_wdata(7 downto 6);
when others =>
null;
end case;
end if;
if reset='1' then
overflow <= '0';
imask <= (others => '0');
end if;
end if;
end process;
flags(0) <= overflow;
flags(1) <= '0';
flags(2) <= '0';
flags(3) <= '0';
flags(4) <= txfifo_full;
flags(5) <= rxfifo_full;
flags(6) <= done;
flags(7) <= rxfifo_dav;
with bus_addr select bus_rdata <=
rxfifo_dout when "00",
flags when "10",
imask & "000000" when "11",
X"00" when others;
uart_irq <= '1' when (flags(7 downto 6) and imask) /= "00" else '0';
end gideon;
|
library ieee;
use ieee.std_logic_1164.all;
entity uart_peripheral is
generic (
tx_fifo : boolean := true;
divisor : natural := 417 );
port (
clock : in std_logic;
reset : in std_logic;
bus_select : in std_logic;
bus_write : in std_logic;
bus_addr : in std_logic_vector(1 downto 0);
bus_wdata : in std_logic_vector(7 downto 0);
bus_rdata : out std_logic_vector(7 downto 0);
uart_irq : out std_logic;
txd : out std_logic;
rxd : in std_logic );
end uart_peripheral;
architecture gideon of uart_peripheral is
signal dotx : std_logic;
signal done : std_logic;
signal rxchar : std_logic_vector(7 downto 0);
signal rx_ack : std_logic;
signal rxfifo_get : std_logic;
signal rxfifo_dout : std_logic_vector(7 downto 0);
signal rxfifo_full : std_logic;
signal rxfifo_dav : std_logic;
signal overflow : std_logic;
signal flags : std_logic_vector(7 downto 0);
signal imask : std_logic_vector(7 downto 6);
signal txfifo_get : std_logic;
signal txfifo_put : std_logic;
signal txfifo_dout : std_logic_vector(7 downto 0);
signal txfifo_full : std_logic := '1';
signal txfifo_dav : std_logic;
signal dotx_d : std_logic;
signal txchar : std_logic_vector(7 downto 0);
begin
my_tx: entity work.tx
generic map (divisor)
port map (
clk => clock,
reset => reset,
dotx => dotx,
txchar => txchar,
txd => txd,
done => done );
my_rx: entity work.rx
generic map (divisor)
port map (
clk => clock,
reset => reset,
rxd => rxd,
rxchar => rxchar,
rx_ack => rx_ack );
my_rxfifo: entity work.srl_fifo
generic map (
Width => 8,
Threshold => 12 )
port map (
clock => clock,
reset => reset,
GetElement => rxfifo_get,
PutElement => rx_ack,
FlushFifo => '0',
DataIn => rxchar,
DataOut => rxfifo_dout,
SpaceInFifo => open,
AlmostFull => rxfifo_full,
DataInFifo => rxfifo_dav );
gentx: if tx_fifo generate
my_txfifo: entity work.srl_fifo
generic map (
Width => 8,
Threshold => 12 )
port map (
clock => clock,
reset => reset,
GetElement => txfifo_get,
PutElement => txfifo_put,
FlushFifo => '0',
DataIn => bus_wdata,
DataOut => txfifo_dout,
SpaceInFifo => open,
AlmostFull => txfifo_full,
DataInFifo => txfifo_dav );
end generate;
process(bus_select, bus_write, bus_addr, txfifo_dav, bus_wdata, txfifo_dout, done)
begin
if not tx_fifo then
txfifo_put <= '0';
txchar <= bus_wdata;
if bus_select='1' and bus_write='1' and bus_addr="00" then
dotx <= '1';
else
dotx <= '0';
end if;
else -- there is a fifo
dotx <= txfifo_dav and done;
txchar <= txfifo_dout;
if bus_select='1' and bus_write='1' and bus_addr="00" then
txfifo_put <= '1';
else
txfifo_put <= '0';
end if;
end if;
end process;
process(clock)
begin
if rising_edge(clock) then
rxfifo_get <= '0';
dotx_d <= dotx;
txfifo_get <= dotx_d;
if rxfifo_full='1' and rx_ack='1' then
overflow <= '1';
end if;
if bus_select='1' and bus_write='1' then
case bus_addr is
when "00" => -- dout
null; -- covered by combi statement
when "01" => -- din
rxfifo_get <= '1';
when "10" => -- clear flags
overflow <= overflow and not bus_wdata(0);
when "11" => -- interrupt control
imask <= bus_wdata(7 downto 6);
when others =>
null;
end case;
end if;
if reset='1' then
overflow <= '0';
imask <= (others => '0');
end if;
end if;
end process;
flags(0) <= overflow;
flags(1) <= '0';
flags(2) <= '0';
flags(3) <= '0';
flags(4) <= txfifo_full;
flags(5) <= rxfifo_full;
flags(6) <= done;
flags(7) <= rxfifo_dav;
with bus_addr select bus_rdata <=
rxfifo_dout when "00",
flags when "10",
imask & "000000" when "11",
X"00" when others;
uart_irq <= '1' when (flags(7 downto 6) and imask) /= "00" else '0';
end gideon;
|
library ieee;
use ieee.std_logic_1164.all;
entity uart_peripheral is
generic (
tx_fifo : boolean := true;
divisor : natural := 417 );
port (
clock : in std_logic;
reset : in std_logic;
bus_select : in std_logic;
bus_write : in std_logic;
bus_addr : in std_logic_vector(1 downto 0);
bus_wdata : in std_logic_vector(7 downto 0);
bus_rdata : out std_logic_vector(7 downto 0);
uart_irq : out std_logic;
txd : out std_logic;
rxd : in std_logic );
end uart_peripheral;
architecture gideon of uart_peripheral is
signal dotx : std_logic;
signal done : std_logic;
signal rxchar : std_logic_vector(7 downto 0);
signal rx_ack : std_logic;
signal rxfifo_get : std_logic;
signal rxfifo_dout : std_logic_vector(7 downto 0);
signal rxfifo_full : std_logic;
signal rxfifo_dav : std_logic;
signal overflow : std_logic;
signal flags : std_logic_vector(7 downto 0);
signal imask : std_logic_vector(7 downto 6);
signal txfifo_get : std_logic;
signal txfifo_put : std_logic;
signal txfifo_dout : std_logic_vector(7 downto 0);
signal txfifo_full : std_logic := '1';
signal txfifo_dav : std_logic;
signal dotx_d : std_logic;
signal txchar : std_logic_vector(7 downto 0);
begin
my_tx: entity work.tx
generic map (divisor)
port map (
clk => clock,
reset => reset,
dotx => dotx,
txchar => txchar,
txd => txd,
done => done );
my_rx: entity work.rx
generic map (divisor)
port map (
clk => clock,
reset => reset,
rxd => rxd,
rxchar => rxchar,
rx_ack => rx_ack );
my_rxfifo: entity work.srl_fifo
generic map (
Width => 8,
Threshold => 12 )
port map (
clock => clock,
reset => reset,
GetElement => rxfifo_get,
PutElement => rx_ack,
FlushFifo => '0',
DataIn => rxchar,
DataOut => rxfifo_dout,
SpaceInFifo => open,
AlmostFull => rxfifo_full,
DataInFifo => rxfifo_dav );
gentx: if tx_fifo generate
my_txfifo: entity work.srl_fifo
generic map (
Width => 8,
Threshold => 12 )
port map (
clock => clock,
reset => reset,
GetElement => txfifo_get,
PutElement => txfifo_put,
FlushFifo => '0',
DataIn => bus_wdata,
DataOut => txfifo_dout,
SpaceInFifo => open,
AlmostFull => txfifo_full,
DataInFifo => txfifo_dav );
end generate;
process(bus_select, bus_write, bus_addr, txfifo_dav, bus_wdata, txfifo_dout, done)
begin
if not tx_fifo then
txfifo_put <= '0';
txchar <= bus_wdata;
if bus_select='1' and bus_write='1' and bus_addr="00" then
dotx <= '1';
else
dotx <= '0';
end if;
else -- there is a fifo
dotx <= txfifo_dav and done;
txchar <= txfifo_dout;
if bus_select='1' and bus_write='1' and bus_addr="00" then
txfifo_put <= '1';
else
txfifo_put <= '0';
end if;
end if;
end process;
process(clock)
begin
if rising_edge(clock) then
rxfifo_get <= '0';
dotx_d <= dotx;
txfifo_get <= dotx_d;
if rxfifo_full='1' and rx_ack='1' then
overflow <= '1';
end if;
if bus_select='1' and bus_write='1' then
case bus_addr is
when "00" => -- dout
null; -- covered by combi statement
when "01" => -- din
rxfifo_get <= '1';
when "10" => -- clear flags
overflow <= overflow and not bus_wdata(0);
when "11" => -- interrupt control
imask <= bus_wdata(7 downto 6);
when others =>
null;
end case;
end if;
if reset='1' then
overflow <= '0';
imask <= (others => '0');
end if;
end if;
end process;
flags(0) <= overflow;
flags(1) <= '0';
flags(2) <= '0';
flags(3) <= '0';
flags(4) <= txfifo_full;
flags(5) <= rxfifo_full;
flags(6) <= done;
flags(7) <= rxfifo_dav;
with bus_addr select bus_rdata <=
rxfifo_dout when "00",
flags when "10",
imask & "000000" when "11",
X"00" when others;
uart_irq <= '1' when (flags(7 downto 6) and imask) /= "00" else '0';
end gideon;
|
library ieee;
use ieee.std_logic_1164.all;
entity uart_peripheral is
generic (
tx_fifo : boolean := true;
divisor : natural := 417 );
port (
clock : in std_logic;
reset : in std_logic;
bus_select : in std_logic;
bus_write : in std_logic;
bus_addr : in std_logic_vector(1 downto 0);
bus_wdata : in std_logic_vector(7 downto 0);
bus_rdata : out std_logic_vector(7 downto 0);
uart_irq : out std_logic;
txd : out std_logic;
rxd : in std_logic );
end uart_peripheral;
architecture gideon of uart_peripheral is
signal dotx : std_logic;
signal done : std_logic;
signal rxchar : std_logic_vector(7 downto 0);
signal rx_ack : std_logic;
signal rxfifo_get : std_logic;
signal rxfifo_dout : std_logic_vector(7 downto 0);
signal rxfifo_full : std_logic;
signal rxfifo_dav : std_logic;
signal overflow : std_logic;
signal flags : std_logic_vector(7 downto 0);
signal imask : std_logic_vector(7 downto 6);
signal txfifo_get : std_logic;
signal txfifo_put : std_logic;
signal txfifo_dout : std_logic_vector(7 downto 0);
signal txfifo_full : std_logic := '1';
signal txfifo_dav : std_logic;
signal dotx_d : std_logic;
signal txchar : std_logic_vector(7 downto 0);
begin
my_tx: entity work.tx
generic map (divisor)
port map (
clk => clock,
reset => reset,
dotx => dotx,
txchar => txchar,
txd => txd,
done => done );
my_rx: entity work.rx
generic map (divisor)
port map (
clk => clock,
reset => reset,
rxd => rxd,
rxchar => rxchar,
rx_ack => rx_ack );
my_rxfifo: entity work.srl_fifo
generic map (
Width => 8,
Threshold => 12 )
port map (
clock => clock,
reset => reset,
GetElement => rxfifo_get,
PutElement => rx_ack,
FlushFifo => '0',
DataIn => rxchar,
DataOut => rxfifo_dout,
SpaceInFifo => open,
AlmostFull => rxfifo_full,
DataInFifo => rxfifo_dav );
gentx: if tx_fifo generate
my_txfifo: entity work.srl_fifo
generic map (
Width => 8,
Threshold => 12 )
port map (
clock => clock,
reset => reset,
GetElement => txfifo_get,
PutElement => txfifo_put,
FlushFifo => '0',
DataIn => bus_wdata,
DataOut => txfifo_dout,
SpaceInFifo => open,
AlmostFull => txfifo_full,
DataInFifo => txfifo_dav );
end generate;
process(bus_select, bus_write, bus_addr, txfifo_dav, bus_wdata, txfifo_dout, done)
begin
if not tx_fifo then
txfifo_put <= '0';
txchar <= bus_wdata;
if bus_select='1' and bus_write='1' and bus_addr="00" then
dotx <= '1';
else
dotx <= '0';
end if;
else -- there is a fifo
dotx <= txfifo_dav and done;
txchar <= txfifo_dout;
if bus_select='1' and bus_write='1' and bus_addr="00" then
txfifo_put <= '1';
else
txfifo_put <= '0';
end if;
end if;
end process;
process(clock)
begin
if rising_edge(clock) then
rxfifo_get <= '0';
dotx_d <= dotx;
txfifo_get <= dotx_d;
if rxfifo_full='1' and rx_ack='1' then
overflow <= '1';
end if;
if bus_select='1' and bus_write='1' then
case bus_addr is
when "00" => -- dout
null; -- covered by combi statement
when "01" => -- din
rxfifo_get <= '1';
when "10" => -- clear flags
overflow <= overflow and not bus_wdata(0);
when "11" => -- interrupt control
imask <= bus_wdata(7 downto 6);
when others =>
null;
end case;
end if;
if reset='1' then
overflow <= '0';
imask <= (others => '0');
end if;
end if;
end process;
flags(0) <= overflow;
flags(1) <= '0';
flags(2) <= '0';
flags(3) <= '0';
flags(4) <= txfifo_full;
flags(5) <= rxfifo_full;
flags(6) <= done;
flags(7) <= rxfifo_dav;
with bus_addr select bus_rdata <=
rxfifo_dout when "00",
flags when "10",
imask & "000000" when "11",
X"00" when others;
uart_irq <= '1' when (flags(7 downto 6) and imask) /= "00" else '0';
end gideon;
|
--LIBRARY ieee;
--USE ieee.std_logic_1164.ALL;
--PACKAGE data_memory is
-- constant memsize: integer := 61;
-- type word is std_logic_vector(15 downto 0);
-- type memory is array(5 downto 0) of word;
-- type memory is array(5 downto 0) of std_logic_vector(15 downto 0);
--END data_memory;
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
USE ieee.std_logic_arith.ALL;
USE ieee.std_logic_unsigned.ALL;
--USE data__memory.ALL;
entity PC104 is port
(
-- bus interface signals --
-- BALE: in STD_LOGIC;
-- TC: in STD_LOGIC;
-- BOSC: in STD_LOGIC;
-- RSTDRV: in STD_LOGIC; --System reset
-- REFRES: in STD_LOGIC;
-- SBHE: in STD_LOGIC;
-- MASTER: in STD_LOGIC;
-- SMEMR: in STD_LOGIC;
-- SMEMW: in STD_LOGIC;
-- IOCHRDY: inout STD_LOGIC;
-- MEMCS16: inout STD_LOGIC;
IOCS16: inout STD_LOGIC;
-- IRQ: out STD_LOGIC_VECTOR (15 downto 3); -- interrupts
-- DACK: in STD_LOGIC_VECTOR (7 downto 6); -- dma acknowledges
-- DRQ: out STD_LOGIC_VECTOR (7 downto 6); -- dma requests
LBE: out STD_LOGIC;
LBDIR: out STD_LOGIC;
-- SYSCLK: in STD_LOGIC; --PC104 bus clock PIN 185 GCK3
SynClk: in STD_LOGIC; --50 MHz local clock PIN 80 GCK0
DIS: out STD_LOGIC;
AEN: in STD_LOGIC;
IORD: in STD_LOGIC;
IOWR: in STD_LOGIC;
SA: in STD_LOGIC_VECTOR (9 downto 0); -- address bus
SD: out STD_LOGIC_VECTOR (15 downto 0); -- data bus
-- led bits
LEDS: out STD_LOGIC_VECTOR(5 downto 0);
strobe: in std_logic;
Hadvance: out STD_LOGIC;
Hreset: out STD_LOGIC;
Hdata: in STD_LOGIC;
HistBits: in std_logic_vector(5 downto 0);
pulse0: in std_logic;
pulse1: in std_logic;
latch_count: in std_logic;
alt_clock: in std_logic;
radar_alt: in std_logic;
-- ckout: out std_logic;
ldebug: out std_logic;
pdebug: out std_logic;
ndebug: out std_logic;
cdebug: out std_logic
);
end PC104;
Architecture behavior of PC104 is
-- 0x220 hex
constant Decode : STD_LOGIC_VECTOR (5 downto 0) := "100010";
-- misc global signals --
-- type memory is array(63 downto 0) of std_logic_vector(15 downto 0);
type ram_type is array(63 downto 0) of std_logic_vector(15 downto 0);
-- signal Histogram: memory; --:=
signal Histogram: ram_type:=
(X"0000",X"0000",X"0000",X"0000",X"0000",X"0000",X"0000",X"0000",
X"0000",X"0000",X"0000",X"0000",X"0000",X"0000",X"0000",X"0000",
X"0000",X"0000",X"0000",X"0000",X"0000",X"0000",X"0000",X"0000",
X"0000",X"0000",X"0000",X"0000",X"0000",X"0000",X"0000",X"0000",
X"0000",X"0000",X"0000",X"0000",X"0000",X"0000",X"0000",X"0000",
X"0000",X"0000",X"0000",X"0000",X"0000",X"0000",X"0000",X"0000",
X"0000",X"0000",X"0000",X"0000",X"0000",X"0000",X"0000",X"0000",
X"0000",X"0000",X"0000",X"0000",X"0000",X"0000",X"0000",X"0000");
signal index: integer:=0;
signal CardSelect: STD_LOGIC:='0';
signal HistAdd: std_logic_vector (15 downto 0):=X"0000";
signal strobes: std_logic_vector (15 downto 0):=X"0000";
signal count0: std_logic_vector(15 downto 0):=X"0000";
signal count1: std_logic_vector(15 downto 0):=X"0000";
signal count0_latch: std_logic_vector(15 downto 0):=X"0000";
signal count1_latch: std_logic_vector(15 downto 0):=X"0000";
signal count_clear: std_logic:='0';
signal altitude: std_logic_vector(23 downto 0):=X"000000";
signal clear_hist: std_logic:='0';
signal house_data: std_logic_vector(15 downto 0):=X"0000";
signal house_adv: std_logic:='0';
signal alt_clock_old1: std_logic:='0';
signal alt_clock_old2: std_logic:='0';
signal read_data: std_logic:='0';
signal read_data_old1: std_logic:='0';
signal read_data_old2: std_logic:='0';
signal pulse0_old1: std_logic:='0';
signal pulse1_old1: std_logic:='0';
signal pulse0_old2: std_logic:='0';
signal pulse1_old2: std_logic:='0';
signal latch_count_old1: std_logic:='0';
signal latch_count_old2: std_logic:='0';
signal strobe_old1: std_logic:='0';
signal strobe_old2: std_logic:='0';
signal Hdata_old1: std_logic:='0';
signal Hdata_old2: std_logic:='0';
signal ledcount: STD_LOGIC_VECTOR (28 downto 0);
--Components:
-- component ledblink is
-- port (
-- clk: in STD_LOGIC;
-- ledx: out STD_LOGIC_VECTOR (5 downto 0)
-- );
-- end component ledblink;
begin
-- gledblink: ledblink port map (
-- clk => SynClk,
-- ledx => LEDS
-- );
-- DRQ <= "ZZ";
-- IRQ <= "ZZZZZZZZZZZZZ";
DIS <= '0'; -- uncomment to leave configuration decode on
-- DIS <= '1'; -- uncomment to disable configuration decode
-- MEMCS16 <= 'Z';
-- IOCHRDY <= 'Z';
-- ckout <= SynClk;
HistAdd(15 downto 6) <= "0000000000";
HistAdd(5 downto 0) <= HistBits(5 downto 0);
-- leds(0) <= not ledcount(23);
leds(0) <= not(HistBits(0) and HistBits(1) and HistBits(2) and HistBits(3)
and HistBits(4) and HistBits(5));
leds(1) <= not ledcount(24);
leds(2) <= not ledcount(25);
leds(3) <= not ledcount(26);
leds(4) <= not ledcount(27);
leds(5) <= not ledcount(28);
ledblinker: process (SynClk)
begin
if rising_edge(SynClk) then
ledcount <= ledcount + 1;
end if;
end process ledblinker;
RadarAltimeter: process (SynClk)
begin
if rising_edge(SynClk) then
alt_clock_old2 <= alt_clock_old1;
alt_clock_old1 <= alt_clock;
if alt_clock_old2 = '0' and alt_clock_old1 = '1' then
-- altitude <= altitude(1 to 23) & radar_alt; --bit into msb
-- altitude <= radar_alt & altitude(0 to 22); --bit into lsb
-- altitude <= altitude(22 downto 0) & radar_alt; --bit into lsb
altitude <= radar_alt & altitude(23 downto 1) ; --bit into msb
ndebug <= radar_alt;
pdebug <= altitude(23);
end if;
end if;
end process RadarAltimeter;
PulseCounters: process (SynClk)
begin
if rising_edge(SynClk) then
pulse0_old1 <= pulse0;
pulse0_old2 <= pulse0_old1;
pulse1_old1 <= pulse1;
pulse1_old2 <= pulse1_old1;
if count_clear = '1' then
count0 <= X"0000";
count1 <= X"0000";
end if;
if pulse0_old2 = '0' and pulse0_old1 = '1' then
count0 <= count0 + 1;
end if;
if pulse1_old2 = '0' and pulse1_old1 = '1' then
count1 <= count1 + 1;
end if;
end if;
end process PulseCounters;
LatchCounts: process (SynCLk)
begin
if rising_edge(SynClk) then
latch_count_old1 <= latch_count;
latch_count_old2 <= latch_count_old1;
if latch_count_old2 = '0' and latch_count_old1 = '1' then
count_clear <= '1';
count0_latch <= count0;
count1_latch <= count1;
else
count_clear <= '0';
end if;
end if;
end process LatchCounts;
HouseCounter: process (SynClk,house_adv)
begin
if (house_adv = '1') then
house_data <= X"0000";
elsif rising_edge(SynClk) then
Hdata_old2 <= Hdata_old1;
Hdata_old1 <= Hdata;
if Hdata_old2 = '0' and Hdata_old1 = '1' then
house_data <= house_data + 1;
end if;
end if;
end process HouseCounter;
CSelect: process (AEN)
begin
if SA(9 downto 4) = Decode and AEN = '0' then
CardSelect <= '1';
LBE <= '0';
else
LBE <= '1';
CardSelect <= '0';
end if;
end process CSelect;
Localbuffer: process (CardSelect, IORD)
begin
if (CardSelect = '1') and (IORD = '0') then
LBDIR <= '0';
else
LBDIR <= '1';
end if;
end process Localbuffer;
AddDecode: process (SA, AEN, IORD)
-- variable i: integer;
begin
clear_hist <= '0';
read_data <= '0';
if SA(3 downto 0) = "0010" and SA(9 downto 4) = Decode and AEN = '0' then
IOCS16 <= '0';
if IORD = '0' then
SD(15 downto 0) <= strobes(15 downto 0);
end if;
elsif SA(3 downto 0) = "0011" and SA(9 downto 4) = Decode and AEN = '0' then
IOCS16 <= 'Z';
if IORD = '0' then
ldebug <= '1';
clear_hist <= '1';
end if;
elsif SA(3 downto 0) = "0100" and SA(9 downto 4) = Decode and AEN = '0' then
IOCS16 <= '0';
if IORD = '0' then
ldebug <= '0';
SD(15 downto 0) <= Histogram(index);
read_data <= '1';
end if;
elsif SA(3 downto 0) = "0101" and SA(9 downto 4) = Decode and AEN = '0' then
IOCS16 <= 'Z';
Hadvance <= '1';
house_adv <= '1';
elsif SA(3 downto 0) = "0110" and SA(9 downto 4) = Decode and AEN = '0' then
IOCS16 <= '0';
if IORD = '0' then
SD <= house_data;
end if;
elsif SA(3 downto 0) = "0111" and SA(9 downto 4) = Decode and AEN = '0' then
IOCS16 <= 'Z';
Hreset <= '1';
elsif SA(3 downto 0) = "1000" and SA(9 downto 4) = Decode and AEN = '0' then
IOCS16 <= '0';
if IORD = '0' then
SD(15 downto 0) <= count0_latch(15 downto 0);
-- cdebug <='0';
end if;
elsif SA(3 downto 0) = "1010" and SA(9 downto 4) = Decode and AEN = '0' then
IOCS16 <= '0';
if IORD = '0' then
SD(15 downto 0) <= count1_latch(15 downto 0);
end if;
elsif SA(3 downto 0) = "1100" and SA(9 downto 4) = Decode and AEN = '0' then
IOCS16 <= '0';
if IORD = '0' then
SD(15 downto 8) <= altitude(21 downto 14);
SD(7 downto 1) <= altitude(13 downto 7);
SD(0) <= altitude(1) or altitude(2) or altitude (4);
end if;
else
Hadvance <= '0';
house_adv <= '0';
Hreset <= '0';
SD(15 downto 0) <= "ZZZZZZZZZZZZZZZZ";
IOCS16 <= 'Z';
-- cdebug <= '1';
end if;
end process AddDecode;
histo: process(SynClk,clear_hist)
variable i: integer;
variable j: integer;
variable k: integer;
variable n: integer;
begin
if clear_hist = '1' then
i := 0;
cdebug <= '1';
strobes <= X"0000";
for k in 0 to 63 loop
Histogram(k) <= X"0000";
end loop;
-- i := 63;
-- while i>=0 loop
-- Histogram(i) <= X"0000";
-- i := i - 1;
-- end loop;
-- i := 31;
-- while i>=0 loop
-- Histogram(i) <= X"0000";
-- i := i - 1;
-- end loop;
elsif rising_edge(SynClk) then
j := conv_integer(HistAdd);
n := j;
cdebug <= '0';
strobe_old2 <= strobe_old1;
strobe_old1 <= strobe;
read_data_old2 <= read_data_old1;
read_data_old1 <= read_data;
if read_data_old2 = '0' and read_data_old1 = '1' then
index <= i;
i := i + 1;
elsif strobe_old2 = '0' and strobe_old1 = '1' then
strobes <= strobes + 1;
Histogram(n) <= Histogram(n) + 1;
end if;
end if;
end process histo;
end behavior;
|
-- $Id: tst_serloop_hiomap.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2011- by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: tst_serloop_hiomap - syn
-- Description: default human I/O mapper
--
-- Dependencies: -
-- Test bench: -
--
-- Target Devices: generic
-- Tool versions: ise 13.1-14.7; viv 2014.4-2015.4; ghdl 0.29-0.33
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-12-09 437 1.0.2 rename serport stat->moni port
-- 2011-11-16 426 1.0.1 setup leds and dps
-- 2011-11-05 420 1.0 Initial version
------------------------------------------------------------------------------
--
-- Usage of Switches, Buttons, LEDs:
--
-- BTN(3): -- unused --
-- (2): -- unused --
-- (1): load enables from SWI(7:4)
-- SWI(7) -> ENAFTDI
-- SWI(6) -> ENATHROTTLE
-- SWI(5) -> ENAESC
-- SWI(4) -> ENAXON
-- (0): reset state [!! decoded by top level design !!]
--
-- SWI(7:4) select display or enable pattern (when BTN(1) pressed)
-- (3) -- unused --
-- (2:1): mode 00 idle
-- 01 rxblast
-- 10 txblast
-- 11 loop
-- SWI(0) 0 -> main board RS232 port
-- 1 -> Pmod1 RS232 port
--
-- LED(7) enaesc
-- (6) enaxon
-- (5) rxfecnt > 0 (frame error)
-- (4) rxoecnt > 0 (overrun error)
-- (3) rxsecnt > 0 (sequence error)
-- (2) abact (shows ab activity)
-- (1) (not rxok) or (not txok) (shows back pressure)
-- (0) rxact or txact (shows activity)
--
-- DSP data as selected by SWI(7:4)
-- 0000 -> rxfecnt
-- 0001 -> rxoecnt
-- 0010 -> rxsecnt
-- 0100 -> rxcnt.l
-- 0101 -> rxcnt.h
-- 0110 -> txcnt.l
-- 0111 -> txcnt.h
-- 1000 -> rxokcnt
-- 1001 -> txokcnt
-- 1010 -> rxuicnt,rxuidat
-- 1111 -> abclkdiv
--
-- DP(3): not SER_MONI.txok (shows tx back pressure)
-- (2): SER_MONI.txact (shows tx activity)
-- (1): not SER_MONI.rxok (shows rx back pressure)
-- (0): SER_MONI.rxact (shows rx activity)
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.serportlib.all;
use work.tst_serlooplib.all;
-- ----------------------------------------------------------------------------
entity tst_serloop_hiomap is -- default human I/O mapper
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
HIO_CNTL : out hio_cntl_type; -- tester controls from hio
HIO_STAT : in hio_stat_type; -- tester status to diaplay by hio
SER_MONI : in serport_moni_type; -- serport monitor to display by hio
SWI : in slv8; -- switch settings
BTN : in slv4; -- button settings
LED : out slv8; -- led data
DSP_DAT : out slv16; -- display data
DSP_DP : out slv4 -- display decimal points
);
end tst_serloop_hiomap;
architecture syn of tst_serloop_hiomap is
type regs_type is record
enaxon : slbit; -- enable xon/xoff handling
enaesc : slbit; -- enable xon/xoff escaping
enathrottle : slbit; -- enable 1 msec tx throttling
enaftdi : slbit; -- enable ftdi flush handling
dspdat : slv16; -- display data
end record regs_type;
constant regs_init : regs_type := (
'0','0','0','0', -- enaxon,enaesc,enathrottle,enaftdi
(others=>'0') -- dspdat
);
signal R_REGS : regs_type := regs_init; -- state registers
signal N_REGS : regs_type := regs_init; -- next value state regs
begin
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
R_REGS <= regs_init;
else
R_REGS <= N_REGS;
end if;
end if;
end process proc_regs;
proc_next: process (R_REGS, HIO_STAT, SER_MONI, SWI, BTN)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
variable icntl : hio_cntl_type := hio_cntl_init;
variable iled : slv8 := (others=>'0');
variable idat : slv16 := (others=>'0');
variable idp : slv4 := (others=>'0');
begin
r := R_REGS;
n := R_REGS;
icntl := hio_cntl_init;
iled := (others=>'0');
idat := (others=>'0');
idp := (others=>'0');
-- handle BTN(1) "load enables" press
if BTN(1) = '1' then
n.enaxon := SWI(4);
n.enaesc := SWI(5);
n.enathrottle := SWI(6);
n.enaftdi := SWI(7);
end if;
-- setup tester controls
icntl.mode := SWI(2 downto 1);
icntl.enaxon := r.enaxon;
icntl.enaesc := r.enaesc;
icntl.enathrottle := r.enathrottle;
icntl.enaftdi := r.enaftdi;
-- setup leds
iled(7) := icntl.enaesc;
iled(6) := icntl.enaxon;
if unsigned(HIO_STAT.rxfecnt) > 0 then iled(5) := '1'; end if;
if unsigned(HIO_STAT.rxoecnt) > 0 then iled(4) := '1'; end if;
if unsigned(HIO_STAT.rxsecnt) > 0 then iled(3) := '1'; end if;
iled(2) := SER_MONI.abact;
iled(1) := (not SER_MONI.rxok) or (not SER_MONI.txok);
iled(0) := SER_MONI.rxact or SER_MONI.txact;
-- setup display data
case SWI(7 downto 4) is
when "0000" => idat := HIO_STAT.rxfecnt;
when "0001" => idat := HIO_STAT.rxoecnt;
when "0010" => idat := HIO_STAT.rxsecnt;
when "0100" => idat := HIO_STAT.rxcnt(15 downto 0);
when "0101" => idat := HIO_STAT.rxcnt(31 downto 16);
when "0110" => idat := HIO_STAT.txcnt(15 downto 0);
when "0111" => idat := HIO_STAT.txcnt(31 downto 16);
when "1000" => idat := HIO_STAT.rxokcnt;
when "1001" => idat := HIO_STAT.txokcnt;
when "1010" => idat := HIO_STAT.rxuicnt & HIO_STAT.rxuidat;
when "1111" => idat := SER_MONI.abclkdiv;
when others => null;
end case;
n.dspdat := idat;
-- setup display decimal points
idp(3) := not SER_MONI.txok; -- tx back pressure
idp(2) := SER_MONI.txact; -- tx activity
idp(1) := not SER_MONI.rxok; -- rx back pressure
idp(0) := SER_MONI.rxact; -- rx activity
N_REGS <= n;
HIO_CNTL <= icntl;
LED <= iled;
DSP_DAT <= r.dspdat;
DSP_DP <= idp;
end process proc_next;
end syn;
|
-- Prosoft VHDL tests.
--
-- Copyright (C) 2011 Prosoft.
--
-- Author: Zefirov, Karavaev.
--
-- This is a set of simplest tests for isolated tests of VHDL features.
--
-- Nothing more than standard package should be required.
--
-- Categories: entity, architecture, process, after, if-then-else, enumerations, array, record, case, for-loop, signals-attributes.
use work.std_logic_1164_for_tst.all;
entity ENT00015_Test_Bench is
end ENT00015_Test_Bench;
architecture ARCH00015_Test_Bench of ENT00015_Test_Bench is
type std_array_array is array (0 to 3, 1 to 4) of std_ulogic;
signal I_saa : std_array_array := (others => x"B");
subtype byte is bit_vector(7 downto 0);
subtype byte2 is bit_vector(0 to 7);
signal b1 : byte := x"00";
signal b2 : byte2 := x"00";
type bit_array_array is array (0 to 3, 4 downto 1) of bit;
signal I_baa : bit_array_array := (others => x"A");
type NatArray is array (natural range <>) of natural;
type std_array is array (0 to 7) of std_logic;
signal I_sa : std_array := "10101010";
type enum is (a_v, b_v, c_v, d_v, e_v, f_v);
type enum_array is array (integer range <>) of enum;
type rec is record
f1 : integer;
f2 : boolean;
f3 : bit;
f4 : enum;
f5 : enum_array(0 to 3);
f6 : NatArray(7 downto 0);
f7 : bit_vector(7 downto 0);
end record;
type rec_array is array (integer range <>) of rec;
signal e : enum := a_v;
signal ea : enum_array(0 to 3) := (others => a_v);
signal r : rec := (
f1 => 10
, f2 => true
, f3 => '1'
, f4 => a_v
, f5 => (others => a_v)
, f6 => (0 => 10, 7 => 3, others => 0)
, f7 => x"33"
);
signal ra : rec_array(0 to 3) := (others => (
f1 => 10
, f2 => true
, f3 => '1'
, f4 => a_v
, f5 => (others => a_v)
, f6 => (0 => 10, 7 => 3, others => 0)
, f7 => x"33"
)
);
signal bv : bit_vector(15 downto 0) := x"CCCC";
signal clk : std_ulogic := '0';
signal clk2 : std_ulogic := '0';
type TimeVector is array (integer range <>) of time;
signal t : TimeVector(1 to 24);
begin
t(1) <= bv'Last_event;
t(2) <= ra'Last_event;
t(3) <= r'Last_event;
t(4) <= ea'Last_event;
t(5) <= e'Last_event;
t(6) <= I_sa'Last_event;
t(7) <= I_baa'Last_event;
t(8) <= I_saa'Last_event;
t(9) <= b1'Last_event;
t(10) <= b2'Last_event;
t(11) <= clk'Last_event;
t(12) <= clk2'Last_event;
clk <= not clk after 1 us;
clk2 <= not clk2 after 3 us;
process (clk)
begin
if clk'event and clk = '1' then
b1 <= b1(6 downto 0) & not b1(7);
case e is
when a_v => e <= b_v;
when b_v => e <= c_v;
when c_v => e <= d_v;
when d_v => e <= e_v;
when e_v => e <= f_v;
when f_v => e <= a_v;
end case;
ea(0) <= e;
ea_loop: for i in 1 to ea'length-1 loop
ea(i) <= ea(i-1);
end loop ea_loop;
elsif falling_edge(clk) then
bv <= bv(bv'left-1 downto bv'low) & bv(bv'high);
r.f1 <= r.f1 + 1;
r.f2 <= not r.f2;
r.f3 <= not r.f3;
r.f4 <= e;
r.f5 <= ea;
r_f6_loop: for i in r.f6'low to r.f6'high loop
r.f6(i) <= r.f6(i) + 1;
end loop r_f6_loop;
r.f7 <= r.f7(6 downto 0) & r.f7(7);
ra(ra'high) <= r;
ra_loop: for i in ra'high-1 downto 0 loop
ra(i) <= ra(i+1);
end loop;
end if;
end process;
process (clk2)
begin
if rising_edge(clk2) then
I_sa <= I_sa(I_sa'length-1) & I_sa(0 to I_sa'length-2);
elsif clk2'event and clk2 = '0' then
I_saa_loop_1: for i in 0 to 3 loop
I_saa_loop_2: for j in 1 to 4 loop
I_saa(i,j) <= I_sa(i+j);
end loop I_saa_loop_2;
end loop I_saa_loop_1;
I_baa_loop_1: for i in 0 to 3 loop
I_baa_loop_2: for j in 1 to 4 loop
I_baa(i,j) <= bv(i*j);
end loop I_baa_loop_2;
end loop I_baa_loop_1;
end if;
end process;
end ARCH00015_Test_Bench ; |
-- Automatically generated VHDL-93
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.MATH_REAL.ALL;
use std.textio.all;
use work.all;
use work.mac_types.all;
entity mac_testbench is
port(done : out boolean);
end;
architecture structural of mac_testbench is
signal finished : boolean;
signal system1000 : std_logic;
signal system1000_rstn : std_logic;
signal w3 : mac_types.tup2;
signal result : signed(8 downto 0);
begin
done <= finished;
-- pragma translate_off
process is
begin
system1000 <= '0';
wait for 3 ns;
while (not finished) loop
system1000 <= not system1000;
wait for 500 ns;
system1000 <= not system1000;
wait for 500 ns;
end loop;
wait;
end process;
-- pragma translate_on
-- pragma translate_off
system1000_rstn <= '0',
'1' after 2 ns;
-- pragma translate_on
totest : entity mac_topentity_0
port map
(system1000 => system1000
,system1000_rstn => system1000_rstn
,w3 => w3
,result => result);
stimuli : entity mac_testinput
port map
(system1000 => system1000
,system1000_rstn => system1000_rstn
,result => w3);
verify : entity mac_expectedoutput
port map
(system1000 => system1000
,system1000_rstn => system1000_rstn
,arg => result
,result => finished);
end;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1548.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s09b00x00p10n01i01548ent IS
END c08s09b00x00p10n01i01548ent;
ARCHITECTURE c08s09b00x00p10n01i01548arch OF c08s09b00x00p10n01i01548ent IS
BEGIN
TESTING: PROCESS
-- All different non-numeric type declarations.
-- enumerated types.
type COLORS is (RED, GREEN, BLUE);
variable k : integer := 0;
BEGIN
-- None of these loops should EVER execute any of their statements.
for I in INTEGER'HIGH to 0 loop
assert (FALSE)
report "For-loop executed once when it should never have been executed.";
k := 1;
end loop;
for I in INTEGER'HIGH to INTEGER'HIGH-1 loop
assert (FALSE)
report "For-loop executed once when it should never have been executed.";
k := 1;
end loop;
for I in INTEGER'LOW downto 0 loop
assert (FALSE)
report "For-loop executed once when it should never have been executed.";
k := 1;
end loop;
for I in INTEGER'LOW downto INTEGER'LOW + 1 loop
assert (FALSE)
report "For-loop executed once when it should never have been executed.";
k := 1;
end loop;
for I in COLORS'HIGH to COLORS'LOW loop
assert (FALSE)
report "For-loop executed once when it should never have been executed.";
k := 1;
end loop;
for I in COLORS'HIGH to COLORS'PRED( COLORS'HIGH ) loop
assert (FALSE)
report "For-loop executed once when it should never have been executed.";
k := 1;
end loop;
for I in COLORS'LOW downto COLORS'HIGH loop
assert (FALSE)
report "For-loop executed once when it should never have been executed.";
k := 1;
end loop;
for I in COLORS'LOW downto COLORS'SUCC( COLORS'LOW ) loop
assert (FALSE)
report "For-loop executed once when it should never have been executed.";
k := 1;
end loop;
assert NOT( k=0 )
report "***PASSED TEST: c08s09b00x00p10n01i01548"
severity NOTE;
assert ( k=0 )
report "***FAILED TEST: c08s09b00x00p10n01i01548 - The sequence of statements is executed once for each value of the discrete range"
severity ERROR;
wait;
END PROCESS TESTING;
END c08s09b00x00p10n01i01548arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1548.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s09b00x00p10n01i01548ent IS
END c08s09b00x00p10n01i01548ent;
ARCHITECTURE c08s09b00x00p10n01i01548arch OF c08s09b00x00p10n01i01548ent IS
BEGIN
TESTING: PROCESS
-- All different non-numeric type declarations.
-- enumerated types.
type COLORS is (RED, GREEN, BLUE);
variable k : integer := 0;
BEGIN
-- None of these loops should EVER execute any of their statements.
for I in INTEGER'HIGH to 0 loop
assert (FALSE)
report "For-loop executed once when it should never have been executed.";
k := 1;
end loop;
for I in INTEGER'HIGH to INTEGER'HIGH-1 loop
assert (FALSE)
report "For-loop executed once when it should never have been executed.";
k := 1;
end loop;
for I in INTEGER'LOW downto 0 loop
assert (FALSE)
report "For-loop executed once when it should never have been executed.";
k := 1;
end loop;
for I in INTEGER'LOW downto INTEGER'LOW + 1 loop
assert (FALSE)
report "For-loop executed once when it should never have been executed.";
k := 1;
end loop;
for I in COLORS'HIGH to COLORS'LOW loop
assert (FALSE)
report "For-loop executed once when it should never have been executed.";
k := 1;
end loop;
for I in COLORS'HIGH to COLORS'PRED( COLORS'HIGH ) loop
assert (FALSE)
report "For-loop executed once when it should never have been executed.";
k := 1;
end loop;
for I in COLORS'LOW downto COLORS'HIGH loop
assert (FALSE)
report "For-loop executed once when it should never have been executed.";
k := 1;
end loop;
for I in COLORS'LOW downto COLORS'SUCC( COLORS'LOW ) loop
assert (FALSE)
report "For-loop executed once when it should never have been executed.";
k := 1;
end loop;
assert NOT( k=0 )
report "***PASSED TEST: c08s09b00x00p10n01i01548"
severity NOTE;
assert ( k=0 )
report "***FAILED TEST: c08s09b00x00p10n01i01548 - The sequence of statements is executed once for each value of the discrete range"
severity ERROR;
wait;
END PROCESS TESTING;
END c08s09b00x00p10n01i01548arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1548.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s09b00x00p10n01i01548ent IS
END c08s09b00x00p10n01i01548ent;
ARCHITECTURE c08s09b00x00p10n01i01548arch OF c08s09b00x00p10n01i01548ent IS
BEGIN
TESTING: PROCESS
-- All different non-numeric type declarations.
-- enumerated types.
type COLORS is (RED, GREEN, BLUE);
variable k : integer := 0;
BEGIN
-- None of these loops should EVER execute any of their statements.
for I in INTEGER'HIGH to 0 loop
assert (FALSE)
report "For-loop executed once when it should never have been executed.";
k := 1;
end loop;
for I in INTEGER'HIGH to INTEGER'HIGH-1 loop
assert (FALSE)
report "For-loop executed once when it should never have been executed.";
k := 1;
end loop;
for I in INTEGER'LOW downto 0 loop
assert (FALSE)
report "For-loop executed once when it should never have been executed.";
k := 1;
end loop;
for I in INTEGER'LOW downto INTEGER'LOW + 1 loop
assert (FALSE)
report "For-loop executed once when it should never have been executed.";
k := 1;
end loop;
for I in COLORS'HIGH to COLORS'LOW loop
assert (FALSE)
report "For-loop executed once when it should never have been executed.";
k := 1;
end loop;
for I in COLORS'HIGH to COLORS'PRED( COLORS'HIGH ) loop
assert (FALSE)
report "For-loop executed once when it should never have been executed.";
k := 1;
end loop;
for I in COLORS'LOW downto COLORS'HIGH loop
assert (FALSE)
report "For-loop executed once when it should never have been executed.";
k := 1;
end loop;
for I in COLORS'LOW downto COLORS'SUCC( COLORS'LOW ) loop
assert (FALSE)
report "For-loop executed once when it should never have been executed.";
k := 1;
end loop;
assert NOT( k=0 )
report "***PASSED TEST: c08s09b00x00p10n01i01548"
severity NOTE;
assert ( k=0 )
report "***FAILED TEST: c08s09b00x00p10n01i01548 - The sequence of statements is executed once for each value of the discrete range"
severity ERROR;
wait;
END PROCESS TESTING;
END c08s09b00x00p10n01i01548arch;
|
-- $Id: pdp11_vmbox.vhd 427 2011-11-19 21:04:11Z mueller $
--
-- Copyright 2006-2011 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: pdp11_vmbox - syn
-- Description: pdp11: virtual memory
--
-- Dependencies: pdp11_mmu
-- pdp11_ubmap
-- ibus/ib_sres_or_4
-- ibus/ib_sres_or_2
-- ibus/ib_sel
--
-- Test bench: tb/tb_pdp11_core (implicit)
-- Target Devices: generic
-- Tool versions: xst 8.2, 9.1, 9.2, 12.1, 13.1; ghdl 0.18-0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-18 427 1.6.3 now numeric_std clean
-- 2010-10-23 335 1.6.2 add r.paddr_iopage, use ib_sel
-- 2010-10-22 334 1.6.1 deassert ibus be's at end-cycle; fix rmw logic
-- 2010-10-17 333 1.6 implement ibus V2 interface
-- 2010-06-27 310 1.5 redo ibus driver logic, now ibus driven from flops
-- 2010-06-20 307 1.4.2 rename cpacc to cacc in vm_cntl_type, mmu_cntl_type
-- 2010-06-18 306 1.4.1 for cpacc: set cacc in ib_mreq, forward racc,be
-- from CP_ADDR; now all ibr handling via vmbox
-- 2010-06-13 305 1.4 rename CPADDR -> CP_ADDR
-- 2009-06-01 221 1.3.8 add dip signal in ib_mreq (set in s_ib)
-- 2009-05-30 220 1.3.7 final removal of snoopers (were already commented)
-- 2009-05-01 211 1.3.6 BUGFIX: add 177776 stack protect (SCCE)
-- 2008-08-22 161 1.3.5 rename pdp11_ibres_ -> ib_sres_, ubf_ -> ibf_
-- 2008-04-25 138 1.3.4 add BRESET port, clear stklim with BRESET
-- 2008-04-20 137 1.3.3 add DM_STAT_VM port
-- 2008-03-19 127 1.3.2 ignore ack state when waiting on a busy IB in s_ib
-- 2008-03-02 121 1.3.1 remove snoopers
-- 2008-02-24 119 1.3 revamp paddr generation; add _ubmap
-- 2008-02-23 118 1.2.1 use sys_conf_mem_losize
-- 2008-02-17 117 1.2 use em_(mreq|sres) interface for external memory
-- 2008-01-26 114 1.1.4 rename 'ubus' to 'ib' (proper name of intbus now)
-- 2008-01-05 110 1.1.3 update snooper.
-- rename IB_MREQ(ena->req) SRES(sel->ack, hold->busy)
-- 2008-01-01 109 1.1.2 Use IB_SRES_(CPU|EXT); use r./n. coding style, move
-- all status into regs_type. add intbus HOLD support.
-- 2007-12-30 108 1.1.1 use ubf_byte[01]
-- 2007-12-30 107 1.1 Use IB_MREQ/IB_SRES interface now; remove DMA port
-- 2007-09-16 83 1.0.2 Use ram_1swsr_wfirst_gen, not ram_2swsr_wfirst_gen
-- 2nd port was unused, connected ADDR caused slow net
-- 2007-06-14 56 1.0.1 Use slvtypes.all
-- 2007-05-12 26 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.iblib.all;
use work.pdp11.all;
use work.sys_conf.all;
-- ----------------------------------------------------------------------------
entity pdp11_vmbox is -- virtual memory
port (
CLK : in slbit; -- clock
GRESET : in slbit; -- global reset
CRESET : in slbit; -- console reset
BRESET : in slbit; -- ibus reset
CP_ADDR : in cp_addr_type; -- console port address
VM_CNTL : in vm_cntl_type; -- vm control port
VM_ADDR : in slv16; -- vm address
VM_DIN : in slv16; -- vm data in
VM_STAT : out vm_stat_type; -- vm status port
VM_DOUT : out slv16; -- vm data out
EM_MREQ : out em_mreq_type; -- external memory: request
EM_SRES : in em_sres_type; -- external memory: response
MMU_MONI : in mmu_moni_type; -- mmu monitor port
IB_MREQ_M : out ib_mreq_type; -- ibus request (master)
IB_SRES_CPU : in ib_sres_type; -- ibus response (CPU registers)
IB_SRES_EXT : in ib_sres_type; -- ibus response (external devices)
DM_STAT_VM : out dm_stat_vm_type -- debug and monitor status
);
end pdp11_vmbox;
architecture syn of pdp11_vmbox is
constant ibaddr_slim : slv16 := slv(to_unsigned(8#177774#,16));
constant atowidth : natural := 5; -- size of access timeout counter
type state_type is (
s_idle, -- s_idle: wait for vm_cntl request
s_mem_w, -- s_mem_w: check mmu, wait for memory
s_ib_w, -- s_ib_w: wait for ibus
s_ib_wend, -- s_ib_wend: ibus write completion
s_ib_rend, -- s_ib_rend: ibus read completion
s_idle_mw_ib, -- s_idle_mw_ib: wait macc write (ibus)
s_idle_mw_mem, -- s_idle_mw_mem: wait macc write (mem)
s_mem_mw_w, -- s_mem_mw_w: wait for memory (macc)
s_fail, -- s_fail: vmbox fatal error catcher
s_errrsv, -- s_errrsv: red stack violation
s_errib -- s_errib: ibus error handler
);
type regs_type is record -- state registers
state : state_type; -- state
wacc : slbit; -- write access
macc : slbit; -- modify access (r-m-w sequence)
cacc : slbit; -- console access
bytop : slbit; -- byte operation
kstack : slbit; -- access through kernel stack
ysv : slbit; -- yellow stack violation detected
vaok : slbit; -- virtual address valid (from MMU)
trap_mmu : slbit; -- mmu trace trap requested
mdin : slv16; -- data input (memory order)
paddr : slv22; -- physical address register
paddr_iopage : slv9; -- iopage base (upper 9 bits of paddr)
atocnt : slv(atowidth-1 downto 0); -- access timeout counter
ibre : slbit; -- ibus re signal
ibwe : slbit; -- ibus we signal
ibbe : slv2; -- ibus be0,be1 signals
ibrmw : slbit; -- ibus rmw signal
ibcacc : slbit; -- ibus cacc signal
ibracc : slbit; -- ibus racc signal
ibdout : slv16; -- ibus dout register
end record regs_type;
constant atocnt_init : slv(atowidth-1 downto 0) := (others=>'1');
constant regs_init : regs_type := (
s_idle, -- state
'0','0','0','0', -- wacc,macc,cacc,bytop
'0','0','0','0', -- kstack,ysv,vaok,trap_mmu
(others=>'0'), -- mdin
(others=>'0'), -- paddr
(others=>'0'), -- paddr_iopage
atocnt_init, -- atocnt
'0','0',"00", -- ibre,ibwe,ibbe
'0','0','0', -- ibrmw,ibcacc,ibracc
(others=>'0') -- ibdout
);
signal R_REGS : regs_type := regs_init;
signal N_REGS : regs_type := regs_init;
signal R_SLIM : slv8 := (others=>'0'); -- stack limit register
signal MMU_CNTL : mmu_cntl_type := mmu_cntl_init;
signal MMU_STAT : mmu_stat_type := mmu_stat_init;
signal PADDRH : slv16 := (others=>'0');
signal IBSEL_SLIM :slbit := '0'; -- select stack limit reg
signal IB_SRES_SLIM : ib_sres_type := ib_sres_init;
signal IB_SRES_MMU : ib_sres_type := ib_sres_init;
signal IB_SRES_UBMAP : ib_sres_type := ib_sres_init;
signal UBMAP_MREQ : slbit := '0';
signal UBMAP_ADDR_PM : slv22_1 := (others=>'0');
signal IB_MREQ : ib_mreq_type := ib_mreq_init; -- ibus request (local)
signal IB_SRES : ib_sres_type := ib_sres_init; -- ibus response (local)
signal IB_SRES_INT : ib_sres_type := ib_sres_init; -- ibus response (cpu)
begin
MMU : pdp11_mmu
port map (
CLK => CLK,
CRESET => CRESET,
BRESET => BRESET,
CNTL => MMU_CNTL,
VADDR => VM_ADDR,
MONI => MMU_MONI,
STAT => MMU_STAT,
PADDRH => PADDRH,
IB_MREQ => IB_MREQ,
IB_SRES => IB_SRES_MMU
);
UBMAP : pdp11_ubmap
port map (
CLK => CLK,
MREQ => UBMAP_MREQ,
ADDR_UB => CP_ADDR.addr(17 downto 1),
ADDR_PM => UBMAP_ADDR_PM,
IB_MREQ => IB_MREQ,
IB_SRES => IB_SRES_UBMAP
);
SRES_OR_INT : ib_sres_or_4
port map (
IB_SRES_1 => IB_SRES_CPU,
IB_SRES_2 => IB_SRES_SLIM,
IB_SRES_3 => IB_SRES_MMU,
IB_SRES_4 => IB_SRES_UBMAP,
IB_SRES_OR => IB_SRES_INT
);
SRES_OR_ALL : ib_sres_or_2
port map (
IB_SRES_1 => IB_SRES_INT,
IB_SRES_2 => IB_SRES_EXT,
IB_SRES_OR => IB_SRES
);
SEL : ib_sel
generic map (
IB_ADDR => ibaddr_slim)
port map (
CLK => CLK,
IB_MREQ => IB_MREQ,
SEL => IBSEL_SLIM
);
proc_ibres : process (IBSEL_SLIM, IB_MREQ, R_SLIM)
variable idout : slv16 := (others=>'0');
begin
idout := (others=>'0');
if IBSEL_SLIM = '1' then
idout(ibf_byte1) := R_SLIM;
end if;
IB_SRES_SLIM.dout <= idout;
IB_SRES_SLIM.ack <= IBSEL_SLIM and (IB_MREQ.re or IB_MREQ.we); -- ack all
IB_SRES_SLIM.busy <= '0';
end process proc_ibres;
proc_slim: process (CLK)
begin
if rising_edge(CLK) then
if BRESET = '1' then
R_SLIM <= (others=>'0');
elsif IBSEL_SLIM='1' and IB_MREQ.we='1' then
if IB_MREQ.be1 = '1' then
R_SLIM <= IB_MREQ.din(ibf_byte1);
end if;
end if;
end if;
end process proc_slim;
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if GRESET = '1' then
R_REGS <= regs_init;
else
R_REGS <= N_REGS;
end if;
end if;
end process proc_regs;
proc_next: process (R_REGS, R_SLIM, CP_ADDR, VM_CNTL, VM_DIN, VM_ADDR,
IB_SRES, UBMAP_ADDR_PM,
EM_SRES, MMU_STAT, PADDRH)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
variable ivm_stat : vm_stat_type := vm_stat_init;
variable ivm_dout : slv16 := (others=>'0');
variable iem_mreq : em_mreq_type := em_mreq_init;
variable immu_cntl : mmu_cntl_type := mmu_cntl_init;
variable ipaddr : slv22 := (others=>'0');
variable ipaddr_iopage : slv9 := (others=>'0');
variable iib_aval : slbit := '0';
variable ato_go : slbit := '0';
variable ato_end : slbit := '0';
variable is_stackyellow : slbit := '1'; -- VM_ADDR in yellow stack zone
variable is_stackred : slbit := '1'; -- VM_ADDR in red stack zone
variable iubmap_mreq : slbit := '0';
variable paddr_mmu : slbit := '0';
variable paddr_sel : slv2 := "00";
constant c_paddr_sel_vmaddr : slv2 := "00";
constant c_paddr_sel_rpaddr : slv2 := "01";
constant c_paddr_sel_cacc : slv2 := "10";
constant c_paddr_sel_ubmap : slv2 := "11";
begin
r := R_REGS;
n := R_REGS;
n.state := s_fail;
ivm_stat := vm_stat_init;
ivm_dout := EM_SRES.dout;
immu_cntl := mmu_cntl_init;
iib_aval := '0';
iem_mreq := em_mreq_init;
iem_mreq.din := VM_DIN;
if VM_CNTL.bytop = '0' then -- if word access
iem_mreq.be := "11"; -- both be's
else
if VM_ADDR(0) = '0' then -- if low byte
iem_mreq.be := "01";
else -- if high byte
iem_mreq.be := "10";
iem_mreq.din(ibf_byte1) := VM_DIN(ibf_byte0);
end if;
end if;
iubmap_mreq :='0';
paddr_mmu := '1'; -- ipaddr selector, used in s_idle
-- and overwritten in s_idle_mw_mem
paddr_sel := "00";
if MMU_STAT.ena_mmu='0' or VM_CNTL.cacc='1' then
paddr_mmu := '0';
paddr_sel := c_paddr_sel_vmaddr;
if VM_CNTL.cacc = '1' then
if CP_ADDR.ena_ubmap='1' and MMU_STAT.ena_ubmap='1' then
paddr_sel := c_paddr_sel_ubmap;
else
paddr_sel := c_paddr_sel_cacc;
end if;
end if;
end if;
-- the iopage base is determined based on mmu regs and request type
-- r.paddr_iopage is updated during s_idle. This way the iopage base
-- address is determined in parallel to paddr and latched at end of s_idle.
-- Note: is VM_CNTL.cacc here, the status in s_idle is relevant !
ipaddr_iopage := "111111111"; -- iopage match pattern (for 22 bit)
if VM_CNTL.cacc = '1' then
if CP_ADDR.ena_22bit = '0' then
ipaddr_iopage := "000000111"; -- 16 bit cacc
end if;
else
if MMU_STAT.ena_mmu = '0' then
ipaddr_iopage := "000000111"; -- 16 bit mode
else
if MMU_STAT.ena_22bit = '0' then
ipaddr_iopage := "000011111"; -- 18 bit mode
end if;
end if;
end if;
ato_go := '0'; -- default: keep access timeout in reset
ato_end := '0';
if unsigned(r.atocnt) = 0 then -- if access timeout count at zero
ato_end := '1'; -- signal expiration
end if;
is_stackyellow := '0';
is_stackred := '0';
if unsigned(VM_ADDR(15 downto 8)) <= unsigned(R_SLIM) then
is_stackyellow := '1';
if unsigned(VM_ADDR(7 downto 5)) /= 7 then -- below 340
is_stackred := '1';
end if;
end if;
if VM_ADDR(15 downto 1) = "111111111111111" then -- vaddr == 177776
is_stackred := '1';
end if;
immu_cntl.wacc := VM_CNTL.wacc;
immu_cntl.macc := VM_CNTL.macc;
immu_cntl.cacc := VM_CNTL.cacc;
immu_cntl.dspace := VM_CNTL.dspace;
immu_cntl.mode := VM_CNTL.mode;
immu_cntl.trap_done := VM_CNTL.trap_done;
case r.state is
when s_idle => -- s_idle: wait for vm_cntl request --
n.state := s_idle;
iubmap_mreq := '1'; -- activate ubmap always in s_idle
if VM_CNTL.req = '1' then
n.wacc := VM_CNTL.wacc;
n.macc := VM_CNTL.macc;
n.cacc := VM_CNTL.cacc;
n.bytop := VM_CNTL.bytop;
n.kstack := VM_CNTL.kstack;
n.ysv := '0';
n.vaok := MMU_STAT.vaok;
n.trap_mmu := MMU_STAT.trap;
n.mdin := iem_mreq.din;
-- n.paddr assignment handled separately in 'if state=s_idle' at the
-- end.
immu_cntl.req := '1';
if VM_CNTL.wacc='1' and VM_CNTL.macc='1' then
n.state := s_fail;
elsif VM_CNTL.kstack='1' and VM_CNTL.intrsv='0' and
is_stackred='1' then
n.state := s_errrsv;
else
iem_mreq.req := '1';
iem_mreq.we := VM_CNTL.wacc;
if VM_CNTL.kstack='1'and VM_CNTL.intrsv='0' then
n.ysv := is_stackyellow;
end if;
n.state := s_mem_w;
end if;
end if;
when s_mem_w => -- s_mem_w: check mmu, wait for memory
if r.bytop='0' and r.paddr(0)='1' then -- odd address ?
ivm_stat.err := '1';
ivm_stat.err_odd := '1';
ivm_stat.err_rsv := r.kstack; -- escalate to rsv if kstack
iem_mreq.cancel := '1'; -- cancel pending mem request
n.state := s_idle;
elsif r.vaok = '0' then -- MMU abort ?
ivm_stat.err := '1';
ivm_stat.err_mmu := '1';
ivm_stat.err_rsv := r.kstack; -- escalate to rsv if kstack
iem_mreq.cancel := '1'; -- cancel pending mem request
n.state := s_idle;
else
if r.paddr(21 downto 13) = r.paddr_iopage then
-- I/O page decoded
iem_mreq.cancel := '1'; -- cancel pending mem request
iib_aval := '1'; -- declare ibus addr valid
n.ibre := not r.wacc;
n.ibwe := r.wacc;
n.ibcacc := r.cacc;
n.ibracc := r.cacc and CP_ADDR.racc;
n.ibbe := "11";
if r.cacc = '1' then -- console access ?
n.ibbe := CP_ADDR.be;
else -- cpu access ?
if r.bytop = '1' then
if r.paddr(0) = '0' then
n.ibbe(1) := '0';
else
n.ibbe(0) := '0';
end if;
end if;
end if;
n.ibrmw := r.macc;
n.state := s_ib_w;
else
if unsigned(r.paddr(21 downto 6)) > sys_conf_mem_losize then
ivm_stat.err := '1';
ivm_stat.err_nxm := '1';
ivm_stat.err_rsv := r.kstack; -- escalate to rsv if kstack
iem_mreq.cancel := '1'; -- cancel pending mem request
n.state := s_idle;
else
if EM_SRES.ack_r='1' or EM_SRES.ack_w='1' then
ivm_stat.ack := '1';
ivm_stat.trap_ysv := r.ysv;
ivm_stat.trap_mmu := r.trap_mmu;
if r.macc='1' and r.wacc='0' then
n.state := s_idle_mw_mem;
else
n.state := s_idle;
end if;
else
n.state := s_mem_w; -- keep waiting
end if;
end if;
end if;
end if;
when s_ib_w => -- s_ib_w: wait for ibus -------------
ato_go := '1'; -- activate timeout counter
iib_aval := '1'; -- declare ibus addr valid
n.ibre := '0'; -- end cycle, unless busy seen
n.ibwe := '0';
n.ibrmw := '0';
n.ibbe := "00";
n.ibcacc := '0';
n.ibracc := '0';
if IB_SRES.ack='1' and IB_SRES.busy='0' then -- ibus cycle finished
if r.wacc = '1' then
n.state := s_ib_wend;
else
if r.macc = '1' then -- if first part of rmw
n.ibrmw := r.macc; -- keep rmw
n.ibbe := r.ibbe; -- keep be's
n.ibcacc := r.ibcacc;
n.ibracc := r.ibracc;
end if;
n.ibdout := IB_SRES.dout;
n.state := s_ib_rend;
end if;
elsif IB_SRES.busy='1' and ato_end='0' then
n.ibre := r.ibre; -- continue ibus cycle
n.ibwe := r.ibwe;
n.ibrmw := r.ibrmw;
n.ibbe := r.ibbe;
n.ibcacc := r.ibcacc;
n.ibracc := r.ibracc;
n.state := s_ib_w;
else
n.state := s_errib;
end if;
when s_ib_wend => -- s_ib_wend: ibus write completion --
ivm_stat.ack := '1';
n.state := s_idle;
when s_ib_rend => -- s_ib_rend: ibus read completion ---
ivm_stat.ack := '1';
ivm_dout := r.ibdout;
if r.macc='1' then -- first part of read-mod-write
iib_aval := '1'; -- keep ibus addr valid
n.state := s_idle_mw_ib;
else
n.state := s_idle;
end if;
when s_idle_mw_ib => -- s_idle_mw_ib: wait macc write (ibus)
n.state := s_idle_mw_ib;
iib_aval := '1'; -- keep ibus addr valid
if r.ibbe = "10" then
iem_mreq.din(ibf_byte1) := VM_DIN(ibf_byte0);
end if;
if VM_CNTL.req = '1' then
n.wacc := VM_CNTL.wacc;
n.macc := VM_CNTL.macc;
n.mdin := iem_mreq.din;
if VM_CNTL.wacc='0' or VM_CNTL.macc='0' then
n.state := s_fail;
else
n.ibwe := '1'; -- Note: all other ibus drivers
-- already set in 1st part
n.state := s_ib_w;
end if;
end if;
when s_idle_mw_mem => -- s_idle_mw_mem: wait macc write (mem)
n.state := s_idle_mw_mem;
paddr_mmu := '0';
paddr_sel := c_paddr_sel_rpaddr;
if VM_CNTL.bytop = '0' then -- if word access
iem_mreq.be := "11"; -- both be's
else
if r.paddr(0) = '0' then -- if low byte
iem_mreq.be := "01";
else -- if high byte
iem_mreq.be := "10";
iem_mreq.din(ibf_byte1) := VM_DIN(ibf_byte0);
end if;
end if;
if VM_CNTL.req = '1' then
n.wacc := VM_CNTL.wacc;
n.macc := VM_CNTL.macc;
n.bytop := VM_CNTL.bytop;
n.mdin := iem_mreq.din;
if VM_CNTL.wacc='0' or VM_CNTL.macc='0' then
n.state := s_fail;
else
iem_mreq.req := '1';
iem_mreq.we := '1';
n.state := s_mem_mw_w;
end if;
end if;
when s_mem_mw_w => -- s_mem_mw_w: wait for memory (macc)
if EM_SRES.ack_w = '1' then
ivm_stat.ack := '1';
n.state := s_idle;
else
n.state := s_mem_mw_w; -- keep waiting
end if;
when s_fail => -- s_fail: vmbox fatal error catcher
ivm_stat.fail := '1';
n.state := s_idle;
when s_errrsv => -- s_errrsv: red stack violation -----
ivm_stat.err := '1';
ivm_stat.err_rsv := '1';
n.state := s_idle;
when s_errib => -- s_errib: ibus error handler -------
ivm_stat.err := '1';
ivm_stat.err_iobto := '1';
ivm_stat.err_rsv := r.kstack; -- escalate to rsv if kstack
n.state := s_idle;
when others => null;
end case;
if r.bytop='1' and r.paddr(0)='1' then
ivm_dout(ibf_byte0) := ivm_dout(ibf_byte1);
end if;
if ato_go = '0' then -- handle access timeout counter
n.atocnt := atocnt_init; -- if ato_go=0, keep in reset
else
n.atocnt := slv(unsigned(r.atocnt) - 1);-- otherwise count down
end if;
ipaddr := (others=>'0');
if paddr_mmu = '1' then
ipaddr( 5 downto 0) := VM_ADDR(5 downto 0);
ipaddr(21 downto 6) := PADDRH;
if MMU_STAT.ena_22bit = '0' then
ipaddr(21 downto 18) := (others=>'0');
end if;
else
case paddr_sel is
when c_paddr_sel_vmaddr =>
ipaddr(15 downto 0) := VM_ADDR(15 downto 0);
when c_paddr_sel_rpaddr =>
ipaddr := r.paddr;
when c_paddr_sel_cacc =>
ipaddr := CP_ADDR.addr & '0';
if CP_ADDR.ena_22bit = '0' then
ipaddr(21 downto 16) := (others=>'0');
end if;
when c_paddr_sel_ubmap =>
ipaddr := UBMAP_ADDR_PM & '0';
when others => null;
end case;
end if;
if r.state = s_idle then
n.paddr := ipaddr;
n.paddr_iopage := ipaddr_iopage;
end if;
iem_mreq.addr := ipaddr(21 downto 1);
N_REGS <= n;
UBMAP_MREQ <= iubmap_mreq;
IB_MREQ.aval <= iib_aval;
IB_MREQ.re <= r.ibre;
IB_MREQ.we <= r.ibwe;
IB_MREQ.be0 <= r.ibbe(0);
IB_MREQ.be1 <= r.ibbe(1);
IB_MREQ.rmw <= r.ibrmw;
IB_MREQ.cacc <= r.ibcacc;
IB_MREQ.racc <= r.ibracc;
IB_MREQ.addr <= r.paddr(12 downto 1);
IB_MREQ.din <= r.mdin;
VM_DOUT <= ivm_dout;
VM_STAT <= ivm_stat;
MMU_CNTL <= immu_cntl;
EM_MREQ <= iem_mreq;
end process proc_next;
IB_MREQ_M <= IB_MREQ; -- external drive master port
DM_STAT_VM.ibmreq <= IB_MREQ;
DM_STAT_VM.ibsres <= IB_SRES;
end syn;
|
-- $Id: pdp11_vmbox.vhd 427 2011-11-19 21:04:11Z mueller $
--
-- Copyright 2006-2011 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: pdp11_vmbox - syn
-- Description: pdp11: virtual memory
--
-- Dependencies: pdp11_mmu
-- pdp11_ubmap
-- ibus/ib_sres_or_4
-- ibus/ib_sres_or_2
-- ibus/ib_sel
--
-- Test bench: tb/tb_pdp11_core (implicit)
-- Target Devices: generic
-- Tool versions: xst 8.2, 9.1, 9.2, 12.1, 13.1; ghdl 0.18-0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-18 427 1.6.3 now numeric_std clean
-- 2010-10-23 335 1.6.2 add r.paddr_iopage, use ib_sel
-- 2010-10-22 334 1.6.1 deassert ibus be's at end-cycle; fix rmw logic
-- 2010-10-17 333 1.6 implement ibus V2 interface
-- 2010-06-27 310 1.5 redo ibus driver logic, now ibus driven from flops
-- 2010-06-20 307 1.4.2 rename cpacc to cacc in vm_cntl_type, mmu_cntl_type
-- 2010-06-18 306 1.4.1 for cpacc: set cacc in ib_mreq, forward racc,be
-- from CP_ADDR; now all ibr handling via vmbox
-- 2010-06-13 305 1.4 rename CPADDR -> CP_ADDR
-- 2009-06-01 221 1.3.8 add dip signal in ib_mreq (set in s_ib)
-- 2009-05-30 220 1.3.7 final removal of snoopers (were already commented)
-- 2009-05-01 211 1.3.6 BUGFIX: add 177776 stack protect (SCCE)
-- 2008-08-22 161 1.3.5 rename pdp11_ibres_ -> ib_sres_, ubf_ -> ibf_
-- 2008-04-25 138 1.3.4 add BRESET port, clear stklim with BRESET
-- 2008-04-20 137 1.3.3 add DM_STAT_VM port
-- 2008-03-19 127 1.3.2 ignore ack state when waiting on a busy IB in s_ib
-- 2008-03-02 121 1.3.1 remove snoopers
-- 2008-02-24 119 1.3 revamp paddr generation; add _ubmap
-- 2008-02-23 118 1.2.1 use sys_conf_mem_losize
-- 2008-02-17 117 1.2 use em_(mreq|sres) interface for external memory
-- 2008-01-26 114 1.1.4 rename 'ubus' to 'ib' (proper name of intbus now)
-- 2008-01-05 110 1.1.3 update snooper.
-- rename IB_MREQ(ena->req) SRES(sel->ack, hold->busy)
-- 2008-01-01 109 1.1.2 Use IB_SRES_(CPU|EXT); use r./n. coding style, move
-- all status into regs_type. add intbus HOLD support.
-- 2007-12-30 108 1.1.1 use ubf_byte[01]
-- 2007-12-30 107 1.1 Use IB_MREQ/IB_SRES interface now; remove DMA port
-- 2007-09-16 83 1.0.2 Use ram_1swsr_wfirst_gen, not ram_2swsr_wfirst_gen
-- 2nd port was unused, connected ADDR caused slow net
-- 2007-06-14 56 1.0.1 Use slvtypes.all
-- 2007-05-12 26 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.iblib.all;
use work.pdp11.all;
use work.sys_conf.all;
-- ----------------------------------------------------------------------------
entity pdp11_vmbox is -- virtual memory
port (
CLK : in slbit; -- clock
GRESET : in slbit; -- global reset
CRESET : in slbit; -- console reset
BRESET : in slbit; -- ibus reset
CP_ADDR : in cp_addr_type; -- console port address
VM_CNTL : in vm_cntl_type; -- vm control port
VM_ADDR : in slv16; -- vm address
VM_DIN : in slv16; -- vm data in
VM_STAT : out vm_stat_type; -- vm status port
VM_DOUT : out slv16; -- vm data out
EM_MREQ : out em_mreq_type; -- external memory: request
EM_SRES : in em_sres_type; -- external memory: response
MMU_MONI : in mmu_moni_type; -- mmu monitor port
IB_MREQ_M : out ib_mreq_type; -- ibus request (master)
IB_SRES_CPU : in ib_sres_type; -- ibus response (CPU registers)
IB_SRES_EXT : in ib_sres_type; -- ibus response (external devices)
DM_STAT_VM : out dm_stat_vm_type -- debug and monitor status
);
end pdp11_vmbox;
architecture syn of pdp11_vmbox is
constant ibaddr_slim : slv16 := slv(to_unsigned(8#177774#,16));
constant atowidth : natural := 5; -- size of access timeout counter
type state_type is (
s_idle, -- s_idle: wait for vm_cntl request
s_mem_w, -- s_mem_w: check mmu, wait for memory
s_ib_w, -- s_ib_w: wait for ibus
s_ib_wend, -- s_ib_wend: ibus write completion
s_ib_rend, -- s_ib_rend: ibus read completion
s_idle_mw_ib, -- s_idle_mw_ib: wait macc write (ibus)
s_idle_mw_mem, -- s_idle_mw_mem: wait macc write (mem)
s_mem_mw_w, -- s_mem_mw_w: wait for memory (macc)
s_fail, -- s_fail: vmbox fatal error catcher
s_errrsv, -- s_errrsv: red stack violation
s_errib -- s_errib: ibus error handler
);
type regs_type is record -- state registers
state : state_type; -- state
wacc : slbit; -- write access
macc : slbit; -- modify access (r-m-w sequence)
cacc : slbit; -- console access
bytop : slbit; -- byte operation
kstack : slbit; -- access through kernel stack
ysv : slbit; -- yellow stack violation detected
vaok : slbit; -- virtual address valid (from MMU)
trap_mmu : slbit; -- mmu trace trap requested
mdin : slv16; -- data input (memory order)
paddr : slv22; -- physical address register
paddr_iopage : slv9; -- iopage base (upper 9 bits of paddr)
atocnt : slv(atowidth-1 downto 0); -- access timeout counter
ibre : slbit; -- ibus re signal
ibwe : slbit; -- ibus we signal
ibbe : slv2; -- ibus be0,be1 signals
ibrmw : slbit; -- ibus rmw signal
ibcacc : slbit; -- ibus cacc signal
ibracc : slbit; -- ibus racc signal
ibdout : slv16; -- ibus dout register
end record regs_type;
constant atocnt_init : slv(atowidth-1 downto 0) := (others=>'1');
constant regs_init : regs_type := (
s_idle, -- state
'0','0','0','0', -- wacc,macc,cacc,bytop
'0','0','0','0', -- kstack,ysv,vaok,trap_mmu
(others=>'0'), -- mdin
(others=>'0'), -- paddr
(others=>'0'), -- paddr_iopage
atocnt_init, -- atocnt
'0','0',"00", -- ibre,ibwe,ibbe
'0','0','0', -- ibrmw,ibcacc,ibracc
(others=>'0') -- ibdout
);
signal R_REGS : regs_type := regs_init;
signal N_REGS : regs_type := regs_init;
signal R_SLIM : slv8 := (others=>'0'); -- stack limit register
signal MMU_CNTL : mmu_cntl_type := mmu_cntl_init;
signal MMU_STAT : mmu_stat_type := mmu_stat_init;
signal PADDRH : slv16 := (others=>'0');
signal IBSEL_SLIM :slbit := '0'; -- select stack limit reg
signal IB_SRES_SLIM : ib_sres_type := ib_sres_init;
signal IB_SRES_MMU : ib_sres_type := ib_sres_init;
signal IB_SRES_UBMAP : ib_sres_type := ib_sres_init;
signal UBMAP_MREQ : slbit := '0';
signal UBMAP_ADDR_PM : slv22_1 := (others=>'0');
signal IB_MREQ : ib_mreq_type := ib_mreq_init; -- ibus request (local)
signal IB_SRES : ib_sres_type := ib_sres_init; -- ibus response (local)
signal IB_SRES_INT : ib_sres_type := ib_sres_init; -- ibus response (cpu)
begin
MMU : pdp11_mmu
port map (
CLK => CLK,
CRESET => CRESET,
BRESET => BRESET,
CNTL => MMU_CNTL,
VADDR => VM_ADDR,
MONI => MMU_MONI,
STAT => MMU_STAT,
PADDRH => PADDRH,
IB_MREQ => IB_MREQ,
IB_SRES => IB_SRES_MMU
);
UBMAP : pdp11_ubmap
port map (
CLK => CLK,
MREQ => UBMAP_MREQ,
ADDR_UB => CP_ADDR.addr(17 downto 1),
ADDR_PM => UBMAP_ADDR_PM,
IB_MREQ => IB_MREQ,
IB_SRES => IB_SRES_UBMAP
);
SRES_OR_INT : ib_sres_or_4
port map (
IB_SRES_1 => IB_SRES_CPU,
IB_SRES_2 => IB_SRES_SLIM,
IB_SRES_3 => IB_SRES_MMU,
IB_SRES_4 => IB_SRES_UBMAP,
IB_SRES_OR => IB_SRES_INT
);
SRES_OR_ALL : ib_sres_or_2
port map (
IB_SRES_1 => IB_SRES_INT,
IB_SRES_2 => IB_SRES_EXT,
IB_SRES_OR => IB_SRES
);
SEL : ib_sel
generic map (
IB_ADDR => ibaddr_slim)
port map (
CLK => CLK,
IB_MREQ => IB_MREQ,
SEL => IBSEL_SLIM
);
proc_ibres : process (IBSEL_SLIM, IB_MREQ, R_SLIM)
variable idout : slv16 := (others=>'0');
begin
idout := (others=>'0');
if IBSEL_SLIM = '1' then
idout(ibf_byte1) := R_SLIM;
end if;
IB_SRES_SLIM.dout <= idout;
IB_SRES_SLIM.ack <= IBSEL_SLIM and (IB_MREQ.re or IB_MREQ.we); -- ack all
IB_SRES_SLIM.busy <= '0';
end process proc_ibres;
proc_slim: process (CLK)
begin
if rising_edge(CLK) then
if BRESET = '1' then
R_SLIM <= (others=>'0');
elsif IBSEL_SLIM='1' and IB_MREQ.we='1' then
if IB_MREQ.be1 = '1' then
R_SLIM <= IB_MREQ.din(ibf_byte1);
end if;
end if;
end if;
end process proc_slim;
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if GRESET = '1' then
R_REGS <= regs_init;
else
R_REGS <= N_REGS;
end if;
end if;
end process proc_regs;
proc_next: process (R_REGS, R_SLIM, CP_ADDR, VM_CNTL, VM_DIN, VM_ADDR,
IB_SRES, UBMAP_ADDR_PM,
EM_SRES, MMU_STAT, PADDRH)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
variable ivm_stat : vm_stat_type := vm_stat_init;
variable ivm_dout : slv16 := (others=>'0');
variable iem_mreq : em_mreq_type := em_mreq_init;
variable immu_cntl : mmu_cntl_type := mmu_cntl_init;
variable ipaddr : slv22 := (others=>'0');
variable ipaddr_iopage : slv9 := (others=>'0');
variable iib_aval : slbit := '0';
variable ato_go : slbit := '0';
variable ato_end : slbit := '0';
variable is_stackyellow : slbit := '1'; -- VM_ADDR in yellow stack zone
variable is_stackred : slbit := '1'; -- VM_ADDR in red stack zone
variable iubmap_mreq : slbit := '0';
variable paddr_mmu : slbit := '0';
variable paddr_sel : slv2 := "00";
constant c_paddr_sel_vmaddr : slv2 := "00";
constant c_paddr_sel_rpaddr : slv2 := "01";
constant c_paddr_sel_cacc : slv2 := "10";
constant c_paddr_sel_ubmap : slv2 := "11";
begin
r := R_REGS;
n := R_REGS;
n.state := s_fail;
ivm_stat := vm_stat_init;
ivm_dout := EM_SRES.dout;
immu_cntl := mmu_cntl_init;
iib_aval := '0';
iem_mreq := em_mreq_init;
iem_mreq.din := VM_DIN;
if VM_CNTL.bytop = '0' then -- if word access
iem_mreq.be := "11"; -- both be's
else
if VM_ADDR(0) = '0' then -- if low byte
iem_mreq.be := "01";
else -- if high byte
iem_mreq.be := "10";
iem_mreq.din(ibf_byte1) := VM_DIN(ibf_byte0);
end if;
end if;
iubmap_mreq :='0';
paddr_mmu := '1'; -- ipaddr selector, used in s_idle
-- and overwritten in s_idle_mw_mem
paddr_sel := "00";
if MMU_STAT.ena_mmu='0' or VM_CNTL.cacc='1' then
paddr_mmu := '0';
paddr_sel := c_paddr_sel_vmaddr;
if VM_CNTL.cacc = '1' then
if CP_ADDR.ena_ubmap='1' and MMU_STAT.ena_ubmap='1' then
paddr_sel := c_paddr_sel_ubmap;
else
paddr_sel := c_paddr_sel_cacc;
end if;
end if;
end if;
-- the iopage base is determined based on mmu regs and request type
-- r.paddr_iopage is updated during s_idle. This way the iopage base
-- address is determined in parallel to paddr and latched at end of s_idle.
-- Note: is VM_CNTL.cacc here, the status in s_idle is relevant !
ipaddr_iopage := "111111111"; -- iopage match pattern (for 22 bit)
if VM_CNTL.cacc = '1' then
if CP_ADDR.ena_22bit = '0' then
ipaddr_iopage := "000000111"; -- 16 bit cacc
end if;
else
if MMU_STAT.ena_mmu = '0' then
ipaddr_iopage := "000000111"; -- 16 bit mode
else
if MMU_STAT.ena_22bit = '0' then
ipaddr_iopage := "000011111"; -- 18 bit mode
end if;
end if;
end if;
ato_go := '0'; -- default: keep access timeout in reset
ato_end := '0';
if unsigned(r.atocnt) = 0 then -- if access timeout count at zero
ato_end := '1'; -- signal expiration
end if;
is_stackyellow := '0';
is_stackred := '0';
if unsigned(VM_ADDR(15 downto 8)) <= unsigned(R_SLIM) then
is_stackyellow := '1';
if unsigned(VM_ADDR(7 downto 5)) /= 7 then -- below 340
is_stackred := '1';
end if;
end if;
if VM_ADDR(15 downto 1) = "111111111111111" then -- vaddr == 177776
is_stackred := '1';
end if;
immu_cntl.wacc := VM_CNTL.wacc;
immu_cntl.macc := VM_CNTL.macc;
immu_cntl.cacc := VM_CNTL.cacc;
immu_cntl.dspace := VM_CNTL.dspace;
immu_cntl.mode := VM_CNTL.mode;
immu_cntl.trap_done := VM_CNTL.trap_done;
case r.state is
when s_idle => -- s_idle: wait for vm_cntl request --
n.state := s_idle;
iubmap_mreq := '1'; -- activate ubmap always in s_idle
if VM_CNTL.req = '1' then
n.wacc := VM_CNTL.wacc;
n.macc := VM_CNTL.macc;
n.cacc := VM_CNTL.cacc;
n.bytop := VM_CNTL.bytop;
n.kstack := VM_CNTL.kstack;
n.ysv := '0';
n.vaok := MMU_STAT.vaok;
n.trap_mmu := MMU_STAT.trap;
n.mdin := iem_mreq.din;
-- n.paddr assignment handled separately in 'if state=s_idle' at the
-- end.
immu_cntl.req := '1';
if VM_CNTL.wacc='1' and VM_CNTL.macc='1' then
n.state := s_fail;
elsif VM_CNTL.kstack='1' and VM_CNTL.intrsv='0' and
is_stackred='1' then
n.state := s_errrsv;
else
iem_mreq.req := '1';
iem_mreq.we := VM_CNTL.wacc;
if VM_CNTL.kstack='1'and VM_CNTL.intrsv='0' then
n.ysv := is_stackyellow;
end if;
n.state := s_mem_w;
end if;
end if;
when s_mem_w => -- s_mem_w: check mmu, wait for memory
if r.bytop='0' and r.paddr(0)='1' then -- odd address ?
ivm_stat.err := '1';
ivm_stat.err_odd := '1';
ivm_stat.err_rsv := r.kstack; -- escalate to rsv if kstack
iem_mreq.cancel := '1'; -- cancel pending mem request
n.state := s_idle;
elsif r.vaok = '0' then -- MMU abort ?
ivm_stat.err := '1';
ivm_stat.err_mmu := '1';
ivm_stat.err_rsv := r.kstack; -- escalate to rsv if kstack
iem_mreq.cancel := '1'; -- cancel pending mem request
n.state := s_idle;
else
if r.paddr(21 downto 13) = r.paddr_iopage then
-- I/O page decoded
iem_mreq.cancel := '1'; -- cancel pending mem request
iib_aval := '1'; -- declare ibus addr valid
n.ibre := not r.wacc;
n.ibwe := r.wacc;
n.ibcacc := r.cacc;
n.ibracc := r.cacc and CP_ADDR.racc;
n.ibbe := "11";
if r.cacc = '1' then -- console access ?
n.ibbe := CP_ADDR.be;
else -- cpu access ?
if r.bytop = '1' then
if r.paddr(0) = '0' then
n.ibbe(1) := '0';
else
n.ibbe(0) := '0';
end if;
end if;
end if;
n.ibrmw := r.macc;
n.state := s_ib_w;
else
if unsigned(r.paddr(21 downto 6)) > sys_conf_mem_losize then
ivm_stat.err := '1';
ivm_stat.err_nxm := '1';
ivm_stat.err_rsv := r.kstack; -- escalate to rsv if kstack
iem_mreq.cancel := '1'; -- cancel pending mem request
n.state := s_idle;
else
if EM_SRES.ack_r='1' or EM_SRES.ack_w='1' then
ivm_stat.ack := '1';
ivm_stat.trap_ysv := r.ysv;
ivm_stat.trap_mmu := r.trap_mmu;
if r.macc='1' and r.wacc='0' then
n.state := s_idle_mw_mem;
else
n.state := s_idle;
end if;
else
n.state := s_mem_w; -- keep waiting
end if;
end if;
end if;
end if;
when s_ib_w => -- s_ib_w: wait for ibus -------------
ato_go := '1'; -- activate timeout counter
iib_aval := '1'; -- declare ibus addr valid
n.ibre := '0'; -- end cycle, unless busy seen
n.ibwe := '0';
n.ibrmw := '0';
n.ibbe := "00";
n.ibcacc := '0';
n.ibracc := '0';
if IB_SRES.ack='1' and IB_SRES.busy='0' then -- ibus cycle finished
if r.wacc = '1' then
n.state := s_ib_wend;
else
if r.macc = '1' then -- if first part of rmw
n.ibrmw := r.macc; -- keep rmw
n.ibbe := r.ibbe; -- keep be's
n.ibcacc := r.ibcacc;
n.ibracc := r.ibracc;
end if;
n.ibdout := IB_SRES.dout;
n.state := s_ib_rend;
end if;
elsif IB_SRES.busy='1' and ato_end='0' then
n.ibre := r.ibre; -- continue ibus cycle
n.ibwe := r.ibwe;
n.ibrmw := r.ibrmw;
n.ibbe := r.ibbe;
n.ibcacc := r.ibcacc;
n.ibracc := r.ibracc;
n.state := s_ib_w;
else
n.state := s_errib;
end if;
when s_ib_wend => -- s_ib_wend: ibus write completion --
ivm_stat.ack := '1';
n.state := s_idle;
when s_ib_rend => -- s_ib_rend: ibus read completion ---
ivm_stat.ack := '1';
ivm_dout := r.ibdout;
if r.macc='1' then -- first part of read-mod-write
iib_aval := '1'; -- keep ibus addr valid
n.state := s_idle_mw_ib;
else
n.state := s_idle;
end if;
when s_idle_mw_ib => -- s_idle_mw_ib: wait macc write (ibus)
n.state := s_idle_mw_ib;
iib_aval := '1'; -- keep ibus addr valid
if r.ibbe = "10" then
iem_mreq.din(ibf_byte1) := VM_DIN(ibf_byte0);
end if;
if VM_CNTL.req = '1' then
n.wacc := VM_CNTL.wacc;
n.macc := VM_CNTL.macc;
n.mdin := iem_mreq.din;
if VM_CNTL.wacc='0' or VM_CNTL.macc='0' then
n.state := s_fail;
else
n.ibwe := '1'; -- Note: all other ibus drivers
-- already set in 1st part
n.state := s_ib_w;
end if;
end if;
when s_idle_mw_mem => -- s_idle_mw_mem: wait macc write (mem)
n.state := s_idle_mw_mem;
paddr_mmu := '0';
paddr_sel := c_paddr_sel_rpaddr;
if VM_CNTL.bytop = '0' then -- if word access
iem_mreq.be := "11"; -- both be's
else
if r.paddr(0) = '0' then -- if low byte
iem_mreq.be := "01";
else -- if high byte
iem_mreq.be := "10";
iem_mreq.din(ibf_byte1) := VM_DIN(ibf_byte0);
end if;
end if;
if VM_CNTL.req = '1' then
n.wacc := VM_CNTL.wacc;
n.macc := VM_CNTL.macc;
n.bytop := VM_CNTL.bytop;
n.mdin := iem_mreq.din;
if VM_CNTL.wacc='0' or VM_CNTL.macc='0' then
n.state := s_fail;
else
iem_mreq.req := '1';
iem_mreq.we := '1';
n.state := s_mem_mw_w;
end if;
end if;
when s_mem_mw_w => -- s_mem_mw_w: wait for memory (macc)
if EM_SRES.ack_w = '1' then
ivm_stat.ack := '1';
n.state := s_idle;
else
n.state := s_mem_mw_w; -- keep waiting
end if;
when s_fail => -- s_fail: vmbox fatal error catcher
ivm_stat.fail := '1';
n.state := s_idle;
when s_errrsv => -- s_errrsv: red stack violation -----
ivm_stat.err := '1';
ivm_stat.err_rsv := '1';
n.state := s_idle;
when s_errib => -- s_errib: ibus error handler -------
ivm_stat.err := '1';
ivm_stat.err_iobto := '1';
ivm_stat.err_rsv := r.kstack; -- escalate to rsv if kstack
n.state := s_idle;
when others => null;
end case;
if r.bytop='1' and r.paddr(0)='1' then
ivm_dout(ibf_byte0) := ivm_dout(ibf_byte1);
end if;
if ato_go = '0' then -- handle access timeout counter
n.atocnt := atocnt_init; -- if ato_go=0, keep in reset
else
n.atocnt := slv(unsigned(r.atocnt) - 1);-- otherwise count down
end if;
ipaddr := (others=>'0');
if paddr_mmu = '1' then
ipaddr( 5 downto 0) := VM_ADDR(5 downto 0);
ipaddr(21 downto 6) := PADDRH;
if MMU_STAT.ena_22bit = '0' then
ipaddr(21 downto 18) := (others=>'0');
end if;
else
case paddr_sel is
when c_paddr_sel_vmaddr =>
ipaddr(15 downto 0) := VM_ADDR(15 downto 0);
when c_paddr_sel_rpaddr =>
ipaddr := r.paddr;
when c_paddr_sel_cacc =>
ipaddr := CP_ADDR.addr & '0';
if CP_ADDR.ena_22bit = '0' then
ipaddr(21 downto 16) := (others=>'0');
end if;
when c_paddr_sel_ubmap =>
ipaddr := UBMAP_ADDR_PM & '0';
when others => null;
end case;
end if;
if r.state = s_idle then
n.paddr := ipaddr;
n.paddr_iopage := ipaddr_iopage;
end if;
iem_mreq.addr := ipaddr(21 downto 1);
N_REGS <= n;
UBMAP_MREQ <= iubmap_mreq;
IB_MREQ.aval <= iib_aval;
IB_MREQ.re <= r.ibre;
IB_MREQ.we <= r.ibwe;
IB_MREQ.be0 <= r.ibbe(0);
IB_MREQ.be1 <= r.ibbe(1);
IB_MREQ.rmw <= r.ibrmw;
IB_MREQ.cacc <= r.ibcacc;
IB_MREQ.racc <= r.ibracc;
IB_MREQ.addr <= r.paddr(12 downto 1);
IB_MREQ.din <= r.mdin;
VM_DOUT <= ivm_dout;
VM_STAT <= ivm_stat;
MMU_CNTL <= immu_cntl;
EM_MREQ <= iem_mreq;
end process proc_next;
IB_MREQ_M <= IB_MREQ; -- external drive master port
DM_STAT_VM.ibmreq <= IB_MREQ;
DM_STAT_VM.ibsres <= IB_SRES;
end syn;
|
--!
--! @file: exercise5_9.vhd
--! @brief: alu using when
--! @author: Antonio Gutierrez
--! @date: 2013-10-23
--!
--!
--------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_all;
--------------------------------------
entity alu is
generic
port (
a, b: in std_logic_vector(N-1 downto 0);
cin: in std_logic_vector(N-1 downto 0);
opcode: in std_logic_vector(3 downto 0);
y: out std_logic_vector(N-1 downto 0));
end entity alu;
--------------------------------------
architecture circuit of alu is
signal a_sig, b_sig: signed(N-1 downto 0);
signal y_unsig: std_logic_vector(N-1 downto 0);
signal y_sig: signed(N-1 downto 0);
signal small_int: integer range 0 to 1;
begin
-- logic unit --
y_unsig <= not a when "000" else
not b when "001" else
a and b when "010" else
a or b when "011" else
a nand b when "100" else
a nor b when "101" else
a xor b when "110" else
a xnor b;
-- arithmetic unit
a_sig <= signed(a);
b_sig <= signed(b);
small_int <= 1 when cin='1' else 0;
y_sig <= a_sig when "000" else
b_sig when "001" else
a_sig + 1 when "010" else
b_sig + 1 when "011" else
a_sig - 1 when "100" else
b_sig - 1 when "101" else
a_sig + b_sig when "110" else
a_sig + b_sig + small_int;
-- mux
y <= y_unsig when opcode(3)='0' else std_logic_vector(y_sig);
end architecture circuit;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity sid_coeffs is
port (
clk : in std_logic;
addr : in integer range 0 to 2047;
val : out std_logic_vector(15 downto 0)
);
end entity;
architecture beh of sid_coeffs is
type mtype is array(0 to 2047) of std_logic_vector(15 downto 0);
constant coef: mtype := (
x"02d5", x"02d5", x"02d5", x"02d5", x"02d5", x"02d5", x"02d5", x"02d5", x"02d5", x"02d5", x"02d5", x"02d5", x"02d5", x"02d5", x"02d5", x"02d5",
x"02d5", x"02d8", x"02d8", x"02d8", x"02d8", x"02d8", x"02d8", x"02d8", x"02d8", x"02d8", x"02d8", x"02d8", x"02d8", x"02d8", x"02d8", x"02d8",
x"02d8", x"02d8", x"02db", x"02db", x"02db", x"02db", x"02db", x"02db", x"02db", x"02db", x"02db", x"02db", x"02db", x"02db", x"02db", x"02db",
x"02db", x"02df", x"02df", x"02df", x"02df", x"02df", x"02df", x"02df", x"02df", x"02df", x"02df", x"02df", x"02df", x"02df", x"02df", x"02df",
x"02e2", x"02e2", x"02e2", x"02e2", x"02e2", x"02e2", x"02e2", x"02e2", x"02e2", x"02e2", x"02e2", x"02e2", x"02e2", x"02e5", x"02e5", x"02e5",
x"02e5", x"02e5", x"02e5", x"02e5", x"02e5", x"02e5", x"02e5", x"02e5", x"02e5", x"02e8", x"02e8", x"02e8", x"02e8", x"02e8", x"02e8", x"02e8",
x"02e8", x"02e8", x"02e8", x"02e8", x"02ec", x"02ec", x"02ec", x"02ec", x"02ec", x"02ec", x"02ec", x"02ec", x"02ec", x"02ec", x"02ef", x"02ef",
x"02ef", x"02ef", x"02ef", x"02ef", x"02ef", x"02ef", x"02ef", x"02ef", x"02f2", x"02f2", x"02f2", x"02f2", x"02f2", x"02f2", x"02f2", x"02f2",
x"02f6", x"02f6", x"02f6", x"02f6", x"02f6", x"02f6", x"02f6", x"02f6", x"02f6", x"02f9", x"02f9", x"02f9", x"02f9", x"02f9", x"02f9", x"02f9",
x"02f9", x"02f9", x"02fc", x"02fc", x"02fc", x"02fc", x"02fc", x"02fc", x"02fc", x"02fc", x"02fc", x"0300", x"0300", x"0300", x"0300", x"0300",
x"0300", x"0300", x"0300", x"0300", x"0303", x"0303", x"0303", x"0303", x"0303", x"0303", x"0303", x"0303", x"0303", x"0306", x"0306", x"0306",
x"0306", x"0306", x"0306", x"0306", x"0306", x"0309", x"0309", x"0309", x"0309", x"0309", x"0309", x"0309", x"0309", x"030d", x"030d", x"030d",
x"030d", x"030d", x"030d", x"030d", x"0310", x"0310", x"0310", x"0310", x"0310", x"0310", x"0310", x"0313", x"0313", x"0313", x"0313", x"0313",
x"0313", x"0317", x"0317", x"0317", x"0317", x"0317", x"0317", x"031a", x"031a", x"031a", x"031a", x"031a", x"031a", x"031d", x"031d", x"031d",
x"031d", x"031d", x"0320", x"0320", x"0320", x"0320", x"0320", x"0324", x"0324", x"0324", x"0324", x"0324", x"0327", x"0327", x"0327", x"0327",
x"0327", x"032a", x"032a", x"032a", x"032a", x"032e", x"032e", x"032e", x"032e", x"0331", x"0331", x"0331", x"0331", x"0334", x"0334", x"0334",
x"0338", x"0338", x"0338", x"0338", x"033b", x"033b", x"033b", x"033b", x"033e", x"033e", x"033e", x"033e", x"0341", x"0341", x"0341", x"0345",
x"0345", x"0345", x"0345", x"0348", x"0348", x"0348", x"0348", x"034b", x"034b", x"034b", x"034f", x"034f", x"034f", x"034f", x"0352", x"0352",
x"0352", x"0355", x"0355", x"0355", x"0355", x"0358", x"0358", x"0358", x"035c", x"035c", x"035c", x"035c", x"035f", x"035f", x"035f", x"0362",
x"0362", x"0362", x"0366", x"0366", x"0366", x"0369", x"0369", x"0369", x"036c", x"036c", x"036c", x"0370", x"0370", x"0370", x"0373", x"0373",
x"0373", x"0376", x"0376", x"0376", x"0379", x"0379", x"0379", x"037d", x"037d", x"0380", x"0380", x"0380", x"0383", x"0383", x"0383", x"0387",
x"0387", x"038a", x"038a", x"038d", x"038d", x"038d", x"0390", x"0390", x"0394", x"0394", x"0397", x"0397", x"0397", x"039a", x"039a", x"039e",
x"039e", x"03a1", x"03a1", x"03a4", x"03a4", x"03a8", x"03a8", x"03ab", x"03ab", x"03ae", x"03ae", x"03b1", x"03b1", x"03b5", x"03b8", x"03b8",
x"03bb", x"03bb", x"03bf", x"03bf", x"03c2", x"03c5", x"03c5", x"03c8", x"03c8", x"03cc", x"03cf", x"03cf", x"03d2", x"03d6", x"03d6", x"03d9",
x"03dc", x"03dc", x"03e0", x"03e0", x"03e3", x"03e6", x"03e6", x"03e9", x"03ed", x"03ed", x"03f0", x"03f0", x"03f3", x"03f7", x"03f7", x"03fa",
x"03fd", x"03fd", x"0400", x"0400", x"0404", x"0404", x"0407", x"040a", x"040a", x"040e", x"040e", x"0411", x"0414", x"0414", x"0418", x"0418",
x"041b", x"041e", x"041e", x"0421", x"0421", x"0425", x"0428", x"0428", x"042b", x"042b", x"042f", x"0432", x"0432", x"0435", x"0438", x"0438",
x"043c", x"043c", x"043f", x"0442", x"0442", x"0446", x"0449", x"044c", x"044c", x"0450", x"0453", x"0453", x"0456", x"0459", x"045d", x"045d",
x"0460", x"0463", x"0467", x"0467", x"046a", x"046d", x"0470", x"0474", x"0477", x"0477", x"047a", x"047e", x"0481", x"0484", x"0488", x"048b",
x"048e", x"0491", x"0495", x"0498", x"049b", x"049f", x"04a2", x"04a5", x"04a8", x"04ac", x"04af", x"04b2", x"04b6", x"04b9", x"04c0", x"04c3",
x"04c6", x"04c9", x"04cd", x"04d3", x"04d7", x"04da", x"04dd", x"04e4", x"04e7", x"04ee", x"04f1", x"04f4", x"04fb", x"04fe", x"0505", x"0508",
x"050f", x"0512", x"0519", x"051c", x"0522", x"0526", x"052c", x"0533", x"0536", x"053d", x"0543", x"0547", x"054d", x"0554", x"055a", x"0561",
x"0568", x"056b", x"0571", x"0578", x"057f", x"0585", x"058c", x"0592", x"0599", x"059c", x"05a3", x"05a9", x"05b0", x"05b7", x"05bd", x"05c4",
x"05ca", x"05d1", x"05d8", x"05de", x"05e5", x"05eb", x"05f2", x"05f9", x"05ff", x"0606", x"060c", x"0613", x"0619", x"0620", x"0627", x"062d",
x"0634", x"063a", x"0641", x"0648", x"064e", x"0655", x"065f", x"0665", x"066c", x"0672", x"0679", x"0680", x"0689", x"0690", x"0697", x"069d",
x"06a7", x"06ae", x"06b4", x"06be", x"06c5", x"06cb", x"06d5", x"06dc", x"06e6", x"06ec", x"06f6", x"06fd", x"0707", x"070d", x"0717", x"071e",
x"0728", x"072e", x"0738", x"0742", x"0749", x"0752", x"075c", x"0763", x"076d", x"0777", x"0781", x"078a", x"0794", x"079b", x"07a5", x"07af",
x"07b9", x"07c2", x"07cc", x"07d6", x"07e0", x"07ea", x"07f7", x"0801", x"080b", x"0815", x"081f", x"082c", x"0836", x"0840", x"084d", x"0857",
x"0864", x"086e", x"0878", x"0885", x"0892", x"089c", x"08a9", x"08b3", x"08c0", x"08cd", x"08da", x"08e4", x"08f1", x"08ff", x"090c", x"0919",
x"0926", x"0933", x"0941", x"094e", x"095b", x"0968", x"0975", x"0986", x"0993", x"09a0", x"09b1", x"09be", x"09cb", x"09db", x"09e9", x"09f9",
x"0a09", x"0a17", x"0a27", x"0a34", x"0a45", x"0a55", x"0a66", x"0a76", x"0a83", x"0a94", x"0aa4", x"0ab5", x"0ac5", x"0ad6", x"0ae6", x"0af7",
x"0b07", x"0b18", x"0b2b", x"0b3c", x"0b4c", x"0b5d", x"0b71", x"0b81", x"0b91", x"0ba5", x"0bb6", x"0bc6", x"0bda", x"0bea", x"0bfe", x"0c12",
x"0c22", x"0c36", x"0c47", x"0c5a", x"0c6e", x"0c7f", x"0c92", x"0ca6", x"0cba", x"0cce", x"0ce1", x"0cf2", x"0d06", x"0d19", x"0d2d", x"0d41",
x"0d55", x"0d69", x"0d7c", x"0d93", x"0da7", x"0dbb", x"0dcf", x"0de2", x"0df9", x"0e0d", x"0e21", x"0e38", x"0e4c", x"0e60", x"0e77", x"0e8a",
x"0ea2", x"0eb5", x"0ecc", x"0ee0", x"0ef7", x"0f0b", x"0f22", x"0f39", x"0f4d", x"0f64", x"0f7b", x"0f8f", x"0fa6", x"0fbd", x"0fd4", x"0feb",
x"0fff", x"1016", x"102d", x"1044", x"105b", x"1072", x"1089", x"10a0", x"10b7", x"10ce", x"10e5", x"1100", x"1117", x"112e", x"1145", x"115c",
x"1176", x"118d", x"11a4", x"11bb", x"11d6", x"11ed", x"1204", x"121e", x"1235", x"1250", x"1267", x"1281", x"1298", x"12b2", x"12ca", x"12e4",
x"12fb", x"1315", x"1330", x"1347", x"1361", x"137b", x"1392", x"13ad", x"13c7", x"13e2", x"13f9", x"1413", x"142d", x"1448", x"1462", x"147c",
x"1497", x"14ae", x"14cb", x"14e6", x"1500", x"151e", x"1538", x"1556", x"1573", x"1591", x"15af", x"15d0", x"15ed", x"160b", x"162c", x"164d",
x"166e", x"168f", x"16b0", x"16d1", x"16f2", x"1712", x"1737", x"1758", x"177c", x"17a0", x"17c1", x"17e5", x"180a", x"182e", x"1852", x"187a",
x"189e", x"18c2", x"18ea", x"190e", x"1935", x"195a", x"1981", x"19a9", x"19cd", x"19f4", x"1a1c", x"1a43", x"1a6b", x"1a93", x"1aba", x"1ae2",
x"1b09", x"1b34", x"1b5b", x"1b83", x"1bab", x"1bd5", x"1bfd", x"1c24", x"1c4f", x"1c77", x"1ca2", x"1cc9", x"1cf4", x"1d1b", x"1d46", x"1d6e",
x"1d99", x"1dc0", x"1deb", x"1e13", x"1e3d", x"1e68", x"1e90", x"1ebb", x"1ee5", x"1f10", x"1f3b", x"1f66", x"1f91", x"1fbb", x"1fe6", x"2011",
x"203f", x"206a", x"2095", x"20c3", x"20ee", x"211c", x"2147", x"2175", x"21a3", x"21ce", x"21fc", x"222a", x"2258", x"2286", x"22b1", x"22df",
x"2311", x"233f", x"236d", x"239b", x"23c9", x"23f7", x"2429", x"2457", x"2488", x"24b6", x"24e8", x"2516", x"2547", x"2575", x"25a7", x"25d8",
x"260a", x"263b", x"266c", x"269e", x"26cf", x"2701", x"2732", x"2764", x"2795", x"27c6", x"27fb", x"282c", x"285e", x"2893", x"28c4", x"28f9",
x"292d", x"295f", x"2994", x"29c8", x"29fa", x"2a2e", x"2a63", x"2a98", x"2acd", x"2b01", x"2b36", x"2b6b", x"2ba3", x"2bd7", x"2c0c", x"2c41",
x"2c79", x"2cad", x"2ce5", x"2d1a", x"2d52", x"2d87", x"2dbf", x"2df7", x"2e2f", x"2e64", x"2e9c", x"2ed4", x"2f0c", x"2f44", x"2f7c", x"2fb4",
x"2fef", x"3027", x"305f", x"3097", x"30d2", x"310a", x"3145", x"317d", x"31b9", x"31f1", x"322c", x"3267", x"329f", x"32db", x"3316", x"3351",
x"338d", x"33c8", x"3403", x"343e", x"347a", x"34b5", x"34f0", x"352f", x"356a", x"35a6", x"35e4", x"361f", x"365e", x"3699", x"36d8", x"3716",
x"3755", x"3790", x"37d2", x"3811", x"3853", x"3895", x"38d6", x"391c", x"3961", x"39a6", x"39eb", x"3a34", x"3a79", x"3ac1", x"3b0a", x"3b56",
x"3b9e", x"3be6", x"3c32", x"3c7e", x"3cc7", x"3d12", x"3d5e", x"3daa", x"3df6", x"3e41", x"3e8d", x"3ed9", x"3f25", x"3f74", x"3fbf", x"400b",
x"4057", x"409f", x"40eb", x"4137", x"4186", x"41d2", x"4221", x"4270", x"42bf", x"4311", x"4364", x"43b6", x"440f", x"4465", x"44c1", x"451d",
x"457d", x"45df", x"4650", x"46c6", x"4747", x"47c7", x"484e", x"48d2", x"4959", x"49dd", x"4a67", x"4af1", x"4b7f", x"4c10", x"4ca1", x"4d35",
x"3b31", x"3b87", x"3bdd", x"3c36", x"3c88", x"3cda", x"3d2d", x"3d78", x"3dc4", x"3e09", x"3e52", x"3e97", x"3edc", x"3f21", x"3f67", x"3fac",
x"3ff1", x"4033", x"4078", x"40ba", x"40ff", x"4141", x"4186", x"41c8", x"420d", x"424f", x"4294", x"42d6", x"431b", x"4360", x"43a6", x"43eb",
x"4433", x"4478", x"44c1", x"4506", x"454f", x"4597", x"45df", x"462b", x"4674", x"46bc", x"4705", x"4750", x"4799", x"47e5", x"482d", x"4879",
x"48c1", x"490a", x"4956", x"499e", x"49e7", x"4a2f", x"4a78", x"4ac0", x"4b08", x"4b51", x"4b96", x"4bdb", x"4c24", x"4c69", x"4cab", x"4cf0",
x"4d35", x"4d77", x"4db9", x"4dfb", x"4e39", x"4e7b", x"4eba", x"4ef8", x"4f3a", x"4f79", x"4fb4", x"4ff3", x"5031", x"506d", x"50ab", x"50e7",
x"5125", x"5161", x"519c", x"51da", x"5216", x"5251", x"528c", x"52cb", x"5306", x"5341", x"537d", x"53bb", x"53f7", x"5435", x"5471", x"54af",
x"54ee", x"5529", x"5568", x"55a6", x"55e5", x"5623", x"5662", x"569d", x"56dc", x"571a", x"5759", x"5798", x"57d6", x"5815", x"5853", x"5892",
x"58d1", x"590f", x"594e", x"598c", x"59c8", x"5a06", x"5a45", x"5a83", x"5abf", x"5afd", x"5b39", x"5b77", x"5bb2", x"5bf1", x"5c2c", x"5c68",
x"5ca6", x"5ce2", x"5d1d", x"5d58", x"5d93", x"5dcf", x"5e0a", x"5e45", x"5e81", x"5ebc", x"5ef7", x"5f32", x"5f6e", x"5fa9", x"5fe4", x"6020",
x"605b", x"6093", x"60ce", x"610a", x"6145", x"6180", x"61bb", x"61f7", x"622f", x"626a", x"62a5", x"62e1", x"631c", x"6354", x"638f", x"63cb",
x"6406", x"643e", x"6479", x"64b4", x"64f0", x"6528", x"6563", x"659e", x"65d6", x"6612", x"664d", x"6688", x"66c0", x"66fb", x"6737", x"676f",
x"67aa", x"67e5", x"6821", x"6859", x"6894", x"68cf", x"6907", x"6943", x"697e", x"69b6", x"69f1", x"6a2c", x"6a68", x"6aa0", x"6adb", x"6b16",
x"6b52", x"6b8a", x"6bc5", x"6c00", x"6c38", x"6c74", x"6caf", x"6cea", x"6d25", x"6d5d", x"6d99", x"6dd4", x"6e0f", x"6e4b", x"6e83", x"6ebe",
x"6ef9", x"6f34", x"6f70", x"6fab", x"6fe6", x"7022", x"705a", x"7095", x"70d0", x"710c", x"7147", x"7182", x"71bd", x"71f9", x"7234", x"726f",
x"72ab", x"72e6", x"7324", x"7360", x"739b", x"73d6", x"7412", x"744d", x"7488", x"74c7", x"7502", x"753d", x"7579", x"75b7", x"75f3", x"762e",
x"766d", x"76a8", x"76e3", x"7722", x"775d", x"779c", x"77d7", x"7815", x"7851", x"788f", x"78cb", x"7909", x"7948", x"7983", x"79c2", x"7a00",
x"7a3f", x"7a7a", x"7ab9", x"7af7", x"7b36", x"7b75", x"7bb0", x"7bee", x"7c2d", x"7c6c", x"7caa", x"7ce9", x"7d27", x"7d66", x"7da5", x"7de3",
x"7e22", x"7e64", x"7ea2", x"7ee1", x"7f1f", x"7f5e", x"7f9d", x"7fde", x"801d", x"805c", x"809a", x"80dc", x"811b", x"8159", x"819b", x"81da",
x"8218", x"825a", x"8299", x"82db", x"8319", x"835b", x"839a", x"83d8", x"841a", x"8459", x"849b", x"84dd", x"851b", x"855d", x"859c", x"85de",
x"861c", x"865e", x"86a0", x"86de", x"8720", x"875f", x"87a1", x"87e3", x"8821", x"8863", x"88a5", x"88e4", x"8926", x"8967", x"89a9", x"89e8",
x"8a2a", x"8a6c", x"8aaa", x"8aec", x"8b2e", x"8b70", x"8baf", x"8bf0", x"8c32", x"8c74", x"8cb6", x"8cf5", x"8d37", x"8d78", x"8dba", x"8df9",
x"8e3b", x"8e7d", x"8ebf", x"8f00", x"8f3f", x"8f81", x"8fc3", x"9005", x"9047", x"9085", x"90c7", x"9109", x"914b", x"9189", x"91cb", x"920d",
x"924f", x"9291", x"92d0", x"9311", x"9353", x"9395", x"93d4", x"9416", x"9458", x"9499", x"94d8", x"951a", x"955c", x"959e", x"95dc", x"961e",
x"9660", x"969f", x"96e0", x"9722", x"9761", x"97a3", x"97e5", x"9823", x"9865", x"98a4", x"98e6", x"9928", x"9966", x"99a8", x"99e7", x"9a28",
x"9a6a", x"9aa9", x"9aeb", x"9b29", x"9b6b", x"9bad", x"9bef", x"9c31", x"9c73", x"9cb5", x"9cf7", x"9d39", x"9d7a", x"9dbc", x"9dfe", x"9e43",
x"9e85", x"9ec7", x"9f0c", x"9f4e", x"9f90", x"9fd5", x"a017", x"a05c", x"a0a1", x"a0e3", x"a129", x"a16a", x"a1b0", x"a1f5", x"a237", x"a27c",
x"a2c1", x"a306", x"a348", x"a38d", x"a3d2", x"a418", x"a45d", x"a49f", x"a4e4", x"a529", x"a56e", x"a5b3", x"a5f9", x"a63a", x"a680", x"a6c5",
x"a70a", x"a74f", x"a794", x"a7d6", x"a81b", x"a861", x"a8a6", x"a8e8", x"a92d", x"a972", x"a9b4", x"a9f9", x"aa3e", x"aa80", x"aac5", x"ab07",
x"ab4c", x"ab8e", x"abd3", x"ac15", x"ac5a", x"ac9c", x"acde", x"ad23", x"ad65", x"ada7", x"ade9", x"ae2b", x"ae6d", x"aeaf", x"aef1", x"af33",
x"af74", x"afb6", x"aff8", x"b03a", x"b079", x"b0bb", x"b0f9", x"b13b", x"b17a", x"b1b8", x"b1fa", x"b239", x"b277", x"b2b6", x"b2f4", x"b333",
x"b372", x"b3b0", x"b3eb", x"b42a", x"b465", x"b4a4", x"b4df", x"b51b", x"b559", x"b594", x"b5d0", x"b60b", x"b643", x"b67e", x"b6ba", x"b6f2",
x"b72d", x"b765", x"b79d", x"b7d8", x"b810", x"b848", x"b87d", x"b8b5", x"b8ed", x"b922", x"b95a", x"b98e", x"b9c3", x"b9f8", x"ba2c", x"ba61",
x"ba96", x"bac7", x"bafc", x"bb2d", x"bb5f", x"bb90", x"bbc5", x"bbf6", x"bc24", x"bc56", x"bc87", x"bcb9", x"bce7", x"bd18", x"bd46", x"bd74",
x"bda6", x"bdd4", x"be02", x"be30", x"be5e", x"be89", x"beb7", x"bee5", x"bf10", x"bf3e", x"bf69", x"bf97", x"bfc2", x"bfed", x"c018", x"c043",
x"c06d", x"c098", x"c0c3", x"c0ee", x"c115", x"c140", x"c16b", x"c193", x"c1bd", x"c1e5", x"c20d", x"c234", x"c25f", x"c286", x"c2ae", x"c2d5",
x"c2fd", x"c325", x"c34c", x"c370", x"c398", x"c3bf", x"c3e4", x"c40b", x"c42f", x"c457", x"c47b", x"c4a3", x"c4c7", x"c4eb", x"c513", x"c537",
x"c55b", x"c57f", x"c5a4", x"c5c8", x"c5ec", x"c610", x"c635", x"c659", x"c67d", x"c6a1", x"c6c2", x"c6e6", x"c70b", x"c72c", x"c750", x"c774",
x"c795", x"c7b9", x"c7da", x"c7fe", x"c81f", x"c844", x"c865", x"c885", x"c8aa", x"c8cb", x"c8ef", x"c910", x"c931", x"c952", x"c976", x"c997",
x"c9b8", x"c9d9", x"c9fa", x"ca1e", x"ca3f", x"ca60", x"ca81", x"caa2", x"cac3", x"cae4", x"cb05", x"cb29", x"cb4a", x"cb6b", x"cb8c", x"cbad",
x"cbce", x"cbee", x"cc0f", x"cc30", x"cc51", x"cc72", x"cc93", x"ccb4", x"ccd8", x"ccf9", x"cd1a", x"cd3b", x"cd5c", x"cd7d", x"cd9e", x"cdbf",
x"cde3", x"ce04", x"ce25", x"ce46", x"ce67", x"ce88", x"cea9", x"ceca", x"ceeb", x"cf0c", x"cf2d", x"cf4e", x"cf6e", x"cf8f", x"cfb0", x"cfd1",
x"cff2", x"d010", x"d031", x"d052", x"d073", x"d094", x"d0b1", x"d0d2", x"d0f3", x"d111", x"d132", x"d153", x"d170", x"d191", x"d1af", x"d1d0",
x"d1ee", x"d20e", x"d22c", x"d24d", x"d26b", x"d28c", x"d2a9", x"d2c7", x"d2e8", x"d306", x"d323", x"d341", x"d362", x"d37f", x"d39d", x"d3bb",
x"d3d8", x"d3f6", x"d414", x"d431", x"d452", x"d470", x"d48a", x"d4a8", x"d4c6", x"d4e3", x"d501", x"d51f", x"d53c", x"d55a", x"d574", x"d592",
x"d5af", x"d5ca", x"d5e7", x"d605", x"d61f", x"d63d", x"d657", x"d675", x"d68f", x"d6ad", x"d6c7", x"d6e5", x"d6ff", x"d71a", x"d737", x"d752",
x"d76c", x"d787", x"d7a4", x"d7bf", x"d7d9", x"d7f3", x"d80e", x"d828", x"d842", x"d85d", x"d877", x"d891", x"d8ac", x"d8c6", x"d8dd", x"d8f7",
x"d912", x"d92c", x"d943", x"d95e", x"d978", x"d98f", x"d9a9", x"d9c0", x"d9db", x"d9f2", x"da0c", x"da23", x"da3e", x"da55", x"da6c", x"da83",
x"da9d", x"dab4", x"dacb", x"dae2", x"daf9", x"db10", x"db27", x"db3f", x"db56", x"db6d", x"db84", x"db9b", x"dbb2", x"dbc6", x"dbdd", x"dbf4",
x"dc0b", x"dc1f", x"dc36", x"dc49", x"dc60", x"dc74", x"dc8b", x"dc9f", x"dcb3", x"dcca", x"dcde", x"dcf1", x"dd05", x"dd19", x"dd2d", x"dd40",
x"dd54", x"dd68", x"dd7c", x"dd90", x"dda3", x"ddb7", x"ddcb", x"dddb", x"ddef", x"de03", x"de13", x"de27", x"de3b", x"de4b", x"de5f", x"de70",
x"de83", x"de94", x"dea4", x"deb8", x"dec8", x"ded9", x"deed", x"defd", x"df0e", x"df1e", x"df2f", x"df3f", x"df50", x"df60", x"df70", x"df81",
x"df91", x"dfa2", x"dfb2", x"dfc3", x"dfd3", x"dfe0", x"dff1", x"e001", x"e012", x"e01f", x"e030", x"e040", x"e04d", x"e05e", x"e06b", x"e07b",
x"e088", x"e099", x"e0a6", x"e0b7", x"e0c4", x"e0d1", x"e0e1", x"e0ef", x"e0fc", x"e10c", x"e119", x"e127", x"e134", x"e144", x"e151", x"e15f",
x"e16c", x"e179", x"e186", x"e197", x"e1a4", x"e1b1", x"e1be", x"e1cb", x"e1d8", x"e1e6", x"e1f3", x"e200", x"e20d", x"e217", x"e224", x"e231",
x"e23f", x"e24c", x"e259", x"e266", x"e270", x"e27d", x"e28a", x"e298", x"e2a1", x"e2af", x"e2bc", x"e2c9", x"e2d3", x"e2e0", x"e2ed", x"e2f7",
x"e304", x"e311", x"e31b", x"e328", x"e336", x"e340", x"e34d", x"e357", x"e364", x"e371", x"e37b", x"e388", x"e392", x"e39f", x"e3a9", x"e3b6",
x"e3c3", x"e3cd", x"e3da", x"e3e4", x"e3ee", x"e3fb", x"e405", x"e412", x"e41c", x"e426", x"e430", x"e43d", x"e447", x"e451", x"e45b", x"e465",
x"e472", x"e47c", x"e486", x"e490", x"e499", x"e4a3", x"e4ad", x"e4b7", x"e4c1", x"e4cb", x"e4d5", x"e4db", x"e4e5", x"e4ef", x"e4f9", x"e503",
x"e50d", x"e513", x"e51d", x"e527", x"e52e", x"e538", x"e541", x"e548", x"e552", x"e55c", x"e562", x"e56c", x"e573", x"e57d", x"e583", x"e58d",
x"e594", x"e59e", x"e5a4", x"e5ab", x"e5b5", x"e5bb", x"e5c5", x"e5cc", x"e5d2", x"e5dc", x"e5e3", x"e5e9", x"e5f0", x"e5fa", x"e601", x"e607",
x"e60e", x"e618", x"e61e", x"e625", x"e62b", x"e632", x"e639", x"e642", x"e649", x"e650", x"e656", x"e65d", x"e663", x"e66a", x"e671", x"e677",
x"e67e", x"e684", x"e68b", x"e691", x"e698", x"e69f", x"e6a5", x"e6ac", x"e6b2", x"e6b9", x"e6c0", x"e6c6", x"e6cd", x"e6d3", x"e6da", x"e6dd",
x"e6e4", x"e6ea", x"e6f1", x"e6f8", x"e6fe", x"e705", x"e708", x"e70f", x"e715", x"e71c", x"e722", x"e729", x"e72c", x"e733", x"e739", x"e740",
x"e747", x"e74d", x"e751", x"e757", x"e75e", x"e764", x"e768", x"e76e", x"e775", x"e77b", x"e782", x"e785", x"e78c", x"e792", x"e799", x"e7a0"
);
begin
process(clk)
begin
if rising_edge(clk) then
val <= coef(addr);
end if;
end process;
end beh;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity sid_coeffs is
port (
clk : in std_logic;
addr : in integer range 0 to 2047;
val : out std_logic_vector(15 downto 0)
);
end entity;
architecture beh of sid_coeffs is
type mtype is array(0 to 2047) of std_logic_vector(15 downto 0);
constant coef: mtype := (
x"02d5", x"02d5", x"02d5", x"02d5", x"02d5", x"02d5", x"02d5", x"02d5", x"02d5", x"02d5", x"02d5", x"02d5", x"02d5", x"02d5", x"02d5", x"02d5",
x"02d5", x"02d8", x"02d8", x"02d8", x"02d8", x"02d8", x"02d8", x"02d8", x"02d8", x"02d8", x"02d8", x"02d8", x"02d8", x"02d8", x"02d8", x"02d8",
x"02d8", x"02d8", x"02db", x"02db", x"02db", x"02db", x"02db", x"02db", x"02db", x"02db", x"02db", x"02db", x"02db", x"02db", x"02db", x"02db",
x"02db", x"02df", x"02df", x"02df", x"02df", x"02df", x"02df", x"02df", x"02df", x"02df", x"02df", x"02df", x"02df", x"02df", x"02df", x"02df",
x"02e2", x"02e2", x"02e2", x"02e2", x"02e2", x"02e2", x"02e2", x"02e2", x"02e2", x"02e2", x"02e2", x"02e2", x"02e2", x"02e5", x"02e5", x"02e5",
x"02e5", x"02e5", x"02e5", x"02e5", x"02e5", x"02e5", x"02e5", x"02e5", x"02e5", x"02e8", x"02e8", x"02e8", x"02e8", x"02e8", x"02e8", x"02e8",
x"02e8", x"02e8", x"02e8", x"02e8", x"02ec", x"02ec", x"02ec", x"02ec", x"02ec", x"02ec", x"02ec", x"02ec", x"02ec", x"02ec", x"02ef", x"02ef",
x"02ef", x"02ef", x"02ef", x"02ef", x"02ef", x"02ef", x"02ef", x"02ef", x"02f2", x"02f2", x"02f2", x"02f2", x"02f2", x"02f2", x"02f2", x"02f2",
x"02f6", x"02f6", x"02f6", x"02f6", x"02f6", x"02f6", x"02f6", x"02f6", x"02f6", x"02f9", x"02f9", x"02f9", x"02f9", x"02f9", x"02f9", x"02f9",
x"02f9", x"02f9", x"02fc", x"02fc", x"02fc", x"02fc", x"02fc", x"02fc", x"02fc", x"02fc", x"02fc", x"0300", x"0300", x"0300", x"0300", x"0300",
x"0300", x"0300", x"0300", x"0300", x"0303", x"0303", x"0303", x"0303", x"0303", x"0303", x"0303", x"0303", x"0303", x"0306", x"0306", x"0306",
x"0306", x"0306", x"0306", x"0306", x"0306", x"0309", x"0309", x"0309", x"0309", x"0309", x"0309", x"0309", x"0309", x"030d", x"030d", x"030d",
x"030d", x"030d", x"030d", x"030d", x"0310", x"0310", x"0310", x"0310", x"0310", x"0310", x"0310", x"0313", x"0313", x"0313", x"0313", x"0313",
x"0313", x"0317", x"0317", x"0317", x"0317", x"0317", x"0317", x"031a", x"031a", x"031a", x"031a", x"031a", x"031a", x"031d", x"031d", x"031d",
x"031d", x"031d", x"0320", x"0320", x"0320", x"0320", x"0320", x"0324", x"0324", x"0324", x"0324", x"0324", x"0327", x"0327", x"0327", x"0327",
x"0327", x"032a", x"032a", x"032a", x"032a", x"032e", x"032e", x"032e", x"032e", x"0331", x"0331", x"0331", x"0331", x"0334", x"0334", x"0334",
x"0338", x"0338", x"0338", x"0338", x"033b", x"033b", x"033b", x"033b", x"033e", x"033e", x"033e", x"033e", x"0341", x"0341", x"0341", x"0345",
x"0345", x"0345", x"0345", x"0348", x"0348", x"0348", x"0348", x"034b", x"034b", x"034b", x"034f", x"034f", x"034f", x"034f", x"0352", x"0352",
x"0352", x"0355", x"0355", x"0355", x"0355", x"0358", x"0358", x"0358", x"035c", x"035c", x"035c", x"035c", x"035f", x"035f", x"035f", x"0362",
x"0362", x"0362", x"0366", x"0366", x"0366", x"0369", x"0369", x"0369", x"036c", x"036c", x"036c", x"0370", x"0370", x"0370", x"0373", x"0373",
x"0373", x"0376", x"0376", x"0376", x"0379", x"0379", x"0379", x"037d", x"037d", x"0380", x"0380", x"0380", x"0383", x"0383", x"0383", x"0387",
x"0387", x"038a", x"038a", x"038d", x"038d", x"038d", x"0390", x"0390", x"0394", x"0394", x"0397", x"0397", x"0397", x"039a", x"039a", x"039e",
x"039e", x"03a1", x"03a1", x"03a4", x"03a4", x"03a8", x"03a8", x"03ab", x"03ab", x"03ae", x"03ae", x"03b1", x"03b1", x"03b5", x"03b8", x"03b8",
x"03bb", x"03bb", x"03bf", x"03bf", x"03c2", x"03c5", x"03c5", x"03c8", x"03c8", x"03cc", x"03cf", x"03cf", x"03d2", x"03d6", x"03d6", x"03d9",
x"03dc", x"03dc", x"03e0", x"03e0", x"03e3", x"03e6", x"03e6", x"03e9", x"03ed", x"03ed", x"03f0", x"03f0", x"03f3", x"03f7", x"03f7", x"03fa",
x"03fd", x"03fd", x"0400", x"0400", x"0404", x"0404", x"0407", x"040a", x"040a", x"040e", x"040e", x"0411", x"0414", x"0414", x"0418", x"0418",
x"041b", x"041e", x"041e", x"0421", x"0421", x"0425", x"0428", x"0428", x"042b", x"042b", x"042f", x"0432", x"0432", x"0435", x"0438", x"0438",
x"043c", x"043c", x"043f", x"0442", x"0442", x"0446", x"0449", x"044c", x"044c", x"0450", x"0453", x"0453", x"0456", x"0459", x"045d", x"045d",
x"0460", x"0463", x"0467", x"0467", x"046a", x"046d", x"0470", x"0474", x"0477", x"0477", x"047a", x"047e", x"0481", x"0484", x"0488", x"048b",
x"048e", x"0491", x"0495", x"0498", x"049b", x"049f", x"04a2", x"04a5", x"04a8", x"04ac", x"04af", x"04b2", x"04b6", x"04b9", x"04c0", x"04c3",
x"04c6", x"04c9", x"04cd", x"04d3", x"04d7", x"04da", x"04dd", x"04e4", x"04e7", x"04ee", x"04f1", x"04f4", x"04fb", x"04fe", x"0505", x"0508",
x"050f", x"0512", x"0519", x"051c", x"0522", x"0526", x"052c", x"0533", x"0536", x"053d", x"0543", x"0547", x"054d", x"0554", x"055a", x"0561",
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x"e088", x"e099", x"e0a6", x"e0b7", x"e0c4", x"e0d1", x"e0e1", x"e0ef", x"e0fc", x"e10c", x"e119", x"e127", x"e134", x"e144", x"e151", x"e15f",
x"e16c", x"e179", x"e186", x"e197", x"e1a4", x"e1b1", x"e1be", x"e1cb", x"e1d8", x"e1e6", x"e1f3", x"e200", x"e20d", x"e217", x"e224", x"e231",
x"e23f", x"e24c", x"e259", x"e266", x"e270", x"e27d", x"e28a", x"e298", x"e2a1", x"e2af", x"e2bc", x"e2c9", x"e2d3", x"e2e0", x"e2ed", x"e2f7",
x"e304", x"e311", x"e31b", x"e328", x"e336", x"e340", x"e34d", x"e357", x"e364", x"e371", x"e37b", x"e388", x"e392", x"e39f", x"e3a9", x"e3b6",
x"e3c3", x"e3cd", x"e3da", x"e3e4", x"e3ee", x"e3fb", x"e405", x"e412", x"e41c", x"e426", x"e430", x"e43d", x"e447", x"e451", x"e45b", x"e465",
x"e472", x"e47c", x"e486", x"e490", x"e499", x"e4a3", x"e4ad", x"e4b7", x"e4c1", x"e4cb", x"e4d5", x"e4db", x"e4e5", x"e4ef", x"e4f9", x"e503",
x"e50d", x"e513", x"e51d", x"e527", x"e52e", x"e538", x"e541", x"e548", x"e552", x"e55c", x"e562", x"e56c", x"e573", x"e57d", x"e583", x"e58d",
x"e594", x"e59e", x"e5a4", x"e5ab", x"e5b5", x"e5bb", x"e5c5", x"e5cc", x"e5d2", x"e5dc", x"e5e3", x"e5e9", x"e5f0", x"e5fa", x"e601", x"e607",
x"e60e", x"e618", x"e61e", x"e625", x"e62b", x"e632", x"e639", x"e642", x"e649", x"e650", x"e656", x"e65d", x"e663", x"e66a", x"e671", x"e677",
x"e67e", x"e684", x"e68b", x"e691", x"e698", x"e69f", x"e6a5", x"e6ac", x"e6b2", x"e6b9", x"e6c0", x"e6c6", x"e6cd", x"e6d3", x"e6da", x"e6dd",
x"e6e4", x"e6ea", x"e6f1", x"e6f8", x"e6fe", x"e705", x"e708", x"e70f", x"e715", x"e71c", x"e722", x"e729", x"e72c", x"e733", x"e739", x"e740",
x"e747", x"e74d", x"e751", x"e757", x"e75e", x"e764", x"e768", x"e76e", x"e775", x"e77b", x"e782", x"e785", x"e78c", x"e792", x"e799", x"e7a0"
);
begin
process(clk)
begin
if rising_edge(clk) then
val <= coef(addr);
end if;
end process;
end beh;
|
--==============================================================================
--! @file ddr3_ctrl_wrapper.vhd
--==============================================================================
--! Standard library
library IEEE;
--! Standard packages
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
--! Specific packages
use work.ddr3_ctrl_wrapper_pkg.all;
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- DDR3 Controller Wrapper
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
--! @brief
--! DDR3 interface wrapper for MCB
--------------------------------------------------------------------------------
--! @details
--! DDR3 interface wrapper for Xilinx MCB (Memory Controller
--! Block). This core is based on the code generated by Xilinx CoreGen for
--! the MCB.
--------------------------------------------------------------------------------
--! @version
--! 0.1 | mc | 12.07.2011 | File creation and Doxygen comments
--! 0.2 | mc | 06.07.2012 | Add bank4_32b_32b and bank5_32b_32b support
--!
--! @author
--! mc : Matthieu Cattin, CERN (BE-CO-HT)
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
--------------------------------------------------------------------------------
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--------------------------------------------------------------------------------
--==============================================================================
--! Entity declaration for ddr3_ctrl_wrapper
--==============================================================================
entity ddr3_ctrl_wrapper is
generic(
--! Bank and port size selection
g_BANK_PORT_SELECT : string := "SPEC_BANK3_32B_32B";
--! Core's clock period in ps
g_MEMCLK_PERIOD : integer := 3000;
--! If TRUE, uses Xilinx calibration core (Input term, DQS centering)
g_CALIB_SOFT_IP : string := "TRUE";
--! User ports addresses maping (BANK_ROW_COLUMN or ROW_BANK_COLUMN)
g_MEM_ADDR_ORDER : string := "ROW_BANK_COLUMN";
--! Simulation mode
g_SIMULATION : string := "FALSE";
--! DDR3 data port width
g_NUM_DQ_PINS : integer := 16;
--! DDR3 address port width
g_MEM_ADDR_WIDTH : integer := 14;
--! DDR3 bank address width
g_MEM_BANKADDR_WIDTH : integer := 3;
--! Port 0 data mask size (8-bit granularity)
g_P0_MASK_SIZE : integer := 4;
--! Port 0 data width
g_P0_DATA_PORT_SIZE : integer := 32;
--! Port 0 byte address width
g_P0_BYTE_ADDR_WIDTH : integer := 30;
--! Port 1 data mask size (8-bit granularity)
g_P1_MASK_SIZE : integer := 4;
--! Port 1 data width
g_P1_DATA_PORT_SIZE : integer := 32;
--! Port 1 byte address width
g_P1_BYTE_ADDR_WIDTH : integer := 30
);
port(
----------------------------------------------------------------------------
-- Clock and reset
----------------------------------------------------------------------------
--! Core's single ended clock input
clk_i : in std_logic;
--! Core's reset input (active low)
rst_n_i : in std_logic;
----------------------------------------------------------------------------
-- Status
----------------------------------------------------------------------------
--! Indicates end of calibration sequence at startup
calib_done_o : out std_logic;
----------------------------------------------------------------------------
-- DDR3 interface
----------------------------------------------------------------------------
--! DDR3 data bus
ddr3_dq_b : inout std_logic_vector(g_NUM_DQ_PINS-1 downto 0);
--! DDR3 address bus
ddr3_a_o : out std_logic_vector(g_MEM_ADDR_WIDTH-1 downto 0);
--! DDR3 bank address
ddr3_ba_o : out std_logic_vector(g_MEM_BANKADDR_WIDTH-1 downto 0);
--! DDR3 row address strobe
ddr3_ras_n_o : out std_logic;
--! DDR3 column address strobe
ddr3_cas_n_o : out std_logic;
--! DDR3 write enable
ddr3_we_n_o : out std_logic;
--! DDR3 on-die termination
ddr3_odt_o : out std_logic;
--! DDR3 reset
ddr3_rst_n_o : out std_logic;
--! DDR3 clock enable
ddr3_cke_o : out std_logic;
--! DDR3 lower byte data mask
ddr3_dm_o : out std_logic;
--! DDR3 upper byte data mask
ddr3_udm_o : out std_logic;
--! DDR3 lower byte data strobe (pos)
ddr3_dqs_p_b : inout std_logic;
--! DDR3 lower byte data strobe (neg)
ddr3_dqs_n_b : inout std_logic;
--! DDR3 upper byte data strobe (pos)
ddr3_udqs_p_b : inout std_logic;
--! DDR3 upper byte data strobe (pos)
ddr3_udqs_n_b : inout std_logic;
--! DDR3 clock (pos)
ddr3_clk_p_o : out std_logic;
--! DDR3 clock (neg)
ddr3_clk_n_o : out std_logic;
--! MCB internal termination calibration resistor
ddr3_rzq_b : inout std_logic;
--! MCB internal termination calibration
ddr3_zio_b : inout std_logic;
----------------------------------------------------------------------------
-- Port 0
----------------------------------------------------------------------------
p0_cmd_clk_i : in std_logic;
p0_cmd_en_i : in std_logic;
p0_cmd_instr_i : in std_logic_vector(2 downto 0);
p0_cmd_bl_i : in std_logic_vector(5 downto 0);
p0_cmd_byte_addr_i : in std_logic_vector(g_P0_BYTE_ADDR_WIDTH - 1 downto 0);
p0_cmd_empty_o : out std_logic;
p0_cmd_full_o : out std_logic;
p0_wr_clk_i : in std_logic;
p0_wr_en_i : in std_logic;
p0_wr_mask_i : in std_logic_vector(g_P0_MASK_SIZE - 1 downto 0);
p0_wr_data_i : in std_logic_vector(g_P0_DATA_PORT_SIZE - 1 downto 0);
p0_wr_full_o : out std_logic;
p0_wr_empty_o : out std_logic;
p0_wr_count_o : out std_logic_vector(6 downto 0);
p0_wr_underrun_o : out std_logic;
p0_wr_error_o : out std_logic;
p0_rd_clk_i : in std_logic;
p0_rd_en_i : in std_logic;
p0_rd_data_o : out std_logic_vector(g_P0_DATA_PORT_SIZE - 1 downto 0);
p0_rd_full_o : out std_logic;
p0_rd_empty_o : out std_logic;
p0_rd_count_o : out std_logic_vector(6 downto 0);
p0_rd_overflow_o : out std_logic;
p0_rd_error_o : out std_logic;
----------------------------------------------------------------------------
-- Port 1
----------------------------------------------------------------------------
p1_cmd_clk_i : in std_logic;
p1_cmd_en_i : in std_logic;
p1_cmd_instr_i : in std_logic_vector(2 downto 0);
p1_cmd_bl_i : in std_logic_vector(5 downto 0);
p1_cmd_byte_addr_i : in std_logic_vector(g_P1_BYTE_ADDR_WIDTH - 1 downto 0);
p1_cmd_empty_o : out std_logic;
p1_cmd_full_o : out std_logic;
p1_wr_clk_i : in std_logic;
p1_wr_en_i : in std_logic;
p1_wr_mask_i : in std_logic_vector(g_P1_MASK_SIZE - 1 downto 0);
p1_wr_data_i : in std_logic_vector(g_P1_DATA_PORT_SIZE - 1 downto 0);
p1_wr_full_o : out std_logic;
p1_wr_empty_o : out std_logic;
p1_wr_count_o : out std_logic_vector(6 downto 0);
p1_wr_underrun_o : out std_logic;
p1_wr_error_o : out std_logic;
p1_rd_clk_i : in std_logic;
p1_rd_en_i : in std_logic;
p1_rd_data_o : out std_logic_vector(g_P1_DATA_PORT_SIZE - 1 downto 0);
p1_rd_full_o : out std_logic;
p1_rd_empty_o : out std_logic;
p1_rd_count_o : out std_logic_vector(6 downto 0);
p1_rd_overflow_o : out std_logic;
p1_rd_error_o : out std_logic
);
end entity ddr3_ctrl_wrapper;
--==============================================================================
--! Architecure declaration for ddr3_ctrl_wrapper
--==============================================================================
architecture rtl of ddr3_ctrl_wrapper is
-- Components generated from Xilinx CoreGen are stored in ddr3_ctrl_wrapper_pkg
--==============================================================================
--! Architecure begin
--==============================================================================
begin
----------------------------------------------------------------------------
-- Selected board/bank check
----------------------------------------------------------------------------
gen_test_bank_port_select : if(g_BANK_PORT_SELECT /= "SPEC_BANK3_32B_32B" and
g_BANK_PORT_SELECT /= "SPEC_BANK3_64B_32B" and
g_BANK_PORT_SELECT /= "SVEC_BANK4_32B_32B" and
g_BANK_PORT_SELECT /= "SVEC_BANK4_64B_32B" and
g_BANK_PORT_SELECT /= "SVEC_BANK5_32B_32B" and
g_BANK_PORT_SELECT /= "SVEC_BANK5_64B_32B" and
g_BANK_PORT_SELECT /= "VFC_BANK1_32B_32B" and
g_BANK_PORT_SELECT /= "VFC_BANK1_64B_32B") generate
assert false report "ddr3_ctrl_wrapper: Selected bank or port size is no supported. Currently supported values are: SPEC_BANK3_64B_32B, SPEC_BANK3_32B_32B, SVEC_BANK4_32B_32B, SVEC_BANK4_64B_32B, SVEC_BANK5_32B_32B, SVEC_BANK5_64B_32B, VFC_BANK1_32B_32B, VFC_BANK1_64B_32B" severity failure;
end generate gen_test_bank_port_select;
----------------------------------------------------------------------------
-- SPEC
----------------------------------------------------------------------------
gen_spec_bank3_32b_32b : if(g_BANK_PORT_SELECT = "SPEC_BANK3_32B_32B") generate
cmp_ddr3_ctrl : ddr3_ctrl_spec_bank3_32b_32b
generic map (
C3_P0_MASK_SIZE => 4,
C3_P0_DATA_PORT_SIZE => 32,
C3_P1_MASK_SIZE => 4,
C3_P1_DATA_PORT_SIZE => 32,
C3_MEMCLK_PERIOD => g_MEMCLK_PERIOD,
C3_RST_ACT_LOW => 1, -- Active low
C3_CALIB_SOFT_IP => g_CALIB_SOFT_IP,
C3_MEM_ADDR_ORDER => g_MEM_ADDR_ORDER,
C3_NUM_DQ_PINS => g_NUM_DQ_PINS,
C3_MEM_ADDR_WIDTH => g_MEM_ADDR_WIDTH,
C3_MEM_BANKADDR_WIDTH => g_MEM_BANKADDR_WIDTH,
C3_SIMULATION => g_SIMULATION,
C3_INPUT_CLK_TYPE => "SINGLE_ENDED"
)
port map (
c3_sys_clk => clk_i,
c3_sys_rst_i => rst_n_i,
c3_clk0 => open,
c3_rst0 => open,
c3_calib_done => calib_done_o,
mcb3_dram_dq => ddr3_dq_b,
mcb3_dram_a => ddr3_a_o,
mcb3_dram_ba => ddr3_ba_o,
mcb3_dram_ras_n => ddr3_ras_n_o,
mcb3_dram_cas_n => ddr3_cas_n_o,
mcb3_dram_we_n => ddr3_we_n_o,
mcb3_dram_odt => ddr3_odt_o,
mcb3_dram_cke => ddr3_cke_o,
mcb3_dram_ck => ddr3_clk_p_o,
mcb3_dram_ck_n => ddr3_clk_n_o,
mcb3_dram_dqs => ddr3_dqs_p_b,
mcb3_dram_dqs_n => ddr3_dqs_n_b,
mcb3_dram_reset_n => ddr3_rst_n_o,
mcb3_dram_udqs => ddr3_udqs_p_b, -- for X16 parts
mcb3_dram_udqs_n => ddr3_udqs_n_b, -- for X16 parts
mcb3_dram_udm => ddr3_udm_o, -- for X16 parts
mcb3_dram_dm => ddr3_dm_o,
mcb3_rzq => ddr3_rzq_b,
c3_p0_cmd_clk => p0_cmd_clk_i,
c3_p0_cmd_en => p0_cmd_en_i,
c3_p0_cmd_instr => p0_cmd_instr_i,
c3_p0_cmd_bl => p0_cmd_bl_i,
c3_p0_cmd_byte_addr => p0_cmd_byte_addr_i,
c3_p0_cmd_empty => p0_cmd_empty_o,
c3_p0_cmd_full => p0_cmd_full_o,
c3_p0_wr_clk => p0_wr_clk_i,
c3_p0_wr_en => p0_wr_en_i,
c3_p0_wr_mask => p0_wr_mask_i,
c3_p0_wr_data => p0_wr_data_i,
c3_p0_wr_full => p0_wr_full_o,
c3_p0_wr_empty => p0_wr_empty_o,
c3_p0_wr_count => p0_wr_count_o,
c3_p0_wr_underrun => p0_wr_underrun_o,
c3_p0_wr_error => p0_wr_error_o,
c3_p0_rd_clk => p0_rd_clk_i,
c3_p0_rd_en => p0_rd_en_i,
c3_p0_rd_data => p0_rd_data_o,
c3_p0_rd_full => p0_rd_full_o,
c3_p0_rd_empty => p0_rd_empty_o,
c3_p0_rd_count => p0_rd_count_o,
c3_p0_rd_overflow => p0_rd_overflow_o,
c3_p0_rd_error => p0_rd_error_o,
c3_p1_cmd_clk => p1_cmd_clk_i,
c3_p1_cmd_en => p1_cmd_en_i,
c3_p1_cmd_instr => p1_cmd_instr_i,
c3_p1_cmd_bl => p1_cmd_bl_i,
c3_p1_cmd_byte_addr => p1_cmd_byte_addr_i,
c3_p1_cmd_empty => p1_cmd_empty_o,
c3_p1_cmd_full => p1_cmd_full_o,
c3_p1_wr_clk => p1_wr_clk_i,
c3_p1_wr_en => p1_wr_en_i,
c3_p1_wr_mask => p1_wr_mask_i,
c3_p1_wr_data => p1_wr_data_i,
c3_p1_wr_full => p1_wr_full_o,
c3_p1_wr_empty => p1_wr_empty_o,
c3_p1_wr_count => p1_wr_count_o,
c3_p1_wr_underrun => p1_wr_underrun_o,
c3_p1_wr_error => p1_wr_error_o,
c3_p1_rd_clk => p1_rd_clk_i,
c3_p1_rd_en => p1_rd_en_i,
c3_p1_rd_data => p1_rd_data_o,
c3_p1_rd_full => p1_rd_full_o,
c3_p1_rd_empty => p1_rd_empty_o,
c3_p1_rd_count => p1_rd_count_o,
c3_p1_rd_overflow => p1_rd_overflow_o,
c3_p1_rd_error => p1_rd_error_o
);
end generate gen_spec_bank3_32b_32b;
gen_spec_bank3_64b_32b : if(g_BANK_PORT_SELECT = "SPEC_BANK3_64B_32B") generate
cmp_ddr3_ctrl : ddr3_ctrl_spec_bank3_64b_32b
generic map (
C3_P0_MASK_SIZE => 4,
C3_P0_DATA_PORT_SIZE => 32,
C3_P1_MASK_SIZE => 4,
C3_P1_DATA_PORT_SIZE => 32,
C3_MEMCLK_PERIOD => g_MEMCLK_PERIOD,
C3_RST_ACT_LOW => 1, -- Active low
C3_CALIB_SOFT_IP => g_CALIB_SOFT_IP,
C3_MEM_ADDR_ORDER => g_MEM_ADDR_ORDER,
C3_NUM_DQ_PINS => g_NUM_DQ_PINS,
C3_MEM_ADDR_WIDTH => g_MEM_ADDR_WIDTH,
C3_MEM_BANKADDR_WIDTH => g_MEM_BANKADDR_WIDTH,
C3_SIMULATION => g_SIMULATION,
C3_INPUT_CLK_TYPE => "SINGLE_ENDED"
)
port map (
c3_sys_clk => clk_i,
c3_sys_rst_i => rst_n_i,
c3_clk0 => open,
c3_rst0 => open,
c3_calib_done => calib_done_o,
mcb3_dram_dq => ddr3_dq_b,
mcb3_dram_a => ddr3_a_o,
mcb3_dram_ba => ddr3_ba_o,
mcb3_dram_ras_n => ddr3_ras_n_o,
mcb3_dram_cas_n => ddr3_cas_n_o,
mcb3_dram_we_n => ddr3_we_n_o,
mcb3_dram_odt => ddr3_odt_o,
mcb3_dram_cke => ddr3_cke_o,
mcb3_dram_ck => ddr3_clk_p_o,
mcb3_dram_ck_n => ddr3_clk_n_o,
mcb3_dram_dqs => ddr3_dqs_p_b,
mcb3_dram_dqs_n => ddr3_dqs_n_b,
mcb3_dram_reset_n => ddr3_rst_n_o,
mcb3_dram_udqs => ddr3_udqs_p_b, -- for X16 parts
mcb3_dram_udqs_n => ddr3_udqs_n_b, -- for X16 parts
mcb3_dram_udm => ddr3_udm_o, -- for X16 parts
mcb3_dram_dm => ddr3_dm_o,
mcb3_rzq => ddr3_rzq_b,
c3_p0_cmd_clk => p0_cmd_clk_i,
c3_p0_cmd_en => p0_cmd_en_i,
c3_p0_cmd_instr => p0_cmd_instr_i,
c3_p0_cmd_bl => p0_cmd_bl_i,
c3_p0_cmd_byte_addr => p0_cmd_byte_addr_i,
c3_p0_cmd_empty => p0_cmd_empty_o,
c3_p0_cmd_full => p0_cmd_full_o,
c3_p0_wr_clk => p0_wr_clk_i,
c3_p0_wr_en => p0_wr_en_i,
c3_p0_wr_mask => p0_wr_mask_i,
c3_p0_wr_data => p0_wr_data_i,
c3_p0_wr_full => p0_wr_full_o,
c3_p0_wr_empty => p0_wr_empty_o,
c3_p0_wr_count => p0_wr_count_o,
c3_p0_wr_underrun => p0_wr_underrun_o,
c3_p0_wr_error => p0_wr_error_o,
c3_p0_rd_clk => p0_rd_clk_i,
c3_p0_rd_en => p0_rd_en_i,
c3_p0_rd_data => p0_rd_data_o,
c3_p0_rd_full => p0_rd_full_o,
c3_p0_rd_empty => p0_rd_empty_o,
c3_p0_rd_count => p0_rd_count_o,
c3_p0_rd_overflow => p0_rd_overflow_o,
c3_p0_rd_error => p0_rd_error_o,
c3_p1_cmd_clk => p1_cmd_clk_i,
c3_p1_cmd_en => p1_cmd_en_i,
c3_p1_cmd_instr => p1_cmd_instr_i,
c3_p1_cmd_bl => p1_cmd_bl_i,
c3_p1_cmd_byte_addr => p1_cmd_byte_addr_i,
c3_p1_cmd_empty => p1_cmd_empty_o,
c3_p1_cmd_full => p1_cmd_full_o,
c3_p1_wr_clk => p1_wr_clk_i,
c3_p1_wr_en => p1_wr_en_i,
c3_p1_wr_mask => p1_wr_mask_i,
c3_p1_wr_data => p1_wr_data_i,
c3_p1_wr_full => p1_wr_full_o,
c3_p1_wr_empty => p1_wr_empty_o,
c3_p1_wr_count => p1_wr_count_o,
c3_p1_wr_underrun => p1_wr_underrun_o,
c3_p1_wr_error => p1_wr_error_o,
c3_p1_rd_clk => p1_rd_clk_i,
c3_p1_rd_en => p1_rd_en_i,
c3_p1_rd_data => p1_rd_data_o,
c3_p1_rd_full => p1_rd_full_o,
c3_p1_rd_empty => p1_rd_empty_o,
c3_p1_rd_count => p1_rd_count_o,
c3_p1_rd_overflow => p1_rd_overflow_o,
c3_p1_rd_error => p1_rd_error_o
);
end generate gen_spec_bank3_64b_32b;
----------------------------------------------------------------------------
-- Common port
----------------------------------------------------------------------------
ddr3_zio_b <= 'Z';
end architecture rtl;
--==============================================================================
--! Architecure end
--==============================================================================
|
--==============================================================================
--! @file ddr3_ctrl_wrapper.vhd
--==============================================================================
--! Standard library
library IEEE;
--! Standard packages
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
--! Specific packages
use work.ddr3_ctrl_wrapper_pkg.all;
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- DDR3 Controller Wrapper
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
--! @brief
--! DDR3 interface wrapper for MCB
--------------------------------------------------------------------------------
--! @details
--! DDR3 interface wrapper for Xilinx MCB (Memory Controller
--! Block). This core is based on the code generated by Xilinx CoreGen for
--! the MCB.
--------------------------------------------------------------------------------
--! @version
--! 0.1 | mc | 12.07.2011 | File creation and Doxygen comments
--! 0.2 | mc | 06.07.2012 | Add bank4_32b_32b and bank5_32b_32b support
--!
--! @author
--! mc : Matthieu Cattin, CERN (BE-CO-HT)
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
--------------------------------------------------------------------------------
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--------------------------------------------------------------------------------
--==============================================================================
--! Entity declaration for ddr3_ctrl_wrapper
--==============================================================================
entity ddr3_ctrl_wrapper is
generic(
--! Bank and port size selection
g_BANK_PORT_SELECT : string := "SPEC_BANK3_32B_32B";
--! Core's clock period in ps
g_MEMCLK_PERIOD : integer := 3000;
--! If TRUE, uses Xilinx calibration core (Input term, DQS centering)
g_CALIB_SOFT_IP : string := "TRUE";
--! User ports addresses maping (BANK_ROW_COLUMN or ROW_BANK_COLUMN)
g_MEM_ADDR_ORDER : string := "ROW_BANK_COLUMN";
--! Simulation mode
g_SIMULATION : string := "FALSE";
--! DDR3 data port width
g_NUM_DQ_PINS : integer := 16;
--! DDR3 address port width
g_MEM_ADDR_WIDTH : integer := 14;
--! DDR3 bank address width
g_MEM_BANKADDR_WIDTH : integer := 3;
--! Port 0 data mask size (8-bit granularity)
g_P0_MASK_SIZE : integer := 4;
--! Port 0 data width
g_P0_DATA_PORT_SIZE : integer := 32;
--! Port 0 byte address width
g_P0_BYTE_ADDR_WIDTH : integer := 30;
--! Port 1 data mask size (8-bit granularity)
g_P1_MASK_SIZE : integer := 4;
--! Port 1 data width
g_P1_DATA_PORT_SIZE : integer := 32;
--! Port 1 byte address width
g_P1_BYTE_ADDR_WIDTH : integer := 30
);
port(
----------------------------------------------------------------------------
-- Clock and reset
----------------------------------------------------------------------------
--! Core's single ended clock input
clk_i : in std_logic;
--! Core's reset input (active low)
rst_n_i : in std_logic;
----------------------------------------------------------------------------
-- Status
----------------------------------------------------------------------------
--! Indicates end of calibration sequence at startup
calib_done_o : out std_logic;
----------------------------------------------------------------------------
-- DDR3 interface
----------------------------------------------------------------------------
--! DDR3 data bus
ddr3_dq_b : inout std_logic_vector(g_NUM_DQ_PINS-1 downto 0);
--! DDR3 address bus
ddr3_a_o : out std_logic_vector(g_MEM_ADDR_WIDTH-1 downto 0);
--! DDR3 bank address
ddr3_ba_o : out std_logic_vector(g_MEM_BANKADDR_WIDTH-1 downto 0);
--! DDR3 row address strobe
ddr3_ras_n_o : out std_logic;
--! DDR3 column address strobe
ddr3_cas_n_o : out std_logic;
--! DDR3 write enable
ddr3_we_n_o : out std_logic;
--! DDR3 on-die termination
ddr3_odt_o : out std_logic;
--! DDR3 reset
ddr3_rst_n_o : out std_logic;
--! DDR3 clock enable
ddr3_cke_o : out std_logic;
--! DDR3 lower byte data mask
ddr3_dm_o : out std_logic;
--! DDR3 upper byte data mask
ddr3_udm_o : out std_logic;
--! DDR3 lower byte data strobe (pos)
ddr3_dqs_p_b : inout std_logic;
--! DDR3 lower byte data strobe (neg)
ddr3_dqs_n_b : inout std_logic;
--! DDR3 upper byte data strobe (pos)
ddr3_udqs_p_b : inout std_logic;
--! DDR3 upper byte data strobe (pos)
ddr3_udqs_n_b : inout std_logic;
--! DDR3 clock (pos)
ddr3_clk_p_o : out std_logic;
--! DDR3 clock (neg)
ddr3_clk_n_o : out std_logic;
--! MCB internal termination calibration resistor
ddr3_rzq_b : inout std_logic;
--! MCB internal termination calibration
ddr3_zio_b : inout std_logic;
----------------------------------------------------------------------------
-- Port 0
----------------------------------------------------------------------------
p0_cmd_clk_i : in std_logic;
p0_cmd_en_i : in std_logic;
p0_cmd_instr_i : in std_logic_vector(2 downto 0);
p0_cmd_bl_i : in std_logic_vector(5 downto 0);
p0_cmd_byte_addr_i : in std_logic_vector(g_P0_BYTE_ADDR_WIDTH - 1 downto 0);
p0_cmd_empty_o : out std_logic;
p0_cmd_full_o : out std_logic;
p0_wr_clk_i : in std_logic;
p0_wr_en_i : in std_logic;
p0_wr_mask_i : in std_logic_vector(g_P0_MASK_SIZE - 1 downto 0);
p0_wr_data_i : in std_logic_vector(g_P0_DATA_PORT_SIZE - 1 downto 0);
p0_wr_full_o : out std_logic;
p0_wr_empty_o : out std_logic;
p0_wr_count_o : out std_logic_vector(6 downto 0);
p0_wr_underrun_o : out std_logic;
p0_wr_error_o : out std_logic;
p0_rd_clk_i : in std_logic;
p0_rd_en_i : in std_logic;
p0_rd_data_o : out std_logic_vector(g_P0_DATA_PORT_SIZE - 1 downto 0);
p0_rd_full_o : out std_logic;
p0_rd_empty_o : out std_logic;
p0_rd_count_o : out std_logic_vector(6 downto 0);
p0_rd_overflow_o : out std_logic;
p0_rd_error_o : out std_logic;
----------------------------------------------------------------------------
-- Port 1
----------------------------------------------------------------------------
p1_cmd_clk_i : in std_logic;
p1_cmd_en_i : in std_logic;
p1_cmd_instr_i : in std_logic_vector(2 downto 0);
p1_cmd_bl_i : in std_logic_vector(5 downto 0);
p1_cmd_byte_addr_i : in std_logic_vector(g_P1_BYTE_ADDR_WIDTH - 1 downto 0);
p1_cmd_empty_o : out std_logic;
p1_cmd_full_o : out std_logic;
p1_wr_clk_i : in std_logic;
p1_wr_en_i : in std_logic;
p1_wr_mask_i : in std_logic_vector(g_P1_MASK_SIZE - 1 downto 0);
p1_wr_data_i : in std_logic_vector(g_P1_DATA_PORT_SIZE - 1 downto 0);
p1_wr_full_o : out std_logic;
p1_wr_empty_o : out std_logic;
p1_wr_count_o : out std_logic_vector(6 downto 0);
p1_wr_underrun_o : out std_logic;
p1_wr_error_o : out std_logic;
p1_rd_clk_i : in std_logic;
p1_rd_en_i : in std_logic;
p1_rd_data_o : out std_logic_vector(g_P1_DATA_PORT_SIZE - 1 downto 0);
p1_rd_full_o : out std_logic;
p1_rd_empty_o : out std_logic;
p1_rd_count_o : out std_logic_vector(6 downto 0);
p1_rd_overflow_o : out std_logic;
p1_rd_error_o : out std_logic
);
end entity ddr3_ctrl_wrapper;
--==============================================================================
--! Architecure declaration for ddr3_ctrl_wrapper
--==============================================================================
architecture rtl of ddr3_ctrl_wrapper is
-- Components generated from Xilinx CoreGen are stored in ddr3_ctrl_wrapper_pkg
--==============================================================================
--! Architecure begin
--==============================================================================
begin
----------------------------------------------------------------------------
-- Selected board/bank check
----------------------------------------------------------------------------
gen_test_bank_port_select : if(g_BANK_PORT_SELECT /= "SPEC_BANK3_32B_32B" and
g_BANK_PORT_SELECT /= "SPEC_BANK3_64B_32B" and
g_BANK_PORT_SELECT /= "SVEC_BANK4_32B_32B" and
g_BANK_PORT_SELECT /= "SVEC_BANK4_64B_32B" and
g_BANK_PORT_SELECT /= "SVEC_BANK5_32B_32B" and
g_BANK_PORT_SELECT /= "SVEC_BANK5_64B_32B" and
g_BANK_PORT_SELECT /= "VFC_BANK1_32B_32B" and
g_BANK_PORT_SELECT /= "VFC_BANK1_64B_32B") generate
assert false report "ddr3_ctrl_wrapper: Selected bank or port size is no supported. Currently supported values are: SPEC_BANK3_64B_32B, SPEC_BANK3_32B_32B, SVEC_BANK4_32B_32B, SVEC_BANK4_64B_32B, SVEC_BANK5_32B_32B, SVEC_BANK5_64B_32B, VFC_BANK1_32B_32B, VFC_BANK1_64B_32B" severity failure;
end generate gen_test_bank_port_select;
----------------------------------------------------------------------------
-- SPEC
----------------------------------------------------------------------------
gen_spec_bank3_32b_32b : if(g_BANK_PORT_SELECT = "SPEC_BANK3_32B_32B") generate
cmp_ddr3_ctrl : ddr3_ctrl_spec_bank3_32b_32b
generic map (
C3_P0_MASK_SIZE => 4,
C3_P0_DATA_PORT_SIZE => 32,
C3_P1_MASK_SIZE => 4,
C3_P1_DATA_PORT_SIZE => 32,
C3_MEMCLK_PERIOD => g_MEMCLK_PERIOD,
C3_RST_ACT_LOW => 1, -- Active low
C3_CALIB_SOFT_IP => g_CALIB_SOFT_IP,
C3_MEM_ADDR_ORDER => g_MEM_ADDR_ORDER,
C3_NUM_DQ_PINS => g_NUM_DQ_PINS,
C3_MEM_ADDR_WIDTH => g_MEM_ADDR_WIDTH,
C3_MEM_BANKADDR_WIDTH => g_MEM_BANKADDR_WIDTH,
C3_SIMULATION => g_SIMULATION,
C3_INPUT_CLK_TYPE => "SINGLE_ENDED"
)
port map (
c3_sys_clk => clk_i,
c3_sys_rst_i => rst_n_i,
c3_clk0 => open,
c3_rst0 => open,
c3_calib_done => calib_done_o,
mcb3_dram_dq => ddr3_dq_b,
mcb3_dram_a => ddr3_a_o,
mcb3_dram_ba => ddr3_ba_o,
mcb3_dram_ras_n => ddr3_ras_n_o,
mcb3_dram_cas_n => ddr3_cas_n_o,
mcb3_dram_we_n => ddr3_we_n_o,
mcb3_dram_odt => ddr3_odt_o,
mcb3_dram_cke => ddr3_cke_o,
mcb3_dram_ck => ddr3_clk_p_o,
mcb3_dram_ck_n => ddr3_clk_n_o,
mcb3_dram_dqs => ddr3_dqs_p_b,
mcb3_dram_dqs_n => ddr3_dqs_n_b,
mcb3_dram_reset_n => ddr3_rst_n_o,
mcb3_dram_udqs => ddr3_udqs_p_b, -- for X16 parts
mcb3_dram_udqs_n => ddr3_udqs_n_b, -- for X16 parts
mcb3_dram_udm => ddr3_udm_o, -- for X16 parts
mcb3_dram_dm => ddr3_dm_o,
mcb3_rzq => ddr3_rzq_b,
c3_p0_cmd_clk => p0_cmd_clk_i,
c3_p0_cmd_en => p0_cmd_en_i,
c3_p0_cmd_instr => p0_cmd_instr_i,
c3_p0_cmd_bl => p0_cmd_bl_i,
c3_p0_cmd_byte_addr => p0_cmd_byte_addr_i,
c3_p0_cmd_empty => p0_cmd_empty_o,
c3_p0_cmd_full => p0_cmd_full_o,
c3_p0_wr_clk => p0_wr_clk_i,
c3_p0_wr_en => p0_wr_en_i,
c3_p0_wr_mask => p0_wr_mask_i,
c3_p0_wr_data => p0_wr_data_i,
c3_p0_wr_full => p0_wr_full_o,
c3_p0_wr_empty => p0_wr_empty_o,
c3_p0_wr_count => p0_wr_count_o,
c3_p0_wr_underrun => p0_wr_underrun_o,
c3_p0_wr_error => p0_wr_error_o,
c3_p0_rd_clk => p0_rd_clk_i,
c3_p0_rd_en => p0_rd_en_i,
c3_p0_rd_data => p0_rd_data_o,
c3_p0_rd_full => p0_rd_full_o,
c3_p0_rd_empty => p0_rd_empty_o,
c3_p0_rd_count => p0_rd_count_o,
c3_p0_rd_overflow => p0_rd_overflow_o,
c3_p0_rd_error => p0_rd_error_o,
c3_p1_cmd_clk => p1_cmd_clk_i,
c3_p1_cmd_en => p1_cmd_en_i,
c3_p1_cmd_instr => p1_cmd_instr_i,
c3_p1_cmd_bl => p1_cmd_bl_i,
c3_p1_cmd_byte_addr => p1_cmd_byte_addr_i,
c3_p1_cmd_empty => p1_cmd_empty_o,
c3_p1_cmd_full => p1_cmd_full_o,
c3_p1_wr_clk => p1_wr_clk_i,
c3_p1_wr_en => p1_wr_en_i,
c3_p1_wr_mask => p1_wr_mask_i,
c3_p1_wr_data => p1_wr_data_i,
c3_p1_wr_full => p1_wr_full_o,
c3_p1_wr_empty => p1_wr_empty_o,
c3_p1_wr_count => p1_wr_count_o,
c3_p1_wr_underrun => p1_wr_underrun_o,
c3_p1_wr_error => p1_wr_error_o,
c3_p1_rd_clk => p1_rd_clk_i,
c3_p1_rd_en => p1_rd_en_i,
c3_p1_rd_data => p1_rd_data_o,
c3_p1_rd_full => p1_rd_full_o,
c3_p1_rd_empty => p1_rd_empty_o,
c3_p1_rd_count => p1_rd_count_o,
c3_p1_rd_overflow => p1_rd_overflow_o,
c3_p1_rd_error => p1_rd_error_o
);
end generate gen_spec_bank3_32b_32b;
gen_spec_bank3_64b_32b : if(g_BANK_PORT_SELECT = "SPEC_BANK3_64B_32B") generate
cmp_ddr3_ctrl : ddr3_ctrl_spec_bank3_64b_32b
generic map (
C3_P0_MASK_SIZE => 4,
C3_P0_DATA_PORT_SIZE => 32,
C3_P1_MASK_SIZE => 4,
C3_P1_DATA_PORT_SIZE => 32,
C3_MEMCLK_PERIOD => g_MEMCLK_PERIOD,
C3_RST_ACT_LOW => 1, -- Active low
C3_CALIB_SOFT_IP => g_CALIB_SOFT_IP,
C3_MEM_ADDR_ORDER => g_MEM_ADDR_ORDER,
C3_NUM_DQ_PINS => g_NUM_DQ_PINS,
C3_MEM_ADDR_WIDTH => g_MEM_ADDR_WIDTH,
C3_MEM_BANKADDR_WIDTH => g_MEM_BANKADDR_WIDTH,
C3_SIMULATION => g_SIMULATION,
C3_INPUT_CLK_TYPE => "SINGLE_ENDED"
)
port map (
c3_sys_clk => clk_i,
c3_sys_rst_i => rst_n_i,
c3_clk0 => open,
c3_rst0 => open,
c3_calib_done => calib_done_o,
mcb3_dram_dq => ddr3_dq_b,
mcb3_dram_a => ddr3_a_o,
mcb3_dram_ba => ddr3_ba_o,
mcb3_dram_ras_n => ddr3_ras_n_o,
mcb3_dram_cas_n => ddr3_cas_n_o,
mcb3_dram_we_n => ddr3_we_n_o,
mcb3_dram_odt => ddr3_odt_o,
mcb3_dram_cke => ddr3_cke_o,
mcb3_dram_ck => ddr3_clk_p_o,
mcb3_dram_ck_n => ddr3_clk_n_o,
mcb3_dram_dqs => ddr3_dqs_p_b,
mcb3_dram_dqs_n => ddr3_dqs_n_b,
mcb3_dram_reset_n => ddr3_rst_n_o,
mcb3_dram_udqs => ddr3_udqs_p_b, -- for X16 parts
mcb3_dram_udqs_n => ddr3_udqs_n_b, -- for X16 parts
mcb3_dram_udm => ddr3_udm_o, -- for X16 parts
mcb3_dram_dm => ddr3_dm_o,
mcb3_rzq => ddr3_rzq_b,
c3_p0_cmd_clk => p0_cmd_clk_i,
c3_p0_cmd_en => p0_cmd_en_i,
c3_p0_cmd_instr => p0_cmd_instr_i,
c3_p0_cmd_bl => p0_cmd_bl_i,
c3_p0_cmd_byte_addr => p0_cmd_byte_addr_i,
c3_p0_cmd_empty => p0_cmd_empty_o,
c3_p0_cmd_full => p0_cmd_full_o,
c3_p0_wr_clk => p0_wr_clk_i,
c3_p0_wr_en => p0_wr_en_i,
c3_p0_wr_mask => p0_wr_mask_i,
c3_p0_wr_data => p0_wr_data_i,
c3_p0_wr_full => p0_wr_full_o,
c3_p0_wr_empty => p0_wr_empty_o,
c3_p0_wr_count => p0_wr_count_o,
c3_p0_wr_underrun => p0_wr_underrun_o,
c3_p0_wr_error => p0_wr_error_o,
c3_p0_rd_clk => p0_rd_clk_i,
c3_p0_rd_en => p0_rd_en_i,
c3_p0_rd_data => p0_rd_data_o,
c3_p0_rd_full => p0_rd_full_o,
c3_p0_rd_empty => p0_rd_empty_o,
c3_p0_rd_count => p0_rd_count_o,
c3_p0_rd_overflow => p0_rd_overflow_o,
c3_p0_rd_error => p0_rd_error_o,
c3_p1_cmd_clk => p1_cmd_clk_i,
c3_p1_cmd_en => p1_cmd_en_i,
c3_p1_cmd_instr => p1_cmd_instr_i,
c3_p1_cmd_bl => p1_cmd_bl_i,
c3_p1_cmd_byte_addr => p1_cmd_byte_addr_i,
c3_p1_cmd_empty => p1_cmd_empty_o,
c3_p1_cmd_full => p1_cmd_full_o,
c3_p1_wr_clk => p1_wr_clk_i,
c3_p1_wr_en => p1_wr_en_i,
c3_p1_wr_mask => p1_wr_mask_i,
c3_p1_wr_data => p1_wr_data_i,
c3_p1_wr_full => p1_wr_full_o,
c3_p1_wr_empty => p1_wr_empty_o,
c3_p1_wr_count => p1_wr_count_o,
c3_p1_wr_underrun => p1_wr_underrun_o,
c3_p1_wr_error => p1_wr_error_o,
c3_p1_rd_clk => p1_rd_clk_i,
c3_p1_rd_en => p1_rd_en_i,
c3_p1_rd_data => p1_rd_data_o,
c3_p1_rd_full => p1_rd_full_o,
c3_p1_rd_empty => p1_rd_empty_o,
c3_p1_rd_count => p1_rd_count_o,
c3_p1_rd_overflow => p1_rd_overflow_o,
c3_p1_rd_error => p1_rd_error_o
);
end generate gen_spec_bank3_64b_32b;
----------------------------------------------------------------------------
-- Common port
----------------------------------------------------------------------------
ddr3_zio_b <= 'Z';
end architecture rtl;
--==============================================================================
--! Architecure end
--==============================================================================
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_05_ch_05_21.vhd,v 1.3 2001-10-26 16:29:34 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- code from book:
entity and_gate is
port ( i : in bit_vector; y : out bit );
end entity and_gate;
-- end of code from book
architecture behavioral of and_gate is
begin
reducer : process (i) is
constant Tpd : delay_length := 2 ns;
variable result : bit;
begin
result := '1';
for index in i'range loop
result := result and i(index);
end loop;
y <= result after Tpd;
end process reducer;
end architecture behavioral;
entity ch_05_21 is
end entity ch_05_21;
library stimulus;
architecture test of ch_05_21 is
-- code from book:
signal serial_select, write_en, bus_clk, serial_wr : bit;
-- end of code from book
use stimulus.stimulus_generators.all;
signal test_input : bit_vector(2 downto 0);
begin
-- code from book:
serial_write_gate : entity work.and_gate
port map ( i(1) => serial_select,
i(2) => write_en,
i(3) => bus_clk,
y => serial_wr );
-- end of code from book
stimulus_proc : all_possible_values( bv => test_input,
delay_between_values => 10 ns );
(serial_select, write_en, bus_clk) <= test_input;
end architecture test;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_05_ch_05_21.vhd,v 1.3 2001-10-26 16:29:34 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- code from book:
entity and_gate is
port ( i : in bit_vector; y : out bit );
end entity and_gate;
-- end of code from book
architecture behavioral of and_gate is
begin
reducer : process (i) is
constant Tpd : delay_length := 2 ns;
variable result : bit;
begin
result := '1';
for index in i'range loop
result := result and i(index);
end loop;
y <= result after Tpd;
end process reducer;
end architecture behavioral;
entity ch_05_21 is
end entity ch_05_21;
library stimulus;
architecture test of ch_05_21 is
-- code from book:
signal serial_select, write_en, bus_clk, serial_wr : bit;
-- end of code from book
use stimulus.stimulus_generators.all;
signal test_input : bit_vector(2 downto 0);
begin
-- code from book:
serial_write_gate : entity work.and_gate
port map ( i(1) => serial_select,
i(2) => write_en,
i(3) => bus_clk,
y => serial_wr );
-- end of code from book
stimulus_proc : all_possible_values( bv => test_input,
delay_between_values => 10 ns );
(serial_select, write_en, bus_clk) <= test_input;
end architecture test;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_05_ch_05_21.vhd,v 1.3 2001-10-26 16:29:34 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- code from book:
entity and_gate is
port ( i : in bit_vector; y : out bit );
end entity and_gate;
-- end of code from book
architecture behavioral of and_gate is
begin
reducer : process (i) is
constant Tpd : delay_length := 2 ns;
variable result : bit;
begin
result := '1';
for index in i'range loop
result := result and i(index);
end loop;
y <= result after Tpd;
end process reducer;
end architecture behavioral;
entity ch_05_21 is
end entity ch_05_21;
library stimulus;
architecture test of ch_05_21 is
-- code from book:
signal serial_select, write_en, bus_clk, serial_wr : bit;
-- end of code from book
use stimulus.stimulus_generators.all;
signal test_input : bit_vector(2 downto 0);
begin
-- code from book:
serial_write_gate : entity work.and_gate
port map ( i(1) => serial_select,
i(2) => write_en,
i(3) => bus_clk,
y => serial_wr );
-- end of code from book
stimulus_proc : all_possible_values( bv => test_input,
delay_between_values => 10 ns );
(serial_select, write_en, bus_clk) <= test_input;
end architecture test;
|
---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Daniel Noyes
--
-- Create Date: SPRING 2015
-- Module Name: ALU_Toplevel
-- Project Name: ALU
-- Target Devices: Spartan-3E
-- Tool versions: Xilinx ISE 14.7
-- Description: ALU top level
---------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.all;
entity ALU is
Port ( CLK : in STD_LOGIC;
RA : in STD_LOGIC_VECTOR (15 downto 0);
RB : in STD_LOGIC_VECTOR (15 downto 0);
OPCODE : in STD_LOGIC_VECTOR (3 downto 0);
CCR : out STD_LOGIC_VECTOR (3 downto 0);
ALU_OUT : out STD_LOGIC_VECTOR (15 downto 0);
LDST_OUT : out STD_LOGIC_VECTOR (15 downto 0));
end ALU;
architecture Structural of ALU is
signal arith : STD_LOGIC_VECTOR (15 downto 0) := (OTHERS => '0');
signal logic : STD_LOGIC_VECTOR (15 downto 0) := (OTHERS => '0');
signal shift : STD_LOGIC_VECTOR (15 downto 0) := (OTHERS => '0');
signal memory : STD_LOGIC_VECTOR (15 downto 0) := (OTHERS => '0');
signal ccr_arith : STD_LOGIC_VECTOR (3 downto 0) := (OTHERS => '0');
signal ccr_logic : STD_LOGIC_VECTOR (3 downto 0) := (OTHERS => '0');
begin
LDST_OUT <= memory;
Arith_Unit: entity work.Arith_Unit
port map( A => RA,
B => RB,
OP => OPCODE(2 downto 0),
CCR => ccr_arith,
RESULT => arith);
Logic_Unit: entity work.Logic_Unit
port map( A => RA,
B => RB,
OP => OPCODE(2 downto 0),
CCR => ccr_logic,
RESULT => logic);
shift_unit: entity work.alu_shift_unit
port map( A => RA,
COUNT => RB(3 downto 0),
OP => opcode(3),
RESULT => shift);
Load_Store_Unit: entity work.Load_Store_Unit
port map( A => RA,
IMMED => RB,
OP => opcode,
RESULT => memory);
ALU_Mux: entity work.ALU_Mux
port map( OP => opcode,
ARITH => arith,
LOGIC => logic,
SHIFT => shift,
MEMORY => memory,
CCR_ARITH => ccr_arith,
CCR_LOGIC => ccr_logic,
ALU_OUT => ALU_OUT,
CCR_OUT => CCR);
end Structural;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3100.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c05s01b00x00p10n01i03100ent IS
ATTRIBUTE attr1 : INTEGER;
END c05s01b00x00p10n01i03100ent;
ARCHITECTURE c05s01b00x00p10n01i03100arch OF c05s01b00x00p10n01i03100ent IS
SIGNAL s1,s2,s3 : BIT;
SIGNAL s4,s5 : INTEGER;
SIGNAL s6,s7 : STRING(1 TO 3);
CONSTANT c1,c2,c3 : BIT := '0';
CONSTANT c4,c5 : INTEGER := 1;
CONSTANT c6,c7 : STRING(1 TO 3) := "ABC";
ATTRIBUTE attr1 OF s3, s7 : SIGNAL IS 1;
ATTRIBUTE attr1 OF OTHERS : SIGNAL IS 20;
ATTRIBUTE attr1 OF c1,c2,c3,c4,c5,c6,c7 : CONSTANT IS 101;
ATTRIBUTE attr1 OF OTHERS : CONSTANT IS 20;
BEGIN
TESTING: PROCESS
BEGIN
ASSERT s1'attr1 = 20 REPORT "Bad value for s1'attr1" SEVERITY FAILURE;
ASSERT s2'attr1 = 20 REPORT "Bad value for s2'attr1" SEVERITY FAILURE;
ASSERT s3'attr1 = 01 REPORT "Bad value for s3'attr1" SEVERITY FAILURE;
ASSERT s4'attr1 = 20 REPORT "Bad value for s4'attr1" SEVERITY FAILURE;
ASSERT s5'attr1 = 20 REPORT "Bad value for s5'attr1" SEVERITY FAILURE;
ASSERT s6'attr1 = 20 REPORT "Bad value for s6'attr1" SEVERITY FAILURE;
ASSERT s7'attr1 = 01 REPORT "Bad value for s7'attr1" SEVERITY FAILURE;
ASSERT c1'attr1 = 101 REPORT "Bad value for c1'attr1" SEVERITY FAILURE;
ASSERT c2'attr1 = 101 REPORT "Bad value for c2'attr1" SEVERITY FAILURE;
ASSERT c3'attr1 = 101 REPORT "Bad value for c3'attr1" SEVERITY FAILURE;
ASSERT c4'attr1 = 101 REPORT "Bad value for c4'attr1" SEVERITY FAILURE;
ASSERT c5'attr1 = 101 REPORT "Bad value for c5'attr1" SEVERITY FAILURE;
ASSERT c6'attr1 = 101 REPORT "Bad value for c6'attr1" SEVERITY FAILURE;
ASSERT c7'attr1 = 101 REPORT "Bad value for c7'attr1" SEVERITY FAILURE;
assert NOT( s1'attr1 = 20 and
s2'attr1 = 20 and
s3'attr1 = 01 and
s4'attr1 = 20 and
s5'attr1 = 20 and
s6'attr1 = 20 and
s7'attr1 = 01 and
c1'attr1 = 101 and
c2'attr1 = 101 and
c3'attr1 = 101 and
c4'attr1 = 101 and
c5'attr1 = 101 and
c6'attr1 = 101 and
c7'attr1 = 101 )
report "***PASSED TEST: c05s01b00x00p10n01i03100"
severity NOTE;
assert ( s1'attr1 = 20 and
s2'attr1 = 20 and
s3'attr1 = 01 and
s4'attr1 = 20 and
s5'attr1 = 20 and
s6'attr1 = 20 and
s7'attr1 = 01 and
c1'attr1 = 101 and
c2'attr1 = 101 and
c3'attr1 = 101 and
c4'attr1 = 101 and
c5'attr1 = 101 and
c6'attr1 = 101 and
c7'attr1 = 101 )
report "***FAILED TEST: c05s01b00x00p10n01i03100 - Reserved word others in entity name list test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c05s01b00x00p10n01i03100arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3100.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c05s01b00x00p10n01i03100ent IS
ATTRIBUTE attr1 : INTEGER;
END c05s01b00x00p10n01i03100ent;
ARCHITECTURE c05s01b00x00p10n01i03100arch OF c05s01b00x00p10n01i03100ent IS
SIGNAL s1,s2,s3 : BIT;
SIGNAL s4,s5 : INTEGER;
SIGNAL s6,s7 : STRING(1 TO 3);
CONSTANT c1,c2,c3 : BIT := '0';
CONSTANT c4,c5 : INTEGER := 1;
CONSTANT c6,c7 : STRING(1 TO 3) := "ABC";
ATTRIBUTE attr1 OF s3, s7 : SIGNAL IS 1;
ATTRIBUTE attr1 OF OTHERS : SIGNAL IS 20;
ATTRIBUTE attr1 OF c1,c2,c3,c4,c5,c6,c7 : CONSTANT IS 101;
ATTRIBUTE attr1 OF OTHERS : CONSTANT IS 20;
BEGIN
TESTING: PROCESS
BEGIN
ASSERT s1'attr1 = 20 REPORT "Bad value for s1'attr1" SEVERITY FAILURE;
ASSERT s2'attr1 = 20 REPORT "Bad value for s2'attr1" SEVERITY FAILURE;
ASSERT s3'attr1 = 01 REPORT "Bad value for s3'attr1" SEVERITY FAILURE;
ASSERT s4'attr1 = 20 REPORT "Bad value for s4'attr1" SEVERITY FAILURE;
ASSERT s5'attr1 = 20 REPORT "Bad value for s5'attr1" SEVERITY FAILURE;
ASSERT s6'attr1 = 20 REPORT "Bad value for s6'attr1" SEVERITY FAILURE;
ASSERT s7'attr1 = 01 REPORT "Bad value for s7'attr1" SEVERITY FAILURE;
ASSERT c1'attr1 = 101 REPORT "Bad value for c1'attr1" SEVERITY FAILURE;
ASSERT c2'attr1 = 101 REPORT "Bad value for c2'attr1" SEVERITY FAILURE;
ASSERT c3'attr1 = 101 REPORT "Bad value for c3'attr1" SEVERITY FAILURE;
ASSERT c4'attr1 = 101 REPORT "Bad value for c4'attr1" SEVERITY FAILURE;
ASSERT c5'attr1 = 101 REPORT "Bad value for c5'attr1" SEVERITY FAILURE;
ASSERT c6'attr1 = 101 REPORT "Bad value for c6'attr1" SEVERITY FAILURE;
ASSERT c7'attr1 = 101 REPORT "Bad value for c7'attr1" SEVERITY FAILURE;
assert NOT( s1'attr1 = 20 and
s2'attr1 = 20 and
s3'attr1 = 01 and
s4'attr1 = 20 and
s5'attr1 = 20 and
s6'attr1 = 20 and
s7'attr1 = 01 and
c1'attr1 = 101 and
c2'attr1 = 101 and
c3'attr1 = 101 and
c4'attr1 = 101 and
c5'attr1 = 101 and
c6'attr1 = 101 and
c7'attr1 = 101 )
report "***PASSED TEST: c05s01b00x00p10n01i03100"
severity NOTE;
assert ( s1'attr1 = 20 and
s2'attr1 = 20 and
s3'attr1 = 01 and
s4'attr1 = 20 and
s5'attr1 = 20 and
s6'attr1 = 20 and
s7'attr1 = 01 and
c1'attr1 = 101 and
c2'attr1 = 101 and
c3'attr1 = 101 and
c4'attr1 = 101 and
c5'attr1 = 101 and
c6'attr1 = 101 and
c7'attr1 = 101 )
report "***FAILED TEST: c05s01b00x00p10n01i03100 - Reserved word others in entity name list test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c05s01b00x00p10n01i03100arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3100.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c05s01b00x00p10n01i03100ent IS
ATTRIBUTE attr1 : INTEGER;
END c05s01b00x00p10n01i03100ent;
ARCHITECTURE c05s01b00x00p10n01i03100arch OF c05s01b00x00p10n01i03100ent IS
SIGNAL s1,s2,s3 : BIT;
SIGNAL s4,s5 : INTEGER;
SIGNAL s6,s7 : STRING(1 TO 3);
CONSTANT c1,c2,c3 : BIT := '0';
CONSTANT c4,c5 : INTEGER := 1;
CONSTANT c6,c7 : STRING(1 TO 3) := "ABC";
ATTRIBUTE attr1 OF s3, s7 : SIGNAL IS 1;
ATTRIBUTE attr1 OF OTHERS : SIGNAL IS 20;
ATTRIBUTE attr1 OF c1,c2,c3,c4,c5,c6,c7 : CONSTANT IS 101;
ATTRIBUTE attr1 OF OTHERS : CONSTANT IS 20;
BEGIN
TESTING: PROCESS
BEGIN
ASSERT s1'attr1 = 20 REPORT "Bad value for s1'attr1" SEVERITY FAILURE;
ASSERT s2'attr1 = 20 REPORT "Bad value for s2'attr1" SEVERITY FAILURE;
ASSERT s3'attr1 = 01 REPORT "Bad value for s3'attr1" SEVERITY FAILURE;
ASSERT s4'attr1 = 20 REPORT "Bad value for s4'attr1" SEVERITY FAILURE;
ASSERT s5'attr1 = 20 REPORT "Bad value for s5'attr1" SEVERITY FAILURE;
ASSERT s6'attr1 = 20 REPORT "Bad value for s6'attr1" SEVERITY FAILURE;
ASSERT s7'attr1 = 01 REPORT "Bad value for s7'attr1" SEVERITY FAILURE;
ASSERT c1'attr1 = 101 REPORT "Bad value for c1'attr1" SEVERITY FAILURE;
ASSERT c2'attr1 = 101 REPORT "Bad value for c2'attr1" SEVERITY FAILURE;
ASSERT c3'attr1 = 101 REPORT "Bad value for c3'attr1" SEVERITY FAILURE;
ASSERT c4'attr1 = 101 REPORT "Bad value for c4'attr1" SEVERITY FAILURE;
ASSERT c5'attr1 = 101 REPORT "Bad value for c5'attr1" SEVERITY FAILURE;
ASSERT c6'attr1 = 101 REPORT "Bad value for c6'attr1" SEVERITY FAILURE;
ASSERT c7'attr1 = 101 REPORT "Bad value for c7'attr1" SEVERITY FAILURE;
assert NOT( s1'attr1 = 20 and
s2'attr1 = 20 and
s3'attr1 = 01 and
s4'attr1 = 20 and
s5'attr1 = 20 and
s6'attr1 = 20 and
s7'attr1 = 01 and
c1'attr1 = 101 and
c2'attr1 = 101 and
c3'attr1 = 101 and
c4'attr1 = 101 and
c5'attr1 = 101 and
c6'attr1 = 101 and
c7'attr1 = 101 )
report "***PASSED TEST: c05s01b00x00p10n01i03100"
severity NOTE;
assert ( s1'attr1 = 20 and
s2'attr1 = 20 and
s3'attr1 = 01 and
s4'attr1 = 20 and
s5'attr1 = 20 and
s6'attr1 = 20 and
s7'attr1 = 01 and
c1'attr1 = 101 and
c2'attr1 = 101 and
c3'attr1 = 101 and
c4'attr1 = 101 and
c5'attr1 = 101 and
c6'attr1 = 101 and
c7'attr1 = 101 )
report "***FAILED TEST: c05s01b00x00p10n01i03100 - Reserved word others in entity name list test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c05s01b00x00p10n01i03100arch;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 20:16:34 11/30/2013
-- Design Name:
-- Module Name: RAM - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.Common.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity RAM is
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
ramaddr : out STD_LOGIC_VECTOR (17 downto 0);
ramdata : inout STD_LOGIC_VECTOR (15 downto 0);
OE : out STD_LOGIC;
WE : out STD_LOGIC;
EN : out STD_LOGIC;
addr : in STD_LOGIC_VECTOR (15 downto 0);
data : in STD_LOGIC_VECTOR (15 downto 0);
dataout: out STD_LOGIC_VECTOR (15 downto 0);
r: in std_logic); --Ϊ1¼´Îª¶Á£¬·ñÔòΪд
end RAM;
architecture Behavioral of RAM is
signal flag: std_logic_vector(1 downto 0):= "00";
begin
process(clk, rst)
begin
if rst = '0' then
OE <= '1';
WE <= '1';
EN <= '1';
flag <= "00";
ramdata <= Int16_Zero;
elsif (clk'event and clk = '1') then
if r = '0' then
case flag is
when "00" =>
EN <= '0';
OE <= '1';
WE <= '1';
ramaddr <= "00" & addr;
ramdata <= data;
flag <= "01";
when "01" =>
WE <= '0';
flag <= "10";
when "10" =>
WE <= '1';
EN <= '1';
flag <= "11";
when others =>
flag <= "00";
end case;
else
case flag is
when "00" =>
EN <= '0';
OE <= '0';
WE <= '1';
ramaddr <= "00" & addr;
ramdata <= "ZZZZZZZZZZZZZZZZ";
flag <= "01";
when "01" =>
dataout <= ramdata;
flag <= "10";
when "10" =>
OE <= '1';
EN <= '1';
flag <= "11";
when others =>
flag <= "00";
end case;
end if;
end if;
end process;
end Behavioral;
|
-------------------------------------------------------------------------------
-- Title : UART
-- Project : UART
-------------------------------------------------------------------------------
-- File : MiniUart.vhd
-- Author : Philippe CARTON
-- ([email protected])
-- Organization:
-- Created : 15/12/2001
-- Last update : 8/1/2003
-- Platform : Foundation 3.1i
-- Simulators : ModelSim 5.5b
-- Synthesizers: Xilinx Synthesis
-- Targets : Xilinx Spartan
-- Dependency : IEEE std_logic_1164, Rxunit.vhd, Txunit.vhd, utils.vhd
-------------------------------------------------------------------------------
-- Description: Uart (Universal Asynchronous Receiver Transmitter) for SoC.
-- Wishbone compatable.
-------------------------------------------------------------------------------
-- Copyright (c) notice
-- This core adheres to the GNU public license
--
-------------------------------------------------------------------------------
-- Revisions :
-- Revision Number :
-- Version :
-- Date :
-- Modifier : name <email>
-- Description :
--
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity MINIUART is
generic (
MainClockSpeed : integer;
DefaultBaud : integer
);
port (
-- Wishbone signals
WB_CLK_I : in std_logic; -- clock
WB_RST_I : in std_logic; -- Reset input
WB_ADR_I : in std_logic_vector(1 downto 0); -- Adress bus
WB_DAT_I : in std_logic_vector(7 downto 0); -- DataIn Bus
WB_DAT_O : out std_logic_vector(7 downto 0); -- DataOut Bus
WB_WE_I : in std_logic; -- Write Enable
WB_STB_I : in std_logic; -- Strobe
WB_ACK_O : out std_logic; -- Acknowledge
-- process signals
IntTx_O : out std_logic; -- Transmit interrupt: indicate waiting for Byte
IntRx_O : out std_logic; -- Receive interrupt: indicate Byte received
BR_Clk_I : in std_logic; -- Clock used for Transmit/Receive
TxD_PAD_O : out std_logic; -- Tx RS232 Line
RxD_PAD_I : in std_logic; -- Rx RS232 Line
ESC_O : out std_logic;
BREAK_O : out std_logic;
uart_irq_n: out std_logic); -- Serial interrupt to CPU core
end MINIUART;
-- Architecture for UART for synthesis
architecture Behaviour of MINIUART is
component Counter
port (
Clk : in std_logic; -- Clock
Reset : in std_logic; -- Reset input
CE : in std_logic; -- Chip Enable
Count : in std_logic_vector (15 downto 0); -- Count revolution
O : out std_logic); -- Output
end component;
component RxUnit
port (
Clk : in std_logic; -- system clock signal
Reset : in std_logic; -- Reset input
Enable : in std_logic; -- Enable input
ReadA : in std_logic; -- Async Read Received Byte
RxD : in std_logic; -- RS-232 data input
RxAv : out std_logic; -- Byte available
DataO : out std_logic_vector(7 downto 0) -- Byte received
);
end component;
component TxUnit
port (
Clk : in std_logic; -- Clock signal
Reset : in std_logic; -- Reset input
Enable : in std_logic; -- Enable input
LoadA : in std_logic; -- Asynchronous Load
TxD : out std_logic; -- RS-232 data output
Busy : out std_logic; -- Tx Busy
DataI : in std_logic_vector(7 downto 0) -- Byte to transmit
);
end component;
signal RxData : std_logic_vector(7 downto 0); -- Last Byte received
signal RxData1 : std_logic_vector(7 downto 0);
signal TxData : std_logic_vector(7 downto 0); -- Last bytes transmitted
signal SReg : std_logic_vector(3 downto 0); -- Status register
signal CReg : std_logic_vector(7 downto 4); -- Control register
signal EnabRx : std_logic; -- Enable RX unit
signal EnabTx : std_logic; -- Enable TX unit
signal RxAv : std_logic; -- Data Received
signal TxBusy : std_logic; -- Transmiter Busy
signal ReadA : std_logic; -- Async Read receive buffer
signal LoadA : std_logic; -- Async Load transmit buffer
signal Sig0 : std_logic; -- gnd signal
signal Sig1 : std_logic; -- vcc signal
signal Divisor : std_logic_vector(15 downto 0); -- Baud Rate
signal TxBusy_last : std_logic;
signal RxAv_last : std_logic;
begin
sig0 <= '0';
sig1 <= '1';
Uart_Rxrate : Counter -- Baud Rate adjust
port map (BR_CLK_I, sig0, sig1, Divisor, EnabRx);
Uart_Txrate : Counter -- 4 Divider for Tx
port map (BR_CLK_I, Sig0, EnabRx, std_logic_vector(to_unsigned(4, 16)), EnabTx);
-- Uart_TxUnit : TxUnit
-- port map (BR_CLK_I, WB_RST_I, EnabTX, LoadA, TxD_PAD_O, TxBusy, TxData, IntTxFlag, IntTxEn);
Uart_TxUnit : TxUnit
port map (
Clk => BR_CLK_I, -- Clock signal
Reset => WB_RST_I, -- Reset input
Enable => EnabTX, -- Enable input
LoadA => LoadA, -- Asynchronous Load
TxD => TxD_PAD_O, -- RS-232 data output
Busy => TxBusy, -- Tx Busy
DataI => TxData -- Byte to transmit
);
-- Uart_RxUnit : RxUnit
-- port map (BR_CLK_I, WB_RST_I, EnabRX, ReadA, RxD_PAD_I, RxAv, RxData, IntRxFlag, IntRxEn);
Uart_RxUnit : RxUnit
port map (
Clk => BR_CLK_I, -- system clock signal
Reset => WB_RST_I, -- Reset input
Enable => EnabRX, -- Enable input
ReadA => ReadA, -- Async Read Received Byte
RxD => RxD_PAD_I, -- RS-232 data input
RxAv => RxAv, -- Byte available
DataO => RxData -- Byte received
);
SReg(0) <= not TxBusy;
SReg(1) <= RxAv;
-- 16MHz x 1M = 64ms
-- ESCctrl: process(WB_CLK_I)
-- variable count : unsigned(19 downto 0);
-- begin
-- if Rising_Edge(WB_CLK_I) then
-- if (WB_RST_I = '1') then
-- ESC_O <= '1';
-- count := (others => '0');
-- elsif RxData = X"1B" then
-- ESC_O <= '0';
-- count := (others => '1');
-- elsif count > 0 then
-- count := count - 1;
-- else
-- ESC_O <= '1';
-- end if;
-- end if;
-- end process;
BREAKctrl: process(WB_CLK_I)
variable count : unsigned(7 downto 0);
begin
if Rising_Edge(WB_CLK_I) then
RxData1 <= RxData;
if (WB_RST_I = '1') then
BREAK_O <= '1';
count := (others => '0');
elsif RxData1 /= X"1A" and RxData = X"1A" and CReg(7) = '1' then
BREAK_O <= '0';
count := (others => '1');
elsif count > 0 then
count := count - 1;
else
BREAK_O <= '1';
end if;
end if;
end process;
ESC_O <= '0' when RxData = X"1B" and CReg(6) = '1' else '1';
-- Implements WishBone data exchange.
-- Clocked on rising edge. Synchronous Reset RST_I
WBctrl : process(WB_CLK_I, WB_RST_I, WB_STB_I, WB_WE_I, WB_ADR_I)
variable StatM : std_logic_vector(4 downto 0);
begin
if Rising_Edge(WB_CLK_I) then
if (WB_RST_I = '1') then
ReadA <= '0';
LoadA <= '0';
Divisor <= std_logic_vector(to_unsigned(MainClockSpeed / 4 / DefaultBaud, 16));
CReg(7 downto 4) <= "0000";
SReg(2) <= '0';
SReg(3) <= '0';
else
-- Set TX Interrupt flag if enabled on falling edge of TxBusy
if TxBusy_last = '1' and TxBusy = '0' then
if CReg(4) = '1' then
SReg(2) <= '1'; -- not TxBusy;
else
SReg(2) <= '0';
end if;
end if;
TxBusy_last <= TxBusy;
-- Set RX Interrupt flag if enabled on riding edge of RxAv
if RxAv_last = '0' and RxAv = '1' then
if CReg(5) = '1' then
SReg(3) <= '1'; -- RxAv
else
SReg(3) <= '0';
end if;
end if;
RxAv_last <= RxAv;
if (WB_STB_I = '1' and WB_WE_I = '1' and WB_ADR_I = "00") then -- Write Byte to Tx
TxData <= WB_DAT_I;
LoadA <= '1'; -- Load signal
else LoadA <= '0';
end if;
if (WB_STB_I = '1' and WB_WE_I = '0' and WB_ADR_I = "00") then -- Read Byte from Rx
ReadA <= '1'; -- Read signal
else ReadA <= '0';
end if;
if (WB_STB_I = '1' and WB_WE_I = '1' and WB_ADR_I = "01") then -- Write Control
CReg <= WB_DAT_I(7 downto 4);
SReg(2) <= '0';
SReg(3) <= '0';
end if;
if (WB_STB_I = '1' and WB_WE_I = '1' and WB_ADR_I = "10") then -- Write Divisor Low
Divisor(7 downto 0) <= WB_DAT_I;
end if;
if (WB_STB_I = '1' and WB_WE_I = '1' and WB_ADR_I = "11") then -- Write Divisor High
Divisor(15 downto 8) <= WB_DAT_I;
end if;
end if;
end if;
end process;
WB_ACK_O <= WB_STB_I;
WB_DAT_O <=
RxData when WB_ADR_I = "00" else -- Read Byte from Rx
CReg & SReg when WB_ADR_I = "01" else -- Read Control/Status Reg
Divisor(7 downto 0) when WB_ADR_I = "10" else -- Read Divisor Low
Divisor(15 downto 8) when WB_ADR_I = "11" else -- Read Divisor Low
"00000000";
uart_irq_n <= not(SReg(2) or SReg(3));
end Behaviour;
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:46:10 01/30/2016
-- Design Name:
-- Module Name: /home/cmp/git/tek7854mpu/debugger/debug_hdl/testbench.vhd
-- Project Name: debug_hdl
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: toplevel
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY testbench IS
END testbench;
ARCHITECTURE behavior OF testbench IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT toplevel
PORT(
clk : IN std_logic;
led : OUT std_logic
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
--Outputs
signal led : std_logic;
-- Clock period definitions
constant clk_period : time := 20 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: toplevel PORT MAP (
clk => clk,
led => led
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
wait for 1000 ms;
-- insert stimulus here
wait;
end process;
END;
|
library verilog;
use verilog.vl_types.all;
entity finalproject_cpu_nios2_oci_pib is
port(
clk : in vl_logic;
clkx2 : in vl_logic;
jrst_n : in vl_logic;
tw : in vl_logic_vector(35 downto 0);
tr_clk : out vl_logic;
tr_data : out vl_logic_vector(17 downto 0)
);
end finalproject_cpu_nios2_oci_pib;
|
--------------------------------------------------------------------------
--
-- Copyright (C) 1993, Peter J. Ashenden
-- Mail: Dept. Computer Science
-- University of Adelaide, SA 5005, Australia
-- e-mail: [email protected]
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 1, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
--
--------------------------------------------------------------------------
--
-- $RCSfile: mux2-behaviour.vhdl,v $ $Revision: 2.1 $ $Date: 1993/11/02 19:02:04 $
--
--------------------------------------------------------------------------
--
-- Behavioural architecture of two-input multiplexor.
--
architecture behaviour of mux2 is
begin
with sel select
y <= i0 after Tpd when '0',
i1 after Tpd when '1';
end behaviour;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity processor_node is
end entity processor_node;
-- code from book
architecture dataflow of processor_node is
-- not in book
subtype word is bit_vector(31 downto 0);
type word_vector is array (natural range <>) of word;
function resolve_unique ( drivers : word_vector ) return word is
begin
if drivers'length > 0 then
return drivers(drivers'left);
else
return X"00000000";
end if;
end function resolve_unique;
-- end not in book
signal address_bus : resolve_unique word bus;
-- . . .
-- not in book
signal cache_miss, dirty, replace_section,
snoop_hit, flag_update : bit := '0';
constant tag_section0 : bit_vector(11 downto 0) := X"000";
constant tag_section1 : bit_vector(11 downto 0) := X"001";
constant set_index : bit_vector(15 downto 0) := X"6666";
constant snoop_address : word := X"88888888";
-- end not in book
begin
cache_to_address_buffer : block ( cache_miss = '1' and dirty = '1' ) is
begin
address_bus <= guarded
tag_section0 & set_index & B"0000" when replace_section = '0' else
tag_section1 & set_index & B"0000";
end block cache_to_address_buffer;
snoop_to_address_buffer : block ( snoop_hit = '1' and flag_update = '1' ) is
begin
address_bus <= guarded snoop_address(31 downto 4) & B"0000";
end block snoop_to_address_buffer;
-- . . .
-- not in book
stimulus : process is
begin
wait for 10 ns;
dirty <= '0'; cache_miss <= '1', '0' after 5 ns; wait for 10 ns;
dirty <= '1'; cache_miss <= '1', '0' after 5 ns; wait for 10 ns;
replace_section <= '1';
cache_miss <= '1', '0' after 5 ns; wait for 10 ns;
flag_update <= '0'; snoop_hit <= '1', '0' after 5 ns; wait for 10 ns;
flag_update <= '1'; snoop_hit <= '1', '0' after 5 ns; wait for 10 ns;
wait;
end process stimulus;
-- end not in book
end architecture dataflow;
-- end code from book
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity processor_node is
end entity processor_node;
-- code from book
architecture dataflow of processor_node is
-- not in book
subtype word is bit_vector(31 downto 0);
type word_vector is array (natural range <>) of word;
function resolve_unique ( drivers : word_vector ) return word is
begin
if drivers'length > 0 then
return drivers(drivers'left);
else
return X"00000000";
end if;
end function resolve_unique;
-- end not in book
signal address_bus : resolve_unique word bus;
-- . . .
-- not in book
signal cache_miss, dirty, replace_section,
snoop_hit, flag_update : bit := '0';
constant tag_section0 : bit_vector(11 downto 0) := X"000";
constant tag_section1 : bit_vector(11 downto 0) := X"001";
constant set_index : bit_vector(15 downto 0) := X"6666";
constant snoop_address : word := X"88888888";
-- end not in book
begin
cache_to_address_buffer : block ( cache_miss = '1' and dirty = '1' ) is
begin
address_bus <= guarded
tag_section0 & set_index & B"0000" when replace_section = '0' else
tag_section1 & set_index & B"0000";
end block cache_to_address_buffer;
snoop_to_address_buffer : block ( snoop_hit = '1' and flag_update = '1' ) is
begin
address_bus <= guarded snoop_address(31 downto 4) & B"0000";
end block snoop_to_address_buffer;
-- . . .
-- not in book
stimulus : process is
begin
wait for 10 ns;
dirty <= '0'; cache_miss <= '1', '0' after 5 ns; wait for 10 ns;
dirty <= '1'; cache_miss <= '1', '0' after 5 ns; wait for 10 ns;
replace_section <= '1';
cache_miss <= '1', '0' after 5 ns; wait for 10 ns;
flag_update <= '0'; snoop_hit <= '1', '0' after 5 ns; wait for 10 ns;
flag_update <= '1'; snoop_hit <= '1', '0' after 5 ns; wait for 10 ns;
wait;
end process stimulus;
-- end not in book
end architecture dataflow;
-- end code from book
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity processor_node is
end entity processor_node;
-- code from book
architecture dataflow of processor_node is
-- not in book
subtype word is bit_vector(31 downto 0);
type word_vector is array (natural range <>) of word;
function resolve_unique ( drivers : word_vector ) return word is
begin
if drivers'length > 0 then
return drivers(drivers'left);
else
return X"00000000";
end if;
end function resolve_unique;
-- end not in book
signal address_bus : resolve_unique word bus;
-- . . .
-- not in book
signal cache_miss, dirty, replace_section,
snoop_hit, flag_update : bit := '0';
constant tag_section0 : bit_vector(11 downto 0) := X"000";
constant tag_section1 : bit_vector(11 downto 0) := X"001";
constant set_index : bit_vector(15 downto 0) := X"6666";
constant snoop_address : word := X"88888888";
-- end not in book
begin
cache_to_address_buffer : block ( cache_miss = '1' and dirty = '1' ) is
begin
address_bus <= guarded
tag_section0 & set_index & B"0000" when replace_section = '0' else
tag_section1 & set_index & B"0000";
end block cache_to_address_buffer;
snoop_to_address_buffer : block ( snoop_hit = '1' and flag_update = '1' ) is
begin
address_bus <= guarded snoop_address(31 downto 4) & B"0000";
end block snoop_to_address_buffer;
-- . . .
-- not in book
stimulus : process is
begin
wait for 10 ns;
dirty <= '0'; cache_miss <= '1', '0' after 5 ns; wait for 10 ns;
dirty <= '1'; cache_miss <= '1', '0' after 5 ns; wait for 10 ns;
replace_section <= '1';
cache_miss <= '1', '0' after 5 ns; wait for 10 ns;
flag_update <= '0'; snoop_hit <= '1', '0' after 5 ns; wait for 10 ns;
flag_update <= '1'; snoop_hit <= '1', '0' after 5 ns; wait for 10 ns;
wait;
end process stimulus;
-- end not in book
end architecture dataflow;
-- end code from book
|
-- NEED RESULT: ARCH00660: Deferred constant declarations passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00660
--
-- AUTHOR:
--
-- A. Wilmot
--
-- TEST OBJECTIVES:
--
-- 4.3.1.1 (1)
--
-- DESIGN UNIT ORDERING:
--
-- PKG00660
-- PKG00660/BODY
-- E00000(ARCH00660)
-- ENT00660_Test_Bench(ARCH00660_Test_Bench)
--
-- REVISION HISTORY:
--
-- 19-AUG-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
package PKG00660 is
constant co_boolean_1 : boolean
;
constant co_bit_1 : bit
;
constant co_severity_level_1 : severity_level
;
constant co_character_1 : character
;
constant co_t_enum1_1 : t_enum1
;
constant co_st_enum1_1 : st_enum1
;
constant co_integer_1 : integer
;
constant co_t_int1_1 : t_int1
;
constant co_st_int1_1 : st_int1
;
constant co_time_1 : time
;
constant co_t_phys1_1 : t_phys1
;
constant co_st_phys1_1 : st_phys1
;
constant co_real_1 : real
;
constant co_t_real1_1 : t_real1
;
constant co_st_real1_1 : st_real1
;
end PKG00660 ;
package body PKG00660 is
constant co_boolean_1 : boolean
:= c_boolean_1 ;
constant co_bit_1 : bit
:= c_bit_1 ;
constant co_severity_level_1 : severity_level
:= c_severity_level_1 ;
constant co_character_1 : character
:= c_character_1 ;
constant co_t_enum1_1 : t_enum1
:= c_t_enum1_1 ;
constant co_st_enum1_1 : st_enum1
:= c_st_enum1_1 ;
constant co_integer_1 : integer
:= c_integer_1 ;
constant co_t_int1_1 : t_int1
:= c_t_int1_1 ;
constant co_st_int1_1 : st_int1
:= c_st_int1_1 ;
constant co_time_1 : time
:= c_time_1 ;
constant co_t_phys1_1 : t_phys1
:= c_t_phys1_1 ;
constant co_st_phys1_1 : st_phys1
:= c_st_phys1_1 ;
constant co_real_1 : real
:= c_real_1 ;
constant co_t_real1_1 : t_real1
:= c_t_real1_1 ;
constant co_st_real1_1 : st_real1
:= c_st_real1_1 ;
end PKG00660 ;
use WORK.STANDARD_TYPES.all ;
use WORK.PKG00660.all ;
architecture ARCH00660 of E00000 is
begin
process
variable correct : boolean := true ;
begin
correct := correct and co_boolean_1
= c_boolean_1 ;
correct := correct and co_bit_1
= c_bit_1 ;
correct := correct and co_severity_level_1
= c_severity_level_1 ;
correct := correct and co_character_1
= c_character_1 ;
correct := correct and co_t_enum1_1
= c_t_enum1_1 ;
correct := correct and co_st_enum1_1
= c_st_enum1_1 ;
correct := correct and co_integer_1
= c_integer_1 ;
correct := correct and co_t_int1_1
= c_t_int1_1 ;
correct := correct and co_st_int1_1
= c_st_int1_1 ;
correct := correct and co_time_1
= c_time_1 ;
correct := correct and co_t_phys1_1
= c_t_phys1_1 ;
correct := correct and co_st_phys1_1
= c_st_phys1_1 ;
correct := correct and co_real_1
= c_real_1 ;
correct := correct and co_t_real1_1
= c_t_real1_1 ;
correct := correct and co_st_real1_1
= c_st_real1_1 ;
test_report ( "ARCH00660" ,
"Deferred constant declarations" ,
correct) ;
wait ;
end process ;
end ARCH00660 ;
--
entity ENT00660_Test_Bench is
end ENT00660_Test_Bench ;
--
architecture ARCH00660_Test_Bench of ENT00660_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.E00000 ( ARCH00660 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00660_Test_Bench ;
|
library ieee;
use ieee.std_logic_1164.all;
entity hello is
generic (constant l : natural := 8);
port (a : in std_logic_vector (after downto 0));
end hello;
architecture behav of hello is
signal clk : std_logic;
signal q : std_logic_vector (l - 1 downto 0);
begin
process
begin
clk <= '0';
wait for 1 ns;
clk <= '1';
wait for 1 ns;
end process;
process (clk)
begin
if rising_edge(clk) then
q <= a;
end if;
end process;
assert false report "Hello world" severity note;
end behav;
|
--------------------------------------------------------------------------------
-- (c) Copyright 2011 - 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
-- Description:
-- This is an example testbench for the FIR Compiler IP core.
-- The testbench has been generated by Vivado to accompany the IP core
-- instance you have generated.
--
-- This testbench is for demonstration purposes only. See note below for
-- instructions on how to use it with your core.
--
-- See the FIR Compiler product guide for further information
-- about this core.
--
--------------------------------------------------------------------------------
-- Using this testbench
--
-- This testbench instantiates your generated FIR Compiler core
-- instance named "fir_lp_15kHz".
--
-- Use Vivado's Run Simulation flow to run this testbench. See the Vivado
-- documentation for details.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity tb_fir_lp_15kHz is
end tb_fir_lp_15kHz;
architecture tb of tb_fir_lp_15kHz is
-----------------------------------------------------------------------
-- Timing constants
-----------------------------------------------------------------------
constant CLOCK_PERIOD : time := 100 ns;
constant T_HOLD : time := 10 ns;
constant T_STROBE : time := CLOCK_PERIOD - (1 ns);
-----------------------------------------------------------------------
-- DUT signals
-----------------------------------------------------------------------
-- General signals
signal aclk : std_logic := '0'; -- the master clock
-- Data slave channel signals
signal s_axis_data_tvalid : std_logic := '0'; -- payload is valid
signal s_axis_data_tready : std_logic := '1'; -- slave is ready
signal s_axis_data_tdata : std_logic_vector(15 downto 0) := (others => '0'); -- data payload
-- Data master channel signals
signal m_axis_data_tvalid : std_logic := '0'; -- payload is valid
signal m_axis_data_tdata : std_logic_vector(47 downto 0) := (others => '0'); -- data payload
-----------------------------------------------------------------------
-- Aliases for AXI channel TDATA and TUSER fields
-- These are a convenience for viewing data in a simulator waveform viewer.
-- If using ModelSim or Questa, add "-voptargs=+acc=n" to the vsim command
-- to prevent the simulator optimizing away these signals.
-----------------------------------------------------------------------
-- Data slave channel alias signals
signal s_axis_data_tdata_data : std_logic_vector(15 downto 0) := (others => '0');
-- Data master channel alias signals
signal m_axis_data_tdata_data : std_logic_vector(40 downto 0) := (others => '0');
begin
-----------------------------------------------------------------------
-- Instantiate the DUT
-----------------------------------------------------------------------
dut : entity work.fir_lp_15kHz
port map (
aclk => aclk,
s_axis_data_tvalid => s_axis_data_tvalid,
s_axis_data_tready => s_axis_data_tready,
s_axis_data_tdata => s_axis_data_tdata,
m_axis_data_tvalid => m_axis_data_tvalid,
m_axis_data_tdata => m_axis_data_tdata
);
-----------------------------------------------------------------------
-- Generate clock
-----------------------------------------------------------------------
clock_gen : process
begin
aclk <= '0';
wait for CLOCK_PERIOD;
loop
aclk <= '0';
wait for CLOCK_PERIOD/2;
aclk <= '1';
wait for CLOCK_PERIOD/2;
end loop;
end process clock_gen;
-----------------------------------------------------------------------
-- Generate inputs
-----------------------------------------------------------------------
stimuli : process
-- Procedure to drive a number of input samples with specific data
-- data is the data value to drive on the tdata signal
-- samples is the number of zero-data input samples to drive
procedure drive_data ( data : std_logic_vector(15 downto 0);
samples : natural := 1 ) is
variable ip_count : integer := 0;
begin
ip_count := 0;
loop
s_axis_data_tvalid <= '1';
s_axis_data_tdata <= data;
loop
wait until rising_edge(aclk);
exit when s_axis_data_tready = '1';
end loop;
ip_count := ip_count + 1;
wait for T_HOLD;
exit when ip_count >= samples;
end loop;
end procedure drive_data;
-- Procedure to drive a number of zero-data input samples
-- samples is the number of zero-data input samples to drive
procedure drive_zeros ( samples : natural := 1 ) is
begin
drive_data((others => '0'), samples);
end procedure drive_zeros;
-- Procedure to drive an impulse and let the impulse response emerge on the data master channel
-- samples is the number of input samples to drive; default is enough for impulse response output to emerge
procedure drive_impulse ( samples : natural := 213 ) is
variable impulse : std_logic_vector(15 downto 0);
begin
impulse := (others => '0'); -- initialize unused bits to zero
impulse(15 downto 0) := "0100000000000000";
drive_data(impulse);
if samples > 1 then
drive_zeros(samples-1);
end if;
end procedure drive_impulse;
begin
-- Drive inputs T_HOLD time after rising edge of clock
wait until rising_edge(aclk);
wait for T_HOLD;
-- Drive a single impulse and let the impulse response emerge
drive_impulse;
-- Drive another impulse, during which demonstrate use and effect of AXI handshaking signals
drive_impulse(2); -- start of impulse; data is now zero
s_axis_data_tvalid <= '0';
wait for CLOCK_PERIOD * 5; -- provide no data for 5 input samples worth
drive_zeros(211); -- back to normal operation
-- End of test
report "Not a real failure. Simulation finished successfully. Test completed successfully" severity failure;
wait;
end process stimuli;
-----------------------------------------------------------------------
-- Check outputs
-----------------------------------------------------------------------
check_outputs : process
variable check_ok : boolean := true;
begin
-- Check outputs T_STROBE time after rising edge of clock
wait until rising_edge(aclk);
wait for T_STROBE;
-- Do not check the output payload values, as this requires the behavioral model
-- which would make this demonstration testbench unwieldy.
-- Instead, check the protocol of the master DATA channel:
-- check that the payload is valid (not X) when TVALID is high
if m_axis_data_tvalid = '1' then
if is_x(m_axis_data_tdata) then
report "ERROR: m_axis_data_tdata is invalid when m_axis_data_tvalid is high" severity error;
check_ok := false;
end if;
end if;
assert check_ok
report "ERROR: terminating test with failures." severity failure;
end process check_outputs;
-----------------------------------------------------------------------
-- Assign TDATA / TUSER fields to aliases, for easy simulator waveform viewing
-----------------------------------------------------------------------
-- Data slave channel alias signals
s_axis_data_tdata_data <= s_axis_data_tdata(15 downto 0);
-- Data master channel alias signals: update these only when they are valid
m_axis_data_tdata_data <= m_axis_data_tdata(40 downto 0) when m_axis_data_tvalid = '1';
end tb;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity alu is
Port ( input_a : in STD_LOGIC_VECTOR (31 downto 0);
input_b : in STD_LOGIC_VECTOR (31 downto 0);
SEL : in STD_LOGIC_VECTOR (4 downto 0);
out_alu : out STD_LOGIC_VECTOR(31 downto 0));
end alu;
architecture Behavioral of alu is
signal shift, hi, lo, mul_result, div_result, div_rem : std_logic_vector (31 downto 0);
begin
process(input_a, input_b, SEL)
begin
case SEL is
when "00000" =>
out_alu<= std_logic_vector(to_unsigned(to_integer (unsigned(input_a)) + to_integer (unsigned(input_b)), out_alu'length)) ; --ADD
when "00001" =>
out_alu<= std_logic_vector(to_unsigned(to_integer (unsigned(input_a)) - to_integer (unsigned(input_b)), out_alu'length)); --SUB
when "00010" =>
out_alu<= std_logic_vector(to_unsigned(to_integer (unsigned(input_a)) + to_integer (unsigned(input_b)), out_alu'length)) ; --ADDI
when "00011" =>
hi<= std_logic_vector(to_unsigned(to_integer (unsigned(input_a)) * to_integer (unsigned(input_b)), 64))(63 downto 32);
lo<= std_logic_vector(to_unsigned(to_integer (unsigned(input_a)) * to_integer (unsigned(input_b)), 64))(31 downto 0);
mul_result <= std_logic_vector(to_unsigned(to_integer (unsigned(input_a)) * to_integer (unsigned(input_b)), 32));
out_alu<= mul_result;
when "00100" =>
div_result <= std_logic_vector(to_unsigned(to_integer (unsigned(input_a)) / to_integer (unsigned(input_b)), div_result'length)); --DIV
div_rem <= std_logic_vector(to_unsigned(to_integer (unsigned(input_a)) mod to_integer (unsigned(input_b)), div_rem'length));
lo <= div_result;
hi <= div_rem;
out_alu <= div_result;
when "00101" =>
if (unsigned(input_a) < unsigned(input_b)) then --SLT
out_alu <= x"00000001";
else
out_alu <= x"00000000";
end if;
when "00110" =>
if (unsigned(input_a) < unsigned(input_b)) then --SLTI
out_alu <= x"00000001";
else
out_alu <= x"00000000";
end if;
when "00111" =>
out_alu<= input_a and input_b; --AND
when "01000" =>
out_alu<= input_a or input_b; --OR
when "01001" =>
out_alu<= input_a nor input_b; --NOR
when "01010" =>
out_alu<= input_a xor input_b; --XOR
when "01011" =>
out_alu<= input_a and input_b; --ANDI
when "01100" =>
out_alu<= input_a or input_b; --ORI
when "01101" =>
out_alu<= input_a xor input_b; --xORI
when "01110" => --MOVE FROM HIGH
out_alu<= hi;
when "01111" => -- MOVE FROM LOW
out_alu<= lo;
when "10000" => -- LUI
out_alu <= input_b (15 downto 0) & std_logic_vector(to_unsigned(0, 16));
when "10001" => --sll
out_alu <= input_a ((31 - to_integer(unsigned(input_b(10 downto 6)))) downto 0) & std_logic_vector(to_unsigned(0, to_integer(unsigned(input_b(10 downto 6)))));
when "10010" => --srl
out_alu <= std_logic_vector(to_unsigned(0, to_integer(unsigned(input_b(10 downto 6))))) & input_a (31 downto (0 + to_integer(unsigned(input_b(10 downto 6)))));
when "10011" => -- sra
if input_a(31) = '0' then
out_alu <= std_logic_vector(to_unsigned(0, to_integer(unsigned(input_b(10 downto 6))))) & input_a (31 downto (0 + to_integer(unsigned(input_b(10 downto 6)))));
else
out_alu <= std_logic_vector(to_unsigned(1, to_integer(unsigned(input_b(10 downto 6))))) & input_a (31 downto (0 + to_integer(unsigned(input_b(10 downto 6)))));
end if;
when "10100" => -- lw
out_alu<= std_logic_vector(to_unsigned(to_integer (unsigned(input_a)) + to_integer (unsigned(input_b)), out_alu'length)) ;
when "10101" => -- sw
out_alu<= std_logic_vector(to_unsigned(to_integer (unsigned(input_a)) + to_integer (unsigned(input_b)), out_alu'length)) ;
when "10110" => -- beq
out_alu<= std_logic_vector(to_unsigned((to_integer (unsigned(input_a)) + to_integer (unsigned(input_b)) * 4), out_alu'length));
when "10111" => -- bne
out_alu<= std_logic_vector(to_unsigned((to_integer (unsigned(input_a)) + to_integer (unsigned(input_b)) * 4), out_alu'length));
when "11000" => -- j ASSUME input b is lower 26 bits 0 padded
out_alu<= input_a(31 downto 28) & input_b(25 downto 0) & "00";
when "11001" => -- jr
out_alu <= input_a;
when "11010" => -- jal
out_alu<= input_a(31 downto 28) & input_b(25 downto 0) & "00";
when others =>
NULL;
end case;
end process;
end Behavioral; |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee; use ieee.math_real.all;
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity comp_2p2z is
generic ( gain : real := 100.0; -- high DC gain for good load regulation
fp1 : real := 7.5e3; -- pole location to achieve crossover frequency
fp2 : real := 531.0e3; -- pole location to cancel effect of ESR
fz1 : real := 403.0; -- zero locations to cancel L-C filter poles
fz2 : real := 403.0 );
port ( terminal input, output, ref : electrical );
end entity comp_2p2z;
----------------------------------------------------------------
architecture ltf of comp_2p2z is
quantity vin across input to ref;
quantity vout across iout through output to ref;
constant wp1 : real := math_2_pi * fp1; -- Pole freq (in radians)
constant wp2 : real := math_2_pi * fp2;
constant wz1 : real := math_2_pi * fz1; -- Zero freq (in radians)
constant wz2 : real := math_2_pi * fz2;
constant num : real_vector := ( 1.0,
(wz1 + wz2) / (wz1 * wz2),
1.0 / (wz1 * wz2) );
constant den : real_vector := ( 1.0e-9, 1.0,
(wp1 + wp2) / (wp1 * wp2),
1.0 / (wp1 * wp2) );
begin
vout == -1.0 * gain * vin'ltf(num, den);
end architecture ltf;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee; use ieee.math_real.all;
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity comp_2p2z is
generic ( gain : real := 100.0; -- high DC gain for good load regulation
fp1 : real := 7.5e3; -- pole location to achieve crossover frequency
fp2 : real := 531.0e3; -- pole location to cancel effect of ESR
fz1 : real := 403.0; -- zero locations to cancel L-C filter poles
fz2 : real := 403.0 );
port ( terminal input, output, ref : electrical );
end entity comp_2p2z;
----------------------------------------------------------------
architecture ltf of comp_2p2z is
quantity vin across input to ref;
quantity vout across iout through output to ref;
constant wp1 : real := math_2_pi * fp1; -- Pole freq (in radians)
constant wp2 : real := math_2_pi * fp2;
constant wz1 : real := math_2_pi * fz1; -- Zero freq (in radians)
constant wz2 : real := math_2_pi * fz2;
constant num : real_vector := ( 1.0,
(wz1 + wz2) / (wz1 * wz2),
1.0 / (wz1 * wz2) );
constant den : real_vector := ( 1.0e-9, 1.0,
(wp1 + wp2) / (wp1 * wp2),
1.0 / (wp1 * wp2) );
begin
vout == -1.0 * gain * vin'ltf(num, den);
end architecture ltf;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee; use ieee.math_real.all;
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity comp_2p2z is
generic ( gain : real := 100.0; -- high DC gain for good load regulation
fp1 : real := 7.5e3; -- pole location to achieve crossover frequency
fp2 : real := 531.0e3; -- pole location to cancel effect of ESR
fz1 : real := 403.0; -- zero locations to cancel L-C filter poles
fz2 : real := 403.0 );
port ( terminal input, output, ref : electrical );
end entity comp_2p2z;
----------------------------------------------------------------
architecture ltf of comp_2p2z is
quantity vin across input to ref;
quantity vout across iout through output to ref;
constant wp1 : real := math_2_pi * fp1; -- Pole freq (in radians)
constant wp2 : real := math_2_pi * fp2;
constant wz1 : real := math_2_pi * fz1; -- Zero freq (in radians)
constant wz2 : real := math_2_pi * fz2;
constant num : real_vector := ( 1.0,
(wz1 + wz2) / (wz1 * wz2),
1.0 / (wz1 * wz2) );
constant den : real_vector := ( 1.0e-9, 1.0,
(wp1 + wp2) / (wp1 * wp2),
1.0 / (wp1 * wp2) );
begin
vout == -1.0 * gain * vin'ltf(num, den);
end architecture ltf;
|
library ieee;
use ieee.std_logic_1164.all;
entity test_fifo is
end test_fifo;
architecture behavioural of test_fifo is
component FIFO is
generic (
addr_bits: natural
);
port (
clock : in std_logic;
push : in std_logic; -- Enable data write
pop : in std_logic; -- Enable data read if possible (push takes priority)
input : in std_logic_vector(7 downto 0); -- Data in
output : out std_logic_vector(7 downto 0); -- Data out
full : out std_logic;
empty : out std_logic
);
end component FIFO;
signal clock: std_logic;
signal push : std_logic := '0';
signal pop : std_logic := '0';
signal input : std_logic_vector(7 downto 0);
signal output : std_logic_vector(7 downto 0);
signal full : std_logic;
signal empty : std_logic;
procedure CYCLE(signal clock: out std_logic) is
begin
clock <= '0';
wait for 1 ns;
clock <= '1';
wait for 1 ns;
end procedure;
procedure PUSH_IMPL(value : in std_logic_vector(7 downto 0);
signal clock : out std_logic;
signal push : out std_logic;
signal pop : out std_logic;
signal fifo_input : out std_logic_vector(7 downto 0)) is
begin
push <= '1';
pop <= '0';
fifo_input <= value;
CYCLE(clock);
end procedure;
procedure POP_IMPL(signal clock: out std_logic;
signal push: out std_logic;
signal pop : out std_logic) is
begin
push <= '0';
pop <= '1';
CYCLE(clock);
end procedure;
begin
queue : FIFO generic map(addr_bits => 3) -- fifo with 8 elements
port map (clock, push, pop, input, output, full, empty);
process
-- Helper macros
-- PUSH wrapper
procedure PUSH_MACRO(value: in std_logic_vector(7 downto 0)) is
begin
PUSH_IMPL(value, clock, push, pop, input);
end procedure;
-- POP wrapper
procedure POP_MACRO(value: out std_logic_vector(7 downto 0)) is
begin
POP_IMPL(clock, push, pop);
value := output;
end procedure;
variable retval : std_logic_vector(7 downto 0);
begin
wait for 1 ns;
assert full = '0'
report "Fresh queue should not be full"
severity error;
assert empty = '1'
report "Fresh queue should be empty"
severity error;
PUSH_MACRO("10101010");
assert full = '0'
report "1 element queue should not be full" severity error;
assert empty = '0'
report "1 element queue should not be empty" severity error;
for i in 1 to 6 loop
CYCLE(clock);
assert full = '0'
report "queue should not be full" severity error;
assert empty = '0'
report "queue should not be empty" severity error;
end loop;
CYCLE(clock);
assert full = '1'
report "8 element queue should be full" severity error;
assert empty = '0'
report "8 element queue should not be empty" severity error;
-- Ensure queue maintains size
push <= '0';
pop <= '0';
CYCLE(clock);
assert full = '1'
report "8 element queue should be full" severity error;
assert empty = '0'
report "8 element queue should not be empty" severity error;
-- Drain queue
for i in 1 to 7 loop
POP_MACRO(retval);
assert full = '0'
report "draining queue should not be full" severity error;
assert empty = '0'
report "draining queue should not be empty" severity error;
end loop;
POP_MACRO(retval);
assert full = '0'
report "Empty queue should not be full" severity error;
assert empty = '1'
report "Empty queue should be empty" severity error;
-- Ensure queue maintains size
push <= '0';
pop <= '0';
CYCLE(clock);
assert full = '0'
report "Empty queue should not be full" severity error;
assert empty = '1'
report "Empty queue should be empty" severity error;
PUSH_MACRO("00001111");
POP_MACRO(retval);
assert retval = "00001111"
report "Returned value should match pushed value" severity error;
PUSH_MACRO("00000001");
PUSH_MACRO("00000010");
PUSH_MACRO("00000100");
PUSH_MACRO("00001000");
POP_MACRO(retval);
assert retval = "00000001"
report "FIFO Queue should maintain FIFO ordering" severity error;
POP_MACRO(retval);
assert retval = "00000010"
report "FIFO Queue should maintain FIFO ordering" severity error;
POP_MACRO(retval);
assert retval = "00000100"
report "FIFO Queue should maintain FIFO ordering" severity error;
POP_MACRO(retval);
assert retval = "00001000"
report "FIFO Queue should maintain FIFO ordering" severity error;
assert empty = '1'
report "Queue should be empty here" severity error;
PUSH_MACRO("00000001"); -- 1
PUSH_MACRO("00000010"); -- 2
PUSH_MACRO("00000100"); -- 3
PUSH_MACRO("00001000"); -- 4
PUSH_MACRO("00010000"); -- 5
PUSH_MACRO("00100000"); -- 6
PUSH_MACRO("01000000"); -- 7
PUSH_MACRO("10000000"); -- 8
assert full = '1'
report "Queue should be full here"
severity error;
PUSH_MACRO("11111111"); -- Overflow
PUSH_MACRO("11111111"); -- Overflow
assert full = '1'
report "Queue should be full after overflow"
severity error;
POP_MACRO(retval);
assert retval = "00000001"
report "FIFO Queue should maintain FIFO ordering in the presence of overflow"
severity error;
POP_MACRO(retval);
assert retval = "00000010"
report "FIFO Queue should maintain FIFO ordering in the presence of overflow"
severity error;
POP_MACRO(retval);
assert retval = "00000100"
report "FIFO Queue should maintain FIFO ordering in the presence of overflow"
severity error;
POP_MACRO(retval);
assert retval = "00001000"
report "FIFO Queue should maintain FIFO ordering in the presence of overflow"
severity error;
POP_MACRO(retval);
assert retval = "00010000"
report "FIFO Queue should maintain FIFO ordering in the presence of overflow"
severity error;
POP_MACRO(retval);
assert retval = "00100000"
report "FIFO Queue should maintain FIFO ordering in the presence of overflow"
severity error;
POP_MACRO(retval);
assert retval = "01000000"
report "FIFO Queue should maintain FIFO ordering in the presence of overflow"
severity error;
POP_MACRO(retval);
assert retval = "10000000"
report "FIFO Queue should maintain FIFO ordering in the presence of overflow"
severity error;
assert empty = '1'
report "Queue should be fully drained here"
severity error;
POP_MACRO(retval);
assert retval = "10000000" -- Just keeps repeating last read value
report "FIFO Queue should have dropped the overflow values"
severity error;
assert empty = '1'
report "Queue should remain fully drained after over-emptying"
severity error;
assert full = '0'
report "Queue should remain fully drained after over-emptying"
severity error;
PUSH_MACRO("11110000");
assert empty = '0'
report "Queue should work correctly after over-emptying"
severity error;
assert full = '0'
report "Queue should work correctly after over-emptying"
severity error;
POP_MACRO(retval);
assert retval = "11110000";
assert empty = '1'
report "Queue should become fully drained here"
severity error;
assert full = '0'
report "Queue should become fully drained here"
severity error;
wait;
end process;
end behavioural;
|
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 3.9
-- \ \ Application : MIG
-- / / Filename : memc3_wrapper.vhd
-- /___/ /\ Date Last Modified : $Date: 2011/06/02 07:16:59 $
-- \ \ / \ Date Created :
-- \___\/\___\
--
--Device : Spartan-6
--Design Name : DDR/DDR2/DDR3/LPDDR
--Purpose : This module instantiates mcb_raw_wrapper module.
--Reference :
--Revision History :
--*****************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity memc3_wrapper is
generic (
C_MEMCLK_PERIOD : integer := 2500;
C_P0_MASK_SIZE : integer := 4;
C_P0_DATA_PORT_SIZE : integer := 32;
C_P1_MASK_SIZE : integer := 4;
C_P1_DATA_PORT_SIZE : integer := 32;
C_ARB_NUM_TIME_SLOTS : integer := 12;
C_ARB_TIME_SLOT_0 : bit_vector := "000";
C_ARB_TIME_SLOT_1 : bit_vector := "000";
C_ARB_TIME_SLOT_2 : bit_vector := "000";
C_ARB_TIME_SLOT_3 : bit_vector := "000";
C_ARB_TIME_SLOT_4 : bit_vector := "000";
C_ARB_TIME_SLOT_5 : bit_vector := "000";
C_ARB_TIME_SLOT_6 : bit_vector := "000";
C_ARB_TIME_SLOT_7 : bit_vector := "000";
C_ARB_TIME_SLOT_8 : bit_vector := "000";
C_ARB_TIME_SLOT_9 : bit_vector := "000";
C_ARB_TIME_SLOT_10 : bit_vector := "000";
C_ARB_TIME_SLOT_11 : bit_vector := "000";
C_MEM_TRAS : integer := 45000;
C_MEM_TRCD : integer := 12500;
C_MEM_TREFI : integer := 7800000;
C_MEM_TRFC : integer := 127500;
C_MEM_TRP : integer := 12500;
C_MEM_TWR : integer := 15000;
C_MEM_TRTP : integer := 7500;
C_MEM_TWTR : integer := 7500;
C_MEM_ADDR_ORDER : string :="ROW_BANK_COLUMN";
C_MEM_TYPE : string :="DDR2";
C_MEM_DENSITY : string :="1Gb";
C_NUM_DQ_PINS : integer := 4;
C_MEM_BURST_LEN : integer := 8;
C_MEM_CAS_LATENCY : integer := 5;
C_MEM_ADDR_WIDTH : integer := 14;
C_MEM_BANKADDR_WIDTH : integer := 3;
C_MEM_NUM_COL_BITS : integer := 11;
C_MEM_DDR1_2_ODS : string := "FULL";
C_MEM_DDR2_RTT : string := "50OHMS";
C_MEM_DDR2_DIFF_DQS_EN : string := "YES";
C_MEM_DDR2_3_PA_SR : string := "FULL";
C_MEM_DDR2_3_HIGH_TEMP_SR : string := "NORMAL";
C_MEM_DDR3_CAS_LATENCY : integer:= 7;
C_MEM_DDR3_CAS_WR_LATENCY : integer:= 5;
C_MEM_DDR3_ODS : string := "DIV6";
C_MEM_DDR3_RTT : string := "DIV2";
C_MEM_DDR3_AUTO_SR : string := "ENABLED";
C_MEM_MOBILE_PA_SR : string := "FULL";
C_MEM_MDDR_ODS : string := "FULL";
C_MC_CALIB_BYPASS : string := "NO";
C_LDQSP_TAP_DELAY_VAL : integer := 0;
C_UDQSP_TAP_DELAY_VAL : integer := 0;
C_LDQSN_TAP_DELAY_VAL : integer := 0;
C_UDQSN_TAP_DELAY_VAL : integer := 0;
C_DQ0_TAP_DELAY_VAL : integer := 0;
C_DQ1_TAP_DELAY_VAL : integer := 0;
C_DQ2_TAP_DELAY_VAL : integer := 0;
C_DQ3_TAP_DELAY_VAL : integer := 0;
C_DQ4_TAP_DELAY_VAL : integer := 0;
C_DQ5_TAP_DELAY_VAL : integer := 0;
C_DQ6_TAP_DELAY_VAL : integer := 0;
C_DQ7_TAP_DELAY_VAL : integer := 0;
C_DQ8_TAP_DELAY_VAL : integer := 0;
C_DQ9_TAP_DELAY_VAL : integer := 0;
C_DQ10_TAP_DELAY_VAL : integer := 0;
C_DQ11_TAP_DELAY_VAL : integer := 0;
C_DQ12_TAP_DELAY_VAL : integer := 0;
C_DQ13_TAP_DELAY_VAL : integer := 0;
C_DQ14_TAP_DELAY_VAL : integer := 0;
C_DQ15_TAP_DELAY_VAL : integer := 0;
C_SKIP_IN_TERM_CAL : integer := 0;
C_SKIP_DYNAMIC_CAL : integer := 0;
C_SIMULATION : string := "FALSE";
C_MC_CALIBRATION_MODE : string := "CALIBRATION";
C_MC_CALIBRATION_DELAY : string := "QUARTER";
C_CALIB_SOFT_IP : string := "TRUE"
);
port
(
-- high-speed PLL clock interface
sysclk_2x : in std_logic;
sysclk_2x_180 : in std_logic;
pll_ce_0 : in std_logic;
pll_ce_90 : in std_logic;
pll_lock : in std_logic;
async_rst : in std_logic;
--User Port0 Interface Signals
p0_cmd_clk : in std_logic;
p0_cmd_en : in std_logic;
p0_cmd_instr : in std_logic_vector(2 downto 0) ;
p0_cmd_bl : in std_logic_vector(5 downto 0) ;
p0_cmd_byte_addr : in std_logic_vector(29 downto 0) ;
p0_cmd_empty : out std_logic;
p0_cmd_full : out std_logic;
-- Data Wr Port signals
p0_wr_clk : in std_logic;
p0_wr_en : in std_logic;
p0_wr_mask : in std_logic_vector(C_P0_MASK_SIZE - 1 downto 0) ;
p0_wr_data : in std_logic_vector(C_P0_DATA_PORT_SIZE - 1 downto 0) ;
p0_wr_full : out std_logic;
p0_wr_empty : out std_logic;
p0_wr_count : out std_logic_vector(6 downto 0) ;
p0_wr_underrun : out std_logic;
p0_wr_error : out std_logic;
--Data Rd Port signals
p0_rd_clk : in std_logic;
p0_rd_en : in std_logic;
p0_rd_data : out std_logic_vector(C_P0_DATA_PORT_SIZE - 1 downto 0) ;
p0_rd_full : out std_logic;
p0_rd_empty : out std_logic;
p0_rd_count : out std_logic_vector(6 downto 0) ;
p0_rd_overflow : out std_logic;
p0_rd_error : out std_logic;
-- memory interface signals
mcb3_dram_ck : out std_logic;
mcb3_dram_ck_n : out std_logic;
mcb3_dram_a : out std_logic_vector(C_MEM_ADDR_WIDTH-1 downto 0);
mcb3_dram_ba : out std_logic_vector(C_MEM_BANKADDR_WIDTH-1 downto 0);
mcb3_dram_ras_n : out std_logic;
mcb3_dram_cas_n : out std_logic;
mcb3_dram_we_n : out std_logic;
mcb3_dram_odt : out std_logic;
-- mcb3_dram_odt : out std_logic;
mcb3_dram_cke : out std_logic;
mcb3_dram_dq : inout std_logic_vector(C_NUM_DQ_PINS-1 downto 0);
mcb3_dram_dqs : inout std_logic;
mcb3_dram_dqs_n : inout std_logic;
mcb3_dram_reset_n : out std_logic;
mcb3_dram_udqs : inout std_logic;
mcb3_dram_udqs_n : inout std_logic;
mcb3_dram_udm : out std_logic;
mcb3_dram_dm : out std_logic;
mcb3_rzq : inout std_logic;
mcb3_zio : inout std_logic;
-- Calibration signals
mcb_drp_clk : in std_logic;
calib_done : out std_logic;
selfrefresh_enter : in std_logic;
selfrefresh_mode : out std_logic
);
end entity;
architecture acch of memc3_wrapper is
component mcb_raw_wrapper IS
GENERIC (
C_MEMCLK_PERIOD : integer;
C_PORT_ENABLE : std_logic_vector(5 downto 0);
C_MEM_ADDR_ORDER : string;
C_ARB_NUM_TIME_SLOTS : integer;
C_ARB_TIME_SLOT_0 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_1 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_2 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_3 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_4 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_5 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_6 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_7 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_8 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_9 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_10 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_11 : bit_vector(17 downto 0);
C_PORT_CONFIG : string;
C_MEM_TRAS : integer;
C_MEM_TRCD : integer;
C_MEM_TREFI : integer;
C_MEM_TRFC : integer;
C_MEM_TRP : integer;
C_MEM_TWR : integer;
C_MEM_TRTP : integer;
C_MEM_TWTR : integer;
C_NUM_DQ_PINS : integer;
C_MEM_TYPE : string;
C_MEM_DENSITY : string;
C_MEM_BURST_LEN : integer;
C_MEM_CAS_LATENCY : integer;
C_MEM_ADDR_WIDTH : integer;
C_MEM_BANKADDR_WIDTH : integer;
C_MEM_NUM_COL_BITS : integer;
C_MEM_DDR3_CAS_LATENCY : integer;
C_MEM_MOBILE_PA_SR : string;
C_MEM_DDR1_2_ODS : string;
C_MEM_DDR3_ODS : string;
C_MEM_DDR2_RTT : string;
C_MEM_DDR3_RTT : string;
C_MEM_MDDR_ODS : string;
C_MEM_DDR2_DIFF_DQS_EN : string;
C_MEM_DDR2_3_PA_SR : string;
C_MEM_DDR3_CAS_WR_LATENCY : integer;
C_MEM_DDR3_AUTO_SR : string;
C_MEM_DDR2_3_HIGH_TEMP_SR : string;
C_MEM_DDR3_DYN_WRT_ODT : string;
C_MC_CALIB_BYPASS : string;
C_MC_CALIBRATION_RA : bit_vector(15 DOWNTO 0);
C_MC_CALIBRATION_BA : bit_vector(2 DOWNTO 0);
C_CALIB_SOFT_IP : string;
C_MC_CALIBRATION_CA : bit_vector(11 DOWNTO 0);
C_MC_CALIBRATION_CLK_DIV : integer;
C_MC_CALIBRATION_MODE : string;
C_MC_CALIBRATION_DELAY : string;
LDQSP_TAP_DELAY_VAL : integer;
UDQSP_TAP_DELAY_VAL : integer;
LDQSN_TAP_DELAY_VAL : integer;
UDQSN_TAP_DELAY_VAL : integer;
DQ0_TAP_DELAY_VAL : integer;
DQ1_TAP_DELAY_VAL : integer;
DQ2_TAP_DELAY_VAL : integer;
DQ3_TAP_DELAY_VAL : integer;
DQ4_TAP_DELAY_VAL : integer;
DQ5_TAP_DELAY_VAL : integer;
DQ6_TAP_DELAY_VAL : integer;
DQ7_TAP_DELAY_VAL : integer;
DQ8_TAP_DELAY_VAL : integer;
DQ9_TAP_DELAY_VAL : integer;
DQ10_TAP_DELAY_VAL : integer;
DQ11_TAP_DELAY_VAL : integer;
DQ12_TAP_DELAY_VAL : integer;
DQ13_TAP_DELAY_VAL : integer;
DQ14_TAP_DELAY_VAL : integer;
DQ15_TAP_DELAY_VAL : integer;
C_P0_MASK_SIZE : integer;
C_P0_DATA_PORT_SIZE : integer;
C_P1_MASK_SIZE : integer;
C_P1_DATA_PORT_SIZE : integer;
C_SIMULATION : string ;
C_SKIP_IN_TERM_CAL : integer;
C_SKIP_DYNAMIC_CAL : integer;
C_SKIP_DYN_IN_TERM : integer;
C_MEM_TZQINIT_MAXCNT : std_logic_vector(9 downto 0)
);
PORT (
-- HIGH-SPEED PLL clock interface
sysclk_2x : in std_logic;
sysclk_2x_180 : in std_logic;
pll_ce_0 : in std_logic;
pll_ce_90 : in std_logic;
pll_lock : in std_logic;
sys_rst : in std_logic;
p0_arb_en : in std_logic;
p0_cmd_clk : in std_logic;
p0_cmd_en : in std_logic;
p0_cmd_instr : in std_logic_vector(2 DOWNTO 0);
p0_cmd_bl : in std_logic_vector(5 DOWNTO 0);
p0_cmd_byte_addr : in std_logic_vector(29 DOWNTO 0);
p0_cmd_empty : out std_logic;
p0_cmd_full : out std_logic;
p0_wr_clk : in std_logic;
p0_wr_en : in std_logic;
p0_wr_mask : in std_logic_vector(C_P0_MASK_SIZE - 1 DOWNTO 0);
p0_wr_data : in std_logic_vector(C_P0_DATA_PORT_SIZE - 1 DOWNTO 0);
p0_wr_full : out std_logic;
p0_wr_empty : out std_logic;
p0_wr_count : out std_logic_vector(6 DOWNTO 0);
p0_wr_underrun : out std_logic;
p0_wr_error : out std_logic;
p0_rd_clk : in std_logic;
p0_rd_en : in std_logic;
p0_rd_data : out std_logic_vector(C_P0_DATA_PORT_SIZE - 1 DOWNTO 0);
p0_rd_full : out std_logic;
p0_rd_empty : out std_logic;
p0_rd_count : out std_logic_vector(6 DOWNTO 0);
p0_rd_overflow : out std_logic;
p0_rd_error : out std_logic;
p1_arb_en : in std_logic;
p1_cmd_clk : in std_logic;
p1_cmd_en : in std_logic;
p1_cmd_instr : in std_logic_vector(2 DOWNTO 0);
p1_cmd_bl : in std_logic_vector(5 DOWNTO 0);
p1_cmd_byte_addr : in std_logic_vector(29 DOWNTO 0);
p1_cmd_empty : out std_logic;
p1_cmd_full : out std_logic;
p1_wr_clk : in std_logic;
p1_wr_en : in std_logic;
p1_wr_mask : in std_logic_vector(C_P1_MASK_SIZE - 1 DOWNTO 0);
p1_wr_data : in std_logic_vector(C_P1_DATA_PORT_SIZE - 1 DOWNTO 0);
p1_wr_full : out std_logic;
p1_wr_empty : out std_logic;
p1_wr_count : out std_logic_vector(6 DOWNTO 0);
p1_wr_underrun : out std_logic;
p1_wr_error : out std_logic;
p1_rd_clk : in std_logic;
p1_rd_en : in std_logic;
p1_rd_data : out std_logic_vector(C_P1_DATA_PORT_SIZE - 1 DOWNTO 0);
p1_rd_full : out std_logic;
p1_rd_empty : out std_logic;
p1_rd_count : out std_logic_vector(6 DOWNTO 0);
p1_rd_overflow : out std_logic;
p1_rd_error : out std_logic;
p2_arb_en : in std_logic;
p2_cmd_clk : in std_logic;
p2_cmd_en : in std_logic;
p2_cmd_instr : in std_logic_vector(2 DOWNTO 0);
p2_cmd_bl : in std_logic_vector(5 DOWNTO 0);
p2_cmd_byte_addr : in std_logic_vector(29 DOWNTO 0);
p2_cmd_empty : out std_logic;
p2_cmd_full : out std_logic;
p2_wr_clk : in std_logic;
p2_wr_en : in std_logic;
p2_wr_mask : in std_logic_vector(3 DOWNTO 0);
p2_wr_data : in std_logic_vector(31 DOWNTO 0);
p2_wr_full : out std_logic;
p2_wr_empty : out std_logic;
p2_wr_count : out std_logic_vector(6 DOWNTO 0);
p2_wr_underrun : out std_logic;
p2_wr_error : out std_logic;
p2_rd_clk : in std_logic;
p2_rd_en : in std_logic;
p2_rd_data : out std_logic_vector(31 DOWNTO 0);
p2_rd_full : out std_logic;
p2_rd_empty : out std_logic;
p2_rd_count : out std_logic_vector(6 DOWNTO 0);
p2_rd_overflow : out std_logic;
p2_rd_error : out std_logic;
p3_arb_en : in std_logic;
p3_cmd_clk : in std_logic;
p3_cmd_en : in std_logic;
p3_cmd_instr : in std_logic_vector(2 DOWNTO 0);
p3_cmd_bl : in std_logic_vector(5 DOWNTO 0);
p3_cmd_byte_addr : in std_logic_vector(29 DOWNTO 0);
p3_cmd_empty : out std_logic;
p3_cmd_full : out std_logic;
p3_wr_clk : in std_logic;
p3_wr_en : in std_logic;
p3_wr_mask : in std_logic_vector(3 DOWNTO 0);
p3_wr_data : in std_logic_vector(31 DOWNTO 0);
p3_wr_full : out std_logic;
p3_wr_empty : out std_logic;
p3_wr_count : out std_logic_vector(6 DOWNTO 0);
p3_wr_underrun : out std_logic;
p3_wr_error : out std_logic;
p3_rd_clk : in std_logic;
p3_rd_en : in std_logic;
p3_rd_data : out std_logic_vector(31 DOWNTO 0);
p3_rd_full : out std_logic;
p3_rd_empty : out std_logic;
p3_rd_count : out std_logic_vector(6 DOWNTO 0);
p3_rd_overflow : out std_logic;
p3_rd_error : out std_logic;
p4_arb_en : in std_logic;
p4_cmd_clk : in std_logic;
p4_cmd_en : in std_logic;
p4_cmd_instr : in std_logic_vector(2 DOWNTO 0);
p4_cmd_bl : in std_logic_vector(5 DOWNTO 0);
p4_cmd_byte_addr : in std_logic_vector(29 DOWNTO 0);
p4_cmd_empty : out std_logic;
p4_cmd_full : out std_logic;
p4_wr_clk : in std_logic;
p4_wr_en : in std_logic;
p4_wr_mask : in std_logic_vector(3 DOWNTO 0);
p4_wr_data : in std_logic_vector(31 DOWNTO 0);
p4_wr_full : out std_logic;
p4_wr_empty : out std_logic;
p4_wr_count : out std_logic_vector(6 DOWNTO 0);
p4_wr_underrun : out std_logic;
p4_wr_error : out std_logic;
p4_rd_clk : in std_logic;
p4_rd_en : in std_logic;
p4_rd_data : out std_logic_vector(31 DOWNTO 0);
p4_rd_full : out std_logic;
p4_rd_empty : out std_logic;
p4_rd_count : out std_logic_vector(6 DOWNTO 0);
p4_rd_overflow : out std_logic;
p4_rd_error : out std_logic;
p5_arb_en : in std_logic;
p5_cmd_clk : in std_logic;
p5_cmd_en : in std_logic;
p5_cmd_instr : in std_logic_vector(2 DOWNTO 0);
p5_cmd_bl : in std_logic_vector(5 DOWNTO 0);
p5_cmd_byte_addr : in std_logic_vector(29 DOWNTO 0);
p5_cmd_empty : out std_logic;
p5_cmd_full : out std_logic;
p5_wr_clk : in std_logic;
p5_wr_en : in std_logic;
p5_wr_mask : in std_logic_vector(3 DOWNTO 0);
p5_wr_data : in std_logic_vector(31 DOWNTO 0);
p5_wr_full : out std_logic;
p5_wr_empty : out std_logic;
p5_wr_count : out std_logic_vector(6 DOWNTO 0);
p5_wr_underrun : out std_logic;
p5_wr_error : out std_logic;
p5_rd_clk : in std_logic;
p5_rd_en : in std_logic;
p5_rd_data : out std_logic_vector(31 DOWNTO 0);
p5_rd_full : out std_logic;
p5_rd_empty : out std_logic;
p5_rd_count : out std_logic_vector(6 DOWNTO 0);
p5_rd_overflow : out std_logic;
p5_rd_error : out std_logic;
mcbx_dram_addr : out std_logic_vector(C_MEM_ADDR_WIDTH - 1 DOWNTO 0);
mcbx_dram_ba : out std_logic_vector(C_MEM_BANKADDR_WIDTH - 1 DOWNTO 0);
mcbx_dram_ras_n : out std_logic;
mcbx_dram_cas_n : out std_logic;
mcbx_dram_we_n : out std_logic;
mcbx_dram_cke : out std_logic;
mcbx_dram_clk : out std_logic;
mcbx_dram_clk_n : out std_logic;
mcbx_dram_dq : inout std_logic_vector(C_NUM_DQ_PINS-1 DOWNTO 0);
mcbx_dram_dqs : inout std_logic;
mcbx_dram_dqs_n : inout std_logic;
mcbx_dram_udqs : inout std_logic;
mcbx_dram_udqs_n : inout std_logic;
mcbx_dram_udm : out std_logic;
mcbx_dram_ldm : out std_logic;
mcbx_dram_odt : out std_logic;
mcbx_dram_ddr3_rst : out std_logic;
calib_recal : in std_logic;
rzq : inout std_logic;
zio : inout std_logic;
ui_read : in std_logic;
ui_add : in std_logic;
ui_cs : in std_logic;
ui_clk : in std_logic;
ui_sdi : in std_logic;
ui_addr : in std_logic_vector(4 DOWNTO 0);
ui_broadcast : in std_logic;
ui_drp_update : in std_logic;
ui_done_cal : in std_logic;
ui_cmd : in std_logic;
ui_cmd_in : in std_logic;
ui_cmd_en : in std_logic;
ui_dqcount : in std_logic_vector(3 DOWNTO 0);
ui_dq_lower_dec : in std_logic;
ui_dq_lower_inc : in std_logic;
ui_dq_upper_dec : in std_logic;
ui_dq_upper_inc : in std_logic;
ui_udqs_inc : in std_logic;
ui_udqs_dec : in std_logic;
ui_ldqs_inc : in std_logic;
ui_ldqs_dec : in std_logic;
uo_data : out std_logic_vector(7 DOWNTO 0);
uo_data_valid : out std_logic;
uo_done_cal : out std_logic;
uo_cmd_ready_in : out std_logic;
uo_refrsh_flag : out std_logic;
uo_cal_start : out std_logic;
uo_sdo : out std_logic;
status : out std_logic_vector(31 DOWNTO 0);
selfrefresh_enter : in std_logic;
selfrefresh_mode : out std_logic
);
end component;
signal uo_data : std_logic_vector(7 downto 0);
constant C_PORT_ENABLE : std_logic_vector(5 downto 0) := "000001";
constant C_PORT_CONFIG : string := "B32_B32_R32_R32_R32_R32";
constant ARB_TIME_SLOT_0 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_0(2 downto 0));
constant ARB_TIME_SLOT_1 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_1(2 downto 0));
constant ARB_TIME_SLOT_2 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_2(2 downto 0));
constant ARB_TIME_SLOT_3 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_3(2 downto 0));
constant ARB_TIME_SLOT_4 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_4(2 downto 0));
constant ARB_TIME_SLOT_5 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_5(2 downto 0));
constant ARB_TIME_SLOT_6 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_6(2 downto 0));
constant ARB_TIME_SLOT_7 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_7(2 downto 0));
constant ARB_TIME_SLOT_8 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_8(2 downto 0));
constant ARB_TIME_SLOT_9 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_9(2 downto 0));
constant ARB_TIME_SLOT_10 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_10(2 downto 0));
constant ARB_TIME_SLOT_11 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_11(2 downto 0));
constant C_MC_CALIBRATION_CLK_DIV : integer := 1;
constant C_MEM_TZQINIT_MAXCNT : std_logic_vector(9 downto 0) := "1000000000" + "0000010000"; -- 16 cycles are added to avoid trfc violations
constant C_SKIP_DYN_IN_TERM : integer := 1;
constant C_MC_CALIBRATION_RA : bit_vector(15 downto 0) := X"0000";
constant C_MC_CALIBRATION_BA : bit_vector(2 downto 0) := o"0";
constant C_MC_CALIBRATION_CA : bit_vector(11 downto 0) := X"000";
constant C_MEM_DDR3_DYN_WRT_ODT : string := "OFF";
signal status : std_logic_vector(31 downto 0);
signal uo_data_valid : std_logic;
signal uo_cmd_ready_in : std_logic;
signal uo_refrsh_flag : std_logic;
signal uo_cal_start : std_logic;
signal uo_sdo : std_logic;
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of acch : architecture IS
"mig_v3_9_ddr3_s6, Coregen 13.3";
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of acch : architecture IS "mcb3_ddr3_s6,mig_v3_9,{LANGUAGE=VHDL, SYNTHESIS_TOOL=ISE, NO_OF_CONTROLLERS=2, AXI_ENABLE=0, MEM_INTERFACE_TYPE=DDR3_SDRAM, CLK_PERIOD=2500, MEMORY_PART=mt41j128m16xx-15e, MEMORY_DEVICE_WIDTH=16, OUTPUT_DRV=DIV6, RTT_NOM=DIV4, AUTO_SR=ENABLED, HIGH_TEMP_SR=NORMAL, PORT_CONFIG=Two 32-bit bi-directional and four 32-bit unidirectional ports, MEM_ADDR_ORDER=ROW_BANK_COLUMN, PORT_ENABLE=Port0, INPUT_PIN_TERMINATION=CALIB_TERM, DATA_TERMINATION=25 Ohms, CLKFBOUT_MULT_F=2, CLKOUT_DIVIDE=1, DEBUG_PORT=0, INPUT_CLK_TYPE=Differential}";
begin
memc3_mcb_raw_wrapper_inst : mcb_raw_wrapper
generic map
(
C_MEMCLK_PERIOD => C_MEMCLK_PERIOD,
C_P0_MASK_SIZE => C_P0_MASK_SIZE,
C_P0_DATA_PORT_SIZE => C_P0_DATA_PORT_SIZE,
C_P1_MASK_SIZE => C_P1_MASK_SIZE,
C_P1_DATA_PORT_SIZE => C_P1_DATA_PORT_SIZE,
C_ARB_NUM_TIME_SLOTS => C_ARB_NUM_TIME_SLOTS,
C_ARB_TIME_SLOT_0 => ARB_TIME_SLOT_0,
C_ARB_TIME_SLOT_1 => ARB_TIME_SLOT_1,
C_ARB_TIME_SLOT_2 => ARB_TIME_SLOT_2,
C_ARB_TIME_SLOT_3 => ARB_TIME_SLOT_3,
C_ARB_TIME_SLOT_4 => ARB_TIME_SLOT_4,
C_ARB_TIME_SLOT_5 => ARB_TIME_SLOT_5,
C_ARB_TIME_SLOT_6 => ARB_TIME_SLOT_6,
C_ARB_TIME_SLOT_7 => ARB_TIME_SLOT_7,
C_ARB_TIME_SLOT_8 => ARB_TIME_SLOT_8,
C_ARB_TIME_SLOT_9 => ARB_TIME_SLOT_9,
C_ARB_TIME_SLOT_10 => ARB_TIME_SLOT_10,
C_ARB_TIME_SLOT_11 => ARB_TIME_SLOT_11,
C_PORT_CONFIG => C_PORT_CONFIG,
C_PORT_ENABLE => C_PORT_ENABLE,
C_MEM_TRAS => C_MEM_TRAS,
C_MEM_TRCD => C_MEM_TRCD,
C_MEM_TREFI => C_MEM_TREFI,
C_MEM_TRFC => C_MEM_TRFC,
C_MEM_TRP => C_MEM_TRP,
C_MEM_TWR => C_MEM_TWR,
C_MEM_TRTP => C_MEM_TRTP,
C_MEM_TWTR => C_MEM_TWTR,
C_MEM_ADDR_ORDER => C_MEM_ADDR_ORDER,
C_NUM_DQ_PINS => C_NUM_DQ_PINS,
C_MEM_TYPE => C_MEM_TYPE,
C_MEM_DENSITY => C_MEM_DENSITY,
C_MEM_BURST_LEN => C_MEM_BURST_LEN,
C_MEM_CAS_LATENCY => C_MEM_CAS_LATENCY,
C_MEM_ADDR_WIDTH => C_MEM_ADDR_WIDTH,
C_MEM_BANKADDR_WIDTH => C_MEM_BANKADDR_WIDTH,
C_MEM_NUM_COL_BITS => C_MEM_NUM_COL_BITS,
C_MEM_DDR1_2_ODS => C_MEM_DDR1_2_ODS,
C_MEM_DDR2_RTT => C_MEM_DDR2_RTT,
C_MEM_DDR2_DIFF_DQS_EN => C_MEM_DDR2_DIFF_DQS_EN,
C_MEM_DDR2_3_PA_SR => C_MEM_DDR2_3_PA_SR,
C_MEM_DDR2_3_HIGH_TEMP_SR => C_MEM_DDR2_3_HIGH_TEMP_SR,
C_MEM_DDR3_CAS_LATENCY => C_MEM_DDR3_CAS_LATENCY,
C_MEM_DDR3_ODS => C_MEM_DDR3_ODS,
C_MEM_DDR3_RTT => C_MEM_DDR3_RTT,
C_MEM_DDR3_CAS_WR_LATENCY => C_MEM_DDR3_CAS_WR_LATENCY,
C_MEM_DDR3_AUTO_SR => C_MEM_DDR3_AUTO_SR,
C_MEM_DDR3_DYN_WRT_ODT => C_MEM_DDR3_DYN_WRT_ODT,
C_MEM_MOBILE_PA_SR => C_MEM_MOBILE_PA_SR,
C_MEM_MDDR_ODS => C_MEM_MDDR_ODS,
C_MC_CALIBRATION_CLK_DIV => C_MC_CALIBRATION_CLK_DIV,
C_MC_CALIBRATION_MODE => C_MC_CALIBRATION_MODE,
C_MC_CALIBRATION_DELAY => C_MC_CALIBRATION_DELAY,
C_MC_CALIB_BYPASS => C_MC_CALIB_BYPASS,
C_MC_CALIBRATION_RA => C_MC_CALIBRATION_RA,
C_MC_CALIBRATION_BA => C_MC_CALIBRATION_BA,
C_MC_CALIBRATION_CA => C_MC_CALIBRATION_CA,
C_CALIB_SOFT_IP => C_CALIB_SOFT_IP,
C_SIMULATION => C_SIMULATION,
C_SKIP_IN_TERM_CAL => C_SKIP_IN_TERM_CAL,
C_SKIP_DYNAMIC_CAL => C_SKIP_DYNAMIC_CAL,
C_SKIP_DYN_IN_TERM => C_SKIP_DYN_IN_TERM,
C_MEM_TZQINIT_MAXCNT => C_MEM_TZQINIT_MAXCNT,
LDQSP_TAP_DELAY_VAL => C_LDQSP_TAP_DELAY_VAL,
UDQSP_TAP_DELAY_VAL => C_UDQSP_TAP_DELAY_VAL,
LDQSN_TAP_DELAY_VAL => C_LDQSN_TAP_DELAY_VAL,
UDQSN_TAP_DELAY_VAL => C_UDQSN_TAP_DELAY_VAL,
DQ0_TAP_DELAY_VAL => C_DQ0_TAP_DELAY_VAL,
DQ1_TAP_DELAY_VAL => C_DQ1_TAP_DELAY_VAL,
DQ2_TAP_DELAY_VAL => C_DQ2_TAP_DELAY_VAL,
DQ3_TAP_DELAY_VAL => C_DQ3_TAP_DELAY_VAL,
DQ4_TAP_DELAY_VAL => C_DQ4_TAP_DELAY_VAL,
DQ5_TAP_DELAY_VAL => C_DQ5_TAP_DELAY_VAL,
DQ6_TAP_DELAY_VAL => C_DQ6_TAP_DELAY_VAL,
DQ7_TAP_DELAY_VAL => C_DQ7_TAP_DELAY_VAL,
DQ8_TAP_DELAY_VAL => C_DQ8_TAP_DELAY_VAL,
DQ9_TAP_DELAY_VAL => C_DQ9_TAP_DELAY_VAL,
DQ10_TAP_DELAY_VAL => C_DQ10_TAP_DELAY_VAL,
DQ11_TAP_DELAY_VAL => C_DQ11_TAP_DELAY_VAL,
DQ12_TAP_DELAY_VAL => C_DQ12_TAP_DELAY_VAL,
DQ13_TAP_DELAY_VAL => C_DQ13_TAP_DELAY_VAL,
DQ14_TAP_DELAY_VAL => C_DQ14_TAP_DELAY_VAL,
DQ15_TAP_DELAY_VAL => C_DQ15_TAP_DELAY_VAL
)
port map
(
sys_rst => async_rst,
sysclk_2x => sysclk_2x,
sysclk_2x_180 => sysclk_2x_180,
pll_ce_0 => pll_ce_0,
pll_ce_90 => pll_ce_90,
pll_lock => pll_lock,
mcbx_dram_addr => mcb3_dram_a,
mcbx_dram_ba => mcb3_dram_ba,
mcbx_dram_ras_n => mcb3_dram_ras_n,
mcbx_dram_cas_n => mcb3_dram_cas_n,
mcbx_dram_we_n => mcb3_dram_we_n,
mcbx_dram_cke => mcb3_dram_cke,
mcbx_dram_clk => mcb3_dram_ck,
mcbx_dram_clk_n => mcb3_dram_ck_n,
mcbx_dram_dq => mcb3_dram_dq,
mcbx_dram_odt => mcb3_dram_odt,
mcbx_dram_ldm => mcb3_dram_dm,
mcbx_dram_udm => mcb3_dram_udm,
mcbx_dram_dqs => mcb3_dram_dqs,
mcbx_dram_dqs_n => mcb3_dram_dqs_n,
mcbx_dram_udqs => mcb3_dram_udqs,
mcbx_dram_udqs_n => mcb3_dram_udqs_n,
mcbx_dram_ddr3_rst => mcb3_dram_reset_n,
calib_recal => '0',
rzq => mcb3_rzq,
zio => mcb3_zio,
ui_read => '0',
ui_add => '0',
ui_cs => '0',
ui_clk => mcb_drp_clk,
ui_sdi => '0',
ui_addr => (others => '0'),
ui_broadcast => '0',
ui_drp_update => '0',
ui_done_cal => '1',
ui_cmd => '0',
ui_cmd_in => '0',
ui_cmd_en => '0',
ui_dqcount => (others => '0'),
ui_dq_lower_dec => '0',
ui_dq_lower_inc => '0',
ui_dq_upper_dec => '0',
ui_dq_upper_inc => '0',
ui_udqs_inc => '0',
ui_udqs_dec => '0',
ui_ldqs_inc => '0',
ui_ldqs_dec => '0',
uo_data => uo_data,
uo_data_valid => uo_data_valid,
uo_done_cal => calib_done,
uo_cmd_ready_in => uo_cmd_ready_in,
uo_refrsh_flag => uo_refrsh_flag,
uo_cal_start => uo_cal_start,
uo_sdo => uo_sdo,
status => status,
selfrefresh_enter => '0',
selfrefresh_mode => selfrefresh_mode,
p0_arb_en => '1',
p0_cmd_clk => p0_cmd_clk,
p0_cmd_en => p0_cmd_en,
p0_cmd_instr => p0_cmd_instr,
p0_cmd_bl => p0_cmd_bl,
p0_cmd_byte_addr => p0_cmd_byte_addr,
p0_cmd_empty => p0_cmd_empty,
p0_cmd_full => p0_cmd_full,
p0_wr_clk => p0_wr_clk,
p0_wr_en => p0_wr_en,
p0_wr_mask => p0_wr_mask,
p0_wr_data => p0_wr_data,
p0_wr_full => p0_wr_full,
p0_wr_empty => p0_wr_empty,
p0_wr_count => p0_wr_count,
p0_wr_underrun => p0_wr_underrun,
p0_wr_error => p0_wr_error,
p0_rd_clk => p0_rd_clk,
p0_rd_en => p0_rd_en,
p0_rd_data => p0_rd_data,
p0_rd_full => p0_rd_full,
p0_rd_empty => p0_rd_empty,
p0_rd_count => p0_rd_count,
p0_rd_overflow => p0_rd_overflow,
p0_rd_error => p0_rd_error,
p1_arb_en => '0',
p1_cmd_clk => '0',
p1_cmd_en => '0',
p1_cmd_instr => (others => '0'),
p1_cmd_bl => (others => '0'),
p1_cmd_byte_addr => (others => '0'),
p1_cmd_empty => open,
p1_cmd_full => open,
p1_rd_clk => '0',
p1_rd_en => '0',
p1_rd_data => open,
p1_rd_full => open,
p1_rd_empty => open,
p1_rd_count => open,
p1_rd_overflow => open,
p1_rd_error => open,
p1_wr_clk => '0',
p1_wr_en => '0',
p1_wr_mask => (others => '0'),
p1_wr_data => (others => '0'),
p1_wr_full => open,
p1_wr_empty => open,
p1_wr_count => open,
p1_wr_underrun => open,
p1_wr_error => open,
p2_arb_en => '0',
p2_cmd_clk => '0',
p2_cmd_en => '0',
p2_cmd_instr => (others => '0'),
p2_cmd_bl => (others => '0'),
p2_cmd_byte_addr => (others => '0'),
p2_cmd_empty => open,
p2_cmd_full => open,
p2_rd_clk => '0',
p2_rd_en => '0',
p2_rd_data => open,
p2_rd_full => open,
p2_rd_empty => open,
p2_rd_count => open,
p2_rd_overflow => open,
p2_rd_error => open,
p2_wr_clk => '0',
p2_wr_en => '0',
p2_wr_mask => (others => '0'),
p2_wr_data => (others => '0'),
p2_wr_full => open,
p2_wr_empty => open,
p2_wr_count => open,
p2_wr_underrun => open,
p2_wr_error => open,
p3_arb_en => '0',
p3_cmd_clk => '0',
p3_cmd_en => '0',
p3_cmd_instr => (others => '0'),
p3_cmd_bl => (others => '0'),
p3_cmd_byte_addr => (others => '0'),
p3_cmd_empty => open,
p3_cmd_full => open,
p3_rd_clk => '0',
p3_rd_en => '0',
p3_rd_data => open,
p3_rd_full => open,
p3_rd_empty => open,
p3_rd_count => open,
p3_rd_overflow => open,
p3_rd_error => open,
p3_wr_clk => '0',
p3_wr_en => '0',
p3_wr_mask => (others => '0'),
p3_wr_data => (others => '0'),
p3_wr_full => open,
p3_wr_empty => open,
p3_wr_count => open,
p3_wr_underrun => open,
p3_wr_error => open,
p4_arb_en => '0',
p4_cmd_clk => '0',
p4_cmd_en => '0',
p4_cmd_instr => (others => '0'),
p4_cmd_bl => (others => '0'),
p4_cmd_byte_addr => (others => '0'),
p4_cmd_empty => open,
p4_cmd_full => open,
p4_rd_clk => '0',
p4_rd_en => '0',
p4_rd_data => open,
p4_rd_full => open,
p4_rd_empty => open,
p4_rd_count => open,
p4_rd_overflow => open,
p4_rd_error => open,
p4_wr_clk => '0',
p4_wr_en => '0',
p4_wr_mask => (others => '0'),
p4_wr_data => (others => '0'),
p4_wr_full => open,
p4_wr_empty => open,
p4_wr_count => open,
p4_wr_underrun => open,
p4_wr_error => open,
p5_arb_en => '0',
p5_cmd_clk => '0',
p5_cmd_en => '0',
p5_cmd_instr => (others => '0'),
p5_cmd_bl => (others => '0'),
p5_cmd_byte_addr => (others => '0'),
p5_cmd_empty => open,
p5_cmd_full => open,
p5_rd_clk => '0',
p5_rd_en => '0',
p5_rd_data => open,
p5_rd_full => open,
p5_rd_empty => open,
p5_rd_count => open,
p5_rd_overflow => open,
p5_rd_error => open,
p5_wr_clk => '0',
p5_wr_en => '0',
p5_wr_mask => (others => '0'),
p5_wr_data => (others => '0'),
p5_wr_full => open,
p5_wr_empty => open,
p5_wr_count => open,
p5_wr_underrun => open,
p5_wr_error => open
);
end architecture;
|
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 3.9
-- \ \ Application : MIG
-- / / Filename : memc3_wrapper.vhd
-- /___/ /\ Date Last Modified : $Date: 2011/06/02 07:16:59 $
-- \ \ / \ Date Created :
-- \___\/\___\
--
--Device : Spartan-6
--Design Name : DDR/DDR2/DDR3/LPDDR
--Purpose : This module instantiates mcb_raw_wrapper module.
--Reference :
--Revision History :
--*****************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity memc3_wrapper is
generic (
C_MEMCLK_PERIOD : integer := 2500;
C_P0_MASK_SIZE : integer := 4;
C_P0_DATA_PORT_SIZE : integer := 32;
C_P1_MASK_SIZE : integer := 4;
C_P1_DATA_PORT_SIZE : integer := 32;
C_ARB_NUM_TIME_SLOTS : integer := 12;
C_ARB_TIME_SLOT_0 : bit_vector := "000";
C_ARB_TIME_SLOT_1 : bit_vector := "000";
C_ARB_TIME_SLOT_2 : bit_vector := "000";
C_ARB_TIME_SLOT_3 : bit_vector := "000";
C_ARB_TIME_SLOT_4 : bit_vector := "000";
C_ARB_TIME_SLOT_5 : bit_vector := "000";
C_ARB_TIME_SLOT_6 : bit_vector := "000";
C_ARB_TIME_SLOT_7 : bit_vector := "000";
C_ARB_TIME_SLOT_8 : bit_vector := "000";
C_ARB_TIME_SLOT_9 : bit_vector := "000";
C_ARB_TIME_SLOT_10 : bit_vector := "000";
C_ARB_TIME_SLOT_11 : bit_vector := "000";
C_MEM_TRAS : integer := 45000;
C_MEM_TRCD : integer := 12500;
C_MEM_TREFI : integer := 7800000;
C_MEM_TRFC : integer := 127500;
C_MEM_TRP : integer := 12500;
C_MEM_TWR : integer := 15000;
C_MEM_TRTP : integer := 7500;
C_MEM_TWTR : integer := 7500;
C_MEM_ADDR_ORDER : string :="ROW_BANK_COLUMN";
C_MEM_TYPE : string :="DDR2";
C_MEM_DENSITY : string :="1Gb";
C_NUM_DQ_PINS : integer := 4;
C_MEM_BURST_LEN : integer := 8;
C_MEM_CAS_LATENCY : integer := 5;
C_MEM_ADDR_WIDTH : integer := 14;
C_MEM_BANKADDR_WIDTH : integer := 3;
C_MEM_NUM_COL_BITS : integer := 11;
C_MEM_DDR1_2_ODS : string := "FULL";
C_MEM_DDR2_RTT : string := "50OHMS";
C_MEM_DDR2_DIFF_DQS_EN : string := "YES";
C_MEM_DDR2_3_PA_SR : string := "FULL";
C_MEM_DDR2_3_HIGH_TEMP_SR : string := "NORMAL";
C_MEM_DDR3_CAS_LATENCY : integer:= 7;
C_MEM_DDR3_CAS_WR_LATENCY : integer:= 5;
C_MEM_DDR3_ODS : string := "DIV6";
C_MEM_DDR3_RTT : string := "DIV2";
C_MEM_DDR3_AUTO_SR : string := "ENABLED";
C_MEM_MOBILE_PA_SR : string := "FULL";
C_MEM_MDDR_ODS : string := "FULL";
C_MC_CALIB_BYPASS : string := "NO";
C_LDQSP_TAP_DELAY_VAL : integer := 0;
C_UDQSP_TAP_DELAY_VAL : integer := 0;
C_LDQSN_TAP_DELAY_VAL : integer := 0;
C_UDQSN_TAP_DELAY_VAL : integer := 0;
C_DQ0_TAP_DELAY_VAL : integer := 0;
C_DQ1_TAP_DELAY_VAL : integer := 0;
C_DQ2_TAP_DELAY_VAL : integer := 0;
C_DQ3_TAP_DELAY_VAL : integer := 0;
C_DQ4_TAP_DELAY_VAL : integer := 0;
C_DQ5_TAP_DELAY_VAL : integer := 0;
C_DQ6_TAP_DELAY_VAL : integer := 0;
C_DQ7_TAP_DELAY_VAL : integer := 0;
C_DQ8_TAP_DELAY_VAL : integer := 0;
C_DQ9_TAP_DELAY_VAL : integer := 0;
C_DQ10_TAP_DELAY_VAL : integer := 0;
C_DQ11_TAP_DELAY_VAL : integer := 0;
C_DQ12_TAP_DELAY_VAL : integer := 0;
C_DQ13_TAP_DELAY_VAL : integer := 0;
C_DQ14_TAP_DELAY_VAL : integer := 0;
C_DQ15_TAP_DELAY_VAL : integer := 0;
C_SKIP_IN_TERM_CAL : integer := 0;
C_SKIP_DYNAMIC_CAL : integer := 0;
C_SIMULATION : string := "FALSE";
C_MC_CALIBRATION_MODE : string := "CALIBRATION";
C_MC_CALIBRATION_DELAY : string := "QUARTER";
C_CALIB_SOFT_IP : string := "TRUE"
);
port
(
-- high-speed PLL clock interface
sysclk_2x : in std_logic;
sysclk_2x_180 : in std_logic;
pll_ce_0 : in std_logic;
pll_ce_90 : in std_logic;
pll_lock : in std_logic;
async_rst : in std_logic;
--User Port0 Interface Signals
p0_cmd_clk : in std_logic;
p0_cmd_en : in std_logic;
p0_cmd_instr : in std_logic_vector(2 downto 0) ;
p0_cmd_bl : in std_logic_vector(5 downto 0) ;
p0_cmd_byte_addr : in std_logic_vector(29 downto 0) ;
p0_cmd_empty : out std_logic;
p0_cmd_full : out std_logic;
-- Data Wr Port signals
p0_wr_clk : in std_logic;
p0_wr_en : in std_logic;
p0_wr_mask : in std_logic_vector(C_P0_MASK_SIZE - 1 downto 0) ;
p0_wr_data : in std_logic_vector(C_P0_DATA_PORT_SIZE - 1 downto 0) ;
p0_wr_full : out std_logic;
p0_wr_empty : out std_logic;
p0_wr_count : out std_logic_vector(6 downto 0) ;
p0_wr_underrun : out std_logic;
p0_wr_error : out std_logic;
--Data Rd Port signals
p0_rd_clk : in std_logic;
p0_rd_en : in std_logic;
p0_rd_data : out std_logic_vector(C_P0_DATA_PORT_SIZE - 1 downto 0) ;
p0_rd_full : out std_logic;
p0_rd_empty : out std_logic;
p0_rd_count : out std_logic_vector(6 downto 0) ;
p0_rd_overflow : out std_logic;
p0_rd_error : out std_logic;
-- memory interface signals
mcb3_dram_ck : out std_logic;
mcb3_dram_ck_n : out std_logic;
mcb3_dram_a : out std_logic_vector(C_MEM_ADDR_WIDTH-1 downto 0);
mcb3_dram_ba : out std_logic_vector(C_MEM_BANKADDR_WIDTH-1 downto 0);
mcb3_dram_ras_n : out std_logic;
mcb3_dram_cas_n : out std_logic;
mcb3_dram_we_n : out std_logic;
mcb3_dram_odt : out std_logic;
-- mcb3_dram_odt : out std_logic;
mcb3_dram_cke : out std_logic;
mcb3_dram_dq : inout std_logic_vector(C_NUM_DQ_PINS-1 downto 0);
mcb3_dram_dqs : inout std_logic;
mcb3_dram_dqs_n : inout std_logic;
mcb3_dram_reset_n : out std_logic;
mcb3_dram_udqs : inout std_logic;
mcb3_dram_udqs_n : inout std_logic;
mcb3_dram_udm : out std_logic;
mcb3_dram_dm : out std_logic;
mcb3_rzq : inout std_logic;
mcb3_zio : inout std_logic;
-- Calibration signals
mcb_drp_clk : in std_logic;
calib_done : out std_logic;
selfrefresh_enter : in std_logic;
selfrefresh_mode : out std_logic
);
end entity;
architecture acch of memc3_wrapper is
component mcb_raw_wrapper IS
GENERIC (
C_MEMCLK_PERIOD : integer;
C_PORT_ENABLE : std_logic_vector(5 downto 0);
C_MEM_ADDR_ORDER : string;
C_ARB_NUM_TIME_SLOTS : integer;
C_ARB_TIME_SLOT_0 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_1 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_2 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_3 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_4 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_5 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_6 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_7 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_8 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_9 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_10 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_11 : bit_vector(17 downto 0);
C_PORT_CONFIG : string;
C_MEM_TRAS : integer;
C_MEM_TRCD : integer;
C_MEM_TREFI : integer;
C_MEM_TRFC : integer;
C_MEM_TRP : integer;
C_MEM_TWR : integer;
C_MEM_TRTP : integer;
C_MEM_TWTR : integer;
C_NUM_DQ_PINS : integer;
C_MEM_TYPE : string;
C_MEM_DENSITY : string;
C_MEM_BURST_LEN : integer;
C_MEM_CAS_LATENCY : integer;
C_MEM_ADDR_WIDTH : integer;
C_MEM_BANKADDR_WIDTH : integer;
C_MEM_NUM_COL_BITS : integer;
C_MEM_DDR3_CAS_LATENCY : integer;
C_MEM_MOBILE_PA_SR : string;
C_MEM_DDR1_2_ODS : string;
C_MEM_DDR3_ODS : string;
C_MEM_DDR2_RTT : string;
C_MEM_DDR3_RTT : string;
C_MEM_MDDR_ODS : string;
C_MEM_DDR2_DIFF_DQS_EN : string;
C_MEM_DDR2_3_PA_SR : string;
C_MEM_DDR3_CAS_WR_LATENCY : integer;
C_MEM_DDR3_AUTO_SR : string;
C_MEM_DDR2_3_HIGH_TEMP_SR : string;
C_MEM_DDR3_DYN_WRT_ODT : string;
C_MC_CALIB_BYPASS : string;
C_MC_CALIBRATION_RA : bit_vector(15 DOWNTO 0);
C_MC_CALIBRATION_BA : bit_vector(2 DOWNTO 0);
C_CALIB_SOFT_IP : string;
C_MC_CALIBRATION_CA : bit_vector(11 DOWNTO 0);
C_MC_CALIBRATION_CLK_DIV : integer;
C_MC_CALIBRATION_MODE : string;
C_MC_CALIBRATION_DELAY : string;
LDQSP_TAP_DELAY_VAL : integer;
UDQSP_TAP_DELAY_VAL : integer;
LDQSN_TAP_DELAY_VAL : integer;
UDQSN_TAP_DELAY_VAL : integer;
DQ0_TAP_DELAY_VAL : integer;
DQ1_TAP_DELAY_VAL : integer;
DQ2_TAP_DELAY_VAL : integer;
DQ3_TAP_DELAY_VAL : integer;
DQ4_TAP_DELAY_VAL : integer;
DQ5_TAP_DELAY_VAL : integer;
DQ6_TAP_DELAY_VAL : integer;
DQ7_TAP_DELAY_VAL : integer;
DQ8_TAP_DELAY_VAL : integer;
DQ9_TAP_DELAY_VAL : integer;
DQ10_TAP_DELAY_VAL : integer;
DQ11_TAP_DELAY_VAL : integer;
DQ12_TAP_DELAY_VAL : integer;
DQ13_TAP_DELAY_VAL : integer;
DQ14_TAP_DELAY_VAL : integer;
DQ15_TAP_DELAY_VAL : integer;
C_P0_MASK_SIZE : integer;
C_P0_DATA_PORT_SIZE : integer;
C_P1_MASK_SIZE : integer;
C_P1_DATA_PORT_SIZE : integer;
C_SIMULATION : string ;
C_SKIP_IN_TERM_CAL : integer;
C_SKIP_DYNAMIC_CAL : integer;
C_SKIP_DYN_IN_TERM : integer;
C_MEM_TZQINIT_MAXCNT : std_logic_vector(9 downto 0)
);
PORT (
-- HIGH-SPEED PLL clock interface
sysclk_2x : in std_logic;
sysclk_2x_180 : in std_logic;
pll_ce_0 : in std_logic;
pll_ce_90 : in std_logic;
pll_lock : in std_logic;
sys_rst : in std_logic;
p0_arb_en : in std_logic;
p0_cmd_clk : in std_logic;
p0_cmd_en : in std_logic;
p0_cmd_instr : in std_logic_vector(2 DOWNTO 0);
p0_cmd_bl : in std_logic_vector(5 DOWNTO 0);
p0_cmd_byte_addr : in std_logic_vector(29 DOWNTO 0);
p0_cmd_empty : out std_logic;
p0_cmd_full : out std_logic;
p0_wr_clk : in std_logic;
p0_wr_en : in std_logic;
p0_wr_mask : in std_logic_vector(C_P0_MASK_SIZE - 1 DOWNTO 0);
p0_wr_data : in std_logic_vector(C_P0_DATA_PORT_SIZE - 1 DOWNTO 0);
p0_wr_full : out std_logic;
p0_wr_empty : out std_logic;
p0_wr_count : out std_logic_vector(6 DOWNTO 0);
p0_wr_underrun : out std_logic;
p0_wr_error : out std_logic;
p0_rd_clk : in std_logic;
p0_rd_en : in std_logic;
p0_rd_data : out std_logic_vector(C_P0_DATA_PORT_SIZE - 1 DOWNTO 0);
p0_rd_full : out std_logic;
p0_rd_empty : out std_logic;
p0_rd_count : out std_logic_vector(6 DOWNTO 0);
p0_rd_overflow : out std_logic;
p0_rd_error : out std_logic;
p1_arb_en : in std_logic;
p1_cmd_clk : in std_logic;
p1_cmd_en : in std_logic;
p1_cmd_instr : in std_logic_vector(2 DOWNTO 0);
p1_cmd_bl : in std_logic_vector(5 DOWNTO 0);
p1_cmd_byte_addr : in std_logic_vector(29 DOWNTO 0);
p1_cmd_empty : out std_logic;
p1_cmd_full : out std_logic;
p1_wr_clk : in std_logic;
p1_wr_en : in std_logic;
p1_wr_mask : in std_logic_vector(C_P1_MASK_SIZE - 1 DOWNTO 0);
p1_wr_data : in std_logic_vector(C_P1_DATA_PORT_SIZE - 1 DOWNTO 0);
p1_wr_full : out std_logic;
p1_wr_empty : out std_logic;
p1_wr_count : out std_logic_vector(6 DOWNTO 0);
p1_wr_underrun : out std_logic;
p1_wr_error : out std_logic;
p1_rd_clk : in std_logic;
p1_rd_en : in std_logic;
p1_rd_data : out std_logic_vector(C_P1_DATA_PORT_SIZE - 1 DOWNTO 0);
p1_rd_full : out std_logic;
p1_rd_empty : out std_logic;
p1_rd_count : out std_logic_vector(6 DOWNTO 0);
p1_rd_overflow : out std_logic;
p1_rd_error : out std_logic;
p2_arb_en : in std_logic;
p2_cmd_clk : in std_logic;
p2_cmd_en : in std_logic;
p2_cmd_instr : in std_logic_vector(2 DOWNTO 0);
p2_cmd_bl : in std_logic_vector(5 DOWNTO 0);
p2_cmd_byte_addr : in std_logic_vector(29 DOWNTO 0);
p2_cmd_empty : out std_logic;
p2_cmd_full : out std_logic;
p2_wr_clk : in std_logic;
p2_wr_en : in std_logic;
p2_wr_mask : in std_logic_vector(3 DOWNTO 0);
p2_wr_data : in std_logic_vector(31 DOWNTO 0);
p2_wr_full : out std_logic;
p2_wr_empty : out std_logic;
p2_wr_count : out std_logic_vector(6 DOWNTO 0);
p2_wr_underrun : out std_logic;
p2_wr_error : out std_logic;
p2_rd_clk : in std_logic;
p2_rd_en : in std_logic;
p2_rd_data : out std_logic_vector(31 DOWNTO 0);
p2_rd_full : out std_logic;
p2_rd_empty : out std_logic;
p2_rd_count : out std_logic_vector(6 DOWNTO 0);
p2_rd_overflow : out std_logic;
p2_rd_error : out std_logic;
p3_arb_en : in std_logic;
p3_cmd_clk : in std_logic;
p3_cmd_en : in std_logic;
p3_cmd_instr : in std_logic_vector(2 DOWNTO 0);
p3_cmd_bl : in std_logic_vector(5 DOWNTO 0);
p3_cmd_byte_addr : in std_logic_vector(29 DOWNTO 0);
p3_cmd_empty : out std_logic;
p3_cmd_full : out std_logic;
p3_wr_clk : in std_logic;
p3_wr_en : in std_logic;
p3_wr_mask : in std_logic_vector(3 DOWNTO 0);
p3_wr_data : in std_logic_vector(31 DOWNTO 0);
p3_wr_full : out std_logic;
p3_wr_empty : out std_logic;
p3_wr_count : out std_logic_vector(6 DOWNTO 0);
p3_wr_underrun : out std_logic;
p3_wr_error : out std_logic;
p3_rd_clk : in std_logic;
p3_rd_en : in std_logic;
p3_rd_data : out std_logic_vector(31 DOWNTO 0);
p3_rd_full : out std_logic;
p3_rd_empty : out std_logic;
p3_rd_count : out std_logic_vector(6 DOWNTO 0);
p3_rd_overflow : out std_logic;
p3_rd_error : out std_logic;
p4_arb_en : in std_logic;
p4_cmd_clk : in std_logic;
p4_cmd_en : in std_logic;
p4_cmd_instr : in std_logic_vector(2 DOWNTO 0);
p4_cmd_bl : in std_logic_vector(5 DOWNTO 0);
p4_cmd_byte_addr : in std_logic_vector(29 DOWNTO 0);
p4_cmd_empty : out std_logic;
p4_cmd_full : out std_logic;
p4_wr_clk : in std_logic;
p4_wr_en : in std_logic;
p4_wr_mask : in std_logic_vector(3 DOWNTO 0);
p4_wr_data : in std_logic_vector(31 DOWNTO 0);
p4_wr_full : out std_logic;
p4_wr_empty : out std_logic;
p4_wr_count : out std_logic_vector(6 DOWNTO 0);
p4_wr_underrun : out std_logic;
p4_wr_error : out std_logic;
p4_rd_clk : in std_logic;
p4_rd_en : in std_logic;
p4_rd_data : out std_logic_vector(31 DOWNTO 0);
p4_rd_full : out std_logic;
p4_rd_empty : out std_logic;
p4_rd_count : out std_logic_vector(6 DOWNTO 0);
p4_rd_overflow : out std_logic;
p4_rd_error : out std_logic;
p5_arb_en : in std_logic;
p5_cmd_clk : in std_logic;
p5_cmd_en : in std_logic;
p5_cmd_instr : in std_logic_vector(2 DOWNTO 0);
p5_cmd_bl : in std_logic_vector(5 DOWNTO 0);
p5_cmd_byte_addr : in std_logic_vector(29 DOWNTO 0);
p5_cmd_empty : out std_logic;
p5_cmd_full : out std_logic;
p5_wr_clk : in std_logic;
p5_wr_en : in std_logic;
p5_wr_mask : in std_logic_vector(3 DOWNTO 0);
p5_wr_data : in std_logic_vector(31 DOWNTO 0);
p5_wr_full : out std_logic;
p5_wr_empty : out std_logic;
p5_wr_count : out std_logic_vector(6 DOWNTO 0);
p5_wr_underrun : out std_logic;
p5_wr_error : out std_logic;
p5_rd_clk : in std_logic;
p5_rd_en : in std_logic;
p5_rd_data : out std_logic_vector(31 DOWNTO 0);
p5_rd_full : out std_logic;
p5_rd_empty : out std_logic;
p5_rd_count : out std_logic_vector(6 DOWNTO 0);
p5_rd_overflow : out std_logic;
p5_rd_error : out std_logic;
mcbx_dram_addr : out std_logic_vector(C_MEM_ADDR_WIDTH - 1 DOWNTO 0);
mcbx_dram_ba : out std_logic_vector(C_MEM_BANKADDR_WIDTH - 1 DOWNTO 0);
mcbx_dram_ras_n : out std_logic;
mcbx_dram_cas_n : out std_logic;
mcbx_dram_we_n : out std_logic;
mcbx_dram_cke : out std_logic;
mcbx_dram_clk : out std_logic;
mcbx_dram_clk_n : out std_logic;
mcbx_dram_dq : inout std_logic_vector(C_NUM_DQ_PINS-1 DOWNTO 0);
mcbx_dram_dqs : inout std_logic;
mcbx_dram_dqs_n : inout std_logic;
mcbx_dram_udqs : inout std_logic;
mcbx_dram_udqs_n : inout std_logic;
mcbx_dram_udm : out std_logic;
mcbx_dram_ldm : out std_logic;
mcbx_dram_odt : out std_logic;
mcbx_dram_ddr3_rst : out std_logic;
calib_recal : in std_logic;
rzq : inout std_logic;
zio : inout std_logic;
ui_read : in std_logic;
ui_add : in std_logic;
ui_cs : in std_logic;
ui_clk : in std_logic;
ui_sdi : in std_logic;
ui_addr : in std_logic_vector(4 DOWNTO 0);
ui_broadcast : in std_logic;
ui_drp_update : in std_logic;
ui_done_cal : in std_logic;
ui_cmd : in std_logic;
ui_cmd_in : in std_logic;
ui_cmd_en : in std_logic;
ui_dqcount : in std_logic_vector(3 DOWNTO 0);
ui_dq_lower_dec : in std_logic;
ui_dq_lower_inc : in std_logic;
ui_dq_upper_dec : in std_logic;
ui_dq_upper_inc : in std_logic;
ui_udqs_inc : in std_logic;
ui_udqs_dec : in std_logic;
ui_ldqs_inc : in std_logic;
ui_ldqs_dec : in std_logic;
uo_data : out std_logic_vector(7 DOWNTO 0);
uo_data_valid : out std_logic;
uo_done_cal : out std_logic;
uo_cmd_ready_in : out std_logic;
uo_refrsh_flag : out std_logic;
uo_cal_start : out std_logic;
uo_sdo : out std_logic;
status : out std_logic_vector(31 DOWNTO 0);
selfrefresh_enter : in std_logic;
selfrefresh_mode : out std_logic
);
end component;
signal uo_data : std_logic_vector(7 downto 0);
constant C_PORT_ENABLE : std_logic_vector(5 downto 0) := "000001";
constant C_PORT_CONFIG : string := "B32_B32_R32_R32_R32_R32";
constant ARB_TIME_SLOT_0 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_0(2 downto 0));
constant ARB_TIME_SLOT_1 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_1(2 downto 0));
constant ARB_TIME_SLOT_2 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_2(2 downto 0));
constant ARB_TIME_SLOT_3 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_3(2 downto 0));
constant ARB_TIME_SLOT_4 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_4(2 downto 0));
constant ARB_TIME_SLOT_5 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_5(2 downto 0));
constant ARB_TIME_SLOT_6 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_6(2 downto 0));
constant ARB_TIME_SLOT_7 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_7(2 downto 0));
constant ARB_TIME_SLOT_8 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_8(2 downto 0));
constant ARB_TIME_SLOT_9 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_9(2 downto 0));
constant ARB_TIME_SLOT_10 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_10(2 downto 0));
constant ARB_TIME_SLOT_11 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_11(2 downto 0));
constant C_MC_CALIBRATION_CLK_DIV : integer := 1;
constant C_MEM_TZQINIT_MAXCNT : std_logic_vector(9 downto 0) := "1000000000" + "0000010000"; -- 16 cycles are added to avoid trfc violations
constant C_SKIP_DYN_IN_TERM : integer := 1;
constant C_MC_CALIBRATION_RA : bit_vector(15 downto 0) := X"0000";
constant C_MC_CALIBRATION_BA : bit_vector(2 downto 0) := o"0";
constant C_MC_CALIBRATION_CA : bit_vector(11 downto 0) := X"000";
constant C_MEM_DDR3_DYN_WRT_ODT : string := "OFF";
signal status : std_logic_vector(31 downto 0);
signal uo_data_valid : std_logic;
signal uo_cmd_ready_in : std_logic;
signal uo_refrsh_flag : std_logic;
signal uo_cal_start : std_logic;
signal uo_sdo : std_logic;
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of acch : architecture IS
"mig_v3_9_ddr3_s6, Coregen 13.3";
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of acch : architecture IS "mcb3_ddr3_s6,mig_v3_9,{LANGUAGE=VHDL, SYNTHESIS_TOOL=ISE, NO_OF_CONTROLLERS=2, AXI_ENABLE=0, MEM_INTERFACE_TYPE=DDR3_SDRAM, CLK_PERIOD=2500, MEMORY_PART=mt41j128m16xx-15e, MEMORY_DEVICE_WIDTH=16, OUTPUT_DRV=DIV6, RTT_NOM=DIV4, AUTO_SR=ENABLED, HIGH_TEMP_SR=NORMAL, PORT_CONFIG=Two 32-bit bi-directional and four 32-bit unidirectional ports, MEM_ADDR_ORDER=ROW_BANK_COLUMN, PORT_ENABLE=Port0, INPUT_PIN_TERMINATION=CALIB_TERM, DATA_TERMINATION=25 Ohms, CLKFBOUT_MULT_F=2, CLKOUT_DIVIDE=1, DEBUG_PORT=0, INPUT_CLK_TYPE=Differential}";
begin
memc3_mcb_raw_wrapper_inst : mcb_raw_wrapper
generic map
(
C_MEMCLK_PERIOD => C_MEMCLK_PERIOD,
C_P0_MASK_SIZE => C_P0_MASK_SIZE,
C_P0_DATA_PORT_SIZE => C_P0_DATA_PORT_SIZE,
C_P1_MASK_SIZE => C_P1_MASK_SIZE,
C_P1_DATA_PORT_SIZE => C_P1_DATA_PORT_SIZE,
C_ARB_NUM_TIME_SLOTS => C_ARB_NUM_TIME_SLOTS,
C_ARB_TIME_SLOT_0 => ARB_TIME_SLOT_0,
C_ARB_TIME_SLOT_1 => ARB_TIME_SLOT_1,
C_ARB_TIME_SLOT_2 => ARB_TIME_SLOT_2,
C_ARB_TIME_SLOT_3 => ARB_TIME_SLOT_3,
C_ARB_TIME_SLOT_4 => ARB_TIME_SLOT_4,
C_ARB_TIME_SLOT_5 => ARB_TIME_SLOT_5,
C_ARB_TIME_SLOT_6 => ARB_TIME_SLOT_6,
C_ARB_TIME_SLOT_7 => ARB_TIME_SLOT_7,
C_ARB_TIME_SLOT_8 => ARB_TIME_SLOT_8,
C_ARB_TIME_SLOT_9 => ARB_TIME_SLOT_9,
C_ARB_TIME_SLOT_10 => ARB_TIME_SLOT_10,
C_ARB_TIME_SLOT_11 => ARB_TIME_SLOT_11,
C_PORT_CONFIG => C_PORT_CONFIG,
C_PORT_ENABLE => C_PORT_ENABLE,
C_MEM_TRAS => C_MEM_TRAS,
C_MEM_TRCD => C_MEM_TRCD,
C_MEM_TREFI => C_MEM_TREFI,
C_MEM_TRFC => C_MEM_TRFC,
C_MEM_TRP => C_MEM_TRP,
C_MEM_TWR => C_MEM_TWR,
C_MEM_TRTP => C_MEM_TRTP,
C_MEM_TWTR => C_MEM_TWTR,
C_MEM_ADDR_ORDER => C_MEM_ADDR_ORDER,
C_NUM_DQ_PINS => C_NUM_DQ_PINS,
C_MEM_TYPE => C_MEM_TYPE,
C_MEM_DENSITY => C_MEM_DENSITY,
C_MEM_BURST_LEN => C_MEM_BURST_LEN,
C_MEM_CAS_LATENCY => C_MEM_CAS_LATENCY,
C_MEM_ADDR_WIDTH => C_MEM_ADDR_WIDTH,
C_MEM_BANKADDR_WIDTH => C_MEM_BANKADDR_WIDTH,
C_MEM_NUM_COL_BITS => C_MEM_NUM_COL_BITS,
C_MEM_DDR1_2_ODS => C_MEM_DDR1_2_ODS,
C_MEM_DDR2_RTT => C_MEM_DDR2_RTT,
C_MEM_DDR2_DIFF_DQS_EN => C_MEM_DDR2_DIFF_DQS_EN,
C_MEM_DDR2_3_PA_SR => C_MEM_DDR2_3_PA_SR,
C_MEM_DDR2_3_HIGH_TEMP_SR => C_MEM_DDR2_3_HIGH_TEMP_SR,
C_MEM_DDR3_CAS_LATENCY => C_MEM_DDR3_CAS_LATENCY,
C_MEM_DDR3_ODS => C_MEM_DDR3_ODS,
C_MEM_DDR3_RTT => C_MEM_DDR3_RTT,
C_MEM_DDR3_CAS_WR_LATENCY => C_MEM_DDR3_CAS_WR_LATENCY,
C_MEM_DDR3_AUTO_SR => C_MEM_DDR3_AUTO_SR,
C_MEM_DDR3_DYN_WRT_ODT => C_MEM_DDR3_DYN_WRT_ODT,
C_MEM_MOBILE_PA_SR => C_MEM_MOBILE_PA_SR,
C_MEM_MDDR_ODS => C_MEM_MDDR_ODS,
C_MC_CALIBRATION_CLK_DIV => C_MC_CALIBRATION_CLK_DIV,
C_MC_CALIBRATION_MODE => C_MC_CALIBRATION_MODE,
C_MC_CALIBRATION_DELAY => C_MC_CALIBRATION_DELAY,
C_MC_CALIB_BYPASS => C_MC_CALIB_BYPASS,
C_MC_CALIBRATION_RA => C_MC_CALIBRATION_RA,
C_MC_CALIBRATION_BA => C_MC_CALIBRATION_BA,
C_MC_CALIBRATION_CA => C_MC_CALIBRATION_CA,
C_CALIB_SOFT_IP => C_CALIB_SOFT_IP,
C_SIMULATION => C_SIMULATION,
C_SKIP_IN_TERM_CAL => C_SKIP_IN_TERM_CAL,
C_SKIP_DYNAMIC_CAL => C_SKIP_DYNAMIC_CAL,
C_SKIP_DYN_IN_TERM => C_SKIP_DYN_IN_TERM,
C_MEM_TZQINIT_MAXCNT => C_MEM_TZQINIT_MAXCNT,
LDQSP_TAP_DELAY_VAL => C_LDQSP_TAP_DELAY_VAL,
UDQSP_TAP_DELAY_VAL => C_UDQSP_TAP_DELAY_VAL,
LDQSN_TAP_DELAY_VAL => C_LDQSN_TAP_DELAY_VAL,
UDQSN_TAP_DELAY_VAL => C_UDQSN_TAP_DELAY_VAL,
DQ0_TAP_DELAY_VAL => C_DQ0_TAP_DELAY_VAL,
DQ1_TAP_DELAY_VAL => C_DQ1_TAP_DELAY_VAL,
DQ2_TAP_DELAY_VAL => C_DQ2_TAP_DELAY_VAL,
DQ3_TAP_DELAY_VAL => C_DQ3_TAP_DELAY_VAL,
DQ4_TAP_DELAY_VAL => C_DQ4_TAP_DELAY_VAL,
DQ5_TAP_DELAY_VAL => C_DQ5_TAP_DELAY_VAL,
DQ6_TAP_DELAY_VAL => C_DQ6_TAP_DELAY_VAL,
DQ7_TAP_DELAY_VAL => C_DQ7_TAP_DELAY_VAL,
DQ8_TAP_DELAY_VAL => C_DQ8_TAP_DELAY_VAL,
DQ9_TAP_DELAY_VAL => C_DQ9_TAP_DELAY_VAL,
DQ10_TAP_DELAY_VAL => C_DQ10_TAP_DELAY_VAL,
DQ11_TAP_DELAY_VAL => C_DQ11_TAP_DELAY_VAL,
DQ12_TAP_DELAY_VAL => C_DQ12_TAP_DELAY_VAL,
DQ13_TAP_DELAY_VAL => C_DQ13_TAP_DELAY_VAL,
DQ14_TAP_DELAY_VAL => C_DQ14_TAP_DELAY_VAL,
DQ15_TAP_DELAY_VAL => C_DQ15_TAP_DELAY_VAL
)
port map
(
sys_rst => async_rst,
sysclk_2x => sysclk_2x,
sysclk_2x_180 => sysclk_2x_180,
pll_ce_0 => pll_ce_0,
pll_ce_90 => pll_ce_90,
pll_lock => pll_lock,
mcbx_dram_addr => mcb3_dram_a,
mcbx_dram_ba => mcb3_dram_ba,
mcbx_dram_ras_n => mcb3_dram_ras_n,
mcbx_dram_cas_n => mcb3_dram_cas_n,
mcbx_dram_we_n => mcb3_dram_we_n,
mcbx_dram_cke => mcb3_dram_cke,
mcbx_dram_clk => mcb3_dram_ck,
mcbx_dram_clk_n => mcb3_dram_ck_n,
mcbx_dram_dq => mcb3_dram_dq,
mcbx_dram_odt => mcb3_dram_odt,
mcbx_dram_ldm => mcb3_dram_dm,
mcbx_dram_udm => mcb3_dram_udm,
mcbx_dram_dqs => mcb3_dram_dqs,
mcbx_dram_dqs_n => mcb3_dram_dqs_n,
mcbx_dram_udqs => mcb3_dram_udqs,
mcbx_dram_udqs_n => mcb3_dram_udqs_n,
mcbx_dram_ddr3_rst => mcb3_dram_reset_n,
calib_recal => '0',
rzq => mcb3_rzq,
zio => mcb3_zio,
ui_read => '0',
ui_add => '0',
ui_cs => '0',
ui_clk => mcb_drp_clk,
ui_sdi => '0',
ui_addr => (others => '0'),
ui_broadcast => '0',
ui_drp_update => '0',
ui_done_cal => '1',
ui_cmd => '0',
ui_cmd_in => '0',
ui_cmd_en => '0',
ui_dqcount => (others => '0'),
ui_dq_lower_dec => '0',
ui_dq_lower_inc => '0',
ui_dq_upper_dec => '0',
ui_dq_upper_inc => '0',
ui_udqs_inc => '0',
ui_udqs_dec => '0',
ui_ldqs_inc => '0',
ui_ldqs_dec => '0',
uo_data => uo_data,
uo_data_valid => uo_data_valid,
uo_done_cal => calib_done,
uo_cmd_ready_in => uo_cmd_ready_in,
uo_refrsh_flag => uo_refrsh_flag,
uo_cal_start => uo_cal_start,
uo_sdo => uo_sdo,
status => status,
selfrefresh_enter => '0',
selfrefresh_mode => selfrefresh_mode,
p0_arb_en => '1',
p0_cmd_clk => p0_cmd_clk,
p0_cmd_en => p0_cmd_en,
p0_cmd_instr => p0_cmd_instr,
p0_cmd_bl => p0_cmd_bl,
p0_cmd_byte_addr => p0_cmd_byte_addr,
p0_cmd_empty => p0_cmd_empty,
p0_cmd_full => p0_cmd_full,
p0_wr_clk => p0_wr_clk,
p0_wr_en => p0_wr_en,
p0_wr_mask => p0_wr_mask,
p0_wr_data => p0_wr_data,
p0_wr_full => p0_wr_full,
p0_wr_empty => p0_wr_empty,
p0_wr_count => p0_wr_count,
p0_wr_underrun => p0_wr_underrun,
p0_wr_error => p0_wr_error,
p0_rd_clk => p0_rd_clk,
p0_rd_en => p0_rd_en,
p0_rd_data => p0_rd_data,
p0_rd_full => p0_rd_full,
p0_rd_empty => p0_rd_empty,
p0_rd_count => p0_rd_count,
p0_rd_overflow => p0_rd_overflow,
p0_rd_error => p0_rd_error,
p1_arb_en => '0',
p1_cmd_clk => '0',
p1_cmd_en => '0',
p1_cmd_instr => (others => '0'),
p1_cmd_bl => (others => '0'),
p1_cmd_byte_addr => (others => '0'),
p1_cmd_empty => open,
p1_cmd_full => open,
p1_rd_clk => '0',
p1_rd_en => '0',
p1_rd_data => open,
p1_rd_full => open,
p1_rd_empty => open,
p1_rd_count => open,
p1_rd_overflow => open,
p1_rd_error => open,
p1_wr_clk => '0',
p1_wr_en => '0',
p1_wr_mask => (others => '0'),
p1_wr_data => (others => '0'),
p1_wr_full => open,
p1_wr_empty => open,
p1_wr_count => open,
p1_wr_underrun => open,
p1_wr_error => open,
p2_arb_en => '0',
p2_cmd_clk => '0',
p2_cmd_en => '0',
p2_cmd_instr => (others => '0'),
p2_cmd_bl => (others => '0'),
p2_cmd_byte_addr => (others => '0'),
p2_cmd_empty => open,
p2_cmd_full => open,
p2_rd_clk => '0',
p2_rd_en => '0',
p2_rd_data => open,
p2_rd_full => open,
p2_rd_empty => open,
p2_rd_count => open,
p2_rd_overflow => open,
p2_rd_error => open,
p2_wr_clk => '0',
p2_wr_en => '0',
p2_wr_mask => (others => '0'),
p2_wr_data => (others => '0'),
p2_wr_full => open,
p2_wr_empty => open,
p2_wr_count => open,
p2_wr_underrun => open,
p2_wr_error => open,
p3_arb_en => '0',
p3_cmd_clk => '0',
p3_cmd_en => '0',
p3_cmd_instr => (others => '0'),
p3_cmd_bl => (others => '0'),
p3_cmd_byte_addr => (others => '0'),
p3_cmd_empty => open,
p3_cmd_full => open,
p3_rd_clk => '0',
p3_rd_en => '0',
p3_rd_data => open,
p3_rd_full => open,
p3_rd_empty => open,
p3_rd_count => open,
p3_rd_overflow => open,
p3_rd_error => open,
p3_wr_clk => '0',
p3_wr_en => '0',
p3_wr_mask => (others => '0'),
p3_wr_data => (others => '0'),
p3_wr_full => open,
p3_wr_empty => open,
p3_wr_count => open,
p3_wr_underrun => open,
p3_wr_error => open,
p4_arb_en => '0',
p4_cmd_clk => '0',
p4_cmd_en => '0',
p4_cmd_instr => (others => '0'),
p4_cmd_bl => (others => '0'),
p4_cmd_byte_addr => (others => '0'),
p4_cmd_empty => open,
p4_cmd_full => open,
p4_rd_clk => '0',
p4_rd_en => '0',
p4_rd_data => open,
p4_rd_full => open,
p4_rd_empty => open,
p4_rd_count => open,
p4_rd_overflow => open,
p4_rd_error => open,
p4_wr_clk => '0',
p4_wr_en => '0',
p4_wr_mask => (others => '0'),
p4_wr_data => (others => '0'),
p4_wr_full => open,
p4_wr_empty => open,
p4_wr_count => open,
p4_wr_underrun => open,
p4_wr_error => open,
p5_arb_en => '0',
p5_cmd_clk => '0',
p5_cmd_en => '0',
p5_cmd_instr => (others => '0'),
p5_cmd_bl => (others => '0'),
p5_cmd_byte_addr => (others => '0'),
p5_cmd_empty => open,
p5_cmd_full => open,
p5_rd_clk => '0',
p5_rd_en => '0',
p5_rd_data => open,
p5_rd_full => open,
p5_rd_empty => open,
p5_rd_count => open,
p5_rd_overflow => open,
p5_rd_error => open,
p5_wr_clk => '0',
p5_wr_en => '0',
p5_wr_mask => (others => '0'),
p5_wr_data => (others => '0'),
p5_wr_full => open,
p5_wr_empty => open,
p5_wr_count => open,
p5_wr_underrun => open,
p5_wr_error => open
);
end architecture;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 19:32:46 06/20/2014
-- Design Name:
-- Module Name: channel_avg - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
USE ieee.numeric_std.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
LIBRARY UNISIM;
USE UNISIM.VComponents.ALL;
ENTITY channel_avg IS
GENERIC (
NCH : positive := 16;
OUTCH_WIDTH : positive := 16;
INTERNAL_WIDTH : positive := 32;
INDATA_WIDTH : positive := 256;
OUTDATA_WIDTH : positive := 256
);
PORT (
RESET : IN std_logic;
CLK : IN std_logic;
-- high 4-bit is offset, 2**(low 4-bit) is number of points to average
CONFIG : IN std_logic_vector(7 DOWNTO 0);
TRIG : IN std_logic;
INDATA_Q : IN std_logic_vector(INDATA_WIDTH-1 DOWNTO 0);
OUTVALID : OUT std_logic;
OUTDATA_Q : OUT std_logic_vector(OUTDATA_WIDTH-1 DOWNTO 0)
);
END channel_avg;
ARCHITECTURE Behavioral OF channel_avg IS
SIGNAL trig_prev : std_logic;
SIGNAL trig_prev1 : std_logic;
SIGNAL trig_prev2 : std_logic;
SIGNAL trig_synced : std_logic;
--
SIGNAL avg_n : positive;
--
TYPE INTERNALVAL IS ARRAY(NCH-1 DOWNTO 0) OF signed(INTERNAL_WIDTH-1 DOWNTO 0);
SIGNAL inch_val : INTERNALVAL;
SIGNAL internal_val : INTERNALVAL;
BEGIN
PROCESS (CLK) IS
VARIABLE i : integer;
BEGIN
IF falling_edge(CLK) THEN -- register half-cycle earlier
FOR i IN 0 TO NCH-1 LOOP
inch_val(i) <= resize(signed(INDATA_Q(16*(i+1)-1 DOWNTO 16*i)), INTERNAL_WIDTH);
END LOOP;
END IF;
END PROCESS;
-- capture the rising edge of trigger
PROCESS (CLK, RESET) IS
BEGIN
IF RESET = '1' THEN
trig_prev <= '0';
trig_prev1 <= '0';
trig_prev2 <= '0';
ELSIF rising_edge(CLK) THEN
trig_prev <= TRIG;
trig_prev1 <= trig_prev;
trig_prev2 <= trig_prev1;
END IF;
END PROCESS;
trig_synced <= '1' WHEN trig_prev2 = '0' AND trig_prev1 = '1' ELSE '0';
avg_n <= to_integer(unsigned(CONFIG(3 DOWNTO 0)));
PROCESS (CLK, RESET) IS
VARIABLE i : integer;
VARIABLE j : unsigned(15 DOWNTO 0);
BEGIN
IF RESET = '1' THEN
FOR i IN 0 TO NCH-1 LOOP
internal_val(i) <= (OTHERS => '0');
END LOOP;
OUTVALID <= '0';
j := (OTHERS => '0');
ELSIF rising_edge(CLK) THEN
IF trig_synced = '1' THEN
j := resize(unsigned(CONFIG(7 DOWNTO 4)), j'length) + 1;
END IF;
FOR i IN 0 TO NCH-1 LOOP
IF j = 1 THEN
internal_val(i) <= inch_val(i);
ELSE
internal_val(i) <= internal_val(i) + inch_val(i);
END IF;
END LOOP;
IF j(avg_n) = '1' THEN
j := to_unsigned(1, j'length);
OUTVALID <= '1';
ELSE
j := j + 1;
OUTVALID <= '0';
END IF;
END IF;
END PROCESS;
outdata_q_inst : FOR i IN 0 TO NCH-1 GENERATE
OUTDATA_Q(OUTCH_WIDTH*(i+1)-1 DOWNTO OUTCH_WIDTH*i) <=
std_logic_vector(internal_val(i)(OUTCH_WIDTH-1+avg_n DOWNTO avg_n));
END GENERATE;
END Behavioral;
|
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