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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity deslocador_bit is
port (
);
end deslocador_bit;
architecture Behavioral of deslocador_bit is
begin
end Behavioral;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity deslocador_bit is
port (
);
end deslocador_bit;
architecture Behavioral of deslocador_bit is
begin
end Behavioral;
|
-------------------------------------------------------
--! @file
--! @brief 2:1 Mux using with-select
-------------------------------------------------------
--! Use standard library
library ieee;
--! Use logic elements
use ieee.std_logic_1164.all;
--! Mux entity brief description
--! Detailed description of this
--! mux design element.
entity mux_using_with is
port (
din_0 : in std_logic; --! Mux first input
din_1 : in std_logic; --! Mux Second input
sel : in std_logic; --! Select input
mux_out : out std_logic --! Mux output
);
end entity;
--! @brief Architure definition of the MUX
--! @details More details about this mux element.
architecture behavior of mux_using_with is
begin
with (sel) select
mux_out <= din_0 when '0',
din_1 when others;
end architecture;
|
-------------------------------------------------------
--! @file
--! @brief 2:1 Mux using with-select
-------------------------------------------------------
--! Use standard library
library ieee;
--! Use logic elements
use ieee.std_logic_1164.all;
--! Mux entity brief description
--! Detailed description of this
--! mux design element.
entity mux_using_with is
port (
din_0 : in std_logic; --! Mux first input
din_1 : in std_logic; --! Mux Second input
sel : in std_logic; --! Select input
mux_out : out std_logic --! Mux output
);
end entity;
--! @brief Architure definition of the MUX
--! @details More details about this mux element.
architecture behavior of mux_using_with is
begin
with (sel) select
mux_out <= din_0 when '0',
din_1 when others;
end architecture;
|
-------------------------------------------------------
--! @file
--! @brief 2:1 Mux using with-select
-------------------------------------------------------
--! Use standard library
library ieee;
--! Use logic elements
use ieee.std_logic_1164.all;
--! Mux entity brief description
--! Detailed description of this
--! mux design element.
entity mux_using_with is
port (
din_0 : in std_logic; --! Mux first input
din_1 : in std_logic; --! Mux Second input
sel : in std_logic; --! Select input
mux_out : out std_logic --! Mux output
);
end entity;
--! @brief Architure definition of the MUX
--! @details More details about this mux element.
architecture behavior of mux_using_with is
begin
with (sel) select
mux_out <= din_0 when '0',
din_1 when others;
end architecture;
|
-------------------------------------------------------
--! @file
--! @brief 2:1 Mux using with-select
-------------------------------------------------------
--! Use standard library
library ieee;
--! Use logic elements
use ieee.std_logic_1164.all;
--! Mux entity brief description
--! Detailed description of this
--! mux design element.
entity mux_using_with is
port (
din_0 : in std_logic; --! Mux first input
din_1 : in std_logic; --! Mux Second input
sel : in std_logic; --! Select input
mux_out : out std_logic --! Mux output
);
end entity;
--! @brief Architure definition of the MUX
--! @details More details about this mux element.
architecture behavior of mux_using_with is
begin
with (sel) select
mux_out <= din_0 when '0',
din_1 when others;
end architecture;
|
-------------------------------------------------------
--! @file
--! @brief 2:1 Mux using with-select
-------------------------------------------------------
--! Use standard library
library ieee;
--! Use logic elements
use ieee.std_logic_1164.all;
--! Mux entity brief description
--! Detailed description of this
--! mux design element.
entity mux_using_with is
port (
din_0 : in std_logic; --! Mux first input
din_1 : in std_logic; --! Mux Second input
sel : in std_logic; --! Select input
mux_out : out std_logic --! Mux output
);
end entity;
--! @brief Architure definition of the MUX
--! @details More details about this mux element.
architecture behavior of mux_using_with is
begin
with (sel) select
mux_out <= din_0 when '0',
din_1 when others;
end architecture;
|
-------------------------------------------------------
--! @file
--! @brief 2:1 Mux using with-select
-------------------------------------------------------
--! Use standard library
library ieee;
--! Use logic elements
use ieee.std_logic_1164.all;
--! Mux entity brief description
--! Detailed description of this
--! mux design element.
entity mux_using_with is
port (
din_0 : in std_logic; --! Mux first input
din_1 : in std_logic; --! Mux Second input
sel : in std_logic; --! Select input
mux_out : out std_logic --! Mux output
);
end entity;
--! @brief Architure definition of the MUX
--! @details More details about this mux element.
architecture behavior of mux_using_with is
begin
with (sel) select
mux_out <= din_0 when '0',
din_1 when others;
end architecture;
|
-------------------------------------------------------
--! @file
--! @brief 2:1 Mux using with-select
-------------------------------------------------------
--! Use standard library
library ieee;
--! Use logic elements
use ieee.std_logic_1164.all;
--! Mux entity brief description
--! Detailed description of this
--! mux design element.
entity mux_using_with is
port (
din_0 : in std_logic; --! Mux first input
din_1 : in std_logic; --! Mux Second input
sel : in std_logic; --! Select input
mux_out : out std_logic --! Mux output
);
end entity;
--! @brief Architure definition of the MUX
--! @details More details about this mux element.
architecture behavior of mux_using_with is
begin
with (sel) select
mux_out <= din_0 when '0',
din_1 when others;
end architecture;
|
-------------------------------------------------------
--! @file
--! @brief 2:1 Mux using with-select
-------------------------------------------------------
--! Use standard library
library ieee;
--! Use logic elements
use ieee.std_logic_1164.all;
--! Mux entity brief description
--! Detailed description of this
--! mux design element.
entity mux_using_with is
port (
din_0 : in std_logic; --! Mux first input
din_1 : in std_logic; --! Mux Second input
sel : in std_logic; --! Select input
mux_out : out std_logic --! Mux output
);
end entity;
--! @brief Architure definition of the MUX
--! @details More details about this mux element.
architecture behavior of mux_using_with is
begin
with (sel) select
mux_out <= din_0 when '0',
din_1 when others;
end architecture;
|
-------------------------------------------------------
--! @file
--! @brief 2:1 Mux using with-select
-------------------------------------------------------
--! Use standard library
library ieee;
--! Use logic elements
use ieee.std_logic_1164.all;
--! Mux entity brief description
--! Detailed description of this
--! mux design element.
entity mux_using_with is
port (
din_0 : in std_logic; --! Mux first input
din_1 : in std_logic; --! Mux Second input
sel : in std_logic; --! Select input
mux_out : out std_logic --! Mux output
);
end entity;
--! @brief Architure definition of the MUX
--! @details More details about this mux element.
architecture behavior of mux_using_with is
begin
with (sel) select
mux_out <= din_0 when '0',
din_1 when others;
end architecture;
|
-------------------------------------------------------
--! @file
--! @brief 2:1 Mux using with-select
-------------------------------------------------------
--! Use standard library
library ieee;
--! Use logic elements
use ieee.std_logic_1164.all;
--! Mux entity brief description
--! Detailed description of this
--! mux design element.
entity mux_using_with is
port (
din_0 : in std_logic; --! Mux first input
din_1 : in std_logic; --! Mux Second input
sel : in std_logic; --! Select input
mux_out : out std_logic --! Mux output
);
end entity;
--! @brief Architure definition of the MUX
--! @details More details about this mux element.
architecture behavior of mux_using_with is
begin
with (sel) select
mux_out <= din_0 when '0',
din_1 when others;
end architecture;
|
-------------------------------------------------------
--! @file
--! @brief 2:1 Mux using with-select
-------------------------------------------------------
--! Use standard library
library ieee;
--! Use logic elements
use ieee.std_logic_1164.all;
--! Mux entity brief description
--! Detailed description of this
--! mux design element.
entity mux_using_with is
port (
din_0 : in std_logic; --! Mux first input
din_1 : in std_logic; --! Mux Second input
sel : in std_logic; --! Select input
mux_out : out std_logic --! Mux output
);
end entity;
--! @brief Architure definition of the MUX
--! @details More details about this mux element.
architecture behavior of mux_using_with is
begin
with (sel) select
mux_out <= din_0 when '0',
din_1 when others;
end architecture;
|
-------------------------------------------------------
--! @file
--! @brief 2:1 Mux using with-select
-------------------------------------------------------
--! Use standard library
library ieee;
--! Use logic elements
use ieee.std_logic_1164.all;
--! Mux entity brief description
--! Detailed description of this
--! mux design element.
entity mux_using_with is
port (
din_0 : in std_logic; --! Mux first input
din_1 : in std_logic; --! Mux Second input
sel : in std_logic; --! Select input
mux_out : out std_logic --! Mux output
);
end entity;
--! @brief Architure definition of the MUX
--! @details More details about this mux element.
architecture behavior of mux_using_with is
begin
with (sel) select
mux_out <= din_0 when '0',
din_1 when others;
end architecture;
|
-------------------------------------------------------
--! @file
--! @brief 2:1 Mux using with-select
-------------------------------------------------------
--! Use standard library
library ieee;
--! Use logic elements
use ieee.std_logic_1164.all;
--! Mux entity brief description
--! Detailed description of this
--! mux design element.
entity mux_using_with is
port (
din_0 : in std_logic; --! Mux first input
din_1 : in std_logic; --! Mux Second input
sel : in std_logic; --! Select input
mux_out : out std_logic --! Mux output
);
end entity;
--! @brief Architure definition of the MUX
--! @details More details about this mux element.
architecture behavior of mux_using_with is
begin
with (sel) select
mux_out <= din_0 when '0',
din_1 when others;
end architecture;
|
-------------------------------------------------------
--! @file
--! @brief 2:1 Mux using with-select
-------------------------------------------------------
--! Use standard library
library ieee;
--! Use logic elements
use ieee.std_logic_1164.all;
--! Mux entity brief description
--! Detailed description of this
--! mux design element.
entity mux_using_with is
port (
din_0 : in std_logic; --! Mux first input
din_1 : in std_logic; --! Mux Second input
sel : in std_logic; --! Select input
mux_out : out std_logic --! Mux output
);
end entity;
--! @brief Architure definition of the MUX
--! @details More details about this mux element.
architecture behavior of mux_using_with is
begin
with (sel) select
mux_out <= din_0 when '0',
din_1 when others;
end architecture;
|
-------------------------------------------------------
--! @file
--! @brief 2:1 Mux using with-select
-------------------------------------------------------
--! Use standard library
library ieee;
--! Use logic elements
use ieee.std_logic_1164.all;
--! Mux entity brief description
--! Detailed description of this
--! mux design element.
entity mux_using_with is
port (
din_0 : in std_logic; --! Mux first input
din_1 : in std_logic; --! Mux Second input
sel : in std_logic; --! Select input
mux_out : out std_logic --! Mux output
);
end entity;
--! @brief Architure definition of the MUX
--! @details More details about this mux element.
architecture behavior of mux_using_with is
begin
with (sel) select
mux_out <= din_0 when '0',
din_1 when others;
end architecture;
|
-------------------------------------------------------
--! @file
--! @brief 2:1 Mux using with-select
-------------------------------------------------------
--! Use standard library
library ieee;
--! Use logic elements
use ieee.std_logic_1164.all;
--! Mux entity brief description
--! Detailed description of this
--! mux design element.
entity mux_using_with is
port (
din_0 : in std_logic; --! Mux first input
din_1 : in std_logic; --! Mux Second input
sel : in std_logic; --! Select input
mux_out : out std_logic --! Mux output
);
end entity;
--! @brief Architure definition of the MUX
--! @details More details about this mux element.
architecture behavior of mux_using_with is
begin
with (sel) select
mux_out <= din_0 when '0',
din_1 when others;
end architecture;
|
-------------------------------------------------------
--! @file
--! @brief 2:1 Mux using with-select
-------------------------------------------------------
--! Use standard library
library ieee;
--! Use logic elements
use ieee.std_logic_1164.all;
--! Mux entity brief description
--! Detailed description of this
--! mux design element.
entity mux_using_with is
port (
din_0 : in std_logic; --! Mux first input
din_1 : in std_logic; --! Mux Second input
sel : in std_logic; --! Select input
mux_out : out std_logic --! Mux output
);
end entity;
--! @brief Architure definition of the MUX
--! @details More details about this mux element.
architecture behavior of mux_using_with is
begin
with (sel) select
mux_out <= din_0 when '0',
din_1 when others;
end architecture;
|
-------------------------------------------------------
--! @file
--! @brief 2:1 Mux using with-select
-------------------------------------------------------
--! Use standard library
library ieee;
--! Use logic elements
use ieee.std_logic_1164.all;
--! Mux entity brief description
--! Detailed description of this
--! mux design element.
entity mux_using_with is
port (
din_0 : in std_logic; --! Mux first input
din_1 : in std_logic; --! Mux Second input
sel : in std_logic; --! Select input
mux_out : out std_logic --! Mux output
);
end entity;
--! @brief Architure definition of the MUX
--! @details More details about this mux element.
architecture behavior of mux_using_with is
begin
with (sel) select
mux_out <= din_0 when '0',
din_1 when others;
end architecture;
|
-------------------------------------------------------
--! @file
--! @brief 2:1 Mux using with-select
-------------------------------------------------------
--! Use standard library
library ieee;
--! Use logic elements
use ieee.std_logic_1164.all;
--! Mux entity brief description
--! Detailed description of this
--! mux design element.
entity mux_using_with is
port (
din_0 : in std_logic; --! Mux first input
din_1 : in std_logic; --! Mux Second input
sel : in std_logic; --! Select input
mux_out : out std_logic --! Mux output
);
end entity;
--! @brief Architure definition of the MUX
--! @details More details about this mux element.
architecture behavior of mux_using_with is
begin
with (sel) select
mux_out <= din_0 when '0',
din_1 when others;
end architecture;
|
-------------------------------------------------------
--! @file
--! @brief 2:1 Mux using with-select
-------------------------------------------------------
--! Use standard library
library ieee;
--! Use logic elements
use ieee.std_logic_1164.all;
--! Mux entity brief description
--! Detailed description of this
--! mux design element.
entity mux_using_with is
port (
din_0 : in std_logic; --! Mux first input
din_1 : in std_logic; --! Mux Second input
sel : in std_logic; --! Select input
mux_out : out std_logic --! Mux output
);
end entity;
--! @brief Architure definition of the MUX
--! @details More details about this mux element.
architecture behavior of mux_using_with is
begin
with (sel) select
mux_out <= din_0 when '0',
din_1 when others;
end architecture;
|
-------------------------------------------------------
--! @file
--! @brief 2:1 Mux using with-select
-------------------------------------------------------
--! Use standard library
library ieee;
--! Use logic elements
use ieee.std_logic_1164.all;
--! Mux entity brief description
--! Detailed description of this
--! mux design element.
entity mux_using_with is
port (
din_0 : in std_logic; --! Mux first input
din_1 : in std_logic; --! Mux Second input
sel : in std_logic; --! Select input
mux_out : out std_logic --! Mux output
);
end entity;
--! @brief Architure definition of the MUX
--! @details More details about this mux element.
architecture behavior of mux_using_with is
begin
with (sel) select
mux_out <= din_0 when '0',
din_1 when others;
end architecture;
|
-------------------------------------------------------
--! @file
--! @brief 2:1 Mux using with-select
-------------------------------------------------------
--! Use standard library
library ieee;
--! Use logic elements
use ieee.std_logic_1164.all;
--! Mux entity brief description
--! Detailed description of this
--! mux design element.
entity mux_using_with is
port (
din_0 : in std_logic; --! Mux first input
din_1 : in std_logic; --! Mux Second input
sel : in std_logic; --! Select input
mux_out : out std_logic --! Mux output
);
end entity;
--! @brief Architure definition of the MUX
--! @details More details about this mux element.
architecture behavior of mux_using_with is
begin
with (sel) select
mux_out <= din_0 when '0',
din_1 when others;
end architecture;
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.3 (win64) Build 1682563 Mon Oct 10 19:07:27 MDT 2016
-- Date : Fri Sep 22 20:11:26 2017
-- Host : vldmr-PC running 64-bit Service Pack 1 (build 7601)
-- Command : write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ tx_axis_gen_sim_netlist.vhdl
-- Design : tx_axis_gen
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7k325tffg676-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dmem is
port (
\goreg_dm.dout_i_reg[64]\ : out STD_LOGIC_VECTOR ( 64 downto 0 );
clk : in STD_LOGIC;
EN : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 64 downto 0 );
\gc0.count_d1_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dmem;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dmem is
signal p_0_out : STD_LOGIC_VECTOR ( 64 downto 0 );
signal NLW_RAM_reg_0_15_0_5_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_12_17_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_18_23_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_24_29_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_30_35_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_36_41_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_42_47_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_48_53_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_54_59_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_60_64_DOC_UNCONNECTED : STD_LOGIC_VECTOR ( 1 to 1 );
signal NLW_RAM_reg_0_15_60_64_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_6_11_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute METHODOLOGY_DRC_VIOS : string;
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_0_5 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_12_17 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_18_23 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_24_29 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_30_35 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_36_41 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_42_47 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_48_53 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_54_59 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_60_64 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_6_11 : label is "";
begin
RAM_reg_0_15_0_5: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => Q(3 downto 0),
DIA(1 downto 0) => din(1 downto 0),
DIB(1 downto 0) => din(3 downto 2),
DIC(1 downto 0) => din(5 downto 4),
DID(1 downto 0) => B"00",
DOA(1 downto 0) => p_0_out(1 downto 0),
DOB(1 downto 0) => p_0_out(3 downto 2),
DOC(1 downto 0) => p_0_out(5 downto 4),
DOD(1 downto 0) => NLW_RAM_reg_0_15_0_5_DOD_UNCONNECTED(1 downto 0),
WCLK => clk,
WE => EN
);
RAM_reg_0_15_12_17: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => Q(3 downto 0),
DIA(1 downto 0) => din(13 downto 12),
DIB(1 downto 0) => din(15 downto 14),
DIC(1 downto 0) => din(17 downto 16),
DID(1 downto 0) => B"00",
DOA(1 downto 0) => p_0_out(13 downto 12),
DOB(1 downto 0) => p_0_out(15 downto 14),
DOC(1 downto 0) => p_0_out(17 downto 16),
DOD(1 downto 0) => NLW_RAM_reg_0_15_12_17_DOD_UNCONNECTED(1 downto 0),
WCLK => clk,
WE => EN
);
RAM_reg_0_15_18_23: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => Q(3 downto 0),
DIA(1 downto 0) => din(19 downto 18),
DIB(1 downto 0) => din(21 downto 20),
DIC(1 downto 0) => din(23 downto 22),
DID(1 downto 0) => B"00",
DOA(1 downto 0) => p_0_out(19 downto 18),
DOB(1 downto 0) => p_0_out(21 downto 20),
DOC(1 downto 0) => p_0_out(23 downto 22),
DOD(1 downto 0) => NLW_RAM_reg_0_15_18_23_DOD_UNCONNECTED(1 downto 0),
WCLK => clk,
WE => EN
);
RAM_reg_0_15_24_29: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => Q(3 downto 0),
DIA(1 downto 0) => din(25 downto 24),
DIB(1 downto 0) => din(27 downto 26),
DIC(1 downto 0) => din(29 downto 28),
DID(1 downto 0) => B"00",
DOA(1 downto 0) => p_0_out(25 downto 24),
DOB(1 downto 0) => p_0_out(27 downto 26),
DOC(1 downto 0) => p_0_out(29 downto 28),
DOD(1 downto 0) => NLW_RAM_reg_0_15_24_29_DOD_UNCONNECTED(1 downto 0),
WCLK => clk,
WE => EN
);
RAM_reg_0_15_30_35: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => Q(3 downto 0),
DIA(1 downto 0) => din(31 downto 30),
DIB(1 downto 0) => din(33 downto 32),
DIC(1 downto 0) => din(35 downto 34),
DID(1 downto 0) => B"00",
DOA(1 downto 0) => p_0_out(31 downto 30),
DOB(1 downto 0) => p_0_out(33 downto 32),
DOC(1 downto 0) => p_0_out(35 downto 34),
DOD(1 downto 0) => NLW_RAM_reg_0_15_30_35_DOD_UNCONNECTED(1 downto 0),
WCLK => clk,
WE => EN
);
RAM_reg_0_15_36_41: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => Q(3 downto 0),
DIA(1 downto 0) => din(37 downto 36),
DIB(1 downto 0) => din(39 downto 38),
DIC(1 downto 0) => din(41 downto 40),
DID(1 downto 0) => B"00",
DOA(1 downto 0) => p_0_out(37 downto 36),
DOB(1 downto 0) => p_0_out(39 downto 38),
DOC(1 downto 0) => p_0_out(41 downto 40),
DOD(1 downto 0) => NLW_RAM_reg_0_15_36_41_DOD_UNCONNECTED(1 downto 0),
WCLK => clk,
WE => EN
);
RAM_reg_0_15_42_47: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => Q(3 downto 0),
DIA(1 downto 0) => din(43 downto 42),
DIB(1 downto 0) => din(45 downto 44),
DIC(1 downto 0) => din(47 downto 46),
DID(1 downto 0) => B"00",
DOA(1 downto 0) => p_0_out(43 downto 42),
DOB(1 downto 0) => p_0_out(45 downto 44),
DOC(1 downto 0) => p_0_out(47 downto 46),
DOD(1 downto 0) => NLW_RAM_reg_0_15_42_47_DOD_UNCONNECTED(1 downto 0),
WCLK => clk,
WE => EN
);
RAM_reg_0_15_48_53: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => Q(3 downto 0),
DIA(1 downto 0) => din(49 downto 48),
DIB(1 downto 0) => din(51 downto 50),
DIC(1 downto 0) => din(53 downto 52),
DID(1 downto 0) => B"00",
DOA(1 downto 0) => p_0_out(49 downto 48),
DOB(1 downto 0) => p_0_out(51 downto 50),
DOC(1 downto 0) => p_0_out(53 downto 52),
DOD(1 downto 0) => NLW_RAM_reg_0_15_48_53_DOD_UNCONNECTED(1 downto 0),
WCLK => clk,
WE => EN
);
RAM_reg_0_15_54_59: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => Q(3 downto 0),
DIA(1 downto 0) => din(55 downto 54),
DIB(1 downto 0) => din(57 downto 56),
DIC(1 downto 0) => din(59 downto 58),
DID(1 downto 0) => B"00",
DOA(1 downto 0) => p_0_out(55 downto 54),
DOB(1 downto 0) => p_0_out(57 downto 56),
DOC(1 downto 0) => p_0_out(59 downto 58),
DOD(1 downto 0) => NLW_RAM_reg_0_15_54_59_DOD_UNCONNECTED(1 downto 0),
WCLK => clk,
WE => EN
);
RAM_reg_0_15_60_64: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => Q(3 downto 0),
DIA(1 downto 0) => din(61 downto 60),
DIB(1 downto 0) => din(63 downto 62),
DIC(1) => '0',
DIC(0) => din(64),
DID(1 downto 0) => B"00",
DOA(1 downto 0) => p_0_out(61 downto 60),
DOB(1 downto 0) => p_0_out(63 downto 62),
DOC(1) => NLW_RAM_reg_0_15_60_64_DOC_UNCONNECTED(1),
DOC(0) => p_0_out(64),
DOD(1 downto 0) => NLW_RAM_reg_0_15_60_64_DOD_UNCONNECTED(1 downto 0),
WCLK => clk,
WE => EN
);
RAM_reg_0_15_6_11: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => Q(3 downto 0),
DIA(1 downto 0) => din(7 downto 6),
DIB(1 downto 0) => din(9 downto 8),
DIC(1 downto 0) => din(11 downto 10),
DID(1 downto 0) => B"00",
DOA(1 downto 0) => p_0_out(7 downto 6),
DOB(1 downto 0) => p_0_out(9 downto 8),
DOC(1 downto 0) => p_0_out(11 downto 10),
DOD(1 downto 0) => NLW_RAM_reg_0_15_6_11_DOD_UNCONNECTED(1 downto 0),
WCLK => clk,
WE => EN
);
\gpr1.dout_i_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => p_0_out(0),
Q => \goreg_dm.dout_i_reg[64]\(0)
);
\gpr1.dout_i_reg[10]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => p_0_out(10),
Q => \goreg_dm.dout_i_reg[64]\(10)
);
\gpr1.dout_i_reg[11]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => p_0_out(11),
Q => \goreg_dm.dout_i_reg[64]\(11)
);
\gpr1.dout_i_reg[12]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => p_0_out(12),
Q => \goreg_dm.dout_i_reg[64]\(12)
);
\gpr1.dout_i_reg[13]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => p_0_out(13),
Q => \goreg_dm.dout_i_reg[64]\(13)
);
\gpr1.dout_i_reg[14]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => p_0_out(14),
Q => \goreg_dm.dout_i_reg[64]\(14)
);
\gpr1.dout_i_reg[15]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => p_0_out(15),
Q => \goreg_dm.dout_i_reg[64]\(15)
);
\gpr1.dout_i_reg[16]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => p_0_out(16),
Q => \goreg_dm.dout_i_reg[64]\(16)
);
\gpr1.dout_i_reg[17]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => p_0_out(17),
Q => \goreg_dm.dout_i_reg[64]\(17)
);
\gpr1.dout_i_reg[18]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => p_0_out(18),
Q => \goreg_dm.dout_i_reg[64]\(18)
);
\gpr1.dout_i_reg[19]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => p_0_out(19),
Q => \goreg_dm.dout_i_reg[64]\(19)
);
\gpr1.dout_i_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => p_0_out(1),
Q => \goreg_dm.dout_i_reg[64]\(1)
);
\gpr1.dout_i_reg[20]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => p_0_out(20),
Q => \goreg_dm.dout_i_reg[64]\(20)
);
\gpr1.dout_i_reg[21]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => p_0_out(21),
Q => \goreg_dm.dout_i_reg[64]\(21)
);
\gpr1.dout_i_reg[22]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => p_0_out(22),
Q => \goreg_dm.dout_i_reg[64]\(22)
);
\gpr1.dout_i_reg[23]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => p_0_out(23),
Q => \goreg_dm.dout_i_reg[64]\(23)
);
\gpr1.dout_i_reg[24]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => p_0_out(24),
Q => \goreg_dm.dout_i_reg[64]\(24)
);
\gpr1.dout_i_reg[25]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => p_0_out(25),
Q => \goreg_dm.dout_i_reg[64]\(25)
);
\gpr1.dout_i_reg[26]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => p_0_out(26),
Q => \goreg_dm.dout_i_reg[64]\(26)
);
\gpr1.dout_i_reg[27]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => p_0_out(27),
Q => \goreg_dm.dout_i_reg[64]\(27)
);
\gpr1.dout_i_reg[28]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => p_0_out(28),
Q => \goreg_dm.dout_i_reg[64]\(28)
);
\gpr1.dout_i_reg[29]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => p_0_out(29),
Q => \goreg_dm.dout_i_reg[64]\(29)
);
\gpr1.dout_i_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => p_0_out(2),
Q => \goreg_dm.dout_i_reg[64]\(2)
);
\gpr1.dout_i_reg[30]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => p_0_out(30),
Q => \goreg_dm.dout_i_reg[64]\(30)
);
\gpr1.dout_i_reg[31]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => p_0_out(31),
Q => \goreg_dm.dout_i_reg[64]\(31)
);
\gpr1.dout_i_reg[32]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => p_0_out(32),
Q => \goreg_dm.dout_i_reg[64]\(32)
);
\gpr1.dout_i_reg[33]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => p_0_out(33),
Q => \goreg_dm.dout_i_reg[64]\(33)
);
\gpr1.dout_i_reg[34]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => p_0_out(34),
Q => \goreg_dm.dout_i_reg[64]\(34)
);
\gpr1.dout_i_reg[35]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => p_0_out(35),
Q => \goreg_dm.dout_i_reg[64]\(35)
);
\gpr1.dout_i_reg[36]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => p_0_out(36),
Q => \goreg_dm.dout_i_reg[64]\(36)
);
\gpr1.dout_i_reg[37]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => p_0_out(37),
Q => \goreg_dm.dout_i_reg[64]\(37)
);
\gpr1.dout_i_reg[38]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => p_0_out(38),
Q => \goreg_dm.dout_i_reg[64]\(38)
);
\gpr1.dout_i_reg[39]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => p_0_out(39),
Q => \goreg_dm.dout_i_reg[64]\(39)
);
\gpr1.dout_i_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => p_0_out(3),
Q => \goreg_dm.dout_i_reg[64]\(3)
);
\gpr1.dout_i_reg[40]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => p_0_out(40),
Q => \goreg_dm.dout_i_reg[64]\(40)
);
\gpr1.dout_i_reg[41]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => p_0_out(41),
Q => \goreg_dm.dout_i_reg[64]\(41)
);
\gpr1.dout_i_reg[42]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => p_0_out(42),
Q => \goreg_dm.dout_i_reg[64]\(42)
);
\gpr1.dout_i_reg[43]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => p_0_out(43),
Q => \goreg_dm.dout_i_reg[64]\(43)
);
\gpr1.dout_i_reg[44]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => p_0_out(44),
Q => \goreg_dm.dout_i_reg[64]\(44)
);
\gpr1.dout_i_reg[45]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => p_0_out(45),
Q => \goreg_dm.dout_i_reg[64]\(45)
);
\gpr1.dout_i_reg[46]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => p_0_out(46),
Q => \goreg_dm.dout_i_reg[64]\(46)
);
\gpr1.dout_i_reg[47]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => p_0_out(47),
Q => \goreg_dm.dout_i_reg[64]\(47)
);
\gpr1.dout_i_reg[48]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => p_0_out(48),
Q => \goreg_dm.dout_i_reg[64]\(48)
);
\gpr1.dout_i_reg[49]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => p_0_out(49),
Q => \goreg_dm.dout_i_reg[64]\(49)
);
\gpr1.dout_i_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => p_0_out(4),
Q => \goreg_dm.dout_i_reg[64]\(4)
);
\gpr1.dout_i_reg[50]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => p_0_out(50),
Q => \goreg_dm.dout_i_reg[64]\(50)
);
\gpr1.dout_i_reg[51]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => p_0_out(51),
Q => \goreg_dm.dout_i_reg[64]\(51)
);
\gpr1.dout_i_reg[52]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => p_0_out(52),
Q => \goreg_dm.dout_i_reg[64]\(52)
);
\gpr1.dout_i_reg[53]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => p_0_out(53),
Q => \goreg_dm.dout_i_reg[64]\(53)
);
\gpr1.dout_i_reg[54]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => p_0_out(54),
Q => \goreg_dm.dout_i_reg[64]\(54)
);
\gpr1.dout_i_reg[55]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => p_0_out(55),
Q => \goreg_dm.dout_i_reg[64]\(55)
);
\gpr1.dout_i_reg[56]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => p_0_out(56),
Q => \goreg_dm.dout_i_reg[64]\(56)
);
\gpr1.dout_i_reg[57]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => p_0_out(57),
Q => \goreg_dm.dout_i_reg[64]\(57)
);
\gpr1.dout_i_reg[58]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => p_0_out(58),
Q => \goreg_dm.dout_i_reg[64]\(58)
);
\gpr1.dout_i_reg[59]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => p_0_out(59),
Q => \goreg_dm.dout_i_reg[64]\(59)
);
\gpr1.dout_i_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => p_0_out(5),
Q => \goreg_dm.dout_i_reg[64]\(5)
);
\gpr1.dout_i_reg[60]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => p_0_out(60),
Q => \goreg_dm.dout_i_reg[64]\(60)
);
\gpr1.dout_i_reg[61]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => p_0_out(61),
Q => \goreg_dm.dout_i_reg[64]\(61)
);
\gpr1.dout_i_reg[62]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => p_0_out(62),
Q => \goreg_dm.dout_i_reg[64]\(62)
);
\gpr1.dout_i_reg[63]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => p_0_out(63),
Q => \goreg_dm.dout_i_reg[64]\(63)
);
\gpr1.dout_i_reg[64]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => p_0_out(64),
Q => \goreg_dm.dout_i_reg[64]\(64)
);
\gpr1.dout_i_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => p_0_out(6),
Q => \goreg_dm.dout_i_reg[64]\(6)
);
\gpr1.dout_i_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => p_0_out(7),
Q => \goreg_dm.dout_i_reg[64]\(7)
);
\gpr1.dout_i_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => p_0_out(8),
Q => \goreg_dm.dout_i_reg[64]\(8)
);
\gpr1.dout_i_reg[9]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => p_0_out(9),
Q => \goreg_dm.dout_i_reg[64]\(9)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_bin_cntr is
port (
Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gpr1.dout_i_reg[1]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
clk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_bin_cntr;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_bin_cntr is
signal \^q\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal plusOp : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gc0.count[2]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \gc0.count[3]_i_1\ : label is "soft_lutpair0";
begin
Q(3 downto 0) <= \^q\(3 downto 0);
\gc0.count[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^q\(0),
O => plusOp(0)
);
\gc0.count[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
O => plusOp(1)
);
\gc0.count[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
I2 => \^q\(2),
O => plusOp(2)
);
\gc0.count[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \^q\(1),
I1 => \^q\(0),
I2 => \^q\(2),
I3 => \^q\(3),
O => plusOp(3)
);
\gc0.count_d1_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => \^q\(0),
Q => \gpr1.dout_i_reg[1]\(0)
);
\gc0.count_d1_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => \^q\(1),
Q => \gpr1.dout_i_reg[1]\(1)
);
\gc0.count_d1_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => \^q\(2),
Q => \gpr1.dout_i_reg[1]\(2)
);
\gc0.count_d1_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => \^q\(3),
Q => \gpr1.dout_i_reg[1]\(3)
);
\gc0.count_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => E(0),
D => plusOp(0),
PRE => AR(0),
Q => \^q\(0)
);
\gc0.count_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => plusOp(1),
Q => \^q\(1)
);
\gc0.count_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => plusOp(2),
Q => \^q\(2)
);
\gc0.count_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => plusOp(3),
Q => \^q\(3)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_fwft is
port (
empty : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\gc0.count_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\goreg_dm.dout_i_reg[64]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
clk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 );
rd_en : in STD_LOGIC;
\out\ : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_fwft;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_fwft is
signal aempty_fwft_fb_i : STD_LOGIC;
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of aempty_fwft_fb_i : signal is std.standard.true;
signal aempty_fwft_i : STD_LOGIC;
attribute DONT_TOUCH of aempty_fwft_i : signal is std.standard.true;
signal aempty_fwft_i0 : STD_LOGIC;
signal curr_fwft_state : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute DONT_TOUCH of curr_fwft_state : signal is std.standard.true;
signal empty_fwft_fb_i : STD_LOGIC;
attribute DONT_TOUCH of empty_fwft_fb_i : signal is std.standard.true;
signal empty_fwft_fb_o_i : STD_LOGIC;
attribute DONT_TOUCH of empty_fwft_fb_o_i : signal is std.standard.true;
signal empty_fwft_fb_o_i0 : STD_LOGIC;
signal empty_fwft_i : STD_LOGIC;
attribute DONT_TOUCH of empty_fwft_i : signal is std.standard.true;
signal empty_fwft_i0 : STD_LOGIC;
signal next_fwft_state : STD_LOGIC_VECTOR ( 1 downto 0 );
signal user_valid : STD_LOGIC;
attribute DONT_TOUCH of user_valid : signal is std.standard.true;
attribute DONT_TOUCH of aempty_fwft_fb_i_reg : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of aempty_fwft_fb_i_reg : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of aempty_fwft_fb_i_reg : label is "no";
attribute DONT_TOUCH of aempty_fwft_i_reg : label is std.standard.true;
attribute KEEP of aempty_fwft_i_reg : label is "yes";
attribute equivalent_register_removal of aempty_fwft_i_reg : label is "no";
attribute DONT_TOUCH of empty_fwft_fb_i_reg : label is std.standard.true;
attribute KEEP of empty_fwft_fb_i_reg : label is "yes";
attribute equivalent_register_removal of empty_fwft_fb_i_reg : label is "no";
attribute DONT_TOUCH of empty_fwft_fb_o_i_reg : label is std.standard.true;
attribute KEEP of empty_fwft_fb_o_i_reg : label is "yes";
attribute equivalent_register_removal of empty_fwft_fb_o_i_reg : label is "no";
attribute DONT_TOUCH of empty_fwft_i_reg : label is std.standard.true;
attribute KEEP of empty_fwft_i_reg : label is "yes";
attribute equivalent_register_removal of empty_fwft_i_reg : label is "no";
attribute DONT_TOUCH of \gpregsm1.curr_fwft_state_reg[0]\ : label is std.standard.true;
attribute KEEP of \gpregsm1.curr_fwft_state_reg[0]\ : label is "yes";
attribute equivalent_register_removal of \gpregsm1.curr_fwft_state_reg[0]\ : label is "no";
attribute DONT_TOUCH of \gpregsm1.curr_fwft_state_reg[1]\ : label is std.standard.true;
attribute KEEP of \gpregsm1.curr_fwft_state_reg[1]\ : label is "yes";
attribute equivalent_register_removal of \gpregsm1.curr_fwft_state_reg[1]\ : label is "no";
attribute DONT_TOUCH of \gpregsm1.user_valid_reg\ : label is std.standard.true;
attribute KEEP of \gpregsm1.user_valid_reg\ : label is "yes";
attribute equivalent_register_removal of \gpregsm1.user_valid_reg\ : label is "no";
begin
empty <= empty_fwft_i;
aempty_fwft_fb_i_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"EEFD8000"
)
port map (
I0 => curr_fwft_state(0),
I1 => \out\,
I2 => rd_en,
I3 => curr_fwft_state(1),
I4 => aempty_fwft_fb_i,
O => aempty_fwft_i0
);
aempty_fwft_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => aempty_fwft_i0,
PRE => AR(0),
Q => aempty_fwft_fb_i
);
aempty_fwft_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => aempty_fwft_i0,
PRE => AR(0),
Q => aempty_fwft_i
);
empty_fwft_fb_i_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"F320"
)
port map (
I0 => rd_en,
I1 => curr_fwft_state(1),
I2 => curr_fwft_state(0),
I3 => empty_fwft_fb_i,
O => empty_fwft_i0
);
empty_fwft_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => empty_fwft_i0,
PRE => AR(0),
Q => empty_fwft_fb_i
);
empty_fwft_fb_o_i_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"F320"
)
port map (
I0 => rd_en,
I1 => curr_fwft_state(1),
I2 => curr_fwft_state(0),
I3 => empty_fwft_fb_o_i,
O => empty_fwft_fb_o_i0
);
empty_fwft_fb_o_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => empty_fwft_fb_o_i0,
PRE => AR(0),
Q => empty_fwft_fb_o_i
);
empty_fwft_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => empty_fwft_i0,
PRE => AR(0),
Q => empty_fwft_i
);
\gc0.count_d1[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"00BF"
)
port map (
I0 => rd_en,
I1 => curr_fwft_state(0),
I2 => curr_fwft_state(1),
I3 => \out\,
O => \gc0.count_reg[0]\(0)
);
\goreg_dm.dout_i[64]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"A2"
)
port map (
I0 => curr_fwft_state(1),
I1 => curr_fwft_state(0),
I2 => rd_en,
O => \goreg_dm.dout_i_reg[64]\(0)
);
\gpr1.dout_i[64]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"00F7"
)
port map (
I0 => curr_fwft_state(1),
I1 => curr_fwft_state(0),
I2 => rd_en,
I3 => \out\,
O => E(0)
);
\gpregsm1.curr_fwft_state[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"BA"
)
port map (
I0 => curr_fwft_state(1),
I1 => rd_en,
I2 => curr_fwft_state(0),
O => next_fwft_state(0)
);
\gpregsm1.curr_fwft_state[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"20FF"
)
port map (
I0 => curr_fwft_state(1),
I1 => rd_en,
I2 => curr_fwft_state(0),
I3 => \out\,
O => next_fwft_state(1)
);
\gpregsm1.curr_fwft_state_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
CLR => AR(0),
D => next_fwft_state(0),
Q => curr_fwft_state(0)
);
\gpregsm1.curr_fwft_state_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
CLR => AR(0),
D => next_fwft_state(1),
Q => curr_fwft_state(1)
);
\gpregsm1.user_valid_reg\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
CLR => AR(0),
D => next_fwft_state(0),
Q => user_valid
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_status_flags_ss is
port (
\out\ : out STD_LOGIC;
ram_empty_fb_i_reg_0 : in STD_LOGIC;
clk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_status_flags_ss;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_status_flags_ss is
signal ram_empty_fb_i : STD_LOGIC;
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of ram_empty_fb_i : signal is std.standard.true;
signal ram_empty_i : STD_LOGIC;
attribute DONT_TOUCH of ram_empty_i : signal is std.standard.true;
attribute DONT_TOUCH of ram_empty_fb_i_reg : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of ram_empty_fb_i_reg : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of ram_empty_fb_i_reg : label is "no";
attribute DONT_TOUCH of ram_empty_i_reg : label is std.standard.true;
attribute KEEP of ram_empty_i_reg : label is "yes";
attribute equivalent_register_removal of ram_empty_i_reg : label is "no";
begin
\out\ <= ram_empty_fb_i;
ram_empty_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => ram_empty_fb_i_reg_0,
PRE => AR(0),
Q => ram_empty_fb_i
);
ram_empty_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => ram_empty_fb_i_reg_0,
PRE => AR(0),
Q => ram_empty_i
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff is
port (
\out\ : out STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg\ : out STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 );
clk : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\out\ <= Q_reg;
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => in0(0),
Q => Q_reg,
R => '0'
);
\ngwrdrst.grst.g7serrst.rd_rst_asreg_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => in0(0),
I1 => Q_reg,
O => \ngwrdrst.grst.g7serrst.rd_rst_asreg_reg\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_0 is
port (
\out\ : out STD_LOGIC;
\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg\ : out STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 );
clk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_0 : entity is "synchronizer_ff";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_0;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_0 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\out\ <= Q_reg;
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => in0(0),
Q => Q_reg,
R => '0'
);
\ngwrdrst.grst.g7serrst.wr_rst_asreg_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => in0(0),
I1 => Q_reg,
O => \ngwrdrst.grst.g7serrst.wr_rst_asreg_reg\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_1 is
port (
AS : out STD_LOGIC_VECTOR ( 0 to 0 );
\out\ : in STD_LOGIC;
clk : in STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_1 : entity is "synchronizer_ff";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_1;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_1 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => \out\,
Q => Q_reg,
R => '0'
);
\ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => in0(0),
I1 => Q_reg,
O => AS(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_2 is
port (
AS : out STD_LOGIC_VECTOR ( 0 to 0 );
\out\ : in STD_LOGIC;
clk : in STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_2 : entity is "synchronizer_ff";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_2;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_2 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => \out\,
Q => Q_reg,
R => '0'
);
\ngwrdrst.grst.g7serrst.wr_rst_reg[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => in0(0),
I1 => Q_reg,
O => AS(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_bin_cntr is
port (
p_2_out : out STD_LOGIC;
ram_full_comb : out STD_LOGIC;
ram_empty_i_reg : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
almost_full : in STD_LOGIC;
p_7_out : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
wr_rst_busy : in STD_LOGIC;
wr_en : in STD_LOGIC;
\out\ : in STD_LOGIC;
ram_empty_fb_i_reg : in STD_LOGIC;
\gc0.count_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gc0.count_d1_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
clk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_bin_cntr;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_bin_cntr is
signal \^q\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \gaf.gaf0.ram_afull_i_i_3_n_0\ : STD_LOGIC;
signal \gwss.wsts/comp0\ : STD_LOGIC;
signal \gwss.wsts/comp1\ : STD_LOGIC;
signal \gwss.wsts/p_0_in\ : STD_LOGIC;
signal p_12_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \plusOp__0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal ram_empty_fb_i_i_3_n_0 : STD_LOGIC;
signal ram_empty_fb_i_i_4_n_0 : STD_LOGIC;
signal ram_empty_fb_i_i_5_n_0 : STD_LOGIC;
signal ram_full_fb_i_i_3_n_0 : STD_LOGIC;
signal wr_pntr_plus2 : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gaf.gaf0.ram_afull_i_i_3\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \gcc0.gc1.gsym.count[1]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \gcc0.gc1.gsym.count[2]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \gcc0.gc1.gsym.count[3]_i_1\ : label is "soft_lutpair2";
begin
Q(3 downto 0) <= \^q\(3 downto 0);
\gaf.gaf0.ram_afull_i_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00AA0000CCEE0CCC"
)
port map (
I0 => \gwss.wsts/p_0_in\,
I1 => almost_full,
I2 => \gwss.wsts/comp1\,
I3 => p_7_out,
I4 => E(0),
I5 => wr_rst_busy,
O => p_2_out
);
\gaf.gaf0.ram_afull_i_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"00009009"
)
port map (
I0 => \gc0.count_d1_reg[3]\(3),
I1 => wr_pntr_plus2(3),
I2 => \gc0.count_d1_reg[3]\(2),
I3 => wr_pntr_plus2(2),
I4 => \gaf.gaf0.ram_afull_i_i_3_n_0\,
O => \gwss.wsts/p_0_in\
);
\gaf.gaf0.ram_afull_i_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"6FF6"
)
port map (
I0 => wr_pntr_plus2(1),
I1 => \gc0.count_d1_reg[3]\(1),
I2 => wr_pntr_plus2(0),
I3 => \gc0.count_d1_reg[3]\(0),
O => \gaf.gaf0.ram_afull_i_i_3_n_0\
);
\gcc0.gc1.gsym.count[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => wr_pntr_plus2(0),
O => \plusOp__0\(0)
);
\gcc0.gc1.gsym.count[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => wr_pntr_plus2(0),
I1 => wr_pntr_plus2(1),
O => \plusOp__0\(1)
);
\gcc0.gc1.gsym.count[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => wr_pntr_plus2(0),
I1 => wr_pntr_plus2(1),
I2 => wr_pntr_plus2(2),
O => \plusOp__0\(2)
);
\gcc0.gc1.gsym.count[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => wr_pntr_plus2(1),
I1 => wr_pntr_plus2(0),
I2 => wr_pntr_plus2(2),
I3 => wr_pntr_plus2(3),
O => \plusOp__0\(3)
);
\gcc0.gc1.gsym.count_d1_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => E(0),
D => wr_pntr_plus2(0),
PRE => AR(0),
Q => p_12_out(0)
);
\gcc0.gc1.gsym.count_d1_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => wr_pntr_plus2(1),
Q => p_12_out(1)
);
\gcc0.gc1.gsym.count_d1_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => wr_pntr_plus2(2),
Q => p_12_out(2)
);
\gcc0.gc1.gsym.count_d1_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => wr_pntr_plus2(3),
Q => p_12_out(3)
);
\gcc0.gc1.gsym.count_d2_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => p_12_out(0),
Q => \^q\(0)
);
\gcc0.gc1.gsym.count_d2_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => p_12_out(1),
Q => \^q\(1)
);
\gcc0.gc1.gsym.count_d2_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => p_12_out(2),
Q => \^q\(2)
);
\gcc0.gc1.gsym.count_d2_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => p_12_out(3),
Q => \^q\(3)
);
\gcc0.gc1.gsym.count_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__0\(0),
Q => wr_pntr_plus2(0)
);
\gcc0.gc1.gsym.count_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => E(0),
D => \plusOp__0\(1),
PRE => AR(0),
Q => wr_pntr_plus2(1)
);
\gcc0.gc1.gsym.count_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__0\(2),
Q => wr_pntr_plus2(2)
);
\gcc0.gc1.gsym.count_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__0\(3),
Q => wr_pntr_plus2(3)
);
ram_empty_fb_i_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"FCFC44FC"
)
port map (
I0 => \gwss.wsts/comp0\,
I1 => ram_empty_fb_i_reg,
I2 => ram_empty_fb_i_i_3_n_0,
I3 => wr_en,
I4 => \out\,
O => ram_empty_i_reg
);
ram_empty_fb_i_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"00009009"
)
port map (
I0 => \gc0.count_d1_reg[3]\(3),
I1 => \^q\(3),
I2 => \gc0.count_d1_reg[3]\(2),
I3 => \^q\(2),
I4 => ram_empty_fb_i_i_4_n_0,
O => \gwss.wsts/comp0\
);
ram_empty_fb_i_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"4100004100000000"
)
port map (
I0 => ram_empty_fb_i_i_5_n_0,
I1 => \^q\(2),
I2 => \gc0.count_reg[3]\(2),
I3 => \^q\(3),
I4 => \gc0.count_reg[3]\(3),
I5 => p_7_out,
O => ram_empty_fb_i_i_3_n_0
);
ram_empty_fb_i_i_4: unisim.vcomponents.LUT4
generic map(
INIT => X"6FF6"
)
port map (
I0 => \^q\(1),
I1 => \gc0.count_d1_reg[3]\(1),
I2 => \^q\(0),
I3 => \gc0.count_d1_reg[3]\(0),
O => ram_empty_fb_i_i_4_n_0
);
ram_empty_fb_i_i_5: unisim.vcomponents.LUT4
generic map(
INIT => X"6FF6"
)
port map (
I0 => \^q\(1),
I1 => \gc0.count_reg[3]\(1),
I2 => \^q\(0),
I3 => \gc0.count_reg[3]\(0),
O => ram_empty_fb_i_i_5_n_0
);
ram_full_fb_i_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"0008000800F8F0F8"
)
port map (
I0 => \gwss.wsts/comp1\,
I1 => wr_en,
I2 => \out\,
I3 => p_7_out,
I4 => \gwss.wsts/comp0\,
I5 => wr_rst_busy,
O => ram_full_comb
);
ram_full_fb_i_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"00009009"
)
port map (
I0 => \gc0.count_d1_reg[3]\(3),
I1 => p_12_out(3),
I2 => \gc0.count_d1_reg[3]\(2),
I3 => p_12_out(2),
I4 => ram_full_fb_i_i_3_n_0,
O => \gwss.wsts/comp1\
);
ram_full_fb_i_i_3: unisim.vcomponents.LUT4
generic map(
INIT => X"6FF6"
)
port map (
I0 => p_12_out(1),
I1 => \gc0.count_d1_reg[3]\(1),
I2 => p_12_out(0),
I3 => \gc0.count_d1_reg[3]\(0),
O => ram_full_fb_i_i_3_n_0
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_status_flags_ss is
port (
\out\ : out STD_LOGIC;
full : out STD_LOGIC;
almost_full : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
ram_full_comb : in STD_LOGIC;
clk : in STD_LOGIC;
\grstd1.grst_full.grst_f.rst_d2_reg\ : in STD_LOGIC;
p_2_out : in STD_LOGIC;
wr_en : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_status_flags_ss;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_status_flags_ss is
signal p_15_out : STD_LOGIC;
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of p_15_out : signal is std.standard.true;
signal ram_afull_i : STD_LOGIC;
attribute DONT_TOUCH of ram_afull_i : signal is std.standard.true;
signal ram_full_fb_i : STD_LOGIC;
attribute DONT_TOUCH of ram_full_fb_i : signal is std.standard.true;
signal ram_full_i : STD_LOGIC;
attribute DONT_TOUCH of ram_full_i : signal is std.standard.true;
attribute DONT_TOUCH of \gaf.gaf0.ram_afull_i_reg\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \gaf.gaf0.ram_afull_i_reg\ : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of \gaf.gaf0.ram_afull_i_reg\ : label is "no";
attribute DONT_TOUCH of ram_full_fb_i_reg : label is std.standard.true;
attribute KEEP of ram_full_fb_i_reg : label is "yes";
attribute equivalent_register_removal of ram_full_fb_i_reg : label is "no";
attribute DONT_TOUCH of ram_full_i_reg : label is std.standard.true;
attribute KEEP of ram_full_i_reg : label is "yes";
attribute equivalent_register_removal of ram_full_i_reg : label is "no";
begin
almost_full <= ram_afull_i;
full <= ram_full_i;
\out\ <= ram_full_fb_i;
\gaf.gaf0.ram_afull_i_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => p_2_out,
PRE => \grstd1.grst_full.grst_f.rst_d2_reg\,
Q => ram_afull_i
);
\gcc0.gc1.gsym.count_d1[3]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => wr_en,
I1 => ram_full_fb_i,
O => E(0)
);
i_0: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => p_15_out
);
ram_full_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => ram_full_comb,
PRE => \grstd1.grst_full.grst_f.rst_d2_reg\,
Q => ram_full_fb_i
);
ram_full_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => ram_full_comb,
PRE => \grstd1.grst_full.grst_f.rst_d2_reg\,
Q => ram_full_i
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_memory is
port (
dout : out STD_LOGIC_VECTOR ( 64 downto 0 );
clk : in STD_LOGIC;
EN : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 64 downto 0 );
\gc0.count_d1_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
AR : in STD_LOGIC_VECTOR ( 0 to 0 );
\gpregsm1.curr_fwft_state_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_memory;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_memory is
signal dout_i : STD_LOGIC_VECTOR ( 64 downto 0 );
begin
\gdm.dm_gen.dm\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dmem
port map (
AR(0) => AR(0),
E(0) => E(0),
EN => EN,
Q(3 downto 0) => Q(3 downto 0),
clk => clk,
din(64 downto 0) => din(64 downto 0),
\gc0.count_d1_reg[3]\(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
\goreg_dm.dout_i_reg[64]\(64 downto 0) => dout_i(64 downto 0)
);
\goreg_dm.dout_i_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
CLR => AR(0),
D => dout_i(0),
Q => dout(0)
);
\goreg_dm.dout_i_reg[10]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
CLR => AR(0),
D => dout_i(10),
Q => dout(10)
);
\goreg_dm.dout_i_reg[11]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
CLR => AR(0),
D => dout_i(11),
Q => dout(11)
);
\goreg_dm.dout_i_reg[12]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
CLR => AR(0),
D => dout_i(12),
Q => dout(12)
);
\goreg_dm.dout_i_reg[13]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
CLR => AR(0),
D => dout_i(13),
Q => dout(13)
);
\goreg_dm.dout_i_reg[14]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
CLR => AR(0),
D => dout_i(14),
Q => dout(14)
);
\goreg_dm.dout_i_reg[15]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
CLR => AR(0),
D => dout_i(15),
Q => dout(15)
);
\goreg_dm.dout_i_reg[16]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
CLR => AR(0),
D => dout_i(16),
Q => dout(16)
);
\goreg_dm.dout_i_reg[17]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
CLR => AR(0),
D => dout_i(17),
Q => dout(17)
);
\goreg_dm.dout_i_reg[18]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
CLR => AR(0),
D => dout_i(18),
Q => dout(18)
);
\goreg_dm.dout_i_reg[19]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
CLR => AR(0),
D => dout_i(19),
Q => dout(19)
);
\goreg_dm.dout_i_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
CLR => AR(0),
D => dout_i(1),
Q => dout(1)
);
\goreg_dm.dout_i_reg[20]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
CLR => AR(0),
D => dout_i(20),
Q => dout(20)
);
\goreg_dm.dout_i_reg[21]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
CLR => AR(0),
D => dout_i(21),
Q => dout(21)
);
\goreg_dm.dout_i_reg[22]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
CLR => AR(0),
D => dout_i(22),
Q => dout(22)
);
\goreg_dm.dout_i_reg[23]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
CLR => AR(0),
D => dout_i(23),
Q => dout(23)
);
\goreg_dm.dout_i_reg[24]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
CLR => AR(0),
D => dout_i(24),
Q => dout(24)
);
\goreg_dm.dout_i_reg[25]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
CLR => AR(0),
D => dout_i(25),
Q => dout(25)
);
\goreg_dm.dout_i_reg[26]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
CLR => AR(0),
D => dout_i(26),
Q => dout(26)
);
\goreg_dm.dout_i_reg[27]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
CLR => AR(0),
D => dout_i(27),
Q => dout(27)
);
\goreg_dm.dout_i_reg[28]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
CLR => AR(0),
D => dout_i(28),
Q => dout(28)
);
\goreg_dm.dout_i_reg[29]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
CLR => AR(0),
D => dout_i(29),
Q => dout(29)
);
\goreg_dm.dout_i_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
CLR => AR(0),
D => dout_i(2),
Q => dout(2)
);
\goreg_dm.dout_i_reg[30]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
CLR => AR(0),
D => dout_i(30),
Q => dout(30)
);
\goreg_dm.dout_i_reg[31]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
CLR => AR(0),
D => dout_i(31),
Q => dout(31)
);
\goreg_dm.dout_i_reg[32]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
CLR => AR(0),
D => dout_i(32),
Q => dout(32)
);
\goreg_dm.dout_i_reg[33]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
CLR => AR(0),
D => dout_i(33),
Q => dout(33)
);
\goreg_dm.dout_i_reg[34]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
CLR => AR(0),
D => dout_i(34),
Q => dout(34)
);
\goreg_dm.dout_i_reg[35]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
CLR => AR(0),
D => dout_i(35),
Q => dout(35)
);
\goreg_dm.dout_i_reg[36]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
CLR => AR(0),
D => dout_i(36),
Q => dout(36)
);
\goreg_dm.dout_i_reg[37]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
CLR => AR(0),
D => dout_i(37),
Q => dout(37)
);
\goreg_dm.dout_i_reg[38]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
CLR => AR(0),
D => dout_i(38),
Q => dout(38)
);
\goreg_dm.dout_i_reg[39]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
CLR => AR(0),
D => dout_i(39),
Q => dout(39)
);
\goreg_dm.dout_i_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
CLR => AR(0),
D => dout_i(3),
Q => dout(3)
);
\goreg_dm.dout_i_reg[40]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
CLR => AR(0),
D => dout_i(40),
Q => dout(40)
);
\goreg_dm.dout_i_reg[41]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
CLR => AR(0),
D => dout_i(41),
Q => dout(41)
);
\goreg_dm.dout_i_reg[42]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
CLR => AR(0),
D => dout_i(42),
Q => dout(42)
);
\goreg_dm.dout_i_reg[43]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
CLR => AR(0),
D => dout_i(43),
Q => dout(43)
);
\goreg_dm.dout_i_reg[44]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
CLR => AR(0),
D => dout_i(44),
Q => dout(44)
);
\goreg_dm.dout_i_reg[45]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
CLR => AR(0),
D => dout_i(45),
Q => dout(45)
);
\goreg_dm.dout_i_reg[46]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
CLR => AR(0),
D => dout_i(46),
Q => dout(46)
);
\goreg_dm.dout_i_reg[47]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
CLR => AR(0),
D => dout_i(47),
Q => dout(47)
);
\goreg_dm.dout_i_reg[48]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
CLR => AR(0),
D => dout_i(48),
Q => dout(48)
);
\goreg_dm.dout_i_reg[49]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
CLR => AR(0),
D => dout_i(49),
Q => dout(49)
);
\goreg_dm.dout_i_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
CLR => AR(0),
D => dout_i(4),
Q => dout(4)
);
\goreg_dm.dout_i_reg[50]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
CLR => AR(0),
D => dout_i(50),
Q => dout(50)
);
\goreg_dm.dout_i_reg[51]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
CLR => AR(0),
D => dout_i(51),
Q => dout(51)
);
\goreg_dm.dout_i_reg[52]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
CLR => AR(0),
D => dout_i(52),
Q => dout(52)
);
\goreg_dm.dout_i_reg[53]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
CLR => AR(0),
D => dout_i(53),
Q => dout(53)
);
\goreg_dm.dout_i_reg[54]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
CLR => AR(0),
D => dout_i(54),
Q => dout(54)
);
\goreg_dm.dout_i_reg[55]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
CLR => AR(0),
D => dout_i(55),
Q => dout(55)
);
\goreg_dm.dout_i_reg[56]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
CLR => AR(0),
D => dout_i(56),
Q => dout(56)
);
\goreg_dm.dout_i_reg[57]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
CLR => AR(0),
D => dout_i(57),
Q => dout(57)
);
\goreg_dm.dout_i_reg[58]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
CLR => AR(0),
D => dout_i(58),
Q => dout(58)
);
\goreg_dm.dout_i_reg[59]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
CLR => AR(0),
D => dout_i(59),
Q => dout(59)
);
\goreg_dm.dout_i_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
CLR => AR(0),
D => dout_i(5),
Q => dout(5)
);
\goreg_dm.dout_i_reg[60]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
CLR => AR(0),
D => dout_i(60),
Q => dout(60)
);
\goreg_dm.dout_i_reg[61]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
CLR => AR(0),
D => dout_i(61),
Q => dout(61)
);
\goreg_dm.dout_i_reg[62]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
CLR => AR(0),
D => dout_i(62),
Q => dout(62)
);
\goreg_dm.dout_i_reg[63]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
CLR => AR(0),
D => dout_i(63),
Q => dout(63)
);
\goreg_dm.dout_i_reg[64]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
CLR => AR(0),
D => dout_i(64),
Q => dout(64)
);
\goreg_dm.dout_i_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
CLR => AR(0),
D => dout_i(6),
Q => dout(6)
);
\goreg_dm.dout_i_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
CLR => AR(0),
D => dout_i(7),
Q => dout(7)
);
\goreg_dm.dout_i_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
CLR => AR(0),
D => dout_i(8),
Q => dout(8)
);
\goreg_dm.dout_i_reg[9]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
CLR => AR(0),
D => dout_i(9),
Q => dout(9)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_logic is
port (
\out\ : out STD_LOGIC;
empty : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
p_7_out : out STD_LOGIC;
\goreg_dm.dout_i_reg[64]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gpr1.dout_i_reg[1]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
ram_empty_fb_i_reg : in STD_LOGIC;
clk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 );
rd_en : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_logic;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_logic is
signal \^out\ : STD_LOGIC;
signal \^p_7_out\ : STD_LOGIC;
begin
\out\ <= \^out\;
p_7_out <= \^p_7_out\;
\gr1.gr1_int.rfwft\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_fwft
port map (
AR(0) => AR(0),
E(0) => E(0),
clk => clk,
empty => empty,
\gc0.count_reg[0]\(0) => \^p_7_out\,
\goreg_dm.dout_i_reg[64]\(0) => \goreg_dm.dout_i_reg[64]\(0),
\out\ => \^out\,
rd_en => rd_en
);
\grss.rsts\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_status_flags_ss
port map (
AR(0) => AR(0),
clk => clk,
\out\ => \^out\,
ram_empty_fb_i_reg_0 => ram_empty_fb_i_reg
);
rpntr: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_bin_cntr
port map (
AR(0) => AR(0),
E(0) => \^p_7_out\,
Q(3 downto 0) => Q(3 downto 0),
clk => clk,
\gpr1.dout_i_reg[1]\(3 downto 0) => \gpr1.dout_i_reg[1]\(3 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_reset_blk_ramfifo is
port (
\out\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gc0.count_reg[1]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
\grstd1.grst_full.grst_f.rst_d3_reg_0\ : out STD_LOGIC;
wr_rst_busy : out STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_reset_blk_ramfifo;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_reset_blk_ramfifo is
signal \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst_n_1\ : STD_LOGIC;
signal \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst_n_1\ : STD_LOGIC;
signal \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0\ : STD_LOGIC;
signal \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0\ : STD_LOGIC;
signal p_7_out : STD_LOGIC;
signal p_8_out : STD_LOGIC;
signal rd_rst_asreg : STD_LOGIC;
signal rd_rst_reg : STD_LOGIC_VECTOR ( 2 downto 0 );
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of rd_rst_reg : signal is std.standard.true;
signal rst_d1 : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of rst_d1 : signal is "true";
attribute msgon : string;
attribute msgon of rst_d1 : signal is "true";
signal rst_d2 : STD_LOGIC;
attribute async_reg of rst_d2 : signal is "true";
attribute msgon of rst_d2 : signal is "true";
signal rst_d3 : STD_LOGIC;
attribute async_reg of rst_d3 : signal is "true";
attribute msgon of rst_d3 : signal is "true";
signal rst_rd_reg1 : STD_LOGIC;
attribute async_reg of rst_rd_reg1 : signal is "true";
attribute msgon of rst_rd_reg1 : signal is "true";
signal rst_rd_reg2 : STD_LOGIC;
attribute async_reg of rst_rd_reg2 : signal is "true";
attribute msgon of rst_rd_reg2 : signal is "true";
signal rst_wr_reg1 : STD_LOGIC;
attribute async_reg of rst_wr_reg1 : signal is "true";
attribute msgon of rst_wr_reg1 : signal is "true";
signal rst_wr_reg2 : STD_LOGIC;
attribute async_reg of rst_wr_reg2 : signal is "true";
attribute msgon of rst_wr_reg2 : signal is "true";
signal wr_rst_asreg : STD_LOGIC;
signal wr_rst_reg : STD_LOGIC_VECTOR ( 2 downto 0 );
attribute DONT_TOUCH of wr_rst_reg : signal is std.standard.true;
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is "yes";
attribute msgon of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is "true";
attribute ASYNC_REG_boolean of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is std.standard.true;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is "yes";
attribute msgon of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is "true";
attribute ASYNC_REG_boolean of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is std.standard.true;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is "yes";
attribute msgon of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is "true";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : label is "no";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is "true";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\ : label is "no";
begin
\gc0.count_reg[1]\(1) <= rd_rst_reg(2);
\gc0.count_reg[1]\(0) <= rd_rst_reg(0);
\grstd1.grst_full.grst_f.rst_d3_reg_0\ <= rst_d2;
\out\(0) <= wr_rst_reg(1);
wr_rst_busy <= rst_d3;
\grstd1.grst_full.grst_f.rst_d1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => '0',
PRE => rst_wr_reg2,
Q => rst_d1
);
\grstd1.grst_full.grst_f.rst_d2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => rst_d1,
PRE => rst_wr_reg2,
Q => rst_d2
);
\grstd1.grst_full.grst_f.rst_d3_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => rst_d2,
PRE => rst_wr_reg2,
Q => rst_d3
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff
port map (
clk => clk,
in0(0) => rd_rst_asreg,
\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg\ => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst_n_1\,
\out\ => p_7_out
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_0
port map (
clk => clk,
in0(0) => wr_rst_asreg,
\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg\ => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst_n_1\,
\out\ => p_8_out
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_1
port map (
AS(0) => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0\,
clk => clk,
in0(0) => rd_rst_asreg,
\out\ => p_7_out
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_2
port map (
AS(0) => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0\,
clk => clk,
in0(0) => wr_rst_asreg,
\out\ => p_8_out
);
\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst_n_1\,
PRE => rst_rd_reg2,
Q => rd_rst_asreg
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0\,
Q => rd_rst_reg(0)
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0\,
Q => rd_rst_reg(1)
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0\,
Q => rd_rst_reg(2)
);
\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => '0',
PRE => rst,
Q => rst_rd_reg1
);
\ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => rst_rd_reg1,
PRE => rst,
Q => rst_rd_reg2
);
\ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => '0',
PRE => rst,
Q => rst_wr_reg1
);
\ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => rst_wr_reg1,
PRE => rst,
Q => rst_wr_reg2
);
\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst_n_1\,
PRE => rst_wr_reg2,
Q => wr_rst_asreg
);
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0\,
Q => wr_rst_reg(0)
);
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0\,
Q => wr_rst_reg(1)
);
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0\,
Q => wr_rst_reg(2)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_logic is
port (
full : out STD_LOGIC;
almost_full : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
ram_empty_i_reg : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
clk : in STD_LOGIC;
\out\ : in STD_LOGIC;
wr_en : in STD_LOGIC;
p_7_out : in STD_LOGIC;
wr_rst_busy : in STD_LOGIC;
ram_empty_fb_i_reg : in STD_LOGIC;
\gc0.count_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gc0.count_d1_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_logic;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_logic is
signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^almost_full\ : STD_LOGIC;
signal \gwss.wsts_n_0\ : STD_LOGIC;
signal p_2_out : STD_LOGIC;
signal ram_full_comb : STD_LOGIC;
begin
E(0) <= \^e\(0);
almost_full <= \^almost_full\;
\gwss.wsts\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_status_flags_ss
port map (
E(0) => \^e\(0),
almost_full => \^almost_full\,
clk => clk,
full => full,
\grstd1.grst_full.grst_f.rst_d2_reg\ => \out\,
\out\ => \gwss.wsts_n_0\,
p_2_out => p_2_out,
ram_full_comb => ram_full_comb,
wr_en => wr_en
);
wpntr: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_bin_cntr
port map (
AR(0) => AR(0),
E(0) => \^e\(0),
Q(3 downto 0) => Q(3 downto 0),
almost_full => \^almost_full\,
clk => clk,
\gc0.count_d1_reg[3]\(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
\gc0.count_reg[3]\(3 downto 0) => \gc0.count_reg[3]\(3 downto 0),
\out\ => \gwss.wsts_n_0\,
p_2_out => p_2_out,
p_7_out => p_7_out,
ram_empty_fb_i_reg => ram_empty_fb_i_reg,
ram_empty_i_reg => ram_empty_i_reg,
ram_full_comb => ram_full_comb,
wr_en => wr_en,
wr_rst_busy => wr_rst_busy
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_ramfifo is
port (
wr_rst_busy : out STD_LOGIC;
empty : out STD_LOGIC;
full : out STD_LOGIC;
almost_full : out STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 64 downto 0 );
rd_en : in STD_LOGIC;
wr_en : in STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 64 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_ramfifo;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_ramfifo is
signal \gntv_or_sync_fifo.gl0.rd_n_2\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.wr_n_2\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.wr_n_3\ : STD_LOGIC;
signal p_0_out_0 : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_11_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_2_out : STD_LOGIC;
signal p_5_out : STD_LOGIC;
signal p_7_out : STD_LOGIC;
signal rd_pntr_plus1 : STD_LOGIC_VECTOR ( 3 downto 0 );
signal rd_rst_i : STD_LOGIC_VECTOR ( 2 downto 0 );
signal rst_full_ff_i : STD_LOGIC;
signal \^wr_rst_busy\ : STD_LOGIC;
signal wr_rst_i : STD_LOGIC_VECTOR ( 1 to 1 );
begin
wr_rst_busy <= \^wr_rst_busy\;
\gntv_or_sync_fifo.gl0.rd\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_logic
port map (
AR(0) => rd_rst_i(2),
E(0) => \gntv_or_sync_fifo.gl0.rd_n_2\,
Q(3 downto 0) => rd_pntr_plus1(3 downto 0),
clk => clk,
empty => empty,
\goreg_dm.dout_i_reg[64]\(0) => p_5_out,
\gpr1.dout_i_reg[1]\(3 downto 0) => p_0_out_0(3 downto 0),
\out\ => p_2_out,
p_7_out => p_7_out,
ram_empty_fb_i_reg => \gntv_or_sync_fifo.gl0.wr_n_3\,
rd_en => rd_en
);
\gntv_or_sync_fifo.gl0.wr\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_logic
port map (
AR(0) => wr_rst_i(1),
E(0) => \gntv_or_sync_fifo.gl0.wr_n_2\,
Q(3 downto 0) => p_11_out(3 downto 0),
almost_full => almost_full,
clk => clk,
full => full,
\gc0.count_d1_reg[3]\(3 downto 0) => p_0_out_0(3 downto 0),
\gc0.count_reg[3]\(3 downto 0) => rd_pntr_plus1(3 downto 0),
\out\ => rst_full_ff_i,
p_7_out => p_7_out,
ram_empty_fb_i_reg => p_2_out,
ram_empty_i_reg => \gntv_or_sync_fifo.gl0.wr_n_3\,
wr_en => wr_en,
wr_rst_busy => \^wr_rst_busy\
);
\gntv_or_sync_fifo.mem\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_memory
port map (
AR(0) => rd_rst_i(0),
E(0) => \gntv_or_sync_fifo.gl0.rd_n_2\,
EN => \gntv_or_sync_fifo.gl0.wr_n_2\,
Q(3 downto 0) => p_11_out(3 downto 0),
clk => clk,
din(64 downto 0) => din(64 downto 0),
dout(64 downto 0) => dout(64 downto 0),
\gc0.count_d1_reg[3]\(3 downto 0) => p_0_out_0(3 downto 0),
\gpregsm1.curr_fwft_state_reg[1]\(0) => p_5_out
);
rstblk: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_reset_blk_ramfifo
port map (
clk => clk,
\gc0.count_reg[1]\(1) => rd_rst_i(2),
\gc0.count_reg[1]\(0) => rd_rst_i(0),
\grstd1.grst_full.grst_f.rst_d3_reg_0\ => rst_full_ff_i,
\out\(0) => wr_rst_i(1),
rst => rst,
wr_rst_busy => \^wr_rst_busy\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_top is
port (
wr_rst_busy : out STD_LOGIC;
empty : out STD_LOGIC;
full : out STD_LOGIC;
almost_full : out STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 64 downto 0 );
rd_en : in STD_LOGIC;
wr_en : in STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 64 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_top;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_top is
begin
\grf.rf\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_ramfifo
port map (
almost_full => almost_full,
clk => clk,
din(64 downto 0) => din(64 downto 0),
dout(64 downto 0) => dout(64 downto 0),
empty => empty,
full => full,
rd_en => rd_en,
rst => rst,
wr_en => wr_en,
wr_rst_busy => wr_rst_busy
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2_synth is
port (
wr_rst_busy : out STD_LOGIC;
empty : out STD_LOGIC;
full : out STD_LOGIC;
almost_full : out STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 64 downto 0 );
rd_en : in STD_LOGIC;
wr_en : in STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 64 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2_synth;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2_synth is
begin
\gconvfifo.rf\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_top
port map (
almost_full => almost_full,
clk => clk,
din(64 downto 0) => din(64 downto 0),
dout(64 downto 0) => dout(64 downto 0),
empty => empty,
full => full,
rd_en => rd_en,
rst => rst,
wr_en => wr_en,
wr_rst_busy => wr_rst_busy
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 is
port (
backup : in STD_LOGIC;
backup_marker : in STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
srst : in STD_LOGIC;
wr_clk : in STD_LOGIC;
wr_rst : in STD_LOGIC;
rd_clk : in STD_LOGIC;
rd_rst : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 64 downto 0 );
wr_en : in STD_LOGIC;
rd_en : in STD_LOGIC;
prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
prog_empty_thresh_assert : in STD_LOGIC_VECTOR ( 3 downto 0 );
prog_empty_thresh_negate : in STD_LOGIC_VECTOR ( 3 downto 0 );
prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
prog_full_thresh_assert : in STD_LOGIC_VECTOR ( 3 downto 0 );
prog_full_thresh_negate : in STD_LOGIC_VECTOR ( 3 downto 0 );
int_clk : in STD_LOGIC;
injectdbiterr : in STD_LOGIC;
injectsbiterr : in STD_LOGIC;
sleep : in STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 64 downto 0 );
full : out STD_LOGIC;
almost_full : out STD_LOGIC;
wr_ack : out STD_LOGIC;
overflow : out STD_LOGIC;
empty : out STD_LOGIC;
almost_empty : out STD_LOGIC;
valid : out STD_LOGIC;
underflow : out STD_LOGIC;
data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
prog_full : out STD_LOGIC;
prog_empty : out STD_LOGIC;
sbiterr : out STD_LOGIC;
dbiterr : out STD_LOGIC;
wr_rst_busy : out STD_LOGIC;
rd_rst_busy : out STD_LOGIC;
m_aclk : in STD_LOGIC;
s_aclk : in STD_LOGIC;
s_aresetn : in STD_LOGIC;
m_aclk_en : in STD_LOGIC;
s_aclk_en : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_buser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
m_axi_awid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_wlast : out STD_LOGIC;
m_axi_wuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_buser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_aruser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_ruser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_arid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_aruser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rlast : in STD_LOGIC;
m_axi_ruser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC;
s_axis_tvalid : in STD_LOGIC;
s_axis_tready : out STD_LOGIC;
s_axis_tdata : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axis_tstrb : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tkeep : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tlast : in STD_LOGIC;
s_axis_tid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tdest : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tuser : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axis_tvalid : out STD_LOGIC;
m_axis_tready : in STD_LOGIC;
m_axis_tdata : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axis_tstrb : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tkeep : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tlast : out STD_LOGIC;
m_axis_tid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tdest : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tuser : out STD_LOGIC_VECTOR ( 3 downto 0 );
axi_aw_injectsbiterr : in STD_LOGIC;
axi_aw_injectdbiterr : in STD_LOGIC;
axi_aw_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_aw_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_aw_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_aw_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_aw_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_aw_sbiterr : out STD_LOGIC;
axi_aw_dbiterr : out STD_LOGIC;
axi_aw_overflow : out STD_LOGIC;
axi_aw_underflow : out STD_LOGIC;
axi_aw_prog_full : out STD_LOGIC;
axi_aw_prog_empty : out STD_LOGIC;
axi_w_injectsbiterr : in STD_LOGIC;
axi_w_injectdbiterr : in STD_LOGIC;
axi_w_prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_w_prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_w_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_w_wr_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_w_rd_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_w_sbiterr : out STD_LOGIC;
axi_w_dbiterr : out STD_LOGIC;
axi_w_overflow : out STD_LOGIC;
axi_w_underflow : out STD_LOGIC;
axi_w_prog_full : out STD_LOGIC;
axi_w_prog_empty : out STD_LOGIC;
axi_b_injectsbiterr : in STD_LOGIC;
axi_b_injectdbiterr : in STD_LOGIC;
axi_b_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_b_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_b_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_b_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_b_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_b_sbiterr : out STD_LOGIC;
axi_b_dbiterr : out STD_LOGIC;
axi_b_overflow : out STD_LOGIC;
axi_b_underflow : out STD_LOGIC;
axi_b_prog_full : out STD_LOGIC;
axi_b_prog_empty : out STD_LOGIC;
axi_ar_injectsbiterr : in STD_LOGIC;
axi_ar_injectdbiterr : in STD_LOGIC;
axi_ar_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_ar_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_ar_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_ar_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_ar_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_ar_sbiterr : out STD_LOGIC;
axi_ar_dbiterr : out STD_LOGIC;
axi_ar_overflow : out STD_LOGIC;
axi_ar_underflow : out STD_LOGIC;
axi_ar_prog_full : out STD_LOGIC;
axi_ar_prog_empty : out STD_LOGIC;
axi_r_injectsbiterr : in STD_LOGIC;
axi_r_injectdbiterr : in STD_LOGIC;
axi_r_prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_r_prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_r_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_r_wr_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_r_rd_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_r_sbiterr : out STD_LOGIC;
axi_r_dbiterr : out STD_LOGIC;
axi_r_overflow : out STD_LOGIC;
axi_r_underflow : out STD_LOGIC;
axi_r_prog_full : out STD_LOGIC;
axi_r_prog_empty : out STD_LOGIC;
axis_injectsbiterr : in STD_LOGIC;
axis_injectdbiterr : in STD_LOGIC;
axis_prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axis_prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axis_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axis_wr_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axis_rd_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axis_sbiterr : out STD_LOGIC;
axis_dbiterr : out STD_LOGIC;
axis_overflow : out STD_LOGIC;
axis_underflow : out STD_LOGIC;
axis_prog_full : out STD_LOGIC;
axis_prog_empty : out STD_LOGIC
);
attribute C_ADD_NGC_CONSTRAINT : integer;
attribute C_ADD_NGC_CONSTRAINT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_APPLICATION_TYPE_AXIS : integer;
attribute C_APPLICATION_TYPE_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_APPLICATION_TYPE_RACH : integer;
attribute C_APPLICATION_TYPE_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_APPLICATION_TYPE_RDCH : integer;
attribute C_APPLICATION_TYPE_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_APPLICATION_TYPE_WACH : integer;
attribute C_APPLICATION_TYPE_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_APPLICATION_TYPE_WDCH : integer;
attribute C_APPLICATION_TYPE_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_APPLICATION_TYPE_WRCH : integer;
attribute C_APPLICATION_TYPE_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_AXIS_TDATA_WIDTH : integer;
attribute C_AXIS_TDATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 8;
attribute C_AXIS_TDEST_WIDTH : integer;
attribute C_AXIS_TDEST_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXIS_TID_WIDTH : integer;
attribute C_AXIS_TID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXIS_TKEEP_WIDTH : integer;
attribute C_AXIS_TKEEP_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXIS_TSTRB_WIDTH : integer;
attribute C_AXIS_TSTRB_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXIS_TUSER_WIDTH : integer;
attribute C_AXIS_TUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 4;
attribute C_AXIS_TYPE : integer;
attribute C_AXIS_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 64;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXI_LEN_WIDTH : integer;
attribute C_AXI_LEN_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 8;
attribute C_AXI_LOCK_WIDTH : integer;
attribute C_AXI_LOCK_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_COMMON_CLOCK : integer;
attribute C_COMMON_CLOCK of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_COUNT_TYPE : integer;
attribute C_COUNT_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_DATA_COUNT_WIDTH : integer;
attribute C_DATA_COUNT_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 5;
attribute C_DEFAULT_VALUE : string;
attribute C_DEFAULT_VALUE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is "BlankString";
attribute C_DIN_WIDTH : integer;
attribute C_DIN_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 65;
attribute C_DIN_WIDTH_AXIS : integer;
attribute C_DIN_WIDTH_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_DIN_WIDTH_RACH : integer;
attribute C_DIN_WIDTH_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 32;
attribute C_DIN_WIDTH_RDCH : integer;
attribute C_DIN_WIDTH_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 64;
attribute C_DIN_WIDTH_WACH : integer;
attribute C_DIN_WIDTH_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_DIN_WIDTH_WDCH : integer;
attribute C_DIN_WIDTH_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 64;
attribute C_DIN_WIDTH_WRCH : integer;
attribute C_DIN_WIDTH_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 2;
attribute C_DOUT_RST_VAL : string;
attribute C_DOUT_RST_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is "0";
attribute C_DOUT_WIDTH : integer;
attribute C_DOUT_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 65;
attribute C_ENABLE_RLOCS : integer;
attribute C_ENABLE_RLOCS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_ENABLE_RST_SYNC : integer;
attribute C_ENABLE_RST_SYNC of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_ERROR_INJECTION_TYPE : integer;
attribute C_ERROR_INJECTION_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_AXIS : integer;
attribute C_ERROR_INJECTION_TYPE_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_RACH : integer;
attribute C_ERROR_INJECTION_TYPE_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_RDCH : integer;
attribute C_ERROR_INJECTION_TYPE_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_WACH : integer;
attribute C_ERROR_INJECTION_TYPE_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_WDCH : integer;
attribute C_ERROR_INJECTION_TYPE_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_WRCH : integer;
attribute C_ERROR_INJECTION_TYPE_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is "kintex7";
attribute C_FULL_FLAGS_RST_VAL : integer;
attribute C_FULL_FLAGS_RST_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_HAS_ALMOST_EMPTY : integer;
attribute C_HAS_ALMOST_EMPTY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_ALMOST_FULL : integer;
attribute C_HAS_ALMOST_FULL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_HAS_AXIS_TDATA : integer;
attribute C_HAS_AXIS_TDATA of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_HAS_AXIS_TDEST : integer;
attribute C_HAS_AXIS_TDEST of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXIS_TID : integer;
attribute C_HAS_AXIS_TID of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXIS_TKEEP : integer;
attribute C_HAS_AXIS_TKEEP of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXIS_TLAST : integer;
attribute C_HAS_AXIS_TLAST of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXIS_TREADY : integer;
attribute C_HAS_AXIS_TREADY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_HAS_AXIS_TSTRB : integer;
attribute C_HAS_AXIS_TSTRB of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXIS_TUSER : integer;
attribute C_HAS_AXIS_TUSER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_HAS_AXI_ARUSER : integer;
attribute C_HAS_AXI_ARUSER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXI_AWUSER : integer;
attribute C_HAS_AXI_AWUSER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXI_BUSER : integer;
attribute C_HAS_AXI_BUSER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXI_RD_CHANNEL : integer;
attribute C_HAS_AXI_RD_CHANNEL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_HAS_AXI_RUSER : integer;
attribute C_HAS_AXI_RUSER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXI_WR_CHANNEL : integer;
attribute C_HAS_AXI_WR_CHANNEL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_HAS_AXI_WUSER : integer;
attribute C_HAS_AXI_WUSER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_BACKUP : integer;
attribute C_HAS_BACKUP of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_DATA_COUNT : integer;
attribute C_HAS_DATA_COUNT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_DATA_COUNTS_AXIS : integer;
attribute C_HAS_DATA_COUNTS_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_DATA_COUNTS_RACH : integer;
attribute C_HAS_DATA_COUNTS_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_DATA_COUNTS_RDCH : integer;
attribute C_HAS_DATA_COUNTS_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_DATA_COUNTS_WACH : integer;
attribute C_HAS_DATA_COUNTS_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_DATA_COUNTS_WDCH : integer;
attribute C_HAS_DATA_COUNTS_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_DATA_COUNTS_WRCH : integer;
attribute C_HAS_DATA_COUNTS_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_INT_CLK : integer;
attribute C_HAS_INT_CLK of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_MASTER_CE : integer;
attribute C_HAS_MASTER_CE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_MEMINIT_FILE : integer;
attribute C_HAS_MEMINIT_FILE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_OVERFLOW : integer;
attribute C_HAS_OVERFLOW of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_PROG_FLAGS_AXIS : integer;
attribute C_HAS_PROG_FLAGS_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_PROG_FLAGS_RACH : integer;
attribute C_HAS_PROG_FLAGS_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_PROG_FLAGS_RDCH : integer;
attribute C_HAS_PROG_FLAGS_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_PROG_FLAGS_WACH : integer;
attribute C_HAS_PROG_FLAGS_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_PROG_FLAGS_WDCH : integer;
attribute C_HAS_PROG_FLAGS_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_PROG_FLAGS_WRCH : integer;
attribute C_HAS_PROG_FLAGS_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_RD_DATA_COUNT : integer;
attribute C_HAS_RD_DATA_COUNT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_RD_RST : integer;
attribute C_HAS_RD_RST of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_RST : integer;
attribute C_HAS_RST of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_HAS_SLAVE_CE : integer;
attribute C_HAS_SLAVE_CE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_SRST : integer;
attribute C_HAS_SRST of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_UNDERFLOW : integer;
attribute C_HAS_UNDERFLOW of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_VALID : integer;
attribute C_HAS_VALID of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_WR_ACK : integer;
attribute C_HAS_WR_ACK of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_WR_DATA_COUNT : integer;
attribute C_HAS_WR_DATA_COUNT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_WR_RST : integer;
attribute C_HAS_WR_RST of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_IMPLEMENTATION_TYPE : integer;
attribute C_IMPLEMENTATION_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_IMPLEMENTATION_TYPE_AXIS : integer;
attribute C_IMPLEMENTATION_TYPE_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_RACH : integer;
attribute C_IMPLEMENTATION_TYPE_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_RDCH : integer;
attribute C_IMPLEMENTATION_TYPE_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_WACH : integer;
attribute C_IMPLEMENTATION_TYPE_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_WDCH : integer;
attribute C_IMPLEMENTATION_TYPE_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_WRCH : integer;
attribute C_IMPLEMENTATION_TYPE_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_INIT_WR_PNTR_VAL : integer;
attribute C_INIT_WR_PNTR_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_MEMORY_TYPE : integer;
attribute C_MEMORY_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 2;
attribute C_MIF_FILE_NAME : string;
attribute C_MIF_FILE_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is "BlankString";
attribute C_MSGON_VAL : integer;
attribute C_MSGON_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_OPTIMIZATION_MODE : integer;
attribute C_OPTIMIZATION_MODE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_OVERFLOW_LOW : integer;
attribute C_OVERFLOW_LOW of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_POWER_SAVING_MODE : integer;
attribute C_POWER_SAVING_MODE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PRELOAD_LATENCY : integer;
attribute C_PRELOAD_LATENCY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PRELOAD_REGS : integer;
attribute C_PRELOAD_REGS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_PRIM_FIFO_TYPE : string;
attribute C_PRIM_FIFO_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is "512x72";
attribute C_PRIM_FIFO_TYPE_AXIS : string;
attribute C_PRIM_FIFO_TYPE_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is "1kx18";
attribute C_PRIM_FIFO_TYPE_RACH : string;
attribute C_PRIM_FIFO_TYPE_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is "512x36";
attribute C_PRIM_FIFO_TYPE_RDCH : string;
attribute C_PRIM_FIFO_TYPE_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is "1kx36";
attribute C_PRIM_FIFO_TYPE_WACH : string;
attribute C_PRIM_FIFO_TYPE_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is "512x36";
attribute C_PRIM_FIFO_TYPE_WDCH : string;
attribute C_PRIM_FIFO_TYPE_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is "1kx36";
attribute C_PRIM_FIFO_TYPE_WRCH : string;
attribute C_PRIM_FIFO_TYPE_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is "512x36";
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 4;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL : integer;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 5;
attribute C_PROG_EMPTY_TYPE : integer;
attribute C_PROG_EMPTY_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_EMPTY_TYPE_AXIS : integer;
attribute C_PROG_EMPTY_TYPE_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_EMPTY_TYPE_RACH : integer;
attribute C_PROG_EMPTY_TYPE_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_EMPTY_TYPE_RDCH : integer;
attribute C_PROG_EMPTY_TYPE_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_EMPTY_TYPE_WACH : integer;
attribute C_PROG_EMPTY_TYPE_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_EMPTY_TYPE_WDCH : integer;
attribute C_PROG_EMPTY_TYPE_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_EMPTY_TYPE_WRCH : integer;
attribute C_PROG_EMPTY_TYPE_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_FULL_THRESH_ASSERT_VAL : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 15;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1023;
attribute C_PROG_FULL_THRESH_NEGATE_VAL : integer;
attribute C_PROG_FULL_THRESH_NEGATE_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 14;
attribute C_PROG_FULL_TYPE : integer;
attribute C_PROG_FULL_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_FULL_TYPE_AXIS : integer;
attribute C_PROG_FULL_TYPE_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_FULL_TYPE_RACH : integer;
attribute C_PROG_FULL_TYPE_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_FULL_TYPE_RDCH : integer;
attribute C_PROG_FULL_TYPE_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_FULL_TYPE_WACH : integer;
attribute C_PROG_FULL_TYPE_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_FULL_TYPE_WDCH : integer;
attribute C_PROG_FULL_TYPE_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_FULL_TYPE_WRCH : integer;
attribute C_PROG_FULL_TYPE_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_RACH_TYPE : integer;
attribute C_RACH_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_RDCH_TYPE : integer;
attribute C_RDCH_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_RD_DATA_COUNT_WIDTH : integer;
attribute C_RD_DATA_COUNT_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 5;
attribute C_RD_DEPTH : integer;
attribute C_RD_DEPTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 16;
attribute C_RD_FREQ : integer;
attribute C_RD_FREQ of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_RD_PNTR_WIDTH : integer;
attribute C_RD_PNTR_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 4;
attribute C_REG_SLICE_MODE_AXIS : integer;
attribute C_REG_SLICE_MODE_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_REG_SLICE_MODE_RACH : integer;
attribute C_REG_SLICE_MODE_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_REG_SLICE_MODE_RDCH : integer;
attribute C_REG_SLICE_MODE_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_REG_SLICE_MODE_WACH : integer;
attribute C_REG_SLICE_MODE_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_REG_SLICE_MODE_WDCH : integer;
attribute C_REG_SLICE_MODE_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_REG_SLICE_MODE_WRCH : integer;
attribute C_REG_SLICE_MODE_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_SELECT_XPM : integer;
attribute C_SELECT_XPM of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_SYNCHRONIZER_STAGE : integer;
attribute C_SYNCHRONIZER_STAGE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 2;
attribute C_UNDERFLOW_LOW : integer;
attribute C_UNDERFLOW_LOW of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_COMMON_OVERFLOW : integer;
attribute C_USE_COMMON_OVERFLOW of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_COMMON_UNDERFLOW : integer;
attribute C_USE_COMMON_UNDERFLOW of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_DEFAULT_SETTINGS : integer;
attribute C_USE_DEFAULT_SETTINGS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_DOUT_RST : integer;
attribute C_USE_DOUT_RST of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_ECC_AXIS : integer;
attribute C_USE_ECC_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_ECC_RACH : integer;
attribute C_USE_ECC_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_ECC_RDCH : integer;
attribute C_USE_ECC_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_ECC_WACH : integer;
attribute C_USE_ECC_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_ECC_WDCH : integer;
attribute C_USE_ECC_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_ECC_WRCH : integer;
attribute C_USE_ECC_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_EMBEDDED_REG : integer;
attribute C_USE_EMBEDDED_REG of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_FIFO16_FLAGS : integer;
attribute C_USE_FIFO16_FLAGS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_FWFT_DATA_COUNT : integer;
attribute C_USE_FWFT_DATA_COUNT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_USE_PIPELINE_REG : integer;
attribute C_USE_PIPELINE_REG of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_VALID_LOW : integer;
attribute C_VALID_LOW of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_WACH_TYPE : integer;
attribute C_WACH_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_WDCH_TYPE : integer;
attribute C_WDCH_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_WRCH_TYPE : integer;
attribute C_WRCH_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_WR_ACK_LOW : integer;
attribute C_WR_ACK_LOW of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_WR_DATA_COUNT_WIDTH : integer;
attribute C_WR_DATA_COUNT_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 5;
attribute C_WR_DEPTH : integer;
attribute C_WR_DEPTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 16;
attribute C_WR_DEPTH_AXIS : integer;
attribute C_WR_DEPTH_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1024;
attribute C_WR_DEPTH_RACH : integer;
attribute C_WR_DEPTH_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 16;
attribute C_WR_DEPTH_RDCH : integer;
attribute C_WR_DEPTH_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1024;
attribute C_WR_DEPTH_WACH : integer;
attribute C_WR_DEPTH_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 16;
attribute C_WR_DEPTH_WDCH : integer;
attribute C_WR_DEPTH_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1024;
attribute C_WR_DEPTH_WRCH : integer;
attribute C_WR_DEPTH_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 16;
attribute C_WR_FREQ : integer;
attribute C_WR_FREQ of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_WR_PNTR_WIDTH : integer;
attribute C_WR_PNTR_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 4;
attribute C_WR_PNTR_WIDTH_AXIS : integer;
attribute C_WR_PNTR_WIDTH_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 10;
attribute C_WR_PNTR_WIDTH_RACH : integer;
attribute C_WR_PNTR_WIDTH_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 4;
attribute C_WR_PNTR_WIDTH_RDCH : integer;
attribute C_WR_PNTR_WIDTH_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 10;
attribute C_WR_PNTR_WIDTH_WACH : integer;
attribute C_WR_PNTR_WIDTH_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 4;
attribute C_WR_PNTR_WIDTH_WDCH : integer;
attribute C_WR_PNTR_WIDTH_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 10;
attribute C_WR_PNTR_WIDTH_WRCH : integer;
attribute C_WR_PNTR_WIDTH_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 4;
attribute C_WR_RESPONSE_LATENCY : integer;
attribute C_WR_RESPONSE_LATENCY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 is
signal \<const0>\ : STD_LOGIC;
signal \<const1>\ : STD_LOGIC;
begin
almost_empty <= \<const0>\;
axi_ar_data_count(4) <= \<const0>\;
axi_ar_data_count(3) <= \<const0>\;
axi_ar_data_count(2) <= \<const0>\;
axi_ar_data_count(1) <= \<const0>\;
axi_ar_data_count(0) <= \<const0>\;
axi_ar_dbiterr <= \<const0>\;
axi_ar_overflow <= \<const0>\;
axi_ar_prog_empty <= \<const1>\;
axi_ar_prog_full <= \<const0>\;
axi_ar_rd_data_count(4) <= \<const0>\;
axi_ar_rd_data_count(3) <= \<const0>\;
axi_ar_rd_data_count(2) <= \<const0>\;
axi_ar_rd_data_count(1) <= \<const0>\;
axi_ar_rd_data_count(0) <= \<const0>\;
axi_ar_sbiterr <= \<const0>\;
axi_ar_underflow <= \<const0>\;
axi_ar_wr_data_count(4) <= \<const0>\;
axi_ar_wr_data_count(3) <= \<const0>\;
axi_ar_wr_data_count(2) <= \<const0>\;
axi_ar_wr_data_count(1) <= \<const0>\;
axi_ar_wr_data_count(0) <= \<const0>\;
axi_aw_data_count(4) <= \<const0>\;
axi_aw_data_count(3) <= \<const0>\;
axi_aw_data_count(2) <= \<const0>\;
axi_aw_data_count(1) <= \<const0>\;
axi_aw_data_count(0) <= \<const0>\;
axi_aw_dbiterr <= \<const0>\;
axi_aw_overflow <= \<const0>\;
axi_aw_prog_empty <= \<const1>\;
axi_aw_prog_full <= \<const0>\;
axi_aw_rd_data_count(4) <= \<const0>\;
axi_aw_rd_data_count(3) <= \<const0>\;
axi_aw_rd_data_count(2) <= \<const0>\;
axi_aw_rd_data_count(1) <= \<const0>\;
axi_aw_rd_data_count(0) <= \<const0>\;
axi_aw_sbiterr <= \<const0>\;
axi_aw_underflow <= \<const0>\;
axi_aw_wr_data_count(4) <= \<const0>\;
axi_aw_wr_data_count(3) <= \<const0>\;
axi_aw_wr_data_count(2) <= \<const0>\;
axi_aw_wr_data_count(1) <= \<const0>\;
axi_aw_wr_data_count(0) <= \<const0>\;
axi_b_data_count(4) <= \<const0>\;
axi_b_data_count(3) <= \<const0>\;
axi_b_data_count(2) <= \<const0>\;
axi_b_data_count(1) <= \<const0>\;
axi_b_data_count(0) <= \<const0>\;
axi_b_dbiterr <= \<const0>\;
axi_b_overflow <= \<const0>\;
axi_b_prog_empty <= \<const1>\;
axi_b_prog_full <= \<const0>\;
axi_b_rd_data_count(4) <= \<const0>\;
axi_b_rd_data_count(3) <= \<const0>\;
axi_b_rd_data_count(2) <= \<const0>\;
axi_b_rd_data_count(1) <= \<const0>\;
axi_b_rd_data_count(0) <= \<const0>\;
axi_b_sbiterr <= \<const0>\;
axi_b_underflow <= \<const0>\;
axi_b_wr_data_count(4) <= \<const0>\;
axi_b_wr_data_count(3) <= \<const0>\;
axi_b_wr_data_count(2) <= \<const0>\;
axi_b_wr_data_count(1) <= \<const0>\;
axi_b_wr_data_count(0) <= \<const0>\;
axi_r_data_count(10) <= \<const0>\;
axi_r_data_count(9) <= \<const0>\;
axi_r_data_count(8) <= \<const0>\;
axi_r_data_count(7) <= \<const0>\;
axi_r_data_count(6) <= \<const0>\;
axi_r_data_count(5) <= \<const0>\;
axi_r_data_count(4) <= \<const0>\;
axi_r_data_count(3) <= \<const0>\;
axi_r_data_count(2) <= \<const0>\;
axi_r_data_count(1) <= \<const0>\;
axi_r_data_count(0) <= \<const0>\;
axi_r_dbiterr <= \<const0>\;
axi_r_overflow <= \<const0>\;
axi_r_prog_empty <= \<const1>\;
axi_r_prog_full <= \<const0>\;
axi_r_rd_data_count(10) <= \<const0>\;
axi_r_rd_data_count(9) <= \<const0>\;
axi_r_rd_data_count(8) <= \<const0>\;
axi_r_rd_data_count(7) <= \<const0>\;
axi_r_rd_data_count(6) <= \<const0>\;
axi_r_rd_data_count(5) <= \<const0>\;
axi_r_rd_data_count(4) <= \<const0>\;
axi_r_rd_data_count(3) <= \<const0>\;
axi_r_rd_data_count(2) <= \<const0>\;
axi_r_rd_data_count(1) <= \<const0>\;
axi_r_rd_data_count(0) <= \<const0>\;
axi_r_sbiterr <= \<const0>\;
axi_r_underflow <= \<const0>\;
axi_r_wr_data_count(10) <= \<const0>\;
axi_r_wr_data_count(9) <= \<const0>\;
axi_r_wr_data_count(8) <= \<const0>\;
axi_r_wr_data_count(7) <= \<const0>\;
axi_r_wr_data_count(6) <= \<const0>\;
axi_r_wr_data_count(5) <= \<const0>\;
axi_r_wr_data_count(4) <= \<const0>\;
axi_r_wr_data_count(3) <= \<const0>\;
axi_r_wr_data_count(2) <= \<const0>\;
axi_r_wr_data_count(1) <= \<const0>\;
axi_r_wr_data_count(0) <= \<const0>\;
axi_w_data_count(10) <= \<const0>\;
axi_w_data_count(9) <= \<const0>\;
axi_w_data_count(8) <= \<const0>\;
axi_w_data_count(7) <= \<const0>\;
axi_w_data_count(6) <= \<const0>\;
axi_w_data_count(5) <= \<const0>\;
axi_w_data_count(4) <= \<const0>\;
axi_w_data_count(3) <= \<const0>\;
axi_w_data_count(2) <= \<const0>\;
axi_w_data_count(1) <= \<const0>\;
axi_w_data_count(0) <= \<const0>\;
axi_w_dbiterr <= \<const0>\;
axi_w_overflow <= \<const0>\;
axi_w_prog_empty <= \<const1>\;
axi_w_prog_full <= \<const0>\;
axi_w_rd_data_count(10) <= \<const0>\;
axi_w_rd_data_count(9) <= \<const0>\;
axi_w_rd_data_count(8) <= \<const0>\;
axi_w_rd_data_count(7) <= \<const0>\;
axi_w_rd_data_count(6) <= \<const0>\;
axi_w_rd_data_count(5) <= \<const0>\;
axi_w_rd_data_count(4) <= \<const0>\;
axi_w_rd_data_count(3) <= \<const0>\;
axi_w_rd_data_count(2) <= \<const0>\;
axi_w_rd_data_count(1) <= \<const0>\;
axi_w_rd_data_count(0) <= \<const0>\;
axi_w_sbiterr <= \<const0>\;
axi_w_underflow <= \<const0>\;
axi_w_wr_data_count(10) <= \<const0>\;
axi_w_wr_data_count(9) <= \<const0>\;
axi_w_wr_data_count(8) <= \<const0>\;
axi_w_wr_data_count(7) <= \<const0>\;
axi_w_wr_data_count(6) <= \<const0>\;
axi_w_wr_data_count(5) <= \<const0>\;
axi_w_wr_data_count(4) <= \<const0>\;
axi_w_wr_data_count(3) <= \<const0>\;
axi_w_wr_data_count(2) <= \<const0>\;
axi_w_wr_data_count(1) <= \<const0>\;
axi_w_wr_data_count(0) <= \<const0>\;
axis_data_count(10) <= \<const0>\;
axis_data_count(9) <= \<const0>\;
axis_data_count(8) <= \<const0>\;
axis_data_count(7) <= \<const0>\;
axis_data_count(6) <= \<const0>\;
axis_data_count(5) <= \<const0>\;
axis_data_count(4) <= \<const0>\;
axis_data_count(3) <= \<const0>\;
axis_data_count(2) <= \<const0>\;
axis_data_count(1) <= \<const0>\;
axis_data_count(0) <= \<const0>\;
axis_dbiterr <= \<const0>\;
axis_overflow <= \<const0>\;
axis_prog_empty <= \<const1>\;
axis_prog_full <= \<const0>\;
axis_rd_data_count(10) <= \<const0>\;
axis_rd_data_count(9) <= \<const0>\;
axis_rd_data_count(8) <= \<const0>\;
axis_rd_data_count(7) <= \<const0>\;
axis_rd_data_count(6) <= \<const0>\;
axis_rd_data_count(5) <= \<const0>\;
axis_rd_data_count(4) <= \<const0>\;
axis_rd_data_count(3) <= \<const0>\;
axis_rd_data_count(2) <= \<const0>\;
axis_rd_data_count(1) <= \<const0>\;
axis_rd_data_count(0) <= \<const0>\;
axis_sbiterr <= \<const0>\;
axis_underflow <= \<const0>\;
axis_wr_data_count(10) <= \<const0>\;
axis_wr_data_count(9) <= \<const0>\;
axis_wr_data_count(8) <= \<const0>\;
axis_wr_data_count(7) <= \<const0>\;
axis_wr_data_count(6) <= \<const0>\;
axis_wr_data_count(5) <= \<const0>\;
axis_wr_data_count(4) <= \<const0>\;
axis_wr_data_count(3) <= \<const0>\;
axis_wr_data_count(2) <= \<const0>\;
axis_wr_data_count(1) <= \<const0>\;
axis_wr_data_count(0) <= \<const0>\;
data_count(4) <= \<const0>\;
data_count(3) <= \<const0>\;
data_count(2) <= \<const0>\;
data_count(1) <= \<const0>\;
data_count(0) <= \<const0>\;
dbiterr <= \<const0>\;
m_axi_araddr(31) <= \<const0>\;
m_axi_araddr(30) <= \<const0>\;
m_axi_araddr(29) <= \<const0>\;
m_axi_araddr(28) <= \<const0>\;
m_axi_araddr(27) <= \<const0>\;
m_axi_araddr(26) <= \<const0>\;
m_axi_araddr(25) <= \<const0>\;
m_axi_araddr(24) <= \<const0>\;
m_axi_araddr(23) <= \<const0>\;
m_axi_araddr(22) <= \<const0>\;
m_axi_araddr(21) <= \<const0>\;
m_axi_araddr(20) <= \<const0>\;
m_axi_araddr(19) <= \<const0>\;
m_axi_araddr(18) <= \<const0>\;
m_axi_araddr(17) <= \<const0>\;
m_axi_araddr(16) <= \<const0>\;
m_axi_araddr(15) <= \<const0>\;
m_axi_araddr(14) <= \<const0>\;
m_axi_araddr(13) <= \<const0>\;
m_axi_araddr(12) <= \<const0>\;
m_axi_araddr(11) <= \<const0>\;
m_axi_araddr(10) <= \<const0>\;
m_axi_araddr(9) <= \<const0>\;
m_axi_araddr(8) <= \<const0>\;
m_axi_araddr(7) <= \<const0>\;
m_axi_araddr(6) <= \<const0>\;
m_axi_araddr(5) <= \<const0>\;
m_axi_araddr(4) <= \<const0>\;
m_axi_araddr(3) <= \<const0>\;
m_axi_araddr(2) <= \<const0>\;
m_axi_araddr(1) <= \<const0>\;
m_axi_araddr(0) <= \<const0>\;
m_axi_arburst(1) <= \<const0>\;
m_axi_arburst(0) <= \<const0>\;
m_axi_arcache(3) <= \<const0>\;
m_axi_arcache(2) <= \<const0>\;
m_axi_arcache(1) <= \<const0>\;
m_axi_arcache(0) <= \<const0>\;
m_axi_arid(0) <= \<const0>\;
m_axi_arlen(7) <= \<const0>\;
m_axi_arlen(6) <= \<const0>\;
m_axi_arlen(5) <= \<const0>\;
m_axi_arlen(4) <= \<const0>\;
m_axi_arlen(3) <= \<const0>\;
m_axi_arlen(2) <= \<const0>\;
m_axi_arlen(1) <= \<const0>\;
m_axi_arlen(0) <= \<const0>\;
m_axi_arlock(0) <= \<const0>\;
m_axi_arprot(2) <= \<const0>\;
m_axi_arprot(1) <= \<const0>\;
m_axi_arprot(0) <= \<const0>\;
m_axi_arqos(3) <= \<const0>\;
m_axi_arqos(2) <= \<const0>\;
m_axi_arqos(1) <= \<const0>\;
m_axi_arqos(0) <= \<const0>\;
m_axi_arregion(3) <= \<const0>\;
m_axi_arregion(2) <= \<const0>\;
m_axi_arregion(1) <= \<const0>\;
m_axi_arregion(0) <= \<const0>\;
m_axi_arsize(2) <= \<const0>\;
m_axi_arsize(1) <= \<const0>\;
m_axi_arsize(0) <= \<const0>\;
m_axi_aruser(0) <= \<const0>\;
m_axi_arvalid <= \<const0>\;
m_axi_awaddr(31) <= \<const0>\;
m_axi_awaddr(30) <= \<const0>\;
m_axi_awaddr(29) <= \<const0>\;
m_axi_awaddr(28) <= \<const0>\;
m_axi_awaddr(27) <= \<const0>\;
m_axi_awaddr(26) <= \<const0>\;
m_axi_awaddr(25) <= \<const0>\;
m_axi_awaddr(24) <= \<const0>\;
m_axi_awaddr(23) <= \<const0>\;
m_axi_awaddr(22) <= \<const0>\;
m_axi_awaddr(21) <= \<const0>\;
m_axi_awaddr(20) <= \<const0>\;
m_axi_awaddr(19) <= \<const0>\;
m_axi_awaddr(18) <= \<const0>\;
m_axi_awaddr(17) <= \<const0>\;
m_axi_awaddr(16) <= \<const0>\;
m_axi_awaddr(15) <= \<const0>\;
m_axi_awaddr(14) <= \<const0>\;
m_axi_awaddr(13) <= \<const0>\;
m_axi_awaddr(12) <= \<const0>\;
m_axi_awaddr(11) <= \<const0>\;
m_axi_awaddr(10) <= \<const0>\;
m_axi_awaddr(9) <= \<const0>\;
m_axi_awaddr(8) <= \<const0>\;
m_axi_awaddr(7) <= \<const0>\;
m_axi_awaddr(6) <= \<const0>\;
m_axi_awaddr(5) <= \<const0>\;
m_axi_awaddr(4) <= \<const0>\;
m_axi_awaddr(3) <= \<const0>\;
m_axi_awaddr(2) <= \<const0>\;
m_axi_awaddr(1) <= \<const0>\;
m_axi_awaddr(0) <= \<const0>\;
m_axi_awburst(1) <= \<const0>\;
m_axi_awburst(0) <= \<const0>\;
m_axi_awcache(3) <= \<const0>\;
m_axi_awcache(2) <= \<const0>\;
m_axi_awcache(1) <= \<const0>\;
m_axi_awcache(0) <= \<const0>\;
m_axi_awid(0) <= \<const0>\;
m_axi_awlen(7) <= \<const0>\;
m_axi_awlen(6) <= \<const0>\;
m_axi_awlen(5) <= \<const0>\;
m_axi_awlen(4) <= \<const0>\;
m_axi_awlen(3) <= \<const0>\;
m_axi_awlen(2) <= \<const0>\;
m_axi_awlen(1) <= \<const0>\;
m_axi_awlen(0) <= \<const0>\;
m_axi_awlock(0) <= \<const0>\;
m_axi_awprot(2) <= \<const0>\;
m_axi_awprot(1) <= \<const0>\;
m_axi_awprot(0) <= \<const0>\;
m_axi_awqos(3) <= \<const0>\;
m_axi_awqos(2) <= \<const0>\;
m_axi_awqos(1) <= \<const0>\;
m_axi_awqos(0) <= \<const0>\;
m_axi_awregion(3) <= \<const0>\;
m_axi_awregion(2) <= \<const0>\;
m_axi_awregion(1) <= \<const0>\;
m_axi_awregion(0) <= \<const0>\;
m_axi_awsize(2) <= \<const0>\;
m_axi_awsize(1) <= \<const0>\;
m_axi_awsize(0) <= \<const0>\;
m_axi_awuser(0) <= \<const0>\;
m_axi_awvalid <= \<const0>\;
m_axi_bready <= \<const0>\;
m_axi_rready <= \<const0>\;
m_axi_wdata(63) <= \<const0>\;
m_axi_wdata(62) <= \<const0>\;
m_axi_wdata(61) <= \<const0>\;
m_axi_wdata(60) <= \<const0>\;
m_axi_wdata(59) <= \<const0>\;
m_axi_wdata(58) <= \<const0>\;
m_axi_wdata(57) <= \<const0>\;
m_axi_wdata(56) <= \<const0>\;
m_axi_wdata(55) <= \<const0>\;
m_axi_wdata(54) <= \<const0>\;
m_axi_wdata(53) <= \<const0>\;
m_axi_wdata(52) <= \<const0>\;
m_axi_wdata(51) <= \<const0>\;
m_axi_wdata(50) <= \<const0>\;
m_axi_wdata(49) <= \<const0>\;
m_axi_wdata(48) <= \<const0>\;
m_axi_wdata(47) <= \<const0>\;
m_axi_wdata(46) <= \<const0>\;
m_axi_wdata(45) <= \<const0>\;
m_axi_wdata(44) <= \<const0>\;
m_axi_wdata(43) <= \<const0>\;
m_axi_wdata(42) <= \<const0>\;
m_axi_wdata(41) <= \<const0>\;
m_axi_wdata(40) <= \<const0>\;
m_axi_wdata(39) <= \<const0>\;
m_axi_wdata(38) <= \<const0>\;
m_axi_wdata(37) <= \<const0>\;
m_axi_wdata(36) <= \<const0>\;
m_axi_wdata(35) <= \<const0>\;
m_axi_wdata(34) <= \<const0>\;
m_axi_wdata(33) <= \<const0>\;
m_axi_wdata(32) <= \<const0>\;
m_axi_wdata(31) <= \<const0>\;
m_axi_wdata(30) <= \<const0>\;
m_axi_wdata(29) <= \<const0>\;
m_axi_wdata(28) <= \<const0>\;
m_axi_wdata(27) <= \<const0>\;
m_axi_wdata(26) <= \<const0>\;
m_axi_wdata(25) <= \<const0>\;
m_axi_wdata(24) <= \<const0>\;
m_axi_wdata(23) <= \<const0>\;
m_axi_wdata(22) <= \<const0>\;
m_axi_wdata(21) <= \<const0>\;
m_axi_wdata(20) <= \<const0>\;
m_axi_wdata(19) <= \<const0>\;
m_axi_wdata(18) <= \<const0>\;
m_axi_wdata(17) <= \<const0>\;
m_axi_wdata(16) <= \<const0>\;
m_axi_wdata(15) <= \<const0>\;
m_axi_wdata(14) <= \<const0>\;
m_axi_wdata(13) <= \<const0>\;
m_axi_wdata(12) <= \<const0>\;
m_axi_wdata(11) <= \<const0>\;
m_axi_wdata(10) <= \<const0>\;
m_axi_wdata(9) <= \<const0>\;
m_axi_wdata(8) <= \<const0>\;
m_axi_wdata(7) <= \<const0>\;
m_axi_wdata(6) <= \<const0>\;
m_axi_wdata(5) <= \<const0>\;
m_axi_wdata(4) <= \<const0>\;
m_axi_wdata(3) <= \<const0>\;
m_axi_wdata(2) <= \<const0>\;
m_axi_wdata(1) <= \<const0>\;
m_axi_wdata(0) <= \<const0>\;
m_axi_wid(0) <= \<const0>\;
m_axi_wlast <= \<const0>\;
m_axi_wstrb(7) <= \<const0>\;
m_axi_wstrb(6) <= \<const0>\;
m_axi_wstrb(5) <= \<const0>\;
m_axi_wstrb(4) <= \<const0>\;
m_axi_wstrb(3) <= \<const0>\;
m_axi_wstrb(2) <= \<const0>\;
m_axi_wstrb(1) <= \<const0>\;
m_axi_wstrb(0) <= \<const0>\;
m_axi_wuser(0) <= \<const0>\;
m_axi_wvalid <= \<const0>\;
m_axis_tdata(7) <= \<const0>\;
m_axis_tdata(6) <= \<const0>\;
m_axis_tdata(5) <= \<const0>\;
m_axis_tdata(4) <= \<const0>\;
m_axis_tdata(3) <= \<const0>\;
m_axis_tdata(2) <= \<const0>\;
m_axis_tdata(1) <= \<const0>\;
m_axis_tdata(0) <= \<const0>\;
m_axis_tdest(0) <= \<const0>\;
m_axis_tid(0) <= \<const0>\;
m_axis_tkeep(0) <= \<const0>\;
m_axis_tlast <= \<const0>\;
m_axis_tstrb(0) <= \<const0>\;
m_axis_tuser(3) <= \<const0>\;
m_axis_tuser(2) <= \<const0>\;
m_axis_tuser(1) <= \<const0>\;
m_axis_tuser(0) <= \<const0>\;
m_axis_tvalid <= \<const0>\;
overflow <= \<const0>\;
prog_empty <= \<const0>\;
prog_full <= \<const0>\;
rd_data_count(4) <= \<const0>\;
rd_data_count(3) <= \<const0>\;
rd_data_count(2) <= \<const0>\;
rd_data_count(1) <= \<const0>\;
rd_data_count(0) <= \<const0>\;
rd_rst_busy <= \<const0>\;
s_axi_arready <= \<const0>\;
s_axi_awready <= \<const0>\;
s_axi_bid(0) <= \<const0>\;
s_axi_bresp(1) <= \<const0>\;
s_axi_bresp(0) <= \<const0>\;
s_axi_buser(0) <= \<const0>\;
s_axi_bvalid <= \<const0>\;
s_axi_rdata(63) <= \<const0>\;
s_axi_rdata(62) <= \<const0>\;
s_axi_rdata(61) <= \<const0>\;
s_axi_rdata(60) <= \<const0>\;
s_axi_rdata(59) <= \<const0>\;
s_axi_rdata(58) <= \<const0>\;
s_axi_rdata(57) <= \<const0>\;
s_axi_rdata(56) <= \<const0>\;
s_axi_rdata(55) <= \<const0>\;
s_axi_rdata(54) <= \<const0>\;
s_axi_rdata(53) <= \<const0>\;
s_axi_rdata(52) <= \<const0>\;
s_axi_rdata(51) <= \<const0>\;
s_axi_rdata(50) <= \<const0>\;
s_axi_rdata(49) <= \<const0>\;
s_axi_rdata(48) <= \<const0>\;
s_axi_rdata(47) <= \<const0>\;
s_axi_rdata(46) <= \<const0>\;
s_axi_rdata(45) <= \<const0>\;
s_axi_rdata(44) <= \<const0>\;
s_axi_rdata(43) <= \<const0>\;
s_axi_rdata(42) <= \<const0>\;
s_axi_rdata(41) <= \<const0>\;
s_axi_rdata(40) <= \<const0>\;
s_axi_rdata(39) <= \<const0>\;
s_axi_rdata(38) <= \<const0>\;
s_axi_rdata(37) <= \<const0>\;
s_axi_rdata(36) <= \<const0>\;
s_axi_rdata(35) <= \<const0>\;
s_axi_rdata(34) <= \<const0>\;
s_axi_rdata(33) <= \<const0>\;
s_axi_rdata(32) <= \<const0>\;
s_axi_rdata(31) <= \<const0>\;
s_axi_rdata(30) <= \<const0>\;
s_axi_rdata(29) <= \<const0>\;
s_axi_rdata(28) <= \<const0>\;
s_axi_rdata(27) <= \<const0>\;
s_axi_rdata(26) <= \<const0>\;
s_axi_rdata(25) <= \<const0>\;
s_axi_rdata(24) <= \<const0>\;
s_axi_rdata(23) <= \<const0>\;
s_axi_rdata(22) <= \<const0>\;
s_axi_rdata(21) <= \<const0>\;
s_axi_rdata(20) <= \<const0>\;
s_axi_rdata(19) <= \<const0>\;
s_axi_rdata(18) <= \<const0>\;
s_axi_rdata(17) <= \<const0>\;
s_axi_rdata(16) <= \<const0>\;
s_axi_rdata(15) <= \<const0>\;
s_axi_rdata(14) <= \<const0>\;
s_axi_rdata(13) <= \<const0>\;
s_axi_rdata(12) <= \<const0>\;
s_axi_rdata(11) <= \<const0>\;
s_axi_rdata(10) <= \<const0>\;
s_axi_rdata(9) <= \<const0>\;
s_axi_rdata(8) <= \<const0>\;
s_axi_rdata(7) <= \<const0>\;
s_axi_rdata(6) <= \<const0>\;
s_axi_rdata(5) <= \<const0>\;
s_axi_rdata(4) <= \<const0>\;
s_axi_rdata(3) <= \<const0>\;
s_axi_rdata(2) <= \<const0>\;
s_axi_rdata(1) <= \<const0>\;
s_axi_rdata(0) <= \<const0>\;
s_axi_rid(0) <= \<const0>\;
s_axi_rlast <= \<const0>\;
s_axi_rresp(1) <= \<const0>\;
s_axi_rresp(0) <= \<const0>\;
s_axi_ruser(0) <= \<const0>\;
s_axi_rvalid <= \<const0>\;
s_axi_wready <= \<const0>\;
s_axis_tready <= \<const0>\;
sbiterr <= \<const0>\;
underflow <= \<const0>\;
valid <= \<const0>\;
wr_ack <= \<const0>\;
wr_data_count(4) <= \<const0>\;
wr_data_count(3) <= \<const0>\;
wr_data_count(2) <= \<const0>\;
wr_data_count(1) <= \<const0>\;
wr_data_count(0) <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
VCC: unisim.vcomponents.VCC
port map (
P => \<const1>\
);
inst_fifo_gen: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2_synth
port map (
almost_full => almost_full,
clk => clk,
din(64 downto 0) => din(64 downto 0),
dout(64 downto 0) => dout(64 downto 0),
empty => empty,
full => full,
rd_en => rd_en,
rst => rst,
wr_en => wr_en,
wr_rst_busy => wr_rst_busy
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
port (
clk : in STD_LOGIC;
rst : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 64 downto 0 );
wr_en : in STD_LOGIC;
rd_en : in STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 64 downto 0 );
full : out STD_LOGIC;
almost_full : out STD_LOGIC;
empty : out STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "tx_axis_gen,fifo_generator_v13_1_2,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "fifo_generator_v13_1_2,Vivado 2016.3";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
signal NLW_U0_almost_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_arvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_awvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_bready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_rready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_wlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_wvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axis_tlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axis_tvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_rd_rst_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_arready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_awready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_bvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_wready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axis_tready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_valid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_wr_ack_UNCONNECTED : STD_LOGIC;
signal NLW_U0_wr_rst_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_ar_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_ar_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_aw_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_aw_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_aw_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_b_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_b_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_b_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_r_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_r_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_r_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_w_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_w_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_w_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axis_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axis_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axis_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_m_axi_araddr_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_m_axi_arburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_m_axi_arcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_arid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_arlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axi_arlock_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_arprot_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_arqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_arregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_arsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_aruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_awaddr_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_m_axi_awburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_m_axi_awcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_awid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_awlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axi_awlock_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_awprot_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_awqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_awregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_awsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_awuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_wdata_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_U0_m_axi_wid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_wstrb_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axi_wuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tdata_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axis_tdest_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tkeep_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tstrb_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tuser_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_buser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_ruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
attribute C_ADD_NGC_CONSTRAINT : integer;
attribute C_ADD_NGC_CONSTRAINT of U0 : label is 0;
attribute C_APPLICATION_TYPE_AXIS : integer;
attribute C_APPLICATION_TYPE_AXIS of U0 : label is 0;
attribute C_APPLICATION_TYPE_RACH : integer;
attribute C_APPLICATION_TYPE_RACH of U0 : label is 0;
attribute C_APPLICATION_TYPE_RDCH : integer;
attribute C_APPLICATION_TYPE_RDCH of U0 : label is 0;
attribute C_APPLICATION_TYPE_WACH : integer;
attribute C_APPLICATION_TYPE_WACH of U0 : label is 0;
attribute C_APPLICATION_TYPE_WDCH : integer;
attribute C_APPLICATION_TYPE_WDCH of U0 : label is 0;
attribute C_APPLICATION_TYPE_WRCH : integer;
attribute C_APPLICATION_TYPE_WRCH of U0 : label is 0;
attribute C_AXIS_TDATA_WIDTH : integer;
attribute C_AXIS_TDATA_WIDTH of U0 : label is 8;
attribute C_AXIS_TDEST_WIDTH : integer;
attribute C_AXIS_TDEST_WIDTH of U0 : label is 1;
attribute C_AXIS_TID_WIDTH : integer;
attribute C_AXIS_TID_WIDTH of U0 : label is 1;
attribute C_AXIS_TKEEP_WIDTH : integer;
attribute C_AXIS_TKEEP_WIDTH of U0 : label is 1;
attribute C_AXIS_TSTRB_WIDTH : integer;
attribute C_AXIS_TSTRB_WIDTH of U0 : label is 1;
attribute C_AXIS_TUSER_WIDTH : integer;
attribute C_AXIS_TUSER_WIDTH of U0 : label is 4;
attribute C_AXIS_TYPE : integer;
attribute C_AXIS_TYPE of U0 : label is 0;
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of U0 : label is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of U0 : label is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of U0 : label is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of U0 : label is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of U0 : label is 64;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of U0 : label is 1;
attribute C_AXI_LEN_WIDTH : integer;
attribute C_AXI_LEN_WIDTH of U0 : label is 8;
attribute C_AXI_LOCK_WIDTH : integer;
attribute C_AXI_LOCK_WIDTH of U0 : label is 1;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of U0 : label is 1;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of U0 : label is 1;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of U0 : label is 1;
attribute C_COMMON_CLOCK : integer;
attribute C_COMMON_CLOCK of U0 : label is 1;
attribute C_COUNT_TYPE : integer;
attribute C_COUNT_TYPE of U0 : label is 0;
attribute C_DATA_COUNT_WIDTH : integer;
attribute C_DATA_COUNT_WIDTH of U0 : label is 5;
attribute C_DEFAULT_VALUE : string;
attribute C_DEFAULT_VALUE of U0 : label is "BlankString";
attribute C_DIN_WIDTH : integer;
attribute C_DIN_WIDTH of U0 : label is 65;
attribute C_DIN_WIDTH_AXIS : integer;
attribute C_DIN_WIDTH_AXIS of U0 : label is 1;
attribute C_DIN_WIDTH_RACH : integer;
attribute C_DIN_WIDTH_RACH of U0 : label is 32;
attribute C_DIN_WIDTH_RDCH : integer;
attribute C_DIN_WIDTH_RDCH of U0 : label is 64;
attribute C_DIN_WIDTH_WACH : integer;
attribute C_DIN_WIDTH_WACH of U0 : label is 1;
attribute C_DIN_WIDTH_WDCH : integer;
attribute C_DIN_WIDTH_WDCH of U0 : label is 64;
attribute C_DIN_WIDTH_WRCH : integer;
attribute C_DIN_WIDTH_WRCH of U0 : label is 2;
attribute C_DOUT_RST_VAL : string;
attribute C_DOUT_RST_VAL of U0 : label is "0";
attribute C_DOUT_WIDTH : integer;
attribute C_DOUT_WIDTH of U0 : label is 65;
attribute C_ENABLE_RLOCS : integer;
attribute C_ENABLE_RLOCS of U0 : label is 0;
attribute C_ENABLE_RST_SYNC : integer;
attribute C_ENABLE_RST_SYNC of U0 : label is 1;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE : integer;
attribute C_ERROR_INJECTION_TYPE of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_AXIS : integer;
attribute C_ERROR_INJECTION_TYPE_AXIS of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_RACH : integer;
attribute C_ERROR_INJECTION_TYPE_RACH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_RDCH : integer;
attribute C_ERROR_INJECTION_TYPE_RDCH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_WACH : integer;
attribute C_ERROR_INJECTION_TYPE_WACH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_WDCH : integer;
attribute C_ERROR_INJECTION_TYPE_WDCH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_WRCH : integer;
attribute C_ERROR_INJECTION_TYPE_WRCH of U0 : label is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "kintex7";
attribute C_FULL_FLAGS_RST_VAL : integer;
attribute C_FULL_FLAGS_RST_VAL of U0 : label is 1;
attribute C_HAS_ALMOST_EMPTY : integer;
attribute C_HAS_ALMOST_EMPTY of U0 : label is 0;
attribute C_HAS_ALMOST_FULL : integer;
attribute C_HAS_ALMOST_FULL of U0 : label is 1;
attribute C_HAS_AXIS_TDATA : integer;
attribute C_HAS_AXIS_TDATA of U0 : label is 1;
attribute C_HAS_AXIS_TDEST : integer;
attribute C_HAS_AXIS_TDEST of U0 : label is 0;
attribute C_HAS_AXIS_TID : integer;
attribute C_HAS_AXIS_TID of U0 : label is 0;
attribute C_HAS_AXIS_TKEEP : integer;
attribute C_HAS_AXIS_TKEEP of U0 : label is 0;
attribute C_HAS_AXIS_TLAST : integer;
attribute C_HAS_AXIS_TLAST of U0 : label is 0;
attribute C_HAS_AXIS_TREADY : integer;
attribute C_HAS_AXIS_TREADY of U0 : label is 1;
attribute C_HAS_AXIS_TSTRB : integer;
attribute C_HAS_AXIS_TSTRB of U0 : label is 0;
attribute C_HAS_AXIS_TUSER : integer;
attribute C_HAS_AXIS_TUSER of U0 : label is 1;
attribute C_HAS_AXI_ARUSER : integer;
attribute C_HAS_AXI_ARUSER of U0 : label is 0;
attribute C_HAS_AXI_AWUSER : integer;
attribute C_HAS_AXI_AWUSER of U0 : label is 0;
attribute C_HAS_AXI_BUSER : integer;
attribute C_HAS_AXI_BUSER of U0 : label is 0;
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of U0 : label is 0;
attribute C_HAS_AXI_RD_CHANNEL : integer;
attribute C_HAS_AXI_RD_CHANNEL of U0 : label is 1;
attribute C_HAS_AXI_RUSER : integer;
attribute C_HAS_AXI_RUSER of U0 : label is 0;
attribute C_HAS_AXI_WR_CHANNEL : integer;
attribute C_HAS_AXI_WR_CHANNEL of U0 : label is 1;
attribute C_HAS_AXI_WUSER : integer;
attribute C_HAS_AXI_WUSER of U0 : label is 0;
attribute C_HAS_BACKUP : integer;
attribute C_HAS_BACKUP of U0 : label is 0;
attribute C_HAS_DATA_COUNT : integer;
attribute C_HAS_DATA_COUNT of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_AXIS : integer;
attribute C_HAS_DATA_COUNTS_AXIS of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_RACH : integer;
attribute C_HAS_DATA_COUNTS_RACH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_RDCH : integer;
attribute C_HAS_DATA_COUNTS_RDCH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_WACH : integer;
attribute C_HAS_DATA_COUNTS_WACH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_WDCH : integer;
attribute C_HAS_DATA_COUNTS_WDCH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_WRCH : integer;
attribute C_HAS_DATA_COUNTS_WRCH of U0 : label is 0;
attribute C_HAS_INT_CLK : integer;
attribute C_HAS_INT_CLK of U0 : label is 0;
attribute C_HAS_MASTER_CE : integer;
attribute C_HAS_MASTER_CE of U0 : label is 0;
attribute C_HAS_MEMINIT_FILE : integer;
attribute C_HAS_MEMINIT_FILE of U0 : label is 0;
attribute C_HAS_OVERFLOW : integer;
attribute C_HAS_OVERFLOW of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_AXIS : integer;
attribute C_HAS_PROG_FLAGS_AXIS of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_RACH : integer;
attribute C_HAS_PROG_FLAGS_RACH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_RDCH : integer;
attribute C_HAS_PROG_FLAGS_RDCH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_WACH : integer;
attribute C_HAS_PROG_FLAGS_WACH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_WDCH : integer;
attribute C_HAS_PROG_FLAGS_WDCH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_WRCH : integer;
attribute C_HAS_PROG_FLAGS_WRCH of U0 : label is 0;
attribute C_HAS_RD_DATA_COUNT : integer;
attribute C_HAS_RD_DATA_COUNT of U0 : label is 0;
attribute C_HAS_RD_RST : integer;
attribute C_HAS_RD_RST of U0 : label is 0;
attribute C_HAS_RST : integer;
attribute C_HAS_RST of U0 : label is 1;
attribute C_HAS_SLAVE_CE : integer;
attribute C_HAS_SLAVE_CE of U0 : label is 0;
attribute C_HAS_SRST : integer;
attribute C_HAS_SRST of U0 : label is 0;
attribute C_HAS_UNDERFLOW : integer;
attribute C_HAS_UNDERFLOW of U0 : label is 0;
attribute C_HAS_VALID : integer;
attribute C_HAS_VALID of U0 : label is 0;
attribute C_HAS_WR_ACK : integer;
attribute C_HAS_WR_ACK of U0 : label is 0;
attribute C_HAS_WR_DATA_COUNT : integer;
attribute C_HAS_WR_DATA_COUNT of U0 : label is 0;
attribute C_HAS_WR_RST : integer;
attribute C_HAS_WR_RST of U0 : label is 0;
attribute C_IMPLEMENTATION_TYPE : integer;
attribute C_IMPLEMENTATION_TYPE of U0 : label is 0;
attribute C_IMPLEMENTATION_TYPE_AXIS : integer;
attribute C_IMPLEMENTATION_TYPE_AXIS of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_RACH : integer;
attribute C_IMPLEMENTATION_TYPE_RACH of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_RDCH : integer;
attribute C_IMPLEMENTATION_TYPE_RDCH of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_WACH : integer;
attribute C_IMPLEMENTATION_TYPE_WACH of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_WDCH : integer;
attribute C_IMPLEMENTATION_TYPE_WDCH of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_WRCH : integer;
attribute C_IMPLEMENTATION_TYPE_WRCH of U0 : label is 1;
attribute C_INIT_WR_PNTR_VAL : integer;
attribute C_INIT_WR_PNTR_VAL of U0 : label is 0;
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of U0 : label is 0;
attribute C_MEMORY_TYPE : integer;
attribute C_MEMORY_TYPE of U0 : label is 2;
attribute C_MIF_FILE_NAME : string;
attribute C_MIF_FILE_NAME of U0 : label is "BlankString";
attribute C_MSGON_VAL : integer;
attribute C_MSGON_VAL of U0 : label is 1;
attribute C_OPTIMIZATION_MODE : integer;
attribute C_OPTIMIZATION_MODE of U0 : label is 0;
attribute C_OVERFLOW_LOW : integer;
attribute C_OVERFLOW_LOW of U0 : label is 0;
attribute C_POWER_SAVING_MODE : integer;
attribute C_POWER_SAVING_MODE of U0 : label is 0;
attribute C_PRELOAD_LATENCY : integer;
attribute C_PRELOAD_LATENCY of U0 : label is 0;
attribute C_PRELOAD_REGS : integer;
attribute C_PRELOAD_REGS of U0 : label is 1;
attribute C_PRIM_FIFO_TYPE : string;
attribute C_PRIM_FIFO_TYPE of U0 : label is "512x72";
attribute C_PRIM_FIFO_TYPE_AXIS : string;
attribute C_PRIM_FIFO_TYPE_AXIS of U0 : label is "1kx18";
attribute C_PRIM_FIFO_TYPE_RACH : string;
attribute C_PRIM_FIFO_TYPE_RACH of U0 : label is "512x36";
attribute C_PRIM_FIFO_TYPE_RDCH : string;
attribute C_PRIM_FIFO_TYPE_RDCH of U0 : label is "1kx36";
attribute C_PRIM_FIFO_TYPE_WACH : string;
attribute C_PRIM_FIFO_TYPE_WACH of U0 : label is "512x36";
attribute C_PRIM_FIFO_TYPE_WDCH : string;
attribute C_PRIM_FIFO_TYPE_WDCH of U0 : label is "1kx36";
attribute C_PRIM_FIFO_TYPE_WRCH : string;
attribute C_PRIM_FIFO_TYPE_WRCH of U0 : label is "512x36";
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL of U0 : label is 4;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL : integer;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL of U0 : label is 5;
attribute C_PROG_EMPTY_TYPE : integer;
attribute C_PROG_EMPTY_TYPE of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_AXIS : integer;
attribute C_PROG_EMPTY_TYPE_AXIS of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_RACH : integer;
attribute C_PROG_EMPTY_TYPE_RACH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_RDCH : integer;
attribute C_PROG_EMPTY_TYPE_RDCH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_WACH : integer;
attribute C_PROG_EMPTY_TYPE_WACH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_WDCH : integer;
attribute C_PROG_EMPTY_TYPE_WDCH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_WRCH : integer;
attribute C_PROG_EMPTY_TYPE_WRCH of U0 : label is 0;
attribute C_PROG_FULL_THRESH_ASSERT_VAL : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL of U0 : label is 15;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_NEGATE_VAL : integer;
attribute C_PROG_FULL_THRESH_NEGATE_VAL of U0 : label is 14;
attribute C_PROG_FULL_TYPE : integer;
attribute C_PROG_FULL_TYPE of U0 : label is 0;
attribute C_PROG_FULL_TYPE_AXIS : integer;
attribute C_PROG_FULL_TYPE_AXIS of U0 : label is 0;
attribute C_PROG_FULL_TYPE_RACH : integer;
attribute C_PROG_FULL_TYPE_RACH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_RDCH : integer;
attribute C_PROG_FULL_TYPE_RDCH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_WACH : integer;
attribute C_PROG_FULL_TYPE_WACH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_WDCH : integer;
attribute C_PROG_FULL_TYPE_WDCH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_WRCH : integer;
attribute C_PROG_FULL_TYPE_WRCH of U0 : label is 0;
attribute C_RACH_TYPE : integer;
attribute C_RACH_TYPE of U0 : label is 0;
attribute C_RDCH_TYPE : integer;
attribute C_RDCH_TYPE of U0 : label is 0;
attribute C_RD_DATA_COUNT_WIDTH : integer;
attribute C_RD_DATA_COUNT_WIDTH of U0 : label is 5;
attribute C_RD_DEPTH : integer;
attribute C_RD_DEPTH of U0 : label is 16;
attribute C_RD_FREQ : integer;
attribute C_RD_FREQ of U0 : label is 1;
attribute C_RD_PNTR_WIDTH : integer;
attribute C_RD_PNTR_WIDTH of U0 : label is 4;
attribute C_REG_SLICE_MODE_AXIS : integer;
attribute C_REG_SLICE_MODE_AXIS of U0 : label is 0;
attribute C_REG_SLICE_MODE_RACH : integer;
attribute C_REG_SLICE_MODE_RACH of U0 : label is 0;
attribute C_REG_SLICE_MODE_RDCH : integer;
attribute C_REG_SLICE_MODE_RDCH of U0 : label is 0;
attribute C_REG_SLICE_MODE_WACH : integer;
attribute C_REG_SLICE_MODE_WACH of U0 : label is 0;
attribute C_REG_SLICE_MODE_WDCH : integer;
attribute C_REG_SLICE_MODE_WDCH of U0 : label is 0;
attribute C_REG_SLICE_MODE_WRCH : integer;
attribute C_REG_SLICE_MODE_WRCH of U0 : label is 0;
attribute C_SELECT_XPM : integer;
attribute C_SELECT_XPM of U0 : label is 0;
attribute C_SYNCHRONIZER_STAGE : integer;
attribute C_SYNCHRONIZER_STAGE of U0 : label is 2;
attribute C_UNDERFLOW_LOW : integer;
attribute C_UNDERFLOW_LOW of U0 : label is 0;
attribute C_USE_COMMON_OVERFLOW : integer;
attribute C_USE_COMMON_OVERFLOW of U0 : label is 0;
attribute C_USE_COMMON_UNDERFLOW : integer;
attribute C_USE_COMMON_UNDERFLOW of U0 : label is 0;
attribute C_USE_DEFAULT_SETTINGS : integer;
attribute C_USE_DEFAULT_SETTINGS of U0 : label is 0;
attribute C_USE_DOUT_RST : integer;
attribute C_USE_DOUT_RST of U0 : label is 1;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of U0 : label is 0;
attribute C_USE_ECC_AXIS : integer;
attribute C_USE_ECC_AXIS of U0 : label is 0;
attribute C_USE_ECC_RACH : integer;
attribute C_USE_ECC_RACH of U0 : label is 0;
attribute C_USE_ECC_RDCH : integer;
attribute C_USE_ECC_RDCH of U0 : label is 0;
attribute C_USE_ECC_WACH : integer;
attribute C_USE_ECC_WACH of U0 : label is 0;
attribute C_USE_ECC_WDCH : integer;
attribute C_USE_ECC_WDCH of U0 : label is 0;
attribute C_USE_ECC_WRCH : integer;
attribute C_USE_ECC_WRCH of U0 : label is 0;
attribute C_USE_EMBEDDED_REG : integer;
attribute C_USE_EMBEDDED_REG of U0 : label is 0;
attribute C_USE_FIFO16_FLAGS : integer;
attribute C_USE_FIFO16_FLAGS of U0 : label is 0;
attribute C_USE_FWFT_DATA_COUNT : integer;
attribute C_USE_FWFT_DATA_COUNT of U0 : label is 1;
attribute C_USE_PIPELINE_REG : integer;
attribute C_USE_PIPELINE_REG of U0 : label is 0;
attribute C_VALID_LOW : integer;
attribute C_VALID_LOW of U0 : label is 0;
attribute C_WACH_TYPE : integer;
attribute C_WACH_TYPE of U0 : label is 0;
attribute C_WDCH_TYPE : integer;
attribute C_WDCH_TYPE of U0 : label is 0;
attribute C_WRCH_TYPE : integer;
attribute C_WRCH_TYPE of U0 : label is 0;
attribute C_WR_ACK_LOW : integer;
attribute C_WR_ACK_LOW of U0 : label is 0;
attribute C_WR_DATA_COUNT_WIDTH : integer;
attribute C_WR_DATA_COUNT_WIDTH of U0 : label is 5;
attribute C_WR_DEPTH : integer;
attribute C_WR_DEPTH of U0 : label is 16;
attribute C_WR_DEPTH_AXIS : integer;
attribute C_WR_DEPTH_AXIS of U0 : label is 1024;
attribute C_WR_DEPTH_RACH : integer;
attribute C_WR_DEPTH_RACH of U0 : label is 16;
attribute C_WR_DEPTH_RDCH : integer;
attribute C_WR_DEPTH_RDCH of U0 : label is 1024;
attribute C_WR_DEPTH_WACH : integer;
attribute C_WR_DEPTH_WACH of U0 : label is 16;
attribute C_WR_DEPTH_WDCH : integer;
attribute C_WR_DEPTH_WDCH of U0 : label is 1024;
attribute C_WR_DEPTH_WRCH : integer;
attribute C_WR_DEPTH_WRCH of U0 : label is 16;
attribute C_WR_FREQ : integer;
attribute C_WR_FREQ of U0 : label is 1;
attribute C_WR_PNTR_WIDTH : integer;
attribute C_WR_PNTR_WIDTH of U0 : label is 4;
attribute C_WR_PNTR_WIDTH_AXIS : integer;
attribute C_WR_PNTR_WIDTH_AXIS of U0 : label is 10;
attribute C_WR_PNTR_WIDTH_RACH : integer;
attribute C_WR_PNTR_WIDTH_RACH of U0 : label is 4;
attribute C_WR_PNTR_WIDTH_RDCH : integer;
attribute C_WR_PNTR_WIDTH_RDCH of U0 : label is 10;
attribute C_WR_PNTR_WIDTH_WACH : integer;
attribute C_WR_PNTR_WIDTH_WACH of U0 : label is 4;
attribute C_WR_PNTR_WIDTH_WDCH : integer;
attribute C_WR_PNTR_WIDTH_WDCH of U0 : label is 10;
attribute C_WR_PNTR_WIDTH_WRCH : integer;
attribute C_WR_PNTR_WIDTH_WRCH of U0 : label is 4;
attribute C_WR_RESPONSE_LATENCY : integer;
attribute C_WR_RESPONSE_LATENCY of U0 : label is 1;
begin
U0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2
port map (
almost_empty => NLW_U0_almost_empty_UNCONNECTED,
almost_full => almost_full,
axi_ar_data_count(4 downto 0) => NLW_U0_axi_ar_data_count_UNCONNECTED(4 downto 0),
axi_ar_dbiterr => NLW_U0_axi_ar_dbiterr_UNCONNECTED,
axi_ar_injectdbiterr => '0',
axi_ar_injectsbiterr => '0',
axi_ar_overflow => NLW_U0_axi_ar_overflow_UNCONNECTED,
axi_ar_prog_empty => NLW_U0_axi_ar_prog_empty_UNCONNECTED,
axi_ar_prog_empty_thresh(3 downto 0) => B"0000",
axi_ar_prog_full => NLW_U0_axi_ar_prog_full_UNCONNECTED,
axi_ar_prog_full_thresh(3 downto 0) => B"0000",
axi_ar_rd_data_count(4 downto 0) => NLW_U0_axi_ar_rd_data_count_UNCONNECTED(4 downto 0),
axi_ar_sbiterr => NLW_U0_axi_ar_sbiterr_UNCONNECTED,
axi_ar_underflow => NLW_U0_axi_ar_underflow_UNCONNECTED,
axi_ar_wr_data_count(4 downto 0) => NLW_U0_axi_ar_wr_data_count_UNCONNECTED(4 downto 0),
axi_aw_data_count(4 downto 0) => NLW_U0_axi_aw_data_count_UNCONNECTED(4 downto 0),
axi_aw_dbiterr => NLW_U0_axi_aw_dbiterr_UNCONNECTED,
axi_aw_injectdbiterr => '0',
axi_aw_injectsbiterr => '0',
axi_aw_overflow => NLW_U0_axi_aw_overflow_UNCONNECTED,
axi_aw_prog_empty => NLW_U0_axi_aw_prog_empty_UNCONNECTED,
axi_aw_prog_empty_thresh(3 downto 0) => B"0000",
axi_aw_prog_full => NLW_U0_axi_aw_prog_full_UNCONNECTED,
axi_aw_prog_full_thresh(3 downto 0) => B"0000",
axi_aw_rd_data_count(4 downto 0) => NLW_U0_axi_aw_rd_data_count_UNCONNECTED(4 downto 0),
axi_aw_sbiterr => NLW_U0_axi_aw_sbiterr_UNCONNECTED,
axi_aw_underflow => NLW_U0_axi_aw_underflow_UNCONNECTED,
axi_aw_wr_data_count(4 downto 0) => NLW_U0_axi_aw_wr_data_count_UNCONNECTED(4 downto 0),
axi_b_data_count(4 downto 0) => NLW_U0_axi_b_data_count_UNCONNECTED(4 downto 0),
axi_b_dbiterr => NLW_U0_axi_b_dbiterr_UNCONNECTED,
axi_b_injectdbiterr => '0',
axi_b_injectsbiterr => '0',
axi_b_overflow => NLW_U0_axi_b_overflow_UNCONNECTED,
axi_b_prog_empty => NLW_U0_axi_b_prog_empty_UNCONNECTED,
axi_b_prog_empty_thresh(3 downto 0) => B"0000",
axi_b_prog_full => NLW_U0_axi_b_prog_full_UNCONNECTED,
axi_b_prog_full_thresh(3 downto 0) => B"0000",
axi_b_rd_data_count(4 downto 0) => NLW_U0_axi_b_rd_data_count_UNCONNECTED(4 downto 0),
axi_b_sbiterr => NLW_U0_axi_b_sbiterr_UNCONNECTED,
axi_b_underflow => NLW_U0_axi_b_underflow_UNCONNECTED,
axi_b_wr_data_count(4 downto 0) => NLW_U0_axi_b_wr_data_count_UNCONNECTED(4 downto 0),
axi_r_data_count(10 downto 0) => NLW_U0_axi_r_data_count_UNCONNECTED(10 downto 0),
axi_r_dbiterr => NLW_U0_axi_r_dbiterr_UNCONNECTED,
axi_r_injectdbiterr => '0',
axi_r_injectsbiterr => '0',
axi_r_overflow => NLW_U0_axi_r_overflow_UNCONNECTED,
axi_r_prog_empty => NLW_U0_axi_r_prog_empty_UNCONNECTED,
axi_r_prog_empty_thresh(9 downto 0) => B"0000000000",
axi_r_prog_full => NLW_U0_axi_r_prog_full_UNCONNECTED,
axi_r_prog_full_thresh(9 downto 0) => B"0000000000",
axi_r_rd_data_count(10 downto 0) => NLW_U0_axi_r_rd_data_count_UNCONNECTED(10 downto 0),
axi_r_sbiterr => NLW_U0_axi_r_sbiterr_UNCONNECTED,
axi_r_underflow => NLW_U0_axi_r_underflow_UNCONNECTED,
axi_r_wr_data_count(10 downto 0) => NLW_U0_axi_r_wr_data_count_UNCONNECTED(10 downto 0),
axi_w_data_count(10 downto 0) => NLW_U0_axi_w_data_count_UNCONNECTED(10 downto 0),
axi_w_dbiterr => NLW_U0_axi_w_dbiterr_UNCONNECTED,
axi_w_injectdbiterr => '0',
axi_w_injectsbiterr => '0',
axi_w_overflow => NLW_U0_axi_w_overflow_UNCONNECTED,
axi_w_prog_empty => NLW_U0_axi_w_prog_empty_UNCONNECTED,
axi_w_prog_empty_thresh(9 downto 0) => B"0000000000",
axi_w_prog_full => NLW_U0_axi_w_prog_full_UNCONNECTED,
axi_w_prog_full_thresh(9 downto 0) => B"0000000000",
axi_w_rd_data_count(10 downto 0) => NLW_U0_axi_w_rd_data_count_UNCONNECTED(10 downto 0),
axi_w_sbiterr => NLW_U0_axi_w_sbiterr_UNCONNECTED,
axi_w_underflow => NLW_U0_axi_w_underflow_UNCONNECTED,
axi_w_wr_data_count(10 downto 0) => NLW_U0_axi_w_wr_data_count_UNCONNECTED(10 downto 0),
axis_data_count(10 downto 0) => NLW_U0_axis_data_count_UNCONNECTED(10 downto 0),
axis_dbiterr => NLW_U0_axis_dbiterr_UNCONNECTED,
axis_injectdbiterr => '0',
axis_injectsbiterr => '0',
axis_overflow => NLW_U0_axis_overflow_UNCONNECTED,
axis_prog_empty => NLW_U0_axis_prog_empty_UNCONNECTED,
axis_prog_empty_thresh(9 downto 0) => B"0000000000",
axis_prog_full => NLW_U0_axis_prog_full_UNCONNECTED,
axis_prog_full_thresh(9 downto 0) => B"0000000000",
axis_rd_data_count(10 downto 0) => NLW_U0_axis_rd_data_count_UNCONNECTED(10 downto 0),
axis_sbiterr => NLW_U0_axis_sbiterr_UNCONNECTED,
axis_underflow => NLW_U0_axis_underflow_UNCONNECTED,
axis_wr_data_count(10 downto 0) => NLW_U0_axis_wr_data_count_UNCONNECTED(10 downto 0),
backup => '0',
backup_marker => '0',
clk => clk,
data_count(4 downto 0) => NLW_U0_data_count_UNCONNECTED(4 downto 0),
dbiterr => NLW_U0_dbiterr_UNCONNECTED,
din(64 downto 0) => din(64 downto 0),
dout(64 downto 0) => dout(64 downto 0),
empty => empty,
full => full,
injectdbiterr => '0',
injectsbiterr => '0',
int_clk => '0',
m_aclk => '0',
m_aclk_en => '0',
m_axi_araddr(31 downto 0) => NLW_U0_m_axi_araddr_UNCONNECTED(31 downto 0),
m_axi_arburst(1 downto 0) => NLW_U0_m_axi_arburst_UNCONNECTED(1 downto 0),
m_axi_arcache(3 downto 0) => NLW_U0_m_axi_arcache_UNCONNECTED(3 downto 0),
m_axi_arid(0) => NLW_U0_m_axi_arid_UNCONNECTED(0),
m_axi_arlen(7 downto 0) => NLW_U0_m_axi_arlen_UNCONNECTED(7 downto 0),
m_axi_arlock(0) => NLW_U0_m_axi_arlock_UNCONNECTED(0),
m_axi_arprot(2 downto 0) => NLW_U0_m_axi_arprot_UNCONNECTED(2 downto 0),
m_axi_arqos(3 downto 0) => NLW_U0_m_axi_arqos_UNCONNECTED(3 downto 0),
m_axi_arready => '0',
m_axi_arregion(3 downto 0) => NLW_U0_m_axi_arregion_UNCONNECTED(3 downto 0),
m_axi_arsize(2 downto 0) => NLW_U0_m_axi_arsize_UNCONNECTED(2 downto 0),
m_axi_aruser(0) => NLW_U0_m_axi_aruser_UNCONNECTED(0),
m_axi_arvalid => NLW_U0_m_axi_arvalid_UNCONNECTED,
m_axi_awaddr(31 downto 0) => NLW_U0_m_axi_awaddr_UNCONNECTED(31 downto 0),
m_axi_awburst(1 downto 0) => NLW_U0_m_axi_awburst_UNCONNECTED(1 downto 0),
m_axi_awcache(3 downto 0) => NLW_U0_m_axi_awcache_UNCONNECTED(3 downto 0),
m_axi_awid(0) => NLW_U0_m_axi_awid_UNCONNECTED(0),
m_axi_awlen(7 downto 0) => NLW_U0_m_axi_awlen_UNCONNECTED(7 downto 0),
m_axi_awlock(0) => NLW_U0_m_axi_awlock_UNCONNECTED(0),
m_axi_awprot(2 downto 0) => NLW_U0_m_axi_awprot_UNCONNECTED(2 downto 0),
m_axi_awqos(3 downto 0) => NLW_U0_m_axi_awqos_UNCONNECTED(3 downto 0),
m_axi_awready => '0',
m_axi_awregion(3 downto 0) => NLW_U0_m_axi_awregion_UNCONNECTED(3 downto 0),
m_axi_awsize(2 downto 0) => NLW_U0_m_axi_awsize_UNCONNECTED(2 downto 0),
m_axi_awuser(0) => NLW_U0_m_axi_awuser_UNCONNECTED(0),
m_axi_awvalid => NLW_U0_m_axi_awvalid_UNCONNECTED,
m_axi_bid(0) => '0',
m_axi_bready => NLW_U0_m_axi_bready_UNCONNECTED,
m_axi_bresp(1 downto 0) => B"00",
m_axi_buser(0) => '0',
m_axi_bvalid => '0',
m_axi_rdata(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
m_axi_rid(0) => '0',
m_axi_rlast => '0',
m_axi_rready => NLW_U0_m_axi_rready_UNCONNECTED,
m_axi_rresp(1 downto 0) => B"00",
m_axi_ruser(0) => '0',
m_axi_rvalid => '0',
m_axi_wdata(63 downto 0) => NLW_U0_m_axi_wdata_UNCONNECTED(63 downto 0),
m_axi_wid(0) => NLW_U0_m_axi_wid_UNCONNECTED(0),
m_axi_wlast => NLW_U0_m_axi_wlast_UNCONNECTED,
m_axi_wready => '0',
m_axi_wstrb(7 downto 0) => NLW_U0_m_axi_wstrb_UNCONNECTED(7 downto 0),
m_axi_wuser(0) => NLW_U0_m_axi_wuser_UNCONNECTED(0),
m_axi_wvalid => NLW_U0_m_axi_wvalid_UNCONNECTED,
m_axis_tdata(7 downto 0) => NLW_U0_m_axis_tdata_UNCONNECTED(7 downto 0),
m_axis_tdest(0) => NLW_U0_m_axis_tdest_UNCONNECTED(0),
m_axis_tid(0) => NLW_U0_m_axis_tid_UNCONNECTED(0),
m_axis_tkeep(0) => NLW_U0_m_axis_tkeep_UNCONNECTED(0),
m_axis_tlast => NLW_U0_m_axis_tlast_UNCONNECTED,
m_axis_tready => '0',
m_axis_tstrb(0) => NLW_U0_m_axis_tstrb_UNCONNECTED(0),
m_axis_tuser(3 downto 0) => NLW_U0_m_axis_tuser_UNCONNECTED(3 downto 0),
m_axis_tvalid => NLW_U0_m_axis_tvalid_UNCONNECTED,
overflow => NLW_U0_overflow_UNCONNECTED,
prog_empty => NLW_U0_prog_empty_UNCONNECTED,
prog_empty_thresh(3 downto 0) => B"0000",
prog_empty_thresh_assert(3 downto 0) => B"0000",
prog_empty_thresh_negate(3 downto 0) => B"0000",
prog_full => NLW_U0_prog_full_UNCONNECTED,
prog_full_thresh(3 downto 0) => B"0000",
prog_full_thresh_assert(3 downto 0) => B"0000",
prog_full_thresh_negate(3 downto 0) => B"0000",
rd_clk => '0',
rd_data_count(4 downto 0) => NLW_U0_rd_data_count_UNCONNECTED(4 downto 0),
rd_en => rd_en,
rd_rst => '0',
rd_rst_busy => NLW_U0_rd_rst_busy_UNCONNECTED,
rst => rst,
s_aclk => '0',
s_aclk_en => '0',
s_aresetn => '0',
s_axi_araddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_arburst(1 downto 0) => B"00",
s_axi_arcache(3 downto 0) => B"0000",
s_axi_arid(0) => '0',
s_axi_arlen(7 downto 0) => B"00000000",
s_axi_arlock(0) => '0',
s_axi_arprot(2 downto 0) => B"000",
s_axi_arqos(3 downto 0) => B"0000",
s_axi_arready => NLW_U0_s_axi_arready_UNCONNECTED,
s_axi_arregion(3 downto 0) => B"0000",
s_axi_arsize(2 downto 0) => B"000",
s_axi_aruser(0) => '0',
s_axi_arvalid => '0',
s_axi_awaddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_awburst(1 downto 0) => B"00",
s_axi_awcache(3 downto 0) => B"0000",
s_axi_awid(0) => '0',
s_axi_awlen(7 downto 0) => B"00000000",
s_axi_awlock(0) => '0',
s_axi_awprot(2 downto 0) => B"000",
s_axi_awqos(3 downto 0) => B"0000",
s_axi_awready => NLW_U0_s_axi_awready_UNCONNECTED,
s_axi_awregion(3 downto 0) => B"0000",
s_axi_awsize(2 downto 0) => B"000",
s_axi_awuser(0) => '0',
s_axi_awvalid => '0',
s_axi_bid(0) => NLW_U0_s_axi_bid_UNCONNECTED(0),
s_axi_bready => '0',
s_axi_bresp(1 downto 0) => NLW_U0_s_axi_bresp_UNCONNECTED(1 downto 0),
s_axi_buser(0) => NLW_U0_s_axi_buser_UNCONNECTED(0),
s_axi_bvalid => NLW_U0_s_axi_bvalid_UNCONNECTED,
s_axi_rdata(63 downto 0) => NLW_U0_s_axi_rdata_UNCONNECTED(63 downto 0),
s_axi_rid(0) => NLW_U0_s_axi_rid_UNCONNECTED(0),
s_axi_rlast => NLW_U0_s_axi_rlast_UNCONNECTED,
s_axi_rready => '0',
s_axi_rresp(1 downto 0) => NLW_U0_s_axi_rresp_UNCONNECTED(1 downto 0),
s_axi_ruser(0) => NLW_U0_s_axi_ruser_UNCONNECTED(0),
s_axi_rvalid => NLW_U0_s_axi_rvalid_UNCONNECTED,
s_axi_wdata(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
s_axi_wid(0) => '0',
s_axi_wlast => '0',
s_axi_wready => NLW_U0_s_axi_wready_UNCONNECTED,
s_axi_wstrb(7 downto 0) => B"00000000",
s_axi_wuser(0) => '0',
s_axi_wvalid => '0',
s_axis_tdata(7 downto 0) => B"00000000",
s_axis_tdest(0) => '0',
s_axis_tid(0) => '0',
s_axis_tkeep(0) => '0',
s_axis_tlast => '0',
s_axis_tready => NLW_U0_s_axis_tready_UNCONNECTED,
s_axis_tstrb(0) => '0',
s_axis_tuser(3 downto 0) => B"0000",
s_axis_tvalid => '0',
sbiterr => NLW_U0_sbiterr_UNCONNECTED,
sleep => '0',
srst => '0',
underflow => NLW_U0_underflow_UNCONNECTED,
valid => NLW_U0_valid_UNCONNECTED,
wr_ack => NLW_U0_wr_ack_UNCONNECTED,
wr_clk => '0',
wr_data_count(4 downto 0) => NLW_U0_wr_data_count_UNCONNECTED(4 downto 0),
wr_en => wr_en,
wr_rst => '0',
wr_rst_busy => NLW_U0_wr_rst_busy_UNCONNECTED
);
end STRUCTURE;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity genericCounter is
generic (
BITS:natural := 4;
MAX_COUNT:natural := 15);
port (
clk: in std_logic;
rst: in std_logic;
ena: in std_logic;
count: out std_logic_vector(BITS-1 downto 0);
carry_o: out std_logic
);
end;
architecture genericCounter_arq of genericCounter is
begin
--El comportamiento se puede hacer de forma logica o por diagrama karnaugh.
process(clk,rst)
variable tmp_count: integer range 0 to MAX_COUNT+1;
begin
if rst = '1' then
count <= (others => '0');
carry_o <= '0';
elsif rising_edge(clk) then
if ena = '1' then
tmp_count:=tmp_count + 1;
if tmp_count = MAX_COUNT then
carry_o <= '1';
elsif tmp_count = MAX_COUNT+1 then
tmp_count := 0;
carry_o <= '0';
else
carry_o <= '0';
end if;
end if;
end if;
count <= std_logic_vector(TO_UNSIGNED(tmp_count,BITS));
end process;
end; |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity genericCounter is
generic (
BITS:natural := 4;
MAX_COUNT:natural := 15);
port (
clk: in std_logic;
rst: in std_logic;
ena: in std_logic;
count: out std_logic_vector(BITS-1 downto 0);
carry_o: out std_logic
);
end;
architecture genericCounter_arq of genericCounter is
begin
--El comportamiento se puede hacer de forma logica o por diagrama karnaugh.
process(clk,rst)
variable tmp_count: integer range 0 to MAX_COUNT+1;
begin
if rst = '1' then
count <= (others => '0');
carry_o <= '0';
elsif rising_edge(clk) then
if ena = '1' then
tmp_count:=tmp_count + 1;
if tmp_count = MAX_COUNT then
carry_o <= '1';
elsif tmp_count = MAX_COUNT+1 then
tmp_count := 0;
carry_o <= '0';
else
carry_o <= '0';
end if;
end if;
end if;
count <= std_logic_vector(TO_UNSIGNED(tmp_count,BITS));
end process;
end; |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity genericCounter is
generic (
BITS:natural := 4;
MAX_COUNT:natural := 15);
port (
clk: in std_logic;
rst: in std_logic;
ena: in std_logic;
count: out std_logic_vector(BITS-1 downto 0);
carry_o: out std_logic
);
end;
architecture genericCounter_arq of genericCounter is
begin
--El comportamiento se puede hacer de forma logica o por diagrama karnaugh.
process(clk,rst)
variable tmp_count: integer range 0 to MAX_COUNT+1;
begin
if rst = '1' then
count <= (others => '0');
carry_o <= '0';
elsif rising_edge(clk) then
if ena = '1' then
tmp_count:=tmp_count + 1;
if tmp_count = MAX_COUNT then
carry_o <= '1';
elsif tmp_count = MAX_COUNT+1 then
tmp_count := 0;
carry_o <= '0';
else
carry_o <= '0';
end if;
end if;
end if;
count <= std_logic_vector(TO_UNSIGNED(tmp_count,BITS));
end process;
end; |
----------------------------------------------------------------------------
-- This file is a part of the LEON VHDL model
-- Copyright (C) 1999 European Space Agency (ESA)
--
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2 of the License, or (at your option) any later version.
--
-- See the file COPYING.LGPL for the full details of the license.
-----------------------------------------------------------------------------
-- Entity: pci
-- File: pci.vhd
-- Author: Jiri Gaisler - Gaisler Reserch
-- Description: Module containing all possible PCI cores
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use work.target.all;
use work.config.all;
use work.iface.all;
use work.amba.all;
use work.ambacomp.all;
entity pci is
port (
resetn : in std_logic;
clk : in clk_type;
pcii : in pci_in_type;
pcio : out pci_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
ahbmi1 : in ahb_mst_in_type;
ahbmo1 : out ahb_mst_out_type;
ahbmi2 : in ahb_mst_in_type;
ahbmo2 : out ahb_mst_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
irq : out std_logic
;clk_out: out std_logic
);
end;
architecture rtl of pci is
signal gnd4 : std_logic_vector(3 downto 0);
begin
-- InSilicon PCI core
pci_is0 : if PCICORE = insilicon generate
pci0 : pci_is
port map (
rst_n =>resetn, app_clk => clk, pci_clk => pcii.pci_clk_in,
pbi => apbi, pbo => apbo, irq => irq,
TargetMasterOut => ahbmo1, TargetMasterIn => ahbmi1,
pci_in => pcii, pci_out => pcio,
InitSlaveOut => ahbso, InitSlaveIn => ahbsi,
InitMasterOut => ahbmo2, InitMasterIn => ahbmi2
);
end generate;
pci_actel0 : if PCICORE = actel generate
-- pci0 : pci_actel
-- generic map (
-- USER_DEVICE_ID => PCI_DEVICE_ID, USER_VENDOR_ID => PCI_VENDOR_ID,
-- USER_REVISION_ID => PCI_REVISION_ID, USER_SUBSYSTEM_ID => PCI_SUBSYS_ID,
-- USER_BASE_CLASS => PCI_CLASS_CODE)
-- port map (
-- rst => resetn, clk => pcii.pci_clk_in, clk_out => clk_out, pcii => pcii, pcio => pcio,
-- ahbmi => ahbmi1, ahbmo => ahbmo1, ahbsi => ahbsi, ahbso => ahbso
-- );
--
-- ahbmo2.hbusreq <= '0';
-- ahbmo2.hlock <= '0';
-- ahbmo2.htrans <= HTRANS_IDLE;
-- ahbmo2.haddr <= (others => '0');
-- ahbmo2.hwrite <= '0';
-- ahbmo2.hburst <= HBURST_SINGLE;
-- ahbmo2.hprot <= (others => '0');
-- ahbmo2.hwdata <= (others => '0');
-- irq <= '0';
end generate;
-- Optional ESA PCI core
-- pci_esa0 : if PCICORE = esa generate
-- pci0 : pci_esa
-- port map (
-- resetn => rst.syncrst, app_clk => clko.clk,
-- pci_in => pcii, pci_out => pcio,
-- ahbmasterin => ahbmi(1), ahbmasterout => ahbmo(1),
-- ahbslavein => ahbsi(2), ahbslaveout => ahbso(2),
-- apbslavein => apbi(10), apbslaveout => apbo(10), irq => pciirq
-- );
-- pciresetn <= pcii.pci_rst_in_n;
-- end generate;
end ;
|
--
-------------------------------------------------------------------------------------------
-- Copyright © 2011, Xilinx, Inc.
-- This file contains confidential and proprietary information of Xilinx, Inc. and is
-- protected under U.S. and international copyright and other intellectual property laws.
-------------------------------------------------------------------------------------------
--
-- Disclaimer:
-- This disclaimer is not a license and does not grant any rights to the materials
-- distributed herewith. Except as otherwise provided in a valid license issued to
-- you by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE
-- MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY
-- DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY,
-- INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT,
-- OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable
-- (whether in contract or tort, including negligence, or under any other theory
-- of liability) for any loss or damage of any kind or nature related to, arising
-- under or in connection with these materials, including for any direct, or any
-- indirect, special, incidental, or consequential loss or damage (including loss
-- of data, profits, goodwill, or any type of loss or damage suffered as a result
-- of any action brought by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-safe, or for use in any
-- application requiring fail-safe performance, such as life-support or safety
-- devices or systems, Class III medical devices, nuclear facilities, applications
-- related to the deployment of airbags, or any other applications that could lead
-- to death, personal injury, or severe property or environmental damage
-- (individually and collectively, "Critical Applications"). Customer assumes the
-- sole risk and liability of any use of Xilinx products in Critical Applications,
-- subject only to applicable laws and regulations governing limitations on product
-- liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------------------
--
-- UART Receiver with integral 16 byte FIFO buffer
--
-- 8 bit, no parity, 1 stop bit
--
-- This module was made for use with Spartan-6 Generation Devices and is also ideally
-- suited for use with Virtex-6 and 7-Series devices.
--
-- Version 1 - 31st March 2011.
--
-- Ken Chapman
-- Xilinx Ltd
-- Benchmark House
-- 203 Brooklands Road
-- Weybridge
-- Surrey KT13 ORH
-- United Kingdom
--
-- [email protected]
--
-------------------------------------------------------------------------------------------
--
-- Format of this file.
--
-- The module defines the implementation of the logic using Xilinx primitives.
-- These ensure predictable synthesis results and maximise the density of the
-- implementation. The Unisim Library is used to define Xilinx primitives. It is also
-- used during simulation.
-- The source can be viewed at %XILINX%\vhdl\src\unisims\unisim_VCOMP.vhd
--
-------------------------------------------------------------------------------------------
--
-- Library declarations
--
-- Standard IEEE libraries
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library unisim;
use unisim.vcomponents.all;
--
-------------------------------------------------------------------------------------------
--
-- Main Entity for
--
entity uart_rx6 is
Port ( serial_in : in std_logic;
en_16_x_baud : in std_logic;
data_out : out std_logic_vector(7 downto 0);
buffer_read : in std_logic;
buffer_data_present : out std_logic;
buffer_half_full : out std_logic;
buffer_full : out std_logic;
buffer_reset : in std_logic;
clk : in std_logic);
end uart_rx6;
--
-------------------------------------------------------------------------------------------
--
-- Start of Main Architecture for uart_rx6
--
architecture low_level_definition of uart_rx6 is
--
-------------------------------------------------------------------------------------------
--
-- Signals used in uart_rx6
--
-------------------------------------------------------------------------------------------
--
signal pointer_value : std_logic_vector(3 downto 0);
signal pointer : std_logic_vector(3 downto 0);
signal en_pointer : std_logic;
signal zero : std_logic;
signal full_int : std_logic;
signal data_present_value : std_logic;
signal data_present_int : std_logic;
signal sample_value : std_logic;
signal sample : std_logic;
signal sample_dly_value : std_logic;
signal sample_dly : std_logic;
signal stop_bit_value : std_logic;
signal stop_bit : std_logic;
signal data_value : std_logic_vector(7 downto 0);
signal data : std_logic_vector(7 downto 0);
signal run_value : std_logic;
signal run : std_logic;
signal start_bit_value : std_logic;
signal start_bit : std_logic;
signal div_value : std_logic_vector(3 downto 0);
signal div : std_logic_vector(3 downto 0);
signal div_carry : std_logic;
signal sample_input_value : std_logic;
signal sample_input : std_logic;
signal buffer_write_value : std_logic;
signal buffer_write : std_logic;
--
-------------------------------------------------------------------------------------------
--
-- Attributes to guide mapping of logic into Slices.
-------------------------------------------------------------------------------------------
--
--
attribute hblknm : string;
attribute hblknm of pointer3_lut : label is "uart_rx6_1";
attribute hblknm of pointer3_flop : label is "uart_rx6_1";
attribute hblknm of pointer2_lut : label is "uart_rx6_1";
attribute hblknm of pointer2_flop : label is "uart_rx6_1";
attribute hblknm of pointer01_lut : label is "uart_rx6_1";
attribute hblknm of pointer1_flop : label is "uart_rx6_1";
attribute hblknm of pointer0_flop : label is "uart_rx6_1";
attribute hblknm of data_present_lut : label is "uart_rx6_1";
attribute hblknm of data_present_flop : label is "uart_rx6_1";
--
attribute hblknm of data01_lut : label is "uart_rx6_2";
attribute hblknm of data0_flop : label is "uart_rx6_2";
attribute hblknm of data1_flop : label is "uart_rx6_2";
attribute hblknm of data23_lut : label is "uart_rx6_2";
attribute hblknm of data2_flop : label is "uart_rx6_2";
attribute hblknm of data3_flop : label is "uart_rx6_2";
attribute hblknm of data45_lut : label is "uart_rx6_2";
attribute hblknm of data4_flop : label is "uart_rx6_2";
attribute hblknm of data5_flop : label is "uart_rx6_2";
attribute hblknm of data67_lut : label is "uart_rx6_2";
attribute hblknm of data6_flop : label is "uart_rx6_2";
attribute hblknm of data7_flop : label is "uart_rx6_2";
--
attribute hblknm of div01_lut : label is "uart_rx6_3";
attribute hblknm of div23_lut : label is "uart_rx6_3";
attribute hblknm of div0_flop : label is "uart_rx6_3";
attribute hblknm of div1_flop : label is "uart_rx6_3";
attribute hblknm of div2_flop : label is "uart_rx6_3";
attribute hblknm of div3_flop : label is "uart_rx6_3";
attribute hblknm of sample_input_lut : label is "uart_rx6_3";
attribute hblknm of sample_input_flop : label is "uart_rx6_3";
attribute hblknm of full_lut : label is "uart_rx6_3";
--
attribute hblknm of sample_lut : label is "uart_rx6_4";
attribute hblknm of sample_flop : label is "uart_rx6_4";
attribute hblknm of sample_dly_flop : label is "uart_rx6_4";
attribute hblknm of stop_bit_lut : label is "uart_rx6_4";
attribute hblknm of stop_bit_flop : label is "uart_rx6_4";
attribute hblknm of buffer_write_flop : label is "uart_rx6_4";
attribute hblknm of start_bit_lut : label is "uart_rx6_4";
attribute hblknm of start_bit_flop : label is "uart_rx6_4";
attribute hblknm of run_lut : label is "uart_rx6_4";
attribute hblknm of run_flop : label is "uart_rx6_4";
--
--
-------------------------------------------------------------------------------------------
--
-- Start of uart_rx6 circuit description
--
-------------------------------------------------------------------------------------------
--
begin
-- SRL16E data storage
data_width_loop: for i in 0 to 7 generate
attribute hblknm : string;
attribute hblknm of storage_srl : label is "uart_rx6_5";
begin
storage_srl: SRL16E
generic map (INIT => X"0000")
port map( D => data(i),
CE => buffer_write,
CLK => clk,
A0 => pointer(0),
A1 => pointer(1),
A2 => pointer(2),
A3 => pointer(3),
Q => data_out(i) );
end generate data_width_loop;
pointer3_lut: LUT6
generic map (INIT => X"FF00FE00FF80FF00")
port map( I0 => pointer(0),
I1 => pointer(1),
I2 => pointer(2),
I3 => pointer(3),
I4 => buffer_write,
I5 => buffer_read,
O => pointer_value(3));
pointer3_flop: FDR
port map ( D => pointer_value(3),
Q => pointer(3),
R => buffer_reset,
C => clk);
pointer2_lut: LUT6
generic map (INIT => X"F0F0E1E0F878F0F0")
port map( I0 => pointer(0),
I1 => pointer(1),
I2 => pointer(2),
I3 => pointer(3),
I4 => buffer_write,
I5 => buffer_read,
O => pointer_value(2));
pointer2_flop: FDR
port map ( D => pointer_value(2),
Q => pointer(2),
R => buffer_reset,
C => clk);
pointer01_lut: LUT6_2
generic map (INIT => X"CC9060CCAA5050AA")
port map( I0 => pointer(0),
I1 => pointer(1),
I2 => en_pointer,
I3 => buffer_write,
I4 => buffer_read,
I5 => '1',
O5 => pointer_value(0),
O6 => pointer_value(1));
pointer1_flop: FDR
port map ( D => pointer_value(1),
Q => pointer(1),
R => buffer_reset,
C => clk);
pointer0_flop: FDR
port map ( D => pointer_value(0),
Q => pointer(0),
R => buffer_reset,
C => clk);
data_present_lut: LUT6_2
generic map (INIT => X"F4FCF4FC040004C0")
port map( I0 => zero,
I1 => data_present_int,
I2 => buffer_write,
I3 => buffer_read,
I4 => full_int,
I5 => '1',
O5 => en_pointer,
O6 => data_present_value);
data_present_flop: FDR
port map ( D => data_present_value,
Q => data_present_int,
R => buffer_reset,
C => clk);
full_lut: LUT6_2
generic map (INIT => X"0001000080000000")
port map( I0 => pointer(0),
I1 => pointer(1),
I2 => pointer(2),
I3 => pointer(3),
I4 => '1',
I5 => '1',
O5 => full_int,
O6 => zero);
sample_lut: LUT6_2
generic map (INIT => X"CCF00000AACC0000")
port map( I0 => serial_in,
I1 => sample,
I2 => sample_dly,
I3 => en_16_x_baud,
I4 => '1',
I5 => '1',
O5 => sample_value,
O6 => sample_dly_value);
sample_flop: FD
port map ( D => sample_value,
Q => sample,
C => clk);
sample_dly_flop: FD
port map ( D => sample_dly_value,
Q => sample_dly,
C => clk);
stop_bit_lut: LUT6_2
generic map (INIT => X"CAFFCAFF0000C0C0")
port map( I0 => stop_bit,
I1 => sample,
I2 => sample_input,
I3 => run,
I4 => data(0),
I5 => '1',
O5 => buffer_write_value,
O6 => stop_bit_value);
buffer_write_flop: FD
port map ( D => buffer_write_value,
Q => buffer_write,
C => clk);
stop_bit_flop: FD
port map ( D => stop_bit_value,
Q => stop_bit,
C => clk);
data01_lut: LUT6_2
generic map (INIT => X"F0CCFFFFCCAAFFFF")
port map( I0 => data(0),
I1 => data(1),
I2 => data(2),
I3 => sample_input,
I4 => run,
I5 => '1',
O5 => data_value(0),
O6 => data_value(1));
data0_flop: FD
port map ( D => data_value(0),
Q => data(0),
C => clk);
data1_flop: FD
port map ( D => data_value(1),
Q => data(1),
C => clk);
data23_lut: LUT6_2
generic map (INIT => X"F0CCFFFFCCAAFFFF")
port map( I0 => data(2),
I1 => data(3),
I2 => data(4),
I3 => sample_input,
I4 => run,
I5 => '1',
O5 => data_value(2),
O6 => data_value(3));
data2_flop: FD
port map ( D => data_value(2),
Q => data(2),
C => clk);
data3_flop: FD
port map ( D => data_value(3),
Q => data(3),
C => clk);
data45_lut: LUT6_2
generic map (INIT => X"F0CCFFFFCCAAFFFF")
port map( I0 => data(4),
I1 => data(5),
I2 => data(6),
I3 => sample_input,
I4 => run,
I5 => '1',
O5 => data_value(4),
O6 => data_value(5));
data4_flop: FD
port map ( D => data_value(4),
Q => data(4),
C => clk);
data5_flop: FD
port map ( D => data_value(5),
Q => data(5),
C => clk);
data67_lut: LUT6_2
generic map (INIT => X"F0CCFFFFCCAAFFFF")
port map( I0 => data(6),
I1 => data(7),
I2 => stop_bit,
I3 => sample_input,
I4 => run,
I5 => '1',
O5 => data_value(6),
O6 => data_value(7));
data6_flop: FD
port map ( D => data_value(6),
Q => data(6),
C => clk);
data7_flop: FD
port map ( D => data_value(7),
Q => data(7),
C => clk);
run_lut: LUT6
generic map (INIT => X"2F2FAFAF0000FF00")
port map( I0 => data(0),
I1 => start_bit,
I2 => sample_input,
I3 => sample_dly,
I4 => sample,
I5 => run,
O => run_value);
run_flop: FD
port map ( D => run_value,
Q => run,
C => clk);
start_bit_lut: LUT6
generic map (INIT => X"222200F000000000")
port map( I0 => start_bit,
I1 => sample_input,
I2 => sample_dly,
I3 => sample,
I4 => run,
I5 => '1',
O => start_bit_value);
start_bit_flop: FD
port map ( D => start_bit_value,
Q => start_bit,
C => clk);
div01_lut: LUT6_2
generic map (INIT => X"6C0000005A000000")
port map( I0 => div(0),
I1 => div(1),
I2 => en_16_x_baud,
I3 => run,
I4 => '1',
I5 => '1',
O5 => div_value(0),
O6 => div_value(1));
div0_flop: FD
port map ( D => div_value(0),
Q => div(0),
C => clk);
div1_flop: FD
port map ( D => div_value(1),
Q => div(1),
C => clk);
div23_lut: LUT6_2
generic map (INIT => X"6CCC00005AAA0000")
port map( I0 => div(2),
I1 => div(3),
I2 => div_carry,
I3 => en_16_x_baud,
I4 => run,
I5 => '1',
O5 => div_value(2),
O6 => div_value(3));
div2_flop: FD
port map ( D => div_value(2),
Q => div(2),
C => clk);
div3_flop: FD
port map ( D => div_value(3),
Q => div(3),
C => clk);
sample_input_lut: LUT6_2
generic map (INIT => X"0080000088888888")
port map( I0 => div(0),
I1 => div(1),
I2 => div(2),
I3 => div(3),
I4 => en_16_x_baud,
I5 => '1',
O5 => div_carry,
O6 => sample_input_value);
sample_input_flop: FD
port map ( D => sample_input_value,
Q => sample_input,
C => clk);
-- assign internal signals to outputs
buffer_full <= full_int;
buffer_half_full <= pointer(3);
buffer_data_present <= data_present_int;
end low_level_definition;
-------------------------------------------------------------------------------------------
--
-- END OF FILE uart_rx6.vhd
--
-------------------------------------------------------------------------------------------
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 18:11:19 04/22/2016
-- Design Name:
-- Module Name: SH_PCREG - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity SH_PCREG is
generic( PCWIDTH:integer:=5;
STACKDEPTH:integer:=4);
Port (CLK : in STD_LOGIC;
RST : in STD_LOGIC;
ADRIN : in STD_LOGIC_VECTOR(PCWIDTH-1 downto 0);
EN : in STD_LOGIC;
WR : in STD_LOGIC; -- '1' is Push, '0' is Pop
ADROUT : buffer STD_LOGIC_VECTOR(PCWIDTH-1 downto 0);
OVFLW : out STD_LOGIC);
end SH_PCREG;
architecture Behavioral of SH_PCREG is
type REG_ARRAY_TYPE is array (0 to STACKDEPTH-2) of STD_LOGIC_VECTOR(PCWIDTH-1 downto 0);
signal PC_STACK: REG_ARRAY_TYPE;
begin
--ADROUT <= PC_STACK(0);
process(CLK,RST)
begin
if RST = '1' then
PC_STACK <= (OTHERS => (OTHERS => '0'));
ADROUT <= (OTHERS => '0');
elsif (CLK'event and CLK = '1' and EN = '1') then
case WR is
when '1' =>
-- case PC_STACK(3) is
-- when "00000" => OVFLW <= '0';
-- when OTHERS => OVFLW <= '1';
-- end case;
PC_STACK(2) <= PC_STACK(1);
PC_STACK(1) <= PC_STACK(0);
PC_STACK(0) <= ADROUT;
ADROUT <= ADRIN;
-- ADROUT <= PC_STACK(0);
WHEN '0' =>
-- ADROUT <= PC_STACK(0);
ADROUT <= PC_STACK(0);
PC_STACK(0) <= PC_STACK(1);
PC_STACK(1) <= PC_STACK(2);
PC_STACK(2) <= (OTHERS => '0');
when OTHERS => ADROUT <= ADRIN; -- Sort of a do nothing
end case;
-- ADROUT <= PC_STACK(0);
end if;
end process;
end Behavioral;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 18:11:19 04/22/2016
-- Design Name:
-- Module Name: SH_PCREG - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity SH_PCREG is
generic( PCWIDTH:integer:=5;
STACKDEPTH:integer:=4);
Port (CLK : in STD_LOGIC;
RST : in STD_LOGIC;
ADRIN : in STD_LOGIC_VECTOR(PCWIDTH-1 downto 0);
EN : in STD_LOGIC;
WR : in STD_LOGIC; -- '1' is Push, '0' is Pop
ADROUT : buffer STD_LOGIC_VECTOR(PCWIDTH-1 downto 0);
OVFLW : out STD_LOGIC);
end SH_PCREG;
architecture Behavioral of SH_PCREG is
type REG_ARRAY_TYPE is array (0 to STACKDEPTH-2) of STD_LOGIC_VECTOR(PCWIDTH-1 downto 0);
signal PC_STACK: REG_ARRAY_TYPE;
begin
--ADROUT <= PC_STACK(0);
process(CLK,RST)
begin
if RST = '1' then
PC_STACK <= (OTHERS => (OTHERS => '0'));
ADROUT <= (OTHERS => '0');
elsif (CLK'event and CLK = '1' and EN = '1') then
case WR is
when '1' =>
-- case PC_STACK(3) is
-- when "00000" => OVFLW <= '0';
-- when OTHERS => OVFLW <= '1';
-- end case;
PC_STACK(2) <= PC_STACK(1);
PC_STACK(1) <= PC_STACK(0);
PC_STACK(0) <= ADROUT;
ADROUT <= ADRIN;
-- ADROUT <= PC_STACK(0);
WHEN '0' =>
-- ADROUT <= PC_STACK(0);
ADROUT <= PC_STACK(0);
PC_STACK(0) <= PC_STACK(1);
PC_STACK(1) <= PC_STACK(2);
PC_STACK(2) <= (OTHERS => '0');
when OTHERS => ADROUT <= ADRIN; -- Sort of a do nothing
end case;
-- ADROUT <= PC_STACK(0);
end if;
end process;
end Behavioral;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 18:11:19 04/22/2016
-- Design Name:
-- Module Name: SH_PCREG - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity SH_PCREG is
generic( PCWIDTH:integer:=5;
STACKDEPTH:integer:=4);
Port (CLK : in STD_LOGIC;
RST : in STD_LOGIC;
ADRIN : in STD_LOGIC_VECTOR(PCWIDTH-1 downto 0);
EN : in STD_LOGIC;
WR : in STD_LOGIC; -- '1' is Push, '0' is Pop
ADROUT : buffer STD_LOGIC_VECTOR(PCWIDTH-1 downto 0);
OVFLW : out STD_LOGIC);
end SH_PCREG;
architecture Behavioral of SH_PCREG is
type REG_ARRAY_TYPE is array (0 to STACKDEPTH-2) of STD_LOGIC_VECTOR(PCWIDTH-1 downto 0);
signal PC_STACK: REG_ARRAY_TYPE;
begin
--ADROUT <= PC_STACK(0);
process(CLK,RST)
begin
if RST = '1' then
PC_STACK <= (OTHERS => (OTHERS => '0'));
ADROUT <= (OTHERS => '0');
elsif (CLK'event and CLK = '1' and EN = '1') then
case WR is
when '1' =>
-- case PC_STACK(3) is
-- when "00000" => OVFLW <= '0';
-- when OTHERS => OVFLW <= '1';
-- end case;
PC_STACK(2) <= PC_STACK(1);
PC_STACK(1) <= PC_STACK(0);
PC_STACK(0) <= ADROUT;
ADROUT <= ADRIN;
-- ADROUT <= PC_STACK(0);
WHEN '0' =>
-- ADROUT <= PC_STACK(0);
ADROUT <= PC_STACK(0);
PC_STACK(0) <= PC_STACK(1);
PC_STACK(1) <= PC_STACK(2);
PC_STACK(2) <= (OTHERS => '0');
when OTHERS => ADROUT <= ADRIN; -- Sort of a do nothing
end case;
-- ADROUT <= PC_STACK(0);
end if;
end process;
end Behavioral;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: rstgen
-- File: rstgen.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Reset generation with glitch filter
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
entity rstgen is
generic (
acthigh : integer := 0;
syncrst : integer := 0;
scanen : integer := 0;
syncin : integer := 0);
port (
rstin : in std_ulogic;
clk : in std_ulogic;
clklock : in std_ulogic;
rstout : out std_ulogic;
rstoutraw : out std_ulogic;
testrst : in std_ulogic := '0';
testen : in std_ulogic := '0'
);
end;
architecture rtl of rstgen is
signal r : std_logic_vector(4 downto 0);
signal rst, rstoutl, clklockl, arst : std_ulogic;
signal rstsyncin : std_ulogic;
signal inrst_syncreg : std_ulogic;
signal genrst : std_ulogic;
signal genrst_syncreg : std_logic_vector(1 downto 0);
begin
nosyncinrst : if syncin = 0 generate
rst <= not rstin when acthigh = 1 else rstin;
clklockl <= clklock;
end generate;
syncinrst : if syncin = 1 generate
rstsyncin <= not rstin when acthigh = 1 else rstin;
syncreg0 : syncreg port map (clk, rstsyncin, inrst_syncreg);
genrst <= testrst when (scanen = 1) and (testen = '1') else inrst_syncreg;
gensyncrest : process (clk, genrst) begin
if rising_edge(clk) then
genrst_syncreg(0) <= '1';
genrst_syncreg(1) <= genrst_syncreg(0);
end if;
if ( genrst = '0') then genrst_syncreg <= (others => '0'); end if;
end process;
rst <= genrst_syncreg(1);
syncreg1 : syncreg port map (clk, clklock, clklockl);
end generate;
rstoutraw <= not rstin when acthigh = 1 else rstin;
arst <= testrst when (scanen = 1) and (testen = '1') else rst;
async : if (syncrst = 0 and syncin = 0) generate
reg1 : process (clk, arst) begin
if rising_edge(clk) then
r <= r(3 downto 0) & clklockl;
rstoutl <= r(4) and r(3) and r(2);
end if;
if (arst = '0') then r <= "00000"; rstoutl <= '0'; end if;
end process;
rstout <= (rstoutl and rst) when scanen = 1 else rstoutl;
end generate;
sync : if (syncrst = 1 or syncin = 1) generate
reg1 : process (clk) begin
if rising_edge(clk) then
r <= (r(3 downto 0) & clklockl) and (rst & rst & rst & rst & rst);
rstoutl <= r(4) and r(3) and r(2);
end if;
end process;
rstout <= rstoutl and rst;
end generate;
end;
|
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
-------------------------------------------------------------------------------
-- This file is part of the Queens@TUD solver suite
-- for enumerating and counting the solutions of an N-Queens Puzzle.
--
-- Copyright (C) 2008-2015
-- Thomas B. Preusser <[email protected]>
-------------------------------------------------------------------------------
-- This design is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Affero General Public License as published
-- by the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU Affero General Public License for more details.
--
-- You should have received a copy of the GNU Affero General Public License
-- along with this design. If not, see <http://www.gnu.org/licenses/>.
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity ml505_queens_uart is
generic (
N : positive := 27;
L : positive := 2;
SOLVERS : positive := 21;
COUNT_CYCLES : boolean := false;
CLK_FREQ : positive := 100000000;
CLK_MUL : positive := 16;
CLK_DIV : positive := 9;
BAUDRATE : positive := 115200;
SENTINEL : std_logic_vector(7 downto 0) := x"FA" -- Start Byte
);
port (
clkx : in std_logic;
rstx : in std_logic;
rx : in std_logic;
tx : out std_logic;
leds : out std_logic_vector(0 to 7)
);
end ml505_queens_uart;
library IEEE;
use IEEE.numeric_std.all;
library UNISIM;
use UNISIM.vcomponents.all;
architecture rtl of ml505_queens_uart is
-- Global Control
signal clk : std_logic;
signal rst : std_logic;
-- Solver Status
signal snap : std_logic_vector(3 downto 0);
signal avail : std_logic;
begin
-----------------------------------------------------------------------------
-- Generate Global Controls
blkGlobal: block is
signal clk_u : std_logic; -- Unbuffered Synthesized Clock
signal rst_s : std_logic_vector(1 downto 0) := (others => '0');
begin
DCM0 : DCM_BASE
generic map (
CLKIN_PERIOD => 1000000000.0/real(CLK_FREQ),
CLKIN_DIVIDE_BY_2 => FALSE,
PHASE_SHIFT => 0,
CLKFX_MULTIPLY => CLK_MUL,
CLKFX_DIVIDE => CLK_DIV,
CLKOUT_PHASE_SHIFT => "NONE",
CLK_FEEDBACK => "NONE", -- only using clkfx
DLL_FREQUENCY_MODE => "HIGH",
DFS_FREQUENCY_MODE => "HIGH",
DUTY_CYCLE_CORRECTION => TRUE,
STARTUP_WAIT => TRUE -- Delay until DCM LOCK
)
port map (
CLK0 => open,
CLK180 => open,
CLK270 => open,
CLK2X => open,
CLK2X180 => open,
CLK90 => open,
CLKDV => open,
CLKFX => clk_u,
CLKFX180 => open,
LOCKED => open,
CLKFB => '0',
CLKIN => clkx,
RST => '0'
);
clk_buf : BUFG
port map (
I => clk_u,
O => clk
);
-- Reset Synchronization
process(clk)
begin
if rising_edge(clk) then
rst_s <= (not rstx) & rst_s(rst_s'left downto 1);
end if;
end process;
rst <= rst_s(0);
end block blkGlobal;
----------------------------------------------------------------------------
-- Solver Chain
chain: entity work.queens_uart
generic map (
N => N,
L => L,
SOLVERS => SOLVERS,
COUNT_CYCLES => COUNT_CYCLES,
CLK_FREQ => integer((real(CLK_MUL)*real(CLK_FREQ))/real(CLK_DIV)),
BAUDRATE => BAUDRATE,
SENTINEL => SENTINEL
)
port map (
clk => clk,
rst => rst,
rx => rx,
tx => tx,
snap => snap,
avail => avail
);
----------------------------------------------------------------------------
-- Basic Status Output
leds <= snap & std_logic_vector(to_unsigned((SOLVERS mod 7)+1, 3)) & avail;
end rtl;
|
library IEEE;
use IEEE.Std_Logic_1164.all;
entity FA is
port (A : in std_logic;
B : in std_logic;
C : in std_logic;
COUT : out std_logic;
S : out std_logic
);
end FA;
architecture fa_estr of FA is
begin
COUT <= (A and B) or (A and C) or (C and B);
S <= ((not C) and (A xor B)) or (C and (A xnor B));
end fa_estr; |
------------------------------
library ieee;
use ieee.std_logic_1164.all;
------------------------------
entity circuit is
--generic declarations
port (
a: in std_logic;
b: in std_logic;
c: in std_logic;
clk: in std_logic;
reg_z: out std_logic);
end entity;
------------------------------
architecture circuit of circuit is
signal z: std_logic;
begin
z <= a xor ((a nand b) or c);
process (clk)
begin
if (clk'event and clk = '1') then
reg_z <= z;
end if;
end process;
end architecture;
------------------------------
|
------------------------------------------------------------------------
-- ps2interface.vhd
------------------------------------------------------------------------
-- Author : Ulrich Zoltán
-- Copyright 2006 Digilent, Inc.
------------------------------------------------------------------------
-- This file contains the implementation of a generic bidirectional
-- ps/2 interface.
------------------------------------------------------------------------
-- Behavioral description
------------------------------------------------------------------------
-- Please read the following article on the web for understanding how
-- the ps/2 protocol works.
-- http://www.computer-engineering.org/ps2protocol/
-- This module implements a generic bidirectional ps/2 interface. It can
-- be used with any ps/2 compatible device. It offers its clients a
-- convenient way to exchange data with the device. The interface
-- transparently wraps the byte to be sent into a ps/2 frame, generates
-- parity for byte and sends the frame one bit at a time to the device.
-- Similarly, when receiving data from the ps2 device, the interface
-- receives the frame, checks for parity, and extract the usefull data
-- and forwards it to the client. If an error occurs during receiving
-- or sending a byte, the client is informed by settings the err output
-- line high. This way, the client can resend the data or can issue
-- a resend command to the device.
-- The physical ps/2 interface uses 4 lines
-- For the 6-pin connector pins are assigned as follows:
-- 1 - Data
-- 2 - Not Implemented
-- 3 - Ground
-- 4 - Vcc (+5V)
-- 5 - Clock
-- 6 - Not Implemented
-- The clock line carries the device generated clock which has a
-- frequency in range 10 - 16.7 kHz (30 to 50us). When line is idle
-- it is placed in high impedance. The clock is only generated when
-- device is sending or receiving data.
-- The Data and Clock lines are both open-collector with pullup
-- resistors to Vcc. An "open-collector" interface has two possible
-- states: low('0') or high impedance('Z').
-- When device wants to send a byte, it pulls the clock line low and the
-- host(i.e. this interfaces) recognizes that the device is sending data
-- When the host wants to send data, it maeks a request to send. This
-- is done by holding the clock line low for at least 100us, then with
-- the clock line low, the data line is brought low. Next the clock line
-- is released (placed in high impedance). The devices begins generating
-- clock signal on clock line.
-- When receiving data, bits are read from the data line (ps2_data) on
-- the falling edge of the clock (ps2_clk). When sending data, the
-- device reads the bits from the data line on the rising edge of the
-- clock.
-- A frame for sending a byte is comprised of 11 bits as shown bellow:
-- bits 10 9 8 7 6 5 4 3 2 1 0
-- -------------------------------------------------------------
-- | STOP| PAR | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 | START |
-- -------------------------------------------------------------
-- STOP - stop bit, always '1'
-- PAR - parity bit, odd parity for the 8 data bits.
-- - select in such way that the number of bits of '1' in the data
-- - bits together with parity bit is odd.
-- D0-7 - data bits.
-- START - start bit, always '0'
--
-- Frame is sent bit by bit starting with the least significant bit
-- (starting bit) and is received the same way. This is done, when
-- receiving, by shifting the frame register to the left when a bit
-- is available and placing the bit on data line on the most significant
-- bit. This way the first bit sent will reach the least significant bit
-- of the frame when all the bits have been received. When sending data
-- the least significant bit of the frame is placed on the data line
-- and the frame is shifted to the right when another bit needs to be
-- sent. During the request to send, when releasing the clock line,
-- the device reads the data line and interprets the data on it as the
-- first bit of the frame. Data line is low at that time, at this is the
-- way the start bit('0') is sent. Because of this, when sending, only
-- 10 shifts of the frame will be made.
-- While the interface is sending or receiving data, the busy output
-- signal goes high. When interface is idle, busy is low.
-- After sending all the bits in the frame, the device must acknowledge
-- the data sent. This is done by the host releasing and data line
-- (clock line is already released) after the last bit is sent. The
-- devices brings the data line and the clock line low, in this order,
-- to acknowledge the data. If data line is high when clock line goes
-- low after last bit, the device did not acknowledge the data and
-- err output is set.
-- A FSM is used to manage the transitions the set all the command
-- signals. States that begin with "rx_" are used to receive data
-- from device and states begining with "tx_" are used to send data
-- to the device.
-- For the parity bit, a ROM holds the parity bit for all possible
-- data (256 possible values, since 8 bits of data). The ROM has
-- dimensions 256x1bit. For obtaining the parity bit of a value,
-- the bit at the data value address is read. Ex: to find the parity
-- bit of 174, the bit at address 174 is read.
-- For generating the necessary delay, counters are used. For example,
-- to generate the 100us delay a 14 bit counter is used that has the
-- upper limit for counting 10000. The interface is designed to run
-- at 100MHz. Thus, 10000x10ns = 100us.
-----------------------------------------------------------------------
-- If using the interface at different frequency than 100MHz, adjusting
-- the delay counters is necessary!!!
-----------------------------------------------------------------------
-- Clock line(ps2_clk) and data line(ps2_data) are passed through a
-- debouncer for the transitions of the clock and data to be clean.
-- Also, ps2_clk_s and ps2_data_s hold the debounced and synchronized
-- value of the clock and data line to the system clock(clk).
------------------------------------------------------------------------
-- Port definitions
------------------------------------------------------------------------
-- ps2_clk - inout pin, clock line of the ps/2 interface
-- ps2_data - inout pin, data line of the ps/2 interface
-- clk - input pin, system clock signal
-- rst - input pin, system reset signal
-- tx_data - input pin, 8 bits, from client
-- - data to be sent to the device
-- write_data - input pin, from client
-- - should be active for one clock period when then
-- - client wants to send data to the device and
-- - data to be sent is valid on tx_data
-- rx_data - output pin, 8 bits, to client
-- - data received from device
-- read - output pin, to client
-- - active for one clock period when new data is
-- - available from device
-- busy - output pin, to client
-- - active while sending or receiving data.
-- err - output pin, to client
-- - active for one clock period when an error occurred
-- - during sending or receiving.
------------------------------------------------------------------------
-- Revision History:
-- 09/18/2006(UlrichZ): created
------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- simulation library
library UNISIM;
use UNISIM.VComponents.all;
-- the ps2interface entity declaration
-- read above for behavioral description and port definitions.
entity Ps2Interface is
port(
ps2_clk : inout std_logic;
ps2_data : inout std_logic;
clk : in std_logic;
rst : in std_logic;
tx_data : in std_logic_vector(7 downto 0);
write_data : in std_logic;
rx_data : out std_logic_vector(7 downto 0);
read_data : out std_logic;
busy : out std_logic;
err : out std_logic
);
-- forces the extraction of distributed ram for
-- the parity rom memory.
-- please remove if block ram is preffered.
attribute rom_extract : string;
attribute rom_extract of Ps2Interface: entity is "yes";
attribute rom_style : string;
attribute rom_style of Ps2Interface: entity is "distributed";
end Ps2Interface;
architecture Behavioral of Ps2Interface is
------------------------------------------------------------------------
-- CONSTANTS
------------------------------------------------------------------------
-- Values are valid for a 100MHz clk. Please adjust for other
-- frequencies if necessary!
-- upper limit for 100us delay counter.
-- 10000 * 10ns = 100us
constant DELAY_100US : std_logic_vector(13 downto 0):= "10011100010000";
-- 10000 clock periods
-- upper limit for 20us delay counter.
-- 2000 * 10ns = 20us
constant DELAY_20US : std_logic_vector(10 downto 0) := "11111010000";
-- 2000 clock periods
-- upper limit for 63clk delay counter.
constant DELAY_63CLK : std_logic_vector(6 downto 0) := "1111111";
-- 63 clock periods
-- delay from debouncing ps2_clk and ps2_data signals
constant DEBOUNCE_DELAY : std_logic_vector(3 downto 0) := "1111";
-- number of bits in a frame
constant NUMBITS: std_logic_vector(3 downto 0) := "1011"; -- 11
-- parity bit position in frame
constant PARITY_BIT: positive := 9;
-- (odd) parity bit ROM
-- Used instead of logic because this way speed is far greater
-- 256x1bit rom
-- If the odd parity bit for a 8 bits number, x, is needed
-- the bit at address x is the parity bit.
type ROM is array(0 to 255) of std_logic;
constant parityrom : ROM := (
'1','0','0','1','0','1','1','0',
'0','1','1','0','1','0','0','1',
'0','1','1','0','1','0','0','1',
'1','0','0','1','0','1','1','0',
'0','1','1','0','1','0','0','1',
'1','0','0','1','0','1','1','0',
'1','0','0','1','0','1','1','0',
'0','1','1','0','1','0','0','1',
'0','1','1','0','1','0','0','1',
'1','0','0','1','0','1','1','0',
'1','0','0','1','0','1','1','0',
'0','1','1','0','1','0','0','1',
'1','0','0','1','0','1','1','0',
'0','1','1','0','1','0','0','1',
'0','1','1','0','1','0','0','1',
'1','0','0','1','0','1','1','0',
'0','1','1','0','1','0','0','1',
'1','0','0','1','0','1','1','0',
'1','0','0','1','0','1','1','0',
'0','1','1','0','1','0','0','1',
'1','0','0','1','0','1','1','0',
'0','1','1','0','1','0','0','1',
'0','1','1','0','1','0','0','1',
'1','0','0','1','0','1','1','0',
'1','0','0','1','0','1','1','0',
'0','1','1','0','1','0','0','1',
'0','1','1','0','1','0','0','1',
'1','0','0','1','0','1','1','0',
'0','1','1','0','1','0','0','1',
'1','0','0','1','0','1','1','0',
'1','0','0','1','0','1','1','0',
'0','1','1','0','1','0','0','1'
);
------------------------------------------------------------------------
-- SIGNALS
------------------------------------------------------------------------
-- 14 bits counter
-- max value DELAY_100US
-- used to wait 100us
signal delay_100us_count: std_logic_vector(13 downto 0) :=
(others => '0');
-- 11 bits counter
-- max value DELAY_20US
-- used to wait 20us
signal delay_20us_count: std_logic_vector(10 downto 0) :=
(others => '0');
-- 11 bits counter
-- max value DELAY_63CLK
-- used to wait 63 clock periods
signal delay_63clk_count: std_logic_vector(6 downto 0) :=
(others => '0');
-- done signal for the couters above
-- when a counter reaches max value,the corresponding done signal is set
signal delay_100us_done, delay_20us_done, delay_63clk_done: std_logic;
-- enable signal for 100us delay counter
signal delay_100us_counter_enable: std_logic := '0';
-- enable signal for 20us delay counter
signal delay_20us_counter_enable : std_logic := '0';
-- enable signal for 63clk delay counter
signal delay_63clk_counter_enable: std_logic := '0';
-- synchronzed input for ps2_clk and ps2_data
signal ps2_clk_s,ps2_data_s: std_logic := '1';
-- control the output of ps2_clk and ps2_data
-- if 1 then corresponding signal (ps2_clk or ps2_data) is
-- put in high impedance ('Z').
signal ps2_clk_h,ps2_data_h: std_logic := '1';
-- states of the FSM for controlling the communcation with the device
-- states that begin with "rx_" are used when receiving data
-- states that begin with "tx_" are used when transmiting data
type fsm_state is
(
idle,rx_clk_h,rx_clk_l,rx_down_edge,rx_error_parity,rx_data_ready,
tx_force_clk_l,tx_bring_data_down,tx_release_clk,
tx_first_wait_down_edge,tx_clk_l,tx_wait_up_edge,tx_clk_h,
tx_wait_up_edge_before_ack,tx_wait_ack,tx_received_ack,
tx_error_no_ack
);
-- the signal that holds the current state of the FSM
-- implicitly state is idle.
signal state: fsm_state := idle;
-- register that holds the frame received or the one to be sent.
-- Its contents are shifted in from the bus one bit at a time
-- from left to right when receiving data and are shifted on the
-- bus (ps2_data) one bit at a time to the right when sending data
signal frame: std_logic_vector(10 downto 0) := (others => '0');
-- how many bits have been sent or received.
signal bit_count: std_logic_vector(3 downto 0) := (others => '0');
-- when active the bit counter is reset.
signal reset_bit_count: std_logic := '0';
-- when active the contents of the frame is shifted to the right
-- and the most significant bit of frame is loaded with ps2_data.
signal shift_frame: std_logic := '0';
-- parity of the byte that was received from the device.
-- must match the parity bit received, else error occurred.
signal rx_parity: std_logic := '0';
-- parity bit that is sent with the frame, representing the
-- odd parity of the byte currently being sent
signal tx_parity: std_logic := '0';
-- when active, frame is loaded with the start bit, data on
-- tx_data, parity bit (tx_parity) and stop bit
-- this frame will be sent to the device.
signal load_tx_data: std_logic := '0';
-- when active bits 8 downto 1 from frame are loaded into
-- rx_data register. This is the byte received from the device.
signal load_rx_data: std_logic := '0';
-- intermediary signals used to debounce the inputs ps2_clk and ps2_data
signal ps2_clk_clean,ps2_data_clean: std_logic := '1';
-- debounce counter for the ps2_clk input and the ps2_data input.
signal clk_count,data_count: std_logic_vector(3 downto 0);
-- last value on ps2_clk and ps2_data.
signal clk_inter,data_inter: std_logic := '1';
begin
---------------------------------------------------------------------
-- FLAGS and PS2 CLOCK AND DATA LINES
---------------------------------------------------------------------
-- clean ps2_clk signal (debounce)
-- note that this introduces a delay in ps2_clk of
-- DEBOUNCE_DELAY clocks
process(clk)
begin
if(rising_edge(clk)) then
-- if the current bit on ps2_clk is different
-- from the last value, then reset counter
-- and retain value
if(ps2_clk /= clk_inter) then
clk_inter <= ps2_clk;
clk_count <= (others => '0');
-- if counter reached upper limit, then
-- the signal is clean
elsif(clk_count = DEBOUNCE_DELAY) then
ps2_clk_clean <= clk_inter;
-- ps2_clk did not change, but counter did not
-- reach limit. Increment counter
else
clk_count <= clk_count + 1;
end if;
end if;
end process;
-- clean ps2_data signal (debounce)
-- note that this introduces a delay in ps2_data of
-- DEBOUNCE_DELAY clocks
process(clk)
begin
if(rising_edge(clk)) then
-- if the current bit on ps2_data is different
-- from the last value, then reset counter
-- and retain value
if(ps2_data /= data_inter) then
data_inter <= ps2_data;
data_count <= (others => '0');
-- if counter reached upper limit, then
-- the signal is clean
elsif(data_count = DEBOUNCE_DELAY) then
ps2_data_clean <= data_inter;
-- ps2_data did not change, but counter did not
-- reach limit. Increment counter
else
data_count <= data_count + 1;
end if;
end if;
end process;
-- Synchronize ps2 entries
ps2_clk_s <= ps2_clk_clean when rising_edge(clk);
ps2_data_s <= ps2_data_clean when rising_edge(clk);
-- Assign parity from frame bits 8 downto 1, this is the parity
-- that should be received inside the frame on PARITY_BIT position
rx_parity <= parityrom(conv_integer(frame(8 downto 1)))
when rising_edge(clk);
-- The parity for the data to be sent
tx_parity <= parityrom(conv_integer(tx_data)) when rising_edge(clk);
-- Force ps2_clk to '0' if ps2_clk_h = '0', else release the line
-- ('Z' = +5Vcc because of pull-ups)
ps2_clk <= 'Z' when ps2_clk_h = '1' else '0';
-- Force ps2_data to '0' if ps2_data_h = '0', else release the line
-- ('Z' = +5Vcc because of pull-ups)
ps2_data <= 'Z' when ps2_data_h = '1' else '0';
-- Control busy flag. Interface is not busy while in idle state.
busy <= '0' when state = idle else '1';
-- reset the bit counter when in idle state.
reset_bit_count <= '1' when state = idle else '0';
-- Control shifting of the frame
-- When receiving from device, data is read
-- on the falling edge of ps2_clk
-- When sending to device, data is read by device
-- on the rising edge of ps2_clk
shift_frame <= '1' when state = rx_down_edge or
state = tx_clk_l else
'0';
---------------------------------------------------------------------
-- FINITE STATE MACHINE
---------------------------------------------------------------------
-- For the current state establish next state
-- and give necessary commands
manage_fsm: process(clk,rst,state,ps2_clk_s,ps2_data_s,write_data,tx_data,
bit_count,rx_parity,frame,delay_100us_done,
delay_20us_done,delay_63clk_done)
begin
-- if reset occurs, go to idle state.
if(rst = '1') then
state <= idle;
elsif(rising_edge(clk)) then
-- default values for these signals
-- ensures signals are reset to default value
-- when coditions for their activation are no
-- longer applied (transition to other state,
-- where signal should not be active)
-- Idle value for ps2_clk and ps2_data is 'Z'
ps2_clk_h <= '1';
ps2_data_h <= '1';
load_tx_data <= '0';
load_rx_data <= '0';
read_data <= '0';
err <= '0';
case state is
-- wait for the device to begin a transmission
-- by pulling the clock line low and go to state
-- rx_down_edge or, if write is high, the
-- client of this interface wants to send a byte
-- to the device and a transition is made to state
-- tx_force_clk_l
when idle =>
if(ps2_clk_s = '0') then
state <= rx_down_edge;
elsif(write_data = '1') then
state <= tx_force_clk_l;
else
state <= idle;
end if;
-- ps2_clk is high, check if all the bits have been read
-- if, last bit read, check parity, and if parity ok
-- load received data into rx_data.
-- else if more bits left, then wait for the ps2_clk to
-- go low
when rx_clk_h =>
if(bit_count = NUMBITS) then
if(not (rx_parity = frame(PARITY_BIT))) then
state <= rx_error_parity;
else
load_rx_data <= '1';
state <= rx_data_ready;
end if;
elsif(ps2_clk_s = '0') then
state <= rx_down_edge;
else
state <= rx_clk_h;
end if;
-- data must be read into frame in this state
-- the ps2_clk just transitioned from high to low
when rx_down_edge =>
state <= rx_clk_l;
-- ps2_clk line is low, wait for it to go high
when rx_clk_l =>
if(ps2_clk_s = '1') then
state <= rx_clk_h;
else
state <= rx_clk_l;
end if;
-- parity bit received is invalid
-- signal error and go back to idle.
when rx_error_parity =>
err <= '1';
state <= idle;
-- parity bit received was good
-- set read signal for the client to know
-- a new byte was received and is available on rx_data
when rx_data_ready =>
read_data <= '1';
state <= idle;
-- the client wishes to transmit a byte to the device
-- this is done by holding ps2_clk down for at least 100us
-- bringing down ps2_data, wait 20us and then releasing
-- the ps2_clk.
-- This constitutes a request to send command.
-- In this state, the ps2_clk line is held down and
-- the counter for waiting 100us is eanbled.
-- when the counter reached upper limit, transition
-- to tx_bring_data_down
when tx_force_clk_l =>
load_tx_data <= '1';
ps2_clk_h <= '0';
if(delay_100us_done = '1') then
state <= tx_bring_data_down;
else
state <= tx_force_clk_l;
end if;
-- with the ps2_clk line low bring ps2_data low
-- wait for 20us and then go to tx_release_clk
when tx_bring_data_down =>
-- keep clock line low
ps2_clk_h <= '0';
-- set data line low
-- when clock is released in the next state
-- the device will read bit 0 on data line
-- and this bit represents the start bit.
ps2_data_h <= '0'; -- start bit = '0'
if(delay_20us_done = '1') then
state <= tx_release_clk;
else
state <= tx_bring_data_down;
end if;
-- release the ps2_clk line
-- keep holding data line low
when tx_release_clk =>
ps2_clk_h <= '1';
-- must maintain data low,
-- otherwise will be released by default value
ps2_data_h <= '0';
state <= tx_first_wait_down_edge;
-- state is necessary because the clock signal
-- is not released instantaneously and, because of debounce,
-- delay is even greater.
-- Wait 63 clock periods for the clock line to release
-- then if clock is low then go to tx_clk_l
-- else wait until ps2_clk goes low.
when tx_first_wait_down_edge =>
ps2_data_h <= '0';
if(delay_63clk_done = '1') then
if(ps2_clk_s = '0') then
state <= tx_clk_l;
else
state <= tx_first_wait_down_edge;
end if;
else
state <= tx_first_wait_down_edge;
end if;
-- place the least significant bit from frame
-- on the data line
-- During this state the frame is shifted one
-- bit to the right
when tx_clk_l =>
ps2_data_h <= frame(0);
state <= tx_wait_up_edge;
-- wait for the clock to go high
-- this is the edge on which the device reads the data
-- on ps2_data.
-- keep holding ps2_data on frame(0) because else
-- will be released by default value.
-- Check if sent the last bit and if so, release data line
-- and go to state that wait for acknowledge
when tx_wait_up_edge =>
ps2_data_h <= frame(0);
-- NUMBITS - 1 because first (start bit = 0) bit was read
-- when the clock line was released in the request to
-- send command (see tx_bring_data_down state).
if(bit_count = NUMBITS-1) then
ps2_data_h <= '1';
state <= tx_wait_up_edge_before_ack;
-- if more bits to send, wait for the up edge
-- of ps2_clk
elsif(ps2_clk_s = '1') then
state <= tx_clk_h;
else
state <= tx_wait_up_edge;
end if;
-- ps2_clk is released, wait for down edge
-- and go to tx_clk_l when arrived
when tx_clk_h =>
ps2_data_h <= frame(0);
if(ps2_clk_s = '0') then
state <= tx_clk_l;
else
state <= tx_clk_h;
end if;
-- release ps2_data and wait for rising edge of ps2_clk
-- once this occurs, transition to tx_wait_ack
when tx_wait_up_edge_before_ack =>
ps2_data_h <= '1';
if(ps2_clk_s = '1') then
state <= tx_wait_ack;
else
state <= tx_wait_up_edge_before_ack;
end if;
-- wait for the falling edge of the clock line
-- if data line is low when this occurs, the
-- ack is received
-- else if data line is high, the device did not
-- acknowledge the transimission
when tx_wait_ack =>
if(ps2_clk_s = '0') then
if(ps2_data_s = '0') then
-- acknowledge received
state <= tx_received_ack;
else
-- acknowledge not received
state <= tx_error_no_ack;
end if;
else
state <= tx_wait_ack;
end if;
-- wait for ps2_clk to be released together with ps2_data
-- (bus to be idle) and go back to idle state
when tx_received_ack =>
if(ps2_clk_s = '1' and ps2_data_s = '1') then
state <= idle;
else
state <= tx_received_ack;
end if;
-- wait for ps2_clk to be released together with ps2_data
-- (bus to be idle) and go back to idle state
-- signal error for not receiving ack
when tx_error_no_ack =>
if(ps2_clk_s = '1' and ps2_data_s = '1') then
err <= '1';
state <= idle;
else
state <= tx_error_no_ack;
end if;
-- if invalid transition occurred, signal error and
-- go back to idle state
when others =>
err <= '1';
state <= idle;
end case;
end if;
end process manage_fsm;
---------------------------------------------------------------------
-- DELAY COUNTERS
---------------------------------------------------------------------
-- Enable the 100us counter only when state is tx_force_clk_l
delay_100us_counter_enable <= '1' when state = tx_force_clk_l else '0';
-- Counter for a 100us delay
-- after done counting, done signal remains active until
-- enable counter is reset.
delay_100us_counter: process(clk)
begin
if(rising_edge(clk)) then
if(delay_100us_counter_enable = '1') then
if(delay_100us_count = (DELAY_100US)) then
delay_100us_count <= delay_100us_count;
delay_100us_done <= '1';
else
delay_100us_count <= delay_100us_count + 1;
delay_100us_done <= '0';
end if;
else
delay_100us_count <= (others => '0');
delay_100us_done <= '0';
end if;
end if;
end process delay_100us_counter;
-- Enable the 20us counter only when state is tx_bring_data_down
delay_20us_counter_enable <= '1' when state = tx_bring_data_down else '0';
-- Counter for a 20us delay
-- after done counting, done signal remains active until
-- enable counter is reset.
delay_20us_counter: process(clk)
begin
if(rising_edge(clk)) then
if(delay_20us_counter_enable = '1') then
if(delay_20us_count = (DELAY_20US)) then
delay_20us_count <= delay_20us_count;
delay_20us_done <= '1';
else
delay_20us_count <= delay_20us_count + 1;
delay_20us_done <= '0';
end if;
else
delay_20us_count <= (others => '0');
delay_20us_done <= '0';
end if;
end if;
end process delay_20us_counter;
-- Enable the 63clk counter only when state is tx_first_wait_down_edge
delay_63clk_counter_enable <= '1' when state = tx_first_wait_down_edge else '0';
-- Counter for a 63 clock periods delay
-- after done counting, done signal remains active until
-- enable counter is reset.
delay_63clk_counter: process(clk)
begin
if(rising_edge(clk)) then
if(delay_63clk_counter_enable = '1') then
if(delay_63clk_count = (DELAY_63CLK)) then
delay_63clk_count <= delay_63clk_count;
delay_63clk_done <= '1';
else
delay_63clk_count <= delay_63clk_count + 1;
delay_63clk_done <= '0';
end if;
else
delay_63clk_count <= (others => '0');
delay_63clk_done <= '0';
end if;
end if;
end process delay_63clk_counter;
---------------------------------------------------------------------
-- BIT COUNTER AND FRAME SHIFTING LOGIC
---------------------------------------------------------------------
-- counts the number of bits shifted into the frame
-- or out of the frame.
bit_counter: process(clk)
begin
if(rising_edge(clk)) then
if(reset_bit_count = '1') then
bit_count <= (others => '0');
elsif(shift_frame = '1') then
bit_count <= bit_count + 1;
end if;
end if;
end process bit_counter;
-- shifts frame with one bit to right when shift_frame is acitve
-- and loads data into frame from tx_data then load_tx_data is high
load_tx_data_into_frame: process(clk)
begin
if(rising_edge(clk)) then
if(load_tx_data = '1') then
frame(8 downto 1) <= tx_data; -- byte to send
frame(0) <= '0'; -- start bit
frame(10) <= '1'; -- stop bit
frame(9) <= tx_parity; -- parity bit
elsif(shift_frame = '1') then
-- shift right 1 bit
frame(9 downto 0) <= frame(10 downto 1);
-- shift in from the ps2_data line
frame(10) <= ps2_data_s;
end if;
end if;
end process load_tx_data_into_frame;
-- Loads data from frame into rx_data output when data is ready
do_load_rx_data: process(clk)
begin
if(rising_edge(clk)) then
if(load_rx_data = '1') then
rx_data <= frame(8 downto 1);
end if;
end if;
end process do_load_rx_data;
end Behavioral;
|
------------------------------------------------------------------------
-- ps2interface.vhd
------------------------------------------------------------------------
-- Author : Ulrich Zoltán
-- Copyright 2006 Digilent, Inc.
------------------------------------------------------------------------
-- This file contains the implementation of a generic bidirectional
-- ps/2 interface.
------------------------------------------------------------------------
-- Behavioral description
------------------------------------------------------------------------
-- Please read the following article on the web for understanding how
-- the ps/2 protocol works.
-- http://www.computer-engineering.org/ps2protocol/
-- This module implements a generic bidirectional ps/2 interface. It can
-- be used with any ps/2 compatible device. It offers its clients a
-- convenient way to exchange data with the device. The interface
-- transparently wraps the byte to be sent into a ps/2 frame, generates
-- parity for byte and sends the frame one bit at a time to the device.
-- Similarly, when receiving data from the ps2 device, the interface
-- receives the frame, checks for parity, and extract the usefull data
-- and forwards it to the client. If an error occurs during receiving
-- or sending a byte, the client is informed by settings the err output
-- line high. This way, the client can resend the data or can issue
-- a resend command to the device.
-- The physical ps/2 interface uses 4 lines
-- For the 6-pin connector pins are assigned as follows:
-- 1 - Data
-- 2 - Not Implemented
-- 3 - Ground
-- 4 - Vcc (+5V)
-- 5 - Clock
-- 6 - Not Implemented
-- The clock line carries the device generated clock which has a
-- frequency in range 10 - 16.7 kHz (30 to 50us). When line is idle
-- it is placed in high impedance. The clock is only generated when
-- device is sending or receiving data.
-- The Data and Clock lines are both open-collector with pullup
-- resistors to Vcc. An "open-collector" interface has two possible
-- states: low('0') or high impedance('Z').
-- When device wants to send a byte, it pulls the clock line low and the
-- host(i.e. this interfaces) recognizes that the device is sending data
-- When the host wants to send data, it maeks a request to send. This
-- is done by holding the clock line low for at least 100us, then with
-- the clock line low, the data line is brought low. Next the clock line
-- is released (placed in high impedance). The devices begins generating
-- clock signal on clock line.
-- When receiving data, bits are read from the data line (ps2_data) on
-- the falling edge of the clock (ps2_clk). When sending data, the
-- device reads the bits from the data line on the rising edge of the
-- clock.
-- A frame for sending a byte is comprised of 11 bits as shown bellow:
-- bits 10 9 8 7 6 5 4 3 2 1 0
-- -------------------------------------------------------------
-- | STOP| PAR | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 | START |
-- -------------------------------------------------------------
-- STOP - stop bit, always '1'
-- PAR - parity bit, odd parity for the 8 data bits.
-- - select in such way that the number of bits of '1' in the data
-- - bits together with parity bit is odd.
-- D0-7 - data bits.
-- START - start bit, always '0'
--
-- Frame is sent bit by bit starting with the least significant bit
-- (starting bit) and is received the same way. This is done, when
-- receiving, by shifting the frame register to the left when a bit
-- is available and placing the bit on data line on the most significant
-- bit. This way the first bit sent will reach the least significant bit
-- of the frame when all the bits have been received. When sending data
-- the least significant bit of the frame is placed on the data line
-- and the frame is shifted to the right when another bit needs to be
-- sent. During the request to send, when releasing the clock line,
-- the device reads the data line and interprets the data on it as the
-- first bit of the frame. Data line is low at that time, at this is the
-- way the start bit('0') is sent. Because of this, when sending, only
-- 10 shifts of the frame will be made.
-- While the interface is sending or receiving data, the busy output
-- signal goes high. When interface is idle, busy is low.
-- After sending all the bits in the frame, the device must acknowledge
-- the data sent. This is done by the host releasing and data line
-- (clock line is already released) after the last bit is sent. The
-- devices brings the data line and the clock line low, in this order,
-- to acknowledge the data. If data line is high when clock line goes
-- low after last bit, the device did not acknowledge the data and
-- err output is set.
-- A FSM is used to manage the transitions the set all the command
-- signals. States that begin with "rx_" are used to receive data
-- from device and states begining with "tx_" are used to send data
-- to the device.
-- For the parity bit, a ROM holds the parity bit for all possible
-- data (256 possible values, since 8 bits of data). The ROM has
-- dimensions 256x1bit. For obtaining the parity bit of a value,
-- the bit at the data value address is read. Ex: to find the parity
-- bit of 174, the bit at address 174 is read.
-- For generating the necessary delay, counters are used. For example,
-- to generate the 100us delay a 14 bit counter is used that has the
-- upper limit for counting 10000. The interface is designed to run
-- at 100MHz. Thus, 10000x10ns = 100us.
-----------------------------------------------------------------------
-- If using the interface at different frequency than 100MHz, adjusting
-- the delay counters is necessary!!!
-----------------------------------------------------------------------
-- Clock line(ps2_clk) and data line(ps2_data) are passed through a
-- debouncer for the transitions of the clock and data to be clean.
-- Also, ps2_clk_s and ps2_data_s hold the debounced and synchronized
-- value of the clock and data line to the system clock(clk).
------------------------------------------------------------------------
-- Port definitions
------------------------------------------------------------------------
-- ps2_clk - inout pin, clock line of the ps/2 interface
-- ps2_data - inout pin, data line of the ps/2 interface
-- clk - input pin, system clock signal
-- rst - input pin, system reset signal
-- tx_data - input pin, 8 bits, from client
-- - data to be sent to the device
-- write_data - input pin, from client
-- - should be active for one clock period when then
-- - client wants to send data to the device and
-- - data to be sent is valid on tx_data
-- rx_data - output pin, 8 bits, to client
-- - data received from device
-- read - output pin, to client
-- - active for one clock period when new data is
-- - available from device
-- busy - output pin, to client
-- - active while sending or receiving data.
-- err - output pin, to client
-- - active for one clock period when an error occurred
-- - during sending or receiving.
------------------------------------------------------------------------
-- Revision History:
-- 09/18/2006(UlrichZ): created
------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- simulation library
library UNISIM;
use UNISIM.VComponents.all;
-- the ps2interface entity declaration
-- read above for behavioral description and port definitions.
entity Ps2Interface is
port(
ps2_clk : inout std_logic;
ps2_data : inout std_logic;
clk : in std_logic;
rst : in std_logic;
tx_data : in std_logic_vector(7 downto 0);
write_data : in std_logic;
rx_data : out std_logic_vector(7 downto 0);
read_data : out std_logic;
busy : out std_logic;
err : out std_logic
);
-- forces the extraction of distributed ram for
-- the parity rom memory.
-- please remove if block ram is preffered.
attribute rom_extract : string;
attribute rom_extract of Ps2Interface: entity is "yes";
attribute rom_style : string;
attribute rom_style of Ps2Interface: entity is "distributed";
end Ps2Interface;
architecture Behavioral of Ps2Interface is
------------------------------------------------------------------------
-- CONSTANTS
------------------------------------------------------------------------
-- Values are valid for a 100MHz clk. Please adjust for other
-- frequencies if necessary!
-- upper limit for 100us delay counter.
-- 10000 * 10ns = 100us
constant DELAY_100US : std_logic_vector(13 downto 0):= "10011100010000";
-- 10000 clock periods
-- upper limit for 20us delay counter.
-- 2000 * 10ns = 20us
constant DELAY_20US : std_logic_vector(10 downto 0) := "11111010000";
-- 2000 clock periods
-- upper limit for 63clk delay counter.
constant DELAY_63CLK : std_logic_vector(6 downto 0) := "1111111";
-- 63 clock periods
-- delay from debouncing ps2_clk and ps2_data signals
constant DEBOUNCE_DELAY : std_logic_vector(3 downto 0) := "1111";
-- number of bits in a frame
constant NUMBITS: std_logic_vector(3 downto 0) := "1011"; -- 11
-- parity bit position in frame
constant PARITY_BIT: positive := 9;
-- (odd) parity bit ROM
-- Used instead of logic because this way speed is far greater
-- 256x1bit rom
-- If the odd parity bit for a 8 bits number, x, is needed
-- the bit at address x is the parity bit.
type ROM is array(0 to 255) of std_logic;
constant parityrom : ROM := (
'1','0','0','1','0','1','1','0',
'0','1','1','0','1','0','0','1',
'0','1','1','0','1','0','0','1',
'1','0','0','1','0','1','1','0',
'0','1','1','0','1','0','0','1',
'1','0','0','1','0','1','1','0',
'1','0','0','1','0','1','1','0',
'0','1','1','0','1','0','0','1',
'0','1','1','0','1','0','0','1',
'1','0','0','1','0','1','1','0',
'1','0','0','1','0','1','1','0',
'0','1','1','0','1','0','0','1',
'1','0','0','1','0','1','1','0',
'0','1','1','0','1','0','0','1',
'0','1','1','0','1','0','0','1',
'1','0','0','1','0','1','1','0',
'0','1','1','0','1','0','0','1',
'1','0','0','1','0','1','1','0',
'1','0','0','1','0','1','1','0',
'0','1','1','0','1','0','0','1',
'1','0','0','1','0','1','1','0',
'0','1','1','0','1','0','0','1',
'0','1','1','0','1','0','0','1',
'1','0','0','1','0','1','1','0',
'1','0','0','1','0','1','1','0',
'0','1','1','0','1','0','0','1',
'0','1','1','0','1','0','0','1',
'1','0','0','1','0','1','1','0',
'0','1','1','0','1','0','0','1',
'1','0','0','1','0','1','1','0',
'1','0','0','1','0','1','1','0',
'0','1','1','0','1','0','0','1'
);
------------------------------------------------------------------------
-- SIGNALS
------------------------------------------------------------------------
-- 14 bits counter
-- max value DELAY_100US
-- used to wait 100us
signal delay_100us_count: std_logic_vector(13 downto 0) :=
(others => '0');
-- 11 bits counter
-- max value DELAY_20US
-- used to wait 20us
signal delay_20us_count: std_logic_vector(10 downto 0) :=
(others => '0');
-- 11 bits counter
-- max value DELAY_63CLK
-- used to wait 63 clock periods
signal delay_63clk_count: std_logic_vector(6 downto 0) :=
(others => '0');
-- done signal for the couters above
-- when a counter reaches max value,the corresponding done signal is set
signal delay_100us_done, delay_20us_done, delay_63clk_done: std_logic;
-- enable signal for 100us delay counter
signal delay_100us_counter_enable: std_logic := '0';
-- enable signal for 20us delay counter
signal delay_20us_counter_enable : std_logic := '0';
-- enable signal for 63clk delay counter
signal delay_63clk_counter_enable: std_logic := '0';
-- synchronzed input for ps2_clk and ps2_data
signal ps2_clk_s,ps2_data_s: std_logic := '1';
-- control the output of ps2_clk and ps2_data
-- if 1 then corresponding signal (ps2_clk or ps2_data) is
-- put in high impedance ('Z').
signal ps2_clk_h,ps2_data_h: std_logic := '1';
-- states of the FSM for controlling the communcation with the device
-- states that begin with "rx_" are used when receiving data
-- states that begin with "tx_" are used when transmiting data
type fsm_state is
(
idle,rx_clk_h,rx_clk_l,rx_down_edge,rx_error_parity,rx_data_ready,
tx_force_clk_l,tx_bring_data_down,tx_release_clk,
tx_first_wait_down_edge,tx_clk_l,tx_wait_up_edge,tx_clk_h,
tx_wait_up_edge_before_ack,tx_wait_ack,tx_received_ack,
tx_error_no_ack
);
-- the signal that holds the current state of the FSM
-- implicitly state is idle.
signal state: fsm_state := idle;
-- register that holds the frame received or the one to be sent.
-- Its contents are shifted in from the bus one bit at a time
-- from left to right when receiving data and are shifted on the
-- bus (ps2_data) one bit at a time to the right when sending data
signal frame: std_logic_vector(10 downto 0) := (others => '0');
-- how many bits have been sent or received.
signal bit_count: std_logic_vector(3 downto 0) := (others => '0');
-- when active the bit counter is reset.
signal reset_bit_count: std_logic := '0';
-- when active the contents of the frame is shifted to the right
-- and the most significant bit of frame is loaded with ps2_data.
signal shift_frame: std_logic := '0';
-- parity of the byte that was received from the device.
-- must match the parity bit received, else error occurred.
signal rx_parity: std_logic := '0';
-- parity bit that is sent with the frame, representing the
-- odd parity of the byte currently being sent
signal tx_parity: std_logic := '0';
-- when active, frame is loaded with the start bit, data on
-- tx_data, parity bit (tx_parity) and stop bit
-- this frame will be sent to the device.
signal load_tx_data: std_logic := '0';
-- when active bits 8 downto 1 from frame are loaded into
-- rx_data register. This is the byte received from the device.
signal load_rx_data: std_logic := '0';
-- intermediary signals used to debounce the inputs ps2_clk and ps2_data
signal ps2_clk_clean,ps2_data_clean: std_logic := '1';
-- debounce counter for the ps2_clk input and the ps2_data input.
signal clk_count,data_count: std_logic_vector(3 downto 0);
-- last value on ps2_clk and ps2_data.
signal clk_inter,data_inter: std_logic := '1';
begin
---------------------------------------------------------------------
-- FLAGS and PS2 CLOCK AND DATA LINES
---------------------------------------------------------------------
-- clean ps2_clk signal (debounce)
-- note that this introduces a delay in ps2_clk of
-- DEBOUNCE_DELAY clocks
process(clk)
begin
if(rising_edge(clk)) then
-- if the current bit on ps2_clk is different
-- from the last value, then reset counter
-- and retain value
if(ps2_clk /= clk_inter) then
clk_inter <= ps2_clk;
clk_count <= (others => '0');
-- if counter reached upper limit, then
-- the signal is clean
elsif(clk_count = DEBOUNCE_DELAY) then
ps2_clk_clean <= clk_inter;
-- ps2_clk did not change, but counter did not
-- reach limit. Increment counter
else
clk_count <= clk_count + 1;
end if;
end if;
end process;
-- clean ps2_data signal (debounce)
-- note that this introduces a delay in ps2_data of
-- DEBOUNCE_DELAY clocks
process(clk)
begin
if(rising_edge(clk)) then
-- if the current bit on ps2_data is different
-- from the last value, then reset counter
-- and retain value
if(ps2_data /= data_inter) then
data_inter <= ps2_data;
data_count <= (others => '0');
-- if counter reached upper limit, then
-- the signal is clean
elsif(data_count = DEBOUNCE_DELAY) then
ps2_data_clean <= data_inter;
-- ps2_data did not change, but counter did not
-- reach limit. Increment counter
else
data_count <= data_count + 1;
end if;
end if;
end process;
-- Synchronize ps2 entries
ps2_clk_s <= ps2_clk_clean when rising_edge(clk);
ps2_data_s <= ps2_data_clean when rising_edge(clk);
-- Assign parity from frame bits 8 downto 1, this is the parity
-- that should be received inside the frame on PARITY_BIT position
rx_parity <= parityrom(conv_integer(frame(8 downto 1)))
when rising_edge(clk);
-- The parity for the data to be sent
tx_parity <= parityrom(conv_integer(tx_data)) when rising_edge(clk);
-- Force ps2_clk to '0' if ps2_clk_h = '0', else release the line
-- ('Z' = +5Vcc because of pull-ups)
ps2_clk <= 'Z' when ps2_clk_h = '1' else '0';
-- Force ps2_data to '0' if ps2_data_h = '0', else release the line
-- ('Z' = +5Vcc because of pull-ups)
ps2_data <= 'Z' when ps2_data_h = '1' else '0';
-- Control busy flag. Interface is not busy while in idle state.
busy <= '0' when state = idle else '1';
-- reset the bit counter when in idle state.
reset_bit_count <= '1' when state = idle else '0';
-- Control shifting of the frame
-- When receiving from device, data is read
-- on the falling edge of ps2_clk
-- When sending to device, data is read by device
-- on the rising edge of ps2_clk
shift_frame <= '1' when state = rx_down_edge or
state = tx_clk_l else
'0';
---------------------------------------------------------------------
-- FINITE STATE MACHINE
---------------------------------------------------------------------
-- For the current state establish next state
-- and give necessary commands
manage_fsm: process(clk,rst,state,ps2_clk_s,ps2_data_s,write_data,tx_data,
bit_count,rx_parity,frame,delay_100us_done,
delay_20us_done,delay_63clk_done)
begin
-- if reset occurs, go to idle state.
if(rst = '1') then
state <= idle;
elsif(rising_edge(clk)) then
-- default values for these signals
-- ensures signals are reset to default value
-- when coditions for their activation are no
-- longer applied (transition to other state,
-- where signal should not be active)
-- Idle value for ps2_clk and ps2_data is 'Z'
ps2_clk_h <= '1';
ps2_data_h <= '1';
load_tx_data <= '0';
load_rx_data <= '0';
read_data <= '0';
err <= '0';
case state is
-- wait for the device to begin a transmission
-- by pulling the clock line low and go to state
-- rx_down_edge or, if write is high, the
-- client of this interface wants to send a byte
-- to the device and a transition is made to state
-- tx_force_clk_l
when idle =>
if(ps2_clk_s = '0') then
state <= rx_down_edge;
elsif(write_data = '1') then
state <= tx_force_clk_l;
else
state <= idle;
end if;
-- ps2_clk is high, check if all the bits have been read
-- if, last bit read, check parity, and if parity ok
-- load received data into rx_data.
-- else if more bits left, then wait for the ps2_clk to
-- go low
when rx_clk_h =>
if(bit_count = NUMBITS) then
if(not (rx_parity = frame(PARITY_BIT))) then
state <= rx_error_parity;
else
load_rx_data <= '1';
state <= rx_data_ready;
end if;
elsif(ps2_clk_s = '0') then
state <= rx_down_edge;
else
state <= rx_clk_h;
end if;
-- data must be read into frame in this state
-- the ps2_clk just transitioned from high to low
when rx_down_edge =>
state <= rx_clk_l;
-- ps2_clk line is low, wait for it to go high
when rx_clk_l =>
if(ps2_clk_s = '1') then
state <= rx_clk_h;
else
state <= rx_clk_l;
end if;
-- parity bit received is invalid
-- signal error and go back to idle.
when rx_error_parity =>
err <= '1';
state <= idle;
-- parity bit received was good
-- set read signal for the client to know
-- a new byte was received and is available on rx_data
when rx_data_ready =>
read_data <= '1';
state <= idle;
-- the client wishes to transmit a byte to the device
-- this is done by holding ps2_clk down for at least 100us
-- bringing down ps2_data, wait 20us and then releasing
-- the ps2_clk.
-- This constitutes a request to send command.
-- In this state, the ps2_clk line is held down and
-- the counter for waiting 100us is eanbled.
-- when the counter reached upper limit, transition
-- to tx_bring_data_down
when tx_force_clk_l =>
load_tx_data <= '1';
ps2_clk_h <= '0';
if(delay_100us_done = '1') then
state <= tx_bring_data_down;
else
state <= tx_force_clk_l;
end if;
-- with the ps2_clk line low bring ps2_data low
-- wait for 20us and then go to tx_release_clk
when tx_bring_data_down =>
-- keep clock line low
ps2_clk_h <= '0';
-- set data line low
-- when clock is released in the next state
-- the device will read bit 0 on data line
-- and this bit represents the start bit.
ps2_data_h <= '0'; -- start bit = '0'
if(delay_20us_done = '1') then
state <= tx_release_clk;
else
state <= tx_bring_data_down;
end if;
-- release the ps2_clk line
-- keep holding data line low
when tx_release_clk =>
ps2_clk_h <= '1';
-- must maintain data low,
-- otherwise will be released by default value
ps2_data_h <= '0';
state <= tx_first_wait_down_edge;
-- state is necessary because the clock signal
-- is not released instantaneously and, because of debounce,
-- delay is even greater.
-- Wait 63 clock periods for the clock line to release
-- then if clock is low then go to tx_clk_l
-- else wait until ps2_clk goes low.
when tx_first_wait_down_edge =>
ps2_data_h <= '0';
if(delay_63clk_done = '1') then
if(ps2_clk_s = '0') then
state <= tx_clk_l;
else
state <= tx_first_wait_down_edge;
end if;
else
state <= tx_first_wait_down_edge;
end if;
-- place the least significant bit from frame
-- on the data line
-- During this state the frame is shifted one
-- bit to the right
when tx_clk_l =>
ps2_data_h <= frame(0);
state <= tx_wait_up_edge;
-- wait for the clock to go high
-- this is the edge on which the device reads the data
-- on ps2_data.
-- keep holding ps2_data on frame(0) because else
-- will be released by default value.
-- Check if sent the last bit and if so, release data line
-- and go to state that wait for acknowledge
when tx_wait_up_edge =>
ps2_data_h <= frame(0);
-- NUMBITS - 1 because first (start bit = 0) bit was read
-- when the clock line was released in the request to
-- send command (see tx_bring_data_down state).
if(bit_count = NUMBITS-1) then
ps2_data_h <= '1';
state <= tx_wait_up_edge_before_ack;
-- if more bits to send, wait for the up edge
-- of ps2_clk
elsif(ps2_clk_s = '1') then
state <= tx_clk_h;
else
state <= tx_wait_up_edge;
end if;
-- ps2_clk is released, wait for down edge
-- and go to tx_clk_l when arrived
when tx_clk_h =>
ps2_data_h <= frame(0);
if(ps2_clk_s = '0') then
state <= tx_clk_l;
else
state <= tx_clk_h;
end if;
-- release ps2_data and wait for rising edge of ps2_clk
-- once this occurs, transition to tx_wait_ack
when tx_wait_up_edge_before_ack =>
ps2_data_h <= '1';
if(ps2_clk_s = '1') then
state <= tx_wait_ack;
else
state <= tx_wait_up_edge_before_ack;
end if;
-- wait for the falling edge of the clock line
-- if data line is low when this occurs, the
-- ack is received
-- else if data line is high, the device did not
-- acknowledge the transimission
when tx_wait_ack =>
if(ps2_clk_s = '0') then
if(ps2_data_s = '0') then
-- acknowledge received
state <= tx_received_ack;
else
-- acknowledge not received
state <= tx_error_no_ack;
end if;
else
state <= tx_wait_ack;
end if;
-- wait for ps2_clk to be released together with ps2_data
-- (bus to be idle) and go back to idle state
when tx_received_ack =>
if(ps2_clk_s = '1' and ps2_data_s = '1') then
state <= idle;
else
state <= tx_received_ack;
end if;
-- wait for ps2_clk to be released together with ps2_data
-- (bus to be idle) and go back to idle state
-- signal error for not receiving ack
when tx_error_no_ack =>
if(ps2_clk_s = '1' and ps2_data_s = '1') then
err <= '1';
state <= idle;
else
state <= tx_error_no_ack;
end if;
-- if invalid transition occurred, signal error and
-- go back to idle state
when others =>
err <= '1';
state <= idle;
end case;
end if;
end process manage_fsm;
---------------------------------------------------------------------
-- DELAY COUNTERS
---------------------------------------------------------------------
-- Enable the 100us counter only when state is tx_force_clk_l
delay_100us_counter_enable <= '1' when state = tx_force_clk_l else '0';
-- Counter for a 100us delay
-- after done counting, done signal remains active until
-- enable counter is reset.
delay_100us_counter: process(clk)
begin
if(rising_edge(clk)) then
if(delay_100us_counter_enable = '1') then
if(delay_100us_count = (DELAY_100US)) then
delay_100us_count <= delay_100us_count;
delay_100us_done <= '1';
else
delay_100us_count <= delay_100us_count + 1;
delay_100us_done <= '0';
end if;
else
delay_100us_count <= (others => '0');
delay_100us_done <= '0';
end if;
end if;
end process delay_100us_counter;
-- Enable the 20us counter only when state is tx_bring_data_down
delay_20us_counter_enable <= '1' when state = tx_bring_data_down else '0';
-- Counter for a 20us delay
-- after done counting, done signal remains active until
-- enable counter is reset.
delay_20us_counter: process(clk)
begin
if(rising_edge(clk)) then
if(delay_20us_counter_enable = '1') then
if(delay_20us_count = (DELAY_20US)) then
delay_20us_count <= delay_20us_count;
delay_20us_done <= '1';
else
delay_20us_count <= delay_20us_count + 1;
delay_20us_done <= '0';
end if;
else
delay_20us_count <= (others => '0');
delay_20us_done <= '0';
end if;
end if;
end process delay_20us_counter;
-- Enable the 63clk counter only when state is tx_first_wait_down_edge
delay_63clk_counter_enable <= '1' when state = tx_first_wait_down_edge else '0';
-- Counter for a 63 clock periods delay
-- after done counting, done signal remains active until
-- enable counter is reset.
delay_63clk_counter: process(clk)
begin
if(rising_edge(clk)) then
if(delay_63clk_counter_enable = '1') then
if(delay_63clk_count = (DELAY_63CLK)) then
delay_63clk_count <= delay_63clk_count;
delay_63clk_done <= '1';
else
delay_63clk_count <= delay_63clk_count + 1;
delay_63clk_done <= '0';
end if;
else
delay_63clk_count <= (others => '0');
delay_63clk_done <= '0';
end if;
end if;
end process delay_63clk_counter;
---------------------------------------------------------------------
-- BIT COUNTER AND FRAME SHIFTING LOGIC
---------------------------------------------------------------------
-- counts the number of bits shifted into the frame
-- or out of the frame.
bit_counter: process(clk)
begin
if(rising_edge(clk)) then
if(reset_bit_count = '1') then
bit_count <= (others => '0');
elsif(shift_frame = '1') then
bit_count <= bit_count + 1;
end if;
end if;
end process bit_counter;
-- shifts frame with one bit to right when shift_frame is acitve
-- and loads data into frame from tx_data then load_tx_data is high
load_tx_data_into_frame: process(clk)
begin
if(rising_edge(clk)) then
if(load_tx_data = '1') then
frame(8 downto 1) <= tx_data; -- byte to send
frame(0) <= '0'; -- start bit
frame(10) <= '1'; -- stop bit
frame(9) <= tx_parity; -- parity bit
elsif(shift_frame = '1') then
-- shift right 1 bit
frame(9 downto 0) <= frame(10 downto 1);
-- shift in from the ps2_data line
frame(10) <= ps2_data_s;
end if;
end if;
end process load_tx_data_into_frame;
-- Loads data from frame into rx_data output when data is ready
do_load_rx_data: process(clk)
begin
if(rising_edge(clk)) then
if(load_rx_data = '1') then
rx_data <= frame(8 downto 1);
end if;
end if;
end process do_load_rx_data;
end Behavioral;
|
------------------------------------------------------------------------
-- ps2interface.vhd
------------------------------------------------------------------------
-- Author : Ulrich Zoltán
-- Copyright 2006 Digilent, Inc.
------------------------------------------------------------------------
-- This file contains the implementation of a generic bidirectional
-- ps/2 interface.
------------------------------------------------------------------------
-- Behavioral description
------------------------------------------------------------------------
-- Please read the following article on the web for understanding how
-- the ps/2 protocol works.
-- http://www.computer-engineering.org/ps2protocol/
-- This module implements a generic bidirectional ps/2 interface. It can
-- be used with any ps/2 compatible device. It offers its clients a
-- convenient way to exchange data with the device. The interface
-- transparently wraps the byte to be sent into a ps/2 frame, generates
-- parity for byte and sends the frame one bit at a time to the device.
-- Similarly, when receiving data from the ps2 device, the interface
-- receives the frame, checks for parity, and extract the usefull data
-- and forwards it to the client. If an error occurs during receiving
-- or sending a byte, the client is informed by settings the err output
-- line high. This way, the client can resend the data or can issue
-- a resend command to the device.
-- The physical ps/2 interface uses 4 lines
-- For the 6-pin connector pins are assigned as follows:
-- 1 - Data
-- 2 - Not Implemented
-- 3 - Ground
-- 4 - Vcc (+5V)
-- 5 - Clock
-- 6 - Not Implemented
-- The clock line carries the device generated clock which has a
-- frequency in range 10 - 16.7 kHz (30 to 50us). When line is idle
-- it is placed in high impedance. The clock is only generated when
-- device is sending or receiving data.
-- The Data and Clock lines are both open-collector with pullup
-- resistors to Vcc. An "open-collector" interface has two possible
-- states: low('0') or high impedance('Z').
-- When device wants to send a byte, it pulls the clock line low and the
-- host(i.e. this interfaces) recognizes that the device is sending data
-- When the host wants to send data, it maeks a request to send. This
-- is done by holding the clock line low for at least 100us, then with
-- the clock line low, the data line is brought low. Next the clock line
-- is released (placed in high impedance). The devices begins generating
-- clock signal on clock line.
-- When receiving data, bits are read from the data line (ps2_data) on
-- the falling edge of the clock (ps2_clk). When sending data, the
-- device reads the bits from the data line on the rising edge of the
-- clock.
-- A frame for sending a byte is comprised of 11 bits as shown bellow:
-- bits 10 9 8 7 6 5 4 3 2 1 0
-- -------------------------------------------------------------
-- | STOP| PAR | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 | START |
-- -------------------------------------------------------------
-- STOP - stop bit, always '1'
-- PAR - parity bit, odd parity for the 8 data bits.
-- - select in such way that the number of bits of '1' in the data
-- - bits together with parity bit is odd.
-- D0-7 - data bits.
-- START - start bit, always '0'
--
-- Frame is sent bit by bit starting with the least significant bit
-- (starting bit) and is received the same way. This is done, when
-- receiving, by shifting the frame register to the left when a bit
-- is available and placing the bit on data line on the most significant
-- bit. This way the first bit sent will reach the least significant bit
-- of the frame when all the bits have been received. When sending data
-- the least significant bit of the frame is placed on the data line
-- and the frame is shifted to the right when another bit needs to be
-- sent. During the request to send, when releasing the clock line,
-- the device reads the data line and interprets the data on it as the
-- first bit of the frame. Data line is low at that time, at this is the
-- way the start bit('0') is sent. Because of this, when sending, only
-- 10 shifts of the frame will be made.
-- While the interface is sending or receiving data, the busy output
-- signal goes high. When interface is idle, busy is low.
-- After sending all the bits in the frame, the device must acknowledge
-- the data sent. This is done by the host releasing and data line
-- (clock line is already released) after the last bit is sent. The
-- devices brings the data line and the clock line low, in this order,
-- to acknowledge the data. If data line is high when clock line goes
-- low after last bit, the device did not acknowledge the data and
-- err output is set.
-- A FSM is used to manage the transitions the set all the command
-- signals. States that begin with "rx_" are used to receive data
-- from device and states begining with "tx_" are used to send data
-- to the device.
-- For the parity bit, a ROM holds the parity bit for all possible
-- data (256 possible values, since 8 bits of data). The ROM has
-- dimensions 256x1bit. For obtaining the parity bit of a value,
-- the bit at the data value address is read. Ex: to find the parity
-- bit of 174, the bit at address 174 is read.
-- For generating the necessary delay, counters are used. For example,
-- to generate the 100us delay a 14 bit counter is used that has the
-- upper limit for counting 10000. The interface is designed to run
-- at 100MHz. Thus, 10000x10ns = 100us.
-----------------------------------------------------------------------
-- If using the interface at different frequency than 100MHz, adjusting
-- the delay counters is necessary!!!
-----------------------------------------------------------------------
-- Clock line(ps2_clk) and data line(ps2_data) are passed through a
-- debouncer for the transitions of the clock and data to be clean.
-- Also, ps2_clk_s and ps2_data_s hold the debounced and synchronized
-- value of the clock and data line to the system clock(clk).
------------------------------------------------------------------------
-- Port definitions
------------------------------------------------------------------------
-- ps2_clk - inout pin, clock line of the ps/2 interface
-- ps2_data - inout pin, data line of the ps/2 interface
-- clk - input pin, system clock signal
-- rst - input pin, system reset signal
-- tx_data - input pin, 8 bits, from client
-- - data to be sent to the device
-- write_data - input pin, from client
-- - should be active for one clock period when then
-- - client wants to send data to the device and
-- - data to be sent is valid on tx_data
-- rx_data - output pin, 8 bits, to client
-- - data received from device
-- read - output pin, to client
-- - active for one clock period when new data is
-- - available from device
-- busy - output pin, to client
-- - active while sending or receiving data.
-- err - output pin, to client
-- - active for one clock period when an error occurred
-- - during sending or receiving.
------------------------------------------------------------------------
-- Revision History:
-- 09/18/2006(UlrichZ): created
------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- simulation library
library UNISIM;
use UNISIM.VComponents.all;
-- the ps2interface entity declaration
-- read above for behavioral description and port definitions.
entity Ps2Interface is
port(
ps2_clk : inout std_logic;
ps2_data : inout std_logic;
clk : in std_logic;
rst : in std_logic;
tx_data : in std_logic_vector(7 downto 0);
write_data : in std_logic;
rx_data : out std_logic_vector(7 downto 0);
read_data : out std_logic;
busy : out std_logic;
err : out std_logic
);
-- forces the extraction of distributed ram for
-- the parity rom memory.
-- please remove if block ram is preffered.
attribute rom_extract : string;
attribute rom_extract of Ps2Interface: entity is "yes";
attribute rom_style : string;
attribute rom_style of Ps2Interface: entity is "distributed";
end Ps2Interface;
architecture Behavioral of Ps2Interface is
------------------------------------------------------------------------
-- CONSTANTS
------------------------------------------------------------------------
-- Values are valid for a 100MHz clk. Please adjust for other
-- frequencies if necessary!
-- upper limit for 100us delay counter.
-- 10000 * 10ns = 100us
constant DELAY_100US : std_logic_vector(13 downto 0):= "10011100010000";
-- 10000 clock periods
-- upper limit for 20us delay counter.
-- 2000 * 10ns = 20us
constant DELAY_20US : std_logic_vector(10 downto 0) := "11111010000";
-- 2000 clock periods
-- upper limit for 63clk delay counter.
constant DELAY_63CLK : std_logic_vector(6 downto 0) := "1111111";
-- 63 clock periods
-- delay from debouncing ps2_clk and ps2_data signals
constant DEBOUNCE_DELAY : std_logic_vector(3 downto 0) := "1111";
-- number of bits in a frame
constant NUMBITS: std_logic_vector(3 downto 0) := "1011"; -- 11
-- parity bit position in frame
constant PARITY_BIT: positive := 9;
-- (odd) parity bit ROM
-- Used instead of logic because this way speed is far greater
-- 256x1bit rom
-- If the odd parity bit for a 8 bits number, x, is needed
-- the bit at address x is the parity bit.
type ROM is array(0 to 255) of std_logic;
constant parityrom : ROM := (
'1','0','0','1','0','1','1','0',
'0','1','1','0','1','0','0','1',
'0','1','1','0','1','0','0','1',
'1','0','0','1','0','1','1','0',
'0','1','1','0','1','0','0','1',
'1','0','0','1','0','1','1','0',
'1','0','0','1','0','1','1','0',
'0','1','1','0','1','0','0','1',
'0','1','1','0','1','0','0','1',
'1','0','0','1','0','1','1','0',
'1','0','0','1','0','1','1','0',
'0','1','1','0','1','0','0','1',
'1','0','0','1','0','1','1','0',
'0','1','1','0','1','0','0','1',
'0','1','1','0','1','0','0','1',
'1','0','0','1','0','1','1','0',
'0','1','1','0','1','0','0','1',
'1','0','0','1','0','1','1','0',
'1','0','0','1','0','1','1','0',
'0','1','1','0','1','0','0','1',
'1','0','0','1','0','1','1','0',
'0','1','1','0','1','0','0','1',
'0','1','1','0','1','0','0','1',
'1','0','0','1','0','1','1','0',
'1','0','0','1','0','1','1','0',
'0','1','1','0','1','0','0','1',
'0','1','1','0','1','0','0','1',
'1','0','0','1','0','1','1','0',
'0','1','1','0','1','0','0','1',
'1','0','0','1','0','1','1','0',
'1','0','0','1','0','1','1','0',
'0','1','1','0','1','0','0','1'
);
------------------------------------------------------------------------
-- SIGNALS
------------------------------------------------------------------------
-- 14 bits counter
-- max value DELAY_100US
-- used to wait 100us
signal delay_100us_count: std_logic_vector(13 downto 0) :=
(others => '0');
-- 11 bits counter
-- max value DELAY_20US
-- used to wait 20us
signal delay_20us_count: std_logic_vector(10 downto 0) :=
(others => '0');
-- 11 bits counter
-- max value DELAY_63CLK
-- used to wait 63 clock periods
signal delay_63clk_count: std_logic_vector(6 downto 0) :=
(others => '0');
-- done signal for the couters above
-- when a counter reaches max value,the corresponding done signal is set
signal delay_100us_done, delay_20us_done, delay_63clk_done: std_logic;
-- enable signal for 100us delay counter
signal delay_100us_counter_enable: std_logic := '0';
-- enable signal for 20us delay counter
signal delay_20us_counter_enable : std_logic := '0';
-- enable signal for 63clk delay counter
signal delay_63clk_counter_enable: std_logic := '0';
-- synchronzed input for ps2_clk and ps2_data
signal ps2_clk_s,ps2_data_s: std_logic := '1';
-- control the output of ps2_clk and ps2_data
-- if 1 then corresponding signal (ps2_clk or ps2_data) is
-- put in high impedance ('Z').
signal ps2_clk_h,ps2_data_h: std_logic := '1';
-- states of the FSM for controlling the communcation with the device
-- states that begin with "rx_" are used when receiving data
-- states that begin with "tx_" are used when transmiting data
type fsm_state is
(
idle,rx_clk_h,rx_clk_l,rx_down_edge,rx_error_parity,rx_data_ready,
tx_force_clk_l,tx_bring_data_down,tx_release_clk,
tx_first_wait_down_edge,tx_clk_l,tx_wait_up_edge,tx_clk_h,
tx_wait_up_edge_before_ack,tx_wait_ack,tx_received_ack,
tx_error_no_ack
);
-- the signal that holds the current state of the FSM
-- implicitly state is idle.
signal state: fsm_state := idle;
-- register that holds the frame received or the one to be sent.
-- Its contents are shifted in from the bus one bit at a time
-- from left to right when receiving data and are shifted on the
-- bus (ps2_data) one bit at a time to the right when sending data
signal frame: std_logic_vector(10 downto 0) := (others => '0');
-- how many bits have been sent or received.
signal bit_count: std_logic_vector(3 downto 0) := (others => '0');
-- when active the bit counter is reset.
signal reset_bit_count: std_logic := '0';
-- when active the contents of the frame is shifted to the right
-- and the most significant bit of frame is loaded with ps2_data.
signal shift_frame: std_logic := '0';
-- parity of the byte that was received from the device.
-- must match the parity bit received, else error occurred.
signal rx_parity: std_logic := '0';
-- parity bit that is sent with the frame, representing the
-- odd parity of the byte currently being sent
signal tx_parity: std_logic := '0';
-- when active, frame is loaded with the start bit, data on
-- tx_data, parity bit (tx_parity) and stop bit
-- this frame will be sent to the device.
signal load_tx_data: std_logic := '0';
-- when active bits 8 downto 1 from frame are loaded into
-- rx_data register. This is the byte received from the device.
signal load_rx_data: std_logic := '0';
-- intermediary signals used to debounce the inputs ps2_clk and ps2_data
signal ps2_clk_clean,ps2_data_clean: std_logic := '1';
-- debounce counter for the ps2_clk input and the ps2_data input.
signal clk_count,data_count: std_logic_vector(3 downto 0);
-- last value on ps2_clk and ps2_data.
signal clk_inter,data_inter: std_logic := '1';
begin
---------------------------------------------------------------------
-- FLAGS and PS2 CLOCK AND DATA LINES
---------------------------------------------------------------------
-- clean ps2_clk signal (debounce)
-- note that this introduces a delay in ps2_clk of
-- DEBOUNCE_DELAY clocks
process(clk)
begin
if(rising_edge(clk)) then
-- if the current bit on ps2_clk is different
-- from the last value, then reset counter
-- and retain value
if(ps2_clk /= clk_inter) then
clk_inter <= ps2_clk;
clk_count <= (others => '0');
-- if counter reached upper limit, then
-- the signal is clean
elsif(clk_count = DEBOUNCE_DELAY) then
ps2_clk_clean <= clk_inter;
-- ps2_clk did not change, but counter did not
-- reach limit. Increment counter
else
clk_count <= clk_count + 1;
end if;
end if;
end process;
-- clean ps2_data signal (debounce)
-- note that this introduces a delay in ps2_data of
-- DEBOUNCE_DELAY clocks
process(clk)
begin
if(rising_edge(clk)) then
-- if the current bit on ps2_data is different
-- from the last value, then reset counter
-- and retain value
if(ps2_data /= data_inter) then
data_inter <= ps2_data;
data_count <= (others => '0');
-- if counter reached upper limit, then
-- the signal is clean
elsif(data_count = DEBOUNCE_DELAY) then
ps2_data_clean <= data_inter;
-- ps2_data did not change, but counter did not
-- reach limit. Increment counter
else
data_count <= data_count + 1;
end if;
end if;
end process;
-- Synchronize ps2 entries
ps2_clk_s <= ps2_clk_clean when rising_edge(clk);
ps2_data_s <= ps2_data_clean when rising_edge(clk);
-- Assign parity from frame bits 8 downto 1, this is the parity
-- that should be received inside the frame on PARITY_BIT position
rx_parity <= parityrom(conv_integer(frame(8 downto 1)))
when rising_edge(clk);
-- The parity for the data to be sent
tx_parity <= parityrom(conv_integer(tx_data)) when rising_edge(clk);
-- Force ps2_clk to '0' if ps2_clk_h = '0', else release the line
-- ('Z' = +5Vcc because of pull-ups)
ps2_clk <= 'Z' when ps2_clk_h = '1' else '0';
-- Force ps2_data to '0' if ps2_data_h = '0', else release the line
-- ('Z' = +5Vcc because of pull-ups)
ps2_data <= 'Z' when ps2_data_h = '1' else '0';
-- Control busy flag. Interface is not busy while in idle state.
busy <= '0' when state = idle else '1';
-- reset the bit counter when in idle state.
reset_bit_count <= '1' when state = idle else '0';
-- Control shifting of the frame
-- When receiving from device, data is read
-- on the falling edge of ps2_clk
-- When sending to device, data is read by device
-- on the rising edge of ps2_clk
shift_frame <= '1' when state = rx_down_edge or
state = tx_clk_l else
'0';
---------------------------------------------------------------------
-- FINITE STATE MACHINE
---------------------------------------------------------------------
-- For the current state establish next state
-- and give necessary commands
manage_fsm: process(clk,rst,state,ps2_clk_s,ps2_data_s,write_data,tx_data,
bit_count,rx_parity,frame,delay_100us_done,
delay_20us_done,delay_63clk_done)
begin
-- if reset occurs, go to idle state.
if(rst = '1') then
state <= idle;
elsif(rising_edge(clk)) then
-- default values for these signals
-- ensures signals are reset to default value
-- when coditions for their activation are no
-- longer applied (transition to other state,
-- where signal should not be active)
-- Idle value for ps2_clk and ps2_data is 'Z'
ps2_clk_h <= '1';
ps2_data_h <= '1';
load_tx_data <= '0';
load_rx_data <= '0';
read_data <= '0';
err <= '0';
case state is
-- wait for the device to begin a transmission
-- by pulling the clock line low and go to state
-- rx_down_edge or, if write is high, the
-- client of this interface wants to send a byte
-- to the device and a transition is made to state
-- tx_force_clk_l
when idle =>
if(ps2_clk_s = '0') then
state <= rx_down_edge;
elsif(write_data = '1') then
state <= tx_force_clk_l;
else
state <= idle;
end if;
-- ps2_clk is high, check if all the bits have been read
-- if, last bit read, check parity, and if parity ok
-- load received data into rx_data.
-- else if more bits left, then wait for the ps2_clk to
-- go low
when rx_clk_h =>
if(bit_count = NUMBITS) then
if(not (rx_parity = frame(PARITY_BIT))) then
state <= rx_error_parity;
else
load_rx_data <= '1';
state <= rx_data_ready;
end if;
elsif(ps2_clk_s = '0') then
state <= rx_down_edge;
else
state <= rx_clk_h;
end if;
-- data must be read into frame in this state
-- the ps2_clk just transitioned from high to low
when rx_down_edge =>
state <= rx_clk_l;
-- ps2_clk line is low, wait for it to go high
when rx_clk_l =>
if(ps2_clk_s = '1') then
state <= rx_clk_h;
else
state <= rx_clk_l;
end if;
-- parity bit received is invalid
-- signal error and go back to idle.
when rx_error_parity =>
err <= '1';
state <= idle;
-- parity bit received was good
-- set read signal for the client to know
-- a new byte was received and is available on rx_data
when rx_data_ready =>
read_data <= '1';
state <= idle;
-- the client wishes to transmit a byte to the device
-- this is done by holding ps2_clk down for at least 100us
-- bringing down ps2_data, wait 20us and then releasing
-- the ps2_clk.
-- This constitutes a request to send command.
-- In this state, the ps2_clk line is held down and
-- the counter for waiting 100us is eanbled.
-- when the counter reached upper limit, transition
-- to tx_bring_data_down
when tx_force_clk_l =>
load_tx_data <= '1';
ps2_clk_h <= '0';
if(delay_100us_done = '1') then
state <= tx_bring_data_down;
else
state <= tx_force_clk_l;
end if;
-- with the ps2_clk line low bring ps2_data low
-- wait for 20us and then go to tx_release_clk
when tx_bring_data_down =>
-- keep clock line low
ps2_clk_h <= '0';
-- set data line low
-- when clock is released in the next state
-- the device will read bit 0 on data line
-- and this bit represents the start bit.
ps2_data_h <= '0'; -- start bit = '0'
if(delay_20us_done = '1') then
state <= tx_release_clk;
else
state <= tx_bring_data_down;
end if;
-- release the ps2_clk line
-- keep holding data line low
when tx_release_clk =>
ps2_clk_h <= '1';
-- must maintain data low,
-- otherwise will be released by default value
ps2_data_h <= '0';
state <= tx_first_wait_down_edge;
-- state is necessary because the clock signal
-- is not released instantaneously and, because of debounce,
-- delay is even greater.
-- Wait 63 clock periods for the clock line to release
-- then if clock is low then go to tx_clk_l
-- else wait until ps2_clk goes low.
when tx_first_wait_down_edge =>
ps2_data_h <= '0';
if(delay_63clk_done = '1') then
if(ps2_clk_s = '0') then
state <= tx_clk_l;
else
state <= tx_first_wait_down_edge;
end if;
else
state <= tx_first_wait_down_edge;
end if;
-- place the least significant bit from frame
-- on the data line
-- During this state the frame is shifted one
-- bit to the right
when tx_clk_l =>
ps2_data_h <= frame(0);
state <= tx_wait_up_edge;
-- wait for the clock to go high
-- this is the edge on which the device reads the data
-- on ps2_data.
-- keep holding ps2_data on frame(0) because else
-- will be released by default value.
-- Check if sent the last bit and if so, release data line
-- and go to state that wait for acknowledge
when tx_wait_up_edge =>
ps2_data_h <= frame(0);
-- NUMBITS - 1 because first (start bit = 0) bit was read
-- when the clock line was released in the request to
-- send command (see tx_bring_data_down state).
if(bit_count = NUMBITS-1) then
ps2_data_h <= '1';
state <= tx_wait_up_edge_before_ack;
-- if more bits to send, wait for the up edge
-- of ps2_clk
elsif(ps2_clk_s = '1') then
state <= tx_clk_h;
else
state <= tx_wait_up_edge;
end if;
-- ps2_clk is released, wait for down edge
-- and go to tx_clk_l when arrived
when tx_clk_h =>
ps2_data_h <= frame(0);
if(ps2_clk_s = '0') then
state <= tx_clk_l;
else
state <= tx_clk_h;
end if;
-- release ps2_data and wait for rising edge of ps2_clk
-- once this occurs, transition to tx_wait_ack
when tx_wait_up_edge_before_ack =>
ps2_data_h <= '1';
if(ps2_clk_s = '1') then
state <= tx_wait_ack;
else
state <= tx_wait_up_edge_before_ack;
end if;
-- wait for the falling edge of the clock line
-- if data line is low when this occurs, the
-- ack is received
-- else if data line is high, the device did not
-- acknowledge the transimission
when tx_wait_ack =>
if(ps2_clk_s = '0') then
if(ps2_data_s = '0') then
-- acknowledge received
state <= tx_received_ack;
else
-- acknowledge not received
state <= tx_error_no_ack;
end if;
else
state <= tx_wait_ack;
end if;
-- wait for ps2_clk to be released together with ps2_data
-- (bus to be idle) and go back to idle state
when tx_received_ack =>
if(ps2_clk_s = '1' and ps2_data_s = '1') then
state <= idle;
else
state <= tx_received_ack;
end if;
-- wait for ps2_clk to be released together with ps2_data
-- (bus to be idle) and go back to idle state
-- signal error for not receiving ack
when tx_error_no_ack =>
if(ps2_clk_s = '1' and ps2_data_s = '1') then
err <= '1';
state <= idle;
else
state <= tx_error_no_ack;
end if;
-- if invalid transition occurred, signal error and
-- go back to idle state
when others =>
err <= '1';
state <= idle;
end case;
end if;
end process manage_fsm;
---------------------------------------------------------------------
-- DELAY COUNTERS
---------------------------------------------------------------------
-- Enable the 100us counter only when state is tx_force_clk_l
delay_100us_counter_enable <= '1' when state = tx_force_clk_l else '0';
-- Counter for a 100us delay
-- after done counting, done signal remains active until
-- enable counter is reset.
delay_100us_counter: process(clk)
begin
if(rising_edge(clk)) then
if(delay_100us_counter_enable = '1') then
if(delay_100us_count = (DELAY_100US)) then
delay_100us_count <= delay_100us_count;
delay_100us_done <= '1';
else
delay_100us_count <= delay_100us_count + 1;
delay_100us_done <= '0';
end if;
else
delay_100us_count <= (others => '0');
delay_100us_done <= '0';
end if;
end if;
end process delay_100us_counter;
-- Enable the 20us counter only when state is tx_bring_data_down
delay_20us_counter_enable <= '1' when state = tx_bring_data_down else '0';
-- Counter for a 20us delay
-- after done counting, done signal remains active until
-- enable counter is reset.
delay_20us_counter: process(clk)
begin
if(rising_edge(clk)) then
if(delay_20us_counter_enable = '1') then
if(delay_20us_count = (DELAY_20US)) then
delay_20us_count <= delay_20us_count;
delay_20us_done <= '1';
else
delay_20us_count <= delay_20us_count + 1;
delay_20us_done <= '0';
end if;
else
delay_20us_count <= (others => '0');
delay_20us_done <= '0';
end if;
end if;
end process delay_20us_counter;
-- Enable the 63clk counter only when state is tx_first_wait_down_edge
delay_63clk_counter_enable <= '1' when state = tx_first_wait_down_edge else '0';
-- Counter for a 63 clock periods delay
-- after done counting, done signal remains active until
-- enable counter is reset.
delay_63clk_counter: process(clk)
begin
if(rising_edge(clk)) then
if(delay_63clk_counter_enable = '1') then
if(delay_63clk_count = (DELAY_63CLK)) then
delay_63clk_count <= delay_63clk_count;
delay_63clk_done <= '1';
else
delay_63clk_count <= delay_63clk_count + 1;
delay_63clk_done <= '0';
end if;
else
delay_63clk_count <= (others => '0');
delay_63clk_done <= '0';
end if;
end if;
end process delay_63clk_counter;
---------------------------------------------------------------------
-- BIT COUNTER AND FRAME SHIFTING LOGIC
---------------------------------------------------------------------
-- counts the number of bits shifted into the frame
-- or out of the frame.
bit_counter: process(clk)
begin
if(rising_edge(clk)) then
if(reset_bit_count = '1') then
bit_count <= (others => '0');
elsif(shift_frame = '1') then
bit_count <= bit_count + 1;
end if;
end if;
end process bit_counter;
-- shifts frame with one bit to right when shift_frame is acitve
-- and loads data into frame from tx_data then load_tx_data is high
load_tx_data_into_frame: process(clk)
begin
if(rising_edge(clk)) then
if(load_tx_data = '1') then
frame(8 downto 1) <= tx_data; -- byte to send
frame(0) <= '0'; -- start bit
frame(10) <= '1'; -- stop bit
frame(9) <= tx_parity; -- parity bit
elsif(shift_frame = '1') then
-- shift right 1 bit
frame(9 downto 0) <= frame(10 downto 1);
-- shift in from the ps2_data line
frame(10) <= ps2_data_s;
end if;
end if;
end process load_tx_data_into_frame;
-- Loads data from frame into rx_data output when data is ready
do_load_rx_data: process(clk)
begin
if(rising_edge(clk)) then
if(load_rx_data = '1') then
rx_data <= frame(8 downto 1);
end if;
end if;
end process do_load_rx_data;
end Behavioral;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.pkg_6502_defs.all;
use work.pkg_6502_decode.all;
-- synthesis translate_off
library std;
use std.textio.all;
--use work.file_io_pkg.all;
-- synthesis translate_on
entity proc_registers is
generic (
vector_page : std_logic_vector(15 downto 4) := X"FFF" );
port (
clock : in std_logic;
clock_en : in std_logic;
ready : in std_logic;
reset : in std_logic;
-- package pins
data_in : in std_logic_vector(7 downto 0);
data_out : out std_logic_vector(7 downto 0);
so_n : in std_logic := '1';
-- data from "data_oper"
alu_data : in std_logic_vector(7 downto 0);
mem_data : in std_logic_vector(7 downto 0);
mem_n : in std_logic := '0';
mem_z : in std_logic := '0';
mem_c : in std_logic := '0';
new_flags : in std_logic_vector(7 downto 0);
flags_imm : in std_logic;
-- from implied handler
set_a : in std_logic;
set_x : in std_logic;
set_y : in std_logic;
set_s : in std_logic;
set_data : in std_logic_vector(7 downto 0);
-- interrupt pins
set_i_flag : in std_logic;
vect_addr : in std_logic_vector(3 downto 0);
-- from processor state machine and decoder
sync : in std_logic; -- latch ireg
rwn : in std_logic;
latch_dreg : in std_logic;
vectoring : in std_logic;
reg_update : in std_logic;
flags_update : in std_logic := '0';
copy_d2p : in std_logic;
a_mux : in t_amux;
dout_mux : in t_dout_mux;
pc_oper : in t_pc_oper;
s_oper : in t_sp_oper;
adl_oper : in t_adl_oper;
adh_oper : in t_adh_oper;
-- outputs to processor state machine
i_reg : out std_logic_vector(7 downto 0) := X"00";
index_carry : out std_logic;
pc_carry : out std_logic;
branch_taken : out boolean;
-- register outputs
addr_out : out std_logic_vector(15 downto 0) := X"FFFF";
d_reg : out std_logic_vector(7 downto 0) := X"00";
a_reg : out std_logic_vector(7 downto 0) := X"00";
x_reg : out std_logic_vector(7 downto 0) := X"00";
y_reg : out std_logic_vector(7 downto 0) := X"00";
s_reg : out std_logic_vector(7 downto 0) := X"00";
p_reg : out std_logic_vector(7 downto 0) := X"00";
pc_out : out std_logic_vector(15 downto 0) );
end proc_registers;
architecture gideon of proc_registers is
signal dreg : std_logic_vector(7 downto 0) := X"00";
signal data_out_i : std_logic_vector(7 downto 0) := X"00";
signal a_reg_i : std_logic_vector(7 downto 0) := X"00";
signal x_reg_i : std_logic_vector(7 downto 0) := X"00";
signal y_reg_i : std_logic_vector(7 downto 0) := X"00";
signal selected_idx : std_logic_vector(7 downto 0) := X"00";
signal i_reg_i : std_logic_vector(7 downto 0) := X"00";
signal s_reg_i : unsigned(7 downto 0) := X"00";
signal p_reg_i : std_logic_vector(7 downto 0) := X"30";
signal pcl, pch : unsigned(7 downto 0) := X"FF";
signal adl, adh : unsigned(7 downto 0) := X"00";
signal pc_carry_i : std_logic;
signal pc_carry_d : std_logic;
signal branch_flag : std_logic;
signal reg_out : std_logic_vector(7 downto 0);
signal h_reg_i : unsigned(7 downto 0);
signal ready_d1 : std_logic;
signal so_d : std_logic;
alias C_flag : std_logic is p_reg_i(0);
alias Z_flag : std_logic is p_reg_i(1);
alias I_flag : std_logic is p_reg_i(2);
alias D_flag : std_logic is p_reg_i(3);
alias B_flag : std_logic is p_reg_i(4);
alias V_flag : std_logic is p_reg_i(6);
alias N_flag : std_logic is p_reg_i(7);
signal p_reg_push : std_logic_vector(7 downto 0);
signal adh_clash : std_logic;
begin
p_reg_push <= p_reg_i(7 downto 6) & '1' & not vectoring & p_reg_i(3 downto 0);
process(clock)
variable pcl_t : unsigned(8 downto 0);
variable adl_t : unsigned(8 downto 0);
variable v_adh : unsigned(7 downto 0);
variable v_reg_sel : std_logic_vector(1 downto 0);
-- synthesis translate_off
file fout : text;
variable count : integer := 0;
variable L : line;
-- synthesis translate_on
begin
if rising_edge(clock) then
if clock_en='1' then
if flags_imm='1' then
p_reg_i <= new_flags;
end if;
-- Logic for the crazy instructions that and with adh + 1
h_reg_i <= X"FF";
ready_d1 <= ready;
adh_clash <= '0';
if ready_d1='1' then
-- $93 $9E/$9F $9C $9B
if i_reg_i(4 downto 0) = "10011" or i_reg_i(4 downto 1) = "1111" or i_reg_i(4 downto 0) = "11100" or i_reg_i(4 downto 0) = "11011" then
h_reg_i <= adh + 1;
if i_reg_i(7 downto 5) = "100" then
adh_clash <= '1';
end if;
end if;
end if;
if ready='1' or rwn='0' then
---- synthesis translate_off
-- if count = 0 then
-- file_open(fout, "trace.txt", WRITE_MODE);
-- elsif count = 180000 then
-- file_close(fout);
-- elsif count < 180000 then
-- write(L, "PC:" & VecToHex(pch, 2) & VecToHex(pcl, 2));
-- write(L, " AD:" & VecToHex(adh, 2) & VecToHex(adl, 2));
-- write(L, " A:" & VecToHex(a_reg_i, 2));
-- write(L, " X:" & VecToHex(x_reg_i, 2));
-- write(L, " Y:" & VecToHex(y_reg_i, 2));
-- write(L, " S:" & VecToHex(s_reg_i, 2));
-- write(L, " P:" & VecToHex(p_reg_i, 2));
-- write(L, " D:" & VecToHex(dreg, 2));
-- write(L, " DO:" & VecToHex(data_out_i, 2));
-- write(L, " I:" & VecToHex(i_reg_i, 2));
-- writeline(fout, L);
-- end if;
-- count := count + 1;
---- synthesis translate_on
-- Data Register
if latch_dreg='1' then
if rwn = '0' then
dreg <= data_out_i;
else
dreg <= data_in;
end if;
end if;
-- Flags Register
if copy_d2p = '1' then
p_reg_i <= dreg;
elsif reg_update='1' then
p_reg_i <= new_flags;
elsif flags_update='1' then
C_flag <= mem_c;
N_flag <= mem_n;
Z_flag <= mem_z;
end if;
if set_i_flag='1' then
I_flag <= '1';
end if;
so_d <= so_n;
if so_n='0' and so_d = '1' then -- assumed that so_n is synchronous
V_flag <= '1';
end if;
-- Instruction Register
if sync='1' then
if vectoring='1' then
i_reg_i <= X"00";
else
i_reg_i <= data_in;
end if;
end if;
-- Logic for the Program Counter
pc_carry_i <= '0';
case pc_oper is
when increment =>
if pcl = X"FF" then
pch <= pch + 1;
end if;
pcl <= pcl + 1;
when copy =>
pcl <= unsigned(dreg);
pch <= unsigned(data_in);
when from_alu =>
pcl_t := ('0' & pcl) + unsigned(dreg(7) & dreg); -- sign extended 1 bit
pcl <= pcl_t(7 downto 0);
pc_carry_i <= pcl_t(8);
pc_carry_d <= dreg(7);
when others => -- keep (and fix)
if pc_carry_i='1' then
if pc_carry_d='1' then
pch <= pch - 1;
else
pch <= pch + 1;
end if;
end if;
end case;
-- Logic for the Address register
case adl_oper is
when increment =>
adl <= adl + 1;
when add_idx =>
adl_t := unsigned('0' & dreg) + unsigned('0' & selected_idx);
adl <= adl_t(7 downto 0);
index_carry <= adl_t(8);
when load_bus =>
adl <= unsigned(data_in);
when copy_dreg =>
adl <= unsigned(dreg);
when others =>
null;
end case;
case adh_oper is
when increment =>
v_adh := adh + 1;
if adh_clash = '1' then
v_reg_sel := i_reg_i(1 downto 0);
case v_reg_sel is
when "00" => v_adh := v_adh and unsigned(y_reg_i);
when "01" => v_adh := v_adh and unsigned(a_reg_i);
when "10" => v_adh := v_adh and unsigned(x_reg_i);
when others => v_adh := v_adh and unsigned(x_reg_i) and unsigned(a_reg_i);
end case;
end if;
adh <= v_adh;
when clear =>
adh <= (others => '0');
when load_bus =>
adh <= unsigned(data_in);
when others =>
null;
end case;
-- Logic for ALU register
if reg_update='1' then
if set_a='1' then
a_reg_i <= set_data;
elsif store_a_from_alu(i_reg_i) then
a_reg_i <= alu_data;
end if;
end if;
-- Logic for Index registers
if reg_update='1' then
if set_x='1' then
x_reg_i <= set_data;
elsif load_x(i_reg_i) then
x_reg_i <= alu_data;
end if;
end if;
if reg_update='1' then
if set_y='1' then
y_reg_i <= set_data;
elsif load_y(i_reg_i) then
y_reg_i <= dreg;
end if;
end if;
-- Logic for the Stack Pointer
if reg_update='1' and set_s='1' then
s_reg_i <= unsigned(set_data);
else
case s_oper is
when increment =>
s_reg_i <= s_reg_i + 1;
when decrement =>
s_reg_i <= s_reg_i - 1;
when others =>
null;
end case;
end if;
end if;
end if;
-- Reset
if reset='1' then
p_reg_i <= X"34"; -- I=1
index_carry <= '0';
so_d <= '1';
end if;
end if;
end process;
with i_reg_i(7 downto 6) select branch_flag <=
N_flag when "00",
V_flag when "01",
C_flag when "10",
Z_flag when "11",
'0' when others;
branch_taken <= (branch_flag xor not i_reg_i(5))='1';
with a_mux select addr_out <=
vector_page & vect_addr when 0,
std_logic_vector(adh & adl) when 1,
X"01" & std_logic_vector(s_reg_i) when 2,
std_logic_vector(pch & pcl) when 3;
with i_reg_i(1 downto 0) select reg_out <=
std_logic_vector(h_reg_i) and y_reg_i when "00",
std_logic_vector(h_reg_i) and a_reg_i when "01",
std_logic_vector(h_reg_i) and x_reg_i when "10",
std_logic_vector(h_reg_i) and a_reg_i and x_reg_i when others;
with dout_mux select data_out_i <=
dreg when reg_d,
a_reg_i when reg_accu,
reg_out when reg_axy,
p_reg_push when reg_flags,
std_logic_vector(pcl) when reg_pcl,
std_logic_vector(pch) when reg_pch,
mem_data when shift_res,
X"FF" when others;
data_out <= data_out_i;
selected_idx <= y_reg_i when select_index_y(i_reg_i) else x_reg_i;
pc_carry <= pc_carry_i;
s_reg <= std_logic_vector(s_reg_i);
p_reg <= p_reg_i;
i_reg <= i_reg_i;
a_reg <= a_reg_i;
x_reg <= x_reg_i;
y_reg <= y_reg_i;
d_reg <= dreg;
pc_out <= std_logic_vector(pch & pcl);
end gideon;
|
-------------------------------------------------------------------------------
-- axi_datamover_rd_sf.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_rd_sf.vhd
--
-- Description:
-- This file implements the AXI DataMover Read (MM2S) Store and Forward module.
-- The design utilizes the AXI DataMover's new address pipelining
-- control function. The design is such that predictive address
-- pipelining can be supported on the AXI Read Bus without over-commiting
-- the internal Data FIFO and potentially throttling the Read Data Channel
-- if the Data FIFO goes full.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library lib_pkg_v1_0_2;
use lib_pkg_v1_0_2.lib_pkg.all;
use lib_pkg_v1_0_2.lib_pkg.clog2;
library axi_datamover_v5_1_9;
use axi_datamover_v5_1_9.axi_datamover_sfifo_autord;
use axi_datamover_v5_1_9.axi_datamover_fifo;
-------------------------------------------------------------------------------
entity axi_datamover_rd_sf is
generic (
C_SF_FIFO_DEPTH : Integer range 128 to 8192 := 512;
-- Sets the desired depth of the internal Data FIFO.
C_MAX_BURST_LEN : Integer range 2 to 256 := 16;
-- Indicates the max burst length being used by the external
-- AXI4 Master for each AXI4 transfer request.
C_DRE_IS_USED : Integer range 0 to 1 := 0;
-- Indicates if the external Master is utilizing a DRE on
-- the stream input to this module.
C_DRE_CNTL_FIFO_DEPTH : Integer range 1 to 32 := 1;
-- Specifies the depth of the internal dre control queue fifo
C_DRE_ALIGN_WIDTH : Integer range 1 to 3 := 2;
-- Sets the width of the DRE alignment control ports
C_MMAP_DWIDTH : Integer range 32 to 1024 := 64;
-- Sets the AXI4 Memory Mapped Bus Data Width
C_STREAM_DWIDTH : Integer range 8 to 1024 := 32;
-- Sets the Stream Data Width for the Input and Output
-- Data streams.
C_STRT_SF_OFFSET_WIDTH : Integer range 1 to 7 := 2;
-- Sets the bit width of the starting address offset port
-- This should be set to log2(C_MMAP_DWIDTH/C_STREAM_DWIDTH)
C_ENABLE_MM2S_TKEEP : integer range 0 to 1 := 1;
C_TAG_WIDTH : Integer range 1 to 8 := 4;
-- Indicates the width of the Tag field of the input DRE command
C_FAMILY : String := "virtex7"
-- Indicates the target FPGA Family.
);
port (
-- Clock and Reset inputs --------------------------------------------
--
aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- Reset input --
reset : in std_logic; --
-- Reset used for the internal syncronization logic --
----------------------------------------------------------------------
-- DataMover Read Side Address Pipelining Control Interface ----------
--
ok_to_post_rd_addr : Out Std_logic; --
-- Indicates that the transfer token pool has at least --
-- one token available to borrow --
--
rd_addr_posted : In std_logic; --
-- Indication that a read address has been posted to AXI4 --
--
rd_xfer_cmplt : In std_logic; --
-- Indicates that the Datamover has completed a Read Data --
-- transfer on the AXI4 --
----------------------------------------------------------------------
-- Read Side Stream In from DataMover MM2S Read Data Controller ----------------------
--
sf2sin_tready : Out Std_logic; --
-- DRE Stream READY input --
--
sin2sf_tvalid : In std_logic; --
-- DRE Stream VALID Output --
--
sin2sf_tdata : In std_logic_vector(C_MMAP_DWIDTH-1 downto 0); --
-- DRE Stream DATA input --
--
sin2sf_tkeep : In std_logic_vector((C_MMAP_DWIDTH/8)-1 downto 0); --
-- DRE Stream STRB input --
--
sin2sf_tlast : In std_logic; --
-- DRE Xfer LAST input --
--------------------------------------------------------------------------------------
-- RDC Store and Forward Supplimental Controls ---------------------
-- These are time aligned and qualified with the RDC Stream Input --
--
data2sf_cmd_cmplt : In std_logic; --
data2sf_dre_flush : In std_logic; --
--------------------------------------------------------------------
-- DRE Control Interface from the Command Calculator -----------------------------
--
dre2mstr_cmd_ready : Out std_logic ; --
-- Indication from the DRE that the command is being --
-- accepted from the Command Calculator --
--
mstr2dre_cmd_valid : In std_logic; --
-- The next command valid indication to the DRE --
-- from the Command Calculator --
--
mstr2dre_tag : In std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The next command tag --
--
mstr2dre_dre_src_align : In std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0); --
-- The source (input) alignment for the DRE --
--
mstr2dre_dre_dest_align : In std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0); --
-- The destinstion (output) alignment for the DRE --
--
-- mstr2dre_btt : In std_logic_vector(C_BTT_USED-1 downto 0); --
-- -- The bytes to transfer value for the input command --
--
mstr2dre_drr : In std_logic; --
-- The starting tranfer of a sequence of transfers --
--
mstr2dre_eof : In std_logic; --
-- The endiing tranfer of a sequence of transfers --
--
-- mstr2dre_cmd_cmplt : In std_logic; --
-- -- The last tranfer command of a sequence of transfers --
-- -- spawned from a single parent command --
--
mstr2dre_calc_error : In std_logic; --
-- Indication if the next command in the calculation pipe --
-- has a calculation error --
--
mstr2dre_strt_offset : In std_logic_vector(C_STRT_SF_OFFSET_WIDTH-1 downto 0);--
-- Outputs the starting offset of a transfer. This is used with Store --
-- and Forward Packer/Unpacker logic --
-----------------------------------------------------------------------------------
-- MM2S DRE Control -------------------------------------------------------------
--
sf2dre_new_align : Out std_logic; --
-- Active high signal indicating new DRE aligment required --
--
sf2dre_use_autodest : Out std_logic; --
-- Active high signal indicating to the DRE to use an auto- --
-- calculated desination alignment based on the last transfer --
--
sf2dre_src_align : Out std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0); --
-- Bit field indicating the byte lane of the first valid data byte --
-- being sent to the DRE --
--
sf2dre_dest_align : Out std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0); --
-- Bit field indicating the desired byte lane of the first valid data byte --
-- to be output by the DRE --
--
sf2dre_flush : Out std_logic; --
-- Active high signal indicating to the DRE to flush the current --
-- contents to the output register in preparation of a new alignment --
-- that will be comming on the next transfer input --
---------------------------------------------------------------------------------
-- Stream Out -----------------------------------------------------------------------
--
sout2sf_tready : In std_logic; --
-- Write READY input from the Stream Master --
--
sf2sout_tvalid : Out std_logic; --
-- Write VALID output to the Stream Master --
--
sf2sout_tdata : Out std_logic_vector(C_STREAM_DWIDTH-1 downto 0); --
-- Write DATA output to the Stream Master --
--
sf2sout_tkeep : Out std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- Write DATA output to the Stream Master --
--
sf2sout_tlast : Out std_logic --
-- Write LAST output to the Stream Master --
--------------------------------------------------------------------------------------
);
end entity axi_datamover_rd_sf;
architecture implementation of axi_datamover_rd_sf is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Functions ---------------------------------------------------------------------------
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_fifo_cnt_width
--
-- Function Description:
-- simple function to set the width of the data fifo read
-- and write count outputs.
-------------------------------------------------------------------
function funct_get_fifo_cnt_width (fifo_depth : integer)
return integer is
Variable temp_width : integer := 8;
begin
if (fifo_depth = 1) then
temp_width := 1;
elsif (fifo_depth = 2) then
temp_width := 2;
elsif (fifo_depth <= 4) then
temp_width := 3;
elsif (fifo_depth <= 8) then
temp_width := 4;
elsif (fifo_depth <= 16) then
temp_width := 5;
elsif (fifo_depth <= 32) then
temp_width := 6;
elsif (fifo_depth <= 64) then
temp_width := 7;
elsif (fifo_depth <= 128) then
temp_width := 8;
elsif (fifo_depth <= 256) then
temp_width := 9;
elsif (fifo_depth <= 512) then
temp_width := 10;
elsif (fifo_depth <= 1024) then
temp_width := 11;
elsif (fifo_depth <= 2048) then
temp_width := 12;
elsif (fifo_depth <= 4096) then
temp_width := 13;
else -- assume 8192 depth
temp_width := 14;
end if;
Return (temp_width);
end function funct_get_fifo_cnt_width;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_wrcnt_lsrip
--
-- Function Description:
-- Calculates the ls index of the upper slice of the data fifo
-- write count needed to repesent one max burst worth of data
-- present in the fifo.
--
-------------------------------------------------------------------
function funct_get_wrcnt_lsrip (max_burst_dbeats : integer) return integer is
Variable temp_ls_index : Integer := 0;
begin
if (max_burst_dbeats <= 2) then
temp_ls_index := 1;
elsif (max_burst_dbeats <= 4) then
temp_ls_index := 2;
elsif (max_burst_dbeats <= 8) then
temp_ls_index := 3;
elsif (max_burst_dbeats <= 16) then
temp_ls_index := 4;
elsif (max_burst_dbeats <= 32) then
temp_ls_index := 5;
elsif (max_burst_dbeats <= 64) then
temp_ls_index := 6;
elsif (max_burst_dbeats <= 128) then
temp_ls_index := 7;
else
temp_ls_index := 8;
end if;
Return (temp_ls_index);
end function funct_get_wrcnt_lsrip;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_stall_thresh
--
-- Function Description:
-- Calculates the Stall threshold for the input side of the Data
-- FIFO. If DRE is being used by the DataMover, then the threshold
-- must be reduced to account for the potential of an extra write
-- databeat per request (DRE alignment dependent).
--
-------------------------------------------------------------------
function funct_get_stall_thresh (dre_is_used : integer;
max_xfer_length : integer;
data_fifo_depth : integer;
pipeline_delay_clks : integer;
fifo_settling_clks : integer) return integer is
Constant DRE_PIPE_DELAY : integer := 2; -- clks
Variable var_num_max_xfers_allowed : Integer := 0;
Variable var_dre_dbeat_overhead : Integer := 0;
Variable var_delay_fudge_factor : Integer := 0;
Variable var_thresh_headroom : Integer := 0;
Variable var_stall_thresh : Integer := 0;
begin
var_num_max_xfers_allowed := data_fifo_depth/max_xfer_length;
var_dre_dbeat_overhead := var_num_max_xfers_allowed * dre_is_used;
var_delay_fudge_factor := (dre_is_used * DRE_PIPE_DELAY) +
pipeline_delay_clks +
fifo_settling_clks;
var_thresh_headroom := max_xfer_length +
var_dre_dbeat_overhead +
var_delay_fudge_factor;
-- Scale the result to be in max transfer length increments
var_stall_thresh := (data_fifo_depth - var_thresh_headroom)/max_xfer_length;
Return (var_stall_thresh);
end function funct_get_stall_thresh;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_size_drecntl_fifo
--
-- Function Description:
-- Assures that the DRE control fifo depth is at least 4 deep else it
-- is equal to the number of max burst transfers that can fit in the
-- Store and Forward Data FIFO.
--
-------------------------------------------------------------------
function funct_size_drecntl_fifo (sf_fifo_depth : integer;
max_burst_length : integer) return integer is
Constant NEEDED_FIFO_DEPTH : integer := sf_fifo_depth/max_burst_length;
Variable temp_fifo_depth : Integer := 4;
begin
If (NEEDED_FIFO_DEPTH < 4) Then
temp_fifo_depth := 4;
Else
temp_fifo_depth := NEEDED_FIFO_DEPTH;
End if;
Return (temp_fifo_depth);
end function funct_size_drecntl_fifo;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_cntr_width
--
-- Function Description:
-- Detirmine the width needed for the address offset counter used
-- for the data fifo mux selects.
--
-------------------------------------------------------------------
function funct_get_cntr_width (num_count_states : integer) return integer is
Variable lvar_temp_width : Integer := 1;
begin
if (num_count_states <= 2) then
lvar_temp_width := 1;
elsif (num_count_states <= 4) then
lvar_temp_width := 2;
elsif (num_count_states <= 8) then
lvar_temp_width := 3;
elsif (num_count_states <= 16) then
lvar_temp_width := 4;
elsif (num_count_states <= 32) then
lvar_temp_width := 5;
elsif (num_count_states <= 64) then
lvar_temp_width := 6;
Else -- 128 cnt states
lvar_temp_width := 7;
end if;
Return (lvar_temp_width);
end function funct_get_cntr_width;
-- Constants ---------------------------------------------------------------------------
Constant LOGIC_LOW : std_logic := '0';
Constant LOGIC_HIGH : std_logic := '1';
Constant BLK_MEM_FIFO : integer := 1;
Constant SRL_FIFO : integer := 0;
Constant NOT_NEEDED : integer := 0;
Constant MMAP_TKEEP_WIDTH : integer := C_MMAP_DWIDTH/8; -- bits
Constant TLAST_WIDTH : integer := 1; -- bits
Constant CMPLT_WIDTH : integer := 1; -- bits
Constant DRE_FLUSH_WIDTH : integer := 1; -- bits
Constant DATA_FIFO_DEPTH : integer := C_SF_FIFO_DEPTH;
Constant DATA_FIFO_CNT_WIDTH : integer := funct_get_fifo_cnt_width(DATA_FIFO_DEPTH);
Constant DF_WRCNT_RIP_LS_INDEX : integer := funct_get_wrcnt_lsrip(C_MAX_BURST_LEN);
Constant DATA_FIFO_WIDTH : integer := C_MMAP_DWIDTH +
MMAP_TKEEP_WIDTH*C_ENABLE_MM2S_TKEEP +
TLAST_WIDTH +
CMPLT_WIDTH +
DRE_FLUSH_WIDTH;
Constant DATA_OUT_LSB_INDEX : integer := 0;
Constant DATA_OUT_MSB_INDEX : integer := C_MMAP_DWIDTH-1;
Constant TKEEP_OUT_LSB_INDEX : integer := DATA_OUT_MSB_INDEX+1;
Constant TKEEP_OUT_MSB_INDEX : integer := (TKEEP_OUT_LSB_INDEX+MMAP_TKEEP_WIDTH*C_ENABLE_MM2S_TKEEP)-1*C_ENABLE_MM2S_TKEEP;
Constant TLAST_OUT_INDEX : integer := TKEEP_OUT_MSB_INDEX+1*C_ENABLE_MM2S_TKEEP;
Constant CMPLT_OUT_INDEX : integer := TLAST_OUT_INDEX+1;
Constant DRE_FLUSH_OUT_INDEX : integer := CMPLT_OUT_INDEX+1;
Constant TOKEN_POOL_SIZE : integer := C_SF_FIFO_DEPTH / C_MAX_BURST_LEN;
Constant TOKEN_CNTR_WIDTH : integer := clog2(TOKEN_POOL_SIZE)+1;
Constant TOKEN_CNT_ZERO : Unsigned(TOKEN_CNTR_WIDTH-1 downto 0) :=
TO_UNSIGNED(0, TOKEN_CNTR_WIDTH);
Constant TOKEN_CNT_ONE : Unsigned(TOKEN_CNTR_WIDTH-1 downto 0) :=
TO_UNSIGNED(1, TOKEN_CNTR_WIDTH);
Constant TOKEN_CNT_MAX : Unsigned(TOKEN_CNTR_WIDTH-1 downto 0) :=
TO_UNSIGNED(TOKEN_POOL_SIZE, TOKEN_CNTR_WIDTH);
Constant THRESH_COMPARE_WIDTH : integer := TOKEN_CNTR_WIDTH+2;
Constant RD_PATH_PIPE_DEPTH : integer := 2; -- clocks excluding DRE
Constant WRCNT_SETTLING_TIME : integer := 2; -- data fifo push or pop settling clocks
Constant DRE_COMPENSATION : integer := 0; -- DRE does not contribute since it is on
-- the output side of the Store and Forward
Constant RD_ADDR_POST_STALL_THRESH : integer :=
funct_get_stall_thresh(DRE_COMPENSATION ,
C_MAX_BURST_LEN ,
C_SF_FIFO_DEPTH ,
RD_PATH_PIPE_DEPTH ,
WRCNT_SETTLING_TIME);
Constant RD_ADDR_POST_STALL_THRESH_US : Unsigned(THRESH_COMPARE_WIDTH-1 downto 0) :=
TO_UNSIGNED(RD_ADDR_POST_STALL_THRESH ,
THRESH_COMPARE_WIDTH);
Constant UNCOM_WRCNT_1 : Unsigned(DATA_FIFO_CNT_WIDTH-1 downto 0) :=
TO_UNSIGNED(1, DATA_FIFO_CNT_WIDTH);
Constant UNCOM_WRCNT_0 : Unsigned(DATA_FIFO_CNT_WIDTH-1 downto 0) :=
TO_UNSIGNED(0, DATA_FIFO_CNT_WIDTH);
Constant USE_SYNC_FIFO : integer := 0;
Constant SRL_FIFO_PRIM : integer := 2;
Constant TAG_WIDTH : integer := C_TAG_WIDTH;
Constant SRC_ALIGN_WIDTH : integer := C_DRE_ALIGN_WIDTH;
Constant DEST_ALIGN_WIDTH : integer := C_DRE_ALIGN_WIDTH;
Constant DRR_WIDTH : integer := 1;
Constant EOF_WIDTH : integer := 1;
Constant CALC_ERR_WIDTH : integer := 1;
Constant SF_OFFSET_WIDTH : integer := C_STRT_SF_OFFSET_WIDTH;
-- Signals ---------------------------------------------------------------------------
signal sig_good_sin_strm_dbeat : std_logic := '0';
signal sig_strm_sin_ready : std_logic := '0';
signal sig_good_sout_strm_dbeat : std_logic := '0';
signal sig_sout2sf_tready : std_logic := '0';
signal sig_sf2sout_tvalid : std_logic := '0';
signal sig_sf2sout_tdata : std_logic_vector(C_STREAM_DWIDTH-1 downto 0) := (others => '0');
signal sig_sf2sout_tkeep : std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0) := (others => '0');
signal sig_sf2sout_tlast : std_logic := '0';
signal sig_sf2dre_flush : std_logic := '0';
signal sig_push_data_fifo : std_logic := '0';
signal sig_pop_data_fifo : std_logic := '0';
signal sig_data_fifo_full : std_logic := '0';
signal sig_data_fifo_data_in : std_logic_vector(DATA_FIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_data_fifo_dvalid : std_logic := '0';
signal sig_data_fifo_data_out : std_logic_vector(DATA_FIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_data_fifo_wr_cnt : std_logic_vector(DATA_FIFO_CNT_WIDTH-1 downto 0) := (others => '0');
signal sig_fifo_wr_cnt_unsgnd : unsigned(DATA_FIFO_CNT_WIDTH-1 downto 0) := (others => '0');
signal sig_wrcnt_mblen_slice : unsigned(DATA_FIFO_CNT_WIDTH-1 downto
DF_WRCNT_RIP_LS_INDEX) := (others => '0');
signal sig_ok_to_post_rd_addr : std_logic := '0';
signal sig_rd_addr_posted : std_logic := '0';
signal sig_rd_xfer_cmplt : std_logic := '0';
signal sig_taking_last_token : std_logic := '0';
signal sig_stall_rd_addr_posts : std_logic := '0';
signal sig_incr_token_cntr : std_logic := '0';
signal sig_decr_token_cntr : std_logic := '0';
signal sig_token_eq_max : std_logic := '0';
signal sig_token_eq_zero : std_logic := '0';
signal sig_token_eq_one : std_logic := '0';
signal sig_token_cntr : Unsigned(TOKEN_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_tokens_commited : Unsigned(TOKEN_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_commit_plus_actual : unsigned(THRESH_COMPARE_WIDTH-1 downto 0) := (others => '0');
signal sig_cntl_fifo_has_data : std_logic := '0';
signal sig_get_cntl_fifo_data : std_logic := '0';
signal sig_curr_tag_reg : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_curr_src_align_reg : std_logic_vector(SRC_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_curr_dest_align_reg : std_logic_vector(DEST_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_curr_drr_reg : std_logic := '0';
signal sig_curr_eof_reg : std_logic := '0';
signal sig_curr_calc_error_reg : std_logic := '0';
signal sig_curr_strt_offset_reg : std_logic_vector(SF_OFFSET_WIDTH-1 downto 0) := (others => '0');
signal sig_ld_dre_cntl_reg : std_logic := '0';
signal sig_dfifo_data_out : std_logic_vector(C_MMAP_DWIDTH-1 downto 0) := (others => '0');
signal sig_dfifo_tkeep_out : std_logic_vector(MMAP_TKEEP_WIDTH-1 downto 0) := (others => '0');
signal sig_dfifo_tlast_out : std_logic := '0';
signal sig_dfifo_cmd_cmplt_out : std_logic := '0';
signal sig_dfifo_dre_flush_out : std_logic := '0';
begin --(architecture implementation)
-- Read Side (MM2S) Control Flags port connections
ok_to_post_rd_addr <= sig_ok_to_post_rd_addr ;
sig_rd_addr_posted <= rd_addr_posted ;
sig_rd_xfer_cmplt <= rd_xfer_cmplt ;
-- Output Stream Port connections
sig_sout2sf_tready <= sout2sf_tready ;
sf2sout_tvalid <= sig_sf2sout_tvalid ;
sf2sout_tdata <= sig_sf2sout_tdata ;
--sf2sout_tkeep <= sig_sf2sout_tkeep ;
sf2sout_tlast <= sig_sf2sout_tlast and
sig_sf2sout_tvalid ;
GEN_MM2S_TKEEP_ENABLE4 : if C_ENABLE_MM2S_TKEEP = 1 generate
begin
sf2sout_tkeep <= sig_sf2sout_tkeep ;
end generate GEN_MM2S_TKEEP_ENABLE4;
GEN_MM2S_TKEEP_DISABLE4 : if C_ENABLE_MM2S_TKEEP = 0 generate
begin
sf2sout_tkeep <= (others => '1');
end generate GEN_MM2S_TKEEP_DISABLE4;
-- Input Stream port connections
sf2sin_tready <= sig_strm_sin_ready;
sig_strm_sin_ready <= not(sig_data_fifo_full); -- Throttle if Read Side Data fifo goes full.
-- This should never happen if read address
-- posting control is working properly.
-- Stream transfer qualifiers
sig_good_sin_strm_dbeat <= sin2sf_tvalid and
sig_strm_sin_ready;
sig_good_sout_strm_dbeat <= sig_sf2sout_tvalid and
sig_sout2sf_tready;
----------------------------------------------------------------
-- Unpacking Logic ------------------------------------------
----------------------------------------------------------------
------------------------------------------------------------
-- If Generate
--
-- Label: OMIT_UNPACKING
--
-- If Generate Description:
-- Omits any unpacking logic in the Store and Forward module.
-- The Stream and MMap data widths are the same. The Data FIFO
-- output can be connected directly to the stream outputs.
--
------------------------------------------------------------
OMIT_UNPACKING : if (C_MMAP_DWIDTH = C_STREAM_DWIDTH) generate
signal lsig_cmd_loaded : std_logic := '0';
signal lsig_ld_cmd : std_logic := '0';
signal lsig_cmd_cmplt_dbeat : std_logic := '0';
signal lsig_cmd_cmplt : std_logic := '0';
begin
-- Data FIFO Output to the stream attachments
sig_sf2sout_tvalid <= sig_data_fifo_dvalid and
lsig_cmd_loaded ;
sig_sf2sout_tdata <= sig_dfifo_data_out ;
sig_sf2sout_tkeep <= sig_dfifo_tkeep_out ;
sig_sf2sout_tlast <= sig_dfifo_tlast_out ;
sig_sf2dre_flush <= sig_dfifo_dre_flush_out ;
-- Control for reading the Data FIFO
sig_pop_data_fifo <= lsig_cmd_loaded and
sig_sout2sf_tready and
sig_data_fifo_dvalid;
-- Control for reading the Command/Offset FIFO
sig_get_cntl_fifo_data <= lsig_ld_cmd ;
-- Control for loading the DRE Control Reg
sig_ld_dre_cntl_reg <= lsig_ld_cmd ;
lsig_cmd_cmplt_dbeat <= sig_dfifo_cmd_cmplt_out and
lsig_cmd_loaded and
sig_data_fifo_dvalid and
sig_sout2sf_tready ;
-- Generate the control that loads the DRE
lsig_ld_cmd <= (sig_cntl_fifo_has_data and -- startup or gap case
not(lsig_cmd_loaded)) or
(sig_cntl_fifo_has_data and -- back to back commands
lsig_cmd_cmplt_dbeat);
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_CMD_LOADED
--
-- Process Description:
-- Implements the flop indicating a command from the cmd fifo
-- has been loaded into the DRE Output Register.
--
-------------------------------------------------------------
IMP_CMD_LOADED : process (aclk)
begin
if (aclk'event and aclk = '1') then
if (reset = '1') then
lsig_cmd_loaded <= '0';
Elsif (lsig_ld_cmd = '1' ) Then
lsig_cmd_loaded <= '1';
elsif (sig_cntl_fifo_has_data = '0' and -- No more commands queued and
lsig_cmd_cmplt_dbeat = '1') then
lsig_cmd_loaded <= '0';
else
null; -- Hold Current State
end if;
end if;
end process IMP_CMD_LOADED;
end generate OMIT_UNPACKING;
------------------------------------------------------------
-- If Generate
--
-- Label: INCLUDE_UNPACKING
--
-- If Generate Description:
-- Includes unpacking logic in the Store and Forward module.
-- The MMap Data bus is wider than the Stream width.
--
------------------------------------------------------------
INCLUDE_UNPACKING : if (C_MMAP_DWIDTH > C_STREAM_DWIDTH) generate
Constant MMAP2STRM_WIDTH_RATO : integer := C_MMAP_DWIDTH/C_STREAM_DWIDTH;
Constant DATA_SLICE_WIDTH : integer := C_STREAM_DWIDTH;
Constant TKEEP_SLICE_WIDTH : integer := C_STREAM_DWIDTH/8;
Constant FLAG_SLICE_WIDTH : integer := TLAST_WIDTH;
Constant OFFSET_CNTR_WIDTH : integer := funct_get_cntr_width(MMAP2STRM_WIDTH_RATO);
Constant OFFSET_CNT_ONE : unsigned(OFFSET_CNTR_WIDTH-1 downto 0) :=
TO_UNSIGNED(1, OFFSET_CNTR_WIDTH);
Constant OFFSET_CNT_MAX : unsigned(OFFSET_CNTR_WIDTH-1 downto 0) :=
TO_UNSIGNED(MMAP2STRM_WIDTH_RATO-1, OFFSET_CNTR_WIDTH);
-- Types -----------------------------------------------------------------------------
type lsig_data_slice_type is array(MMAP2STRM_WIDTH_RATO-1 downto 0) of
std_logic_vector(DATA_SLICE_WIDTH-1 downto 0);
type lsig_tkeep_slice_type is array(MMAP2STRM_WIDTH_RATO downto 0) of
std_logic_vector(TKEEP_SLICE_WIDTH-1 downto 0);
type lsig_flag_slice_type is array(MMAP2STRM_WIDTH_RATO-1 downto 0) of
std_logic_vector(FLAG_SLICE_WIDTH-1 downto 0);
-- local signals
signal lsig_0ffset_cntr : unsigned(OFFSET_CNTR_WIDTH-1 downto 0) := (others => '0');
signal lsig_ld_offset : std_logic := '0';
signal lsig_incr_offset : std_logic := '0';
signal lsig_offset_cntr_eq_max : std_logic := '0';
signal lsig_fifo_data_out_wide : lsig_data_slice_type;
signal lsig_fifo_tkeep_out_wide : lsig_tkeep_slice_type;
signal lsig_mux_sel : integer range 0 to MMAP2STRM_WIDTH_RATO-1;
signal lsig_data_mux_out : std_logic_vector(DATA_SLICE_WIDTH-1 downto 0) ;
signal lsig_tkeep_mux_out : std_logic_vector(TKEEP_SLICE_WIDTH-1 downto 0);
signal lsig_tlast_out : std_logic := '0';
signal lsig_dre_flush_out : std_logic := '0';
signal lsig_this_fifo_wrd_done : std_logic := '0';
signal lsig_cmd_loaded : std_logic := '0';
signal lsig_cmd_cmplt_dbeat : std_logic := '0';
signal lsig_cmd_cmplt : std_logic := '0';
signal lsig_next_slice_tkeep_0 : std_logic := '0';
begin
sig_sf2sout_tvalid <= sig_data_fifo_dvalid and
lsig_cmd_loaded ;
sig_sf2sout_tdata <= lsig_data_mux_out ;
sig_sf2sout_tkeep <= lsig_tkeep_mux_out(TKEEP_SLICE_WIDTH-1 downto 0);
sig_sf2sout_tlast <= lsig_tlast_out ;
sig_sf2dre_flush <= lsig_dre_flush_out ;
-- Control for reading the Data FIFO
sig_pop_data_fifo <= lsig_this_fifo_wrd_done and
lsig_cmd_loaded and
sig_sout2sf_tready and
sig_data_fifo_dvalid;
-- Control for reading the Command/Offset FIFO
sig_get_cntl_fifo_data <= lsig_ld_offset;
-- Control for loading the DRE Control Reg
sig_ld_dre_cntl_reg <= lsig_ld_offset ;
lsig_next_slice_tkeep_0 <= lsig_fifo_tkeep_out_wide(lsig_mux_sel+1)(0);
-- Detirmine if a Command Complete condition exists
lsig_cmd_cmplt <= '1'
when (sig_dfifo_cmd_cmplt_out = '1' and
lsig_next_slice_tkeep_0 = '0')
Else '0';
-- Detirmine if a TLAST condition exists
-- From the RDC via the Data FIFO
lsig_tlast_out <= '1'
when (sig_dfifo_tlast_out = '1' and
lsig_next_slice_tkeep_0 = '0')
Else '0';
-- Detimine if a DRE Flush condition exists
-- From the RDC via the Data FIFO
lsig_dre_flush_out <= '1'
when (sig_dfifo_dre_flush_out = '1' and
lsig_next_slice_tkeep_0 = '0')
Else '0';
lsig_cmd_cmplt_dbeat <= lsig_cmd_cmplt and
lsig_cmd_loaded and
sig_data_fifo_dvalid and
sig_sout2sf_tready ;
-- Check to see if the FIFO output word is finished. This occurs
-- when the offset counter is at max value or the tlast from the
-- fifo is set and the LS TKEED of the next MS Slice is zero.
lsig_this_fifo_wrd_done <= '1'
When (lsig_offset_cntr_eq_max = '1' or
(lsig_cmd_cmplt_dbeat = '1' and
lsig_next_slice_tkeep_0 = '0'))
Else '0';
-- Generate the control that loads the starting address
-- offset for the next input packet
lsig_ld_offset <= (sig_cntl_fifo_has_data and -- startup or gap case
not(lsig_cmd_loaded)) or
(sig_cntl_fifo_has_data and -- back to back commands
lsig_cmd_cmplt_dbeat);
-- Generate the control for incrementing the offset counter
lsig_incr_offset <= sig_good_sout_strm_dbeat;
-- Check to see if the offset counter has reached its max
-- value
lsig_offset_cntr_eq_max <= '1'
when (lsig_0ffset_cntr = OFFSET_CNT_MAX)
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_CMD_LOADED
--
-- Process Description:
-- Implements the flop indicating a command from the cmd fifo
-- has been loaded into the unpacker control logic.
--
-------------------------------------------------------------
IMP_CMD_LOADED : process (aclk)
begin
if (aclk'event and aclk = '1') then
if (reset = '1') then
lsig_cmd_loaded <= '0';
Elsif (lsig_ld_offset = '1' ) Then
lsig_cmd_loaded <= '1';
elsif (sig_cntl_fifo_has_data = '0' and -- No more commands queued
lsig_cmd_cmplt_dbeat = '1') then
lsig_cmd_loaded <= '0';
else
null; -- Hold Current State
end if;
end if;
end process IMP_CMD_LOADED;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_OFFSET_CNTR
--
-- Process Description:
-- Implements the address offset counter that is used to
-- generate the data and tkeep mux selects.
-- Note that the counter has to be loaded with the starting
-- offset plus one to sync up with the data input.
-------------------------------------------------------------
IMP_OFFSET_CNTR : process (aclk)
begin
if (aclk'event and aclk = '1') then
if (reset = '1') then
lsig_0ffset_cntr <= (others => '0');
Elsif (lsig_ld_offset = '1') Then
lsig_0ffset_cntr <= UNSIGNED(sig_curr_strt_offset_reg);
elsif (lsig_incr_offset = '1') then
lsig_0ffset_cntr <= lsig_0ffset_cntr + OFFSET_CNT_ONE;
else
null; -- Hold Current State
end if;
end if;
end process IMP_OFFSET_CNTR;
------------------------------------------------------------
-- For Generate
--
-- Label: DO_DATA_CONVERTER
--
-- For Generate Description:
-- This ForGen converts the FIFO output data and tkeep from a single
-- std logic vector type to a vector of slices.
--
------------------------------------------------------------
DO_DATA_CONVERTER : for slice_index in 1 to MMAP2STRM_WIDTH_RATO generate
begin
lsig_fifo_data_out_wide(slice_index-1) <=
sig_dfifo_data_out((slice_index*DATA_SLICE_WIDTH)-1 downto
(slice_index-1)*DATA_SLICE_WIDTH);
lsig_fifo_tkeep_out_wide(slice_index-1) <=
sig_dfifo_tkeep_out((slice_index*TKEEP_SLICE_WIDTH)-1 downto
(slice_index-1)*TKEEP_SLICE_WIDTH);
end generate DO_DATA_CONVERTER;
-- Assign the extra tkeep slice to all zeros to allow for detection
-- of the data word done when the ls tkeep bit of the next tkeep
-- slice is zero and the offset count is pointing to the last slice
-- position.
lsig_fifo_tkeep_out_wide(MMAP2STRM_WIDTH_RATO) <= (others => '0');
-- Mux the appropriate data and tkeep slice to the stream output
lsig_mux_sel <= TO_INTEGER(lsig_0ffset_cntr);
lsig_data_mux_out <= lsig_fifo_data_out_wide(lsig_mux_sel) ;
lsig_tkeep_mux_out(TKEEP_SLICE_WIDTH-1 downto 0) <= lsig_fifo_tkeep_out_wide(lsig_mux_sel);
end generate INCLUDE_UNPACKING;
------------------------------------------------------------
-- If Generate
--
-- Label: OMIT_DRE_CNTL
--
-- If Generate Description:
-- This IfGen is used to omit the DRE control logic and
-- minimize the Control FIFO when MM2S DRE is not included
-- in the MM2S.
--
------------------------------------------------------------
OMIT_DRE_CNTL : if (C_DRE_IS_USED = 0) generate
-- Constant Declarations ------------------------------------------------------------------
Constant USE_SYNC_FIFO : integer := 0;
Constant SRL_FIFO_PRIM : integer := 2;
Constant TAG_WIDTH : integer := C_TAG_WIDTH;
Constant DRR_WIDTH : integer := 1;
Constant EOF_WIDTH : integer := 1;
Constant CALC_ERR_WIDTH : integer := 1;
Constant SF_OFFSET_WIDTH : integer := C_STRT_SF_OFFSET_WIDTH;
Constant SF_OFFSET_FIFO_DEPTH : integer := funct_size_drecntl_fifo(C_DRE_CNTL_FIFO_DEPTH,
C_MAX_BURST_LEN);
Constant SF_OFFSET_FIFO_WIDTH : Integer := TAG_WIDTH + -- Tag field
DRR_WIDTH + -- DRE Re-alignment Request Flag Field
EOF_WIDTH + -- EOF flag field
CALC_ERR_WIDTH + -- Calc error flag
SF_OFFSET_WIDTH; -- Store and Forward Offset
Constant TAG_STRT_INDEX : integer := 0;
Constant DRR_STRT_INDEX : integer := TAG_STRT_INDEX + TAG_WIDTH;
Constant EOF_STRT_INDEX : integer := DRR_STRT_INDEX + DRR_WIDTH;
Constant CALC_ERR_STRT_INDEX : integer := EOF_STRT_INDEX + EOF_WIDTH;
Constant SF_OFFSET_STRT_INDEX : integer := CALC_ERR_STRT_INDEX+CALC_ERR_WIDTH;
-- Signal Declarations --------------------------------------------------------------------
signal sig_offset_fifo_data_in : std_logic_vector(SF_OFFSET_FIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_offset_fifo_data_out : std_logic_vector(SF_OFFSET_FIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_offset_fifo_wr_valid : std_logic := '0';
signal sig_offset_fifo_wr_ready : std_logic := '0';
signal sig_offset_fifo_rd_valid : std_logic := '0';
signal sig_offset_fifo_rd_ready : std_logic := '0';
begin
-- PCC DRE Command interface handshake
dre2mstr_cmd_ready <= sig_offset_fifo_wr_ready ;
sig_offset_fifo_wr_valid <= mstr2dre_cmd_valid ;
-- No DRE so no controls
sf2dre_new_align <= '0';
sf2dre_use_autodest <= '0';
sf2dre_src_align <= (others => '0');
sf2dre_dest_align <= (others => '0');
sf2dre_flush <= '0';
-- No DRE so no alignment values
sig_curr_src_align_reg <= (others => '0');
sig_curr_dest_align_reg <= (others => '0');
-- Format the input data word for the Offset FIFO Queue
sig_offset_fifo_data_in <= mstr2dre_strt_offset & -- MS field
mstr2dre_calc_error &
mstr2dre_eof &
mstr2dre_drr &
mstr2dre_tag; -- LS Field
sig_cntl_fifo_has_data <= sig_offset_fifo_rd_valid ;
sig_offset_fifo_rd_ready <= sig_get_cntl_fifo_data ;
-- Rip the output fifo data word
sig_curr_tag_reg <= sig_offset_fifo_data_out((TAG_STRT_INDEX+TAG_WIDTH)-1 downto TAG_STRT_INDEX);
sig_curr_drr_reg <= sig_offset_fifo_data_out(DRR_STRT_INDEX);
sig_curr_eof_reg <= sig_offset_fifo_data_out(EOF_STRT_INDEX);
sig_curr_calc_error_reg <= sig_offset_fifo_data_out(CALC_ERR_STRT_INDEX);
sig_curr_strt_offset_reg <= sig_offset_fifo_data_out((SF_OFFSET_STRT_INDEX+SF_OFFSET_WIDTH)-1 downto
SF_OFFSET_STRT_INDEX);
------------------------------------------------------------
-- Instance: I_DRE_CNTL_FIFO
--
-- Description:
-- Instance for the Offset Control FIFO. This is still needed
-- by the unpacker logic to get the starting offset at the
-- begining of an input packet coming out of the Store and
-- Forward data FIFO.
--
------------------------------------------------------------
I_DRE_CNTL_FIFO : entity axi_datamover_v5_1_9.axi_datamover_fifo
generic map (
C_DWIDTH => SF_OFFSET_FIFO_WIDTH ,
C_DEPTH => SF_OFFSET_FIFO_DEPTH ,
C_IS_ASYNC => USE_SYNC_FIFO ,
C_PRIM_TYPE => SRL_FIFO_PRIM ,
C_FAMILY => C_FAMILY
)
port map (
-- Write Clock and reset
fifo_wr_reset => reset ,
fifo_wr_clk => aclk ,
-- Write Side
fifo_wr_tvalid => sig_offset_fifo_wr_valid ,
fifo_wr_tready => sig_offset_fifo_wr_ready ,
fifo_wr_tdata => sig_offset_fifo_data_in ,
fifo_wr_full => open ,
-- Read Clock and reset
fifo_async_rd_reset => aclk ,
fifo_async_rd_clk => reset ,
-- Read Side
fifo_rd_tvalid => sig_offset_fifo_rd_valid ,
fifo_rd_tready => sig_offset_fifo_rd_ready ,
fifo_rd_tdata => sig_offset_fifo_data_out ,
fifo_rd_empty => open
);
end generate OMIT_DRE_CNTL;
------------------------------------------------------------
-- If Generate
--
-- Label: INCLUDE_DRE_CNTL
--
-- If Generate Description:
-- This IfGen is used to include the DRE control logic and
-- Control FIFO when MM2S DRE is included in the MM2S.
--
--
------------------------------------------------------------
INCLUDE_DRE_CNTL : if (C_DRE_IS_USED = 1) generate
-- Constant Declarations
Constant DRECNTL_FIFO_DEPTH : integer := funct_size_drecntl_fifo(C_DRE_CNTL_FIFO_DEPTH,
C_MAX_BURST_LEN);
Constant DRECNTL_FIFO_WIDTH : Integer := TAG_WIDTH + -- Tag field
SRC_ALIGN_WIDTH + -- Source align field width
DEST_ALIGN_WIDTH + -- Dest align field width
DRR_WIDTH + -- DRE Re-alignment Request Flag Field
EOF_WIDTH + -- EOF flag field
CALC_ERR_WIDTH + -- Calc error flag
SF_OFFSET_WIDTH; -- Store and Forward Offset
Constant TAG_STRT_INDEX : integer := 0;
Constant SRC_ALIGN_STRT_INDEX : integer := TAG_STRT_INDEX + TAG_WIDTH;
Constant DEST_ALIGN_STRT_INDEX : integer := SRC_ALIGN_STRT_INDEX + SRC_ALIGN_WIDTH;
Constant DRR_STRT_INDEX : integer := DEST_ALIGN_STRT_INDEX + DEST_ALIGN_WIDTH;
Constant EOF_STRT_INDEX : integer := DRR_STRT_INDEX + DRR_WIDTH;
Constant CALC_ERR_STRT_INDEX : integer := EOF_STRT_INDEX + EOF_WIDTH;
Constant SF_OFFSET_STRT_INDEX : integer := CALC_ERR_STRT_INDEX+CALC_ERR_WIDTH;
signal sig_cmd_fifo_data_in : std_logic_vector(DRECNTL_FIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd_fifo_data_out : std_logic_vector(DRECNTL_FIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_fifo_wr_cmd_valid : std_logic := '0';
signal sig_fifo_wr_cmd_ready : std_logic := '0';
signal sig_fifo_rd_cmd_valid : std_logic := '0';
signal sig_fifo_rd_cmd_ready : std_logic := '0';
signal sig_dre_align_ready : std_logic := '0';
signal sig_dre_align_valid_reg : std_logic := '0';
signal sig_dre_use_autodest_reg : std_logic := '0';
signal sig_dre_src_align_reg : std_logic_vector(SRC_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_dre_dest_align_reg : std_logic_vector(DEST_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_dre_flush_reg : std_logic := '0';
begin
-- Assign the DRE Control Outputs
sf2dre_new_align <= sig_dre_align_valid_reg;
sf2dre_use_autodest <= sig_dre_use_autodest_reg;
sf2dre_src_align <= sig_dre_src_align_reg;
sf2dre_dest_align <= sig_dre_dest_align_reg;
sf2dre_flush <= sig_sf2dre_flush; -- from RDC via data FIFO
-- PCC DRE Command interface handshake
dre2mstr_cmd_ready <= sig_fifo_wr_cmd_ready;
sig_fifo_wr_cmd_valid <= mstr2dre_cmd_valid ;
-- Format the input data word for the DRE Control FIFO Queue
sig_cmd_fifo_data_in <= mstr2dre_strt_offset &
mstr2dre_calc_error &
mstr2dre_eof &
mstr2dre_drr &
mstr2dre_dre_dest_align &
mstr2dre_dre_src_align &
mstr2dre_tag;
-- Formulate the DRE Control FIFO Read signaling
sig_cntl_fifo_has_data <= sig_fifo_rd_cmd_valid ;
sig_fifo_rd_cmd_ready <= sig_get_cntl_fifo_data ;
-- Rip the output fifo data word
sig_curr_tag_reg <= sig_cmd_fifo_data_out((TAG_STRT_INDEX+TAG_WIDTH)-1 downto TAG_STRT_INDEX);
sig_curr_src_align_reg <= sig_cmd_fifo_data_out((SRC_ALIGN_STRT_INDEX+SRC_ALIGN_WIDTH)-1 downto
SRC_ALIGN_STRT_INDEX);
sig_curr_dest_align_reg <= sig_cmd_fifo_data_out((DEST_ALIGN_STRT_INDEX+DEST_ALIGN_WIDTH)-1 downto
DEST_ALIGN_STRT_INDEX);
sig_curr_drr_reg <= sig_cmd_fifo_data_out(DRR_STRT_INDEX);
sig_curr_eof_reg <= sig_cmd_fifo_data_out(EOF_STRT_INDEX);
sig_curr_calc_error_reg <= sig_cmd_fifo_data_out(CALC_ERR_STRT_INDEX);
sig_curr_strt_offset_reg <= sig_cmd_fifo_data_out((SF_OFFSET_STRT_INDEX+SF_OFFSET_WIDTH)-1 downto
SF_OFFSET_STRT_INDEX);
------------------------------------------------------------
-- Instance: I_DRE_CNTL_FIFO
--
-- Description:
-- Instance for the DRE Control FIFO
--
------------------------------------------------------------
I_DRE_CNTL_FIFO : entity axi_datamover_v5_1_9.axi_datamover_fifo
generic map (
C_DWIDTH => DRECNTL_FIFO_WIDTH ,
C_DEPTH => DRECNTL_FIFO_DEPTH ,
C_IS_ASYNC => USE_SYNC_FIFO ,
C_PRIM_TYPE => SRL_FIFO_PRIM ,
C_FAMILY => C_FAMILY
)
port map (
-- Write Clock and reset
fifo_wr_reset => reset ,
fifo_wr_clk => aclk ,
-- Write Side
fifo_wr_tvalid => sig_fifo_wr_cmd_valid ,
fifo_wr_tready => sig_fifo_wr_cmd_ready ,
fifo_wr_tdata => sig_cmd_fifo_data_in ,
fifo_wr_full => open ,
-- Read Clock and reset
fifo_async_rd_reset => aclk ,
fifo_async_rd_clk => reset ,
-- Read Side
fifo_rd_tvalid => sig_fifo_rd_cmd_valid ,
fifo_rd_tready => sig_fifo_rd_cmd_ready ,
fifo_rd_tdata => sig_cmd_fifo_data_out ,
fifo_rd_empty => open
);
-------------------------------------------------------------------------
-- DRE Control Register
-------------------------------------------------------------------------
-- The DRE will auto-flush on a received TLAST so a commanded Flush
-- is not needed.
sig_dre_flush_reg <= '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_CNTL_REG
--
-- Process Description:
-- Implements the DRE alignment Output Register.
--
-------------------------------------------------------------
IMP_CNTL_REG : process (aclk)
begin
if (aclk'event and aclk = '1') then
if (reset = '1') then
sig_dre_use_autodest_reg <= '0' ;
sig_dre_src_align_reg <= (others => '0') ;
sig_dre_dest_align_reg <= (others => '0') ;
Elsif (sig_ld_dre_cntl_reg = '1' ) Then
sig_dre_use_autodest_reg <= not(sig_curr_drr_reg) ;
sig_dre_src_align_reg <= sig_curr_src_align_reg ;
sig_dre_dest_align_reg <= sig_curr_dest_align_reg ;
Elsif (sig_good_sout_strm_dbeat = '1') Then
sig_dre_use_autodest_reg <= '0' ;
sig_dre_src_align_reg <= (others => '0') ;
sig_dre_dest_align_reg <= (others => '0') ;
else
null; -- Hold Current State
end if;
end if;
end process IMP_CNTL_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_DRE_CNTL_VALID_REG
--
-- Process Description:
-- Implements the DRE Alignment valid Register.
--
-------------------------------------------------------------
IMP_DRE_CNTL_VALID_REG : process (aclk)
begin
if (aclk'event and aclk = '1') then
if (reset = '1') then
sig_dre_align_valid_reg <= '0' ;
Elsif (sig_ld_dre_cntl_reg = '1' ) Then
sig_dre_align_valid_reg <= '1' ;
Elsif (sig_good_sout_strm_dbeat = '1') Then
sig_dre_align_valid_reg <= '0' ;
else
null; -- Hold Current State
end if;
end if;
end process IMP_DRE_CNTL_VALID_REG;
end generate INCLUDE_DRE_CNTL;
----------------------------------------------------------------
-- Token Counter Logic
-- Predicting fifo space availability at some point in the
-- future is based on managing a virtual pool of transfer tokens.
-- A token represents 1 max length burst worth of space in the
-- Data FIFO.
----------------------------------------------------------------
-- calculate how many tokens are commited to pending transfers
sig_tokens_commited <= TOKEN_CNT_MAX - sig_token_cntr;
-- Decrement the token counter when a token is
-- borrowed
sig_decr_token_cntr <= '1'
when (sig_rd_addr_posted = '1' and
sig_token_eq_zero = '0')
else '0';
-- Increment the token counter when a
-- token is returned.
sig_incr_token_cntr <= '1'
when (sig_rd_xfer_cmplt = '1' and
sig_token_eq_max = '0')
else '0';
-- Detect when the xfer token count is at max value
sig_token_eq_max <= '1'
when (sig_token_cntr = TOKEN_CNT_MAX)
Else '0';
-- Detect when the xfer token count is at one
sig_token_eq_one <= '1'
when (sig_token_cntr = TOKEN_CNT_ONE)
Else '0';
-- Detect when the xfer token count is at zero
sig_token_eq_zero <= '1'
when (sig_token_cntr = TOKEN_CNT_ZERO)
Else '0';
-- Look ahead to see if the xfer token pool is going empty
sig_taking_last_token <= '1'
When (sig_token_eq_one = '1' and
sig_rd_addr_posted = '1')
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_TOKEN_CNTR
--
-- Process Description:
-- Implements the Token counter
--
-------------------------------------------------------------
IMP_TOKEN_CNTR : process (aclk)
begin
if (aclk'event and aclk = '1') then
if (reset = '1' ) then
sig_token_cntr <= TOKEN_CNT_MAX;
elsif (sig_incr_token_cntr = '1' and
sig_decr_token_cntr = '0') then
sig_token_cntr <= sig_token_cntr + TOKEN_CNT_ONE;
elsif (sig_incr_token_cntr = '0' and
sig_decr_token_cntr = '1') then
sig_token_cntr <= sig_token_cntr - TOKEN_CNT_ONE;
else
null; -- hold current value
end if;
end if;
end process IMP_TOKEN_CNTR;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_TOKEN_AVAIL_FLAG
--
-- Process Description:
-- Implements the flag indicating that the AXI Read Master
-- can post a read address request on the AXI4 bus.
--
-- Read address posting can occur if:
--
-- - The write side LEN fifo is not empty.
-- - The commited plus actual Data FIFO space is less than
-- the stall threshold (a max length read burst can fit
-- in the data FIFO without overflow).
-- - The max allowed commited read count has not been reached.
--
-- The flag is cleared after each address has been posted to
-- ensure a second unauthorized post does not occur.
-------------------------------------------------------------
IMP_TOKEN_AVAIL_FLAG : process (aclk)
begin
if (aclk'event and aclk = '1') then
if (reset = '1' or
sig_rd_addr_posted = '1') then
sig_ok_to_post_rd_addr <= '0';
else
sig_ok_to_post_rd_addr <= not(sig_stall_rd_addr_posts) and -- the commited Data FIFO space is approaching full
not(sig_token_eq_zero) and -- max allowed pending reads has not been reached
not(sig_taking_last_token); -- the max allowed pending reads is about to be reached
end if;
end if;
end process IMP_TOKEN_AVAIL_FLAG;
----------------------------------------------------------------
-- Data FIFO Logic ------------------------------------------
----------------------------------------------------------------
GEN_MM2S_TKEEP_ENABLE3 : if C_ENABLE_MM2S_TKEEP = 1 generate
begin
-- FIFO Output ripping to components
sig_dfifo_data_out <= sig_data_fifo_data_out(DATA_OUT_MSB_INDEX downto
DATA_OUT_LSB_INDEX);
sig_dfifo_tkeep_out <= sig_data_fifo_data_out(TKEEP_OUT_MSB_INDEX downto
TKEEP_OUT_LSB_INDEX);
sig_dfifo_tlast_out <= sig_data_fifo_data_out(TLAST_OUT_INDEX) ;
sig_dfifo_cmd_cmplt_out <= sig_data_fifo_data_out(CMPLT_OUT_INDEX) ;
sig_dfifo_dre_flush_out <= sig_data_fifo_data_out(DRE_FLUSH_OUT_INDEX) ;
end generate GEN_MM2S_TKEEP_ENABLE3;
GEN_MM2S_TKEEP_DISABLE3 : if C_ENABLE_MM2S_TKEEP = 0 generate
begin
-- FIFO Output ripping to components
sig_dfifo_data_out <= sig_data_fifo_data_out(DATA_OUT_MSB_INDEX downto
DATA_OUT_LSB_INDEX);
sig_dfifo_tkeep_out <= (others => '1');
sig_dfifo_tlast_out <= sig_data_fifo_data_out(TLAST_OUT_INDEX) ;
sig_dfifo_cmd_cmplt_out <= sig_data_fifo_data_out(CMPLT_OUT_INDEX) ;
sig_dfifo_dre_flush_out <= sig_data_fifo_data_out(DRE_FLUSH_OUT_INDEX) ;
end generate GEN_MM2S_TKEEP_DISABLE3;
-- Stall Threshold calculations
sig_fifo_wr_cnt_unsgnd <= UNSIGNED(sig_data_fifo_wr_cnt);
sig_wrcnt_mblen_slice <= sig_fifo_wr_cnt_unsgnd(DATA_FIFO_CNT_WIDTH-1 downto
DF_WRCNT_RIP_LS_INDEX);
sig_commit_plus_actual <= RESIZE(sig_tokens_commited, THRESH_COMPARE_WIDTH) +
RESIZE(sig_wrcnt_mblen_slice, THRESH_COMPARE_WIDTH);
-- Compare the commited read space plus the actual used space against the
-- stall threshold. Assert the read address posting stall flag if the
-- threshold is met or exceeded.
sig_stall_rd_addr_posts <= '1'
when (sig_commit_plus_actual > RD_ADDR_POST_STALL_THRESH_US)
Else '0';
-- FIFO Rd/WR Controls
sig_push_data_fifo <= sig_good_sin_strm_dbeat;
-- sig_pop_data_fifo <= sig_sout2sf_tready and
-- sig_data_fifo_dvalid;
GEN_MM2S_TKEEP_ENABLE2 : if C_ENABLE_MM2S_TKEEP = 1 generate
begin
-- Concatonate the Stream inputs into the single FIFO data in value
sig_data_fifo_data_in <= data2sf_dre_flush & -- ms Field
data2sf_cmd_cmplt &
sin2sf_tlast &
sin2sf_tkeep &
sin2sf_tdata; -- ls field
end generate GEN_MM2S_TKEEP_ENABLE2;
GEN_MM2S_TKEEP_DISABLE2 : if C_ENABLE_MM2S_TKEEP = 0 generate
begin
-- Concatonate the Stream inputs into the single FIFO data in value
sig_data_fifo_data_in <= data2sf_dre_flush & -- ms Field
data2sf_cmd_cmplt &
sin2sf_tlast &
--sin2sf_tkeep &
sin2sf_tdata; -- ls field
end generate GEN_MM2S_TKEEP_DISABLE2;
------------------------------------------------------------
-- Instance: I_DATA_FIFO
--
-- Description:
-- Implements the Store and Forward data FIFO (synchronous)
--
------------------------------------------------------------
I_DATA_FIFO : entity axi_datamover_v5_1_9.axi_datamover_sfifo_autord
generic map (
C_DWIDTH => DATA_FIFO_WIDTH ,
C_DEPTH => DATA_FIFO_DEPTH ,
C_DATA_CNT_WIDTH => DATA_FIFO_CNT_WIDTH ,
C_NEED_ALMOST_EMPTY => NOT_NEEDED ,
C_NEED_ALMOST_FULL => NOT_NEEDED ,
C_USE_BLKMEM => BLK_MEM_FIFO ,
C_FAMILY => C_FAMILY
)
port map (
-- Inputs
SFIFO_Sinit => reset ,
SFIFO_Clk => aclk ,
SFIFO_Wr_en => sig_push_data_fifo ,
SFIFO_Din => sig_data_fifo_data_in ,
SFIFO_Rd_en => sig_pop_data_fifo ,
SFIFO_Clr_Rd_Data_Valid => LOGIC_LOW ,
-- Outputs
SFIFO_DValid => sig_data_fifo_dvalid ,
SFIFO_Dout => sig_data_fifo_data_out ,
SFIFO_Full => sig_data_fifo_full ,
SFIFO_Empty => open ,
SFIFO_Almost_full => open ,
SFIFO_Almost_empty => open ,
SFIFO_Rd_count => open ,
SFIFO_Rd_count_minus1 => open ,
SFIFO_Wr_count => sig_data_fifo_wr_cnt ,
SFIFO_Rd_ack => open
);
end implementation;
|
-------------------------------------------------------------------------------
-- axi_datamover_rd_sf.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_rd_sf.vhd
--
-- Description:
-- This file implements the AXI DataMover Read (MM2S) Store and Forward module.
-- The design utilizes the AXI DataMover's new address pipelining
-- control function. The design is such that predictive address
-- pipelining can be supported on the AXI Read Bus without over-commiting
-- the internal Data FIFO and potentially throttling the Read Data Channel
-- if the Data FIFO goes full.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library lib_pkg_v1_0_2;
use lib_pkg_v1_0_2.lib_pkg.all;
use lib_pkg_v1_0_2.lib_pkg.clog2;
library axi_datamover_v5_1_9;
use axi_datamover_v5_1_9.axi_datamover_sfifo_autord;
use axi_datamover_v5_1_9.axi_datamover_fifo;
-------------------------------------------------------------------------------
entity axi_datamover_rd_sf is
generic (
C_SF_FIFO_DEPTH : Integer range 128 to 8192 := 512;
-- Sets the desired depth of the internal Data FIFO.
C_MAX_BURST_LEN : Integer range 2 to 256 := 16;
-- Indicates the max burst length being used by the external
-- AXI4 Master for each AXI4 transfer request.
C_DRE_IS_USED : Integer range 0 to 1 := 0;
-- Indicates if the external Master is utilizing a DRE on
-- the stream input to this module.
C_DRE_CNTL_FIFO_DEPTH : Integer range 1 to 32 := 1;
-- Specifies the depth of the internal dre control queue fifo
C_DRE_ALIGN_WIDTH : Integer range 1 to 3 := 2;
-- Sets the width of the DRE alignment control ports
C_MMAP_DWIDTH : Integer range 32 to 1024 := 64;
-- Sets the AXI4 Memory Mapped Bus Data Width
C_STREAM_DWIDTH : Integer range 8 to 1024 := 32;
-- Sets the Stream Data Width for the Input and Output
-- Data streams.
C_STRT_SF_OFFSET_WIDTH : Integer range 1 to 7 := 2;
-- Sets the bit width of the starting address offset port
-- This should be set to log2(C_MMAP_DWIDTH/C_STREAM_DWIDTH)
C_ENABLE_MM2S_TKEEP : integer range 0 to 1 := 1;
C_TAG_WIDTH : Integer range 1 to 8 := 4;
-- Indicates the width of the Tag field of the input DRE command
C_FAMILY : String := "virtex7"
-- Indicates the target FPGA Family.
);
port (
-- Clock and Reset inputs --------------------------------------------
--
aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- Reset input --
reset : in std_logic; --
-- Reset used for the internal syncronization logic --
----------------------------------------------------------------------
-- DataMover Read Side Address Pipelining Control Interface ----------
--
ok_to_post_rd_addr : Out Std_logic; --
-- Indicates that the transfer token pool has at least --
-- one token available to borrow --
--
rd_addr_posted : In std_logic; --
-- Indication that a read address has been posted to AXI4 --
--
rd_xfer_cmplt : In std_logic; --
-- Indicates that the Datamover has completed a Read Data --
-- transfer on the AXI4 --
----------------------------------------------------------------------
-- Read Side Stream In from DataMover MM2S Read Data Controller ----------------------
--
sf2sin_tready : Out Std_logic; --
-- DRE Stream READY input --
--
sin2sf_tvalid : In std_logic; --
-- DRE Stream VALID Output --
--
sin2sf_tdata : In std_logic_vector(C_MMAP_DWIDTH-1 downto 0); --
-- DRE Stream DATA input --
--
sin2sf_tkeep : In std_logic_vector((C_MMAP_DWIDTH/8)-1 downto 0); --
-- DRE Stream STRB input --
--
sin2sf_tlast : In std_logic; --
-- DRE Xfer LAST input --
--------------------------------------------------------------------------------------
-- RDC Store and Forward Supplimental Controls ---------------------
-- These are time aligned and qualified with the RDC Stream Input --
--
data2sf_cmd_cmplt : In std_logic; --
data2sf_dre_flush : In std_logic; --
--------------------------------------------------------------------
-- DRE Control Interface from the Command Calculator -----------------------------
--
dre2mstr_cmd_ready : Out std_logic ; --
-- Indication from the DRE that the command is being --
-- accepted from the Command Calculator --
--
mstr2dre_cmd_valid : In std_logic; --
-- The next command valid indication to the DRE --
-- from the Command Calculator --
--
mstr2dre_tag : In std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The next command tag --
--
mstr2dre_dre_src_align : In std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0); --
-- The source (input) alignment for the DRE --
--
mstr2dre_dre_dest_align : In std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0); --
-- The destinstion (output) alignment for the DRE --
--
-- mstr2dre_btt : In std_logic_vector(C_BTT_USED-1 downto 0); --
-- -- The bytes to transfer value for the input command --
--
mstr2dre_drr : In std_logic; --
-- The starting tranfer of a sequence of transfers --
--
mstr2dre_eof : In std_logic; --
-- The endiing tranfer of a sequence of transfers --
--
-- mstr2dre_cmd_cmplt : In std_logic; --
-- -- The last tranfer command of a sequence of transfers --
-- -- spawned from a single parent command --
--
mstr2dre_calc_error : In std_logic; --
-- Indication if the next command in the calculation pipe --
-- has a calculation error --
--
mstr2dre_strt_offset : In std_logic_vector(C_STRT_SF_OFFSET_WIDTH-1 downto 0);--
-- Outputs the starting offset of a transfer. This is used with Store --
-- and Forward Packer/Unpacker logic --
-----------------------------------------------------------------------------------
-- MM2S DRE Control -------------------------------------------------------------
--
sf2dre_new_align : Out std_logic; --
-- Active high signal indicating new DRE aligment required --
--
sf2dre_use_autodest : Out std_logic; --
-- Active high signal indicating to the DRE to use an auto- --
-- calculated desination alignment based on the last transfer --
--
sf2dre_src_align : Out std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0); --
-- Bit field indicating the byte lane of the first valid data byte --
-- being sent to the DRE --
--
sf2dre_dest_align : Out std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0); --
-- Bit field indicating the desired byte lane of the first valid data byte --
-- to be output by the DRE --
--
sf2dre_flush : Out std_logic; --
-- Active high signal indicating to the DRE to flush the current --
-- contents to the output register in preparation of a new alignment --
-- that will be comming on the next transfer input --
---------------------------------------------------------------------------------
-- Stream Out -----------------------------------------------------------------------
--
sout2sf_tready : In std_logic; --
-- Write READY input from the Stream Master --
--
sf2sout_tvalid : Out std_logic; --
-- Write VALID output to the Stream Master --
--
sf2sout_tdata : Out std_logic_vector(C_STREAM_DWIDTH-1 downto 0); --
-- Write DATA output to the Stream Master --
--
sf2sout_tkeep : Out std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- Write DATA output to the Stream Master --
--
sf2sout_tlast : Out std_logic --
-- Write LAST output to the Stream Master --
--------------------------------------------------------------------------------------
);
end entity axi_datamover_rd_sf;
architecture implementation of axi_datamover_rd_sf is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Functions ---------------------------------------------------------------------------
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_fifo_cnt_width
--
-- Function Description:
-- simple function to set the width of the data fifo read
-- and write count outputs.
-------------------------------------------------------------------
function funct_get_fifo_cnt_width (fifo_depth : integer)
return integer is
Variable temp_width : integer := 8;
begin
if (fifo_depth = 1) then
temp_width := 1;
elsif (fifo_depth = 2) then
temp_width := 2;
elsif (fifo_depth <= 4) then
temp_width := 3;
elsif (fifo_depth <= 8) then
temp_width := 4;
elsif (fifo_depth <= 16) then
temp_width := 5;
elsif (fifo_depth <= 32) then
temp_width := 6;
elsif (fifo_depth <= 64) then
temp_width := 7;
elsif (fifo_depth <= 128) then
temp_width := 8;
elsif (fifo_depth <= 256) then
temp_width := 9;
elsif (fifo_depth <= 512) then
temp_width := 10;
elsif (fifo_depth <= 1024) then
temp_width := 11;
elsif (fifo_depth <= 2048) then
temp_width := 12;
elsif (fifo_depth <= 4096) then
temp_width := 13;
else -- assume 8192 depth
temp_width := 14;
end if;
Return (temp_width);
end function funct_get_fifo_cnt_width;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_wrcnt_lsrip
--
-- Function Description:
-- Calculates the ls index of the upper slice of the data fifo
-- write count needed to repesent one max burst worth of data
-- present in the fifo.
--
-------------------------------------------------------------------
function funct_get_wrcnt_lsrip (max_burst_dbeats : integer) return integer is
Variable temp_ls_index : Integer := 0;
begin
if (max_burst_dbeats <= 2) then
temp_ls_index := 1;
elsif (max_burst_dbeats <= 4) then
temp_ls_index := 2;
elsif (max_burst_dbeats <= 8) then
temp_ls_index := 3;
elsif (max_burst_dbeats <= 16) then
temp_ls_index := 4;
elsif (max_burst_dbeats <= 32) then
temp_ls_index := 5;
elsif (max_burst_dbeats <= 64) then
temp_ls_index := 6;
elsif (max_burst_dbeats <= 128) then
temp_ls_index := 7;
else
temp_ls_index := 8;
end if;
Return (temp_ls_index);
end function funct_get_wrcnt_lsrip;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_stall_thresh
--
-- Function Description:
-- Calculates the Stall threshold for the input side of the Data
-- FIFO. If DRE is being used by the DataMover, then the threshold
-- must be reduced to account for the potential of an extra write
-- databeat per request (DRE alignment dependent).
--
-------------------------------------------------------------------
function funct_get_stall_thresh (dre_is_used : integer;
max_xfer_length : integer;
data_fifo_depth : integer;
pipeline_delay_clks : integer;
fifo_settling_clks : integer) return integer is
Constant DRE_PIPE_DELAY : integer := 2; -- clks
Variable var_num_max_xfers_allowed : Integer := 0;
Variable var_dre_dbeat_overhead : Integer := 0;
Variable var_delay_fudge_factor : Integer := 0;
Variable var_thresh_headroom : Integer := 0;
Variable var_stall_thresh : Integer := 0;
begin
var_num_max_xfers_allowed := data_fifo_depth/max_xfer_length;
var_dre_dbeat_overhead := var_num_max_xfers_allowed * dre_is_used;
var_delay_fudge_factor := (dre_is_used * DRE_PIPE_DELAY) +
pipeline_delay_clks +
fifo_settling_clks;
var_thresh_headroom := max_xfer_length +
var_dre_dbeat_overhead +
var_delay_fudge_factor;
-- Scale the result to be in max transfer length increments
var_stall_thresh := (data_fifo_depth - var_thresh_headroom)/max_xfer_length;
Return (var_stall_thresh);
end function funct_get_stall_thresh;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_size_drecntl_fifo
--
-- Function Description:
-- Assures that the DRE control fifo depth is at least 4 deep else it
-- is equal to the number of max burst transfers that can fit in the
-- Store and Forward Data FIFO.
--
-------------------------------------------------------------------
function funct_size_drecntl_fifo (sf_fifo_depth : integer;
max_burst_length : integer) return integer is
Constant NEEDED_FIFO_DEPTH : integer := sf_fifo_depth/max_burst_length;
Variable temp_fifo_depth : Integer := 4;
begin
If (NEEDED_FIFO_DEPTH < 4) Then
temp_fifo_depth := 4;
Else
temp_fifo_depth := NEEDED_FIFO_DEPTH;
End if;
Return (temp_fifo_depth);
end function funct_size_drecntl_fifo;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_cntr_width
--
-- Function Description:
-- Detirmine the width needed for the address offset counter used
-- for the data fifo mux selects.
--
-------------------------------------------------------------------
function funct_get_cntr_width (num_count_states : integer) return integer is
Variable lvar_temp_width : Integer := 1;
begin
if (num_count_states <= 2) then
lvar_temp_width := 1;
elsif (num_count_states <= 4) then
lvar_temp_width := 2;
elsif (num_count_states <= 8) then
lvar_temp_width := 3;
elsif (num_count_states <= 16) then
lvar_temp_width := 4;
elsif (num_count_states <= 32) then
lvar_temp_width := 5;
elsif (num_count_states <= 64) then
lvar_temp_width := 6;
Else -- 128 cnt states
lvar_temp_width := 7;
end if;
Return (lvar_temp_width);
end function funct_get_cntr_width;
-- Constants ---------------------------------------------------------------------------
Constant LOGIC_LOW : std_logic := '0';
Constant LOGIC_HIGH : std_logic := '1';
Constant BLK_MEM_FIFO : integer := 1;
Constant SRL_FIFO : integer := 0;
Constant NOT_NEEDED : integer := 0;
Constant MMAP_TKEEP_WIDTH : integer := C_MMAP_DWIDTH/8; -- bits
Constant TLAST_WIDTH : integer := 1; -- bits
Constant CMPLT_WIDTH : integer := 1; -- bits
Constant DRE_FLUSH_WIDTH : integer := 1; -- bits
Constant DATA_FIFO_DEPTH : integer := C_SF_FIFO_DEPTH;
Constant DATA_FIFO_CNT_WIDTH : integer := funct_get_fifo_cnt_width(DATA_FIFO_DEPTH);
Constant DF_WRCNT_RIP_LS_INDEX : integer := funct_get_wrcnt_lsrip(C_MAX_BURST_LEN);
Constant DATA_FIFO_WIDTH : integer := C_MMAP_DWIDTH +
MMAP_TKEEP_WIDTH*C_ENABLE_MM2S_TKEEP +
TLAST_WIDTH +
CMPLT_WIDTH +
DRE_FLUSH_WIDTH;
Constant DATA_OUT_LSB_INDEX : integer := 0;
Constant DATA_OUT_MSB_INDEX : integer := C_MMAP_DWIDTH-1;
Constant TKEEP_OUT_LSB_INDEX : integer := DATA_OUT_MSB_INDEX+1;
Constant TKEEP_OUT_MSB_INDEX : integer := (TKEEP_OUT_LSB_INDEX+MMAP_TKEEP_WIDTH*C_ENABLE_MM2S_TKEEP)-1*C_ENABLE_MM2S_TKEEP;
Constant TLAST_OUT_INDEX : integer := TKEEP_OUT_MSB_INDEX+1*C_ENABLE_MM2S_TKEEP;
Constant CMPLT_OUT_INDEX : integer := TLAST_OUT_INDEX+1;
Constant DRE_FLUSH_OUT_INDEX : integer := CMPLT_OUT_INDEX+1;
Constant TOKEN_POOL_SIZE : integer := C_SF_FIFO_DEPTH / C_MAX_BURST_LEN;
Constant TOKEN_CNTR_WIDTH : integer := clog2(TOKEN_POOL_SIZE)+1;
Constant TOKEN_CNT_ZERO : Unsigned(TOKEN_CNTR_WIDTH-1 downto 0) :=
TO_UNSIGNED(0, TOKEN_CNTR_WIDTH);
Constant TOKEN_CNT_ONE : Unsigned(TOKEN_CNTR_WIDTH-1 downto 0) :=
TO_UNSIGNED(1, TOKEN_CNTR_WIDTH);
Constant TOKEN_CNT_MAX : Unsigned(TOKEN_CNTR_WIDTH-1 downto 0) :=
TO_UNSIGNED(TOKEN_POOL_SIZE, TOKEN_CNTR_WIDTH);
Constant THRESH_COMPARE_WIDTH : integer := TOKEN_CNTR_WIDTH+2;
Constant RD_PATH_PIPE_DEPTH : integer := 2; -- clocks excluding DRE
Constant WRCNT_SETTLING_TIME : integer := 2; -- data fifo push or pop settling clocks
Constant DRE_COMPENSATION : integer := 0; -- DRE does not contribute since it is on
-- the output side of the Store and Forward
Constant RD_ADDR_POST_STALL_THRESH : integer :=
funct_get_stall_thresh(DRE_COMPENSATION ,
C_MAX_BURST_LEN ,
C_SF_FIFO_DEPTH ,
RD_PATH_PIPE_DEPTH ,
WRCNT_SETTLING_TIME);
Constant RD_ADDR_POST_STALL_THRESH_US : Unsigned(THRESH_COMPARE_WIDTH-1 downto 0) :=
TO_UNSIGNED(RD_ADDR_POST_STALL_THRESH ,
THRESH_COMPARE_WIDTH);
Constant UNCOM_WRCNT_1 : Unsigned(DATA_FIFO_CNT_WIDTH-1 downto 0) :=
TO_UNSIGNED(1, DATA_FIFO_CNT_WIDTH);
Constant UNCOM_WRCNT_0 : Unsigned(DATA_FIFO_CNT_WIDTH-1 downto 0) :=
TO_UNSIGNED(0, DATA_FIFO_CNT_WIDTH);
Constant USE_SYNC_FIFO : integer := 0;
Constant SRL_FIFO_PRIM : integer := 2;
Constant TAG_WIDTH : integer := C_TAG_WIDTH;
Constant SRC_ALIGN_WIDTH : integer := C_DRE_ALIGN_WIDTH;
Constant DEST_ALIGN_WIDTH : integer := C_DRE_ALIGN_WIDTH;
Constant DRR_WIDTH : integer := 1;
Constant EOF_WIDTH : integer := 1;
Constant CALC_ERR_WIDTH : integer := 1;
Constant SF_OFFSET_WIDTH : integer := C_STRT_SF_OFFSET_WIDTH;
-- Signals ---------------------------------------------------------------------------
signal sig_good_sin_strm_dbeat : std_logic := '0';
signal sig_strm_sin_ready : std_logic := '0';
signal sig_good_sout_strm_dbeat : std_logic := '0';
signal sig_sout2sf_tready : std_logic := '0';
signal sig_sf2sout_tvalid : std_logic := '0';
signal sig_sf2sout_tdata : std_logic_vector(C_STREAM_DWIDTH-1 downto 0) := (others => '0');
signal sig_sf2sout_tkeep : std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0) := (others => '0');
signal sig_sf2sout_tlast : std_logic := '0';
signal sig_sf2dre_flush : std_logic := '0';
signal sig_push_data_fifo : std_logic := '0';
signal sig_pop_data_fifo : std_logic := '0';
signal sig_data_fifo_full : std_logic := '0';
signal sig_data_fifo_data_in : std_logic_vector(DATA_FIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_data_fifo_dvalid : std_logic := '0';
signal sig_data_fifo_data_out : std_logic_vector(DATA_FIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_data_fifo_wr_cnt : std_logic_vector(DATA_FIFO_CNT_WIDTH-1 downto 0) := (others => '0');
signal sig_fifo_wr_cnt_unsgnd : unsigned(DATA_FIFO_CNT_WIDTH-1 downto 0) := (others => '0');
signal sig_wrcnt_mblen_slice : unsigned(DATA_FIFO_CNT_WIDTH-1 downto
DF_WRCNT_RIP_LS_INDEX) := (others => '0');
signal sig_ok_to_post_rd_addr : std_logic := '0';
signal sig_rd_addr_posted : std_logic := '0';
signal sig_rd_xfer_cmplt : std_logic := '0';
signal sig_taking_last_token : std_logic := '0';
signal sig_stall_rd_addr_posts : std_logic := '0';
signal sig_incr_token_cntr : std_logic := '0';
signal sig_decr_token_cntr : std_logic := '0';
signal sig_token_eq_max : std_logic := '0';
signal sig_token_eq_zero : std_logic := '0';
signal sig_token_eq_one : std_logic := '0';
signal sig_token_cntr : Unsigned(TOKEN_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_tokens_commited : Unsigned(TOKEN_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_commit_plus_actual : unsigned(THRESH_COMPARE_WIDTH-1 downto 0) := (others => '0');
signal sig_cntl_fifo_has_data : std_logic := '0';
signal sig_get_cntl_fifo_data : std_logic := '0';
signal sig_curr_tag_reg : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_curr_src_align_reg : std_logic_vector(SRC_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_curr_dest_align_reg : std_logic_vector(DEST_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_curr_drr_reg : std_logic := '0';
signal sig_curr_eof_reg : std_logic := '0';
signal sig_curr_calc_error_reg : std_logic := '0';
signal sig_curr_strt_offset_reg : std_logic_vector(SF_OFFSET_WIDTH-1 downto 0) := (others => '0');
signal sig_ld_dre_cntl_reg : std_logic := '0';
signal sig_dfifo_data_out : std_logic_vector(C_MMAP_DWIDTH-1 downto 0) := (others => '0');
signal sig_dfifo_tkeep_out : std_logic_vector(MMAP_TKEEP_WIDTH-1 downto 0) := (others => '0');
signal sig_dfifo_tlast_out : std_logic := '0';
signal sig_dfifo_cmd_cmplt_out : std_logic := '0';
signal sig_dfifo_dre_flush_out : std_logic := '0';
begin --(architecture implementation)
-- Read Side (MM2S) Control Flags port connections
ok_to_post_rd_addr <= sig_ok_to_post_rd_addr ;
sig_rd_addr_posted <= rd_addr_posted ;
sig_rd_xfer_cmplt <= rd_xfer_cmplt ;
-- Output Stream Port connections
sig_sout2sf_tready <= sout2sf_tready ;
sf2sout_tvalid <= sig_sf2sout_tvalid ;
sf2sout_tdata <= sig_sf2sout_tdata ;
--sf2sout_tkeep <= sig_sf2sout_tkeep ;
sf2sout_tlast <= sig_sf2sout_tlast and
sig_sf2sout_tvalid ;
GEN_MM2S_TKEEP_ENABLE4 : if C_ENABLE_MM2S_TKEEP = 1 generate
begin
sf2sout_tkeep <= sig_sf2sout_tkeep ;
end generate GEN_MM2S_TKEEP_ENABLE4;
GEN_MM2S_TKEEP_DISABLE4 : if C_ENABLE_MM2S_TKEEP = 0 generate
begin
sf2sout_tkeep <= (others => '1');
end generate GEN_MM2S_TKEEP_DISABLE4;
-- Input Stream port connections
sf2sin_tready <= sig_strm_sin_ready;
sig_strm_sin_ready <= not(sig_data_fifo_full); -- Throttle if Read Side Data fifo goes full.
-- This should never happen if read address
-- posting control is working properly.
-- Stream transfer qualifiers
sig_good_sin_strm_dbeat <= sin2sf_tvalid and
sig_strm_sin_ready;
sig_good_sout_strm_dbeat <= sig_sf2sout_tvalid and
sig_sout2sf_tready;
----------------------------------------------------------------
-- Unpacking Logic ------------------------------------------
----------------------------------------------------------------
------------------------------------------------------------
-- If Generate
--
-- Label: OMIT_UNPACKING
--
-- If Generate Description:
-- Omits any unpacking logic in the Store and Forward module.
-- The Stream and MMap data widths are the same. The Data FIFO
-- output can be connected directly to the stream outputs.
--
------------------------------------------------------------
OMIT_UNPACKING : if (C_MMAP_DWIDTH = C_STREAM_DWIDTH) generate
signal lsig_cmd_loaded : std_logic := '0';
signal lsig_ld_cmd : std_logic := '0';
signal lsig_cmd_cmplt_dbeat : std_logic := '0';
signal lsig_cmd_cmplt : std_logic := '0';
begin
-- Data FIFO Output to the stream attachments
sig_sf2sout_tvalid <= sig_data_fifo_dvalid and
lsig_cmd_loaded ;
sig_sf2sout_tdata <= sig_dfifo_data_out ;
sig_sf2sout_tkeep <= sig_dfifo_tkeep_out ;
sig_sf2sout_tlast <= sig_dfifo_tlast_out ;
sig_sf2dre_flush <= sig_dfifo_dre_flush_out ;
-- Control for reading the Data FIFO
sig_pop_data_fifo <= lsig_cmd_loaded and
sig_sout2sf_tready and
sig_data_fifo_dvalid;
-- Control for reading the Command/Offset FIFO
sig_get_cntl_fifo_data <= lsig_ld_cmd ;
-- Control for loading the DRE Control Reg
sig_ld_dre_cntl_reg <= lsig_ld_cmd ;
lsig_cmd_cmplt_dbeat <= sig_dfifo_cmd_cmplt_out and
lsig_cmd_loaded and
sig_data_fifo_dvalid and
sig_sout2sf_tready ;
-- Generate the control that loads the DRE
lsig_ld_cmd <= (sig_cntl_fifo_has_data and -- startup or gap case
not(lsig_cmd_loaded)) or
(sig_cntl_fifo_has_data and -- back to back commands
lsig_cmd_cmplt_dbeat);
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_CMD_LOADED
--
-- Process Description:
-- Implements the flop indicating a command from the cmd fifo
-- has been loaded into the DRE Output Register.
--
-------------------------------------------------------------
IMP_CMD_LOADED : process (aclk)
begin
if (aclk'event and aclk = '1') then
if (reset = '1') then
lsig_cmd_loaded <= '0';
Elsif (lsig_ld_cmd = '1' ) Then
lsig_cmd_loaded <= '1';
elsif (sig_cntl_fifo_has_data = '0' and -- No more commands queued and
lsig_cmd_cmplt_dbeat = '1') then
lsig_cmd_loaded <= '0';
else
null; -- Hold Current State
end if;
end if;
end process IMP_CMD_LOADED;
end generate OMIT_UNPACKING;
------------------------------------------------------------
-- If Generate
--
-- Label: INCLUDE_UNPACKING
--
-- If Generate Description:
-- Includes unpacking logic in the Store and Forward module.
-- The MMap Data bus is wider than the Stream width.
--
------------------------------------------------------------
INCLUDE_UNPACKING : if (C_MMAP_DWIDTH > C_STREAM_DWIDTH) generate
Constant MMAP2STRM_WIDTH_RATO : integer := C_MMAP_DWIDTH/C_STREAM_DWIDTH;
Constant DATA_SLICE_WIDTH : integer := C_STREAM_DWIDTH;
Constant TKEEP_SLICE_WIDTH : integer := C_STREAM_DWIDTH/8;
Constant FLAG_SLICE_WIDTH : integer := TLAST_WIDTH;
Constant OFFSET_CNTR_WIDTH : integer := funct_get_cntr_width(MMAP2STRM_WIDTH_RATO);
Constant OFFSET_CNT_ONE : unsigned(OFFSET_CNTR_WIDTH-1 downto 0) :=
TO_UNSIGNED(1, OFFSET_CNTR_WIDTH);
Constant OFFSET_CNT_MAX : unsigned(OFFSET_CNTR_WIDTH-1 downto 0) :=
TO_UNSIGNED(MMAP2STRM_WIDTH_RATO-1, OFFSET_CNTR_WIDTH);
-- Types -----------------------------------------------------------------------------
type lsig_data_slice_type is array(MMAP2STRM_WIDTH_RATO-1 downto 0) of
std_logic_vector(DATA_SLICE_WIDTH-1 downto 0);
type lsig_tkeep_slice_type is array(MMAP2STRM_WIDTH_RATO downto 0) of
std_logic_vector(TKEEP_SLICE_WIDTH-1 downto 0);
type lsig_flag_slice_type is array(MMAP2STRM_WIDTH_RATO-1 downto 0) of
std_logic_vector(FLAG_SLICE_WIDTH-1 downto 0);
-- local signals
signal lsig_0ffset_cntr : unsigned(OFFSET_CNTR_WIDTH-1 downto 0) := (others => '0');
signal lsig_ld_offset : std_logic := '0';
signal lsig_incr_offset : std_logic := '0';
signal lsig_offset_cntr_eq_max : std_logic := '0';
signal lsig_fifo_data_out_wide : lsig_data_slice_type;
signal lsig_fifo_tkeep_out_wide : lsig_tkeep_slice_type;
signal lsig_mux_sel : integer range 0 to MMAP2STRM_WIDTH_RATO-1;
signal lsig_data_mux_out : std_logic_vector(DATA_SLICE_WIDTH-1 downto 0) ;
signal lsig_tkeep_mux_out : std_logic_vector(TKEEP_SLICE_WIDTH-1 downto 0);
signal lsig_tlast_out : std_logic := '0';
signal lsig_dre_flush_out : std_logic := '0';
signal lsig_this_fifo_wrd_done : std_logic := '0';
signal lsig_cmd_loaded : std_logic := '0';
signal lsig_cmd_cmplt_dbeat : std_logic := '0';
signal lsig_cmd_cmplt : std_logic := '0';
signal lsig_next_slice_tkeep_0 : std_logic := '0';
begin
sig_sf2sout_tvalid <= sig_data_fifo_dvalid and
lsig_cmd_loaded ;
sig_sf2sout_tdata <= lsig_data_mux_out ;
sig_sf2sout_tkeep <= lsig_tkeep_mux_out(TKEEP_SLICE_WIDTH-1 downto 0);
sig_sf2sout_tlast <= lsig_tlast_out ;
sig_sf2dre_flush <= lsig_dre_flush_out ;
-- Control for reading the Data FIFO
sig_pop_data_fifo <= lsig_this_fifo_wrd_done and
lsig_cmd_loaded and
sig_sout2sf_tready and
sig_data_fifo_dvalid;
-- Control for reading the Command/Offset FIFO
sig_get_cntl_fifo_data <= lsig_ld_offset;
-- Control for loading the DRE Control Reg
sig_ld_dre_cntl_reg <= lsig_ld_offset ;
lsig_next_slice_tkeep_0 <= lsig_fifo_tkeep_out_wide(lsig_mux_sel+1)(0);
-- Detirmine if a Command Complete condition exists
lsig_cmd_cmplt <= '1'
when (sig_dfifo_cmd_cmplt_out = '1' and
lsig_next_slice_tkeep_0 = '0')
Else '0';
-- Detirmine if a TLAST condition exists
-- From the RDC via the Data FIFO
lsig_tlast_out <= '1'
when (sig_dfifo_tlast_out = '1' and
lsig_next_slice_tkeep_0 = '0')
Else '0';
-- Detimine if a DRE Flush condition exists
-- From the RDC via the Data FIFO
lsig_dre_flush_out <= '1'
when (sig_dfifo_dre_flush_out = '1' and
lsig_next_slice_tkeep_0 = '0')
Else '0';
lsig_cmd_cmplt_dbeat <= lsig_cmd_cmplt and
lsig_cmd_loaded and
sig_data_fifo_dvalid and
sig_sout2sf_tready ;
-- Check to see if the FIFO output word is finished. This occurs
-- when the offset counter is at max value or the tlast from the
-- fifo is set and the LS TKEED of the next MS Slice is zero.
lsig_this_fifo_wrd_done <= '1'
When (lsig_offset_cntr_eq_max = '1' or
(lsig_cmd_cmplt_dbeat = '1' and
lsig_next_slice_tkeep_0 = '0'))
Else '0';
-- Generate the control that loads the starting address
-- offset for the next input packet
lsig_ld_offset <= (sig_cntl_fifo_has_data and -- startup or gap case
not(lsig_cmd_loaded)) or
(sig_cntl_fifo_has_data and -- back to back commands
lsig_cmd_cmplt_dbeat);
-- Generate the control for incrementing the offset counter
lsig_incr_offset <= sig_good_sout_strm_dbeat;
-- Check to see if the offset counter has reached its max
-- value
lsig_offset_cntr_eq_max <= '1'
when (lsig_0ffset_cntr = OFFSET_CNT_MAX)
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_CMD_LOADED
--
-- Process Description:
-- Implements the flop indicating a command from the cmd fifo
-- has been loaded into the unpacker control logic.
--
-------------------------------------------------------------
IMP_CMD_LOADED : process (aclk)
begin
if (aclk'event and aclk = '1') then
if (reset = '1') then
lsig_cmd_loaded <= '0';
Elsif (lsig_ld_offset = '1' ) Then
lsig_cmd_loaded <= '1';
elsif (sig_cntl_fifo_has_data = '0' and -- No more commands queued
lsig_cmd_cmplt_dbeat = '1') then
lsig_cmd_loaded <= '0';
else
null; -- Hold Current State
end if;
end if;
end process IMP_CMD_LOADED;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_OFFSET_CNTR
--
-- Process Description:
-- Implements the address offset counter that is used to
-- generate the data and tkeep mux selects.
-- Note that the counter has to be loaded with the starting
-- offset plus one to sync up with the data input.
-------------------------------------------------------------
IMP_OFFSET_CNTR : process (aclk)
begin
if (aclk'event and aclk = '1') then
if (reset = '1') then
lsig_0ffset_cntr <= (others => '0');
Elsif (lsig_ld_offset = '1') Then
lsig_0ffset_cntr <= UNSIGNED(sig_curr_strt_offset_reg);
elsif (lsig_incr_offset = '1') then
lsig_0ffset_cntr <= lsig_0ffset_cntr + OFFSET_CNT_ONE;
else
null; -- Hold Current State
end if;
end if;
end process IMP_OFFSET_CNTR;
------------------------------------------------------------
-- For Generate
--
-- Label: DO_DATA_CONVERTER
--
-- For Generate Description:
-- This ForGen converts the FIFO output data and tkeep from a single
-- std logic vector type to a vector of slices.
--
------------------------------------------------------------
DO_DATA_CONVERTER : for slice_index in 1 to MMAP2STRM_WIDTH_RATO generate
begin
lsig_fifo_data_out_wide(slice_index-1) <=
sig_dfifo_data_out((slice_index*DATA_SLICE_WIDTH)-1 downto
(slice_index-1)*DATA_SLICE_WIDTH);
lsig_fifo_tkeep_out_wide(slice_index-1) <=
sig_dfifo_tkeep_out((slice_index*TKEEP_SLICE_WIDTH)-1 downto
(slice_index-1)*TKEEP_SLICE_WIDTH);
end generate DO_DATA_CONVERTER;
-- Assign the extra tkeep slice to all zeros to allow for detection
-- of the data word done when the ls tkeep bit of the next tkeep
-- slice is zero and the offset count is pointing to the last slice
-- position.
lsig_fifo_tkeep_out_wide(MMAP2STRM_WIDTH_RATO) <= (others => '0');
-- Mux the appropriate data and tkeep slice to the stream output
lsig_mux_sel <= TO_INTEGER(lsig_0ffset_cntr);
lsig_data_mux_out <= lsig_fifo_data_out_wide(lsig_mux_sel) ;
lsig_tkeep_mux_out(TKEEP_SLICE_WIDTH-1 downto 0) <= lsig_fifo_tkeep_out_wide(lsig_mux_sel);
end generate INCLUDE_UNPACKING;
------------------------------------------------------------
-- If Generate
--
-- Label: OMIT_DRE_CNTL
--
-- If Generate Description:
-- This IfGen is used to omit the DRE control logic and
-- minimize the Control FIFO when MM2S DRE is not included
-- in the MM2S.
--
------------------------------------------------------------
OMIT_DRE_CNTL : if (C_DRE_IS_USED = 0) generate
-- Constant Declarations ------------------------------------------------------------------
Constant USE_SYNC_FIFO : integer := 0;
Constant SRL_FIFO_PRIM : integer := 2;
Constant TAG_WIDTH : integer := C_TAG_WIDTH;
Constant DRR_WIDTH : integer := 1;
Constant EOF_WIDTH : integer := 1;
Constant CALC_ERR_WIDTH : integer := 1;
Constant SF_OFFSET_WIDTH : integer := C_STRT_SF_OFFSET_WIDTH;
Constant SF_OFFSET_FIFO_DEPTH : integer := funct_size_drecntl_fifo(C_DRE_CNTL_FIFO_DEPTH,
C_MAX_BURST_LEN);
Constant SF_OFFSET_FIFO_WIDTH : Integer := TAG_WIDTH + -- Tag field
DRR_WIDTH + -- DRE Re-alignment Request Flag Field
EOF_WIDTH + -- EOF flag field
CALC_ERR_WIDTH + -- Calc error flag
SF_OFFSET_WIDTH; -- Store and Forward Offset
Constant TAG_STRT_INDEX : integer := 0;
Constant DRR_STRT_INDEX : integer := TAG_STRT_INDEX + TAG_WIDTH;
Constant EOF_STRT_INDEX : integer := DRR_STRT_INDEX + DRR_WIDTH;
Constant CALC_ERR_STRT_INDEX : integer := EOF_STRT_INDEX + EOF_WIDTH;
Constant SF_OFFSET_STRT_INDEX : integer := CALC_ERR_STRT_INDEX+CALC_ERR_WIDTH;
-- Signal Declarations --------------------------------------------------------------------
signal sig_offset_fifo_data_in : std_logic_vector(SF_OFFSET_FIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_offset_fifo_data_out : std_logic_vector(SF_OFFSET_FIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_offset_fifo_wr_valid : std_logic := '0';
signal sig_offset_fifo_wr_ready : std_logic := '0';
signal sig_offset_fifo_rd_valid : std_logic := '0';
signal sig_offset_fifo_rd_ready : std_logic := '0';
begin
-- PCC DRE Command interface handshake
dre2mstr_cmd_ready <= sig_offset_fifo_wr_ready ;
sig_offset_fifo_wr_valid <= mstr2dre_cmd_valid ;
-- No DRE so no controls
sf2dre_new_align <= '0';
sf2dre_use_autodest <= '0';
sf2dre_src_align <= (others => '0');
sf2dre_dest_align <= (others => '0');
sf2dre_flush <= '0';
-- No DRE so no alignment values
sig_curr_src_align_reg <= (others => '0');
sig_curr_dest_align_reg <= (others => '0');
-- Format the input data word for the Offset FIFO Queue
sig_offset_fifo_data_in <= mstr2dre_strt_offset & -- MS field
mstr2dre_calc_error &
mstr2dre_eof &
mstr2dre_drr &
mstr2dre_tag; -- LS Field
sig_cntl_fifo_has_data <= sig_offset_fifo_rd_valid ;
sig_offset_fifo_rd_ready <= sig_get_cntl_fifo_data ;
-- Rip the output fifo data word
sig_curr_tag_reg <= sig_offset_fifo_data_out((TAG_STRT_INDEX+TAG_WIDTH)-1 downto TAG_STRT_INDEX);
sig_curr_drr_reg <= sig_offset_fifo_data_out(DRR_STRT_INDEX);
sig_curr_eof_reg <= sig_offset_fifo_data_out(EOF_STRT_INDEX);
sig_curr_calc_error_reg <= sig_offset_fifo_data_out(CALC_ERR_STRT_INDEX);
sig_curr_strt_offset_reg <= sig_offset_fifo_data_out((SF_OFFSET_STRT_INDEX+SF_OFFSET_WIDTH)-1 downto
SF_OFFSET_STRT_INDEX);
------------------------------------------------------------
-- Instance: I_DRE_CNTL_FIFO
--
-- Description:
-- Instance for the Offset Control FIFO. This is still needed
-- by the unpacker logic to get the starting offset at the
-- begining of an input packet coming out of the Store and
-- Forward data FIFO.
--
------------------------------------------------------------
I_DRE_CNTL_FIFO : entity axi_datamover_v5_1_9.axi_datamover_fifo
generic map (
C_DWIDTH => SF_OFFSET_FIFO_WIDTH ,
C_DEPTH => SF_OFFSET_FIFO_DEPTH ,
C_IS_ASYNC => USE_SYNC_FIFO ,
C_PRIM_TYPE => SRL_FIFO_PRIM ,
C_FAMILY => C_FAMILY
)
port map (
-- Write Clock and reset
fifo_wr_reset => reset ,
fifo_wr_clk => aclk ,
-- Write Side
fifo_wr_tvalid => sig_offset_fifo_wr_valid ,
fifo_wr_tready => sig_offset_fifo_wr_ready ,
fifo_wr_tdata => sig_offset_fifo_data_in ,
fifo_wr_full => open ,
-- Read Clock and reset
fifo_async_rd_reset => aclk ,
fifo_async_rd_clk => reset ,
-- Read Side
fifo_rd_tvalid => sig_offset_fifo_rd_valid ,
fifo_rd_tready => sig_offset_fifo_rd_ready ,
fifo_rd_tdata => sig_offset_fifo_data_out ,
fifo_rd_empty => open
);
end generate OMIT_DRE_CNTL;
------------------------------------------------------------
-- If Generate
--
-- Label: INCLUDE_DRE_CNTL
--
-- If Generate Description:
-- This IfGen is used to include the DRE control logic and
-- Control FIFO when MM2S DRE is included in the MM2S.
--
--
------------------------------------------------------------
INCLUDE_DRE_CNTL : if (C_DRE_IS_USED = 1) generate
-- Constant Declarations
Constant DRECNTL_FIFO_DEPTH : integer := funct_size_drecntl_fifo(C_DRE_CNTL_FIFO_DEPTH,
C_MAX_BURST_LEN);
Constant DRECNTL_FIFO_WIDTH : Integer := TAG_WIDTH + -- Tag field
SRC_ALIGN_WIDTH + -- Source align field width
DEST_ALIGN_WIDTH + -- Dest align field width
DRR_WIDTH + -- DRE Re-alignment Request Flag Field
EOF_WIDTH + -- EOF flag field
CALC_ERR_WIDTH + -- Calc error flag
SF_OFFSET_WIDTH; -- Store and Forward Offset
Constant TAG_STRT_INDEX : integer := 0;
Constant SRC_ALIGN_STRT_INDEX : integer := TAG_STRT_INDEX + TAG_WIDTH;
Constant DEST_ALIGN_STRT_INDEX : integer := SRC_ALIGN_STRT_INDEX + SRC_ALIGN_WIDTH;
Constant DRR_STRT_INDEX : integer := DEST_ALIGN_STRT_INDEX + DEST_ALIGN_WIDTH;
Constant EOF_STRT_INDEX : integer := DRR_STRT_INDEX + DRR_WIDTH;
Constant CALC_ERR_STRT_INDEX : integer := EOF_STRT_INDEX + EOF_WIDTH;
Constant SF_OFFSET_STRT_INDEX : integer := CALC_ERR_STRT_INDEX+CALC_ERR_WIDTH;
signal sig_cmd_fifo_data_in : std_logic_vector(DRECNTL_FIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd_fifo_data_out : std_logic_vector(DRECNTL_FIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_fifo_wr_cmd_valid : std_logic := '0';
signal sig_fifo_wr_cmd_ready : std_logic := '0';
signal sig_fifo_rd_cmd_valid : std_logic := '0';
signal sig_fifo_rd_cmd_ready : std_logic := '0';
signal sig_dre_align_ready : std_logic := '0';
signal sig_dre_align_valid_reg : std_logic := '0';
signal sig_dre_use_autodest_reg : std_logic := '0';
signal sig_dre_src_align_reg : std_logic_vector(SRC_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_dre_dest_align_reg : std_logic_vector(DEST_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_dre_flush_reg : std_logic := '0';
begin
-- Assign the DRE Control Outputs
sf2dre_new_align <= sig_dre_align_valid_reg;
sf2dre_use_autodest <= sig_dre_use_autodest_reg;
sf2dre_src_align <= sig_dre_src_align_reg;
sf2dre_dest_align <= sig_dre_dest_align_reg;
sf2dre_flush <= sig_sf2dre_flush; -- from RDC via data FIFO
-- PCC DRE Command interface handshake
dre2mstr_cmd_ready <= sig_fifo_wr_cmd_ready;
sig_fifo_wr_cmd_valid <= mstr2dre_cmd_valid ;
-- Format the input data word for the DRE Control FIFO Queue
sig_cmd_fifo_data_in <= mstr2dre_strt_offset &
mstr2dre_calc_error &
mstr2dre_eof &
mstr2dre_drr &
mstr2dre_dre_dest_align &
mstr2dre_dre_src_align &
mstr2dre_tag;
-- Formulate the DRE Control FIFO Read signaling
sig_cntl_fifo_has_data <= sig_fifo_rd_cmd_valid ;
sig_fifo_rd_cmd_ready <= sig_get_cntl_fifo_data ;
-- Rip the output fifo data word
sig_curr_tag_reg <= sig_cmd_fifo_data_out((TAG_STRT_INDEX+TAG_WIDTH)-1 downto TAG_STRT_INDEX);
sig_curr_src_align_reg <= sig_cmd_fifo_data_out((SRC_ALIGN_STRT_INDEX+SRC_ALIGN_WIDTH)-1 downto
SRC_ALIGN_STRT_INDEX);
sig_curr_dest_align_reg <= sig_cmd_fifo_data_out((DEST_ALIGN_STRT_INDEX+DEST_ALIGN_WIDTH)-1 downto
DEST_ALIGN_STRT_INDEX);
sig_curr_drr_reg <= sig_cmd_fifo_data_out(DRR_STRT_INDEX);
sig_curr_eof_reg <= sig_cmd_fifo_data_out(EOF_STRT_INDEX);
sig_curr_calc_error_reg <= sig_cmd_fifo_data_out(CALC_ERR_STRT_INDEX);
sig_curr_strt_offset_reg <= sig_cmd_fifo_data_out((SF_OFFSET_STRT_INDEX+SF_OFFSET_WIDTH)-1 downto
SF_OFFSET_STRT_INDEX);
------------------------------------------------------------
-- Instance: I_DRE_CNTL_FIFO
--
-- Description:
-- Instance for the DRE Control FIFO
--
------------------------------------------------------------
I_DRE_CNTL_FIFO : entity axi_datamover_v5_1_9.axi_datamover_fifo
generic map (
C_DWIDTH => DRECNTL_FIFO_WIDTH ,
C_DEPTH => DRECNTL_FIFO_DEPTH ,
C_IS_ASYNC => USE_SYNC_FIFO ,
C_PRIM_TYPE => SRL_FIFO_PRIM ,
C_FAMILY => C_FAMILY
)
port map (
-- Write Clock and reset
fifo_wr_reset => reset ,
fifo_wr_clk => aclk ,
-- Write Side
fifo_wr_tvalid => sig_fifo_wr_cmd_valid ,
fifo_wr_tready => sig_fifo_wr_cmd_ready ,
fifo_wr_tdata => sig_cmd_fifo_data_in ,
fifo_wr_full => open ,
-- Read Clock and reset
fifo_async_rd_reset => aclk ,
fifo_async_rd_clk => reset ,
-- Read Side
fifo_rd_tvalid => sig_fifo_rd_cmd_valid ,
fifo_rd_tready => sig_fifo_rd_cmd_ready ,
fifo_rd_tdata => sig_cmd_fifo_data_out ,
fifo_rd_empty => open
);
-------------------------------------------------------------------------
-- DRE Control Register
-------------------------------------------------------------------------
-- The DRE will auto-flush on a received TLAST so a commanded Flush
-- is not needed.
sig_dre_flush_reg <= '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_CNTL_REG
--
-- Process Description:
-- Implements the DRE alignment Output Register.
--
-------------------------------------------------------------
IMP_CNTL_REG : process (aclk)
begin
if (aclk'event and aclk = '1') then
if (reset = '1') then
sig_dre_use_autodest_reg <= '0' ;
sig_dre_src_align_reg <= (others => '0') ;
sig_dre_dest_align_reg <= (others => '0') ;
Elsif (sig_ld_dre_cntl_reg = '1' ) Then
sig_dre_use_autodest_reg <= not(sig_curr_drr_reg) ;
sig_dre_src_align_reg <= sig_curr_src_align_reg ;
sig_dre_dest_align_reg <= sig_curr_dest_align_reg ;
Elsif (sig_good_sout_strm_dbeat = '1') Then
sig_dre_use_autodest_reg <= '0' ;
sig_dre_src_align_reg <= (others => '0') ;
sig_dre_dest_align_reg <= (others => '0') ;
else
null; -- Hold Current State
end if;
end if;
end process IMP_CNTL_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_DRE_CNTL_VALID_REG
--
-- Process Description:
-- Implements the DRE Alignment valid Register.
--
-------------------------------------------------------------
IMP_DRE_CNTL_VALID_REG : process (aclk)
begin
if (aclk'event and aclk = '1') then
if (reset = '1') then
sig_dre_align_valid_reg <= '0' ;
Elsif (sig_ld_dre_cntl_reg = '1' ) Then
sig_dre_align_valid_reg <= '1' ;
Elsif (sig_good_sout_strm_dbeat = '1') Then
sig_dre_align_valid_reg <= '0' ;
else
null; -- Hold Current State
end if;
end if;
end process IMP_DRE_CNTL_VALID_REG;
end generate INCLUDE_DRE_CNTL;
----------------------------------------------------------------
-- Token Counter Logic
-- Predicting fifo space availability at some point in the
-- future is based on managing a virtual pool of transfer tokens.
-- A token represents 1 max length burst worth of space in the
-- Data FIFO.
----------------------------------------------------------------
-- calculate how many tokens are commited to pending transfers
sig_tokens_commited <= TOKEN_CNT_MAX - sig_token_cntr;
-- Decrement the token counter when a token is
-- borrowed
sig_decr_token_cntr <= '1'
when (sig_rd_addr_posted = '1' and
sig_token_eq_zero = '0')
else '0';
-- Increment the token counter when a
-- token is returned.
sig_incr_token_cntr <= '1'
when (sig_rd_xfer_cmplt = '1' and
sig_token_eq_max = '0')
else '0';
-- Detect when the xfer token count is at max value
sig_token_eq_max <= '1'
when (sig_token_cntr = TOKEN_CNT_MAX)
Else '0';
-- Detect when the xfer token count is at one
sig_token_eq_one <= '1'
when (sig_token_cntr = TOKEN_CNT_ONE)
Else '0';
-- Detect when the xfer token count is at zero
sig_token_eq_zero <= '1'
when (sig_token_cntr = TOKEN_CNT_ZERO)
Else '0';
-- Look ahead to see if the xfer token pool is going empty
sig_taking_last_token <= '1'
When (sig_token_eq_one = '1' and
sig_rd_addr_posted = '1')
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_TOKEN_CNTR
--
-- Process Description:
-- Implements the Token counter
--
-------------------------------------------------------------
IMP_TOKEN_CNTR : process (aclk)
begin
if (aclk'event and aclk = '1') then
if (reset = '1' ) then
sig_token_cntr <= TOKEN_CNT_MAX;
elsif (sig_incr_token_cntr = '1' and
sig_decr_token_cntr = '0') then
sig_token_cntr <= sig_token_cntr + TOKEN_CNT_ONE;
elsif (sig_incr_token_cntr = '0' and
sig_decr_token_cntr = '1') then
sig_token_cntr <= sig_token_cntr - TOKEN_CNT_ONE;
else
null; -- hold current value
end if;
end if;
end process IMP_TOKEN_CNTR;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_TOKEN_AVAIL_FLAG
--
-- Process Description:
-- Implements the flag indicating that the AXI Read Master
-- can post a read address request on the AXI4 bus.
--
-- Read address posting can occur if:
--
-- - The write side LEN fifo is not empty.
-- - The commited plus actual Data FIFO space is less than
-- the stall threshold (a max length read burst can fit
-- in the data FIFO without overflow).
-- - The max allowed commited read count has not been reached.
--
-- The flag is cleared after each address has been posted to
-- ensure a second unauthorized post does not occur.
-------------------------------------------------------------
IMP_TOKEN_AVAIL_FLAG : process (aclk)
begin
if (aclk'event and aclk = '1') then
if (reset = '1' or
sig_rd_addr_posted = '1') then
sig_ok_to_post_rd_addr <= '0';
else
sig_ok_to_post_rd_addr <= not(sig_stall_rd_addr_posts) and -- the commited Data FIFO space is approaching full
not(sig_token_eq_zero) and -- max allowed pending reads has not been reached
not(sig_taking_last_token); -- the max allowed pending reads is about to be reached
end if;
end if;
end process IMP_TOKEN_AVAIL_FLAG;
----------------------------------------------------------------
-- Data FIFO Logic ------------------------------------------
----------------------------------------------------------------
GEN_MM2S_TKEEP_ENABLE3 : if C_ENABLE_MM2S_TKEEP = 1 generate
begin
-- FIFO Output ripping to components
sig_dfifo_data_out <= sig_data_fifo_data_out(DATA_OUT_MSB_INDEX downto
DATA_OUT_LSB_INDEX);
sig_dfifo_tkeep_out <= sig_data_fifo_data_out(TKEEP_OUT_MSB_INDEX downto
TKEEP_OUT_LSB_INDEX);
sig_dfifo_tlast_out <= sig_data_fifo_data_out(TLAST_OUT_INDEX) ;
sig_dfifo_cmd_cmplt_out <= sig_data_fifo_data_out(CMPLT_OUT_INDEX) ;
sig_dfifo_dre_flush_out <= sig_data_fifo_data_out(DRE_FLUSH_OUT_INDEX) ;
end generate GEN_MM2S_TKEEP_ENABLE3;
GEN_MM2S_TKEEP_DISABLE3 : if C_ENABLE_MM2S_TKEEP = 0 generate
begin
-- FIFO Output ripping to components
sig_dfifo_data_out <= sig_data_fifo_data_out(DATA_OUT_MSB_INDEX downto
DATA_OUT_LSB_INDEX);
sig_dfifo_tkeep_out <= (others => '1');
sig_dfifo_tlast_out <= sig_data_fifo_data_out(TLAST_OUT_INDEX) ;
sig_dfifo_cmd_cmplt_out <= sig_data_fifo_data_out(CMPLT_OUT_INDEX) ;
sig_dfifo_dre_flush_out <= sig_data_fifo_data_out(DRE_FLUSH_OUT_INDEX) ;
end generate GEN_MM2S_TKEEP_DISABLE3;
-- Stall Threshold calculations
sig_fifo_wr_cnt_unsgnd <= UNSIGNED(sig_data_fifo_wr_cnt);
sig_wrcnt_mblen_slice <= sig_fifo_wr_cnt_unsgnd(DATA_FIFO_CNT_WIDTH-1 downto
DF_WRCNT_RIP_LS_INDEX);
sig_commit_plus_actual <= RESIZE(sig_tokens_commited, THRESH_COMPARE_WIDTH) +
RESIZE(sig_wrcnt_mblen_slice, THRESH_COMPARE_WIDTH);
-- Compare the commited read space plus the actual used space against the
-- stall threshold. Assert the read address posting stall flag if the
-- threshold is met or exceeded.
sig_stall_rd_addr_posts <= '1'
when (sig_commit_plus_actual > RD_ADDR_POST_STALL_THRESH_US)
Else '0';
-- FIFO Rd/WR Controls
sig_push_data_fifo <= sig_good_sin_strm_dbeat;
-- sig_pop_data_fifo <= sig_sout2sf_tready and
-- sig_data_fifo_dvalid;
GEN_MM2S_TKEEP_ENABLE2 : if C_ENABLE_MM2S_TKEEP = 1 generate
begin
-- Concatonate the Stream inputs into the single FIFO data in value
sig_data_fifo_data_in <= data2sf_dre_flush & -- ms Field
data2sf_cmd_cmplt &
sin2sf_tlast &
sin2sf_tkeep &
sin2sf_tdata; -- ls field
end generate GEN_MM2S_TKEEP_ENABLE2;
GEN_MM2S_TKEEP_DISABLE2 : if C_ENABLE_MM2S_TKEEP = 0 generate
begin
-- Concatonate the Stream inputs into the single FIFO data in value
sig_data_fifo_data_in <= data2sf_dre_flush & -- ms Field
data2sf_cmd_cmplt &
sin2sf_tlast &
--sin2sf_tkeep &
sin2sf_tdata; -- ls field
end generate GEN_MM2S_TKEEP_DISABLE2;
------------------------------------------------------------
-- Instance: I_DATA_FIFO
--
-- Description:
-- Implements the Store and Forward data FIFO (synchronous)
--
------------------------------------------------------------
I_DATA_FIFO : entity axi_datamover_v5_1_9.axi_datamover_sfifo_autord
generic map (
C_DWIDTH => DATA_FIFO_WIDTH ,
C_DEPTH => DATA_FIFO_DEPTH ,
C_DATA_CNT_WIDTH => DATA_FIFO_CNT_WIDTH ,
C_NEED_ALMOST_EMPTY => NOT_NEEDED ,
C_NEED_ALMOST_FULL => NOT_NEEDED ,
C_USE_BLKMEM => BLK_MEM_FIFO ,
C_FAMILY => C_FAMILY
)
port map (
-- Inputs
SFIFO_Sinit => reset ,
SFIFO_Clk => aclk ,
SFIFO_Wr_en => sig_push_data_fifo ,
SFIFO_Din => sig_data_fifo_data_in ,
SFIFO_Rd_en => sig_pop_data_fifo ,
SFIFO_Clr_Rd_Data_Valid => LOGIC_LOW ,
-- Outputs
SFIFO_DValid => sig_data_fifo_dvalid ,
SFIFO_Dout => sig_data_fifo_data_out ,
SFIFO_Full => sig_data_fifo_full ,
SFIFO_Empty => open ,
SFIFO_Almost_full => open ,
SFIFO_Almost_empty => open ,
SFIFO_Rd_count => open ,
SFIFO_Rd_count_minus1 => open ,
SFIFO_Wr_count => sig_data_fifo_wr_cnt ,
SFIFO_Rd_ack => open
);
end implementation;
|
-------------------------------------------------------------------------------
-- axi_datamover_rd_sf.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_rd_sf.vhd
--
-- Description:
-- This file implements the AXI DataMover Read (MM2S) Store and Forward module.
-- The design utilizes the AXI DataMover's new address pipelining
-- control function. The design is such that predictive address
-- pipelining can be supported on the AXI Read Bus without over-commiting
-- the internal Data FIFO and potentially throttling the Read Data Channel
-- if the Data FIFO goes full.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library lib_pkg_v1_0_2;
use lib_pkg_v1_0_2.lib_pkg.all;
use lib_pkg_v1_0_2.lib_pkg.clog2;
library axi_datamover_v5_1_9;
use axi_datamover_v5_1_9.axi_datamover_sfifo_autord;
use axi_datamover_v5_1_9.axi_datamover_fifo;
-------------------------------------------------------------------------------
entity axi_datamover_rd_sf is
generic (
C_SF_FIFO_DEPTH : Integer range 128 to 8192 := 512;
-- Sets the desired depth of the internal Data FIFO.
C_MAX_BURST_LEN : Integer range 2 to 256 := 16;
-- Indicates the max burst length being used by the external
-- AXI4 Master for each AXI4 transfer request.
C_DRE_IS_USED : Integer range 0 to 1 := 0;
-- Indicates if the external Master is utilizing a DRE on
-- the stream input to this module.
C_DRE_CNTL_FIFO_DEPTH : Integer range 1 to 32 := 1;
-- Specifies the depth of the internal dre control queue fifo
C_DRE_ALIGN_WIDTH : Integer range 1 to 3 := 2;
-- Sets the width of the DRE alignment control ports
C_MMAP_DWIDTH : Integer range 32 to 1024 := 64;
-- Sets the AXI4 Memory Mapped Bus Data Width
C_STREAM_DWIDTH : Integer range 8 to 1024 := 32;
-- Sets the Stream Data Width for the Input and Output
-- Data streams.
C_STRT_SF_OFFSET_WIDTH : Integer range 1 to 7 := 2;
-- Sets the bit width of the starting address offset port
-- This should be set to log2(C_MMAP_DWIDTH/C_STREAM_DWIDTH)
C_ENABLE_MM2S_TKEEP : integer range 0 to 1 := 1;
C_TAG_WIDTH : Integer range 1 to 8 := 4;
-- Indicates the width of the Tag field of the input DRE command
C_FAMILY : String := "virtex7"
-- Indicates the target FPGA Family.
);
port (
-- Clock and Reset inputs --------------------------------------------
--
aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- Reset input --
reset : in std_logic; --
-- Reset used for the internal syncronization logic --
----------------------------------------------------------------------
-- DataMover Read Side Address Pipelining Control Interface ----------
--
ok_to_post_rd_addr : Out Std_logic; --
-- Indicates that the transfer token pool has at least --
-- one token available to borrow --
--
rd_addr_posted : In std_logic; --
-- Indication that a read address has been posted to AXI4 --
--
rd_xfer_cmplt : In std_logic; --
-- Indicates that the Datamover has completed a Read Data --
-- transfer on the AXI4 --
----------------------------------------------------------------------
-- Read Side Stream In from DataMover MM2S Read Data Controller ----------------------
--
sf2sin_tready : Out Std_logic; --
-- DRE Stream READY input --
--
sin2sf_tvalid : In std_logic; --
-- DRE Stream VALID Output --
--
sin2sf_tdata : In std_logic_vector(C_MMAP_DWIDTH-1 downto 0); --
-- DRE Stream DATA input --
--
sin2sf_tkeep : In std_logic_vector((C_MMAP_DWIDTH/8)-1 downto 0); --
-- DRE Stream STRB input --
--
sin2sf_tlast : In std_logic; --
-- DRE Xfer LAST input --
--------------------------------------------------------------------------------------
-- RDC Store and Forward Supplimental Controls ---------------------
-- These are time aligned and qualified with the RDC Stream Input --
--
data2sf_cmd_cmplt : In std_logic; --
data2sf_dre_flush : In std_logic; --
--------------------------------------------------------------------
-- DRE Control Interface from the Command Calculator -----------------------------
--
dre2mstr_cmd_ready : Out std_logic ; --
-- Indication from the DRE that the command is being --
-- accepted from the Command Calculator --
--
mstr2dre_cmd_valid : In std_logic; --
-- The next command valid indication to the DRE --
-- from the Command Calculator --
--
mstr2dre_tag : In std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The next command tag --
--
mstr2dre_dre_src_align : In std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0); --
-- The source (input) alignment for the DRE --
--
mstr2dre_dre_dest_align : In std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0); --
-- The destinstion (output) alignment for the DRE --
--
-- mstr2dre_btt : In std_logic_vector(C_BTT_USED-1 downto 0); --
-- -- The bytes to transfer value for the input command --
--
mstr2dre_drr : In std_logic; --
-- The starting tranfer of a sequence of transfers --
--
mstr2dre_eof : In std_logic; --
-- The endiing tranfer of a sequence of transfers --
--
-- mstr2dre_cmd_cmplt : In std_logic; --
-- -- The last tranfer command of a sequence of transfers --
-- -- spawned from a single parent command --
--
mstr2dre_calc_error : In std_logic; --
-- Indication if the next command in the calculation pipe --
-- has a calculation error --
--
mstr2dre_strt_offset : In std_logic_vector(C_STRT_SF_OFFSET_WIDTH-1 downto 0);--
-- Outputs the starting offset of a transfer. This is used with Store --
-- and Forward Packer/Unpacker logic --
-----------------------------------------------------------------------------------
-- MM2S DRE Control -------------------------------------------------------------
--
sf2dre_new_align : Out std_logic; --
-- Active high signal indicating new DRE aligment required --
--
sf2dre_use_autodest : Out std_logic; --
-- Active high signal indicating to the DRE to use an auto- --
-- calculated desination alignment based on the last transfer --
--
sf2dre_src_align : Out std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0); --
-- Bit field indicating the byte lane of the first valid data byte --
-- being sent to the DRE --
--
sf2dre_dest_align : Out std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0); --
-- Bit field indicating the desired byte lane of the first valid data byte --
-- to be output by the DRE --
--
sf2dre_flush : Out std_logic; --
-- Active high signal indicating to the DRE to flush the current --
-- contents to the output register in preparation of a new alignment --
-- that will be comming on the next transfer input --
---------------------------------------------------------------------------------
-- Stream Out -----------------------------------------------------------------------
--
sout2sf_tready : In std_logic; --
-- Write READY input from the Stream Master --
--
sf2sout_tvalid : Out std_logic; --
-- Write VALID output to the Stream Master --
--
sf2sout_tdata : Out std_logic_vector(C_STREAM_DWIDTH-1 downto 0); --
-- Write DATA output to the Stream Master --
--
sf2sout_tkeep : Out std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- Write DATA output to the Stream Master --
--
sf2sout_tlast : Out std_logic --
-- Write LAST output to the Stream Master --
--------------------------------------------------------------------------------------
);
end entity axi_datamover_rd_sf;
architecture implementation of axi_datamover_rd_sf is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Functions ---------------------------------------------------------------------------
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_fifo_cnt_width
--
-- Function Description:
-- simple function to set the width of the data fifo read
-- and write count outputs.
-------------------------------------------------------------------
function funct_get_fifo_cnt_width (fifo_depth : integer)
return integer is
Variable temp_width : integer := 8;
begin
if (fifo_depth = 1) then
temp_width := 1;
elsif (fifo_depth = 2) then
temp_width := 2;
elsif (fifo_depth <= 4) then
temp_width := 3;
elsif (fifo_depth <= 8) then
temp_width := 4;
elsif (fifo_depth <= 16) then
temp_width := 5;
elsif (fifo_depth <= 32) then
temp_width := 6;
elsif (fifo_depth <= 64) then
temp_width := 7;
elsif (fifo_depth <= 128) then
temp_width := 8;
elsif (fifo_depth <= 256) then
temp_width := 9;
elsif (fifo_depth <= 512) then
temp_width := 10;
elsif (fifo_depth <= 1024) then
temp_width := 11;
elsif (fifo_depth <= 2048) then
temp_width := 12;
elsif (fifo_depth <= 4096) then
temp_width := 13;
else -- assume 8192 depth
temp_width := 14;
end if;
Return (temp_width);
end function funct_get_fifo_cnt_width;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_wrcnt_lsrip
--
-- Function Description:
-- Calculates the ls index of the upper slice of the data fifo
-- write count needed to repesent one max burst worth of data
-- present in the fifo.
--
-------------------------------------------------------------------
function funct_get_wrcnt_lsrip (max_burst_dbeats : integer) return integer is
Variable temp_ls_index : Integer := 0;
begin
if (max_burst_dbeats <= 2) then
temp_ls_index := 1;
elsif (max_burst_dbeats <= 4) then
temp_ls_index := 2;
elsif (max_burst_dbeats <= 8) then
temp_ls_index := 3;
elsif (max_burst_dbeats <= 16) then
temp_ls_index := 4;
elsif (max_burst_dbeats <= 32) then
temp_ls_index := 5;
elsif (max_burst_dbeats <= 64) then
temp_ls_index := 6;
elsif (max_burst_dbeats <= 128) then
temp_ls_index := 7;
else
temp_ls_index := 8;
end if;
Return (temp_ls_index);
end function funct_get_wrcnt_lsrip;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_stall_thresh
--
-- Function Description:
-- Calculates the Stall threshold for the input side of the Data
-- FIFO. If DRE is being used by the DataMover, then the threshold
-- must be reduced to account for the potential of an extra write
-- databeat per request (DRE alignment dependent).
--
-------------------------------------------------------------------
function funct_get_stall_thresh (dre_is_used : integer;
max_xfer_length : integer;
data_fifo_depth : integer;
pipeline_delay_clks : integer;
fifo_settling_clks : integer) return integer is
Constant DRE_PIPE_DELAY : integer := 2; -- clks
Variable var_num_max_xfers_allowed : Integer := 0;
Variable var_dre_dbeat_overhead : Integer := 0;
Variable var_delay_fudge_factor : Integer := 0;
Variable var_thresh_headroom : Integer := 0;
Variable var_stall_thresh : Integer := 0;
begin
var_num_max_xfers_allowed := data_fifo_depth/max_xfer_length;
var_dre_dbeat_overhead := var_num_max_xfers_allowed * dre_is_used;
var_delay_fudge_factor := (dre_is_used * DRE_PIPE_DELAY) +
pipeline_delay_clks +
fifo_settling_clks;
var_thresh_headroom := max_xfer_length +
var_dre_dbeat_overhead +
var_delay_fudge_factor;
-- Scale the result to be in max transfer length increments
var_stall_thresh := (data_fifo_depth - var_thresh_headroom)/max_xfer_length;
Return (var_stall_thresh);
end function funct_get_stall_thresh;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_size_drecntl_fifo
--
-- Function Description:
-- Assures that the DRE control fifo depth is at least 4 deep else it
-- is equal to the number of max burst transfers that can fit in the
-- Store and Forward Data FIFO.
--
-------------------------------------------------------------------
function funct_size_drecntl_fifo (sf_fifo_depth : integer;
max_burst_length : integer) return integer is
Constant NEEDED_FIFO_DEPTH : integer := sf_fifo_depth/max_burst_length;
Variable temp_fifo_depth : Integer := 4;
begin
If (NEEDED_FIFO_DEPTH < 4) Then
temp_fifo_depth := 4;
Else
temp_fifo_depth := NEEDED_FIFO_DEPTH;
End if;
Return (temp_fifo_depth);
end function funct_size_drecntl_fifo;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_cntr_width
--
-- Function Description:
-- Detirmine the width needed for the address offset counter used
-- for the data fifo mux selects.
--
-------------------------------------------------------------------
function funct_get_cntr_width (num_count_states : integer) return integer is
Variable lvar_temp_width : Integer := 1;
begin
if (num_count_states <= 2) then
lvar_temp_width := 1;
elsif (num_count_states <= 4) then
lvar_temp_width := 2;
elsif (num_count_states <= 8) then
lvar_temp_width := 3;
elsif (num_count_states <= 16) then
lvar_temp_width := 4;
elsif (num_count_states <= 32) then
lvar_temp_width := 5;
elsif (num_count_states <= 64) then
lvar_temp_width := 6;
Else -- 128 cnt states
lvar_temp_width := 7;
end if;
Return (lvar_temp_width);
end function funct_get_cntr_width;
-- Constants ---------------------------------------------------------------------------
Constant LOGIC_LOW : std_logic := '0';
Constant LOGIC_HIGH : std_logic := '1';
Constant BLK_MEM_FIFO : integer := 1;
Constant SRL_FIFO : integer := 0;
Constant NOT_NEEDED : integer := 0;
Constant MMAP_TKEEP_WIDTH : integer := C_MMAP_DWIDTH/8; -- bits
Constant TLAST_WIDTH : integer := 1; -- bits
Constant CMPLT_WIDTH : integer := 1; -- bits
Constant DRE_FLUSH_WIDTH : integer := 1; -- bits
Constant DATA_FIFO_DEPTH : integer := C_SF_FIFO_DEPTH;
Constant DATA_FIFO_CNT_WIDTH : integer := funct_get_fifo_cnt_width(DATA_FIFO_DEPTH);
Constant DF_WRCNT_RIP_LS_INDEX : integer := funct_get_wrcnt_lsrip(C_MAX_BURST_LEN);
Constant DATA_FIFO_WIDTH : integer := C_MMAP_DWIDTH +
MMAP_TKEEP_WIDTH*C_ENABLE_MM2S_TKEEP +
TLAST_WIDTH +
CMPLT_WIDTH +
DRE_FLUSH_WIDTH;
Constant DATA_OUT_LSB_INDEX : integer := 0;
Constant DATA_OUT_MSB_INDEX : integer := C_MMAP_DWIDTH-1;
Constant TKEEP_OUT_LSB_INDEX : integer := DATA_OUT_MSB_INDEX+1;
Constant TKEEP_OUT_MSB_INDEX : integer := (TKEEP_OUT_LSB_INDEX+MMAP_TKEEP_WIDTH*C_ENABLE_MM2S_TKEEP)-1*C_ENABLE_MM2S_TKEEP;
Constant TLAST_OUT_INDEX : integer := TKEEP_OUT_MSB_INDEX+1*C_ENABLE_MM2S_TKEEP;
Constant CMPLT_OUT_INDEX : integer := TLAST_OUT_INDEX+1;
Constant DRE_FLUSH_OUT_INDEX : integer := CMPLT_OUT_INDEX+1;
Constant TOKEN_POOL_SIZE : integer := C_SF_FIFO_DEPTH / C_MAX_BURST_LEN;
Constant TOKEN_CNTR_WIDTH : integer := clog2(TOKEN_POOL_SIZE)+1;
Constant TOKEN_CNT_ZERO : Unsigned(TOKEN_CNTR_WIDTH-1 downto 0) :=
TO_UNSIGNED(0, TOKEN_CNTR_WIDTH);
Constant TOKEN_CNT_ONE : Unsigned(TOKEN_CNTR_WIDTH-1 downto 0) :=
TO_UNSIGNED(1, TOKEN_CNTR_WIDTH);
Constant TOKEN_CNT_MAX : Unsigned(TOKEN_CNTR_WIDTH-1 downto 0) :=
TO_UNSIGNED(TOKEN_POOL_SIZE, TOKEN_CNTR_WIDTH);
Constant THRESH_COMPARE_WIDTH : integer := TOKEN_CNTR_WIDTH+2;
Constant RD_PATH_PIPE_DEPTH : integer := 2; -- clocks excluding DRE
Constant WRCNT_SETTLING_TIME : integer := 2; -- data fifo push or pop settling clocks
Constant DRE_COMPENSATION : integer := 0; -- DRE does not contribute since it is on
-- the output side of the Store and Forward
Constant RD_ADDR_POST_STALL_THRESH : integer :=
funct_get_stall_thresh(DRE_COMPENSATION ,
C_MAX_BURST_LEN ,
C_SF_FIFO_DEPTH ,
RD_PATH_PIPE_DEPTH ,
WRCNT_SETTLING_TIME);
Constant RD_ADDR_POST_STALL_THRESH_US : Unsigned(THRESH_COMPARE_WIDTH-1 downto 0) :=
TO_UNSIGNED(RD_ADDR_POST_STALL_THRESH ,
THRESH_COMPARE_WIDTH);
Constant UNCOM_WRCNT_1 : Unsigned(DATA_FIFO_CNT_WIDTH-1 downto 0) :=
TO_UNSIGNED(1, DATA_FIFO_CNT_WIDTH);
Constant UNCOM_WRCNT_0 : Unsigned(DATA_FIFO_CNT_WIDTH-1 downto 0) :=
TO_UNSIGNED(0, DATA_FIFO_CNT_WIDTH);
Constant USE_SYNC_FIFO : integer := 0;
Constant SRL_FIFO_PRIM : integer := 2;
Constant TAG_WIDTH : integer := C_TAG_WIDTH;
Constant SRC_ALIGN_WIDTH : integer := C_DRE_ALIGN_WIDTH;
Constant DEST_ALIGN_WIDTH : integer := C_DRE_ALIGN_WIDTH;
Constant DRR_WIDTH : integer := 1;
Constant EOF_WIDTH : integer := 1;
Constant CALC_ERR_WIDTH : integer := 1;
Constant SF_OFFSET_WIDTH : integer := C_STRT_SF_OFFSET_WIDTH;
-- Signals ---------------------------------------------------------------------------
signal sig_good_sin_strm_dbeat : std_logic := '0';
signal sig_strm_sin_ready : std_logic := '0';
signal sig_good_sout_strm_dbeat : std_logic := '0';
signal sig_sout2sf_tready : std_logic := '0';
signal sig_sf2sout_tvalid : std_logic := '0';
signal sig_sf2sout_tdata : std_logic_vector(C_STREAM_DWIDTH-1 downto 0) := (others => '0');
signal sig_sf2sout_tkeep : std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0) := (others => '0');
signal sig_sf2sout_tlast : std_logic := '0';
signal sig_sf2dre_flush : std_logic := '0';
signal sig_push_data_fifo : std_logic := '0';
signal sig_pop_data_fifo : std_logic := '0';
signal sig_data_fifo_full : std_logic := '0';
signal sig_data_fifo_data_in : std_logic_vector(DATA_FIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_data_fifo_dvalid : std_logic := '0';
signal sig_data_fifo_data_out : std_logic_vector(DATA_FIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_data_fifo_wr_cnt : std_logic_vector(DATA_FIFO_CNT_WIDTH-1 downto 0) := (others => '0');
signal sig_fifo_wr_cnt_unsgnd : unsigned(DATA_FIFO_CNT_WIDTH-1 downto 0) := (others => '0');
signal sig_wrcnt_mblen_slice : unsigned(DATA_FIFO_CNT_WIDTH-1 downto
DF_WRCNT_RIP_LS_INDEX) := (others => '0');
signal sig_ok_to_post_rd_addr : std_logic := '0';
signal sig_rd_addr_posted : std_logic := '0';
signal sig_rd_xfer_cmplt : std_logic := '0';
signal sig_taking_last_token : std_logic := '0';
signal sig_stall_rd_addr_posts : std_logic := '0';
signal sig_incr_token_cntr : std_logic := '0';
signal sig_decr_token_cntr : std_logic := '0';
signal sig_token_eq_max : std_logic := '0';
signal sig_token_eq_zero : std_logic := '0';
signal sig_token_eq_one : std_logic := '0';
signal sig_token_cntr : Unsigned(TOKEN_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_tokens_commited : Unsigned(TOKEN_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_commit_plus_actual : unsigned(THRESH_COMPARE_WIDTH-1 downto 0) := (others => '0');
signal sig_cntl_fifo_has_data : std_logic := '0';
signal sig_get_cntl_fifo_data : std_logic := '0';
signal sig_curr_tag_reg : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_curr_src_align_reg : std_logic_vector(SRC_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_curr_dest_align_reg : std_logic_vector(DEST_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_curr_drr_reg : std_logic := '0';
signal sig_curr_eof_reg : std_logic := '0';
signal sig_curr_calc_error_reg : std_logic := '0';
signal sig_curr_strt_offset_reg : std_logic_vector(SF_OFFSET_WIDTH-1 downto 0) := (others => '0');
signal sig_ld_dre_cntl_reg : std_logic := '0';
signal sig_dfifo_data_out : std_logic_vector(C_MMAP_DWIDTH-1 downto 0) := (others => '0');
signal sig_dfifo_tkeep_out : std_logic_vector(MMAP_TKEEP_WIDTH-1 downto 0) := (others => '0');
signal sig_dfifo_tlast_out : std_logic := '0';
signal sig_dfifo_cmd_cmplt_out : std_logic := '0';
signal sig_dfifo_dre_flush_out : std_logic := '0';
begin --(architecture implementation)
-- Read Side (MM2S) Control Flags port connections
ok_to_post_rd_addr <= sig_ok_to_post_rd_addr ;
sig_rd_addr_posted <= rd_addr_posted ;
sig_rd_xfer_cmplt <= rd_xfer_cmplt ;
-- Output Stream Port connections
sig_sout2sf_tready <= sout2sf_tready ;
sf2sout_tvalid <= sig_sf2sout_tvalid ;
sf2sout_tdata <= sig_sf2sout_tdata ;
--sf2sout_tkeep <= sig_sf2sout_tkeep ;
sf2sout_tlast <= sig_sf2sout_tlast and
sig_sf2sout_tvalid ;
GEN_MM2S_TKEEP_ENABLE4 : if C_ENABLE_MM2S_TKEEP = 1 generate
begin
sf2sout_tkeep <= sig_sf2sout_tkeep ;
end generate GEN_MM2S_TKEEP_ENABLE4;
GEN_MM2S_TKEEP_DISABLE4 : if C_ENABLE_MM2S_TKEEP = 0 generate
begin
sf2sout_tkeep <= (others => '1');
end generate GEN_MM2S_TKEEP_DISABLE4;
-- Input Stream port connections
sf2sin_tready <= sig_strm_sin_ready;
sig_strm_sin_ready <= not(sig_data_fifo_full); -- Throttle if Read Side Data fifo goes full.
-- This should never happen if read address
-- posting control is working properly.
-- Stream transfer qualifiers
sig_good_sin_strm_dbeat <= sin2sf_tvalid and
sig_strm_sin_ready;
sig_good_sout_strm_dbeat <= sig_sf2sout_tvalid and
sig_sout2sf_tready;
----------------------------------------------------------------
-- Unpacking Logic ------------------------------------------
----------------------------------------------------------------
------------------------------------------------------------
-- If Generate
--
-- Label: OMIT_UNPACKING
--
-- If Generate Description:
-- Omits any unpacking logic in the Store and Forward module.
-- The Stream and MMap data widths are the same. The Data FIFO
-- output can be connected directly to the stream outputs.
--
------------------------------------------------------------
OMIT_UNPACKING : if (C_MMAP_DWIDTH = C_STREAM_DWIDTH) generate
signal lsig_cmd_loaded : std_logic := '0';
signal lsig_ld_cmd : std_logic := '0';
signal lsig_cmd_cmplt_dbeat : std_logic := '0';
signal lsig_cmd_cmplt : std_logic := '0';
begin
-- Data FIFO Output to the stream attachments
sig_sf2sout_tvalid <= sig_data_fifo_dvalid and
lsig_cmd_loaded ;
sig_sf2sout_tdata <= sig_dfifo_data_out ;
sig_sf2sout_tkeep <= sig_dfifo_tkeep_out ;
sig_sf2sout_tlast <= sig_dfifo_tlast_out ;
sig_sf2dre_flush <= sig_dfifo_dre_flush_out ;
-- Control for reading the Data FIFO
sig_pop_data_fifo <= lsig_cmd_loaded and
sig_sout2sf_tready and
sig_data_fifo_dvalid;
-- Control for reading the Command/Offset FIFO
sig_get_cntl_fifo_data <= lsig_ld_cmd ;
-- Control for loading the DRE Control Reg
sig_ld_dre_cntl_reg <= lsig_ld_cmd ;
lsig_cmd_cmplt_dbeat <= sig_dfifo_cmd_cmplt_out and
lsig_cmd_loaded and
sig_data_fifo_dvalid and
sig_sout2sf_tready ;
-- Generate the control that loads the DRE
lsig_ld_cmd <= (sig_cntl_fifo_has_data and -- startup or gap case
not(lsig_cmd_loaded)) or
(sig_cntl_fifo_has_data and -- back to back commands
lsig_cmd_cmplt_dbeat);
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_CMD_LOADED
--
-- Process Description:
-- Implements the flop indicating a command from the cmd fifo
-- has been loaded into the DRE Output Register.
--
-------------------------------------------------------------
IMP_CMD_LOADED : process (aclk)
begin
if (aclk'event and aclk = '1') then
if (reset = '1') then
lsig_cmd_loaded <= '0';
Elsif (lsig_ld_cmd = '1' ) Then
lsig_cmd_loaded <= '1';
elsif (sig_cntl_fifo_has_data = '0' and -- No more commands queued and
lsig_cmd_cmplt_dbeat = '1') then
lsig_cmd_loaded <= '0';
else
null; -- Hold Current State
end if;
end if;
end process IMP_CMD_LOADED;
end generate OMIT_UNPACKING;
------------------------------------------------------------
-- If Generate
--
-- Label: INCLUDE_UNPACKING
--
-- If Generate Description:
-- Includes unpacking logic in the Store and Forward module.
-- The MMap Data bus is wider than the Stream width.
--
------------------------------------------------------------
INCLUDE_UNPACKING : if (C_MMAP_DWIDTH > C_STREAM_DWIDTH) generate
Constant MMAP2STRM_WIDTH_RATO : integer := C_MMAP_DWIDTH/C_STREAM_DWIDTH;
Constant DATA_SLICE_WIDTH : integer := C_STREAM_DWIDTH;
Constant TKEEP_SLICE_WIDTH : integer := C_STREAM_DWIDTH/8;
Constant FLAG_SLICE_WIDTH : integer := TLAST_WIDTH;
Constant OFFSET_CNTR_WIDTH : integer := funct_get_cntr_width(MMAP2STRM_WIDTH_RATO);
Constant OFFSET_CNT_ONE : unsigned(OFFSET_CNTR_WIDTH-1 downto 0) :=
TO_UNSIGNED(1, OFFSET_CNTR_WIDTH);
Constant OFFSET_CNT_MAX : unsigned(OFFSET_CNTR_WIDTH-1 downto 0) :=
TO_UNSIGNED(MMAP2STRM_WIDTH_RATO-1, OFFSET_CNTR_WIDTH);
-- Types -----------------------------------------------------------------------------
type lsig_data_slice_type is array(MMAP2STRM_WIDTH_RATO-1 downto 0) of
std_logic_vector(DATA_SLICE_WIDTH-1 downto 0);
type lsig_tkeep_slice_type is array(MMAP2STRM_WIDTH_RATO downto 0) of
std_logic_vector(TKEEP_SLICE_WIDTH-1 downto 0);
type lsig_flag_slice_type is array(MMAP2STRM_WIDTH_RATO-1 downto 0) of
std_logic_vector(FLAG_SLICE_WIDTH-1 downto 0);
-- local signals
signal lsig_0ffset_cntr : unsigned(OFFSET_CNTR_WIDTH-1 downto 0) := (others => '0');
signal lsig_ld_offset : std_logic := '0';
signal lsig_incr_offset : std_logic := '0';
signal lsig_offset_cntr_eq_max : std_logic := '0';
signal lsig_fifo_data_out_wide : lsig_data_slice_type;
signal lsig_fifo_tkeep_out_wide : lsig_tkeep_slice_type;
signal lsig_mux_sel : integer range 0 to MMAP2STRM_WIDTH_RATO-1;
signal lsig_data_mux_out : std_logic_vector(DATA_SLICE_WIDTH-1 downto 0) ;
signal lsig_tkeep_mux_out : std_logic_vector(TKEEP_SLICE_WIDTH-1 downto 0);
signal lsig_tlast_out : std_logic := '0';
signal lsig_dre_flush_out : std_logic := '0';
signal lsig_this_fifo_wrd_done : std_logic := '0';
signal lsig_cmd_loaded : std_logic := '0';
signal lsig_cmd_cmplt_dbeat : std_logic := '0';
signal lsig_cmd_cmplt : std_logic := '0';
signal lsig_next_slice_tkeep_0 : std_logic := '0';
begin
sig_sf2sout_tvalid <= sig_data_fifo_dvalid and
lsig_cmd_loaded ;
sig_sf2sout_tdata <= lsig_data_mux_out ;
sig_sf2sout_tkeep <= lsig_tkeep_mux_out(TKEEP_SLICE_WIDTH-1 downto 0);
sig_sf2sout_tlast <= lsig_tlast_out ;
sig_sf2dre_flush <= lsig_dre_flush_out ;
-- Control for reading the Data FIFO
sig_pop_data_fifo <= lsig_this_fifo_wrd_done and
lsig_cmd_loaded and
sig_sout2sf_tready and
sig_data_fifo_dvalid;
-- Control for reading the Command/Offset FIFO
sig_get_cntl_fifo_data <= lsig_ld_offset;
-- Control for loading the DRE Control Reg
sig_ld_dre_cntl_reg <= lsig_ld_offset ;
lsig_next_slice_tkeep_0 <= lsig_fifo_tkeep_out_wide(lsig_mux_sel+1)(0);
-- Detirmine if a Command Complete condition exists
lsig_cmd_cmplt <= '1'
when (sig_dfifo_cmd_cmplt_out = '1' and
lsig_next_slice_tkeep_0 = '0')
Else '0';
-- Detirmine if a TLAST condition exists
-- From the RDC via the Data FIFO
lsig_tlast_out <= '1'
when (sig_dfifo_tlast_out = '1' and
lsig_next_slice_tkeep_0 = '0')
Else '0';
-- Detimine if a DRE Flush condition exists
-- From the RDC via the Data FIFO
lsig_dre_flush_out <= '1'
when (sig_dfifo_dre_flush_out = '1' and
lsig_next_slice_tkeep_0 = '0')
Else '0';
lsig_cmd_cmplt_dbeat <= lsig_cmd_cmplt and
lsig_cmd_loaded and
sig_data_fifo_dvalid and
sig_sout2sf_tready ;
-- Check to see if the FIFO output word is finished. This occurs
-- when the offset counter is at max value or the tlast from the
-- fifo is set and the LS TKEED of the next MS Slice is zero.
lsig_this_fifo_wrd_done <= '1'
When (lsig_offset_cntr_eq_max = '1' or
(lsig_cmd_cmplt_dbeat = '1' and
lsig_next_slice_tkeep_0 = '0'))
Else '0';
-- Generate the control that loads the starting address
-- offset for the next input packet
lsig_ld_offset <= (sig_cntl_fifo_has_data and -- startup or gap case
not(lsig_cmd_loaded)) or
(sig_cntl_fifo_has_data and -- back to back commands
lsig_cmd_cmplt_dbeat);
-- Generate the control for incrementing the offset counter
lsig_incr_offset <= sig_good_sout_strm_dbeat;
-- Check to see if the offset counter has reached its max
-- value
lsig_offset_cntr_eq_max <= '1'
when (lsig_0ffset_cntr = OFFSET_CNT_MAX)
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_CMD_LOADED
--
-- Process Description:
-- Implements the flop indicating a command from the cmd fifo
-- has been loaded into the unpacker control logic.
--
-------------------------------------------------------------
IMP_CMD_LOADED : process (aclk)
begin
if (aclk'event and aclk = '1') then
if (reset = '1') then
lsig_cmd_loaded <= '0';
Elsif (lsig_ld_offset = '1' ) Then
lsig_cmd_loaded <= '1';
elsif (sig_cntl_fifo_has_data = '0' and -- No more commands queued
lsig_cmd_cmplt_dbeat = '1') then
lsig_cmd_loaded <= '0';
else
null; -- Hold Current State
end if;
end if;
end process IMP_CMD_LOADED;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_OFFSET_CNTR
--
-- Process Description:
-- Implements the address offset counter that is used to
-- generate the data and tkeep mux selects.
-- Note that the counter has to be loaded with the starting
-- offset plus one to sync up with the data input.
-------------------------------------------------------------
IMP_OFFSET_CNTR : process (aclk)
begin
if (aclk'event and aclk = '1') then
if (reset = '1') then
lsig_0ffset_cntr <= (others => '0');
Elsif (lsig_ld_offset = '1') Then
lsig_0ffset_cntr <= UNSIGNED(sig_curr_strt_offset_reg);
elsif (lsig_incr_offset = '1') then
lsig_0ffset_cntr <= lsig_0ffset_cntr + OFFSET_CNT_ONE;
else
null; -- Hold Current State
end if;
end if;
end process IMP_OFFSET_CNTR;
------------------------------------------------------------
-- For Generate
--
-- Label: DO_DATA_CONVERTER
--
-- For Generate Description:
-- This ForGen converts the FIFO output data and tkeep from a single
-- std logic vector type to a vector of slices.
--
------------------------------------------------------------
DO_DATA_CONVERTER : for slice_index in 1 to MMAP2STRM_WIDTH_RATO generate
begin
lsig_fifo_data_out_wide(slice_index-1) <=
sig_dfifo_data_out((slice_index*DATA_SLICE_WIDTH)-1 downto
(slice_index-1)*DATA_SLICE_WIDTH);
lsig_fifo_tkeep_out_wide(slice_index-1) <=
sig_dfifo_tkeep_out((slice_index*TKEEP_SLICE_WIDTH)-1 downto
(slice_index-1)*TKEEP_SLICE_WIDTH);
end generate DO_DATA_CONVERTER;
-- Assign the extra tkeep slice to all zeros to allow for detection
-- of the data word done when the ls tkeep bit of the next tkeep
-- slice is zero and the offset count is pointing to the last slice
-- position.
lsig_fifo_tkeep_out_wide(MMAP2STRM_WIDTH_RATO) <= (others => '0');
-- Mux the appropriate data and tkeep slice to the stream output
lsig_mux_sel <= TO_INTEGER(lsig_0ffset_cntr);
lsig_data_mux_out <= lsig_fifo_data_out_wide(lsig_mux_sel) ;
lsig_tkeep_mux_out(TKEEP_SLICE_WIDTH-1 downto 0) <= lsig_fifo_tkeep_out_wide(lsig_mux_sel);
end generate INCLUDE_UNPACKING;
------------------------------------------------------------
-- If Generate
--
-- Label: OMIT_DRE_CNTL
--
-- If Generate Description:
-- This IfGen is used to omit the DRE control logic and
-- minimize the Control FIFO when MM2S DRE is not included
-- in the MM2S.
--
------------------------------------------------------------
OMIT_DRE_CNTL : if (C_DRE_IS_USED = 0) generate
-- Constant Declarations ------------------------------------------------------------------
Constant USE_SYNC_FIFO : integer := 0;
Constant SRL_FIFO_PRIM : integer := 2;
Constant TAG_WIDTH : integer := C_TAG_WIDTH;
Constant DRR_WIDTH : integer := 1;
Constant EOF_WIDTH : integer := 1;
Constant CALC_ERR_WIDTH : integer := 1;
Constant SF_OFFSET_WIDTH : integer := C_STRT_SF_OFFSET_WIDTH;
Constant SF_OFFSET_FIFO_DEPTH : integer := funct_size_drecntl_fifo(C_DRE_CNTL_FIFO_DEPTH,
C_MAX_BURST_LEN);
Constant SF_OFFSET_FIFO_WIDTH : Integer := TAG_WIDTH + -- Tag field
DRR_WIDTH + -- DRE Re-alignment Request Flag Field
EOF_WIDTH + -- EOF flag field
CALC_ERR_WIDTH + -- Calc error flag
SF_OFFSET_WIDTH; -- Store and Forward Offset
Constant TAG_STRT_INDEX : integer := 0;
Constant DRR_STRT_INDEX : integer := TAG_STRT_INDEX + TAG_WIDTH;
Constant EOF_STRT_INDEX : integer := DRR_STRT_INDEX + DRR_WIDTH;
Constant CALC_ERR_STRT_INDEX : integer := EOF_STRT_INDEX + EOF_WIDTH;
Constant SF_OFFSET_STRT_INDEX : integer := CALC_ERR_STRT_INDEX+CALC_ERR_WIDTH;
-- Signal Declarations --------------------------------------------------------------------
signal sig_offset_fifo_data_in : std_logic_vector(SF_OFFSET_FIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_offset_fifo_data_out : std_logic_vector(SF_OFFSET_FIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_offset_fifo_wr_valid : std_logic := '0';
signal sig_offset_fifo_wr_ready : std_logic := '0';
signal sig_offset_fifo_rd_valid : std_logic := '0';
signal sig_offset_fifo_rd_ready : std_logic := '0';
begin
-- PCC DRE Command interface handshake
dre2mstr_cmd_ready <= sig_offset_fifo_wr_ready ;
sig_offset_fifo_wr_valid <= mstr2dre_cmd_valid ;
-- No DRE so no controls
sf2dre_new_align <= '0';
sf2dre_use_autodest <= '0';
sf2dre_src_align <= (others => '0');
sf2dre_dest_align <= (others => '0');
sf2dre_flush <= '0';
-- No DRE so no alignment values
sig_curr_src_align_reg <= (others => '0');
sig_curr_dest_align_reg <= (others => '0');
-- Format the input data word for the Offset FIFO Queue
sig_offset_fifo_data_in <= mstr2dre_strt_offset & -- MS field
mstr2dre_calc_error &
mstr2dre_eof &
mstr2dre_drr &
mstr2dre_tag; -- LS Field
sig_cntl_fifo_has_data <= sig_offset_fifo_rd_valid ;
sig_offset_fifo_rd_ready <= sig_get_cntl_fifo_data ;
-- Rip the output fifo data word
sig_curr_tag_reg <= sig_offset_fifo_data_out((TAG_STRT_INDEX+TAG_WIDTH)-1 downto TAG_STRT_INDEX);
sig_curr_drr_reg <= sig_offset_fifo_data_out(DRR_STRT_INDEX);
sig_curr_eof_reg <= sig_offset_fifo_data_out(EOF_STRT_INDEX);
sig_curr_calc_error_reg <= sig_offset_fifo_data_out(CALC_ERR_STRT_INDEX);
sig_curr_strt_offset_reg <= sig_offset_fifo_data_out((SF_OFFSET_STRT_INDEX+SF_OFFSET_WIDTH)-1 downto
SF_OFFSET_STRT_INDEX);
------------------------------------------------------------
-- Instance: I_DRE_CNTL_FIFO
--
-- Description:
-- Instance for the Offset Control FIFO. This is still needed
-- by the unpacker logic to get the starting offset at the
-- begining of an input packet coming out of the Store and
-- Forward data FIFO.
--
------------------------------------------------------------
I_DRE_CNTL_FIFO : entity axi_datamover_v5_1_9.axi_datamover_fifo
generic map (
C_DWIDTH => SF_OFFSET_FIFO_WIDTH ,
C_DEPTH => SF_OFFSET_FIFO_DEPTH ,
C_IS_ASYNC => USE_SYNC_FIFO ,
C_PRIM_TYPE => SRL_FIFO_PRIM ,
C_FAMILY => C_FAMILY
)
port map (
-- Write Clock and reset
fifo_wr_reset => reset ,
fifo_wr_clk => aclk ,
-- Write Side
fifo_wr_tvalid => sig_offset_fifo_wr_valid ,
fifo_wr_tready => sig_offset_fifo_wr_ready ,
fifo_wr_tdata => sig_offset_fifo_data_in ,
fifo_wr_full => open ,
-- Read Clock and reset
fifo_async_rd_reset => aclk ,
fifo_async_rd_clk => reset ,
-- Read Side
fifo_rd_tvalid => sig_offset_fifo_rd_valid ,
fifo_rd_tready => sig_offset_fifo_rd_ready ,
fifo_rd_tdata => sig_offset_fifo_data_out ,
fifo_rd_empty => open
);
end generate OMIT_DRE_CNTL;
------------------------------------------------------------
-- If Generate
--
-- Label: INCLUDE_DRE_CNTL
--
-- If Generate Description:
-- This IfGen is used to include the DRE control logic and
-- Control FIFO when MM2S DRE is included in the MM2S.
--
--
------------------------------------------------------------
INCLUDE_DRE_CNTL : if (C_DRE_IS_USED = 1) generate
-- Constant Declarations
Constant DRECNTL_FIFO_DEPTH : integer := funct_size_drecntl_fifo(C_DRE_CNTL_FIFO_DEPTH,
C_MAX_BURST_LEN);
Constant DRECNTL_FIFO_WIDTH : Integer := TAG_WIDTH + -- Tag field
SRC_ALIGN_WIDTH + -- Source align field width
DEST_ALIGN_WIDTH + -- Dest align field width
DRR_WIDTH + -- DRE Re-alignment Request Flag Field
EOF_WIDTH + -- EOF flag field
CALC_ERR_WIDTH + -- Calc error flag
SF_OFFSET_WIDTH; -- Store and Forward Offset
Constant TAG_STRT_INDEX : integer := 0;
Constant SRC_ALIGN_STRT_INDEX : integer := TAG_STRT_INDEX + TAG_WIDTH;
Constant DEST_ALIGN_STRT_INDEX : integer := SRC_ALIGN_STRT_INDEX + SRC_ALIGN_WIDTH;
Constant DRR_STRT_INDEX : integer := DEST_ALIGN_STRT_INDEX + DEST_ALIGN_WIDTH;
Constant EOF_STRT_INDEX : integer := DRR_STRT_INDEX + DRR_WIDTH;
Constant CALC_ERR_STRT_INDEX : integer := EOF_STRT_INDEX + EOF_WIDTH;
Constant SF_OFFSET_STRT_INDEX : integer := CALC_ERR_STRT_INDEX+CALC_ERR_WIDTH;
signal sig_cmd_fifo_data_in : std_logic_vector(DRECNTL_FIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd_fifo_data_out : std_logic_vector(DRECNTL_FIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_fifo_wr_cmd_valid : std_logic := '0';
signal sig_fifo_wr_cmd_ready : std_logic := '0';
signal sig_fifo_rd_cmd_valid : std_logic := '0';
signal sig_fifo_rd_cmd_ready : std_logic := '0';
signal sig_dre_align_ready : std_logic := '0';
signal sig_dre_align_valid_reg : std_logic := '0';
signal sig_dre_use_autodest_reg : std_logic := '0';
signal sig_dre_src_align_reg : std_logic_vector(SRC_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_dre_dest_align_reg : std_logic_vector(DEST_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_dre_flush_reg : std_logic := '0';
begin
-- Assign the DRE Control Outputs
sf2dre_new_align <= sig_dre_align_valid_reg;
sf2dre_use_autodest <= sig_dre_use_autodest_reg;
sf2dre_src_align <= sig_dre_src_align_reg;
sf2dre_dest_align <= sig_dre_dest_align_reg;
sf2dre_flush <= sig_sf2dre_flush; -- from RDC via data FIFO
-- PCC DRE Command interface handshake
dre2mstr_cmd_ready <= sig_fifo_wr_cmd_ready;
sig_fifo_wr_cmd_valid <= mstr2dre_cmd_valid ;
-- Format the input data word for the DRE Control FIFO Queue
sig_cmd_fifo_data_in <= mstr2dre_strt_offset &
mstr2dre_calc_error &
mstr2dre_eof &
mstr2dre_drr &
mstr2dre_dre_dest_align &
mstr2dre_dre_src_align &
mstr2dre_tag;
-- Formulate the DRE Control FIFO Read signaling
sig_cntl_fifo_has_data <= sig_fifo_rd_cmd_valid ;
sig_fifo_rd_cmd_ready <= sig_get_cntl_fifo_data ;
-- Rip the output fifo data word
sig_curr_tag_reg <= sig_cmd_fifo_data_out((TAG_STRT_INDEX+TAG_WIDTH)-1 downto TAG_STRT_INDEX);
sig_curr_src_align_reg <= sig_cmd_fifo_data_out((SRC_ALIGN_STRT_INDEX+SRC_ALIGN_WIDTH)-1 downto
SRC_ALIGN_STRT_INDEX);
sig_curr_dest_align_reg <= sig_cmd_fifo_data_out((DEST_ALIGN_STRT_INDEX+DEST_ALIGN_WIDTH)-1 downto
DEST_ALIGN_STRT_INDEX);
sig_curr_drr_reg <= sig_cmd_fifo_data_out(DRR_STRT_INDEX);
sig_curr_eof_reg <= sig_cmd_fifo_data_out(EOF_STRT_INDEX);
sig_curr_calc_error_reg <= sig_cmd_fifo_data_out(CALC_ERR_STRT_INDEX);
sig_curr_strt_offset_reg <= sig_cmd_fifo_data_out((SF_OFFSET_STRT_INDEX+SF_OFFSET_WIDTH)-1 downto
SF_OFFSET_STRT_INDEX);
------------------------------------------------------------
-- Instance: I_DRE_CNTL_FIFO
--
-- Description:
-- Instance for the DRE Control FIFO
--
------------------------------------------------------------
I_DRE_CNTL_FIFO : entity axi_datamover_v5_1_9.axi_datamover_fifo
generic map (
C_DWIDTH => DRECNTL_FIFO_WIDTH ,
C_DEPTH => DRECNTL_FIFO_DEPTH ,
C_IS_ASYNC => USE_SYNC_FIFO ,
C_PRIM_TYPE => SRL_FIFO_PRIM ,
C_FAMILY => C_FAMILY
)
port map (
-- Write Clock and reset
fifo_wr_reset => reset ,
fifo_wr_clk => aclk ,
-- Write Side
fifo_wr_tvalid => sig_fifo_wr_cmd_valid ,
fifo_wr_tready => sig_fifo_wr_cmd_ready ,
fifo_wr_tdata => sig_cmd_fifo_data_in ,
fifo_wr_full => open ,
-- Read Clock and reset
fifo_async_rd_reset => aclk ,
fifo_async_rd_clk => reset ,
-- Read Side
fifo_rd_tvalid => sig_fifo_rd_cmd_valid ,
fifo_rd_tready => sig_fifo_rd_cmd_ready ,
fifo_rd_tdata => sig_cmd_fifo_data_out ,
fifo_rd_empty => open
);
-------------------------------------------------------------------------
-- DRE Control Register
-------------------------------------------------------------------------
-- The DRE will auto-flush on a received TLAST so a commanded Flush
-- is not needed.
sig_dre_flush_reg <= '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_CNTL_REG
--
-- Process Description:
-- Implements the DRE alignment Output Register.
--
-------------------------------------------------------------
IMP_CNTL_REG : process (aclk)
begin
if (aclk'event and aclk = '1') then
if (reset = '1') then
sig_dre_use_autodest_reg <= '0' ;
sig_dre_src_align_reg <= (others => '0') ;
sig_dre_dest_align_reg <= (others => '0') ;
Elsif (sig_ld_dre_cntl_reg = '1' ) Then
sig_dre_use_autodest_reg <= not(sig_curr_drr_reg) ;
sig_dre_src_align_reg <= sig_curr_src_align_reg ;
sig_dre_dest_align_reg <= sig_curr_dest_align_reg ;
Elsif (sig_good_sout_strm_dbeat = '1') Then
sig_dre_use_autodest_reg <= '0' ;
sig_dre_src_align_reg <= (others => '0') ;
sig_dre_dest_align_reg <= (others => '0') ;
else
null; -- Hold Current State
end if;
end if;
end process IMP_CNTL_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_DRE_CNTL_VALID_REG
--
-- Process Description:
-- Implements the DRE Alignment valid Register.
--
-------------------------------------------------------------
IMP_DRE_CNTL_VALID_REG : process (aclk)
begin
if (aclk'event and aclk = '1') then
if (reset = '1') then
sig_dre_align_valid_reg <= '0' ;
Elsif (sig_ld_dre_cntl_reg = '1' ) Then
sig_dre_align_valid_reg <= '1' ;
Elsif (sig_good_sout_strm_dbeat = '1') Then
sig_dre_align_valid_reg <= '0' ;
else
null; -- Hold Current State
end if;
end if;
end process IMP_DRE_CNTL_VALID_REG;
end generate INCLUDE_DRE_CNTL;
----------------------------------------------------------------
-- Token Counter Logic
-- Predicting fifo space availability at some point in the
-- future is based on managing a virtual pool of transfer tokens.
-- A token represents 1 max length burst worth of space in the
-- Data FIFO.
----------------------------------------------------------------
-- calculate how many tokens are commited to pending transfers
sig_tokens_commited <= TOKEN_CNT_MAX - sig_token_cntr;
-- Decrement the token counter when a token is
-- borrowed
sig_decr_token_cntr <= '1'
when (sig_rd_addr_posted = '1' and
sig_token_eq_zero = '0')
else '0';
-- Increment the token counter when a
-- token is returned.
sig_incr_token_cntr <= '1'
when (sig_rd_xfer_cmplt = '1' and
sig_token_eq_max = '0')
else '0';
-- Detect when the xfer token count is at max value
sig_token_eq_max <= '1'
when (sig_token_cntr = TOKEN_CNT_MAX)
Else '0';
-- Detect when the xfer token count is at one
sig_token_eq_one <= '1'
when (sig_token_cntr = TOKEN_CNT_ONE)
Else '0';
-- Detect when the xfer token count is at zero
sig_token_eq_zero <= '1'
when (sig_token_cntr = TOKEN_CNT_ZERO)
Else '0';
-- Look ahead to see if the xfer token pool is going empty
sig_taking_last_token <= '1'
When (sig_token_eq_one = '1' and
sig_rd_addr_posted = '1')
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_TOKEN_CNTR
--
-- Process Description:
-- Implements the Token counter
--
-------------------------------------------------------------
IMP_TOKEN_CNTR : process (aclk)
begin
if (aclk'event and aclk = '1') then
if (reset = '1' ) then
sig_token_cntr <= TOKEN_CNT_MAX;
elsif (sig_incr_token_cntr = '1' and
sig_decr_token_cntr = '0') then
sig_token_cntr <= sig_token_cntr + TOKEN_CNT_ONE;
elsif (sig_incr_token_cntr = '0' and
sig_decr_token_cntr = '1') then
sig_token_cntr <= sig_token_cntr - TOKEN_CNT_ONE;
else
null; -- hold current value
end if;
end if;
end process IMP_TOKEN_CNTR;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_TOKEN_AVAIL_FLAG
--
-- Process Description:
-- Implements the flag indicating that the AXI Read Master
-- can post a read address request on the AXI4 bus.
--
-- Read address posting can occur if:
--
-- - The write side LEN fifo is not empty.
-- - The commited plus actual Data FIFO space is less than
-- the stall threshold (a max length read burst can fit
-- in the data FIFO without overflow).
-- - The max allowed commited read count has not been reached.
--
-- The flag is cleared after each address has been posted to
-- ensure a second unauthorized post does not occur.
-------------------------------------------------------------
IMP_TOKEN_AVAIL_FLAG : process (aclk)
begin
if (aclk'event and aclk = '1') then
if (reset = '1' or
sig_rd_addr_posted = '1') then
sig_ok_to_post_rd_addr <= '0';
else
sig_ok_to_post_rd_addr <= not(sig_stall_rd_addr_posts) and -- the commited Data FIFO space is approaching full
not(sig_token_eq_zero) and -- max allowed pending reads has not been reached
not(sig_taking_last_token); -- the max allowed pending reads is about to be reached
end if;
end if;
end process IMP_TOKEN_AVAIL_FLAG;
----------------------------------------------------------------
-- Data FIFO Logic ------------------------------------------
----------------------------------------------------------------
GEN_MM2S_TKEEP_ENABLE3 : if C_ENABLE_MM2S_TKEEP = 1 generate
begin
-- FIFO Output ripping to components
sig_dfifo_data_out <= sig_data_fifo_data_out(DATA_OUT_MSB_INDEX downto
DATA_OUT_LSB_INDEX);
sig_dfifo_tkeep_out <= sig_data_fifo_data_out(TKEEP_OUT_MSB_INDEX downto
TKEEP_OUT_LSB_INDEX);
sig_dfifo_tlast_out <= sig_data_fifo_data_out(TLAST_OUT_INDEX) ;
sig_dfifo_cmd_cmplt_out <= sig_data_fifo_data_out(CMPLT_OUT_INDEX) ;
sig_dfifo_dre_flush_out <= sig_data_fifo_data_out(DRE_FLUSH_OUT_INDEX) ;
end generate GEN_MM2S_TKEEP_ENABLE3;
GEN_MM2S_TKEEP_DISABLE3 : if C_ENABLE_MM2S_TKEEP = 0 generate
begin
-- FIFO Output ripping to components
sig_dfifo_data_out <= sig_data_fifo_data_out(DATA_OUT_MSB_INDEX downto
DATA_OUT_LSB_INDEX);
sig_dfifo_tkeep_out <= (others => '1');
sig_dfifo_tlast_out <= sig_data_fifo_data_out(TLAST_OUT_INDEX) ;
sig_dfifo_cmd_cmplt_out <= sig_data_fifo_data_out(CMPLT_OUT_INDEX) ;
sig_dfifo_dre_flush_out <= sig_data_fifo_data_out(DRE_FLUSH_OUT_INDEX) ;
end generate GEN_MM2S_TKEEP_DISABLE3;
-- Stall Threshold calculations
sig_fifo_wr_cnt_unsgnd <= UNSIGNED(sig_data_fifo_wr_cnt);
sig_wrcnt_mblen_slice <= sig_fifo_wr_cnt_unsgnd(DATA_FIFO_CNT_WIDTH-1 downto
DF_WRCNT_RIP_LS_INDEX);
sig_commit_plus_actual <= RESIZE(sig_tokens_commited, THRESH_COMPARE_WIDTH) +
RESIZE(sig_wrcnt_mblen_slice, THRESH_COMPARE_WIDTH);
-- Compare the commited read space plus the actual used space against the
-- stall threshold. Assert the read address posting stall flag if the
-- threshold is met or exceeded.
sig_stall_rd_addr_posts <= '1'
when (sig_commit_plus_actual > RD_ADDR_POST_STALL_THRESH_US)
Else '0';
-- FIFO Rd/WR Controls
sig_push_data_fifo <= sig_good_sin_strm_dbeat;
-- sig_pop_data_fifo <= sig_sout2sf_tready and
-- sig_data_fifo_dvalid;
GEN_MM2S_TKEEP_ENABLE2 : if C_ENABLE_MM2S_TKEEP = 1 generate
begin
-- Concatonate the Stream inputs into the single FIFO data in value
sig_data_fifo_data_in <= data2sf_dre_flush & -- ms Field
data2sf_cmd_cmplt &
sin2sf_tlast &
sin2sf_tkeep &
sin2sf_tdata; -- ls field
end generate GEN_MM2S_TKEEP_ENABLE2;
GEN_MM2S_TKEEP_DISABLE2 : if C_ENABLE_MM2S_TKEEP = 0 generate
begin
-- Concatonate the Stream inputs into the single FIFO data in value
sig_data_fifo_data_in <= data2sf_dre_flush & -- ms Field
data2sf_cmd_cmplt &
sin2sf_tlast &
--sin2sf_tkeep &
sin2sf_tdata; -- ls field
end generate GEN_MM2S_TKEEP_DISABLE2;
------------------------------------------------------------
-- Instance: I_DATA_FIFO
--
-- Description:
-- Implements the Store and Forward data FIFO (synchronous)
--
------------------------------------------------------------
I_DATA_FIFO : entity axi_datamover_v5_1_9.axi_datamover_sfifo_autord
generic map (
C_DWIDTH => DATA_FIFO_WIDTH ,
C_DEPTH => DATA_FIFO_DEPTH ,
C_DATA_CNT_WIDTH => DATA_FIFO_CNT_WIDTH ,
C_NEED_ALMOST_EMPTY => NOT_NEEDED ,
C_NEED_ALMOST_FULL => NOT_NEEDED ,
C_USE_BLKMEM => BLK_MEM_FIFO ,
C_FAMILY => C_FAMILY
)
port map (
-- Inputs
SFIFO_Sinit => reset ,
SFIFO_Clk => aclk ,
SFIFO_Wr_en => sig_push_data_fifo ,
SFIFO_Din => sig_data_fifo_data_in ,
SFIFO_Rd_en => sig_pop_data_fifo ,
SFIFO_Clr_Rd_Data_Valid => LOGIC_LOW ,
-- Outputs
SFIFO_DValid => sig_data_fifo_dvalid ,
SFIFO_Dout => sig_data_fifo_data_out ,
SFIFO_Full => sig_data_fifo_full ,
SFIFO_Empty => open ,
SFIFO_Almost_full => open ,
SFIFO_Almost_empty => open ,
SFIFO_Rd_count => open ,
SFIFO_Rd_count_minus1 => open ,
SFIFO_Wr_count => sig_data_fifo_wr_cnt ,
SFIFO_Rd_ack => open
);
end implementation;
|
-------------------------------------------------------------------------------
-- axi_datamover_rd_sf.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_rd_sf.vhd
--
-- Description:
-- This file implements the AXI DataMover Read (MM2S) Store and Forward module.
-- The design utilizes the AXI DataMover's new address pipelining
-- control function. The design is such that predictive address
-- pipelining can be supported on the AXI Read Bus without over-commiting
-- the internal Data FIFO and potentially throttling the Read Data Channel
-- if the Data FIFO goes full.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library lib_pkg_v1_0_2;
use lib_pkg_v1_0_2.lib_pkg.all;
use lib_pkg_v1_0_2.lib_pkg.clog2;
library axi_datamover_v5_1_9;
use axi_datamover_v5_1_9.axi_datamover_sfifo_autord;
use axi_datamover_v5_1_9.axi_datamover_fifo;
-------------------------------------------------------------------------------
entity axi_datamover_rd_sf is
generic (
C_SF_FIFO_DEPTH : Integer range 128 to 8192 := 512;
-- Sets the desired depth of the internal Data FIFO.
C_MAX_BURST_LEN : Integer range 2 to 256 := 16;
-- Indicates the max burst length being used by the external
-- AXI4 Master for each AXI4 transfer request.
C_DRE_IS_USED : Integer range 0 to 1 := 0;
-- Indicates if the external Master is utilizing a DRE on
-- the stream input to this module.
C_DRE_CNTL_FIFO_DEPTH : Integer range 1 to 32 := 1;
-- Specifies the depth of the internal dre control queue fifo
C_DRE_ALIGN_WIDTH : Integer range 1 to 3 := 2;
-- Sets the width of the DRE alignment control ports
C_MMAP_DWIDTH : Integer range 32 to 1024 := 64;
-- Sets the AXI4 Memory Mapped Bus Data Width
C_STREAM_DWIDTH : Integer range 8 to 1024 := 32;
-- Sets the Stream Data Width for the Input and Output
-- Data streams.
C_STRT_SF_OFFSET_WIDTH : Integer range 1 to 7 := 2;
-- Sets the bit width of the starting address offset port
-- This should be set to log2(C_MMAP_DWIDTH/C_STREAM_DWIDTH)
C_ENABLE_MM2S_TKEEP : integer range 0 to 1 := 1;
C_TAG_WIDTH : Integer range 1 to 8 := 4;
-- Indicates the width of the Tag field of the input DRE command
C_FAMILY : String := "virtex7"
-- Indicates the target FPGA Family.
);
port (
-- Clock and Reset inputs --------------------------------------------
--
aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- Reset input --
reset : in std_logic; --
-- Reset used for the internal syncronization logic --
----------------------------------------------------------------------
-- DataMover Read Side Address Pipelining Control Interface ----------
--
ok_to_post_rd_addr : Out Std_logic; --
-- Indicates that the transfer token pool has at least --
-- one token available to borrow --
--
rd_addr_posted : In std_logic; --
-- Indication that a read address has been posted to AXI4 --
--
rd_xfer_cmplt : In std_logic; --
-- Indicates that the Datamover has completed a Read Data --
-- transfer on the AXI4 --
----------------------------------------------------------------------
-- Read Side Stream In from DataMover MM2S Read Data Controller ----------------------
--
sf2sin_tready : Out Std_logic; --
-- DRE Stream READY input --
--
sin2sf_tvalid : In std_logic; --
-- DRE Stream VALID Output --
--
sin2sf_tdata : In std_logic_vector(C_MMAP_DWIDTH-1 downto 0); --
-- DRE Stream DATA input --
--
sin2sf_tkeep : In std_logic_vector((C_MMAP_DWIDTH/8)-1 downto 0); --
-- DRE Stream STRB input --
--
sin2sf_tlast : In std_logic; --
-- DRE Xfer LAST input --
--------------------------------------------------------------------------------------
-- RDC Store and Forward Supplimental Controls ---------------------
-- These are time aligned and qualified with the RDC Stream Input --
--
data2sf_cmd_cmplt : In std_logic; --
data2sf_dre_flush : In std_logic; --
--------------------------------------------------------------------
-- DRE Control Interface from the Command Calculator -----------------------------
--
dre2mstr_cmd_ready : Out std_logic ; --
-- Indication from the DRE that the command is being --
-- accepted from the Command Calculator --
--
mstr2dre_cmd_valid : In std_logic; --
-- The next command valid indication to the DRE --
-- from the Command Calculator --
--
mstr2dre_tag : In std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The next command tag --
--
mstr2dre_dre_src_align : In std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0); --
-- The source (input) alignment for the DRE --
--
mstr2dre_dre_dest_align : In std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0); --
-- The destinstion (output) alignment for the DRE --
--
-- mstr2dre_btt : In std_logic_vector(C_BTT_USED-1 downto 0); --
-- -- The bytes to transfer value for the input command --
--
mstr2dre_drr : In std_logic; --
-- The starting tranfer of a sequence of transfers --
--
mstr2dre_eof : In std_logic; --
-- The endiing tranfer of a sequence of transfers --
--
-- mstr2dre_cmd_cmplt : In std_logic; --
-- -- The last tranfer command of a sequence of transfers --
-- -- spawned from a single parent command --
--
mstr2dre_calc_error : In std_logic; --
-- Indication if the next command in the calculation pipe --
-- has a calculation error --
--
mstr2dre_strt_offset : In std_logic_vector(C_STRT_SF_OFFSET_WIDTH-1 downto 0);--
-- Outputs the starting offset of a transfer. This is used with Store --
-- and Forward Packer/Unpacker logic --
-----------------------------------------------------------------------------------
-- MM2S DRE Control -------------------------------------------------------------
--
sf2dre_new_align : Out std_logic; --
-- Active high signal indicating new DRE aligment required --
--
sf2dre_use_autodest : Out std_logic; --
-- Active high signal indicating to the DRE to use an auto- --
-- calculated desination alignment based on the last transfer --
--
sf2dre_src_align : Out std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0); --
-- Bit field indicating the byte lane of the first valid data byte --
-- being sent to the DRE --
--
sf2dre_dest_align : Out std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0); --
-- Bit field indicating the desired byte lane of the first valid data byte --
-- to be output by the DRE --
--
sf2dre_flush : Out std_logic; --
-- Active high signal indicating to the DRE to flush the current --
-- contents to the output register in preparation of a new alignment --
-- that will be comming on the next transfer input --
---------------------------------------------------------------------------------
-- Stream Out -----------------------------------------------------------------------
--
sout2sf_tready : In std_logic; --
-- Write READY input from the Stream Master --
--
sf2sout_tvalid : Out std_logic; --
-- Write VALID output to the Stream Master --
--
sf2sout_tdata : Out std_logic_vector(C_STREAM_DWIDTH-1 downto 0); --
-- Write DATA output to the Stream Master --
--
sf2sout_tkeep : Out std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- Write DATA output to the Stream Master --
--
sf2sout_tlast : Out std_logic --
-- Write LAST output to the Stream Master --
--------------------------------------------------------------------------------------
);
end entity axi_datamover_rd_sf;
architecture implementation of axi_datamover_rd_sf is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Functions ---------------------------------------------------------------------------
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_fifo_cnt_width
--
-- Function Description:
-- simple function to set the width of the data fifo read
-- and write count outputs.
-------------------------------------------------------------------
function funct_get_fifo_cnt_width (fifo_depth : integer)
return integer is
Variable temp_width : integer := 8;
begin
if (fifo_depth = 1) then
temp_width := 1;
elsif (fifo_depth = 2) then
temp_width := 2;
elsif (fifo_depth <= 4) then
temp_width := 3;
elsif (fifo_depth <= 8) then
temp_width := 4;
elsif (fifo_depth <= 16) then
temp_width := 5;
elsif (fifo_depth <= 32) then
temp_width := 6;
elsif (fifo_depth <= 64) then
temp_width := 7;
elsif (fifo_depth <= 128) then
temp_width := 8;
elsif (fifo_depth <= 256) then
temp_width := 9;
elsif (fifo_depth <= 512) then
temp_width := 10;
elsif (fifo_depth <= 1024) then
temp_width := 11;
elsif (fifo_depth <= 2048) then
temp_width := 12;
elsif (fifo_depth <= 4096) then
temp_width := 13;
else -- assume 8192 depth
temp_width := 14;
end if;
Return (temp_width);
end function funct_get_fifo_cnt_width;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_wrcnt_lsrip
--
-- Function Description:
-- Calculates the ls index of the upper slice of the data fifo
-- write count needed to repesent one max burst worth of data
-- present in the fifo.
--
-------------------------------------------------------------------
function funct_get_wrcnt_lsrip (max_burst_dbeats : integer) return integer is
Variable temp_ls_index : Integer := 0;
begin
if (max_burst_dbeats <= 2) then
temp_ls_index := 1;
elsif (max_burst_dbeats <= 4) then
temp_ls_index := 2;
elsif (max_burst_dbeats <= 8) then
temp_ls_index := 3;
elsif (max_burst_dbeats <= 16) then
temp_ls_index := 4;
elsif (max_burst_dbeats <= 32) then
temp_ls_index := 5;
elsif (max_burst_dbeats <= 64) then
temp_ls_index := 6;
elsif (max_burst_dbeats <= 128) then
temp_ls_index := 7;
else
temp_ls_index := 8;
end if;
Return (temp_ls_index);
end function funct_get_wrcnt_lsrip;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_stall_thresh
--
-- Function Description:
-- Calculates the Stall threshold for the input side of the Data
-- FIFO. If DRE is being used by the DataMover, then the threshold
-- must be reduced to account for the potential of an extra write
-- databeat per request (DRE alignment dependent).
--
-------------------------------------------------------------------
function funct_get_stall_thresh (dre_is_used : integer;
max_xfer_length : integer;
data_fifo_depth : integer;
pipeline_delay_clks : integer;
fifo_settling_clks : integer) return integer is
Constant DRE_PIPE_DELAY : integer := 2; -- clks
Variable var_num_max_xfers_allowed : Integer := 0;
Variable var_dre_dbeat_overhead : Integer := 0;
Variable var_delay_fudge_factor : Integer := 0;
Variable var_thresh_headroom : Integer := 0;
Variable var_stall_thresh : Integer := 0;
begin
var_num_max_xfers_allowed := data_fifo_depth/max_xfer_length;
var_dre_dbeat_overhead := var_num_max_xfers_allowed * dre_is_used;
var_delay_fudge_factor := (dre_is_used * DRE_PIPE_DELAY) +
pipeline_delay_clks +
fifo_settling_clks;
var_thresh_headroom := max_xfer_length +
var_dre_dbeat_overhead +
var_delay_fudge_factor;
-- Scale the result to be in max transfer length increments
var_stall_thresh := (data_fifo_depth - var_thresh_headroom)/max_xfer_length;
Return (var_stall_thresh);
end function funct_get_stall_thresh;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_size_drecntl_fifo
--
-- Function Description:
-- Assures that the DRE control fifo depth is at least 4 deep else it
-- is equal to the number of max burst transfers that can fit in the
-- Store and Forward Data FIFO.
--
-------------------------------------------------------------------
function funct_size_drecntl_fifo (sf_fifo_depth : integer;
max_burst_length : integer) return integer is
Constant NEEDED_FIFO_DEPTH : integer := sf_fifo_depth/max_burst_length;
Variable temp_fifo_depth : Integer := 4;
begin
If (NEEDED_FIFO_DEPTH < 4) Then
temp_fifo_depth := 4;
Else
temp_fifo_depth := NEEDED_FIFO_DEPTH;
End if;
Return (temp_fifo_depth);
end function funct_size_drecntl_fifo;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_cntr_width
--
-- Function Description:
-- Detirmine the width needed for the address offset counter used
-- for the data fifo mux selects.
--
-------------------------------------------------------------------
function funct_get_cntr_width (num_count_states : integer) return integer is
Variable lvar_temp_width : Integer := 1;
begin
if (num_count_states <= 2) then
lvar_temp_width := 1;
elsif (num_count_states <= 4) then
lvar_temp_width := 2;
elsif (num_count_states <= 8) then
lvar_temp_width := 3;
elsif (num_count_states <= 16) then
lvar_temp_width := 4;
elsif (num_count_states <= 32) then
lvar_temp_width := 5;
elsif (num_count_states <= 64) then
lvar_temp_width := 6;
Else -- 128 cnt states
lvar_temp_width := 7;
end if;
Return (lvar_temp_width);
end function funct_get_cntr_width;
-- Constants ---------------------------------------------------------------------------
Constant LOGIC_LOW : std_logic := '0';
Constant LOGIC_HIGH : std_logic := '1';
Constant BLK_MEM_FIFO : integer := 1;
Constant SRL_FIFO : integer := 0;
Constant NOT_NEEDED : integer := 0;
Constant MMAP_TKEEP_WIDTH : integer := C_MMAP_DWIDTH/8; -- bits
Constant TLAST_WIDTH : integer := 1; -- bits
Constant CMPLT_WIDTH : integer := 1; -- bits
Constant DRE_FLUSH_WIDTH : integer := 1; -- bits
Constant DATA_FIFO_DEPTH : integer := C_SF_FIFO_DEPTH;
Constant DATA_FIFO_CNT_WIDTH : integer := funct_get_fifo_cnt_width(DATA_FIFO_DEPTH);
Constant DF_WRCNT_RIP_LS_INDEX : integer := funct_get_wrcnt_lsrip(C_MAX_BURST_LEN);
Constant DATA_FIFO_WIDTH : integer := C_MMAP_DWIDTH +
MMAP_TKEEP_WIDTH*C_ENABLE_MM2S_TKEEP +
TLAST_WIDTH +
CMPLT_WIDTH +
DRE_FLUSH_WIDTH;
Constant DATA_OUT_LSB_INDEX : integer := 0;
Constant DATA_OUT_MSB_INDEX : integer := C_MMAP_DWIDTH-1;
Constant TKEEP_OUT_LSB_INDEX : integer := DATA_OUT_MSB_INDEX+1;
Constant TKEEP_OUT_MSB_INDEX : integer := (TKEEP_OUT_LSB_INDEX+MMAP_TKEEP_WIDTH*C_ENABLE_MM2S_TKEEP)-1*C_ENABLE_MM2S_TKEEP;
Constant TLAST_OUT_INDEX : integer := TKEEP_OUT_MSB_INDEX+1*C_ENABLE_MM2S_TKEEP;
Constant CMPLT_OUT_INDEX : integer := TLAST_OUT_INDEX+1;
Constant DRE_FLUSH_OUT_INDEX : integer := CMPLT_OUT_INDEX+1;
Constant TOKEN_POOL_SIZE : integer := C_SF_FIFO_DEPTH / C_MAX_BURST_LEN;
Constant TOKEN_CNTR_WIDTH : integer := clog2(TOKEN_POOL_SIZE)+1;
Constant TOKEN_CNT_ZERO : Unsigned(TOKEN_CNTR_WIDTH-1 downto 0) :=
TO_UNSIGNED(0, TOKEN_CNTR_WIDTH);
Constant TOKEN_CNT_ONE : Unsigned(TOKEN_CNTR_WIDTH-1 downto 0) :=
TO_UNSIGNED(1, TOKEN_CNTR_WIDTH);
Constant TOKEN_CNT_MAX : Unsigned(TOKEN_CNTR_WIDTH-1 downto 0) :=
TO_UNSIGNED(TOKEN_POOL_SIZE, TOKEN_CNTR_WIDTH);
Constant THRESH_COMPARE_WIDTH : integer := TOKEN_CNTR_WIDTH+2;
Constant RD_PATH_PIPE_DEPTH : integer := 2; -- clocks excluding DRE
Constant WRCNT_SETTLING_TIME : integer := 2; -- data fifo push or pop settling clocks
Constant DRE_COMPENSATION : integer := 0; -- DRE does not contribute since it is on
-- the output side of the Store and Forward
Constant RD_ADDR_POST_STALL_THRESH : integer :=
funct_get_stall_thresh(DRE_COMPENSATION ,
C_MAX_BURST_LEN ,
C_SF_FIFO_DEPTH ,
RD_PATH_PIPE_DEPTH ,
WRCNT_SETTLING_TIME);
Constant RD_ADDR_POST_STALL_THRESH_US : Unsigned(THRESH_COMPARE_WIDTH-1 downto 0) :=
TO_UNSIGNED(RD_ADDR_POST_STALL_THRESH ,
THRESH_COMPARE_WIDTH);
Constant UNCOM_WRCNT_1 : Unsigned(DATA_FIFO_CNT_WIDTH-1 downto 0) :=
TO_UNSIGNED(1, DATA_FIFO_CNT_WIDTH);
Constant UNCOM_WRCNT_0 : Unsigned(DATA_FIFO_CNT_WIDTH-1 downto 0) :=
TO_UNSIGNED(0, DATA_FIFO_CNT_WIDTH);
Constant USE_SYNC_FIFO : integer := 0;
Constant SRL_FIFO_PRIM : integer := 2;
Constant TAG_WIDTH : integer := C_TAG_WIDTH;
Constant SRC_ALIGN_WIDTH : integer := C_DRE_ALIGN_WIDTH;
Constant DEST_ALIGN_WIDTH : integer := C_DRE_ALIGN_WIDTH;
Constant DRR_WIDTH : integer := 1;
Constant EOF_WIDTH : integer := 1;
Constant CALC_ERR_WIDTH : integer := 1;
Constant SF_OFFSET_WIDTH : integer := C_STRT_SF_OFFSET_WIDTH;
-- Signals ---------------------------------------------------------------------------
signal sig_good_sin_strm_dbeat : std_logic := '0';
signal sig_strm_sin_ready : std_logic := '0';
signal sig_good_sout_strm_dbeat : std_logic := '0';
signal sig_sout2sf_tready : std_logic := '0';
signal sig_sf2sout_tvalid : std_logic := '0';
signal sig_sf2sout_tdata : std_logic_vector(C_STREAM_DWIDTH-1 downto 0) := (others => '0');
signal sig_sf2sout_tkeep : std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0) := (others => '0');
signal sig_sf2sout_tlast : std_logic := '0';
signal sig_sf2dre_flush : std_logic := '0';
signal sig_push_data_fifo : std_logic := '0';
signal sig_pop_data_fifo : std_logic := '0';
signal sig_data_fifo_full : std_logic := '0';
signal sig_data_fifo_data_in : std_logic_vector(DATA_FIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_data_fifo_dvalid : std_logic := '0';
signal sig_data_fifo_data_out : std_logic_vector(DATA_FIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_data_fifo_wr_cnt : std_logic_vector(DATA_FIFO_CNT_WIDTH-1 downto 0) := (others => '0');
signal sig_fifo_wr_cnt_unsgnd : unsigned(DATA_FIFO_CNT_WIDTH-1 downto 0) := (others => '0');
signal sig_wrcnt_mblen_slice : unsigned(DATA_FIFO_CNT_WIDTH-1 downto
DF_WRCNT_RIP_LS_INDEX) := (others => '0');
signal sig_ok_to_post_rd_addr : std_logic := '0';
signal sig_rd_addr_posted : std_logic := '0';
signal sig_rd_xfer_cmplt : std_logic := '0';
signal sig_taking_last_token : std_logic := '0';
signal sig_stall_rd_addr_posts : std_logic := '0';
signal sig_incr_token_cntr : std_logic := '0';
signal sig_decr_token_cntr : std_logic := '0';
signal sig_token_eq_max : std_logic := '0';
signal sig_token_eq_zero : std_logic := '0';
signal sig_token_eq_one : std_logic := '0';
signal sig_token_cntr : Unsigned(TOKEN_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_tokens_commited : Unsigned(TOKEN_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_commit_plus_actual : unsigned(THRESH_COMPARE_WIDTH-1 downto 0) := (others => '0');
signal sig_cntl_fifo_has_data : std_logic := '0';
signal sig_get_cntl_fifo_data : std_logic := '0';
signal sig_curr_tag_reg : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_curr_src_align_reg : std_logic_vector(SRC_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_curr_dest_align_reg : std_logic_vector(DEST_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_curr_drr_reg : std_logic := '0';
signal sig_curr_eof_reg : std_logic := '0';
signal sig_curr_calc_error_reg : std_logic := '0';
signal sig_curr_strt_offset_reg : std_logic_vector(SF_OFFSET_WIDTH-1 downto 0) := (others => '0');
signal sig_ld_dre_cntl_reg : std_logic := '0';
signal sig_dfifo_data_out : std_logic_vector(C_MMAP_DWIDTH-1 downto 0) := (others => '0');
signal sig_dfifo_tkeep_out : std_logic_vector(MMAP_TKEEP_WIDTH-1 downto 0) := (others => '0');
signal sig_dfifo_tlast_out : std_logic := '0';
signal sig_dfifo_cmd_cmplt_out : std_logic := '0';
signal sig_dfifo_dre_flush_out : std_logic := '0';
begin --(architecture implementation)
-- Read Side (MM2S) Control Flags port connections
ok_to_post_rd_addr <= sig_ok_to_post_rd_addr ;
sig_rd_addr_posted <= rd_addr_posted ;
sig_rd_xfer_cmplt <= rd_xfer_cmplt ;
-- Output Stream Port connections
sig_sout2sf_tready <= sout2sf_tready ;
sf2sout_tvalid <= sig_sf2sout_tvalid ;
sf2sout_tdata <= sig_sf2sout_tdata ;
--sf2sout_tkeep <= sig_sf2sout_tkeep ;
sf2sout_tlast <= sig_sf2sout_tlast and
sig_sf2sout_tvalid ;
GEN_MM2S_TKEEP_ENABLE4 : if C_ENABLE_MM2S_TKEEP = 1 generate
begin
sf2sout_tkeep <= sig_sf2sout_tkeep ;
end generate GEN_MM2S_TKEEP_ENABLE4;
GEN_MM2S_TKEEP_DISABLE4 : if C_ENABLE_MM2S_TKEEP = 0 generate
begin
sf2sout_tkeep <= (others => '1');
end generate GEN_MM2S_TKEEP_DISABLE4;
-- Input Stream port connections
sf2sin_tready <= sig_strm_sin_ready;
sig_strm_sin_ready <= not(sig_data_fifo_full); -- Throttle if Read Side Data fifo goes full.
-- This should never happen if read address
-- posting control is working properly.
-- Stream transfer qualifiers
sig_good_sin_strm_dbeat <= sin2sf_tvalid and
sig_strm_sin_ready;
sig_good_sout_strm_dbeat <= sig_sf2sout_tvalid and
sig_sout2sf_tready;
----------------------------------------------------------------
-- Unpacking Logic ------------------------------------------
----------------------------------------------------------------
------------------------------------------------------------
-- If Generate
--
-- Label: OMIT_UNPACKING
--
-- If Generate Description:
-- Omits any unpacking logic in the Store and Forward module.
-- The Stream and MMap data widths are the same. The Data FIFO
-- output can be connected directly to the stream outputs.
--
------------------------------------------------------------
OMIT_UNPACKING : if (C_MMAP_DWIDTH = C_STREAM_DWIDTH) generate
signal lsig_cmd_loaded : std_logic := '0';
signal lsig_ld_cmd : std_logic := '0';
signal lsig_cmd_cmplt_dbeat : std_logic := '0';
signal lsig_cmd_cmplt : std_logic := '0';
begin
-- Data FIFO Output to the stream attachments
sig_sf2sout_tvalid <= sig_data_fifo_dvalid and
lsig_cmd_loaded ;
sig_sf2sout_tdata <= sig_dfifo_data_out ;
sig_sf2sout_tkeep <= sig_dfifo_tkeep_out ;
sig_sf2sout_tlast <= sig_dfifo_tlast_out ;
sig_sf2dre_flush <= sig_dfifo_dre_flush_out ;
-- Control for reading the Data FIFO
sig_pop_data_fifo <= lsig_cmd_loaded and
sig_sout2sf_tready and
sig_data_fifo_dvalid;
-- Control for reading the Command/Offset FIFO
sig_get_cntl_fifo_data <= lsig_ld_cmd ;
-- Control for loading the DRE Control Reg
sig_ld_dre_cntl_reg <= lsig_ld_cmd ;
lsig_cmd_cmplt_dbeat <= sig_dfifo_cmd_cmplt_out and
lsig_cmd_loaded and
sig_data_fifo_dvalid and
sig_sout2sf_tready ;
-- Generate the control that loads the DRE
lsig_ld_cmd <= (sig_cntl_fifo_has_data and -- startup or gap case
not(lsig_cmd_loaded)) or
(sig_cntl_fifo_has_data and -- back to back commands
lsig_cmd_cmplt_dbeat);
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_CMD_LOADED
--
-- Process Description:
-- Implements the flop indicating a command from the cmd fifo
-- has been loaded into the DRE Output Register.
--
-------------------------------------------------------------
IMP_CMD_LOADED : process (aclk)
begin
if (aclk'event and aclk = '1') then
if (reset = '1') then
lsig_cmd_loaded <= '0';
Elsif (lsig_ld_cmd = '1' ) Then
lsig_cmd_loaded <= '1';
elsif (sig_cntl_fifo_has_data = '0' and -- No more commands queued and
lsig_cmd_cmplt_dbeat = '1') then
lsig_cmd_loaded <= '0';
else
null; -- Hold Current State
end if;
end if;
end process IMP_CMD_LOADED;
end generate OMIT_UNPACKING;
------------------------------------------------------------
-- If Generate
--
-- Label: INCLUDE_UNPACKING
--
-- If Generate Description:
-- Includes unpacking logic in the Store and Forward module.
-- The MMap Data bus is wider than the Stream width.
--
------------------------------------------------------------
INCLUDE_UNPACKING : if (C_MMAP_DWIDTH > C_STREAM_DWIDTH) generate
Constant MMAP2STRM_WIDTH_RATO : integer := C_MMAP_DWIDTH/C_STREAM_DWIDTH;
Constant DATA_SLICE_WIDTH : integer := C_STREAM_DWIDTH;
Constant TKEEP_SLICE_WIDTH : integer := C_STREAM_DWIDTH/8;
Constant FLAG_SLICE_WIDTH : integer := TLAST_WIDTH;
Constant OFFSET_CNTR_WIDTH : integer := funct_get_cntr_width(MMAP2STRM_WIDTH_RATO);
Constant OFFSET_CNT_ONE : unsigned(OFFSET_CNTR_WIDTH-1 downto 0) :=
TO_UNSIGNED(1, OFFSET_CNTR_WIDTH);
Constant OFFSET_CNT_MAX : unsigned(OFFSET_CNTR_WIDTH-1 downto 0) :=
TO_UNSIGNED(MMAP2STRM_WIDTH_RATO-1, OFFSET_CNTR_WIDTH);
-- Types -----------------------------------------------------------------------------
type lsig_data_slice_type is array(MMAP2STRM_WIDTH_RATO-1 downto 0) of
std_logic_vector(DATA_SLICE_WIDTH-1 downto 0);
type lsig_tkeep_slice_type is array(MMAP2STRM_WIDTH_RATO downto 0) of
std_logic_vector(TKEEP_SLICE_WIDTH-1 downto 0);
type lsig_flag_slice_type is array(MMAP2STRM_WIDTH_RATO-1 downto 0) of
std_logic_vector(FLAG_SLICE_WIDTH-1 downto 0);
-- local signals
signal lsig_0ffset_cntr : unsigned(OFFSET_CNTR_WIDTH-1 downto 0) := (others => '0');
signal lsig_ld_offset : std_logic := '0';
signal lsig_incr_offset : std_logic := '0';
signal lsig_offset_cntr_eq_max : std_logic := '0';
signal lsig_fifo_data_out_wide : lsig_data_slice_type;
signal lsig_fifo_tkeep_out_wide : lsig_tkeep_slice_type;
signal lsig_mux_sel : integer range 0 to MMAP2STRM_WIDTH_RATO-1;
signal lsig_data_mux_out : std_logic_vector(DATA_SLICE_WIDTH-1 downto 0) ;
signal lsig_tkeep_mux_out : std_logic_vector(TKEEP_SLICE_WIDTH-1 downto 0);
signal lsig_tlast_out : std_logic := '0';
signal lsig_dre_flush_out : std_logic := '0';
signal lsig_this_fifo_wrd_done : std_logic := '0';
signal lsig_cmd_loaded : std_logic := '0';
signal lsig_cmd_cmplt_dbeat : std_logic := '0';
signal lsig_cmd_cmplt : std_logic := '0';
signal lsig_next_slice_tkeep_0 : std_logic := '0';
begin
sig_sf2sout_tvalid <= sig_data_fifo_dvalid and
lsig_cmd_loaded ;
sig_sf2sout_tdata <= lsig_data_mux_out ;
sig_sf2sout_tkeep <= lsig_tkeep_mux_out(TKEEP_SLICE_WIDTH-1 downto 0);
sig_sf2sout_tlast <= lsig_tlast_out ;
sig_sf2dre_flush <= lsig_dre_flush_out ;
-- Control for reading the Data FIFO
sig_pop_data_fifo <= lsig_this_fifo_wrd_done and
lsig_cmd_loaded and
sig_sout2sf_tready and
sig_data_fifo_dvalid;
-- Control for reading the Command/Offset FIFO
sig_get_cntl_fifo_data <= lsig_ld_offset;
-- Control for loading the DRE Control Reg
sig_ld_dre_cntl_reg <= lsig_ld_offset ;
lsig_next_slice_tkeep_0 <= lsig_fifo_tkeep_out_wide(lsig_mux_sel+1)(0);
-- Detirmine if a Command Complete condition exists
lsig_cmd_cmplt <= '1'
when (sig_dfifo_cmd_cmplt_out = '1' and
lsig_next_slice_tkeep_0 = '0')
Else '0';
-- Detirmine if a TLAST condition exists
-- From the RDC via the Data FIFO
lsig_tlast_out <= '1'
when (sig_dfifo_tlast_out = '1' and
lsig_next_slice_tkeep_0 = '0')
Else '0';
-- Detimine if a DRE Flush condition exists
-- From the RDC via the Data FIFO
lsig_dre_flush_out <= '1'
when (sig_dfifo_dre_flush_out = '1' and
lsig_next_slice_tkeep_0 = '0')
Else '0';
lsig_cmd_cmplt_dbeat <= lsig_cmd_cmplt and
lsig_cmd_loaded and
sig_data_fifo_dvalid and
sig_sout2sf_tready ;
-- Check to see if the FIFO output word is finished. This occurs
-- when the offset counter is at max value or the tlast from the
-- fifo is set and the LS TKEED of the next MS Slice is zero.
lsig_this_fifo_wrd_done <= '1'
When (lsig_offset_cntr_eq_max = '1' or
(lsig_cmd_cmplt_dbeat = '1' and
lsig_next_slice_tkeep_0 = '0'))
Else '0';
-- Generate the control that loads the starting address
-- offset for the next input packet
lsig_ld_offset <= (sig_cntl_fifo_has_data and -- startup or gap case
not(lsig_cmd_loaded)) or
(sig_cntl_fifo_has_data and -- back to back commands
lsig_cmd_cmplt_dbeat);
-- Generate the control for incrementing the offset counter
lsig_incr_offset <= sig_good_sout_strm_dbeat;
-- Check to see if the offset counter has reached its max
-- value
lsig_offset_cntr_eq_max <= '1'
when (lsig_0ffset_cntr = OFFSET_CNT_MAX)
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_CMD_LOADED
--
-- Process Description:
-- Implements the flop indicating a command from the cmd fifo
-- has been loaded into the unpacker control logic.
--
-------------------------------------------------------------
IMP_CMD_LOADED : process (aclk)
begin
if (aclk'event and aclk = '1') then
if (reset = '1') then
lsig_cmd_loaded <= '0';
Elsif (lsig_ld_offset = '1' ) Then
lsig_cmd_loaded <= '1';
elsif (sig_cntl_fifo_has_data = '0' and -- No more commands queued
lsig_cmd_cmplt_dbeat = '1') then
lsig_cmd_loaded <= '0';
else
null; -- Hold Current State
end if;
end if;
end process IMP_CMD_LOADED;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_OFFSET_CNTR
--
-- Process Description:
-- Implements the address offset counter that is used to
-- generate the data and tkeep mux selects.
-- Note that the counter has to be loaded with the starting
-- offset plus one to sync up with the data input.
-------------------------------------------------------------
IMP_OFFSET_CNTR : process (aclk)
begin
if (aclk'event and aclk = '1') then
if (reset = '1') then
lsig_0ffset_cntr <= (others => '0');
Elsif (lsig_ld_offset = '1') Then
lsig_0ffset_cntr <= UNSIGNED(sig_curr_strt_offset_reg);
elsif (lsig_incr_offset = '1') then
lsig_0ffset_cntr <= lsig_0ffset_cntr + OFFSET_CNT_ONE;
else
null; -- Hold Current State
end if;
end if;
end process IMP_OFFSET_CNTR;
------------------------------------------------------------
-- For Generate
--
-- Label: DO_DATA_CONVERTER
--
-- For Generate Description:
-- This ForGen converts the FIFO output data and tkeep from a single
-- std logic vector type to a vector of slices.
--
------------------------------------------------------------
DO_DATA_CONVERTER : for slice_index in 1 to MMAP2STRM_WIDTH_RATO generate
begin
lsig_fifo_data_out_wide(slice_index-1) <=
sig_dfifo_data_out((slice_index*DATA_SLICE_WIDTH)-1 downto
(slice_index-1)*DATA_SLICE_WIDTH);
lsig_fifo_tkeep_out_wide(slice_index-1) <=
sig_dfifo_tkeep_out((slice_index*TKEEP_SLICE_WIDTH)-1 downto
(slice_index-1)*TKEEP_SLICE_WIDTH);
end generate DO_DATA_CONVERTER;
-- Assign the extra tkeep slice to all zeros to allow for detection
-- of the data word done when the ls tkeep bit of the next tkeep
-- slice is zero and the offset count is pointing to the last slice
-- position.
lsig_fifo_tkeep_out_wide(MMAP2STRM_WIDTH_RATO) <= (others => '0');
-- Mux the appropriate data and tkeep slice to the stream output
lsig_mux_sel <= TO_INTEGER(lsig_0ffset_cntr);
lsig_data_mux_out <= lsig_fifo_data_out_wide(lsig_mux_sel) ;
lsig_tkeep_mux_out(TKEEP_SLICE_WIDTH-1 downto 0) <= lsig_fifo_tkeep_out_wide(lsig_mux_sel);
end generate INCLUDE_UNPACKING;
------------------------------------------------------------
-- If Generate
--
-- Label: OMIT_DRE_CNTL
--
-- If Generate Description:
-- This IfGen is used to omit the DRE control logic and
-- minimize the Control FIFO when MM2S DRE is not included
-- in the MM2S.
--
------------------------------------------------------------
OMIT_DRE_CNTL : if (C_DRE_IS_USED = 0) generate
-- Constant Declarations ------------------------------------------------------------------
Constant USE_SYNC_FIFO : integer := 0;
Constant SRL_FIFO_PRIM : integer := 2;
Constant TAG_WIDTH : integer := C_TAG_WIDTH;
Constant DRR_WIDTH : integer := 1;
Constant EOF_WIDTH : integer := 1;
Constant CALC_ERR_WIDTH : integer := 1;
Constant SF_OFFSET_WIDTH : integer := C_STRT_SF_OFFSET_WIDTH;
Constant SF_OFFSET_FIFO_DEPTH : integer := funct_size_drecntl_fifo(C_DRE_CNTL_FIFO_DEPTH,
C_MAX_BURST_LEN);
Constant SF_OFFSET_FIFO_WIDTH : Integer := TAG_WIDTH + -- Tag field
DRR_WIDTH + -- DRE Re-alignment Request Flag Field
EOF_WIDTH + -- EOF flag field
CALC_ERR_WIDTH + -- Calc error flag
SF_OFFSET_WIDTH; -- Store and Forward Offset
Constant TAG_STRT_INDEX : integer := 0;
Constant DRR_STRT_INDEX : integer := TAG_STRT_INDEX + TAG_WIDTH;
Constant EOF_STRT_INDEX : integer := DRR_STRT_INDEX + DRR_WIDTH;
Constant CALC_ERR_STRT_INDEX : integer := EOF_STRT_INDEX + EOF_WIDTH;
Constant SF_OFFSET_STRT_INDEX : integer := CALC_ERR_STRT_INDEX+CALC_ERR_WIDTH;
-- Signal Declarations --------------------------------------------------------------------
signal sig_offset_fifo_data_in : std_logic_vector(SF_OFFSET_FIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_offset_fifo_data_out : std_logic_vector(SF_OFFSET_FIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_offset_fifo_wr_valid : std_logic := '0';
signal sig_offset_fifo_wr_ready : std_logic := '0';
signal sig_offset_fifo_rd_valid : std_logic := '0';
signal sig_offset_fifo_rd_ready : std_logic := '0';
begin
-- PCC DRE Command interface handshake
dre2mstr_cmd_ready <= sig_offset_fifo_wr_ready ;
sig_offset_fifo_wr_valid <= mstr2dre_cmd_valid ;
-- No DRE so no controls
sf2dre_new_align <= '0';
sf2dre_use_autodest <= '0';
sf2dre_src_align <= (others => '0');
sf2dre_dest_align <= (others => '0');
sf2dre_flush <= '0';
-- No DRE so no alignment values
sig_curr_src_align_reg <= (others => '0');
sig_curr_dest_align_reg <= (others => '0');
-- Format the input data word for the Offset FIFO Queue
sig_offset_fifo_data_in <= mstr2dre_strt_offset & -- MS field
mstr2dre_calc_error &
mstr2dre_eof &
mstr2dre_drr &
mstr2dre_tag; -- LS Field
sig_cntl_fifo_has_data <= sig_offset_fifo_rd_valid ;
sig_offset_fifo_rd_ready <= sig_get_cntl_fifo_data ;
-- Rip the output fifo data word
sig_curr_tag_reg <= sig_offset_fifo_data_out((TAG_STRT_INDEX+TAG_WIDTH)-1 downto TAG_STRT_INDEX);
sig_curr_drr_reg <= sig_offset_fifo_data_out(DRR_STRT_INDEX);
sig_curr_eof_reg <= sig_offset_fifo_data_out(EOF_STRT_INDEX);
sig_curr_calc_error_reg <= sig_offset_fifo_data_out(CALC_ERR_STRT_INDEX);
sig_curr_strt_offset_reg <= sig_offset_fifo_data_out((SF_OFFSET_STRT_INDEX+SF_OFFSET_WIDTH)-1 downto
SF_OFFSET_STRT_INDEX);
------------------------------------------------------------
-- Instance: I_DRE_CNTL_FIFO
--
-- Description:
-- Instance for the Offset Control FIFO. This is still needed
-- by the unpacker logic to get the starting offset at the
-- begining of an input packet coming out of the Store and
-- Forward data FIFO.
--
------------------------------------------------------------
I_DRE_CNTL_FIFO : entity axi_datamover_v5_1_9.axi_datamover_fifo
generic map (
C_DWIDTH => SF_OFFSET_FIFO_WIDTH ,
C_DEPTH => SF_OFFSET_FIFO_DEPTH ,
C_IS_ASYNC => USE_SYNC_FIFO ,
C_PRIM_TYPE => SRL_FIFO_PRIM ,
C_FAMILY => C_FAMILY
)
port map (
-- Write Clock and reset
fifo_wr_reset => reset ,
fifo_wr_clk => aclk ,
-- Write Side
fifo_wr_tvalid => sig_offset_fifo_wr_valid ,
fifo_wr_tready => sig_offset_fifo_wr_ready ,
fifo_wr_tdata => sig_offset_fifo_data_in ,
fifo_wr_full => open ,
-- Read Clock and reset
fifo_async_rd_reset => aclk ,
fifo_async_rd_clk => reset ,
-- Read Side
fifo_rd_tvalid => sig_offset_fifo_rd_valid ,
fifo_rd_tready => sig_offset_fifo_rd_ready ,
fifo_rd_tdata => sig_offset_fifo_data_out ,
fifo_rd_empty => open
);
end generate OMIT_DRE_CNTL;
------------------------------------------------------------
-- If Generate
--
-- Label: INCLUDE_DRE_CNTL
--
-- If Generate Description:
-- This IfGen is used to include the DRE control logic and
-- Control FIFO when MM2S DRE is included in the MM2S.
--
--
------------------------------------------------------------
INCLUDE_DRE_CNTL : if (C_DRE_IS_USED = 1) generate
-- Constant Declarations
Constant DRECNTL_FIFO_DEPTH : integer := funct_size_drecntl_fifo(C_DRE_CNTL_FIFO_DEPTH,
C_MAX_BURST_LEN);
Constant DRECNTL_FIFO_WIDTH : Integer := TAG_WIDTH + -- Tag field
SRC_ALIGN_WIDTH + -- Source align field width
DEST_ALIGN_WIDTH + -- Dest align field width
DRR_WIDTH + -- DRE Re-alignment Request Flag Field
EOF_WIDTH + -- EOF flag field
CALC_ERR_WIDTH + -- Calc error flag
SF_OFFSET_WIDTH; -- Store and Forward Offset
Constant TAG_STRT_INDEX : integer := 0;
Constant SRC_ALIGN_STRT_INDEX : integer := TAG_STRT_INDEX + TAG_WIDTH;
Constant DEST_ALIGN_STRT_INDEX : integer := SRC_ALIGN_STRT_INDEX + SRC_ALIGN_WIDTH;
Constant DRR_STRT_INDEX : integer := DEST_ALIGN_STRT_INDEX + DEST_ALIGN_WIDTH;
Constant EOF_STRT_INDEX : integer := DRR_STRT_INDEX + DRR_WIDTH;
Constant CALC_ERR_STRT_INDEX : integer := EOF_STRT_INDEX + EOF_WIDTH;
Constant SF_OFFSET_STRT_INDEX : integer := CALC_ERR_STRT_INDEX+CALC_ERR_WIDTH;
signal sig_cmd_fifo_data_in : std_logic_vector(DRECNTL_FIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd_fifo_data_out : std_logic_vector(DRECNTL_FIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_fifo_wr_cmd_valid : std_logic := '0';
signal sig_fifo_wr_cmd_ready : std_logic := '0';
signal sig_fifo_rd_cmd_valid : std_logic := '0';
signal sig_fifo_rd_cmd_ready : std_logic := '0';
signal sig_dre_align_ready : std_logic := '0';
signal sig_dre_align_valid_reg : std_logic := '0';
signal sig_dre_use_autodest_reg : std_logic := '0';
signal sig_dre_src_align_reg : std_logic_vector(SRC_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_dre_dest_align_reg : std_logic_vector(DEST_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_dre_flush_reg : std_logic := '0';
begin
-- Assign the DRE Control Outputs
sf2dre_new_align <= sig_dre_align_valid_reg;
sf2dre_use_autodest <= sig_dre_use_autodest_reg;
sf2dre_src_align <= sig_dre_src_align_reg;
sf2dre_dest_align <= sig_dre_dest_align_reg;
sf2dre_flush <= sig_sf2dre_flush; -- from RDC via data FIFO
-- PCC DRE Command interface handshake
dre2mstr_cmd_ready <= sig_fifo_wr_cmd_ready;
sig_fifo_wr_cmd_valid <= mstr2dre_cmd_valid ;
-- Format the input data word for the DRE Control FIFO Queue
sig_cmd_fifo_data_in <= mstr2dre_strt_offset &
mstr2dre_calc_error &
mstr2dre_eof &
mstr2dre_drr &
mstr2dre_dre_dest_align &
mstr2dre_dre_src_align &
mstr2dre_tag;
-- Formulate the DRE Control FIFO Read signaling
sig_cntl_fifo_has_data <= sig_fifo_rd_cmd_valid ;
sig_fifo_rd_cmd_ready <= sig_get_cntl_fifo_data ;
-- Rip the output fifo data word
sig_curr_tag_reg <= sig_cmd_fifo_data_out((TAG_STRT_INDEX+TAG_WIDTH)-1 downto TAG_STRT_INDEX);
sig_curr_src_align_reg <= sig_cmd_fifo_data_out((SRC_ALIGN_STRT_INDEX+SRC_ALIGN_WIDTH)-1 downto
SRC_ALIGN_STRT_INDEX);
sig_curr_dest_align_reg <= sig_cmd_fifo_data_out((DEST_ALIGN_STRT_INDEX+DEST_ALIGN_WIDTH)-1 downto
DEST_ALIGN_STRT_INDEX);
sig_curr_drr_reg <= sig_cmd_fifo_data_out(DRR_STRT_INDEX);
sig_curr_eof_reg <= sig_cmd_fifo_data_out(EOF_STRT_INDEX);
sig_curr_calc_error_reg <= sig_cmd_fifo_data_out(CALC_ERR_STRT_INDEX);
sig_curr_strt_offset_reg <= sig_cmd_fifo_data_out((SF_OFFSET_STRT_INDEX+SF_OFFSET_WIDTH)-1 downto
SF_OFFSET_STRT_INDEX);
------------------------------------------------------------
-- Instance: I_DRE_CNTL_FIFO
--
-- Description:
-- Instance for the DRE Control FIFO
--
------------------------------------------------------------
I_DRE_CNTL_FIFO : entity axi_datamover_v5_1_9.axi_datamover_fifo
generic map (
C_DWIDTH => DRECNTL_FIFO_WIDTH ,
C_DEPTH => DRECNTL_FIFO_DEPTH ,
C_IS_ASYNC => USE_SYNC_FIFO ,
C_PRIM_TYPE => SRL_FIFO_PRIM ,
C_FAMILY => C_FAMILY
)
port map (
-- Write Clock and reset
fifo_wr_reset => reset ,
fifo_wr_clk => aclk ,
-- Write Side
fifo_wr_tvalid => sig_fifo_wr_cmd_valid ,
fifo_wr_tready => sig_fifo_wr_cmd_ready ,
fifo_wr_tdata => sig_cmd_fifo_data_in ,
fifo_wr_full => open ,
-- Read Clock and reset
fifo_async_rd_reset => aclk ,
fifo_async_rd_clk => reset ,
-- Read Side
fifo_rd_tvalid => sig_fifo_rd_cmd_valid ,
fifo_rd_tready => sig_fifo_rd_cmd_ready ,
fifo_rd_tdata => sig_cmd_fifo_data_out ,
fifo_rd_empty => open
);
-------------------------------------------------------------------------
-- DRE Control Register
-------------------------------------------------------------------------
-- The DRE will auto-flush on a received TLAST so a commanded Flush
-- is not needed.
sig_dre_flush_reg <= '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_CNTL_REG
--
-- Process Description:
-- Implements the DRE alignment Output Register.
--
-------------------------------------------------------------
IMP_CNTL_REG : process (aclk)
begin
if (aclk'event and aclk = '1') then
if (reset = '1') then
sig_dre_use_autodest_reg <= '0' ;
sig_dre_src_align_reg <= (others => '0') ;
sig_dre_dest_align_reg <= (others => '0') ;
Elsif (sig_ld_dre_cntl_reg = '1' ) Then
sig_dre_use_autodest_reg <= not(sig_curr_drr_reg) ;
sig_dre_src_align_reg <= sig_curr_src_align_reg ;
sig_dre_dest_align_reg <= sig_curr_dest_align_reg ;
Elsif (sig_good_sout_strm_dbeat = '1') Then
sig_dre_use_autodest_reg <= '0' ;
sig_dre_src_align_reg <= (others => '0') ;
sig_dre_dest_align_reg <= (others => '0') ;
else
null; -- Hold Current State
end if;
end if;
end process IMP_CNTL_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_DRE_CNTL_VALID_REG
--
-- Process Description:
-- Implements the DRE Alignment valid Register.
--
-------------------------------------------------------------
IMP_DRE_CNTL_VALID_REG : process (aclk)
begin
if (aclk'event and aclk = '1') then
if (reset = '1') then
sig_dre_align_valid_reg <= '0' ;
Elsif (sig_ld_dre_cntl_reg = '1' ) Then
sig_dre_align_valid_reg <= '1' ;
Elsif (sig_good_sout_strm_dbeat = '1') Then
sig_dre_align_valid_reg <= '0' ;
else
null; -- Hold Current State
end if;
end if;
end process IMP_DRE_CNTL_VALID_REG;
end generate INCLUDE_DRE_CNTL;
----------------------------------------------------------------
-- Token Counter Logic
-- Predicting fifo space availability at some point in the
-- future is based on managing a virtual pool of transfer tokens.
-- A token represents 1 max length burst worth of space in the
-- Data FIFO.
----------------------------------------------------------------
-- calculate how many tokens are commited to pending transfers
sig_tokens_commited <= TOKEN_CNT_MAX - sig_token_cntr;
-- Decrement the token counter when a token is
-- borrowed
sig_decr_token_cntr <= '1'
when (sig_rd_addr_posted = '1' and
sig_token_eq_zero = '0')
else '0';
-- Increment the token counter when a
-- token is returned.
sig_incr_token_cntr <= '1'
when (sig_rd_xfer_cmplt = '1' and
sig_token_eq_max = '0')
else '0';
-- Detect when the xfer token count is at max value
sig_token_eq_max <= '1'
when (sig_token_cntr = TOKEN_CNT_MAX)
Else '0';
-- Detect when the xfer token count is at one
sig_token_eq_one <= '1'
when (sig_token_cntr = TOKEN_CNT_ONE)
Else '0';
-- Detect when the xfer token count is at zero
sig_token_eq_zero <= '1'
when (sig_token_cntr = TOKEN_CNT_ZERO)
Else '0';
-- Look ahead to see if the xfer token pool is going empty
sig_taking_last_token <= '1'
When (sig_token_eq_one = '1' and
sig_rd_addr_posted = '1')
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_TOKEN_CNTR
--
-- Process Description:
-- Implements the Token counter
--
-------------------------------------------------------------
IMP_TOKEN_CNTR : process (aclk)
begin
if (aclk'event and aclk = '1') then
if (reset = '1' ) then
sig_token_cntr <= TOKEN_CNT_MAX;
elsif (sig_incr_token_cntr = '1' and
sig_decr_token_cntr = '0') then
sig_token_cntr <= sig_token_cntr + TOKEN_CNT_ONE;
elsif (sig_incr_token_cntr = '0' and
sig_decr_token_cntr = '1') then
sig_token_cntr <= sig_token_cntr - TOKEN_CNT_ONE;
else
null; -- hold current value
end if;
end if;
end process IMP_TOKEN_CNTR;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_TOKEN_AVAIL_FLAG
--
-- Process Description:
-- Implements the flag indicating that the AXI Read Master
-- can post a read address request on the AXI4 bus.
--
-- Read address posting can occur if:
--
-- - The write side LEN fifo is not empty.
-- - The commited plus actual Data FIFO space is less than
-- the stall threshold (a max length read burst can fit
-- in the data FIFO without overflow).
-- - The max allowed commited read count has not been reached.
--
-- The flag is cleared after each address has been posted to
-- ensure a second unauthorized post does not occur.
-------------------------------------------------------------
IMP_TOKEN_AVAIL_FLAG : process (aclk)
begin
if (aclk'event and aclk = '1') then
if (reset = '1' or
sig_rd_addr_posted = '1') then
sig_ok_to_post_rd_addr <= '0';
else
sig_ok_to_post_rd_addr <= not(sig_stall_rd_addr_posts) and -- the commited Data FIFO space is approaching full
not(sig_token_eq_zero) and -- max allowed pending reads has not been reached
not(sig_taking_last_token); -- the max allowed pending reads is about to be reached
end if;
end if;
end process IMP_TOKEN_AVAIL_FLAG;
----------------------------------------------------------------
-- Data FIFO Logic ------------------------------------------
----------------------------------------------------------------
GEN_MM2S_TKEEP_ENABLE3 : if C_ENABLE_MM2S_TKEEP = 1 generate
begin
-- FIFO Output ripping to components
sig_dfifo_data_out <= sig_data_fifo_data_out(DATA_OUT_MSB_INDEX downto
DATA_OUT_LSB_INDEX);
sig_dfifo_tkeep_out <= sig_data_fifo_data_out(TKEEP_OUT_MSB_INDEX downto
TKEEP_OUT_LSB_INDEX);
sig_dfifo_tlast_out <= sig_data_fifo_data_out(TLAST_OUT_INDEX) ;
sig_dfifo_cmd_cmplt_out <= sig_data_fifo_data_out(CMPLT_OUT_INDEX) ;
sig_dfifo_dre_flush_out <= sig_data_fifo_data_out(DRE_FLUSH_OUT_INDEX) ;
end generate GEN_MM2S_TKEEP_ENABLE3;
GEN_MM2S_TKEEP_DISABLE3 : if C_ENABLE_MM2S_TKEEP = 0 generate
begin
-- FIFO Output ripping to components
sig_dfifo_data_out <= sig_data_fifo_data_out(DATA_OUT_MSB_INDEX downto
DATA_OUT_LSB_INDEX);
sig_dfifo_tkeep_out <= (others => '1');
sig_dfifo_tlast_out <= sig_data_fifo_data_out(TLAST_OUT_INDEX) ;
sig_dfifo_cmd_cmplt_out <= sig_data_fifo_data_out(CMPLT_OUT_INDEX) ;
sig_dfifo_dre_flush_out <= sig_data_fifo_data_out(DRE_FLUSH_OUT_INDEX) ;
end generate GEN_MM2S_TKEEP_DISABLE3;
-- Stall Threshold calculations
sig_fifo_wr_cnt_unsgnd <= UNSIGNED(sig_data_fifo_wr_cnt);
sig_wrcnt_mblen_slice <= sig_fifo_wr_cnt_unsgnd(DATA_FIFO_CNT_WIDTH-1 downto
DF_WRCNT_RIP_LS_INDEX);
sig_commit_plus_actual <= RESIZE(sig_tokens_commited, THRESH_COMPARE_WIDTH) +
RESIZE(sig_wrcnt_mblen_slice, THRESH_COMPARE_WIDTH);
-- Compare the commited read space plus the actual used space against the
-- stall threshold. Assert the read address posting stall flag if the
-- threshold is met or exceeded.
sig_stall_rd_addr_posts <= '1'
when (sig_commit_plus_actual > RD_ADDR_POST_STALL_THRESH_US)
Else '0';
-- FIFO Rd/WR Controls
sig_push_data_fifo <= sig_good_sin_strm_dbeat;
-- sig_pop_data_fifo <= sig_sout2sf_tready and
-- sig_data_fifo_dvalid;
GEN_MM2S_TKEEP_ENABLE2 : if C_ENABLE_MM2S_TKEEP = 1 generate
begin
-- Concatonate the Stream inputs into the single FIFO data in value
sig_data_fifo_data_in <= data2sf_dre_flush & -- ms Field
data2sf_cmd_cmplt &
sin2sf_tlast &
sin2sf_tkeep &
sin2sf_tdata; -- ls field
end generate GEN_MM2S_TKEEP_ENABLE2;
GEN_MM2S_TKEEP_DISABLE2 : if C_ENABLE_MM2S_TKEEP = 0 generate
begin
-- Concatonate the Stream inputs into the single FIFO data in value
sig_data_fifo_data_in <= data2sf_dre_flush & -- ms Field
data2sf_cmd_cmplt &
sin2sf_tlast &
--sin2sf_tkeep &
sin2sf_tdata; -- ls field
end generate GEN_MM2S_TKEEP_DISABLE2;
------------------------------------------------------------
-- Instance: I_DATA_FIFO
--
-- Description:
-- Implements the Store and Forward data FIFO (synchronous)
--
------------------------------------------------------------
I_DATA_FIFO : entity axi_datamover_v5_1_9.axi_datamover_sfifo_autord
generic map (
C_DWIDTH => DATA_FIFO_WIDTH ,
C_DEPTH => DATA_FIFO_DEPTH ,
C_DATA_CNT_WIDTH => DATA_FIFO_CNT_WIDTH ,
C_NEED_ALMOST_EMPTY => NOT_NEEDED ,
C_NEED_ALMOST_FULL => NOT_NEEDED ,
C_USE_BLKMEM => BLK_MEM_FIFO ,
C_FAMILY => C_FAMILY
)
port map (
-- Inputs
SFIFO_Sinit => reset ,
SFIFO_Clk => aclk ,
SFIFO_Wr_en => sig_push_data_fifo ,
SFIFO_Din => sig_data_fifo_data_in ,
SFIFO_Rd_en => sig_pop_data_fifo ,
SFIFO_Clr_Rd_Data_Valid => LOGIC_LOW ,
-- Outputs
SFIFO_DValid => sig_data_fifo_dvalid ,
SFIFO_Dout => sig_data_fifo_data_out ,
SFIFO_Full => sig_data_fifo_full ,
SFIFO_Empty => open ,
SFIFO_Almost_full => open ,
SFIFO_Almost_empty => open ,
SFIFO_Rd_count => open ,
SFIFO_Rd_count_minus1 => open ,
SFIFO_Wr_count => sig_data_fifo_wr_cnt ,
SFIFO_Rd_ack => open
);
end implementation;
|
architecture ARCH of ENTITY1 is
begin
U_INST1 : entity fifo_dsn.INST1(rtl);
U_INST2 : component INST2
generic map (
G_GEN_1 => 3,
G_GEN_2 => 4,
G_GEN_3 => 5
);
U_INST3 : INST3
generic map (
G_GEN_1 => 3,
G_GEN_2 => 4,
G_GEN_3 => 5
)
port map (
PORT_1 => w_port_1,
PORT_2 => w_port_2,
PORT_3 => w_port_3
);
-- Violation below
U_INST1 : entity fifo_dsn.INST1(rtl)
;
U_INST2 : component INST2
generic map (
G_GEN_1 => 3,
G_GEN_2 => 4,
G_GEN_3 => 5
)
;
U_INST3 : INST3
generic map (
G_GEN_1 => 3,
G_GEN_2 => 4,
G_GEN_3 => 5
)
port map (
PORT_1 => w_port_1,
PORT_2 => w_port_2,
PORT_3 => w_port_3
)
;
end architecture ARCH;
|
--
-- Copyright (C) 2009-2012 Chris McClelland
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity sdram is
port(
clk_in : in std_logic;
reset_in : in std_logic;
-- DVR interface -----------------------------------------------------------------------------
--chanAddr_in : in std_logic_vector(6 downto 0); -- the selected channel (0-127)
-- Host >> FPGA pipe:
h2fData_in : in std_logic_vector(7 downto 0); -- data lines used when the host writes to a channel
h2fValid_in : in std_logic; -- '1' means "on the next clock rising edge, please accept the data on h2fData"
h2fReady_out : out std_logic; -- channel logic can drive this low to say "I'm not ready for more data yet"
-- Host << FPGA pipe:
f2hData_out : out std_logic_vector(7 downto 0); -- data lines used when the host reads from a channel
f2hValid_out : out std_logic; -- channel logic can drive this low to say "I don't have data ready for you"
f2hReady_in : in std_logic; -- '1' means "on the next clock rising edge, put your next byte of data on f2hData"
-- SDRAM interface ---------------------------------------------------------------------------
ramCmd_out : out std_logic_vector(2 downto 0);
ramBank_out : out std_logic_vector(1 downto 0);
ramAddr_out : out std_logic_vector(11 downto 0);
ramData_io : inout std_logic_vector(15 downto 0);
ramLDQM_out : out std_logic;
ramUDQM_out : out std_logic
);
end entity;
|
--
-- This file is part of IP_register
-- Copyright (C) 2011 Julien Thevenon ( julien_thevenon at yahoo.fr )
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity my_register is
generic (
size : natural := 1);-- size
port (
clk : in std_logic; -- clock
rst : in std_logic; --rst
input : in std_logic_vector(size - 1 downto 0); -- input
output : out std_logic_vector(size -1 downto 0) -- output
-- input : in std_logic_vector; -- input
-- output : out std_logic_vector -- output
);
end my_register;
architecture behavourial of my_register is
begin -- behavourial
my_register: process(clk,rst)
begin
if rising_edge(clk) then
if rst = '1' then
output <= (others => '0');
else
output <= input;
end if;
end if;
end process;
end behavourial;
|
-- $Id: tb_s3board_core.vhd 476 2013-01-26 22:23:53Z mueller $
--
-- Copyright 2010-2011 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: tb_s3board_core - sim
-- Description: Test bench for s3board - core device handling
--
-- Dependencies: vlib/parts/issi/is61lv25616al
--
-- To test: generic, any s3board target
--
-- Target Devices: generic
-- Tool versions: xst 11.4, 13.1; ghdl 0.26-0.29
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-19 427 1.0.2 now numeric_std clean
-- 2010-05-02 287 1.0.1 add sbaddr_(swi|btn) defs, now sbus addr 16,17
-- 2010-04-24 282 1.0 Initial version (from vlib/s3board/tb/tb_s3board)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.slvtypes.all;
use work.serportlib.all;
use work.simbus.all;
entity tb_s3board_core is
port (
I_SWI : out slv8; -- s3 switches
I_BTN : out slv4; -- s3 buttons
O_MEM_CE_N : in slv2; -- sram: chip enables (act.low)
O_MEM_BE_N : in slv4; -- sram: byte enables (act.low)
O_MEM_WE_N : in slbit; -- sram: write enable (act.low)
O_MEM_OE_N : in slbit; -- sram: output enable (act.low)
O_MEM_ADDR : in slv18; -- sram: address lines
IO_MEM_DATA : inout slv32 -- sram: data lines
);
end tb_s3board_core;
architecture sim of tb_s3board_core is
signal R_SWI : slv8 := (others=>'0');
signal R_BTN : slv4 := (others=>'0');
constant sbaddr_swi: slv8 := slv(to_unsigned( 16,8));
constant sbaddr_btn: slv8 := slv(to_unsigned( 17,8));
begin
MEM_L : entity work.is61lv25616al
port map (
CE_N => O_MEM_CE_N(0),
OE_N => O_MEM_OE_N,
WE_N => O_MEM_WE_N,
UB_N => O_MEM_BE_N(1),
LB_N => O_MEM_BE_N(0),
ADDR => O_MEM_ADDR,
DATA => IO_MEM_DATA(15 downto 0)
);
MEM_U : entity work.is61lv25616al
port map (
CE_N => O_MEM_CE_N(1),
OE_N => O_MEM_OE_N,
WE_N => O_MEM_WE_N,
UB_N => O_MEM_BE_N(3),
LB_N => O_MEM_BE_N(2),
ADDR => O_MEM_ADDR,
DATA => IO_MEM_DATA(31 downto 16)
);
proc_simbus: process (SB_VAL)
begin
if SB_VAL'event and to_x01(SB_VAL)='1' then
if SB_ADDR = sbaddr_swi then
R_SWI <= to_x01(SB_DATA(R_SWI'range));
end if;
if SB_ADDR = sbaddr_btn then
R_BTN <= to_x01(SB_DATA(R_BTN'range));
end if;
end if;
end process proc_simbus;
I_SWI <= R_SWI;
I_BTN <= R_BTN;
end sim;
|
--------------------------------------------------------------------------------
-- Company: Dossmatik GmbH
-- Create Date: 21:08:31 05/17/2011
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench
-- test for VHPI
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.sim_pkg.all;
entity tb_cosim is
end tb_cosim;
architecture behavior of tb_cosim is
function crc (crc_value : std_logic_vector(31 downto 0)
) return std_logic_vector is
variable crc_out : std_logic_vector(31 downto 0);
begin
crc_out := (crc(3 downto 0)& crc_out(31 downto 4)) xor crc;
return crc_out;
end crc;
signal random : std_logic_vector ( 31 downto 0):=X"00000000";
-- Clock period definitions
constant board_clk_period : time := 20 ns;
signal board_clk: std_logic;
begin
process (board_clk)
begin
if rising_edge(board_clk) then
street(to_integer(unsigned(random)));
random<=crc(random);
end if;
end process;
-- Clock process definitions
board_clk_process : process
begin
board_clk <= '0';
wait for board_clk_period/2;
board_clk <= '1';
wait for board_clk_period/2;
end process;
end;
|
--------------------------------------------------------------------------------
-- Company: Dossmatik GmbH
-- Create Date: 21:08:31 05/17/2011
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench
-- test for VHPI
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.sim_pkg.all;
entity tb_cosim is
end tb_cosim;
architecture behavior of tb_cosim is
function crc (crc_value : std_logic_vector(31 downto 0)
) return std_logic_vector is
variable crc_out : std_logic_vector(31 downto 0);
begin
crc_out := (crc(3 downto 0)& crc_out(31 downto 4)) xor crc;
return crc_out;
end crc;
signal random : std_logic_vector ( 31 downto 0):=X"00000000";
-- Clock period definitions
constant board_clk_period : time := 20 ns;
signal board_clk: std_logic;
begin
process (board_clk)
begin
if rising_edge(board_clk) then
street(to_integer(unsigned(random)));
random<=crc(random);
end if;
end process;
-- Clock process definitions
board_clk_process : process
begin
board_clk <= '0';
wait for board_clk_period/2;
board_clk <= '1';
wait for board_clk_period/2;
end process;
end;
|
-------------------------------------------------------------------------------
--
-- Title : R4B user core
-- Design : r4b
-- Author : Bulent Selek
-- Company : Best Bilgisayar ve Elektronik Sanayi Ticaret
--
-------------------------------------------------------------------------------
--
-- File : ts7300_usercore.vhd
-- Generated : Fri Jan 8 13:22:36 2007
--
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Modified by Nigel Gunton
-- Company : Bristol Institute of Technology
-- version 1.0
-- full access to the DIO pins split into 3 registers plus output enable registers
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ts7300_usercore is
-- 75Mhz clock is fed to this module */
port (
wb_clk_i : in std_logic;
wb_rst_i : in std_logic;
wb_adr_i : in std_logic_vector ( 21 downto 0 );
wb_dat_i : in std_logic_vector ( 31 downto 0 );
wb_cyc_i : in std_logic;
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_dat_o : out std_logic_vector ( 31 downto 0 );
headerpin_i : in std_logic_vector( 40 downto 1 );
headerpin_o : out std_logic_vector( 40 downto 1 );
headerpin_oe_o : out std_logic_vector( 40 downto 1 );
irq_o : out std_logic;
-- SDRAM
sdram_ras_o : out std_logic; -- SDRAM row address strobe
sdram_cas_o : out std_logic; -- SDRAM column address strobe
sdram_we_n_o : out std_logic; -- SDRAM write enable
sdram_ba_o : out std_logic_vector( 1 downto 0 ); -- SDRAM bank address
sdram_saddr_o : out std_logic_vector( 11 downto 0 ); -- SDRAM row/column address
sdram_sdata_i : in std_logic_vector ( 15 downto 0 ); -- data from SDRAM
sdram_sdata_o : out std_logic_vector ( 15 downto 0 ); -- data to SDRAM
sdram_sdata_oe : out std_logic -- true if data is output to SDRAM on sDOut
);
end ts7300_usercore;
architecture ts7300_usercore of ts7300_usercore is
--- PWM Stuff ---
component pwm
port (
clk : in std_logic;
duty_cycle : in std_logic_vector(15 downto 0);
pwm_enable : in std_logic;
resetn : in std_logic;
pwm_out : out std_logic);
end component;
constant deadbeaf : std_logic_vector( 31 downto 0 ) := x"deadcafe";
signal vga_reg : std_logic_vector( 14 downto 0 ); -- only 14 downto 0 valid
signal dio2_reg : std_logic_vector( 15 downto 0 ); -- only 15 downto 0 valid
signal dummyreg : std_logic_vector( 31 downto 0 ); -- temporary reg
signal misc_reg : std_logic_vector( 3 downto 0 ); -- only 3 downto 0 valid
signal vga_enable : std_logic_vector( 14 downto 0 ); -- 1 = output enabled
signal dio2_enable : std_logic_vector( 15 downto 0 ); -- ditto
signal misc_enable : std_logic_vector( 3 downto 0 ); -- ditto
signal vga_read : std_logic_vector(14 downto 0); -- read from I/O pins
signal dio2_read : std_logic_vector(15 downto 0); -- ditto
signal misc_read : std_logic_vector(3 downto 0); -- ditto
signal DUTY_CYCLEA : std_logic_vector(15 downto 0) := X"006F";
signal DUTY_CYCLEB : std_logic_vector(15 downto 0) := X"006F";
signal DUTY_CYCLEC : std_logic_vector(15 downto 0) := X"006F";
signal DUTY_CYCLED : std_logic_vector(15 downto 0) := X"006F";
signal PWM_not_reset, PWM_enable_A, PWM_enable_B, PWM_enable_C, PWM_enable_D : std_logic := '1';
--- Read and write cycles of FPGA by and to the Processor
begin
process ( wb_clk_i )
variable addr : std_logic_vector ( 23 downto 0 );
begin
if ( wb_clk_i'event ) and ( wb_clk_i = '1' ) then
addr := "00" & wb_adr_i;
if (wb_cyc_i = '1' and wb_stb_i = '1' ) and ( wb_we_i = '1') then
-- WRITE CYCLE
case addr is
when x"280000" => vga_reg <= wb_dat_i(14 downto 0);
when x"280001" => vga_enable <= wb_dat_i(14 downto 0);
when x"280002" => dio2_reg <= wb_dat_i(15 downto 0);
when x"280003" => dio2_enable <= wb_dat_i(15 downto 0);
when x"280004" => misc_reg <= wb_dat_i(3 downto 0);
when x"280005" => misc_enable <= wb_dat_i(3 downto 0);
when x"280006" => DUTY_CYCLEA <= wb_dat_i(15 downto 0);
when x"280007" => DUTY_CYCLEB <= wb_dat_i(15 downto 0);
when x"280008" => DUTY_CYCLEC <= wb_dat_i(15 downto 0);
when x"280009" => DUTY_CYCLED <= wb_dat_i(15 downto 0);
when x"28000A" => PWM_enable_A <= wb_dat_i(0);
when x"28000B" => PWM_enable_B <= wb_dat_i(0);
when x"28000C" => PWM_enable_C <= wb_dat_i(0);
when x"28000D" => PWM_enable_D <= wb_dat_i(0);
when x"28000E" => PWM_not_reset <= wb_dat_i(0);
when others => null;
end case;
end if;
-- READ CYCLE
case addr is
when x"280000" => dummyreg <= "00000000000000000" & vga_read;
when x"280001" => dummyreg <= "00000000000000000" & vga_enable;
when x"280002" => dummyreg <= "0000000000000000" & dio2_read;
when x"280003" => dummyreg <= "0000000000000000" & dio2_enable;
when x"280004" => dummyreg <= "0000000000000000000000000000" & misc_read;
when x"280005" => dummyreg <= "0000000000000000000000000000" & misc_enable;
when x"280006" => dummyreg <= "0000000000000000" & DUTY_CYCLEA;
when x"280007" => dummyreg <= "0000000000000000" & DUTY_CYCLEB;
when x"280008" => dummyreg <= "0000000000000000" & DUTY_CYCLEC;
when x"280009" => dummyreg <= "0000000000000000" & DUTY_CYCLED;
when x"28000A" => dummyreg <= "0000000000000000000000000000000" & PWM_enable_A;
when x"28000B" => dummyreg <= "0000000000000000000000000000000" & PWM_enable_B;
when x"28000C" => dummyreg <= "0000000000000000000000000000000" & PWM_enable_C;
when x"28000D" => dummyreg <= "0000000000000000000000000000000" & PWM_enable_D;
when x"28000E" => dummyreg <= "0000000000000000000000000000000" & PWM_not_reset ;
when others => dummyreg <= x"deadbeef";
end case;
end if;
end process;
wb_ack_o <= wb_cyc_i and wb_stb_i; -- 0-wait state WISHBONE
wb_dat_o <= dummyreg;
irq_o <= '0';
-------------------------------------------------------------------------------
-- FPGA DIO output enable assignments: 40 downto 1
-- What follows is a pigs ear of assignments as the output enables are in pin
-- number order and the enable registers are in data name order
-------------------------------------------------------------------------------
headerpin_oe_o(1) <= vga_enable(0); -- blu0
headerpin_oe_o(3) <= vga_enable(1); -- blu1
headerpin_oe_o(5) <= vga_enable(2); -- blu2
headerpin_oe_o(7) <= vga_enable(3); -- blu3
headerpin_oe_o(9) <= vga_enable(4); -- blu4
headerpin_oe_o(11) <= vga_enable(5); -- grn0
headerpin_oe_o(13) <= vga_enable(6); -- grn1
headerpin_oe_o(15) <= vga_enable(7); -- grn2
headerpin_oe_o(17) <= vga_enable(8); -- grn3
headerpin_oe_o(4) <= vga_enable(10); -- red0
headerpin_oe_o(6) <= vga_enable(11); -- red1
headerpin_oe_o(8) <= vga_enable(12); -- red2
headerpin_oe_o(10) <= vga_enable(13); -- red3
headerpin_oe_o(12) <= vga_enable(14); -- red4
--headerpin_oe_o(19) <= '1';
headerpin_oe_o(21) <= '1';
headerpin_oe_o(23) <= '1';
headerpin_oe_o(25) <= '1';
headerpin_oe_o(29) <= '1';
-- headerpin_oe_o(29) <= dio2_enable(4); -- DIO2
headerpin_oe_o(31) <= dio2_enable(5); -- DIO2
headerpin_oe_o(33) <= dio2_enable(6); -- DIO2
headerpin_oe_o(35) <= dio2_enable(7); -- DIO2
headerpin_oe_o(37) <= dio2_enable(8); -- DIO2
-- THE FOLLOWING PIN IS DEDICATED CLK INPUT ONLY
-- headerpin_oe_o(39) <= dio2_enable(9); -- DIO2
headerpin_oe_o(24) <= dio2_enable(10); -- DIO2
headerpin_oe_o(26) <= dio2_enable(11); -- DIO2
headerpin_oe_o(28) <= dio2_enable(12); -- DIO2
headerpin_oe_o(30) <= dio2_enable(13); -- DIO2
headerpin_oe_o(32) <= dio2_enable(14); -- DIO2
headerpin_oe_o(34) <= dio2_enable(15); -- DIO2
headerpin_oe_o(14) <= misc_enable(0); -- HSYNC
headerpin_oe_o(16) <= misc_enable(1); -- VSYNC
headerpin_oe_o(36) <= misc_enable(2); -- RX_LD
headerpin_oe_o(38) <= misc_enable(3); -- TX_LD
-- the following MUST NOT be altered as they have dedicated use
headerpin_oe_o(2) <= '0'; -- GND
headerpin_oe_o(18) <= '0'; -- OEV
headerpin_oe_o(20) <= '0'; -- +5v fused
headerpin_oe_o(22) <= '0'; -- GND
headerpin_oe_o(39) <= '0'; -- external clk input only
headerpin_oe_o(40) <= '0'; -- +3.3v
-------------------------------------------------------------------------------
-- output assignments
-------------------------------------------------------------------------------
headerpin_o(1) <= vga_reg(0); --blu0
headerpin_o(3) <= vga_reg(1); --blu1
headerpin_o(5) <= vga_reg(2); --blu2
headerpin_o(6) <= vga_reg(3); --blu3
headerpin_o(7) <= vga_reg(4); --blu4
headerpin_o(11) <= vga_reg(5); --grn0
headerpin_o(13) <= vga_reg(6); --grn1
headerpin_o(15) <= vga_reg(7); --grn2
headerpin_o(17) <= vga_reg(8); --grn3
-- headerpin_o(29) <= dio2_reg(4); -- DIO2
headerpin_o(31) <= dio2_reg(5); -- DIO2
headerpin_o(33) <= dio2_reg(6); -- DIO2
headerpin_o(35) <= dio2_reg(7); -- DIO2
headerpin_o(37) <= dio2_reg(8); -- DIO2
-- THE FOLLOWING PIN IS INPUT ONLY
-- headerpin_o(39) <= dio2_reg(9); -- DIO2
headerpin_o(24) <= dio2_reg(10); -- DIO2
headerpin_o(26) <= dio2_reg(11); -- DIO2
headerpin_o(28) <= dio2_reg(12); -- DIO2
headerpin_o(30) <= dio2_reg(13); -- DIO2
headerpin_o(32) <= dio2_reg(14); -- DIO2
headerpin_o(34) <= dio2_reg(15); -- DIO2
headerpin_o(14) <= misc_reg(0); -- HSYNC
headerpin_o(16) <= misc_reg(1); -- VSYNC
headerpin_o(36) <= misc_reg(2); -- RX_LD
headerpin_o(38) <= misc_reg(3); -- TX_LD
-- just to keep synthesis warnings down ;)
headerpin_o(2) <= '0'; -- GND
headerpin_o(18) <= '0'; -- OEV
headerpin_o(20) <= '0'; -- +5v fused
headerpin_o(22) <= '0'; -- GND
headerpin_o(40) <= '0'; -- +3.3v
-----------------------------------------------------------------------------
-- read values on the IO pins; the special pins are handled in ts7300_top.v
-----------------------------------------------------------------------------
vga_read(0) <= headerpin_i(1); -- blu0
vga_read(1) <= headerpin_i(3); -- blu1
vga_read(2) <= headerpin_i(5); -- blu2
vga_read(3) <= headerpin_i(7); -- blu3
vga_read(4) <= headerpin_i(9); -- blu4
vga_read(5) <= headerpin_i(11); -- grn0
vga_read(6) <= headerpin_i(13); -- grn1
vga_read(7) <= headerpin_i(15); -- grn2
vga_read(8) <= headerpin_i(17); -- grn3
dio2_read(0) <= headerpin_i(21); -- DIO2
dio2_read(1) <= headerpin_i(23); -- DIO2
dio2_read(2) <= headerpin_i(25); -- DIO2
dio2_read(3) <= headerpin_i(27); -- DIO2
dio2_read(4) <= headerpin_i(29); -- DIO2
dio2_read(5) <= headerpin_i(31); -- DIO2
dio2_read(6) <= headerpin_i(33); -- DIO2
dio2_read(7) <= headerpin_i(35); -- DIO2
dio2_read(8) <= headerpin_i(37); -- DIO2
-- dio2_read(9) deliberately left out; see above
dio2_read(10) <= headerpin_i(24); -- DIO2
dio2_read(11) <= headerpin_i(26); -- DIO2
dio2_read(12) <= headerpin_i(28); -- DIO2
dio2_read(13) <= headerpin_i(30); -- DIO2
dio2_read(14) <= headerpin_i(32); -- DIO2
dio2_read(15) <= headerpin_i(34); -- DIO2
misc_read(0) <= headerpin_i(14); -- HSYNC
misc_read(1) <= headerpin_i(16); -- VSYNC
misc_read(2) <= headerpin_i(36); -- RX_LD but not a lot of point
misc_read(3) <= headerpin_i(38); -- TX_LD
PWM_1:pwm
port map (
clk => wb_clk_i,
duty_cycle => DUTY_CYCLEA,
pwm_enable => PWM_enable_A,--Enable_output_A,
resetn => PWM_not_reset,
pwm_out => headerpin_o(21));
PWM_2:pwm
port map (
clk => wb_clk_i,
duty_cycle => DUTY_CYCLEB,
pwm_enable => PWM_enable_B,--Enable_output_B,
resetn => PWM_not_reset,
pwm_out => headerpin_o(23));
PWM_3:pwm
port map (
clk => wb_clk_i,
duty_cycle => DUTY_CYCLEC,
pwm_enable => PWM_enable_C,--Enable_output_C,
resetn => PWM_not_reset,
pwm_out => headerpin_o(25));
PWM_4:pwm
port map (
clk => wb_clk_i,
duty_cycle => DUTY_CYCLED,
pwm_enable => PWM_enable_D,--Enable_output_D,
resetn => PWM_not_reset,
pwm_out => headerpin_o(29));
end ts7300_usercore;
|
entity paren3 is
end paren3;
architecture behav of paren3
is
subtype a is integer;
constant b : real := 3.15;
begin
assert a(b) = 3;
end behav;
|
entity paren3 is
end paren3;
architecture behav of paren3
is
subtype a is integer;
constant b : real := 3.15;
begin
assert a(b) = 3;
end behav;
|
entity paren3 is
end paren3;
architecture behav of paren3
is
subtype a is integer;
constant b : real := 3.15;
begin
assert a(b) = 3;
end behav;
|
architecture RTL of FIFO is
begin
process
begin
if a = '1' then
b <= '0';
elsif c = '1' then
b <= '1';
else
if x = '1' then
z <= '0';
elsif x = '0' then
z <= '1';
else
z <= 'Z';
END if;
END if;
-- Violations below
if a = '1' then
b <= '0';
elsif c = '1' then
b <= '1';
else
if x = '1' then
z <= '0';
elsif x = '0' then
z <= '1';
else
z <= 'Z';
END if;
END if;
end process;
end architecture RTL;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use WORK.alu_types.all;
-- Behavioral
entity SUMGENERATOR is
generic(
NBIT: integer := NSUMG; --32,64
NCSB: integer := NCSUMG --8,16
);
port (
A: in std_logic_vector(NBIT-1 downto 0);
B: in std_logic_vector(NBIT-1 downto 0);
Ci: in std_logic_vector(NCSB-1 downto 0);
S: out std_logic_vector(NBIT-1 downto 0)
);
end SUMGENERATOR;
-- Architectures
architecture structural of SUMGENERATOR is
component CSB
generic(
N: integer := NCSBLOCK -- 4
);
port (
A: in std_logic_vector(N-1 downto 0);
B: in std_logic_vector(N-1 downto 0);
Ci: in std_logic;
S: out std_logic_vector(N-1 downto 0)
);
end component;
begin
-- For NCSBLOCK and others constants refer to P4ADDER_constants file.
-- This structural architecture generates (NCSB - 1) carry selects block of NCSBLOCK bits,
-- which is the number of carry bits generated by the sparse tree, plus 1, that is the carry in.
CS: for i in 0 to NCSB-1 generate
CSBX: CSB
port map(
A(((i*NCSBLOCK)+NCSBLOCK-1) downto i*NCSBLOCK),
B(((i*NCSBLOCK)+NCSBLOCK-1) downto i*NCSBLOCK),
Ci(i),
S(((i*NCSBLOCK)+NCSBLOCK-1) downto i*NCSBLOCK)
);
end generate;
end structural;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1558.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s10b00x00p03n01i01558ent IS
END c08s10b00x00p03n01i01558ent;
ARCHITECTURE c08s10b00x00p03n01i01558arch OF c08s10b00x00p03n01i01558ent IS
BEGIN
TESTING: PROCESS
variable k : integer := 0;
BEGIN
L : for i in 1 to 10 loop
next L;
k := 5;
end loop;
assert NOT( k=0 )
report "***PASSED TEST: c08s10b00x00p03n01i01558"
severity NOTE;
assert ( k=0 )
report "***FAILED TEST: c08s10b00x00p03n01i01558 - a next statement with a loop label is allowed inside a labeled loop"
severity ERROR;
wait;
END PROCESS TESTING;
END c08s10b00x00p03n01i01558arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1558.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s10b00x00p03n01i01558ent IS
END c08s10b00x00p03n01i01558ent;
ARCHITECTURE c08s10b00x00p03n01i01558arch OF c08s10b00x00p03n01i01558ent IS
BEGIN
TESTING: PROCESS
variable k : integer := 0;
BEGIN
L : for i in 1 to 10 loop
next L;
k := 5;
end loop;
assert NOT( k=0 )
report "***PASSED TEST: c08s10b00x00p03n01i01558"
severity NOTE;
assert ( k=0 )
report "***FAILED TEST: c08s10b00x00p03n01i01558 - a next statement with a loop label is allowed inside a labeled loop"
severity ERROR;
wait;
END PROCESS TESTING;
END c08s10b00x00p03n01i01558arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1558.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s10b00x00p03n01i01558ent IS
END c08s10b00x00p03n01i01558ent;
ARCHITECTURE c08s10b00x00p03n01i01558arch OF c08s10b00x00p03n01i01558ent IS
BEGIN
TESTING: PROCESS
variable k : integer := 0;
BEGIN
L : for i in 1 to 10 loop
next L;
k := 5;
end loop;
assert NOT( k=0 )
report "***PASSED TEST: c08s10b00x00p03n01i01558"
severity NOTE;
assert ( k=0 )
report "***FAILED TEST: c08s10b00x00p03n01i01558 - a next statement with a loop label is allowed inside a labeled loop"
severity ERROR;
wait;
END PROCESS TESTING;
END c08s10b00x00p03n01i01558arch;
|
--*****************************************************************************
--* Copyright (c) 2012 by Michael Fischer. All rights reserved.
--*
--* Redistribution and use in source and binary forms, with or without
--* modification, are permitted provided that the following conditions
--* are met:
--*
--* 1. Redistributions of source code must retain the above copyright
--* notice, this list of conditions and the following disclaimer.
--* 2. Redistributions in binary form must reproduce the above copyright
--* notice, this list of conditions and the following disclaimer in the
--* documentation and/or other materials provided with the distribution.
--* 3. Neither the name of the author nor the names of its contributors may
--* be used to endorse or promote products derived from this software
--* without specific prior written permiSS_asyncion.
--*
--* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
--* "AS IS" AND ANY EXPRESS_async OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
--* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS_async
--* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
--* THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
--* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
--* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS_async
--* OF USE, DATA, OR PROFITS; OR BUSINESS_async INTERRUPTION) HOWEVER CAUSED
--* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
--* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
--* THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSS_asyncIBILITY OF
--* SUCH DAMAGE.
--*
--*****************************************************************************
--* History:
--*
--* 14.07.2011 mifi First Version
--*****************************************************************************
--*****************************************************************************
--* DEFINE: Library *
--*****************************************************************************
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use ieee.std_logic_arith.all;
--*****************************************************************************
--* DEFINE: Entity *
--*****************************************************************************
entity uart_halfduplex is
port(
clk : in std_logic;
rst : in std_logic;
parallell_data_out : out std_logic_vector(7 downto 0);
parallell_data_out_valid : out std_logic;
uart_data_in : in std_logic;
parallell_data_in : in std_logic_vector(7 downto 0);
parallell_data_in_valid : in std_logic;
parallell_data_in_sent : out std_logic;
uart_data_out : out std_logic;
rts : out std_logic
);
end entity uart_halfduplex;
--*****************************************************************************
--* DEFINE: Architecture *
--****************************************************************************
architecture syn of uart_halfduplex is
component txuart is
port(
clk : in std_logic;
rst : in std_logic;
parallell_data_in : in std_logic_vector(7 downto 0);
parallell_data_in_valid : in std_logic;
parallell_data_in_sent : out std_logic;
uart_data_out : out std_logic;
busy : out std_logic
);
end component;
component rxuart is
port(
clk : in std_logic;
rst : in std_logic;
parallell_data_out : out std_logic_vector(7 downto 0);
parallell_data_out_valid : out std_logic;
uart_data_in_ext : in std_logic
);
end component;
begin
inst_txuart : txuart
port map(
clk => clk,
rst => rst,
parallell_data_in => parallell_data_in,
parallell_data_in_valid => parallell_data_in_valid,
parallell_data_in_sent => parallell_data_in_sent,
uart_data_out => uart_data_out,
busy => rts
);
inst_rxuart : rxuart
port map(
clk => clk,
rst => rst,
parallell_data_out => parallell_data_out,
parallell_data_out_valid => parallell_data_out_valid,
uart_data_in_ext => uart_data_in
);
end architecture syn;
-- *** EOF ***
|
entity e is
end entity;
architecture a of e is
begin
process
type LongInteger is range -2**47 to 2**47-1;
variable v : LongInteger;
begin
v := 12345678901;
report "v = " & LongInteger'image(v) severity note;
-- report "v = " & to_string(v) severity note; -- works
-- report "v = " & to_string(LongInteger'pos(v)) severity note; -- works
wait;
end process;
end architecture;
|
entity e is
end entity;
architecture a of e is
begin
process
type LongInteger is range -2**47 to 2**47-1;
variable v : LongInteger;
begin
v := 12345678901;
report "v = " & LongInteger'image(v) severity note;
-- report "v = " & to_string(v) severity note; -- works
-- report "v = " & to_string(LongInteger'pos(v)) severity note; -- works
wait;
end process;
end architecture;
|
-- Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2015.2 (lin64) Build 1266856 Fri Jun 26 16:35:25 MDT 2015
-- Date : Mon Nov 30 13:52:22 2015
-- Host : centennial.andrew.cmu.edu running 64-bit Red Hat Enterprise Linux Server release 7.2 (Maipo)
-- Command : write_vhdl -force -mode synth_stub
-- /afs/ece.cmu.edu/usr/rmrobert/Private/18545/Atari7800/Atari7900/Atari7900.srcs/sources_1/ip/DIGDUG_ROM_1/DIGDUG_ROM_stub.vhdl
-- Design : DIGDUG_ROM
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity DIGDUG_ROM is
Port (
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
douta : out STD_LOGIC_VECTOR ( 7 downto 0 )
);
end DIGDUG_ROM;
architecture stub of DIGDUG_ROM is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "clka,addra[13:0],douta[7:0]";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "blk_mem_gen_v8_2,Vivado 2015.2";
begin
end;
|
-- NEED RESULT: ARCH00410.P1: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00410: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00410: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00410: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00410: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: P1: Inertial transactions completed entirely passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00410
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 9.5 (3)
-- 9.5.1 (1)
-- 9.5.1 (2)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00410(ARCH00410)
-- ENT00410_Test_Bench(ARCH00410_Test_Bench)
--
-- REVISION HISTORY:
--
-- 30-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
entity ENT00410 is
end ENT00410 ;
--
--
architecture ARCH00410 of ENT00410 is
subtype chk_sig_type is integer range -1 to 100 ;
signal chk_st_rec3 : chk_sig_type := -1 ;
--
subtype chk_time_type is Time ;
signal s_st_rec3_savt : chk_time_type := 0 ns ;
--
subtype chk_cnt_type is Integer ;
signal s_st_rec3_cnt : chk_cnt_type := 0 ;
--
type select_type is range 1 to 6 ;
signal st_rec3_select : select_type := 1 ;
--
signal s_st_rec3 : st_rec3
:= c_st_rec3_1 ;
--
begin
CHG1 :
process
variable correct : boolean ;
begin
case s_st_rec3_cnt is
when 0
=> null ;
-- s_st_rec3.f3(lowb,true) <=
-- c_st_rec3_2.f3(lowb,true) after 10 ns,
-- c_st_rec3_1.f3(lowb,true) after 20 ns ;
--
when 1
=> correct :=
s_st_rec3.f3(lowb,true) =
c_st_rec3_2.f3(lowb,true) and
(s_st_rec3_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec3.f3(lowb,true) =
c_st_rec3_1.f3(lowb,true) and
(s_st_rec3_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00410.P1" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_rec3_select <= transport 2 ;
-- s_st_rec3.f3(lowb,true) <=
-- c_st_rec3_2.f3(lowb,true) after 10 ns ,
-- c_st_rec3_1.f3(lowb,true) after 20 ns ,
-- c_st_rec3_2.f3(lowb,true) after 30 ns ,
-- c_st_rec3_1.f3(lowb,true) after 40 ns ;
--
when 3
=> correct :=
s_st_rec3.f3(lowb,true) =
c_st_rec3_2.f3(lowb,true) and
(s_st_rec3_savt + 10 ns) = Std.Standard.Now ;
st_rec3_select <= transport 3 ;
-- s_st_rec3.f3(lowb,true) <=
-- c_st_rec3_1.f3(lowb,true) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec3.f3(lowb,true) =
c_st_rec3_1.f3(lowb,true) and
(s_st_rec3_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00410" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_rec3_select <= transport 4 ;
-- s_st_rec3.f3(lowb,true) <=
-- c_st_rec3_1.f3(lowb,true) after 100 ns ;
--
when 5
=> correct :=
correct and
s_st_rec3.f3(lowb,true) =
c_st_rec3_1.f3(lowb,true) and
(s_st_rec3_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00410" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
st_rec3_select <= transport 5 ;
-- s_st_rec3.f3(lowb,true) <=
-- c_st_rec3_2.f3(lowb,true) after 10 ns ,
-- c_st_rec3_1.f3(lowb,true) after 20 ns ,
-- c_st_rec3_2.f3(lowb,true) after 30 ns ,
-- c_st_rec3_1.f3(lowb,true) after 40 ns ;
--
when 6
=> correct :=
correct and
s_st_rec3.f3(lowb,true) =
c_st_rec3_2.f3(lowb,true) and
(s_st_rec3_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00410" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_rec3_select <= transport 6 ;
-- Last transaction above is marked
-- s_st_rec3.f3(lowb,true) <=
-- c_st_rec3_1.f3(lowb,true) after 40 ns ;
--
when 7
=> correct :=
correct and
s_st_rec3.f3(lowb,true) =
c_st_rec3_1.f3(lowb,true) and
(s_st_rec3_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_st_rec3.f3(lowb,true) =
c_st_rec3_1.f3(lowb,true) and
(s_st_rec3_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00410" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00410" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_st_rec3_savt <= transport Std.Standard.Now ;
chk_st_rec3 <= transport s_st_rec3_cnt
after (1 us - Std.Standard.Now) ;
s_st_rec3_cnt <= transport s_st_rec3_cnt + 1 ;
wait until (not s_st_rec3.f3(lowb,true)'Quiet) and
(s_st_rec3_savt /= Std.Standard.Now) ;
--
end process CHG1 ;
--
PGEN_CHKP_1 :
process ( chk_st_rec3 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P1" ,
"Inertial transactions completed entirely",
chk_st_rec3 = 8 ) ;
end if ;
end process PGEN_CHKP_1 ;
--
--
s_st_rec3.f3(lowb,true) <=
c_st_rec3_2.f3(lowb,true) after 10 ns,
c_st_rec3_1.f3(lowb,true) after 20 ns
when st_rec3_select = 1 else
--
c_st_rec3_2.f3(lowb,true) after 10 ns ,
c_st_rec3_1.f3(lowb,true) after 20 ns ,
c_st_rec3_2.f3(lowb,true) after 30 ns ,
c_st_rec3_1.f3(lowb,true) after 40 ns
when st_rec3_select = 2 else
--
c_st_rec3_1.f3(lowb,true) after 5 ns
when st_rec3_select = 3 else
--
c_st_rec3_1.f3(lowb,true) after 100 ns
when st_rec3_select = 4 else
--
c_st_rec3_2.f3(lowb,true) after 10 ns ,
c_st_rec3_1.f3(lowb,true) after 20 ns ,
c_st_rec3_2.f3(lowb,true) after 30 ns ,
c_st_rec3_1.f3(lowb,true) after 40 ns
when st_rec3_select = 5 else
--
-- Last transaction above is marked
c_st_rec3_1.f3(lowb,true) after 40 ns ;
--
end ARCH00410 ;
--
--
use WORK.STANDARD_TYPES.all ;
entity ENT00410_Test_Bench is
end ENT00410_Test_Bench ;
--
--
architecture ARCH00410_Test_Bench of ENT00410_Test_Bench is
begin
L1:
block
component UUT
end component ;
--
for CIS1 : UUT use entity WORK.ENT00410 ( ARCH00410 ) ;
begin
CIS1 : UUT
;
end block L1 ;
end ARCH00410_Test_Bench ;
|
-- **********************************************************
-- Corso di Reti Logiche - Progetto Registratore Portatile
-- Andrea Carrer - 729101
-- Modulo Audio_In_Deserializer.vhd
-- Versione 1.01 - 14.03.2013
-- **********************************************************
-- **********************************************************
-- Lettura dati dall'ADC. I dati vengono ricevuti in seriale
-- e deserializzati, cioe' raggruppati in blocchi da 32 bit.
-- **********************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity Audio_In_Deserializer is
generic (
AUDIO_DATA_WIDTH: integer := 32;
BIT_COUNTER_INIT: std_logic_vector (4 downto 0) := "11111"
);
port (
clk: in std_logic;
reset: in std_logic;
bit_clk_rising_edge: in std_logic;
bit_clk_falling_edge: in std_logic;
left_right_clk_rising_edge: in std_logic;
left_right_clk_falling_edge: in std_logic;
done_channel_sync: in std_logic;
serial_audio_in_data: in std_logic;
read_left_audio_data_en: in std_logic;
read_right_audio_data_en: in std_logic;
left_audio_fifo_read_space: out std_logic_vector(7 downto 0);
right_audio_fifo_read_space: out std_logic_vector(7 downto 0);
left_channel_data: out std_logic_vector(AUDIO_DATA_WIDTH downto 1);
right_channel_data: out std_logic_vector(AUDIO_DATA_WIDTH downto 1)
);
end Audio_In_Deserializer;
architecture behaviour of Audio_In_Deserializer is
component Audio_Bit_Counter is
generic(
BIT_COUNTER_INIT: std_logic_vector(4 downto 0) := "11111"
);
port(
clk: in std_logic;
reset: in std_logic;
bit_clk_rising_edge: in std_logic;
bit_clk_falling_edge: in std_logic;
left_right_clk_rising_edge: in std_logic;
left_right_clk_falling_edge: in std_logic;
counting: out std_logic
);
end component;
component SYNC_FIFO is
generic (
DATA_WIDTH: integer := 32;
DATA_DEPTH: integer := 128;
ADDR_WIDTH: integer := 7
);
port (
clk: in std_logic;
reset: in std_logic;
write_en: in std_logic;
write_data: in std_logic_vector(DATA_WIDTH downto 1);
read_en: in std_logic;
fifo_is_empty: out std_logic;
fifo_is_full: out std_logic;
words_used: out std_logic_vector(ADDR_WIDTH downto 1);
read_data: out std_logic_vector(DATA_WIDTH downto 1)
);
end component;
signal valid_audio_input: std_logic;
signal left_channel_fifo_is_empty: std_logic;
signal right_channel_fifo_is_empty: std_logic;
signal left_channel_fifo_is_full: std_logic;
signal right_channel_fifo_is_full: std_logic;
signal left_channel_fifo_used: std_logic_vector(6 downto 0);
signal right_channel_fifo_used: std_logic_vector(6 downto 0);
signal data_in_shift_reg: std_logic_vector(AUDIO_DATA_WIDTH downto 1);
begin
process(clk)
begin
if (rising_edge(clk)) then
if (reset = '1') then
left_audio_fifo_read_space <= "00000000";
else
left_audio_fifo_read_space(7) <= left_channel_fifo_is_full;
left_audio_fifo_read_space(6 downto 0) <= left_channel_fifo_used;
end if;
end if;
end process;
process(clk)
begin
if (rising_edge(clk)) then
if (reset = '1') then
right_audio_fifo_read_space <= "00000000";
else
right_audio_fifo_read_space(7) <= right_channel_fifo_is_full;
right_audio_fifo_read_space(6 downto 0) <= right_channel_fifo_used;
end if;
end if;
end process;
process(clk)
begin
if (rising_edge(clk)) then
if (reset = '1') then
data_in_shift_reg <= "00000000000000000000000000000000";
elsif (bit_clk_rising_edge='1' and valid_audio_input='1') then
data_in_shift_reg <= data_in_shift_reg((AUDIO_DATA_WIDTH - 1) downto 1) & serial_audio_in_data;
end if;
end if;
end process;
Audio_Out_Bit_Counter: Audio_Bit_Counter generic map (
BIT_COUNTER_INIT => BIT_COUNTER_INIT
)
port map(
clk => clk,
reset => reset,
bit_clk_rising_edge => bit_clk_rising_edge,
bit_clk_falling_edge => bit_clk_falling_edge,
left_right_clk_rising_edge => left_right_clk_rising_edge,
left_right_clk_falling_edge => left_right_clk_falling_edge,
counting => valid_audio_input
);
Audio_In_Left_Channel_FIFO: SYNC_FIFO generic map(
DATA_WIDTH => AUDIO_DATA_WIDTH,
DATA_DEPTH => 128,
ADDR_WIDTH => 7
)
port map (
clk => clk,
reset => reset,
write_en => left_right_clk_falling_edge and not left_channel_fifo_is_full and done_channel_sync,
write_data => data_in_shift_reg,
read_en => read_left_audio_data_en and not left_channel_fifo_is_empty,
fifo_is_empty => left_channel_fifo_is_empty,
fifo_is_full => left_channel_fifo_is_full,
words_used => left_channel_fifo_used,
read_data => left_channel_data
);
Audio_In_Right_Channel_FIFO: SYNC_FIFO generic map(
DATA_WIDTH => AUDIO_DATA_WIDTH,
DATA_DEPTH => 128,
ADDR_WIDTH => 7
)
port map (
clk => clk,
reset => reset,
write_en => left_right_clk_rising_edge and not right_channel_fifo_is_full and done_channel_sync,
write_data => data_in_shift_reg,
read_en => read_right_audio_data_en and not right_channel_fifo_is_empty,
fifo_is_empty => right_channel_fifo_is_empty,
fifo_is_full => right_channel_fifo_is_full,
words_used => right_channel_fifo_used,
read_data => right_channel_data
);
end behaviour; |
architecture RTL of FIFO is
begin
BLOCK_LABEL : block is begin end block BLOCK_LABEL;
-- Violations below
BLOCK_LABEL : block is begin end block BLOCK_LABEL;
end architecture RTL;
|
-- Copyright (C) 2014 Roland Dobai
--
-- This file is part of ZyEHW.
--
-- ZyEHW is free software: you can redistribute it and/or modify it under the
-- terms of the GNU General Public License as published by the Free Software
-- Foundation, either version 3 of the License, or (at your option) any later
-- version.
--
-- ZyEHW is distributed in the hope that it will be useful, but WITHOUT ANY
-- WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
-- FOR A PARTICULAR PURPOSE. See the GNU General Public License for more
-- details.
--
-- You should have received a copy of the GNU General Public License along
-- with ZyEHW. If not, see <http://www.gnu.org/licenses/>.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.zyehw_pkg.all;
entity tb_fifo is
end tb_fifo;
architecture behav_tb_fifo of tb_fifo is
component fifo is
port (
rdclk: in std_logic;
wrclk: in std_logic;
rden: in std_logic;
wren: in std_logic;
datain: in fifo_t;
dataout: out fifo_t;
rderr: out std_logic;
wrerr: out std_logic;
near_full: out std_logic;
half_full: out std_logic
);
end component;
constant t_wr: time:= 18 ns;
constant t_rd: time:= 10 ns;
constant data_low: integer:= 0;
constant data_high: integer:= (2**16)-1;
signal rdclk: std_logic;
signal wrclk: std_logic;
signal rden: std_logic:= '0';
signal wren: std_logic:= '0';
signal write: std_logic;
signal pre_datain, datain: fifo_t;
signal dataout: fifo_t;
signal rderr: std_logic;
signal wrerr: std_logic;
signal near_full: std_logic;
signal half_full: std_logic;
begin
write <= '0', '1' after 10*t_wr;
-- In the axi_data core the write enable is written into a register. Here,
-- the signal write mimics this: it writes the datain into a register and
-- is similarly stored into another register.
process (wrclk)
begin
if wrclk'event and wrclk = '1' then
wren <= write;
if write = '1' then
datain <= pre_datain;
end if;
end if;
end process;
rden_proc: process (rdclk)
variable readon: boolean:= false;
variable i: integer;
variable rd: std_logic;
begin
-- It waits for half_full and then it reads a frame from the fifo
if (rdclk'event and rdclk = '1') then
if (half_full = '1' and readon = false) then
readon:= true;
i:= 0;
end if;
if (readon = true) then
rd := '1';
if (i = 128*128-1) then
readon:= false;
else
i:= i + 1;
end if;
else
rd := '0';
end if;
rden <= rd;
end if;
end process;
datain_proc: process
variable input: integer:= data_low;
variable input_v: std_logic_vector(2*cgp_t'length-1 downto 0);
begin
input_v:= std_logic_vector(to_unsigned(input, input_v'length));
pre_datain.input <= input_v(1*cgp_t'length-1 downto 0*cgp_t'length);
pre_datain.output <= input_v(2*cgp_t'length-1 downto 1*cgp_t'length);
if input = data_high then
input:= data_low;
else
input:= input + 1;
end if;
wait for t_wr;
end process;
rdclk_proc: process
variable tmp_clk: std_logic:= '1';
begin
rdclk <= tmp_clk;
tmp_clk := not tmp_clk;
wait for t_rd / 2;
end process;
wrclk_proc: process
variable tmp_clk: std_logic:= '1';
begin
wrclk <= tmp_clk;
tmp_clk := not tmp_clk;
wait for t_wr / 2;
end process;
fifo_i: fifo
port map (
rdclk => rdclk,
wrclk => wrclk,
rden => rden,
wren => wren,
datain => datain,
dataout => dataout,
rderr => rderr,
wrerr => wrerr,
near_full => near_full,
half_full => half_full
);
end behav_tb_fifo;
|
-- -------------------------------------------------------------
--
-- Entity Declaration for inst_8_e
--
-- Generated
-- by: wig
-- on: Fri Jul 15 13:54:30 2005
-- cmd: h:/work/eclipse/mix/mix_0.pl -nodelta ../macro.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_8_e-e.vhd,v 1.2 2005/07/15 16:20:00 wig Exp $
-- $Date: 2005/07/15 16:20:00 $
-- $Log: inst_8_e-e.vhd,v $
-- Revision 1.2 2005/07/15 16:20:00 wig
-- Update all testcases; still problems though
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.55 2005/07/13 15:38:34 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.36 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/enty
--
--
-- Start of Generated Entity inst_8_e
--
entity inst_8_e is
-- Generics:
-- No Generated Generics for Entity inst_8_e
-- Generated Port Declaration:
-- No Generated Port for Entity inst_8_e
end inst_8_e;
--
-- End of Generated Entity inst_8_e
--
--
--!End of Entity/ies
-- --------------------------------------------------------------
|
entity case1 is
end;
architecture behav of case1 is
begin
process
begin
for i in 1 to 10 loop
case i is
when 1 =>
report "one";
wait for 1 ns;
when 2 =>
report "two";
wait for 2 ns;
when 3 =>
report "three";
wait for 3 ns;
when 4 to 9 =>
report "a big digit";
wait for 5 ns;
when others =>
report "a number"; -- including 0.
wait for 10 ns;
end case;
end loop;
report "SUCCESS";
wait;
end process;
end behav;
|
entity case1 is
end;
architecture behav of case1 is
begin
process
begin
for i in 1 to 10 loop
case i is
when 1 =>
report "one";
wait for 1 ns;
when 2 =>
report "two";
wait for 2 ns;
when 3 =>
report "three";
wait for 3 ns;
when 4 to 9 =>
report "a big digit";
wait for 5 ns;
when others =>
report "a number"; -- including 0.
wait for 10 ns;
end case;
end loop;
report "SUCCESS";
wait;
end process;
end behav;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity MUX_PCSOURCE is
Port ( PCdisp30 : in STD_LOGIC_VECTOR (31 downto 0);
PCSEUdisp22 : in STD_LOGIC_VECTOR (31 downto 0);
ALURESULT : in STD_LOGIC_VECTOR (31 downto 0);
PC : in STD_LOGIC_VECTOR(31 downto 0);
PCSOURCE : in STD_LOGIC_VECTOR (1 downto 0);
nPC : out STD_LOGIC_VECTOR (31 downto 0));
end MUX_PCSOURCE;
architecture Behavioral of MUX_PCSOURCE is
begin
process(PC,PCdisp30,PCSEUdisp22,ALURESULT,PCSOURCE)
begin
case PCSOURCE is
when "00"=>nPC<=PCdisp30;
when "01"=>nPC<=PCSEUdisp22;
when "10"=>nPC<=PC;
when others=>nPC<=ALURESULT;--11
end case;
end process;
end Behavioral;
|
-- -------------------------------------------------------------
--
-- Entity Declaration for ioblock0_e
--
-- Generated
-- by: wig
-- on: Mon Jul 18 15:46:40 2005
-- cmd: h:/work/eclipse/mix/mix_0.pl -strip -nodelta ../../padio.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: ioblock0_e-e.vhd,v 1.2 2005/07/19 07:13:15 wig Exp $
-- $Date: 2005/07/19 07:13:15 $
-- $Log: ioblock0_e-e.vhd,v $
-- Revision 1.2 2005/07/19 07:13:15 wig
-- Update testcases. Added highlow/nolowbus
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.57 2005/07/18 08:58:22 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.36 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/enty
--
--
-- Start of Generated Entity ioblock0_e
--
entity ioblock0_e is
-- Generics:
-- No Generated Generics for Entity ioblock0_e
-- Generated Port Declaration:
port(
-- Generated Port for Entity ioblock0_e
p_mix_data_i1_go : out std_ulogic_vector(7 downto 0);
p_mix_data_o1_gi : in std_ulogic_vector(7 downto 0);
p_mix_iosel_0_gi : in std_ulogic;
p_mix_iosel_1_gi : in std_ulogic;
p_mix_iosel_2_gi : in std_ulogic;
p_mix_iosel_3_gi : in std_ulogic;
p_mix_iosel_4_gi : in std_ulogic;
p_mix_iosel_5_gi : in std_ulogic;
p_mix_nand_dir_gi : in std_ulogic;
p_mix_nand_out_2_go : out std_ulogic;
p_mix_pad_di_1_gi : in std_ulogic;
p_mix_pad_do_2_go : out std_ulogic;
p_mix_pad_en_2_go : out std_ulogic
-- End of Generated Port for Entity ioblock0_e
);
end ioblock0_e;
--
-- End of Generated Entity ioblock0_e
--
--
--!End of Entity/ies
-- --------------------------------------------------------------
|
-- =================================================================================
-- // Name: Bryan Mason, James Batcheler, & Brad McMahon
-- // File: tetris_control.vhd
-- // Date: 12/9/2004
-- // Description: Tetris program controller
-- // Class: CSE 378
-- =================================================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity tetris_control is
port
(
clk: in STD_LOGIC;
clr: in STD_LOGIC;
i_buttons: in STD_LOGIC_VECTOR(7 downto 0); -- controller buttons vector
i_block_code: in STD_LOGIC_VECTOR(2 downto 0); -- 0..7, chooses next block
o_load_xpos: out STD_LOGIC; -- '1' when xreg should be loaded with xpos
o_xpos_val: out STD_LOGIC_VECTOR(3 downto 0); -- 0..9 < 16
o_load_ypos: out STD_LOGIC; -- '1' when yreg should be loaded with ypos
o_ypos_val: out STD_LOGIC_VECTOR(4 downto 0); -- 0..19 < 32
o_load_block: out STD_LOGIC; -- '1' when blockreg should be loaded with shape
o_block_val: out STD_LOGIC_VECTOR(15 downto 0); -- 4x4 block, '1' = SOLID
o_paused: out STD_LOGIC; -- '1' when the game is paused
-- // for fetching rows into and out of tetris_control / ramtable
i_row_val: in STD_LOGIC_VECTOR(15 downto 0);
o_row_fetch: out STD_LOGIC; -- '1' when i_row_val should be loaded for i_row_no
o_row_load: out STD_LOGIC; -- '1' when o_row_val should br put for o_row_no
o_row_no: out STD_LOGIC_VECTOR(4 downto 0); -- 0..19 < 32
o_row_val: out STD_LOGIC_VECTOR(15 downto 0);
o_Lines_Destroyed : out std_logic_vector(2 downto 0);
i_Clear_Lines : in std_logic
);
end tetris_control;
architecture tetris_control_arch of tetris_control is
type state_type is
(
startup,
purge,
wait_for_start,
read_nes_pad,
make_block,
move_left,
move_right,
move_down,
check_down,
check_down2,
rot_right,
rot_left,
fetch_in_row0,
fetch_in_row1,
fetch_in_row2,
write_out_row0,
write_out_row,
kill_row,
kill_row2,
kill_row3,
kill_row4
);
-- // the number of clock cycles that pass before the block will drop
-- // 50,000,000 = 1 Hz = 1 second
constant C_READ_GAME_INPUT_MAX_TICKS: positive := 50000000;
--constant C_READ_GAME_INPUT_MAX_TICKS: positive := 20;
-- // the number of ticks to wait between controller commands (buffering)
constant C_MASTER_READ_WAIT_TICKS: positive := 25000000 / 5;
--constant C_MASTER_READ_WAIT_TICKS: positive := 10;
-- // the grid offset for to the first position (x,y) on screen
constant C_GRID_OFFSET: positive := 3;
constant C_READ_BUTTON_A_WAIT_TICKS: positive := C_MASTER_READ_WAIT_TICKS*2;
constant C_READ_BUTTON_B_WAIT_TICKS: positive := C_MASTER_READ_WAIT_TICKS*2;
constant C_READ_BUTTON_SELECT_WAIT_TICKS: positive := C_MASTER_READ_WAIT_TICKS;
constant C_READ_BUTTON_START_WAIT_TICKS: positive := C_MASTER_READ_WAIT_TICKS*4;
constant C_READ_BUTTON_UP_WAIT_TICKS: positive := C_MASTER_READ_WAIT_TICKS/2;
constant C_READ_BUTTON_DOWN_WAIT_TICKS: positive := C_MASTER_READ_WAIT_TICKS/2;
constant C_READ_BUTTON_LEFT_WAIT_TICKS: positive := C_MASTER_READ_WAIT_TICKS/2;
constant C_READ_BUTTON_RIGHT_WAIT_TICKS: positive := C_MASTER_READ_WAIT_TICKS/2;
-- // indexes to breakout the individual buttons from the button vector
constant BUTTON_A: integer := 7;
constant BUTTON_B: integer := 6;
constant BUTTON_SELECT: integer := 5;
constant BUTTON_START: integer := 4;
constant BUTTON_UP: integer := 3;
constant BUTTON_DOWN: integer := 2;
constant BUTTON_LEFT: integer := 1;
constant BUTTON_RIGHT: integer := 0;
-- // the current count of clock cycles past since the last reset
signal t_read_game_input_ticks: std_logic_vector(31 downto 0) := X"00000000";
-- // counts up the number of rows that have been "purged" / reset
signal t_purge_counter : integer := 0;
signal t_Lines_Destroyed : std_logic_vector(2 downto 0) := "000";
signal t_kill_counter : integer := 0;
-- // the number of ticks that the controller input is disabled
signal t_button_a_wait_ticks_remain: std_logic_vector(31 downto 0) := X"00000000";
signal t_button_b_wait_ticks_remain: std_logic_vector(31 downto 0) := X"00000000";
signal t_button_select_wait_ticks_remain: std_logic_vector(31 downto 0) := X"00000000";
signal t_button_start_wait_ticks_remain: std_logic_vector(31 downto 0) := X"00000000";
signal t_button_up_wait_ticks_remain: std_logic_vector(31 downto 0) := X"00000000";
signal t_button_down_wait_ticks_remain: std_logic_vector(31 downto 0) := X"00000000";
signal t_button_left_wait_ticks_remain: std_logic_vector(31 downto 0) := X"00000000";
signal t_button_right_wait_ticks_remain: std_logic_vector(31 downto 0) := X"00000000";
signal t_lines_killed : std_logic_vector(2 downto 0) := "000";
signal t_condense_inner_counter : integer := 23;
signal t_condense_outer_counter : integer := 0;
signal t_Shift_row : std_logic := '0';
signal t_condenseB : std_logic_vector(15 downto 0) := "0000000000000000";
signal t_condenseA : std_logic_vector(15 downto 0) := "0000000000000000";
-- // signals holding for the states set for the program
signal current_state, next_state: state_type;
-- // the current block shape
signal t_block_val : std_logic_vector(15 downto 0) := X"0000";
-- // the x-position of the block on the grid
signal t_xpos : std_logic_vector(3 downto 0) := "0011";
-- // the y-position of the block on the grid
signal t_ypos : std_logic_vector(4 downto 0) := "00011";
-- // '1' when the read_nes_pad state should write out rows / make block
signal t_down_movement_done : std_logic := '0';
-- // '1' when the fetch_row routines should stop looping
signal t_row_fetches_done : std_logic := '1';
-- // temp work variable for storing the last row processed in reading / writing
signal t_last_row_processed : std_logic_vector(4 downto 0) := "00011";
-- // cached row data around and below the current piece
signal t_row0_data : std_logic_vector(15 downto 0) := X"0000";
signal t_row1_data : std_logic_vector(15 downto 0) := X"0000";
signal t_row2_data : std_logic_vector(15 downto 0) := X"0000";
signal t_row3_data : std_logic_vector(15 downto 0) := X"0000";
signal t_row4_data : std_logic_vector(15 downto 0) := X"0000";
begin
-- // =================================================================
-- // process for clear, setting up first state, next state progression
-- // also increments counter for clock cycles processed
-- // =================================================================
synch: process(clk, clr)
begin
if clr = '1' then -- on clear
current_state <= startup;
elsif (clk'event and clk = '1') then -- on the rising edge of the clock
-- // set the next state
current_state <= next_state;
end if;
end process synch;
-- // =================================================================
-- // process for setting up the next state based on the current state
-- // =================================================================
C1: process(current_state,
t_read_game_input_ticks,
t_button_a_wait_ticks_remain,
t_button_b_wait_ticks_remain,
t_button_select_wait_ticks_remain,
t_button_start_wait_ticks_remain,
t_button_up_wait_ticks_remain,
t_button_down_wait_ticks_remain,
t_button_left_wait_ticks_remain,
t_button_right_wait_ticks_remain,
i_buttons,
t_last_row_processed,
t_purge_counter, t_block_val, t_row_fetches_done, t_down_movement_done, t_ypos, t_kill_counter,t_condense_outer_counter, t_Shift_row,t_condense_inner_counter)
begin
case current_state is
when startup =>
next_state <= purge;
when purge =>
if t_purge_counter < 32 then
next_state <= purge;
else
next_state <= wait_for_start;
end if;
when wait_for_start =>
-- // wait for START button depressed, else keep waiting
if i_buttons(BUTTON_START) = '1' then
if t_button_start_wait_ticks_remain = X"00000000" then
-- // TRUE when we haven't recently done something on button press
if t_block_val /= X"0000" then
next_state <= read_nes_pad;
else
next_state <= make_block;
end if;
else
-- // OR FALSE when we need to just keep waiting (next_state <= this)
next_state <= wait_for_start;
end if;
else
next_state <= wait_for_start;
end if;
when read_nes_pad =>
-- // we get out of the read loop state when we have spent a certain number
-- // of clock ticks here, the move and rot states return back to here
if t_read_game_input_ticks < C_READ_GAME_INPUT_MAX_TICKS then
-- // ==============================================
-- // ALL IN GAME BUTTON next states are set here
-- // ==============================================
if i_buttons(BUTTON_LEFT) = '1' then
if t_button_left_wait_ticks_remain = X"00000000" then
-- // TRUE when we haven't recently done something on button press
next_state <= move_left;
else
-- // OR FALSE when we need to just keep waiting (next_state <= this)
next_state <= read_nes_pad;
end if;
elsif i_buttons(BUTTON_RIGHT) = '1' then
if t_button_right_wait_ticks_remain = X"00000000" then
-- // TRUE when we haven't recently done something on button press
next_state <= move_right;
else
-- // OR FALSE when we need to just keep waiting (next_state <= this)
next_state <= read_nes_pad;
end if;
elsif i_buttons(BUTTON_B) = '1' then
if t_button_b_wait_ticks_remain = X"00000000" then
-- // TRUE when we haven't recently done something on button press
next_state <= rot_left;
else
-- // OR FALSE when we need to just keep waiting (next_state <= this)
next_state <= read_nes_pad;
end if;
elsif i_buttons(BUTTON_A) = '1' then
if t_button_a_wait_ticks_remain = X"00000000" then
-- // TRUE when we haven't recently done something on button press
next_state <= rot_right;
else
-- // OR FALSE when we need to just keep waiting (next_state <= this)
next_state <= read_nes_pad;
end if;
elsif i_buttons(BUTTON_START) = '1' then
if t_button_start_wait_ticks_remain = X"00000000" then
-- // TRUE when we haven't recently done something on button press
next_state <= wait_for_start;
else
-- // OR FALSE when we need to just keep waiting (next_state <= this)
next_state <= read_nes_pad;
end if;
elsif i_buttons(BUTTON_DOWN) = '1' then
if t_button_down_wait_ticks_remain = X"00000000" then
-- // TRUE when we haven't recently done something on button press
next_state <= move_down;
else
-- // OR FALSE when we need to just keep waiting (next_state <= this)
next_state <= read_nes_pad;
end if;
else
next_state <= read_nes_pad;
end if;
else
next_state <= move_down;
end if;
when make_block =>
-- // pull random number from random number generator
-- // use random number to get a block and write it into
-- // current block description RAM
-- // dump the starting block position out to the xreg, yreg
next_state <= read_nes_pad;
when fetch_in_row0 =>
next_state <= fetch_in_row1;
when fetch_in_row1 =>
if t_row_fetches_done /= '1' then
next_state <= fetch_in_row2;
else
next_state <= check_down;
end if;
when fetch_in_row2 =>
next_state <= fetch_in_row1;
when check_down =>
next_state <= check_down2;
when check_down2 =>
if t_down_movement_done = '1' then
next_state <= write_out_row0;
else
next_state <= read_nes_pad;
end if;
when move_down =>
next_state <= fetch_in_row0;
when move_left =>
next_state <= read_nes_pad;
when move_right =>
next_state <= read_nes_pad;
when rot_left =>
next_state <= read_nes_pad;
when rot_right =>
next_state <= read_nes_pad;
when write_out_row0 =>
next_state <= write_out_row;
when write_out_row =>
if t_last_row_processed = t_ypos + 4 then
next_state <= kill_row;
else
next_state <= write_out_row;
end if;
when kill_row =>
if t_kill_counter <= 22 then
next_state <= kill_row2;
else
next_state <= kill_row4;
end if;
when kill_row2 =>
next_state <= kill_row3;
when kill_row3 =>
next_state <= kill_row;
when kill_row4 =>
next_state <= make_block; --condense0;
end case;
end process C1;
C2: process(current_state, clr, clk)
-- // is set to '1' when the process should clear current clock
-- // cycle count to zero rather than increment it
variable p_read_game_input_clear: std_logic := '0';
-- // temp variable used by make block
variable p_block_val: std_logic_vector(15 downto 0) := X"0000";
-- // what the block would look like rotated to the left
variable p_block_left : std_logic_vector(15 downto 0) := X"0000";
-- // what the block would look like rotated to the right
variable p_block_right : std_logic_vector(15 downto 0) := X"0000";
-- // temporary variables
variable p_tmp_work : std_logic_vector(3 downto 0) := "0000";
variable p_tmp_var : std_logic := '0';
-- // temporary x,y position
variable p_ypos : integer range 26 downto 0 := 0;
variable p_xpos : integer range 16 downto 0 := 0;
-- // the data behind / near the block at its current position
variable p_data_behind_block : std_logic_vector(15 downto 0) := X"0000";
variable p_data_below_block : std_logic_vector(3 downto 0) := "0000";
variable p_data_right_of_block : std_logic_vector(3 downto 0) := "0000";
variable p_data_left_of_block : std_logic_vector(3 downto 0) := "0000";
-- // '1' when named action is allowed for the current state of block
variable p_move_down_ok : std_logic := '0';
variable p_move_left_ok : std_logic := '0';
variable p_move_right_ok : std_logic := '0';
variable p_rotate_right_ok : std_logic := '0';
variable p_rotate_left_ok : std_logic := '0';
-- // row data if the current t_block were committed to the row data
variable p_row0_final_data : std_logic_vector(15 downto 0) := X"0000";
variable p_row1_final_data : std_logic_vector(15 downto 0) := X"0000";
variable p_row2_final_data : std_logic_vector(15 downto 0) := X"0000";
variable p_row3_final_data : std_logic_vector(15 downto 0) := X"0000";
-- // first filled columns and rows
variable p_first_filled_column_from_left : integer := 0;
variable p_first_filled_column_from_right : integer := 0;
variable p_first_filled_row_from_bottom : integer := 0;
begin
if (clr = '1') then
t_Shift_row <= '0';
t_condenseA <= "0000000000000000";
t_condenseB <= "0000000000000000";
t_condense_inner_counter <= 23;
t_condense_outer_counter <= 0;
t_read_game_input_ticks <= X"00000000";
t_purge_counter <= 0;
t_button_a_wait_ticks_remain <= X"00000000";
t_button_b_wait_ticks_remain <= X"00000000";
t_button_select_wait_ticks_remain <= X"00000000";
t_button_start_wait_ticks_remain <= X"00000000";
t_button_up_wait_ticks_remain <= X"00000000";
t_button_down_wait_ticks_remain <= X"00000000";
t_button_left_wait_ticks_remain <= X"00000000";
t_button_right_wait_ticks_remain <= X"00000000";
t_Lines_Destroyed <= "000";
o_Lines_Destroyed <= "000";
t_block_val <= X"0000";
t_xpos <= "0011";
t_ypos <= "00011";
t_down_movement_done <= '0';
t_row_fetches_done <= '1';
t_last_row_processed <= "00011";
t_row0_data <= X"0000";
t_row1_data <= X"0000";
t_row2_data <= X"0000";
t_row3_data <= X"0000";
t_row4_data <= X"0000";
t_kill_counter <= 3;
p_read_game_input_clear := '0';
p_block_val := X"0000";
p_block_left := X"0000";
p_block_right := X"0000";
p_tmp_work := "0000";
p_tmp_var := '0';
p_ypos := 0;
p_xpos := 0;
p_data_behind_block := X"0000";
p_data_below_block := "0000";
p_data_right_of_block := "0000";
p_data_left_of_block := "0000";
p_move_down_ok := '0';
p_move_left_ok := '0';
p_move_right_ok := '0';
p_rotate_right_ok := '0';
p_rotate_left_ok := '0';
p_row0_final_data := X"0000";
p_row1_final_data := X"0000";
p_row2_final_data := X"0000";
p_row3_final_data := X"0000";
p_first_filled_column_from_left := 0;
p_first_filled_column_from_right := 0;
p_first_filled_row_from_bottom := 0;
t_Shift_row <= '0';
elsif (clk'event and clk = '1') then
if i_Clear_Lines = '1' then
t_Lines_Destroyed <= "000";
o_Lines_Destroyed <= t_Lines_Destroyed;
end if;
-- // by default, don't load new xpos, ypos, or blocks
o_load_xpos <= '0';
o_xpos_val <= "0000";
o_load_ypos <= '0';
o_ypos_val <= "00000";
o_load_block <= '0';
o_block_val <= X"0000";
o_row_fetch <= '0';
o_row_load <= '0';
o_row_no <= "00000";
o_row_val <= X"0000";
p_block_val := t_block_val;
p_xpos := CONV_INTEGER(t_xpos);
p_ypos := CONV_INTEGER(t_ypos);
p_read_game_input_clear := '0';
p_tmp_var := '0';
-- // by default we are not paused
o_paused <= '0';
-- // predetermine the rotated forms of the current piece
p_block_left := p_block_val(3) & p_block_val(7) & p_block_val(11) & p_block_val(15) &
p_block_val(2) & p_block_val(6) & p_block_val(10) & p_block_val(14) &
p_block_val(1) & p_block_val(5) & p_block_val(9) & p_block_val(13) &
p_block_val(0) & p_block_val(4) & p_block_val(8) & p_block_val(12);
p_block_right := p_block_val(12) & p_block_val(8) & p_block_val(4) & p_block_val(0) &
p_block_val(13) & p_block_val(9) & p_block_val(5) & p_block_val(1) &
p_block_val(14) & p_block_val(10) & p_block_val(6) & p_block_val(2) &
p_block_val(15) & p_block_val(11) & p_block_val(7) & p_block_val(3);
-- // fetch data behind / near the block using the position of the current block
for i in 0 to 3 loop
p_data_behind_block(15 - i) := t_row0_data(15 - p_xpos - i);
p_data_behind_block(11 - i) := t_row1_data(15 - p_xpos - i);
p_data_behind_block(7 - i) := t_row2_data(15 - p_xpos - i);
p_data_behind_block(3 - i) := t_row3_data(15 - p_xpos - i);
end loop;
-- // find the first row (from bottom to top) on the piece that contains a bit
if ((t_block_val(12) or t_block_val(13) or t_block_val(14) or t_block_val(15)) = '1') then
p_first_filled_row_from_bottom := 3;
elsif ((t_block_val(8) or t_block_val(9) or t_block_val(10) or t_block_val(11)) = '1') then
p_first_filled_row_from_bottom := 2;
elsif ((t_block_val(4) or t_block_val(5) or t_block_val(6) or t_block_val(7)) = '1') then
p_first_filled_row_from_bottom := 1;
else
p_first_filled_row_from_bottom := 0;
end if;
-- // find the first column (from right to left) on the piece that contains a bit
if ((t_block_val(3) or t_block_val(7) or t_block_val(11) or t_block_val(15)) = '1') then
p_first_filled_column_from_right := 3;
elsif ((t_block_val(2) or t_block_val(6) or t_block_val(10) or t_block_val(14)) = '1') then
p_first_filled_column_from_right := 2;
elsif ((t_block_val(1) or t_block_val(5) or t_block_val(9) or t_block_val(13)) = '1') then
p_first_filled_column_from_right := 1;
else
p_first_filled_column_from_right := 0;
end if;
-- // find the first column (from left to right) on the piece that contains a bit
if ((t_block_val(0) or t_block_val(4) or t_block_val(8) or t_block_val(12)) = '1') then
p_first_filled_column_from_left := 0;
elsif ((t_block_val(1) or t_block_val(5) or t_block_val(9) or t_block_val(13)) = '1') then
p_first_filled_column_from_left := 1;
elsif ((t_block_val(2) or t_block_val(6) or t_block_val(10) or t_block_val(14)) = '1') then
p_first_filled_column_from_left := 2;
else
p_first_filled_column_from_left := 3;
end if;
-- // fetch data below
for i in 0 to 3 loop
p_data_below_block(3 - i) := t_row4_data(15 - p_xpos - i);
end loop;
-- // fetch data to the right
--Changed from 0...3 to 1...4
p_data_right_of_block(3 downto 0) := t_row0_data(15 - p_xpos - 4) &
t_row1_data(15 - p_xpos - 4) &
t_row2_data(15 - p_xpos - 4) &
t_row3_data(15 - p_xpos - 4);
-- // fetch data to the left
p_data_left_of_block(3 downto 0) := t_row0_data(15 - p_xpos + 1) &
t_row1_data(15 - p_xpos + 1) &
t_row2_data(15 - p_xpos + 1) &
t_row3_data(15 - p_xpos + 1);
-- // ===========================================================
-- // perform checks to see if movements are allowed
-- // ===========================================================
-- // check downward movement
p_tmp_var := '1';
for i in 0 to 3 loop
p_tmp_var := p_tmp_var and (p_data_below_block(i) nand t_block_val(i));
end loop;
for i in 0 to 11 loop
p_tmp_var := p_tmp_var and (p_data_behind_block(i) nand t_block_val(i+4));
end loop;
if p_tmp_var = '1' then
p_move_down_ok := '1';
else
p_move_down_ok := '0';
end if;
-- // check left movement
p_tmp_var := '1';
for i in 0 to 15 loop
if i /= 15 and i /= 11 and i /= 7 and i /= 3 then -- exclude farthest right column
p_tmp_var := (p_tmp_var and (p_data_behind_block(i + 1) nand t_block_val(i)));
end if;
end loop; -- check farthest left data column
for i in 0 to 3 loop
p_tmp_var := p_tmp_var and (t_block_val(4*i+3) nand p_data_left_of_block(i));
end loop;
if p_tmp_var = '1' then
p_move_left_ok := '1';
else
p_move_left_ok := '0';
end if;
-- // check right movement
p_tmp_var := '1';
for i in 0 to 15 loop
if i /= 0 and i /= 4 and i /= 8 and i /= 12 then -- exclude farthest left column
p_tmp_var := (p_tmp_var and (p_data_behind_block(i - 1) nand t_block_val(i)));
end if;
end loop; -- check farthest right column
for i in 0 to 3 loop
p_tmp_var := p_tmp_var and (t_block_val(4*i) nand p_data_right_of_block(i));
end loop;
if p_tmp_var = '1' then
p_move_right_ok := '1';
else
p_move_right_ok := '0';
end if;
-- // check left rotation
p_tmp_var := '1';
for i in 0 to 15 loop
p_tmp_var := p_tmp_var and (p_data_behind_block(i) nand p_block_left(i));
end loop;
if p_tmp_var = '1' then
p_rotate_left_ok := '1';
else
p_rotate_left_ok := '0';
end if;
-- // check right rotation
p_tmp_var := '1';
for i in 0 to 15 loop
p_tmp_var := p_tmp_var and (p_data_behind_block(i) nand p_block_right(i));
end loop;
if p_tmp_var = '1' then
p_rotate_right_ok := '1';
else
p_rotate_right_ok := '0';
end if;
-- // =============================================================
-- // build the final piece data that will be used when writing out
-- // =============================================================
p_row0_final_data(15 downto 0) := t_row0_data(15 downto 0);
p_row1_final_data(15 downto 0) := t_row1_data(15 downto 0);
p_row2_final_data(15 downto 0) := t_row2_data(15 downto 0);
p_row3_final_data(15 downto 0) := t_row3_data(15 downto 0);
for i in 0 to 3 loop
p_row0_final_data(15 - p_xpos - i) := (t_block_val(15 - i) or t_row0_data(15 - p_xpos - i));
p_row1_final_data(15 - p_xpos - i) := (t_block_val(11 - i) or t_row1_data(15 - p_xpos - i));
p_row2_final_data(15 - p_xpos - i) := (t_block_val(7 - i) or t_row2_data(15 - p_xpos - i));
p_row3_final_data(15 - p_xpos - i) := (t_block_val(3 - i) or t_row3_data(15 - p_xpos - i));
end loop;
case current_state is
when startup =>
t_purge_counter <= 0;
when purge =>
if t_purge_counter < 3 or t_purge_counter > 22 then
o_row_val <= "1111111111111111";
else
o_row_val <= "1110000000000111";
end if;
o_row_load <= '1';
o_row_no <= CONV_STD_LOGIC_VECTOR(t_purge_counter, 5);
t_purge_counter <= t_purge_counter + 1;
when wait_for_start =>
-- // wait for START button depressed, else keep waiting
o_paused <= '1';
if (i_buttons(BUTTON_START) = '1') then
t_button_start_wait_ticks_remain <= CONV_STD_LOGIC_VECTOR(C_READ_BUTTON_START_WAIT_TICKS, 32);
end if;
when read_nes_pad =>
-- // check for controller keystrokes
when fetch_in_row0 =>
t_last_row_processed <= conv_std_logic_vector(p_ypos,5);
when fetch_in_row1 =>
o_row_fetch <= '1';
o_row_no <= t_last_row_processed;
when fetch_in_row2 =>
if (t_last_row_processed /= p_ypos + 5) then
-- // shift all rows up and shift in new row to bottom
t_row0_data <= t_row1_data;
t_row1_data <= t_row2_data;
t_row2_data <= t_row3_data;
t_row3_data <= t_row4_data;
t_row4_data <= i_row_val;
--for i in 0 to 15 loop --backwards read
-- t_row4_data(i) <= i_row_val(15 - i);
--end loop;
t_last_row_processed <= t_last_row_processed + 1;
else
t_row_fetches_done <= '1';
end if;
when move_left =>
-- // move the xreg position left
if p_move_left_ok = '1' then
o_load_xpos <= '1';
p_xpos := p_xpos - 1;
o_xpos_val <= CONV_STD_LOGIC_VECTOR(p_xpos, 4);
t_xpos <= CONV_STD_LOGIC_VECTOR(p_xpos, 4);
t_button_left_wait_ticks_remain <= CONV_STD_LOGIC_VECTOR(C_READ_BUTTON_LEFT_WAIT_TICKS, 32);
end if;
when move_right =>
-- // move the xreg position right
if p_move_right_ok = '1' then
o_load_xpos <= '1';
p_xpos := p_xpos + 1;
o_xpos_val <= CONV_STD_LOGIC_VECTOR(p_xpos, 4);
t_xpos <= CONV_STD_LOGIC_VECTOR(p_xpos, 4);
t_button_right_wait_ticks_remain <= CONV_STD_LOGIC_VECTOR(C_READ_BUTTON_RIGHT_WAIT_TICKS, 32);
end if;
when move_down =>
when check_down =>
t_row_fetches_done <= '0';
if p_move_down_ok = '0' then
t_down_movement_done <= '1';
end if;
if p_move_down_ok = '1' then
t_down_movement_done <= '0';
-- // decrement the yreg position
o_load_ypos <= '1';
p_ypos := p_ypos + 1;
o_ypos_val <= CONV_STD_LOGIC_VECTOR(p_ypos, 5);
t_ypos <= CONV_STD_LOGIC_VECTOR(p_ypos, 5);
-- // the block has moved down, reset the allowed input time
p_read_game_input_clear := '1';
t_button_down_wait_ticks_remain <= CONV_STD_LOGIC_VECTOR(C_READ_BUTTON_DOWN_WAIT_TICKS, 32);
else
--t_last_row_processed <= CONV_STD_LOGIC_VECTOR(p_ypos, 5) - 1;
end if;
when check_down2 =>
when rot_left =>
-- // rotate the piece left
if p_rotate_left_ok = '1' then
o_load_block <= '1';
t_block_val <= p_block_left;
o_block_val <= p_block_left;
p_block_val := p_block_left;
t_button_b_wait_ticks_remain <= CONV_STD_LOGIC_VECTOR(C_READ_BUTTON_B_WAIT_TICKS, 32);
end if;
when rot_right =>
-- // rotate the piece right
if p_rotate_right_ok = '1' then
o_load_block <= '1';
t_block_val <= p_block_right;
o_block_val <= p_block_right;
p_block_val := p_block_right;
t_button_a_wait_ticks_remain <= CONV_STD_LOGIC_VECTOR(C_READ_BUTTON_A_WAIT_TICKS, 32);
end if;
when make_block =>
-- // pull random number from random number generator
-- // use random number to get a block and write it into
-- // current block description RAM
-- // dump the starting block position out to the xreg, yreg
--Reset killed lines counter.
t_last_row_processed <= CONV_STD_LOGIC_VECTOR(C_GRID_OFFSET, 5);
o_load_xpos <= '1';
o_load_ypos <= '1';
o_xpos_val <= CONV_STD_LOGIC_VECTOR(C_GRID_OFFSET + 4, 4); -- 7, middle (x) of screen (+3 offset border)
o_ypos_val <= CONV_STD_LOGIC_VECTOR(C_GRID_OFFSET, 5); -- 3, top (y) of screen (+3 offset border)
-- // also store current x,y position stored in signals
t_xpos <= CONV_STD_LOGIC_VECTOR(C_GRID_OFFSET + 4, 4);
t_ypos <= CONV_STD_LOGIC_VECTOR(C_GRID_OFFSET, 5);
o_load_block <= '1';
if i_block_code = "000" then
p_block_val := "1010" & -- custom "cup" block
"1010" & -- a REAL PAIN
"1110" &
"0000";
elsif i_block_code = "001" then
p_block_val := "0000" & -- square block
"0110" &
"0110" &
"0000";
elsif i_block_code = "010" then
p_block_val := "0010" & -- tee block
"0110" &
"0010" &
"0000";
elsif i_block_code = "011" then
p_block_val := "0100" & -- bolt right block
"0110" &
"0010" &
"0000";
elsif i_block_code = "100" then
p_block_val := "0010" & -- bolt left block
"0110" &
"0100" &
"0000";
elsif i_block_code = "101" then
p_block_val := "0010" & -- arch left block
"0010" &
"0110" &
"0000";
elsif i_block_code = "110" then
p_block_val := "0100" & -- arch right block
"0100" &
"0110" &
"0000";
elsif i_block_code = "111" then
p_block_val := "0100" & -- the legendary pipe block
"0100" &
"0100" &
"0100";
end if;
t_block_val <= p_block_val;
o_block_val <= p_block_val;
when kill_row =>
--Read in row
o_row_no <= conv_std_logic_vector(t_kill_counter, 5);
when kill_row2 =>
--Make comparison.
if i_row_val = "1111111111111111" and t_kill_counter >= 3 and t_kill_counter <= 22 then
o_row_val <= "1110000000000111";
o_row_no <= conv_std_logic_vector(t_kill_counter, 5);
o_row_load <= '1';
t_lines_killed <= t_lines_killed + 1;
end if;
when kill_row3 =>
t_kill_counter <= t_kill_counter + 1;
when kill_row4 =>
t_kill_counter <= 0;
t_Lines_Destroyed <= t_lines_killed;
o_Lines_Destroyed <= t_Lines_Destroyed;
t_lines_killed <= "000";
when write_out_row0 =>
t_last_row_processed <= conv_std_logic_vector(p_ypos,5);
when write_out_row =>
t_down_movement_done <= '0';
if t_last_row_processed = p_ypos then
o_row_val <= p_row0_final_data;
o_row_load <= '1';
o_row_no <= CONV_STD_LOGIC_VECTOR(p_ypos, 5);
elsif t_last_row_processed = p_ypos + 1 then
o_row_val <= p_row1_final_data;
o_row_load <= '1';
o_row_no <= CONV_STD_LOGIC_VECTOR(p_ypos + 1, 5);
elsif t_last_row_processed = p_ypos + 2 then
o_row_val <= p_row2_final_data;
o_row_load <= '1';
o_row_no <= CONV_STD_LOGIC_VECTOR(p_ypos + 2, 5);
elsif t_last_row_processed = p_ypos + 3 then
o_row_val <= p_row3_final_data ;
o_row_load <= '1';
o_row_no <= CONV_STD_LOGIC_VECTOR(p_ypos + 3, 5);
end if;
t_last_row_processed <= t_last_row_processed + 1;
end case;
-- // either increment or clear the number of ticks that have passed
if p_read_game_input_clear = '1' then
t_read_game_input_ticks <= X"00000000";
else
t_read_game_input_ticks <= t_read_game_input_ticks + 1;
end if;
-- // decrement the no of clock cycles the read counters must wait
if t_button_a_wait_ticks_remain > X"00000000" then
t_button_a_wait_ticks_remain <= t_button_a_wait_ticks_remain - 1;
end if;
if t_button_b_wait_ticks_remain > X"00000000" then
t_button_b_wait_ticks_remain <= t_button_b_wait_ticks_remain - 1;
end if;
if t_button_start_wait_ticks_remain > X"00000000" then
t_button_start_wait_ticks_remain <= t_button_start_wait_ticks_remain - 1;
end if;
if t_button_select_wait_ticks_remain > X"00000000" then
t_button_select_wait_ticks_remain <= t_button_select_wait_ticks_remain - 1;
end if;
if t_button_up_wait_ticks_remain > X"00000000" then
t_button_up_wait_ticks_remain <= t_button_up_wait_ticks_remain - 1;
end if;
if t_button_down_wait_ticks_remain > X"00000000" then
t_button_down_wait_ticks_remain <= t_button_down_wait_ticks_remain - 1;
end if;
if t_button_left_wait_ticks_remain > X"00000000" then
t_button_left_wait_ticks_remain <= t_button_left_wait_ticks_remain - 1;
end if;
if t_button_right_wait_ticks_remain > X"00000000" then
t_button_right_wait_ticks_remain <= t_button_right_wait_ticks_remain - 1;
end if;
end if; -- // matching endif for clk='1' and clk'event
end process C2;
end; |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: tap_altera
-- File: tap_altera_gen.vhd
-- Author: Edvin Catovic - Gaisler Research
-- Description: Altera TAP controllers wrappers
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library altera_mf;
use altera_mf.altera_mf_components.all;
use altera_mf.sld_virtual_jtag;
-- pragma translate_on
entity altera_tap is
port (
tapi_tdo1 : in std_ulogic;
tapi_tdo2 : in std_ulogic;
tapo_tck : out std_ulogic;
tapo_tdi : out std_ulogic;
tapo_inst : out std_logic_vector(7 downto 0);
tapo_rst : out std_ulogic;
tapo_capt : out std_ulogic;
tapo_shft : out std_ulogic;
tapo_upd : out std_ulogic;
tapo_xsel1 : out std_ulogic;
tapo_xsel2 : out std_ulogic
);
end;
architecture rtl of altera_tap is
signal ir0 : std_logic_vector(7 downto 0);
component sld_virtual_jtag
generic (
--lpm_hint : string := "UNUSED";
--lpm_type : string := "sld_virtual_jtag";
sld_auto_instance_index : string := "NO";
sld_instance_index : natural := 0;
sld_ir_width : natural := 1
--sld_sim_action : string := "UNUSED"
--sld_sim_n_scan : natural := 0;
--sld_sim_total_length : natural := 0
);
port(
ir_in : out std_logic_vector(sld_ir_width-1 downto 0);
ir_out : in std_logic_vector(sld_ir_width-1 downto 0);
jtag_state_cdr : out std_logic;
jtag_state_cir : out std_logic;
jtag_state_e1dr : out std_logic;
jtag_state_e1ir : out std_logic;
jtag_state_e2dr : out std_logic;
jtag_state_e2ir : out std_logic;
jtag_state_pdr : out std_logic;
jtag_state_pir : out std_logic;
jtag_state_rti : out std_logic;
jtag_state_sdr : out std_logic;
jtag_state_sdrs : out std_logic;
jtag_state_sir : out std_logic;
jtag_state_sirs : out std_logic;
jtag_state_tlr : out std_logic;
jtag_state_udr : out std_logic;
jtag_state_uir : out std_logic;
tck : out std_logic;
tdi : out std_logic;
tdo : in std_logic;
tms : out std_logic;
virtual_state_cdr : out std_logic;
virtual_state_cir : out std_logic;
virtual_state_e1dr : out std_logic;
virtual_state_e2dr : out std_logic;
virtual_state_pdr : out std_logic;
virtual_state_sdr : out std_logic;
virtual_state_udr : out std_logic;
virtual_state_uir : out std_logic
);
end component;
begin
tapo_rst <= '0';
tapo_xsel1 <= '0'; tapo_xsel2 <= '0';
u0 : sld_virtual_jtag
generic map (sld_ir_width => 8,
sld_auto_instance_index => "NO",
sld_instance_index => 0)
port map (ir_in => tapo_inst,
ir_out => ir0,
jtag_state_cdr => open,
jtag_state_cir => open,
jtag_state_e1dr => open,
jtag_state_e1ir => open,
jtag_state_e2dr => open,
jtag_state_e2ir => open,
jtag_state_pdr => open,
jtag_state_pir => open,
jtag_state_rti => open,
jtag_state_sdr => open,
jtag_state_sdrs => open,
jtag_state_sir => open,
jtag_state_sirs => open,
jtag_state_tlr => open,
jtag_state_udr => open,
jtag_state_uir => open,
tck => tapo_tck,
tdi => tapo_tdi,
tdo => tapi_tdo1,
tms => open,
virtual_state_cdr => tapo_capt,
virtual_state_cir => open,
virtual_state_e1dr => open,
virtual_state_e2dr => open,
virtual_state_pdr => open,
virtual_state_sdr => tapo_shft,
virtual_state_udr => tapo_upd,
virtual_state_uir => open);
end;
|
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`protect end_protected
|
library UNISIM;
use UNISIM.vcomponents.all;
library ieee;
use ieee.std_logic_1164.all;
entity clk_gen is
port(
sys_clk_p_i : in std_logic;
sys_clk_n_i : in std_logic;
sys_clk_o : out std_logic
);
end clk_gen;
architecture syn of clk_gen is
-- Internal clock signal
signal s_sys_clk : std_logic;
begin
-- IBUFGDS: Differential Global Clock Input Buffer
-- Virtex-6
-- Xilinx HDL Language Template, version 13.4
cpm_ibufgds_clk_gen : IBUFGDS
generic map (
DIFF_TERM => FALSE, -- Differential Termination
IBUF_LOW_PWR => TRUE, -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
IOSTANDARD => "DEFAULT"
)
port map (
O => s_sys_clk, -- Clock buffer output
I => sys_clk_p_i, -- Diff_p clock buffer input (connect directly to top-level port)
IB => sys_clk_n_i -- Diff_n clock buffer input (connect directly to top-level port)
);
-- BUFG: Global Clock Buffer
-- Virtex-6
-- Xilinx HDL Language Template, version 13.4
cmp_bufg_clk_gen : BUFG
port map (
O => sys_clk_o, -- 1-bit output: Clock buffer output
I => s_sys_clk -- 1-bit input: Clock buffer input
);
end syn;
|
library UNISIM;
use UNISIM.vcomponents.all;
library ieee;
use ieee.std_logic_1164.all;
entity clk_gen is
port(
sys_clk_p_i : in std_logic;
sys_clk_n_i : in std_logic;
sys_clk_o : out std_logic
);
end clk_gen;
architecture syn of clk_gen is
-- Internal clock signal
signal s_sys_clk : std_logic;
begin
-- IBUFGDS: Differential Global Clock Input Buffer
-- Virtex-6
-- Xilinx HDL Language Template, version 13.4
cpm_ibufgds_clk_gen : IBUFGDS
generic map (
DIFF_TERM => FALSE, -- Differential Termination
IBUF_LOW_PWR => TRUE, -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
IOSTANDARD => "DEFAULT"
)
port map (
O => s_sys_clk, -- Clock buffer output
I => sys_clk_p_i, -- Diff_p clock buffer input (connect directly to top-level port)
IB => sys_clk_n_i -- Diff_n clock buffer input (connect directly to top-level port)
);
-- BUFG: Global Clock Buffer
-- Virtex-6
-- Xilinx HDL Language Template, version 13.4
cmp_bufg_clk_gen : BUFG
port map (
O => sys_clk_o, -- 1-bit output: Clock buffer output
I => s_sys_clk -- 1-bit input: Clock buffer input
);
end syn;
|
library UNISIM;
use UNISIM.vcomponents.all;
library ieee;
use ieee.std_logic_1164.all;
entity clk_gen is
port(
sys_clk_p_i : in std_logic;
sys_clk_n_i : in std_logic;
sys_clk_o : out std_logic
);
end clk_gen;
architecture syn of clk_gen is
-- Internal clock signal
signal s_sys_clk : std_logic;
begin
-- IBUFGDS: Differential Global Clock Input Buffer
-- Virtex-6
-- Xilinx HDL Language Template, version 13.4
cpm_ibufgds_clk_gen : IBUFGDS
generic map (
DIFF_TERM => FALSE, -- Differential Termination
IBUF_LOW_PWR => TRUE, -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
IOSTANDARD => "DEFAULT"
)
port map (
O => s_sys_clk, -- Clock buffer output
I => sys_clk_p_i, -- Diff_p clock buffer input (connect directly to top-level port)
IB => sys_clk_n_i -- Diff_n clock buffer input (connect directly to top-level port)
);
-- BUFG: Global Clock Buffer
-- Virtex-6
-- Xilinx HDL Language Template, version 13.4
cmp_bufg_clk_gen : BUFG
port map (
O => sys_clk_o, -- 1-bit output: Clock buffer output
I => s_sys_clk -- 1-bit input: Clock buffer input
);
end syn;
|
library UNISIM;
use UNISIM.vcomponents.all;
library ieee;
use ieee.std_logic_1164.all;
entity clk_gen is
port(
sys_clk_p_i : in std_logic;
sys_clk_n_i : in std_logic;
sys_clk_o : out std_logic
);
end clk_gen;
architecture syn of clk_gen is
-- Internal clock signal
signal s_sys_clk : std_logic;
begin
-- IBUFGDS: Differential Global Clock Input Buffer
-- Virtex-6
-- Xilinx HDL Language Template, version 13.4
cpm_ibufgds_clk_gen : IBUFGDS
generic map (
DIFF_TERM => FALSE, -- Differential Termination
IBUF_LOW_PWR => TRUE, -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
IOSTANDARD => "DEFAULT"
)
port map (
O => s_sys_clk, -- Clock buffer output
I => sys_clk_p_i, -- Diff_p clock buffer input (connect directly to top-level port)
IB => sys_clk_n_i -- Diff_n clock buffer input (connect directly to top-level port)
);
-- BUFG: Global Clock Buffer
-- Virtex-6
-- Xilinx HDL Language Template, version 13.4
cmp_bufg_clk_gen : BUFG
port map (
O => sys_clk_o, -- 1-bit output: Clock buffer output
I => s_sys_clk -- 1-bit input: Clock buffer input
);
end syn;
|
library UNISIM;
use UNISIM.vcomponents.all;
library ieee;
use ieee.std_logic_1164.all;
entity clk_gen is
port(
sys_clk_p_i : in std_logic;
sys_clk_n_i : in std_logic;
sys_clk_o : out std_logic
);
end clk_gen;
architecture syn of clk_gen is
-- Internal clock signal
signal s_sys_clk : std_logic;
begin
-- IBUFGDS: Differential Global Clock Input Buffer
-- Virtex-6
-- Xilinx HDL Language Template, version 13.4
cpm_ibufgds_clk_gen : IBUFGDS
generic map (
DIFF_TERM => FALSE, -- Differential Termination
IBUF_LOW_PWR => TRUE, -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
IOSTANDARD => "DEFAULT"
)
port map (
O => s_sys_clk, -- Clock buffer output
I => sys_clk_p_i, -- Diff_p clock buffer input (connect directly to top-level port)
IB => sys_clk_n_i -- Diff_n clock buffer input (connect directly to top-level port)
);
-- BUFG: Global Clock Buffer
-- Virtex-6
-- Xilinx HDL Language Template, version 13.4
cmp_bufg_clk_gen : BUFG
port map (
O => sys_clk_o, -- 1-bit output: Clock buffer output
I => s_sys_clk -- 1-bit input: Clock buffer input
);
end syn;
|
library UNISIM;
use UNISIM.vcomponents.all;
library ieee;
use ieee.std_logic_1164.all;
entity clk_gen is
port(
sys_clk_p_i : in std_logic;
sys_clk_n_i : in std_logic;
sys_clk_o : out std_logic
);
end clk_gen;
architecture syn of clk_gen is
-- Internal clock signal
signal s_sys_clk : std_logic;
begin
-- IBUFGDS: Differential Global Clock Input Buffer
-- Virtex-6
-- Xilinx HDL Language Template, version 13.4
cpm_ibufgds_clk_gen : IBUFGDS
generic map (
DIFF_TERM => FALSE, -- Differential Termination
IBUF_LOW_PWR => TRUE, -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
IOSTANDARD => "DEFAULT"
)
port map (
O => s_sys_clk, -- Clock buffer output
I => sys_clk_p_i, -- Diff_p clock buffer input (connect directly to top-level port)
IB => sys_clk_n_i -- Diff_n clock buffer input (connect directly to top-level port)
);
-- BUFG: Global Clock Buffer
-- Virtex-6
-- Xilinx HDL Language Template, version 13.4
cmp_bufg_clk_gen : BUFG
port map (
O => sys_clk_o, -- 1-bit output: Clock buffer output
I => s_sys_clk -- 1-bit input: Clock buffer input
);
end syn;
|
library UNISIM;
use UNISIM.vcomponents.all;
library ieee;
use ieee.std_logic_1164.all;
entity clk_gen is
port(
sys_clk_p_i : in std_logic;
sys_clk_n_i : in std_logic;
sys_clk_o : out std_logic
);
end clk_gen;
architecture syn of clk_gen is
-- Internal clock signal
signal s_sys_clk : std_logic;
begin
-- IBUFGDS: Differential Global Clock Input Buffer
-- Virtex-6
-- Xilinx HDL Language Template, version 13.4
cpm_ibufgds_clk_gen : IBUFGDS
generic map (
DIFF_TERM => FALSE, -- Differential Termination
IBUF_LOW_PWR => TRUE, -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
IOSTANDARD => "DEFAULT"
)
port map (
O => s_sys_clk, -- Clock buffer output
I => sys_clk_p_i, -- Diff_p clock buffer input (connect directly to top-level port)
IB => sys_clk_n_i -- Diff_n clock buffer input (connect directly to top-level port)
);
-- BUFG: Global Clock Buffer
-- Virtex-6
-- Xilinx HDL Language Template, version 13.4
cmp_bufg_clk_gen : BUFG
port map (
O => sys_clk_o, -- 1-bit output: Clock buffer output
I => s_sys_clk -- 1-bit input: Clock buffer input
);
end syn;
|
library UNISIM;
use UNISIM.vcomponents.all;
library ieee;
use ieee.std_logic_1164.all;
entity clk_gen is
port(
sys_clk_p_i : in std_logic;
sys_clk_n_i : in std_logic;
sys_clk_o : out std_logic
);
end clk_gen;
architecture syn of clk_gen is
-- Internal clock signal
signal s_sys_clk : std_logic;
begin
-- IBUFGDS: Differential Global Clock Input Buffer
-- Virtex-6
-- Xilinx HDL Language Template, version 13.4
cpm_ibufgds_clk_gen : IBUFGDS
generic map (
DIFF_TERM => FALSE, -- Differential Termination
IBUF_LOW_PWR => TRUE, -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
IOSTANDARD => "DEFAULT"
)
port map (
O => s_sys_clk, -- Clock buffer output
I => sys_clk_p_i, -- Diff_p clock buffer input (connect directly to top-level port)
IB => sys_clk_n_i -- Diff_n clock buffer input (connect directly to top-level port)
);
-- BUFG: Global Clock Buffer
-- Virtex-6
-- Xilinx HDL Language Template, version 13.4
cmp_bufg_clk_gen : BUFG
port map (
O => sys_clk_o, -- 1-bit output: Clock buffer output
I => s_sys_clk -- 1-bit input: Clock buffer input
);
end syn;
|
library UNISIM;
use UNISIM.vcomponents.all;
library ieee;
use ieee.std_logic_1164.all;
entity clk_gen is
port(
sys_clk_p_i : in std_logic;
sys_clk_n_i : in std_logic;
sys_clk_o : out std_logic
);
end clk_gen;
architecture syn of clk_gen is
-- Internal clock signal
signal s_sys_clk : std_logic;
begin
-- IBUFGDS: Differential Global Clock Input Buffer
-- Virtex-6
-- Xilinx HDL Language Template, version 13.4
cpm_ibufgds_clk_gen : IBUFGDS
generic map (
DIFF_TERM => FALSE, -- Differential Termination
IBUF_LOW_PWR => TRUE, -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
IOSTANDARD => "DEFAULT"
)
port map (
O => s_sys_clk, -- Clock buffer output
I => sys_clk_p_i, -- Diff_p clock buffer input (connect directly to top-level port)
IB => sys_clk_n_i -- Diff_n clock buffer input (connect directly to top-level port)
);
-- BUFG: Global Clock Buffer
-- Virtex-6
-- Xilinx HDL Language Template, version 13.4
cmp_bufg_clk_gen : BUFG
port map (
O => sys_clk_o, -- 1-bit output: Clock buffer output
I => s_sys_clk -- 1-bit input: Clock buffer input
);
end syn;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
-- Entity: spi2ahb
-- File: spi2ahb.vhd
-- Author: Jan Andersson - Aeroflex Gaisler AB
-- Contact: [email protected]
-- Description: Simple SPI slave providing a bridge to AMBA AHB
-- See spi2ahbx.vhd and GRIP for documentation
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.conv_std_logic_vector;
library gaisler;
use gaisler.spi.all;
entity spi2ahb is
generic (
-- AHB Configuration
hindex : integer := 0;
--
ahbaddrh : integer := 0;
ahbaddrl : integer := 0;
ahbmaskh : integer := 0;
ahbmaskl : integer := 0;
--
oepol : integer range 0 to 1 := 0;
--
filter : integer range 2 to 512 := 2;
--
cpol : integer range 0 to 1 := 0;
cpha : integer range 0 to 1 := 0
);
port (
rstn : in std_ulogic;
clk : in std_ulogic;
-- AHB master interface
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
-- SPI signals
spii : in spi_in_type;
spio : out spi_out_type
);
end entity spi2ahb;
architecture rtl of spi2ahb is
signal spi2ahbi : spi2ahb_in_type;
begin
bridge : spi2ahbx
generic map (
hindex => hindex,
oepol => oepol,
filter => filter,
cpol => cpol,
cpha => cpha)
port map (
rstn => rstn,
clk => clk,
ahbi => ahbi,
ahbo => ahbo,
spii => spii,
spio => spio,
spi2ahbi => spi2ahbi,
spi2ahbo => open);
spi2ahbi.en <= '1';
spi2ahbi.haddr <= conv_std_logic_vector(ahbaddrh, 16) &
conv_std_logic_vector(ahbaddrl, 16);
spi2ahbi.hmask <= conv_std_logic_vector(ahbmaskh, 16) &
conv_std_logic_vector(ahbmaskl, 16);
end architecture rtl;
|
-- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity alt_dspbuilder_counter is
generic (
USE_USR_ACLR : string := "false";
USE_ENA : string := "false";
USE_CIN : string := "false";
USE_SSET : string := "false";
NDIRECTION : natural := 1;
SVALUE : string := "0";
USE_SLOAD : string := "false";
USE_SCLR : string := "false";
USE_COUT : string := "false";
MODULUS : integer := 256;
USE_CNT_ENA : string := "false";
WIDTH : natural := 8;
USE_ASET : string := "false";
USE_ALOAD : string := "false";
AVALUE : string := "0"
);
port (
user_aclr : in std_logic := '0';
clock : in std_logic := '0';
q : out std_logic_vector(width-1 downto 0);
direction : in std_logic := '0';
sclr : in std_logic := '0';
data : in std_logic_vector(width-1 downto 0) := (others=>'0');
aset : in std_logic := '0';
cout : out std_logic;
sset : in std_logic := '0';
aclr : in std_logic := '0';
cnt_ena : in std_logic := '0';
cin : in std_logic := '0';
ena : in std_logic := '0';
aload : in std_logic := '0';
sload : in std_logic := '0'
);
end entity alt_dspbuilder_counter;
architecture rtl of alt_dspbuilder_counter is
component alt_dspbuilder_counter_GNCXSYJEM5 is
generic (
USE_USR_ACLR : string := "false";
USE_ENA : string := "false";
USE_CIN : string := "false";
USE_SSET : string := "false";
NDIRECTION : natural := 1;
SVALUE : string := "1";
USE_SLOAD : string := "false";
USE_SCLR : string := "true";
USE_COUT : string := "false";
MODULUS : integer := -1;
USE_CNT_ENA : string := "true";
WIDTH : natural := 16;
USE_ASET : string := "false";
USE_ALOAD : string := "false";
AVALUE : string := "0"
);
port (
aclr : in std_logic := '0';
clock : in std_logic := '0';
cnt_ena : in std_logic := '0';
cout : out std_logic;
q : out std_logic_vector(16-1 downto 0);
sclr : in std_logic := '0'
);
end component alt_dspbuilder_counter_GNCXSYJEM5;
component alt_dspbuilder_counter_GNW5IG44CT is
generic (
USE_USR_ACLR : string := "false";
USE_ENA : string := "false";
USE_CIN : string := "false";
USE_SSET : string := "false";
NDIRECTION : natural := 1;
SVALUE : string := "1";
USE_SLOAD : string := "false";
USE_SCLR : string := "true";
USE_COUT : string := "false";
MODULUS : integer := -1;
USE_CNT_ENA : string := "true";
WIDTH : natural := 3;
USE_ASET : string := "false";
USE_ALOAD : string := "false";
AVALUE : string := "0"
);
port (
aclr : in std_logic := '0';
clock : in std_logic := '0';
cnt_ena : in std_logic := '0';
cout : out std_logic;
q : out std_logic_vector(3-1 downto 0);
sclr : in std_logic := '0'
);
end component alt_dspbuilder_counter_GNW5IG44CT;
begin
alt_dspbuilder_counter_GNCXSYJEM5_0: if ((USE_USR_ACLR = "false") and (USE_ENA = "false") and (USE_CIN = "false") and (USE_SSET = "false") and (NDIRECTION = 1) and (SVALUE = "1") and (USE_SLOAD = "false") and (USE_SCLR = "true") and (USE_COUT = "false") and (MODULUS = -1) and (USE_CNT_ENA = "true") and (WIDTH = 16) and (USE_ASET = "false") and (USE_ALOAD = "false") and (AVALUE = "0")) generate
inst_alt_dspbuilder_counter_GNCXSYJEM5_0: alt_dspbuilder_counter_GNCXSYJEM5
generic map(USE_USR_ACLR => "false", USE_ENA => "false", USE_CIN => "false", USE_SSET => "false", NDIRECTION => 1, SVALUE => "1", USE_SLOAD => "false", USE_SCLR => "true", USE_COUT => "false", MODULUS => -1, USE_CNT_ENA => "true", WIDTH => 16, USE_ASET => "false", USE_ALOAD => "false", AVALUE => "0")
port map(aclr => aclr, clock => clock, cnt_ena => cnt_ena, cout => cout, q => q, sclr => sclr);
end generate;
alt_dspbuilder_counter_GNW5IG44CT_1: if ((USE_USR_ACLR = "false") and (USE_ENA = "false") and (USE_CIN = "false") and (USE_SSET = "false") and (NDIRECTION = 1) and (SVALUE = "1") and (USE_SLOAD = "false") and (USE_SCLR = "true") and (USE_COUT = "false") and (MODULUS = -1) and (USE_CNT_ENA = "true") and (WIDTH = 3) and (USE_ASET = "false") and (USE_ALOAD = "false") and (AVALUE = "0")) generate
inst_alt_dspbuilder_counter_GNW5IG44CT_1: alt_dspbuilder_counter_GNW5IG44CT
generic map(USE_USR_ACLR => "false", USE_ENA => "false", USE_CIN => "false", USE_SSET => "false", NDIRECTION => 1, SVALUE => "1", USE_SLOAD => "false", USE_SCLR => "true", USE_COUT => "false", MODULUS => -1, USE_CNT_ENA => "true", WIDTH => 3, USE_ASET => "false", USE_ALOAD => "false", AVALUE => "0")
port map(aclr => aclr, clock => clock, cnt_ena => cnt_ena, cout => cout, q => q, sclr => sclr);
end generate;
assert not (((USE_USR_ACLR = "false") and (USE_ENA = "false") and (USE_CIN = "false") and (USE_SSET = "false") and (NDIRECTION = 1) and (SVALUE = "1") and (USE_SLOAD = "false") and (USE_SCLR = "true") and (USE_COUT = "false") and (MODULUS = -1) and (USE_CNT_ENA = "true") and (WIDTH = 16) and (USE_ASET = "false") and (USE_ALOAD = "false") and (AVALUE = "0")) or ((USE_USR_ACLR = "false") and (USE_ENA = "false") and (USE_CIN = "false") and (USE_SSET = "false") and (NDIRECTION = 1) and (SVALUE = "1") and (USE_SLOAD = "false") and (USE_SCLR = "true") and (USE_COUT = "false") and (MODULUS = -1) and (USE_CNT_ENA = "true") and (WIDTH = 3) and (USE_ASET = "false") and (USE_ALOAD = "false") and (AVALUE = "0")))
report "Please run generate again" severity error;
end architecture rtl;
|
-- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity alt_dspbuilder_counter is
generic (
USE_USR_ACLR : string := "false";
USE_ENA : string := "false";
USE_CIN : string := "false";
USE_SSET : string := "false";
NDIRECTION : natural := 1;
SVALUE : string := "0";
USE_SLOAD : string := "false";
USE_SCLR : string := "false";
USE_COUT : string := "false";
MODULUS : integer := 256;
USE_CNT_ENA : string := "false";
WIDTH : natural := 8;
USE_ASET : string := "false";
USE_ALOAD : string := "false";
AVALUE : string := "0"
);
port (
user_aclr : in std_logic := '0';
clock : in std_logic := '0';
q : out std_logic_vector(width-1 downto 0);
direction : in std_logic := '0';
sclr : in std_logic := '0';
data : in std_logic_vector(width-1 downto 0) := (others=>'0');
aset : in std_logic := '0';
cout : out std_logic;
sset : in std_logic := '0';
aclr : in std_logic := '0';
cnt_ena : in std_logic := '0';
cin : in std_logic := '0';
ena : in std_logic := '0';
aload : in std_logic := '0';
sload : in std_logic := '0'
);
end entity alt_dspbuilder_counter;
architecture rtl of alt_dspbuilder_counter is
component alt_dspbuilder_counter_GNCXSYJEM5 is
generic (
USE_USR_ACLR : string := "false";
USE_ENA : string := "false";
USE_CIN : string := "false";
USE_SSET : string := "false";
NDIRECTION : natural := 1;
SVALUE : string := "1";
USE_SLOAD : string := "false";
USE_SCLR : string := "true";
USE_COUT : string := "false";
MODULUS : integer := -1;
USE_CNT_ENA : string := "true";
WIDTH : natural := 16;
USE_ASET : string := "false";
USE_ALOAD : string := "false";
AVALUE : string := "0"
);
port (
aclr : in std_logic := '0';
clock : in std_logic := '0';
cnt_ena : in std_logic := '0';
cout : out std_logic;
q : out std_logic_vector(16-1 downto 0);
sclr : in std_logic := '0'
);
end component alt_dspbuilder_counter_GNCXSYJEM5;
component alt_dspbuilder_counter_GNW5IG44CT is
generic (
USE_USR_ACLR : string := "false";
USE_ENA : string := "false";
USE_CIN : string := "false";
USE_SSET : string := "false";
NDIRECTION : natural := 1;
SVALUE : string := "1";
USE_SLOAD : string := "false";
USE_SCLR : string := "true";
USE_COUT : string := "false";
MODULUS : integer := -1;
USE_CNT_ENA : string := "true";
WIDTH : natural := 3;
USE_ASET : string := "false";
USE_ALOAD : string := "false";
AVALUE : string := "0"
);
port (
aclr : in std_logic := '0';
clock : in std_logic := '0';
cnt_ena : in std_logic := '0';
cout : out std_logic;
q : out std_logic_vector(3-1 downto 0);
sclr : in std_logic := '0'
);
end component alt_dspbuilder_counter_GNW5IG44CT;
begin
alt_dspbuilder_counter_GNCXSYJEM5_0: if ((USE_USR_ACLR = "false") and (USE_ENA = "false") and (USE_CIN = "false") and (USE_SSET = "false") and (NDIRECTION = 1) and (SVALUE = "1") and (USE_SLOAD = "false") and (USE_SCLR = "true") and (USE_COUT = "false") and (MODULUS = -1) and (USE_CNT_ENA = "true") and (WIDTH = 16) and (USE_ASET = "false") and (USE_ALOAD = "false") and (AVALUE = "0")) generate
inst_alt_dspbuilder_counter_GNCXSYJEM5_0: alt_dspbuilder_counter_GNCXSYJEM5
generic map(USE_USR_ACLR => "false", USE_ENA => "false", USE_CIN => "false", USE_SSET => "false", NDIRECTION => 1, SVALUE => "1", USE_SLOAD => "false", USE_SCLR => "true", USE_COUT => "false", MODULUS => -1, USE_CNT_ENA => "true", WIDTH => 16, USE_ASET => "false", USE_ALOAD => "false", AVALUE => "0")
port map(aclr => aclr, clock => clock, cnt_ena => cnt_ena, cout => cout, q => q, sclr => sclr);
end generate;
alt_dspbuilder_counter_GNW5IG44CT_1: if ((USE_USR_ACLR = "false") and (USE_ENA = "false") and (USE_CIN = "false") and (USE_SSET = "false") and (NDIRECTION = 1) and (SVALUE = "1") and (USE_SLOAD = "false") and (USE_SCLR = "true") and (USE_COUT = "false") and (MODULUS = -1) and (USE_CNT_ENA = "true") and (WIDTH = 3) and (USE_ASET = "false") and (USE_ALOAD = "false") and (AVALUE = "0")) generate
inst_alt_dspbuilder_counter_GNW5IG44CT_1: alt_dspbuilder_counter_GNW5IG44CT
generic map(USE_USR_ACLR => "false", USE_ENA => "false", USE_CIN => "false", USE_SSET => "false", NDIRECTION => 1, SVALUE => "1", USE_SLOAD => "false", USE_SCLR => "true", USE_COUT => "false", MODULUS => -1, USE_CNT_ENA => "true", WIDTH => 3, USE_ASET => "false", USE_ALOAD => "false", AVALUE => "0")
port map(aclr => aclr, clock => clock, cnt_ena => cnt_ena, cout => cout, q => q, sclr => sclr);
end generate;
assert not (((USE_USR_ACLR = "false") and (USE_ENA = "false") and (USE_CIN = "false") and (USE_SSET = "false") and (NDIRECTION = 1) and (SVALUE = "1") and (USE_SLOAD = "false") and (USE_SCLR = "true") and (USE_COUT = "false") and (MODULUS = -1) and (USE_CNT_ENA = "true") and (WIDTH = 16) and (USE_ASET = "false") and (USE_ALOAD = "false") and (AVALUE = "0")) or ((USE_USR_ACLR = "false") and (USE_ENA = "false") and (USE_CIN = "false") and (USE_SSET = "false") and (NDIRECTION = 1) and (SVALUE = "1") and (USE_SLOAD = "false") and (USE_SCLR = "true") and (USE_COUT = "false") and (MODULUS = -1) and (USE_CNT_ENA = "true") and (WIDTH = 3) and (USE_ASET = "false") and (USE_ALOAD = "false") and (AVALUE = "0")))
report "Please run generate again" severity error;
end architecture rtl;
|
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|
`protect begin_protected
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|
`protect begin_protected
`protect version = 1
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
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`protect end_protected
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.tl_string_util_pkg.all;
entity noise_generator_tb is
end;
architecture tb of noise_generator_tb is
constant c_type : string := "Fibonacci";
-- constant c_polynom : std_logic_vector := X"E10000";
constant c_polynom : std_logic_vector := "11100100000000000000000";
signal polynom : std_logic_vector(22 downto 0) := c_polynom;
-- constant c_type : string := "Galois";
-- constant c_polynom : std_logic_vector := X"5D6DCB";
-- constant c_seed : std_logic_vector := X"000001";
constant c_seed : std_logic_vector := "11111111111111111111111";
signal clock : std_logic := '0';
signal reset : std_logic;
signal q : std_logic_vector(c_polynom'length-1 downto 0);
signal selected_bits : std_logic_vector(7 downto 0);
begin
clock <= not clock after 10 ns;
--reset <= '1', '0' after 100 ns;
i_lfsr: entity work.noise_generator
generic map (
g_type => c_type,
g_polynom => c_polynom,
g_fixed_polynom => false,
g_seed => c_seed )
port map (
clock => clock,
reset => reset,
enable => '1',
polynom => polynom,
q => q );
selected_bits(7) <= q(22);
selected_bits(6) <= q(20);
selected_bits(5) <= q(16);
selected_bits(4) <= q(13);
selected_bits(3) <= q(11);
selected_bits(2) <= q(7);
selected_bits(1) <= q(4);
selected_bits(0) <= q(2);
p_test: process
variable poly : std_logic_vector(7 downto 0);
variable count : integer;
function count_bits(p : std_logic_vector) return integer is
variable c : integer;
begin
c := 0;
for i in p'range loop
if p(i)='1' then
c := c + 1;
end if;
end loop;
return c;
end function;
procedure perform_test is
begin
reset <= '1';
wait until clock='1';
wait until clock='1';
wait until clock='1';
reset <= '0';
wait until clock='1';
wait until clock='1';
count := 1;
while q /= c_seed loop
wait until clock='1';
count := count + 1;
end loop;
report "Polynom = " & hstr(polynom) & ". Length of LFSR = " & integer'image(count) severity note;
end procedure;
begin
reset <= '0';
for i in 0 to 255 loop -- test 256 different polynoms, at least; ones that result in an even number of bits set
poly := std_logic_vector(to_unsigned(i, 8));
if(count_bits(poly) mod 2) = 1 then
polynom <= "1" & poly & "00000000000000";
perform_test;
end if;
end loop;
wait;
end process;
-- assert count=0 or q/=c_seed
-- report "Length of LFSR = " & integer'image(count)
-- severity failure;
-- count := count + 1;
-- end if;
-- end if;
-- end process;
--
end tb;
-- FF 11111111111111111111111
-- FF 11111111111111111111110
-- FF 11111111111111111111100
-- FE 11111111111111111111000 2
-- FE 11111111111111111110000
-- FC 11111111111111111100000 4
-- FC 11111111111111111000000
-- FC 11111111111111110000000
-- F8 11111111111111100000000 7
-- F8 11111111111111000000000
-- F8 11111111111110000000000
-- F8 11111111111100000000000
-- F0 11111111111000000000000 11
-- F0 11111111110000000000000
-- E0 11111111100000000000000 13
-- E0 11111111000000000000000
-- E0 11111110000000000000000
-- C0 11111100000000000000000 16
-- C0 1111100000000000000000-
-- C0 11110000000000000000001
-- C0 1110000000000000000001-
-- 81 110000000000000000001-- 20
-- 81 10000000000000000001---
-- 03 000000000000000000----- 22
-- 03
-- 06
-- 06
-- 06
--
--
-- |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.tl_string_util_pkg.all;
entity noise_generator_tb is
end;
architecture tb of noise_generator_tb is
constant c_type : string := "Fibonacci";
-- constant c_polynom : std_logic_vector := X"E10000";
constant c_polynom : std_logic_vector := "11100100000000000000000";
signal polynom : std_logic_vector(22 downto 0) := c_polynom;
-- constant c_type : string := "Galois";
-- constant c_polynom : std_logic_vector := X"5D6DCB";
-- constant c_seed : std_logic_vector := X"000001";
constant c_seed : std_logic_vector := "11111111111111111111111";
signal clock : std_logic := '0';
signal reset : std_logic;
signal q : std_logic_vector(c_polynom'length-1 downto 0);
signal selected_bits : std_logic_vector(7 downto 0);
begin
clock <= not clock after 10 ns;
--reset <= '1', '0' after 100 ns;
i_lfsr: entity work.noise_generator
generic map (
g_type => c_type,
g_polynom => c_polynom,
g_fixed_polynom => false,
g_seed => c_seed )
port map (
clock => clock,
reset => reset,
enable => '1',
polynom => polynom,
q => q );
selected_bits(7) <= q(22);
selected_bits(6) <= q(20);
selected_bits(5) <= q(16);
selected_bits(4) <= q(13);
selected_bits(3) <= q(11);
selected_bits(2) <= q(7);
selected_bits(1) <= q(4);
selected_bits(0) <= q(2);
p_test: process
variable poly : std_logic_vector(7 downto 0);
variable count : integer;
function count_bits(p : std_logic_vector) return integer is
variable c : integer;
begin
c := 0;
for i in p'range loop
if p(i)='1' then
c := c + 1;
end if;
end loop;
return c;
end function;
procedure perform_test is
begin
reset <= '1';
wait until clock='1';
wait until clock='1';
wait until clock='1';
reset <= '0';
wait until clock='1';
wait until clock='1';
count := 1;
while q /= c_seed loop
wait until clock='1';
count := count + 1;
end loop;
report "Polynom = " & hstr(polynom) & ". Length of LFSR = " & integer'image(count) severity note;
end procedure;
begin
reset <= '0';
for i in 0 to 255 loop -- test 256 different polynoms, at least; ones that result in an even number of bits set
poly := std_logic_vector(to_unsigned(i, 8));
if(count_bits(poly) mod 2) = 1 then
polynom <= "1" & poly & "00000000000000";
perform_test;
end if;
end loop;
wait;
end process;
-- assert count=0 or q/=c_seed
-- report "Length of LFSR = " & integer'image(count)
-- severity failure;
-- count := count + 1;
-- end if;
-- end if;
-- end process;
--
end tb;
-- FF 11111111111111111111111
-- FF 11111111111111111111110
-- FF 11111111111111111111100
-- FE 11111111111111111111000 2
-- FE 11111111111111111110000
-- FC 11111111111111111100000 4
-- FC 11111111111111111000000
-- FC 11111111111111110000000
-- F8 11111111111111100000000 7
-- F8 11111111111111000000000
-- F8 11111111111110000000000
-- F8 11111111111100000000000
-- F0 11111111111000000000000 11
-- F0 11111111110000000000000
-- E0 11111111100000000000000 13
-- E0 11111111000000000000000
-- E0 11111110000000000000000
-- C0 11111100000000000000000 16
-- C0 1111100000000000000000-
-- C0 11110000000000000000001
-- C0 1110000000000000000001-
-- 81 110000000000000000001-- 20
-- 81 10000000000000000001---
-- 03 000000000000000000----- 22
-- 03
-- 06
-- 06
-- 06
--
--
-- |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.tl_string_util_pkg.all;
entity noise_generator_tb is
end;
architecture tb of noise_generator_tb is
constant c_type : string := "Fibonacci";
-- constant c_polynom : std_logic_vector := X"E10000";
constant c_polynom : std_logic_vector := "11100100000000000000000";
signal polynom : std_logic_vector(22 downto 0) := c_polynom;
-- constant c_type : string := "Galois";
-- constant c_polynom : std_logic_vector := X"5D6DCB";
-- constant c_seed : std_logic_vector := X"000001";
constant c_seed : std_logic_vector := "11111111111111111111111";
signal clock : std_logic := '0';
signal reset : std_logic;
signal q : std_logic_vector(c_polynom'length-1 downto 0);
signal selected_bits : std_logic_vector(7 downto 0);
begin
clock <= not clock after 10 ns;
--reset <= '1', '0' after 100 ns;
i_lfsr: entity work.noise_generator
generic map (
g_type => c_type,
g_polynom => c_polynom,
g_fixed_polynom => false,
g_seed => c_seed )
port map (
clock => clock,
reset => reset,
enable => '1',
polynom => polynom,
q => q );
selected_bits(7) <= q(22);
selected_bits(6) <= q(20);
selected_bits(5) <= q(16);
selected_bits(4) <= q(13);
selected_bits(3) <= q(11);
selected_bits(2) <= q(7);
selected_bits(1) <= q(4);
selected_bits(0) <= q(2);
p_test: process
variable poly : std_logic_vector(7 downto 0);
variable count : integer;
function count_bits(p : std_logic_vector) return integer is
variable c : integer;
begin
c := 0;
for i in p'range loop
if p(i)='1' then
c := c + 1;
end if;
end loop;
return c;
end function;
procedure perform_test is
begin
reset <= '1';
wait until clock='1';
wait until clock='1';
wait until clock='1';
reset <= '0';
wait until clock='1';
wait until clock='1';
count := 1;
while q /= c_seed loop
wait until clock='1';
count := count + 1;
end loop;
report "Polynom = " & hstr(polynom) & ". Length of LFSR = " & integer'image(count) severity note;
end procedure;
begin
reset <= '0';
for i in 0 to 255 loop -- test 256 different polynoms, at least; ones that result in an even number of bits set
poly := std_logic_vector(to_unsigned(i, 8));
if(count_bits(poly) mod 2) = 1 then
polynom <= "1" & poly & "00000000000000";
perform_test;
end if;
end loop;
wait;
end process;
-- assert count=0 or q/=c_seed
-- report "Length of LFSR = " & integer'image(count)
-- severity failure;
-- count := count + 1;
-- end if;
-- end if;
-- end process;
--
end tb;
-- FF 11111111111111111111111
-- FF 11111111111111111111110
-- FF 11111111111111111111100
-- FE 11111111111111111111000 2
-- FE 11111111111111111110000
-- FC 11111111111111111100000 4
-- FC 11111111111111111000000
-- FC 11111111111111110000000
-- F8 11111111111111100000000 7
-- F8 11111111111111000000000
-- F8 11111111111110000000000
-- F8 11111111111100000000000
-- F0 11111111111000000000000 11
-- F0 11111111110000000000000
-- E0 11111111100000000000000 13
-- E0 11111111000000000000000
-- E0 11111110000000000000000
-- C0 11111100000000000000000 16
-- C0 1111100000000000000000-
-- C0 11110000000000000000001
-- C0 1110000000000000000001-
-- 81 110000000000000000001-- 20
-- 81 10000000000000000001---
-- 03 000000000000000000----- 22
-- 03
-- 06
-- 06
-- 06
--
--
-- |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.tl_string_util_pkg.all;
entity noise_generator_tb is
end;
architecture tb of noise_generator_tb is
constant c_type : string := "Fibonacci";
-- constant c_polynom : std_logic_vector := X"E10000";
constant c_polynom : std_logic_vector := "11100100000000000000000";
signal polynom : std_logic_vector(22 downto 0) := c_polynom;
-- constant c_type : string := "Galois";
-- constant c_polynom : std_logic_vector := X"5D6DCB";
-- constant c_seed : std_logic_vector := X"000001";
constant c_seed : std_logic_vector := "11111111111111111111111";
signal clock : std_logic := '0';
signal reset : std_logic;
signal q : std_logic_vector(c_polynom'length-1 downto 0);
signal selected_bits : std_logic_vector(7 downto 0);
begin
clock <= not clock after 10 ns;
--reset <= '1', '0' after 100 ns;
i_lfsr: entity work.noise_generator
generic map (
g_type => c_type,
g_polynom => c_polynom,
g_fixed_polynom => false,
g_seed => c_seed )
port map (
clock => clock,
reset => reset,
enable => '1',
polynom => polynom,
q => q );
selected_bits(7) <= q(22);
selected_bits(6) <= q(20);
selected_bits(5) <= q(16);
selected_bits(4) <= q(13);
selected_bits(3) <= q(11);
selected_bits(2) <= q(7);
selected_bits(1) <= q(4);
selected_bits(0) <= q(2);
p_test: process
variable poly : std_logic_vector(7 downto 0);
variable count : integer;
function count_bits(p : std_logic_vector) return integer is
variable c : integer;
begin
c := 0;
for i in p'range loop
if p(i)='1' then
c := c + 1;
end if;
end loop;
return c;
end function;
procedure perform_test is
begin
reset <= '1';
wait until clock='1';
wait until clock='1';
wait until clock='1';
reset <= '0';
wait until clock='1';
wait until clock='1';
count := 1;
while q /= c_seed loop
wait until clock='1';
count := count + 1;
end loop;
report "Polynom = " & hstr(polynom) & ". Length of LFSR = " & integer'image(count) severity note;
end procedure;
begin
reset <= '0';
for i in 0 to 255 loop -- test 256 different polynoms, at least; ones that result in an even number of bits set
poly := std_logic_vector(to_unsigned(i, 8));
if(count_bits(poly) mod 2) = 1 then
polynom <= "1" & poly & "00000000000000";
perform_test;
end if;
end loop;
wait;
end process;
-- assert count=0 or q/=c_seed
-- report "Length of LFSR = " & integer'image(count)
-- severity failure;
-- count := count + 1;
-- end if;
-- end if;
-- end process;
--
end tb;
-- FF 11111111111111111111111
-- FF 11111111111111111111110
-- FF 11111111111111111111100
-- FE 11111111111111111111000 2
-- FE 11111111111111111110000
-- FC 11111111111111111100000 4
-- FC 11111111111111111000000
-- FC 11111111111111110000000
-- F8 11111111111111100000000 7
-- F8 11111111111111000000000
-- F8 11111111111110000000000
-- F8 11111111111100000000000
-- F0 11111111111000000000000 11
-- F0 11111111110000000000000
-- E0 11111111100000000000000 13
-- E0 11111111000000000000000
-- E0 11111110000000000000000
-- C0 11111100000000000000000 16
-- C0 1111100000000000000000-
-- C0 11110000000000000000001
-- C0 1110000000000000000001-
-- 81 110000000000000000001-- 20
-- 81 10000000000000000001---
-- 03 000000000000000000----- 22
-- 03
-- 06
-- 06
-- 06
--
--
-- |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.tl_string_util_pkg.all;
entity noise_generator_tb is
end;
architecture tb of noise_generator_tb is
constant c_type : string := "Fibonacci";
-- constant c_polynom : std_logic_vector := X"E10000";
constant c_polynom : std_logic_vector := "11100100000000000000000";
signal polynom : std_logic_vector(22 downto 0) := c_polynom;
-- constant c_type : string := "Galois";
-- constant c_polynom : std_logic_vector := X"5D6DCB";
-- constant c_seed : std_logic_vector := X"000001";
constant c_seed : std_logic_vector := "11111111111111111111111";
signal clock : std_logic := '0';
signal reset : std_logic;
signal q : std_logic_vector(c_polynom'length-1 downto 0);
signal selected_bits : std_logic_vector(7 downto 0);
begin
clock <= not clock after 10 ns;
--reset <= '1', '0' after 100 ns;
i_lfsr: entity work.noise_generator
generic map (
g_type => c_type,
g_polynom => c_polynom,
g_fixed_polynom => false,
g_seed => c_seed )
port map (
clock => clock,
reset => reset,
enable => '1',
polynom => polynom,
q => q );
selected_bits(7) <= q(22);
selected_bits(6) <= q(20);
selected_bits(5) <= q(16);
selected_bits(4) <= q(13);
selected_bits(3) <= q(11);
selected_bits(2) <= q(7);
selected_bits(1) <= q(4);
selected_bits(0) <= q(2);
p_test: process
variable poly : std_logic_vector(7 downto 0);
variable count : integer;
function count_bits(p : std_logic_vector) return integer is
variable c : integer;
begin
c := 0;
for i in p'range loop
if p(i)='1' then
c := c + 1;
end if;
end loop;
return c;
end function;
procedure perform_test is
begin
reset <= '1';
wait until clock='1';
wait until clock='1';
wait until clock='1';
reset <= '0';
wait until clock='1';
wait until clock='1';
count := 1;
while q /= c_seed loop
wait until clock='1';
count := count + 1;
end loop;
report "Polynom = " & hstr(polynom) & ". Length of LFSR = " & integer'image(count) severity note;
end procedure;
begin
reset <= '0';
for i in 0 to 255 loop -- test 256 different polynoms, at least; ones that result in an even number of bits set
poly := std_logic_vector(to_unsigned(i, 8));
if(count_bits(poly) mod 2) = 1 then
polynom <= "1" & poly & "00000000000000";
perform_test;
end if;
end loop;
wait;
end process;
-- assert count=0 or q/=c_seed
-- report "Length of LFSR = " & integer'image(count)
-- severity failure;
-- count := count + 1;
-- end if;
-- end if;
-- end process;
--
end tb;
-- FF 11111111111111111111111
-- FF 11111111111111111111110
-- FF 11111111111111111111100
-- FE 11111111111111111111000 2
-- FE 11111111111111111110000
-- FC 11111111111111111100000 4
-- FC 11111111111111111000000
-- FC 11111111111111110000000
-- F8 11111111111111100000000 7
-- F8 11111111111111000000000
-- F8 11111111111110000000000
-- F8 11111111111100000000000
-- F0 11111111111000000000000 11
-- F0 11111111110000000000000
-- E0 11111111100000000000000 13
-- E0 11111111000000000000000
-- E0 11111110000000000000000
-- C0 11111100000000000000000 16
-- C0 1111100000000000000000-
-- C0 11110000000000000000001
-- C0 1110000000000000000001-
-- 81 110000000000000000001-- 20
-- 81 10000000000000000001---
-- 03 000000000000000000----- 22
-- 03
-- 06
-- 06
-- 06
--
--
-- |
library verilog;
use verilog.vl_types.all;
entity NbitCounter_vlg_check_tst is
port(
Q : in vl_logic_vector(15 downto 0);
sampler_rx : in vl_logic
);
end NbitCounter_vlg_check_tst;
|
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