content
stringlengths 1
1.04M
⌀ |
|---|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: cdcfifo_synth.vhd
--
-- Description:
-- This is the demo testbench for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.STD_LOGIC_1164.ALL;
USE ieee.STD_LOGIC_unsigned.ALL;
USE IEEE.STD_LOGIC_arith.ALL;
USE ieee.numeric_std.ALL;
USE ieee.STD_LOGIC_misc.ALL;
LIBRARY std;
USE std.textio.ALL;
LIBRARY work;
USE work.cdcfifo_pkg.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY cdcfifo_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE simulation_arch OF cdcfifo_synth IS
-- FIFO interface signal declarations
SIGNAL wr_clk_i : STD_LOGIC;
SIGNAL rd_clk_i : STD_LOGIC;
SIGNAL almost_full : STD_LOGIC;
SIGNAL almost_empty : STD_LOGIC;
SIGNAL rst : STD_LOGIC;
SIGNAL wr_en : STD_LOGIC;
SIGNAL rd_en : STD_LOGIC;
SIGNAL din : STD_LOGIC_VECTOR(8-1 DOWNTO 0);
SIGNAL dout : STD_LOGIC_VECTOR(8-1 DOWNTO 0);
SIGNAL full : STD_LOGIC;
SIGNAL empty : STD_LOGIC;
-- TB Signals
SIGNAL wr_data : STD_LOGIC_VECTOR(8-1 DOWNTO 0);
SIGNAL dout_i : STD_LOGIC_VECTOR(8-1 DOWNTO 0);
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL full_i : STD_LOGIC := '0';
SIGNAL empty_i : STD_LOGIC := '0';
SIGNAL almost_full_i : STD_LOGIC := '0';
SIGNAL almost_empty_i : STD_LOGIC := '0';
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL dout_chk_i : STD_LOGIC := '0';
SIGNAL rst_int_rd : STD_LOGIC := '0';
SIGNAL rst_int_wr : STD_LOGIC := '0';
SIGNAL rst_s_wr1 : STD_LOGIC := '0';
SIGNAL rst_s_wr2 : STD_LOGIC := '0';
SIGNAL rst_gen_rd : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL rst_s_wr3 : STD_LOGIC := '0';
SIGNAL rst_s_rd : STD_LOGIC := '0';
SIGNAL reset_en : STD_LOGIC := '0';
SIGNAL rst_async_wr1 : STD_LOGIC := '0';
SIGNAL rst_async_wr2 : STD_LOGIC := '0';
SIGNAL rst_async_wr3 : STD_LOGIC := '0';
SIGNAL rst_async_rd1 : STD_LOGIC := '0';
SIGNAL rst_async_rd2 : STD_LOGIC := '0';
SIGNAL rst_async_rd3 : STD_LOGIC := '0';
BEGIN
---- Reset generation logic -----
rst_int_wr <= rst_async_wr3 OR rst_s_wr3;
rst_int_rd <= rst_async_rd3 OR rst_s_rd;
--Testbench reset synchronization
PROCESS(rd_clk_i,RESET)
BEGIN
IF(RESET = '1') THEN
rst_async_rd1 <= '1';
rst_async_rd2 <= '1';
rst_async_rd3 <= '1';
ELSIF(rd_clk_i'event AND rd_clk_i='1') THEN
rst_async_rd1 <= RESET;
rst_async_rd2 <= rst_async_rd1;
rst_async_rd3 <= rst_async_rd2;
END IF;
END PROCESS;
PROCESS(wr_clk_i,RESET)
BEGIN
IF(RESET = '1') THEN
rst_async_wr1 <= '1';
rst_async_wr2 <= '1';
rst_async_wr3 <= '1';
ELSIF(wr_clk_i'event AND wr_clk_i='1') THEN
rst_async_wr1 <= RESET;
rst_async_wr2 <= rst_async_wr1;
rst_async_wr3 <= rst_async_wr2;
END IF;
END PROCESS;
--Soft reset for core and testbench
PROCESS(rd_clk_i)
BEGIN
IF(rd_clk_i'event AND rd_clk_i='1') THEN
rst_gen_rd <= rst_gen_rd + "1";
IF(reset_en = '1' AND AND_REDUCE(rst_gen_rd) = '1') THEN
rst_s_rd <= '1';
assert false
report "Reset applied..Memory Collision checks are not valid"
severity note;
ELSE
IF(AND_REDUCE(rst_gen_rd) = '1' AND rst_s_rd = '1') THEN
rst_s_rd <= '0';
END IF;
END IF;
END IF;
END PROCESS;
PROCESS(wr_clk_i)
BEGIN
IF(wr_clk_i'event AND wr_clk_i='1') THEN
rst_s_wr1 <= rst_s_rd;
rst_s_wr2 <= rst_s_wr1;
rst_s_wr3 <= rst_s_wr2;
IF(rst_s_wr3 = '1' AND rst_s_wr2 = '0') THEN
assert false
report "Reset removed..Memory Collision checks are valid"
severity note;
END IF;
END IF;
END PROCESS;
------------------
---- Clock buffers for testbench ----
wr_clk_i <= WR_CLK;
rd_clk_i <= RD_CLK;
------------------
rst <= RESET OR rst_s_rd AFTER 12 ns;
din <= wr_data;
dout_i <= dout;
wr_en <= wr_en_i;
rd_en <= rd_en_i;
full_i <= full;
empty_i <= empty;
almost_empty_i <= almost_empty;
almost_full_i <= almost_full;
fg_dg_nv: cdcfifo_dgen
GENERIC MAP (
C_DIN_WIDTH => 8,
C_DOUT_WIDTH => 8,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP ( -- Write Port
RESET => rst_int_wr,
WR_CLK => wr_clk_i,
PRC_WR_EN => prc_we_i,
FULL => full_i,
WR_EN => wr_en_i,
WR_DATA => wr_data
);
fg_dv_nv: cdcfifo_dverif
GENERIC MAP (
C_DOUT_WIDTH => 8,
C_DIN_WIDTH => 8,
C_USE_EMBEDDED_REG => 0,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP(
RESET => rst_int_rd,
RD_CLK => rd_clk_i,
PRC_RD_EN => prc_re_i,
RD_EN => rd_en_i,
EMPTY => empty_i,
DATA_OUT => dout_i,
DOUT_CHK => dout_chk_i
);
fg_pc_nv: cdcfifo_pctrl
GENERIC MAP (
AXI_CHANNEL => "Native",
C_APPLICATION_TYPE => 0,
C_DOUT_WIDTH => 8,
C_DIN_WIDTH => 8,
C_WR_PNTR_WIDTH => 11,
C_RD_PNTR_WIDTH => 11,
C_CH_TYPE => 0,
FREEZEON_ERROR => FREEZEON_ERROR,
TB_SEED => TB_SEED,
TB_STOP_CNT => TB_STOP_CNT
)
PORT MAP(
RESET_WR => rst_int_wr,
RESET_RD => rst_int_rd,
RESET_EN => reset_en,
WR_CLK => wr_clk_i,
RD_CLK => rd_clk_i,
PRC_WR_EN => prc_we_i,
PRC_RD_EN => prc_re_i,
FULL => full_i,
ALMOST_FULL => almost_full_i,
ALMOST_EMPTY => almost_empty_i,
DOUT_CHK => dout_chk_i,
EMPTY => empty_i,
DATA_IN => wr_data,
DATA_OUT => dout,
SIM_DONE => SIM_DONE,
STATUS => STATUS
);
cdcfifo_inst : cdcfifo_exdes
PORT MAP (
WR_CLK => wr_clk_i,
RD_CLK => rd_clk_i,
ALMOST_FULL => almost_full,
ALMOST_EMPTY => almost_empty,
RST => rst,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: cdcfifo_synth.vhd
--
-- Description:
-- This is the demo testbench for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.STD_LOGIC_1164.ALL;
USE ieee.STD_LOGIC_unsigned.ALL;
USE IEEE.STD_LOGIC_arith.ALL;
USE ieee.numeric_std.ALL;
USE ieee.STD_LOGIC_misc.ALL;
LIBRARY std;
USE std.textio.ALL;
LIBRARY work;
USE work.cdcfifo_pkg.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY cdcfifo_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE simulation_arch OF cdcfifo_synth IS
-- FIFO interface signal declarations
SIGNAL wr_clk_i : STD_LOGIC;
SIGNAL rd_clk_i : STD_LOGIC;
SIGNAL almost_full : STD_LOGIC;
SIGNAL almost_empty : STD_LOGIC;
SIGNAL rst : STD_LOGIC;
SIGNAL wr_en : STD_LOGIC;
SIGNAL rd_en : STD_LOGIC;
SIGNAL din : STD_LOGIC_VECTOR(8-1 DOWNTO 0);
SIGNAL dout : STD_LOGIC_VECTOR(8-1 DOWNTO 0);
SIGNAL full : STD_LOGIC;
SIGNAL empty : STD_LOGIC;
-- TB Signals
SIGNAL wr_data : STD_LOGIC_VECTOR(8-1 DOWNTO 0);
SIGNAL dout_i : STD_LOGIC_VECTOR(8-1 DOWNTO 0);
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL full_i : STD_LOGIC := '0';
SIGNAL empty_i : STD_LOGIC := '0';
SIGNAL almost_full_i : STD_LOGIC := '0';
SIGNAL almost_empty_i : STD_LOGIC := '0';
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL dout_chk_i : STD_LOGIC := '0';
SIGNAL rst_int_rd : STD_LOGIC := '0';
SIGNAL rst_int_wr : STD_LOGIC := '0';
SIGNAL rst_s_wr1 : STD_LOGIC := '0';
SIGNAL rst_s_wr2 : STD_LOGIC := '0';
SIGNAL rst_gen_rd : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL rst_s_wr3 : STD_LOGIC := '0';
SIGNAL rst_s_rd : STD_LOGIC := '0';
SIGNAL reset_en : STD_LOGIC := '0';
SIGNAL rst_async_wr1 : STD_LOGIC := '0';
SIGNAL rst_async_wr2 : STD_LOGIC := '0';
SIGNAL rst_async_wr3 : STD_LOGIC := '0';
SIGNAL rst_async_rd1 : STD_LOGIC := '0';
SIGNAL rst_async_rd2 : STD_LOGIC := '0';
SIGNAL rst_async_rd3 : STD_LOGIC := '0';
BEGIN
---- Reset generation logic -----
rst_int_wr <= rst_async_wr3 OR rst_s_wr3;
rst_int_rd <= rst_async_rd3 OR rst_s_rd;
--Testbench reset synchronization
PROCESS(rd_clk_i,RESET)
BEGIN
IF(RESET = '1') THEN
rst_async_rd1 <= '1';
rst_async_rd2 <= '1';
rst_async_rd3 <= '1';
ELSIF(rd_clk_i'event AND rd_clk_i='1') THEN
rst_async_rd1 <= RESET;
rst_async_rd2 <= rst_async_rd1;
rst_async_rd3 <= rst_async_rd2;
END IF;
END PROCESS;
PROCESS(wr_clk_i,RESET)
BEGIN
IF(RESET = '1') THEN
rst_async_wr1 <= '1';
rst_async_wr2 <= '1';
rst_async_wr3 <= '1';
ELSIF(wr_clk_i'event AND wr_clk_i='1') THEN
rst_async_wr1 <= RESET;
rst_async_wr2 <= rst_async_wr1;
rst_async_wr3 <= rst_async_wr2;
END IF;
END PROCESS;
--Soft reset for core and testbench
PROCESS(rd_clk_i)
BEGIN
IF(rd_clk_i'event AND rd_clk_i='1') THEN
rst_gen_rd <= rst_gen_rd + "1";
IF(reset_en = '1' AND AND_REDUCE(rst_gen_rd) = '1') THEN
rst_s_rd <= '1';
assert false
report "Reset applied..Memory Collision checks are not valid"
severity note;
ELSE
IF(AND_REDUCE(rst_gen_rd) = '1' AND rst_s_rd = '1') THEN
rst_s_rd <= '0';
END IF;
END IF;
END IF;
END PROCESS;
PROCESS(wr_clk_i)
BEGIN
IF(wr_clk_i'event AND wr_clk_i='1') THEN
rst_s_wr1 <= rst_s_rd;
rst_s_wr2 <= rst_s_wr1;
rst_s_wr3 <= rst_s_wr2;
IF(rst_s_wr3 = '1' AND rst_s_wr2 = '0') THEN
assert false
report "Reset removed..Memory Collision checks are valid"
severity note;
END IF;
END IF;
END PROCESS;
------------------
---- Clock buffers for testbench ----
wr_clk_i <= WR_CLK;
rd_clk_i <= RD_CLK;
------------------
rst <= RESET OR rst_s_rd AFTER 12 ns;
din <= wr_data;
dout_i <= dout;
wr_en <= wr_en_i;
rd_en <= rd_en_i;
full_i <= full;
empty_i <= empty;
almost_empty_i <= almost_empty;
almost_full_i <= almost_full;
fg_dg_nv: cdcfifo_dgen
GENERIC MAP (
C_DIN_WIDTH => 8,
C_DOUT_WIDTH => 8,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP ( -- Write Port
RESET => rst_int_wr,
WR_CLK => wr_clk_i,
PRC_WR_EN => prc_we_i,
FULL => full_i,
WR_EN => wr_en_i,
WR_DATA => wr_data
);
fg_dv_nv: cdcfifo_dverif
GENERIC MAP (
C_DOUT_WIDTH => 8,
C_DIN_WIDTH => 8,
C_USE_EMBEDDED_REG => 0,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP(
RESET => rst_int_rd,
RD_CLK => rd_clk_i,
PRC_RD_EN => prc_re_i,
RD_EN => rd_en_i,
EMPTY => empty_i,
DATA_OUT => dout_i,
DOUT_CHK => dout_chk_i
);
fg_pc_nv: cdcfifo_pctrl
GENERIC MAP (
AXI_CHANNEL => "Native",
C_APPLICATION_TYPE => 0,
C_DOUT_WIDTH => 8,
C_DIN_WIDTH => 8,
C_WR_PNTR_WIDTH => 11,
C_RD_PNTR_WIDTH => 11,
C_CH_TYPE => 0,
FREEZEON_ERROR => FREEZEON_ERROR,
TB_SEED => TB_SEED,
TB_STOP_CNT => TB_STOP_CNT
)
PORT MAP(
RESET_WR => rst_int_wr,
RESET_RD => rst_int_rd,
RESET_EN => reset_en,
WR_CLK => wr_clk_i,
RD_CLK => rd_clk_i,
PRC_WR_EN => prc_we_i,
PRC_RD_EN => prc_re_i,
FULL => full_i,
ALMOST_FULL => almost_full_i,
ALMOST_EMPTY => almost_empty_i,
DOUT_CHK => dout_chk_i,
EMPTY => empty_i,
DATA_IN => wr_data,
DATA_OUT => dout,
SIM_DONE => SIM_DONE,
STATUS => STATUS
);
cdcfifo_inst : cdcfifo_exdes
PORT MAP (
WR_CLK => wr_clk_i,
RD_CLK => rd_clk_i,
ALMOST_FULL => almost_full,
ALMOST_EMPTY => almost_empty,
RST => rst,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
END ARCHITECTURE;
|
library verilog;
use verilog.vl_types.all;
entity F2DSS_ACE_MISC_APB3 is
port(
PRESETN : in vl_logic;
PRDATA_SSE : in vl_logic_vector(15 downto 0);
PRDATA_PPE : in vl_logic_vector(31 downto 0);
PRDATA_MISC : in vl_logic_vector(31 downto 0);
PREADY_SSE : in vl_logic;
PREADY_PPE : in vl_logic;
PREADY_MISC : in vl_logic;
PSEL_SSE : out vl_logic;
PSEL_PPE : out vl_logic;
PSEL_MISC : out vl_logic;
PADDR : in vl_logic_vector(12 downto 0);
PSEL : in vl_logic;
PRDATA : out vl_logic_vector(31 downto 0);
PREADY : out vl_logic;
PSLVERR : out vl_logic
);
end F2DSS_ACE_MISC_APB3;
|
library verilog;
use verilog.vl_types.all;
entity F2DSS_ACE_MISC_APB3 is
port(
PRESETN : in vl_logic;
PRDATA_SSE : in vl_logic_vector(15 downto 0);
PRDATA_PPE : in vl_logic_vector(31 downto 0);
PRDATA_MISC : in vl_logic_vector(31 downto 0);
PREADY_SSE : in vl_logic;
PREADY_PPE : in vl_logic;
PREADY_MISC : in vl_logic;
PSEL_SSE : out vl_logic;
PSEL_PPE : out vl_logic;
PSEL_MISC : out vl_logic;
PADDR : in vl_logic_vector(12 downto 0);
PSEL : in vl_logic;
PRDATA : out vl_logic_vector(31 downto 0);
PREADY : out vl_logic;
PSLVERR : out vl_logic
);
end F2DSS_ACE_MISC_APB3;
|
library verilog;
use verilog.vl_types.all;
entity F2DSS_ACE_MISC_APB3 is
port(
PRESETN : in vl_logic;
PRDATA_SSE : in vl_logic_vector(15 downto 0);
PRDATA_PPE : in vl_logic_vector(31 downto 0);
PRDATA_MISC : in vl_logic_vector(31 downto 0);
PREADY_SSE : in vl_logic;
PREADY_PPE : in vl_logic;
PREADY_MISC : in vl_logic;
PSEL_SSE : out vl_logic;
PSEL_PPE : out vl_logic;
PSEL_MISC : out vl_logic;
PADDR : in vl_logic_vector(12 downto 0);
PSEL : in vl_logic;
PRDATA : out vl_logic_vector(31 downto 0);
PREADY : out vl_logic;
PSLVERR : out vl_logic
);
end F2DSS_ACE_MISC_APB3;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: ddrspm
-- File: ddrspm.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: 16-, 32- or 64-bit DDR266 memory controller module.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
library gaisler;
use grlib.devices.all;
use gaisler.ddrpkg.all;
library techmap;
use techmap.gencomp.all;
entity ddrspa is
generic (
fabtech : integer := virtex2;
memtech : integer := 0;
rskew : integer := 0;
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#f00#;
ioaddr : integer := 16#000#;
iomask : integer := 16#fff#;
MHz : integer := 100;
clkmul : integer := 2;
clkdiv : integer := 2;
col : integer := 9;
Mbyte : integer := 16;
rstdel : integer := 200;
pwron : integer := 0;
oepol : integer := 0;
ddrbits : integer := 16;
ahbfreq : integer := 50;
mobile : integer := 0;
confapi : integer := 0;
conf0 : integer := 0;
conf1 : integer := 0;
regoutput : integer := 0;
nosync : integer := 0;
ddr400 : integer := 1;
scantest: integer := 0;
phyiconf : integer := 0
);
port (
rst_ddr : in std_ulogic;
rst_ahb : in std_ulogic;
clk_ddr : in std_ulogic;
clk_ahb : in std_ulogic;
lock : out std_ulogic; -- DCM locked
clkddro : out std_ulogic; -- DCM locked
clkddri : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
ddr_clk : out std_logic_vector(2 downto 0);
ddr_clkb : out std_logic_vector(2 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(1 downto 0);
ddr_csb : out std_logic_vector(1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (ddrbits/8-1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (ddrbits/8-1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (13 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (ddrbits-1 downto 0) -- ddr data
);
end;
architecture rtl of ddrspa is
constant DDR_FREQ : integer := (clkmul * MHz) / clkdiv;
signal sdi : ddrctrl_in_type;
signal sdo : ddrctrl_out_type;
signal clkread : std_ulogic;
signal ilock: std_ulogic;
signal ddr_rst: std_logic;
signal ddr_rst_gen: std_logic_vector(3 downto 0);
constant ddr_syncrst: integer := 0;
begin
lock <= ilock;
ddr_rst <= (ddr_rst_gen(3) and ddr_rst_gen(2) and ddr_rst_gen(1) and rst_ahb); -- Reset signal in DDR clock domain
ddrrstproc: process(clkddri, ilock)
begin
if rising_edge(clkddri) then
ddr_rst_gen <= ddr_rst_gen(2 downto 0) & '1';
if ddr_syncrst /= 0 and rst_ahb='0' then
ddr_rst_gen <= "0000";
end if;
end if;
if ddr_syncrst=0 and ilock='0' then
ddr_rst_gen <= "0000";
end if;
end process;
ddr_phy0 : ddrphy_wrap_cbd generic map (tech => fabtech, MHz => MHz,
dbits => ddrbits, rstdelay => 0, clk_mul => clkmul,
clk_div => clkdiv, rskew => rskew, mobile => mobile,
scantest => scantest, phyiconf => phyiconf)
port map (
rst_ddr, clk_ddr, clkddro, clkddri, clkread, ilock,
ddr_clk, ddr_clkb, ddr_clk_fb_out, ddr_clk_fb,
ddr_cke, ddr_csb, ddr_web, ddr_rasb, ddr_casb,
ddr_dm, ddr_dqs, ddr_ad, ddr_ba, ddr_dq, sdi, sdo,
ahbsi.testen, ahbsi.testrst, ahbsi.scanen, ahbsi.testoen);
ddrc : ddr1spax generic map (ddrbits => ddrbits, memtech => memtech, phytech => fabtech,
hindex => hindex, haddr => haddr, hmask => hmask, ioaddr => ioaddr, iomask => iomask,
pwron => pwron, MHz => DDR_FREQ, col => col, Mbyte => Mbyte,
mobile => mobile, confapi => confapi, conf0 => conf0,
conf1 => conf1, regoutput => regoutput, nosync => nosync, ddr400 => ddr400, ahbbits => 32,
rstdel => rstdel, scantest => scantest)
port map (ddr_rst, rst_ahb, clkddri, clk_ahb, ahbsi, ahbso, sdi, sdo);
end;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:zybo_vga:1.0
-- IP Revision: 5
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_zybo_vga_0_0 IS
PORT (
clk : IN STD_LOGIC;
active : IN STD_LOGIC;
rgb : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
vga_r : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
vga_g : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
vga_b : OUT STD_LOGIC_VECTOR(4 DOWNTO 0)
);
END system_zybo_vga_0_0;
ARCHITECTURE system_zybo_vga_0_0_arch OF system_zybo_vga_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_zybo_vga_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT zybo_vga IS
PORT (
clk : IN STD_LOGIC;
active : IN STD_LOGIC;
rgb : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
vga_r : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
vga_g : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
vga_b : OUT STD_LOGIC_VECTOR(4 DOWNTO 0)
);
END COMPONENT zybo_vga;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clk CLK";
BEGIN
U0 : zybo_vga
PORT MAP (
clk => clk,
active => active,
rgb => rgb,
vga_r => vga_r,
vga_g => vga_g,
vga_b => vga_b
);
END system_zybo_vga_0_0_arch;
|
----------------------------------------------------------------------------------------------
--
-- VHDL file generated by X-HDL - Revision 3.2.53 Aug. 1, 2005
-- Tue Aug 9 07:33:50 2005
--
-- Input file : C:/Documents and Settings/BryantI/My Documents/tmp/can_top.v
-- Design name : can_acf
-- Author :
-- Company : Actel
--
-- Description :
--
--
----------------------------------------------------------------------------------------------
--
--////////////////////////////////////////////////////////////////////
--// ////
--// can_acf.v ////
--// ////
--// ////
--// This file is part of the CAN Protocol Controller ////
--// http://www.opencores.org/projects/can/ ////
--// ////
--// ////
--// Author(s): ////
--// Igor Mohor ////
--// [email protected] ////
--// ////
--// ////
--// All additional information is available in the README.txt ////
--// file. ////
--// ////
--////////////////////////////////////////////////////////////////////
--// ////
--// Copyright (C) 2002, 2003, 2004 Authors ////
--// ////
--// This source file may be used and distributed without ////
--// restriction provided that this copyright statement is not ////
--// removed from the file and that any derivative work contains ////
--// the original copyright notice and the associated disclaimer. ////
--// ////
--// This source file is free software; you can redistribute it ////
--// and/or modify it under the terms of the GNU Lesser General ////
--// Public License as published by the Free Software Foundation; ////
--// either version 2.1 of the License, or (at your option) any ////
--// later version. ////
--// ////
--// This source is distributed in the hope that it will be ////
--// useful, but WITHOUT ANY WARRANTY; without even the implied ////
--// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
--// PURPOSE. See the GNU Lesser General Public License for more ////
--// details. ////
--// ////
--// You should have received a copy of the GNU Lesser General ////
--// Public License along with this source; if not, download it ////
--// from http://www.opencores.org/lgpl.shtml ////
--// ////
--// The CAN protocol is developed by Robert Bosch GmbH and ////
--// protected by patents. Anybody who wants to implement this ////
--// CAN IP core on silicon has to obtain a CAN protocol license ////
--// from Bosch. ////
--// ////
--////////////////////////////////////////////////////////////////////
--
-- CVS Revision History
--
-- $Log: can_acf.v,v $
-- Revision 1.10 2005/04/08 13:03:07 igorm
-- In "Extended mode" when dual filter was used and standard frame received,
-- upper nibble of the data was not filtered ok.
--
-- Revision 1.9 2004/05/31 14:46:11 igorm
-- Bit acceptance_filter_mode was inverted.
--
-- Revision 1.8 2004/02/08 14:16:44 mohor
-- Header changed.
--
-- Revision 1.7 2003/07/16 13:41:34 mohor
-- Fixed according to the linter.
--
-- Revision 1.6 2003/02/10 16:02:11 mohor
-- CAN is working according to the specification. WB interface and more
-- registers (status, IRQ, ...) needs to be added.
--
-- Revision 1.5 2003/02/09 18:40:29 mohor
-- Overload fixed. Hard synchronization also enabled at the last bit of
-- interframe.
--
-- Revision 1.4 2003/02/09 02:24:33 mohor
-- Bosch license warning added. Error counters finished. Overload frames
-- still need to be fixed.
--
-- Revision 1.3 2003/01/31 01:13:37 mohor
-- backup.
--
-- Revision 1.2 2003/01/14 12:19:35 mohor
-- rx_fifo is now working.
--
-- Revision 1.1 2003/01/08 02:13:15 mohor
-- Acceptance filter added.
--
--
--
--
-- synopsys translate_off
--`include "can_defines.v"
-- synopsys translate_on
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
library grlib;
use grlib.stdlib.all;
ENTITY can_acf IS
PORT (
clk : IN std_logic;
rst : IN std_logic;
id : IN std_logic_vector(28 DOWNTO 0);
reset_mode : IN std_logic;
acceptance_filter_mode : IN std_logic;
extended_mode : IN std_logic;
acceptance_code_0 : IN std_logic_vector(7 DOWNTO 0);
acceptance_code_1 : IN std_logic_vector(7 DOWNTO 0);
acceptance_code_2 : IN std_logic_vector(7 DOWNTO 0);
acceptance_code_3 : IN std_logic_vector(7 DOWNTO 0);
acceptance_mask_0 : IN std_logic_vector(7 DOWNTO 0);
acceptance_mask_1 : IN std_logic_vector(7 DOWNTO 0);
acceptance_mask_2 : IN std_logic_vector(7 DOWNTO 0);
acceptance_mask_3 : IN std_logic_vector(7 DOWNTO 0);
go_rx_crc_lim : IN std_logic;
go_rx_inter : IN std_logic;
go_error_frame : IN std_logic;
data0 : IN std_logic_vector(7 DOWNTO 0);
data1 : IN std_logic_vector(7 DOWNTO 0);
rtr1 : IN std_logic;
rtr2 : IN std_logic;
ide : IN std_logic;
no_byte0 : IN std_logic;
no_byte1 : IN std_logic;
id_ok : OUT std_logic);
END ENTITY can_acf;
ARCHITECTURE RTL OF can_acf IS
SIGNAL match : std_logic;
SIGNAL match_sf_std : std_logic;
SIGNAL match_sf_ext : std_logic;
SIGNAL match_df_std : std_logic;
SIGNAL match_df_ext : std_logic;
SIGNAL id_ok_xhdl1 : std_logic;
BEGIN
id_ok <= id_ok_xhdl1;
-- Working in basic mode. ID match for standard format (11-bit ID).
match <= (((((((CONV_STD_LOGIC(id(3) = acceptance_code_0(0)) OR acceptance_mask_0(0)) AND (CONV_STD_LOGIC(id(4) = acceptance_code_0(1)) OR acceptance_mask_0(1))) AND (CONV_STD_LOGIC(id(5) = acceptance_code_0(2)) OR acceptance_mask_0(2))) AND (CONV_STD_LOGIC(id(6) = acceptance_code_0(3)) OR acceptance_mask_0(3))) AND (CONV_STD_LOGIC(id(7) = acceptance_code_0(4)) OR acceptance_mask_0(4))) AND (CONV_STD_LOGIC(id(8) = acceptance_code_0(5)) OR acceptance_mask_0(5))) AND (CONV_STD_LOGIC(id(9) = acceptance_code_0(6)) OR acceptance_mask_0(6))) AND (CONV_STD_LOGIC(id(10) = acceptance_code_0(7)) OR acceptance_mask_0(7)) ;
-- Working in extended mode. ID match for standard format (11-bit ID). Using single filter.
match_sf_std <= (((((((((((((((((((((((((((CONV_STD_LOGIC(id(3) = acceptance_code_0(0)) OR acceptance_mask_0(0)) AND (CONV_STD_LOGIC(id(4) = acceptance_code_0(1))
OR acceptance_mask_0(1))) AND (CONV_STD_LOGIC(id(5) = acceptance_code_0(2)) OR acceptance_mask_0(2))) AND (CONV_STD_LOGIC(id(6) = acceptance_code_0(3))
OR acceptance_mask_0(3))) AND (CONV_STD_LOGIC(id(7) = acceptance_code_0(4)) OR acceptance_mask_0(4))) AND (CONV_STD_LOGIC(id(8) = acceptance_code_0(5))
OR acceptance_mask_0(5))) AND (CONV_STD_LOGIC(id(9) = acceptance_code_0(6)) OR acceptance_mask_0(6))) AND (CONV_STD_LOGIC(id(10) = acceptance_code_0(7))
OR acceptance_mask_0(7))) AND (CONV_STD_LOGIC(rtr1 = acceptance_code_1(4)) OR acceptance_mask_1(4))) AND (CONV_STD_LOGIC(id(0) = acceptance_code_1(5))
OR acceptance_mask_1(5))) AND (CONV_STD_LOGIC(id(1) = acceptance_code_1(6)) OR acceptance_mask_1(6))) AND (CONV_STD_LOGIC(id(2) = acceptance_code_1(7))
OR acceptance_mask_1(7))) AND (CONV_STD_LOGIC(data0(0) = acceptance_code_2(0)) OR acceptance_mask_2(0) OR no_byte0)) AND (CONV_STD_LOGIC(data0(1) = acceptance_code_2(1))
OR acceptance_mask_2(1) OR no_byte0)) AND (CONV_STD_LOGIC(data0(2) = acceptance_code_2(2)) OR acceptance_mask_2(2)
OR no_byte0)) AND (CONV_STD_LOGIC(data0(3) = acceptance_code_2(3)) OR acceptance_mask_2(3) OR no_byte0)) AND (CONV_STD_LOGIC(data0(4) = acceptance_code_2(4))
OR acceptance_mask_2(4) OR no_byte0)) AND (CONV_STD_LOGIC(data0(5) = acceptance_code_2(5)) OR acceptance_mask_2(5) OR no_byte0)) AND (CONV_STD_LOGIC(data0(6) = acceptance_code_2(6))
OR acceptance_mask_2(6) OR no_byte0)) AND (CONV_STD_LOGIC(data0(7) = acceptance_code_2(7)) OR acceptance_mask_2(7) OR no_byte0)) AND (CONV_STD_LOGIC(data1(0) = acceptance_code_3(0))
OR acceptance_mask_3(0) OR no_byte1)) AND (CONV_STD_LOGIC(data1(1) = acceptance_code_3(1)) OR acceptance_mask_3(1) OR no_byte1)) AND (CONV_STD_LOGIC(data1(2) = acceptance_code_3(2))
OR acceptance_mask_3(2) OR no_byte1)) AND (CONV_STD_LOGIC(data1(3) = acceptance_code_3(3)) OR acceptance_mask_3(3) OR no_byte1)) AND (CONV_STD_LOGIC(data1(4) = acceptance_code_3(4))
OR acceptance_mask_3(4) OR no_byte1)) AND (CONV_STD_LOGIC(data1(5) = acceptance_code_3(5)) OR acceptance_mask_3(5) OR no_byte1)) AND (CONV_STD_LOGIC(data1(6) = acceptance_code_3(6))
OR acceptance_mask_3(6) OR no_byte1)) AND (CONV_STD_LOGIC(data1(7) = acceptance_code_3(7)) OR acceptance_mask_3(7) OR no_byte1) ;
-- Working in extended mode. ID match for extended format (29-bit ID). Using single filter.
match_sf_ext <= (((((((((((((((((((((((((((((CONV_STD_LOGIC(id(21) = acceptance_code_0(0)) OR acceptance_mask_0(0)) AND (CONV_STD_LOGIC(id(22) = acceptance_code_0(1))
OR acceptance_mask_0(1))) AND (CONV_STD_LOGIC(id(23) = acceptance_code_0(2)) OR acceptance_mask_0(2))) AND (CONV_STD_LOGIC(id(24) = acceptance_code_0(3))
OR acceptance_mask_0(3))) AND (CONV_STD_LOGIC(id(25) = acceptance_code_0(4)) OR acceptance_mask_0(4))) AND (CONV_STD_LOGIC(id(26) = acceptance_code_0(5))
OR acceptance_mask_0(5))) AND (CONV_STD_LOGIC(id(27) = acceptance_code_0(6)) OR acceptance_mask_0(6))) AND (CONV_STD_LOGIC(id(28) = acceptance_code_0(7))
OR acceptance_mask_0(7))) AND (CONV_STD_LOGIC(id(13) = acceptance_code_1(0)) OR acceptance_mask_1(0))) AND (CONV_STD_LOGIC(id(14) = acceptance_code_1(1))
OR acceptance_mask_1(1))) AND (CONV_STD_LOGIC(id(15) = acceptance_code_1(2)) OR acceptance_mask_1(2))) AND (CONV_STD_LOGIC(id(16) = acceptance_code_1(3))
OR acceptance_mask_1(3))) AND (CONV_STD_LOGIC(id(17) = acceptance_code_1(4)) OR acceptance_mask_1(4))) AND (CONV_STD_LOGIC(id(18) = acceptance_code_1(5))
OR acceptance_mask_1(5))) AND (CONV_STD_LOGIC(id(19) = acceptance_code_1(6)) OR acceptance_mask_1(6))) AND (CONV_STD_LOGIC(id(20) = acceptance_code_1(7))
OR acceptance_mask_1(7))) AND (CONV_STD_LOGIC(id(5) = acceptance_code_2(0)) OR acceptance_mask_2(0))) AND (CONV_STD_LOGIC(id(6) = acceptance_code_2(1))
OR acceptance_mask_2(1))) AND (CONV_STD_LOGIC(id(7) = acceptance_code_2(2)) OR acceptance_mask_2(2))) AND (CONV_STD_LOGIC(id(8) = acceptance_code_2(3))
OR acceptance_mask_2(3))) AND (CONV_STD_LOGIC(id(9) = acceptance_code_2(4)) OR acceptance_mask_2(4))) AND (CONV_STD_LOGIC(id(10) = acceptance_code_2(5))
OR acceptance_mask_2(5))) AND (CONV_STD_LOGIC(id(11) = acceptance_code_2(6)) OR acceptance_mask_2(6))) AND (CONV_STD_LOGIC(id(12) = acceptance_code_2(7))
OR acceptance_mask_2(7))) AND (CONV_STD_LOGIC(rtr2 = acceptance_code_3(2)) OR acceptance_mask_3(2))) AND (CONV_STD_LOGIC(id(0) = acceptance_code_3(3))
OR acceptance_mask_3(3))) AND (CONV_STD_LOGIC(id(1) = acceptance_code_3(4)) OR acceptance_mask_3(4))) AND (CONV_STD_LOGIC(id(2) = acceptance_code_3(5))
OR acceptance_mask_3(5))) AND (CONV_STD_LOGIC(id(3) = acceptance_code_3(6)) OR acceptance_mask_3(6))) AND (CONV_STD_LOGIC(id(4) = acceptance_code_3(7))
OR acceptance_mask_3(7)) ;
-- Working in extended mode. ID match for standard format (11-bit ID). Using double filter.
match_df_std <= ((((((((((((((((((((CONV_STD_LOGIC(id(3) = acceptance_code_0(0)) OR acceptance_mask_0(0)) AND (CONV_STD_LOGIC(id(4) = acceptance_code_0(1))
OR acceptance_mask_0(1))) AND (CONV_STD_LOGIC(id(5) = acceptance_code_0(2)) OR acceptance_mask_0(2))) AND (CONV_STD_LOGIC(id(6) = acceptance_code_0(3))
OR acceptance_mask_0(3))) AND (CONV_STD_LOGIC(id(7) = acceptance_code_0(4)) OR acceptance_mask_0(4))) AND (CONV_STD_LOGIC(id(8) = acceptance_code_0(5))
OR acceptance_mask_0(5))) AND (CONV_STD_LOGIC(id(9) = acceptance_code_0(6)) OR acceptance_mask_0(6))) AND (CONV_STD_LOGIC(id(10) = acceptance_code_0(7))
OR acceptance_mask_0(7))) AND (CONV_STD_LOGIC(rtr1 = acceptance_code_1(4)) OR acceptance_mask_1(4))) AND (CONV_STD_LOGIC(id(0) = acceptance_code_1(5))
OR acceptance_mask_1(5))) AND (CONV_STD_LOGIC(id(1) = acceptance_code_1(6)) OR acceptance_mask_1(6))) AND (CONV_STD_LOGIC(id(2) = acceptance_code_1(7))
OR acceptance_mask_1(7))) AND (CONV_STD_LOGIC(data0(0) = acceptance_code_3(0)) OR acceptance_mask_3(0)
OR no_byte0)) AND (CONV_STD_LOGIC(data0(1) = acceptance_code_3(1)) OR acceptance_mask_3(1) OR no_byte0)) AND (CONV_STD_LOGIC(data0(2) = acceptance_code_3(2))
OR acceptance_mask_3(2) OR no_byte0)) AND (CONV_STD_LOGIC(data0(3) = acceptance_code_3(3)) OR acceptance_mask_3(3)
OR no_byte0)) AND (CONV_STD_LOGIC(data0(4) = acceptance_code_1(0)) OR acceptance_mask_1(0) OR no_byte0)) AND (CONV_STD_LOGIC(data0(5) = acceptance_code_1(1))
OR acceptance_mask_1(1) OR no_byte0)) AND (CONV_STD_LOGIC(data0(6) = acceptance_code_1(2))
OR acceptance_mask_1(2) OR no_byte0)) AND (CONV_STD_LOGIC(data0(7) = acceptance_code_1(3)) OR acceptance_mask_1(3) OR no_byte0))
OR ((((((((((((CONV_STD_LOGIC(id(3) = acceptance_code_2(0)) OR acceptance_mask_2(0)) AND (CONV_STD_LOGIC(id(4) = acceptance_code_2(1))
OR acceptance_mask_2(1))) AND (CONV_STD_LOGIC(id(5) = acceptance_code_2(2)) OR acceptance_mask_2(2))) AND (CONV_STD_LOGIC(id(6) = acceptance_code_2(3))
OR acceptance_mask_2(3))) AND (CONV_STD_LOGIC(id(7) = acceptance_code_2(4)) OR acceptance_mask_2(4))) AND (CONV_STD_LOGIC(id(8) = acceptance_code_2(5))
OR acceptance_mask_2(5))) AND (CONV_STD_LOGIC(id(9) = acceptance_code_2(6)) OR acceptance_mask_2(6))) AND (CONV_STD_LOGIC(id(10) = acceptance_code_2(7))
OR acceptance_mask_2(7))) AND (CONV_STD_LOGIC(rtr1 = acceptance_code_3(4)) OR acceptance_mask_3(4))) AND (CONV_STD_LOGIC(id(0) = acceptance_code_3(5))
OR acceptance_mask_3(5))) AND (CONV_STD_LOGIC(id(1) = acceptance_code_3(6)) OR acceptance_mask_3(6))) AND (CONV_STD_LOGIC(id(2) = acceptance_code_3(7))
OR acceptance_mask_3(7))) ;
-- Working in extended mode. ID match for extended format (29-bit ID). Using double filter.
match_df_ext <= ((((((((((((((((CONV_STD_LOGIC(id(21) = acceptance_code_0(0)) OR acceptance_mask_0(0)) AND (CONV_STD_LOGIC(id(22) = acceptance_code_0(1))
OR acceptance_mask_0(1))) AND (CONV_STD_LOGIC(id(23) = acceptance_code_0(2)) OR acceptance_mask_0(2))) AND (CONV_STD_LOGIC(id(24) = acceptance_code_0(3))
OR acceptance_mask_0(3))) AND (CONV_STD_LOGIC(id(25) = acceptance_code_0(4)) OR acceptance_mask_0(4))) AND (CONV_STD_LOGIC(id(26) = acceptance_code_0(5))
OR acceptance_mask_0(5))) AND (CONV_STD_LOGIC(id(27) = acceptance_code_0(6)) OR acceptance_mask_0(6))) AND (CONV_STD_LOGIC(id(28) = acceptance_code_0(7))
OR acceptance_mask_0(7))) AND (CONV_STD_LOGIC(id(13) = acceptance_code_1(0)) OR acceptance_mask_1(0))) AND (CONV_STD_LOGIC(id(14) = acceptance_code_1(1))
OR acceptance_mask_1(1))) AND (CONV_STD_LOGIC(id(15) = acceptance_code_1(2)) OR acceptance_mask_1(2))) AND (CONV_STD_LOGIC(id(16) = acceptance_code_1(3))
OR acceptance_mask_1(3))) AND (CONV_STD_LOGIC(id(17) = acceptance_code_1(4)) OR acceptance_mask_1(4))) AND (CONV_STD_LOGIC(id(18) = acceptance_code_1(5))
OR acceptance_mask_1(5))) AND (CONV_STD_LOGIC(id(19) = acceptance_code_1(6)) OR acceptance_mask_1(6))) AND (CONV_STD_LOGIC(id(20) = acceptance_code_1(7))
OR acceptance_mask_1(7))) OR ((((((((((((((((CONV_STD_LOGIC(id(21) = acceptance_code_2(0)) OR acceptance_mask_2(0)) AND (CONV_STD_LOGIC(id(22) = acceptance_code_2(1))
OR acceptance_mask_2(1))) AND (CONV_STD_LOGIC(id(23) = acceptance_code_2(2)) OR acceptance_mask_2(2))) AND (CONV_STD_LOGIC(id(24) = acceptance_code_2(3))
OR acceptance_mask_2(3))) AND (CONV_STD_LOGIC(id(25) = acceptance_code_2(4)) OR acceptance_mask_2(4))) AND (CONV_STD_LOGIC(id(26) = acceptance_code_2(5))
OR acceptance_mask_2(5))) AND (CONV_STD_LOGIC(id(27) = acceptance_code_2(6)) OR acceptance_mask_2(6))) AND (CONV_STD_LOGIC(id(28) = acceptance_code_2(7))
OR acceptance_mask_2(7))) AND (CONV_STD_LOGIC(id(13) = acceptance_code_3(0)) OR acceptance_mask_3(0))) AND (CONV_STD_LOGIC(id(14) = acceptance_code_3(1))
OR acceptance_mask_3(1))) AND (CONV_STD_LOGIC(id(15) = acceptance_code_3(2)) OR acceptance_mask_3(2))) AND (CONV_STD_LOGIC(id(16) = acceptance_code_3(3))
OR acceptance_mask_3(3))) AND (CONV_STD_LOGIC(id(17) = acceptance_code_3(4)) OR acceptance_mask_3(4))) AND (CONV_STD_LOGIC(id(18) = acceptance_code_3(5))
OR acceptance_mask_3(5))) AND (CONV_STD_LOGIC(id(19) = acceptance_code_3(6)) OR acceptance_mask_3(6))) AND (CONV_STD_LOGIC(id(20) = acceptance_code_3(7))
OR acceptance_mask_3(7))) ;
-- ID ok signal generation
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
id_ok_xhdl1 <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (go_rx_crc_lim = '1') THEN
-- sample_point is already included in go_rx_crc_lim
IF (extended_mode = '1') THEN
IF (NOT acceptance_filter_mode = '1') THEN
-- dual filter
IF (ide = '1') THEN
-- extended frame message
id_ok_xhdl1 <= match_df_ext ;
ELSE
-- standard frame message
id_ok_xhdl1 <= match_df_std ;
END IF;
ELSE
-- single filter
IF (ide = '1') THEN
-- extended frame message
id_ok_xhdl1 <= match_sf_ext ;
ELSE
-- standard frame message
id_ok_xhdl1 <= match_sf_std ;
END IF;
END IF;
ELSE
id_ok_xhdl1 <= match ;
END IF;
ELSE
IF ((reset_mode OR go_rx_inter OR go_error_frame) = '1') THEN
-- sample_point is already included in go_rx_inter
id_ok_xhdl1 <= '0' ;
END IF;
END IF;
END IF;
END PROCESS;
END ARCHITECTURE RTL;
----------------------------------------------------------------------------------------------
--
-- VHDL file generated by X-HDL - Revision 3.2.53 Aug. 1, 2005
-- Tue Aug 9 07:33:51 2005
--
-- Input file : C:/Documents and Settings/BryantI/My Documents/tmp/can_top.v
-- Design name : can_btl
-- Author :
-- Company : Actel
--
-- Description :
--
--
----------------------------------------------------------------------------------------------
--
--////////////////////////////////////////////////////////////////////
--// ////
--// can_btl.v ////
--// ////
--// ////
--// This file is part of the CAN Protocol Controller ////
--// http://www.opencores.org/projects/can/ ////
--// ////
--// ////
--// Author(s): ////
--// Igor Mohor ////
--// [email protected] ////
--// ////
--// ////
--// All additional information is available in the README.txt ////
--// file. ////
--// ////
--////////////////////////////////////////////////////////////////////
--// ////
--// Copyright (C) 2002, 2003, 2004 Authors ////
--// ////
--// This source file may be used and distributed without ////
--// restriction provided that this copyright statement is not ////
--// removed from the file and that any derivative work contains ////
--// the original copyright notice and the associated disclaimer. ////
--// ////
--// This source file is free software; you can redistribute it ////
--// and/or modify it under the terms of the GNU Lesser General ////
--// Public License as published by the Free Software Foundation; ////
--// either version 2.1 of the License, or (at your option) any ////
--// later version. ////
--// ////
--// This source is distributed in the hope that it will be ////
--// useful, but WITHOUT ANY WARRANTY; without even the implied ////
--// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
--// PURPOSE. See the GNU Lesser General Public License for more ////
--// details. ////
--// ////
--// You should have received a copy of the GNU Lesser General ////
--// Public License along with this source; if not, download it ////
--// from http://www.opencores.org/lgpl.shtml ////
--// ////
--// The CAN protocol is developed by Robert Bosch GmbH and ////
--// protected by patents. Anybody who wants to implement this ////
--// CAN IP core on silicon has to obtain a CAN protocol license ////
--// from Bosch. ////
--// ////
--////////////////////////////////////////////////////////////////////
--
-- CVS Revision History
--
-- $Log: can_btl.v,v $
-- Revision 1.30 2004/10/27 18:51:37 igorm
-- Fixed synchronization problem in real hardware when 0xf is used for TSEG1.
--
-- Revision 1.29 2004/05/12 15:58:41 igorm
-- Core improved to pass all tests with the Bosch VHDL Reference system.
--
-- Revision 1.28 2004/02/08 14:25:26 mohor
-- Header changed.
--
-- Revision 1.27 2003/09/30 00:55:13 mohor
-- Error counters fixed to be compatible with Bosch VHDL reference model.
-- Small synchronization changes.
--
-- Revision 1.26 2003/09/25 18:55:49 mohor
-- Synchronization changed, error counters fixed.
--
-- Revision 1.25 2003/07/16 13:40:35 mohor
-- Fixed according to the linter.
--
-- Revision 1.24 2003/07/10 15:32:28 mohor
-- Unused signal removed.
--
-- Revision 1.23 2003/07/10 01:59:04 tadejm
-- Synchronization fixed. In some strange cases it didn't work according to
-- the VHDL reference model.
--
-- Revision 1.22 2003/07/07 11:21:37 mohor
-- Little fixes (to fix warnings).
--
-- Revision 1.21 2003/07/03 09:32:20 mohor
-- Synchronization changed.
--
-- Revision 1.20 2003/06/20 14:51:11 mohor
-- Previous change removed. When resynchronization occurs we go to seg1
-- stage. sync stage does not cause another start of seg1 stage.
--
-- Revision 1.19 2003/06/20 14:28:20 mohor
-- When hard_sync or resync occure we need to go to seg1 segment. Going to
-- sync segment is in that case blocked.
--
-- Revision 1.18 2003/06/17 15:53:33 mohor
-- clk_cnt reduced from [8:0] to [6:0].
--
-- Revision 1.17 2003/06/17 14:32:17 mohor
-- Removed few signals.
--
-- Revision 1.16 2003/06/16 13:57:58 mohor
-- tx_point generated one clk earlier. rx_i registered. Data corrected when
-- using extended mode.
--
-- Revision 1.15 2003/06/13 15:02:24 mohor
-- Synchronization is also needed when transmitting a message.
--
-- Revision 1.14 2003/06/13 14:55:11 mohor
-- Counters width changed.
--
-- Revision 1.13 2003/06/11 14:21:35 mohor
-- When switching to tx, sync stage is overjumped.
--
-- Revision 1.12 2003/02/14 20:17:01 mohor
-- Several registers added. Not finished, yet.
--
-- Revision 1.11 2003/02/09 18:40:29 mohor
-- Overload fixed. Hard synchronization also enabled at the last bit of
-- interframe.
--
-- Revision 1.10 2003/02/09 02:24:33 mohor
-- Bosch license warning added. Error counters finished. Overload frames
-- still need to be fixed.
--
-- Revision 1.9 2003/01/31 01:13:38 mohor
-- backup.
--
-- Revision 1.8 2003/01/10 17:51:34 mohor
-- Temporary version (backup).
--
-- Revision 1.7 2003/01/08 02:10:53 mohor
-- Acceptance filter added.
--
-- Revision 1.6 2002/12/28 04:13:23 mohor
-- Backup version.
--
-- Revision 1.5 2002/12/27 00:12:52 mohor
-- Header changed, testbench improved to send a frame (crc still missing).
--
-- Revision 1.4 2002/12/26 01:33:05 mohor
-- Tripple sampling supported.
--
-- Revision 1.3 2002/12/25 23:44:16 mohor
-- Commented lines removed.
--
-- Revision 1.2 2002/12/25 14:17:00 mohor
-- Synchronization working.
--
-- Revision 1.1.1.1 2002/12/20 16:39:21 mohor
-- Initial
--
--
--
-- synopsys translate_off
--`include "can_defines.v"
-- synopsys translate_on
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
library grlib;
use grlib.stdlib.all;
ENTITY can_btl IS
PORT (
clk : IN std_logic;
rst : IN std_logic;
rx : IN std_logic;
tx : IN std_logic;
-- Bus Timing 0 register
baud_r_presc : IN std_logic_vector(5 DOWNTO 0);
sync_jump_width : IN std_logic_vector(1 DOWNTO 0);
-- Bus Timing 1 register
time_segment1 : IN std_logic_vector(3 DOWNTO 0);
time_segment2 : IN std_logic_vector(2 DOWNTO 0);
triple_sampling : IN std_logic;
-- Output signals from this module
sample_point : OUT std_logic;
sampled_bit : OUT std_logic;
sampled_bit_q : OUT std_logic;
tx_point : OUT std_logic;
hard_sync : OUT std_logic;
-- Output from can_bsp module
rx_idle : IN std_logic;
rx_inter : IN std_logic;
transmitting : IN std_logic;
transmitter : IN std_logic;
go_rx_inter : IN std_logic;
tx_next : IN std_logic;
go_overload_frame : IN std_logic;
go_error_frame : IN std_logic;
go_tx : IN std_logic;
send_ack : IN std_logic;
node_error_passive : IN std_logic);
END ENTITY can_btl;
ARCHITECTURE RTL OF can_btl IS
TYPE xhdl_46 IS ARRAY (0 TO 7) OF std_logic_vector(7 DOWNTO 0);
SIGNAL clk_cnt : std_logic_vector(6 DOWNTO 0);
SIGNAL clk_en : std_logic;
SIGNAL clk_en_q : std_logic;
SIGNAL sync_blocked : std_logic;
SIGNAL hard_sync_blocked : std_logic;
SIGNAL quant_cnt : std_logic_vector(4 DOWNTO 0);
SIGNAL delay : std_logic_vector(3 DOWNTO 0);
SIGNAL sync : std_logic;
SIGNAL seg1 : std_logic;
SIGNAL seg2 : std_logic;
SIGNAL resync_latched : std_logic;
SIGNAL sample : std_logic_vector(1 DOWNTO 0);
SIGNAL tx_next_sp : std_logic;
SIGNAL go_sync : std_logic;
SIGNAL go_seg1 : std_logic;
SIGNAL go_seg2 : std_logic;
SIGNAL preset_cnt : std_logic_vector(7 DOWNTO 0);
SIGNAL sync_window : std_logic;
SIGNAL resync : std_logic;
-- when transmitting 0 with positive error delay is set to 0
SIGNAL temp_xhdl6 : std_logic_vector(4 DOWNTO 0);
SIGNAL sample_point_xhdl1 : std_logic;
SIGNAL sampled_bit_xhdl2 : std_logic;
SIGNAL sampled_bit_q_xhdl3 : std_logic;
SIGNAL tx_point_xhdl4 : std_logic;
SIGNAL hard_sync_xhdl5 : std_logic;
signal time_segment1_ext, delay_ext, add_ext: std_logic_vector(4 DOWNTO 0); --##
BEGIN
sample_point <= sample_point_xhdl1;
sampled_bit <= sampled_bit_xhdl2;
sampled_bit_q <= sampled_bit_q_xhdl3;
tx_point <= tx_point_xhdl4;
hard_sync <= hard_sync_xhdl5;
preset_cnt <= (('0' & baud_r_presc) + 1) & "0" ;
hard_sync_xhdl5 <= (((rx_idle OR rx_inter) AND (NOT rx)) AND sampled_bit_xhdl2) AND (NOT hard_sync_blocked) ;
resync <= ((((NOT rx_idle) AND (NOT rx_inter)) AND (NOT rx)) AND sampled_bit_xhdl2) AND (NOT sync_blocked) ;
-- Generating general enable signal that defines baud rate.
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
clk_cnt <= "0000000";
ELSIF (clk'EVENT AND clk = '1') THEN
IF (('0' & clk_cnt) >= (preset_cnt - "00000001")) THEN
clk_cnt <= "0000000" ;
ELSE
clk_cnt <= clk_cnt + "0000001" ;
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
clk_en <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (('0' & clk_cnt) = (preset_cnt - "00000001")) THEN
clk_en <= '1' ;
ELSE
clk_en <= '0' ;
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
clk_en_q <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
clk_en_q <= clk_en ;
END IF;
END PROCESS;
-- Changing states
go_sync <= (((clk_en_q AND seg2) AND CONV_STD_LOGIC(quant_cnt(2 DOWNTO 0) = time_segment2)) AND (NOT hard_sync_xhdl5)) AND (NOT resync) ;
go_seg1 <= clk_en_q AND (sync OR hard_sync_xhdl5 OR ((resync AND seg2) AND sync_window) OR (resync_latched AND sync_window)) ;
--## go_seg2 <= clk_en_q AND ((seg1 AND (NOT hard_sync_xhdl5)) AND CONV_STD_LOGIC(quant_cnt = ( '0' & (time_segment1 + delay)))) ;
go_seg2 <= clk_en_q AND ((seg1 AND (NOT hard_sync_xhdl5)) AND CONV_STD_LOGIC(quant_cnt = add_ext)) ;--##
time_segment1_ext <= '0' & time_segment1; --## fix comparison for max values
delay_ext <= '0' & delay; --##
add_ext <= time_segment1_ext + delay_ext; --##
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
tx_point_xhdl4 <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
tx_point_xhdl4 <= (NOT tx_point_xhdl4 AND seg2) AND ((clk_en AND CONV_STD_LOGIC(quant_cnt(2 DOWNTO 0) = time_segment2)) OR ((clk_en OR clk_en_q) AND (resync OR hard_sync_xhdl5))) ; -- When transmitter we should transmit as soon as possible.
END IF;
END PROCESS;
-- When early edge is detected outside of the SJW field, synchronization request is latched and performed when
-- When early edge is detected outside of the SJW field, synchronization request is latched and performed when
-- SJW is reached
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
resync_latched <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (((resync AND seg2) AND (NOT sync_window)) = '1') THEN
resync_latched <= '1' ;
ELSE
IF (go_seg1 = '1') THEN
resync_latched <= '0';
END IF;
END IF;
END IF;
END PROCESS;
-- Synchronization stage/segment
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
sync <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (clk_en_q = '1') THEN
sync <= go_sync ;
END IF;
END IF;
END PROCESS;
-- Seg1 stage/segment (together with propagation segment which is 1 quant long)
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
seg1 <= '1';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (go_seg1 = '1') THEN
seg1 <= '1' ;
ELSE
IF (go_seg2 = '1') THEN
seg1 <= '0' ;
END IF;
END IF;
END IF;
END PROCESS;
-- Seg2 stage/segment
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
seg2 <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (go_seg2 = '1') THEN
seg2 <= '1' ;
ELSE
IF ((go_sync OR go_seg1) = '1') THEN
seg2 <= '0' ;
END IF;
END IF;
END IF;
END PROCESS;
-- Quant counter
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
quant_cnt <= "00000";
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((go_sync OR go_seg1 OR go_seg2) = '1') THEN
quant_cnt <= "00000" ;
ELSE
IF (clk_en_q = '1') THEN
quant_cnt <= quant_cnt + "00001" ;
END IF;
END IF;
END IF;
END PROCESS;
--## temp_xhdl6 <= ("0" & ("00" & sync_jump_width + "0001")) WHEN (quant_cnt > "000" & sync_jump_width) ELSE (quant_cnt + "00001");
temp_xhdl6 <= ("0" & (("00" & sync_jump_width) + "0001")) WHEN (quant_cnt > ("000" & sync_jump_width)) ELSE (quant_cnt + "00001");
-- When late edge is detected (in seg1 stage), stage seg1 is prolonged.
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
delay <= "0000";
ELSIF (clk'EVENT AND clk = '1') THEN
IF (((resync AND seg1) AND (NOT transmitting OR (transmitting AND (tx_next_sp OR (tx AND (NOT rx)))))) = '1') THEN
delay <= temp_xhdl6(3 DOWNTO 0) ;
ELSE
IF ((go_sync OR go_seg1) = '1') THEN
delay <= "0000" ;
END IF;
END IF;
END IF;
END PROCESS;
-- If early edge appears within this window (in seg2 stage), phase error is fully compensated
--## sync_window <= CONV_STD_LOGIC((time_segment2 - quant_cnt(2 DOWNTO 0)) < ('0' & (sync_jump_width + "01"))) ;
sync_window <= '1' when (time_segment2 - quant_cnt(2 DOWNTO 0)) < (('0' & sync_jump_width) + "01") else '0';
-- Sampling data (memorizing two samples all the time).
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
sample <= "11";
ELSIF (clk'EVENT AND clk = '1') THEN
IF (clk_en_q = '1') THEN
sample <= sample(0) & rx;
END IF;
END IF;
END PROCESS;
-- When enabled, tripple sampling is done here.
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
sampled_bit_xhdl2 <= '1';
sampled_bit_q_xhdl3 <= '1';
sample_point_xhdl1 <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (go_error_frame = '1') THEN
sampled_bit_q_xhdl3 <= sampled_bit_xhdl2 ;
sample_point_xhdl1 <= '0' ;
ELSE
IF ((clk_en_q AND (NOT hard_sync_xhdl5)) = '1') THEN
--## IF ((seg1 AND CONV_STD_LOGIC(quant_cnt = ('0' & (time_segment1 + delay)))) = '1') then
IF ((seg1 AND CONV_STD_LOGIC(quant_cnt = add_ext )) = '1') then --##
sample_point_xhdl1 <= '1' ;
sampled_bit_q_xhdl3 <= sampled_bit_xhdl2 ;
IF (triple_sampling = '1') THEN
sampled_bit_xhdl2 <= (sample(0) AND sample(1)) OR (sample(0) AND rx) OR (sample(1) AND rx) ;
ELSE
sampled_bit_xhdl2 <= rx ;
END IF;
-- kc fix
ELSE
sample_point_xhdl1 <= '0' ;
--
END IF;
ELSE
sample_point_xhdl1 <= '0' ;
END IF;
END IF;
END IF;
END PROCESS;
-- tx_next_sp shows next value that will be driven on the TX. When driving 1 and receiving 0 we
-- need to synchronize (even when we are a transmitter)
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
tx_next_sp <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((go_overload_frame OR (go_error_frame AND (NOT node_error_passive)) OR go_tx OR send_ack) = '1') THEN
tx_next_sp <= '0' ;
ELSE
IF ((go_error_frame AND node_error_passive) = '1') THEN
tx_next_sp <= '1' ;
ELSE
IF (sample_point_xhdl1 = '1') THEN
tx_next_sp <= tx_next ;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
-- Blocking synchronization (can occur only once in a bit time)
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
sync_blocked <= '1' ;
ELSIF (clk'EVENT AND clk = '1') THEN
IF (clk_en_q = '1') THEN
IF (resync = '1') THEN
sync_blocked <= '1' ;
ELSE
IF (go_seg2 = '1') THEN
sync_blocked <= '0' ;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
-- Blocking hard synchronization when occurs once or when we are transmitting a msg
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
hard_sync_blocked <= '0' ;
ELSIF (clk'EVENT AND clk = '1') THEN
IF (((hard_sync_xhdl5 AND clk_en_q) OR ((((transmitting AND transmitter) OR go_tx) AND tx_point_xhdl4) AND (NOT tx_next))) = '1') THEN
hard_sync_blocked <= '1' ;
ELSE
IF ((go_rx_inter OR (((rx_idle OR rx_inter) AND sample_point_xhdl1) AND sampled_bit_xhdl2)) = '1') THEN
-- When a glitch performed synchronization
hard_sync_blocked <= '0' ;
END IF;
END IF;
END IF;
END PROCESS;
END ARCHITECTURE RTL;
----------------------------------------------------------------------------------------------
--
-- VHDL file generated by X-HDL - Revision 3.2.53 Aug. 1, 2005
-- Tue Aug 9 07:33:51 2005
--
-- Input file : C:/Documents and Settings/BryantI/My Documents/tmp/can_top.v
-- Design name : can_fifo
-- Author :
-- Company : Actel
--
-- Description :
--
--
----------------------------------------------------------------------------------------------
--
--////////////////////////////////////////////////////////////////////
--// ////
--// can_fifo.v ////
--// ////
--// ////
--// This file is part of the CAN Protocol Controller ////
--// http://www.opencores.org/projects/can/ ////
--// ////
--// ////
--// Author(s): ////
--// Igor Mohor ////
--// [email protected] ////
--// ////
--// ////
--// All additional information is available in the README.txt ////
--// file. ////
--// ////
--////////////////////////////////////////////////////////////////////
--// ////
--// Copyright (C) 2002, 2003, 2004 Authors ////
--// ////
--// This source file may be used and distributed without ////
--// restriction provided that this copyright statement is not ////
--// removed from the file and that any derivative work contains ////
--// the original copyright notice and the associated disclaimer. ////
--// ////
--// This source file is free software; you can redistribute it ////
--// and/or modify it under the terms of the GNU Lesser General ////
--// Public License as published by the Free Software Foundation; ////
--// either version 2.1 of the License, or (at your option) any ////
--// later version. ////
--// ////
--// This source is distributed in the hope that it will be ////
--// useful, but WITHOUT ANY WARRANTY; without even the implied ////
--// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
--// PURPOSE. See the GNU Lesser General Public License for more ////
--// details. ////
--// ////
--// You should have received a copy of the GNU Lesser General ////
--// Public License along with this source; if not, download it ////
--// from http://www.opencores.org/lgpl.shtml ////
--// ////
--// The CAN protocol is developed by Robert Bosch GmbH and ////
--// protected by patents. Anybody who wants to implement this ////
--// CAN IP core on silicon has to obtain a CAN protocol license ////
--// from Bosch. ////
--// ////
--////////////////////////////////////////////////////////////////////
--
-- CVS Revision History
--
-- Rev 1.28 rd_info_pointer fix from opencores merged. /Kristoffer
--
-- $Log: can_fifo.v,v $
-- Revision 1.27 2004/11/18 12:39:34 igorm
-- Fixes for compatibility after the SW reset.
--
-- Revision 1.26 2004/02/08 14:30:57 mohor
-- Header changed.
--
-- Revision 1.25 2003/10/23 16:52:17 mohor
-- Active high/low problem when Altera devices are used. Bug fixed by
-- Rojhalat Ibrahim.
--
-- Revision 1.24 2003/10/17 05:55:20 markom
-- mbist signals updated according to newest convention
--
-- Revision 1.23 2003/09/05 12:46:41 mohor
-- ALTERA_RAM supported.
--
-- Revision 1.22 2003/08/20 09:59:16 mohor
-- Artisan RAM fixed (when not using BIST).
--
-- Revision 1.21 2003/08/14 16:04:52 simons
-- Artisan ram instances added.
--
-- Revision 1.20 2003/07/16 14:00:45 mohor
-- Fixed according to the linter.
--
-- Revision 1.19 2003/07/03 09:30:44 mohor
-- PCI_BIST replaced with CAN_BIST.
--
-- Revision 1.18 2003/06/27 22:14:23 simons
-- Overrun fifo implemented with FFs, because it is not possible to create such a memory.
--
-- Revision 1.17 2003/06/27 20:56:15 simons
-- Virtual silicon ram instances added.
--
-- Revision 1.16 2003/06/18 23:03:44 mohor
-- Typo fixed.
--
-- Revision 1.15 2003/06/11 09:37:05 mohor
-- overrun and length_info fifos are initialized at the end of reset.
--
-- Revision 1.14 2003/03/05 15:02:30 mohor
-- Xilinx RAM added.
--
-- Revision 1.13 2003/03/01 22:53:33 mohor
-- Actel APA ram supported.
--
-- Revision 1.12 2003/02/19 14:44:03 mohor
-- CAN core finished. Host interface added. Registers finished.
-- Synchronization to the wishbone finished.
--
-- Revision 1.11 2003/02/14 20:17:01 mohor
-- Several registers added. Not finished, yet.
--
-- Revision 1.10 2003/02/11 00:56:06 mohor
-- Wishbone interface added.
--
-- Revision 1.9 2003/02/09 02:24:33 mohor
-- Bosch license warning added. Error counters finished. Overload frames
-- still need to be fixed.
--
-- Revision 1.8 2003/01/31 01:13:38 mohor
-- backup.
--
-- Revision 1.7 2003/01/17 17:44:31 mohor
-- Fifo corrected to be synthesizable.
--
-- Revision 1.6 2003/01/15 13:16:47 mohor
-- When a frame with "remote request" is received, no data is stored
-- to fifo, just the frame information (identifier, ...). Data length
-- that is stored is the received data length and not the actual data
-- length that is stored to fifo.
--
-- Revision 1.5 2003/01/14 17:25:09 mohor
-- Addresses corrected to decimal values (previously hex).
--
-- Revision 1.4 2003/01/14 12:19:35 mohor
-- rx_fifo is now working.
--
-- Revision 1.3 2003/01/09 21:54:45 mohor
-- rx fifo added. Not 100 % verified, yet.
--
-- Revision 1.2 2003/01/09 14:46:58 mohor
-- Temporary files (backup).
--
-- Revision 1.1 2003/01/08 02:10:55 mohor
-- Acceptance filter added.
--
--
--
--
-- synopsys translate_off
--`include "can_defines.v"
-- synopsys translate_on
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
library grlib;
use grlib.stdlib.all;
ENTITY can_fifo IS
PORT (
clk : IN std_logic;
rst : IN std_logic;
wr : IN std_logic;
data_in : IN std_logic_vector(7 DOWNTO 0);
addr : IN std_logic_vector(5 DOWNTO 0);
data_out : OUT std_logic_vector(7 DOWNTO 0);
fifo_selected : IN std_logic;
reset_mode : IN std_logic;
release_buffer : IN std_logic;
extended_mode : IN std_logic;
overrun : OUT std_logic;
info_empty : OUT std_logic;
info_cnt : OUT std_logic_vector(6 DOWNTO 0);
--------------------------------------------------
-- port connections for Ram
--64x8
q_dp_64x8 : IN std_logic_vector(7 DOWNTO 0);
data_64x8 : OUT std_logic_vector(7 DOWNTO 0);
wren_64x8 : OUT std_logic;
rden_64x8 : OUT std_logic;
wraddress_64x8 : OUT std_logic_vector(5 DOWNTO 0);
rdaddress_64x8 : OUT std_logic_vector(5 DOWNTO 0);
--64x4
q_dp_64x4 : IN std_logic_vector(3 DOWNTO 0);
data_64x4 : OUT std_logic_vector(3 DOWNTO 0);
wren_64x4x1 : OUT std_logic;
wraddress_64x4x1 : OUT std_logic_vector(5 DOWNTO 0);
rdaddress_64x4x1 : OUT std_logic_vector(5 DOWNTO 0);
--64x1
q_dp_64x1 : IN std_logic;
data_64x1 : OUT std_logic);
END ENTITY can_fifo;
ARCHITECTURE RTL OF can_fifo IS
TYPE xhdl_15 IS ARRAY (0 TO 63) OF std_logic_vector(7 DOWNTO 0);
TYPE xhdl_16 IS ARRAY (0 TO 63) OF std_logic_vector(3 DOWNTO 0);
TYPE xhdl_17 IS ARRAY (0 TO 63) OF std_logic;
TYPE xhdl_46 IS ARRAY (0 TO 7) OF std_logic_vector(7 DOWNTO 0);
--------------------------------------------------
SIGNAL fifo : xhdl_15;
SIGNAL length_fifo : xhdl_16;
SIGNAL overrun_info : xhdl_17;
SIGNAL rd_pointer : std_logic_vector(5 DOWNTO 0);
SIGNAL wr_pointer : std_logic_vector(5 DOWNTO 0);
SIGNAL read_address : std_logic_vector(5 DOWNTO 0);
SIGNAL wr_info_pointer : std_logic_vector(5 DOWNTO 0);
SIGNAL rd_info_pointer : std_logic_vector(5 DOWNTO 0);
SIGNAL wr_q : std_logic;
SIGNAL len_cnt : std_logic_vector(3 DOWNTO 0);
SIGNAL fifo_cnt : std_logic_vector(6 DOWNTO 0);
SIGNAL latch_overrun : std_logic;
SIGNAL initialize_memories : std_logic;
SIGNAL length_info : std_logic_vector(3 DOWNTO 0);
SIGNAL write_length_info : std_logic;
SIGNAL fifo_empty : std_logic;
SIGNAL fifo_full : std_logic;
SIGNAL info_full : std_logic;
SIGNAL data_out_xhdl1 : std_logic_vector(7 DOWNTO 0);
SIGNAL overrun_xhdl2 : std_logic;
SIGNAL info_empty_xhdl3 : std_logic;
SIGNAL info_cnt_xhdl4 : std_logic_vector(6 DOWNTO 0);
SIGNAL data_64x8_xhdl5 : std_logic_vector(7 DOWNTO 0);
SIGNAL wren_64x8_xhdl6 : std_logic;
SIGNAL rden_64x8_xhdl7 : std_logic;
SIGNAL wraddress_64x8_xhdl8 : std_logic_vector(5 DOWNTO 0);
SIGNAL rdaddress_64x8_xhdl9 : std_logic_vector(5 DOWNTO 0);
SIGNAL data_64x4_xhdl10 : std_logic_vector(3 DOWNTO 0);
SIGNAL wren_64x4x1_xhdl11 : std_logic;
SIGNAL wraddress_64x4x1_xhdl12 : std_logic_vector(5 DOWNTO 0);
SIGNAL rdaddress_64x4x1_xhdl13 : std_logic_vector(5 DOWNTO 0);
SIGNAL data_64x1_xhdl14 : std_logic;
BEGIN
data_out <= data_out_xhdl1;
overrun <= overrun_xhdl2;
info_empty <= info_empty_xhdl3;
info_cnt <= info_cnt_xhdl4;
data_64x8 <= data_64x8_xhdl5;
wren_64x8 <= wren_64x8_xhdl6;
rden_64x8 <= rden_64x8_xhdl7;
wraddress_64x8 <= wraddress_64x8_xhdl8;
rdaddress_64x8 <= rdaddress_64x8_xhdl9;
data_64x4 <= data_64x4_xhdl10;
wren_64x4x1 <= wren_64x4x1_xhdl11;
wraddress_64x4x1 <= wraddress_64x4x1_xhdl12;
rdaddress_64x4x1 <= rdaddress_64x4x1_xhdl13;
data_64x1 <= data_64x1_xhdl14;
write_length_info <= (NOT wr) AND wr_q ;
-- Delayed write signal
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
wr_q <= '0' ;
ELSIF (clk'EVENT AND clk = '1') THEN
IF (reset_mode = '1') THEN
wr_q <= '0' ;
ELSE
wr_q <= wr ;
END IF;
END IF;
END PROCESS;
-- length counter
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
len_cnt <= "0000";
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR write_length_info) = '1') THEN
len_cnt <= "0000" ;
ELSE
IF ((wr AND (NOT fifo_full)) = '1') THEN
len_cnt <= len_cnt + "0001" ;
END IF;
END IF;
END IF;
END PROCESS;
-- wr_info_pointer
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
wr_info_pointer <= "000000";
ELSIF (clk'EVENT AND clk = '1') THEN
IF (((write_length_info AND (NOT info_full)) OR initialize_memories) = '1') THEN
wr_info_pointer <= wr_info_pointer + "000001" ;
ELSE
IF (reset_mode = '1') THEN
wr_info_pointer <= rd_info_pointer ;
END IF;
END IF;
END IF;
END PROCESS;
-- rd_info_pointer
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
rd_info_pointer <= "000000";
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((release_buffer AND (NOT info_empty_xhdl3)) = '1') THEN
-- Fix from opencores rev 1.28
-- IF ((release_buffer AND (NOT fifo_empty)) = '1') THEN
rd_info_pointer <= rd_info_pointer + "000001" ;
END IF;
END IF;
END PROCESS;
-- rd_pointer
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
rd_pointer <= "000000";
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((release_buffer AND (NOT fifo_empty)) = '1') THEN
rd_pointer <= rd_pointer + ("00" & length_info) ;
END IF;
END IF;
END PROCESS;
-- wr_pointer
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
wr_pointer <= "000000";
ELSIF (clk'EVENT AND clk = '1') THEN
IF (reset_mode = '1') THEN
wr_pointer <= rd_pointer ;
ELSE
IF ((wr AND (NOT fifo_full)) = '1') THEN
wr_pointer <= wr_pointer + "000001" ;
END IF;
END IF;
END IF;
END PROCESS;
-- latch_overrun
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
latch_overrun <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR write_length_info) = '1') THEN
latch_overrun <= '0' ;
ELSE
IF ((wr AND fifo_full) = '1') THEN
latch_overrun <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
-- Counting data in fifo
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
fifo_cnt <= "0000000";
ELSIF (clk'EVENT AND clk = '1') THEN
IF (reset_mode = '1') THEN
fifo_cnt <= "0000000" ;
ELSE
IF (((wr AND (NOT release_buffer)) AND (NOT fifo_full)) = '1') THEN
fifo_cnt <= fifo_cnt + "0000001" ;
ELSE
IF ((((NOT wr) AND release_buffer) AND (NOT fifo_empty)) = '1') THEN
fifo_cnt <= fifo_cnt - ("000" & length_info) ;
ELSE
IF ((((wr AND release_buffer) AND (NOT fifo_full)) AND (NOT fifo_empty)) = '1') THEN
fifo_cnt <= fifo_cnt - ("000" & length_info) + "0000001" ;
END IF;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
fifo_full <= CONV_STD_LOGIC(fifo_cnt = "1000000") ;
fifo_empty <= CONV_STD_LOGIC(fifo_cnt = "0000000") ;
-- Counting data in length_fifo and overrun_info fifo
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
info_cnt_xhdl4 <= "0000000" ;
ELSIF (clk'EVENT AND clk = '1') THEN
IF (reset_mode = '1') THEN
info_cnt_xhdl4 <= "0000000" ;
ELSE
IF ((write_length_info XOR release_buffer) = '1') THEN
IF ((release_buffer AND (NOT info_empty_xhdl3)) = '1') THEN
info_cnt_xhdl4 <= info_cnt_xhdl4 - "0000001" ;
ELSE
IF ((write_length_info AND (NOT info_full)) = '1') THEN
info_cnt_xhdl4 <= info_cnt_xhdl4 + "0000001" ;
END IF;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
info_full <= CONV_STD_LOGIC(info_cnt_xhdl4 = "1000000") ;
info_empty_xhdl3 <= CONV_STD_LOGIC(info_cnt_xhdl4 = "0000000") ;
-- Selecting which address will be used for reading data from rx fifo
PROCESS (extended_mode, rd_pointer, addr)
VARIABLE read_address_xhdl18 : std_logic_vector(5 DOWNTO 0);
BEGIN
IF (extended_mode = '1') THEN
-- extended mode
read_address_xhdl18 := rd_pointer + (addr - "010000");
ELSE
-- normal mode
read_address_xhdl18 := rd_pointer + (addr - "010100");
END IF;
read_address <= read_address_xhdl18;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
initialize_memories <= '1';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (andv(wr_info_pointer) = '1') THEN
initialize_memories <= '0' ;
END IF;
END IF;
END PROCESS;
-- port connections for Ram
--64x8
data_out_xhdl1 <= q_dp_64x8 ;
data_64x8_xhdl5 <= data_in ;
wren_64x8_xhdl6 <= wr AND (NOT fifo_full) ;
rden_64x8_xhdl7 <= fifo_selected ;
wraddress_64x8_xhdl8 <= wr_pointer ;
rdaddress_64x8_xhdl9 <= read_address ;
--64x4
length_info <= q_dp_64x4 ;
data_64x4_xhdl10 <= len_cnt AND NOT initialize_memories & NOT initialize_memories & NOT initialize_memories & NOT initialize_memories ;
wren_64x4x1_xhdl11 <= (write_length_info AND (NOT info_full)) OR initialize_memories ;
wraddress_64x4x1_xhdl12 <= wr_info_pointer ;
rdaddress_64x4x1_xhdl13 <= rd_info_pointer ;
--64x1
overrun_xhdl2 <= q_dp_64x1 ;
data_64x1_xhdl14 <= (latch_overrun OR (wr AND fifo_full)) AND (NOT initialize_memories) ;
-- `ifdef ALTERA_RAM
-- // altera_ram_64x8_sync fifo
-- lpm_ram_dp fifo
-- (
-- .q (data_out),
-- .rdclock (clk),
-- .wrclock (clk),
-- .data (data_in),
-- .wren (wr & (~fifo_full)),
-- .rden (fifo_selected),
-- .wraddress (wr_pointer),
-- .rdaddress (read_address)
-- );
-- defparam fifo.lpm_width = 8;
-- defparam fifo.lpm_widthad = 6;
-- defparam fifo.lpm_numwords = 64;
--
--
-- // altera_ram_64x4_sync info_fifo
-- lpm_ram_dp info_fifo
-- (
-- .q (length_info),
-- .rdclock (clk),
-- .wrclock (clk),
-- .data (len_cnt & {4{~initialize_memories}}),
-- .wren (write_length_info & (~info_full) | initialize_memories),
-- .wraddress (wr_info_pointer),
-- .rdaddress (rd_info_pointer)
-- );
-- defparam info_fifo.lpm_width = 4;
-- defparam info_fifo.lpm_widthad = 6;
-- defparam info_fifo.lpm_numwords = 64;
--
--
-- // altera_ram_64x1_sync overrun_fifo
-- lpm_ram_dp overrun_fifo
-- (
-- .q (overrun),
-- .rdclock (clk),
-- .wrclock (clk),
-- .data ((latch_overrun | (wr & fifo_full)) & (~initialize_memories)),
-- .wren (write_length_info & (~info_full) | initialize_memories),
-- .wraddress (wr_info_pointer),
-- .rdaddress (rd_info_pointer)
-- );
-- defparam overrun_fifo.lpm_width = 1;
-- defparam overrun_fifo.lpm_widthad = 6;
-- defparam overrun_fifo.lpm_numwords = 64;
END ARCHITECTURE RTL;
----------------------------------------------------------------------------------------------
--
-- VHDL file generated by X-HDL - Revision 3.2.53 Aug. 1, 2005
-- Tue Aug 9 07:33:51 2005
--
-- Input file : C:/Documents and Settings/BryantI/My Documents/tmp/can_top.v
-- Design name : can_crc
-- Author :
-- Company : Actel
--
-- Description :
--
--
----------------------------------------------------------------------------------------------
--
--////////////////////////////////////////////////////////////////////
--// ////
--// can_crc.v ////
--// ////
--// ////
--// This file is part of the CAN Protocol Controller ////
--// http://www.opencores.org/projects/can/ ////
--// ////
--// ////
--// Author(s): ////
--// Igor Mohor ////
--// [email protected] ////
--// ////
--// ////
--// All additional information is available in the README.txt ////
--// file. ////
--// ////
--////////////////////////////////////////////////////////////////////
--// ////
--// Copyright (C) 2002, 2003, 2004 Authors ////
--// ////
--// This source file may be used and distributed without ////
--// restriction provided that this copyright statement is not ////
--// removed from the file and that any derivative work contains ////
--// the original copyright notice and the associated disclaimer. ////
--// ////
--// This source file is free software; you can redistribute it ////
--// and/or modify it under the terms of the GNU Lesser General ////
--// Public License as published by the Free Software Foundation; ////
--// either version 2.1 of the License, or (at your option) any ////
--// later version. ////
--// ////
--// This source is distributed in the hope that it will be ////
--// useful, but WITHOUT ANY WARRANTY; without even the implied ////
--// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
--// PURPOSE. See the GNU Lesser General Public License for more ////
--// details. ////
--// ////
--// You should have received a copy of the GNU Lesser General ////
--// Public License along with this source; if not, download it ////
--// from http://www.opencores.org/lgpl.shtml ////
--// ////
--// The CAN protocol is developed by Robert Bosch GmbH and ////
--// protected by patents. Anybody who wants to implement this ////
--// CAN IP core on silicon has to obtain a CAN protocol license ////
--// from Bosch. ////
--// ////
--////////////////////////////////////////////////////////////////////
--
-- CVS Revision History
--
-- $Log: can_crc.v,v $
-- Revision 1.5 2004/02/08 14:25:57 mohor
-- Header changed.
--
-- Revision 1.4 2003/07/16 13:16:51 mohor
-- Fixed according to the linter.
--
-- Revision 1.3 2003/02/10 16:02:11 mohor
-- CAN is working according to the specification. WB interface and more
-- registers (status, IRQ, ...) needs to be added.
--
-- Revision 1.2 2003/02/09 02:24:33 mohor
-- Bosch license warning added. Error counters finished. Overload frames
-- still need to be fixed.
--
-- Revision 1.1 2003/01/08 02:10:54 mohor
-- Acceptance filter added.
--
--
--
--
-- synopsys translate_off
--`include "can_defines.v"
-- synopsys translate_on
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
library grlib;
use grlib.stdlib.all;
ENTITY can_crc IS
PORT (
clk : IN std_logic;
data : IN std_logic;
enable : IN std_logic;
initialize : IN std_logic;
crc : OUT std_logic_vector(14 DOWNTO 0));
END ENTITY can_crc;
ARCHITECTURE RTL OF can_crc IS
TYPE xhdl_46 IS ARRAY (0 TO 7) OF std_logic_vector(7 DOWNTO 0);
SIGNAL crc_next : std_logic;
SIGNAL crc_tmp : std_logic_vector(14 DOWNTO 0);
SIGNAL crc_xhdl1 : std_logic_vector(14 DOWNTO 0);
BEGIN
crc <= crc_xhdl1;
crc_next <= data XOR crc_xhdl1(14) ;
crc_tmp <= crc_xhdl1(13 DOWNTO 0) & '0' ;
PROCESS (clk)
BEGIN
IF (clk'EVENT AND clk = '1') THEN
IF (initialize = '1') THEN
crc_xhdl1 <= "000000000000000";
ELSE
IF (enable = '1') THEN
IF (crc_next = '1') THEN
crc_xhdl1 <= crc_tmp XOR "100010110011001";
ELSE
crc_xhdl1 <= crc_tmp ;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
END ARCHITECTURE RTL;
----------------------------------------------------------------------------------------------
--
-- VHDL file generated by X-HDL - Revision 3.2.53 Aug. 1, 2005
-- Tue Aug 9 07:33:51 2005
--
-- Input file : C:/Documents and Settings/BryantI/My Documents/tmp/can_top.v
-- Design name : can_ibo
-- Author :
-- Company : Actel
--
-- Description :
--
--
----------------------------------------------------------------------------------------------
--
--////////////////////////////////////////////////////////////////////
--// ////
--// can_ibo.v ////
--// ////
--// ////
--// This file is part of the CAN Protocol Controller ////
--// http://www.opencores.org/projects/can/ ////
--// ////
--// ////
--// Author(s): ////
--// Igor Mohor ////
--// [email protected] ////
--// ////
--// ////
--// All additional information is available in the README.txt ////
--// file. ////
--// ////
--////////////////////////////////////////////////////////////////////
--// ////
--// Copyright (C) 2002, 2003, 2004 Authors ////
--// ////
--// This source file may be used and distributed without ////
--// restriction provided that this copyright statement is not ////
--// removed from the file and that any derivative work contains ////
--// the original copyright notice and the associated disclaimer. ////
--// ////
--// This source file is free software; you can redistribute it ////
--// and/or modify it under the terms of the GNU Lesser General ////
--// Public License as published by the Free Software Foundation; ////
--// either version 2.1 of the License, or (at your option) any ////
--// later version. ////
--// ////
--// This source is distributed in the hope that it will be ////
--// useful, but WITHOUT ANY WARRANTY; without even the implied ////
--// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
--// PURPOSE. See the GNU Lesser General Public License for more ////
--// details. ////
--// ////
--// You should have received a copy of the GNU Lesser General ////
--// Public License along with this source; if not, download it ////
--// from http://www.opencores.org/lgpl.shtml ////
--// ////
--// The CAN protocol is developed by Robert Bosch GmbH and ////
--// protected by patents. Anybody who wants to implement this ////
--// CAN IP core on silicon has to obtain a CAN protocol license ////
--// from Bosch. ////
--// ////
--////////////////////////////////////////////////////////////////////
--
-- CVS Revision History
--
-- $Log: can_ibo.v,v $
-- Revision 1.3 2004/02/08 14:31:44 mohor
-- Header changed.
--
-- Revision 1.2 2003/02/09 02:24:33 mohor
-- Bosch license warning added. Error counters finished. Overload frames
-- still need to be fixed.
--
-- Revision 1.1 2003/02/04 14:34:52 mohor
-- *** empty log message ***
--
--
--
--
-- synopsys translate_off
--`include "can_defines.v"
-- synopsys translate_on
-- This module only inverts bit order
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY can_ibo IS
PORT (
di : IN std_logic_vector(7 DOWNTO 0);
do : OUT std_logic_vector(7 DOWNTO 0));
END ENTITY can_ibo;
ARCHITECTURE RTL OF can_ibo IS
TYPE xhdl_15 IS ARRAY (0 TO 63) OF std_logic_vector(7 DOWNTO 0);
TYPE xhdl_16 IS ARRAY (0 TO 63) OF std_logic_vector(3 DOWNTO 0);
TYPE xhdl_17 IS ARRAY (0 TO 63) OF std_logic;
TYPE xhdl_46 IS ARRAY (0 TO 7) OF std_logic_vector(7 DOWNTO 0);
SIGNAL do_xhdl1 : std_logic_vector(7 DOWNTO 0);
BEGIN
do <= do_xhdl1;
do_xhdl1(0) <= di(7) ;
do_xhdl1(1) <= di(6) ;
do_xhdl1(2) <= di(5) ;
do_xhdl1(3) <= di(4) ;
do_xhdl1(4) <= di(3) ;
do_xhdl1(5) <= di(2) ;
do_xhdl1(6) <= di(1) ;
do_xhdl1(7) <= di(0) ;
END ARCHITECTURE RTL;
----------------------------------------------------------------------------------------------
--
-- VHDL file generated by X-HDL - Revision 3.2.53 Aug. 1, 2005
-- Tue Aug 9 07:33:51 2005
--
-- Input file : C:/Documents and Settings/BryantI/My Documents/tmp/can_top.v
-- Design name : can_bsp
-- Author :
-- Company : Actel
--
-- Description :
--
--
----------------------------------------------------------------------------------------------
--
--////////////////////////////////////////////////////////////////////
--// ////
--// can_bsp.v ////
--// ////
--// ////
--// This file is part of the CAN Protocol Controller ////
--// http://www.opencores.org/projects/can/ ////
--// ////
--// ////
--// Author(s): ////
--// Igor Mohor ////
--// [email protected] ////
--// ////
--// ////
--// All additional information is available in the README.txt ////
--// file. ////
--// ////
--////////////////////////////////////////////////////////////////////
--// ////
--// Copyright (C) 2002, 2003, 2004 Authors ////
--// ////
--// This source file may be used and distributed without ////
--// restriction provided that this copyright statement is not ////
--// removed from the file and that any derivative work contains ////
--// the original copyright notice and the associated disclaimer. ////
--// ////
--// This source file is free software; you can redistribute it ////
--// and/or modify it under the terms of the GNU Lesser General ////
--// Public License as published by the Free Software Foundation; ////
--// either version 2.1 of the License, or (at your option) any ////
--// later version. ////
--// ////
--// This source is distributed in the hope that it will be ////
--// useful, but WITHOUT ANY WARRANTY; without even the implied ////
--// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
--// PURPOSE. See the GNU Lesser General Public License for more ////
--// details. ////
--// ////
--// You should have received a copy of the GNU Lesser General ////
--// Public License along with this source; if not, download it ////
--// from http://www.opencores.org/lgpl.shtml ////
--// ////
--// The CAN protocol is developed by Robert Bosch GmbH and ////
--// protected by patents. Anybody who wants to implement this ////
--// CAN IP core on silicon has to obtain a CAN protocol license ////
--// from Bosch. ////
--// ////
--////////////////////////////////////////////////////////////////////
--
-- CVS Revision History
--
-- $Log: can_bsp.v,v $
-- Revision 1.52 2004/11/18 12:39:21 igorm
-- Fixes for compatibility after the SW reset.
--
-- Revision 1.51 2004/11/15 18:23:21 igorm
-- When CAN was reset by setting the reset_mode signal in mode register, it
-- was possible that CAN was blocked for a short period of time. Problem
-- occured very rarly.
--
-- Revision 1.50 2004/10/27 18:51:36 igorm
-- Fixed synchronization problem in real hardware when 0xf is used for TSEG1.
--
-- Revision 1.49 2004/10/25 06:37:51 igorm
-- Arbitration bug fixed.
--
-- Revision 1.48 2004/05/12 15:58:41 igorm
-- Core improved to pass all tests with the Bosch VHDL Reference system.
--
-- Revision 1.47 2004/02/08 14:24:10 mohor
-- Error counters changed.
--
-- Revision 1.46 2003/10/17 05:55:20 markom
-- mbist signals updated according to newest convention
--
-- Revision 1.45 2003/09/30 21:14:33 mohor
-- Error counters changed.
--
-- Revision 1.44 2003/09/30 00:55:12 mohor
-- Error counters fixed to be compatible with Bosch VHDL reference model.
-- Small synchronization changes.
--
-- Revision 1.43 2003/09/25 18:55:49 mohor
-- Synchronization changed, error counters fixed.
--
-- Revision 1.42 2003/08/29 07:01:14 mohor
-- When detecting bus-free, signal bus_free_cnt_en was cleared to zero
-- although the last sampled bit was zero instead of one.
--
-- Revision 1.41 2003/07/18 15:23:31 tadejm
-- Tx and rx length are limited to 8 bytes regardless to the DLC value.
--
-- Revision 1.40 2003/07/16 15:10:17 mohor
-- Fixed according to the linter.
--
-- Revision 1.39 2003/07/16 13:12:46 mohor
-- Fixed according to the linter.
--
-- Revision 1.38 2003/07/10 01:59:04 tadejm
-- Synchronization fixed. In some strange cases it didn't work according to
-- the VHDL reference model.
--
-- Revision 1.37 2003/07/07 11:21:37 mohor
-- Little fixes (to fix warnings).
--
-- Revision 1.36 2003/07/03 09:32:20 mohor
-- Synchronization changed.
--
-- Revision 1.35 2003/06/27 20:56:12 simons
-- Virtual silicon ram instances added.
--
-- Revision 1.34 2003/06/22 09:43:03 mohor
-- synthesi full_case parallel_case fixed.
--
-- Revision 1.33 2003/06/21 12:16:30 mohor
-- paralel_case and full_case compiler directives added to case statements.
--
-- Revision 1.32 2003/06/17 14:28:32 mohor
-- Form error was detected when stuff bit occured at the end of crc.
--
-- Revision 1.31 2003/06/16 14:31:29 tadejm
-- Bit stuffing corrected when stuffing comes at the end of the crc.
--
-- Revision 1.30 2003/06/16 13:57:58 mohor
-- tx_point generated one clk earlier. rx_i registered. Data corrected when
-- using extended mode.
--
-- Revision 1.29 2003/06/11 14:21:35 mohor
-- When switching to tx, sync stage is overjumped.
--
-- Revision 1.28 2003/03/01 22:53:33 mohor
-- Actel APA ram supported.
--
-- Revision 1.27 2003/02/20 00:26:02 mohor
-- When a dominant bit was detected at the third bit of the intermission and
-- node had a message to transmit, bit_stuff error could occur. Fixed.
--
-- Revision 1.26 2003/02/19 23:21:54 mohor
-- When bit error occured while active error flag was transmitted, counter was
-- not incremented.
--
-- Revision 1.25 2003/02/19 14:44:03 mohor
-- CAN core finished. Host interface added. Registers finished.
-- Synchronization to the wishbone finished.
--
-- Revision 1.24 2003/02/18 00:10:15 mohor
-- Most of the registers added. Registers "arbitration lost capture", "error code
-- capture" + few more still need to be added.
--
-- Revision 1.23 2003/02/14 20:17:01 mohor
-- Several registers added. Not finished, yet.
--
-- Revision 1.22 2003/02/12 14:23:59 mohor
-- abort_tx added. Bit destuff fixed.
--
-- Revision 1.21 2003/02/11 00:56:06 mohor
-- Wishbone interface added.
--
-- Revision 1.20 2003/02/10 16:02:11 mohor
-- CAN is working according to the specification. WB interface and more
-- registers (status, IRQ, ...) needs to be added.
--
-- Revision 1.19 2003/02/09 18:40:29 mohor
-- Overload fixed. Hard synchronization also enabled at the last bit of
-- interframe.
--
-- Revision 1.18 2003/02/09 02:24:33 mohor
-- Bosch license warning added. Error counters finished. Overload frames
-- still need to be fixed.
--
-- Revision 1.17 2003/02/04 17:24:41 mohor
-- Backup.
--
-- Revision 1.16 2003/02/04 14:34:52 mohor
-- *** empty log message ***
--
-- Revision 1.15 2003/01/31 01:13:37 mohor
-- backup.
--
-- Revision 1.14 2003/01/16 13:36:19 mohor
-- Form error supported. When receiving messages, last bit of the end-of-frame
-- does not generate form error. Receiver goes to the idle mode one bit sooner.
-- (CAN specification ver 2.0, part B, page 57).
--
-- Revision 1.13 2003/01/15 21:59:45 mohor
-- Data is stored to fifo at the end of ack stage.
--
-- Revision 1.12 2003/01/15 21:05:11 mohor
-- CRC checking fixed (when bitstuff occurs at the end of a CRC sequence).
--
-- Revision 1.11 2003/01/15 14:40:23 mohor
-- RX state machine fixed to receive "remote request" frames correctly.
-- No data bytes are written to fifo when such frames are received.
--
-- Revision 1.10 2003/01/15 13:16:47 mohor
-- When a frame with "remote request" is received, no data is stored to
-- fifo, just the frame information (identifier, ...). Data length that
-- is stored is the received data length and not the actual data length
-- that is stored to fifo.
--
-- Revision 1.9 2003/01/14 12:19:35 mohor
-- rx_fifo is now working.
--
-- Revision 1.8 2003/01/10 17:51:33 mohor
-- Temporary version (backup).
--
-- Revision 1.7 2003/01/09 21:54:45 mohor
-- rx fifo added. Not 100 % verified, yet.
--
-- Revision 1.6 2003/01/09 14:46:58 mohor
-- Temporary files (backup).
--
-- Revision 1.5 2003/01/08 13:30:31 mohor
-- Temp version.
--
-- Revision 1.4 2003/01/08 02:10:53 mohor
-- Acceptance filter added.
--
-- Revision 1.3 2002/12/28 04:13:23 mohor
-- Backup version.
--
-- Revision 1.2 2002/12/27 00:12:52 mohor
-- Header changed, testbench improved to send a frame (crc still missing).
--
-- Revision 1.1.1.1 2002/12/20 16:39:21 mohor
-- Initial
--
--
--
-- synopsys translate_off
--`include "can_defines.v"
-- synopsys translate_on
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
library grlib;
use grlib.stdlib.all;
ENTITY can_bsp IS
PORT (
clk : IN std_logic;
rst : IN std_logic;
sample_point : IN std_logic;
sampled_bit : IN std_logic;
sampled_bit_q : IN std_logic;
tx_point : IN std_logic;
hard_sync : IN std_logic;
addr : IN std_logic_vector(7 DOWNTO 0);
data_in : IN std_logic_vector(7 DOWNTO 0);
data_out : OUT std_logic_vector(7 DOWNTO 0);
fifo_selected : IN std_logic;
reset_mode : IN std_logic;
listen_only_mode : IN std_logic;
acceptance_filter_mode : IN std_logic;
self_test_mode : IN std_logic;
-- Command register
release_buffer : IN std_logic;
tx_request : IN std_logic;
abort_tx : IN std_logic;
self_rx_request : IN std_logic;
single_shot_transmission: IN std_logic;
tx_state : OUT std_logic;
tx_state_q : OUT std_logic;
overload_request : IN std_logic; -- When receiver is busy, it needs to send overload frame. Only 2 overload frames are allowed to
overload_frame : OUT std_logic; -- be send in a row. This is not implemented, yet, because host can not send an overload request.
-- Arbitration Lost Capture Register
read_arbitration_lost_capture_reg: IN std_logic;
-- Error Code Capture Register
read_error_code_capture_reg: IN std_logic;
error_capture_code : OUT std_logic_vector(7 DOWNTO 0);
-- Error Warning Limit register
error_warning_limit : IN std_logic_vector(7 DOWNTO 0);
-- Rx Error Counter register
we_rx_err_cnt : IN std_logic;
-- Tx Error Counter register
we_tx_err_cnt : IN std_logic;
extended_mode : IN std_logic;
rx_idle : OUT std_logic;
transmitting : OUT std_logic;
transmitter : OUT std_logic;
go_rx_inter : OUT std_logic;
not_first_bit_of_inter : OUT std_logic;
rx_inter : OUT std_logic;
set_reset_mode : OUT std_logic;
node_bus_off : OUT std_logic;
error_status : OUT std_logic;
rx_err_cnt : OUT std_logic_vector(8 DOWNTO 0);
tx_err_cnt : OUT std_logic_vector(8 DOWNTO 0);
transmit_status : OUT std_logic;
receive_status : OUT std_logic;
tx_successful : OUT std_logic;
need_to_tx : OUT std_logic;
overrun : OUT std_logic;
info_empty : OUT std_logic;
set_bus_error_irq : OUT std_logic;
set_arbitration_lost_irq: OUT std_logic;
arbitration_lost_capture: OUT std_logic_vector(4 DOWNTO 0);
node_error_passive : OUT std_logic;
node_error_active : OUT std_logic;
rx_message_counter : OUT std_logic_vector(6 DOWNTO 0);
-- This section is for BASIC and EXTENDED mode -- Acceptance code register
acceptance_code_0 : IN std_logic_vector(7 DOWNTO 0);
-- Acceptance mask register
acceptance_mask_0 : IN std_logic_vector(7 DOWNTO 0);
-- End: This section is for BASIC and EXTENDED mode -- This section is for EXTENDED mode -- Acceptance code register
acceptance_code_1 : IN std_logic_vector(7 DOWNTO 0);
acceptance_code_2 : IN std_logic_vector(7 DOWNTO 0);
acceptance_code_3 : IN std_logic_vector(7 DOWNTO 0);
-- Acceptance mask register
acceptance_mask_1 : IN std_logic_vector(7 DOWNTO 0);
acceptance_mask_2 : IN std_logic_vector(7 DOWNTO 0);
acceptance_mask_3 : IN std_logic_vector(7 DOWNTO 0);
-- End: This section is for EXTENDED mode -- Tx data registers. Holding identifier (basic mode), tx frame information (extended mode) and data
tx_data_0 : IN std_logic_vector(7 DOWNTO 0);
tx_data_1 : IN std_logic_vector(7 DOWNTO 0);
tx_data_2 : IN std_logic_vector(7 DOWNTO 0);
tx_data_3 : IN std_logic_vector(7 DOWNTO 0);
tx_data_4 : IN std_logic_vector(7 DOWNTO 0);
tx_data_5 : IN std_logic_vector(7 DOWNTO 0);
tx_data_6 : IN std_logic_vector(7 DOWNTO 0);
tx_data_7 : IN std_logic_vector(7 DOWNTO 0);
tx_data_8 : IN std_logic_vector(7 DOWNTO 0);
tx_data_9 : IN std_logic_vector(7 DOWNTO 0);
tx_data_10 : IN std_logic_vector(7 DOWNTO 0);
tx_data_11 : IN std_logic_vector(7 DOWNTO 0);
tx_data_12 : IN std_logic_vector(7 DOWNTO 0);
-- End: Tx data registers -- Tx signal
tx : OUT std_logic;
tx_next : OUT std_logic;
bus_off_on : OUT std_logic;
go_overload_frame : OUT std_logic;
go_error_frame : OUT std_logic;
go_tx : OUT std_logic;
send_ack : OUT std_logic;
-- Bist -- port connections for Ram
--64x8
q_dp_64x8 : IN std_logic_vector(7 DOWNTO 0);
data_64x8 : OUT std_logic_vector(7 DOWNTO 0);
wren_64x8 : OUT std_logic;
rden_64x8 : OUT std_logic;
wraddress_64x8 : OUT std_logic_vector(5 DOWNTO 0);
rdaddress_64x8 : OUT std_logic_vector(5 DOWNTO 0);
--64x4
q_dp_64x4 : IN std_logic_vector(3 DOWNTO 0);
data_64x4 : OUT std_logic_vector(3 DOWNTO 0);
wren_64x4x1 : OUT std_logic;
wraddress_64x4x1 : OUT std_logic_vector(5 DOWNTO 0);
rdaddress_64x4x1 : OUT std_logic_vector(5 DOWNTO 0);
--64x1
q_dp_64x1 : IN std_logic;
data_64x1 : OUT std_logic);
END ENTITY can_bsp;
ARCHITECTURE RTL OF can_bsp IS
COMPONENT can_acf
PORT (
clk : IN std_logic;
rst : IN std_logic;
id : IN std_logic_vector(28 DOWNTO 0);
reset_mode : IN std_logic;
acceptance_filter_mode : IN std_logic;
extended_mode : IN std_logic;
acceptance_code_0 : IN std_logic_vector(7 DOWNTO 0);
acceptance_code_1 : IN std_logic_vector(7 DOWNTO 0);
acceptance_code_2 : IN std_logic_vector(7 DOWNTO 0);
acceptance_code_3 : IN std_logic_vector(7 DOWNTO 0);
acceptance_mask_0 : IN std_logic_vector(7 DOWNTO 0);
acceptance_mask_1 : IN std_logic_vector(7 DOWNTO 0);
acceptance_mask_2 : IN std_logic_vector(7 DOWNTO 0);
acceptance_mask_3 : IN std_logic_vector(7 DOWNTO 0);
go_rx_crc_lim : IN std_logic;
go_rx_inter : IN std_logic;
go_error_frame : IN std_logic;
data0 : IN std_logic_vector(7 DOWNTO 0);
data1 : IN std_logic_vector(7 DOWNTO 0);
rtr1 : IN std_logic;
rtr2 : IN std_logic;
ide : IN std_logic;
no_byte0 : IN std_logic;
no_byte1 : IN std_logic;
id_ok : OUT std_logic);
END COMPONENT;
COMPONENT can_crc
PORT (
clk : IN std_logic;
data : IN std_logic;
enable : IN std_logic;
initialize : IN std_logic;
crc : OUT std_logic_vector(14 DOWNTO 0));
END COMPONENT;
COMPONENT can_fifo
PORT (
clk : IN std_logic;
rst : IN std_logic;
wr : IN std_logic;
data_in : IN std_logic_vector(7 DOWNTO 0);
addr : IN std_logic_vector(5 DOWNTO 0);
data_out : OUT std_logic_vector(7 DOWNTO 0);
fifo_selected : IN std_logic;
reset_mode : IN std_logic;
release_buffer : IN std_logic;
extended_mode : IN std_logic;
overrun : OUT std_logic;
info_empty : OUT std_logic;
info_cnt : OUT std_logic_vector(6 DOWNTO 0);
q_dp_64x8 : IN std_logic_vector(7 DOWNTO 0);
data_64x8 : OUT std_logic_vector(7 DOWNTO 0);
wren_64x8 : OUT std_logic;
rden_64x8 : OUT std_logic;
wraddress_64x8 : OUT std_logic_vector(5 DOWNTO 0);
rdaddress_64x8 : OUT std_logic_vector(5 DOWNTO 0);
q_dp_64x4 : IN std_logic_vector(3 DOWNTO 0);
data_64x4 : OUT std_logic_vector(3 DOWNTO 0);
wren_64x4x1 : OUT std_logic;
wraddress_64x4x1 : OUT std_logic_vector(5 DOWNTO 0);
rdaddress_64x4x1 : OUT std_logic_vector(5 DOWNTO 0);
q_dp_64x1 : IN std_logic;
data_64x1 : OUT std_logic);
END COMPONENT;
COMPONENT can_ibo
PORT (
di : IN std_logic_vector(7 DOWNTO 0);
do : OUT std_logic_vector(7 DOWNTO 0));
END COMPONENT;
TYPE xhdl_46 IS ARRAY (0 TO 7) OF std_logic_vector(7 DOWNTO 0);
------------------------------
SIGNAL reset_mode_q : std_logic;
SIGNAL bit_cnt : std_logic_vector(5 DOWNTO 0);
SIGNAL data_len : std_logic_vector(3 DOWNTO 0);
SIGNAL id : std_logic_vector(28 DOWNTO 0);
SIGNAL bit_stuff_cnt : std_logic_vector(2 DOWNTO 0);
SIGNAL bit_stuff_cnt_tx : std_logic_vector(2 DOWNTO 0);
SIGNAL tx_point_q : std_logic;
SIGNAL rx_id1 : std_logic;
SIGNAL rx_rtr1 : std_logic;
SIGNAL rx_ide : std_logic;
SIGNAL rx_id2 : std_logic;
SIGNAL rx_rtr2 : std_logic;
SIGNAL rx_r1 : std_logic;
SIGNAL rx_r0 : std_logic;
SIGNAL rx_dlc : std_logic;
SIGNAL rx_data : std_logic;
SIGNAL rx_crc : std_logic;
SIGNAL rx_crc_lim : std_logic;
SIGNAL rx_ack : std_logic;
SIGNAL rx_ack_lim : std_logic;
SIGNAL rx_eof : std_logic;
SIGNAL go_early_tx_latched : std_logic;
SIGNAL rtr1 : std_logic;
SIGNAL ide : std_logic;
SIGNAL rtr2 : std_logic;
SIGNAL crc_in : std_logic_vector(14 DOWNTO 0);
SIGNAL tmp_data : std_logic_vector(7 DOWNTO 0);
SIGNAL tmp_fifo : xhdl_46;
SIGNAL write_data_to_tmp_fifo : std_logic;
SIGNAL byte_cnt : std_logic_vector(2 DOWNTO 0);
SIGNAL bit_stuff_cnt_en : std_logic;
SIGNAL crc_enable : std_logic;
SIGNAL eof_cnt : std_logic_vector(2 DOWNTO 0);
SIGNAL passive_cnt : std_logic_vector(2 DOWNTO 0);
SIGNAL error_frame : std_logic;
SIGNAL enable_error_cnt2 : std_logic;
SIGNAL error_cnt1 : std_logic_vector(2 DOWNTO 0);
SIGNAL error_cnt2 : std_logic_vector(2 DOWNTO 0);
SIGNAL delayed_dominant_cnt : std_logic_vector(2 DOWNTO 0);
SIGNAL enable_overload_cnt2 : std_logic;
SIGNAL overload_frame_blocked : std_logic;
SIGNAL overload_request_cnt : std_logic_vector(1 DOWNTO 0);
SIGNAL overload_cnt1 : std_logic_vector(2 DOWNTO 0);
SIGNAL overload_cnt2 : std_logic_vector(2 DOWNTO 0);
SIGNAL crc_err : std_logic;
SIGNAL arbitration_lost : std_logic;
SIGNAL arbitration_lost_q : std_logic;
SIGNAL read_arbitration_lost_capture_reg_q: std_logic;
signal read_error_code_capture_reg_q : std_logic;
signal reset_error_code_capture_reg : std_logic;
SIGNAL arbitration_cnt_en : std_logic;
SIGNAL arbitration_blocked : std_logic;
SIGNAL tx_q : std_logic;
SIGNAL data_cnt : std_logic_vector(3 DOWNTO 0); -- Counting the data bytes that are written to FIFO
SIGNAL header_cnt : std_logic_vector(2 DOWNTO 0); -- Counting header length
SIGNAL wr_fifo : std_logic; -- Write data and header to 64-byte fifo
SIGNAL data_for_fifo : std_logic_vector(7 DOWNTO 0); -- Multiplexed data that is stored to 64-byte fifo
SIGNAL tx_pointer : std_logic_vector(5 DOWNTO 0);
SIGNAL tx_bit : std_logic;
SIGNAL finish_msg : std_logic;
SIGNAL bus_free_cnt : std_logic_vector(3 DOWNTO 0);
SIGNAL bus_free_cnt_en : std_logic;
SIGNAL bus_free : std_logic;
SIGNAL waiting_for_bus_free : std_logic;
SIGNAL node_bus_off_q : std_logic;
SIGNAL ack_err_latched : std_logic;
SIGNAL bit_err_latched : std_logic;
SIGNAL stuff_err_latched : std_logic;
SIGNAL form_err_latched : std_logic;
SIGNAL rule3_exc1_1 : std_logic;
SIGNAL rule3_exc1_2 : std_logic;
SIGNAL suspend : std_logic;
SIGNAL susp_cnt_en : std_logic;
SIGNAL susp_cnt : std_logic_vector(2 DOWNTO 0);
SIGNAL error_flag_over_latched : std_logic;
SIGNAL error_capture_code_type : std_logic_vector(7 DOWNTO 6);
SIGNAL error_capture_code_blocked : std_logic;
SIGNAL first_compare_bit : std_logic;
SIGNAL error_capture_code_segment : std_logic_vector(4 DOWNTO 0);
SIGNAL error_capture_code_direction : std_logic;
SIGNAL bit_de_stuff : std_logic;
SIGNAL bit_de_stuff_tx : std_logic;
SIGNAL rule5 : std_logic;
-- Rx state machine
SIGNAL go_rx_idle : std_logic;
SIGNAL go_rx_id1 : std_logic;
SIGNAL go_rx_rtr1 : std_logic;
SIGNAL go_rx_ide : std_logic;
SIGNAL go_rx_id2 : std_logic;
SIGNAL go_rx_rtr2 : std_logic;
SIGNAL go_rx_r1 : std_logic;
SIGNAL go_rx_r0 : std_logic;
SIGNAL go_rx_dlc : std_logic;
SIGNAL go_rx_data : std_logic;
SIGNAL go_rx_crc : std_logic;
SIGNAL go_rx_crc_lim : std_logic;
SIGNAL go_rx_ack : std_logic;
SIGNAL go_rx_ack_lim : std_logic;
SIGNAL go_rx_eof : std_logic;
SIGNAL last_bit_of_inter : std_logic;
SIGNAL go_crc_enable : std_logic;
SIGNAL rst_crc_enable : std_logic;
SIGNAL bit_de_stuff_set : std_logic;
SIGNAL bit_de_stuff_reset : std_logic;
SIGNAL go_early_tx : std_logic;
SIGNAL calculated_crc : std_logic_vector(14 DOWNTO 0);
SIGNAL r_calculated_crc : std_logic_vector(15 DOWNTO 0);
SIGNAL remote_rq : std_logic;
SIGNAL limited_data_len : std_logic_vector(3 DOWNTO 0);
SIGNAL form_err : std_logic;
SIGNAL error_frame_ended : std_logic;
SIGNAL overload_frame_ended : std_logic;
SIGNAL bit_err : std_logic;
SIGNAL ack_err : std_logic;
SIGNAL stuff_err : std_logic;
SIGNAL id_ok : std_logic; -- If received ID matches ID set in registers
SIGNAL no_byte0 : std_logic; -- There is no byte 0 (RTR bit set to 1 or DLC field equal to 0). Signal used for acceptance filter.
SIGNAL no_byte1 : std_logic; -- There is no byte 1 (RTR bit set to 1 or DLC field equal to 1). Signal used for acceptance filter.
SIGNAL header_len : std_logic_vector(2 DOWNTO 0);
SIGNAL storing_header : std_logic;
SIGNAL limited_data_len_minus1 : std_logic_vector(3 DOWNTO 0);
SIGNAL reset_wr_fifo : std_logic;
SIGNAL err : std_logic;
SIGNAL arbitration_field : std_logic;
SIGNAL basic_chain : std_logic_vector(18 DOWNTO 0);
SIGNAL basic_chain_data : std_logic_vector(63 DOWNTO 0);
SIGNAL extended_chain_std : std_logic_vector(18 DOWNTO 0);
SIGNAL extended_chain_ext : std_logic_vector(38 DOWNTO 0);
SIGNAL extended_chain_data_std : std_logic_vector(63 DOWNTO 0);
SIGNAL extended_chain_data_ext : std_logic_vector(63 DOWNTO 0);
SIGNAL rst_tx_pointer : std_logic;
SIGNAL r_tx_data_0 : std_logic_vector(7 DOWNTO 0);
SIGNAL r_tx_data_1 : std_logic_vector(7 DOWNTO 0);
SIGNAL r_tx_data_2 : std_logic_vector(7 DOWNTO 0);
SIGNAL r_tx_data_3 : std_logic_vector(7 DOWNTO 0);
SIGNAL r_tx_data_4 : std_logic_vector(7 DOWNTO 0);
SIGNAL r_tx_data_5 : std_logic_vector(7 DOWNTO 0);
SIGNAL r_tx_data_6 : std_logic_vector(7 DOWNTO 0);
SIGNAL r_tx_data_7 : std_logic_vector(7 DOWNTO 0);
SIGNAL r_tx_data_8 : std_logic_vector(7 DOWNTO 0);
SIGNAL r_tx_data_9 : std_logic_vector(7 DOWNTO 0);
SIGNAL r_tx_data_10 : std_logic_vector(7 DOWNTO 0);
SIGNAL r_tx_data_11 : std_logic_vector(7 DOWNTO 0);
SIGNAL r_tx_data_12 : std_logic_vector(7 DOWNTO 0);
SIGNAL bit_err_exc1 : std_logic;
SIGNAL bit_err_exc2 : std_logic;
SIGNAL bit_err_exc3 : std_logic;
SIGNAL bit_err_exc4 : std_logic;
SIGNAL bit_err_exc5 : std_logic;
SIGNAL bit_err_exc6 : std_logic;
SIGNAL error_flag_over : std_logic;
SIGNAL overload_flag_over : std_logic;
SIGNAL limited_tx_cnt_ext : std_logic_vector(5 DOWNTO 0);
SIGNAL limited_tx_cnt_std : std_logic_vector(5 DOWNTO 0);
-- port connections for Ram
--64x8
SIGNAL w_q_dp_64x8 : std_logic_vector(7 DOWNTO 0);
SIGNAL w_data_64x8 : std_logic_vector(7 DOWNTO 0);
SIGNAL w_wren_64x8 : std_logic;
SIGNAL w_rden_64x8 : std_logic;
SIGNAL w_wraddress_64x8 : std_logic_vector(5 DOWNTO 0);
SIGNAL w_rdaddress_64x8 : std_logic_vector(5 DOWNTO 0);
--64x4
SIGNAL w_q_dp_64x4 : std_logic_vector(3 DOWNTO 0);
SIGNAL w_data_64x4 : std_logic_vector(3 DOWNTO 0);
SIGNAL w_wren_64x4x1 : std_logic;
SIGNAL w_wraddress_64x4x1 : std_logic_vector(5 DOWNTO 0);
SIGNAL w_rdaddress_64x4x1 : std_logic_vector(5 DOWNTO 0);
--64x1
SIGNAL w_q_dp_64x1 : std_logic;
SIGNAL w_data_64x1 : std_logic;
SIGNAL temp_xhdl47 : std_logic_vector(3 DOWNTO 0);
-- Instantiation of the RX CRC module
SIGNAL xhdl_49 : std_logic;
-- Mode register
-- Clock Divider register
-- This section is for BASIC and EXTENDED mode
-- Acceptance code register
-- Acceptance mask register
-- End: This section is for BASIC and EXTENDED mode
-- This section is for EXTENDED mode
-- Acceptance code register
-- Acceptance mask register
-- End: This section is for EXTENDED mode
SIGNAL port_xhdl73 : std_logic_vector(7 DOWNTO 0);
SIGNAL port_xhdl74 : std_logic_vector(7 DOWNTO 0);
SIGNAL temp_xhdl75 : std_logic_vector(2 DOWNTO 0);
SIGNAL temp_xhdl76 : std_logic_vector(2 DOWNTO 0);
SIGNAL temp_xhdl77 : std_logic_vector(3 DOWNTO 0);
SIGNAL temp_xhdl78 : std_logic_vector(3 DOWNTO 0); -- - 1 because counter counts from 0
SIGNAL xhdl_106 : std_logic_vector(7 DOWNTO 0);
SIGNAL temp_xhdl108 : std_logic_vector(5 DOWNTO 0);
SIGNAL temp_xhdl109 : std_logic_vector(5 DOWNTO 0);
SIGNAL temp_xhdl110 : boolean;
SIGNAL temp_xhdl111 : std_logic;
SIGNAL data_out_xhdl1 : std_logic_vector(7 DOWNTO 0);
SIGNAL tx_state_xhdl2 : std_logic;
SIGNAL tx_state_q_xhdl3 : std_logic;
SIGNAL overload_frame_xhdl4 : std_logic;
SIGNAL error_capture_code_xhdl5 : std_logic_vector(7 DOWNTO 0);
SIGNAL rx_idle_xhdl6 : std_logic;
SIGNAL transmitting_xhdl7 : std_logic;
SIGNAL transmitter_xhdl8 : std_logic;
SIGNAL go_rx_inter_xhdl9 : std_logic;
SIGNAL not_first_bit_of_inter_xhdl10 : std_logic;
SIGNAL rx_inter_xhdl11 : std_logic;
SIGNAL set_reset_mode_xhdl12 : std_logic;
SIGNAL node_bus_off_xhdl13 : std_logic;
SIGNAL error_status_xhdl14 : std_logic;
SIGNAL rx_err_cnt_xhdl15 : std_logic_vector(8 DOWNTO 0);
SIGNAL tx_err_cnt_xhdl16 : std_logic_vector(8 DOWNTO 0);
SIGNAL transmit_status_xhdl17 : std_logic;
SIGNAL receive_status_xhdl18 : std_logic;
SIGNAL tx_successful_xhdl19 : std_logic;
SIGNAL need_to_tx_xhdl20 : std_logic;
SIGNAL overrun_xhdl21 : std_logic;
SIGNAL info_empty_xhdl22 : std_logic;
SIGNAL set_bus_error_irq_xhdl23 : std_logic;
SIGNAL set_arbitration_lost_irq_xhdl24 : std_logic;
SIGNAL arbitration_lost_capture_xhdl25 : std_logic_vector(4 DOWNTO 0);
SIGNAL node_error_passive_xhdl26: std_logic;
SIGNAL node_error_active_xhdl27 : std_logic;
SIGNAL rx_message_counter_xhdl28: std_logic_vector(6 DOWNTO 0);
SIGNAL tx_xhdl29 : std_logic;
SIGNAL tx_next_xhdl30 : std_logic;
SIGNAL bus_off_on_xhdl31 : std_logic;
SIGNAL go_overload_frame_xhdl32 : std_logic;
SIGNAL go_error_frame_xhdl33 : std_logic;
SIGNAL go_tx_xhdl34 : std_logic;
SIGNAL send_ack_xhdl35 : std_logic;
SIGNAL data_64x8_xhdl36 : std_logic_vector(7 DOWNTO 0);
SIGNAL wren_64x8_xhdl37 : std_logic;
SIGNAL rden_64x8_xhdl38 : std_logic;
SIGNAL wraddress_64x8_xhdl39 : std_logic_vector(5 DOWNTO 0);
SIGNAL rdaddress_64x8_xhdl40 : std_logic_vector(5 DOWNTO 0);
SIGNAL data_64x4_xhdl41 : std_logic_vector(3 DOWNTO 0);
SIGNAL wren_64x4x1_xhdl42 : std_logic;
SIGNAL wraddress_64x4x1_xhdl43 : std_logic_vector(5 DOWNTO 0);
SIGNAL rdaddress_64x4x1_xhdl44 : std_logic_vector(5 DOWNTO 0);
SIGNAL data_64x1_xhdl45 : std_logic;
BEGIN
data_out <= data_out_xhdl1;
tx_state <= tx_state_xhdl2;
tx_state_q <= tx_state_q_xhdl3;
overload_frame <= overload_frame_xhdl4;
error_capture_code <= error_capture_code_xhdl5;
rx_idle <= rx_idle_xhdl6;
transmitting <= transmitting_xhdl7;
transmitter <= transmitter_xhdl8;
go_rx_inter <= go_rx_inter_xhdl9;
not_first_bit_of_inter <= not_first_bit_of_inter_xhdl10;
rx_inter <= rx_inter_xhdl11;
set_reset_mode <= set_reset_mode_xhdl12;
node_bus_off <= node_bus_off_xhdl13;
error_status <= error_status_xhdl14;
rx_err_cnt <= rx_err_cnt_xhdl15;
tx_err_cnt <= tx_err_cnt_xhdl16;
transmit_status <= transmit_status_xhdl17;
receive_status <= receive_status_xhdl18;
tx_successful <= tx_successful_xhdl19;
need_to_tx <= need_to_tx_xhdl20;
overrun <= overrun_xhdl21;
info_empty <= info_empty_xhdl22;
set_bus_error_irq <= set_bus_error_irq_xhdl23;
set_arbitration_lost_irq <= set_arbitration_lost_irq_xhdl24;
arbitration_lost_capture <= arbitration_lost_capture_xhdl25;
node_error_passive <= node_error_passive_xhdl26;
node_error_active <= node_error_active_xhdl27;
rx_message_counter <= rx_message_counter_xhdl28;
tx <= tx_xhdl29;
tx_next <= tx_next_xhdl30;
bus_off_on <= bus_off_on_xhdl31;
go_overload_frame <= go_overload_frame_xhdl32;
go_error_frame <= go_error_frame_xhdl33;
go_tx <= go_tx_xhdl34;
send_ack <= send_ack_xhdl35;
data_64x8 <= data_64x8_xhdl36;
wren_64x8 <= wren_64x8_xhdl37;
rden_64x8 <= rden_64x8_xhdl38;
wraddress_64x8 <= wraddress_64x8_xhdl39;
rdaddress_64x8 <= rdaddress_64x8_xhdl40;
data_64x4 <= data_64x4_xhdl41;
wren_64x4x1 <= wren_64x4x1_xhdl42;
wraddress_64x4x1 <= wraddress_64x4x1_xhdl43;
rdaddress_64x4x1 <= rdaddress_64x4x1_xhdl44;
data_64x1 <= data_64x1_xhdl45;
-- port connections for Ram
--64x8
w_q_dp_64x8 <= q_dp_64x8 ;
data_64x8_xhdl36 <= w_data_64x8 ;
wren_64x8_xhdl37 <= w_wren_64x8 ;
rden_64x8_xhdl38 <= w_rden_64x8 ;
wraddress_64x8_xhdl39 <= w_wraddress_64x8 ;
rdaddress_64x8_xhdl40 <= w_rdaddress_64x8 ;
--64x4
w_q_dp_64x4 <= q_dp_64x4 ;
data_64x4_xhdl41 <= w_data_64x4 ;
wren_64x4x1_xhdl42 <= w_wren_64x4x1 ;
wraddress_64x4x1_xhdl43 <= w_wraddress_64x4x1 ;
rdaddress_64x4x1_xhdl44 <= w_rdaddress_64x4x1 ;
--64x1
w_q_dp_64x1 <= q_dp_64x1 ;
data_64x1_xhdl45 <= w_data_64x1 ;
-- ----------------------
go_rx_idle <= ((sample_point AND sampled_bit) AND last_bit_of_inter) OR (bus_free AND (NOT node_bus_off_xhdl13)) ;
go_rx_id1 <= (sample_point AND (NOT sampled_bit)) AND (rx_idle_xhdl6 OR last_bit_of_inter) ;
go_rx_rtr1 <= (((NOT bit_de_stuff) AND sample_point) AND rx_id1) AND CONV_STD_LOGIC(bit_cnt(3 DOWNTO 0) = "1010") ;
go_rx_ide <= ((NOT bit_de_stuff) AND sample_point) AND rx_rtr1 ;
go_rx_id2 <= (((NOT bit_de_stuff) AND sample_point) AND rx_ide) AND sampled_bit ;
go_rx_rtr2 <= (((NOT bit_de_stuff) AND sample_point) AND rx_id2) AND CONV_STD_LOGIC(bit_cnt(4 DOWNTO 0) = "10001") ;
go_rx_r1 <= ((NOT bit_de_stuff) AND sample_point) AND rx_rtr2 ;
go_rx_r0 <= ((NOT bit_de_stuff) AND sample_point) AND ((rx_ide AND (NOT sampled_bit)) OR rx_r1) ;
go_rx_dlc <= ((NOT bit_de_stuff) AND sample_point) AND rx_r0 ;
go_rx_data <= (((((NOT bit_de_stuff) AND sample_point) AND rx_dlc) AND CONV_STD_LOGIC(bit_cnt(1 DOWNTO 0) = "11")) AND (sampled_bit OR (orv(data_len(2 DOWNTO 0))))) AND (NOT remote_rq) ;
--## go_rx_crc <= ((NOT bit_de_stuff) AND sample_point) AND (((rx_dlc AND CONV_STD_LOGIC(bit_cnt(1 DOWNTO 0) = "11")) AND (((NOT sampled_bit) AND (NOT (orv(data_len(2 DOWNTO 0))))) OR remote_rq)) OR (rx_data AND CONV_STD_LOGIC('0' & bit_cnt(5 DOWNTO 0) = ((limited_data_len & "000") - 1)))) ;
go_rx_crc <= ((NOT bit_de_stuff) AND sample_point) AND (((rx_dlc AND CONV_STD_LOGIC(bit_cnt(1 DOWNTO 0) = "11")) AND (((NOT sampled_bit) AND (NOT (orv(data_len(2 DOWNTO 0))))) OR remote_rq)) OR (rx_data AND CONV_STD_LOGIC(('0' & bit_cnt(5 DOWNTO 0)) = ((limited_data_len & "000") - 1)))) ;
go_rx_crc_lim <= (((NOT bit_de_stuff) AND sample_point) AND rx_crc) AND CONV_STD_LOGIC(bit_cnt(3 DOWNTO 0) = "1110") ;
go_rx_ack <= ((NOT bit_de_stuff) AND sample_point) AND rx_crc_lim ;
go_rx_ack_lim <= sample_point AND rx_ack ;
go_rx_eof <= sample_point AND rx_ack_lim ;
go_rx_inter_xhdl9 <= (((sample_point AND rx_eof) AND CONV_STD_LOGIC(eof_cnt = "110")) OR error_frame_ended OR overload_frame_ended) AND (NOT overload_request) ;
go_error_frame_xhdl33 <= form_err OR stuff_err OR bit_err OR ack_err OR (crc_err AND go_rx_eof) ;
error_frame_ended <= CONV_STD_LOGIC(error_cnt2 = "111") AND tx_point ;
overload_frame_ended <= CONV_STD_LOGIC(overload_cnt2 = "111") AND tx_point ;
go_overload_frame_xhdl32 <= (((sample_point AND ((NOT sampled_bit) OR overload_request)) AND (((rx_eof AND (NOT transmitter_xhdl8)) AND CONV_STD_LOGIC(eof_cnt = "110")) OR error_frame_ended OR overload_frame_ended)) OR (((sample_point AND (NOT sampled_bit)) AND rx_inter_xhdl11) AND CONV_STD_LOGIC(bit_cnt(1 DOWNTO 0) < "10")) OR ((sample_point AND (NOT sampled_bit)) AND CONV_STD_LOGIC((error_cnt2 = "111") OR (overload_cnt2 = "111")))) AND (NOT overload_frame_blocked) ;
go_crc_enable <= hard_sync OR go_tx_xhdl34 ;
rst_crc_enable <= go_rx_crc ;
bit_de_stuff_set <= go_rx_id1 AND (NOT go_error_frame_xhdl33) ;
bit_de_stuff_reset <= go_rx_ack OR reset_mode OR go_error_frame_xhdl33 OR go_overload_frame_xhdl32 ;
remote_rq <= ((NOT ide) AND rtr1) OR (ide AND rtr2) ;
temp_xhdl47 <= data_len WHEN (data_len < "1000") ELSE "1000";
limited_data_len <= temp_xhdl47 ;
ack_err <= (((rx_ack AND sample_point) AND sampled_bit) AND tx_state_xhdl2) AND (NOT self_test_mode) ;
bit_err <= ((((((((tx_state_xhdl2 OR error_frame OR overload_frame_xhdl4 OR rx_ack) AND sample_point) AND CONV_STD_LOGIC(tx_xhdl29 /= sampled_bit)) AND (NOT bit_err_exc1)) AND (NOT bit_err_exc2)) AND (NOT bit_err_exc3)) AND (NOT bit_err_exc4)) AND (NOT bit_err_exc5)) AND (NOT bit_err_exc6) ;
bit_err_exc1 <= (tx_state_xhdl2 AND arbitration_field) AND tx_xhdl29 ;
bit_err_exc2 <= rx_ack AND tx_xhdl29 ;
bit_err_exc3 <= (error_frame AND node_error_passive_xhdl26) AND CONV_STD_LOGIC(error_cnt1 < "111") ;
bit_err_exc4 <= ((error_frame AND CONV_STD_LOGIC(error_cnt1 = "111")) AND (NOT enable_error_cnt2)) OR ((overload_frame_xhdl4 AND CONV_STD_LOGIC(overload_cnt1 = "111")) AND (NOT enable_overload_cnt2)) ;
bit_err_exc5 <= (error_frame AND CONV_STD_LOGIC(error_cnt2 = "111")) OR (overload_frame_xhdl4 AND CONV_STD_LOGIC(overload_cnt2 = "111")) ;
bit_err_exc6 <= (CONV_STD_LOGIC(eof_cnt = "110") AND rx_eof) AND (NOT transmitter_xhdl8) ;
arbitration_field <= rx_id1 OR rx_rtr1 OR rx_ide OR rx_id2 OR rx_rtr2 ;
last_bit_of_inter <= rx_inter_xhdl11 AND CONV_STD_LOGIC(bit_cnt(1 DOWNTO 0) = "10") ;
not_first_bit_of_inter_xhdl10 <= rx_inter_xhdl11 AND CONV_STD_LOGIC(bit_cnt(1 DOWNTO 0) /= "00") ;
-- Rx idle state
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
rx_idle_xhdl6 <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR go_rx_id1 OR go_error_frame_xhdl33) = '1') THEN
rx_idle_xhdl6 <= '0' ;
ELSE
IF (go_rx_idle = '1') THEN
rx_idle_xhdl6 <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
-- Rx id1 state
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
rx_id1 <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR go_rx_rtr1 OR go_error_frame_xhdl33) = '1') THEN
rx_id1 <= '0' ;
ELSE
IF (go_rx_id1 = '1') THEN
rx_id1 <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
-- Rx rtr1 state
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
rx_rtr1 <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR go_rx_ide OR go_error_frame_xhdl33) = '1') THEN
rx_rtr1 <= '0' ;
ELSE
IF (go_rx_rtr1 = '1') THEN
rx_rtr1 <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
-- Rx ide state
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
rx_ide <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR go_rx_r0 OR go_rx_id2 OR go_error_frame_xhdl33) = '1') THEN
rx_ide <= '0' ;
ELSE
IF (go_rx_ide = '1') THEN
rx_ide <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
-- Rx id2 state
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
rx_id2 <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR go_rx_rtr2 OR go_error_frame_xhdl33) = '1') THEN
rx_id2 <= '0' ;
ELSE
IF (go_rx_id2 = '1') THEN
rx_id2 <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
-- Rx rtr2 state
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
rx_rtr2 <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR go_rx_r1 OR go_error_frame_xhdl33) = '1') THEN
rx_rtr2 <= '0' ;
ELSE
IF (go_rx_rtr2 = '1') THEN
rx_rtr2 <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
-- Rx r0 state
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
rx_r1 <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR go_rx_r0 OR go_error_frame_xhdl33) = '1') THEN
rx_r1 <= '0' ;
ELSE
IF (go_rx_r1 = '1') THEN
rx_r1 <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
-- Rx r0 state
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
rx_r0 <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR go_rx_dlc OR go_error_frame_xhdl33) = '1') THEN
rx_r0 <= '0' ;
ELSE
IF (go_rx_r0 = '1') THEN
rx_r0 <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
-- Rx dlc state
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
rx_dlc <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR go_rx_data OR go_rx_crc OR go_error_frame_xhdl33) = '1') THEN
rx_dlc <= '0' ;
ELSE
IF (go_rx_dlc = '1') THEN
rx_dlc <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
-- Rx data state
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
rx_data <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR go_rx_crc OR go_error_frame_xhdl33) = '1') THEN
rx_data <= '0' ;
ELSE
IF (go_rx_data = '1') THEN
rx_data <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
-- Rx crc state
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
rx_crc <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR go_rx_crc_lim OR go_error_frame_xhdl33) = '1') THEN
rx_crc <= '0' ;
ELSE
IF (go_rx_crc = '1') THEN
rx_crc <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
-- Rx crc delimiter state
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
rx_crc_lim <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR go_rx_ack OR go_error_frame_xhdl33) = '1') THEN
rx_crc_lim <= '0' ;
ELSE
IF (go_rx_crc_lim = '1') THEN
rx_crc_lim <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
-- Rx ack state
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
rx_ack <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR go_rx_ack_lim OR go_error_frame_xhdl33) = '1') THEN
rx_ack <= '0' ;
ELSE
IF (go_rx_ack = '1') THEN
rx_ack <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
-- Rx ack delimiter state
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
rx_ack_lim <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR go_rx_eof OR go_error_frame_xhdl33) = '1') THEN
rx_ack_lim <= '0' ;
ELSE
IF (go_rx_ack_lim = '1') THEN
rx_ack_lim <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
-- Rx eof state
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
rx_eof <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR go_rx_inter_xhdl9 OR go_error_frame_xhdl33 OR go_overload_frame_xhdl32) = '1') THEN
rx_eof <= '0' ;
ELSE
IF (go_rx_eof = '1') THEN
rx_eof <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
-- Interframe space
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
rx_inter_xhdl11 <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR go_rx_idle OR go_rx_id1 OR go_overload_frame_xhdl32 OR go_error_frame_xhdl33) = '1') THEN
rx_inter_xhdl11 <= '0' ;
ELSE
IF (go_rx_inter_xhdl9 = '1') THEN
rx_inter_xhdl11 <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
-- ID register
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
id <= "00000000000000000000000000000";
ELSIF (clk'EVENT AND clk = '1') THEN
IF (reset_mode = '1') THEN
id <= "00000000000000000000000000000";
ELSE
IF (((sample_point AND (rx_id1 OR rx_id2)) AND (NOT bit_de_stuff)) = '1') THEN
id <= id(27 DOWNTO 0) & sampled_bit ;
END IF;
END IF;
END IF;
END PROCESS;
-- rtr1 bit
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
rtr1 <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (reset_mode = '1') THEN
rtr1 <= '0';
ELSE
IF (((sample_point AND rx_rtr1) AND (NOT bit_de_stuff)) = '1') THEN
rtr1 <= sampled_bit ;
END IF;
END IF;
END IF;
END PROCESS;
-- rtr2 bit
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
rtr2 <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (reset_mode = '1') THEN
rtr2 <= '0';
ELSE
IF (((sample_point AND rx_rtr2) AND (NOT bit_de_stuff)) = '1') THEN
rtr2 <= sampled_bit ;
END IF;
END IF;
END IF;
END PROCESS;
-- ide bit
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
ide <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (reset_mode = '1') THEN
ide <= '0';
ELSE
IF (((sample_point AND rx_ide) AND (NOT bit_de_stuff)) = '1') THEN
ide <= sampled_bit ;
END IF;
END IF;
END IF;
END PROCESS;
-- Data length
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
data_len <= "0000";
ELSIF (clk'EVENT AND clk = '1') THEN
IF (reset_mode = '1') THEN
data_len <= "0000";
ELSE
IF (((sample_point AND rx_dlc) AND (NOT bit_de_stuff)) = '1') THEN
data_len <= data_len(2 DOWNTO 0) & sampled_bit ;
END IF;
END IF;
END IF;
END PROCESS;
-- Data
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
tmp_data <= "00000000";
ELSIF (clk'EVENT AND clk = '1') THEN
IF (reset_mode = '1') THEN
tmp_data <= "00000000";
ELSE
IF (((sample_point AND rx_data) AND (NOT bit_de_stuff)) = '1') THEN
tmp_data <= tmp_data(6 DOWNTO 0) & sampled_bit ;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
write_data_to_tmp_fifo <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (reset_mode = '1') THEN
write_data_to_tmp_fifo <= '0';
ELSE
IF ((((sample_point AND rx_data) AND (NOT bit_de_stuff)) AND (andv(bit_cnt(2 DOWNTO 0)))) = '1') THEN
write_data_to_tmp_fifo <= '1' ;
ELSE
write_data_to_tmp_fifo <= '0' ;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
byte_cnt <= "000";
ELSIF (clk'EVENT AND clk = '1') THEN
IF (reset_mode = '1') THEN
byte_cnt <= "000";
ELSE
IF (write_data_to_tmp_fifo = '1') THEN
byte_cnt <= byte_cnt + "001" ;
ELSE
--## IF ((sample_point AND go_rx_crc_lim) = '1') THEN
IF (((sample_point AND go_rx_crc_lim) or rx_dlc) = '1') then --## OpenCores: byte count when recovering from error frame
byte_cnt <= "000" ;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk)
BEGIN
IF (clk'EVENT AND clk = '1') THEN
IF (write_data_to_tmp_fifo = '1') THEN
tmp_fifo(conv_integer(byte_cnt)) <= tmp_data ;
END IF;
END IF;
END PROCESS;
-- CRC
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
crc_in <= "000000000000000";
ELSIF (clk'EVENT AND clk = '1') THEN
IF (reset_mode = '1') THEN
crc_in <= "000000000000000";
ELSE
IF (((sample_point AND rx_crc) AND (NOT bit_de_stuff)) = '1') THEN
crc_in <= crc_in(13 DOWNTO 0) & sampled_bit ;
END IF;
END IF;
END IF;
END PROCESS;
-- bit_cnt
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
bit_cnt <= "000000";
ELSIF (clk'EVENT AND clk = '1') THEN
IF (reset_mode = '1') THEN
bit_cnt <= "000000";
ELSE
IF ((go_rx_id1 OR go_rx_id2 OR go_rx_dlc OR go_rx_data OR go_rx_crc OR go_rx_ack OR go_rx_eof OR go_rx_inter_xhdl9 OR go_error_frame_xhdl33 OR go_overload_frame_xhdl32) = '1') THEN
bit_cnt <= "000000" ;
ELSE
IF ((sample_point AND (NOT bit_de_stuff)) = '1') THEN
bit_cnt <= bit_cnt + "000001" ;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
-- eof_cnt
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
eof_cnt <= "000";
ELSIF (clk'EVENT AND clk = '1') THEN
IF (reset_mode = '1') THEN
eof_cnt <= "000";
ELSE
IF (sample_point = '1') THEN
IF ((go_rx_inter_xhdl9 OR go_error_frame_xhdl33 OR go_overload_frame_xhdl32) = '1') THEN
eof_cnt <= "000" ;
ELSE
IF (rx_eof = '1') THEN
eof_cnt <= eof_cnt + "001" ;
END IF;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
-- Enabling bit de-stuffing
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
bit_stuff_cnt_en <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (reset_mode = '1') THEN
bit_stuff_cnt_en <= '0';
ELSE
IF (bit_de_stuff_set = '1') THEN
bit_stuff_cnt_en <= '1' ;
ELSE
IF (bit_de_stuff_reset = '1') THEN
bit_stuff_cnt_en <= '0' ;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
-- bit_stuff_cnt
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
bit_stuff_cnt <= "001";
ELSIF (clk'EVENT AND clk = '1') THEN
IF (reset_mode = '1') THEN
bit_stuff_cnt <= "001";
ELSE
IF (bit_de_stuff_reset = '1') THEN
bit_stuff_cnt <= "001" ;
ELSE
IF ((sample_point AND bit_stuff_cnt_en) = '1') THEN
IF (bit_stuff_cnt = "101") THEN
bit_stuff_cnt <= "001" ;
ELSE
IF (sampled_bit = sampled_bit_q) THEN
bit_stuff_cnt <= bit_stuff_cnt + "001" ;
ELSE
bit_stuff_cnt <= "001" ;
END IF;
END IF;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
-- bit_stuff_cnt_tx
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
bit_stuff_cnt_tx <= "001";
ELSIF (clk'EVENT AND clk = '1') THEN
IF (reset_mode = '1') THEN
bit_stuff_cnt_tx <= "001";
ELSE
IF (bit_de_stuff_reset = '1') THEN
bit_stuff_cnt_tx <= "001" ;
ELSE
IF ((tx_point_q AND bit_stuff_cnt_en) = '1') THEN
IF (bit_stuff_cnt_tx = "101") THEN
bit_stuff_cnt_tx <= "001" ;
ELSE
IF (tx_xhdl29 = tx_q) THEN
bit_stuff_cnt_tx <= bit_stuff_cnt_tx + "001" ;
ELSE
bit_stuff_cnt_tx <= "001" ;
END IF;
END IF;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
bit_de_stuff <= CONV_STD_LOGIC(bit_stuff_cnt = "101") ;
bit_de_stuff_tx <= CONV_STD_LOGIC(bit_stuff_cnt_tx = "101") ;
-- stuff_err
stuff_err <= ((sample_point AND bit_stuff_cnt_en) AND bit_de_stuff) AND CONV_STD_LOGIC(sampled_bit = sampled_bit_q) ;
-- Generating delayed signals
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
reset_mode_q <= '0' ;
node_bus_off_q <= '0' ;
ELSIF (clk'EVENT AND clk = '1') THEN
reset_mode_q <= reset_mode ;
node_bus_off_q <= node_bus_off_xhdl13 ;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
crc_enable <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR rst_crc_enable) = '1') THEN
crc_enable <= '0' ;
ELSE
IF (go_crc_enable = '1') THEN
crc_enable <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
-- CRC error generation
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
crc_err <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR error_frame_ended) = '1') THEN
crc_err <= '0' ;
ELSE
IF (go_rx_ack = '1') THEN
crc_err <= CONV_STD_LOGIC(crc_in /= calculated_crc) ;
END IF;
END IF;
END IF;
END PROCESS;
-- Conditions for form error
form_err <= sample_point AND ((((NOT bit_de_stuff) AND rx_crc_lim) AND (NOT sampled_bit)) OR (rx_ack_lim AND (NOT sampled_bit)) OR (((CONV_STD_LOGIC(eof_cnt < "110") AND rx_eof) AND (NOT sampled_bit)) AND (NOT transmitter_xhdl8)) OR (((rx_eof) AND (NOT sampled_bit)) AND transmitter_xhdl8)) ;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
ack_err_latched <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR error_frame_ended OR go_overload_frame_xhdl32) = '1') THEN
ack_err_latched <= '0' ;
ELSE
IF (ack_err = '1') THEN
ack_err_latched <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
bit_err_latched <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR error_frame_ended OR go_overload_frame_xhdl32) = '1') THEN
bit_err_latched <= '0' ;
ELSE
IF (bit_err = '1') THEN
bit_err_latched <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
-- Rule 5 (Fault confinement).
rule5 <= bit_err AND ((((NOT node_error_passive_xhdl26) AND error_frame) AND CONV_STD_LOGIC(error_cnt1 < "111")) OR (overload_frame_xhdl4 AND CONV_STD_LOGIC(overload_cnt1 < "111"))) ;
-- Rule 3 exception 1 - first part (Fault confinement).
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
rule3_exc1_1 <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR error_flag_over OR rule3_exc1_2) = '1') THEN
rule3_exc1_1 <= '0' ;
ELSE
IF (((transmitter_xhdl8 AND node_error_passive_xhdl26) AND ack_err) = '1') THEN
rule3_exc1_1 <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
-- Rule 3 exception 1 - second part (Fault confinement).
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
rule3_exc1_2 <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR go_error_frame_xhdl33 OR rule3_exc1_2) = '1') THEN
rule3_exc1_2 <= '0' ;
ELSE
IF ((((rule3_exc1_1 AND CONV_STD_LOGIC(error_cnt1 < "111")) AND sample_point) AND (NOT sampled_bit)) = '1') THEN
rule3_exc1_2 <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
stuff_err_latched <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR error_frame_ended OR go_overload_frame_xhdl32) = '1') THEN
stuff_err_latched <= '0' ;
ELSE
IF (stuff_err = '1') THEN
stuff_err_latched <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
form_err_latched <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR error_frame_ended OR go_overload_frame_xhdl32) = '1') THEN
form_err_latched <= '0' ;
ELSE
IF (form_err = '1') THEN
form_err_latched <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
xhdl_49 <= ((crc_enable AND sample_point) AND (NOT bit_de_stuff));
i_can_crc_rx : can_crc
PORT MAP (
clk => clk,
data => sampled_bit,
enable => xhdl_49,
initialize => go_crc_enable,
crc => calculated_crc);
no_byte0 <= rtr1 OR CONV_STD_LOGIC(data_len < "0001") ;
no_byte1 <= rtr1 OR CONV_STD_LOGIC(data_len < "0010") ;
port_xhdl73 <= tmp_fifo(0);
port_xhdl74 <= tmp_fifo(1);
i_can_acf : can_acf
PORT MAP (
clk => clk,
rst => rst,
id => id,
reset_mode => reset_mode,
acceptance_filter_mode => acceptance_filter_mode,
extended_mode => extended_mode,
acceptance_code_0 => acceptance_code_0,
acceptance_mask_0 => acceptance_mask_0,
acceptance_code_1 => acceptance_code_1,
acceptance_code_2 => acceptance_code_2,
acceptance_code_3 => acceptance_code_3,
acceptance_mask_1 => acceptance_mask_1,
acceptance_mask_2 => acceptance_mask_2,
acceptance_mask_3 => acceptance_mask_3,
go_rx_crc_lim => go_rx_crc_lim,
go_rx_inter => go_rx_inter_xhdl9,
go_error_frame => go_error_frame_xhdl33,
data0 => port_xhdl73,
data1 => port_xhdl74,
rtr1 => rtr1,
rtr2 => rtr2,
ide => ide,
no_byte0 => no_byte0,
no_byte1 => no_byte1,
id_ok => id_ok);
temp_xhdl75 <= "101" WHEN ide = '1' ELSE "011";
temp_xhdl76 <= (temp_xhdl75) WHEN extended_mode = '1' ELSE "010";
header_len(2 DOWNTO 0) <= temp_xhdl76 ;
storing_header <= CONV_STD_LOGIC(header_cnt < header_len) ;
temp_xhdl77 <= (data_len - "0001") WHEN (data_len < "1000") ELSE "0111";
temp_xhdl78 <= "1111" WHEN remote_rq = '1' ELSE (temp_xhdl77);
limited_data_len_minus1(3 DOWNTO 0) <= temp_xhdl78 ;
reset_wr_fifo <= CONV_STD_LOGIC(data_cnt = (limited_data_len_minus1 + ('0' & header_len))) OR reset_mode ;
err <= form_err OR stuff_err OR bit_err OR ack_err OR form_err_latched OR stuff_err_latched OR bit_err_latched OR ack_err_latched OR crc_err ;
-- Write enable signal for 64-byte rx fifo
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
wr_fifo <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (reset_wr_fifo = '1') THEN
wr_fifo <= '0' ;
ELSE
IF ((((go_rx_inter_xhdl9 AND id_ok) AND (NOT error_frame_ended)) AND ((NOT tx_state_xhdl2) OR self_rx_request)) = '1') THEN
wr_fifo <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
-- Header counter. Header length depends on the mode of operation and frame format.
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
header_cnt <= "000";
ELSIF (clk'EVENT AND clk = '1') THEN
IF (reset_wr_fifo = '1') THEN
header_cnt <= "000" ;
ELSE
IF ((wr_fifo AND storing_header) = '1') THEN
header_cnt <= header_cnt + "001" ;
END IF;
END IF;
END IF;
END PROCESS;
-- Data counter. Length of the data is limited to 8 bytes.
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
data_cnt <= "0000";
ELSIF (clk'EVENT AND clk = '1') THEN
IF (reset_wr_fifo = '1') THEN
data_cnt <= "0000" ;
ELSE
IF (wr_fifo = '1') THEN
data_cnt <= data_cnt + "0001" ;
END IF;
END IF;
END IF;
END PROCESS;
-- Multiplexing data that is stored to 64-byte fifo depends on the mode of operation and frame format
PROCESS (extended_mode, ide, data_cnt, header_cnt, header_len, storing_header, id, rtr1, rtr2, data_len, tmp_fifo)
VARIABLE data_for_fifo_xhdl79 : std_logic_vector(7 DOWNTO 0);
VARIABLE temp_xhdl80 : std_logic_vector(5 DOWNTO 0);
BEGIN
temp_xhdl80 := storing_header & extended_mode & ide & header_cnt;
IF (std_match(temp_xhdl80, "111000")) THEN
data_for_fifo_xhdl79 := '1' & rtr2 & "00" & data_len; -- extended mode, extended format header
ELSIF (std_match(temp_xhdl80, "111001")) THEN
data_for_fifo_xhdl79 := id(28 DOWNTO 21); -- extended mode, extended format header
ELSIF (std_match(temp_xhdl80, "111010")) THEN
data_for_fifo_xhdl79 := id(20 DOWNTO 13); -- extended mode, extended format header
ELSIF (std_match(temp_xhdl80, "111011")) THEN
data_for_fifo_xhdl79 := id(12 DOWNTO 5); -- extended mode, extended format header
ELSIF (std_match(temp_xhdl80, "111100")) THEN
data_for_fifo_xhdl79 := id(4 DOWNTO 0) & rtr2 & "00"; -- extended mode, extended format header
ELSIF (std_match(temp_xhdl80, "110000")) THEN
data_for_fifo_xhdl79 := '0' & rtr1 & "00" & data_len; -- extended mode, standard format header
ELSIF (std_match(temp_xhdl80, "110001")) THEN
data_for_fifo_xhdl79 := id(10 DOWNTO 3); -- extended mode, standard format header
ELSIF (std_match(temp_xhdl80, "110010")) THEN
data_for_fifo_xhdl79 := id(2 DOWNTO 0) & rtr1 & "0000"; -- extended mode, standard format header
ELSIF (std_match(temp_xhdl80, "10-000")) THEN
data_for_fifo_xhdl79 := id(10 DOWNTO 3); -- normal mode header
ELSIF (std_match(temp_xhdl80, "10-001")) THEN
data_for_fifo_xhdl79 := id(2 DOWNTO 0) & rtr1 & data_len; -- normal mode header
ELSE
data_for_fifo_xhdl79 := tmp_fifo(conv_integer(data_cnt - ('0' & header_len)) mod 8); -- data
END IF;
data_for_fifo <= data_for_fifo_xhdl79;
END PROCESS;
-- Instantiation of the RX fifo module
-- port connections for Ram
--64x8
--64x4
--64x1
i_can_fifo : can_fifo
PORT MAP (
clk => clk,
rst => rst,
wr => wr_fifo,
data_in => data_for_fifo,
addr => addr(5 DOWNTO 0),
data_out => data_out_xhdl1,
fifo_selected => fifo_selected,
reset_mode => reset_mode,
release_buffer => release_buffer,
extended_mode => extended_mode,
overrun => overrun_xhdl21,
info_empty => info_empty_xhdl22,
info_cnt => rx_message_counter_xhdl28,
q_dp_64x8 => w_q_dp_64x8,
data_64x8 => w_data_64x8,
wren_64x8 => w_wren_64x8,
rden_64x8 => w_rden_64x8,
wraddress_64x8 => w_wraddress_64x8,
rdaddress_64x8 => w_rdaddress_64x8,
q_dp_64x4 => w_q_dp_64x4,
data_64x4 => w_data_64x4,
wren_64x4x1 => w_wren_64x4x1,
wraddress_64x4x1 => w_wraddress_64x4x1,
rdaddress_64x4x1 => w_rdaddress_64x4x1,
q_dp_64x1 => w_q_dp_64x1,
data_64x1 => w_data_64x1);
-- Transmitting error frame.
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
error_frame <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR error_frame_ended OR go_overload_frame_xhdl32) = '1') THEN
error_frame <= '0' ;
ELSE
IF (go_error_frame_xhdl33 = '1') THEN
error_frame <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
error_cnt1 <= "000";
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR error_frame_ended OR go_error_frame_xhdl33 OR go_overload_frame_xhdl32) = '1') THEN
error_cnt1 <= "000" ;
ELSE
IF (((error_frame AND tx_point) AND CONV_STD_LOGIC(error_cnt1 < "111")) = '1') THEN
error_cnt1 <= error_cnt1 + "001" ;
END IF;
END IF;
END IF;
END PROCESS;
error_flag_over <= ((((NOT node_error_passive_xhdl26) AND sample_point) AND CONV_STD_LOGIC(error_cnt1 = "111")) OR ((node_error_passive_xhdl26 AND sample_point) AND CONV_STD_LOGIC(passive_cnt = "110"))) AND (NOT enable_error_cnt2) ;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
error_flag_over_latched <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR error_frame_ended OR go_error_frame_xhdl33 OR go_overload_frame_xhdl32) = '1') THEN
error_flag_over_latched <= '0' ;
ELSE
IF (error_flag_over = '1') THEN
error_flag_over_latched <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
enable_error_cnt2 <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR error_frame_ended OR go_error_frame_xhdl33 OR go_overload_frame_xhdl32) = '1') THEN
enable_error_cnt2 <= '0' ;
ELSE
IF ((error_frame AND (error_flag_over AND sampled_bit)) = '1') THEN
enable_error_cnt2 <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
error_cnt2 <= "000";
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR error_frame_ended OR go_error_frame_xhdl33 OR go_overload_frame_xhdl32) = '1') THEN
error_cnt2 <= "000" ;
ELSE
IF ((enable_error_cnt2 AND tx_point) = '1') THEN
error_cnt2 <= error_cnt2 + "001" ;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
delayed_dominant_cnt <= "000";
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR enable_error_cnt2 OR go_error_frame_xhdl33 OR enable_overload_cnt2 OR go_overload_frame_xhdl32) = '1') THEN
delayed_dominant_cnt <= "000" ;
ELSE
IF (((sample_point AND (NOT sampled_bit)) AND CONV_STD_LOGIC((error_cnt1 = "111") OR (overload_cnt1 = "111"))) = '1') THEN
delayed_dominant_cnt <= delayed_dominant_cnt + "001" ;
END IF;
END IF;
END IF;
END PROCESS;
-- passive_cnt
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
passive_cnt <= "001";
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR error_frame_ended OR go_error_frame_xhdl33 OR go_overload_frame_xhdl32 OR first_compare_bit) = '1') THEN
passive_cnt <= "001" ;
ELSE
IF ((sample_point AND CONV_STD_LOGIC(passive_cnt < "110")) = '1') THEN
IF (((error_frame AND (NOT enable_error_cnt2)) AND CONV_STD_LOGIC(sampled_bit = sampled_bit_q)) = '1') THEN
passive_cnt <= passive_cnt + "001" ;
ELSE
passive_cnt <= "001" ;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
-- When comparing 6 equal bits, first is always equal
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
first_compare_bit <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (go_error_frame_xhdl33 = '1') THEN
first_compare_bit <= '1' ;
ELSE
IF (sample_point = '1') THEN
first_compare_bit <= '0';
END IF;
END IF;
END IF;
END PROCESS;
-- Transmitting overload frame.
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
overload_frame_xhdl4 <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR overload_frame_ended OR go_error_frame_xhdl33) = '1') THEN
overload_frame_xhdl4 <= '0' ;
ELSE
IF (go_overload_frame_xhdl32 = '1') THEN
overload_frame_xhdl4 <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
overload_cnt1 <= "000";
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR overload_frame_ended OR go_error_frame_xhdl33 OR go_overload_frame_xhdl32) = '1') THEN
overload_cnt1 <= "000" ;
ELSE
IF (((overload_frame_xhdl4 AND tx_point) AND CONV_STD_LOGIC(overload_cnt1 < "111")) = '1') THEN
overload_cnt1 <= overload_cnt1 + "001" ;
END IF;
END IF;
END IF;
END PROCESS;
overload_flag_over <= (sample_point AND CONV_STD_LOGIC(overload_cnt1 = "111")) AND (NOT enable_overload_cnt2) ;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
enable_overload_cnt2 <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR overload_frame_ended OR go_error_frame_xhdl33 OR go_overload_frame_xhdl32) = '1') THEN
enable_overload_cnt2 <= '0' ;
ELSE
IF ((overload_frame_xhdl4 AND (overload_flag_over AND sampled_bit)) = '1') THEN
enable_overload_cnt2 <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
overload_cnt2 <= "000";
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR overload_frame_ended OR go_error_frame_xhdl33 OR go_overload_frame_xhdl32) = '1') THEN
overload_cnt2 <= "000" ;
ELSE
IF ((enable_overload_cnt2 AND tx_point) = '1') THEN
overload_cnt2 <= overload_cnt2 + "001" ;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
overload_request_cnt <= "00";
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR go_error_frame_xhdl33 OR go_rx_id1) = '1') THEN
overload_request_cnt <= "00" ;
ELSE
IF ((overload_request AND overload_frame_xhdl4) = '1') THEN
overload_request_cnt <= overload_request_cnt + "01" ;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
overload_frame_blocked <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR go_error_frame_xhdl33 OR go_rx_id1) = '1') THEN
overload_frame_blocked <= '0' ;
ELSE
IF (((overload_request AND overload_frame_xhdl4) AND CONV_STD_LOGIC(overload_request_cnt = "10")) = '1') THEN
-- This is a second sequential overload_request
overload_frame_blocked <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
send_ack_xhdl35 <= (((NOT tx_state_xhdl2) AND rx_ack) AND (NOT err)) AND (NOT listen_only_mode) ;
PROCESS (reset_mode, node_bus_off_xhdl13, tx_state_xhdl2, go_tx_xhdl34, bit_de_stuff_tx, tx_bit, tx_q, send_ack_xhdl35, go_overload_frame_xhdl32, overload_frame_xhdl4, overload_cnt1, go_error_frame_xhdl33, error_frame, error_cnt1, node_error_passive_xhdl26)
VARIABLE tx_next_xhdl30_xhdl105 : std_logic;
BEGIN
IF ((reset_mode OR node_bus_off_xhdl13) = '1') THEN
-- Reset or node_bus_off
tx_next_xhdl30_xhdl105 := '1';
ELSE
IF ((go_error_frame_xhdl33 OR error_frame) = '1') THEN
-- Transmitting error frame
IF (error_cnt1 < "110") THEN
IF (node_error_passive_xhdl26 = '1') THEN
tx_next_xhdl30_xhdl105 := '1';
ELSE
tx_next_xhdl30_xhdl105 := '0';
END IF;
ELSE
tx_next_xhdl30_xhdl105 := '1';
END IF;
ELSE
IF ((go_overload_frame_xhdl32 OR overload_frame_xhdl4) = '1') THEN
-- Transmitting overload frame
IF (overload_cnt1 < "110") THEN
tx_next_xhdl30_xhdl105 := '0';
ELSE
tx_next_xhdl30_xhdl105 := '1';
END IF;
ELSE
IF ((go_tx_xhdl34 OR tx_state_xhdl2) = '1') THEN
-- Transmitting message
tx_next_xhdl30_xhdl105 := ((NOT bit_de_stuff_tx) AND tx_bit) OR (bit_de_stuff_tx AND (NOT tx_q));
ELSE
IF (send_ack_xhdl35 = '1') THEN
-- Acknowledge
tx_next_xhdl30_xhdl105 := '0';
ELSE
tx_next_xhdl30_xhdl105 := '1';
END IF;
END IF;
END IF;
END IF;
END IF;
tx_next_xhdl30 <= tx_next_xhdl30_xhdl105;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
tx_xhdl29 <= '1';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (reset_mode = '1') THEN
tx_xhdl29 <= '1';
ELSE
IF (tx_point = '1') THEN
tx_xhdl29 <= tx_next_xhdl30 ;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
tx_q <= '0' ;
ELSIF (clk'EVENT AND clk = '1') THEN
IF (reset_mode = '1') THEN
tx_q <= '0' ;
ELSE
IF (tx_point = '1') THEN
tx_q <= tx_xhdl29 AND (NOT go_early_tx_latched) ;
END IF;
END IF;
END IF;
END PROCESS;
-- Delayed tx point
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
tx_point_q <= '0' ;
ELSIF (clk'EVENT AND clk = '1') THEN
IF (reset_mode = '1') THEN
tx_point_q <= '0' ;
ELSE
tx_point_q <= tx_point ;
END IF;
END IF;
END PROCESS;
-- Changing bit order from [7:0] to [0:7]
i_ibo_tx_data_0 : can_ibo
PORT MAP (
di => tx_data_0,
do => r_tx_data_0);
i_ibo_tx_data_1 : can_ibo
PORT MAP (
di => tx_data_1,
do => r_tx_data_1);
i_ibo_tx_data_2 : can_ibo
PORT MAP (
di => tx_data_2,
do => r_tx_data_2);
i_ibo_tx_data_3 : can_ibo
PORT MAP (
di => tx_data_3,
do => r_tx_data_3);
i_ibo_tx_data_4 : can_ibo
PORT MAP (
di => tx_data_4,
do => r_tx_data_4);
i_ibo_tx_data_5 : can_ibo
PORT MAP (
di => tx_data_5,
do => r_tx_data_5);
i_ibo_tx_data_6 : can_ibo
PORT MAP (
di => tx_data_6,
do => r_tx_data_6);
i_ibo_tx_data_7 : can_ibo
PORT MAP (
di => tx_data_7,
do => r_tx_data_7);
i_ibo_tx_data_8 : can_ibo
PORT MAP (
di => tx_data_8,
do => r_tx_data_8);
i_ibo_tx_data_9 : can_ibo
PORT MAP (
di => tx_data_9,
do => r_tx_data_9);
i_ibo_tx_data_10 : can_ibo
PORT MAP (
di => tx_data_10,
do => r_tx_data_10);
i_ibo_tx_data_11 : can_ibo
PORT MAP (
di => tx_data_11,
do => r_tx_data_11);
i_ibo_tx_data_12 : can_ibo
PORT MAP (
di => tx_data_12,
do => r_tx_data_12);
-- Changing bit order from [14:0] to [0:14]
i_calculated_crc0 : can_ibo
PORT MAP (
di => calculated_crc(14 DOWNTO 7),
do => r_calculated_crc(7 DOWNTO 0));
xhdl_106 <= calculated_crc(6 DOWNTO 0) & '0';
i_calculated_crc1 : can_ibo
PORT MAP (
di => xhdl_106,
do => r_calculated_crc(15 DOWNTO 8));
basic_chain <= r_tx_data_1(7 DOWNTO 4) & "00" & r_tx_data_1(3 DOWNTO 0) & r_tx_data_0(7 DOWNTO 0) & '0' ;
basic_chain_data <= r_tx_data_9 & r_tx_data_8 & r_tx_data_7 & r_tx_data_6 & r_tx_data_5 & r_tx_data_4 & r_tx_data_3 & r_tx_data_2 ;
extended_chain_std <= r_tx_data_0(7 DOWNTO 4) & "00" & r_tx_data_0(1) & r_tx_data_2(2 DOWNTO 0) & r_tx_data_1(7 DOWNTO 0) & '0' ;
extended_chain_ext <= r_tx_data_0(7 DOWNTO 4) & "00" & r_tx_data_0(1) & r_tx_data_4(4 DOWNTO 0) & r_tx_data_3(7 DOWNTO 0) & r_tx_data_2(7 DOWNTO 3) & '1' & '1' & r_tx_data_2(2 DOWNTO 0) & r_tx_data_1(7 DOWNTO 0) & '0' ;
extended_chain_data_std <= r_tx_data_10 & r_tx_data_9 & r_tx_data_8 & r_tx_data_7 & r_tx_data_6 & r_tx_data_5 & r_tx_data_4 & r_tx_data_3 ;
extended_chain_data_ext <= r_tx_data_12 & r_tx_data_11 & r_tx_data_10 & r_tx_data_9 & r_tx_data_8 & r_tx_data_7 & r_tx_data_6 & r_tx_data_5 ;
PROCESS (extended_mode, rx_data, tx_pointer, extended_chain_data_std, extended_chain_data_ext, rx_crc, r_calculated_crc, r_tx_data_0, extended_chain_ext, extended_chain_std, basic_chain_data, basic_chain, finish_msg)
VARIABLE tx_bit_xhdl107 : std_logic;
BEGIN
IF (extended_mode = '1') THEN
IF (rx_data = '1') THEN
-- data stage
IF (r_tx_data_0(0) = '1') THEN
-- Extended frame
tx_bit_xhdl107 := extended_chain_data_ext(conv_integer(tx_pointer));
ELSE
tx_bit_xhdl107 := extended_chain_data_std(conv_integer(tx_pointer));
END IF;
ELSE
IF (rx_crc = '1') THEN
tx_bit_xhdl107 := r_calculated_crc(conv_integer(tx_pointer(3 downto 0)));
ELSE
IF (finish_msg = '1') THEN
tx_bit_xhdl107 := '1';
ELSE
IF (r_tx_data_0(0) = '1') THEN
-- Extended frame
tx_bit_xhdl107 := extended_chain_ext(conv_integer(tx_pointer));
ELSE
tx_bit_xhdl107 := extended_chain_std(conv_integer(tx_pointer));
END IF;
END IF;
END IF;
END IF;
ELSE
-- Basic mode
IF (rx_data = '1') THEN
-- data stage
tx_bit_xhdl107 := basic_chain_data(conv_integer(tx_pointer));
ELSE
IF (rx_crc = '1') THEN
tx_bit_xhdl107 := r_calculated_crc(conv_integer(tx_pointer));
ELSE
IF (finish_msg = '1') THEN
tx_bit_xhdl107 := '1';
ELSE
tx_bit_xhdl107 := basic_chain(conv_integer(tx_pointer));
END IF;
END IF;
END IF;
END IF;
tx_bit <= tx_bit_xhdl107;
END PROCESS;
temp_xhdl108 <= "111111" WHEN tx_data_0(3) = '1' ELSE ((tx_data_0(2 DOWNTO 0) & "000") - 1);
limited_tx_cnt_ext <= temp_xhdl108 ;
temp_xhdl109 <= "111111" WHEN tx_data_1(3) = '1' ELSE ((tx_data_1(2 DOWNTO 0) & "000") - 1);
limited_tx_cnt_std <= temp_xhdl109 ;
-- arbitration + control for extended format
-- arbitration + control for extended format
-- arbitration + control for standard format
-- data (overflow is OK here)
-- data (overflow is OK here)
-- crc
-- at the end
rst_tx_pointer <= ((((((NOT bit_de_stuff_tx) AND tx_point) AND (NOT rx_data)) AND extended_mode) AND r_tx_data_0(0)) AND CONV_STD_LOGIC(tx_pointer = "100110")) OR ((((((NOT bit_de_stuff_tx) AND tx_point) AND (NOT rx_data)) AND extended_mode) AND (NOT r_tx_data_0(0))) AND CONV_STD_LOGIC(tx_pointer = "010010")) OR (((((NOT bit_de_stuff_tx) AND tx_point) AND (NOT rx_data)) AND (NOT extended_mode)) AND CONV_STD_LOGIC(tx_pointer = "010010")) OR (((((NOT bit_de_stuff_tx) AND tx_point) AND rx_data) AND extended_mode) AND CONV_STD_LOGIC(tx_pointer = limited_tx_cnt_ext)) OR (((((NOT bit_de_stuff_tx) AND tx_point) AND rx_data) AND (NOT extended_mode)) AND CONV_STD_LOGIC(tx_pointer = limited_tx_cnt_std)) OR (tx_point AND rx_crc_lim) OR (go_rx_idle) OR (reset_mode) OR (overload_frame_xhdl4) OR (error_frame) ;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
tx_pointer <= "000000";
ELSIF (clk'EVENT AND clk = '1') THEN
IF (rst_tx_pointer = '1') THEN
tx_pointer <= "000000" ;
ELSE
IF ((go_early_tx OR ((tx_point AND (tx_state_xhdl2 OR go_tx_xhdl34)) AND (NOT bit_de_stuff_tx))) = '1') THEN
tx_pointer <= tx_pointer + "000001" ;
END IF;
END IF;
END IF;
END PROCESS;
tx_successful_xhdl19 <= ((((transmitter_xhdl8 AND go_rx_inter_xhdl9) AND (NOT go_error_frame_xhdl33)) AND (NOT error_frame_ended)) AND (NOT overload_frame_ended)) AND (NOT arbitration_lost) ;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
need_to_tx_xhdl20 <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((tx_successful_xhdl19 OR reset_mode OR (abort_tx AND (NOT transmitting_xhdl7)) OR (((NOT tx_state_xhdl2) AND tx_state_q_xhdl3) AND single_shot_transmission)) = '1') THEN
need_to_tx_xhdl20 <= '0' ;
ELSE
IF ((tx_request AND sample_point) = '1') THEN
need_to_tx_xhdl20 <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
go_early_tx <= ((((((NOT listen_only_mode) AND need_to_tx_xhdl20) AND (NOT tx_state_xhdl2)) AND (NOT suspend OR CONV_STD_LOGIC(susp_cnt = "111"))) AND sample_point) AND (NOT sampled_bit)) AND (rx_idle_xhdl6 OR last_bit_of_inter) ;
go_tx_xhdl34 <= ((((NOT listen_only_mode) AND need_to_tx_xhdl20) AND (NOT tx_state_xhdl2)) AND (NOT suspend OR (sample_point AND CONV_STD_LOGIC(susp_cnt = "111")))) AND (go_early_tx OR rx_idle_xhdl6) ;
-- go_early_tx latched (for proper bit_de_stuff generation)
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
go_early_tx_latched <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR tx_point) = '1') THEN
go_early_tx_latched <= '0' ;
ELSE
IF (go_early_tx = '1') THEN
go_early_tx_latched <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
-- Tx state
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
tx_state_xhdl2 <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR go_rx_inter_xhdl9 OR error_frame OR arbitration_lost) = '1') THEN
tx_state_xhdl2 <= '0' ;
ELSE
IF (go_tx_xhdl34 = '1') THEN
tx_state_xhdl2 <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
tx_state_q_xhdl3 <= '0' ;
ELSIF (clk'EVENT AND clk = '1') THEN
IF (reset_mode = '1') THEN
tx_state_q_xhdl3 <= '0' ;
ELSE
tx_state_q_xhdl3 <= tx_state_xhdl2 ;
END IF;
END IF;
END PROCESS;
-- Node is a transmitter
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
transmitter_xhdl8 <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (go_tx_xhdl34 = '1') THEN
transmitter_xhdl8 <= '1' ;
ELSE
IF ((reset_mode OR go_rx_idle OR (suspend AND go_rx_id1)) = '1') THEN
transmitter_xhdl8 <= '0' ;
END IF;
END IF;
END IF;
END PROCESS;
-- Signal "transmitting" signals that the core is a transmitting (message, error frame or overload frame). No synchronization is done meanwhile.
-- Node might be both transmitter or receiver (sending error or overload frame)
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
transmitting_xhdl7 <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((go_error_frame_xhdl33 OR go_overload_frame_xhdl32 OR go_tx_xhdl34 OR send_ack_xhdl35) = '1') THEN
transmitting_xhdl7 <= '1' ;
ELSE
IF ((reset_mode OR go_rx_idle OR (go_rx_id1 AND (NOT tx_state_xhdl2)) OR (arbitration_lost AND tx_state_xhdl2)) = '1') THEN
transmitting_xhdl7 <= '0' ;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
suspend <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR (sample_point AND CONV_STD_LOGIC(susp_cnt = "111"))) = '1') THEN
suspend <= '0' ;
ELSE
IF (((not_first_bit_of_inter_xhdl10 AND transmitter_xhdl8) AND node_error_passive_xhdl26) = '1') THEN
suspend <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
susp_cnt_en <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR (sample_point AND CONV_STD_LOGIC(susp_cnt = "111"))) = '1') THEN
susp_cnt_en <= '0' ;
ELSE
IF (((suspend AND sample_point) AND last_bit_of_inter) = '1') THEN
susp_cnt_en <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
susp_cnt <= "000";
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR (sample_point AND CONV_STD_LOGIC(susp_cnt = "111"))) = '1') THEN
susp_cnt <= "000" ;
ELSE
IF ((susp_cnt_en AND sample_point) = '1') THEN
susp_cnt <= susp_cnt + "001" ;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
finish_msg <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((go_rx_idle OR go_rx_id1 OR error_frame OR reset_mode) = '1') THEN
finish_msg <= '0' ;
ELSE
IF (go_rx_crc_lim = '1') THEN
finish_msg <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
arbitration_lost <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((go_rx_idle OR error_frame_ended OR reset_mode) = '1') THEN
arbitration_lost <= '0' ;
ELSE
IF (((((transmitter_xhdl8 AND sample_point) AND tx_xhdl29) AND arbitration_field) AND NOT sampled_bit) = '1') THEN
arbitration_lost <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
arbitration_lost_q <= '0' ;
read_arbitration_lost_capture_reg_q <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (reset_mode = '1') THEN
arbitration_lost_q <= '0';
read_arbitration_lost_capture_reg_q <= '0';
ELSE
arbitration_lost_q <= arbitration_lost;
read_arbitration_lost_capture_reg_q <= read_arbitration_lost_capture_reg ;
END IF;
END IF;
END PROCESS;
set_arbitration_lost_irq_xhdl24 <= (arbitration_lost AND (NOT arbitration_lost_q)) AND (NOT arbitration_blocked) ;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
read_error_code_capture_reg_q <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
read_error_code_capture_reg_q <= read_error_code_capture_reg;
END IF;
END PROCESS;
reset_error_code_capture_reg <= read_error_code_capture_reg_q and not read_error_code_capture_reg;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
arbitration_cnt_en <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR arbitration_blocked) = '1') THEN
arbitration_cnt_en <= '0' ;
ELSE
IF (((rx_id1 AND sample_point) AND (NOT arbitration_blocked)) = '1') THEN
arbitration_cnt_en <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
arbitration_blocked <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR read_arbitration_lost_capture_reg) = '1') THEN
arbitration_blocked <= '0' ;
ELSE
IF (set_arbitration_lost_irq_xhdl24 = '1') THEN
arbitration_blocked <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
arbitration_lost_capture_xhdl25 <= "00000";
ELSIF (clk'EVENT AND clk = '1') THEN
IF (read_arbitration_lost_capture_reg_q = '1') THEN
arbitration_lost_capture_xhdl25 <= "00000" ;
ELSE
IF ((((sample_point AND (NOT arbitration_blocked)) AND arbitration_cnt_en) AND (NOT bit_de_stuff)) = '1') THEN
arbitration_lost_capture_xhdl25 <= arbitration_lost_capture_xhdl25 + "00001" ;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
rx_err_cnt_xhdl15 <= "000000000";
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((we_rx_err_cnt AND (NOT node_bus_off_xhdl13)) = '1') THEN
rx_err_cnt_xhdl15 <= '0' & data_in ;
ELSE
IF (set_reset_mode_xhdl12 = '1') THEN
rx_err_cnt_xhdl15 <= "000000000" ;
ELSE
IF (((NOT listen_only_mode) AND (NOT transmitter_xhdl8 OR arbitration_lost)) = '1') THEN
IF ((((go_rx_ack_lim AND (NOT go_error_frame_xhdl33)) AND (NOT crc_err)) AND CONV_STD_LOGIC(rx_err_cnt_xhdl15 > "000000000")) = '1') THEN
IF (rx_err_cnt_xhdl15 > "001111111") THEN
rx_err_cnt_xhdl15 <= "001111111" ;
ELSE
rx_err_cnt_xhdl15 <= rx_err_cnt_xhdl15 - "000000001" ;
END IF;
ELSE
IF (rx_err_cnt_xhdl15 < "010000000") THEN
IF ((go_error_frame_xhdl33 AND (NOT rule5)) = '1') THEN
-- 1 (rule 5 is just the opposite then rule 1 exception
rx_err_cnt_xhdl15 <= rx_err_cnt_xhdl15 + "000000001" ;
ELSE
IF ((((((error_flag_over AND (NOT error_flag_over_latched)) AND sample_point) AND (NOT sampled_bit)) AND CONV_STD_LOGIC(error_cnt1 = "111")) OR (go_error_frame_xhdl33 AND rule5) OR ((sample_point AND (NOT sampled_bit)) AND CONV_STD_LOGIC(delayed_dominant_cnt = "111"))) = '1') THEN
-- 2
-- 5
-- 6
rx_err_cnt_xhdl15 <= rx_err_cnt_xhdl15 + "000001000" ;
END IF;
END IF;
END IF;
END IF;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
tx_err_cnt_xhdl16 <= "000000000";
ELSIF (clk'EVENT AND clk = '1') THEN
IF (we_tx_err_cnt = '1') THEN
tx_err_cnt_xhdl16 <= '0' & data_in ;
ELSE
IF (set_reset_mode_xhdl12 = '1') THEN
tx_err_cnt_xhdl16 <= "010000000" ;
ELSE
IF ((CONV_STD_LOGIC(tx_err_cnt_xhdl16 > "000000000") AND (tx_successful_xhdl19 OR bus_free)) = '1') THEN
tx_err_cnt_xhdl16 <= tx_err_cnt_xhdl16 - "000000001" ;
ELSE
IF ((transmitter_xhdl8 AND (NOT arbitration_lost)) = '1') THEN
IF ((((sample_point AND (NOT sampled_bit)) AND CONV_STD_LOGIC(delayed_dominant_cnt = "111")) OR (go_error_frame_xhdl33 AND rule5) OR ((go_error_frame_xhdl33 AND (NOT ((transmitter_xhdl8 AND node_error_passive_xhdl26) AND ack_err))) AND (NOT (((((transmitter_xhdl8 AND stuff_err) AND arbitration_field) AND sample_point) AND tx_xhdl29) AND (NOT sampled_bit)))) OR (error_frame AND rule3_exc1_2)) = '1') THEN
-- 6
-- 4 (rule 5 is the same as rule 4)
-- 3
-- 3
tx_err_cnt_xhdl16 <= tx_err_cnt_xhdl16 + "000001000" ;
END IF;
END IF;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
node_error_passive_xhdl26 <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((rx_err_cnt_xhdl15 < "010000000") AND (tx_err_cnt_xhdl16 < "010000000")) THEN
node_error_passive_xhdl26 <= '0' ;
ELSE
IF (((CONV_STD_LOGIC((rx_err_cnt_xhdl15 >= "010000000") OR (tx_err_cnt_xhdl16 >= "010000000")) AND (error_frame_ended OR go_error_frame_xhdl33 OR ((NOT reset_mode) AND reset_mode_q))) AND (NOT node_bus_off_xhdl13)) = '1') THEN
node_error_passive_xhdl26 <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
node_error_active_xhdl27 <= NOT (node_error_passive_xhdl26 OR node_bus_off_xhdl13) ;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
node_bus_off_xhdl13 <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (((CONV_STD_LOGIC((rx_err_cnt_xhdl15 = "000000000") AND (tx_err_cnt_xhdl16 = "000000000")) AND (NOT reset_mode)) OR (we_tx_err_cnt AND CONV_STD_LOGIC(data_in < "11111111"))) = '1') THEN
node_bus_off_xhdl13 <= '0' ;
ELSE
IF ((CONV_STD_LOGIC(tx_err_cnt_xhdl16 >= "100000000") OR (we_tx_err_cnt AND CONV_STD_LOGIC(data_in = "11111111"))) = '1') THEN
node_bus_off_xhdl13 <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
bus_free_cnt <= "0000";
ELSIF (clk'EVENT AND clk = '1') THEN
IF (reset_mode = '1') THEN
bus_free_cnt <= "0000" ;
ELSE
IF (sample_point = '1') THEN
IF (((sampled_bit AND bus_free_cnt_en) AND CONV_STD_LOGIC(bus_free_cnt < "1010")) = '1') THEN
bus_free_cnt <= bus_free_cnt + "0001" ;
ELSE
bus_free_cnt <= "0000" ;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
bus_free_cnt_en <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((((NOT reset_mode) AND reset_mode_q) OR (node_bus_off_q AND (NOT reset_mode))) = '1') THEN
bus_free_cnt_en <= '1' ;
ELSE
IF ((((sample_point AND sampled_bit) AND CONV_STD_LOGIC(bus_free_cnt = "1010")) AND (NOT node_bus_off_xhdl13)) = '1') THEN
bus_free_cnt_en <= '0' ;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
bus_free <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (reset_mode = '1') THEN
bus_free <= '0';
ELSE
IF (((sample_point AND sampled_bit) AND CONV_STD_LOGIC(bus_free_cnt = "1010")) = '1') THEN
bus_free <= '1' ;
ELSE
bus_free <= '0' ;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
waiting_for_bus_free <= '1';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (reset_mode = '1') THEN
waiting_for_bus_free <= '1';
ELSE
IF ((bus_free AND (NOT node_bus_off_xhdl13)) = '1') THEN
waiting_for_bus_free <= '0' ;
ELSE
IF ((((NOT reset_mode) AND reset_mode_q) OR (node_bus_off_q AND (NOT reset_mode))) = '1') THEN
waiting_for_bus_free <= '1' ;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
bus_off_on_xhdl31 <= NOT node_bus_off_xhdl13 ;
set_reset_mode_xhdl12 <= node_bus_off_xhdl13 AND (NOT node_bus_off_q) ;
--## temp_xhdl110 <= ((rx_err_cnt_xhdl15 >= ('0' & error_warning_limit)) OR (tx_err_cnt_xhdl16 >= ('0' & error_warning_limit))) WHEN extended_mode = '1' ELSE ((rx_err_cnt_xhdl15 >= "001100000") OR (tx_err_cnt_xhdl16 >= "001100000"));
temp_xhdl110 <= ((rx_err_cnt_xhdl15 >= ('0' & error_warning_limit)) OR (tx_err_cnt_xhdl16 >= ('0' & error_warning_limit)) or (node_bus_off_xhdl13='1')) WHEN extended_mode = '1' ELSE ((rx_err_cnt_xhdl15 >= "001100000") OR (tx_err_cnt_xhdl16 >= "001100000") or (node_bus_off_xhdl13='1')); --## OpenCores: Error in recovery from BUSOFF
error_status_xhdl14 <= CONV_STD_LOGIC(temp_xhdl110) ;
transmit_status_xhdl17 <= transmitting_xhdl7 OR (extended_mode AND waiting_for_bus_free) ;
temp_xhdl111 <= (waiting_for_bus_free OR ((NOT rx_idle_xhdl6) AND (NOT transmitting_xhdl7))) WHEN extended_mode = '1' ELSE (((NOT waiting_for_bus_free) AND (NOT rx_idle_xhdl6)) AND (NOT transmitting_xhdl7));
receive_status_xhdl18 <= temp_xhdl111 ;
-- Error code capture register
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
error_capture_code_xhdl5 <= "00000000";
ELSIF (clk'EVENT AND clk = '1') THEN
IF (reset_error_code_capture_reg = '1') THEN
error_capture_code_xhdl5 <= "00000000" ;
ELSE
IF (set_bus_error_irq_xhdl23 = '1') THEN
error_capture_code_xhdl5 <= error_capture_code_type(7 DOWNTO 6) & error_capture_code_direction & error_capture_code_segment(4 DOWNTO 0) ;
END IF;
END IF;
END IF;
END PROCESS;
error_capture_code_segment(0) <= rx_idle_xhdl6 OR rx_ide OR (rx_id2 AND CONV_STD_LOGIC(bit_cnt < "001101")) OR rx_r1 OR rx_r0 OR rx_dlc OR rx_ack OR rx_ack_lim OR (error_frame AND node_error_active_xhdl27) ;
error_capture_code_segment(1) <= rx_idle_xhdl6 OR rx_id1 OR rx_id2 OR rx_dlc OR rx_data OR rx_ack_lim OR rx_eof OR rx_inter_xhdl11 OR (error_frame AND node_error_passive_xhdl26) ;
error_capture_code_segment(2) <= (rx_id1 AND CONV_STD_LOGIC(bit_cnt > "000111")) OR rx_rtr1 OR rx_ide OR rx_id2 OR rx_rtr2 OR rx_r1 OR (error_frame AND node_error_passive_xhdl26) OR overload_frame_xhdl4 ;
error_capture_code_segment(3) <= (rx_id2 AND CONV_STD_LOGIC(bit_cnt > "000100")) OR rx_rtr2 OR rx_r1 OR rx_r0 OR rx_dlc OR rx_data OR rx_crc OR rx_crc_lim OR rx_ack OR rx_ack_lim OR rx_eof OR overload_frame_xhdl4 ;
error_capture_code_segment(4) <= rx_crc_lim OR rx_ack OR rx_ack_lim OR rx_eof OR rx_inter_xhdl11 OR error_frame OR overload_frame_xhdl4 ;
error_capture_code_direction <= NOT transmitting_xhdl7 ;
PROCESS (bit_err, form_err, stuff_err)
VARIABLE error_capture_code_type_xhdl112 : std_logic_vector(7 DOWNTO 6);
BEGIN
IF (bit_err = '1') THEN
error_capture_code_type_xhdl112(7 DOWNTO 6) := "00";
ELSE
IF (form_err = '1') THEN
error_capture_code_type_xhdl112(7 DOWNTO 6) := "01";
ELSE
IF (stuff_err = '1') THEN
error_capture_code_type_xhdl112(7 DOWNTO 6) := "10";
ELSE
error_capture_code_type_xhdl112(7 DOWNTO 6) := "11";
END IF;
END IF;
END IF;
error_capture_code_type <= error_capture_code_type_xhdl112;
END PROCESS;
set_bus_error_irq_xhdl23 <= go_error_frame_xhdl33 AND (NOT error_capture_code_blocked) ;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
error_capture_code_blocked <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (read_error_code_capture_reg = '1') THEN
error_capture_code_blocked <= '0' ;
ELSE
IF (set_bus_error_irq_xhdl23 = '1') THEN
error_capture_code_blocked <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
END ARCHITECTURE RTL;
----------------------------------------------------------------------------------------------
--
-- VHDL file generated by X-HDL - Revision 3.2.53 Aug. 1, 2005
-- Tue Aug 9 07:33:51 2005
--
-- Input file : C:/Documents and Settings/BryantI/My Documents/tmp/can_top.v
-- Design name : can_register
-- Author :
-- Company : Actel
--
-- Description :
--
--
----------------------------------------------------------------------------------------------
--
--////////////////////////////////////////////////////////////////////
--// ////
--// can_register.v ////
--// ////
--// ////
--// This file is part of the CAN Protocol Controller ////
--// http://www.opencores.org/projects/can/ ////
--// ////
--// ////
--// Author(s): ////
--// Igor Mohor ////
--// [email protected] ////
--// ////
--// ////
--// All additional information is available in the README.txt ////
--// file. ////
--// ////
--////////////////////////////////////////////////////////////////////
--// ////
--// Copyright (C) 2002, 2003, 2004 Authors ////
--// ////
--// This source file may be used and distributed without ////
--// restriction provided that this copyright statement is not ////
--// removed from the file and that any derivative work contains ////
--// the original copyright notice and the associated disclaimer. ////
--// ////
--// This source file is free software; you can redistribute it ////
--// and/or modify it under the terms of the GNU Lesser General ////
--// Public License as published by the Free Software Foundation; ////
--// either version 2.1 of the License, or (at your option) any ////
--// later version. ////
--// ////
--// This source is distributed in the hope that it will be ////
--// useful, but WITHOUT ANY WARRANTY; without even the implied ////
--// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
--// PURPOSE. See the GNU Lesser General Public License for more ////
--// details. ////
--// ////
--// You should have received a copy of the GNU Lesser General ////
--// Public License along with this source; if not, download it ////
--// from http://www.opencores.org/lgpl.shtml ////
--// ////
--// The CAN protocol is developed by Robert Bosch GmbH and ////
--// protected by patents. Anybody who wants to implement this ////
--// CAN IP core on silicon has to obtain a CAN protocol license ////
--// from Bosch. ////
--// ////
--////////////////////////////////////////////////////////////////////
--
-- CVS Revision History
--
-- $Log: can_register.v,v $
-- Revision 1.7 2004/02/08 14:32:31 mohor
-- Header changed.
--
-- Revision 1.6 2003/03/20 16:58:50 mohor
-- unix.
--
-- Revision 1.4 2003/03/11 16:32:34 mohor
-- timescale.v is used for simulation only.
--
-- Revision 1.3 2003/02/09 02:24:33 mohor
-- Bosch license warning added. Error counters finished. Overload frames
-- still need to be fixed.
--
-- Revision 1.2 2002/12/27 00:12:52 mohor
-- Header changed, testbench improved to send a frame (crc still missing).
--
-- Revision 1.1.1.1 2002/12/20 16:39:21 mohor
-- Initial
--
--
--
-- synopsys translate_off
--`include "can_defines.v"
-- synopsys translate_on
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY can_register IS
GENERIC (
WIDTH : integer := 8); -- default parameter of the register width
PORT (
data_in : IN std_logic_vector(WIDTH - 1 DOWNTO 0);
data_out : OUT std_logic_vector(WIDTH - 1 DOWNTO 0);
we : IN std_logic;
clk : IN std_logic);
END ENTITY can_register;
ARCHITECTURE RTL OF can_register IS
TYPE xhdl_15 IS ARRAY (0 TO 63) OF std_logic_vector(7 DOWNTO 0);
TYPE xhdl_16 IS ARRAY (0 TO 63) OF std_logic_vector(3 DOWNTO 0);
TYPE xhdl_17 IS ARRAY (0 TO 63) OF std_logic;
TYPE xhdl_46 IS ARRAY (0 TO 7) OF std_logic_vector(7 DOWNTO 0);
SIGNAL data_out_xhdl1 : std_logic_vector(WIDTH - 1 DOWNTO 0);
BEGIN
data_out <= data_out_xhdl1;
PROCESS (clk)
BEGIN
IF (clk'EVENT AND clk = '1') THEN
IF (we = '1') THEN
-- write
data_out_xhdl1 <= data_in;
END IF;
END IF;
END PROCESS;
END ARCHITECTURE RTL;
----------------------------------------------------------------------------------------------
--
-- VHDL file generated by X-HDL - Revision 3.2.53 Aug. 1, 2005
-- Tue Aug 9 07:33:51 2005
--
-- Input file : C:/Documents and Settings/BryantI/My Documents/tmp/can_top.v
-- Design name : can_register_asyn
-- Author :
-- Company : Actel
--
-- Description :
--
--
----------------------------------------------------------------------------------------------
--
--////////////////////////////////////////////////////////////////////
--// ////
--// can_register_asyn.v ////
--// ////
--// ////
--// This file is part of the CAN Protocol Controller ////
--// http://www.opencores.org/projects/can/ ////
--// ////
--// ////
--// Author(s): ////
--// Igor Mohor ////
--// [email protected] ////
--// ////
--// ////
--// All additional information is available in the README.txt ////
--// file. ////
--// ////
--////////////////////////////////////////////////////////////////////
--// ////
--// Copyright (C) 2002, 2003, 2004 Authors ////
--// ////
--// This source file may be used and distributed without ////
--// restriction provided that this copyright statement is not ////
--// removed from the file and that any derivative work contains ////
--// the original copyright notice and the associated disclaimer. ////
--// ////
--// This source file is free software; you can redistribute it ////
--// and/or modify it under the terms of the GNU Lesser General ////
--// Public License as published by the Free Software Foundation; ////
--// either version 2.1 of the License, or (at your option) any ////
--// later version. ////
--// ////
--// This source is distributed in the hope that it will be ////
--// useful, but WITHOUT ANY WARRANTY; without even the implied ////
--// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
--// PURPOSE. See the GNU Lesser General Public License for more ////
--// details. ////
--// ////
--// You should have received a copy of the GNU Lesser General ////
--// Public License along with this source; if not, download it ////
--// from http://www.opencores.org/lgpl.shtml ////
--// ////
--// The CAN protocol is developed by Robert Bosch GmbH and ////
--// protected by patents. Anybody who wants to implement this ////
--// CAN IP core on silicon has to obtain a CAN protocol license ////
--// from Bosch. ////
--// ////
--////////////////////////////////////////////////////////////////////
--
-- CVS Revision History
--
-- $Log: can_register_asyn.v,v $
-- Revision 1.7 2004/02/08 14:33:19 mohor
-- Header changed.
--
-- Revision 1.6 2003/03/20 16:58:50 mohor
-- unix.
--
-- Revision 1.4 2003/03/11 16:32:34 mohor
-- timescale.v is used for simulation only.
--
-- Revision 1.3 2003/02/09 02:24:33 mohor
-- Bosch license warning added. Error counters finished. Overload frames
-- still need to be fixed.
--
-- Revision 1.2 2002/12/27 00:12:52 mohor
-- Header changed, testbench improved to send a frame (crc still missing).
--
-- Revision 1.1.1.1 2002/12/20 16:39:21 mohor
-- Initial
--
--
--
-- synopsys translate_off
--`include "can_defines.v"
-- synopsys translate_on
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
library grlib;
use grlib.stdlib.all;
ENTITY can_register_asyn IS
GENERIC (
WIDTH : integer := 8; -- default parameter of the register width
RESET_VALUE : integer := 0);
PORT (
data_in : IN std_logic_vector(WIDTH - 1 DOWNTO 0);
data_out : OUT std_logic_vector(WIDTH - 1 DOWNTO 0);
we : IN std_logic;
clk : IN std_logic;
rst : IN std_logic);
END ENTITY can_register_asyn;
ARCHITECTURE RTL OF can_register_asyn IS
TYPE xhdl_15 IS ARRAY (0 TO 63) OF std_logic_vector(7 DOWNTO 0);
TYPE xhdl_16 IS ARRAY (0 TO 63) OF std_logic_vector(3 DOWNTO 0);
TYPE xhdl_17 IS ARRAY (0 TO 63) OF std_logic;
TYPE xhdl_46 IS ARRAY (0 TO 7) OF std_logic_vector(7 DOWNTO 0);
SIGNAL data_out_xhdl1 : std_logic_vector(WIDTH - 1 DOWNTO 0);
BEGIN
data_out <= data_out_xhdl1;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
-- asynchronous reset
data_out_xhdl1 <= CONV_STD_LOGIC_VECTOR(RESET_VALUE, WIDTH);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (we = '1') THEN
-- write
data_out_xhdl1 <= data_in ;
END IF;
END IF;
END PROCESS;
END ARCHITECTURE RTL;
----------------------------------------------------------------------------------------------
--
-- VHDL file generated by X-HDL - Revision 3.2.53 Aug. 1, 2005
-- Tue Aug 9 07:33:52 2005
--
-- Input file : C:/Documents and Settings/BryantI/My Documents/tmp/can_top.v
-- Design name : can_register_asyn_syn
-- Author :
-- Company : Actel
--
-- Description :
--
--
----------------------------------------------------------------------------------------------
--
--////////////////////////////////////////////////////////////////////
--// ////
--// can_register_asyn_syn.v ////
--// ////
--// ////
--// This file is part of the CAN Protocol Controller ////
--// http://www.opencores.org/projects/can/ ////
--// ////
--// ////
--// Author(s): ////
--// Igor Mohor ////
--// [email protected] ////
--// ////
--// ////
--// All additional information is available in the README.txt ////
--// file. ////
--// ////
--////////////////////////////////////////////////////////////////////
--// ////
--// Copyright (C) 2002, 2003, 2004 Authors ////
--// ////
--// This source file may be used and distributed without ////
--// restriction provided that this copyright statement is not ////
--// removed from the file and that any derivative work contains ////
--// the original copyright notice and the associated disclaimer. ////
--// ////
--// This source file is free software; you can redistribute it ////
--// and/or modify it under the terms of the GNU Lesser General ////
--// Public License as published by the Free Software Foundation; ////
--// either version 2.1 of the License, or (at your option) any ////
--// later version. ////
--// ////
--// This source is distributed in the hope that it will be ////
--// useful, but WITHOUT ANY WARRANTY; without even the implied ////
--// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
--// PURPOSE. See the GNU Lesser General Public License for more ////
--// details. ////
--// ////
--// You should have received a copy of the GNU Lesser General ////
--// Public License along with this source; if not, download it ////
--// from http://www.opencores.org/lgpl.shtml ////
--// ////
--// The CAN protocol is developed by Robert Bosch GmbH and ////
--// protected by patents. Anybody who wants to implement this ////
--// CAN IP core on silicon has to obtain a CAN protocol license ////
--// from Bosch. ////
--// ////
--////////////////////////////////////////////////////////////////////
--
-- CVS Revision History
--
-- $Log: can_register_asyn_syn.v,v $
-- Revision 1.7 2004/02/08 14:33:59 mohor
-- Header changed.
--
-- Revision 1.6 2003/03/20 16:52:43 mohor
-- unix.
--
-- Revision 1.4 2003/03/11 16:32:34 mohor
-- timescale.v is used for simulation only.
--
-- Revision 1.3 2003/02/09 02:24:33 mohor
-- Bosch license warning added. Error counters finished. Overload frames
-- still need to be fixed.
--
-- Revision 1.2 2002/12/27 00:12:52 mohor
-- Header changed, testbench improved to send a frame (crc still missing).
--
-- Revision 1.1.1.1 2002/12/20 16:39:21 mohor
-- Initial
--
--
--
-- synopsys translate_off
--`include "can_defines.v"
-- synopsys translate_on
LIBRARY ieee;
USE ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
ENTITY can_register_asyn_syn IS
GENERIC (
WIDTH : integer := 8; -- default parameter of the register width
RESET_VALUE : integer := 0);
PORT (
data_in : IN std_logic_vector(WIDTH - 1 DOWNTO 0);
data_out : OUT std_logic_vector(WIDTH - 1 DOWNTO 0);
we : IN std_logic;
clk : IN std_logic;
rst : IN std_logic;
rst_sync : IN std_logic);
END ENTITY can_register_asyn_syn;
ARCHITECTURE RTL OF can_register_asyn_syn IS
TYPE xhdl_15 IS ARRAY (0 TO 63) OF std_logic_vector(7 DOWNTO 0);
TYPE xhdl_16 IS ARRAY (0 TO 63) OF std_logic_vector(3 DOWNTO 0);
TYPE xhdl_17 IS ARRAY (0 TO 63) OF std_logic;
TYPE xhdl_46 IS ARRAY (0 TO 7) OF std_logic_vector(7 DOWNTO 0);
SIGNAL data_out_xhdl1 : std_logic_vector(WIDTH - 1 DOWNTO 0);
BEGIN
data_out <= data_out_xhdl1;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
data_out_xhdl1 <= CONV_STD_LOGIC_VECTOR(RESET_VALUE, WIDTH);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (rst_sync = '1') THEN
-- synchronous reset
data_out_xhdl1 <= CONV_STD_LOGIC_VECTOR(RESET_VALUE, WIDTH);
ELSE
IF (we = '1') THEN
-- write
data_out_xhdl1 <= data_in ;
END IF;
END IF;
END IF;
END PROCESS;
END ARCHITECTURE RTL;
----------------------------------------------------------------------------------------------
--
-- VHDL file generated by X-HDL - Revision 3.2.53 Aug. 1, 2005
-- Tue Aug 9 07:33:52 2005
--
-- Input file : C:/Documents and Settings/BryantI/My Documents/tmp/can_top.v
-- Design name : can_register_syn
-- Author :
-- Company : Actel
--
-- Description :
--
--
----------------------------------------------------------------------------------------------
--
--////////////////////////////////////////////////////////////////////
--// ////
--// can_register_syn.v ////
--// ////
--// ////
--// This file is part of the CAN Protocol Controller ////
--// http://www.opencores.org/projects/can/ ////
--// ////
--// ////
--// Author(s): ////
--// Igor Mohor ////
--// [email protected] ////
--// ////
--// ////
--// All additional information is available in the README.txt ////
--// file. ////
--// ////
--////////////////////////////////////////////////////////////////////
--// ////
--// Copyright (C) 2002, 2003, 2004 Authors ////
--// ////
--// This source file may be used and distributed without ////
--// restriction provided that this copyright statement is not ////
--// removed from the file and that any derivative work contains ////
--// the original copyright notice and the associated disclaimer. ////
--// ////
--// This source file is free software; you can redistribute it ////
--// and/or modify it under the terms of the GNU Lesser General ////
--// Public License as published by the Free Software Foundation; ////
--// either version 2.1 of the License, or (at your option) any ////
--// later version. ////
--// ////
--// This source is distributed in the hope that it will be ////
--// useful, but WITHOUT ANY WARRANTY; without even the implied ////
--// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
--// PURPOSE. See the GNU Lesser General Public License for more ////
--// details. ////
--// ////
--// You should have received a copy of the GNU Lesser General ////
--// Public License along with this source; if not, download it ////
--// from http://www.opencores.org/lgpl.shtml ////
--// ////
--// The CAN protocol is developed by Robert Bosch GmbH and ////
--// protected by patents. Anybody who wants to implement this ////
--// CAN IP core on silicon has to obtain a CAN protocol license ////
--// from Bosch. ////
--// ////
--////////////////////////////////////////////////////////////////////
--
-- CVS Revision History
--
-- $Log: can_register_syn.v,v $
-- Revision 1.5 2004/02/08 14:34:40 mohor
-- Header changed.
--
-- Revision 1.4 2003/03/11 16:31:58 mohor
-- timescale.v is used for simulation only.
--
-- Revision 1.3 2003/02/09 02:24:33 mohor
-- Bosch license warning added. Error counters finished. Overload frames
-- still need to be fixed.
--
-- Revision 1.2 2002/12/27 00:12:52 mohor
-- Header changed, testbench improved to send a frame (crc still missing).
--
-- Revision 1.1.1.1 2002/12/20 16:39:21 mohor
-- Initial
--
--
--
-- synopsys translate_off
--`include "can_defines.v"
-- synopsys translate_on
LIBRARY ieee;
USE ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
ENTITY can_register_syn IS
GENERIC (
WIDTH : integer := 8; -- default parameter of the register width
RESET_VALUE : integer := 0);
PORT (
data_in : IN std_logic_vector(WIDTH - 1 DOWNTO 0);
data_out : OUT std_logic_vector(WIDTH - 1 DOWNTO 0);
we : IN std_logic;
clk : IN std_logic;
rst_sync : IN std_logic);
END ENTITY can_register_syn;
ARCHITECTURE RTL OF can_register_syn IS
TYPE xhdl_15 IS ARRAY (0 TO 63) OF std_logic_vector(7 DOWNTO 0);
TYPE xhdl_16 IS ARRAY (0 TO 63) OF std_logic_vector(3 DOWNTO 0);
TYPE xhdl_17 IS ARRAY (0 TO 63) OF std_logic;
TYPE xhdl_46 IS ARRAY (0 TO 7) OF std_logic_vector(7 DOWNTO 0);
SIGNAL data_out_xhdl1 : std_logic_vector(WIDTH - 1 DOWNTO 0);
BEGIN
data_out <= data_out_xhdl1;
PROCESS (clk)
BEGIN
IF (clk'EVENT AND clk = '1') THEN
IF (rst_sync = '1') THEN
-- synchronous reset
data_out_xhdl1 <= CONV_STD_LOGIC_VECTOR(RESET_VALUE, 8);
ELSE
IF (we = '1') THEN
-- write
data_out_xhdl1 <= data_in ;
END IF;
END IF;
END IF;
END PROCESS;
END ARCHITECTURE RTL;
----------------------------------------------------------------------------------------------
--
-- VHDL file generated by X-HDL - Revision 3.2.53 Aug. 1, 2005
-- Tue Aug 9 07:33:52 2005
--
-- Input file : C:/Documents and Settings/BryantI/My Documents/tmp/can_top.v
-- Design name : can_registers
-- Author :
-- Company : Actel
--
-- Description :
--
--
----------------------------------------------------------------------------------------------
--
--////////////////////////////////////////////////////////////////////
--// ////
--// can_registers.v ////
--// ////
--// ////
--// This file is part of the CAN Protocol Controller ////
--// http://www.opencores.org/projects/can/ ////
--// ////
--// ////
--// Author(s): ////
--// Igor Mohor ////
--// [email protected] ////
--// ////
--// ////
--// All additional information is available in the README.txt ////
--// file. ////
--// ////
--////////////////////////////////////////////////////////////////////
--// ////
--// Copyright (C) 2002, 2003 Authors ////
--// ////
--// This source file may be used and distributed without ////
--// restriction provided that this copyright statement is not ////
--// removed from the file and that any derivative work contains ////
--// the original copyright notice and the associated disclaimer. ////
--// ////
--// This source file is free software; you can redistribute it ////
--// and/or modify it under the terms of the GNU Lesser General ////
--// Public License as published by the Free Software Foundation; ////
--// either version 2.1 of the License, or (at your option) any ////
--// later version. ////
--// ////
--// This source is distributed in the hope that it will be ////
--// useful, but WITHOUT ANY WARRANTY; without even the implied ////
--// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
--// PURPOSE. See the GNU Lesser General Public License for more ////
--// details. ////
--// ////
--// You should have received a copy of the GNU Lesser General ////
--// Public License along with this source; if not, download it ////
--// from http://www.opencores.org/lgpl.shtml ////
--// ////
--// The CAN protocol is developed by Robert Bosch GmbH and ////
--// protected by patents. Anybody who wants to implement this ////
--// CAN IP core on silicon has to obtain a CAN protocol license ////
--// from Bosch. ////
--// ////
--////////////////////////////////////////////////////////////////////
--
-- CVS Revision History
-- Revision 1.36 2005/03/18 15:04:05 igorm
-- Wake-up interrupt was generated in some cases.
--
-- Revision 1.35 2004/11/30 15:08:26 igorm
-- irq is cleared after the release_buffer command. This bug was entered with
-- changes for the edge triggered interrupts.
--
-- Revision 1.34 2004/11/18 12:39:43 igorm
-- Fixes for compatibility after the SW reset.
--
-- Revision 1.33 2004/10/25 11:44:38 igorm
-- Interrupt is always cleared for one clock after the irq register is read.
-- This fixes problems when CPU is using IRQs that are edge triggered.
--
-- Revision 1.32 2004/05/12 15:58:41 igorm
-- Core improved to pass all tests with the Bosch VHDL Reference system.
--
-- Revision 1.31 2003/09/25 18:55:49 mohor
-- Synchronization changed, error counters fixed.
--
-- Revision 1.30 2003/07/16 15:19:34 mohor
-- Fixed according to the linter.
-- Case statement for data_out joined.
--
-- Revision 1.29 2003/07/10 01:59:04 tadejm
-- Synchronization fixed. In some strange cases it didn't work according to
-- the VHDL reference model.
--
-- Revision 1.28 2003/07/07 11:21:37 mohor
-- Little fixes (to fix warnings).
--
-- Revision 1.27 2003/06/22 09:43:03 mohor
-- synthesi full_case parallel_case fixed.
--
-- Revision 1.26 2003/06/22 01:33:14 mohor
-- clkout is clk/2 after the reset.
--
-- Revision 1.25 2003/06/21 12:16:30 mohor
-- paralel_case and full_case compiler directives added to case statements.
--
-- Revision 1.24 2003/06/09 11:22:54 mohor
-- data_out is already registered in the can_top.v file.
--
-- Revision 1.23 2003/04/15 15:31:24 mohor
-- Some features are supported in extended mode only (listen_only_mode...).
--
-- Revision 1.22 2003/03/20 16:58:50 mohor
-- unix.
--
-- Revision 1.20 2003/03/11 16:31:05 mohor
-- Mux used for clkout to avoid "gated clocks warning".
--
-- Revision 1.19 2003/03/10 17:34:25 mohor
-- Doubled declarations removed.
--
-- Revision 1.18 2003/03/01 22:52:11 mohor
-- Data is latched on read.
--
-- Revision 1.17 2003/02/19 15:09:02 mohor
-- Incomplete sensitivity list fixed.
--
-- Revision 1.16 2003/02/19 14:44:03 mohor
-- CAN core finished. Host interface added. Registers finished.
-- Synchronization to the wishbone finished.
--
-- Revision 1.15 2003/02/18 00:10:15 mohor
-- Most of the registers added. Registers "arbitration lost capture", "error code
-- capture" + few more still need to be added.
--
-- Revision 1.14 2003/02/14 20:17:01 mohor
-- Several registers added. Not finished, yet.
--
-- Revision 1.13 2003/02/12 14:25:30 mohor
-- abort_tx added.
--
-- Revision 1.12 2003/02/11 00:56:06 mohor
-- Wishbone interface added.
--
-- Revision 1.11 2003/02/09 02:24:33 mohor
-- Bosch license warning added. Error counters finished. Overload frames
-- still need to be fixed.
--
-- Revision 1.10 2003/01/31 01:13:38 mohor
-- backup.
--
-- Revision 1.9 2003/01/15 13:16:48 mohor
-- When a frame with "remote request" is received, no data is stored
-- to fifo, just the frame information (identifier, ...). Data length
-- that is stored is the received data length and not the actual data
-- length that is stored to fifo.
--
-- Revision 1.8 2003/01/14 17:25:09 mohor
-- Addresses corrected to decimal values (previously hex).
--
-- Revision 1.7 2003/01/14 12:19:35 mohor
-- rx_fifo is now working.
--
-- Revision 1.6 2003/01/10 17:51:34 mohor
-- Temporary version (backup).
--
-- Revision 1.5 2003/01/09 14:46:58 mohor
-- Temporary files (backup).
--
-- Revision 1.4 2003/01/08 02:10:55 mohor
-- Acceptance filter added.
--
-- Revision 1.3 2002/12/27 00:12:52 mohor
-- Header changed, testbench improved to send a frame (crc still missing).
--
-- Revision 1.2 2002/12/26 16:00:34 mohor
-- Testbench define file added. Clock divider register added.
--
-- Revision 1.1.1.1 2002/12/20 16:39:21 mohor
-- Initial
--
--
--
-- synopsys translate_off
--`include "can_defines.v"
-- synopsys translate_on
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
library grlib;
use grlib.stdlib.all;
ENTITY can_registers IS
PORT (
clk : IN std_logic;
rst : IN std_logic;
cs : IN std_logic;
we : IN std_logic;
addr : IN std_logic_vector(7 DOWNTO 0);
data_in : IN std_logic_vector(7 DOWNTO 0);
data_out : OUT std_logic_vector(7 DOWNTO 0);
irq_n : OUT std_logic;
sample_point : IN std_logic;
transmitting : IN std_logic;
set_reset_mode : IN std_logic;
node_bus_off : IN std_logic;
error_status : IN std_logic;
rx_err_cnt : IN std_logic_vector(7 DOWNTO 0);
tx_err_cnt : IN std_logic_vector(7 DOWNTO 0);
transmit_status : IN std_logic;
receive_status : IN std_logic;
tx_successful : IN std_logic;
need_to_tx : IN std_logic;
overrun : IN std_logic;
info_empty : IN std_logic;
set_bus_error_irq : IN std_logic;
set_arbitration_lost_irq: IN std_logic;
arbitration_lost_capture: IN std_logic_vector(4 DOWNTO 0);
node_error_passive : IN std_logic;
node_error_active : IN std_logic;
rx_message_counter : IN std_logic_vector(6 DOWNTO 0);
-- Mode register
reset_mode : OUT std_logic;
listen_only_mode : OUT std_logic;
acceptance_filter_mode : OUT std_logic;
self_test_mode : OUT std_logic;
-- Command register
clear_data_overrun : OUT std_logic;
release_buffer : OUT std_logic;
abort_tx : OUT std_logic;
tx_request : OUT std_logic;
self_rx_request : OUT std_logic;
single_shot_transmission: OUT std_logic;
tx_state : IN std_logic;
tx_state_q : IN std_logic;
overload_request : OUT std_logic;
overload_frame : IN std_logic;
-- Arbitration Lost Capture Register
read_arbitration_lost_capture_reg: OUT std_logic;
-- Error Code Capture Register
read_error_code_capture_reg: OUT std_logic;
error_capture_code : IN std_logic_vector(7 DOWNTO 0);
-- Bus Timing 0 register
baud_r_presc : OUT std_logic_vector(5 DOWNTO 0);
sync_jump_width : OUT std_logic_vector(1 DOWNTO 0);
-- Bus Timing 1 register
time_segment1 : OUT std_logic_vector(3 DOWNTO 0);
time_segment2 : OUT std_logic_vector(2 DOWNTO 0);
triple_sampling : OUT std_logic;
-- Error Warning Limit register
error_warning_limit : OUT std_logic_vector(7 DOWNTO 0);
-- Rx Error Counter register
we_rx_err_cnt : OUT std_logic;
-- Tx Error Counter register
we_tx_err_cnt : OUT std_logic;
-- Clock Divider register
extended_mode : OUT std_logic;
clkout : OUT std_logic;
-- This section is for BASIC and EXTENDED mode -- Acceptance code register
acceptance_code_0 : OUT std_logic_vector(7 DOWNTO 0);
-- Acceptance mask register
acceptance_mask_0 : OUT std_logic_vector(7 DOWNTO 0);
-- End: This section is for BASIC and EXTENDED mode -- This section is for EXTENDED mode -- Acceptance code register
acceptance_code_1 : OUT std_logic_vector(7 DOWNTO 0);
acceptance_code_2 : OUT std_logic_vector(7 DOWNTO 0);
acceptance_code_3 : OUT std_logic_vector(7 DOWNTO 0);
-- Acceptance mask register
acceptance_mask_1 : OUT std_logic_vector(7 DOWNTO 0);
acceptance_mask_2 : OUT std_logic_vector(7 DOWNTO 0);
acceptance_mask_3 : OUT std_logic_vector(7 DOWNTO 0);
-- End: This section is for EXTENDED mode -- Tx data registers. Holding identifier (basic mode), tx frame information (extended mode) and data
tx_data_0 : OUT std_logic_vector(7 DOWNTO 0);
tx_data_1 : OUT std_logic_vector(7 DOWNTO 0);
tx_data_2 : OUT std_logic_vector(7 DOWNTO 0);
tx_data_3 : OUT std_logic_vector(7 DOWNTO 0);
tx_data_4 : OUT std_logic_vector(7 DOWNTO 0);
tx_data_5 : OUT std_logic_vector(7 DOWNTO 0);
tx_data_6 : OUT std_logic_vector(7 DOWNTO 0);
tx_data_7 : OUT std_logic_vector(7 DOWNTO 0);
tx_data_8 : OUT std_logic_vector(7 DOWNTO 0);
tx_data_9 : OUT std_logic_vector(7 DOWNTO 0);
tx_data_10 : OUT std_logic_vector(7 DOWNTO 0);
tx_data_11 : OUT std_logic_vector(7 DOWNTO 0);
tx_data_12 : OUT std_logic_vector(7 DOWNTO 0));
END ENTITY can_registers;
ARCHITECTURE RTL OF can_registers IS
CONSTANT xhdl_timescale : time := 1 ns;
COMPONENT can_register
GENERIC (
WIDTH : integer := 8); -- default parameter of the register width
PORT (
data_in : IN std_logic_vector(WIDTH - 1 DOWNTO 0);
data_out : OUT std_logic_vector(WIDTH - 1 DOWNTO 0);
we : IN std_logic;
clk : IN std_logic);
END COMPONENT;
COMPONENT can_register_asyn
GENERIC (
WIDTH : integer := 8; -- default parameter of the register width
RESET_VALUE : integer := 0);
PORT (
data_in : IN std_logic_vector(WIDTH - 1 DOWNTO 0);
data_out : OUT std_logic_vector(WIDTH - 1 DOWNTO 0);
we : IN std_logic;
clk : IN std_logic;
rst : IN std_logic);
END COMPONENT;
COMPONENT can_register_asyn_syn
GENERIC (
WIDTH : integer := 8; -- default parameter of the register width
RESET_VALUE : integer := 0);
PORT (
data_in : IN std_logic_vector(WIDTH - 1 DOWNTO 0);
data_out : OUT std_logic_vector(WIDTH - 1 DOWNTO 0);
we : IN std_logic;
clk : IN std_logic;
rst : IN std_logic;
rst_sync : IN std_logic);
END COMPONENT;
TYPE xhdl_15 IS ARRAY (0 TO 63) OF std_logic_vector(7 DOWNTO 0);
TYPE xhdl_16 IS ARRAY (0 TO 63) OF std_logic_vector(3 DOWNTO 0);
TYPE xhdl_17 IS ARRAY (0 TO 63) OF std_logic;
TYPE xhdl_46 IS ARRAY (0 TO 7) OF std_logic_vector(7 DOWNTO 0);
-- End: Tx data registers
signal read_irq_reg_q : std_logic;
signal reset_irq_reg : std_logic;
SIGNAL tx_successful_q : std_logic;
SIGNAL overrun_q : std_logic;
SIGNAL overrun_status : std_logic;
SIGNAL transmission_complete : std_logic;
SIGNAL transmit_buffer_status_q : std_logic;
SIGNAL receive_buffer_status : std_logic;
SIGNAL error_status_q : std_logic;
SIGNAL node_bus_off_q : std_logic;
SIGNAL node_error_passive_q : std_logic;
SIGNAL transmit_buffer_status : std_logic;
-- Some interrupts exist in basic mode and in extended mode. Since they are in different registers they need to be multiplexed.
SIGNAL data_overrun_irq_en : std_logic;
SIGNAL error_warning_irq_en : std_logic;
SIGNAL transmit_irq_en : std_logic;
SIGNAL receive_irq_en : std_logic;
SIGNAL irq_reg : std_logic_vector(7 DOWNTO 0);
SIGNAL irq : std_logic;
SIGNAL we_mode : std_logic;
SIGNAL we_command : std_logic;
SIGNAL we_bus_timing_0 : std_logic;
SIGNAL we_bus_timing_1 : std_logic;
SIGNAL we_clock_divider_low : std_logic;
SIGNAL we_clock_divider_hi : std_logic;
SIGNAL read : std_logic;
SIGNAL read_irq_reg : std_logic;
-- This section is for BASIC and EXTENDED mode
SIGNAL we_acceptance_code_0 : std_logic;
SIGNAL we_acceptance_mask_0 : std_logic;
SIGNAL we_tx_data_0 : std_logic;
SIGNAL we_tx_data_1 : std_logic;
SIGNAL we_tx_data_2 : std_logic;
SIGNAL we_tx_data_3 : std_logic;
SIGNAL we_tx_data_4 : std_logic;
SIGNAL we_tx_data_5 : std_logic;
SIGNAL we_tx_data_6 : std_logic;
SIGNAL we_tx_data_7 : std_logic;
SIGNAL we_tx_data_8 : std_logic;
SIGNAL we_tx_data_9 : std_logic;
SIGNAL we_tx_data_10 : std_logic;
SIGNAL we_tx_data_11 : std_logic;
SIGNAL we_tx_data_12 : std_logic;
-- End: This section is for BASIC and EXTENDED mode
-- This section is for EXTENDED mode
SIGNAL we_interrupt_enable : std_logic;
SIGNAL we_error_warning_limit : std_logic;
SIGNAL we_acceptance_code_1 : std_logic;
SIGNAL we_acceptance_code_2 : std_logic;
SIGNAL we_acceptance_code_3 : std_logic;
SIGNAL we_acceptance_mask_1 : std_logic;
SIGNAL we_acceptance_mask_2 : std_logic;
SIGNAL we_acceptance_mask_3 : std_logic;
-- Mode register
SIGNAL mode : std_logic;
SIGNAL mode_basic : std_logic_vector(4 DOWNTO 1);
SIGNAL mode_ext : std_logic_vector(3 DOWNTO 1);
SIGNAL receive_irq_en_basic : std_logic;
SIGNAL transmit_irq_en_basic : std_logic;
SIGNAL error_irq_en_basic : std_logic;
SIGNAL overrun_irq_en_basic : std_logic;
SIGNAL port_xhdl52 : std_logic;
SIGNAL xhdl_61 : std_logic;
-- End Mode register
-- Command register
SIGNAL command : std_logic_vector(4 DOWNTO 0);
SIGNAL xhdl_69 : std_logic;
SIGNAL port_xhdl70 : std_logic;
SIGNAL port_xhdl71 : std_logic;
SIGNAL xhdl_77 : std_logic;
SIGNAL port_xhdl78 : std_logic;
SIGNAL port_xhdl79 : std_logic;
SIGNAL xhdl_85 : std_logic;
SIGNAL xhdl_91 : std_logic;
SIGNAL port_xhdl92 : std_logic;
SIGNAL port_xhdl93 : std_logic;
-- End Command register
-- Status register
SIGNAL status : std_logic_vector(7 DOWNTO 0);
-- End Status register
-- Interrupt Enable register (extended mode)
SIGNAL irq_en_ext : std_logic_vector(7 DOWNTO 0);
SIGNAL bus_error_irq_en : std_logic;
SIGNAL arbitration_lost_irq_en : std_logic;
SIGNAL error_passive_irq_en : std_logic;
SIGNAL data_overrun_irq_en_ext : std_logic;
SIGNAL error_warning_irq_en_ext : std_logic;
SIGNAL transmit_irq_en_ext : std_logic;
SIGNAL receive_irq_en_ext : std_logic;
-- End Bus Timing 0 register
-- Bus Timing 0 register
SIGNAL bus_timing_0 : std_logic_vector(7 DOWNTO 0);
-- End Bus Timing 0 register
-- Bus Timing 1 register
SIGNAL bus_timing_1 : std_logic_vector(7 DOWNTO 0);
-- End Error Warning Limit register
-- Clock Divider register
SIGNAL clock_divider : std_logic_vector(7 DOWNTO 0);
SIGNAL clock_off : std_logic;
SIGNAL cd : std_logic_vector(2 DOWNTO 0);
SIGNAL clkout_div : std_logic_vector(2 DOWNTO 0);
SIGNAL clkout_cnt : std_logic_vector(2 DOWNTO 0);
SIGNAL clkout_tmp : std_logic;
SIGNAL port_xhdl116 : std_logic;
SIGNAL port_xhdl117 : std_logic;
SIGNAL port_xhdl123 : std_logic;
SIGNAL port_xhdl124 : std_logic;
SIGNAL temp_xhdl131 : std_logic;
SIGNAL temp_xhdl132 : std_logic;
SIGNAL temp_xhdl218 : std_logic_vector(7 DOWNTO 0); -- basic mode
SIGNAL temp_xhdl219 : std_logic_vector(7 DOWNTO 0); -- basic mode
SIGNAL temp_xhdl220 : std_logic_vector(7 DOWNTO 0); -- basic mode
SIGNAL temp_xhdl221 : std_logic_vector(7 DOWNTO 0); -- basic mode
SIGNAL temp_xhdl222 : std_logic_vector(7 DOWNTO 0); -- basic mode
SIGNAL temp_xhdl223 : std_logic_vector(7 DOWNTO 0); -- basic mode
SIGNAL temp_xhdl224 : std_logic_vector(7 DOWNTO 0); -- basic mode
SIGNAL temp_xhdl225 : std_logic_vector(7 DOWNTO 0); -- basic mode
SIGNAL temp_xhdl226 : std_logic_vector(7 DOWNTO 0); -- basic mode
SIGNAL temp_xhdl227 : std_logic_vector(7 DOWNTO 0); -- basic mode
SIGNAL temp_xhdl228 : std_logic_vector(7 DOWNTO 0); -- basic mode
SIGNAL temp_xhdl229 : std_logic_vector(7 DOWNTO 0); -- basic mode
SIGNAL temp_xhdl230 : std_logic_vector(7 DOWNTO 0); -- basic mode
SIGNAL temp_xhdl231 : std_logic_vector(7 DOWNTO 0); -- basic mode
-- Some interrupts exist in basic mode and in extended mode. Since they are in different registers they need to be multiplexed.
SIGNAL temp_xhdl233 : std_logic;
SIGNAL temp_xhdl234 : std_logic;
SIGNAL temp_xhdl235 : std_logic;
SIGNAL temp_xhdl236 : std_logic;
SIGNAL data_overrun_irq : std_logic;
SIGNAL transmit_irq : std_logic;
SIGNAL receive_irq : std_logic;
SIGNAL error_irq : std_logic;
SIGNAL bus_error_irq : std_logic;
SIGNAL arbitration_lost_irq : std_logic;
SIGNAL error_passive_irq : std_logic;
SIGNAL data_out_xhdl1 : std_logic_vector(7 DOWNTO 0);
SIGNAL irq_n_xhdl2 : std_logic;
SIGNAL reset_mode_xhdl3 : std_logic;
SIGNAL listen_only_mode_xhdl4 : std_logic;
SIGNAL acceptance_filter_mode_xhdl5 : std_logic;
SIGNAL self_test_mode_xhdl6 : std_logic;
SIGNAL clear_data_overrun_xhdl7 : std_logic;
SIGNAL release_buffer_xhdl8 : std_logic;
SIGNAL abort_tx_xhdl9 : std_logic;
SIGNAL tx_request_xhdl10 : std_logic;
SIGNAL self_rx_request_xhdl11 : std_logic;
SIGNAL single_shot_transmission_xhdl12 : std_logic;
SIGNAL overload_request_xhdl13 : std_logic;
SIGNAL read_arbitration_lost_capture_reg_xhdl14: std_logic;
SIGNAL read_error_code_capture_reg_xhdl15: std_logic;
SIGNAL baud_r_presc_xhdl16 : std_logic_vector(5 DOWNTO 0);
SIGNAL sync_jump_width_xhdl17 : std_logic_vector(1 DOWNTO 0);
SIGNAL time_segment1_xhdl18 : std_logic_vector(3 DOWNTO 0);
SIGNAL time_segment2_xhdl19 : std_logic_vector(2 DOWNTO 0);
SIGNAL triple_sampling_xhdl20 : std_logic;
SIGNAL error_warning_limit_xhdl21 : std_logic_vector(7 DOWNTO 0);
SIGNAL we_rx_err_cnt_xhdl22 : std_logic;
SIGNAL we_tx_err_cnt_xhdl23 : std_logic;
SIGNAL extended_mode_xhdl24 : std_logic;
SIGNAL clkout_xhdl25 : std_logic;
SIGNAL acceptance_code_0_xhdl26 : std_logic_vector(7 DOWNTO 0);
SIGNAL acceptance_mask_0_xhdl27 : std_logic_vector(7 DOWNTO 0);
SIGNAL acceptance_code_1_xhdl28 : std_logic_vector(7 DOWNTO 0);
SIGNAL acceptance_code_2_xhdl29 : std_logic_vector(7 DOWNTO 0);
SIGNAL acceptance_code_3_xhdl30 : std_logic_vector(7 DOWNTO 0);
SIGNAL acceptance_mask_1_xhdl31 : std_logic_vector(7 DOWNTO 0);
SIGNAL acceptance_mask_2_xhdl32 : std_logic_vector(7 DOWNTO 0);
SIGNAL acceptance_mask_3_xhdl33 : std_logic_vector(7 DOWNTO 0);
SIGNAL tx_data_0_xhdl34 : std_logic_vector(7 DOWNTO 0);
SIGNAL tx_data_1_xhdl35 : std_logic_vector(7 DOWNTO 0);
SIGNAL tx_data_2_xhdl36 : std_logic_vector(7 DOWNTO 0);
SIGNAL tx_data_3_xhdl37 : std_logic_vector(7 DOWNTO 0);
SIGNAL tx_data_4_xhdl38 : std_logic_vector(7 DOWNTO 0);
SIGNAL tx_data_5_xhdl39 : std_logic_vector(7 DOWNTO 0);
SIGNAL tx_data_6_xhdl40 : std_logic_vector(7 DOWNTO 0);
SIGNAL tx_data_7_xhdl41 : std_logic_vector(7 DOWNTO 0);
SIGNAL tx_data_8_xhdl42 : std_logic_vector(7 DOWNTO 0);
SIGNAL tx_data_9_xhdl43 : std_logic_vector(7 DOWNTO 0);
SIGNAL tx_data_10_xhdl44 : std_logic_vector(7 DOWNTO 0);
SIGNAL tx_data_11_xhdl45 : std_logic_vector(7 DOWNTO 0);
SIGNAL tx_data_12_xhdl46 : std_logic_vector(7 DOWNTO 0);
BEGIN
data_out <= data_out_xhdl1;
irq_n <= irq_n_xhdl2;
reset_mode <= reset_mode_xhdl3;
listen_only_mode <= listen_only_mode_xhdl4;
acceptance_filter_mode <= acceptance_filter_mode_xhdl5;
self_test_mode <= self_test_mode_xhdl6;
clear_data_overrun <= clear_data_overrun_xhdl7;
release_buffer <= release_buffer_xhdl8;
abort_tx <= abort_tx_xhdl9;
tx_request <= tx_request_xhdl10;
self_rx_request <= self_rx_request_xhdl11;
single_shot_transmission <= single_shot_transmission_xhdl12;
overload_request <= overload_request_xhdl13;
read_arbitration_lost_capture_reg <= read_arbitration_lost_capture_reg_xhdl14;
read_error_code_capture_reg <= read_error_code_capture_reg_xhdl15;
baud_r_presc <= baud_r_presc_xhdl16;
sync_jump_width <= sync_jump_width_xhdl17;
time_segment1 <= time_segment1_xhdl18;
time_segment2 <= time_segment2_xhdl19;
triple_sampling <= triple_sampling_xhdl20;
error_warning_limit <= error_warning_limit_xhdl21;
we_rx_err_cnt <= we_rx_err_cnt_xhdl22;
we_tx_err_cnt <= we_tx_err_cnt_xhdl23;
extended_mode <= extended_mode_xhdl24;
clkout <= clkout_xhdl25;
acceptance_code_0 <= acceptance_code_0_xhdl26;
acceptance_mask_0 <= acceptance_mask_0_xhdl27;
acceptance_code_1 <= acceptance_code_1_xhdl28;
acceptance_code_2 <= acceptance_code_2_xhdl29;
acceptance_code_3 <= acceptance_code_3_xhdl30;
acceptance_mask_1 <= acceptance_mask_1_xhdl31;
acceptance_mask_2 <= acceptance_mask_2_xhdl32;
acceptance_mask_3 <= acceptance_mask_3_xhdl33;
tx_data_0 <= tx_data_0_xhdl34;
tx_data_1 <= tx_data_1_xhdl35;
tx_data_2 <= tx_data_2_xhdl36;
tx_data_3 <= tx_data_3_xhdl37;
tx_data_4 <= tx_data_4_xhdl38;
tx_data_5 <= tx_data_5_xhdl39;
tx_data_6 <= tx_data_6_xhdl40;
tx_data_7 <= tx_data_7_xhdl41;
tx_data_8 <= tx_data_8_xhdl42;
tx_data_9 <= tx_data_9_xhdl43;
tx_data_10 <= tx_data_10_xhdl44;
tx_data_11 <= tx_data_11_xhdl45;
tx_data_12 <= tx_data_12_xhdl46;
we_mode <= (cs AND we) AND CONV_STD_LOGIC(addr = "00000000") ;
we_command <= (cs AND we) AND CONV_STD_LOGIC(addr = "00000001") ;
we_bus_timing_0 <= ((cs AND we) AND CONV_STD_LOGIC(addr = "00000110")) AND reset_mode_xhdl3 ;
we_bus_timing_1 <= ((cs AND we) AND CONV_STD_LOGIC(addr = "00000111")) AND reset_mode_xhdl3 ;
we_clock_divider_low <= (cs AND we) AND CONV_STD_LOGIC(addr = "00011111") ;
we_clock_divider_hi <= we_clock_divider_low AND reset_mode_xhdl3 ;
read <= cs AND (NOT we) ;
read_irq_reg <= read AND CONV_STD_LOGIC(addr = "00000011") ;
reset_irq_reg <= read_irq_reg_q and not read_irq_reg;
read_arbitration_lost_capture_reg_xhdl14 <= (read AND extended_mode_xhdl24) AND CONV_STD_LOGIC(addr = "00001011") ;
read_error_code_capture_reg_xhdl15 <= (read AND extended_mode_xhdl24) AND CONV_STD_LOGIC(addr = "00001100") ;
we_acceptance_code_0 <= ((cs AND we) AND reset_mode_xhdl3) AND (((NOT extended_mode_xhdl24) AND CONV_STD_LOGIC(addr = "00000100")) OR (extended_mode_xhdl24 AND CONV_STD_LOGIC(addr = "00010000"))) ;
we_acceptance_mask_0 <= ((cs AND we) AND reset_mode_xhdl3) AND (((NOT extended_mode_xhdl24) AND CONV_STD_LOGIC(addr = "00000101")) OR (extended_mode_xhdl24 AND CONV_STD_LOGIC(addr = "00010100"))) ;
we_tx_data_0 <= (((cs AND we) AND (NOT reset_mode_xhdl3)) AND (((NOT extended_mode_xhdl24) AND CONV_STD_LOGIC(addr = "00001010")) OR (extended_mode_xhdl24 AND CONV_STD_LOGIC(addr = "00010000")))) AND transmit_buffer_status ;
we_tx_data_1 <= (((cs AND we) AND (NOT reset_mode_xhdl3)) AND (((NOT extended_mode_xhdl24) AND CONV_STD_LOGIC(addr = "00001011")) OR (extended_mode_xhdl24 AND CONV_STD_LOGIC(addr = "00010001")))) AND transmit_buffer_status ;
we_tx_data_2 <= (((cs AND we) AND (NOT reset_mode_xhdl3)) AND (((NOT extended_mode_xhdl24) AND CONV_STD_LOGIC(addr = "00001100")) OR (extended_mode_xhdl24 AND CONV_STD_LOGIC(addr = "00010010")))) AND transmit_buffer_status ;
we_tx_data_3 <= (((cs AND we) AND (NOT reset_mode_xhdl3)) AND (((NOT extended_mode_xhdl24) AND CONV_STD_LOGIC(addr = "00001101")) OR (extended_mode_xhdl24 AND CONV_STD_LOGIC(addr = "00010011")))) AND transmit_buffer_status ;
we_tx_data_4 <= (((cs AND we) AND (NOT reset_mode_xhdl3)) AND (((NOT extended_mode_xhdl24) AND CONV_STD_LOGIC(addr = "00001110")) OR (extended_mode_xhdl24 AND CONV_STD_LOGIC(addr = "00010100")))) AND transmit_buffer_status ;
we_tx_data_5 <= (((cs AND we) AND (NOT reset_mode_xhdl3)) AND (((NOT extended_mode_xhdl24) AND CONV_STD_LOGIC(addr = "00001111")) OR (extended_mode_xhdl24 AND CONV_STD_LOGIC(addr = "00010101")))) AND transmit_buffer_status ;
we_tx_data_6 <= (((cs AND we) AND (NOT reset_mode_xhdl3)) AND (((NOT extended_mode_xhdl24) AND CONV_STD_LOGIC(addr = "00010000")) OR (extended_mode_xhdl24 AND CONV_STD_LOGIC(addr = "00010110")))) AND transmit_buffer_status ;
we_tx_data_7 <= (((cs AND we) AND (NOT reset_mode_xhdl3)) AND (((NOT extended_mode_xhdl24) AND CONV_STD_LOGIC(addr = "00010001")) OR (extended_mode_xhdl24 AND CONV_STD_LOGIC(addr = "00010111")))) AND transmit_buffer_status ;
we_tx_data_8 <= (((cs AND we) AND (NOT reset_mode_xhdl3)) AND (((NOT extended_mode_xhdl24) AND CONV_STD_LOGIC(addr = "00010010")) OR (extended_mode_xhdl24 AND CONV_STD_LOGIC(addr = "00011000")))) AND transmit_buffer_status ;
we_tx_data_9 <= (((cs AND we) AND (NOT reset_mode_xhdl3)) AND (((NOT extended_mode_xhdl24) AND CONV_STD_LOGIC(addr = "00010011")) OR (extended_mode_xhdl24 AND CONV_STD_LOGIC(addr = "00011001")))) AND transmit_buffer_status ;
we_tx_data_10 <= (((cs AND we) AND (NOT reset_mode_xhdl3)) AND (extended_mode_xhdl24 AND CONV_STD_LOGIC(addr = "00011010"))) AND transmit_buffer_status ;
we_tx_data_11 <= (((cs AND we) AND (NOT reset_mode_xhdl3)) AND (extended_mode_xhdl24 AND CONV_STD_LOGIC(addr = "00011011"))) AND transmit_buffer_status ;
we_tx_data_12 <= (((cs AND we) AND (NOT reset_mode_xhdl3)) AND (extended_mode_xhdl24 AND CONV_STD_LOGIC(addr = "00011100"))) AND transmit_buffer_status ;
we_interrupt_enable <= ((cs AND we) AND CONV_STD_LOGIC(addr = "00000100")) AND extended_mode_xhdl24 ;
we_error_warning_limit <= (((cs AND we) AND CONV_STD_LOGIC(addr = "00001101")) AND reset_mode_xhdl3) AND extended_mode_xhdl24 ;
we_rx_err_cnt_xhdl22 <= (((cs AND we) AND CONV_STD_LOGIC(addr = "00001110")) AND reset_mode_xhdl3) AND extended_mode_xhdl24 ;
we_tx_err_cnt_xhdl23 <= (((cs AND we) AND CONV_STD_LOGIC(addr = "00001111")) AND reset_mode_xhdl3) AND extended_mode_xhdl24 ;
we_acceptance_code_1 <= (((cs AND we) AND CONV_STD_LOGIC(addr = "00010001")) AND reset_mode_xhdl3) AND extended_mode_xhdl24 ;
we_acceptance_code_2 <= (((cs AND we) AND CONV_STD_LOGIC(addr = "00010010")) AND reset_mode_xhdl3) AND extended_mode_xhdl24 ;
we_acceptance_code_3 <= (((cs AND we) AND CONV_STD_LOGIC(addr = "00010011")) AND reset_mode_xhdl3) AND extended_mode_xhdl24 ;
we_acceptance_mask_1 <= (((cs AND we) AND CONV_STD_LOGIC(addr = "00010101")) AND reset_mode_xhdl3) AND extended_mode_xhdl24 ;
we_acceptance_mask_2 <= (((cs AND we) AND CONV_STD_LOGIC(addr = "00010110")) AND reset_mode_xhdl3) AND extended_mode_xhdl24 ;
we_acceptance_mask_3 <= (((cs AND we) AND CONV_STD_LOGIC(addr = "00010111")) AND reset_mode_xhdl3) AND extended_mode_xhdl24 ;
-- End: This section is for EXTENDED mode
PROCESS (clk)
BEGIN
IF (clk'EVENT AND clk = '1') THEN
read_irq_reg_q <= read_irq_reg;
tx_successful_q <= tx_successful ;
overrun_q <= overrun ;
transmit_buffer_status_q <= transmit_buffer_status ;
error_status_q <= error_status ;
node_bus_off_q <= node_bus_off ;
node_error_passive_q <= node_error_passive ;
END IF;
END PROCESS;
port_xhdl52 <= data_in(0);
MODE_REG0 : can_register_asyn_syn
GENERIC MAP (1, 1)
PORT MAP (
data_in(0) => port_xhdl52,
data_out(0) => mode,
we => we_mode,
clk => clk,
rst => rst,
rst_sync => set_reset_mode);
MODE_REG_BASIC : can_register_asyn
GENERIC MAP (4, 0)
PORT MAP (
data_in => data_in(4 DOWNTO 1),
data_out => mode_basic(4 DOWNTO 1),
we => we_mode,
clk => clk,
rst => rst);
xhdl_61 <= (we_mode AND reset_mode_xhdl3);
MODE_REG_EXT : can_register_asyn
GENERIC MAP (3, 0)
PORT MAP (
data_in => data_in(3 DOWNTO 1),
data_out => mode_ext(3 DOWNTO 1),
we => xhdl_61,
clk => clk,
rst => rst);
reset_mode_xhdl3 <= mode ;
listen_only_mode_xhdl4 <= extended_mode_xhdl24 AND mode_ext(1) ;
self_test_mode_xhdl6 <= extended_mode_xhdl24 AND mode_ext(2) ;
acceptance_filter_mode_xhdl5 <= extended_mode_xhdl24 AND mode_ext(3) ;
receive_irq_en_basic <= mode_basic(1) ;
transmit_irq_en_basic <= mode_basic(2) ;
error_irq_en_basic <= mode_basic(3) ;
overrun_irq_en_basic <= mode_basic(4) ;
xhdl_69 <= (command(0) AND sample_point) OR reset_mode_xhdl3;
port_xhdl70 <= data_in(0);
command(0) <= port_xhdl71;
COMMAND_REG0 : can_register_asyn_syn
GENERIC MAP (1, 0)
PORT MAP (
data_in(0) => port_xhdl70,
data_out(0) => port_xhdl71,
we => we_command,
clk => clk,
rst => rst,
rst_sync => xhdl_69);
xhdl_77 <= (sample_point AND (tx_request_xhdl10 OR (abort_tx_xhdl9 AND NOT transmitting))) OR reset_mode_xhdl3;
port_xhdl78 <= data_in(1);
command(1) <= port_xhdl79;
COMMAND_REG1 : can_register_asyn_syn
GENERIC MAP (1, 0)
PORT MAP (
data_in(0) => port_xhdl78,
data_out(0) => port_xhdl79,
we => we_command,
clk => clk,
rst => rst,
rst_sync => xhdl_77);
xhdl_85 <= orv(command(3 DOWNTO 2)) OR reset_mode_xhdl3;
COMMAND_REG : can_register_asyn_syn
GENERIC MAP (2, 0)
PORT MAP (
data_in => data_in(3 DOWNTO 2),
data_out => command(3 DOWNTO 2),
we => we_command,
clk => clk,
rst => rst,
rst_sync => xhdl_85);
xhdl_91 <= (command(4) AND sample_point) OR reset_mode_xhdl3;
port_xhdl92 <= data_in(4);
command(4) <= port_xhdl93;
COMMAND_REG4 : can_register_asyn_syn
GENERIC MAP (1, 0)
PORT MAP (
data_in(0) => port_xhdl92,
data_out(0) => port_xhdl93,
we => we_command,
clk => clk,
rst => rst,
rst_sync => xhdl_91);
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
self_rx_request_xhdl11 <= '0';
ELSif clk'event and clk = '1' then
IF ((command(4) AND (NOT command(0))) = '1') THEN
self_rx_request_xhdl11 <= '1' ;
ELSE
IF (((NOT tx_state) AND tx_state_q) = '1') THEN
self_rx_request_xhdl11 <= '0' ;
END IF;
END IF;
END IF;
END PROCESS;
clear_data_overrun_xhdl7 <= command(3) ;
release_buffer_xhdl8 <= command(2) ;
tx_request_xhdl10 <= command(0) OR command(4) ;
abort_tx_xhdl9 <= command(1) AND (NOT tx_request_xhdl10) ;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
single_shot_transmission_xhdl12 <= '0';
ELSif clk'event and clk = '1' then
IF (((tx_request_xhdl10 AND command(1)) AND sample_point) = '1') THEN
single_shot_transmission_xhdl12 <= '1' ;
ELSE
IF (((NOT tx_state) AND tx_state_q) = '1') THEN
single_shot_transmission_xhdl12 <= '0' ;
END IF;
END IF;
END IF;
END PROCESS;
--
-- can_register_asyn_syn #(1, 1'h0) COMMAND_REG_OVERLOAD // Uncomment this to enable overload requests !!!
-- ( .data_in(data_in[5]),
-- .data_out(overload_request),
-- .we(we_command),
-- .clk(clk),
-- .rst(rst),
-- .rst_sync(overload_frame & ~overload_frame_q)
-- );
-- reg overload_frame_q;
-- always @ (posedge clk or posedge rst)
-- begin
-- if (rst)
-- overload_frame_q <= 1'b0;
-- else
-- overload_frame_q <=#Tp overload_frame;
-- end
--
overload_request_xhdl13 <= '0' ;
status(7) <= node_bus_off ;
status(6) <= error_status ;
status(5) <= transmit_status ;
status(4) <= receive_status ;
status(3) <= transmission_complete ;
status(2) <= transmit_buffer_status ;
status(1) <= overrun_status ;
status(0) <= receive_buffer_status ;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
transmission_complete <= '1';
ELSif clk'event and clk = '1' then
IF ((tx_successful AND ((NOT tx_successful_q) OR abort_tx_xhdl9)) = '1') THEN
-- transmission_complete was always set when abort_tx=1
-- Original code:
-- IF (((tx_successful AND (NOT tx_successful_q)) OR abort_tx_xhdl9) = '1') THEN
transmission_complete <= '1' ;
ELSE
IF (tx_request_xhdl10 = '1') THEN
transmission_complete <= '0' ;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
transmit_buffer_status <= '1';
ELSif clk'event and clk = '1' then
IF (tx_request_xhdl10 = '1') THEN
transmit_buffer_status <= '0' ;
ELSE
IF ((reset_mode_xhdl3 OR NOT need_to_tx) = '1') THEN
transmit_buffer_status <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
overrun_status <= '0';
ELSif clk'event and clk = '1' then
IF ((overrun AND (NOT overrun_q)) = '1') THEN
overrun_status <= '1' ;
ELSE
IF ((reset_mode_xhdl3 OR clear_data_overrun_xhdl7) = '1') THEN
overrun_status <= '0' ;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
receive_buffer_status <= '0';
ELSif clk'event and clk = '1' then
IF ((reset_mode_xhdl3 OR release_buffer_xhdl8) = '1') THEN
receive_buffer_status <= '0' ;
ELSE
IF (NOT info_empty = '1') THEN
receive_buffer_status <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
IRQ_EN_REG : can_register
GENERIC MAP (8)
PORT MAP (
data_in => data_in,
data_out => irq_en_ext,
we => we_interrupt_enable,
clk => clk);
bus_error_irq_en <= irq_en_ext(7) ;
arbitration_lost_irq_en <= irq_en_ext(6) ;
error_passive_irq_en <= irq_en_ext(5) ;
data_overrun_irq_en_ext <= irq_en_ext(3) ;
error_warning_irq_en_ext <= irq_en_ext(2) ;
transmit_irq_en_ext <= irq_en_ext(1) ;
receive_irq_en_ext <= irq_en_ext(0) ;
BUS_TIMING_0_REG : can_register
GENERIC MAP (8)
PORT MAP (
data_in => data_in,
data_out => bus_timing_0,
we => we_bus_timing_0,
clk => clk);
baud_r_presc_xhdl16 <= bus_timing_0(5 DOWNTO 0) ;
sync_jump_width_xhdl17 <= bus_timing_0(7 DOWNTO 6) ;
BUS_TIMING_1_REG : can_register
GENERIC MAP (8)
PORT MAP (
data_in => data_in,
data_out => bus_timing_1,
we => we_bus_timing_1,
clk => clk);
time_segment1_xhdl18 <= bus_timing_1(3 DOWNTO 0) ;
time_segment2_xhdl19 <= bus_timing_1(6 DOWNTO 4) ;
triple_sampling_xhdl20 <= bus_timing_1(7) ;
-- End Bus Timing 1 register -- Error Warning Limit register
ERROR_WARNING_REG : can_register_asyn
GENERIC MAP (8, 96)
PORT MAP (
data_in => data_in,
data_out => error_warning_limit_xhdl21,
we => we_error_warning_limit,
clk => clk,
rst => rst);
port_xhdl116 <= data_in(7);
clock_divider(7) <= port_xhdl117;
CLOCK_DIVIDER_REG_7 : can_register_asyn
GENERIC MAP (1, 0)
PORT MAP (
data_in(0) => port_xhdl116,
data_out(0) => port_xhdl117,
we => we_clock_divider_hi,
clk => clk,
rst => rst);
clock_divider(6 DOWNTO 4) <= "000" ;
port_xhdl123 <= data_in(3);
clock_divider(3) <= port_xhdl124;
CLOCK_DIVIDER_REG_3 : can_register_asyn
GENERIC MAP (1, 0)
PORT MAP (
data_in(0) => port_xhdl123,
data_out(0) => port_xhdl124,
we => we_clock_divider_hi,
clk => clk,
rst => rst);
CLOCK_DIVIDER_REG_LOW : can_register_asyn
GENERIC MAP (3, 0)
PORT MAP (
data_in => data_in(2 DOWNTO 0),
data_out => clock_divider(2 DOWNTO 0),
we => we_clock_divider_low,
clk => clk,
rst => rst);
extended_mode_xhdl24 <= clock_divider(7) ;
clock_off <= clock_divider(3) ;
cd(2 DOWNTO 0) <= clock_divider(2 DOWNTO 0) ;
PROCESS (cd)
VARIABLE clkout_div_xhdl130 : std_logic_vector(2 DOWNTO 0);
BEGIN
CASE cd IS
-- synthesis full_case parallel_case
WHEN "000" =>
clkout_div_xhdl130 := "000";
WHEN "001" =>
clkout_div_xhdl130 := "001";
WHEN "010" =>
clkout_div_xhdl130 := "010";
WHEN "011" =>
clkout_div_xhdl130 := "011";
WHEN "100" =>
clkout_div_xhdl130 := "100";
WHEN "101" =>
clkout_div_xhdl130 := "101";
WHEN "110" =>
clkout_div_xhdl130 := "110";
WHEN "111" =>
clkout_div_xhdl130 := "000";
WHEN OTHERS =>
NULL;
END CASE;
clkout_div <= clkout_div_xhdl130;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
clkout_cnt <= "000";
ELSif clk'event and clk = '1' then
IF (clkout_cnt = clkout_div) THEN
clkout_cnt <= "000" ;
ELSE
clkout_cnt <= clkout_cnt + "001";
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
clkout_tmp <= '0';
ELSif clk'event and clk = '1' then
IF (clkout_cnt = clkout_div) THEN
clkout_tmp <= NOT clkout_tmp ;
END IF;
END IF;
END PROCESS;
temp_xhdl131 <= clk WHEN (andv(cd)) = '1' ELSE clkout_tmp;
temp_xhdl132 <= '1' WHEN clock_off = '1' ELSE (temp_xhdl131);
clkout_xhdl25 <= temp_xhdl132 ;
-- End Clock Divider register -- This section is for BASIC and EXTENDED mode -- Acceptance code register
ACCEPTANCE_CODE_REG0 : can_register
GENERIC MAP (8)
PORT MAP (
data_in => data_in,
data_out => acceptance_code_0_xhdl26,
we => we_acceptance_code_0,
clk => clk);
-- End: Acceptance code register -- Acceptance mask register
ACCEPTANCE_MASK_REG0 : can_register
GENERIC MAP (8)
PORT MAP (
data_in => data_in,
data_out => acceptance_mask_0_xhdl27,
we => we_acceptance_mask_0,
clk => clk);
-- End: Acceptance mask register -- End: This section is for BASIC and EXTENDED mode -- Tx data 0 register.
TX_DATA_REG0 : can_register
GENERIC MAP (8)
PORT MAP (
data_in => data_in,
data_out => tx_data_0_xhdl34,
we => we_tx_data_0,
clk => clk);
-- End: Tx data 0 register. -- Tx data 1 register.
TX_DATA_REG1 : can_register
GENERIC MAP (8)
PORT MAP (
data_in => data_in,
data_out => tx_data_1_xhdl35,
we => we_tx_data_1,
clk => clk);
-- End: Tx data 1 register. -- Tx data 2 register.
TX_DATA_REG2 : can_register
GENERIC MAP (8)
PORT MAP (
data_in => data_in,
data_out => tx_data_2_xhdl36,
we => we_tx_data_2,
clk => clk);
-- End: Tx data 2 register. -- Tx data 3 register.
TX_DATA_REG3 : can_register
GENERIC MAP (8)
PORT MAP (
data_in => data_in,
data_out => tx_data_3_xhdl37,
we => we_tx_data_3,
clk => clk);
-- End: Tx data 3 register. -- Tx data 4 register.
TX_DATA_REG4 : can_register
GENERIC MAP (8)
PORT MAP (
data_in => data_in,
data_out => tx_data_4_xhdl38,
we => we_tx_data_4,
clk => clk);
-- End: Tx data 4 register. -- Tx data 5 register.
TX_DATA_REG5 : can_register
GENERIC MAP (8)
PORT MAP (
data_in => data_in,
data_out => tx_data_5_xhdl39,
we => we_tx_data_5,
clk => clk);
-- End: Tx data 5 register. -- Tx data 6 register.
TX_DATA_REG6 : can_register
GENERIC MAP (8)
PORT MAP (
data_in => data_in,
data_out => tx_data_6_xhdl40,
we => we_tx_data_6,
clk => clk);
-- End: Tx data 6 register. -- Tx data 7 register.
TX_DATA_REG7 : can_register
GENERIC MAP (8)
PORT MAP (
data_in => data_in,
data_out => tx_data_7_xhdl41,
we => we_tx_data_7,
clk => clk);
-- End: Tx data 7 register. -- Tx data 8 register.
TX_DATA_REG8 : can_register
GENERIC MAP (8)
PORT MAP (
data_in => data_in,
data_out => tx_data_8_xhdl42,
we => we_tx_data_8,
clk => clk);
-- End: Tx data 8 register. -- Tx data 9 register.
TX_DATA_REG9 : can_register
GENERIC MAP (8)
PORT MAP (
data_in => data_in,
data_out => tx_data_9_xhdl43,
we => we_tx_data_9,
clk => clk);
-- End: Tx data 9 register. -- Tx data 10 register.
TX_DATA_REG10 : can_register
GENERIC MAP (8)
PORT MAP (
data_in => data_in,
data_out => tx_data_10_xhdl44,
we => we_tx_data_10,
clk => clk);
-- End: Tx data 10 register. -- Tx data 11 register.
TX_DATA_REG11 : can_register
GENERIC MAP (8)
PORT MAP (
data_in => data_in,
data_out => tx_data_11_xhdl45,
we => we_tx_data_11,
clk => clk);
-- End: Tx data 11 register. -- Tx data 12 register.
TX_DATA_REG12 : can_register
GENERIC MAP (8)
PORT MAP (
data_in => data_in,
data_out => tx_data_12_xhdl46,
we => we_tx_data_12,
clk => clk);
-- End: Tx data 12 register. -- This section is for EXTENDED mode -- Acceptance code register 1
ACCEPTANCE_CODE_REG1 : can_register
GENERIC MAP (8)
PORT MAP (
data_in => data_in,
data_out => acceptance_code_1_xhdl28,
we => we_acceptance_code_1,
clk => clk);
-- End: Acceptance code register -- Acceptance code register 2
ACCEPTANCE_CODE_REG2 : can_register
GENERIC MAP (8)
PORT MAP (
data_in => data_in,
data_out => acceptance_code_2_xhdl29,
we => we_acceptance_code_2,
clk => clk);
-- End: Acceptance code register -- Acceptance code register 3
ACCEPTANCE_CODE_REG3 : can_register
GENERIC MAP (8)
PORT MAP (
data_in => data_in,
data_out => acceptance_code_3_xhdl30,
we => we_acceptance_code_3,
clk => clk);
-- End: Acceptance code register -- Acceptance mask register 1
ACCEPTANCE_MASK_REG1 : can_register
GENERIC MAP (8)
PORT MAP (
data_in => data_in,
data_out => acceptance_mask_1_xhdl31,
we => we_acceptance_mask_1,
clk => clk);
-- End: Acceptance code register -- Acceptance mask register 2
ACCEPTANCE_MASK_REG2 : can_register
GENERIC MAP (8)
PORT MAP (
data_in => data_in,
data_out => acceptance_mask_2_xhdl32,
we => we_acceptance_mask_2,
clk => clk);
-- End: Acceptance code register -- Acceptance mask register 3
ACCEPTANCE_MASK_REG3 : can_register
GENERIC MAP (8)
PORT MAP (
data_in => data_in,
data_out => acceptance_mask_3_xhdl33,
we => we_acceptance_mask_3,
clk => clk);
temp_xhdl218 <= acceptance_code_0_xhdl26 WHEN reset_mode_xhdl3 = '1' ELSE "11111111";
temp_xhdl219 <= acceptance_mask_0_xhdl27 WHEN reset_mode_xhdl3 = '1' ELSE "11111111";
temp_xhdl220 <= bus_timing_0 WHEN reset_mode_xhdl3 = '1' ELSE "11111111";
temp_xhdl221 <= bus_timing_1 WHEN reset_mode_xhdl3 = '1' ELSE "11111111";
temp_xhdl222 <= "11111111" WHEN reset_mode_xhdl3 = '1' ELSE tx_data_0_xhdl34;
temp_xhdl223 <= "11111111" WHEN reset_mode_xhdl3 = '1' ELSE tx_data_1_xhdl35;
temp_xhdl224 <= "11111111" WHEN reset_mode_xhdl3 = '1' ELSE tx_data_2_xhdl36;
temp_xhdl225 <= "11111111" WHEN reset_mode_xhdl3 = '1' ELSE tx_data_3_xhdl37;
temp_xhdl226 <= "11111111" WHEN reset_mode_xhdl3 = '1' ELSE tx_data_4_xhdl38;
temp_xhdl227 <= "11111111" WHEN reset_mode_xhdl3 = '1' ELSE tx_data_5_xhdl39;
temp_xhdl228 <= "11111111" WHEN reset_mode_xhdl3 = '1' ELSE tx_data_6_xhdl40;
temp_xhdl229 <= "11111111" WHEN reset_mode_xhdl3 = '1' ELSE tx_data_7_xhdl41;
temp_xhdl230 <= "11111111" WHEN reset_mode_xhdl3 = '1' ELSE tx_data_8_xhdl42;
temp_xhdl231 <= "11111111" WHEN reset_mode_xhdl3 = '1' ELSE tx_data_9_xhdl43;
-- End: Acceptance code register -- End: This section is for EXTENDED mode -- Reading data from registers
PROCESS (addr, extended_mode_xhdl24, mode, bus_timing_0, bus_timing_1, clock_divider,
acceptance_code_0_xhdl26, acceptance_code_1_xhdl28, acceptance_code_2_xhdl29,
acceptance_code_3_xhdl30, acceptance_mask_0_xhdl27, acceptance_mask_1_xhdl31,
acceptance_mask_2_xhdl32, acceptance_mask_3_xhdl33, status,
error_warning_limit_xhdl21, rx_err_cnt, tx_err_cnt, irq_en_ext, irq_reg, mode_ext,
arbitration_lost_capture, rx_message_counter, mode_basic, error_capture_code,
temp_xhdl218, temp_xhdl219, temp_xhdl220, temp_xhdl221, temp_xhdl222, temp_xhdl223,
temp_xhdl224, temp_xhdl225, temp_xhdl226, temp_xhdl227, temp_xhdl228, temp_xhdl229,
temp_xhdl230, temp_xhdl231
)
VARIABLE data_out_xhdl1_xhdl217 : std_logic_vector(7 DOWNTO 0);
VARIABLE temp_xhdl232 : std_logic_vector(5 DOWNTO 0);
BEGIN
temp_xhdl232 := extended_mode_xhdl24 & addr(4 DOWNTO 0);
CASE temp_xhdl232 IS
WHEN "100000" =>
data_out_xhdl1_xhdl217 := "0000" & mode_ext(3 DOWNTO 1) & mode; -- extended mode
WHEN "100001" =>
data_out_xhdl1_xhdl217 := "00000000"; -- extended mode
WHEN "100010" =>
data_out_xhdl1_xhdl217 := status; -- extended mode
WHEN "100011" =>
data_out_xhdl1_xhdl217 := irq_reg; -- extended mode
WHEN "100100" =>
data_out_xhdl1_xhdl217 := irq_en_ext; -- extended mode
WHEN "100110" =>
data_out_xhdl1_xhdl217 := bus_timing_0; -- extended mode
WHEN "100111" =>
data_out_xhdl1_xhdl217 := bus_timing_1; -- extended mode
WHEN "101011" =>
data_out_xhdl1_xhdl217 := "000" & arbitration_lost_capture(4 DOWNTO 0); -- extended mode
WHEN "101100" =>
data_out_xhdl1_xhdl217 := error_capture_code; -- extended mode
WHEN "101101" =>
data_out_xhdl1_xhdl217 := error_warning_limit_xhdl21; -- extended mode
WHEN "101110" =>
data_out_xhdl1_xhdl217 := rx_err_cnt; -- extended mode
WHEN "101111" =>
data_out_xhdl1_xhdl217 := tx_err_cnt; -- extended mode
WHEN "110000" =>
data_out_xhdl1_xhdl217 := acceptance_code_0_xhdl26; -- extended mode
WHEN "110001" =>
data_out_xhdl1_xhdl217 := acceptance_code_1_xhdl28; -- extended mode
WHEN "110010" =>
data_out_xhdl1_xhdl217 := acceptance_code_2_xhdl29; -- extended mode
WHEN "110011" =>
data_out_xhdl1_xhdl217 := acceptance_code_3_xhdl30; -- extended mode
WHEN "110100" =>
data_out_xhdl1_xhdl217 := acceptance_mask_0_xhdl27; -- extended mode
WHEN "110101" =>
data_out_xhdl1_xhdl217 := acceptance_mask_1_xhdl31; -- extended mode
WHEN "110110" =>
data_out_xhdl1_xhdl217 := acceptance_mask_2_xhdl32; -- extended mode
WHEN "110111" =>
data_out_xhdl1_xhdl217 := acceptance_mask_3_xhdl33; -- extended mode
WHEN "111000" =>
data_out_xhdl1_xhdl217 := "00000000"; -- extended mode
WHEN "111001" =>
data_out_xhdl1_xhdl217 := "00000000"; -- extended mode
WHEN "111010" =>
data_out_xhdl1_xhdl217 := "00000000"; -- extended mode
WHEN "111011" =>
data_out_xhdl1_xhdl217 := "00000000"; -- extended mode
WHEN "111100" =>
data_out_xhdl1_xhdl217 := "00000000"; -- extended mode
WHEN "111101" =>
data_out_xhdl1_xhdl217 := '0' & rx_message_counter; -- extended mode
WHEN "111111" =>
data_out_xhdl1_xhdl217 := clock_divider; -- extended mode
WHEN "000000" =>
data_out_xhdl1_xhdl217 := "001" & mode_basic(4 DOWNTO 1) & mode; -- basic mode
WHEN "000001" =>
data_out_xhdl1_xhdl217 := "11111111"; -- basic mode
WHEN "000010" =>
data_out_xhdl1_xhdl217 := status; -- basic mode
WHEN "000011" =>
data_out_xhdl1_xhdl217 := "1110" & irq_reg(3 DOWNTO 0); -- basic mode
WHEN "000100" =>
data_out_xhdl1_xhdl217 := temp_xhdl218;
WHEN "000101" =>
data_out_xhdl1_xhdl217 := temp_xhdl219;
WHEN "000110" =>
data_out_xhdl1_xhdl217 := temp_xhdl220;
WHEN "000111" =>
data_out_xhdl1_xhdl217 := temp_xhdl221;
WHEN "001010" =>
data_out_xhdl1_xhdl217 := temp_xhdl222;
WHEN "001011" =>
data_out_xhdl1_xhdl217 := temp_xhdl223;
WHEN "001100" =>
data_out_xhdl1_xhdl217 := temp_xhdl224;
WHEN "001101" =>
data_out_xhdl1_xhdl217 := temp_xhdl225;
WHEN "001110" =>
data_out_xhdl1_xhdl217 := temp_xhdl226;
WHEN "001111" =>
data_out_xhdl1_xhdl217 := temp_xhdl227;
WHEN "010000" =>
data_out_xhdl1_xhdl217 := temp_xhdl228;
WHEN "010001" =>
data_out_xhdl1_xhdl217 := temp_xhdl229;
WHEN "010010" =>
data_out_xhdl1_xhdl217 := temp_xhdl230;
WHEN "010011" =>
data_out_xhdl1_xhdl217 := temp_xhdl231;
WHEN "011111" =>
data_out_xhdl1_xhdl217 := clock_divider; -- basic mode
WHEN OTHERS =>
data_out_xhdl1_xhdl217 := "00000000"; -- the rest is read as 0
END CASE;
data_out_xhdl1 <= data_out_xhdl1_xhdl217;
END PROCESS;
temp_xhdl233 <= data_overrun_irq_en_ext WHEN extended_mode_xhdl24 = '1' ELSE overrun_irq_en_basic;
data_overrun_irq_en <= temp_xhdl233 ;
temp_xhdl234 <= error_warning_irq_en_ext WHEN extended_mode_xhdl24 = '1' ELSE error_irq_en_basic;
error_warning_irq_en <= temp_xhdl234 ;
temp_xhdl235 <= transmit_irq_en_ext WHEN extended_mode_xhdl24 = '1' ELSE transmit_irq_en_basic;
transmit_irq_en <= temp_xhdl235 ;
temp_xhdl236 <= receive_irq_en_ext WHEN extended_mode_xhdl24 = '1' ELSE receive_irq_en_basic;
receive_irq_en <= temp_xhdl236 ;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
data_overrun_irq <= '0';
ELSif clk'event and clk = '1' then
IF (((overrun AND (NOT overrun_q)) AND data_overrun_irq_en) = '1') THEN
data_overrun_irq <= '1' ;
ELSE
IF ((reset_mode_xhdl3 OR reset_irq_reg) = '1') THEN
data_overrun_irq <= '0' ;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
transmit_irq <= '0';
ELSif clk'event and clk = '1' then
IF (reset_mode_xhdl3 = '1') THEN
transmit_irq <= '0' ;
ELSE
IF (((transmit_buffer_status AND (NOT transmit_buffer_status_q)) AND transmit_irq_en) = '1') THEN
transmit_irq <= '1' ;
elsif (reset_irq_reg = '1') then
transmit_irq <= '0';
end if;
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
receive_irq <= '0';
ELSif clk'event and clk = '1' then
IF ((((NOT info_empty) AND (NOT receive_irq)) AND receive_irq_en) = '1') THEN
receive_irq <= '1' ;
ELSE
IF ((reset_mode_xhdl3 OR release_buffer_xhdl8) = '1') THEN
receive_irq <= '0' ;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
error_irq <= '0';
ELSif clk'event and clk = '1' then
IF ((((error_status XOR error_status_q) OR (node_bus_off XOR node_bus_off_q)) AND error_warning_irq_en) = '1') THEN
error_irq <= '1' ;
ELSE
IF (reset_irq_reg = '1') THEN
error_irq <= '0' ;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
bus_error_irq <= '0';
ELSif clk'event and clk = '1' then
IF ((set_bus_error_irq AND bus_error_irq_en) = '1') THEN
bus_error_irq <= '1' ;
ELSE
IF ((reset_mode_xhdl3 OR reset_irq_reg) = '1') THEN
bus_error_irq <= '0' ;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
arbitration_lost_irq <= '0';
ELSif clk'event and clk = '1' then
IF ((set_arbitration_lost_irq AND arbitration_lost_irq_en) = '1') THEN
arbitration_lost_irq <= '1' ;
ELSE
IF ((reset_mode_xhdl3 OR reset_irq_reg) = '1') THEN
arbitration_lost_irq <= '0' ;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
error_passive_irq <= '0';
ELSif clk'event and clk = '1' then
IF ((((node_error_passive AND (NOT node_error_passive_q)) OR (((NOT node_error_passive) AND node_error_passive_q) AND node_error_active)) AND error_passive_irq_en) = '1') THEN
error_passive_irq <= '1' ;
ELSE
IF ((reset_mode_xhdl3 OR reset_irq_reg) = '1') THEN
error_passive_irq <= '0' ;
END IF;
END IF;
END IF;
END PROCESS;
irq_reg <= bus_error_irq & arbitration_lost_irq & error_passive_irq & '0' & data_overrun_irq & error_irq & transmit_irq & receive_irq ;
irq <= data_overrun_irq OR transmit_irq OR receive_irq OR error_irq OR bus_error_irq OR arbitration_lost_irq OR error_passive_irq ;
-- irq_o reset change /Kristoffer 2006-02-23 PROCESS (clk, rst)
-- BEGIN
-- IF (rst = '1') THEN
-- irq_n_xhdl2 <= '1';
-- ELSif clk'event and clk = '1' then
-- IF (reset_irq_reg = '1' or release_buffer_xhdl8='1') THEN
-- irq_n_xhdl2 <= '1';
-- ELSE
-- IF (irq = '1') THEN
-- irq_n_xhdl2 <= '0' ;
-- END IF;
-- END IF;
-- END IF;
-- END PROCESS;
PROCESS (clk, rst, release_buffer_xhdl8)
BEGIN
IF (rst = '1' or release_buffer_xhdl8 = '1') THEN
irq_n_xhdl2 <= '1';
ELSif clk'event and clk = '1' then
irq_n_xhdl2 <= not irq;
END IF;
END PROCESS;
END ARCHITECTURE RTL;
----------------------------------------------------------------------------------------------
--
-- VHDL file generated by X-HDL - Revision 3.2.53 Aug. 1, 2005
-- Tue Aug 9 07:33:50 2005
--
-- Input file : C:/Documents and Settings/BryantI/My Documents/tmp/can_top.v
-- Design name : can_top
-- Author :
-- Company : Actel
--
-- Description :
--
--
----------------------------------------------------------------------------------------------
--
--////////////////////////////////////////////////////////////////////
--// ////
--// can_top.v ////
--// ////
--// ////
--// This file is part of the CAN Protocol Controller ////
--// http://www.opencores.org/projects/can/ ////
--// ////
--// ////
--// Author(s): ////
--// Igor Mohor ////
--// [email protected] ////
--// ////
--// ////
--// All additional information is available in the README.txt ////
--// file. ////
--// ////
--////////////////////////////////////////////////////////////////////
--// ////
--// Copyright (C) 2002, 2003, 2004 Authors ////
--// ////
--// This source file may be used and distributed without ////
--// restriction provided that this copyright statement is not ////
--// removed from the file and that any derivative work contains ////
--// the original copyright notice and the associated disclaimer. ////
--// ////
--// This source file is free software; you can redistribute it ////
--// and/or modify it under the terms of the GNU Lesser General ////
--// Public License as published by the Free Software Foundation; ////
--// either version 2.1 of the License, or (at your option) any ////
--// later version. ////
--// ////
--// This source is distributed in the hope that it will be ////
--// useful, but WITHOUT ANY WARRANTY; without even the implied ////
--// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
--// PURPOSE. See the GNU Lesser General Public License for more ////
--// details. ////
--// ////
--// You should have received a copy of the GNU Lesser General ////
--// Public License along with this source; if not, download it ////
--// from http://www.opencores.org/lgpl.shtml ////
--// ////
--// The CAN protocol is developed by Robert Bosch GmbH and ////
--// protected by patents. Anybody who wants to implement this ////
--// CAN IP core on silicon has to obtain a CAN protocol license ////
--// from Bosch. ////
--// ////
--////////////////////////////////////////////////////////////////////
--
-- CVS Revision History
--
-- $Log: can_top.v,v $
-- Revision 1.48 2004/10/25 11:44:47 igorm
-- Interrupt is always cleared for one clock after the irq register is read.
-- This fixes problems when CPU is using IRQs that are edge triggered.
--
-- Revision 1.47 2004/02/08 14:53:54 mohor
-- Header changed. Address latched to posedge. bus_off_on signal added.
--
-- Revision 1.46 2003/10/17 05:55:20 markom
-- mbist signals updated according to newest convention
--
-- Revision 1.45 2003/09/30 00:55:13 mohor
-- Error counters fixed to be compatible with Bosch VHDL reference model.
-- Small synchronization changes.
--
-- Revision 1.44 2003/09/25 18:55:49 mohor
-- Synchronization changed, error counters fixed.
--
-- Revision 1.43 2003/08/20 09:57:39 mohor
-- Tristate signal tx_o is separated to tx_o and tx_oen_o. Both signals need
-- to be joined together on higher level.
--
-- Revision 1.42 2003/07/16 15:11:28 mohor
-- Fixed according to the linter.
--
-- Revision 1.41 2003/07/10 15:32:27 mohor
-- Unused signal removed.
--
-- Revision 1.40 2003/07/10 01:59:04 tadejm
-- Synchronization fixed. In some strange cases it didn't work according to
-- the VHDL reference model.
--
-- Revision 1.39 2003/07/07 11:21:37 mohor
-- Little fixes (to fix warnings).
--
-- Revision 1.38 2003/07/03 09:32:20 mohor
-- Synchronization changed.
--
-- Revision 1.37 2003/06/27 20:56:15 simons
-- Virtual silicon ram instances added.
--
-- Revision 1.36 2003/06/17 14:30:30 mohor
-- "chip select" signal cs_can_i is used only when not using WISHBONE
-- interface.
--
-- Revision 1.35 2003/06/16 13:57:58 mohor
-- tx_point generated one clk earlier. rx_i registered. Data corrected when
-- using extended mode.
--
-- Revision 1.34 2003/06/13 15:02:24 mohor
-- Synchronization is also needed when transmitting a message.
--
-- Revision 1.33 2003/06/11 14:21:35 mohor
-- When switching to tx, sync stage is overjumped.
--
-- Revision 1.32 2003/06/09 11:32:36 mohor
-- Ports added for the CAN_BIST.
--
-- Revision 1.31 2003/03/26 11:19:46 mohor
-- CAN interrupt is active low.
--
-- Revision 1.30 2003/03/20 17:01:17 mohor
-- unix.
--
-- Revision 1.28 2003/03/14 19:36:48 mohor
-- can_cs signal used for generation of the cs.
--
-- Revision 1.27 2003/03/12 05:56:33 mohor
-- Bidirectional port_0_i changed to port_0_io.
-- input cs_can changed to cs_can_i.
--
-- Revision 1.26 2003/03/12 04:39:40 mohor
-- rd_i and wr_i are active high signals. If 8051 is connected, these two signals
-- need to be negated one level higher.
--
-- Revision 1.25 2003/03/12 04:17:36 mohor
-- 8051 interface added (besides WISHBONE interface). Selection is made in
-- can_defines.v file.
--
-- Revision 1.24 2003/03/10 17:24:40 mohor
-- wire declaration added.
--
-- Revision 1.23 2003/03/05 15:33:13 mohor
-- tx_o is now tristated signal. tx_oen and tx_o combined together.
--
-- Revision 1.22 2003/03/05 15:01:56 mohor
-- Top level signal names changed.
--
-- Revision 1.21 2003/03/01 22:53:33 mohor
-- Actel APA ram supported.
--
-- Revision 1.20 2003/02/19 15:09:02 mohor
-- Incomplete sensitivity list fixed.
--
-- Revision 1.19 2003/02/19 15:04:14 mohor
-- Typo fixed.
--
-- Revision 1.18 2003/02/19 14:44:03 mohor
-- CAN core finished. Host interface added. Registers finished.
-- Synchronization to the wishbone finished.
--
-- Revision 1.17 2003/02/18 00:10:15 mohor
-- Most of the registers added. Registers "arbitration lost capture", "error code
-- capture" + few more still need to be added.
--
-- Revision 1.16 2003/02/14 20:17:01 mohor
-- Several registers added. Not finished, yet.
--
-- Revision 1.15 2003/02/12 14:25:30 mohor
-- abort_tx added.
--
-- Revision 1.14 2003/02/11 00:56:06 mohor
-- Wishbone interface added.
--
-- Revision 1.13 2003/02/09 18:40:29 mohor
-- Overload fixed. Hard synchronization also enabled at the last bit of
-- interframe.
--
-- Revision 1.12 2003/02/09 02:24:33 mohor
-- Bosch license warning added. Error counters finished. Overload frames
-- still need to be fixed.
--
-- Revision 1.11 2003/02/04 14:34:52 mohor
-- *** empty log message ***
--
-- Revision 1.10 2003/01/31 01:13:38 mohor
-- backup.
--
-- Revision 1.9 2003/01/15 13:16:48 mohor
-- When a frame with "remote request" is received, no data is stored to
-- fifo, just the frame information (identifier, ...). Data length that
-- is stored is the received data length and not the actual data length
-- that is stored to fifo.
--
-- Revision 1.8 2003/01/14 17:25:09 mohor
-- Addresses corrected to decimal values (previously hex).
--
-- Revision 1.7 2003/01/10 17:51:34 mohor
-- Temporary version (backup).
--
-- Revision 1.6 2003/01/09 21:54:45 mohor
-- rx fifo added. Not 100 % verified, yet.
--
-- Revision 1.5 2003/01/08 02:10:56 mohor
-- Acceptance filter added.
--
-- Revision 1.4 2002/12/28 04:13:23 mohor
-- Backup version.
--
-- Revision 1.3 2002/12/27 00:12:52 mohor
-- Header changed, testbench improved to send a frame (crc still missing).
--
-- Revision 1.2 2002/12/26 16:00:34 mohor
-- Testbench define file added. Clock divider register added.
--
-- Revision 1.1.1.1 2002/12/20 16:39:21 mohor
-- Initial
--
--
--
-- synopsys translate_off
--`include "can_defines.v"
-- synopsys translate_on
LIBRARY ieee;
USE ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
ENTITY can_top IS
PORT (
-- wb_clk_i : IN std_logic;
-- wb_rst_i : IN std_logic;
-- wb_dat_i : IN std_logic_vector(7 DOWNTO 0);
-- wb_dat_o : OUT std_logic_vector(7 DOWNTO 0);
-- wb_cyc_i : IN std_logic;
-- wb_stb_i : IN std_logic;
-- wb_we_i : IN std_logic;
-- wb_adr_i : IN std_logic_vector(7 DOWNTO 0);
-- wb_ack_o : OUT std_logic;
rst : IN std_logic;
addr : IN std_logic_vector(7 DOWNTO 0);
data_in : IN std_logic_vector(7 DOWNTO 0);
data_out : OUT std_logic_vector(7 DOWNTO 0);
cs : IN std_logic;
we : IN std_logic;
clk_i : IN std_logic;
rx_i : IN std_logic;
tx_o : OUT std_logic;
bus_off_on : OUT std_logic;
irq_on : OUT std_logic;
clkout_o : OUT std_logic;
-- Bist
-- port connections for Ram
--64x8
q_dp_64x8 : IN std_logic_vector(7 DOWNTO 0);
data_64x8 : OUT std_logic_vector(7 DOWNTO 0);
wren_64x8 : OUT std_logic;
rden_64x8 : OUT std_logic;
wraddress_64x8 : OUT std_logic_vector(5 DOWNTO 0);
rdaddress_64x8 : OUT std_logic_vector(5 DOWNTO 0);
--64x4
q_dp_64x4 : IN std_logic_vector(3 DOWNTO 0);
data_64x4 : OUT std_logic_vector(3 DOWNTO 0);
wren_64x4x1 : OUT std_logic;
wraddress_64x4x1 : OUT std_logic_vector(5 DOWNTO 0);
rdaddress_64x4x1 : OUT std_logic_vector(5 DOWNTO 0);
--64x1
q_dp_64x1 : IN std_logic;
data_64x1 : OUT std_logic);
END ENTITY can_top;
ARCHITECTURE RTL OF can_top IS
COMPONENT can_bsp
PORT (
clk : IN std_logic;
rst : IN std_logic;
sample_point : IN std_logic;
sampled_bit : IN std_logic;
sampled_bit_q : IN std_logic;
tx_point : IN std_logic;
hard_sync : IN std_logic;
addr : IN std_logic_vector(7 DOWNTO 0);
data_in : IN std_logic_vector(7 DOWNTO 0);
data_out : OUT std_logic_vector(7 DOWNTO 0);
fifo_selected : IN std_logic;
reset_mode : IN std_logic;
listen_only_mode : IN std_logic;
acceptance_filter_mode : IN std_logic;
self_test_mode : IN std_logic;
release_buffer : IN std_logic;
tx_request : IN std_logic;
abort_tx : IN std_logic;
self_rx_request : IN std_logic;
single_shot_transmission: IN std_logic;
tx_state : OUT std_logic;
tx_state_q : OUT std_logic;
overload_request : IN std_logic;
overload_frame : OUT std_logic;
read_arbitration_lost_capture_reg: IN std_logic;
read_error_code_capture_reg: IN std_logic;
error_capture_code : OUT std_logic_vector(7 DOWNTO 0);
error_warning_limit : IN std_logic_vector(7 DOWNTO 0);
we_rx_err_cnt : IN std_logic;
we_tx_err_cnt : IN std_logic;
extended_mode : IN std_logic;
rx_idle : OUT std_logic;
transmitting : OUT std_logic;
transmitter : OUT std_logic;
go_rx_inter : OUT std_logic;
not_first_bit_of_inter : OUT std_logic;
rx_inter : OUT std_logic;
set_reset_mode : OUT std_logic;
node_bus_off : OUT std_logic;
error_status : OUT std_logic;
rx_err_cnt : OUT std_logic_vector(8 DOWNTO 0);
tx_err_cnt : OUT std_logic_vector(8 DOWNTO 0);
transmit_status : OUT std_logic;
receive_status : OUT std_logic;
tx_successful : OUT std_logic;
need_to_tx : OUT std_logic;
overrun : OUT std_logic;
info_empty : OUT std_logic;
set_bus_error_irq : OUT std_logic;
set_arbitration_lost_irq: OUT std_logic;
arbitration_lost_capture: OUT std_logic_vector(4 DOWNTO 0);
node_error_passive : OUT std_logic;
node_error_active : OUT std_logic;
rx_message_counter : OUT std_logic_vector(6 DOWNTO 0);
acceptance_code_0 : IN std_logic_vector(7 DOWNTO 0);
acceptance_mask_0 : IN std_logic_vector(7 DOWNTO 0);
acceptance_code_1 : IN std_logic_vector(7 DOWNTO 0);
acceptance_code_2 : IN std_logic_vector(7 DOWNTO 0);
acceptance_code_3 : IN std_logic_vector(7 DOWNTO 0);
acceptance_mask_1 : IN std_logic_vector(7 DOWNTO 0);
acceptance_mask_2 : IN std_logic_vector(7 DOWNTO 0);
acceptance_mask_3 : IN std_logic_vector(7 DOWNTO 0);
tx_data_0 : IN std_logic_vector(7 DOWNTO 0);
tx_data_1 : IN std_logic_vector(7 DOWNTO 0);
tx_data_2 : IN std_logic_vector(7 DOWNTO 0);
tx_data_3 : IN std_logic_vector(7 DOWNTO 0);
tx_data_4 : IN std_logic_vector(7 DOWNTO 0);
tx_data_5 : IN std_logic_vector(7 DOWNTO 0);
tx_data_6 : IN std_logic_vector(7 DOWNTO 0);
tx_data_7 : IN std_logic_vector(7 DOWNTO 0);
tx_data_8 : IN std_logic_vector(7 DOWNTO 0);
tx_data_9 : IN std_logic_vector(7 DOWNTO 0);
tx_data_10 : IN std_logic_vector(7 DOWNTO 0);
tx_data_11 : IN std_logic_vector(7 DOWNTO 0);
tx_data_12 : IN std_logic_vector(7 DOWNTO 0);
tx : OUT std_logic;
tx_next : OUT std_logic;
bus_off_on : OUT std_logic;
go_overload_frame : OUT std_logic;
go_error_frame : OUT std_logic;
go_tx : OUT std_logic;
send_ack : OUT std_logic;
q_dp_64x8 : IN std_logic_vector(7 DOWNTO 0);
data_64x8 : OUT std_logic_vector(7 DOWNTO 0);
wren_64x8 : OUT std_logic;
rden_64x8 : OUT std_logic;
wraddress_64x8 : OUT std_logic_vector(5 DOWNTO 0);
rdaddress_64x8 : OUT std_logic_vector(5 DOWNTO 0);
q_dp_64x4 : IN std_logic_vector(3 DOWNTO 0);
data_64x4 : OUT std_logic_vector(3 DOWNTO 0);
wren_64x4x1 : OUT std_logic;
wraddress_64x4x1 : OUT std_logic_vector(5 DOWNTO 0);
rdaddress_64x4x1 : OUT std_logic_vector(5 DOWNTO 0);
q_dp_64x1 : IN std_logic;
data_64x1 : OUT std_logic);
END COMPONENT;
COMPONENT can_btl
PORT (
clk : IN std_logic;
rst : IN std_logic;
rx : IN std_logic;
tx : IN std_logic;
baud_r_presc : IN std_logic_vector(5 DOWNTO 0);
sync_jump_width : IN std_logic_vector(1 DOWNTO 0);
time_segment1 : IN std_logic_vector(3 DOWNTO 0);
time_segment2 : IN std_logic_vector(2 DOWNTO 0);
triple_sampling : IN std_logic;
sample_point : OUT std_logic;
sampled_bit : OUT std_logic;
sampled_bit_q : OUT std_logic;
tx_point : OUT std_logic;
hard_sync : OUT std_logic;
rx_idle : IN std_logic;
rx_inter : IN std_logic;
transmitting : IN std_logic;
transmitter : IN std_logic;
go_rx_inter : IN std_logic;
tx_next : IN std_logic;
go_overload_frame : IN std_logic;
go_error_frame : IN std_logic;
go_tx : IN std_logic;
send_ack : IN std_logic;
node_error_passive : IN std_logic);
END COMPONENT;
COMPONENT can_registers
PORT (
clk : IN std_logic;
rst : IN std_logic;
cs : IN std_logic;
we : IN std_logic;
addr : IN std_logic_vector(7 DOWNTO 0);
data_in : IN std_logic_vector(7 DOWNTO 0);
data_out : OUT std_logic_vector(7 DOWNTO 0);
irq_n : OUT std_logic;
sample_point : IN std_logic;
transmitting : IN std_logic;
set_reset_mode : IN std_logic;
node_bus_off : IN std_logic;
error_status : IN std_logic;
rx_err_cnt : IN std_logic_vector(7 DOWNTO 0);
tx_err_cnt : IN std_logic_vector(7 DOWNTO 0);
transmit_status : IN std_logic;
receive_status : IN std_logic;
tx_successful : IN std_logic;
need_to_tx : IN std_logic;
overrun : IN std_logic;
info_empty : IN std_logic;
set_bus_error_irq : IN std_logic;
set_arbitration_lost_irq: IN std_logic;
arbitration_lost_capture: IN std_logic_vector(4 DOWNTO 0);
node_error_passive : IN std_logic;
node_error_active : IN std_logic;
rx_message_counter : IN std_logic_vector(6 DOWNTO 0);
reset_mode : OUT std_logic;
listen_only_mode : OUT std_logic;
acceptance_filter_mode : OUT std_logic;
self_test_mode : OUT std_logic;
clear_data_overrun : OUT std_logic;
release_buffer : OUT std_logic;
abort_tx : OUT std_logic;
tx_request : OUT std_logic;
self_rx_request : OUT std_logic;
single_shot_transmission: OUT std_logic;
tx_state : IN std_logic;
tx_state_q : IN std_logic;
overload_request : OUT std_logic;
overload_frame : IN std_logic;
read_arbitration_lost_capture_reg: OUT std_logic;
read_error_code_capture_reg: OUT std_logic;
error_capture_code : IN std_logic_vector(7 DOWNTO 0);
baud_r_presc : OUT std_logic_vector(5 DOWNTO 0);
sync_jump_width : OUT std_logic_vector(1 DOWNTO 0);
time_segment1 : OUT std_logic_vector(3 DOWNTO 0);
time_segment2 : OUT std_logic_vector(2 DOWNTO 0);
triple_sampling : OUT std_logic;
error_warning_limit : OUT std_logic_vector(7 DOWNTO 0);
we_rx_err_cnt : OUT std_logic;
we_tx_err_cnt : OUT std_logic;
extended_mode : OUT std_logic;
clkout : OUT std_logic;
acceptance_code_0 : OUT std_logic_vector(7 DOWNTO 0);
acceptance_mask_0 : OUT std_logic_vector(7 DOWNTO 0);
acceptance_code_1 : OUT std_logic_vector(7 DOWNTO 0);
acceptance_code_2 : OUT std_logic_vector(7 DOWNTO 0);
acceptance_code_3 : OUT std_logic_vector(7 DOWNTO 0);
acceptance_mask_1 : OUT std_logic_vector(7 DOWNTO 0);
acceptance_mask_2 : OUT std_logic_vector(7 DOWNTO 0);
acceptance_mask_3 : OUT std_logic_vector(7 DOWNTO 0);
tx_data_0 : OUT std_logic_vector(7 DOWNTO 0);
tx_data_1 : OUT std_logic_vector(7 DOWNTO 0);
tx_data_2 : OUT std_logic_vector(7 DOWNTO 0);
tx_data_3 : OUT std_logic_vector(7 DOWNTO 0);
tx_data_4 : OUT std_logic_vector(7 DOWNTO 0);
tx_data_5 : OUT std_logic_vector(7 DOWNTO 0);
tx_data_6 : OUT std_logic_vector(7 DOWNTO 0);
tx_data_7 : OUT std_logic_vector(7 DOWNTO 0);
tx_data_8 : OUT std_logic_vector(7 DOWNTO 0);
tx_data_9 : OUT std_logic_vector(7 DOWNTO 0);
tx_data_10 : OUT std_logic_vector(7 DOWNTO 0);
tx_data_11 : OUT std_logic_vector(7 DOWNTO 0);
tx_data_12 : OUT std_logic_vector(7 DOWNTO 0));
END COMPONENT;
-- SIGNAL cs_sync1 : std_logic;
-- SIGNAL cs_sync2 : std_logic;
-- SIGNAL cs_sync3 : std_logic;
-- SIGNAL cs_ack1 : std_logic;
-- SIGNAL cs_ack2 : std_logic;
-- SIGNAL cs_ack3 : std_logic;
-- SIGNAL cs_sync_rst1 : std_logic;
-- SIGNAL cs_sync_rst2 : std_logic;
-- SIGNAL cs_can_i : std_logic;
---------------------------------
SIGNAL data_out_fifo_selected : std_logic;
SIGNAL data_out_fifo : std_logic_vector(7 DOWNTO 0);
SIGNAL data_out_regs : std_logic_vector(7 DOWNTO 0);
-- Mode register
SIGNAL reset_mode : std_logic;
SIGNAL listen_only_mode : std_logic;
SIGNAL acceptance_filter_mode : std_logic;
SIGNAL self_test_mode : std_logic;
-- Command register
SIGNAL release_buffer : std_logic;
SIGNAL tx_request : std_logic;
SIGNAL abort_tx : std_logic;
SIGNAL self_rx_request : std_logic;
SIGNAL single_shot_transmission : std_logic;
SIGNAL tx_state : std_logic;
SIGNAL tx_state_q : std_logic;
SIGNAL overload_request : std_logic;
SIGNAL overload_frame : std_logic;
-- Arbitration Lost Capture Register
SIGNAL read_arbitration_lost_capture_reg: std_logic;
-- Error Code Capture Register
SIGNAL read_error_code_capture_reg : std_logic;
SIGNAL error_capture_code : std_logic_vector(7 DOWNTO 0);
-- Bus Timing 0 register
SIGNAL baud_r_presc : std_logic_vector(5 DOWNTO 0);
SIGNAL sync_jump_width : std_logic_vector(1 DOWNTO 0);
-- Bus Timing 1 register
SIGNAL time_segment1 : std_logic_vector(3 DOWNTO 0);
SIGNAL time_segment2 : std_logic_vector(2 DOWNTO 0);
SIGNAL triple_sampling : std_logic;
-- Error Warning Limit register
SIGNAL error_warning_limit : std_logic_vector(7 DOWNTO 0);
-- Rx Error Counter register
SIGNAL we_rx_err_cnt : std_logic;
-- Tx Error Counter register
SIGNAL we_tx_err_cnt : std_logic;
-- Clock Divider register
SIGNAL extended_mode : std_logic;
-- This section is for BASIC and EXTENDED mode
-- Acceptance code register
SIGNAL acceptance_code_0 : std_logic_vector(7 DOWNTO 0);
-- Acceptance mask register
SIGNAL acceptance_mask_0 : std_logic_vector(7 DOWNTO 0);
-- End: This section is for BASIC and EXTENDED mode
-- This section is for EXTENDED mode
-- Acceptance code register
SIGNAL acceptance_code_1 : std_logic_vector(7 DOWNTO 0);
SIGNAL acceptance_code_2 : std_logic_vector(7 DOWNTO 0);
SIGNAL acceptance_code_3 : std_logic_vector(7 DOWNTO 0);
-- Acceptance mask register
SIGNAL acceptance_mask_1 : std_logic_vector(7 DOWNTO 0);
SIGNAL acceptance_mask_2 : std_logic_vector(7 DOWNTO 0);
SIGNAL acceptance_mask_3 : std_logic_vector(7 DOWNTO 0);
-- End: This section is for EXTENDED mode
-- Tx data registers. Holding identifier (basic mode), tx frame information (extended mode) and data
SIGNAL tx_data_0 : std_logic_vector(7 DOWNTO 0);
SIGNAL tx_data_1 : std_logic_vector(7 DOWNTO 0);
SIGNAL tx_data_2 : std_logic_vector(7 DOWNTO 0);
SIGNAL tx_data_3 : std_logic_vector(7 DOWNTO 0);
SIGNAL tx_data_4 : std_logic_vector(7 DOWNTO 0);
SIGNAL tx_data_5 : std_logic_vector(7 DOWNTO 0);
SIGNAL tx_data_6 : std_logic_vector(7 DOWNTO 0);
SIGNAL tx_data_7 : std_logic_vector(7 DOWNTO 0);
SIGNAL tx_data_8 : std_logic_vector(7 DOWNTO 0);
SIGNAL tx_data_9 : std_logic_vector(7 DOWNTO 0);
SIGNAL tx_data_10 : std_logic_vector(7 DOWNTO 0);
SIGNAL tx_data_11 : std_logic_vector(7 DOWNTO 0);
SIGNAL tx_data_12 : std_logic_vector(7 DOWNTO 0);
-- End: Tx data registers
-- SIGNAL cs : std_logic;
-- Output signals from can_btl module
SIGNAL sample_point : std_logic;
SIGNAL sampled_bit : std_logic;
SIGNAL sampled_bit_q : std_logic;
SIGNAL tx_point : std_logic;
SIGNAL hard_sync : std_logic;
-- output from can_bsp module
SIGNAL rx_idle : std_logic;
SIGNAL transmitting : std_logic;
SIGNAL transmitter : std_logic;
SIGNAL go_rx_inter : std_logic;
SIGNAL not_first_bit_of_inter : std_logic;
SIGNAL set_reset_mode : std_logic;
SIGNAL node_bus_off : std_logic;
SIGNAL error_status : std_logic;
SIGNAL rx_err_cnt : std_logic_vector(7 DOWNTO 0);
SIGNAL tx_err_cnt : std_logic_vector(7 DOWNTO 0);
SIGNAL rx_err_cnt_dummy : std_logic; -- The MSB is not displayed. It is just used for easier calculation (no counter overflow).
SIGNAL tx_err_cnt_dummy : std_logic; -- The MSB is not displayed. It is just used for easier calculation (no counter overflow).
SIGNAL transmit_status : std_logic;
SIGNAL receive_status : std_logic;
SIGNAL tx_successful : std_logic;
SIGNAL need_to_tx : std_logic;
SIGNAL overrun : std_logic;
SIGNAL info_empty : std_logic;
SIGNAL set_bus_error_irq : std_logic;
SIGNAL set_arbitration_lost_irq : std_logic;
SIGNAL arbitration_lost_capture : std_logic_vector(4 DOWNTO 0);
SIGNAL node_error_passive : std_logic;
SIGNAL node_error_active : std_logic;
SIGNAL rx_message_counter : std_logic_vector(6 DOWNTO 0);
SIGNAL tx_next : std_logic;
SIGNAL go_overload_frame : std_logic;
SIGNAL go_error_frame : std_logic;
SIGNAL go_tx : std_logic;
SIGNAL send_ack : std_logic;
-- SIGNAL rst : std_logic;
-- SIGNAL we : std_logic;
-- SIGNAL addr : std_logic_vector(7 DOWNTO 0);
-- SIGNAL data_in : std_logic_vector(7 DOWNTO 0);
-- SIGNAL data_out : std_logic_vector(7 DOWNTO 0);
SIGNAL rx_sync_tmp : std_logic;
SIGNAL rx_sync : std_logic;
-- port connections for Ram
--64x8
SIGNAL w_q_dp_64x8 : std_logic_vector(7 DOWNTO 0);
SIGNAL w_data_64x8 : std_logic_vector(7 DOWNTO 0);
SIGNAL w_wren_64x8 : std_logic;
SIGNAL w_rden_64x8 : std_logic;
SIGNAL w_wraddress_64x8 : std_logic_vector(5 DOWNTO 0);
SIGNAL w_rdaddress_64x8 : std_logic_vector(5 DOWNTO 0);
--64x4
SIGNAL w_q_dp_64x4 : std_logic_vector(3 DOWNTO 0);
SIGNAL w_data_64x4 : std_logic_vector(3 DOWNTO 0);
SIGNAL w_wren_64x4x1 : std_logic;
SIGNAL w_wraddress_64x4x1 : std_logic_vector(5 DOWNTO 0);
SIGNAL w_rdaddress_64x4x1 : std_logic_vector(5 DOWNTO 0);
--64x1
SIGNAL w_q_dp_64x1 : std_logic;
SIGNAL w_data_64x1 : std_logic;
-- From btl module
-- Mode register
-- Command register
-- Arbitration Lost Capture Register
-- Error Code Capture Register
-- Error Warning Limit register
-- Rx Error Counter register
-- Tx Error Counter register
-- Clock Divider register
-- output from can_bsp module
SIGNAL xhdl_148 : std_logic_vector(8 DOWNTO 0);
-- The MSB is not displayed. It is just used for easier calculation (no counter overflow).
SIGNAL xhdl_150 : std_logic_vector(8 DOWNTO 0);
-- SIGNAL wb_dat_o_xhdl1 : std_logic_vector(7 DOWNTO 0);
-- SIGNAL wb_ack_o_xhdl2 : std_logic;
SIGNAL tx_o_xhdl3 : std_logic;
SIGNAL bus_off_on_xhdl4 : std_logic;
SIGNAL irq_on_xhdl5 : std_logic;
SIGNAL clkout_o_xhdl6 : std_logic;
SIGNAL data_64x8_xhdl7 : std_logic_vector(7 DOWNTO 0);
SIGNAL wren_64x8_xhdl8 : std_logic;
SIGNAL rden_64x8_xhdl9 : std_logic;
SIGNAL wraddress_64x8_xhdl10 : std_logic_vector(5 DOWNTO 0);
SIGNAL rdaddress_64x8_xhdl11 : std_logic_vector(5 DOWNTO 0);
SIGNAL data_64x4_xhdl12 : std_logic_vector(3 DOWNTO 0);
SIGNAL wren_64x4x1_xhdl13 : std_logic;
SIGNAL wraddress_64x4x1_xhdl14 : std_logic_vector(5 DOWNTO 0);
SIGNAL rdaddress_64x4x1_xhdl15 : std_logic_vector(5 DOWNTO 0);
SIGNAL data_64x1_xhdl16 : std_logic;
SIGNAL rx_inter : std_logic;
BEGIN
-- wb_dat_o <= wb_dat_o_xhdl1;
-- wb_ack_o <= wb_ack_o_xhdl2;
tx_o <= tx_o_xhdl3;
bus_off_on <= bus_off_on_xhdl4;
irq_on <= irq_on_xhdl5;
clkout_o <= clkout_o_xhdl6;
data_64x8 <= data_64x8_xhdl7;
wren_64x8 <= wren_64x8_xhdl8;
rden_64x8 <= rden_64x8_xhdl9;
wraddress_64x8 <= wraddress_64x8_xhdl10;
rdaddress_64x8 <= rdaddress_64x8_xhdl11;
data_64x4 <= data_64x4_xhdl12;
wren_64x4x1 <= wren_64x4x1_xhdl13;
wraddress_64x4x1 <= wraddress_64x4x1_xhdl14;
rdaddress_64x4x1 <= rdaddress_64x4x1_xhdl15;
data_64x1 <= data_64x1_xhdl16;
-- port connections for Ram
--64x8
w_q_dp_64x8 <= q_dp_64x8 ;
data_64x8_xhdl7 <= w_data_64x8 ;
wren_64x8_xhdl8 <= w_wren_64x8 ;
rden_64x8_xhdl9 <= w_rden_64x8 ;
wraddress_64x8_xhdl10 <= w_wraddress_64x8 ;
rdaddress_64x8_xhdl11 <= w_rdaddress_64x8 ;
--64x4
w_q_dp_64x4 <= q_dp_64x4 ;
data_64x4_xhdl12 <= w_data_64x4 ;
wren_64x4x1_xhdl13 <= w_wren_64x4x1 ;
wraddress_64x4x1_xhdl14 <= w_wraddress_64x4x1 ;
rdaddress_64x4x1_xhdl15 <= w_rdaddress_64x4x1 ;
--64x1
w_q_dp_64x1 <= q_dp_64x1 ;
data_64x1_xhdl16 <= w_data_64x1 ;
-- Connecting can_registers module -- Mode register -- Command register -- Arbitration Lost Capture Register -- Error Code Capture Register -- Bus Timing 0 register -- Bus Timing 1 register -- Error Warning Limit register -- Rx Error Counter register -- Tx Error Counter register -- Clock Divider register -- This section is for BASIC and EXTENDED mode -- Acceptance code register -- Acceptance mask register -- End: This section is for BASIC and EXTENDED mode -- This section is for EXTENDED mode -- Acceptance code register -- Acceptance mask register -- End: This section is for EXTENDED mode -- Tx data registers. Holding identifier (basic mode), tx frame information (extended mode) and data -- End: Tx data registers
i_can_registers : can_registers
PORT MAP (
clk => clk_i,
rst => rst,
cs => cs,
we => we,
addr => addr,
data_in => data_in,
data_out => data_out_regs,
irq_n => irq_on_xhdl5,
sample_point => sample_point,
transmitting => transmitting,
set_reset_mode => set_reset_mode,
node_bus_off => node_bus_off,
error_status => error_status,
rx_err_cnt => rx_err_cnt,
tx_err_cnt => tx_err_cnt,
transmit_status => transmit_status,
receive_status => receive_status,
tx_successful => tx_successful,
need_to_tx => need_to_tx,
overrun => overrun,
info_empty => info_empty,
set_bus_error_irq => set_bus_error_irq,
set_arbitration_lost_irq => set_arbitration_lost_irq,
arbitration_lost_capture => arbitration_lost_capture,
node_error_passive => node_error_passive,
node_error_active => node_error_active,
rx_message_counter => rx_message_counter,
reset_mode => reset_mode,
listen_only_mode => listen_only_mode,
acceptance_filter_mode => acceptance_filter_mode,
self_test_mode => self_test_mode,
clear_data_overrun => open,
release_buffer => release_buffer,
abort_tx => abort_tx,
tx_request => tx_request,
self_rx_request => self_rx_request,
single_shot_transmission => single_shot_transmission,
tx_state => tx_state,
tx_state_q => tx_state_q,
overload_request => overload_request,
overload_frame => overload_frame,
read_arbitration_lost_capture_reg => read_arbitration_lost_capture_reg,
read_error_code_capture_reg => read_error_code_capture_reg,
error_capture_code => error_capture_code,
baud_r_presc => baud_r_presc,
sync_jump_width => sync_jump_width,
time_segment1 => time_segment1,
time_segment2 => time_segment2,
triple_sampling => triple_sampling,
error_warning_limit => error_warning_limit,
we_rx_err_cnt => we_rx_err_cnt,
we_tx_err_cnt => we_tx_err_cnt,
extended_mode => extended_mode,
clkout => clkout_o_xhdl6,
acceptance_code_0 => acceptance_code_0,
acceptance_mask_0 => acceptance_mask_0,
acceptance_code_1 => acceptance_code_1,
acceptance_code_2 => acceptance_code_2,
acceptance_code_3 => acceptance_code_3,
acceptance_mask_1 => acceptance_mask_1,
acceptance_mask_2 => acceptance_mask_2,
acceptance_mask_3 => acceptance_mask_3,
tx_data_0 => tx_data_0,
tx_data_1 => tx_data_1,
tx_data_2 => tx_data_2,
tx_data_3 => tx_data_3,
tx_data_4 => tx_data_4,
tx_data_5 => tx_data_5,
tx_data_6 => tx_data_6,
tx_data_7 => tx_data_7,
tx_data_8 => tx_data_8,
tx_data_9 => tx_data_9,
tx_data_10 => tx_data_10,
tx_data_11 => tx_data_11,
tx_data_12 => tx_data_12);
-- Connecting can_btl module -- Bus Timing 0 register -- Bus Timing 1 register -- Output signals from this module -- output from can_bsp module
i_can_btl : can_btl
PORT MAP (
clk => clk_i,
rst => rst,
rx => rx_sync,
tx => tx_o_xhdl3,
baud_r_presc => baud_r_presc,
sync_jump_width => sync_jump_width,
time_segment1 => time_segment1,
time_segment2 => time_segment2,
triple_sampling => triple_sampling,
sample_point => sample_point,
sampled_bit => sampled_bit,
sampled_bit_q => sampled_bit_q,
tx_point => tx_point,
hard_sync => hard_sync,
rx_idle => rx_idle,
rx_inter => rx_inter,
transmitting => transmitting,
transmitter => transmitter,
go_rx_inter => go_rx_inter,
tx_next => tx_next,
go_overload_frame => go_overload_frame,
go_error_frame => go_error_frame,
go_tx => go_tx,
send_ack => send_ack,
node_error_passive => node_error_passive);
-- xhdl_148 <= rx_err_cnt_dummy & rx_err_cnt(7 DOWNTO 0);
rx_err_cnt_dummy <= xhdl_148(8);
rx_err_cnt(7 DOWNTO 0) <= xhdl_148(7 DOWNTO 0);
-- xhdl_150 <= tx_err_cnt_dummy & tx_err_cnt(7 DOWNTO 0);
tx_err_cnt_dummy <= xhdl_150(8);
tx_err_cnt(7 DOWNTO 0) <= xhdl_150(7 DOWNTO 0);
-- The MSB is not displayed. It is just used for easier calculation (no counter overflow).
-- This section is for BASIC and EXTENDED mode -- Acceptance code register -- Acceptance mask register -- End: This section is for BASIC and EXTENDED mode -- This section is for EXTENDED mode -- Acceptance code register -- Acceptance mask register -- End: This section is for EXTENDED mode -- Tx data registers. Holding identifier (basic mode), tx frame information (extended mode) and data -- End: Tx data registers -- Tx signal -- port connections for Ram
--64x8
--64x4
--64x1
i_can_bsp : can_bsp
PORT MAP (
clk => clk_i,
rst => rst,
sample_point => sample_point,
sampled_bit => sampled_bit,
sampled_bit_q => sampled_bit_q,
tx_point => tx_point,
hard_sync => hard_sync,
addr => addr,
data_in => data_in,
data_out => data_out_fifo,
fifo_selected => data_out_fifo_selected,
reset_mode => reset_mode,
listen_only_mode => listen_only_mode,
acceptance_filter_mode => acceptance_filter_mode,
self_test_mode => self_test_mode,
release_buffer => release_buffer,
tx_request => tx_request,
abort_tx => abort_tx,
self_rx_request => self_rx_request,
single_shot_transmission => single_shot_transmission,
tx_state => tx_state,
tx_state_q => tx_state_q,
overload_request => overload_request,
overload_frame => overload_frame,
read_arbitration_lost_capture_reg => read_arbitration_lost_capture_reg,
read_error_code_capture_reg => read_error_code_capture_reg,
error_capture_code => error_capture_code,
error_warning_limit => error_warning_limit,
we_rx_err_cnt => we_rx_err_cnt,
we_tx_err_cnt => we_tx_err_cnt,
extended_mode => extended_mode,
rx_idle => rx_idle,
transmitting => transmitting,
transmitter => transmitter,
go_rx_inter => go_rx_inter,
not_first_bit_of_inter => not_first_bit_of_inter,
rx_inter => rx_inter,
set_reset_mode => set_reset_mode,
node_bus_off => node_bus_off,
error_status => error_status,
rx_err_cnt => xhdl_148,
tx_err_cnt => xhdl_150,
transmit_status => transmit_status,
receive_status => receive_status,
tx_successful => tx_successful,
need_to_tx => need_to_tx,
overrun => overrun,
info_empty => info_empty,
set_bus_error_irq => set_bus_error_irq,
set_arbitration_lost_irq => set_arbitration_lost_irq,
arbitration_lost_capture => arbitration_lost_capture,
node_error_passive => node_error_passive,
node_error_active => node_error_active,
rx_message_counter => rx_message_counter,
acceptance_code_0 => acceptance_code_0,
acceptance_mask_0 => acceptance_mask_0,
acceptance_code_1 => acceptance_code_1,
acceptance_code_2 => acceptance_code_2,
acceptance_code_3 => acceptance_code_3,
acceptance_mask_1 => acceptance_mask_1,
acceptance_mask_2 => acceptance_mask_2,
acceptance_mask_3 => acceptance_mask_3,
tx_data_0 => tx_data_0,
tx_data_1 => tx_data_1,
tx_data_2 => tx_data_2,
tx_data_3 => tx_data_3,
tx_data_4 => tx_data_4,
tx_data_5 => tx_data_5,
tx_data_6 => tx_data_6,
tx_data_7 => tx_data_7,
tx_data_8 => tx_data_8,
tx_data_9 => tx_data_9,
tx_data_10 => tx_data_10,
tx_data_11 => tx_data_11,
tx_data_12 => tx_data_12,
tx => tx_o_xhdl3,
tx_next => tx_next,
bus_off_on => bus_off_on_xhdl4,
go_overload_frame => go_overload_frame,
go_error_frame => go_error_frame,
go_tx => go_tx,
send_ack => send_ack,
q_dp_64x8 => w_q_dp_64x8,
data_64x8 => w_data_64x8,
wren_64x8 => w_wren_64x8,
rden_64x8 => w_rden_64x8,
wraddress_64x8 => w_wraddress_64x8,
rdaddress_64x8 => w_rdaddress_64x8,
q_dp_64x4 => w_q_dp_64x4,
data_64x4 => w_data_64x4,
wren_64x4x1 => w_wren_64x4x1,
wraddress_64x4x1 => w_wraddress_64x4x1,
rdaddress_64x4x1 => w_rdaddress_64x4x1,
q_dp_64x1 => w_q_dp_64x1,
data_64x1 => w_data_64x1);
-- Multiplexing wb_dat_o from registers and rx fifo
PROCESS (extended_mode, addr, reset_mode)
VARIABLE data_out_fifo_selected_xhdl203 : std_logic;
BEGIN
IF ((((extended_mode AND (NOT reset_mode)) AND CONV_STD_LOGIC((addr >= "00010000") AND (addr<="00011100"))) OR ((NOT extended_mode) AND CONV_STD_LOGIC((addr >= "00010100") AND (addr<="00011101")))) = '1') THEN
data_out_fifo_selected_xhdl203 := '1';
ELSE
data_out_fifo_selected_xhdl203 := '0';
END IF;
data_out_fifo_selected <= data_out_fifo_selected_xhdl203;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((cs AND (NOT we)) = '1') THEN
IF (data_out_fifo_selected = '1') THEN
data_out <= data_out_fifo ;
ELSE
data_out <= data_out_regs ;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk_i, rst)
BEGIN
IF (rst = '1') THEN
rx_sync_tmp <= '1';
rx_sync <= '1';
ELSIF (clk_i'EVENT AND clk_i = '1') THEN
rx_sync_tmp <= rx_i ;
rx_sync <= rx_sync_tmp ;
END IF;
END PROCESS;
-- cs_can_i <= '1' ;
-- Combining wb_cyc_i and wb_stb_i signals to cs signal. Than synchronizing to clk_i clock domain.
-- PROCESS (clk_i, rst)
-- BEGIN
-- IF (rst = '1') THEN
-- cs_sync1 <= '0';
-- cs_sync2 <= '0';
-- cs_sync3 <= '0';
-- cs_sync_rst1 <= '0';
-- cs_sync_rst2 <= '0';
-- ELSIF (clk_i'EVENT AND clk_i = '1') THEN
-- cs_sync1 <= ((wb_cyc_i AND wb_stb_i) AND (NOT cs_sync_rst2)) AND cs_can_i ;
-- cs_sync2 <= cs_sync1 AND (NOT cs_sync_rst2) ;
-- cs_sync3 <= cs_sync2 AND (NOT cs_sync_rst2) ;
-- cs_sync_rst1 <= cs_ack3 ;
-- cs_sync_rst2 <= cs_sync_rst1 ;
-- END IF;
-- END PROCESS;
-- cs <= cs_sync2 AND (NOT cs_sync3) ;
--
-- PROCESS (wb_clk_i)
-- BEGIN
-- IF (wb_clk_i'EVENT AND wb_clk_i = '1') THEN
-- cs_ack1 <= cs_sync3 ;
-- cs_ack2 <= cs_ack1 ;
-- cs_ack3 <= cs_ack2 ;
-- END IF;
-- END PROCESS;
-- Generating acknowledge signal
-- PROCESS (wb_clk_i)
-- BEGIN
-- IF (wb_clk_i'EVENT AND wb_clk_i = '1') THEN
-- wb_ack_o_xhdl2 <= cs_ack2 AND (NOT cs_ack3) ;
-- END IF;
-- END PROCESS;
-- rst <= wb_rst_i ;
-- we <= wb_we_i ;
-- addr <= wb_adr_i ;
-- data_in <= wb_dat_i ;
-- wb_dat_o_xhdl1 <= data_out ;
END ARCHITECTURE RTL;
|
-- -------------------------------------------------------------
--
-- Generated Configuration for inst_ed_e
--
-- Generated
-- by: wig
-- on: Mon Apr 10 13:27:22 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -nodelta ../../bitsplice.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_ed_e-rtl-conf-c.vhd,v 1.1 2006/04/10 15:42:05 wig Exp $
-- $Date: 2006/04/10 15:42:05 $
-- $Log: inst_ed_e-rtl-conf-c.vhd,v $
-- Revision 1.1 2006/04/10 15:42:05 wig
-- Updated testcase (__TOP__)
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.79 2006/03/17 09:18:31 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.44 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/conf
--
-- Start of Generated Configuration inst_ed_e_rtl_conf / inst_ed_e
--
configuration inst_ed_e_rtl_conf of inst_ed_e is
for rtl
-- Generated Configuration
-- __I_NO_CONFIG_VERILOG --for inst_eda : inst_eda_e
-- __I_NO_CONFIG_VERILOG -- use configuration work.inst_eda_e_rtl_conf;
-- __I_NO_CONFIG_VERILOG --end for;
-- __I_NO_CONFIG_VERILOG --for inst_edb : inst_edb_e
-- __I_NO_CONFIG_VERILOG -- use configuration work.inst_edb_e_rtl_conf;
-- __I_NO_CONFIG_VERILOG --end for;
end for;
end inst_ed_e_rtl_conf;
--
-- End of Generated Configuration inst_ed_e_rtl_conf
--
--
--!End of Configuration/ies
-- --------------------------------------------------------------
|
entity attr5 is
end entity;
architecture test of attr5 is
type int_vec is array (integer range <>) of integer;
type int_vec_ptr is access int_vec;
begin
process is
variable p : int_vec_ptr;
begin
p := new int_vec(1 to 10);
report integer'image(p.all'length);
assert p.all'length = 10;
deallocate(p);
p := new int_vec(1 to 20);
report integer'image(p'length);
assert p'length = 20;
wait;
end process;
end architecture;
|
entity attr5 is
end entity;
architecture test of attr5 is
type int_vec is array (integer range <>) of integer;
type int_vec_ptr is access int_vec;
begin
process is
variable p : int_vec_ptr;
begin
p := new int_vec(1 to 10);
report integer'image(p.all'length);
assert p.all'length = 10;
deallocate(p);
p := new int_vec(1 to 20);
report integer'image(p'length);
assert p'length = 20;
wait;
end process;
end architecture;
|
entity attr5 is
end entity;
architecture test of attr5 is
type int_vec is array (integer range <>) of integer;
type int_vec_ptr is access int_vec;
begin
process is
variable p : int_vec_ptr;
begin
p := new int_vec(1 to 10);
report integer'image(p.all'length);
assert p.all'length = 10;
deallocate(p);
p := new int_vec(1 to 20);
report integer'image(p'length);
assert p'length = 20;
wait;
end process;
end architecture;
|
entity attr5 is
end entity;
architecture test of attr5 is
type int_vec is array (integer range <>) of integer;
type int_vec_ptr is access int_vec;
begin
process is
variable p : int_vec_ptr;
begin
p := new int_vec(1 to 10);
report integer'image(p.all'length);
assert p.all'length = 10;
deallocate(p);
p := new int_vec(1 to 20);
report integer'image(p'length);
assert p'length = 20;
wait;
end process;
end architecture;
|
entity attr5 is
end entity;
architecture test of attr5 is
type int_vec is array (integer range <>) of integer;
type int_vec_ptr is access int_vec;
begin
process is
variable p : int_vec_ptr;
begin
p := new int_vec(1 to 10);
report integer'image(p.all'length);
assert p.all'length = 10;
deallocate(p);
p := new int_vec(1 to 20);
report integer'image(p'length);
assert p'length = 20;
wait;
end process;
end architecture;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Stimulus Generator For Single Port ROM
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: bmg_stim_gen.vhd
--
-- Description:
-- Stimulus Generation For SROM
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY REGISTER_LOGIC_SROM IS
PORT(
Q : OUT STD_LOGIC;
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
D : IN STD_LOGIC
);
END REGISTER_LOGIC_SROM;
ARCHITECTURE REGISTER_ARCH OF REGISTER_LOGIC_SROM IS
SIGNAL Q_O : STD_LOGIC :='0';
BEGIN
Q <= Q_O;
FF_BEH: PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST /= '0' ) THEN
Q_O <= '0';
ELSE
Q_O <= D;
END IF;
END IF;
END PROCESS;
END REGISTER_ARCH;
LIBRARY STD;
USE STD.TEXTIO.ALL;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
--USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY BMG_STIM_GEN IS
GENERIC ( C_ROM_SYNTH : INTEGER := 0
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
ADDRA: OUT STD_LOGIC_VECTOR(16 DOWNTO 0) := (OTHERS => '0');
DATA_IN : IN STD_LOGIC_VECTOR (11 DOWNTO 0); --OUTPUT VECTOR
STATUS : OUT STD_LOGIC:= '0'
);
END BMG_STIM_GEN;
ARCHITECTURE BEHAVIORAL OF BMG_STIM_GEN IS
FUNCTION hex_to_std_logic_vector(
hex_str : STRING;
return_width : INTEGER)
RETURN STD_LOGIC_VECTOR IS
VARIABLE tmp : STD_LOGIC_VECTOR((hex_str'LENGTH*4)+return_width-1
DOWNTO 0);
BEGIN
tmp := (OTHERS => '0');
FOR i IN 1 TO hex_str'LENGTH LOOP
CASE hex_str((hex_str'LENGTH+1)-i) IS
WHEN '0' => tmp(i*4-1 DOWNTO (i-1)*4) := "0000";
WHEN '1' => tmp(i*4-1 DOWNTO (i-1)*4) := "0001";
WHEN '2' => tmp(i*4-1 DOWNTO (i-1)*4) := "0010";
WHEN '3' => tmp(i*4-1 DOWNTO (i-1)*4) := "0011";
WHEN '4' => tmp(i*4-1 DOWNTO (i-1)*4) := "0100";
WHEN '5' => tmp(i*4-1 DOWNTO (i-1)*4) := "0101";
WHEN '6' => tmp(i*4-1 DOWNTO (i-1)*4) := "0110";
WHEN '7' => tmp(i*4-1 DOWNTO (i-1)*4) := "0111";
WHEN '8' => tmp(i*4-1 DOWNTO (i-1)*4) := "1000";
WHEN '9' => tmp(i*4-1 DOWNTO (i-1)*4) := "1001";
WHEN 'a' | 'A' => tmp(i*4-1 DOWNTO (i-1)*4) := "1010";
WHEN 'b' | 'B' => tmp(i*4-1 DOWNTO (i-1)*4) := "1011";
WHEN 'c' | 'C' => tmp(i*4-1 DOWNTO (i-1)*4) := "1100";
WHEN 'd' | 'D' => tmp(i*4-1 DOWNTO (i-1)*4) := "1101";
WHEN 'e' | 'E' => tmp(i*4-1 DOWNTO (i-1)*4) := "1110";
WHEN 'f' | 'F' => tmp(i*4-1 DOWNTO (i-1)*4) := "1111";
WHEN OTHERS => tmp(i*4-1 DOWNTO (i-1)*4) := "1111";
END CASE;
END LOOP;
RETURN tmp(return_width-1 DOWNTO 0);
END hex_to_std_logic_vector;
CONSTANT ZERO : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR_INT : STD_LOGIC_VECTOR(16 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL CHECK_READ_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL EXPECTED_DATA : STD_LOGIC_VECTOR(11 DOWNTO 0) := (OTHERS => '0');
SIGNAL DO_READ : STD_LOGIC := '0';
SIGNAL CHECK_DATA : STD_LOGIC := '0';
SIGNAL CHECK_DATA_R : STD_LOGIC := '0';
SIGNAL CHECK_DATA_2R : STD_LOGIC := '0';
SIGNAL DO_READ_REG: STD_LOGIC_VECTOR(4 DOWNTO 0) :=(OTHERS => '0');
CONSTANT DEFAULT_DATA : STD_LOGIC_VECTOR(11 DOWNTO 0):= hex_to_std_logic_vector("0",12);
BEGIN
SYNTH_COE: IF(C_ROM_SYNTH =0 ) GENERATE
type mem_type is array (99199 downto 0) of std_logic_vector(11 downto 0);
FUNCTION bit_to_sl(input: BIT) RETURN STD_LOGIC IS
VARIABLE temp_return : STD_LOGIC;
BEGIN
IF (input = '0') THEN
temp_return := '0';
ELSE
temp_return := '1';
END IF;
RETURN temp_return;
END bit_to_sl;
function char_to_std_logic (
char : in character)
return std_logic is
variable data : std_logic;
begin
if char = '0' then
data := '0';
elsif char = '1' then
data := '1';
elsif char = 'X' then
data := 'X';
else
assert false
report "character which is not '0', '1' or 'X'."
severity warning;
data := 'U';
end if;
return data;
end char_to_std_logic;
impure FUNCTION init_memory( C_USE_DEFAULT_DATA : INTEGER;
C_LOAD_INIT_FILE : INTEGER ;
C_INIT_FILE_NAME : STRING ;
DEFAULT_DATA : STD_LOGIC_VECTOR(11 DOWNTO 0);
width : INTEGER;
depth : INTEGER)
RETURN mem_type IS
VARIABLE init_return : mem_type := (OTHERS => (OTHERS => '0'));
FILE init_file : TEXT;
VARIABLE mem_vector : BIT_VECTOR(width-1 DOWNTO 0);
VARIABLE bitline : LINE;
variable bitsgood : boolean := true;
variable bitchar : character;
VARIABLE i : INTEGER;
VARIABLE j : INTEGER;
BEGIN
--Display output message indicating that the behavioral model is being
--initialized
ASSERT (NOT (C_USE_DEFAULT_DATA=1 OR C_LOAD_INIT_FILE=1)) REPORT " Block Memory Generator CORE Generator module loading initial data..." SEVERITY NOTE;
-- Setup the default data
-- Default data is with respect to write_port_A and may be wider
-- or narrower than init_return width. The following loops map
-- default data into the memory
IF (C_USE_DEFAULT_DATA=1) THEN
FOR i IN 0 TO depth-1 LOOP
init_return(i) := DEFAULT_DATA;
END LOOP;
END IF;
-- Read in the .mif file
-- The init data is formatted with respect to write port A dimensions.
-- The init_return vector is formatted with respect to minimum width and
-- maximum depth; the following loops map the .mif file into the memory
IF (C_LOAD_INIT_FILE=1) THEN
file_open(init_file, C_INIT_FILE_NAME, read_mode);
i := 0;
WHILE (i < depth AND NOT endfile(init_file)) LOOP
mem_vector := (OTHERS => '0');
readline(init_file, bitline);
-- read(file_buffer, mem_vector(file_buffer'LENGTH-1 DOWNTO 0));
FOR j IN 0 TO width-1 LOOP
read(bitline,bitchar,bitsgood);
init_return(i)(width-1-j) := char_to_std_logic(bitchar);
END LOOP;
i := i + 1;
END LOOP;
file_close(init_file);
END IF;
RETURN init_return;
END FUNCTION;
--***************************************************************
-- convert bit to STD_LOGIC
--***************************************************************
constant c_init : mem_type := init_memory(0,
1,
"road.mif",
DEFAULT_DATA,
12,
99200);
constant rom : mem_type := c_init;
BEGIN
EXPECTED_DATA <= rom(conv_integer(unsigned(check_read_addr)));
CHECKER_RD_ADDR_GEN_INST:ENTITY work.ADDR_GEN
GENERIC MAP( C_MAX_DEPTH =>99200 )
PORT MAP(
CLK => CLK,
RST => RST,
EN => CHECK_DATA_2R,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => CHECK_READ_ADDR
);
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(CHECK_DATA_2R ='1') THEN
IF(EXPECTED_DATA = DATA_IN) THEN
STATUS<='0';
ELSE
STATUS <= '1';
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE;
-- Simulatable ROM
--Synthesizable ROM
SYNTH_CHECKER: IF(C_ROM_SYNTH = 1) GENERATE
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(CHECK_DATA_2R='1') THEN
IF(DATA_IN=DEFAULT_DATA) THEN
STATUS <= '0';
ELSE
STATUS <= '1';
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE;
READ_ADDR_INT(16 DOWNTO 0) <= READ_ADDR(16 DOWNTO 0);
ADDRA <= READ_ADDR_INT ;
CHECK_DATA <= DO_READ;
RD_ADDR_GEN_INST:ENTITY work.ADDR_GEN
GENERIC MAP( C_MAX_DEPTH => 99200 )
PORT MAP(
CLK => CLK,
RST => RST,
EN => DO_READ,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => READ_ADDR
);
RD_PROCESS: PROCESS (CLK)
BEGIN
IF (RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
DO_READ <= '0';
ELSE
DO_READ <= '1';
END IF;
END IF;
END PROCESS;
BEGIN_SHIFT_REG: FOR I IN 0 TO 4 GENERATE
BEGIN
DFF_RIGHT: IF I=0 GENERATE
BEGIN
SHIFT_INST_0: ENTITY work.REGISTER_LOGIC_SROM
PORT MAP(
Q => DO_READ_REG(0),
CLK =>CLK,
RST=>RST,
D =>DO_READ
);
END GENERATE DFF_RIGHT;
DFF_OTHERS: IF ((I>0) AND (I<=4)) GENERATE
BEGIN
SHIFT_INST: ENTITY work.REGISTER_LOGIC_SROM
PORT MAP(
Q => DO_READ_REG(I),
CLK =>CLK,
RST=>RST,
D =>DO_READ_REG(I-1)
);
END GENERATE DFF_OTHERS;
END GENERATE BEGIN_SHIFT_REG;
CHECK_DATA_REG_1: ENTITY work.REGISTER_LOGIC_SROM
PORT MAP(
Q => CHECK_DATA_2R,
CLK =>CLK,
RST=>RST,
D =>CHECK_DATA_R
);
CHECK_DATA_REG: ENTITY work.REGISTER_LOGIC_SROM
PORT MAP(
Q => CHECK_DATA_R,
CLK =>CLK,
RST=>RST,
D =>CHECK_DATA
);
END ARCHITECTURE;
|
--This is an autogenerated file
--Do not modify it by hand
--Generated at 2017-12-14T16:53:23+13:00
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.enforcement_types_WaterBoilerEnforcer.all;
entity enforcement_top_WaterBoilerEnforcer is
port
(
clk : in std_logic;
reset : in std_logic;
Pboiler_i : in unsigned(7 downto 0);
Pboiler_o : out unsigned(7 downto 0);
Fin_i : in unsigned(7 downto 0);
Fin_o : out unsigned(7 downto 0);
Fout_i : in unsigned(7 downto 0);
Fout_o : out unsigned(7 downto 0);
Fop_i : in unsigned(7 downto 0);
Fop_o : out unsigned(7 downto 0);
Lboiler_i : in unsigned(7 downto 0);
Lboiler_o : out unsigned(7 downto 0);
Hboiler_i : in std_logic;
Hboiler_o : out std_logic;
Cin_i : in std_logic;
Cin_o : out std_logic;
Vin_i : in unsigned(7 downto 0);
Vin_o : out unsigned(7 downto 0);
Vop_i : in unsigned(7 downto 0);
Vop_o : out unsigned(7 downto 0);
Vout_i : in unsigned(7 downto 0);
Vout_o : out unsigned(7 downto 0);
Aop_i : in std_logic;
Aop_o : out std_logic;
e : out std_logic_vector(1 downto 0)
);
end entity;
architecture behaviour of enforcement_top_WaterBoilerEnforcer is
signal ns_time : unsigned(63 downto 0);
signal enfI, enf0_1, enfO : enforced_signals_WaterBoilerEnforcer;
begin
--this is our global nanosecond timer which counts time since inception
--64 refers to the number of bits in the counter
--20 refers to the number the counter will be incremented each tick (for a 50MHz clock, we will have 20ns per tick)
--a 64-bit nanosecond timer will be able to count for 584.554531 years before overflowing
count: entity work.binary_counter generic map(
N => 64,
I => 20
) port map (
clk => clk,
reset => '0',
enable => '1',
q => ns_time
);
--connect the IO
enfI.Pboiler <= Pboiler_i;
Pboiler_o <= enfO.Pboiler;
enfI.Fin <= Fin_i;
Fin_o <= enfO.Fin;
enfI.Fout <= Fout_i;
Fout_o <= enfO.Fout;
enfI.Fop <= Fop_i;
Fop_o <= enfO.Fop;
enfI.Lboiler <= Lboiler_i;
Lboiler_o <= enfO.Lboiler;
enfI.Hboiler <= Hboiler_i;
Hboiler_o <= enfO.Hboiler;
enfI.Cin <= Cin_i;
Cin_o <= enfO.Cin;
enfI.Vin <= Vin_i;
Vin_o <= enfO.Vin;
enfI.Vop <= Vop_i;
Vop_o <= enfO.Vop;
enfI.Vout <= Vout_i;
Vout_o <= enfO.Vout;
enfI.Aop <= Aop_i;
Aop_o <= enfO.Aop;
--policies
enf0 : entity work.enforcer_WaterBoilerEnforcer_P1 port map (
clk => clk,
reset => reset,
t => ns_time,
e => e(0),
q => enfI,
q_prime => enf0_1
);
enf1 : entity work.enforcer_WaterBoilerEnforcer_P2 port map (
clk => clk,
reset => reset,
t => ns_time,
e => e(1),
q => enf0_1,
q_prime => enfO
);
end architecture;
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
CqRISoHPXZYJj3QR4E/CjftWkY/P1IhtgyNWvgVekMt/RKOkzujhaciVHATStTHy3h+1Zm/164++
4mcuvYhNOg==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
Qo8OgKp6wQUoudW5GoXZ/HeiCizNY96lqLhLwYY3BsmjnO9G5QlzIafDF46pZqy4gGxE7EWYsX5M
4/IXm3MOkDEaexJM8tIR5Ar1wwViMFTJQSSdHnEGjAsT0pQTTAaUWUWYy4aT7UeyHt8EScEHuQSj
G8wICKdb+5yMoaJpnB0=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
YQ9nhMBLYXor+kxP9zRGJrdDzZBZ2tWF2wV0oEH/P2yrxfmuEC9HXyrVyXOOYlm3rX80f+u2t6EE
V2rKYV+hISugWXLZce4u/ogzq55CmoigNeWyvLvKMKqEn+caLpw4nTNciMcRPM5Gauo5B4LwvxlY
L4ud6StR3nnEOSBiuhCUfOHbKDXzOFG36fgA2xOLYeI1dIoxVyY2Hjsr+8fJBM/ryOJ1yA6EPNvZ
JLZ9pkTwp+FoJ18cWalT1+RtOkJWm7OwCFdfAypjbT4ISpohMl672e1mQV8VcTFHN2BBMCLgNKCN
eOKikRzucLaWGg3agVyJ0GZNi3JTtmDRPpC5qg==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
zHj1+y/Mcs6E7y+zVOTKNFim0j0kVGEvdHiqWgD7VpbUIy+UFNwQkOF1o7+hB6DRi+6nSE2QNc6L
S6eXHV11xUedX1NK/drQ/lfB7BwhB0RVKzRyGdime0WGILq1gzK9uZDquB0TuggWrb3zfS7JCXOI
OTxYb0jo+V5SOyXatRs=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
e+wRO+tCnUT8/kAsXUc5J4k2t//lFDte6/0B4JSn9qQvHbRV+RIEOwNQALHq6XEACA+w979KEMhr
mqHXsNaC/LYDqA1woQ/yfqZYDN4+ykKf+WwXNEat5d8xUDIVVj1w3ynruhcUJxP3RX2C0FALIZWT
Ve2E/Yq1GJCCa2WB9R0z2sJSjuIR3LHgdTn6v3ZDOrRsUzzMUIbcndZawV2st+lTQRwE27wpqVI8
zCJE3PqX607fkk1YIzwwkGG+EaWgl6Q3ftA/yV53UYXEnS1/t8sXXLqQau6eNJtiuwmQz+PU0aIc
v0IWhmSvj0/kR2+z6Q9IGA5azfAXegWNMra4jQ==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 22240)
`protect data_block
6Oq2NHS0qZqPKk+yyC7INg4ikrI/gd2O8Oq6I4l2evyG4WDw/pIRXVM5oJLszhSU/yJvvcDvxTWV
7GMfzTtTbLGRF0sh+4pA62N/0if6jVpgnxE1v+bU/lpvHpD7Wp3F1UDkd4yh7TadDUzxG+B7oJiF
b+vw4jR/c8m5Je69xSbHVGAET2bvTDwXzVbRqAVrxFJTnFrrubR8DtVLM5n7+I/fErax+WcEJv9C
JvmNdqfO4DTGkSmtLDMnshsgA0y/wXrE2R24e5XqgFVd3VCnTkuNP0etnpjCZRSxodV6Cw3cnikk
/5i5+o6jBS3mnGzb3IWdpTWeZSuboaywggzKcVayTuiBebe2kAzptJtAhJ4ViD9sxl4rUckNZb1P
O8cw5w8L8ppPQRLgsvixLHrcnUSwdCurr3d0LjAfamruw0eBGVXm+nyxCmdXtWS9t+j8zDkpB/1w
PPwj1et561xHjA/UKca1jp/ZFl9skZpIITlXzo6gIoPzQERu/iQ9T6LMqhJ/dLbormlkgFENdZ4Z
VizKCa8P0i5qgDWsy/Fg04iKeV3SiUYHZTPNSkvSXPm5rIy6Kzx3NDF8P27Zx7rDVGxDheF7X6b/
J18qm+rHTI4/d86ULfL9wmBElBZl4BBZiNujCArZQ/tPKFaZvVhnLXygd5wHo5Ehqk6ocJSXu86P
aQpyVCWsFsypelWE5n9oRDZrtqGZQIpqNPKLk5jtr6aEASwM3n0Zjgk2xBwPTqncuhFbevWLtQXj
w+ov+/jXaF2ZZIFzJr4EtZAF7n2mYHHeWKYTxmiEu12v99JFOjK7eNjlZm673RmR19QCXxX+K+kV
GbbSFocAQ/FEFEc1TLSVVUzc2uVPaZwKLRvfSrZ4J8RAVcZJXYJ1JcI34xwRME4fdPzc74Ranv2Z
meJdOLfa4hpEyh5m1UX+Y49nVIZ90n82wq5Nl3n4vCKGchhupGqOycpyjmuPwnq8Vi8Kim3/C4Gb
ZhzLdZz1Qbn+kdTP6guPdnN15dnrUhoy7/5G4Ks6aT2EneB8u9oX0jwjrF/VEZIg53ha/9878Cgd
zoC2TDV/w3OEXHysF42hvyC3+jyV5MUHPh57HA1scdvPnH1jTuVzC0CzZ3iU5kHTUGMxSyVTXbpM
2iTbjuKrCQ9BjgtGeY2Lu+oQdKugSHan9aWgXDe0frqWZeW1ejpkgRWp7ATrSwt+jjPBV6tjIYEU
TSJDSsxGKcVqEKX+qtZA0VLmO+dot1vi3ODCpnKBLcEoIPnwbwUYfwDAW/aQlUzuLTN/UfK4bS5G
0VMaHSj8cGfelWlxbB4C5FNfMnNFVyztSxzkUnIK9M7HboKWrYUXGKmj/rnxFs+EQPh1mFpDpsCk
GxbfWPso5MdeiEJPVCyG6O7mcc8MexdvQ0lSvKIZpivJUzKdfisxUiFH/hnAKeLBiW59cvF8x92I
1UclpfZx04JNWI71yHxDXOSCPBo/asiU6BRjlvwyT4C+laF5za/GbSCwYKnOnoFmSSVVcG7+UCcp
I5J851717fhVXbiYDokQztEzGr9LOP4wy6/E0aso55LwQ5Ysn1bOdA6CMR7PYVKsdKzLfJ9N1kZ1
qOVujqH3Kf/5uHFSA3pPM1CVAiL58NJqqZdNpmQcTv/l35XzVHt/qh/NKGRuigT63kZp/9JXNXON
8KIPj5BVIbPfz1gErmICx4MJ98JwYuXzDPHByBOgF6ee8pE7Z9wWveNGYUGfnInCesONFDMv/UtI
AOBwfBPE7/syxXY/Q9jgA1xLPMsFUZuOPYznCDEUoPExBMiISqjlv0xFmBWHc4aUUrTSU5yIHSfM
FdbOUb4AcRXiOntjhZEytpL1W4Q4BguYNg9jNzgP5tUC7SmbBla3X1tjA0oszoGAhXZsVMA3OlZG
LV56QiAvpeP53PXzhDYIKQFhWsc8MOo1t1W/fcfzcws0zlloy910eIwVzAfkrP3cucOp3obwVH5y
3K5RjSckB3fKKUcRdRQG5cy0esJHX1yDa9EqqC/ngBKpY8lydEFdYGteHlCaqiLmbYGkZLWTMldQ
LlvVcS7m3dPu0qzb3Nh/lmXih4AHXQHbs7Jrp33HEu1mzbDGfPTXAieaAcrs3edk1uL4npHWI2eY
Q6QqpYo93H0THE1rQbGFkZS8hudnmuNphXG7s18bUo6E+1Sl3c8n4s7UefK3Hg3c1rNkf9QNYAuC
k9DIuJ3+Fp9Hi8C84JTxMPzpA8Yue7mjXYN6FLpz1JD+amw8PlCjWWepNr9R53q4RbA5rbcZmNyJ
cIUVI4lCifMbNYlUkf5bcSrbk3N37DPosvXNMO0+cWdREtmD847YUtFE3PCu9QDwZW+evIC76SM/
M3Y+wzJ8gvCzqlAUR39lVBWu4KLXZQuBBkbS8lEqd30QcS2t1GXhLLY9ciej/+J1EZ7M8NEYts9m
wwVLISnvV7TiOEMZLsG3XCOx9FCKB7HIavbwI5npJgbA6zNS0M2u3rnqyxItFxq50xBH2ne064Fc
ZhC/EJRAmpEdgG8tZJv+7ZteaHdzdrAgBAUoe1vYvYWLKqWJWLmrPeCk98g8RmY91aJDdK6FIXxj
oFUmzeGSxyskLq2V0l49RWTr7rYlalyKzKbzYsnwoN/2FPUpf+gEvBCjsGUCP73KUcD7OUP8Fzd+
93cnspWfhua/8o56xZKQRJraIyKowhQQ5ER3DgJvXcsgofv/7Kepe+OtrqgUmC8U/Q+riAJlMgPE
+R6tvjF0+GBjMeUXNl1/V04Yq4rejUCuK6UCtBDCSfakV+u7AW98pNtqtHcA23BMWRp/kVDI8/dt
NW8aekHVPOv1Z53IBiAgRDMuqI2xN8OMGX2RBwDbup9cSgBh3+xOFpbwy1aI7LeYE7NXCqUettFV
ig4+JE16C36ZjyvMTUiB1aKO5puwIM0Qf4+5jrNp1oSZyljSAJ4a6R95AiXbhKWxaSa54jvqBF2i
VultK9J+qQunfavQEsxfJs3rWcBI2RyFpau8u0Os8mq24qcaJPneya0/01jOAHI4TzSdK4lGqHqk
vjRNq7cO553DWFf1hGAKW6+Rkn8ggaf+5uTfeU/zmGy28fcnqMCUobsWvaB076lRY9YDcF5Avtxa
zkaM21PehSrKj0NvlxzJq5+lYnSWdxEgEXT9uAFJZf1v2IJXtLxQvOE71IBkUYDUxnZRu+dRyoSU
sLKuSSbipmVN35Q5DqTsKs/+LYYZbk5tKnfwjZfcPk2qmlHKjulOjbvVIKwHaIdmTKxzyjIJXat0
qFciWeldr2cPnxmBWkFOI54XniF3IHJiDrGoE+IxMfAJZxfcKRCeJBYcik1pK3aU1DXd3YpHN2H9
EUuyypx7tARhloPqcbIeemIRI/ctYS33g4Z1nH6YKKOZ0Syk8AINeoPHK3X1/5JjV4LYQVxv17A4
/Oon4K4SS8NbEpGVSi+OQytVXJQfOW2fRXzZrEhErFjcNXp7pHNxyc9N9gSCaoLNBznVIAFIJCIt
aAIzybCch/Wg+6SfpOGH/VqWYeKv9MTZu9YZfXPlSUqNz5OzltwtlTBfuAFG7+YYLvOXaNuVdfFo
m0xEEpjfHcD2zMnwF+BJgWpVWm7x53Wg8AjUAZsz0bnze3kWo5QWIxs3y0/8lfTHiJ1L4Qx5uJE7
iEyHokC1CzmHMbYJHshpvkbdMMSU2saC9tgw8ewkL+pqf38l60fTrGfIB/cJFuMns64hhlGEtRvK
s/cenwUz8OokFEigmGE0fdzMg0KX6i8raswJgJi1iBOldgss0ZS/oN1U1FKix5Q/pVS13+NtH7CR
NoPIqkNhm1sRiN8JPdChEoSzcdbK9gOH/+h0min5seAx6sxaR1Wwnc8TRRn1GzCCFNZXT7vQSQYR
/tBznOFbLmV87XM//u1WBNenPhMDsTBpGjpcVZ9Tnzyj1pMZneBnmD7DSjcabpuRaU2m/2hCjZjg
jv0Y6EXddt9kYcUmz0ytpA8UdZ9FDkNbZzbGnNLxUfSXeIR049irUQ4GjgKXaIEapM9rKvPwBHVk
Z5xFPuwG0SVTodTdAKoNqrYtrY21CvpwXsasXRcO8Thke2rBc1jLZ+ii6zg4/PhPqggOMlhgx5Ln
A/+gaSi1Q6s1KXC9elFFLZNqU1LjfyMwwXadLfiiH4EIs+Ha2bd4nEh+pcYnupJbiwrusdfQWjrX
2elLF/Fah31pPntJXCqekobv7tUkNK6HADNf/YQdQ87CeubuxGmK6/gtm+RLoO/dZ3kANuu4icTZ
1fd9gEjG5pz+n+qxkaCtRQIKexFIgXw5lFFEZkJyzOw3423ftPBUZ0IFJ2SnVn7FeO0rcgEREs9X
GSEaxXRrOwiRVEv5WHQGglkyvwmhUZJKO41Cmlubsur33WBWMHOZXvWJwbOhAWMxfaR/i0LlgXrj
zjicpX81A0v+oughDtObHKgRoxHgSFMcbTdOsPJKAxKD5n8D3XwCEppF68nEkBpPpyokcIc1t40b
Uuw8Te/h1oO7YbX3yRSamYYpTUaWfzKWLV4q2CUBBnZDALqzzAr6p3bqeDna0aiEt6/iE51mbsQc
HiSUyJAdqPE5rNiZQbWPPzdy4EUeEbl3jeCNoIdz4LcU9mFhfX91jVEeSzi1AjRbud3/DFkhEFIb
CU193tf2JPSkQtjV3LZ7xlug6PXWwBjgL3yJmThmBRAYz3Go0tVcIbAiXlEseVua44R9YUswDysl
Ow2yOZEt7xU9+lpDlE78+M5Tk2PZDex9xWnQpbFM2q1iIy2+sgsvga/VWwwIPAGqYQkS6b8LviZb
FAJfiDlQwAUGID6RMAGVsAcw1t9L/CYdpPUaQyHCo0at7vBT6zPUckjNlALP/BynRvfQ1qe/qkA+
OehjbBPtfyNzRpPrc7BKOkUQADVGdQwHIIQyOnws9EWz/07Q1xlTr06SBw/tHl9lBmZWLdZae2Ls
nYK4dQNVYgkfmWV2DCSzQLwiXNU26zK01op/DXrU7ehaMsmLBfz6AiMZo5K4/5ZdrFo+juhtC5O5
io/PsTpuGURjbeECUZ7Houvz9yqrSdjukmbcbIHgoddrR25v1PkAGLqVaecLaIiaPOZ6/1yh5N+Q
Mg/YJ9XbAygoxPohYRgu8xym8cDBbKmb0pxZ6+Pt5uo3X/lmrV0ikKVKFxYSfQ/5IPMpuCAp5Jx2
9kwxBO4WXjfYq6/IyoHNfgc0MncGN7QhAj6I6zC2dAgLbbGBsC4V1b7T5T1oAc8iBhT938vdv9qn
RDP9oAHQKwJB6/yNykapItiDZSUcukGV4PJNMEEY0TheuoLxulwGdv6NmDbMRQ/EcSfkx90yY12V
Y273aDQEQqNWMOSamhMPnXBZYCgjs3bRCDPbUbhAeLaXl6O7t6XuPV5QcfgBUAzfbeK3yWnyRcOb
BIRO9fgFwVoagx7g58qGR3UZ+bUEhQZ+XJYq1nOU07STVT02OPIYDJADIoy1YO20uoPVlA/Qbp6p
SnSpIWiji2lqO1us2FvceOzpIXMQovQzZ+sSYLoKZzytO2+8HOqZvAmczxNZ5AaXor0MQEeX3BV6
iZWy1ZGHqGtXy0DTa6f3E2zHdxpC6g9/qbxgL4XvsfKnNnQ06TUr2JR9lMPjMa2W7ZT7WYMr9EvM
ARu3B0GdS9QVXS0suYpya+gZUybl+DYKPmDh1naAeXtGyBTtoa+dAFqvvUnn6uJpArMMDHF1WE8X
3JGqt+J888/QgpIG+W7Fl7nZfWQi2+ON3XyM4O5neZm9c2koKNUTIUpJrwH5Tr9SBRL/wxW0hLKJ
B6M+5VUqZ2PAcJGrpGqQbK6rWHlvHFzQJ9lN5YnTCbihfBBYQ91aNEA+QwAGZs5RU+2e4J9GnGh/
sL3WyqUyBTdjxSODINRFCS+Zb43pbMqFU5Im9i0Ab02e+WcswssxQEItmPvHB47CBEGaeYJL3Nyj
/pua+ORU4eyDfPZHS09gtj53Z+zIUH0Ht8HNPaZ+OMuzjaU3+ViW0pupGzW5xO2VF1740z+rcsla
MAxYmrvOizJ1FdWYwptksm0YFG9v5S0QtPEFfwaBEZUNoyxkQ9ulxgRkNBUSb+flfS59rp8BKzwG
8kAb6rQhJH2ybDbD01fxB9uE88v6VorCzDGlv7qZ+kEYOzJ8b88HcVysrYBXsCheginvPVznm5h3
tlJ9nG15QIDNP9+9S9khzrspZ3k+MvORCq/+SyYAsh/LjI6OiYgDklKjosxSqmtq/4IiU8GdotGo
OInmwLl47iLo6nrts0V95vCaeSj+y5Dbc5XeuvECwVb+GJODdzSRUN7q9eU1hcMeW54XyGah6mBG
feyzdO4zksAaOcbMPiXwqulmai9LDqrlJJm/y88UhByUNKpGmI8e6+2VkR8aB2B5s2LnLs7Iu9o3
Fl5O3yPqtxWODExdgqjaFtEFDygZsblzt9WJHCk2F+hBKVZnmoCmIu8OOTaazc/5tak8Q1nfyIqb
9AITSpcmxpWRAeGhT6zQFi1RdFgR2idKjp/fhBJmtIoyjrjsJHz3B4j+Ip+LisYC/w480UI4/kM0
yEGD37SEPYmLzlk59qET39AeEP7hxHWQOLbJjNZ3jAERUJNc7yhS1oQ1Twv1N/fDO4enrf0BdsqY
v/pK4MySiUdagJ9HqIQVX6Jz571iqkusUgMX8k7u5bPhgW2ZaT2fznGDwCt0Trb9Q8yCLSKyfmpr
oLYA6WeNIcCvZx02undKdC8/5dEz8a3hEdfo+QjeFd37x2ytD4ODeSurXf+OX5mi/KdFDhpz94Eg
LhonDWQhv9uNkssUhvcNtxmKiIe7MiuRQqA9I1jUUpO7h0+iEuObS0nigI/ApLQrMOnVaNkpXfmK
8rOGX07xoUi2mKLIGnhGAPVItr/0Jz3G9uhqFotOpnYjQb34YbCfMlQgUygFXr0uzIvhBzLysixd
UeUDHzbba5McNZE6QSKStRqTJpdzM/Yu9xtumUxEzCT1c3uYe2WFRiNPEM/tio0DMaluD2J+aD9h
IforGmf6zQKOHPTFd5KHSPN6nj53j4F1v+wtbSj+pTsG+mBJBHIe+Ug1yLcn4kFTdmOg/9Ee283L
e8XcLeEIJG+yJhr+5wMLOgoKQ2Upshol68+3LEX7HRjW0Z4WRkPpTQCDg4u9v/Sz1YyA3Y5Yb1xy
saGIcrLGiGb23ciU4QSodic8Jbpgq+NwemcOPuudNlhoIeYivzLYj0Q6tgR5QSwyPtixeciRXd3/
rRB4MuXdQAvuVdkTAR6MVUMa2GJrh3UtiiSfzbtkuLpetvwoO4ST0rx65624oGoa161WxxLvDNX1
Et0+RUv5aBott4hXpqXLaU01O53xHGFokP7mkpafTn6TQRV4hwCZNn9qBWBuT+EF8ZgE7SbbnZ4o
TqNxbzJR1sYQOzEuTGTSGOih1o2zWiQP1ZFXz/IfSj+g3g7pGSKLMwsCjgw4BedO/UKNWXWDIati
mSqiM6AK+cuTK+4RXJ+J9xFYVR1kngrQg3EgtpmgUuYUq5OwYEcD5JLL9NmbMP3SWBSaW0pXw2GF
4MMllM3nVfmFkYeGnYW25qnBustf3ajQivRLHSWhNJP8S6yS2r4rOghsMi3nT7p9oyavRBTMeS+k
+cNnDOgZcewiyyaHfpVXujfySbwXLOWeLn9tAIA7koIm0Va4hM+Kp4Gt/fmUNjLNSj4H2peWP69I
bPU3DYv1NtVglmt6YFSEc3x/AoawFXLhPKC913HHcaVdNfyziwmzGPL+5jjLKqxDHkP+G8RfkmUp
FakaPIvcAgKhwv9ftCGZER6voaL2aevo76tRaLkjhwCYHCrUoFZBEe62FN8gMtkN1gPkNwuDrC6a
NWXqQUwY6PVnCwqeBOep920MDxgqg8OH8Nk17r8eTnURmPP3A7Cynep33DIjROPY5ObBdnuRUJCV
IDWt0S6uN/FFa7aNvwlf9ESGASw1PzFYHDXUrl9mewGO6Hy8qu2cs45P0r2ufaEH1NpGTKnh8HWN
kWtcntdFD49trITUP7MJrzkf8/mq6AxFS0N+XgOQ9wKdD3J7ZbSw36XL76gXSSw2O2e4AlLQwx1L
9qXUxoUbxvle1DT9sQMNLWU+7/axr4wEAQw8iqE2gkgmoptOqPj2ZwpIkDJV2J7Ef9qtFCYrN4cm
tlQGPVHSd/dFmyk0Jae7flTTDmEeTNXk+UFXZweqKjrI6nnU9uxeD+AoYiiH0RmyRt05+PKY6B/0
gramsu6/jnYMJZDiVihLsgCwu84ewAxn4BM12gHSreR3sCmjsX0KkmPHXG7HOXMniwe1vJV8B4SO
ZDf22EAFittMsmC0ArMxzZKPJYFea2bHGNsaDknEoZ4aXhgOwGQGLkAhIepMzF+nSxNc65H5fqWz
1Iyt+fCRvWoqI+oC+Djq6ZOa2Du9abBHB8RGJ21vBqbKmIAatsmBR2ZBL7pVvFAfiCkZxA/GuVCW
UvokFMUU5O3T3vSI9DJb27rUCpSLpCGf+PE3fMbcRRIAindG3TIf1kU0exL1k/zqyYv5hSpG6k38
2aq+bNTO2L9ZTi8JQoRHMaLBma6NqEyrzs6Xx7ZIF4tMYL3zbfduGmbGucLmOtZLG/WGwEyOtbOd
fR5h/5QBU50+p6LrXbYtC1PAWS4pHB6N0/O0XR8ul0aGJTPx89IHI/A2+dFn1DpMTpMn6BX2HKAW
dE1SQKmTRC4DdptV31nA0mp7nofYFfflUr+mcIsbDVGePebRTfA1ZcmBkr8QRx8F+SHtGRGVmbps
XSsFyQKFGisILmHetxOXU3TPEOXBYGZLgh8uyk9oOnQkXKhH2/8mFKsvW4KPeUpXKpDYrhLsneYk
tD+k5TBpvK2s7+J+PgRUY100YCYXLCFGm+4l6qUR0BzialRUizXVQTW7nSRvnpJrZf6k4AG4R3ud
Pj63FNUe8NoCUsRDSgayuzWt7DodUVAhUknFYBxgbPRjOLet4BnV4fpKuHHDSzw+HM6DpatGGf8H
0yYGxUZFqn7Hf8U80cjaYLviCE1QJah8ZThZcXunn6hmsja6M1dmPeWMYjHRFGYjhgsN0U9BjAOY
UMOsBREGlUelO/098J5AGQYMFGpAHcD6UUlwbJEOy77Imhd9CM3vyzOtLjdUUQpNXDDWWnvTBslk
3jqOz8yUqTMjlc5BGv5TAXf0h39eDHl15FmMRSS03z9N1VDt3LMM2zDLHdJvofVSyPO6R/8RmJ2U
JJ5dUAhHdqzvmI1hlxBRncT6V/IrjX0snBq0Wov9MIOsrdBoJP93BDZpCIEVTBrTzXyXCAQAjSj3
1Pb6sWseXmiIi26+MZA40h12rsW93yFjOKj55GWnP3A5b5/Iqux1+ZIFjN2hJUXJawAwe+F8I+yN
jOida1InoKhnMXvYA7hJsSBON4/HTVp3KwEKNRxCCCdGtVsADKzIHmr7n50By7DHKY/5Bm2Fal9l
j/wmCFtF6aJ7bkbhSAjPrZwFCMPJ53BCXA5kOY+sp+BxheEk5xYRTOO/8QM3WiF3lMyBBCsX10Jd
OSy8ctUQ2u4oGVARUPq5kDecSsxdmQKgb/mLx060coCbMfKDMKimpfSGtateXb8HkAyLBCpNevPO
cWXeeF0owOmVyEduLl3hGQw87SMcHjgv63WHgq45zANtjAR1glsAv72Qd5Ww6gsUze4IpEYixEH6
UQUXetvPIeQKcpre1zdHzuiFTjUVN33Yr05oU/hmcX1IB+TMNy7poSt1K12uvOmag2mRoROMOgWo
XtxtETQfmUYue/WOMI+MuHcPn6DhnbsetNSVYW0ZzrJFhviO0RuNCNMJhHPtFAIAR9Y3V18dXQqk
+8IWZqcCCHHF9EBAmeAInmpz3AEE2Qs4iDmUPYcBZ+cFj4S7raY83tYRIBqU2UgO7LOoMAZ2rB3D
kkqbYDbLq7lALuibk0qCHZOgqa9vu8GS6MH3mQSgR1Wm/HJJX8bdxW3oQLCTpJPsWXHU+q0Y9LUM
ONwlDgC1KxT9bwZvkqRXrg8dP/N80I2xEcWaol79zTBmV1bGMQzRNCcCXYpWI64G3cCdxnefHqjp
tu3nfiar2VJ/Ax/D+O4DWJXbxNb9PtqBwG2d7qzZedRyZeTd4PMIOtxkK9kwMFHPAwpIXjqtYv3N
7vLqD3wEUjm5NOyep/F/LmxOgMDv6xQzmWp/UqLVZ+2hq445zaTudsyCPkGT2/1Dxp+v3Fn+Wuaf
HGc8Mp4+GtmcLi2Z/Y7/hESq0lfS7lLZwMS8ZY4qiN7qYUmVzmMgkzS+238bax7IqTFWAn+0hj8A
PWUeJ6fukqB/HFV/UKUQLefBiMg3Bzzr+MATELJ11s1910jSv0Wk3jAs0zd1rl9XlKRALVcr22e+
p60rEeIwSyiiuV/BBbDo/w0IO78ZdAX/Kj4nRKeaPUd6ThVIicRy9SXlWUdYEIqC709Lgkvbp7A5
7wjd2WBFyhPgRpd7AMO1alSu+zAxn+aQvZLlNX1HgdrauzqZI3ztIjmlRhthyi75e1VWbJr0qcha
I8gqOieX1SbLd/IEXyYkZtBT24OuNwI5Va3ihVKMv9dsHC5TS2hUb2U8PjDsLzoenyTu7PPVHexF
LAo3QmtC2z0SLttacGdJpc6cMmka0wn1DKMv0fQ76izwIi7tou7nFOjxwctkEyRNeH3wWmh/NuL1
eWKWGWN+WtO3nzZdKDXAaW+BVVXYcmSSmcdCz8s5UxHzn7zmAL7gHd4ENlM30LHU/mLDeCFVhA+B
SqsDLiqodwQIN81zSnG9s2WJ/54bxswz2cGZxnh54+SjRAlPqf+Mh1ZmTkl0a7tjGWfS/6Nslnn0
lhgPP20wu/YkVAVcQR+x163+tq6MzzGQOyBmmWAw+pYD24uVwLFuhMmej4dLHi0sLYNTI7tzVeg7
DBtUYulcDNiHm/ZjgLMgrfsvXWg0xRg6xoaTe3/hy/nfi/Jmudp63NxJnseb+UktrofniQ86TIJR
v/h0X1BIsvsSO1vTzmVFHX9zlO9OZRSRhxShC3PNK6a+MZkZ8eftnMPBqbMKOdgBB6RQzKl0vwMG
4zinrrIJIL+lLmNkpp65ssMYM/QuC0dPRgeOXZxDIGNeVnqQ9PBHCxUoaRqI52itc8h+expYbngb
tu54lGm0QOibt97D3O5HNlRcEsm9O4gixTSt4gFJdGTPPRpUJP6K6g9omQ8JUama6IPUL75yHDLJ
CrFwe7jxApv5PsLoi1pUp9W1SXGVtyj1fFaPYgjFezN9KecBqfPbLt4pSNZ52BrvPlmb+cksYfu9
taChHlVmOrP8/09xV86cbbYehYTcqu1ED0y/5jNk42wVgzMmFnxasQpe/nKQ5WHI1qHSQR6Skhll
WdJFw8me5imKDDVCDATQReDc1mAz2YT7RYN2DBiuFnsa+A5rScM3lK/zf5WE+AWhXiqppV//eDGc
+57ywlI7QLcaxfjcs0o4skPVgalowfz1z8GB2NWrjTaWEgdBumVPA55sMU0iOEEvtEyABztvksne
yIjt7LE2McY75v7ltTgJob0FEyVWuf4Dm44W+ix63P+pxQYdHdgkfRjwwXJi7IC5IaQgY65LcM/3
89/e9ubaa/IpFiwEfayVER0dZFRUv0bl15dCTSM4z53LiVJ3KHjU6AqNbQV1yvq8fxugcVoeSXuN
pNqN344n3mVDCP3KGegBjxpypetnd4f5q3FyOTc0dIAbRDEG4hzED8LOYPOvtPdHGRd2EkRzWz9K
Axj5QnV8aKXw7PGr7rhC/i3u9gqPp8DCbY2EsmNmT9ZEVaCHadq+nhfhrM2iuXFNLLBVPQ9uAoKe
rkU7ybzoF0LsQ0p8hytJLgd5o1R3bsC0JvMRPo7QBFLAUKtmWeHZFVOIX2r4TmwEv7qhD9nAMgz2
Lglvm749hdQifcHH2dQTZRvn2eB55NJlExDtEReEyVLGv2Mx1JxAY+0/GMEfpAOAG3ji9o4g5UPk
iaCTy6zUz8GyrIPMbc0Zez8qqYh9bsbpeN+CixtXteQHwK18Bk+EC95bEu+MWUvTOpQsjElGC8UY
NFCglflgaeuvFtIbi4lLYOH2sNVUs/DjeGak5ipoDhnrbsIkJoP9MFf3NNPFAFW+Hx/d+neL2mrt
NH31tGWGFceBEPv8/o1NuL0H9dtqbJlFYTTZTXnQQnf9xjcUZHhzxcbxHP5eL19NI1w1lrU27RlI
0/w5XtkRhnb3r7C3htYmk2vITYuLrjPBZ2E2vIjS6pzB6hTWeuNhI3uueqe3cVlYBw4RVn4XPR+f
PJmmRNVLT4ugVuI4KSSGyZu3/lrUqli68gCh4mOCWFWNmLhLjksmftUKzSRBANgNVg9HNYYEe3zE
5fKO45jsGVL8VH5CmD6FXmnTbOrTfF46+ePDCYjTBof6Hc7nbLx/XbYzOtBjxI7RTTkoMUwh7RVz
g12Sw+m2nAb2/KUxfwGCsBFJ0KKr3MSH8LW8UXS2rO+LAYKLW57Ri2HPQAVuoyNvVbg5Z1oVkjeG
2bdHNSyJ3fDs+Xpsp0eTdx/XzOsvvOAPSeA0/nIMKlgAVC3bPEWSmUDczlAuIrHPNid23W6MfX6F
mhKDdvIwLwa7hx4oOY/uc8igBu8tgD803dut+A7XvUJO8yDyFVWHE6LDfeo3u5wc8Bitn+xDJeDt
1JV/mS+29+TamnMoiHVMIXUvAm86lBhb1cGKubJFwjlLaLillDsDEuZwAywXFMIIAZu2dL85/u24
BF+RXPLSHT4lu+YG/ZMs7co+0e2V+Ghz5f4oogpozsWvaSPFMGTX8g4ZagbllvMrQzF3OO/ii4/c
XHcNHAMHQraIZ0ZmdvuK+IQTqssZyYtPNynWrIpoTSZvDqt+5RGqbDsoe2haAlU3zBP3/jzhNpdE
Oa+JEOmX81JuyQwpUiSa7arYVQgPxJdXUz1RSJ9jKcFQYcdwAU7TifLlsh6mSk8rZW3U9uyZpAew
Yy2lxj16EOIYYdtZLOL71iQY9rBCpgKfaRXb83LgasXizf5vEUV0EHioKTkTsV5GCaIu30o5AvPt
oDkbTS2dbKMakAqrDTqCagqfPkMil8nWynT7gbuZoWVo6GYwshoGGaLaO9X6FcNJQUrpVBiNMZbn
QLbv9XWJ8tSFjtvRLoXJOfdt5ZVwwb9j17Q8zWvmcpWNfg4MkCkBgYl4RIVJa1YuFncxkrLtR4F0
S+ika8NG/zdO7WkDm8huo6OkpTHZKWZsSJAx47dd7IZGyvUby/IuKs8/12xOBvKODQ35SiM3mZzi
/KujLqygsN7uZmhBGLNg/K2+xAebuMY0a+pLNr0yVfpUY5RvhepZNN/fQmvK8B2FcE92etkKhXHN
0iW99YGHJQ7yPhC/9EwD23mCxCGiyf5fUmqQrtxZbv/ZKqz2XLj8bVaUcHn8N/BHSSzyUlOddyhd
7wX/PdqW2/nxuBtKtwiBkhrOzvWudSdPgbggpe58jBjpxfni3jYEGFCyjQF+o3+53sBjIcvn3l28
iZ/JKqBPpIUZzdqjMImLqe+Djgva1Ozw0mHLDQDF4v1GL7wAEF5xDzJ5Nu/6K7ohPltziabx6MfC
0a/gRP7sfBoq8YFr+jnLl9a28wJxpuUN366MVHnEhnRMadqxDTglNhY0GvLSCSL/EXjsHZGP4S1p
JSJHuNXlufhfnfv4cksiM5x2PQtz0Un0hKW3usKzUEY3CpJeU71K+UhhArfKexxMUMsVfMZn7/+i
MjlcVCgqw256aGN2mHdYl8XwyTeXf1uV+Au5mPD7c9z+m66GGan+k5lVRMAWtT6jLqBSdQfOvjm/
TJdFSzx6W/vuafIDg09GLK4dJ30huPqv0UeFo70H8inA4yCjarDLfUzBAfpyhK+jCRg1r7BPUpDk
CiQWfe496NtHN0nN/dxKKuBPgC9pzCazd3Au/77D+R87x8y5sv6CZ2rtNsSaB/Q20xlLGeqLAs5c
uwhH3zV/A3AOUJtLj8L/O5nPMyFNUPmGywFxkfhAyPX/yi7U0OUmp/QM1OgCBinGwpKwHXTwUaHV
1TBuKUvVs03pP/HuefN4OzDMGy5GB5INvKB/4UuGGqnhHcZ6b4M0YgzHRICK9svPesJQyxt0RhKF
YvOIDA460FvP1Hj5I6PazPwLWXTYt1mmW7nIaohpiMptSsY2xjf/b1Ep370W0UkrLmmm5ChTXWaT
31wNxh7rqQl8zYAFLhkQVzrAAzMVPaP/OJXsnSDnvJD8tzjje2Cg+MRyeRkMtmEHV43mvgEY83Z8
EmZTqqW8MHYfBdie4QqYD+4IMIhR0AvZRtItCUlQeKJO7Lgg/93qkbEQ5yd1S6wvYLnbWFzRK69A
CG0U/2t6R2hNfQn7NPkKYuYWFX3gm9hH1s+BMqpRsCvbb4CQoyT8nif69n+TXm64YAySDoC8L/Kk
hsY65RnO6Gx8PA/pLYA6IYdKfX9a19pZwglUO0PT+aLFtv7u6dfXC/JaxIHqRAHeO3DwwyRMPIFX
12RdADSIYqGS019MpXplfnIuEQdiN+5mVLq5aPPEoHIhj19Bm/a1E569235AIq9fTaR65IDd6FrJ
8mIxf4oUCM59UhAIfBdwf+Q84FaDwIjhPF62AwsJNg2g7jF6LkSmhBXNahyk/w9RUi2xJQ/IWP+l
rusdKfxKH3aO9fQSjBtnMbfhFNphIiOWmFQh/nt3sKxXd/v3Y3Tx0IZ4gpS1wCgqAehYIdf64xby
3ibj+VbubmoYchVk4S/hwAekHyQVBP/ira+UsE9IMunYhFQX1NCtlONEHyRLoAup8QDiWfNSZ/hm
YQ/B17GBEnZwnXrySn4h3/5MB9e06vMFf5NadorqRfc+yXO+hb8PPi+D0n+fieW4SneyLHHvmys8
z/irYY7McUAhVv7bT2lQNrXbX3ok8DBf/13GXw74oMMpcZYooMeTLQ1n1VT8K6Lq5gbGz9CyLmaU
NhB/YZynDeUklPYtk683ZjuGBIOZCqrtat9HNeUSxX0UVAyYsqO14RT2Fw5hIXmOwSUwaTYXvuwf
YkNoY5Fp27XYMUsVcDjhweUe/wp/2FvKjN9CXRdybzNr27BM/exfmmy56Bv1c6Z3fgmcGD5wnsvy
H07V0K0IOWoK32+ldqI+dQbw6P0GyahPpr5AlWGF9vn91yE0pC2XiqLbrD7UATi5U0drCUC9lA42
uYc1HnUopDee1NEO3gG0Cn14nJo929P3cTaHhCOa8AxvrpOevznsS2yeXqj3oEf9p+mqZIPaHVIB
Db+KWLtlg5RaLI8gw76220Je2zhnWcY0LJO5DIJGRfEW2WY3ckcQQrdlE6uwqBlvZwkT3XwuGp1u
yc7CzZc1q6BapWV0g0NgwIEwcxfG3/OKR6NJa2F41YKzbUOSwcJkrZkaCJ7IyUAU01MoYBr9P1JF
GyxfeJq64/aqL4W8534cZ4TgFYI5Lz6+3ZP3LZLRf2m65EkSmr4C2aXqQ00RwLK3/ZZ97621z1g8
5A15xr582QJyOGAwfdy+jGEq+jDtltej8Chmo/eUNhB+MMf+R+Y4EveAw5d9vFgFNtYYMZZfCvk5
tMUlwQM/IHobQU56My2i8FlPmuyKev9wzC65lSx1ozx2P5AVHsk8JZevVXqKvUcp7fFH8b1IQ5U6
O0Ik7tqbrqbRpk+8oDcFbf6qPk5uclszgVS2DTi3/Dvneg/LucLlLi4GDNE3f/LSyYjOAnd9ZRn5
ffxGwd8R2Ov/MtbXoWw+sCMgN11UdRnsxpQx2xEp5uGtKqjNb6HxKh2Ol7wv5w3QhRVvixjqnlp6
I+0MLeKzcx/OqtaBL6ALWKgvHUJX38ql6nBpk8IbW5qSaRJ1NYN35/8LDxbW2hjlTpsgeqdWI6yN
psbnvUiMenA3bvc1ujyL51IR9Q8dtu4/+Fv9X6/9mNJJzxp7akvlg77F1SZv1coKh7CBXbCh2NtC
JFq483fW258u7flbz0UEuTIN/pJnWl+nwLohc+Pe6o2gVPk1lspeyjf/oVKKpskEVsonWT8nml1w
uxkY+17Au+1Fu7A3l3uAzlZHTtBOytESasHGasbWj5ZNE7SDn349Dqa1QsZi00GXMMFQ95LuZZbg
sG7MI7p5USsKFXsr/xVKHII7DuNy019/YaukToypIginQK/sXjsqcfE53c/b7qYjoMPF+bSuyd3g
0AoDur9Oxii8BQS6pXMRMf7iwrSetZ6iShYz4rFFbW7NshkBj16UvjNTdtuqTDWEHoiyuw9Nir2V
SKqR2DMSsLWWWqliy0T/fT8YIUaz1pfJp8zWT6YTuBghz+3J1QNHkUQxySUgtmFHmSmSrivME71w
Ty1IHR/MN7gqmnvFNlvmo4j+MWBbyHMq9//IG0bHkJfjgJ0ev1RWjK0zTaEhh2V4+Fxb7UqHHbyn
VsMV8QEgYYjx6N/uRGxgl1KC0ptprz7s06XyyTjioju2ChjasSyH+SjV32gBxRXWIvTgTmMTUML2
wVoAABzX0CYKIkTAW79hF00j3O0SXkJg1Y9J6b5JU9d/98jCsjR5Y2VX4wqUCvYuNFv5oBnH9Gnx
JO7aTBmkSXDzIHw4E8SSvSRWNa8z+x4PMFD0qt16etJcFwsBX1YdySRwD50PGNcA4ao9eoybb5o4
G/DjHS5caEtxbKOYqd+9GHDG7OQxIAiEGLA320fM8BmhKbx3mPEJaoZUcwQRVs7+xn4EeBwzGZOT
krgXUpK8SQJ2eldaTsJSdFrs9Mzy/JLlOsXVsQlpE8aWR/bi+VB++DqmUY0i0TW2jS50mWe7BYfJ
17/DjbxBLozg2l8FYT+K/SyN6KPcByQ280q4m0F8cx7RF8epYMFAir2qVJ1k2qbwdX40WXx8tyym
hUY1SiY7MsnYAINdg/xvU4uMW2Z3gYL2mhwYB35+kntg5qq0KRjQK2ph4mxVdTKuDhIyulF1qgjd
88YbMkeUy5pQvUqeJQ5Qfs02DDr9abQvpZkONbA063pP/pmmyhGPnt+PIkSthFOJSOsiXCzaZCvy
dz410sYezJnreKmvk40EJuqj5yKYoBKJLREuNrTLpfGnOofkDjfg8MML3ucrIa0d9toRtdnpLmI1
er4Hros8eJUbthUW6VLCTJicI7lW4y/fPbmG5PEAViM9KkmYRcrY0gwjUk9rLE/p4hC+WaBzR2Mz
w4mziRomb1txkUHCu62Mv8gzWYXOd0tvxolRVI8n1AyXBE9XN6TdkVeaRbZ8fiRSJXqcmPo+qbB1
GYoLBFgrmO7Uo3THJaEpC3gVHXYlK6Qi0S2pAgt8codvqUxZb8cKBTnwUMOs56N/E8D4l7WclRnq
fFG0JUA0EsDWKTMKTg2n3ROxP0J+EsmxfjagZcDjNcKYgtMOcP5W5hXKRn2jJIvNRmu8GX9xwTRE
bZFGsPaj1h8Vf95uyEThTnj5HhsHosp7W9yCVL80Nqj+wS1l90HIcRUd67jt75ojTg2tqUe9V7fh
f1ATFa5P4ZKga0+M6DavkaRRRl2HfUCuwldjo/p5X0uXdu2XuJMAqLOCsC70AHn7PYMfLf/GcfhT
CnkUhL+r2Ov+tqegMl0FnWp6bKzvxXJDbz43MkKojGkl7Pp4STpC7UTejj7Gl2T0qW6NrArg8G9b
Bn+TFDdzSix6scEVzydCdAjmgQJJeW+oZtl+dV2BOQhHjc/GnkPJ29hVyAyT3IPdT6hV5L5y/Ab1
triCeAZAOBl8lfJFbOeAirOLlWOnIM43YvR5wQQUpJHwNHFFhX3tQplkqdQVngQvVfpMhU950fgi
anE2NdWwvMz/E+3CNNTy2tX+8AGrM1HkUTCehOdZv5KfkwbgzYYmcRA27Cl4KQwSbXOpeJbLrEBo
3spa9qu9NRI527Fth1XG1okm9x1hyqSU2XIsm48QUy8HGN2cjXwMpG+XFf9+pC0cf8N287Y+4eCw
x900s7nqjqzlVLmhNaOxLYimlpZj6l5/mmpgF1erPFxZ3MnF4pmHHY8gzCVVllz0GubIIc3wsTfG
nNkR14fUD3F25Z+1SFRtB3G251BjBgwnFrjIOT+MU926kLHKsdtMfQ1uGvIG7IJQZ5FompDlOB33
bnWO6+cTCvjwFSobRBcJKtg95uJZw8vDtNLvwEyLkywigauh/LXSlCGG6+g3XWk4GjmaQ4SpeHN7
9iYDKPwycxVtkFaYA5csZ3ICqf3axLJfmbjTwOblipGK0ZdB3CSY+cEUjo44u5YxaF+YXEIY0FJw
lQEYvGAUecoVLyFFybb3ILLuxLmm4pNUWcIBPcT+HiGHCJFIcS9CJk35HVTBj0rT3HVc9ywFqwqx
ISTjhAtNliSNRhwhgOo7unRiiWDsFm9Qv8e0AsKiNrOP/rPA+BE11hx686q3fHvdvGMsW3hgz3jW
8QIoCk2APXPNNrrEGcPzUQ9UknfjBt/Ok1ykGMvyQ/1luyTyd4rS7GTN2Z+ztGXDhuIYKNj1ucaP
rHbQAWO45TgU3uUpOc3uu9hk7hOkwsyLDQNESHSZ+0Icpi8y6svbb6N3j27JsVd+3bK46wpq2K/M
8FUNcmUogxouEkpFsrfYANA450egmsE0T0vm7iqW1J6qVm8jYqA/xzC8wVOW5bMCXjLr5vsYTHQQ
8G+GTbcbd3EETP9th3DoJybBeHjErb6L7LmF9KQMrNhhSER6PRqmNY9mVdm3wSCabxgPbCG948om
5YSWv7Jpvunv79/x2Rmst+119egz0qxQDIZfTLdnL3ZAxnIwIl4muIj+7N5nwQZeGiO7HuDBwj6i
Hqg4j5qo+E4GZpy/rVwOTpHb6yEwqxkP9M5NzodvQKw+Fiz41BFbe4xg30y4fzpDIZOzDCK9Lxv0
MwJTMjwSNl7IksaeYImu9p/U9t94l3Fp8zwbkpT+m0/gtDv9mhIY5N4ISKIikZICMQT1PhhwuWlk
lGVQj/Ns6StBbJ1M/FjwGg7cW8HzI5ti2vTBV7czdHV5bt2puhKK224XyPs2UCeRsb2+bP90Qllc
keDnqKTUHbXaGUv7m47W936rV3IW6yeAn4AiVG01SEeYpQam7vPO/TYc18p/9jNaxRZdBCNqiybZ
ZwIYv9EfIJocu2J3rC0wcq0sGvuCdSg2G9S8Xb1Fb+/l5t6UviEmPZNnu+CHg9L2sYLBgq5OC7PK
YfCe3lkHWmmLr6miKx4i5OUj07g3idvadz8Ehr2XM/Sj2LLzoZH3BvCLj3OBvwI0+vxBWXp7XTQq
Dj4ZZHt0Z46ZLuNsvils066ne4t1t0DdVSeQIM+6TIGiV0Vaf/kWBOeZ/rE5FMNLq7g1mjeieMRT
wxWrugfjCTEl50YObtwmTsKX3fiwM6xmsrBvjsWwbL1kQ6TfFEfpiYWQUMH/oLBZNWpTWcETZJSi
lR6s10W6Y2H79ZXdRs5b2XNQBYHYteZf0RB5v4k0AwZmW1xx20p+ULDKSTA76JtVUWjSWIPjGK1Q
oHH+jYhumAorwcGxKNTZjEgh5qJrFnZRODw7MWSu1FHgllH3w0F1850Hi+W4imjmrnuD7rC2Nc8g
J8cjsMvDNxTzau0D/++JKG8JufaY7IwC4hHhr4ZnQZ+Wt2ybHxu8EhXOht8QvBkS1EvFduK9M/zS
Ism507EpL1LaccEYaiI6fMxu2UXNITTtXt08znYQzkNgFKzoXkyIoOg8t2jWO83uJ4on7vg9T/H/
4HwD2wHqyBcb+29xktZrizHIK/JOedQlU33qOfiNHnpJRFkd2kM2s4Ga2PMONEsBLlNGmK0xW87W
wdmXQvtl/hj92IbObDQwhaDNMWdxm/Tt+PUF69pllOXJpPzSo8bGPRERqpQRuCepy0URZlZiiJvX
K3pHDu+OlWOFan1xSjNj2efX8MYTIhH4UyPlDTVh0ZdBqv6UpeyUlRJfeKUisJsGWk2JUaUOa+wj
sZ8OFEgIv6NgG8bLnrUAwKqzwF32K1edMvPBB3EZbsfCHev1d1lLJmhzQ/KoCziXRAcSfpLlRbp8
vVqinDvVhuTSlAErMPCxdQoP/669AOJHjnHKQw1UgHwdX33JQnmH9C9Kj6WbqUXQ487bKmkqc5d2
S5lTN9ySDpk103BNrGK2PBKTgUv8lAQd6hxpm0gWq5dabeWiaXIGPmQkj4Fw5FYtT20E2PYRituO
N2l8siNozP5rh2YBeGOohpCo++vf5OzcBmI/7qBsZwLfcguFgPgY/ibEN/2QN9bJP9uCwsXXlumM
6LsFmq+/Q08ssHk2LLvouibo4p3qqnBgd/G3u8GPXtw4q3V23naVAdv4U+R8G2RIYNeVzbBZyBJX
f5BKFeGMAcSY8/8No+DE5jGT/1iuIV+nKVYEablE0inXmtZOZps4BJGiUfdR91S1YZvCUdC+3+KD
53z/03BAseoL0VFta/7sna4QIDptjA5zRdSKH82fUexsaQlIkBP0jGTsIoW0STsz+/FyXJuojbLj
8Bq2bLNv8R606M5kl3g3U5QBq9dKvNUVNqrW8Yf51kUhESQXML30LgmTxRX22xEj0thumQiEbd79
pHqpLNJ8GQH4ocPx6vjWIrLqGIL/Xpv7tL+k9ZrheBnnidcRGIYe2PzR8g60Botpr0vJIPS9qLr9
RCuU3babDHG6wwTYG46x+ZEjijfPXC/psZN86jAJ+6vVgT3XrdDokqc18NyyWrD0ysS9EpFxcnyK
Kl3ntMQGQlhR0mWymAokn0aFztcu5IsFxNVtIGwgFjBFUGYpESpEE48kTPFjYTVnzGt/jnLsmg7j
ooO0lAfv6fiMrfIJb8aweR8smKjBwXcH5P8QxEI0rK6VuNmwy6pledTaVXnABPfdYzwaW9Y9Lpcx
dQuJkh7TclC9CeOLC3QaYISJr9m885/GRAVk/jcrBmDtD1kaYDd7ZDHgRnggyn0tTk+SpOipDYLi
BkCytPvHO7sZDwX4C+ODm5v0ykGVQCTlOwyv9M5TFOW6eqBcNalRZyiOyR30n+wkBiF9K9Q6qPfU
E8a22kGoSPz/VqQlp/ZfaAQclbgpIkuDDhOgyjcPei5Fe1vqViHgjIA1fesX5LaG2Eru7gOsiPps
a1V60UV/q+wbA7B3k+eXqmqpncXIe0Xmk28gf+aNzj+xAudvKqRYCy1ktdICuIuXpTkzX7G2NAvk
efzGMGc7l2ZWWGWKcWiCjsRcqu1sjlJm1tvqEYcD36xhywz/9e1N4cwUfBgQMxFyuYq6POPeXBrB
1GamH1fy8eiMGFkIduvr8nllyhPfbVPrrG3DEkfnFqsBg078YMwO0WYp4BX00BfkR0HXn0di5Hlh
Khz+hgQXd9XW35r3g8OxH45mvWYdM2aGk3UJyGBkqlZBfmYmMlwmJZlRBhcdf6uSjlXOpUSf0w2G
oBxapJgLcns+xSRkPjhP7ivAOSvmF74pfh6en4hAzbzQwF9MI1GsFoUc9yGANunS8FLBBVyjmJmq
XHO47k8Ge3f85xepaqZatX6ZPgcGaG1UIDBsIwjvMT/WRD+r+cTP3akPW07FK7dVtTGpIE/10pr9
4HrmcTWLpYxN/AD6CRiTeYGZq3t/UO3vjI/kuLvdVsEKralzyPRFaO6QLCtQlaV/Ay3FGmKgW5j5
1VqKQqv4h221+S/pnl75gisCYR3+TUVeStXs/Yt9758BiIw/SLWU00xi3DPmNgp5vtttu/GDeTTr
z0cuZGjf6AFFrHrg/GpS5nfc+RzveSnr62QdH+ETrb2CWTr6ig2MXFhbnXxwvGB8QGpVffGeRBC3
8kIQry2tz1o8Gd2DjfG6HENXQsaKQckt62gFlUSnrSfFvGiYr+fG/tW21kdMkr31kp7RtxT28J+7
Y1dANCX2qr1DJObVUyex9qVI4/rnXoxehwTgJnqhlLnkAGjuw+jzUkF1eSeOL5z0Ngd+63pjtSEp
o/G9op8APUOt3kkEzrwuG9uY6lhFtO0IpuibaHX03/OqC7BuOrt8qpsnozw3K2RSmmT7ldEkYJW7
5IbsGuFRQJywDIcO9L8i3o21dumFNXZcDM0FWSUX80KCuJ1FIsf6tjYrzVP6erd2KdmbBvYFeG8o
IUO7lLHeSiyAu7kFXpMueLBDaCYbP5O1a7V3v+APCZNi4VxD1oQoiUpaB2jR+IqjwfWcEWBKpr7Z
yA1ITvRKH321dcM12F1stHBDjmE6y7/SnpSfHXPQkckpukSjNTTyjR6H9QtIU2Gc/UCm6jhWKUUF
xvQuRt8TgDUCrmRHF1Zh50QmEIu1elxPUzPRmNiP7iVN+XLb38NkkTkQ2axHjEEK/9rYGFC2PmIm
KB89luSvztu1cpAnXDeTj5boaSYtKXVL/upOknCm8UJ2gsNajpEfLA6XkHROvkUkodrHOy8cfDkk
ZPanJmJB2VKYFbEsFhZTjTKbPiLzxuOVcSiM2lBVxWuZKIg1TlHhJqupFmT7TlQ+EkK/Jny5glsx
l7rDfzzbRjX/mVOHQeHRkf7PsHhpxHItYX9iumaO8sIj7GfM9QUaYSdOWh4spBRLq/zDoO2dL7Un
W36PKl53Hm29Yir4FUmKC6TwzrPGlpaGKI4kCU/CJCCvbP9I3IfiBuoPUQY7mi7grRHljdekxDGR
uMmUTEejjmlju3HMph3ISh8Hi+TpFmIe1O4QzN47+2tCIDSM3NIcT8fLCBNpGIXSiJGvVdCffB1h
lKmJL+7qSpvjvUtY9bFMfJCkp/o4UG0nhiVvvLy6VNsxax1FJLLUA3jktbxDpsF6C2bTObjKyHxv
iwmJ6fk+Sg3K/zIRD8l3IYzqpUYfzFlEpkYl7fupo9xf/R2vYhU1mUjPzPCbNEpuNTpqk73AJ/Ql
mJhH+wN23IbGUihxO4FEKrKp0ZCCBtj39DGwP1AZZe5MWHLbeCuI4IqUU6ZRs8DHt7s3yODuCtSv
0yeRPp55LX2C2UJ+IVMalYUI0rSdvoW65TnNPI/w9nj43eekcmmCEMW16pwjmPG11Ih5/B4rlMxE
OBlm3l7rgxgpWGizZvncHZlNTd5jDtyfe8SG2TTUri5JabiUkS15bZu5cVc5qOEFRq934ISkdC58
6KP6ERnr94GFXfGCoXqSNaaKtiXyXMxNsLGN4UpoGLcTpU6U1xc6PLnczJKycaNJ/9NoS1e7APKm
J9djwtvJ4DRDtsnUrLefXJ2XBqyyLvPn8DR4oE03KOIyYvE9nlEClCSG5Ir821iLsn0c/DCOg+G0
gIoY8ot1y5cy3xr8zFQ+Rm66PDa4A+K12v5RrlWnBARYOkMvWamjZuDBpb2N1zcBEK22+2ikcVa7
nmm+Mg/YXm5f0zMDhCmcMHa8xw8c3JWThmp9mvnbuNgH6NP2PUHGiIZcp54UKdHclSkx9h6XbhSU
mv84keJhiqCC2JvKiy/D7g42JvZw1lT+X0/xqq2xyy5R+rTgEX+MPEuoo04b4e9b4rb/s8r4B10O
Nu3+2RmSbru0hgEOSuQEK+Zg3plLdckGg/yONHSt9J6/fiQqarA1CLp2Y0XuXI4NJRAHiOQxaGja
mxjvqgnympNcdm5vfwOn7kOPs9/7vC97+KECsFeVJra/O1yFbxVnmaFOT4MUQ//jfko3TSyTyDWz
w1LmTMQvwjImGJo5xBxR4OvlSnBHsuWs8W2wn/SV/tLiBdL0QEBtJUe+Rvva2I0BFMTBkPCrAaF8
DiyTi7Vc2sElxPKdn6gKSKGtfDdD+IkegJ8R021Uw/YDMnA+JpZoJ1nZVWHpqaSg2aFRkpUSTuWH
ebRlO1KrmA/GMkTqAJIVIji6OY15xb3F5TJQHOc/WignVhYqLBQaZzGTVXrobGdX4kBaEP1QOg35
R3sMl1AsGsXg+SHhy8D3m33J9J0Yfxr7c3RuWvOyrfKIiflx4M90s77Qsmpd/oAqHJI+59zEG6Ea
xuxuckaKzJBXQ+pwrZQZILHDDc277d3h9TWyb7vwndn2C0CvJwszvWgj1DMPC1TuvvbxS/TSctIr
+oWeGXTaCKIGGFLy+Az2J4fhQ9wXdqGP/qpZ6SzLs/Gi98ivx+GEZgcuGC3kYE36SXdBNi+b4EmC
tBzbbWji4haG2VBEyycJHXAJbTIYrShRCWPs60sL4KKBohRq8I/GBmtrLD1/BX2EcqcpKv3z6rIn
Qrh0Z2CnuV67JSzItaA6RNmU21Rs8bywwPWMacppN9PXJeIRLMZcoRYwL/bjwb7OyFCrAvi+nYe2
CaW3OBH46XKisqBigvk//YQHupxR7cRuaVn8f8Ipic8fQqIKyHSQ7ZZznDsQg2aTjwu03Xi8QM0A
MQg61wEKITblm2YoPUIL1+JMxU+LOE9xA268Yj5/CnKVyze6rYLPRF3TrshfVO1TEhFduzYMOMSC
/GfbGkTkWvhigBDUa/wagmbrxiMIhHYp36zc0adJnYhkqml7YkLuueX2BbomD6h3aq+3Zv+eNYI5
efwXiZXExyKvNO8lTNBVoY2CGAgLdVmJ2Tfv3jagMqNEyMuzLMZ2cyFBzfvDKwjttt2YFFszcT6k
a28q2NPzeOfIxxp4lUqcasY7jlxKna0V0o8DINJBcQvY2JW+TbMjeU7Q7ofykgNaSWwvmv+DtZbV
KMekk3qr1VNBmcqUvZh6NqSbJbw2ODwQe+y5SaHTSyP5LNOvRdMMDlH43tKhoHsP1F+Yywt60y3J
RssAK8iSDXM3H54rqygWX7vte+PIWZTgivf2YpbEsqvDgSFGgL8UNb+BJkk18SIA3v6xrCYWom2N
dkCDLqQo3HAWebhF6qrSXg0r7oOhtfVZ1ntH8qbMRHWUy8nNuysFXwcd0aegBxG1ny2ObhZQIFvd
fHFpvBhWhUfMYRVmS52QU+JlfuPjjIxkNCBO19Vuood9pm2s5WAAnb7ZzPQDddLiZOAYDgA2VKOy
0nasu0KKQXdddF38U+ALReLafNBRelo1PNLWzZMwmIi98qSGi2To0CyJ08yDWF+MCR1r8ICp2Q3W
qSyDA0xxx1Y0yYM6A30+z/XgR2hYWQaZOnzk55lLLEnMYHzQA4ziMb51PCXG+zn/YmAyABIplr7e
taKy4Wh2By6ztxW2o2mcvy8wItYU+ti5BAUfCVXZjcLV/FTp5RSm5MTwpXtexbEHwzltCKWs3Hsv
VlOjrEdNgWoQrOZVYNYKx29pK47C6D3hGBxPy7bs5gfjJLAP8014Er+22EA1GXxg3A0or5KoGoTH
qe6ocnaduk0da9RAOTZlInA/+KEdEDVv/O24Cf6JVphRlYOhdOaqKcDGmHM/RPhATt+0xCmgyfbx
Lbw4RWJGvw+7aNcR/VaNpqYRwpVVC5Nwsg5jds8f2yFJri92n1PLFTLA4tqFvuZlq8A/uaLAAT6d
lLvmcFWmTMqvmBfP64f/QGYRyao//P8WGITwTPHCmQzVQ0iDWDYdFUiSlWZ6+zQea3J0Yml6eFlf
2zO0brsBTxbna2ob2U/e86rhhSUvjzF8g73MhsFXZwAxCSFx8FdLv2a9yUKzl+LGyUlp9TcDTz2E
6eZ/A0xU8ZrM0OCsj1mhW3bYD2MzZYjJki1Desr3jIRvKvS8jeYrHqzJqJH6+23cQ7bimZa6HhE+
nfryYFir4/wSF9QZkQGbmkHn1ssMzRA1SKZ0t1YE91DUdxHJGjG8s8ALH5+wNqLJPAORJtF/GDcF
mU1caPGkg6vQqq5hkFbg2bePTjM1CMicwD2CXCNliGO6xEIwYaPwCSuWqgARYrNtnV5Hkg6b0lD4
Q1Brj6bRWbMpFDFSD/IC1XHVxxOH/AWs2IS1mRGWQdM38+rD3GFf8Jos2BjxXltELOwPGXw25Mi6
KGYGY6ooq9nh3NqpiRJHiKn5uhLlmp9Td7K9GX8zmJrhqotKgTnUNtvugdvKRmY+LOdNlsULwkXI
pGlFS9kNVPKOEPB6XrxymiZgG30fnRILv5I5Lb16njXR5Rs3mp4OOmG/RXdrdpNva26K95hmmuzJ
nIHLiXAMxRMAofcs/zNHJArjOfPgPyWw00x2rzbqEBrwgdjhDktOZLfOjtwYvqO4PGU1bQUTltIA
2fGHGvM3IcmQ02akbjoFDyJeFyx+Fdr+DFZvfZ1vIM8+lfmHT+RKyDbRbSTM+6ISjWZcbvFnBPvD
gcdKACLt6T3TcRG6MrMQ0ZLiiJCFzsOuTYbX4olwbmRuwa/P5mU3kj3D8kiUoFH4fk0ubrjNe8ul
JZWTih3sqJvoQHZpC55N+9RlhWCDM2AnjwkteHcYpH2gWQyIO6tDTkSDrKnx7rvop4p52rBOsDBM
BEI44jJZtYJWSgF5aJJ3vlupqZ3xHxo3hgHYRl5SDeZb6RA4BE2IIP5wbV1Dsmo2QXW2LD9PlIBo
NSlLG7rrF44cmMvGbr0gz2QfVVQynb22GAXpNfyYksM0nzArn6CjEGWEDAJwJTpxCPmFnOmpDKpB
76LvjGPzbBnQKCNjIBA+NsaRElC8ri6c5Fb2vHx803MjduX23Qv5Q9eVvDqUOLy5JR3pYfNwJzOL
FrLcTsRksw9ES+SUa+Dpp33/FyB9N0XMpknqAa/hKG63ur1DrEj95t5Wt7BSuK7fojQNcPCaOEce
NcMxyNWMUKgmd1z/y1UrXqBy259uqTVOhV6pVD0F2xCSrUYBDb80+ubyjUw6lhHXxGlObTxNk484
AiQncTDd7NqW4vNzt93la3UJdZ37VTFwTlJ/16NI782R8rerpK69X5KK5RMWGeCW4dIxJfY0cQpL
WGdleKtylIMH09BPVdT7WgfXKV8dZkePcxMBPKu9FLyEX3dIrC+XwR15SoFKfTMeRuudExu/OIX/
Td4p8wsUEGAQBTo85+g74WD0pQXI1Eeuq12W5sscVHB30MnpcGEtgy5FIYe7xtNWn0lUxRm7+ZzV
GClQaowohcWTXdxhKltUPn1IdPL6Mg00fXmyw6j/MVCp/E0e/2ei7tvxzsZ4lEeeYRISvzGM6nua
MLx2XzUnJWPTDCsdAmTYPdd/BO2gIT0ctsQepFQqTsDk3gf5l23Djifn1SgO+VDPpo93sQLel7kU
IwKhQyjVoi4Jl1l/ft7AtA5jmDxOupRsvrIp/TUABurbYFO/e0bKXX5QflKx6YoD2hsQ9laFhC7T
HkeoNmDdDPVWC6AGvc31TLs3X1RUbhWhP+ikHYQPzoT7sOzTUQWoiGRI29QaNZ0zuWOJvrBFhfUi
bOA1vqeu5372QPCOI38LtzvCIseIJupey/n74JYgkaWuKkJLM+mI/WHfNtW78OdAbERwdL+IGAAN
m2yaj6RVhCE+HV2UZmqxng64a9G21hzSLtyQ+aWUzWHk8eJoHDdxwTIujblwwNmZM8Yz7ILFkmXi
BhDQiVKPOyjjhSYmr6x/U3q1foAGHVTaS0n9rI0gqSl/jQHn6L4O0reGZKpH0wSbvTcVBfYR4LF3
V1d2ROE7ca7rZ23/s7UMfvKK1GeSc0uvAFh+cniP5zOeyFmvWtYWhuZfe8rB6A+kx+2l+qLnfdmV
8bJWitx9+rnkpGYYk1oUVLMDeKvsOtIvODmRmdU49Dic7h8QFCDvUpUbyIWiUFBs6gK9IyxE/JII
uJILr64zx6xKYSlMt1wXhUYtJeJyaUtVkBt8hGKFSuSRZwtVJLKG4I5xLzWAyG0LPIXgFwg0q5N/
qq+iI2gpYzIEf4CfozDwxNIZk09GeDQM1XVI5cVjeeTEIuihM92zWpcvRvfg6/cv/daV7qEFrBnQ
Wq+L9lsDqkFwykTdSxu2o4y/7bOqqm7N9GXasp34gzgBak6xmVeTFdh50J6qYTtLH+p5ZkVF/M3W
hq6R4RsCDQOigQWxxy5nY6gZJ9wkut0E36zacXRSuuIWdIowUvYIHRWiyPjAu8820EOf4akKUL09
nuhdktXtYLIiqlm8eRu4rkXB3j8A8B0ugqNt4aU8rNoddVPfYahHjS/Q27+TFl1iWxODZDPKoFkM
WvZkFQrhvJWK7rrvAi3joNz/4p9xTgdwb0xkGkzu48vfuIvVuOOG6YZjkxvKf2meCd8+h6dg0qRT
d40+lvQqBv7zkZV5rY4qGhN7nDc5ofRSM5bqP2blFDBaDbJgCiweCotusK4SJnL8+X/aMaarUsA+
L9/jpeDXtsQTXfk4VTaxw82tW9j++HxNoJtVwVdMkOQpkHfwNqbNxxD5Mj6lyILdXTlviz4qf7iS
TJ4NudcjGMtUZ2WCIHR4dt+Qt3vdIVCh5SUuD09XY6sJp/yx/hdzzXwrc7w5a/d9yGbHD5SRwgZC
QxadUetCG6wSJIgIJkUXC5ag1nsngPWD6BeTGHGj5mNytxkqBBywoVypm8ELG8FqT0uBQSA+LjvP
wt9ayfgNgjvDGVWl7Mx934FJI4DifyOi6xrZqb6NeTH1cAycVTE5XE6bjo/LRaDgOFvwBFDKpvGH
5Ew4WcoGWKoz6r1fpW8YroxYt9dKHODhhz3vKMqMF9Xz4aguzaLAHz+gnB5Rw8ltrYzoBQyju3Wp
M4P4mbmMUO4mjuJENkVq5cGcnnNz0svUEIySmk0lO61SHZTGXtHWlz/GzRgqMM2L19pdvc4Mqtdh
GXYdLplVT11/a2fF2XoUvjf58QbFadB5EKsjKbdbTxXWRIDD+mv+qO4BYx0SjyD5NHu77ZIQdhO0
qrRPzCqZn7rTtOzIOqsNNbroAv6nl7uTXnijUNsPlKR8yPS5AlJkDPNsdjvFiAXH8uO86ymC+hrh
IFPYTCeMqmTgG0rCr/ikAmSHQUmsYDTPmAZqkVWmJm3h1CsFF7GtBJAje9r8Ltw7SwUO1Zgsd76j
FrzyEPlm8Wme6dyCK/cRs/E3Xl21+0O21rDsBu/rfCsCfpE8UEik7J6rbWa7T0VqxeJyNA00nYSV
K1YhiJPJ5p3CYB3fjABn8S5syO9EOW48vTQhfMe5vZ+v57E3HHSd0OG0XcTpQwmmCmPO8bX1mMkO
5E3RKHcPOOYpwV+9xE9Ue22w9bFPupMY6fHTS0XXsKJYO3nJ/OJrZcHzyHJCbSd1QFMIaZomQno9
aRPoxBbqAMjSS3K/V517Hcc0SbpQsC+GYuUEDG7Y5fPWOPP8cxMHYCj4SQlcgjaa/9UjZxVi8YEp
kNuh5B6ZOtF0E5L2lFuzCcS8FjRwB2cnjbkbC5xqWCgxfPUE9ElLbYhivJGPvwFBT41DyVeb/2hV
uJ4ZQ6RZaxgzuh97HpqDEfVV88nbsEH6Bs2dJ4qSHEUZ4EDWBq6prCUD9ClilpL2K/nXDjxPe3B9
07D8le+daCsbgkoAuQd59tZRC2uZ3VyWB12XCRW9wt+kqijAU0Tpxuv5Jxlu5JI6nYf4TPL+1Dl6
ED9stZVCtx+E3S9sGPW9IvobMRMSjVrvA/x8foGXOpJE2QvpYHTaXH19XI0CN/++1O3duowugD2d
OrD6HtDs2WIn9GpBpY9xk4tiub24bRKBjYLP/C4uS2ZiUA0uxCrFlsgWNpjYD8nkjwxkwZn6SUr5
3MJt4L7cJV2ETex7U0hsUJRBYQH4spFOHcztFEhJseMJu60+e3Bl5q8lGU0g+LpRdKKC/+rCVUg0
wOGMBVVMwsFFRt7fs4XdEMLm6jkDfMpend3/lMQCy9pFXFGRvj7ulNEt3ylp6vu3NrCw9PXL9r+Y
0BChDLaFs3/mBoDw/avPq67x63hX3pZ1m+DSnqoQHqU7tTaWg5HZV3rym5fLWFxNWjykTaVEHxm+
Xmf6VwrYsSq1T8rw1cbxfcY82mnFVB9MXHbNF6rNY2hYyexVokTt9Rmobe23ThnHAq7hqEjPtUbz
dtTbS4o+XlpLoA==
`protect end_protected
|
package pkg is
type MULTI_LEVEL_LOGIC is (LOW, HIGH, RISING, FALLING, AMBIGUOUS);
type BIT is ('0', '1');
type SWITCH_LEVEL is ('0', '1', 'X');
type MIXED is ('0', '1', SOME_OTHER);
end;
library work;
use work.pkg.all;
entity foo is end;
architecture bar of foo is
signal a0 : MULTI_LEVEL_LOGIC; -- should be initialized to LOW
signal a1 : MULTI_LEVEL_LOGIC := LOW;
signal a2 : MULTI_LEVEL_LOGIC := HIGH;
signal a3 : MULTI_LEVEL_LOGIC := RISING;
signal a4 : MULTI_LEVEL_LOGIC := FALLING;
signal a5 : MULTI_LEVEL_LOGIC := AMBIGUOUS;
signal b0 : BIT; -- should be initialized to '0'
signal b1 : BIT := '0';
signal b2 : BIT := '1';
signal c0 : SWITCH_LEVEL; -- should be initialized to '0'
signal c1 : SWITCH_LEVEL := '0';
signal c2 : SWITCH_LEVEL := '1';
signal c3 : SWITCH_LEVEL := 'X';
signal d0 : MIXED; -- should be initialized to '0'
signal d1 : MIXED := '0';
signal d2 : MIXED := '1';
signal d3 : MIXED := SOME_OTHER;
begin end;
--!@ elab foo(bar)
--| entity @foo_bar () () {
--| %a0 = sig n5 0
--| %a1 = sig n5 0
--| %a2 = sig n5 1
--| %a3 = sig n5 2
--| %a4 = sig n5 3
--| %a5 = sig n5 4
--| %b0 = sig n2 0
--| %b1 = sig n2 0
--| %b2 = sig n2 1
--| %c0 = sig n3 0
--| %c1 = sig n3 0
--| %c2 = sig n3 1
--| %c3 = sig n3 2
--| %d0 = sig n3 0
--| %d1 = sig n3 0
--| %d2 = sig n3 1
--| %d3 = sig n3 2
--| }
|
-------------------------------------------------------------------------------
--
-- The Port 2 unit.
-- Implements the Port 2 logic.
--
-- $Id: p2.vhd,v 1.9 2006-06-20 00:46:04 arniml Exp $
--
-- Copyright (c) 2004, Arnim Laeuger ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t48/
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.t48_pack.word_t;
use work.t48_pack.nibble_t;
entity t48_p2 is
port (
-- Global Interface -------------------------------------------------------
clk_i : in std_logic;
res_i : in std_logic;
en_clk_i : in boolean;
xtal_i : in std_logic;
xtal_en_i : in boolean;
-- T48 Bus Interface ------------------------------------------------------
data_i : in word_t;
data_o : out word_t;
write_p2_i : in boolean;
write_exp_i : in boolean;
read_p2_i : in boolean;
read_reg_i : in boolean;
read_exp_i : in boolean;
-- Port 2 Interface -------------------------------------------------------
output_pch_i : in boolean;
pch_i : in nibble_t;
p2_i : in word_t;
p2_o : out word_t;
p2l_low_imp_o : out std_logic;
p2h_low_imp_o : out std_logic
);
end t48_p2;
use work.t48_pack.clk_active_c;
use work.t48_pack.res_active_c;
use work.t48_pack.bus_idle_level_c;
architecture rtl of t48_p2 is
-- the port output register
signal p2_q : word_t;
-- the low impedance markers
signal l_low_imp_q,
h_low_imp_q : std_logic;
signal en_clk_q : boolean;
signal l_low_imp_del_q,
h_low_imp_del_q : std_logic;
signal output_pch_q : boolean;
begin
-----------------------------------------------------------------------------
-- Process p2_regs
--
-- Purpose:
-- Implements the port output and expander registers.
--
p2_regs: process (res_i, clk_i)
begin
if res_i = res_active_c then
p2_q <= (others => '1');
l_low_imp_q <= '0';
h_low_imp_q <= '0';
elsif clk_i'event and clk_i = clk_active_c then
if en_clk_i then
-- default: reset low impedance marker
l_low_imp_q <= '0';
h_low_imp_q <= '0';
if write_p2_i then
-- write whole P2
p2_q <= data_i;
l_low_imp_q <= '1';
h_low_imp_q <= '1';
elsif write_exp_i then
-- write lower nibble of P2
p2_q(nibble_t'range) <= data_i(nibble_t'range);
l_low_imp_q <= '1';
end if;
end if;
end if;
end process p2_regs;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Process p2_port
--
-- Purpose:
-- Generates the output byte vector for Port 2.
-- It is a synchronous process clocked with XTAL. This ensures that
-- P2 data and low impedance markers are free of glitches and stabilize
-- during the same clock/machine state.
-- On the other hand, P2 is delayed by 1 XTAL cycle.
--
p2_port: process (res_i, xtal_i)
begin
if res_i = res_active_c then
p2_o <= (others => '1');
l_low_imp_del_q <= '0';
h_low_imp_del_q <= '0';
output_pch_q <= false;
en_clk_q <= false;
elsif xtal_i'event and xtal_i = clk_active_c then
if xtal_en_i then
-- delay clock enable by one XTAL period
en_clk_q <= en_clk_i;
p2_o <= p2_q;
output_pch_q <= output_pch_i;
if output_pch_i then
p2_o(nibble_t'range) <= pch_i;
end if;
-- generate low impedance trigger for one XTAL clock period after
-- global clock enable when
-- a) switching to or from PCH
-- b) l_low_imp_q is active
if en_clk_q and
((output_pch_q xor output_pch_i) or
l_low_imp_q = '1') then
l_low_imp_del_q <= '1';
else
l_low_imp_del_q <= '0';
end if;
-- generate low impedance trigger for on XTAL clock period after
-- global clock enable when
-- h_low_imp_q is active
if en_clk_q and
h_low_imp_q = '1' then
h_low_imp_del_q <= '1';
else
h_low_imp_del_q <= '0';
end if;
end if;
end if;
end process p2_port;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Process p2_data
--
-- Purpose:
-- Generates the T48 bus data.
--
p2_data: process (read_p2_i,
p2_i,
read_reg_i,
p2_q,
read_exp_i)
begin
data_o <= (others => bus_idle_level_c);
if read_p2_i then
if read_reg_i then
data_o <= p2_q;
elsif read_exp_i then
data_o <= "0000" & p2_i(nibble_t'range);
else
data_o <= p2_i;
end if;
end if;
end process p2_data;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Output Mapping.
-----------------------------------------------------------------------------
p2l_low_imp_o <= l_low_imp_del_q;
p2h_low_imp_o <= h_low_imp_del_q;
end rtl;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: not supported by cvs2svn $
-- Revision 1.8 2005/11/01 21:27:55 arniml
-- * change low impedance markers for P2
-- separate marker for low and high part
-- * p2_o output is also registered to prevent combinational
-- output to pads
--
-- Revision 1.7 2005/06/11 10:08:43 arniml
-- introduce prefix 't48_' for all packages, entities and configurations
--
-- Revision 1.6 2004/07/11 16:51:33 arniml
-- cleanup copyright notice
--
-- Revision 1.5 2004/05/17 13:52:46 arniml
-- Fix bug "ANL and ORL to P1/P2 read port status instead of port output register"
--
-- Revision 1.4 2004/04/24 23:44:25 arniml
-- move from std_logic_arith to numeric_std
--
-- Revision 1.3 2004/03/29 19:39:58 arniml
-- rename pX_limp to pX_low_imp
--
-- Revision 1.2 2004/03/28 13:11:43 arniml
-- rework Port 2 expander handling
--
-- Revision 1.1 2004/03/23 21:31:53 arniml
-- initial check-in
--
-------------------------------------------------------------------------------
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.conv_integer;
use ieee.std_logic_arith.conv_std_logic_vector;
use ieee.std_logic_unsigned.all;
--
-- MOTO NES FPGA On DE0-CV Environment Virtual Cuicuit Board
-- All of the components are assembled and instanciated on this board.
--
entity level_shift_test01 is
port (
pi_base_clk : in std_logic;
pi_sw : in std_logic_vector(9 downto 0);
pi_btn_n : in std_logic_vector(3 downto 0);
po_led_r : out std_logic_vector(9 downto 0);
po_led_g : out std_logic_vector(7 downto 0);
pio_gpio0 : inout std_logic_vector(7 downto 0);
pio_gpio1 : inout std_logic_vector(7 downto 0)
);
end level_shift_test01;
architecture rtl of level_shift_test01 is
--slow down button update timing.
constant FREQ_DEVIDE : integer := 1000000;
signal reg_cnt_devider : integer range 0 to FREQ_DEVIDE;
signal reg_8bit_cnt : std_logic_vector(7 downto 0);
signal wr_rst_n : std_logic;
signal wr_direction : std_logic;
signal wr_dvd : std_logic;
begin
wr_rst_n <= pi_btn_n(0);
wr_direction <= pi_sw(9);
wr_dvd <= pi_sw(8);
gpio_p : process (wr_rst_n, pi_base_clk)
begin
if (wr_rst_n = '0') then
pio_gpio0 <= (others => 'Z');
pio_gpio1 <= (others => 'Z');
po_led_r <= (others => '0');
po_led_g <= (others => '0');
elsif (rising_edge(pi_base_clk)) then
if (wr_direction = '0') then
--case off = cp gpio 1 to 0
pio_gpio0 <= (others => 'Z');
pio_gpio1 <= pi_sw(7 downto 0);
po_led_r <= pi_sw;
po_led_g <= pio_gpio0;
else
--on = cp gpio 0 to 1
pio_gpio0 <= reg_8bit_cnt;
pio_gpio1 <= (others => 'Z');
po_led_r(7 downto 0) <= pio_gpio1;
po_led_r(9 downto 8) <= pi_sw(9 downto 8);
po_led_g <= reg_8bit_cnt;
end if;
end if;
end process;
--key3 button proc.
key3_cnt_p : process (wr_rst_n, pi_base_clk)
begin
if (wr_rst_n = '0') then
reg_8bit_cnt <= (others => '0');
elsif (rising_edge(pi_base_clk)) then
if (wr_dvd = '1') then
--slow down count up
if (pi_btn_n(3) = '0' and reg_cnt_devider = 0) then
reg_8bit_cnt <= reg_8bit_cnt + 1;
end if;
else
--clock speed count up.
if (pi_btn_n(3) = '0') then
reg_8bit_cnt <= reg_8bit_cnt + 1;
end if;
end if;
end if;
end process;
--
cnt_devide_p : process (wr_rst_n, pi_base_clk)
begin
if (wr_rst_n = '0') then
reg_cnt_devider <= 0;
elsif (rising_edge(pi_base_clk)) then
reg_cnt_devider <= reg_cnt_devider + 1;
end if;
end process;
end rtl;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
procedure p1 is
variable v : integer;
procedure p2 is
variable v : integer;
begin -- p2
. . .
v := v + 1;
. . .
end procedure p2;
begin -- p1
. . .
v := 2 * v;
. . .
end procedure p1;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
procedure p1 is
variable v : integer;
procedure p2 is
variable v : integer;
begin -- p2
. . .
v := v + 1;
. . .
end procedure p2;
begin -- p1
. . .
v := 2 * v;
. . .
end procedure p1;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
procedure p1 is
variable v : integer;
procedure p2 is
variable v : integer;
begin -- p2
. . .
v := v + 1;
. . .
end procedure p2;
begin -- p1
. . .
v := 2 * v;
. . .
end procedure p1;
|
-- TestBench Template
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY testbench IS
END testbench;
ARCHITECTURE behavior OF testbench IS
-- Component Declaration
COMPONENT <component name>
PORT(
<port1> : IN std_logic;
<port2> : IN std_logic_vector(3 downto 0);
<port3> : OUT std_logic_vector(3 downto 0)
);
END COMPONENT;
SIGNAL <signal1> : std_logic;
SIGNAL <signal2> : std_logic_vector(3 downto 0);
BEGIN
-- Component Instantiation
uut: <component name> PORT MAP(
<port1> => <signal1>,
<port3> => <signal2>
);
-- Test Bench Statements
tb : PROCESS
BEGIN
wait for 100 ns; -- wait until global set/reset completes
-- Add user defined stimulus here
wait; -- will wait forever
END PROCESS tb;
-- End Test Bench
END;
|
-- TestBench Template
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY testbench IS
END testbench;
ARCHITECTURE behavior OF testbench IS
-- Component Declaration
COMPONENT <component name>
PORT(
<port1> : IN std_logic;
<port2> : IN std_logic_vector(3 downto 0);
<port3> : OUT std_logic_vector(3 downto 0)
);
END COMPONENT;
SIGNAL <signal1> : std_logic;
SIGNAL <signal2> : std_logic_vector(3 downto 0);
BEGIN
-- Component Instantiation
uut: <component name> PORT MAP(
<port1> => <signal1>,
<port3> => <signal2>
);
-- Test Bench Statements
tb : PROCESS
BEGIN
wait for 100 ns; -- wait until global set/reset completes
-- Add user defined stimulus here
wait; -- will wait forever
END PROCESS tb;
-- End Test Bench
END;
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity agito_memory_V_ram is
generic(
mem_type : string := "distributed";
dwidth : integer := 32;
awidth : integer := 5;
mem_size : integer := 30
);
port (
addr0 : in std_logic_vector(awidth-1 downto 0);
ce0 : in std_logic;
q0 : out std_logic_vector(dwidth-1 downto 0);
addr1 : in std_logic_vector(awidth-1 downto 0);
ce1 : in std_logic;
d1 : in std_logic_vector(dwidth-1 downto 0);
we1 : in std_logic;
clk : in std_logic
);
end entity;
architecture rtl of agito_memory_V_ram is
signal addr0_tmp : std_logic_vector(awidth-1 downto 0);
type mem_array is array (0 to mem_size-1) of std_logic_vector (dwidth-1 downto 0);
shared variable ram : mem_array := (
0 => "00110000000000000000000000000001",
1 to 29=> "00000000000000000000000000000000" );
attribute syn_ramstyle : string;
attribute syn_ramstyle of ram : variable is "select_ram";
attribute ram_style : string;
attribute ram_style of ram : variable is mem_type;
attribute EQUIVALENT_REGISTER_REMOVAL : string;
begin
memory_access_guard_0: process (addr0)
begin
addr0_tmp <= addr0;
--synthesis translate_off
if (CONV_INTEGER(addr0) > mem_size-1) then
addr0_tmp <= (others => '0');
else
addr0_tmp <= addr0;
end if;
--synthesis translate_on
end process;
p_memory_access_0: process (clk)
begin
if (clk'event and clk = '1') then
if (ce0 = '1') then
q0 <= ram(CONV_INTEGER(addr0_tmp));
end if;
end if;
end process;
p_memory_access_1: process (clk)
begin
if (clk'event and clk = '1') then
if (ce1 = '1') then
if (we1 = '1') then
ram(CONV_INTEGER(addr1)) := d1;
end if;
end if;
end if;
end process;
end rtl;
Library IEEE;
use IEEE.std_logic_1164.all;
entity agito_memory_V is
generic (
DataWidth : INTEGER := 32;
AddressRange : INTEGER := 30;
AddressWidth : INTEGER := 5);
port (
reset : IN STD_LOGIC;
clk : IN STD_LOGIC;
address0 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce0 : IN STD_LOGIC;
q0 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address1 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce1 : IN STD_LOGIC;
we1 : IN STD_LOGIC;
d1 : IN STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0));
end entity;
architecture arch of agito_memory_V is
component agito_memory_V_ram is
port (
clk : IN STD_LOGIC;
addr0 : IN STD_LOGIC_VECTOR;
ce0 : IN STD_LOGIC;
q0 : OUT STD_LOGIC_VECTOR;
addr1 : IN STD_LOGIC_VECTOR;
ce1 : IN STD_LOGIC;
d1 : IN STD_LOGIC_VECTOR;
we1 : IN STD_LOGIC);
end component;
begin
agito_memory_V_ram_U : component agito_memory_V_ram
port map (
clk => clk,
addr0 => address0,
ce0 => ce0,
q0 => q0,
addr1 => address1,
ce1 => ce1,
d1 => d1,
we1 => we1);
end architecture;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
library board;
use board.zpuino_config.all;
use board.zpu_config_hyperion.all;
use board.zpupkg_hyperion.all;
use board.zpuinopkg.all;
entity zpuino_debug_core_hyperion is
port (
clk: in std_logic;
rst: in std_logic;
dbg_in: in zpu_dbg_out_type;
dbg_out: out zpu_dbg_in_type;
dbg_reset: out std_logic;
jtag_data_chain_out: out std_logic_vector(98 downto 0);
jtag_ctrl_chain_in: in std_logic_vector(11 downto 0)
);
end entity;
architecture behave of zpuino_debug_core_hyperion is
signal enter_ss: std_logic :='0';
signal step: std_logic := '0';
signal status_injection_ready: std_logic;
signal status_injectmode: std_logic;
type state_type is (
state_idle,
state_debug,
state_enter_inject,
state_flush,
state_inject,
state_leave_inject,
state_step
);
type dbgregs_type is record
state: state_type;
step: std_logic;
inject: std_logic;
freeze: std_logic;
injectmode: std_logic;
reset: std_logic;
flush: std_logic;
opcode: std_logic_vector(7 downto 0);
end record;
signal dbgr: dbgregs_type;
signal injected: std_logic;
signal inject_q_in: std_logic := '0';
signal inject_q: std_logic := '0';
alias jtag_debug: std_logic is jtag_ctrl_chain_in(0);
alias jtag_inject: std_logic is jtag_ctrl_chain_in(1);
alias jtag_step: std_logic is jtag_ctrl_chain_in(2);
alias jtag_reset: std_logic is jtag_ctrl_chain_in(3);
alias jtag_opcode: std_logic_vector(7 downto 0) is jtag_ctrl_chain_in(11 downto 4);
signal pc_i: std_logic_vector(wordSize-1 downto 0);
signal sp_i: std_logic_vector(wordSize-1 downto 0);
begin
pc_i(wordSize-1 downto dbg_in.pc'high+1) <= (others => '0');
pc_i(dbg_in.pc'high downto dbg_in.pc'low) <= dbg_in.pc;
sp_i(wordSize-1 downto dbg_in.sp'high+1) <= (others => '0');
sp_i(dbg_in.sp'high downto dbg_in.sp'low) <= dbg_in.sp;
sp_i(dbg_in.sp'low-1 downto 0) <= (others => '0');
-- jtag chain output
jtag_data_chain_out <=
dbg_in.idim &
sp_i &
dbg_in.stacka &
pc_i &
dbg_in.brk &
status_injection_ready
;
status_injection_ready <= '1' when dbgr.state = state_debug else '0';
process(clk, rst, dbgr, dbg_in.valid, jtag_debug, jtag_opcode,
inject_q, dbg_in.ready, dbg_in.pc, dbg_in.idim, jtag_ctrl_chain_in)
variable w: dbgregs_type;
begin
w := dbgr;
if rst='1' then
w.state := state_idle;
w.reset := '0';
w.flush := '0';
w.injectmode := '0';
w.inject := '0';
w.step := '0';
w.freeze := '0';
injected <= '0';
else
injected <= '0';
case dbgr.state is
when state_idle =>
w.freeze := '0';
--if jtag_debug='1' then
-- w.freeze := '1';
-- w.state := state_debug;
--end if;
if jtag_debug='1' then
--if dbg_ready='1' then
w.injectmode := '1';
--w.opcode := jtag_opcode;
-- end if;
-- Wait for pipeline to finish
if dbg_in.valid='0' and dbg_in.ready='1' then
--report "Enter PC " & hstr(dbg_pc) & " IDIM flag " & chr(dbg_idim) severity note;
w.state:=state_debug;
end if;
--end if;
end if;
when state_debug =>
w.step := '0';
if inject_q='1' then
w.state := state_enter_inject;
w.injectmode := '1';
w.opcode := jtag_opcode;
elsif jtag_debug='0' then
w.flush:='1';
w.state := state_leave_inject;
end if;
when state_leave_inject =>
w.flush := '0';
w.injectmode:='0';
w.state := state_idle;
when state_enter_inject =>
-- w.state := state_flush;
w.state := state_inject;
when state_flush =>
w.flush := '1';
w.state := state_inject;
when state_inject =>
w.inject := '1';
w.flush := '0';
-- Here ?
injected <= '1';
w.state := state_step;
when state_step =>
injected <= '0';
w.inject := '0';
if dbg_in.valid='1' then
-- w.step := '1';
w.state := state_debug;
end if;
when others =>
end case;
end if;
if rising_edge(clk) then
dbgr <= w;
end if;
end process;
dbg_out.freeze <= dbgr.freeze;
--dbg_reset <= dbgr.reset;
dbg_out.inject <= dbgr.inject;
dbg_out.injectmode <= dbgr.injectmode;-- and dbg_ready;
dbg_out.step <= dbgr.step;
dbg_out.flush <= dbgr.flush;
dbg_out.opcode <= dbgr.opcode;
process(clk)
begin
if rising_edge(clk) then
dbg_reset <= jtag_ctrl_chain_in(3);
end if;
end process;
-- Synchronization stuff
process(jtag_inject, clk, injected, inject_q_in)
begin
if injected='1' then
inject_q <= '0';
inject_q_in <= '0';
else
if rising_edge(jtag_inject) then
inject_q_in <= '1';
--else
-- inject_q_in <= inject_q_in;
end if;
if rising_edge(clk) then
inject_q <= inject_q_in;
end if;
end if;
end process;
end behave;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
library board;
use board.zpuino_config.all;
use board.zpu_config_hyperion.all;
use board.zpupkg_hyperion.all;
use board.zpuinopkg.all;
entity zpuino_debug_core_hyperion is
port (
clk: in std_logic;
rst: in std_logic;
dbg_in: in zpu_dbg_out_type;
dbg_out: out zpu_dbg_in_type;
dbg_reset: out std_logic;
jtag_data_chain_out: out std_logic_vector(98 downto 0);
jtag_ctrl_chain_in: in std_logic_vector(11 downto 0)
);
end entity;
architecture behave of zpuino_debug_core_hyperion is
signal enter_ss: std_logic :='0';
signal step: std_logic := '0';
signal status_injection_ready: std_logic;
signal status_injectmode: std_logic;
type state_type is (
state_idle,
state_debug,
state_enter_inject,
state_flush,
state_inject,
state_leave_inject,
state_step
);
type dbgregs_type is record
state: state_type;
step: std_logic;
inject: std_logic;
freeze: std_logic;
injectmode: std_logic;
reset: std_logic;
flush: std_logic;
opcode: std_logic_vector(7 downto 0);
end record;
signal dbgr: dbgregs_type;
signal injected: std_logic;
signal inject_q_in: std_logic := '0';
signal inject_q: std_logic := '0';
alias jtag_debug: std_logic is jtag_ctrl_chain_in(0);
alias jtag_inject: std_logic is jtag_ctrl_chain_in(1);
alias jtag_step: std_logic is jtag_ctrl_chain_in(2);
alias jtag_reset: std_logic is jtag_ctrl_chain_in(3);
alias jtag_opcode: std_logic_vector(7 downto 0) is jtag_ctrl_chain_in(11 downto 4);
signal pc_i: std_logic_vector(wordSize-1 downto 0);
signal sp_i: std_logic_vector(wordSize-1 downto 0);
begin
pc_i(wordSize-1 downto dbg_in.pc'high+1) <= (others => '0');
pc_i(dbg_in.pc'high downto dbg_in.pc'low) <= dbg_in.pc;
sp_i(wordSize-1 downto dbg_in.sp'high+1) <= (others => '0');
sp_i(dbg_in.sp'high downto dbg_in.sp'low) <= dbg_in.sp;
sp_i(dbg_in.sp'low-1 downto 0) <= (others => '0');
-- jtag chain output
jtag_data_chain_out <=
dbg_in.idim &
sp_i &
dbg_in.stacka &
pc_i &
dbg_in.brk &
status_injection_ready
;
status_injection_ready <= '1' when dbgr.state = state_debug else '0';
process(clk, rst, dbgr, dbg_in.valid, jtag_debug, jtag_opcode,
inject_q, dbg_in.ready, dbg_in.pc, dbg_in.idim, jtag_ctrl_chain_in)
variable w: dbgregs_type;
begin
w := dbgr;
if rst='1' then
w.state := state_idle;
w.reset := '0';
w.flush := '0';
w.injectmode := '0';
w.inject := '0';
w.step := '0';
w.freeze := '0';
injected <= '0';
else
injected <= '0';
case dbgr.state is
when state_idle =>
w.freeze := '0';
--if jtag_debug='1' then
-- w.freeze := '1';
-- w.state := state_debug;
--end if;
if jtag_debug='1' then
--if dbg_ready='1' then
w.injectmode := '1';
--w.opcode := jtag_opcode;
-- end if;
-- Wait for pipeline to finish
if dbg_in.valid='0' and dbg_in.ready='1' then
--report "Enter PC " & hstr(dbg_pc) & " IDIM flag " & chr(dbg_idim) severity note;
w.state:=state_debug;
end if;
--end if;
end if;
when state_debug =>
w.step := '0';
if inject_q='1' then
w.state := state_enter_inject;
w.injectmode := '1';
w.opcode := jtag_opcode;
elsif jtag_debug='0' then
w.flush:='1';
w.state := state_leave_inject;
end if;
when state_leave_inject =>
w.flush := '0';
w.injectmode:='0';
w.state := state_idle;
when state_enter_inject =>
-- w.state := state_flush;
w.state := state_inject;
when state_flush =>
w.flush := '1';
w.state := state_inject;
when state_inject =>
w.inject := '1';
w.flush := '0';
-- Here ?
injected <= '1';
w.state := state_step;
when state_step =>
injected <= '0';
w.inject := '0';
if dbg_in.valid='1' then
-- w.step := '1';
w.state := state_debug;
end if;
when others =>
end case;
end if;
if rising_edge(clk) then
dbgr <= w;
end if;
end process;
dbg_out.freeze <= dbgr.freeze;
--dbg_reset <= dbgr.reset;
dbg_out.inject <= dbgr.inject;
dbg_out.injectmode <= dbgr.injectmode;-- and dbg_ready;
dbg_out.step <= dbgr.step;
dbg_out.flush <= dbgr.flush;
dbg_out.opcode <= dbgr.opcode;
process(clk)
begin
if rising_edge(clk) then
dbg_reset <= jtag_ctrl_chain_in(3);
end if;
end process;
-- Synchronization stuff
process(jtag_inject, clk, injected, inject_q_in)
begin
if injected='1' then
inject_q <= '0';
inject_q_in <= '0';
else
if rising_edge(jtag_inject) then
inject_q_in <= '1';
--else
-- inject_q_in <= inject_q_in;
end if;
if rising_edge(clk) then
inject_q <= inject_q_in;
end if;
end if;
end process;
end behave;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
library board;
use board.zpuino_config.all;
use board.zpu_config_hyperion.all;
use board.zpupkg_hyperion.all;
use board.zpuinopkg.all;
entity zpuino_debug_core_hyperion is
port (
clk: in std_logic;
rst: in std_logic;
dbg_in: in zpu_dbg_out_type;
dbg_out: out zpu_dbg_in_type;
dbg_reset: out std_logic;
jtag_data_chain_out: out std_logic_vector(98 downto 0);
jtag_ctrl_chain_in: in std_logic_vector(11 downto 0)
);
end entity;
architecture behave of zpuino_debug_core_hyperion is
signal enter_ss: std_logic :='0';
signal step: std_logic := '0';
signal status_injection_ready: std_logic;
signal status_injectmode: std_logic;
type state_type is (
state_idle,
state_debug,
state_enter_inject,
state_flush,
state_inject,
state_leave_inject,
state_step
);
type dbgregs_type is record
state: state_type;
step: std_logic;
inject: std_logic;
freeze: std_logic;
injectmode: std_logic;
reset: std_logic;
flush: std_logic;
opcode: std_logic_vector(7 downto 0);
end record;
signal dbgr: dbgregs_type;
signal injected: std_logic;
signal inject_q_in: std_logic := '0';
signal inject_q: std_logic := '0';
alias jtag_debug: std_logic is jtag_ctrl_chain_in(0);
alias jtag_inject: std_logic is jtag_ctrl_chain_in(1);
alias jtag_step: std_logic is jtag_ctrl_chain_in(2);
alias jtag_reset: std_logic is jtag_ctrl_chain_in(3);
alias jtag_opcode: std_logic_vector(7 downto 0) is jtag_ctrl_chain_in(11 downto 4);
signal pc_i: std_logic_vector(wordSize-1 downto 0);
signal sp_i: std_logic_vector(wordSize-1 downto 0);
begin
pc_i(wordSize-1 downto dbg_in.pc'high+1) <= (others => '0');
pc_i(dbg_in.pc'high downto dbg_in.pc'low) <= dbg_in.pc;
sp_i(wordSize-1 downto dbg_in.sp'high+1) <= (others => '0');
sp_i(dbg_in.sp'high downto dbg_in.sp'low) <= dbg_in.sp;
sp_i(dbg_in.sp'low-1 downto 0) <= (others => '0');
-- jtag chain output
jtag_data_chain_out <=
dbg_in.idim &
sp_i &
dbg_in.stacka &
pc_i &
dbg_in.brk &
status_injection_ready
;
status_injection_ready <= '1' when dbgr.state = state_debug else '0';
process(clk, rst, dbgr, dbg_in.valid, jtag_debug, jtag_opcode,
inject_q, dbg_in.ready, dbg_in.pc, dbg_in.idim, jtag_ctrl_chain_in)
variable w: dbgregs_type;
begin
w := dbgr;
if rst='1' then
w.state := state_idle;
w.reset := '0';
w.flush := '0';
w.injectmode := '0';
w.inject := '0';
w.step := '0';
w.freeze := '0';
injected <= '0';
else
injected <= '0';
case dbgr.state is
when state_idle =>
w.freeze := '0';
--if jtag_debug='1' then
-- w.freeze := '1';
-- w.state := state_debug;
--end if;
if jtag_debug='1' then
--if dbg_ready='1' then
w.injectmode := '1';
--w.opcode := jtag_opcode;
-- end if;
-- Wait for pipeline to finish
if dbg_in.valid='0' and dbg_in.ready='1' then
--report "Enter PC " & hstr(dbg_pc) & " IDIM flag " & chr(dbg_idim) severity note;
w.state:=state_debug;
end if;
--end if;
end if;
when state_debug =>
w.step := '0';
if inject_q='1' then
w.state := state_enter_inject;
w.injectmode := '1';
w.opcode := jtag_opcode;
elsif jtag_debug='0' then
w.flush:='1';
w.state := state_leave_inject;
end if;
when state_leave_inject =>
w.flush := '0';
w.injectmode:='0';
w.state := state_idle;
when state_enter_inject =>
-- w.state := state_flush;
w.state := state_inject;
when state_flush =>
w.flush := '1';
w.state := state_inject;
when state_inject =>
w.inject := '1';
w.flush := '0';
-- Here ?
injected <= '1';
w.state := state_step;
when state_step =>
injected <= '0';
w.inject := '0';
if dbg_in.valid='1' then
-- w.step := '1';
w.state := state_debug;
end if;
when others =>
end case;
end if;
if rising_edge(clk) then
dbgr <= w;
end if;
end process;
dbg_out.freeze <= dbgr.freeze;
--dbg_reset <= dbgr.reset;
dbg_out.inject <= dbgr.inject;
dbg_out.injectmode <= dbgr.injectmode;-- and dbg_ready;
dbg_out.step <= dbgr.step;
dbg_out.flush <= dbgr.flush;
dbg_out.opcode <= dbgr.opcode;
process(clk)
begin
if rising_edge(clk) then
dbg_reset <= jtag_ctrl_chain_in(3);
end if;
end process;
-- Synchronization stuff
process(jtag_inject, clk, injected, inject_q_in)
begin
if injected='1' then
inject_q <= '0';
inject_q_in <= '0';
else
if rising_edge(jtag_inject) then
inject_q_in <= '1';
--else
-- inject_q_in <= inject_q_in;
end if;
if rising_edge(clk) then
inject_q <= inject_q_in;
end if;
end if;
end process;
end behave;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
library board;
use board.zpuino_config.all;
use board.zpu_config_hyperion.all;
use board.zpupkg_hyperion.all;
use board.zpuinopkg.all;
entity zpuino_debug_core_hyperion is
port (
clk: in std_logic;
rst: in std_logic;
dbg_in: in zpu_dbg_out_type;
dbg_out: out zpu_dbg_in_type;
dbg_reset: out std_logic;
jtag_data_chain_out: out std_logic_vector(98 downto 0);
jtag_ctrl_chain_in: in std_logic_vector(11 downto 0)
);
end entity;
architecture behave of zpuino_debug_core_hyperion is
signal enter_ss: std_logic :='0';
signal step: std_logic := '0';
signal status_injection_ready: std_logic;
signal status_injectmode: std_logic;
type state_type is (
state_idle,
state_debug,
state_enter_inject,
state_flush,
state_inject,
state_leave_inject,
state_step
);
type dbgregs_type is record
state: state_type;
step: std_logic;
inject: std_logic;
freeze: std_logic;
injectmode: std_logic;
reset: std_logic;
flush: std_logic;
opcode: std_logic_vector(7 downto 0);
end record;
signal dbgr: dbgregs_type;
signal injected: std_logic;
signal inject_q_in: std_logic := '0';
signal inject_q: std_logic := '0';
alias jtag_debug: std_logic is jtag_ctrl_chain_in(0);
alias jtag_inject: std_logic is jtag_ctrl_chain_in(1);
alias jtag_step: std_logic is jtag_ctrl_chain_in(2);
alias jtag_reset: std_logic is jtag_ctrl_chain_in(3);
alias jtag_opcode: std_logic_vector(7 downto 0) is jtag_ctrl_chain_in(11 downto 4);
signal pc_i: std_logic_vector(wordSize-1 downto 0);
signal sp_i: std_logic_vector(wordSize-1 downto 0);
begin
pc_i(wordSize-1 downto dbg_in.pc'high+1) <= (others => '0');
pc_i(dbg_in.pc'high downto dbg_in.pc'low) <= dbg_in.pc;
sp_i(wordSize-1 downto dbg_in.sp'high+1) <= (others => '0');
sp_i(dbg_in.sp'high downto dbg_in.sp'low) <= dbg_in.sp;
sp_i(dbg_in.sp'low-1 downto 0) <= (others => '0');
-- jtag chain output
jtag_data_chain_out <=
dbg_in.idim &
sp_i &
dbg_in.stacka &
pc_i &
dbg_in.brk &
status_injection_ready
;
status_injection_ready <= '1' when dbgr.state = state_debug else '0';
process(clk, rst, dbgr, dbg_in.valid, jtag_debug, jtag_opcode,
inject_q, dbg_in.ready, dbg_in.pc, dbg_in.idim, jtag_ctrl_chain_in)
variable w: dbgregs_type;
begin
w := dbgr;
if rst='1' then
w.state := state_idle;
w.reset := '0';
w.flush := '0';
w.injectmode := '0';
w.inject := '0';
w.step := '0';
w.freeze := '0';
injected <= '0';
else
injected <= '0';
case dbgr.state is
when state_idle =>
w.freeze := '0';
--if jtag_debug='1' then
-- w.freeze := '1';
-- w.state := state_debug;
--end if;
if jtag_debug='1' then
--if dbg_ready='1' then
w.injectmode := '1';
--w.opcode := jtag_opcode;
-- end if;
-- Wait for pipeline to finish
if dbg_in.valid='0' and dbg_in.ready='1' then
--report "Enter PC " & hstr(dbg_pc) & " IDIM flag " & chr(dbg_idim) severity note;
w.state:=state_debug;
end if;
--end if;
end if;
when state_debug =>
w.step := '0';
if inject_q='1' then
w.state := state_enter_inject;
w.injectmode := '1';
w.opcode := jtag_opcode;
elsif jtag_debug='0' then
w.flush:='1';
w.state := state_leave_inject;
end if;
when state_leave_inject =>
w.flush := '0';
w.injectmode:='0';
w.state := state_idle;
when state_enter_inject =>
-- w.state := state_flush;
w.state := state_inject;
when state_flush =>
w.flush := '1';
w.state := state_inject;
when state_inject =>
w.inject := '1';
w.flush := '0';
-- Here ?
injected <= '1';
w.state := state_step;
when state_step =>
injected <= '0';
w.inject := '0';
if dbg_in.valid='1' then
-- w.step := '1';
w.state := state_debug;
end if;
when others =>
end case;
end if;
if rising_edge(clk) then
dbgr <= w;
end if;
end process;
dbg_out.freeze <= dbgr.freeze;
--dbg_reset <= dbgr.reset;
dbg_out.inject <= dbgr.inject;
dbg_out.injectmode <= dbgr.injectmode;-- and dbg_ready;
dbg_out.step <= dbgr.step;
dbg_out.flush <= dbgr.flush;
dbg_out.opcode <= dbgr.opcode;
process(clk)
begin
if rising_edge(clk) then
dbg_reset <= jtag_ctrl_chain_in(3);
end if;
end process;
-- Synchronization stuff
process(jtag_inject, clk, injected, inject_q_in)
begin
if injected='1' then
inject_q <= '0';
inject_q_in <= '0';
else
if rising_edge(jtag_inject) then
inject_q_in <= '1';
--else
-- inject_q_in <= inject_q_in;
end if;
if rising_edge(clk) then
inject_q <= inject_q_in;
end if;
end if;
end process;
end behave;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
library board;
use board.zpuino_config.all;
use board.zpu_config_hyperion.all;
use board.zpupkg_hyperion.all;
use board.zpuinopkg.all;
entity zpuino_debug_core_hyperion is
port (
clk: in std_logic;
rst: in std_logic;
dbg_in: in zpu_dbg_out_type;
dbg_out: out zpu_dbg_in_type;
dbg_reset: out std_logic;
jtag_data_chain_out: out std_logic_vector(98 downto 0);
jtag_ctrl_chain_in: in std_logic_vector(11 downto 0)
);
end entity;
architecture behave of zpuino_debug_core_hyperion is
signal enter_ss: std_logic :='0';
signal step: std_logic := '0';
signal status_injection_ready: std_logic;
signal status_injectmode: std_logic;
type state_type is (
state_idle,
state_debug,
state_enter_inject,
state_flush,
state_inject,
state_leave_inject,
state_step
);
type dbgregs_type is record
state: state_type;
step: std_logic;
inject: std_logic;
freeze: std_logic;
injectmode: std_logic;
reset: std_logic;
flush: std_logic;
opcode: std_logic_vector(7 downto 0);
end record;
signal dbgr: dbgregs_type;
signal injected: std_logic;
signal inject_q_in: std_logic := '0';
signal inject_q: std_logic := '0';
alias jtag_debug: std_logic is jtag_ctrl_chain_in(0);
alias jtag_inject: std_logic is jtag_ctrl_chain_in(1);
alias jtag_step: std_logic is jtag_ctrl_chain_in(2);
alias jtag_reset: std_logic is jtag_ctrl_chain_in(3);
alias jtag_opcode: std_logic_vector(7 downto 0) is jtag_ctrl_chain_in(11 downto 4);
signal pc_i: std_logic_vector(wordSize-1 downto 0);
signal sp_i: std_logic_vector(wordSize-1 downto 0);
begin
pc_i(wordSize-1 downto dbg_in.pc'high+1) <= (others => '0');
pc_i(dbg_in.pc'high downto dbg_in.pc'low) <= dbg_in.pc;
sp_i(wordSize-1 downto dbg_in.sp'high+1) <= (others => '0');
sp_i(dbg_in.sp'high downto dbg_in.sp'low) <= dbg_in.sp;
sp_i(dbg_in.sp'low-1 downto 0) <= (others => '0');
-- jtag chain output
jtag_data_chain_out <=
dbg_in.idim &
sp_i &
dbg_in.stacka &
pc_i &
dbg_in.brk &
status_injection_ready
;
status_injection_ready <= '1' when dbgr.state = state_debug else '0';
process(clk, rst, dbgr, dbg_in.valid, jtag_debug, jtag_opcode,
inject_q, dbg_in.ready, dbg_in.pc, dbg_in.idim, jtag_ctrl_chain_in)
variable w: dbgregs_type;
begin
w := dbgr;
if rst='1' then
w.state := state_idle;
w.reset := '0';
w.flush := '0';
w.injectmode := '0';
w.inject := '0';
w.step := '0';
w.freeze := '0';
injected <= '0';
else
injected <= '0';
case dbgr.state is
when state_idle =>
w.freeze := '0';
--if jtag_debug='1' then
-- w.freeze := '1';
-- w.state := state_debug;
--end if;
if jtag_debug='1' then
--if dbg_ready='1' then
w.injectmode := '1';
--w.opcode := jtag_opcode;
-- end if;
-- Wait for pipeline to finish
if dbg_in.valid='0' and dbg_in.ready='1' then
--report "Enter PC " & hstr(dbg_pc) & " IDIM flag " & chr(dbg_idim) severity note;
w.state:=state_debug;
end if;
--end if;
end if;
when state_debug =>
w.step := '0';
if inject_q='1' then
w.state := state_enter_inject;
w.injectmode := '1';
w.opcode := jtag_opcode;
elsif jtag_debug='0' then
w.flush:='1';
w.state := state_leave_inject;
end if;
when state_leave_inject =>
w.flush := '0';
w.injectmode:='0';
w.state := state_idle;
when state_enter_inject =>
-- w.state := state_flush;
w.state := state_inject;
when state_flush =>
w.flush := '1';
w.state := state_inject;
when state_inject =>
w.inject := '1';
w.flush := '0';
-- Here ?
injected <= '1';
w.state := state_step;
when state_step =>
injected <= '0';
w.inject := '0';
if dbg_in.valid='1' then
-- w.step := '1';
w.state := state_debug;
end if;
when others =>
end case;
end if;
if rising_edge(clk) then
dbgr <= w;
end if;
end process;
dbg_out.freeze <= dbgr.freeze;
--dbg_reset <= dbgr.reset;
dbg_out.inject <= dbgr.inject;
dbg_out.injectmode <= dbgr.injectmode;-- and dbg_ready;
dbg_out.step <= dbgr.step;
dbg_out.flush <= dbgr.flush;
dbg_out.opcode <= dbgr.opcode;
process(clk)
begin
if rising_edge(clk) then
dbg_reset <= jtag_ctrl_chain_in(3);
end if;
end process;
-- Synchronization stuff
process(jtag_inject, clk, injected, inject_q_in)
begin
if injected='1' then
inject_q <= '0';
inject_q_in <= '0';
else
if rising_edge(jtag_inject) then
inject_q_in <= '1';
--else
-- inject_q_in <= inject_q_in;
end if;
if rising_edge(clk) then
inject_q <= inject_q_in;
end if;
end if;
end process;
end behave;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
library board;
use board.zpuino_config.all;
use board.zpu_config_hyperion.all;
use board.zpupkg_hyperion.all;
use board.zpuinopkg.all;
entity zpuino_debug_core_hyperion is
port (
clk: in std_logic;
rst: in std_logic;
dbg_in: in zpu_dbg_out_type;
dbg_out: out zpu_dbg_in_type;
dbg_reset: out std_logic;
jtag_data_chain_out: out std_logic_vector(98 downto 0);
jtag_ctrl_chain_in: in std_logic_vector(11 downto 0)
);
end entity;
architecture behave of zpuino_debug_core_hyperion is
signal enter_ss: std_logic :='0';
signal step: std_logic := '0';
signal status_injection_ready: std_logic;
signal status_injectmode: std_logic;
type state_type is (
state_idle,
state_debug,
state_enter_inject,
state_flush,
state_inject,
state_leave_inject,
state_step
);
type dbgregs_type is record
state: state_type;
step: std_logic;
inject: std_logic;
freeze: std_logic;
injectmode: std_logic;
reset: std_logic;
flush: std_logic;
opcode: std_logic_vector(7 downto 0);
end record;
signal dbgr: dbgregs_type;
signal injected: std_logic;
signal inject_q_in: std_logic := '0';
signal inject_q: std_logic := '0';
alias jtag_debug: std_logic is jtag_ctrl_chain_in(0);
alias jtag_inject: std_logic is jtag_ctrl_chain_in(1);
alias jtag_step: std_logic is jtag_ctrl_chain_in(2);
alias jtag_reset: std_logic is jtag_ctrl_chain_in(3);
alias jtag_opcode: std_logic_vector(7 downto 0) is jtag_ctrl_chain_in(11 downto 4);
signal pc_i: std_logic_vector(wordSize-1 downto 0);
signal sp_i: std_logic_vector(wordSize-1 downto 0);
begin
pc_i(wordSize-1 downto dbg_in.pc'high+1) <= (others => '0');
pc_i(dbg_in.pc'high downto dbg_in.pc'low) <= dbg_in.pc;
sp_i(wordSize-1 downto dbg_in.sp'high+1) <= (others => '0');
sp_i(dbg_in.sp'high downto dbg_in.sp'low) <= dbg_in.sp;
sp_i(dbg_in.sp'low-1 downto 0) <= (others => '0');
-- jtag chain output
jtag_data_chain_out <=
dbg_in.idim &
sp_i &
dbg_in.stacka &
pc_i &
dbg_in.brk &
status_injection_ready
;
status_injection_ready <= '1' when dbgr.state = state_debug else '0';
process(clk, rst, dbgr, dbg_in.valid, jtag_debug, jtag_opcode,
inject_q, dbg_in.ready, dbg_in.pc, dbg_in.idim, jtag_ctrl_chain_in)
variable w: dbgregs_type;
begin
w := dbgr;
if rst='1' then
w.state := state_idle;
w.reset := '0';
w.flush := '0';
w.injectmode := '0';
w.inject := '0';
w.step := '0';
w.freeze := '0';
injected <= '0';
else
injected <= '0';
case dbgr.state is
when state_idle =>
w.freeze := '0';
--if jtag_debug='1' then
-- w.freeze := '1';
-- w.state := state_debug;
--end if;
if jtag_debug='1' then
--if dbg_ready='1' then
w.injectmode := '1';
--w.opcode := jtag_opcode;
-- end if;
-- Wait for pipeline to finish
if dbg_in.valid='0' and dbg_in.ready='1' then
--report "Enter PC " & hstr(dbg_pc) & " IDIM flag " & chr(dbg_idim) severity note;
w.state:=state_debug;
end if;
--end if;
end if;
when state_debug =>
w.step := '0';
if inject_q='1' then
w.state := state_enter_inject;
w.injectmode := '1';
w.opcode := jtag_opcode;
elsif jtag_debug='0' then
w.flush:='1';
w.state := state_leave_inject;
end if;
when state_leave_inject =>
w.flush := '0';
w.injectmode:='0';
w.state := state_idle;
when state_enter_inject =>
-- w.state := state_flush;
w.state := state_inject;
when state_flush =>
w.flush := '1';
w.state := state_inject;
when state_inject =>
w.inject := '1';
w.flush := '0';
-- Here ?
injected <= '1';
w.state := state_step;
when state_step =>
injected <= '0';
w.inject := '0';
if dbg_in.valid='1' then
-- w.step := '1';
w.state := state_debug;
end if;
when others =>
end case;
end if;
if rising_edge(clk) then
dbgr <= w;
end if;
end process;
dbg_out.freeze <= dbgr.freeze;
--dbg_reset <= dbgr.reset;
dbg_out.inject <= dbgr.inject;
dbg_out.injectmode <= dbgr.injectmode;-- and dbg_ready;
dbg_out.step <= dbgr.step;
dbg_out.flush <= dbgr.flush;
dbg_out.opcode <= dbgr.opcode;
process(clk)
begin
if rising_edge(clk) then
dbg_reset <= jtag_ctrl_chain_in(3);
end if;
end process;
-- Synchronization stuff
process(jtag_inject, clk, injected, inject_q_in)
begin
if injected='1' then
inject_q <= '0';
inject_q_in <= '0';
else
if rising_edge(jtag_inject) then
inject_q_in <= '1';
--else
-- inject_q_in <= inject_q_in;
end if;
if rising_edge(clk) then
inject_q <= inject_q_in;
end if;
end if;
end process;
end behave;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
library board;
use board.zpuino_config.all;
use board.zpu_config_hyperion.all;
use board.zpupkg_hyperion.all;
use board.zpuinopkg.all;
entity zpuino_debug_core_hyperion is
port (
clk: in std_logic;
rst: in std_logic;
dbg_in: in zpu_dbg_out_type;
dbg_out: out zpu_dbg_in_type;
dbg_reset: out std_logic;
jtag_data_chain_out: out std_logic_vector(98 downto 0);
jtag_ctrl_chain_in: in std_logic_vector(11 downto 0)
);
end entity;
architecture behave of zpuino_debug_core_hyperion is
signal enter_ss: std_logic :='0';
signal step: std_logic := '0';
signal status_injection_ready: std_logic;
signal status_injectmode: std_logic;
type state_type is (
state_idle,
state_debug,
state_enter_inject,
state_flush,
state_inject,
state_leave_inject,
state_step
);
type dbgregs_type is record
state: state_type;
step: std_logic;
inject: std_logic;
freeze: std_logic;
injectmode: std_logic;
reset: std_logic;
flush: std_logic;
opcode: std_logic_vector(7 downto 0);
end record;
signal dbgr: dbgregs_type;
signal injected: std_logic;
signal inject_q_in: std_logic := '0';
signal inject_q: std_logic := '0';
alias jtag_debug: std_logic is jtag_ctrl_chain_in(0);
alias jtag_inject: std_logic is jtag_ctrl_chain_in(1);
alias jtag_step: std_logic is jtag_ctrl_chain_in(2);
alias jtag_reset: std_logic is jtag_ctrl_chain_in(3);
alias jtag_opcode: std_logic_vector(7 downto 0) is jtag_ctrl_chain_in(11 downto 4);
signal pc_i: std_logic_vector(wordSize-1 downto 0);
signal sp_i: std_logic_vector(wordSize-1 downto 0);
begin
pc_i(wordSize-1 downto dbg_in.pc'high+1) <= (others => '0');
pc_i(dbg_in.pc'high downto dbg_in.pc'low) <= dbg_in.pc;
sp_i(wordSize-1 downto dbg_in.sp'high+1) <= (others => '0');
sp_i(dbg_in.sp'high downto dbg_in.sp'low) <= dbg_in.sp;
sp_i(dbg_in.sp'low-1 downto 0) <= (others => '0');
-- jtag chain output
jtag_data_chain_out <=
dbg_in.idim &
sp_i &
dbg_in.stacka &
pc_i &
dbg_in.brk &
status_injection_ready
;
status_injection_ready <= '1' when dbgr.state = state_debug else '0';
process(clk, rst, dbgr, dbg_in.valid, jtag_debug, jtag_opcode,
inject_q, dbg_in.ready, dbg_in.pc, dbg_in.idim, jtag_ctrl_chain_in)
variable w: dbgregs_type;
begin
w := dbgr;
if rst='1' then
w.state := state_idle;
w.reset := '0';
w.flush := '0';
w.injectmode := '0';
w.inject := '0';
w.step := '0';
w.freeze := '0';
injected <= '0';
else
injected <= '0';
case dbgr.state is
when state_idle =>
w.freeze := '0';
--if jtag_debug='1' then
-- w.freeze := '1';
-- w.state := state_debug;
--end if;
if jtag_debug='1' then
--if dbg_ready='1' then
w.injectmode := '1';
--w.opcode := jtag_opcode;
-- end if;
-- Wait for pipeline to finish
if dbg_in.valid='0' and dbg_in.ready='1' then
--report "Enter PC " & hstr(dbg_pc) & " IDIM flag " & chr(dbg_idim) severity note;
w.state:=state_debug;
end if;
--end if;
end if;
when state_debug =>
w.step := '0';
if inject_q='1' then
w.state := state_enter_inject;
w.injectmode := '1';
w.opcode := jtag_opcode;
elsif jtag_debug='0' then
w.flush:='1';
w.state := state_leave_inject;
end if;
when state_leave_inject =>
w.flush := '0';
w.injectmode:='0';
w.state := state_idle;
when state_enter_inject =>
-- w.state := state_flush;
w.state := state_inject;
when state_flush =>
w.flush := '1';
w.state := state_inject;
when state_inject =>
w.inject := '1';
w.flush := '0';
-- Here ?
injected <= '1';
w.state := state_step;
when state_step =>
injected <= '0';
w.inject := '0';
if dbg_in.valid='1' then
-- w.step := '1';
w.state := state_debug;
end if;
when others =>
end case;
end if;
if rising_edge(clk) then
dbgr <= w;
end if;
end process;
dbg_out.freeze <= dbgr.freeze;
--dbg_reset <= dbgr.reset;
dbg_out.inject <= dbgr.inject;
dbg_out.injectmode <= dbgr.injectmode;-- and dbg_ready;
dbg_out.step <= dbgr.step;
dbg_out.flush <= dbgr.flush;
dbg_out.opcode <= dbgr.opcode;
process(clk)
begin
if rising_edge(clk) then
dbg_reset <= jtag_ctrl_chain_in(3);
end if;
end process;
-- Synchronization stuff
process(jtag_inject, clk, injected, inject_q_in)
begin
if injected='1' then
inject_q <= '0';
inject_q_in <= '0';
else
if rising_edge(jtag_inject) then
inject_q_in <= '1';
--else
-- inject_q_in <= inject_q_in;
end if;
if rising_edge(clk) then
inject_q <= inject_q_in;
end if;
end if;
end process;
end behave;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
library board;
use board.zpuino_config.all;
use board.zpu_config_hyperion.all;
use board.zpupkg_hyperion.all;
use board.zpuinopkg.all;
entity zpuino_debug_core_hyperion is
port (
clk: in std_logic;
rst: in std_logic;
dbg_in: in zpu_dbg_out_type;
dbg_out: out zpu_dbg_in_type;
dbg_reset: out std_logic;
jtag_data_chain_out: out std_logic_vector(98 downto 0);
jtag_ctrl_chain_in: in std_logic_vector(11 downto 0)
);
end entity;
architecture behave of zpuino_debug_core_hyperion is
signal enter_ss: std_logic :='0';
signal step: std_logic := '0';
signal status_injection_ready: std_logic;
signal status_injectmode: std_logic;
type state_type is (
state_idle,
state_debug,
state_enter_inject,
state_flush,
state_inject,
state_leave_inject,
state_step
);
type dbgregs_type is record
state: state_type;
step: std_logic;
inject: std_logic;
freeze: std_logic;
injectmode: std_logic;
reset: std_logic;
flush: std_logic;
opcode: std_logic_vector(7 downto 0);
end record;
signal dbgr: dbgregs_type;
signal injected: std_logic;
signal inject_q_in: std_logic := '0';
signal inject_q: std_logic := '0';
alias jtag_debug: std_logic is jtag_ctrl_chain_in(0);
alias jtag_inject: std_logic is jtag_ctrl_chain_in(1);
alias jtag_step: std_logic is jtag_ctrl_chain_in(2);
alias jtag_reset: std_logic is jtag_ctrl_chain_in(3);
alias jtag_opcode: std_logic_vector(7 downto 0) is jtag_ctrl_chain_in(11 downto 4);
signal pc_i: std_logic_vector(wordSize-1 downto 0);
signal sp_i: std_logic_vector(wordSize-1 downto 0);
begin
pc_i(wordSize-1 downto dbg_in.pc'high+1) <= (others => '0');
pc_i(dbg_in.pc'high downto dbg_in.pc'low) <= dbg_in.pc;
sp_i(wordSize-1 downto dbg_in.sp'high+1) <= (others => '0');
sp_i(dbg_in.sp'high downto dbg_in.sp'low) <= dbg_in.sp;
sp_i(dbg_in.sp'low-1 downto 0) <= (others => '0');
-- jtag chain output
jtag_data_chain_out <=
dbg_in.idim &
sp_i &
dbg_in.stacka &
pc_i &
dbg_in.brk &
status_injection_ready
;
status_injection_ready <= '1' when dbgr.state = state_debug else '0';
process(clk, rst, dbgr, dbg_in.valid, jtag_debug, jtag_opcode,
inject_q, dbg_in.ready, dbg_in.pc, dbg_in.idim, jtag_ctrl_chain_in)
variable w: dbgregs_type;
begin
w := dbgr;
if rst='1' then
w.state := state_idle;
w.reset := '0';
w.flush := '0';
w.injectmode := '0';
w.inject := '0';
w.step := '0';
w.freeze := '0';
injected <= '0';
else
injected <= '0';
case dbgr.state is
when state_idle =>
w.freeze := '0';
--if jtag_debug='1' then
-- w.freeze := '1';
-- w.state := state_debug;
--end if;
if jtag_debug='1' then
--if dbg_ready='1' then
w.injectmode := '1';
--w.opcode := jtag_opcode;
-- end if;
-- Wait for pipeline to finish
if dbg_in.valid='0' and dbg_in.ready='1' then
--report "Enter PC " & hstr(dbg_pc) & " IDIM flag " & chr(dbg_idim) severity note;
w.state:=state_debug;
end if;
--end if;
end if;
when state_debug =>
w.step := '0';
if inject_q='1' then
w.state := state_enter_inject;
w.injectmode := '1';
w.opcode := jtag_opcode;
elsif jtag_debug='0' then
w.flush:='1';
w.state := state_leave_inject;
end if;
when state_leave_inject =>
w.flush := '0';
w.injectmode:='0';
w.state := state_idle;
when state_enter_inject =>
-- w.state := state_flush;
w.state := state_inject;
when state_flush =>
w.flush := '1';
w.state := state_inject;
when state_inject =>
w.inject := '1';
w.flush := '0';
-- Here ?
injected <= '1';
w.state := state_step;
when state_step =>
injected <= '0';
w.inject := '0';
if dbg_in.valid='1' then
-- w.step := '1';
w.state := state_debug;
end if;
when others =>
end case;
end if;
if rising_edge(clk) then
dbgr <= w;
end if;
end process;
dbg_out.freeze <= dbgr.freeze;
--dbg_reset <= dbgr.reset;
dbg_out.inject <= dbgr.inject;
dbg_out.injectmode <= dbgr.injectmode;-- and dbg_ready;
dbg_out.step <= dbgr.step;
dbg_out.flush <= dbgr.flush;
dbg_out.opcode <= dbgr.opcode;
process(clk)
begin
if rising_edge(clk) then
dbg_reset <= jtag_ctrl_chain_in(3);
end if;
end process;
-- Synchronization stuff
process(jtag_inject, clk, injected, inject_q_in)
begin
if injected='1' then
inject_q <= '0';
inject_q_in <= '0';
else
if rising_edge(jtag_inject) then
inject_q_in <= '1';
--else
-- inject_q_in <= inject_q_in;
end if;
if rising_edge(clk) then
inject_q <= inject_q_in;
end if;
end if;
end process;
end behave;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
library board;
use board.zpuino_config.all;
use board.zpu_config_hyperion.all;
use board.zpupkg_hyperion.all;
use board.zpuinopkg.all;
entity zpuino_debug_core_hyperion is
port (
clk: in std_logic;
rst: in std_logic;
dbg_in: in zpu_dbg_out_type;
dbg_out: out zpu_dbg_in_type;
dbg_reset: out std_logic;
jtag_data_chain_out: out std_logic_vector(98 downto 0);
jtag_ctrl_chain_in: in std_logic_vector(11 downto 0)
);
end entity;
architecture behave of zpuino_debug_core_hyperion is
signal enter_ss: std_logic :='0';
signal step: std_logic := '0';
signal status_injection_ready: std_logic;
signal status_injectmode: std_logic;
type state_type is (
state_idle,
state_debug,
state_enter_inject,
state_flush,
state_inject,
state_leave_inject,
state_step
);
type dbgregs_type is record
state: state_type;
step: std_logic;
inject: std_logic;
freeze: std_logic;
injectmode: std_logic;
reset: std_logic;
flush: std_logic;
opcode: std_logic_vector(7 downto 0);
end record;
signal dbgr: dbgregs_type;
signal injected: std_logic;
signal inject_q_in: std_logic := '0';
signal inject_q: std_logic := '0';
alias jtag_debug: std_logic is jtag_ctrl_chain_in(0);
alias jtag_inject: std_logic is jtag_ctrl_chain_in(1);
alias jtag_step: std_logic is jtag_ctrl_chain_in(2);
alias jtag_reset: std_logic is jtag_ctrl_chain_in(3);
alias jtag_opcode: std_logic_vector(7 downto 0) is jtag_ctrl_chain_in(11 downto 4);
signal pc_i: std_logic_vector(wordSize-1 downto 0);
signal sp_i: std_logic_vector(wordSize-1 downto 0);
begin
pc_i(wordSize-1 downto dbg_in.pc'high+1) <= (others => '0');
pc_i(dbg_in.pc'high downto dbg_in.pc'low) <= dbg_in.pc;
sp_i(wordSize-1 downto dbg_in.sp'high+1) <= (others => '0');
sp_i(dbg_in.sp'high downto dbg_in.sp'low) <= dbg_in.sp;
sp_i(dbg_in.sp'low-1 downto 0) <= (others => '0');
-- jtag chain output
jtag_data_chain_out <=
dbg_in.idim &
sp_i &
dbg_in.stacka &
pc_i &
dbg_in.brk &
status_injection_ready
;
status_injection_ready <= '1' when dbgr.state = state_debug else '0';
process(clk, rst, dbgr, dbg_in.valid, jtag_debug, jtag_opcode,
inject_q, dbg_in.ready, dbg_in.pc, dbg_in.idim, jtag_ctrl_chain_in)
variable w: dbgregs_type;
begin
w := dbgr;
if rst='1' then
w.state := state_idle;
w.reset := '0';
w.flush := '0';
w.injectmode := '0';
w.inject := '0';
w.step := '0';
w.freeze := '0';
injected <= '0';
else
injected <= '0';
case dbgr.state is
when state_idle =>
w.freeze := '0';
--if jtag_debug='1' then
-- w.freeze := '1';
-- w.state := state_debug;
--end if;
if jtag_debug='1' then
--if dbg_ready='1' then
w.injectmode := '1';
--w.opcode := jtag_opcode;
-- end if;
-- Wait for pipeline to finish
if dbg_in.valid='0' and dbg_in.ready='1' then
--report "Enter PC " & hstr(dbg_pc) & " IDIM flag " & chr(dbg_idim) severity note;
w.state:=state_debug;
end if;
--end if;
end if;
when state_debug =>
w.step := '0';
if inject_q='1' then
w.state := state_enter_inject;
w.injectmode := '1';
w.opcode := jtag_opcode;
elsif jtag_debug='0' then
w.flush:='1';
w.state := state_leave_inject;
end if;
when state_leave_inject =>
w.flush := '0';
w.injectmode:='0';
w.state := state_idle;
when state_enter_inject =>
-- w.state := state_flush;
w.state := state_inject;
when state_flush =>
w.flush := '1';
w.state := state_inject;
when state_inject =>
w.inject := '1';
w.flush := '0';
-- Here ?
injected <= '1';
w.state := state_step;
when state_step =>
injected <= '0';
w.inject := '0';
if dbg_in.valid='1' then
-- w.step := '1';
w.state := state_debug;
end if;
when others =>
end case;
end if;
if rising_edge(clk) then
dbgr <= w;
end if;
end process;
dbg_out.freeze <= dbgr.freeze;
--dbg_reset <= dbgr.reset;
dbg_out.inject <= dbgr.inject;
dbg_out.injectmode <= dbgr.injectmode;-- and dbg_ready;
dbg_out.step <= dbgr.step;
dbg_out.flush <= dbgr.flush;
dbg_out.opcode <= dbgr.opcode;
process(clk)
begin
if rising_edge(clk) then
dbg_reset <= jtag_ctrl_chain_in(3);
end if;
end process;
-- Synchronization stuff
process(jtag_inject, clk, injected, inject_q_in)
begin
if injected='1' then
inject_q <= '0';
inject_q_in <= '0';
else
if rising_edge(jtag_inject) then
inject_q_in <= '1';
--else
-- inject_q_in <= inject_q_in;
end if;
if rising_edge(clk) then
inject_q <= inject_q_in;
end if;
end if;
end process;
end behave;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
library board;
use board.zpuino_config.all;
use board.zpu_config_hyperion.all;
use board.zpupkg_hyperion.all;
use board.zpuinopkg.all;
entity zpuino_debug_core_hyperion is
port (
clk: in std_logic;
rst: in std_logic;
dbg_in: in zpu_dbg_out_type;
dbg_out: out zpu_dbg_in_type;
dbg_reset: out std_logic;
jtag_data_chain_out: out std_logic_vector(98 downto 0);
jtag_ctrl_chain_in: in std_logic_vector(11 downto 0)
);
end entity;
architecture behave of zpuino_debug_core_hyperion is
signal enter_ss: std_logic :='0';
signal step: std_logic := '0';
signal status_injection_ready: std_logic;
signal status_injectmode: std_logic;
type state_type is (
state_idle,
state_debug,
state_enter_inject,
state_flush,
state_inject,
state_leave_inject,
state_step
);
type dbgregs_type is record
state: state_type;
step: std_logic;
inject: std_logic;
freeze: std_logic;
injectmode: std_logic;
reset: std_logic;
flush: std_logic;
opcode: std_logic_vector(7 downto 0);
end record;
signal dbgr: dbgregs_type;
signal injected: std_logic;
signal inject_q_in: std_logic := '0';
signal inject_q: std_logic := '0';
alias jtag_debug: std_logic is jtag_ctrl_chain_in(0);
alias jtag_inject: std_logic is jtag_ctrl_chain_in(1);
alias jtag_step: std_logic is jtag_ctrl_chain_in(2);
alias jtag_reset: std_logic is jtag_ctrl_chain_in(3);
alias jtag_opcode: std_logic_vector(7 downto 0) is jtag_ctrl_chain_in(11 downto 4);
signal pc_i: std_logic_vector(wordSize-1 downto 0);
signal sp_i: std_logic_vector(wordSize-1 downto 0);
begin
pc_i(wordSize-1 downto dbg_in.pc'high+1) <= (others => '0');
pc_i(dbg_in.pc'high downto dbg_in.pc'low) <= dbg_in.pc;
sp_i(wordSize-1 downto dbg_in.sp'high+1) <= (others => '0');
sp_i(dbg_in.sp'high downto dbg_in.sp'low) <= dbg_in.sp;
sp_i(dbg_in.sp'low-1 downto 0) <= (others => '0');
-- jtag chain output
jtag_data_chain_out <=
dbg_in.idim &
sp_i &
dbg_in.stacka &
pc_i &
dbg_in.brk &
status_injection_ready
;
status_injection_ready <= '1' when dbgr.state = state_debug else '0';
process(clk, rst, dbgr, dbg_in.valid, jtag_debug, jtag_opcode,
inject_q, dbg_in.ready, dbg_in.pc, dbg_in.idim, jtag_ctrl_chain_in)
variable w: dbgregs_type;
begin
w := dbgr;
if rst='1' then
w.state := state_idle;
w.reset := '0';
w.flush := '0';
w.injectmode := '0';
w.inject := '0';
w.step := '0';
w.freeze := '0';
injected <= '0';
else
injected <= '0';
case dbgr.state is
when state_idle =>
w.freeze := '0';
--if jtag_debug='1' then
-- w.freeze := '1';
-- w.state := state_debug;
--end if;
if jtag_debug='1' then
--if dbg_ready='1' then
w.injectmode := '1';
--w.opcode := jtag_opcode;
-- end if;
-- Wait for pipeline to finish
if dbg_in.valid='0' and dbg_in.ready='1' then
--report "Enter PC " & hstr(dbg_pc) & " IDIM flag " & chr(dbg_idim) severity note;
w.state:=state_debug;
end if;
--end if;
end if;
when state_debug =>
w.step := '0';
if inject_q='1' then
w.state := state_enter_inject;
w.injectmode := '1';
w.opcode := jtag_opcode;
elsif jtag_debug='0' then
w.flush:='1';
w.state := state_leave_inject;
end if;
when state_leave_inject =>
w.flush := '0';
w.injectmode:='0';
w.state := state_idle;
when state_enter_inject =>
-- w.state := state_flush;
w.state := state_inject;
when state_flush =>
w.flush := '1';
w.state := state_inject;
when state_inject =>
w.inject := '1';
w.flush := '0';
-- Here ?
injected <= '1';
w.state := state_step;
when state_step =>
injected <= '0';
w.inject := '0';
if dbg_in.valid='1' then
-- w.step := '1';
w.state := state_debug;
end if;
when others =>
end case;
end if;
if rising_edge(clk) then
dbgr <= w;
end if;
end process;
dbg_out.freeze <= dbgr.freeze;
--dbg_reset <= dbgr.reset;
dbg_out.inject <= dbgr.inject;
dbg_out.injectmode <= dbgr.injectmode;-- and dbg_ready;
dbg_out.step <= dbgr.step;
dbg_out.flush <= dbgr.flush;
dbg_out.opcode <= dbgr.opcode;
process(clk)
begin
if rising_edge(clk) then
dbg_reset <= jtag_ctrl_chain_in(3);
end if;
end process;
-- Synchronization stuff
process(jtag_inject, clk, injected, inject_q_in)
begin
if injected='1' then
inject_q <= '0';
inject_q_in <= '0';
else
if rising_edge(jtag_inject) then
inject_q_in <= '1';
--else
-- inject_q_in <= inject_q_in;
end if;
if rising_edge(clk) then
inject_q <= inject_q_in;
end if;
end if;
end process;
end behave;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
library board;
use board.zpuino_config.all;
use board.zpu_config_hyperion.all;
use board.zpupkg_hyperion.all;
use board.zpuinopkg.all;
entity zpuino_debug_core_hyperion is
port (
clk: in std_logic;
rst: in std_logic;
dbg_in: in zpu_dbg_out_type;
dbg_out: out zpu_dbg_in_type;
dbg_reset: out std_logic;
jtag_data_chain_out: out std_logic_vector(98 downto 0);
jtag_ctrl_chain_in: in std_logic_vector(11 downto 0)
);
end entity;
architecture behave of zpuino_debug_core_hyperion is
signal enter_ss: std_logic :='0';
signal step: std_logic := '0';
signal status_injection_ready: std_logic;
signal status_injectmode: std_logic;
type state_type is (
state_idle,
state_debug,
state_enter_inject,
state_flush,
state_inject,
state_leave_inject,
state_step
);
type dbgregs_type is record
state: state_type;
step: std_logic;
inject: std_logic;
freeze: std_logic;
injectmode: std_logic;
reset: std_logic;
flush: std_logic;
opcode: std_logic_vector(7 downto 0);
end record;
signal dbgr: dbgregs_type;
signal injected: std_logic;
signal inject_q_in: std_logic := '0';
signal inject_q: std_logic := '0';
alias jtag_debug: std_logic is jtag_ctrl_chain_in(0);
alias jtag_inject: std_logic is jtag_ctrl_chain_in(1);
alias jtag_step: std_logic is jtag_ctrl_chain_in(2);
alias jtag_reset: std_logic is jtag_ctrl_chain_in(3);
alias jtag_opcode: std_logic_vector(7 downto 0) is jtag_ctrl_chain_in(11 downto 4);
signal pc_i: std_logic_vector(wordSize-1 downto 0);
signal sp_i: std_logic_vector(wordSize-1 downto 0);
begin
pc_i(wordSize-1 downto dbg_in.pc'high+1) <= (others => '0');
pc_i(dbg_in.pc'high downto dbg_in.pc'low) <= dbg_in.pc;
sp_i(wordSize-1 downto dbg_in.sp'high+1) <= (others => '0');
sp_i(dbg_in.sp'high downto dbg_in.sp'low) <= dbg_in.sp;
sp_i(dbg_in.sp'low-1 downto 0) <= (others => '0');
-- jtag chain output
jtag_data_chain_out <=
dbg_in.idim &
sp_i &
dbg_in.stacka &
pc_i &
dbg_in.brk &
status_injection_ready
;
status_injection_ready <= '1' when dbgr.state = state_debug else '0';
process(clk, rst, dbgr, dbg_in.valid, jtag_debug, jtag_opcode,
inject_q, dbg_in.ready, dbg_in.pc, dbg_in.idim, jtag_ctrl_chain_in)
variable w: dbgregs_type;
begin
w := dbgr;
if rst='1' then
w.state := state_idle;
w.reset := '0';
w.flush := '0';
w.injectmode := '0';
w.inject := '0';
w.step := '0';
w.freeze := '0';
injected <= '0';
else
injected <= '0';
case dbgr.state is
when state_idle =>
w.freeze := '0';
--if jtag_debug='1' then
-- w.freeze := '1';
-- w.state := state_debug;
--end if;
if jtag_debug='1' then
--if dbg_ready='1' then
w.injectmode := '1';
--w.opcode := jtag_opcode;
-- end if;
-- Wait for pipeline to finish
if dbg_in.valid='0' and dbg_in.ready='1' then
--report "Enter PC " & hstr(dbg_pc) & " IDIM flag " & chr(dbg_idim) severity note;
w.state:=state_debug;
end if;
--end if;
end if;
when state_debug =>
w.step := '0';
if inject_q='1' then
w.state := state_enter_inject;
w.injectmode := '1';
w.opcode := jtag_opcode;
elsif jtag_debug='0' then
w.flush:='1';
w.state := state_leave_inject;
end if;
when state_leave_inject =>
w.flush := '0';
w.injectmode:='0';
w.state := state_idle;
when state_enter_inject =>
-- w.state := state_flush;
w.state := state_inject;
when state_flush =>
w.flush := '1';
w.state := state_inject;
when state_inject =>
w.inject := '1';
w.flush := '0';
-- Here ?
injected <= '1';
w.state := state_step;
when state_step =>
injected <= '0';
w.inject := '0';
if dbg_in.valid='1' then
-- w.step := '1';
w.state := state_debug;
end if;
when others =>
end case;
end if;
if rising_edge(clk) then
dbgr <= w;
end if;
end process;
dbg_out.freeze <= dbgr.freeze;
--dbg_reset <= dbgr.reset;
dbg_out.inject <= dbgr.inject;
dbg_out.injectmode <= dbgr.injectmode;-- and dbg_ready;
dbg_out.step <= dbgr.step;
dbg_out.flush <= dbgr.flush;
dbg_out.opcode <= dbgr.opcode;
process(clk)
begin
if rising_edge(clk) then
dbg_reset <= jtag_ctrl_chain_in(3);
end if;
end process;
-- Synchronization stuff
process(jtag_inject, clk, injected, inject_q_in)
begin
if injected='1' then
inject_q <= '0';
inject_q_in <= '0';
else
if rising_edge(jtag_inject) then
inject_q_in <= '1';
--else
-- inject_q_in <= inject_q_in;
end if;
if rising_edge(clk) then
inject_q <= inject_q_in;
end if;
end if;
end process;
end behave;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
library board;
use board.zpuino_config.all;
use board.zpu_config_hyperion.all;
use board.zpupkg_hyperion.all;
use board.zpuinopkg.all;
entity zpuino_debug_core_hyperion is
port (
clk: in std_logic;
rst: in std_logic;
dbg_in: in zpu_dbg_out_type;
dbg_out: out zpu_dbg_in_type;
dbg_reset: out std_logic;
jtag_data_chain_out: out std_logic_vector(98 downto 0);
jtag_ctrl_chain_in: in std_logic_vector(11 downto 0)
);
end entity;
architecture behave of zpuino_debug_core_hyperion is
signal enter_ss: std_logic :='0';
signal step: std_logic := '0';
signal status_injection_ready: std_logic;
signal status_injectmode: std_logic;
type state_type is (
state_idle,
state_debug,
state_enter_inject,
state_flush,
state_inject,
state_leave_inject,
state_step
);
type dbgregs_type is record
state: state_type;
step: std_logic;
inject: std_logic;
freeze: std_logic;
injectmode: std_logic;
reset: std_logic;
flush: std_logic;
opcode: std_logic_vector(7 downto 0);
end record;
signal dbgr: dbgregs_type;
signal injected: std_logic;
signal inject_q_in: std_logic := '0';
signal inject_q: std_logic := '0';
alias jtag_debug: std_logic is jtag_ctrl_chain_in(0);
alias jtag_inject: std_logic is jtag_ctrl_chain_in(1);
alias jtag_step: std_logic is jtag_ctrl_chain_in(2);
alias jtag_reset: std_logic is jtag_ctrl_chain_in(3);
alias jtag_opcode: std_logic_vector(7 downto 0) is jtag_ctrl_chain_in(11 downto 4);
signal pc_i: std_logic_vector(wordSize-1 downto 0);
signal sp_i: std_logic_vector(wordSize-1 downto 0);
begin
pc_i(wordSize-1 downto dbg_in.pc'high+1) <= (others => '0');
pc_i(dbg_in.pc'high downto dbg_in.pc'low) <= dbg_in.pc;
sp_i(wordSize-1 downto dbg_in.sp'high+1) <= (others => '0');
sp_i(dbg_in.sp'high downto dbg_in.sp'low) <= dbg_in.sp;
sp_i(dbg_in.sp'low-1 downto 0) <= (others => '0');
-- jtag chain output
jtag_data_chain_out <=
dbg_in.idim &
sp_i &
dbg_in.stacka &
pc_i &
dbg_in.brk &
status_injection_ready
;
status_injection_ready <= '1' when dbgr.state = state_debug else '0';
process(clk, rst, dbgr, dbg_in.valid, jtag_debug, jtag_opcode,
inject_q, dbg_in.ready, dbg_in.pc, dbg_in.idim, jtag_ctrl_chain_in)
variable w: dbgregs_type;
begin
w := dbgr;
if rst='1' then
w.state := state_idle;
w.reset := '0';
w.flush := '0';
w.injectmode := '0';
w.inject := '0';
w.step := '0';
w.freeze := '0';
injected <= '0';
else
injected <= '0';
case dbgr.state is
when state_idle =>
w.freeze := '0';
--if jtag_debug='1' then
-- w.freeze := '1';
-- w.state := state_debug;
--end if;
if jtag_debug='1' then
--if dbg_ready='1' then
w.injectmode := '1';
--w.opcode := jtag_opcode;
-- end if;
-- Wait for pipeline to finish
if dbg_in.valid='0' and dbg_in.ready='1' then
--report "Enter PC " & hstr(dbg_pc) & " IDIM flag " & chr(dbg_idim) severity note;
w.state:=state_debug;
end if;
--end if;
end if;
when state_debug =>
w.step := '0';
if inject_q='1' then
w.state := state_enter_inject;
w.injectmode := '1';
w.opcode := jtag_opcode;
elsif jtag_debug='0' then
w.flush:='1';
w.state := state_leave_inject;
end if;
when state_leave_inject =>
w.flush := '0';
w.injectmode:='0';
w.state := state_idle;
when state_enter_inject =>
-- w.state := state_flush;
w.state := state_inject;
when state_flush =>
w.flush := '1';
w.state := state_inject;
when state_inject =>
w.inject := '1';
w.flush := '0';
-- Here ?
injected <= '1';
w.state := state_step;
when state_step =>
injected <= '0';
w.inject := '0';
if dbg_in.valid='1' then
-- w.step := '1';
w.state := state_debug;
end if;
when others =>
end case;
end if;
if rising_edge(clk) then
dbgr <= w;
end if;
end process;
dbg_out.freeze <= dbgr.freeze;
--dbg_reset <= dbgr.reset;
dbg_out.inject <= dbgr.inject;
dbg_out.injectmode <= dbgr.injectmode;-- and dbg_ready;
dbg_out.step <= dbgr.step;
dbg_out.flush <= dbgr.flush;
dbg_out.opcode <= dbgr.opcode;
process(clk)
begin
if rising_edge(clk) then
dbg_reset <= jtag_ctrl_chain_in(3);
end if;
end process;
-- Synchronization stuff
process(jtag_inject, clk, injected, inject_q_in)
begin
if injected='1' then
inject_q <= '0';
inject_q_in <= '0';
else
if rising_edge(jtag_inject) then
inject_q_in <= '1';
--else
-- inject_q_in <= inject_q_in;
end if;
if rising_edge(clk) then
inject_q <= inject_q_in;
end if;
end if;
end process;
end behave;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
library board;
use board.zpuino_config.all;
use board.zpu_config_hyperion.all;
use board.zpupkg_hyperion.all;
use board.zpuinopkg.all;
entity zpuino_debug_core_hyperion is
port (
clk: in std_logic;
rst: in std_logic;
dbg_in: in zpu_dbg_out_type;
dbg_out: out zpu_dbg_in_type;
dbg_reset: out std_logic;
jtag_data_chain_out: out std_logic_vector(98 downto 0);
jtag_ctrl_chain_in: in std_logic_vector(11 downto 0)
);
end entity;
architecture behave of zpuino_debug_core_hyperion is
signal enter_ss: std_logic :='0';
signal step: std_logic := '0';
signal status_injection_ready: std_logic;
signal status_injectmode: std_logic;
type state_type is (
state_idle,
state_debug,
state_enter_inject,
state_flush,
state_inject,
state_leave_inject,
state_step
);
type dbgregs_type is record
state: state_type;
step: std_logic;
inject: std_logic;
freeze: std_logic;
injectmode: std_logic;
reset: std_logic;
flush: std_logic;
opcode: std_logic_vector(7 downto 0);
end record;
signal dbgr: dbgregs_type;
signal injected: std_logic;
signal inject_q_in: std_logic := '0';
signal inject_q: std_logic := '0';
alias jtag_debug: std_logic is jtag_ctrl_chain_in(0);
alias jtag_inject: std_logic is jtag_ctrl_chain_in(1);
alias jtag_step: std_logic is jtag_ctrl_chain_in(2);
alias jtag_reset: std_logic is jtag_ctrl_chain_in(3);
alias jtag_opcode: std_logic_vector(7 downto 0) is jtag_ctrl_chain_in(11 downto 4);
signal pc_i: std_logic_vector(wordSize-1 downto 0);
signal sp_i: std_logic_vector(wordSize-1 downto 0);
begin
pc_i(wordSize-1 downto dbg_in.pc'high+1) <= (others => '0');
pc_i(dbg_in.pc'high downto dbg_in.pc'low) <= dbg_in.pc;
sp_i(wordSize-1 downto dbg_in.sp'high+1) <= (others => '0');
sp_i(dbg_in.sp'high downto dbg_in.sp'low) <= dbg_in.sp;
sp_i(dbg_in.sp'low-1 downto 0) <= (others => '0');
-- jtag chain output
jtag_data_chain_out <=
dbg_in.idim &
sp_i &
dbg_in.stacka &
pc_i &
dbg_in.brk &
status_injection_ready
;
status_injection_ready <= '1' when dbgr.state = state_debug else '0';
process(clk, rst, dbgr, dbg_in.valid, jtag_debug, jtag_opcode,
inject_q, dbg_in.ready, dbg_in.pc, dbg_in.idim, jtag_ctrl_chain_in)
variable w: dbgregs_type;
begin
w := dbgr;
if rst='1' then
w.state := state_idle;
w.reset := '0';
w.flush := '0';
w.injectmode := '0';
w.inject := '0';
w.step := '0';
w.freeze := '0';
injected <= '0';
else
injected <= '0';
case dbgr.state is
when state_idle =>
w.freeze := '0';
--if jtag_debug='1' then
-- w.freeze := '1';
-- w.state := state_debug;
--end if;
if jtag_debug='1' then
--if dbg_ready='1' then
w.injectmode := '1';
--w.opcode := jtag_opcode;
-- end if;
-- Wait for pipeline to finish
if dbg_in.valid='0' and dbg_in.ready='1' then
--report "Enter PC " & hstr(dbg_pc) & " IDIM flag " & chr(dbg_idim) severity note;
w.state:=state_debug;
end if;
--end if;
end if;
when state_debug =>
w.step := '0';
if inject_q='1' then
w.state := state_enter_inject;
w.injectmode := '1';
w.opcode := jtag_opcode;
elsif jtag_debug='0' then
w.flush:='1';
w.state := state_leave_inject;
end if;
when state_leave_inject =>
w.flush := '0';
w.injectmode:='0';
w.state := state_idle;
when state_enter_inject =>
-- w.state := state_flush;
w.state := state_inject;
when state_flush =>
w.flush := '1';
w.state := state_inject;
when state_inject =>
w.inject := '1';
w.flush := '0';
-- Here ?
injected <= '1';
w.state := state_step;
when state_step =>
injected <= '0';
w.inject := '0';
if dbg_in.valid='1' then
-- w.step := '1';
w.state := state_debug;
end if;
when others =>
end case;
end if;
if rising_edge(clk) then
dbgr <= w;
end if;
end process;
dbg_out.freeze <= dbgr.freeze;
--dbg_reset <= dbgr.reset;
dbg_out.inject <= dbgr.inject;
dbg_out.injectmode <= dbgr.injectmode;-- and dbg_ready;
dbg_out.step <= dbgr.step;
dbg_out.flush <= dbgr.flush;
dbg_out.opcode <= dbgr.opcode;
process(clk)
begin
if rising_edge(clk) then
dbg_reset <= jtag_ctrl_chain_in(3);
end if;
end process;
-- Synchronization stuff
process(jtag_inject, clk, injected, inject_q_in)
begin
if injected='1' then
inject_q <= '0';
inject_q_in <= '0';
else
if rising_edge(jtag_inject) then
inject_q_in <= '1';
--else
-- inject_q_in <= inject_q_in;
end if;
if rising_edge(clk) then
inject_q <= inject_q_in;
end if;
end if;
end process;
end behave;
|
--
-- Package File Template
--
-- Purpose: This package defines supplemental types, subtypes,
-- constants, and functions
--
-- To use any of the example code shown below, uncomment the lines and modify as necessary
--
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.numeric_std.all;
package Common is
-- type <new_type> is
-- record
-- <type_name> : std_logic_vector( 7 downto 0);
-- <type_name> : std_logic;
-- end record;
--
-- Declare constants
--
-- constant <constant_name> : time := <time_unit> ns;
-- constant <constant_name> : integer := <value;
--
-- Declare functions and procedure
--
-- function <function_name> (signal <signal_name> : in <type_declaration>) return <type_declaration>;
-- procedure <procedure_name> (<type_declaration> <constant_name> : in <type_declaration>);
--
subtype Int16 is std_logic_vector(15 downto 0);
subtype Int15 is std_logic_vector(14 downto 0);
subtype Int5 is std_logic_vector(4 downto 0);
subtype Int4 is std_logic_vector(3 downto 0);
subtype Int3 is std_logic_vector(2 downto 0);
subtype Int8 is std_logic_vector(7 downto 0);
constant Int16_Zero : Int16 := "0000000000000000";
constant Int15_Zero : Int15 := "000000000000000";
constant Int5_Zero : Int5 := "00000";
constant Int4_Zero : Int4 := "0000";
constant Int4_One : Int4 := "1111";
constant Int3_Zero : Int3 := "000";
constant Int8_Zero : Int8 := "00000000";
constant Int16_eight: Int16 := "0000000000001000";
constant Int16_Z : int16 := "ZZZZZZZZZZZZZZZZ";
constant Zero_Reg: Int4 := "1000";
constant PC_Reg: Int4 := "1010";
constant IH_reg: Int4 := "1011";
constant RA_reg: Int4 := "1100";
constant SP_reg: Int4 := "1101";
function sll_2(imm: Int16) return Int16;
function extend(imm: Int16; imm_n: Int4; sign: std_logic) return int16;
end Common;
package body Common is
---- Example 1
-- function <function_name> (signal <signal_name> : in <type_declaration> ) return <type_declaration> is
-- variable <variable_name> : <type_declaration>;
-- begin
-- <variable_name> := <signal_name> xor <signal_name>;
-- return <variable_name>;
-- end <function_name>;
---- Example 2
-- function <function_name> (signal <signal_name> : in <type_declaration>;
-- signal <signal_name> : in <type_declaration> ) return <type_declaration> is
-- begin
-- if (<signal_name> = '1') then
-- return <signal_name>;
-- else
-- return 'Z';
-- end if;
-- end <function_name>;
---- Procedure Example
-- procedure <procedure_name> (<type_declaration> <constant_name> : in <type_declaration>) is
--
-- begin
--
-- end <procedure_name>;
function sll_2(imm: Int16) return Int16 is
variable i : integer := 2;
variable n1: bit_vector(15 downto 0);
begin
i := 2;
n1 := TO_BITVECTOR(imm);
return TO_STDLOGICVECTOR(n1 sll i);
end sll_2;
function extend(imm: Int16; imm_n: Int4; sign: std_logic) return int16 is
variable re: int16 := int16_zero;
begin
if sign = '1' then --sign_extend
case imm_n is
when "0011" =>
re(15 downto 3) := (others => imm(2));
re(2 downto 0) := imm(2 downto 0);
when "1000" =>
re(15 downto 8) := (others => imm(7));
re(7 downto 0) := imm(7 downto 0);
when "0100" =>
re(15 downto 4) := (others => imm(3));
re(3 downto 0) := imm(3 downto 0);
when "0101" =>
re(15 downto 5) := (others => imm(4));
re(4 downto 0) := imm(4 downto 0);
when "1011" =>
re(15 downto 11) := (others => imm(10));
re(10 downto 0) := imm(10 downto 0);
when others => null;
end case;
else --zero_extend
case imm_n is
when "1000" =>
re(15 downto 8) := (others => '0');
re(7 downto 0) := imm(7 downto 0);
when "0011" =>
re(15 downto 3) := (others => '0');
re(2 downto 0) := imm(2 downto 0);
when others => null;
end case;
end if;
return re;
end extend;
end Common;
|
-- libraries --------------------------------------------------------------------------------- {{{
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
use ieee.std_logic_textio.all;
use std.textio.all;
------------------------------------------------------------------------------------------------- }}}
package FGPU_definitions is
-- Begin of Configurable FGPU Parameters ----------------------------------------------------------------{{{
constant N_CU_W : natural := 0; --0 to 3
-- Bitwidth of # of CUs
constant LMEM_ADDR_W : natural := 10;
-- bitwidth of local memory address for a single PE
constant N_AXI_W : natural := 0;
-- Bitwidth of # of AXI data ports
constant SUB_INTEGER_IMPLEMENT : natural := 0;
-- implement sub-integer store operations
constant N_STATIONS_ALU : natural := 4;
-- # stations to store memory requests sourced by a single ALU
constant ATOMIC_IMPLEMENT : natural := 0;
-- implement global atomic operations
constant AADD_ATOMIC : natural := 1;
constant AMAX_ATOMIC : natural := 1;
constant LMEM_IMPLEMENT : natural := 1;
-- implement local scratchpad
constant N_TAG_MANAGERS_W : natural := N_CU_W+0; -- 0 to 1
-- Bitwidth of # tag controllers per CU
constant RD_CACHE_N_WORDS_W : natural := 0;
-- Bitwidth of # of words the global read bus cache -> CUs
constant RD_CACHE_FIFO_PORTB_ADDR_W : natural := 8;
-- Bitwidth of the fifo buffer for the data read out of the cache. A fifo is implemented in each CU.
constant CACHE_N_BANKS_W : natural := 2;
-- Bitwidth of # words within a cache line. Minimum is 2
constant N_RECEIVERS_CU_W : natural := 6-N_CU_W;
-- Bitwidth of # of receivers inside the global memory controller per CU. (6-N_CU_W) will lead to 64 receivers whatever the # of CU is.
constant BURST_WORDS_W : natural := 5;
-- Bitwidth # of words within a single AXI burst (only 5 is tested intensively, 4 & 6 should work but needs testing)
constant ENABLE_READ_PRIORIRY_PIPE : boolean := false;
-- Implements a priority pipeline for the stations of the global memory controller which prioritizes waiting stations when more time is elapsed
constant FIFO_ADDR_W : natural := 3;
-- Bitwidth of the fifo size to store outgoing memory requests from a CU
constant FINISH_FIFO_ADDR_W : natural := 3;
-- Bitwidth of the fifo depth to mark dirty cache lines to be cleared at the end
constant CV_W : natural := 3;
-- bitwidth of # of PEs within a CV (only 3 was tested, i.e. 8 PEs/CU)
-- Floating-point hardware support:
constant FLOAT_IMPLEMENT : natural := 0;
constant FADD_IMPLEMENT : integer := 1;
constant FMUL_IMPLEMENT : integer := 1;
constant FDIV_IMPLEMENT : integer := 1;
constant FSQRT_IMPLEMENT : integer := 1;
constant UITOFP_IMPLEMENT : integer := 1;
constant FSLT_IMPLEMENT : integer := 1;
constant FRSQRT_IMPLEMENT : integer := 0;
constant FADD_DELAY : integer := 11;
constant UITOFP_DELAY : integer := 5;
constant FMUL_DELAY : integer := 8;
constant FDIV_DELAY : integer := 28;
constant FSQRT_DELAY : integer := 28;
constant FRSQRT_DELAY : integer := 28;
constant FSLT_DELAY : integer := 2;
constant MAX_FPU_DELAY : integer := FDIV_DELAY;
constant CV_TO_CACHE_SLICE : natural := 3;
constant INSTR_READ_SLICE : boolean := true;
constant RTM_WRITE_SLICE : boolean := true;
constant WRITE_PHASE_W : natural := 1;
-- # of MSBs of the receiver index in the global memory controller which will be selected to write. These bits increments always.
-- This incrmenetation should help to balance serving the receivers
constant RCV_PRIORITY_W : natural := 3;
-- End of Configurable FGPU Parameters ------------------------------------------------------------------}}}
constant N_WF_CU_W : natural := 3;
-- bitwidth of # of WFs that can be simultaneously managed within a CU
constant N_RD_FIFOS_TAG_MANAGER_W : natural := 0;
-- one fifo to store data read out of global memory for each tag manager (now, only 0 makes sense)
constant GMEM_N_BANK_W : natural := 1;
-- Bitwidth of the number of words of a single AXI data interface, i.e. the global memory bus
constant ID_WIDTH : natural := 6;
-- Bitwidth of the read & write id channels of AXI4
constant PHASE_W : natural := 3;
-- # of clock cycles when executing the same instruction on the a CV (only 3 is tested)
constant CV_SIZE : natural := 2**CV_W;
-- constant CRAM_BLOCKS : natural := 1;
-- # of CRAM replicates. Each replicate will serve some CUs (1 or 2 supported only)
constant RD_CACHE_N_WORDS : natural := 2**RD_CACHE_N_WORDS_W;
constant WF_SIZE_W : natural := PHASE_W + CV_W;
-- A WF will be executed on the PEs of a single CV withen PAHSE_LEN cycels
constant WG_SIZE_W : natural := WF_SIZE_W + N_WF_CU_W;
-- A WG must be executed on a single CV. It contains a number of WFs which is at maximum the amount that can be managed within a CV
constant RTM_ADDR_W : natural := 1+2+N_WF_CU_W+PHASE_W; -- 1+2+3+3 = 9bit
-- The MSB if select between local indcs or other information
-- The lower 2 MSBs for d0, d1 or d2. The middle N_WF_CU_W are for the WF index with the CV. The lower LSBs are for the phase index
constant RTM_DATA_W : natural := CV_SIZE*WG_SIZE_W; -- Bitwidth of RTM data ports
constant BURST_W : natural := BURST_WORDS_W - GMEM_N_BANK_W; -- burst width in number of transfers on the axi bus
constant RD_FIFO_N_BURSTS_W : natural := 1;
constant RD_FIFO_W : natural := BURST_W + RD_FIFO_N_BURSTS_W;
constant N_TAG_MANAGERS : natural := 2**N_TAG_MANAGERS_W;
constant N_AXI : natural := 2**N_AXI_W;
constant N_WR_FIFOS_AXI_W : natural := N_TAG_MANAGERS_W-N_AXI_W;
constant INTERFCE_W_ADDR_W : natural := 14;
constant CRAM_ADDR_W : natural := 12; -- TODO
constant DATA_W : natural := 32;
constant BRAM18kb32b_ADDR_W : natural := 9;
constant BRAM36kb64b_ADDR_W : natural := 9;
constant BRAM36kb_ADDR_W : natural := 10;
constant INST_FIFO_PRE_LEN : natural := 8;
constant CV_INST_FIFO_W : natural := 3;
constant LOC_MEM_W : natural := BRAM18kb32b_ADDR_W;
constant N_PARAMS_W : natural := 4;
constant GMEM_ADDR_W : natural := 32;
constant WI_REG_ADDR_W : natural := 5;
constant N_REG_BLOCKS_W : natural := 2;
constant REG_FILE_BLOCK_W : natural := PHASE_W+WI_REG_ADDR_W+N_WF_CU_W-N_REG_BLOCKS_W; -- default=3+5+3-2=9
constant N_WR_FIFOS_W : natural := N_WR_FIFOS_AXI_W + N_AXI_W;
constant N_WR_FIFOS_AXI : natural := 2**N_WR_FIFOS_AXI_W;
constant N_WR_FIFOS : natural := 2**N_WR_FIFOS_W;
constant STAT : natural := 1;
constant STAT_LOAD : natural := 0;
-- cache & gmem controller constants
constant BRMEM_ADDR_W : natural := BRAM36kb_ADDR_W; -- default=10
constant N_RD_PORTS : natural := 4;
constant N : natural := CACHE_N_BANKS_W; -- max. 3
constant L : natural := BURST_WORDS_W-N; -- min. 2
constant M : natural := BRMEM_ADDR_W - L; -- max. 8
-- L+M = BMEM_ADDR_W = 10 = #address bits of a BRAM
-- cache size = 2^(N+L+M) words; max.=8*4KB=32KB
constant N_RECEIVERS_CU : natural := 2**N_RECEIVERS_CU_W;
constant N_RECEIVERS_W : natural := N_CU_W + N_RECEIVERS_CU_W;
constant N_RECEIVERS : natural := 2**N_RECEIVERS_W;
constant N_CU_STATIONS_W : natural := 6;
constant GMEM_WORD_ADDR_W : natural := GMEM_ADDR_W - 2;
constant TAG_W : natural := GMEM_WORD_ADDR_W -M -L -N;
constant GMEM_N_BANK : natural := 2**GMEM_N_BANK_W;
constant CACHE_N_BANKS : natural := 2**CACHE_N_BANKS_W;
constant REG_FILE_W : natural := N_REG_BLOCKS_W+REG_FILE_BLOCK_W;
constant N_REG_BLOCKS : natural := 2**N_REG_BLOCKS_W;
constant REG_ADDR_W : natural := BRAM18kb32b_ADDR_W+BRAM18kb32b_ADDR_W;
constant REG_FILE_SIZE : natural := 2**REG_ADDR_W;
constant REG_FILE_BLOCK_SIZE : natural := 2**REG_FILE_BLOCK_W;
constant GMEM_DATA_W : natural := GMEM_N_BANK * DATA_W;
constant N_PARAMS : natural := 2**N_PARAMS_W;
constant LOC_MEM_SIZE : natural := 2**LOC_MEM_W;
constant PHASE_LEN : natural := 2**PHASE_W;
constant CV_INST_FIFO_SIZE : natural := 2**CV_INST_FIFO_W;
constant N_CU : natural := 2**N_CU_W;
constant N_WF_CU : natural := 2**N_WF_CU_W;
constant WF_SIZE : natural := 2**WF_SIZE_W;
constant CRAM_SIZE : natural := 2**CRAM_ADDR_W;
constant RTM_SIZE : natural := 2**RTM_ADDR_W;
constant BRAM18kb_SIZE : natural := 2**BRAM18kb32b_ADDR_W;
constant regFile_addr : natural := 2**(INTERFCE_W_ADDR_W-1); -- "10" of the address msbs to choose the register file
constant Rstat_addr : natural := regFile_addr + 0; --address of status register in the register file
constant Rstart_addr : natural := regFile_addr + 1; --address of stat register in the register file
constant RcleanCache_addr : natural := regFile_addr + 2; --address of cleanCache register in the register file
constant RInitiate_addr : natural := regFile_addr + 3; --address of cleanCache register in the register file
constant Rstat_regFile_addr : natural := 0; --address of status register in the register file
constant Rstart_regFile_addr : natural := 1; --address of stat register in the register file
constant RcleanCache_regFile_addr : natural := 2; --address of cleanCache register in the register file
constant RInitiate_regFile_addr : natural := 3; --address of initiate register in the register file
constant N_REG_W : natural := 2;
constant PARAMS_ADDR_LOC_MEM_OFFSET : natural := LOC_MEM_SIZE - N_PARAMS;
-- constant GMEM_RQST_BUS_W : natural := GMEM_DATA_W;
-- new kernel descriptor ----------------------------------------------------------------
constant NEW_KRNL_DESC_W : natural := 5; -- length of the kernel's descripto
constant NEW_KRNL_INDX_W : natural := 4; -- bitwidth of number of kernels that can be started
constant NEW_KRNL_DESC_LEN : natural := 12;
constant WG_MAX_SIZE : natural := 2**WG_SIZE_W;
constant NEW_KRNL_DESC_MAX_LEN : natural := 2**NEW_KRNL_DESC_W;
constant NEW_KRNL_MAX_INDX : natural := 2**NEW_KRNL_INDX_W;
constant KRNL_SCH_ADDR_W : natural := NEW_KRNL_DESC_W + NEW_KRNL_INDX_W;
constant NEW_KRNL_DESC_N_WF : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 0;
constant NEW_KRNL_DESC_ID0_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 1;
constant NEW_KRNL_DESC_ID1_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 2;
constant NEW_KRNL_DESC_ID2_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 3;
constant NEW_KRNL_DESC_ID0_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 4;
constant NEW_KRNL_DESC_ID1_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 5;
constant NEW_KRNL_DESC_ID2_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 6;
constant NEW_KRNL_DESC_WG_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 7;
constant NEW_KRNL_DESC_N_WG_0 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 8;
constant NEW_KRNL_DESC_N_WG_1 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 9;
constant NEW_KRNL_DESC_N_WG_2 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 10;
constant NEW_KRNL_DESC_N_PARAMS : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 11;
constant PARAMS_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 16;
constant WG_SIZE_0_OFFSET : natural := 0;
constant WG_SIZE_1_OFFSET : natural := 10;
constant WG_SIZE_2_OFFSET : natural := 20;
constant N_DIM_OFFSET : natural := 30;
constant ADDR_FIRST_INST_OFFSET : natural := 0;
constant ADDR_LAST_INST_OFFSET : natural := 14;
constant N_WF_OFFSET : natural := 28;
constant N_WG_0_OFFSET : natural := 16;
constant N_WG_1_OFFSET : natural := 0;
constant N_WG_2_OFFSET : natural := 16;
constant WG_SIZE_OFFSET : natural := 0;
constant N_PARAMS_OFFSET : natural := 28;
type cram_type is array (2**CRAM_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0);
type slv32_array is array (natural range<>) of std_logic_vector(DATA_W-1 downto 0);
type krnl_scheduler_ram_TYPE is array (2**KRNL_SCH_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0);
type cram_addr_array is array (natural range <>) of unsigned(CRAM_ADDR_W-1 downto 0); -- range 0 to CRAM_SIZE-1;
type rtm_ram_type is array (natural range <>) of unsigned(RTM_DATA_W-1 downto 0);
type gmem_addr_array is array (natural range<>) of unsigned(GMEM_ADDR_W-1 downto 0);
type op_arith_shift_type is (op_add, op_lw, op_mult, op_bra, op_shift, op_slt, op_mov, op_ato, op_lmem);
type op_logical_type is (op_andi, op_and, op_ori, op_or, op_xor, op_xori, op_nor);
type be_array is array(natural range <>) of std_logic_vector(DATA_W/8-1 downto 0);
type gmem_be_array is array(natural range <>) of std_logic_vector(GMEM_N_BANK*DATA_W/8-1 downto 0);
type sl_array is array(natural range <>) of std_logic;
type nat_array is array(natural range <>) of natural;
type nat_2d_array is array(natural range <>, natural range <>) of natural;
type reg_addr_array is array (natural range <>) of unsigned(REG_FILE_W-1 downto 0);
type gmem_word_addr_array is array(natural range <>) of unsigned(GMEM_WORD_ADDR_W-1 downto 0);
type gmem_addr_array_no_bank is array (natural range <>) of unsigned(GMEM_WORD_ADDR_W-CACHE_N_BANKS_W-1 downto 0);
type alu_en_vec_type is array(natural range <>) of std_logic_vector(CV_SIZE-1 downto 0);
type alu_en_rdAddr_type is array(natural range <>) of unsigned(PHASE_W+N_WF_CU_W-1 downto 0);
type tag_array is array (natural range <>) of unsigned(TAG_W-1 downto 0);
type gmem_word_array is array (natural range <>) of std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0);
type wf_active_array is array (natural range <>) of std_logic_vector(N_WF_CU-1 downto 0);
type cache_addr_array is array(natural range <>) of unsigned(M+L-1 downto 0);
type cache_word_array is array(natural range <>) of std_logic_vector(CACHE_N_BANKS*DATA_W-1 downto 0);
type tag_addr_array is array(natural range <>) of unsigned(M-1 downto 0);
type reg_file_block_array is array(natural range<>) of unsigned(REG_FILE_BLOCK_W-1 downto 0);
type id_array is array(natural range<>) of std_logic_vector(ID_WIDTH-1 downto 0);
type real_array is array (natural range <>) of real;
type atomic_sgntr_array is array (natural range <>) of std_logic_vector(N_CU_STATIONS_W-1 downto 0);
attribute max_fanout: integer;
attribute keep: string;
attribute mark_debug : string;
impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type;
impure function init_SLV32_ARRAY_from_file(file_name : in string; len: in natural; file_len: in natural) return SLV32_ARRAY;
impure function init_CRAM(file_name : in string; file_len: in natural) return cram_type;
function pri_enc(datain: in std_logic_vector) return integer;
function max (LEFT, RIGHT: integer) return integer;
function min_int (LEFT, RIGHT: integer) return integer;
function clogb2 (bit_depth : integer) return integer;
--- ISA --------------------------------------------------------------------------------------
constant FAMILY_W : natural := 4;
constant CODE_W : natural := 4;
constant IMM_ARITH_W : natural := 14;
constant IMM_W : natural := 16;
constant BRANCH_ADDR_W : natural := 14;
constant FAMILY_POS : natural := 28;
constant CODE_POS : natural := 24;
constant RD_POS : natural := 0;
constant RS_POS : natural := 5;
constant RT_POS : natural := 10;
constant IMM_POS : natural := 10;
constant DIM_POS : natural := 5;
constant PARAM_POS : natural := 5;
constant BRANCH_ADDR_POS : natural := 10;
--------------- families
constant ADD_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"1";
constant SHF_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"2";
constant LGK_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"3";
constant MOV_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"4";
constant MUL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"5";
constant BRA_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"6";
constant GLS_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"7";
constant ATO_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"8";
constant CTL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"9";
constant RTM_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"A";
constant CND_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"B";
constant FLT_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"C";
constant LSI_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"D";
--------------- codes
--RTM
constant LID : std_logic_vector(CODE_W-1 downto 0) := X"0"; --upper two MSBs indicate if the operation is localdx or offsetdx
constant WGOFF : std_logic_vector(CODE_W-1 downto 0) := X"1";
constant SIZE : std_logic_vector(CODE_W-1 downto 0) := X"2";
constant WGID : std_logic_vector(CODE_W-1 downto 0) := X"3";
constant WGSIZE : std_logic_vector(CODE_W-1 downto 0) := X"4";
constant LP : std_logic_vector(CODE_W-1 downto 0) := X"8";
--ADD
constant ADD : std_logic_vector(CODE_W-1 downto 0) := "0000";
constant SUB : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant ADDI : std_logic_vector(CODE_W-1 downto 0) := "0001";
constant LI : std_logic_vector(CODE_W-1 downto 0) := "1001";
constant LUI : std_logic_vector(CODE_W-1 downto 0) := "1101";
--MUL
constant MACC : std_logic_vector(CODE_W-1 downto 0) := "1000";
--BRA
constant BEQ : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant BNE : std_logic_vector(CODE_W-1 downto 0) := "0011";
constant JSUB : std_logic_vector(CODE_W-1 downto 0) := "0100";
--GLS
constant LW : std_logic_vector(CODE_W-1 downto 0) := "0100";
constant SW : std_logic_vector(CODE_W-1 downto 0) := "1100";
--CTL
constant RET : std_logic_vector(CODE_W-1 downto 0) := "0010";
--SHF
constant SLLI : std_logic_vector(CODE_W-1 downto 0) := "0001";
--LGK
constant CODE_AND : std_logic_vector(CODE_W-1 downto 0) := "0000";
constant CODE_ANDI : std_logic_vector(CODE_W-1 downto 0) := "0001";
constant CODE_OR : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant CODE_ORI : std_logic_vector(CODE_W-1 downto 0) := "0011";
constant CODE_XOR : std_logic_vector(CODE_W-1 downto 0) := "0100";
constant CODE_XORI : std_logic_vector(CODE_W-1 downto 0) := "0101";
constant CODE_NOR : std_logic_vector(CODE_W-1 downto 0) := "1000";
--ATO
constant CODE_AMAX : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant CODE_AADD : std_logic_vector(CODE_W-1 downto 0) := "0001";
type branch_distance_vec is array(natural range <>) of unsigned(BRANCH_ADDR_W-1 downto 0);
type code_vec_type is array(natural range <>) of std_logic_vector(CODE_W-1 downto 0);
type atomic_type_vec_type is array(natural range <>) of std_logic_vector(2 downto 0);
end FGPU_definitions;
package body FGPU_definitions is
-- function called clogb2 that returns an integer which has the
--value of the ceiling of the log base 2
function clogb2 (bit_depth : integer) return integer is
variable depth : integer := bit_depth;
variable count : integer := 1;
begin
for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers
if (bit_depth <= 2) then
count := 1;
else
if(depth <= 1) then
count := count;
else
depth := depth / 2;
count := count + 1;
end if;
end if;
end loop;
return(count);
end;
impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type is
file init_file : text open read_mode is file_name;
variable init_line : line;
variable temp_bv : bit_vector(DATA_W-1 downto 0);
variable temp_mem : KRNL_SCHEDULER_RAM_type;
begin
for i in 0 to 16*32-1 loop
readline(init_file, init_line);
hread(init_line, temp_mem(i));
-- read(init_line, temp_bv);
-- temp_mem(i) := to_stdlogicvector(temp_bv);
end loop;
return temp_mem;
end function;
function max (LEFT, RIGHT: integer) return integer is
begin
if LEFT > RIGHT then return LEFT;
else return RIGHT;
end if;
end max;
function min_int (LEFT, RIGHT: integer) return integer is
begin
if LEFT > RIGHT then return RIGHT;
else return LEFT;
end if;
end min_int;
impure function init_CRAM(file_name : in string; file_len : in natural) return cram_type is
file init_file : text open read_mode is file_name;
variable init_line : line;
variable cram : cram_type;
-- variable tmp: std_logic_vector(DATA_W-1 downto 0);
begin
for i in 0 to file_len-1 loop
readline(init_file, init_line);
hread(init_line, cram(i)); -- vivado breaks when synthesizing hread(init_line, cram(0)(i)) without giving any indication about the error
-- cram(i) := tmp;
-- if CRAM_BLOCKS > 1 then
-- for j in 1 to max(1,CRAM_BLOCKS-1) loop
-- cram(j)(i) := cram(0)(i);
-- end loop;
-- end if;
end loop;
return cram;
end function;
impure function init_SLV32_ARRAY_from_file(file_name : in string; len : in natural; file_len : in natural) return SLV32_ARRAY is
file init_file : text open read_mode is file_name;
variable init_line : line;
variable temp_mem : SLV32_ARRAY(len-1 downto 0);
begin
for i in 0 to file_len-1 loop
readline(init_file, init_line);
hread(init_line, temp_mem(i));
end loop;
return temp_mem;
end function;
function pri_enc(datain: in std_logic_vector) return integer is
variable res : integer range 0 to datain'high;
begin
res := 0;
for i in datain'high downto 1 loop
if datain(i) = '1' then
res := i;
end if;
end loop;
return res;
end function;
end FGPU_definitions;
|
----------------------------------------------------------------------------------
-- Company: Ratner Engineering
-- Engineer: James Ratner
--
-- Create Date: 19:42:08 11/28/2011
-- Design Name:
-- Module Name: FSM - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description: This is a RET debouncer with both one-shot and pulse output.
-- The SIG is the signal to be debounced and the CLK is the system
-- clock. The level output remains asserted as long as the signal to
-- be debounced remains asserted once the signal is deemed "good" by
-- the debounce unit. The pulse output is a 2-clock wide signal
-- that is output once the input signal passes the debounce
-- qualifications.
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created: 03-12-2015
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity ret_db_1shot is
Port ( CLK : in STD_LOGIC;
SIG : in STD_LOGIC;
PULSE : out STD_LOGIC;
LEVEL : out STD_LOGIC);
end ret_db_1shot;
architecture Behavioral of ret_db_1shot is
type state_type is (st_wait, st_count, st_hold);
signal PS, NS : state_type;
constant WAIT_COUNT : integer := 5; -- debounce wait counter
signal s_en : std_logic;
signal s_rco : std_logic;
signal s_one_shot_1 : std_logic;
signal s_one_shot_2 : std_logic;
begin
--------------------------------------------------
-- input FSM
--------------------------------------------------
sync_proc : process (CLK, NS)
begin
if (rising_edge(CLK)) then
PS <= NS;
end if;
end process sync_proc;
comb_proc : process (PS, s_rco, SIG)
begin
s_en <= '0';
LEVEL <= '0';
case PS is
when st_wait =>
s_en <= '0';
LEVEL <= '0';
if (SIG = '0') then
NS <= st_wait;
else
NS <= st_count;
end if;
when st_count =>
s_en <= '1';
LEVEL <= '0';
if (s_rco = '0') then
NS <= st_count;
elsif (s_RCO = '1' and SIG = '1') then
NS <= st_hold;
else
NS <= st_wait;
end if;
when st_hold =>
s_en <= '0';
LEVEL <= '1';
if (SIG = '0') then
NS <= st_wait;
else
NS <= st_hold;
end if;
when others =>
NS <= st_wait;
end case;
end process comb_proc;
--------------------------------------------------
--------------------------------------------------
-- debounce counter
--------------------------------------------------
process(CLK)
variable v_pulse_cnt : integer := 0;
begin
if (rising_edge(CLK)) then
if (s_en = '1') then
if (v_pulse_cnt = WAIT_COUNT) then
v_pulse_cnt := 0; -- reset pulse count
s_rco <= '1'; -- reset pulse flip flop
else
v_pulse_cnt := v_pulse_cnt + 1;
s_rco <= '0';
end if;
else -- reset count if s_en turns off
v_pulse_cnt := 0;
s_rco <= '0';
end if;
end if;
end process;
--------------------------------------------------
-- debounce counter
--------------------------------------------------
process(CLK, s_rco, SIG)
begin
if (rising_edge(CLK)) then
if (s_rco = '1' and SIG = '1') then
s_one_shot_1 <= '1';
s_one_shot_2 <= s_one_shot_1;
else
s_one_shot_1 <= '0';
s_one_shot_2 <= s_one_shot_1;
end if;
end if;
end process;
PULSE <= s_one_shot_2 or s_one_shot_1;
--------------------------------------------------
end Behavioral;
|
package pack is
type rec is record
x, y : integer;
end record;
end package;
-------------------------------------------------------------------------------
use work.pack.all;
entity sub is
generic ( r : rec; en : boolean );
port ( x_out, y_out : out bit_vector(1 to 2) );
end entity;
architecture test of sub is
begin
g: if en generate
main: process is
function get_bits(n : integer) return bit_vector is
begin
case n is
when 1 => return (1 to 2 => '1');
when others => return (1 to 2 => '0');
end case;
end function;
constant x : bit_vector(1 to 2) := get_bits(r.x);
constant y : bit_vector(1 to 2) := get_bits(r.y);
begin
x_out <= x;
y_out <= y;
wait;
end process;
end generate;
end architecture;
-------------------------------------------------------------------------------
entity elab28 is
end entity;
architecture test of elab28 is
signal x, y : bit_vector(1 to 2);
begin
uut: entity work.sub
generic map ( ( 0, 1 ), true )
port map ( x, y );
end architecture;
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Thu May 25 15:18:23 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub
-- C:/ZyboIP/examples/zed_camera_test/zed_camera_test.srcs/sources_1/bd/system/ip/system_vga_sync_ref_0_0/system_vga_sync_ref_0_0_stub.vhdl
-- Design : system_vga_sync_ref_0_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity system_vga_sync_ref_0_0 is
Port (
clk : in STD_LOGIC;
rst : in STD_LOGIC;
hsync : in STD_LOGIC;
vsync : in STD_LOGIC;
start : out STD_LOGIC;
active : out STD_LOGIC;
xaddr : out STD_LOGIC_VECTOR ( 9 downto 0 );
yaddr : out STD_LOGIC_VECTOR ( 9 downto 0 )
);
end system_vga_sync_ref_0_0;
architecture stub of system_vga_sync_ref_0_0 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "clk,rst,hsync,vsync,start,active,xaddr[9:0],yaddr[9:0]";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "vga_sync_ref,Vivado 2016.4";
begin
end;
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Thu May 25 15:18:23 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub
-- C:/ZyboIP/examples/zed_camera_test/zed_camera_test.srcs/sources_1/bd/system/ip/system_vga_sync_ref_0_0/system_vga_sync_ref_0_0_stub.vhdl
-- Design : system_vga_sync_ref_0_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity system_vga_sync_ref_0_0 is
Port (
clk : in STD_LOGIC;
rst : in STD_LOGIC;
hsync : in STD_LOGIC;
vsync : in STD_LOGIC;
start : out STD_LOGIC;
active : out STD_LOGIC;
xaddr : out STD_LOGIC_VECTOR ( 9 downto 0 );
yaddr : out STD_LOGIC_VECTOR ( 9 downto 0 )
);
end system_vga_sync_ref_0_0;
architecture stub of system_vga_sync_ref_0_0 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "clk,rst,hsync,vsync,start,active,xaddr[9:0],yaddr[9:0]";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "vga_sync_ref,Vivado 2016.4";
begin
end;
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Thu May 25 15:18:23 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub
-- C:/ZyboIP/examples/zed_camera_test/zed_camera_test.srcs/sources_1/bd/system/ip/system_vga_sync_ref_0_0/system_vga_sync_ref_0_0_stub.vhdl
-- Design : system_vga_sync_ref_0_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity system_vga_sync_ref_0_0 is
Port (
clk : in STD_LOGIC;
rst : in STD_LOGIC;
hsync : in STD_LOGIC;
vsync : in STD_LOGIC;
start : out STD_LOGIC;
active : out STD_LOGIC;
xaddr : out STD_LOGIC_VECTOR ( 9 downto 0 );
yaddr : out STD_LOGIC_VECTOR ( 9 downto 0 )
);
end system_vga_sync_ref_0_0;
architecture stub of system_vga_sync_ref_0_0 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "clk,rst,hsync,vsync,start,active,xaddr[9:0],yaddr[9:0]";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "vga_sync_ref,Vivado 2016.4";
begin
end;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: tbufmem
-- File: tbufmem.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: 256-bit trace buffer memory (CPU/AHB)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.leon3.all;
library techmap;
use techmap.gencomp.all;
library grlib;
use grlib.stdlib.all;
entity tbufmem is
generic (
tech : integer := 0;
tbuf : integer := 0; -- trace buf size in kB (0 - no trace buffer)
dwidth : integer := 32; -- AHB data width
testen : integer := 0
);
port (
clk : in std_ulogic;
di : in tracebuf_in_type;
do : out tracebuf_out_type;
testin : in std_logic_vector(TESTIN_WIDTH-1 downto 0)
);
end;
architecture rtl of tbufmem is
constant ADDRBITS : integer := 10 + log2(tbuf) - 4;
signal enable : std_logic_vector(1 downto 0);
begin
enable <= di.enable & di.enable;
mem32 : for i in 0 to 1 generate -- basic 128 buffer
ram0 : syncram64 generic map (tech => tech, abits => addrbits, testen => testen, custombits => memtest_vlen)
port map ( clk, di.addr(addrbits-1 downto 0), di.data(((i*64)+63) downto (i*64)),
do.data(((i*64)+63) downto (i*64)), enable ,di.write(i*2+1 downto i*2), testin
);
end generate;
mem64 : if dwidth > 32 generate -- extra data buffer for 64-bit bus
ram0 : syncram generic map (tech => tech, abits => addrbits, dbits => 32, testen => testen, custombits => memtest_vlen)
port map ( clk, di.addr(addrbits-1 downto 0), di.data((128+31) downto 128),
do.data((128+31) downto 128), di.enable, di.write(7), testin
);
end generate;
mem128 : if dwidth > 64 generate -- extra data buffer for 128-bit bus
ram0 : syncram64 generic map (tech => tech, abits => addrbits, testen => testen, custombits => memtest_vlen)
port map ( clk, di.addr(addrbits-1 downto 0), di.data((128+95) downto (128+32)),
do.data((128+95) downto (128+32)), enable ,di.write(6 downto 5), testin
);
end generate;
nomem64 : if dwidth < 64 generate -- no extra data buffer for 64-bit bus
do.data((128+31) downto 128) <= (others => '0');
end generate;
nomem128 : if dwidth < 128 generate -- no extra data buffer for 128-bit bus
do.data((128+95) downto (128+32)) <= (others => '0');
end generate;
do.data(255 downto 224) <= (others => '0');
end;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_02_tb_02_01.vhd,v 1.1.1.1 2001-08-22 18:20:47 paw Exp $
-- $Revision: 1.1.1.1 $
--
-- ---------------------------------------------------------------------
entity ent is
end entity ent;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_02_tb_02_01.vhd,v 1.1.1.1 2001-08-22 18:20:47 paw Exp $
-- $Revision: 1.1.1.1 $
--
-- ---------------------------------------------------------------------
entity ent is
end entity ent;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_02_tb_02_01.vhd,v 1.1.1.1 2001-08-22 18:20:47 paw Exp $
-- $Revision: 1.1.1.1 $
--
-- ---------------------------------------------------------------------
entity ent is
end entity ent;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity bitsToNumbers is
port(
cadenaOriginalDeBits: IN STD_LOGIC_VECTOR(8 downto 0);
numero : OUT STD_LOGIC_VECTOR(3 downto 0)
);
end bitsToNumbers;
architecture Behavioral of bitsToNumbers is
begin
process(cadenaOriginalDeBits)
begin
case cadenaOriginalDeBits is
when "100000000" => numero <= "0001";
when "010000000" => numero <= "0010";
when "001000000" => numero <= "0011";
when "000100000" => numero <= "0100";
when "000010000" => numero <= "0101";
when "000001000" => numero <= "0110";
when "000000100" => numero <= "0111";
when "000000010" => numero <= "1000";
when "000000001" => numero <= "1001";
when others => numero <= "0000";
end case;
end process;
end architecture;
|
component ghrd_10as066n2_pr_region_controller_0 is
port (
avl_csr_read : in std_logic := 'X'; -- read
avl_csr_write : in std_logic := 'X'; -- write
avl_csr_address : in std_logic_vector(1 downto 0) := (others => 'X'); -- address
avl_csr_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
avl_csr_readdata : out std_logic_vector(31 downto 0); -- readdata
bridge_freeze0_freeze : out std_logic; -- freeze
bridge_freeze0_illegal_request : in std_logic := 'X'; -- illegal_request
bridge_freeze1_freeze : out std_logic; -- freeze
bridge_freeze1_illegal_request : in std_logic := 'X'; -- illegal_request
clock_clk : in std_logic := 'X'; -- clk
pr_handshake_start_req : out std_logic; -- start_req
pr_handshake_start_ack : in std_logic := 'X'; -- start_ack
pr_handshake_stop_req : out std_logic; -- stop_req
pr_handshake_stop_ack : in std_logic := 'X'; -- stop_ack
reset_reset : in std_logic := 'X'; -- reset
reset_source_reset : out std_logic -- reset
);
end component ghrd_10as066n2_pr_region_controller_0;
u0 : component ghrd_10as066n2_pr_region_controller_0
port map (
avl_csr_read => CONNECTED_TO_avl_csr_read, -- avl_csr.read
avl_csr_write => CONNECTED_TO_avl_csr_write, -- .write
avl_csr_address => CONNECTED_TO_avl_csr_address, -- .address
avl_csr_writedata => CONNECTED_TO_avl_csr_writedata, -- .writedata
avl_csr_readdata => CONNECTED_TO_avl_csr_readdata, -- .readdata
bridge_freeze0_freeze => CONNECTED_TO_bridge_freeze0_freeze, -- bridge_freeze0.freeze
bridge_freeze0_illegal_request => CONNECTED_TO_bridge_freeze0_illegal_request, -- .illegal_request
bridge_freeze1_freeze => CONNECTED_TO_bridge_freeze1_freeze, -- bridge_freeze1.freeze
bridge_freeze1_illegal_request => CONNECTED_TO_bridge_freeze1_illegal_request, -- .illegal_request
clock_clk => CONNECTED_TO_clock_clk, -- clock.clk
pr_handshake_start_req => CONNECTED_TO_pr_handshake_start_req, -- pr_handshake.start_req
pr_handshake_start_ack => CONNECTED_TO_pr_handshake_start_ack, -- .start_ack
pr_handshake_stop_req => CONNECTED_TO_pr_handshake_stop_req, -- .stop_req
pr_handshake_stop_ack => CONNECTED_TO_pr_handshake_stop_ack, -- .stop_ack
reset_reset => CONNECTED_TO_reset_reset, -- reset.reset
reset_source_reset => CONNECTED_TO_reset_source_reset -- reset_source.reset
);
|
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: utt.fr:hls_video:doImgProc:1.0
-- IP Revision: 1606211642
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY design_1_doImgProc_0_2 IS
PORT (
s_axi_CRTL_BUS_AWADDR : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
s_axi_CRTL_BUS_AWVALID : IN STD_LOGIC;
s_axi_CRTL_BUS_AWREADY : OUT STD_LOGIC;
s_axi_CRTL_BUS_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_CRTL_BUS_WSTRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_CRTL_BUS_WVALID : IN STD_LOGIC;
s_axi_CRTL_BUS_WREADY : OUT STD_LOGIC;
s_axi_CRTL_BUS_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_CRTL_BUS_BVALID : OUT STD_LOGIC;
s_axi_CRTL_BUS_BREADY : IN STD_LOGIC;
s_axi_CRTL_BUS_ARADDR : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
s_axi_CRTL_BUS_ARVALID : IN STD_LOGIC;
s_axi_CRTL_BUS_ARREADY : OUT STD_LOGIC;
s_axi_CRTL_BUS_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_CRTL_BUS_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_CRTL_BUS_RVALID : OUT STD_LOGIC;
s_axi_CRTL_BUS_RREADY : IN STD_LOGIC;
s_axi_KERNEL_BUS_AWADDR : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
s_axi_KERNEL_BUS_AWVALID : IN STD_LOGIC;
s_axi_KERNEL_BUS_AWREADY : OUT STD_LOGIC;
s_axi_KERNEL_BUS_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_KERNEL_BUS_WSTRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_KERNEL_BUS_WVALID : IN STD_LOGIC;
s_axi_KERNEL_BUS_WREADY : OUT STD_LOGIC;
s_axi_KERNEL_BUS_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_KERNEL_BUS_BVALID : OUT STD_LOGIC;
s_axi_KERNEL_BUS_BREADY : IN STD_LOGIC;
s_axi_KERNEL_BUS_ARADDR : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
s_axi_KERNEL_BUS_ARVALID : IN STD_LOGIC;
s_axi_KERNEL_BUS_ARREADY : OUT STD_LOGIC;
s_axi_KERNEL_BUS_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_KERNEL_BUS_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_KERNEL_BUS_RVALID : OUT STD_LOGIC;
s_axi_KERNEL_BUS_RREADY : IN STD_LOGIC;
ap_clk : IN STD_LOGIC;
ap_rst_n : IN STD_LOGIC;
interrupt : OUT STD_LOGIC;
inStream_TVALID : IN STD_LOGIC;
inStream_TREADY : OUT STD_LOGIC;
inStream_TDATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
inStream_TDEST : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
inStream_TKEEP : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
inStream_TSTRB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
inStream_TUSER : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
inStream_TLAST : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
inStream_TID : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
outStream_TVALID : OUT STD_LOGIC;
outStream_TREADY : IN STD_LOGIC;
outStream_TDATA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
outStream_TDEST : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
outStream_TKEEP : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
outStream_TSTRB : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
outStream_TUSER : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
outStream_TLAST : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
outStream_TID : OUT STD_LOGIC_VECTOR(4 DOWNTO 0)
);
END design_1_doImgProc_0_2;
ARCHITECTURE design_1_doImgProc_0_2_arch OF design_1_doImgProc_0_2 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_doImgProc_0_2_arch: ARCHITECTURE IS "yes";
COMPONENT doImgProc IS
GENERIC (
C_S_AXI_CRTL_BUS_ADDR_WIDTH : INTEGER;
C_S_AXI_CRTL_BUS_DATA_WIDTH : INTEGER;
C_S_AXI_KERNEL_BUS_ADDR_WIDTH : INTEGER;
C_S_AXI_KERNEL_BUS_DATA_WIDTH : INTEGER
);
PORT (
s_axi_CRTL_BUS_AWADDR : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
s_axi_CRTL_BUS_AWVALID : IN STD_LOGIC;
s_axi_CRTL_BUS_AWREADY : OUT STD_LOGIC;
s_axi_CRTL_BUS_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_CRTL_BUS_WSTRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_CRTL_BUS_WVALID : IN STD_LOGIC;
s_axi_CRTL_BUS_WREADY : OUT STD_LOGIC;
s_axi_CRTL_BUS_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_CRTL_BUS_BVALID : OUT STD_LOGIC;
s_axi_CRTL_BUS_BREADY : IN STD_LOGIC;
s_axi_CRTL_BUS_ARADDR : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
s_axi_CRTL_BUS_ARVALID : IN STD_LOGIC;
s_axi_CRTL_BUS_ARREADY : OUT STD_LOGIC;
s_axi_CRTL_BUS_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_CRTL_BUS_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_CRTL_BUS_RVALID : OUT STD_LOGIC;
s_axi_CRTL_BUS_RREADY : IN STD_LOGIC;
s_axi_KERNEL_BUS_AWADDR : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
s_axi_KERNEL_BUS_AWVALID : IN STD_LOGIC;
s_axi_KERNEL_BUS_AWREADY : OUT STD_LOGIC;
s_axi_KERNEL_BUS_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_KERNEL_BUS_WSTRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_KERNEL_BUS_WVALID : IN STD_LOGIC;
s_axi_KERNEL_BUS_WREADY : OUT STD_LOGIC;
s_axi_KERNEL_BUS_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_KERNEL_BUS_BVALID : OUT STD_LOGIC;
s_axi_KERNEL_BUS_BREADY : IN STD_LOGIC;
s_axi_KERNEL_BUS_ARADDR : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
s_axi_KERNEL_BUS_ARVALID : IN STD_LOGIC;
s_axi_KERNEL_BUS_ARREADY : OUT STD_LOGIC;
s_axi_KERNEL_BUS_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_KERNEL_BUS_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_KERNEL_BUS_RVALID : OUT STD_LOGIC;
s_axi_KERNEL_BUS_RREADY : IN STD_LOGIC;
ap_clk : IN STD_LOGIC;
ap_rst_n : IN STD_LOGIC;
interrupt : OUT STD_LOGIC;
inStream_TVALID : IN STD_LOGIC;
inStream_TREADY : OUT STD_LOGIC;
inStream_TDATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
inStream_TDEST : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
inStream_TKEEP : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
inStream_TSTRB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
inStream_TUSER : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
inStream_TLAST : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
inStream_TID : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
outStream_TVALID : OUT STD_LOGIC;
outStream_TREADY : IN STD_LOGIC;
outStream_TDATA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
outStream_TDEST : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
outStream_TKEEP : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
outStream_TSTRB : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
outStream_TUSER : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
outStream_TLAST : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
outStream_TID : OUT STD_LOGIC_VECTOR(4 DOWNTO 0)
);
END COMPONENT doImgProc;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axi_CRTL_BUS_AWADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_CRTL_BUS AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_CRTL_BUS_AWVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_CRTL_BUS AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_CRTL_BUS_AWREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_CRTL_BUS AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_CRTL_BUS_WDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_CRTL_BUS WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_CRTL_BUS_WSTRB: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_CRTL_BUS WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_CRTL_BUS_WVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_CRTL_BUS WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_CRTL_BUS_WREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_CRTL_BUS WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_CRTL_BUS_BRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_CRTL_BUS BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_CRTL_BUS_BVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_CRTL_BUS BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_CRTL_BUS_BREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_CRTL_BUS BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_CRTL_BUS_ARADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_CRTL_BUS ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_CRTL_BUS_ARVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_CRTL_BUS ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_CRTL_BUS_ARREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_CRTL_BUS ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_CRTL_BUS_RDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_CRTL_BUS RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_CRTL_BUS_RRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_CRTL_BUS RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_CRTL_BUS_RVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_CRTL_BUS RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_CRTL_BUS_RREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_CRTL_BUS RREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_KERNEL_BUS_AWADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_KERNEL_BUS AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_KERNEL_BUS_AWVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_KERNEL_BUS AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_KERNEL_BUS_AWREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_KERNEL_BUS AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_KERNEL_BUS_WDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_KERNEL_BUS WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_KERNEL_BUS_WSTRB: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_KERNEL_BUS WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_KERNEL_BUS_WVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_KERNEL_BUS WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_KERNEL_BUS_WREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_KERNEL_BUS WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_KERNEL_BUS_BRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_KERNEL_BUS BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_KERNEL_BUS_BVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_KERNEL_BUS BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_KERNEL_BUS_BREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_KERNEL_BUS BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_KERNEL_BUS_ARADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_KERNEL_BUS ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_KERNEL_BUS_ARVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_KERNEL_BUS ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_KERNEL_BUS_ARREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_KERNEL_BUS ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_KERNEL_BUS_RDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_KERNEL_BUS RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_KERNEL_BUS_RRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_KERNEL_BUS RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_KERNEL_BUS_RVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_KERNEL_BUS RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_KERNEL_BUS_RREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_KERNEL_BUS RREADY";
ATTRIBUTE X_INTERFACE_INFO OF ap_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 ap_clk CLK";
ATTRIBUTE X_INTERFACE_INFO OF ap_rst_n: SIGNAL IS "xilinx.com:signal:reset:1.0 ap_rst_n RST";
ATTRIBUTE X_INTERFACE_INFO OF interrupt: SIGNAL IS "xilinx.com:signal:interrupt:1.0 interrupt INTERRUPT";
ATTRIBUTE X_INTERFACE_INFO OF inStream_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 inStream TVALID";
ATTRIBUTE X_INTERFACE_INFO OF inStream_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 inStream TREADY";
ATTRIBUTE X_INTERFACE_INFO OF inStream_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 inStream TDATA";
ATTRIBUTE X_INTERFACE_INFO OF inStream_TDEST: SIGNAL IS "xilinx.com:interface:axis:1.0 inStream TDEST";
ATTRIBUTE X_INTERFACE_INFO OF inStream_TKEEP: SIGNAL IS "xilinx.com:interface:axis:1.0 inStream TKEEP";
ATTRIBUTE X_INTERFACE_INFO OF inStream_TSTRB: SIGNAL IS "xilinx.com:interface:axis:1.0 inStream TSTRB";
ATTRIBUTE X_INTERFACE_INFO OF inStream_TUSER: SIGNAL IS "xilinx.com:interface:axis:1.0 inStream TUSER";
ATTRIBUTE X_INTERFACE_INFO OF inStream_TLAST: SIGNAL IS "xilinx.com:interface:axis:1.0 inStream TLAST";
ATTRIBUTE X_INTERFACE_INFO OF inStream_TID: SIGNAL IS "xilinx.com:interface:axis:1.0 inStream TID";
ATTRIBUTE X_INTERFACE_INFO OF outStream_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 outStream TVALID";
ATTRIBUTE X_INTERFACE_INFO OF outStream_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 outStream TREADY";
ATTRIBUTE X_INTERFACE_INFO OF outStream_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 outStream TDATA";
ATTRIBUTE X_INTERFACE_INFO OF outStream_TDEST: SIGNAL IS "xilinx.com:interface:axis:1.0 outStream TDEST";
ATTRIBUTE X_INTERFACE_INFO OF outStream_TKEEP: SIGNAL IS "xilinx.com:interface:axis:1.0 outStream TKEEP";
ATTRIBUTE X_INTERFACE_INFO OF outStream_TSTRB: SIGNAL IS "xilinx.com:interface:axis:1.0 outStream TSTRB";
ATTRIBUTE X_INTERFACE_INFO OF outStream_TUSER: SIGNAL IS "xilinx.com:interface:axis:1.0 outStream TUSER";
ATTRIBUTE X_INTERFACE_INFO OF outStream_TLAST: SIGNAL IS "xilinx.com:interface:axis:1.0 outStream TLAST";
ATTRIBUTE X_INTERFACE_INFO OF outStream_TID: SIGNAL IS "xilinx.com:interface:axis:1.0 outStream TID";
BEGIN
U0 : doImgProc
GENERIC MAP (
C_S_AXI_CRTL_BUS_ADDR_WIDTH => 5,
C_S_AXI_CRTL_BUS_DATA_WIDTH => 32,
C_S_AXI_KERNEL_BUS_ADDR_WIDTH => 5,
C_S_AXI_KERNEL_BUS_DATA_WIDTH => 32
)
PORT MAP (
s_axi_CRTL_BUS_AWADDR => s_axi_CRTL_BUS_AWADDR,
s_axi_CRTL_BUS_AWVALID => s_axi_CRTL_BUS_AWVALID,
s_axi_CRTL_BUS_AWREADY => s_axi_CRTL_BUS_AWREADY,
s_axi_CRTL_BUS_WDATA => s_axi_CRTL_BUS_WDATA,
s_axi_CRTL_BUS_WSTRB => s_axi_CRTL_BUS_WSTRB,
s_axi_CRTL_BUS_WVALID => s_axi_CRTL_BUS_WVALID,
s_axi_CRTL_BUS_WREADY => s_axi_CRTL_BUS_WREADY,
s_axi_CRTL_BUS_BRESP => s_axi_CRTL_BUS_BRESP,
s_axi_CRTL_BUS_BVALID => s_axi_CRTL_BUS_BVALID,
s_axi_CRTL_BUS_BREADY => s_axi_CRTL_BUS_BREADY,
s_axi_CRTL_BUS_ARADDR => s_axi_CRTL_BUS_ARADDR,
s_axi_CRTL_BUS_ARVALID => s_axi_CRTL_BUS_ARVALID,
s_axi_CRTL_BUS_ARREADY => s_axi_CRTL_BUS_ARREADY,
s_axi_CRTL_BUS_RDATA => s_axi_CRTL_BUS_RDATA,
s_axi_CRTL_BUS_RRESP => s_axi_CRTL_BUS_RRESP,
s_axi_CRTL_BUS_RVALID => s_axi_CRTL_BUS_RVALID,
s_axi_CRTL_BUS_RREADY => s_axi_CRTL_BUS_RREADY,
s_axi_KERNEL_BUS_AWADDR => s_axi_KERNEL_BUS_AWADDR,
s_axi_KERNEL_BUS_AWVALID => s_axi_KERNEL_BUS_AWVALID,
s_axi_KERNEL_BUS_AWREADY => s_axi_KERNEL_BUS_AWREADY,
s_axi_KERNEL_BUS_WDATA => s_axi_KERNEL_BUS_WDATA,
s_axi_KERNEL_BUS_WSTRB => s_axi_KERNEL_BUS_WSTRB,
s_axi_KERNEL_BUS_WVALID => s_axi_KERNEL_BUS_WVALID,
s_axi_KERNEL_BUS_WREADY => s_axi_KERNEL_BUS_WREADY,
s_axi_KERNEL_BUS_BRESP => s_axi_KERNEL_BUS_BRESP,
s_axi_KERNEL_BUS_BVALID => s_axi_KERNEL_BUS_BVALID,
s_axi_KERNEL_BUS_BREADY => s_axi_KERNEL_BUS_BREADY,
s_axi_KERNEL_BUS_ARADDR => s_axi_KERNEL_BUS_ARADDR,
s_axi_KERNEL_BUS_ARVALID => s_axi_KERNEL_BUS_ARVALID,
s_axi_KERNEL_BUS_ARREADY => s_axi_KERNEL_BUS_ARREADY,
s_axi_KERNEL_BUS_RDATA => s_axi_KERNEL_BUS_RDATA,
s_axi_KERNEL_BUS_RRESP => s_axi_KERNEL_BUS_RRESP,
s_axi_KERNEL_BUS_RVALID => s_axi_KERNEL_BUS_RVALID,
s_axi_KERNEL_BUS_RREADY => s_axi_KERNEL_BUS_RREADY,
ap_clk => ap_clk,
ap_rst_n => ap_rst_n,
interrupt => interrupt,
inStream_TVALID => inStream_TVALID,
inStream_TREADY => inStream_TREADY,
inStream_TDATA => inStream_TDATA,
inStream_TDEST => inStream_TDEST,
inStream_TKEEP => inStream_TKEEP,
inStream_TSTRB => inStream_TSTRB,
inStream_TUSER => inStream_TUSER,
inStream_TLAST => inStream_TLAST,
inStream_TID => inStream_TID,
outStream_TVALID => outStream_TVALID,
outStream_TREADY => outStream_TREADY,
outStream_TDATA => outStream_TDATA,
outStream_TDEST => outStream_TDEST,
outStream_TKEEP => outStream_TKEEP,
outStream_TSTRB => outStream_TSTRB,
outStream_TUSER => outStream_TUSER,
outStream_TLAST => outStream_TLAST,
outStream_TID => outStream_TID
);
END design_1_doImgProc_0_2_arch;
|
-- -------------------------------------------------------------
--
-- File Name: hdl_prj/hdlsrc/OFDM_transmitter/RADIX22FFT_SDNF2_2_block6.vhd
-- Created: 2017-03-27 15:50:06
--
-- Generated by MATLAB 9.1 and HDL Coder 3.9
--
-- -------------------------------------------------------------
-- -------------------------------------------------------------
--
-- Module: RADIX22FFT_SDNF2_2_block6
-- Source Path: OFDM_transmitter/IFFT HDL Optimized/RADIX22FFT_SDNF2_2
-- Hierarchy Level: 2
--
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY RADIX22FFT_SDNF2_2_block6 IS
PORT( clk : IN std_logic;
reset : IN std_logic;
enb_1_16_0 : IN std_logic;
rotate_15 : IN std_logic; -- ufix1
dout_8_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_8_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_16_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_16_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_1_vld : IN std_logic;
softReset : IN std_logic;
dout_15_re : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_15_im : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_16_re_1 : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_16_im_1 : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_2_vld : OUT std_logic
);
END RADIX22FFT_SDNF2_2_block6;
ARCHITECTURE rtl OF RADIX22FFT_SDNF2_2_block6 IS
-- Signals
SIGNAL dout_8_re_signed : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL dout_8_im_signed : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL dout_16_re_signed : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL dout_16_im_signed : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL Radix22ButterflyG2_NF_din_vld_dly : std_logic;
SIGNAL Radix22ButterflyG2_NF_btf1_re_reg : signed(16 DOWNTO 0); -- sfix17
SIGNAL Radix22ButterflyG2_NF_btf1_im_reg : signed(16 DOWNTO 0); -- sfix17
SIGNAL Radix22ButterflyG2_NF_btf2_re_reg : signed(16 DOWNTO 0); -- sfix17
SIGNAL Radix22ButterflyG2_NF_btf2_im_reg : signed(16 DOWNTO 0); -- sfix17
SIGNAL Radix22ButterflyG2_NF_din_vld_dly_next : std_logic;
SIGNAL Radix22ButterflyG2_NF_btf1_re_reg_next : signed(16 DOWNTO 0); -- sfix17_En13
SIGNAL Radix22ButterflyG2_NF_btf1_im_reg_next : signed(16 DOWNTO 0); -- sfix17_En13
SIGNAL Radix22ButterflyG2_NF_btf2_re_reg_next : signed(16 DOWNTO 0); -- sfix17_En13
SIGNAL Radix22ButterflyG2_NF_btf2_im_reg_next : signed(16 DOWNTO 0); -- sfix17_En13
SIGNAL dout_15_re_tmp : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL dout_15_im_tmp : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL dout_16_re_tmp : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL dout_16_im_tmp : signed(15 DOWNTO 0); -- sfix16_En13
BEGIN
dout_8_re_signed <= signed(dout_8_re);
dout_8_im_signed <= signed(dout_8_im);
dout_16_re_signed <= signed(dout_16_re);
dout_16_im_signed <= signed(dout_16_im);
-- Radix22ButterflyG2_NF
Radix22ButterflyG2_NF_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
Radix22ButterflyG2_NF_din_vld_dly <= '0';
Radix22ButterflyG2_NF_btf1_re_reg <= to_signed(16#00000#, 17);
Radix22ButterflyG2_NF_btf1_im_reg <= to_signed(16#00000#, 17);
Radix22ButterflyG2_NF_btf2_re_reg <= to_signed(16#00000#, 17);
Radix22ButterflyG2_NF_btf2_im_reg <= to_signed(16#00000#, 17);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
Radix22ButterflyG2_NF_din_vld_dly <= Radix22ButterflyG2_NF_din_vld_dly_next;
Radix22ButterflyG2_NF_btf1_re_reg <= Radix22ButterflyG2_NF_btf1_re_reg_next;
Radix22ButterflyG2_NF_btf1_im_reg <= Radix22ButterflyG2_NF_btf1_im_reg_next;
Radix22ButterflyG2_NF_btf2_re_reg <= Radix22ButterflyG2_NF_btf2_re_reg_next;
Radix22ButterflyG2_NF_btf2_im_reg <= Radix22ButterflyG2_NF_btf2_im_reg_next;
END IF;
END IF;
END PROCESS Radix22ButterflyG2_NF_process;
Radix22ButterflyG2_NF_output : PROCESS (Radix22ButterflyG2_NF_din_vld_dly, Radix22ButterflyG2_NF_btf1_re_reg,
Radix22ButterflyG2_NF_btf1_im_reg, Radix22ButterflyG2_NF_btf2_re_reg,
Radix22ButterflyG2_NF_btf2_im_reg, dout_8_re_signed, dout_8_im_signed,
dout_16_re_signed, dout_16_im_signed, dout_1_vld, rotate_15)
VARIABLE add_cast : signed(16 DOWNTO 0);
VARIABLE add_cast_0 : signed(16 DOWNTO 0);
VARIABLE add_cast_1 : signed(16 DOWNTO 0);
VARIABLE add_cast_2 : signed(16 DOWNTO 0);
VARIABLE sub_cast : signed(16 DOWNTO 0);
VARIABLE sub_cast_0 : signed(16 DOWNTO 0);
VARIABLE sub_cast_1 : signed(16 DOWNTO 0);
VARIABLE sub_cast_2 : signed(16 DOWNTO 0);
VARIABLE sra_temp : signed(16 DOWNTO 0);
VARIABLE add_cast_3 : signed(16 DOWNTO 0);
VARIABLE add_cast_4 : signed(16 DOWNTO 0);
VARIABLE add_cast_5 : signed(16 DOWNTO 0);
VARIABLE add_cast_6 : signed(16 DOWNTO 0);
VARIABLE sra_temp_0 : signed(16 DOWNTO 0);
VARIABLE sub_cast_3 : signed(16 DOWNTO 0);
VARIABLE sub_cast_4 : signed(16 DOWNTO 0);
VARIABLE sub_cast_5 : signed(16 DOWNTO 0);
VARIABLE sub_cast_6 : signed(16 DOWNTO 0);
VARIABLE sra_temp_1 : signed(16 DOWNTO 0);
VARIABLE sra_temp_2 : signed(16 DOWNTO 0);
BEGIN
Radix22ButterflyG2_NF_btf1_re_reg_next <= Radix22ButterflyG2_NF_btf1_re_reg;
Radix22ButterflyG2_NF_btf1_im_reg_next <= Radix22ButterflyG2_NF_btf1_im_reg;
Radix22ButterflyG2_NF_btf2_re_reg_next <= Radix22ButterflyG2_NF_btf2_re_reg;
Radix22ButterflyG2_NF_btf2_im_reg_next <= Radix22ButterflyG2_NF_btf2_im_reg;
Radix22ButterflyG2_NF_din_vld_dly_next <= dout_1_vld;
IF rotate_15 /= '0' THEN
IF dout_1_vld = '1' THEN
add_cast_1 := resize(dout_8_re_signed, 17);
add_cast_2 := resize(dout_16_im_signed, 17);
Radix22ButterflyG2_NF_btf1_re_reg_next <= add_cast_1 + add_cast_2;
sub_cast_1 := resize(dout_8_re_signed, 17);
sub_cast_2 := resize(dout_16_im_signed, 17);
Radix22ButterflyG2_NF_btf2_re_reg_next <= sub_cast_1 - sub_cast_2;
add_cast_5 := resize(dout_8_im_signed, 17);
add_cast_6 := resize(dout_16_re_signed, 17);
Radix22ButterflyG2_NF_btf2_im_reg_next <= add_cast_5 + add_cast_6;
sub_cast_5 := resize(dout_8_im_signed, 17);
sub_cast_6 := resize(dout_16_re_signed, 17);
Radix22ButterflyG2_NF_btf1_im_reg_next <= sub_cast_5 - sub_cast_6;
END IF;
ELSIF dout_1_vld = '1' THEN
add_cast := resize(dout_8_re_signed, 17);
add_cast_0 := resize(dout_16_re_signed, 17);
Radix22ButterflyG2_NF_btf1_re_reg_next <= add_cast + add_cast_0;
sub_cast := resize(dout_8_re_signed, 17);
sub_cast_0 := resize(dout_16_re_signed, 17);
Radix22ButterflyG2_NF_btf2_re_reg_next <= sub_cast - sub_cast_0;
add_cast_3 := resize(dout_8_im_signed, 17);
add_cast_4 := resize(dout_16_im_signed, 17);
Radix22ButterflyG2_NF_btf1_im_reg_next <= add_cast_3 + add_cast_4;
sub_cast_3 := resize(dout_8_im_signed, 17);
sub_cast_4 := resize(dout_16_im_signed, 17);
Radix22ButterflyG2_NF_btf2_im_reg_next <= sub_cast_3 - sub_cast_4;
END IF;
sra_temp := SHIFT_RIGHT(Radix22ButterflyG2_NF_btf1_re_reg, 1);
dout_15_re_tmp <= sra_temp(15 DOWNTO 0);
sra_temp_0 := SHIFT_RIGHT(Radix22ButterflyG2_NF_btf1_im_reg, 1);
dout_15_im_tmp <= sra_temp_0(15 DOWNTO 0);
sra_temp_1 := SHIFT_RIGHT(Radix22ButterflyG2_NF_btf2_re_reg, 1);
dout_16_re_tmp <= sra_temp_1(15 DOWNTO 0);
sra_temp_2 := SHIFT_RIGHT(Radix22ButterflyG2_NF_btf2_im_reg, 1);
dout_16_im_tmp <= sra_temp_2(15 DOWNTO 0);
dout_2_vld <= Radix22ButterflyG2_NF_din_vld_dly;
END PROCESS Radix22ButterflyG2_NF_output;
dout_15_re <= std_logic_vector(dout_15_re_tmp);
dout_15_im <= std_logic_vector(dout_15_im_tmp);
dout_16_re_1 <= std_logic_vector(dout_16_re_tmp);
dout_16_im_1 <= std_logic_vector(dout_16_im_tmp);
END rtl;
|
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- Authors: Patrick Lehmann
-- Thomas B. Preusser
--
-- Package: Simulation constants, functions and utilities.
--
-- Description:
-- ------------------------------------
-- TODO
--
-- License:
-- =============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library PoC;
use PoC.vectors.all;
use PoC.strings.all;
use PoC.physical.all;
package simulation is
-- predefined constants to ease testvector concatenation
constant U8 : T_SLV_8 := (others => 'U');
constant U16 : T_SLV_16 := (others => 'U');
constant U24 : T_SLV_24 := (others => 'U');
constant U32 : T_SLV_32 := (others => 'U');
constant D8 : T_SLV_8 := (others => '-');
constant D16 : T_SLV_16 := (others => '-');
constant D24 : T_SLV_24 := (others => '-');
constant D32 : T_SLV_32 := (others => '-');
-- Testbench Status Management
-- ===========================================================================
-- VHDL'08: Provide a protected tSimStatus type that may be used for
-- other purposes as well. For compatibility with the VHDL'93
-- implementation, the plain procedure implementation is also
-- provided on top of a package private instance of this type.
type T_TB_STATUS is protected
-- The status is changed to failed. If a message is provided, it is
-- reported as an error.
procedure simFail(msg : in string := "");
-- If the passed condition has evaluated false, the status is marked
-- as failed. In this case, the optional message will be reported as
-- an error if provided.
procedure simAssert(cond : in boolean; msg : in string := "");
-- Prints the final status. Unless simFail() or simAssert() with a
-- false condition have been called before, a successful completion
-- will be indicated, a failure otherwise.
procedure simReport;
end protected;
type T_SIM_STATUS is protected
procedure stop;
impure function isStopped return BOOLEAN;
end protected;
-- The testbench is marked as failed. If a message is provided, it is
-- reported as an error.
procedure tbFail(msg : in string := "");
-- If the passed condition has evaluated false, the testbench is marked
-- as failed. In this case, the optional message will be reported as an
-- error if one was provided.
procedure tbAssert(cond : in boolean; msg : in string := "");
-- Prints out the overall testbench result as defined by the automated
-- testbench process. Unless tbFail() or tbAssert() with a false condition
-- have been called before, a successful completion will be reported, a
-- failure otherwise.
procedure tbPrintResult;
-- clock generation
-- ===========================================================================
subtype T_DutyCycle is REAL range 0.0 to 1.0;
procedure simStop;
impure function simIsStopped return BOOLEAN;
procedure simGenerateClock(signal Clock : out STD_LOGIC; constant Frequency : in FREQ; constant DutyCycle : T_DutyCycle := 0.5);
procedure simGenerateClock(signal Clock : out STD_LOGIC; constant Period : in TIME; constant DutyCycle : T_DutyCycle := 0.5);
-- waveform generation
-- ===========================================================================
type T_SIM_WAVEFORM_TUPLE_SL is record
Delay : TIME;
Value : STD_LOGIC;
end record;
type T_SIM_WAVEFORM_TUPLE_SLV_8 is record
Delay : TIME;
Value : T_SLV_8;
end record;
type T_SIM_WAVEFORM_TUPLE_SLV_16 is record
Delay : TIME;
Value : T_SLV_16;
end record;
type T_SIM_WAVEFORM_TUPLE_SLV_24 is record
Delay : TIME;
Value : T_SLV_24;
end record;
type T_SIM_WAVEFORM_TUPLE_SLV_32 is record
Delay : TIME;
Value : T_SLV_32;
end record;
type T_SIM_WAVEFORM_TUPLE_SLV_48 is record
Delay : TIME;
Value : T_SLV_48;
end record;
type T_SIM_WAVEFORM_TUPLE_SLV_64 is record
Delay : TIME;
Value : T_SLV_64;
end record;
type T_SIM_WAVEFORM_SL is array(NATURAL range <>) of T_SIM_WAVEFORM_TUPLE_SL;
type T_SIM_WAVEFORM_SLV_8 is array(NATURAL range <>) of T_SIM_WAVEFORM_TUPLE_SLV_8;
type T_SIM_WAVEFORM_SLV_16 is array(NATURAL range <>) of T_SIM_WAVEFORM_TUPLE_SLV_16;
type T_SIM_WAVEFORM_SLV_24 is array(NATURAL range <>) of T_SIM_WAVEFORM_TUPLE_SLV_24;
type T_SIM_WAVEFORM_SLV_32 is array(NATURAL range <>) of T_SIM_WAVEFORM_TUPLE_SLV_32;
type T_SIM_WAVEFORM_SLV_48 is array(NATURAL range <>) of T_SIM_WAVEFORM_TUPLE_SLV_48;
type T_SIM_WAVEFORM_SLV_64 is array(NATURAL range <>) of T_SIM_WAVEFORM_TUPLE_SLV_64;
procedure simGenerateWaveform(signal Wave : out BOOLEAN; Waveform: T_TIMEVEC; InitialValue : BOOLEAN);
procedure simGenerateWaveform(signal Wave : out STD_LOGIC; Waveform: T_TIMEVEC; InitialValue : STD_LOGIC := '0');
procedure simGenerateWaveform(signal Wave : out STD_LOGIC; Waveform: T_SIM_WAVEFORM_SL; InitialValue : STD_LOGIC := '0');
procedure simGenerateWaveform(signal Wave : out T_SLV_8; Waveform: T_SIM_WAVEFORM_SLV_8; InitialValue : T_SLV_8);
procedure simGenerateWaveform(signal Wave : out T_SLV_16; Waveform: T_SIM_WAVEFORM_SLV_16; InitialValue : T_SLV_16);
procedure simGenerateWaveform(signal Wave : out T_SLV_24; Waveform: T_SIM_WAVEFORM_SLV_24; InitialValue : T_SLV_24);
procedure simGenerateWaveform(signal Wave : out T_SLV_32; Waveform: T_SIM_WAVEFORM_SLV_32; InitialValue : T_SLV_32);
procedure simGenerateWaveform(signal Wave : out T_SLV_48; Waveform: T_SIM_WAVEFORM_SLV_48; InitialValue : T_SLV_48);
procedure simGenerateWaveform(signal Wave : out T_SLV_64; Waveform: T_SIM_WAVEFORM_SLV_64; InitialValue : T_SLV_64);
function simGenerateWaveform_Reset(constant Pause : TIME := 0 ns; ResetPulse : TIME := 10 ns) return T_TIMEVEC;
end;
use std.TextIO.all;
package body simulation is
-- Testbench Status Management
-- ===========================================================================
type T_TB_STATUS is protected body
-- Internal state variable to log a failure condition for final reporting.
-- Once de-asserted, this variable will never return to a value of true.
variable pass : boolean := true;
procedure simFail(msg : in string := "") is
begin
if msg'length > 0 then
report msg severity error;
end if;
pass := false;
end;
procedure simAssert(cond : in boolean; msg : in string := "") is
begin
if not cond then
simFail(msg);
end if;
end;
procedure simReport is
variable l : line;
begin
write(l, string'("SIMULATION RESULT = "));
if pass then
write(l, string'("PASSED"));
else
write(l, string'("FAILED"));
end if;
writeline(output, l);
end;
end protected body;
type T_SIM_STATUS is protected body
variable stopped : BOOLEAN := FALSE;
procedure stop is
begin
stopped := TRUE;
end procedure;
impure function isStopped return BOOLEAN is
begin
return stopped;
end function;
end protected body;
-- The default global tSimStatus object.
shared variable tbStatus : T_TB_STATUS;
shared variable simStatus : T_SIM_STATUS;
-- legacy procedures
-- ===========================================================================
procedure tbFail(msg : in string := "") is
begin
tbStatus.simFail(msg);
end;
procedure tbAssert(cond : in boolean; msg : in string := "") is
begin
tbStatus.simAssert(cond, msg);
end;
procedure tbPrintResult is
begin
tbStatus.simReport;
end procedure;
-- clock generation
-- ===========================================================================
procedure simStop is
begin
simStatus.stop;
end procedure;
impure function simIsStopped return BOOLEAN is
begin
return simStatus.isStopped;
end function;
procedure simGenerateClock(signal Clock : out STD_LOGIC; constant Frequency : in FREQ; constant DutyCycle : T_DutyCycle := 0.5) is
constant Period : TIME := to_time(Frequency);
begin
simGenerateClock(Clock, Period, DutyCycle);
end procedure;
procedure simGenerateClock(signal Clock : out STD_LOGIC; constant Period : in TIME; constant DutyCycle : T_DutyCycle := 0.5) is
constant TIME_HIGH : TIME := Period * DutyCycle;
constant TIME_LOW : TIME := Period - TIME_HIGH;
begin
Clock <= '0';
while (not simStatus.isStopped) loop
wait for TIME_LOW;
Clock <= '1';
wait for TIME_HIGH;
Clock <= '0';
end loop;
end procedure;
-- waveform generation
-- ===========================================================================
procedure simGenerateWaveform(signal Wave : out BOOLEAN; Waveform : T_TIMEVEC; InitialValue : BOOLEAN) is
variable State : BOOLEAN := InitialValue;
begin
Wave <= State;
for i in Waveform'range loop
wait for Waveform(i);
State := not State;
Wave <= State;
end loop;
end procedure;
procedure simGenerateWaveform(signal Wave : out STD_LOGIC; Waveform: T_TIMEVEC; InitialValue : STD_LOGIC := '0') is
variable State : STD_LOGIC := InitialValue;
begin
Wave <= State;
for i in Waveform'range loop
wait for Waveform(i);
State := not State;
Wave <= State;
end loop;
end procedure;
procedure simGenerateWaveform(signal Wave : out STD_LOGIC; Waveform: T_SIM_WAVEFORM_SL; InitialValue : STD_LOGIC := '0') is
begin
Wave <= InitialValue;
for i in Waveform'range loop
wait for Waveform(i).Delay;
Wave <= Waveform(i).Value;
end loop;
end procedure;
procedure simGenerateWaveform(signal Wave : out T_SLV_8; Waveform: T_SIM_WAVEFORM_SLV_8; InitialValue : T_SLV_8) is
begin
Wave <= InitialValue;
for i in Waveform'range loop
wait for Waveform(i).Delay;
Wave <= Waveform(i).Value;
end loop;
end procedure;
procedure simGenerateWaveform(signal Wave : out T_SLV_16; Waveform: T_SIM_WAVEFORM_SLV_16; InitialValue : T_SLV_16) is
begin
Wave <= InitialValue;
for i in Waveform'range loop
wait for Waveform(i).Delay;
Wave <= Waveform(i).Value;
end loop;
end procedure;
procedure simGenerateWaveform(signal Wave : out T_SLV_24; Waveform: T_SIM_WAVEFORM_SLV_24; InitialValue : T_SLV_24) is
begin
Wave <= InitialValue;
for i in Waveform'range loop
wait for Waveform(i).Delay;
Wave <= Waveform(i).Value;
end loop;
end procedure;
procedure simGenerateWaveform(signal Wave : out T_SLV_32; Waveform: T_SIM_WAVEFORM_SLV_32; InitialValue : T_SLV_32) is
begin
Wave <= InitialValue;
for i in Waveform'range loop
wait for Waveform(i).Delay;
Wave <= Waveform(i).Value;
end loop;
end procedure;
procedure simGenerateWaveform(signal Wave : out T_SLV_48; Waveform: T_SIM_WAVEFORM_SLV_48; InitialValue : T_SLV_48) is
begin
Wave <= InitialValue;
for i in Waveform'range loop
wait for Waveform(i).Delay;
Wave <= Waveform(i).Value;
end loop;
end procedure;
procedure simGenerateWaveform(signal Wave : out T_SLV_64; Waveform: T_SIM_WAVEFORM_SLV_64; InitialValue : T_SLV_64) is
begin
Wave <= InitialValue;
for i in Waveform'range loop
wait for Waveform(i).Delay;
Wave <= Waveform(i).Value;
end loop;
end procedure;
function simGenerateWaveform_Reset(constant Pause : TIME := 0 ns; ResetPulse : TIME := 10 ns) return T_TIMEVEC is
begin
return (0 => Pause, 1 => ResetPulse);
end function;
end package body;
|
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- Authors: Patrick Lehmann
-- Thomas B. Preusser
--
-- Package: Simulation constants, functions and utilities.
--
-- Description:
-- ------------------------------------
-- TODO
--
-- License:
-- =============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library PoC;
use PoC.vectors.all;
use PoC.strings.all;
use PoC.physical.all;
package simulation is
-- predefined constants to ease testvector concatenation
constant U8 : T_SLV_8 := (others => 'U');
constant U16 : T_SLV_16 := (others => 'U');
constant U24 : T_SLV_24 := (others => 'U');
constant U32 : T_SLV_32 := (others => 'U');
constant D8 : T_SLV_8 := (others => '-');
constant D16 : T_SLV_16 := (others => '-');
constant D24 : T_SLV_24 := (others => '-');
constant D32 : T_SLV_32 := (others => '-');
-- Testbench Status Management
-- ===========================================================================
-- VHDL'08: Provide a protected tSimStatus type that may be used for
-- other purposes as well. For compatibility with the VHDL'93
-- implementation, the plain procedure implementation is also
-- provided on top of a package private instance of this type.
type T_TB_STATUS is protected
-- The status is changed to failed. If a message is provided, it is
-- reported as an error.
procedure simFail(msg : in string := "");
-- If the passed condition has evaluated false, the status is marked
-- as failed. In this case, the optional message will be reported as
-- an error if provided.
procedure simAssert(cond : in boolean; msg : in string := "");
-- Prints the final status. Unless simFail() or simAssert() with a
-- false condition have been called before, a successful completion
-- will be indicated, a failure otherwise.
procedure simReport;
end protected;
type T_SIM_STATUS is protected
procedure stop;
impure function isStopped return BOOLEAN;
end protected;
-- The testbench is marked as failed. If a message is provided, it is
-- reported as an error.
procedure tbFail(msg : in string := "");
-- If the passed condition has evaluated false, the testbench is marked
-- as failed. In this case, the optional message will be reported as an
-- error if one was provided.
procedure tbAssert(cond : in boolean; msg : in string := "");
-- Prints out the overall testbench result as defined by the automated
-- testbench process. Unless tbFail() or tbAssert() with a false condition
-- have been called before, a successful completion will be reported, a
-- failure otherwise.
procedure tbPrintResult;
-- clock generation
-- ===========================================================================
subtype T_DutyCycle is REAL range 0.0 to 1.0;
procedure simStop;
impure function simIsStopped return BOOLEAN;
procedure simGenerateClock(signal Clock : out STD_LOGIC; constant Frequency : in FREQ; constant DutyCycle : T_DutyCycle := 0.5);
procedure simGenerateClock(signal Clock : out STD_LOGIC; constant Period : in TIME; constant DutyCycle : T_DutyCycle := 0.5);
-- waveform generation
-- ===========================================================================
type T_SIM_WAVEFORM_TUPLE_SL is record
Delay : TIME;
Value : STD_LOGIC;
end record;
type T_SIM_WAVEFORM_TUPLE_SLV_8 is record
Delay : TIME;
Value : T_SLV_8;
end record;
type T_SIM_WAVEFORM_TUPLE_SLV_16 is record
Delay : TIME;
Value : T_SLV_16;
end record;
type T_SIM_WAVEFORM_TUPLE_SLV_24 is record
Delay : TIME;
Value : T_SLV_24;
end record;
type T_SIM_WAVEFORM_TUPLE_SLV_32 is record
Delay : TIME;
Value : T_SLV_32;
end record;
type T_SIM_WAVEFORM_TUPLE_SLV_48 is record
Delay : TIME;
Value : T_SLV_48;
end record;
type T_SIM_WAVEFORM_TUPLE_SLV_64 is record
Delay : TIME;
Value : T_SLV_64;
end record;
type T_SIM_WAVEFORM_SL is array(NATURAL range <>) of T_SIM_WAVEFORM_TUPLE_SL;
type T_SIM_WAVEFORM_SLV_8 is array(NATURAL range <>) of T_SIM_WAVEFORM_TUPLE_SLV_8;
type T_SIM_WAVEFORM_SLV_16 is array(NATURAL range <>) of T_SIM_WAVEFORM_TUPLE_SLV_16;
type T_SIM_WAVEFORM_SLV_24 is array(NATURAL range <>) of T_SIM_WAVEFORM_TUPLE_SLV_24;
type T_SIM_WAVEFORM_SLV_32 is array(NATURAL range <>) of T_SIM_WAVEFORM_TUPLE_SLV_32;
type T_SIM_WAVEFORM_SLV_48 is array(NATURAL range <>) of T_SIM_WAVEFORM_TUPLE_SLV_48;
type T_SIM_WAVEFORM_SLV_64 is array(NATURAL range <>) of T_SIM_WAVEFORM_TUPLE_SLV_64;
procedure simGenerateWaveform(signal Wave : out BOOLEAN; Waveform: T_TIMEVEC; InitialValue : BOOLEAN);
procedure simGenerateWaveform(signal Wave : out STD_LOGIC; Waveform: T_TIMEVEC; InitialValue : STD_LOGIC := '0');
procedure simGenerateWaveform(signal Wave : out STD_LOGIC; Waveform: T_SIM_WAVEFORM_SL; InitialValue : STD_LOGIC := '0');
procedure simGenerateWaveform(signal Wave : out T_SLV_8; Waveform: T_SIM_WAVEFORM_SLV_8; InitialValue : T_SLV_8);
procedure simGenerateWaveform(signal Wave : out T_SLV_16; Waveform: T_SIM_WAVEFORM_SLV_16; InitialValue : T_SLV_16);
procedure simGenerateWaveform(signal Wave : out T_SLV_24; Waveform: T_SIM_WAVEFORM_SLV_24; InitialValue : T_SLV_24);
procedure simGenerateWaveform(signal Wave : out T_SLV_32; Waveform: T_SIM_WAVEFORM_SLV_32; InitialValue : T_SLV_32);
procedure simGenerateWaveform(signal Wave : out T_SLV_48; Waveform: T_SIM_WAVEFORM_SLV_48; InitialValue : T_SLV_48);
procedure simGenerateWaveform(signal Wave : out T_SLV_64; Waveform: T_SIM_WAVEFORM_SLV_64; InitialValue : T_SLV_64);
function simGenerateWaveform_Reset(constant Pause : TIME := 0 ns; ResetPulse : TIME := 10 ns) return T_TIMEVEC;
end;
use std.TextIO.all;
package body simulation is
-- Testbench Status Management
-- ===========================================================================
type T_TB_STATUS is protected body
-- Internal state variable to log a failure condition for final reporting.
-- Once de-asserted, this variable will never return to a value of true.
variable pass : boolean := true;
procedure simFail(msg : in string := "") is
begin
if msg'length > 0 then
report msg severity error;
end if;
pass := false;
end;
procedure simAssert(cond : in boolean; msg : in string := "") is
begin
if not cond then
simFail(msg);
end if;
end;
procedure simReport is
variable l : line;
begin
write(l, string'("SIMULATION RESULT = "));
if pass then
write(l, string'("PASSED"));
else
write(l, string'("FAILED"));
end if;
writeline(output, l);
end;
end protected body;
type T_SIM_STATUS is protected body
variable stopped : BOOLEAN := FALSE;
procedure stop is
begin
stopped := TRUE;
end procedure;
impure function isStopped return BOOLEAN is
begin
return stopped;
end function;
end protected body;
-- The default global tSimStatus object.
shared variable tbStatus : T_TB_STATUS;
shared variable simStatus : T_SIM_STATUS;
-- legacy procedures
-- ===========================================================================
procedure tbFail(msg : in string := "") is
begin
tbStatus.simFail(msg);
end;
procedure tbAssert(cond : in boolean; msg : in string := "") is
begin
tbStatus.simAssert(cond, msg);
end;
procedure tbPrintResult is
begin
tbStatus.simReport;
end procedure;
-- clock generation
-- ===========================================================================
procedure simStop is
begin
simStatus.stop;
end procedure;
impure function simIsStopped return BOOLEAN is
begin
return simStatus.isStopped;
end function;
procedure simGenerateClock(signal Clock : out STD_LOGIC; constant Frequency : in FREQ; constant DutyCycle : T_DutyCycle := 0.5) is
constant Period : TIME := to_time(Frequency);
begin
simGenerateClock(Clock, Period, DutyCycle);
end procedure;
procedure simGenerateClock(signal Clock : out STD_LOGIC; constant Period : in TIME; constant DutyCycle : T_DutyCycle := 0.5) is
constant TIME_HIGH : TIME := Period * DutyCycle;
constant TIME_LOW : TIME := Period - TIME_HIGH;
begin
Clock <= '0';
while (not simStatus.isStopped) loop
wait for TIME_LOW;
Clock <= '1';
wait for TIME_HIGH;
Clock <= '0';
end loop;
end procedure;
-- waveform generation
-- ===========================================================================
procedure simGenerateWaveform(signal Wave : out BOOLEAN; Waveform : T_TIMEVEC; InitialValue : BOOLEAN) is
variable State : BOOLEAN := InitialValue;
begin
Wave <= State;
for i in Waveform'range loop
wait for Waveform(i);
State := not State;
Wave <= State;
end loop;
end procedure;
procedure simGenerateWaveform(signal Wave : out STD_LOGIC; Waveform: T_TIMEVEC; InitialValue : STD_LOGIC := '0') is
variable State : STD_LOGIC := InitialValue;
begin
Wave <= State;
for i in Waveform'range loop
wait for Waveform(i);
State := not State;
Wave <= State;
end loop;
end procedure;
procedure simGenerateWaveform(signal Wave : out STD_LOGIC; Waveform: T_SIM_WAVEFORM_SL; InitialValue : STD_LOGIC := '0') is
begin
Wave <= InitialValue;
for i in Waveform'range loop
wait for Waveform(i).Delay;
Wave <= Waveform(i).Value;
end loop;
end procedure;
procedure simGenerateWaveform(signal Wave : out T_SLV_8; Waveform: T_SIM_WAVEFORM_SLV_8; InitialValue : T_SLV_8) is
begin
Wave <= InitialValue;
for i in Waveform'range loop
wait for Waveform(i).Delay;
Wave <= Waveform(i).Value;
end loop;
end procedure;
procedure simGenerateWaveform(signal Wave : out T_SLV_16; Waveform: T_SIM_WAVEFORM_SLV_16; InitialValue : T_SLV_16) is
begin
Wave <= InitialValue;
for i in Waveform'range loop
wait for Waveform(i).Delay;
Wave <= Waveform(i).Value;
end loop;
end procedure;
procedure simGenerateWaveform(signal Wave : out T_SLV_24; Waveform: T_SIM_WAVEFORM_SLV_24; InitialValue : T_SLV_24) is
begin
Wave <= InitialValue;
for i in Waveform'range loop
wait for Waveform(i).Delay;
Wave <= Waveform(i).Value;
end loop;
end procedure;
procedure simGenerateWaveform(signal Wave : out T_SLV_32; Waveform: T_SIM_WAVEFORM_SLV_32; InitialValue : T_SLV_32) is
begin
Wave <= InitialValue;
for i in Waveform'range loop
wait for Waveform(i).Delay;
Wave <= Waveform(i).Value;
end loop;
end procedure;
procedure simGenerateWaveform(signal Wave : out T_SLV_48; Waveform: T_SIM_WAVEFORM_SLV_48; InitialValue : T_SLV_48) is
begin
Wave <= InitialValue;
for i in Waveform'range loop
wait for Waveform(i).Delay;
Wave <= Waveform(i).Value;
end loop;
end procedure;
procedure simGenerateWaveform(signal Wave : out T_SLV_64; Waveform: T_SIM_WAVEFORM_SLV_64; InitialValue : T_SLV_64) is
begin
Wave <= InitialValue;
for i in Waveform'range loop
wait for Waveform(i).Delay;
Wave <= Waveform(i).Value;
end loop;
end procedure;
function simGenerateWaveform_Reset(constant Pause : TIME := 0 ns; ResetPulse : TIME := 10 ns) return T_TIMEVEC is
begin
return (0 => Pause, 1 => ResetPulse);
end function;
end package body;
|
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- Authors: Patrick Lehmann
-- Thomas B. Preusser
--
-- Package: Simulation constants, functions and utilities.
--
-- Description:
-- ------------------------------------
-- TODO
--
-- License:
-- =============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library PoC;
use PoC.vectors.all;
use PoC.strings.all;
use PoC.physical.all;
package simulation is
-- predefined constants to ease testvector concatenation
constant U8 : T_SLV_8 := (others => 'U');
constant U16 : T_SLV_16 := (others => 'U');
constant U24 : T_SLV_24 := (others => 'U');
constant U32 : T_SLV_32 := (others => 'U');
constant D8 : T_SLV_8 := (others => '-');
constant D16 : T_SLV_16 := (others => '-');
constant D24 : T_SLV_24 := (others => '-');
constant D32 : T_SLV_32 := (others => '-');
-- Testbench Status Management
-- ===========================================================================
-- VHDL'08: Provide a protected tSimStatus type that may be used for
-- other purposes as well. For compatibility with the VHDL'93
-- implementation, the plain procedure implementation is also
-- provided on top of a package private instance of this type.
type T_TB_STATUS is protected
-- The status is changed to failed. If a message is provided, it is
-- reported as an error.
procedure simFail(msg : in string := "");
-- If the passed condition has evaluated false, the status is marked
-- as failed. In this case, the optional message will be reported as
-- an error if provided.
procedure simAssert(cond : in boolean; msg : in string := "");
-- Prints the final status. Unless simFail() or simAssert() with a
-- false condition have been called before, a successful completion
-- will be indicated, a failure otherwise.
procedure simReport;
end protected;
type T_SIM_STATUS is protected
procedure stop;
impure function isStopped return BOOLEAN;
end protected;
-- The testbench is marked as failed. If a message is provided, it is
-- reported as an error.
procedure tbFail(msg : in string := "");
-- If the passed condition has evaluated false, the testbench is marked
-- as failed. In this case, the optional message will be reported as an
-- error if one was provided.
procedure tbAssert(cond : in boolean; msg : in string := "");
-- Prints out the overall testbench result as defined by the automated
-- testbench process. Unless tbFail() or tbAssert() with a false condition
-- have been called before, a successful completion will be reported, a
-- failure otherwise.
procedure tbPrintResult;
-- clock generation
-- ===========================================================================
subtype T_DutyCycle is REAL range 0.0 to 1.0;
procedure simStop;
impure function simIsStopped return BOOLEAN;
procedure simGenerateClock(signal Clock : out STD_LOGIC; constant Frequency : in FREQ; constant DutyCycle : T_DutyCycle := 0.5);
procedure simGenerateClock(signal Clock : out STD_LOGIC; constant Period : in TIME; constant DutyCycle : T_DutyCycle := 0.5);
-- waveform generation
-- ===========================================================================
type T_SIM_WAVEFORM_TUPLE_SL is record
Delay : TIME;
Value : STD_LOGIC;
end record;
type T_SIM_WAVEFORM_TUPLE_SLV_8 is record
Delay : TIME;
Value : T_SLV_8;
end record;
type T_SIM_WAVEFORM_TUPLE_SLV_16 is record
Delay : TIME;
Value : T_SLV_16;
end record;
type T_SIM_WAVEFORM_TUPLE_SLV_24 is record
Delay : TIME;
Value : T_SLV_24;
end record;
type T_SIM_WAVEFORM_TUPLE_SLV_32 is record
Delay : TIME;
Value : T_SLV_32;
end record;
type T_SIM_WAVEFORM_TUPLE_SLV_48 is record
Delay : TIME;
Value : T_SLV_48;
end record;
type T_SIM_WAVEFORM_TUPLE_SLV_64 is record
Delay : TIME;
Value : T_SLV_64;
end record;
type T_SIM_WAVEFORM_SL is array(NATURAL range <>) of T_SIM_WAVEFORM_TUPLE_SL;
type T_SIM_WAVEFORM_SLV_8 is array(NATURAL range <>) of T_SIM_WAVEFORM_TUPLE_SLV_8;
type T_SIM_WAVEFORM_SLV_16 is array(NATURAL range <>) of T_SIM_WAVEFORM_TUPLE_SLV_16;
type T_SIM_WAVEFORM_SLV_24 is array(NATURAL range <>) of T_SIM_WAVEFORM_TUPLE_SLV_24;
type T_SIM_WAVEFORM_SLV_32 is array(NATURAL range <>) of T_SIM_WAVEFORM_TUPLE_SLV_32;
type T_SIM_WAVEFORM_SLV_48 is array(NATURAL range <>) of T_SIM_WAVEFORM_TUPLE_SLV_48;
type T_SIM_WAVEFORM_SLV_64 is array(NATURAL range <>) of T_SIM_WAVEFORM_TUPLE_SLV_64;
procedure simGenerateWaveform(signal Wave : out BOOLEAN; Waveform: T_TIMEVEC; InitialValue : BOOLEAN);
procedure simGenerateWaveform(signal Wave : out STD_LOGIC; Waveform: T_TIMEVEC; InitialValue : STD_LOGIC := '0');
procedure simGenerateWaveform(signal Wave : out STD_LOGIC; Waveform: T_SIM_WAVEFORM_SL; InitialValue : STD_LOGIC := '0');
procedure simGenerateWaveform(signal Wave : out T_SLV_8; Waveform: T_SIM_WAVEFORM_SLV_8; InitialValue : T_SLV_8);
procedure simGenerateWaveform(signal Wave : out T_SLV_16; Waveform: T_SIM_WAVEFORM_SLV_16; InitialValue : T_SLV_16);
procedure simGenerateWaveform(signal Wave : out T_SLV_24; Waveform: T_SIM_WAVEFORM_SLV_24; InitialValue : T_SLV_24);
procedure simGenerateWaveform(signal Wave : out T_SLV_32; Waveform: T_SIM_WAVEFORM_SLV_32; InitialValue : T_SLV_32);
procedure simGenerateWaveform(signal Wave : out T_SLV_48; Waveform: T_SIM_WAVEFORM_SLV_48; InitialValue : T_SLV_48);
procedure simGenerateWaveform(signal Wave : out T_SLV_64; Waveform: T_SIM_WAVEFORM_SLV_64; InitialValue : T_SLV_64);
function simGenerateWaveform_Reset(constant Pause : TIME := 0 ns; ResetPulse : TIME := 10 ns) return T_TIMEVEC;
end;
use std.TextIO.all;
package body simulation is
-- Testbench Status Management
-- ===========================================================================
type T_TB_STATUS is protected body
-- Internal state variable to log a failure condition for final reporting.
-- Once de-asserted, this variable will never return to a value of true.
variable pass : boolean := true;
procedure simFail(msg : in string := "") is
begin
if msg'length > 0 then
report msg severity error;
end if;
pass := false;
end;
procedure simAssert(cond : in boolean; msg : in string := "") is
begin
if not cond then
simFail(msg);
end if;
end;
procedure simReport is
variable l : line;
begin
write(l, string'("SIMULATION RESULT = "));
if pass then
write(l, string'("PASSED"));
else
write(l, string'("FAILED"));
end if;
writeline(output, l);
end;
end protected body;
type T_SIM_STATUS is protected body
variable stopped : BOOLEAN := FALSE;
procedure stop is
begin
stopped := TRUE;
end procedure;
impure function isStopped return BOOLEAN is
begin
return stopped;
end function;
end protected body;
-- The default global tSimStatus object.
shared variable tbStatus : T_TB_STATUS;
shared variable simStatus : T_SIM_STATUS;
-- legacy procedures
-- ===========================================================================
procedure tbFail(msg : in string := "") is
begin
tbStatus.simFail(msg);
end;
procedure tbAssert(cond : in boolean; msg : in string := "") is
begin
tbStatus.simAssert(cond, msg);
end;
procedure tbPrintResult is
begin
tbStatus.simReport;
end procedure;
-- clock generation
-- ===========================================================================
procedure simStop is
begin
simStatus.stop;
end procedure;
impure function simIsStopped return BOOLEAN is
begin
return simStatus.isStopped;
end function;
procedure simGenerateClock(signal Clock : out STD_LOGIC; constant Frequency : in FREQ; constant DutyCycle : T_DutyCycle := 0.5) is
constant Period : TIME := to_time(Frequency);
begin
simGenerateClock(Clock, Period, DutyCycle);
end procedure;
procedure simGenerateClock(signal Clock : out STD_LOGIC; constant Period : in TIME; constant DutyCycle : T_DutyCycle := 0.5) is
constant TIME_HIGH : TIME := Period * DutyCycle;
constant TIME_LOW : TIME := Period - TIME_HIGH;
begin
Clock <= '0';
while (not simStatus.isStopped) loop
wait for TIME_LOW;
Clock <= '1';
wait for TIME_HIGH;
Clock <= '0';
end loop;
end procedure;
-- waveform generation
-- ===========================================================================
procedure simGenerateWaveform(signal Wave : out BOOLEAN; Waveform : T_TIMEVEC; InitialValue : BOOLEAN) is
variable State : BOOLEAN := InitialValue;
begin
Wave <= State;
for i in Waveform'range loop
wait for Waveform(i);
State := not State;
Wave <= State;
end loop;
end procedure;
procedure simGenerateWaveform(signal Wave : out STD_LOGIC; Waveform: T_TIMEVEC; InitialValue : STD_LOGIC := '0') is
variable State : STD_LOGIC := InitialValue;
begin
Wave <= State;
for i in Waveform'range loop
wait for Waveform(i);
State := not State;
Wave <= State;
end loop;
end procedure;
procedure simGenerateWaveform(signal Wave : out STD_LOGIC; Waveform: T_SIM_WAVEFORM_SL; InitialValue : STD_LOGIC := '0') is
begin
Wave <= InitialValue;
for i in Waveform'range loop
wait for Waveform(i).Delay;
Wave <= Waveform(i).Value;
end loop;
end procedure;
procedure simGenerateWaveform(signal Wave : out T_SLV_8; Waveform: T_SIM_WAVEFORM_SLV_8; InitialValue : T_SLV_8) is
begin
Wave <= InitialValue;
for i in Waveform'range loop
wait for Waveform(i).Delay;
Wave <= Waveform(i).Value;
end loop;
end procedure;
procedure simGenerateWaveform(signal Wave : out T_SLV_16; Waveform: T_SIM_WAVEFORM_SLV_16; InitialValue : T_SLV_16) is
begin
Wave <= InitialValue;
for i in Waveform'range loop
wait for Waveform(i).Delay;
Wave <= Waveform(i).Value;
end loop;
end procedure;
procedure simGenerateWaveform(signal Wave : out T_SLV_24; Waveform: T_SIM_WAVEFORM_SLV_24; InitialValue : T_SLV_24) is
begin
Wave <= InitialValue;
for i in Waveform'range loop
wait for Waveform(i).Delay;
Wave <= Waveform(i).Value;
end loop;
end procedure;
procedure simGenerateWaveform(signal Wave : out T_SLV_32; Waveform: T_SIM_WAVEFORM_SLV_32; InitialValue : T_SLV_32) is
begin
Wave <= InitialValue;
for i in Waveform'range loop
wait for Waveform(i).Delay;
Wave <= Waveform(i).Value;
end loop;
end procedure;
procedure simGenerateWaveform(signal Wave : out T_SLV_48; Waveform: T_SIM_WAVEFORM_SLV_48; InitialValue : T_SLV_48) is
begin
Wave <= InitialValue;
for i in Waveform'range loop
wait for Waveform(i).Delay;
Wave <= Waveform(i).Value;
end loop;
end procedure;
procedure simGenerateWaveform(signal Wave : out T_SLV_64; Waveform: T_SIM_WAVEFORM_SLV_64; InitialValue : T_SLV_64) is
begin
Wave <= InitialValue;
for i in Waveform'range loop
wait for Waveform(i).Delay;
Wave <= Waveform(i).Value;
end loop;
end procedure;
function simGenerateWaveform_Reset(constant Pause : TIME := 0 ns; ResetPulse : TIME := 10 ns) return T_TIMEVEC is
begin
return (0 => Pause, 1 => ResetPulse);
end function;
end package body;
|
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- Authors: Patrick Lehmann
-- Thomas B. Preusser
--
-- Package: Simulation constants, functions and utilities.
--
-- Description:
-- ------------------------------------
-- TODO
--
-- License:
-- =============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library PoC;
use PoC.vectors.all;
use PoC.strings.all;
use PoC.physical.all;
package simulation is
-- predefined constants to ease testvector concatenation
constant U8 : T_SLV_8 := (others => 'U');
constant U16 : T_SLV_16 := (others => 'U');
constant U24 : T_SLV_24 := (others => 'U');
constant U32 : T_SLV_32 := (others => 'U');
constant D8 : T_SLV_8 := (others => '-');
constant D16 : T_SLV_16 := (others => '-');
constant D24 : T_SLV_24 := (others => '-');
constant D32 : T_SLV_32 := (others => '-');
-- Testbench Status Management
-- ===========================================================================
-- VHDL'08: Provide a protected tSimStatus type that may be used for
-- other purposes as well. For compatibility with the VHDL'93
-- implementation, the plain procedure implementation is also
-- provided on top of a package private instance of this type.
type T_TB_STATUS is protected
-- The status is changed to failed. If a message is provided, it is
-- reported as an error.
procedure simFail(msg : in string := "");
-- If the passed condition has evaluated false, the status is marked
-- as failed. In this case, the optional message will be reported as
-- an error if provided.
procedure simAssert(cond : in boolean; msg : in string := "");
-- Prints the final status. Unless simFail() or simAssert() with a
-- false condition have been called before, a successful completion
-- will be indicated, a failure otherwise.
procedure simReport;
end protected;
type T_SIM_STATUS is protected
procedure stop;
impure function isStopped return BOOLEAN;
end protected;
-- The testbench is marked as failed. If a message is provided, it is
-- reported as an error.
procedure tbFail(msg : in string := "");
-- If the passed condition has evaluated false, the testbench is marked
-- as failed. In this case, the optional message will be reported as an
-- error if one was provided.
procedure tbAssert(cond : in boolean; msg : in string := "");
-- Prints out the overall testbench result as defined by the automated
-- testbench process. Unless tbFail() or tbAssert() with a false condition
-- have been called before, a successful completion will be reported, a
-- failure otherwise.
procedure tbPrintResult;
-- clock generation
-- ===========================================================================
subtype T_DutyCycle is REAL range 0.0 to 1.0;
procedure simStop;
impure function simIsStopped return BOOLEAN;
procedure simGenerateClock(signal Clock : out STD_LOGIC; constant Frequency : in FREQ; constant DutyCycle : T_DutyCycle := 0.5);
procedure simGenerateClock(signal Clock : out STD_LOGIC; constant Period : in TIME; constant DutyCycle : T_DutyCycle := 0.5);
-- waveform generation
-- ===========================================================================
type T_SIM_WAVEFORM_TUPLE_SL is record
Delay : TIME;
Value : STD_LOGIC;
end record;
type T_SIM_WAVEFORM_TUPLE_SLV_8 is record
Delay : TIME;
Value : T_SLV_8;
end record;
type T_SIM_WAVEFORM_TUPLE_SLV_16 is record
Delay : TIME;
Value : T_SLV_16;
end record;
type T_SIM_WAVEFORM_TUPLE_SLV_24 is record
Delay : TIME;
Value : T_SLV_24;
end record;
type T_SIM_WAVEFORM_TUPLE_SLV_32 is record
Delay : TIME;
Value : T_SLV_32;
end record;
type T_SIM_WAVEFORM_TUPLE_SLV_48 is record
Delay : TIME;
Value : T_SLV_48;
end record;
type T_SIM_WAVEFORM_TUPLE_SLV_64 is record
Delay : TIME;
Value : T_SLV_64;
end record;
type T_SIM_WAVEFORM_SL is array(NATURAL range <>) of T_SIM_WAVEFORM_TUPLE_SL;
type T_SIM_WAVEFORM_SLV_8 is array(NATURAL range <>) of T_SIM_WAVEFORM_TUPLE_SLV_8;
type T_SIM_WAVEFORM_SLV_16 is array(NATURAL range <>) of T_SIM_WAVEFORM_TUPLE_SLV_16;
type T_SIM_WAVEFORM_SLV_24 is array(NATURAL range <>) of T_SIM_WAVEFORM_TUPLE_SLV_24;
type T_SIM_WAVEFORM_SLV_32 is array(NATURAL range <>) of T_SIM_WAVEFORM_TUPLE_SLV_32;
type T_SIM_WAVEFORM_SLV_48 is array(NATURAL range <>) of T_SIM_WAVEFORM_TUPLE_SLV_48;
type T_SIM_WAVEFORM_SLV_64 is array(NATURAL range <>) of T_SIM_WAVEFORM_TUPLE_SLV_64;
procedure simGenerateWaveform(signal Wave : out BOOLEAN; Waveform: T_TIMEVEC; InitialValue : BOOLEAN);
procedure simGenerateWaveform(signal Wave : out STD_LOGIC; Waveform: T_TIMEVEC; InitialValue : STD_LOGIC := '0');
procedure simGenerateWaveform(signal Wave : out STD_LOGIC; Waveform: T_SIM_WAVEFORM_SL; InitialValue : STD_LOGIC := '0');
procedure simGenerateWaveform(signal Wave : out T_SLV_8; Waveform: T_SIM_WAVEFORM_SLV_8; InitialValue : T_SLV_8);
procedure simGenerateWaveform(signal Wave : out T_SLV_16; Waveform: T_SIM_WAVEFORM_SLV_16; InitialValue : T_SLV_16);
procedure simGenerateWaveform(signal Wave : out T_SLV_24; Waveform: T_SIM_WAVEFORM_SLV_24; InitialValue : T_SLV_24);
procedure simGenerateWaveform(signal Wave : out T_SLV_32; Waveform: T_SIM_WAVEFORM_SLV_32; InitialValue : T_SLV_32);
procedure simGenerateWaveform(signal Wave : out T_SLV_48; Waveform: T_SIM_WAVEFORM_SLV_48; InitialValue : T_SLV_48);
procedure simGenerateWaveform(signal Wave : out T_SLV_64; Waveform: T_SIM_WAVEFORM_SLV_64; InitialValue : T_SLV_64);
function simGenerateWaveform_Reset(constant Pause : TIME := 0 ns; ResetPulse : TIME := 10 ns) return T_TIMEVEC;
end;
use std.TextIO.all;
package body simulation is
-- Testbench Status Management
-- ===========================================================================
type T_TB_STATUS is protected body
-- Internal state variable to log a failure condition for final reporting.
-- Once de-asserted, this variable will never return to a value of true.
variable pass : boolean := true;
procedure simFail(msg : in string := "") is
begin
if msg'length > 0 then
report msg severity error;
end if;
pass := false;
end;
procedure simAssert(cond : in boolean; msg : in string := "") is
begin
if not cond then
simFail(msg);
end if;
end;
procedure simReport is
variable l : line;
begin
write(l, string'("SIMULATION RESULT = "));
if pass then
write(l, string'("PASSED"));
else
write(l, string'("FAILED"));
end if;
writeline(output, l);
end;
end protected body;
type T_SIM_STATUS is protected body
variable stopped : BOOLEAN := FALSE;
procedure stop is
begin
stopped := TRUE;
end procedure;
impure function isStopped return BOOLEAN is
begin
return stopped;
end function;
end protected body;
-- The default global tSimStatus object.
shared variable tbStatus : T_TB_STATUS;
shared variable simStatus : T_SIM_STATUS;
-- legacy procedures
-- ===========================================================================
procedure tbFail(msg : in string := "") is
begin
tbStatus.simFail(msg);
end;
procedure tbAssert(cond : in boolean; msg : in string := "") is
begin
tbStatus.simAssert(cond, msg);
end;
procedure tbPrintResult is
begin
tbStatus.simReport;
end procedure;
-- clock generation
-- ===========================================================================
procedure simStop is
begin
simStatus.stop;
end procedure;
impure function simIsStopped return BOOLEAN is
begin
return simStatus.isStopped;
end function;
procedure simGenerateClock(signal Clock : out STD_LOGIC; constant Frequency : in FREQ; constant DutyCycle : T_DutyCycle := 0.5) is
constant Period : TIME := to_time(Frequency);
begin
simGenerateClock(Clock, Period, DutyCycle);
end procedure;
procedure simGenerateClock(signal Clock : out STD_LOGIC; constant Period : in TIME; constant DutyCycle : T_DutyCycle := 0.5) is
constant TIME_HIGH : TIME := Period * DutyCycle;
constant TIME_LOW : TIME := Period - TIME_HIGH;
begin
Clock <= '0';
while (not simStatus.isStopped) loop
wait for TIME_LOW;
Clock <= '1';
wait for TIME_HIGH;
Clock <= '0';
end loop;
end procedure;
-- waveform generation
-- ===========================================================================
procedure simGenerateWaveform(signal Wave : out BOOLEAN; Waveform : T_TIMEVEC; InitialValue : BOOLEAN) is
variable State : BOOLEAN := InitialValue;
begin
Wave <= State;
for i in Waveform'range loop
wait for Waveform(i);
State := not State;
Wave <= State;
end loop;
end procedure;
procedure simGenerateWaveform(signal Wave : out STD_LOGIC; Waveform: T_TIMEVEC; InitialValue : STD_LOGIC := '0') is
variable State : STD_LOGIC := InitialValue;
begin
Wave <= State;
for i in Waveform'range loop
wait for Waveform(i);
State := not State;
Wave <= State;
end loop;
end procedure;
procedure simGenerateWaveform(signal Wave : out STD_LOGIC; Waveform: T_SIM_WAVEFORM_SL; InitialValue : STD_LOGIC := '0') is
begin
Wave <= InitialValue;
for i in Waveform'range loop
wait for Waveform(i).Delay;
Wave <= Waveform(i).Value;
end loop;
end procedure;
procedure simGenerateWaveform(signal Wave : out T_SLV_8; Waveform: T_SIM_WAVEFORM_SLV_8; InitialValue : T_SLV_8) is
begin
Wave <= InitialValue;
for i in Waveform'range loop
wait for Waveform(i).Delay;
Wave <= Waveform(i).Value;
end loop;
end procedure;
procedure simGenerateWaveform(signal Wave : out T_SLV_16; Waveform: T_SIM_WAVEFORM_SLV_16; InitialValue : T_SLV_16) is
begin
Wave <= InitialValue;
for i in Waveform'range loop
wait for Waveform(i).Delay;
Wave <= Waveform(i).Value;
end loop;
end procedure;
procedure simGenerateWaveform(signal Wave : out T_SLV_24; Waveform: T_SIM_WAVEFORM_SLV_24; InitialValue : T_SLV_24) is
begin
Wave <= InitialValue;
for i in Waveform'range loop
wait for Waveform(i).Delay;
Wave <= Waveform(i).Value;
end loop;
end procedure;
procedure simGenerateWaveform(signal Wave : out T_SLV_32; Waveform: T_SIM_WAVEFORM_SLV_32; InitialValue : T_SLV_32) is
begin
Wave <= InitialValue;
for i in Waveform'range loop
wait for Waveform(i).Delay;
Wave <= Waveform(i).Value;
end loop;
end procedure;
procedure simGenerateWaveform(signal Wave : out T_SLV_48; Waveform: T_SIM_WAVEFORM_SLV_48; InitialValue : T_SLV_48) is
begin
Wave <= InitialValue;
for i in Waveform'range loop
wait for Waveform(i).Delay;
Wave <= Waveform(i).Value;
end loop;
end procedure;
procedure simGenerateWaveform(signal Wave : out T_SLV_64; Waveform: T_SIM_WAVEFORM_SLV_64; InitialValue : T_SLV_64) is
begin
Wave <= InitialValue;
for i in Waveform'range loop
wait for Waveform(i).Delay;
Wave <= Waveform(i).Value;
end loop;
end procedure;
function simGenerateWaveform_Reset(constant Pause : TIME := 0 ns; ResetPulse : TIME := 10 ns) return T_TIMEVEC is
begin
return (0 => Pause, 1 => ResetPulse);
end function;
end package body;
|
package pack1 is
type t is (foo, bar, baz);
type p is range 0 to 100
units
one;
ten = 10 one;
end units;
end package;
use work.pack1.t;
use work.pack1.p;
package pack2 is
constant c : t := foo; -- OK
constant k : p := 5 one; -- Ok
end package;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Stimulus Generator For Single Port ROM
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: bmg_stim_gen.vhd
--
-- Description:
-- Stimulus Generation For SROM
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY REGISTER_LOGIC_SROM IS
PORT(
Q : OUT STD_LOGIC;
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
D : IN STD_LOGIC
);
END REGISTER_LOGIC_SROM;
ARCHITECTURE REGISTER_ARCH OF REGISTER_LOGIC_SROM IS
SIGNAL Q_O : STD_LOGIC :='0';
BEGIN
Q <= Q_O;
FF_BEH: PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST /= '0' ) THEN
Q_O <= '0';
ELSE
Q_O <= D;
END IF;
END IF;
END PROCESS;
END REGISTER_ARCH;
LIBRARY STD;
USE STD.TEXTIO.ALL;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
--USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY BMG_STIM_GEN IS
GENERIC ( C_ROM_SYNTH : INTEGER := 0
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
ADDRA: OUT STD_LOGIC_VECTOR(9 DOWNTO 0) := (OTHERS => '0');
DATA_IN : IN STD_LOGIC_VECTOR (31 DOWNTO 0); --OUTPUT VECTOR
STATUS : OUT STD_LOGIC:= '0'
);
END BMG_STIM_GEN;
ARCHITECTURE BEHAVIORAL OF BMG_STIM_GEN IS
FUNCTION hex_to_std_logic_vector(
hex_str : STRING;
return_width : INTEGER)
RETURN STD_LOGIC_VECTOR IS
VARIABLE tmp : STD_LOGIC_VECTOR((hex_str'LENGTH*4)+return_width-1
DOWNTO 0);
BEGIN
tmp := (OTHERS => '0');
FOR i IN 1 TO hex_str'LENGTH LOOP
CASE hex_str((hex_str'LENGTH+1)-i) IS
WHEN '0' => tmp(i*4-1 DOWNTO (i-1)*4) := "0000";
WHEN '1' => tmp(i*4-1 DOWNTO (i-1)*4) := "0001";
WHEN '2' => tmp(i*4-1 DOWNTO (i-1)*4) := "0010";
WHEN '3' => tmp(i*4-1 DOWNTO (i-1)*4) := "0011";
WHEN '4' => tmp(i*4-1 DOWNTO (i-1)*4) := "0100";
WHEN '5' => tmp(i*4-1 DOWNTO (i-1)*4) := "0101";
WHEN '6' => tmp(i*4-1 DOWNTO (i-1)*4) := "0110";
WHEN '7' => tmp(i*4-1 DOWNTO (i-1)*4) := "0111";
WHEN '8' => tmp(i*4-1 DOWNTO (i-1)*4) := "1000";
WHEN '9' => tmp(i*4-1 DOWNTO (i-1)*4) := "1001";
WHEN 'a' | 'A' => tmp(i*4-1 DOWNTO (i-1)*4) := "1010";
WHEN 'b' | 'B' => tmp(i*4-1 DOWNTO (i-1)*4) := "1011";
WHEN 'c' | 'C' => tmp(i*4-1 DOWNTO (i-1)*4) := "1100";
WHEN 'd' | 'D' => tmp(i*4-1 DOWNTO (i-1)*4) := "1101";
WHEN 'e' | 'E' => tmp(i*4-1 DOWNTO (i-1)*4) := "1110";
WHEN 'f' | 'F' => tmp(i*4-1 DOWNTO (i-1)*4) := "1111";
WHEN OTHERS => tmp(i*4-1 DOWNTO (i-1)*4) := "1111";
END CASE;
END LOOP;
RETURN tmp(return_width-1 DOWNTO 0);
END hex_to_std_logic_vector;
CONSTANT ZERO : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR_INT : STD_LOGIC_VECTOR(9 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL CHECK_READ_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL EXPECTED_DATA : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL DO_READ : STD_LOGIC := '0';
SIGNAL CHECK_DATA : STD_LOGIC := '0';
SIGNAL CHECK_DATA_R : STD_LOGIC := '0';
SIGNAL CHECK_DATA_2R : STD_LOGIC := '0';
SIGNAL DO_READ_REG: STD_LOGIC_VECTOR(4 DOWNTO 0) :=(OTHERS => '0');
CONSTANT DEFAULT_DATA : STD_LOGIC_VECTOR(31 DOWNTO 0):= hex_to_std_logic_vector("0",32);
BEGIN
SYNTH_COE: IF(C_ROM_SYNTH =0 ) GENERATE
type mem_type is array (1023 downto 0) of std_logic_vector(31 downto 0);
FUNCTION bit_to_sl(input: BIT) RETURN STD_LOGIC IS
VARIABLE temp_return : STD_LOGIC;
BEGIN
IF (input = '0') THEN
temp_return := '0';
ELSE
temp_return := '1';
END IF;
RETURN temp_return;
END bit_to_sl;
function char_to_std_logic (
char : in character)
return std_logic is
variable data : std_logic;
begin
if char = '0' then
data := '0';
elsif char = '1' then
data := '1';
elsif char = 'X' then
data := 'X';
else
assert false
report "character which is not '0', '1' or 'X'."
severity warning;
data := 'U';
end if;
return data;
end char_to_std_logic;
impure FUNCTION init_memory( C_USE_DEFAULT_DATA : INTEGER;
C_LOAD_INIT_FILE : INTEGER ;
C_INIT_FILE_NAME : STRING ;
DEFAULT_DATA : STD_LOGIC_VECTOR(31 DOWNTO 0);
width : INTEGER;
depth : INTEGER)
RETURN mem_type IS
VARIABLE init_return : mem_type := (OTHERS => (OTHERS => '0'));
FILE init_file : TEXT;
VARIABLE mem_vector : BIT_VECTOR(width-1 DOWNTO 0);
VARIABLE bitline : LINE;
variable bitsgood : boolean := true;
variable bitchar : character;
VARIABLE i : INTEGER;
VARIABLE j : INTEGER;
BEGIN
--Display output message indicating that the behavioral model is being
--initialized
ASSERT (NOT (C_USE_DEFAULT_DATA=1 OR C_LOAD_INIT_FILE=1)) REPORT " Block Memory Generator CORE Generator module loading initial data..." SEVERITY NOTE;
-- Setup the default data
-- Default data is with respect to write_port_A and may be wider
-- or narrower than init_return width. The following loops map
-- default data into the memory
IF (C_USE_DEFAULT_DATA=1) THEN
FOR i IN 0 TO depth-1 LOOP
init_return(i) := DEFAULT_DATA;
END LOOP;
END IF;
-- Read in the .mif file
-- The init data is formatted with respect to write port A dimensions.
-- The init_return vector is formatted with respect to minimum width and
-- maximum depth; the following loops map the .mif file into the memory
IF (C_LOAD_INIT_FILE=1) THEN
file_open(init_file, C_INIT_FILE_NAME, read_mode);
i := 0;
WHILE (i < depth AND NOT endfile(init_file)) LOOP
mem_vector := (OTHERS => '0');
readline(init_file, bitline);
-- read(file_buffer, mem_vector(file_buffer'LENGTH-1 DOWNTO 0));
FOR j IN 0 TO width-1 LOOP
read(bitline,bitchar,bitsgood);
init_return(i)(width-1-j) := char_to_std_logic(bitchar);
END LOOP;
i := i + 1;
END LOOP;
file_close(init_file);
END IF;
RETURN init_return;
END FUNCTION;
--***************************************************************
-- convert bit to STD_LOGIC
--***************************************************************
constant c_init : mem_type := init_memory(0,
1,
"instrmem.mif",
DEFAULT_DATA,
32,
1024);
constant rom : mem_type := c_init;
BEGIN
EXPECTED_DATA <= rom(conv_integer(unsigned(check_read_addr)));
CHECKER_RD_ADDR_GEN_INST:ENTITY work.ADDR_GEN
GENERIC MAP( C_MAX_DEPTH =>1024 )
PORT MAP(
CLK => CLK,
RST => RST,
EN => CHECK_DATA_2R,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => CHECK_READ_ADDR
);
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(CHECK_DATA_2R ='1') THEN
IF(EXPECTED_DATA = DATA_IN) THEN
STATUS<='0';
ELSE
STATUS <= '1';
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE;
-- Simulatable ROM
--Synthesizable ROM
SYNTH_CHECKER: IF(C_ROM_SYNTH = 1) GENERATE
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(CHECK_DATA_2R='1') THEN
IF(DATA_IN=DEFAULT_DATA) THEN
STATUS <= '0';
ELSE
STATUS <= '1';
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE;
READ_ADDR_INT(9 DOWNTO 0) <= READ_ADDR(9 DOWNTO 0);
ADDRA <= READ_ADDR_INT ;
CHECK_DATA <= DO_READ;
RD_ADDR_GEN_INST:ENTITY work.ADDR_GEN
GENERIC MAP( C_MAX_DEPTH => 1024 )
PORT MAP(
CLK => CLK,
RST => RST,
EN => DO_READ,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => READ_ADDR
);
RD_PROCESS: PROCESS (CLK)
BEGIN
IF (RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
DO_READ <= '0';
ELSE
DO_READ <= '1';
END IF;
END IF;
END PROCESS;
BEGIN_SHIFT_REG: FOR I IN 0 TO 4 GENERATE
BEGIN
DFF_RIGHT: IF I=0 GENERATE
BEGIN
SHIFT_INST_0: ENTITY work.REGISTER_LOGIC_SROM
PORT MAP(
Q => DO_READ_REG(0),
CLK =>CLK,
RST=>RST,
D =>DO_READ
);
END GENERATE DFF_RIGHT;
DFF_OTHERS: IF ((I>0) AND (I<=4)) GENERATE
BEGIN
SHIFT_INST: ENTITY work.REGISTER_LOGIC_SROM
PORT MAP(
Q => DO_READ_REG(I),
CLK =>CLK,
RST=>RST,
D =>DO_READ_REG(I-1)
);
END GENERATE DFF_OTHERS;
END GENERATE BEGIN_SHIFT_REG;
CHECK_DATA_REG_1: ENTITY work.REGISTER_LOGIC_SROM
PORT MAP(
Q => CHECK_DATA_2R,
CLK =>CLK,
RST=>RST,
D =>CHECK_DATA_R
);
CHECK_DATA_REG: ENTITY work.REGISTER_LOGIC_SROM
PORT MAP(
Q => CHECK_DATA_R,
CLK =>CLK,
RST=>RST,
D =>CHECK_DATA
);
END ARCHITECTURE;
|
library ieee;
use ieee.std_logic_1164.all;
entity JC is
generic (i:integer := 2);
port(
CLK: in std_logic;
RST: in std_logic;
LS: in std_logic;
Pin: in std_logic_vector(0 to 2**i-1);
Pout: out std_logic_vector(0 to 2**i-1)
);
end JC;
architecture Beh of JC is
signal sreg: std_logic_vector(0 to 2**i-1);
signal sdat: std_logic_vector(0 to 2**i-1);
Begin
Main: process (CLK, RST, sdat)
begin
if RST = '1' then
sreg <= (others => '0');
elsif rising_edge(CLK) then
sreg <= sdat;
end if;
end process;
Data: process (LS, Pin, sreg)
begin
if LS = '0' then
sdat <= Pin;
else
sdat <= not(sreg(2**i-1)) & sreg(0 to 2**i-2);
end if;
end process;
Pout <= sreg;
End Beh; |
------------------------------------------------------------------------------
---- ----
---- ZPU Exec ----
---- ----
---- http://www.opencores.org/ ----
---- ----
---- Description: ----
---- ZPU is a 32 bits small stack cpu. This is a modified version of ----
---- the zpu_small implementation. This one has a third (8-bit) port for ----
---- fetching instructions. This modification reduces the LUT size by ----
---- approximately 10% and increases the performance with 21%. ----
---- Needs external dual ported memory, plus single cycle external ----
---- program memory. It also requires a different linker script to ----
---- place the text segment on a logically different address to stick to ----
---- the single-, flat memory model programming paradigm. ----
---- ----
---- To Do: ----
---- Add a 'ready' for the external code memory ----
---- More thorough testing, cleanup code a bit more ----
---- ----
---- Author: ----
---- - Øyvind Harboe, oyvind.harboe zylin.com ----
---- - Salvador E. Tropea, salvador inti.gob.ar ----
---- - Gideon Zweijtzer, gideon.zweijtzer technolution.eu
---- ----
------------------------------------------------------------------------------
---- ----
---- Copyright (c) 2008 Øyvind Harboe <oyvind.harboe zylin.com> ----
---- Copyright (c) 2008 Salvador E. Tropea <salvador inti.gob.ar> ----
---- Copyright (c) 2008 Instituto Nacional de Tecnología Industrial ----
---- ----
---- Distributed under the BSD license ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Design unit: zpu_tiny(Behave) (Entity and architecture) ----
---- File name: zpu_tiny.vhdl ----
---- Note: None ----
---- Limitations: None known ----
---- Errors: None known ----
---- Library: work ----
---- Dependencies: ieee.std_logic_1164 ----
---- ieee.numeric_std ----
---- work.zpupkg ----
---- Target FPGA: Spartan 3E (XC3S500E-4-PQG208) ----
---- Language: VHDL ----
---- Wishbone: No ----
---- Synthesis tools: Xilinx Release 10.1.03i - xst K.39 ----
---- Simulation tools: Modelsim ----
---- Text editor: UltraEdit 11.00a+ ----
---- ----
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.zpupkg.all;
entity zpu_tiny is
generic(
g_addr_size : integer := 16; -- Total address space width (incl. I/O)
g_stack_size : integer := 12; -- Memory (stack+data) width
g_prog_size : integer := 14; -- Program size
g_dont_care : std_logic := '-'); -- Value used to fill the unsused bits, can be '-' or '0'
port(
clk_i : in std_logic; -- System Clock
reset_i : in std_logic; -- Synchronous Reset
interrupt_i : in std_logic; -- Interrupt
break_o : out std_logic; -- Breakpoint opcode executed
-- synthesis translate_off
dbg_o : out zpu_dbgo_t; -- Debug outputs (i.e. trace log)
-- synthesis translate_on
-- BRAM (stack ONLY)
a_we_o : out std_logic; -- BRAM A port Write Enable
a_addr_o : out unsigned(g_stack_size-1 downto 2):=(others => '0'); -- BRAM A Address
a_o : out unsigned(31 downto 0):=(others => '0'); -- Data to BRAM A port
a_i : in unsigned(31 downto 0); -- Data from BRAM A port
b_we_o : out std_logic; -- BRAM B port Write Enable
b_addr_o : out unsigned(g_stack_size-1 downto 2):=(others => '0'); -- BRAM B Address
b_o : out unsigned(31 downto 0):=(others => '0'); -- Data to BRAM B port
b_i : in unsigned(31 downto 0); -- Data from BRAM B port
-- memory port for text, bss, data
c_addr_o : out unsigned(g_addr_size-1 downto 0) := (others => '0');
c_i : in unsigned(c_opcode_width-1 downto 0);
c_o : out unsigned(c_opcode_width-1 downto 0);
c_we_o : out std_logic;
-- Memory mapped I/O
mem_busy_i : in std_logic;
data_i : in unsigned(31 downto 0);
data_o : out unsigned(31 downto 0);
addr_o : out unsigned(g_addr_size-1 downto 0);
write_en_o : out std_logic;
read_en_o : out std_logic);
end entity zpu_tiny;
architecture Behave of zpu_tiny is
constant c_max_addr_bit : integer:=g_addr_size-1;
-- Stack Pointer initial value: BRAM size-8
constant SP_START_1 : unsigned(g_addr_size-1 downto 0):=to_unsigned((2**g_stack_size)-8, g_addr_size);
constant SP_START : unsigned(g_stack_size-1 downto 2):=
SP_START_1(g_stack_size-1 downto 2);
constant IO_BIT : integer:=g_addr_size-1; -- Address bit to determine this is an I/O
-- Program counter
signal pc_r : unsigned(c_max_addr_bit downto 0):=(others => '0');
-- Stack pointer
signal sp_r : unsigned(g_stack_size-1 downto 2):=SP_START;
signal idim_r : std_logic:='0';
-- BRAM (text, some data, bss and stack)
-- a_r is a register for the top of the stack [SP]
-- Note: as this is a stack CPU this is a very important register.
signal a_we_r : std_logic:='0';
signal a_addr_r : unsigned(g_stack_size-1 downto 2):=(others => '0');
signal a_r : unsigned(31 downto 0):=(others => '0');
-- b_r is a register for the next value in the stack [SP+1]
signal b_we_r : std_logic:='0';
signal b_addr_r : unsigned(g_stack_size-1 downto 2):=(others => '0');
signal b_r : unsigned(31 downto 0):=(others => '0');
signal c_we_r : std_logic := '0';
signal c_en_r : std_logic := '0';
signal c_mux_r : std_logic := '0';
signal first : std_logic := '0';
signal byte_cnt : unsigned(1 downto 0) := "00";
signal byte_cnt_d : unsigned(1 downto 0) := "00";
signal posted_wr_a : std_logic;
-- State machine.
type state_t is (st_fetch, st_write_io_done, st_execute, st_add, st_or,
st_and, st_store, st_read_mem, st_write_mem, st_read_io, st_write_io,
st_add_sp, st_decode, st_resync);
signal state : state_t:=st_resync;
attribute fsm_encoding : string;
attribute fsm_encoding of state : signal is "one-hot";
-- Decoded Opcode
type decode_t is (dec_nop, dec_im, dec_load_sp, dec_store_sp, dec_add_sp,
dec_emulate, dec_break, dec_push_sp, dec_pop_pc, dec_add,
dec_or, dec_and, dec_load, dec_not, dec_flip, dec_store,
dec_pop_sp, dec_interrupt);
signal d_opcode_r : decode_t;
signal d_opcode : decode_t;
signal opcode : unsigned(c_opcode_width-1 downto 0); -- Decoded
signal opcode_r : unsigned(c_opcode_width-1 downto 0); -- Registered
-- IRQ flag
signal in_irq_r : std_logic:='0';
-- I/O space address
signal addr_r : unsigned(g_addr_size-1 downto 0):=(others => '0');
begin
-- Dual ported memory interface
a_we_o <= a_we_r;
a_addr_o <= a_addr_r(g_stack_size-1 downto 2);
a_o <= a_r;
b_we_o <= b_we_r;
b_addr_o <= b_addr_r(g_stack_size-1 downto 2);
b_o <= b_r;
opcode <= c_i;
c_addr_o <= resize(pc_r(g_prog_size-1 downto 0), g_addr_size) when c_mux_r = '0'
else addr_r;
c_we_o <= c_we_r;
-- c_addr_o(g_prog_size-1 downto 2) <= pc_r(g_prog_size-1 downto 2);
-- c_addr_o(1 downto 0) <= not pc_r(1 downto 0); -- fix big endianess
-------------------------
-- Instruction Decoder --
-------------------------
-- Note: We use a separate memory port to fetch opcodes.
decode_control:
process(opcode)
begin
if (opcode(7 downto 7)=OPCODE_IM) then
d_opcode <= dec_im;
elsif (opcode(7 downto 5)=OPCODE_STORESP) then
d_opcode <= dec_store_sp;
elsif (opcode(7 downto 5)=OPCODE_LOADSP) then
d_opcode <= dec_load_sp;
elsif (opcode(7 downto 5)=OPCODE_EMULATE) then
d_opcode <= dec_emulate;
elsif (opcode(7 downto 4)=OPCODE_ADDSP) then
d_opcode <= dec_add_sp;
else -- OPCODE_SHORT
case opcode(3 downto 0) is
when OPCODE_BREAK =>
d_opcode <= dec_break;
when OPCODE_PUSHSP =>
d_opcode <= dec_push_sp;
when OPCODE_POPPC =>
d_opcode <= dec_pop_pc;
when OPCODE_ADD =>
d_opcode <= dec_add;
when OPCODE_OR =>
d_opcode <= dec_or;
when OPCODE_AND =>
d_opcode <= dec_and;
when OPCODE_LOAD =>
d_opcode <= dec_load;
when OPCODE_NOT =>
d_opcode <= dec_not;
when OPCODE_FLIP =>
d_opcode <= dec_flip;
when OPCODE_STORE =>
d_opcode <= dec_store;
when OPCODE_POPSP =>
d_opcode <= dec_pop_sp;
when others => -- OPCODE_NOP and others
d_opcode <= dec_nop;
end case;
end if;
end process decode_control;
data_o <= b_i;
opcode_control:
process (clk_i)
variable sp_offset : unsigned(4 downto 0);
begin
if rising_edge(clk_i) then
break_o <= '0';
write_en_o <= '0';
read_en_o <= '0';
-- synthesis translate_off
dbg_o.b_inst <= '0';
-- synthesis translate_on
posted_wr_a <= '0';
c_we_r <= '0';
c_en_r <= '0';
byte_cnt_d <= byte_cnt;
if reset_i='1' then
state <= st_resync;
sp_r <= SP_START;
pc_r <= (others => '0');
idim_r <= '0';
a_addr_r <= (others => '0');
b_addr_r <= (others => '0');
a_we_r <= '0';
b_we_r <= '0';
a_r <= (others => '0');
b_r <= (others => '0');
in_irq_r <= '0';
addr_r <= (others => '0');
c_mux_r <= '0';
first <= '0';
else -- reset_i/='1'
a_we_r <= '0';
b_we_r <= '0';
-- This saves LUTs, by explicitly declaring that the
-- a_o can be left at whatever value if a_we_r is
-- not set.
-- a_r <= (others => g_dont_care);
b_r <= (others => g_dont_care);
sp_offset:=(others => g_dont_care);
a_addr_r <= (others => g_dont_care);
-- b_addr_r <= (others => g_dont_care);
-- addr_r <= a_i(g_addr_size-1 downto 0);
d_opcode_r <= d_opcode;
opcode_r <= opcode;
if interrupt_i='0' then
in_irq_r <= '0'; -- no longer in an interrupt
end if;
case state is
when st_execute =>
state <= st_fetch;
-- At this point:
-- b_i contains opcode word
-- a_i contains top of stack
pc_r <= pc_r+1;
-- synthesis translate_off
-- Debug info (Trace)
dbg_o.b_inst <= '1';
dbg_o.pc <= (others => '0');
dbg_o.pc(g_addr_size-1 downto 0) <= pc_r;
dbg_o.opcode <= opcode_r;
dbg_o.sp <= (others => '0');
dbg_o.sp(g_stack_size-1 downto 2) <= sp_r;
dbg_o.stk_a <= a_i;
dbg_o.stk_b <= b_i;
-- synthesis translate_on
-- During the next cycle we'll be reading the next opcode
sp_offset(4):=not opcode_r(4);
sp_offset(3 downto 0):=opcode_r(3 downto 0);
idim_r <= '0';
--------------------
-- Execution Unit --
--------------------
case d_opcode_r is
when dec_interrupt =>
-- Not a real instruction, but an interrupt
-- Push(PC); PC=32
sp_r <= sp_r-1;
a_addr_r <= sp_r-1;
a_we_r <= '1';
a_r <= (others => g_dont_care);
a_r(c_max_addr_bit downto 0) <= pc_r;
-- Jump to ISR
pc_r <= to_unsigned(32, c_max_addr_bit+1); -- interrupt address
--report "ZPU jumped to interrupt!" severity note;
when dec_im =>
idim_r <= '1';
a_we_r <= '1';
if idim_r='0' then
-- First IM
-- Push the 7 bits (extending the sign)
sp_r <= sp_r-1;
a_addr_r <= sp_r-1;
a_r <= unsigned(resize(signed(opcode_r(6 downto 0)),32));
else
-- Next IMs, shift the word and put the new value in the lower
-- bits
a_addr_r <= sp_r;
a_r(31 downto 7) <= a_i(24 downto 0);
a_r(6 downto 0) <= opcode_r(6 downto 0);
end if;
when dec_store_sp =>
-- [SP+Offset]=Pop()
b_we_r <= '1';
b_addr_r <= sp_r+sp_offset;
b_r <= a_i;
sp_r <= sp_r+1;
state <= st_resync;
when dec_load_sp =>
-- Push([SP+Offset])
sp_r <= sp_r-1;
a_addr_r <= sp_r+sp_offset;
posted_wr_a <= '1';
state <= st_resync;
when dec_emulate =>
-- Push(PC+1), PC=Opcode[4:0]*32
sp_r <= sp_r-1;
a_we_r <= '1';
a_addr_r <= sp_r-1;
a_r <= (others => g_dont_care);
a_r(c_max_addr_bit downto 0) <= pc_r+1;
-- Jump to NUM*32
-- The emulate address is:
-- 98 7654 3210
-- 0000 00aa aaa0 0000
pc_r <= (others => '0');
pc_r(9 downto 5) <= opcode_r(4 downto 0);
when dec_add_sp =>
-- Push(Pop()+[SP+Offset])
a_addr_r <= sp_r;
b_addr_r <= sp_r+sp_offset;
state <= st_add_sp;
when dec_break =>
--report "Break instruction encountered" severity failure;
break_o <= '1';
when dec_push_sp =>
-- Push(SP)
sp_r <= sp_r-1;
a_we_r <= '1';
a_addr_r <= sp_r-1;
a_r <= (others => '0');
a_r(sp_r'range) <= sp_r;
a_r(31) <= '1'; -- DEBUG
when dec_pop_pc =>
-- Pop(PC)
pc_r <= a_i(pc_r'range);
sp_r <= sp_r+1;
state <= st_resync;
when dec_add =>
-- Push(Pop()+Pop())
sp_r <= sp_r+1;
state <= st_add;
when dec_or =>
-- Push(Pop() or Pop())
sp_r <= sp_r+1;
state <= st_or;
when dec_and =>
-- Push(Pop() and Pop())
sp_r <= sp_r+1;
state <= st_and;
when dec_load =>
-- Push([Pop()])
addr_r <= a_i(g_addr_size-1 downto 0);
if a_i(IO_BIT)='1' then
read_en_o <= '1';
state <= st_read_io;
elsif a_i(31)='1' then -- stack
a_addr_r <= a_i(a_addr_r'range);
posted_wr_a <= '1';
state <= st_resync;
else
c_en_r <= '1';
c_mux_r <= '1';
state <= st_read_mem;
byte_cnt <= "11"; -- 4 bytes
byte_cnt_d <= "11";
end if;
when dec_not =>
-- Push(not(Pop()))
a_addr_r <= sp_r;
a_we_r <= '1';
a_r <= not a_i;
when dec_flip =>
-- Push(flip(Pop()))
a_addr_r <= sp_r;
a_we_r <= '1';
for i in 0 to 31 loop
a_r(i) <= a_i(31-i);
end loop;
when dec_store =>
-- a=Pop(), b=Pop(), [a]=b
sp_r <= sp_r+1;
b_addr_r <= sp_r+1; -- added from store/io_store
if a_i(IO_BIT)='1' then
state <= st_write_io;
elsif a_i(31) = '1' then
state <= st_store;
b_addr_r <= sp_r+1;
else
state <= st_write_mem;
byte_cnt <= "11"; -- 4 bytes
first <= '1';
c_mux_r <= '1';
end if;
when dec_pop_sp =>
-- SP=Pop()
sp_r <= a_i(g_stack_size-1 downto 2);
state <= st_resync;
when dec_nop =>
-- Default, keep addressing to of the stack (A)
a_addr_r <= sp_r;
when others =>
null;
end case;
when st_store =>
sp_r <= sp_r+1;
a_we_r <= '1';
a_addr_r <= a_i(g_stack_size-1 downto 2);
a_r <= b_i;
state <= st_resync;
when st_read_mem =>
-- BIG ENDIAN
case byte_cnt_d is
when "00" =>
a_r(7 downto 0) <= c_i;
when "01" =>
a_r(15 downto 8) <= c_i;
when "10" =>
a_r(23 downto 16) <= c_i;
when others => -- 11
a_r(31 downto 24) <= c_i;
end case;
addr_r(1 downto 0) <= addr_r(1 downto 0) + 1;
byte_cnt <= byte_cnt - 1;
if byte_cnt_d = "00" then
a_addr_r <= sp_r;
a_we_r <= '1';
state <= st_fetch;
c_mux_r <= '0';
c_en_r <= '0';
end if;
when st_write_mem =>
case byte_cnt is
when "00" =>
c_o <= b_i(7 downto 0);
when "01" =>
c_o <= b_i(15 downto 8);
when "10" =>
c_o <= b_i(23 downto 16);
when others => -- 11
c_o <= b_i(31 downto 24);
end case;
if first='1' then
first <= '0';
addr_r <= a_i(g_addr_size-1 downto 0);
else
addr_r(1 downto 0) <= addr_r(1 downto 0) + 1;
end if;
c_en_r <= '1';
c_we_r <= '1';
byte_cnt <= byte_cnt - 1;
if byte_cnt = "00" then
sp_r <= sp_r+1;
state <= st_resync;
end if;
when st_read_io =>
-- Wait until memory I/O isn't busy
a_addr_r <= sp_r;
a_r <= data_i;
if mem_busy_i='0' then
state <= st_fetch;
a_we_r <= '1';
end if;
when st_write_io =>
-- [A]=B
sp_r <= sp_r+1;
write_en_o <= '1';
addr_r <= a_i(g_addr_size-1 downto 0);
state <= st_write_io_done;
when st_write_io_done =>
-- Wait until memory I/O isn't busy
if mem_busy_i='0' then
state <= st_resync;
end if;
when st_fetch =>
-- We need to resync. During this cycle
-- we'll fetch the opcode @ pc and thus it will
-- be available for st_execute in the next cycle
-- At this point a_i contains the value that is from the top of the stack
-- or that was fetched from the stack with an offset (loadsp)
a_we_r <= posted_wr_a;
a_r <= a_i;
a_addr_r <= sp_r;
b_addr_r <= sp_r+1;
state <= st_decode;
when st_decode =>
if interrupt_i='1' and in_irq_r='0' and idim_r='0' then
-- We got an interrupt, execute interrupt instead of next instruction
in_irq_r <= '1';
d_opcode_r <= dec_interrupt;
end if;
-- during the st_execute cycle we'll be fetching SP+1
a_addr_r <= sp_r;
b_addr_r <= sp_r+1;
state <= st_execute;
when st_add_sp =>
state <= st_add;
when st_add =>
a_addr_r <= sp_r;
a_we_r <= '1';
a_r <= a_i+b_i;
state <= st_fetch;
when st_or =>
a_addr_r <= sp_r;
a_we_r <= '1';
a_r <= a_i or b_i;
state <= st_fetch;
when st_and =>
a_addr_r <= sp_r;
a_we_r <= '1';
a_r <= a_i and b_i;
state <= st_fetch;
when st_resync =>
c_mux_r <= '0';
a_addr_r <= sp_r;
state <= st_fetch;
posted_wr_a <= posted_wr_a; -- keep
when others =>
null;
end case;
end if; -- else reset_i/='1'
end if; -- rising_edge(clk_i)
end process opcode_control;
addr_o <= addr_r;
end architecture Behave; -- Entity: zpu_tiny
|
------------------------------------------------------------------------------
---- ----
---- ZPU Exec ----
---- ----
---- http://www.opencores.org/ ----
---- ----
---- Description: ----
---- ZPU is a 32 bits small stack cpu. This is a modified version of ----
---- the zpu_small implementation. This one has a third (8-bit) port for ----
---- fetching instructions. This modification reduces the LUT size by ----
---- approximately 10% and increases the performance with 21%. ----
---- Needs external dual ported memory, plus single cycle external ----
---- program memory. It also requires a different linker script to ----
---- place the text segment on a logically different address to stick to ----
---- the single-, flat memory model programming paradigm. ----
---- ----
---- To Do: ----
---- Add a 'ready' for the external code memory ----
---- More thorough testing, cleanup code a bit more ----
---- ----
---- Author: ----
---- - Øyvind Harboe, oyvind.harboe zylin.com ----
---- - Salvador E. Tropea, salvador inti.gob.ar ----
---- - Gideon Zweijtzer, gideon.zweijtzer technolution.eu
---- ----
------------------------------------------------------------------------------
---- ----
---- Copyright (c) 2008 Øyvind Harboe <oyvind.harboe zylin.com> ----
---- Copyright (c) 2008 Salvador E. Tropea <salvador inti.gob.ar> ----
---- Copyright (c) 2008 Instituto Nacional de Tecnología Industrial ----
---- ----
---- Distributed under the BSD license ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Design unit: zpu_tiny(Behave) (Entity and architecture) ----
---- File name: zpu_tiny.vhdl ----
---- Note: None ----
---- Limitations: None known ----
---- Errors: None known ----
---- Library: work ----
---- Dependencies: ieee.std_logic_1164 ----
---- ieee.numeric_std ----
---- work.zpupkg ----
---- Target FPGA: Spartan 3E (XC3S500E-4-PQG208) ----
---- Language: VHDL ----
---- Wishbone: No ----
---- Synthesis tools: Xilinx Release 10.1.03i - xst K.39 ----
---- Simulation tools: Modelsim ----
---- Text editor: UltraEdit 11.00a+ ----
---- ----
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.zpupkg.all;
entity zpu_tiny is
generic(
g_addr_size : integer := 16; -- Total address space width (incl. I/O)
g_stack_size : integer := 12; -- Memory (stack+data) width
g_prog_size : integer := 14; -- Program size
g_dont_care : std_logic := '-'); -- Value used to fill the unsused bits, can be '-' or '0'
port(
clk_i : in std_logic; -- System Clock
reset_i : in std_logic; -- Synchronous Reset
interrupt_i : in std_logic; -- Interrupt
break_o : out std_logic; -- Breakpoint opcode executed
-- synthesis translate_off
dbg_o : out zpu_dbgo_t; -- Debug outputs (i.e. trace log)
-- synthesis translate_on
-- BRAM (stack ONLY)
a_we_o : out std_logic; -- BRAM A port Write Enable
a_addr_o : out unsigned(g_stack_size-1 downto 2):=(others => '0'); -- BRAM A Address
a_o : out unsigned(31 downto 0):=(others => '0'); -- Data to BRAM A port
a_i : in unsigned(31 downto 0); -- Data from BRAM A port
b_we_o : out std_logic; -- BRAM B port Write Enable
b_addr_o : out unsigned(g_stack_size-1 downto 2):=(others => '0'); -- BRAM B Address
b_o : out unsigned(31 downto 0):=(others => '0'); -- Data to BRAM B port
b_i : in unsigned(31 downto 0); -- Data from BRAM B port
-- memory port for text, bss, data
c_addr_o : out unsigned(g_addr_size-1 downto 0) := (others => '0');
c_i : in unsigned(c_opcode_width-1 downto 0);
c_o : out unsigned(c_opcode_width-1 downto 0);
c_we_o : out std_logic;
-- Memory mapped I/O
mem_busy_i : in std_logic;
data_i : in unsigned(31 downto 0);
data_o : out unsigned(31 downto 0);
addr_o : out unsigned(g_addr_size-1 downto 0);
write_en_o : out std_logic;
read_en_o : out std_logic);
end entity zpu_tiny;
architecture Behave of zpu_tiny is
constant c_max_addr_bit : integer:=g_addr_size-1;
-- Stack Pointer initial value: BRAM size-8
constant SP_START_1 : unsigned(g_addr_size-1 downto 0):=to_unsigned((2**g_stack_size)-8, g_addr_size);
constant SP_START : unsigned(g_stack_size-1 downto 2):=
SP_START_1(g_stack_size-1 downto 2);
constant IO_BIT : integer:=g_addr_size-1; -- Address bit to determine this is an I/O
-- Program counter
signal pc_r : unsigned(c_max_addr_bit downto 0):=(others => '0');
-- Stack pointer
signal sp_r : unsigned(g_stack_size-1 downto 2):=SP_START;
signal idim_r : std_logic:='0';
-- BRAM (text, some data, bss and stack)
-- a_r is a register for the top of the stack [SP]
-- Note: as this is a stack CPU this is a very important register.
signal a_we_r : std_logic:='0';
signal a_addr_r : unsigned(g_stack_size-1 downto 2):=(others => '0');
signal a_r : unsigned(31 downto 0):=(others => '0');
-- b_r is a register for the next value in the stack [SP+1]
signal b_we_r : std_logic:='0';
signal b_addr_r : unsigned(g_stack_size-1 downto 2):=(others => '0');
signal b_r : unsigned(31 downto 0):=(others => '0');
signal c_we_r : std_logic := '0';
signal c_en_r : std_logic := '0';
signal c_mux_r : std_logic := '0';
signal first : std_logic := '0';
signal byte_cnt : unsigned(1 downto 0) := "00";
signal byte_cnt_d : unsigned(1 downto 0) := "00";
signal posted_wr_a : std_logic;
-- State machine.
type state_t is (st_fetch, st_write_io_done, st_execute, st_add, st_or,
st_and, st_store, st_read_mem, st_write_mem, st_read_io, st_write_io,
st_add_sp, st_decode, st_resync);
signal state : state_t:=st_resync;
attribute fsm_encoding : string;
attribute fsm_encoding of state : signal is "one-hot";
-- Decoded Opcode
type decode_t is (dec_nop, dec_im, dec_load_sp, dec_store_sp, dec_add_sp,
dec_emulate, dec_break, dec_push_sp, dec_pop_pc, dec_add,
dec_or, dec_and, dec_load, dec_not, dec_flip, dec_store,
dec_pop_sp, dec_interrupt);
signal d_opcode_r : decode_t;
signal d_opcode : decode_t;
signal opcode : unsigned(c_opcode_width-1 downto 0); -- Decoded
signal opcode_r : unsigned(c_opcode_width-1 downto 0); -- Registered
-- IRQ flag
signal in_irq_r : std_logic:='0';
-- I/O space address
signal addr_r : unsigned(g_addr_size-1 downto 0):=(others => '0');
begin
-- Dual ported memory interface
a_we_o <= a_we_r;
a_addr_o <= a_addr_r(g_stack_size-1 downto 2);
a_o <= a_r;
b_we_o <= b_we_r;
b_addr_o <= b_addr_r(g_stack_size-1 downto 2);
b_o <= b_r;
opcode <= c_i;
c_addr_o <= resize(pc_r(g_prog_size-1 downto 0), g_addr_size) when c_mux_r = '0'
else addr_r;
c_we_o <= c_we_r;
-- c_addr_o(g_prog_size-1 downto 2) <= pc_r(g_prog_size-1 downto 2);
-- c_addr_o(1 downto 0) <= not pc_r(1 downto 0); -- fix big endianess
-------------------------
-- Instruction Decoder --
-------------------------
-- Note: We use a separate memory port to fetch opcodes.
decode_control:
process(opcode)
begin
if (opcode(7 downto 7)=OPCODE_IM) then
d_opcode <= dec_im;
elsif (opcode(7 downto 5)=OPCODE_STORESP) then
d_opcode <= dec_store_sp;
elsif (opcode(7 downto 5)=OPCODE_LOADSP) then
d_opcode <= dec_load_sp;
elsif (opcode(7 downto 5)=OPCODE_EMULATE) then
d_opcode <= dec_emulate;
elsif (opcode(7 downto 4)=OPCODE_ADDSP) then
d_opcode <= dec_add_sp;
else -- OPCODE_SHORT
case opcode(3 downto 0) is
when OPCODE_BREAK =>
d_opcode <= dec_break;
when OPCODE_PUSHSP =>
d_opcode <= dec_push_sp;
when OPCODE_POPPC =>
d_opcode <= dec_pop_pc;
when OPCODE_ADD =>
d_opcode <= dec_add;
when OPCODE_OR =>
d_opcode <= dec_or;
when OPCODE_AND =>
d_opcode <= dec_and;
when OPCODE_LOAD =>
d_opcode <= dec_load;
when OPCODE_NOT =>
d_opcode <= dec_not;
when OPCODE_FLIP =>
d_opcode <= dec_flip;
when OPCODE_STORE =>
d_opcode <= dec_store;
when OPCODE_POPSP =>
d_opcode <= dec_pop_sp;
when others => -- OPCODE_NOP and others
d_opcode <= dec_nop;
end case;
end if;
end process decode_control;
data_o <= b_i;
opcode_control:
process (clk_i)
variable sp_offset : unsigned(4 downto 0);
begin
if rising_edge(clk_i) then
break_o <= '0';
write_en_o <= '0';
read_en_o <= '0';
-- synthesis translate_off
dbg_o.b_inst <= '0';
-- synthesis translate_on
posted_wr_a <= '0';
c_we_r <= '0';
c_en_r <= '0';
byte_cnt_d <= byte_cnt;
if reset_i='1' then
state <= st_resync;
sp_r <= SP_START;
pc_r <= (others => '0');
idim_r <= '0';
a_addr_r <= (others => '0');
b_addr_r <= (others => '0');
a_we_r <= '0';
b_we_r <= '0';
a_r <= (others => '0');
b_r <= (others => '0');
in_irq_r <= '0';
addr_r <= (others => '0');
c_mux_r <= '0';
first <= '0';
else -- reset_i/='1'
a_we_r <= '0';
b_we_r <= '0';
-- This saves LUTs, by explicitly declaring that the
-- a_o can be left at whatever value if a_we_r is
-- not set.
-- a_r <= (others => g_dont_care);
b_r <= (others => g_dont_care);
sp_offset:=(others => g_dont_care);
a_addr_r <= (others => g_dont_care);
-- b_addr_r <= (others => g_dont_care);
-- addr_r <= a_i(g_addr_size-1 downto 0);
d_opcode_r <= d_opcode;
opcode_r <= opcode;
if interrupt_i='0' then
in_irq_r <= '0'; -- no longer in an interrupt
end if;
case state is
when st_execute =>
state <= st_fetch;
-- At this point:
-- b_i contains opcode word
-- a_i contains top of stack
pc_r <= pc_r+1;
-- synthesis translate_off
-- Debug info (Trace)
dbg_o.b_inst <= '1';
dbg_o.pc <= (others => '0');
dbg_o.pc(g_addr_size-1 downto 0) <= pc_r;
dbg_o.opcode <= opcode_r;
dbg_o.sp <= (others => '0');
dbg_o.sp(g_stack_size-1 downto 2) <= sp_r;
dbg_o.stk_a <= a_i;
dbg_o.stk_b <= b_i;
-- synthesis translate_on
-- During the next cycle we'll be reading the next opcode
sp_offset(4):=not opcode_r(4);
sp_offset(3 downto 0):=opcode_r(3 downto 0);
idim_r <= '0';
--------------------
-- Execution Unit --
--------------------
case d_opcode_r is
when dec_interrupt =>
-- Not a real instruction, but an interrupt
-- Push(PC); PC=32
sp_r <= sp_r-1;
a_addr_r <= sp_r-1;
a_we_r <= '1';
a_r <= (others => g_dont_care);
a_r(c_max_addr_bit downto 0) <= pc_r;
-- Jump to ISR
pc_r <= to_unsigned(32, c_max_addr_bit+1); -- interrupt address
--report "ZPU jumped to interrupt!" severity note;
when dec_im =>
idim_r <= '1';
a_we_r <= '1';
if idim_r='0' then
-- First IM
-- Push the 7 bits (extending the sign)
sp_r <= sp_r-1;
a_addr_r <= sp_r-1;
a_r <= unsigned(resize(signed(opcode_r(6 downto 0)),32));
else
-- Next IMs, shift the word and put the new value in the lower
-- bits
a_addr_r <= sp_r;
a_r(31 downto 7) <= a_i(24 downto 0);
a_r(6 downto 0) <= opcode_r(6 downto 0);
end if;
when dec_store_sp =>
-- [SP+Offset]=Pop()
b_we_r <= '1';
b_addr_r <= sp_r+sp_offset;
b_r <= a_i;
sp_r <= sp_r+1;
state <= st_resync;
when dec_load_sp =>
-- Push([SP+Offset])
sp_r <= sp_r-1;
a_addr_r <= sp_r+sp_offset;
posted_wr_a <= '1';
state <= st_resync;
when dec_emulate =>
-- Push(PC+1), PC=Opcode[4:0]*32
sp_r <= sp_r-1;
a_we_r <= '1';
a_addr_r <= sp_r-1;
a_r <= (others => g_dont_care);
a_r(c_max_addr_bit downto 0) <= pc_r+1;
-- Jump to NUM*32
-- The emulate address is:
-- 98 7654 3210
-- 0000 00aa aaa0 0000
pc_r <= (others => '0');
pc_r(9 downto 5) <= opcode_r(4 downto 0);
when dec_add_sp =>
-- Push(Pop()+[SP+Offset])
a_addr_r <= sp_r;
b_addr_r <= sp_r+sp_offset;
state <= st_add_sp;
when dec_break =>
--report "Break instruction encountered" severity failure;
break_o <= '1';
when dec_push_sp =>
-- Push(SP)
sp_r <= sp_r-1;
a_we_r <= '1';
a_addr_r <= sp_r-1;
a_r <= (others => '0');
a_r(sp_r'range) <= sp_r;
a_r(31) <= '1'; -- DEBUG
when dec_pop_pc =>
-- Pop(PC)
pc_r <= a_i(pc_r'range);
sp_r <= sp_r+1;
state <= st_resync;
when dec_add =>
-- Push(Pop()+Pop())
sp_r <= sp_r+1;
state <= st_add;
when dec_or =>
-- Push(Pop() or Pop())
sp_r <= sp_r+1;
state <= st_or;
when dec_and =>
-- Push(Pop() and Pop())
sp_r <= sp_r+1;
state <= st_and;
when dec_load =>
-- Push([Pop()])
addr_r <= a_i(g_addr_size-1 downto 0);
if a_i(IO_BIT)='1' then
read_en_o <= '1';
state <= st_read_io;
elsif a_i(31)='1' then -- stack
a_addr_r <= a_i(a_addr_r'range);
posted_wr_a <= '1';
state <= st_resync;
else
c_en_r <= '1';
c_mux_r <= '1';
state <= st_read_mem;
byte_cnt <= "11"; -- 4 bytes
byte_cnt_d <= "11";
end if;
when dec_not =>
-- Push(not(Pop()))
a_addr_r <= sp_r;
a_we_r <= '1';
a_r <= not a_i;
when dec_flip =>
-- Push(flip(Pop()))
a_addr_r <= sp_r;
a_we_r <= '1';
for i in 0 to 31 loop
a_r(i) <= a_i(31-i);
end loop;
when dec_store =>
-- a=Pop(), b=Pop(), [a]=b
sp_r <= sp_r+1;
b_addr_r <= sp_r+1; -- added from store/io_store
if a_i(IO_BIT)='1' then
state <= st_write_io;
elsif a_i(31) = '1' then
state <= st_store;
b_addr_r <= sp_r+1;
else
state <= st_write_mem;
byte_cnt <= "11"; -- 4 bytes
first <= '1';
c_mux_r <= '1';
end if;
when dec_pop_sp =>
-- SP=Pop()
sp_r <= a_i(g_stack_size-1 downto 2);
state <= st_resync;
when dec_nop =>
-- Default, keep addressing to of the stack (A)
a_addr_r <= sp_r;
when others =>
null;
end case;
when st_store =>
sp_r <= sp_r+1;
a_we_r <= '1';
a_addr_r <= a_i(g_stack_size-1 downto 2);
a_r <= b_i;
state <= st_resync;
when st_read_mem =>
-- BIG ENDIAN
case byte_cnt_d is
when "00" =>
a_r(7 downto 0) <= c_i;
when "01" =>
a_r(15 downto 8) <= c_i;
when "10" =>
a_r(23 downto 16) <= c_i;
when others => -- 11
a_r(31 downto 24) <= c_i;
end case;
addr_r(1 downto 0) <= addr_r(1 downto 0) + 1;
byte_cnt <= byte_cnt - 1;
if byte_cnt_d = "00" then
a_addr_r <= sp_r;
a_we_r <= '1';
state <= st_fetch;
c_mux_r <= '0';
c_en_r <= '0';
end if;
when st_write_mem =>
case byte_cnt is
when "00" =>
c_o <= b_i(7 downto 0);
when "01" =>
c_o <= b_i(15 downto 8);
when "10" =>
c_o <= b_i(23 downto 16);
when others => -- 11
c_o <= b_i(31 downto 24);
end case;
if first='1' then
first <= '0';
addr_r <= a_i(g_addr_size-1 downto 0);
else
addr_r(1 downto 0) <= addr_r(1 downto 0) + 1;
end if;
c_en_r <= '1';
c_we_r <= '1';
byte_cnt <= byte_cnt - 1;
if byte_cnt = "00" then
sp_r <= sp_r+1;
state <= st_resync;
end if;
when st_read_io =>
-- Wait until memory I/O isn't busy
a_addr_r <= sp_r;
a_r <= data_i;
if mem_busy_i='0' then
state <= st_fetch;
a_we_r <= '1';
end if;
when st_write_io =>
-- [A]=B
sp_r <= sp_r+1;
write_en_o <= '1';
addr_r <= a_i(g_addr_size-1 downto 0);
state <= st_write_io_done;
when st_write_io_done =>
-- Wait until memory I/O isn't busy
if mem_busy_i='0' then
state <= st_resync;
end if;
when st_fetch =>
-- We need to resync. During this cycle
-- we'll fetch the opcode @ pc and thus it will
-- be available for st_execute in the next cycle
-- At this point a_i contains the value that is from the top of the stack
-- or that was fetched from the stack with an offset (loadsp)
a_we_r <= posted_wr_a;
a_r <= a_i;
a_addr_r <= sp_r;
b_addr_r <= sp_r+1;
state <= st_decode;
when st_decode =>
if interrupt_i='1' and in_irq_r='0' and idim_r='0' then
-- We got an interrupt, execute interrupt instead of next instruction
in_irq_r <= '1';
d_opcode_r <= dec_interrupt;
end if;
-- during the st_execute cycle we'll be fetching SP+1
a_addr_r <= sp_r;
b_addr_r <= sp_r+1;
state <= st_execute;
when st_add_sp =>
state <= st_add;
when st_add =>
a_addr_r <= sp_r;
a_we_r <= '1';
a_r <= a_i+b_i;
state <= st_fetch;
when st_or =>
a_addr_r <= sp_r;
a_we_r <= '1';
a_r <= a_i or b_i;
state <= st_fetch;
when st_and =>
a_addr_r <= sp_r;
a_we_r <= '1';
a_r <= a_i and b_i;
state <= st_fetch;
when st_resync =>
c_mux_r <= '0';
a_addr_r <= sp_r;
state <= st_fetch;
posted_wr_a <= posted_wr_a; -- keep
when others =>
null;
end case;
end if; -- else reset_i/='1'
end if; -- rising_edge(clk_i)
end process opcode_control;
addr_o <= addr_r;
end architecture Behave; -- Entity: zpu_tiny
|
------------------------------------------------------------------------------
---- ----
---- ZPU Exec ----
---- ----
---- http://www.opencores.org/ ----
---- ----
---- Description: ----
---- ZPU is a 32 bits small stack cpu. This is a modified version of ----
---- the zpu_small implementation. This one has a third (8-bit) port for ----
---- fetching instructions. This modification reduces the LUT size by ----
---- approximately 10% and increases the performance with 21%. ----
---- Needs external dual ported memory, plus single cycle external ----
---- program memory. It also requires a different linker script to ----
---- place the text segment on a logically different address to stick to ----
---- the single-, flat memory model programming paradigm. ----
---- ----
---- To Do: ----
---- Add a 'ready' for the external code memory ----
---- More thorough testing, cleanup code a bit more ----
---- ----
---- Author: ----
---- - Øyvind Harboe, oyvind.harboe zylin.com ----
---- - Salvador E. Tropea, salvador inti.gob.ar ----
---- - Gideon Zweijtzer, gideon.zweijtzer technolution.eu
---- ----
------------------------------------------------------------------------------
---- ----
---- Copyright (c) 2008 Øyvind Harboe <oyvind.harboe zylin.com> ----
---- Copyright (c) 2008 Salvador E. Tropea <salvador inti.gob.ar> ----
---- Copyright (c) 2008 Instituto Nacional de Tecnología Industrial ----
---- ----
---- Distributed under the BSD license ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Design unit: zpu_tiny(Behave) (Entity and architecture) ----
---- File name: zpu_tiny.vhdl ----
---- Note: None ----
---- Limitations: None known ----
---- Errors: None known ----
---- Library: work ----
---- Dependencies: ieee.std_logic_1164 ----
---- ieee.numeric_std ----
---- work.zpupkg ----
---- Target FPGA: Spartan 3E (XC3S500E-4-PQG208) ----
---- Language: VHDL ----
---- Wishbone: No ----
---- Synthesis tools: Xilinx Release 10.1.03i - xst K.39 ----
---- Simulation tools: Modelsim ----
---- Text editor: UltraEdit 11.00a+ ----
---- ----
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.zpupkg.all;
entity zpu_tiny is
generic(
g_addr_size : integer := 16; -- Total address space width (incl. I/O)
g_stack_size : integer := 12; -- Memory (stack+data) width
g_prog_size : integer := 14; -- Program size
g_dont_care : std_logic := '-'); -- Value used to fill the unsused bits, can be '-' or '0'
port(
clk_i : in std_logic; -- System Clock
reset_i : in std_logic; -- Synchronous Reset
interrupt_i : in std_logic; -- Interrupt
break_o : out std_logic; -- Breakpoint opcode executed
-- synthesis translate_off
dbg_o : out zpu_dbgo_t; -- Debug outputs (i.e. trace log)
-- synthesis translate_on
-- BRAM (stack ONLY)
a_we_o : out std_logic; -- BRAM A port Write Enable
a_addr_o : out unsigned(g_stack_size-1 downto 2):=(others => '0'); -- BRAM A Address
a_o : out unsigned(31 downto 0):=(others => '0'); -- Data to BRAM A port
a_i : in unsigned(31 downto 0); -- Data from BRAM A port
b_we_o : out std_logic; -- BRAM B port Write Enable
b_addr_o : out unsigned(g_stack_size-1 downto 2):=(others => '0'); -- BRAM B Address
b_o : out unsigned(31 downto 0):=(others => '0'); -- Data to BRAM B port
b_i : in unsigned(31 downto 0); -- Data from BRAM B port
-- memory port for text, bss, data
c_addr_o : out unsigned(g_addr_size-1 downto 0) := (others => '0');
c_i : in unsigned(c_opcode_width-1 downto 0);
c_o : out unsigned(c_opcode_width-1 downto 0);
c_we_o : out std_logic;
-- Memory mapped I/O
mem_busy_i : in std_logic;
data_i : in unsigned(31 downto 0);
data_o : out unsigned(31 downto 0);
addr_o : out unsigned(g_addr_size-1 downto 0);
write_en_o : out std_logic;
read_en_o : out std_logic);
end entity zpu_tiny;
architecture Behave of zpu_tiny is
constant c_max_addr_bit : integer:=g_addr_size-1;
-- Stack Pointer initial value: BRAM size-8
constant SP_START_1 : unsigned(g_addr_size-1 downto 0):=to_unsigned((2**g_stack_size)-8, g_addr_size);
constant SP_START : unsigned(g_stack_size-1 downto 2):=
SP_START_1(g_stack_size-1 downto 2);
constant IO_BIT : integer:=g_addr_size-1; -- Address bit to determine this is an I/O
-- Program counter
signal pc_r : unsigned(c_max_addr_bit downto 0):=(others => '0');
-- Stack pointer
signal sp_r : unsigned(g_stack_size-1 downto 2):=SP_START;
signal idim_r : std_logic:='0';
-- BRAM (text, some data, bss and stack)
-- a_r is a register for the top of the stack [SP]
-- Note: as this is a stack CPU this is a very important register.
signal a_we_r : std_logic:='0';
signal a_addr_r : unsigned(g_stack_size-1 downto 2):=(others => '0');
signal a_r : unsigned(31 downto 0):=(others => '0');
-- b_r is a register for the next value in the stack [SP+1]
signal b_we_r : std_logic:='0';
signal b_addr_r : unsigned(g_stack_size-1 downto 2):=(others => '0');
signal b_r : unsigned(31 downto 0):=(others => '0');
signal c_we_r : std_logic := '0';
signal c_en_r : std_logic := '0';
signal c_mux_r : std_logic := '0';
signal first : std_logic := '0';
signal byte_cnt : unsigned(1 downto 0) := "00";
signal byte_cnt_d : unsigned(1 downto 0) := "00";
signal posted_wr_a : std_logic;
-- State machine.
type state_t is (st_fetch, st_write_io_done, st_execute, st_add, st_or,
st_and, st_store, st_read_mem, st_write_mem, st_read_io, st_write_io,
st_add_sp, st_decode, st_resync);
signal state : state_t:=st_resync;
attribute fsm_encoding : string;
attribute fsm_encoding of state : signal is "one-hot";
-- Decoded Opcode
type decode_t is (dec_nop, dec_im, dec_load_sp, dec_store_sp, dec_add_sp,
dec_emulate, dec_break, dec_push_sp, dec_pop_pc, dec_add,
dec_or, dec_and, dec_load, dec_not, dec_flip, dec_store,
dec_pop_sp, dec_interrupt);
signal d_opcode_r : decode_t;
signal d_opcode : decode_t;
signal opcode : unsigned(c_opcode_width-1 downto 0); -- Decoded
signal opcode_r : unsigned(c_opcode_width-1 downto 0); -- Registered
-- IRQ flag
signal in_irq_r : std_logic:='0';
-- I/O space address
signal addr_r : unsigned(g_addr_size-1 downto 0):=(others => '0');
begin
-- Dual ported memory interface
a_we_o <= a_we_r;
a_addr_o <= a_addr_r(g_stack_size-1 downto 2);
a_o <= a_r;
b_we_o <= b_we_r;
b_addr_o <= b_addr_r(g_stack_size-1 downto 2);
b_o <= b_r;
opcode <= c_i;
c_addr_o <= resize(pc_r(g_prog_size-1 downto 0), g_addr_size) when c_mux_r = '0'
else addr_r;
c_we_o <= c_we_r;
-- c_addr_o(g_prog_size-1 downto 2) <= pc_r(g_prog_size-1 downto 2);
-- c_addr_o(1 downto 0) <= not pc_r(1 downto 0); -- fix big endianess
-------------------------
-- Instruction Decoder --
-------------------------
-- Note: We use a separate memory port to fetch opcodes.
decode_control:
process(opcode)
begin
if (opcode(7 downto 7)=OPCODE_IM) then
d_opcode <= dec_im;
elsif (opcode(7 downto 5)=OPCODE_STORESP) then
d_opcode <= dec_store_sp;
elsif (opcode(7 downto 5)=OPCODE_LOADSP) then
d_opcode <= dec_load_sp;
elsif (opcode(7 downto 5)=OPCODE_EMULATE) then
d_opcode <= dec_emulate;
elsif (opcode(7 downto 4)=OPCODE_ADDSP) then
d_opcode <= dec_add_sp;
else -- OPCODE_SHORT
case opcode(3 downto 0) is
when OPCODE_BREAK =>
d_opcode <= dec_break;
when OPCODE_PUSHSP =>
d_opcode <= dec_push_sp;
when OPCODE_POPPC =>
d_opcode <= dec_pop_pc;
when OPCODE_ADD =>
d_opcode <= dec_add;
when OPCODE_OR =>
d_opcode <= dec_or;
when OPCODE_AND =>
d_opcode <= dec_and;
when OPCODE_LOAD =>
d_opcode <= dec_load;
when OPCODE_NOT =>
d_opcode <= dec_not;
when OPCODE_FLIP =>
d_opcode <= dec_flip;
when OPCODE_STORE =>
d_opcode <= dec_store;
when OPCODE_POPSP =>
d_opcode <= dec_pop_sp;
when others => -- OPCODE_NOP and others
d_opcode <= dec_nop;
end case;
end if;
end process decode_control;
data_o <= b_i;
opcode_control:
process (clk_i)
variable sp_offset : unsigned(4 downto 0);
begin
if rising_edge(clk_i) then
break_o <= '0';
write_en_o <= '0';
read_en_o <= '0';
-- synthesis translate_off
dbg_o.b_inst <= '0';
-- synthesis translate_on
posted_wr_a <= '0';
c_we_r <= '0';
c_en_r <= '0';
byte_cnt_d <= byte_cnt;
if reset_i='1' then
state <= st_resync;
sp_r <= SP_START;
pc_r <= (others => '0');
idim_r <= '0';
a_addr_r <= (others => '0');
b_addr_r <= (others => '0');
a_we_r <= '0';
b_we_r <= '0';
a_r <= (others => '0');
b_r <= (others => '0');
in_irq_r <= '0';
addr_r <= (others => '0');
c_mux_r <= '0';
first <= '0';
else -- reset_i/='1'
a_we_r <= '0';
b_we_r <= '0';
-- This saves LUTs, by explicitly declaring that the
-- a_o can be left at whatever value if a_we_r is
-- not set.
-- a_r <= (others => g_dont_care);
b_r <= (others => g_dont_care);
sp_offset:=(others => g_dont_care);
a_addr_r <= (others => g_dont_care);
-- b_addr_r <= (others => g_dont_care);
-- addr_r <= a_i(g_addr_size-1 downto 0);
d_opcode_r <= d_opcode;
opcode_r <= opcode;
if interrupt_i='0' then
in_irq_r <= '0'; -- no longer in an interrupt
end if;
case state is
when st_execute =>
state <= st_fetch;
-- At this point:
-- b_i contains opcode word
-- a_i contains top of stack
pc_r <= pc_r+1;
-- synthesis translate_off
-- Debug info (Trace)
dbg_o.b_inst <= '1';
dbg_o.pc <= (others => '0');
dbg_o.pc(g_addr_size-1 downto 0) <= pc_r;
dbg_o.opcode <= opcode_r;
dbg_o.sp <= (others => '0');
dbg_o.sp(g_stack_size-1 downto 2) <= sp_r;
dbg_o.stk_a <= a_i;
dbg_o.stk_b <= b_i;
-- synthesis translate_on
-- During the next cycle we'll be reading the next opcode
sp_offset(4):=not opcode_r(4);
sp_offset(3 downto 0):=opcode_r(3 downto 0);
idim_r <= '0';
--------------------
-- Execution Unit --
--------------------
case d_opcode_r is
when dec_interrupt =>
-- Not a real instruction, but an interrupt
-- Push(PC); PC=32
sp_r <= sp_r-1;
a_addr_r <= sp_r-1;
a_we_r <= '1';
a_r <= (others => g_dont_care);
a_r(c_max_addr_bit downto 0) <= pc_r;
-- Jump to ISR
pc_r <= to_unsigned(32, c_max_addr_bit+1); -- interrupt address
--report "ZPU jumped to interrupt!" severity note;
when dec_im =>
idim_r <= '1';
a_we_r <= '1';
if idim_r='0' then
-- First IM
-- Push the 7 bits (extending the sign)
sp_r <= sp_r-1;
a_addr_r <= sp_r-1;
a_r <= unsigned(resize(signed(opcode_r(6 downto 0)),32));
else
-- Next IMs, shift the word and put the new value in the lower
-- bits
a_addr_r <= sp_r;
a_r(31 downto 7) <= a_i(24 downto 0);
a_r(6 downto 0) <= opcode_r(6 downto 0);
end if;
when dec_store_sp =>
-- [SP+Offset]=Pop()
b_we_r <= '1';
b_addr_r <= sp_r+sp_offset;
b_r <= a_i;
sp_r <= sp_r+1;
state <= st_resync;
when dec_load_sp =>
-- Push([SP+Offset])
sp_r <= sp_r-1;
a_addr_r <= sp_r+sp_offset;
posted_wr_a <= '1';
state <= st_resync;
when dec_emulate =>
-- Push(PC+1), PC=Opcode[4:0]*32
sp_r <= sp_r-1;
a_we_r <= '1';
a_addr_r <= sp_r-1;
a_r <= (others => g_dont_care);
a_r(c_max_addr_bit downto 0) <= pc_r+1;
-- Jump to NUM*32
-- The emulate address is:
-- 98 7654 3210
-- 0000 00aa aaa0 0000
pc_r <= (others => '0');
pc_r(9 downto 5) <= opcode_r(4 downto 0);
when dec_add_sp =>
-- Push(Pop()+[SP+Offset])
a_addr_r <= sp_r;
b_addr_r <= sp_r+sp_offset;
state <= st_add_sp;
when dec_break =>
--report "Break instruction encountered" severity failure;
break_o <= '1';
when dec_push_sp =>
-- Push(SP)
sp_r <= sp_r-1;
a_we_r <= '1';
a_addr_r <= sp_r-1;
a_r <= (others => '0');
a_r(sp_r'range) <= sp_r;
a_r(31) <= '1'; -- DEBUG
when dec_pop_pc =>
-- Pop(PC)
pc_r <= a_i(pc_r'range);
sp_r <= sp_r+1;
state <= st_resync;
when dec_add =>
-- Push(Pop()+Pop())
sp_r <= sp_r+1;
state <= st_add;
when dec_or =>
-- Push(Pop() or Pop())
sp_r <= sp_r+1;
state <= st_or;
when dec_and =>
-- Push(Pop() and Pop())
sp_r <= sp_r+1;
state <= st_and;
when dec_load =>
-- Push([Pop()])
addr_r <= a_i(g_addr_size-1 downto 0);
if a_i(IO_BIT)='1' then
read_en_o <= '1';
state <= st_read_io;
elsif a_i(31)='1' then -- stack
a_addr_r <= a_i(a_addr_r'range);
posted_wr_a <= '1';
state <= st_resync;
else
c_en_r <= '1';
c_mux_r <= '1';
state <= st_read_mem;
byte_cnt <= "11"; -- 4 bytes
byte_cnt_d <= "11";
end if;
when dec_not =>
-- Push(not(Pop()))
a_addr_r <= sp_r;
a_we_r <= '1';
a_r <= not a_i;
when dec_flip =>
-- Push(flip(Pop()))
a_addr_r <= sp_r;
a_we_r <= '1';
for i in 0 to 31 loop
a_r(i) <= a_i(31-i);
end loop;
when dec_store =>
-- a=Pop(), b=Pop(), [a]=b
sp_r <= sp_r+1;
b_addr_r <= sp_r+1; -- added from store/io_store
if a_i(IO_BIT)='1' then
state <= st_write_io;
elsif a_i(31) = '1' then
state <= st_store;
b_addr_r <= sp_r+1;
else
state <= st_write_mem;
byte_cnt <= "11"; -- 4 bytes
first <= '1';
c_mux_r <= '1';
end if;
when dec_pop_sp =>
-- SP=Pop()
sp_r <= a_i(g_stack_size-1 downto 2);
state <= st_resync;
when dec_nop =>
-- Default, keep addressing to of the stack (A)
a_addr_r <= sp_r;
when others =>
null;
end case;
when st_store =>
sp_r <= sp_r+1;
a_we_r <= '1';
a_addr_r <= a_i(g_stack_size-1 downto 2);
a_r <= b_i;
state <= st_resync;
when st_read_mem =>
-- BIG ENDIAN
case byte_cnt_d is
when "00" =>
a_r(7 downto 0) <= c_i;
when "01" =>
a_r(15 downto 8) <= c_i;
when "10" =>
a_r(23 downto 16) <= c_i;
when others => -- 11
a_r(31 downto 24) <= c_i;
end case;
addr_r(1 downto 0) <= addr_r(1 downto 0) + 1;
byte_cnt <= byte_cnt - 1;
if byte_cnt_d = "00" then
a_addr_r <= sp_r;
a_we_r <= '1';
state <= st_fetch;
c_mux_r <= '0';
c_en_r <= '0';
end if;
when st_write_mem =>
case byte_cnt is
when "00" =>
c_o <= b_i(7 downto 0);
when "01" =>
c_o <= b_i(15 downto 8);
when "10" =>
c_o <= b_i(23 downto 16);
when others => -- 11
c_o <= b_i(31 downto 24);
end case;
if first='1' then
first <= '0';
addr_r <= a_i(g_addr_size-1 downto 0);
else
addr_r(1 downto 0) <= addr_r(1 downto 0) + 1;
end if;
c_en_r <= '1';
c_we_r <= '1';
byte_cnt <= byte_cnt - 1;
if byte_cnt = "00" then
sp_r <= sp_r+1;
state <= st_resync;
end if;
when st_read_io =>
-- Wait until memory I/O isn't busy
a_addr_r <= sp_r;
a_r <= data_i;
if mem_busy_i='0' then
state <= st_fetch;
a_we_r <= '1';
end if;
when st_write_io =>
-- [A]=B
sp_r <= sp_r+1;
write_en_o <= '1';
addr_r <= a_i(g_addr_size-1 downto 0);
state <= st_write_io_done;
when st_write_io_done =>
-- Wait until memory I/O isn't busy
if mem_busy_i='0' then
state <= st_resync;
end if;
when st_fetch =>
-- We need to resync. During this cycle
-- we'll fetch the opcode @ pc and thus it will
-- be available for st_execute in the next cycle
-- At this point a_i contains the value that is from the top of the stack
-- or that was fetched from the stack with an offset (loadsp)
a_we_r <= posted_wr_a;
a_r <= a_i;
a_addr_r <= sp_r;
b_addr_r <= sp_r+1;
state <= st_decode;
when st_decode =>
if interrupt_i='1' and in_irq_r='0' and idim_r='0' then
-- We got an interrupt, execute interrupt instead of next instruction
in_irq_r <= '1';
d_opcode_r <= dec_interrupt;
end if;
-- during the st_execute cycle we'll be fetching SP+1
a_addr_r <= sp_r;
b_addr_r <= sp_r+1;
state <= st_execute;
when st_add_sp =>
state <= st_add;
when st_add =>
a_addr_r <= sp_r;
a_we_r <= '1';
a_r <= a_i+b_i;
state <= st_fetch;
when st_or =>
a_addr_r <= sp_r;
a_we_r <= '1';
a_r <= a_i or b_i;
state <= st_fetch;
when st_and =>
a_addr_r <= sp_r;
a_we_r <= '1';
a_r <= a_i and b_i;
state <= st_fetch;
when st_resync =>
c_mux_r <= '0';
a_addr_r <= sp_r;
state <= st_fetch;
posted_wr_a <= posted_wr_a; -- keep
when others =>
null;
end case;
end if; -- else reset_i/='1'
end if; -- rising_edge(clk_i)
end process opcode_control;
addr_o <= addr_r;
end architecture Behave; -- Entity: zpu_tiny
|
------------------------------------------------------------------------------
---- ----
---- ZPU Exec ----
---- ----
---- http://www.opencores.org/ ----
---- ----
---- Description: ----
---- ZPU is a 32 bits small stack cpu. This is a modified version of ----
---- the zpu_small implementation. This one has a third (8-bit) port for ----
---- fetching instructions. This modification reduces the LUT size by ----
---- approximately 10% and increases the performance with 21%. ----
---- Needs external dual ported memory, plus single cycle external ----
---- program memory. It also requires a different linker script to ----
---- place the text segment on a logically different address to stick to ----
---- the single-, flat memory model programming paradigm. ----
---- ----
---- To Do: ----
---- Add a 'ready' for the external code memory ----
---- More thorough testing, cleanup code a bit more ----
---- ----
---- Author: ----
---- - Øyvind Harboe, oyvind.harboe zylin.com ----
---- - Salvador E. Tropea, salvador inti.gob.ar ----
---- - Gideon Zweijtzer, gideon.zweijtzer technolution.eu
---- ----
------------------------------------------------------------------------------
---- ----
---- Copyright (c) 2008 Øyvind Harboe <oyvind.harboe zylin.com> ----
---- Copyright (c) 2008 Salvador E. Tropea <salvador inti.gob.ar> ----
---- Copyright (c) 2008 Instituto Nacional de Tecnología Industrial ----
---- ----
---- Distributed under the BSD license ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Design unit: zpu_tiny(Behave) (Entity and architecture) ----
---- File name: zpu_tiny.vhdl ----
---- Note: None ----
---- Limitations: None known ----
---- Errors: None known ----
---- Library: work ----
---- Dependencies: ieee.std_logic_1164 ----
---- ieee.numeric_std ----
---- work.zpupkg ----
---- Target FPGA: Spartan 3E (XC3S500E-4-PQG208) ----
---- Language: VHDL ----
---- Wishbone: No ----
---- Synthesis tools: Xilinx Release 10.1.03i - xst K.39 ----
---- Simulation tools: Modelsim ----
---- Text editor: UltraEdit 11.00a+ ----
---- ----
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.zpupkg.all;
entity zpu_tiny is
generic(
g_addr_size : integer := 16; -- Total address space width (incl. I/O)
g_stack_size : integer := 12; -- Memory (stack+data) width
g_prog_size : integer := 14; -- Program size
g_dont_care : std_logic := '-'); -- Value used to fill the unsused bits, can be '-' or '0'
port(
clk_i : in std_logic; -- System Clock
reset_i : in std_logic; -- Synchronous Reset
interrupt_i : in std_logic; -- Interrupt
break_o : out std_logic; -- Breakpoint opcode executed
-- synthesis translate_off
dbg_o : out zpu_dbgo_t; -- Debug outputs (i.e. trace log)
-- synthesis translate_on
-- BRAM (stack ONLY)
a_we_o : out std_logic; -- BRAM A port Write Enable
a_addr_o : out unsigned(g_stack_size-1 downto 2):=(others => '0'); -- BRAM A Address
a_o : out unsigned(31 downto 0):=(others => '0'); -- Data to BRAM A port
a_i : in unsigned(31 downto 0); -- Data from BRAM A port
b_we_o : out std_logic; -- BRAM B port Write Enable
b_addr_o : out unsigned(g_stack_size-1 downto 2):=(others => '0'); -- BRAM B Address
b_o : out unsigned(31 downto 0):=(others => '0'); -- Data to BRAM B port
b_i : in unsigned(31 downto 0); -- Data from BRAM B port
-- memory port for text, bss, data
c_addr_o : out unsigned(g_addr_size-1 downto 0) := (others => '0');
c_i : in unsigned(c_opcode_width-1 downto 0);
c_o : out unsigned(c_opcode_width-1 downto 0);
c_we_o : out std_logic;
-- Memory mapped I/O
mem_busy_i : in std_logic;
data_i : in unsigned(31 downto 0);
data_o : out unsigned(31 downto 0);
addr_o : out unsigned(g_addr_size-1 downto 0);
write_en_o : out std_logic;
read_en_o : out std_logic);
end entity zpu_tiny;
architecture Behave of zpu_tiny is
constant c_max_addr_bit : integer:=g_addr_size-1;
-- Stack Pointer initial value: BRAM size-8
constant SP_START_1 : unsigned(g_addr_size-1 downto 0):=to_unsigned((2**g_stack_size)-8, g_addr_size);
constant SP_START : unsigned(g_stack_size-1 downto 2):=
SP_START_1(g_stack_size-1 downto 2);
constant IO_BIT : integer:=g_addr_size-1; -- Address bit to determine this is an I/O
-- Program counter
signal pc_r : unsigned(c_max_addr_bit downto 0):=(others => '0');
-- Stack pointer
signal sp_r : unsigned(g_stack_size-1 downto 2):=SP_START;
signal idim_r : std_logic:='0';
-- BRAM (text, some data, bss and stack)
-- a_r is a register for the top of the stack [SP]
-- Note: as this is a stack CPU this is a very important register.
signal a_we_r : std_logic:='0';
signal a_addr_r : unsigned(g_stack_size-1 downto 2):=(others => '0');
signal a_r : unsigned(31 downto 0):=(others => '0');
-- b_r is a register for the next value in the stack [SP+1]
signal b_we_r : std_logic:='0';
signal b_addr_r : unsigned(g_stack_size-1 downto 2):=(others => '0');
signal b_r : unsigned(31 downto 0):=(others => '0');
signal c_we_r : std_logic := '0';
signal c_en_r : std_logic := '0';
signal c_mux_r : std_logic := '0';
signal first : std_logic := '0';
signal byte_cnt : unsigned(1 downto 0) := "00";
signal byte_cnt_d : unsigned(1 downto 0) := "00";
signal posted_wr_a : std_logic;
-- State machine.
type state_t is (st_fetch, st_write_io_done, st_execute, st_add, st_or,
st_and, st_store, st_read_mem, st_write_mem, st_read_io, st_write_io,
st_add_sp, st_decode, st_resync);
signal state : state_t:=st_resync;
attribute fsm_encoding : string;
attribute fsm_encoding of state : signal is "one-hot";
-- Decoded Opcode
type decode_t is (dec_nop, dec_im, dec_load_sp, dec_store_sp, dec_add_sp,
dec_emulate, dec_break, dec_push_sp, dec_pop_pc, dec_add,
dec_or, dec_and, dec_load, dec_not, dec_flip, dec_store,
dec_pop_sp, dec_interrupt);
signal d_opcode_r : decode_t;
signal d_opcode : decode_t;
signal opcode : unsigned(c_opcode_width-1 downto 0); -- Decoded
signal opcode_r : unsigned(c_opcode_width-1 downto 0); -- Registered
-- IRQ flag
signal in_irq_r : std_logic:='0';
-- I/O space address
signal addr_r : unsigned(g_addr_size-1 downto 0):=(others => '0');
begin
-- Dual ported memory interface
a_we_o <= a_we_r;
a_addr_o <= a_addr_r(g_stack_size-1 downto 2);
a_o <= a_r;
b_we_o <= b_we_r;
b_addr_o <= b_addr_r(g_stack_size-1 downto 2);
b_o <= b_r;
opcode <= c_i;
c_addr_o <= resize(pc_r(g_prog_size-1 downto 0), g_addr_size) when c_mux_r = '0'
else addr_r;
c_we_o <= c_we_r;
-- c_addr_o(g_prog_size-1 downto 2) <= pc_r(g_prog_size-1 downto 2);
-- c_addr_o(1 downto 0) <= not pc_r(1 downto 0); -- fix big endianess
-------------------------
-- Instruction Decoder --
-------------------------
-- Note: We use a separate memory port to fetch opcodes.
decode_control:
process(opcode)
begin
if (opcode(7 downto 7)=OPCODE_IM) then
d_opcode <= dec_im;
elsif (opcode(7 downto 5)=OPCODE_STORESP) then
d_opcode <= dec_store_sp;
elsif (opcode(7 downto 5)=OPCODE_LOADSP) then
d_opcode <= dec_load_sp;
elsif (opcode(7 downto 5)=OPCODE_EMULATE) then
d_opcode <= dec_emulate;
elsif (opcode(7 downto 4)=OPCODE_ADDSP) then
d_opcode <= dec_add_sp;
else -- OPCODE_SHORT
case opcode(3 downto 0) is
when OPCODE_BREAK =>
d_opcode <= dec_break;
when OPCODE_PUSHSP =>
d_opcode <= dec_push_sp;
when OPCODE_POPPC =>
d_opcode <= dec_pop_pc;
when OPCODE_ADD =>
d_opcode <= dec_add;
when OPCODE_OR =>
d_opcode <= dec_or;
when OPCODE_AND =>
d_opcode <= dec_and;
when OPCODE_LOAD =>
d_opcode <= dec_load;
when OPCODE_NOT =>
d_opcode <= dec_not;
when OPCODE_FLIP =>
d_opcode <= dec_flip;
when OPCODE_STORE =>
d_opcode <= dec_store;
when OPCODE_POPSP =>
d_opcode <= dec_pop_sp;
when others => -- OPCODE_NOP and others
d_opcode <= dec_nop;
end case;
end if;
end process decode_control;
data_o <= b_i;
opcode_control:
process (clk_i)
variable sp_offset : unsigned(4 downto 0);
begin
if rising_edge(clk_i) then
break_o <= '0';
write_en_o <= '0';
read_en_o <= '0';
-- synthesis translate_off
dbg_o.b_inst <= '0';
-- synthesis translate_on
posted_wr_a <= '0';
c_we_r <= '0';
c_en_r <= '0';
byte_cnt_d <= byte_cnt;
if reset_i='1' then
state <= st_resync;
sp_r <= SP_START;
pc_r <= (others => '0');
idim_r <= '0';
a_addr_r <= (others => '0');
b_addr_r <= (others => '0');
a_we_r <= '0';
b_we_r <= '0';
a_r <= (others => '0');
b_r <= (others => '0');
in_irq_r <= '0';
addr_r <= (others => '0');
c_mux_r <= '0';
first <= '0';
else -- reset_i/='1'
a_we_r <= '0';
b_we_r <= '0';
-- This saves LUTs, by explicitly declaring that the
-- a_o can be left at whatever value if a_we_r is
-- not set.
-- a_r <= (others => g_dont_care);
b_r <= (others => g_dont_care);
sp_offset:=(others => g_dont_care);
a_addr_r <= (others => g_dont_care);
-- b_addr_r <= (others => g_dont_care);
-- addr_r <= a_i(g_addr_size-1 downto 0);
d_opcode_r <= d_opcode;
opcode_r <= opcode;
if interrupt_i='0' then
in_irq_r <= '0'; -- no longer in an interrupt
end if;
case state is
when st_execute =>
state <= st_fetch;
-- At this point:
-- b_i contains opcode word
-- a_i contains top of stack
pc_r <= pc_r+1;
-- synthesis translate_off
-- Debug info (Trace)
dbg_o.b_inst <= '1';
dbg_o.pc <= (others => '0');
dbg_o.pc(g_addr_size-1 downto 0) <= pc_r;
dbg_o.opcode <= opcode_r;
dbg_o.sp <= (others => '0');
dbg_o.sp(g_stack_size-1 downto 2) <= sp_r;
dbg_o.stk_a <= a_i;
dbg_o.stk_b <= b_i;
-- synthesis translate_on
-- During the next cycle we'll be reading the next opcode
sp_offset(4):=not opcode_r(4);
sp_offset(3 downto 0):=opcode_r(3 downto 0);
idim_r <= '0';
--------------------
-- Execution Unit --
--------------------
case d_opcode_r is
when dec_interrupt =>
-- Not a real instruction, but an interrupt
-- Push(PC); PC=32
sp_r <= sp_r-1;
a_addr_r <= sp_r-1;
a_we_r <= '1';
a_r <= (others => g_dont_care);
a_r(c_max_addr_bit downto 0) <= pc_r;
-- Jump to ISR
pc_r <= to_unsigned(32, c_max_addr_bit+1); -- interrupt address
--report "ZPU jumped to interrupt!" severity note;
when dec_im =>
idim_r <= '1';
a_we_r <= '1';
if idim_r='0' then
-- First IM
-- Push the 7 bits (extending the sign)
sp_r <= sp_r-1;
a_addr_r <= sp_r-1;
a_r <= unsigned(resize(signed(opcode_r(6 downto 0)),32));
else
-- Next IMs, shift the word and put the new value in the lower
-- bits
a_addr_r <= sp_r;
a_r(31 downto 7) <= a_i(24 downto 0);
a_r(6 downto 0) <= opcode_r(6 downto 0);
end if;
when dec_store_sp =>
-- [SP+Offset]=Pop()
b_we_r <= '1';
b_addr_r <= sp_r+sp_offset;
b_r <= a_i;
sp_r <= sp_r+1;
state <= st_resync;
when dec_load_sp =>
-- Push([SP+Offset])
sp_r <= sp_r-1;
a_addr_r <= sp_r+sp_offset;
posted_wr_a <= '1';
state <= st_resync;
when dec_emulate =>
-- Push(PC+1), PC=Opcode[4:0]*32
sp_r <= sp_r-1;
a_we_r <= '1';
a_addr_r <= sp_r-1;
a_r <= (others => g_dont_care);
a_r(c_max_addr_bit downto 0) <= pc_r+1;
-- Jump to NUM*32
-- The emulate address is:
-- 98 7654 3210
-- 0000 00aa aaa0 0000
pc_r <= (others => '0');
pc_r(9 downto 5) <= opcode_r(4 downto 0);
when dec_add_sp =>
-- Push(Pop()+[SP+Offset])
a_addr_r <= sp_r;
b_addr_r <= sp_r+sp_offset;
state <= st_add_sp;
when dec_break =>
--report "Break instruction encountered" severity failure;
break_o <= '1';
when dec_push_sp =>
-- Push(SP)
sp_r <= sp_r-1;
a_we_r <= '1';
a_addr_r <= sp_r-1;
a_r <= (others => '0');
a_r(sp_r'range) <= sp_r;
a_r(31) <= '1'; -- DEBUG
when dec_pop_pc =>
-- Pop(PC)
pc_r <= a_i(pc_r'range);
sp_r <= sp_r+1;
state <= st_resync;
when dec_add =>
-- Push(Pop()+Pop())
sp_r <= sp_r+1;
state <= st_add;
when dec_or =>
-- Push(Pop() or Pop())
sp_r <= sp_r+1;
state <= st_or;
when dec_and =>
-- Push(Pop() and Pop())
sp_r <= sp_r+1;
state <= st_and;
when dec_load =>
-- Push([Pop()])
addr_r <= a_i(g_addr_size-1 downto 0);
if a_i(IO_BIT)='1' then
read_en_o <= '1';
state <= st_read_io;
elsif a_i(31)='1' then -- stack
a_addr_r <= a_i(a_addr_r'range);
posted_wr_a <= '1';
state <= st_resync;
else
c_en_r <= '1';
c_mux_r <= '1';
state <= st_read_mem;
byte_cnt <= "11"; -- 4 bytes
byte_cnt_d <= "11";
end if;
when dec_not =>
-- Push(not(Pop()))
a_addr_r <= sp_r;
a_we_r <= '1';
a_r <= not a_i;
when dec_flip =>
-- Push(flip(Pop()))
a_addr_r <= sp_r;
a_we_r <= '1';
for i in 0 to 31 loop
a_r(i) <= a_i(31-i);
end loop;
when dec_store =>
-- a=Pop(), b=Pop(), [a]=b
sp_r <= sp_r+1;
b_addr_r <= sp_r+1; -- added from store/io_store
if a_i(IO_BIT)='1' then
state <= st_write_io;
elsif a_i(31) = '1' then
state <= st_store;
b_addr_r <= sp_r+1;
else
state <= st_write_mem;
byte_cnt <= "11"; -- 4 bytes
first <= '1';
c_mux_r <= '1';
end if;
when dec_pop_sp =>
-- SP=Pop()
sp_r <= a_i(g_stack_size-1 downto 2);
state <= st_resync;
when dec_nop =>
-- Default, keep addressing to of the stack (A)
a_addr_r <= sp_r;
when others =>
null;
end case;
when st_store =>
sp_r <= sp_r+1;
a_we_r <= '1';
a_addr_r <= a_i(g_stack_size-1 downto 2);
a_r <= b_i;
state <= st_resync;
when st_read_mem =>
-- BIG ENDIAN
case byte_cnt_d is
when "00" =>
a_r(7 downto 0) <= c_i;
when "01" =>
a_r(15 downto 8) <= c_i;
when "10" =>
a_r(23 downto 16) <= c_i;
when others => -- 11
a_r(31 downto 24) <= c_i;
end case;
addr_r(1 downto 0) <= addr_r(1 downto 0) + 1;
byte_cnt <= byte_cnt - 1;
if byte_cnt_d = "00" then
a_addr_r <= sp_r;
a_we_r <= '1';
state <= st_fetch;
c_mux_r <= '0';
c_en_r <= '0';
end if;
when st_write_mem =>
case byte_cnt is
when "00" =>
c_o <= b_i(7 downto 0);
when "01" =>
c_o <= b_i(15 downto 8);
when "10" =>
c_o <= b_i(23 downto 16);
when others => -- 11
c_o <= b_i(31 downto 24);
end case;
if first='1' then
first <= '0';
addr_r <= a_i(g_addr_size-1 downto 0);
else
addr_r(1 downto 0) <= addr_r(1 downto 0) + 1;
end if;
c_en_r <= '1';
c_we_r <= '1';
byte_cnt <= byte_cnt - 1;
if byte_cnt = "00" then
sp_r <= sp_r+1;
state <= st_resync;
end if;
when st_read_io =>
-- Wait until memory I/O isn't busy
a_addr_r <= sp_r;
a_r <= data_i;
if mem_busy_i='0' then
state <= st_fetch;
a_we_r <= '1';
end if;
when st_write_io =>
-- [A]=B
sp_r <= sp_r+1;
write_en_o <= '1';
addr_r <= a_i(g_addr_size-1 downto 0);
state <= st_write_io_done;
when st_write_io_done =>
-- Wait until memory I/O isn't busy
if mem_busy_i='0' then
state <= st_resync;
end if;
when st_fetch =>
-- We need to resync. During this cycle
-- we'll fetch the opcode @ pc and thus it will
-- be available for st_execute in the next cycle
-- At this point a_i contains the value that is from the top of the stack
-- or that was fetched from the stack with an offset (loadsp)
a_we_r <= posted_wr_a;
a_r <= a_i;
a_addr_r <= sp_r;
b_addr_r <= sp_r+1;
state <= st_decode;
when st_decode =>
if interrupt_i='1' and in_irq_r='0' and idim_r='0' then
-- We got an interrupt, execute interrupt instead of next instruction
in_irq_r <= '1';
d_opcode_r <= dec_interrupt;
end if;
-- during the st_execute cycle we'll be fetching SP+1
a_addr_r <= sp_r;
b_addr_r <= sp_r+1;
state <= st_execute;
when st_add_sp =>
state <= st_add;
when st_add =>
a_addr_r <= sp_r;
a_we_r <= '1';
a_r <= a_i+b_i;
state <= st_fetch;
when st_or =>
a_addr_r <= sp_r;
a_we_r <= '1';
a_r <= a_i or b_i;
state <= st_fetch;
when st_and =>
a_addr_r <= sp_r;
a_we_r <= '1';
a_r <= a_i and b_i;
state <= st_fetch;
when st_resync =>
c_mux_r <= '0';
a_addr_r <= sp_r;
state <= st_fetch;
posted_wr_a <= posted_wr_a; -- keep
when others =>
null;
end case;
end if; -- else reset_i/='1'
end if; -- rising_edge(clk_i)
end process opcode_control;
addr_o <= addr_r;
end architecture Behave; -- Entity: zpu_tiny
|
------------------------------------------------------------------------------
---- ----
---- ZPU Exec ----
---- ----
---- http://www.opencores.org/ ----
---- ----
---- Description: ----
---- ZPU is a 32 bits small stack cpu. This is a modified version of ----
---- the zpu_small implementation. This one has a third (8-bit) port for ----
---- fetching instructions. This modification reduces the LUT size by ----
---- approximately 10% and increases the performance with 21%. ----
---- Needs external dual ported memory, plus single cycle external ----
---- program memory. It also requires a different linker script to ----
---- place the text segment on a logically different address to stick to ----
---- the single-, flat memory model programming paradigm. ----
---- ----
---- To Do: ----
---- Add a 'ready' for the external code memory ----
---- More thorough testing, cleanup code a bit more ----
---- ----
---- Author: ----
---- - Øyvind Harboe, oyvind.harboe zylin.com ----
---- - Salvador E. Tropea, salvador inti.gob.ar ----
---- - Gideon Zweijtzer, gideon.zweijtzer technolution.eu
---- ----
------------------------------------------------------------------------------
---- ----
---- Copyright (c) 2008 Øyvind Harboe <oyvind.harboe zylin.com> ----
---- Copyright (c) 2008 Salvador E. Tropea <salvador inti.gob.ar> ----
---- Copyright (c) 2008 Instituto Nacional de Tecnología Industrial ----
---- ----
---- Distributed under the BSD license ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Design unit: zpu_tiny(Behave) (Entity and architecture) ----
---- File name: zpu_tiny.vhdl ----
---- Note: None ----
---- Limitations: None known ----
---- Errors: None known ----
---- Library: work ----
---- Dependencies: ieee.std_logic_1164 ----
---- ieee.numeric_std ----
---- work.zpupkg ----
---- Target FPGA: Spartan 3E (XC3S500E-4-PQG208) ----
---- Language: VHDL ----
---- Wishbone: No ----
---- Synthesis tools: Xilinx Release 10.1.03i - xst K.39 ----
---- Simulation tools: Modelsim ----
---- Text editor: UltraEdit 11.00a+ ----
---- ----
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.zpupkg.all;
entity zpu_tiny is
generic(
g_addr_size : integer := 16; -- Total address space width (incl. I/O)
g_stack_size : integer := 12; -- Memory (stack+data) width
g_prog_size : integer := 14; -- Program size
g_dont_care : std_logic := '-'); -- Value used to fill the unsused bits, can be '-' or '0'
port(
clk_i : in std_logic; -- System Clock
reset_i : in std_logic; -- Synchronous Reset
interrupt_i : in std_logic; -- Interrupt
break_o : out std_logic; -- Breakpoint opcode executed
-- synthesis translate_off
dbg_o : out zpu_dbgo_t; -- Debug outputs (i.e. trace log)
-- synthesis translate_on
-- BRAM (stack ONLY)
a_we_o : out std_logic; -- BRAM A port Write Enable
a_addr_o : out unsigned(g_stack_size-1 downto 2):=(others => '0'); -- BRAM A Address
a_o : out unsigned(31 downto 0):=(others => '0'); -- Data to BRAM A port
a_i : in unsigned(31 downto 0); -- Data from BRAM A port
b_we_o : out std_logic; -- BRAM B port Write Enable
b_addr_o : out unsigned(g_stack_size-1 downto 2):=(others => '0'); -- BRAM B Address
b_o : out unsigned(31 downto 0):=(others => '0'); -- Data to BRAM B port
b_i : in unsigned(31 downto 0); -- Data from BRAM B port
-- memory port for text, bss, data
c_addr_o : out unsigned(g_addr_size-1 downto 0) := (others => '0');
c_i : in unsigned(c_opcode_width-1 downto 0);
c_o : out unsigned(c_opcode_width-1 downto 0);
c_we_o : out std_logic;
-- Memory mapped I/O
mem_busy_i : in std_logic;
data_i : in unsigned(31 downto 0);
data_o : out unsigned(31 downto 0);
addr_o : out unsigned(g_addr_size-1 downto 0);
write_en_o : out std_logic;
read_en_o : out std_logic);
end entity zpu_tiny;
architecture Behave of zpu_tiny is
constant c_max_addr_bit : integer:=g_addr_size-1;
-- Stack Pointer initial value: BRAM size-8
constant SP_START_1 : unsigned(g_addr_size-1 downto 0):=to_unsigned((2**g_stack_size)-8, g_addr_size);
constant SP_START : unsigned(g_stack_size-1 downto 2):=
SP_START_1(g_stack_size-1 downto 2);
constant IO_BIT : integer:=g_addr_size-1; -- Address bit to determine this is an I/O
-- Program counter
signal pc_r : unsigned(c_max_addr_bit downto 0):=(others => '0');
-- Stack pointer
signal sp_r : unsigned(g_stack_size-1 downto 2):=SP_START;
signal idim_r : std_logic:='0';
-- BRAM (text, some data, bss and stack)
-- a_r is a register for the top of the stack [SP]
-- Note: as this is a stack CPU this is a very important register.
signal a_we_r : std_logic:='0';
signal a_addr_r : unsigned(g_stack_size-1 downto 2):=(others => '0');
signal a_r : unsigned(31 downto 0):=(others => '0');
-- b_r is a register for the next value in the stack [SP+1]
signal b_we_r : std_logic:='0';
signal b_addr_r : unsigned(g_stack_size-1 downto 2):=(others => '0');
signal b_r : unsigned(31 downto 0):=(others => '0');
signal c_we_r : std_logic := '0';
signal c_en_r : std_logic := '0';
signal c_mux_r : std_logic := '0';
signal first : std_logic := '0';
signal byte_cnt : unsigned(1 downto 0) := "00";
signal byte_cnt_d : unsigned(1 downto 0) := "00";
signal posted_wr_a : std_logic;
-- State machine.
type state_t is (st_fetch, st_write_io_done, st_execute, st_add, st_or,
st_and, st_store, st_read_mem, st_write_mem, st_read_io, st_write_io,
st_add_sp, st_decode, st_resync);
signal state : state_t:=st_resync;
attribute fsm_encoding : string;
attribute fsm_encoding of state : signal is "one-hot";
-- Decoded Opcode
type decode_t is (dec_nop, dec_im, dec_load_sp, dec_store_sp, dec_add_sp,
dec_emulate, dec_break, dec_push_sp, dec_pop_pc, dec_add,
dec_or, dec_and, dec_load, dec_not, dec_flip, dec_store,
dec_pop_sp, dec_interrupt);
signal d_opcode_r : decode_t;
signal d_opcode : decode_t;
signal opcode : unsigned(c_opcode_width-1 downto 0); -- Decoded
signal opcode_r : unsigned(c_opcode_width-1 downto 0); -- Registered
-- IRQ flag
signal in_irq_r : std_logic:='0';
-- I/O space address
signal addr_r : unsigned(g_addr_size-1 downto 0):=(others => '0');
begin
-- Dual ported memory interface
a_we_o <= a_we_r;
a_addr_o <= a_addr_r(g_stack_size-1 downto 2);
a_o <= a_r;
b_we_o <= b_we_r;
b_addr_o <= b_addr_r(g_stack_size-1 downto 2);
b_o <= b_r;
opcode <= c_i;
c_addr_o <= resize(pc_r(g_prog_size-1 downto 0), g_addr_size) when c_mux_r = '0'
else addr_r;
c_we_o <= c_we_r;
-- c_addr_o(g_prog_size-1 downto 2) <= pc_r(g_prog_size-1 downto 2);
-- c_addr_o(1 downto 0) <= not pc_r(1 downto 0); -- fix big endianess
-------------------------
-- Instruction Decoder --
-------------------------
-- Note: We use a separate memory port to fetch opcodes.
decode_control:
process(opcode)
begin
if (opcode(7 downto 7)=OPCODE_IM) then
d_opcode <= dec_im;
elsif (opcode(7 downto 5)=OPCODE_STORESP) then
d_opcode <= dec_store_sp;
elsif (opcode(7 downto 5)=OPCODE_LOADSP) then
d_opcode <= dec_load_sp;
elsif (opcode(7 downto 5)=OPCODE_EMULATE) then
d_opcode <= dec_emulate;
elsif (opcode(7 downto 4)=OPCODE_ADDSP) then
d_opcode <= dec_add_sp;
else -- OPCODE_SHORT
case opcode(3 downto 0) is
when OPCODE_BREAK =>
d_opcode <= dec_break;
when OPCODE_PUSHSP =>
d_opcode <= dec_push_sp;
when OPCODE_POPPC =>
d_opcode <= dec_pop_pc;
when OPCODE_ADD =>
d_opcode <= dec_add;
when OPCODE_OR =>
d_opcode <= dec_or;
when OPCODE_AND =>
d_opcode <= dec_and;
when OPCODE_LOAD =>
d_opcode <= dec_load;
when OPCODE_NOT =>
d_opcode <= dec_not;
when OPCODE_FLIP =>
d_opcode <= dec_flip;
when OPCODE_STORE =>
d_opcode <= dec_store;
when OPCODE_POPSP =>
d_opcode <= dec_pop_sp;
when others => -- OPCODE_NOP and others
d_opcode <= dec_nop;
end case;
end if;
end process decode_control;
data_o <= b_i;
opcode_control:
process (clk_i)
variable sp_offset : unsigned(4 downto 0);
begin
if rising_edge(clk_i) then
break_o <= '0';
write_en_o <= '0';
read_en_o <= '0';
-- synthesis translate_off
dbg_o.b_inst <= '0';
-- synthesis translate_on
posted_wr_a <= '0';
c_we_r <= '0';
c_en_r <= '0';
byte_cnt_d <= byte_cnt;
if reset_i='1' then
state <= st_resync;
sp_r <= SP_START;
pc_r <= (others => '0');
idim_r <= '0';
a_addr_r <= (others => '0');
b_addr_r <= (others => '0');
a_we_r <= '0';
b_we_r <= '0';
a_r <= (others => '0');
b_r <= (others => '0');
in_irq_r <= '0';
addr_r <= (others => '0');
c_mux_r <= '0';
first <= '0';
else -- reset_i/='1'
a_we_r <= '0';
b_we_r <= '0';
-- This saves LUTs, by explicitly declaring that the
-- a_o can be left at whatever value if a_we_r is
-- not set.
-- a_r <= (others => g_dont_care);
b_r <= (others => g_dont_care);
sp_offset:=(others => g_dont_care);
a_addr_r <= (others => g_dont_care);
-- b_addr_r <= (others => g_dont_care);
-- addr_r <= a_i(g_addr_size-1 downto 0);
d_opcode_r <= d_opcode;
opcode_r <= opcode;
if interrupt_i='0' then
in_irq_r <= '0'; -- no longer in an interrupt
end if;
case state is
when st_execute =>
state <= st_fetch;
-- At this point:
-- b_i contains opcode word
-- a_i contains top of stack
pc_r <= pc_r+1;
-- synthesis translate_off
-- Debug info (Trace)
dbg_o.b_inst <= '1';
dbg_o.pc <= (others => '0');
dbg_o.pc(g_addr_size-1 downto 0) <= pc_r;
dbg_o.opcode <= opcode_r;
dbg_o.sp <= (others => '0');
dbg_o.sp(g_stack_size-1 downto 2) <= sp_r;
dbg_o.stk_a <= a_i;
dbg_o.stk_b <= b_i;
-- synthesis translate_on
-- During the next cycle we'll be reading the next opcode
sp_offset(4):=not opcode_r(4);
sp_offset(3 downto 0):=opcode_r(3 downto 0);
idim_r <= '0';
--------------------
-- Execution Unit --
--------------------
case d_opcode_r is
when dec_interrupt =>
-- Not a real instruction, but an interrupt
-- Push(PC); PC=32
sp_r <= sp_r-1;
a_addr_r <= sp_r-1;
a_we_r <= '1';
a_r <= (others => g_dont_care);
a_r(c_max_addr_bit downto 0) <= pc_r;
-- Jump to ISR
pc_r <= to_unsigned(32, c_max_addr_bit+1); -- interrupt address
--report "ZPU jumped to interrupt!" severity note;
when dec_im =>
idim_r <= '1';
a_we_r <= '1';
if idim_r='0' then
-- First IM
-- Push the 7 bits (extending the sign)
sp_r <= sp_r-1;
a_addr_r <= sp_r-1;
a_r <= unsigned(resize(signed(opcode_r(6 downto 0)),32));
else
-- Next IMs, shift the word and put the new value in the lower
-- bits
a_addr_r <= sp_r;
a_r(31 downto 7) <= a_i(24 downto 0);
a_r(6 downto 0) <= opcode_r(6 downto 0);
end if;
when dec_store_sp =>
-- [SP+Offset]=Pop()
b_we_r <= '1';
b_addr_r <= sp_r+sp_offset;
b_r <= a_i;
sp_r <= sp_r+1;
state <= st_resync;
when dec_load_sp =>
-- Push([SP+Offset])
sp_r <= sp_r-1;
a_addr_r <= sp_r+sp_offset;
posted_wr_a <= '1';
state <= st_resync;
when dec_emulate =>
-- Push(PC+1), PC=Opcode[4:0]*32
sp_r <= sp_r-1;
a_we_r <= '1';
a_addr_r <= sp_r-1;
a_r <= (others => g_dont_care);
a_r(c_max_addr_bit downto 0) <= pc_r+1;
-- Jump to NUM*32
-- The emulate address is:
-- 98 7654 3210
-- 0000 00aa aaa0 0000
pc_r <= (others => '0');
pc_r(9 downto 5) <= opcode_r(4 downto 0);
when dec_add_sp =>
-- Push(Pop()+[SP+Offset])
a_addr_r <= sp_r;
b_addr_r <= sp_r+sp_offset;
state <= st_add_sp;
when dec_break =>
--report "Break instruction encountered" severity failure;
break_o <= '1';
when dec_push_sp =>
-- Push(SP)
sp_r <= sp_r-1;
a_we_r <= '1';
a_addr_r <= sp_r-1;
a_r <= (others => '0');
a_r(sp_r'range) <= sp_r;
a_r(31) <= '1'; -- DEBUG
when dec_pop_pc =>
-- Pop(PC)
pc_r <= a_i(pc_r'range);
sp_r <= sp_r+1;
state <= st_resync;
when dec_add =>
-- Push(Pop()+Pop())
sp_r <= sp_r+1;
state <= st_add;
when dec_or =>
-- Push(Pop() or Pop())
sp_r <= sp_r+1;
state <= st_or;
when dec_and =>
-- Push(Pop() and Pop())
sp_r <= sp_r+1;
state <= st_and;
when dec_load =>
-- Push([Pop()])
addr_r <= a_i(g_addr_size-1 downto 0);
if a_i(IO_BIT)='1' then
read_en_o <= '1';
state <= st_read_io;
elsif a_i(31)='1' then -- stack
a_addr_r <= a_i(a_addr_r'range);
posted_wr_a <= '1';
state <= st_resync;
else
c_en_r <= '1';
c_mux_r <= '1';
state <= st_read_mem;
byte_cnt <= "11"; -- 4 bytes
byte_cnt_d <= "11";
end if;
when dec_not =>
-- Push(not(Pop()))
a_addr_r <= sp_r;
a_we_r <= '1';
a_r <= not a_i;
when dec_flip =>
-- Push(flip(Pop()))
a_addr_r <= sp_r;
a_we_r <= '1';
for i in 0 to 31 loop
a_r(i) <= a_i(31-i);
end loop;
when dec_store =>
-- a=Pop(), b=Pop(), [a]=b
sp_r <= sp_r+1;
b_addr_r <= sp_r+1; -- added from store/io_store
if a_i(IO_BIT)='1' then
state <= st_write_io;
elsif a_i(31) = '1' then
state <= st_store;
b_addr_r <= sp_r+1;
else
state <= st_write_mem;
byte_cnt <= "11"; -- 4 bytes
first <= '1';
c_mux_r <= '1';
end if;
when dec_pop_sp =>
-- SP=Pop()
sp_r <= a_i(g_stack_size-1 downto 2);
state <= st_resync;
when dec_nop =>
-- Default, keep addressing to of the stack (A)
a_addr_r <= sp_r;
when others =>
null;
end case;
when st_store =>
sp_r <= sp_r+1;
a_we_r <= '1';
a_addr_r <= a_i(g_stack_size-1 downto 2);
a_r <= b_i;
state <= st_resync;
when st_read_mem =>
-- BIG ENDIAN
case byte_cnt_d is
when "00" =>
a_r(7 downto 0) <= c_i;
when "01" =>
a_r(15 downto 8) <= c_i;
when "10" =>
a_r(23 downto 16) <= c_i;
when others => -- 11
a_r(31 downto 24) <= c_i;
end case;
addr_r(1 downto 0) <= addr_r(1 downto 0) + 1;
byte_cnt <= byte_cnt - 1;
if byte_cnt_d = "00" then
a_addr_r <= sp_r;
a_we_r <= '1';
state <= st_fetch;
c_mux_r <= '0';
c_en_r <= '0';
end if;
when st_write_mem =>
case byte_cnt is
when "00" =>
c_o <= b_i(7 downto 0);
when "01" =>
c_o <= b_i(15 downto 8);
when "10" =>
c_o <= b_i(23 downto 16);
when others => -- 11
c_o <= b_i(31 downto 24);
end case;
if first='1' then
first <= '0';
addr_r <= a_i(g_addr_size-1 downto 0);
else
addr_r(1 downto 0) <= addr_r(1 downto 0) + 1;
end if;
c_en_r <= '1';
c_we_r <= '1';
byte_cnt <= byte_cnt - 1;
if byte_cnt = "00" then
sp_r <= sp_r+1;
state <= st_resync;
end if;
when st_read_io =>
-- Wait until memory I/O isn't busy
a_addr_r <= sp_r;
a_r <= data_i;
if mem_busy_i='0' then
state <= st_fetch;
a_we_r <= '1';
end if;
when st_write_io =>
-- [A]=B
sp_r <= sp_r+1;
write_en_o <= '1';
addr_r <= a_i(g_addr_size-1 downto 0);
state <= st_write_io_done;
when st_write_io_done =>
-- Wait until memory I/O isn't busy
if mem_busy_i='0' then
state <= st_resync;
end if;
when st_fetch =>
-- We need to resync. During this cycle
-- we'll fetch the opcode @ pc and thus it will
-- be available for st_execute in the next cycle
-- At this point a_i contains the value that is from the top of the stack
-- or that was fetched from the stack with an offset (loadsp)
a_we_r <= posted_wr_a;
a_r <= a_i;
a_addr_r <= sp_r;
b_addr_r <= sp_r+1;
state <= st_decode;
when st_decode =>
if interrupt_i='1' and in_irq_r='0' and idim_r='0' then
-- We got an interrupt, execute interrupt instead of next instruction
in_irq_r <= '1';
d_opcode_r <= dec_interrupt;
end if;
-- during the st_execute cycle we'll be fetching SP+1
a_addr_r <= sp_r;
b_addr_r <= sp_r+1;
state <= st_execute;
when st_add_sp =>
state <= st_add;
when st_add =>
a_addr_r <= sp_r;
a_we_r <= '1';
a_r <= a_i+b_i;
state <= st_fetch;
when st_or =>
a_addr_r <= sp_r;
a_we_r <= '1';
a_r <= a_i or b_i;
state <= st_fetch;
when st_and =>
a_addr_r <= sp_r;
a_we_r <= '1';
a_r <= a_i and b_i;
state <= st_fetch;
when st_resync =>
c_mux_r <= '0';
a_addr_r <= sp_r;
state <= st_fetch;
posted_wr_a <= posted_wr_a; -- keep
when others =>
null;
end case;
end if; -- else reset_i/='1'
end if; -- rising_edge(clk_i)
end process opcode_control;
addr_o <= addr_r;
end architecture Behave; -- Entity: zpu_tiny
|
-- Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2015.4 (win64) Build 1412921 Wed Nov 18 09:43:45 MST 2015
-- Date : Thu Jul 20 11:47:27 2017
-- Host : ACER-BLUES running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub
-- d:/Design_Project/E_elements/Project_BipedRobot/Project_BipedRobot.srcs/sources_1/ip/vio_0/vio_0_stub.vhdl
-- Design : vio_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7a35tcsg324-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity vio_0 is
Port (
clk : in STD_LOGIC;
probe_out0 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out1 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out2 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out3 : out STD_LOGIC_VECTOR ( 0 to 0 )
);
end vio_0;
architecture stub of vio_0 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "clk,probe_out0[0:0],probe_out1[0:0],probe_out2[0:0],probe_out3[0:0]";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of stub : architecture is "vio,Vivado 2015.4";
begin
end;
|
--------------------------------------------------------------------------------
-- Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: H.42
-- \ \ Application: netgen
-- / / Filename: contadorbinario_synthesis.vhd
-- /___/ /\ Timestamp: Tue Sep 20 14:51:22 2011
-- \ \ / \
-- \___\/\___\
--
-- Command : -intstyle ise -ar Structure -w -ofmt vhdl -sim contadorbinario.ngc contadorbinario_synthesis.vhd
-- Device : xc3s200-5-ft256
-- Input file : contadorbinario.ngc
-- Output file : contadorbinario_synthesis.vhd
-- # of Entities : 1
-- Design Name : contadorbinario
-- Xilinx : C:/Xilinx
--
-- Purpose:
-- This VHDL netlist is a verification model and uses simulation
-- primitives which may not represent the true implementation of the
-- device, however the netlist is functionally correct and should not
-- be modified. This file cannot be synthesized and should only be used
-- with supported simulation tools.
--
-- Reference:
-- Development System Reference Guide, Chapter 23
-- Synthesis and Verification Design Guide, Chapter 6
--
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity contadorbinario is
port (
reset : in STD_LOGIC := 'X';
count_direction : in STD_LOGIC := 'X';
clock : in STD_LOGIC := 'X';
clock_enable : in STD_LOGIC := 'X';
count : out STD_LOGIC_VECTOR ( 7 downto 0 )
);
end contadorbinario;
architecture Structure of contadorbinario is
signal reset_IBUF : STD_LOGIC;
signal count_direction_IBUF : STD_LOGIC;
signal clock_BUFGP : STD_LOGIC;
signal clock_enable_IBUF : STD_LOGIC;
signal Q_n0001 : STD_LOGIC;
signal count_temp_n0002 : STD_LOGIC;
signal N10 : STD_LOGIC;
signal N3 : STD_LOGIC;
signal contadorbinario_count_temp_n0000_0_cyo : STD_LOGIC;
signal N4 : STD_LOGIC;
signal contadorbinario_count_temp_n0000_1_cyo : STD_LOGIC;
signal N5 : STD_LOGIC;
signal contadorbinario_count_temp_n0000_2_cyo : STD_LOGIC;
signal N6 : STD_LOGIC;
signal contadorbinario_count_temp_n0000_3_cyo : STD_LOGIC;
signal N7 : STD_LOGIC;
signal contadorbinario_count_temp_n0000_4_cyo : STD_LOGIC;
signal N8 : STD_LOGIC;
signal contadorbinario_count_temp_n0000_5_cyo : STD_LOGIC;
signal N9 : STD_LOGIC;
signal contadorbinario_count_temp_n0000_6_cyo : STD_LOGIC;
signal count_temp : STD_LOGIC_VECTOR ( 7 downto 0 );
signal count_temp_n0000 : STD_LOGIC_VECTOR ( 7 downto 0 );
begin
count_temp_6 : FDE
port map (
D => count_temp_n0000(6),
CE => Q_n0001,
C => clock_BUFGP,
Q => count_temp(6)
);
count_temp_n00021_INV_0 : INV
port map (
I => count_direction_IBUF,
O => count_temp_n0002
);
Q_n00011 : LUT2
generic map(
INIT => X"2"
)
port map (
I0 => clock_enable_IBUF,
I1 => reset_IBUF,
O => Q_n0001
);
count_temp_7 : FDE
port map (
D => count_temp_n0000(7),
CE => Q_n0001,
C => clock_BUFGP,
Q => count_temp(7)
);
contadorbinario_count_temp_n0000_7_xor : XORCY
port map (
CI => contadorbinario_count_temp_n0000_6_cyo,
LI => N10,
O => count_temp_n0000(7)
);
count_temp_0 : FDE
port map (
D => count_temp_n0000(0),
CE => Q_n0001,
C => clock_BUFGP,
Q => count_temp(0)
);
count_temp_1 : FDE
port map (
D => count_temp_n0000(1),
CE => Q_n0001,
C => clock_BUFGP,
Q => count_temp(1)
);
count_temp_2 : FDE
port map (
D => count_temp_n0000(2),
CE => Q_n0001,
C => clock_BUFGP,
Q => count_temp(2)
);
count_temp_3 : FDE
port map (
D => count_temp_n0000(3),
CE => Q_n0001,
C => clock_BUFGP,
Q => count_temp(3)
);
count_temp_4 : FDE
port map (
D => count_temp_n0000(4),
CE => Q_n0001,
C => clock_BUFGP,
Q => count_temp(4)
);
count_temp_5 : FDE
port map (
D => count_temp_n0000(5),
CE => Q_n0001,
C => clock_BUFGP,
Q => count_temp(5)
);
contadorbinario_count_temp_n0000_7_lut : LUT2_L
generic map(
INIT => X"9"
)
port map (
I0 => count_temp(7),
I1 => count_direction_IBUF,
LO => N10
);
count_1_OBUF : OBUF
port map (
I => count_temp(1),
O => count(1)
);
count_0_OBUF : OBUF
port map (
I => count_temp(0),
O => count(0)
);
contadorbinario_count_temp_n0000_0_cy : MUXCY
port map (
CI => count_temp_n0002,
DI => count_temp(0),
S => N3,
O => contadorbinario_count_temp_n0000_0_cyo
);
contadorbinario_count_temp_n0000_0_xor : XORCY
port map (
CI => count_temp_n0002,
LI => N3,
O => count_temp_n0000(0)
);
contadorbinario_count_temp_n0000_0_lut : LUT2_L
generic map(
INIT => X"6"
)
port map (
I0 => count_direction_IBUF,
I1 => count_temp(0),
LO => N3
);
contadorbinario_count_temp_n0000_1_cy : MUXCY
port map (
CI => contadorbinario_count_temp_n0000_0_cyo,
DI => count_temp(1),
S => N4,
O => contadorbinario_count_temp_n0000_1_cyo
);
contadorbinario_count_temp_n0000_1_xor : XORCY
port map (
CI => contadorbinario_count_temp_n0000_0_cyo,
LI => N4,
O => count_temp_n0000(1)
);
contadorbinario_count_temp_n0000_1_lut : LUT2_L
generic map(
INIT => X"9"
)
port map (
I0 => count_direction_IBUF,
I1 => count_temp(1),
LO => N4
);
contadorbinario_count_temp_n0000_2_cy : MUXCY
port map (
CI => contadorbinario_count_temp_n0000_1_cyo,
DI => count_temp(2),
S => N5,
O => contadorbinario_count_temp_n0000_2_cyo
);
contadorbinario_count_temp_n0000_2_xor : XORCY
port map (
CI => contadorbinario_count_temp_n0000_1_cyo,
LI => N5,
O => count_temp_n0000(2)
);
contadorbinario_count_temp_n0000_2_lut : LUT2_L
generic map(
INIT => X"9"
)
port map (
I0 => count_direction_IBUF,
I1 => count_temp(2),
LO => N5
);
contadorbinario_count_temp_n0000_3_cy : MUXCY
port map (
CI => contadorbinario_count_temp_n0000_2_cyo,
DI => count_temp(3),
S => N6,
O => contadorbinario_count_temp_n0000_3_cyo
);
contadorbinario_count_temp_n0000_3_xor : XORCY
port map (
CI => contadorbinario_count_temp_n0000_2_cyo,
LI => N6,
O => count_temp_n0000(3)
);
contadorbinario_count_temp_n0000_3_lut : LUT2_L
generic map(
INIT => X"9"
)
port map (
I0 => count_direction_IBUF,
I1 => count_temp(3),
LO => N6
);
contadorbinario_count_temp_n0000_4_cy : MUXCY
port map (
CI => contadorbinario_count_temp_n0000_3_cyo,
DI => count_temp(4),
S => N7,
O => contadorbinario_count_temp_n0000_4_cyo
);
contadorbinario_count_temp_n0000_4_xor : XORCY
port map (
CI => contadorbinario_count_temp_n0000_3_cyo,
LI => N7,
O => count_temp_n0000(4)
);
contadorbinario_count_temp_n0000_4_lut : LUT2_L
generic map(
INIT => X"9"
)
port map (
I0 => count_direction_IBUF,
I1 => count_temp(4),
LO => N7
);
contadorbinario_count_temp_n0000_5_cy : MUXCY
port map (
CI => contadorbinario_count_temp_n0000_4_cyo,
DI => count_temp(5),
S => N8,
O => contadorbinario_count_temp_n0000_5_cyo
);
contadorbinario_count_temp_n0000_5_xor : XORCY
port map (
CI => contadorbinario_count_temp_n0000_4_cyo,
LI => N8,
O => count_temp_n0000(5)
);
contadorbinario_count_temp_n0000_5_lut : LUT2_L
generic map(
INIT => X"9"
)
port map (
I0 => count_direction_IBUF,
I1 => count_temp(5),
LO => N8
);
contadorbinario_count_temp_n0000_6_cy : MUXCY
port map (
CI => contadorbinario_count_temp_n0000_5_cyo,
DI => count_temp(6),
S => N9,
O => contadorbinario_count_temp_n0000_6_cyo
);
contadorbinario_count_temp_n0000_6_xor : XORCY
port map (
CI => contadorbinario_count_temp_n0000_5_cyo,
LI => N9,
O => count_temp_n0000(6)
);
contadorbinario_count_temp_n0000_6_lut : LUT2_L
generic map(
INIT => X"9"
)
port map (
I0 => count_direction_IBUF,
I1 => count_temp(6),
LO => N9
);
clock_BUFGP_0 : BUFGP
port map (
I => clock,
O => clock_BUFGP
);
reset_IBUF_1 : IBUF
port map (
I => reset,
O => reset_IBUF
);
count_direction_IBUF_2 : IBUF
port map (
I => count_direction,
O => count_direction_IBUF
);
clock_enable_IBUF_3 : IBUF
port map (
I => clock_enable,
O => clock_enable_IBUF
);
count_7_OBUF : OBUF
port map (
I => count_temp(7),
O => count(7)
);
count_6_OBUF : OBUF
port map (
I => count_temp(6),
O => count(6)
);
count_5_OBUF : OBUF
port map (
I => count_temp(5),
O => count(5)
);
count_4_OBUF : OBUF
port map (
I => count_temp(4),
O => count(4)
);
count_3_OBUF : OBUF
port map (
I => count_temp(3),
O => count(3)
);
count_2_OBUF : OBUF
port map (
I => count_temp(2),
O => count(2)
);
end Structure;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity hardware_interface is
Port ( ssegAnode : out STD_LOGIC_VECTOR (7 downto 0);
ssegCathode : out STD_LOGIC_VECTOR (7 downto 0);
slideSwitches : in STD_LOGIC_VECTOR (15 downto 0);
pushButtons : in STD_LOGIC_VECTOR (4 downto 0);
LEDs : out STD_LOGIC_VECTOR (15 downto 0);
clk100mhz : in STD_LOGIC;
logic_analyzer : out STD_LOGIC_VECTOR (7 downto 0)
);
end hardware_interface;
architecture Behavioral of hardware_interface is
component ssegDriver port (
clk : in std_logic;
rst : in std_logic;
cathode_p: out std_logic_vector(7 downto 0);
anode_p : out std_logic_vector(7 downto 0);
digit1_p : in std_logic_vector(3 downto 0);
digit2_p : in std_logic_vector(3 downto 0);
digit3_p : in std_logic_vector(3 downto 0);
digit4_p : in std_logic_vector(3 downto 0);
digit5_p : in std_logic_vector(3 downto 0);
digit6_p : in std_logic_vector(3 downto 0);
digit7_p : in std_logic_vector(3 downto 0);
digit8_p : in std_logic_vector(3 downto 0)
);
end component;
component bcd_counter port (
rst : in std_logic;
en : in std_logic;
bcd_out : out std_logic_vector(7 downto 0);
clk : in std_logic
);
end component;
--Central Button
signal masterReset : std_logic;
signal buttonLeft : std_logic;
signal buttonRight : std_logic;
signal buttonUp : std_logic;
signal buttonDown : std_logic;
signal displayLower : std_logic_vector(15 downto 0);
signal displayUpper : std_logic_vector(15 downto 0);
signal clockScalers : std_logic_vector (26 downto 0);
--Clock scaled signals
signal clk2Hz : std_logic := '0';
--Component Signals
signal en1 : std_logic := '0';
signal en2 : std_logic := '0';
--System Signals
TYPE timer_state_fsm IS (start, stop1, stop2);
signal timer_state : timer_state_fsm := stop2;
begin
u1 : ssegDriver port map (
clk => clockScalers(11),
rst => masterReset,
cathode_p => ssegCathode,
anode_p => ssegAnode,
digit1_p => displayLower (3 downto 0),
digit2_p => displayLower (7 downto 4),
digit3_p => displayLower (11 downto 8),
digit4_p => displayLower (15 downto 12),
digit5_p => displayUpper (3 downto 0),
digit6_p => displayUpper (7 downto 4),
digit7_p => displayUpper (11 downto 8),
digit8_p => displayUpper (15 downto 12)
);
k1 : bcd_counter port map (masterReset, en1, displayUpper(7 downto 0), clk2Hz);
k2 : bcd_counter port map (masterReset, en2, displayLower(7 downto 0), clk2Hz);
--Central Button
masterReset <= pushButtons(4);
buttonLeft <= pushButtons(3);
buttonRight <= pushButtons(0);
buttonUp <= pushButtons(2);
buttonDown <= pushButtons(1);
LEDs (15 downto 0) <= clockScalers(26 downto 11);
logic_analyzer (7 downto 0) <= clockScalers(26 downto 19);
--clk2Hz <= clockScalers(26);
-- 3 of 24
process (clockScalers(23), masterReset )
variable count_scaler : std_logic_vector(2 downto 0) := (others => '0');
begin
if (masterReset = '1') then
count_scaler := (others => '0');
elsif (clockScalers(23)'event and clockScalers(23) = '1') then
count_scaler := count_scaler + '1';
if (count_scaler = 3) then
clk2Hz <= not(clk2Hz);
count_scaler := (others => '0');
end if;
end if;
end process;
process (clk100mhz, masterReset) begin
if (masterReset = '1') then
clockScalers <= "000000000000000000000000000";
elsif (clk100mhz'event and clk100mhz = '1')then
clockScalers <= clockScalers + '1';
end if;
end process;
--en1 <= '1' when (timer_state = start) else '0'
process (masterReset, buttonDown) begin
if (masterReset = '1') then
timer_state <= stop2;
en1 <= '0';
en2 <= '0';
elsif (buttonDown'event and buttonDown = '1') then
case timer_state is
when stop2 =>
en1 <= '1';
en2 <= '1';
timer_state <= start;
when start =>
en1 <= '0';
timer_state <= stop1;
when stop1 =>
en2 <= '0';
timer_state <= stop2;
end case;
end if;
end process;
end Behavioral; |
architecture ARCH of ENTITY1 is
begin
U_INST1 : INST1
generic map (
G_GEN_1 => 3,
G_GEN_2 => 4,
G_GEN_3 => 5
)
port map (
PORT_1 => w_port_1,
PORT_2 => w_port_2,
PORT_3 => w_port_3
);
-- Violations below
U_INST1 : INST1
generic map (G_GEN_1 => 3,
G_GEN_2 => 4,
G_GEN_3 => 5
)
port map (
PORT_1 => w_port_1,
PORT_2 => w_port_2,
PORT_3 => w_port_3
);
U_INST1 : INST1
generic map ( G_GEN_1 => 1,
G_GEN_2 => 2,
G_GEN_3 => 3
);
end architecture ARCH;
|
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Authors: Patrick Lehmann
--
-- Module: A generic buffer module for the PoC.Stream protocol.
--
-- Description:
-- ------------------------------------
-- This module implements a generic buffer (FifO) for the PoC.Stream protocol.
-- It is generic in DATA_BITS and in META_BITS as well as in FifO depths for
-- data and meta information.
--
-- License:
-- ============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS of ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ============================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library PoC;
use PoC.config.all;
use PoC.utils.all;
use PoC.vectors.all;
entity Stream_Mux is
generic (
portS : POSITIVE := 2;
DATA_BITS : POSITIVE := 8;
META_BITS : NATURAL := 8;
META_REV_BITS : NATURAL := 2--;
-- WEIGHTS : T_INTVEC := (1, 1)
);
port (
Clock : in STD_LOGIC;
Reset : in STD_LOGIC;
-- IN Ports
In_Valid : in STD_LOGIC_VECTOR(portS - 1 downto 0);
In_Data : in T_SLM(portS - 1 downto 0, DATA_BITS - 1 downto 0);
In_Meta : in T_SLM(portS - 1 downto 0, META_BITS - 1 downto 0);
In_Meta_rev : out T_SLM(portS - 1 downto 0, META_REV_BITS - 1 downto 0);
In_SOF : in STD_LOGIC_VECTOR(portS - 1 downto 0);
In_EOF : in STD_LOGIC_VECTOR(portS - 1 downto 0);
In_Ack : out STD_LOGIC_VECTOR(portS - 1 downto 0);
-- OUT Port
Out_Valid : out STD_LOGIC;
Out_Data : out STD_LOGIC_VECTOR(DATA_BITS - 1 downto 0);
Out_Meta : out STD_LOGIC_VECTOR(META_BITS - 1 downto 0);
Out_Meta_rev : in STD_LOGIC_VECTOR(META_REV_BITS - 1 downto 0);
Out_SOF : out STD_LOGIC;
Out_EOF : out STD_LOGIC;
Out_Ack : in STD_LOGIC
);
end;
architecture rtl of Stream_Mux is
attribute KEEP : BOOLEAN;
attribute FSM_ENCODING : STRING;
subtype T_CHANNEL_INDEX is NATURAL range 0 to portS - 1;
type T_STATE is (ST_IDLE, ST_DATAFLOW);
signal State : T_STATE := ST_IDLE;
signal NextState : T_STATE;
signal FSM_Dataflow_en : STD_LOGIC;
signal RequestVector : STD_LOGIC_VECTOR(portS - 1 downto 0);
signal RequestWithSelf : STD_LOGIC;
signal RequestWithoutSelf : STD_LOGIC;
signal RequestLeft : UNSIGNED(portS - 1 downto 0);
signal SelectLeft : UNSIGNED(portS - 1 downto 0);
signal SelectRight : UNSIGNED(portS - 1 downto 0);
signal ChannelPointer_en : STD_LOGIC;
signal ChannelPointer : STD_LOGIC_VECTOR(portS - 1 downto 0);
signal ChannelPointer_d : STD_LOGIC_VECTOR(portS - 1 downto 0) := to_slv(2 ** (portS - 1), portS);
signal ChannelPointer_nxt : STD_LOGIC_VECTOR(portS - 1 downto 0);
signal ChannelPointer_bin : UNSIGNED(log2ceilnz(portS) - 1 downto 0);
signal idx : T_CHANNEL_INDEX;
signal Out_EOF_i : STD_LOGIC;
begin
RequestVector <= In_Valid and In_SOF;
RequestWithSelf <= slv_or(RequestVector);
RequestWithoutSelf <= slv_or(RequestVector and not ChannelPointer_d);
process(Clock)
begin
if rising_edge(Clock) then
if (Reset = '1') then
State <= ST_IDLE;
else
State <= NextState;
end if;
end if;
end process;
process(State, RequestWithSelf, RequestWithoutSelf, Out_Ack, Out_EOF_i, ChannelPointer_d, ChannelPointer_nxt)
begin
NextState <= State;
FSM_Dataflow_en <= '0';
ChannelPointer_en <= '0';
ChannelPointer <= ChannelPointer_d;
case State is
when ST_IDLE =>
if (RequestWithSelf = '1') then
ChannelPointer_en <= '1';
NextState <= ST_DATAFLOW;
end if;
when ST_DATAFLOW =>
FSM_Dataflow_en <= '1';
if ((Out_Ack and Out_EOF_i) = '1') then
if (RequestWithoutSelf = '0') then
NextState <= ST_IDLE;
else
ChannelPointer_en <= '1';
end if;
end if;
end case;
end process;
process(Clock)
begin
if rising_edge(Clock) then
if (Reset = '1') then
ChannelPointer_d <= to_slv(2 ** (portS - 1), portS);
elsif (ChannelPointer_en = '1') then
ChannelPointer_d <= ChannelPointer_nxt;
end if;
end if;
end process;
RequestLeft <= (not ((unsigned(ChannelPointer_d) - 1) or unsigned(ChannelPointer_d))) and unsigned(RequestVector);
SelectLeft <= (unsigned(not RequestLeft) + 1) and RequestLeft;
SelectRight <= (unsigned(not RequestVector) + 1) and unsigned(RequestVector);
ChannelPointer_nxt <= std_logic_vector(ite((RequestLeft = (RequestLeft'range => '0')), SelectRight, SelectLeft));
ChannelPointer_bin <= onehot2bin(ChannelPointer);
idx <= to_integer(ChannelPointer_bin);
Out_Data <= get_row(In_Data, idx);
Out_Meta <= get_row(In_Meta, idx);
Out_SOF <= In_SOF(to_integer(ChannelPointer_bin));
Out_EOF_i <= In_EOF(to_integer(ChannelPointer_bin));
Out_Valid <= In_Valid(to_integer(ChannelPointer_bin)) and FSM_Dataflow_en;
Out_EOF <= Out_EOF_i;
In_Ack <= (In_Ack 'range => (Out_Ack and FSM_Dataflow_en)) and ChannelPointer;
genMetaReverse_0 : if (META_REV_BITS = 0) generate
In_Meta_rev <= (others => (others => '0'));
end generate;
genMetaReverse_1 : if (META_REV_BITS > 0) generate
signal Temp_Meta_rev : T_SLM(portS - 1 downto 0, META_REV_BITS - 1 downto 0) := (others => (others => 'Z'));
begin
genAssign : for i in 0 to portS - 1 generate
signal row : STD_LOGIC_VECTOR(META_REV_BITS - 1 downto 0);
begin
row <= Out_Meta_rev and (row'range => ChannelPointer(i));
assign_row(Temp_Meta_rev, row, i);
end generate;
In_Meta_rev <= Temp_Meta_rev;
end generate;
end architecture;
|
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Authors: Patrick Lehmann
--
-- Module: A generic buffer module for the PoC.Stream protocol.
--
-- Description:
-- ------------------------------------
-- This module implements a generic buffer (FifO) for the PoC.Stream protocol.
-- It is generic in DATA_BITS and in META_BITS as well as in FifO depths for
-- data and meta information.
--
-- License:
-- ============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS of ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ============================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library PoC;
use PoC.config.all;
use PoC.utils.all;
use PoC.vectors.all;
entity Stream_Mux is
generic (
portS : POSITIVE := 2;
DATA_BITS : POSITIVE := 8;
META_BITS : NATURAL := 8;
META_REV_BITS : NATURAL := 2--;
-- WEIGHTS : T_INTVEC := (1, 1)
);
port (
Clock : in STD_LOGIC;
Reset : in STD_LOGIC;
-- IN Ports
In_Valid : in STD_LOGIC_VECTOR(portS - 1 downto 0);
In_Data : in T_SLM(portS - 1 downto 0, DATA_BITS - 1 downto 0);
In_Meta : in T_SLM(portS - 1 downto 0, META_BITS - 1 downto 0);
In_Meta_rev : out T_SLM(portS - 1 downto 0, META_REV_BITS - 1 downto 0);
In_SOF : in STD_LOGIC_VECTOR(portS - 1 downto 0);
In_EOF : in STD_LOGIC_VECTOR(portS - 1 downto 0);
In_Ack : out STD_LOGIC_VECTOR(portS - 1 downto 0);
-- OUT Port
Out_Valid : out STD_LOGIC;
Out_Data : out STD_LOGIC_VECTOR(DATA_BITS - 1 downto 0);
Out_Meta : out STD_LOGIC_VECTOR(META_BITS - 1 downto 0);
Out_Meta_rev : in STD_LOGIC_VECTOR(META_REV_BITS - 1 downto 0);
Out_SOF : out STD_LOGIC;
Out_EOF : out STD_LOGIC;
Out_Ack : in STD_LOGIC
);
end;
architecture rtl of Stream_Mux is
attribute KEEP : BOOLEAN;
attribute FSM_ENCODING : STRING;
subtype T_CHANNEL_INDEX is NATURAL range 0 to portS - 1;
type T_STATE is (ST_IDLE, ST_DATAFLOW);
signal State : T_STATE := ST_IDLE;
signal NextState : T_STATE;
signal FSM_Dataflow_en : STD_LOGIC;
signal RequestVector : STD_LOGIC_VECTOR(portS - 1 downto 0);
signal RequestWithSelf : STD_LOGIC;
signal RequestWithoutSelf : STD_LOGIC;
signal RequestLeft : UNSIGNED(portS - 1 downto 0);
signal SelectLeft : UNSIGNED(portS - 1 downto 0);
signal SelectRight : UNSIGNED(portS - 1 downto 0);
signal ChannelPointer_en : STD_LOGIC;
signal ChannelPointer : STD_LOGIC_VECTOR(portS - 1 downto 0);
signal ChannelPointer_d : STD_LOGIC_VECTOR(portS - 1 downto 0) := to_slv(2 ** (portS - 1), portS);
signal ChannelPointer_nxt : STD_LOGIC_VECTOR(portS - 1 downto 0);
signal ChannelPointer_bin : UNSIGNED(log2ceilnz(portS) - 1 downto 0);
signal idx : T_CHANNEL_INDEX;
signal Out_EOF_i : STD_LOGIC;
begin
RequestVector <= In_Valid and In_SOF;
RequestWithSelf <= slv_or(RequestVector);
RequestWithoutSelf <= slv_or(RequestVector and not ChannelPointer_d);
process(Clock)
begin
if rising_edge(Clock) then
if (Reset = '1') then
State <= ST_IDLE;
else
State <= NextState;
end if;
end if;
end process;
process(State, RequestWithSelf, RequestWithoutSelf, Out_Ack, Out_EOF_i, ChannelPointer_d, ChannelPointer_nxt)
begin
NextState <= State;
FSM_Dataflow_en <= '0';
ChannelPointer_en <= '0';
ChannelPointer <= ChannelPointer_d;
case State is
when ST_IDLE =>
if (RequestWithSelf = '1') then
ChannelPointer_en <= '1';
NextState <= ST_DATAFLOW;
end if;
when ST_DATAFLOW =>
FSM_Dataflow_en <= '1';
if ((Out_Ack and Out_EOF_i) = '1') then
if (RequestWithoutSelf = '0') then
NextState <= ST_IDLE;
else
ChannelPointer_en <= '1';
end if;
end if;
end case;
end process;
process(Clock)
begin
if rising_edge(Clock) then
if (Reset = '1') then
ChannelPointer_d <= to_slv(2 ** (portS - 1), portS);
elsif (ChannelPointer_en = '1') then
ChannelPointer_d <= ChannelPointer_nxt;
end if;
end if;
end process;
RequestLeft <= (not ((unsigned(ChannelPointer_d) - 1) or unsigned(ChannelPointer_d))) and unsigned(RequestVector);
SelectLeft <= (unsigned(not RequestLeft) + 1) and RequestLeft;
SelectRight <= (unsigned(not RequestVector) + 1) and unsigned(RequestVector);
ChannelPointer_nxt <= std_logic_vector(ite((RequestLeft = (RequestLeft'range => '0')), SelectRight, SelectLeft));
ChannelPointer_bin <= onehot2bin(ChannelPointer);
idx <= to_integer(ChannelPointer_bin);
Out_Data <= get_row(In_Data, idx);
Out_Meta <= get_row(In_Meta, idx);
Out_SOF <= In_SOF(to_integer(ChannelPointer_bin));
Out_EOF_i <= In_EOF(to_integer(ChannelPointer_bin));
Out_Valid <= In_Valid(to_integer(ChannelPointer_bin)) and FSM_Dataflow_en;
Out_EOF <= Out_EOF_i;
In_Ack <= (In_Ack 'range => (Out_Ack and FSM_Dataflow_en)) and ChannelPointer;
genMetaReverse_0 : if (META_REV_BITS = 0) generate
In_Meta_rev <= (others => (others => '0'));
end generate;
genMetaReverse_1 : if (META_REV_BITS > 0) generate
signal Temp_Meta_rev : T_SLM(portS - 1 downto 0, META_REV_BITS - 1 downto 0) := (others => (others => 'Z'));
begin
genAssign : for i in 0 to portS - 1 generate
signal row : STD_LOGIC_VECTOR(META_REV_BITS - 1 downto 0);
begin
row <= Out_Meta_rev and (row'range => ChannelPointer(i));
assign_row(Temp_Meta_rev, row, i);
end generate;
In_Meta_rev <= Temp_Meta_rev;
end generate;
end architecture;
|
--------------------------------------------------------------------------------
--This file is part of fpga_gpib_controller.
--
-- Fpga_gpib_controller is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- Fpga_gpib_controller is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with Fpga_gpib_controller. If not, see <http://www.gnu.org/licenses/>.
--------------------------------------------------------------------------------
-- Author: Andrzej Paluch
--
-- Create Date: 23:21:05 10/21/2011
-- Design Name:
-- Module Name: /windows/h/projekty/elektronika/USB_to_HPIB/usbToHpib/test_scr//gpibInterfaceTest.vhd
-- Project Name: usbToHpib
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: gpibInterface
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
use work.gpibComponents.all;
use work.helperComponents.all;
ENTITY gpib_TE_LE_Test IS
END gpib_TE_LE_Test;
ARCHITECTURE behavior OF gpib_TE_LE_Test IS
-- Component Declaration for the Unit Under Test (UUT)
component gpibCableEmulator is port (
-- interface signals
DIO_1 : in std_logic_vector (7 downto 0);
output_valid_1 : in std_logic;
DIO_2 : in std_logic_vector (7 downto 0);
output_valid_2 : in std_logic;
DIO : out std_logic_vector (7 downto 0);
-- attention
ATN_1 : in std_logic;
ATN_2 : in std_logic;
ATN : out std_logic;
-- data valid
DAV_1 : in std_logic;
DAV_2 : in std_logic;
DAV : out std_logic;
-- not ready for data
NRFD_1 : in std_logic;
NRFD_2 : in std_logic;
NRFD : out std_logic;
-- no data accepted
NDAC_1 : in std_logic;
NDAC_2 : in std_logic;
NDAC : out std_logic;
-- end or identify
EOI_1 : in std_logic;
EOI_2 : in std_logic;
EOI : out std_logic;
-- service request
SRQ_1 : in std_logic;
SRQ_2 : in std_logic;
SRQ : out std_logic;
-- interface clear
IFC_1 : in std_logic;
IFC_2 : in std_logic;
IFC : out std_logic;
-- remote enable
REN_1 : in std_logic;
REN_2 : in std_logic;
REN : out std_logic
);
end component;
-- inputs common
signal clk : std_logic := '0';
signal reset : std_logic := '0';
signal T1 : std_logic_vector(7 downto 0) := "00000100";
-- inputs 1
signal data_1 : std_logic_vector(7 downto 0) := (others => '0');
signal status_byte_1 : std_logic_vector(7 downto 0) := (others => '0');
signal rdy_1 : std_logic := '0';
signal nba_1 : std_logic := '0';
signal ltn_1 : std_logic := '0';
signal lun_1 : std_logic := '0';
signal lon_1 : std_logic := '0';
signal ton_1 : std_logic := '0';
signal endOf_1 : std_logic := '0';
signal gts_1 : std_logic := '0';
signal rpp_1 : std_logic := '0';
signal tcs_1 : std_logic := '0';
signal tca_1 : std_logic := '0';
signal sic_1 : std_logic := '0';
signal rsc_1 : std_logic := '0';
signal sre_1 : std_logic := '0';
signal rtl_1 : std_logic := '0';
signal rsv_1 : std_logic := '0';
signal ist_1 : std_logic := '0';
signal lpe_1 : std_logic := '0';
-- inputs 2
signal data_2 : std_logic_vector(7 downto 0) := (others => '0');
signal status_byte_2 : std_logic_vector(7 downto 0) := (others => '0');
signal rdy_2 : std_logic := '0';
signal nba_2 : std_logic := '0';
signal ltn_2 : std_logic := '0';
signal lun_2 : std_logic := '0';
signal lon_2 : std_logic := '0';
signal ton_2 : std_logic := '0';
signal endOf_2 : std_logic := '0';
signal gts_2 : std_logic := '0';
signal rpp_2 : std_logic := '0';
signal tcs_2 : std_logic := '0';
signal tca_2 : std_logic := '0';
signal sic_2 : std_logic := '0';
signal rsc_2 : std_logic := '0';
signal sre_2 : std_logic := '0';
signal rtl_2 : std_logic := '0';
signal rsv_2 : std_logic := '0';
signal ist_2 : std_logic := '0';
signal lpe_2 : std_logic := '0';
-- outputs 1
signal dvd_1 : std_logic;
signal wnc_1 : std_logic;
signal tac_1 : std_logic;
signal lac_1 : std_logic;
signal cwrc_1 : std_logic;
signal cwrd_1 : std_logic;
signal clr_1 : std_logic;
signal trg_1 : std_logic;
signal atl_1 : std_logic;
signal att_1 : std_logic;
signal mla_1 : std_logic;
signal lsb_1 : std_logic;
signal spa_1 : std_logic;
signal ppr_1 : std_logic;
signal sreq_1 : std_logic;
signal isLocal_1 : std_logic;
signal currentSecAddr_1 : std_logic_vector (4 downto 0);
-- outputs 2
signal dvd_2 : std_logic;
signal wnc_2 : std_logic;
signal tac_2 : std_logic;
signal lac_2 : std_logic;
signal cwrc_2 : std_logic;
signal cwrd_2 : std_logic;
signal clr_2 : std_logic;
signal trg_2 : std_logic;
signal atl_2 : std_logic;
signal att_2 : std_logic;
signal mla_2 : std_logic;
signal lsb_2 : std_logic;
signal spa_2 : std_logic;
signal ppr_2 : std_logic;
signal sreq_2 : std_logic;
signal isLocal_2 : std_logic;
signal currentSecAddr_2 : std_logic_vector (4 downto 0);
-- common
signal DO : std_logic_vector (7 downto 0);
signal DI_1 : std_logic_vector (7 downto 0);
signal output_valid_1 : std_logic;
signal DI_2 : std_logic_vector (7 downto 0);
signal output_valid_2 : std_logic;
signal ATN_1, ATN_2, ATN : std_logic;
signal DAV_1, DAV_2, DAV : std_logic;
signal NRFD_1, NRFD_2, NRFD : std_logic;
signal NDAC_1, NDAC_2, NDAC : std_logic;
signal EOI_1, EOI_2, EOI : std_logic;
signal SRQ_1, SRQ_2, SRQ : std_logic;
signal IFC_1, IFC_2, IFC : std_logic;
signal REN_1, REN_2, REN : std_logic;
-- gpib reader
signal buf_interrupt : std_logic;
signal data_available : std_logic;
signal last_byte_addr : std_logic_vector (3 downto 0);
signal end_of_stream : std_logic;
signal byte_addr : std_logic_vector (3 downto 0);
signal data_out : std_logic_vector (7 downto 0);
signal reset_buffer : std_logic := '0';
signal dataSecAddr : std_logic_vector (4 downto 0);
-- gpib writer
signal w_last_byte_addr : std_logic_vector (3 downto 0)
:= (others => '0');
signal w_end_of_stream : std_logic := '0';
signal w_data_available : std_logic := '0';
signal w_buf_interrupt : std_logic;
signal w_data_in : std_logic_vector (7 downto 0);
signal w_byte_addr : std_logic_vector (3 downto 0);
signal w_reset_buffer : std_logic := '0';
signal w_dataSecAddr : std_logic_vector (4 downto 0);
type WR_BUF_TYPE is
array (0 to 15) of std_logic_vector (7 downto 0);
signal w_write_buffer : WR_BUF_TYPE;
-- Clock period definitions
constant clk_period : time := 2ps;
BEGIN
-- Instantiate the Unit Under Test (UUT)
gpib1: gpibInterface PORT MAP (
clk => clk,
reset => reset,
isLE => '1',
isTE => '1',
lpeUsed => '0',
fixedPpLine => "000",
eosUsed => '0',
eosMark => "00000000",
myListAddr => "00001",
myTalkAddr => "00001",
secAddrMask => "00000000000000000000000000000110",
data => data_1,
status_byte => status_byte_1,
T1 => T1,
rdy => rdy_1,
nba => nba_1,
ltn => ltn_1,
lun => lun_1,
lon => lon_1,
ton => ton_1,
endOf => endOf_1,
gts => gts_1,
rpp => rpp_1,
tcs => tcs_1,
tca => tca_1,
sic => sic_1,
rsc => rsc_1,
sre => sre_1,
rtl => rtl_1,
rsv => rsv_1,
ist => ist_1,
lpe => lpe_1,
dvd => dvd_1,
wnc => wnc_1,
tac => tac_1,
lac => lac_1,
cwrc => cwrc_1,
cwrd => cwrd_1,
clr => clr_1,
trg => trg_1,
atl => atl_1,
att => att_1,
mla => mla_1,
lsb => lsb_1,
spa => spa_1,
ppr => ppr_1,
sreq => sreq_1,
isLocal => isLocal_1,
currentSecAddr => currentSecAddr_1,
DI => DO,
DO => DI_1,
output_valid => output_valid_1,
ATN_in => ATN,
ATN_out => ATN_1,
DAV_in => DAV,
DAV_out => DAV_1,
NRFD_in => NRFD,
NRFD_out => NRFD_1,
NDAC_in => NDAC,
NDAC_out => NDAC_1,
EOI_in => EOI,
EOI_out => EOI_1,
SRQ_in => SRQ,
SRQ_out => SRQ_1,
IFC_in => IFC,
IFC_out => IFC_1,
REN_in => REN,
REN_out => REN_1
);
-- Instantiate the Unit Under Test (UUT)
gpib2: gpibInterface PORT MAP (
clk => clk,
reset => reset,
isLE => '1',
isTE => '1',
lpeUsed => '0',
fixedPpLine => "000",
eosUsed => '0',
eosMark => "00000000",
myListAddr => "00010",
myTalkAddr => "00010",
secAddrMask => "00000000000000000000000000000110",
data => data_2,
status_byte => status_byte_2,
T1 => T1,
rdy => rdy_2,
nba => nba_2,
ltn => ltn_2,
lun => lun_2,
lon => lon_2,
ton => ton_2,
endOf => endOf_2,
gts => gts_2,
rpp => rpp_2,
tcs => tcs_2,
tca => tca_2,
sic => sic_2,
rsc => rsc_2,
sre => sre_2,
rtl => rtl_2,
rsv => rsv_2,
ist => ist_2,
lpe => lpe_2,
dvd => dvd_2,
wnc => wnc_2,
tac => tac_2,
lac => lac_2,
cwrc => cwrc_2,
cwrd => cwrd_2,
clr => clr_2,
trg => trg_2,
atl => atl_2,
att => att_2,
mla => mla_2,
lsb => lsb_2,
spa => spa_2,
ppr => ppr_2,
sreq => sreq_2,
isLocal => isLocal_2,
currentSecAddr => currentSecAddr_2,
DI => DO,
DO => DI_2,
output_valid => output_valid_2,
ATN_in => ATN,
ATN_out => ATN_2,
DAV_in => DAV,
DAV_out => DAV_2,
NRFD_in => NRFD,
NRFD_out => NRFD_2,
NDAC_in => NDAC,
NDAC_out => NDAC_2,
EOI_in => EOI,
EOI_out => EOI_2,
SRQ_in => SRQ,
SRQ_out => SRQ_2,
IFC_in => IFC,
IFC_out => IFC_2,
REN_in => REN,
REN_out => REN_2
);
ce: gpibCableEmulator port map (
-- interface signals
DIO_1 => DI_1,
output_valid_1 => output_valid_1,
DIO_2 => DI_2,
output_valid_2 => output_valid_2,
DIO => DO,
-- attention
ATN_1 => ATN_1, ATN_2 => ATN_2, ATN => ATN,
DAV_1 => DAV_1, DAV_2 => DAV_2, DAV => DAV,
NRFD_1 => NRFD_1, NRFD_2 => NRFD_2, NRFD => NRFD,
NDAC_1 => NDAC_1, NDAC_2 => NDAC_2, NDAC => NDAC,
EOI_1 => EOI_1, EOI_2 => EOI_2, EOI => EOI,
SRQ_1 => SRQ_1, SRQ_2 => SRQ_2, SRQ => SRQ,
IFC_1 => IFC_1, IFC_2 => IFC_2, IFC => IFC,
REN_1 => REN_1, REN_2 => REN_2, REN => REN
);
gr: gpibReader generic map (ADDR_WIDTH => 4) port map (
clk => clk, reset => reset,
------------------------------------------------------------------------
------ GPIB interface --------------------------------------------------
------------------------------------------------------------------------
data_in => DO, dvd => dvd_2, lac => lac_2, lsb => lsb_2, rdy => rdy_2,
------------------------------------------------------------------------
------ external interface ----------------------------------------------
------------------------------------------------------------------------
isLE => '1', secAddr => currentSecAddr_1, dataSecAddr => dataSecAddr,
buf_interrupt => buf_interrupt, data_available => data_available,
last_byte_addr => last_byte_addr, end_of_stream => end_of_stream,
byte_addr => byte_addr, data_out => data_out,
reset_buffer => reset_buffer
);
w_data_in <= w_write_buffer(conv_integer(w_byte_addr));
gw: gpibWriter generic map (ADDR_WIDTH => 4) port map (
clk => clk, reset => reset,
------------------------------------------------------------------------
------ GPIB interface --------------------------------------------------
------------------------------------------------------------------------
data_out => data_1, wnc => wnc_1, spa => spa_1, nba => nba_1,
endOf => endOf_1, tac => tac_1, cwrc => cwrc_1,
------------------------------------------------------------------------
------ external interface ----------------------------------------------
------------------------------------------------------------------------
isTE => '1', secAddr => currentSecAddr_1, dataSecAddr => w_dataSecAddr,
last_byte_addr => w_last_byte_addr, end_of_stream => w_end_of_stream,
data_available => w_data_available, buf_interrupt => w_buf_interrupt,
data_in => w_data_in, byte_addr => w_byte_addr,
reset_buffer => w_reset_buffer
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 10 clock periods.
reset <= '1';
wait for clk_period*10;
reset <= '0';
wait for clk_period*10;
-- requests system control
rsc_1 <= '1';
-- interface clear
sic_1 <= '1';
wait until IFC_1 = '1';
sic_1 <= '0';
wait until IFC_1 = '0';
-- gpib2 to listen
w_write_buffer(0) <= "00100010";
w_write_buffer(1) <= "01100010";
-- gpib1 to talk
w_write_buffer(2) <= "01000001";
w_write_buffer(3) <= "01100010";
w_last_byte_addr <= "0011";
w_data_available <= '1';
wait until w_buf_interrupt='1';
gts_1 <= '1';
wait until ATN='0';
w_reset_buffer <= '1';
wait for clk_period*2;
w_reset_buffer <= '0';
w_dataSecAddr <= "00010";
wait for clk_period*1;
w_write_buffer(0) <= "10101010";
w_write_buffer(1) <= "01010101";
w_write_buffer(2) <= "11111111";
w_last_byte_addr <= "0010";
w_end_of_stream <= '1';
w_data_available <= '1';
wait until buf_interrupt='1';
byte_addr <= "0000";
wait for clk_period*1;
assert data_out = "10101010";
byte_addr <= "0001";
wait for clk_period*1;
assert data_out = "01010101";
byte_addr <= "0010";
wait for clk_period*1;
assert data_out = "11111111";
report "$$$ END OF TEST - TE / LE $$$";
wait;
end process;
END;
|
-- (C) 2001-2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- Alex, 02-10-07, this package declaration results in error at built time on a new machine
--
use work.auk_dspip_math_pkg_hpfir.all;
package auk_dspip_lib_pkg_hpfir is
--Component names:
--auk_dspip_atlantic_sink
--auk_dspip_atlantic_source
--auk_dspip_interface_controller
--auk_dspip_avalon_streaming_controller_hpfir
--auk_dspip_avalon_streaming_controller_pe_fir_91
--auk_dspip_avalon_streaming_sink_hpfir
--auk_dspip_avalon_streaming_source_hpfir
--auk_dspip_delay_fir_91
--auk_dspip_fastadd_fir_91
--auk_dspip_fastaddsub_fir_91
--auk_dspip_pipelined_adder_fir_91
--auk_dspip_fast_accumulator_fir_91
--auk_dspip_fifo_pfc_fir_91
--auk_dspip_fpcompiler_alufp
--auk_dspip_fpcompiler_aslf
--auk_dspip_fpcompiler_asrf
--auk_dspip_fpcompiler_castftox
--auk_dspip_fpcompiler_castxtof
--auk_dspip_fpcompiler_clzf
--auk_dspip_fpcompiler_mulfp
--auk_dspip_pfc_fir_91
--auk_dspip_roundsat_fir_91
component auk_dspip_atlantic_sink is
generic(
WIDTH : integer := 16;
PACKET_SIZE : natural := 4;
log2packet_size : integer := 2
);
port(
clk : in std_logic;
reset_n : in std_logic;
----------------- DESIGN SIDE SIGNALS
data_available : out std_logic; --goes high when new data is available
data : out std_logic_vector(WIDTH-1 downto 0);
sink_ready_ctrl : in std_logic; --the controller will tell
--the interface whether
--new input can be accepted.
sink_stall : out std_logic; --needs to stall the design
--if no new data is coming
packet_error : out std_logic_vector (1 downto 0); --this is for SOP and EOP check only.
--when any of these doesn't behave as
--expected, the error is flagged.
send_sop : out std_logic; -- transmit SOP signal to the design.
-- It only transmits the legal SOP.
send_eop : out std_logic; -- transmit EOP signal to the design.
-- It only transmits the legal EOP.
----------------- ATLANTIC SIDE SIGNALS
at_sink_ready : out std_logic; --it will be '1' whenever the
--sink_ready_ctrl signal is high.
at_sink_valid : in std_logic;
at_sink_data : in std_logic_vector(WIDTH-1 downto 0);
at_sink_sop : in std_logic := '0';
at_sink_eop : in std_logic := '0';
at_sink_error : in std_logic_vector(1 downto 0) --it indicates to the data source
--that the SOP and EOP signals
--are not received as expected.
);
end component auk_dspip_atlantic_sink;
component auk_dspip_atlantic_source is
generic(
WIDTH : integer := 16;
packet_size : natural := 4;
LOG2packet_size : integer := 2;
multi_channel : BOOLEAN := TRUE
);
port(
clk : in std_logic;
reset_n : in std_logic;
----------------- DESIGN SIDE SIGNALS
data : in std_logic_vector (WIDTH-1 downto 0);
data_count : in std_logic_vector (LOG2packet_size-1 downto 0) := (others => '0');
source_valid_ctrl : in std_logic; --the controller will tell
--the interface whether
--new input can be accepted.
source_stall : out std_logic; --needs to stall the design
--if no new data is coming
packet_error : in std_logic_vector (1 downto 0);
----------------- ATLANTIC SIDE SIGNALS
at_source_ready : in std_logic;
at_source_valid : out std_logic;
at_source_data : out std_logic_vector (WIDTH-1 downto 0);
at_source_channel : out std_logic_vector (log2packet_size-1 downto 0);
at_source_error : out std_logic_vector (1 downto 0);
at_source_sop : out std_logic;
at_source_eop : out std_logic
);
-- Declarations
end component auk_dspip_atlantic_source;
component auk_dspip_interface_controller IS
PORT(
clk : in std_logic;
reset : IN std_logic;
ready : in std_logic;
sink_packet_error : IN std_logic_vector (1 DOWNTO 0);
sink_stall : IN std_logic;
source_stall : IN std_logic;
valid : IN std_logic;
reset_design : OUT std_logic;
reset_n : OUT std_logic;
sink_ready_ctrl : OUT std_logic;
source_packet_error : OUT std_logic_vector (1 DOWNTO 0);
source_valid_ctrl : OUT std_logic;
stall : OUT std_logic
);
-- Declarations
end component auk_dspip_interface_controller ;
component auk_dspip_avalon_streaming_controller_hpfir is
port(
clk : in std_logic;
--clk_en : in std_logic := '1';
reset_n : in std_logic;
--ready : in std_logic;
sink_packet_error : in std_logic_vector (1 downto 0);
--sink_stall : in std_logic;
source_stall : in std_logic;
valid : in std_logic;
reset_design : out std_logic;
sink_ready_ctrl : out std_logic;
source_packet_error : out std_logic_vector (1 downto 0);
source_valid_ctrl : out std_logic;
stall : out std_logic
);
-- Declarations
end component auk_dspip_avalon_streaming_controller_hpfir;
component auk_dspip_avalon_streaming_controller_pe_fir_91 is
generic (
FIFO_WIDTH_g : natural := 8;
ENABLE_PIPELINE_DEPTH_g : natural := 0; -- this value should match the depth of the enable pipeline in the core
FAMILY_g : string := "Stratix II";
MEM_TYPE_g : string := "Auto"
);
port(
clk : in std_logic;
clk_en : in std_logic := '1';
reset_n : in std_logic;
ready : in std_logic;
sink_packet_error : in std_logic_vector (1 downto 0);
sink_stall : in std_logic;
source_stall : in std_logic;
valid : in std_logic;
reset_design : out std_logic;
sink_ready_ctrl : out std_logic;
source_packet_error : out std_logic_vector (1 downto 0);
source_valid_ctrl : out std_logic;
stall : out std_logic;
data_in : in std_logic_vector(FIFO_WIDTH_g-1 downto 0);
data_out : out std_logic_vector(FIFO_WIDTH_g-1 downto 0);
design_stall : out std_logic
);
-- Declarations
end component auk_dspip_avalon_streaming_controller_pe_fir_91;
component auk_dspip_avalon_streaming_sink_hpfir is
generic(
WIDTH_g : integer := 16;
DATA_WIDTH : integer := 8;
DATA_PORT_COUNT : integer := 3;
PACKET_SIZE_g : natural := 4
--FIFO_DEPTH_g : natural := 5 --if PFC mode is selected, this generic
--is used for passing the poly_factor.
--MIN_DATA_COUNT_g : natural := 2;
--PFC_MODE_g : boolean := false;
--SOP_EOP_CALC_g : boolean := false; -- calculate sop and eop rather than
-- reading value from fifo
--FAMILY_g : string := "Stratix II";
--MEM_TYPE_g : string := "Auto"
);
port(
clk : in std_logic;
reset_n : in std_logic;
----------------- DESIGN SIDE SIGNALS
data : out std_logic_vector(WIDTH_g-1 downto 0);
data_valid : out std_logic_vector(0 downto 0);
sink_ready_ctrl : in std_logic; --the controller will tell
--the interface whether
--new input can be accepted.
--sink_stall : out std_logic; --needs to stall the design
--if no new data is coming
packet_error : out std_logic_vector (1 downto 0); --this is for SOP and EOP check only.
--when any of these doesn't behave as
--expected, the error is flagged.
--send_sop : out std_logic; -- transmit SOP signal to the design.
-- It only transmits the legal SOP.
--send_eop : out std_logic; -- transmit EOP signal to the design.
-- It only transmits the legal EOP.
----------------- ATLANTIC SIDE SIGNALS
at_sink_ready : out std_logic; --it will be '1' whenever the
--sink_ready_ctrl signal is high.
at_sink_valid : in std_logic;
at_sink_data : in std_logic_vector(WIDTH_g-1 downto 0);
at_sink_sop : in std_logic := '0';
at_sink_eop : in std_logic := '0';
at_sink_error : in std_logic_vector(1 downto 0) := "00" --it indicates
--that there is an error in the packet.
);
end component auk_dspip_avalon_streaming_sink_hpfir;
component auk_dspip_avalon_streaming_source_hpfir is
generic(
WIDTH_g : integer := 8;
DATA_WIDTH : integer := 8;
DATA_PORT_COUNT : integer := 1;
PACKET_SIZE_g : natural := 2;
FIFO_DEPTH_g : natural := 0;
HAVE_COUNTER_g : boolean := false;
COUNTER_LIMIT_g : natural := 4;
--MULTI_CHANNEL_g : boolean := true;
USE_PACKETS : integer := 1;
--FAMILY_g : string := "Stratix II";
--MEM_TYPE_g : string := "Auto";
ENABLE_BACKPRESSURE_g : boolean := true
);
port(
clk : in std_logic;
reset_n : in std_logic;
----------------- DESIGN SIDE SIGNALS
data_in : in std_logic_vector (WIDTH_g-1 downto 0);
data_count : in std_logic_vector (log2_ceil_one(PACKET_SIZE_g)-1 downto 0) := (others => '0');
source_valid_ctrl : in std_logic;
source_stall : out std_logic;
packet_error : in std_logic_vector (1 downto 0);
----------------- AVALON_STREAMING SIDE SIGNALS
at_source_ready : in std_logic;
at_source_valid : out std_logic;
at_source_data : out std_logic_vector (WIDTH_g-1 downto 0);
at_source_channel : out std_logic_vector (log2_ceil_one(PACKET_SIZE_g)-1 downto 0);
at_source_error : out std_logic_vector (1 downto 0);
at_source_sop : out std_logic;
at_source_eop : out std_logic
);
-- Declarations
end component auk_dspip_avalon_streaming_source_hpfir;
component auk_dspip_roundsat_hpfir is
generic (
IN_WIDTH_g : natural := 8; -- i/p data width
REM_LSB_BIT_g : natural := 2; -- no. of lsb to be removed
REM_LSB_TYPE_g : string := "Truncation"; -- TRUNCATE/ROUND_UP
REM_MSB_BIT_g : natural := 2; -- no. of msb to be removed
REM_MSB_TYPE_g : string := "Truncation" -- TRUNCATE/SATURATE
);
port (
clk : in std_logic;
reset_n : in std_logic;
enable : in std_logic;
datain : in std_logic_vector(IN_WIDTH_g-1 downto 0);
valid : out std_logic;
dataout : out std_logic_vector(IN_WIDTH_g-REM_LSB_BIT_g-REM_MSB_BIT_g-1 downto 0)
);
end component auk_dspip_roundsat_hpfir;
component auk_dspip_delay_fir_91 is
generic (
WIDTH_g : natural := 8; -- data width
DELAY_g : natural := 8;
-- number of clock cycles the input
-- will be delayed by
MEMORY_TYPE_g : string := "AUTO";
-- possible values are "m4k", "m512",
-- "register", "mram", "auto",
-- "lutram", "M9K", "M144K".
-- Any other string will be interpreted
-- as "auto"
REGISTER_FIRST_g : natural := 1;
-- if "1", the first delay is guaranteed
-- to be in registers
REGISTER_LAST_g : natural := 1); -- if "1", the last delay is guaranteed
-- to be in registers
port (
clk : in std_logic;
reset : in std_logic;
enable : in std_logic; -- global clock enable
datain : in std_logic_vector(WIDTH_g-1 downto 0);
dataout : out std_logic_vector(WIDTH_g-1 downto 0)
);
end component auk_dspip_delay_fir_91;
component auk_dspip_fastadd_fir_91 is
generic (
INWIDTH_g : natural := 18;
LABWIDTH_g : natural := 16);
-- width of lab in selected device ( 10 or 16 in Cyclone,
-- Cylone II, Stratix and Stratix II. Don't know
-- Stratix III yet.
port (
datain1 : in std_logic_vector(INWIDTH_g-1 downto 0);
datain2 : in std_logic_vector(INWIDTH_g-1 downto 0);
clk : in std_logic;
enable : in std_logic;
reset : in std_logic;
dataout : out std_logic_vector(INWIDTH_g downto 0));
end component auk_dspip_fastadd_fir_91;
component auk_dspip_fastaddsub_fir_91 is
generic (
INWIDTH_g : natural := 18;
LABWIDTH_g : natural := 16);
-- width of lab in selected device ( 10 or 16 in Cyclone,
-- Cylone II, Stratix and Stratix II. Don't know
-- Stratix III yet.
port (
datain1 : in std_logic_vector(INWIDTH_g-1 downto 0);
datain2 : in std_logic_vector(INWIDTH_g-1 downto 0);
add_nsub : in std_logic;
clk : in std_logic;
enable : in std_logic;
reset : in std_logic;
dataout : out std_logic_vector(INWIDTH_g downto 0));
end component auk_dspip_fastaddsub_fir_91;
component auk_dspip_pipelined_adder_fir_91 is
generic (
INWIDTH_g : natural := 42;
-- width of lab in selected device ( 10 or 16 in Cyclone,
-- Cylone II, Stratix and Stratix II.
-- Alex : should I use 19 bits for Stratix III?
-- The rational being 10 ALM (2 bits x ALM + the carry chain inside the same LAB for efficiency.
LABWIDTH_g : natural := 38);
port (
datain1 : in std_logic_vector(INWIDTH_g-1 downto 0);
datain2 : in std_logic_vector(INWIDTH_g-1 downto 0);
clk : in std_logic;
enable : in std_logic;
reset : in std_logic;
dataout : out std_logic_vector(INWIDTH_g downto 0));
end component auk_dspip_pipelined_adder_fir_91;
component auk_dspip_fast_accumulator_fir_91 is
generic (
DATA_WIDTH_g : natural := 42;
-- width of lab in selected device ( 10 or 16 in Cyclone,
-- Cylone II, Stratix and Stratix II.
-- for Stratix III is 20 so labwidth should be set to 18.
-- The rational being 10 ALM (2 bits x ALM + the carry chain inside the same LAB for efficiency.
LABWIDTH_g : natural := 38;
NUM_OF_CHANNELS_g : natural := 1;
ACCUM_OUT_WIDTH_g : natural := 48;
ACCUM_MEM_TYPE_g : string := "auto");
port (
reset : in std_logic;
clk : in std_logic;
enb : in std_logic;
add_to_zero : in std_logic;
datai : in std_logic_vector(DATA_WIDTH_g-1 downto 0);
datao : out std_logic_vector(ACCUM_OUT_WIDTH_g-1 downto 0));
end component auk_dspip_fast_accumulator_fir_91;
component auk_dspip_fifo_pfc_fir_91 is
generic (
NUM_CHANNELS_g : integer := 5;
POLY_FACTOR_g : integer := 3;
DATA_WIDTH_g : integer := 16;
ALMOST_FULL_VALUE_g : integer := 2;
RAM_TYPE_g : string := "AUTO";
CALCULATE_USED_WORDS_ONCE : boolean := true
);
port (
datai : in std_logic_vector(DATA_WIDTH_g-1 downto 0);
datao : out std_logic_vector(DATA_WIDTH_g-1 downto 0);
channel_out : out std_logic_vector(log2_ceil(NUM_CHANNELS_g)-1 downto 0);
used_w : out std_logic_vector(log2_ceil(POLY_FACTOR_g * NUM_CHANNELS_g)+1 downto 0);
wrreq : in std_logic;
rdreq : in std_logic;
almost_full : out std_logic;
empty : out std_logic;
sclr : in std_logic;
clk : in std_logic;
reset : in std_logic;
enable : in std_logic
);
end component auk_dspip_fifo_pfc_fir_91;
component auk_dspip_fpcompiler_alufp is
port (
sysclk : in std_logic;
reset : in std_logic;
enable : in std_logic;
addsub : in std_logic;
aa : in std_logic_vector (42 downto 1);
aasat, aazip : in std_logic;
bb : in std_logic_vector (42 downto 1);
bbsat, bbzip : in std_logic;
cc : out std_logic_vector (42 downto 1);
ccsat, cczip : out std_logic
);
end component auk_dspip_fpcompiler_alufp;
component auk_dspip_fpcompiler_aslf is
port (
inbus : in std_logic_vector (32 downto 1);
shift : in std_logic_vector (5 downto 1);
outbus : out std_logic_vector (32 downto 1)
);
end component auk_dspip_fpcompiler_aslf;
component auk_dspip_fpcompiler_asrf is
port (
inbus : in std_logic_vector (32 downto 1);
shift : in std_logic_vector (5 downto 1);
outbus : out std_logic_vector (32 downto 1)
);
end component auk_dspip_fpcompiler_asrf;
component auk_dspip_fpcompiler_castftox is
port (
aa : in std_logic_vector (32 downto 1);
cc : out std_logic_vector (42 downto 1);
ccsat, cczip : out std_logic
);
end component auk_dspip_fpcompiler_castftox;
component auk_dspip_fpcompiler_castxtof is
port (
sysclk : in std_logic;
reset : in std_logic;
enable : in std_logic;
aa : in std_logic_vector (42 downto 1);
aasat, aazip : in std_logic;
cc : out std_logic_vector (32 downto 1)
);
end component auk_dspip_fpcompiler_castxtof;
component auk_dspip_fpcompiler_clzf is
port (
frac : in std_logic_vector (32 downto 1);
count : out std_logic_vector (5 downto 1)
);
end component auk_dspip_fpcompiler_clzf;
component auk_dspip_fpcompiler_mulfp is
port (
sysclk : in std_logic;
reset : in std_logic;
enable : in std_logic;
aa : in std_logic_vector (42 downto 1);
aasat, aazip : in std_logic;
bb : in std_logic_vector (42 downto 1);
bbsat, bbzip : in std_logic;
cc : out std_logic_vector (42 downto 1);
ccsat, cczip : out std_logic
);
end component auk_dspip_fpcompiler_mulfp;
component auk_dspip_pfc_fir_91 is
generic (
NUM_CHANNELS_g : integer := 5;
POLY_FACTOR_g : integer := 3;
DATA_WIDTH_g : integer := 16;
RAM_TYPE_g : string := "AUTO"
);
port (
datai : in std_logic_vector(DATA_WIDTH_g-1 downto 0);
datao : out std_logic_vector(DATA_WIDTH_g-1 downto 0);
channel_out : out std_logic_vector(log2_ceil(NUM_CHANNELS_g)-1 downto 0);
in_valid : in std_logic;
out_valid : out std_logic;
clk : in std_logic;
reset : in std_logic;
enable : in std_logic
);
end component auk_dspip_pfc_fir_91;
component auk_dspip_roundsat_fir_91 is
generic (
IN_WIDTH_g : natural := 8; -- data width
OUT_WIDTH_g : natural := 8; -- data width
ROUNDING_TYPE_g : string := "TRUNCATE_LOW"
);
port (
clk : in std_logic;
reset : in std_logic;
enable : in std_logic; -- global clock enable
datain : in std_logic_vector(IN_WIDTH_g-1 downto 0);
dataout : out std_logic_vector(OUT_WIDTH_g-1 downto 0));
end component auk_dspip_roundsat_fir_91;
component auk_dspip_avalon_streaming_block_source_fir_91 is
generic (
MAX_BLK_g : natural;
DATAWIDTH_g : natural);
port (
clk : in std_logic;
reset : in std_logic;
in_blk : in std_logic_vector(log2_ceil(MAX_BLK_g) downto 0);
in_valid : in std_logic;
source_stall : out std_logic;
in_data : in std_logic_vector(DATAWIDTH_g - 1 downto 0);
source_valid : out std_logic;
source_ready : in std_logic;
source_sop : out std_logic;
source_eop : out std_logic;
source_data : out std_logic_vector(DATAWIDTH_g - 1 downto 0));
end component auk_dspip_avalon_streaming_block_source_fir_91;
component auk_dspip_avalon_streaming_block_sink_fir_91 is
generic (
MAX_BLK_g : natural;
STALL_g : natural;
DATAWIDTH_g : natural;
-- this generic is specific for the FFT.
NUM_STAGES_g : natural);
port (
clk : in std_logic;
reset : in std_logic;
in_blk : in std_logic_vector(log2_ceil(MAX_BLK_g) downto 0);
in_sop : in std_logic;
in_eop : in std_logic;
in_inverse : in std_logic;
sink_valid : in std_logic;
sink_ready : out std_logic;
source_stall : in std_logic;
in_data : in std_logic_vector(DATAWIDTH_g - 1 downto 0);
processing : in std_logic;
in_error : in std_logic_vector(1 downto 0);
out_error : out std_logic_vector(1 downto 0);
out_valid : out std_logic;
out_sop : out std_logic;
out_eop : out std_logic;
out_data : out std_logic_vector(DATAWIDTH_g - 1 downto 0);
curr_blk : out std_logic_vector(log2_ceil(MAX_BLK_g) downto 0);
-- these are specific to the FFT, no effort has been made to optimize!
curr_pwr_2 : out std_logic;
curr_inverse : out std_logic;
curr_input_sel : out std_logic_vector(NUM_STAGES_g - 1 downto 0));
end component auk_dspip_avalon_streaming_block_sink_fir_91;
end package auk_dspip_lib_pkg_hpfir;
|
-- (C) 2001-2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- Alex, 02-10-07, this package declaration results in error at built time on a new machine
--
use work.auk_dspip_math_pkg_hpfir.all;
package auk_dspip_lib_pkg_hpfir is
--Component names:
--auk_dspip_atlantic_sink
--auk_dspip_atlantic_source
--auk_dspip_interface_controller
--auk_dspip_avalon_streaming_controller_hpfir
--auk_dspip_avalon_streaming_controller_pe_fir_91
--auk_dspip_avalon_streaming_sink_hpfir
--auk_dspip_avalon_streaming_source_hpfir
--auk_dspip_delay_fir_91
--auk_dspip_fastadd_fir_91
--auk_dspip_fastaddsub_fir_91
--auk_dspip_pipelined_adder_fir_91
--auk_dspip_fast_accumulator_fir_91
--auk_dspip_fifo_pfc_fir_91
--auk_dspip_fpcompiler_alufp
--auk_dspip_fpcompiler_aslf
--auk_dspip_fpcompiler_asrf
--auk_dspip_fpcompiler_castftox
--auk_dspip_fpcompiler_castxtof
--auk_dspip_fpcompiler_clzf
--auk_dspip_fpcompiler_mulfp
--auk_dspip_pfc_fir_91
--auk_dspip_roundsat_fir_91
component auk_dspip_atlantic_sink is
generic(
WIDTH : integer := 16;
PACKET_SIZE : natural := 4;
log2packet_size : integer := 2
);
port(
clk : in std_logic;
reset_n : in std_logic;
----------------- DESIGN SIDE SIGNALS
data_available : out std_logic; --goes high when new data is available
data : out std_logic_vector(WIDTH-1 downto 0);
sink_ready_ctrl : in std_logic; --the controller will tell
--the interface whether
--new input can be accepted.
sink_stall : out std_logic; --needs to stall the design
--if no new data is coming
packet_error : out std_logic_vector (1 downto 0); --this is for SOP and EOP check only.
--when any of these doesn't behave as
--expected, the error is flagged.
send_sop : out std_logic; -- transmit SOP signal to the design.
-- It only transmits the legal SOP.
send_eop : out std_logic; -- transmit EOP signal to the design.
-- It only transmits the legal EOP.
----------------- ATLANTIC SIDE SIGNALS
at_sink_ready : out std_logic; --it will be '1' whenever the
--sink_ready_ctrl signal is high.
at_sink_valid : in std_logic;
at_sink_data : in std_logic_vector(WIDTH-1 downto 0);
at_sink_sop : in std_logic := '0';
at_sink_eop : in std_logic := '0';
at_sink_error : in std_logic_vector(1 downto 0) --it indicates to the data source
--that the SOP and EOP signals
--are not received as expected.
);
end component auk_dspip_atlantic_sink;
component auk_dspip_atlantic_source is
generic(
WIDTH : integer := 16;
packet_size : natural := 4;
LOG2packet_size : integer := 2;
multi_channel : BOOLEAN := TRUE
);
port(
clk : in std_logic;
reset_n : in std_logic;
----------------- DESIGN SIDE SIGNALS
data : in std_logic_vector (WIDTH-1 downto 0);
data_count : in std_logic_vector (LOG2packet_size-1 downto 0) := (others => '0');
source_valid_ctrl : in std_logic; --the controller will tell
--the interface whether
--new input can be accepted.
source_stall : out std_logic; --needs to stall the design
--if no new data is coming
packet_error : in std_logic_vector (1 downto 0);
----------------- ATLANTIC SIDE SIGNALS
at_source_ready : in std_logic;
at_source_valid : out std_logic;
at_source_data : out std_logic_vector (WIDTH-1 downto 0);
at_source_channel : out std_logic_vector (log2packet_size-1 downto 0);
at_source_error : out std_logic_vector (1 downto 0);
at_source_sop : out std_logic;
at_source_eop : out std_logic
);
-- Declarations
end component auk_dspip_atlantic_source;
component auk_dspip_interface_controller IS
PORT(
clk : in std_logic;
reset : IN std_logic;
ready : in std_logic;
sink_packet_error : IN std_logic_vector (1 DOWNTO 0);
sink_stall : IN std_logic;
source_stall : IN std_logic;
valid : IN std_logic;
reset_design : OUT std_logic;
reset_n : OUT std_logic;
sink_ready_ctrl : OUT std_logic;
source_packet_error : OUT std_logic_vector (1 DOWNTO 0);
source_valid_ctrl : OUT std_logic;
stall : OUT std_logic
);
-- Declarations
end component auk_dspip_interface_controller ;
component auk_dspip_avalon_streaming_controller_hpfir is
port(
clk : in std_logic;
--clk_en : in std_logic := '1';
reset_n : in std_logic;
--ready : in std_logic;
sink_packet_error : in std_logic_vector (1 downto 0);
--sink_stall : in std_logic;
source_stall : in std_logic;
valid : in std_logic;
reset_design : out std_logic;
sink_ready_ctrl : out std_logic;
source_packet_error : out std_logic_vector (1 downto 0);
source_valid_ctrl : out std_logic;
stall : out std_logic
);
-- Declarations
end component auk_dspip_avalon_streaming_controller_hpfir;
component auk_dspip_avalon_streaming_controller_pe_fir_91 is
generic (
FIFO_WIDTH_g : natural := 8;
ENABLE_PIPELINE_DEPTH_g : natural := 0; -- this value should match the depth of the enable pipeline in the core
FAMILY_g : string := "Stratix II";
MEM_TYPE_g : string := "Auto"
);
port(
clk : in std_logic;
clk_en : in std_logic := '1';
reset_n : in std_logic;
ready : in std_logic;
sink_packet_error : in std_logic_vector (1 downto 0);
sink_stall : in std_logic;
source_stall : in std_logic;
valid : in std_logic;
reset_design : out std_logic;
sink_ready_ctrl : out std_logic;
source_packet_error : out std_logic_vector (1 downto 0);
source_valid_ctrl : out std_logic;
stall : out std_logic;
data_in : in std_logic_vector(FIFO_WIDTH_g-1 downto 0);
data_out : out std_logic_vector(FIFO_WIDTH_g-1 downto 0);
design_stall : out std_logic
);
-- Declarations
end component auk_dspip_avalon_streaming_controller_pe_fir_91;
component auk_dspip_avalon_streaming_sink_hpfir is
generic(
WIDTH_g : integer := 16;
DATA_WIDTH : integer := 8;
DATA_PORT_COUNT : integer := 3;
PACKET_SIZE_g : natural := 4
--FIFO_DEPTH_g : natural := 5 --if PFC mode is selected, this generic
--is used for passing the poly_factor.
--MIN_DATA_COUNT_g : natural := 2;
--PFC_MODE_g : boolean := false;
--SOP_EOP_CALC_g : boolean := false; -- calculate sop and eop rather than
-- reading value from fifo
--FAMILY_g : string := "Stratix II";
--MEM_TYPE_g : string := "Auto"
);
port(
clk : in std_logic;
reset_n : in std_logic;
----------------- DESIGN SIDE SIGNALS
data : out std_logic_vector(WIDTH_g-1 downto 0);
data_valid : out std_logic_vector(0 downto 0);
sink_ready_ctrl : in std_logic; --the controller will tell
--the interface whether
--new input can be accepted.
--sink_stall : out std_logic; --needs to stall the design
--if no new data is coming
packet_error : out std_logic_vector (1 downto 0); --this is for SOP and EOP check only.
--when any of these doesn't behave as
--expected, the error is flagged.
--send_sop : out std_logic; -- transmit SOP signal to the design.
-- It only transmits the legal SOP.
--send_eop : out std_logic; -- transmit EOP signal to the design.
-- It only transmits the legal EOP.
----------------- ATLANTIC SIDE SIGNALS
at_sink_ready : out std_logic; --it will be '1' whenever the
--sink_ready_ctrl signal is high.
at_sink_valid : in std_logic;
at_sink_data : in std_logic_vector(WIDTH_g-1 downto 0);
at_sink_sop : in std_logic := '0';
at_sink_eop : in std_logic := '0';
at_sink_error : in std_logic_vector(1 downto 0) := "00" --it indicates
--that there is an error in the packet.
);
end component auk_dspip_avalon_streaming_sink_hpfir;
component auk_dspip_avalon_streaming_source_hpfir is
generic(
WIDTH_g : integer := 8;
DATA_WIDTH : integer := 8;
DATA_PORT_COUNT : integer := 1;
PACKET_SIZE_g : natural := 2;
FIFO_DEPTH_g : natural := 0;
HAVE_COUNTER_g : boolean := false;
COUNTER_LIMIT_g : natural := 4;
--MULTI_CHANNEL_g : boolean := true;
USE_PACKETS : integer := 1;
--FAMILY_g : string := "Stratix II";
--MEM_TYPE_g : string := "Auto";
ENABLE_BACKPRESSURE_g : boolean := true
);
port(
clk : in std_logic;
reset_n : in std_logic;
----------------- DESIGN SIDE SIGNALS
data_in : in std_logic_vector (WIDTH_g-1 downto 0);
data_count : in std_logic_vector (log2_ceil_one(PACKET_SIZE_g)-1 downto 0) := (others => '0');
source_valid_ctrl : in std_logic;
source_stall : out std_logic;
packet_error : in std_logic_vector (1 downto 0);
----------------- AVALON_STREAMING SIDE SIGNALS
at_source_ready : in std_logic;
at_source_valid : out std_logic;
at_source_data : out std_logic_vector (WIDTH_g-1 downto 0);
at_source_channel : out std_logic_vector (log2_ceil_one(PACKET_SIZE_g)-1 downto 0);
at_source_error : out std_logic_vector (1 downto 0);
at_source_sop : out std_logic;
at_source_eop : out std_logic
);
-- Declarations
end component auk_dspip_avalon_streaming_source_hpfir;
component auk_dspip_roundsat_hpfir is
generic (
IN_WIDTH_g : natural := 8; -- i/p data width
REM_LSB_BIT_g : natural := 2; -- no. of lsb to be removed
REM_LSB_TYPE_g : string := "Truncation"; -- TRUNCATE/ROUND_UP
REM_MSB_BIT_g : natural := 2; -- no. of msb to be removed
REM_MSB_TYPE_g : string := "Truncation" -- TRUNCATE/SATURATE
);
port (
clk : in std_logic;
reset_n : in std_logic;
enable : in std_logic;
datain : in std_logic_vector(IN_WIDTH_g-1 downto 0);
valid : out std_logic;
dataout : out std_logic_vector(IN_WIDTH_g-REM_LSB_BIT_g-REM_MSB_BIT_g-1 downto 0)
);
end component auk_dspip_roundsat_hpfir;
component auk_dspip_delay_fir_91 is
generic (
WIDTH_g : natural := 8; -- data width
DELAY_g : natural := 8;
-- number of clock cycles the input
-- will be delayed by
MEMORY_TYPE_g : string := "AUTO";
-- possible values are "m4k", "m512",
-- "register", "mram", "auto",
-- "lutram", "M9K", "M144K".
-- Any other string will be interpreted
-- as "auto"
REGISTER_FIRST_g : natural := 1;
-- if "1", the first delay is guaranteed
-- to be in registers
REGISTER_LAST_g : natural := 1); -- if "1", the last delay is guaranteed
-- to be in registers
port (
clk : in std_logic;
reset : in std_logic;
enable : in std_logic; -- global clock enable
datain : in std_logic_vector(WIDTH_g-1 downto 0);
dataout : out std_logic_vector(WIDTH_g-1 downto 0)
);
end component auk_dspip_delay_fir_91;
component auk_dspip_fastadd_fir_91 is
generic (
INWIDTH_g : natural := 18;
LABWIDTH_g : natural := 16);
-- width of lab in selected device ( 10 or 16 in Cyclone,
-- Cylone II, Stratix and Stratix II. Don't know
-- Stratix III yet.
port (
datain1 : in std_logic_vector(INWIDTH_g-1 downto 0);
datain2 : in std_logic_vector(INWIDTH_g-1 downto 0);
clk : in std_logic;
enable : in std_logic;
reset : in std_logic;
dataout : out std_logic_vector(INWIDTH_g downto 0));
end component auk_dspip_fastadd_fir_91;
component auk_dspip_fastaddsub_fir_91 is
generic (
INWIDTH_g : natural := 18;
LABWIDTH_g : natural := 16);
-- width of lab in selected device ( 10 or 16 in Cyclone,
-- Cylone II, Stratix and Stratix II. Don't know
-- Stratix III yet.
port (
datain1 : in std_logic_vector(INWIDTH_g-1 downto 0);
datain2 : in std_logic_vector(INWIDTH_g-1 downto 0);
add_nsub : in std_logic;
clk : in std_logic;
enable : in std_logic;
reset : in std_logic;
dataout : out std_logic_vector(INWIDTH_g downto 0));
end component auk_dspip_fastaddsub_fir_91;
component auk_dspip_pipelined_adder_fir_91 is
generic (
INWIDTH_g : natural := 42;
-- width of lab in selected device ( 10 or 16 in Cyclone,
-- Cylone II, Stratix and Stratix II.
-- Alex : should I use 19 bits for Stratix III?
-- The rational being 10 ALM (2 bits x ALM + the carry chain inside the same LAB for efficiency.
LABWIDTH_g : natural := 38);
port (
datain1 : in std_logic_vector(INWIDTH_g-1 downto 0);
datain2 : in std_logic_vector(INWIDTH_g-1 downto 0);
clk : in std_logic;
enable : in std_logic;
reset : in std_logic;
dataout : out std_logic_vector(INWIDTH_g downto 0));
end component auk_dspip_pipelined_adder_fir_91;
component auk_dspip_fast_accumulator_fir_91 is
generic (
DATA_WIDTH_g : natural := 42;
-- width of lab in selected device ( 10 or 16 in Cyclone,
-- Cylone II, Stratix and Stratix II.
-- for Stratix III is 20 so labwidth should be set to 18.
-- The rational being 10 ALM (2 bits x ALM + the carry chain inside the same LAB for efficiency.
LABWIDTH_g : natural := 38;
NUM_OF_CHANNELS_g : natural := 1;
ACCUM_OUT_WIDTH_g : natural := 48;
ACCUM_MEM_TYPE_g : string := "auto");
port (
reset : in std_logic;
clk : in std_logic;
enb : in std_logic;
add_to_zero : in std_logic;
datai : in std_logic_vector(DATA_WIDTH_g-1 downto 0);
datao : out std_logic_vector(ACCUM_OUT_WIDTH_g-1 downto 0));
end component auk_dspip_fast_accumulator_fir_91;
component auk_dspip_fifo_pfc_fir_91 is
generic (
NUM_CHANNELS_g : integer := 5;
POLY_FACTOR_g : integer := 3;
DATA_WIDTH_g : integer := 16;
ALMOST_FULL_VALUE_g : integer := 2;
RAM_TYPE_g : string := "AUTO";
CALCULATE_USED_WORDS_ONCE : boolean := true
);
port (
datai : in std_logic_vector(DATA_WIDTH_g-1 downto 0);
datao : out std_logic_vector(DATA_WIDTH_g-1 downto 0);
channel_out : out std_logic_vector(log2_ceil(NUM_CHANNELS_g)-1 downto 0);
used_w : out std_logic_vector(log2_ceil(POLY_FACTOR_g * NUM_CHANNELS_g)+1 downto 0);
wrreq : in std_logic;
rdreq : in std_logic;
almost_full : out std_logic;
empty : out std_logic;
sclr : in std_logic;
clk : in std_logic;
reset : in std_logic;
enable : in std_logic
);
end component auk_dspip_fifo_pfc_fir_91;
component auk_dspip_fpcompiler_alufp is
port (
sysclk : in std_logic;
reset : in std_logic;
enable : in std_logic;
addsub : in std_logic;
aa : in std_logic_vector (42 downto 1);
aasat, aazip : in std_logic;
bb : in std_logic_vector (42 downto 1);
bbsat, bbzip : in std_logic;
cc : out std_logic_vector (42 downto 1);
ccsat, cczip : out std_logic
);
end component auk_dspip_fpcompiler_alufp;
component auk_dspip_fpcompiler_aslf is
port (
inbus : in std_logic_vector (32 downto 1);
shift : in std_logic_vector (5 downto 1);
outbus : out std_logic_vector (32 downto 1)
);
end component auk_dspip_fpcompiler_aslf;
component auk_dspip_fpcompiler_asrf is
port (
inbus : in std_logic_vector (32 downto 1);
shift : in std_logic_vector (5 downto 1);
outbus : out std_logic_vector (32 downto 1)
);
end component auk_dspip_fpcompiler_asrf;
component auk_dspip_fpcompiler_castftox is
port (
aa : in std_logic_vector (32 downto 1);
cc : out std_logic_vector (42 downto 1);
ccsat, cczip : out std_logic
);
end component auk_dspip_fpcompiler_castftox;
component auk_dspip_fpcompiler_castxtof is
port (
sysclk : in std_logic;
reset : in std_logic;
enable : in std_logic;
aa : in std_logic_vector (42 downto 1);
aasat, aazip : in std_logic;
cc : out std_logic_vector (32 downto 1)
);
end component auk_dspip_fpcompiler_castxtof;
component auk_dspip_fpcompiler_clzf is
port (
frac : in std_logic_vector (32 downto 1);
count : out std_logic_vector (5 downto 1)
);
end component auk_dspip_fpcompiler_clzf;
component auk_dspip_fpcompiler_mulfp is
port (
sysclk : in std_logic;
reset : in std_logic;
enable : in std_logic;
aa : in std_logic_vector (42 downto 1);
aasat, aazip : in std_logic;
bb : in std_logic_vector (42 downto 1);
bbsat, bbzip : in std_logic;
cc : out std_logic_vector (42 downto 1);
ccsat, cczip : out std_logic
);
end component auk_dspip_fpcompiler_mulfp;
component auk_dspip_pfc_fir_91 is
generic (
NUM_CHANNELS_g : integer := 5;
POLY_FACTOR_g : integer := 3;
DATA_WIDTH_g : integer := 16;
RAM_TYPE_g : string := "AUTO"
);
port (
datai : in std_logic_vector(DATA_WIDTH_g-1 downto 0);
datao : out std_logic_vector(DATA_WIDTH_g-1 downto 0);
channel_out : out std_logic_vector(log2_ceil(NUM_CHANNELS_g)-1 downto 0);
in_valid : in std_logic;
out_valid : out std_logic;
clk : in std_logic;
reset : in std_logic;
enable : in std_logic
);
end component auk_dspip_pfc_fir_91;
component auk_dspip_roundsat_fir_91 is
generic (
IN_WIDTH_g : natural := 8; -- data width
OUT_WIDTH_g : natural := 8; -- data width
ROUNDING_TYPE_g : string := "TRUNCATE_LOW"
);
port (
clk : in std_logic;
reset : in std_logic;
enable : in std_logic; -- global clock enable
datain : in std_logic_vector(IN_WIDTH_g-1 downto 0);
dataout : out std_logic_vector(OUT_WIDTH_g-1 downto 0));
end component auk_dspip_roundsat_fir_91;
component auk_dspip_avalon_streaming_block_source_fir_91 is
generic (
MAX_BLK_g : natural;
DATAWIDTH_g : natural);
port (
clk : in std_logic;
reset : in std_logic;
in_blk : in std_logic_vector(log2_ceil(MAX_BLK_g) downto 0);
in_valid : in std_logic;
source_stall : out std_logic;
in_data : in std_logic_vector(DATAWIDTH_g - 1 downto 0);
source_valid : out std_logic;
source_ready : in std_logic;
source_sop : out std_logic;
source_eop : out std_logic;
source_data : out std_logic_vector(DATAWIDTH_g - 1 downto 0));
end component auk_dspip_avalon_streaming_block_source_fir_91;
component auk_dspip_avalon_streaming_block_sink_fir_91 is
generic (
MAX_BLK_g : natural;
STALL_g : natural;
DATAWIDTH_g : natural;
-- this generic is specific for the FFT.
NUM_STAGES_g : natural);
port (
clk : in std_logic;
reset : in std_logic;
in_blk : in std_logic_vector(log2_ceil(MAX_BLK_g) downto 0);
in_sop : in std_logic;
in_eop : in std_logic;
in_inverse : in std_logic;
sink_valid : in std_logic;
sink_ready : out std_logic;
source_stall : in std_logic;
in_data : in std_logic_vector(DATAWIDTH_g - 1 downto 0);
processing : in std_logic;
in_error : in std_logic_vector(1 downto 0);
out_error : out std_logic_vector(1 downto 0);
out_valid : out std_logic;
out_sop : out std_logic;
out_eop : out std_logic;
out_data : out std_logic_vector(DATAWIDTH_g - 1 downto 0);
curr_blk : out std_logic_vector(log2_ceil(MAX_BLK_g) downto 0);
-- these are specific to the FFT, no effort has been made to optimize!
curr_pwr_2 : out std_logic;
curr_inverse : out std_logic;
curr_input_sel : out std_logic_vector(NUM_STAGES_g - 1 downto 0));
end component auk_dspip_avalon_streaming_block_sink_fir_91;
end package auk_dspip_lib_pkg_hpfir;
|
--!
--! Copyright 2018 Sergey Khabarov, [email protected]
--!
--! Licensed under the Apache License, Version 2.0 (the "License");
--! you may not use this file except in compliance with the License.
--! You may obtain a copy of the License at
--!
--! http://www.apache.org/licenses/LICENSE-2.0
--! Unless required by applicable law or agreed to in writing, software
--! distributed under the License is distributed on an "AS IS" BASIS,
--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
--! See the License for the specific language governing permissions and
--! limitations under the License.
--!
--! Standard library.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library commonlib;
use commonlib.types_common.all;
--! Technology definition library.
library techmap;
use techmap.gencomp.all;
--! CPU, System Bus and common peripheries library.
library ambalib;
use ambalib.types_amba4.all;
use ambalib.types_bus0.all;
--! @brief Declaration of components visible on SoC top level.
package types_misc is
--! @defgroup irq_id_group AXI4 interrupt generic IDs.
--! @ingroup axi4_config_generic_group
--! @details Unique indentificator of the interrupt pin also used
--! as an index in the interrupts bus.
--! @{
--! Zero interrupt index must be unused.
constant CFG_IRQ_UNUSED : integer := 0;
--! UART_A interrupt pin.
constant CFG_IRQ_UART1 : integer := 1;
--! Ethernet MAC interrupt pin.
constant CFG_IRQ_ETHMAC : integer := 2;
--! GP Timers interrupt pin
constant CFG_IRQ_GPTIMERS : integer := 3;
--! GNSS Engine IRQ pin that generates 1 msec pulses.
constant CFG_IRQ_GNSSENGINE : integer := 4;
--! Total number of used interrupts in a system
constant CFG_IRQ_TOTAL : integer := 5;
--! @}
--! @brief SOC global reset former.
--! @details This module produces output reset signal in a case if
--! button 'Reset' was pushed or PLL isn't a 'lock' state.
--! param[in] inSysReset Button generated signal
--! param[in] inSysClk Clock from the PLL. Bus clock.
--! param[out] outReset Output reset signal with active 'High' (1 = reset).
component reset_global
port (
inSysReset : in std_ulogic;
inSysClk : in std_ulogic;
outReset : out std_ulogic );
end component;
--! Boot ROM with AXI4 interface declaration.
component axi4_rom is
generic (
memtech : integer := inferred;
async_reset : boolean := false;
xaddr : integer := 0;
xmask : integer := 16#fffff#;
sim_hexfile : string
);
port (
clk : in std_logic;
nrst : in std_logic;
cfg : out axi4_slave_config_type;
i : in axi4_slave_in_type;
o : out axi4_slave_out_type
);
end component;
--! Internal RAM with AXI4 interface declaration.
component axi4_sram is
generic (
memtech : integer := inferred;
async_reset : boolean := false;
xaddr : integer := 0;
xmask : integer := 16#fffff#;
abits : integer := 17;
init_file : string := "" -- only for 'inferred'
);
port (
clk : in std_logic;
nrst : in std_logic;
cfg : out axi4_slave_config_type;
i : in axi4_slave_in_type;
o : out axi4_slave_out_type
);
end component;
--! AXI4 to SPI brdige for external Flash IC Micron M25AA1024
type spi_in_type is record
SDI : std_logic;
end record;
type spi_out_type is record
SDO : std_logic;
SCK : std_logic;
nCS : std_logic;
nWP : std_logic;
nHOLD : std_logic;
RESET : std_logic;
end record;
constant spi_out_none : spi_out_type := (
'0', '0', '1', '1', '1', '0'
);
component axi4_flashspi is
generic (
async_reset : boolean := false;
xaddr : integer := 0;
xmask : integer := 16#fffff#;
wait_while_write : boolean := true -- hold AXI bus response until end of write cycle
);
port (
clk : in std_logic;
nrst : in std_logic;
cfg : out axi4_slave_config_type;
i_spi : in spi_in_type;
o_spi : out spi_out_type;
i_axi : in axi4_slave_in_type;
o_axi : out axi4_slave_out_type );
end component;
--! @brief AXI4 GPIO controller
component axi4_gpio is
generic (
async_reset : boolean := false;
xaddr : integer := 0;
xmask : integer := 16#fffff#;
xirq : integer := 0;
width : integer := 12
);
port (
clk : in std_logic;
nrst : in std_logic;
cfg : out axi4_slave_config_type;
i : in axi4_slave_in_type;
o : out axi4_slave_out_type;
i_gpio : in std_logic_vector(width-1 downto 0);
o_gpio : out std_logic_vector(width-1 downto 0);
o_gpio_dir : out std_logic_vector(width-1 downto 0)
);
end component;
type uart_in_type is record
rd : std_ulogic;
cts : std_ulogic;
end record;
type uart_out_type is record
td : std_ulogic;
rts : std_ulogic;
end record;
--! UART with the AXI4 interface declaration.
component axi4_uart is
generic (
async_reset : boolean := false;
xaddr : integer := 0;
xmask : integer := 16#fffff#;
xirq : integer := 0;
fifosz : integer := 16
);
port (
clk : in std_logic;
nrst : in std_logic;
cfg : out axi4_slave_config_type;
i_uart : in uart_in_type;
o_uart : out uart_out_type;
i_axi : in axi4_slave_in_type;
o_axi : out axi4_slave_out_type;
o_irq : out std_logic);
end component;
--! Test Access Point via UART (debug access)
component uart_tap is
port (
nrst : in std_logic;
clk : in std_logic;
i_uart : in uart_in_type;
o_uart : out uart_out_type;
i_msti : in axi4_master_in_type;
o_msto : out axi4_master_out_type;
o_mstcfg : out axi4_master_config_type
);
end component;
-- JTAG TAP
component tap_jtag is
port (
nrst : in std_logic;
clk : in std_logic;
i_tck : in std_logic; -- in: Test Clock
i_ntrst : in std_logic; -- in:
i_tms : in std_logic; -- in: Test Mode State
i_tdi : in std_logic; -- in: Test Data Input
o_tdo : out std_logic; -- out: Test Data Output
o_jtag_vref : out std_logic;
-- DMI interface
o_dmi_req_valid : out std_logic;
i_dmi_req_ready : in std_logic;
o_dmi_write : out std_logic;
o_dmi_addr : out std_logic_vector(6 downto 0);
o_dmi_wdata : out std_logic_vector(31 downto 0);
i_dmi_resp_valid : in std_logic;
o_dmi_resp_ready : out std_logic;
i_dmi_rdata : in std_logic_vector(31 downto 0)
);
end component;
--! @brief Interrupt controller with the AXI4 interface declaration.
--! @details To rise interrupt on certain CPU HostIO interface is used.
component axi4_irqctrl is
generic (
async_reset : boolean := false;
xaddr : integer := 0;
xmask : integer := 16#fffff#
);
port
(
clk : in std_logic;
nrst : in std_logic;
i_irqs : in std_logic_vector(CFG_IRQ_TOTAL-1 downto 1);
o_cfg : out axi4_slave_config_type;
i_axi : in axi4_slave_in_type;
o_axi : out axi4_slave_out_type;
o_irq_meip : out std_logic
);
end component;
--! @brief General Purpose Timers with the AXI interface.
--! @details This module provides high precision counter and
--! generic number of GP timers.
component axi4_gptimers is
generic (
async_reset : boolean := false;
xaddr : integer := 0;
xmask : integer := 16#fffff#;
xirq : integer := 0;
tmr_total : integer := 2
);
port (
clk : in std_logic;
nrst : in std_logic;
cfg : out axi4_slave_config_type;
i_axi : in axi4_slave_in_type;
o_axi : out axi4_slave_out_type;
o_pwm : out std_logic_vector(tmr_total-1 downto 0);
o_irq : out std_logic
);
end component;
--! @brief Plug-n-Play support module with AXI4 interface declaration.
--! @details Each device in a system hase to implements sideband signal
--! structure 'nasti_slave_config_type' that allows FW to
--! detect Hardware configuration in a run-time.
--! @todo Implements PnP signals for all Masters devices.
component axi4_pnp is
generic (
async_reset : boolean := false;
xaddr : integer := 0;
xmask : integer := 16#fffff#;
tech : integer := 0;
hw_id : std_logic_vector(31 downto 0) := X"20170101"
);
port (
sys_clk : in std_logic;
adc_clk : in std_logic;
nrst : in std_logic;
mstcfg : in bus0_xmst_cfg_vector;
slvcfg : in bus0_xslv_cfg_vector;
cfg : out axi4_slave_config_type;
i : in axi4_slave_in_type;
o : out axi4_slave_out_type;
-- OTP Timing control
i_otp_busy : in std_logic;
o_otp_cfg_rsetup : out std_logic_vector(3 downto 0);
o_otp_cfg_wadrsetup : out std_logic_vector(3 downto 0);
o_otp_cfg_wactive : out std_logic_vector(31 downto 0);
o_otp_cfg_whold : out std_logic_vector(3 downto 0)
);
end component;
component axi4_otp is
generic (
async_reset : boolean := false;
xaddr : integer := 0;
xmask : integer := 16#ffffe#
);
port (
clk : in std_logic;
nrst : in std_logic;
cfg : out axi4_slave_config_type;
i_axi : in axi4_slave_in_type;
o_axi : out axi4_slave_out_type;
o_otp_we : out std_ulogic;
o_otp_re : out std_ulogic;
o_otp_addr : out std_logic_vector(11 downto 0);
o_otp_wdata : out std_logic_vector(15 downto 0);
i_otp_rdata : in std_logic_vector(15 downto 0);
i_cfg_rsetup : in std_logic_vector(3 downto 0);
i_cfg_wadrsetup : in std_logic_vector(3 downto 0);
i_cfg_wactive : in std_logic_vector(31 downto 0);
i_cfg_whold : in std_logic_vector(3 downto 0);
o_busy : out std_logic
);
end component;
end; -- package declaration
|
---------------------------------------------------------------------
-- TITLE: Ethernet DMA
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 12/27/07
-- FILENAME: eth_dma.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Ethernet DMA (Direct Memory Access) controller.
-- Reads four bits and writes four bits from/to the Ethernet PHY each
-- 2.5 MHz clock cycle. Received data is DMAed starting at 0x13ff0000
-- transmit data is read from 0x13fd0000.
-- To send a packet write bytes/4 to Ethernet send register.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use work.mlite_pack.all;
entity eth_dma is port(
clk : in std_logic; --25 MHz
reset : in std_logic;
enable_eth : in std_logic; --enable receive DMA
select_eth : in std_logic;
rec_isr : out std_logic; --data received
send_isr : out std_logic; --transmit done
address : out std_logic_vector(31 downto 2); --to DDR
byte_we : out std_logic_vector(3 downto 0);
data_write : out std_logic_vector(31 downto 0);
data_read : in std_logic_vector(31 downto 0);
pause_in : in std_logic;
mem_address : in std_logic_vector(31 downto 2); --from CPU
mem_byte_we : in std_logic_vector(3 downto 0);
data_w : in std_logic_vector(31 downto 0);
pause_out : out std_logic;
E_RX_CLK : in std_logic; --2.5 MHz receive
E_RX_DV : in std_logic; --data valid
E_RXD : in std_logic_vector(3 downto 0); --receive nibble
E_TX_CLK : in std_logic; --2.5 MHz transmit
E_TX_EN : out std_logic; --transmit enable
E_TXD : out std_logic_vector(3 downto 0)); --transmit nibble
end; --entity eth_dma
architecture logic of eth_dma is
signal rec_clk : std_logic_vector(1 downto 0); --receive
signal rec_store : std_logic_vector(31 downto 0); --to DDR
signal rec_data : std_logic_vector(27 downto 0);
signal rec_cnt : std_logic_vector(2 downto 0); --nibbles
signal rec_words : std_logic_vector(13 downto 0);
signal rec_dma : std_logic_vector(1 downto 0); --active & request
signal rec_done : std_logic;
signal send_clk : std_logic_vector(1 downto 0); --transmit
signal send_read : std_logic_vector(31 downto 0); --from DDR
signal send_data : std_logic_vector(31 downto 0);
signal send_cnt : std_logic_vector(2 downto 0); --nibbles
signal send_words : std_logic_vector(8 downto 0);
signal send_level : std_logic_vector(8 downto 0);
signal send_dma : std_logic_vector(1 downto 0); --active & request
signal send_enable: std_logic;
begin --architecture
dma_proc: process(clk, reset, enable_eth, select_eth,
data_read, pause_in, mem_address, mem_byte_we, data_w,
E_RX_CLK, E_RX_DV, E_RXD, E_TX_CLK,
rec_clk, rec_store, rec_data,
rec_cnt, rec_words, rec_dma, rec_done,
send_clk, send_read, send_data, send_cnt, send_words,
send_level, send_dma, send_enable)
begin
if reset = '1' then
rec_clk <= "00";
rec_cnt <= "000";
rec_words <= ZERO(13 downto 0);
rec_dma <= "00";
rec_done <= '0';
send_clk <= "00";
send_cnt <= "000";
send_words <= ZERO(8 downto 0);
send_level <= ZERO(8 downto 0);
send_dma <= "00";
send_enable <= '0';
elsif rising_edge(clk) then
--Receive nibble on low->high E_RX_CLK. Send to DDR every 32 bits.
rec_clk <= rec_clk(0) & E_RX_CLK;
if rec_clk = "01" and enable_eth = '1' then
if E_RX_DV = '1' or rec_cnt /= "000" then
if rec_cnt = "111" then
rec_store <= rec_data & E_RXD;
rec_dma(0) <= '1'; --request DMA
end if;
rec_data <= rec_data(23 downto 0) & E_RXD;
rec_cnt <= rec_cnt + 1;
end if;
end if;
--Set transmit count or clear receive interrupt
if select_eth = '1' then
if mem_byte_we /= "0000" then
send_cnt <= "000";
send_words <= ZERO(8 downto 0);
send_level <= data_w(8 downto 0);
send_dma(0) <= '1';
else
rec_done <= '0';
end if;
end if;
--Transmit nibble on low->high E_TX_CLK. Get 32 bits from DDR.
send_clk <= send_clk(0) & E_TX_CLK;
if send_clk = "01" then
if send_cnt = "111" then
if send_words /= send_level then
send_data <= send_read;
send_dma(0) <= '1';
send_enable <= '1';
else
send_enable <= '0';
end if;
else
send_data(31 downto 4) <= send_data(27 downto 0);
end if;
send_cnt <= send_cnt + 1;
end if;
--Pick which type of DMA operation: bit0 = request; bit1 = active
if pause_in = '0' then
if rec_dma(1) = '1' then
rec_dma <= "00"; --DMA done
rec_words <= rec_words + 1;
if E_RX_DV = '0' then
rec_done <= '1';
end if;
elsif send_dma(1) = '1' then
send_dma <= "00";
send_words <= send_words + 1;
send_read <= data_read;
elsif rec_dma(0) = '1' then
rec_dma(1) <= '1'; --start DMA
elsif send_dma(0) = '1' then
send_dma(1) <= '1'; --start DMA
end if;
end if;
end if; --rising_edge(clk)
E_TXD <= send_data(31 downto 28);
E_TX_EN <= send_enable;
rec_isr <= rec_done;
if send_words = send_level then
send_isr <= '1';
else
send_isr <= '0';
end if;
if rec_dma(1) = '1' then
address <= "0001001111111111" & rec_words; --0x13ff0000
byte_we <= "1111";
data_write <= rec_store;
pause_out <= '1'; --to CPU
elsif send_dma(1) = '1' then
address <= "000100111111111000000" & send_words; --0x13fe0000
byte_we <= "0000";
data_write <= data_w;
pause_out <= '1';
else
address <= mem_address; --Send request from CPU to DDR
byte_we <= mem_byte_we;
data_write <= data_w;
pause_out <= '0';
end if;
end process;
end; --architecture logic
|
---------------------------------------------------------------------
-- TITLE: Ethernet DMA
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 12/27/07
-- FILENAME: eth_dma.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Ethernet DMA (Direct Memory Access) controller.
-- Reads four bits and writes four bits from/to the Ethernet PHY each
-- 2.5 MHz clock cycle. Received data is DMAed starting at 0x13ff0000
-- transmit data is read from 0x13fd0000.
-- To send a packet write bytes/4 to Ethernet send register.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use work.mlite_pack.all;
entity eth_dma is port(
clk : in std_logic; --25 MHz
reset : in std_logic;
enable_eth : in std_logic; --enable receive DMA
select_eth : in std_logic;
rec_isr : out std_logic; --data received
send_isr : out std_logic; --transmit done
address : out std_logic_vector(31 downto 2); --to DDR
byte_we : out std_logic_vector(3 downto 0);
data_write : out std_logic_vector(31 downto 0);
data_read : in std_logic_vector(31 downto 0);
pause_in : in std_logic;
mem_address : in std_logic_vector(31 downto 2); --from CPU
mem_byte_we : in std_logic_vector(3 downto 0);
data_w : in std_logic_vector(31 downto 0);
pause_out : out std_logic;
E_RX_CLK : in std_logic; --2.5 MHz receive
E_RX_DV : in std_logic; --data valid
E_RXD : in std_logic_vector(3 downto 0); --receive nibble
E_TX_CLK : in std_logic; --2.5 MHz transmit
E_TX_EN : out std_logic; --transmit enable
E_TXD : out std_logic_vector(3 downto 0)); --transmit nibble
end; --entity eth_dma
architecture logic of eth_dma is
signal rec_clk : std_logic_vector(1 downto 0); --receive
signal rec_store : std_logic_vector(31 downto 0); --to DDR
signal rec_data : std_logic_vector(27 downto 0);
signal rec_cnt : std_logic_vector(2 downto 0); --nibbles
signal rec_words : std_logic_vector(13 downto 0);
signal rec_dma : std_logic_vector(1 downto 0); --active & request
signal rec_done : std_logic;
signal send_clk : std_logic_vector(1 downto 0); --transmit
signal send_read : std_logic_vector(31 downto 0); --from DDR
signal send_data : std_logic_vector(31 downto 0);
signal send_cnt : std_logic_vector(2 downto 0); --nibbles
signal send_words : std_logic_vector(8 downto 0);
signal send_level : std_logic_vector(8 downto 0);
signal send_dma : std_logic_vector(1 downto 0); --active & request
signal send_enable: std_logic;
begin --architecture
dma_proc: process(clk, reset, enable_eth, select_eth,
data_read, pause_in, mem_address, mem_byte_we, data_w,
E_RX_CLK, E_RX_DV, E_RXD, E_TX_CLK,
rec_clk, rec_store, rec_data,
rec_cnt, rec_words, rec_dma, rec_done,
send_clk, send_read, send_data, send_cnt, send_words,
send_level, send_dma, send_enable)
begin
if reset = '1' then
rec_clk <= "00";
rec_cnt <= "000";
rec_words <= ZERO(13 downto 0);
rec_dma <= "00";
rec_done <= '0';
send_clk <= "00";
send_cnt <= "000";
send_words <= ZERO(8 downto 0);
send_level <= ZERO(8 downto 0);
send_dma <= "00";
send_enable <= '0';
elsif rising_edge(clk) then
--Receive nibble on low->high E_RX_CLK. Send to DDR every 32 bits.
rec_clk <= rec_clk(0) & E_RX_CLK;
if rec_clk = "01" and enable_eth = '1' then
if E_RX_DV = '1' or rec_cnt /= "000" then
if rec_cnt = "111" then
rec_store <= rec_data & E_RXD;
rec_dma(0) <= '1'; --request DMA
end if;
rec_data <= rec_data(23 downto 0) & E_RXD;
rec_cnt <= rec_cnt + 1;
end if;
end if;
--Set transmit count or clear receive interrupt
if select_eth = '1' then
if mem_byte_we /= "0000" then
send_cnt <= "000";
send_words <= ZERO(8 downto 0);
send_level <= data_w(8 downto 0);
send_dma(0) <= '1';
else
rec_done <= '0';
end if;
end if;
--Transmit nibble on low->high E_TX_CLK. Get 32 bits from DDR.
send_clk <= send_clk(0) & E_TX_CLK;
if send_clk = "01" then
if send_cnt = "111" then
if send_words /= send_level then
send_data <= send_read;
send_dma(0) <= '1';
send_enable <= '1';
else
send_enable <= '0';
end if;
else
send_data(31 downto 4) <= send_data(27 downto 0);
end if;
send_cnt <= send_cnt + 1;
end if;
--Pick which type of DMA operation: bit0 = request; bit1 = active
if pause_in = '0' then
if rec_dma(1) = '1' then
rec_dma <= "00"; --DMA done
rec_words <= rec_words + 1;
if E_RX_DV = '0' then
rec_done <= '1';
end if;
elsif send_dma(1) = '1' then
send_dma <= "00";
send_words <= send_words + 1;
send_read <= data_read;
elsif rec_dma(0) = '1' then
rec_dma(1) <= '1'; --start DMA
elsif send_dma(0) = '1' then
send_dma(1) <= '1'; --start DMA
end if;
end if;
end if; --rising_edge(clk)
E_TXD <= send_data(31 downto 28);
E_TX_EN <= send_enable;
rec_isr <= rec_done;
if send_words = send_level then
send_isr <= '1';
else
send_isr <= '0';
end if;
if rec_dma(1) = '1' then
address <= "0001001111111111" & rec_words; --0x13ff0000
byte_we <= "1111";
data_write <= rec_store;
pause_out <= '1'; --to CPU
elsif send_dma(1) = '1' then
address <= "000100111111111000000" & send_words; --0x13fe0000
byte_we <= "0000";
data_write <= data_w;
pause_out <= '1';
else
address <= mem_address; --Send request from CPU to DDR
byte_we <= mem_byte_we;
data_write <= data_w;
pause_out <= '0';
end if;
end process;
end; --architecture logic
|
---------------------------------------------------------------------
-- TITLE: Ethernet DMA
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 12/27/07
-- FILENAME: eth_dma.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Ethernet DMA (Direct Memory Access) controller.
-- Reads four bits and writes four bits from/to the Ethernet PHY each
-- 2.5 MHz clock cycle. Received data is DMAed starting at 0x13ff0000
-- transmit data is read from 0x13fd0000.
-- To send a packet write bytes/4 to Ethernet send register.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use work.mlite_pack.all;
entity eth_dma is port(
clk : in std_logic; --25 MHz
reset : in std_logic;
enable_eth : in std_logic; --enable receive DMA
select_eth : in std_logic;
rec_isr : out std_logic; --data received
send_isr : out std_logic; --transmit done
address : out std_logic_vector(31 downto 2); --to DDR
byte_we : out std_logic_vector(3 downto 0);
data_write : out std_logic_vector(31 downto 0);
data_read : in std_logic_vector(31 downto 0);
pause_in : in std_logic;
mem_address : in std_logic_vector(31 downto 2); --from CPU
mem_byte_we : in std_logic_vector(3 downto 0);
data_w : in std_logic_vector(31 downto 0);
pause_out : out std_logic;
E_RX_CLK : in std_logic; --2.5 MHz receive
E_RX_DV : in std_logic; --data valid
E_RXD : in std_logic_vector(3 downto 0); --receive nibble
E_TX_CLK : in std_logic; --2.5 MHz transmit
E_TX_EN : out std_logic; --transmit enable
E_TXD : out std_logic_vector(3 downto 0)); --transmit nibble
end; --entity eth_dma
architecture logic of eth_dma is
signal rec_clk : std_logic_vector(1 downto 0); --receive
signal rec_store : std_logic_vector(31 downto 0); --to DDR
signal rec_data : std_logic_vector(27 downto 0);
signal rec_cnt : std_logic_vector(2 downto 0); --nibbles
signal rec_words : std_logic_vector(13 downto 0);
signal rec_dma : std_logic_vector(1 downto 0); --active & request
signal rec_done : std_logic;
signal send_clk : std_logic_vector(1 downto 0); --transmit
signal send_read : std_logic_vector(31 downto 0); --from DDR
signal send_data : std_logic_vector(31 downto 0);
signal send_cnt : std_logic_vector(2 downto 0); --nibbles
signal send_words : std_logic_vector(8 downto 0);
signal send_level : std_logic_vector(8 downto 0);
signal send_dma : std_logic_vector(1 downto 0); --active & request
signal send_enable: std_logic;
begin --architecture
dma_proc: process(clk, reset, enable_eth, select_eth,
data_read, pause_in, mem_address, mem_byte_we, data_w,
E_RX_CLK, E_RX_DV, E_RXD, E_TX_CLK,
rec_clk, rec_store, rec_data,
rec_cnt, rec_words, rec_dma, rec_done,
send_clk, send_read, send_data, send_cnt, send_words,
send_level, send_dma, send_enable)
begin
if reset = '1' then
rec_clk <= "00";
rec_cnt <= "000";
rec_words <= ZERO(13 downto 0);
rec_dma <= "00";
rec_done <= '0';
send_clk <= "00";
send_cnt <= "000";
send_words <= ZERO(8 downto 0);
send_level <= ZERO(8 downto 0);
send_dma <= "00";
send_enable <= '0';
elsif rising_edge(clk) then
--Receive nibble on low->high E_RX_CLK. Send to DDR every 32 bits.
rec_clk <= rec_clk(0) & E_RX_CLK;
if rec_clk = "01" and enable_eth = '1' then
if E_RX_DV = '1' or rec_cnt /= "000" then
if rec_cnt = "111" then
rec_store <= rec_data & E_RXD;
rec_dma(0) <= '1'; --request DMA
end if;
rec_data <= rec_data(23 downto 0) & E_RXD;
rec_cnt <= rec_cnt + 1;
end if;
end if;
--Set transmit count or clear receive interrupt
if select_eth = '1' then
if mem_byte_we /= "0000" then
send_cnt <= "000";
send_words <= ZERO(8 downto 0);
send_level <= data_w(8 downto 0);
send_dma(0) <= '1';
else
rec_done <= '0';
end if;
end if;
--Transmit nibble on low->high E_TX_CLK. Get 32 bits from DDR.
send_clk <= send_clk(0) & E_TX_CLK;
if send_clk = "01" then
if send_cnt = "111" then
if send_words /= send_level then
send_data <= send_read;
send_dma(0) <= '1';
send_enable <= '1';
else
send_enable <= '0';
end if;
else
send_data(31 downto 4) <= send_data(27 downto 0);
end if;
send_cnt <= send_cnt + 1;
end if;
--Pick which type of DMA operation: bit0 = request; bit1 = active
if pause_in = '0' then
if rec_dma(1) = '1' then
rec_dma <= "00"; --DMA done
rec_words <= rec_words + 1;
if E_RX_DV = '0' then
rec_done <= '1';
end if;
elsif send_dma(1) = '1' then
send_dma <= "00";
send_words <= send_words + 1;
send_read <= data_read;
elsif rec_dma(0) = '1' then
rec_dma(1) <= '1'; --start DMA
elsif send_dma(0) = '1' then
send_dma(1) <= '1'; --start DMA
end if;
end if;
end if; --rising_edge(clk)
E_TXD <= send_data(31 downto 28);
E_TX_EN <= send_enable;
rec_isr <= rec_done;
if send_words = send_level then
send_isr <= '1';
else
send_isr <= '0';
end if;
if rec_dma(1) = '1' then
address <= "0001001111111111" & rec_words; --0x13ff0000
byte_we <= "1111";
data_write <= rec_store;
pause_out <= '1'; --to CPU
elsif send_dma(1) = '1' then
address <= "000100111111111000000" & send_words; --0x13fe0000
byte_we <= "0000";
data_write <= data_w;
pause_out <= '1';
else
address <= mem_address; --Send request from CPU to DDR
byte_we <= mem_byte_we;
data_write <= data_w;
pause_out <= '0';
end if;
end process;
end; --architecture logic
|
---------------------------------------------------------------------
-- TITLE: Ethernet DMA
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 12/27/07
-- FILENAME: eth_dma.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Ethernet DMA (Direct Memory Access) controller.
-- Reads four bits and writes four bits from/to the Ethernet PHY each
-- 2.5 MHz clock cycle. Received data is DMAed starting at 0x13ff0000
-- transmit data is read from 0x13fd0000.
-- To send a packet write bytes/4 to Ethernet send register.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use work.mlite_pack.all;
entity eth_dma is port(
clk : in std_logic; --25 MHz
reset : in std_logic;
enable_eth : in std_logic; --enable receive DMA
select_eth : in std_logic;
rec_isr : out std_logic; --data received
send_isr : out std_logic; --transmit done
address : out std_logic_vector(31 downto 2); --to DDR
byte_we : out std_logic_vector(3 downto 0);
data_write : out std_logic_vector(31 downto 0);
data_read : in std_logic_vector(31 downto 0);
pause_in : in std_logic;
mem_address : in std_logic_vector(31 downto 2); --from CPU
mem_byte_we : in std_logic_vector(3 downto 0);
data_w : in std_logic_vector(31 downto 0);
pause_out : out std_logic;
E_RX_CLK : in std_logic; --2.5 MHz receive
E_RX_DV : in std_logic; --data valid
E_RXD : in std_logic_vector(3 downto 0); --receive nibble
E_TX_CLK : in std_logic; --2.5 MHz transmit
E_TX_EN : out std_logic; --transmit enable
E_TXD : out std_logic_vector(3 downto 0)); --transmit nibble
end; --entity eth_dma
architecture logic of eth_dma is
signal rec_clk : std_logic_vector(1 downto 0); --receive
signal rec_store : std_logic_vector(31 downto 0); --to DDR
signal rec_data : std_logic_vector(27 downto 0);
signal rec_cnt : std_logic_vector(2 downto 0); --nibbles
signal rec_words : std_logic_vector(13 downto 0);
signal rec_dma : std_logic_vector(1 downto 0); --active & request
signal rec_done : std_logic;
signal send_clk : std_logic_vector(1 downto 0); --transmit
signal send_read : std_logic_vector(31 downto 0); --from DDR
signal send_data : std_logic_vector(31 downto 0);
signal send_cnt : std_logic_vector(2 downto 0); --nibbles
signal send_words : std_logic_vector(8 downto 0);
signal send_level : std_logic_vector(8 downto 0);
signal send_dma : std_logic_vector(1 downto 0); --active & request
signal send_enable: std_logic;
begin --architecture
dma_proc: process(clk, reset, enable_eth, select_eth,
data_read, pause_in, mem_address, mem_byte_we, data_w,
E_RX_CLK, E_RX_DV, E_RXD, E_TX_CLK,
rec_clk, rec_store, rec_data,
rec_cnt, rec_words, rec_dma, rec_done,
send_clk, send_read, send_data, send_cnt, send_words,
send_level, send_dma, send_enable)
begin
if reset = '1' then
rec_clk <= "00";
rec_cnt <= "000";
rec_words <= ZERO(13 downto 0);
rec_dma <= "00";
rec_done <= '0';
send_clk <= "00";
send_cnt <= "000";
send_words <= ZERO(8 downto 0);
send_level <= ZERO(8 downto 0);
send_dma <= "00";
send_enable <= '0';
elsif rising_edge(clk) then
--Receive nibble on low->high E_RX_CLK. Send to DDR every 32 bits.
rec_clk <= rec_clk(0) & E_RX_CLK;
if rec_clk = "01" and enable_eth = '1' then
if E_RX_DV = '1' or rec_cnt /= "000" then
if rec_cnt = "111" then
rec_store <= rec_data & E_RXD;
rec_dma(0) <= '1'; --request DMA
end if;
rec_data <= rec_data(23 downto 0) & E_RXD;
rec_cnt <= rec_cnt + 1;
end if;
end if;
--Set transmit count or clear receive interrupt
if select_eth = '1' then
if mem_byte_we /= "0000" then
send_cnt <= "000";
send_words <= ZERO(8 downto 0);
send_level <= data_w(8 downto 0);
send_dma(0) <= '1';
else
rec_done <= '0';
end if;
end if;
--Transmit nibble on low->high E_TX_CLK. Get 32 bits from DDR.
send_clk <= send_clk(0) & E_TX_CLK;
if send_clk = "01" then
if send_cnt = "111" then
if send_words /= send_level then
send_data <= send_read;
send_dma(0) <= '1';
send_enable <= '1';
else
send_enable <= '0';
end if;
else
send_data(31 downto 4) <= send_data(27 downto 0);
end if;
send_cnt <= send_cnt + 1;
end if;
--Pick which type of DMA operation: bit0 = request; bit1 = active
if pause_in = '0' then
if rec_dma(1) = '1' then
rec_dma <= "00"; --DMA done
rec_words <= rec_words + 1;
if E_RX_DV = '0' then
rec_done <= '1';
end if;
elsif send_dma(1) = '1' then
send_dma <= "00";
send_words <= send_words + 1;
send_read <= data_read;
elsif rec_dma(0) = '1' then
rec_dma(1) <= '1'; --start DMA
elsif send_dma(0) = '1' then
send_dma(1) <= '1'; --start DMA
end if;
end if;
end if; --rising_edge(clk)
E_TXD <= send_data(31 downto 28);
E_TX_EN <= send_enable;
rec_isr <= rec_done;
if send_words = send_level then
send_isr <= '1';
else
send_isr <= '0';
end if;
if rec_dma(1) = '1' then
address <= "0001001111111111" & rec_words; --0x13ff0000
byte_we <= "1111";
data_write <= rec_store;
pause_out <= '1'; --to CPU
elsif send_dma(1) = '1' then
address <= "000100111111111000000" & send_words; --0x13fe0000
byte_we <= "0000";
data_write <= data_w;
pause_out <= '1';
else
address <= mem_address; --Send request from CPU to DDR
byte_we <= mem_byte_we;
data_write <= data_w;
pause_out <= '0';
end if;
end process;
end; --architecture logic
|
---------------------------------------------------------------------
-- TITLE: Ethernet DMA
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 12/27/07
-- FILENAME: eth_dma.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Ethernet DMA (Direct Memory Access) controller.
-- Reads four bits and writes four bits from/to the Ethernet PHY each
-- 2.5 MHz clock cycle. Received data is DMAed starting at 0x13ff0000
-- transmit data is read from 0x13fd0000.
-- To send a packet write bytes/4 to Ethernet send register.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use work.mlite_pack.all;
entity eth_dma is port(
clk : in std_logic; --25 MHz
reset : in std_logic;
enable_eth : in std_logic; --enable receive DMA
select_eth : in std_logic;
rec_isr : out std_logic; --data received
send_isr : out std_logic; --transmit done
address : out std_logic_vector(31 downto 2); --to DDR
byte_we : out std_logic_vector(3 downto 0);
data_write : out std_logic_vector(31 downto 0);
data_read : in std_logic_vector(31 downto 0);
pause_in : in std_logic;
mem_address : in std_logic_vector(31 downto 2); --from CPU
mem_byte_we : in std_logic_vector(3 downto 0);
data_w : in std_logic_vector(31 downto 0);
pause_out : out std_logic;
E_RX_CLK : in std_logic; --2.5 MHz receive
E_RX_DV : in std_logic; --data valid
E_RXD : in std_logic_vector(3 downto 0); --receive nibble
E_TX_CLK : in std_logic; --2.5 MHz transmit
E_TX_EN : out std_logic; --transmit enable
E_TXD : out std_logic_vector(3 downto 0)); --transmit nibble
end; --entity eth_dma
architecture logic of eth_dma is
signal rec_clk : std_logic_vector(1 downto 0); --receive
signal rec_store : std_logic_vector(31 downto 0); --to DDR
signal rec_data : std_logic_vector(27 downto 0);
signal rec_cnt : std_logic_vector(2 downto 0); --nibbles
signal rec_words : std_logic_vector(13 downto 0);
signal rec_dma : std_logic_vector(1 downto 0); --active & request
signal rec_done : std_logic;
signal send_clk : std_logic_vector(1 downto 0); --transmit
signal send_read : std_logic_vector(31 downto 0); --from DDR
signal send_data : std_logic_vector(31 downto 0);
signal send_cnt : std_logic_vector(2 downto 0); --nibbles
signal send_words : std_logic_vector(8 downto 0);
signal send_level : std_logic_vector(8 downto 0);
signal send_dma : std_logic_vector(1 downto 0); --active & request
signal send_enable: std_logic;
begin --architecture
dma_proc: process(clk, reset, enable_eth, select_eth,
data_read, pause_in, mem_address, mem_byte_we, data_w,
E_RX_CLK, E_RX_DV, E_RXD, E_TX_CLK,
rec_clk, rec_store, rec_data,
rec_cnt, rec_words, rec_dma, rec_done,
send_clk, send_read, send_data, send_cnt, send_words,
send_level, send_dma, send_enable)
begin
if reset = '1' then
rec_clk <= "00";
rec_cnt <= "000";
rec_words <= ZERO(13 downto 0);
rec_dma <= "00";
rec_done <= '0';
send_clk <= "00";
send_cnt <= "000";
send_words <= ZERO(8 downto 0);
send_level <= ZERO(8 downto 0);
send_dma <= "00";
send_enable <= '0';
elsif rising_edge(clk) then
--Receive nibble on low->high E_RX_CLK. Send to DDR every 32 bits.
rec_clk <= rec_clk(0) & E_RX_CLK;
if rec_clk = "01" and enable_eth = '1' then
if E_RX_DV = '1' or rec_cnt /= "000" then
if rec_cnt = "111" then
rec_store <= rec_data & E_RXD;
rec_dma(0) <= '1'; --request DMA
end if;
rec_data <= rec_data(23 downto 0) & E_RXD;
rec_cnt <= rec_cnt + 1;
end if;
end if;
--Set transmit count or clear receive interrupt
if select_eth = '1' then
if mem_byte_we /= "0000" then
send_cnt <= "000";
send_words <= ZERO(8 downto 0);
send_level <= data_w(8 downto 0);
send_dma(0) <= '1';
else
rec_done <= '0';
end if;
end if;
--Transmit nibble on low->high E_TX_CLK. Get 32 bits from DDR.
send_clk <= send_clk(0) & E_TX_CLK;
if send_clk = "01" then
if send_cnt = "111" then
if send_words /= send_level then
send_data <= send_read;
send_dma(0) <= '1';
send_enable <= '1';
else
send_enable <= '0';
end if;
else
send_data(31 downto 4) <= send_data(27 downto 0);
end if;
send_cnt <= send_cnt + 1;
end if;
--Pick which type of DMA operation: bit0 = request; bit1 = active
if pause_in = '0' then
if rec_dma(1) = '1' then
rec_dma <= "00"; --DMA done
rec_words <= rec_words + 1;
if E_RX_DV = '0' then
rec_done <= '1';
end if;
elsif send_dma(1) = '1' then
send_dma <= "00";
send_words <= send_words + 1;
send_read <= data_read;
elsif rec_dma(0) = '1' then
rec_dma(1) <= '1'; --start DMA
elsif send_dma(0) = '1' then
send_dma(1) <= '1'; --start DMA
end if;
end if;
end if; --rising_edge(clk)
E_TXD <= send_data(31 downto 28);
E_TX_EN <= send_enable;
rec_isr <= rec_done;
if send_words = send_level then
send_isr <= '1';
else
send_isr <= '0';
end if;
if rec_dma(1) = '1' then
address <= "0001001111111111" & rec_words; --0x13ff0000
byte_we <= "1111";
data_write <= rec_store;
pause_out <= '1'; --to CPU
elsif send_dma(1) = '1' then
address <= "000100111111111000000" & send_words; --0x13fe0000
byte_we <= "0000";
data_write <= data_w;
pause_out <= '1';
else
address <= mem_address; --Send request from CPU to DDR
byte_we <= mem_byte_we;
data_write <= data_w;
pause_out <= '0';
end if;
end process;
end; --architecture logic
|
---------------------------------------------------------------------
-- TITLE: Ethernet DMA
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 12/27/07
-- FILENAME: eth_dma.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Ethernet DMA (Direct Memory Access) controller.
-- Reads four bits and writes four bits from/to the Ethernet PHY each
-- 2.5 MHz clock cycle. Received data is DMAed starting at 0x13ff0000
-- transmit data is read from 0x13fd0000.
-- To send a packet write bytes/4 to Ethernet send register.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use work.mlite_pack.all;
entity eth_dma is port(
clk : in std_logic; --25 MHz
reset : in std_logic;
enable_eth : in std_logic; --enable receive DMA
select_eth : in std_logic;
rec_isr : out std_logic; --data received
send_isr : out std_logic; --transmit done
address : out std_logic_vector(31 downto 2); --to DDR
byte_we : out std_logic_vector(3 downto 0);
data_write : out std_logic_vector(31 downto 0);
data_read : in std_logic_vector(31 downto 0);
pause_in : in std_logic;
mem_address : in std_logic_vector(31 downto 2); --from CPU
mem_byte_we : in std_logic_vector(3 downto 0);
data_w : in std_logic_vector(31 downto 0);
pause_out : out std_logic;
E_RX_CLK : in std_logic; --2.5 MHz receive
E_RX_DV : in std_logic; --data valid
E_RXD : in std_logic_vector(3 downto 0); --receive nibble
E_TX_CLK : in std_logic; --2.5 MHz transmit
E_TX_EN : out std_logic; --transmit enable
E_TXD : out std_logic_vector(3 downto 0)); --transmit nibble
end; --entity eth_dma
architecture logic of eth_dma is
signal rec_clk : std_logic_vector(1 downto 0); --receive
signal rec_store : std_logic_vector(31 downto 0); --to DDR
signal rec_data : std_logic_vector(27 downto 0);
signal rec_cnt : std_logic_vector(2 downto 0); --nibbles
signal rec_words : std_logic_vector(13 downto 0);
signal rec_dma : std_logic_vector(1 downto 0); --active & request
signal rec_done : std_logic;
signal send_clk : std_logic_vector(1 downto 0); --transmit
signal send_read : std_logic_vector(31 downto 0); --from DDR
signal send_data : std_logic_vector(31 downto 0);
signal send_cnt : std_logic_vector(2 downto 0); --nibbles
signal send_words : std_logic_vector(8 downto 0);
signal send_level : std_logic_vector(8 downto 0);
signal send_dma : std_logic_vector(1 downto 0); --active & request
signal send_enable: std_logic;
begin --architecture
dma_proc: process(clk, reset, enable_eth, select_eth,
data_read, pause_in, mem_address, mem_byte_we, data_w,
E_RX_CLK, E_RX_DV, E_RXD, E_TX_CLK,
rec_clk, rec_store, rec_data,
rec_cnt, rec_words, rec_dma, rec_done,
send_clk, send_read, send_data, send_cnt, send_words,
send_level, send_dma, send_enable)
begin
if reset = '1' then
rec_clk <= "00";
rec_cnt <= "000";
rec_words <= ZERO(13 downto 0);
rec_dma <= "00";
rec_done <= '0';
send_clk <= "00";
send_cnt <= "000";
send_words <= ZERO(8 downto 0);
send_level <= ZERO(8 downto 0);
send_dma <= "00";
send_enable <= '0';
elsif rising_edge(clk) then
--Receive nibble on low->high E_RX_CLK. Send to DDR every 32 bits.
rec_clk <= rec_clk(0) & E_RX_CLK;
if rec_clk = "01" and enable_eth = '1' then
if E_RX_DV = '1' or rec_cnt /= "000" then
if rec_cnt = "111" then
rec_store <= rec_data & E_RXD;
rec_dma(0) <= '1'; --request DMA
end if;
rec_data <= rec_data(23 downto 0) & E_RXD;
rec_cnt <= rec_cnt + 1;
end if;
end if;
--Set transmit count or clear receive interrupt
if select_eth = '1' then
if mem_byte_we /= "0000" then
send_cnt <= "000";
send_words <= ZERO(8 downto 0);
send_level <= data_w(8 downto 0);
send_dma(0) <= '1';
else
rec_done <= '0';
end if;
end if;
--Transmit nibble on low->high E_TX_CLK. Get 32 bits from DDR.
send_clk <= send_clk(0) & E_TX_CLK;
if send_clk = "01" then
if send_cnt = "111" then
if send_words /= send_level then
send_data <= send_read;
send_dma(0) <= '1';
send_enable <= '1';
else
send_enable <= '0';
end if;
else
send_data(31 downto 4) <= send_data(27 downto 0);
end if;
send_cnt <= send_cnt + 1;
end if;
--Pick which type of DMA operation: bit0 = request; bit1 = active
if pause_in = '0' then
if rec_dma(1) = '1' then
rec_dma <= "00"; --DMA done
rec_words <= rec_words + 1;
if E_RX_DV = '0' then
rec_done <= '1';
end if;
elsif send_dma(1) = '1' then
send_dma <= "00";
send_words <= send_words + 1;
send_read <= data_read;
elsif rec_dma(0) = '1' then
rec_dma(1) <= '1'; --start DMA
elsif send_dma(0) = '1' then
send_dma(1) <= '1'; --start DMA
end if;
end if;
end if; --rising_edge(clk)
E_TXD <= send_data(31 downto 28);
E_TX_EN <= send_enable;
rec_isr <= rec_done;
if send_words = send_level then
send_isr <= '1';
else
send_isr <= '0';
end if;
if rec_dma(1) = '1' then
address <= "0001001111111111" & rec_words; --0x13ff0000
byte_we <= "1111";
data_write <= rec_store;
pause_out <= '1'; --to CPU
elsif send_dma(1) = '1' then
address <= "000100111111111000000" & send_words; --0x13fe0000
byte_we <= "0000";
data_write <= data_w;
pause_out <= '1';
else
address <= mem_address; --Send request from CPU to DDR
byte_we <= mem_byte_we;
data_write <= data_w;
pause_out <= '0';
end if;
end process;
end; --architecture logic
|
---------------------------------------------------------------------
-- TITLE: Ethernet DMA
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 12/27/07
-- FILENAME: eth_dma.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Ethernet DMA (Direct Memory Access) controller.
-- Reads four bits and writes four bits from/to the Ethernet PHY each
-- 2.5 MHz clock cycle. Received data is DMAed starting at 0x13ff0000
-- transmit data is read from 0x13fd0000.
-- To send a packet write bytes/4 to Ethernet send register.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use work.mlite_pack.all;
entity eth_dma is port(
clk : in std_logic; --25 MHz
reset : in std_logic;
enable_eth : in std_logic; --enable receive DMA
select_eth : in std_logic;
rec_isr : out std_logic; --data received
send_isr : out std_logic; --transmit done
address : out std_logic_vector(31 downto 2); --to DDR
byte_we : out std_logic_vector(3 downto 0);
data_write : out std_logic_vector(31 downto 0);
data_read : in std_logic_vector(31 downto 0);
pause_in : in std_logic;
mem_address : in std_logic_vector(31 downto 2); --from CPU
mem_byte_we : in std_logic_vector(3 downto 0);
data_w : in std_logic_vector(31 downto 0);
pause_out : out std_logic;
E_RX_CLK : in std_logic; --2.5 MHz receive
E_RX_DV : in std_logic; --data valid
E_RXD : in std_logic_vector(3 downto 0); --receive nibble
E_TX_CLK : in std_logic; --2.5 MHz transmit
E_TX_EN : out std_logic; --transmit enable
E_TXD : out std_logic_vector(3 downto 0)); --transmit nibble
end; --entity eth_dma
architecture logic of eth_dma is
signal rec_clk : std_logic_vector(1 downto 0); --receive
signal rec_store : std_logic_vector(31 downto 0); --to DDR
signal rec_data : std_logic_vector(27 downto 0);
signal rec_cnt : std_logic_vector(2 downto 0); --nibbles
signal rec_words : std_logic_vector(13 downto 0);
signal rec_dma : std_logic_vector(1 downto 0); --active & request
signal rec_done : std_logic;
signal send_clk : std_logic_vector(1 downto 0); --transmit
signal send_read : std_logic_vector(31 downto 0); --from DDR
signal send_data : std_logic_vector(31 downto 0);
signal send_cnt : std_logic_vector(2 downto 0); --nibbles
signal send_words : std_logic_vector(8 downto 0);
signal send_level : std_logic_vector(8 downto 0);
signal send_dma : std_logic_vector(1 downto 0); --active & request
signal send_enable: std_logic;
begin --architecture
dma_proc: process(clk, reset, enable_eth, select_eth,
data_read, pause_in, mem_address, mem_byte_we, data_w,
E_RX_CLK, E_RX_DV, E_RXD, E_TX_CLK,
rec_clk, rec_store, rec_data,
rec_cnt, rec_words, rec_dma, rec_done,
send_clk, send_read, send_data, send_cnt, send_words,
send_level, send_dma, send_enable)
begin
if reset = '1' then
rec_clk <= "00";
rec_cnt <= "000";
rec_words <= ZERO(13 downto 0);
rec_dma <= "00";
rec_done <= '0';
send_clk <= "00";
send_cnt <= "000";
send_words <= ZERO(8 downto 0);
send_level <= ZERO(8 downto 0);
send_dma <= "00";
send_enable <= '0';
elsif rising_edge(clk) then
--Receive nibble on low->high E_RX_CLK. Send to DDR every 32 bits.
rec_clk <= rec_clk(0) & E_RX_CLK;
if rec_clk = "01" and enable_eth = '1' then
if E_RX_DV = '1' or rec_cnt /= "000" then
if rec_cnt = "111" then
rec_store <= rec_data & E_RXD;
rec_dma(0) <= '1'; --request DMA
end if;
rec_data <= rec_data(23 downto 0) & E_RXD;
rec_cnt <= rec_cnt + 1;
end if;
end if;
--Set transmit count or clear receive interrupt
if select_eth = '1' then
if mem_byte_we /= "0000" then
send_cnt <= "000";
send_words <= ZERO(8 downto 0);
send_level <= data_w(8 downto 0);
send_dma(0) <= '1';
else
rec_done <= '0';
end if;
end if;
--Transmit nibble on low->high E_TX_CLK. Get 32 bits from DDR.
send_clk <= send_clk(0) & E_TX_CLK;
if send_clk = "01" then
if send_cnt = "111" then
if send_words /= send_level then
send_data <= send_read;
send_dma(0) <= '1';
send_enable <= '1';
else
send_enable <= '0';
end if;
else
send_data(31 downto 4) <= send_data(27 downto 0);
end if;
send_cnt <= send_cnt + 1;
end if;
--Pick which type of DMA operation: bit0 = request; bit1 = active
if pause_in = '0' then
if rec_dma(1) = '1' then
rec_dma <= "00"; --DMA done
rec_words <= rec_words + 1;
if E_RX_DV = '0' then
rec_done <= '1';
end if;
elsif send_dma(1) = '1' then
send_dma <= "00";
send_words <= send_words + 1;
send_read <= data_read;
elsif rec_dma(0) = '1' then
rec_dma(1) <= '1'; --start DMA
elsif send_dma(0) = '1' then
send_dma(1) <= '1'; --start DMA
end if;
end if;
end if; --rising_edge(clk)
E_TXD <= send_data(31 downto 28);
E_TX_EN <= send_enable;
rec_isr <= rec_done;
if send_words = send_level then
send_isr <= '1';
else
send_isr <= '0';
end if;
if rec_dma(1) = '1' then
address <= "0001001111111111" & rec_words; --0x13ff0000
byte_we <= "1111";
data_write <= rec_store;
pause_out <= '1'; --to CPU
elsif send_dma(1) = '1' then
address <= "000100111111111000000" & send_words; --0x13fe0000
byte_we <= "0000";
data_write <= data_w;
pause_out <= '1';
else
address <= mem_address; --Send request from CPU to DDR
byte_we <= mem_byte_we;
data_write <= data_w;
pause_out <= '0';
end if;
end process;
end; --architecture logic
|
---------------------------------------------------------------------
-- TITLE: Ethernet DMA
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 12/27/07
-- FILENAME: eth_dma.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Ethernet DMA (Direct Memory Access) controller.
-- Reads four bits and writes four bits from/to the Ethernet PHY each
-- 2.5 MHz clock cycle. Received data is DMAed starting at 0x13ff0000
-- transmit data is read from 0x13fd0000.
-- To send a packet write bytes/4 to Ethernet send register.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use work.mlite_pack.all;
entity eth_dma is port(
clk : in std_logic; --25 MHz
reset : in std_logic;
enable_eth : in std_logic; --enable receive DMA
select_eth : in std_logic;
rec_isr : out std_logic; --data received
send_isr : out std_logic; --transmit done
address : out std_logic_vector(31 downto 2); --to DDR
byte_we : out std_logic_vector(3 downto 0);
data_write : out std_logic_vector(31 downto 0);
data_read : in std_logic_vector(31 downto 0);
pause_in : in std_logic;
mem_address : in std_logic_vector(31 downto 2); --from CPU
mem_byte_we : in std_logic_vector(3 downto 0);
data_w : in std_logic_vector(31 downto 0);
pause_out : out std_logic;
E_RX_CLK : in std_logic; --2.5 MHz receive
E_RX_DV : in std_logic; --data valid
E_RXD : in std_logic_vector(3 downto 0); --receive nibble
E_TX_CLK : in std_logic; --2.5 MHz transmit
E_TX_EN : out std_logic; --transmit enable
E_TXD : out std_logic_vector(3 downto 0)); --transmit nibble
end; --entity eth_dma
architecture logic of eth_dma is
signal rec_clk : std_logic_vector(1 downto 0); --receive
signal rec_store : std_logic_vector(31 downto 0); --to DDR
signal rec_data : std_logic_vector(27 downto 0);
signal rec_cnt : std_logic_vector(2 downto 0); --nibbles
signal rec_words : std_logic_vector(13 downto 0);
signal rec_dma : std_logic_vector(1 downto 0); --active & request
signal rec_done : std_logic;
signal send_clk : std_logic_vector(1 downto 0); --transmit
signal send_read : std_logic_vector(31 downto 0); --from DDR
signal send_data : std_logic_vector(31 downto 0);
signal send_cnt : std_logic_vector(2 downto 0); --nibbles
signal send_words : std_logic_vector(8 downto 0);
signal send_level : std_logic_vector(8 downto 0);
signal send_dma : std_logic_vector(1 downto 0); --active & request
signal send_enable: std_logic;
begin --architecture
dma_proc: process(clk, reset, enable_eth, select_eth,
data_read, pause_in, mem_address, mem_byte_we, data_w,
E_RX_CLK, E_RX_DV, E_RXD, E_TX_CLK,
rec_clk, rec_store, rec_data,
rec_cnt, rec_words, rec_dma, rec_done,
send_clk, send_read, send_data, send_cnt, send_words,
send_level, send_dma, send_enable)
begin
if reset = '1' then
rec_clk <= "00";
rec_cnt <= "000";
rec_words <= ZERO(13 downto 0);
rec_dma <= "00";
rec_done <= '0';
send_clk <= "00";
send_cnt <= "000";
send_words <= ZERO(8 downto 0);
send_level <= ZERO(8 downto 0);
send_dma <= "00";
send_enable <= '0';
elsif rising_edge(clk) then
--Receive nibble on low->high E_RX_CLK. Send to DDR every 32 bits.
rec_clk <= rec_clk(0) & E_RX_CLK;
if rec_clk = "01" and enable_eth = '1' then
if E_RX_DV = '1' or rec_cnt /= "000" then
if rec_cnt = "111" then
rec_store <= rec_data & E_RXD;
rec_dma(0) <= '1'; --request DMA
end if;
rec_data <= rec_data(23 downto 0) & E_RXD;
rec_cnt <= rec_cnt + 1;
end if;
end if;
--Set transmit count or clear receive interrupt
if select_eth = '1' then
if mem_byte_we /= "0000" then
send_cnt <= "000";
send_words <= ZERO(8 downto 0);
send_level <= data_w(8 downto 0);
send_dma(0) <= '1';
else
rec_done <= '0';
end if;
end if;
--Transmit nibble on low->high E_TX_CLK. Get 32 bits from DDR.
send_clk <= send_clk(0) & E_TX_CLK;
if send_clk = "01" then
if send_cnt = "111" then
if send_words /= send_level then
send_data <= send_read;
send_dma(0) <= '1';
send_enable <= '1';
else
send_enable <= '0';
end if;
else
send_data(31 downto 4) <= send_data(27 downto 0);
end if;
send_cnt <= send_cnt + 1;
end if;
--Pick which type of DMA operation: bit0 = request; bit1 = active
if pause_in = '0' then
if rec_dma(1) = '1' then
rec_dma <= "00"; --DMA done
rec_words <= rec_words + 1;
if E_RX_DV = '0' then
rec_done <= '1';
end if;
elsif send_dma(1) = '1' then
send_dma <= "00";
send_words <= send_words + 1;
send_read <= data_read;
elsif rec_dma(0) = '1' then
rec_dma(1) <= '1'; --start DMA
elsif send_dma(0) = '1' then
send_dma(1) <= '1'; --start DMA
end if;
end if;
end if; --rising_edge(clk)
E_TXD <= send_data(31 downto 28);
E_TX_EN <= send_enable;
rec_isr <= rec_done;
if send_words = send_level then
send_isr <= '1';
else
send_isr <= '0';
end if;
if rec_dma(1) = '1' then
address <= "0001001111111111" & rec_words; --0x13ff0000
byte_we <= "1111";
data_write <= rec_store;
pause_out <= '1'; --to CPU
elsif send_dma(1) = '1' then
address <= "000100111111111000000" & send_words; --0x13fe0000
byte_we <= "0000";
data_write <= data_w;
pause_out <= '1';
else
address <= mem_address; --Send request from CPU to DDR
byte_we <= mem_byte_we;
data_write <= data_w;
pause_out <= '0';
end if;
end process;
end; --architecture logic
|
---------------------------------------------------------------------
-- TITLE: Ethernet DMA
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 12/27/07
-- FILENAME: eth_dma.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Ethernet DMA (Direct Memory Access) controller.
-- Reads four bits and writes four bits from/to the Ethernet PHY each
-- 2.5 MHz clock cycle. Received data is DMAed starting at 0x13ff0000
-- transmit data is read from 0x13fd0000.
-- To send a packet write bytes/4 to Ethernet send register.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use work.mlite_pack.all;
entity eth_dma is port(
clk : in std_logic; --25 MHz
reset : in std_logic;
enable_eth : in std_logic; --enable receive DMA
select_eth : in std_logic;
rec_isr : out std_logic; --data received
send_isr : out std_logic; --transmit done
address : out std_logic_vector(31 downto 2); --to DDR
byte_we : out std_logic_vector(3 downto 0);
data_write : out std_logic_vector(31 downto 0);
data_read : in std_logic_vector(31 downto 0);
pause_in : in std_logic;
mem_address : in std_logic_vector(31 downto 2); --from CPU
mem_byte_we : in std_logic_vector(3 downto 0);
data_w : in std_logic_vector(31 downto 0);
pause_out : out std_logic;
E_RX_CLK : in std_logic; --2.5 MHz receive
E_RX_DV : in std_logic; --data valid
E_RXD : in std_logic_vector(3 downto 0); --receive nibble
E_TX_CLK : in std_logic; --2.5 MHz transmit
E_TX_EN : out std_logic; --transmit enable
E_TXD : out std_logic_vector(3 downto 0)); --transmit nibble
end; --entity eth_dma
architecture logic of eth_dma is
signal rec_clk : std_logic_vector(1 downto 0); --receive
signal rec_store : std_logic_vector(31 downto 0); --to DDR
signal rec_data : std_logic_vector(27 downto 0);
signal rec_cnt : std_logic_vector(2 downto 0); --nibbles
signal rec_words : std_logic_vector(13 downto 0);
signal rec_dma : std_logic_vector(1 downto 0); --active & request
signal rec_done : std_logic;
signal send_clk : std_logic_vector(1 downto 0); --transmit
signal send_read : std_logic_vector(31 downto 0); --from DDR
signal send_data : std_logic_vector(31 downto 0);
signal send_cnt : std_logic_vector(2 downto 0); --nibbles
signal send_words : std_logic_vector(8 downto 0);
signal send_level : std_logic_vector(8 downto 0);
signal send_dma : std_logic_vector(1 downto 0); --active & request
signal send_enable: std_logic;
begin --architecture
dma_proc: process(clk, reset, enable_eth, select_eth,
data_read, pause_in, mem_address, mem_byte_we, data_w,
E_RX_CLK, E_RX_DV, E_RXD, E_TX_CLK,
rec_clk, rec_store, rec_data,
rec_cnt, rec_words, rec_dma, rec_done,
send_clk, send_read, send_data, send_cnt, send_words,
send_level, send_dma, send_enable)
begin
if reset = '1' then
rec_clk <= "00";
rec_cnt <= "000";
rec_words <= ZERO(13 downto 0);
rec_dma <= "00";
rec_done <= '0';
send_clk <= "00";
send_cnt <= "000";
send_words <= ZERO(8 downto 0);
send_level <= ZERO(8 downto 0);
send_dma <= "00";
send_enable <= '0';
elsif rising_edge(clk) then
--Receive nibble on low->high E_RX_CLK. Send to DDR every 32 bits.
rec_clk <= rec_clk(0) & E_RX_CLK;
if rec_clk = "01" and enable_eth = '1' then
if E_RX_DV = '1' or rec_cnt /= "000" then
if rec_cnt = "111" then
rec_store <= rec_data & E_RXD;
rec_dma(0) <= '1'; --request DMA
end if;
rec_data <= rec_data(23 downto 0) & E_RXD;
rec_cnt <= rec_cnt + 1;
end if;
end if;
--Set transmit count or clear receive interrupt
if select_eth = '1' then
if mem_byte_we /= "0000" then
send_cnt <= "000";
send_words <= ZERO(8 downto 0);
send_level <= data_w(8 downto 0);
send_dma(0) <= '1';
else
rec_done <= '0';
end if;
end if;
--Transmit nibble on low->high E_TX_CLK. Get 32 bits from DDR.
send_clk <= send_clk(0) & E_TX_CLK;
if send_clk = "01" then
if send_cnt = "111" then
if send_words /= send_level then
send_data <= send_read;
send_dma(0) <= '1';
send_enable <= '1';
else
send_enable <= '0';
end if;
else
send_data(31 downto 4) <= send_data(27 downto 0);
end if;
send_cnt <= send_cnt + 1;
end if;
--Pick which type of DMA operation: bit0 = request; bit1 = active
if pause_in = '0' then
if rec_dma(1) = '1' then
rec_dma <= "00"; --DMA done
rec_words <= rec_words + 1;
if E_RX_DV = '0' then
rec_done <= '1';
end if;
elsif send_dma(1) = '1' then
send_dma <= "00";
send_words <= send_words + 1;
send_read <= data_read;
elsif rec_dma(0) = '1' then
rec_dma(1) <= '1'; --start DMA
elsif send_dma(0) = '1' then
send_dma(1) <= '1'; --start DMA
end if;
end if;
end if; --rising_edge(clk)
E_TXD <= send_data(31 downto 28);
E_TX_EN <= send_enable;
rec_isr <= rec_done;
if send_words = send_level then
send_isr <= '1';
else
send_isr <= '0';
end if;
if rec_dma(1) = '1' then
address <= "0001001111111111" & rec_words; --0x13ff0000
byte_we <= "1111";
data_write <= rec_store;
pause_out <= '1'; --to CPU
elsif send_dma(1) = '1' then
address <= "000100111111111000000" & send_words; --0x13fe0000
byte_we <= "0000";
data_write <= data_w;
pause_out <= '1';
else
address <= mem_address; --Send request from CPU to DDR
byte_we <= mem_byte_we;
data_write <= data_w;
pause_out <= '0';
end if;
end process;
end; --architecture logic
|
---------------------------------------------------------------------
-- TITLE: Ethernet DMA
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 12/27/07
-- FILENAME: eth_dma.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Ethernet DMA (Direct Memory Access) controller.
-- Reads four bits and writes four bits from/to the Ethernet PHY each
-- 2.5 MHz clock cycle. Received data is DMAed starting at 0x13ff0000
-- transmit data is read from 0x13fd0000.
-- To send a packet write bytes/4 to Ethernet send register.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use work.mlite_pack.all;
entity eth_dma is port(
clk : in std_logic; --25 MHz
reset : in std_logic;
enable_eth : in std_logic; --enable receive DMA
select_eth : in std_logic;
rec_isr : out std_logic; --data received
send_isr : out std_logic; --transmit done
address : out std_logic_vector(31 downto 2); --to DDR
byte_we : out std_logic_vector(3 downto 0);
data_write : out std_logic_vector(31 downto 0);
data_read : in std_logic_vector(31 downto 0);
pause_in : in std_logic;
mem_address : in std_logic_vector(31 downto 2); --from CPU
mem_byte_we : in std_logic_vector(3 downto 0);
data_w : in std_logic_vector(31 downto 0);
pause_out : out std_logic;
E_RX_CLK : in std_logic; --2.5 MHz receive
E_RX_DV : in std_logic; --data valid
E_RXD : in std_logic_vector(3 downto 0); --receive nibble
E_TX_CLK : in std_logic; --2.5 MHz transmit
E_TX_EN : out std_logic; --transmit enable
E_TXD : out std_logic_vector(3 downto 0)); --transmit nibble
end; --entity eth_dma
architecture logic of eth_dma is
signal rec_clk : std_logic_vector(1 downto 0); --receive
signal rec_store : std_logic_vector(31 downto 0); --to DDR
signal rec_data : std_logic_vector(27 downto 0);
signal rec_cnt : std_logic_vector(2 downto 0); --nibbles
signal rec_words : std_logic_vector(13 downto 0);
signal rec_dma : std_logic_vector(1 downto 0); --active & request
signal rec_done : std_logic;
signal send_clk : std_logic_vector(1 downto 0); --transmit
signal send_read : std_logic_vector(31 downto 0); --from DDR
signal send_data : std_logic_vector(31 downto 0);
signal send_cnt : std_logic_vector(2 downto 0); --nibbles
signal send_words : std_logic_vector(8 downto 0);
signal send_level : std_logic_vector(8 downto 0);
signal send_dma : std_logic_vector(1 downto 0); --active & request
signal send_enable: std_logic;
begin --architecture
dma_proc: process(clk, reset, enable_eth, select_eth,
data_read, pause_in, mem_address, mem_byte_we, data_w,
E_RX_CLK, E_RX_DV, E_RXD, E_TX_CLK,
rec_clk, rec_store, rec_data,
rec_cnt, rec_words, rec_dma, rec_done,
send_clk, send_read, send_data, send_cnt, send_words,
send_level, send_dma, send_enable)
begin
if reset = '1' then
rec_clk <= "00";
rec_cnt <= "000";
rec_words <= ZERO(13 downto 0);
rec_dma <= "00";
rec_done <= '0';
send_clk <= "00";
send_cnt <= "000";
send_words <= ZERO(8 downto 0);
send_level <= ZERO(8 downto 0);
send_dma <= "00";
send_enable <= '0';
elsif rising_edge(clk) then
--Receive nibble on low->high E_RX_CLK. Send to DDR every 32 bits.
rec_clk <= rec_clk(0) & E_RX_CLK;
if rec_clk = "01" and enable_eth = '1' then
if E_RX_DV = '1' or rec_cnt /= "000" then
if rec_cnt = "111" then
rec_store <= rec_data & E_RXD;
rec_dma(0) <= '1'; --request DMA
end if;
rec_data <= rec_data(23 downto 0) & E_RXD;
rec_cnt <= rec_cnt + 1;
end if;
end if;
--Set transmit count or clear receive interrupt
if select_eth = '1' then
if mem_byte_we /= "0000" then
send_cnt <= "000";
send_words <= ZERO(8 downto 0);
send_level <= data_w(8 downto 0);
send_dma(0) <= '1';
else
rec_done <= '0';
end if;
end if;
--Transmit nibble on low->high E_TX_CLK. Get 32 bits from DDR.
send_clk <= send_clk(0) & E_TX_CLK;
if send_clk = "01" then
if send_cnt = "111" then
if send_words /= send_level then
send_data <= send_read;
send_dma(0) <= '1';
send_enable <= '1';
else
send_enable <= '0';
end if;
else
send_data(31 downto 4) <= send_data(27 downto 0);
end if;
send_cnt <= send_cnt + 1;
end if;
--Pick which type of DMA operation: bit0 = request; bit1 = active
if pause_in = '0' then
if rec_dma(1) = '1' then
rec_dma <= "00"; --DMA done
rec_words <= rec_words + 1;
if E_RX_DV = '0' then
rec_done <= '1';
end if;
elsif send_dma(1) = '1' then
send_dma <= "00";
send_words <= send_words + 1;
send_read <= data_read;
elsif rec_dma(0) = '1' then
rec_dma(1) <= '1'; --start DMA
elsif send_dma(0) = '1' then
send_dma(1) <= '1'; --start DMA
end if;
end if;
end if; --rising_edge(clk)
E_TXD <= send_data(31 downto 28);
E_TX_EN <= send_enable;
rec_isr <= rec_done;
if send_words = send_level then
send_isr <= '1';
else
send_isr <= '0';
end if;
if rec_dma(1) = '1' then
address <= "0001001111111111" & rec_words; --0x13ff0000
byte_we <= "1111";
data_write <= rec_store;
pause_out <= '1'; --to CPU
elsif send_dma(1) = '1' then
address <= "000100111111111000000" & send_words; --0x13fe0000
byte_we <= "0000";
data_write <= data_w;
pause_out <= '1';
else
address <= mem_address; --Send request from CPU to DDR
byte_we <= mem_byte_we;
data_write <= data_w;
pause_out <= '0';
end if;
end process;
end; --architecture logic
|
---------------------------------------------------------------------
-- TITLE: Ethernet DMA
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 12/27/07
-- FILENAME: eth_dma.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Ethernet DMA (Direct Memory Access) controller.
-- Reads four bits and writes four bits from/to the Ethernet PHY each
-- 2.5 MHz clock cycle. Received data is DMAed starting at 0x13ff0000
-- transmit data is read from 0x13fd0000.
-- To send a packet write bytes/4 to Ethernet send register.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use work.mlite_pack.all;
entity eth_dma is port(
clk : in std_logic; --25 MHz
reset : in std_logic;
enable_eth : in std_logic; --enable receive DMA
select_eth : in std_logic;
rec_isr : out std_logic; --data received
send_isr : out std_logic; --transmit done
address : out std_logic_vector(31 downto 2); --to DDR
byte_we : out std_logic_vector(3 downto 0);
data_write : out std_logic_vector(31 downto 0);
data_read : in std_logic_vector(31 downto 0);
pause_in : in std_logic;
mem_address : in std_logic_vector(31 downto 2); --from CPU
mem_byte_we : in std_logic_vector(3 downto 0);
data_w : in std_logic_vector(31 downto 0);
pause_out : out std_logic;
E_RX_CLK : in std_logic; --2.5 MHz receive
E_RX_DV : in std_logic; --data valid
E_RXD : in std_logic_vector(3 downto 0); --receive nibble
E_TX_CLK : in std_logic; --2.5 MHz transmit
E_TX_EN : out std_logic; --transmit enable
E_TXD : out std_logic_vector(3 downto 0)); --transmit nibble
end; --entity eth_dma
architecture logic of eth_dma is
signal rec_clk : std_logic_vector(1 downto 0); --receive
signal rec_store : std_logic_vector(31 downto 0); --to DDR
signal rec_data : std_logic_vector(27 downto 0);
signal rec_cnt : std_logic_vector(2 downto 0); --nibbles
signal rec_words : std_logic_vector(13 downto 0);
signal rec_dma : std_logic_vector(1 downto 0); --active & request
signal rec_done : std_logic;
signal send_clk : std_logic_vector(1 downto 0); --transmit
signal send_read : std_logic_vector(31 downto 0); --from DDR
signal send_data : std_logic_vector(31 downto 0);
signal send_cnt : std_logic_vector(2 downto 0); --nibbles
signal send_words : std_logic_vector(8 downto 0);
signal send_level : std_logic_vector(8 downto 0);
signal send_dma : std_logic_vector(1 downto 0); --active & request
signal send_enable: std_logic;
begin --architecture
dma_proc: process(clk, reset, enable_eth, select_eth,
data_read, pause_in, mem_address, mem_byte_we, data_w,
E_RX_CLK, E_RX_DV, E_RXD, E_TX_CLK,
rec_clk, rec_store, rec_data,
rec_cnt, rec_words, rec_dma, rec_done,
send_clk, send_read, send_data, send_cnt, send_words,
send_level, send_dma, send_enable)
begin
if reset = '1' then
rec_clk <= "00";
rec_cnt <= "000";
rec_words <= ZERO(13 downto 0);
rec_dma <= "00";
rec_done <= '0';
send_clk <= "00";
send_cnt <= "000";
send_words <= ZERO(8 downto 0);
send_level <= ZERO(8 downto 0);
send_dma <= "00";
send_enable <= '0';
elsif rising_edge(clk) then
--Receive nibble on low->high E_RX_CLK. Send to DDR every 32 bits.
rec_clk <= rec_clk(0) & E_RX_CLK;
if rec_clk = "01" and enable_eth = '1' then
if E_RX_DV = '1' or rec_cnt /= "000" then
if rec_cnt = "111" then
rec_store <= rec_data & E_RXD;
rec_dma(0) <= '1'; --request DMA
end if;
rec_data <= rec_data(23 downto 0) & E_RXD;
rec_cnt <= rec_cnt + 1;
end if;
end if;
--Set transmit count or clear receive interrupt
if select_eth = '1' then
if mem_byte_we /= "0000" then
send_cnt <= "000";
send_words <= ZERO(8 downto 0);
send_level <= data_w(8 downto 0);
send_dma(0) <= '1';
else
rec_done <= '0';
end if;
end if;
--Transmit nibble on low->high E_TX_CLK. Get 32 bits from DDR.
send_clk <= send_clk(0) & E_TX_CLK;
if send_clk = "01" then
if send_cnt = "111" then
if send_words /= send_level then
send_data <= send_read;
send_dma(0) <= '1';
send_enable <= '1';
else
send_enable <= '0';
end if;
else
send_data(31 downto 4) <= send_data(27 downto 0);
end if;
send_cnt <= send_cnt + 1;
end if;
--Pick which type of DMA operation: bit0 = request; bit1 = active
if pause_in = '0' then
if rec_dma(1) = '1' then
rec_dma <= "00"; --DMA done
rec_words <= rec_words + 1;
if E_RX_DV = '0' then
rec_done <= '1';
end if;
elsif send_dma(1) = '1' then
send_dma <= "00";
send_words <= send_words + 1;
send_read <= data_read;
elsif rec_dma(0) = '1' then
rec_dma(1) <= '1'; --start DMA
elsif send_dma(0) = '1' then
send_dma(1) <= '1'; --start DMA
end if;
end if;
end if; --rising_edge(clk)
E_TXD <= send_data(31 downto 28);
E_TX_EN <= send_enable;
rec_isr <= rec_done;
if send_words = send_level then
send_isr <= '1';
else
send_isr <= '0';
end if;
if rec_dma(1) = '1' then
address <= "0001001111111111" & rec_words; --0x13ff0000
byte_we <= "1111";
data_write <= rec_store;
pause_out <= '1'; --to CPU
elsif send_dma(1) = '1' then
address <= "000100111111111000000" & send_words; --0x13fe0000
byte_we <= "0000";
data_write <= data_w;
pause_out <= '1';
else
address <= mem_address; --Send request from CPU to DDR
byte_we <= mem_byte_we;
data_write <= data_w;
pause_out <= '0';
end if;
end process;
end; --architecture logic
|
---------------------------------------------------------------------
-- TITLE: Ethernet DMA
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 12/27/07
-- FILENAME: eth_dma.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Ethernet DMA (Direct Memory Access) controller.
-- Reads four bits and writes four bits from/to the Ethernet PHY each
-- 2.5 MHz clock cycle. Received data is DMAed starting at 0x13ff0000
-- transmit data is read from 0x13fd0000.
-- To send a packet write bytes/4 to Ethernet send register.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use work.mlite_pack.all;
entity eth_dma is port(
clk : in std_logic; --25 MHz
reset : in std_logic;
enable_eth : in std_logic; --enable receive DMA
select_eth : in std_logic;
rec_isr : out std_logic; --data received
send_isr : out std_logic; --transmit done
address : out std_logic_vector(31 downto 2); --to DDR
byte_we : out std_logic_vector(3 downto 0);
data_write : out std_logic_vector(31 downto 0);
data_read : in std_logic_vector(31 downto 0);
pause_in : in std_logic;
mem_address : in std_logic_vector(31 downto 2); --from CPU
mem_byte_we : in std_logic_vector(3 downto 0);
data_w : in std_logic_vector(31 downto 0);
pause_out : out std_logic;
E_RX_CLK : in std_logic; --2.5 MHz receive
E_RX_DV : in std_logic; --data valid
E_RXD : in std_logic_vector(3 downto 0); --receive nibble
E_TX_CLK : in std_logic; --2.5 MHz transmit
E_TX_EN : out std_logic; --transmit enable
E_TXD : out std_logic_vector(3 downto 0)); --transmit nibble
end; --entity eth_dma
architecture logic of eth_dma is
signal rec_clk : std_logic_vector(1 downto 0); --receive
signal rec_store : std_logic_vector(31 downto 0); --to DDR
signal rec_data : std_logic_vector(27 downto 0);
signal rec_cnt : std_logic_vector(2 downto 0); --nibbles
signal rec_words : std_logic_vector(13 downto 0);
signal rec_dma : std_logic_vector(1 downto 0); --active & request
signal rec_done : std_logic;
signal send_clk : std_logic_vector(1 downto 0); --transmit
signal send_read : std_logic_vector(31 downto 0); --from DDR
signal send_data : std_logic_vector(31 downto 0);
signal send_cnt : std_logic_vector(2 downto 0); --nibbles
signal send_words : std_logic_vector(8 downto 0);
signal send_level : std_logic_vector(8 downto 0);
signal send_dma : std_logic_vector(1 downto 0); --active & request
signal send_enable: std_logic;
begin --architecture
dma_proc: process(clk, reset, enable_eth, select_eth,
data_read, pause_in, mem_address, mem_byte_we, data_w,
E_RX_CLK, E_RX_DV, E_RXD, E_TX_CLK,
rec_clk, rec_store, rec_data,
rec_cnt, rec_words, rec_dma, rec_done,
send_clk, send_read, send_data, send_cnt, send_words,
send_level, send_dma, send_enable)
begin
if reset = '1' then
rec_clk <= "00";
rec_cnt <= "000";
rec_words <= ZERO(13 downto 0);
rec_dma <= "00";
rec_done <= '0';
send_clk <= "00";
send_cnt <= "000";
send_words <= ZERO(8 downto 0);
send_level <= ZERO(8 downto 0);
send_dma <= "00";
send_enable <= '0';
elsif rising_edge(clk) then
--Receive nibble on low->high E_RX_CLK. Send to DDR every 32 bits.
rec_clk <= rec_clk(0) & E_RX_CLK;
if rec_clk = "01" and enable_eth = '1' then
if E_RX_DV = '1' or rec_cnt /= "000" then
if rec_cnt = "111" then
rec_store <= rec_data & E_RXD;
rec_dma(0) <= '1'; --request DMA
end if;
rec_data <= rec_data(23 downto 0) & E_RXD;
rec_cnt <= rec_cnt + 1;
end if;
end if;
--Set transmit count or clear receive interrupt
if select_eth = '1' then
if mem_byte_we /= "0000" then
send_cnt <= "000";
send_words <= ZERO(8 downto 0);
send_level <= data_w(8 downto 0);
send_dma(0) <= '1';
else
rec_done <= '0';
end if;
end if;
--Transmit nibble on low->high E_TX_CLK. Get 32 bits from DDR.
send_clk <= send_clk(0) & E_TX_CLK;
if send_clk = "01" then
if send_cnt = "111" then
if send_words /= send_level then
send_data <= send_read;
send_dma(0) <= '1';
send_enable <= '1';
else
send_enable <= '0';
end if;
else
send_data(31 downto 4) <= send_data(27 downto 0);
end if;
send_cnt <= send_cnt + 1;
end if;
--Pick which type of DMA operation: bit0 = request; bit1 = active
if pause_in = '0' then
if rec_dma(1) = '1' then
rec_dma <= "00"; --DMA done
rec_words <= rec_words + 1;
if E_RX_DV = '0' then
rec_done <= '1';
end if;
elsif send_dma(1) = '1' then
send_dma <= "00";
send_words <= send_words + 1;
send_read <= data_read;
elsif rec_dma(0) = '1' then
rec_dma(1) <= '1'; --start DMA
elsif send_dma(0) = '1' then
send_dma(1) <= '1'; --start DMA
end if;
end if;
end if; --rising_edge(clk)
E_TXD <= send_data(31 downto 28);
E_TX_EN <= send_enable;
rec_isr <= rec_done;
if send_words = send_level then
send_isr <= '1';
else
send_isr <= '0';
end if;
if rec_dma(1) = '1' then
address <= "0001001111111111" & rec_words; --0x13ff0000
byte_we <= "1111";
data_write <= rec_store;
pause_out <= '1'; --to CPU
elsif send_dma(1) = '1' then
address <= "000100111111111000000" & send_words; --0x13fe0000
byte_we <= "0000";
data_write <= data_w;
pause_out <= '1';
else
address <= mem_address; --Send request from CPU to DDR
byte_we <= mem_byte_we;
data_write <= data_w;
pause_out <= '0';
end if;
end process;
end; --architecture logic
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: syncram_2pbw
-- File: syncram_2pbw.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: syncronous 2-port ram with tech selection and 8-bit write
-- strobes
------------------------------------------------------------------------------
library ieee;
library techmap;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
use techmap.allmem.all;
library grlib;
use grlib.config.all;
use grlib.config_types.all;
use grlib.stdlib.all;
entity syncram_2pbw is
generic (tech : integer := 0; abits : integer := 6; dbits : integer := 8;
sepclk : integer := 0; wrfst : integer := 0; testen : integer := 0;
words : integer := 0; custombits : integer := 1);
port (
rclk : in std_ulogic;
renable : in std_logic_vector((dbits/8-1) downto 0);
raddress : in std_logic_vector((abits-1) downto 0);
dataout : out std_logic_vector((dbits-1) downto 0);
wclk : in std_ulogic;
write : in std_logic_vector((dbits/8-1) downto 0);
waddress : in std_logic_vector((abits-1) downto 0);
datain : in std_logic_vector((dbits-1) downto 0);
testin : in std_logic_vector(TESTIN_WIDTH-1 downto 0) := testin_none;
customclk: in std_ulogic := '0';
customin : in std_logic_vector((dbits/8)*custombits-1 downto 0) := (others => '0');
customout:out std_logic_vector((dbits/8)*custombits-1 downto 0));
end;
architecture rtl of syncram_2pbw is
constant nctrl : integer := abits*2 + 2 + 2*dbits/8;
signal dataoutx : std_logic_vector((dbits -1) downto 0);
signal databp, testdata : std_logic_vector((dbits -1) downto 0);
signal renable2 : std_logic_vector((dbits/8-1) downto 0);
constant SCANTESTBP : boolean := (testen = 1) and (tech /= 0) and (tech /= ut90);
constant iwrfst : integer := (1-syncram_2p_write_through(tech)) * wrfst;
signal xrenable,xwrite : std_logic_vector(dbits/8-1 downto 0);
signal custominx,customoutx: std_logic_vector(syncram_customif_maxwidth downto 0);
begin
xrenable <= renable when testen=0 or testin(TESTIN_WIDTH-2)='0' else (others => '0');
xwrite <= write when testen=0 or testin(TESTIN_WIDTH-2)='0' else (others => '0');
s2pbw : if has_sram_2pbw(tech) = 1 generate
no_wrfst : if iwrfst = 0 generate
scanbp : if SCANTESTBP generate
comb : process (waddress, raddress, datain, renable, write, testin)
variable tmp : std_logic_vector((dbits -1) downto 0);
variable ctrlsigs : std_logic_vector((nctrl -1) downto 0);
begin
ctrlsigs := testin(1 downto 0) & write & renable & raddress & waddress;
tmp := datain;
for i in 0 to nctrl-1 loop
tmp(i mod dbits) := tmp(i mod dbits) xor ctrlsigs(i);
end loop;
testdata <= tmp;
end process;
reg : process(wclk) begin
if rising_edge(wclk) then databp <= testdata; end if;
end process;
dmuxout : for i in 0 to dbits-1 generate
x0 : grmux2 generic map (tech)
port map (dataoutx(i), databp(i), testin(3), dataout(i));
end generate;
end generate;
noscanbp : if not SCANTESTBP generate dataout <= dataoutx; end generate;
-- Write contention check (if applicable)
wcheck : for i in 0 to dbits/8-1 generate
renable2(i) <= '0' when ((sepclk = 0 and syncram_2p_dest_rw_collision(tech) = 1) and
(renable(i) and write(i)) = '1' and raddress = waddress) else renable(i);
end generate;
end generate;
wrfst_gen : if iwrfst = 1 generate
-- No risk for read/write contention. Register addresses and mux on comparator
no_contention_check : if syncram_2p_dest_rw_collision(tech) = 0 generate
wfrstblocknoc : block
type wrfst_type is record
raddr : std_logic_vector((abits-1) downto 0);
waddr : std_logic_vector((abits-1) downto 0);
datain : std_logic_vector((dbits-1) downto 0);
write : std_logic_vector((dbits/8-1) downto 0);
renable : std_logic_vector((dbits/8-1) downto 0);
end record;
signal r : wrfst_type;
begin
comb : process(r, dataoutx, testin) begin
for i in 0 to dbits/8-1 loop
if (SCANTESTBP and (testin(3) = '1')) or
(((r.write(i) and r.renable(i)) = '1') and (r.raddr = r.waddr)) then
dataout(i*8+7 downto i*8) <= r.datain(i*8+7 downto i*8);
else dataout(i*8+7 downto i*8) <= dataoutx(i*8+7 downto i*8); end if;
end loop;
end process;
reg : process(wclk) begin
if rising_edge(wclk) then
r.raddr <= raddress; r.waddr <= waddress;
r.datain <= datain; r.write <= write;
r.renable <= renable;
end if;
end process;
end block wfrstblocknoc;
renable2 <= renable;
end generate;
-- Risk of read/write contention. Use same comparator to gate read enable
-- and mux data.
contention_safe : if syncram_2p_dest_rw_collision(tech) /= 0 generate
wfrstblockc : block
signal col, mux : std_logic_vector((dbits/8-1) downto 0);
signal rdatain : std_logic_vector((dbits-1) downto 0);
begin
comb : process(mux, renable, write, raddress, waddress, rdatain,
dataoutx, testin)
begin
for i in 0 to dbits/8-1 loop
col(i) <= '0'; renable2(i) <= renable(i);
if (write(i) and renable(i)) = '1' and raddress = waddress then
col(i) <= '1'; renable2(i) <= '0';
end if;
if (SCANTESTBP and (testin(3) = '1')) or mux(i) = '1' then
dataout(i*8+7 downto i*8) <= rdatain(i*8+7 downto i*8);
else dataout(i*8+7 downto i*8) <= dataoutx(i*8+7 downto i*8); end if;
end loop;
end process;
reg : process(wclk) begin
if rising_edge(wclk) then
rdatain <= datain; mux <= col;
end if;
end process;
end block wfrstblockc;
end generate;
end generate wrfst_gen;
custominx(custominx'high downto custombits) <= (others => '0');
custominx(custombits-1 downto 0) <= customin;
nocust: if has_sram_2pbw(tech)=0 or syncram_has_customif(tech)=0 generate
customoutx <= (others => '0');
end generate;
co0: if has_sram_2pbw(tech)=1 generate
customout(custombits-1 downto 0) <= customoutx(custombits-1 downto 0);
customout(customout'high downto custombits) <= (others => '0');
end generate;
n2x : if tech = easic45 generate
x0 : n2x_syncram_2p_be generic map (abits, dbits, sepclk, iwrfst)
port map (rclk, renable2, raddress, dataoutx, wclk,
write, waddress, datain);
end generate;
-- pragma translate_off
noram : if has_2pram(tech) = 0 generate
x : process
begin
assert false report "synram_2pbw: technology " & tech_table(tech) &
" not supported"
severity failure;
wait;
end process;
end generate;
dmsg : if GRLIB_CONFIG_ARRAY(grlib_debug_level) >= 2 generate
x : process
begin
assert false report "syncram_2pbw: " & tost(2**abits) & "x" & tost(dbits) &
" (" & tech_table(tech) & ")"
severity note;
wait;
end process;
end generate;
generic_check : process
begin
assert sepclk = 0 or wrfst = 0
report "syncram_2pbw: Write-first not supported for RAM with separate clocks"
severity failure;
wait;
end process;
-- pragma translate_on
end generate;
nos2pbw : if has_sram_2pbw(tech) /= 1 generate
rx : for i in 0 to dbits/8-1 generate
x0 : syncram_2p generic map (tech, abits, 8, sepclk, wrfst, testen, words, custombits)
port map (rclk, renable(i), raddress, dataout(i*8+7 downto i*8), wclk, write(i),
waddress, datain(i*8+7 downto i*8), testin,
customclk, customin((i+1)*custombits-1 downto i*custombits),
customout((i+1)*custombits-1 downto i*custombits));
end generate;
end generate;
end;
|
-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.3.1 (lin64) Build 2035080 Fri Oct 20 14:20:00 MDT 2017
-- Date : Fri Mar 9 12:16:02 2018
-- Host : hwreg2.conveycomputer.com running 64-bit CentOS release 6.7 (Final)
-- Command : write_vhdl -force -mode synth_stub
-- /netscratch/cbaronne/WX2_UIO_PRBS/DAY9/uvpt_100REF_25G_initclk/ip/aurora_64b66b_25p4G/aurora_64b66b_25p4G_stub.vhdl
-- Design : aurora_64b66b_25p4G
-- Purpose : Stub declaration of top-level module interface
-- Device : xcvu7p-flvb2104-2L-e
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity aurora_64b66b_25p4G is
Port (
s_axi_tx_tdata : in STD_LOGIC_VECTOR ( 0 to 63 );
s_axi_tx_tlast : in STD_LOGIC;
s_axi_tx_tkeep : in STD_LOGIC_VECTOR ( 0 to 7 );
s_axi_tx_tvalid : in STD_LOGIC;
s_axi_tx_tready : out STD_LOGIC;
m_axi_rx_tdata : out STD_LOGIC_VECTOR ( 0 to 63 );
m_axi_rx_tlast : out STD_LOGIC;
m_axi_rx_tkeep : out STD_LOGIC_VECTOR ( 0 to 7 );
m_axi_rx_tvalid : out STD_LOGIC;
rxp : in STD_LOGIC_VECTOR ( 0 to 0 );
rxn : in STD_LOGIC_VECTOR ( 0 to 0 );
txp : out STD_LOGIC_VECTOR ( 0 to 0 );
txn : out STD_LOGIC_VECTOR ( 0 to 0 );
refclk1_in : in STD_LOGIC;
hard_err : out STD_LOGIC;
soft_err : out STD_LOGIC;
channel_up : out STD_LOGIC;
lane_up : out STD_LOGIC_VECTOR ( 0 to 0 );
mmcm_not_locked : in STD_LOGIC;
user_clk : in STD_LOGIC;
sync_clk : in STD_LOGIC;
reset_pb : in STD_LOGIC;
gt_rxcdrovrden_in : in STD_LOGIC;
power_down : in STD_LOGIC;
loopback : in STD_LOGIC_VECTOR ( 2 downto 0 );
pma_init : in STD_LOGIC;
gt_pll_lock : out STD_LOGIC;
gt_qpllclk_quad1_in : in STD_LOGIC;
gt_qpllrefclk_quad1_in : in STD_LOGIC;
gt_qplllock_quad1_in : in STD_LOGIC;
gt_qpllrefclklost_quad1 : in STD_LOGIC;
gt_to_common_qpllreset_out : out STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bvalid : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rready : in STD_LOGIC;
init_clk : in STD_LOGIC;
link_reset_out : out STD_LOGIC;
gt_powergood : out STD_LOGIC_VECTOR ( 0 to 0 );
sys_reset_out : out STD_LOGIC;
bufg_gt_clr_out : out STD_LOGIC;
tx_out_clk : out STD_LOGIC
);
end aurora_64b66b_25p4G;
architecture stub of aurora_64b66b_25p4G is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "s_axi_tx_tdata[0:63],s_axi_tx_tlast,s_axi_tx_tkeep[0:7],s_axi_tx_tvalid,s_axi_tx_tready,m_axi_rx_tdata[0:63],m_axi_rx_tlast,m_axi_rx_tkeep[0:7],m_axi_rx_tvalid,rxp[0:0],rxn[0:0],txp[0:0],txn[0:0],refclk1_in,hard_err,soft_err,channel_up,lane_up[0:0],mmcm_not_locked,user_clk,sync_clk,reset_pb,gt_rxcdrovrden_in,power_down,loopback[2:0],pma_init,gt_pll_lock,gt_qpllclk_quad1_in,gt_qpllrefclk_quad1_in,gt_qplllock_quad1_in,gt_qpllrefclklost_quad1,gt_to_common_qpllreset_out,s_axi_awaddr[31:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wvalid,s_axi_wready,s_axi_bvalid,s_axi_bresp[1:0],s_axi_bready,s_axi_araddr[31:0],s_axi_arvalid,s_axi_arready,s_axi_rdata[31:0],s_axi_rvalid,s_axi_rresp[1:0],s_axi_rready,init_clk,link_reset_out,gt_powergood[0:0],sys_reset_out,bufg_gt_clr_out,tx_out_clk";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of stub : architecture is "aurora_64b66b_v11_2_2, Coregen v14.3_ip3, Number of lanes = 1, Line rate is double25.4Gbps, Reference Clock is double100.0MHz, Interface is Framing, Flow Control is None and is operating in DUPLEX configuration";
begin
end;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 28.08.2016 18:42:39
-- Design Name:
-- Module Name: states_tb - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library SlowWorm;
use SlowWorm.SlowWorm.ALL;
entity states_tb is
end states_tb;
architecture Behavioral of states_tb is
signal clk : std_ulogic;
signal inst_mem_data : data_t;
signal inst_mem_addr : addr_t;
signal data_mem_we : std_ulogic;
signal rstack_push : std_ulogic;
signal rstack_pop : std_ulogic;
signal dstack_push : std_ulogic;
signal dstack_pop : std_ulogic;
constant ClockPeriod : TIME := 50 ns;
constant NOP : data_t := "0000000000000001";
begin
control: entity work.control port map (
clk => clk,
inst_mem_data => inst_mem_data,
inst_mem_addr => inst_mem_addr,
data_mem_we => data_mem_we,
dstack_push => dstack_push,
dstack_pop => dstack_pop,
rstack_push => rstack_push,
rstack_pop => rstack_pop,
-- Unused.
rstack_data_read => UNK_DATA,
data_mem_data_read => UNK_DATA,
dstack_data_read => UNK_DATA
);
clock: process begin
clk <= '0';
wait for ClockPeriod;
loop
clk <= not clk;
wait for (ClockPeriod / 2);
end loop;
end process;
stimulus: process begin
-- Starting values.
inst_mem_data <= NOP;
wait until falling_edge(clk);
-- Should see PC and inst_mem_addr incrementing, states cycling.
-- Do nothing more.
wait;
end process;
end Behavioral;
|
-- $Id: ibdr_pc11.vhd 427 2011-11-19 21:04:11Z mueller $
--
-- Copyright 2009-2011 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: ibdr_pc11 - syn
-- Description: ibus dev(rem): PC11
--
-- Dependencies: -
-- Test bench: xxdp: zpcae0
-- Target Devices: generic
-- Tool versions: xst 8.2, 9.1, 9.2, 12.1, 13.1; ghdl 0.18-0.29
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2010-10-17 333 12.1 M53d xc3s1000-4 26 97 0 57 s 6.0
-- 2009-06-28 230 10.1.03 K39 xc3s1000-4 25 92 0 54 s 4.9
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-18 427 1.2.2 now numeric_std clean
-- 2010-10-23 335 1.2.1 rename RRI_LAM->RB_LAM;
-- 2010-10-17 333 1.2 use ibus V2 interface
-- 2010-06-11 303 1.1 use IB_MREQ.racc instead of RRI_REQ
-- 2009-06-28 230 1.0 prdy now inits to '1'; setting err bit in csr now
-- causes interrupt, if enabled; validated with zpcae0
-- 2009-06-01 221 0.9 Initial version (untested)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.iblib.all;
-- ----------------------------------------------------------------------------
entity ibdr_pc11 is -- ibus dev(rem): PC11
-- fixed address: 177550
port (
CLK : in slbit; -- clock
RESET : in slbit; -- system reset
BRESET : in slbit; -- ibus reset
RB_LAM : out slbit; -- remote attention
IB_MREQ : in ib_mreq_type; -- ibus request
IB_SRES : out ib_sres_type; -- ibus response
EI_REQ_PTR : out slbit; -- interrupt request, reader
EI_REQ_PTP : out slbit; -- interrupt request, punch
EI_ACK_PTR : in slbit; -- interrupt acknowledge, reader
EI_ACK_PTP : in slbit -- interrupt acknowledge, punch
);
end ibdr_pc11;
architecture syn of ibdr_pc11 is
constant ibaddr_pc11 : slv16 := slv(to_unsigned(8#177550#,16));
constant ibaddr_rcsr : slv2 := "00"; -- rcsr address offset
constant ibaddr_rbuf : slv2 := "01"; -- rbuf address offset
constant ibaddr_pcsr : slv2 := "10"; -- pcsr address offset
constant ibaddr_pbuf : slv2 := "11"; -- pbuf address offset
constant rcsr_ibf_rerr : integer := 15;
constant rcsr_ibf_rbusy : integer := 11;
constant rcsr_ibf_rdone : integer := 7;
constant rcsr_ibf_rie : integer := 6;
constant rcsr_ibf_renb : integer := 0;
constant pcsr_ibf_perr : integer := 15;
constant pcsr_ibf_prdy : integer := 7;
constant pcsr_ibf_pie : integer := 6;
constant pbuf_ibf_pval : integer := 8;
constant pbuf_ibf_rbusy : integer := 9;
type regs_type is record -- state registers
ibsel : slbit; -- ibus select
rerr : slbit; -- rcsr: reader error
rbusy : slbit; -- rcsr: reader busy
rdone : slbit; -- rcsr: reader done
rie : slbit; -- rcsr: reader interrupt enable
rbuf : slv8; -- rbuf:
rintreq : slbit; -- ptr interrupt request
perr : slbit; -- pcsr: punch error
prdy : slbit; -- pcsr: punch ready
pie : slbit; -- pcsr: punch interrupt enable
pbuf : slv8; -- pbuf:
pintreq : slbit; -- ptp interrupt request
end record regs_type;
constant regs_init : regs_type := (
'0', -- ibsel
'1', -- rerr (init=1!)
'0','0','0', -- rbusy,rdone,rie
(others=>'0'), -- rbuf
'0', -- rintreq
'1', -- perr (init=1!)
'1', -- prdy (init=1!)
'0', -- pie
(others=>'0'), -- pbuf
'0' -- pintreq
);
signal R_REGS : regs_type := regs_init;
signal N_REGS : regs_type := regs_init;
begin
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if BRESET = '1' then -- BRESET is 1 for system and ibus reset
R_REGS <= regs_init; --
if RESET = '0' then -- if RESET=0 we do just an ibus reset
R_REGS.rerr <= N_REGS.rerr; -- don't reset RERR flag
R_REGS.perr <= N_REGS.perr; -- don't reset PERR flag
end if;
else
R_REGS <= N_REGS;
end if;
end if;
end process proc_regs;
proc_next : process (R_REGS, IB_MREQ, EI_ACK_PTR, EI_ACK_PTP)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
variable idout : slv16 := (others=>'0');
variable ibreq : slbit := '0';
variable ibrd : slbit := '0';
variable ibw0 : slbit := '0';
variable ibw1 : slbit := '0';
variable ilam : slbit := '0';
begin
r := R_REGS;
n := R_REGS;
idout := (others=>'0');
ibreq := IB_MREQ.re or IB_MREQ.we;
ibrd := IB_MREQ.re;
ibw0 := IB_MREQ.we and IB_MREQ.be0;
ibw1 := IB_MREQ.we and IB_MREQ.be1;
ilam := '0';
-- ibus address decoder
n.ibsel := '0';
if IB_MREQ.aval='1' and
IB_MREQ.addr(12 downto 3)=ibaddr_pc11(12 downto 3) then
n.ibsel := '1';
end if;
-- ibus transactions
if r.ibsel = '1' then
case IB_MREQ.addr(2 downto 1) is
when ibaddr_rcsr => -- RCSR -- reader control status -----
idout(rcsr_ibf_rerr) := r.rerr;
idout(rcsr_ibf_rbusy) := r.rbusy;
idout(rcsr_ibf_rdone) := r.rdone;
idout(rcsr_ibf_rie) := r.rie;
if IB_MREQ.racc = '0' then -- cpu ---------------------
if ibw0 = '1' then
n.rie := IB_MREQ.din(rcsr_ibf_rie);
if IB_MREQ.din(rcsr_ibf_rie) = '1' then-- set IE to 1
if r.rie = '0' and -- IE 0->1 transition
IB_MREQ.din(rcsr_ibf_renb)='0' and -- when RENB not set
(r.rerr='1' or r.rdone='1') then -- but err or done set
n.rintreq := '1'; -- request interrupt
end if;
else -- set IE to 0
n.rintreq := '0'; -- cancel interrupts
end if;
if IB_MREQ.din(rcsr_ibf_renb) = '1' then -- set RENB
if r.rerr = '0' then -- if not in error state
n.rbusy := '1'; -- set busy
n.rdone := '0'; -- clear done
n.rbuf := (others=>'0'); -- clear buffer
n.rintreq := '0'; -- cancel interrupt
ilam := '1'; -- rri lam
else -- if in error state
if r.rie = '1' then -- if interrupts on
n.rintreq := '1'; -- request interrupt
end if;
end if;
end if;
end if;
else -- rri ---------------------
if ibw1 = '1' then
n.rerr := IB_MREQ.din(rcsr_ibf_rerr); -- set ERR bit
if IB_MREQ.din(rcsr_ibf_rerr)='1' -- if 0->1 transition
and r.rerr='0' then
n.rbusy := '0'; -- clear busy
n.rdone := '0'; -- clear done
if r.rie = '1' then -- if interrupts on
n.rintreq := '1'; -- request interrupt
end if;
end if;
end if;
end if;
when ibaddr_rbuf => -- RBUF -- reader data buffer --------
idout(r.rbuf'range) := r.rbuf;
if IB_MREQ.racc = '0' then -- cpu ---------------------
if true then -- !! PC11 is unusual !!
n.rdone := '0'; -- any read or write will clear done
n.rbuf := (others=>'0'); -- and the reader buffer
n.rintreq := '0'; -- also interrupt is canceled
end if;
else -- rri ---------------------
if ibw0 = '1' then
n.rbuf := IB_MREQ.din(n.rbuf'range);
n.rbusy := '0';
n.rdone := '1';
if r.rie = '1' then
n.rintreq := '1';
end if;
end if;
end if;
when ibaddr_pcsr => -- PCSR -- punch control status ------
idout(pcsr_ibf_perr) := r.perr;
idout(pcsr_ibf_prdy) := r.prdy;
idout(pcsr_ibf_pie) := r.pie;
if IB_MREQ.racc = '0' then -- cpu ---------------------
if ibw0 = '1' then
n.pie := IB_MREQ.din(pcsr_ibf_pie);
if IB_MREQ.din(pcsr_ibf_pie) = '1' then-- set IE to 1
if r.pie='0' and -- IE 0->1 transition
(r.perr='1' or r.prdy='1') then -- but err or done set
n.pintreq := '1'; -- request interrupt
end if;
else -- set IE to 0
n.pintreq := '0'; -- cancel interrupts
end if;
end if;
else -- rri ---------------------
if ibw1 = '1' then
n.perr := IB_MREQ.din(pcsr_ibf_perr); -- set ERR bit
if IB_MREQ.din(pcsr_ibf_perr)='1' -- if 0->1 transition
and r.perr='0' then
n.prdy := '1'; -- set ready
if r.pie = '1' then -- if interrupts on
n.pintreq := '1'; -- request interrupt
end if;
end if;
end if;
end if;
when ibaddr_pbuf => -- PBUF -- punch data buffer ---------
if IB_MREQ.racc = '0' then -- cpu ---------------------
if ibw0 = '1' then
if r.perr = '0' then -- if not in error state
n.pbuf := IB_MREQ.din(n.pbuf'range);
n.prdy := '0'; -- clear ready
n.pintreq := '0'; -- cancel interrupts
ilam := '1'; -- rri lam
else -- if in error state
if r.pie = '1' then -- if interrupts on
n.pintreq := '1'; -- request interrupt
end if;
end if;
end if;
else -- rri ---------------------
idout(r.pbuf'range) := r.pbuf;
idout(pbuf_ibf_pval) := not r.prdy;
idout(pbuf_ibf_rbusy) := r.rbusy;
if ibrd = '1' then
n.prdy := '1';
if r.pie = '1' then
n.pintreq := '1';
end if;
end if;
end if;
when others => null;
end case;
end if;
-- other state changes
if EI_ACK_PTR = '1' then
n.rintreq := '0';
end if;
if EI_ACK_PTP = '1' then
n.pintreq := '0';
end if;
N_REGS <= n;
IB_SRES.dout <= idout;
IB_SRES.ack <= r.ibsel and ibreq;
IB_SRES.busy <= '0';
RB_LAM <= ilam;
EI_REQ_PTR <= r.rintreq;
EI_REQ_PTP <= r.pintreq;
end process proc_next;
end syn;
|
--------------------------------------------------------------------------------
-- UART
-- Implements a universal asynchronous receiver transmitter with parameterisable
-- BAUD rate. Tested on a Spartan 6 LX9 connected to a Silicon Labs Cp210
-- USB-UART Bridge.
--
-- @author Peter A Bennett
-- @copyright (c) 2012 Peter A Bennett
-- @license LGPL
-- @email [email protected]
-- @contact www.bytebash.com
--
-- Extended by
-- @author Robert Lange
-- @copyright (c) 2013 Robert Lange
-- @license LGPL
-- @home https://github.com/sd2k9/
--
-- Modified by
-- @author Kevin Johnson
-- @license LGPL
-- @email [email protected]
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- Math log2,ceil required to get the number of bits for our counter
use ieee.math_real.log2;
use ieee.math_real.ceil;
entity UART is
Generic (
-- Baudrate in bps
-- The baudrate must satisify the following condition:
-- BAUD_DIVIDER := truncate(CLOCK_FREQUENCY/BAUD_RATE)
-- remainder(BAUD_DIVIDER/16) == 0
-- Why: 16 times oversampling on the receiver side
-- Also take care that the remainder(CLOCK_FREQUENCY/BAUD_RATE) is
-- small because this determines the UART baud rate error
-- See constant c_oversample_divider_val for more information
BAUD_RATE : positive := 9600;
-- Input Clock frequency in Hz
-- Actual clock for SCOMP version is 14.72MHz, but we tell the UART
-- 14.7456MHz to make the divider calculations work out. This creates
-- a 0.13% error, which is well within the acceptable range.
CLOCK_FREQUENCY : positive := 14745600
);
Port (
-- System Clock
CLOCK : in std_logic;
-- High-Active Asynchronous Reset
RESET : in std_logic;
-- The input data: 8 bit - this is the UART sender
-- Provide data on DATA_STREAM_IN and set STB to high
-- Keep the data stable until ACK is set to high which shows that
-- the data is copied into the internal buffer. Then you should
-- revoke STB and you can change IN as you want.
DATA_STREAM_IN : in std_logic_vector(7 downto 0);
DATA_STREAM_IN_STB : in std_logic;
DATA_STREAM_IN_ACK : out std_logic := '0';
-- The output data: 8 bit - this is the UART receiver
-- Data is only valid during the time the STB is high
-- Acknowledge the data with a pulse on ACK, which is confirmed by
-- revoking STB.
-- When the following start bit is received the data becomes
-- invalid and the STB is revoked. So take care about fetching the
-- data early enough, or install your own FIFO buffer
DATA_STREAM_OUT : out std_logic_vector(7 downto 0);
DATA_STREAM_OUT_STB : out std_logic;
DATA_STREAM_OUT_ACK : in std_logic;
TX : out std_logic;
RX : in std_logic -- Async Receive
);
end UART;
architecture RTL of UART is
----------------------------------------------------------------------------
-- BAUD Generation
----------------------------------------------------------------------------
-- First create the divider for the 16 times oversampled baud rate,
-- the baud rate then is derived by dividing by 16.
-- Thats why the 16 times oversampling clock must be derived without any reminder left
-- from the baud rate, to not disturb the resulting bit rate
-- You need to take care about this when selecting baud and clock frequency
-- Substract one, otherwise the reloading step is counted twice
constant c_oversample_divider_steps : natural := natural(CLOCK_FREQUENCY / (16*BAUD_RATE))-1;
-- And also how many bits do we need?
constant c_oversample_divider_bits : natural := natural(ceil(log2(real(c_oversample_divider_steps))));
-- And this is the counter type we use
subtype oversample_baud_counter_type is unsigned(c_oversample_divider_bits-1 downto 0);
-- Please only use this final value
constant c_oversample_divider_val : oversample_baud_counter_type := to_unsigned(c_oversample_divider_steps, c_oversample_divider_bits);
-- Datatype for the rx and tx counter type, must accomodate for the 8bit positions
subtype uart_rxtx_count_type is unsigned(2 downto 0);
constant c_uart_rxtx_count_reset : uart_rxtx_count_type := "000"; -- Reset value: 0
signal oversample_baud_counter : oversample_baud_counter_type := c_oversample_divider_val;
-- Tick created every counter reset
signal oversample_baud_tick : std_ulogic := '0';
-- At this moment we sample the incoming signal
signal uart_rx_sample_tick : std_ulogic := '0';
-- The baud rate itself is the oversampling tick divided by 16
subtype baud_counter_type is unsigned(3 downto 0);
signal baud_counter : baud_counter_type := ( others => '1');
signal baud_tick : std_ulogic := '0';
----------------------------------------------------------------------------
-- Transmitter Signals
----------------------------------------------------------------------------
type uart_tx_states is ( idle,
wait_for_tick,
send_start_bit,
transmit_data,
send_stop_bit);
signal uart_tx_state : uart_tx_states := idle;
signal uart_tx_data_block : std_logic_vector(7 downto 0) := (others => '0');
signal uart_tx_data : std_logic := '1';
signal uart_tx_count : uart_rxtx_count_type := c_uart_rxtx_count_reset; -- 8 states, stored in 3 bits
signal uart_rx_data_in_ack : std_logic := '0';
----------------------------------------------------------------------------
-- Receiver Signals
----------------------------------------------------------------------------
type uart_rx_states is ( rx_wait_start_synchronise -- Wait and deliver data
, rx_get_start_bit -- We are reading the start bit
, rx_get_data
, rx_get_stop_bit
);
signal uart_rx_state : uart_rx_states := rx_wait_start_synchronise;
signal uart_rx_bit : std_logic := '0';
signal uart_rx_data_block : std_logic_vector(7 downto 0) := (others => '0');
signal uart_rx_filter : unsigned(1 downto 0) := (others => '0');
signal uart_rx_count : uart_rxtx_count_type := c_uart_rxtx_count_reset; -- 8 states, stored in 3 bits
signal uart_rx_data_out_stb: std_ulogic := '0';
-- Syncing Clock to Receive Data, compared to baud_counter and creates uart_rx_sample_tick
signal uart_rx_sync_clock : baud_counter_type := (others => '0');
----------------------------------------------------------------------------
-- Helper functions
----------------------------------------------------------------------------
pure function shift_right_by_one ( -- Shift right by 1, fill with new bit
constant shift : in std_logic_vector(7 downto 0); -- Signal to shift
constant fill : in std_ulogic) -- New bit 7
return std_logic_vector is
variable ret : std_logic_vector(7 downto 0);
begin -- function shift_right_by_one
ret(7) := fill;
ret(6 downto 0) := shift (7 downto 1);
return ret;
end function shift_right_by_one;
----------------------------------------------------------------------------
-- Begin Body
----------------------------------------------------------------------------
begin
----------------------------------------------------------------------------
-- Transmitter Part: Sending Data
----------------------------------------------------------------------------
TX <= uart_tx_data;
-- The input clock is CLOCK_FREQUENCY
-- For example its set to 100Mhz, then needs to be divided down to the
-- rate dictated by the BAUD_RATE. For example, if 115200 baud is selected
-- (115200 baud = 115200 bps - 115.2kbps) a tick must be generated once
-- every 1/115200
-- As explained above we use a two-step approach, so we just scale down
-- here the 16-times oversampled RX clock again
-- Use a down-counter to have a simple test for zero
-- Thats the counter part
TX_CLOCK_DIVIDER : process (CLOCK, RESET)
begin
if RESET = '1' then
baud_counter <= (others => '1');
elsif rising_edge (CLOCK) then
if oversample_baud_tick = '1' then -- Use as Clock enable
if baud_counter = 0 then
baud_counter <= (others => '1');
else
baud_counter <= baud_counter - 1;
end if;
end if;
end if;
end process TX_CLOCK_DIVIDER;
-- And thats the baud tick, which is of course only one clock long
-- So both counters should be Zero
TX_TICK: baud_tick <= '0' when RESET = '1' else
'1' when oversample_baud_tick = '1' and baud_counter = 0 else
'0';
-- Get data from DATA_STREAM_IN and send it one bit at a time
-- upon each BAUD tick. LSB first.
-- Wait 1 tick, Send Start Bit (0), Send Data 0-7, Send Stop Bit (1)
UART_SEND_DATA : process(CLOCK, RESET)
begin
if RESET = '1' then
uart_tx_data <= '1';
uart_tx_data_block <= (others => '0');
uart_tx_count <= c_uart_rxtx_count_reset;
uart_tx_state <= idle;
uart_rx_data_in_ack <= '0';
elsif rising_edge(CLOCK) then
uart_rx_data_in_ack <= '0';
case uart_tx_state is
when idle =>
if DATA_STREAM_IN_STB = '1' then
uart_tx_data_block <= DATA_STREAM_IN;
uart_rx_data_in_ack <= '1';
uart_tx_state <= wait_for_tick;
end if;
when wait_for_tick =>
if baud_tick = '1' then
uart_tx_state <= send_start_bit;
end if;
when send_start_bit =>
if baud_tick = '1' then
uart_tx_data <= '0';
uart_tx_state <= transmit_data;
end if;
when transmit_data =>
if baud_tick = '1' then
-- Send next bit
uart_tx_data <= uart_tx_data_block(0);
-- Shift for next transmit bit, filling with don't care
-- Xilinx ISE does not know srl? So just build it ourself, hehe
-- uart_tx_data_block <= uart_tx_data_block srl 1;
uart_tx_data_block <= shift_right_by_one(uart_tx_data_block, '-');
if uart_tx_count = 7 then -- binary 111
-- We're done, move to next state
uart_tx_state <= send_stop_bit;
else
-- Stay in current state
uart_tx_state <= transmit_data;
end if;
-- Always increment here, will go to zero if we're out
uart_tx_count <= uart_tx_count + 1;
end if;
when send_stop_bit =>
if baud_tick = '1' then
uart_tx_data <= '1';
uart_tx_state <= idle;
end if;
when others =>
uart_tx_data <= '1';
uart_tx_state <= idle;
end case;
end if;
end process UART_SEND_DATA;
----------------------------------------------------------------------------
-- Receiver Part: Getting Data
----------------------------------------------------------------------------
DATA_STREAM_IN_ACK <= uart_rx_data_in_ack;
DATA_STREAM_OUT <= uart_rx_data_block;
DATA_STREAM_OUT_STB <= uart_rx_data_out_stb;
-- The RX clock divider uses the 16 times oversampled clock, which we
-- create here from the input clock
-- Use a down-counter to have a simple test for zero
-- Thats for the counter and tick creation part
RX_CLOCK_DIVIDER : process (CLOCK, RESET)
begin
if RESET = '1' then
oversample_baud_counter <= c_oversample_divider_val;
oversample_baud_tick <= '0';
elsif rising_edge (CLOCK) then
if oversample_baud_counter = 0 then
oversample_baud_counter <= c_oversample_divider_val;
oversample_baud_tick <= '1';
else
oversample_baud_counter <= oversample_baud_counter - 1;
oversample_baud_tick <= '0';
end if;
end if;
end process RX_CLOCK_DIVIDER;
-- We create the sample time by syncing the oversampled tick (BAUD * 16)
-- to the received start bit by comparing then vs. the stored receive sync value
-- It's only one clock tick active
RX_SAMPLE: uart_rx_sample_tick <= '0' when RESET = '1' else
'1' when oversample_baud_tick = '1' and uart_rx_sync_clock = baud_counter else
'0';
-- Synchronise RXD and Filter to suppress spikes with a 2 bit counter
-- This is done with the 16-times oversampled clock
-- Take care, every time the receive clock is resynchronized to the next
-- start bit we can have somewhat of a jump here. But thats no problem
-- because the jump (in case it occur) is still synchronous. And we save us
-- another counter :-)
RXD_SYNC_FILTER : process(CLOCK, RESET)
begin
if RESET = '1' then
uart_rx_filter <= (others => '1');
uart_rx_bit <= '1';
elsif rising_edge(CLOCK) then
if oversample_baud_tick = '1' then
-- Filter RXD.
if RX = '1' and uart_rx_filter < 3 then
uart_rx_filter <= uart_rx_filter + 1;
elsif RX = '0' and uart_rx_filter > 0 then
uart_rx_filter <= uart_rx_filter - 1;
end if;
-- Set the RX bit.
if uart_rx_filter = 3 then
uart_rx_bit <= '1';
elsif uart_rx_filter = 0 then
uart_rx_bit <= '0';
end if;
end if;
end if;
end process RXD_SYNC_FILTER;
UART_RECEIVE_DATA : process(CLOCK, RESET)
begin
if RESET = '1' then
uart_rx_state <= rx_wait_start_synchronise;
uart_rx_data_block <= (others => '0');
uart_rx_count <= c_uart_rxtx_count_reset;
uart_rx_data_out_stb <= '0';
uart_rx_sync_clock <= (others => '0');
elsif rising_edge(CLOCK) then
case uart_rx_state is
-- Waiting for new data to come
when rx_wait_start_synchronise =>
-- With normal clock: Take care about the ACK from
-- previous received data
if DATA_STREAM_OUT_ACK = '1' then
-- Revoke strobe
uart_rx_data_out_stb <= '0';
-- No need to reset data block, it's anyway overwritten during recive
-- uart_rx_data_block <= (others => '0');
end if;
-- Only here we need to look for start with the
-- oversampled clock rate
if oversample_baud_tick = '1' and uart_rx_bit = '0' then
-- We are back in business!
uart_rx_state <= rx_get_start_bit;
-- Resynchronize the receive bit timing with the input signal
-- invert the MSB, because we need to skip half of
-- the start bit.
-- We want to sample in the MIDDLE of the bit, remember?
-- This will be used from now on as sample moment
uart_rx_sync_clock <=
(not baud_counter(3), baud_counter(2), baud_counter(1), baud_counter(0) );
end if; -- oversample_baud_tick = '1' and uart_rx_bit = '0'
when rx_get_start_bit =>
-- With normal clock: Take care about the ACK from
-- previous received data
if DATA_STREAM_OUT_ACK = '1' then
-- Revoke strobe
uart_rx_data_out_stb <= '0';
-- No need to reset data block, it's anyway overwritten during recive
-- uart_rx_data_block <= (others => '0');
end if;
if uart_rx_sample_tick = '1' then
if uart_rx_bit = '0' then
-- Everything alright, we really got a start bit
-- Please continue with data reception
uart_rx_state <= rx_get_data;
-- This is the last time we can revoke a potentially pending
-- receive strobe
-- Your fault if you didn't fetched the data until here!
uart_rx_data_out_stb <= '0';
-- But at least warn about this
-- Not for synthesis:
-- pragma translate_off
assert uart_rx_data_out_stb = '0'
report "Receive Data was not fetched by system! Losing previous data byte!"
severity warning;
-- pragma translate_on
else
-- Oh no! Corrupted Start bit! Now we're in trouble
-- Best to abort the game and issue a (simulation)
-- warning
uart_rx_state <= rx_wait_start_synchronise;
-- Not for synthesis:
-- pragma translate_off
report "We got an corrupted start bit! Something is wrong and most likely we will now fail to receive the following data. Trying to reset the receive state machine."
severity error;
-- pragma translate_on
end if;
end if;
when rx_get_data =>
if uart_rx_sample_tick = '1' then
-- Receive next bit, shift others one bit down
-- We receive lsb first, thus we're filling and shifting from msb direction
uart_rx_data_block <= shift_right_by_one(uart_rx_data_block, uart_rx_bit);
if uart_rx_count = 7 then -- binary 111
-- We're done, move to next state
uart_rx_state <= rx_get_stop_bit;
else
-- Continue in this state
uart_rx_state <= rx_get_data;
end if;
-- Always increment here, will go to zero if we're out
uart_rx_count <= uart_rx_count + 1;
end if;
when rx_get_stop_bit =>
if uart_rx_sample_tick = '1' then
if uart_rx_bit = '1' then
-- Everything alright, we really got the closing stop bit
-- Set our strobe: Data is ready!
uart_rx_data_out_stb <= '1';
else
-- Oh no! Corrupted Stop bit! Now we're in trouble
-- Best to abort the game and issue a (simulation) warning
-- Not for synthesis:
-- pragma translate_off
report "We got an corrupted stop bit! Something is wrong - throwing away this data byte"
severity error;
-- pragma translate_on
end if;
-- Anyway, go to wait for next datablock
uart_rx_state <= rx_wait_start_synchronise;
end if;
when others => -- This is an illegal state - start over
uart_rx_state <= rx_wait_start_synchronise;
end case;
end if;
end process UART_RECEIVE_DATA;
end RTL;
|
library ieee;
use ieee.std_logic_1164.all;
entity bug is
end entity;
architecture a of bug is
signal irunning :natural range 0 to 1 := 2; -- reports no error
begin
irunning <= 2; -- reports error, but no information
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
entity bug is
end entity;
architecture a of bug is
signal irunning :natural range 0 to 1 := 2; -- reports no error
begin
irunning <= 2; -- reports error, but no information
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
entity bug is
end entity;
architecture a of bug is
signal irunning :natural range 0 to 1 := 2; -- reports no error
begin
irunning <= 2; -- reports error, but no information
end architecture;
|
-- fichier access_test.vhdl
-- created by Yann Guidon / ygdes.com
-- version jeu. avril 10 01:03:13 CEST 2014
-- Copyright (C) 2014 Yann GUIDON
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
library work;
use work.ghdl_access.all;
entity test_access is
-- vide
end test_access;
architecture test of test_access is
begin
process
begin
report "integer=" & integer'image(my_data.all);
my_data.all := 42;
report "integer=" & integer'image(my_data.all);
change_int(24);
report "integer=" & integer'image(my_data.all);
wait;
end process;
end test;
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
-- Date : Mon Apr 03 17:46:36 2017
-- Host : LAPTOP-IQ9G3D1I running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub
-- C:/Users/andrewandre/Documents/GitHub/axiplasma/hdl/projects/VC707/bd/mig_wrap/ip/mig_wrap_mig_7series_0_0/mig_wrap_mig_7series_0_0_stub.vhdl
-- Design : mig_wrap_mig_7series_0_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7vx485tffg1761-2
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity mig_wrap_mig_7series_0_0 is
Port (
ddr3_dq : inout STD_LOGIC_VECTOR ( 63 downto 0 );
ddr3_dqs_n : inout STD_LOGIC_VECTOR ( 7 downto 0 );
ddr3_dqs_p : inout STD_LOGIC_VECTOR ( 7 downto 0 );
ddr3_addr : out STD_LOGIC_VECTOR ( 13 downto 0 );
ddr3_ba : out STD_LOGIC_VECTOR ( 2 downto 0 );
ddr3_ras_n : out STD_LOGIC;
ddr3_cas_n : out STD_LOGIC;
ddr3_we_n : out STD_LOGIC;
ddr3_reset_n : out STD_LOGIC;
ddr3_ck_p : out STD_LOGIC_VECTOR ( 0 to 0 );
ddr3_ck_n : out STD_LOGIC_VECTOR ( 0 to 0 );
ddr3_cke : out STD_LOGIC_VECTOR ( 0 to 0 );
ddr3_cs_n : out STD_LOGIC_VECTOR ( 0 to 0 );
ddr3_dm : out STD_LOGIC_VECTOR ( 7 downto 0 );
ddr3_odt : out STD_LOGIC_VECTOR ( 0 to 0 );
sys_clk_p : in STD_LOGIC;
sys_clk_n : in STD_LOGIC;
ui_clk : out STD_LOGIC;
ui_clk_sync_rst : out STD_LOGIC;
ui_addn_clk_0 : out STD_LOGIC;
ui_addn_clk_1 : out STD_LOGIC;
ui_addn_clk_2 : out STD_LOGIC;
ui_addn_clk_3 : out STD_LOGIC;
ui_addn_clk_4 : out STD_LOGIC;
mmcm_locked : out STD_LOGIC;
aresetn : in STD_LOGIC;
app_sr_active : out STD_LOGIC;
app_ref_ack : out STD_LOGIC;
app_zq_ack : out STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 29 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 511 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 63 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 29 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 511 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
init_calib_complete : out STD_LOGIC;
device_temp : out STD_LOGIC_VECTOR ( 11 downto 0 );
sys_rst : in STD_LOGIC
);
end mig_wrap_mig_7series_0_0;
architecture stub of mig_wrap_mig_7series_0_0 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "ddr3_dq[63:0],ddr3_dqs_n[7:0],ddr3_dqs_p[7:0],ddr3_addr[13:0],ddr3_ba[2:0],ddr3_ras_n,ddr3_cas_n,ddr3_we_n,ddr3_reset_n,ddr3_ck_p[0:0],ddr3_ck_n[0:0],ddr3_cke[0:0],ddr3_cs_n[0:0],ddr3_dm[7:0],ddr3_odt[0:0],sys_clk_p,sys_clk_n,ui_clk,ui_clk_sync_rst,ui_addn_clk_0,ui_addn_clk_1,ui_addn_clk_2,ui_addn_clk_3,ui_addn_clk_4,mmcm_locked,aresetn,app_sr_active,app_ref_ack,app_zq_ack,s_axi_awid[3:0],s_axi_awaddr[29:0],s_axi_awlen[7:0],s_axi_awsize[2:0],s_axi_awburst[1:0],s_axi_awlock[0:0],s_axi_awcache[3:0],s_axi_awprot[2:0],s_axi_awqos[3:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[511:0],s_axi_wstrb[63:0],s_axi_wlast,s_axi_wvalid,s_axi_wready,s_axi_bready,s_axi_bid[3:0],s_axi_bresp[1:0],s_axi_bvalid,s_axi_arid[3:0],s_axi_araddr[29:0],s_axi_arlen[7:0],s_axi_arsize[2:0],s_axi_arburst[1:0],s_axi_arlock[0:0],s_axi_arcache[3:0],s_axi_arprot[2:0],s_axi_arqos[3:0],s_axi_arvalid,s_axi_arready,s_axi_rready,s_axi_rid[3:0],s_axi_rdata[511:0],s_axi_rresp[1:0],s_axi_rlast,s_axi_rvalid,init_calib_complete,device_temp[11:0],sys_rst";
begin
end;
|
-------------------------------------------------------------------------------
--
-- T400 Core
--
-- $Id: t400_por.vhd,v 1.1 2006-05-07 01:47:51 arniml Exp $
--
-- Wrapper for technology dependent power-on reset circuitry.
--
-- Xilinx Spartan3 flavor.
--
-- Generate a reset upon power-on for specified number of clocks.
--
-------------------------------------------------------------------------------
--
-- Copyright (c) 2006, Arnim Laeuger ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity t400_por is
generic (
delay_g : integer := 4;
cnt_width_g : integer := 2
);
port (
clk_i : in std_logic;
por_n_o : out std_logic
);
end t400_por;
library ieee;
use ieee.numeric_std.all;
architecture spartan of t400_por is
-----------------------------------------------------------------------------
-- According to
-- "XST User Guide", Chapter 6 "VHDL Language Support", "Initial Values"
-- XST honors the initial value assigned to a flip-flop. Simple :-)
--
signal por_cnt_q : unsigned(cnt_width_g-1 downto 0)
:= to_unsigned(delay_g, cnt_width_g);
signal por_n_q : std_logic := '0';
--
-----------------------------------------------------------------------------
begin
-----------------------------------------------------------------------------
-- Process por_cnt
--
-- Purpose:
-- Generate a power-on reset for the specified number of clocks.
--
por_cnt: process (clk_i)
begin
if clk_i'event and clk_i = '1' then
if por_cnt_q = 0 then
por_n_q <= '1';
else
por_cnt_q <= por_cnt_q - 1;
end if;
end if;
end process por_cnt;
--
-----------------------------------------------------------------------------
por_n_o <= por_n_q;
end spartan;
|
----------------------------------------------------------------------------------
--
-- full_tb.vhd
--
-- (c) 2015
-- L. Schrittwieser
-- N. Huesser
--
----------------------------------------------------------------------------------
--
-- A testbench to test the logger core with real inputs.
--
----------------------------------------------------------------------------------
library UNISIM;
use UNISIM.VCOMPONENTS.all;
library UNIMACRO;
use UNIMACRO.VCOMPONENTS.all;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.math_real.all;
entity full_tb is
end full_tb;
architecture Behavioral of full_tb is
-- TODO:
-- create testsignals here
signal tbClkxC : std_logic := '0';
signal tbRstxRB : std_logic := '0';
signal tbDataxD : std_logic_vector(31 downto 0) := (others => '0');
signal tbCntxD: signed(15 downto 0) := to_signed(-430, 16);
signal tbValidxS : std_logic := '0';
signal tbReadyxS: std_logic := '0';
signal tbData0xDO: std_logic_vector(15 downto 0) := (others => '0');
signal tbData1xDO: std_logic_vector(15 downto 0) := (others => '0');
signal tbStrobexS: std_logic := '0';
begin
-- generate clock
tbClkxC <= not tbClkxC after 1ns;
tbDataxD <= std_logic_vector(tbCntxD) & std_logic_vector(tbCntxD);
DUT : entity work.axis_to_data_lanes
generic map (
Decimation => 3
)
port map (
ClkxCI => tbClkxC,
RstxRBI => tbRstxRB,
AxiTDataxDI=> tbDataxD,
AxiTValid => tbValidxS,
AxiTReady => tbReadyxS,
Data0xDO => tbData0xDO,
Data1xDO => tbData1xDO,
DataStrobexDO => tbStrobexS
);
process
begin
-- TODO:
-- write chain of events here
tbRstxRB <= '0';
wait until rising_edge(tbClkxC);
wait until rising_edge(tbClkxC);
tbRstxRB <= '1';
wait until rising_edge(tbClkxC);
tbValidxS <= '0';
for i in 0 to 30 loop
wait until rising_edge(tbClkxC);
end loop;
tbValidxS <= '1';
for i in 0 to 30 loop
wait until rising_edge(tbClkxC);
end loop;
wait;
end process;
process(tbClkxC, tbRstxRB, tbCntxD)
begin
if rising_edge(tbClkxC) then
tbCntxD <= to_signed(-430, 16);
if tbRstxRB = '1' then
tbCntxD <= tbCntxD + 1;
end if;
end if;
end process;
end Behavioral;
|
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.