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-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:buffer_register:1.0
-- IP Revision: 2
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_buffer_register_1_0 IS
PORT (
clk : IN STD_LOGIC;
val_in : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
val_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END system_buffer_register_1_0;
ARCHITECTURE system_buffer_register_1_0_arch OF system_buffer_register_1_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_buffer_register_1_0_arch: ARCHITECTURE IS "yes";
COMPONENT buffer_register IS
GENERIC (
WIDTH : INTEGER
);
PORT (
clk : IN STD_LOGIC;
val_in : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
val_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT buffer_register;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF system_buffer_register_1_0_arch: ARCHITECTURE IS "buffer_register,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF system_buffer_register_1_0_arch : ARCHITECTURE IS "system_buffer_register_1_0,buffer_register,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF system_buffer_register_1_0_arch: ARCHITECTURE IS "system_buffer_register_1_0,buffer_register,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=user,x_ipName=buffer_register,x_ipVersion=1.0,x_ipCoreRevision=2,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,WIDTH=32}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clk CLK";
BEGIN
U0 : buffer_register
GENERIC MAP (
WIDTH => 32
)
PORT MAP (
clk => clk,
val_in => val_in,
val_out => val_out
);
END system_buffer_register_1_0_arch;
|
entity tb_modulo_test is
end tb_modulo_test;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_modulo_test is
signal a, b, c : integer := 0;
begin
dut: entity work.modulo_test
port map (a, b, c);
process
begin
a <= 7;
wait for 1 ns;
assert b = 7 severity failure;
assert c = 7 severity failure;
a <= 8;
wait for 1 ns;
assert b = 0 severity failure;
assert c = 0 severity failure;
a <= -7;
wait for 1 ns;
assert b = 1 severity failure;
assert c = -7 severity failure;
wait;
end process;
end behav;
|
package pack1 is
type ma_t is array(1 downto 0) of bit_vector(1 downto 0);
end pack1;
use work.pack1.all;
entity arraysub is
generic(par1: bit_vector(3 downto 0) := "1111");
end entity;
architecture test of arraysub is
signal s1, s2: ma_t;
begin
s1(1)<=par1(1 downto 0);
s1(0)<=par1(3 downto 2);
s2(1 downto 1) <= ( 1 => par1(3 downto 2) );
s2(0 downto 0) <= ( 0 => par1(1 downto 0) );
process is
begin
wait for 1 ns;
assert s1 = ( "11", "11" );
wait;
end process;
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity feature_buffer_block is
generic (
PARITY : std_logic := '0'
);
port (
clk_x2 : in std_logic;
enable : in std_logic;
clear : in std_logic;
x_in_left : in std_logic_vector(9 downto 0);
y_in_left : in std_logic_vector(9 downto 0);
hessian_in_left : in std_logic_vector(31 downto 0);
x_in_right : in std_logic_vector(9 downto 0);
y_in_right : in std_logic_vector(9 downto 0);
hessian_in_right : in std_logic_vector(31 downto 0);
x_out_left : out std_logic_vector(9 downto 0);
y_out_left : out std_logic_vector(9 downto 0);
hessian_out_left : out std_logic_vector(31 downto 0);
x_out_right : out std_logic_vector(9 downto 0);
y_out_right : out std_logic_vector(9 downto 0);
hessian_out_right : out std_logic_vector(31 downto 0)
);
end feature_buffer_block;
architecture Behavioral of feature_buffer_block is
signal hessian : unsigned(31 downto 0) := x"00000000";
signal x : std_logic_vector(9 downto 0) := "0000000000";
signal y : std_logic_vector(9 downto 0) := "0000000000";
signal cycle : std_logic := '0';
begin
hessian_out_left <= std_logic_vector(hessian);
x_out_left <= x;
y_out_left <= y;
hessian_out_right <= std_logic_vector(hessian);
x_out_right <= x;
y_out_right <= y;
process(clk_x2)
begin
if rising_edge(clk_x2) then
if clear = '1' then
hessian <= x"00000000";
x <= "0000000000";
y <= "0000000000";
cycle <= '0';
else
if enable = '1' then
if PARITY = cycle then
if hessian > unsigned(hessian_in_right) then
hessian <= unsigned(hessian_in_right);
x <= x_in_right;
y <= y_in_right;
end if;
else
if hessian < unsigned(hessian_in_left) then
hessian <= unsigned(hessian_in_left);
x <= x_in_left;
y <= y_in_left;
end if;
end if;
cycle <= not cycle;
end if;
end if;
end if;
end process;
end Behavioral;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity feature_buffer_block is
generic (
PARITY : std_logic := '0'
);
port (
clk_x2 : in std_logic;
enable : in std_logic;
clear : in std_logic;
x_in_left : in std_logic_vector(9 downto 0);
y_in_left : in std_logic_vector(9 downto 0);
hessian_in_left : in std_logic_vector(31 downto 0);
x_in_right : in std_logic_vector(9 downto 0);
y_in_right : in std_logic_vector(9 downto 0);
hessian_in_right : in std_logic_vector(31 downto 0);
x_out_left : out std_logic_vector(9 downto 0);
y_out_left : out std_logic_vector(9 downto 0);
hessian_out_left : out std_logic_vector(31 downto 0);
x_out_right : out std_logic_vector(9 downto 0);
y_out_right : out std_logic_vector(9 downto 0);
hessian_out_right : out std_logic_vector(31 downto 0)
);
end feature_buffer_block;
architecture Behavioral of feature_buffer_block is
signal hessian : unsigned(31 downto 0) := x"00000000";
signal x : std_logic_vector(9 downto 0) := "0000000000";
signal y : std_logic_vector(9 downto 0) := "0000000000";
signal cycle : std_logic := '0';
begin
hessian_out_left <= std_logic_vector(hessian);
x_out_left <= x;
y_out_left <= y;
hessian_out_right <= std_logic_vector(hessian);
x_out_right <= x;
y_out_right <= y;
process(clk_x2)
begin
if rising_edge(clk_x2) then
if clear = '1' then
hessian <= x"00000000";
x <= "0000000000";
y <= "0000000000";
cycle <= '0';
else
if enable = '1' then
if PARITY = cycle then
if hessian > unsigned(hessian_in_right) then
hessian <= unsigned(hessian_in_right);
x <= x_in_right;
y <= y_in_right;
end if;
else
if hessian < unsigned(hessian_in_left) then
hessian <= unsigned(hessian_in_left);
x <= x_in_left;
y <= y_in_left;
end if;
end if;
cycle <= not cycle;
end if;
end if;
end if;
end process;
end Behavioral;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity feature_buffer_block is
generic (
PARITY : std_logic := '0'
);
port (
clk_x2 : in std_logic;
enable : in std_logic;
clear : in std_logic;
x_in_left : in std_logic_vector(9 downto 0);
y_in_left : in std_logic_vector(9 downto 0);
hessian_in_left : in std_logic_vector(31 downto 0);
x_in_right : in std_logic_vector(9 downto 0);
y_in_right : in std_logic_vector(9 downto 0);
hessian_in_right : in std_logic_vector(31 downto 0);
x_out_left : out std_logic_vector(9 downto 0);
y_out_left : out std_logic_vector(9 downto 0);
hessian_out_left : out std_logic_vector(31 downto 0);
x_out_right : out std_logic_vector(9 downto 0);
y_out_right : out std_logic_vector(9 downto 0);
hessian_out_right : out std_logic_vector(31 downto 0)
);
end feature_buffer_block;
architecture Behavioral of feature_buffer_block is
signal hessian : unsigned(31 downto 0) := x"00000000";
signal x : std_logic_vector(9 downto 0) := "0000000000";
signal y : std_logic_vector(9 downto 0) := "0000000000";
signal cycle : std_logic := '0';
begin
hessian_out_left <= std_logic_vector(hessian);
x_out_left <= x;
y_out_left <= y;
hessian_out_right <= std_logic_vector(hessian);
x_out_right <= x;
y_out_right <= y;
process(clk_x2)
begin
if rising_edge(clk_x2) then
if clear = '1' then
hessian <= x"00000000";
x <= "0000000000";
y <= "0000000000";
cycle <= '0';
else
if enable = '1' then
if PARITY = cycle then
if hessian > unsigned(hessian_in_right) then
hessian <= unsigned(hessian_in_right);
x <= x_in_right;
y <= y_in_right;
end if;
else
if hessian < unsigned(hessian_in_left) then
hessian <= unsigned(hessian_in_left);
x <= x_in_left;
y <= y_in_left;
end if;
end if;
cycle <= not cycle;
end if;
end if;
end if;
end process;
end Behavioral;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity projeto2 is
port (
a : in std_logic_vector (3 downto 0) := "0001"; -- Entrada A.
b : in std_logic_vector (3 downto 0) := "0000"; -- Entrada B.
sel : in std_logic := '0'; -- Seletora de displays.
clk : in std_logic := '0'; -- Clock.
display1 : out std_logic_vector (6 downto 0);
display2 : out std_logic_vector (6 downto 0)
);
end projeto2;
architecture Behavioral of projeto2 is
signal saida_mux : std_logic_vector (3 downto 0);
signal bcd : std_logic_vector (6 downto 0); -- BCD.
begin
-- Mux 8->4.
process (a,b, clk)
begin
if (clk = '0') then
saida_mux <= a;
else
saida_mux <= b;
end if;
end process;
-- BCD.
process (a,b,clk, saida_mux, bcd)
begin
if (saida_mux = "0000") then -- 0
bcd <= "1111110";
elsif (saida_mux = "0001") then -- 1
bcd <= "0110000";
elsif (saida_mux = "0010") then -- 2
bcd <= "1101101";
elsif (saida_mux = "0011") then -- 3
bcd <= "1111001";
elsif (saida_mux = "0100") then -- 4
bcd <= "0110010";
elsif (saida_mux = "0101") then -- 5
bcd <= "1011010";
elsif (saida_mux = "0110") then -- 6
bcd <= "1011111";
elsif (saida_mux = "0111") then -- 7
bcd <= "1110000";
elsif (saida_mux = "1000") then -- 8
bcd <= "1111111";
elsif (saida_mux = "1001") then -- 9
bcd <= "1111011";
elsif (saida_mux = "1010") then -- A
bcd <= "1110111";
elsif (saida_mux = "1011") then -- B
bcd <= "0011111";
elsif (saida_mux = "1100") then -- C
bcd <= "1001110";
elsif (saida_mux = "1101") then -- D
bcd <= "0111101";
elsif (saida_mux = "1110") then -- E
bcd <= "1001111";
else
bcd <= "1000111"; -- Caso defaul -> 'F'
end if;
end process;
-- Mux 1->2.
process (bcd, clk, sel)
begin
if (clk = '0' and sel = '0') then -- Se sel = 0 então mostra B.
display2 <= bcd; -- Mostra B no display.
display1 <= "00000000"; -- Desliga A.
elsif (clk = '1' and sel = '1') then -- Se sel = 1 então mostra A.
display1 <= bcd; -- Mostra A no display.
display2 <= "00000000"; -- Desliga B.
else
-- Caso inesperado.
display1 <= "00000000"; -- Desliga A.
display2 <= "00000000"; -- Desliga B.
end if;
end process;
end Behavioral;
|
-- -------------------------------------------------------------
--
-- Generated Configuration for ent_b
--
-- Generated
-- by: wig
-- on: Thu Jan 19 08:06:43 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -strip -nodelta ../intra.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: ent_b-rtl-conf-c.vhd,v 1.2 2006/01/19 08:50:41 wig Exp $
-- $Date: 2006/01/19 08:50:41 $
-- $Log: ent_b-rtl-conf-c.vhd,v $
-- Revision 1.2 2006/01/19 08:50:41 wig
-- Updated testcases, left 6 failing now (constant, bitsplice/X, ...)
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.75 2006/01/18 16:59:29 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.43 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/conf
--
-- Start of Generated Configuration ent_b_rtl_conf / ent_b
--
configuration ent_b_rtl_conf of ent_b is
for rtl
-- Generated Configuration
-- __I_NO_CONFIG_VERILOG --for inst_ba : ent_ba
-- __I_NO_CONFIG_VERILOG -- use configuration work.ent_ba_rtl_conf;
-- __I_NO_CONFIG_VERILOG --end for;
for inst_bb : ent_bb
use configuration work.ent_bb_rtl_conf;
end for;
end for;
end ent_b_rtl_conf;
--
-- End of Generated Configuration ent_b_rtl_conf
--
--
--!End of Configuration/ies
-- --------------------------------------------------------------
|
-- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity Gray_Binarization is
port (
Avalon_MM_Slave_address : in std_logic_vector(2-1 downto 0);
Avalon_MM_Slave_write : in std_logic;
Avalon_MM_Slave_writedata : in std_logic_vector(32-1 downto 0);
Avalon_ST_Sink_data : in std_logic_vector(24-1 downto 0);
Avalon_ST_Sink_endofpacket : in std_logic;
Avalon_ST_Sink_ready : out std_logic;
Avalon_ST_Sink_startofpacket : in std_logic;
Avalon_ST_Sink_valid : in std_logic;
Avalon_ST_Source_data : out std_logic_vector(24-1 downto 0);
Avalon_ST_Source_endofpacket : out std_logic;
Avalon_ST_Source_ready : in std_logic;
Avalon_ST_Source_startofpacket : out std_logic;
Avalon_ST_Source_valid : out std_logic;
Clock : in std_logic;
aclr : in std_logic
);
end entity Gray_Binarization;
architecture rtl of Gray_Binarization is
component Gray_Binarization_GN is
port (
Avalon_MM_Slave_address : in std_logic_vector(2-1 downto 0);
Avalon_MM_Slave_write : in std_logic;
Avalon_MM_Slave_writedata : in std_logic_vector(32-1 downto 0);
Avalon_ST_Sink_data : in std_logic_vector(24-1 downto 0);
Avalon_ST_Sink_endofpacket : in std_logic;
Avalon_ST_Sink_ready : out std_logic;
Avalon_ST_Sink_startofpacket : in std_logic;
Avalon_ST_Sink_valid : in std_logic;
Avalon_ST_Source_data : out std_logic_vector(24-1 downto 0);
Avalon_ST_Source_endofpacket : out std_logic;
Avalon_ST_Source_ready : in std_logic;
Avalon_ST_Source_startofpacket : out std_logic;
Avalon_ST_Source_valid : out std_logic;
Clock : in std_logic;
aclr : in std_logic
);
end component Gray_Binarization_GN;
begin
Gray_Binarization_GN_0: if true generate
inst_Gray_Binarization_GN_0: Gray_Binarization_GN
port map(Avalon_MM_Slave_address => Avalon_MM_Slave_address, Avalon_MM_Slave_write => Avalon_MM_Slave_write, Avalon_MM_Slave_writedata => Avalon_MM_Slave_writedata, Avalon_ST_Sink_data => Avalon_ST_Sink_data, Avalon_ST_Sink_endofpacket => Avalon_ST_Sink_endofpacket, Avalon_ST_Sink_ready => Avalon_ST_Sink_ready, Avalon_ST_Sink_startofpacket => Avalon_ST_Sink_startofpacket, Avalon_ST_Sink_valid => Avalon_ST_Sink_valid, Avalon_ST_Source_data => Avalon_ST_Source_data, Avalon_ST_Source_endofpacket => Avalon_ST_Source_endofpacket, Avalon_ST_Source_ready => Avalon_ST_Source_ready, Avalon_ST_Source_startofpacket => Avalon_ST_Source_startofpacket, Avalon_ST_Source_valid => Avalon_ST_Source_valid, Clock => Clock, aclr => aclr);
end generate;
end architecture rtl;
|
-- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity Gray_Binarization is
port (
Avalon_MM_Slave_address : in std_logic_vector(2-1 downto 0);
Avalon_MM_Slave_write : in std_logic;
Avalon_MM_Slave_writedata : in std_logic_vector(32-1 downto 0);
Avalon_ST_Sink_data : in std_logic_vector(24-1 downto 0);
Avalon_ST_Sink_endofpacket : in std_logic;
Avalon_ST_Sink_ready : out std_logic;
Avalon_ST_Sink_startofpacket : in std_logic;
Avalon_ST_Sink_valid : in std_logic;
Avalon_ST_Source_data : out std_logic_vector(24-1 downto 0);
Avalon_ST_Source_endofpacket : out std_logic;
Avalon_ST_Source_ready : in std_logic;
Avalon_ST_Source_startofpacket : out std_logic;
Avalon_ST_Source_valid : out std_logic;
Clock : in std_logic;
aclr : in std_logic
);
end entity Gray_Binarization;
architecture rtl of Gray_Binarization is
component Gray_Binarization_GN is
port (
Avalon_MM_Slave_address : in std_logic_vector(2-1 downto 0);
Avalon_MM_Slave_write : in std_logic;
Avalon_MM_Slave_writedata : in std_logic_vector(32-1 downto 0);
Avalon_ST_Sink_data : in std_logic_vector(24-1 downto 0);
Avalon_ST_Sink_endofpacket : in std_logic;
Avalon_ST_Sink_ready : out std_logic;
Avalon_ST_Sink_startofpacket : in std_logic;
Avalon_ST_Sink_valid : in std_logic;
Avalon_ST_Source_data : out std_logic_vector(24-1 downto 0);
Avalon_ST_Source_endofpacket : out std_logic;
Avalon_ST_Source_ready : in std_logic;
Avalon_ST_Source_startofpacket : out std_logic;
Avalon_ST_Source_valid : out std_logic;
Clock : in std_logic;
aclr : in std_logic
);
end component Gray_Binarization_GN;
begin
Gray_Binarization_GN_0: if true generate
inst_Gray_Binarization_GN_0: Gray_Binarization_GN
port map(Avalon_MM_Slave_address => Avalon_MM_Slave_address, Avalon_MM_Slave_write => Avalon_MM_Slave_write, Avalon_MM_Slave_writedata => Avalon_MM_Slave_writedata, Avalon_ST_Sink_data => Avalon_ST_Sink_data, Avalon_ST_Sink_endofpacket => Avalon_ST_Sink_endofpacket, Avalon_ST_Sink_ready => Avalon_ST_Sink_ready, Avalon_ST_Sink_startofpacket => Avalon_ST_Sink_startofpacket, Avalon_ST_Sink_valid => Avalon_ST_Sink_valid, Avalon_ST_Source_data => Avalon_ST_Source_data, Avalon_ST_Source_endofpacket => Avalon_ST_Source_endofpacket, Avalon_ST_Source_ready => Avalon_ST_Source_ready, Avalon_ST_Source_startofpacket => Avalon_ST_Source_startofpacket, Avalon_ST_Source_valid => Avalon_ST_Source_valid, Clock => Clock, aclr => aclr);
end generate;
end architecture rtl;
|
-- Copyright (c) 2015 CERN
-- Maciej Suminski <[email protected]>
--
-- This source code is free software; you can redistribute it
-- and/or modify it in source code form under the terms of the GNU
-- General Public License as published by the Free Software
-- Foundation; either version 2 of the License, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
-- Report & assert tests.
library ieee;
use ieee.std_logic_1164.all;
use work.vhdl_report_pkg.all;
entity vhdl_report is
port (start_test : in std_logic);
end vhdl_report;
architecture test of vhdl_report is
begin
process(start_test)
begin
if(start_test = '1') then
-- Report without severity specified, by default it is NOTE
report "normal report";
-- Report with severity specified
-- should continue execution when severity != FAILURE
report "report with severity"
severity ERROR;
-- Assert, no report, no severity specified, by default it is ERROR
assert false;
-- Assert with report, no severity specified, by default it is ERROR
assert 1 = 0
report "assert with report";
-- Assert without report, severity specified
-- should continue execution when severity != FAILURE
assert 1 = 2
severity NOTE;
-- Assert with report and severity specified
assert false
report "assert with report & severity"
severity FAILURE; -- FAILURE causes program to stop
report "this should never be shown";
end if;
end process;
end architecture test;
|
-- Copyright (c) 2015 CERN
-- Maciej Suminski <[email protected]>
--
-- This source code is free software; you can redistribute it
-- and/or modify it in source code form under the terms of the GNU
-- General Public License as published by the Free Software
-- Foundation; either version 2 of the License, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
-- Report & assert tests.
library ieee;
use ieee.std_logic_1164.all;
use work.vhdl_report_pkg.all;
entity vhdl_report is
port (start_test : in std_logic);
end vhdl_report;
architecture test of vhdl_report is
begin
process(start_test)
begin
if(start_test = '1') then
-- Report without severity specified, by default it is NOTE
report "normal report";
-- Report with severity specified
-- should continue execution when severity != FAILURE
report "report with severity"
severity ERROR;
-- Assert, no report, no severity specified, by default it is ERROR
assert false;
-- Assert with report, no severity specified, by default it is ERROR
assert 1 = 0
report "assert with report";
-- Assert without report, severity specified
-- should continue execution when severity != FAILURE
assert 1 = 2
severity NOTE;
-- Assert with report and severity specified
assert false
report "assert with report & severity"
severity FAILURE; -- FAILURE causes program to stop
report "this should never be shown";
end if;
end process;
end architecture test;
|
-- Copyright (c) 2015 CERN
-- Maciej Suminski <[email protected]>
--
-- This source code is free software; you can redistribute it
-- and/or modify it in source code form under the terms of the GNU
-- General Public License as published by the Free Software
-- Foundation; either version 2 of the License, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
-- Report & assert tests.
library ieee;
use ieee.std_logic_1164.all;
use work.vhdl_report_pkg.all;
entity vhdl_report is
port (start_test : in std_logic);
end vhdl_report;
architecture test of vhdl_report is
begin
process(start_test)
begin
if(start_test = '1') then
-- Report without severity specified, by default it is NOTE
report "normal report";
-- Report with severity specified
-- should continue execution when severity != FAILURE
report "report with severity"
severity ERROR;
-- Assert, no report, no severity specified, by default it is ERROR
assert false;
-- Assert with report, no severity specified, by default it is ERROR
assert 1 = 0
report "assert with report";
-- Assert without report, severity specified
-- should continue execution when severity != FAILURE
assert 1 = 2
severity NOTE;
-- Assert with report and severity specified
assert false
report "assert with report & severity"
severity FAILURE; -- FAILURE causes program to stop
report "this should never be shown";
end if;
end process;
end architecture test;
|
library verilog;
use verilog.vl_types.all;
entity arm_id_stage is
port(
clk : in vl_logic;
rst_b : in vl_logic;
inst : in vl_logic_vector(31 downto 0);
data0 : in vl_logic_vector(31 downto 0);
data1 : in vl_logic_vector(31 downto 0);
data2 : in vl_logic_vector(31 downto 0);
cpsr_out : in vl_logic_vector(31 downto 0);
EXID_cpsr : in vl_logic_vector(31 downto 0);
EXID_rd_we : in vl_logic;
MEMID_rd_we : in vl_logic;
EXID_cpsr_we : in vl_logic;
EXID_rd_num : in vl_logic_vector(3 downto 0);
MEMID_rd_num : in vl_logic_vector(3 downto 0);
data0_reg_num : out vl_logic_vector(3 downto 0);
data1_reg_num : out vl_logic_vector(3 downto 0);
data2_reg_num : out vl_logic_vector(3 downto 0);
real_PCWrite : out vl_logic;
halted : out vl_logic;
IDEX_rs_or_rd_data: out vl_logic_vector(31 downto 0);
IDEX_rn_data : out vl_logic_vector(31 downto 0);
IDEX_rm_data : out vl_logic_vector(31 downto 0);
IDEX_rd_we : out vl_logic;
IDEX_cpsr_we : out vl_logic;
IDEX_rd_data_sel: out vl_logic;
IDEX_is_imm : out vl_logic;
IDEX_alu_or_mac : out vl_logic;
IDEX_up_down : out vl_logic;
IDEX_mac_sel : out vl_logic;
IDEX_alu_sel : out vl_logic_vector(3 downto 0);
IDEX_cpsr_mask : out vl_logic_vector(3 downto 0);
IDEX_is_alu_for_mem_addr: out vl_logic;
IDEX_rd_sel : out vl_logic;
IDEX_mem_write_en: out vl_logic_vector(3 downto 0);
IDEX_ld_byte_or_word: out vl_logic;
IDEX_cpsr : out vl_logic_vector(31 downto 0);
IDEX_inst_11_0 : out vl_logic_vector(11 downto 0);
IDEX_inst_19_16 : out vl_logic_vector(3 downto 0);
IDEX_inst_15_12 : out vl_logic_vector(3 downto 0);
IFID_Write : out vl_logic
);
end arm_id_stage;
|
--Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use IEEE.NUMERIC_STD.all;
use ieee.math_real.all;
use std.textio.all;
use ieee.std_logic_misc.all;
package TB_Package is
function Header_gen(source, destination: integer ) return std_logic_vector ;
function Body_1_gen(Packet_length, packet_id: integer ) return std_logic_vector ;
function Body_gen(Data: integer ) return std_logic_vector ;
function Tail_gen(Packet_length, Data: integer ) return std_logic_vector ;
procedure credit_counter_control(signal clk: in std_logic;
signal credit_in: in std_logic; signal valid_out: in std_logic;
signal credit_counter_out: out std_logic_vector(1 downto 0));
procedure gen_random_packet(network_size, frame_length, source, initial_delay, min_packet_size, max_packet_size: in integer;
finish_time: in time; signal clk: in std_logic;
signal credit_counter_in: in std_logic_vector(1 downto 0); signal valid_out: out std_logic;
signal port_in: out std_logic_vector);
procedure gen_bit_reversed_packet(network_size, frame_length, source, initial_delay, min_packet_size, max_packet_size: in integer;
finish_time: in time; signal clk: in std_logic;
signal credit_counter_in: in std_logic_vector(1 downto 0); signal valid_out: out std_logic;
signal port_in: out std_logic_vector);
procedure get_packet(DATA_WIDTH, initial_delay, Node_ID: in integer; signal clk: in std_logic;
signal credit_out: out std_logic; signal valid_in: in std_logic; signal port_in: in std_logic_vector);
end TB_Package;
package body TB_Package is
constant Header_type : std_logic_vector := "001";
constant Body_type : std_logic_vector := "010";
constant Tail_type : std_logic_vector := "100";
function Header_gen(source, destination: integer)
return std_logic_vector is
variable Header_flit: std_logic_vector (31 downto 0);
begin
Header_flit := Header_type & std_logic_vector(to_unsigned(source, 14)) &
std_logic_vector(to_unsigned(destination, 14)) & XOR_REDUCE(Header_type & std_logic_vector(to_unsigned(source, 14)) &
std_logic_vector(to_unsigned(destination, 14)));
return Header_flit;
end Header_gen;
function Body_1_gen(Packet_length, packet_id: integer)
return std_logic_vector is
variable Body_flit: std_logic_vector (31 downto 0);
begin
Body_flit := Body_type & std_logic_vector(to_unsigned(Packet_length, 14))& std_logic_vector(to_unsigned(packet_id, 14)) &
XOR_REDUCE(Body_type & std_logic_vector(to_unsigned(Packet_length, 14))& std_logic_vector(to_unsigned(packet_id, 14)));
return Body_flit;
end Body_1_gen;
function Body_gen(Data: integer)
return std_logic_vector is
variable Body_flit: std_logic_vector (31 downto 0);
begin
Body_flit := Body_type & std_logic_vector(to_unsigned(Data, 28)) & XOR_REDUCE(Body_type & std_logic_vector(to_unsigned(Data, 28)));
return Body_flit;
end Body_gen;
function Tail_gen(Packet_length, Data: integer)
return std_logic_vector is
variable Tail_flit: std_logic_vector (31 downto 0);
begin
Tail_flit := Tail_type & std_logic_vector(to_unsigned(Data, 28)) & XOR_REDUCE(Tail_type & std_logic_vector(to_unsigned(Data, 28)));
return Tail_flit;
end Tail_gen;
procedure credit_counter_control(signal clk: in std_logic;
signal credit_in: in std_logic; signal valid_out: in std_logic;
signal credit_counter_out: out std_logic_vector(1 downto 0)) is
variable credit_counter: std_logic_vector (1 downto 0);
begin
credit_counter := "11";
while true loop
credit_counter_out<= credit_counter;
wait until clk'event and clk ='1';
if valid_out = '1' and credit_in ='1' then
credit_counter := credit_counter;
elsif credit_in = '1' then
credit_counter := credit_counter + 1;
elsif valid_out = '1' and credit_counter > 0 then
credit_counter := credit_counter - 1;
else
credit_counter := credit_counter;
end if;
end loop;
end credit_counter_control;
procedure gen_random_packet(network_size, frame_length, source, initial_delay, min_packet_size, max_packet_size: in integer;
finish_time: in time; signal clk: in std_logic;
signal credit_counter_in: in std_logic_vector(1 downto 0); signal valid_out: out std_logic;
signal port_in: out std_logic_vector) is
variable seed1 :positive := source+1;
variable seed2 :positive := source+1;
variable LINEVARIABLE : line;
file VEC_FILE : text is out "sent.txt";
variable rand : real ;
variable destination_id: integer;
variable id_counter, frame_starting_delay, Packet_length, frame_ending_delay : integer:= 0;
variable credit_counter: std_logic_vector (1 downto 0);
begin
Packet_length := integer((integer(rand*100.0)*frame_length)/100);
valid_out <= '0';
port_in <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX" ;
wait until clk'event and clk ='1';
for i in 0 to initial_delay loop
wait until clk'event and clk ='1';
end loop;
port_in <= "UUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU" ;
while true loop
--generating the frame initial delay
uniform(seed1, seed2, rand);
frame_starting_delay := integer(((integer(rand*100.0)*(frame_length - Packet_length-1)))/100);
--generating the frame ending delay
frame_ending_delay := frame_length - (Packet_length+frame_starting_delay);
for k in 0 to frame_starting_delay-1 loop
wait until clk'event and clk ='0';
end loop;
valid_out <= '0';
while credit_counter_in = 0 loop
wait until clk'event and clk ='0';
end loop;
-- generating the packet
id_counter := id_counter + 1;
if id_counter = 16384 then
id_counter := 0;
end if;
--------------------------------------
uniform(seed1, seed2, rand);
Packet_length := integer((integer(rand*100.0)*frame_length)/100);
if (Packet_length < min_packet_size) then
Packet_length:=min_packet_size;
end if;
if (Packet_length > max_packet_size) then
Packet_length:=max_packet_size;
end if;
--------------------------------------
uniform(seed1, seed2, rand);
destination_id := integer(rand*real((network_size**2)-1));
while (destination_id = source) loop
uniform(seed1, seed2, rand);
destination_id := integer(rand*real((network_size**2)-1));
end loop;
--------------------------------------
write(LINEVARIABLE, "Packet generated at " & time'image(now) & " From " & integer'image(source) & " to " & integer'image(destination_id) & " with length: " & integer'image(Packet_length) & " id: " & integer'image(id_counter));
writeline(VEC_FILE, LINEVARIABLE);
wait until clk'event and clk ='0'; -- On negative edge of clk (for syncing purposes)
port_in <= Header_gen(source, destination_id); -- Generating the header flit of the packet (All packets have a header flit)!
valid_out <= '1';
wait until clk'event and clk ='0';
for I in 0 to Packet_length-3 loop
-- The reason for -3 is that we have packet length of Packet_length, now if you exclude header and tail
-- it would be Packet_length-2 to enumerate them, you can count from 0 to Packet_length-3.
if credit_counter_in = "00" then
valid_out <= '0';
-- Wait until next router/NI has at least enough space for one flit in its input FIFO
wait until credit_counter_in'event and credit_counter_in > 0;
wait until clk'event and clk ='0';
end if;
uniform(seed1, seed2, rand);
-- Each packet can have no body flits or one or more than body flits.
if I = 0 then
port_in <= Body_1_gen(Packet_length, id_counter);
else
port_in <= Body_gen(integer(rand*1000.0));
end if;
valid_out <= '1';
wait until clk'event and clk ='0';
end loop;
if credit_counter_in = "00" then
valid_out <= '0';
-- Wait until next router/NI has at least enough space for one flit in its input FIFO
wait until credit_counter_in'event and credit_counter_in > 0;
wait until clk'event and clk ='0';
end if;
uniform(seed1, seed2, rand);
-- Close the packet with a tail flit (All packets have one tail flit)!
port_in <= Tail_gen(Packet_length, integer(rand*1000.0));
valid_out <= '1';
wait until clk'event and clk ='0';
valid_out <= '0';
port_in <= "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ" ;
for l in 0 to frame_ending_delay-1 loop
wait until clk'event and clk ='0';
end loop;
port_in <= "UUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU" ;
if now > finish_time then
wait;
end if;
end loop;
end gen_random_packet;
procedure gen_bit_reversed_packet(network_size, frame_length, source, initial_delay, min_packet_size, max_packet_size: in integer;
finish_time: in time; signal clk: in std_logic;
signal credit_counter_in: in std_logic_vector(1 downto 0); signal valid_out: out std_logic;
signal port_in: out std_logic_vector) is
variable seed1 :positive := source+1;
variable seed2 :positive := source+1;
variable LINEVARIABLE : line;
file VEC_FILE : text is out "sent.txt";
variable rand : real ;
variable destination_id: integer;
variable id_counter, frame_starting_delay, Packet_length, frame_ending_delay : integer:= 0;
variable credit_counter: std_logic_vector (1 downto 0);
begin
Packet_length := integer((integer(rand*100.0)*frame_length)/300);
valid_out <= '0';
port_in <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX" ;
wait until clk'event and clk ='1';
for i in 0 to initial_delay loop
wait until clk'event and clk ='1';
end loop;
port_in <= "UUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU" ;
while true loop
--generating the frame initial delay
uniform(seed1, seed2, rand);
frame_starting_delay := integer(((integer(rand*100.0)*(frame_length - 3*Packet_length)))/100);
--generating the frame ending delay
frame_ending_delay := frame_length - (3*Packet_length+frame_starting_delay);
for k in 0 to frame_starting_delay-1 loop
wait until clk'event and clk ='0';
end loop;
valid_out <= '0';
while credit_counter_in = 0 loop
wait until clk'event and clk ='0';
end loop;
-- generating the packet
id_counter := id_counter + 1;
if id_counter = 16384 then
id_counter := 0;
end if;
--------------------------------------
uniform(seed1, seed2, rand);
Packet_length := integer((integer(rand*100.0)*frame_length)/300);
if (Packet_length < min_packet_size) then
Packet_length:=min_packet_size;
end if;
if (Packet_length > max_packet_size) then
Packet_length:=max_packet_size;
end if;
--------------------------------------
destination_id := to_integer(unsigned(not std_logic_vector(to_unsigned(source, network_size))));
if destination_id = source then
wait;
end if;
--------------------------------------
write(LINEVARIABLE, "Packet generated at " & time'image(now) & " From " & integer'image(source) & " to " & integer'image(destination_id) & " with length: " & integer'image(Packet_length) & " id: " & integer'image(id_counter));
writeline(VEC_FILE, LINEVARIABLE);
wait until clk'event and clk ='0';
port_in <= Header_gen(source, destination_id); -- Generating the header flit of the packet (All packets have a header flit)!
valid_out <= '1';
wait until clk'event and clk ='0';
for I in 0 to Packet_length-3 loop
if credit_counter_in = "00" then
valid_out <= '0';
wait until credit_counter_in'event and credit_counter_in >0;
wait until clk'event and clk ='0';
end if;
uniform(seed1, seed2, rand);
if I = 0 then
port_in <= Body_1_gen(Packet_length, id_counter);
else
port_in <= Body_gen(integer(rand*1000.0));
end if;
valid_out <= '1';
wait until clk'event and clk ='0';
end loop;
if credit_counter_in = "00" then
valid_out <= '0';
wait until credit_counter_in'event and credit_counter_in >0;
wait until clk'event and clk ='0';
end if;
uniform(seed1, seed2, rand);
port_in <= Tail_gen(Packet_length, integer(rand*1000.0));
valid_out <= '1';
wait until clk'event and clk ='0';
valid_out <= '0';
port_in <= "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ" ;
for l in 0 to frame_ending_delay-1 loop
wait until clk'event and clk ='0';
end loop;
port_in <= "UUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU" ;
if now > finish_time then
wait;
end if;
end loop;
end gen_bit_reversed_packet;
procedure get_packet(DATA_WIDTH, initial_delay, Node_ID: in integer; signal clk: in std_logic;
signal credit_out: out std_logic; signal valid_in: in std_logic; signal port_in: in std_logic_vector) is
-- initial_delay: waits for this number of clock cycles before sending the packet!
variable source_node, destination_node, P_length, packet_id, counter: integer;
variable LINEVARIABLE : line;
file VEC_FILE : text is out "received.txt";
file DIAGNOSIS_FILE : text is out "DIAGNOSIS.txt";
variable DIAGNOSIS: std_logic;
variable DIAGNOSIS_vector: std_logic_vector(12 downto 0);
begin
credit_out <= '1';
counter := 0;
while true loop
wait until clk'event and clk ='1';
if valid_in = '1' then
if (port_in(DATA_WIDTH-1 downto DATA_WIDTH-3) = "001") then
counter := 1;
DIAGNOSIS := '0';
source_node := to_integer(unsigned(port_in(28 downto 15)));
destination_node := to_integer(unsigned(port_in(14 downto 1)));
end if;
if (port_in(DATA_WIDTH-1 downto DATA_WIDTH-3) = "010") then
--report "flit type: " &integer'image(to_integer(unsigned(port_in(DATA_WIDTH-1 downto DATA_WIDTH-3)))) ;
--report "counter: " & integer'image(counter);
if counter = 1 then
P_length := to_integer(unsigned(port_in(28 downto 15)));
packet_id := to_integer(unsigned(port_in(15 downto 1)));
end if;
counter := counter+1;
if port_in(28 downto 13) = "0100011001000100" then
DIAGNOSIS := '1';
DIAGNOSIS_vector(11 downto 0) := port_in(12 downto 1);
end if;
end if;
if (port_in(DATA_WIDTH-1 downto DATA_WIDTH-3) = "100") then
counter := counter+1;
report "Node: " & integer'image(Node_ID) & " Packet received at " & time'image(now) & " From " & integer'image(source_node) & " to " & integer'image(destination_node) & " with length: "& integer'image(P_length) & " counter: "& integer'image(counter);
assert (P_length=counter) report "wrong packet size" severity warning;
assert (Node_ID=destination_node) report "wrong packet destination " severity failure;
if DIAGNOSIS = '1' then
DIAGNOSIS_vector(12) := port_in(28);
write(LINEVARIABLE, "Packet received at " & time'image(now) & " From: " & integer'image(source_node) & " to: " & integer'image(destination_node) & " length: "& integer'image(P_length) & " actual length: "& integer'image(counter) & " id: "& integer'image(packet_id));
writeline(DIAGNOSIS_FILE, LINEVARIABLE);
else
write(LINEVARIABLE, "Packet received at " & time'image(now) & " From: " & integer'image(source_node) & " to: " & integer'image(destination_node) & " length: "& integer'image(P_length) & " actual length: "& integer'image(counter) & " id: "& integer'image(packet_id));
writeline(VEC_FILE, LINEVARIABLE);
end if;
counter := 0;
end if;
end if;
end loop;
end get_packet;
end TB_Package;
|
--Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use IEEE.NUMERIC_STD.all;
use ieee.math_real.all;
use std.textio.all;
use ieee.std_logic_misc.all;
package TB_Package is
function Header_gen(source, destination: integer ) return std_logic_vector ;
function Body_1_gen(Packet_length, packet_id: integer ) return std_logic_vector ;
function Body_gen(Data: integer ) return std_logic_vector ;
function Tail_gen(Packet_length, Data: integer ) return std_logic_vector ;
procedure credit_counter_control(signal clk: in std_logic;
signal credit_in: in std_logic; signal valid_out: in std_logic;
signal credit_counter_out: out std_logic_vector(1 downto 0));
procedure gen_random_packet(network_size, frame_length, source, initial_delay, min_packet_size, max_packet_size: in integer;
finish_time: in time; signal clk: in std_logic;
signal credit_counter_in: in std_logic_vector(1 downto 0); signal valid_out: out std_logic;
signal port_in: out std_logic_vector);
procedure gen_bit_reversed_packet(network_size, frame_length, source, initial_delay, min_packet_size, max_packet_size: in integer;
finish_time: in time; signal clk: in std_logic;
signal credit_counter_in: in std_logic_vector(1 downto 0); signal valid_out: out std_logic;
signal port_in: out std_logic_vector);
procedure get_packet(DATA_WIDTH, initial_delay, Node_ID: in integer; signal clk: in std_logic;
signal credit_out: out std_logic; signal valid_in: in std_logic; signal port_in: in std_logic_vector);
end TB_Package;
package body TB_Package is
constant Header_type : std_logic_vector := "001";
constant Body_type : std_logic_vector := "010";
constant Tail_type : std_logic_vector := "100";
function Header_gen(source, destination: integer)
return std_logic_vector is
variable Header_flit: std_logic_vector (31 downto 0);
begin
Header_flit := Header_type & std_logic_vector(to_unsigned(source, 14)) &
std_logic_vector(to_unsigned(destination, 14)) & XOR_REDUCE(Header_type & std_logic_vector(to_unsigned(source, 14)) &
std_logic_vector(to_unsigned(destination, 14)));
return Header_flit;
end Header_gen;
function Body_1_gen(Packet_length, packet_id: integer)
return std_logic_vector is
variable Body_flit: std_logic_vector (31 downto 0);
begin
Body_flit := Body_type & std_logic_vector(to_unsigned(Packet_length, 14))& std_logic_vector(to_unsigned(packet_id, 14)) &
XOR_REDUCE(Body_type & std_logic_vector(to_unsigned(Packet_length, 14))& std_logic_vector(to_unsigned(packet_id, 14)));
return Body_flit;
end Body_1_gen;
function Body_gen(Data: integer)
return std_logic_vector is
variable Body_flit: std_logic_vector (31 downto 0);
begin
Body_flit := Body_type & std_logic_vector(to_unsigned(Data, 28)) & XOR_REDUCE(Body_type & std_logic_vector(to_unsigned(Data, 28)));
return Body_flit;
end Body_gen;
function Tail_gen(Packet_length, Data: integer)
return std_logic_vector is
variable Tail_flit: std_logic_vector (31 downto 0);
begin
Tail_flit := Tail_type & std_logic_vector(to_unsigned(Data, 28)) & XOR_REDUCE(Tail_type & std_logic_vector(to_unsigned(Data, 28)));
return Tail_flit;
end Tail_gen;
procedure credit_counter_control(signal clk: in std_logic;
signal credit_in: in std_logic; signal valid_out: in std_logic;
signal credit_counter_out: out std_logic_vector(1 downto 0)) is
variable credit_counter: std_logic_vector (1 downto 0);
begin
credit_counter := "11";
while true loop
credit_counter_out<= credit_counter;
wait until clk'event and clk ='1';
if valid_out = '1' and credit_in ='1' then
credit_counter := credit_counter;
elsif credit_in = '1' then
credit_counter := credit_counter + 1;
elsif valid_out = '1' and credit_counter > 0 then
credit_counter := credit_counter - 1;
else
credit_counter := credit_counter;
end if;
end loop;
end credit_counter_control;
procedure gen_random_packet(network_size, frame_length, source, initial_delay, min_packet_size, max_packet_size: in integer;
finish_time: in time; signal clk: in std_logic;
signal credit_counter_in: in std_logic_vector(1 downto 0); signal valid_out: out std_logic;
signal port_in: out std_logic_vector) is
variable seed1 :positive := source+1;
variable seed2 :positive := source+1;
variable LINEVARIABLE : line;
file VEC_FILE : text is out "sent.txt";
variable rand : real ;
variable destination_id: integer;
variable id_counter, frame_starting_delay, Packet_length, frame_ending_delay : integer:= 0;
variable credit_counter: std_logic_vector (1 downto 0);
begin
Packet_length := integer((integer(rand*100.0)*frame_length)/100);
valid_out <= '0';
port_in <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX" ;
wait until clk'event and clk ='1';
for i in 0 to initial_delay loop
wait until clk'event and clk ='1';
end loop;
port_in <= "UUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU" ;
while true loop
--generating the frame initial delay
uniform(seed1, seed2, rand);
frame_starting_delay := integer(((integer(rand*100.0)*(frame_length - Packet_length-1)))/100);
--generating the frame ending delay
frame_ending_delay := frame_length - (Packet_length+frame_starting_delay);
for k in 0 to frame_starting_delay-1 loop
wait until clk'event and clk ='0';
end loop;
valid_out <= '0';
while credit_counter_in = 0 loop
wait until clk'event and clk ='0';
end loop;
-- generating the packet
id_counter := id_counter + 1;
if id_counter = 16384 then
id_counter := 0;
end if;
--------------------------------------
uniform(seed1, seed2, rand);
Packet_length := integer((integer(rand*100.0)*frame_length)/100);
if (Packet_length < min_packet_size) then
Packet_length:=min_packet_size;
end if;
if (Packet_length > max_packet_size) then
Packet_length:=max_packet_size;
end if;
--------------------------------------
uniform(seed1, seed2, rand);
destination_id := integer(rand*real((network_size**2)-1));
while (destination_id = source) loop
uniform(seed1, seed2, rand);
destination_id := integer(rand*real((network_size**2)-1));
end loop;
--------------------------------------
write(LINEVARIABLE, "Packet generated at " & time'image(now) & " From " & integer'image(source) & " to " & integer'image(destination_id) & " with length: " & integer'image(Packet_length) & " id: " & integer'image(id_counter));
writeline(VEC_FILE, LINEVARIABLE);
wait until clk'event and clk ='0'; -- On negative edge of clk (for syncing purposes)
port_in <= Header_gen(source, destination_id); -- Generating the header flit of the packet (All packets have a header flit)!
valid_out <= '1';
wait until clk'event and clk ='0';
for I in 0 to Packet_length-3 loop
-- The reason for -3 is that we have packet length of Packet_length, now if you exclude header and tail
-- it would be Packet_length-2 to enumerate them, you can count from 0 to Packet_length-3.
if credit_counter_in = "00" then
valid_out <= '0';
-- Wait until next router/NI has at least enough space for one flit in its input FIFO
wait until credit_counter_in'event and credit_counter_in > 0;
wait until clk'event and clk ='0';
end if;
uniform(seed1, seed2, rand);
-- Each packet can have no body flits or one or more than body flits.
if I = 0 then
port_in <= Body_1_gen(Packet_length, id_counter);
else
port_in <= Body_gen(integer(rand*1000.0));
end if;
valid_out <= '1';
wait until clk'event and clk ='0';
end loop;
if credit_counter_in = "00" then
valid_out <= '0';
-- Wait until next router/NI has at least enough space for one flit in its input FIFO
wait until credit_counter_in'event and credit_counter_in > 0;
wait until clk'event and clk ='0';
end if;
uniform(seed1, seed2, rand);
-- Close the packet with a tail flit (All packets have one tail flit)!
port_in <= Tail_gen(Packet_length, integer(rand*1000.0));
valid_out <= '1';
wait until clk'event and clk ='0';
valid_out <= '0';
port_in <= "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ" ;
for l in 0 to frame_ending_delay-1 loop
wait until clk'event and clk ='0';
end loop;
port_in <= "UUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU" ;
if now > finish_time then
wait;
end if;
end loop;
end gen_random_packet;
procedure gen_bit_reversed_packet(network_size, frame_length, source, initial_delay, min_packet_size, max_packet_size: in integer;
finish_time: in time; signal clk: in std_logic;
signal credit_counter_in: in std_logic_vector(1 downto 0); signal valid_out: out std_logic;
signal port_in: out std_logic_vector) is
variable seed1 :positive := source+1;
variable seed2 :positive := source+1;
variable LINEVARIABLE : line;
file VEC_FILE : text is out "sent.txt";
variable rand : real ;
variable destination_id: integer;
variable id_counter, frame_starting_delay, Packet_length, frame_ending_delay : integer:= 0;
variable credit_counter: std_logic_vector (1 downto 0);
begin
Packet_length := integer((integer(rand*100.0)*frame_length)/300);
valid_out <= '0';
port_in <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX" ;
wait until clk'event and clk ='1';
for i in 0 to initial_delay loop
wait until clk'event and clk ='1';
end loop;
port_in <= "UUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU" ;
while true loop
--generating the frame initial delay
uniform(seed1, seed2, rand);
frame_starting_delay := integer(((integer(rand*100.0)*(frame_length - 3*Packet_length)))/100);
--generating the frame ending delay
frame_ending_delay := frame_length - (3*Packet_length+frame_starting_delay);
for k in 0 to frame_starting_delay-1 loop
wait until clk'event and clk ='0';
end loop;
valid_out <= '0';
while credit_counter_in = 0 loop
wait until clk'event and clk ='0';
end loop;
-- generating the packet
id_counter := id_counter + 1;
if id_counter = 16384 then
id_counter := 0;
end if;
--------------------------------------
uniform(seed1, seed2, rand);
Packet_length := integer((integer(rand*100.0)*frame_length)/300);
if (Packet_length < min_packet_size) then
Packet_length:=min_packet_size;
end if;
if (Packet_length > max_packet_size) then
Packet_length:=max_packet_size;
end if;
--------------------------------------
destination_id := to_integer(unsigned(not std_logic_vector(to_unsigned(source, network_size))));
if destination_id = source then
wait;
end if;
--------------------------------------
write(LINEVARIABLE, "Packet generated at " & time'image(now) & " From " & integer'image(source) & " to " & integer'image(destination_id) & " with length: " & integer'image(Packet_length) & " id: " & integer'image(id_counter));
writeline(VEC_FILE, LINEVARIABLE);
wait until clk'event and clk ='0';
port_in <= Header_gen(source, destination_id); -- Generating the header flit of the packet (All packets have a header flit)!
valid_out <= '1';
wait until clk'event and clk ='0';
for I in 0 to Packet_length-3 loop
if credit_counter_in = "00" then
valid_out <= '0';
wait until credit_counter_in'event and credit_counter_in >0;
wait until clk'event and clk ='0';
end if;
uniform(seed1, seed2, rand);
if I = 0 then
port_in <= Body_1_gen(Packet_length, id_counter);
else
port_in <= Body_gen(integer(rand*1000.0));
end if;
valid_out <= '1';
wait until clk'event and clk ='0';
end loop;
if credit_counter_in = "00" then
valid_out <= '0';
wait until credit_counter_in'event and credit_counter_in >0;
wait until clk'event and clk ='0';
end if;
uniform(seed1, seed2, rand);
port_in <= Tail_gen(Packet_length, integer(rand*1000.0));
valid_out <= '1';
wait until clk'event and clk ='0';
valid_out <= '0';
port_in <= "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ" ;
for l in 0 to frame_ending_delay-1 loop
wait until clk'event and clk ='0';
end loop;
port_in <= "UUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU" ;
if now > finish_time then
wait;
end if;
end loop;
end gen_bit_reversed_packet;
procedure get_packet(DATA_WIDTH, initial_delay, Node_ID: in integer; signal clk: in std_logic;
signal credit_out: out std_logic; signal valid_in: in std_logic; signal port_in: in std_logic_vector) is
-- initial_delay: waits for this number of clock cycles before sending the packet!
variable source_node, destination_node, P_length, packet_id, counter: integer;
variable LINEVARIABLE : line;
file VEC_FILE : text is out "received.txt";
file DIAGNOSIS_FILE : text is out "DIAGNOSIS.txt";
variable DIAGNOSIS: std_logic;
variable DIAGNOSIS_vector: std_logic_vector(12 downto 0);
begin
credit_out <= '1';
counter := 0;
while true loop
wait until clk'event and clk ='1';
if valid_in = '1' then
if (port_in(DATA_WIDTH-1 downto DATA_WIDTH-3) = "001") then
counter := 1;
DIAGNOSIS := '0';
source_node := to_integer(unsigned(port_in(28 downto 15)));
destination_node := to_integer(unsigned(port_in(14 downto 1)));
end if;
if (port_in(DATA_WIDTH-1 downto DATA_WIDTH-3) = "010") then
--report "flit type: " &integer'image(to_integer(unsigned(port_in(DATA_WIDTH-1 downto DATA_WIDTH-3)))) ;
--report "counter: " & integer'image(counter);
if counter = 1 then
P_length := to_integer(unsigned(port_in(28 downto 15)));
packet_id := to_integer(unsigned(port_in(15 downto 1)));
end if;
counter := counter+1;
if port_in(28 downto 13) = "0100011001000100" then
DIAGNOSIS := '1';
DIAGNOSIS_vector(11 downto 0) := port_in(12 downto 1);
end if;
end if;
if (port_in(DATA_WIDTH-1 downto DATA_WIDTH-3) = "100") then
counter := counter+1;
report "Node: " & integer'image(Node_ID) & " Packet received at " & time'image(now) & " From " & integer'image(source_node) & " to " & integer'image(destination_node) & " with length: "& integer'image(P_length) & " counter: "& integer'image(counter);
assert (P_length=counter) report "wrong packet size" severity warning;
assert (Node_ID=destination_node) report "wrong packet destination " severity failure;
if DIAGNOSIS = '1' then
DIAGNOSIS_vector(12) := port_in(28);
write(LINEVARIABLE, "Packet received at " & time'image(now) & " From: " & integer'image(source_node) & " to: " & integer'image(destination_node) & " length: "& integer'image(P_length) & " actual length: "& integer'image(counter) & " id: "& integer'image(packet_id));
writeline(DIAGNOSIS_FILE, LINEVARIABLE);
else
write(LINEVARIABLE, "Packet received at " & time'image(now) & " From: " & integer'image(source_node) & " to: " & integer'image(destination_node) & " length: "& integer'image(P_length) & " actual length: "& integer'image(counter) & " id: "& integer'image(packet_id));
writeline(VEC_FILE, LINEVARIABLE);
end if;
counter := 0;
end if;
end if;
end loop;
end get_packet;
end TB_Package;
|
--Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use IEEE.NUMERIC_STD.all;
use ieee.math_real.all;
use std.textio.all;
use ieee.std_logic_misc.all;
package TB_Package is
function Header_gen(source, destination: integer ) return std_logic_vector ;
function Body_1_gen(Packet_length, packet_id: integer ) return std_logic_vector ;
function Body_gen(Data: integer ) return std_logic_vector ;
function Tail_gen(Packet_length, Data: integer ) return std_logic_vector ;
procedure credit_counter_control(signal clk: in std_logic;
signal credit_in: in std_logic; signal valid_out: in std_logic;
signal credit_counter_out: out std_logic_vector(1 downto 0));
procedure gen_random_packet(network_size, frame_length, source, initial_delay, min_packet_size, max_packet_size: in integer;
finish_time: in time; signal clk: in std_logic;
signal credit_counter_in: in std_logic_vector(1 downto 0); signal valid_out: out std_logic;
signal port_in: out std_logic_vector);
procedure gen_bit_reversed_packet(network_size, frame_length, source, initial_delay, min_packet_size, max_packet_size: in integer;
finish_time: in time; signal clk: in std_logic;
signal credit_counter_in: in std_logic_vector(1 downto 0); signal valid_out: out std_logic;
signal port_in: out std_logic_vector);
procedure get_packet(DATA_WIDTH, initial_delay, Node_ID: in integer; signal clk: in std_logic;
signal credit_out: out std_logic; signal valid_in: in std_logic; signal port_in: in std_logic_vector);
end TB_Package;
package body TB_Package is
constant Header_type : std_logic_vector := "001";
constant Body_type : std_logic_vector := "010";
constant Tail_type : std_logic_vector := "100";
function Header_gen(source, destination: integer)
return std_logic_vector is
variable Header_flit: std_logic_vector (31 downto 0);
begin
Header_flit := Header_type & std_logic_vector(to_unsigned(source, 14)) &
std_logic_vector(to_unsigned(destination, 14)) & XOR_REDUCE(Header_type & std_logic_vector(to_unsigned(source, 14)) &
std_logic_vector(to_unsigned(destination, 14)));
return Header_flit;
end Header_gen;
function Body_1_gen(Packet_length, packet_id: integer)
return std_logic_vector is
variable Body_flit: std_logic_vector (31 downto 0);
begin
Body_flit := Body_type & std_logic_vector(to_unsigned(Packet_length, 14))& std_logic_vector(to_unsigned(packet_id, 14)) &
XOR_REDUCE(Body_type & std_logic_vector(to_unsigned(Packet_length, 14))& std_logic_vector(to_unsigned(packet_id, 14)));
return Body_flit;
end Body_1_gen;
function Body_gen(Data: integer)
return std_logic_vector is
variable Body_flit: std_logic_vector (31 downto 0);
begin
Body_flit := Body_type & std_logic_vector(to_unsigned(Data, 28)) & XOR_REDUCE(Body_type & std_logic_vector(to_unsigned(Data, 28)));
return Body_flit;
end Body_gen;
function Tail_gen(Packet_length, Data: integer)
return std_logic_vector is
variable Tail_flit: std_logic_vector (31 downto 0);
begin
Tail_flit := Tail_type & std_logic_vector(to_unsigned(Data, 28)) & XOR_REDUCE(Tail_type & std_logic_vector(to_unsigned(Data, 28)));
return Tail_flit;
end Tail_gen;
procedure credit_counter_control(signal clk: in std_logic;
signal credit_in: in std_logic; signal valid_out: in std_logic;
signal credit_counter_out: out std_logic_vector(1 downto 0)) is
variable credit_counter: std_logic_vector (1 downto 0);
begin
credit_counter := "11";
while true loop
credit_counter_out<= credit_counter;
wait until clk'event and clk ='1';
if valid_out = '1' and credit_in ='1' then
credit_counter := credit_counter;
elsif credit_in = '1' then
credit_counter := credit_counter + 1;
elsif valid_out = '1' and credit_counter > 0 then
credit_counter := credit_counter - 1;
else
credit_counter := credit_counter;
end if;
end loop;
end credit_counter_control;
procedure gen_random_packet(network_size, frame_length, source, initial_delay, min_packet_size, max_packet_size: in integer;
finish_time: in time; signal clk: in std_logic;
signal credit_counter_in: in std_logic_vector(1 downto 0); signal valid_out: out std_logic;
signal port_in: out std_logic_vector) is
variable seed1 :positive := source+1;
variable seed2 :positive := source+1;
variable LINEVARIABLE : line;
file VEC_FILE : text is out "sent.txt";
variable rand : real ;
variable destination_id: integer;
variable id_counter, frame_starting_delay, Packet_length, frame_ending_delay : integer:= 0;
variable credit_counter: std_logic_vector (1 downto 0);
begin
Packet_length := integer((integer(rand*100.0)*frame_length)/100);
valid_out <= '0';
port_in <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX" ;
wait until clk'event and clk ='1';
for i in 0 to initial_delay loop
wait until clk'event and clk ='1';
end loop;
port_in <= "UUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU" ;
while true loop
--generating the frame initial delay
uniform(seed1, seed2, rand);
frame_starting_delay := integer(((integer(rand*100.0)*(frame_length - Packet_length-1)))/100);
--generating the frame ending delay
frame_ending_delay := frame_length - (Packet_length+frame_starting_delay);
for k in 0 to frame_starting_delay-1 loop
wait until clk'event and clk ='0';
end loop;
valid_out <= '0';
while credit_counter_in = 0 loop
wait until clk'event and clk ='0';
end loop;
-- generating the packet
id_counter := id_counter + 1;
if id_counter = 16384 then
id_counter := 0;
end if;
--------------------------------------
uniform(seed1, seed2, rand);
Packet_length := integer((integer(rand*100.0)*frame_length)/100);
if (Packet_length < min_packet_size) then
Packet_length:=min_packet_size;
end if;
if (Packet_length > max_packet_size) then
Packet_length:=max_packet_size;
end if;
--------------------------------------
uniform(seed1, seed2, rand);
destination_id := integer(rand*real((network_size**2)-1));
while (destination_id = source) loop
uniform(seed1, seed2, rand);
destination_id := integer(rand*real((network_size**2)-1));
end loop;
--------------------------------------
write(LINEVARIABLE, "Packet generated at " & time'image(now) & " From " & integer'image(source) & " to " & integer'image(destination_id) & " with length: " & integer'image(Packet_length) & " id: " & integer'image(id_counter));
writeline(VEC_FILE, LINEVARIABLE);
wait until clk'event and clk ='0'; -- On negative edge of clk (for syncing purposes)
port_in <= Header_gen(source, destination_id); -- Generating the header flit of the packet (All packets have a header flit)!
valid_out <= '1';
wait until clk'event and clk ='0';
for I in 0 to Packet_length-3 loop
-- The reason for -3 is that we have packet length of Packet_length, now if you exclude header and tail
-- it would be Packet_length-2 to enumerate them, you can count from 0 to Packet_length-3.
if credit_counter_in = "00" then
valid_out <= '0';
-- Wait until next router/NI has at least enough space for one flit in its input FIFO
wait until credit_counter_in'event and credit_counter_in > 0;
wait until clk'event and clk ='0';
end if;
uniform(seed1, seed2, rand);
-- Each packet can have no body flits or one or more than body flits.
if I = 0 then
port_in <= Body_1_gen(Packet_length, id_counter);
else
port_in <= Body_gen(integer(rand*1000.0));
end if;
valid_out <= '1';
wait until clk'event and clk ='0';
end loop;
if credit_counter_in = "00" then
valid_out <= '0';
-- Wait until next router/NI has at least enough space for one flit in its input FIFO
wait until credit_counter_in'event and credit_counter_in > 0;
wait until clk'event and clk ='0';
end if;
uniform(seed1, seed2, rand);
-- Close the packet with a tail flit (All packets have one tail flit)!
port_in <= Tail_gen(Packet_length, integer(rand*1000.0));
valid_out <= '1';
wait until clk'event and clk ='0';
valid_out <= '0';
port_in <= "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ" ;
for l in 0 to frame_ending_delay-1 loop
wait until clk'event and clk ='0';
end loop;
port_in <= "UUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU" ;
if now > finish_time then
wait;
end if;
end loop;
end gen_random_packet;
procedure gen_bit_reversed_packet(network_size, frame_length, source, initial_delay, min_packet_size, max_packet_size: in integer;
finish_time: in time; signal clk: in std_logic;
signal credit_counter_in: in std_logic_vector(1 downto 0); signal valid_out: out std_logic;
signal port_in: out std_logic_vector) is
variable seed1 :positive := source+1;
variable seed2 :positive := source+1;
variable LINEVARIABLE : line;
file VEC_FILE : text is out "sent.txt";
variable rand : real ;
variable destination_id: integer;
variable id_counter, frame_starting_delay, Packet_length, frame_ending_delay : integer:= 0;
variable credit_counter: std_logic_vector (1 downto 0);
begin
Packet_length := integer((integer(rand*100.0)*frame_length)/300);
valid_out <= '0';
port_in <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX" ;
wait until clk'event and clk ='1';
for i in 0 to initial_delay loop
wait until clk'event and clk ='1';
end loop;
port_in <= "UUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU" ;
while true loop
--generating the frame initial delay
uniform(seed1, seed2, rand);
frame_starting_delay := integer(((integer(rand*100.0)*(frame_length - 3*Packet_length)))/100);
--generating the frame ending delay
frame_ending_delay := frame_length - (3*Packet_length+frame_starting_delay);
for k in 0 to frame_starting_delay-1 loop
wait until clk'event and clk ='0';
end loop;
valid_out <= '0';
while credit_counter_in = 0 loop
wait until clk'event and clk ='0';
end loop;
-- generating the packet
id_counter := id_counter + 1;
if id_counter = 16384 then
id_counter := 0;
end if;
--------------------------------------
uniform(seed1, seed2, rand);
Packet_length := integer((integer(rand*100.0)*frame_length)/300);
if (Packet_length < min_packet_size) then
Packet_length:=min_packet_size;
end if;
if (Packet_length > max_packet_size) then
Packet_length:=max_packet_size;
end if;
--------------------------------------
destination_id := to_integer(unsigned(not std_logic_vector(to_unsigned(source, network_size))));
if destination_id = source then
wait;
end if;
--------------------------------------
write(LINEVARIABLE, "Packet generated at " & time'image(now) & " From " & integer'image(source) & " to " & integer'image(destination_id) & " with length: " & integer'image(Packet_length) & " id: " & integer'image(id_counter));
writeline(VEC_FILE, LINEVARIABLE);
wait until clk'event and clk ='0';
port_in <= Header_gen(source, destination_id); -- Generating the header flit of the packet (All packets have a header flit)!
valid_out <= '1';
wait until clk'event and clk ='0';
for I in 0 to Packet_length-3 loop
if credit_counter_in = "00" then
valid_out <= '0';
wait until credit_counter_in'event and credit_counter_in >0;
wait until clk'event and clk ='0';
end if;
uniform(seed1, seed2, rand);
if I = 0 then
port_in <= Body_1_gen(Packet_length, id_counter);
else
port_in <= Body_gen(integer(rand*1000.0));
end if;
valid_out <= '1';
wait until clk'event and clk ='0';
end loop;
if credit_counter_in = "00" then
valid_out <= '0';
wait until credit_counter_in'event and credit_counter_in >0;
wait until clk'event and clk ='0';
end if;
uniform(seed1, seed2, rand);
port_in <= Tail_gen(Packet_length, integer(rand*1000.0));
valid_out <= '1';
wait until clk'event and clk ='0';
valid_out <= '0';
port_in <= "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ" ;
for l in 0 to frame_ending_delay-1 loop
wait until clk'event and clk ='0';
end loop;
port_in <= "UUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU" ;
if now > finish_time then
wait;
end if;
end loop;
end gen_bit_reversed_packet;
procedure get_packet(DATA_WIDTH, initial_delay, Node_ID: in integer; signal clk: in std_logic;
signal credit_out: out std_logic; signal valid_in: in std_logic; signal port_in: in std_logic_vector) is
-- initial_delay: waits for this number of clock cycles before sending the packet!
variable source_node, destination_node, P_length, packet_id, counter: integer;
variable LINEVARIABLE : line;
file VEC_FILE : text is out "received.txt";
file DIAGNOSIS_FILE : text is out "DIAGNOSIS.txt";
variable DIAGNOSIS: std_logic;
variable DIAGNOSIS_vector: std_logic_vector(12 downto 0);
begin
credit_out <= '1';
counter := 0;
while true loop
wait until clk'event and clk ='1';
if valid_in = '1' then
if (port_in(DATA_WIDTH-1 downto DATA_WIDTH-3) = "001") then
counter := 1;
DIAGNOSIS := '0';
source_node := to_integer(unsigned(port_in(28 downto 15)));
destination_node := to_integer(unsigned(port_in(14 downto 1)));
end if;
if (port_in(DATA_WIDTH-1 downto DATA_WIDTH-3) = "010") then
--report "flit type: " &integer'image(to_integer(unsigned(port_in(DATA_WIDTH-1 downto DATA_WIDTH-3)))) ;
--report "counter: " & integer'image(counter);
if counter = 1 then
P_length := to_integer(unsigned(port_in(28 downto 15)));
packet_id := to_integer(unsigned(port_in(15 downto 1)));
end if;
counter := counter+1;
if port_in(28 downto 13) = "0100011001000100" then
DIAGNOSIS := '1';
DIAGNOSIS_vector(11 downto 0) := port_in(12 downto 1);
end if;
end if;
if (port_in(DATA_WIDTH-1 downto DATA_WIDTH-3) = "100") then
counter := counter+1;
report "Node: " & integer'image(Node_ID) & " Packet received at " & time'image(now) & " From " & integer'image(source_node) & " to " & integer'image(destination_node) & " with length: "& integer'image(P_length) & " counter: "& integer'image(counter);
assert (P_length=counter) report "wrong packet size" severity warning;
assert (Node_ID=destination_node) report "wrong packet destination " severity failure;
if DIAGNOSIS = '1' then
DIAGNOSIS_vector(12) := port_in(28);
write(LINEVARIABLE, "Packet received at " & time'image(now) & " From: " & integer'image(source_node) & " to: " & integer'image(destination_node) & " length: "& integer'image(P_length) & " actual length: "& integer'image(counter) & " id: "& integer'image(packet_id));
writeline(DIAGNOSIS_FILE, LINEVARIABLE);
else
write(LINEVARIABLE, "Packet received at " & time'image(now) & " From: " & integer'image(source_node) & " to: " & integer'image(destination_node) & " length: "& integer'image(P_length) & " actual length: "& integer'image(counter) & " id: "& integer'image(packet_id));
writeline(VEC_FILE, LINEVARIABLE);
end if;
counter := 0;
end if;
end if;
end loop;
end get_packet;
end TB_Package;
|
architecture RTL of FIFO is
begin
FOR_LABEL : for i in 0 to 7 generate
end generate FOR_LABEL;
IF_LABEL : if a = '1' generate
end generate IF_LABEL;
CASE_LABEL : case data generate
end generate CASE_LABEL;
-- Violations below
FOR_LABEL : for i in 0 to 7 generate
end generate for_label;
IF_LABEL : if a = '1' generate
end generate if_label1;
CASE_LABEL : case data generate
end generate case_label;
end;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.3
-- IP Revision: 3
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY blk_mem_gen_v8_3_3;
USE blk_mem_gen_v8_3_3.blk_mem_gen_v8_3_3;
ENTITY sig1dualRAM IS
PORT (
clka : IN STD_LOGIC;
ena : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
clkb : IN STD_LOGIC;
enb : IN STD_LOGIC;
addrb : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END sig1dualRAM;
ARCHITECTURE sig1dualRAM_arch OF sig1dualRAM IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF sig1dualRAM_arch: ARCHITECTURE IS "yes";
COMPONENT blk_mem_gen_v8_3_3 IS
GENERIC (
C_FAMILY : STRING;
C_XDEVICEFAMILY : STRING;
C_ELABORATION_DIR : STRING;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_AXI_SLAVE_TYPE : INTEGER;
C_USE_BRAM_BLOCK : INTEGER;
C_ENABLE_32BIT_ADDRESS : INTEGER;
C_CTRL_ECC_ALGO : STRING;
C_HAS_AXI_ID : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_MEM_TYPE : INTEGER;
C_BYTE_SIZE : INTEGER;
C_ALGORITHM : INTEGER;
C_PRIM_TYPE : INTEGER;
C_LOAD_INIT_FILE : INTEGER;
C_INIT_FILE_NAME : STRING;
C_INIT_FILE : STRING;
C_USE_DEFAULT_DATA : INTEGER;
C_DEFAULT_DATA : STRING;
C_HAS_RSTA : INTEGER;
C_RST_PRIORITY_A : STRING;
C_RSTRAM_A : INTEGER;
C_INITA_VAL : STRING;
C_HAS_ENA : INTEGER;
C_HAS_REGCEA : INTEGER;
C_USE_BYTE_WEA : INTEGER;
C_WEA_WIDTH : INTEGER;
C_WRITE_MODE_A : STRING;
C_WRITE_WIDTH_A : INTEGER;
C_READ_WIDTH_A : INTEGER;
C_WRITE_DEPTH_A : INTEGER;
C_READ_DEPTH_A : INTEGER;
C_ADDRA_WIDTH : INTEGER;
C_HAS_RSTB : INTEGER;
C_RST_PRIORITY_B : STRING;
C_RSTRAM_B : INTEGER;
C_INITB_VAL : STRING;
C_HAS_ENB : INTEGER;
C_HAS_REGCEB : INTEGER;
C_USE_BYTE_WEB : INTEGER;
C_WEB_WIDTH : INTEGER;
C_WRITE_MODE_B : STRING;
C_WRITE_WIDTH_B : INTEGER;
C_READ_WIDTH_B : INTEGER;
C_WRITE_DEPTH_B : INTEGER;
C_READ_DEPTH_B : INTEGER;
C_ADDRB_WIDTH : INTEGER;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER;
C_MUX_PIPELINE_STAGES : INTEGER;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER;
C_USE_SOFTECC : INTEGER;
C_USE_ECC : INTEGER;
C_EN_ECC_PIPE : INTEGER;
C_HAS_INJECTERR : INTEGER;
C_SIM_COLLISION_CHECK : STRING;
C_COMMON_CLK : INTEGER;
C_DISABLE_WARN_BHV_COLL : INTEGER;
C_EN_SLEEP_PIN : INTEGER;
C_USE_URAM : INTEGER;
C_EN_RDADDRA_CHG : INTEGER;
C_EN_RDADDRB_CHG : INTEGER;
C_EN_DEEPSLEEP_PIN : INTEGER;
C_EN_SHUTDOWN_PIN : INTEGER;
C_EN_SAFETY_CKT : INTEGER;
C_DISABLE_WARN_BHV_RANGE : INTEGER;
C_COUNT_36K_BRAM : STRING;
C_COUNT_18K_BRAM : STRING;
C_EST_POWER_SUMMARY : STRING
);
PORT (
clka : IN STD_LOGIC;
rsta : IN STD_LOGIC;
ena : IN STD_LOGIC;
regcea : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
clkb : IN STD_LOGIC;
rstb : IN STD_LOGIC;
enb : IN STD_LOGIC;
regceb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
injectsbiterr : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
eccpipece : IN STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
rdaddrecc : OUT STD_LOGIC_VECTOR(13 DOWNTO 0);
sleep : IN STD_LOGIC;
deepsleep : IN STD_LOGIC;
shutdown : IN STD_LOGIC;
rsta_busy : OUT STD_LOGIC;
rstb_busy : OUT STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi_injectsbiterr : IN STD_LOGIC;
s_axi_injectdbiterr : IN STD_LOGIC;
s_axi_sbiterr : OUT STD_LOGIC;
s_axi_dbiterr : OUT STD_LOGIC;
s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(13 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_3_3;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF sig1dualRAM_arch: ARCHITECTURE IS "blk_mem_gen_v8_3_3,Vivado 2016.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF sig1dualRAM_arch : ARCHITECTURE IS "sig1dualRAM,blk_mem_gen_v8_3_3,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF sig1dualRAM_arch: ARCHITECTURE IS "sig1dualRAM,blk_mem_gen_v8_3_3,{x_ipProduct=Vivado 2016.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.3,x_ipCoreRevision=3,x_ipLanguage=VHDL,x_ipSimLanguage=VHDL,C_FAMILY=artix7,C_XDEVICEFAMILY=artix7,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=0,C_ENABLE_32BIT_ADDRESS=0,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=1,C_BYTE_SIZE=9,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=0,C_INIT_FILE_NAME=no_coe_file" &
"_loaded,C_INIT_FILE=sig1dualRAM.mem,C_USE_DEFAULT_DATA=0,C_DEFAULT_DATA=0,C_HAS_RSTA=0,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=1,C_HAS_REGCEA=0,C_USE_BYTE_WEA=0,C_WEA_WIDTH=1,C_WRITE_MODE_A=NO_CHANGE,C_WRITE_WIDTH_A=8,C_READ_WIDTH_A=8,C_WRITE_DEPTH_A=11520,C_READ_DEPTH_A=11520,C_ADDRA_WIDTH=14,C_HAS_RSTB=0,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=1,C_HAS_REGCEB=0,C_USE_BYTE_WEB=0,C_WEB_WIDTH=1,C_WRITE_MODE_B=WRITE_FIRST,C_WRITE_WIDTH_B=8,C_READ_WIDTH_B=8,C_WRITE_" &
"DEPTH_B=11520,C_READ_DEPTH_B=11520,C_ADDRB_WIDTH=14,C_HAS_MEM_OUTPUT_REGS_A=0,C_HAS_MEM_OUTPUT_REGS_B=1,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=0,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_USE_URAM=0,C_EN_RDADDRA_CHG=0,C_EN_RDADDRB_CHG=0,C_EN_DEEPSLEEP_PIN=0,C_EN_SHUTDOWN_PIN=0,C_EN_SAFETY_CKT=0,C_DIS" &
"ABLE_WARN_BHV_RANGE=0,C_COUNT_36K_BRAM=3,C_COUNT_18K_BRAM=0,C_EST_POWER_SUMMARY=Estimated Power for IP _ 4.53475 mW}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clka: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
ATTRIBUTE X_INTERFACE_INFO OF ena: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA EN";
ATTRIBUTE X_INTERFACE_INFO OF wea: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
ATTRIBUTE X_INTERFACE_INFO OF addra: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
ATTRIBUTE X_INTERFACE_INFO OF dina: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
ATTRIBUTE X_INTERFACE_INFO OF clkb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB CLK";
ATTRIBUTE X_INTERFACE_INFO OF enb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB EN";
ATTRIBUTE X_INTERFACE_INFO OF addrb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR";
ATTRIBUTE X_INTERFACE_INFO OF doutb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT";
BEGIN
U0 : blk_mem_gen_v8_3_3
GENERIC MAP (
C_FAMILY => "artix7",
C_XDEVICEFAMILY => "artix7",
C_ELABORATION_DIR => "./",
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_AXI_SLAVE_TYPE => 0,
C_USE_BRAM_BLOCK => 0,
C_ENABLE_32BIT_ADDRESS => 0,
C_CTRL_ECC_ALGO => "NONE",
C_HAS_AXI_ID => 0,
C_AXI_ID_WIDTH => 4,
C_MEM_TYPE => 1,
C_BYTE_SIZE => 9,
C_ALGORITHM => 1,
C_PRIM_TYPE => 1,
C_LOAD_INIT_FILE => 0,
C_INIT_FILE_NAME => "no_coe_file_loaded",
C_INIT_FILE => "sig1dualRAM.mem",
C_USE_DEFAULT_DATA => 0,
C_DEFAULT_DATA => "0",
C_HAS_RSTA => 0,
C_RST_PRIORITY_A => "CE",
C_RSTRAM_A => 0,
C_INITA_VAL => "0",
C_HAS_ENA => 1,
C_HAS_REGCEA => 0,
C_USE_BYTE_WEA => 0,
C_WEA_WIDTH => 1,
C_WRITE_MODE_A => "NO_CHANGE",
C_WRITE_WIDTH_A => 8,
C_READ_WIDTH_A => 8,
C_WRITE_DEPTH_A => 11520,
C_READ_DEPTH_A => 11520,
C_ADDRA_WIDTH => 14,
C_HAS_RSTB => 0,
C_RST_PRIORITY_B => "CE",
C_RSTRAM_B => 0,
C_INITB_VAL => "0",
C_HAS_ENB => 1,
C_HAS_REGCEB => 0,
C_USE_BYTE_WEB => 0,
C_WEB_WIDTH => 1,
C_WRITE_MODE_B => "WRITE_FIRST",
C_WRITE_WIDTH_B => 8,
C_READ_WIDTH_B => 8,
C_WRITE_DEPTH_B => 11520,
C_READ_DEPTH_B => 11520,
C_ADDRB_WIDTH => 14,
C_HAS_MEM_OUTPUT_REGS_A => 0,
C_HAS_MEM_OUTPUT_REGS_B => 1,
C_HAS_MUX_OUTPUT_REGS_A => 0,
C_HAS_MUX_OUTPUT_REGS_B => 0,
C_MUX_PIPELINE_STAGES => 0,
C_HAS_SOFTECC_INPUT_REGS_A => 0,
C_HAS_SOFTECC_OUTPUT_REGS_B => 0,
C_USE_SOFTECC => 0,
C_USE_ECC => 0,
C_EN_ECC_PIPE => 0,
C_HAS_INJECTERR => 0,
C_SIM_COLLISION_CHECK => "ALL",
C_COMMON_CLK => 0,
C_DISABLE_WARN_BHV_COLL => 0,
C_EN_SLEEP_PIN => 0,
C_USE_URAM => 0,
C_EN_RDADDRA_CHG => 0,
C_EN_RDADDRB_CHG => 0,
C_EN_DEEPSLEEP_PIN => 0,
C_EN_SHUTDOWN_PIN => 0,
C_EN_SAFETY_CKT => 0,
C_DISABLE_WARN_BHV_RANGE => 0,
C_COUNT_36K_BRAM => "3",
C_COUNT_18K_BRAM => "0",
C_EST_POWER_SUMMARY => "Estimated Power for IP : 4.53475 mW"
)
PORT MAP (
clka => clka,
rsta => '0',
ena => ena,
regcea => '0',
wea => wea,
addra => addra,
dina => dina,
clkb => clkb,
rstb => '0',
enb => enb,
regceb => '0',
web => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
addrb => addrb,
dinb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
doutb => doutb,
injectsbiterr => '0',
injectdbiterr => '0',
eccpipece => '0',
sleep => '0',
deepsleep => '0',
shutdown => '0',
s_aclk => '0',
s_aresetn => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awvalid => '0',
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wlast => '0',
s_axi_wvalid => '0',
s_axi_bready => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arvalid => '0',
s_axi_rready => '0',
s_axi_injectsbiterr => '0',
s_axi_injectdbiterr => '0'
);
END sig1dualRAM_arch;
|
clockbuzzer1k_inst : clockbuzzer1k PORT MAP (
clock => clock_sig,
cout => cout_sig,
q => q_sig
);
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc788.vhd,v 1.2 2001-10-26 16:30:27 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c01s01b02x00p03n01i00788ent IS
entity illegal is -- entity illegal here
end illegal;
END c01s01b02x00p03n01i00788ent;
ARCHITECTURE c01s01b02x00p03n01i00788arch OF c01s01b02x00p03n01i00788ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c01s01b02x00p03n01i00788 - Entity declarations are not permitted in an entity declaration."
severity ERROR;
wait;
END PROCESS TESTING;
END c01s01b02x00p03n01i00788arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc788.vhd,v 1.2 2001-10-26 16:30:27 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c01s01b02x00p03n01i00788ent IS
entity illegal is -- entity illegal here
end illegal;
END c01s01b02x00p03n01i00788ent;
ARCHITECTURE c01s01b02x00p03n01i00788arch OF c01s01b02x00p03n01i00788ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c01s01b02x00p03n01i00788 - Entity declarations are not permitted in an entity declaration."
severity ERROR;
wait;
END PROCESS TESTING;
END c01s01b02x00p03n01i00788arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc788.vhd,v 1.2 2001-10-26 16:30:27 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c01s01b02x00p03n01i00788ent IS
entity illegal is -- entity illegal here
end illegal;
END c01s01b02x00p03n01i00788ent;
ARCHITECTURE c01s01b02x00p03n01i00788arch OF c01s01b02x00p03n01i00788ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c01s01b02x00p03n01i00788 - Entity declarations are not permitted in an entity declaration."
severity ERROR;
wait;
END PROCESS TESTING;
END c01s01b02x00p03n01i00788arch;
|
entity test is
end test;
architecture only of test is
type small is range 1 to 3;
begin -- only
p: process
begin -- process p
assert small'pred(2) = 1 report "TEST FAILED. pred 2 = 1" severity FAILURE;
report "TEST PASSED pred 2 = 1" severity NOTE;
assert small'pred(3) = 2 report "TEST FAILED. pred 3 = 2" severity FAILURE;
report "TEST PASSED pred 3 = 2" severity NOTE;
wait;
end process p;
end only;
|
entity test is
end test;
architecture only of test is
type small is range 1 to 3;
begin -- only
p: process
begin -- process p
assert small'pred(2) = 1 report "TEST FAILED. pred 2 = 1" severity FAILURE;
report "TEST PASSED pred 2 = 1" severity NOTE;
assert small'pred(3) = 2 report "TEST FAILED. pred 3 = 2" severity FAILURE;
report "TEST PASSED pred 3 = 2" severity NOTE;
wait;
end process p;
end only;
|
entity test is
end test;
architecture only of test is
type small is range 1 to 3;
begin -- only
p: process
begin -- process p
assert small'pred(2) = 1 report "TEST FAILED. pred 2 = 1" severity FAILURE;
report "TEST PASSED pred 2 = 1" severity NOTE;
assert small'pred(3) = 2 report "TEST FAILED. pred 3 = 2" severity FAILURE;
report "TEST PASSED pred 3 = 2" severity NOTE;
wait;
end process p;
end only;
|
architecture rtl of fifo is
begin
procedure_call_label : postponed wr_en(a, b);
PROCEDURE_CALL_LABEL : postponed wr_en(a, b);
process_label : process
begin
procedure_call_label : wr_en(a, b);
PROCEDURE_CALL_LABEL : wr_en(a, b);
end process;
end architecture rtl;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.2
-- IP Revision: 4
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY blk_mem_gen_v8_2;
USE blk_mem_gen_v8_2.blk_mem_gen_v8_2;
ENTITY SDPRAM_16A9024X32B4512 IS
PORT (
clka : IN STD_LOGIC;
ena : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
clkb : IN STD_LOGIC;
enb : IN STD_LOGIC;
addrb : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END SDPRAM_16A9024X32B4512;
ARCHITECTURE SDPRAM_16A9024X32B4512_arch OF SDPRAM_16A9024X32B4512 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF SDPRAM_16A9024X32B4512_arch: ARCHITECTURE IS "yes";
COMPONENT blk_mem_gen_v8_2 IS
GENERIC (
C_FAMILY : STRING;
C_XDEVICEFAMILY : STRING;
C_ELABORATION_DIR : STRING;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_AXI_SLAVE_TYPE : INTEGER;
C_USE_BRAM_BLOCK : INTEGER;
C_ENABLE_32BIT_ADDRESS : INTEGER;
C_CTRL_ECC_ALGO : STRING;
C_HAS_AXI_ID : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_MEM_TYPE : INTEGER;
C_BYTE_SIZE : INTEGER;
C_ALGORITHM : INTEGER;
C_PRIM_TYPE : INTEGER;
C_LOAD_INIT_FILE : INTEGER;
C_INIT_FILE_NAME : STRING;
C_INIT_FILE : STRING;
C_USE_DEFAULT_DATA : INTEGER;
C_DEFAULT_DATA : STRING;
C_HAS_RSTA : INTEGER;
C_RST_PRIORITY_A : STRING;
C_RSTRAM_A : INTEGER;
C_INITA_VAL : STRING;
C_HAS_ENA : INTEGER;
C_HAS_REGCEA : INTEGER;
C_USE_BYTE_WEA : INTEGER;
C_WEA_WIDTH : INTEGER;
C_WRITE_MODE_A : STRING;
C_WRITE_WIDTH_A : INTEGER;
C_READ_WIDTH_A : INTEGER;
C_WRITE_DEPTH_A : INTEGER;
C_READ_DEPTH_A : INTEGER;
C_ADDRA_WIDTH : INTEGER;
C_HAS_RSTB : INTEGER;
C_RST_PRIORITY_B : STRING;
C_RSTRAM_B : INTEGER;
C_INITB_VAL : STRING;
C_HAS_ENB : INTEGER;
C_HAS_REGCEB : INTEGER;
C_USE_BYTE_WEB : INTEGER;
C_WEB_WIDTH : INTEGER;
C_WRITE_MODE_B : STRING;
C_WRITE_WIDTH_B : INTEGER;
C_READ_WIDTH_B : INTEGER;
C_WRITE_DEPTH_B : INTEGER;
C_READ_DEPTH_B : INTEGER;
C_ADDRB_WIDTH : INTEGER;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER;
C_MUX_PIPELINE_STAGES : INTEGER;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER;
C_USE_SOFTECC : INTEGER;
C_USE_ECC : INTEGER;
C_EN_ECC_PIPE : INTEGER;
C_HAS_INJECTERR : INTEGER;
C_SIM_COLLISION_CHECK : STRING;
C_COMMON_CLK : INTEGER;
C_DISABLE_WARN_BHV_COLL : INTEGER;
C_EN_SLEEP_PIN : INTEGER;
C_DISABLE_WARN_BHV_RANGE : INTEGER;
C_COUNT_36K_BRAM : STRING;
C_COUNT_18K_BRAM : STRING;
C_EST_POWER_SUMMARY : STRING
);
PORT (
clka : IN STD_LOGIC;
rsta : IN STD_LOGIC;
ena : IN STD_LOGIC;
regcea : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
clkb : IN STD_LOGIC;
rstb : IN STD_LOGIC;
enb : IN STD_LOGIC;
regceb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
injectsbiterr : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
eccpipece : IN STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
rdaddrecc : OUT STD_LOGIC_VECTOR(12 DOWNTO 0);
sleep : IN STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi_injectsbiterr : IN STD_LOGIC;
s_axi_injectdbiterr : IN STD_LOGIC;
s_axi_sbiterr : OUT STD_LOGIC;
s_axi_dbiterr : OUT STD_LOGIC;
s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(12 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_2;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF SDPRAM_16A9024X32B4512_arch: ARCHITECTURE IS "blk_mem_gen_v8_2,Vivado 2014.4.1";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF SDPRAM_16A9024X32B4512_arch : ARCHITECTURE IS "SDPRAM_16A9024X32B4512,blk_mem_gen_v8_2,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF SDPRAM_16A9024X32B4512_arch: ARCHITECTURE IS "SDPRAM_16A9024X32B4512,blk_mem_gen_v8_2,{x_ipProduct=Vivado 2014.4.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.2,x_ipCoreRevision=4,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_XDEVICEFAMILY=zynq,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=0,C_ENABLE_32BIT_ADDRESS=0,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=1,C_BYTE_SIZE=9,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=0,C_INIT_FILE_NAME=no_coe_file_loaded,C_INIT_FILE=SDPRAM_16A9024X32B4512.mem,C_USE_DEFAULT_DATA=0,C_DEFAULT_DATA=0,C_HAS_RSTA=0,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=1,C_HAS_REGCEA=0,C_USE_BYTE_WEA=0,C_WEA_WIDTH=1,C_WRITE_MODE_A=NO_CHANGE,C_WRITE_WIDTH_A=16,C_READ_WIDTH_A=16,C_WRITE_DEPTH_A=9024,C_READ_DEPTH_A=9024,C_ADDRA_WIDTH=14,C_HAS_RSTB=0,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=1,C_HAS_REGCEB=0,C_USE_BYTE_WEB=0,C_WEB_WIDTH=1,C_WRITE_MODE_B=READ_FIRST,C_WRITE_WIDTH_B=32,C_READ_WIDTH_B=32,C_WRITE_DEPTH_B=4512,C_READ_DEPTH_B=4512,C_ADDRB_WIDTH=13,C_HAS_MEM_OUTPUT_REGS_A=0,C_HAS_MEM_OUTPUT_REGS_B=0,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=1,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_DISABLE_WARN_BHV_RANGE=0,C_COUNT_36K_BRAM=4,C_COUNT_18K_BRAM=1,C_EST_POWER_SUMMARY=Estimated Power for IP _ 8.9942449999999994 mW}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clka: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
ATTRIBUTE X_INTERFACE_INFO OF ena: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA EN";
ATTRIBUTE X_INTERFACE_INFO OF wea: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
ATTRIBUTE X_INTERFACE_INFO OF addra: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
ATTRIBUTE X_INTERFACE_INFO OF dina: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
ATTRIBUTE X_INTERFACE_INFO OF clkb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB CLK";
ATTRIBUTE X_INTERFACE_INFO OF enb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB EN";
ATTRIBUTE X_INTERFACE_INFO OF addrb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR";
ATTRIBUTE X_INTERFACE_INFO OF doutb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT";
BEGIN
U0 : blk_mem_gen_v8_2
GENERIC MAP (
C_FAMILY => "zynq",
C_XDEVICEFAMILY => "zynq",
C_ELABORATION_DIR => "./",
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_AXI_SLAVE_TYPE => 0,
C_USE_BRAM_BLOCK => 0,
C_ENABLE_32BIT_ADDRESS => 0,
C_CTRL_ECC_ALGO => "NONE",
C_HAS_AXI_ID => 0,
C_AXI_ID_WIDTH => 4,
C_MEM_TYPE => 1,
C_BYTE_SIZE => 9,
C_ALGORITHM => 1,
C_PRIM_TYPE => 1,
C_LOAD_INIT_FILE => 0,
C_INIT_FILE_NAME => "no_coe_file_loaded",
C_INIT_FILE => "SDPRAM_16A9024X32B4512.mem",
C_USE_DEFAULT_DATA => 0,
C_DEFAULT_DATA => "0",
C_HAS_RSTA => 0,
C_RST_PRIORITY_A => "CE",
C_RSTRAM_A => 0,
C_INITA_VAL => "0",
C_HAS_ENA => 1,
C_HAS_REGCEA => 0,
C_USE_BYTE_WEA => 0,
C_WEA_WIDTH => 1,
C_WRITE_MODE_A => "NO_CHANGE",
C_WRITE_WIDTH_A => 16,
C_READ_WIDTH_A => 16,
C_WRITE_DEPTH_A => 9024,
C_READ_DEPTH_A => 9024,
C_ADDRA_WIDTH => 14,
C_HAS_RSTB => 0,
C_RST_PRIORITY_B => "CE",
C_RSTRAM_B => 0,
C_INITB_VAL => "0",
C_HAS_ENB => 1,
C_HAS_REGCEB => 0,
C_USE_BYTE_WEB => 0,
C_WEB_WIDTH => 1,
C_WRITE_MODE_B => "READ_FIRST",
C_WRITE_WIDTH_B => 32,
C_READ_WIDTH_B => 32,
C_WRITE_DEPTH_B => 4512,
C_READ_DEPTH_B => 4512,
C_ADDRB_WIDTH => 13,
C_HAS_MEM_OUTPUT_REGS_A => 0,
C_HAS_MEM_OUTPUT_REGS_B => 0,
C_HAS_MUX_OUTPUT_REGS_A => 0,
C_HAS_MUX_OUTPUT_REGS_B => 0,
C_MUX_PIPELINE_STAGES => 0,
C_HAS_SOFTECC_INPUT_REGS_A => 0,
C_HAS_SOFTECC_OUTPUT_REGS_B => 0,
C_USE_SOFTECC => 0,
C_USE_ECC => 0,
C_EN_ECC_PIPE => 0,
C_HAS_INJECTERR => 0,
C_SIM_COLLISION_CHECK => "ALL",
C_COMMON_CLK => 1,
C_DISABLE_WARN_BHV_COLL => 0,
C_EN_SLEEP_PIN => 0,
C_DISABLE_WARN_BHV_RANGE => 0,
C_COUNT_36K_BRAM => "4",
C_COUNT_18K_BRAM => "1",
C_EST_POWER_SUMMARY => "Estimated Power for IP : 8.9942449999999994 mW"
)
PORT MAP (
clka => clka,
rsta => '0',
ena => ena,
regcea => '0',
wea => wea,
addra => addra,
dina => dina,
clkb => clkb,
rstb => '0',
enb => enb,
regceb => '0',
web => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
addrb => addrb,
dinb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
doutb => doutb,
injectsbiterr => '0',
injectdbiterr => '0',
eccpipece => '0',
sleep => '0',
s_aclk => '0',
s_aresetn => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awvalid => '0',
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 16)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wlast => '0',
s_axi_wvalid => '0',
s_axi_bready => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arvalid => '0',
s_axi_rready => '0',
s_axi_injectsbiterr => '0',
s_axi_injectdbiterr => '0'
);
END SDPRAM_16A9024X32B4512_arch;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.2
-- IP Revision: 4
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY blk_mem_gen_v8_2;
USE blk_mem_gen_v8_2.blk_mem_gen_v8_2;
ENTITY SDPRAM_16A9024X32B4512 IS
PORT (
clka : IN STD_LOGIC;
ena : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
clkb : IN STD_LOGIC;
enb : IN STD_LOGIC;
addrb : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END SDPRAM_16A9024X32B4512;
ARCHITECTURE SDPRAM_16A9024X32B4512_arch OF SDPRAM_16A9024X32B4512 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF SDPRAM_16A9024X32B4512_arch: ARCHITECTURE IS "yes";
COMPONENT blk_mem_gen_v8_2 IS
GENERIC (
C_FAMILY : STRING;
C_XDEVICEFAMILY : STRING;
C_ELABORATION_DIR : STRING;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_AXI_SLAVE_TYPE : INTEGER;
C_USE_BRAM_BLOCK : INTEGER;
C_ENABLE_32BIT_ADDRESS : INTEGER;
C_CTRL_ECC_ALGO : STRING;
C_HAS_AXI_ID : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_MEM_TYPE : INTEGER;
C_BYTE_SIZE : INTEGER;
C_ALGORITHM : INTEGER;
C_PRIM_TYPE : INTEGER;
C_LOAD_INIT_FILE : INTEGER;
C_INIT_FILE_NAME : STRING;
C_INIT_FILE : STRING;
C_USE_DEFAULT_DATA : INTEGER;
C_DEFAULT_DATA : STRING;
C_HAS_RSTA : INTEGER;
C_RST_PRIORITY_A : STRING;
C_RSTRAM_A : INTEGER;
C_INITA_VAL : STRING;
C_HAS_ENA : INTEGER;
C_HAS_REGCEA : INTEGER;
C_USE_BYTE_WEA : INTEGER;
C_WEA_WIDTH : INTEGER;
C_WRITE_MODE_A : STRING;
C_WRITE_WIDTH_A : INTEGER;
C_READ_WIDTH_A : INTEGER;
C_WRITE_DEPTH_A : INTEGER;
C_READ_DEPTH_A : INTEGER;
C_ADDRA_WIDTH : INTEGER;
C_HAS_RSTB : INTEGER;
C_RST_PRIORITY_B : STRING;
C_RSTRAM_B : INTEGER;
C_INITB_VAL : STRING;
C_HAS_ENB : INTEGER;
C_HAS_REGCEB : INTEGER;
C_USE_BYTE_WEB : INTEGER;
C_WEB_WIDTH : INTEGER;
C_WRITE_MODE_B : STRING;
C_WRITE_WIDTH_B : INTEGER;
C_READ_WIDTH_B : INTEGER;
C_WRITE_DEPTH_B : INTEGER;
C_READ_DEPTH_B : INTEGER;
C_ADDRB_WIDTH : INTEGER;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER;
C_MUX_PIPELINE_STAGES : INTEGER;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER;
C_USE_SOFTECC : INTEGER;
C_USE_ECC : INTEGER;
C_EN_ECC_PIPE : INTEGER;
C_HAS_INJECTERR : INTEGER;
C_SIM_COLLISION_CHECK : STRING;
C_COMMON_CLK : INTEGER;
C_DISABLE_WARN_BHV_COLL : INTEGER;
C_EN_SLEEP_PIN : INTEGER;
C_DISABLE_WARN_BHV_RANGE : INTEGER;
C_COUNT_36K_BRAM : STRING;
C_COUNT_18K_BRAM : STRING;
C_EST_POWER_SUMMARY : STRING
);
PORT (
clka : IN STD_LOGIC;
rsta : IN STD_LOGIC;
ena : IN STD_LOGIC;
regcea : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
clkb : IN STD_LOGIC;
rstb : IN STD_LOGIC;
enb : IN STD_LOGIC;
regceb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
injectsbiterr : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
eccpipece : IN STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
rdaddrecc : OUT STD_LOGIC_VECTOR(12 DOWNTO 0);
sleep : IN STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi_injectsbiterr : IN STD_LOGIC;
s_axi_injectdbiterr : IN STD_LOGIC;
s_axi_sbiterr : OUT STD_LOGIC;
s_axi_dbiterr : OUT STD_LOGIC;
s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(12 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_2;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF SDPRAM_16A9024X32B4512_arch: ARCHITECTURE IS "blk_mem_gen_v8_2,Vivado 2014.4.1";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF SDPRAM_16A9024X32B4512_arch : ARCHITECTURE IS "SDPRAM_16A9024X32B4512,blk_mem_gen_v8_2,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF SDPRAM_16A9024X32B4512_arch: ARCHITECTURE IS "SDPRAM_16A9024X32B4512,blk_mem_gen_v8_2,{x_ipProduct=Vivado 2014.4.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.2,x_ipCoreRevision=4,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_XDEVICEFAMILY=zynq,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=0,C_ENABLE_32BIT_ADDRESS=0,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=1,C_BYTE_SIZE=9,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=0,C_INIT_FILE_NAME=no_coe_file_loaded,C_INIT_FILE=SDPRAM_16A9024X32B4512.mem,C_USE_DEFAULT_DATA=0,C_DEFAULT_DATA=0,C_HAS_RSTA=0,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=1,C_HAS_REGCEA=0,C_USE_BYTE_WEA=0,C_WEA_WIDTH=1,C_WRITE_MODE_A=NO_CHANGE,C_WRITE_WIDTH_A=16,C_READ_WIDTH_A=16,C_WRITE_DEPTH_A=9024,C_READ_DEPTH_A=9024,C_ADDRA_WIDTH=14,C_HAS_RSTB=0,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=1,C_HAS_REGCEB=0,C_USE_BYTE_WEB=0,C_WEB_WIDTH=1,C_WRITE_MODE_B=READ_FIRST,C_WRITE_WIDTH_B=32,C_READ_WIDTH_B=32,C_WRITE_DEPTH_B=4512,C_READ_DEPTH_B=4512,C_ADDRB_WIDTH=13,C_HAS_MEM_OUTPUT_REGS_A=0,C_HAS_MEM_OUTPUT_REGS_B=0,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=1,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_DISABLE_WARN_BHV_RANGE=0,C_COUNT_36K_BRAM=4,C_COUNT_18K_BRAM=1,C_EST_POWER_SUMMARY=Estimated Power for IP _ 8.9942449999999994 mW}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clka: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
ATTRIBUTE X_INTERFACE_INFO OF ena: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA EN";
ATTRIBUTE X_INTERFACE_INFO OF wea: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
ATTRIBUTE X_INTERFACE_INFO OF addra: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
ATTRIBUTE X_INTERFACE_INFO OF dina: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
ATTRIBUTE X_INTERFACE_INFO OF clkb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB CLK";
ATTRIBUTE X_INTERFACE_INFO OF enb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB EN";
ATTRIBUTE X_INTERFACE_INFO OF addrb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR";
ATTRIBUTE X_INTERFACE_INFO OF doutb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT";
BEGIN
U0 : blk_mem_gen_v8_2
GENERIC MAP (
C_FAMILY => "zynq",
C_XDEVICEFAMILY => "zynq",
C_ELABORATION_DIR => "./",
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_AXI_SLAVE_TYPE => 0,
C_USE_BRAM_BLOCK => 0,
C_ENABLE_32BIT_ADDRESS => 0,
C_CTRL_ECC_ALGO => "NONE",
C_HAS_AXI_ID => 0,
C_AXI_ID_WIDTH => 4,
C_MEM_TYPE => 1,
C_BYTE_SIZE => 9,
C_ALGORITHM => 1,
C_PRIM_TYPE => 1,
C_LOAD_INIT_FILE => 0,
C_INIT_FILE_NAME => "no_coe_file_loaded",
C_INIT_FILE => "SDPRAM_16A9024X32B4512.mem",
C_USE_DEFAULT_DATA => 0,
C_DEFAULT_DATA => "0",
C_HAS_RSTA => 0,
C_RST_PRIORITY_A => "CE",
C_RSTRAM_A => 0,
C_INITA_VAL => "0",
C_HAS_ENA => 1,
C_HAS_REGCEA => 0,
C_USE_BYTE_WEA => 0,
C_WEA_WIDTH => 1,
C_WRITE_MODE_A => "NO_CHANGE",
C_WRITE_WIDTH_A => 16,
C_READ_WIDTH_A => 16,
C_WRITE_DEPTH_A => 9024,
C_READ_DEPTH_A => 9024,
C_ADDRA_WIDTH => 14,
C_HAS_RSTB => 0,
C_RST_PRIORITY_B => "CE",
C_RSTRAM_B => 0,
C_INITB_VAL => "0",
C_HAS_ENB => 1,
C_HAS_REGCEB => 0,
C_USE_BYTE_WEB => 0,
C_WEB_WIDTH => 1,
C_WRITE_MODE_B => "READ_FIRST",
C_WRITE_WIDTH_B => 32,
C_READ_WIDTH_B => 32,
C_WRITE_DEPTH_B => 4512,
C_READ_DEPTH_B => 4512,
C_ADDRB_WIDTH => 13,
C_HAS_MEM_OUTPUT_REGS_A => 0,
C_HAS_MEM_OUTPUT_REGS_B => 0,
C_HAS_MUX_OUTPUT_REGS_A => 0,
C_HAS_MUX_OUTPUT_REGS_B => 0,
C_MUX_PIPELINE_STAGES => 0,
C_HAS_SOFTECC_INPUT_REGS_A => 0,
C_HAS_SOFTECC_OUTPUT_REGS_B => 0,
C_USE_SOFTECC => 0,
C_USE_ECC => 0,
C_EN_ECC_PIPE => 0,
C_HAS_INJECTERR => 0,
C_SIM_COLLISION_CHECK => "ALL",
C_COMMON_CLK => 1,
C_DISABLE_WARN_BHV_COLL => 0,
C_EN_SLEEP_PIN => 0,
C_DISABLE_WARN_BHV_RANGE => 0,
C_COUNT_36K_BRAM => "4",
C_COUNT_18K_BRAM => "1",
C_EST_POWER_SUMMARY => "Estimated Power for IP : 8.9942449999999994 mW"
)
PORT MAP (
clka => clka,
rsta => '0',
ena => ena,
regcea => '0',
wea => wea,
addra => addra,
dina => dina,
clkb => clkb,
rstb => '0',
enb => enb,
regceb => '0',
web => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
addrb => addrb,
dinb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
doutb => doutb,
injectsbiterr => '0',
injectdbiterr => '0',
eccpipece => '0',
sleep => '0',
s_aclk => '0',
s_aresetn => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awvalid => '0',
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 16)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wlast => '0',
s_axi_wvalid => '0',
s_axi_bready => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arvalid => '0',
s_axi_rready => '0',
s_axi_injectsbiterr => '0',
s_axi_injectdbiterr => '0'
);
END SDPRAM_16A9024X32B4512_arch;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.2
-- IP Revision: 4
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY blk_mem_gen_v8_2;
USE blk_mem_gen_v8_2.blk_mem_gen_v8_2;
ENTITY SDPRAM_16A9024X32B4512 IS
PORT (
clka : IN STD_LOGIC;
ena : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
clkb : IN STD_LOGIC;
enb : IN STD_LOGIC;
addrb : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END SDPRAM_16A9024X32B4512;
ARCHITECTURE SDPRAM_16A9024X32B4512_arch OF SDPRAM_16A9024X32B4512 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF SDPRAM_16A9024X32B4512_arch: ARCHITECTURE IS "yes";
COMPONENT blk_mem_gen_v8_2 IS
GENERIC (
C_FAMILY : STRING;
C_XDEVICEFAMILY : STRING;
C_ELABORATION_DIR : STRING;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_AXI_SLAVE_TYPE : INTEGER;
C_USE_BRAM_BLOCK : INTEGER;
C_ENABLE_32BIT_ADDRESS : INTEGER;
C_CTRL_ECC_ALGO : STRING;
C_HAS_AXI_ID : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_MEM_TYPE : INTEGER;
C_BYTE_SIZE : INTEGER;
C_ALGORITHM : INTEGER;
C_PRIM_TYPE : INTEGER;
C_LOAD_INIT_FILE : INTEGER;
C_INIT_FILE_NAME : STRING;
C_INIT_FILE : STRING;
C_USE_DEFAULT_DATA : INTEGER;
C_DEFAULT_DATA : STRING;
C_HAS_RSTA : INTEGER;
C_RST_PRIORITY_A : STRING;
C_RSTRAM_A : INTEGER;
C_INITA_VAL : STRING;
C_HAS_ENA : INTEGER;
C_HAS_REGCEA : INTEGER;
C_USE_BYTE_WEA : INTEGER;
C_WEA_WIDTH : INTEGER;
C_WRITE_MODE_A : STRING;
C_WRITE_WIDTH_A : INTEGER;
C_READ_WIDTH_A : INTEGER;
C_WRITE_DEPTH_A : INTEGER;
C_READ_DEPTH_A : INTEGER;
C_ADDRA_WIDTH : INTEGER;
C_HAS_RSTB : INTEGER;
C_RST_PRIORITY_B : STRING;
C_RSTRAM_B : INTEGER;
C_INITB_VAL : STRING;
C_HAS_ENB : INTEGER;
C_HAS_REGCEB : INTEGER;
C_USE_BYTE_WEB : INTEGER;
C_WEB_WIDTH : INTEGER;
C_WRITE_MODE_B : STRING;
C_WRITE_WIDTH_B : INTEGER;
C_READ_WIDTH_B : INTEGER;
C_WRITE_DEPTH_B : INTEGER;
C_READ_DEPTH_B : INTEGER;
C_ADDRB_WIDTH : INTEGER;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER;
C_MUX_PIPELINE_STAGES : INTEGER;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER;
C_USE_SOFTECC : INTEGER;
C_USE_ECC : INTEGER;
C_EN_ECC_PIPE : INTEGER;
C_HAS_INJECTERR : INTEGER;
C_SIM_COLLISION_CHECK : STRING;
C_COMMON_CLK : INTEGER;
C_DISABLE_WARN_BHV_COLL : INTEGER;
C_EN_SLEEP_PIN : INTEGER;
C_DISABLE_WARN_BHV_RANGE : INTEGER;
C_COUNT_36K_BRAM : STRING;
C_COUNT_18K_BRAM : STRING;
C_EST_POWER_SUMMARY : STRING
);
PORT (
clka : IN STD_LOGIC;
rsta : IN STD_LOGIC;
ena : IN STD_LOGIC;
regcea : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
clkb : IN STD_LOGIC;
rstb : IN STD_LOGIC;
enb : IN STD_LOGIC;
regceb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
injectsbiterr : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
eccpipece : IN STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
rdaddrecc : OUT STD_LOGIC_VECTOR(12 DOWNTO 0);
sleep : IN STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi_injectsbiterr : IN STD_LOGIC;
s_axi_injectdbiterr : IN STD_LOGIC;
s_axi_sbiterr : OUT STD_LOGIC;
s_axi_dbiterr : OUT STD_LOGIC;
s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(12 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_2;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF SDPRAM_16A9024X32B4512_arch: ARCHITECTURE IS "blk_mem_gen_v8_2,Vivado 2014.4.1";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF SDPRAM_16A9024X32B4512_arch : ARCHITECTURE IS "SDPRAM_16A9024X32B4512,blk_mem_gen_v8_2,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF SDPRAM_16A9024X32B4512_arch: ARCHITECTURE IS "SDPRAM_16A9024X32B4512,blk_mem_gen_v8_2,{x_ipProduct=Vivado 2014.4.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.2,x_ipCoreRevision=4,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_XDEVICEFAMILY=zynq,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=0,C_ENABLE_32BIT_ADDRESS=0,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=1,C_BYTE_SIZE=9,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=0,C_INIT_FILE_NAME=no_coe_file_loaded,C_INIT_FILE=SDPRAM_16A9024X32B4512.mem,C_USE_DEFAULT_DATA=0,C_DEFAULT_DATA=0,C_HAS_RSTA=0,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=1,C_HAS_REGCEA=0,C_USE_BYTE_WEA=0,C_WEA_WIDTH=1,C_WRITE_MODE_A=NO_CHANGE,C_WRITE_WIDTH_A=16,C_READ_WIDTH_A=16,C_WRITE_DEPTH_A=9024,C_READ_DEPTH_A=9024,C_ADDRA_WIDTH=14,C_HAS_RSTB=0,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=1,C_HAS_REGCEB=0,C_USE_BYTE_WEB=0,C_WEB_WIDTH=1,C_WRITE_MODE_B=READ_FIRST,C_WRITE_WIDTH_B=32,C_READ_WIDTH_B=32,C_WRITE_DEPTH_B=4512,C_READ_DEPTH_B=4512,C_ADDRB_WIDTH=13,C_HAS_MEM_OUTPUT_REGS_A=0,C_HAS_MEM_OUTPUT_REGS_B=0,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=1,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_DISABLE_WARN_BHV_RANGE=0,C_COUNT_36K_BRAM=4,C_COUNT_18K_BRAM=1,C_EST_POWER_SUMMARY=Estimated Power for IP _ 8.9942449999999994 mW}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clka: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
ATTRIBUTE X_INTERFACE_INFO OF ena: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA EN";
ATTRIBUTE X_INTERFACE_INFO OF wea: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
ATTRIBUTE X_INTERFACE_INFO OF addra: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
ATTRIBUTE X_INTERFACE_INFO OF dina: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
ATTRIBUTE X_INTERFACE_INFO OF clkb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB CLK";
ATTRIBUTE X_INTERFACE_INFO OF enb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB EN";
ATTRIBUTE X_INTERFACE_INFO OF addrb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR";
ATTRIBUTE X_INTERFACE_INFO OF doutb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT";
BEGIN
U0 : blk_mem_gen_v8_2
GENERIC MAP (
C_FAMILY => "zynq",
C_XDEVICEFAMILY => "zynq",
C_ELABORATION_DIR => "./",
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_AXI_SLAVE_TYPE => 0,
C_USE_BRAM_BLOCK => 0,
C_ENABLE_32BIT_ADDRESS => 0,
C_CTRL_ECC_ALGO => "NONE",
C_HAS_AXI_ID => 0,
C_AXI_ID_WIDTH => 4,
C_MEM_TYPE => 1,
C_BYTE_SIZE => 9,
C_ALGORITHM => 1,
C_PRIM_TYPE => 1,
C_LOAD_INIT_FILE => 0,
C_INIT_FILE_NAME => "no_coe_file_loaded",
C_INIT_FILE => "SDPRAM_16A9024X32B4512.mem",
C_USE_DEFAULT_DATA => 0,
C_DEFAULT_DATA => "0",
C_HAS_RSTA => 0,
C_RST_PRIORITY_A => "CE",
C_RSTRAM_A => 0,
C_INITA_VAL => "0",
C_HAS_ENA => 1,
C_HAS_REGCEA => 0,
C_USE_BYTE_WEA => 0,
C_WEA_WIDTH => 1,
C_WRITE_MODE_A => "NO_CHANGE",
C_WRITE_WIDTH_A => 16,
C_READ_WIDTH_A => 16,
C_WRITE_DEPTH_A => 9024,
C_READ_DEPTH_A => 9024,
C_ADDRA_WIDTH => 14,
C_HAS_RSTB => 0,
C_RST_PRIORITY_B => "CE",
C_RSTRAM_B => 0,
C_INITB_VAL => "0",
C_HAS_ENB => 1,
C_HAS_REGCEB => 0,
C_USE_BYTE_WEB => 0,
C_WEB_WIDTH => 1,
C_WRITE_MODE_B => "READ_FIRST",
C_WRITE_WIDTH_B => 32,
C_READ_WIDTH_B => 32,
C_WRITE_DEPTH_B => 4512,
C_READ_DEPTH_B => 4512,
C_ADDRB_WIDTH => 13,
C_HAS_MEM_OUTPUT_REGS_A => 0,
C_HAS_MEM_OUTPUT_REGS_B => 0,
C_HAS_MUX_OUTPUT_REGS_A => 0,
C_HAS_MUX_OUTPUT_REGS_B => 0,
C_MUX_PIPELINE_STAGES => 0,
C_HAS_SOFTECC_INPUT_REGS_A => 0,
C_HAS_SOFTECC_OUTPUT_REGS_B => 0,
C_USE_SOFTECC => 0,
C_USE_ECC => 0,
C_EN_ECC_PIPE => 0,
C_HAS_INJECTERR => 0,
C_SIM_COLLISION_CHECK => "ALL",
C_COMMON_CLK => 1,
C_DISABLE_WARN_BHV_COLL => 0,
C_EN_SLEEP_PIN => 0,
C_DISABLE_WARN_BHV_RANGE => 0,
C_COUNT_36K_BRAM => "4",
C_COUNT_18K_BRAM => "1",
C_EST_POWER_SUMMARY => "Estimated Power for IP : 8.9942449999999994 mW"
)
PORT MAP (
clka => clka,
rsta => '0',
ena => ena,
regcea => '0',
wea => wea,
addra => addra,
dina => dina,
clkb => clkb,
rstb => '0',
enb => enb,
regceb => '0',
web => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
addrb => addrb,
dinb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
doutb => doutb,
injectsbiterr => '0',
injectdbiterr => '0',
eccpipece => '0',
sleep => '0',
s_aclk => '0',
s_aresetn => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awvalid => '0',
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 16)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wlast => '0',
s_axi_wvalid => '0',
s_axi_bready => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arvalid => '0',
s_axi_rready => '0',
s_axi_injectsbiterr => '0',
s_axi_injectdbiterr => '0'
);
END SDPRAM_16A9024X32B4512_arch;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.2
-- IP Revision: 4
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY blk_mem_gen_v8_2;
USE blk_mem_gen_v8_2.blk_mem_gen_v8_2;
ENTITY SDPRAM_16A9024X32B4512 IS
PORT (
clka : IN STD_LOGIC;
ena : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
clkb : IN STD_LOGIC;
enb : IN STD_LOGIC;
addrb : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END SDPRAM_16A9024X32B4512;
ARCHITECTURE SDPRAM_16A9024X32B4512_arch OF SDPRAM_16A9024X32B4512 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF SDPRAM_16A9024X32B4512_arch: ARCHITECTURE IS "yes";
COMPONENT blk_mem_gen_v8_2 IS
GENERIC (
C_FAMILY : STRING;
C_XDEVICEFAMILY : STRING;
C_ELABORATION_DIR : STRING;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_AXI_SLAVE_TYPE : INTEGER;
C_USE_BRAM_BLOCK : INTEGER;
C_ENABLE_32BIT_ADDRESS : INTEGER;
C_CTRL_ECC_ALGO : STRING;
C_HAS_AXI_ID : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_MEM_TYPE : INTEGER;
C_BYTE_SIZE : INTEGER;
C_ALGORITHM : INTEGER;
C_PRIM_TYPE : INTEGER;
C_LOAD_INIT_FILE : INTEGER;
C_INIT_FILE_NAME : STRING;
C_INIT_FILE : STRING;
C_USE_DEFAULT_DATA : INTEGER;
C_DEFAULT_DATA : STRING;
C_HAS_RSTA : INTEGER;
C_RST_PRIORITY_A : STRING;
C_RSTRAM_A : INTEGER;
C_INITA_VAL : STRING;
C_HAS_ENA : INTEGER;
C_HAS_REGCEA : INTEGER;
C_USE_BYTE_WEA : INTEGER;
C_WEA_WIDTH : INTEGER;
C_WRITE_MODE_A : STRING;
C_WRITE_WIDTH_A : INTEGER;
C_READ_WIDTH_A : INTEGER;
C_WRITE_DEPTH_A : INTEGER;
C_READ_DEPTH_A : INTEGER;
C_ADDRA_WIDTH : INTEGER;
C_HAS_RSTB : INTEGER;
C_RST_PRIORITY_B : STRING;
C_RSTRAM_B : INTEGER;
C_INITB_VAL : STRING;
C_HAS_ENB : INTEGER;
C_HAS_REGCEB : INTEGER;
C_USE_BYTE_WEB : INTEGER;
C_WEB_WIDTH : INTEGER;
C_WRITE_MODE_B : STRING;
C_WRITE_WIDTH_B : INTEGER;
C_READ_WIDTH_B : INTEGER;
C_WRITE_DEPTH_B : INTEGER;
C_READ_DEPTH_B : INTEGER;
C_ADDRB_WIDTH : INTEGER;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER;
C_MUX_PIPELINE_STAGES : INTEGER;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER;
C_USE_SOFTECC : INTEGER;
C_USE_ECC : INTEGER;
C_EN_ECC_PIPE : INTEGER;
C_HAS_INJECTERR : INTEGER;
C_SIM_COLLISION_CHECK : STRING;
C_COMMON_CLK : INTEGER;
C_DISABLE_WARN_BHV_COLL : INTEGER;
C_EN_SLEEP_PIN : INTEGER;
C_DISABLE_WARN_BHV_RANGE : INTEGER;
C_COUNT_36K_BRAM : STRING;
C_COUNT_18K_BRAM : STRING;
C_EST_POWER_SUMMARY : STRING
);
PORT (
clka : IN STD_LOGIC;
rsta : IN STD_LOGIC;
ena : IN STD_LOGIC;
regcea : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
clkb : IN STD_LOGIC;
rstb : IN STD_LOGIC;
enb : IN STD_LOGIC;
regceb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
injectsbiterr : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
eccpipece : IN STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
rdaddrecc : OUT STD_LOGIC_VECTOR(12 DOWNTO 0);
sleep : IN STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi_injectsbiterr : IN STD_LOGIC;
s_axi_injectdbiterr : IN STD_LOGIC;
s_axi_sbiterr : OUT STD_LOGIC;
s_axi_dbiterr : OUT STD_LOGIC;
s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(12 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_2;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF SDPRAM_16A9024X32B4512_arch: ARCHITECTURE IS "blk_mem_gen_v8_2,Vivado 2014.4.1";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF SDPRAM_16A9024X32B4512_arch : ARCHITECTURE IS "SDPRAM_16A9024X32B4512,blk_mem_gen_v8_2,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF SDPRAM_16A9024X32B4512_arch: ARCHITECTURE IS "SDPRAM_16A9024X32B4512,blk_mem_gen_v8_2,{x_ipProduct=Vivado 2014.4.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.2,x_ipCoreRevision=4,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_XDEVICEFAMILY=zynq,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=0,C_ENABLE_32BIT_ADDRESS=0,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=1,C_BYTE_SIZE=9,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=0,C_INIT_FILE_NAME=no_coe_file_loaded,C_INIT_FILE=SDPRAM_16A9024X32B4512.mem,C_USE_DEFAULT_DATA=0,C_DEFAULT_DATA=0,C_HAS_RSTA=0,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=1,C_HAS_REGCEA=0,C_USE_BYTE_WEA=0,C_WEA_WIDTH=1,C_WRITE_MODE_A=NO_CHANGE,C_WRITE_WIDTH_A=16,C_READ_WIDTH_A=16,C_WRITE_DEPTH_A=9024,C_READ_DEPTH_A=9024,C_ADDRA_WIDTH=14,C_HAS_RSTB=0,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=1,C_HAS_REGCEB=0,C_USE_BYTE_WEB=0,C_WEB_WIDTH=1,C_WRITE_MODE_B=READ_FIRST,C_WRITE_WIDTH_B=32,C_READ_WIDTH_B=32,C_WRITE_DEPTH_B=4512,C_READ_DEPTH_B=4512,C_ADDRB_WIDTH=13,C_HAS_MEM_OUTPUT_REGS_A=0,C_HAS_MEM_OUTPUT_REGS_B=0,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=1,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_DISABLE_WARN_BHV_RANGE=0,C_COUNT_36K_BRAM=4,C_COUNT_18K_BRAM=1,C_EST_POWER_SUMMARY=Estimated Power for IP _ 8.9942449999999994 mW}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clka: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
ATTRIBUTE X_INTERFACE_INFO OF ena: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA EN";
ATTRIBUTE X_INTERFACE_INFO OF wea: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
ATTRIBUTE X_INTERFACE_INFO OF addra: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
ATTRIBUTE X_INTERFACE_INFO OF dina: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
ATTRIBUTE X_INTERFACE_INFO OF clkb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB CLK";
ATTRIBUTE X_INTERFACE_INFO OF enb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB EN";
ATTRIBUTE X_INTERFACE_INFO OF addrb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR";
ATTRIBUTE X_INTERFACE_INFO OF doutb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT";
BEGIN
U0 : blk_mem_gen_v8_2
GENERIC MAP (
C_FAMILY => "zynq",
C_XDEVICEFAMILY => "zynq",
C_ELABORATION_DIR => "./",
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_AXI_SLAVE_TYPE => 0,
C_USE_BRAM_BLOCK => 0,
C_ENABLE_32BIT_ADDRESS => 0,
C_CTRL_ECC_ALGO => "NONE",
C_HAS_AXI_ID => 0,
C_AXI_ID_WIDTH => 4,
C_MEM_TYPE => 1,
C_BYTE_SIZE => 9,
C_ALGORITHM => 1,
C_PRIM_TYPE => 1,
C_LOAD_INIT_FILE => 0,
C_INIT_FILE_NAME => "no_coe_file_loaded",
C_INIT_FILE => "SDPRAM_16A9024X32B4512.mem",
C_USE_DEFAULT_DATA => 0,
C_DEFAULT_DATA => "0",
C_HAS_RSTA => 0,
C_RST_PRIORITY_A => "CE",
C_RSTRAM_A => 0,
C_INITA_VAL => "0",
C_HAS_ENA => 1,
C_HAS_REGCEA => 0,
C_USE_BYTE_WEA => 0,
C_WEA_WIDTH => 1,
C_WRITE_MODE_A => "NO_CHANGE",
C_WRITE_WIDTH_A => 16,
C_READ_WIDTH_A => 16,
C_WRITE_DEPTH_A => 9024,
C_READ_DEPTH_A => 9024,
C_ADDRA_WIDTH => 14,
C_HAS_RSTB => 0,
C_RST_PRIORITY_B => "CE",
C_RSTRAM_B => 0,
C_INITB_VAL => "0",
C_HAS_ENB => 1,
C_HAS_REGCEB => 0,
C_USE_BYTE_WEB => 0,
C_WEB_WIDTH => 1,
C_WRITE_MODE_B => "READ_FIRST",
C_WRITE_WIDTH_B => 32,
C_READ_WIDTH_B => 32,
C_WRITE_DEPTH_B => 4512,
C_READ_DEPTH_B => 4512,
C_ADDRB_WIDTH => 13,
C_HAS_MEM_OUTPUT_REGS_A => 0,
C_HAS_MEM_OUTPUT_REGS_B => 0,
C_HAS_MUX_OUTPUT_REGS_A => 0,
C_HAS_MUX_OUTPUT_REGS_B => 0,
C_MUX_PIPELINE_STAGES => 0,
C_HAS_SOFTECC_INPUT_REGS_A => 0,
C_HAS_SOFTECC_OUTPUT_REGS_B => 0,
C_USE_SOFTECC => 0,
C_USE_ECC => 0,
C_EN_ECC_PIPE => 0,
C_HAS_INJECTERR => 0,
C_SIM_COLLISION_CHECK => "ALL",
C_COMMON_CLK => 1,
C_DISABLE_WARN_BHV_COLL => 0,
C_EN_SLEEP_PIN => 0,
C_DISABLE_WARN_BHV_RANGE => 0,
C_COUNT_36K_BRAM => "4",
C_COUNT_18K_BRAM => "1",
C_EST_POWER_SUMMARY => "Estimated Power for IP : 8.9942449999999994 mW"
)
PORT MAP (
clka => clka,
rsta => '0',
ena => ena,
regcea => '0',
wea => wea,
addra => addra,
dina => dina,
clkb => clkb,
rstb => '0',
enb => enb,
regceb => '0',
web => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
addrb => addrb,
dinb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
doutb => doutb,
injectsbiterr => '0',
injectdbiterr => '0',
eccpipece => '0',
sleep => '0',
s_aclk => '0',
s_aresetn => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awvalid => '0',
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 16)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wlast => '0',
s_axi_wvalid => '0',
s_axi_bready => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arvalid => '0',
s_axi_rready => '0',
s_axi_injectsbiterr => '0',
s_axi_injectdbiterr => '0'
);
END SDPRAM_16A9024X32B4512_arch;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.2
-- IP Revision: 4
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY blk_mem_gen_v8_2;
USE blk_mem_gen_v8_2.blk_mem_gen_v8_2;
ENTITY SDPRAM_16A9024X32B4512 IS
PORT (
clka : IN STD_LOGIC;
ena : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
clkb : IN STD_LOGIC;
enb : IN STD_LOGIC;
addrb : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END SDPRAM_16A9024X32B4512;
ARCHITECTURE SDPRAM_16A9024X32B4512_arch OF SDPRAM_16A9024X32B4512 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF SDPRAM_16A9024X32B4512_arch: ARCHITECTURE IS "yes";
COMPONENT blk_mem_gen_v8_2 IS
GENERIC (
C_FAMILY : STRING;
C_XDEVICEFAMILY : STRING;
C_ELABORATION_DIR : STRING;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_AXI_SLAVE_TYPE : INTEGER;
C_USE_BRAM_BLOCK : INTEGER;
C_ENABLE_32BIT_ADDRESS : INTEGER;
C_CTRL_ECC_ALGO : STRING;
C_HAS_AXI_ID : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_MEM_TYPE : INTEGER;
C_BYTE_SIZE : INTEGER;
C_ALGORITHM : INTEGER;
C_PRIM_TYPE : INTEGER;
C_LOAD_INIT_FILE : INTEGER;
C_INIT_FILE_NAME : STRING;
C_INIT_FILE : STRING;
C_USE_DEFAULT_DATA : INTEGER;
C_DEFAULT_DATA : STRING;
C_HAS_RSTA : INTEGER;
C_RST_PRIORITY_A : STRING;
C_RSTRAM_A : INTEGER;
C_INITA_VAL : STRING;
C_HAS_ENA : INTEGER;
C_HAS_REGCEA : INTEGER;
C_USE_BYTE_WEA : INTEGER;
C_WEA_WIDTH : INTEGER;
C_WRITE_MODE_A : STRING;
C_WRITE_WIDTH_A : INTEGER;
C_READ_WIDTH_A : INTEGER;
C_WRITE_DEPTH_A : INTEGER;
C_READ_DEPTH_A : INTEGER;
C_ADDRA_WIDTH : INTEGER;
C_HAS_RSTB : INTEGER;
C_RST_PRIORITY_B : STRING;
C_RSTRAM_B : INTEGER;
C_INITB_VAL : STRING;
C_HAS_ENB : INTEGER;
C_HAS_REGCEB : INTEGER;
C_USE_BYTE_WEB : INTEGER;
C_WEB_WIDTH : INTEGER;
C_WRITE_MODE_B : STRING;
C_WRITE_WIDTH_B : INTEGER;
C_READ_WIDTH_B : INTEGER;
C_WRITE_DEPTH_B : INTEGER;
C_READ_DEPTH_B : INTEGER;
C_ADDRB_WIDTH : INTEGER;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER;
C_MUX_PIPELINE_STAGES : INTEGER;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER;
C_USE_SOFTECC : INTEGER;
C_USE_ECC : INTEGER;
C_EN_ECC_PIPE : INTEGER;
C_HAS_INJECTERR : INTEGER;
C_SIM_COLLISION_CHECK : STRING;
C_COMMON_CLK : INTEGER;
C_DISABLE_WARN_BHV_COLL : INTEGER;
C_EN_SLEEP_PIN : INTEGER;
C_DISABLE_WARN_BHV_RANGE : INTEGER;
C_COUNT_36K_BRAM : STRING;
C_COUNT_18K_BRAM : STRING;
C_EST_POWER_SUMMARY : STRING
);
PORT (
clka : IN STD_LOGIC;
rsta : IN STD_LOGIC;
ena : IN STD_LOGIC;
regcea : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
clkb : IN STD_LOGIC;
rstb : IN STD_LOGIC;
enb : IN STD_LOGIC;
regceb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
injectsbiterr : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
eccpipece : IN STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
rdaddrecc : OUT STD_LOGIC_VECTOR(12 DOWNTO 0);
sleep : IN STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi_injectsbiterr : IN STD_LOGIC;
s_axi_injectdbiterr : IN STD_LOGIC;
s_axi_sbiterr : OUT STD_LOGIC;
s_axi_dbiterr : OUT STD_LOGIC;
s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(12 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_2;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF SDPRAM_16A9024X32B4512_arch: ARCHITECTURE IS "blk_mem_gen_v8_2,Vivado 2014.4.1";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF SDPRAM_16A9024X32B4512_arch : ARCHITECTURE IS "SDPRAM_16A9024X32B4512,blk_mem_gen_v8_2,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF SDPRAM_16A9024X32B4512_arch: ARCHITECTURE IS "SDPRAM_16A9024X32B4512,blk_mem_gen_v8_2,{x_ipProduct=Vivado 2014.4.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.2,x_ipCoreRevision=4,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_XDEVICEFAMILY=zynq,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=0,C_ENABLE_32BIT_ADDRESS=0,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=1,C_BYTE_SIZE=9,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=0,C_INIT_FILE_NAME=no_coe_file_loaded,C_INIT_FILE=SDPRAM_16A9024X32B4512.mem,C_USE_DEFAULT_DATA=0,C_DEFAULT_DATA=0,C_HAS_RSTA=0,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=1,C_HAS_REGCEA=0,C_USE_BYTE_WEA=0,C_WEA_WIDTH=1,C_WRITE_MODE_A=NO_CHANGE,C_WRITE_WIDTH_A=16,C_READ_WIDTH_A=16,C_WRITE_DEPTH_A=9024,C_READ_DEPTH_A=9024,C_ADDRA_WIDTH=14,C_HAS_RSTB=0,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=1,C_HAS_REGCEB=0,C_USE_BYTE_WEB=0,C_WEB_WIDTH=1,C_WRITE_MODE_B=READ_FIRST,C_WRITE_WIDTH_B=32,C_READ_WIDTH_B=32,C_WRITE_DEPTH_B=4512,C_READ_DEPTH_B=4512,C_ADDRB_WIDTH=13,C_HAS_MEM_OUTPUT_REGS_A=0,C_HAS_MEM_OUTPUT_REGS_B=0,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=1,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_DISABLE_WARN_BHV_RANGE=0,C_COUNT_36K_BRAM=4,C_COUNT_18K_BRAM=1,C_EST_POWER_SUMMARY=Estimated Power for IP _ 8.9942449999999994 mW}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clka: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
ATTRIBUTE X_INTERFACE_INFO OF ena: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA EN";
ATTRIBUTE X_INTERFACE_INFO OF wea: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
ATTRIBUTE X_INTERFACE_INFO OF addra: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
ATTRIBUTE X_INTERFACE_INFO OF dina: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
ATTRIBUTE X_INTERFACE_INFO OF clkb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB CLK";
ATTRIBUTE X_INTERFACE_INFO OF enb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB EN";
ATTRIBUTE X_INTERFACE_INFO OF addrb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR";
ATTRIBUTE X_INTERFACE_INFO OF doutb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT";
BEGIN
U0 : blk_mem_gen_v8_2
GENERIC MAP (
C_FAMILY => "zynq",
C_XDEVICEFAMILY => "zynq",
C_ELABORATION_DIR => "./",
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_AXI_SLAVE_TYPE => 0,
C_USE_BRAM_BLOCK => 0,
C_ENABLE_32BIT_ADDRESS => 0,
C_CTRL_ECC_ALGO => "NONE",
C_HAS_AXI_ID => 0,
C_AXI_ID_WIDTH => 4,
C_MEM_TYPE => 1,
C_BYTE_SIZE => 9,
C_ALGORITHM => 1,
C_PRIM_TYPE => 1,
C_LOAD_INIT_FILE => 0,
C_INIT_FILE_NAME => "no_coe_file_loaded",
C_INIT_FILE => "SDPRAM_16A9024X32B4512.mem",
C_USE_DEFAULT_DATA => 0,
C_DEFAULT_DATA => "0",
C_HAS_RSTA => 0,
C_RST_PRIORITY_A => "CE",
C_RSTRAM_A => 0,
C_INITA_VAL => "0",
C_HAS_ENA => 1,
C_HAS_REGCEA => 0,
C_USE_BYTE_WEA => 0,
C_WEA_WIDTH => 1,
C_WRITE_MODE_A => "NO_CHANGE",
C_WRITE_WIDTH_A => 16,
C_READ_WIDTH_A => 16,
C_WRITE_DEPTH_A => 9024,
C_READ_DEPTH_A => 9024,
C_ADDRA_WIDTH => 14,
C_HAS_RSTB => 0,
C_RST_PRIORITY_B => "CE",
C_RSTRAM_B => 0,
C_INITB_VAL => "0",
C_HAS_ENB => 1,
C_HAS_REGCEB => 0,
C_USE_BYTE_WEB => 0,
C_WEB_WIDTH => 1,
C_WRITE_MODE_B => "READ_FIRST",
C_WRITE_WIDTH_B => 32,
C_READ_WIDTH_B => 32,
C_WRITE_DEPTH_B => 4512,
C_READ_DEPTH_B => 4512,
C_ADDRB_WIDTH => 13,
C_HAS_MEM_OUTPUT_REGS_A => 0,
C_HAS_MEM_OUTPUT_REGS_B => 0,
C_HAS_MUX_OUTPUT_REGS_A => 0,
C_HAS_MUX_OUTPUT_REGS_B => 0,
C_MUX_PIPELINE_STAGES => 0,
C_HAS_SOFTECC_INPUT_REGS_A => 0,
C_HAS_SOFTECC_OUTPUT_REGS_B => 0,
C_USE_SOFTECC => 0,
C_USE_ECC => 0,
C_EN_ECC_PIPE => 0,
C_HAS_INJECTERR => 0,
C_SIM_COLLISION_CHECK => "ALL",
C_COMMON_CLK => 1,
C_DISABLE_WARN_BHV_COLL => 0,
C_EN_SLEEP_PIN => 0,
C_DISABLE_WARN_BHV_RANGE => 0,
C_COUNT_36K_BRAM => "4",
C_COUNT_18K_BRAM => "1",
C_EST_POWER_SUMMARY => "Estimated Power for IP : 8.9942449999999994 mW"
)
PORT MAP (
clka => clka,
rsta => '0',
ena => ena,
regcea => '0',
wea => wea,
addra => addra,
dina => dina,
clkb => clkb,
rstb => '0',
enb => enb,
regceb => '0',
web => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
addrb => addrb,
dinb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
doutb => doutb,
injectsbiterr => '0',
injectdbiterr => '0',
eccpipece => '0',
sleep => '0',
s_aclk => '0',
s_aresetn => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awvalid => '0',
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 16)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wlast => '0',
s_axi_wvalid => '0',
s_axi_bready => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arvalid => '0',
s_axi_rready => '0',
s_axi_injectsbiterr => '0',
s_axi_injectdbiterr => '0'
);
END SDPRAM_16A9024X32B4512_arch;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.2
-- IP Revision: 4
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY blk_mem_gen_v8_2;
USE blk_mem_gen_v8_2.blk_mem_gen_v8_2;
ENTITY SDPRAM_16A9024X32B4512 IS
PORT (
clka : IN STD_LOGIC;
ena : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
clkb : IN STD_LOGIC;
enb : IN STD_LOGIC;
addrb : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END SDPRAM_16A9024X32B4512;
ARCHITECTURE SDPRAM_16A9024X32B4512_arch OF SDPRAM_16A9024X32B4512 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF SDPRAM_16A9024X32B4512_arch: ARCHITECTURE IS "yes";
COMPONENT blk_mem_gen_v8_2 IS
GENERIC (
C_FAMILY : STRING;
C_XDEVICEFAMILY : STRING;
C_ELABORATION_DIR : STRING;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_AXI_SLAVE_TYPE : INTEGER;
C_USE_BRAM_BLOCK : INTEGER;
C_ENABLE_32BIT_ADDRESS : INTEGER;
C_CTRL_ECC_ALGO : STRING;
C_HAS_AXI_ID : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_MEM_TYPE : INTEGER;
C_BYTE_SIZE : INTEGER;
C_ALGORITHM : INTEGER;
C_PRIM_TYPE : INTEGER;
C_LOAD_INIT_FILE : INTEGER;
C_INIT_FILE_NAME : STRING;
C_INIT_FILE : STRING;
C_USE_DEFAULT_DATA : INTEGER;
C_DEFAULT_DATA : STRING;
C_HAS_RSTA : INTEGER;
C_RST_PRIORITY_A : STRING;
C_RSTRAM_A : INTEGER;
C_INITA_VAL : STRING;
C_HAS_ENA : INTEGER;
C_HAS_REGCEA : INTEGER;
C_USE_BYTE_WEA : INTEGER;
C_WEA_WIDTH : INTEGER;
C_WRITE_MODE_A : STRING;
C_WRITE_WIDTH_A : INTEGER;
C_READ_WIDTH_A : INTEGER;
C_WRITE_DEPTH_A : INTEGER;
C_READ_DEPTH_A : INTEGER;
C_ADDRA_WIDTH : INTEGER;
C_HAS_RSTB : INTEGER;
C_RST_PRIORITY_B : STRING;
C_RSTRAM_B : INTEGER;
C_INITB_VAL : STRING;
C_HAS_ENB : INTEGER;
C_HAS_REGCEB : INTEGER;
C_USE_BYTE_WEB : INTEGER;
C_WEB_WIDTH : INTEGER;
C_WRITE_MODE_B : STRING;
C_WRITE_WIDTH_B : INTEGER;
C_READ_WIDTH_B : INTEGER;
C_WRITE_DEPTH_B : INTEGER;
C_READ_DEPTH_B : INTEGER;
C_ADDRB_WIDTH : INTEGER;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER;
C_MUX_PIPELINE_STAGES : INTEGER;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER;
C_USE_SOFTECC : INTEGER;
C_USE_ECC : INTEGER;
C_EN_ECC_PIPE : INTEGER;
C_HAS_INJECTERR : INTEGER;
C_SIM_COLLISION_CHECK : STRING;
C_COMMON_CLK : INTEGER;
C_DISABLE_WARN_BHV_COLL : INTEGER;
C_EN_SLEEP_PIN : INTEGER;
C_DISABLE_WARN_BHV_RANGE : INTEGER;
C_COUNT_36K_BRAM : STRING;
C_COUNT_18K_BRAM : STRING;
C_EST_POWER_SUMMARY : STRING
);
PORT (
clka : IN STD_LOGIC;
rsta : IN STD_LOGIC;
ena : IN STD_LOGIC;
regcea : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
clkb : IN STD_LOGIC;
rstb : IN STD_LOGIC;
enb : IN STD_LOGIC;
regceb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
injectsbiterr : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
eccpipece : IN STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
rdaddrecc : OUT STD_LOGIC_VECTOR(12 DOWNTO 0);
sleep : IN STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi_injectsbiterr : IN STD_LOGIC;
s_axi_injectdbiterr : IN STD_LOGIC;
s_axi_sbiterr : OUT STD_LOGIC;
s_axi_dbiterr : OUT STD_LOGIC;
s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(12 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_2;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF SDPRAM_16A9024X32B4512_arch: ARCHITECTURE IS "blk_mem_gen_v8_2,Vivado 2014.4.1";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF SDPRAM_16A9024X32B4512_arch : ARCHITECTURE IS "SDPRAM_16A9024X32B4512,blk_mem_gen_v8_2,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF SDPRAM_16A9024X32B4512_arch: ARCHITECTURE IS "SDPRAM_16A9024X32B4512,blk_mem_gen_v8_2,{x_ipProduct=Vivado 2014.4.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.2,x_ipCoreRevision=4,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_XDEVICEFAMILY=zynq,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=0,C_ENABLE_32BIT_ADDRESS=0,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=1,C_BYTE_SIZE=9,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=0,C_INIT_FILE_NAME=no_coe_file_loaded,C_INIT_FILE=SDPRAM_16A9024X32B4512.mem,C_USE_DEFAULT_DATA=0,C_DEFAULT_DATA=0,C_HAS_RSTA=0,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=1,C_HAS_REGCEA=0,C_USE_BYTE_WEA=0,C_WEA_WIDTH=1,C_WRITE_MODE_A=NO_CHANGE,C_WRITE_WIDTH_A=16,C_READ_WIDTH_A=16,C_WRITE_DEPTH_A=9024,C_READ_DEPTH_A=9024,C_ADDRA_WIDTH=14,C_HAS_RSTB=0,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=1,C_HAS_REGCEB=0,C_USE_BYTE_WEB=0,C_WEB_WIDTH=1,C_WRITE_MODE_B=READ_FIRST,C_WRITE_WIDTH_B=32,C_READ_WIDTH_B=32,C_WRITE_DEPTH_B=4512,C_READ_DEPTH_B=4512,C_ADDRB_WIDTH=13,C_HAS_MEM_OUTPUT_REGS_A=0,C_HAS_MEM_OUTPUT_REGS_B=0,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=1,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_DISABLE_WARN_BHV_RANGE=0,C_COUNT_36K_BRAM=4,C_COUNT_18K_BRAM=1,C_EST_POWER_SUMMARY=Estimated Power for IP _ 8.9942449999999994 mW}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clka: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
ATTRIBUTE X_INTERFACE_INFO OF ena: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA EN";
ATTRIBUTE X_INTERFACE_INFO OF wea: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
ATTRIBUTE X_INTERFACE_INFO OF addra: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
ATTRIBUTE X_INTERFACE_INFO OF dina: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
ATTRIBUTE X_INTERFACE_INFO OF clkb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB CLK";
ATTRIBUTE X_INTERFACE_INFO OF enb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB EN";
ATTRIBUTE X_INTERFACE_INFO OF addrb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR";
ATTRIBUTE X_INTERFACE_INFO OF doutb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT";
BEGIN
U0 : blk_mem_gen_v8_2
GENERIC MAP (
C_FAMILY => "zynq",
C_XDEVICEFAMILY => "zynq",
C_ELABORATION_DIR => "./",
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_AXI_SLAVE_TYPE => 0,
C_USE_BRAM_BLOCK => 0,
C_ENABLE_32BIT_ADDRESS => 0,
C_CTRL_ECC_ALGO => "NONE",
C_HAS_AXI_ID => 0,
C_AXI_ID_WIDTH => 4,
C_MEM_TYPE => 1,
C_BYTE_SIZE => 9,
C_ALGORITHM => 1,
C_PRIM_TYPE => 1,
C_LOAD_INIT_FILE => 0,
C_INIT_FILE_NAME => "no_coe_file_loaded",
C_INIT_FILE => "SDPRAM_16A9024X32B4512.mem",
C_USE_DEFAULT_DATA => 0,
C_DEFAULT_DATA => "0",
C_HAS_RSTA => 0,
C_RST_PRIORITY_A => "CE",
C_RSTRAM_A => 0,
C_INITA_VAL => "0",
C_HAS_ENA => 1,
C_HAS_REGCEA => 0,
C_USE_BYTE_WEA => 0,
C_WEA_WIDTH => 1,
C_WRITE_MODE_A => "NO_CHANGE",
C_WRITE_WIDTH_A => 16,
C_READ_WIDTH_A => 16,
C_WRITE_DEPTH_A => 9024,
C_READ_DEPTH_A => 9024,
C_ADDRA_WIDTH => 14,
C_HAS_RSTB => 0,
C_RST_PRIORITY_B => "CE",
C_RSTRAM_B => 0,
C_INITB_VAL => "0",
C_HAS_ENB => 1,
C_HAS_REGCEB => 0,
C_USE_BYTE_WEB => 0,
C_WEB_WIDTH => 1,
C_WRITE_MODE_B => "READ_FIRST",
C_WRITE_WIDTH_B => 32,
C_READ_WIDTH_B => 32,
C_WRITE_DEPTH_B => 4512,
C_READ_DEPTH_B => 4512,
C_ADDRB_WIDTH => 13,
C_HAS_MEM_OUTPUT_REGS_A => 0,
C_HAS_MEM_OUTPUT_REGS_B => 0,
C_HAS_MUX_OUTPUT_REGS_A => 0,
C_HAS_MUX_OUTPUT_REGS_B => 0,
C_MUX_PIPELINE_STAGES => 0,
C_HAS_SOFTECC_INPUT_REGS_A => 0,
C_HAS_SOFTECC_OUTPUT_REGS_B => 0,
C_USE_SOFTECC => 0,
C_USE_ECC => 0,
C_EN_ECC_PIPE => 0,
C_HAS_INJECTERR => 0,
C_SIM_COLLISION_CHECK => "ALL",
C_COMMON_CLK => 1,
C_DISABLE_WARN_BHV_COLL => 0,
C_EN_SLEEP_PIN => 0,
C_DISABLE_WARN_BHV_RANGE => 0,
C_COUNT_36K_BRAM => "4",
C_COUNT_18K_BRAM => "1",
C_EST_POWER_SUMMARY => "Estimated Power for IP : 8.9942449999999994 mW"
)
PORT MAP (
clka => clka,
rsta => '0',
ena => ena,
regcea => '0',
wea => wea,
addra => addra,
dina => dina,
clkb => clkb,
rstb => '0',
enb => enb,
regceb => '0',
web => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
addrb => addrb,
dinb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
doutb => doutb,
injectsbiterr => '0',
injectdbiterr => '0',
eccpipece => '0',
sleep => '0',
s_aclk => '0',
s_aresetn => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awvalid => '0',
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 16)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wlast => '0',
s_axi_wvalid => '0',
s_axi_bready => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arvalid => '0',
s_axi_rready => '0',
s_axi_injectsbiterr => '0',
s_axi_injectdbiterr => '0'
);
END SDPRAM_16A9024X32B4512_arch;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:21:26 06/06/2016
-- Design Name:
-- Module Name: Buffer3_8bit - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Buffer3_8bit is
Port ( d : in STD_LOGIC_VECTOR (7 downto 0);
enable : in STD_LOGIC;
q : out STD_LOGIC_VECTOR (7 downto 0));
end Buffer3_8bit;
architecture Behavioral of Buffer3_8bit is
begin
q <= d WHEN enable = '1' ELSE
"ZZZZZZZZ";
end Behavioral;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:module_ref:Counter10bit:1.0
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY RAT_Counter10bit_0_0 IS
PORT (
Din : IN STD_LOGIC_VECTOR(0 TO 9);
LOAD : IN STD_LOGIC;
INC : IN STD_LOGIC;
RESET : IN STD_LOGIC;
CLK : IN STD_LOGIC;
COUNT : OUT STD_LOGIC_VECTOR(0 TO 9)
);
END RAT_Counter10bit_0_0;
ARCHITECTURE RAT_Counter10bit_0_0_arch OF RAT_Counter10bit_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF RAT_Counter10bit_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT Counter10bit IS
PORT (
Din : IN STD_LOGIC_VECTOR(0 TO 9);
LOAD : IN STD_LOGIC;
INC : IN STD_LOGIC;
RESET : IN STD_LOGIC;
CLK : IN STD_LOGIC;
COUNT : OUT STD_LOGIC_VECTOR(0 TO 9)
);
END COMPONENT Counter10bit;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF RAT_Counter10bit_0_0_arch: ARCHITECTURE IS "Counter10bit,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF RAT_Counter10bit_0_0_arch : ARCHITECTURE IS "RAT_Counter10bit_0_0,Counter10bit,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF RAT_Counter10bit_0_0_arch: ARCHITECTURE IS "RAT_Counter10bit_0_0,Counter10bit,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=module_ref,x_ipName=Counter10bit,x_ipVersion=1.0,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF RESET: SIGNAL IS "xilinx.com:signal:reset:1.0 RESET RST";
ATTRIBUTE X_INTERFACE_INFO OF CLK: SIGNAL IS "xilinx.com:signal:clock:1.0 CLK CLK";
BEGIN
U0 : Counter10bit
PORT MAP (
Din => Din,
LOAD => LOAD,
INC => INC,
RESET => RESET,
CLK => CLK,
COUNT => COUNT
);
END RAT_Counter10bit_0_0_arch;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:module_ref:Counter10bit:1.0
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY RAT_Counter10bit_0_0 IS
PORT (
Din : IN STD_LOGIC_VECTOR(0 TO 9);
LOAD : IN STD_LOGIC;
INC : IN STD_LOGIC;
RESET : IN STD_LOGIC;
CLK : IN STD_LOGIC;
COUNT : OUT STD_LOGIC_VECTOR(0 TO 9)
);
END RAT_Counter10bit_0_0;
ARCHITECTURE RAT_Counter10bit_0_0_arch OF RAT_Counter10bit_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF RAT_Counter10bit_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT Counter10bit IS
PORT (
Din : IN STD_LOGIC_VECTOR(0 TO 9);
LOAD : IN STD_LOGIC;
INC : IN STD_LOGIC;
RESET : IN STD_LOGIC;
CLK : IN STD_LOGIC;
COUNT : OUT STD_LOGIC_VECTOR(0 TO 9)
);
END COMPONENT Counter10bit;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF RAT_Counter10bit_0_0_arch: ARCHITECTURE IS "Counter10bit,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF RAT_Counter10bit_0_0_arch : ARCHITECTURE IS "RAT_Counter10bit_0_0,Counter10bit,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF RAT_Counter10bit_0_0_arch: ARCHITECTURE IS "RAT_Counter10bit_0_0,Counter10bit,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=module_ref,x_ipName=Counter10bit,x_ipVersion=1.0,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF RESET: SIGNAL IS "xilinx.com:signal:reset:1.0 RESET RST";
ATTRIBUTE X_INTERFACE_INFO OF CLK: SIGNAL IS "xilinx.com:signal:clock:1.0 CLK CLK";
BEGIN
U0 : Counter10bit
PORT MAP (
Din => Din,
LOAD => LOAD,
INC => INC,
RESET => RESET,
CLK => CLK,
COUNT => COUNT
);
END RAT_Counter10bit_0_0_arch;
|
-- ***************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2010 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ***************************************************************************
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
use proc_common_v3_00_a.ipif_pkg.all;
library axi_lite_ipif_v1_01_a;
use axi_lite_ipif_v1_01_a.axi_lite_ipif;
library clk_detect_v1_00_a;
use clk_detect_v1_00_a.user_logic;
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_S_AXI_DATA_WIDTH --
-- C_S_AXI_ADDR_WIDTH --
-- C_S_AXI_MIN_SIZE --
-- C_USE_WSTRB --
-- C_DPHASE_TIMEOUT --
-- C_BASEADDR -- AXI4LITE slave: base address
-- C_HIGHADDR -- AXI4LITE slave: high address
-- C_FAMILY --
-- C_NUM_REG -- Number of software accessible registers
-- C_NUM_MEM -- Number of address-ranges
-- C_SLV_AWIDTH -- Slave interface address bus width
-- C_SLV_DWIDTH -- Slave interface data bus width
--
-- Definition of Ports:
-- S_AXI_ACLK --
-- S_AXI_ARESETN --
-- S_AXI_AWADDR --
-- S_AXI_AWVALID --
-- S_AXI_WDATA --
-- S_AXI_WSTRB --
-- S_AXI_WVALID --
-- S_AXI_BREADY --
-- S_AXI_ARADDR --
-- S_AXI_ARVALID --
-- S_AXI_RREADY --
-- S_AXI_ARREADY --
-- S_AXI_RDATA --
-- S_AXI_RRESP --
-- S_AXI_RVALID --
-- S_AXI_WREADY --
-- S_AXI_BRESP --
-- S_AXI_BVALID --
-- S_AXI_AWREADY --
------------------------------------------------------------------------------
entity clk_detect is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_S_AXI_DATA_WIDTH : integer := 32;
C_S_AXI_ADDR_WIDTH : integer := 32;
C_S_AXI_MIN_SIZE : std_logic_vector := X"000001FF";
C_USE_WSTRB : integer := 0;
C_DPHASE_TIMEOUT : integer := 8;
C_BASEADDR : std_logic_vector := X"40000000";
C_HIGHADDR : std_logic_vector := X"40000FFF";
C_FAMILY : string := "virtex6";
C_NUM_REG : integer := 1;
C_NUM_MEM : integer := 1;
C_SLV_AWIDTH : integer := 32;
C_SLV_DWIDTH : integer := 32
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
-- User logic ports
DUT_CLK : in std_logic;
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_RREADY : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_AWREADY : out std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute MAX_FANOUT : string;
attribute SIGIS : string;
attribute MAX_FANOUT of S_AXI_ACLK : signal is "10000";
attribute MAX_FANOUT of S_AXI_ARESETN : signal is "10000";
attribute SIGIS of S_AXI_ACLK : signal is "Clk";
attribute SIGIS of S_AXI_ARESETN : signal is "Rst";
end entity clk_detect;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of clk_detect is
constant USER_SLV_DWIDTH : integer := C_S_AXI_DATA_WIDTH;
constant IPIF_SLV_DWIDTH : integer := C_S_AXI_DATA_WIDTH;
constant ZERO_ADDR_PAD : std_logic_vector(0 to 31) := (others => '0');
constant USER_SLV_BASEADDR : std_logic_vector := C_BASEADDR;
constant USER_SLV_HIGHADDR : std_logic_vector := C_BASEADDR or X"0000001F";
constant IPIF_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
(
ZERO_ADDR_PAD & USER_SLV_BASEADDR, -- user logic slave space base address
ZERO_ADDR_PAD & USER_SLV_HIGHADDR -- user logic slave space high address
);
constant USER_SLV_NUM_REG : integer := 8;
constant USER_NUM_REG : integer := USER_SLV_NUM_REG;
constant TOTAL_IPIF_CE : integer := USER_NUM_REG;
constant IPIF_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => (USER_SLV_NUM_REG) -- number of ce for user logic slave space
);
------------------------------------------
-- Index for CS/CE
------------------------------------------
constant USER_SLV_CS_INDEX : integer := 0;
constant USER_SLV_CE_INDEX : integer := calc_start_ce_index(IPIF_ARD_NUM_CE_ARRAY, USER_SLV_CS_INDEX);
constant USER_CE_INDEX : integer := USER_SLV_CE_INDEX;
------------------------------------------
-- IP Interconnect (IPIC) signal declarations
------------------------------------------
signal ipif_Bus2IP_Clk : std_logic;
signal ipif_Bus2IP_Resetn : std_logic;
signal ipif_Bus2IP_Addr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal ipif_Bus2IP_RNW : std_logic;
signal ipif_Bus2IP_BE : std_logic_vector(IPIF_SLV_DWIDTH/8-1 downto 0);
signal ipif_Bus2IP_CS : std_logic_vector((IPIF_ARD_ADDR_RANGE_ARRAY'LENGTH)/2-1 downto 0);
signal ipif_Bus2IP_RdCE : std_logic_vector(calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1 downto 0);
signal ipif_Bus2IP_WrCE : std_logic_vector(calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1 downto 0);
signal ipif_Bus2IP_Data : std_logic_vector(IPIF_SLV_DWIDTH-1 downto 0);
signal ipif_IP2Bus_WrAck : std_logic;
signal ipif_IP2Bus_RdAck : std_logic;
signal ipif_IP2Bus_Error : std_logic;
signal ipif_IP2Bus_Data : std_logic_vector(IPIF_SLV_DWIDTH-1 downto 0);
signal user_Bus2IP_RdCE : std_logic_vector(USER_NUM_REG-1 downto 0);
signal user_Bus2IP_WrCE : std_logic_vector(USER_NUM_REG-1 downto 0);
signal user_IP2Bus_Data : std_logic_vector(USER_SLV_DWIDTH-1 downto 0);
signal user_IP2Bus_RdAck : std_logic;
signal user_IP2Bus_WrAck : std_logic;
signal user_IP2Bus_Error : std_logic;
begin
------------------------------------------
-- instantiate axi_lite_ipif
------------------------------------------
AXI_LITE_IPIF_I : entity axi_lite_ipif_v1_01_a.axi_lite_ipif
generic map
(
C_S_AXI_DATA_WIDTH => IPIF_SLV_DWIDTH,
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH,
C_S_AXI_MIN_SIZE => C_S_AXI_MIN_SIZE,
C_USE_WSTRB => C_USE_WSTRB,
C_DPHASE_TIMEOUT => C_DPHASE_TIMEOUT,
C_ARD_ADDR_RANGE_ARRAY => IPIF_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => IPIF_ARD_NUM_CE_ARRAY,
C_FAMILY => C_FAMILY
)
port map
(
S_AXI_ACLK => S_AXI_ACLK,
S_AXI_ARESETN => S_AXI_ARESETN,
S_AXI_AWADDR => S_AXI_AWADDR,
S_AXI_AWVALID => S_AXI_AWVALID,
S_AXI_WDATA => S_AXI_WDATA,
S_AXI_WSTRB => S_AXI_WSTRB,
S_AXI_WVALID => S_AXI_WVALID,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_ARADDR => S_AXI_ARADDR,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_RREADY => S_AXI_RREADY,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_RDATA => S_AXI_RDATA,
S_AXI_RRESP => S_AXI_RRESP,
S_AXI_RVALID => S_AXI_RVALID,
S_AXI_WREADY => S_AXI_WREADY,
S_AXI_BRESP => S_AXI_BRESP,
S_AXI_BVALID => S_AXI_BVALID,
S_AXI_AWREADY => S_AXI_AWREADY,
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Resetn => ipif_Bus2IP_Resetn,
Bus2IP_Addr => ipif_Bus2IP_Addr,
Bus2IP_RNW => ipif_Bus2IP_RNW,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_CS => ipif_Bus2IP_CS,
Bus2IP_RdCE => ipif_Bus2IP_RdCE,
Bus2IP_WrCE => ipif_Bus2IP_WrCE,
Bus2IP_Data => ipif_Bus2IP_Data,
IP2Bus_WrAck => ipif_IP2Bus_WrAck,
IP2Bus_RdAck => ipif_IP2Bus_RdAck,
IP2Bus_Error => ipif_IP2Bus_Error,
IP2Bus_Data => ipif_IP2Bus_Data
);
------------------------------------------
-- instantiate User Logic
------------------------------------------
USER_LOGIC_I : entity clk_detect_v1_00_a.user_logic
generic map
(
-- MAP USER GENERICS BELOW THIS LINE ---------------
--USER generics mapped here
-- MAP USER GENERICS ABOVE THIS LINE ---------------
C_NUM_REG => USER_NUM_REG,
C_SLV_DWIDTH => USER_SLV_DWIDTH
)
port map
(
-- MAP USER PORTS BELOW THIS LINE ------------------
-- User logic ports
dut_clk => dut_CLK,
-- MAP USER PORTS ABOVE THIS LINE ------------------
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Resetn => ipif_Bus2IP_Resetn,
Bus2IP_Data => ipif_Bus2IP_Data,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_RdCE => user_Bus2IP_RdCE,
Bus2IP_WrCE => user_Bus2IP_WrCE,
IP2Bus_Data => user_IP2Bus_Data,
IP2Bus_RdAck => user_IP2Bus_RdAck,
IP2Bus_WrAck => user_IP2Bus_WrAck,
IP2Bus_Error => user_IP2Bus_Error
);
------------------------------------------
-- connect internal signals
------------------------------------------
ipif_IP2Bus_Data <= user_IP2Bus_Data;
ipif_IP2Bus_WrAck <= user_IP2Bus_WrAck;
ipif_IP2Bus_RdAck <= user_IP2Bus_RdAck;
ipif_IP2Bus_Error <= user_IP2Bus_Error;
user_Bus2IP_RdCE <= ipif_Bus2IP_RdCE(USER_NUM_REG-1 downto 0);
user_Bus2IP_WrCE <= ipif_Bus2IP_WrCE(USER_NUM_REG-1 downto 0);
end IMP;
|
----------------------------------------------------------------------------------
-- Felix Winterstein, Imperial College London
--
-- Module Name: process_tree_node - Behavioral
--
-- Revision 1.01
-- Additional Comments: distributed under a BSD license, see LICENSE.txt
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use ieee.math_real.all;
use work.filtering_algorithm_pkg.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity process_tree_node is
port (
clk : in std_logic;
sclr : in std_logic;
nd : in std_logic;
u_in : in node_data_type;
centre_positions_in : in data_type;
centre_indices_in : in centre_index_type;
update_centre_buffer : out std_logic;
final_index_out : out centre_index_type;
sum_sq_out : out coord_type_ext;
rdy : out std_logic;
dead_end : out std_logic;
u_out : out node_data_type;
k_out : out centre_index_type;
centre_index_rdy : out std_logic;
centre_index_wr : out std_logic;
centre_indices_out : out centre_index_type
);
end process_tree_node;
architecture Behavioral of process_tree_node is
constant LAT_DOT_PRODUCT : integer := MUL_CORE_LATENCY+2*integer(ceil(log2(real(D))));
constant LAT_SQ_SUM : integer := MUL_CORE_LATENCY+2+1;
constant LAT_PRUNING_TEST : integer := 2*2+MUL_CORE_LATENCY+2*integer(ceil(log2(real(D))));
constant ADD_LAT_PRUNING : integer := 2;
constant SUB_LAT : integer := 2;
constant LAT_DIFF : integer := LAT_PRUNING_TEST+ADD_LAT_PRUNING-LAT_DOT_PRODUCT-LAT_SQ_SUM;
type sub_res_type is array(0 to D-1) of std_logic_vector(COORD_BITWIDTH+1-1 downto 0);
type node_data_delay_type2 is array(0 to SUB_LAT-1) of node_data_type;
type node_data_delay_type is array(0 to LAT_PRUNING_TEST+ADD_LAT_PRUNING-1) of node_data_type;
type centre_index_delay_type is array(0 to LAT_PRUNING_TEST+ADD_LAT_PRUNING-1) of centre_index_type;
type coord_ext_delay_type is array(0 to LAT_DIFF-1) of coord_type_ext;
component addorsub
generic (
A_BITWIDTH : integer := 16;
B_BITWIDTH : integer := 16;
RES_BITWIDTH : integer := 16
);
port (
clk : in std_logic;
sclr : in std_logic;
nd : in std_logic;
sub : in std_logic;
a : in std_logic_vector(A_BITWIDTH-1 downto 0);
b : in std_logic_vector(B_BITWIDTH-1 downto 0);
res : out std_logic_vector(RES_BITWIDTH-1 downto 0);
rdy : out std_logic
);
end component;
component closest_to_point_top
port (
clk : in std_logic;
sclr : in std_logic;
nd : in std_logic;
u_in : in node_data_type;
point : in data_type_ext; -- assume always ext!!
point_list_d : in data_type; -- assume FIFO interface !!!
point_list_idx : in centre_index_type;
max_idx : out centre_index_type;
min_point : out data_type;
min_index : out centre_index_type;
point_list_d_out : out data_type; -- feed input to output
point_list_idx_out : out centre_index_type; -- feed input to output
u_out : out node_data_type;
closest_n_first_rdy : out std_logic;
point_list_rdy : out std_logic
);
end component;
component dot_product
generic (
SCALE_MUL_RESULT : integer := 0
);
port (
clk : in std_logic;
sclr : in std_logic;
nd : in std_logic;
point_1 : in data_type_ext;
point_2 : in data_type_ext;
result : out coord_type_ext;
rdy : out std_logic
);
end component;
component compute_squared_sums
port (
clk : in std_logic;
sclr : in std_logic;
nd : in std_logic;
u_sum_sq : in coord_type_ext;
u_count : in coord_type_ext;
op1 : in coord_type_ext;
op2 : in coord_type_ext;
rdy : out std_logic;
squared_sums : out coord_type_ext
);
end component;
component resync_search_results
generic (
RESYNC_NODE_DATA : boolean := true;
RESYNC_CNTR_IDX : boolean := true
);
port (
clk : in std_logic;
sclr : in std_logic;
point_list_nd : in std_logic;
point_list_d : in data_type;
point_list_idx : in centre_index_type;
closest_n_first_nd : in std_logic;
max_idx : in centre_index_type;
min_point : in data_type;
min_index : in centre_index_type;
u_in : in node_data_type;
min_point_out : out data_type;
min_index_out : out centre_index_type;
point_list_d_out : out data_type;
point_list_idx_out : out centre_index_type;
u_out : out node_data_type;
rdy : out std_logic;
rdy_last_cycle : out std_logic
);
end component;
component prune_centres
port (
clk : in std_logic;
sclr : in std_logic;
nd : in std_logic;
point : in data_type;
point_list_idx : in centre_index_type;
point_list_d : in data_type; -- assume FIFO interface !!!
bnd_lo : in data_type;
bnd_hi : in data_type;
valid : out std_logic;
point_list_idx_out : out centre_index_type;
result : out std_logic;
rdy : out std_logic;
min_num_centres: out centre_index_type
);
end component;
-- midPoint
signal tmp_u_midPoint : sub_res_type;
signal u_midPoint : data_type;
signal midPoint_rdy : std_logic;
signal node_data_delay_input : node_data_delay_type2;
-- closest centre (zstar)
signal comp_point : data_type_ext;
signal centre_positions_downstream : data_type;
signal centre_indices_downstream : centre_index_type;
signal centre_positions_downstream_rdy : std_logic;
signal tmp_u_downstream : node_data_type;
signal max_idx : centre_index_type;
signal closest_centre : data_type;
signal closest_index : centre_index_type;
signal closest_centre_rdy : std_logic;
-- dot products
signal tmp_wgtCent_scale : data_type_ext;
signal tmp_op2_scale : coord_type_ext;
signal tmp_sum_sq_scale : coord_type_ext;
signal tmp_dot_product_1_2 : coord_type_ext;
signal tmp_dot_product_2_2 : coord_type_ext;
signal tmp_dot_product_1_2_rdy : std_logic;
signal tmp_dot_product_2_2_rdy : std_logic;
-- resync
signal centre_positions_downstream_resync : data_type;
signal centre_indices_downstream_resync : centre_index_type;
signal closest_centre_resync : data_type;
signal closest_index_resync : centre_index_type;
signal tmp_u_downstream_resync : node_data_type;
signal resync_rdy : std_logic;
signal resync_rdy_last_cycle : std_logic;
-- prune test
signal new_k : centre_index_type;
signal prune_test_rdy : std_logic;
signal prune_test_valid : std_logic;
signal prune_test_result : std_logic;
signal prune_test_index_out : centre_index_type;
-- delay node data once again
signal node_data_delay : node_data_delay_type;
signal min_index_delay : centre_index_delay_type;
-- compute squared sums
signal tmp_op1 : coord_type_ext;
signal tmp_op2 : coord_type_ext;
signal tmp_u_count_ext : coord_type_ext;
signal tmp_sum_sq_rdy : std_logic;
signal tmp_sum_sq : coord_type_ext;
signal sum_sq_delay : coord_ext_delay_type;
signal sum_sq_rdy_delay : std_logic_vector(0 to LAT_DIFF-1);
-- write back
signal tmp_leaf_node : std_logic;
signal tmp_dead_end : std_logic;
signal tmp_u_left : node_address_type;
signal tmp_u_right : node_address_type;
signal tmp_final_index : centre_index_type;
begin
-- G0 : for I in 0 to D-1 generate
-- G_FIRST : if I = 0 generate
-- addorsub_inst : addorsub
-- generic map(
-- A_BITWIDTH => COORD_BITWIDTH,
-- B_BITWIDTH => COORD_BITWIDTH,
-- RES_BITWIDTH => COORD_BITWIDTH+1
-- )
-- port map(
-- clk => clk,
-- sclr => sclr,
-- nd => nd,
-- sub => '0',
-- a => u_in.bnd_hi(I),
-- b => u_in.bnd_lo(I),
-- res => tmp_u_midPoint(I),
-- rdy => midPoint_rdy
-- );
-- end generate G_FIRST;
-- G_OTHER : if I > 0 generate
-- addorsub_inst : addorsub
-- generic map(
-- A_BITWIDTH => COORD_BITWIDTH,
-- B_BITWIDTH => COORD_BITWIDTH,
-- RES_BITWIDTH => COORD_BITWIDTH+1
-- )
-- port map(
-- clk => clk,
-- sclr => sclr,
-- nd => nd,
-- sub => '0',
-- a => u_in.bnd_hi(I),
-- b => u_in.bnd_lo(I),
-- res => tmp_u_midPoint(I),
-- rdy => open
-- );
-- end generate G_OTHER;
-- u_midPoint(I) <= tmp_u_midPoint(I)(COORD_BITWIDTH+1-1 downto 1);
-- end generate G0;
--
-- data_delay_input_proc : process(clk)
-- begin
-- if rising_edge(clk) then
-- node_data_delay_input(0) <= u_in;
-- node_data_delay_input(1 to SUB_LAT-1) <= node_data_delay_input(0 to SUB_LAT-2);
-- end if;
-- end process data_delay_input_proc;
--
--
-- -- input muxing
-- comp_point <= node_data_delay_input(SUB_LAT-1).wgtCent WHEN node_data_delay_input(SUB_LAT-1).left = std_logic_vector(to_unsigned(0,NODE_POINTER_BITWIDTH)) AND node_data_delay_input(SUB_LAT-1).right = std_logic_vector(to_unsigned(0,NODE_POINTER_BITWIDTH)) ELSE conv_normal_2_ext(u_midPoint);
--
comp_point <= u_in.wgtCent WHEN u_in.left = std_logic_vector(to_unsigned(0,NODE_POINTER_BITWIDTH)) AND u_in.right = std_logic_vector(to_unsigned(0,NODE_POINTER_BITWIDTH)) ELSE conv_normal_2_ext(u_in.midPoint);
closest_to_point_inst : closest_to_point_top
port map (
clk => clk,
sclr => sclr,
nd => nd,
u_in => u_in,
point => comp_point,
point_list_d => centre_positions_in,
point_list_idx => centre_indices_in,
max_idx => max_idx,
min_point => closest_centre,
min_index => closest_index,
point_list_d_out => centre_positions_downstream,
point_list_idx_out => centre_indices_downstream,
u_out => tmp_u_downstream,
closest_n_first_rdy => closest_centre_rdy,
point_list_rdy => centre_positions_downstream_rdy
);
resync_search_results_inst : resync_search_results
generic map (
RESYNC_NODE_DATA => true,
RESYNC_CNTR_IDX => true
)
port map(
clk => clk,
sclr => sclr,
closest_n_first_nd => closest_centre_rdy,
max_idx => max_idx,
point_list_nd => centre_positions_downstream_rdy,
min_point => closest_centre,
min_index => closest_index,
u_in => tmp_u_downstream,
point_list_d => centre_positions_downstream,
point_list_idx => centre_indices_downstream,
min_point_out => closest_centre_resync,
min_index_out => closest_index_resync,
u_out => tmp_u_downstream_resync,
point_list_d_out => centre_positions_downstream_resync,
point_list_idx_out => centre_indices_downstream_resync,
rdy => resync_rdy,
rdy_last_cycle => resync_rdy_last_cycle
);
G_SCALE : for I in 0 to D-1 generate
tmp_wgtCent_scale(I)(COORD_BITWIDTH_EXT-MUL_FRACTIONAL_BITS-1 downto 0) <= tmp_u_downstream_resync.wgtCent(I)(COORD_BITWIDTH_EXT-1 downto MUL_FRACTIONAL_BITS);
tmp_wgtCent_scale(I)(COORD_BITWIDTH_EXT-1 downto COORD_BITWIDTH_EXT-MUL_FRACTIONAL_BITS) <= (others => tmp_u_downstream_resync.wgtCent(I)(COORD_BITWIDTH_EXT-1));
end generate G_SCALE;
dot_product_inst_1_2 : dot_product
generic map (
SCALE_MUL_RESULT => 0
)
port map (
clk => clk,
sclr => sclr,
nd => resync_rdy_last_cycle,
point_1 => conv_normal_2_ext(closest_centre_resync),
point_2 => tmp_wgtCent_scale,
result => tmp_dot_product_1_2,
rdy => tmp_dot_product_1_2_rdy
);
dot_product_inst_2_2 : dot_product
generic map (
SCALE_MUL_RESULT => 0
)
port map (
clk => clk,
sclr => sclr,
nd => resync_rdy_last_cycle,
point_1 => conv_normal_2_ext(closest_centre_resync),
point_2 => conv_normal_2_ext(closest_centre_resync),
result => tmp_dot_product_2_2,
rdy => tmp_dot_product_2_2_rdy
);
-- feed delay various data/control signals
data_delay_proc : process(clk)
begin
if rising_edge(clk) then
node_data_delay(0) <= tmp_u_downstream_resync;
node_data_delay(1 to LAT_PRUNING_TEST+ADD_LAT_PRUNING-1) <= node_data_delay(0 to LAT_PRUNING_TEST+ADD_LAT_PRUNING-2);
min_index_delay(0) <= closest_index_resync;
min_index_delay(1 to LAT_PRUNING_TEST+ADD_LAT_PRUNING-1) <= min_index_delay(0 to LAT_PRUNING_TEST+ADD_LAT_PRUNING-2);
-- if sclr = '1' then
-- sum_sq_rdy_delay <= (others => '0');
-- else
-- sum_sq_rdy_delay(0) <= tmp_sum_sq_rdy;
-- sum_sq_rdy_delay(1 to LAT_DIFF-1) <= sum_sq_rdy_delay(0 to LAT_DIFF-2);
-- sum_sq_delay(0) <= tmp_sum_sq;
-- sum_sq_delay(1 to LAT_DIFF-1) <= sum_sq_delay(0 to LAT_DIFF-2);
-- end if;
end if;
end process data_delay_proc;
tmp_op1 <= tmp_dot_product_1_2;
tmp_op2 <= tmp_dot_product_2_2;
-- scaling
tmp_op2_scale(COORD_BITWIDTH_EXT-MUL_FRACTIONAL_BITS-1 downto 0) <= tmp_op2(COORD_BITWIDTH_EXT-1 downto MUL_FRACTIONAL_BITS);
tmp_op2_scale(COORD_BITWIDTH_EXT-1 downto COORD_BITWIDTH_EXT-MUL_FRACTIONAL_BITS) <= (others => tmp_op2(COORD_BITWIDTH_EXT-1));
-- input data already scaled
tmp_sum_sq_scale <= node_data_delay(LAT_DOT_PRODUCT-1).sum_sq;
tmp_u_count_ext <= zext(node_data_delay(LAT_DOT_PRODUCT-1).count,COORD_BITWIDTH_EXT);
compute_squared_sums_inst : compute_squared_sums
port map (
clk => clk,
sclr => sclr,
nd => tmp_dot_product_1_2_rdy,
u_sum_sq => tmp_sum_sq_scale, -- node_data_delay(LAT_DOT_PRODUCT-1).sum_sq
u_count => tmp_u_count_ext,
op1 => tmp_op1,
op2 => tmp_op2_scale,
rdy => tmp_sum_sq_rdy,
squared_sums => tmp_sum_sq
);
prune_centres_inst : prune_centres
port map (
clk => clk,
sclr => sclr,
nd => resync_rdy,
point => closest_centre_resync,
point_list_d => centre_positions_downstream_resync,
point_list_idx => centre_indices_downstream_resync,
bnd_lo => tmp_u_downstream_resync.bnd_lo,
bnd_hi => tmp_u_downstream_resync.bnd_hi,
valid => prune_test_valid,
point_list_idx_out => prune_test_index_out,
result => prune_test_result,
rdy => prune_test_rdy,
min_num_centres => new_k
);
tmp_u_left <= node_data_delay(LAT_PRUNING_TEST+ADD_LAT_PRUNING-1).left;
tmp_u_right <= node_data_delay(LAT_PRUNING_TEST+ADD_LAT_PRUNING-1).right;
-- this could be determined much more simply...
tmp_leaf_node <= '1' WHEN tmp_u_left = std_logic_vector(to_unsigned(0,NODE_POINTER_BITWIDTH)) AND tmp_u_right = std_logic_vector(to_unsigned(0,NODE_POINTER_BITWIDTH)) ELSE '0';
tmp_dead_end <= '1' WHEN tmp_leaf_node = '1' OR new_k = to_unsigned(0,INDEX_BITWIDTH) ELSE '0';
tmp_final_index <= min_index_delay(LAT_PRUNING_TEST+ADD_LAT_PRUNING-1);
-- outputs
update_centre_buffer <= tmp_dead_end AND prune_test_rdy; -- same as sum_sq_rdy_delay(LAT_DIFF-1)
final_index_out <= tmp_final_index;
G_LD : if LAT_DIFF > 0 generate
sum_sq_out <= sum_sq_delay(LAT_DIFF-1);
end generate G_LD;
G_NLD : if LAT_DIFF = 0 generate
sum_sq_out <= tmp_sum_sq;
end generate G_NLD;
u_out <= node_data_delay(LAT_PRUNING_TEST+ADD_LAT_PRUNING-1);
rdy <= prune_test_rdy;
dead_end <= tmp_dead_end;
k_out <= new_k;
centre_index_rdy <= prune_test_valid;
centre_index_wr <= prune_test_result;
centre_indices_out <= prune_test_index_out;
end Behavioral;
|
--------------------------------------------------------------------------------
-- FILE: tbDlx
-- DESC: Testbench for DLX
--
-- Author:
-- Create: 2015-05-24
-- Update: 2015-05-24
-- Status: UNTESTED
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.consts.all;
--------------------------------------------------------------------------------
-- ENTITY
--------------------------------------------------------------------------------
entity tbDlx is
end tbDlx;
--------------------------------------------------------------------------------
-- ARCHITECTURE
--------------------------------------------------------------------------------
architecture tb_dlx_arch of tbDlx is
signal clk: std_logic := '0';
signal rst: std_logic := '0';
component Dlx
generic (
ADDR_SIZE : integer := C_SYS_ADDR_SIZE;
DATA_SIZE : integer := C_SYS_DATA_SIZE;
ISTR_SIZE : integer := C_SYS_ISTR_SIZE;
DRCW_SIZE : integer := C_CTR_DRCW_SIZE
);
port (
clk : in std_logic := '0';
rst : in std_logic := '0'; -- Active Low
en_iram: out std_logic:='1';
pc_bus : out std_logic_vector(ADDR_SIZE-1 downto 0):=(others=>'0');
ir_bus : in std_logic_vector(ISTR_SIZE-1 downto 0):=(others=>'0');
en_dram : out std_logic:='1';
addr_bus : out std_logic_vector(ADDR_SIZE-1 downto 0):=(others=>'0');
di_bus : out std_logic_vector(DATA_SIZE-1 downto 0):=(others=>'0');
do_bus : in std_logic_vector(DATA_SIZE-1 downto 0):=(others=>'0');
dr_cw : out std_logic_vector(DRCW_SIZE-1 downto 0):=(others=>'0')
);
end component;
-- Instruction RAM
component InstructionRam is
generic (
ADDR_SIZE : integer := C_SYS_ADDR_SIZE;
ISTR_SIZE : integer := C_SYS_ISTR_SIZE
);
port (
rst : in std_logic;
clk : in std_logic;
en : in std_logic;
addr : in std_logic_vector(ADDR_SIZE-1 downto 0):=(others=>'0');
iout : out std_logic_vector(ISTR_SIZE-1 downto 0)
);
end component;
-- Data RAM
component DataRam is
generic (
DRCW_SIZE : integer := C_CTR_DRCW_SIZE; -- Data RAM Control Word: R/W
ADDR_SIZE : integer := C_SYS_ADDR_SIZE;
DATA_SIZE : integer := C_SYS_DATA_SIZE
);
port (
rst : in std_logic;
clk : in std_logic;
en : in std_logic;
addr : in std_logic_vector(ADDR_SIZE-1 downto 0):=(others=>'0');
din : in std_logic_vector(DATA_SIZE-1 downto 0);
dout : out std_logic_vector(DATA_SIZE-1 downto 0);
dr_cw : in std_logic_vector(DRCW_SIZE-1 downto 0)
);
end component;
constant ADDR_SIZE : integer := C_SYS_ADDR_SIZE;
constant DATA_SIZE : integer := C_SYS_DATA_SIZE;
constant ISTR_SIZE : integer := C_SYS_ISTR_SIZE;
constant DRCW_SIZE : integer := C_CTR_DRCW_SIZE;
signal ir_bus : std_logic_vector(ISTR_SIZE-1 downto 0):=(others=>'0');
signal pc_bus : std_logic_vector(ADDR_SIZE-1 downto 0):=(others=>'0');
signal di_bus : std_logic_vector(DATA_SIZE-1 downto 0):=(others=>'0');
signal do_bus : std_logic_vector(DATA_SIZE-1 downto 0):=(others=>'0');
signal addr_bus : std_logic_vector(ADDR_SIZE-1 downto 0):=(others=>'0');
signal dr_cw : std_logic_vector(DRCW_SIZE-1 downto 0):=(others=>'0');
signal en_iram : std_logic:='1';
signal en_dram : std_logic:='1';
begin
-- DLX Processor
DLX0: Dlx
generic map(ADDR_SIZE,DATA_SIZE,ISTR_SIZE,DRCW_SIZE)
port map (clk, rst, en_iram, pc_bus, ir_bus, en_dram, addr_bus, di_bus, do_bus, dr_cw);
-- Clock generator
PCLOCK : process(clk)
begin
clk <= not(clk) after 0.5 ns;
end process;
-- Reset test
rst <= '0', '1' after 2 ns;
IR0: InstructionRam
generic map(ADDR_SIZE, ISTR_SIZE)
port map(rst, clk, en_iram, pc_bus, ir_bus);
DR0: DataRam
generic map(DRCW_SIZE, ADDR_SIZE, DATA_SIZE)
port map(rst, clk, en_dram, addr_bus, di_bus, do_bus, dr_cw);
end tb_dlx_arch;
--------------------------------------------------------------------------------
-- CONFIGURATION
--------------------------------------------------------------------------------
configuration tb_dlx_cfg of tbDlx is
for tb_dlx_arch
end for;
end tb_dlx_cfg;
|
architecture ARCH of ENTITY is
begin
PROC_1 : process (a, b, c) is
begin
case boolean_1 is
when STATE_1 =>
a <= b;
b <= c;
c <= d;
when others =>
z <= a;
end case;
end process PROC_1;
PROC_2 : process (a, b, c) is
begin
case boolean_1 is
when STATE_1 =>
a <= b;
b <= c;
c <= d;
when STATE_1 =>
a <= b;
b <= c;
c <= d;
when others =>
z <= a;
when others =>
z <= a;
end case;
end process PROC_2;
end architecture ARCH;
|
entity jcore6 is
end entity;
architecture test of jcore6 is
procedure update(signal x : in bit_vector(1 downto 0);
sel : in integer;
signal y : out bit) is
begin
y <= x(sel);
end procedure;
signal s_sel : integer range 0 to 1;
signal s_x : bit_vector(1 downto 0);
signal s_y : bit;
begin
update(s_x, s_sel, s_y);
process is
begin
s_x <= "10";
s_sel <= 1;
wait for 1 ns;
assert s_y = '1';
s_sel <= 0;
wait for 1 ns;
assert s_y = '0';
wait;
end process;
end architecture;
|
entity jcore6 is
end entity;
architecture test of jcore6 is
procedure update(signal x : in bit_vector(1 downto 0);
sel : in integer;
signal y : out bit) is
begin
y <= x(sel);
end procedure;
signal s_sel : integer range 0 to 1;
signal s_x : bit_vector(1 downto 0);
signal s_y : bit;
begin
update(s_x, s_sel, s_y);
process is
begin
s_x <= "10";
s_sel <= 1;
wait for 1 ns;
assert s_y = '1';
s_sel <= 0;
wait for 1 ns;
assert s_y = '0';
wait;
end process;
end architecture;
|
entity jcore6 is
end entity;
architecture test of jcore6 is
procedure update(signal x : in bit_vector(1 downto 0);
sel : in integer;
signal y : out bit) is
begin
y <= x(sel);
end procedure;
signal s_sel : integer range 0 to 1;
signal s_x : bit_vector(1 downto 0);
signal s_y : bit;
begin
update(s_x, s_sel, s_y);
process is
begin
s_x <= "10";
s_sel <= 1;
wait for 1 ns;
assert s_y = '1';
s_sel <= 0;
wait for 1 ns;
assert s_y = '0';
wait;
end process;
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity shift_unit is
port(
a : in std_logic_vector(31 downto 0);
b : in std_logic_vector( 4 downto 0);
op : in std_logic_vector( 2 downto 0);
r : out std_logic_vector(31 downto 0)
);
end shift_unit;
architecture synth of shift_unit is
signal rotate, shift_left, shift_right : std_logic_vector(31 downto 0);
begin
-- selection between the operations
sel: process(op, rotate, shift_left, shift_right)
begin
case op(1 downto 0) is
when "00" | "01" => r <= rotate;
when "10" => r <= shift_left;
when "11" => r <= shift_right;
when others =>
end case;
end process;
-- rotate left or right
ror_rol: process(a, b, op)
variable b_s : std_logic_vector( 4 downto 0);
variable v : std_logic_vector(31 downto 0);
begin
-- we invert b if we want to rotate to the right:
-- (a rol b <=> a ror (-b))
-- When we rotate to the right op(0)='1'
b_s := (b xor (4 downto 0 => op(0))) + op(0);
v := a;
for i in 0 to 4 loop
if(b_s(i)='1')then
v := v(31-2**i downto 0) & v(31 downto 32-2**i);
end if;
end loop;
rotate <= v;
end process;
-- shift_right
srl_sra: process(a, b, op)
variable sign : std_logic;
variable v : std_logic_vector(31 downto 0);
begin
-- if op(2)='1' we have to replicate the sign of the operand a.
sign := op(2) and a(31);
v := a;
for i in 0 to 4 loop
if(b(i)='1')then
v := ((2**i)-1 downto 0 => sign) & v(31 downto 2**i);
end if;
end loop;
shift_right<= v;
end process;
-- shift_left
sh_left: process(a, b)
variable v : std_logic_vector(31 downto 0);
begin
v := a;
for i in 0 to 4 loop
if(b(i)='1')then
v := v(31-2**i downto 0) & ((2**i)-1 downto 0 => '0');
end if;
end loop;
shift_left<= v;
end process;
end synth;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
-- Entity: ahb2mig_ztex
-- File: ahb2mig_ztex.vhd
-- Author: Jiri Gaisler - Aeroflex Gaisler AB
--
-- This is a AHB-2.0 interface for the Xilinx Spartan-6 MIG.
-- One bidir 32-bit port is used for the main AHB bus.
-------------------------------------------------------------------------------
-- Patched for ZTEX: Oleg Belousov <[email protected]>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
entity ahb2mig_ztex is
generic(
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#f00#;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
MEMCLK_PERIOD : integer := 5000
);
port(
mcb3_dram_dq : inout std_logic_vector(15 downto 0);
mcb3_dram_udqs : inout std_logic;
mcb3_dram_udqs_n : inout std_logic;
mcb3_dram_dqs : inout std_logic;
mcb3_dram_dqs_n : inout std_logic;
mcb3_dram_a : out std_logic_vector(12 downto 0);
mcb3_dram_ba : out std_logic_vector(2 downto 0);
mcb3_dram_cke : out std_logic;
mcb3_dram_ras_n : out std_logic;
mcb3_dram_cas_n : out std_logic;
mcb3_dram_we_n : out std_logic;
mcb3_dram_dm : out std_logic;
mcb3_dram_udm : out std_logic;
mcb3_dram_ck : out std_logic;
mcb3_dram_ck_n : out std_logic;
mcb3_rzq : inout std_logic;
mcb3_zio : inout std_logic;
ahbso : out ahb_slv_out_type;
ahbsi : in ahb_slv_in_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
calib_done : out std_logic;
test_error : out std_logic;
rst_n_syn : in std_logic;
rst_n_async : in std_logic;
clk_amba : in std_logic;
clk_mem : in std_logic
);
end ;
architecture rtl of ahb2mig_ztex is
component mig_37
generic(
C3_P0_MASK_SIZE : integer := 4;
C3_P0_DATA_PORT_SIZE : integer := 32;
C3_P1_MASK_SIZE : integer := 4;
C3_P1_DATA_PORT_SIZE : integer := 32;
C3_MEMCLK_PERIOD : integer := 5000;
C3_RST_ACT_LOW : integer := 0;
C3_INPUT_CLK_TYPE : string := "SINGLE_ENDED";
C3_CALIB_SOFT_IP : string := "TRUE";
C3_SIMULATION : string := "FALSE";
DEBUG_EN : integer := 0;
C3_MEM_ADDR_ORDER : string := "ROW_BANK_COLUMN";
C3_NUM_DQ_PINS : integer := 16;
C3_MEM_ADDR_WIDTH : integer := 13;
C3_MEM_BANKADDR_WIDTH : integer := 3
);
port (
mcb3_dram_dq : inout std_logic_vector(C3_NUM_DQ_PINS-1 downto 0);
mcb3_dram_a : out std_logic_vector(C3_MEM_ADDR_WIDTH-1 downto 0);
mcb3_dram_ba : out std_logic_vector(C3_MEM_BANKADDR_WIDTH-1 downto 0);
mcb3_dram_cke : out std_logic;
mcb3_dram_ras_n : out std_logic;
mcb3_dram_cas_n : out std_logic;
mcb3_dram_we_n : out std_logic;
mcb3_dram_dm : out std_logic;
mcb3_dram_udqs : inout std_logic;
mcb3_dram_udqs_n : inout std_logic;
mcb3_rzq : inout std_logic;
mcb3_zio : inout std_logic;
mcb3_dram_udm : out std_logic;
c3_sys_clk : in std_logic;
c3_sys_rst_n : in std_logic;
c3_calib_done : out std_logic;
c3_clk0 : out std_logic;
c3_rst0 : out std_logic;
mcb3_dram_dqs : inout std_logic;
mcb3_dram_dqs_n : inout std_logic;
mcb3_dram_ck : out std_logic;
mcb3_dram_ck_n : out std_logic;
c3_p0_cmd_clk : in std_logic;
c3_p0_cmd_en : in std_logic;
c3_p0_cmd_instr : in std_logic_vector(2 downto 0);
c3_p0_cmd_bl : in std_logic_vector(5 downto 0);
c3_p0_cmd_byte_addr : in std_logic_vector(29 downto 0);
c3_p0_cmd_empty : out std_logic;
c3_p0_cmd_full : out std_logic;
c3_p0_wr_clk : in std_logic;
c3_p0_wr_en : in std_logic;
c3_p0_wr_mask : in std_logic_vector(C3_P0_MASK_SIZE - 1 downto 0);
c3_p0_wr_data : in std_logic_vector(C3_P0_DATA_PORT_SIZE - 1 downto 0);
c3_p0_wr_full : out std_logic;
c3_p0_wr_empty : out std_logic;
c3_p0_wr_count : out std_logic_vector(6 downto 0);
c3_p0_wr_underrun : out std_logic;
c3_p0_wr_error : out std_logic;
c3_p0_rd_clk : in std_logic;
c3_p0_rd_en : in std_logic;
c3_p0_rd_data : out std_logic_vector(C3_P0_DATA_PORT_SIZE - 1 downto 0);
c3_p0_rd_full : out std_logic;
c3_p0_rd_empty : out std_logic;
c3_p0_rd_count : out std_logic_vector(6 downto 0);
c3_p0_rd_overflow : out std_logic;
c3_p0_rd_error : out std_logic
);
end component;
type bstate_type is (idle, start, read1);
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_MIGDDR2, 0, 0, 0),
4 => ahb_membar(haddr, '1', '1', hmask),
-- 5 => ahb_iobar(ioaddr, iomask),
others => zero32);
constant pconfig : apb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_MIGDDR2, 0, 0, 0),
1 => apb_iobar(paddr, pmask));
type reg_type is record
bstate : bstate_type;
cmd_bl : std_logic_vector(5 downto 0);
wr_count : std_logic_vector(6 downto 0);
rd_cnt : std_logic_vector(5 downto 0);
hready : std_logic;
hsel : std_logic;
hwrite : std_logic;
htrans : std_logic_vector(1 downto 0);
hburst : std_logic_vector(2 downto 0);
hsize : std_logic_vector(2 downto 0);
hrdata : std_logic_vector(31 downto 0);
haddr : std_logic_vector(31 downto 0);
hmaster : std_logic_vector(3 downto 0);
end record;
type mcb_type is record
cmd_en : std_logic;
cmd_instr : std_logic_vector(2 downto 0);
cmd_empty : std_logic;
cmd_full : std_logic;
cmd_bl : std_logic_vector(5 downto 0);
cmd_byte_addr : std_logic_vector(29 downto 0);
wr_full : std_logic;
wr_empty : std_logic;
wr_underrun : std_logic;
wr_error : std_logic;
wr_mask : std_logic_vector(3 downto 0);
wr_en : std_logic;
wr_data : std_logic_vector(31 downto 0);
wr_count : std_logic_vector(6 downto 0);
rd_data : std_logic_vector(31 downto 0);
rd_full : std_logic;
rd_empty : std_logic;
rd_count : std_logic_vector(6 downto 0);
rd_overflow : std_logic;
rd_error : std_logic;
rd_en : std_logic;
end record;
signal r, rin : reg_type;
signal i : mcb_type;
begin
comb: process( rst_n_syn, r, ahbsi, i )
variable v : reg_type;
variable wmask : std_logic_vector(3 downto 0);
variable wr_en : std_logic;
variable cmd_en : std_logic;
variable cmd_instr : std_logic_vector(2 downto 0);
variable rd_en : std_logic;
variable cmd_bl : std_logic_vector(5 downto 0);
variable hwdata : std_logic_vector(31 downto 0);
variable readdata : std_logic_vector(31 downto 0);
begin
v := r; wr_en := '0'; cmd_en := '0'; cmd_instr := "000";
rd_en := '0';
if (ahbsi.hready = '1') then
if (ahbsi.hsel(hindex) and ahbsi.htrans(1)) = '1' then
v.hsel := '1'; v.hburst := ahbsi.hburst;
v.hwrite := ahbsi.hwrite; v.hsize := ahbsi.hsize;
v.hmaster := ahbsi.hmaster;
v.hready := '0';
if ahbsi.htrans(0) = '0' then v.haddr := ahbsi.haddr; end if;
else
v.hsel := '0'; v.hready := '1';
end if;
v.htrans := ahbsi.htrans;
end if;
hwdata := ahbsi.hwdata(15 downto 0) & ahbsi.hwdata(31 downto 16);
case r.hsize(1 downto 0) is
when "00" => wmask := not decode(r.haddr(1 downto 0));
case r.haddr(1 downto 0) is
when "00" => wmask := "1101";
when "01" => wmask := "1110";
when "10" => wmask := "0111";
when others => wmask := "1011";
end case;
when "01" => wmask := not decode(r.haddr(1 downto 0));
wmask(3) := wmask(2); wmask(1) := wmask(0);
when others => wmask := "0000";
end case;
i.wr_mask <= wmask;
cmd_bl := r.cmd_bl;
case r.bstate is
when idle =>
if v.hsel = '1' then
v.bstate := start;
v.hready := ahbsi.hwrite and not i.cmd_full and not i.wr_full;
v.haddr := ahbsi.haddr;
end if;
v.cmd_bl := (others => '0');
when start =>
if r.hwrite = '1' then
v.haddr := r.haddr;
if r.hready = '1' then
v.cmd_bl := r.cmd_bl + 1; v.hready := '1'; wr_en := '1';
if (ahbsi.htrans /= "11") then
if v.hsel = '1' then
if (ahbsi.hwrite = '0') or (i.wr_count >= "0000100") then
v.hready := '0';
else v.hready := '1'; end if;
else v.bstate := idle; end if;
v.cmd_bl := (others => '0'); v.haddr := ahbsi.haddr;
cmd_en := '1';
elsif (i.cmd_full = '1') then
v.hready := '0';
elsif (i.wr_count >= "0101111") then
v.hready := '0'; cmd_en := '1';
v.cmd_bl := (others => '0'); v.haddr := ahbsi.haddr;
end if;
else
if (i.cmd_full = '0') and (i.wr_count <= "0001111") then
v.hready := '1';
end if;
end if;
else
if i.cmd_full = '0' then
cmd_en := '1'; cmd_instr(0) := '1';
v.cmd_bl := "000" & not r.haddr(4 downto 2);
cmd_bl := v.cmd_bl;
v.bstate := read1;
end if;
end if;
when read1 =>
v.hready := '0';
if (r.rd_cnt = "000000") then -- flush data from previous line
if (i.rd_empty = '0') or ((r.hready = '1') and (ahbsi.htrans /= "11")) then
v.hrdata(31 downto 0) := i.rd_data(15 downto 0) & i.rd_data(31 downto 16);
v.hready := '1';
if (i.rd_empty = '0') then v.cmd_bl := r.cmd_bl - 1; rd_en := '1'; end if;
if (r.cmd_bl = "000000") or (ahbsi.htrans /= "11") then
if (ahbsi.hsel(hindex) = '1') and (ahbsi.htrans = "10") and (r.hready = '1') then
v.bstate := start; v.hready := ahbsi.hwrite and not i.cmd_full and not i.wr_full;
v.cmd_bl := (others => '0');
else
v.bstate := idle;
end if;
if (i.rd_empty = '1') then v.rd_cnt := r.cmd_bl + 1;
else v.rd_cnt := r.cmd_bl; end if;
end if;
end if;
end if;
when others =>
end case;
readdata := (others => '0');
-- case apbi.paddr(5 downto 2) is
-- when "0000" => readdata(nbits-1 downto 0) := r.din2;
-- when "0001" => readdata(nbits-1 downto 0) := r.dout;
-- when others =>
-- end case;
readdata(20 downto 0) :=
i.rd_error & i.rd_overflow & i.wr_error & i.wr_underrun &
i.cmd_full & i.rd_full & i.rd_empty & i.wr_full & i.wr_empty &
r.rd_cnt & r.cmd_bl;
if (r.rd_cnt /= "000000") and (i.rd_empty = '0') then
rd_en := '1'; v.rd_cnt := r.rd_cnt - 1;
end if;
if rst_n_syn = '0' then
v.rd_cnt := "000000"; v.bstate := idle; v.hready := '1';
end if;
rin <= v;
apbo.prdata <= readdata;
i.rd_en <= rd_en;
i.wr_en <= wr_en;
i.cmd_bl <= cmd_bl;
i.cmd_en <= cmd_en;
i.cmd_instr <= cmd_instr;
i.wr_data <= hwdata;
end process;
i.cmd_byte_addr <= r.haddr(29 downto 2) & "00";
ahbso.hready <= r.hready;
ahbso.hresp <= "00"; --r.hresp;
ahbso.hrdata <= r.hrdata;
ahbso.hconfig <= hconfig;
ahbso.hirq <= (others => '0');
ahbso.hindex <= hindex;
ahbso.hsplit <= (others => '0');
apbo.pirq <= (others => '0');
apbo.pindex <= pindex;
apbo.pconfig <= pconfig;
regs : process(clk_amba)
begin
if rising_edge(clk_amba) then
r <= rin;
end if;
end process;
MCB_inst : entity work.mig_37 generic map(
C3_RST_ACT_LOW => 1,
-- pragma translate_off
C3_SIMULATION => "TRUE",
-- pragma translate_on
C3_MEM_ADDR_ORDER => "BANK_ROW_COLUMN",
C3_MEMCLK_PERIOD => MEMCLK_PERIOD
)
port map (
mcb3_dram_dq => mcb3_dram_dq,
mcb3_rzq => mcb3_rzq,
mcb3_zio => mcb3_zio,
mcb3_dram_udqs => mcb3_dram_udqs,
mcb3_dram_udqs_n => mcb3_dram_udqs_n,
mcb3_dram_dqs => mcb3_dram_dqs,
mcb3_dram_dqs_n => mcb3_dram_dqs_n,
mcb3_dram_a => mcb3_dram_a,
mcb3_dram_ba => mcb3_dram_ba,
mcb3_dram_cke => mcb3_dram_cke,
mcb3_dram_ras_n => mcb3_dram_ras_n,
mcb3_dram_cas_n => mcb3_dram_cas_n,
mcb3_dram_we_n => mcb3_dram_we_n,
mcb3_dram_dm => mcb3_dram_dm,
mcb3_dram_udm => mcb3_dram_udm,
mcb3_dram_ck => mcb3_dram_ck,
mcb3_dram_ck_n => mcb3_dram_ck_n,
c3_sys_clk => clk_mem,
c3_sys_rst_n => rst_n_async,
c3_calib_done => calib_done,
c3_clk0 => open,
c3_rst0 => open,
c3_p0_cmd_clk => clk_amba,
c3_p0_cmd_en => i.cmd_en,
c3_p0_cmd_instr => i.cmd_instr,
c3_p0_cmd_bl => i.cmd_bl,
c3_p0_cmd_byte_addr => i.cmd_byte_addr,
c3_p0_cmd_empty => i.cmd_empty,
c3_p0_cmd_full => i.cmd_full,
c3_p0_wr_clk => clk_amba,
c3_p0_wr_en => i.wr_en,
c3_p0_wr_mask => i.wr_mask,
c3_p0_wr_data => i.wr_data,
c3_p0_wr_full => i.wr_full,
c3_p0_wr_empty => i.wr_empty,
c3_p0_wr_count => i.wr_count,
c3_p0_wr_underrun => i.wr_underrun,
c3_p0_wr_error => i.wr_error,
c3_p0_rd_clk => clk_amba,
c3_p0_rd_en => i.rd_en,
c3_p0_rd_data => i.rd_data,
c3_p0_rd_full => i.rd_full,
c3_p0_rd_empty => i.rd_empty,
c3_p0_rd_count => i.rd_count,
c3_p0_rd_overflow => i.rd_overflow,
c3_p0_rd_error => i.rd_error
);
end;
|
---------------------------------------------------------------------
-- Copyright (C) 2016 Siavoosh Payandeh Azad
--
-- Network interface: Its an interrupt based memory mapped I/O for sending and recieving packets.
-- the data that is sent to NI should be of the following form:
-- FIRST write: 4bit source(31-28), 4 bit destination(27-14), 8bit packet length(23-16)
-- Body write: 28 bit data(27-0)
-- Last write: 28 bit data(27-0)
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use IEEE.NUMERIC_STD.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.mlite_pack.all;
use ieee.std_logic_misc.all;
entity NI is
generic(current_address : integer := 10; -- the current node's address
SHMU_address : integer := 0;
reserved_address : std_logic_vector(29 downto 0) := "000000000000000001111111111111"; -- Behrad: NI's reserved address ?
flag_address : std_logic_vector(29 downto 0) := "000000000000000010000000000000"; -- reserved address for the memory mapped I/O
counter_address : std_logic_vector(29 downto 0) := "000000000000000010000000000001";
reconfiguration_address : std_logic_vector(29 downto 0) := "000000000000000010000000000010"; -- reserved address for reconfiguration register
self_diagnosis_address : std_logic_vector(29 downto 0) := "000000000000000010000000000011"); -- reserved address for self diagnosis register
port(clk : in std_logic;
reset : in std_logic;
enable : in std_logic;
write_byte_enable : in std_logic_vector(3 downto 0);
address : in std_logic_vector(31 downto 2);
data_write : in std_logic_vector(31 downto 0);
data_read : out std_logic_vector(31 downto 0);
-- Flags used by JNIFR and JNIFW instructions
--NI_read_flag : out std_logic; -- One if the N2P fifo is empty. No read should be performed if one.
--NI_write_flag : out std_logic; -- One if P2N fifo is full. no write should be performed if one.
-- interrupt signal: generated evertime a packet is recieved!
irq_out : out std_logic;
-- signals for sending packets to network
credit_in : in std_logic;
valid_out: out std_logic;
TX: out std_logic_vector(31 downto 0); -- data sent to the NoC
-- signals for reciving packets from the network
credit_out : out std_logic;
valid_in: in std_logic;
RX: in std_logic_vector(31 downto 0); -- data recieved form the NoC
-- fault information signals from the router
link_faults: in std_logic_vector(4 downto 0);
turn_faults: in std_logic_vector(19 downto 0);
Rxy_reconf_PE: out std_logic_vector(7 downto 0);
Cx_reconf_PE: out std_logic_vector(3 downto 0); -- if you are not going to update Cx you should write all ones! (it will be and will the current Cx bits)
Reconfig_command : out std_logic
);
end; --entity NI
architecture logic of NI is
-- packet format:
-- the parity bit is calculated by the NI and the processor has no control over it
-- flit type is generated by the NI and process has no control over it
-- header flit
-- 32 3bits 14 bits 14 bits 1bit 0
-- .----------------------------------------------------------------------.
-- | flit type| SOURCE ADDRESS | DESTINATION ADDRESS |parity bit |
-- '----------------------------------------------------------------------'
-- SOURCE ADDRESS is added automatically by the NI (the processor has no control over it)
-- DESTINATION ADDRESS is writen in the first write by the PE in FIFO_Data_out(13 downto 0)
-- body flit 1
-- 32 3bits 14 bits 14 bits 1bit 0
-- .----------------------------------------------------------------------.
-- | flit type| PACKET LENGTH | PACKET ID |parity bit |
-- '----------------------------------------------------------------------'
-- PACEKT ID is determined and added by the NI (the processor has no control over it)
-- PACKET LENGTH is written in the 2nd write by PE in FIFO_Data_out(27 downto 14)
-- other body flits
-- 32 3bits 28 bits 1bit 0
-- .----------------------------------------------------------------------.
-- | flit type| PAYLOAD DATA |parity bit |
-- '----------------------------------------------------------------------'
-- PAYLOAD DATA is written by the PE in FIFO_Data_out(27 downto 0)
-- Tail flits
-- 32 3bits 28 bits 1bit 0
-- .----------------------------------------------------------------------.
-- | flit type| PAYLOAD DATA |parity bit |
-- '----------------------------------------------------------------------'
-- PAYLOAD DATA is written by the PE in FIFO_Data_out(27 downto 0)
-- all the following signals are for sending data from processor to NoC
signal storage, storage_in : std_logic_vector(31 downto 0);
signal valid_data_in, valid_data: std_logic;
signal old_address: std_logic_vector(31 downto 2); -- Behrad: What is old address ?
signal P2N_FIFO_read_pointer, P2N_FIFO_read_pointer_in, P2N_FIFO_write_pointer, P2N_FIFO_write_pointer_in: std_logic_vector(3 downto 0);
signal P2N_write_en: std_logic;
signal P2N_FIFO_MEM_1, P2N_FIFO_MEM_1_in : std_logic_vector(31 downto 0);
signal P2N_FIFO_MEM_2, P2N_FIFO_MEM_2_in : std_logic_vector(31 downto 0);
signal P2N_FIFO_MEM_3, P2N_FIFO_MEM_3_in : std_logic_vector(31 downto 0);
signal P2N_FIFO_MEM_4, P2N_FIFO_MEM_4_in : std_logic_vector(31 downto 0);
signal P2N_full, P2N_empty: std_logic;
signal credit_counter_in, credit_counter_out: std_logic_vector(1 downto 0);
signal packet_counter_in, packet_counter_out: std_logic_vector(13 downto 0);
signal packet_length_counter_in, packet_length_counter_out: std_logic_vector(13 downto 0);
signal grant : std_logic;
type STATE_TYPE IS (IDLE, HEADER_FLIT, BODY_FLIT_1, BODY_FLIT, TAIL_FLIT, DIAGNOSIS_HEADER, DIAGNOSIS_BODY, DIAGNOSIS_BODY_1, DIAGNOSIS_TAIL);
signal state, state_in : STATE_TYPE := IDLE;
signal FIFO_Data_out : std_logic_vector(31 downto 0);
signal flag_register, flag_register_in : std_logic_vector(31 downto 0);
-- all the following signals are for sending the packets from NoC to processor
signal N2P_FIFO_MEM_1, N2P_FIFO_MEM_1_in : std_logic_vector(31 downto 0);
signal N2P_FIFO_MEM_2, N2P_FIFO_MEM_2_in : std_logic_vector(31 downto 0);
signal N2P_FIFO_MEM_3, N2P_FIFO_MEM_3_in : std_logic_vector(31 downto 0);
signal N2P_FIFO_MEM_4, N2P_FIFO_MEM_4_in : std_logic_vector(31 downto 0);
signal N2P_Data_out, data_read_in : std_logic_vector(31 downto 0);
signal N2P_FIFO_read_pointer, N2P_FIFO_read_pointer_in: std_logic_vector(3 downto 0);
signal N2P_FIFO_write_pointer, N2P_FIFO_write_pointer_in: std_logic_vector(3 downto 0);
signal N2P_full, N2P_empty: std_logic;
signal N2P_read_en, N2P_read_en_in, N2P_write_en: std_logic;
signal counter_register_in, counter_register : std_logic_vector(1 downto 0);
signal fault_info, fault_info_in: std_logic_vector(24 downto 0);
signal sent_info, fault_info_ready, fault_info_ready_in: std_logic;
signal self_diagnosis_reg_out, self_diagnosis_reg_in: std_logic_vector(31 downto 0);
signal self_diagnosis_flag, self_diagnosis_flag_in: std_logic;
begin
process(clk, enable, write_byte_enable) begin
if reset = '1' then
storage <= (others => '0');
valid_data <= '0';
P2N_FIFO_read_pointer <= "0001";
P2N_FIFO_write_pointer <= "0001";
P2N_FIFO_MEM_1 <= (others=>'0');
P2N_FIFO_MEM_2 <= (others=>'0');
P2N_FIFO_MEM_3 <= (others=>'0');
P2N_FIFO_MEM_4 <= (others=>'0');
credit_counter_out <= "11";
packet_length_counter_out <= (others=>'0');
state <= IDLE;
packet_counter_out <= (others=>'0');
------------------------------------------------
N2P_FIFO_MEM_1 <= (others=>'0');
N2P_FIFO_MEM_2 <= (others=>'0');
N2P_FIFO_MEM_3 <= (others=>'0');
N2P_FIFO_MEM_4 <= (others=>'0');
N2P_FIFO_read_pointer <= "0001";
N2P_FIFO_write_pointer <= "0001";
credit_out <= '0';
counter_register <= (others => '0');
N2P_read_en <= '0';
flag_register <= (others =>'0');
old_address <= (others =>'0');
fault_info <= (others => '0');
fault_info_ready <= '0';
self_diagnosis_reg_out <= (others => '0');
self_diagnosis_flag <= '0';
elsif clk'event and clk = '1' then
old_address <= address;
P2N_FIFO_write_pointer <= P2N_FIFO_write_pointer_in;
P2N_FIFO_read_pointer <= P2N_FIFO_read_pointer_in;
credit_counter_out <= credit_counter_in;
packet_length_counter_out <= packet_length_counter_in;
valid_data <= valid_data_in;
if P2N_write_en = '1' then
--write into the memory
P2N_FIFO_MEM_1 <= P2N_FIFO_MEM_1_in;
P2N_FIFO_MEM_2 <= P2N_FIFO_MEM_2_in;
P2N_FIFO_MEM_3 <= P2N_FIFO_MEM_3_in;
P2N_FIFO_MEM_4 <= P2N_FIFO_MEM_4_in;
end if;
packet_counter_out <= packet_counter_in;
if write_byte_enable /= "0000" then
storage <= storage_in;
end if;
state <= state_in;
------------------------------------------------
if N2P_write_en = '1' then
--write into the memory
N2P_FIFO_MEM_1 <= N2P_FIFO_MEM_1_in;
N2P_FIFO_MEM_2 <= N2P_FIFO_MEM_2_in;
N2P_FIFO_MEM_3 <= N2P_FIFO_MEM_3_in;
N2P_FIFO_MEM_4 <= N2P_FIFO_MEM_4_in;
end if;
counter_register <= counter_register_in;
N2P_FIFO_write_pointer <= N2P_FIFO_write_pointer_in;
N2P_FIFO_read_pointer <= N2P_FIFO_read_pointer_in;
credit_out <= '0';
N2P_read_en <= N2P_read_en_in;
if N2P_read_en = '1' then
credit_out <= '1';
end if;
flag_register <= flag_register_in;
fault_info <= fault_info_in;
fault_info_ready <= fault_info_ready_in;
self_diagnosis_reg_out <= self_diagnosis_reg_in;
self_diagnosis_flag <= self_diagnosis_flag_in;
end if;
end process;
-- everything bellow this line is pure combinatorial!
---------------------------------------------------------------------------------------
--below this is code for communication from PE 2 NoC
-- Process used for sending reconfiguration command from PE to router (which is part of NoC)
process(enable, address, write_byte_enable) begin
-- Some initializations
Reconfig_command <= '0';
Rxy_reconf_PE <= (others =>'0');
Cx_reconf_PE <= (others =>'0');
if address = reconfiguration_address and enable = '1' then
if write_byte_enable /= "0000" then
-- In this case, data_write definitely includes the connectivity bits and routing bits for
-- reconfiguring LBDR logic.
Rxy_reconf_PE <= data_write(7 downto 0); -- Rxy is 8 bits long
Cx_reconf_PE <= data_write(11 downto 8); -- Cx is 4 bits long
Reconfig_command <= '1';
end if;
end if;
end process;
process(write_byte_enable, enable, address, storage, data_write, valid_data, P2N_write_en) begin
storage_in <= storage ;
valid_data_in <= valid_data;
-- If PE wants to send data to NoC via NI (data is valid)
if enable = '1' and address = reserved_address then
if write_byte_enable /= "0000" then
valid_data_in <= '1';
end if;
-- Behrad: So according to Plasma, is write_byte_enable always one-hot ?
-- (of course it can also be "0000")
if write_byte_enable(0) = '1' then
storage_in(7 downto 0) <= data_write(7 downto 0);
end if;
if write_byte_enable(1) = '1' then
storage_in(15 downto 8) <= data_write(15 downto 8);
end if;
if write_byte_enable(2) = '1' then
storage_in(23 downto 16) <= data_write(23 downto 16);
end if;
if write_byte_enable(3) = '1' then
storage_in(31 downto 24) <= data_write(31 downto 24);
end if;
end if;
if P2N_write_en = '1' then
valid_data_in <= '0';
end if;
end process;
-- Process for storing in FIFO (based on the position write pointer is pointing to)
-- Write pointer is encoded as one-hot!
process(storage, P2N_FIFO_write_pointer, P2N_FIFO_MEM_1, P2N_FIFO_MEM_2, P2N_FIFO_MEM_3, P2N_FIFO_MEM_4)begin
case(P2N_FIFO_write_pointer) is
when "0001" => P2N_FIFO_MEM_1_in <= storage; P2N_FIFO_MEM_2_in <= P2N_FIFO_MEM_2; P2N_FIFO_MEM_3_in <= P2N_FIFO_MEM_3; P2N_FIFO_MEM_4_in <= P2N_FIFO_MEM_4;
when "0010" => P2N_FIFO_MEM_1_in <= P2N_FIFO_MEM_1; P2N_FIFO_MEM_2_in <= storage; P2N_FIFO_MEM_3_in <= P2N_FIFO_MEM_3; P2N_FIFO_MEM_4_in <= P2N_FIFO_MEM_4;
when "0100" => P2N_FIFO_MEM_1_in <= P2N_FIFO_MEM_1; P2N_FIFO_MEM_2_in <= P2N_FIFO_MEM_2; P2N_FIFO_MEM_3_in <= storage; P2N_FIFO_MEM_4_in <= P2N_FIFO_MEM_4;
when "1000" => P2N_FIFO_MEM_1_in <= P2N_FIFO_MEM_1; P2N_FIFO_MEM_2_in <= P2N_FIFO_MEM_2; P2N_FIFO_MEM_3_in <= P2N_FIFO_MEM_3; P2N_FIFO_MEM_4_in <= storage;
when others => P2N_FIFO_MEM_1_in <= P2N_FIFO_MEM_1; P2N_FIFO_MEM_2_in <= P2N_FIFO_MEM_2; P2N_FIFO_MEM_3_in <= P2N_FIFO_MEM_3; P2N_FIFO_MEM_4_in <= P2N_FIFO_MEM_4;
end case ;
end process;
-- Process for reading from FIFO (based on the position read pointer is pointing to)
-- read pointer is encoded as one-hot!
process(P2N_FIFO_read_pointer, P2N_FIFO_MEM_1, P2N_FIFO_MEM_2, P2N_FIFO_MEM_3, P2N_FIFO_MEM_4)begin
case( P2N_FIFO_read_pointer ) is
when "0001" => FIFO_Data_out <= P2N_FIFO_MEM_1;
when "0010" => FIFO_Data_out <= P2N_FIFO_MEM_2;
when "0100" => FIFO_Data_out <= P2N_FIFO_MEM_3;
when "1000" => FIFO_Data_out <= P2N_FIFO_MEM_4;
when others => FIFO_Data_out <= P2N_FIFO_MEM_1;
end case ;
end process;
-- Write pointer update process (after each write operation, write pointer is rotated one bit to the left)
process(P2N_write_en, P2N_FIFO_write_pointer)begin
if P2N_write_en = '1' then
P2N_FIFO_write_pointer_in <= P2N_FIFO_write_pointer(2 downto 0) & P2N_FIFO_write_pointer(3);
else
P2N_FIFO_write_pointer_in <= P2N_FIFO_write_pointer;
end if;
end process;
-- Read pointer update process (after each read operation, read pointer is rotated one bit to the left)
process(P2N_FIFO_read_pointer, grant, fault_info_ready)begin
P2N_FIFO_read_pointer_in <= P2N_FIFO_read_pointer;
if grant = '1' and fault_info_ready = '0' then -- Behrad: so grant here works somehow like read_en signal for FIFO ?
P2N_FIFO_read_pointer_in <= P2N_FIFO_read_pointer(2 downto 0) & P2N_FIFO_read_pointer(3);
end if;
end process;
process(P2N_full, valid_data) begin
if valid_data = '1' and P2N_full ='0' then
P2N_write_en <= '1';
else
P2N_write_en <= '0';
end if;
end process;
-- Process for updating full and empty signals
process(P2N_FIFO_write_pointer, P2N_FIFO_read_pointer) begin
P2N_empty <= '0';
P2N_full <= '0';
if P2N_FIFO_read_pointer = P2N_FIFO_write_pointer then
P2N_empty <= '1';
end if;
if P2N_FIFO_write_pointer = P2N_FIFO_read_pointer(0) & P2N_FIFO_read_pointer(3 downto 1) then
P2N_full <= '1';
end if;
end process;
process (credit_in, credit_counter_out, grant)begin
credit_counter_in <= credit_counter_out;
if credit_in = '1' and grant = '1' then
credit_counter_in <= credit_counter_out;
elsif credit_in = '1' and credit_counter_out < 3 then
credit_counter_in <= credit_counter_out + 1;
elsif grant = '1' and credit_counter_out > 0 then
credit_counter_in <= credit_counter_out - 1;
end if;
end process;
-- flag setting and clearing for self diagnosis
process(link_faults, turn_faults, self_diagnosis_flag, old_address)begin
if (link_faults /= "00000" or turn_faults /= "00000000000000000000") and SHMU_address = current_address then
self_diagnosis_flag_in <= '1';
elsif old_address = self_diagnosis_address then
self_diagnosis_flag_in <= '0';
else
self_diagnosis_flag_in <= self_diagnosis_flag;
end if;
end process;
-- handling fault information!
process(link_faults, turn_faults, sent_info, fault_info_ready, fault_info)begin
self_diagnosis_reg_in <= self_diagnosis_reg_out;
-- If current node is not SHMU, we need to send fault information to SHMU
if (link_faults /= "00000" or turn_faults /= "00000000") and SHMU_address /= current_address then
fault_info_in <= turn_faults & link_faults;
fault_info_ready_in <= '1';
-- If current node is SHMU, we handle it locally
elsif (link_faults /= "00000" or turn_faults /= "00000000") and SHMU_address = current_address then
self_diagnosis_reg_in <= "0000000" & turn_faults & link_faults;
else
fault_info_in <= fault_info;
fault_info_ready_in <= fault_info_ready;
end if;
if sent_info = '1' then
fault_info_ready_in <= '0';
end if;
end process;
process(P2N_empty, state, credit_counter_out, packet_length_counter_out, packet_counter_out, FIFO_Data_out, fault_info_ready)
begin
-- Some initializations
sent_info <= '0';
TX <= (others => '0');
grant<= '0';
packet_length_counter_in <= packet_length_counter_out;
packet_counter_in <= packet_counter_out;
case(state) is
when IDLE =>
if fault_info_ready = '1' then
state_in <= DIAGNOSIS_HEADER;
elsif P2N_empty = '0' then
state_in <= HEADER_FLIT;
else
state_in <= IDLE;
end if;
when HEADER_FLIT =>
if credit_counter_out /= "00" and P2N_empty = '0' then
grant <= '1';
--TX <= "001" & "0000" & FIFO_Data_out(23 downto 16) & FIFO_Data_out(31 downto 28) &
-- std_logic_vector(to_unsigned(current_address, 4)) & packet_counter_out & XOR_REDUCE("001" & "0000" &
-- FIFO_Data_out(23 downto 16) & FIFO_Data_out(31 downto 28) &
-- std_logic_vector(to_unsigned(current_address, 4)) & packet_counter_out);
TX <= "001" & std_logic_vector(to_unsigned(current_address, 14)) & FIFO_Data_out(13 downto 0) & XOR_REDUCE("001" & std_logic_vector(to_unsigned(current_address, 14)) & FIFO_Data_out(13 downto 0));
state_in <= BODY_FLIT_1;
else
state_in <= HEADER_FLIT;
end if;
when BODY_FLIT_1 =>
if credit_counter_out /= "00" and P2N_empty = '0'then
packet_length_counter_in <= (FIFO_Data_out(27 downto 14))-2;
grant <= '1';
TX <= "010" &FIFO_Data_out(27 downto 14) & packet_counter_out & XOR_REDUCE( "010" &FIFO_Data_out(27 downto 14) & packet_counter_out);
state_in <= BODY_FLIT;
else
state_in <= BODY_FLIT_1;
end if;
when BODY_FLIT =>
if credit_counter_out /= "00" and P2N_empty = '0'then
grant <= '1';
TX <= "010" & FIFO_Data_out(27 downto 0) & XOR_REDUCE("010" & FIFO_Data_out(27 downto 0));
packet_length_counter_in <= packet_length_counter_out - 1;
if packet_length_counter_out > 2 then
state_in <= BODY_FLIT;
else
state_in <= TAIL_FLIT;
end if;
else
state_in <= BODY_FLIT;
end if;
when TAIL_FLIT =>
if credit_counter_out /= "00" and P2N_empty = '0' then
grant <= '1';
packet_length_counter_in <= packet_length_counter_out - 1;
TX <= "100" & FIFO_Data_out(27 downto 0) & XOR_REDUCE("100" & FIFO_Data_out(27 downto 0));
packet_counter_in <= packet_counter_out +1;
state_in <= IDLE;
else
state_in <= TAIL_FLIT;
end if;
-- SHMU stuff ----------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------
when DIAGNOSIS_HEADER =>
if credit_counter_out /= "00" then
grant <= '1';
TX <= "001" & std_logic_vector(to_unsigned(current_address, 14)) & FIFO_Data_out(13 downto 0) & XOR_REDUCE("001" & std_logic_vector(to_unsigned(current_address, 14)) & FIFO_Data_out(13 downto 0));
--TX <= "001" & "000000000011" & "0000" & std_logic_vector(to_unsigned(current_address, 4)) & packet_counter_out & XOR_REDUCE("001" & "000000000011" & "0000" & std_logic_vector(to_unsigned(current_address, 4)) & packet_counter_out);
state_in <= DIAGNOSIS_BODY_1;
else
state_in <= DIAGNOSIS_HEADER;
end if;
when DIAGNOSIS_BODY_1 =>
if credit_counter_out /= "00" then
grant <= '1';
state_in <= DIAGNOSIS_BODY;
TX <= "010" & std_logic_vector(to_unsigned(4, 14)) & packet_counter_out & XOR_REDUCE( "010" & std_logic_vector(to_unsigned(4, 14)) & packet_counter_out );
else
state_in <= DIAGNOSIS_BODY_1;
end if;
when DIAGNOSIS_BODY =>
if credit_counter_out /= "00" then
grant <= '1';
--FD (Fault Diagnosis) : 01000110 01000100
-- fault info is 13 bits
TX <= "010" & "0100011001000100" & fault_info(11 downto 0) & XOR_REDUCE("010" & "0100011001000100" & fault_info(11 downto 0));
state_in <= DIAGNOSIS_TAIL;
else
state_in <= DIAGNOSIS_BODY;
end if;
when DIAGNOSIS_TAIL =>
if credit_counter_out /= "00" then
grant <= '1';
TX <= "100" & fault_info(24 downto 12) & "000000000000000" & XOR_REDUCE("100" & fault_info(24 downto 12) & "000000000000000");
state_in <= IDLE;
sent_info <= '1';
packet_counter_in <= packet_counter_out +1;
else
state_in <= DIAGNOSIS_TAIL;
end if;
when others =>
state_in <= IDLE;
end case ;
end procesS;
valid_out <= grant;
----------------------------------------------------------------------------------------
--below this is code for communication from NoC 2 PE
process(RX, N2P_FIFO_write_pointer, N2P_FIFO_MEM_1, N2P_FIFO_MEM_2, N2P_FIFO_MEM_3, N2P_FIFO_MEM_4)begin
case( N2P_FIFO_write_pointer ) is
when "0001" => N2P_FIFO_MEM_1_in <= RX; N2P_FIFO_MEM_2_in <= N2P_FIFO_MEM_2; N2P_FIFO_MEM_3_in <= N2P_FIFO_MEM_3; N2P_FIFO_MEM_4_in <= N2P_FIFO_MEM_4;
when "0010" => N2P_FIFO_MEM_1_in <= N2P_FIFO_MEM_1; N2P_FIFO_MEM_2_in <= RX; N2P_FIFO_MEM_3_in <= N2P_FIFO_MEM_3; N2P_FIFO_MEM_4_in <= N2P_FIFO_MEM_4;
when "0100" => N2P_FIFO_MEM_1_in <= N2P_FIFO_MEM_1; N2P_FIFO_MEM_2_in <= N2P_FIFO_MEM_2; N2P_FIFO_MEM_3_in <= RX; N2P_FIFO_MEM_4_in <= N2P_FIFO_MEM_4;
when "1000" => N2P_FIFO_MEM_1_in <= N2P_FIFO_MEM_1; N2P_FIFO_MEM_2_in <= N2P_FIFO_MEM_2; N2P_FIFO_MEM_3_in <= N2P_FIFO_MEM_3; N2P_FIFO_MEM_4_in <= RX;
when others => N2P_FIFO_MEM_1_in <= N2P_FIFO_MEM_1; N2P_FIFO_MEM_2_in <= N2P_FIFO_MEM_2; N2P_FIFO_MEM_3_in <= N2P_FIFO_MEM_3; N2P_FIFO_MEM_4_in <= N2P_FIFO_MEM_4;
end case ;
end process;
process(N2P_FIFO_read_pointer, N2P_FIFO_MEM_1, N2P_FIFO_MEM_2, N2P_FIFO_MEM_3, N2P_FIFO_MEM_4)begin
case( N2P_FIFO_read_pointer ) is
when "0001" => N2P_Data_out <= N2P_FIFO_MEM_1;
when "0010" => N2P_Data_out <= N2P_FIFO_MEM_2;
when "0100" => N2P_Data_out <= N2P_FIFO_MEM_3;
when "1000" => N2P_Data_out <= N2P_FIFO_MEM_4;
when others => N2P_Data_out <= N2P_FIFO_MEM_1;
end case ;
end process;
process(address, write_byte_enable, N2P_empty)begin
if address = reserved_address and write_byte_enable = "0000" and N2P_empty = '0' then
N2P_read_en_in <= '1';
else
N2P_read_en_in <= '0';
end if;
end process;
process(N2P_write_en, N2P_FIFO_write_pointer)begin
if N2P_write_en = '1'then
N2P_FIFO_write_pointer_in <= N2P_FIFO_write_pointer(2 downto 0)&N2P_FIFO_write_pointer(3);
else
N2P_FIFO_write_pointer_in <= N2P_FIFO_write_pointer;
end if;
end process;
process(N2P_read_en, N2P_empty, N2P_FIFO_read_pointer)begin
if (N2P_read_en = '1' and N2P_empty = '0') then
N2P_FIFO_read_pointer_in <= N2P_FIFO_read_pointer(2 downto 0)&N2P_FIFO_read_pointer(3);
else
N2P_FIFO_read_pointer_in <= N2P_FIFO_read_pointer;
end if;
end process;
process(N2P_full, valid_in) begin
if (valid_in = '1' and N2P_full ='0') then
N2P_write_en <= '1';
else
N2P_write_en <= '0';
end if;
end process;
process(N2P_FIFO_write_pointer, N2P_FIFO_read_pointer) begin
if N2P_FIFO_read_pointer = N2P_FIFO_write_pointer then
N2P_empty <= '1';
else
N2P_empty <= '0';
end if;
if N2P_FIFO_write_pointer = N2P_FIFO_read_pointer(0)&N2P_FIFO_read_pointer(3 downto 1) then
N2P_full <= '1';
else
N2P_full <= '0';
end if;
end process;
process(N2P_read_en, N2P_Data_out, old_address, flag_register) begin
if old_address = reserved_address and N2P_read_en = '1' then
data_read <= N2P_Data_out;
elsif old_address = flag_address then
data_read <= flag_register;
elsif old_address = counter_address then
data_read <= "000000000000000000000000000000" & counter_register;
elsif old_address = self_diagnosis_address then
data_read <= self_diagnosis_reg_out;
else
data_read <= (others => 'U');
end if;
end process;
process(N2P_write_en, N2P_read_en, RX, N2P_Data_out)begin
counter_register_in <= counter_register;
if N2P_write_en = '1' and RX(31 downto 29) = "001" and N2P_read_en = '1' and N2P_Data_out(31 downto 29) = "100" then
counter_register_in <= counter_register;
elsif N2P_write_en = '1' and RX(31 downto 29) = "001" then
counter_register_in <= counter_register +1;
elsif N2P_read_en = '1' and N2P_Data_out(31 downto 29) = "100" then
counter_register_in <= counter_register -1;
end if;
end process;
flag_register_in <= N2P_empty & P2N_full & self_diagnosis_flag & "00000000000000000000000000000";
--NI_read_flag <= N2P_empty;
--NI_write_flag <= P2N_full;
irq_out <= '0';
end; --architecture logic
|
---------------------------------------------------------------------
-- Copyright (C) 2016 Siavoosh Payandeh Azad
--
-- Network interface: Its an interrupt based memory mapped I/O for sending and recieving packets.
-- the data that is sent to NI should be of the following form:
-- FIRST write: 4bit source(31-28), 4 bit destination(27-14), 8bit packet length(23-16)
-- Body write: 28 bit data(27-0)
-- Last write: 28 bit data(27-0)
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use IEEE.NUMERIC_STD.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.mlite_pack.all;
use ieee.std_logic_misc.all;
entity NI is
generic(current_address : integer := 10; -- the current node's address
SHMU_address : integer := 0;
reserved_address : std_logic_vector(29 downto 0) := "000000000000000001111111111111"; -- Behrad: NI's reserved address ?
flag_address : std_logic_vector(29 downto 0) := "000000000000000010000000000000"; -- reserved address for the memory mapped I/O
counter_address : std_logic_vector(29 downto 0) := "000000000000000010000000000001";
reconfiguration_address : std_logic_vector(29 downto 0) := "000000000000000010000000000010"; -- reserved address for reconfiguration register
self_diagnosis_address : std_logic_vector(29 downto 0) := "000000000000000010000000000011"); -- reserved address for self diagnosis register
port(clk : in std_logic;
reset : in std_logic;
enable : in std_logic;
write_byte_enable : in std_logic_vector(3 downto 0);
address : in std_logic_vector(31 downto 2);
data_write : in std_logic_vector(31 downto 0);
data_read : out std_logic_vector(31 downto 0);
-- Flags used by JNIFR and JNIFW instructions
--NI_read_flag : out std_logic; -- One if the N2P fifo is empty. No read should be performed if one.
--NI_write_flag : out std_logic; -- One if P2N fifo is full. no write should be performed if one.
-- interrupt signal: generated evertime a packet is recieved!
irq_out : out std_logic;
-- signals for sending packets to network
credit_in : in std_logic;
valid_out: out std_logic;
TX: out std_logic_vector(31 downto 0); -- data sent to the NoC
-- signals for reciving packets from the network
credit_out : out std_logic;
valid_in: in std_logic;
RX: in std_logic_vector(31 downto 0); -- data recieved form the NoC
-- fault information signals from the router
link_faults: in std_logic_vector(4 downto 0);
turn_faults: in std_logic_vector(19 downto 0);
Rxy_reconf_PE: out std_logic_vector(7 downto 0);
Cx_reconf_PE: out std_logic_vector(3 downto 0); -- if you are not going to update Cx you should write all ones! (it will be and will the current Cx bits)
Reconfig_command : out std_logic
);
end; --entity NI
architecture logic of NI is
-- packet format:
-- the parity bit is calculated by the NI and the processor has no control over it
-- flit type is generated by the NI and process has no control over it
-- header flit
-- 32 3bits 14 bits 14 bits 1bit 0
-- .----------------------------------------------------------------------.
-- | flit type| SOURCE ADDRESS | DESTINATION ADDRESS |parity bit |
-- '----------------------------------------------------------------------'
-- SOURCE ADDRESS is added automatically by the NI (the processor has no control over it)
-- DESTINATION ADDRESS is writen in the first write by the PE in FIFO_Data_out(13 downto 0)
-- body flit 1
-- 32 3bits 14 bits 14 bits 1bit 0
-- .----------------------------------------------------------------------.
-- | flit type| PACKET LENGTH | PACKET ID |parity bit |
-- '----------------------------------------------------------------------'
-- PACEKT ID is determined and added by the NI (the processor has no control over it)
-- PACKET LENGTH is written in the 2nd write by PE in FIFO_Data_out(27 downto 14)
-- other body flits
-- 32 3bits 28 bits 1bit 0
-- .----------------------------------------------------------------------.
-- | flit type| PAYLOAD DATA |parity bit |
-- '----------------------------------------------------------------------'
-- PAYLOAD DATA is written by the PE in FIFO_Data_out(27 downto 0)
-- Tail flits
-- 32 3bits 28 bits 1bit 0
-- .----------------------------------------------------------------------.
-- | flit type| PAYLOAD DATA |parity bit |
-- '----------------------------------------------------------------------'
-- PAYLOAD DATA is written by the PE in FIFO_Data_out(27 downto 0)
-- all the following signals are for sending data from processor to NoC
signal storage, storage_in : std_logic_vector(31 downto 0);
signal valid_data_in, valid_data: std_logic;
signal old_address: std_logic_vector(31 downto 2); -- Behrad: What is old address ?
signal P2N_FIFO_read_pointer, P2N_FIFO_read_pointer_in, P2N_FIFO_write_pointer, P2N_FIFO_write_pointer_in: std_logic_vector(3 downto 0);
signal P2N_write_en: std_logic;
signal P2N_FIFO_MEM_1, P2N_FIFO_MEM_1_in : std_logic_vector(31 downto 0);
signal P2N_FIFO_MEM_2, P2N_FIFO_MEM_2_in : std_logic_vector(31 downto 0);
signal P2N_FIFO_MEM_3, P2N_FIFO_MEM_3_in : std_logic_vector(31 downto 0);
signal P2N_FIFO_MEM_4, P2N_FIFO_MEM_4_in : std_logic_vector(31 downto 0);
signal P2N_full, P2N_empty: std_logic;
signal credit_counter_in, credit_counter_out: std_logic_vector(1 downto 0);
signal packet_counter_in, packet_counter_out: std_logic_vector(13 downto 0);
signal packet_length_counter_in, packet_length_counter_out: std_logic_vector(13 downto 0);
signal grant : std_logic;
type STATE_TYPE IS (IDLE, HEADER_FLIT, BODY_FLIT_1, BODY_FLIT, TAIL_FLIT, DIAGNOSIS_HEADER, DIAGNOSIS_BODY, DIAGNOSIS_BODY_1, DIAGNOSIS_TAIL);
signal state, state_in : STATE_TYPE := IDLE;
signal FIFO_Data_out : std_logic_vector(31 downto 0);
signal flag_register, flag_register_in : std_logic_vector(31 downto 0);
-- all the following signals are for sending the packets from NoC to processor
signal N2P_FIFO_MEM_1, N2P_FIFO_MEM_1_in : std_logic_vector(31 downto 0);
signal N2P_FIFO_MEM_2, N2P_FIFO_MEM_2_in : std_logic_vector(31 downto 0);
signal N2P_FIFO_MEM_3, N2P_FIFO_MEM_3_in : std_logic_vector(31 downto 0);
signal N2P_FIFO_MEM_4, N2P_FIFO_MEM_4_in : std_logic_vector(31 downto 0);
signal N2P_Data_out, data_read_in : std_logic_vector(31 downto 0);
signal N2P_FIFO_read_pointer, N2P_FIFO_read_pointer_in: std_logic_vector(3 downto 0);
signal N2P_FIFO_write_pointer, N2P_FIFO_write_pointer_in: std_logic_vector(3 downto 0);
signal N2P_full, N2P_empty: std_logic;
signal N2P_read_en, N2P_read_en_in, N2P_write_en: std_logic;
signal counter_register_in, counter_register : std_logic_vector(1 downto 0);
signal fault_info, fault_info_in: std_logic_vector(24 downto 0);
signal sent_info, fault_info_ready, fault_info_ready_in: std_logic;
signal self_diagnosis_reg_out, self_diagnosis_reg_in: std_logic_vector(31 downto 0);
signal self_diagnosis_flag, self_diagnosis_flag_in: std_logic;
begin
process(clk, enable, write_byte_enable) begin
if reset = '1' then
storage <= (others => '0');
valid_data <= '0';
P2N_FIFO_read_pointer <= "0001";
P2N_FIFO_write_pointer <= "0001";
P2N_FIFO_MEM_1 <= (others=>'0');
P2N_FIFO_MEM_2 <= (others=>'0');
P2N_FIFO_MEM_3 <= (others=>'0');
P2N_FIFO_MEM_4 <= (others=>'0');
credit_counter_out <= "11";
packet_length_counter_out <= (others=>'0');
state <= IDLE;
packet_counter_out <= (others=>'0');
------------------------------------------------
N2P_FIFO_MEM_1 <= (others=>'0');
N2P_FIFO_MEM_2 <= (others=>'0');
N2P_FIFO_MEM_3 <= (others=>'0');
N2P_FIFO_MEM_4 <= (others=>'0');
N2P_FIFO_read_pointer <= "0001";
N2P_FIFO_write_pointer <= "0001";
credit_out <= '0';
counter_register <= (others => '0');
N2P_read_en <= '0';
flag_register <= (others =>'0');
old_address <= (others =>'0');
fault_info <= (others => '0');
fault_info_ready <= '0';
self_diagnosis_reg_out <= (others => '0');
self_diagnosis_flag <= '0';
elsif clk'event and clk = '1' then
old_address <= address;
P2N_FIFO_write_pointer <= P2N_FIFO_write_pointer_in;
P2N_FIFO_read_pointer <= P2N_FIFO_read_pointer_in;
credit_counter_out <= credit_counter_in;
packet_length_counter_out <= packet_length_counter_in;
valid_data <= valid_data_in;
if P2N_write_en = '1' then
--write into the memory
P2N_FIFO_MEM_1 <= P2N_FIFO_MEM_1_in;
P2N_FIFO_MEM_2 <= P2N_FIFO_MEM_2_in;
P2N_FIFO_MEM_3 <= P2N_FIFO_MEM_3_in;
P2N_FIFO_MEM_4 <= P2N_FIFO_MEM_4_in;
end if;
packet_counter_out <= packet_counter_in;
if write_byte_enable /= "0000" then
storage <= storage_in;
end if;
state <= state_in;
------------------------------------------------
if N2P_write_en = '1' then
--write into the memory
N2P_FIFO_MEM_1 <= N2P_FIFO_MEM_1_in;
N2P_FIFO_MEM_2 <= N2P_FIFO_MEM_2_in;
N2P_FIFO_MEM_3 <= N2P_FIFO_MEM_3_in;
N2P_FIFO_MEM_4 <= N2P_FIFO_MEM_4_in;
end if;
counter_register <= counter_register_in;
N2P_FIFO_write_pointer <= N2P_FIFO_write_pointer_in;
N2P_FIFO_read_pointer <= N2P_FIFO_read_pointer_in;
credit_out <= '0';
N2P_read_en <= N2P_read_en_in;
if N2P_read_en = '1' then
credit_out <= '1';
end if;
flag_register <= flag_register_in;
fault_info <= fault_info_in;
fault_info_ready <= fault_info_ready_in;
self_diagnosis_reg_out <= self_diagnosis_reg_in;
self_diagnosis_flag <= self_diagnosis_flag_in;
end if;
end process;
-- everything bellow this line is pure combinatorial!
---------------------------------------------------------------------------------------
--below this is code for communication from PE 2 NoC
-- Process used for sending reconfiguration command from PE to router (which is part of NoC)
process(enable, address, write_byte_enable) begin
-- Some initializations
Reconfig_command <= '0';
Rxy_reconf_PE <= (others =>'0');
Cx_reconf_PE <= (others =>'0');
if address = reconfiguration_address and enable = '1' then
if write_byte_enable /= "0000" then
-- In this case, data_write definitely includes the connectivity bits and routing bits for
-- reconfiguring LBDR logic.
Rxy_reconf_PE <= data_write(7 downto 0); -- Rxy is 8 bits long
Cx_reconf_PE <= data_write(11 downto 8); -- Cx is 4 bits long
Reconfig_command <= '1';
end if;
end if;
end process;
process(write_byte_enable, enable, address, storage, data_write, valid_data, P2N_write_en) begin
storage_in <= storage ;
valid_data_in <= valid_data;
-- If PE wants to send data to NoC via NI (data is valid)
if enable = '1' and address = reserved_address then
if write_byte_enable /= "0000" then
valid_data_in <= '1';
end if;
-- Behrad: So according to Plasma, is write_byte_enable always one-hot ?
-- (of course it can also be "0000")
if write_byte_enable(0) = '1' then
storage_in(7 downto 0) <= data_write(7 downto 0);
end if;
if write_byte_enable(1) = '1' then
storage_in(15 downto 8) <= data_write(15 downto 8);
end if;
if write_byte_enable(2) = '1' then
storage_in(23 downto 16) <= data_write(23 downto 16);
end if;
if write_byte_enable(3) = '1' then
storage_in(31 downto 24) <= data_write(31 downto 24);
end if;
end if;
if P2N_write_en = '1' then
valid_data_in <= '0';
end if;
end process;
-- Process for storing in FIFO (based on the position write pointer is pointing to)
-- Write pointer is encoded as one-hot!
process(storage, P2N_FIFO_write_pointer, P2N_FIFO_MEM_1, P2N_FIFO_MEM_2, P2N_FIFO_MEM_3, P2N_FIFO_MEM_4)begin
case(P2N_FIFO_write_pointer) is
when "0001" => P2N_FIFO_MEM_1_in <= storage; P2N_FIFO_MEM_2_in <= P2N_FIFO_MEM_2; P2N_FIFO_MEM_3_in <= P2N_FIFO_MEM_3; P2N_FIFO_MEM_4_in <= P2N_FIFO_MEM_4;
when "0010" => P2N_FIFO_MEM_1_in <= P2N_FIFO_MEM_1; P2N_FIFO_MEM_2_in <= storage; P2N_FIFO_MEM_3_in <= P2N_FIFO_MEM_3; P2N_FIFO_MEM_4_in <= P2N_FIFO_MEM_4;
when "0100" => P2N_FIFO_MEM_1_in <= P2N_FIFO_MEM_1; P2N_FIFO_MEM_2_in <= P2N_FIFO_MEM_2; P2N_FIFO_MEM_3_in <= storage; P2N_FIFO_MEM_4_in <= P2N_FIFO_MEM_4;
when "1000" => P2N_FIFO_MEM_1_in <= P2N_FIFO_MEM_1; P2N_FIFO_MEM_2_in <= P2N_FIFO_MEM_2; P2N_FIFO_MEM_3_in <= P2N_FIFO_MEM_3; P2N_FIFO_MEM_4_in <= storage;
when others => P2N_FIFO_MEM_1_in <= P2N_FIFO_MEM_1; P2N_FIFO_MEM_2_in <= P2N_FIFO_MEM_2; P2N_FIFO_MEM_3_in <= P2N_FIFO_MEM_3; P2N_FIFO_MEM_4_in <= P2N_FIFO_MEM_4;
end case ;
end process;
-- Process for reading from FIFO (based on the position read pointer is pointing to)
-- read pointer is encoded as one-hot!
process(P2N_FIFO_read_pointer, P2N_FIFO_MEM_1, P2N_FIFO_MEM_2, P2N_FIFO_MEM_3, P2N_FIFO_MEM_4)begin
case( P2N_FIFO_read_pointer ) is
when "0001" => FIFO_Data_out <= P2N_FIFO_MEM_1;
when "0010" => FIFO_Data_out <= P2N_FIFO_MEM_2;
when "0100" => FIFO_Data_out <= P2N_FIFO_MEM_3;
when "1000" => FIFO_Data_out <= P2N_FIFO_MEM_4;
when others => FIFO_Data_out <= P2N_FIFO_MEM_1;
end case ;
end process;
-- Write pointer update process (after each write operation, write pointer is rotated one bit to the left)
process(P2N_write_en, P2N_FIFO_write_pointer)begin
if P2N_write_en = '1' then
P2N_FIFO_write_pointer_in <= P2N_FIFO_write_pointer(2 downto 0) & P2N_FIFO_write_pointer(3);
else
P2N_FIFO_write_pointer_in <= P2N_FIFO_write_pointer;
end if;
end process;
-- Read pointer update process (after each read operation, read pointer is rotated one bit to the left)
process(P2N_FIFO_read_pointer, grant, fault_info_ready)begin
P2N_FIFO_read_pointer_in <= P2N_FIFO_read_pointer;
if grant = '1' and fault_info_ready = '0' then -- Behrad: so grant here works somehow like read_en signal for FIFO ?
P2N_FIFO_read_pointer_in <= P2N_FIFO_read_pointer(2 downto 0) & P2N_FIFO_read_pointer(3);
end if;
end process;
process(P2N_full, valid_data) begin
if valid_data = '1' and P2N_full ='0' then
P2N_write_en <= '1';
else
P2N_write_en <= '0';
end if;
end process;
-- Process for updating full and empty signals
process(P2N_FIFO_write_pointer, P2N_FIFO_read_pointer) begin
P2N_empty <= '0';
P2N_full <= '0';
if P2N_FIFO_read_pointer = P2N_FIFO_write_pointer then
P2N_empty <= '1';
end if;
if P2N_FIFO_write_pointer = P2N_FIFO_read_pointer(0) & P2N_FIFO_read_pointer(3 downto 1) then
P2N_full <= '1';
end if;
end process;
process (credit_in, credit_counter_out, grant)begin
credit_counter_in <= credit_counter_out;
if credit_in = '1' and grant = '1' then
credit_counter_in <= credit_counter_out;
elsif credit_in = '1' and credit_counter_out < 3 then
credit_counter_in <= credit_counter_out + 1;
elsif grant = '1' and credit_counter_out > 0 then
credit_counter_in <= credit_counter_out - 1;
end if;
end process;
-- flag setting and clearing for self diagnosis
process(link_faults, turn_faults, self_diagnosis_flag, old_address)begin
if (link_faults /= "00000" or turn_faults /= "00000000000000000000") and SHMU_address = current_address then
self_diagnosis_flag_in <= '1';
elsif old_address = self_diagnosis_address then
self_diagnosis_flag_in <= '0';
else
self_diagnosis_flag_in <= self_diagnosis_flag;
end if;
end process;
-- handling fault information!
process(link_faults, turn_faults, sent_info, fault_info_ready, fault_info)begin
self_diagnosis_reg_in <= self_diagnosis_reg_out;
-- If current node is not SHMU, we need to send fault information to SHMU
if (link_faults /= "00000" or turn_faults /= "00000000") and SHMU_address /= current_address then
fault_info_in <= turn_faults & link_faults;
fault_info_ready_in <= '1';
-- If current node is SHMU, we handle it locally
elsif (link_faults /= "00000" or turn_faults /= "00000000") and SHMU_address = current_address then
self_diagnosis_reg_in <= "0000000" & turn_faults & link_faults;
else
fault_info_in <= fault_info;
fault_info_ready_in <= fault_info_ready;
end if;
if sent_info = '1' then
fault_info_ready_in <= '0';
end if;
end process;
process(P2N_empty, state, credit_counter_out, packet_length_counter_out, packet_counter_out, FIFO_Data_out, fault_info_ready)
begin
-- Some initializations
sent_info <= '0';
TX <= (others => '0');
grant<= '0';
packet_length_counter_in <= packet_length_counter_out;
packet_counter_in <= packet_counter_out;
case(state) is
when IDLE =>
if fault_info_ready = '1' then
state_in <= DIAGNOSIS_HEADER;
elsif P2N_empty = '0' then
state_in <= HEADER_FLIT;
else
state_in <= IDLE;
end if;
when HEADER_FLIT =>
if credit_counter_out /= "00" and P2N_empty = '0' then
grant <= '1';
--TX <= "001" & "0000" & FIFO_Data_out(23 downto 16) & FIFO_Data_out(31 downto 28) &
-- std_logic_vector(to_unsigned(current_address, 4)) & packet_counter_out & XOR_REDUCE("001" & "0000" &
-- FIFO_Data_out(23 downto 16) & FIFO_Data_out(31 downto 28) &
-- std_logic_vector(to_unsigned(current_address, 4)) & packet_counter_out);
TX <= "001" & std_logic_vector(to_unsigned(current_address, 14)) & FIFO_Data_out(13 downto 0) & XOR_REDUCE("001" & std_logic_vector(to_unsigned(current_address, 14)) & FIFO_Data_out(13 downto 0));
state_in <= BODY_FLIT_1;
else
state_in <= HEADER_FLIT;
end if;
when BODY_FLIT_1 =>
if credit_counter_out /= "00" and P2N_empty = '0'then
packet_length_counter_in <= (FIFO_Data_out(27 downto 14))-2;
grant <= '1';
TX <= "010" &FIFO_Data_out(27 downto 14) & packet_counter_out & XOR_REDUCE( "010" &FIFO_Data_out(27 downto 14) & packet_counter_out);
state_in <= BODY_FLIT;
else
state_in <= BODY_FLIT_1;
end if;
when BODY_FLIT =>
if credit_counter_out /= "00" and P2N_empty = '0'then
grant <= '1';
TX <= "010" & FIFO_Data_out(27 downto 0) & XOR_REDUCE("010" & FIFO_Data_out(27 downto 0));
packet_length_counter_in <= packet_length_counter_out - 1;
if packet_length_counter_out > 2 then
state_in <= BODY_FLIT;
else
state_in <= TAIL_FLIT;
end if;
else
state_in <= BODY_FLIT;
end if;
when TAIL_FLIT =>
if credit_counter_out /= "00" and P2N_empty = '0' then
grant <= '1';
packet_length_counter_in <= packet_length_counter_out - 1;
TX <= "100" & FIFO_Data_out(27 downto 0) & XOR_REDUCE("100" & FIFO_Data_out(27 downto 0));
packet_counter_in <= packet_counter_out +1;
state_in <= IDLE;
else
state_in <= TAIL_FLIT;
end if;
-- SHMU stuff ----------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------
when DIAGNOSIS_HEADER =>
if credit_counter_out /= "00" then
grant <= '1';
TX <= "001" & std_logic_vector(to_unsigned(current_address, 14)) & FIFO_Data_out(13 downto 0) & XOR_REDUCE("001" & std_logic_vector(to_unsigned(current_address, 14)) & FIFO_Data_out(13 downto 0));
--TX <= "001" & "000000000011" & "0000" & std_logic_vector(to_unsigned(current_address, 4)) & packet_counter_out & XOR_REDUCE("001" & "000000000011" & "0000" & std_logic_vector(to_unsigned(current_address, 4)) & packet_counter_out);
state_in <= DIAGNOSIS_BODY_1;
else
state_in <= DIAGNOSIS_HEADER;
end if;
when DIAGNOSIS_BODY_1 =>
if credit_counter_out /= "00" then
grant <= '1';
state_in <= DIAGNOSIS_BODY;
TX <= "010" & std_logic_vector(to_unsigned(4, 14)) & packet_counter_out & XOR_REDUCE( "010" & std_logic_vector(to_unsigned(4, 14)) & packet_counter_out );
else
state_in <= DIAGNOSIS_BODY_1;
end if;
when DIAGNOSIS_BODY =>
if credit_counter_out /= "00" then
grant <= '1';
--FD (Fault Diagnosis) : 01000110 01000100
-- fault info is 13 bits
TX <= "010" & "0100011001000100" & fault_info(11 downto 0) & XOR_REDUCE("010" & "0100011001000100" & fault_info(11 downto 0));
state_in <= DIAGNOSIS_TAIL;
else
state_in <= DIAGNOSIS_BODY;
end if;
when DIAGNOSIS_TAIL =>
if credit_counter_out /= "00" then
grant <= '1';
TX <= "100" & fault_info(24 downto 12) & "000000000000000" & XOR_REDUCE("100" & fault_info(24 downto 12) & "000000000000000");
state_in <= IDLE;
sent_info <= '1';
packet_counter_in <= packet_counter_out +1;
else
state_in <= DIAGNOSIS_TAIL;
end if;
when others =>
state_in <= IDLE;
end case ;
end procesS;
valid_out <= grant;
----------------------------------------------------------------------------------------
--below this is code for communication from NoC 2 PE
process(RX, N2P_FIFO_write_pointer, N2P_FIFO_MEM_1, N2P_FIFO_MEM_2, N2P_FIFO_MEM_3, N2P_FIFO_MEM_4)begin
case( N2P_FIFO_write_pointer ) is
when "0001" => N2P_FIFO_MEM_1_in <= RX; N2P_FIFO_MEM_2_in <= N2P_FIFO_MEM_2; N2P_FIFO_MEM_3_in <= N2P_FIFO_MEM_3; N2P_FIFO_MEM_4_in <= N2P_FIFO_MEM_4;
when "0010" => N2P_FIFO_MEM_1_in <= N2P_FIFO_MEM_1; N2P_FIFO_MEM_2_in <= RX; N2P_FIFO_MEM_3_in <= N2P_FIFO_MEM_3; N2P_FIFO_MEM_4_in <= N2P_FIFO_MEM_4;
when "0100" => N2P_FIFO_MEM_1_in <= N2P_FIFO_MEM_1; N2P_FIFO_MEM_2_in <= N2P_FIFO_MEM_2; N2P_FIFO_MEM_3_in <= RX; N2P_FIFO_MEM_4_in <= N2P_FIFO_MEM_4;
when "1000" => N2P_FIFO_MEM_1_in <= N2P_FIFO_MEM_1; N2P_FIFO_MEM_2_in <= N2P_FIFO_MEM_2; N2P_FIFO_MEM_3_in <= N2P_FIFO_MEM_3; N2P_FIFO_MEM_4_in <= RX;
when others => N2P_FIFO_MEM_1_in <= N2P_FIFO_MEM_1; N2P_FIFO_MEM_2_in <= N2P_FIFO_MEM_2; N2P_FIFO_MEM_3_in <= N2P_FIFO_MEM_3; N2P_FIFO_MEM_4_in <= N2P_FIFO_MEM_4;
end case ;
end process;
process(N2P_FIFO_read_pointer, N2P_FIFO_MEM_1, N2P_FIFO_MEM_2, N2P_FIFO_MEM_3, N2P_FIFO_MEM_4)begin
case( N2P_FIFO_read_pointer ) is
when "0001" => N2P_Data_out <= N2P_FIFO_MEM_1;
when "0010" => N2P_Data_out <= N2P_FIFO_MEM_2;
when "0100" => N2P_Data_out <= N2P_FIFO_MEM_3;
when "1000" => N2P_Data_out <= N2P_FIFO_MEM_4;
when others => N2P_Data_out <= N2P_FIFO_MEM_1;
end case ;
end process;
process(address, write_byte_enable, N2P_empty)begin
if address = reserved_address and write_byte_enable = "0000" and N2P_empty = '0' then
N2P_read_en_in <= '1';
else
N2P_read_en_in <= '0';
end if;
end process;
process(N2P_write_en, N2P_FIFO_write_pointer)begin
if N2P_write_en = '1'then
N2P_FIFO_write_pointer_in <= N2P_FIFO_write_pointer(2 downto 0)&N2P_FIFO_write_pointer(3);
else
N2P_FIFO_write_pointer_in <= N2P_FIFO_write_pointer;
end if;
end process;
process(N2P_read_en, N2P_empty, N2P_FIFO_read_pointer)begin
if (N2P_read_en = '1' and N2P_empty = '0') then
N2P_FIFO_read_pointer_in <= N2P_FIFO_read_pointer(2 downto 0)&N2P_FIFO_read_pointer(3);
else
N2P_FIFO_read_pointer_in <= N2P_FIFO_read_pointer;
end if;
end process;
process(N2P_full, valid_in) begin
if (valid_in = '1' and N2P_full ='0') then
N2P_write_en <= '1';
else
N2P_write_en <= '0';
end if;
end process;
process(N2P_FIFO_write_pointer, N2P_FIFO_read_pointer) begin
if N2P_FIFO_read_pointer = N2P_FIFO_write_pointer then
N2P_empty <= '1';
else
N2P_empty <= '0';
end if;
if N2P_FIFO_write_pointer = N2P_FIFO_read_pointer(0)&N2P_FIFO_read_pointer(3 downto 1) then
N2P_full <= '1';
else
N2P_full <= '0';
end if;
end process;
process(N2P_read_en, N2P_Data_out, old_address, flag_register) begin
if old_address = reserved_address and N2P_read_en = '1' then
data_read <= N2P_Data_out;
elsif old_address = flag_address then
data_read <= flag_register;
elsif old_address = counter_address then
data_read <= "000000000000000000000000000000" & counter_register;
elsif old_address = self_diagnosis_address then
data_read <= self_diagnosis_reg_out;
else
data_read <= (others => 'U');
end if;
end process;
process(N2P_write_en, N2P_read_en, RX, N2P_Data_out)begin
counter_register_in <= counter_register;
if N2P_write_en = '1' and RX(31 downto 29) = "001" and N2P_read_en = '1' and N2P_Data_out(31 downto 29) = "100" then
counter_register_in <= counter_register;
elsif N2P_write_en = '1' and RX(31 downto 29) = "001" then
counter_register_in <= counter_register +1;
elsif N2P_read_en = '1' and N2P_Data_out(31 downto 29) = "100" then
counter_register_in <= counter_register -1;
end if;
end process;
flag_register_in <= N2P_empty & P2N_full & self_diagnosis_flag & "00000000000000000000000000000";
--NI_read_flag <= N2P_empty;
--NI_write_flag <= P2N_full;
irq_out <= '0';
end; --architecture logic
|
---------------------------------------------------------------------
-- Copyright (C) 2016 Siavoosh Payandeh Azad
--
-- Network interface: Its an interrupt based memory mapped I/O for sending and recieving packets.
-- the data that is sent to NI should be of the following form:
-- FIRST write: 4bit source(31-28), 4 bit destination(27-14), 8bit packet length(23-16)
-- Body write: 28 bit data(27-0)
-- Last write: 28 bit data(27-0)
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use IEEE.NUMERIC_STD.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.mlite_pack.all;
use ieee.std_logic_misc.all;
entity NI is
generic(current_address : integer := 10; -- the current node's address
SHMU_address : integer := 0;
reserved_address : std_logic_vector(29 downto 0) := "000000000000000001111111111111"; -- Behrad: NI's reserved address ?
flag_address : std_logic_vector(29 downto 0) := "000000000000000010000000000000"; -- reserved address for the memory mapped I/O
counter_address : std_logic_vector(29 downto 0) := "000000000000000010000000000001";
reconfiguration_address : std_logic_vector(29 downto 0) := "000000000000000010000000000010"; -- reserved address for reconfiguration register
self_diagnosis_address : std_logic_vector(29 downto 0) := "000000000000000010000000000011"); -- reserved address for self diagnosis register
port(clk : in std_logic;
reset : in std_logic;
enable : in std_logic;
write_byte_enable : in std_logic_vector(3 downto 0);
address : in std_logic_vector(31 downto 2);
data_write : in std_logic_vector(31 downto 0);
data_read : out std_logic_vector(31 downto 0);
-- Flags used by JNIFR and JNIFW instructions
--NI_read_flag : out std_logic; -- One if the N2P fifo is empty. No read should be performed if one.
--NI_write_flag : out std_logic; -- One if P2N fifo is full. no write should be performed if one.
-- interrupt signal: generated evertime a packet is recieved!
irq_out : out std_logic;
-- signals for sending packets to network
credit_in : in std_logic;
valid_out: out std_logic;
TX: out std_logic_vector(31 downto 0); -- data sent to the NoC
-- signals for reciving packets from the network
credit_out : out std_logic;
valid_in: in std_logic;
RX: in std_logic_vector(31 downto 0); -- data recieved form the NoC
-- fault information signals from the router
link_faults: in std_logic_vector(4 downto 0);
turn_faults: in std_logic_vector(19 downto 0);
Rxy_reconf_PE: out std_logic_vector(7 downto 0);
Cx_reconf_PE: out std_logic_vector(3 downto 0); -- if you are not going to update Cx you should write all ones! (it will be and will the current Cx bits)
Reconfig_command : out std_logic
);
end; --entity NI
architecture logic of NI is
-- packet format:
-- the parity bit is calculated by the NI and the processor has no control over it
-- flit type is generated by the NI and process has no control over it
-- header flit
-- 32 3bits 14 bits 14 bits 1bit 0
-- .----------------------------------------------------------------------.
-- | flit type| SOURCE ADDRESS | DESTINATION ADDRESS |parity bit |
-- '----------------------------------------------------------------------'
-- SOURCE ADDRESS is added automatically by the NI (the processor has no control over it)
-- DESTINATION ADDRESS is writen in the first write by the PE in FIFO_Data_out(13 downto 0)
-- body flit 1
-- 32 3bits 14 bits 14 bits 1bit 0
-- .----------------------------------------------------------------------.
-- | flit type| PACKET LENGTH | PACKET ID |parity bit |
-- '----------------------------------------------------------------------'
-- PACEKT ID is determined and added by the NI (the processor has no control over it)
-- PACKET LENGTH is written in the 2nd write by PE in FIFO_Data_out(27 downto 14)
-- other body flits
-- 32 3bits 28 bits 1bit 0
-- .----------------------------------------------------------------------.
-- | flit type| PAYLOAD DATA |parity bit |
-- '----------------------------------------------------------------------'
-- PAYLOAD DATA is written by the PE in FIFO_Data_out(27 downto 0)
-- Tail flits
-- 32 3bits 28 bits 1bit 0
-- .----------------------------------------------------------------------.
-- | flit type| PAYLOAD DATA |parity bit |
-- '----------------------------------------------------------------------'
-- PAYLOAD DATA is written by the PE in FIFO_Data_out(27 downto 0)
-- all the following signals are for sending data from processor to NoC
signal storage, storage_in : std_logic_vector(31 downto 0);
signal valid_data_in, valid_data: std_logic;
signal old_address: std_logic_vector(31 downto 2); -- Behrad: What is old address ?
signal P2N_FIFO_read_pointer, P2N_FIFO_read_pointer_in, P2N_FIFO_write_pointer, P2N_FIFO_write_pointer_in: std_logic_vector(3 downto 0);
signal P2N_write_en: std_logic;
signal P2N_FIFO_MEM_1, P2N_FIFO_MEM_1_in : std_logic_vector(31 downto 0);
signal P2N_FIFO_MEM_2, P2N_FIFO_MEM_2_in : std_logic_vector(31 downto 0);
signal P2N_FIFO_MEM_3, P2N_FIFO_MEM_3_in : std_logic_vector(31 downto 0);
signal P2N_FIFO_MEM_4, P2N_FIFO_MEM_4_in : std_logic_vector(31 downto 0);
signal P2N_full, P2N_empty: std_logic;
signal credit_counter_in, credit_counter_out: std_logic_vector(1 downto 0);
signal packet_counter_in, packet_counter_out: std_logic_vector(13 downto 0);
signal packet_length_counter_in, packet_length_counter_out: std_logic_vector(13 downto 0);
signal grant : std_logic;
type STATE_TYPE IS (IDLE, HEADER_FLIT, BODY_FLIT_1, BODY_FLIT, TAIL_FLIT, DIAGNOSIS_HEADER, DIAGNOSIS_BODY, DIAGNOSIS_BODY_1, DIAGNOSIS_TAIL);
signal state, state_in : STATE_TYPE := IDLE;
signal FIFO_Data_out : std_logic_vector(31 downto 0);
signal flag_register, flag_register_in : std_logic_vector(31 downto 0);
-- all the following signals are for sending the packets from NoC to processor
signal N2P_FIFO_MEM_1, N2P_FIFO_MEM_1_in : std_logic_vector(31 downto 0);
signal N2P_FIFO_MEM_2, N2P_FIFO_MEM_2_in : std_logic_vector(31 downto 0);
signal N2P_FIFO_MEM_3, N2P_FIFO_MEM_3_in : std_logic_vector(31 downto 0);
signal N2P_FIFO_MEM_4, N2P_FIFO_MEM_4_in : std_logic_vector(31 downto 0);
signal N2P_Data_out, data_read_in : std_logic_vector(31 downto 0);
signal N2P_FIFO_read_pointer, N2P_FIFO_read_pointer_in: std_logic_vector(3 downto 0);
signal N2P_FIFO_write_pointer, N2P_FIFO_write_pointer_in: std_logic_vector(3 downto 0);
signal N2P_full, N2P_empty: std_logic;
signal N2P_read_en, N2P_read_en_in, N2P_write_en: std_logic;
signal counter_register_in, counter_register : std_logic_vector(1 downto 0);
signal fault_info, fault_info_in: std_logic_vector(24 downto 0);
signal sent_info, fault_info_ready, fault_info_ready_in: std_logic;
signal self_diagnosis_reg_out, self_diagnosis_reg_in: std_logic_vector(31 downto 0);
signal self_diagnosis_flag, self_diagnosis_flag_in: std_logic;
begin
process(clk, enable, write_byte_enable) begin
if reset = '1' then
storage <= (others => '0');
valid_data <= '0';
P2N_FIFO_read_pointer <= "0001";
P2N_FIFO_write_pointer <= "0001";
P2N_FIFO_MEM_1 <= (others=>'0');
P2N_FIFO_MEM_2 <= (others=>'0');
P2N_FIFO_MEM_3 <= (others=>'0');
P2N_FIFO_MEM_4 <= (others=>'0');
credit_counter_out <= "11";
packet_length_counter_out <= (others=>'0');
state <= IDLE;
packet_counter_out <= (others=>'0');
------------------------------------------------
N2P_FIFO_MEM_1 <= (others=>'0');
N2P_FIFO_MEM_2 <= (others=>'0');
N2P_FIFO_MEM_3 <= (others=>'0');
N2P_FIFO_MEM_4 <= (others=>'0');
N2P_FIFO_read_pointer <= "0001";
N2P_FIFO_write_pointer <= "0001";
credit_out <= '0';
counter_register <= (others => '0');
N2P_read_en <= '0';
flag_register <= (others =>'0');
old_address <= (others =>'0');
fault_info <= (others => '0');
fault_info_ready <= '0';
self_diagnosis_reg_out <= (others => '0');
self_diagnosis_flag <= '0';
elsif clk'event and clk = '1' then
old_address <= address;
P2N_FIFO_write_pointer <= P2N_FIFO_write_pointer_in;
P2N_FIFO_read_pointer <= P2N_FIFO_read_pointer_in;
credit_counter_out <= credit_counter_in;
packet_length_counter_out <= packet_length_counter_in;
valid_data <= valid_data_in;
if P2N_write_en = '1' then
--write into the memory
P2N_FIFO_MEM_1 <= P2N_FIFO_MEM_1_in;
P2N_FIFO_MEM_2 <= P2N_FIFO_MEM_2_in;
P2N_FIFO_MEM_3 <= P2N_FIFO_MEM_3_in;
P2N_FIFO_MEM_4 <= P2N_FIFO_MEM_4_in;
end if;
packet_counter_out <= packet_counter_in;
if write_byte_enable /= "0000" then
storage <= storage_in;
end if;
state <= state_in;
------------------------------------------------
if N2P_write_en = '1' then
--write into the memory
N2P_FIFO_MEM_1 <= N2P_FIFO_MEM_1_in;
N2P_FIFO_MEM_2 <= N2P_FIFO_MEM_2_in;
N2P_FIFO_MEM_3 <= N2P_FIFO_MEM_3_in;
N2P_FIFO_MEM_4 <= N2P_FIFO_MEM_4_in;
end if;
counter_register <= counter_register_in;
N2P_FIFO_write_pointer <= N2P_FIFO_write_pointer_in;
N2P_FIFO_read_pointer <= N2P_FIFO_read_pointer_in;
credit_out <= '0';
N2P_read_en <= N2P_read_en_in;
if N2P_read_en = '1' then
credit_out <= '1';
end if;
flag_register <= flag_register_in;
fault_info <= fault_info_in;
fault_info_ready <= fault_info_ready_in;
self_diagnosis_reg_out <= self_diagnosis_reg_in;
self_diagnosis_flag <= self_diagnosis_flag_in;
end if;
end process;
-- everything bellow this line is pure combinatorial!
---------------------------------------------------------------------------------------
--below this is code for communication from PE 2 NoC
-- Process used for sending reconfiguration command from PE to router (which is part of NoC)
process(enable, address, write_byte_enable) begin
-- Some initializations
Reconfig_command <= '0';
Rxy_reconf_PE <= (others =>'0');
Cx_reconf_PE <= (others =>'0');
if address = reconfiguration_address and enable = '1' then
if write_byte_enable /= "0000" then
-- In this case, data_write definitely includes the connectivity bits and routing bits for
-- reconfiguring LBDR logic.
Rxy_reconf_PE <= data_write(7 downto 0); -- Rxy is 8 bits long
Cx_reconf_PE <= data_write(11 downto 8); -- Cx is 4 bits long
Reconfig_command <= '1';
end if;
end if;
end process;
process(write_byte_enable, enable, address, storage, data_write, valid_data, P2N_write_en) begin
storage_in <= storage ;
valid_data_in <= valid_data;
-- If PE wants to send data to NoC via NI (data is valid)
if enable = '1' and address = reserved_address then
if write_byte_enable /= "0000" then
valid_data_in <= '1';
end if;
-- Behrad: So according to Plasma, is write_byte_enable always one-hot ?
-- (of course it can also be "0000")
if write_byte_enable(0) = '1' then
storage_in(7 downto 0) <= data_write(7 downto 0);
end if;
if write_byte_enable(1) = '1' then
storage_in(15 downto 8) <= data_write(15 downto 8);
end if;
if write_byte_enable(2) = '1' then
storage_in(23 downto 16) <= data_write(23 downto 16);
end if;
if write_byte_enable(3) = '1' then
storage_in(31 downto 24) <= data_write(31 downto 24);
end if;
end if;
if P2N_write_en = '1' then
valid_data_in <= '0';
end if;
end process;
-- Process for storing in FIFO (based on the position write pointer is pointing to)
-- Write pointer is encoded as one-hot!
process(storage, P2N_FIFO_write_pointer, P2N_FIFO_MEM_1, P2N_FIFO_MEM_2, P2N_FIFO_MEM_3, P2N_FIFO_MEM_4)begin
case(P2N_FIFO_write_pointer) is
when "0001" => P2N_FIFO_MEM_1_in <= storage; P2N_FIFO_MEM_2_in <= P2N_FIFO_MEM_2; P2N_FIFO_MEM_3_in <= P2N_FIFO_MEM_3; P2N_FIFO_MEM_4_in <= P2N_FIFO_MEM_4;
when "0010" => P2N_FIFO_MEM_1_in <= P2N_FIFO_MEM_1; P2N_FIFO_MEM_2_in <= storage; P2N_FIFO_MEM_3_in <= P2N_FIFO_MEM_3; P2N_FIFO_MEM_4_in <= P2N_FIFO_MEM_4;
when "0100" => P2N_FIFO_MEM_1_in <= P2N_FIFO_MEM_1; P2N_FIFO_MEM_2_in <= P2N_FIFO_MEM_2; P2N_FIFO_MEM_3_in <= storage; P2N_FIFO_MEM_4_in <= P2N_FIFO_MEM_4;
when "1000" => P2N_FIFO_MEM_1_in <= P2N_FIFO_MEM_1; P2N_FIFO_MEM_2_in <= P2N_FIFO_MEM_2; P2N_FIFO_MEM_3_in <= P2N_FIFO_MEM_3; P2N_FIFO_MEM_4_in <= storage;
when others => P2N_FIFO_MEM_1_in <= P2N_FIFO_MEM_1; P2N_FIFO_MEM_2_in <= P2N_FIFO_MEM_2; P2N_FIFO_MEM_3_in <= P2N_FIFO_MEM_3; P2N_FIFO_MEM_4_in <= P2N_FIFO_MEM_4;
end case ;
end process;
-- Process for reading from FIFO (based on the position read pointer is pointing to)
-- read pointer is encoded as one-hot!
process(P2N_FIFO_read_pointer, P2N_FIFO_MEM_1, P2N_FIFO_MEM_2, P2N_FIFO_MEM_3, P2N_FIFO_MEM_4)begin
case( P2N_FIFO_read_pointer ) is
when "0001" => FIFO_Data_out <= P2N_FIFO_MEM_1;
when "0010" => FIFO_Data_out <= P2N_FIFO_MEM_2;
when "0100" => FIFO_Data_out <= P2N_FIFO_MEM_3;
when "1000" => FIFO_Data_out <= P2N_FIFO_MEM_4;
when others => FIFO_Data_out <= P2N_FIFO_MEM_1;
end case ;
end process;
-- Write pointer update process (after each write operation, write pointer is rotated one bit to the left)
process(P2N_write_en, P2N_FIFO_write_pointer)begin
if P2N_write_en = '1' then
P2N_FIFO_write_pointer_in <= P2N_FIFO_write_pointer(2 downto 0) & P2N_FIFO_write_pointer(3);
else
P2N_FIFO_write_pointer_in <= P2N_FIFO_write_pointer;
end if;
end process;
-- Read pointer update process (after each read operation, read pointer is rotated one bit to the left)
process(P2N_FIFO_read_pointer, grant, fault_info_ready)begin
P2N_FIFO_read_pointer_in <= P2N_FIFO_read_pointer;
if grant = '1' and fault_info_ready = '0' then -- Behrad: so grant here works somehow like read_en signal for FIFO ?
P2N_FIFO_read_pointer_in <= P2N_FIFO_read_pointer(2 downto 0) & P2N_FIFO_read_pointer(3);
end if;
end process;
process(P2N_full, valid_data) begin
if valid_data = '1' and P2N_full ='0' then
P2N_write_en <= '1';
else
P2N_write_en <= '0';
end if;
end process;
-- Process for updating full and empty signals
process(P2N_FIFO_write_pointer, P2N_FIFO_read_pointer) begin
P2N_empty <= '0';
P2N_full <= '0';
if P2N_FIFO_read_pointer = P2N_FIFO_write_pointer then
P2N_empty <= '1';
end if;
if P2N_FIFO_write_pointer = P2N_FIFO_read_pointer(0) & P2N_FIFO_read_pointer(3 downto 1) then
P2N_full <= '1';
end if;
end process;
process (credit_in, credit_counter_out, grant)begin
credit_counter_in <= credit_counter_out;
if credit_in = '1' and grant = '1' then
credit_counter_in <= credit_counter_out;
elsif credit_in = '1' and credit_counter_out < 3 then
credit_counter_in <= credit_counter_out + 1;
elsif grant = '1' and credit_counter_out > 0 then
credit_counter_in <= credit_counter_out - 1;
end if;
end process;
-- flag setting and clearing for self diagnosis
process(link_faults, turn_faults, self_diagnosis_flag, old_address)begin
if (link_faults /= "00000" or turn_faults /= "00000000000000000000") and SHMU_address = current_address then
self_diagnosis_flag_in <= '1';
elsif old_address = self_diagnosis_address then
self_diagnosis_flag_in <= '0';
else
self_diagnosis_flag_in <= self_diagnosis_flag;
end if;
end process;
-- handling fault information!
process(link_faults, turn_faults, sent_info, fault_info_ready, fault_info)begin
self_diagnosis_reg_in <= self_diagnosis_reg_out;
-- If current node is not SHMU, we need to send fault information to SHMU
if (link_faults /= "00000" or turn_faults /= "00000000") and SHMU_address /= current_address then
fault_info_in <= turn_faults & link_faults;
fault_info_ready_in <= '1';
-- If current node is SHMU, we handle it locally
elsif (link_faults /= "00000" or turn_faults /= "00000000") and SHMU_address = current_address then
self_diagnosis_reg_in <= "0000000" & turn_faults & link_faults;
else
fault_info_in <= fault_info;
fault_info_ready_in <= fault_info_ready;
end if;
if sent_info = '1' then
fault_info_ready_in <= '0';
end if;
end process;
process(P2N_empty, state, credit_counter_out, packet_length_counter_out, packet_counter_out, FIFO_Data_out, fault_info_ready)
begin
-- Some initializations
sent_info <= '0';
TX <= (others => '0');
grant<= '0';
packet_length_counter_in <= packet_length_counter_out;
packet_counter_in <= packet_counter_out;
case(state) is
when IDLE =>
if fault_info_ready = '1' then
state_in <= DIAGNOSIS_HEADER;
elsif P2N_empty = '0' then
state_in <= HEADER_FLIT;
else
state_in <= IDLE;
end if;
when HEADER_FLIT =>
if credit_counter_out /= "00" and P2N_empty = '0' then
grant <= '1';
--TX <= "001" & "0000" & FIFO_Data_out(23 downto 16) & FIFO_Data_out(31 downto 28) &
-- std_logic_vector(to_unsigned(current_address, 4)) & packet_counter_out & XOR_REDUCE("001" & "0000" &
-- FIFO_Data_out(23 downto 16) & FIFO_Data_out(31 downto 28) &
-- std_logic_vector(to_unsigned(current_address, 4)) & packet_counter_out);
TX <= "001" & std_logic_vector(to_unsigned(current_address, 14)) & FIFO_Data_out(13 downto 0) & XOR_REDUCE("001" & std_logic_vector(to_unsigned(current_address, 14)) & FIFO_Data_out(13 downto 0));
state_in <= BODY_FLIT_1;
else
state_in <= HEADER_FLIT;
end if;
when BODY_FLIT_1 =>
if credit_counter_out /= "00" and P2N_empty = '0'then
packet_length_counter_in <= (FIFO_Data_out(27 downto 14))-2;
grant <= '1';
TX <= "010" &FIFO_Data_out(27 downto 14) & packet_counter_out & XOR_REDUCE( "010" &FIFO_Data_out(27 downto 14) & packet_counter_out);
state_in <= BODY_FLIT;
else
state_in <= BODY_FLIT_1;
end if;
when BODY_FLIT =>
if credit_counter_out /= "00" and P2N_empty = '0'then
grant <= '1';
TX <= "010" & FIFO_Data_out(27 downto 0) & XOR_REDUCE("010" & FIFO_Data_out(27 downto 0));
packet_length_counter_in <= packet_length_counter_out - 1;
if packet_length_counter_out > 2 then
state_in <= BODY_FLIT;
else
state_in <= TAIL_FLIT;
end if;
else
state_in <= BODY_FLIT;
end if;
when TAIL_FLIT =>
if credit_counter_out /= "00" and P2N_empty = '0' then
grant <= '1';
packet_length_counter_in <= packet_length_counter_out - 1;
TX <= "100" & FIFO_Data_out(27 downto 0) & XOR_REDUCE("100" & FIFO_Data_out(27 downto 0));
packet_counter_in <= packet_counter_out +1;
state_in <= IDLE;
else
state_in <= TAIL_FLIT;
end if;
-- SHMU stuff ----------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------
when DIAGNOSIS_HEADER =>
if credit_counter_out /= "00" then
grant <= '1';
TX <= "001" & std_logic_vector(to_unsigned(current_address, 14)) & FIFO_Data_out(13 downto 0) & XOR_REDUCE("001" & std_logic_vector(to_unsigned(current_address, 14)) & FIFO_Data_out(13 downto 0));
--TX <= "001" & "000000000011" & "0000" & std_logic_vector(to_unsigned(current_address, 4)) & packet_counter_out & XOR_REDUCE("001" & "000000000011" & "0000" & std_logic_vector(to_unsigned(current_address, 4)) & packet_counter_out);
state_in <= DIAGNOSIS_BODY_1;
else
state_in <= DIAGNOSIS_HEADER;
end if;
when DIAGNOSIS_BODY_1 =>
if credit_counter_out /= "00" then
grant <= '1';
state_in <= DIAGNOSIS_BODY;
TX <= "010" & std_logic_vector(to_unsigned(4, 14)) & packet_counter_out & XOR_REDUCE( "010" & std_logic_vector(to_unsigned(4, 14)) & packet_counter_out );
else
state_in <= DIAGNOSIS_BODY_1;
end if;
when DIAGNOSIS_BODY =>
if credit_counter_out /= "00" then
grant <= '1';
--FD (Fault Diagnosis) : 01000110 01000100
-- fault info is 13 bits
TX <= "010" & "0100011001000100" & fault_info(11 downto 0) & XOR_REDUCE("010" & "0100011001000100" & fault_info(11 downto 0));
state_in <= DIAGNOSIS_TAIL;
else
state_in <= DIAGNOSIS_BODY;
end if;
when DIAGNOSIS_TAIL =>
if credit_counter_out /= "00" then
grant <= '1';
TX <= "100" & fault_info(24 downto 12) & "000000000000000" & XOR_REDUCE("100" & fault_info(24 downto 12) & "000000000000000");
state_in <= IDLE;
sent_info <= '1';
packet_counter_in <= packet_counter_out +1;
else
state_in <= DIAGNOSIS_TAIL;
end if;
when others =>
state_in <= IDLE;
end case ;
end procesS;
valid_out <= grant;
----------------------------------------------------------------------------------------
--below this is code for communication from NoC 2 PE
process(RX, N2P_FIFO_write_pointer, N2P_FIFO_MEM_1, N2P_FIFO_MEM_2, N2P_FIFO_MEM_3, N2P_FIFO_MEM_4)begin
case( N2P_FIFO_write_pointer ) is
when "0001" => N2P_FIFO_MEM_1_in <= RX; N2P_FIFO_MEM_2_in <= N2P_FIFO_MEM_2; N2P_FIFO_MEM_3_in <= N2P_FIFO_MEM_3; N2P_FIFO_MEM_4_in <= N2P_FIFO_MEM_4;
when "0010" => N2P_FIFO_MEM_1_in <= N2P_FIFO_MEM_1; N2P_FIFO_MEM_2_in <= RX; N2P_FIFO_MEM_3_in <= N2P_FIFO_MEM_3; N2P_FIFO_MEM_4_in <= N2P_FIFO_MEM_4;
when "0100" => N2P_FIFO_MEM_1_in <= N2P_FIFO_MEM_1; N2P_FIFO_MEM_2_in <= N2P_FIFO_MEM_2; N2P_FIFO_MEM_3_in <= RX; N2P_FIFO_MEM_4_in <= N2P_FIFO_MEM_4;
when "1000" => N2P_FIFO_MEM_1_in <= N2P_FIFO_MEM_1; N2P_FIFO_MEM_2_in <= N2P_FIFO_MEM_2; N2P_FIFO_MEM_3_in <= N2P_FIFO_MEM_3; N2P_FIFO_MEM_4_in <= RX;
when others => N2P_FIFO_MEM_1_in <= N2P_FIFO_MEM_1; N2P_FIFO_MEM_2_in <= N2P_FIFO_MEM_2; N2P_FIFO_MEM_3_in <= N2P_FIFO_MEM_3; N2P_FIFO_MEM_4_in <= N2P_FIFO_MEM_4;
end case ;
end process;
process(N2P_FIFO_read_pointer, N2P_FIFO_MEM_1, N2P_FIFO_MEM_2, N2P_FIFO_MEM_3, N2P_FIFO_MEM_4)begin
case( N2P_FIFO_read_pointer ) is
when "0001" => N2P_Data_out <= N2P_FIFO_MEM_1;
when "0010" => N2P_Data_out <= N2P_FIFO_MEM_2;
when "0100" => N2P_Data_out <= N2P_FIFO_MEM_3;
when "1000" => N2P_Data_out <= N2P_FIFO_MEM_4;
when others => N2P_Data_out <= N2P_FIFO_MEM_1;
end case ;
end process;
process(address, write_byte_enable, N2P_empty)begin
if address = reserved_address and write_byte_enable = "0000" and N2P_empty = '0' then
N2P_read_en_in <= '1';
else
N2P_read_en_in <= '0';
end if;
end process;
process(N2P_write_en, N2P_FIFO_write_pointer)begin
if N2P_write_en = '1'then
N2P_FIFO_write_pointer_in <= N2P_FIFO_write_pointer(2 downto 0)&N2P_FIFO_write_pointer(3);
else
N2P_FIFO_write_pointer_in <= N2P_FIFO_write_pointer;
end if;
end process;
process(N2P_read_en, N2P_empty, N2P_FIFO_read_pointer)begin
if (N2P_read_en = '1' and N2P_empty = '0') then
N2P_FIFO_read_pointer_in <= N2P_FIFO_read_pointer(2 downto 0)&N2P_FIFO_read_pointer(3);
else
N2P_FIFO_read_pointer_in <= N2P_FIFO_read_pointer;
end if;
end process;
process(N2P_full, valid_in) begin
if (valid_in = '1' and N2P_full ='0') then
N2P_write_en <= '1';
else
N2P_write_en <= '0';
end if;
end process;
process(N2P_FIFO_write_pointer, N2P_FIFO_read_pointer) begin
if N2P_FIFO_read_pointer = N2P_FIFO_write_pointer then
N2P_empty <= '1';
else
N2P_empty <= '0';
end if;
if N2P_FIFO_write_pointer = N2P_FIFO_read_pointer(0)&N2P_FIFO_read_pointer(3 downto 1) then
N2P_full <= '1';
else
N2P_full <= '0';
end if;
end process;
process(N2P_read_en, N2P_Data_out, old_address, flag_register) begin
if old_address = reserved_address and N2P_read_en = '1' then
data_read <= N2P_Data_out;
elsif old_address = flag_address then
data_read <= flag_register;
elsif old_address = counter_address then
data_read <= "000000000000000000000000000000" & counter_register;
elsif old_address = self_diagnosis_address then
data_read <= self_diagnosis_reg_out;
else
data_read <= (others => 'U');
end if;
end process;
process(N2P_write_en, N2P_read_en, RX, N2P_Data_out)begin
counter_register_in <= counter_register;
if N2P_write_en = '1' and RX(31 downto 29) = "001" and N2P_read_en = '1' and N2P_Data_out(31 downto 29) = "100" then
counter_register_in <= counter_register;
elsif N2P_write_en = '1' and RX(31 downto 29) = "001" then
counter_register_in <= counter_register +1;
elsif N2P_read_en = '1' and N2P_Data_out(31 downto 29) = "100" then
counter_register_in <= counter_register -1;
end if;
end process;
flag_register_in <= N2P_empty & P2N_full & self_diagnosis_flag & "00000000000000000000000000000";
--NI_read_flag <= N2P_empty;
--NI_write_flag <= P2N_full;
irq_out <= '0';
end; --architecture logic
|
-------------------------------------------------------------------------------
-- Title : Motortestboard
-------------------------------------------------------------------------------
-- Author : Fabian Greif <[email protected]>
-- Company : Roboterclub Aachen e.V.
-- Platform : Spartan 3-400
-------------------------------------------------------------------------------
-- Description:
-- This board is used to develop the FPGA and STM32F4xx Peripherals and
-- test if the system is suitable as main controller for the RCA robots.
--
-- The FPGA is able to control the following peripherals:
-- 2x Brushless Motor (with Hall-Sensors and Encoders)
-- 2x DC Motor (with Encoders)
-- 1x RGB LED
-- 3x Servo
-- ...
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.bus_pkg.all;
use work.spislave_pkg.all;
use work.motor_control_pkg.all;
use work.peripheral_register_pkg.all;
use work.pwm_module_pkg.all;
use work.dc_motor_module_pkg.all;
use work.bldc_motor_module_pkg.all;
use work.encoder_module_pkg.all;
use work.servo_module_pkg.all;
use work.adc_mcp3008_pkg.all;
use work.reg_file_pkg.all;
-------------------------------------------------------------------------------
entity toplevel is
port (
-- Motortestboard
led_red_p : out std_logic;
led_green_p : out std_logic;
led_blue_p : out std_logic;
-- BLDC 1 & 2
bldc1_driver_p : out bldc_driver_stage_type;
bldc1_hall_p : in hall_sensor_type;
bldc1_encoder_p : in encoder_type;
bldc1_encoder_index_p : in std_logic;
bldc2_driver_p : out bldc_driver_stage_type;
bldc2_hall_p : in hall_sensor_type;
bldc2_encoder_p : in encoder_type;
bldc2_encoder_index_p : in std_logic;
-- Motor 3 & 4
motor3_pwm1_p : out std_logic;
motor3_pwm2_p : out std_logic;
motor3_sd_np : out std_logic;
motor3_encoder_p : in encoder_type;
motor3_encoder_index_p : in std_logic;
motor4_pwm1_p : out std_logic;
motor4_pwm2_p : out std_logic;
motor4_sd_np : out std_logic;
motor4_encoder_p : in encoder_type;
motor4_encoder_index_p : in std_logic;
-- Encoder 6
encoder6_p : in encoder_type;
encoder6_index_p : in std_logic;
servo_p : out std_logic_vector(3 downto 1);
-- Connections to the STM32F407
cs_np : in std_logic;
sck_p : in std_logic;
miso_p : out std_logic;
mosi_p : in std_logic;
load_p : in std_logic; -- On the rising edge encoders etc are sampled
reset_n : in std_logic;
-- Internal connections
led_np : out std_logic_vector (3 downto 0);
sw_np : in std_logic_vector (1 downto 0);
adc_out_p : out adc_mcp3008_spi_out_type;
adc_in_p : in adc_mcp3008_spi_in_type;
clk : in std_logic
);
end toplevel;
architecture structural of toplevel is
signal reset_r : std_logic_vector(1 downto 0) := (others => '0');
signal reset : std_logic;
signal load_r : std_logic_vector(1 downto 0) := (others => '0');
signal load : std_logic;
signal sw_1r : std_logic_vector(1 downto 0);
signal sw_2r : std_logic_vector(1 downto 0);
signal register_out : std_logic_vector(15 downto 0);
signal register_in : std_logic_vector(15 downto 0);
signal encoder6_index_r : std_logic_vector(1 downto 0);
signal motor3_sd : std_logic := '1';
signal motor4_sd : std_logic := '1';
signal servo_signals : std_logic_vector(2 downto 0);
-- Connection to the Busmaster
signal bus_o : busmaster_out_type;
signal bus_i : busmaster_in_type;
-- Outputs form the Bus devices
signal bus_register_out : busdevice_out_type;
signal bus_adc_out : busdevice_out_type;
signal bus_pwm1_out : busdevice_out_type;
signal bus_pwm2_out : busdevice_out_type;
signal bus_pwm3_out : busdevice_out_type;
signal bus_bldc1_out : busdevice_out_type;
signal bus_bldc1_encoder_out : busdevice_out_type;
signal bus_bldc2_out : busdevice_out_type;
signal bus_bldc2_encoder_out : busdevice_out_type;
signal bus_motor3_pwm_out : busdevice_out_type;
signal bus_motor3_encoder_out : busdevice_out_type;
signal bus_motor4_pwm_out : busdevice_out_type;
signal bus_motor4_encoder_out : busdevice_out_type;
signal bus_encoder6_out : busdevice_out_type;
signal bus_servo_out : busdevice_out_type;
begin
-- synchronize reset and other signals
process (clk)
begin
if rising_edge(clk) then
reset_r <= reset_r(0) & reset_n;
load_r <= load_r(0) & load_p;
end if;
end process;
reset <= not reset_r(1);
load <= load_r(1);
----------------------------------------------------------------------------
-- SPI connection to the STM32F4xx and Busmaster
-- for the internal bus
spi : spi_slave
port map (
miso_p => miso_p,
mosi_p => mosi_p,
sck_p => sck_p,
csn_p => cs_np,
bus_o => bus_o,
bus_i => bus_i,
reset => reset,
clk => clk);
bus_i.data <= bus_register_out.data or bus_adc_out.data or
bus_pwm1_out.data or bus_pwm2_out.data or bus_pwm3_out.data or
bus_bldc1_out.data or bus_bldc1_encoder_out.data or
bus_bldc2_out.data or bus_bldc2_encoder_out.data or
bus_motor3_pwm_out.data or bus_motor3_encoder_out.data or
bus_motor4_pwm_out.data or bus_motor4_encoder_out.data or
bus_encoder6_out.data or
bus_servo_out.data;
----------------------------------------------------------------------------
-- Register
preg : peripheral_register
generic map (
BASE_ADDRESS => 16#0000#)
port map (
dout_p => register_out,
din_p => register_in,
bus_o => bus_register_out,
bus_i => bus_o,
reset => reset,
clk => clk);
process (clk)
begin
if rising_edge(clk) then
sw_1r <= not sw_np;
sw_2r <= sw_1r;
encoder6_index_r <= encoder6_index_r(0) & not encoder6_index_p;
end if;
end process;
register_in <= x"abc" & "0" & encoder6_index_r(1) & sw_2r;
led_np <= not register_out(3 downto 0);
-- component instantiation
adc : adc_mcp3008_module
generic map (
BASE_ADDRESS => 16#0080#)
port map (
adc_out_p => adc_out_p,
adc_in_p => adc_in_p,
bus_o => bus_adc_out,
bus_i => bus_o,
adc_values_o => open,
reset => reset,
clk => clk);
----------------------------------------------------------------------------
-- Bus devices
pwm_module_1 : pwm_module
generic map (
BASE_ADDRESS => 16#0001#,
WIDTH => 16,
PRESCALER => 2)
port map (
pwm_p => led_red_p,
bus_o => bus_pwm1_out,
bus_i => bus_o,
reset => reset,
clk => clk);
pwm_module_2 : pwm_module
generic map (
BASE_ADDRESS => 16#0002#,
WIDTH => 16,
PRESCALER => 2)
port map (
pwm_p => led_green_p,
bus_o => bus_pwm2_out,
bus_i => bus_o,
reset => reset,
clk => clk);
pwm_module_3 : pwm_module
generic map (
BASE_ADDRESS => 16#0003#,
WIDTH => 16,
PRESCALER => 2)
port map (
pwm_p => led_blue_p,
bus_o => bus_pwm3_out,
bus_i => bus_o,
reset => reset,
clk => clk);
-----------------------------------------------------------------------------
-- BLDC motors 1 & 2
bldc1 : bldc_motor_module
generic map (
BASE_ADDRESS => 16#0010#,
WIDTH => 10,
PRESCALER => 1)
port map (
driver_stage_p => bldc1_driver_p,
hall_p => bldc1_hall_p,
bus_o => bus_bldc1_out,
bus_i => bus_o,
reset => reset,
clk => clk);
bldc1_encoder : encoder_module_extended
generic map (
BASE_ADDRESS => 16#0012#)
port map (
encoder_p => bldc1_encoder_p,
index_p => bldc1_encoder_index_p,
load_p => load,
bus_o => bus_bldc1_encoder_out,
bus_i => bus_o,
reset => reset,
clk => clk);
bldc2 : bldc_motor_module
generic map (
BASE_ADDRESS => 16#0020#,
WIDTH => 10,
PRESCALER => 1)
port map (
driver_stage_p => bldc2_driver_p,
hall_p => bldc2_hall_p,
bus_o => bus_bldc2_out,
bus_i => bus_o,
reset => reset,
clk => clk);
bldc2_encoder : encoder_module_extended
generic map (
BASE_ADDRESS => 16#0022#)
port map (
encoder_p => bldc2_encoder_p,
index_p => bldc2_encoder_index_p,
load_p => load,
bus_o => bus_bldc2_encoder_out,
bus_i => bus_o,
reset => reset,
clk => clk);
----------------------------------------------------------------------------
-- DC Motors 3 & 4
motor3_pwm_module : dc_motor_module
generic map (
BASE_ADDRESS => 16#0030#,
WIDTH => 12,
PRESCALER => 2)
port map (
pwm1_p => motor3_pwm1_p,
pwm2_p => motor3_pwm2_p,
sd_p => motor3_sd,
bus_o => bus_motor3_pwm_out,
bus_i => bus_o,
reset => reset,
clk => clk);
motor3_sd_np <= not motor3_sd;
motor3_encoder_module : encoder_module
generic map (
BASE_ADDRESS => 16#0032#)
port map (
encoder_p => motor3_encoder_p,
index_p => motor3_encoder_index_p,
load_p => load,
bus_o => bus_motor3_encoder_out,
bus_i => bus_o,
reset => reset,
clk => clk);
motor4_pwm_module : dc_motor_module
generic map (
BASE_ADDRESS => 16#0040#,
WIDTH => 12,
PRESCALER => 2)
port map (
pwm1_p => motor4_pwm1_p,
pwm2_p => motor4_pwm2_p,
sd_p => motor4_sd,
bus_o => bus_motor4_pwm_out,
bus_i => bus_o,
reset => reset,
clk => clk);
motor4_sd_np <= not motor4_sd;
motor4_encoder_module : encoder_module
generic map (
BASE_ADDRESS => 16#0042#)
port map (
encoder_p => motor4_encoder_p,
index_p => motor4_encoder_index_p,
load_p => load,
bus_o => bus_motor4_encoder_out,
bus_i => bus_o,
reset => reset,
clk => clk);
----------------------------------------------------------------------------
-- Encoder 6
encoder6 : encoder_module
generic map (
BASE_ADDRESS => 16#0060#)
port map (
encoder_p => encoder6_p,
index_p => encoder6_index_p,
load_p => load,
bus_o => bus_encoder6_out,
bus_i => bus_o,
reset => reset,
clk => clk);
----------------------------------------------------------------------------
-- Servos
servo_module_1: servo_module
generic map (
BASE_ADDRESS => 16#0070#,
SERVO_COUNT => 3)
port map (
servo_p => servo_signals,
bus_o => bus_servo_out,
bus_i => bus_o,
reset => reset,
clk => clk);
servo_p <= servo_signals;
end structural;
|
----------------------------------------------------------------------------------
-- Company: Caltech EE 119B
-- Engineer: Albert Gural and Bryan He
--
-- Create Date: 15:07:46 01/25/2015
-- Design Name: AVR-Processor
-- Module Name: ALUFBlock - DataFlow
-- Project Name: AVR-Processor
-- Target Devices: Xilinx Spartan III XC3S1200EFGG3204C
-- Tool versions: Xilinx ISE 14.7
-- Description: Computes logical operations on two arguments.
--
-- Revision: 1.0
-- For file history, see https://github.com/agural/AVR-Processor
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity ALUFBlock is
port (
operand : in std_logic_vector(3 downto 0); -- Selects which logic operation to do
opA : in std_logic_vector(7 downto 0); -- Argument A
opB : in std_logic_vector(7 downto 0); -- Argument B
result : out std_logic_vector(7 downto 0) -- Result of logic operation
);
end ALUFBlock;
architecture DataFlow of ALUFBlock is
begin
process(operand, opA, opB)
begin
-- each bit [i] of result is an F-block MUX of the bit of the operand
-- indexed by bits [i] of opA and opB
for i in 0 to 7 loop
if (is_x(operand) or is_x(opA) or is_x(opB)) then
result(i) <= 'X';
else
result(i) <= operand(to_integer(unsigned(std_logic_vector(to_unsigned(0,0)) & opA(i) & opB(i))));
end if;
end loop;
end process;
end DataFlow;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity data_memory is
port(clk : in std_logic;
rst : in std_logic;
address : in std_logic_vector(31 downto 0);
data_in : in std_logic_vector(31 downto 0);
data_out : out std_logic_vector(31 downto 0);
we : in std_logic);
end data_memory;
architecture Behavioral of data_memory is
type memory_data_type is array (63 downto 0) of std_logic_vector(31 downto 0); --256 B of data memory
signal memory_data : memory_data_type;
signal address_short : std_logic_vector(5 downto 0);
begin
address_short <= address(5 downto 0);
main : process (clk, rst) is
begin
if rst = '1' then
memory_data <= (others => (others => '0'));
elsif falling_edge(clk) then
if we = '1' then
memory_data(conv_integer(unsigned(address_short))) <= data_in;
end if;
end if;
end process;
data_out <= memory_data(conv_integer(unsigned(address_short)));
end Behavioral;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity data_memory is
port(clk : in std_logic;
rst : in std_logic;
address : in std_logic_vector(31 downto 0);
data_in : in std_logic_vector(31 downto 0);
data_out : out std_logic_vector(31 downto 0);
we : in std_logic);
end data_memory;
architecture Behavioral of data_memory is
type memory_data_type is array (63 downto 0) of std_logic_vector(31 downto 0); --256 B of data memory
signal memory_data : memory_data_type;
signal address_short : std_logic_vector(5 downto 0);
begin
address_short <= address(5 downto 0);
main : process (clk, rst) is
begin
if rst = '1' then
memory_data <= (others => (others => '0'));
elsif falling_edge(clk) then
if we = '1' then
memory_data(conv_integer(unsigned(address_short))) <= data_in;
end if;
end if;
end process;
data_out <= memory_data(conv_integer(unsigned(address_short)));
end Behavioral;
|
architecture RTL of FIFO is
type state_machine is (idle, write, read, done);
-- Violations below
TYPE state_machine is (idle, write, read, done);
begin
end architecture RTL;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: ekyr.kth.se:user:axi_spi_master:1.0
-- IP Revision: 9
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY DemoInterconnect_axi_spi_master_0_1 IS
PORT (
m_spi_mosi : OUT STD_LOGIC;
m_spi_miso : IN STD_LOGIC;
m_spi_ss : OUT STD_LOGIC;
m_spi_sclk : OUT STD_LOGIC;
s00_axi_awaddr : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s00_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s00_axi_awvalid : IN STD_LOGIC;
s00_axi_awready : OUT STD_LOGIC;
s00_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s00_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s00_axi_wvalid : IN STD_LOGIC;
s00_axi_wready : OUT STD_LOGIC;
s00_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s00_axi_bvalid : OUT STD_LOGIC;
s00_axi_bready : IN STD_LOGIC;
s00_axi_araddr : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s00_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s00_axi_arvalid : IN STD_LOGIC;
s00_axi_arready : OUT STD_LOGIC;
s00_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s00_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s00_axi_rvalid : OUT STD_LOGIC;
s00_axi_rready : IN STD_LOGIC;
s00_axi_aclk : IN STD_LOGIC;
s00_axi_aresetn : IN STD_LOGIC
);
END DemoInterconnect_axi_spi_master_0_1;
ARCHITECTURE DemoInterconnect_axi_spi_master_0_1_arch OF DemoInterconnect_axi_spi_master_0_1 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF DemoInterconnect_axi_spi_master_0_1_arch: ARCHITECTURE IS "yes";
COMPONENT axi_spi_master_v1_0 IS
GENERIC (
C_S00_AXI_DATA_WIDTH : INTEGER; -- Width of S_AXI data bus
C_S00_AXI_ADDR_WIDTH : INTEGER; -- Width of S_AXI address bus
SPI_DATA_WIDTH : INTEGER;
SPI_CLK_DIV : INTEGER
);
PORT (
m_spi_mosi : OUT STD_LOGIC;
m_spi_miso : IN STD_LOGIC;
m_spi_ss : OUT STD_LOGIC;
m_spi_sclk : OUT STD_LOGIC;
s00_axi_awaddr : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s00_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s00_axi_awvalid : IN STD_LOGIC;
s00_axi_awready : OUT STD_LOGIC;
s00_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s00_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s00_axi_wvalid : IN STD_LOGIC;
s00_axi_wready : OUT STD_LOGIC;
s00_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s00_axi_bvalid : OUT STD_LOGIC;
s00_axi_bready : IN STD_LOGIC;
s00_axi_araddr : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s00_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s00_axi_arvalid : IN STD_LOGIC;
s00_axi_arready : OUT STD_LOGIC;
s00_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s00_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s00_axi_rvalid : OUT STD_LOGIC;
s00_axi_rready : IN STD_LOGIC;
s00_axi_aclk : IN STD_LOGIC;
s00_axi_aresetn : IN STD_LOGIC
);
END COMPONENT axi_spi_master_v1_0;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF DemoInterconnect_axi_spi_master_0_1_arch: ARCHITECTURE IS "axi_spi_master_v1_0,Vivado 2017.3";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF DemoInterconnect_axi_spi_master_0_1_arch : ARCHITECTURE IS "DemoInterconnect_axi_spi_master_0_1,axi_spi_master_v1_0,{}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER OF s00_axi_aresetn: SIGNAL IS "XIL_INTERFACENAME S00_AXI_RST, POLARITY ACTIVE_LOW, XIL_INTERFACENAME s00_axi_aresetn, POLARITY ACTIVE_LOW";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 S00_AXI_RST RST, xilinx.com:signal:reset:1.0 s00_axi_aresetn RST";
ATTRIBUTE X_INTERFACE_PARAMETER OF s00_axi_aclk: SIGNAL IS "XIL_INTERFACENAME S00_AXI_CLK, ASSOCIATED_BUSIF S00_AXI, ASSOCIATED_RESET s00_axi_aresetn, FREQ_HZ 100000000, PHASE 0.000, XIL_INTERFACENAME s00_axi_aclk, ASSOCIATED_RESET s00_axi_aresetn, FREQ_HZ 72000000, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, ASSOCIATED_BUSIF S00_AXI";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S00_AXI_CLK CLK, xilinx.com:signal:clock:1.0 s00_axi_aclk CLK";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI RREADY";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_arprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI ARPROT";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_awprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI AWPROT";
ATTRIBUTE X_INTERFACE_PARAMETER OF s00_axi_awaddr: SIGNAL IS "XIL_INTERFACENAME S00_AXI, WIZ_DATA_WIDTH 32, WIZ_NUM_REG 4, SUPPORTS_NARROW_BURST 0, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 72000000, ID_WIDTH 0, ADDR_WIDTH 4, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI AWADDR";
ATTRIBUTE X_INTERFACE_PARAMETER OF m_spi_sclk: SIGNAL IS "XIL_INTERFACENAME m_spi_sclk, ASSOCIATED_CLKEN m_spi_ss, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN DemoInterconnect_axi_spi_master_0_1_m_spi_sclk";
ATTRIBUTE X_INTERFACE_INFO OF m_spi_sclk: SIGNAL IS "xilinx.com:signal:clock:1.0 m_spi_sclk CLK";
ATTRIBUTE X_INTERFACE_PARAMETER OF m_spi_ss: SIGNAL IS "XIL_INTERFACENAME m_spi_ss, FREQ_HZ 100000000, PHASE 0, POLARITY ACTIVE_LOW";
ATTRIBUTE X_INTERFACE_INFO OF m_spi_ss: SIGNAL IS "xilinx.com:signal:clockenable:1.0 m_spi_ss CE";
ATTRIBUTE X_INTERFACE_PARAMETER OF m_spi_miso: SIGNAL IS "XIL_INTERFACENAME m_spi_miso, LAYERED_METADATA undef";
ATTRIBUTE X_INTERFACE_INFO OF m_spi_miso: SIGNAL IS "xilinx.com:signal:data:1.0 m_spi_miso DATA";
ATTRIBUTE X_INTERFACE_PARAMETER OF m_spi_mosi: SIGNAL IS "XIL_INTERFACENAME m_spi_mosi, LAYERED_METADATA undef";
ATTRIBUTE X_INTERFACE_INFO OF m_spi_mosi: SIGNAL IS "xilinx.com:signal:data:1.0 m_spi_mosi DATA";
BEGIN
U0 : axi_spi_master_v1_0
GENERIC MAP (
C_S00_AXI_DATA_WIDTH => 32,
C_S00_AXI_ADDR_WIDTH => 4,
SPI_DATA_WIDTH => 8,
SPI_CLK_DIV => 6
)
PORT MAP (
m_spi_mosi => m_spi_mosi,
m_spi_miso => m_spi_miso,
m_spi_ss => m_spi_ss,
m_spi_sclk => m_spi_sclk,
s00_axi_awaddr => s00_axi_awaddr,
s00_axi_awprot => s00_axi_awprot,
s00_axi_awvalid => s00_axi_awvalid,
s00_axi_awready => s00_axi_awready,
s00_axi_wdata => s00_axi_wdata,
s00_axi_wstrb => s00_axi_wstrb,
s00_axi_wvalid => s00_axi_wvalid,
s00_axi_wready => s00_axi_wready,
s00_axi_bresp => s00_axi_bresp,
s00_axi_bvalid => s00_axi_bvalid,
s00_axi_bready => s00_axi_bready,
s00_axi_araddr => s00_axi_araddr,
s00_axi_arprot => s00_axi_arprot,
s00_axi_arvalid => s00_axi_arvalid,
s00_axi_arready => s00_axi_arready,
s00_axi_rdata => s00_axi_rdata,
s00_axi_rresp => s00_axi_rresp,
s00_axi_rvalid => s00_axi_rvalid,
s00_axi_rready => s00_axi_rready,
s00_axi_aclk => s00_axi_aclk,
s00_axi_aresetn => s00_axi_aresetn
);
END DemoInterconnect_axi_spi_master_0_1_arch;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
use work.mem_bus_pkg.all;
use work.endianness_pkg.all;
entity bus_analyzer_32 is
generic (
g_big_endian : boolean );
port (
clock : in std_logic;
reset : in std_logic;
addr : in std_logic_vector(15 downto 0);
data : in std_logic_vector(7 downto 0);
rstn : in std_logic;
phi2 : in std_logic;
rwn : in std_logic;
ba : in std_logic;
dman : in std_logic;
ROMLn : in std_logic;
ROMHn : in std_logic;
EXROMn : in std_logic;
GAMEn : in std_logic;
IO1n : in std_logic;
IO2n : in std_logic;
IRQn : in std_logic;
NMIn : in std_logic;
trigger : in std_logic;
sync : in std_logic;
drv_enable : out std_logic;
---
mem_req : out t_mem_req_32;
mem_resp : in t_mem_resp_32;
debug_data : out std_logic_vector(31 downto 0);
debug_valid : out std_logic;
io_req : in t_io_req;
io_resp : out t_io_resp );
end entity;
architecture gideon of bus_analyzer_32 is
type t_state is (idle, writing, recording, wait_trigger, wait_sync);
signal enable_log : std_logic;
signal ev_addr : unsigned(24 downto 0);
signal state : t_state;
signal vector_in : std_logic_vector(31 downto 0);
signal vector_c : std_logic_vector(31 downto 0);
signal vector_d1 : std_logic_vector(31 downto 0);
signal vector_d2 : std_logic_vector(31 downto 0);
signal vector_d3 : std_logic_vector(31 downto 0);
signal ba_history : std_logic_vector(2 downto 0) := "000";
signal debug_data_i : std_logic_vector(31 downto 0) := (others => '0');
signal debug_valid_i: std_logic := '0';
signal mem_request : std_logic;
signal phi_c : std_logic := '0';
signal phi_d1 : std_logic := '0';
signal phi_d2 : std_logic := '0';
signal dman_c : std_logic := '0';
signal io : std_logic;
signal interrupt : std_logic;
signal rom : std_logic;
signal frame_tick : std_logic := '0';
signal counter : integer range 0 to 312*63; -- PAL
signal drv_enable_i : std_logic;
signal cpu_cycle_enable : std_logic := '1';
signal vic_cycle_enable : std_logic := '1';
begin
io <= io1n and io2n;
rom <= romln and romhn;
interrupt <= irqn and nmin;
vector_in <= phi2 & gamen & exromn & ba & irqn & rom & nmin & rwn & data & addr;
--vector_in <= phi2 & gamen & exromn & ba & irqn & rom & nmin & rwn & data & addr;
--vector_in <= phi2 & gamen & exromn & ba & interrupt & rom & io & rwn & data & addr;
debug_data <= debug_data_i;
debug_valid <= debug_valid_i;
process(clock)
begin
if rising_edge(clock) then
dman_c <= dman;
phi_c <= phi2;
phi_d1 <= phi_c;
phi_d2 <= phi_d1;
vector_c <= vector_in;
vector_d1 <= vector_c;
vector_d2 <= vector_d1;
vector_d3 <= vector_d2;
-- BA 1 1 1 0 0 0 0 0 0 0 1 1 1
-- BA0 1 1 1 1 0 0 0 0 0 0 0 1 1
-- BA1 1 1 1 1 1 0 0 0 0 0 0 0 1
-- BA2 1 1 1 1 1 1 0 0 0 0 0 0 0
-- CPU 1 1 1 1 1 1 0 0 0 0 1 1 1
--
debug_valid_i <= '0';
if phi_d2 /= phi_d1 then
debug_data_i <= vector_d3;
if phi_d2 = '1' then
ba_history <= ba_history(1 downto 0) & vector_d3(28); -- BA position!
end if;
if phi_d2 = '1' then
if (vector_d3(28) = '1' or ba_history /= "000" or drv_enable_i = '1') and cpu_cycle_enable = '1' then
debug_valid_i <= '1';
elsif vic_cycle_enable = '1' then
debug_valid_i <= '1';
end if;
elsif vic_cycle_enable = '1' then
debug_valid_i <= '1';
end if;
end if;
if sync = '1' then
counter <= 312 * 63 - 1;
elsif phi_d1 = '1' and phi_d2 = '0' then
if counter = 0 then
counter <= 312 * 63 - 1;
frame_tick <= '1';
else
counter <= counter - 1;
frame_tick <= '0';
end if;
end if;
case state is
when idle =>
if enable_log = '1' then
state <= wait_trigger;
end if;
when wait_trigger =>
if enable_log = '0' then
state <= idle;
elsif trigger = '1' then
state <= wait_sync;
end if;
when wait_sync =>
if enable_log = '0' then
state <= idle;
elsif frame_tick = '1' then
state <= recording;
end if;
when recording =>
if debug_valid_i = '1' then
mem_request <= '1';
state <= writing;
end if;
when writing =>
if mem_resp.rack='1' and mem_resp.rack_tag=X"F0" then
ev_addr <= ev_addr + 4;
if ev_addr = 16#1FFFFF4# then
enable_log <= '0';
end if;
mem_request <= '0';
if enable_log = '0' then
state <= idle;
else
state <= recording;
end if;
end if;
when others =>
null;
end case;
io_resp <= c_io_resp_init;
if io_req.read='1' then
io_resp.ack <= '1';
if g_big_endian then
case io_req.address(2 downto 0) is
when "011" =>
io_resp.data <= std_logic_vector(ev_addr(7 downto 0));
when "010" =>
io_resp.data <= std_logic_vector(ev_addr(15 downto 8));
when "001" =>
io_resp.data <= std_logic_vector(ev_addr(23 downto 16));
when "000" =>
io_resp.data <= "0000001" & ev_addr(24);
when others =>
null;
end case;
else
case io_req.address(2 downto 0) is
when "000" =>
io_resp.data <= std_logic_vector(ev_addr(7 downto 0));
when "001" =>
io_resp.data <= std_logic_vector(ev_addr(15 downto 8));
when "010" =>
io_resp.data <= std_logic_vector(ev_addr(23 downto 16));
when "011" =>
io_resp.data <= "0000001" & ev_addr(24);
when others =>
null;
end case;
end if;
elsif io_req.write='1' then
io_resp.ack <= '1';
case io_req.address(3 downto 0) is
when X"6" =>
enable_log <= '0';
when X"7" =>
ev_addr <= (others => '0');
enable_log <= '1';
when X"8" =>
cpu_cycle_enable <= io_req.data(0);
vic_cycle_enable <= io_req.data(1);
drv_enable_i <= io_req.data(2);
when others =>
null;
end case;
end if;
if reset='1' then
state <= idle;
enable_log <= '0';
mem_request <= '0';
ev_addr <= (others => '0');
drv_enable_i <= '0';
end if;
end if;
end process;
drv_enable <= drv_enable_i;
mem_req.data <= byte_swap(debug_data_i, g_big_endian);
mem_req.request <= mem_request;
mem_req.tag <= X"F0";
mem_req.address <= "1" & unsigned(ev_addr);
mem_req.read_writen <= '0'; -- write only
mem_req.byte_en <= "1111";
end gideon;
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:15:16 07/16/2015
-- Design Name:
-- Module Name: C:/Users/rccoder/ALU/Lab3/count4_tb.vhd
-- Project Name: Lab3
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: count4
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY count4_tb IS
END count4_tb;
ARCHITECTURE behavior OF count4_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT count4
PORT(
clk : IN std_logic;
clrn : IN std_logic;
q : OUT std_logic_vector(3 downto 0)
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal clrn : std_logic := '0';
--Outputs
signal q : std_logic_vector(3 downto 0);
-- Clock period definitions
constant clk_period : time := 100 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: count4 PORT MAP (
clk => clk,
clrn => clrn,
q => q
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 10 ns;
clrn <= '0';
wait for clk_period*2;
wait for 10 ns;
clrn <= '1';
wait for clk_period*15;
clrn <= '0';
-- insert stimulus here
wait;
end process;
END;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc175.vhd,v 1.2 2001-10-26 16:30:12 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s03b03x01p03n02i00175ent IS
END c04s03b03x01p03n02i00175ent;
ARCHITECTURE c04s03b03x01p03n02i00175arch OF c04s03b03x01p03n02i00175ent IS
signal Addr : bit;
alias SIGN1 : integer is Addr; -- Failure_here
-- error as Addr is of type bit
BEGIN
TESTING: PROCESS
BEGIN
wait for 10 ns;
assert FALSE
report "***FAILED TEST: c04s03b03x01p03n02i00175 - Alias base type does not match subtype indication."
severity ERROR;
wait;
END PROCESS TESTING;
END c04s03b03x01p03n02i00175arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc175.vhd,v 1.2 2001-10-26 16:30:12 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s03b03x01p03n02i00175ent IS
END c04s03b03x01p03n02i00175ent;
ARCHITECTURE c04s03b03x01p03n02i00175arch OF c04s03b03x01p03n02i00175ent IS
signal Addr : bit;
alias SIGN1 : integer is Addr; -- Failure_here
-- error as Addr is of type bit
BEGIN
TESTING: PROCESS
BEGIN
wait for 10 ns;
assert FALSE
report "***FAILED TEST: c04s03b03x01p03n02i00175 - Alias base type does not match subtype indication."
severity ERROR;
wait;
END PROCESS TESTING;
END c04s03b03x01p03n02i00175arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc175.vhd,v 1.2 2001-10-26 16:30:12 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s03b03x01p03n02i00175ent IS
END c04s03b03x01p03n02i00175ent;
ARCHITECTURE c04s03b03x01p03n02i00175arch OF c04s03b03x01p03n02i00175ent IS
signal Addr : bit;
alias SIGN1 : integer is Addr; -- Failure_here
-- error as Addr is of type bit
BEGIN
TESTING: PROCESS
BEGIN
wait for 10 ns;
assert FALSE
report "***FAILED TEST: c04s03b03x01p03n02i00175 - Alias base type does not match subtype indication."
severity ERROR;
wait;
END PROCESS TESTING;
END c04s03b03x01p03n02i00175arch;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v6_3 Core - Random Number Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: random.vhd
--
-- Description:
-- Random Generator
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY RANDOM IS
GENERIC ( WIDTH : INTEGER := 32;
SEED : INTEGER :=2
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0) --OUTPUT VECTOR
);
END RANDOM;
ARCHITECTURE BEHAVIORAL OF RANDOM IS
BEGIN
PROCESS(CLK)
VARIABLE RAND_TEMP : STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0):=CONV_STD_LOGIC_VECTOR(SEED,WIDTH);
VARIABLE TEMP : STD_LOGIC := '0';
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
RAND_TEMP := CONV_STD_LOGIC_VECTOR(SEED,WIDTH);
ELSE
IF(EN = '1') THEN
TEMP := RAND_TEMP(WIDTH-1) XOR RAND_TEMP(WIDTH-2);
RAND_TEMP(WIDTH-1 DOWNTO 1) := RAND_TEMP(WIDTH-2 DOWNTO 0);
RAND_TEMP(0) := TEMP;
END IF;
END IF;
END IF;
RANDOM_NUM <= RAND_TEMP;
END PROCESS;
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v6_3 Core - Random Number Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: random.vhd
--
-- Description:
-- Random Generator
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY RANDOM IS
GENERIC ( WIDTH : INTEGER := 32;
SEED : INTEGER :=2
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0) --OUTPUT VECTOR
);
END RANDOM;
ARCHITECTURE BEHAVIORAL OF RANDOM IS
BEGIN
PROCESS(CLK)
VARIABLE RAND_TEMP : STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0):=CONV_STD_LOGIC_VECTOR(SEED,WIDTH);
VARIABLE TEMP : STD_LOGIC := '0';
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
RAND_TEMP := CONV_STD_LOGIC_VECTOR(SEED,WIDTH);
ELSE
IF(EN = '1') THEN
TEMP := RAND_TEMP(WIDTH-1) XOR RAND_TEMP(WIDTH-2);
RAND_TEMP(WIDTH-1 DOWNTO 1) := RAND_TEMP(WIDTH-2 DOWNTO 0);
RAND_TEMP(0) := TEMP;
END IF;
END IF;
END IF;
RANDOM_NUM <= RAND_TEMP;
END PROCESS;
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v6_3 Core - Random Number Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: random.vhd
--
-- Description:
-- Random Generator
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY RANDOM IS
GENERIC ( WIDTH : INTEGER := 32;
SEED : INTEGER :=2
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0) --OUTPUT VECTOR
);
END RANDOM;
ARCHITECTURE BEHAVIORAL OF RANDOM IS
BEGIN
PROCESS(CLK)
VARIABLE RAND_TEMP : STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0):=CONV_STD_LOGIC_VECTOR(SEED,WIDTH);
VARIABLE TEMP : STD_LOGIC := '0';
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
RAND_TEMP := CONV_STD_LOGIC_VECTOR(SEED,WIDTH);
ELSE
IF(EN = '1') THEN
TEMP := RAND_TEMP(WIDTH-1) XOR RAND_TEMP(WIDTH-2);
RAND_TEMP(WIDTH-1 DOWNTO 1) := RAND_TEMP(WIDTH-2 DOWNTO 0);
RAND_TEMP(0) := TEMP;
END IF;
END IF;
END IF;
RANDOM_NUM <= RAND_TEMP;
END PROCESS;
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v6_3 Core - Random Number Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: random.vhd
--
-- Description:
-- Random Generator
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY RANDOM IS
GENERIC ( WIDTH : INTEGER := 32;
SEED : INTEGER :=2
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0) --OUTPUT VECTOR
);
END RANDOM;
ARCHITECTURE BEHAVIORAL OF RANDOM IS
BEGIN
PROCESS(CLK)
VARIABLE RAND_TEMP : STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0):=CONV_STD_LOGIC_VECTOR(SEED,WIDTH);
VARIABLE TEMP : STD_LOGIC := '0';
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
RAND_TEMP := CONV_STD_LOGIC_VECTOR(SEED,WIDTH);
ELSE
IF(EN = '1') THEN
TEMP := RAND_TEMP(WIDTH-1) XOR RAND_TEMP(WIDTH-2);
RAND_TEMP(WIDTH-1 DOWNTO 1) := RAND_TEMP(WIDTH-2 DOWNTO 0);
RAND_TEMP(0) := TEMP;
END IF;
END IF;
END IF;
RANDOM_NUM <= RAND_TEMP;
END PROCESS;
END ARCHITECTURE;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
library work;
entity bin_alu is
generic(NUMBITS : natural := 32);
Port ( Atemp : in STD_LOGIC_VECTOR(NUMBITS - 1 downto 0);
Btemp : in STD_LOGIC_VECTOR(NUMBITS - 1 downto 0);
A : in STD_LOGIC_VECTOR(NUMBITS - 1 downto 0);
B : in STD_LOGIC_VECTOR(NUMBITS - 1 downto 0);
opcode : in STD_LOGIC_VECTOR(3 downto 0);
result : out STD_LOGIC_VECTOR(NUMBITS - 1 downto 0);
carryout : out STD_LOGIC;
overflow : out STD_LOGIC;
zero : out STD_LOGIC);
end bin_alu;
architecture Behavioral of bin_alu is
--temp signal for alu
signal stuff: std_logic_vector(NUMBITS downto 0);
begin
process (A, B, opcode, stuff, Atemp, Btemp)
begin
--UNSIGNED ADD
if opcode = "1000" then
stuff <= std_logic_vector( unsigned('0' & A ) + unsigned( '0' & B));
result <= stuff(NUMBITS-1 downto 0);
--carryout <= '1';
carryout <= stuff(NUMBITS);
overflow <= '0';
if stuff(NUMBITS downto 0) = 0 then
zero <= '1';
else
zero <= '0';
end if;
--SIGNED ADD
elsif opcode = "1100" then
stuff <= std_logic_vector( signed('0' & A) + signed('0' & B) );
result <= stuff(NUMBITS-1 downto 0);
overflow <= '0';
carryout <= stuff(NUMBITS);
if stuff(NUMBITS - 1 downto 0) = 0 then
zero <= '1';
else
zero <= '0';
end if;
--UNSIGNED SUB
elsif opcode = "1001" then
stuff <= std_logic_vector( ('0' & unsigned(A) ) + ( '0' & ((not unsigned(B)) + 1)));
result <= stuff(NUMBITS-1 downto 0);
if (Atemp < Btemp) then
overflow <= '1';
end if;
if stuff(NUMBITS - 1) = '0' then
carryout <= '1';
else
carryout <= '0';
end if;
if stuff(NUMBITS - 1 downto 0) = 0 then
zero <= '1';
else
zero <= '0';
end if;
--SIGNED SUB
elsif opcode = "1101" then
stuff <= std_logic_vector( ('0' & signed(A) ) + ( '0' & ((not signed(B)) + 1)));
result <= stuff(NUMBITS-1 downto 0);
if (A(NUMBITS-1) = '0') and (B(NUMBITS-1) = '1') and (stuff(NUMBITS-2) = '1') then
overflow <= '1';
elsif (A(NUMBITS-1) = '1') and (B(NUMBITS-1) = '0') and (stuff(NUMBITS-2) = '0') then
overflow <= '1';
else
overflow <= '0';
end if;
carryout <= stuff(NUMBITS);
if stuff(NUMBITS - 1 downto 0) = 0 then
zero <= '1';
else
zero <= '0';
end if;
end if;
end process;
end Behavioral;
|
------------------------------------------------------------
-- Notes:
-- HOLD Clocked on FALLING EDGE
-- OUTPUT Clocked on rising EDGE
--
-- Revision:
-- 0.01 - File Created
-- 0.02 - Cleaned up Code given
-- 0.03 - Incorporated a enable switch
-- 0.04 - Have the register latch data on the falling
-- clock cycle.
-- 0.05 - Forked and added a input hold for the register
--
-- Additional Comments:
-- The register latches it's output data on the Rising edge
-- Hold latch on the falling edge
-- The main reason why I included a hold latch was to Prevent
-- Any register transfer faults that could occur.
-- Mostly acts as a safety buffer.
--
-----------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
ENTITY Reg24_LATCH IS
GENERIC(
DATA_WIDTH:INTEGER := 24
);
PORT(
Clock : IN STD_LOGIC;
Resetn : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
INPUT : IN STD_LOGIC_VECTOR(DATA_WIDTH-1 DOWNTO 0);
HOLD_OUT : OUT STD_LOGIC_VECTOR(DATA_WIDTH-1 DOWNTO 0);
OUTPUT : OUT STD_LOGIC_VECTOR(DATA_WIDTH-1 DOWNTO 0)
);
END Reg24_LATCH;
ARCHITECTURE Behavior OF Reg24_LATCH IS
SIGNAL HOLD : STD_LOGIC_VECTOR(DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
BEGIN
HOLD_OUT <= HOLD;
PROCESS(Resetn, Clock)
BEGIN
IF Resetn = '0' THEN
HOLD <= (OTHERS => '0');
OUTPUT <= (OTHERS => '0');
ELSE
IF (ENABLE = '1') AND Clock'EVENT THEN
IF Clock = '1' THEN
OUTPUT <= HOLD;
ELSE
HOLD <= INPUT;
END IF;
END IF;
END IF;
END PROCESS;
END Behavior;
|
function test_factor(input:std_logic_vector; value: integer; factor: integer) return boolean is
variable result: boolean := false;
begin
for f in 0 to factor loop
if(to_integer(unsigned(input)) = (f*value)/factor )then
result := true;
end if;
end loop;
return result;
end;
|
-- $Id: sys_tst_serloop1_n2.vhd 476 2013-01-26 22:23:53Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: sys_tst_serloop1_n2 - syn
-- Description: Tester serial link for nexys2
--
-- Dependencies: genlib/clkdivce
-- bpgen/bp_rs232_2l4l_iob
-- bpgen/sn_humanio
-- tst_serloop_hiomap
-- vlib/serport/serport_1clock
-- tst_serloop
-- vlib/nxcramlib/nx_cram_dummy
--
-- Test bench: -
--
-- Target Devices: generic
-- Tool versions: xst 13.1; ghdl 0.29
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2011-12-16 439 13.1 O40d xc3s1200e-4 433 634 64 490 t 13.1
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-12-23 444 1.1 remove clksys output hack
-- 2011-12-16 439 1.0 Initial version
------------------------------------------------------------------------------
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.xlib.all;
use work.genlib.all;
use work.bpgenlib.all;
use work.tst_serlooplib.all;
use work.serportlib.all;
use work.nxcramlib.all;
use work.sys_conf.all;
-- ----------------------------------------------------------------------------
entity sys_tst_serloop1_n2 is -- top level
-- implements nexys2_fusp_aif
port (
I_CLK50 : in slbit; -- 50 MHz clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
I_SWI : in slv8; -- n2 switches
I_BTN : in slv4; -- n2 buttons
O_LED : out slv8; -- n2 leds
O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low)
O_SEG_N : out slv8; -- 7 segment disp: segments (act.low)
O_MEM_CE_N : out slbit; -- cram: chip enable (act.low)
O_MEM_BE_N : out slv2; -- cram: byte enables (act.low)
O_MEM_WE_N : out slbit; -- cram: write enable (act.low)
O_MEM_OE_N : out slbit; -- cram: output enable (act.low)
O_MEM_ADV_N : out slbit; -- cram: address valid (act.low)
O_MEM_CLK : out slbit; -- cram: clock
O_MEM_CRE : out slbit; -- cram: command register enable
I_MEM_WAIT : in slbit; -- cram: mem wait
O_MEM_ADDR : out slv23; -- cram: address lines
IO_MEM_DATA : inout slv16; -- cram: data lines
O_FLA_CE_N : out slbit; -- flash ce.. (act.low)
O_FUSP_RTS_N : out slbit; -- fusp: rs232 rts_n
I_FUSP_CTS_N : in slbit; -- fusp: rs232 cts_n
I_FUSP_RXD : in slbit; -- fusp: rs232 rx
O_FUSP_TXD : out slbit -- fusp: rs232 tx
);
end sys_tst_serloop1_n2;
architecture syn of sys_tst_serloop1_n2 is
signal CLK : slbit := '0';
signal RESET : slbit := '0';
signal CE_USEC : slbit := '0';
signal CE_MSEC : slbit := '0';
signal RXD : slbit := '0';
signal TXD : slbit := '0';
signal CTS_N : slbit := '0';
signal RTS_N : slbit := '0';
signal SWI : slv8 := (others=>'0');
signal BTN : slv4 := (others=>'0');
signal LED : slv8 := (others=>'0');
signal DSP_DAT : slv16 := (others=>'0');
signal DSP_DP : slv4 := (others=>'0');
signal HIO_CNTL : hio_cntl_type := hio_cntl_init;
signal HIO_STAT : hio_stat_type := hio_stat_init;
signal RXDATA : slv8 := (others=>'0');
signal RXVAL : slbit := '0';
signal RXHOLD : slbit := '0';
signal TXDATA : slv8 := (others=>'0');
signal TXENA : slbit := '0';
signal TXBUSY : slbit := '0';
signal SER_MONI : serport_moni_type := serport_moni_init;
begin
CLK <= I_CLK50;
CLKDIV : clkdivce
generic map (
CDUWIDTH => 7,
USECDIV => sys_conf_clkdiv_usecdiv, -- syn: 100 sim: 20
MSECDIV => sys_conf_clkdiv_msecdiv) -- syn: 1000 sim: 5
port map (
CLK => CLK,
CE_USEC => open,
CE_MSEC => CE_MSEC
);
HIO : sn_humanio
generic map (
DEBOUNCE => sys_conf_hio_debounce)
port map (
CLK => CLK,
RESET => '0',
CE_MSEC => CE_MSEC,
SWI => SWI,
BTN => BTN,
LED => LED,
DSP_DAT => DSP_DAT,
DSP_DP => DSP_DP,
I_SWI => I_SWI,
I_BTN => I_BTN,
O_LED => O_LED,
O_ANO_N => O_ANO_N,
O_SEG_N => O_SEG_N
);
RESET <= BTN(0); -- BTN(0) will reset tester !!
HIOMAP : tst_serloop_hiomap
port map (
CLK => CLK,
RESET => RESET,
HIO_CNTL => HIO_CNTL,
HIO_STAT => HIO_STAT,
SER_MONI => SER_MONI,
SWI => SWI,
BTN => BTN,
LED => LED,
DSP_DAT => DSP_DAT,
DSP_DP => DSP_DP
);
IOB_RS232 : bp_rs232_2l4l_iob
port map (
CLK => CLK,
RESET => '0',
SEL => SWI(0), -- port selection
RXD => RXD,
TXD => TXD,
CTS_N => CTS_N,
RTS_N => RTS_N,
I_RXD0 => I_RXD,
O_TXD0 => O_TXD,
I_RXD1 => I_FUSP_RXD,
O_TXD1 => O_FUSP_TXD,
I_CTS1_N => I_FUSP_CTS_N,
O_RTS1_N => O_FUSP_RTS_N
);
SERPORT : serport_1clock
generic map (
CDWIDTH => 15,
CDINIT => sys_conf_uart_cdinit,
RXFAWIDTH => 5,
TXFAWIDTH => 5)
port map (
CLK => CLK,
CE_MSEC => CE_MSEC,
RESET => RESET,
ENAXON => HIO_CNTL.enaxon,
ENAESC => HIO_CNTL.enaesc,
RXDATA => RXDATA,
RXVAL => RXVAL,
RXHOLD => RXHOLD,
TXDATA => TXDATA,
TXENA => TXENA,
TXBUSY => TXBUSY,
MONI => SER_MONI,
RXSD => RXD,
TXSD => TXD,
RXRTS_N => RTS_N,
TXCTS_N => CTS_N
);
TESTER : tst_serloop
port map (
CLK => CLK,
RESET => RESET,
CE_MSEC => CE_MSEC,
HIO_CNTL => HIO_CNTL,
HIO_STAT => HIO_STAT,
SER_MONI => SER_MONI,
RXDATA => RXDATA,
RXVAL => RXVAL,
RXHOLD => RXHOLD,
TXDATA => TXDATA,
TXENA => TXENA,
TXBUSY => TXBUSY
);
SRAM_PROT : nx_cram_dummy -- connect CRAM to protection dummy
port map (
O_MEM_CE_N => O_MEM_CE_N,
O_MEM_BE_N => O_MEM_BE_N,
O_MEM_WE_N => O_MEM_WE_N,
O_MEM_OE_N => O_MEM_OE_N,
O_MEM_ADV_N => O_MEM_ADV_N,
O_MEM_CLK => O_MEM_CLK,
O_MEM_CRE => O_MEM_CRE,
I_MEM_WAIT => I_MEM_WAIT,
O_MEM_ADDR => O_MEM_ADDR,
IO_MEM_DATA => IO_MEM_DATA
);
O_FLA_CE_N <= '1'; -- keep Flash memory disabled
end syn;
|
library ieee;
use ieee.std_logic_1164.all;
entity Dummy is
end entity;
architecture arch of Dummy is
subtype t_null is std_logic_vector(-1 downto 0);
type array_of_nulls is array(1 downto 0) of t_null;
begin
end architecture;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 09/30/2016 02:38:42 PM
-- Design Name:
-- Module Name: W_Decoder - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Decoder is
Port (
i_w_Addr : in std_logic_vector(4 downto 0);
o_w_Addr : out std_logic_vector(31 downto 0)
);
end Decoder;
architecture Behavioral of Decoder is
begin
process(i_w_Addr)
begin
case i_w_Addr is
when "00000" =>
o_w_Addr <= "00000000000000000000000000000001";
when "00001" =>
o_w_Addr <= "00000000000000000000000000000010";
when "00010" =>
o_w_Addr <= "00000000000000000000000000000100";
when "00011" =>
o_w_Addr <= "00000000000000000000000000001000";
when "00100" =>
o_w_Addr <= "00000000000000000000000000010000";
when "00101" =>
o_w_Addr <= "00000000000000000000000000100000";
when "00110" =>
o_w_Addr <= "00000000000000000000000001000000";
when "00111" =>
o_w_Addr <= "00000000000000000000000010000000";
when "01000" =>
o_w_Addr <= "00000000000000000000000100000000";
when "01001" =>
o_w_Addr <= "00000000000000000000001000000000";
when "01010" =>
o_w_Addr <= "00000000000000000000010000000000";
when "01011" =>
o_w_Addr <= "00000000000000000000100000000000";
when "01100" =>
o_w_Addr <= "00000000000000000001000000000000";
when "01101" =>
o_w_Addr <= "00000000000000000010000000000000";
when "01110" =>
o_w_Addr <= "00000000000000000100000000000000";
when "01111" =>
o_w_Addr <= "00000000000000001000000000000000";
when "10000" =>
o_w_Addr <= "00000000000000010000000000000000";
when "10001" =>
o_w_Addr <= "00000000000000100000000000000000";
when "10010" =>
o_w_Addr <= "00000000000001000000000000000000";
when "10011" =>
o_w_Addr <= "00000000000010000000000000000000";
when "10100" =>
o_w_Addr <= "00000000000100000000000000000000";
when "10101" =>
o_w_Addr <= "00000000001000000000000000000000";
when "10110" =>
o_w_Addr <= "00000000010000000000000000000000";
when "10111" =>
o_w_Addr <= "00000000100000000000000000000000";
when "11000" =>
o_w_Addr <= "00000001000000000000000000000000";
when "11001" =>
o_w_Addr <= "00000010000000000000000000000000";
when "11010" =>
o_w_Addr <= "00000100000000000000000000000000";
when "11011" =>
o_w_Addr <= "00001000000000000000000000000000";
when "11100" =>
o_w_Addr <= "00010000000000000000000000000000";
when "11101" =>
o_w_Addr <= "00100000000000000000000000000000";
when "11110" =>
o_w_Addr <= "01000000000000000000000000000000";
when "11111" =>
o_w_Addr <= "10000000000000000000000000000000";
when others =>
o_w_Addr <= "00000000000000000000000000000000";
end case;
end process;
end Behavioral;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 09/30/2016 02:38:42 PM
-- Design Name:
-- Module Name: W_Decoder - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Decoder is
Port (
i_w_Addr : in std_logic_vector(4 downto 0);
o_w_Addr : out std_logic_vector(31 downto 0)
);
end Decoder;
architecture Behavioral of Decoder is
begin
process(i_w_Addr)
begin
case i_w_Addr is
when "00000" =>
o_w_Addr <= "00000000000000000000000000000001";
when "00001" =>
o_w_Addr <= "00000000000000000000000000000010";
when "00010" =>
o_w_Addr <= "00000000000000000000000000000100";
when "00011" =>
o_w_Addr <= "00000000000000000000000000001000";
when "00100" =>
o_w_Addr <= "00000000000000000000000000010000";
when "00101" =>
o_w_Addr <= "00000000000000000000000000100000";
when "00110" =>
o_w_Addr <= "00000000000000000000000001000000";
when "00111" =>
o_w_Addr <= "00000000000000000000000010000000";
when "01000" =>
o_w_Addr <= "00000000000000000000000100000000";
when "01001" =>
o_w_Addr <= "00000000000000000000001000000000";
when "01010" =>
o_w_Addr <= "00000000000000000000010000000000";
when "01011" =>
o_w_Addr <= "00000000000000000000100000000000";
when "01100" =>
o_w_Addr <= "00000000000000000001000000000000";
when "01101" =>
o_w_Addr <= "00000000000000000010000000000000";
when "01110" =>
o_w_Addr <= "00000000000000000100000000000000";
when "01111" =>
o_w_Addr <= "00000000000000001000000000000000";
when "10000" =>
o_w_Addr <= "00000000000000010000000000000000";
when "10001" =>
o_w_Addr <= "00000000000000100000000000000000";
when "10010" =>
o_w_Addr <= "00000000000001000000000000000000";
when "10011" =>
o_w_Addr <= "00000000000010000000000000000000";
when "10100" =>
o_w_Addr <= "00000000000100000000000000000000";
when "10101" =>
o_w_Addr <= "00000000001000000000000000000000";
when "10110" =>
o_w_Addr <= "00000000010000000000000000000000";
when "10111" =>
o_w_Addr <= "00000000100000000000000000000000";
when "11000" =>
o_w_Addr <= "00000001000000000000000000000000";
when "11001" =>
o_w_Addr <= "00000010000000000000000000000000";
when "11010" =>
o_w_Addr <= "00000100000000000000000000000000";
when "11011" =>
o_w_Addr <= "00001000000000000000000000000000";
when "11100" =>
o_w_Addr <= "00010000000000000000000000000000";
when "11101" =>
o_w_Addr <= "00100000000000000000000000000000";
when "11110" =>
o_w_Addr <= "01000000000000000000000000000000";
when "11111" =>
o_w_Addr <= "10000000000000000000000000000000";
when others =>
o_w_Addr <= "00000000000000000000000000000000";
end case;
end process;
end Behavioral;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity halfAdder is
Port (
A: in STD_LOGIC;
B: in STD_LOGIC;
Sum: out STD_LOGIC;
Cout: out STD_LOGIC;
);
end entity;
architecture HalfAdderBehavioral is
begin
Sum <= A xor B;
Cout <= A and B;
end HalfAdderBehavioral;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
library board;
use board.zpu_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
use board.zpuino_config.all;
use board.wishbonepkg.all;
entity zpuino_lsu is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_ack_i: in std_logic;
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_adr_o: out std_logic_vector(maxAddrBitIncIO downto 2);
wb_cyc_o: out std_logic;
wb_stb_o: out std_logic;
wb_sel_o: out std_logic_vector(3 downto 0);
wb_we_o: out std_logic;
-- Connection to cpu
req: in std_logic;
we: in std_logic;
busy: out std_logic;
data_read: out std_logic_vector(wordSize-1 downto 0);
data_write: in std_logic_vector(wordSize-1 downto 0);
data_sel: in std_logic_vector(3 downto 0);
address: in std_logic_vector(maxAddrBitIncIO downto 0)
);
end zpuino_lsu;
architecture behave of zpuino_lsu is
type lsu_state is (
lsu_idle,
lsu_read,
lsu_write
);
type regs is record
state: lsu_state;
addr: std_logic_vector(maxAddrBitIncIO downto 2);
sel: std_logic_vector(3 downto 0);
data: std_logic_vector(wordSize-1 downto 0);
end record;
signal r: regs;
begin
data_read <= wb_dat_i;
process(r,wb_clk_i, we, req, wb_ack_i, address, data_write, data_sel, wb_rst_i)
variable w: regs;
begin
w:=r;
wb_cyc_o <= '0';
wb_stb_o <= 'X';
wb_we_o <= 'X';
wb_adr_o <= r.addr;
wb_dat_o <= r.data;
wb_sel_o <= r.sel;
case r.state is
when lsu_idle =>
busy <= '0';
w.addr := address(maxAddrBitIncIO downto 2);
w.data := data_write;
w.sel := data_sel;
if req='1' then
if we='1' then
w.state := lsu_write;
busy <= address(maxAddrBitIncIO);
else
w.state := lsu_read;
busy <= '1';
end if;
end if;
when lsu_write =>
wb_cyc_o <= '1';
wb_stb_o <= '1';
wb_we_o <= '1';
if req='1' then
busy <= '1';
else
busy <= '0';
end if;
if wb_ack_i='1' then
w.state := lsu_idle;
if r.addr(maxAddrBitIncIO)='1' then
busy <= '0';
end if;
end if;
when lsu_read =>
wb_cyc_o <= '1';
wb_stb_o <= '1';
wb_we_o <= '0';
busy <= not wb_ack_i;
if wb_ack_i='1' then
w.state := lsu_idle;
end if;
when others =>
end case;
if wb_rst_i='1' then
w.state := lsu_idle;
wb_cyc_o <= '0';
end if;
if rising_edge(wb_clk_i) then
r <= w;
end if;
end process;
end behave;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
library board;
use board.zpu_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
use board.zpuino_config.all;
use board.wishbonepkg.all;
entity zpuino_lsu is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_ack_i: in std_logic;
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_adr_o: out std_logic_vector(maxAddrBitIncIO downto 2);
wb_cyc_o: out std_logic;
wb_stb_o: out std_logic;
wb_sel_o: out std_logic_vector(3 downto 0);
wb_we_o: out std_logic;
-- Connection to cpu
req: in std_logic;
we: in std_logic;
busy: out std_logic;
data_read: out std_logic_vector(wordSize-1 downto 0);
data_write: in std_logic_vector(wordSize-1 downto 0);
data_sel: in std_logic_vector(3 downto 0);
address: in std_logic_vector(maxAddrBitIncIO downto 0)
);
end zpuino_lsu;
architecture behave of zpuino_lsu is
type lsu_state is (
lsu_idle,
lsu_read,
lsu_write
);
type regs is record
state: lsu_state;
addr: std_logic_vector(maxAddrBitIncIO downto 2);
sel: std_logic_vector(3 downto 0);
data: std_logic_vector(wordSize-1 downto 0);
end record;
signal r: regs;
begin
data_read <= wb_dat_i;
process(r,wb_clk_i, we, req, wb_ack_i, address, data_write, data_sel, wb_rst_i)
variable w: regs;
begin
w:=r;
wb_cyc_o <= '0';
wb_stb_o <= 'X';
wb_we_o <= 'X';
wb_adr_o <= r.addr;
wb_dat_o <= r.data;
wb_sel_o <= r.sel;
case r.state is
when lsu_idle =>
busy <= '0';
w.addr := address(maxAddrBitIncIO downto 2);
w.data := data_write;
w.sel := data_sel;
if req='1' then
if we='1' then
w.state := lsu_write;
busy <= address(maxAddrBitIncIO);
else
w.state := lsu_read;
busy <= '1';
end if;
end if;
when lsu_write =>
wb_cyc_o <= '1';
wb_stb_o <= '1';
wb_we_o <= '1';
if req='1' then
busy <= '1';
else
busy <= '0';
end if;
if wb_ack_i='1' then
w.state := lsu_idle;
if r.addr(maxAddrBitIncIO)='1' then
busy <= '0';
end if;
end if;
when lsu_read =>
wb_cyc_o <= '1';
wb_stb_o <= '1';
wb_we_o <= '0';
busy <= not wb_ack_i;
if wb_ack_i='1' then
w.state := lsu_idle;
end if;
when others =>
end case;
if wb_rst_i='1' then
w.state := lsu_idle;
wb_cyc_o <= '0';
end if;
if rising_edge(wb_clk_i) then
r <= w;
end if;
end process;
end behave;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
library board;
use board.zpu_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
use board.zpuino_config.all;
use board.wishbonepkg.all;
entity zpuino_lsu is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_ack_i: in std_logic;
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_adr_o: out std_logic_vector(maxAddrBitIncIO downto 2);
wb_cyc_o: out std_logic;
wb_stb_o: out std_logic;
wb_sel_o: out std_logic_vector(3 downto 0);
wb_we_o: out std_logic;
-- Connection to cpu
req: in std_logic;
we: in std_logic;
busy: out std_logic;
data_read: out std_logic_vector(wordSize-1 downto 0);
data_write: in std_logic_vector(wordSize-1 downto 0);
data_sel: in std_logic_vector(3 downto 0);
address: in std_logic_vector(maxAddrBitIncIO downto 0)
);
end zpuino_lsu;
architecture behave of zpuino_lsu is
type lsu_state is (
lsu_idle,
lsu_read,
lsu_write
);
type regs is record
state: lsu_state;
addr: std_logic_vector(maxAddrBitIncIO downto 2);
sel: std_logic_vector(3 downto 0);
data: std_logic_vector(wordSize-1 downto 0);
end record;
signal r: regs;
begin
data_read <= wb_dat_i;
process(r,wb_clk_i, we, req, wb_ack_i, address, data_write, data_sel, wb_rst_i)
variable w: regs;
begin
w:=r;
wb_cyc_o <= '0';
wb_stb_o <= 'X';
wb_we_o <= 'X';
wb_adr_o <= r.addr;
wb_dat_o <= r.data;
wb_sel_o <= r.sel;
case r.state is
when lsu_idle =>
busy <= '0';
w.addr := address(maxAddrBitIncIO downto 2);
w.data := data_write;
w.sel := data_sel;
if req='1' then
if we='1' then
w.state := lsu_write;
busy <= address(maxAddrBitIncIO);
else
w.state := lsu_read;
busy <= '1';
end if;
end if;
when lsu_write =>
wb_cyc_o <= '1';
wb_stb_o <= '1';
wb_we_o <= '1';
if req='1' then
busy <= '1';
else
busy <= '0';
end if;
if wb_ack_i='1' then
w.state := lsu_idle;
if r.addr(maxAddrBitIncIO)='1' then
busy <= '0';
end if;
end if;
when lsu_read =>
wb_cyc_o <= '1';
wb_stb_o <= '1';
wb_we_o <= '0';
busy <= not wb_ack_i;
if wb_ack_i='1' then
w.state := lsu_idle;
end if;
when others =>
end case;
if wb_rst_i='1' then
w.state := lsu_idle;
wb_cyc_o <= '0';
end if;
if rising_edge(wb_clk_i) then
r <= w;
end if;
end process;
end behave;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
library board;
use board.zpu_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
use board.zpuino_config.all;
use board.wishbonepkg.all;
entity zpuino_lsu is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_ack_i: in std_logic;
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_adr_o: out std_logic_vector(maxAddrBitIncIO downto 2);
wb_cyc_o: out std_logic;
wb_stb_o: out std_logic;
wb_sel_o: out std_logic_vector(3 downto 0);
wb_we_o: out std_logic;
-- Connection to cpu
req: in std_logic;
we: in std_logic;
busy: out std_logic;
data_read: out std_logic_vector(wordSize-1 downto 0);
data_write: in std_logic_vector(wordSize-1 downto 0);
data_sel: in std_logic_vector(3 downto 0);
address: in std_logic_vector(maxAddrBitIncIO downto 0)
);
end zpuino_lsu;
architecture behave of zpuino_lsu is
type lsu_state is (
lsu_idle,
lsu_read,
lsu_write
);
type regs is record
state: lsu_state;
addr: std_logic_vector(maxAddrBitIncIO downto 2);
sel: std_logic_vector(3 downto 0);
data: std_logic_vector(wordSize-1 downto 0);
end record;
signal r: regs;
begin
data_read <= wb_dat_i;
process(r,wb_clk_i, we, req, wb_ack_i, address, data_write, data_sel, wb_rst_i)
variable w: regs;
begin
w:=r;
wb_cyc_o <= '0';
wb_stb_o <= 'X';
wb_we_o <= 'X';
wb_adr_o <= r.addr;
wb_dat_o <= r.data;
wb_sel_o <= r.sel;
case r.state is
when lsu_idle =>
busy <= '0';
w.addr := address(maxAddrBitIncIO downto 2);
w.data := data_write;
w.sel := data_sel;
if req='1' then
if we='1' then
w.state := lsu_write;
busy <= address(maxAddrBitIncIO);
else
w.state := lsu_read;
busy <= '1';
end if;
end if;
when lsu_write =>
wb_cyc_o <= '1';
wb_stb_o <= '1';
wb_we_o <= '1';
if req='1' then
busy <= '1';
else
busy <= '0';
end if;
if wb_ack_i='1' then
w.state := lsu_idle;
if r.addr(maxAddrBitIncIO)='1' then
busy <= '0';
end if;
end if;
when lsu_read =>
wb_cyc_o <= '1';
wb_stb_o <= '1';
wb_we_o <= '0';
busy <= not wb_ack_i;
if wb_ack_i='1' then
w.state := lsu_idle;
end if;
when others =>
end case;
if wb_rst_i='1' then
w.state := lsu_idle;
wb_cyc_o <= '0';
end if;
if rising_edge(wb_clk_i) then
r <= w;
end if;
end process;
end behave;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
library board;
use board.zpu_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
use board.zpuino_config.all;
use board.wishbonepkg.all;
entity zpuino_lsu is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_ack_i: in std_logic;
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_adr_o: out std_logic_vector(maxAddrBitIncIO downto 2);
wb_cyc_o: out std_logic;
wb_stb_o: out std_logic;
wb_sel_o: out std_logic_vector(3 downto 0);
wb_we_o: out std_logic;
-- Connection to cpu
req: in std_logic;
we: in std_logic;
busy: out std_logic;
data_read: out std_logic_vector(wordSize-1 downto 0);
data_write: in std_logic_vector(wordSize-1 downto 0);
data_sel: in std_logic_vector(3 downto 0);
address: in std_logic_vector(maxAddrBitIncIO downto 0)
);
end zpuino_lsu;
architecture behave of zpuino_lsu is
type lsu_state is (
lsu_idle,
lsu_read,
lsu_write
);
type regs is record
state: lsu_state;
addr: std_logic_vector(maxAddrBitIncIO downto 2);
sel: std_logic_vector(3 downto 0);
data: std_logic_vector(wordSize-1 downto 0);
end record;
signal r: regs;
begin
data_read <= wb_dat_i;
process(r,wb_clk_i, we, req, wb_ack_i, address, data_write, data_sel, wb_rst_i)
variable w: regs;
begin
w:=r;
wb_cyc_o <= '0';
wb_stb_o <= 'X';
wb_we_o <= 'X';
wb_adr_o <= r.addr;
wb_dat_o <= r.data;
wb_sel_o <= r.sel;
case r.state is
when lsu_idle =>
busy <= '0';
w.addr := address(maxAddrBitIncIO downto 2);
w.data := data_write;
w.sel := data_sel;
if req='1' then
if we='1' then
w.state := lsu_write;
busy <= address(maxAddrBitIncIO);
else
w.state := lsu_read;
busy <= '1';
end if;
end if;
when lsu_write =>
wb_cyc_o <= '1';
wb_stb_o <= '1';
wb_we_o <= '1';
if req='1' then
busy <= '1';
else
busy <= '0';
end if;
if wb_ack_i='1' then
w.state := lsu_idle;
if r.addr(maxAddrBitIncIO)='1' then
busy <= '0';
end if;
end if;
when lsu_read =>
wb_cyc_o <= '1';
wb_stb_o <= '1';
wb_we_o <= '0';
busy <= not wb_ack_i;
if wb_ack_i='1' then
w.state := lsu_idle;
end if;
when others =>
end case;
if wb_rst_i='1' then
w.state := lsu_idle;
wb_cyc_o <= '0';
end if;
if rising_edge(wb_clk_i) then
r <= w;
end if;
end process;
end behave;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
library board;
use board.zpu_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
use board.zpuino_config.all;
use board.wishbonepkg.all;
entity zpuino_lsu is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_ack_i: in std_logic;
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_adr_o: out std_logic_vector(maxAddrBitIncIO downto 2);
wb_cyc_o: out std_logic;
wb_stb_o: out std_logic;
wb_sel_o: out std_logic_vector(3 downto 0);
wb_we_o: out std_logic;
-- Connection to cpu
req: in std_logic;
we: in std_logic;
busy: out std_logic;
data_read: out std_logic_vector(wordSize-1 downto 0);
data_write: in std_logic_vector(wordSize-1 downto 0);
data_sel: in std_logic_vector(3 downto 0);
address: in std_logic_vector(maxAddrBitIncIO downto 0)
);
end zpuino_lsu;
architecture behave of zpuino_lsu is
type lsu_state is (
lsu_idle,
lsu_read,
lsu_write
);
type regs is record
state: lsu_state;
addr: std_logic_vector(maxAddrBitIncIO downto 2);
sel: std_logic_vector(3 downto 0);
data: std_logic_vector(wordSize-1 downto 0);
end record;
signal r: regs;
begin
data_read <= wb_dat_i;
process(r,wb_clk_i, we, req, wb_ack_i, address, data_write, data_sel, wb_rst_i)
variable w: regs;
begin
w:=r;
wb_cyc_o <= '0';
wb_stb_o <= 'X';
wb_we_o <= 'X';
wb_adr_o <= r.addr;
wb_dat_o <= r.data;
wb_sel_o <= r.sel;
case r.state is
when lsu_idle =>
busy <= '0';
w.addr := address(maxAddrBitIncIO downto 2);
w.data := data_write;
w.sel := data_sel;
if req='1' then
if we='1' then
w.state := lsu_write;
busy <= address(maxAddrBitIncIO);
else
w.state := lsu_read;
busy <= '1';
end if;
end if;
when lsu_write =>
wb_cyc_o <= '1';
wb_stb_o <= '1';
wb_we_o <= '1';
if req='1' then
busy <= '1';
else
busy <= '0';
end if;
if wb_ack_i='1' then
w.state := lsu_idle;
if r.addr(maxAddrBitIncIO)='1' then
busy <= '0';
end if;
end if;
when lsu_read =>
wb_cyc_o <= '1';
wb_stb_o <= '1';
wb_we_o <= '0';
busy <= not wb_ack_i;
if wb_ack_i='1' then
w.state := lsu_idle;
end if;
when others =>
end case;
if wb_rst_i='1' then
w.state := lsu_idle;
wb_cyc_o <= '0';
end if;
if rising_edge(wb_clk_i) then
r <= w;
end if;
end process;
end behave;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
library board;
use board.zpu_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
use board.zpuino_config.all;
use board.wishbonepkg.all;
entity zpuino_lsu is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_ack_i: in std_logic;
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_adr_o: out std_logic_vector(maxAddrBitIncIO downto 2);
wb_cyc_o: out std_logic;
wb_stb_o: out std_logic;
wb_sel_o: out std_logic_vector(3 downto 0);
wb_we_o: out std_logic;
-- Connection to cpu
req: in std_logic;
we: in std_logic;
busy: out std_logic;
data_read: out std_logic_vector(wordSize-1 downto 0);
data_write: in std_logic_vector(wordSize-1 downto 0);
data_sel: in std_logic_vector(3 downto 0);
address: in std_logic_vector(maxAddrBitIncIO downto 0)
);
end zpuino_lsu;
architecture behave of zpuino_lsu is
type lsu_state is (
lsu_idle,
lsu_read,
lsu_write
);
type regs is record
state: lsu_state;
addr: std_logic_vector(maxAddrBitIncIO downto 2);
sel: std_logic_vector(3 downto 0);
data: std_logic_vector(wordSize-1 downto 0);
end record;
signal r: regs;
begin
data_read <= wb_dat_i;
process(r,wb_clk_i, we, req, wb_ack_i, address, data_write, data_sel, wb_rst_i)
variable w: regs;
begin
w:=r;
wb_cyc_o <= '0';
wb_stb_o <= 'X';
wb_we_o <= 'X';
wb_adr_o <= r.addr;
wb_dat_o <= r.data;
wb_sel_o <= r.sel;
case r.state is
when lsu_idle =>
busy <= '0';
w.addr := address(maxAddrBitIncIO downto 2);
w.data := data_write;
w.sel := data_sel;
if req='1' then
if we='1' then
w.state := lsu_write;
busy <= address(maxAddrBitIncIO);
else
w.state := lsu_read;
busy <= '1';
end if;
end if;
when lsu_write =>
wb_cyc_o <= '1';
wb_stb_o <= '1';
wb_we_o <= '1';
if req='1' then
busy <= '1';
else
busy <= '0';
end if;
if wb_ack_i='1' then
w.state := lsu_idle;
if r.addr(maxAddrBitIncIO)='1' then
busy <= '0';
end if;
end if;
when lsu_read =>
wb_cyc_o <= '1';
wb_stb_o <= '1';
wb_we_o <= '0';
busy <= not wb_ack_i;
if wb_ack_i='1' then
w.state := lsu_idle;
end if;
when others =>
end case;
if wb_rst_i='1' then
w.state := lsu_idle;
wb_cyc_o <= '0';
end if;
if rising_edge(wb_clk_i) then
r <= w;
end if;
end process;
end behave;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
library board;
use board.zpu_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
use board.zpuino_config.all;
use board.wishbonepkg.all;
entity zpuino_lsu is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_ack_i: in std_logic;
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_adr_o: out std_logic_vector(maxAddrBitIncIO downto 2);
wb_cyc_o: out std_logic;
wb_stb_o: out std_logic;
wb_sel_o: out std_logic_vector(3 downto 0);
wb_we_o: out std_logic;
-- Connection to cpu
req: in std_logic;
we: in std_logic;
busy: out std_logic;
data_read: out std_logic_vector(wordSize-1 downto 0);
data_write: in std_logic_vector(wordSize-1 downto 0);
data_sel: in std_logic_vector(3 downto 0);
address: in std_logic_vector(maxAddrBitIncIO downto 0)
);
end zpuino_lsu;
architecture behave of zpuino_lsu is
type lsu_state is (
lsu_idle,
lsu_read,
lsu_write
);
type regs is record
state: lsu_state;
addr: std_logic_vector(maxAddrBitIncIO downto 2);
sel: std_logic_vector(3 downto 0);
data: std_logic_vector(wordSize-1 downto 0);
end record;
signal r: regs;
begin
data_read <= wb_dat_i;
process(r,wb_clk_i, we, req, wb_ack_i, address, data_write, data_sel, wb_rst_i)
variable w: regs;
begin
w:=r;
wb_cyc_o <= '0';
wb_stb_o <= 'X';
wb_we_o <= 'X';
wb_adr_o <= r.addr;
wb_dat_o <= r.data;
wb_sel_o <= r.sel;
case r.state is
when lsu_idle =>
busy <= '0';
w.addr := address(maxAddrBitIncIO downto 2);
w.data := data_write;
w.sel := data_sel;
if req='1' then
if we='1' then
w.state := lsu_write;
busy <= address(maxAddrBitIncIO);
else
w.state := lsu_read;
busy <= '1';
end if;
end if;
when lsu_write =>
wb_cyc_o <= '1';
wb_stb_o <= '1';
wb_we_o <= '1';
if req='1' then
busy <= '1';
else
busy <= '0';
end if;
if wb_ack_i='1' then
w.state := lsu_idle;
if r.addr(maxAddrBitIncIO)='1' then
busy <= '0';
end if;
end if;
when lsu_read =>
wb_cyc_o <= '1';
wb_stb_o <= '1';
wb_we_o <= '0';
busy <= not wb_ack_i;
if wb_ack_i='1' then
w.state := lsu_idle;
end if;
when others =>
end case;
if wb_rst_i='1' then
w.state := lsu_idle;
wb_cyc_o <= '0';
end if;
if rising_edge(wb_clk_i) then
r <= w;
end if;
end process;
end behave;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
library board;
use board.zpu_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
use board.zpuino_config.all;
use board.wishbonepkg.all;
entity zpuino_lsu is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_ack_i: in std_logic;
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_adr_o: out std_logic_vector(maxAddrBitIncIO downto 2);
wb_cyc_o: out std_logic;
wb_stb_o: out std_logic;
wb_sel_o: out std_logic_vector(3 downto 0);
wb_we_o: out std_logic;
-- Connection to cpu
req: in std_logic;
we: in std_logic;
busy: out std_logic;
data_read: out std_logic_vector(wordSize-1 downto 0);
data_write: in std_logic_vector(wordSize-1 downto 0);
data_sel: in std_logic_vector(3 downto 0);
address: in std_logic_vector(maxAddrBitIncIO downto 0)
);
end zpuino_lsu;
architecture behave of zpuino_lsu is
type lsu_state is (
lsu_idle,
lsu_read,
lsu_write
);
type regs is record
state: lsu_state;
addr: std_logic_vector(maxAddrBitIncIO downto 2);
sel: std_logic_vector(3 downto 0);
data: std_logic_vector(wordSize-1 downto 0);
end record;
signal r: regs;
begin
data_read <= wb_dat_i;
process(r,wb_clk_i, we, req, wb_ack_i, address, data_write, data_sel, wb_rst_i)
variable w: regs;
begin
w:=r;
wb_cyc_o <= '0';
wb_stb_o <= 'X';
wb_we_o <= 'X';
wb_adr_o <= r.addr;
wb_dat_o <= r.data;
wb_sel_o <= r.sel;
case r.state is
when lsu_idle =>
busy <= '0';
w.addr := address(maxAddrBitIncIO downto 2);
w.data := data_write;
w.sel := data_sel;
if req='1' then
if we='1' then
w.state := lsu_write;
busy <= address(maxAddrBitIncIO);
else
w.state := lsu_read;
busy <= '1';
end if;
end if;
when lsu_write =>
wb_cyc_o <= '1';
wb_stb_o <= '1';
wb_we_o <= '1';
if req='1' then
busy <= '1';
else
busy <= '0';
end if;
if wb_ack_i='1' then
w.state := lsu_idle;
if r.addr(maxAddrBitIncIO)='1' then
busy <= '0';
end if;
end if;
when lsu_read =>
wb_cyc_o <= '1';
wb_stb_o <= '1';
wb_we_o <= '0';
busy <= not wb_ack_i;
if wb_ack_i='1' then
w.state := lsu_idle;
end if;
when others =>
end case;
if wb_rst_i='1' then
w.state := lsu_idle;
wb_cyc_o <= '0';
end if;
if rising_edge(wb_clk_i) then
r <= w;
end if;
end process;
end behave;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
library board;
use board.zpu_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
use board.zpuino_config.all;
use board.wishbonepkg.all;
entity zpuino_lsu is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_ack_i: in std_logic;
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_adr_o: out std_logic_vector(maxAddrBitIncIO downto 2);
wb_cyc_o: out std_logic;
wb_stb_o: out std_logic;
wb_sel_o: out std_logic_vector(3 downto 0);
wb_we_o: out std_logic;
-- Connection to cpu
req: in std_logic;
we: in std_logic;
busy: out std_logic;
data_read: out std_logic_vector(wordSize-1 downto 0);
data_write: in std_logic_vector(wordSize-1 downto 0);
data_sel: in std_logic_vector(3 downto 0);
address: in std_logic_vector(maxAddrBitIncIO downto 0)
);
end zpuino_lsu;
architecture behave of zpuino_lsu is
type lsu_state is (
lsu_idle,
lsu_read,
lsu_write
);
type regs is record
state: lsu_state;
addr: std_logic_vector(maxAddrBitIncIO downto 2);
sel: std_logic_vector(3 downto 0);
data: std_logic_vector(wordSize-1 downto 0);
end record;
signal r: regs;
begin
data_read <= wb_dat_i;
process(r,wb_clk_i, we, req, wb_ack_i, address, data_write, data_sel, wb_rst_i)
variable w: regs;
begin
w:=r;
wb_cyc_o <= '0';
wb_stb_o <= 'X';
wb_we_o <= 'X';
wb_adr_o <= r.addr;
wb_dat_o <= r.data;
wb_sel_o <= r.sel;
case r.state is
when lsu_idle =>
busy <= '0';
w.addr := address(maxAddrBitIncIO downto 2);
w.data := data_write;
w.sel := data_sel;
if req='1' then
if we='1' then
w.state := lsu_write;
busy <= address(maxAddrBitIncIO);
else
w.state := lsu_read;
busy <= '1';
end if;
end if;
when lsu_write =>
wb_cyc_o <= '1';
wb_stb_o <= '1';
wb_we_o <= '1';
if req='1' then
busy <= '1';
else
busy <= '0';
end if;
if wb_ack_i='1' then
w.state := lsu_idle;
if r.addr(maxAddrBitIncIO)='1' then
busy <= '0';
end if;
end if;
when lsu_read =>
wb_cyc_o <= '1';
wb_stb_o <= '1';
wb_we_o <= '0';
busy <= not wb_ack_i;
if wb_ack_i='1' then
w.state := lsu_idle;
end if;
when others =>
end case;
if wb_rst_i='1' then
w.state := lsu_idle;
wb_cyc_o <= '0';
end if;
if rising_edge(wb_clk_i) then
r <= w;
end if;
end process;
end behave;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
library board;
use board.zpu_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
use board.zpuino_config.all;
use board.wishbonepkg.all;
entity zpuino_lsu is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_ack_i: in std_logic;
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_adr_o: out std_logic_vector(maxAddrBitIncIO downto 2);
wb_cyc_o: out std_logic;
wb_stb_o: out std_logic;
wb_sel_o: out std_logic_vector(3 downto 0);
wb_we_o: out std_logic;
-- Connection to cpu
req: in std_logic;
we: in std_logic;
busy: out std_logic;
data_read: out std_logic_vector(wordSize-1 downto 0);
data_write: in std_logic_vector(wordSize-1 downto 0);
data_sel: in std_logic_vector(3 downto 0);
address: in std_logic_vector(maxAddrBitIncIO downto 0)
);
end zpuino_lsu;
architecture behave of zpuino_lsu is
type lsu_state is (
lsu_idle,
lsu_read,
lsu_write
);
type regs is record
state: lsu_state;
addr: std_logic_vector(maxAddrBitIncIO downto 2);
sel: std_logic_vector(3 downto 0);
data: std_logic_vector(wordSize-1 downto 0);
end record;
signal r: regs;
begin
data_read <= wb_dat_i;
process(r,wb_clk_i, we, req, wb_ack_i, address, data_write, data_sel, wb_rst_i)
variable w: regs;
begin
w:=r;
wb_cyc_o <= '0';
wb_stb_o <= 'X';
wb_we_o <= 'X';
wb_adr_o <= r.addr;
wb_dat_o <= r.data;
wb_sel_o <= r.sel;
case r.state is
when lsu_idle =>
busy <= '0';
w.addr := address(maxAddrBitIncIO downto 2);
w.data := data_write;
w.sel := data_sel;
if req='1' then
if we='1' then
w.state := lsu_write;
busy <= address(maxAddrBitIncIO);
else
w.state := lsu_read;
busy <= '1';
end if;
end if;
when lsu_write =>
wb_cyc_o <= '1';
wb_stb_o <= '1';
wb_we_o <= '1';
if req='1' then
busy <= '1';
else
busy <= '0';
end if;
if wb_ack_i='1' then
w.state := lsu_idle;
if r.addr(maxAddrBitIncIO)='1' then
busy <= '0';
end if;
end if;
when lsu_read =>
wb_cyc_o <= '1';
wb_stb_o <= '1';
wb_we_o <= '0';
busy <= not wb_ack_i;
if wb_ack_i='1' then
w.state := lsu_idle;
end if;
when others =>
end case;
if wb_rst_i='1' then
w.state := lsu_idle;
wb_cyc_o <= '0';
end if;
if rising_edge(wb_clk_i) then
r <= w;
end if;
end process;
end behave;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
library board;
use board.zpu_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
use board.zpuino_config.all;
use board.wishbonepkg.all;
entity zpuino_lsu is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_ack_i: in std_logic;
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_adr_o: out std_logic_vector(maxAddrBitIncIO downto 2);
wb_cyc_o: out std_logic;
wb_stb_o: out std_logic;
wb_sel_o: out std_logic_vector(3 downto 0);
wb_we_o: out std_logic;
-- Connection to cpu
req: in std_logic;
we: in std_logic;
busy: out std_logic;
data_read: out std_logic_vector(wordSize-1 downto 0);
data_write: in std_logic_vector(wordSize-1 downto 0);
data_sel: in std_logic_vector(3 downto 0);
address: in std_logic_vector(maxAddrBitIncIO downto 0)
);
end zpuino_lsu;
architecture behave of zpuino_lsu is
type lsu_state is (
lsu_idle,
lsu_read,
lsu_write
);
type regs is record
state: lsu_state;
addr: std_logic_vector(maxAddrBitIncIO downto 2);
sel: std_logic_vector(3 downto 0);
data: std_logic_vector(wordSize-1 downto 0);
end record;
signal r: regs;
begin
data_read <= wb_dat_i;
process(r,wb_clk_i, we, req, wb_ack_i, address, data_write, data_sel, wb_rst_i)
variable w: regs;
begin
w:=r;
wb_cyc_o <= '0';
wb_stb_o <= 'X';
wb_we_o <= 'X';
wb_adr_o <= r.addr;
wb_dat_o <= r.data;
wb_sel_o <= r.sel;
case r.state is
when lsu_idle =>
busy <= '0';
w.addr := address(maxAddrBitIncIO downto 2);
w.data := data_write;
w.sel := data_sel;
if req='1' then
if we='1' then
w.state := lsu_write;
busy <= address(maxAddrBitIncIO);
else
w.state := lsu_read;
busy <= '1';
end if;
end if;
when lsu_write =>
wb_cyc_o <= '1';
wb_stb_o <= '1';
wb_we_o <= '1';
if req='1' then
busy <= '1';
else
busy <= '0';
end if;
if wb_ack_i='1' then
w.state := lsu_idle;
if r.addr(maxAddrBitIncIO)='1' then
busy <= '0';
end if;
end if;
when lsu_read =>
wb_cyc_o <= '1';
wb_stb_o <= '1';
wb_we_o <= '0';
busy <= not wb_ack_i;
if wb_ack_i='1' then
w.state := lsu_idle;
end if;
when others =>
end case;
if wb_rst_i='1' then
w.state := lsu_idle;
wb_cyc_o <= '0';
end if;
if rising_edge(wb_clk_i) then
r <= w;
end if;
end process;
end behave;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
library board;
use board.zpu_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
use board.zpuino_config.all;
use board.wishbonepkg.all;
entity zpuino_lsu is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_ack_i: in std_logic;
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_adr_o: out std_logic_vector(maxAddrBitIncIO downto 2);
wb_cyc_o: out std_logic;
wb_stb_o: out std_logic;
wb_sel_o: out std_logic_vector(3 downto 0);
wb_we_o: out std_logic;
-- Connection to cpu
req: in std_logic;
we: in std_logic;
busy: out std_logic;
data_read: out std_logic_vector(wordSize-1 downto 0);
data_write: in std_logic_vector(wordSize-1 downto 0);
data_sel: in std_logic_vector(3 downto 0);
address: in std_logic_vector(maxAddrBitIncIO downto 0)
);
end zpuino_lsu;
architecture behave of zpuino_lsu is
type lsu_state is (
lsu_idle,
lsu_read,
lsu_write
);
type regs is record
state: lsu_state;
addr: std_logic_vector(maxAddrBitIncIO downto 2);
sel: std_logic_vector(3 downto 0);
data: std_logic_vector(wordSize-1 downto 0);
end record;
signal r: regs;
begin
data_read <= wb_dat_i;
process(r,wb_clk_i, we, req, wb_ack_i, address, data_write, data_sel, wb_rst_i)
variable w: regs;
begin
w:=r;
wb_cyc_o <= '0';
wb_stb_o <= 'X';
wb_we_o <= 'X';
wb_adr_o <= r.addr;
wb_dat_o <= r.data;
wb_sel_o <= r.sel;
case r.state is
when lsu_idle =>
busy <= '0';
w.addr := address(maxAddrBitIncIO downto 2);
w.data := data_write;
w.sel := data_sel;
if req='1' then
if we='1' then
w.state := lsu_write;
busy <= address(maxAddrBitIncIO);
else
w.state := lsu_read;
busy <= '1';
end if;
end if;
when lsu_write =>
wb_cyc_o <= '1';
wb_stb_o <= '1';
wb_we_o <= '1';
if req='1' then
busy <= '1';
else
busy <= '0';
end if;
if wb_ack_i='1' then
w.state := lsu_idle;
if r.addr(maxAddrBitIncIO)='1' then
busy <= '0';
end if;
end if;
when lsu_read =>
wb_cyc_o <= '1';
wb_stb_o <= '1';
wb_we_o <= '0';
busy <= not wb_ack_i;
if wb_ack_i='1' then
w.state := lsu_idle;
end if;
when others =>
end case;
if wb_rst_i='1' then
w.state := lsu_idle;
wb_cyc_o <= '0';
end if;
if rising_edge(wb_clk_i) then
r <= w;
end if;
end process;
end behave;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2024.vhd,v 1.2 2001-10-26 16:30:15 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b04x00p01n01i02024ent IS
END c07s02b04x00p01n01i02024ent;
ARCHITECTURE c07s02b04x00p01n01i02024arch OF c07s02b04x00p01n01i02024ent IS
BEGIN
TESTING: PROCESS
type SWITCH_LEVEL is ('0', '1', 'X');
variable SWITCHV : SWITCH_LEVEL := '0';
subtype LOGIC_SWITCH is SWITCH_LEVEL range '0' to '1';
variable LOGICV : LOGIC_SWITCH := '0';
BEGIN
LOGICV := LOGICV + SWITCHV;
assert FALSE
report "***FAILED TEST: c07s02b04x00p01n01i02024 - The adding operators + and - are predefined for any numeric type."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b04x00p01n01i02024arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2024.vhd,v 1.2 2001-10-26 16:30:15 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b04x00p01n01i02024ent IS
END c07s02b04x00p01n01i02024ent;
ARCHITECTURE c07s02b04x00p01n01i02024arch OF c07s02b04x00p01n01i02024ent IS
BEGIN
TESTING: PROCESS
type SWITCH_LEVEL is ('0', '1', 'X');
variable SWITCHV : SWITCH_LEVEL := '0';
subtype LOGIC_SWITCH is SWITCH_LEVEL range '0' to '1';
variable LOGICV : LOGIC_SWITCH := '0';
BEGIN
LOGICV := LOGICV + SWITCHV;
assert FALSE
report "***FAILED TEST: c07s02b04x00p01n01i02024 - The adding operators + and - are predefined for any numeric type."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b04x00p01n01i02024arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2024.vhd,v 1.2 2001-10-26 16:30:15 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b04x00p01n01i02024ent IS
END c07s02b04x00p01n01i02024ent;
ARCHITECTURE c07s02b04x00p01n01i02024arch OF c07s02b04x00p01n01i02024ent IS
BEGIN
TESTING: PROCESS
type SWITCH_LEVEL is ('0', '1', 'X');
variable SWITCHV : SWITCH_LEVEL := '0';
subtype LOGIC_SWITCH is SWITCH_LEVEL range '0' to '1';
variable LOGICV : LOGIC_SWITCH := '0';
BEGIN
LOGICV := LOGICV + SWITCHV;
assert FALSE
report "***FAILED TEST: c07s02b04x00p01n01i02024 - The adding operators + and - are predefined for any numeric type."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b04x00p01n01i02024arch;
|
library ieee;
use ieee.math_real.all;
entity ent is
end ent;
architecture a of ent is
constant sin_val : real := sin(1.0);
begin
end a;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc58.vhd,v 1.2 2001-10-26 16:30:26 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s03b01x01p05n01i00058ent IS
END c04s03b01x01p05n01i00058ent;
ARCHITECTURE c04s03b01x01p05n01i00058arch OF c04s03b01x01p05n01i00058ent IS
BEGIN
TESTING : PROCESS
BEGIN
T1 := 20 ns; --- failure_here
assert FALSE
report "***FAILED TEST: c04s03b01x01p05n01i00058 - Generics cannot be updated."
severity ERROR;
wait;
END PROCESS TESTING;
ENDc04s03b01x01p05n01i00058arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc58.vhd,v 1.2 2001-10-26 16:30:26 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s03b01x01p05n01i00058ent IS
END c04s03b01x01p05n01i00058ent;
ARCHITECTURE c04s03b01x01p05n01i00058arch OF c04s03b01x01p05n01i00058ent IS
BEGIN
TESTING : PROCESS
BEGIN
T1 := 20 ns; --- failure_here
assert FALSE
report "***FAILED TEST: c04s03b01x01p05n01i00058 - Generics cannot be updated."
severity ERROR;
wait;
END PROCESS TESTING;
ENDc04s03b01x01p05n01i00058arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc58.vhd,v 1.2 2001-10-26 16:30:26 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s03b01x01p05n01i00058ent IS
END c04s03b01x01p05n01i00058ent;
ARCHITECTURE c04s03b01x01p05n01i00058arch OF c04s03b01x01p05n01i00058ent IS
BEGIN
TESTING : PROCESS
BEGIN
T1 := 20 ns; --- failure_here
assert FALSE
report "***FAILED TEST: c04s03b01x01p05n01i00058 - Generics cannot be updated."
severity ERROR;
wait;
END PROCESS TESTING;
ENDc04s03b01x01p05n01i00058arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2980.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c02s04b00x00p03n02i02980ent IS
END c02s04b00x00p03n02i02980ent;
ARCHITECTURE c02s04b00x00p03n02i02980arch OF c02s04b00x00p03n02i02980ent IS
-- Create low-level resolution function and its subtypes.
function Always_Zero( S : BIT_VECTOR ) return BIT is
begin
return( '0' );
end Always_Zero;
subtype BIT_SUB is Always_Zero BIT;
type NEW_BIT_VECTOR is array( 1 to 10 ) of BIT_SUB;
-- Create the composite signal resolved at both levels.
signal ONE : NEW_BIT_VECTOR;
BEGIN
-- Create two drivers for the composite.
ONE <= NEW_BIT_VECTOR'(B"1111111111") after 10 ns;
ONE <= NEW_BIT_VECTOR'(B"0000000000") after 20 ns;
TESTING: PROCESS(one)
BEGIN
assert NOT( ONE = B"0000000000" )
report "***PASSED TEST: c02s04b00x00p03n02i02980"
severity NOTE;
assert ( ONE = B"0000000000" )
report "***FAILED TEST: c02s04b00x00p03n02i02980 - Low level resolution function does not got called."
severity ERROR;
END PROCESS TESTING;
END c02s04b00x00p03n02i02980arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2980.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c02s04b00x00p03n02i02980ent IS
END c02s04b00x00p03n02i02980ent;
ARCHITECTURE c02s04b00x00p03n02i02980arch OF c02s04b00x00p03n02i02980ent IS
-- Create low-level resolution function and its subtypes.
function Always_Zero( S : BIT_VECTOR ) return BIT is
begin
return( '0' );
end Always_Zero;
subtype BIT_SUB is Always_Zero BIT;
type NEW_BIT_VECTOR is array( 1 to 10 ) of BIT_SUB;
-- Create the composite signal resolved at both levels.
signal ONE : NEW_BIT_VECTOR;
BEGIN
-- Create two drivers for the composite.
ONE <= NEW_BIT_VECTOR'(B"1111111111") after 10 ns;
ONE <= NEW_BIT_VECTOR'(B"0000000000") after 20 ns;
TESTING: PROCESS(one)
BEGIN
assert NOT( ONE = B"0000000000" )
report "***PASSED TEST: c02s04b00x00p03n02i02980"
severity NOTE;
assert ( ONE = B"0000000000" )
report "***FAILED TEST: c02s04b00x00p03n02i02980 - Low level resolution function does not got called."
severity ERROR;
END PROCESS TESTING;
END c02s04b00x00p03n02i02980arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2980.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c02s04b00x00p03n02i02980ent IS
END c02s04b00x00p03n02i02980ent;
ARCHITECTURE c02s04b00x00p03n02i02980arch OF c02s04b00x00p03n02i02980ent IS
-- Create low-level resolution function and its subtypes.
function Always_Zero( S : BIT_VECTOR ) return BIT is
begin
return( '0' );
end Always_Zero;
subtype BIT_SUB is Always_Zero BIT;
type NEW_BIT_VECTOR is array( 1 to 10 ) of BIT_SUB;
-- Create the composite signal resolved at both levels.
signal ONE : NEW_BIT_VECTOR;
BEGIN
-- Create two drivers for the composite.
ONE <= NEW_BIT_VECTOR'(B"1111111111") after 10 ns;
ONE <= NEW_BIT_VECTOR'(B"0000000000") after 20 ns;
TESTING: PROCESS(one)
BEGIN
assert NOT( ONE = B"0000000000" )
report "***PASSED TEST: c02s04b00x00p03n02i02980"
severity NOTE;
assert ( ONE = B"0000000000" )
report "***FAILED TEST: c02s04b00x00p03n02i02980 - Low level resolution function does not got called."
severity ERROR;
END PROCESS TESTING;
END c02s04b00x00p03n02i02980arch;
|
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_gpio:2.0
-- IP Revision: 7
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_gpio_v2_0;
USE axi_gpio_v2_0.axi_gpio;
ENTITY system_axi_gpio_0_0 IS
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
gpio_io_i : IN STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END system_axi_gpio_0_0;
ARCHITECTURE system_axi_gpio_0_0_arch OF system_axi_gpio_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_axi_gpio_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_gpio IS
GENERIC (
C_FAMILY : STRING;
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER;
C_GPIO_WIDTH : INTEGER;
C_GPIO2_WIDTH : INTEGER;
C_ALL_INPUTS : INTEGER;
C_ALL_INPUTS_2 : INTEGER;
C_ALL_OUTPUTS : INTEGER;
C_ALL_OUTPUTS_2 : INTEGER;
C_INTERRUPT_PRESENT : INTEGER;
C_DOUT_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_TRI_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_IS_DUAL : INTEGER;
C_DOUT_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_TRI_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0)
);
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
ip2intc_irpt : OUT STD_LOGIC;
gpio_io_i : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
gpio_io_o : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
gpio_io_t : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
gpio2_io_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
gpio2_io_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
gpio2_io_t : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT axi_gpio;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXI_ACLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 S_AXI_ARESETN RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
ATTRIBUTE X_INTERFACE_INFO OF gpio_io_i: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_I";
BEGIN
U0 : axi_gpio
GENERIC MAP (
C_FAMILY => "zynq",
C_S_AXI_ADDR_WIDTH => 9,
C_S_AXI_DATA_WIDTH => 32,
C_GPIO_WIDTH => 8,
C_GPIO2_WIDTH => 32,
C_ALL_INPUTS => 1,
C_ALL_INPUTS_2 => 0,
C_ALL_OUTPUTS => 0,
C_ALL_OUTPUTS_2 => 0,
C_INTERRUPT_PRESENT => 0,
C_DOUT_DEFAULT => X"00000000",
C_TRI_DEFAULT => X"FFFFFFFF",
C_IS_DUAL => 0,
C_DOUT_DEFAULT_2 => X"00000000",
C_TRI_DEFAULT_2 => X"FFFFFFFF"
)
PORT MAP (
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_awaddr => s_axi_awaddr,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_araddr => s_axi_araddr,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
gpio_io_i => gpio_io_i,
gpio2_io_i => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32))
);
END system_axi_gpio_0_0_arch;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity SignalExtender_11x16 is
Port (
input : STD_LOGIC_VECTOR (10 downto 0);
output : out STD_LOGIC_VECTOR (15 downto 0));
end SignalExtender_11x16;
architecture skeleton of SignalExtender_11x16 is
begin
process(input) is
begin
for i in 10 downto 0 loop
output(i) <= input(i);
end loop;
for i in 15 downto 10 loop
output(i) <= input(10);
end loop;
end process;
end skeleton; |
--
-- TemporalMixer.vhd
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use WORK.VM2413.ALL;
entity TemporalMixer is
port (
clk : in std_logic;
reset : in std_logic;
clkena : in std_logic;
slot : in SLOT_TYPE;
stage : in STAGE_TYPE;
rhythm : in std_logic;
maddr : out SLOT_TYPE;
mdata : in SIGNED_LI_TYPE;
mo : out std_logic_vector(9 downto 0);
ro : out std_logic_vector(9 downto 0)
);
end TemporalMixer;
architecture RTL of TemporalMixer is
signal mmute, rmute : std_logic;
begin
process (clk, reset)
begin
if reset = '1' then
mo <= (others =>'0');
ro <= (others =>'0');
maddr <= 0;
mmute <= '1';
rmute <= '1';
elsif clk'event and clk = '1' then if clkena='1' then
if stage = 0 then
mo <= "1000000000";
ro <= "1000000000";
if rhythm = '0' then
case slot is
when 0 => maddr <= 1; mmute <='0'; -- CH0
when 1 => maddr <= 3; mmute <='0'; -- CH1
when 2 => maddr <= 5; mmute <='0'; -- CH2
when 3 => mmute <= '1';
when 4 => mmute <= '1';
when 5 => mmute <= '1';
when 6 => maddr <= 7; mmute<='0'; -- CH3
when 7 => maddr <= 9; mmute<='0'; -- CH4
when 8 => maddr <= 11; mmute<='0'; -- CH5
when 9 => mmute <= '1';
when 10 => mmute <= '1';
when 11 => mmute <= '1';
when 12 => maddr <= 13; mmute<='0'; -- CH6
when 13 => maddr <= 15; mmute<='0'; -- CH7
when 14 => maddr <= 17; mmute<='0'; -- CH8
when 15 => mmute <= '1';
when 16 => mmute <= '1';
when 17 => mmute <= '1';
end case;
rmute <= '1';
else
case slot is
when 0 => maddr <= 1; mmute <='0'; rmute <='1'; -- CH0
when 1 => maddr <= 3; mmute <='0'; rmute <='1'; -- CH1
when 2 => maddr <= 5; mmute <='0'; rmute <='1'; -- CH2
when 3 => mmute <='1'; maddr <= 15; rmute <='0'; -- SD
when 4 => mmute <='1'; maddr <= 17; rmute <='0'; -- CYM
when 5 => mmute <='1'; rmute <='1';
when 6 => maddr <= 7; mmute <='0'; rmute <='1'; -- CH3
when 7 => maddr <= 9; mmute <='0'; rmute <='1'; -- CH4
when 8 => maddr <= 11;mmute <='0'; rmute <='1'; -- CH5
when 9 => mmute <='1'; maddr <= 14; rmute <='0'; -- HH
when 10 => mmute <='1'; maddr <= 16; rmute <='0'; -- TOM
when 11 => mmute <='1'; maddr <= 13; rmute <='0'; -- BD
when 12 => mmute <='1'; maddr <= 15; rmute <='0'; -- SD
when 13 => mmute <='1'; maddr <= 17; rmute <='0'; -- CYM
when 14 => mmute <='1'; maddr <= 14; rmute <='0'; -- HH
when 15 => mmute <='1'; maddr <= 16; rmute <='0'; -- TOM
when 16 => mmute <='1'; maddr <= 13; rmute <='0'; -- BD
when 17 => mmute <='1'; rmute <='1';
end case;
end if;
else
if mmute = '0' then
if mdata.sign = '0' then
mo <= "1000000000" + mdata.value;
else
mo <= "1000000000" - mdata.value;
end if;
else
mo <= "1000000000";
end if;
if rmute = '0' then
if mdata.sign = '0' then
ro <= "1000000000" + mdata.value;
else
ro <= "1000000000" - mdata.value;
end if;
else
ro <= "1000000000";
end if;
end if;
end if; end if;
end process;
end RTL; |
--
-- TemporalMixer.vhd
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use WORK.VM2413.ALL;
entity TemporalMixer is
port (
clk : in std_logic;
reset : in std_logic;
clkena : in std_logic;
slot : in SLOT_TYPE;
stage : in STAGE_TYPE;
rhythm : in std_logic;
maddr : out SLOT_TYPE;
mdata : in SIGNED_LI_TYPE;
mo : out std_logic_vector(9 downto 0);
ro : out std_logic_vector(9 downto 0)
);
end TemporalMixer;
architecture RTL of TemporalMixer is
signal mmute, rmute : std_logic;
begin
process (clk, reset)
begin
if reset = '1' then
mo <= (others =>'0');
ro <= (others =>'0');
maddr <= 0;
mmute <= '1';
rmute <= '1';
elsif clk'event and clk = '1' then if clkena='1' then
if stage = 0 then
mo <= "1000000000";
ro <= "1000000000";
if rhythm = '0' then
case slot is
when 0 => maddr <= 1; mmute <='0'; -- CH0
when 1 => maddr <= 3; mmute <='0'; -- CH1
when 2 => maddr <= 5; mmute <='0'; -- CH2
when 3 => mmute <= '1';
when 4 => mmute <= '1';
when 5 => mmute <= '1';
when 6 => maddr <= 7; mmute<='0'; -- CH3
when 7 => maddr <= 9; mmute<='0'; -- CH4
when 8 => maddr <= 11; mmute<='0'; -- CH5
when 9 => mmute <= '1';
when 10 => mmute <= '1';
when 11 => mmute <= '1';
when 12 => maddr <= 13; mmute<='0'; -- CH6
when 13 => maddr <= 15; mmute<='0'; -- CH7
when 14 => maddr <= 17; mmute<='0'; -- CH8
when 15 => mmute <= '1';
when 16 => mmute <= '1';
when 17 => mmute <= '1';
end case;
rmute <= '1';
else
case slot is
when 0 => maddr <= 1; mmute <='0'; rmute <='1'; -- CH0
when 1 => maddr <= 3; mmute <='0'; rmute <='1'; -- CH1
when 2 => maddr <= 5; mmute <='0'; rmute <='1'; -- CH2
when 3 => mmute <='1'; maddr <= 15; rmute <='0'; -- SD
when 4 => mmute <='1'; maddr <= 17; rmute <='0'; -- CYM
when 5 => mmute <='1'; rmute <='1';
when 6 => maddr <= 7; mmute <='0'; rmute <='1'; -- CH3
when 7 => maddr <= 9; mmute <='0'; rmute <='1'; -- CH4
when 8 => maddr <= 11;mmute <='0'; rmute <='1'; -- CH5
when 9 => mmute <='1'; maddr <= 14; rmute <='0'; -- HH
when 10 => mmute <='1'; maddr <= 16; rmute <='0'; -- TOM
when 11 => mmute <='1'; maddr <= 13; rmute <='0'; -- BD
when 12 => mmute <='1'; maddr <= 15; rmute <='0'; -- SD
when 13 => mmute <='1'; maddr <= 17; rmute <='0'; -- CYM
when 14 => mmute <='1'; maddr <= 14; rmute <='0'; -- HH
when 15 => mmute <='1'; maddr <= 16; rmute <='0'; -- TOM
when 16 => mmute <='1'; maddr <= 13; rmute <='0'; -- BD
when 17 => mmute <='1'; rmute <='1';
end case;
end if;
else
if mmute = '0' then
if mdata.sign = '0' then
mo <= "1000000000" + mdata.value;
else
mo <= "1000000000" - mdata.value;
end if;
else
mo <= "1000000000";
end if;
if rmute = '0' then
if mdata.sign = '0' then
ro <= "1000000000" + mdata.value;
else
ro <= "1000000000" - mdata.value;
end if;
else
ro <= "1000000000";
end if;
end if;
end if; end if;
end process;
end RTL; |
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used --
-- solely for design, simulation, implementation and creation of --
-- design files limited to Xilinx devices or technologies. Use --
-- with non-Xilinx devices or technologies is expressly prohibited --
-- and immediately terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
-- FOR A PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support --
-- appliances, devices, or systems. Use in such applications are --
-- expressly prohibited. --
-- --
-- (c) Copyright 1995-2009 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
-- You must compile the wrapper file blk_mem_gen_v4_2.vhd when simulating
-- the core, blk_mem_gen_v4_2. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
Library XilinxCoreLib;
-- synthesis translate_on
ENTITY blk_mem_gen_v4_2 IS
port (
clka: IN std_logic;
ena: IN std_logic;
wea: IN std_logic_VECTOR(0 downto 0);
addra: IN std_logic_VECTOR(4 downto 0);
dina: IN std_logic_VECTOR(127 downto 0);
douta: OUT std_logic_VECTOR(127 downto 0));
END blk_mem_gen_v4_2;
ARCHITECTURE blk_mem_gen_v4_2_a OF blk_mem_gen_v4_2 IS
-- synthesis translate_off
component wrapped_blk_mem_gen_v4_2
port (
clka: IN std_logic;
ena: IN std_logic;
wea: IN std_logic_VECTOR(0 downto 0);
addra: IN std_logic_VECTOR(4 downto 0);
dina: IN std_logic_VECTOR(127 downto 0);
douta: OUT std_logic_VECTOR(127 downto 0));
end component;
-- Configuration specification
for all : wrapped_blk_mem_gen_v4_2 use entity XilinxCoreLib.blk_mem_gen_v4_2(behavioral)
generic map(
c_has_regceb => 0,
c_has_regcea => 0,
c_mem_type => 0,
c_rstram_b => 0,
c_rstram_a => 0,
c_has_injecterr => 0,
c_rst_type => "SYNC",
c_prim_type => 1,
c_read_width_b => 128,
c_initb_val => "0",
c_family => "spartan3",
c_read_width_a => 128,
c_disable_warn_bhv_coll => 0,
c_use_softecc => 0,
c_write_mode_b => "WRITE_FIRST",
c_init_file_name => "no_coe_file_loaded",
c_write_mode_a => "WRITE_FIRST",
c_mux_pipeline_stages => 0,
c_has_softecc_output_regs_b => 0,
c_has_mem_output_regs_b => 0,
c_has_mem_output_regs_a => 0,
c_load_init_file => 0,
c_xdevicefamily => "spartan3",
c_write_depth_b => 32,
c_write_depth_a => 32,
c_has_rstb => 0,
c_has_rsta => 0,
c_has_mux_output_regs_b => 0,
c_inita_val => "0",
c_has_mux_output_regs_a => 0,
c_addra_width => 5,
c_has_softecc_input_regs_a => 0,
c_addrb_width => 5,
c_default_data => "0",
c_use_ecc => 0,
c_algorithm => 1,
c_disable_warn_bhv_range => 0,
c_write_width_b => 128,
c_write_width_a => 128,
c_read_depth_b => 32,
c_read_depth_a => 32,
c_byte_size => 9,
c_sim_collision_check => "ALL",
c_common_clk => 0,
c_wea_width => 1,
c_has_enb => 0,
c_web_width => 1,
c_has_ena => 1,
c_use_byte_web => 0,
c_use_byte_wea => 0,
c_rst_priority_b => "CE",
c_rst_priority_a => "CE",
c_use_default_data => 0);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_blk_mem_gen_v4_2
port map (
clka => clka,
ena => ena,
wea => wea,
addra => addra,
dina => dina,
douta => douta);
-- synthesis translate_on
END blk_mem_gen_v4_2_a;
|
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`protect end_protected
|
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