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-- new_component.vhd
-- This file was auto-generated as a prototype implementation of a module
-- created in component editor. It ties off all outputs to ground and
-- ignores all inputs. It needs to be edited to make it do something
-- useful.
--
-- This file will not be automatically regenerated. You should check it in
-- to your version control system if you want to keep it.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity ip_pwm_top is
port (
avs_s0_address : in std_logic_vector(7 downto 0) := (others => '0'); -- avs_s0.address
avs_s0_read : in std_logic := '0'; -- .read
avs_s0_readdata : out std_logic_vector(31 downto 0); -- .readdata
avs_s0_write : in std_logic := '0'; -- .write
avs_s0_writedata : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata
avs_s0_waitrequest : out std_logic; -- .waitrequest
clock_clk : in std_logic := '0'; -- clock.clk
reset_reset : in std_logic := '0'; -- reset.reset
pwm_out : out std_logic_vector(1 downto 0); -- pwm.pwm_signal
pwm_dir : out std_logic_vector(1 downto 0) -- .dir_signal
);
end entity ip_pwm_top;
architecture rtl of ip_pwm_top is
component ip_pwm_out is
port (
reset_n : in STD_LOGIC;
clk : in STD_LOGIC;
pwm_hz : in STD_LOGIC_VECTOR (7 downto 0);
pwm_dir : in STD_LOGIC;
pwm_duty : in STD_LOGIC_VECTOR (7 downto 0);
pwm_pin_duty : out STD_LOGIC;
pwm_pin_dir : out STD_LOGIC
);
end component ip_pwm_out;
signal reg_data_out :std_logic_vector(31 downto 0);
signal slv_reg0 :std_logic_vector(31 downto 0);
signal slv_reg1 :std_logic_vector(31 downto 0);
signal slv_reg2 :std_logic_vector(31 downto 0);
signal slv_reg3 :std_logic_vector(31 downto 0);
begin
-- TODO: Auto-generated HDL template
process (clock_clk, reset_reset)
variable loc_addr :std_logic_vector(7 downto 0);
begin
if rising_edge(clock_clk) then
if reset_reset = '1' then
slv_reg0 <= (others => '0');
slv_reg1 <= (others => '0');
slv_reg2 <= (others => '0');
slv_reg3 <= (others => '0');
else
loc_addr := avs_s0_address(7 downto 0);
if (avs_s0_write = '1') then
case loc_addr is
when x"00" =>
slv_reg0 <= avs_s0_writedata;
when x"01" =>
slv_reg1 <= avs_s0_writedata;
when x"02" =>
slv_reg2 <= avs_s0_writedata;
when x"03" =>
slv_reg3 <= avs_s0_writedata;
when others =>
slv_reg0 <= slv_reg0;
slv_reg1 <= slv_reg1;
slv_reg2 <= slv_reg2;
slv_reg3 <= slv_reg3;
end case;
end if;
end if;
end if;
end process;
process (slv_reg0, slv_reg1, slv_reg2, slv_reg3)
variable loc_addr :std_logic_vector(7 downto 0);
begin
-- Address decoding for reading registers
loc_addr := avs_s0_address;
case loc_addr is
when x"00" =>
reg_data_out <= slv_reg0;
when x"01" =>
reg_data_out <= slv_reg1;
when x"02" =>
reg_data_out <= slv_reg2;
when x"03" =>
reg_data_out <= slv_reg3;
when others =>
reg_data_out <= (others => '0');
end case;
end process;
avs_s0_readdata <= reg_data_out;
avs_s0_waitrequest <= '0';
PWM_0 : ip_pwm_out
port map (
reset_n => not reset_reset,
clk => clock_clk,
pwm_hz => slv_reg0( 7 downto 0 ),
pwm_dir => slv_reg0( 8 ),
pwm_duty => slv_reg1( 7 downto 0 ),
pwm_pin_duty => pwm_out(0),
pwm_pin_dir => pwm_dir(0)
);
PWM_1 : ip_pwm_out
port map (
reset_n => not reset_reset,
clk => clock_clk,
pwm_hz => slv_reg2( 7 downto 0 ),
pwm_dir => slv_reg2( 8 ),
pwm_duty => slv_reg3( 7 downto 0 ),
pwm_pin_duty => pwm_out(1),
pwm_pin_dir => pwm_dir(1)
);
end architecture rtl; -- of new_component
|
-- new_component.vhd
-- This file was auto-generated as a prototype implementation of a module
-- created in component editor. It ties off all outputs to ground and
-- ignores all inputs. It needs to be edited to make it do something
-- useful.
--
-- This file will not be automatically regenerated. You should check it in
-- to your version control system if you want to keep it.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity ip_pwm_top is
port (
avs_s0_address : in std_logic_vector(7 downto 0) := (others => '0'); -- avs_s0.address
avs_s0_read : in std_logic := '0'; -- .read
avs_s0_readdata : out std_logic_vector(31 downto 0); -- .readdata
avs_s0_write : in std_logic := '0'; -- .write
avs_s0_writedata : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata
avs_s0_waitrequest : out std_logic; -- .waitrequest
clock_clk : in std_logic := '0'; -- clock.clk
reset_reset : in std_logic := '0'; -- reset.reset
pwm_out : out std_logic_vector(1 downto 0); -- pwm.pwm_signal
pwm_dir : out std_logic_vector(1 downto 0) -- .dir_signal
);
end entity ip_pwm_top;
architecture rtl of ip_pwm_top is
component ip_pwm_out is
port (
reset_n : in STD_LOGIC;
clk : in STD_LOGIC;
pwm_hz : in STD_LOGIC_VECTOR (7 downto 0);
pwm_dir : in STD_LOGIC;
pwm_duty : in STD_LOGIC_VECTOR (7 downto 0);
pwm_pin_duty : out STD_LOGIC;
pwm_pin_dir : out STD_LOGIC
);
end component ip_pwm_out;
signal reg_data_out :std_logic_vector(31 downto 0);
signal slv_reg0 :std_logic_vector(31 downto 0);
signal slv_reg1 :std_logic_vector(31 downto 0);
signal slv_reg2 :std_logic_vector(31 downto 0);
signal slv_reg3 :std_logic_vector(31 downto 0);
begin
-- TODO: Auto-generated HDL template
process (clock_clk, reset_reset)
variable loc_addr :std_logic_vector(7 downto 0);
begin
if rising_edge(clock_clk) then
if reset_reset = '1' then
slv_reg0 <= (others => '0');
slv_reg1 <= (others => '0');
slv_reg2 <= (others => '0');
slv_reg3 <= (others => '0');
else
loc_addr := avs_s0_address(7 downto 0);
if (avs_s0_write = '1') then
case loc_addr is
when x"00" =>
slv_reg0 <= avs_s0_writedata;
when x"01" =>
slv_reg1 <= avs_s0_writedata;
when x"02" =>
slv_reg2 <= avs_s0_writedata;
when x"03" =>
slv_reg3 <= avs_s0_writedata;
when others =>
slv_reg0 <= slv_reg0;
slv_reg1 <= slv_reg1;
slv_reg2 <= slv_reg2;
slv_reg3 <= slv_reg3;
end case;
end if;
end if;
end if;
end process;
process (slv_reg0, slv_reg1, slv_reg2, slv_reg3)
variable loc_addr :std_logic_vector(7 downto 0);
begin
-- Address decoding for reading registers
loc_addr := avs_s0_address;
case loc_addr is
when x"00" =>
reg_data_out <= slv_reg0;
when x"01" =>
reg_data_out <= slv_reg1;
when x"02" =>
reg_data_out <= slv_reg2;
when x"03" =>
reg_data_out <= slv_reg3;
when others =>
reg_data_out <= (others => '0');
end case;
end process;
avs_s0_readdata <= reg_data_out;
avs_s0_waitrequest <= '0';
PWM_0 : ip_pwm_out
port map (
reset_n => not reset_reset,
clk => clock_clk,
pwm_hz => slv_reg0( 7 downto 0 ),
pwm_dir => slv_reg0( 8 ),
pwm_duty => slv_reg1( 7 downto 0 ),
pwm_pin_duty => pwm_out(0),
pwm_pin_dir => pwm_dir(0)
);
PWM_1 : ip_pwm_out
port map (
reset_n => not reset_reset,
clk => clock_clk,
pwm_hz => slv_reg2( 7 downto 0 ),
pwm_dir => slv_reg2( 8 ),
pwm_duty => slv_reg3( 7 downto 0 ),
pwm_pin_duty => pwm_out(1),
pwm_pin_dir => pwm_dir(1)
);
end architecture rtl; -- of new_component
|
-- new_component.vhd
-- This file was auto-generated as a prototype implementation of a module
-- created in component editor. It ties off all outputs to ground and
-- ignores all inputs. It needs to be edited to make it do something
-- useful.
--
-- This file will not be automatically regenerated. You should check it in
-- to your version control system if you want to keep it.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity ip_pwm_top is
port (
avs_s0_address : in std_logic_vector(7 downto 0) := (others => '0'); -- avs_s0.address
avs_s0_read : in std_logic := '0'; -- .read
avs_s0_readdata : out std_logic_vector(31 downto 0); -- .readdata
avs_s0_write : in std_logic := '0'; -- .write
avs_s0_writedata : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata
avs_s0_waitrequest : out std_logic; -- .waitrequest
clock_clk : in std_logic := '0'; -- clock.clk
reset_reset : in std_logic := '0'; -- reset.reset
pwm_out : out std_logic_vector(1 downto 0); -- pwm.pwm_signal
pwm_dir : out std_logic_vector(1 downto 0) -- .dir_signal
);
end entity ip_pwm_top;
architecture rtl of ip_pwm_top is
component ip_pwm_out is
port (
reset_n : in STD_LOGIC;
clk : in STD_LOGIC;
pwm_hz : in STD_LOGIC_VECTOR (7 downto 0);
pwm_dir : in STD_LOGIC;
pwm_duty : in STD_LOGIC_VECTOR (7 downto 0);
pwm_pin_duty : out STD_LOGIC;
pwm_pin_dir : out STD_LOGIC
);
end component ip_pwm_out;
signal reg_data_out :std_logic_vector(31 downto 0);
signal slv_reg0 :std_logic_vector(31 downto 0);
signal slv_reg1 :std_logic_vector(31 downto 0);
signal slv_reg2 :std_logic_vector(31 downto 0);
signal slv_reg3 :std_logic_vector(31 downto 0);
begin
-- TODO: Auto-generated HDL template
process (clock_clk, reset_reset)
variable loc_addr :std_logic_vector(7 downto 0);
begin
if rising_edge(clock_clk) then
if reset_reset = '1' then
slv_reg0 <= (others => '0');
slv_reg1 <= (others => '0');
slv_reg2 <= (others => '0');
slv_reg3 <= (others => '0');
else
loc_addr := avs_s0_address(7 downto 0);
if (avs_s0_write = '1') then
case loc_addr is
when x"00" =>
slv_reg0 <= avs_s0_writedata;
when x"01" =>
slv_reg1 <= avs_s0_writedata;
when x"02" =>
slv_reg2 <= avs_s0_writedata;
when x"03" =>
slv_reg3 <= avs_s0_writedata;
when others =>
slv_reg0 <= slv_reg0;
slv_reg1 <= slv_reg1;
slv_reg2 <= slv_reg2;
slv_reg3 <= slv_reg3;
end case;
end if;
end if;
end if;
end process;
process (slv_reg0, slv_reg1, slv_reg2, slv_reg3)
variable loc_addr :std_logic_vector(7 downto 0);
begin
-- Address decoding for reading registers
loc_addr := avs_s0_address;
case loc_addr is
when x"00" =>
reg_data_out <= slv_reg0;
when x"01" =>
reg_data_out <= slv_reg1;
when x"02" =>
reg_data_out <= slv_reg2;
when x"03" =>
reg_data_out <= slv_reg3;
when others =>
reg_data_out <= (others => '0');
end case;
end process;
avs_s0_readdata <= reg_data_out;
avs_s0_waitrequest <= '0';
PWM_0 : ip_pwm_out
port map (
reset_n => not reset_reset,
clk => clock_clk,
pwm_hz => slv_reg0( 7 downto 0 ),
pwm_dir => slv_reg0( 8 ),
pwm_duty => slv_reg1( 7 downto 0 ),
pwm_pin_duty => pwm_out(0),
pwm_pin_dir => pwm_dir(0)
);
PWM_1 : ip_pwm_out
port map (
reset_n => not reset_reset,
clk => clock_clk,
pwm_hz => slv_reg2( 7 downto 0 ),
pwm_dir => slv_reg2( 8 ),
pwm_duty => slv_reg3( 7 downto 0 ),
pwm_pin_duty => pwm_out(1),
pwm_pin_dir => pwm_dir(1)
);
end architecture rtl; -- of new_component
|
-- new_component.vhd
-- This file was auto-generated as a prototype implementation of a module
-- created in component editor. It ties off all outputs to ground and
-- ignores all inputs. It needs to be edited to make it do something
-- useful.
--
-- This file will not be automatically regenerated. You should check it in
-- to your version control system if you want to keep it.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity ip_pwm_top is
port (
avs_s0_address : in std_logic_vector(7 downto 0) := (others => '0'); -- avs_s0.address
avs_s0_read : in std_logic := '0'; -- .read
avs_s0_readdata : out std_logic_vector(31 downto 0); -- .readdata
avs_s0_write : in std_logic := '0'; -- .write
avs_s0_writedata : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata
avs_s0_waitrequest : out std_logic; -- .waitrequest
clock_clk : in std_logic := '0'; -- clock.clk
reset_reset : in std_logic := '0'; -- reset.reset
pwm_out : out std_logic_vector(1 downto 0); -- pwm.pwm_signal
pwm_dir : out std_logic_vector(1 downto 0) -- .dir_signal
);
end entity ip_pwm_top;
architecture rtl of ip_pwm_top is
component ip_pwm_out is
port (
reset_n : in STD_LOGIC;
clk : in STD_LOGIC;
pwm_hz : in STD_LOGIC_VECTOR (7 downto 0);
pwm_dir : in STD_LOGIC;
pwm_duty : in STD_LOGIC_VECTOR (7 downto 0);
pwm_pin_duty : out STD_LOGIC;
pwm_pin_dir : out STD_LOGIC
);
end component ip_pwm_out;
signal reg_data_out :std_logic_vector(31 downto 0);
signal slv_reg0 :std_logic_vector(31 downto 0);
signal slv_reg1 :std_logic_vector(31 downto 0);
signal slv_reg2 :std_logic_vector(31 downto 0);
signal slv_reg3 :std_logic_vector(31 downto 0);
begin
-- TODO: Auto-generated HDL template
process (clock_clk, reset_reset)
variable loc_addr :std_logic_vector(7 downto 0);
begin
if rising_edge(clock_clk) then
if reset_reset = '1' then
slv_reg0 <= (others => '0');
slv_reg1 <= (others => '0');
slv_reg2 <= (others => '0');
slv_reg3 <= (others => '0');
else
loc_addr := avs_s0_address(7 downto 0);
if (avs_s0_write = '1') then
case loc_addr is
when x"00" =>
slv_reg0 <= avs_s0_writedata;
when x"01" =>
slv_reg1 <= avs_s0_writedata;
when x"02" =>
slv_reg2 <= avs_s0_writedata;
when x"03" =>
slv_reg3 <= avs_s0_writedata;
when others =>
slv_reg0 <= slv_reg0;
slv_reg1 <= slv_reg1;
slv_reg2 <= slv_reg2;
slv_reg3 <= slv_reg3;
end case;
end if;
end if;
end if;
end process;
process (slv_reg0, slv_reg1, slv_reg2, slv_reg3)
variable loc_addr :std_logic_vector(7 downto 0);
begin
-- Address decoding for reading registers
loc_addr := avs_s0_address;
case loc_addr is
when x"00" =>
reg_data_out <= slv_reg0;
when x"01" =>
reg_data_out <= slv_reg1;
when x"02" =>
reg_data_out <= slv_reg2;
when x"03" =>
reg_data_out <= slv_reg3;
when others =>
reg_data_out <= (others => '0');
end case;
end process;
avs_s0_readdata <= reg_data_out;
avs_s0_waitrequest <= '0';
PWM_0 : ip_pwm_out
port map (
reset_n => not reset_reset,
clk => clock_clk,
pwm_hz => slv_reg0( 7 downto 0 ),
pwm_dir => slv_reg0( 8 ),
pwm_duty => slv_reg1( 7 downto 0 ),
pwm_pin_duty => pwm_out(0),
pwm_pin_dir => pwm_dir(0)
);
PWM_1 : ip_pwm_out
port map (
reset_n => not reset_reset,
clk => clock_clk,
pwm_hz => slv_reg2( 7 downto 0 ),
pwm_dir => slv_reg2( 8 ),
pwm_duty => slv_reg3( 7 downto 0 ),
pwm_pin_duty => pwm_out(1),
pwm_pin_dir => pwm_dir(1)
);
end architecture rtl; -- of new_component
|
-- new_component.vhd
-- This file was auto-generated as a prototype implementation of a module
-- created in component editor. It ties off all outputs to ground and
-- ignores all inputs. It needs to be edited to make it do something
-- useful.
--
-- This file will not be automatically regenerated. You should check it in
-- to your version control system if you want to keep it.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity ip_pwm_top is
port (
avs_s0_address : in std_logic_vector(7 downto 0) := (others => '0'); -- avs_s0.address
avs_s0_read : in std_logic := '0'; -- .read
avs_s0_readdata : out std_logic_vector(31 downto 0); -- .readdata
avs_s0_write : in std_logic := '0'; -- .write
avs_s0_writedata : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata
avs_s0_waitrequest : out std_logic; -- .waitrequest
clock_clk : in std_logic := '0'; -- clock.clk
reset_reset : in std_logic := '0'; -- reset.reset
pwm_out : out std_logic_vector(1 downto 0); -- pwm.pwm_signal
pwm_dir : out std_logic_vector(1 downto 0) -- .dir_signal
);
end entity ip_pwm_top;
architecture rtl of ip_pwm_top is
component ip_pwm_out is
port (
reset_n : in STD_LOGIC;
clk : in STD_LOGIC;
pwm_hz : in STD_LOGIC_VECTOR (7 downto 0);
pwm_dir : in STD_LOGIC;
pwm_duty : in STD_LOGIC_VECTOR (7 downto 0);
pwm_pin_duty : out STD_LOGIC;
pwm_pin_dir : out STD_LOGIC
);
end component ip_pwm_out;
signal reg_data_out :std_logic_vector(31 downto 0);
signal slv_reg0 :std_logic_vector(31 downto 0);
signal slv_reg1 :std_logic_vector(31 downto 0);
signal slv_reg2 :std_logic_vector(31 downto 0);
signal slv_reg3 :std_logic_vector(31 downto 0);
begin
-- TODO: Auto-generated HDL template
process (clock_clk, reset_reset)
variable loc_addr :std_logic_vector(7 downto 0);
begin
if rising_edge(clock_clk) then
if reset_reset = '1' then
slv_reg0 <= (others => '0');
slv_reg1 <= (others => '0');
slv_reg2 <= (others => '0');
slv_reg3 <= (others => '0');
else
loc_addr := avs_s0_address(7 downto 0);
if (avs_s0_write = '1') then
case loc_addr is
when x"00" =>
slv_reg0 <= avs_s0_writedata;
when x"01" =>
slv_reg1 <= avs_s0_writedata;
when x"02" =>
slv_reg2 <= avs_s0_writedata;
when x"03" =>
slv_reg3 <= avs_s0_writedata;
when others =>
slv_reg0 <= slv_reg0;
slv_reg1 <= slv_reg1;
slv_reg2 <= slv_reg2;
slv_reg3 <= slv_reg3;
end case;
end if;
end if;
end if;
end process;
process (slv_reg0, slv_reg1, slv_reg2, slv_reg3)
variable loc_addr :std_logic_vector(7 downto 0);
begin
-- Address decoding for reading registers
loc_addr := avs_s0_address;
case loc_addr is
when x"00" =>
reg_data_out <= slv_reg0;
when x"01" =>
reg_data_out <= slv_reg1;
when x"02" =>
reg_data_out <= slv_reg2;
when x"03" =>
reg_data_out <= slv_reg3;
when others =>
reg_data_out <= (others => '0');
end case;
end process;
avs_s0_readdata <= reg_data_out;
avs_s0_waitrequest <= '0';
PWM_0 : ip_pwm_out
port map (
reset_n => not reset_reset,
clk => clock_clk,
pwm_hz => slv_reg0( 7 downto 0 ),
pwm_dir => slv_reg0( 8 ),
pwm_duty => slv_reg1( 7 downto 0 ),
pwm_pin_duty => pwm_out(0),
pwm_pin_dir => pwm_dir(0)
);
PWM_1 : ip_pwm_out
port map (
reset_n => not reset_reset,
clk => clock_clk,
pwm_hz => slv_reg2( 7 downto 0 ),
pwm_dir => slv_reg2( 8 ),
pwm_duty => slv_reg3( 7 downto 0 ),
pwm_pin_duty => pwm_out(1),
pwm_pin_dir => pwm_dir(1)
);
end architecture rtl; -- of new_component
|
-- Library Declaration
library IEEE;
use IEEE.std_logic_1164.all;
-- Component Declaration
entity x4time is port (
b_in : in std_logic_vector (7 downto 0);
b_out : out std_logic_vector (7 downto 0) ) ;
end x4time;
-- Architecture of the Component
architecture a_x4time of x4time is
begin
b_out(7) <= b_in(4);
b_out(6) <= b_in(3) xor b_in(7);
b_out(5) <= b_in(2) xor b_in(6) xor b_in(7);
b_out(4) <= b_in(1) xor b_in(5) xor b_in(6);
b_out(3) <= b_in(0) xor b_in(5) xor b_in(7);
b_out(2) <= b_in(6) xor b_in(7);
b_out(1) <= b_in(5) xor b_in(6);
b_out(0) <= b_in(5);
end a_x4time;
|
-- Library Declaration
library IEEE;
use IEEE.std_logic_1164.all;
-- Component Declaration
entity x4time is port (
b_in : in std_logic_vector (7 downto 0);
b_out : out std_logic_vector (7 downto 0) ) ;
end x4time;
-- Architecture of the Component
architecture a_x4time of x4time is
begin
b_out(7) <= b_in(4);
b_out(6) <= b_in(3) xor b_in(7);
b_out(5) <= b_in(2) xor b_in(6) xor b_in(7);
b_out(4) <= b_in(1) xor b_in(5) xor b_in(6);
b_out(3) <= b_in(0) xor b_in(5) xor b_in(7);
b_out(2) <= b_in(6) xor b_in(7);
b_out(1) <= b_in(5) xor b_in(6);
b_out(0) <= b_in(5);
end a_x4time;
|
-------------------------------------------------------------------------------
-- bfm_memory_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library plbv46_slave_bfm_v1_00_a;
use plbv46_slave_bfm_v1_00_a.all;
entity bfm_memory_wrapper is
port (
PLB_CLK : in std_logic;
PLB_RESET : in std_logic;
SYNCH_OUT : out std_logic_vector(0 to 31);
SYNCH_IN : in std_logic_vector(0 to 31);
PLB_PAValid : in std_logic;
PLB_SAValid : in std_logic;
PLB_rdPrim : in std_logic;
PLB_wrPrim : in std_logic;
PLB_masterID : in std_logic_vector(0 to 0);
PLB_abort : in std_logic;
PLB_busLock : in std_logic;
PLB_RNW : in std_logic;
PLB_BE : in std_logic_vector(0 to 15);
PLB_msize : in std_logic_vector(0 to 1);
PLB_size : in std_logic_vector(0 to 3);
PLB_type : in std_logic_vector(0 to 2);
PLB_TAttribute : in std_logic_vector(0 to 15);
PLB_lockErr : in std_logic;
PLB_UABus : in std_logic_vector(0 to 31);
PLB_ABus : in std_logic_vector(0 to 31);
PLB_wrDBus : in std_logic_vector(0 to 127);
PLB_wrBurst : in std_logic;
PLB_rdBurst : in std_logic;
PLB_rdpendReq : in std_logic;
PLB_wrpendReq : in std_logic;
PLB_rdpendPri : in std_logic_vector(0 to 1);
PLB_wrpendPri : in std_logic_vector(0 to 1);
PLB_reqPri : in std_logic_vector(0 to 1);
Sl_addrAck : out std_logic;
Sl_ssize : out std_logic_vector(0 to 1);
Sl_wait : out std_logic;
Sl_rearbitrate : out std_logic;
Sl_wrDAck : out std_logic;
Sl_wrComp : out std_logic;
Sl_wrBTerm : out std_logic;
Sl_rdDBus : out std_logic_vector(0 to 127);
Sl_rdWdAddr : out std_logic_vector(0 to 3);
Sl_rdDAck : out std_logic;
Sl_rdComp : out std_logic;
Sl_rdBTerm : out std_logic;
Sl_MBusy : out std_logic_vector(0 to 0);
Sl_MRdErr : out std_logic_vector(0 to 0);
Sl_MWrErr : out std_logic_vector(0 to 0);
Sl_MIRQ : out std_logic_vector(0 to 0)
);
end bfm_memory_wrapper;
architecture STRUCTURE of bfm_memory_wrapper is
component plbv46_slave_bfm is
generic (
PLB_SLAVE_SIZE : std_logic_vector(0 to 1);
PLB_SLAVE_NUM : std_logic_vector(0 to 3);
PLB_SLAVE_ADDR_LO_0 : std_logic_vector(0 to 31);
PLB_SLAVE_ADDR_HI_0 : std_logic_vector(0 to 31);
PLB_SLAVE_ADDR_LO_1 : std_logic_vector(0 to 31);
PLB_SLAVE_ADDR_HI_1 : std_logic_vector(0 to 31);
C_SPLB_DWIDTH : integer;
C_SPLB_NUM_MASTERS : integer;
C_SPLB_MID_WIDTH : integer
);
port (
PLB_CLK : in std_logic;
PLB_RESET : in std_logic;
SYNCH_OUT : out std_logic_vector(0 to 31);
SYNCH_IN : in std_logic_vector(0 to 31);
PLB_PAValid : in std_logic;
PLB_SAValid : in std_logic;
PLB_rdPrim : in std_logic;
PLB_wrPrim : in std_logic;
PLB_masterID : in std_logic_vector(0 to C_SPLB_MID_WIDTH-1);
PLB_abort : in std_logic;
PLB_busLock : in std_logic;
PLB_RNW : in std_logic;
PLB_BE : in std_logic_vector(0 to ((C_SPLB_DWIDTH/8)-1));
PLB_msize : in std_logic_vector(0 to 1);
PLB_size : in std_logic_vector(0 to 3);
PLB_type : in std_logic_vector(0 to 2);
PLB_TAttribute : in std_logic_vector(0 to 15);
PLB_lockErr : in std_logic;
PLB_UABus : in std_logic_vector(0 to 31);
PLB_ABus : in std_logic_vector(0 to 31);
PLB_wrDBus : in std_logic_vector(0 to (C_SPLB_DWIDTH-1));
PLB_wrBurst : in std_logic;
PLB_rdBurst : in std_logic;
PLB_rdpendReq : in std_logic;
PLB_wrpendReq : in std_logic;
PLB_rdpendPri : in std_logic_vector(0 to 1);
PLB_wrpendPri : in std_logic_vector(0 to 1);
PLB_reqPri : in std_logic_vector(0 to 1);
Sl_addrAck : out std_logic;
Sl_ssize : out std_logic_vector(0 to 1);
Sl_wait : out std_logic;
Sl_rearbitrate : out std_logic;
Sl_wrDAck : out std_logic;
Sl_wrComp : out std_logic;
Sl_wrBTerm : out std_logic;
Sl_rdDBus : out std_logic_vector(0 to (C_SPLB_DWIDTH-1));
Sl_rdWdAddr : out std_logic_vector(0 to 3);
Sl_rdDAck : out std_logic;
Sl_rdComp : out std_logic;
Sl_rdBTerm : out std_logic;
Sl_MBusy : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1));
Sl_MRdErr : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1));
Sl_MWrErr : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1));
Sl_MIRQ : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1))
);
end component;
begin
bfm_memory : plbv46_slave_bfm
generic map (
PLB_SLAVE_SIZE => B"10",
PLB_SLAVE_NUM => B"0000",
PLB_SLAVE_ADDR_LO_0 => X"10000000",
PLB_SLAVE_ADDR_HI_0 => X"1000ffff",
PLB_SLAVE_ADDR_LO_1 => X"20000000",
PLB_SLAVE_ADDR_HI_1 => X"2000ffff",
C_SPLB_DWIDTH => 128,
C_SPLB_NUM_MASTERS => 1,
C_SPLB_MID_WIDTH => 1
)
port map (
PLB_CLK => PLB_CLK,
PLB_RESET => PLB_RESET,
SYNCH_OUT => SYNCH_OUT,
SYNCH_IN => SYNCH_IN,
PLB_PAValid => PLB_PAValid,
PLB_SAValid => PLB_SAValid,
PLB_rdPrim => PLB_rdPrim,
PLB_wrPrim => PLB_wrPrim,
PLB_masterID => PLB_masterID,
PLB_abort => PLB_abort,
PLB_busLock => PLB_busLock,
PLB_RNW => PLB_RNW,
PLB_BE => PLB_BE,
PLB_msize => PLB_msize,
PLB_size => PLB_size,
PLB_type => PLB_type,
PLB_TAttribute => PLB_TAttribute,
PLB_lockErr => PLB_lockErr,
PLB_UABus => PLB_UABus,
PLB_ABus => PLB_ABus,
PLB_wrDBus => PLB_wrDBus,
PLB_wrBurst => PLB_wrBurst,
PLB_rdBurst => PLB_rdBurst,
PLB_rdpendReq => PLB_rdpendReq,
PLB_wrpendReq => PLB_wrpendReq,
PLB_rdpendPri => PLB_rdpendPri,
PLB_wrpendPri => PLB_wrpendPri,
PLB_reqPri => PLB_reqPri,
Sl_addrAck => Sl_addrAck,
Sl_ssize => Sl_ssize,
Sl_wait => Sl_wait,
Sl_rearbitrate => Sl_rearbitrate,
Sl_wrDAck => Sl_wrDAck,
Sl_wrComp => Sl_wrComp,
Sl_wrBTerm => Sl_wrBTerm,
Sl_rdDBus => Sl_rdDBus,
Sl_rdWdAddr => Sl_rdWdAddr,
Sl_rdDAck => Sl_rdDAck,
Sl_rdComp => Sl_rdComp,
Sl_rdBTerm => Sl_rdBTerm,
Sl_MBusy => Sl_MBusy,
Sl_MRdErr => Sl_MRdErr,
Sl_MWrErr => Sl_MWrErr,
Sl_MIRQ => Sl_MIRQ
);
end architecture STRUCTURE;
|
-------------------------------------------------------------------------------
-- bfm_memory_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library plbv46_slave_bfm_v1_00_a;
use plbv46_slave_bfm_v1_00_a.all;
entity bfm_memory_wrapper is
port (
PLB_CLK : in std_logic;
PLB_RESET : in std_logic;
SYNCH_OUT : out std_logic_vector(0 to 31);
SYNCH_IN : in std_logic_vector(0 to 31);
PLB_PAValid : in std_logic;
PLB_SAValid : in std_logic;
PLB_rdPrim : in std_logic;
PLB_wrPrim : in std_logic;
PLB_masterID : in std_logic_vector(0 to 0);
PLB_abort : in std_logic;
PLB_busLock : in std_logic;
PLB_RNW : in std_logic;
PLB_BE : in std_logic_vector(0 to 15);
PLB_msize : in std_logic_vector(0 to 1);
PLB_size : in std_logic_vector(0 to 3);
PLB_type : in std_logic_vector(0 to 2);
PLB_TAttribute : in std_logic_vector(0 to 15);
PLB_lockErr : in std_logic;
PLB_UABus : in std_logic_vector(0 to 31);
PLB_ABus : in std_logic_vector(0 to 31);
PLB_wrDBus : in std_logic_vector(0 to 127);
PLB_wrBurst : in std_logic;
PLB_rdBurst : in std_logic;
PLB_rdpendReq : in std_logic;
PLB_wrpendReq : in std_logic;
PLB_rdpendPri : in std_logic_vector(0 to 1);
PLB_wrpendPri : in std_logic_vector(0 to 1);
PLB_reqPri : in std_logic_vector(0 to 1);
Sl_addrAck : out std_logic;
Sl_ssize : out std_logic_vector(0 to 1);
Sl_wait : out std_logic;
Sl_rearbitrate : out std_logic;
Sl_wrDAck : out std_logic;
Sl_wrComp : out std_logic;
Sl_wrBTerm : out std_logic;
Sl_rdDBus : out std_logic_vector(0 to 127);
Sl_rdWdAddr : out std_logic_vector(0 to 3);
Sl_rdDAck : out std_logic;
Sl_rdComp : out std_logic;
Sl_rdBTerm : out std_logic;
Sl_MBusy : out std_logic_vector(0 to 0);
Sl_MRdErr : out std_logic_vector(0 to 0);
Sl_MWrErr : out std_logic_vector(0 to 0);
Sl_MIRQ : out std_logic_vector(0 to 0)
);
end bfm_memory_wrapper;
architecture STRUCTURE of bfm_memory_wrapper is
component plbv46_slave_bfm is
generic (
PLB_SLAVE_SIZE : std_logic_vector(0 to 1);
PLB_SLAVE_NUM : std_logic_vector(0 to 3);
PLB_SLAVE_ADDR_LO_0 : std_logic_vector(0 to 31);
PLB_SLAVE_ADDR_HI_0 : std_logic_vector(0 to 31);
PLB_SLAVE_ADDR_LO_1 : std_logic_vector(0 to 31);
PLB_SLAVE_ADDR_HI_1 : std_logic_vector(0 to 31);
C_SPLB_DWIDTH : integer;
C_SPLB_NUM_MASTERS : integer;
C_SPLB_MID_WIDTH : integer
);
port (
PLB_CLK : in std_logic;
PLB_RESET : in std_logic;
SYNCH_OUT : out std_logic_vector(0 to 31);
SYNCH_IN : in std_logic_vector(0 to 31);
PLB_PAValid : in std_logic;
PLB_SAValid : in std_logic;
PLB_rdPrim : in std_logic;
PLB_wrPrim : in std_logic;
PLB_masterID : in std_logic_vector(0 to C_SPLB_MID_WIDTH-1);
PLB_abort : in std_logic;
PLB_busLock : in std_logic;
PLB_RNW : in std_logic;
PLB_BE : in std_logic_vector(0 to ((C_SPLB_DWIDTH/8)-1));
PLB_msize : in std_logic_vector(0 to 1);
PLB_size : in std_logic_vector(0 to 3);
PLB_type : in std_logic_vector(0 to 2);
PLB_TAttribute : in std_logic_vector(0 to 15);
PLB_lockErr : in std_logic;
PLB_UABus : in std_logic_vector(0 to 31);
PLB_ABus : in std_logic_vector(0 to 31);
PLB_wrDBus : in std_logic_vector(0 to (C_SPLB_DWIDTH-1));
PLB_wrBurst : in std_logic;
PLB_rdBurst : in std_logic;
PLB_rdpendReq : in std_logic;
PLB_wrpendReq : in std_logic;
PLB_rdpendPri : in std_logic_vector(0 to 1);
PLB_wrpendPri : in std_logic_vector(0 to 1);
PLB_reqPri : in std_logic_vector(0 to 1);
Sl_addrAck : out std_logic;
Sl_ssize : out std_logic_vector(0 to 1);
Sl_wait : out std_logic;
Sl_rearbitrate : out std_logic;
Sl_wrDAck : out std_logic;
Sl_wrComp : out std_logic;
Sl_wrBTerm : out std_logic;
Sl_rdDBus : out std_logic_vector(0 to (C_SPLB_DWIDTH-1));
Sl_rdWdAddr : out std_logic_vector(0 to 3);
Sl_rdDAck : out std_logic;
Sl_rdComp : out std_logic;
Sl_rdBTerm : out std_logic;
Sl_MBusy : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1));
Sl_MRdErr : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1));
Sl_MWrErr : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1));
Sl_MIRQ : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1))
);
end component;
begin
bfm_memory : plbv46_slave_bfm
generic map (
PLB_SLAVE_SIZE => B"10",
PLB_SLAVE_NUM => B"0000",
PLB_SLAVE_ADDR_LO_0 => X"10000000",
PLB_SLAVE_ADDR_HI_0 => X"1000ffff",
PLB_SLAVE_ADDR_LO_1 => X"20000000",
PLB_SLAVE_ADDR_HI_1 => X"2000ffff",
C_SPLB_DWIDTH => 128,
C_SPLB_NUM_MASTERS => 1,
C_SPLB_MID_WIDTH => 1
)
port map (
PLB_CLK => PLB_CLK,
PLB_RESET => PLB_RESET,
SYNCH_OUT => SYNCH_OUT,
SYNCH_IN => SYNCH_IN,
PLB_PAValid => PLB_PAValid,
PLB_SAValid => PLB_SAValid,
PLB_rdPrim => PLB_rdPrim,
PLB_wrPrim => PLB_wrPrim,
PLB_masterID => PLB_masterID,
PLB_abort => PLB_abort,
PLB_busLock => PLB_busLock,
PLB_RNW => PLB_RNW,
PLB_BE => PLB_BE,
PLB_msize => PLB_msize,
PLB_size => PLB_size,
PLB_type => PLB_type,
PLB_TAttribute => PLB_TAttribute,
PLB_lockErr => PLB_lockErr,
PLB_UABus => PLB_UABus,
PLB_ABus => PLB_ABus,
PLB_wrDBus => PLB_wrDBus,
PLB_wrBurst => PLB_wrBurst,
PLB_rdBurst => PLB_rdBurst,
PLB_rdpendReq => PLB_rdpendReq,
PLB_wrpendReq => PLB_wrpendReq,
PLB_rdpendPri => PLB_rdpendPri,
PLB_wrpendPri => PLB_wrpendPri,
PLB_reqPri => PLB_reqPri,
Sl_addrAck => Sl_addrAck,
Sl_ssize => Sl_ssize,
Sl_wait => Sl_wait,
Sl_rearbitrate => Sl_rearbitrate,
Sl_wrDAck => Sl_wrDAck,
Sl_wrComp => Sl_wrComp,
Sl_wrBTerm => Sl_wrBTerm,
Sl_rdDBus => Sl_rdDBus,
Sl_rdWdAddr => Sl_rdWdAddr,
Sl_rdDAck => Sl_rdDAck,
Sl_rdComp => Sl_rdComp,
Sl_rdBTerm => Sl_rdBTerm,
Sl_MBusy => Sl_MBusy,
Sl_MRdErr => Sl_MRdErr,
Sl_MWrErr => Sl_MWrErr,
Sl_MIRQ => Sl_MIRQ
);
end architecture STRUCTURE;
|
--
-- Package File Template
--
-- Purpose: This package defines supplemental types, subtypes,
-- constants, and functions
--
-- To use any of the example code shown below, uncomment the lines and modify as necessary
--
library IEEE;
use IEEE.STD_LOGIC_1164.all;
package MyWork is
-- type <new_type> is
-- record
-- <type_name> : std_logic_vector( 7 downto 0);
-- <type_name> : std_logic;
-- end record;
--
-- Declare constants
--
-- constant <constant_name> : time := <time_unit> ns;
-- constant <constant_name> : integer := <value;
--
-- Declare functions and procedure
--
-- function <function_name> (signal <signal_name> : in <type_declaration>) return <type_declaration>;
-- procedure <procedure_name> (<type_declaration> <constant_name> : in <type_declaration>);
--
end MyWork;
package body MyWork is
---- Example 1
-- function <function_name> (signal <signal_name> : in <type_declaration> ) return <type_declaration> is
-- variable <variable_name> : <type_declaration>;
-- begin
-- <variable_name> := <signal_name> xor <signal_name>;
-- return <variable_name>;
-- end <function_name>;
---- Example 2
-- function <function_name> (signal <signal_name> : in <type_declaration>;
-- signal <signal_name> : in <type_declaration> ) return <type_declaration> is
-- begin
-- if (<signal_name> = '1') then
-- return <signal_name>;
-- else
-- return 'Z';
-- end if;
-- end <function_name>;
---- Procedure Example
-- procedure <procedure_name> (<type_declaration> <constant_name> : in <type_declaration>) is
--
-- begin
--
-- end <procedure_name>;
type PartialProduct is array (integer range <>) of std_logic_vector(16 downto 0);
end MyWork;
|
-- control module (implements MIPS control unit)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_SIGNED.ALL;
ENTITY control IS
PORT(
Opcode : IN STD_LOGIC_VECTOR( 5 DOWNTO 0 );
flush : OUT STD_LOGIC;
flushP : IN STD_LOGIC;
Zero : IN STD_LOGIC;
LessThanZero : IN STD_LOGIC;
RegDst : OUT STD_LOGIC;
ALUSrc : OUT STD_LOGIC;
MemtoReg : OUT STD_LOGIC;
RegWrite : OUT STD_LOGIC;
MemRead : OUT STD_LOGIC;
MemWrite : OUT STD_LOGIC;
Branch : OUT STD_LOGIC;
BranchLessThanZero: OUT STD_LOGIC;
ALUop : OUT STD_LOGIC_VECTOR( 1 DOWNTO 0 );
clock, reset : IN STD_LOGIC );
END control;
ARCHITECTURE behavior OF control IS
SIGNAL R_format, Lw, Sw, Beq, Blt, Addi : STD_LOGIC;
BEGIN
-- Code to generate control signals using opcode bits
R_format <= '1' WHEN Opcode = "000000" ELSE '0';
Lw <= '1' WHEN Opcode = "100011" ELSE '0';
Sw <= '1' WHEN Opcode = "101011" ELSE '0';
Beq <= '1' WHEN Opcode = "000100" ELSE '0';
Blt <= '1' WHEN Opcode = "000110" ELSE '0';
Addi <= '1' WHEN Opcode = "001000" ELSE '0';
RegDst <= R_format ;--OR Addi;
ALUSrc <= Lw OR Sw OR Addi;
MemtoReg <= Lw when flushP = '0' else '0';
RegWrite <= (R_format OR Lw OR Addi) when flushP = '0' else '0';
MemRead <= Lw when flushP = '0' else '0';
MemWrite <= Sw when flushP = '0' else '0';
Branch <= Beq when flushP = '0' else '0';
BranchLessThanZero <= Blt when flushP = '0' else '0';
ALUOp( 1 ) <= R_format;
ALUOp( 0 ) <= Beq OR Blt; --Backup: ALUOp( 0 ) <= Beq ;
flush <= '1' when (flushP='0') AND (( (( Beq = '1' ) AND ( Zero = '1' )) OR (( BLt = '1' ) AND ( LessThanZero = '1' ))))
else '0';
END behavior;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_17_ch_17_04.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity ch_17_04 is
end entity ch_17_04;
----------------------------------------------------------------
architecture test of ch_17_04 is
begin
process is
-- code from book:
type stimulus_record is record
stimulus_time : time;
stimulus_value : bit_vector(0 to 3);
end record stimulus_record;
type stimulus_ptr is access stimulus_record;
variable bus_stimulus : stimulus_ptr;
-- end of code from book
begin
bus_stimulus := new stimulus_record;
bus_stimulus.all := stimulus_record'(20 ns, B"0011");
report time'image(bus_stimulus.all.stimulus_time);
report time'image(bus_stimulus.stimulus_time);
wait;
end process;
end architecture test;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_17_ch_17_04.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity ch_17_04 is
end entity ch_17_04;
----------------------------------------------------------------
architecture test of ch_17_04 is
begin
process is
-- code from book:
type stimulus_record is record
stimulus_time : time;
stimulus_value : bit_vector(0 to 3);
end record stimulus_record;
type stimulus_ptr is access stimulus_record;
variable bus_stimulus : stimulus_ptr;
-- end of code from book
begin
bus_stimulus := new stimulus_record;
bus_stimulus.all := stimulus_record'(20 ns, B"0011");
report time'image(bus_stimulus.all.stimulus_time);
report time'image(bus_stimulus.stimulus_time);
wait;
end process;
end architecture test;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_17_ch_17_04.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity ch_17_04 is
end entity ch_17_04;
----------------------------------------------------------------
architecture test of ch_17_04 is
begin
process is
-- code from book:
type stimulus_record is record
stimulus_time : time;
stimulus_value : bit_vector(0 to 3);
end record stimulus_record;
type stimulus_ptr is access stimulus_record;
variable bus_stimulus : stimulus_ptr;
-- end of code from book
begin
bus_stimulus := new stimulus_record;
bus_stimulus.all := stimulus_record'(20 ns, B"0011");
report time'image(bus_stimulus.all.stimulus_time);
report time'image(bus_stimulus.stimulus_time);
wait;
end process;
end architecture test;
|
package foo is
-- enum_type_def
type foo;
type MULTI_LEVEL_LOGIC is (LOW, HIGH, RISING, FALLING, AMBIGUOUS);
type BIT is ('0','1');
type SWITCH_LEVEL is ('0','1','X');
-- integer_type_def
type TWOS_COMPLEMENT_INTEGER is range -32768 to 32767;
type BYTE_LENGTH_INTEGER is range 0 to 255;
type WORD_INDEX is range 31 downto 0;
-- floating_type_def
type bubba is range -1E18 to 1E18;
-- physical_type_def
type DURATION is range -1E18 to 1E18
units
fs;
ps = 1000 fs;
ns = 1000 ps;
us = 1000 ns;
ms = 1000 us;
sec = 1000 ms;
min = 60 sec;
end units;
type DISTANCE is range 0 to 1E16
units
-- primary unit:
Å;
-- metric lengths:
nm = 10 Å;
um = 1000 nm;
mm = 1000 um;
cm = 10 mm;
m = 1000 mm;
km = 1000 m;
-- English lengths:
mil = 254000 Å;
inch = 1000 mil;
ft = 12 inch;
yd = 3 ft;
fm = 6 ft;
mi = 5280 ft;
lg = 3 mi;
end units DISTANCE;
-- array_type_def
type MY_WORD is array (0 to 31) of BIT;
type DATA_IN is array (7 downto 0) of FIVE_LEVEL_LOGIC;
type MEMORY is array (INTEGER range <>) of MY_WORD;
type SIGNED_FXPT is array (INTEGER range <>) of BIT;
type SIGNED_FXPT_VECTOR is array (NATURAL range <>) of SIGNED_FXPT;
type SIGNED_FXPT_5x4 is array (1 to 5, 1 to 4) of SIGNED_FXPT;
type Word is array (NATURAL range <>) of BIT;
type Memory is array (NATURAL range <>) of Word (31 downto 0);
type E is array (NATURAL range <>) of INTEGER;
type T is array (1 to 10) of E (1 to 0);
-- record_type_def
type DATE is record
DAY : INTEGER range 1 to 31;
MONTH : MONTH_NAME;
YEAR : INTEGER range 0 to 4000;
end record;
type SIGNED_FXPT_COMPLEX is record
RE : SIGNED_FXPT;
IM : SIGNED_FXPT;
end record;
-- access_type_def
type ADDRESS is access MEMORY;
type BUFFER_PTR is access TEMP_BUFFER;
-- file_type_def
type A is file of STRING;
type B is file of NATURAL;
end;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity pio_n is
generic (
RegCnt : positive := 256;
ByteEnable: boolean := false
);
port (
clk : in std_logic := '0'; -- clk.clk
reset : in std_logic := '0'; -- reset.reset
data_in_value : in std_logic_vector(RegCnt*32-1 downto 0) := (others => '0'); -- data.data_in_value
data_in_read : out std_logic_vector(RegCnt-1 downto 0); -- .data_in_read
data_out_value : out std_logic_vector(RegCnt*32-1 downto 0); -- .data_out_value
data_out_write : out std_logic_vector(RegCnt-1 downto 0); -- .data_out_write
avl_mm_address : in std_logic_vector(7 downto 0) := (others => '0'); -- avl_mm.address
avl_mm_writebyteenable : in std_logic_vector(3 downto 0) := (others => '0'); -- .writebyteenable
avl_mm_writedata : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata
avl_mm_chipselect : in std_logic := '0'; -- .chipselect
avl_mm_readdata : out std_logic_vector(31 downto 0); -- .readdata
avl_mm_read : in std_logic := '0' -- .read
);
end entity pio_n;
architecture rtl of pio_n is
begin
p_sync_rd: process(clk,reset) is
begin
if reset = '1' then
avl_mm_readdata <= (others=>'0');
data_in_read <= (others=>'0');
elsif rising_edge(clk) then
data_in_read <= (others=>'0');
for i in 0 to RegCnt-1 loop
if i = unsigned(avl_mm_address) then
avl_mm_readdata <= data_in_value((i+1)*32-1 downto i*32);
if avl_mm_chipselect = '1' and avl_mm_read = '1' then
data_in_read(i) <= '1';
end if;
end if;
end loop;
end if;
end process;
p_sync_wr: process(clk,reset) is
begin
if reset = '1' then
data_out_value <= (others=>'0');
data_out_write <= (others=>'0');
elsif rising_edge(clk) then
data_out_write <= (others=>'0');
for i in 0 to RegCnt-1 loop
if i = unsigned(avl_mm_address) and avl_mm_chipselect = '1' then--and avl_mm_writebyteenable /= "0000" then
for b in 0 to 4-1 loop
if avl_mm_writebyteenable(b) = '1' then
data_out_value((i)*32+(b+1)*8-1 downto b*8+i*32) <= avl_mm_writedata((b+1)*8-1 downto b*8);
data_out_write(i) <= '1';
end if;
end loop;
end if;
end loop;
end if;
end process;
end architecture rtl; -- of new_component
|
-- $Id: sn_humanio.vhd 410 2011-09-18 11:23:09Z mueller $
--
-- Copyright 2010-2011 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: sn_humanio - syn
-- Description: All BTN, SWI, LED and DSP handling for s3board, nexys2/3
--
-- Dependencies: xlib/iob_reg_o_gen
-- bpgen/bp_swibtnled
-- bpgen/sn_4x7segctl
--
-- Test bench: -
--
-- Target Devices: generic
-- Tool versions: xst 11.4, 12.1, 13.1; ghdl 0.26
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2011-09-17 409 13.1 O40d xc3s1000-4 49 86 0 53 s 5.3 ns
-- 2011-07-02 387 12.1 M53d xc3s1000-4 48 87 0 53 s 5.1 ns
-- 2010-04-10 275 11.4 L68 xc3s1000-4 48 87 0 53 s 5.2 ns
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-07-30 400 1.2.1 use CDWIDTH=7 for sn_4x7segctl (for 100 MHz)
-- 2011-07-08 390 1.2 renamed from s3_humanio, add BWIDTH generic
-- 2011-07-02 387 1.1.2 use bp_swibtnled
-- 2010-04-17 278 1.1.1 rename dispdrv -> s3_dispdrv
-- 2010-04-11 276 1.1 instantiate BTN/SWI debouncers via DEBOUNCE generic
-- 2010-04-10 275 1.0 Initial version
------------------------------------------------------------------------------
--
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
use work.xlib.all;
use work.bpgenlib.all;
-- ----------------------------------------------------------------------------
entity sn_humanio is -- human i/o handling: swi,btn,led,dsp
generic (
SWIDTH : positive := 8; -- SWI port width
BWIDTH : positive := 4; -- BTN port width
LWIDTH : positive := 8; -- LED port width
DEBOUNCE : boolean := true); -- instantiate debouncer for SWI,BTN
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset
CE_MSEC : in slbit; -- 1 ms clock enable
SWI : out slv(SWIDTH-1 downto 0); -- switch settings, debounced
BTN : out slv(BWIDTH-1 downto 0); -- button settings, debounced
LED : in slv(LWIDTH-1 downto 0); -- led data
DSP_DAT : in slv16; -- display data
DSP_DP : in slv4; -- display decimal points
I_SWI : in slv(SWIDTH-1 downto 0); -- pad-i: switches
I_BTN : in slv(BWIDTH-1 downto 0); -- pad-i: buttons
O_LED : out slv(LWIDTH-1 downto 0); -- pad-o: leds
O_ANO_N : out slv4; -- pad-o: 7 seg disp: anodes (act.low)
O_SEG_N : out slv8 -- pad-o: 7 seg disp: segments (act.low)
);
end sn_humanio;
architecture syn of sn_humanio is
signal N_ANO_N : slv4 := (others=>'0');
signal N_SEG_N : slv8 := (others=>'0');
begin
IOB_ANO_N : iob_reg_o_gen
generic map (DWIDTH => 4)
port map (CLK => CLK, CE => '1', DO => N_ANO_N, PAD => O_ANO_N);
IOB_SEG_N : iob_reg_o_gen
generic map (DWIDTH => 8)
port map (CLK => CLK, CE => '1', DO => N_SEG_N, PAD => O_SEG_N);
HIO : bp_swibtnled
generic map (
SWIDTH => SWIDTH,
BWIDTH => BWIDTH,
LWIDTH => LWIDTH,
DEBOUNCE => DEBOUNCE)
port map (
CLK => CLK,
RESET => RESET,
CE_MSEC => CE_MSEC,
SWI => SWI,
BTN => BTN,
LED => LED,
I_SWI => I_SWI,
I_BTN => I_BTN,
O_LED => O_LED
);
DRV : sn_4x7segctl
generic map (
CDWIDTH => 7) -- 7 good for 100 MHz on nexys2
port map (
CLK => CLK,
DIN => DSP_DAT,
DP => DSP_DP,
ANO_N => N_ANO_N,
SEG_N => N_SEG_N
);
end syn;
|
-- ####################################
-- # Project: Yarr
-- # Author: Timon Heim
-- # E-Mail: timon.heim at cern.ch
-- # Comments: Deglitches async inputs
-- # Data: 09/2016
-- # Outputs are synchronous to clk_i
-- ####################################
library IEEE;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity synchronizer is
port (
-- Sys connect
clk_i : in std_logic;
rst_n_i : in std_logic;
-- Async input
async_in : in std_logic;
sync_out : out std_logic
);
end synchronizer;
architecture rtl of synchronizer is
signal deglitch_t1 : std_logic;
signal deglitch_t2 : std_logic;
begin
deglitch_proc : process(clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
sync_out <= '0';
deglitch_t1 <= '0';
deglitch_t2 <= '0';
elsif rising_edge(clk_i) then
deglitch_t1 <= async_in;
deglitch_t2 <= deglitch_t1;
sync_out <= deglitch_t2;
end if;
end process deglitch_proc;
end rtl;
|
-- ####################################
-- # Project: Yarr
-- # Author: Timon Heim
-- # E-Mail: timon.heim at cern.ch
-- # Comments: Deglitches async inputs
-- # Data: 09/2016
-- # Outputs are synchronous to clk_i
-- ####################################
library IEEE;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity synchronizer is
port (
-- Sys connect
clk_i : in std_logic;
rst_n_i : in std_logic;
-- Async input
async_in : in std_logic;
sync_out : out std_logic
);
end synchronizer;
architecture rtl of synchronizer is
signal deglitch_t1 : std_logic;
signal deglitch_t2 : std_logic;
begin
deglitch_proc : process(clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
sync_out <= '0';
deglitch_t1 <= '0';
deglitch_t2 <= '0';
elsif rising_edge(clk_i) then
deglitch_t1 <= async_in;
deglitch_t2 <= deglitch_t1;
sync_out <= deglitch_t2;
end if;
end process deglitch_proc;
end rtl;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: syncram128
-- File: syncram128.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: 128-bit syncronous 1-port ram with 32-bit write strobes
-- and tech selection
------------------------------------------------------------------------------
library ieee;
library techmap;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
use techmap.allmem.all;
library grlib;
use grlib.config.all;
use grlib.config_types.all;
use grlib.stdlib.all;
entity syncram128 is
generic (tech : integer := 0; abits : integer := 6; testen : integer := 0;
paren : integer := 0; custombits : integer := 1);
port (
clk : in std_ulogic;
address : in std_logic_vector (abits -1 downto 0);
datain : in std_logic_vector (127+16*paren downto 0);
dataout : out std_logic_vector (127+16*paren downto 0);
enable : in std_logic_vector (3 downto 0);
write : in std_logic_vector (3 downto 0);
testin : in std_logic_vector (TESTIN_WIDTH-1 downto 0) := testin_none;
customclk: in std_ulogic := '0';
customin : in std_logic_vector(4*custombits-1 downto 0) := (others => '0');
customout:out std_logic_vector(4*custombits-1 downto 0));
end;
architecture rtl of syncram128 is
component unisim_syncram128
generic ( abits : integer := 9);
port (
clk : in std_ulogic;
address : in std_logic_vector (abits -1 downto 0);
datain : in std_logic_vector (127 downto 0);
dataout : out std_logic_vector (127 downto 0);
enable : in std_logic_vector (3 downto 0);
write : in std_logic_vector (3 downto 0)
);
end component;
signal dinp, doutp : std_logic_vector(143 downto 0);
signal xenable,xwrite : std_logic_vector(3 downto 0);
signal custominx,customoutx: std_logic_vector(syncram_customif_maxwidth downto 0);
begin
xenable <= enable when testen=0 or testin(TESTIN_WIDTH-2)='0' else "0000";
xwrite <= write when testen=0 or testin(TESTIN_WIDTH-2)='0' else "0000";
custominx(custominx'high downto custombits) <= (others => '0');
custominx(custombits-1 downto 0) <= customin(custombits-1 downto 0);
nocust: if syncram_has_customif(tech)=0 or has_sram128(tech)=0 or paren=1 generate
customoutx <= (others => '0');
end generate;
nopar : if paren = 0 generate
s128 : if has_sram128(tech) = 1 generate
uni : if (is_unisim(tech) = 1) generate
x0 : unisim_syncram128 generic map (abits)
port map (clk, address, datain, dataout, xenable, xwrite);
end generate;
n2x : if (tech = easic45) generate
x0 : n2x_syncram_we generic map (abits => abits, dbits => 128)
port map(clk, address, datain, dataout, xenable, xwrite);
end generate;
customout(4*custombits-1 downto custombits) <= (others => '0');
customout(custombits-1 downto 0) <= customoutx(custombits-1 downto 0);
-- pragma translate_off
dmsg : if GRLIB_CONFIG_ARRAY(grlib_debug_level) >= 2 generate
x : process
begin
assert false report "syncram128: " & tost(2**abits) & "x128" &
" (" & tech_table(tech) & ")"
severity note;
wait;
end process;
end generate;
-- pragma translate_on
end generate;
nos128 : if has_sram128(tech) = 0 generate
x0 : syncram64 generic map (tech, abits, testen, 0, custombits)
port map (clk, address, datain(127 downto 64), dataout(127 downto 64),
enable(3 downto 2), write(3 downto 2), testin,
customclk, customin(4*custombits-1 downto 2*custombits),
customout(4*custombits-1 downto 2*custombits));
x1 : syncram64 generic map (tech, abits, testen, 0, custombits)
port map (clk, address, datain(63 downto 0), dataout(63 downto 0),
enable(1 downto 0), write(1 downto 0), testin,
customclk, customin(2*custombits-1 downto 0), customout(2*custombits-1 downto 0));
end generate;
end generate;
par : if paren = 1 generate
dinp <= datain(127+16*paren downto 120+16*paren) & datain(127 downto 64) &
datain(127+8*paren downto 120+8*paren) & datain(63 downto 0);
dataout <= doutp(143 downto 136) & doutp(71 downto 64) &
doutp(135 downto 72) & doutp(63-16+16*paren downto 0);
x0 : syncram64 generic map (tech, abits, testen, 1, custombits)
port map (clk, address, dinp(143 downto 72), doutp(143 downto 72),
enable(3 downto 2), write(3 downto 2), testin,
customclk, customin(4*custombits-1 downto 2*custombits), customout(4*custombits-1 downto 2*custombits));
x1 : syncram64 generic map (tech, abits, testen, 1, custombits)
port map (clk, address, dinp(71 downto 0), doutp(71 downto 0),
enable(1 downto 0), write(1 downto 0), testin,
customclk, customin(2*custombits-1 downto 0), customout(2*custombits-1 downto 0));
end generate;
end;
|
-- Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2014.1 (lin64) Build 881834 Fri Apr 4 14:00:25 MDT 2014
-- Date : Thu May 22 15:29:26 2014
-- Host : macbook running 64-bit Arch Linux
-- Command : write_vhdl -force -mode synth_stub
-- /home/keith/Documents/VHDL-lib/top/mono_radio/ip/fir_lp_800kHz_0/fir_lp_800kHz_stub.vhdl
-- Design : fir_lp_800kHz
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity fir_lp_800kHz is
Port (
aclk : in STD_LOGIC;
s_axis_data_tvalid : in STD_LOGIC;
s_axis_data_tready : out STD_LOGIC;
s_axis_data_tdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axis_data_tvalid : out STD_LOGIC;
m_axis_data_tdata : out STD_LOGIC_VECTOR ( 95 downto 0 )
);
end fir_lp_800kHz;
architecture stub of fir_lp_800kHz is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "aclk,s_axis_data_tvalid,s_axis_data_tready,s_axis_data_tdata[31:0],m_axis_data_tvalid,m_axis_data_tdata[95:0]";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "fir_compiler_v7_1,Vivado 2014.1";
begin
end;
|
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_t_e
--
-- Generated
-- by: wig
-- on: Fri Jul 15 10:12:12 2005
-- cmd: h:/work/eclipse/mix/mix_0.pl -strip -nodelta ../../autoopen.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_t_e-rtl-a.vhd,v 1.2 2005/07/15 16:20:06 wig Exp $
-- $Date: 2005/07/15 16:20:06 $
-- $Log: inst_t_e-rtl-a.vhd,v $
-- Revision 1.2 2005/07/15 16:20:06 wig
-- Update all testcases; still problems though
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.55 2005/07/13 15:38:34 wig Exp
--
-- Generator: mix_0.pl Revision: 1.36 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of inst_t_e
--
architecture rtl of inst_t_e is
-- Generated Constant Declarations
--
-- Components
--
-- Generated Components
component inst_a_e --
-- No Generated Generics
port (
-- Generated Port for Entity inst_a_e
s_open_i : in std_ulogic;
s_open_o : out std_ulogic
-- End of Generated Port for Entity inst_a_e
);
end component;
-- ---------
--
-- Nets
--
--
-- Generated Signal List
--
signal s_open_i : std_ulogic;
signal s_open_o : std_ulogic;
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
-- Generated Signal Assignments
--
-- Generated Instances
--
-- Generated Instances and Port Mappings
-- Generated Instance Port Map for inst_a
inst_a: inst_a_e
port map (
s_open_i => s_open_i, -- open input
s_open_o => s_open_o -- open output
);
-- End of Generated Instance Port Map for inst_a
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
--------------------------------------------------------------------------------
-- --
-- V H D L F I L E --
-- COPYRIGHT (C) 2009 --
-- --
--------------------------------------------------------------------------------
-- --
-- Title : RLE --
-- Design : MDCT CORE --
-- Author : Michal Krepa --
-- --
--------------------------------------------------------------------------------
-- --
-- File : RLE.VHD --
-- Created : Wed Mar 04 2009 --
-- --
--------------------------------------------------------------------------------
-- --
-- Description : Run Length Encoder --
-- Baseline Entropy Coding --
--------------------------------------------------------------------------------
-- //////////////////////////////////////////////////////////////////////////////
-- /// Copyright (c) 2013, Jahanzeb Ahmad
-- /// All rights reserved.
-- ///
-- /// Redistribution and use in source and binary forms, with or without modification,
-- /// are permitted provided that the following conditions are met:
-- ///
-- /// * Redistributions of source code must retain the above copyright notice,
-- /// this list of conditions and the following disclaimer.
-- /// * Redistributions in binary form must reproduce the above copyright notice,
-- /// this list of conditions and the following disclaimer in the documentation and/or
-- /// other materials provided with the distribution.
-- ///
-- /// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY
-- /// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
-- /// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
-- /// SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- /// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-- /// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-- /// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-- /// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- /// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- /// POSSIBILITY OF SUCH DAMAGE.
-- ///
-- ///
-- /// * http://opensource.org/licenses/MIT
-- /// * http://copyfree.org/licenses/mit/license.txt
-- ///
-- //////////////////////////////////////////////////////////////////////////////
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.All;
use IEEE.NUMERIC_STD.all;
library work;
use work.JPEG_PKG.all;
entity rle is
generic
(
RAMADDR_W : INTEGER := 6;
RAMDATA_W : INTEGER := 12
);
port
(
rst : in STD_LOGIC;
clk : in STD_LOGIC;
di : in STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0);
start_pb : in std_logic;
sof : in std_logic;
rle_sm_settings : in T_SM_SETTINGS;
runlength : out STD_LOGIC_VECTOR(3 downto 0);
size : out STD_LOGIC_VECTOR(3 downto 0);
amplitude : out STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0);
dovalid : out STD_LOGIC;
rd_addr : out STD_LOGIC_VECTOR(5 downto 0)
);
end rle;
architecture rtl of rle is
constant SIZE_REG_C : INTEGER := 4;
constant ZEROS_32_C : UNSIGNED(31 downto 0) := (others => '0');
signal prev_dc_reg_0 : SIGNED(RAMDATA_W-1 downto 0):= (others => '0');
signal prev_dc_reg_1 : SIGNED(RAMDATA_W-1 downto 0):= (others => '0');
signal prev_dc_reg_2 : SIGNED(RAMDATA_W-1 downto 0):= (others => '0');
signal prev_dc_reg_3 : SIGNED(RAMDATA_W-1 downto 0):= (others => '0');
signal acc_reg : SIGNED(RAMDATA_W downto 0):= (others => '0');
signal size_reg : UNSIGNED(SIZE_REG_C-1 downto 0):= (others => '0');
signal ampli_vli_reg : SIGNED(RAMDATA_W downto 0):= (others => '0');
signal runlength_reg : UNSIGNED(3 downto 0):= (others => '0');
signal dovalid_reg : STD_LOGIC:='0';
signal zero_cnt : unsigned(5 downto 0):= (others => '0');
signal wr_cnt_d1 : unsigned(5 downto 0):= (others => '0');
signal wr_cnt : unsigned(5 downto 0):= (others => '0');
signal rd_cnt : unsigned(5 downto 0):= (others => '0');
signal rd_en : std_logic:='0';
signal divalid : STD_LOGIC:='0';
signal divalid_en : std_logic:='0';
signal zrl_proc : std_logic:='0';
signal zrl_di : STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0):= (others => '0');
begin
size <= STD_LOGIC_VECTOR(size_reg);
amplitude <= STD_LOGIC_VECTOR(ampli_vli_reg(11 downto 0));
rd_addr <= STD_LOGIC_VECTOR(rd_cnt);
-------------------------------------------
-- MAIN PROCESSING
-------------------------------------------
process(clk,rst)
begin
if rst = '1' then
wr_cnt_d1 <= (others => '0');
prev_dc_reg_0 <= (others => '0');
prev_dc_reg_1 <= (others => '0');
prev_dc_reg_2 <= (others => '0');
prev_dc_reg_3 <= (others => '0');
dovalid_reg <= '0';
acc_reg <= (others => '0');
runlength_reg <= (others => '0');
runlength <= (others => '0');
dovalid <= '0';
zero_cnt <= (others => '0');
zrl_proc <= '0';
rd_en <= '0';
rd_cnt <= (others => '0');
divalid_en <= '0';
elsif clk = '1' and clk'event then
dovalid_reg <= '0';
runlength_reg <= (others => '0');
wr_cnt_d1 <= wr_cnt;
runlength <= std_logic_vector(runlength_reg);
dovalid <= dovalid_reg;
divalid <= rd_en;
if start_pb = '1' then
rd_cnt <= (others => '0');
rd_en <= '1';
divalid_en <= '1';
end if;
if divalid = '1' and wr_cnt = 63 then
divalid_en <= '0';
end if;
-- input read enable
if rd_en = '1' then
if rd_cnt = 64-1 then
rd_cnt <= (others => '0');
rd_en <= '0';
else
rd_cnt <= rd_cnt + 1;
end if;
end if;
-- input data valid
if divalid = '1' then
wr_cnt <= wr_cnt + 1;
-- first DCT coefficient received, DC data
if wr_cnt = 0 then
-- differental coding of DC data per component
case rle_sm_settings.cmp_idx is
when "000" | "001" =>
acc_reg <= RESIZE(SIGNED(di),RAMDATA_W+1) - RESIZE(prev_dc_reg_0,RAMDATA_W+1);
prev_dc_reg_0 <= SIGNED(di);
when "010" =>
acc_reg <= RESIZE(SIGNED(di),RAMDATA_W+1) - RESIZE(prev_dc_reg_1,RAMDATA_W+1);
prev_dc_reg_1 <= SIGNED(di);
when "011" =>
acc_reg <= RESIZE(SIGNED(di),RAMDATA_W+1) - RESIZE(prev_dc_reg_2,RAMDATA_W+1);
prev_dc_reg_2 <= SIGNED(di);
when others =>
null;
end case;
runlength_reg <= (others => '0');
dovalid_reg <= '1';
-- AC coefficient
else
-- zero AC
if signed(di) = 0 then
-- EOB
if wr_cnt = 63 then
acc_reg <= (others => '0');
runlength_reg <= (others => '0');
dovalid_reg <= '1';
-- no EOB
else
zero_cnt <= zero_cnt + 1;
end if;
-- non-zero AC
else
-- normal RLE case
if zero_cnt <= 15 then
acc_reg <= RESIZE(SIGNED(di),RAMDATA_W+1);
runlength_reg <= zero_cnt(3 downto 0);
zero_cnt <= (others => '0');
dovalid_reg <= '1';
-- zero_cnt > 15
else
-- generate ZRL
acc_reg <= (others => '0');
runlength_reg <= X"F";
zero_cnt <= zero_cnt - 16;
dovalid_reg <= '1';
-- stall input until ZRL is handled
zrl_proc <= '1';
zrl_di <= di;
divalid <= '0';
rd_cnt <= rd_cnt;
end if;
end if;
end if;
end if;
-- ZRL processing
if zrl_proc = '1' then
if zero_cnt <= 15 then
acc_reg <= RESIZE(SIGNED(zrl_di),RAMDATA_W+1);
runlength_reg <= zero_cnt(3 downto 0);
if signed(zrl_di) = 0 then
zero_cnt <= to_unsigned(1,zero_cnt'length);
else
zero_cnt <= (others => '0');
end if;
dovalid_reg <= '1';
divalid <= divalid_en;
-- continue input handling
zrl_proc <= '0';
-- zero_cnt > 15
else
-- generate ZRL
acc_reg <= (others => '0');
runlength_reg <= X"F";
zero_cnt <= zero_cnt - 16;
dovalid_reg <= '1';
divalid <= '0';
rd_cnt <= rd_cnt;
end if;
end if;
-- start of 8x8 block processing
if start_pb = '1' then
zero_cnt <= (others => '0');
wr_cnt <= (others => '0');
end if;
if sof = '1' then
prev_dc_reg_0 <= (others => '0');
prev_dc_reg_1 <= (others => '0');
prev_dc_reg_2 <= (others => '0');
prev_dc_reg_3 <= (others => '0');
end if;
end if;
end process;
-------------------------------------------------------------------
-- Entropy Coder
-------------------------------------------------------------------
p_entropy_coder : process(CLK, RST)
begin
if RST = '1' then
ampli_vli_reg <= (others => '0');
size_reg <= (others => '0');
elsif CLK'event and CLK = '1' then
-- perform VLI (variable length integer) encoding for Symbol-2 (Amplitude)
-- positive input
if acc_reg >= 0 then
ampli_vli_reg <= acc_reg;
else
ampli_vli_reg <= acc_reg - TO_SIGNED(1,RAMDATA_W+1);
end if;
-- compute Symbol-1 Size
if acc_reg = TO_SIGNED(-1,RAMDATA_W+1) then
size_reg <= TO_UNSIGNED(1,SIZE_REG_C);
elsif (acc_reg < TO_SIGNED(-1,RAMDATA_W+1) and acc_reg > TO_SIGNED(-4,RAMDATA_W+1)) then
size_reg <= TO_UNSIGNED(2,SIZE_REG_C);
elsif (acc_reg < TO_SIGNED(-3,RAMDATA_W+1) and acc_reg > TO_SIGNED(-8,RAMDATA_W+1)) then
size_reg <= TO_UNSIGNED(3,SIZE_REG_C);
elsif (acc_reg < TO_SIGNED(-7,RAMDATA_W+1) and acc_reg > TO_SIGNED(-16,RAMDATA_W+1)) then
size_reg <= TO_UNSIGNED(4,SIZE_REG_C);
elsif (acc_reg < TO_SIGNED(-15,RAMDATA_W+1) and acc_reg > TO_SIGNED(-32,RAMDATA_W+1)) then
size_reg <= TO_UNSIGNED(5,SIZE_REG_C);
elsif (acc_reg < TO_SIGNED(-31,RAMDATA_W+1) and acc_reg > TO_SIGNED(-64,RAMDATA_W+1)) then
size_reg <= TO_UNSIGNED(6,SIZE_REG_C);
elsif (acc_reg < TO_SIGNED(-63,RAMDATA_W+1) and acc_reg > TO_SIGNED(-128,RAMDATA_W+1)) then
size_reg <= TO_UNSIGNED(7,SIZE_REG_C);
elsif (acc_reg < TO_SIGNED(-127,RAMDATA_W+1) and acc_reg > TO_SIGNED(-256,RAMDATA_W+1)) then
size_reg <= TO_UNSIGNED(8,SIZE_REG_C);
elsif (acc_reg < TO_SIGNED(-255,RAMDATA_W+1) and acc_reg > TO_SIGNED(-512,RAMDATA_W+1)) then
size_reg <= TO_UNSIGNED(9,SIZE_REG_C);
elsif (acc_reg < TO_SIGNED(-511,RAMDATA_W+1) and acc_reg > TO_SIGNED(-1024,RAMDATA_W+1)) then
size_reg <= TO_UNSIGNED(10,SIZE_REG_C);
elsif (acc_reg < TO_SIGNED(-1023,RAMDATA_W+1) and acc_reg > TO_SIGNED(-2048,RAMDATA_W+1)) then
size_reg <= TO_UNSIGNED(11,SIZE_REG_C);
end if;
-- compute Symbol-1 Size
-- positive input
if acc_reg = TO_SIGNED(1,RAMDATA_W+1) then
size_reg <= TO_UNSIGNED(1,SIZE_REG_C);
elsif (acc_reg > TO_SIGNED(1,RAMDATA_W+1) and acc_reg < TO_SIGNED(4,RAMDATA_W+1)) then
size_reg <= TO_UNSIGNED(2,SIZE_REG_C);
elsif (acc_reg > TO_SIGNED(3,RAMDATA_W+1) and acc_reg < TO_SIGNED(8,RAMDATA_W+1)) then
size_reg <= TO_UNSIGNED(3,SIZE_REG_C);
elsif (acc_reg > TO_SIGNED(7,RAMDATA_W+1) and acc_reg < TO_SIGNED(16,RAMDATA_W+1)) then
size_reg <= TO_UNSIGNED(4,SIZE_REG_C);
elsif (acc_reg > TO_SIGNED(15,RAMDATA_W+1) and acc_reg < TO_SIGNED(32,RAMDATA_W+1)) then
size_reg <= TO_UNSIGNED(5,SIZE_REG_C);
elsif (acc_reg > TO_SIGNED(31,RAMDATA_W+1) and acc_reg < TO_SIGNED(64,RAMDATA_W+1)) then
size_reg <= TO_UNSIGNED(6,SIZE_REG_C);
elsif (acc_reg > TO_SIGNED(63,RAMDATA_W+1) and acc_reg < TO_SIGNED(128,RAMDATA_W+1)) then
size_reg <= TO_UNSIGNED(7,SIZE_REG_C);
elsif (acc_reg > TO_SIGNED(127,RAMDATA_W+1) and acc_reg < TO_SIGNED(256,RAMDATA_W+1)) then
size_reg <= TO_UNSIGNED(8,SIZE_REG_C);
elsif (acc_reg > TO_SIGNED(255,RAMDATA_W+1) and acc_reg < TO_SIGNED(512,RAMDATA_W+1)) then
size_reg <= TO_UNSIGNED(9,SIZE_REG_C);
elsif (acc_reg > TO_SIGNED(511,RAMDATA_W+1) and acc_reg < TO_SIGNED(1024,RAMDATA_W+1)) then
size_reg <= TO_UNSIGNED(10,SIZE_REG_C);
elsif (acc_reg > TO_SIGNED(1023,RAMDATA_W+1) and acc_reg < TO_SIGNED(2048,RAMDATA_W+1)) then
size_reg <= TO_UNSIGNED(11,SIZE_REG_C);
end if;
-- DC coefficient amplitude=0 case OR EOB
if acc_reg = 0 then
size_reg <= TO_UNSIGNED(0,SIZE_REG_C);
end if;
end if;
end process;
end rtl;
--------------------------------------------------------------------------------
|
--------------------------------------------------------------------------------
-- --
-- V H D L F I L E --
-- COPYRIGHT (C) 2009 --
-- --
--------------------------------------------------------------------------------
-- --
-- Title : RLE --
-- Design : MDCT CORE --
-- Author : Michal Krepa --
-- --
--------------------------------------------------------------------------------
-- --
-- File : RLE.VHD --
-- Created : Wed Mar 04 2009 --
-- --
--------------------------------------------------------------------------------
-- --
-- Description : Run Length Encoder --
-- Baseline Entropy Coding --
--------------------------------------------------------------------------------
-- //////////////////////////////////////////////////////////////////////////////
-- /// Copyright (c) 2013, Jahanzeb Ahmad
-- /// All rights reserved.
-- ///
-- /// Redistribution and use in source and binary forms, with or without modification,
-- /// are permitted provided that the following conditions are met:
-- ///
-- /// * Redistributions of source code must retain the above copyright notice,
-- /// this list of conditions and the following disclaimer.
-- /// * Redistributions in binary form must reproduce the above copyright notice,
-- /// this list of conditions and the following disclaimer in the documentation and/or
-- /// other materials provided with the distribution.
-- ///
-- /// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY
-- /// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
-- /// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
-- /// SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- /// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-- /// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-- /// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-- /// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- /// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- /// POSSIBILITY OF SUCH DAMAGE.
-- ///
-- ///
-- /// * http://opensource.org/licenses/MIT
-- /// * http://copyfree.org/licenses/mit/license.txt
-- ///
-- //////////////////////////////////////////////////////////////////////////////
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.All;
use IEEE.NUMERIC_STD.all;
library work;
use work.JPEG_PKG.all;
entity rle is
generic
(
RAMADDR_W : INTEGER := 6;
RAMDATA_W : INTEGER := 12
);
port
(
rst : in STD_LOGIC;
clk : in STD_LOGIC;
di : in STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0);
start_pb : in std_logic;
sof : in std_logic;
rle_sm_settings : in T_SM_SETTINGS;
runlength : out STD_LOGIC_VECTOR(3 downto 0);
size : out STD_LOGIC_VECTOR(3 downto 0);
amplitude : out STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0);
dovalid : out STD_LOGIC;
rd_addr : out STD_LOGIC_VECTOR(5 downto 0)
);
end rle;
architecture rtl of rle is
constant SIZE_REG_C : INTEGER := 4;
constant ZEROS_32_C : UNSIGNED(31 downto 0) := (others => '0');
signal prev_dc_reg_0 : SIGNED(RAMDATA_W-1 downto 0):= (others => '0');
signal prev_dc_reg_1 : SIGNED(RAMDATA_W-1 downto 0):= (others => '0');
signal prev_dc_reg_2 : SIGNED(RAMDATA_W-1 downto 0):= (others => '0');
signal prev_dc_reg_3 : SIGNED(RAMDATA_W-1 downto 0):= (others => '0');
signal acc_reg : SIGNED(RAMDATA_W downto 0):= (others => '0');
signal size_reg : UNSIGNED(SIZE_REG_C-1 downto 0):= (others => '0');
signal ampli_vli_reg : SIGNED(RAMDATA_W downto 0):= (others => '0');
signal runlength_reg : UNSIGNED(3 downto 0):= (others => '0');
signal dovalid_reg : STD_LOGIC:='0';
signal zero_cnt : unsigned(5 downto 0):= (others => '0');
signal wr_cnt_d1 : unsigned(5 downto 0):= (others => '0');
signal wr_cnt : unsigned(5 downto 0):= (others => '0');
signal rd_cnt : unsigned(5 downto 0):= (others => '0');
signal rd_en : std_logic:='0';
signal divalid : STD_LOGIC:='0';
signal divalid_en : std_logic:='0';
signal zrl_proc : std_logic:='0';
signal zrl_di : STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0):= (others => '0');
begin
size <= STD_LOGIC_VECTOR(size_reg);
amplitude <= STD_LOGIC_VECTOR(ampli_vli_reg(11 downto 0));
rd_addr <= STD_LOGIC_VECTOR(rd_cnt);
-------------------------------------------
-- MAIN PROCESSING
-------------------------------------------
process(clk,rst)
begin
if rst = '1' then
wr_cnt_d1 <= (others => '0');
prev_dc_reg_0 <= (others => '0');
prev_dc_reg_1 <= (others => '0');
prev_dc_reg_2 <= (others => '0');
prev_dc_reg_3 <= (others => '0');
dovalid_reg <= '0';
acc_reg <= (others => '0');
runlength_reg <= (others => '0');
runlength <= (others => '0');
dovalid <= '0';
zero_cnt <= (others => '0');
zrl_proc <= '0';
rd_en <= '0';
rd_cnt <= (others => '0');
divalid_en <= '0';
elsif clk = '1' and clk'event then
dovalid_reg <= '0';
runlength_reg <= (others => '0');
wr_cnt_d1 <= wr_cnt;
runlength <= std_logic_vector(runlength_reg);
dovalid <= dovalid_reg;
divalid <= rd_en;
if start_pb = '1' then
rd_cnt <= (others => '0');
rd_en <= '1';
divalid_en <= '1';
end if;
if divalid = '1' and wr_cnt = 63 then
divalid_en <= '0';
end if;
-- input read enable
if rd_en = '1' then
if rd_cnt = 64-1 then
rd_cnt <= (others => '0');
rd_en <= '0';
else
rd_cnt <= rd_cnt + 1;
end if;
end if;
-- input data valid
if divalid = '1' then
wr_cnt <= wr_cnt + 1;
-- first DCT coefficient received, DC data
if wr_cnt = 0 then
-- differental coding of DC data per component
case rle_sm_settings.cmp_idx is
when "000" | "001" =>
acc_reg <= RESIZE(SIGNED(di),RAMDATA_W+1) - RESIZE(prev_dc_reg_0,RAMDATA_W+1);
prev_dc_reg_0 <= SIGNED(di);
when "010" =>
acc_reg <= RESIZE(SIGNED(di),RAMDATA_W+1) - RESIZE(prev_dc_reg_1,RAMDATA_W+1);
prev_dc_reg_1 <= SIGNED(di);
when "011" =>
acc_reg <= RESIZE(SIGNED(di),RAMDATA_W+1) - RESIZE(prev_dc_reg_2,RAMDATA_W+1);
prev_dc_reg_2 <= SIGNED(di);
when others =>
null;
end case;
runlength_reg <= (others => '0');
dovalid_reg <= '1';
-- AC coefficient
else
-- zero AC
if signed(di) = 0 then
-- EOB
if wr_cnt = 63 then
acc_reg <= (others => '0');
runlength_reg <= (others => '0');
dovalid_reg <= '1';
-- no EOB
else
zero_cnt <= zero_cnt + 1;
end if;
-- non-zero AC
else
-- normal RLE case
if zero_cnt <= 15 then
acc_reg <= RESIZE(SIGNED(di),RAMDATA_W+1);
runlength_reg <= zero_cnt(3 downto 0);
zero_cnt <= (others => '0');
dovalid_reg <= '1';
-- zero_cnt > 15
else
-- generate ZRL
acc_reg <= (others => '0');
runlength_reg <= X"F";
zero_cnt <= zero_cnt - 16;
dovalid_reg <= '1';
-- stall input until ZRL is handled
zrl_proc <= '1';
zrl_di <= di;
divalid <= '0';
rd_cnt <= rd_cnt;
end if;
end if;
end if;
end if;
-- ZRL processing
if zrl_proc = '1' then
if zero_cnt <= 15 then
acc_reg <= RESIZE(SIGNED(zrl_di),RAMDATA_W+1);
runlength_reg <= zero_cnt(3 downto 0);
if signed(zrl_di) = 0 then
zero_cnt <= to_unsigned(1,zero_cnt'length);
else
zero_cnt <= (others => '0');
end if;
dovalid_reg <= '1';
divalid <= divalid_en;
-- continue input handling
zrl_proc <= '0';
-- zero_cnt > 15
else
-- generate ZRL
acc_reg <= (others => '0');
runlength_reg <= X"F";
zero_cnt <= zero_cnt - 16;
dovalid_reg <= '1';
divalid <= '0';
rd_cnt <= rd_cnt;
end if;
end if;
-- start of 8x8 block processing
if start_pb = '1' then
zero_cnt <= (others => '0');
wr_cnt <= (others => '0');
end if;
if sof = '1' then
prev_dc_reg_0 <= (others => '0');
prev_dc_reg_1 <= (others => '0');
prev_dc_reg_2 <= (others => '0');
prev_dc_reg_3 <= (others => '0');
end if;
end if;
end process;
-------------------------------------------------------------------
-- Entropy Coder
-------------------------------------------------------------------
p_entropy_coder : process(CLK, RST)
begin
if RST = '1' then
ampli_vli_reg <= (others => '0');
size_reg <= (others => '0');
elsif CLK'event and CLK = '1' then
-- perform VLI (variable length integer) encoding for Symbol-2 (Amplitude)
-- positive input
if acc_reg >= 0 then
ampli_vli_reg <= acc_reg;
else
ampli_vli_reg <= acc_reg - TO_SIGNED(1,RAMDATA_W+1);
end if;
-- compute Symbol-1 Size
if acc_reg = TO_SIGNED(-1,RAMDATA_W+1) then
size_reg <= TO_UNSIGNED(1,SIZE_REG_C);
elsif (acc_reg < TO_SIGNED(-1,RAMDATA_W+1) and acc_reg > TO_SIGNED(-4,RAMDATA_W+1)) then
size_reg <= TO_UNSIGNED(2,SIZE_REG_C);
elsif (acc_reg < TO_SIGNED(-3,RAMDATA_W+1) and acc_reg > TO_SIGNED(-8,RAMDATA_W+1)) then
size_reg <= TO_UNSIGNED(3,SIZE_REG_C);
elsif (acc_reg < TO_SIGNED(-7,RAMDATA_W+1) and acc_reg > TO_SIGNED(-16,RAMDATA_W+1)) then
size_reg <= TO_UNSIGNED(4,SIZE_REG_C);
elsif (acc_reg < TO_SIGNED(-15,RAMDATA_W+1) and acc_reg > TO_SIGNED(-32,RAMDATA_W+1)) then
size_reg <= TO_UNSIGNED(5,SIZE_REG_C);
elsif (acc_reg < TO_SIGNED(-31,RAMDATA_W+1) and acc_reg > TO_SIGNED(-64,RAMDATA_W+1)) then
size_reg <= TO_UNSIGNED(6,SIZE_REG_C);
elsif (acc_reg < TO_SIGNED(-63,RAMDATA_W+1) and acc_reg > TO_SIGNED(-128,RAMDATA_W+1)) then
size_reg <= TO_UNSIGNED(7,SIZE_REG_C);
elsif (acc_reg < TO_SIGNED(-127,RAMDATA_W+1) and acc_reg > TO_SIGNED(-256,RAMDATA_W+1)) then
size_reg <= TO_UNSIGNED(8,SIZE_REG_C);
elsif (acc_reg < TO_SIGNED(-255,RAMDATA_W+1) and acc_reg > TO_SIGNED(-512,RAMDATA_W+1)) then
size_reg <= TO_UNSIGNED(9,SIZE_REG_C);
elsif (acc_reg < TO_SIGNED(-511,RAMDATA_W+1) and acc_reg > TO_SIGNED(-1024,RAMDATA_W+1)) then
size_reg <= TO_UNSIGNED(10,SIZE_REG_C);
elsif (acc_reg < TO_SIGNED(-1023,RAMDATA_W+1) and acc_reg > TO_SIGNED(-2048,RAMDATA_W+1)) then
size_reg <= TO_UNSIGNED(11,SIZE_REG_C);
end if;
-- compute Symbol-1 Size
-- positive input
if acc_reg = TO_SIGNED(1,RAMDATA_W+1) then
size_reg <= TO_UNSIGNED(1,SIZE_REG_C);
elsif (acc_reg > TO_SIGNED(1,RAMDATA_W+1) and acc_reg < TO_SIGNED(4,RAMDATA_W+1)) then
size_reg <= TO_UNSIGNED(2,SIZE_REG_C);
elsif (acc_reg > TO_SIGNED(3,RAMDATA_W+1) and acc_reg < TO_SIGNED(8,RAMDATA_W+1)) then
size_reg <= TO_UNSIGNED(3,SIZE_REG_C);
elsif (acc_reg > TO_SIGNED(7,RAMDATA_W+1) and acc_reg < TO_SIGNED(16,RAMDATA_W+1)) then
size_reg <= TO_UNSIGNED(4,SIZE_REG_C);
elsif (acc_reg > TO_SIGNED(15,RAMDATA_W+1) and acc_reg < TO_SIGNED(32,RAMDATA_W+1)) then
size_reg <= TO_UNSIGNED(5,SIZE_REG_C);
elsif (acc_reg > TO_SIGNED(31,RAMDATA_W+1) and acc_reg < TO_SIGNED(64,RAMDATA_W+1)) then
size_reg <= TO_UNSIGNED(6,SIZE_REG_C);
elsif (acc_reg > TO_SIGNED(63,RAMDATA_W+1) and acc_reg < TO_SIGNED(128,RAMDATA_W+1)) then
size_reg <= TO_UNSIGNED(7,SIZE_REG_C);
elsif (acc_reg > TO_SIGNED(127,RAMDATA_W+1) and acc_reg < TO_SIGNED(256,RAMDATA_W+1)) then
size_reg <= TO_UNSIGNED(8,SIZE_REG_C);
elsif (acc_reg > TO_SIGNED(255,RAMDATA_W+1) and acc_reg < TO_SIGNED(512,RAMDATA_W+1)) then
size_reg <= TO_UNSIGNED(9,SIZE_REG_C);
elsif (acc_reg > TO_SIGNED(511,RAMDATA_W+1) and acc_reg < TO_SIGNED(1024,RAMDATA_W+1)) then
size_reg <= TO_UNSIGNED(10,SIZE_REG_C);
elsif (acc_reg > TO_SIGNED(1023,RAMDATA_W+1) and acc_reg < TO_SIGNED(2048,RAMDATA_W+1)) then
size_reg <= TO_UNSIGNED(11,SIZE_REG_C);
end if;
-- DC coefficient amplitude=0 case OR EOB
if acc_reg = 0 then
size_reg <= TO_UNSIGNED(0,SIZE_REG_C);
end if;
end if;
end process;
end rtl;
--------------------------------------------------------------------------------
|
--------------------------------------------------------------------------------
-- --
-- V H D L F I L E --
-- COPYRIGHT (C) 2009 --
-- --
--------------------------------------------------------------------------------
-- --
-- Title : RLE --
-- Design : MDCT CORE --
-- Author : Michal Krepa --
-- --
--------------------------------------------------------------------------------
-- --
-- File : RLE.VHD --
-- Created : Wed Mar 04 2009 --
-- --
--------------------------------------------------------------------------------
-- --
-- Description : Run Length Encoder --
-- Baseline Entropy Coding --
--------------------------------------------------------------------------------
-- //////////////////////////////////////////////////////////////////////////////
-- /// Copyright (c) 2013, Jahanzeb Ahmad
-- /// All rights reserved.
-- ///
-- /// Redistribution and use in source and binary forms, with or without modification,
-- /// are permitted provided that the following conditions are met:
-- ///
-- /// * Redistributions of source code must retain the above copyright notice,
-- /// this list of conditions and the following disclaimer.
-- /// * Redistributions in binary form must reproduce the above copyright notice,
-- /// this list of conditions and the following disclaimer in the documentation and/or
-- /// other materials provided with the distribution.
-- ///
-- /// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY
-- /// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
-- /// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
-- /// SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- /// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-- /// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-- /// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-- /// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- /// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- /// POSSIBILITY OF SUCH DAMAGE.
-- ///
-- ///
-- /// * http://opensource.org/licenses/MIT
-- /// * http://copyfree.org/licenses/mit/license.txt
-- ///
-- //////////////////////////////////////////////////////////////////////////////
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.All;
use IEEE.NUMERIC_STD.all;
library work;
use work.JPEG_PKG.all;
entity rle is
generic
(
RAMADDR_W : INTEGER := 6;
RAMDATA_W : INTEGER := 12
);
port
(
rst : in STD_LOGIC;
clk : in STD_LOGIC;
di : in STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0);
start_pb : in std_logic;
sof : in std_logic;
rle_sm_settings : in T_SM_SETTINGS;
runlength : out STD_LOGIC_VECTOR(3 downto 0);
size : out STD_LOGIC_VECTOR(3 downto 0);
amplitude : out STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0);
dovalid : out STD_LOGIC;
rd_addr : out STD_LOGIC_VECTOR(5 downto 0)
);
end rle;
architecture rtl of rle is
constant SIZE_REG_C : INTEGER := 4;
constant ZEROS_32_C : UNSIGNED(31 downto 0) := (others => '0');
signal prev_dc_reg_0 : SIGNED(RAMDATA_W-1 downto 0):= (others => '0');
signal prev_dc_reg_1 : SIGNED(RAMDATA_W-1 downto 0):= (others => '0');
signal prev_dc_reg_2 : SIGNED(RAMDATA_W-1 downto 0):= (others => '0');
signal prev_dc_reg_3 : SIGNED(RAMDATA_W-1 downto 0):= (others => '0');
signal acc_reg : SIGNED(RAMDATA_W downto 0):= (others => '0');
signal size_reg : UNSIGNED(SIZE_REG_C-1 downto 0):= (others => '0');
signal ampli_vli_reg : SIGNED(RAMDATA_W downto 0):= (others => '0');
signal runlength_reg : UNSIGNED(3 downto 0):= (others => '0');
signal dovalid_reg : STD_LOGIC:='0';
signal zero_cnt : unsigned(5 downto 0):= (others => '0');
signal wr_cnt_d1 : unsigned(5 downto 0):= (others => '0');
signal wr_cnt : unsigned(5 downto 0):= (others => '0');
signal rd_cnt : unsigned(5 downto 0):= (others => '0');
signal rd_en : std_logic:='0';
signal divalid : STD_LOGIC:='0';
signal divalid_en : std_logic:='0';
signal zrl_proc : std_logic:='0';
signal zrl_di : STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0):= (others => '0');
begin
size <= STD_LOGIC_VECTOR(size_reg);
amplitude <= STD_LOGIC_VECTOR(ampli_vli_reg(11 downto 0));
rd_addr <= STD_LOGIC_VECTOR(rd_cnt);
-------------------------------------------
-- MAIN PROCESSING
-------------------------------------------
process(clk,rst)
begin
if rst = '1' then
wr_cnt_d1 <= (others => '0');
prev_dc_reg_0 <= (others => '0');
prev_dc_reg_1 <= (others => '0');
prev_dc_reg_2 <= (others => '0');
prev_dc_reg_3 <= (others => '0');
dovalid_reg <= '0';
acc_reg <= (others => '0');
runlength_reg <= (others => '0');
runlength <= (others => '0');
dovalid <= '0';
zero_cnt <= (others => '0');
zrl_proc <= '0';
rd_en <= '0';
rd_cnt <= (others => '0');
divalid_en <= '0';
elsif clk = '1' and clk'event then
dovalid_reg <= '0';
runlength_reg <= (others => '0');
wr_cnt_d1 <= wr_cnt;
runlength <= std_logic_vector(runlength_reg);
dovalid <= dovalid_reg;
divalid <= rd_en;
if start_pb = '1' then
rd_cnt <= (others => '0');
rd_en <= '1';
divalid_en <= '1';
end if;
if divalid = '1' and wr_cnt = 63 then
divalid_en <= '0';
end if;
-- input read enable
if rd_en = '1' then
if rd_cnt = 64-1 then
rd_cnt <= (others => '0');
rd_en <= '0';
else
rd_cnt <= rd_cnt + 1;
end if;
end if;
-- input data valid
if divalid = '1' then
wr_cnt <= wr_cnt + 1;
-- first DCT coefficient received, DC data
if wr_cnt = 0 then
-- differental coding of DC data per component
case rle_sm_settings.cmp_idx is
when "000" | "001" =>
acc_reg <= RESIZE(SIGNED(di),RAMDATA_W+1) - RESIZE(prev_dc_reg_0,RAMDATA_W+1);
prev_dc_reg_0 <= SIGNED(di);
when "010" =>
acc_reg <= RESIZE(SIGNED(di),RAMDATA_W+1) - RESIZE(prev_dc_reg_1,RAMDATA_W+1);
prev_dc_reg_1 <= SIGNED(di);
when "011" =>
acc_reg <= RESIZE(SIGNED(di),RAMDATA_W+1) - RESIZE(prev_dc_reg_2,RAMDATA_W+1);
prev_dc_reg_2 <= SIGNED(di);
when others =>
null;
end case;
runlength_reg <= (others => '0');
dovalid_reg <= '1';
-- AC coefficient
else
-- zero AC
if signed(di) = 0 then
-- EOB
if wr_cnt = 63 then
acc_reg <= (others => '0');
runlength_reg <= (others => '0');
dovalid_reg <= '1';
-- no EOB
else
zero_cnt <= zero_cnt + 1;
end if;
-- non-zero AC
else
-- normal RLE case
if zero_cnt <= 15 then
acc_reg <= RESIZE(SIGNED(di),RAMDATA_W+1);
runlength_reg <= zero_cnt(3 downto 0);
zero_cnt <= (others => '0');
dovalid_reg <= '1';
-- zero_cnt > 15
else
-- generate ZRL
acc_reg <= (others => '0');
runlength_reg <= X"F";
zero_cnt <= zero_cnt - 16;
dovalid_reg <= '1';
-- stall input until ZRL is handled
zrl_proc <= '1';
zrl_di <= di;
divalid <= '0';
rd_cnt <= rd_cnt;
end if;
end if;
end if;
end if;
-- ZRL processing
if zrl_proc = '1' then
if zero_cnt <= 15 then
acc_reg <= RESIZE(SIGNED(zrl_di),RAMDATA_W+1);
runlength_reg <= zero_cnt(3 downto 0);
if signed(zrl_di) = 0 then
zero_cnt <= to_unsigned(1,zero_cnt'length);
else
zero_cnt <= (others => '0');
end if;
dovalid_reg <= '1';
divalid <= divalid_en;
-- continue input handling
zrl_proc <= '0';
-- zero_cnt > 15
else
-- generate ZRL
acc_reg <= (others => '0');
runlength_reg <= X"F";
zero_cnt <= zero_cnt - 16;
dovalid_reg <= '1';
divalid <= '0';
rd_cnt <= rd_cnt;
end if;
end if;
-- start of 8x8 block processing
if start_pb = '1' then
zero_cnt <= (others => '0');
wr_cnt <= (others => '0');
end if;
if sof = '1' then
prev_dc_reg_0 <= (others => '0');
prev_dc_reg_1 <= (others => '0');
prev_dc_reg_2 <= (others => '0');
prev_dc_reg_3 <= (others => '0');
end if;
end if;
end process;
-------------------------------------------------------------------
-- Entropy Coder
-------------------------------------------------------------------
p_entropy_coder : process(CLK, RST)
begin
if RST = '1' then
ampli_vli_reg <= (others => '0');
size_reg <= (others => '0');
elsif CLK'event and CLK = '1' then
-- perform VLI (variable length integer) encoding for Symbol-2 (Amplitude)
-- positive input
if acc_reg >= 0 then
ampli_vli_reg <= acc_reg;
else
ampli_vli_reg <= acc_reg - TO_SIGNED(1,RAMDATA_W+1);
end if;
-- compute Symbol-1 Size
if acc_reg = TO_SIGNED(-1,RAMDATA_W+1) then
size_reg <= TO_UNSIGNED(1,SIZE_REG_C);
elsif (acc_reg < TO_SIGNED(-1,RAMDATA_W+1) and acc_reg > TO_SIGNED(-4,RAMDATA_W+1)) then
size_reg <= TO_UNSIGNED(2,SIZE_REG_C);
elsif (acc_reg < TO_SIGNED(-3,RAMDATA_W+1) and acc_reg > TO_SIGNED(-8,RAMDATA_W+1)) then
size_reg <= TO_UNSIGNED(3,SIZE_REG_C);
elsif (acc_reg < TO_SIGNED(-7,RAMDATA_W+1) and acc_reg > TO_SIGNED(-16,RAMDATA_W+1)) then
size_reg <= TO_UNSIGNED(4,SIZE_REG_C);
elsif (acc_reg < TO_SIGNED(-15,RAMDATA_W+1) and acc_reg > TO_SIGNED(-32,RAMDATA_W+1)) then
size_reg <= TO_UNSIGNED(5,SIZE_REG_C);
elsif (acc_reg < TO_SIGNED(-31,RAMDATA_W+1) and acc_reg > TO_SIGNED(-64,RAMDATA_W+1)) then
size_reg <= TO_UNSIGNED(6,SIZE_REG_C);
elsif (acc_reg < TO_SIGNED(-63,RAMDATA_W+1) and acc_reg > TO_SIGNED(-128,RAMDATA_W+1)) then
size_reg <= TO_UNSIGNED(7,SIZE_REG_C);
elsif (acc_reg < TO_SIGNED(-127,RAMDATA_W+1) and acc_reg > TO_SIGNED(-256,RAMDATA_W+1)) then
size_reg <= TO_UNSIGNED(8,SIZE_REG_C);
elsif (acc_reg < TO_SIGNED(-255,RAMDATA_W+1) and acc_reg > TO_SIGNED(-512,RAMDATA_W+1)) then
size_reg <= TO_UNSIGNED(9,SIZE_REG_C);
elsif (acc_reg < TO_SIGNED(-511,RAMDATA_W+1) and acc_reg > TO_SIGNED(-1024,RAMDATA_W+1)) then
size_reg <= TO_UNSIGNED(10,SIZE_REG_C);
elsif (acc_reg < TO_SIGNED(-1023,RAMDATA_W+1) and acc_reg > TO_SIGNED(-2048,RAMDATA_W+1)) then
size_reg <= TO_UNSIGNED(11,SIZE_REG_C);
end if;
-- compute Symbol-1 Size
-- positive input
if acc_reg = TO_SIGNED(1,RAMDATA_W+1) then
size_reg <= TO_UNSIGNED(1,SIZE_REG_C);
elsif (acc_reg > TO_SIGNED(1,RAMDATA_W+1) and acc_reg < TO_SIGNED(4,RAMDATA_W+1)) then
size_reg <= TO_UNSIGNED(2,SIZE_REG_C);
elsif (acc_reg > TO_SIGNED(3,RAMDATA_W+1) and acc_reg < TO_SIGNED(8,RAMDATA_W+1)) then
size_reg <= TO_UNSIGNED(3,SIZE_REG_C);
elsif (acc_reg > TO_SIGNED(7,RAMDATA_W+1) and acc_reg < TO_SIGNED(16,RAMDATA_W+1)) then
size_reg <= TO_UNSIGNED(4,SIZE_REG_C);
elsif (acc_reg > TO_SIGNED(15,RAMDATA_W+1) and acc_reg < TO_SIGNED(32,RAMDATA_W+1)) then
size_reg <= TO_UNSIGNED(5,SIZE_REG_C);
elsif (acc_reg > TO_SIGNED(31,RAMDATA_W+1) and acc_reg < TO_SIGNED(64,RAMDATA_W+1)) then
size_reg <= TO_UNSIGNED(6,SIZE_REG_C);
elsif (acc_reg > TO_SIGNED(63,RAMDATA_W+1) and acc_reg < TO_SIGNED(128,RAMDATA_W+1)) then
size_reg <= TO_UNSIGNED(7,SIZE_REG_C);
elsif (acc_reg > TO_SIGNED(127,RAMDATA_W+1) and acc_reg < TO_SIGNED(256,RAMDATA_W+1)) then
size_reg <= TO_UNSIGNED(8,SIZE_REG_C);
elsif (acc_reg > TO_SIGNED(255,RAMDATA_W+1) and acc_reg < TO_SIGNED(512,RAMDATA_W+1)) then
size_reg <= TO_UNSIGNED(9,SIZE_REG_C);
elsif (acc_reg > TO_SIGNED(511,RAMDATA_W+1) and acc_reg < TO_SIGNED(1024,RAMDATA_W+1)) then
size_reg <= TO_UNSIGNED(10,SIZE_REG_C);
elsif (acc_reg > TO_SIGNED(1023,RAMDATA_W+1) and acc_reg < TO_SIGNED(2048,RAMDATA_W+1)) then
size_reg <= TO_UNSIGNED(11,SIZE_REG_C);
end if;
-- DC coefficient amplitude=0 case OR EOB
if acc_reg = 0 then
size_reg <= TO_UNSIGNED(0,SIZE_REG_C);
end if;
end if;
end process;
end rtl;
--------------------------------------------------------------------------------
|
--------------------------------------------------------------------------------
-- --
-- V H D L F I L E --
-- COPYRIGHT (C) 2009 --
-- --
--------------------------------------------------------------------------------
-- --
-- Title : RLE --
-- Design : MDCT CORE --
-- Author : Michal Krepa --
-- --
--------------------------------------------------------------------------------
-- --
-- File : RLE.VHD --
-- Created : Wed Mar 04 2009 --
-- --
--------------------------------------------------------------------------------
-- --
-- Description : Run Length Encoder --
-- Baseline Entropy Coding --
--------------------------------------------------------------------------------
-- //////////////////////////////////////////////////////////////////////////////
-- /// Copyright (c) 2013, Jahanzeb Ahmad
-- /// All rights reserved.
-- ///
-- /// Redistribution and use in source and binary forms, with or without modification,
-- /// are permitted provided that the following conditions are met:
-- ///
-- /// * Redistributions of source code must retain the above copyright notice,
-- /// this list of conditions and the following disclaimer.
-- /// * Redistributions in binary form must reproduce the above copyright notice,
-- /// this list of conditions and the following disclaimer in the documentation and/or
-- /// other materials provided with the distribution.
-- ///
-- /// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY
-- /// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
-- /// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
-- /// SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- /// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-- /// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-- /// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-- /// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- /// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- /// POSSIBILITY OF SUCH DAMAGE.
-- ///
-- ///
-- /// * http://opensource.org/licenses/MIT
-- /// * http://copyfree.org/licenses/mit/license.txt
-- ///
-- //////////////////////////////////////////////////////////////////////////////
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.All;
use IEEE.NUMERIC_STD.all;
library work;
use work.JPEG_PKG.all;
entity rle is
generic
(
RAMADDR_W : INTEGER := 6;
RAMDATA_W : INTEGER := 12
);
port
(
rst : in STD_LOGIC;
clk : in STD_LOGIC;
di : in STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0);
start_pb : in std_logic;
sof : in std_logic;
rle_sm_settings : in T_SM_SETTINGS;
runlength : out STD_LOGIC_VECTOR(3 downto 0);
size : out STD_LOGIC_VECTOR(3 downto 0);
amplitude : out STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0);
dovalid : out STD_LOGIC;
rd_addr : out STD_LOGIC_VECTOR(5 downto 0)
);
end rle;
architecture rtl of rle is
constant SIZE_REG_C : INTEGER := 4;
constant ZEROS_32_C : UNSIGNED(31 downto 0) := (others => '0');
signal prev_dc_reg_0 : SIGNED(RAMDATA_W-1 downto 0):= (others => '0');
signal prev_dc_reg_1 : SIGNED(RAMDATA_W-1 downto 0):= (others => '0');
signal prev_dc_reg_2 : SIGNED(RAMDATA_W-1 downto 0):= (others => '0');
signal prev_dc_reg_3 : SIGNED(RAMDATA_W-1 downto 0):= (others => '0');
signal acc_reg : SIGNED(RAMDATA_W downto 0):= (others => '0');
signal size_reg : UNSIGNED(SIZE_REG_C-1 downto 0):= (others => '0');
signal ampli_vli_reg : SIGNED(RAMDATA_W downto 0):= (others => '0');
signal runlength_reg : UNSIGNED(3 downto 0):= (others => '0');
signal dovalid_reg : STD_LOGIC:='0';
signal zero_cnt : unsigned(5 downto 0):= (others => '0');
signal wr_cnt_d1 : unsigned(5 downto 0):= (others => '0');
signal wr_cnt : unsigned(5 downto 0):= (others => '0');
signal rd_cnt : unsigned(5 downto 0):= (others => '0');
signal rd_en : std_logic:='0';
signal divalid : STD_LOGIC:='0';
signal divalid_en : std_logic:='0';
signal zrl_proc : std_logic:='0';
signal zrl_di : STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0):= (others => '0');
begin
size <= STD_LOGIC_VECTOR(size_reg);
amplitude <= STD_LOGIC_VECTOR(ampli_vli_reg(11 downto 0));
rd_addr <= STD_LOGIC_VECTOR(rd_cnt);
-------------------------------------------
-- MAIN PROCESSING
-------------------------------------------
process(clk,rst)
begin
if rst = '1' then
wr_cnt_d1 <= (others => '0');
prev_dc_reg_0 <= (others => '0');
prev_dc_reg_1 <= (others => '0');
prev_dc_reg_2 <= (others => '0');
prev_dc_reg_3 <= (others => '0');
dovalid_reg <= '0';
acc_reg <= (others => '0');
runlength_reg <= (others => '0');
runlength <= (others => '0');
dovalid <= '0';
zero_cnt <= (others => '0');
zrl_proc <= '0';
rd_en <= '0';
rd_cnt <= (others => '0');
divalid_en <= '0';
elsif clk = '1' and clk'event then
dovalid_reg <= '0';
runlength_reg <= (others => '0');
wr_cnt_d1 <= wr_cnt;
runlength <= std_logic_vector(runlength_reg);
dovalid <= dovalid_reg;
divalid <= rd_en;
if start_pb = '1' then
rd_cnt <= (others => '0');
rd_en <= '1';
divalid_en <= '1';
end if;
if divalid = '1' and wr_cnt = 63 then
divalid_en <= '0';
end if;
-- input read enable
if rd_en = '1' then
if rd_cnt = 64-1 then
rd_cnt <= (others => '0');
rd_en <= '0';
else
rd_cnt <= rd_cnt + 1;
end if;
end if;
-- input data valid
if divalid = '1' then
wr_cnt <= wr_cnt + 1;
-- first DCT coefficient received, DC data
if wr_cnt = 0 then
-- differental coding of DC data per component
case rle_sm_settings.cmp_idx is
when "000" | "001" =>
acc_reg <= RESIZE(SIGNED(di),RAMDATA_W+1) - RESIZE(prev_dc_reg_0,RAMDATA_W+1);
prev_dc_reg_0 <= SIGNED(di);
when "010" =>
acc_reg <= RESIZE(SIGNED(di),RAMDATA_W+1) - RESIZE(prev_dc_reg_1,RAMDATA_W+1);
prev_dc_reg_1 <= SIGNED(di);
when "011" =>
acc_reg <= RESIZE(SIGNED(di),RAMDATA_W+1) - RESIZE(prev_dc_reg_2,RAMDATA_W+1);
prev_dc_reg_2 <= SIGNED(di);
when others =>
null;
end case;
runlength_reg <= (others => '0');
dovalid_reg <= '1';
-- AC coefficient
else
-- zero AC
if signed(di) = 0 then
-- EOB
if wr_cnt = 63 then
acc_reg <= (others => '0');
runlength_reg <= (others => '0');
dovalid_reg <= '1';
-- no EOB
else
zero_cnt <= zero_cnt + 1;
end if;
-- non-zero AC
else
-- normal RLE case
if zero_cnt <= 15 then
acc_reg <= RESIZE(SIGNED(di),RAMDATA_W+1);
runlength_reg <= zero_cnt(3 downto 0);
zero_cnt <= (others => '0');
dovalid_reg <= '1';
-- zero_cnt > 15
else
-- generate ZRL
acc_reg <= (others => '0');
runlength_reg <= X"F";
zero_cnt <= zero_cnt - 16;
dovalid_reg <= '1';
-- stall input until ZRL is handled
zrl_proc <= '1';
zrl_di <= di;
divalid <= '0';
rd_cnt <= rd_cnt;
end if;
end if;
end if;
end if;
-- ZRL processing
if zrl_proc = '1' then
if zero_cnt <= 15 then
acc_reg <= RESIZE(SIGNED(zrl_di),RAMDATA_W+1);
runlength_reg <= zero_cnt(3 downto 0);
if signed(zrl_di) = 0 then
zero_cnt <= to_unsigned(1,zero_cnt'length);
else
zero_cnt <= (others => '0');
end if;
dovalid_reg <= '1';
divalid <= divalid_en;
-- continue input handling
zrl_proc <= '0';
-- zero_cnt > 15
else
-- generate ZRL
acc_reg <= (others => '0');
runlength_reg <= X"F";
zero_cnt <= zero_cnt - 16;
dovalid_reg <= '1';
divalid <= '0';
rd_cnt <= rd_cnt;
end if;
end if;
-- start of 8x8 block processing
if start_pb = '1' then
zero_cnt <= (others => '0');
wr_cnt <= (others => '0');
end if;
if sof = '1' then
prev_dc_reg_0 <= (others => '0');
prev_dc_reg_1 <= (others => '0');
prev_dc_reg_2 <= (others => '0');
prev_dc_reg_3 <= (others => '0');
end if;
end if;
end process;
-------------------------------------------------------------------
-- Entropy Coder
-------------------------------------------------------------------
p_entropy_coder : process(CLK, RST)
begin
if RST = '1' then
ampli_vli_reg <= (others => '0');
size_reg <= (others => '0');
elsif CLK'event and CLK = '1' then
-- perform VLI (variable length integer) encoding for Symbol-2 (Amplitude)
-- positive input
if acc_reg >= 0 then
ampli_vli_reg <= acc_reg;
else
ampli_vli_reg <= acc_reg - TO_SIGNED(1,RAMDATA_W+1);
end if;
-- compute Symbol-1 Size
if acc_reg = TO_SIGNED(-1,RAMDATA_W+1) then
size_reg <= TO_UNSIGNED(1,SIZE_REG_C);
elsif (acc_reg < TO_SIGNED(-1,RAMDATA_W+1) and acc_reg > TO_SIGNED(-4,RAMDATA_W+1)) then
size_reg <= TO_UNSIGNED(2,SIZE_REG_C);
elsif (acc_reg < TO_SIGNED(-3,RAMDATA_W+1) and acc_reg > TO_SIGNED(-8,RAMDATA_W+1)) then
size_reg <= TO_UNSIGNED(3,SIZE_REG_C);
elsif (acc_reg < TO_SIGNED(-7,RAMDATA_W+1) and acc_reg > TO_SIGNED(-16,RAMDATA_W+1)) then
size_reg <= TO_UNSIGNED(4,SIZE_REG_C);
elsif (acc_reg < TO_SIGNED(-15,RAMDATA_W+1) and acc_reg > TO_SIGNED(-32,RAMDATA_W+1)) then
size_reg <= TO_UNSIGNED(5,SIZE_REG_C);
elsif (acc_reg < TO_SIGNED(-31,RAMDATA_W+1) and acc_reg > TO_SIGNED(-64,RAMDATA_W+1)) then
size_reg <= TO_UNSIGNED(6,SIZE_REG_C);
elsif (acc_reg < TO_SIGNED(-63,RAMDATA_W+1) and acc_reg > TO_SIGNED(-128,RAMDATA_W+1)) then
size_reg <= TO_UNSIGNED(7,SIZE_REG_C);
elsif (acc_reg < TO_SIGNED(-127,RAMDATA_W+1) and acc_reg > TO_SIGNED(-256,RAMDATA_W+1)) then
size_reg <= TO_UNSIGNED(8,SIZE_REG_C);
elsif (acc_reg < TO_SIGNED(-255,RAMDATA_W+1) and acc_reg > TO_SIGNED(-512,RAMDATA_W+1)) then
size_reg <= TO_UNSIGNED(9,SIZE_REG_C);
elsif (acc_reg < TO_SIGNED(-511,RAMDATA_W+1) and acc_reg > TO_SIGNED(-1024,RAMDATA_W+1)) then
size_reg <= TO_UNSIGNED(10,SIZE_REG_C);
elsif (acc_reg < TO_SIGNED(-1023,RAMDATA_W+1) and acc_reg > TO_SIGNED(-2048,RAMDATA_W+1)) then
size_reg <= TO_UNSIGNED(11,SIZE_REG_C);
end if;
-- compute Symbol-1 Size
-- positive input
if acc_reg = TO_SIGNED(1,RAMDATA_W+1) then
size_reg <= TO_UNSIGNED(1,SIZE_REG_C);
elsif (acc_reg > TO_SIGNED(1,RAMDATA_W+1) and acc_reg < TO_SIGNED(4,RAMDATA_W+1)) then
size_reg <= TO_UNSIGNED(2,SIZE_REG_C);
elsif (acc_reg > TO_SIGNED(3,RAMDATA_W+1) and acc_reg < TO_SIGNED(8,RAMDATA_W+1)) then
size_reg <= TO_UNSIGNED(3,SIZE_REG_C);
elsif (acc_reg > TO_SIGNED(7,RAMDATA_W+1) and acc_reg < TO_SIGNED(16,RAMDATA_W+1)) then
size_reg <= TO_UNSIGNED(4,SIZE_REG_C);
elsif (acc_reg > TO_SIGNED(15,RAMDATA_W+1) and acc_reg < TO_SIGNED(32,RAMDATA_W+1)) then
size_reg <= TO_UNSIGNED(5,SIZE_REG_C);
elsif (acc_reg > TO_SIGNED(31,RAMDATA_W+1) and acc_reg < TO_SIGNED(64,RAMDATA_W+1)) then
size_reg <= TO_UNSIGNED(6,SIZE_REG_C);
elsif (acc_reg > TO_SIGNED(63,RAMDATA_W+1) and acc_reg < TO_SIGNED(128,RAMDATA_W+1)) then
size_reg <= TO_UNSIGNED(7,SIZE_REG_C);
elsif (acc_reg > TO_SIGNED(127,RAMDATA_W+1) and acc_reg < TO_SIGNED(256,RAMDATA_W+1)) then
size_reg <= TO_UNSIGNED(8,SIZE_REG_C);
elsif (acc_reg > TO_SIGNED(255,RAMDATA_W+1) and acc_reg < TO_SIGNED(512,RAMDATA_W+1)) then
size_reg <= TO_UNSIGNED(9,SIZE_REG_C);
elsif (acc_reg > TO_SIGNED(511,RAMDATA_W+1) and acc_reg < TO_SIGNED(1024,RAMDATA_W+1)) then
size_reg <= TO_UNSIGNED(10,SIZE_REG_C);
elsif (acc_reg > TO_SIGNED(1023,RAMDATA_W+1) and acc_reg < TO_SIGNED(2048,RAMDATA_W+1)) then
size_reg <= TO_UNSIGNED(11,SIZE_REG_C);
end if;
-- DC coefficient amplitude=0 case OR EOB
if acc_reg = 0 then
size_reg <= TO_UNSIGNED(0,SIZE_REG_C);
end if;
end if;
end process;
end rtl;
--------------------------------------------------------------------------------
|
--------------------------------------------------------------------------------
-- --
-- V H D L F I L E --
-- COPYRIGHT (C) 2009 --
-- --
--------------------------------------------------------------------------------
-- --
-- Title : RLE --
-- Design : MDCT CORE --
-- Author : Michal Krepa --
-- --
--------------------------------------------------------------------------------
-- --
-- File : RLE.VHD --
-- Created : Wed Mar 04 2009 --
-- --
--------------------------------------------------------------------------------
-- --
-- Description : Run Length Encoder --
-- Baseline Entropy Coding --
--------------------------------------------------------------------------------
-- //////////////////////////////////////////////////////////////////////////////
-- /// Copyright (c) 2013, Jahanzeb Ahmad
-- /// All rights reserved.
-- ///
-- /// Redistribution and use in source and binary forms, with or without modification,
-- /// are permitted provided that the following conditions are met:
-- ///
-- /// * Redistributions of source code must retain the above copyright notice,
-- /// this list of conditions and the following disclaimer.
-- /// * Redistributions in binary form must reproduce the above copyright notice,
-- /// this list of conditions and the following disclaimer in the documentation and/or
-- /// other materials provided with the distribution.
-- ///
-- /// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY
-- /// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
-- /// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
-- /// SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- /// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-- /// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-- /// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-- /// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- /// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- /// POSSIBILITY OF SUCH DAMAGE.
-- ///
-- ///
-- /// * http://opensource.org/licenses/MIT
-- /// * http://copyfree.org/licenses/mit/license.txt
-- ///
-- //////////////////////////////////////////////////////////////////////////////
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.All;
use IEEE.NUMERIC_STD.all;
library work;
use work.JPEG_PKG.all;
entity rle is
generic
(
RAMADDR_W : INTEGER := 6;
RAMDATA_W : INTEGER := 12
);
port
(
rst : in STD_LOGIC;
clk : in STD_LOGIC;
di : in STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0);
start_pb : in std_logic;
sof : in std_logic;
rle_sm_settings : in T_SM_SETTINGS;
runlength : out STD_LOGIC_VECTOR(3 downto 0);
size : out STD_LOGIC_VECTOR(3 downto 0);
amplitude : out STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0);
dovalid : out STD_LOGIC;
rd_addr : out STD_LOGIC_VECTOR(5 downto 0)
);
end rle;
architecture rtl of rle is
constant SIZE_REG_C : INTEGER := 4;
constant ZEROS_32_C : UNSIGNED(31 downto 0) := (others => '0');
signal prev_dc_reg_0 : SIGNED(RAMDATA_W-1 downto 0):= (others => '0');
signal prev_dc_reg_1 : SIGNED(RAMDATA_W-1 downto 0):= (others => '0');
signal prev_dc_reg_2 : SIGNED(RAMDATA_W-1 downto 0):= (others => '0');
signal prev_dc_reg_3 : SIGNED(RAMDATA_W-1 downto 0):= (others => '0');
signal acc_reg : SIGNED(RAMDATA_W downto 0):= (others => '0');
signal size_reg : UNSIGNED(SIZE_REG_C-1 downto 0):= (others => '0');
signal ampli_vli_reg : SIGNED(RAMDATA_W downto 0):= (others => '0');
signal runlength_reg : UNSIGNED(3 downto 0):= (others => '0');
signal dovalid_reg : STD_LOGIC:='0';
signal zero_cnt : unsigned(5 downto 0):= (others => '0');
signal wr_cnt_d1 : unsigned(5 downto 0):= (others => '0');
signal wr_cnt : unsigned(5 downto 0):= (others => '0');
signal rd_cnt : unsigned(5 downto 0):= (others => '0');
signal rd_en : std_logic:='0';
signal divalid : STD_LOGIC:='0';
signal divalid_en : std_logic:='0';
signal zrl_proc : std_logic:='0';
signal zrl_di : STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0):= (others => '0');
begin
size <= STD_LOGIC_VECTOR(size_reg);
amplitude <= STD_LOGIC_VECTOR(ampli_vli_reg(11 downto 0));
rd_addr <= STD_LOGIC_VECTOR(rd_cnt);
-------------------------------------------
-- MAIN PROCESSING
-------------------------------------------
process(clk,rst)
begin
if rst = '1' then
wr_cnt_d1 <= (others => '0');
prev_dc_reg_0 <= (others => '0');
prev_dc_reg_1 <= (others => '0');
prev_dc_reg_2 <= (others => '0');
prev_dc_reg_3 <= (others => '0');
dovalid_reg <= '0';
acc_reg <= (others => '0');
runlength_reg <= (others => '0');
runlength <= (others => '0');
dovalid <= '0';
zero_cnt <= (others => '0');
zrl_proc <= '0';
rd_en <= '0';
rd_cnt <= (others => '0');
divalid_en <= '0';
elsif clk = '1' and clk'event then
dovalid_reg <= '0';
runlength_reg <= (others => '0');
wr_cnt_d1 <= wr_cnt;
runlength <= std_logic_vector(runlength_reg);
dovalid <= dovalid_reg;
divalid <= rd_en;
if start_pb = '1' then
rd_cnt <= (others => '0');
rd_en <= '1';
divalid_en <= '1';
end if;
if divalid = '1' and wr_cnt = 63 then
divalid_en <= '0';
end if;
-- input read enable
if rd_en = '1' then
if rd_cnt = 64-1 then
rd_cnt <= (others => '0');
rd_en <= '0';
else
rd_cnt <= rd_cnt + 1;
end if;
end if;
-- input data valid
if divalid = '1' then
wr_cnt <= wr_cnt + 1;
-- first DCT coefficient received, DC data
if wr_cnt = 0 then
-- differental coding of DC data per component
case rle_sm_settings.cmp_idx is
when "000" | "001" =>
acc_reg <= RESIZE(SIGNED(di),RAMDATA_W+1) - RESIZE(prev_dc_reg_0,RAMDATA_W+1);
prev_dc_reg_0 <= SIGNED(di);
when "010" =>
acc_reg <= RESIZE(SIGNED(di),RAMDATA_W+1) - RESIZE(prev_dc_reg_1,RAMDATA_W+1);
prev_dc_reg_1 <= SIGNED(di);
when "011" =>
acc_reg <= RESIZE(SIGNED(di),RAMDATA_W+1) - RESIZE(prev_dc_reg_2,RAMDATA_W+1);
prev_dc_reg_2 <= SIGNED(di);
when others =>
null;
end case;
runlength_reg <= (others => '0');
dovalid_reg <= '1';
-- AC coefficient
else
-- zero AC
if signed(di) = 0 then
-- EOB
if wr_cnt = 63 then
acc_reg <= (others => '0');
runlength_reg <= (others => '0');
dovalid_reg <= '1';
-- no EOB
else
zero_cnt <= zero_cnt + 1;
end if;
-- non-zero AC
else
-- normal RLE case
if zero_cnt <= 15 then
acc_reg <= RESIZE(SIGNED(di),RAMDATA_W+1);
runlength_reg <= zero_cnt(3 downto 0);
zero_cnt <= (others => '0');
dovalid_reg <= '1';
-- zero_cnt > 15
else
-- generate ZRL
acc_reg <= (others => '0');
runlength_reg <= X"F";
zero_cnt <= zero_cnt - 16;
dovalid_reg <= '1';
-- stall input until ZRL is handled
zrl_proc <= '1';
zrl_di <= di;
divalid <= '0';
rd_cnt <= rd_cnt;
end if;
end if;
end if;
end if;
-- ZRL processing
if zrl_proc = '1' then
if zero_cnt <= 15 then
acc_reg <= RESIZE(SIGNED(zrl_di),RAMDATA_W+1);
runlength_reg <= zero_cnt(3 downto 0);
if signed(zrl_di) = 0 then
zero_cnt <= to_unsigned(1,zero_cnt'length);
else
zero_cnt <= (others => '0');
end if;
dovalid_reg <= '1';
divalid <= divalid_en;
-- continue input handling
zrl_proc <= '0';
-- zero_cnt > 15
else
-- generate ZRL
acc_reg <= (others => '0');
runlength_reg <= X"F";
zero_cnt <= zero_cnt - 16;
dovalid_reg <= '1';
divalid <= '0';
rd_cnt <= rd_cnt;
end if;
end if;
-- start of 8x8 block processing
if start_pb = '1' then
zero_cnt <= (others => '0');
wr_cnt <= (others => '0');
end if;
if sof = '1' then
prev_dc_reg_0 <= (others => '0');
prev_dc_reg_1 <= (others => '0');
prev_dc_reg_2 <= (others => '0');
prev_dc_reg_3 <= (others => '0');
end if;
end if;
end process;
-------------------------------------------------------------------
-- Entropy Coder
-------------------------------------------------------------------
p_entropy_coder : process(CLK, RST)
begin
if RST = '1' then
ampli_vli_reg <= (others => '0');
size_reg <= (others => '0');
elsif CLK'event and CLK = '1' then
-- perform VLI (variable length integer) encoding for Symbol-2 (Amplitude)
-- positive input
if acc_reg >= 0 then
ampli_vli_reg <= acc_reg;
else
ampli_vli_reg <= acc_reg - TO_SIGNED(1,RAMDATA_W+1);
end if;
-- compute Symbol-1 Size
if acc_reg = TO_SIGNED(-1,RAMDATA_W+1) then
size_reg <= TO_UNSIGNED(1,SIZE_REG_C);
elsif (acc_reg < TO_SIGNED(-1,RAMDATA_W+1) and acc_reg > TO_SIGNED(-4,RAMDATA_W+1)) then
size_reg <= TO_UNSIGNED(2,SIZE_REG_C);
elsif (acc_reg < TO_SIGNED(-3,RAMDATA_W+1) and acc_reg > TO_SIGNED(-8,RAMDATA_W+1)) then
size_reg <= TO_UNSIGNED(3,SIZE_REG_C);
elsif (acc_reg < TO_SIGNED(-7,RAMDATA_W+1) and acc_reg > TO_SIGNED(-16,RAMDATA_W+1)) then
size_reg <= TO_UNSIGNED(4,SIZE_REG_C);
elsif (acc_reg < TO_SIGNED(-15,RAMDATA_W+1) and acc_reg > TO_SIGNED(-32,RAMDATA_W+1)) then
size_reg <= TO_UNSIGNED(5,SIZE_REG_C);
elsif (acc_reg < TO_SIGNED(-31,RAMDATA_W+1) and acc_reg > TO_SIGNED(-64,RAMDATA_W+1)) then
size_reg <= TO_UNSIGNED(6,SIZE_REG_C);
elsif (acc_reg < TO_SIGNED(-63,RAMDATA_W+1) and acc_reg > TO_SIGNED(-128,RAMDATA_W+1)) then
size_reg <= TO_UNSIGNED(7,SIZE_REG_C);
elsif (acc_reg < TO_SIGNED(-127,RAMDATA_W+1) and acc_reg > TO_SIGNED(-256,RAMDATA_W+1)) then
size_reg <= TO_UNSIGNED(8,SIZE_REG_C);
elsif (acc_reg < TO_SIGNED(-255,RAMDATA_W+1) and acc_reg > TO_SIGNED(-512,RAMDATA_W+1)) then
size_reg <= TO_UNSIGNED(9,SIZE_REG_C);
elsif (acc_reg < TO_SIGNED(-511,RAMDATA_W+1) and acc_reg > TO_SIGNED(-1024,RAMDATA_W+1)) then
size_reg <= TO_UNSIGNED(10,SIZE_REG_C);
elsif (acc_reg < TO_SIGNED(-1023,RAMDATA_W+1) and acc_reg > TO_SIGNED(-2048,RAMDATA_W+1)) then
size_reg <= TO_UNSIGNED(11,SIZE_REG_C);
end if;
-- compute Symbol-1 Size
-- positive input
if acc_reg = TO_SIGNED(1,RAMDATA_W+1) then
size_reg <= TO_UNSIGNED(1,SIZE_REG_C);
elsif (acc_reg > TO_SIGNED(1,RAMDATA_W+1) and acc_reg < TO_SIGNED(4,RAMDATA_W+1)) then
size_reg <= TO_UNSIGNED(2,SIZE_REG_C);
elsif (acc_reg > TO_SIGNED(3,RAMDATA_W+1) and acc_reg < TO_SIGNED(8,RAMDATA_W+1)) then
size_reg <= TO_UNSIGNED(3,SIZE_REG_C);
elsif (acc_reg > TO_SIGNED(7,RAMDATA_W+1) and acc_reg < TO_SIGNED(16,RAMDATA_W+1)) then
size_reg <= TO_UNSIGNED(4,SIZE_REG_C);
elsif (acc_reg > TO_SIGNED(15,RAMDATA_W+1) and acc_reg < TO_SIGNED(32,RAMDATA_W+1)) then
size_reg <= TO_UNSIGNED(5,SIZE_REG_C);
elsif (acc_reg > TO_SIGNED(31,RAMDATA_W+1) and acc_reg < TO_SIGNED(64,RAMDATA_W+1)) then
size_reg <= TO_UNSIGNED(6,SIZE_REG_C);
elsif (acc_reg > TO_SIGNED(63,RAMDATA_W+1) and acc_reg < TO_SIGNED(128,RAMDATA_W+1)) then
size_reg <= TO_UNSIGNED(7,SIZE_REG_C);
elsif (acc_reg > TO_SIGNED(127,RAMDATA_W+1) and acc_reg < TO_SIGNED(256,RAMDATA_W+1)) then
size_reg <= TO_UNSIGNED(8,SIZE_REG_C);
elsif (acc_reg > TO_SIGNED(255,RAMDATA_W+1) and acc_reg < TO_SIGNED(512,RAMDATA_W+1)) then
size_reg <= TO_UNSIGNED(9,SIZE_REG_C);
elsif (acc_reg > TO_SIGNED(511,RAMDATA_W+1) and acc_reg < TO_SIGNED(1024,RAMDATA_W+1)) then
size_reg <= TO_UNSIGNED(10,SIZE_REG_C);
elsif (acc_reg > TO_SIGNED(1023,RAMDATA_W+1) and acc_reg < TO_SIGNED(2048,RAMDATA_W+1)) then
size_reg <= TO_UNSIGNED(11,SIZE_REG_C);
end if;
-- DC coefficient amplitude=0 case OR EOB
if acc_reg = 0 then
size_reg <= TO_UNSIGNED(0,SIZE_REG_C);
end if;
end if;
end process;
end rtl;
--------------------------------------------------------------------------------
|
library ieee;
use ieee.std_logic_1164.all;
entity ent is
end;
architecture a of ent is
begin
assert false
report "Just a note"
severity note;
assert false
report "Test assertion failed"
severity failure;
end;
|
architecture ARCH of FIFO is
signal sig1 : std_logic; -- comment
signal sig1 : std_logic; -- comment
signal sig1 : std_logic; -- comment
signal sig1 : std_logic; -- comment
signal sig1 : std_logic; -- comment
-- This comment should be left alone
signal sig1 : std_logic; -- comment
signal sig1 : std_logic; -- comment
signal sig1 : std_logic; -- comment
signal sig1 : std_logic; -- comment
signal sig1 : std_logic; -- comment
signal sig1 : std_logic; -- comment
signal sig1 : std_logic; -- comment
signal sig1 : std_logic; -- comment
signal sig1 : std_logic; -- comment
signal sig1 : std_logic; -- comment
-- This comment should be left alone
signal sig1 : std_logic; -- comment
signal sig1 : std_logic; -- comment
signal sig1 : std_logic; -- comment
signal sig1 : std_logic; -- comment
signal sig1 : std_logic; -- comment
--------------------
-- COMMENT BLOCK
--
--
--
--------------------
begin
end architecture ARCH;
|
-- ____ _ _
-- / ___| ___ _ _ _ __ __| | __ _ __ _| |_ ___ ___
-- \___ \ / _ \| | | | '_ \ / _` |/ _` |/ _` | __/ _ \/ __|
-- ___) | (_) | |_| | | | | (_| | (_| | (_| | || __/\__ \
-- |____/ \___/ \__,_|_| |_|\__,_|\__, |\__,_|\__\___||___/
-- |___/
-- ======================================================================
--
-- title: VHDL module - hwt_ramp
--
-- project: PG-Soundgates
-- author: Hendrik Hangmann, University of Paderborn
--
-- description: Hardware thread for generating ramp envelope
--
-- ======================================================================
library ieee;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
--library proc_common_v3_00_a;
--use proc_common_v3_00_a.proc_common_pkg.all;
library reconos_v3_00_c;
use reconos_v3_00_c.reconos_pkg.all;
library soundgates_v1_00_a;
use soundgates_v1_00_a.soundgates_common_pkg.all;
use soundgates_v1_00_a.soundgates_reconos_pkg.all;
entity hwt_ramp is
port (
-- OSIF FIFO ports
OSIF_FIFO_Sw2Hw_Data : in std_logic_vector(31 downto 0);
OSIF_FIFO_Sw2Hw_Fill : in std_logic_vector(15 downto 0);
OSIF_FIFO_Sw2Hw_Empty : in std_logic;
OSIF_FIFO_Sw2Hw_RE : out std_logic;
OSIF_FIFO_Hw2Sw_Data : out std_logic_vector(31 downto 0);
OSIF_FIFO_Hw2Sw_Rem : in std_logic_vector(15 downto 0);
OSIF_FIFO_Hw2Sw_Full : in std_logic;
OSIF_FIFO_Hw2Sw_WE : out std_logic;
-- MEMIF FIFO ports
MEMIF_FIFO_Hwt2Mem_Data : out std_logic_vector(31 downto 0);
MEMIF_FIFO_Hwt2Mem_Rem : in std_logic_vector(15 downto 0);
MEMIF_FIFO_Hwt2Mem_Full : in std_logic;
MEMIF_FIFO_Hwt2Mem_WE : out std_logic;
MEMIF_FIFO_Mem2Hwt_Data : in std_logic_vector(31 downto 0);
MEMIF_FIFO_Mem2Hwt_Fill : in std_logic_vector(15 downto 0);
MEMIF_FIFO_Mem2Hwt_Empty : in std_logic;
MEMIF_FIFO_Mem2Hwt_RE : out std_logic;
HWT_Clk : in std_logic;
HWT_Rst : in std_logic
);
end hwt_ramp;
architecture Behavioral of hwt_ramp is
----------------------------------------------------------------
-- Subcomponent declarations
----------------------------------------------------------------
component ramp is
port(
clk : in std_logic;
rst : in std_logic;
ce : in std_logic;
incr : in signed(31 downto 0);
incr2 : in signed(31 downto 0);
rmp : out signed(31 downto 0)
);
end component ramp;
signal clk : std_logic;
signal rst : std_logic;
-- ReconOS Stuff
signal i_osif : i_osif_t;
signal o_osif : o_osif_t;
signal i_memif : i_memif_t;
signal o_memif : o_memif_t;
signal i_ram : i_ram_t;
signal o_ram : o_ram_t;
constant MBOX_START : std_logic_vector(31 downto 0) := x"00000000";
constant MBOX_FINISH : std_logic_vector(31 downto 0) := x"00000001";
-- /ReconOS Stuff
type STATE_TYPE is (STATE_INIT, STATE_WAITING, STATE_REFRESH_INPUT, STATE_PROCESS, STATE_WRITE_MEM, STATE_NOTIFY, STATE_EXIT);
signal state : STATE_TYPE;
----------------------------------------------------------------
-- Common sound component signals, constants and types
----------------------------------------------------------------
constant C_MAX_SAMPLE_COUNT : integer := 64;
-- define size of local RAM here
constant C_LOCAL_RAM_SIZE : integer := C_MAX_SAMPLE_COUNT;
constant C_LOCAL_RAM_ADDRESS_WIDTH : integer := 6;--clog2(C_LOCAL_RAM_SIZE);
constant C_LOCAL_RAM_SIZE_IN_BYTES : integer := 4*C_LOCAL_RAM_SIZE;
type LOCAL_MEMORY_T is array (0 to C_LOCAL_RAM_SIZE-1) of std_logic_vector(31 downto 0);
signal o_RAMAddr_ramp : std_logic_vector(0 to C_LOCAL_RAM_ADDRESS_WIDTH-1);
signal o_RAMData_ramp : std_logic_vector(0 to 31); -- ramp to local ram
signal i_RAMData_ramp : std_logic_vector(0 to 31); -- local ram to ramp
signal o_RAMWE_ramp : std_logic;
signal o_RAMAddr_reconos : std_logic_vector(0 to C_LOCAL_RAM_ADDRESS_WIDTH-1);
signal o_RAMAddr_reconos_2 : std_logic_vector(0 to 31);
signal o_RAMData_reconos : std_logic_vector(0 to 31);
signal o_RAMWE_reconos : std_logic;
signal i_RAMData_reconos : std_logic_vector(0 to 31);
signal osif_ctrl_signal : std_logic_vector(31 downto 0);
signal ignore : std_logic_vector(31 downto 0);
constant o_RAMAddr_max : std_logic_vector(0 to C_LOCAL_RAM_ADDRESS_WIDTH-1) := (others=>'1');
shared variable local_ram : LOCAL_MEMORY_T;
signal snd_comp_header : snd_comp_header_msg_t; -- common sound component header
signal sample_count : unsigned(15 downto 0) := to_unsigned(0, 16);
----------------------------------------------------------------
-- Component dependent signals
----------------------------------------------------------------
signal ramp_ce : std_logic; -- ramp clock enable (like a start/stop signal)
signal input_data : signed(31 downto 0);
signal ramp_data : signed(31 downto 0);
signal ramp_wave : signed(31 downto 0);
signal start : std_logic;
signal stop : std_logic;
signal refresh_state : integer range 0 to 2;
signal process_state : integer range 0 to 2;
signal incr : std_logic_vector(31 downto 0);
signal decr : std_logic_vector(31 downto 0);
signal incr_addr : std_logic_vector(31 downto 0);
signal decr_addr : std_logic_vector(31 downto 0);
----------------------------------------------------------------
-- OS Communication
----------------------------------------------------------------
constant RAMP_START : std_logic_vector(31 downto 0) := x"0000000F";
constant RAMP_EXIT : std_logic_vector(31 downto 0) := x"000000F0";
begin
-----------------------------------
-- Hard wirings
-----------------------------------
clk <= HWT_Clk;
rst <= HWT_Rst;
--o_RAMData_ramp <= std_logic_vector(ramp_wave);
o_RAMAddr_reconos(0 to C_LOCAL_RAM_ADDRESS_WIDTH-1) <= o_RAMAddr_reconos_2((32-C_LOCAL_RAM_ADDRESS_WIDTH) to 31);
-- ReconOS Stuff
osif_setup (
i_osif,
o_osif,
OSIF_FIFO_Sw2Hw_Data,
OSIF_FIFO_Sw2Hw_Fill,
OSIF_FIFO_Sw2Hw_Empty,
OSIF_FIFO_Hw2Sw_Rem,
OSIF_FIFO_Hw2Sw_Full,
OSIF_FIFO_Sw2Hw_RE,
OSIF_FIFO_Hw2Sw_Data,
OSIF_FIFO_Hw2Sw_WE
);
memif_setup (
i_memif,
o_memif,
MEMIF_FIFO_Mem2Hwt_Data,
MEMIF_FIFO_Mem2Hwt_Fill,
MEMIF_FIFO_Mem2Hwt_Empty,
MEMIF_FIFO_Hwt2Mem_Rem,
MEMIF_FIFO_Hwt2Mem_Full,
MEMIF_FIFO_Mem2Hwt_RE,
MEMIF_FIFO_Hwt2Mem_Data,
MEMIF_FIFO_Hwt2Mem_WE
);
ram_setup (
i_ram,
o_ram,
o_RAMAddr_reconos_2,
o_RAMWE_reconos,
o_RAMData_reconos,
i_RAMData_reconos
);
-- /ReconOS Stuff
ramp_INST : ramp
port map(
clk => clk,
rst => rst,
ce => ramp_ce,
incr => signed(incr),
incr2 => signed(decr),
rmp => ramp_data
);
local_ram_ctrl_1 : process (clk) is
begin
if (rising_edge(clk)) then
if (o_RAMWE_reconos = '1') then
local_ram(to_integer(unsigned(o_RAMAddr_reconos))) := o_RAMData_reconos;
else
i_RAMData_reconos <= local_ram(to_integer(unsigned(o_RAMAddr_reconos)));
end if;
end if;
end process;
local_ram_ctrl_2 : process (clk) is
begin
if (rising_edge(clk)) then
if (o_RAMWE_ramp = '1') then
local_ram(to_integer(unsigned(o_RAMAddr_ramp))) := o_RAMData_ramp;
else -- else needed, because ramp is consuming samples
i_RAMData_ramp <= local_ram(to_integer(unsigned(o_RAMAddr_ramp)));
end if;
end if;
end process;
ramp_CTRL_FSM_PROC : process (clk, rst, o_osif, o_memif) is
variable done : boolean;
begin
if rst = '1' then
osif_reset(o_osif);
memif_reset(o_memif);
ram_reset(o_ram);
state <= STATE_INIT;
sample_count <= to_unsigned(0, 16);
osif_ctrl_signal <= (others => '0');
ramp_ce <= '0';
incr <= (others => '0');
decr <= (others => '0');
o_RAMWE_ramp<= '0';
o_RAMAddr_ramp <= (others => '0');
refresh_state <= 0;
done := False;
elsif rising_edge(clk) then
case state is
-- INIT State gets the address of the header struct
when STATE_INIT =>
snd_comp_get_header(i_osif, o_osif, i_memif, o_memif, snd_comp_header, done);
if done then
incr_addr <= snd_comp_header.opt_arg_addr;
decr_addr <= std_logic_vector(unsigned(snd_comp_header.opt_arg_addr) + 4);
state <= STATE_WAITING;
end if;
when STATE_WAITING =>
-- Software process "Synthesizer" sends the start signal via mbox_start
osif_mbox_get(i_osif, o_osif, MBOX_START, osif_ctrl_signal, done);
if done then
if osif_ctrl_signal = RAMP_START then
sample_count <= to_unsigned(0, 16);
state <= STATE_REFRESH_INPUT;
elsif osif_ctrl_signal = RAMP_EXIT then
state <= STATE_EXIT;
end if;
end if;
when STATE_REFRESH_INPUT =>
-- Refresh your signals
case refresh_state is
when 0 =>
memif_read_word(i_memif, o_memif, incr_addr , incr, done);
if done then
refresh_state <= 1;
end if;
when 1 =>
memif_read_word(i_memif, o_memif, decr_addr , decr, done);
if done then
refresh_state <= 2;
end if;
when 2 =>
memif_read(i_ram, o_ram, i_memif, o_memif, snd_comp_header.source_addr, X"00000000", std_logic_vector(to_unsigned(C_LOCAL_RAM_SIZE_IN_BYTES,24)) ,done);
if done then
refresh_state <= 0;
state <= STATE_PROCESS;
end if;
end case;
when STATE_PROCESS =>
if sample_count < to_unsigned(C_MAX_SAMPLE_COUNT, 16) then
case process_state is
when 0 =>
ramp_ce <= '1';
process_state <= 1;
when 1 =>
o_RAMData_ramp <= std_logic_vector(resize(ramp_data * signed(i_RAMData_ramp), 32));
o_RAMWE_ramp <= '1';
ramp_ce <= '0';
process_state <= 0;
when 2 =>
o_RAMWE_ramp <= '0';
o_RAMAddr_ramp <= std_logic_vector(unsigned(o_RAMAddr_ramp) + 1);
sample_count <= sample_count + 1;
process_state <= 0;
end case;
else
-- Samples have been generated
o_RAMAddr_ramp <= (others => '0');
sample_count <= to_unsigned(0, 16);
state <= STATE_WRITE_MEM;
end if;
when STATE_WRITE_MEM =>
memif_write(i_ram, o_ram, i_memif, o_memif, X"00000000", snd_comp_header.dest_addr, std_logic_vector(to_unsigned(C_LOCAL_RAM_SIZE_IN_BYTES,24)), done);
if done then
state <= STATE_NOTIFY;
end if;
when STATE_NOTIFY =>
osif_mbox_put(i_osif, o_osif, MBOX_FINISH, snd_comp_header.dest_addr, ignore, done);
if done then
state <= STATE_WAITING;
end if;
when STATE_EXIT =>
osif_thread_exit(i_osif,o_osif);
end case;
end if;
end process;
end Behavioral;
-- ====================================
-- = RECONOS Function Library - Copy and Paste!
-- ====================================
-- osif_mbox_put(i_osif, o_osif, MBOX_NAME, SOURCESIGNAL, ignore, done);
-- osif_mbox_get(i_osif, o_osif, MBOX_NAME, TARGETSIGNAL, done);
-- Read from shared memory:
-- Speicherzugriffe:
-- Wortzugriff:
-- memif_read_word(i_memif, o_memif, addr, TARGETSIGNAL, done);
-- memif_write_word(i_memif, o_memif, addr, SOURCESIGNAL, done);
-- Die Laenge ist bei Speicherzugriffen Byte adressiert!
-- memif_read(i_ram, o_ram, i_memif, o_memif, SRC_ADDR std_logic_vector(31 downto 0);
-- dst_addr std_logic_vector(31 downto 0);
-- BYTES std_logic_vector(23 downto 0);
-- done);
-- memif_write(i_ram, o_ram, i_memif, o_memif,
-- src_addr : in std_logic_vector(31 downto 0),
-- dst_addr : in std_logic_vector(31 downto 0);
-- len : in std_logic_vector(23 downto 0);
-- done);
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
library std;
use std.textio.all;
entity memory_no_clk is
generic ( N : integer := 1);
port ( clk : in std_logic;
write_en: in std_logic;
addr_1 : in std_logic_vector (31 downto 0);
addr_2 : in std_logic_vector (31 downto 0);
data_w2 : in std_logic_vector (31 downto 0);
data_r1 : out std_logic_vector (31 downto 0);
data_r2 : out std_logic_vector (31 downto 0));
end memory_no_clk;
architecture Behavioral of memory_no_clk is
type type_mem_file is array(0 to N) of bit_vector(31 downto 0);
impure function load_from_mem (ram_file_name : in string) return type_mem_file is
file ram_file : text is in ram_file_name;
variable line_name : line;
variable ram_name : type_mem_file;
begin
for I in type_mem_file'range loop
readline (ram_file, line_name);
read (line_name, ram_name(I));
end loop;
return ram_name;
end function;
signal mem_file : type_mem_file := load_from_mem("push");
signal addr_1_tmp, addr_2_tmp : std_logic_vector (31 downto 0);
begin
write_port : process(clk)
begin
if rising_edge(clk) then
if write_en = '1' then
mem_file(conv_integer(addr_2)) <= to_bitvector(data_w2);
end if;
end if;
end process;
addr_1_tmp <= addr_1 when conv_integer(addr_1) < N and conv_integer(addr_1) > 0 else (others=>'0');
addr_2_tmp <= addr_2 when conv_integer(addr_2) < N and conv_integer(addr_2) > 0 else (others=>'0');
data_r1 <= to_stdlogicvector(mem_file(conv_integer(addr_1_tmp))) when conv_integer(addr_1) < N and conv_integer(addr_1) > 0 else (others=>'0');
data_r2 <= to_stdlogicvector(mem_file(conv_integer(addr_2_tmp))) when conv_integer(addr_2) < N and conv_integer(addr_2) > 0 else (others=>'0');
end Behavioral; |
library IEEE;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counters is
port(
sysclk : in std_logic;
foo_card : in std_logic;
wfoo0_baz : in std_logic;
wfoo0_blrb : in std_logic;
wfoo0_zz1pb : in std_logic;
wfoo0_turn : in std_logic_vector(31 downto 0);
debct_baz : in std_logic;
debct_blrb : in std_logic;
debct_zz1pb : in std_logic;
debct_bar : in std_logic;
debct_turn : in std_logic_vector(31 downto 0);
Z0_bar : in std_logic;
Z0_baz : in std_logic;
Z0_blrb : in std_logic;
Z0_zz1pb : in std_logic;
Z0_turn : in std_logic_vector(31 downto 0);
Y1_bar : in std_logic;
Y1_baz : in std_logic;
Y1_blrb : in std_logic;
Y1_zz1pb : in std_logic;
Y1_turn : in std_logic_vector(31 downto 0);
X2_bar : in std_logic;
X2_baz : in std_logic;
X2_blrb : in std_logic;
X2_zz1pb : in std_logic;
X2_turn : in std_logic_vector(31 downto 0);
W3_bar : in std_logic;
W3_baz : in std_logic;
W3_blrb : in std_logic;
W3_zz1pb : in std_logic;
W3_turn : in std_logic_vector(31 downto 0);
-- to engine block
Z0_cwm : out std_logic;
Z0 : out std_logic_vector(31 downto 0);
Y1_cwm : out std_logic;
Y1 : out std_logic_vector(31 downto 0);
X2_cwm : out std_logic;
X2 : out std_logic_vector(31 downto 0);
W3_cwm : out std_logic;
W3 : out std_logic_vector(31 downto 0);
wfoo0_cwm : out std_logic;
wfoo0_llwln : out std_logic_vector(31 downto 0);
debct_cwm : out std_logic;
debct_pull : out std_logic;
debct : out std_logic_vector(31 downto 0);
wdfilecardA2P : out std_logic
);
end counters;
architecture rtl of counters is
signal wfoo0_llwln_var : unsigned(31 downto 0);
signal debct_var : unsigned(31 downto 0);
signal Z0_var : unsigned(31 downto 0);
signal Y1_var : unsigned(31 downto 0);
signal X2_var : unsigned(31 downto 0);
signal W3_var : unsigned(31 downto 0);
signal main_wfoo0_cwm : std_logic;
signal do_q3p_Z0 : std_logic;
signal do_q3p_Y1 : std_logic;
signal do_q3p_X2 : std_logic;
signal do_q3p_W3 : std_logic;
signal do_q3p_wfoo0 : std_logic;
signal do_q3p_debct : std_logic;
signal Z0_cwm_i : std_logic;
signal Y1_cwm_i : std_logic;
signal X2_cwm_i : std_logic;
signal W3_cwm_i : std_logic;
signal debct_cwm_i : std_logic;
signal file_card_i : std_logic;
signal do_file_card_i : std_logic;
signal prev_do_file_card : std_logic;
begin
-----
-- form the outputs
wfoo0_llwln <= std_logic_vector(wfoo0_llwln_var);
debct <= std_logic_vector(debct_var);
Z0 <= std_logic_vector(Z0_var);
Y1 <= std_logic_vector(Y1_var);
X2 <= std_logic_vector(X2_var);
W3 <= std_logic_vector(W3_var);
Z0_cwm <= Z0_cwm_i;
Y1_cwm <= Y1_cwm_i;
X2_cwm <= X2_cwm_i;
W3_cwm <= W3_cwm_i;
debct_cwm <= debct_cwm_i;
wdfilecardA2P <= do_file_card_i;
LLWLNS :
process(foo_card, sysclk)
begin
if foo_card = '1' then
wfoo0_llwln_var <= (others => '0');
debct_var <= (others => '0');
Z0_var <= (others => '0');
Y1_var <= (others => '0');
X2_var <= (others => '0');
W3_var <= (others => '0');
wfoo0_cwm <= '0';
debct_cwm_i <= '0';
debct_pull <= '0';
Z0_cwm_i <= '0';
Y1_cwm_i <= '0';
X2_cwm_i <= '0';
W3_cwm_i <= '0';
main_wfoo0_cwm <= '0';
file_card_i <= '0';
do_q3p_wfoo0 <= '0';
do_file_card_i <= '0';
prev_do_file_card <= '0';
do_q3p_Z0 <= '0';
do_q3p_Y1 <= '0';
do_q3p_X2 <= '0';
do_q3p_W3 <= '0';
do_q3p_debct <= '0';
else
if sysclk'event and sysclk = '1' then
-- pull
debct_pull <= '0';
do_file_card_i <= '0';
----
-- wfoo0
if wfoo0_baz = '1' then
wfoo0_llwln_var <= unsigned(wfoo0_turn);
main_wfoo0_cwm <= '0';
if wfoo0_llwln_var = "00000000000000000000000000000000" then
do_q3p_wfoo0 <= '0';
else
do_q3p_wfoo0 <= '1';
end if;
else
if do_q3p_wfoo0 = '1' and wfoo0_blrb = '1' then
wfoo0_llwln_var <= wfoo0_llwln_var - 1;
if (wfoo0_llwln_var = "00000000000000000000000000000000") then
wfoo0_llwln_var <= unsigned(wfoo0_turn);
if main_wfoo0_cwm = '0' then
wfoo0_cwm <= '1';
main_wfoo0_cwm <= '1';
else
do_file_card_i <= '1';
do_q3p_wfoo0 <= '0';
end if;
end if;
end if;
end if;
if wfoo0_zz1pb = '0' then
wfoo0_cwm <= '0';
end if;
if Z0_baz = '1' then -- counter Baz
Z0_var <= unsigned(Z0_turn);
if Z0_turn = "00000000000000000000000000000000" then
do_q3p_Z0 <= '0';
else
do_q3p_Z0 <= '1';
end if;
else
if do_q3p_Z0 = '1' and Z0_blrb = '1' then
if Z0_bar = '0' then
if Z0_cwm_i = '0' then
if do_q3p_Z0 = '1' then
Z0_var <= Z0_var - 1;
if (Z0_var = "00000000000000000000000000000001") then
Z0_cwm_i <= '1';
do_q3p_Z0 <= '0';
end if;
end if;
end if;
else
Z0_var <= Z0_var - 1;
if (Z0_var = "00000000000000000000000000000000") then
Z0_cwm_i <= '1';
Z0_var <= unsigned(Z0_turn);
end if;
end if; -- Z0_bar
end if;
end if; -- Z0_blrb
if Z0_zz1pb = '0' then
Z0_cwm_i <= '0';
end if;
if Y1_baz = '1' then -- counter Baz
Y1_var <= unsigned(Y1_turn);
if Y1_turn = "00000000000000000000000000000000" then
do_q3p_Y1 <= '0';
else
do_q3p_Y1 <= '1';
end if;
elsif do_q3p_Y1 = '1' and Y1_blrb = '1' then
if Y1_bar = '0' then
if Y1_cwm_i = '0' then
if do_q3p_Y1 = '1' then
Y1_var <= Y1_var - 1;
if (Y1_var = "00000000000000000000000000000001") then
Y1_cwm_i <= '1';
do_q3p_Y1 <= '0';
end if;
end if;
end if;
else
Y1_var <= Y1_var - 1;
if (Y1_var = "00000000000000000000000000000000") then
Y1_cwm_i <= '1';
Y1_var <= unsigned(Y1_turn);
end if;
end if; -- Y1_bar
end if; -- Y1_blrb
if Y1_zz1pb = '0' then
Y1_cwm_i <= '0';
end if;
if X2_baz = '1' then -- counter Baz
X2_var <= unsigned(X2_turn);
if X2_turn = "00000000000000000000000000000000" then
do_q3p_X2 <= '0';
else
do_q3p_X2 <= '1';
end if;
elsif do_q3p_X2 = '1' and X2_blrb = '1' then
if X2_bar = '0' then
if X2_cwm_i = '0' then
if do_q3p_X2 = '1' then
X2_var <= X2_var - 1;
if (X2_var = "00000000000000000000000000000001") then
X2_cwm_i <= '1';
do_q3p_X2 <= '0';
end if;
end if;
end if;
else
X2_var <= X2_var - 1;
if (X2_var = "00000000000000000000000000000000") then --{
X2_cwm_i <= '1';
X2_var <= unsigned(X2_turn);
end if;
end if; --X2_bar
end if; -- X2_blrb
if X2_zz1pb = '0' then
X2_cwm_i <= '0';
end if;
if W3_baz = '1' then -- counter Baz
W3_var <= unsigned(W3_turn);
if W3_turn = "00000000000000000000000000000000" then
do_q3p_W3 <= '0';
else
do_q3p_W3 <= '1';
end if;
elsif do_q3p_W3 = '1' and W3_blrb = '1' then
if W3_bar = '0' then
if W3_cwm_i = '0'then
if do_q3p_W3 = '1' then
W3_var <= W3_var - 1;
if (W3_var = "00000000000000000000000000000001") then
W3_cwm_i <= '1';
do_q3p_W3 <= '0';
end if;
end if;
end if;
else
W3_var <= W3_var - 1;
if (W3_var = "00000000000000000000000000000000") then --{
W3_cwm_i <= '1';
W3_var <= unsigned(W3_turn);
end if;
end if; -- W3_bar
end if; -- W3_blrb
if W3_zz1pb = '0' then
W3_cwm_i <= '0';
end if;
if debct_baz = '1' then -- counter Baz
debct_var <= unsigned(debct_turn);
if debct_turn = "00000000000000000000000000000000" then
do_q3p_debct <= '0';
else
do_q3p_debct <= '1';
end if;
elsif do_q3p_debct = '1' and debct_blrb = '1' then
if debct_bar = '0' then
if debct_cwm_i = '0'then
if do_q3p_debct = '1' then
debct_var <= debct_var - 1;
if (debct_var = "00000000000000000000000000000001") then
debct_cwm_i <= '1';
debct_pull <= '1';
do_q3p_debct <= '0';
end if;
end if;
end if;
else
---- T
-- Continue
debct_var <= debct_var - 1;
-- ending
if (debct_var = "00000000000000000000000000000000") then --{
debct_cwm_i <= '1';
debct_pull <= '1';
debct_var <= unsigned(debct_turn);
end if;
end if; -- debct_bar
end if; -- debct_blrb
-- comment
if debct_zz1pb = '0' then
debct_cwm_i <= '0';
end if;
end if;
end if;
end process;
end rtl;
|
----------------------------------------------------------------------
-- Created by SmartDesign Thu Jun 22 17:22:48 2017
-- Version: v11.8 11.8.0.26
----------------------------------------------------------------------
----------------------------------------------------------------------
-- Libraries
----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library proasic3;
use proasic3.all;
library COREUART_LIB;
use COREUART_LIB.all;
use COREUART_LIB.CU_TOP_FPGA_UART_components.all;
----------------------------------------------------------------------
-- CU_TOP entity declaration
----------------------------------------------------------------------
entity CU_TOP is
-- Port list
port(
-- Inputs
CLK : in std_logic;
FPGA_UART_RX : in std_logic;
PWRONRESET : in std_logic;
-- Outputs
CUTTER : out std_logic;
FPGA_UART_TX : out std_logic;
L1_GPS_PWR : out std_logic;
LED1 : out std_logic;
LED2 : out std_logic;
MICRO_CLK : out std_logic;
PRESSURE_PWR : out std_logic;
SAT_PWR : out std_logic;
SENS_MEM_L5_PWR : out std_logic;
VHF_PWR : out std_logic
);
end CU_TOP;
----------------------------------------------------------------------
-- CU_TOP architecture body
----------------------------------------------------------------------
architecture RTL of CU_TOP is
----------------------------------------------------------------------
-- Component declarations
----------------------------------------------------------------------
-- CLKINT
component CLKINT
-- Port list
port(
-- Inputs
A : in std_logic;
-- Outputs
Y : out std_logic
);
end component;
-- CUTTER_PWM
component CUTTER_PWM
-- Port list
port(
-- Inputs
duty : in std_logic_vector(7 downto 0);
duty_wrt : in std_logic;
ena : in std_logic;
mclk : in std_logic;
reset : in std_logic;
-- Outputs
pwm_out : out std_logic_vector(0 to 0)
);
end component;
-- CU_TOP_FPGA_UART_COREUART - Actel:DirectCore:COREUART:5.6.102
component CU_TOP_FPGA_UART_COREUART
generic(
BAUD_VAL_FRCTN_EN : integer := 1 ;
FAMILY : integer := 15 ;
RX_FIFO : integer := 0 ;
RX_LEGACY_MODE : integer := 0 ;
TX_FIFO : integer := 0
);
-- Port list
port(
-- Inputs
BAUD_VAL : in std_logic_vector(12 downto 0);
BAUD_VAL_FRACTION : in std_logic_vector(2 downto 0);
BIT8 : in std_logic;
CLK : in std_logic;
CSN : in std_logic;
DATA_IN : in std_logic_vector(7 downto 0);
ODD_N_EVEN : in std_logic;
OEN : in std_logic;
PARITY_EN : in std_logic;
RESET_N : in std_logic;
RX : in std_logic;
WEN : in std_logic;
-- Outputs
DATA_OUT : out std_logic_vector(7 downto 0);
FRAMING_ERR : out std_logic;
OVERFLOW : out std_logic;
PARITY_ERR : out std_logic;
RXRDY : out std_logic;
TX : out std_logic;
TXRDY : out std_logic
);
end component;
-- OR2
component OR2
-- Port list
port(
-- Inputs
A : in std_logic;
B : in std_logic;
-- Outputs
Y : out std_logic
);
end component;
-- system_clock
component system_clock
-- Port list
port(
-- Inputs
mclk : in std_logic;
reset : in std_logic;
-- Outputs
m_time : out std_logic_vector(25 downto 0)
);
end component;
-- UART_reset_monitor
component UART_reset_monitor
-- Port list
port(
-- Inputs
data_in : in std_logic_vector(7 downto 0);
mclk : in std_logic;
reset_in : in std_logic;
txrdy : in std_logic;
-- Outputs
reset_out : out std_logic
);
end component;
-- WOLF_CONTROLLER
component WOLF_CONTROLLER
-- Port list
port(
-- Inputs
clk_1hz : in std_logic;
mclk : in std_logic;
reset : in std_logic;
uart_data_in : in std_logic_vector(7 downto 0);
uart_rxrdy : in std_logic;
uart_txrdy : in std_logic;
-- Outputs
cutter_en : out std_logic;
cutter_pwm_duty : out std_logic_vector(7 downto 0);
led1 : out std_logic;
led2 : out std_logic;
uart_baud_val : out std_logic_vector(12 downto 0);
uart_baud_val_frac : out std_logic_vector(2 downto 0);
uart_data_out : out std_logic_vector(7 downto 0);
uart_oen : out std_logic;
uart_wen : out std_logic
);
end component;
----------------------------------------------------------------------
-- Signal declarations
----------------------------------------------------------------------
signal CLKINT_0_Y : std_logic;
signal CLKINT_1_Y : std_logic;
signal CUTTER_net_0 : std_logic_vector(0 to 0);
signal FPGA_UART_DATA_OUT : std_logic_vector(7 downto 0);
signal FPGA_UART_TX_net_0 : std_logic;
signal FPGA_UART_TXRDY : std_logic;
signal LED1_net_0 : std_logic;
signal LED1_0 : std_logic;
signal LED1_2 : std_logic;
signal LED1_3 : std_logic;
signal LED2_net_0 : std_logic;
signal LED2_1 : std_logic_vector(25 to 25);
signal MICRO_CLK_net_0 : std_logic_vector(1 to 1);
signal OR2_0_Y : std_logic;
signal WOLF_CONTROLLER_cutter_pwm_duty : std_logic_vector(7 downto 0);
signal WOLF_CONTROLLER_uart_baud_val : std_logic_vector(12 downto 0);
signal WOLF_CONTROLLER_uart_baud_val_frac : std_logic_vector(2 downto 0);
signal WOLF_CONTROLLER_uart_data_out : std_logic_vector(7 downto 0);
signal CUTTER_net_1 : std_logic;
signal LED2_1_net_0 : std_logic;
signal FPGA_UART_TX_net_1 : std_logic;
signal LED1_3_net_0 : std_logic;
signal MICRO_CLK_net_1 : std_logic;
signal m_time_slice_0 : std_logic_vector(0 to 0);
signal m_time_slice_1 : std_logic_vector(10 to 10);
signal m_time_slice_2 : std_logic_vector(11 to 11);
signal m_time_slice_3 : std_logic_vector(12 to 12);
signal m_time_slice_4 : std_logic_vector(13 to 13);
signal m_time_slice_5 : std_logic_vector(14 to 14);
signal m_time_slice_6 : std_logic_vector(15 to 15);
signal m_time_slice_7 : std_logic_vector(16 to 16);
signal m_time_slice_8 : std_logic_vector(17 to 17);
signal m_time_slice_9 : std_logic_vector(18 to 18);
signal m_time_slice_10 : std_logic_vector(19 to 19);
signal m_time_slice_11 : std_logic_vector(20 to 20);
signal m_time_slice_12 : std_logic_vector(21 to 21);
signal m_time_slice_13 : std_logic_vector(22 to 22);
signal m_time_slice_14 : std_logic_vector(23 to 23);
signal m_time_slice_15 : std_logic_vector(24 to 24);
signal m_time_slice_16 : std_logic_vector(2 to 2);
signal m_time_slice_17 : std_logic_vector(3 to 3);
signal m_time_slice_18 : std_logic_vector(4 to 4);
signal m_time_slice_19 : std_logic_vector(5 to 5);
signal m_time_slice_20 : std_logic_vector(6 to 6);
signal m_time_slice_21 : std_logic_vector(7 to 7);
signal m_time_slice_22 : std_logic_vector(8 to 8);
signal m_time_slice_23 : std_logic_vector(9 to 9);
signal m_time_net_0 : std_logic_vector(25 downto 0);
----------------------------------------------------------------------
-- TiedOff Signals
----------------------------------------------------------------------
signal GND_net : std_logic;
signal VCC_net : std_logic;
----------------------------------------------------------------------
-- Inverted Signals
----------------------------------------------------------------------
signal RESET_N_IN_POST_INV0_0 : std_logic;
begin
----------------------------------------------------------------------
-- Constant assignments
----------------------------------------------------------------------
GND_net <= '0';
VCC_net <= '1';
----------------------------------------------------------------------
-- Inversions
----------------------------------------------------------------------
RESET_N_IN_POST_INV0_0 <= NOT OR2_0_Y;
----------------------------------------------------------------------
-- TieOff assignments
----------------------------------------------------------------------
L1_GPS_PWR <= '0';
VHF_PWR <= '0';
SENS_MEM_L5_PWR <= '0';
SAT_PWR <= '0';
PRESSURE_PWR <= '0';
----------------------------------------------------------------------
-- Top level output port assignments
----------------------------------------------------------------------
CUTTER_net_1 <= CUTTER_net_0(0);
CUTTER <= CUTTER_net_1;
LED2_1_net_0 <= LED2_1(25);
LED2 <= LED2_1_net_0;
FPGA_UART_TX_net_1 <= FPGA_UART_TX_net_0;
FPGA_UART_TX <= FPGA_UART_TX_net_1;
LED1_3_net_0 <= LED1_3;
LED1 <= LED1_3_net_0;
MICRO_CLK_net_1 <= MICRO_CLK_net_0(1);
MICRO_CLK <= MICRO_CLK_net_1;
----------------------------------------------------------------------
-- Slices assignments
----------------------------------------------------------------------
LED2_1(25) <= m_time_net_0(25);
MICRO_CLK_net_0(1) <= m_time_net_0(1);
m_time_slice_0(0) <= m_time_net_0(0);
m_time_slice_1(10) <= m_time_net_0(10);
m_time_slice_2(11) <= m_time_net_0(11);
m_time_slice_3(12) <= m_time_net_0(12);
m_time_slice_4(13) <= m_time_net_0(13);
m_time_slice_5(14) <= m_time_net_0(14);
m_time_slice_6(15) <= m_time_net_0(15);
m_time_slice_7(16) <= m_time_net_0(16);
m_time_slice_8(17) <= m_time_net_0(17);
m_time_slice_9(18) <= m_time_net_0(18);
m_time_slice_10(19) <= m_time_net_0(19);
m_time_slice_11(20) <= m_time_net_0(20);
m_time_slice_12(21) <= m_time_net_0(21);
m_time_slice_13(22) <= m_time_net_0(22);
m_time_slice_14(23) <= m_time_net_0(23);
m_time_slice_15(24) <= m_time_net_0(24);
m_time_slice_16(2) <= m_time_net_0(2);
m_time_slice_17(3) <= m_time_net_0(3);
m_time_slice_18(4) <= m_time_net_0(4);
m_time_slice_19(5) <= m_time_net_0(5);
m_time_slice_20(6) <= m_time_net_0(6);
m_time_slice_21(7) <= m_time_net_0(7);
m_time_slice_22(8) <= m_time_net_0(8);
m_time_slice_23(9) <= m_time_net_0(9);
----------------------------------------------------------------------
-- Component instances
----------------------------------------------------------------------
-- CLKINT_0
CLKINT_0 : CLKINT
port map(
-- Inputs
A => CLK,
-- Outputs
Y => CLKINT_0_Y
);
-- CLKINT_1
CLKINT_1 : CLKINT
port map(
-- Inputs
A => PWRONRESET,
-- Outputs
Y => CLKINT_1_Y
);
-- CUTTER_PWM_inst_0
CUTTER_PWM_inst_0 : CUTTER_PWM
port map(
-- Inputs
mclk => CLKINT_0_Y,
reset => OR2_0_Y,
ena => LED2_net_0,
duty_wrt => VCC_net,
duty => WOLF_CONTROLLER_cutter_pwm_duty,
-- Outputs
pwm_out => CUTTER_net_0
);
-- FPGA_UART - Actel:DirectCore:COREUART:5.6.102
FPGA_UART : CU_TOP_FPGA_UART_COREUART
generic map(
BAUD_VAL_FRCTN_EN => ( 1 ),
FAMILY => ( 15 ),
RX_FIFO => ( 0 ),
RX_LEGACY_MODE => ( 0 ),
TX_FIFO => ( 0 )
)
port map(
-- Inputs
BIT8 => VCC_net,
CLK => CLKINT_0_Y,
CSN => GND_net,
ODD_N_EVEN => VCC_net,
OEN => LED1_3,
PARITY_EN => GND_net,
RESET_N => RESET_N_IN_POST_INV0_0,
RX => FPGA_UART_RX,
WEN => LED1_2,
BAUD_VAL => WOLF_CONTROLLER_uart_baud_val,
DATA_IN => WOLF_CONTROLLER_uart_data_out,
BAUD_VAL_FRACTION => WOLF_CONTROLLER_uart_baud_val_frac,
-- Outputs
OVERFLOW => OPEN,
PARITY_ERR => OPEN,
RXRDY => LED1_0,
TX => FPGA_UART_TX_net_0,
TXRDY => FPGA_UART_TXRDY,
FRAMING_ERR => OPEN,
DATA_OUT => FPGA_UART_DATA_OUT
);
-- OR2_0
OR2_0 : OR2
port map(
-- Inputs
A => CLKINT_1_Y,
B => LED1_net_0,
-- Outputs
Y => OR2_0_Y
);
-- system_clock_inst_0
system_clock_inst_0 : system_clock
port map(
-- Inputs
mclk => CLKINT_0_Y,
reset => OR2_0_Y,
-- Outputs
m_time => m_time_net_0
);
-- UART_reset_monitor_inst_0
UART_reset_monitor_inst_0 : UART_reset_monitor
port map(
-- Inputs
mclk => CLKINT_0_Y,
reset_in => CLKINT_1_Y,
txrdy => FPGA_UART_TXRDY,
data_in => FPGA_UART_DATA_OUT,
-- Outputs
reset_out => LED1_net_0
);
-- WOLF_CONTROLLER_inst_0
WOLF_CONTROLLER_inst_0 : WOLF_CONTROLLER
port map(
-- Inputs
mclk => CLKINT_0_Y,
clk_1hz => LED2_1(25),
reset => OR2_0_Y,
uart_txrdy => FPGA_UART_TXRDY,
uart_rxrdy => LED1_0,
uart_data_in => FPGA_UART_DATA_OUT,
-- Outputs
cutter_en => LED2_net_0,
uart_wen => LED1_2,
uart_oen => LED1_3,
led1 => OPEN,
led2 => OPEN,
cutter_pwm_duty => WOLF_CONTROLLER_cutter_pwm_duty,
uart_data_out => WOLF_CONTROLLER_uart_data_out,
uart_baud_val => WOLF_CONTROLLER_uart_baud_val,
uart_baud_val_frac => WOLF_CONTROLLER_uart_baud_val_frac
);
end RTL;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer: fpgaddicted (Stefan Naco)
--
-- Create Date: 17:26:19 04/27/2017
-- Design Name:
-- Module Name: animation_engine - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity animation_engine is
Port ( t_left,t_right,t_brake,t_alarm : in STD_LOGIC;
clk,reset : in STD_LOGIC;
led_left,led_right : out STD_LOGIC_VECTOR (2 downto 0);
led_stop : out STD_LOGIC_VECTOR (1 downto 0));
end animation_engine;
architecture Port_map of animation_engine is
COMPONENT turnsignals_anim
PORT(
clk : IN std_logic;
reset : IN std_logic;
en : IN std_logic;
led_out : OUT std_logic_vector(2 downto 0)
);
END COMPONENT;
COMPONENT alarm_anim
PORT(
clk : IN std_logic;
reset : IN std_logic;
en : IN std_logic;
led_out : OUT std_logic_vector(2 downto 0)
);
END COMPONENT;
COMPONENT brake_anim
PORT(
clk : IN std_logic;
reset : IN std_logic;
en : IN std_logic;
led_out : OUT std_logic_vector(1 downto 0)
);
END COMPONENT;
COMPONENT signal_mux
PORT(
sel : in STD_LOGIC;
sig_out : out STD_LOGIC_VECTOR (2 downto 0);
sig_turn : in STD_LOGIC_VECTOR (2 downto 0);
sig_alarm : in STD_LOGIC_VECTOR (2 downto 0)
);
END COMPONENT;
signal led_signal_R: std_logic_vector (2 downto 0);
signal led_signal_L : std_logic_vector (2 downto 0);
signal led_signal_A : std_logic_vector (2 downto 0);
begin
RIGHT: turnsignals_anim PORT MAP (
clk => clk,
reset => reset,
en => t_right,
led_out => led_signal_R
);
LEFT: turnsignals_anim PORT MAP (
clk => clk,
reset => reset,
en => t_left,
led_out => led_signal_L
);
ALARM : alarm_anim PORT MAP (
clk=> clk,
reset => reset,
en => t_alarm,
led_out => led_signal_A
);
BRAKE : brake_anim PORT MAP (
clk=> clk,
reset => reset,
en => t_brake,
led_out => led_stop
);
ALARM_CONTROL_L : signal_mux PORT MAP (
sel => t_alarm,
sig_turn => led_signal_L,
sig_alarm => led_signal_A,
sig_out => led_left
);
ALARM_CONTROL_R : signal_mux PORT MAP (
sel => t_alarm,
sig_turn => led_signal_R,
sig_alarm => led_signal_A,
sig_out => led_right
);
end Port_map;
|
--*****************************************************************************
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: 3.92
-- \ \ Application: MIG
-- / / Filename: phy_rddata_sync.vhd
-- /___/ /\ Date Last Modified: $Date: 2011/06/02 07:18:13 $
-- \ \ / \ Date Created: Aug 03 2009
-- \___\/\___\
--
--Device: Virtex-6
--Design Name: DDR3 SDRAM
--Purpose:
-- Synchronization of captured read data along with appropriately delayed
-- valid signal (both in clk_rsync domain) to MC/PHY rdlvl logic clock (clk)
--Reference:
--Revision History:
--*****************************************************************************
--******************************************************************************
--**$Id: phy_rddata_sync.vhd,v 1.1 2011/06/02 07:18:13 mishra Exp $
--**$Date: 2011/06/02 07:18:13 $
--**$Author: mishra $
--**$Revision: 1.1 $
--**$Source: /devl/xcs/repo/env/Databases/ip/src2/O/mig_v3_9/data/dlib/virtex6/ddr3_sdram/vhdl/rtl/phy/phy_rddata_sync.vhd,v $
--******************************************************************************
library unisim;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity phy_rddata_sync is
generic (
TCQ : integer := 100; -- clk->out delay (sim only)
DQ_WIDTH : integer := 64; -- # of DQ (data)
DQS_WIDTH : integer := 8; -- # of DQS (strobe)
DRAM_WIDTH : integer := 8; -- # # of DQ per DQS
nDQS_COL0 : integer := 4; -- # DQS groups in I/O column #1
nDQS_COL1 : integer := 4; -- # DQS groups in I/O column #2
nDQS_COL2 : integer := 4; -- # DQS groups in I/O column #3
nDQS_COL3 : integer := 4; -- # DQS groups in I/O column #4
DQS_LOC_COL0 : std_logic_vector(143 downto 0) := X"11100F0E0D0C0B0A09080706050403020100";
-- DQS grps in col #1
DQS_LOC_COL1 : std_logic_vector(143 downto 0) := X"000000000000000000000000000000000000";
-- DQS grps in col #2
DQS_LOC_COL2 : std_logic_vector(143 downto 0) := X"000000000000000000000000000000000000";
-- DQS grps in col #3
DQS_LOC_COL3 : std_logic_vector(143 downto 0) := X"000000000000000000000000000000000000"
);
port (
clk : in std_logic;
clk_rsync : in std_logic_vector(3 downto 0);
rst_rsync : in std_logic_vector(3 downto 0);
-- Captured data in resync clock domain
rd_data_rise0 : in std_logic_vector((DQ_WIDTH-1) downto 0);
rd_data_fall0 : in std_logic_vector((DQ_WIDTH-1) downto 0);
rd_data_rise1 : in std_logic_vector((DQ_WIDTH-1) downto 0);
rd_data_fall1 : in std_logic_vector((DQ_WIDTH-1) downto 0);
rd_dqs_rise0 : in std_logic_vector((DQS_WIDTH-1) downto 0);
rd_dqs_fall0 : in std_logic_vector((DQS_WIDTH-1) downto 0);
rd_dqs_rise1 : in std_logic_vector((DQS_WIDTH-1) downto 0);
rd_dqs_fall1 : in std_logic_vector((DQS_WIDTH-1) downto 0);
-- Synchronized data/valid back to MC/PHY rdlvl logic
dfi_rddata : out std_logic_vector((4*DQ_WIDTH-1) downto 0);
dfi_rd_dqs : out std_logic_vector((4*DQS_WIDTH-1) downto 0)
);
end phy_rddata_sync;
architecture trans of phy_rddata_sync is
function CALC_COL0_VECT_WIDTH return integer is
begin
if (nDQS_COL0 > 0) then
return (nDQS_COL0);
else
return 1;
end if;
end function CALC_COL0_VECT_WIDTH;
function CALC_COL1_VECT_WIDTH return integer is
begin
if (nDQS_COL1 > 0) then
return (nDQS_COL1);
else
return 1;
end if;
end function CALC_COL1_VECT_WIDTH;
function CALC_COL2_VECT_WIDTH return integer is
begin
if (nDQS_COL2 > 0) then
return (nDQS_COL2);
else
return 1;
end if;
end function CALC_COL2_VECT_WIDTH;
function CALC_COL3_VECT_WIDTH return integer is
begin
if (nDQS_COL3 > 0) then
return (nDQS_COL3);
else
return 1;
end if;
end function CALC_COL3_VECT_WIDTH;
-- Ensure nonzero width for certain buses to prevent syntax errors
-- during compile in the event they are not used (e.g. buses that have to
-- do with column #2 in a single column design never get used, although
-- those buses still will get declared)
constant COL0_VECT_WIDTH : integer := CALC_COL0_VECT_WIDTH;
constant COL1_VECT_WIDTH : integer := CALC_COL1_VECT_WIDTH;
constant COL2_VECT_WIDTH : integer := CALC_COL2_VECT_WIDTH;
constant COL3_VECT_WIDTH : integer := CALC_COL3_VECT_WIDTH;
signal data_c0 : std_logic_vector((4*DRAM_WIDTH*COL0_VECT_WIDTH-1) downto 0);
signal data_c1 : std_logic_vector((4*DRAM_WIDTH*COL1_VECT_WIDTH-1) downto 0);
signal data_c2 : std_logic_vector((4*DRAM_WIDTH*COL2_VECT_WIDTH-1) downto 0);
signal data_c3 : std_logic_vector((4*DRAM_WIDTH*COL3_VECT_WIDTH-1) downto 0);
signal data_fall0_sync : std_logic_vector((DQ_WIDTH-1) downto 0);
signal data_fall1_sync : std_logic_vector((DQ_WIDTH-1) downto 0);
signal data_rise0_sync : std_logic_vector((DQ_WIDTH-1) downto 0);
signal data_rise1_sync : std_logic_vector((DQ_WIDTH-1) downto 0);
signal data_sync_c0 : std_logic_vector((4*DRAM_WIDTH*COL0_VECT_WIDTH-1) downto 0);
signal data_sync_c1 : std_logic_vector((4*DRAM_WIDTH*COL1_VECT_WIDTH-1) downto 0);
signal data_sync_c2 : std_logic_vector((4*DRAM_WIDTH*COL2_VECT_WIDTH-1) downto 0);
signal data_sync_c3 : std_logic_vector((4*DRAM_WIDTH*COL3_VECT_WIDTH-1) downto 0);
signal dqs_c0 : std_logic_vector((4*COL0_VECT_WIDTH-1) downto 0);
signal dqs_c1 : std_logic_vector((4*COL1_VECT_WIDTH-1) downto 0);
signal dqs_c2 : std_logic_vector((4*COL2_VECT_WIDTH-1) downto 0);
signal dqs_c3 : std_logic_vector((4*COL3_VECT_WIDTH-1) downto 0);
signal dqs_fall0_sync : std_logic_vector((DQS_WIDTH-1) downto 0);
signal dqs_fall1_sync : std_logic_vector((DQS_WIDTH-1) downto 0);
signal dqs_rise0_sync : std_logic_vector((DQS_WIDTH-1) downto 0);
signal dqs_rise1_sync : std_logic_vector((DQS_WIDTH-1) downto 0);
signal dqs_sync_c0 : std_logic_vector((4*COL0_VECT_WIDTH-1) downto 0);
signal dqs_sync_c1 : std_logic_vector((4*COL1_VECT_WIDTH-1) downto 0);
signal dqs_sync_c2 : std_logic_vector((4*COL2_VECT_WIDTH-1) downto 0);
signal dqs_sync_c3 : std_logic_vector((4*COL3_VECT_WIDTH-1) downto 0);
-- Declare the intermediate signals for the inputs of circ buffer
signal wdata_xhdl3 : std_logic_vector((4*COL3_VECT_WIDTH)+(4*DRAM_WIDTH*COL3_VECT_WIDTH)-1 downto 0);
signal rdata_xhdl3 : std_logic_vector((4*COL3_VECT_WIDTH)+(4*DRAM_WIDTH*COL3_VECT_WIDTH)-1 downto 0);
signal wdata_xhdl2 : std_logic_vector((4*COL2_VECT_WIDTH)+(4*DRAM_WIDTH*COL2_VECT_WIDTH)-1 downto 0);
signal rdata_xhdl2 : std_logic_vector((4*COL2_VECT_WIDTH)+(4*DRAM_WIDTH*COL2_VECT_WIDTH)-1 downto 0);
signal wdata_xhdl1 : std_logic_vector((4*COL1_VECT_WIDTH)+(4*DRAM_WIDTH*COL1_VECT_WIDTH)-1 downto 0);
signal rdata_xhdl1 : std_logic_vector((4*COL1_VECT_WIDTH)+(4*DRAM_WIDTH*COL1_VECT_WIDTH)-1 downto 0);
signal wdata_xhdl0 : std_logic_vector((4*COL0_VECT_WIDTH)+(4*DRAM_WIDTH*COL0_VECT_WIDTH)-1 downto 0);
signal rdata_xhdl0 : std_logic_vector((4*COL0_VECT_WIDTH)+(4*DRAM_WIDTH*COL0_VECT_WIDTH)-1 downto 0);
--------- circ buffer component ---------
component circ_buffer
generic (
TCQ : integer := 100;
DATA_WIDTH : integer := 1;
BUF_DEPTH : integer := 5 -- valid values are 5, 6, 7, and 8
);
port (
rdata : out std_logic_vector(DATA_WIDTH - 1 downto 0);
wdata : in std_logic_vector(DATA_WIDTH - 1 downto 0);
rclk : in std_logic;
wclk : in std_logic;
rst : in std_logic
);
end component;
begin
--***************************************************************************
-- Synchronization of both data and active/valid signal from clk_rsync to
-- clk domain
-- NOTES:
-- 1. For now, assume both rddata_valid0 and rddata_valid1 are driven at
-- same time. PHY returns data aligned in this manner
-- 2. Circular buffer implementation is preliminary (i.e. shortcuts have
-- been taken!). Will later need some sort of calibration.
-- - Substitute this with enhanced circular buffer design for
-- release (5 deep design)
-- 3. Up to 4 circular buffers are used, one for each CLK_RSYNC[x] domain.
-- 4. RD_ACTIVE synchronized to CLK_RSYNC[0] circular buffer. This is
-- TEMPORARY only. For release, do not need this - RD_ACTIVE will
-- remain totally in the
-- A single circular buffer is used for the entire data bus. This will
-- be an issue in H/W - will need to examine this based on clock
-- frequency, and skew matching achievable in H/W.
--***************************************************************************
gen_c0: if(nDQS_COL0 > 0 ) generate
begin
gen_loop_c0: for c0_i in 0 to (nDQS_COL0-1) generate
begin
-- Steer data to circular buffer - merge FALL/RISE data into single bus
process (rd_dqs_fall0, rd_dqs_fall1, rd_dqs_rise0,
rd_dqs_rise1)
begin
dqs_c0(4*(c0_i+1)-1 downto 4*(c0_i+1)-4) <= rd_dqs_fall1(TO_INTEGER(unsigned(DQS_LOC_COL0((8*(c0_i+1))-1 downto 8*c0_i)))) &
rd_dqs_rise1(TO_INTEGER(unsigned(DQS_LOC_COL0((8*(c0_i+1))-1 downto 8*c0_i)))) &
rd_dqs_fall0(TO_INTEGER(unsigned(DQS_LOC_COL0((8*(c0_i+1))-1 downto 8*c0_i)))) &
rd_dqs_rise0(TO_INTEGER(unsigned(DQS_LOC_COL0((8*(c0_i+1))-1 downto 8*c0_i))));
end process;
process (rd_data_rise0, rd_data_rise1, rd_data_fall0,
rd_data_fall1)
begin
data_c0(4*DRAM_WIDTH*(c0_i+1)-1 downto 4*DRAM_WIDTH*c0_i) <=
rd_data_fall1(DRAM_WIDTH*(TO_INTEGER(unsigned(DQS_LOC_COL0((8*(c0_i+1))-1 downto 8*c0_i)))+1) - 1 downto DRAM_WIDTH*(TO_INTEGER(unsigned(DQS_LOC_COL0((8*(c0_i+1))-1 downto 8*c0_i))) )) &
rd_data_rise1(DRAM_WIDTH*(TO_INTEGER(unsigned(DQS_LOC_COL0((8*(c0_i+1))-1 downto 8*c0_i)))+1) - 1 downto DRAM_WIDTH*(TO_INTEGER(unsigned(DQS_LOC_COL0((8*(c0_i+1))-1 downto 8*c0_i))) )) &
rd_data_fall0(DRAM_WIDTH*(TO_INTEGER(unsigned(DQS_LOC_COL0((8*(c0_i+1))-1 downto 8*c0_i)))+1) - 1 downto DRAM_WIDTH*(TO_INTEGER(unsigned(DQS_LOC_COL0((8*(c0_i+1))-1 downto 8*c0_i))) )) &
rd_data_rise0(DRAM_WIDTH*(TO_INTEGER(unsigned(DQS_LOC_COL0((8*(c0_i+1))-1 downto 8*c0_i)))+1) - 1 downto DRAM_WIDTH*(TO_INTEGER(unsigned(DQS_LOC_COL0((8*(c0_i+1))-1 downto 8*c0_i))) ));
end process;
-- Reassemble data from circular buffer
process (dqs_sync_c0(4*c0_i), dqs_sync_c0(4*c0_i+1),
dqs_sync_c0(4*c0_i+2), dqs_sync_c0(4*c0_i+3))
begin
dqs_fall1_sync(TO_INTEGER(unsigned(DQS_LOC_COL0((8*(c0_i+1))-1 downto 8*c0_i)))) <= dqs_sync_c0(4*c0_i+3);
dqs_rise1_sync(TO_INTEGER(unsigned(DQS_LOC_COL0((8*(c0_i+1))-1 downto 8*c0_i)))) <= dqs_sync_c0(4*c0_i+2);
dqs_fall0_sync(TO_INTEGER(unsigned(DQS_LOC_COL0((8*(c0_i+1))-1 downto 8*c0_i)))) <= dqs_sync_c0(4*c0_i+1);
dqs_rise0_sync(TO_INTEGER(unsigned(DQS_LOC_COL0((8*(c0_i+1))-1 downto 8*c0_i)))) <= dqs_sync_c0(4*c0_i+0);
end process;
process (data_sync_c0((4*DRAM_WIDTH*c0_i)+DRAM_WIDTH-1 downto 4*DRAM_WIDTH*c0_i),
data_sync_c0((4*DRAM_WIDTH*c0_i)+2*DRAM_WIDTH-1 downto 4*DRAM_WIDTH*c0_i + DRAM_WIDTH),
data_sync_c0((4*DRAM_WIDTH*c0_i)+3*DRAM_WIDTH-1 downto 4*DRAM_WIDTH*c0_i + 2*DRAM_WIDTH),
data_sync_c0((4*DRAM_WIDTH*c0_i)+4*DRAM_WIDTH-1 downto 4*DRAM_WIDTH*c0_i + 3*DRAM_WIDTH)
)
begin
data_fall1_sync(DRAM_WIDTH*(TO_INTEGER(unsigned(DQS_LOC_COL0((8*(c0_i+1))-1 downto 8*c0_i)))+1) - 1 downto DRAM_WIDTH*(TO_INTEGER(unsigned(DQS_LOC_COL0((8*(c0_i+1))-1 downto 8*c0_i)))))
<= data_sync_c0((4*DRAM_WIDTH*c0_i)+4*DRAM_WIDTH-1 downto 4*DRAM_WIDTH*c0_i + 3*DRAM_WIDTH);
data_rise1_sync(DRAM_WIDTH*(TO_INTEGER(unsigned(DQS_LOC_COL0((8*(c0_i+1))-1 downto 8*c0_i)))+1) - 1 downto DRAM_WIDTH*(TO_INTEGER(unsigned(DQS_LOC_COL0((8*(c0_i+1))-1 downto 8*c0_i)))))
<= data_sync_c0((4*DRAM_WIDTH*c0_i)+3*DRAM_WIDTH-1 downto 4*DRAM_WIDTH*c0_i + 2*DRAM_WIDTH);
data_fall0_sync(DRAM_WIDTH*(TO_INTEGER(unsigned(DQS_LOC_COL0((8*(c0_i+1))-1 downto 8*c0_i)))+1) - 1 downto DRAM_WIDTH*(TO_INTEGER(unsigned(DQS_LOC_COL0((8*(c0_i+1))-1 downto 8*c0_i)))))
<= data_sync_c0((4*DRAM_WIDTH*c0_i)+2*DRAM_WIDTH-1 downto 4*DRAM_WIDTH*c0_i + 1*DRAM_WIDTH);
data_rise0_sync(DRAM_WIDTH*(TO_INTEGER(unsigned(DQS_LOC_COL0((8*(c0_i+1))-1 downto 8*c0_i)))+1) - 1 downto DRAM_WIDTH*(TO_INTEGER(unsigned(DQS_LOC_COL0((8*(c0_i+1))-1 downto 8*c0_i)))))
<= data_sync_c0((4*DRAM_WIDTH*c0_i)+DRAM_WIDTH-1 downto 4*DRAM_WIDTH*c0_i);
end process;
end generate;
u_rddata_sync_c0: circ_buffer
generic map (
TCQ => TCQ,
DATA_WIDTH => (4*nDQS_COL0)+(4*DRAM_WIDTH*nDQS_COL0),
BUF_DEPTH => 6
)
port map (
rclk => clk,
wclk => clk_rsync(0),
rst => rst_rsync(0),
wdata => wdata_xhdl0,
rdata => rdata_xhdl0
);
end generate;
gen_c1: if (nDQS_COL1 > 0) generate
begin
gen_loop_c1: for c1_i in 0 to (nDQS_COL1-1) generate
begin
-- Steer data to circular buffer - merge FALL/RISE data into single bus
process (rd_dqs_fall0, rd_dqs_fall1, rd_dqs_rise0,
rd_dqs_rise1)
begin
dqs_c1(4*(c1_i+1)-1 downto 4*(c1_i+1)-4) <= rd_dqs_fall1(TO_INTEGER(unsigned(DQS_LOC_COL1((8*(c1_i+1))-1 downto 8*c1_i)))) &
rd_dqs_rise1(TO_INTEGER(unsigned(DQS_LOC_COL1((8*(c1_i+1))-1 downto 8*c1_i)))) &
rd_dqs_fall0(TO_INTEGER(unsigned(DQS_LOC_COL1((8*(c1_i+1))-1 downto 8*c1_i)))) &
rd_dqs_rise0(TO_INTEGER(unsigned(DQS_LOC_COL1((8*(c1_i+1))-1 downto 8*c1_i))));
end process;
process (rd_data_rise0, rd_data_rise1, rd_data_fall0,
rd_data_fall1)
begin
data_c1(4*DRAM_WIDTH*(c1_i+1)-1 downto 4*DRAM_WIDTH*c1_i) <=
rd_data_fall1(DRAM_WIDTH*(TO_INTEGER(unsigned(DQS_LOC_COL1((8*(c1_i+1))-1 downto 8*c1_i)))+1) - 1 downto DRAM_WIDTH*(TO_INTEGER(unsigned(DQS_LOC_COL1((8*(c1_i+1))-1 downto 8*c1_i))) )) &
rd_data_rise1(DRAM_WIDTH*(TO_INTEGER(unsigned(DQS_LOC_COL1((8*(c1_i+1))-1 downto 8*c1_i)))+1) - 1 downto DRAM_WIDTH*(TO_INTEGER(unsigned(DQS_LOC_COL1((8*(c1_i+1))-1 downto 8*c1_i))) )) &
rd_data_fall0(DRAM_WIDTH*(TO_INTEGER(unsigned(DQS_LOC_COL1((8*(c1_i+1))-1 downto 8*c1_i)))+1) - 1 downto DRAM_WIDTH*(TO_INTEGER(unsigned(DQS_LOC_COL1((8*(c1_i+1))-1 downto 8*c1_i))) )) &
rd_data_rise0(DRAM_WIDTH*(TO_INTEGER(unsigned(DQS_LOC_COL1((8*(c1_i+1))-1 downto 8*c1_i)))+1) - 1 downto DRAM_WIDTH*(TO_INTEGER(unsigned(DQS_LOC_COL1((8*(c1_i+1))-1 downto 8*c1_i))) ));
end process;
-- Reassemble data from circular buffer
process (dqs_sync_c1(4*c1_i), dqs_sync_c1(4*c1_i+1),
dqs_sync_c1(4*c1_i+2), dqs_sync_c1(4*c1_i+3))
begin
dqs_fall1_sync(TO_INTEGER(unsigned(DQS_LOC_COL1((8*(c1_i+1))-1 downto 8*c1_i)))) <= dqs_sync_c1(4*c1_i+3);
dqs_rise1_sync(TO_INTEGER(unsigned(DQS_LOC_COL1((8*(c1_i+1))-1 downto 8*c1_i)))) <= dqs_sync_c1(4*c1_i+2);
dqs_fall0_sync(TO_INTEGER(unsigned(DQS_LOC_COL1((8*(c1_i+1))-1 downto 8*c1_i)))) <= dqs_sync_c1(4*c1_i+1);
dqs_rise0_sync(TO_INTEGER(unsigned(DQS_LOC_COL1((8*(c1_i+1))-1 downto 8*c1_i)))) <= dqs_sync_c1(4*c1_i+0);
end process;
process (data_sync_c1((4*DRAM_WIDTH*c1_i)+DRAM_WIDTH-1 downto 4*DRAM_WIDTH*c1_i),
data_sync_c1((4*DRAM_WIDTH*c1_i)+2*DRAM_WIDTH-1 downto 4*DRAM_WIDTH*c1_i + DRAM_WIDTH),
data_sync_c1((4*DRAM_WIDTH*c1_i)+3*DRAM_WIDTH-1 downto 4*DRAM_WIDTH*c1_i + 2*DRAM_WIDTH),
data_sync_c1((4*DRAM_WIDTH*c1_i)+4*DRAM_WIDTH-1 downto 4*DRAM_WIDTH*c1_i + 3*DRAM_WIDTH)
)
begin
data_fall1_sync(DRAM_WIDTH*(TO_INTEGER(unsigned(DQS_LOC_COL1((8*(c1_i+1))-1 downto 8*c1_i)))+1) - 1 downto DRAM_WIDTH*(TO_INTEGER(unsigned(DQS_LOC_COL1((8*(c1_i+1))-1 downto 8*c1_i)))))
<= data_sync_c1((4*DRAM_WIDTH*c1_i)+4*DRAM_WIDTH-1 downto 4*DRAM_WIDTH*c1_i + 3*DRAM_WIDTH);
data_rise1_sync(DRAM_WIDTH*(TO_INTEGER(unsigned(DQS_LOC_COL1((8*(c1_i+1))-1 downto 8*c1_i)))+1) - 1 downto DRAM_WIDTH*(TO_INTEGER(unsigned(DQS_LOC_COL1((8*(c1_i+1))-1 downto 8*c1_i)))))
<= data_sync_c1((4*DRAM_WIDTH*c1_i)+3*DRAM_WIDTH-1 downto 4*DRAM_WIDTH*c1_i + 2*DRAM_WIDTH);
data_fall0_sync(DRAM_WIDTH*(TO_INTEGER(unsigned(DQS_LOC_COL1((8*(c1_i+1))-1 downto 8*c1_i)))+1) - 1 downto DRAM_WIDTH*(TO_INTEGER(unsigned(DQS_LOC_COL1((8*(c1_i+1))-1 downto 8*c1_i)))))
<= data_sync_c1((4*DRAM_WIDTH*c1_i)+2*DRAM_WIDTH-1 downto 4*DRAM_WIDTH*c1_i + 1*DRAM_WIDTH);
data_rise0_sync(DRAM_WIDTH*(TO_INTEGER(unsigned(DQS_LOC_COL1((8*(c1_i+1))-1 downto 8*c1_i)))+1) - 1 downto DRAM_WIDTH*(TO_INTEGER(unsigned(DQS_LOC_COL1((8*(c1_i+1))-1 downto 8*c1_i)))))
<= data_sync_c1((4*DRAM_WIDTH*c1_i)+DRAM_WIDTH-1 downto 4*DRAM_WIDTH*c1_i);
end process;
end generate;
u_rddata_sync_c1: circ_buffer
generic map (
TCQ => TCQ,
DATA_WIDTH => (4*nDQS_COL1)+(4*DRAM_WIDTH*nDQS_COL1),
BUF_DEPTH => 6
)
port map (
rclk => clk,
wclk => clk_rsync(1),
rst => rst_rsync(1),
wdata => wdata_xhdl1,
rdata => rdata_xhdl1
);
end generate;
gen_c2: if (nDQS_COL2 > 0) generate
begin
gen_loop_c2: for c2_i in 0 to (nDQS_COL2-1) generate
begin
-- Steer data to circular buffer - merge FALL/RISE data into single bus
process (rd_dqs_fall0, rd_dqs_fall1, rd_dqs_rise0,
rd_dqs_rise1)
begin
dqs_c2(4*(c2_i+1)-1 downto 4*(c2_i+1)-4) <= rd_dqs_fall1(TO_INTEGER(unsigned(DQS_LOC_COL2((8*(c2_i+1))-1 downto 8*c2_i)))) &
rd_dqs_rise1(TO_INTEGER(unsigned(DQS_LOC_COL2((8*(c2_i+1))-1 downto 8*c2_i)))) &
rd_dqs_fall0(TO_INTEGER(unsigned(DQS_LOC_COL2((8*(c2_i+1))-1 downto 8*c2_i)))) &
rd_dqs_rise0(TO_INTEGER(unsigned(DQS_LOC_COL2((8*(c2_i+1))-1 downto 8*c2_i))));
end process;
process (rd_data_rise0, rd_data_rise1, rd_data_fall0,
rd_data_fall1)
begin
data_c2(4*DRAM_WIDTH*(c2_i+1)-1 downto 4*DRAM_WIDTH*c2_i) <=
rd_data_fall1(DRAM_WIDTH*(TO_INTEGER(unsigned(DQS_LOC_COL2((8*(c2_i+1))-1 downto 8*c2_i)))+1) - 1 downto DRAM_WIDTH*(TO_INTEGER(unsigned(DQS_LOC_COL2((8*(c2_i+1))-1 downto 8*c2_i))) )) &
rd_data_rise1(DRAM_WIDTH*(TO_INTEGER(unsigned(DQS_LOC_COL2((8*(c2_i+1))-1 downto 8*c2_i)))+1) - 1 downto DRAM_WIDTH*(TO_INTEGER(unsigned(DQS_LOC_COL2((8*(c2_i+1))-1 downto 8*c2_i))) )) &
rd_data_fall0(DRAM_WIDTH*(TO_INTEGER(unsigned(DQS_LOC_COL2((8*(c2_i+1))-1 downto 8*c2_i)))+1) - 1 downto DRAM_WIDTH*(TO_INTEGER(unsigned(DQS_LOC_COL2((8*(c2_i+1))-1 downto 8*c2_i))) )) &
rd_data_rise0(DRAM_WIDTH*(TO_INTEGER(unsigned(DQS_LOC_COL2((8*(c2_i+1))-1 downto 8*c2_i)))+1) - 1 downto DRAM_WIDTH*(TO_INTEGER(unsigned(DQS_LOC_COL2((8*(c2_i+1))-1 downto 8*c2_i))) ));
end process;
-- Reassemble data from circular buffer
process (dqs_sync_c2(4*c2_i), dqs_sync_c2(4*c2_i+1),
dqs_sync_c2(4*c2_i+2), dqs_sync_c2(4*c2_i+3))
begin
dqs_fall1_sync(TO_INTEGER(unsigned(DQS_LOC_COL2((8*(c2_i+1))-1 downto 8*c2_i)))) <= dqs_sync_c2(4*c2_i+3);
dqs_rise1_sync(TO_INTEGER(unsigned(DQS_LOC_COL2((8*(c2_i+1))-1 downto 8*c2_i)))) <= dqs_sync_c2(4*c2_i+2);
dqs_fall0_sync(TO_INTEGER(unsigned(DQS_LOC_COL2((8*(c2_i+1))-1 downto 8*c2_i)))) <= dqs_sync_c2(4*c2_i+1);
dqs_rise0_sync(TO_INTEGER(unsigned(DQS_LOC_COL2((8*(c2_i+1))-1 downto 8*c2_i)))) <= dqs_sync_c2(4*c2_i+0);
end process;
process (data_sync_c2((4*DRAM_WIDTH*c2_i)+DRAM_WIDTH-1 downto 4*DRAM_WIDTH*c2_i),
data_sync_c2((4*DRAM_WIDTH*c2_i)+2*DRAM_WIDTH-1 downto 4*DRAM_WIDTH*c2_i + DRAM_WIDTH),
data_sync_c2((4*DRAM_WIDTH*c2_i)+3*DRAM_WIDTH-1 downto 4*DRAM_WIDTH*c2_i + 2*DRAM_WIDTH),
data_sync_c2((4*DRAM_WIDTH*c2_i)+4*DRAM_WIDTH-1 downto 4*DRAM_WIDTH*c2_i + 3*DRAM_WIDTH)
)
begin
data_fall1_sync(DRAM_WIDTH*(TO_INTEGER(unsigned(DQS_LOC_COL2((8*(c2_i+1))-1 downto 8*c2_i)))+1) - 1 downto DRAM_WIDTH*(TO_INTEGER(unsigned(DQS_LOC_COL2((8*(c2_i+1))-1 downto 8*c2_i)))))
<= data_sync_c2((4*DRAM_WIDTH*c2_i)+4*DRAM_WIDTH-1 downto 4*DRAM_WIDTH*c2_i + 3*DRAM_WIDTH);
data_rise1_sync(DRAM_WIDTH*(TO_INTEGER(unsigned(DQS_LOC_COL2((8*(c2_i+1))-1 downto 8*c2_i)))+1) - 1 downto DRAM_WIDTH*(TO_INTEGER(unsigned(DQS_LOC_COL2((8*(c2_i+1))-1 downto 8*c2_i)))))
<= data_sync_c2((4*DRAM_WIDTH*c2_i)+3*DRAM_WIDTH-1 downto 4*DRAM_WIDTH*c2_i + 2*DRAM_WIDTH);
data_fall0_sync(DRAM_WIDTH*(TO_INTEGER(unsigned(DQS_LOC_COL2((8*(c2_i+1))-1 downto 8*c2_i)))+1) - 1 downto DRAM_WIDTH*(TO_INTEGER(unsigned(DQS_LOC_COL2((8*(c2_i+1))-1 downto 8*c2_i)))))
<= data_sync_c2((4*DRAM_WIDTH*c2_i)+2*DRAM_WIDTH-1 downto 4*DRAM_WIDTH*c2_i + 1*DRAM_WIDTH);
data_rise0_sync(DRAM_WIDTH*(TO_INTEGER(unsigned(DQS_LOC_COL2((8*(c2_i+1))-1 downto 8*c2_i)))+1) - 1 downto DRAM_WIDTH*(TO_INTEGER(unsigned(DQS_LOC_COL2((8*(c2_i+1))-1 downto 8*c2_i)))))
<= data_sync_c2((4*DRAM_WIDTH*c2_i)+DRAM_WIDTH-1 downto 4*DRAM_WIDTH*c2_i);
end process;
end generate;
u_rddata_sync_c2: circ_buffer
generic map (
TCQ => TCQ,
DATA_WIDTH => (4*nDQS_COL2)+(4*DRAM_WIDTH*nDQS_COL2),
BUF_DEPTH => 6
)
port map (
rclk => clk,
wclk => clk_rsync(2),
rst => rst_rsync(2),
wdata => wdata_xhdl2,
rdata => rdata_xhdl2
);
end generate;
gen_c3: if (nDQS_COL3 > 0) generate
begin
gen_loop_c3: for c3_i in 0 to (nDQS_COL3-1) generate
begin
-- Steer data to circular buffer - merge FALL/RISE data into single bus
process (rd_dqs_fall0, rd_dqs_fall1, rd_dqs_rise0,
rd_dqs_rise1)
begin
dqs_c3(4*(c3_i+1)-1 downto 4*(c3_i+1)-4) <= rd_dqs_fall1(TO_INTEGER(unsigned(DQS_LOC_COL3((8*(c3_i+1))-1 downto 8*c3_i)))) &
rd_dqs_rise1(TO_INTEGER(unsigned(DQS_LOC_COL3((8*(c3_i+1))-1 downto 8*c3_i)))) &
rd_dqs_fall0(TO_INTEGER(unsigned(DQS_LOC_COL3((8*(c3_i+1))-1 downto 8*c3_i)))) &
rd_dqs_rise0(TO_INTEGER(unsigned(DQS_LOC_COL3((8*(c3_i+1))-1 downto 8*c3_i))));
end process;
process (rd_data_rise0, rd_data_rise1, rd_data_fall0,
rd_data_fall1)
begin
data_c3(4*DRAM_WIDTH*(c3_i+1)-1 downto 4*DRAM_WIDTH*c3_i) <=
rd_data_fall1(DRAM_WIDTH*(TO_INTEGER(unsigned(DQS_LOC_COL3((8*(c3_i+1))-1 downto 8*c3_i)))+1) - 1 downto DRAM_WIDTH*(TO_INTEGER(unsigned(DQS_LOC_COL3((8*(c3_i+1))-1 downto 8*c3_i))) )) &
rd_data_rise1(DRAM_WIDTH*(TO_INTEGER(unsigned(DQS_LOC_COL3((8*(c3_i+1))-1 downto 8*c3_i)))+1) - 1 downto DRAM_WIDTH*(TO_INTEGER(unsigned(DQS_LOC_COL3((8*(c3_i+1))-1 downto 8*c3_i))) )) &
rd_data_fall0(DRAM_WIDTH*(TO_INTEGER(unsigned(DQS_LOC_COL3((8*(c3_i+1))-1 downto 8*c3_i)))+1) - 1 downto DRAM_WIDTH*(TO_INTEGER(unsigned(DQS_LOC_COL3((8*(c3_i+1))-1 downto 8*c3_i))) )) &
rd_data_rise0(DRAM_WIDTH*(TO_INTEGER(unsigned(DQS_LOC_COL3((8*(c3_i+1))-1 downto 8*c3_i)))+1) - 1 downto DRAM_WIDTH*(TO_INTEGER(unsigned(DQS_LOC_COL3((8*(c3_i+1))-1 downto 8*c3_i))) ));
end process;
-- Reassemble data from circular buffer
process (dqs_sync_c3(4*c3_i), dqs_sync_c3(4*c3_i+1),
dqs_sync_c3(4*c3_i+2), dqs_sync_c3(4*c3_i+3))
begin
dqs_fall1_sync(TO_INTEGER(unsigned(DQS_LOC_COL3((8*(c3_i+1))-1 downto 8*c3_i)))) <= dqs_sync_c3(4*c3_i+3);
dqs_rise1_sync(TO_INTEGER(unsigned(DQS_LOC_COL3((8*(c3_i+1))-1 downto 8*c3_i)))) <= dqs_sync_c3(4*c3_i+2);
dqs_fall0_sync(TO_INTEGER(unsigned(DQS_LOC_COL3((8*(c3_i+1))-1 downto 8*c3_i)))) <= dqs_sync_c3(4*c3_i+1);
dqs_rise0_sync(TO_INTEGER(unsigned(DQS_LOC_COL3((8*(c3_i+1))-1 downto 8*c3_i)))) <= dqs_sync_c3(4*c3_i+0);
end process;
process (data_sync_c3((4*DRAM_WIDTH*c3_i)+DRAM_WIDTH-1 downto 4*DRAM_WIDTH*c3_i),
data_sync_c3((4*DRAM_WIDTH*c3_i)+2*DRAM_WIDTH-1 downto 4*DRAM_WIDTH*c3_i + DRAM_WIDTH),
data_sync_c3((4*DRAM_WIDTH*c3_i)+3*DRAM_WIDTH-1 downto 4*DRAM_WIDTH*c3_i + 2*DRAM_WIDTH),
data_sync_c3((4*DRAM_WIDTH*c3_i)+4*DRAM_WIDTH-1 downto 4*DRAM_WIDTH*c3_i + 3*DRAM_WIDTH)
)
begin
data_fall1_sync(DRAM_WIDTH*(TO_INTEGER(unsigned(DQS_LOC_COL3((8*(c3_i+1))-1 downto 8*c3_i)))+1) - 1 downto DRAM_WIDTH*(TO_INTEGER(unsigned(DQS_LOC_COL3((8*(c3_i+1))-1 downto 8*c3_i)))))
<= data_sync_c3((4*DRAM_WIDTH*c3_i)+4*DRAM_WIDTH-1 downto 4*DRAM_WIDTH*c3_i + 3*DRAM_WIDTH);
data_rise1_sync(DRAM_WIDTH*(TO_INTEGER(unsigned(DQS_LOC_COL3((8*(c3_i+1))-1 downto 8*c3_i)))+1) - 1 downto DRAM_WIDTH*(TO_INTEGER(unsigned(DQS_LOC_COL3((8*(c3_i+1))-1 downto 8*c3_i)))))
<= data_sync_c3((4*DRAM_WIDTH*c3_i)+3*DRAM_WIDTH-1 downto 4*DRAM_WIDTH*c3_i + 2*DRAM_WIDTH);
data_fall0_sync(DRAM_WIDTH*(TO_INTEGER(unsigned(DQS_LOC_COL3((8*(c3_i+1))-1 downto 8*c3_i)))+1) - 1 downto DRAM_WIDTH*(TO_INTEGER(unsigned(DQS_LOC_COL3((8*(c3_i+1))-1 downto 8*c3_i)))))
<= data_sync_c3((4*DRAM_WIDTH*c3_i)+2*DRAM_WIDTH-1 downto 4*DRAM_WIDTH*c3_i + 1*DRAM_WIDTH);
data_rise0_sync(DRAM_WIDTH*(TO_INTEGER(unsigned(DQS_LOC_COL3((8*(c3_i+1))-1 downto 8*c3_i)))+1) - 1 downto DRAM_WIDTH*(TO_INTEGER(unsigned(DQS_LOC_COL3((8*(c3_i+1))-1 downto 8*c3_i)))))
<= data_sync_c3((4*DRAM_WIDTH*c3_i)+DRAM_WIDTH-1 downto 4*DRAM_WIDTH*c3_i);
end process;
end generate;
u_rddata_sync_c3: circ_buffer
generic map (
TCQ => TCQ,
DATA_WIDTH => (4*nDQS_COL3)+(4*DRAM_WIDTH*nDQS_COL3),
BUF_DEPTH => 6
)
port map (
rclk => clk,
wclk => clk_rsync(3),
rst => rst_rsync(3),
wdata => wdata_xhdl3,
rdata => rdata_xhdl3
);
end generate;
--*******************************************************************************
-- Pipeline stage only required if timing not met otherwise
process (clk)
begin
if (clk'event and clk = '1') then
dfi_rddata <= (data_fall1_sync & data_rise1_sync & data_fall0_sync & data_rise0_sync) after TCQ*1 ps;
dfi_rd_dqs <= (dqs_fall1_sync & dqs_rise1_sync & dqs_fall0_sync & dqs_rise0_sync) after TCQ*1 ps;
end if;
end process;
-- Drive the inputs of circular buffer
wdata_xhdl0 <= (dqs_c0 & data_c0);
dqs_sync_c0 <= rdata_xhdl0(((4*COL0_VECT_WIDTH)+(4*DRAM_WIDTH*COL0_VECT_WIDTH)-1) downto (4*DRAM_WIDTH*COL0_VECT_WIDTH));
data_sync_c0 <= rdata_xhdl0(((4*DRAM_WIDTH*COL0_VECT_WIDTH)-1) downto 0 );
wdata_xhdl1 <= (dqs_c1 & data_c1);
dqs_sync_c1 <= rdata_xhdl1(((4*COL1_VECT_WIDTH)+(4*DRAM_WIDTH*COL1_VECT_WIDTH)-1) downto (4*DRAM_WIDTH*COL1_VECT_WIDTH));
data_sync_c1 <= rdata_xhdl1(((4*DRAM_WIDTH*COL1_VECT_WIDTH)-1) downto 0 );
wdata_xhdl2 <= (dqs_c2 & data_c2);
dqs_sync_c2 <= rdata_xhdl2(((4*COL2_VECT_WIDTH)+(4*DRAM_WIDTH*COL2_VECT_WIDTH)-1) downto (4*DRAM_WIDTH*COL2_VECT_WIDTH));
data_sync_c2 <= rdata_xhdl2(((4*DRAM_WIDTH*COL2_VECT_WIDTH)-1) downto 0 );
wdata_xhdl3 <= (dqs_c3 & data_c3);
dqs_sync_c3 <= rdata_xhdl3(((4*COL3_VECT_WIDTH)+(4*DRAM_WIDTH*COL3_VECT_WIDTH)-1) downto (4*DRAM_WIDTH*COL3_VECT_WIDTH));
data_sync_c3 <= rdata_xhdl3(((4*DRAM_WIDTH*COL3_VECT_WIDTH)-1) downto 0 );
end trans;
|
--!
--! \file dcrfifo.vhd
--!
--! Implementation of a FIFO with DCR bus attachment.
--!
--! control register : BASE_ADDR
--! when read:
--! bit 31 = underrun indicator (initial: 0)
--! bit 30 = overflow indicator (initial: 0)
--! bit 28 = write only indicator (initial: 1)
--! bits 0 to 27 = number of words in FIFO (initial: 0)
--!
--! Writing 0xAFFEBEAF to the control register clears the write only bit.
--! Reading from the FIFO then becomes possible. Writing 0xAFFEDEAD to
--! the control register resets the FIFO. This is at the moment the only
--! way to clear the underrun and overflow bits. Writing any other value
--! to the control register sets the write only bit. This is a precaution
--! to protect the FIFO from crazy operating systems.
--!
--! fifo resgister : BASE_ADDR + 1
--! Reading from the fifo register returns the first word in the FIFO.
--! If the FIFO is empty the result is undefined and the underrun bit is
--! set.
--! When the write only bit is cleared, reading from the fifo register
--! also advances to the next word in the fifo. IF the write only bit is
--! set, reads from the fifo register do not alter the contents of the
--! FIFO.
--! Writing a word to the fifo register puts that word into the FIFO
--! unless no more space is left. In that case the value written is
--! discarded and the overflow bit is set.
--!
--!
--! \author Andreas Agne <[email protected]>
--! \date 18.02.2009
--
-----------------------------------------------------------------------------
-- %%%RECONOS_COPYRIGHT_BEGIN%%%
--
-- This file is part of ReconOS (http://www.reconos.de).
-- Copyright (c) 2006-2010 The ReconOS Project and contributors (see AUTHORS).
-- All rights reserved.
--
-- ReconOS is free software: you can redistribute it and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 3 of the License, or (at your option)
-- any later version.
--
-- ReconOS is distributed in the hope that it will be useful, but WITHOUT ANY
-- WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
-- FOR A PARTICULAR PURPOSE. See the GNU General Public License for more
-- details.
--
-- You should have received a copy of the GNU General Public License along
-- with ReconOS. If not, see <http://www.gnu.org/licenses/>.
--
-- %%%RECONOS_COPYRIGHT_END%%%
-----------------------------------------------------------------------------
--
-- Major changes
-- 18.02.2009 Andreas Agne Initial implementation
---
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity dcrfifo is
generic (
C_DCR_BASEADDR : std_logic_vector := "1111111111";
C_DCR_HIGHADDR : std_logic_vector := "0000000000";
C_DCR_AWIDTH : integer := 10;
C_DCR_DWIDTH : integer := 32;
C_NUM_REGS : integer := 2;
C_FIFO_AWIDTH : integer := 15
);
port ( -- the DCR bus interface
clk : in std_logic;
reset : in std_logic; -- high active synchronous
o_dcrAck : out std_logic;
o_dcrDBus : out std_logic_vector(C_DCR_DWIDTH-1 downto 0);
i_dcrABus : in std_logic_vector(C_DCR_AWIDTH-1 downto 0);
i_dcrDBus : in std_logic_vector(C_DCR_DWIDTH-1 downto 0);
i_dcrRead : in std_logic;
i_dcrWrite : in std_logic
);
end dcrfifo;
architecture Behavioral of dcrfifo is
-- address of status register (read only)
constant ADDR_COUNT : std_logic_vector := C_DCR_BASEADDR;
-- address of fifo register (read/write)
constant ADDR_FIFO : std_logic_vector := C_DCR_BASEADDR + 1;
-- fifo count width
constant FIFO_DEPTH : integer := 2**C_FIFO_AWIDTH;
-- fifo memory type
type t_ram is array (FIFO_DEPTH-1 downto 0) of std_logic_vector(C_DCR_DWIDTH-1 downto 0);
-- fifo memory
signal fifo_mem : t_ram;
-- fifo output
signal fifo_out : std_logic_vector(C_DCR_DWIDTH-1 downto 0);
-- fifo input
signal fifo_in : std_logic_vector(C_DCR_DWIDTH-1 downto 0);
-- fifo output address register
signal fifo_outaddr : std_logic_vector(C_FIFO_AWIDTH-1 downto 0);
-- fifo input address register
signal fifo_inaddr : std_logic_vector(C_FIFO_AWIDTH-1 downto 0);
-- fifo count register
signal fifo_count : std_logic_vector(C_FIFO_AWIDTH-1 downto 0);
-- fifo write_enable signal
signal fifo_we : std_logic;
-- advance to next output word
signal fifo_next : std_logic;
-- fifo full indicator
signal fifo_full : std_logic;
-- fifo empty indicator
signal fifo_empty : std_logic;
-- fifo overflow
signal fifo_overflow : std_logic;
-- fifo underrun
signal fifo_underrun : std_logic;
-- fifo contol
signal fifo_ctrl : std_logic;
-- fifo write only
signal fifo_wronly_set : std_logic;
signal fifo_wronly : std_logic;
-- fifo reset
signal fifo_reset : std_logic;
-- registers indicating type of request
signal readStateReg : std_logic;
signal writeStateReg : std_logic;
signal readFifoReg : std_logic;
signal writeFifoReg : std_logic;
-- asynchronous signals indicating type of request (input to the registers above)
signal readState : std_logic;
signal writeState : std_logic;
signal readFifo : std_logic;
signal writeFifo : std_logic;
begin
-- asynchronously determine the type of request
readState <= '1' when i_dcrRead = '1' and i_dcrABus = ADDR_COUNT else '0';
writeState <= '1' when i_dcrWrite = '1' and i_dcrABus = ADDR_COUNT else '0';
readFifo <= '1' when i_dcrRead = '1' and i_dcrABus = ADDR_FIFO else '0';
writeFifo <= '1' when i_dcrWrite = '1' and i_dcrABus = ADDR_FIFO else '0';
-- DCR ack
o_dcrAck <= readStateReg or readFifoReg or writeFifoReg or writeStateReg;
-- fifo advance to next word
fifo_next <= readFifoReg and (not readFifo);
-- fifo write enable
fifo_we <= (not writeFifoReg) and writeFifo;
-- control register access
fifo_ctrl <= (not writeStateReg) and writeState;
-- connect fifo input to DCR
fifo_in <= i_dcrDBus;
-- fifo full and empty signals
fifo_empty <= '1' when CONV_INTEGER(fifo_count) = 0 else '0';
fifo_full <= '1' when CONV_INTEGER(fifo_count) = FIFO_DEPTH - 1 else '0';
-- fifo control signals
fifo_wronly_set <= '0' when i_dcrDBus = X"AFFEBEEF" else '1';
fifo_reset <= '1' when i_dcrDBus = X"AFFEDEAD" else '0';
-- bypass mux as in UG018 page 105 (data output for read requests)
bypass_mux : process (readFifo, readState, i_dcrDBus, fifo_count, fifo_out,
fifo_underrun, fifo_overflow, fifo_wronly)
begin
o_dcrDBus <= i_dcrDBus;
if readFifo = '1' then o_dcrDBus <= fifo_out;
elsif readState = '1' then
o_dcrDBus(C_FIFO_AWIDTH-1 downto 0) <= fifo_count;
o_dcrDBus(C_DCR_DWIDTH-1) <= fifo_underrun;
o_dcrDBus(C_DCR_DWIDTH-2) <= fifo_overflow;
o_dcrDBus(C_DCR_DWIDTH-7) <= fifo_wronly;
end if;
end process;
-- process registers that indicate the type of request
syn_req : process (clk, reset, readFifo, readState, writeFifo)
begin
if reset = '1' then
readStateReg <= '0';
readFifoReg <= '0';
writeFifoReg <= '0';
writeStateReg <= '0';
elsif rising_edge(clk) then
readStateReg <= '0';
readFifoReg <= '0';
writeFifoReg <= '0';
writeStateReg <= '0';
if readFifo = '1' then readFifoReg <= '1'; end if;
if readState = '1' then readStateReg <= '1'; end if;
if writeFifo = '1' then writeFifoReg <= '1'; end if;
if writeState = '1' then writeStateReg <= '1'; end if;
end if;
end process;
-- FIFO implementation: this inferres a two port block ram and some additional
-- control logic and registers
fifo : process (clk, reset, fifo_we, fifo_next, fifo_full, fifo_empty, fifo_reset,
fifo_ctrl, fifo_wronly, fifo_wronly_set)
begin
if reset = '1' then
fifo_inaddr <= (others => '0');
fifo_outaddr <= (others => '0');
fifo_count <= (others => '0');
fifo_overflow <= '0';
fifo_underrun <= '0';
fifo_wronly <= '1';
elsif rising_edge(clk) then
fifo_out <= fifo_mem(CONV_INTEGER(fifo_outaddr));
if fifo_ctrl = '1' then
if fifo_reset = '1' then
fifo_inaddr <= (others => '0');
fifo_outaddr <= (others => '0');
fifo_count <= (others => '0');
fifo_overflow <= '0';
fifo_underrun <= '0';
fifo_wronly <= '1';
end if;
fifo_wronly <= fifo_wronly_set;
elsif fifo_we = '1' then
if fifo_full = '1' then
fifo_overflow <= '1';
else
fifo_mem(CONV_INTEGER(fifo_inaddr)) <= fifo_in;
fifo_inaddr <= fifo_inaddr + 1;
fifo_count <= fifo_count + 1;
end if;
elsif fifo_next = '1' and fifo_wronly = '0' then
if fifo_empty = '1' then
fifo_underrun <= '1';
else
fifo_outaddr <= fifo_outaddr + 1;
fifo_count <= fifo_count - 1;
end if;
end if;
end if;
end process;
end Behavioral;
|
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY test_fsm_prac4 IS
END test_fsm_prac4;
ARCHITECTURE behavior OF test_fsm_prac4 IS
COMPONENT fsm_prac4
PORT(
X : IN std_logic;
RESET : IN std_logic;
clk100mhz : IN std_logic;
Z : OUT std_logic
);
END COMPONENT;
signal X : std_logic := '0';
signal RESET : std_logic := '0';
signal clk100mhz : std_logic := '0';
signal Z : std_logic;
signal check_data_line : std_logic_vector (15 downto 0) := "0110110100011100";
signal check_data_match : std_logic_vector (15 downto 0) := "0000011011000000";
signal check_state_trans : std_logic_vector (19 downto 0) := "11010011101100011010";
constant clk100mhz_period : time := 10 ns;
signal full_check_state : std_logic_vector(31 downto 0) := (others => '0');
subtype counter_bit_int is integer range 0 to 31;
BEGIN
full_check_state(31 downto 16) <= check_data_line;
full_check_state(15 downto 0) <= check_data_match;
uut: fsm_prac4 PORT MAP (
X => X,
RESET => RESET,
clk100mhz => clk100mhz,
Z => Z
);
-- Clock process definitions
clk100mhz_process :process
begin
clk100mhz <= '0';
wait for clk100mhz_period/2;
clk100mhz <= '1';
wait for clk100mhz_period/2;
end process;
RESET <= '1';
-- Stimulus process
stim_proc: process
begin
RESET <= '0' ;
wait for clk100mhz_period*10;
RESET <= '1' ;
wait for clk100mhz_period*10;
FOR I in 19 downto 0 loop
wait until clk100mhz'event;
if clk100mhz = '1' then
X <= check_state_trans(I);
end if;
--assert ( Z = check_data_match(I) ) report "MATCH ERROR" severity error;
END loop;
wait until clk100mhz'event and clk100mhz = '1';
wait for clk100mhz_period*10;
wait;
end process;
-- tester : process (clk100mHz)
-- variable counter : counter_bit_int := 0;
-- begin
-- --wait until submitButton'event and submitButton = '1' ;
-- if (clk100mhz'event and clk100mhz = '1') then
-- if (counter >= 0) then
-- X <= full_check_state(counter);
-- counter := counter - 1;
-- else
-- counter := 31;
-- end if;
-- end if;
-- end process;
END;
|
-------------------------------------------------------------------------------
--
-- The Port 2 unit.
-- Implements the Port 2 logic.
--
-- $Id: p2-c.vhd,v 1.2 2005-06-11 10:08:43 arniml Exp $
--
-- All rights reserved
--
-------------------------------------------------------------------------------
configuration t48_p2_rtl_c0 of t48_p2 is
for rtl
end for;
end t48_p2_rtl_c0;
|
package p1 is
constant k : integer := 1;
constant j : integer := 5;
type t is (FOO, BAR);
end package;
package p2 is
constant k : integer := 2;
constant j : integer := 7;
type t is (BAR, BAZ);
end package;
use work.p1.all;
use work.p2.all;
package p3 is
constant x : integer := k; -- Error
constant j : integer := 2; -- OK
constant y : integer := j; -- OK
constant z : t := FOO; -- Error
constant b : boolean := BAR; -- Error
end package;
|
-- megafunction wizard: %LPM_COUNTER%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: lpm_counter
-- ============================================================
-- File Name: clock1hz.vhd
-- Megafunction Name(s):
-- lpm_counter
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2010 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY clock1hz IS
PORT
(
clock : IN STD_LOGIC ;
cout : OUT STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (29 DOWNTO 0)
);
END clock1hz;
ARCHITECTURE SYN OF clock1hz IS
SIGNAL sub_wire0 : STD_LOGIC ;
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (29 DOWNTO 0);
COMPONENT lpm_counter
GENERIC (
lpm_direction : STRING;
lpm_modulus : NATURAL;
lpm_port_updown : STRING;
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
clock : IN STD_LOGIC ;
cout : OUT STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (29 DOWNTO 0)
);
END COMPONENT;
BEGIN
cout <= sub_wire0;
q <= sub_wire1(29 DOWNTO 0);
lpm_counter_component : lpm_counter
GENERIC MAP (
lpm_direction => "UP",
lpm_modulus => 200000,
lpm_port_updown => "PORT_UNUSED",
lpm_type => "LPM_COUNTER",
lpm_width => 30
)
PORT MAP (
clock => clock,
cout => sub_wire0,
q => sub_wire1
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACLR NUMERIC "0"
-- Retrieval info: PRIVATE: ALOAD NUMERIC "0"
-- Retrieval info: PRIVATE: ASET NUMERIC "0"
-- Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
-- Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
-- Retrieval info: PRIVATE: CNT_EN NUMERIC "0"
-- Retrieval info: PRIVATE: CarryIn NUMERIC "0"
-- Retrieval info: PRIVATE: CarryOut NUMERIC "1"
-- Retrieval info: PRIVATE: Direction NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone"
-- Retrieval info: PRIVATE: ModulusCounter NUMERIC "1"
-- Retrieval info: PRIVATE: ModulusValue NUMERIC "200000"
-- Retrieval info: PRIVATE: SCLR NUMERIC "0"
-- Retrieval info: PRIVATE: SLOAD NUMERIC "0"
-- Retrieval info: PRIVATE: SSET NUMERIC "0"
-- Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: nBit NUMERIC "30"
-- Retrieval info: CONSTANT: LPM_DIRECTION STRING "UP"
-- Retrieval info: CONSTANT: LPM_MODULUS NUMERIC "200000"
-- Retrieval info: CONSTANT: LPM_PORT_UPDOWN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_COUNTER"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "30"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
-- Retrieval info: USED_PORT: cout 0 0 0 0 OUTPUT NODEFVAL cout
-- Retrieval info: USED_PORT: q 0 0 30 0 OUTPUT NODEFVAL q[29..0]
-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 30 0 @q 0 0 30 0
-- Retrieval info: CONNECT: cout 0 0 0 0 @cout 0 0 0 0
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: GEN_FILE: TYPE_NORMAL clock1hz.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL clock1hz.inc TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL clock1hz.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL clock1hz.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL clock1hz_inst.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL clock1hz_waveforms.html TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL clock1hz_wave*.jpg FALSE
-- Retrieval info: LIB_FILE: lpm
|
--!
--! \file mem_plb34.vhd
--!
--! Memory bus interface for the 64-bit PLB v34.
--!
--! \author Enno Luebbers <[email protected]>
--! \date 08.12.2008
--
-----------------------------------------------------------------------------
-- %%%RECONOS_COPYRIGHT_BEGIN%%%
--
-- This file is part of ReconOS (http://www.reconos.de).
-- Copyright (c) 2006-2010 The ReconOS Project and contributors (see AUTHORS).
-- All rights reserved.
--
-- ReconOS is free software: you can redistribute it and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 3 of the License, or (at your option)
-- any later version.
--
-- ReconOS is distributed in the hope that it will be useful, but WITHOUT ANY
-- WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
-- FOR A PARTICULAR PURPOSE. See the GNU General Public License for more
-- details.
--
-- You should have received a copy of the GNU General Public License along
-- with ReconOS. If not, see <http://www.gnu.org/licenses/>.
--
-- %%%RECONOS_COPYRIGHT_END%%%
-----------------------------------------------------------------------------
--
-- Major Changes:
--
-- 08.12.2008 Enno Luebbers File created.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library reconos_v2_01_a;
use reconos_v2_01_a.reconos_pkg.all;
library plb_osif_v2_01_a;
use plb_osif_v2_01_a.all;
entity mem_plb34 is
generic
(
C_SLAVE_BASEADDR : std_logic_vector := X"FFFFFFFF";
-- Bus protocol parameters
C_AWIDTH : integer := 32;
C_DWIDTH : integer := 32;
C_PLB_AWIDTH : integer := 32;
C_PLB_DWIDTH : integer := 64;
C_NUM_CE : integer := 2;
C_BURST_AWIDTH : integer := 13; -- 1024 x 64 Bit = 8192 Bytes = 2^13 Bytes
C_BURST_BASEADDR : std_logic_vector := X"00004000"; -- system memory base address for burst ram access
C_BURSTLEN_WIDTH : integer := 5
);
port
(
clk : in std_logic;
reset : in std_logic;
-- data interface ---------------------------
-- burst mem interface
o_burstAddr : out std_logic_vector(0 to C_BURST_AWIDTH-1);
o_burstData : out std_logic_vector(0 to C_PLB_DWIDTH-1);
i_burstData : in std_logic_vector(0 to C_PLB_DWIDTH-1);
o_burstWE : out std_logic;
o_burstBE : out std_logic_vector(0 to C_PLB_DWIDTH/8-1);
-- single word data input/output
i_singleData : in std_logic_vector(0 to C_OSIF_DATA_WIDTH-1);
-- osif2bus
o_singleData : out std_logic_vector(0 to C_OSIF_DATA_WIDTH-1);
-- bus2osif
-- control interface ------------------------
-- addresses for master transfers
i_localAddr : in std_logic_vector(0 to C_AWIDTH-1);
i_targetAddr : in std_logic_vector(0 to C_AWIDTH-1);
-- single word transfer requests
i_singleRdReq : in std_logic;
i_singleWrReq : in std_logic;
-- burst transfer requests
i_burstRdReq : in std_logic;
i_burstWrReq : in std_logic;
i_burstLen : in std_logic_vector(0 to C_BURSTLEN_WIDTH-1); -- number of burst beats (n x 64 bits)
-- status outputs
o_busy : out std_logic;
o_rdDone : out std_logic;
o_wrDone : out std_logic;
-- PLBv34 bus interface -----------------------------------------
-- Bus protocol ports, do not add to or delete
Bus2IP_Clk : in std_logic;
Bus2IP_Reset : in std_logic;
Bus2IP_Addr : in std_logic_vector(0 to C_AWIDTH - 1);
Bus2IP_Data : in std_logic_vector(0 to C_DWIDTH-1);
Bus2IP_DataX : in std_logic_vector(C_DWIDTH to C_PLB_DWIDTH-1);
Bus2IP_BE : in std_logic_vector(0 to C_PLB_DWIDTH/8-1);
Bus2IP_Burst : in std_logic;
Bus2IP_RdCE : in std_logic_vector(0 to C_NUM_CE-1);
Bus2IP_WrCE : in std_logic_vector(0 to C_NUM_CE-1);
Bus2IP_RdReq : in std_logic;
Bus2IP_WrReq : in std_logic;
IP2Bus_Data : out std_logic_vector(0 to C_DWIDTH-1);
IP2Bus_DataX : out std_logic_vector(C_DWIDTH to C_PLB_DWIDTH-1);
IP2Bus_Retry : out std_logic;
IP2Bus_Error : out std_logic;
IP2Bus_ToutSup : out std_logic;
IP2Bus_RdAck : out std_logic;
IP2Bus_WrAck : out std_logic;
Bus2IP_MstError : in std_logic;
Bus2IP_MstLastAck : in std_logic;
Bus2IP_MstRdAck : in std_logic;
Bus2IP_MstWrAck : in std_logic;
Bus2IP_MstRetry : in std_logic;
Bus2IP_MstTimeOut : in std_logic;
IP2Bus_Addr : out std_logic_vector(0 to C_AWIDTH-1);
IP2Bus_MstBE : out std_logic_vector(0 to C_PLB_DWIDTH/8-1);
IP2Bus_MstBurst : out std_logic;
IP2Bus_MstBusLock : out std_logic;
IP2Bus_MstNum : out std_logic_vector(0 to 4);
IP2Bus_MstRdReq : out std_logic;
IP2Bus_MstWrReq : out std_logic;
IP2IP_Addr : out std_logic_vector(0 to C_AWIDTH-1)
);
end entity mem_plb34;
architecture arch of mem_plb34 is
---------
-- read/write acknowledge
---------
signal ram_IP2Bus_RdAck : std_logic;
signal ram_IP2Bus_WrAck : std_logic;
signal slv_IP2Bus_RdAck : std_logic;
signal slv_IP2Bus_WrAck : std_logic;
signal slv_rddata : std_logic_vector(0 to C_DWIDTH-1);
begin
-----------------------------------------------------------------------
-- bus_master_inst: bus master instantiation
--
-- The bus_master module is responsible for initiating a bus read or
-- write transaction through the IPIF master services. The actual
-- transaction will appear like a bus initiated slave request at the
-- IPIF slave attachment and is therefore handled by bus_slave_regs
-- or the bus2burst process.
-----------------------------------------------------------------------
bus_master_inst : entity plb_osif_v2_01_a.bus_master
generic map (
C_AWIDTH => C_AWIDTH,
C_DWIDTH => C_DWIDTH,
C_PLB_DWIDTH => C_PLB_DWIDTH,
C_SLAVE_BASEADDR => C_SLAVE_BASEADDR,
C_BURST_BASEADDR => C_BURST_BASEADDR,
C_BURSTLEN_WIDTH => C_BURSTLEN_WIDTH
)
port map (
clk => clk,
reset => reset,
-- PLB bus master signals
Bus2IP_MstError => Bus2IP_MstError,
Bus2IP_MstLastAck => Bus2IP_MstLastAck,
Bus2IP_MstRdAck => Bus2IP_MstRdAck,
Bus2IP_MstWrAck => Bus2IP_MstWrAck,
Bus2IP_MstRetry => Bus2IP_MstRetry,
Bus2IP_MstTimeOut => Bus2IP_MstTimeOut,
IP2Bus_Addr => IP2Bus_Addr,
IP2Bus_MstBE => IP2Bus_MstBE,
IP2Bus_MstBurst => IP2Bus_MstBurst,
IP2Bus_MstBusLock => IP2Bus_MstBusLock,
IP2Bus_MstNum => IP2Bus_MstNum,
IP2Bus_MstRdReq => IP2Bus_MstRdReq,
IP2Bus_MstWrReq => IP2Bus_MstWrReq,
IP2IP_Addr => IP2IP_Addr,
-- user interface
i_target_addr => i_targetAddr,
i_my_addr => i_localAddr,
i_read_req => i_singleRdReq,
i_write_req => i_singleWrReq,
i_burst_read_req => i_burstRdReq,
i_burst_write_req => i_burstWrReq,
i_burst_length => i_burstLen,
o_busy => o_busy,
o_read_done => o_rdDone,
o_write_done => o_wrDone
);
-----------------------------------------------------------------------
-- bus_slave_regs_inst: PLB bus slave instatiation
--
-- Handles access to the shared memory register
-- Used for single word memory accesses
-- (e.g. reconos_read() and reconos_write())
-----------------------------------------------------------------------
bus_slave_regs_inst : entity plb_osif_v2_01_a.bus_slave_regs
generic map (
C_DWIDTH => C_DWIDTH,
C_NUM_REGS => C_NUM_CE-1
)
port map (
clk => Bus2IP_Clk,
reset => Bus2IP_Reset,
-- bus slave signals
Bus2IP_Data => Bus2IP_Data,
Bus2IP_BE => Bus2IP_BE(0 to (C_DWIDTH/8)-1),
Bus2IP_RdCE => Bus2IP_RdCE(0 to C_NUM_CE-2),
Bus2IP_WrCE => Bus2IP_WrCE(0 to C_NUM_CE-2),
IP2Bus_Data => slv_RdData,
IP2Bus_RdAck => slv_IP2Bus_RdAck,
IP2Bus_WrAck => slv_IP2Bus_WrAck,
-- user registers
slv_osif2bus_shm => i_singleData,
slv_bus2osif_shm => o_singleData
);
-- read/write acknowledge
IP2Bus_RdAck <= slv_IP2Bus_RdAck or ram_IP2Bus_RdAck;
IP2Bus_WrAck <= slv_IP2Bus_WrAck or ram_IP2Bus_WrAck;
-- no error handling / retry / timeout
IP2Bus_Error <= '0';
IP2Bus_Retry <= '0';
IP2Bus_ToutSup <= '0';
-- multiplex data, if PLB connected
IP2Bus_Data <= i_burstData(0 to C_DWIDTH-1) when ram_IP2Bus_RdAck = '1' else slv_RdData;
IP2Bus_DataX <= i_burstData(C_DWIDTH to C_PLB_DWIDTH-1);
o_burstData <= Bus2IP_Data & Bus2IP_DataX;
-- burstWE <= ram_IP2Bus_WrAck and Bus2IP_WrReq;
o_burstBE <= Bus2IP_BE;
-------------------------------------------------------------------
-- bus2burst: handles bus accesses to burst memory
--
-- supports both single and burst accesses
-------------------------------------------------------------------
bus2burst : process(Bus2IP_Clk, Bus2IP_Reset)
type ram_state_t is (IDLE, BURST_READ, BURST_WRITE, SINGLE_READ);
variable ram_state : ram_state_t;
variable start_addr : std_logic_vector(0 to C_BURST_AWIDTH-1);
variable counter : natural := 0;
begin
if Bus2IP_Reset = '1' then
ram_state := IDLE;
start_addr := (others => '0');
counter := 0;
ram_IP2Bus_RdAck <= '0';
ram_IP2Bus_WrAck <= '0';
o_burstAddr <= (others => '0');
o_burstWE <= '0';
elsif rising_edge(Bus2IP_Clk) then
case ram_state is
when IDLE =>
counter := 0;
o_burstWE <= '0';
ram_IP2Bus_RdAck <= '0';
ram_IP2Bus_WrAck <= '0';
-- if Bus2IP_RdReq = '1' then
if Bus2IP_RdCE(1) = '1' and Bus2IP_RdReq = '1' then
if Bus2IP_Burst = '1' then
start_addr := Bus2IP_Addr(C_PLB_AWIDTH-C_BURST_AWIDTH to C_PLB_AWIDTH-1); -- get burst start address
o_burstAddr <= start_addr + counter*8;
ram_state := BURST_READ;
else
o_burstAddr <= Bus2IP_Addr(C_PLB_AWIDTH-C_BURST_AWIDTH to C_PLB_AWIDTH-1);
ram_state := SINGLE_READ;
end if;
-- elsif Bus2IP_WrReq = '1' then
elsif Bus2IP_WrCE(1) = '1'and Bus2IP_WrReq = '1' then
if Bus2IP_Burst = '1' then
start_addr := Bus2IP_Addr(C_PLB_AWIDTH-C_BURST_AWIDTH to C_PLB_AWIDTH-1); -- get burst start address
o_burstAddr <= start_addr + counter*8;
ram_IP2Bus_WrAck <= '1';
o_burstWE <= '1';
ram_state := BURST_WRITE;
else
o_burstAddr <= Bus2IP_Addr(C_PLB_AWIDTH-C_BURST_AWIDTH to C_PLB_AWIDTH-1);
ram_IP2Bus_WrAck <= '1';
o_burstWE <= '1';
ram_state := IDLE;
end if;
end if;
when BURST_READ =>
ram_IP2Bus_RdAck <= '1';
counter := counter + 1;
if Bus2IP_Burst = '0' then -- Bus2IP_Burst is deasserted at the second to last data beat
ram_IP2Bus_RdAck <= '0';
ram_state := IDLE;
end if;
o_burstAddr <= start_addr + counter*8;
when BURST_WRITE =>
counter := counter + 1;
if Bus2IP_Burst = '0' then -- Bus2IP_Burst is deasserted at the second to last data beat
ram_IP2Bus_WrAck <= '0';
o_burstWE <= '0';
ram_state := IDLE;
end if;
o_burstAddr <= start_addr + counter*8;
when SINGLE_READ =>
ram_IP2Bus_RdAck <= '1';
ram_state := IDLE;
end case;
end if;
end process;
end arch;
|
-- bitonic_sort9.vhd
-- Jan Viktorin <[email protected]>
-- Copyright (C) 2011, 2012 Jan Viktorin
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity bitonic_sort9 is
generic (
LEVEL : integer := -1
);
port (
CLK : in std_logic;
CE : in std_logic;
DI : in std_logic_vector(9 * 8 - 1 downto 0);
DO : out std_logic_vector(9 * 8 - 1 downto 0)
);
end entity;
---
-- Pipeline level of the bitonic_sort9 unit.
-- For every LEVEL in range 0..7 generates apropriate cmp_swap units
-- and pipeline registers.
--
-- See paper Novel Hardware Implementation of Adaptive Median Filters
-- at http://www.fit.vutbr.cz/research/view_pub.php.cs?id=8604.
---
architecture level_x of bitonic_sort9 is
begin
assert LEVEL >= 0 and LEVEL <= 7
report "Invalid LEVEL of bitonic_sort9(level_x): " & integer'image(LEVEL)
severity failure;
-----------------------------------------
-----------------------------------------
-----------------------------------------
gen_level0: if LEVEL = 0
generate
swap_10_i : entity work.cmp_swap
port map (
CLK => CLK,
CE => CE,
I_A => DI(15 downto 8),
I_B => DI( 7 downto 0),
O_A => DO(15 downto 8),
O_B => DO( 7 downto 0)
);
swap_23_i : entity work.cmp_swap
port map (
CLK => CLK,
CE => CE,
I_A => DI(23 downto 16),
I_B => DI(31 downto 24),
O_A => DO(23 downto 16),
O_B => DO(31 downto 24)
);
swap_45_i : entity work.cmp_swap
port map (
CLK => CLK,
CE => CE,
I_A => DI(39 downto 32),
I_B => DI(47 downto 40),
O_A => DO(39 downto 32),
O_B => DO(47 downto 40)
);
reg_6p : process(CLK, CE, DI)
begin
if rising_edge(CLK) then
if CE = '1' then
DO(55 downto 48) <= DI(55 downto 48);
end if;
end if;
end process;
swap_87_i : entity work.cmp_swap
port map (
CLK => CLK,
CE => CE,
I_A => DI(71 downto 64),
I_B => DI(63 downto 56),
O_A => DO(71 downto 64),
O_B => DO(63 downto 56)
);
end generate;
-----------------------------------------
-----------------------------------------
-----------------------------------------
gen_level1: if LEVEL = 1
generate
swap_02_i : entity work.cmp_swap
port map (
CLK => CLK,
CE => CE,
I_A => DI( 7 downto 0),
I_B => DI(23 downto 16),
O_A => DO( 7 downto 0),
O_B => DO(23 downto 16)
);
swap_13_i : entity work.cmp_swap
port map (
CLK => CLK,
CE => CE,
I_A => DI(15 downto 8),
I_B => DI(31 downto 24),
O_A => DO(15 downto 8),
O_B => DO(31 downto 24)
);
reg_457p : process(CLK, CE, DI)
begin
if rising_edge(CLK) then
if CE = '1' then
DO(47 downto 32) <= DI(47 downto 32);
DO(63 downto 56) <= DI(63 downto 56);
end if;
end if;
end process;
swap_86_i : entity work.cmp_swap
port map (
CLK => CLK,
CE => CE,
I_A => DI(71 downto 64),
I_B => DI(55 downto 48),
O_A => DO(71 downto 64),
O_B => DO(55 downto 48)
);
end generate;
-----------------------------------------
-----------------------------------------
-----------------------------------------
gen_level2: if LEVEL = 2
generate
swap_01_i : entity work.cmp_swap
port map (
CLK => CLK,
CE => CE,
I_A => DI( 7 downto 0),
I_B => DI(15 downto 8),
O_A => DO( 7 downto 0),
O_B => DO(15 downto 8)
);
swap_23_i : entity work.cmp_swap
port map (
CLK => CLK,
CE => CE,
I_A => DI(23 downto 16),
I_B => DI(31 downto 24),
O_A => DO(23 downto 16),
O_B => DO(31 downto 24)
);
swap_84_i : entity work.cmp_swap
port map (
CLK => CLK,
CE => CE,
I_A => DI(71 downto 64),
I_B => DI(39 downto 32),
O_A => DO(71 downto 64),
O_B => DO(39 downto 32)
);
reg_5p : process(CLK, CE, DI)
begin
if rising_edge(CLK) then
if CE = '1' then
DO(47 downto 40) <= DI(47 downto 40);
end if;
end if;
end process;
swap_76_i : entity work.cmp_swap
port map (
CLK => CLK,
CE => CE,
I_A => DI(63 downto 56),
I_B => DI(55 downto 48),
O_A => DO(63 downto 56),
O_B => DO(55 downto 48)
);
end generate;
-----------------------------------------
-----------------------------------------
-----------------------------------------
gen_level3: if LEVEL = 3
generate
swap_80_i : entity work.cmp_swap
port map (
CLK => CLK,
CE => CE,
I_A => DI(71 downto 64),
I_B => DI( 7 downto 0),
O_A => DO(71 downto 64),
O_B => DO( 7 downto 0)
);
reg_123p : process(CLK, CE, DI)
begin
if rising_edge(CLK) then
if CE = '1' then
DO(31 downto 8) <= DI(31 downto 8);
end if;
end if;
end process;
swap_64_i : entity work.cmp_swap
port map (
CLK => CLK,
CE => CE,
I_A => DI(55 downto 48),
I_B => DI(39 downto 32),
O_A => DO(55 downto 48),
O_B => DO(39 downto 32)
);
swap_75_i : entity work.cmp_swap
port map (
CLK => CLK,
CE => CE,
I_A => DI(63 downto 56),
I_B => DI(47 downto 40),
O_A => DO(63 downto 56),
O_B => DO(47 downto 40)
);
end generate;
-----------------------------------------
-----------------------------------------
-----------------------------------------
gen_level4: if LEVEL = 4
generate
reg_01238p : process(CLK, CE, DI)
begin
if rising_edge(CLK) then
if CE = '1' then
DO(31 downto 0) <= DI(31 downto 0);
DO(71 downto 64) <= DI(71 downto 64);
end if;
end if;
end process;
swap_54_i : entity work.cmp_swap
port map (
CLK => CLK,
CE => CE,
I_A => DI(47 downto 40),
I_B => DI(39 downto 32),
O_A => DO(47 downto 40),
O_B => DO(39 downto 32)
);
swap_76_i : entity work.cmp_swap
port map (
CLK => CLK,
CE => CE,
I_A => DI(63 downto 56),
I_B => DI(55 downto 48),
O_A => DO(63 downto 56),
O_B => DO(55 downto 48)
);
end generate;
-----------------------------------------
-----------------------------------------
-----------------------------------------
gen_level5: if LEVEL = 5
generate
swap_40_i : entity work.cmp_swap
port map (
CLK => CLK,
CE => CE,
I_A => DI(39 downto 32),
I_B => DI( 7 downto 0),
O_A => DO(39 downto 32),
O_B => DO( 7 downto 0)
);
swap_51_i : entity work.cmp_swap
port map (
CLK => CLK,
CE => CE,
I_A => DI(47 downto 40),
I_B => DI(15 downto 8),
O_A => DO(47 downto 40),
O_B => DO(15 downto 8)
);
swap_62_i : entity work.cmp_swap
port map (
CLK => CLK,
CE => CE,
I_A => DI(55 downto 48),
I_B => DI(23 downto 16),
O_A => DO(55 downto 48),
O_B => DO(23 downto 16)
);
swap_73_i : entity work.cmp_swap
port map (
CLK => CLK,
CE => CE,
I_A => DI(63 downto 56),
I_B => DI(31 downto 24),
O_A => DO(63 downto 56),
O_B => DO(31 downto 24)
);
reg_8p : process(CLK, CE, DI)
begin
if rising_edge(CLK) then
if CE = '1' then
DO(71 downto 64) <= DI(71 downto 64);
end if;
end if;
end process;
end generate;
-----------------------------------------
-----------------------------------------
-----------------------------------------
gen_level6: if LEVEL = 6
generate
swap_20_i : entity work.cmp_swap
port map (
CLK => CLK,
CE => CE,
I_A => DI(23 downto 16),
I_B => DI( 7 downto 0),
O_A => DO(23 downto 16),
O_B => DO( 7 downto 0)
);
swap_31_i : entity work.cmp_swap
port map (
CLK => CLK,
CE => CE,
I_A => DI(31 downto 24),
I_B => DI(15 downto 8),
O_A => DO(31 downto 24),
O_B => DO(15 downto 8)
);
swap_46_i : entity work.cmp_swap
port map (
CLK => CLK,
CE => CE,
I_A => DI(55 downto 48),
I_B => DI(39 downto 32),
O_A => DO(55 downto 48),
O_B => DO(39 downto 32)
);
swap_57_i : entity work.cmp_swap
port map (
CLK => CLK,
CE => CE,
I_A => DI(63 downto 56),
I_B => DI(47 downto 40),
O_A => DO(63 downto 56),
O_B => DO(47 downto 40)
);
reg_8p : process(CLK, CE, DI)
begin
if rising_edge(CLK) then
if CE = '1' then
DO(71 downto 64) <= DI(71 downto 64);
end if;
end if;
end process;
end generate;
-----------------------------------------
-----------------------------------------
-----------------------------------------
gen_level7: if LEVEL = 7
generate
swap_10_i : entity work.cmp_swap
port map (
CLK => CLK,
CE => CE,
I_A => DI(15 downto 8),
I_B => DI( 7 downto 0),
O_A => DO(15 downto 8),
O_B => DO( 7 downto 0)
);
swap_32_i : entity work.cmp_swap
port map (
CLK => CLK,
CE => CE,
I_A => DI(31 downto 24),
I_B => DI(23 downto 16),
O_A => DO(31 downto 24),
O_B => DO(23 downto 16)
);
swap_54_i : entity work.cmp_swap
port map (
CLK => CLK,
CE => CE,
I_A => DI(47 downto 40),
I_B => DI(39 downto 32),
O_A => DO(47 downto 40),
O_B => DO(39 downto 32)
);
swap_76_i : entity work.cmp_swap
port map (
CLK => CLK,
CE => CE,
I_A => DI(63 downto 56),
I_B => DI(55 downto 48),
O_A => DO(63 downto 56),
O_B => DO(55 downto 48)
);
reg_8p : process(CLK, CE, DI)
begin
if rising_edge(CLK) then
if CE = '1' then
DO(71 downto 64) <= DI(71 downto 64);
end if;
end if;
end process;
end generate;
end architecture;
---
-- Top level creates 8 levels of smaller sorters.
-- Generic LEVEL is ignored and must be set to -1.
---
architecture top_level of bitonic_sort9 is
type level_data_t is array(0 to 8) of std_logic_vector(71 downto 0);
signal level_data : level_data_t;
begin
assert LEVEL = -1
report "Setting LEVEL for bitonic_sort9(top_level) does not make sense"
severity failure;
-----------------------------------------
level_data(0) <= DI;
DO <= level_data(8);
-----------------------------------------
gen_levels: for i in 0 to 7
generate
level_x_i : entity work.bitonic_sort9(level_x)
generic map (
LEVEL => i
)
port map (
CLK => CLK,
CE => CE,
DI => level_data(i),
DO => level_data(i + 1)
);
end generate;
end architecture;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_cast_GN76IOUHQH is
generic ( round : natural := 0;
saturate : natural := 0);
port(
input : in std_logic_vector(11 downto 0);
output : out std_logic_vector(3 downto 0));
end entity;
architecture rtl of alt_dspbuilder_cast_GN76IOUHQH is
Begin
-- Output - I/O assignment from Simulink Block "Output"
Outputi : alt_dspbuilder_SBF generic map(
width_inl=> 4 + 1 ,
width_inr=> 8,
width_outl=> 4,
width_outr=> 0,
lpm_signed=> BusIsUnsigned ,
round=> round,
satur=> saturate)
port map (
xin(11 downto 0) => input,
xin(12) => '0', yout => output
);
end architecture; |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_cast_GN76IOUHQH is
generic ( round : natural := 0;
saturate : natural := 0);
port(
input : in std_logic_vector(11 downto 0);
output : out std_logic_vector(3 downto 0));
end entity;
architecture rtl of alt_dspbuilder_cast_GN76IOUHQH is
Begin
-- Output - I/O assignment from Simulink Block "Output"
Outputi : alt_dspbuilder_SBF generic map(
width_inl=> 4 + 1 ,
width_inr=> 8,
width_outl=> 4,
width_outr=> 0,
lpm_signed=> BusIsUnsigned ,
round=> round,
satur=> saturate)
port map (
xin(11 downto 0) => input,
xin(12) => '0', yout => output
);
end architecture; |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_cast_GN76IOUHQH is
generic ( round : natural := 0;
saturate : natural := 0);
port(
input : in std_logic_vector(11 downto 0);
output : out std_logic_vector(3 downto 0));
end entity;
architecture rtl of alt_dspbuilder_cast_GN76IOUHQH is
Begin
-- Output - I/O assignment from Simulink Block "Output"
Outputi : alt_dspbuilder_SBF generic map(
width_inl=> 4 + 1 ,
width_inr=> 8,
width_outl=> 4,
width_outr=> 0,
lpm_signed=> BusIsUnsigned ,
round=> round,
satur=> saturate)
port map (
xin(11 downto 0) => input,
xin(12) => '0', yout => output
);
end architecture; |
-- count number of '1'.
library ieee;
use ieee.std_logic_1164.all;
entity ent is
port (
sel : in std_ulogic;
din : in std_ulogic_vector(15 downto 0);
dout : out std_ulogic
);
end;
architecture rtl of ent is
begin
comb : process (sel, din)
variable v : std_ulogic;
begin
v := '0';
if sel = '1' then
for i in din'range loop
if din(i) = '0' then
next;
end if;
v := not v;
end loop;
end if;
dout <= v;
end process;
end;
|
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
LIBRARY UNISIM;
USE UNISIM.vcomponents.ALL;
ENTITY CLK IS
PORT
(
reset, clk_input : IN STD_LOGIC;
clk_output : OUT STD_LOGIC
);
END CLK;
ARCHITECTURE Behavioral OF clk IS
SIGNAL sig_clk, clkfb : STD_LOGIC;
BEGIN
-- force sig_CLK_108MHZ to use a BUFG for clock distribution
i_CLK_BUFG : BUFG PORT MAP
(I => sig_clk, O => clk_output);
i_DCM_SP : DCM_SP
GENERIC
MAP(
CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
-- 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
CLKFX_DIVIDE => 4, -- Can be any interger from 1 to 32
CLKFX_MULTIPLY => 9, -- Can be any integer from 1 to 32
CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature
CLKIN_PERIOD => 20.833000, -- Specify period of input clock
CLKOUT_PHASE_SHIFT => "NONE", -- Specify phase shift of "NONE", "FIXED" or "VARIABLE"
CLK_FEEDBACK => "1X", -- Specify clock feedback of "NONE", "1X" or "2X"
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", -- "SOURCE_SYNCHRONOUS", "SYSTEM_SYNCHRONOUS" or
-- an integer from 0 to 15
DLL_FREQUENCY_MODE => "LOW", -- "HIGH" or "LOW" frequency mode for DLL
DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE
PHASE_SHIFT => 0, -- Amount of fixed phase shift from -255 to 255
STARTUP_WAIT => TRUE) -- Delay configuration DONE until DCM_SP LOCK, TRUE/FALSE
PORT
MAP(
CLK0 => clkfb, -- 0 degree DCM CLK ouptput
-- CLK180 => CLK180, -- 180 degree DCM CLK output
-- CLK270 => CLK270, -- 270 degree DCM CLK output
-- CLK2X => CLK2X, -- 2X DCM CLK output
-- CLK2X180 => CLK2X180, -- 2X, 180 degree DCM CLK out
-- CLK90 => CLK90, -- 90 degree DCM CLK output
-- CLKDV => CLKDV, -- Divided DCM CLK out (CLKDV_DIVIDE)
CLKFX => sig_CLK, -- DCM CLK synthesis out (M/D)
-- CLKFX180 => CLKFX180, -- 180 degree CLK synthesis out
-- LOCKED => LOCKED, -- DCM LOCK status output
-- PSDONE => PSDONE, -- Dynamic phase adjust done output
-- STATUS => STATUS, -- 8-bit DCM status bits output
CLKFB => clkfb, -- DCM clock feedback
CLKIN => clk_input, -- Clock input (from IBUFG, BUFG or DCM)
-- PSCLK => PSCLK, -- Dynamic phase adjust clock input
-- PSEN => PSEN, -- Dynamic phase adjust enable input
-- PSINCDEC => PSINCDEC, -- Dynamic phase adjust increment/decrement
RST => reset -- DCM asynchronous reset input
);
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 14:58:07 09/10/2009
-- Design Name:
-- Module Name: /home/abaez/ise_projects/complete_pic/src//complete_pic_test.vhd
-- Project Name: ise_proj
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: complete_pic
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY complete_pic_test IS
generic (
C_NUM_INTERRUPTS : integer := 8;
C_REG_SIZE : integer := 9;
C_CMD_WIDTH : integer := 4;
)
END complete_pic_test;
ARCHITECTURE behavior OF complete_pic_test IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT complete_pic
PORT(
msg_chan_channelDataIn : OUT std_logic_vector(0 to 7);
msg_chan_channelDataOut : IN std_logic_vector(0 to 7);
msg_chan_exists : IN std_logic;
msg_chan_full : IN std_logic;
msg_chan_channelRead : OUT std_logic;
msg_chan_channelWrite : OUT std_logic;
go : IN std_logic;
ack : OUT std_logic;
TID_IN : IN std_logic_vector(0 to 7);
IID_IN : IN std_logic_vector(0 to log2(C_NUM_INTERRUPTS)-1);
CMD_IN : IN std_logic_vector(0 to C_CMD_WIDTH-1);
RET_OUT : OUT std_logic_vector(0 to 7);
TID_OUT : OUT std_logic_vector(0 to 7);
interrupts_in : IN std_logic_vector(0 to C_NUM_INTERRUPTS-1);
clock_sig : IN std_logic;
reset_sig : IN std_logic
);
END COMPONENT;
--Inputs
signal msg_chan_channelDataOut : std_logic_vector(0 to 7) := (others => '0');
signal msg_chan_exists : std_logic := '0';
signal msg_chan_full : std_logic := '0';
signal go : std_logic := '0';
signal TID_IN : std_logic_vector(0 to 7) := (others => '0');
signal IID_IN : std_logic_vector(0 to log2(C_NUM_INTERRUPTS)-1) := (others => '0');
signal CMD_IN : std_logic_vector(0 to C_CMD_WIDTH-1) := (others => '0');
signal interrupts_in : std_logic_vector(0 to C_CMD_WIDTH-1) := (others => '0');
signal clock_sig : std_logic := '0';
signal reset_sig : std_logic := '0';
--Outputs
signal msg_chan_channelDataIn : std_logic_vector(0 to 7);
signal msg_chan_channelRead : std_logic;
signal msg_chan_channelWrite : std_logic;
signal ack : std_logic;
signal RET_OUT : std_logic_vector(0 to 7);
signal TID_OUT : std_logic_vector(0 to 7);
-- Clock period definitions
constant clock_sig_period : time := 1 us;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: complete_pic PORT MAP (
msg_chan_channelDataIn => msg_chan_channelDataIn,
msg_chan_channelDataOut => msg_chan_channelDataOut,
msg_chan_exists => msg_chan_exists,
msg_chan_full => msg_chan_full,
msg_chan_channelRead => msg_chan_channelRead,
msg_chan_channelWrite => msg_chan_channelWrite,
go => go,
ack => ack,
TID_IN => TID_IN,
IID_IN => IID_IN,
CMD_IN => CMD_IN,
RET_OUT => RET_OUT,
TID_OUT => TID_OUT,
interrupts_in => interrupts_in,
clock_sig => clock_sig,
reset_sig => reset_sig
);
-- Clock process definitions
clock_sig_process :process
begin
clock_sig <= '0';
wait for clock_sig_period/2;
clock_sig <= '1';
wait for clock_sig_period/2;
end process;
-- Calculate the log base 2 of some natural number. This function can be
-- used to determine the minimum number of bits needed to represent the
-- given natural number.
function log2( n : in natural ) return positive is
begin
if n <= 2 then
return 1;
else
return 1 + log2(n/2);
end if;
end function log2;
-- Stimulus process
stim_proc: process
procedure assoc(tid : in std_logic_vector(0 to 7); iid : in std_logic_vector(0 to log2(C_NUM_INTERRUPTS)-1)) is
begin
wait until clock_sig = '0';
TID_IN <= tid;
IID_IN <= iid;
CMD_IN <= "0001";
go <= '1';
wait until ack = '1';
wait for 2*clock_sig_period;
TID_IN <= tid;
IID_IN <= iid;
CMD_IN <= "0001";
go <= '0';
wait until ack = '0';
end procedure assoc;
procedure read_entry(tid : in std_logic_vector(0 to 7); iid : in std_logic_vector(0 to log2(C_NUM_INTERRUPTS)-1)) is
begin
wait until clock_sig = '0';
TID_IN <= tid;
IID_IN <= iid;
CMD_IN <= "0000";
go <= '1';
wait until ack = '1';
wait for 2*clock_sig_period;
TID_IN <= tid;
IID_IN <= iid;
CMD_IN <= "0000";
go <= '0';
wait until ack = '0';
end procedure read_entry;
procedure clear_entry(tid : in std_logic_vector(0 to 7); iid : in std_logic_vector(0 to log2(C_NUM_INTERRUPTS)-1)) is
begin
wait until clock_sig = '0';
TID_IN <= tid;
IID_IN <= iid;
CMD_IN <= "0010";
go <= '1';
wait until ack = '1';
wait for 2*clock_sig_period;
TID_IN <= tid;
IID_IN <= iid;
CMD_IN <= "0010";
go <= '0';
wait until ack = '0';
end procedure clear_entry;
procedure generate_interrupt(intr : in std_logic_vector(0 to C_NUM_INTERRUPTS-1)) is
begin
wait until clock_sig = '0';
interrupts_in <= intr;
wait until clock_sig = '1';
wait for 5*clock_sig_period;
end procedure generate_interrupt;
begin
-- hold reset state for 100ms.
wait for 50 ns;
reset_sig <= '1';
wait for clock_sig_period;
reset_sig <= '0';
wait for 5*clock_sig_period;
-- insert stimulus here
go <= '0';
-- start. Write into memory #2 and #3 values 15 and 8.
assoc("00001111","010");
assoc("00001000","011");
-- Change the command to interrupt read an empty register
generate_interrupt("0100");
read_entry("00001010","010");
-- write another TID to memory #0
assoc("10110000","000");
-- specify another write to already chosen memory #0 - failure condition
assoc("00100000","000");
-- Set go to LOW and try to write.
wait for 4*clock_sig_period;
go <= '0';
TID_IN <= "11001100";
IID_IN <= "10";
-- Generate an interrupt for registers #0,#1 and #3
generate_interrupt("1101");
-- read memory address 3
read_entry("00110011","011");
-- Generate last interrupt
wait for 5*clock_sig_period;
generate_interrupt("1111");
wait;
end process;
END;
|
-- -------------------------------------------------------------
--
-- File Name: hdl_prj/hdlsrc/OFDM_transmitter/Complex3Multiply_block4.vhd
-- Created: 2017-03-27 15:50:06
--
-- Generated by MATLAB 9.1 and HDL Coder 3.9
--
-- -------------------------------------------------------------
-- -------------------------------------------------------------
--
-- Module: Complex3Multiply_block4
-- Source Path: OFDM_transmitter/IFFT HDL Optimized/TWDLMULT_SDNF1_3/Complex3Multiply
-- Hierarchy Level: 3
--
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY Complex3Multiply_block4 IS
PORT( clk : IN std_logic;
reset : IN std_logic;
enb_1_16_0 : IN std_logic;
din2_re_dly3 : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
din2_im_dly3 : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
di2_vld_dly3 : IN std_logic;
twdl_3_8_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En14
twdl_3_8_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En14
softReset : IN std_logic;
twdlXdin_8_re : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_8_im : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin2_vld : OUT std_logic
);
END Complex3Multiply_block4;
ARCHITECTURE rtl OF Complex3Multiply_block4 IS
-- Signals
SIGNAL din2_re_dly3_signed : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL din_re_reg : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL din2_im_dly3_signed : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL din_im_reg : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL adder_add_cast : signed(16 DOWNTO 0); -- sfix17_En13
SIGNAL adder_add_cast_1 : signed(16 DOWNTO 0); -- sfix17_En13
SIGNAL din_sum : signed(16 DOWNTO 0); -- sfix17_En13
SIGNAL twdl_3_8_re_signed : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL twdl_re_reg : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL twdl_3_8_im_signed : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL twdl_im_reg : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL adder_add_cast_2 : signed(16 DOWNTO 0); -- sfix17_En14
SIGNAL adder_add_cast_3 : signed(16 DOWNTO 0); -- sfix17_En14
SIGNAL twdl_sum : signed(16 DOWNTO 0); -- sfix17_En14
SIGNAL Complex3Multiply_din1_re_pipe1 : signed(15 DOWNTO 0); -- sfix16
SIGNAL Complex3Multiply_din1_im_pipe1 : signed(15 DOWNTO 0); -- sfix16
SIGNAL Complex3Multiply_din1_sum_pipe1 : signed(16 DOWNTO 0); -- sfix17
SIGNAL Complex3Multiply_prodOfRe_pipe1 : signed(31 DOWNTO 0); -- sfix32
SIGNAL Complex3Multiply_ProdOfIm_pipe1 : signed(31 DOWNTO 0); -- sfix32
SIGNAL Complex3Multiply_prodOfSum_pipe1 : signed(33 DOWNTO 0); -- sfix34
SIGNAL Complex3Multiply_twiddle_re_pipe1 : signed(15 DOWNTO 0); -- sfix16
SIGNAL Complex3Multiply_twiddle_im_pipe1 : signed(15 DOWNTO 0); -- sfix16
SIGNAL Complex3Multiply_twiddle_sum_pipe1 : signed(16 DOWNTO 0); -- sfix17
SIGNAL prodOfRe : signed(31 DOWNTO 0); -- sfix32_En27
SIGNAL prodOfIm : signed(31 DOWNTO 0); -- sfix32_En27
SIGNAL prodOfSum : signed(33 DOWNTO 0); -- sfix34_En27
SIGNAL din_vld_dly1 : std_logic;
SIGNAL din_vld_dly2 : std_logic;
SIGNAL din_vld_dly3 : std_logic;
SIGNAL prod_vld : std_logic;
SIGNAL Complex3Add_tmpResult_reg : signed(33 DOWNTO 0); -- sfix34
SIGNAL Complex3Add_multRes_re_reg1 : signed(32 DOWNTO 0); -- sfix33
SIGNAL Complex3Add_multRes_re_reg2 : signed(32 DOWNTO 0); -- sfix33
SIGNAL Complex3Add_multRes_im_reg : signed(34 DOWNTO 0); -- sfix35
SIGNAL Complex3Add_prod_vld_reg1 : std_logic;
SIGNAL Complex3Add_prod_vld_reg2 : std_logic;
SIGNAL Complex3Add_prodOfSum_reg : signed(33 DOWNTO 0); -- sfix34
SIGNAL Complex3Add_tmpResult_reg_next : signed(33 DOWNTO 0); -- sfix34_En27
SIGNAL Complex3Add_multRes_re_reg1_next : signed(32 DOWNTO 0); -- sfix33_En27
SIGNAL Complex3Add_multRes_re_reg2_next : signed(32 DOWNTO 0); -- sfix33_En27
SIGNAL Complex3Add_multRes_im_reg_next : signed(34 DOWNTO 0); -- sfix35_En27
SIGNAL Complex3Add_prod_vld_reg1_next : std_logic;
SIGNAL Complex3Add_prod_vld_reg2_next : std_logic;
SIGNAL Complex3Add_prodOfSum_reg_next : signed(33 DOWNTO 0); -- sfix34_En27
SIGNAL multResFP_re : signed(32 DOWNTO 0); -- sfix33_En27
SIGNAL multResFP_im : signed(34 DOWNTO 0); -- sfix35_En27
SIGNAL twdlXdin_8_re_tmp : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL twdlXdin_8_im_tmp : signed(15 DOWNTO 0); -- sfix16_En13
BEGIN
din2_re_dly3_signed <= signed(din2_re_dly3);
intdelay_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din_re_reg <= to_signed(16#0000#, 16);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
IF softReset = '1' THEN
din_re_reg <= to_signed(16#0000#, 16);
ELSE
din_re_reg <= din2_re_dly3_signed;
END IF;
END IF;
END IF;
END PROCESS intdelay_process;
din2_im_dly3_signed <= signed(din2_im_dly3);
intdelay_1_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din_im_reg <= to_signed(16#0000#, 16);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
IF softReset = '1' THEN
din_im_reg <= to_signed(16#0000#, 16);
ELSE
din_im_reg <= din2_im_dly3_signed;
END IF;
END IF;
END IF;
END PROCESS intdelay_1_process;
adder_add_cast <= resize(din_re_reg, 17);
adder_add_cast_1 <= resize(din_im_reg, 17);
din_sum <= adder_add_cast + adder_add_cast_1;
twdl_3_8_re_signed <= signed(twdl_3_8_re);
intdelay_2_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
twdl_re_reg <= to_signed(16#0000#, 16);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
IF softReset = '1' THEN
twdl_re_reg <= to_signed(16#0000#, 16);
ELSE
twdl_re_reg <= twdl_3_8_re_signed;
END IF;
END IF;
END IF;
END PROCESS intdelay_2_process;
twdl_3_8_im_signed <= signed(twdl_3_8_im);
intdelay_3_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
twdl_im_reg <= to_signed(16#0000#, 16);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
IF softReset = '1' THEN
twdl_im_reg <= to_signed(16#0000#, 16);
ELSE
twdl_im_reg <= twdl_3_8_im_signed;
END IF;
END IF;
END IF;
END PROCESS intdelay_3_process;
adder_add_cast_2 <= resize(twdl_re_reg, 17);
adder_add_cast_3 <= resize(twdl_im_reg, 17);
twdl_sum <= adder_add_cast_2 + adder_add_cast_3;
-- Complex3Multiply
Complex3Multiply_process : PROCESS (clk)
BEGIN
IF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
prodOfRe <= Complex3Multiply_prodOfRe_pipe1;
prodOfIm <= Complex3Multiply_ProdOfIm_pipe1;
prodOfSum <= Complex3Multiply_prodOfSum_pipe1;
Complex3Multiply_twiddle_re_pipe1 <= twdl_re_reg;
Complex3Multiply_twiddle_im_pipe1 <= twdl_im_reg;
Complex3Multiply_twiddle_sum_pipe1 <= twdl_sum;
Complex3Multiply_din1_re_pipe1 <= din_re_reg;
Complex3Multiply_din1_im_pipe1 <= din_im_reg;
Complex3Multiply_din1_sum_pipe1 <= din_sum;
Complex3Multiply_prodOfRe_pipe1 <= Complex3Multiply_din1_re_pipe1 * Complex3Multiply_twiddle_re_pipe1;
Complex3Multiply_ProdOfIm_pipe1 <= Complex3Multiply_din1_im_pipe1 * Complex3Multiply_twiddle_im_pipe1;
Complex3Multiply_prodOfSum_pipe1 <= Complex3Multiply_din1_sum_pipe1 * Complex3Multiply_twiddle_sum_pipe1;
END IF;
END IF;
END PROCESS Complex3Multiply_process;
intdelay_4_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din_vld_dly1 <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
din_vld_dly1 <= di2_vld_dly3;
END IF;
END IF;
END PROCESS intdelay_4_process;
intdelay_5_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din_vld_dly2 <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
din_vld_dly2 <= din_vld_dly1;
END IF;
END IF;
END PROCESS intdelay_5_process;
intdelay_6_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din_vld_dly3 <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
din_vld_dly3 <= din_vld_dly2;
END IF;
END IF;
END PROCESS intdelay_6_process;
intdelay_7_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
prod_vld <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
prod_vld <= din_vld_dly3;
END IF;
END IF;
END PROCESS intdelay_7_process;
-- Complex3Add
Complex3Add_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
Complex3Add_prodOfSum_reg <= to_signed(0, 34);
Complex3Add_tmpResult_reg <= to_signed(0, 34);
Complex3Add_multRes_re_reg1 <= to_signed(0, 33);
Complex3Add_multRes_re_reg2 <= to_signed(0, 33);
Complex3Add_multRes_im_reg <= to_signed(0, 35);
Complex3Add_prod_vld_reg1 <= '0';
Complex3Add_prod_vld_reg2 <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
Complex3Add_tmpResult_reg <= Complex3Add_tmpResult_reg_next;
Complex3Add_multRes_re_reg1 <= Complex3Add_multRes_re_reg1_next;
Complex3Add_multRes_re_reg2 <= Complex3Add_multRes_re_reg2_next;
Complex3Add_multRes_im_reg <= Complex3Add_multRes_im_reg_next;
Complex3Add_prod_vld_reg1 <= Complex3Add_prod_vld_reg1_next;
Complex3Add_prod_vld_reg2 <= Complex3Add_prod_vld_reg2_next;
Complex3Add_prodOfSum_reg <= Complex3Add_prodOfSum_reg_next;
END IF;
END IF;
END PROCESS Complex3Add_process;
Complex3Add_output : PROCESS (Complex3Add_tmpResult_reg, Complex3Add_multRes_re_reg1,
Complex3Add_multRes_re_reg2, Complex3Add_multRes_im_reg,
Complex3Add_prod_vld_reg1, Complex3Add_prod_vld_reg2,
Complex3Add_prodOfSum_reg, prodOfRe, prodOfIm, prodOfSum, prod_vld)
VARIABLE sub_cast : signed(32 DOWNTO 0);
VARIABLE sub_cast_0 : signed(32 DOWNTO 0);
VARIABLE sub_cast_1 : signed(34 DOWNTO 0);
VARIABLE sub_cast_2 : signed(34 DOWNTO 0);
VARIABLE add_cast : signed(32 DOWNTO 0);
VARIABLE add_cast_0 : signed(32 DOWNTO 0);
VARIABLE add_temp : signed(32 DOWNTO 0);
BEGIN
Complex3Add_tmpResult_reg_next <= Complex3Add_tmpResult_reg;
Complex3Add_multRes_re_reg1_next <= Complex3Add_multRes_re_reg1;
Complex3Add_prodOfSum_reg_next <= Complex3Add_prodOfSum_reg;
Complex3Add_multRes_re_reg2_next <= Complex3Add_multRes_re_reg1;
IF prod_vld = '1' THEN
sub_cast := resize(prodOfRe, 33);
sub_cast_0 := resize(prodOfIm, 33);
Complex3Add_multRes_re_reg1_next <= sub_cast - sub_cast_0;
END IF;
sub_cast_1 := resize(Complex3Add_prodOfSum_reg, 35);
sub_cast_2 := resize(Complex3Add_tmpResult_reg, 35);
Complex3Add_multRes_im_reg_next <= sub_cast_1 - sub_cast_2;
IF prod_vld = '1' THEN
add_cast := resize(prodOfRe, 33);
add_cast_0 := resize(prodOfIm, 33);
add_temp := add_cast + add_cast_0;
Complex3Add_tmpResult_reg_next <= resize(add_temp, 34);
END IF;
IF prod_vld = '1' THEN
Complex3Add_prodOfSum_reg_next <= prodOfSum;
END IF;
Complex3Add_prod_vld_reg2_next <= Complex3Add_prod_vld_reg1;
Complex3Add_prod_vld_reg1_next <= prod_vld;
multResFP_re <= Complex3Add_multRes_re_reg2;
multResFP_im <= Complex3Add_multRes_im_reg;
twdlXdin2_vld <= Complex3Add_prod_vld_reg2;
END PROCESS Complex3Add_output;
twdlXdin_8_re_tmp <= multResFP_re(29 DOWNTO 14);
twdlXdin_8_re <= std_logic_vector(twdlXdin_8_re_tmp);
twdlXdin_8_im_tmp <= multResFP_im(29 DOWNTO 14);
twdlXdin_8_im <= std_logic_vector(twdlXdin_8_im_tmp);
END rtl;
|
-- Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2014.3 (lin64) Build 1034051 Fri Oct 3 16:31:15 MDT 2014
-- Date : Sun Oct 25 15:45:18 2015
-- Host : arthas-ubuntu running 64-bit Ubuntu 14.04.3 LTS
-- Command : write_vhdl -force -mode synth_stub
-- /home/arthas/git/SHD/SHD.srcs/sources_1/ip/shd_pe_fifo/shd_pe_fifo_stub.vhdl
-- Design : shd_pe_fifo
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7vx690tffg1761-2
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity shd_pe_fifo is
Port (
rst : in STD_LOGIC;
wr_clk : in STD_LOGIC;
rd_clk : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 7 downto 0 );
wr_en : in STD_LOGIC;
rd_en : in STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 7 downto 0 );
full : out STD_LOGIC;
empty : out STD_LOGIC
);
end shd_pe_fifo;
architecture stub of shd_pe_fifo is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "rst,wr_clk,rd_clk,din[7:0],wr_en,rd_en,dout[7:0],full,empty";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "fifo_generator_v12_0,Vivado 2014.3";
begin
end;
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12:12:46 09/15/2014
-- Design Name:
-- Module Name: H:/Documents/md5_test/tb_md5.vhd
-- Project Name: md5_test
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: MD5
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use ieee.numeric_std.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY tb_md5 IS
END tb_md5;
ARCHITECTURE behavior OF tb_md5 IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT MD5
PORT(
i_clk : IN std_logic;
i_rst_n : IN std_logic;
i_start : IN std_logic;
i_data : IN unsigned(71 downto 0);
o_done : OUT std_logic;
o_hash_0 : OUT unsigned(31 downto 0);
o_hash_1 : OUT unsigned(31 downto 0);
o_hash_2 : OUT unsigned(31 downto 0);
o_hash_3 : OUT unsigned(31 downto 0)
);
END COMPONENT;
--Inputs
signal i_clk : std_logic := '0';
signal i_rst_n : std_logic := '1';
signal i_start : std_logic := '0';
signal i_data : unsigned(71 downto 0) := (others => '0');
--Outputs
signal o_done : std_logic;
signal o_hash_0, o_hash_1, o_hash_2, o_hash_3 : unsigned(31 downto 0);
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: MD5 PORT MAP (
i_clk => i_clk,
i_rst_n => i_rst_n,
i_start => i_start,
i_data => i_data,
o_done => o_done,
o_hash_0 => o_hash_0,
o_hash_1 => o_hash_1,
o_hash_2 => o_hash_2,
o_hash_3 => o_hash_3
);
-- Clock process definitions
clk_process :process
begin
i_clk <= '0';
wait for clk_period/2;
i_clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
wait for clk_period/2;
i_rst_n <= '0';
wait for clk_period;
i_rst_n <= '1';
i_start <= '1';
i_data <= x"626161616161616180";
--i_data <= (others => '1');
wait for clk_period;
-- insert stimulus here
wait;
end process;
END;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.plasoc_uart_pack.all;
entity generic_fifo is
generic (
FIFO_WIDTH : positive := 32;
FIFO_DEPTH : positive := 1024
);
port (
clock : in std_logic;
nreset : in std_logic;
write_data : in std_logic_vector(FIFO_WIDTH-1 downto 0);
read_data : out std_logic_vector(FIFO_WIDTH-1 downto 0);
write_en : in std_logic;
read_en : in std_logic;
full : out std_logic;
empty : out std_logic;
level : out std_logic_vector(clogb2(FIFO_DEPTH)-1 downto 0
)
);
end entity;
architecture RTL of generic_fifo is
---------------------------------------------------------------------------
-- Functions
---------------------------------------------------------------------------
function get_fifo_level(
write_pointer : unsigned;
read_pointer : unsigned;
depth : positive) return integer is
begin
if write_pointer > read_pointer then
return to_integer(write_pointer - read_pointer);
elsif write_pointer = read_pointer then
return 0;
else
return (
((depth) - to_integer(read_pointer)) +
to_integer(write_pointer)
);
end if;
end function get_fifo_level;
---------------------------------------------------------------------------
-- Types
---------------------------------------------------------------------------
type memory is array (0 to FIFO_DEPTH-1) of std_logic_vector(
FIFO_WIDTH-1 downto 0
);
---------------------------------------------------------------------------
-- Signals
---------------------------------------------------------------------------
signal fifo_memory : memory := (others => (others => '0'));
signal read_pointer, write_pointer : unsigned(clogb2(FIFO_DEPTH)-1 downto 0) := (others => '0');
signal fifo_empty : std_logic := '1';
signal fifo_full : std_logic := '0';
begin
full <= fifo_full;
empty <= fifo_empty;
FIFO_FLAGS : process(write_pointer, read_pointer) is
variable lev : integer range 0 to FIFO_DEPTH - 1;
begin
lev := get_fifo_level(write_pointer, read_pointer, FIFO_DEPTH);
level <= std_logic_vector(to_unsigned(lev, level'length));
if lev = FIFO_DEPTH - 1 then
fifo_full <= '1';
else
fifo_full <= '0';
end if;
if lev = 0 then
fifo_empty <= '1';
else
fifo_empty <= '0';
end if;
end process;
FIFO_LOGIC : process(clock) is
begin
if rising_edge(clock) then
if nreset = '0' then
write_pointer <= (others => '0');
read_pointer <= (others => '0');
else
-- FIFO WRITE
if write_en = '1' and fifo_full = '0' then
fifo_memory(to_integer(write_pointer)) <= write_data;
if write_pointer < FIFO_DEPTH - 1 then
write_pointer <= write_pointer + 1;
else
write_pointer <= (others => '0');
end if;
end if;
-- FIFO READ
if read_en = '1' and fifo_empty = '0' then
if read_pointer < FIFO_DEPTH - 1 then
read_pointer <= read_pointer + 1;
else
read_pointer <= (others => '0');
end if;
end if;
end if;
end if;
end process;
read_data <= fifo_memory(to_integer(read_pointer));
end RTL;
|
-- Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2014.3.1 (lin64) Build 1056140 Thu Oct 30 16:30:39 MDT 2014
-- Date : Wed Apr 8 23:17:20 2015
-- Host : parallella running 64-bit Ubuntu 14.04.2 LTS
-- Command : write_vhdl -force -mode synth_stub
-- /home/aolofsson/Work_all/parallella-hw/fpga/ip/xilinx/axi_bram_ctrl_16b/axi_bram_ctrl_16b_stub.vhdl
-- Design : axi_bram_ctrl_16b
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z010clg400-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity axi_bram_ctrl_16b is
Port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 15 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 15 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
bram_rst_a : out STD_LOGIC;
bram_clk_a : out STD_LOGIC;
bram_en_a : out STD_LOGIC;
bram_we_a : out STD_LOGIC_VECTOR ( 3 downto 0 );
bram_addr_a : out STD_LOGIC_VECTOR ( 15 downto 0 );
bram_wrdata_a : out STD_LOGIC_VECTOR ( 31 downto 0 );
bram_rddata_a : in STD_LOGIC_VECTOR ( 31 downto 0 )
);
end axi_bram_ctrl_16b;
architecture stub of axi_bram_ctrl_16b is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "s_axi_aclk,s_axi_aresetn,s_axi_awaddr[15:0],s_axi_awprot[2:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wvalid,s_axi_wready,s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_araddr[15:0],s_axi_arprot[2:0],s_axi_arvalid,s_axi_arready,s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rvalid,s_axi_rready,bram_rst_a,bram_clk_a,bram_en_a,bram_we_a[3:0],bram_addr_a[15:0],bram_wrdata_a[31:0],bram_rddata_a[31:0]";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "axi_bram_ctrl,Vivado 2014.3.1";
begin
end;
|
entity issue436 is
end entity;
architecture MODEL of issue436 is
type VEC_RANGE_TYPE is record
DATA_LO : integer;
DATA_HI : integer;
end record;
function SET_VEC_RANGE return VEC_RANGE_TYPE is
variable v : VEC_RANGE_TYPE;
begin
v.DATA_HI := 31;
v.DATA_LO := 0;
return v;
end function;
constant VEC_RANGE : VEC_RANGE_TYPE := SET_VEC_RANGE;
signal data : bit_vector(VEC_RANGE.DATA_HI downto VEC_RANGE.DATA_LO);
type int_vector is array (natural range <>) of integer;
function get_array return int_vector is
variable v : int_vector(1 to 3);
begin
v := (1, 2, 3);
return v;
end function;
constant c2 : int_vector := get_array;
signal data2 : bit_vector(c2(2) downto 0);
begin
end MODEL;
|
library ieee;
use ieee.std_logic_1164.all;
package miscellaneous is
component ClockGenerator
port (
Clk : in std_ulogic;
Reset : in std_ulogic;
oMCLK : out std_ulogic;
oBCLK : out std_ulogic;
oSCLK : out std_ulogic;
oLRCOUT : out std_ulogic);
end component;
component vgaclkgen
PORT
(
areset : IN STD_LOGIC := '0';
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC ;
locked : OUT STD_LOGIC
);
end component;
component Clk100MhzTo40MHz
PORT
(
inclk0 : IN STD_LOGIC := '0';
pllena : IN STD_LOGIC := '1';
areset : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC ;
locked : OUT STD_LOGIC
);
end component;
-- Gleichmann board types
constant compact_v1 : integer := 1;
constant compact_v2 : integer := 2;
constant mini_altera : integer := 3;
constant mini_lattice : integer := 4;
constant mini_lattice2 : integer := 5;
constant midi : integer := 6;
end miscellaneous;
|
library ieee;
use ieee.std_logic_1164.all;
package miscellaneous is
component ClockGenerator
port (
Clk : in std_ulogic;
Reset : in std_ulogic;
oMCLK : out std_ulogic;
oBCLK : out std_ulogic;
oSCLK : out std_ulogic;
oLRCOUT : out std_ulogic);
end component;
component vgaclkgen
PORT
(
areset : IN STD_LOGIC := '0';
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC ;
locked : OUT STD_LOGIC
);
end component;
component Clk100MhzTo40MHz
PORT
(
inclk0 : IN STD_LOGIC := '0';
pllena : IN STD_LOGIC := '1';
areset : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC ;
locked : OUT STD_LOGIC
);
end component;
-- Gleichmann board types
constant compact_v1 : integer := 1;
constant compact_v2 : integer := 2;
constant mini_altera : integer := 3;
constant mini_lattice : integer := 4;
constant mini_lattice2 : integer := 5;
constant midi : integer := 6;
end miscellaneous;
|
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity w_split7 is
port (
clk : in std_logic;
ra0_data : out std_logic_vector(7 downto 0);
wa0_data : in std_logic_vector(7 downto 0);
wa0_addr : in std_logic;
wa0_en : in std_logic;
ra0_addr : in std_logic
);
end w_split7;
architecture augh of w_split7 is
-- Embedded RAM
type ram_type is array (0 to 1) of std_logic_vector(7 downto 0);
signal ram : ram_type := (
"00000111", "00000111"
);
-- Little utility functions to make VHDL syntactically correct
-- with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic.
-- This happens when accessing arrays with <= 2 cells, for example.
function to_integer(B: std_logic) return integer is
variable V: std_logic_vector(0 to 0);
begin
V(0) := B;
return to_integer(unsigned(V));
end;
function to_integer(V: std_logic_vector) return integer is
begin
return to_integer(unsigned(V));
end;
begin
-- Sequential process
-- It handles the Writes
process (clk)
begin
if rising_edge(clk) then
-- Write to the RAM
-- Note: there should be only one port.
if wa0_en = '1' then
ram( to_integer(wa0_addr) ) <= wa0_data;
end if;
end if;
end process;
-- The Read side (the outputs)
ra0_data <= ram( to_integer(ra0_addr) );
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity w_split7 is
port (
clk : in std_logic;
ra0_data : out std_logic_vector(7 downto 0);
wa0_data : in std_logic_vector(7 downto 0);
wa0_addr : in std_logic;
wa0_en : in std_logic;
ra0_addr : in std_logic
);
end w_split7;
architecture augh of w_split7 is
-- Embedded RAM
type ram_type is array (0 to 1) of std_logic_vector(7 downto 0);
signal ram : ram_type := (
"00000111", "00000111"
);
-- Little utility functions to make VHDL syntactically correct
-- with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic.
-- This happens when accessing arrays with <= 2 cells, for example.
function to_integer(B: std_logic) return integer is
variable V: std_logic_vector(0 to 0);
begin
V(0) := B;
return to_integer(unsigned(V));
end;
function to_integer(V: std_logic_vector) return integer is
begin
return to_integer(unsigned(V));
end;
begin
-- Sequential process
-- It handles the Writes
process (clk)
begin
if rising_edge(clk) then
-- Write to the RAM
-- Note: there should be only one port.
if wa0_en = '1' then
ram( to_integer(wa0_addr) ) <= wa0_data;
end if;
end if;
end process;
-- The Read side (the outputs)
ra0_data <= ram( to_integer(ra0_addr) );
end architecture;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:ieee754_fp_to_uint:1.0
-- IP Revision: 2
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY affine_block_ieee754_fp_to_uint_0_0 IS
PORT (
x : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
y : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
);
END affine_block_ieee754_fp_to_uint_0_0;
ARCHITECTURE affine_block_ieee754_fp_to_uint_0_0_arch OF affine_block_ieee754_fp_to_uint_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF affine_block_ieee754_fp_to_uint_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT ieee754_fp_to_uint IS
GENERIC (
WIDTH : INTEGER
);
PORT (
x : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
y : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
);
END COMPONENT ieee754_fp_to_uint;
BEGIN
U0 : ieee754_fp_to_uint
GENERIC MAP (
WIDTH => 10
)
PORT MAP (
x => x,
y => y
);
END affine_block_ieee754_fp_to_uint_0_0_arch;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:ieee754_fp_to_uint:1.0
-- IP Revision: 2
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY affine_block_ieee754_fp_to_uint_0_0 IS
PORT (
x : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
y : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
);
END affine_block_ieee754_fp_to_uint_0_0;
ARCHITECTURE affine_block_ieee754_fp_to_uint_0_0_arch OF affine_block_ieee754_fp_to_uint_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF affine_block_ieee754_fp_to_uint_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT ieee754_fp_to_uint IS
GENERIC (
WIDTH : INTEGER
);
PORT (
x : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
y : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
);
END COMPONENT ieee754_fp_to_uint;
BEGIN
U0 : ieee754_fp_to_uint
GENERIC MAP (
WIDTH => 10
)
PORT MAP (
x => x,
y => y
);
END affine_block_ieee754_fp_to_uint_0_0_arch;
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2013.4
-- Copyright (C) 2013 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity nfa_accept_samples_generic_hw_mul_8ns_6ns_14_9_MulnS_1 is
port (
clk: in std_logic;
ce: in std_logic;
a: in std_logic_vector(8 - 1 downto 0);
b: in std_logic_vector(6 - 1 downto 0);
p: out std_logic_vector(14 - 1 downto 0));
end entity;
architecture behav of nfa_accept_samples_generic_hw_mul_8ns_6ns_14_9_MulnS_1 is
signal tmp_product : std_logic_vector(14 - 1 downto 0);
signal a_i : std_logic_vector(8 - 1 downto 0);
signal b_i : std_logic_vector(6 - 1 downto 0);
signal p_tmp : std_logic_vector(14 - 1 downto 0);
signal a_reg : std_logic_vector(8 - 1 downto 0);
signal b_reg : std_logic_vector(6 - 1 downto 0);
attribute keep : string;
attribute keep of a_i : signal is "true";
attribute keep of b_i : signal is "true";
signal buff0 : std_logic_vector(14 - 1 downto 0);
signal buff1 : std_logic_vector(14 - 1 downto 0);
signal buff2 : std_logic_vector(14 - 1 downto 0);
signal buff3 : std_logic_vector(14 - 1 downto 0);
signal buff4 : std_logic_vector(14 - 1 downto 0);
signal buff5 : std_logic_vector(14 - 1 downto 0);
signal buff6 : std_logic_vector(14 - 1 downto 0);
begin
a_i <= a;
b_i <= b;
p <= p_tmp;
p_tmp <= buff6;
tmp_product <= std_logic_vector(resize(unsigned(a_reg) * unsigned(b_reg), 14));
process(clk)
begin
if (clk'event and clk = '1') then
if (ce = '1') then
a_reg <= a_i;
b_reg <= b_i;
buff0 <= tmp_product;
buff1 <= buff0;
buff2 <= buff1;
buff3 <= buff2;
buff4 <= buff3;
buff5 <= buff4;
buff6 <= buff5;
end if;
end if;
end process;
end architecture;
Library IEEE;
use IEEE.std_logic_1164.all;
entity nfa_accept_samples_generic_hw_mul_8ns_6ns_14_9 is
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
ce : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR(din0_WIDTH - 1 DOWNTO 0);
din1 : IN STD_LOGIC_VECTOR(din1_WIDTH - 1 DOWNTO 0);
dout : OUT STD_LOGIC_VECTOR(dout_WIDTH - 1 DOWNTO 0));
end entity;
architecture arch of nfa_accept_samples_generic_hw_mul_8ns_6ns_14_9 is
component nfa_accept_samples_generic_hw_mul_8ns_6ns_14_9_MulnS_1 is
port (
clk : IN STD_LOGIC;
ce : IN STD_LOGIC;
a : IN STD_LOGIC_VECTOR;
b : IN STD_LOGIC_VECTOR;
p : OUT STD_LOGIC_VECTOR);
end component;
begin
nfa_accept_samples_generic_hw_mul_8ns_6ns_14_9_MulnS_1_U : component nfa_accept_samples_generic_hw_mul_8ns_6ns_14_9_MulnS_1
port map (
clk => clk,
ce => ce,
a => din0,
b => din1,
p => dout);
end architecture;
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2013.4
-- Copyright (C) 2013 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity nfa_accept_samples_generic_hw_mul_8ns_6ns_14_9_MulnS_1 is
port (
clk: in std_logic;
ce: in std_logic;
a: in std_logic_vector(8 - 1 downto 0);
b: in std_logic_vector(6 - 1 downto 0);
p: out std_logic_vector(14 - 1 downto 0));
end entity;
architecture behav of nfa_accept_samples_generic_hw_mul_8ns_6ns_14_9_MulnS_1 is
signal tmp_product : std_logic_vector(14 - 1 downto 0);
signal a_i : std_logic_vector(8 - 1 downto 0);
signal b_i : std_logic_vector(6 - 1 downto 0);
signal p_tmp : std_logic_vector(14 - 1 downto 0);
signal a_reg : std_logic_vector(8 - 1 downto 0);
signal b_reg : std_logic_vector(6 - 1 downto 0);
attribute keep : string;
attribute keep of a_i : signal is "true";
attribute keep of b_i : signal is "true";
signal buff0 : std_logic_vector(14 - 1 downto 0);
signal buff1 : std_logic_vector(14 - 1 downto 0);
signal buff2 : std_logic_vector(14 - 1 downto 0);
signal buff3 : std_logic_vector(14 - 1 downto 0);
signal buff4 : std_logic_vector(14 - 1 downto 0);
signal buff5 : std_logic_vector(14 - 1 downto 0);
signal buff6 : std_logic_vector(14 - 1 downto 0);
begin
a_i <= a;
b_i <= b;
p <= p_tmp;
p_tmp <= buff6;
tmp_product <= std_logic_vector(resize(unsigned(a_reg) * unsigned(b_reg), 14));
process(clk)
begin
if (clk'event and clk = '1') then
if (ce = '1') then
a_reg <= a_i;
b_reg <= b_i;
buff0 <= tmp_product;
buff1 <= buff0;
buff2 <= buff1;
buff3 <= buff2;
buff4 <= buff3;
buff5 <= buff4;
buff6 <= buff5;
end if;
end if;
end process;
end architecture;
Library IEEE;
use IEEE.std_logic_1164.all;
entity nfa_accept_samples_generic_hw_mul_8ns_6ns_14_9 is
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
ce : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR(din0_WIDTH - 1 DOWNTO 0);
din1 : IN STD_LOGIC_VECTOR(din1_WIDTH - 1 DOWNTO 0);
dout : OUT STD_LOGIC_VECTOR(dout_WIDTH - 1 DOWNTO 0));
end entity;
architecture arch of nfa_accept_samples_generic_hw_mul_8ns_6ns_14_9 is
component nfa_accept_samples_generic_hw_mul_8ns_6ns_14_9_MulnS_1 is
port (
clk : IN STD_LOGIC;
ce : IN STD_LOGIC;
a : IN STD_LOGIC_VECTOR;
b : IN STD_LOGIC_VECTOR;
p : OUT STD_LOGIC_VECTOR);
end component;
begin
nfa_accept_samples_generic_hw_mul_8ns_6ns_14_9_MulnS_1_U : component nfa_accept_samples_generic_hw_mul_8ns_6ns_14_9_MulnS_1
port map (
clk => clk,
ce => ce,
a => din0,
b => din1,
p => dout);
end architecture;
|
ARCHITECTURE spice_beh OF voltage_dependend_capacitor IS
QUANTITY v ACROSS i THROUGH lt TO rt;
QUANTITY c : real;
BEGIN
-- c == ((TT * ISS)/(N * VT)) * exp(v/(N*VT)) + CJ0 * (always_positive(1.0 - v/PB))**(-M);
c == ((TT * ISS)/(N * VT)) * exp(v/(N*VT)) + CJ0 * (1.0 - v/PB)**(-M);
v'dot == i / always_positive(c);
END ARCHITECTURE spice_beh;
|
ARCHITECTURE spice_beh OF voltage_dependend_capacitor IS
QUANTITY v ACROSS i THROUGH lt TO rt;
QUANTITY c : real;
BEGIN
-- c == ((TT * ISS)/(N * VT)) * exp(v/(N*VT)) + CJ0 * (always_positive(1.0 - v/PB))**(-M);
c == ((TT * ISS)/(N * VT)) * exp(v/(N*VT)) + CJ0 * (1.0 - v/PB)**(-M);
v'dot == i / always_positive(c);
END ARCHITECTURE spice_beh;
|
ARCHITECTURE spice_beh OF voltage_dependend_capacitor IS
QUANTITY v ACROSS i THROUGH lt TO rt;
QUANTITY c : real;
BEGIN
-- c == ((TT * ISS)/(N * VT)) * exp(v/(N*VT)) + CJ0 * (always_positive(1.0 - v/PB))**(-M);
c == ((TT * ISS)/(N * VT)) * exp(v/(N*VT)) + CJ0 * (1.0 - v/PB)**(-M);
v'dot == i / always_positive(c);
END ARCHITECTURE spice_beh;
|
ARCHITECTURE spice_beh OF voltage_dependend_capacitor IS
QUANTITY v ACROSS i THROUGH lt TO rt;
QUANTITY c : real;
BEGIN
-- c == ((TT * ISS)/(N * VT)) * exp(v/(N*VT)) + CJ0 * (always_positive(1.0 - v/PB))**(-M);
c == ((TT * ISS)/(N * VT)) * exp(v/(N*VT)) + CJ0 * (1.0 - v/PB)**(-M);
v'dot == i / always_positive(c);
END ARCHITECTURE spice_beh;
|
ARCHITECTURE spice_beh OF voltage_dependend_capacitor IS
QUANTITY v ACROSS i THROUGH lt TO rt;
QUANTITY c : real;
BEGIN
-- c == ((TT * ISS)/(N * VT)) * exp(v/(N*VT)) + CJ0 * (always_positive(1.0 - v/PB))**(-M);
c == ((TT * ISS)/(N * VT)) * exp(v/(N*VT)) + CJ0 * (1.0 - v/PB)**(-M);
v'dot == i / always_positive(c);
END ARCHITECTURE spice_beh;
|
ARCHITECTURE spice_beh OF voltage_dependend_capacitor IS
QUANTITY v ACROSS i THROUGH lt TO rt;
QUANTITY c : real;
BEGIN
-- c == ((TT * ISS)/(N * VT)) * exp(v/(N*VT)) + CJ0 * (always_positive(1.0 - v/PB))**(-M);
c == ((TT * ISS)/(N * VT)) * exp(v/(N*VT)) + CJ0 * (1.0 - v/PB)**(-M);
v'dot == i / always_positive(c);
END ARCHITECTURE spice_beh;
|
ARCHITECTURE spice_beh OF voltage_dependend_capacitor IS
QUANTITY v ACROSS i THROUGH lt TO rt;
QUANTITY c : real;
BEGIN
-- c == ((TT * ISS)/(N * VT)) * exp(v/(N*VT)) + CJ0 * (always_positive(1.0 - v/PB))**(-M);
c == ((TT * ISS)/(N * VT)) * exp(v/(N*VT)) + CJ0 * (1.0 - v/PB)**(-M);
v'dot == i / always_positive(c);
END ARCHITECTURE spice_beh;
|
ARCHITECTURE spice_beh OF voltage_dependend_capacitor IS
QUANTITY v ACROSS i THROUGH lt TO rt;
QUANTITY c : real;
BEGIN
-- c == ((TT * ISS)/(N * VT)) * exp(v/(N*VT)) + CJ0 * (always_positive(1.0 - v/PB))**(-M);
c == ((TT * ISS)/(N * VT)) * exp(v/(N*VT)) + CJ0 * (1.0 - v/PB)**(-M);
v'dot == i / always_positive(c);
END ARCHITECTURE spice_beh;
|
ARCHITECTURE spice_beh OF voltage_dependend_capacitor IS
QUANTITY v ACROSS i THROUGH lt TO rt;
QUANTITY c : real;
BEGIN
-- c == ((TT * ISS)/(N * VT)) * exp(v/(N*VT)) + CJ0 * (always_positive(1.0 - v/PB))**(-M);
c == ((TT * ISS)/(N * VT)) * exp(v/(N*VT)) + CJ0 * (1.0 - v/PB)**(-M);
v'dot == i / always_positive(c);
END ARCHITECTURE spice_beh;
|
ARCHITECTURE spice_beh OF voltage_dependend_capacitor IS
QUANTITY v ACROSS i THROUGH lt TO rt;
QUANTITY c : real;
BEGIN
-- c == ((TT * ISS)/(N * VT)) * exp(v/(N*VT)) + CJ0 * (always_positive(1.0 - v/PB))**(-M);
c == ((TT * ISS)/(N * VT)) * exp(v/(N*VT)) + CJ0 * (1.0 - v/PB)**(-M);
v'dot == i / always_positive(c);
END ARCHITECTURE spice_beh;
|
ARCHITECTURE spice_beh OF voltage_dependend_capacitor IS
QUANTITY v ACROSS i THROUGH lt TO rt;
QUANTITY c : real;
BEGIN
-- c == ((TT * ISS)/(N * VT)) * exp(v/(N*VT)) + CJ0 * (always_positive(1.0 - v/PB))**(-M);
c == ((TT * ISS)/(N * VT)) * exp(v/(N*VT)) + CJ0 * (1.0 - v/PB)**(-M);
v'dot == i / always_positive(c);
END ARCHITECTURE spice_beh;
|
ARCHITECTURE spice_beh OF voltage_dependend_capacitor IS
QUANTITY v ACROSS i THROUGH lt TO rt;
QUANTITY c : real;
BEGIN
-- c == ((TT * ISS)/(N * VT)) * exp(v/(N*VT)) + CJ0 * (always_positive(1.0 - v/PB))**(-M);
c == ((TT * ISS)/(N * VT)) * exp(v/(N*VT)) + CJ0 * (1.0 - v/PB)**(-M);
v'dot == i / always_positive(c);
END ARCHITECTURE spice_beh;
|
ARCHITECTURE spice_beh OF voltage_dependend_capacitor IS
QUANTITY v ACROSS i THROUGH lt TO rt;
QUANTITY c : real;
BEGIN
-- c == ((TT * ISS)/(N * VT)) * exp(v/(N*VT)) + CJ0 * (always_positive(1.0 - v/PB))**(-M);
c == ((TT * ISS)/(N * VT)) * exp(v/(N*VT)) + CJ0 * (1.0 - v/PB)**(-M);
v'dot == i / always_positive(c);
END ARCHITECTURE spice_beh;
|
--!
--! \file just_wait.vhd
--!
--! Benchmark for cooperative multithreading
--!
--! \author Enno Luebbers <[email protected]>
--! \date 13.03.2009
--
-----------------------------------------------------------------------------
-- %%%RECONOS_COPYRIGHT_BEGIN%%%
-- %%%RECONOS_COPYRIGHT_END%%%
-----------------------------------------------------------------------------
--
-- Major Changes:
--
-- 13.03.2009 Enno Luebbers File created.
library IEEE;
use IEEE.STD_LOGIC_1164.all;
--use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
use IEEE.NUMERIC_STD.all;
library reconos_v2_01_a;
use reconos_v2_01_a.reconos_pkg.all;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity just_wait is
generic (
C_BURST_AWIDTH : integer := 11;
C_BURST_DWIDTH : integer := 32;
C_SUB_NADD : integer := 0 -- 0: ADD, 1: SUB
);
port (
clk : in std_logic;
reset : in std_logic;
i_osif : in osif_os2task_t;
o_osif : out osif_task2os_t;
-- burst ram interface
o_RAMAddr : out std_logic_vector(0 to C_BURST_AWIDTH-1);
o_RAMData : out std_logic_vector(0 to C_BURST_DWIDTH-1);
i_RAMData : in std_logic_vector(0 to C_BURST_DWIDTH-1);
o_RAMWE : out std_logic;
o_RAMClk : out std_logic
);
end just_wait;
architecture Behavioral of just_wait is
-- OS synchronization state machine states
type state_t is (STATE_INIT,
STATE_WAIT,
STATE_EXIT);
type encode_t is array(state_t) of reconos_state_enc_t;
type decode_t is array(natural range <>) of state_t;
constant encode : encode_t := (X"00",
X"01",
X"03");
constant decode : decode_t := (STATE_INIT,
STATE_WAIT,
STATE_EXIT);
signal state : state_t := STATE_INIT;
begin
-- tie RAM signals low (we don't use them)
o_RAMAddr <= (others => '0');
o_RAMData <= (others => '0');
o_RAMWe <= '0';
o_RAMClk <= '0';
-- OS synchronization state machine
state_proc : process(clk, reset)
variable done : boolean;
variable success : boolean;
variable next_state : state_t := STATE_INIT;
variable wait_time : std_logic_vector(0 to C_OSIF_DATA_WIDTH/2-2); -- possible values: 0..32767 (x 6553 us)
variable counter : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1);
variable init_data : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1);
begin
if reset = '1' then
reconos_reset(o_osif, i_osif);
state <= STATE_INIT;
next_state := STATE_INIT;
done := false;
success := false;
wait_time := (others => '0');
counter := (others => '0');
init_data := (others => '0');
elsif rising_edge(clk) then
reconos_begin(o_osif, i_osif);
if reconos_ready(i_osif) then
case state is
when STATE_INIT =>
reconos_get_init_data(done, o_osif, i_osif, init_data);
wait_time := init_data(17 to 31);
counter := wait_time & "0" & X"0000"; -- x 1.31 ms
next_state := STATE_WAIT;
when STATE_WAIT =>
if counter = X"00000000" then
next_state := STATE_EXIT;
else
counter := counter - 1;
end if;
when STATE_EXIT =>
reconos_thread_exit(o_osif, i_osif, X"00000000");
when others =>
next_state := STATE_EXIT;
end case;
if done then
state <= next_state;
end if;
end if;
end if;
end process;
end Behavioral;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: pt_pci_arb
-- File: pt_pci_arb.vhd
-- Author: Alf Vaerneus, Gaisler Research
-- Description: PCI arbiter
------------------------------------------------------------------------------
-- pragma translate_off
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.pt_pkg.all;
entity pt_pci_arb is
generic (
slots : integer := 5;
tval : time := 7 ns);
port (
systclk : in pci_syst_type;
ifcin : in pci_ifc_type;
arbin : in pci_arb_type;
arbout : out pci_arb_type);
end pt_pci_arb;
architecture tb of pt_pci_arb is
type queue_type is array (0 to slots-1) of integer range 0 to slots;
signal queue : queue_type;
signal queue_nr : integer range 0 to slots;
signal wfbus : boolean;
begin
arb : process(systclk)
variable i, slotgnt : integer;
variable set : boolean;
variable bus_idle : boolean;
variable vqueue_nr : integer range 0 to slots;
variable gnt,req : std_logic_vector(slots-1 downto 0);
begin
set := false; vqueue_nr := queue_nr;
if (ifcin.frame and ifcin.irdy) = '1' then bus_idle := true; else bus_idle := false; end if;
gnt := to_x01(arbin.gnt(slots-1 downto 0));
req := to_x01(arbin.req(slots-1 downto 0));
if systclk.rst = '0' then
gnt := (others => '1');
wfbus <= false;
for i in 0 to slots-1 loop
queue(i) <= 0;
end loop;
queue_nr <= 0;
elsif rising_edge(systclk.clk) then
for i in 0 to slots-1 loop
if (gnt(i) or req(i)) = '0' then
if (bus_idle or wfbus) then
set := true;
end if;
end if;
end loop;
for i in 0 to slots-1 loop
if (gnt(i) and not req(i)) = '1' then
if queue(i) = 0 then
vqueue_nr := vqueue_nr+1;
queue(i) <= vqueue_nr;
elsif (queue(i) = 1 and set = false) then
gnt := (others => '1'); gnt(i) := '0';
queue(i) <= 0;
if not bus_idle then wfbus <= true; end if;
if vqueue_nr > 0 then vqueue_nr := vqueue_nr-1; end if;
elsif queue(i) >= 2 then
if (set = false or vqueue_nr <= 1) then
queue(i) <= queue(i)-1;
-- if vqueue_nr > 0 then vqueue_nr := vqueue_nr-1; end if;
end if;
end if;
elsif (req(i) and not gnt(i)) = '1' then
queue(i) <= 0; gnt(i) := '1';
-- if vqueue_nr > 0 then vqueue_nr := vqueue_nr-1; end if;
elsif (req(i) and gnt(i)) = '1' then
if (queue(i) > 0 and set = false) then
queue(i) <= queue(i)-1;
if (vqueue_nr > 0 and queue(i) = 1) then vqueue_nr := vqueue_nr-1; end if;
end if;
end if;
end loop;
end if;
if bus_idle then wfbus <= false; end if;
queue_nr <= vqueue_nr;
arbout.req <= (others => 'Z');
arbout.gnt <= (others => 'Z');
arbout.gnt(slots-1 downto 0) <= gnt;
end process;
end;
-- pragma translate_on
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity ScanRegister_for_SIBFCX is
Generic (Size : positive;
BitOrder : string; -- MSBLSB / LSBMSB
SOSource : natural;
ResetValue : STD_LOGIC_VECTOR);
Port ( SI : in STD_LOGIC;
CE : in STD_LOGIC;
SE : in STD_LOGIC;
UE : in STD_LOGIC;
SEL : in STD_LOGIC;
RST : in STD_LOGIC;
TCK : in STD_LOGIC;
SO : out STD_LOGIC;
CaptureSource : in STD_LOGIC_VECTOR (Size-1 downto 0);
ScanRegister_out : out STD_LOGIC_VECTOR (Size-1 downto 0);
ue_mux_out : out STD_LOGIC_VECTOR (Size-1 downto 0));
end ScanRegister_for_SIBFCX;
architecture ScanRegister_arch of ScanRegister_for_SIBFCX is
signal and_ce, and_se, and_ue: std_logic;
signal internal_si: std_logic_vector(Size downto 0);
signal cs_reg: std_logic_vector(Size-1 downto 0);
signal u_reg: std_logic_vector(Size-1 downto 0):=ResetValue;
signal se_mux, ce_mux, ue_mux: std_logic_vector(Size-1 downto 0);
begin
-- Basic Combinational Logic
and_ce <= CE and SEL;
and_se <= SE and SEL;
and_ue <= UE and SEL;
internal_si(Size) <= SI;
-- TDR Shift Register Core
SCAN_REGISTER: for i in Size-1 downto 0 generate
-- Multiplexers
se_mux(i) <= internal_si(i+1) when and_se = '1' else cs_reg(i);
ce_mux(i) <= CaptureSource(i) when and_ce = '1' else se_mux(i);
ue_mux(i) <= cs_reg(i) when and_ue = '1' else u_reg(i);
-- Flip-Flops
cs_reg(i) <= ce_mux(i) when TCK'event and TCK = '1';
process(RST,TCK)
begin
if RST = '1' then
u_reg(i) <= ResetValue(Size-1-i);
elsif TCK'event and TCK = '0' then
u_reg(i) <= ue_mux(i);
end if;
end process;
-- Internal Connections
internal_si(i) <= cs_reg(i);
end generate;
-- Outputs
MSBLSB_SO : if BitOrder = "MSBLSB" generate
SO <= internal_si(SOSource);
end generate;
LSBMSB_SO : if BitOrder = "LSBMSB" generate
SO <= internal_si(Size-1-SOSource);
end generate;
ScanRegister_out <= u_reg;
ue_mux_out <= ue_mux;
end ScanRegister_arch; |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity ScanRegister_for_SIBFCX is
Generic (Size : positive;
BitOrder : string; -- MSBLSB / LSBMSB
SOSource : natural;
ResetValue : STD_LOGIC_VECTOR);
Port ( SI : in STD_LOGIC;
CE : in STD_LOGIC;
SE : in STD_LOGIC;
UE : in STD_LOGIC;
SEL : in STD_LOGIC;
RST : in STD_LOGIC;
TCK : in STD_LOGIC;
SO : out STD_LOGIC;
CaptureSource : in STD_LOGIC_VECTOR (Size-1 downto 0);
ScanRegister_out : out STD_LOGIC_VECTOR (Size-1 downto 0);
ue_mux_out : out STD_LOGIC_VECTOR (Size-1 downto 0));
end ScanRegister_for_SIBFCX;
architecture ScanRegister_arch of ScanRegister_for_SIBFCX is
signal and_ce, and_se, and_ue: std_logic;
signal internal_si: std_logic_vector(Size downto 0);
signal cs_reg: std_logic_vector(Size-1 downto 0);
signal u_reg: std_logic_vector(Size-1 downto 0):=ResetValue;
signal se_mux, ce_mux, ue_mux: std_logic_vector(Size-1 downto 0);
begin
-- Basic Combinational Logic
and_ce <= CE and SEL;
and_se <= SE and SEL;
and_ue <= UE and SEL;
internal_si(Size) <= SI;
-- TDR Shift Register Core
SCAN_REGISTER: for i in Size-1 downto 0 generate
-- Multiplexers
se_mux(i) <= internal_si(i+1) when and_se = '1' else cs_reg(i);
ce_mux(i) <= CaptureSource(i) when and_ce = '1' else se_mux(i);
ue_mux(i) <= cs_reg(i) when and_ue = '1' else u_reg(i);
-- Flip-Flops
cs_reg(i) <= ce_mux(i) when TCK'event and TCK = '1';
process(RST,TCK)
begin
if RST = '1' then
u_reg(i) <= ResetValue(Size-1-i);
elsif TCK'event and TCK = '0' then
u_reg(i) <= ue_mux(i);
end if;
end process;
-- Internal Connections
internal_si(i) <= cs_reg(i);
end generate;
-- Outputs
MSBLSB_SO : if BitOrder = "MSBLSB" generate
SO <= internal_si(SOSource);
end generate;
LSBMSB_SO : if BitOrder = "LSBMSB" generate
SO <= internal_si(Size-1-SOSource);
end generate;
ScanRegister_out <= u_reg;
ue_mux_out <= ue_mux;
end ScanRegister_arch; |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity ScanRegister_for_SIBFCX is
Generic (Size : positive;
BitOrder : string; -- MSBLSB / LSBMSB
SOSource : natural;
ResetValue : STD_LOGIC_VECTOR);
Port ( SI : in STD_LOGIC;
CE : in STD_LOGIC;
SE : in STD_LOGIC;
UE : in STD_LOGIC;
SEL : in STD_LOGIC;
RST : in STD_LOGIC;
TCK : in STD_LOGIC;
SO : out STD_LOGIC;
CaptureSource : in STD_LOGIC_VECTOR (Size-1 downto 0);
ScanRegister_out : out STD_LOGIC_VECTOR (Size-1 downto 0);
ue_mux_out : out STD_LOGIC_VECTOR (Size-1 downto 0));
end ScanRegister_for_SIBFCX;
architecture ScanRegister_arch of ScanRegister_for_SIBFCX is
signal and_ce, and_se, and_ue: std_logic;
signal internal_si: std_logic_vector(Size downto 0);
signal cs_reg: std_logic_vector(Size-1 downto 0);
signal u_reg: std_logic_vector(Size-1 downto 0):=ResetValue;
signal se_mux, ce_mux, ue_mux: std_logic_vector(Size-1 downto 0);
begin
-- Basic Combinational Logic
and_ce <= CE and SEL;
and_se <= SE and SEL;
and_ue <= UE and SEL;
internal_si(Size) <= SI;
-- TDR Shift Register Core
SCAN_REGISTER: for i in Size-1 downto 0 generate
-- Multiplexers
se_mux(i) <= internal_si(i+1) when and_se = '1' else cs_reg(i);
ce_mux(i) <= CaptureSource(i) when and_ce = '1' else se_mux(i);
ue_mux(i) <= cs_reg(i) when and_ue = '1' else u_reg(i);
-- Flip-Flops
cs_reg(i) <= ce_mux(i) when TCK'event and TCK = '1';
process(RST,TCK)
begin
if RST = '1' then
u_reg(i) <= ResetValue(Size-1-i);
elsif TCK'event and TCK = '0' then
u_reg(i) <= ue_mux(i);
end if;
end process;
-- Internal Connections
internal_si(i) <= cs_reg(i);
end generate;
-- Outputs
MSBLSB_SO : if BitOrder = "MSBLSB" generate
SO <= internal_si(SOSource);
end generate;
LSBMSB_SO : if BitOrder = "LSBMSB" generate
SO <= internal_si(Size-1-SOSource);
end generate;
ScanRegister_out <= u_reg;
ue_mux_out <= ue_mux;
end ScanRegister_arch; |
----------------------------------------------------------------------------------
-- Company:
-- Engineer: Tolga Sel
--
-- Create Date: 09:51:37 11/03/2015
-- Design Name:
-- Module Name: /home/ga69kaw/vhdl_system_design_lab/workspace/Exercise1/direct_implementation/tb_mulop.vhd
-- Project Name: direct_implementation
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: mulop
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY tb_mulop IS
END tb_mulop;
ARCHITECTURE behavior OF tb_mulop IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT mulop
PORT(
X : IN std_logic_vector(15 downto 0);
Y : IN std_logic_vector(15 downto 0);
O : OUT std_logic_vector(15 downto 0)
);
END COMPONENT;
--Inputs
signal X : std_logic_vector(15 downto 0) := (others => '0');
signal Y : std_logic_vector(15 downto 0) := (others => '0');
--Outputs
signal O : std_logic_vector(15 downto 0);
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
BEGIN
-- Instantiate the Unit Under Test (UUT) (43241*63743) mod (65537)
uut: mulop PORT MAP (
X => X,
Y => Y,
O => O
);
X <= "0000000000000000", "1000000000000000" after 200ns, "1111111111111111" after 400ns, "1010100011101001" after 800ns;
Y <= "0000000000000000", "1000000000000000" after 200ns, "1111111111111111" after 400ns, "1111100011111111" after 800ns;
end behavior;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer: Tolga Sel
--
-- Create Date: 09:51:37 11/03/2015
-- Design Name:
-- Module Name: /home/ga69kaw/vhdl_system_design_lab/workspace/Exercise1/direct_implementation/tb_mulop.vhd
-- Project Name: direct_implementation
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: mulop
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY tb_mulop IS
END tb_mulop;
ARCHITECTURE behavior OF tb_mulop IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT mulop
PORT(
X : IN std_logic_vector(15 downto 0);
Y : IN std_logic_vector(15 downto 0);
O : OUT std_logic_vector(15 downto 0)
);
END COMPONENT;
--Inputs
signal X : std_logic_vector(15 downto 0) := (others => '0');
signal Y : std_logic_vector(15 downto 0) := (others => '0');
--Outputs
signal O : std_logic_vector(15 downto 0);
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
BEGIN
-- Instantiate the Unit Under Test (UUT) (43241*63743) mod (65537)
uut: mulop PORT MAP (
X => X,
Y => Y,
O => O
);
X <= "0000000000000000", "1000000000000000" after 200ns, "1111111111111111" after 400ns, "1010100011101001" after 800ns;
Y <= "0000000000000000", "1000000000000000" after 200ns, "1111111111111111" after 400ns, "1111100011111111" after 800ns;
end behavior;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer: Tolga Sel
--
-- Create Date: 09:51:37 11/03/2015
-- Design Name:
-- Module Name: /home/ga69kaw/vhdl_system_design_lab/workspace/Exercise1/direct_implementation/tb_mulop.vhd
-- Project Name: direct_implementation
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: mulop
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY tb_mulop IS
END tb_mulop;
ARCHITECTURE behavior OF tb_mulop IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT mulop
PORT(
X : IN std_logic_vector(15 downto 0);
Y : IN std_logic_vector(15 downto 0);
O : OUT std_logic_vector(15 downto 0)
);
END COMPONENT;
--Inputs
signal X : std_logic_vector(15 downto 0) := (others => '0');
signal Y : std_logic_vector(15 downto 0) := (others => '0');
--Outputs
signal O : std_logic_vector(15 downto 0);
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
BEGIN
-- Instantiate the Unit Under Test (UUT) (43241*63743) mod (65537)
uut: mulop PORT MAP (
X => X,
Y => Y,
O => O
);
X <= "0000000000000000", "1000000000000000" after 200ns, "1111111111111111" after 400ns, "1010100011101001" after 800ns;
Y <= "0000000000000000", "1000000000000000" after 200ns, "1111111111111111" after 400ns, "1111100011111111" after 800ns;
end behavior;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer: Tolga Sel
--
-- Create Date: 09:51:37 11/03/2015
-- Design Name:
-- Module Name: /home/ga69kaw/vhdl_system_design_lab/workspace/Exercise1/direct_implementation/tb_mulop.vhd
-- Project Name: direct_implementation
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: mulop
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY tb_mulop IS
END tb_mulop;
ARCHITECTURE behavior OF tb_mulop IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT mulop
PORT(
X : IN std_logic_vector(15 downto 0);
Y : IN std_logic_vector(15 downto 0);
O : OUT std_logic_vector(15 downto 0)
);
END COMPONENT;
--Inputs
signal X : std_logic_vector(15 downto 0) := (others => '0');
signal Y : std_logic_vector(15 downto 0) := (others => '0');
--Outputs
signal O : std_logic_vector(15 downto 0);
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
BEGIN
-- Instantiate the Unit Under Test (UUT) (43241*63743) mod (65537)
uut: mulop PORT MAP (
X => X,
Y => Y,
O => O
);
X <= "0000000000000000", "1000000000000000" after 200ns, "1111111111111111" after 400ns, "1010100011101001" after 800ns;
Y <= "0000000000000000", "1000000000000000" after 200ns, "1111111111111111" after 400ns, "1111100011111111" after 800ns;
end behavior;
|
entity bounds7 is
end entity;
architecture test of bounds7 is
type my_int is range 1 to 10;
begin
process is
variable x : my_int;
variable y : integer;
begin
x := 6;
y := integer(x);
x := 10;
x := 11;
wait;
end process;
end architecture;
|
-------------------------------------------------------------------------------
-- Title : Accelerator Adapter
-- Project :
-------------------------------------------------------------------------------
-- File : async_fifo_dist_inst.vhd
-- Author : ghanash
-- Company : Xilinx, Inc.
-- Created : 2014-11-21
-- Last update:
-- Platform :
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2014-11-21 1.0 ghanash Created
-------------------------------------------------------------------------------
-- ****************************************************************************
--
-- (c) Copyright 2010, 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- ****************************************************************************
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library axis_accelerator_adapter_v2_1_6;
use axis_accelerator_adapter_v2_1_6.xd_adapter_pkg.all;
library fifo_generator_v13_0_1;
use fifo_generator_v13_0_1.all;
entity async_fifo_dist_inst is
generic (
C_FAMILY : string := "virtex6"; -- Xilinx FPGA family
DEPTH : integer := 31;
WIDTH : integer := 32);
port (
din : in std_logic_vector(WIDTH-1 downto 0);
din_vld : in std_logic;
din_rdy : out std_logic;
wr_clk : in std_logic;
wr_rst : in std_logic;
dout : out std_logic_vector(WIDTH-1 downto 0);
dout_vld : out std_logic;
dout_rdy : in std_logic;
rd_clk : in std_logic;
rd_rst : in std_logic);
end async_fifo_dist_inst;
architecture rtl of async_fifo_dist_inst is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of rtl : architecture is "yes";
--constant FIFO_DEPTH : integer := calc_fifo_depth(DEPTH);
--constant ADDR_BITS : integer := log2(FIFO_DEPTH);
signal din_rdy_n : std_logic;
signal dout_vld_i : std_logic;
signal fifo_we : std_logic;
signal fifo_re : std_logic;
signal empty : std_logic;
signal full : std_logic;
signal almost_full :std_logic;
signal wr_ack :std_logic;
signal overflow :std_logic;
signal almost_empty :std_logic;
signal valid :std_logic;
signal underflow :std_logic;
signal data_count :std_logic_vector(4 downto 0);
signal rd_data_count :std_logic_vector(4 downto 0);
signal wr_data_count :std_logic_vector(4 downto 0);
signal prog_full :std_logic;
signal prog_empty :std_logic;
signal sbiterr :std_logic;
signal dbiterr :std_logic;
signal wr_rst_busy :std_logic;
signal rd_rst_busy :std_logic;
signal m_axi_awid :std_logic_vector(0 downto 0);
signal m_axi_awaddr :std_logic_vector(31 downto 0);
signal m_axi_awlen :std_logic_vector(7 downto 0);
signal m_axi_awsize :std_logic_vector(2 downto 0);
signal m_axi_awburst :std_logic_vector(1 downto 0);
signal m_axi_awlock :std_logic_vector(0 downto 0);
signal m_axi_awcache :std_logic_vector(3 downto 0);
signal m_axi_awprot :std_logic_vector(2 downto 0);
signal m_axi_awqos :std_logic_vector(3 downto 0);
signal m_axi_awregion :std_logic_vector(3 downto 0);
signal m_axi_awuser :std_logic_vector(0 downto 0);
signal m_axi_awvalid :std_logic;
signal m_axi_wid :std_logic_vector(0 downto 0);
signal m_axi_wdata :std_logic_vector(63 downto 0);
signal m_axi_wstrb :std_logic_vector(7 downto 0);
signal m_axi_wlast :std_logic;
signal m_axi_wuser :std_logic_vector(0 downto 0);
signal m_axi_wvalid :std_logic;
signal m_axi_bready :std_logic;
signal s_axi_awready :std_logic;
signal s_axi_wready :std_logic;
signal s_axi_bid :std_logic_vector(0 downto 0);
signal s_axi_bresp :std_logic_vector(1 downto 0);
signal s_axi_buser :std_logic_vector(0 downto 0);
signal m_axi_arid :std_logic_vector(0 downto 0);
signal m_axi_araddr :std_logic_vector(31 downto 0);
signal m_axi_arlen :std_logic_vector(7 downto 0);
signal m_axi_arsize :std_logic_vector(2 downto 0);
signal m_axi_arburst :std_logic_vector(1 downto 0);
signal m_axi_arlock :std_logic_vector(0 downto 0);
signal m_axi_arcache :std_logic_vector(3 downto 0);
signal m_axi_arprot :std_logic_vector(2 downto 0);
signal m_axi_arqos :std_logic_vector(3 downto 0);
signal m_axi_arregion :std_logic_vector(3 downto 0);
signal m_axi_aruser :std_logic_vector(0 downto 0);
signal m_axi_arvalid :std_logic;
signal m_axi_rready :std_logic;
signal s_axi_arready :std_logic;
signal s_axi_rid :std_logic_vector(0 downto 0);
signal s_axi_rdata :std_logic_vector(63 downto 0);
signal s_axi_rresp :std_logic_vector(1 downto 0);
signal s_axi_rlast :std_logic;
signal s_axi_ruser :std_logic_vector(0 downto 0);
signal m_axis_tvalid :std_logic;
signal m_axis_tdata :std_logic_vector(7 downto 0);
signal m_axis_tstrb :std_logic_vector(0 downto 0);
signal m_axis_tlast :std_logic;
signal m_axis_tkeep :std_logic_vector(0 downto 0);
signal m_axis_tid :std_logic_vector(0 downto 0);
signal m_axis_tdest :std_logic_vector(0 downto 0);
signal m_axis_tuser :std_logic_vector(3 downto 0);
signal s_axis_tready :std_logic;
signal axi_aw_data_count :std_logic_vector(4 downto 0);
signal axi_aw_wr_data_count :std_logic_vector(4 downto 0);
signal axi_aw_rd_data_count :std_logic_vector(4 downto 0);
signal axi_aw_sbiterr :std_logic;
signal axi_aw_dbiterr :std_logic;
signal axi_aw_overflow :std_logic;
signal axi_aw_underflow :std_logic;
signal axi_aw_prog_full :std_logic;
signal axi_aw_prog_empty :std_logic;
signal axi_w_data_count :std_logic_vector(10 downto 0);
signal axi_w_wr_data_count :std_logic_vector(10 downto 0);
signal axi_w_rd_data_count :std_logic_vector(10 downto 0);
signal axi_w_sbiterr :std_logic;
signal axi_w_dbiterr :std_logic;
signal axi_w_overflow :std_logic;
signal axi_w_underflow :std_logic;
signal axi_w_prog_full :std_logic;
signal axi_w_prog_empty :std_logic;
signal axi_b_data_count :std_logic_vector(4 downto 0);
signal axi_b_wr_data_count :std_logic_vector(4 downto 0);
signal axi_b_rd_data_count :std_logic_vector(4 downto 0);
signal axi_b_sbiterr :std_logic;
signal axi_b_dbiterr :std_logic;
signal axi_b_overflow :std_logic;
signal axi_b_underflow :std_logic;
signal axi_b_prog_full :std_logic;
signal axi_b_prog_empty :std_logic;
signal axi_ar_data_count :std_logic_vector(4 downto 0);
signal axi_ar_wr_data_count :std_logic_vector(4 downto 0);
signal axi_ar_rd_data_count :std_logic_vector(4 downto 0);
signal axi_ar_sbiterr :std_logic;
signal axi_ar_dbiterr :std_logic;
signal axi_ar_overflow :std_logic;
signal axi_ar_underflow :std_logic;
signal axi_ar_prog_full :std_logic;
signal axi_ar_prog_empty :std_logic;
signal axi_r_data_count :std_logic_vector(10 downto 0);
signal axi_r_wr_data_count :std_logic_vector(10 downto 0);
signal axi_r_rd_data_count :std_logic_vector(10 downto 0);
signal axi_r_sbiterr :std_logic;
signal axi_r_dbiterr :std_logic;
signal axi_r_overflow :std_logic;
signal axi_r_underflow :std_logic;
signal axi_r_prog_full :std_logic;
signal axi_r_prog_empty :std_logic;
signal axis_data_count :std_logic_vector(10 downto 0);
signal axis_wr_data_count :std_logic_vector(10 downto 0);
signal axis_rd_data_count :std_logic_vector(10 downto 0);
signal axis_sbiterr :std_logic;
signal axis_dbiterr :std_logic;
signal axis_overflow :std_logic;
signal axis_underflow :std_logic;
signal axis_prog_full :std_logic;
signal axis_prog_empty :std_logic;
begin
-- fifo_we <= din_vld and (not(full));
-- fifo_re <= (not(dout_vld_i) or (dout_vld_i and dout_rdy)) and (not(empty));
din_rdy <= not(full);
dout_vld <= dout_vld_i;
-- fifo_we <= din_vld and (not(full));
-- fifo_re <= dout_rdy and (not(empty));
--
--
--
-- process(wr_clk, wr_rst)
-- begin
-- if(wr_rst = '1') then
-- din_rdy <= '0';
-- elsif(wr_clk'event and wr_clk = '1') then
-- if(fifo_we = '1') then
-- dout_vld <= not(empty);
-- end if;
-- end if;
-- end process;
-- process(rd_clk, rd_rst)
-- begin
-- if(rd_rst = '1') then
-- dout_vld_i <= '0';
-- elsif(rd_clk'event and rd_clk = '1') then
-- if((not(dout_vld_i) or (dout_vld_i and dout_rdy)) = '1') then
dout_vld_i <= not(empty);
-- end if;
-- end if;
-- end process;
FIF_DMG_INST : entity fifo_generator_v13_0_1.fifo_generator_v13_0_1
GENERIC MAP (
C_COMMON_CLOCK => 0,
C_COUNT_TYPE => 0,
C_DATA_COUNT_WIDTH => 5,
C_DEFAULT_VALUE => "BlankString",
C_DIN_WIDTH => 32,
C_DOUT_RST_VAL => "0",
C_DOUT_WIDTH => 32,
C_ENABLE_RLOCS => 0,
C_FAMILY => C_FAMILY,
C_FULL_FLAGS_RST_VAL => 0,
C_HAS_ALMOST_EMPTY => 0,
C_HAS_ALMOST_FULL => 0,
C_HAS_BACKUP => 0,
C_HAS_DATA_COUNT => 0,
C_HAS_INT_CLK => 0,
C_HAS_MEMINIT_FILE => 0,
C_HAS_OVERFLOW => 0,
C_HAS_RD_DATA_COUNT => 0,
C_HAS_RD_RST => 0,
C_HAS_RST => 1,
C_HAS_SRST => 0,
C_HAS_UNDERFLOW => 0,
C_HAS_VALID => 0,
C_HAS_WR_ACK => 0,
C_HAS_WR_DATA_COUNT => 0,
C_HAS_WR_RST => 0,
C_IMPLEMENTATION_TYPE => 2,
C_INIT_WR_PNTR_VAL => 0,
C_MEMORY_TYPE => 2,
C_MIF_FILE_NAME => "BlankString",
C_OPTIMIZATION_MODE => 0,
C_OVERFLOW_LOW => 0,
C_PRELOAD_LATENCY => 0,
C_PRELOAD_REGS => 1,
C_PRIM_FIFO_TYPE => "512x36",
C_PROG_EMPTY_THRESH_ASSERT_VAL => 2,
C_PROG_EMPTY_THRESH_NEGATE_VAL => 3,
C_PROG_EMPTY_TYPE => 0,
C_PROG_FULL_THRESH_ASSERT_VAL => 29,
C_PROG_FULL_THRESH_NEGATE_VAL => 28,
C_PROG_FULL_TYPE => 0,
C_RD_DATA_COUNT_WIDTH => 5,
C_RD_DEPTH => 32,
C_RD_FREQ => 1,
C_RD_PNTR_WIDTH => 5,
C_UNDERFLOW_LOW => 0,
C_USE_DOUT_RST => 1,
C_USE_ECC => 0,
C_USE_EMBEDDED_REG => 0,
C_USE_PIPELINE_REG => 0,
C_POWER_SAVING_MODE => 0,
C_USE_FIFO16_FLAGS => 0,
C_USE_FWFT_DATA_COUNT => 0,
C_VALID_LOW => 0,
C_WR_ACK_LOW => 0,
C_WR_DATA_COUNT_WIDTH => 5,
C_WR_DEPTH => 32,
C_WR_FREQ => 1,
C_WR_PNTR_WIDTH => 5,
C_WR_RESPONSE_LATENCY => 1,
C_MSGON_VAL => 1,
C_ENABLE_RST_SYNC => 0,
C_ERROR_INJECTION_TYPE => 0,
C_SYNCHRONIZER_STAGE => 2,
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_HAS_AXI_WR_CHANNEL => 1,
C_HAS_AXI_RD_CHANNEL => 1,
C_HAS_SLAVE_CE => 0,
C_HAS_MASTER_CE => 0,
C_ADD_NGC_CONSTRAINT => 0,
C_USE_COMMON_OVERFLOW => 0,
C_USE_COMMON_UNDERFLOW => 0,
C_USE_DEFAULT_SETTINGS => 0,
C_AXI_ID_WIDTH => 1,
C_AXI_ADDR_WIDTH => 32,
C_AXI_DATA_WIDTH => 64,
C_AXI_LEN_WIDTH => 8,
C_AXI_LOCK_WIDTH => 1,
C_HAS_AXI_ID => 0,
C_HAS_AXI_AWUSER => 0,
C_HAS_AXI_WUSER => 0,
C_HAS_AXI_BUSER => 0,
C_HAS_AXI_ARUSER => 0,
C_HAS_AXI_RUSER => 0,
C_AXI_ARUSER_WIDTH => 1,
C_AXI_AWUSER_WIDTH => 1,
C_AXI_WUSER_WIDTH => 1,
C_AXI_BUSER_WIDTH => 1,
C_AXI_RUSER_WIDTH => 1,
C_HAS_AXIS_TDATA => 1,
C_HAS_AXIS_TID => 0,
C_HAS_AXIS_TDEST => 0,
C_HAS_AXIS_TUSER => 1,
C_HAS_AXIS_TREADY => 1,
C_HAS_AXIS_TLAST => 0,
C_HAS_AXIS_TSTRB => 0,
C_HAS_AXIS_TKEEP => 0,
C_AXIS_TDATA_WIDTH => 8,
C_AXIS_TID_WIDTH => 1,
C_AXIS_TDEST_WIDTH => 1,
C_AXIS_TUSER_WIDTH => 4,
C_AXIS_TSTRB_WIDTH => 1,
C_AXIS_TKEEP_WIDTH => 1,
C_WACH_TYPE => 0,
C_WDCH_TYPE => 0,
C_WRCH_TYPE => 0,
C_RACH_TYPE => 0,
C_RDCH_TYPE => 0,
C_AXIS_TYPE => 0,
C_IMPLEMENTATION_TYPE_WACH => 1,
C_IMPLEMENTATION_TYPE_WDCH => 1,
C_IMPLEMENTATION_TYPE_WRCH => 1,
C_IMPLEMENTATION_TYPE_RACH => 1,
C_IMPLEMENTATION_TYPE_RDCH => 1,
C_IMPLEMENTATION_TYPE_AXIS => 1,
C_APPLICATION_TYPE_WACH => 0,
C_APPLICATION_TYPE_WDCH => 0,
C_APPLICATION_TYPE_WRCH => 0,
C_APPLICATION_TYPE_RACH => 0,
C_APPLICATION_TYPE_RDCH => 0,
C_APPLICATION_TYPE_AXIS => 0,
C_PRIM_FIFO_TYPE_WACH => "512x36",
C_PRIM_FIFO_TYPE_WDCH => "1kx36",
C_PRIM_FIFO_TYPE_WRCH => "512x36",
C_PRIM_FIFO_TYPE_RACH => "512x36",
C_PRIM_FIFO_TYPE_RDCH => "1kx36",
C_PRIM_FIFO_TYPE_AXIS => "1kx18",
C_USE_ECC_WACH => 0,
C_USE_ECC_WDCH => 0,
C_USE_ECC_WRCH => 0,
C_USE_ECC_RACH => 0,
C_USE_ECC_RDCH => 0,
C_USE_ECC_AXIS => 0,
C_ERROR_INJECTION_TYPE_WACH => 0,
C_ERROR_INJECTION_TYPE_WDCH => 0,
C_ERROR_INJECTION_TYPE_WRCH => 0,
C_ERROR_INJECTION_TYPE_RACH => 0,
C_ERROR_INJECTION_TYPE_RDCH => 0,
C_ERROR_INJECTION_TYPE_AXIS => 0,
C_DIN_WIDTH_WACH => 32,
C_DIN_WIDTH_WDCH => 64,
C_DIN_WIDTH_WRCH => 2,
C_DIN_WIDTH_RACH => 32,
C_DIN_WIDTH_RDCH => 64,
C_DIN_WIDTH_AXIS => 1,
C_WR_DEPTH_WACH => 16,
C_WR_DEPTH_WDCH => 1024,
C_WR_DEPTH_WRCH => 16,
C_WR_DEPTH_RACH => 16,
C_WR_DEPTH_RDCH => 1024,
C_WR_DEPTH_AXIS => 1024,
C_WR_PNTR_WIDTH_WACH => 4,
C_WR_PNTR_WIDTH_WDCH => 10,
C_WR_PNTR_WIDTH_WRCH => 4,
C_WR_PNTR_WIDTH_RACH => 4,
C_WR_PNTR_WIDTH_RDCH => 10,
C_WR_PNTR_WIDTH_AXIS => 10,
C_HAS_DATA_COUNTS_WACH => 0,
C_HAS_DATA_COUNTS_WDCH => 0,
C_HAS_DATA_COUNTS_WRCH => 0,
C_HAS_DATA_COUNTS_RACH => 0,
C_HAS_DATA_COUNTS_RDCH => 0,
C_HAS_DATA_COUNTS_AXIS => 0,
C_HAS_PROG_FLAGS_WACH => 0,
C_HAS_PROG_FLAGS_WDCH => 0,
C_HAS_PROG_FLAGS_WRCH => 0,
C_HAS_PROG_FLAGS_RACH => 0,
C_HAS_PROG_FLAGS_RDCH => 0,
C_HAS_PROG_FLAGS_AXIS => 0,
C_PROG_FULL_TYPE_WACH => 0,
C_PROG_FULL_TYPE_WDCH => 0,
C_PROG_FULL_TYPE_WRCH => 0,
C_PROG_FULL_TYPE_RACH => 0,
C_PROG_FULL_TYPE_RDCH => 0,
C_PROG_FULL_TYPE_AXIS => 0,
C_PROG_FULL_THRESH_ASSERT_VAL_WACH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_RACH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS => 1023,
C_PROG_EMPTY_TYPE_WACH => 0,
C_PROG_EMPTY_TYPE_WDCH => 0,
C_PROG_EMPTY_TYPE_WRCH => 0,
C_PROG_EMPTY_TYPE_RACH => 0,
C_PROG_EMPTY_TYPE_RDCH => 0,
C_PROG_EMPTY_TYPE_AXIS => 0,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS => 1022,
C_REG_SLICE_MODE_WACH => 0,
C_REG_SLICE_MODE_WDCH => 0,
C_REG_SLICE_MODE_WRCH => 0,
C_REG_SLICE_MODE_RACH => 0,
C_REG_SLICE_MODE_RDCH => 0,
C_REG_SLICE_MODE_AXIS => 0
)
PORT MAP (
backup => '0',
backup_marker => '0',
clk => '0',
rst => '0',
srst => '0',
wr_clk => wr_clk,
wr_rst => wr_rst,
rd_clk => rd_clk,
rd_rst => rd_rst,
din => din,
wr_en => din_vld,
rd_en => dout_rdy,
prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 5)),
prog_empty_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 5)),
prog_empty_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 5)),
prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 5)),
prog_full_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 5)),
prog_full_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 5)),
int_clk => '0',
injectdbiterr => '0',
injectsbiterr => '0',
sleep => '0',
dout => dout,
full => full,
almost_full => almost_full,
wr_ack => wr_ack,
overflow => overflow,
empty => empty,
almost_empty => almost_empty,
valid => valid,
underflow => underflow,
data_count => data_count,
rd_data_count => rd_data_count,
wr_data_count => wr_data_count,
prog_full => prog_full,
prog_empty => prog_empty,
sbiterr => sbiterr,
dbiterr => dbiterr,
wr_rst_busy => wr_rst_busy,
rd_rst_busy => rd_rst_busy,
m_aclk => '0',
s_aclk => '0',
s_aresetn => '0',
m_aclk_en => '0',
s_aclk_en => '0',
m_axi_awid => m_axi_awid,
m_axi_awaddr => m_axi_awaddr,
m_axi_awlen => m_axi_awlen,
m_axi_awsize => m_axi_awsize,
m_axi_awburst => m_axi_awburst,
m_axi_awlock => m_axi_awlock,
m_axi_awcache => m_axi_awcache,
m_axi_awprot => m_axi_awprot,
m_axi_awqos => m_axi_awqos,
m_axi_awregion => m_axi_awregion,
m_axi_awuser => m_axi_awuser,
m_axi_awvalid => m_axi_awvalid,
m_axi_awready => '0',
m_axi_wid => m_axi_wid,
m_axi_wdata => m_axi_wdata,
m_axi_wstrb => m_axi_wstrb,
m_axi_wlast => m_axi_wlast,
m_axi_wuser => m_axi_wuser,
m_axi_wvalid => m_axi_wvalid,
m_axi_wready => '0',
m_axi_bid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_bresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_buser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_bvalid => '0',
m_axi_bready => m_axi_bready,
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awvalid => '0',
s_axi_awready => s_axi_awready,
s_axi_wid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_wlast => '0',
s_axi_wuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wvalid => '0',
s_axi_wready => s_axi_wready,
s_axi_bid => s_axi_bid,
s_axi_bresp => s_axi_bresp,
s_axi_buser => s_axi_buser,
s_axi_bready => '0',
m_axi_arid => m_axi_arid,
m_axi_araddr => m_axi_araddr,
m_axi_arlen => m_axi_arlen,
m_axi_arsize => m_axi_arsize,
m_axi_arburst => m_axi_arburst,
m_axi_arlock => m_axi_arlock,
m_axi_arcache => m_axi_arcache,
m_axi_arprot => m_axi_arprot,
m_axi_arqos => m_axi_arqos,
m_axi_arregion => m_axi_arregion,
m_axi_aruser => m_axi_aruser,
m_axi_arvalid => m_axi_arvalid,
m_axi_arready => '0',
m_axi_rid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_rdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
m_axi_rresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_rlast => '0',
m_axi_ruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_rvalid => '0',
m_axi_rready => m_axi_rready,
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_arcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_aruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_arvalid => '0',
s_axi_arready => s_axi_arready,
s_axi_rid => s_axi_rid,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rlast => s_axi_rlast,
s_axi_ruser => s_axi_ruser,
s_axi_rready => '0',
m_axis_tvalid => m_axis_tvalid,
m_axis_tready => '0',
m_axis_tdata => m_axis_tdata ,
m_axis_tstrb => m_axis_tstrb ,
m_axis_tkeep => m_axis_tkeep ,
m_axis_tlast => m_axis_tlast ,
m_axis_tid => m_axis_tid ,
m_axis_tdest => m_axis_tdest ,
m_axis_tuser => m_axis_tuser ,
s_axis_tvalid => '0',
s_axis_tready => s_axis_tready,
s_axis_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_tstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tkeep => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tlast => '0',
s_axis_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_aw_injectsbiterr => '0',
axi_aw_injectdbiterr => '0',
axi_aw_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_aw_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_aw_data_count => axi_aw_data_count,
axi_aw_wr_data_count => axi_aw_wr_data_count,
axi_aw_rd_data_count => axi_aw_rd_data_count,
axi_aw_sbiterr => axi_aw_sbiterr,
axi_aw_dbiterr => axi_aw_dbiterr,
axi_aw_overflow => axi_aw_overflow,
axi_aw_underflow => axi_aw_underflow,
axi_aw_prog_full => axi_aw_prog_full,
axi_aw_prog_empty => axi_aw_prog_empty,
axi_w_injectsbiterr => '0',
axi_w_injectdbiterr => '0',
axi_w_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_w_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_w_data_count => axi_w_data_count,
axi_w_wr_data_count => axi_w_wr_data_count,
axi_w_rd_data_count => axi_w_rd_data_count,
axi_w_sbiterr => axi_w_sbiterr,
axi_w_dbiterr => axi_w_dbiterr,
axi_w_overflow => axi_w_overflow,
axi_w_underflow => axi_w_underflow,
axi_w_prog_full => axi_w_prog_full,
axi_w_prog_empty => axi_w_prog_empty,
axi_b_injectsbiterr => '0',
axi_b_injectdbiterr => '0',
axi_b_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_b_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_b_data_count => axi_b_data_count,
axi_b_wr_data_count => axi_b_wr_data_count,
axi_b_rd_data_count => axi_b_rd_data_count,
axi_b_sbiterr => axi_b_sbiterr,
axi_b_dbiterr => axi_b_dbiterr,
axi_b_overflow => axi_b_overflow,
axi_b_underflow => axi_b_underflow,
axi_b_prog_full => axi_b_prog_full,
axi_b_prog_empty => axi_b_prog_empty,
axi_ar_injectsbiterr => '0',
axi_ar_injectdbiterr => '0',
axi_ar_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_ar_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_ar_data_count => axi_ar_data_count,
axi_ar_wr_data_count => axi_ar_wr_data_count,
axi_ar_rd_data_count => axi_ar_rd_data_count,
axi_ar_sbiterr => axi_ar_sbiterr,
axi_ar_dbiterr => axi_ar_dbiterr,
axi_ar_overflow => axi_ar_overflow,
axi_ar_underflow => axi_ar_underflow,
axi_ar_prog_full => axi_ar_prog_full,
axi_ar_prog_empty => axi_ar_prog_empty,
axi_r_injectsbiterr => '0',
axi_r_injectdbiterr => '0',
axi_r_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_r_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_r_data_count => axi_r_data_count,
axi_r_wr_data_count => axi_r_wr_data_count,
axi_r_rd_data_count => axi_r_rd_data_count,
axi_r_sbiterr => axi_r_sbiterr,
axi_r_dbiterr => axi_r_dbiterr,
axi_r_overflow => axi_r_overflow,
axi_r_underflow => axi_r_underflow,
axi_r_prog_full => axi_r_prog_full,
axi_r_prog_empty => axi_r_prog_empty,
axis_injectsbiterr => '0',
axis_injectdbiterr => '0',
axis_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axis_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axis_data_count => axis_data_count,
axis_wr_data_count => axis_wr_data_count,
axis_rd_data_count => axis_rd_data_count,
axis_sbiterr => axis_sbiterr,
axis_dbiterr => axis_dbiterr,
axis_overflow => axis_overflow,
axis_underflow => axis_underflow,
axis_prog_full => axis_prog_full,
axis_prog_empty => axis_prog_empty
);
end rtl;
|
-------------------------------------------------------------------------------
-- Copyright (c) 2014 Xilinx, Inc.
-- All Rights Reserved
-------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 13.4
-- \ \ Application: XILINX CORE Generator
-- / / Filename : chipscope_icon.vhd
-- /___/ /\ Timestamp : Sat Nov 01 15:30:54 BRST 2014
-- \ \ / \
-- \___\/\___\
--
-- Design Name: VHDL Synthesis Wrapper
-------------------------------------------------------------------------------
-- This wrapper is used to integrate with Project Navigator and PlanAhead
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY chipscope_icon IS
port (
CONTROL0: inout std_logic_vector(35 downto 0);
CONTROL1: inout std_logic_vector(35 downto 0);
CONTROL2: inout std_logic_vector(35 downto 0));
END chipscope_icon;
ARCHITECTURE chipscope_icon_a OF chipscope_icon IS
BEGIN
END chipscope_icon_a;
|
--========================================================================================================================
-- Copyright (c) 2017 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <[email protected]>.
--
-- UVVM AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
-- WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS
-- OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
-- OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH UVVM OR THE USE OR OTHER DEALINGS IN UVVM.
--========================================================================================================================
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library uvvm_vvc_framework;
use uvvm_vvc_framework.ti_vvc_framework_support_pkg.all;
library bitvis_vip_sbi;
library bitvis_vip_uart;
library bitvis_uart;
-- Test harness entity
entity uart_vvc_th is
end entity;
-- Test harness architecture
architecture struct of uart_vvc_th is
-- DSP interface and general control signals
signal clk : std_logic := '0';
signal arst : std_logic := '0';
-- SBI VVC signals
signal cs : std_logic;
signal addr : unsigned(2 downto 0);
signal wr : std_logic;
signal rd : std_logic;
signal wdata : std_logic_vector(7 downto 0);
signal rdata : std_logic_vector(7 downto 0);
signal ready : std_logic;
-- UART VVC signals
signal uart_vvc_rx : std_logic := '1';
signal uart_vvc_tx : std_logic := '1';
constant C_CLK_PERIOD : time := 10 ns; -- 100 MHz
begin
-----------------------------------------------------------------------------
-- Instantiate the concurrent procedure that initializes UVVM
-----------------------------------------------------------------------------
i_ti_uvvm_engine : entity uvvm_vvc_framework.ti_uvvm_engine;
-----------------------------------------------------------------------------
-- Instantiate DUT
-----------------------------------------------------------------------------
i_uart: entity work.uart
port map (
-- DSP interface and general control signals
clk => clk,
arst => arst,
-- CPU interface
cs => cs,
addr => addr,
wr => wr,
rd => rd,
wdata => wdata,
rdata => rdata,
-- UART signals
rx_a => uart_vvc_tx,
tx => uart_vvc_rx
);
-----------------------------------------------------------------------------
-- SBI VVC
-----------------------------------------------------------------------------
i1_sbi_vvc: entity bitvis_vip_sbi.sbi_vvc
generic map(
GC_ADDR_WIDTH => 3,
GC_DATA_WIDTH => 8,
GC_INSTANCE_IDX => 1
)
port map(
clk => clk,
sbi_vvc_master_if.cs => cs,
sbi_vvc_master_if.rena => rd,
sbi_vvc_master_if.wena => wr,
sbi_vvc_master_if.addr => addr,
sbi_vvc_master_if.wdata => wdata,
sbi_vvc_master_if.ready => ready,
sbi_vvc_master_if.rdata => rdata
);
-----------------------------------------------------------------------------
-- UART VVC
-----------------------------------------------------------------------------
i1_uart_vvc: entity bitvis_vip_uart.uart_vvc
generic map(
GC_DATA_WIDTH => 8,
GC_INSTANCE_IDX => 1
)
port map(
uart_vvc_rx => uart_vvc_rx,
uart_vvc_tx => uart_vvc_tx
);
-- Static '1' ready signal for the SBI VVC
ready <= '1';
-- Toggle the reset after 5 clock periods
p_arst: arst <= '1', '0' after 5 *C_CLK_PERIOD;
-----------------------------------------------------------------------------
-- Clock process
-----------------------------------------------------------------------------
p_clk: process
begin
clk <= '0', '1' after C_CLK_PERIOD / 2;
wait for C_CLK_PERIOD;
end process;
end struct;
|
--========================================================================================================================
-- Copyright (c) 2017 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <[email protected]>.
--
-- UVVM AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
-- WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS
-- OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
-- OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH UVVM OR THE USE OR OTHER DEALINGS IN UVVM.
--========================================================================================================================
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library uvvm_vvc_framework;
use uvvm_vvc_framework.ti_vvc_framework_support_pkg.all;
library bitvis_vip_sbi;
library bitvis_vip_uart;
library bitvis_uart;
-- Test harness entity
entity uart_vvc_th is
end entity;
-- Test harness architecture
architecture struct of uart_vvc_th is
-- DSP interface and general control signals
signal clk : std_logic := '0';
signal arst : std_logic := '0';
-- SBI VVC signals
signal cs : std_logic;
signal addr : unsigned(2 downto 0);
signal wr : std_logic;
signal rd : std_logic;
signal wdata : std_logic_vector(7 downto 0);
signal rdata : std_logic_vector(7 downto 0);
signal ready : std_logic;
-- UART VVC signals
signal uart_vvc_rx : std_logic := '1';
signal uart_vvc_tx : std_logic := '1';
constant C_CLK_PERIOD : time := 10 ns; -- 100 MHz
begin
-----------------------------------------------------------------------------
-- Instantiate the concurrent procedure that initializes UVVM
-----------------------------------------------------------------------------
i_ti_uvvm_engine : entity uvvm_vvc_framework.ti_uvvm_engine;
-----------------------------------------------------------------------------
-- Instantiate DUT
-----------------------------------------------------------------------------
i_uart: entity work.uart
port map (
-- DSP interface and general control signals
clk => clk,
arst => arst,
-- CPU interface
cs => cs,
addr => addr,
wr => wr,
rd => rd,
wdata => wdata,
rdata => rdata,
-- UART signals
rx_a => uart_vvc_tx,
tx => uart_vvc_rx
);
-----------------------------------------------------------------------------
-- SBI VVC
-----------------------------------------------------------------------------
i1_sbi_vvc: entity bitvis_vip_sbi.sbi_vvc
generic map(
GC_ADDR_WIDTH => 3,
GC_DATA_WIDTH => 8,
GC_INSTANCE_IDX => 1
)
port map(
clk => clk,
sbi_vvc_master_if.cs => cs,
sbi_vvc_master_if.rena => rd,
sbi_vvc_master_if.wena => wr,
sbi_vvc_master_if.addr => addr,
sbi_vvc_master_if.wdata => wdata,
sbi_vvc_master_if.ready => ready,
sbi_vvc_master_if.rdata => rdata
);
-----------------------------------------------------------------------------
-- UART VVC
-----------------------------------------------------------------------------
i1_uart_vvc: entity bitvis_vip_uart.uart_vvc
generic map(
GC_DATA_WIDTH => 8,
GC_INSTANCE_IDX => 1
)
port map(
uart_vvc_rx => uart_vvc_rx,
uart_vvc_tx => uart_vvc_tx
);
-- Static '1' ready signal for the SBI VVC
ready <= '1';
-- Toggle the reset after 5 clock periods
p_arst: arst <= '1', '0' after 5 *C_CLK_PERIOD;
-----------------------------------------------------------------------------
-- Clock process
-----------------------------------------------------------------------------
p_clk: process
begin
clk <= '0', '1' after C_CLK_PERIOD / 2;
wait for C_CLK_PERIOD;
end process;
end struct;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity CI_4511 is
Port ( Ai, Bi, Ci, Di : in STD_LOGIC;
Ao, Bo, Co, Do, Eo, Fo, Go : out STD_LOGIC
);
end CI_4511;
architecture Behavioral of CI_4511 is
begin
process(Ai, Bi, Ci, Di)
begin
if (Ai = '1') and (Bi = '0') and (Ci = '0') and (Di = '0') then
Ao <= '0';
Bo <= '1';
Co <= '1';
Do <= '0';
Eo <= '0';
Fo <= '0';
Go <= '0';
elsif (Ai = '0') and (Bi = '1') and (Ci = '0') and (Di = '0') then
Ao <= '1';
Bo <= '1';
Co <= '0';
Do <= '1';
Eo <= '1';
Fo <= '0';
Go <= '1';
elsif (Ai = '1') and (Bi = '1') and (Ci = '0') and (Di = '0') then
Ao <= '1';
Bo <= '1';
Co <= '1';
Do <= '1';
Eo <= '0';
Fo <= '0';
Go <= '1';
elsif (Ai = '0') and (Bi = '0') and (Ci = '1') and (Di = '0') then
Ao <= '0';
Bo <= '1';
Co <= '1';
Do <= '0';
Eo <= '0';
Fo <= '1';
Go <= '1';
elsif (Ai = '1') and (Bi = '0') and (Ci = '1') and (Di = '0') then
Ao <= '1';
Bo <= '0';
Co <= '1';
Do <= '1';
Eo <= '0';
Fo <= '1';
Go <= '1';
elsif (Ai = '0') and (Bi = '1') and (Ci = '1') and (Di = '0') then
Ao <= '0';
Bo <= '0';
Co <= '1';
Do <= '1';
Eo <= '1';
Fo <= '1';
Go <= '1';
elsif (Ai = '1') and (Bi = '1') and (Ci = '1') and (Di = '0') then
Ao <= '1';
Bo <= '1';
Co <= '1';
Do <= '0';
Eo <= '0';
Fo <= '0';
Go <= '0';
elsif (Ai = '0') and (Bi = '0') and (Ci = '0') and (Di = '1') then
Ao <= '1';
Bo <= '1';
Co <= '1';
Do <= '1';
Eo <= '1';
Fo <= '1';
Go <= '1';
elsif (Ai = '1') and (Bi = '0') and (Ci = '0') and (Di = '1') then
Ao <= '1';
Bo <= '1';
Co <= '1';
Do <= '0';
Eo <= '0';
Fo <= '0';
Go <= '0';
else
Ao <= '0';
Bo <= '0';
Co <= '0';
Do <= '0';
Eo <= '0';
Fo <= '0';
Go <= '0';
end if;
end process;
end Behavioral; |
-------------------------------------------------------------------------------
-- ac97_core.vhd
-------------------------------------------------------------------------------
--
-- Mike Wirthlin
--
-------------------------------------------------------------------------------
-- Filename: ac97_acore.vhd
--
-- Description: Provides a simple synchronous interface to a
-- AC97 codec. This was designed for the National
-- LM4549A and only supports slots 0-4.
-- This interface does not have any data buffering.
--
-- The interface to the AC97 is straightforward.
-- To transfer playback data, this interface will
-- sample the playback data and control signals
-- when the PCM_Playback_X_Accept signals are asserted.
-- This sample will
-- be sent to the codec during the next frame. The Record (
-- input) data is provided as an ouptput and is valid when
-- new_frame is asserted.
--
-- This core supports the full 20-bit PCM sample size. The
-- actual size of the PCM can be modified to a lower value for
-- easier interfacing using the C_PCM_DATA_WIDTH generic. This
-- core will stuff the remaining lsb bits with '0' if a value
-- lower than 20 is used.
--
-- This core is synchronous to the AC97_Bit_Clk and all
-- signals interfacing to this core should be synchronized to
-- this clock.
--
-- AC97 Register Interface
--
-- This core provides a simple interface to the AC97 codec registers. To write
-- a new value to the register, drive the AC97_Reg_Addr and
-- AC97_Reg_Write_Data input signals and assert the AC97_Reg_Write_Strobe
-- signal. To read a register value, drive the AC97_Reg_Addr and assert
-- the AC97_Reg_Read_Strobe signal. Once either strobe has been asserted, the
-- register interface state machine will process the request to the CODEC and
-- assert the AC97_Reg_Busy signal. The strobe control signals will be ignored
-- while the state machine is busy (the AC97 only supports one read or write
-- transaction at a time).
--
-- When the transaction is complete, the state machine will respond as
-- follows: first, the AC97_Reg_Busy signal will be deasserted indicating that
-- the transaction is complete and that the interface is ready to handle
-- another interface. If there was an error with the response (i.e. the AC97
-- codec did not respond properly to the request), the AC97_Reg_Error signal
-- will be asserted. This signal will remain asserted until a new register
-- transfer has been initiated.
--
-- On the successful completion of a register read operation, the
-- AC97_Reg_Read_Data_Valid signal will be asserted to validate the data
-- read from the AC97 controller. This signal will remain asserted until a new
-- register transaction is initiated.
--
--
-- This core will produce valid data on the AC97_SData_Out signal
-- during the following slots:
--
-- Slot 0: Tag Phase (indicates valid slots in packet)
-- Slot 1: Read/Write, Control Address
-- Slot 2: Command Data
-- Slot 3: PCM Left
-- Slot 4: PCM Right
--
-- This core will recognize valid data on the AC97_SData_In signal
-- during the following slots:
--
-- Slot 0: Codec/Slot Status Bits
-- Slot 1: Status Address / Slot Request
-- Slot 2: Status Data
-- Slot 3: PCM Record Left
-- Slot 4: PCM Record Righ
--
-- To Do:
-- - signal to validate recorded data
-- - signal to "request" playback data
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- - ac97_core
-- - ac97_timing
--
-------------------------------------------------------------------------------
-- Author: Mike Wirthlin
--
-- History:
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use std.TextIO.all;
library opb_ac97_v2_00_a;
use opb_ac97_v2_00_a.all;
-------------------------------------------------------------------------------
--
-- Genearics Summary
-- C_PLAYBACK: Enable playback logic. Disable to simplify circuit
-- C_RECORD: Enable record logic. Disable to simplify circuit
-- C_PCM_DATA_WIDTH:
-- AC97 specifies a 20-bit data word. HOwever, many codecs don't
-- support the full resolution (The LM4549 only supports 18). This
-- value indicates the number of data bits that will be sent/received
-- from the CODEC. Zeros will be inserted for least-significant digits.
--
-- Signal Summary
--
-- AC97_Bit_Clk:
-- Input clock generated by the AC97 Codec
-- AC97_Sync:
-- Frame synchronization signal. Generated by ac97_timing module.
-- AC97_SData_Out:
-- Serial data out. Transitions on the rising edge of bit_clk. Is
-- sampled by the CODEC on the falling edge
-- AC97_SData_In:
-- Serial data in. Transitions on the rising edge of bit_clk. Is
-- sampled by the this module on the falling edge.
-- AC97_SData_In:
-- CODEC_RDY:
-- This signal is generated by each frame from the AC97
-- Codec. It arrives each frame as the first bit of Slot 1.
-------------------------------------------------------------------------------
entity ac97_core is
generic (
C_PCM_DATA_WIDTH : integer := 16
);
port (
Reset : in std_logic;
-- signals attaching directly to AC97 codec
AC97_Bit_Clk : in std_logic;
AC97_Sync : out std_logic;
AC97_SData_Out : out std_logic;
AC97_SData_In : in std_logic;
-- AC97 register interface
AC97_Reg_Addr : in std_logic_vector(0 to 6);
AC97_Reg_Write_Data : in std_logic_vector(0 to 15);
AC97_Reg_Read_Data : out std_logic_vector(0 to 15);
AC97_Reg_Read_Strobe : in std_logic; -- initiates a "read" command
AC97_Reg_Write_Strobe : in std_logic; -- initiates a "write" command
AC97_Reg_Busy : out std_logic;
AC97_Reg_Error : out std_logic;
AC97_Reg_Read_Data_Valid : out std_logic;
-- Playback signal interface
PCM_Playback_Left: in std_logic_vector(0 to C_PCM_DATA_WIDTH-1);
PCM_Playback_Right: in std_logic_vector(0 to C_PCM_DATA_WIDTH-1);
PCM_Playback_Left_Valid: in std_logic;
PCM_Playback_Right_Valid: in std_logic;
PCM_Playback_Left_Accept: out std_logic;
PCM_Playback_Right_Accept: out std_logic;
-- Record signal interface
PCM_Record_Left: out std_logic_vector(0 to C_PCM_DATA_WIDTH-1);
PCM_Record_Right: out std_logic_vector(0 to C_PCM_DATA_WIDTH-1);
PCM_Record_Left_Valid: out std_logic;
PCM_Record_Right_Valid: out std_logic;
DEBUG : out std_logic_vector(0 to 15);
--
CODEC_RDY : out std_logic
);
end entity ac97_core;
library unisim;
use unisim.all;
architecture IMP of ac97_core is
component ac97_timing is
port (
Bit_Clk : in std_logic;
Reset : in std_logic;
Sync : out std_logic;
Bit_Num : out natural range 0 to 19;
Slot_Num : out natural range 0 to 12;
Slot_End : out std_logic;
Frame_End : out std_logic
);
end component ac97_timing;
signal last_frame_cycle : std_logic;
signal sync_i : std_logic;
signal slot_end : std_logic;
signal slot_No : natural range 0 to 12;
--signal bit_No : natural range 0 to 19;
-- register IF signals
type reg_if_states is (IDLE, WAIT_FOR_NEW_FRAME, SEND_REQUEST_FRAME,
RESPONSE_SLOT0, RESPONSE_SLOT1, RESPONSE_SLOT2,
END_STATE);
signal reg_if_state : reg_if_states := IDLE;
signal register_addr : std_logic_vector(0 to 6) := (others => '0');
signal register_data : std_logic_vector(0 to 15) := (others => '0');
signal register_write_cmd : std_logic := '0';
signal ac97_reg_error_i, ac97_reg_busy_i : std_logic := '0';
signal valid_Frame : std_logic;
signal valid_Control_Addr : std_logic;
-- Slot 0 in signals
signal record_pcm_left_valid : std_logic;
signal record_pcm_right_valid : std_logic;
--signal return_status_address_valid : std_logic;
--signal return_status_data_valid : std_logic;
signal accept_pcm_left : std_logic;
signal accept_pcm_right : std_logic;
signal new_data_out : std_logic_vector(19 downto 0) := (others => '0');
signal data_out : std_logic_vector(19 downto 0) := (others => '0');
signal data_in : std_logic_vector(19 downto 0);
signal slot0 : std_logic_vector(15 downto 0);
signal slot1 : std_logic_vector(19 downto 0);
signal slot2 : std_logic_vector(19 downto 0);
signal slot3 : std_logic_vector(19 downto 0) := (others => '0');
signal slot4 : std_logic_vector(19 downto 0) := (others => '0');
signal codec_rdy_i : std_logic := '0';
signal PCM_Record_Left_i: std_logic_vector(0 to C_PCM_DATA_WIDTH-1);
signal PCM_Record_Right_i: std_logic_vector(0 to C_PCM_DATA_WIDTH-1);
begin -- architecture IMP
-----------------------------------------------------------------------------
-- AC97 Timing Module & Interface signals
-----------------------------------------------------------------------------
ac97_timing_I_1 : ac97_timing
port map (
Bit_Clk => AC97_Bit_Clk,
Reset => Reset,
Sync => sync_i,
Bit_Num => open,
Slot_Num => slot_No,
Slot_End => slot_end,
Frame_End => last_frame_cycle
);
AC97_Sync <= sync_i;
-----------------------------------------------------------------------------
-- AC97 Register Interface
-----------------------------------------------------------------------------
-- Register state machine
register_if_PROCESS : process (AC97_Bit_Clk) is
begin
if RESET = '1' then
reg_if_state <= IDLE;
ac97_reg_busy_i <= '0';
ac97_reg_error_i <= '0';
AC97_Reg_Read_Data_Valid <= '0';
elsif AC97_Bit_Clk'event and AC97_Bit_Clk = '1' then
case reg_if_state is
-- Wait for a register transfer strobe to occur.
when IDLE =>
if (AC97_Reg_Read_Strobe = '1' or AC97_Reg_Write_Strobe = '1')
and codec_rdy_i = '1' then
reg_if_state <= WAIT_FOR_NEW_FRAME;
ac97_reg_busy_i <= '1';
ac97_reg_error_i <= '0';
AC97_Reg_Read_Data_Valid <= '0';
register_addr <= AC97_Reg_Addr;
if AC97_Reg_Write_Strobe = '1' then
register_data <= AC97_Reg_Write_Data;
register_write_cmd <= '1';
else
register_write_cmd <= '0';
end if;
end if;
-- Wait for the end of the current frame. During the last cycle of
-- this state (last_frame_cycle = 1), all the signals are
-- latched into slot 0 and a valid request is on its way out.
when WAIT_FOR_NEW_FRAME =>
if last_frame_cycle = '1' then
reg_if_state <= SEND_REQUEST_FRAME;
end if;
-- Wait for the request to be completely sent to the codec.
when SEND_REQUEST_FRAME =>
if last_frame_cycle = '1' then
reg_if_state <= RESPONSE_SLOT0;
end if;
-- Wait for the response in slot 0 and make sure the
-- appropriate response bits are set
when RESPONSE_SLOT0 =>
if slot_No = 0 and slot_end = '1' then
if register_write_cmd = '0' then
if (data_in(14) /= '1' or data_in(13) /= '1') then
-- Bit 14 of Slot 0 indicates a valid slot 1 data
-- (echo the requested address). If this is not a
-- '1' then there is was an error. Bit 13 of Slot 0
-- indicates a valid data response. If the transaction
-- was a read and it is not true, an error.
ac97_reg_error_i <= '1';
reg_if_state <= END_STATE;
else
reg_if_state <= RESPONSE_SLOT1;
end if;
else
-- Nothing else to do for writes
reg_if_state <= END_STATE;
end if;
end if;
-- Check the data in slot 1 and make sure it matches
-- the address sent
when RESPONSE_SLOT1 =>
if slot_No = 1 and slot_end = '1' then
if data_in(18 downto 12) /= register_addr then
ac97_reg_error_i <= '1';
reg_if_state <= END_STATE;
else
-- we need to get the data for read commands
reg_if_state <= RESPONSE_SLOT2;
end if;
end if;
when RESPONSE_SLOT2 =>
if slot_No = 2 and slot_end = '1' then
AC97_Reg_Read_Data <= data_in(19 downto 4);
AC97_Reg_Read_Data_Valid <= '1';
reg_if_state <= END_STATE;
end if;
when END_STATE =>
ac97_reg_busy_i <= '0';
reg_if_state <= IDLE;
when others => NULL;
end case;
end if;
end process register_if_PROCESS;
AC97_Reg_Busy <= ac97_reg_busy_i;
AC97_Reg_Error <= ac97_reg_error_i;
with reg_if_state select
debug(0 to 2) <= "000" when IDLE,
"001" when WAIT_FOR_NEW_FRAME,
"010" when SEND_REQUEST_FRAME,
"011" when RESPONSE_SLOT0,
"100" when RESPONSE_SLOT1,
"101" when RESPONSE_SLOT2,
"110" when END_STATE,
"000" when others;
debug(3 to 15) <= (others => '0');
-- This signal indicates that we are sending a request command
-- and that the address send to the codec is valid
valid_Control_Addr <= '1' when reg_if_state = WAIT_FOR_NEW_FRAME
else '0';
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Output Section
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Setup slot0 data at start of frame
--
-- Slot 0 is the TAG slot. The bits of this slot are defined as
-- follows:
-- bit 15: Valid frame
-- bit 14: valid control address (slot 1)
-- bit 13: valid control data (slot 2)
-- bit 12: valid PCM playback data Left (slot 3)
-- bit 11: valid PCM playback data Right (slot 4)
-- bot 10-2: ignored - fill with zeros
-- bit 1-0: 2-bit codec ID (assigned to '00' for primary)
--
-- The slot 0 signals are created directly from the inputs
-- of the module rather than using the "registered" versions
-- (i.e. ac97_reg_write instead of ac97_reag_write_i). The
-- slot0 signal is latched on the clock edge following
-- the frame signal into the shift register signal "data_out".
--
-----------------------------------------------------------------------------
-- temporary
valid_Frame <= valid_Control_Addr or
pcm_playback_left_valid or
pcm_playback_right_valid;
slot0(15) <= valid_Frame;
slot0(14) <= valid_Control_Addr;
slot0(13) <= register_write_cmd; -- valid data only during write
slot0(12) <= PCM_Playback_Left_Valid;
slot0(11) <= PCM_Playback_Right_Valid;
slot0(10 downto 2) <= "000000000";
slot0(1 downto 0) <= "00";
-----------------------------------------------------------------------------
-- Slot 1
--
-- Slot 1 is the Command Address:
-- Bit 19: Read/Write (1=read,0=write)
-- Bit 18-12: Control register index/address
-- Bit 11:0 reserved (stuff with 0)
-----------------------------------------------------------------------------
slot1(19) <= not register_write_cmd;
slot1(18 downto 12) <= register_addr;
slot1(11 downto 0) <= (others => '0');
-----------------------------------------------------------------------------
-- Slot 2
--
-- Slot 2 is the Command Data Port:
-- Bit 19-4: Control register write data
-- Bit 3-0: reserved (stuff with 0)
-----------------------------------------------------------------------------
slot2(19 downto 4) <= register_data;
slot2( 3 downto 0) <= (others => '0');
-----------------------------------------------------------------------------
-- Setup slot3 data (PCM play left)
-----------------------------------------------------------------------------
process (PCM_Playback_Left) is
begin
slot3((20 - C_PCM_DATA_WIDTH-1) downto 0) <= (others => '0');
slot3(19 downto (20 - C_PCM_DATA_WIDTH)) <= PCM_Playback_Left;
end process;
-----------------------------------------------------------------------------
-- Setup slot4 data (PCM play right)
-----------------------------------------------------------------------------
process (PCM_Playback_Right) is
begin
slot4((20 - C_PCM_DATA_WIDTH-1) downto 0) <= (others => '0');
slot4(19 downto (20 - C_PCM_DATA_WIDTH)) <= PCM_Playback_Right;
end process;
-----------------------------------------------------------------------------
-- Output data multiplexer for AC97_SData_Out signal
--
-- Choose the appropriate data to send out the shift register
-- (new_data_out)
-----------------------------------------------------------------------------
process (last_frame_cycle, slot_end, slot_No, slot0,
slot1, slot2, slot3, slot4) is
begin -- process
new_data_out <= (others => '0');
if (last_frame_cycle = '1') then
new_data_out(19 downto 4) <= slot0;
elsif (slot_end = '1') then
case slot_No is
when 0 => new_data_out(slot1'range) <= slot1;
when 1 => new_data_out(slot2'range) <= slot2;
when 2 => new_data_out <= slot3;
when 3 => new_data_out <= slot4;
when others => null;
end case;
end if;
end process;
-----------------------------------------------------------------------------
-- AC97 data out shift register
-----------------------------------------------------------------------------
Data_Out_Handle : process (AC97_Bit_Clk) is
begin -- process Data_Out_Handle
if reset = '1' then
data_out <= (others => '0');
elsif AC97_Bit_Clk'event and AC97_Bit_Clk = '1' then -- rising clock edge
if (last_frame_cycle = '1') or (slot_end = '1') then
data_out <= New_Data_Out;
else
data_out(19 downto 0) <= data_out(18 downto 0) & '0';
end if;
end if;
end process Data_Out_Handle;
AC97_SData_Out <= data_out(19);
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Input Section
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- AC97 data in shift register
-----------------------------------------------------------------------------
Shifting_Data_Coming_Back : process (AC97_Bit_Clk) is
begin -- process Shifting_Data_Coming_Back
if AC97_Bit_Clk'event and AC97_Bit_Clk = '0' then -- falling clock edge
data_in(19 downto 0) <= data_in(18 downto 0) & AC97_SData_In;
end if;
end process Shifting_Data_Coming_Back;
-----------------------------------------------------------------------------
-- Get slot 0 data (TAG - which slots are valid)
-----------------------------------------------------------------------------
process (AC97_Bit_Clk) is
begin
if AC97_Bit_Clk'event and AC97_Bit_Clk = '1' then -- rising clock edge
if (slot_no = 0 and slot_end = '1') then
codec_rdy_i <= data_in(15);
-- data_in(14) and data(13) are used directly in the reg_if
-- state machine
--return_status_address_valid <= data_in(14);
-- return_status_data_valid <= data_in(13);
record_pcm_left_valid <= data_in(12);
record_pcm_right_valid <= data_in(11);
end if;
end if;
end process;
PCM_Record_Left_Valid <= record_pcm_left_valid and last_frame_cycle;
PCM_Record_Right_Valid <= record_pcm_right_valid and last_frame_cycle;
codec_rdy <= codec_rdy_i;
-----------------------------------------------------------------------------
-- Get slot 1 PCM request bit
-----------------------------------------------------------------------------
process (AC97_Bit_Clk) is
begin
if AC97_Bit_Clk'event and AC97_Bit_Clk = '1' then
if (slot_end = '1' and slot_No = 1 ) then
accept_pcm_left <= not data_in(11);
accept_pcm_right <= not data_in(10);
end if;
end if;
end process;
PCM_Playback_Left_Accept <= accept_pcm_left and last_frame_cycle;
PCM_Playback_Right_Accept <= accept_pcm_right and last_frame_cycle;
-----------------------------------------------------------------------------
-- Get slot 3 and 4 data
-----------------------------------------------------------------------------
Get_Record_Data : process (AC97_Bit_Clk) is
-- synthesis translate_off
variable my_line : LINE;
-- synthesis translate_on
begin -- process Get_Record_Data
if AC97_Bit_Clk'event and AC97_Bit_Clk = '1' then -- rising clock edge
if (slot_end = '1' and slot_No = 3 ) then
PCM_Record_Left_i <= data_in(19 downto (20 - C_PCM_DATA_WIDTH));
-- synthesis translate_off
write(my_line, string'("AC97 Core: Received Left Value "));
write(my_line, bit_vector'( To_bitvector(PCM_Record_Left_i) ));
writeline(output, my_line);
-- synthesis translate_on
elsif (slot_end = '1' and slot_No = 4 ) then
PCM_Record_Right_i <= data_in(19 downto (20 - C_PCM_DATA_WIDTH));
-- synthesis translate_off
write(my_line, string'("AC97 Core: Received Right Value "));
write(my_line, bit_vector'( To_bitvector(PCM_Record_Right_i) ));
writeline(output, my_line);
-- synthesis translate_on
end if;
end if;
end process Get_Record_Data;
PCM_Record_Left <= PCM_Record_Left_i;
PCM_Record_Right <= PCM_Record_Right_i;
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
end architecture IMP;
|
-------------------------------------------------------------------------------
-- ac97_core.vhd
-------------------------------------------------------------------------------
--
-- Mike Wirthlin
--
-------------------------------------------------------------------------------
-- Filename: ac97_acore.vhd
--
-- Description: Provides a simple synchronous interface to a
-- AC97 codec. This was designed for the National
-- LM4549A and only supports slots 0-4.
-- This interface does not have any data buffering.
--
-- The interface to the AC97 is straightforward.
-- To transfer playback data, this interface will
-- sample the playback data and control signals
-- when the PCM_Playback_X_Accept signals are asserted.
-- This sample will
-- be sent to the codec during the next frame. The Record (
-- input) data is provided as an ouptput and is valid when
-- new_frame is asserted.
--
-- This core supports the full 20-bit PCM sample size. The
-- actual size of the PCM can be modified to a lower value for
-- easier interfacing using the C_PCM_DATA_WIDTH generic. This
-- core will stuff the remaining lsb bits with '0' if a value
-- lower than 20 is used.
--
-- This core is synchronous to the AC97_Bit_Clk and all
-- signals interfacing to this core should be synchronized to
-- this clock.
--
-- AC97 Register Interface
--
-- This core provides a simple interface to the AC97 codec registers. To write
-- a new value to the register, drive the AC97_Reg_Addr and
-- AC97_Reg_Write_Data input signals and assert the AC97_Reg_Write_Strobe
-- signal. To read a register value, drive the AC97_Reg_Addr and assert
-- the AC97_Reg_Read_Strobe signal. Once either strobe has been asserted, the
-- register interface state machine will process the request to the CODEC and
-- assert the AC97_Reg_Busy signal. The strobe control signals will be ignored
-- while the state machine is busy (the AC97 only supports one read or write
-- transaction at a time).
--
-- When the transaction is complete, the state machine will respond as
-- follows: first, the AC97_Reg_Busy signal will be deasserted indicating that
-- the transaction is complete and that the interface is ready to handle
-- another interface. If there was an error with the response (i.e. the AC97
-- codec did not respond properly to the request), the AC97_Reg_Error signal
-- will be asserted. This signal will remain asserted until a new register
-- transfer has been initiated.
--
-- On the successful completion of a register read operation, the
-- AC97_Reg_Read_Data_Valid signal will be asserted to validate the data
-- read from the AC97 controller. This signal will remain asserted until a new
-- register transaction is initiated.
--
--
-- This core will produce valid data on the AC97_SData_Out signal
-- during the following slots:
--
-- Slot 0: Tag Phase (indicates valid slots in packet)
-- Slot 1: Read/Write, Control Address
-- Slot 2: Command Data
-- Slot 3: PCM Left
-- Slot 4: PCM Right
--
-- This core will recognize valid data on the AC97_SData_In signal
-- during the following slots:
--
-- Slot 0: Codec/Slot Status Bits
-- Slot 1: Status Address / Slot Request
-- Slot 2: Status Data
-- Slot 3: PCM Record Left
-- Slot 4: PCM Record Righ
--
-- To Do:
-- - signal to validate recorded data
-- - signal to "request" playback data
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- - ac97_core
-- - ac97_timing
--
-------------------------------------------------------------------------------
-- Author: Mike Wirthlin
--
-- History:
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use std.TextIO.all;
library opb_ac97_v2_00_a;
use opb_ac97_v2_00_a.all;
-------------------------------------------------------------------------------
--
-- Genearics Summary
-- C_PLAYBACK: Enable playback logic. Disable to simplify circuit
-- C_RECORD: Enable record logic. Disable to simplify circuit
-- C_PCM_DATA_WIDTH:
-- AC97 specifies a 20-bit data word. HOwever, many codecs don't
-- support the full resolution (The LM4549 only supports 18). This
-- value indicates the number of data bits that will be sent/received
-- from the CODEC. Zeros will be inserted for least-significant digits.
--
-- Signal Summary
--
-- AC97_Bit_Clk:
-- Input clock generated by the AC97 Codec
-- AC97_Sync:
-- Frame synchronization signal. Generated by ac97_timing module.
-- AC97_SData_Out:
-- Serial data out. Transitions on the rising edge of bit_clk. Is
-- sampled by the CODEC on the falling edge
-- AC97_SData_In:
-- Serial data in. Transitions on the rising edge of bit_clk. Is
-- sampled by the this module on the falling edge.
-- AC97_SData_In:
-- CODEC_RDY:
-- This signal is generated by each frame from the AC97
-- Codec. It arrives each frame as the first bit of Slot 1.
-------------------------------------------------------------------------------
entity ac97_core is
generic (
C_PCM_DATA_WIDTH : integer := 16
);
port (
Reset : in std_logic;
-- signals attaching directly to AC97 codec
AC97_Bit_Clk : in std_logic;
AC97_Sync : out std_logic;
AC97_SData_Out : out std_logic;
AC97_SData_In : in std_logic;
-- AC97 register interface
AC97_Reg_Addr : in std_logic_vector(0 to 6);
AC97_Reg_Write_Data : in std_logic_vector(0 to 15);
AC97_Reg_Read_Data : out std_logic_vector(0 to 15);
AC97_Reg_Read_Strobe : in std_logic; -- initiates a "read" command
AC97_Reg_Write_Strobe : in std_logic; -- initiates a "write" command
AC97_Reg_Busy : out std_logic;
AC97_Reg_Error : out std_logic;
AC97_Reg_Read_Data_Valid : out std_logic;
-- Playback signal interface
PCM_Playback_Left: in std_logic_vector(0 to C_PCM_DATA_WIDTH-1);
PCM_Playback_Right: in std_logic_vector(0 to C_PCM_DATA_WIDTH-1);
PCM_Playback_Left_Valid: in std_logic;
PCM_Playback_Right_Valid: in std_logic;
PCM_Playback_Left_Accept: out std_logic;
PCM_Playback_Right_Accept: out std_logic;
-- Record signal interface
PCM_Record_Left: out std_logic_vector(0 to C_PCM_DATA_WIDTH-1);
PCM_Record_Right: out std_logic_vector(0 to C_PCM_DATA_WIDTH-1);
PCM_Record_Left_Valid: out std_logic;
PCM_Record_Right_Valid: out std_logic;
DEBUG : out std_logic_vector(0 to 15);
--
CODEC_RDY : out std_logic
);
end entity ac97_core;
library unisim;
use unisim.all;
architecture IMP of ac97_core is
component ac97_timing is
port (
Bit_Clk : in std_logic;
Reset : in std_logic;
Sync : out std_logic;
Bit_Num : out natural range 0 to 19;
Slot_Num : out natural range 0 to 12;
Slot_End : out std_logic;
Frame_End : out std_logic
);
end component ac97_timing;
signal last_frame_cycle : std_logic;
signal sync_i : std_logic;
signal slot_end : std_logic;
signal slot_No : natural range 0 to 12;
--signal bit_No : natural range 0 to 19;
-- register IF signals
type reg_if_states is (IDLE, WAIT_FOR_NEW_FRAME, SEND_REQUEST_FRAME,
RESPONSE_SLOT0, RESPONSE_SLOT1, RESPONSE_SLOT2,
END_STATE);
signal reg_if_state : reg_if_states := IDLE;
signal register_addr : std_logic_vector(0 to 6) := (others => '0');
signal register_data : std_logic_vector(0 to 15) := (others => '0');
signal register_write_cmd : std_logic := '0';
signal ac97_reg_error_i, ac97_reg_busy_i : std_logic := '0';
signal valid_Frame : std_logic;
signal valid_Control_Addr : std_logic;
-- Slot 0 in signals
signal record_pcm_left_valid : std_logic;
signal record_pcm_right_valid : std_logic;
--signal return_status_address_valid : std_logic;
--signal return_status_data_valid : std_logic;
signal accept_pcm_left : std_logic;
signal accept_pcm_right : std_logic;
signal new_data_out : std_logic_vector(19 downto 0) := (others => '0');
signal data_out : std_logic_vector(19 downto 0) := (others => '0');
signal data_in : std_logic_vector(19 downto 0);
signal slot0 : std_logic_vector(15 downto 0);
signal slot1 : std_logic_vector(19 downto 0);
signal slot2 : std_logic_vector(19 downto 0);
signal slot3 : std_logic_vector(19 downto 0) := (others => '0');
signal slot4 : std_logic_vector(19 downto 0) := (others => '0');
signal codec_rdy_i : std_logic := '0';
signal PCM_Record_Left_i: std_logic_vector(0 to C_PCM_DATA_WIDTH-1);
signal PCM_Record_Right_i: std_logic_vector(0 to C_PCM_DATA_WIDTH-1);
begin -- architecture IMP
-----------------------------------------------------------------------------
-- AC97 Timing Module & Interface signals
-----------------------------------------------------------------------------
ac97_timing_I_1 : ac97_timing
port map (
Bit_Clk => AC97_Bit_Clk,
Reset => Reset,
Sync => sync_i,
Bit_Num => open,
Slot_Num => slot_No,
Slot_End => slot_end,
Frame_End => last_frame_cycle
);
AC97_Sync <= sync_i;
-----------------------------------------------------------------------------
-- AC97 Register Interface
-----------------------------------------------------------------------------
-- Register state machine
register_if_PROCESS : process (AC97_Bit_Clk) is
begin
if RESET = '1' then
reg_if_state <= IDLE;
ac97_reg_busy_i <= '0';
ac97_reg_error_i <= '0';
AC97_Reg_Read_Data_Valid <= '0';
elsif AC97_Bit_Clk'event and AC97_Bit_Clk = '1' then
case reg_if_state is
-- Wait for a register transfer strobe to occur.
when IDLE =>
if (AC97_Reg_Read_Strobe = '1' or AC97_Reg_Write_Strobe = '1')
and codec_rdy_i = '1' then
reg_if_state <= WAIT_FOR_NEW_FRAME;
ac97_reg_busy_i <= '1';
ac97_reg_error_i <= '0';
AC97_Reg_Read_Data_Valid <= '0';
register_addr <= AC97_Reg_Addr;
if AC97_Reg_Write_Strobe = '1' then
register_data <= AC97_Reg_Write_Data;
register_write_cmd <= '1';
else
register_write_cmd <= '0';
end if;
end if;
-- Wait for the end of the current frame. During the last cycle of
-- this state (last_frame_cycle = 1), all the signals are
-- latched into slot 0 and a valid request is on its way out.
when WAIT_FOR_NEW_FRAME =>
if last_frame_cycle = '1' then
reg_if_state <= SEND_REQUEST_FRAME;
end if;
-- Wait for the request to be completely sent to the codec.
when SEND_REQUEST_FRAME =>
if last_frame_cycle = '1' then
reg_if_state <= RESPONSE_SLOT0;
end if;
-- Wait for the response in slot 0 and make sure the
-- appropriate response bits are set
when RESPONSE_SLOT0 =>
if slot_No = 0 and slot_end = '1' then
if register_write_cmd = '0' then
if (data_in(14) /= '1' or data_in(13) /= '1') then
-- Bit 14 of Slot 0 indicates a valid slot 1 data
-- (echo the requested address). If this is not a
-- '1' then there is was an error. Bit 13 of Slot 0
-- indicates a valid data response. If the transaction
-- was a read and it is not true, an error.
ac97_reg_error_i <= '1';
reg_if_state <= END_STATE;
else
reg_if_state <= RESPONSE_SLOT1;
end if;
else
-- Nothing else to do for writes
reg_if_state <= END_STATE;
end if;
end if;
-- Check the data in slot 1 and make sure it matches
-- the address sent
when RESPONSE_SLOT1 =>
if slot_No = 1 and slot_end = '1' then
if data_in(18 downto 12) /= register_addr then
ac97_reg_error_i <= '1';
reg_if_state <= END_STATE;
else
-- we need to get the data for read commands
reg_if_state <= RESPONSE_SLOT2;
end if;
end if;
when RESPONSE_SLOT2 =>
if slot_No = 2 and slot_end = '1' then
AC97_Reg_Read_Data <= data_in(19 downto 4);
AC97_Reg_Read_Data_Valid <= '1';
reg_if_state <= END_STATE;
end if;
when END_STATE =>
ac97_reg_busy_i <= '0';
reg_if_state <= IDLE;
when others => NULL;
end case;
end if;
end process register_if_PROCESS;
AC97_Reg_Busy <= ac97_reg_busy_i;
AC97_Reg_Error <= ac97_reg_error_i;
with reg_if_state select
debug(0 to 2) <= "000" when IDLE,
"001" when WAIT_FOR_NEW_FRAME,
"010" when SEND_REQUEST_FRAME,
"011" when RESPONSE_SLOT0,
"100" when RESPONSE_SLOT1,
"101" when RESPONSE_SLOT2,
"110" when END_STATE,
"000" when others;
debug(3 to 15) <= (others => '0');
-- This signal indicates that we are sending a request command
-- and that the address send to the codec is valid
valid_Control_Addr <= '1' when reg_if_state = WAIT_FOR_NEW_FRAME
else '0';
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Output Section
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Setup slot0 data at start of frame
--
-- Slot 0 is the TAG slot. The bits of this slot are defined as
-- follows:
-- bit 15: Valid frame
-- bit 14: valid control address (slot 1)
-- bit 13: valid control data (slot 2)
-- bit 12: valid PCM playback data Left (slot 3)
-- bit 11: valid PCM playback data Right (slot 4)
-- bot 10-2: ignored - fill with zeros
-- bit 1-0: 2-bit codec ID (assigned to '00' for primary)
--
-- The slot 0 signals are created directly from the inputs
-- of the module rather than using the "registered" versions
-- (i.e. ac97_reg_write instead of ac97_reag_write_i). The
-- slot0 signal is latched on the clock edge following
-- the frame signal into the shift register signal "data_out".
--
-----------------------------------------------------------------------------
-- temporary
valid_Frame <= valid_Control_Addr or
pcm_playback_left_valid or
pcm_playback_right_valid;
slot0(15) <= valid_Frame;
slot0(14) <= valid_Control_Addr;
slot0(13) <= register_write_cmd; -- valid data only during write
slot0(12) <= PCM_Playback_Left_Valid;
slot0(11) <= PCM_Playback_Right_Valid;
slot0(10 downto 2) <= "000000000";
slot0(1 downto 0) <= "00";
-----------------------------------------------------------------------------
-- Slot 1
--
-- Slot 1 is the Command Address:
-- Bit 19: Read/Write (1=read,0=write)
-- Bit 18-12: Control register index/address
-- Bit 11:0 reserved (stuff with 0)
-----------------------------------------------------------------------------
slot1(19) <= not register_write_cmd;
slot1(18 downto 12) <= register_addr;
slot1(11 downto 0) <= (others => '0');
-----------------------------------------------------------------------------
-- Slot 2
--
-- Slot 2 is the Command Data Port:
-- Bit 19-4: Control register write data
-- Bit 3-0: reserved (stuff with 0)
-----------------------------------------------------------------------------
slot2(19 downto 4) <= register_data;
slot2( 3 downto 0) <= (others => '0');
-----------------------------------------------------------------------------
-- Setup slot3 data (PCM play left)
-----------------------------------------------------------------------------
process (PCM_Playback_Left) is
begin
slot3((20 - C_PCM_DATA_WIDTH-1) downto 0) <= (others => '0');
slot3(19 downto (20 - C_PCM_DATA_WIDTH)) <= PCM_Playback_Left;
end process;
-----------------------------------------------------------------------------
-- Setup slot4 data (PCM play right)
-----------------------------------------------------------------------------
process (PCM_Playback_Right) is
begin
slot4((20 - C_PCM_DATA_WIDTH-1) downto 0) <= (others => '0');
slot4(19 downto (20 - C_PCM_DATA_WIDTH)) <= PCM_Playback_Right;
end process;
-----------------------------------------------------------------------------
-- Output data multiplexer for AC97_SData_Out signal
--
-- Choose the appropriate data to send out the shift register
-- (new_data_out)
-----------------------------------------------------------------------------
process (last_frame_cycle, slot_end, slot_No, slot0,
slot1, slot2, slot3, slot4) is
begin -- process
new_data_out <= (others => '0');
if (last_frame_cycle = '1') then
new_data_out(19 downto 4) <= slot0;
elsif (slot_end = '1') then
case slot_No is
when 0 => new_data_out(slot1'range) <= slot1;
when 1 => new_data_out(slot2'range) <= slot2;
when 2 => new_data_out <= slot3;
when 3 => new_data_out <= slot4;
when others => null;
end case;
end if;
end process;
-----------------------------------------------------------------------------
-- AC97 data out shift register
-----------------------------------------------------------------------------
Data_Out_Handle : process (AC97_Bit_Clk) is
begin -- process Data_Out_Handle
if reset = '1' then
data_out <= (others => '0');
elsif AC97_Bit_Clk'event and AC97_Bit_Clk = '1' then -- rising clock edge
if (last_frame_cycle = '1') or (slot_end = '1') then
data_out <= New_Data_Out;
else
data_out(19 downto 0) <= data_out(18 downto 0) & '0';
end if;
end if;
end process Data_Out_Handle;
AC97_SData_Out <= data_out(19);
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Input Section
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- AC97 data in shift register
-----------------------------------------------------------------------------
Shifting_Data_Coming_Back : process (AC97_Bit_Clk) is
begin -- process Shifting_Data_Coming_Back
if AC97_Bit_Clk'event and AC97_Bit_Clk = '0' then -- falling clock edge
data_in(19 downto 0) <= data_in(18 downto 0) & AC97_SData_In;
end if;
end process Shifting_Data_Coming_Back;
-----------------------------------------------------------------------------
-- Get slot 0 data (TAG - which slots are valid)
-----------------------------------------------------------------------------
process (AC97_Bit_Clk) is
begin
if AC97_Bit_Clk'event and AC97_Bit_Clk = '1' then -- rising clock edge
if (slot_no = 0 and slot_end = '1') then
codec_rdy_i <= data_in(15);
-- data_in(14) and data(13) are used directly in the reg_if
-- state machine
--return_status_address_valid <= data_in(14);
-- return_status_data_valid <= data_in(13);
record_pcm_left_valid <= data_in(12);
record_pcm_right_valid <= data_in(11);
end if;
end if;
end process;
PCM_Record_Left_Valid <= record_pcm_left_valid and last_frame_cycle;
PCM_Record_Right_Valid <= record_pcm_right_valid and last_frame_cycle;
codec_rdy <= codec_rdy_i;
-----------------------------------------------------------------------------
-- Get slot 1 PCM request bit
-----------------------------------------------------------------------------
process (AC97_Bit_Clk) is
begin
if AC97_Bit_Clk'event and AC97_Bit_Clk = '1' then
if (slot_end = '1' and slot_No = 1 ) then
accept_pcm_left <= not data_in(11);
accept_pcm_right <= not data_in(10);
end if;
end if;
end process;
PCM_Playback_Left_Accept <= accept_pcm_left and last_frame_cycle;
PCM_Playback_Right_Accept <= accept_pcm_right and last_frame_cycle;
-----------------------------------------------------------------------------
-- Get slot 3 and 4 data
-----------------------------------------------------------------------------
Get_Record_Data : process (AC97_Bit_Clk) is
-- synthesis translate_off
variable my_line : LINE;
-- synthesis translate_on
begin -- process Get_Record_Data
if AC97_Bit_Clk'event and AC97_Bit_Clk = '1' then -- rising clock edge
if (slot_end = '1' and slot_No = 3 ) then
PCM_Record_Left_i <= data_in(19 downto (20 - C_PCM_DATA_WIDTH));
-- synthesis translate_off
write(my_line, string'("AC97 Core: Received Left Value "));
write(my_line, bit_vector'( To_bitvector(PCM_Record_Left_i) ));
writeline(output, my_line);
-- synthesis translate_on
elsif (slot_end = '1' and slot_No = 4 ) then
PCM_Record_Right_i <= data_in(19 downto (20 - C_PCM_DATA_WIDTH));
-- synthesis translate_off
write(my_line, string'("AC97 Core: Received Right Value "));
write(my_line, bit_vector'( To_bitvector(PCM_Record_Right_i) ));
writeline(output, my_line);
-- synthesis translate_on
end if;
end if;
end process Get_Record_Data;
PCM_Record_Left <= PCM_Record_Left_i;
PCM_Record_Right <= PCM_Record_Right_i;
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
end architecture IMP;
|
-------------------------------------------------------------------------------
-- ac97_core.vhd
-------------------------------------------------------------------------------
--
-- Mike Wirthlin
--
-------------------------------------------------------------------------------
-- Filename: ac97_acore.vhd
--
-- Description: Provides a simple synchronous interface to a
-- AC97 codec. This was designed for the National
-- LM4549A and only supports slots 0-4.
-- This interface does not have any data buffering.
--
-- The interface to the AC97 is straightforward.
-- To transfer playback data, this interface will
-- sample the playback data and control signals
-- when the PCM_Playback_X_Accept signals are asserted.
-- This sample will
-- be sent to the codec during the next frame. The Record (
-- input) data is provided as an ouptput and is valid when
-- new_frame is asserted.
--
-- This core supports the full 20-bit PCM sample size. The
-- actual size of the PCM can be modified to a lower value for
-- easier interfacing using the C_PCM_DATA_WIDTH generic. This
-- core will stuff the remaining lsb bits with '0' if a value
-- lower than 20 is used.
--
-- This core is synchronous to the AC97_Bit_Clk and all
-- signals interfacing to this core should be synchronized to
-- this clock.
--
-- AC97 Register Interface
--
-- This core provides a simple interface to the AC97 codec registers. To write
-- a new value to the register, drive the AC97_Reg_Addr and
-- AC97_Reg_Write_Data input signals and assert the AC97_Reg_Write_Strobe
-- signal. To read a register value, drive the AC97_Reg_Addr and assert
-- the AC97_Reg_Read_Strobe signal. Once either strobe has been asserted, the
-- register interface state machine will process the request to the CODEC and
-- assert the AC97_Reg_Busy signal. The strobe control signals will be ignored
-- while the state machine is busy (the AC97 only supports one read or write
-- transaction at a time).
--
-- When the transaction is complete, the state machine will respond as
-- follows: first, the AC97_Reg_Busy signal will be deasserted indicating that
-- the transaction is complete and that the interface is ready to handle
-- another interface. If there was an error with the response (i.e. the AC97
-- codec did not respond properly to the request), the AC97_Reg_Error signal
-- will be asserted. This signal will remain asserted until a new register
-- transfer has been initiated.
--
-- On the successful completion of a register read operation, the
-- AC97_Reg_Read_Data_Valid signal will be asserted to validate the data
-- read from the AC97 controller. This signal will remain asserted until a new
-- register transaction is initiated.
--
--
-- This core will produce valid data on the AC97_SData_Out signal
-- during the following slots:
--
-- Slot 0: Tag Phase (indicates valid slots in packet)
-- Slot 1: Read/Write, Control Address
-- Slot 2: Command Data
-- Slot 3: PCM Left
-- Slot 4: PCM Right
--
-- This core will recognize valid data on the AC97_SData_In signal
-- during the following slots:
--
-- Slot 0: Codec/Slot Status Bits
-- Slot 1: Status Address / Slot Request
-- Slot 2: Status Data
-- Slot 3: PCM Record Left
-- Slot 4: PCM Record Righ
--
-- To Do:
-- - signal to validate recorded data
-- - signal to "request" playback data
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- - ac97_core
-- - ac97_timing
--
-------------------------------------------------------------------------------
-- Author: Mike Wirthlin
--
-- History:
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use std.TextIO.all;
library opb_ac97_v2_00_a;
use opb_ac97_v2_00_a.all;
-------------------------------------------------------------------------------
--
-- Genearics Summary
-- C_PLAYBACK: Enable playback logic. Disable to simplify circuit
-- C_RECORD: Enable record logic. Disable to simplify circuit
-- C_PCM_DATA_WIDTH:
-- AC97 specifies a 20-bit data word. HOwever, many codecs don't
-- support the full resolution (The LM4549 only supports 18). This
-- value indicates the number of data bits that will be sent/received
-- from the CODEC. Zeros will be inserted for least-significant digits.
--
-- Signal Summary
--
-- AC97_Bit_Clk:
-- Input clock generated by the AC97 Codec
-- AC97_Sync:
-- Frame synchronization signal. Generated by ac97_timing module.
-- AC97_SData_Out:
-- Serial data out. Transitions on the rising edge of bit_clk. Is
-- sampled by the CODEC on the falling edge
-- AC97_SData_In:
-- Serial data in. Transitions on the rising edge of bit_clk. Is
-- sampled by the this module on the falling edge.
-- AC97_SData_In:
-- CODEC_RDY:
-- This signal is generated by each frame from the AC97
-- Codec. It arrives each frame as the first bit of Slot 1.
-------------------------------------------------------------------------------
entity ac97_core is
generic (
C_PCM_DATA_WIDTH : integer := 16
);
port (
Reset : in std_logic;
-- signals attaching directly to AC97 codec
AC97_Bit_Clk : in std_logic;
AC97_Sync : out std_logic;
AC97_SData_Out : out std_logic;
AC97_SData_In : in std_logic;
-- AC97 register interface
AC97_Reg_Addr : in std_logic_vector(0 to 6);
AC97_Reg_Write_Data : in std_logic_vector(0 to 15);
AC97_Reg_Read_Data : out std_logic_vector(0 to 15);
AC97_Reg_Read_Strobe : in std_logic; -- initiates a "read" command
AC97_Reg_Write_Strobe : in std_logic; -- initiates a "write" command
AC97_Reg_Busy : out std_logic;
AC97_Reg_Error : out std_logic;
AC97_Reg_Read_Data_Valid : out std_logic;
-- Playback signal interface
PCM_Playback_Left: in std_logic_vector(0 to C_PCM_DATA_WIDTH-1);
PCM_Playback_Right: in std_logic_vector(0 to C_PCM_DATA_WIDTH-1);
PCM_Playback_Left_Valid: in std_logic;
PCM_Playback_Right_Valid: in std_logic;
PCM_Playback_Left_Accept: out std_logic;
PCM_Playback_Right_Accept: out std_logic;
-- Record signal interface
PCM_Record_Left: out std_logic_vector(0 to C_PCM_DATA_WIDTH-1);
PCM_Record_Right: out std_logic_vector(0 to C_PCM_DATA_WIDTH-1);
PCM_Record_Left_Valid: out std_logic;
PCM_Record_Right_Valid: out std_logic;
DEBUG : out std_logic_vector(0 to 15);
--
CODEC_RDY : out std_logic
);
end entity ac97_core;
library unisim;
use unisim.all;
architecture IMP of ac97_core is
component ac97_timing is
port (
Bit_Clk : in std_logic;
Reset : in std_logic;
Sync : out std_logic;
Bit_Num : out natural range 0 to 19;
Slot_Num : out natural range 0 to 12;
Slot_End : out std_logic;
Frame_End : out std_logic
);
end component ac97_timing;
signal last_frame_cycle : std_logic;
signal sync_i : std_logic;
signal slot_end : std_logic;
signal slot_No : natural range 0 to 12;
--signal bit_No : natural range 0 to 19;
-- register IF signals
type reg_if_states is (IDLE, WAIT_FOR_NEW_FRAME, SEND_REQUEST_FRAME,
RESPONSE_SLOT0, RESPONSE_SLOT1, RESPONSE_SLOT2,
END_STATE);
signal reg_if_state : reg_if_states := IDLE;
signal register_addr : std_logic_vector(0 to 6) := (others => '0');
signal register_data : std_logic_vector(0 to 15) := (others => '0');
signal register_write_cmd : std_logic := '0';
signal ac97_reg_error_i, ac97_reg_busy_i : std_logic := '0';
signal valid_Frame : std_logic;
signal valid_Control_Addr : std_logic;
-- Slot 0 in signals
signal record_pcm_left_valid : std_logic;
signal record_pcm_right_valid : std_logic;
--signal return_status_address_valid : std_logic;
--signal return_status_data_valid : std_logic;
signal accept_pcm_left : std_logic;
signal accept_pcm_right : std_logic;
signal new_data_out : std_logic_vector(19 downto 0) := (others => '0');
signal data_out : std_logic_vector(19 downto 0) := (others => '0');
signal data_in : std_logic_vector(19 downto 0);
signal slot0 : std_logic_vector(15 downto 0);
signal slot1 : std_logic_vector(19 downto 0);
signal slot2 : std_logic_vector(19 downto 0);
signal slot3 : std_logic_vector(19 downto 0) := (others => '0');
signal slot4 : std_logic_vector(19 downto 0) := (others => '0');
signal codec_rdy_i : std_logic := '0';
signal PCM_Record_Left_i: std_logic_vector(0 to C_PCM_DATA_WIDTH-1);
signal PCM_Record_Right_i: std_logic_vector(0 to C_PCM_DATA_WIDTH-1);
begin -- architecture IMP
-----------------------------------------------------------------------------
-- AC97 Timing Module & Interface signals
-----------------------------------------------------------------------------
ac97_timing_I_1 : ac97_timing
port map (
Bit_Clk => AC97_Bit_Clk,
Reset => Reset,
Sync => sync_i,
Bit_Num => open,
Slot_Num => slot_No,
Slot_End => slot_end,
Frame_End => last_frame_cycle
);
AC97_Sync <= sync_i;
-----------------------------------------------------------------------------
-- AC97 Register Interface
-----------------------------------------------------------------------------
-- Register state machine
register_if_PROCESS : process (AC97_Bit_Clk) is
begin
if RESET = '1' then
reg_if_state <= IDLE;
ac97_reg_busy_i <= '0';
ac97_reg_error_i <= '0';
AC97_Reg_Read_Data_Valid <= '0';
elsif AC97_Bit_Clk'event and AC97_Bit_Clk = '1' then
case reg_if_state is
-- Wait for a register transfer strobe to occur.
when IDLE =>
if (AC97_Reg_Read_Strobe = '1' or AC97_Reg_Write_Strobe = '1')
and codec_rdy_i = '1' then
reg_if_state <= WAIT_FOR_NEW_FRAME;
ac97_reg_busy_i <= '1';
ac97_reg_error_i <= '0';
AC97_Reg_Read_Data_Valid <= '0';
register_addr <= AC97_Reg_Addr;
if AC97_Reg_Write_Strobe = '1' then
register_data <= AC97_Reg_Write_Data;
register_write_cmd <= '1';
else
register_write_cmd <= '0';
end if;
end if;
-- Wait for the end of the current frame. During the last cycle of
-- this state (last_frame_cycle = 1), all the signals are
-- latched into slot 0 and a valid request is on its way out.
when WAIT_FOR_NEW_FRAME =>
if last_frame_cycle = '1' then
reg_if_state <= SEND_REQUEST_FRAME;
end if;
-- Wait for the request to be completely sent to the codec.
when SEND_REQUEST_FRAME =>
if last_frame_cycle = '1' then
reg_if_state <= RESPONSE_SLOT0;
end if;
-- Wait for the response in slot 0 and make sure the
-- appropriate response bits are set
when RESPONSE_SLOT0 =>
if slot_No = 0 and slot_end = '1' then
if register_write_cmd = '0' then
if (data_in(14) /= '1' or data_in(13) /= '1') then
-- Bit 14 of Slot 0 indicates a valid slot 1 data
-- (echo the requested address). If this is not a
-- '1' then there is was an error. Bit 13 of Slot 0
-- indicates a valid data response. If the transaction
-- was a read and it is not true, an error.
ac97_reg_error_i <= '1';
reg_if_state <= END_STATE;
else
reg_if_state <= RESPONSE_SLOT1;
end if;
else
-- Nothing else to do for writes
reg_if_state <= END_STATE;
end if;
end if;
-- Check the data in slot 1 and make sure it matches
-- the address sent
when RESPONSE_SLOT1 =>
if slot_No = 1 and slot_end = '1' then
if data_in(18 downto 12) /= register_addr then
ac97_reg_error_i <= '1';
reg_if_state <= END_STATE;
else
-- we need to get the data for read commands
reg_if_state <= RESPONSE_SLOT2;
end if;
end if;
when RESPONSE_SLOT2 =>
if slot_No = 2 and slot_end = '1' then
AC97_Reg_Read_Data <= data_in(19 downto 4);
AC97_Reg_Read_Data_Valid <= '1';
reg_if_state <= END_STATE;
end if;
when END_STATE =>
ac97_reg_busy_i <= '0';
reg_if_state <= IDLE;
when others => NULL;
end case;
end if;
end process register_if_PROCESS;
AC97_Reg_Busy <= ac97_reg_busy_i;
AC97_Reg_Error <= ac97_reg_error_i;
with reg_if_state select
debug(0 to 2) <= "000" when IDLE,
"001" when WAIT_FOR_NEW_FRAME,
"010" when SEND_REQUEST_FRAME,
"011" when RESPONSE_SLOT0,
"100" when RESPONSE_SLOT1,
"101" when RESPONSE_SLOT2,
"110" when END_STATE,
"000" when others;
debug(3 to 15) <= (others => '0');
-- This signal indicates that we are sending a request command
-- and that the address send to the codec is valid
valid_Control_Addr <= '1' when reg_if_state = WAIT_FOR_NEW_FRAME
else '0';
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Output Section
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Setup slot0 data at start of frame
--
-- Slot 0 is the TAG slot. The bits of this slot are defined as
-- follows:
-- bit 15: Valid frame
-- bit 14: valid control address (slot 1)
-- bit 13: valid control data (slot 2)
-- bit 12: valid PCM playback data Left (slot 3)
-- bit 11: valid PCM playback data Right (slot 4)
-- bot 10-2: ignored - fill with zeros
-- bit 1-0: 2-bit codec ID (assigned to '00' for primary)
--
-- The slot 0 signals are created directly from the inputs
-- of the module rather than using the "registered" versions
-- (i.e. ac97_reg_write instead of ac97_reag_write_i). The
-- slot0 signal is latched on the clock edge following
-- the frame signal into the shift register signal "data_out".
--
-----------------------------------------------------------------------------
-- temporary
valid_Frame <= valid_Control_Addr or
pcm_playback_left_valid or
pcm_playback_right_valid;
slot0(15) <= valid_Frame;
slot0(14) <= valid_Control_Addr;
slot0(13) <= register_write_cmd; -- valid data only during write
slot0(12) <= PCM_Playback_Left_Valid;
slot0(11) <= PCM_Playback_Right_Valid;
slot0(10 downto 2) <= "000000000";
slot0(1 downto 0) <= "00";
-----------------------------------------------------------------------------
-- Slot 1
--
-- Slot 1 is the Command Address:
-- Bit 19: Read/Write (1=read,0=write)
-- Bit 18-12: Control register index/address
-- Bit 11:0 reserved (stuff with 0)
-----------------------------------------------------------------------------
slot1(19) <= not register_write_cmd;
slot1(18 downto 12) <= register_addr;
slot1(11 downto 0) <= (others => '0');
-----------------------------------------------------------------------------
-- Slot 2
--
-- Slot 2 is the Command Data Port:
-- Bit 19-4: Control register write data
-- Bit 3-0: reserved (stuff with 0)
-----------------------------------------------------------------------------
slot2(19 downto 4) <= register_data;
slot2( 3 downto 0) <= (others => '0');
-----------------------------------------------------------------------------
-- Setup slot3 data (PCM play left)
-----------------------------------------------------------------------------
process (PCM_Playback_Left) is
begin
slot3((20 - C_PCM_DATA_WIDTH-1) downto 0) <= (others => '0');
slot3(19 downto (20 - C_PCM_DATA_WIDTH)) <= PCM_Playback_Left;
end process;
-----------------------------------------------------------------------------
-- Setup slot4 data (PCM play right)
-----------------------------------------------------------------------------
process (PCM_Playback_Right) is
begin
slot4((20 - C_PCM_DATA_WIDTH-1) downto 0) <= (others => '0');
slot4(19 downto (20 - C_PCM_DATA_WIDTH)) <= PCM_Playback_Right;
end process;
-----------------------------------------------------------------------------
-- Output data multiplexer for AC97_SData_Out signal
--
-- Choose the appropriate data to send out the shift register
-- (new_data_out)
-----------------------------------------------------------------------------
process (last_frame_cycle, slot_end, slot_No, slot0,
slot1, slot2, slot3, slot4) is
begin -- process
new_data_out <= (others => '0');
if (last_frame_cycle = '1') then
new_data_out(19 downto 4) <= slot0;
elsif (slot_end = '1') then
case slot_No is
when 0 => new_data_out(slot1'range) <= slot1;
when 1 => new_data_out(slot2'range) <= slot2;
when 2 => new_data_out <= slot3;
when 3 => new_data_out <= slot4;
when others => null;
end case;
end if;
end process;
-----------------------------------------------------------------------------
-- AC97 data out shift register
-----------------------------------------------------------------------------
Data_Out_Handle : process (AC97_Bit_Clk) is
begin -- process Data_Out_Handle
if reset = '1' then
data_out <= (others => '0');
elsif AC97_Bit_Clk'event and AC97_Bit_Clk = '1' then -- rising clock edge
if (last_frame_cycle = '1') or (slot_end = '1') then
data_out <= New_Data_Out;
else
data_out(19 downto 0) <= data_out(18 downto 0) & '0';
end if;
end if;
end process Data_Out_Handle;
AC97_SData_Out <= data_out(19);
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Input Section
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- AC97 data in shift register
-----------------------------------------------------------------------------
Shifting_Data_Coming_Back : process (AC97_Bit_Clk) is
begin -- process Shifting_Data_Coming_Back
if AC97_Bit_Clk'event and AC97_Bit_Clk = '0' then -- falling clock edge
data_in(19 downto 0) <= data_in(18 downto 0) & AC97_SData_In;
end if;
end process Shifting_Data_Coming_Back;
-----------------------------------------------------------------------------
-- Get slot 0 data (TAG - which slots are valid)
-----------------------------------------------------------------------------
process (AC97_Bit_Clk) is
begin
if AC97_Bit_Clk'event and AC97_Bit_Clk = '1' then -- rising clock edge
if (slot_no = 0 and slot_end = '1') then
codec_rdy_i <= data_in(15);
-- data_in(14) and data(13) are used directly in the reg_if
-- state machine
--return_status_address_valid <= data_in(14);
-- return_status_data_valid <= data_in(13);
record_pcm_left_valid <= data_in(12);
record_pcm_right_valid <= data_in(11);
end if;
end if;
end process;
PCM_Record_Left_Valid <= record_pcm_left_valid and last_frame_cycle;
PCM_Record_Right_Valid <= record_pcm_right_valid and last_frame_cycle;
codec_rdy <= codec_rdy_i;
-----------------------------------------------------------------------------
-- Get slot 1 PCM request bit
-----------------------------------------------------------------------------
process (AC97_Bit_Clk) is
begin
if AC97_Bit_Clk'event and AC97_Bit_Clk = '1' then
if (slot_end = '1' and slot_No = 1 ) then
accept_pcm_left <= not data_in(11);
accept_pcm_right <= not data_in(10);
end if;
end if;
end process;
PCM_Playback_Left_Accept <= accept_pcm_left and last_frame_cycle;
PCM_Playback_Right_Accept <= accept_pcm_right and last_frame_cycle;
-----------------------------------------------------------------------------
-- Get slot 3 and 4 data
-----------------------------------------------------------------------------
Get_Record_Data : process (AC97_Bit_Clk) is
-- synthesis translate_off
variable my_line : LINE;
-- synthesis translate_on
begin -- process Get_Record_Data
if AC97_Bit_Clk'event and AC97_Bit_Clk = '1' then -- rising clock edge
if (slot_end = '1' and slot_No = 3 ) then
PCM_Record_Left_i <= data_in(19 downto (20 - C_PCM_DATA_WIDTH));
-- synthesis translate_off
write(my_line, string'("AC97 Core: Received Left Value "));
write(my_line, bit_vector'( To_bitvector(PCM_Record_Left_i) ));
writeline(output, my_line);
-- synthesis translate_on
elsif (slot_end = '1' and slot_No = 4 ) then
PCM_Record_Right_i <= data_in(19 downto (20 - C_PCM_DATA_WIDTH));
-- synthesis translate_off
write(my_line, string'("AC97 Core: Received Right Value "));
write(my_line, bit_vector'( To_bitvector(PCM_Record_Right_i) ));
writeline(output, my_line);
-- synthesis translate_on
end if;
end if;
end process Get_Record_Data;
PCM_Record_Left <= PCM_Record_Left_i;
PCM_Record_Right <= PCM_Record_Right_i;
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
end architecture IMP;
|
-------------------------------------------------------------------------------
-- ac97_core.vhd
-------------------------------------------------------------------------------
--
-- Mike Wirthlin
--
-------------------------------------------------------------------------------
-- Filename: ac97_acore.vhd
--
-- Description: Provides a simple synchronous interface to a
-- AC97 codec. This was designed for the National
-- LM4549A and only supports slots 0-4.
-- This interface does not have any data buffering.
--
-- The interface to the AC97 is straightforward.
-- To transfer playback data, this interface will
-- sample the playback data and control signals
-- when the PCM_Playback_X_Accept signals are asserted.
-- This sample will
-- be sent to the codec during the next frame. The Record (
-- input) data is provided as an ouptput and is valid when
-- new_frame is asserted.
--
-- This core supports the full 20-bit PCM sample size. The
-- actual size of the PCM can be modified to a lower value for
-- easier interfacing using the C_PCM_DATA_WIDTH generic. This
-- core will stuff the remaining lsb bits with '0' if a value
-- lower than 20 is used.
--
-- This core is synchronous to the AC97_Bit_Clk and all
-- signals interfacing to this core should be synchronized to
-- this clock.
--
-- AC97 Register Interface
--
-- This core provides a simple interface to the AC97 codec registers. To write
-- a new value to the register, drive the AC97_Reg_Addr and
-- AC97_Reg_Write_Data input signals and assert the AC97_Reg_Write_Strobe
-- signal. To read a register value, drive the AC97_Reg_Addr and assert
-- the AC97_Reg_Read_Strobe signal. Once either strobe has been asserted, the
-- register interface state machine will process the request to the CODEC and
-- assert the AC97_Reg_Busy signal. The strobe control signals will be ignored
-- while the state machine is busy (the AC97 only supports one read or write
-- transaction at a time).
--
-- When the transaction is complete, the state machine will respond as
-- follows: first, the AC97_Reg_Busy signal will be deasserted indicating that
-- the transaction is complete and that the interface is ready to handle
-- another interface. If there was an error with the response (i.e. the AC97
-- codec did not respond properly to the request), the AC97_Reg_Error signal
-- will be asserted. This signal will remain asserted until a new register
-- transfer has been initiated.
--
-- On the successful completion of a register read operation, the
-- AC97_Reg_Read_Data_Valid signal will be asserted to validate the data
-- read from the AC97 controller. This signal will remain asserted until a new
-- register transaction is initiated.
--
--
-- This core will produce valid data on the AC97_SData_Out signal
-- during the following slots:
--
-- Slot 0: Tag Phase (indicates valid slots in packet)
-- Slot 1: Read/Write, Control Address
-- Slot 2: Command Data
-- Slot 3: PCM Left
-- Slot 4: PCM Right
--
-- This core will recognize valid data on the AC97_SData_In signal
-- during the following slots:
--
-- Slot 0: Codec/Slot Status Bits
-- Slot 1: Status Address / Slot Request
-- Slot 2: Status Data
-- Slot 3: PCM Record Left
-- Slot 4: PCM Record Righ
--
-- To Do:
-- - signal to validate recorded data
-- - signal to "request" playback data
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- - ac97_core
-- - ac97_timing
--
-------------------------------------------------------------------------------
-- Author: Mike Wirthlin
--
-- History:
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use std.TextIO.all;
library opb_ac97_v2_00_a;
use opb_ac97_v2_00_a.all;
-------------------------------------------------------------------------------
--
-- Genearics Summary
-- C_PLAYBACK: Enable playback logic. Disable to simplify circuit
-- C_RECORD: Enable record logic. Disable to simplify circuit
-- C_PCM_DATA_WIDTH:
-- AC97 specifies a 20-bit data word. HOwever, many codecs don't
-- support the full resolution (The LM4549 only supports 18). This
-- value indicates the number of data bits that will be sent/received
-- from the CODEC. Zeros will be inserted for least-significant digits.
--
-- Signal Summary
--
-- AC97_Bit_Clk:
-- Input clock generated by the AC97 Codec
-- AC97_Sync:
-- Frame synchronization signal. Generated by ac97_timing module.
-- AC97_SData_Out:
-- Serial data out. Transitions on the rising edge of bit_clk. Is
-- sampled by the CODEC on the falling edge
-- AC97_SData_In:
-- Serial data in. Transitions on the rising edge of bit_clk. Is
-- sampled by the this module on the falling edge.
-- AC97_SData_In:
-- CODEC_RDY:
-- This signal is generated by each frame from the AC97
-- Codec. It arrives each frame as the first bit of Slot 1.
-------------------------------------------------------------------------------
entity ac97_core is
generic (
C_PCM_DATA_WIDTH : integer := 16
);
port (
Reset : in std_logic;
-- signals attaching directly to AC97 codec
AC97_Bit_Clk : in std_logic;
AC97_Sync : out std_logic;
AC97_SData_Out : out std_logic;
AC97_SData_In : in std_logic;
-- AC97 register interface
AC97_Reg_Addr : in std_logic_vector(0 to 6);
AC97_Reg_Write_Data : in std_logic_vector(0 to 15);
AC97_Reg_Read_Data : out std_logic_vector(0 to 15);
AC97_Reg_Read_Strobe : in std_logic; -- initiates a "read" command
AC97_Reg_Write_Strobe : in std_logic; -- initiates a "write" command
AC97_Reg_Busy : out std_logic;
AC97_Reg_Error : out std_logic;
AC97_Reg_Read_Data_Valid : out std_logic;
-- Playback signal interface
PCM_Playback_Left: in std_logic_vector(0 to C_PCM_DATA_WIDTH-1);
PCM_Playback_Right: in std_logic_vector(0 to C_PCM_DATA_WIDTH-1);
PCM_Playback_Left_Valid: in std_logic;
PCM_Playback_Right_Valid: in std_logic;
PCM_Playback_Left_Accept: out std_logic;
PCM_Playback_Right_Accept: out std_logic;
-- Record signal interface
PCM_Record_Left: out std_logic_vector(0 to C_PCM_DATA_WIDTH-1);
PCM_Record_Right: out std_logic_vector(0 to C_PCM_DATA_WIDTH-1);
PCM_Record_Left_Valid: out std_logic;
PCM_Record_Right_Valid: out std_logic;
DEBUG : out std_logic_vector(0 to 15);
--
CODEC_RDY : out std_logic
);
end entity ac97_core;
library unisim;
use unisim.all;
architecture IMP of ac97_core is
component ac97_timing is
port (
Bit_Clk : in std_logic;
Reset : in std_logic;
Sync : out std_logic;
Bit_Num : out natural range 0 to 19;
Slot_Num : out natural range 0 to 12;
Slot_End : out std_logic;
Frame_End : out std_logic
);
end component ac97_timing;
signal last_frame_cycle : std_logic;
signal sync_i : std_logic;
signal slot_end : std_logic;
signal slot_No : natural range 0 to 12;
--signal bit_No : natural range 0 to 19;
-- register IF signals
type reg_if_states is (IDLE, WAIT_FOR_NEW_FRAME, SEND_REQUEST_FRAME,
RESPONSE_SLOT0, RESPONSE_SLOT1, RESPONSE_SLOT2,
END_STATE);
signal reg_if_state : reg_if_states := IDLE;
signal register_addr : std_logic_vector(0 to 6) := (others => '0');
signal register_data : std_logic_vector(0 to 15) := (others => '0');
signal register_write_cmd : std_logic := '0';
signal ac97_reg_error_i, ac97_reg_busy_i : std_logic := '0';
signal valid_Frame : std_logic;
signal valid_Control_Addr : std_logic;
-- Slot 0 in signals
signal record_pcm_left_valid : std_logic;
signal record_pcm_right_valid : std_logic;
--signal return_status_address_valid : std_logic;
--signal return_status_data_valid : std_logic;
signal accept_pcm_left : std_logic;
signal accept_pcm_right : std_logic;
signal new_data_out : std_logic_vector(19 downto 0) := (others => '0');
signal data_out : std_logic_vector(19 downto 0) := (others => '0');
signal data_in : std_logic_vector(19 downto 0);
signal slot0 : std_logic_vector(15 downto 0);
signal slot1 : std_logic_vector(19 downto 0);
signal slot2 : std_logic_vector(19 downto 0);
signal slot3 : std_logic_vector(19 downto 0) := (others => '0');
signal slot4 : std_logic_vector(19 downto 0) := (others => '0');
signal codec_rdy_i : std_logic := '0';
signal PCM_Record_Left_i: std_logic_vector(0 to C_PCM_DATA_WIDTH-1);
signal PCM_Record_Right_i: std_logic_vector(0 to C_PCM_DATA_WIDTH-1);
begin -- architecture IMP
-----------------------------------------------------------------------------
-- AC97 Timing Module & Interface signals
-----------------------------------------------------------------------------
ac97_timing_I_1 : ac97_timing
port map (
Bit_Clk => AC97_Bit_Clk,
Reset => Reset,
Sync => sync_i,
Bit_Num => open,
Slot_Num => slot_No,
Slot_End => slot_end,
Frame_End => last_frame_cycle
);
AC97_Sync <= sync_i;
-----------------------------------------------------------------------------
-- AC97 Register Interface
-----------------------------------------------------------------------------
-- Register state machine
register_if_PROCESS : process (AC97_Bit_Clk) is
begin
if RESET = '1' then
reg_if_state <= IDLE;
ac97_reg_busy_i <= '0';
ac97_reg_error_i <= '0';
AC97_Reg_Read_Data_Valid <= '0';
elsif AC97_Bit_Clk'event and AC97_Bit_Clk = '1' then
case reg_if_state is
-- Wait for a register transfer strobe to occur.
when IDLE =>
if (AC97_Reg_Read_Strobe = '1' or AC97_Reg_Write_Strobe = '1')
and codec_rdy_i = '1' then
reg_if_state <= WAIT_FOR_NEW_FRAME;
ac97_reg_busy_i <= '1';
ac97_reg_error_i <= '0';
AC97_Reg_Read_Data_Valid <= '0';
register_addr <= AC97_Reg_Addr;
if AC97_Reg_Write_Strobe = '1' then
register_data <= AC97_Reg_Write_Data;
register_write_cmd <= '1';
else
register_write_cmd <= '0';
end if;
end if;
-- Wait for the end of the current frame. During the last cycle of
-- this state (last_frame_cycle = 1), all the signals are
-- latched into slot 0 and a valid request is on its way out.
when WAIT_FOR_NEW_FRAME =>
if last_frame_cycle = '1' then
reg_if_state <= SEND_REQUEST_FRAME;
end if;
-- Wait for the request to be completely sent to the codec.
when SEND_REQUEST_FRAME =>
if last_frame_cycle = '1' then
reg_if_state <= RESPONSE_SLOT0;
end if;
-- Wait for the response in slot 0 and make sure the
-- appropriate response bits are set
when RESPONSE_SLOT0 =>
if slot_No = 0 and slot_end = '1' then
if register_write_cmd = '0' then
if (data_in(14) /= '1' or data_in(13) /= '1') then
-- Bit 14 of Slot 0 indicates a valid slot 1 data
-- (echo the requested address). If this is not a
-- '1' then there is was an error. Bit 13 of Slot 0
-- indicates a valid data response. If the transaction
-- was a read and it is not true, an error.
ac97_reg_error_i <= '1';
reg_if_state <= END_STATE;
else
reg_if_state <= RESPONSE_SLOT1;
end if;
else
-- Nothing else to do for writes
reg_if_state <= END_STATE;
end if;
end if;
-- Check the data in slot 1 and make sure it matches
-- the address sent
when RESPONSE_SLOT1 =>
if slot_No = 1 and slot_end = '1' then
if data_in(18 downto 12) /= register_addr then
ac97_reg_error_i <= '1';
reg_if_state <= END_STATE;
else
-- we need to get the data for read commands
reg_if_state <= RESPONSE_SLOT2;
end if;
end if;
when RESPONSE_SLOT2 =>
if slot_No = 2 and slot_end = '1' then
AC97_Reg_Read_Data <= data_in(19 downto 4);
AC97_Reg_Read_Data_Valid <= '1';
reg_if_state <= END_STATE;
end if;
when END_STATE =>
ac97_reg_busy_i <= '0';
reg_if_state <= IDLE;
when others => NULL;
end case;
end if;
end process register_if_PROCESS;
AC97_Reg_Busy <= ac97_reg_busy_i;
AC97_Reg_Error <= ac97_reg_error_i;
with reg_if_state select
debug(0 to 2) <= "000" when IDLE,
"001" when WAIT_FOR_NEW_FRAME,
"010" when SEND_REQUEST_FRAME,
"011" when RESPONSE_SLOT0,
"100" when RESPONSE_SLOT1,
"101" when RESPONSE_SLOT2,
"110" when END_STATE,
"000" when others;
debug(3 to 15) <= (others => '0');
-- This signal indicates that we are sending a request command
-- and that the address send to the codec is valid
valid_Control_Addr <= '1' when reg_if_state = WAIT_FOR_NEW_FRAME
else '0';
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Output Section
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Setup slot0 data at start of frame
--
-- Slot 0 is the TAG slot. The bits of this slot are defined as
-- follows:
-- bit 15: Valid frame
-- bit 14: valid control address (slot 1)
-- bit 13: valid control data (slot 2)
-- bit 12: valid PCM playback data Left (slot 3)
-- bit 11: valid PCM playback data Right (slot 4)
-- bot 10-2: ignored - fill with zeros
-- bit 1-0: 2-bit codec ID (assigned to '00' for primary)
--
-- The slot 0 signals are created directly from the inputs
-- of the module rather than using the "registered" versions
-- (i.e. ac97_reg_write instead of ac97_reag_write_i). The
-- slot0 signal is latched on the clock edge following
-- the frame signal into the shift register signal "data_out".
--
-----------------------------------------------------------------------------
-- temporary
valid_Frame <= valid_Control_Addr or
pcm_playback_left_valid or
pcm_playback_right_valid;
slot0(15) <= valid_Frame;
slot0(14) <= valid_Control_Addr;
slot0(13) <= register_write_cmd; -- valid data only during write
slot0(12) <= PCM_Playback_Left_Valid;
slot0(11) <= PCM_Playback_Right_Valid;
slot0(10 downto 2) <= "000000000";
slot0(1 downto 0) <= "00";
-----------------------------------------------------------------------------
-- Slot 1
--
-- Slot 1 is the Command Address:
-- Bit 19: Read/Write (1=read,0=write)
-- Bit 18-12: Control register index/address
-- Bit 11:0 reserved (stuff with 0)
-----------------------------------------------------------------------------
slot1(19) <= not register_write_cmd;
slot1(18 downto 12) <= register_addr;
slot1(11 downto 0) <= (others => '0');
-----------------------------------------------------------------------------
-- Slot 2
--
-- Slot 2 is the Command Data Port:
-- Bit 19-4: Control register write data
-- Bit 3-0: reserved (stuff with 0)
-----------------------------------------------------------------------------
slot2(19 downto 4) <= register_data;
slot2( 3 downto 0) <= (others => '0');
-----------------------------------------------------------------------------
-- Setup slot3 data (PCM play left)
-----------------------------------------------------------------------------
process (PCM_Playback_Left) is
begin
slot3((20 - C_PCM_DATA_WIDTH-1) downto 0) <= (others => '0');
slot3(19 downto (20 - C_PCM_DATA_WIDTH)) <= PCM_Playback_Left;
end process;
-----------------------------------------------------------------------------
-- Setup slot4 data (PCM play right)
-----------------------------------------------------------------------------
process (PCM_Playback_Right) is
begin
slot4((20 - C_PCM_DATA_WIDTH-1) downto 0) <= (others => '0');
slot4(19 downto (20 - C_PCM_DATA_WIDTH)) <= PCM_Playback_Right;
end process;
-----------------------------------------------------------------------------
-- Output data multiplexer for AC97_SData_Out signal
--
-- Choose the appropriate data to send out the shift register
-- (new_data_out)
-----------------------------------------------------------------------------
process (last_frame_cycle, slot_end, slot_No, slot0,
slot1, slot2, slot3, slot4) is
begin -- process
new_data_out <= (others => '0');
if (last_frame_cycle = '1') then
new_data_out(19 downto 4) <= slot0;
elsif (slot_end = '1') then
case slot_No is
when 0 => new_data_out(slot1'range) <= slot1;
when 1 => new_data_out(slot2'range) <= slot2;
when 2 => new_data_out <= slot3;
when 3 => new_data_out <= slot4;
when others => null;
end case;
end if;
end process;
-----------------------------------------------------------------------------
-- AC97 data out shift register
-----------------------------------------------------------------------------
Data_Out_Handle : process (AC97_Bit_Clk) is
begin -- process Data_Out_Handle
if reset = '1' then
data_out <= (others => '0');
elsif AC97_Bit_Clk'event and AC97_Bit_Clk = '1' then -- rising clock edge
if (last_frame_cycle = '1') or (slot_end = '1') then
data_out <= New_Data_Out;
else
data_out(19 downto 0) <= data_out(18 downto 0) & '0';
end if;
end if;
end process Data_Out_Handle;
AC97_SData_Out <= data_out(19);
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Input Section
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- AC97 data in shift register
-----------------------------------------------------------------------------
Shifting_Data_Coming_Back : process (AC97_Bit_Clk) is
begin -- process Shifting_Data_Coming_Back
if AC97_Bit_Clk'event and AC97_Bit_Clk = '0' then -- falling clock edge
data_in(19 downto 0) <= data_in(18 downto 0) & AC97_SData_In;
end if;
end process Shifting_Data_Coming_Back;
-----------------------------------------------------------------------------
-- Get slot 0 data (TAG - which slots are valid)
-----------------------------------------------------------------------------
process (AC97_Bit_Clk) is
begin
if AC97_Bit_Clk'event and AC97_Bit_Clk = '1' then -- rising clock edge
if (slot_no = 0 and slot_end = '1') then
codec_rdy_i <= data_in(15);
-- data_in(14) and data(13) are used directly in the reg_if
-- state machine
--return_status_address_valid <= data_in(14);
-- return_status_data_valid <= data_in(13);
record_pcm_left_valid <= data_in(12);
record_pcm_right_valid <= data_in(11);
end if;
end if;
end process;
PCM_Record_Left_Valid <= record_pcm_left_valid and last_frame_cycle;
PCM_Record_Right_Valid <= record_pcm_right_valid and last_frame_cycle;
codec_rdy <= codec_rdy_i;
-----------------------------------------------------------------------------
-- Get slot 1 PCM request bit
-----------------------------------------------------------------------------
process (AC97_Bit_Clk) is
begin
if AC97_Bit_Clk'event and AC97_Bit_Clk = '1' then
if (slot_end = '1' and slot_No = 1 ) then
accept_pcm_left <= not data_in(11);
accept_pcm_right <= not data_in(10);
end if;
end if;
end process;
PCM_Playback_Left_Accept <= accept_pcm_left and last_frame_cycle;
PCM_Playback_Right_Accept <= accept_pcm_right and last_frame_cycle;
-----------------------------------------------------------------------------
-- Get slot 3 and 4 data
-----------------------------------------------------------------------------
Get_Record_Data : process (AC97_Bit_Clk) is
-- synthesis translate_off
variable my_line : LINE;
-- synthesis translate_on
begin -- process Get_Record_Data
if AC97_Bit_Clk'event and AC97_Bit_Clk = '1' then -- rising clock edge
if (slot_end = '1' and slot_No = 3 ) then
PCM_Record_Left_i <= data_in(19 downto (20 - C_PCM_DATA_WIDTH));
-- synthesis translate_off
write(my_line, string'("AC97 Core: Received Left Value "));
write(my_line, bit_vector'( To_bitvector(PCM_Record_Left_i) ));
writeline(output, my_line);
-- synthesis translate_on
elsif (slot_end = '1' and slot_No = 4 ) then
PCM_Record_Right_i <= data_in(19 downto (20 - C_PCM_DATA_WIDTH));
-- synthesis translate_off
write(my_line, string'("AC97 Core: Received Right Value "));
write(my_line, bit_vector'( To_bitvector(PCM_Record_Right_i) ));
writeline(output, my_line);
-- synthesis translate_on
end if;
end if;
end process Get_Record_Data;
PCM_Record_Left <= PCM_Record_Left_i;
PCM_Record_Right <= PCM_Record_Right_i;
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
end architecture IMP;
|
-------------------------------------------------------------------------------
-- ac97_core.vhd
-------------------------------------------------------------------------------
--
-- Mike Wirthlin
--
-------------------------------------------------------------------------------
-- Filename: ac97_acore.vhd
--
-- Description: Provides a simple synchronous interface to a
-- AC97 codec. This was designed for the National
-- LM4549A and only supports slots 0-4.
-- This interface does not have any data buffering.
--
-- The interface to the AC97 is straightforward.
-- To transfer playback data, this interface will
-- sample the playback data and control signals
-- when the PCM_Playback_X_Accept signals are asserted.
-- This sample will
-- be sent to the codec during the next frame. The Record (
-- input) data is provided as an ouptput and is valid when
-- new_frame is asserted.
--
-- This core supports the full 20-bit PCM sample size. The
-- actual size of the PCM can be modified to a lower value for
-- easier interfacing using the C_PCM_DATA_WIDTH generic. This
-- core will stuff the remaining lsb bits with '0' if a value
-- lower than 20 is used.
--
-- This core is synchronous to the AC97_Bit_Clk and all
-- signals interfacing to this core should be synchronized to
-- this clock.
--
-- AC97 Register Interface
--
-- This core provides a simple interface to the AC97 codec registers. To write
-- a new value to the register, drive the AC97_Reg_Addr and
-- AC97_Reg_Write_Data input signals and assert the AC97_Reg_Write_Strobe
-- signal. To read a register value, drive the AC97_Reg_Addr and assert
-- the AC97_Reg_Read_Strobe signal. Once either strobe has been asserted, the
-- register interface state machine will process the request to the CODEC and
-- assert the AC97_Reg_Busy signal. The strobe control signals will be ignored
-- while the state machine is busy (the AC97 only supports one read or write
-- transaction at a time).
--
-- When the transaction is complete, the state machine will respond as
-- follows: first, the AC97_Reg_Busy signal will be deasserted indicating that
-- the transaction is complete and that the interface is ready to handle
-- another interface. If there was an error with the response (i.e. the AC97
-- codec did not respond properly to the request), the AC97_Reg_Error signal
-- will be asserted. This signal will remain asserted until a new register
-- transfer has been initiated.
--
-- On the successful completion of a register read operation, the
-- AC97_Reg_Read_Data_Valid signal will be asserted to validate the data
-- read from the AC97 controller. This signal will remain asserted until a new
-- register transaction is initiated.
--
--
-- This core will produce valid data on the AC97_SData_Out signal
-- during the following slots:
--
-- Slot 0: Tag Phase (indicates valid slots in packet)
-- Slot 1: Read/Write, Control Address
-- Slot 2: Command Data
-- Slot 3: PCM Left
-- Slot 4: PCM Right
--
-- This core will recognize valid data on the AC97_SData_In signal
-- during the following slots:
--
-- Slot 0: Codec/Slot Status Bits
-- Slot 1: Status Address / Slot Request
-- Slot 2: Status Data
-- Slot 3: PCM Record Left
-- Slot 4: PCM Record Righ
--
-- To Do:
-- - signal to validate recorded data
-- - signal to "request" playback data
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- - ac97_core
-- - ac97_timing
--
-------------------------------------------------------------------------------
-- Author: Mike Wirthlin
--
-- History:
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use std.TextIO.all;
library opb_ac97_v2_00_a;
use opb_ac97_v2_00_a.all;
-------------------------------------------------------------------------------
--
-- Genearics Summary
-- C_PLAYBACK: Enable playback logic. Disable to simplify circuit
-- C_RECORD: Enable record logic. Disable to simplify circuit
-- C_PCM_DATA_WIDTH:
-- AC97 specifies a 20-bit data word. HOwever, many codecs don't
-- support the full resolution (The LM4549 only supports 18). This
-- value indicates the number of data bits that will be sent/received
-- from the CODEC. Zeros will be inserted for least-significant digits.
--
-- Signal Summary
--
-- AC97_Bit_Clk:
-- Input clock generated by the AC97 Codec
-- AC97_Sync:
-- Frame synchronization signal. Generated by ac97_timing module.
-- AC97_SData_Out:
-- Serial data out. Transitions on the rising edge of bit_clk. Is
-- sampled by the CODEC on the falling edge
-- AC97_SData_In:
-- Serial data in. Transitions on the rising edge of bit_clk. Is
-- sampled by the this module on the falling edge.
-- AC97_SData_In:
-- CODEC_RDY:
-- This signal is generated by each frame from the AC97
-- Codec. It arrives each frame as the first bit of Slot 1.
-------------------------------------------------------------------------------
entity ac97_core is
generic (
C_PCM_DATA_WIDTH : integer := 16
);
port (
Reset : in std_logic;
-- signals attaching directly to AC97 codec
AC97_Bit_Clk : in std_logic;
AC97_Sync : out std_logic;
AC97_SData_Out : out std_logic;
AC97_SData_In : in std_logic;
-- AC97 register interface
AC97_Reg_Addr : in std_logic_vector(0 to 6);
AC97_Reg_Write_Data : in std_logic_vector(0 to 15);
AC97_Reg_Read_Data : out std_logic_vector(0 to 15);
AC97_Reg_Read_Strobe : in std_logic; -- initiates a "read" command
AC97_Reg_Write_Strobe : in std_logic; -- initiates a "write" command
AC97_Reg_Busy : out std_logic;
AC97_Reg_Error : out std_logic;
AC97_Reg_Read_Data_Valid : out std_logic;
-- Playback signal interface
PCM_Playback_Left: in std_logic_vector(0 to C_PCM_DATA_WIDTH-1);
PCM_Playback_Right: in std_logic_vector(0 to C_PCM_DATA_WIDTH-1);
PCM_Playback_Left_Valid: in std_logic;
PCM_Playback_Right_Valid: in std_logic;
PCM_Playback_Left_Accept: out std_logic;
PCM_Playback_Right_Accept: out std_logic;
-- Record signal interface
PCM_Record_Left: out std_logic_vector(0 to C_PCM_DATA_WIDTH-1);
PCM_Record_Right: out std_logic_vector(0 to C_PCM_DATA_WIDTH-1);
PCM_Record_Left_Valid: out std_logic;
PCM_Record_Right_Valid: out std_logic;
DEBUG : out std_logic_vector(0 to 15);
--
CODEC_RDY : out std_logic
);
end entity ac97_core;
library unisim;
use unisim.all;
architecture IMP of ac97_core is
component ac97_timing is
port (
Bit_Clk : in std_logic;
Reset : in std_logic;
Sync : out std_logic;
Bit_Num : out natural range 0 to 19;
Slot_Num : out natural range 0 to 12;
Slot_End : out std_logic;
Frame_End : out std_logic
);
end component ac97_timing;
signal last_frame_cycle : std_logic;
signal sync_i : std_logic;
signal slot_end : std_logic;
signal slot_No : natural range 0 to 12;
--signal bit_No : natural range 0 to 19;
-- register IF signals
type reg_if_states is (IDLE, WAIT_FOR_NEW_FRAME, SEND_REQUEST_FRAME,
RESPONSE_SLOT0, RESPONSE_SLOT1, RESPONSE_SLOT2,
END_STATE);
signal reg_if_state : reg_if_states := IDLE;
signal register_addr : std_logic_vector(0 to 6) := (others => '0');
signal register_data : std_logic_vector(0 to 15) := (others => '0');
signal register_write_cmd : std_logic := '0';
signal ac97_reg_error_i, ac97_reg_busy_i : std_logic := '0';
signal valid_Frame : std_logic;
signal valid_Control_Addr : std_logic;
-- Slot 0 in signals
signal record_pcm_left_valid : std_logic;
signal record_pcm_right_valid : std_logic;
--signal return_status_address_valid : std_logic;
--signal return_status_data_valid : std_logic;
signal accept_pcm_left : std_logic;
signal accept_pcm_right : std_logic;
signal new_data_out : std_logic_vector(19 downto 0) := (others => '0');
signal data_out : std_logic_vector(19 downto 0) := (others => '0');
signal data_in : std_logic_vector(19 downto 0);
signal slot0 : std_logic_vector(15 downto 0);
signal slot1 : std_logic_vector(19 downto 0);
signal slot2 : std_logic_vector(19 downto 0);
signal slot3 : std_logic_vector(19 downto 0) := (others => '0');
signal slot4 : std_logic_vector(19 downto 0) := (others => '0');
signal codec_rdy_i : std_logic := '0';
signal PCM_Record_Left_i: std_logic_vector(0 to C_PCM_DATA_WIDTH-1);
signal PCM_Record_Right_i: std_logic_vector(0 to C_PCM_DATA_WIDTH-1);
begin -- architecture IMP
-----------------------------------------------------------------------------
-- AC97 Timing Module & Interface signals
-----------------------------------------------------------------------------
ac97_timing_I_1 : ac97_timing
port map (
Bit_Clk => AC97_Bit_Clk,
Reset => Reset,
Sync => sync_i,
Bit_Num => open,
Slot_Num => slot_No,
Slot_End => slot_end,
Frame_End => last_frame_cycle
);
AC97_Sync <= sync_i;
-----------------------------------------------------------------------------
-- AC97 Register Interface
-----------------------------------------------------------------------------
-- Register state machine
register_if_PROCESS : process (AC97_Bit_Clk) is
begin
if RESET = '1' then
reg_if_state <= IDLE;
ac97_reg_busy_i <= '0';
ac97_reg_error_i <= '0';
AC97_Reg_Read_Data_Valid <= '0';
elsif AC97_Bit_Clk'event and AC97_Bit_Clk = '1' then
case reg_if_state is
-- Wait for a register transfer strobe to occur.
when IDLE =>
if (AC97_Reg_Read_Strobe = '1' or AC97_Reg_Write_Strobe = '1')
and codec_rdy_i = '1' then
reg_if_state <= WAIT_FOR_NEW_FRAME;
ac97_reg_busy_i <= '1';
ac97_reg_error_i <= '0';
AC97_Reg_Read_Data_Valid <= '0';
register_addr <= AC97_Reg_Addr;
if AC97_Reg_Write_Strobe = '1' then
register_data <= AC97_Reg_Write_Data;
register_write_cmd <= '1';
else
register_write_cmd <= '0';
end if;
end if;
-- Wait for the end of the current frame. During the last cycle of
-- this state (last_frame_cycle = 1), all the signals are
-- latched into slot 0 and a valid request is on its way out.
when WAIT_FOR_NEW_FRAME =>
if last_frame_cycle = '1' then
reg_if_state <= SEND_REQUEST_FRAME;
end if;
-- Wait for the request to be completely sent to the codec.
when SEND_REQUEST_FRAME =>
if last_frame_cycle = '1' then
reg_if_state <= RESPONSE_SLOT0;
end if;
-- Wait for the response in slot 0 and make sure the
-- appropriate response bits are set
when RESPONSE_SLOT0 =>
if slot_No = 0 and slot_end = '1' then
if register_write_cmd = '0' then
if (data_in(14) /= '1' or data_in(13) /= '1') then
-- Bit 14 of Slot 0 indicates a valid slot 1 data
-- (echo the requested address). If this is not a
-- '1' then there is was an error. Bit 13 of Slot 0
-- indicates a valid data response. If the transaction
-- was a read and it is not true, an error.
ac97_reg_error_i <= '1';
reg_if_state <= END_STATE;
else
reg_if_state <= RESPONSE_SLOT1;
end if;
else
-- Nothing else to do for writes
reg_if_state <= END_STATE;
end if;
end if;
-- Check the data in slot 1 and make sure it matches
-- the address sent
when RESPONSE_SLOT1 =>
if slot_No = 1 and slot_end = '1' then
if data_in(18 downto 12) /= register_addr then
ac97_reg_error_i <= '1';
reg_if_state <= END_STATE;
else
-- we need to get the data for read commands
reg_if_state <= RESPONSE_SLOT2;
end if;
end if;
when RESPONSE_SLOT2 =>
if slot_No = 2 and slot_end = '1' then
AC97_Reg_Read_Data <= data_in(19 downto 4);
AC97_Reg_Read_Data_Valid <= '1';
reg_if_state <= END_STATE;
end if;
when END_STATE =>
ac97_reg_busy_i <= '0';
reg_if_state <= IDLE;
when others => NULL;
end case;
end if;
end process register_if_PROCESS;
AC97_Reg_Busy <= ac97_reg_busy_i;
AC97_Reg_Error <= ac97_reg_error_i;
with reg_if_state select
debug(0 to 2) <= "000" when IDLE,
"001" when WAIT_FOR_NEW_FRAME,
"010" when SEND_REQUEST_FRAME,
"011" when RESPONSE_SLOT0,
"100" when RESPONSE_SLOT1,
"101" when RESPONSE_SLOT2,
"110" when END_STATE,
"000" when others;
debug(3 to 15) <= (others => '0');
-- This signal indicates that we are sending a request command
-- and that the address send to the codec is valid
valid_Control_Addr <= '1' when reg_if_state = WAIT_FOR_NEW_FRAME
else '0';
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Output Section
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Setup slot0 data at start of frame
--
-- Slot 0 is the TAG slot. The bits of this slot are defined as
-- follows:
-- bit 15: Valid frame
-- bit 14: valid control address (slot 1)
-- bit 13: valid control data (slot 2)
-- bit 12: valid PCM playback data Left (slot 3)
-- bit 11: valid PCM playback data Right (slot 4)
-- bot 10-2: ignored - fill with zeros
-- bit 1-0: 2-bit codec ID (assigned to '00' for primary)
--
-- The slot 0 signals are created directly from the inputs
-- of the module rather than using the "registered" versions
-- (i.e. ac97_reg_write instead of ac97_reag_write_i). The
-- slot0 signal is latched on the clock edge following
-- the frame signal into the shift register signal "data_out".
--
-----------------------------------------------------------------------------
-- temporary
valid_Frame <= valid_Control_Addr or
pcm_playback_left_valid or
pcm_playback_right_valid;
slot0(15) <= valid_Frame;
slot0(14) <= valid_Control_Addr;
slot0(13) <= register_write_cmd; -- valid data only during write
slot0(12) <= PCM_Playback_Left_Valid;
slot0(11) <= PCM_Playback_Right_Valid;
slot0(10 downto 2) <= "000000000";
slot0(1 downto 0) <= "00";
-----------------------------------------------------------------------------
-- Slot 1
--
-- Slot 1 is the Command Address:
-- Bit 19: Read/Write (1=read,0=write)
-- Bit 18-12: Control register index/address
-- Bit 11:0 reserved (stuff with 0)
-----------------------------------------------------------------------------
slot1(19) <= not register_write_cmd;
slot1(18 downto 12) <= register_addr;
slot1(11 downto 0) <= (others => '0');
-----------------------------------------------------------------------------
-- Slot 2
--
-- Slot 2 is the Command Data Port:
-- Bit 19-4: Control register write data
-- Bit 3-0: reserved (stuff with 0)
-----------------------------------------------------------------------------
slot2(19 downto 4) <= register_data;
slot2( 3 downto 0) <= (others => '0');
-----------------------------------------------------------------------------
-- Setup slot3 data (PCM play left)
-----------------------------------------------------------------------------
process (PCM_Playback_Left) is
begin
slot3((20 - C_PCM_DATA_WIDTH-1) downto 0) <= (others => '0');
slot3(19 downto (20 - C_PCM_DATA_WIDTH)) <= PCM_Playback_Left;
end process;
-----------------------------------------------------------------------------
-- Setup slot4 data (PCM play right)
-----------------------------------------------------------------------------
process (PCM_Playback_Right) is
begin
slot4((20 - C_PCM_DATA_WIDTH-1) downto 0) <= (others => '0');
slot4(19 downto (20 - C_PCM_DATA_WIDTH)) <= PCM_Playback_Right;
end process;
-----------------------------------------------------------------------------
-- Output data multiplexer for AC97_SData_Out signal
--
-- Choose the appropriate data to send out the shift register
-- (new_data_out)
-----------------------------------------------------------------------------
process (last_frame_cycle, slot_end, slot_No, slot0,
slot1, slot2, slot3, slot4) is
begin -- process
new_data_out <= (others => '0');
if (last_frame_cycle = '1') then
new_data_out(19 downto 4) <= slot0;
elsif (slot_end = '1') then
case slot_No is
when 0 => new_data_out(slot1'range) <= slot1;
when 1 => new_data_out(slot2'range) <= slot2;
when 2 => new_data_out <= slot3;
when 3 => new_data_out <= slot4;
when others => null;
end case;
end if;
end process;
-----------------------------------------------------------------------------
-- AC97 data out shift register
-----------------------------------------------------------------------------
Data_Out_Handle : process (AC97_Bit_Clk) is
begin -- process Data_Out_Handle
if reset = '1' then
data_out <= (others => '0');
elsif AC97_Bit_Clk'event and AC97_Bit_Clk = '1' then -- rising clock edge
if (last_frame_cycle = '1') or (slot_end = '1') then
data_out <= New_Data_Out;
else
data_out(19 downto 0) <= data_out(18 downto 0) & '0';
end if;
end if;
end process Data_Out_Handle;
AC97_SData_Out <= data_out(19);
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Input Section
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- AC97 data in shift register
-----------------------------------------------------------------------------
Shifting_Data_Coming_Back : process (AC97_Bit_Clk) is
begin -- process Shifting_Data_Coming_Back
if AC97_Bit_Clk'event and AC97_Bit_Clk = '0' then -- falling clock edge
data_in(19 downto 0) <= data_in(18 downto 0) & AC97_SData_In;
end if;
end process Shifting_Data_Coming_Back;
-----------------------------------------------------------------------------
-- Get slot 0 data (TAG - which slots are valid)
-----------------------------------------------------------------------------
process (AC97_Bit_Clk) is
begin
if AC97_Bit_Clk'event and AC97_Bit_Clk = '1' then -- rising clock edge
if (slot_no = 0 and slot_end = '1') then
codec_rdy_i <= data_in(15);
-- data_in(14) and data(13) are used directly in the reg_if
-- state machine
--return_status_address_valid <= data_in(14);
-- return_status_data_valid <= data_in(13);
record_pcm_left_valid <= data_in(12);
record_pcm_right_valid <= data_in(11);
end if;
end if;
end process;
PCM_Record_Left_Valid <= record_pcm_left_valid and last_frame_cycle;
PCM_Record_Right_Valid <= record_pcm_right_valid and last_frame_cycle;
codec_rdy <= codec_rdy_i;
-----------------------------------------------------------------------------
-- Get slot 1 PCM request bit
-----------------------------------------------------------------------------
process (AC97_Bit_Clk) is
begin
if AC97_Bit_Clk'event and AC97_Bit_Clk = '1' then
if (slot_end = '1' and slot_No = 1 ) then
accept_pcm_left <= not data_in(11);
accept_pcm_right <= not data_in(10);
end if;
end if;
end process;
PCM_Playback_Left_Accept <= accept_pcm_left and last_frame_cycle;
PCM_Playback_Right_Accept <= accept_pcm_right and last_frame_cycle;
-----------------------------------------------------------------------------
-- Get slot 3 and 4 data
-----------------------------------------------------------------------------
Get_Record_Data : process (AC97_Bit_Clk) is
-- synthesis translate_off
variable my_line : LINE;
-- synthesis translate_on
begin -- process Get_Record_Data
if AC97_Bit_Clk'event and AC97_Bit_Clk = '1' then -- rising clock edge
if (slot_end = '1' and slot_No = 3 ) then
PCM_Record_Left_i <= data_in(19 downto (20 - C_PCM_DATA_WIDTH));
-- synthesis translate_off
write(my_line, string'("AC97 Core: Received Left Value "));
write(my_line, bit_vector'( To_bitvector(PCM_Record_Left_i) ));
writeline(output, my_line);
-- synthesis translate_on
elsif (slot_end = '1' and slot_No = 4 ) then
PCM_Record_Right_i <= data_in(19 downto (20 - C_PCM_DATA_WIDTH));
-- synthesis translate_off
write(my_line, string'("AC97 Core: Received Right Value "));
write(my_line, bit_vector'( To_bitvector(PCM_Record_Right_i) ));
writeline(output, my_line);
-- synthesis translate_on
end if;
end if;
end process Get_Record_Data;
PCM_Record_Left <= PCM_Record_Left_i;
PCM_Record_Right <= PCM_Record_Right_i;
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
end architecture IMP;
|
-------------------------------------------------------------------------------
-- ac97_core.vhd
-------------------------------------------------------------------------------
--
-- Mike Wirthlin
--
-------------------------------------------------------------------------------
-- Filename: ac97_acore.vhd
--
-- Description: Provides a simple synchronous interface to a
-- AC97 codec. This was designed for the National
-- LM4549A and only supports slots 0-4.
-- This interface does not have any data buffering.
--
-- The interface to the AC97 is straightforward.
-- To transfer playback data, this interface will
-- sample the playback data and control signals
-- when the PCM_Playback_X_Accept signals are asserted.
-- This sample will
-- be sent to the codec during the next frame. The Record (
-- input) data is provided as an ouptput and is valid when
-- new_frame is asserted.
--
-- This core supports the full 20-bit PCM sample size. The
-- actual size of the PCM can be modified to a lower value for
-- easier interfacing using the C_PCM_DATA_WIDTH generic. This
-- core will stuff the remaining lsb bits with '0' if a value
-- lower than 20 is used.
--
-- This core is synchronous to the AC97_Bit_Clk and all
-- signals interfacing to this core should be synchronized to
-- this clock.
--
-- AC97 Register Interface
--
-- This core provides a simple interface to the AC97 codec registers. To write
-- a new value to the register, drive the AC97_Reg_Addr and
-- AC97_Reg_Write_Data input signals and assert the AC97_Reg_Write_Strobe
-- signal. To read a register value, drive the AC97_Reg_Addr and assert
-- the AC97_Reg_Read_Strobe signal. Once either strobe has been asserted, the
-- register interface state machine will process the request to the CODEC and
-- assert the AC97_Reg_Busy signal. The strobe control signals will be ignored
-- while the state machine is busy (the AC97 only supports one read or write
-- transaction at a time).
--
-- When the transaction is complete, the state machine will respond as
-- follows: first, the AC97_Reg_Busy signal will be deasserted indicating that
-- the transaction is complete and that the interface is ready to handle
-- another interface. If there was an error with the response (i.e. the AC97
-- codec did not respond properly to the request), the AC97_Reg_Error signal
-- will be asserted. This signal will remain asserted until a new register
-- transfer has been initiated.
--
-- On the successful completion of a register read operation, the
-- AC97_Reg_Read_Data_Valid signal will be asserted to validate the data
-- read from the AC97 controller. This signal will remain asserted until a new
-- register transaction is initiated.
--
--
-- This core will produce valid data on the AC97_SData_Out signal
-- during the following slots:
--
-- Slot 0: Tag Phase (indicates valid slots in packet)
-- Slot 1: Read/Write, Control Address
-- Slot 2: Command Data
-- Slot 3: PCM Left
-- Slot 4: PCM Right
--
-- This core will recognize valid data on the AC97_SData_In signal
-- during the following slots:
--
-- Slot 0: Codec/Slot Status Bits
-- Slot 1: Status Address / Slot Request
-- Slot 2: Status Data
-- Slot 3: PCM Record Left
-- Slot 4: PCM Record Righ
--
-- To Do:
-- - signal to validate recorded data
-- - signal to "request" playback data
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- - ac97_core
-- - ac97_timing
--
-------------------------------------------------------------------------------
-- Author: Mike Wirthlin
--
-- History:
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use std.TextIO.all;
library opb_ac97_v2_00_a;
use opb_ac97_v2_00_a.all;
-------------------------------------------------------------------------------
--
-- Genearics Summary
-- C_PLAYBACK: Enable playback logic. Disable to simplify circuit
-- C_RECORD: Enable record logic. Disable to simplify circuit
-- C_PCM_DATA_WIDTH:
-- AC97 specifies a 20-bit data word. HOwever, many codecs don't
-- support the full resolution (The LM4549 only supports 18). This
-- value indicates the number of data bits that will be sent/received
-- from the CODEC. Zeros will be inserted for least-significant digits.
--
-- Signal Summary
--
-- AC97_Bit_Clk:
-- Input clock generated by the AC97 Codec
-- AC97_Sync:
-- Frame synchronization signal. Generated by ac97_timing module.
-- AC97_SData_Out:
-- Serial data out. Transitions on the rising edge of bit_clk. Is
-- sampled by the CODEC on the falling edge
-- AC97_SData_In:
-- Serial data in. Transitions on the rising edge of bit_clk. Is
-- sampled by the this module on the falling edge.
-- AC97_SData_In:
-- CODEC_RDY:
-- This signal is generated by each frame from the AC97
-- Codec. It arrives each frame as the first bit of Slot 1.
-------------------------------------------------------------------------------
entity ac97_core is
generic (
C_PCM_DATA_WIDTH : integer := 16
);
port (
Reset : in std_logic;
-- signals attaching directly to AC97 codec
AC97_Bit_Clk : in std_logic;
AC97_Sync : out std_logic;
AC97_SData_Out : out std_logic;
AC97_SData_In : in std_logic;
-- AC97 register interface
AC97_Reg_Addr : in std_logic_vector(0 to 6);
AC97_Reg_Write_Data : in std_logic_vector(0 to 15);
AC97_Reg_Read_Data : out std_logic_vector(0 to 15);
AC97_Reg_Read_Strobe : in std_logic; -- initiates a "read" command
AC97_Reg_Write_Strobe : in std_logic; -- initiates a "write" command
AC97_Reg_Busy : out std_logic;
AC97_Reg_Error : out std_logic;
AC97_Reg_Read_Data_Valid : out std_logic;
-- Playback signal interface
PCM_Playback_Left: in std_logic_vector(0 to C_PCM_DATA_WIDTH-1);
PCM_Playback_Right: in std_logic_vector(0 to C_PCM_DATA_WIDTH-1);
PCM_Playback_Left_Valid: in std_logic;
PCM_Playback_Right_Valid: in std_logic;
PCM_Playback_Left_Accept: out std_logic;
PCM_Playback_Right_Accept: out std_logic;
-- Record signal interface
PCM_Record_Left: out std_logic_vector(0 to C_PCM_DATA_WIDTH-1);
PCM_Record_Right: out std_logic_vector(0 to C_PCM_DATA_WIDTH-1);
PCM_Record_Left_Valid: out std_logic;
PCM_Record_Right_Valid: out std_logic;
DEBUG : out std_logic_vector(0 to 15);
--
CODEC_RDY : out std_logic
);
end entity ac97_core;
library unisim;
use unisim.all;
architecture IMP of ac97_core is
component ac97_timing is
port (
Bit_Clk : in std_logic;
Reset : in std_logic;
Sync : out std_logic;
Bit_Num : out natural range 0 to 19;
Slot_Num : out natural range 0 to 12;
Slot_End : out std_logic;
Frame_End : out std_logic
);
end component ac97_timing;
signal last_frame_cycle : std_logic;
signal sync_i : std_logic;
signal slot_end : std_logic;
signal slot_No : natural range 0 to 12;
--signal bit_No : natural range 0 to 19;
-- register IF signals
type reg_if_states is (IDLE, WAIT_FOR_NEW_FRAME, SEND_REQUEST_FRAME,
RESPONSE_SLOT0, RESPONSE_SLOT1, RESPONSE_SLOT2,
END_STATE);
signal reg_if_state : reg_if_states := IDLE;
signal register_addr : std_logic_vector(0 to 6) := (others => '0');
signal register_data : std_logic_vector(0 to 15) := (others => '0');
signal register_write_cmd : std_logic := '0';
signal ac97_reg_error_i, ac97_reg_busy_i : std_logic := '0';
signal valid_Frame : std_logic;
signal valid_Control_Addr : std_logic;
-- Slot 0 in signals
signal record_pcm_left_valid : std_logic;
signal record_pcm_right_valid : std_logic;
--signal return_status_address_valid : std_logic;
--signal return_status_data_valid : std_logic;
signal accept_pcm_left : std_logic;
signal accept_pcm_right : std_logic;
signal new_data_out : std_logic_vector(19 downto 0) := (others => '0');
signal data_out : std_logic_vector(19 downto 0) := (others => '0');
signal data_in : std_logic_vector(19 downto 0);
signal slot0 : std_logic_vector(15 downto 0);
signal slot1 : std_logic_vector(19 downto 0);
signal slot2 : std_logic_vector(19 downto 0);
signal slot3 : std_logic_vector(19 downto 0) := (others => '0');
signal slot4 : std_logic_vector(19 downto 0) := (others => '0');
signal codec_rdy_i : std_logic := '0';
signal PCM_Record_Left_i: std_logic_vector(0 to C_PCM_DATA_WIDTH-1);
signal PCM_Record_Right_i: std_logic_vector(0 to C_PCM_DATA_WIDTH-1);
begin -- architecture IMP
-----------------------------------------------------------------------------
-- AC97 Timing Module & Interface signals
-----------------------------------------------------------------------------
ac97_timing_I_1 : ac97_timing
port map (
Bit_Clk => AC97_Bit_Clk,
Reset => Reset,
Sync => sync_i,
Bit_Num => open,
Slot_Num => slot_No,
Slot_End => slot_end,
Frame_End => last_frame_cycle
);
AC97_Sync <= sync_i;
-----------------------------------------------------------------------------
-- AC97 Register Interface
-----------------------------------------------------------------------------
-- Register state machine
register_if_PROCESS : process (AC97_Bit_Clk) is
begin
if RESET = '1' then
reg_if_state <= IDLE;
ac97_reg_busy_i <= '0';
ac97_reg_error_i <= '0';
AC97_Reg_Read_Data_Valid <= '0';
elsif AC97_Bit_Clk'event and AC97_Bit_Clk = '1' then
case reg_if_state is
-- Wait for a register transfer strobe to occur.
when IDLE =>
if (AC97_Reg_Read_Strobe = '1' or AC97_Reg_Write_Strobe = '1')
and codec_rdy_i = '1' then
reg_if_state <= WAIT_FOR_NEW_FRAME;
ac97_reg_busy_i <= '1';
ac97_reg_error_i <= '0';
AC97_Reg_Read_Data_Valid <= '0';
register_addr <= AC97_Reg_Addr;
if AC97_Reg_Write_Strobe = '1' then
register_data <= AC97_Reg_Write_Data;
register_write_cmd <= '1';
else
register_write_cmd <= '0';
end if;
end if;
-- Wait for the end of the current frame. During the last cycle of
-- this state (last_frame_cycle = 1), all the signals are
-- latched into slot 0 and a valid request is on its way out.
when WAIT_FOR_NEW_FRAME =>
if last_frame_cycle = '1' then
reg_if_state <= SEND_REQUEST_FRAME;
end if;
-- Wait for the request to be completely sent to the codec.
when SEND_REQUEST_FRAME =>
if last_frame_cycle = '1' then
reg_if_state <= RESPONSE_SLOT0;
end if;
-- Wait for the response in slot 0 and make sure the
-- appropriate response bits are set
when RESPONSE_SLOT0 =>
if slot_No = 0 and slot_end = '1' then
if register_write_cmd = '0' then
if (data_in(14) /= '1' or data_in(13) /= '1') then
-- Bit 14 of Slot 0 indicates a valid slot 1 data
-- (echo the requested address). If this is not a
-- '1' then there is was an error. Bit 13 of Slot 0
-- indicates a valid data response. If the transaction
-- was a read and it is not true, an error.
ac97_reg_error_i <= '1';
reg_if_state <= END_STATE;
else
reg_if_state <= RESPONSE_SLOT1;
end if;
else
-- Nothing else to do for writes
reg_if_state <= END_STATE;
end if;
end if;
-- Check the data in slot 1 and make sure it matches
-- the address sent
when RESPONSE_SLOT1 =>
if slot_No = 1 and slot_end = '1' then
if data_in(18 downto 12) /= register_addr then
ac97_reg_error_i <= '1';
reg_if_state <= END_STATE;
else
-- we need to get the data for read commands
reg_if_state <= RESPONSE_SLOT2;
end if;
end if;
when RESPONSE_SLOT2 =>
if slot_No = 2 and slot_end = '1' then
AC97_Reg_Read_Data <= data_in(19 downto 4);
AC97_Reg_Read_Data_Valid <= '1';
reg_if_state <= END_STATE;
end if;
when END_STATE =>
ac97_reg_busy_i <= '0';
reg_if_state <= IDLE;
when others => NULL;
end case;
end if;
end process register_if_PROCESS;
AC97_Reg_Busy <= ac97_reg_busy_i;
AC97_Reg_Error <= ac97_reg_error_i;
with reg_if_state select
debug(0 to 2) <= "000" when IDLE,
"001" when WAIT_FOR_NEW_FRAME,
"010" when SEND_REQUEST_FRAME,
"011" when RESPONSE_SLOT0,
"100" when RESPONSE_SLOT1,
"101" when RESPONSE_SLOT2,
"110" when END_STATE,
"000" when others;
debug(3 to 15) <= (others => '0');
-- This signal indicates that we are sending a request command
-- and that the address send to the codec is valid
valid_Control_Addr <= '1' when reg_if_state = WAIT_FOR_NEW_FRAME
else '0';
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Output Section
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Setup slot0 data at start of frame
--
-- Slot 0 is the TAG slot. The bits of this slot are defined as
-- follows:
-- bit 15: Valid frame
-- bit 14: valid control address (slot 1)
-- bit 13: valid control data (slot 2)
-- bit 12: valid PCM playback data Left (slot 3)
-- bit 11: valid PCM playback data Right (slot 4)
-- bot 10-2: ignored - fill with zeros
-- bit 1-0: 2-bit codec ID (assigned to '00' for primary)
--
-- The slot 0 signals are created directly from the inputs
-- of the module rather than using the "registered" versions
-- (i.e. ac97_reg_write instead of ac97_reag_write_i). The
-- slot0 signal is latched on the clock edge following
-- the frame signal into the shift register signal "data_out".
--
-----------------------------------------------------------------------------
-- temporary
valid_Frame <= valid_Control_Addr or
pcm_playback_left_valid or
pcm_playback_right_valid;
slot0(15) <= valid_Frame;
slot0(14) <= valid_Control_Addr;
slot0(13) <= register_write_cmd; -- valid data only during write
slot0(12) <= PCM_Playback_Left_Valid;
slot0(11) <= PCM_Playback_Right_Valid;
slot0(10 downto 2) <= "000000000";
slot0(1 downto 0) <= "00";
-----------------------------------------------------------------------------
-- Slot 1
--
-- Slot 1 is the Command Address:
-- Bit 19: Read/Write (1=read,0=write)
-- Bit 18-12: Control register index/address
-- Bit 11:0 reserved (stuff with 0)
-----------------------------------------------------------------------------
slot1(19) <= not register_write_cmd;
slot1(18 downto 12) <= register_addr;
slot1(11 downto 0) <= (others => '0');
-----------------------------------------------------------------------------
-- Slot 2
--
-- Slot 2 is the Command Data Port:
-- Bit 19-4: Control register write data
-- Bit 3-0: reserved (stuff with 0)
-----------------------------------------------------------------------------
slot2(19 downto 4) <= register_data;
slot2( 3 downto 0) <= (others => '0');
-----------------------------------------------------------------------------
-- Setup slot3 data (PCM play left)
-----------------------------------------------------------------------------
process (PCM_Playback_Left) is
begin
slot3((20 - C_PCM_DATA_WIDTH-1) downto 0) <= (others => '0');
slot3(19 downto (20 - C_PCM_DATA_WIDTH)) <= PCM_Playback_Left;
end process;
-----------------------------------------------------------------------------
-- Setup slot4 data (PCM play right)
-----------------------------------------------------------------------------
process (PCM_Playback_Right) is
begin
slot4((20 - C_PCM_DATA_WIDTH-1) downto 0) <= (others => '0');
slot4(19 downto (20 - C_PCM_DATA_WIDTH)) <= PCM_Playback_Right;
end process;
-----------------------------------------------------------------------------
-- Output data multiplexer for AC97_SData_Out signal
--
-- Choose the appropriate data to send out the shift register
-- (new_data_out)
-----------------------------------------------------------------------------
process (last_frame_cycle, slot_end, slot_No, slot0,
slot1, slot2, slot3, slot4) is
begin -- process
new_data_out <= (others => '0');
if (last_frame_cycle = '1') then
new_data_out(19 downto 4) <= slot0;
elsif (slot_end = '1') then
case slot_No is
when 0 => new_data_out(slot1'range) <= slot1;
when 1 => new_data_out(slot2'range) <= slot2;
when 2 => new_data_out <= slot3;
when 3 => new_data_out <= slot4;
when others => null;
end case;
end if;
end process;
-----------------------------------------------------------------------------
-- AC97 data out shift register
-----------------------------------------------------------------------------
Data_Out_Handle : process (AC97_Bit_Clk) is
begin -- process Data_Out_Handle
if reset = '1' then
data_out <= (others => '0');
elsif AC97_Bit_Clk'event and AC97_Bit_Clk = '1' then -- rising clock edge
if (last_frame_cycle = '1') or (slot_end = '1') then
data_out <= New_Data_Out;
else
data_out(19 downto 0) <= data_out(18 downto 0) & '0';
end if;
end if;
end process Data_Out_Handle;
AC97_SData_Out <= data_out(19);
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Input Section
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- AC97 data in shift register
-----------------------------------------------------------------------------
Shifting_Data_Coming_Back : process (AC97_Bit_Clk) is
begin -- process Shifting_Data_Coming_Back
if AC97_Bit_Clk'event and AC97_Bit_Clk = '0' then -- falling clock edge
data_in(19 downto 0) <= data_in(18 downto 0) & AC97_SData_In;
end if;
end process Shifting_Data_Coming_Back;
-----------------------------------------------------------------------------
-- Get slot 0 data (TAG - which slots are valid)
-----------------------------------------------------------------------------
process (AC97_Bit_Clk) is
begin
if AC97_Bit_Clk'event and AC97_Bit_Clk = '1' then -- rising clock edge
if (slot_no = 0 and slot_end = '1') then
codec_rdy_i <= data_in(15);
-- data_in(14) and data(13) are used directly in the reg_if
-- state machine
--return_status_address_valid <= data_in(14);
-- return_status_data_valid <= data_in(13);
record_pcm_left_valid <= data_in(12);
record_pcm_right_valid <= data_in(11);
end if;
end if;
end process;
PCM_Record_Left_Valid <= record_pcm_left_valid and last_frame_cycle;
PCM_Record_Right_Valid <= record_pcm_right_valid and last_frame_cycle;
codec_rdy <= codec_rdy_i;
-----------------------------------------------------------------------------
-- Get slot 1 PCM request bit
-----------------------------------------------------------------------------
process (AC97_Bit_Clk) is
begin
if AC97_Bit_Clk'event and AC97_Bit_Clk = '1' then
if (slot_end = '1' and slot_No = 1 ) then
accept_pcm_left <= not data_in(11);
accept_pcm_right <= not data_in(10);
end if;
end if;
end process;
PCM_Playback_Left_Accept <= accept_pcm_left and last_frame_cycle;
PCM_Playback_Right_Accept <= accept_pcm_right and last_frame_cycle;
-----------------------------------------------------------------------------
-- Get slot 3 and 4 data
-----------------------------------------------------------------------------
Get_Record_Data : process (AC97_Bit_Clk) is
-- synthesis translate_off
variable my_line : LINE;
-- synthesis translate_on
begin -- process Get_Record_Data
if AC97_Bit_Clk'event and AC97_Bit_Clk = '1' then -- rising clock edge
if (slot_end = '1' and slot_No = 3 ) then
PCM_Record_Left_i <= data_in(19 downto (20 - C_PCM_DATA_WIDTH));
-- synthesis translate_off
write(my_line, string'("AC97 Core: Received Left Value "));
write(my_line, bit_vector'( To_bitvector(PCM_Record_Left_i) ));
writeline(output, my_line);
-- synthesis translate_on
elsif (slot_end = '1' and slot_No = 4 ) then
PCM_Record_Right_i <= data_in(19 downto (20 - C_PCM_DATA_WIDTH));
-- synthesis translate_off
write(my_line, string'("AC97 Core: Received Right Value "));
write(my_line, bit_vector'( To_bitvector(PCM_Record_Right_i) ));
writeline(output, my_line);
-- synthesis translate_on
end if;
end if;
end process Get_Record_Data;
PCM_Record_Left <= PCM_Record_Left_i;
PCM_Record_Right <= PCM_Record_Right_i;
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
end architecture IMP;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: ahbtrace_mb
-- File: ahbtrace_mb.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Modified: Jan Andersson - Aeroflex Gaisler
-- Description: AHB trace unit that can have registers on a separate bus
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.misc.all;
entity ahbtrace_mb is
generic (
hindex : integer := 0;
ioaddr : integer := 16#000#;
iomask : integer := 16#E00#;
tech : integer := DEFMEMTECH;
irq : integer := 0;
kbytes : integer := 1;
bwidth : integer := 32;
ahbfilt : integer := 0;
scantest : integer range 0 to 1 := 0;
exttimer : integer range 0 to 1 := 0;
exten : integer range 0 to 1 := 0);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type; -- Register interface
ahbso : out ahb_slv_out_type;
tahbmi : in ahb_mst_in_type; -- Trace
tahbsi : in ahb_slv_in_type;
timer : in std_logic_vector(30 downto 0) := (others => '0');
astat : out amba_stat_type;
resen : in std_ulogic := '0'
);
end;
architecture rtl of ahbtrace_mb is
signal tahbmiv : ahb_mst_in_vector_type(0 to 0);
signal tahbsiv : ahb_slv_in_vector_type(0 to 0);
begin
tahbmiv(0) <= tahbmi;
tahbsiv(0) <= tahbsi;
ahbt0 : ahbtrace_mmb
generic map (
hindex => hindex,
ioaddr => ioaddr,
iomask => iomask,
tech => tech,
irq => irq,
kbytes => kbytes,
bwidth => bwidth,
ahbfilt => ahbfilt,
ntrace => 1,
scantest => scantest,
exttimer => exttimer,
exten => exten)
port map(
rst => rst,
clk => clk,
ahbsi => ahbsi,
ahbso => ahbso,
tahbmiv => tahbmiv,
tahbsiv => tahbsiv,
timer => timer,
astat => astat,
resen => resen);
end;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity multiplex_1_tb is
end entity;
architecture behav of multiplex_1_tb is
component multiplex_1
port (
smi : in std_logic_vector(6 downto 0);
smo : out std_logic;
se : in std_logic_vector(2 downto 0)
);
end component;
for multiplex_1_0 : multiplex_1 use entity work.multiplex_1;
signal smi : std_logic_vector (6 downto 0);
signal se : std_logic_vector (2 downto 0);
signal smo : std_logic;
begin
multiplex_1_0: multiplex_1 port map (smi=>smi, smo=>smo, se=>se);
process
begin
smi <= "1111011";
se <= "000";
wait for 5 ns;
se <= "001";
wait for 5 ns;
se <= "010";
wait for 5 ns;
se <= "011";
wait for 5 ns;
se <= "100";
wait for 5 ns;
smi <= "1110111";
se <= "000";
wait for 5 ns;
se <= "001";
wait for 5 ns;
se <= "010";
wait for 5 ns;
se <= "011";
wait for 5 ns;
se <= "100";
wait for 5 ns;
se <= "101";
wait for 5 ns;
se <= "110";
wait for 5 ns;
se <= "111";
wait for 5 ns;
smi <= "1011111";
se <= "000";
wait for 5 ns;
se <= "110";
wait for 5 ns;
se <= "010";
wait for 5 ns;
se <= "111";
wait for 5 ns;
se <= "101";
wait for 5 ns;
wait;
end process;
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.conv_integer;
use ieee.std_logic_arith.conv_std_logic_vector;
use ieee.std_logic_unsigned.all;
---po_i2c_status(3): '1' = bus transfering, '0' = stopped.
---po_i2c_status(2): '1' = read, '0' = write.
---po_i2c_status(1): '1' = data acknowleged, '0' = not acknowleged.
---po_i2c_status(0): '1' = addr acknowleged, '0' = not acknowleged.
entity i2c_slave is
port (
pi_rst_n : in std_logic;
pi_base_clk : in std_logic;
---i2c bus lines...
pi_slave_addr : in std_logic_vector (6 downto 0);
pi_i2c_scl : in std_logic;
pi_i2c_sda : in std_logic;
po_i2c_sda : out std_logic;
---i2c bus contoler internal lines...
pi_i2c_read_data : in std_logic_vector (7 downto 0);
po_i2c_write_data : out std_logic_vector (7 downto 0);
po_i2c_status : out std_logic_vector (3 downto 0)
);
end i2c_slave;
architecture rtl of i2c_slave is
type i2c_sp_stat is (
stop, start, restart
);
type i2c_bus_stat is (
idle,
a6, a5, a4, a3, a2, a1, a0, rw, a_ack,
d7, d6, d5, d4, d3, d2, d1, d0, d_ack
);
component edge_detecter port (
pi_rst_n : in std_logic;
pi_base_clk : in std_logic;
pi_input : in std_logic;
po_rise : out std_logic;
po_fall : out std_logic
);
end component;
signal reg_cur_sp : i2c_sp_stat;
signal reg_scl_rise : std_logic;
signal reg_scl_fall : std_logic;
signal reg_sda_rise : std_logic;
signal reg_sda_fall : std_logic;
signal reg_cur_state : i2c_bus_stat;
signal reg_next_state : i2c_bus_stat;
signal reg_i2c_cmd_addr : std_logic_vector(6 downto 0);
signal reg_i2c_cmd_r_nw : std_logic;
signal reg_i2c_cmd_in_data : std_logic_vector(6 downto 0);
begin
--edge detecter...
scl_detect_p : edge_detecter port map (pi_rst_n, pi_base_clk, pi_i2c_scl, reg_scl_rise, reg_scl_fall);
sda_detect_p : edge_detecter port map (pi_rst_n, pi_base_clk, pi_i2c_sda, reg_sda_rise, reg_sda_fall);
--start/stop w/ edge detect.
start_stop_p : process (pi_rst_n, pi_base_clk)
begin
if (pi_rst_n = '0') then
reg_cur_sp <= stop;
elsif (rising_edge(pi_base_clk)) then
if (pi_i2c_scl = '1' and reg_scl_rise = '0' and reg_scl_fall = '0' and reg_sda_fall = '1'
and reg_cur_sp = stop) then
reg_cur_sp <= start;
elsif (pi_i2c_scl = '1' and reg_scl_rise = '0' and reg_scl_fall = '0' and reg_sda_fall = '1'
and reg_cur_sp = start) then
reg_cur_sp <= restart;
elsif (pi_i2c_scl = '1' and reg_scl_rise = '0' and reg_scl_fall = '0' and reg_sda_rise = '1'
and reg_cur_sp = start) then
reg_cur_sp <= stop;
elsif (reg_cur_sp = restart) then
reg_cur_sp <= start;
end if;
end if;--if (pi_rst_n = '0') then
end process;
--i2c bus state machine (state transition)...
set_stat_p : process (pi_rst_n, reg_cur_sp, pi_base_clk)
begin
if (pi_rst_n = '0') then
reg_cur_state <= idle;
elsif (reg_cur_sp = stop or reg_cur_sp = restart) then
reg_cur_state <= idle;
elsif (rising_edge(pi_base_clk)) then
if (reg_scl_rise = '1') then
reg_cur_state <= reg_next_state;
end if;
end if;--if (pi_rst_n = '0') then
end process;
--state change to next.
next_stat_p : process (reg_cur_state, reg_i2c_cmd_r_nw, pi_i2c_sda)
procedure set_next_stat
(
pi_stat : in i2c_bus_stat
) is
begin
reg_next_state <= pi_stat;
end;
begin
case reg_cur_state is
when idle =>
set_next_stat(a6);
when a6 =>
set_next_stat(a5);
when a5 =>
set_next_stat(a4);
when a4 =>
set_next_stat(a3);
when a3 =>
set_next_stat(a2);
when a2 =>
set_next_stat(a1);
when a1 =>
set_next_stat(a0);
when a0 =>
set_next_stat(rw);
when rw =>
set_next_stat(a_ack);
when a_ack =>
set_next_stat(d7);
when d7 =>
set_next_stat(d6);
when d6 =>
set_next_stat(d5);
when d5 =>
set_next_stat(d4);
when d4 =>
set_next_stat(d3);
when d3 =>
set_next_stat(d2);
when d2 =>
set_next_stat(d1);
when d1 =>
set_next_stat(d0);
when d0 =>
if (reg_i2c_cmd_r_nw = '0') then
set_next_stat(d_ack);
else
--wait for ack.
if (pi_i2c_sda = '0') then
set_next_stat(d_ack);
else
set_next_stat(d0);
end if;
end if;
when d_ack =>
set_next_stat(d7);
end case;
end process;
--i2c addr/data set.
set_addr : process (pi_rst_n, pi_base_clk)
begin
if (pi_rst_n = '0') then
reg_i2c_cmd_addr <= (others => '0');
reg_i2c_cmd_r_nw <= '1';
reg_i2c_cmd_in_data <= (others => '0');
po_i2c_write_data <= (others => '0');
elsif (rising_edge(pi_base_clk)) then
if (reg_scl_rise = '1') then
--address sequence.
if (reg_cur_sp = start and reg_cur_state = idle) then
reg_i2c_cmd_addr (6) <= pi_i2c_sda;
elsif (reg_cur_state = a6) then
reg_i2c_cmd_addr (5) <= pi_i2c_sda;
elsif (reg_cur_state = a5) then
reg_i2c_cmd_addr (4) <= pi_i2c_sda;
elsif (reg_cur_state = a4) then
reg_i2c_cmd_addr (3) <= pi_i2c_sda;
elsif (reg_cur_state = a3) then
reg_i2c_cmd_addr (2) <= pi_i2c_sda;
elsif (reg_cur_state = a2) then
reg_i2c_cmd_addr (1) <= pi_i2c_sda;
elsif (reg_cur_state = a1) then
reg_i2c_cmd_addr (0) <= pi_i2c_sda;
elsif (reg_cur_state = a0) then
reg_i2c_cmd_r_nw <= pi_i2c_sda;
--data write sequence (input).
elsif (reg_cur_state = a_ack and reg_i2c_cmd_r_nw = '0') then
reg_i2c_cmd_in_data (6) <= pi_i2c_sda;
elsif (reg_cur_state = d7 and reg_i2c_cmd_r_nw = '0') then
reg_i2c_cmd_in_data (5) <= pi_i2c_sda;
elsif (reg_cur_state = d6 and reg_i2c_cmd_r_nw = '0') then
reg_i2c_cmd_in_data (4) <= pi_i2c_sda;
elsif (reg_cur_state = d5 and reg_i2c_cmd_r_nw = '0') then
reg_i2c_cmd_in_data (3) <= pi_i2c_sda;
elsif (reg_cur_state = d4 and reg_i2c_cmd_r_nw = '0') then
reg_i2c_cmd_in_data (2) <= pi_i2c_sda;
elsif (reg_cur_state = d3 and reg_i2c_cmd_r_nw = '0') then
reg_i2c_cmd_in_data (1) <= pi_i2c_sda;
elsif (reg_cur_state = d2 and reg_i2c_cmd_r_nw = '0') then
reg_i2c_cmd_in_data (0) <= pi_i2c_sda;
elsif (reg_cur_state = d1 and reg_i2c_cmd_r_nw = '0') then
po_i2c_write_data <= reg_i2c_cmd_in_data & pi_i2c_sda;
end if;
end if;--if (reg_scl_rise = '1') then
end if;--if (pi_rst_n = '0') then
end process;
--output status.
out_stat : process (pi_rst_n, pi_base_clk)
begin
if (pi_rst_n = '0') then
po_i2c_status <= (others => '0');
elsif (rising_edge(pi_base_clk)) then
if (reg_scl_rise = '1') then
if (reg_i2c_cmd_addr = pi_slave_addr) then
if (reg_cur_state = d7 or
reg_cur_state = d6 or
reg_cur_state = d5 or
reg_cur_state = d4 or
reg_cur_state = d3 or
reg_cur_state = d2 or
reg_cur_state = d1 or
reg_cur_state = d0) then
po_i2c_status(3) <= '1';
else
po_i2c_status(3) <= '0';
end if;
po_i2c_status(2) <= reg_i2c_cmd_r_nw;
if (reg_cur_state = d_ack and reg_i2c_cmd_r_nw = '0') then
--write
po_i2c_status(1) <= '1';
elsif (reg_cur_state = d0 and reg_i2c_cmd_r_nw = '1') then
--read
po_i2c_status(1) <= not pi_i2c_sda;
else
po_i2c_status(1) <= '0';
end if;
if (reg_cur_state = a_ack) then
po_i2c_status(0) <= '1';
else
po_i2c_status(0) <= '0';
end if;
else
po_i2c_status <= (others => '0');
end if;--if (reg_i2c_cmd_addr = pi_slave_addr) then
end if;--if (reg_scl_rise = '1') then
end if;--if (pi_rst_n = '0') then
end process;
--output (ack and read response: output) i2c bus.
out_data : process (pi_rst_n, pi_base_clk)
begin
if (pi_rst_n = '0') then
po_i2c_sda <= 'Z';
elsif (rising_edge(pi_base_clk)) then
if (reg_scl_fall = '1') then
if (reg_i2c_cmd_addr = pi_slave_addr) then
if (reg_cur_state = idle) then
--stand by.
po_i2c_sda <= 'Z';
elsif (reg_cur_state = rw) then
--addr ack reply.
po_i2c_sda <= '0';
elsif (reg_cur_state = a_ack) then
--data input.
if (reg_i2c_cmd_r_nw = '0') then
po_i2c_sda <= 'Z';
--data output.
else
po_i2c_sda <= pi_i2c_read_data(7);
end if;
--data output.
elsif (reg_cur_state = d7 and reg_i2c_cmd_r_nw = '1') then
po_i2c_sda <= pi_i2c_read_data(6);
elsif (reg_cur_state = d6 and reg_i2c_cmd_r_nw = '1') then
po_i2c_sda <= pi_i2c_read_data(5);
elsif (reg_cur_state = d5 and reg_i2c_cmd_r_nw = '1') then
po_i2c_sda <= pi_i2c_read_data(4);
elsif (reg_cur_state = d4 and reg_i2c_cmd_r_nw = '1') then
po_i2c_sda <= pi_i2c_read_data(3);
elsif (reg_cur_state = d3 and reg_i2c_cmd_r_nw = '1') then
po_i2c_sda <= pi_i2c_read_data(2);
elsif (reg_cur_state = d2 and reg_i2c_cmd_r_nw = '1') then
po_i2c_sda <= pi_i2c_read_data(1);
elsif (reg_cur_state = d1 and reg_i2c_cmd_r_nw = '1') then
po_i2c_sda <= pi_i2c_read_data(0);
elsif (reg_cur_state = d0) then
--data ack reply.
if (reg_i2c_cmd_r_nw = '0') then
po_i2c_sda <= '0';
else
--yield bus for incoming data.
po_i2c_sda <= 'Z';
end if;
elsif (reg_cur_state = d_ack) then
--data receive.
if (reg_i2c_cmd_r_nw = '0') then
po_i2c_sda <= 'Z';
else
--data out.
po_i2c_sda <= pi_i2c_read_data(7);
end if;
end if;
else
po_i2c_sda <= 'Z';
end if;--reg_i2c_cmd_addr = pi_slave_addr
end if;--if (reg_scl_fall = '1') then
end if;--if (pi_rst_n = '0') then
end process;
end rtl;
|
entity one is
end entity;
architecture a of one is
signal x : integer;
signal y, z : integer := 7;
begin
end architecture;
architecture b of one is
begin
end b;
architecture c of one is
begin
end;
|
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