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`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect end_protected
|
architecture RTL of FIFO is
begin
process
begin
loop
a <= b;
end loop;
-- Violations below
loop
a <= b;
end loop;
end process;
end;
|
library ieee;
use ieee.std_logic_1164.all;
package test_pkg is
signal glob_sig : std_logic := '1';
end package;
library ieee;
use ieee.std_logic_1164.all;
use work.test_pkg.all;
entity issue483 is
end entity;
architecture rtl of issue483 is
begin
p_proc : process
constant C_CONST : std_logic := glob_sig;
begin
assert C_CONST = '1';
wait;
end process;
end architecture;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: pci_mt
-- File: pci_mt.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Modified: Alf Vaerneus - Gaisler Research
-- Description: Simple PCI master and target interface
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library gaisler;
use gaisler.pci.all;
use gaisler.pcilib.all;
entity pci_mt is
generic (
hmstndx : integer := 0;
abits : integer := 21;
device_id : integer := 0; -- PCI device ID
vendor_id : integer := 0; -- PCI vendor ID
master : integer := 1; -- Enable PCI Master
hslvndx : integer := 0;
haddr : integer := 16#F00#;
hmask : integer := 16#F00#;
ioaddr : integer := 16#000#;
nsync : integer range 1 to 2 := 1; -- 1 or 2 sync regs between clocks
oepol : integer := 0
);
port(
rst : in std_logic;
clk : in std_logic;
pciclk : in std_logic;
pcii : in pci_in_type;
pcio : out pci_out_type;
ahbmi : in ahb_mst_in_type;
ahbmo : out ahb_mst_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type
);
end;
architecture rtl of pci_mt is
constant REVISION : amba_version_type := 0;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_PCISBRG, 0, REVISION, 0),
4 => ahb_membar(haddr, '0', '0', hmask),
5 => ahb_iobar (ioaddr, 16#E00#),
others => zero32);
constant CSYNC : integer := nsync-1;
constant MADDR_WIDTH : integer := abits;
constant HADDR_WIDTH : integer := 28;
type pci_input_type is record
ad : std_logic_vector(31 downto 0);
cbe : std_logic_vector(3 downto 0);
frame : std_logic;
devsel : std_logic;
idsel : std_logic;
trdy : std_logic;
irdy : std_logic;
par : std_logic;
stop : std_logic;
rst : std_logic;
gnt : std_logic;
end record;
type ahbs_input_type is record
haddr : std_logic_vector(HADDR_WIDTH - 1 downto 0);
htrans : std_logic_vector(1 downto 0);
hwrite : std_logic;
hsize : std_logic_vector(1 downto 0);
hburst : std_logic_vector(2 downto 0);
hwdata : std_logic_vector(31 downto 0);
hsel : std_logic;
hiosel : std_logic;
hready : std_logic;
end record;
type pci_target_state_type is (idle, b_busy, s_data, backoff, turn_ar);
type pci_master_state_type is (idle, addr, m_data, turn_ar, s_tar, dr_bus);
type pci_config_command_type is record
ioen : std_logic; -- I/O access enable
men : std_logic; -- Memory access enable
msen : std_logic; -- Master enable
spcen : std_logic; -- Special cycle enable
mwie : std_logic; -- Memory write and invalidate enable
vgaps : std_logic; -- VGA palette snooping enable
per : std_logic; -- Parity error response enable
wcc : std_logic; -- Address stepping enable
serre : std_logic; -- Enable SERR# driver
fbtbe : std_logic; -- Fast back-to-back enable
end record;
type pci_config_status_type is record
c66mhz : std_logic; -- 66MHz capability
udf : std_logic; -- UDF supported
fbtbc : std_logic; -- Fast back-to-back capability
dped : std_logic; -- Data parity error detected
dst : std_logic_vector(1 downto 0); -- DEVSEL timing
sta : std_logic; -- Signaled target abort
rta : std_logic; -- Received target abort
rma : std_logic; -- Received master abort
sse : std_logic; -- Signaled system error
dpe : std_logic; -- Detected parity error
end record;
type pci_reg_type is record
addr : std_logic_vector(MADDR_WIDTH-1 downto 0);
ad : std_logic_vector(31 downto 0);
cbe : std_logic_vector(3 downto 0);
lcbe : std_logic_vector(3 downto 0);
t_state : pci_target_state_type; -- PCI target state machine
m_state : pci_master_state_type; -- PCI master state machine
csel : std_logic; -- Configuration chip select
msel : std_logic; -- Memory hit
read : std_logic;
devsel : std_logic; -- PCI device select
trdy : std_logic; -- Target ready
irdy : std_logic; -- Master ready
stop : std_logic; -- Target stop request
par : std_logic; -- PCI bus parity
req : std_logic; -- Master bus request
oe_par : std_logic;
oe_ad : std_logic;
oe_trdy : std_logic;
oe_devsel: std_logic;
oe_ctrl : std_logic;
oe_cbe : std_logic;
oe_stop : std_logic;
oe_frame : std_logic;
oe_irdy : std_logic;
oe_req : std_logic;
noe_par : std_logic;
noe_ad : std_logic;
noe_trdy : std_logic;
noe_devsel: std_logic;
noe_ctrl : std_logic;
noe_cbe : std_logic;
noe_stop : std_logic;
noe_frame : std_logic;
noe_irdy : std_logic;
noe_req : std_logic;
request : std_logic; -- Request from Back-end
frame : std_logic; -- Master frame
bar0 : std_logic_vector(31 downto MADDR_WIDTH);
page : std_logic_vector(31 downto MADDR_WIDTH-1);
comm : pci_config_command_type;
stat : pci_config_status_type;
laddr : std_logic_vector(31 downto 0);
ldata : std_logic_vector(31 downto 0);
pwrite : std_logic;
hwrite : std_logic;
start : std_logic;
hreq : std_logic;
hreq_ack : std_logic_vector(csync downto 0);
preq : std_logic_vector(csync downto 0);
preq_ack : std_logic;
rready : std_logic_vector(csync downto 0);
wready : std_logic_vector(csync downto 0);
sync : std_logic_vector(csync downto 0);
pabort : std_logic;
mcnt : std_logic_vector(2 downto 0);
maddr : std_logic_vector(31 downto 0);
mdata : std_logic_vector(31 downto 0);
stop_req : std_logic;
end record;
type cpu_master_state_type is (idle, sync1, busy, sync2);
type cpu_slave_state_type is (idle, getd, req, sync, read, sync2, t_done);
type cpu_reg_type is record
tdata : std_logic_vector(31 downto 0); -- Target data
maddr : std_logic_vector(31 downto 0); -- Master data
mdata : std_logic_vector(31 downto 0); -- Master data
be : std_logic_vector(3 downto 0);
m_state : cpu_master_state_type; -- AMBA master state machine
s_state : cpu_slave_state_type; -- AMBA slave state machine
start : std_logic_vector(csync downto 0);
hreq : std_logic_vector(csync downto 0);
hreq_ack : std_logic;
preq : std_logic;
preq_ack : std_logic_vector(csync downto 0);
sync : std_logic;
hwrite : std_logic; -- AHB write on PCI
pabort : std_logic_vector(csync downto 0);
perror : std_logic;
rready : std_logic;
wready : std_logic;
hrdata : std_logic_vector(31 downto 0);
hresp : std_logic_vector(1 downto 0);
pciba : std_logic_vector(3 downto 0);
end record;
signal clk_int : std_logic;
signal pr : pci_input_type;
signal hr : ahbs_input_type;
signal r, rin : pci_reg_type;
signal r2, r2in : cpu_reg_type;
signal dmai : ahb_dma_in_type;
signal dmao : ahb_dma_out_type;
signal roe_ad, rioe_ad : std_logic_vector(31 downto 0);
attribute syn_preserve : boolean;
attribute syn_preserve of roe_ad : signal is true;
begin
-- Back-end state machine (AHB clock domain)
comb : process (rst, r2, r, dmao, hr, ahbsi)
variable vdmai : ahb_dma_in_type;
variable v : cpu_reg_type;
variable request : std_logic;
variable hready : std_logic;
variable hresp, hsize, htrans : std_logic_vector(1 downto 0);
variable p_done : std_logic;
begin
v := r2;
vdmai.start := '0'; vdmai.burst := '0'; vdmai.size := "010";
vdmai.address := r.laddr; v.sync := '1';
vdmai.wdata := ahbdrivedata(r.ldata); vdmai.write := r.pwrite;
v.start(0) := r2.start(csync); v.start(csync) := r.start;
v.hreq(0) := r2.hreq(csync); v.hreq(csync) := r.hreq;
v.pabort(0) := r2.pabort(csync); v.pabort(csync) := r.pabort;
v.preq_ack(0) := r2.preq_ack(csync); v.preq_ack(csync) := r.preq_ack;
hready := '1'; hresp := HRESP_OKAY; request := '0';
hsize := "10"; htrans := "00";
p_done := r2.hreq(0) or r2.pabort(0);
---- *** APB register access *** ----
--if (apbi.psel and apbi.penable and apbi.pwrite) = '1' then
--v.pciba := apbi.pwdata(31 downto 28);
--end if;
--apbo.prdata <= r2.pciba & addzero;
if hr.hiosel = '1' then
if hr.hwrite = '1' then v.pciba := ahbreadword(ahbsi.hwdata)(31 downto 28); end if;
v.hrdata := r2.pciba & addzero(27 downto 0);
end if;
---- *** AHB MASTER *** ----
case r2.m_state is
when idle =>
v.sync := '0';
if r2.start(0) = '1' then
if r.pwrite = '1' then v.m_state := sync1; v.wready := '0';
else v.m_state := busy; vdmai.start := '1'; end if;
end if;
when sync1 =>
if r2.start(0) = '0' then v.m_state := busy; vdmai.start := '1'; end if;
when busy =>
if dmao.active = '1' then
if dmao.ready = '1' then
v.rready := not r.pwrite; v.tdata := dmao.rdata(31 downto 0); v.m_state := sync2;
end if;
else vdmai.start := '1'; end if;
when sync2 =>
if r2.start(0) = '0' then
v.m_state := idle; v.wready := '1'; v.rready := '0';
end if;
end case;
---- *** AHB MASTER END *** ----
---- *** AHB SLAVE *** ----
if MASTER = 1 then
if (hr.hready and hr.hsel) = '1' then
hsize := hr.hsize; htrans := hr.htrans;
if (hr.htrans(1) and r.comm.msen) = '1' then request := '1'; end if;
end if;
if (request = '1' and r2.s_state = idle) then
v.maddr := r2.pciba & hr.haddr;
v.hwrite := hr.hwrite;
case hsize is
when "00" => v.be := "1110"; -- Decode byte enable
when "01" => v.be := "1100";
when "10" => v.be := "0000";
when others => v.be := "1111";
end case;
elsif r2.s_state = getd and r2.hwrite = '1' then
v.mdata := hr.hwdata;
end if;
if r2.hreq(0) = '1' then v.hrdata := r.ldata; end if;
if r2.preq_ack(0) = '1' then v.preq := '0'; end if;
if r2.pabort(0) = '1' then v.perror := '1'; end if;
if p_done = '0' then v.hreq_ack := '0'; end if;
-- AHB slave state machine
case r2.s_state is
when idle => if request = '1' then v.s_state := getd; end if;
when getd => v.s_state := req; v.preq := '1';
when req => if r2.preq_ack(0) = '1' then v.s_state := sync; end if;
when sync => if r2.preq_ack(0) = '0' then v.s_state := read; end if;
when read =>
if p_done = '1' then v.hreq_ack := '1'; v.s_state := sync2; end if;
when sync2 => if p_done = '0' then v.s_state := t_done; end if;
when t_done => if request = '1' then v.s_state := idle; end if;
when others => v.s_state := idle;
end case;
if request = '1' then
if r2.s_state = t_done then
if r2.perror = '1' then hresp := HRESP_ERROR;
else hresp := HRESP_OKAY; end if;
v.perror := '0';
else hresp := HRESP_RETRY; end if;
end if;
if r.comm.msen = '0' then hresp := HRESP_ERROR; end if; -- Master disabled
if htrans(1) = '0' then hresp := HRESP_OKAY; end if; -- Response OK for BUSY and IDLE
if (hresp /= HRESP_OKAY and (hr.hready and hr.hsel) = '1') then -- insert one wait cycle
hready := '0';
end if;
if hr.hready = '0' then hresp := r2.hresp; end if;
v.hresp := hresp;
end if;
---- *** AHB SLAVE END *** ----
if rst = '0' then
v.s_state := idle; v.rready := '0'; v.wready := '1';
v.m_state := idle; v.preq := '0'; v.hreq_ack := '0';
v.perror := '0'; v.be := (others => '1');
v.pciba := (others => '0'); v.hresp := (others => '0');
end if;
r2in <= v; dmai <= vdmai;
ahbso.hready <= hready;
ahbso.hresp <= hresp;
ahbso.hrdata <= ahbdrivedata(r2.hrdata);
end process;
ahbso.hconfig <= hconfig when MASTER = 1 else (others => zero32);
ahbso.hsplit <= (others => '0');
ahbso.hirq <= (others => '0');
ahbso.hindex <= hslvndx;
-- PCI target core (PCI clock domain)
pcicomb : process(pcii.rst, pr, pcii, r, r2, roe_ad)
variable v : pci_reg_type;
variable chit, mhit, hit, ready, cwrite : std_logic;
variable cdata, cwdata : std_logic_vector(31 downto 0);
variable comp : std_logic; -- Last transaction cycle on PCI bus
variable iready : std_logic;
variable mto : std_logic;
variable tad, mad : std_logic_vector(31 downto 0);
-- variable cbe : std_logic_vector(3 downto 0);
variable caddr : std_logic_vector(7 downto 2);
variable voe_ad : std_logic_vector(31 downto 0);
variable oe_par : std_logic;
variable oe_ad : std_logic;
variable oe_ctrl : std_logic;
variable oe_trdy : std_logic;
variable oe_devsel: std_logic;
variable oe_cbe : std_logic;
variable oe_stop : std_logic;
variable oe_frame : std_logic;
variable oe_irdy : std_logic;
variable oe_req : std_logic;
begin
-- Process defaults
v := r; v.trdy := '1'; v.stop := '1'; v.frame := '1';
v.oe_ad := '1'; v.devsel := '1'; v.oe_frame := '1';
v.irdy := '1'; v.req := '1'; voe_ad := roe_ad;
v.oe_req := '0'; v.oe_cbe := '1'; v.oe_irdy := '1';
v.rready(0) := r.rready(csync); v.rready(csync) := r2.rready;
v.wready(0) := r.wready(csync); v.wready(csync) := r2.wready;
v.sync(0) := r.sync(csync); v.sync(csync) := r2.sync;
v.preq(0) := r.preq(csync); v.preq(csync) := r2.preq;
v.hreq_ack(0) := r.hreq_ack(csync); v.hreq_ack(csync) := r2.hreq_ack;
comp := '0'; mto := '0'; tad := r.ad; mad := r.ad; v.stop_req := '0';
--cbe := r.cbe;
----- *** PCI TARGET *** --------
-- address decoding
if (r.t_state = s_data) and ((pr.irdy or r.trdy or r.read) = '0') then
cwrite := r.csel;
if ((r.msel and r.addr(MADDR_WIDTH-1)) = '1') and (pr.cbe = "0000") then
v.page := pr.ad(31 downto MADDR_WIDTH-1);
end if;
if (pr.cbe = "0000") and (r.addr(MADDR_WIDTH-1) = '1') then
end if;
else cwrite := '0'; end if;
cdata := (others => '0'); caddr := r.addr(7 downto 2);
case caddr is
when "000000" => -- 0x00, device & vendor id
cdata := conv_std_logic_vector(DEVICE_ID, 16) &
conv_std_logic_vector(VENDOR_ID, 16);
when "000001" => -- 0x04, status & command
cdata(1) := r.comm.men; cdata(2) := r.comm.msen; cdata(25) := '1';
cdata(28) := r.stat.rta; cdata(29) := r.stat.rma;
when "000010" => -- 0x08, class code & revision
when "000011" => -- 0x0c, latency & cacheline size
when "000100" => -- 0x10, BAR0
cdata(31 downto MADDR_WIDTH) := r.bar0;
when others =>
end case;
cwdata := pr.ad;
if pr.cbe(3) = '1' then cwdata(31 downto 24) := cdata(31 downto 24); end if;
if pr.cbe(2) = '1' then cwdata(23 downto 16) := cdata(23 downto 16); end if;
if pr.cbe(1) = '1' then cwdata(15 downto 8) := cdata(15 downto 8); end if;
if pr.cbe(0) = '1' then cwdata( 7 downto 0) := cdata( 7 downto 0); end if;
if cwrite = '1' then
case caddr is
when "000001" => -- 0x04, status & command
v.comm.men := cwdata(1);
v.comm.msen := cwdata(2);
v.stat.rta := r.stat.rta and not cwdata(28);
v.stat.rma := r.stat.rma and not cwdata(29);
when "000100" => -- 0x10, BAR0
v.bar0 := cwdata(31 downto MADDR_WIDTH);
when others =>
end case;
end if;
if (((pr.cbe = pci_config_read) or (pr.cbe = pci_config_write))
and (pr.ad(1 downto 0) = "00"))
then chit := '1'; else chit := '0'; end if;
if ((pr.cbe = pci_memory_read) or (pr.cbe = pci_memory_write))
and (r.bar0 = pr.ad(31 downto MADDR_WIDTH))
and (r.bar0 /= zero(31 downto MADDR_WIDTH))
then mhit := '1'; else mhit := '0'; end if;
hit := r.csel or r.msel;
ready := r.csel or (r.rready(0) and r.read) or (r.wready(0) and not r.read and not r.start) or
r.addr(MADDR_WIDTH-1);
-- target state machine
case r.t_state is
when idle =>
if pr.frame = '0' then v.t_state := b_busy; end if; -- !HIT ?
v.addr := pr.ad(MADDR_WIDTH-1 downto 0); -- v.cbe := pr.cbe;
v.csel := pr.idsel and chit;
v.msel := r.comm.men and mhit; v.read := not pr.cbe(0);
if (r.sync(0) and r.start and r.pwrite) = '1' then v.start := '0'; end if;
when turn_ar =>
if pr.frame = '1' then v.t_state := idle; end if;
if pr.frame = '0' then v.t_state := b_busy; end if; -- !HIT ?
v.addr := pr.ad(MADDR_WIDTH-1 downto 0); -- v.cbe := pr.cbe;
v.csel := pr.idsel and chit;
v.msel := r.comm.men and mhit; v.read := not pr.cbe(0);
if (r.sync(0) and r.start and r.pwrite) = '1' then v.start := '0'; end if;
when b_busy =>
if hit = '1' then
v.t_state := s_data; v.trdy := not ready; v.stop := pr.frame and ready;
v.devsel := '0';
else
v.t_state := backoff;
end if;
when s_data =>
v.stop := r.stop; v.devsel := '0';
v.trdy := r.trdy or not pcii.irdy;
if (pcii.frame and not pcii.irdy) = '1' then
v.t_state := turn_ar; v.stop := '1'; v.trdy := '1'; v.devsel := '1';
end if;
when backoff =>
if pr.frame = '1' then v.t_state := idle; end if;
end case;
if ((r.t_state = s_data) or (r.t_state = turn_ar)) and
(((pr.irdy or pr.trdy) = '0') or
((not pr.irdy and not pr.stop and pr.trdy and not r.start and r.wready(0)) = '1'))
then
if (pr.trdy and r.read)= '0' then v.start := '0'; end if;
if (r.start = '0') and ((r.msel and not r.addr(MADDR_WIDTH-1)) = '1') and
(((pr.trdy and r.read and not r.rready(0)) or (not pr.trdy and not r.read)) = '1')
then
v.laddr := r.page & r.addr(MADDR_WIDTH-2 downto 0);
v.ldata := pr.ad; v.pwrite := not r.read; v.start := '1';
end if;
end if;
-- if (v.t_state = s_data) and (r.read = '1') then v.oe_ad := '0'; end if;
-- v.oe_par := r.oe_ad;
if r.csel = '1' then tad := cdata;
elsif r.addr(MADDR_WIDTH-1) = '1' then
tad(31 downto MADDR_WIDTH-1) := r.page;
tad(MADDR_WIDTH-2 downto 0) := (others => '0');
else tad := r2.tdata; end if;
if (v.t_state = s_data) or (r.t_state = s_data) then
v.oe_ctrl := '0';
else v.oe_ctrl := '1'; end if;
----- *** PCI TARGET END*** --------
----- *** PCI MASTER *** --------
if MASTER = 1 then
if r.preq(0) = '1' then
if (r.m_state = idle or r.m_state = dr_bus) and r.request = '0' and r.hreq = '0' then
v.request := '1';
v.hwrite := r2.hwrite;
v.lcbe := r2.be;
v.mdata := r2.mdata;
v.maddr :=r2.maddr;
end if;
end if;
if r.hreq_ack(0) = '1' then v.hreq := '0'; v.pabort := '0'; end if;
if r.preq(0) = '0' then v.preq_ack := '0'; end if;
comp := not(pcii.trdy or pcii.irdy);
if ((pr.irdy and not pr.frame) or (pr.devsel and r.frame and not r.oe_frame)) = '1' then -- Covers both master timeout and devsel timeout
if r.mcnt /= "000" then v.mcnt := r.mcnt - 1;
else mto := '1'; end if;
else v.mcnt := (others => '1'); end if;
-- PCI master state machine
case r.m_state is
when idle => -- Master idle
if (pr.gnt = '0' and (pr.frame and pr.irdy) = '1') then
if r.request = '1' then v.m_state := addr; v.preq_ack := '1';
else v.m_state := dr_bus; end if;
end if;
when addr => -- Always one address cycle at the beginning of an transaction
v.m_state := m_data;
when m_data => -- Master transfers data
--if (r.request and not pr.gnt and pr.frame and not pr.trdy -- Not supporting address stepping!
--and pr.stop and l_cycle and sa) = '1' then
--v.m_state <= addr;
v.hreq := comp;
if (pr.frame = '0') or ((pr.frame and pcii.trdy and pcii.stop and not mto) = '1') then
v.m_state := m_data;
elsif ((pr.frame and (mto or not pcii.stop)) = '1') then
v.m_state := s_tar;
else v.m_state := turn_ar; v.request := '0'; end if;
when turn_ar => -- Transaction complete
if (r.request and not pr.gnt) = '1' then v.m_state := addr;
elsif (r.request or pr.gnt) = '0' then v.m_state := dr_bus;
else v.m_state := idle; end if;
when s_tar => -- Stop was asserted
v.request := pr.trdy and not pr.stop and not pr.devsel;
v.stop_req := '1';
if (pr.stop or pr.devsel or pr.trdy) = '0' then -- Disconnect with data
v.m_state := turn_ar;
elsif pr.gnt = '0' then
v.pabort := not v.request;
v.m_state := dr_bus;
else v.m_state := idle; v.pabort := not v.request; end if;
when dr_bus => -- Drive bus when parked on this agent
if (r.request = '1' and (pcii.gnt or r.req) = '0') then v.m_state := addr; v.preq_ack := '1';
elsif pcii.gnt = '1' then v.m_state := idle; end if;
end case;
if v.m_state = addr then mad := r.maddr; else mad := r.mdata; end if;
if (pr.irdy or pr.trdy or r.hwrite) = '0' then v.ldata := pr.ad; end if;
-- Target abort
if ((pr.devsel and pr.trdy and not pr.gnt and not pr.stop) = '1') then v.stat.rta := '1'; end if;
-- Master abort
if mto = '1' then v.stat.rma := '1'; end if;
-- Drive FRAME# and IRDY#
if (v.m_state = addr or v.m_state = m_data) then v.oe_frame := '0'; end if;
-- Drive CBE#
if (v.m_state = addr or v.m_state = m_data or v.m_state = dr_bus) then v.oe_cbe := '0'; end if;
-- Drive IRDY# (FRAME# delayed one pciclk)
v.oe_irdy := r.oe_frame;
-- FRAME# assert
if v.m_state = addr then v.frame := '0'; end if; -- Only single transfers valid
-- IRDY# assert
if v.m_state = m_data then v.irdy := '0'; end if;
-- REQ# assert
if (v.request = '1' and (v.m_state = idle or r.m_state = idle) and (v.stop_req or r.stop_req) = '0') then v.req := '0'; end if;
-- C/BE# assert
if v.m_state = addr then v.cbe := "011" & r.hwrite; else v.cbe := r.lcbe; end if;
end if;
----- *** PCI MASTER END *** --------
----- *** SHARED BUS SIGNALS *** -------
-- Drive PAR
v.oe_par := r.oe_ad; --Delayed one clock
v.par := xorv(r.ad & r.cbe); -- Default asserted by master
v.ad := mad; -- Default asserted by master
-- Master
if (v.m_state = addr or (v.m_state = m_data and r.hwrite = '1') or v.m_state = dr_bus) then
v.oe_ad := '0';
end if;
-- Drive AD
-- Target
if r.read = '1' then
if v.t_state = s_data then
v.oe_ad := '0';
v.ad := tad;
elsif r.t_state = s_data then
v.par := xorv(r.ad & pcii.cbe);
end if;
end if;
v.oe_stop := v.oe_ctrl; v.oe_devsel := v.oe_ctrl; v.oe_trdy := v.oe_ctrl;
v.noe_ad := not v.oe_ad; v.noe_ctrl := not v.oe_ctrl;
v.noe_par := not v.oe_par; v.noe_req := not v.oe_req;
v.noe_frame := not v.oe_frame; v.noe_cbe := not v.oe_cbe;
v.noe_irdy := not v.oe_irdy;
v.noe_stop := not v.oe_ctrl; v.noe_devsel := not v.oe_ctrl;
v.noe_trdy := not v.oe_ctrl;
if oepol = 0 then
voe_ad := (others => v.oe_ad);
oe_ad := r.oe_ad; oe_ctrl := r.oe_ctrl; oe_par := r.oe_par;
oe_req := r.oe_req; oe_frame := r.oe_frame; oe_cbe := r.oe_cbe;
oe_irdy := r.oe_irdy; oe_stop := r.oe_stop; oe_trdy := r.oe_trdy;
oe_devsel := r.oe_devsel;
else
voe_ad := (others => v.noe_ad);
oe_ad := r.noe_ad; oe_ctrl := r.noe_ctrl; oe_par := r.noe_par;
oe_req := r.noe_req; oe_frame := r.noe_frame; oe_cbe := r.noe_cbe;
oe_irdy := r.noe_irdy; oe_stop := r.noe_stop; oe_trdy := r.noe_trdy;
oe_devsel := r.noe_devsel;
end if;
----- *** SHARED BUS SIGNALS END *** -------
if pr.rst = '0' then
v.t_state := idle; v.m_state := idle; v.comm.men := '0'; v.start := '0';
v.bar0 := (others => '0'); v.msel := '0'; v.csel := '0';
v.page := (others => '0'); v.page(31 downto 30) := "01"; v.par := '0';
v.hwrite := '0'; v.request := '0'; v.comm.msen := '0';
v.laddr := (others => '0'); v.ldata := (others => '0');
v.hreq := '0'; v.preq_ack := '0'; v.pabort := '0';
v.mcnt := (others => '1'); v.maddr := (others => '0');
v.lcbe := (others => '0'); v.mdata := (others => '0');
v.pwrite := '0'; v.stop_req := '0';
v.stat.rta := '0'; v.stat.rma := '0';
end if;
rin <= v;
rioe_ad <= voe_ad;
pcio.reqen <= oe_req;
pcio.req <= r.req;
pcio.frameen <= oe_frame;
pcio.frame <= r.frame;
pcio.irdyen <= oe_irdy;
pcio.irdy <= r.irdy;
pcio.cbeen <= (others => oe_cbe);
pcio.cbe <= r.cbe;
pcio.vaden <= roe_ad;
pcio.aden <= oe_ad;
pcio.ad <= r.ad;
pcio.trdy <= r.trdy;
pcio.ctrlen <= oe_ctrl;
pcio.trdyen <= oe_trdy;
pcio.devselen <= oe_devsel;
pcio.stopen <= oe_stop;
pcio.stop <= r.stop;
pcio.devsel <= r.devsel;
pcio.par <= r.par;
pcio.paren <= oe_par;
pcio.rst <= '1';
end process;
pcir : process (pciclk, pcii.rst)
begin
if rising_edge (pciclk) then
pr.ad <= to_x01(pcii.ad);
pr.cbe <= to_x01(pcii.cbe);
pr.devsel <= to_x01(pcii.devsel);
pr.frame <= to_x01(pcii.frame);
pr.idsel <= to_x01(pcii.idsel);
pr.irdy <= to_x01(pcii.irdy);
pr.trdy <= to_x01(pcii.trdy);
pr.par <= to_x01(pcii.par);
pr.stop <= to_x01(pcii.stop);
pr.rst <= to_x01(pcii.rst);
pr.gnt <= to_x01(pcii.gnt);
r <= rin;
roe_ad <= rioe_ad;
end if;
if pcii.rst = '0' then -- asynch reset required
r.oe_ad <= '1'; r.oe_ctrl <= '1'; r.oe_par <= '1'; r.oe_stop <= '1';
r.oe_req <= '1'; r.oe_frame <= '1'; r.oe_cbe <= '1'; r.oe_irdy <= '1';
r.oe_trdy <= '1'; r.oe_devsel <= '1';
r.noe_ad <= '0'; r.noe_ctrl <= '0'; r.noe_par <= '0'; r.noe_req <= '0';
r.noe_frame <= '0'; r.noe_cbe <= '0'; r.noe_irdy <= '0'; r.noe_stop <= '0';
r.noe_trdy <= '0'; r.noe_devsel <= '0';
if oepol = 0 then roe_ad <= (others => '1');
else roe_ad <= (others => '0'); end if;
end if;
end process;
cpur : process (rst,clk)
begin
if rising_edge (clk) then
hr.haddr <= ahbsi.haddr(HADDR_WIDTH - 1 downto 0);
hr.htrans <= ahbsi.htrans;
hr.hwrite <= ahbsi.hwrite;
hr.hsize <= ahbsi.hsize(1 downto 0);
hr.hburst <= ahbsi.hburst;
hr.hwdata <= ahbreadword(ahbsi.hwdata);
hr.hsel <= ahbsi.hsel(hslvndx) and ahbsi.hmbsel(0);
hr.hiosel <= ahbsi.hsel(hslvndx) and ahbsi.hmbsel(1);
hr.hready <= ahbsi.hready;
r2 <= r2in;
end if;
end process;
oe0 : if oepol = 0 generate
pcio.perren <= '1';
pcio.serren <= '1';
pcio.inten <= '1';
pcio.vinten <= (others => '1');
pcio.locken <= '1';
end generate;
oe1 : if oepol = 1 generate
pcio.perren <= '0';
pcio.serren <= '0';
pcio.inten <= '0';
pcio.vinten <= (others => '0');
pcio.locken <= '0';
end generate;
pcio.perr <= '1';
pcio.serr <= '1';
pcio.int <= '1';
msttgt : if MASTER = 1 generate
ahbmst0 : ahbmst generic map (hindex => hmstndx, devid => GAISLER_PCISBRG)
port map (rst, clk, dmai, dmao, ahbmi, ahbmo);
-- pragma translate_off
bootmsg : report_version
generic map ("pci_mt" & tost(hslvndx) &
": Simple 32-bit PCI Bridge, rev " & tost(REVISION) &
", " & tost(2**abits/2**20) & " Mbyte PCI memory BAR" );
-- pragma translate_on
end generate;
tgtonly : if MASTER = 0 generate
ahbmst0 : ahbmst generic map (hindex => hmstndx, devid => GAISLER_PCITRG)
port map (rst, clk, dmai, dmao, ahbmi, ahbmo);
-- pragma translate_off
bootmsg : report_version
generic map ("pci_mt" & tost(hmstndx) &
": Simple 32-bit Bridge, target-only, rev " & tost(REVISION) &
", " & tost(2**abits/2**20) & " Mbyte PCI memory BAR" );
-- pragma translate_on
end generate;
end;
|
-------------------------------------------------------------------------------
-- $Id: or_gate.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- or_gate.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2001-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: or_gate.vhd
-- Version: v1.00a
-- Description: OR gate implementation
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- or_gate.vhd
--
-------------------------------------------------------------------------------
-- Author: B.L. Tise
-- History:
-- BLT 2001-05-23 First Version
-- ^^^^^^
-- First version of OPB Bus.
-- ~~~~~~
--
-- DET 1/17/2008 v3_00_a
-- ~~~~~~
-- - Changed proc_common library version to v3_00_a
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.all;
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_OR_WIDTH -- Which Xilinx FPGA family to target when
-- syntesizing, affect the RLOC string values
-- C_BUS_WIDTH -- Which Y position the RLOC should start from
--
-- Definition of Ports:
-- A -- Input. Input buses are concatenated together to
-- form input A. Example: to OR buses R, S, and T,
-- assign A <= R & S & T;
-- Y -- Output. Same width as input buses.
--
-------------------------------------------------------------------------------
entity or_gate is
generic (
C_OR_WIDTH : natural range 1 to 32 := 17;
C_BUS_WIDTH : natural range 1 to 64 := 1;
C_USE_LUT_OR : boolean := TRUE
);
port (
A : in std_logic_vector(0 to C_OR_WIDTH*C_BUS_WIDTH-1);
Y : out std_logic_vector(0 to C_BUS_WIDTH-1)
);
end entity or_gate;
architecture imp of or_gate is
-------------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------------
component or_muxcy
generic (
C_NUM_BITS : integer := 8
);
port (
In_bus : in std_logic_vector(0 to C_NUM_BITS-1);
Or_out : out std_logic
);
end component or_muxcy;
signal test : std_logic_vector(0 to C_BUS_WIDTH-1);
-------------------------------------------------------------------------------
-- Begin architecture
-------------------------------------------------------------------------------
begin
USE_LUT_OR_GEN: if C_USE_LUT_OR generate
OR_PROCESS: process( A ) is
variable yi : std_logic_vector(0 to (C_OR_WIDTH));
begin
for j in 0 to C_BUS_WIDTH-1 loop
yi(0) := '0';
for i in 0 to C_OR_WIDTH-1 loop
yi(i+1) := yi(i) or A(i*C_BUS_WIDTH+j);
end loop;
Y(j) <= yi(C_OR_WIDTH);
end loop;
end process OR_PROCESS;
end generate USE_LUT_OR_GEN;
USE_MUXCY_OR_GEN: if not C_USE_LUT_OR generate
BUS_WIDTH_FOR_GEN: for i in 0 to C_BUS_WIDTH-1 generate
signal in_Bus : std_logic_vector(0 to C_OR_WIDTH-1);
begin
ORDER_INPUT_BUS_PROCESS: process( A ) is
begin
for k in 0 to C_OR_WIDTH-1 loop
in_Bus(k) <= A(k*C_BUS_WIDTH+i);
end loop;
end process ORDER_INPUT_BUS_PROCESS;
OR_BITS_I: or_muxcy
generic map (
C_NUM_BITS => C_OR_WIDTH
)
port map (
In_bus => in_Bus, --[in]
Or_out => Y(i) --[out]
);
end generate BUS_WIDTH_FOR_GEN;
end generate USE_MUXCY_OR_GEN;
end architecture imp;
|
-----------------------------------------------------------------
-- Project : Invent a Chip
-- Module : ADC Model
-- Last update : 27.04.2015
-----------------------------------------------------------------
-- Libraries
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library std;
use std.textio.all;
entity adc_model is
generic(
SYSTEM_CYCLE_TIME : time := 20 ns; -- 50 MHz
FULL_DEBUG : natural := 0;
FILE_NAME_PRELOAD : string := "adc_preload.txt"
);
port(
-- Global Signals
end_simulation : in std_ulogic;
-- SPI Signals
spi_clk : in std_ulogic;
spi_miso : out std_logic;
spi_cs_n : in std_ulogic;
-- Switch Signals
swt_select : in std_ulogic_vector(2 downto 0);
swt_enable_n : in std_ulogic
);
end entity adc_model;
architecture sim of adc_model is
file file_preload : text open read_mode is FILE_NAME_PRELOAD;
type adc_reg_t is array (0 to 7) of std_ulogic_vector(15 downto 0);
signal tx : std_ulogic_vector(15 downto 0);
signal swt_sel_lut : std_ulogic_vector(2 downto 0);
begin
process
variable adc_reg : adc_reg_t;
variable active_line, out_line : line;
variable cnt : natural := 0;
variable neol : boolean := false;
variable adc_val : real := 0.000;
begin
adc_reg := (others => (others => 'U'));
tx <= (others => 'U');
-- force wait for 1 ps to display full-debug messages after library warnings
if FULL_DEBUG = 1 then
wait for 1 ps;
end if;
-- preload data from adc file here...
while not endfile(file_preload) loop
readline(file_preload, active_line);
loop
read(active_line, adc_val, neol);
exit when not neol;
exit when cnt = 8;
adc_reg(cnt) := std_ulogic_vector(to_unsigned(integer(adc_val*real(4096)/real(3.3)), tx'length));
-- display read values from file
if FULL_DEBUG = 1 then
write(out_line, "[ADC] Preloading channel " & integer'image(cnt) & " with ");
write(out_line, adc_val, right, 3, 3);
write(out_line, 'V');
writeline(output, out_line);
end if;
cnt := cnt + 1;
end loop;
exit when cnt = 8;
end loop;
file_close(file_preload);
-- display unassigned channels
if FULL_DEBUG = 1 then
if cnt < 8 then
for i in cnt to 7 loop
write(out_line, "[ADC] Channel " & integer'image(i) & " is unassigned!");
writeline(output, out_line);
end loop;
end if;
end if;
-- do real work (send adc-values by request)
loop
exit when end_simulation = '1';
if spi_cs_n = '0' then
if swt_enable_n = '0' then
-- data has to be sent out shifted one bit to the left (as in actual chip)
tx <= adc_reg(to_integer(unsigned(swt_sel_lut)))(14 downto 0) & '0';
else
tx <= (others => 'U');
end if;
for i in 0 to 15 loop
wait until spi_clk = '1';
wait until spi_clk = '0';
tx <= tx(14 downto 0) & '0';
end loop;
wait until spi_cs_n = '1';
else
wait for SYSTEM_CYCLE_TIME;
end if;
end loop;
wait;
end process;
spi_miso <= '0' when tx(15) = '0' AND spi_cs_n = '0' else 'Z';
-- lut to map swt_select to correct register content (inverse to interface)
process(swt_select)
variable sel : natural;
begin
sel := to_integer(unsigned(swt_select));
case sel is
when 0 => swt_sel_lut <= std_ulogic_vector(to_unsigned(5, swt_sel_lut'length));
when 1 => swt_sel_lut <= std_ulogic_vector(to_unsigned(3, swt_sel_lut'length));
when 2 => swt_sel_lut <= std_ulogic_vector(to_unsigned(1, swt_sel_lut'length));
when 3 => swt_sel_lut <= std_ulogic_vector(to_unsigned(7, swt_sel_lut'length));
when 4 => swt_sel_lut <= std_ulogic_vector(to_unsigned(6, swt_sel_lut'length));
when 5 => swt_sel_lut <= std_ulogic_vector(to_unsigned(2, swt_sel_lut'length));
when 6 => swt_sel_lut <= std_ulogic_vector(to_unsigned(4, swt_sel_lut'length));
when 7 => swt_sel_lut <= std_ulogic_vector(to_unsigned(0, swt_sel_lut'length));
when others => swt_sel_lut <= std_ulogic_vector(to_unsigned(5, swt_sel_lut'length));
end case;
end process;
end architecture sim; |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc553.vhd,v 1.2 2001-10-26 16:30:26 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s04b00x00p03n05i00553ent IS
END c03s04b00x00p03n05i00553ent;
ARCHITECTURE c03s04b00x00p03n05i00553arch OF c03s04b00x00p03n05i00553ent IS
type TM is -- unconstrained array decl
array (Integer range <>, Integer range <>) of Integer;
type FT is -- file decl
file of TM; -- Failure_here
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c03s04b00x00p03n05i00553 - A file may not be declared to contain multi dimensional arrays."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s04b00x00p03n05i00553arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc553.vhd,v 1.2 2001-10-26 16:30:26 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s04b00x00p03n05i00553ent IS
END c03s04b00x00p03n05i00553ent;
ARCHITECTURE c03s04b00x00p03n05i00553arch OF c03s04b00x00p03n05i00553ent IS
type TM is -- unconstrained array decl
array (Integer range <>, Integer range <>) of Integer;
type FT is -- file decl
file of TM; -- Failure_here
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c03s04b00x00p03n05i00553 - A file may not be declared to contain multi dimensional arrays."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s04b00x00p03n05i00553arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc553.vhd,v 1.2 2001-10-26 16:30:26 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s04b00x00p03n05i00553ent IS
END c03s04b00x00p03n05i00553ent;
ARCHITECTURE c03s04b00x00p03n05i00553arch OF c03s04b00x00p03n05i00553ent IS
type TM is -- unconstrained array decl
array (Integer range <>, Integer range <>) of Integer;
type FT is -- file decl
file of TM; -- Failure_here
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c03s04b00x00p03n05i00553 - A file may not be declared to contain multi dimensional arrays."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s04b00x00p03n05i00553arch;
|
--Copyright 2014 by Emmanuel D. Bello <[email protected]>
--Laboratorio de Computacion Reconfigurable (LCR)
--Universidad Tecnologica Nacional
--Facultad Regional Mendoza
--Argentina
--This file is part of FREAK-on-FPGA.
--FREAK-on-FPGA is free software: you can redistribute it and/or modify
--it under the terms of the GNU General Public License as published by
--the Free Software Foundation, either version 3 of the License, or
--(at your option) any later version.
--FREAK-on-FPGA is distributed in the hope that it will be useful,
--but WITHOUT ANY WARRANTY; without even the implied warranty of
--MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
--GNU General Public License for more details.
--You should have received a copy of the GNU General Public License
--along with FREAK-on-FPGA. If not, see <http://www.gnu.org/licenses/>.
--------------------------------------------------------------------------------
-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version : 14.6
-- \ \ Application :
-- / / Filename : xil_3coJ3K
-- /___/ /\ Timestamp : 04/06/2014 00:34:14
-- \ \ / \
-- \___\/\___\
--
--Command:
--Design Name:
--
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
--library UNISIM;
--use UNISIM.Vcomponents.ALL;
use work.RetinaParameters.ALL;
entity TopDescriptorMaker is
port ( clk : in std_logic;
rst : in std_logic;
enableIn : in std_logic;
inputValue : in std_logic_vector (OUT_HORIZ_CONV_BW-1 downto 0);
descriptor : out std_logic_vector (DESCRIPTOR_SIZE-1 downto 0);
enableOut : out std_logic
);
end TopDescriptorMaker;
architecture BEHAVIORAL of TopDescriptorMaker is
signal sPointSet: T_POINT_SET;
signal sEnableOutPBuff: std_logic := '0';
signal addr: std_logic_vector(4 downto 0);
signal points1: T_POINT_INDEX;
signal points2: T_POINT_INDEX;
component ROM_PAIRS
port(
clk : in std_logic;
addr : in std_logic_vector(4 downto 0);
points1 : out T_POINT_INDEX;
points2 : out T_POINT_INDEX
);
end component;
component PointBuffer is
port ( clk : in std_logic;
enableIn : in std_logic;
inputValue : in std_logic_vector (OUT_HORIZ_CONV_BW-1 downto 0);
rst : in std_logic;
enableOut : out std_logic;
pointSet : out T_POINT_SET
);
end component;
component DescriptorMaker is
port ( clk : in std_logic;
rst : in std_logic;
pointIndexs1: in T_POINT_INDEX;
pointIndexs2: in T_POINT_INDEX;
enableInPointSet : in std_logic;
pointSet : in T_POINT_SET;
descriptor : out std_logic_vector (DESCRIPTOR_SIZE-1 downto 0);
enableOut : out std_logic
);
end component;
begin
--mapping
rom: ROM_PAIRS
port map(
clk => clk,
addr => addr,
points1 => points1,
points2 => points2
);
pointBufferX: PointBuffer
port map( clk => clk,
enableIn => enableIn,
inputValue => inputValue,
rst => rst,
enableOut => sEnableOutPBuff,
pointSet => sPointSet
);
descripMakerX: DescriptorMaker
port map( clk => clk,
rst => rst,
pointIndexs1 => points1,
pointIndexs2 => points2,
enableInPointSet => sEnableOutPBuff,
pointSet => sPointSet,
descriptor => descriptor,
enableOut => enableOut
);
loadPointIndexes: process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
addr <= (others => '0');
else
if sEnableOutPBuff = '1' then
addr <= "00001";
elsif addr = "11111" then
addr <= (others => '0');
else
addr <= std_logic_vector(resize(unsigned(addr)+1,addr'length));
end if;
end if;
end if;
end process;
end BEHAVIORAL;
|
architecture RTl of FIFO is
component fifo is
port (
a : in std_logic
);
end component fifo;
-- Failures below
component fifo is
port (
a : in std_logic
);
end component fifo;
component fifo is
port (
a : in std_logic
);
end component fifo;
begin
end architecture RTL;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_06_srff.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
library ieee; use ieee.std_logic_1164.all;
entity synch_sr_ff is
port ( clk : in std_ulogic;
set, clr : in std_ulogic;
q : out std_ulogic );
end entity synch_sr_ff;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_06_srff.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
library ieee; use ieee.std_logic_1164.all;
entity synch_sr_ff is
port ( clk : in std_ulogic;
set, clr : in std_ulogic;
q : out std_ulogic );
end entity synch_sr_ff;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_06_srff.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
library ieee; use ieee.std_logic_1164.all;
entity synch_sr_ff is
port ( clk : in std_ulogic;
set, clr : in std_ulogic;
q : out std_ulogic );
end entity synch_sr_ff;
|
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity testbench is
end testbench;
architecture final_testbench of testbench is
component project2
port (
clock : in std_logic;
reset : in std_logic;
valid : in std_logic;
hold_me : in std_logic;
data_in : in std_logic_vector (7 downto 0);
data_out : out std_logic_vector (18 downto 0);
hold_prev : out std_logic
);
end component project2;
signal clock : std_logic := '0';
signal reset : std_logic := '1';
signal valid : std_logic := '0';
signal datain : std_logic_vector (7 downto 0);
signal dataout : std_logic_vector (18 downto 0);
signal hold_me : std_logic;
signal hold_prev:std_logic;
begin
--MAP TO COMPONENT
project_map : project2 port map ( clock => clock,
reset => reset,
valid => valid,
hold_me => hold_me,
data_in => datain,
data_out => dataout,
hold_prev => hold_prev
);
--SET CLOCK PERIOD
process
begin
clock <= '1';
wait for 1 ns;
clock <='0';
wait for 1 ns;
end process;
--STARTING WITH RESET
process
begin
reset <= '1';
wait for 8 ns;
reset <= '0';
wait for 188 ns;
reset <= '1';
wait for 10 ns;
reset <= '0';
wait;
end process;
--INITIALIZE THE INPUT AND SEND IT
process
begin
hold_me <= '0';
wait for 12 ns;
datain <= "10000000";
valid <= '1';
wait for 2 ns;
valid <='0';
wait for 2 ns;
datain <= "10000000";
valid <= '1';
wait for 2 ns;
valid <='0';
wait for 2 ns;
datain <= "10000000";
valid <= '1';
wait for 2 ns;
valid <='0';
wait for 2 ns;
datain <= "10000000";
valid <= '1';
wait for 2 ns;
valid <='0';
wait for 2 ns;
datain <= "10000000";
valid <= '1';
wait for 2 ns;
valid <='0';
wait for 2 ns;
datain <= "10000000";
valid <= '1';
wait for 2 ns;
valid <='0';
wait for 2 ns;
datain <= "10000000";
valid <= '1';
wait for 2 ns;
valid <='0';
wait for 2 ns;
datain <= "10000000";
valid <= '1';
wait for 2 ns;
valid <='0';
--------------------------------------------
--2nd vector
wait for 170 ns;
datain <= "01111111";
valid <= '1';
wait for 2 ns;
valid <='0';
wait for 2 ns;
datain <= "01111111";
valid <= '1';
wait for 2 ns;
valid <='0';
wait for 2 ns;
datain <= "01111111";
valid <= '1';
wait for 2 ns;
valid <='0';
wait for 2 ns;
datain <= "01111111";
valid <= '1';
wait for 2 ns;
valid <='0';
wait for 2 ns;
datain <= "01111111";
valid <= '1';
wait for 2 ns;
valid <='0';
wait for 2 ns;
datain <= "01111111";
valid <= '1';
wait for 2 ns;
valid <='0';
wait for 2 ns;
datain <= "01111111";
valid <= '1';
wait for 2 ns;
valid <='0';
wait for 2 ns;
datain <= "01111111";
valid <= '1';
wait for 2 ns;
valid <='0';
wait for 170 ns;
valid <= '1';
datain <= "01010101";
wait for 2 ns;
valid <= '0';
--TELOS
wait;
end process;
end architecture final_testbench;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 07.11.2012 05:36:01
-- Design Name:
-- Module Name: cam_pkg - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
--use IEEE.STD_LOGIC_UNSIGNED.ALL;
--use ieee.std_logic_arith.all;
package CAM_PKG is
constant Image_Width : positive := 480;
constant Image_Hight : positive := 640;
constant bytes_per_px : positive := 3;
subtype int8u is integer range 0 to 255;
type RGB_COLOR is record
r : integer range 0 TO 255;
g : integer range 0 TO 255;
b : integer range 0 TO 255;
end record;
type pixel_position is record
x : integer range 1 TO Image_Width;
y : integer range 1 TO Image_Hight;
end record;
type pixel is record
pos : pixel_position;
color : RGB_COLOR;
end record;
type sensor is record
pos : pixel_position;
color : RGB_COLOR;
max_pos : integer range 0 to 31;
min_pos : integer range 0 to 31;
end record;
subtype sensor_vector is std_logic_vector(63 downto 0);
type positions_array is array (31 downto 0) of pixel_position;
type color_array is array (31 downto 0) of RGB_COLOR;
type shift_position is array (16 downto 0) of integer range 0 to 8; --- FIXME größe 3 bit
function log2(n : natural) return natural;
function middle_value(v1 : in RGB_COLOR; v2 : in RGB_COLOR) return RGB_COLOR;
function color_distance(Pixel0 : in RGB_COLOR; Pixel1 : in RGB_COLOR) return integer;
function sensor2vector(sensor_t : sensor) return sensor_vector;
function vector2sensor(slv : sensor_vector) return sensor;
function or_reduct(slv : in std_logic_vector) return std_logic;
end package CAM_PKG;
package body CAM_PKG is
-----------------------------------------------------------------------------
function log2(n : natural) return natural is
begin
for i in 0 to 31 loop
if (2 ** i) >= n then
return i;
end if;
end loop;
return 32;
end log2;
function middle_value(v1 : in RGB_COLOR; v2 : in RGB_COLOR) return RGB_COLOR is
variable r : RGB_COLOR;
begin
r.r := (v1.r + v2.r)/2;
r.g := (v1.g + v2.g)/2;
r.b := (v1.b + v2.b)/2;
return r;
end function middle_value;
function color_distance(Pixel0 : in RGB_COLOR; Pixel1 : in RGB_COLOR) return integer is
begin
return (((Pixel0.r + Pixel0.g + Pixel0.b) - (Pixel1.r + Pixel1.g + Pixel1.b)));
end function color_distance;
function sensor2vector(sensor_t : sensor) return sensor_vector is
variable slv : sensor_vector;
begin
slv(63 downto 52) := std_logic_vector(to_unsigned(sensor_t.pos.x, 12));
slv(51 downto 40) := std_logic_vector(to_unsigned(sensor_t.pos.y, 12));
slv(39 downto 32) := std_logic_vector(to_unsigned(sensor_t.color.r, 8));
slv(31 downto 24) := std_logic_vector(to_unsigned(sensor_t.color.g, 8));
slv(23 downto 16) := std_logic_vector(to_unsigned(sensor_t.color.b, 8));
slv(15 downto 8) := std_logic_vector(to_signed(sensor_t.max_pos, 8));
slv(7 downto 0) := std_logic_vector(to_signed(sensor_t.min_pos, 8));
return slv;
end;
function vector2sensor(slv : sensor_vector) return sensor is
variable sensor_t : sensor;
begin
sensor_t.pos.x := to_integer(unsigned(slv(63 downto 52))); -- FIXME prüfen ob richtig funktioniert
sensor_t.pos.y := to_integer(unsigned(slv(51 downto 40)));
sensor_t.color.r := to_integer(unsigned(slv(39 downto 32)));
sensor_t.color.r := to_integer(unsigned(slv(31 downto 24)));
sensor_t.color.r := to_integer(unsigned(slv(23 downto 16)));
sensor_t.max_pos := to_integer(signed(slv(15 downto 08)));
sensor_t.min_pos := to_integer(signed(slv(07 downto 00)));
return sensor_t;
end;
function or_reduct(slv : in std_logic_vector) return std_logic is
variable res_v : std_logic;
begin
res_v := '0';
for i in slv'range loop
res_v := res_v or slv(i);
end loop;
return res_v;
end function;
--ENTITY orn IS
--GENERIC (n : INTEGER := 4);
--PORT (x : IN STD_LOGIC_VECTOR(1 TO n);
--f : OUT STD_LOGIC);
--END orn;
--
--ARCHITECTURE dataflow OF orn IS
--SIGNAL tmp : STD_LOGIC_VECTOR(1 TO n);
--BEGIN
--tmp <= (OTHERS => '0');
--f <= '0' WHEN x = tmp ELSE '1';
--END dataflow;
end package body CAM_PKG;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc370.vhd,v 1.2 2001-10-26 16:30:26 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s02b01x01p03n02i00370ent IS
END c03s02b01x01p03n02i00370ent;
ARCHITECTURE c03s02b01x01p03n02i00370arch OF c03s02b01x01p03n02i00370ent IS
subtype BFALSE is BOOLEAN range FALSE to FALSE;
type ONETWO is range 1 to 2;
type A3 is array (1 to 2,
ONETWO range <>) of BFALSE; -- Failure_here
-- ERROR - SYNTAX ERROR: CONSTRAINED AND UNCONSTRAINED INDEX RANGES
-- CANNOT BE MIXED
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c03s02b01x01p03n02i00370 - Unconstrained and constrained index ranges cannot be mixed."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x01p03n02i00370arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc370.vhd,v 1.2 2001-10-26 16:30:26 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s02b01x01p03n02i00370ent IS
END c03s02b01x01p03n02i00370ent;
ARCHITECTURE c03s02b01x01p03n02i00370arch OF c03s02b01x01p03n02i00370ent IS
subtype BFALSE is BOOLEAN range FALSE to FALSE;
type ONETWO is range 1 to 2;
type A3 is array (1 to 2,
ONETWO range <>) of BFALSE; -- Failure_here
-- ERROR - SYNTAX ERROR: CONSTRAINED AND UNCONSTRAINED INDEX RANGES
-- CANNOT BE MIXED
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c03s02b01x01p03n02i00370 - Unconstrained and constrained index ranges cannot be mixed."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x01p03n02i00370arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc370.vhd,v 1.2 2001-10-26 16:30:26 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s02b01x01p03n02i00370ent IS
END c03s02b01x01p03n02i00370ent;
ARCHITECTURE c03s02b01x01p03n02i00370arch OF c03s02b01x01p03n02i00370ent IS
subtype BFALSE is BOOLEAN range FALSE to FALSE;
type ONETWO is range 1 to 2;
type A3 is array (1 to 2,
ONETWO range <>) of BFALSE; -- Failure_here
-- ERROR - SYNTAX ERROR: CONSTRAINED AND UNCONSTRAINED INDEX RANGES
-- CANNOT BE MIXED
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c03s02b01x01p03n02i00370 - Unconstrained and constrained index ranges cannot be mixed."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x01p03n02i00370arch;
|
-- -------------------------------------------------------------
--
-- Generated Configuration for inst_shadow_ok_2_e
--
-- Generated
-- by: wig
-- on: Tue Nov 21 12:18:38 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../macro.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_shadow_ok_2_e-c.vhd,v 1.1 2006/11/22 10:40:09 wig Exp $
-- $Date: 2006/11/22 10:40:09 $
-- $Log: inst_shadow_ok_2_e-c.vhd,v $
-- Revision 1.1 2006/11/22 10:40:09 wig
-- Detect missing directories and flag that as error.
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.99 2006/11/02 15:37:48 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.47 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/conf
--
-- Start of Generated Configuration inst_shadow_ok_2_rtl_conf / inst_shadow_ok_2_e
--
configuration inst_shadow_ok_2_rtl_conf of inst_shadow_ok_2_e is
for rtl
-- Generated Configuration
end for;
end inst_shadow_ok_2_rtl_conf;
--
-- End of Generated Configuration inst_shadow_ok_2_rtl_conf
--
--
--!End of Configuration/ies
-- --------------------------------------------------------------
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_misc.all;
-- ******************************************************************************
-- * License Agreement *
-- * *
-- * Copyright (c) 1991-2012 Altera Corporation, San Jose, California, USA. *
-- * All rights reserved. *
-- * *
-- * Any megafunction design, and related net list (encrypted or decrypted), *
-- * support information, device programming or simulation file, and any other *
-- * associated documentation or information provided by Altera or a partner *
-- * under Altera's Megafunction Partnership Program may be used only to *
-- * program PLD devices (but not masked PLD devices) from Altera. Any other *
-- * use of such megafunction design, net list, support information, device *
-- * programming or simulation file, or any other related documentation or *
-- * information is prohibited for any other purpose, including, but not *
-- * limited to modification, reverse engineering, de-compiling, or use with *
-- * any other silicon devices, unless such use is explicitly licensed under *
-- * a separate agreement with Altera or a megafunction partner. Title to *
-- * the intellectual property, including patents, copyrights, trademarks, *
-- * trade secrets, or maskworks, embodied in any such megafunction design, *
-- * net list, support information, device programming or simulation file, or *
-- * any other related documentation or information provided by Altera or a *
-- * megafunction partner, remains with Altera, the megafunction partner, or *
-- * their respective licensors. No other licenses, including any licenses *
-- * needed under any third party's intellectual property, are provided herein.*
-- * Copying or modifying any file, or portion thereof, to which this notice *
-- * is attached violates this copyright. *
-- * *
-- * THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
-- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
-- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL *
-- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
-- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
-- * FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS *
-- * IN THIS FILE. *
-- * *
-- * This agreement shall be governed in all respects by the laws of the State *
-- * of California and by the laws of the United States of America. *
-- * *
-- ******************************************************************************
-- ******************************************************************************
-- * *
-- * This module converts resamples the chroma components of a video in *
-- * stream, whos colour space is YCrCb. *
-- * *
-- ******************************************************************************
ENTITY Video_System_Chroma_Resampler IS
-- *****************************************************************************
-- * Generic Declarations *
-- *****************************************************************************
GENERIC (
IDW :INTEGER := 15; -- Incoming frame's data width
ODW :INTEGER := 23; -- Outcoming frame's data width
IEW :INTEGER := 0; -- Incoming frame's empty width
OEW :INTEGER := 1 -- Outcoming frame's empty width
);
-- *****************************************************************************
-- * Port Declarations *
-- *****************************************************************************
PORT (
-- Inputs
clk :IN STD_LOGIC;
reset :IN STD_LOGIC;
stream_in_data :IN STD_LOGIC_VECTOR(IDW DOWNTO 0);
stream_in_startofpacket :IN STD_LOGIC;
stream_in_endofpacket :IN STD_LOGIC;
stream_in_empty :IN STD_LOGIC_VECTOR(IEW DOWNTO 0);
stream_in_valid :IN STD_LOGIC;
stream_out_ready :IN STD_LOGIC;
-- Bidirectional
-- Outputs
stream_in_ready :BUFFER STD_LOGIC;
stream_out_data :BUFFER STD_LOGIC_VECTOR(ODW DOWNTO 0);
stream_out_startofpacket :BUFFER STD_LOGIC;
stream_out_endofpacket :BUFFER STD_LOGIC;
stream_out_empty :BUFFER STD_LOGIC_VECTOR(OEW DOWNTO 0);
stream_out_valid :BUFFER STD_LOGIC
);
END Video_System_Chroma_Resampler;
ARCHITECTURE Behaviour OF Video_System_Chroma_Resampler IS
-- *****************************************************************************
-- * Constant Declarations *
-- *****************************************************************************
-- *****************************************************************************
-- * Internal Signals Declarations *
-- *****************************************************************************
-- Internal Wires
SIGNAL transfer_data :STD_LOGIC;
SIGNAL converted_data :STD_LOGIC_VECTOR(ODW DOWNTO 0);
SIGNAL converted_startofpacket :STD_LOGIC;
SIGNAL converted_endofpacket :STD_LOGIC;
SIGNAL converted_empty :STD_LOGIC_VECTOR(OEW DOWNTO 0);
SIGNAL converted_valid :STD_LOGIC;
-- Internal Registers
SIGNAL data :STD_LOGIC_VECTOR(IDW DOWNTO 0);
SIGNAL startofpacket :STD_LOGIC;
SIGNAL endofpacket :STD_LOGIC;
SIGNAL empty :STD_LOGIC_VECTOR(IEW DOWNTO 0);
SIGNAL valid :STD_LOGIC;
SIGNAL saved_CrCb :STD_LOGIC_VECTOR( 7 DOWNTO 0);
SIGNAL cur_is_Cr_or_Cb :STD_LOGIC;
-- State Machine Registers
-- Integers
-- *****************************************************************************
-- * Component Declarations *
-- *****************************************************************************
BEGIN
-- *****************************************************************************
-- * Finite State Machine(s) *
-- *****************************************************************************
-- *****************************************************************************
-- * Sequential Logic *
-- *****************************************************************************
-- Output Registers
PROCESS (clk)
BEGIN
IF clk'EVENT AND clk = '1' THEN
IF (reset = '1') THEN
stream_out_data <= (OTHERS => '0');
stream_out_startofpacket <= '0';
stream_out_endofpacket <= '0';
stream_out_empty <= (OTHERS => '0');
stream_out_valid <= '0';
ELSIF (transfer_data = '1') THEN
stream_out_data <= converted_data;
stream_out_startofpacket <= converted_startofpacket;
stream_out_endofpacket <= converted_endofpacket;
stream_out_empty <= converted_empty;
stream_out_valid <= converted_valid;
END IF;
END IF;
END PROCESS;
-- Internal Registers
PROCESS (clk)
BEGIN
IF clk'EVENT AND clk = '1' THEN
IF (reset = '1') THEN
data <= (OTHERS => '0');
startofpacket <= '0';
endofpacket <= '0';
empty <= (OTHERS => '0');
valid <= '0';
ELSIF (stream_in_ready = '1') THEN
data <= stream_in_data;
startofpacket <= stream_in_startofpacket;
endofpacket <= stream_in_endofpacket;
empty <= stream_in_empty;
valid <= stream_in_valid;
ELSIF (transfer_data = '1') THEN
data <= (OTHERS => '0');
startofpacket <= '0';
endofpacket <= '0';
empty <= (OTHERS => '0');
valid <= '0';
END IF;
END IF;
END PROCESS;
PROCESS (clk)
BEGIN
IF clk'EVENT AND clk = '1' THEN
IF (reset = '1') THEN
saved_CrCb <= B"00000000";
ELSIF ((stream_in_ready = '1') AND (stream_in_startofpacket = '1')) THEN
saved_CrCb <= B"00000000";
ELSIF ((transfer_data = '1') AND (valid = '1')) THEN
saved_CrCb <= data(15 DOWNTO 8);
END IF;
END IF;
END PROCESS;
PROCESS (clk)
BEGIN
IF clk'EVENT AND clk = '1' THEN
IF (reset = '1') THEN
cur_is_Cr_or_Cb <= '0';
ELSIF ((stream_in_ready = '1') AND (stream_in_startofpacket = '1')) THEN
cur_is_Cr_or_Cb <= '0';
ELSIF (stream_in_ready = '1') THEN
cur_is_Cr_or_Cb <= cur_is_Cr_or_Cb XOR '1';
END IF;
END IF;
END PROCESS;
-- *****************************************************************************
-- * Combinational Logic *
-- *****************************************************************************
-- Output Assignments
stream_in_ready <= stream_in_valid AND (NOT valid OR transfer_data);
-- Internal Assignments
transfer_data <=
NOT stream_out_valid OR (stream_out_ready AND stream_out_valid);
converted_data(23 DOWNTO 16) <= data(15 DOWNTO 8) WHEN (cur_is_Cr_or_Cb = '1')
ELSE saved_CrCb;
converted_data(15 DOWNTO 8) <= saved_CrCb WHEN (cur_is_Cr_or_Cb = '1')
ELSE data(15 DOWNTO 8);
converted_data( 7 DOWNTO 0) <= data( 7 DOWNTO 0);
converted_startofpacket <= startofpacket;
converted_endofpacket <= endofpacket;
converted_empty <= empty;
converted_valid <= valid;
-- *****************************************************************************
-- * Component Instantiations *
-- *****************************************************************************
END Behaviour;
|
-- --------------------------
-- TIMING
-- --------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
-- ----------------------------------------------------
Entity timing is
-- ----------------------------------------------------
generic (
F : natural;
min_baud: natural
);
port (
CLK : in std_logic;
RST : in std_logic;
divisor : in std_logic_vector;
ClrDiv : in std_logic;
Top16 : buffer std_logic;
TopTx : out std_logic;
TopRx : out std_logic
);
end timing;
-- ----------------------------------------------------
Architecture timing of timing is
-- ----------------------------------------------------
-- signal baud_value : natural;
constant max_div : natural := ((F*1000)/(16*min_baud));
subtype div16_type is natural range 0 to max_div-1;
signal Div16 : div16_type;
signal ClkDiv : integer;
signal RxDiv : integer;
begin
-- --------------------------
-- Baud rate selection
-- --------------------------
--
-- process (CLK) -- baud_value setting.
-- begin
-- if rising_edge(CLK) then
-- case Baud is
-- when "000" => baud_value <= 115200;
-- when "001" => baud_value <= 57600;
-- when "010" => baud_value <= 38400;
-- when "011" => baud_value <= 19200;
-- when "100" => baud_value <= 9600;
-- when "101" => baud_value <= 4800;
-- when "110" => baud_value <= 2400;
-- when "111" => baud_value <= 1200;
-- when others => baud_value <= 1200; -- n.u.
-- end case;
-- end if;
-- end process;
--
-- --------------------------
-- Clk16 Clock Generation
-- --------------------------
process (RST, CLK)
begin
if RST='1' then
Top16 <= '0';
Div16 <= 0;
elsif rising_edge(CLK) then
Top16 <= '0';
if Div16 = conv_integer(divisor) then
Div16 <= 0;
Top16 <= '1';
else
Div16 <= Div16 + 1;
end if;
end if;
end process;
-- --------------------------
-- Tx Clock Generation
-- --------------------------
process (RST, CLK)
begin
if RST='1' then
TopTx <= '0';
ClkDiv <= 0; --(others=>'0');
elsif rising_edge(CLK) then
TopTx <= '0';
if Top16='1' then
ClkDiv <= ClkDiv + 1;
if ClkDiv = 15 then
TopTx <= '1';
ClkDiv <= 0;
end if;
end if;
end if;
end process;
-- ------------------------------
-- Rx Sampling Clock Generation
-- ------------------------------
process (RST, CLK)
begin
if RST='1' then
TopRx <= '0';
RxDiv <= 0;
elsif rising_edge(CLK) then
TopRx <= '0';
if ClrDiv='1' then
RxDiv <= 0;
elsif Top16='1' then
if RxDiv = 7 then
RxDiv <= 0;
TopRx <= '1';
else
RxDiv <= RxDiv + 1;
end if;
end if;
end if;
end process;
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
entity verzoegerung_tb is
end verzoegerung_tb;
architecture behavior of verzoegerung_tb is
component verzoegerung
port(
CLK, START : in std_logic;
STOP : in std_logic; -- Aufgabe 2
ALARM : out std_logic
);
end component;
signal START : std_logic := '0';
signal STOP : std_logic := '0';
signal CLK : std_logic := '0';
signal ALARM : std_logic;
constant clk_period : time := 1 sec;
begin
uut: verzoegerung port map (START => START, STOP => STOP, CLK => CLK,
ALARM => ALARM
);
p0 :process
begin
CLK <= '0';
wait for clk_period/2;
CLK <= '1';
wait for clk_period/2;
end process;
p1: process
begin
wait for 2 * clk_period;
START <= '1';
wait for clk_period;
wait for clk_period;
wait for clk_period;
wait for clk_period;
wait for clk_period;
wait for clk_period;
START <= '0';
wait for clk_period;
START <= '1';
wait for clk_period;
wait for clk_period;
STOP <= '1';
wait for clk_period;
wait for clk_period;
wait for clk_period;
wait for clk_period;
end process;
end;
|
library ieee;
use ieee.std_logic_1164.all;
entity verzoegerung_tb is
end verzoegerung_tb;
architecture behavior of verzoegerung_tb is
component verzoegerung
port(
CLK, START : in std_logic;
STOP : in std_logic; -- Aufgabe 2
ALARM : out std_logic
);
end component;
signal START : std_logic := '0';
signal STOP : std_logic := '0';
signal CLK : std_logic := '0';
signal ALARM : std_logic;
constant clk_period : time := 1 sec;
begin
uut: verzoegerung port map (START => START, STOP => STOP, CLK => CLK,
ALARM => ALARM
);
p0 :process
begin
CLK <= '0';
wait for clk_period/2;
CLK <= '1';
wait for clk_period/2;
end process;
p1: process
begin
wait for 2 * clk_period;
START <= '1';
wait for clk_period;
wait for clk_period;
wait for clk_period;
wait for clk_period;
wait for clk_period;
wait for clk_period;
START <= '0';
wait for clk_period;
START <= '1';
wait for clk_period;
wait for clk_period;
STOP <= '1';
wait for clk_period;
wait for clk_period;
wait for clk_period;
wait for clk_period;
end process;
end;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 21:44:15 11/21/2012
-- Design Name:
-- Module Name: BancoDeRegistros - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity BancoDeRegistros is
--generic( P: integer:=32; -- ancho de palabra
--N: integer:=32; -- nº de palabras
--tam_addr: integer:=5); -- ancho dirección
port( Clock: in std_logic;
Reg_Write: in std_logic;
RA: in std_logic_vector(4 downto 0);
RB: in std_logic_vector(4 downto 0);
RW: in std_logic_vector(4 downto 0);
busW: in std_logic_vector(31 downto 0);
busA: out std_logic_vector(31 downto 0);
busB: out std_logic_vector(31 downto 0);
reg0: out std_logic_vector(31 downto 0);
reg1: out std_logic_vector(31 downto 0);
reg2: out std_logic_vector(31 downto 0);
reg3: out std_logic_vector(31 downto 0)
);
end BancoDeRegistros;
architecture Behavioral of BancoDeRegistros is
type br_type is array (0 to 31) of std_logic_vector(31 downto 0);
signal tmp: br_type:=(
"00000000000000000000000000000000",
"00000000000000000000000000000001",
"00000000000000011000000000000000",
"00000000000000000000100000000001",
"00000000000000000000000000000111",
"00000000000000000000000000000001",
"00000000000000000000000000000110",
"00000000000000000000000000000001",
"00000000000000000000000000000000",
"00000000000000000000000000000001",
"00000000000000000000000000000000",
"00000000000000000000000000000001",
"00000000000000000000000000000000",
"00000000000000000000000000000001",
"00000000000000000000000000000000",
"00000000000000000000000000000001",
"00000000000000000000000000000000",
"00000000000000000000000000000001",
"00000000000000000000000000000000",
"00000000000000000000000000000001",
"00000000000000000000000000000000",
"00000000000000000000000000000001",
"00000000000000000000000000000000",
"00000000000000000000000000000001",
"00000000000000000000000000000000",
"00000000000000000000000000000001",
"00000000000000000000000000000000",
"00000000000000000000000000000001",
"00000000000000000000000000000000",
"00000000000000000000000000000001",
"00000000000000000000000000000000",
"00000000000000000000000000001111");
begin
-- Lectura asíncrona
busA <= tmp(conv_integer(RA));
busB <= tmp(conv_integer(RB));
reg0 <= tmp(conv_integer(0));
reg1 <= tmp(conv_integer(1));
reg2 <= tmp(conv_integer(2));
reg3 <= tmp(conv_integer(3));
-- Escritura
process(Clock, Reg_Write)
begin
if (Clock'event and Clock='1') then
if Reg_Write='1' then
tmp(conv_integer(RW)) <= busW;
end if;
end if;
end process;
end Behavioral;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_gpio:2.0
-- IP Revision: 16
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_gpio_v2_0_16;
USE axi_gpio_v2_0_16.axi_gpio;
ENTITY ip_design_axi_gpio_0_0 IS
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
gpio_io_i : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
gpio_io_o : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
gpio_io_t : OUT STD_LOGIC_VECTOR(1 DOWNTO 0)
);
END ip_design_axi_gpio_0_0;
ARCHITECTURE ip_design_axi_gpio_0_0_arch OF ip_design_axi_gpio_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF ip_design_axi_gpio_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_gpio IS
GENERIC (
C_FAMILY : STRING;
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER;
C_GPIO_WIDTH : INTEGER;
C_GPIO2_WIDTH : INTEGER;
C_ALL_INPUTS : INTEGER;
C_ALL_INPUTS_2 : INTEGER;
C_ALL_OUTPUTS : INTEGER;
C_ALL_OUTPUTS_2 : INTEGER;
C_INTERRUPT_PRESENT : INTEGER;
C_DOUT_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_TRI_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_IS_DUAL : INTEGER;
C_DOUT_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_TRI_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0)
);
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
ip2intc_irpt : OUT STD_LOGIC;
gpio_io_i : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
gpio_io_o : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
gpio_io_t : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
gpio2_io_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
gpio2_io_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
gpio2_io_t : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT axi_gpio;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF ip_design_axi_gpio_0_0_arch: ARCHITECTURE IS "axi_gpio,Vivado 2017.3";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF ip_design_axi_gpio_0_0_arch : ARCHITECTURE IS "ip_design_axi_gpio_0_0,axi_gpio,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF ip_design_axi_gpio_0_0_arch: ARCHITECTURE IS "ip_design_axi_gpio_0_0,axi_gpio,{x_ipProduct=Vivado 2017.3,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_gpio,x_ipVersion=2.0,x_ipCoreRevision=16,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_S_AXI_ADDR_WIDTH=9,C_S_AXI_DATA_WIDTH=32,C_GPIO_WIDTH=2,C_GPIO2_WIDTH=32,C_ALL_INPUTS=0,C_ALL_INPUTS_2=0,C_ALL_OUTPUTS=0,C_ALL_OUTPUTS_2=0,C_INTERRUPT_PRESENT=0,C_DOUT_DEFAULT=0x00000000,C_TRI_DEFAULT=0xFFFFFFFF,C_IS_DUAL=0,C_DOUT_DEFAULT_2=0x00000000,C_TRI_DEFAULT_2=0xFFFFFFFF}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
ATTRIBUTE X_INTERFACE_INFO OF gpio_io_t: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_T";
ATTRIBUTE X_INTERFACE_INFO OF gpio_io_o: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_O";
ATTRIBUTE X_INTERFACE_PARAMETER OF gpio_io_i: SIGNAL IS "XIL_INTERFACENAME GPIO, BOARD.ASSOCIATED_PARAM GPIO_BOARD_INTERFACE";
ATTRIBUTE X_INTERFACE_INFO OF gpio_io_i: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_I";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_awaddr: SIGNAL IS "XIL_INTERFACENAME S_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 9, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN ip_design_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_aresetn: SIGNAL IS "XIL_INTERFACENAME S_AXI_ARESETN, POLARITY ACTIVE_LOW";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 S_AXI_ARESETN RST";
ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_aclk: SIGNAL IS "XIL_INTERFACENAME S_AXI_ACLK, ASSOCIATED_BUSIF S_AXI, ASSOCIATED_RESET s_axi_aresetn, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN ip_design_processing_system7_0_0_FCLK_CLK0";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXI_ACLK CLK";
BEGIN
U0 : axi_gpio
GENERIC MAP (
C_FAMILY => "zynq",
C_S_AXI_ADDR_WIDTH => 9,
C_S_AXI_DATA_WIDTH => 32,
C_GPIO_WIDTH => 2,
C_GPIO2_WIDTH => 32,
C_ALL_INPUTS => 0,
C_ALL_INPUTS_2 => 0,
C_ALL_OUTPUTS => 0,
C_ALL_OUTPUTS_2 => 0,
C_INTERRUPT_PRESENT => 0,
C_DOUT_DEFAULT => X"00000000",
C_TRI_DEFAULT => X"FFFFFFFF",
C_IS_DUAL => 0,
C_DOUT_DEFAULT_2 => X"00000000",
C_TRI_DEFAULT_2 => X"FFFFFFFF"
)
PORT MAP (
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_awaddr => s_axi_awaddr,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_araddr => s_axi_araddr,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
gpio_io_i => gpio_io_i,
gpio_io_o => gpio_io_o,
gpio_io_t => gpio_io_t,
gpio2_io_i => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32))
);
END ip_design_axi_gpio_0_0_arch;
|
LIBRARY ieee ;
USE ieee.std_logic_1164.all;
entity conv_7seg_int is
port(digit: in integer;
seg: out std_logic_vector(6 downto 0));
end conv_7seg_int;
architecture Behavior of conv_7seg_int is
begin
with digit select
seg <=
"1000000" when 0,
"1111001" when 1,
"0100100" when 2,
"0110000" when 3,
"0011001" when 4,
"0010010" when 5,
"0000010" when 6,
"1111000" when 7,
"0000000" when 8,
"0010000" when 9,
"0001000" when 10,
"0000011" when 11,
"1000110" when 12,
"0100001" when 13,
"0000110" when 14,
"0001110" when 15,
"1000000" when others;
end Behavior;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity test is
end test;
architecture rtl of test is
component top is
port( clk : in std_logic;
reset : in std_logic;
vs : out std_logic;
hs : out std_logic;
red : out std_logic_vector(2 downto 0);
green : out std_logic_vector(2 downto 0);
blue : out std_logic_vector(1 downto 0));
end component;
signal red : std_logic_vector(2 downto 0);
signal green : std_logic_vector(2 downto 0);
signal blue : std_logic_vector(1 downto 0);
signal HS : std_logic;
signal VS : std_logic;
signal clk : std_logic;
signal s_reset : std_logic;
begin
top0 : top port map(clk => clk,
reset => s_reset,
red => red,
blue => blue,
green => green,
HS => HS,
VS => VS);
process
begin
s_reset <= '1';
wait for 20 ns;
s_reset <= '0';
wait;
end process;
process
begin
clk <= '0';
wait for 10 ns;
clk <= '1';
wait for 10 ns;
end process;
end rtl;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2071.vhd,v 1.2 2001-10-26 16:30:15 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b04x00p01n02i02071ent IS
END c07s02b04x00p01n02i02071ent;
ARCHITECTURE c07s02b04x00p01n02i02071arch OF c07s02b04x00p01n02i02071ent IS
BEGIN
TESTING: PROCESS
-- All different type declarations.
-- integer types.
type POSITIVE is range 0 to INTEGER'HIGH;
-- floating point types.
type POSITIVE_R is range 0.0 to REAL'HIGH;
-- Local declarations.
variable POSV : POSITIVE := 0;
variable POSRV : POSITIVE_R := 0.0;
BEGIN
POSV := POSV + POSRV;
assert FALSE
report "***FAILED TEST: c07s02b04x00p01n02i02071 - The operands of the operators + and - cannot be of different types."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b04x00p01n02i02071arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2071.vhd,v 1.2 2001-10-26 16:30:15 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b04x00p01n02i02071ent IS
END c07s02b04x00p01n02i02071ent;
ARCHITECTURE c07s02b04x00p01n02i02071arch OF c07s02b04x00p01n02i02071ent IS
BEGIN
TESTING: PROCESS
-- All different type declarations.
-- integer types.
type POSITIVE is range 0 to INTEGER'HIGH;
-- floating point types.
type POSITIVE_R is range 0.0 to REAL'HIGH;
-- Local declarations.
variable POSV : POSITIVE := 0;
variable POSRV : POSITIVE_R := 0.0;
BEGIN
POSV := POSV + POSRV;
assert FALSE
report "***FAILED TEST: c07s02b04x00p01n02i02071 - The operands of the operators + and - cannot be of different types."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b04x00p01n02i02071arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2071.vhd,v 1.2 2001-10-26 16:30:15 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b04x00p01n02i02071ent IS
END c07s02b04x00p01n02i02071ent;
ARCHITECTURE c07s02b04x00p01n02i02071arch OF c07s02b04x00p01n02i02071ent IS
BEGIN
TESTING: PROCESS
-- All different type declarations.
-- integer types.
type POSITIVE is range 0 to INTEGER'HIGH;
-- floating point types.
type POSITIVE_R is range 0.0 to REAL'HIGH;
-- Local declarations.
variable POSV : POSITIVE := 0;
variable POSRV : POSITIVE_R := 0.0;
BEGIN
POSV := POSV + POSRV;
assert FALSE
report "***FAILED TEST: c07s02b04x00p01n02i02071 - The operands of the operators + and - cannot be of different types."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b04x00p01n02i02071arch;
|
Library ieee;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_signed.all;
entity mul32const is
port(
in1: in std_logic_vector(31 downto 0);
out1: out std_logic_vector(34 downto 0)
);
end mul32const;
architecture rtl of mul32const is
begin
out1<= ((in1 & "000") + (in1) + (in1));
end rtl;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.fastfilter_types.all;
entity taps2 is
generic (
PIXEL_SIZE : integer;
TAPS_WIDTH : integer;
KERNEL_SIZE : integer
);
port (
clk : in std_logic;
reset_n : in std_logic;
enable : in std_logic;
in_data : in std_logic_vector (PIXEL_SIZE-1 downto 0);
taps_data : out pixel_array (0 to KERNEL_SIZE -1 );
out_data : out std_logic_vector (PIXEL_SIZE-1 downto 0)
);
end taps2;
architecture bhv of taps2 is
signal cell : pixel_array (0 to TAPS_WIDTH-1);
begin
process(clk)
variable i : integer := 0;
begin
if ( reset_n = '0' ) then
cell <= (others =>(others => '0'));
out_data <= (others => '0');
taps_data <= (others =>(others => '0'));
elsif (rising_edge(clk)) then
if (enable='1') then
cell(0) <= in_data;
for i in 1 to (TAPS_WIDTH-1) loop
cell(i) <= cell(i-1);
end loop;
taps_data <= cell(0 to KERNEL_SIZE-1);
out_data <= cell(TAPS_WIDTH-1);
end if;
end if;
end process;
end bhv;
|
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_block
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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|
-- (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:fir_compiler:7.1
-- IP Revision: 3
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY fir_compiler_v7_1;
USE fir_compiler_v7_1.fir_compiler_v7_1;
ENTITY fir_lp_15kHz IS
PORT (
aclk : IN STD_LOGIC;
s_axis_data_tvalid : IN STD_LOGIC;
s_axis_data_tready : OUT STD_LOGIC;
s_axis_data_tdata : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
m_axis_data_tvalid : OUT STD_LOGIC;
m_axis_data_tdata : OUT STD_LOGIC_VECTOR(47 DOWNTO 0)
);
END fir_lp_15kHz;
ARCHITECTURE fir_lp_15kHz_arch OF fir_lp_15kHz IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF fir_lp_15kHz_arch: ARCHITECTURE IS "yes";
COMPONENT fir_compiler_v7_1 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_ELABORATION_DIR : STRING;
C_COMPONENT_NAME : STRING;
C_COEF_FILE : STRING;
C_COEF_FILE_LINES : INTEGER;
C_FILTER_TYPE : INTEGER;
C_INTERP_RATE : INTEGER;
C_DECIM_RATE : INTEGER;
C_ZERO_PACKING_FACTOR : INTEGER;
C_SYMMETRY : INTEGER;
C_NUM_FILTS : INTEGER;
C_NUM_TAPS : INTEGER;
C_NUM_CHANNELS : INTEGER;
C_CHANNEL_PATTERN : STRING;
C_ROUND_MODE : INTEGER;
C_COEF_RELOAD : INTEGER;
C_NUM_RELOAD_SLOTS : INTEGER;
C_COL_MODE : INTEGER;
C_COL_PIPE_LEN : INTEGER;
C_COL_CONFIG : STRING;
C_OPTIMIZATION : INTEGER;
C_DATA_PATH_WIDTHS : STRING;
C_DATA_IP_PATH_WIDTHS : STRING;
C_DATA_PX_PATH_WIDTHS : STRING;
C_DATA_WIDTH : INTEGER;
C_COEF_PATH_WIDTHS : STRING;
C_COEF_WIDTH : INTEGER;
C_DATA_PATH_SRC : STRING;
C_COEF_PATH_SRC : STRING;
C_DATA_PATH_SIGN : STRING;
C_COEF_PATH_SIGN : STRING;
C_ACCUM_PATH_WIDTHS : STRING;
C_OUTPUT_WIDTH : INTEGER;
C_OUTPUT_PATH_WIDTHS : STRING;
C_ACCUM_OP_PATH_WIDTHS : STRING;
C_EXT_MULT_CNFG : STRING;
C_DATA_PATH_PSAMP_SRC : STRING;
C_OP_PATH_PSAMP_SRC : STRING;
C_NUM_MADDS : INTEGER;
C_OPT_MADDS : STRING;
C_OVERSAMPLING_RATE : INTEGER;
C_INPUT_RATE : INTEGER;
C_OUTPUT_RATE : INTEGER;
C_DATA_MEMTYPE : INTEGER;
C_COEF_MEMTYPE : INTEGER;
C_IPBUFF_MEMTYPE : INTEGER;
C_OPBUFF_MEMTYPE : INTEGER;
C_DATAPATH_MEMTYPE : INTEGER;
C_MEM_ARRANGEMENT : INTEGER;
C_DATA_MEM_PACKING : INTEGER;
C_COEF_MEM_PACKING : INTEGER;
C_FILTS_PACKED : INTEGER;
C_LATENCY : INTEGER;
C_HAS_ARESETn : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_DATA_HAS_TLAST : INTEGER;
C_S_DATA_HAS_FIFO : INTEGER;
C_S_DATA_HAS_TUSER : INTEGER;
C_S_DATA_TDATA_WIDTH : INTEGER;
C_S_DATA_TUSER_WIDTH : INTEGER;
C_M_DATA_HAS_TREADY : INTEGER;
C_M_DATA_HAS_TUSER : INTEGER;
C_M_DATA_TDATA_WIDTH : INTEGER;
C_M_DATA_TUSER_WIDTH : INTEGER;
C_HAS_CONFIG_CHANNEL : INTEGER;
C_CONFIG_SYNC_MODE : INTEGER;
C_CONFIG_PACKET_SIZE : INTEGER;
C_CONFIG_TDATA_WIDTH : INTEGER;
C_RELOAD_TDATA_WIDTH : INTEGER
);
PORT (
aresetn : IN STD_LOGIC;
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
s_axis_data_tvalid : IN STD_LOGIC;
s_axis_data_tready : OUT STD_LOGIC;
s_axis_data_tlast : IN STD_LOGIC;
s_axis_data_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_data_tdata : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
s_axis_config_tvalid : IN STD_LOGIC;
s_axis_config_tready : OUT STD_LOGIC;
s_axis_config_tlast : IN STD_LOGIC;
s_axis_config_tdata : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_reload_tvalid : IN STD_LOGIC;
s_axis_reload_tready : OUT STD_LOGIC;
s_axis_reload_tlast : IN STD_LOGIC;
s_axis_reload_tdata : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_data_tvalid : OUT STD_LOGIC;
m_axis_data_tready : IN STD_LOGIC;
m_axis_data_tlast : OUT STD_LOGIC;
m_axis_data_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_data_tdata : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
event_s_data_tlast_missing : OUT STD_LOGIC;
event_s_data_tlast_unexpected : OUT STD_LOGIC;
event_s_data_chanid_incorrect : OUT STD_LOGIC;
event_s_config_tlast_missing : OUT STD_LOGIC;
event_s_config_tlast_unexpected : OUT STD_LOGIC;
event_s_reload_tlast_missing : OUT STD_LOGIC;
event_s_reload_tlast_unexpected : OUT STD_LOGIC
);
END COMPONENT fir_compiler_v7_1;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_data_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_DATA TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_data_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_DATA TREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_data_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_DATA TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_data_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_DATA TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_data_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_DATA TDATA";
BEGIN
U0 : fir_compiler_v7_1
GENERIC MAP (
C_XDEVICEFAMILY => "zynq",
C_ELABORATION_DIR => "./",
C_COMPONENT_NAME => "fir_lp_15kHz",
C_COEF_FILE => "fir_lp_15kHz.mif",
C_COEF_FILE_LINES => 1024,
C_FILTER_TYPE => 1,
C_INTERP_RATE => 1,
C_DECIM_RATE => 4,
C_ZERO_PACKING_FACTOR => 1,
C_SYMMETRY => 1,
C_NUM_FILTS => 1,
C_NUM_TAPS => 2048,
C_NUM_CHANNELS => 1,
C_CHANNEL_PATTERN => "fixed",
C_ROUND_MODE => 0,
C_COEF_RELOAD => 0,
C_NUM_RELOAD_SLOTS => 1,
C_COL_MODE => 1,
C_COL_PIPE_LEN => 4,
C_COL_CONFIG => "16",
C_OPTIMIZATION => 2046,
C_DATA_PATH_WIDTHS => "16",
C_DATA_IP_PATH_WIDTHS => "16",
C_DATA_PX_PATH_WIDTHS => "16",
C_DATA_WIDTH => 16,
C_COEF_PATH_WIDTHS => "24",
C_COEF_WIDTH => 24,
C_DATA_PATH_SRC => "0",
C_COEF_PATH_SRC => "0",
C_DATA_PATH_SIGN => "0",
C_COEF_PATH_SIGN => "0",
C_ACCUM_PATH_WIDTHS => "44",
C_OUTPUT_WIDTH => 44,
C_OUTPUT_PATH_WIDTHS => "44",
C_ACCUM_OP_PATH_WIDTHS => "44",
C_EXT_MULT_CNFG => "none",
C_DATA_PATH_PSAMP_SRC => "0",
C_OP_PATH_PSAMP_SRC => "0",
C_NUM_MADDS => 16,
C_OPT_MADDS => "none",
C_OVERSAMPLING_RATE => 16,
C_INPUT_RATE => 16,
C_OUTPUT_RATE => 64,
C_DATA_MEMTYPE => 0,
C_COEF_MEMTYPE => 2,
C_IPBUFF_MEMTYPE => 0,
C_OPBUFF_MEMTYPE => 0,
C_DATAPATH_MEMTYPE => 2,
C_MEM_ARRANGEMENT => 1,
C_DATA_MEM_PACKING => 0,
C_COEF_MEM_PACKING => 0,
C_FILTS_PACKED => 0,
C_LATENCY => 40,
C_HAS_ARESETn => 0,
C_HAS_ACLKEN => 0,
C_DATA_HAS_TLAST => 0,
C_S_DATA_HAS_FIFO => 1,
C_S_DATA_HAS_TUSER => 0,
C_S_DATA_TDATA_WIDTH => 16,
C_S_DATA_TUSER_WIDTH => 1,
C_M_DATA_HAS_TREADY => 0,
C_M_DATA_HAS_TUSER => 0,
C_M_DATA_TDATA_WIDTH => 48,
C_M_DATA_TUSER_WIDTH => 1,
C_HAS_CONFIG_CHANNEL => 0,
C_CONFIG_SYNC_MODE => 0,
C_CONFIG_PACKET_SIZE => 0,
C_CONFIG_TDATA_WIDTH => 1,
C_RELOAD_TDATA_WIDTH => 1
)
PORT MAP (
aresetn => '1',
aclk => aclk,
aclken => '1',
s_axis_data_tvalid => s_axis_data_tvalid,
s_axis_data_tready => s_axis_data_tready,
s_axis_data_tlast => '0',
s_axis_data_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_data_tdata => s_axis_data_tdata,
s_axis_config_tvalid => '0',
s_axis_config_tlast => '0',
s_axis_config_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_reload_tvalid => '0',
s_axis_reload_tlast => '0',
s_axis_reload_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axis_data_tvalid => m_axis_data_tvalid,
m_axis_data_tready => '1',
m_axis_data_tdata => m_axis_data_tdata
);
END fir_lp_15kHz_arch;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:13:29 11/08/2013
-- Design Name:
-- Module Name: cerrojoElectronico - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity cerrojoElectronico is
port (
-- Entradas
intro: in std_logic; -- Boton para confirmar la introduccion de clave
switch: in std_logic_vector(7 downto 0); -- Switches para escribir la clave
clk: in std_logic; -- Reloj
rst: in std_logic; -- Reset
-- Salidas
segs: out std_logic_vector(7 downto 0); -- Display 8-Segmentos para visualizar numero de intentos restantes
lock: out std_logic -- Encederemos el primer LED para indicar que esta LOCK
);
end cerrojoElectronico;
architecture Behavioral of cerrojoElectronico is
-- CERROJO ELECTRONICO
signal xDebounced,xDebRiseEdge,xDebFallingEdge: std_logic;
signal load: std_logic;
signal salidaRegistro: std_logic_vector(7 downto 0);
signal rightSeg: std_logic_vector(7 downto 0);
-- MAQUINA DE ESTADOS
type ESTADOS is (INICIAL,S0, S1, S2, S3);
signal ESTADO, SIG_ESTADO: ESTADOS;
signal st: std_logic_vector(3 downto 0);
--
signal clave: std_logic_vector(7 downto 0);
component debouncer
port(rst: in std_logic;
clk: in std_logic;
x: in std_logic;
xDeb: out std_logic;
xDebFallingEdge: out std_logic;
xDebRisingEdge: out std_logic);
end component;
component binToSeg
port (
bin: in std_logic_vector(3 downto 0);
displaySeg: out std_logic_vector(7 downto 0) -- 7 = A / 6 = B / ... / 0 = H
);
end component;
begin
segs <= rightSeg;
clave <= switch;
button: debouncer port map (rst,clk,intro,xDebounced,xDebFallingEdge,xDebRiseEdge);
registro:
process (clk, rst)
begin
-- Los Push Buttons, como los Switches, tienen logica negativa, es decir, es al reves.
if rst='0' then
salidaRegistro <= (others=>'0');
elsif (clk'event and clk='1') then
if load='1' then
salidaRegistro <= switch;
end if;
end if;
end process;
-- MAQUINA ESTADOS: SINCRONO
maqEstadosSyn:
process(clk,rst)
begin
if rst ='0' then
ESTADO <= INICIAL;
elsif clk'event and clk='1' then
ESTADO <= SIG_ESTADO;
end if;
end process;
-- MAQUINA ESTADOS: COMBINACIONAL
maqEstadosComb:
process(ESTADO,rst,xDebFallingEdge,salidaRegistro,clave)
begin
SIG_ESTADO <= ESTADO;
load <= '0';
lock <= '1';
case ESTADO is
when INICIAL =>
lock <= '0';
st <= "1010";
if xDebFallingEdge = '1' then
load <= '1';
SIG_ESTADO <= S3;
end if;
when S3 =>
st <= "0011";
if xDebFallingEdge = '1' and (salidaRegistro = clave) then
SIG_ESTADO <= INICIAL;
elsif xDebFallingEdge = '1' and (salidaRegistro /= clave) then
SIG_ESTADO <= S2;
end if;
when S2 =>
st <= "0010";
if xDebFallingEdge = '1' and (salidaRegistro = clave) then
SIG_ESTADO <= INICIAL;
elsif xDebFallingEdge = '1' and (salidaRegistro /= clave) then
SIG_ESTADO <= S1;
end if;
when S1 =>
st <= "0001";
if xDebFallingEdge = '1' and (salidaRegistro = clave) then
SIG_ESTADO <= INICIAL;
elsif xDebFallingEdge = '1' and (salidaRegistro /= clave) then
SIG_ESTADO <= S0;
end if;
when S0 =>
st <= "0000";
end case;
end process;
displayCuenta: binToSeg port map (st,rightSeg);
end Behavioral;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
----------------------------------------------------------------------------
-- Entity: ahbctrl
-- File: ahbctrl.vhd
-- Author: Jiri Gaisler, Gaisler Research
-- Modified: Edvin Catovic, Gaisler Research
-- Description: AMBA arbiter, decoder and multiplexer with plug&play support
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
use grlib.amba.all;
use grlib.config_types.all;
use grlib.config.all;
-- pragma translate_off
use grlib.devices.all;
use std.textio.all;
-- pragma translate_on
entity ahbctrl is
generic (
defmast : integer := 0; -- default master
split : integer := 0; -- split support
rrobin : integer := 0; -- round-robin arbitration
timeout : integer range 0 to 255 := 0; -- HREADY timeout
ioaddr : ahb_addr_type := 16#fff#; -- I/O area MSB address
iomask : ahb_addr_type := 16#fff#; -- I/O area address mask
cfgaddr : ahb_addr_type := 16#ff0#; -- config area MSB address
cfgmask : ahb_addr_type := 16#ff0#; -- config area address mask
nahbm : integer range 1 to NAHBMST := NAHBMST; -- number of masters
nahbs : integer range 1 to NAHBSLV := NAHBSLV; -- number of slaves
ioen : integer range 0 to 15 := 1; -- enable I/O area
disirq : integer range 0 to 1 := 0; -- disable interrupt routing
fixbrst : integer range 0 to 1 := 0; -- support fix-length bursts
debug : integer range 0 to 2 := 2; -- report cores to console
fpnpen : integer range 0 to 1 := 0; -- full PnP configuration decoding
icheck : integer range 0 to 1 := 1;
devid : integer := 0; -- unique device ID
enbusmon : integer range 0 to 1 := 0; --enable bus monitor
assertwarn : integer range 0 to 1 := 0; --enable assertions for warnings
asserterr : integer range 0 to 1 := 0; --enable assertions for errors
hmstdisable : integer := 0; --disable master checks
hslvdisable : integer := 0; --disable slave checks
arbdisable : integer := 0; --disable arbiter checks
mprio : integer := 0; --master with highest priority
mcheck : integer range 0 to 2 := 1; --check memory map for intersects
ccheck : integer range 0 to 1 := 1; --perform sanity checks on pnp config
acdm : integer := 0; --AMBA compliant data muxing (for hsize > word)
index : integer := 0; --Index for trace print-out
ahbtrace : integer := 0; --AHB trace enable
hwdebug : integer := 0; --Hardware debug
fourgslv : integer := 0 --1=Single slave with single 4 GB bar
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
msti : out ahb_mst_in_type;
msto : in ahb_mst_out_vector;
slvi : out ahb_slv_in_type;
slvo : in ahb_slv_out_vector;
testen : in std_ulogic := '0';
testrst : in std_ulogic := '1';
scanen : in std_ulogic := '0';
testoen : in std_ulogic := '1';
testsig : in std_logic_vector(1+GRLIB_CONFIG_ARRAY(grlib_techmap_testin_extra) downto 0) := (others => '0')
);
end;
architecture rtl of ahbctrl is
constant nahbmx : integer := 2**log2(nahbm);
type nmstarr is array (1 to 3) of integer range 0 to nahbmx-1;
type nvalarr is array (1 to 3) of boolean;
type reg_type is record
hmaster : integer range 0 to nahbmx -1;
hmasterd : integer range 0 to nahbmx -1;
hslave : integer range 0 to nahbs-1;
hmasterlock : std_ulogic;
hmasterlockd : std_ulogic;
hready : std_ulogic;
defslv : std_ulogic;
htrans : std_logic_vector(1 downto 0);
hsize : std_logic_vector(2 downto 0);
haddr : std_logic_vector(15 downto 2);
cfgsel : std_ulogic;
cfga11 : std_ulogic;
hrdatam : std_logic_vector(31 downto 0);
hrdatas : std_logic_vector(31 downto 0);
beat : std_logic_vector(3 downto 0);
defmst : std_ulogic;
ldefmst : std_ulogic;
lsplmst : integer range 0 to nahbmx-1;
end record;
constant RESET_ALL : boolean := GRLIB_CONFIG_ARRAY(grlib_sync_reset_enable_all) = 1;
constant RES_r : reg_type := (
hmaster => 0, hmasterd => 0, hslave => 0, hmasterlock => '0',
hmasterlockd => '0', hready => '1', defslv => '0',
htrans => HTRANS_IDLE, hsize => (others => '0'),
haddr => (others => '0'), cfgsel => '0', cfga11 => '0',
hrdatam => (others => '0'), hrdatas => (others => '0'),
beat => (others => '0'), defmst => '0', ldefmst => '0',
lsplmst => 0);
constant RES_split : std_logic_vector(0 to nahbmx-1) := (others => '0');
constant primst : std_logic_vector(NAHBMST downto 0) := conv_std_logic_vector(mprio, NAHBMST+1);
type l0_type is array (0 to 15) of std_logic_vector(2 downto 0);
type l1_type is array (0 to 7) of std_logic_vector(3 downto 0);
type l2_type is array (0 to 3) of std_logic_vector(4 downto 0);
type l3_type is array (0 to 1) of std_logic_vector(5 downto 0);
type tztab_type is array (0 to 15) of std_logic_vector(2 downto 0);
--returns the index number of the highest priority request
--signal in the two lsb bits when indexed with a 4-bit
--request vector with the highest priority signal on the
--lsb. the returned msb bit indicates if a request was
--active ('1' = no request active corresponds to "0000")
constant tztab : tztab_type := ("100", "000", "001", "000",
"010", "000", "001", "000",
"011", "000", "001", "000",
"010", "000", "001", "000");
--calculate the number of the highest priority request signal(up to 64
--requests are supported) in vect_in using a divide and conquer
--algorithm. The lower the index in the vector the higher the priority
--of the signal. First 4-bit slices are indexed in tztab and the msb
--indicates whether there is an active request or not. Then the resulting
--3 bit vectors are compared in pairs (the one corresponding to (3:0) with
--(7:4), (11:8) with (15:12) and so on). If the least significant of the two
--contains an active signal a '0' is added to the msb side (the vector
--becomes one bit wider at each level) to the next level to indicate that
--there are active signals in the lower nibble of the two. Otherwise
--the msb is removed from the vector corresponding to the higher nibble
--and "10" is added if it does not contain active requests and "01" if
--does contain active signals. Thus the msb still indicates if the new
--slice contains active signals and a '1' is added if it is the higher
--part. This results in a 6-bit vector containing the index number
--of the highest priority master in 5:0 if bit 6 is '0' otherwise
--no master requested the bus.
function tz(vect_in : std_logic_vector) return std_logic_vector is
variable vect : std_logic_vector(63 downto 0);
variable l0 : l0_type;
variable l1 : l1_type;
variable l2 : l2_type;
variable l3 : l3_type;
variable l4 : std_logic_vector(6 downto 0);
variable bci_lsb, bci_msb : std_logic_vector(3 downto 0);
variable bco_lsb, bco_msb : std_logic_vector(2 downto 0);
variable sel : std_logic;
begin
vect := (others => '1');
vect(vect_in'length-1 downto 0) := vect_in;
-- level 0
for i in 0 to 7 loop
bci_lsb := vect(8*i+3 downto 8*i);
bci_msb := vect(8*i+7 downto 8*i+4);
--lookup the highest priority request in each nibble
bco_lsb := tztab(conv_integer(bci_lsb));
bco_msb := tztab(conv_integer(bci_msb));
--select which of two nibbles contain the highest priority ACTIVE
--signal, and forward the corresponding vector to the next level
sel := bco_lsb(2);
if sel = '0' then l1(i) := '0' & bco_lsb;
else l1(i) := bco_msb(2) & not bco_msb(2) & bco_msb(1 downto 0); end if;
end loop;
-- level 1
for i in 0 to 3 loop
sel := l1(2*i)(3);
--select which of two 8-bit vectors contain the
--highest priority ACTIVE signal. the msb set at the previous level
--for each 8-bit slice determines this
if sel = '0' then l2(i) := '0' & l1(2*i);
else
l2(i) := l1(2*i+1)(3) & not l1(2*i+1)(3) & l1(2*i+1)(2 downto 0);
end if;
end loop;
-- level 2
for i in 0 to 1 loop
--16-bit vectors, the msb set at the previous level for each 16-bit
--slice determines the higher priority slice
sel := l2(2*i)(4);
if sel = '0' then l3(i) := '0' & l2(2*i);
else
l3(i) := l2(2*i+1)(4) & not l2(2*i+1)(4) & l2(2*i+1)(3 downto 0);
end if;
end loop;
--level 3
--32-bit vectors, the msb set at the previous level for each 32-bit
--slice determines the higher priority slice
if l3(0)(5) = '0' then l4 := '0' & l3(0);
else l4 := l3(1)(5) & not l3(1)(5) & l3(1)(4 downto 0); end if;
return(l4);
end;
--invert the bit order of the hbusreq signals located in vect_in
--since the highest hbusreq has the highest priority but the
--algorithm in tz has the highest priority on lsb
function lz(vect_in : std_logic_vector) return std_logic_vector is
variable vect : std_logic_vector(vect_in'length-1 downto 0);
variable vect2 : std_logic_vector(vect_in'length-1 downto 0);
begin
vect := vect_in;
for i in vect'right to vect'left loop
vect2(i) := vect(vect'left-i);
end loop;
return(tz(vect2));
end;
-- Find next master:
-- * 2 arbitration policies: fixed priority or round-robin
-- * Fixed priority: priority is fixed, highest index has highest priority
-- * Round-robin: arbiter maintains circular queue of masters
-- * (master 0, master 1, ..., master (nahbmx-1)). First requesting master
-- * in the queue is granted access to the bus and moved to the end of the queue.
-- * splitted masters are not granted
-- * bus is re-arbited when current owner does not request the bus,
-- or when it performs non-burst accesses
-- * fix length burst transfers will not be interrupted
-- * incremental bursts should assert hbusreq until last access
procedure selmast(r : in reg_type;
msto : in ahb_mst_out_vector;
rsplit : in std_logic_vector(0 to nahbmx-1);
mast : out integer range 0 to nahbmx-1;
defmst : out std_ulogic) is
variable nmst : nmstarr;
variable nvalid : nvalarr;
variable rrvec : std_logic_vector(nahbmx*2-1 downto 0);
variable zcnt : std_logic_vector(log2(nahbmx)+1 downto 0);
variable hpvec : std_logic_vector(nahbmx-1 downto 0);
variable zcnt2 : std_logic_vector(log2(nahbmx) downto 0);
begin
nvalid(1 to 3) := (others => false); nmst(1 to 3) := (others => 0);
mast := r.hmaster;
defmst := '0';
if nahbm = 1 then
mast := 0;
elsif rrobin = 0 then
hpvec := (others => '0');
for i in 0 to nahbmx-1 loop
--masters which have received split are not granted
if ((rsplit(i) = '0') or (split = 0)) then
hpvec(i) := msto(i).hbusreq;
end if;
end loop;
--check if any bus requests are active (nvalid(2) set to true)
--and determine the index (zcnt2) of the highest priority master
zcnt2 := lz(hpvec)(log2(nahbmx) downto 0);
if zcnt2(log2(nahbmx)) = '0' then nvalid(2) := true; end if;
nmst(2) := conv_integer(not (zcnt2(log2(nahbmx)-1 downto 0)));
--find the default master number
for i in 0 to nahbmx-1 loop
if not ((nmst(3) = defmast) and nvalid(3)) then
nmst(3) := i; nvalid(3) := true;
end if;
end loop;
else
rrvec := (others => '0');
--mask requests up to and including current master. Concatenate
--an unmasked request vector above the masked vector. Otherwise
--the rules are the same as for fixed priority
for i in 0 to nahbmx-1 loop
if ((rsplit(i) = '0') or (split = 0)) then
if (i <= r.hmaster) then rrvec(i) := '0';
else rrvec(i) := msto(i).hbusreq; end if;
rrvec(nahbmx+i) := msto(i).hbusreq;
end if;
end loop;
--find the next master uzing tz which gives priority to lower
--indexes
zcnt := tz(rrvec)(log2(nahbmx)+1 downto 0);
--was there a master requesting the bus?
if zcnt(log2(nahbmx)+1) = '0' then nvalid(2) := true; end if;
nmst(2) := conv_integer(zcnt(log2(nahbmx)-1 downto 0));
--if no other master is requesting the bus select the current one
nmst(3) := r.hmaster; nvalid(3) := true;
--check if any masters configured with higher priority are requesting
--the bus
if mprio /= 0 then
for i in 0 to nahbm-1 loop
if (((rsplit(i) = '0') or (split = 0)) and (primst(i) = '1')) then
if msto(i).hbusreq = '1' then nmst(1) := i; nvalid(1) := true; end if;
end if;
end loop;
end if;
end if;
--select the next master. If for round robin a high priority master
--(mprio) requested the bus if nvalid(1) is true. Otherwise
--if nvalid(2) is true at least one master was requesting the bus
--and the one with highest priority was selected. If none of these
--were true then the default master is selected (nvalid(3) true)
for i in 1 to 3 loop
if nvalid(i) then mast := nmst(i); exit; end if;
end loop;
--if no master was requesting the bus and split is enabled
--then select builtin dummy master which only does
--idle transfers
if (not (nvalid(1) or nvalid(2))) and (split /= 0) then
defmst := orv(rsplit);
end if;
end;
constant MIMAX : integer := log2x(nahbmx) - 1;
constant SIMAX : integer := log2x(nahbs) - 1;
constant IOAREA : std_logic_vector(11 downto 0) :=
conv_std_logic_vector(ioaddr, 12);
constant IOMSK : std_logic_vector(11 downto 0) :=
conv_std_logic_vector(iomask, 12);
constant CFGAREA : std_logic_vector(11 downto 0) :=
conv_std_logic_vector(cfgaddr, 12);
constant CFGMSK : std_logic_vector(11 downto 0) :=
conv_std_logic_vector(cfgmask, 12);
constant FULLPNP : boolean := (fpnpen /= 0);
signal r, rin : reg_type;
signal rsplit, rsplitin : std_logic_vector(0 to nahbmx-1);
-- pragma translate_off
signal lmsti : ahb_mst_in_type;
signal lslvi : ahb_slv_in_type;
-- pragma translate_on
begin
comb : process(rst, msto, slvo, r, rsplit, testen, testrst, scanen, testoen, testsig)
variable v : reg_type;
variable nhmaster: integer range 0 to nahbmx -1;
variable hgrant : std_logic_vector(0 to NAHBMST-1); -- bus grant
variable hsel : std_logic_vector(0 to 31); -- slave select
variable hmbsel : std_logic_vector(0 to NAHBAMR-1);
variable nslave : natural range 0 to 31;
variable vsplit : std_logic_vector(0 to nahbmx-1);
variable bnslave : std_logic_vector(3 downto 0);
variable area : std_logic_vector(1 downto 0);
variable hready : std_ulogic;
variable defslv : std_ulogic;
variable cfgsel : std_ulogic;
variable hresp : std_logic_vector(1 downto 0);
variable hrdata : std_logic_vector(AHBDW-1 downto 0);
variable haddr : std_logic_vector(31 downto 0);
variable hirq : std_logic_vector(NAHBIRQ-1 downto 0);
variable arb : std_ulogic;
variable hconfndx : integer range 0 to 7;
variable vslvi : ahb_slv_in_type;
variable defmst : std_ulogic;
variable tmpv : std_logic_vector(0 to nahbmx-1);
begin
v := r; hgrant := (others => '0'); defmst := '0';
haddr := msto(r.hmaster).haddr;
nhmaster := r.hmaster;
--determine if bus should be rearbitrated. This is done if the current
--master is not performing a locked transfer and if not in the middle
--of burst
arb := '0';
if (r.hmasterlock or r.ldefmst) = '0' then
case msto(r.hmaster).htrans is
when HTRANS_IDLE => arb := '1';
when HTRANS_NONSEQ =>
case msto(r.hmaster).hburst is
when HBURST_SINGLE => arb := '1';
when HBURST_INCR => arb := not msto(r.hmaster).hbusreq;
when others =>
end case;
when HTRANS_SEQ =>
case msto(r.hmaster).hburst is
when HBURST_WRAP4 | HBURST_INCR4 => if (fixbrst = 1) and (r.beat(1 downto 0) = "11") then arb := '1'; end if;
when HBURST_WRAP8 | HBURST_INCR8 => if (fixbrst = 1) and (r.beat(2 downto 0) = "111") then arb := '1'; end if;
when HBURST_WRAP16 | HBURST_INCR16 => if (fixbrst = 1) and (r.beat(3 downto 0) = "1111") then arb := '1'; end if;
when HBURST_INCR => arb := not msto(r.hmaster).hbusreq;
when others =>
end case;
when others => arb := '0';
end case;
end if;
if (split /= 0) then
for i in 0 to nahbmx-1 loop
tmpv(i) := (msto(i).htrans(1) or (msto(i).hbusreq)) and not rsplit(i) and not r.ldefmst;
end loop;
if (r.defmst and orv(tmpv)) = '1' then arb := '1'; end if;
end if;
--rearbitrate bus with selmast. If not arbitrated one must
--ensure that the dummy master is selected for locked splits.
if (arb = '1') then
selmast(r, msto, rsplit, nhmaster, defmst);
elsif (split /= 0) then
defmst := r.defmst;
end if;
-- slave decoding
hsel := (others => '0'); hmbsel := (others => '0');
if fourgslv = 0 then
for i in 0 to nahbs-1 loop
for j in NAHBIR to NAHBCFG-1 loop
area := slvo(i).hconfig(j)(1 downto 0);
case area is
when "10" =>
if ((ioen = 0) or ((IOAREA and IOMSK) /= (haddr(31 downto 20) and IOMSK))) and
((slvo(i).hconfig(j)(31 downto 20) and slvo(i).hconfig(j)(15 downto 4)) =
(haddr(31 downto 20) and slvo(i).hconfig(j)(15 downto 4))) and
(slvo(i).hconfig(j)(15 downto 4) /= "000000000000")
then hsel(i) := '1'; hmbsel(j-NAHBIR) := '1'; end if;
when "11" =>
if ((ioen /= 0) and ((IOAREA and IOMSK) = (haddr(31 downto 20) and IOMSK))) and
((slvo(i).hconfig(j)(31 downto 20) and slvo(i).hconfig(j)(15 downto 4)) =
(haddr(19 downto 8) and slvo(i).hconfig(j)(15 downto 4))) and
(slvo(i).hconfig(j)(15 downto 4) /= "000000000000")
then hsel(i) := '1'; hmbsel(j-NAHBIR) := '1'; end if;
when others =>
end case;
end loop;
end loop;
else
-- There is only one slave on the bus. The slave has only one bar, which
-- maps 4 GB address space.
hsel(0) := '1'; hmbsel(0) := '1';
end if;
if r.defmst = '1' then hsel := (others => '0'); end if;
bnslave(0) := hsel(1) or hsel(3) or hsel(5) or hsel(7) or
hsel(9) or hsel(11) or hsel(13) or hsel(15);
bnslave(1) := hsel(2) or hsel(3) or hsel(6) or hsel(7) or
hsel(10) or hsel(11) or hsel(14) or hsel(15);
bnslave(2) := hsel(4) or hsel(5) or hsel(6) or hsel(7) or
hsel(12) or hsel(13) or hsel(14) or hsel(15);
bnslave(3) := hsel(8) or hsel(9) or hsel(10) or hsel(11) or
hsel(12) or hsel(13) or hsel(14) or hsel(15);
nslave := conv_integer(bnslave(SIMAX downto 0));
if ((((IOAREA and IOMSK) = (haddr(31 downto 20) and IOMSK)) and (ioen /= 0))
or ((IOAREA = haddr(31 downto 20)) and (ioen = 0))) and
((CFGAREA and CFGMSK) = (haddr(19 downto 8) and CFGMSK))
and (cfgmask /= 0)
then cfgsel := '1'; hsel := (others => '0');
else cfgsel := '0'; end if;
if (nslave = 0) and (hsel(0) = '0') and (cfgsel = '0') then defslv := '1';
else defslv := '0'; end if;
if r.defmst = '1' then
cfgsel := '0'; defslv := '1';
end if;
-- error response on undecoded area
v.hready := '0';
hready := slvo(r.hslave).hready; hresp := slvo(r.hslave).hresp;
if r.defslv = '1' then
-- default slave
if (r.htrans = HTRANS_IDLE) or (r.htrans = HTRANS_BUSY) then
hresp := HRESP_OKAY; hready := '1';
else
-- return two-cycle error in case of unimplemented slave access
hresp := HRESP_ERROR; hready := r.hready; v.hready := not r.hready;
end if;
end if;
if acdm = 0 then
hrdata := slvo(r.hslave).hrdata;
else
hrdata := ahbselectdata(slvo(r.hslave).hrdata, r.haddr(4 downto 2), r.hsize);
end if;
if cfgmask /= 0 then
-- plug&play information for masters
if FULLPNP then hconfndx := conv_integer(r.haddr(4 downto 2)); else hconfndx := 0; end if;
if (r.haddr(10 downto MIMAX+6) = zero32(10 downto MIMAX+6)) and (FULLPNP or (r.haddr(4 downto 2) = "000"))
then v.hrdatam := msto(conv_integer(r.haddr(MIMAX+5 downto 5))).hconfig(hconfndx);
else v.hrdatam := (others => '0'); end if;
-- plug&play information for slaves
if (r.haddr(10 downto SIMAX+6) = zero32(10 downto SIMAX+6)) and
(FULLPNP or (r.haddr(4 downto 2) = "000") or (r.haddr(4) = '1'))
then v.hrdatas := slvo(conv_integer(r.haddr(SIMAX+5 downto 5))).hconfig(conv_integer(r.haddr(4 downto 2)));
else v.hrdatas := (others => '0'); end if;
-- device ID, library build and potentially debug information
if r.haddr(10 downto 4) = "1111111" then
if hwdebug = 0 or r.haddr(3 downto 2) = "00" then
v.hrdatas(15 downto 0) := conv_std_logic_vector(LIBVHDL_BUILD, 16);
v.hrdatas(31 downto 16) := conv_std_logic_vector(devid, 16);
elsif r.haddr(3 downto 2) = "01" then
for i in 0 to nahbmx-1 loop v.hrdatas(i) := msto(i).hbusreq; end loop;
else
for i in 0 to nahbmx-1 loop v.hrdatas(i) := rsplit(i); end loop;
end if;
end if;
if r.cfgsel = '1' then
hrdata := (others => '0');
-- default slave
if (r.htrans = HTRANS_IDLE) or (r.htrans = HTRANS_BUSY) then
hresp := HRESP_OKAY; hready := '1';
else
-- return two-cycle read/write respons
hresp := HRESP_OKAY; hready := r.hready; v.hready := not r.hready;
end if;
if r.cfga11 = '0' then hrdata := ahbdrivedata(r.hrdatam);
else hrdata := ahbdrivedata(r.hrdatas); end if;
end if;
end if;
--degrant all masters when split occurs for locked access
if (r.hmasterlockd = '1') then
if (hresp = HRESP_RETRY) or ((split /= 0) and (hresp = HRESP_SPLIT)) then
nhmaster := r.hmaster;
end if;
if split /= 0 then
if hresp = HRESP_SPLIT then
v.ldefmst := '1'; defmst := '1';
v.lsplmst := nhmaster;
end if;
end if;
end if;
if split /= 0 and r.ldefmst = '1' then
if rsplit(r.lsplmst) = '0' then
v.ldefmst := '0'; defmst := '0';
end if;
end if;
if (split = 0) or (defmst = '0') then hgrant(nhmaster) := '1'; end if;
-- latch active master and slave
if hready = '1' then
v.hmaster := nhmaster; v.hmasterd := r.hmaster;
v.hsize := msto(r.hmaster).hsize;
v.hslave := nslave; v.defslv := defslv;
v.hmasterlockd := r.hmasterlock;
if (split = 0) or (r.defmst = '0') then v.htrans := msto(r.hmaster).htrans;
else v.htrans := HTRANS_IDLE; end if;
v.cfgsel := cfgsel;
v.cfga11 := msto(r.hmaster).haddr(11);
v.haddr := msto(r.hmaster).haddr(15 downto 2);
if (msto(r.hmaster).htrans = HTRANS_NONSEQ) or (msto(r.hmaster).htrans = HTRANS_IDLE) then
v.beat := "0001";
elsif (msto(r.hmaster).htrans = HTRANS_SEQ) then
if (fixbrst = 1) then v.beat := r.beat + 1; end if;
end if;
if (split /= 0) then v.defmst := defmst; end if;
end if;
--assign new hmasterlock, v.hmaster is used because if hready
--then master can have changed, and when not hready then the
--previous master will still be selected
v.hmasterlock := msto(v.hmaster).hlock or (r.hmasterlock and not hready);
--if the master asserting hlock received a SPLIT/RETRY response
--to the previous access then disregard the current lock request.
--the bus will otherwise be locked when the previous access is
--retried instead of treating hlock as coupled to the next access.
--use hmasterlockd to keep the bus locked for SPLIT/RETRY to locked
--accesses.
if v.hmaster = r.hmasterd and slvo(r.hslave).hresp(1) = '1' then
if r.hmasterlockd = '0' then
v.hmasterlock := '0'; v.hmasterlockd := '0';
end if;
end if;
-- split support
vsplit := (others => '0');
if SPLIT /= 0 then
vsplit := rsplit;
if slvo(r.hslave).hresp = HRESP_SPLIT then vsplit(r.hmasterd) := '1'; end if;
for i in 0 to nahbs-1 loop
for j in 0 to nahbmx-1 loop
vsplit(j) := vsplit(j) and not slvo(i).hsplit(j);
end loop;
end loop;
end if;
-- interrupt merging
hirq := (others => '0');
if disirq = 0 then
for i in 0 to nahbs-1 loop hirq := hirq or slvo(i).hirq; end loop;
for i in 0 to nahbm-1 loop hirq := hirq or msto(i).hirq; end loop;
end if;
if (split = 0) or (r.defmst = '0') then
vslvi.haddr := haddr;
vslvi.htrans := msto(r.hmaster).htrans;
vslvi.hwrite := msto(r.hmaster).hwrite;
vslvi.hsize := msto(r.hmaster).hsize;
vslvi.hburst := msto(r.hmaster).hburst;
vslvi.hready := hready;
vslvi.hprot := msto(r.hmaster).hprot;
-- vslvi.hmastlock := msto(r.hmaster).hlock;
vslvi.hmastlock := r.hmasterlock;
vslvi.hmaster := conv_std_logic_vector(r.hmaster, 4);
vslvi.hsel := hsel(0 to NAHBSLV-1);
vslvi.hmbsel := hmbsel;
vslvi.hirq := hirq;
else
vslvi := ahbs_in_none;
vslvi.hready := hready;
vslvi.hirq := hirq;
end if;
if acdm = 0 then
vslvi.hwdata := msto(r.hmasterd).hwdata;
else
vslvi.hwdata := ahbselectdata(msto(r.hmasterd).hwdata, r.haddr(4 downto 2), r.hsize);
end if;
vslvi.testen := testen;
vslvi.testrst := testrst;
vslvi.scanen := scanen and testen;
vslvi.testoen := testoen;
vslvi.testin := testen & (scanen and testen) & testsig;
-- reset operation
if (not RESET_ALL) and (rst = '0') then
v.hmaster := RES_r.hmaster; v.hmasterlock := RES_r.hmasterlock;
vsplit := (others => '0');
v.htrans := RES_r.htrans; v.defslv := RES_r.defslv;
v.hslave := RES_r.hslave; v.cfgsel := RES_r.cfgsel;
v.defmst := RES_r.defmst; v.ldefmst := RES_r.ldefmst;
end if;
-- drive master inputs
msti.hgrant <= hgrant;
msti.hready <= hready;
msti.hresp <= hresp;
msti.hrdata <= hrdata;
msti.hirq <= hirq;
msti.testen <= testen;
msti.testrst <= testrst;
msti.scanen <= scanen and testen;
msti.testoen <= testoen;
msti.testin <= testen & (scanen and testen) & testsig;
-- drive slave inputs
slvi <= vslvi;
-- pragma translate_off
--drive internal signals to bus monitor
lslvi <= vslvi;
lmsti.hgrant <= hgrant;
lmsti.hready <= hready;
lmsti.hresp <= hresp;
lmsti.hrdata <= hrdata;
lmsti.hirq <= hirq;
-- pragma translate_on
if split = 0 then v.ldefmst := '0'; v.lsplmst := 0; end if;
rin <= v; rsplitin <= vsplit;
end process;
reg0 : process(clk)
begin
if rising_edge(clk) then
r <= rin;
if RESET_ALL and rst = '0' then
r <= RES_r;
end if;
end if;
if (split = 0) then r.defmst <= '0'; end if;
end process;
splitreg : if SPLIT /= 0 generate
reg1 : process(clk)
begin
if rising_edge(clk) then
rsplit <= rsplitin;
if RESET_ALL and rst = '0' then
rsplit <= RES_split;
end if;
end if;
end process;
end generate;
nosplitreg : if SPLIT = 0 generate
rsplit <= (others => '0');
end generate;
-- pragma translate_off
ahblog : if ahbtrace /= 0 generate
log : process (clk)
variable hwrite : std_logic;
variable hsize : std_logic_vector(2 downto 0);
variable htrans : std_logic_vector(1 downto 0);
variable hmaster : std_logic_vector(3 downto 0);
variable haddr : std_logic_vector(31 downto 0);
variable hwdata, hrdata : std_logic_vector(127 downto 0);
variable mbit, bitoffs : integer;
variable t : integer;
begin
if rising_edge(clk) then
if htrans(1)='1' and lmsti.hready='0' and (lmsti.hresp="01") then
if hwrite = '1' then
grlib.testlib.print("mst" & tost(hmaster) & ": " & tost(haddr) & " write " & tost(mbit/8) & " bytes [" & tost(lslvi.hwdata(mbit-1+bitoffs downto bitoffs)) & "] - ERROR!");
else
grlib.testlib.print("mst" & tost(hmaster) & ": " & tost(haddr) & " read " & tost(mbit/8) & " bytes [" & tost(lmsti.hrdata(mbit-1+bitoffs downto bitoffs)) & "] - ERROR!");
end if;
end if;
if ((htrans(1) and lmsti.hready) = '1') and (lmsti.hresp = "00") then
mbit := 2**conv_integer(hsize)*8;
bitoffs := 0;
if mbit < ahbdw then
bitoffs := mbit * conv_integer(haddr(log2(ahbdw/8)-1 downto conv_integer(hsize)));
bitoffs := lslvi.hwdata'length-mbit-bitoffs;
end if;
t := (now/1 ns);
if hwrite = '1' then
grlib.testlib.print("mst" & tost(hmaster) & ": " & tost(haddr) & " write " & tost(mbit/8) & " bytes [" & tost(lslvi.hwdata(mbit-1+bitoffs downto bitoffs)) & "]");
else
grlib.testlib.print("mst" & tost(hmaster) & ": " & tost(haddr) & " read " & tost(mbit/8) & " bytes [" & tost(lmsti.hrdata(mbit-1+bitoffs downto bitoffs)) & "]");
end if;
end if;
if lmsti.hready = '1' then
hwrite := lslvi.hwrite;
hsize := lslvi.hsize;
haddr := lslvi.haddr;
htrans := lslvi.htrans;
hmaster := lslvi.hmaster;
end if;
end if;
end process;
end generate;
mon0 : if enbusmon /= 0 generate
mon : ahbmon
generic map(
asserterr => asserterr,
assertwarn => assertwarn,
hmstdisable => hmstdisable,
hslvdisable => hslvdisable,
arbdisable => arbdisable,
nahbm => nahbm,
nahbs => nahbs)
port map(
rst => rst,
clk => clk,
ahbmi => lmsti,
ahbmo => msto,
ahbsi => lslvi,
ahbso => slvo,
err => open);
end generate;
diag : process
type ahbsbank_type is record
start : std_logic_vector(31 downto 8);
stop : std_logic_vector(31 downto 8);
io : std_ulogic;
end record;
type ahbsbanks_type is array (0 to 3) of ahbsbank_type;
type memmap_type is array (0 to nahbs-1) of ahbsbanks_type;
variable k : integer;
variable mask : std_logic_vector(11 downto 0);
variable device : std_logic_vector(11 downto 0);
variable devicei : integer;
variable vendor : std_logic_vector( 7 downto 0);
variable area : std_logic_vector( 1 downto 0);
variable vendori : integer;
variable iosize, tmp : integer;
variable iounit : string(1 to 5) := " byte";
variable memtype : string(1 to 9);
variable iostart : std_logic_vector(11 downto 0) := IOAREA and IOMSK;
variable cfgstart : std_logic_vector(11 downto 0) := CFGAREA and CFGMSK;
variable L1 : line := new string'("");
variable S1 : string(1 to 255);
variable memmap : memmap_type;
begin
wait for 2 ns;
if debug = 0 then wait; end if;
if debug > 0 then
k := 0; mask := IOMSK;
while (k<12) and (mask(k) = '0') loop k := k+1; end loop;
print("ahbctrl: AHB arbiter/multiplexer rev 1");
if ioen /= 0 then
print("ahbctrl: Common I/O area at " & tost(iostart) & "00000, " & tost(2**k) & " Mbyte");
else
print("ahbctrl: Common I/O area disabled");
end if;
print("ahbctrl: AHB masters: " & tost(nahbm) & ", AHB slaves: " & tost(nahbs));
if cfgmask /= 0 then
print("ahbctrl: Configuration area at " & tost(iostart & cfgstart) & "00, 4 kbyte");
else
print("ahbctrl: Configuration area disabled");
end if;
end if;
for i in 0 to nahbm-1 loop
vendor := msto(i).hconfig(0)(31 downto 24);
vendori := conv_integer(vendor);
if vendori /= 0 then
if debug > 1 then
device := msto(i).hconfig(0)(23 downto 12);
devicei := conv_integer(device);
print("ahbctrl: mst" & tost(i) & ": " & iptable(vendori).vendordesc &
iptable(vendori).device_table(devicei));
end if;
for j in 1 to NAHBIR-1 loop
assert (msto(i).hconfig(j) = zx or FULLPNP or ccheck = 0 or cfgmask = 0)
report "AHB master " & tost(i) & " propagates non-zero user defined PnP data, " &
"but AHBCTRL full PnP decoding has not been enabled (check fpnpen VHDL generic)"
severity warning;
end loop;
assert (msto(i).hindex = i) or (icheck = 0)
report "AHB master index error on master " & tost(i) &
". Detected index value " & tost(msto(i).hindex) severity failure;
else
for j in 0 to NAHBCFG-1 loop
assert (msto(i).hconfig(j) = zx or ccheck = 0)
report "AHB master " & tost(i) & " appears to be disabled, " &
"but the master config record is not driven to zero " &
"(check vendor ID or drive unused bus index with appropriate values)."
severity warning;
end loop;
end if;
end loop;
if nahbm < NAHBMST then
for i in nahbm to NAHBMST-1 loop
for j in 0 to NAHBCFG-1 loop
assert (msto(i).hconfig(j) = zx or ccheck = 0)
report "AHB master " & tost(i) & " is outside the range of " &
"decoded master indexes but the master config record is not driven to zero " &
"(check nahbm VHDL generic)."
severity warning;
end loop;
end loop;
end if;
for i in 0 to nahbs-1 loop
vendor := slvo(i).hconfig(0)(31 downto 24);
vendori := conv_integer(vendor);
if vendori /= 0 then
if debug > 1 then
device := slvo(i).hconfig(0)(23 downto 12);
devicei := conv_integer(device);
std.textio.write(L1, "ahbctrl: slv" & tost(i) & ": " & iptable(vendori).vendordesc &
iptable(vendori).device_table(devicei));
std.textio.writeline(OUTPUT, L1);
end if;
for j in 1 to NAHBIR-1 loop
assert (slvo(i).hconfig(j) = zx or FULLPNP or ccheck = 0 or cfgmask = 0)
report "AHB slave " & tost(i) & " propagates non-zero user defined PnP data, " &
"but AHBCTRL full PnP decoding has not been enabled (check fpnpen VHDL generic)."
severity warning;
end loop;
for j in NAHBIR to NAHBCFG-1 loop
area := slvo(i).hconfig(j)(1 downto 0);
mask := slvo(i).hconfig(j)(15 downto 4);
memmap(i)(j mod NAHBIR).start := (others => '0');
memmap(i)(j mod NAHBIR).stop := (others => '0');
memmap(i)(j mod NAHBIR).io := slvo(i).hconfig(j)(0);
if (mask /= "000000000000" or fourgslv = 1) then
case area is
when "01" =>
when "10" =>
k := 0;
while (k<12) and (mask(k) = '0') loop k := k+1; end loop;
if debug > 1 then
std.textio.write(L1, "ahbctrl: memory at " &
tost(slvo(i).hconfig(j)(31 downto 20) and mask) &
"00000, size "& tost(2**k) & " Mbyte");
if slvo(i).hconfig(j)(16) = '1' then
std.textio.write(L1, string'(", cacheable"));
end if;
if slvo(i).hconfig(j)(17) = '1' then
std.textio.write(L1, string'(", prefetch"));
end if;
std.textio.writeline(OUTPUT, L1);
end if;
memmap(i)(j mod NAHBIR).start(31 downto 20) := slvo(i).hconfig(j)(31 downto 20);
memmap(i)(j mod NAHBIR).start(31 downto 20) :=
(slvo(i).hconfig(j)(31 downto 20) and mask);
memmap(i)(j mod NAHBIR).start(19 downto 8) := (others => '0');
memmap(i)(j mod NAHBIR).stop := memmap(i)(j mod NAHBIR).start + 2**(k+12) - 1;
-- Be verbose if an address with bits set outside the area
-- selected by the mask is encountered
assert ((slvo(i).hconfig(j)(31 downto 20) and not mask) = zero32(11 downto 0)) report
"AHB slave " & tost(i) & " may decode an area larger than intended. Bar " &
tost(j mod NAHBIR) & " will have base address " &
tost(slvo(i).hconfig(j)(31 downto 20) and mask) &
"00000, the intended base address may have been " &
tost(slvo(i).hconfig(j)(31 downto 20)) & "00000"
severity warning;
when "11" =>
if ioen /= 0 then
k := 0;
while (k<12) and (mask(k) = '0') loop k := k+1; end loop;
memmap(i)(j mod NAHBIR).start := iostart & (slvo(i).hconfig(j)(31 downto 20) and
slvo(i).hconfig(j)(15 downto 4));
memmap(i)(j mod NAHBIR).stop := memmap(i)(j mod NAHBIR).start + 2**k - 1;
if debug > 1 then
iosize := 256 * 2**k; iounit(1) := ' ';
if (iosize > 1023) then
iosize := iosize/1024; iounit(1) := 'k';
end if;
print("ahbctrl: I/O port at " & tost(iostart &
((slvo(i).hconfig(j)(31 downto 20)) and slvo(i).hconfig(j)(15 downto 4))) &
"00, size "& tost(iosize) & iounit);
end if;
assert ((slvo(i).hconfig(j)(31 downto 20) and not mask) = zero32(11 downto 0)) report
"AHB slave " & tost(i) & " may decode an I/O area larger than intended. Bar " &
tost(j mod NAHBIR) & " will have base address " &
tost(iostart & (slvo(i).hconfig(j)(31 downto 20) and mask)) &
"00, the intended base address may have been " &
tost(iostart & slvo(i).hconfig(j)(31 downto 20)) & "00"
severity warning;
else
assert false report
"AHB slave " & tost(i) & " maps bar " & tost(j mod NAHBIR) &
" to the IO area, but this AHBCTRL has been configured with VHDL generic ioen = 0"
severity warning;
end if;
when others =>
end case;
end if;
end loop;
assert (slvo(i).hindex = i) or (icheck = 0)
report "AHB slave index error on slave " & tost(i) &
". Detected index value " & tost(slvo(i).hindex) severity failure;
if mcheck /= 0 then
for j in 0 to i loop
for k in memmap(i)'range loop
if memmap(i)(k).stop /= zero32(memmap(i)(k).stop'range) then
for l in memmap(j)'range loop
assert ((memmap(i)(k).start >= memmap(j)(l).stop) or
(memmap(i)(k).stop <= memmap(j)(l).start) or
(mcheck /= 2 and (memmap(i)(k).io xor memmap(j)(l).io) = '1') or
(i = j and k = l))
report "AHB slave " & tost(i) & " bank " & tost(k) &
" intersects with AHB slave " & tost(j) & " bank " & tost(l)
severity failure;
end loop;
end if;
end loop;
end loop;
end if;
else
for j in 0 to NAHBCFG-1 loop
assert (slvo(i).hconfig(j) = zx or ccheck = 0)
report "AHB slave " & tost(i) & " appears to be disabled, " &
"but the slave config record is not driven to zero " &
"(check vendor ID or drive unused bus index with appropriate values)."
severity warning;
end loop;
end if;
end loop;
if nahbs < NAHBSLV then
for i in nahbs to NAHBSLV-1 loop
for j in 0 to NAHBCFG-1 loop
assert (slvo(i).hconfig(j) = zx or ccheck = 0)
report "AHB slave " & tost(i) & " is outside the range of " &
"decoded slave indexes but the slave config record is not driven to zero " &
"(check nahbs VHDL generic)."
severity warning;
end loop;
end loop;
end if;
wait;
end process;
-- pragma translate_on
end;
|
------------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2012 Aeroflex Gaisler
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.libdcom.all;
use gaisler.sim.all;
use work.debug.all;
library techmap;
use techmap.gencomp.all;
library micron;
use micron.components.all;
library grlib;
use grlib.stdlib.all;
use work.config.all; -- configuration
entity testbench is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
romdepth : integer := 22 -- rom address depth (flash 4 MB)
);
end;
architecture behav of testbench is
constant promfile : string := "prom.srec";
constant sdramfile : string := "ram.srec";
signal clock_50 : std_logic := '0';
signal led : std_logic_vector(7 downto 0);
signal key : std_logic_vector(1 downto 0);
signal sw : std_logic_vector(3 downto 0);
signal dram_ba : std_logic_vector(1 downto 0);
signal dram_dqm : std_logic_vector(1 downto 0);
signal dram_ras_n : std_ulogic;
signal dram_cas_n : std_ulogic;
signal dram_cke : std_ulogic;
signal dram_clk : std_ulogic;
signal dram_we_n : std_ulogic;
signal dram_cs_n : std_ulogic;
signal dram_dq : std_logic_vector(15 downto 0);
signal dram_addr : std_logic_vector(12 downto 0);
signal epcs_data0 : std_logic;
signal epcs_dclk : std_logic;
signal epcs_ncso : std_logic;
signal epcs_asdo : std_logic;
signal i2c_sclk : std_logic;
signal i2c_sdat : std_logic;
signal g_sensor_cs_n : std_ulogic;
signal g_sensor_int : std_ulogic;
signal adc_cs_n : std_ulogic;
signal adc_saddr : std_ulogic;
signal adc_sclk : std_ulogic;
signal adc_sdat : std_ulogic;
signal gpio_2 : std_logic_vector(12 downto 0);
signal gpio_2_in : std_logic_vector(2 downto 0);
signal gpio_1_in : std_logic_vector(1 downto 0);
signal gpio_1 : std_logic_vector(33 downto 0);
signal gpio_0_in : std_logic_vector(1 downto 0);
signal gpio_0 : std_logic_vector(33 downto 0);
begin
clock_50 <= not clock_50 after 10 ns; --50 MHz clk
key(0) <= '0', '1' after 300 ns;
key(1) <= '1'; -- DSU break, disabled
sw <= (others => 'H');
gpio_0 <= (others => 'H');
gpio_0_in <= (others => 'H');
gpio_1 <= (others => 'H');
gpio_1_in <= (others => 'H');
gpio_2 <= (others => 'H');
gpio_2_in <= (others => 'H');
led(5 downto 0) <= (others => 'H');
d3 : entity work.leon3mp
generic map ( fabtech, memtech, padtech, clktech, disas, dbguart, pclow )
port map (
clock_50 => clock_50,
led => led,
key => key,
sw => sw,
dram_ba => dram_ba,
dram_dqm => dram_dqm,
dram_ras_n => dram_ras_n,
dram_cas_n => dram_cas_n,
dram_cke => dram_cke,
dram_clk => dram_clk,
dram_we_n => dram_we_n,
dram_cs_n => dram_cs_n,
dram_dq => dram_dq,
dram_addr => dram_addr,
epcs_data0 => epcs_data0,
epcs_dclk => epcs_dclk,
epcs_ncso => epcs_ncso,
epcs_asdo => epcs_asdo,
i2c_sclk => i2c_sclk,
i2c_sdat => i2c_sdat,
g_sensor_cs_n => g_sensor_cs_n,
g_sensor_int => g_sensor_int,
adc_cs_n => adc_cs_n,
adc_saddr => adc_saddr,
adc_sclk => adc_sclk,
adc_sdat => adc_sdat,
gpio_2 => gpio_2,
gpio_2_in => gpio_2_in,
gpio_1_in => gpio_1_in,
gpio_1 => gpio_1,
gpio_0_in => gpio_0_in,
gpio_0 => gpio_0);
sd1 : if (CFG_SDCTRL /= 0) generate
u1: entity work.mt48lc16m16a2 generic map (addr_bits => 13, col_bits => 8, index => 1024, fname => sdramfile)
PORT MAP(
Dq => dram_dq, Addr => dram_addr, Ba => dram_ba, Clk => dram_clk,
Cke => dram_cke, Cs_n => dram_cs_n, Ras_n => dram_ras_n,
Cas_n => dram_cas_n, We_n => dram_we_n, Dqm => dram_dqm);
end generate;
dram_dq <= buskeep(dram_dq) after 5 ns;
spif : if CFG_SPIMCTRL /= 0 generate
spi0: spi_flash
generic map (
ftype => 4,
debug => 0,
fname => promfile,
readcmd => CFG_SPIMCTRL_READCMD,
dummybyte => CFG_SPIMCTRL_DUMMYBYTE,
dualoutput => CFG_SPIMCTRL_DUALOUTPUT,
memoffset => CFG_SPIMCTRL_OFFSET)
port map (
sck => epcs_dclk,
di => epcs_asdo,
do => epcs_data0,
csn => epcs_ncso,
sd_cmd_timeout => open,
sd_data_timeout => open);
end generate;
iuerr : process
begin
wait for 2500 ns;
if to_x01(led(6)) = '1' then wait on led(6); end if;
assert (to_x01(led(6)) = '1')
report "*** IU in error mode, simulation halted ***"
severity failure ;
end process;
end ;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity phonybench is
generic (
GENSTR : string := "adrien";
GENSTDLV : std_logic_vector(5 downto 0) := "111000";
GENSTDL : std_logic := '1';
GENNAT : natural := 22
);
end phonybench;
architecture bench of phonybench is
type char2std_t is array(character) of std_ulogic;
constant char2std_c : char2std_t := (
'U' => 'U',
'X' => 'X',
'0' => '0',
'1' => '1',
'Z' => 'Z',
'W' => 'W',
'L' => 'L',
'H' => 'H',
'-' => '-',
others => 'X'
);
function str2std(arg : string) return std_logic_vector is
variable result : std_logic_vector(arg'length - 1 downto 0);
variable j : integer;
begin
j := arg'length - 1;
for i in arg'range loop
result(j) := char2std_c(arg(i));
j := j - 1;
end loop;
return result;
end function;
signal sigvec1 : std_logic_vector(5 downto 0) := str2std(GENSTR);
signal sigvec2 : std_logic_vector(5 downto 0) := GENSTDLV;
signal siglog : std_logic := GENSTDL;
signal signat : natural := GENNAT;
signal clk : std_logic := '0';
begin
clk <= not clk after 5 ms;
sigvec1 <= str2std(GENSTR);
sigvec2 <= GENSTDLV;
siglog <= GENSTDL;
signat <= GENNAT;
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity phonybench is
generic (
GENSTR : string := "adrien";
GENSTDLV : std_logic_vector(5 downto 0) := "111000";
GENSTDL : std_logic := '1';
GENNAT : natural := 22
);
end phonybench;
architecture bench of phonybench is
type char2std_t is array(character) of std_ulogic;
constant char2std_c : char2std_t := (
'U' => 'U',
'X' => 'X',
'0' => '0',
'1' => '1',
'Z' => 'Z',
'W' => 'W',
'L' => 'L',
'H' => 'H',
'-' => '-',
others => 'X'
);
function str2std(arg : string) return std_logic_vector is
variable result : std_logic_vector(arg'length - 1 downto 0);
variable j : integer;
begin
j := arg'length - 1;
for i in arg'range loop
result(j) := char2std_c(arg(i));
j := j - 1;
end loop;
return result;
end function;
signal sigvec1 : std_logic_vector(5 downto 0) := str2std(GENSTR);
signal sigvec2 : std_logic_vector(5 downto 0) := GENSTDLV;
signal siglog : std_logic := GENSTDL;
signal signat : natural := GENNAT;
signal clk : std_logic := '0';
begin
clk <= not clk after 5 ms;
sigvec1 <= str2std(GENSTR);
sigvec2 <= GENSTDLV;
siglog <= GENSTDL;
signat <= GENNAT;
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity phonybench is
generic (
GENSTR : string := "adrien";
GENSTDLV : std_logic_vector(5 downto 0) := "111000";
GENSTDL : std_logic := '1';
GENNAT : natural := 22
);
end phonybench;
architecture bench of phonybench is
type char2std_t is array(character) of std_ulogic;
constant char2std_c : char2std_t := (
'U' => 'U',
'X' => 'X',
'0' => '0',
'1' => '1',
'Z' => 'Z',
'W' => 'W',
'L' => 'L',
'H' => 'H',
'-' => '-',
others => 'X'
);
function str2std(arg : string) return std_logic_vector is
variable result : std_logic_vector(arg'length - 1 downto 0);
variable j : integer;
begin
j := arg'length - 1;
for i in arg'range loop
result(j) := char2std_c(arg(i));
j := j - 1;
end loop;
return result;
end function;
signal sigvec1 : std_logic_vector(5 downto 0) := str2std(GENSTR);
signal sigvec2 : std_logic_vector(5 downto 0) := GENSTDLV;
signal siglog : std_logic := GENSTDL;
signal signat : natural := GENNAT;
signal clk : std_logic := '0';
begin
clk <= not clk after 5 ms;
sigvec1 <= str2std(GENSTR);
sigvec2 <= GENSTDLV;
siglog <= GENSTDL;
signat <= GENNAT;
end architecture;
|
------------------------------------------------------------------------
--
-- This source file may be used and distributed without restriction.
-- No declarations or definitions shall be added to this package.
-- This package cannot be sold or distributed for profit.
--
-- ****************************************************************
-- * *
-- * W A R N I N G *
-- * *
-- * This DRAFT version IS NOT endorsed or approved by IEEE *
-- * *
-- ****************************************************************
--
-- Title: PACKAGE MATH_REAL
--
-- Library: This package shall be compiled into a library
-- symbolically named IEEE.
--
-- Purpose: VHDL declarations for mathematical package MATH_REAL
-- which contains common real constants, common real
-- functions, and real trascendental functions.
--
-- Author: IEEE VHDL Math Package Study Group
--
-- Notes:
-- The package body shall be considered the formal definition of
-- the semantics of this package. Tool developers may choose to implement
-- the package body in the most efficient manner available to them.
--
-- History:
-- Version 0.1 (Strawman) Jose A. Torres 6/22/92
-- Version 0.2 Jose A. Torres 1/15/93
-- Version 0.3 Jose A. Torres 4/13/93
-- Version 0.4 Jose A. Torres 4/19/93
-- Version 0.5 Jose A. Torres 4/20/93 Added RANDOM()
-- Version 0.6 Jose A. Torres 4/23/93 Renamed RANDOM as
-- UNIFORM. Modified
-- rights banner.
-- Version 0.7 Jose A. Torres 5/28/93 Rev up for compatibility
-- with package body.
-------------------------------------------------------------
Library IEEE;
Package MATH_REAL is
--
-- commonly used constants
--
constant MATH_E : real := 2.71828_18284_59045_23536;
-- value of e
constant MATH_1_E: real := 0.36787_94411_71442_32160;
-- value of 1/e
constant MATH_PI : real := 3.14159_26535_89793_23846;
-- value of pi
constant MATH_1_PI : real := 0.31830_98861_83790_67154;
-- value of 1/pi
constant MATH_LOG_OF_2: real := 0.69314_71805_59945_30942;
-- natural log of 2
constant MATH_LOG_OF_10: real := 2.30258_50929_94045_68402;
-- natural log of10
constant MATH_LOG2_OF_E: real := 1.44269_50408_88963_4074;
-- log base 2 of e
constant MATH_LOG10_OF_E: real := 0.43429_44819_03251_82765;
-- log base 10 of e
constant MATH_SQRT2: real := 1.41421_35623_73095_04880;
-- sqrt of 2
constant MATH_SQRT1_2: real := 0.70710_67811_86547_52440;
-- sqrt of 1/2
constant MATH_SQRT_PI: real := 1.77245_38509_05516_02730;
-- sqrt of pi
constant MATH_DEG_TO_RAD: real := 0.01745_32925_19943_29577;
-- conversion factor from degree to radian
constant MATH_RAD_TO_DEG: real := 57.29577_95130_82320_87685;
-- conversion factor from radian to degree
--
-- attribute for functions whose implementation is foreign (C native)
--
attribute FOREIGN : string; -- predefined attribute in VHDL-1992
--
-- function declarations
--
function SIGN (X: real ) return real;
-- returns 1.0 if X > 0.0; 0.0 if X == 0.0; -1.0 if X < 0.0
function CEIL (X : real ) return real;
-- returns smallest integer value (as real) not less than X
function FLOOR (X : real ) return real;
-- returns largest integer value (as real) not greater than X
function ROUND (X : real ) return real;
-- returns integer FLOOR(X + 0.5) if X > 0;
-- return integer CEIL(X - 0.5) if X < 0
function FMAX (X, Y : real ) return real;
-- returns the algebraically larger of X and Y
function FMIN (X, Y : real ) return real;
-- returns the algebraically smaller of X and Y
procedure UNIFORM (variable Seed1,Seed2:inout integer; variable X:out real);
-- returns a pseudo-random number with uniform distribution in the
-- interval (0.0, 1.0).
-- Before the first call to UNIFORM, the seed values (Seed1, Seed2) must
-- be initialized to values in the range [1, 2147483562] and
-- [1, 2147483398] respectively. The seed values are modified after
-- each call to UNIFORM.
-- This random number generator is portable for 32-bit computers, and
-- it has period ~2.30584*(10**18) for each set of seed values.
--
-- For VHDL-1992, the seeds will be global variables, functions to
-- initialize their values (INIT_SEED) will be provided, and the UNIFORM
-- procedure call will be modified accordingly.
function SRAND (seed: in integer ) return integer;
--
-- sets value of seed for sequence of
-- pseudo-random numbers.
-- It uses the foreign native C function srand().
attribute FOREIGN of SRAND : function is "C_NATIVE";
function RAND return integer;
--
-- returns an integer pseudo-random number with uniform distribution.
-- It uses the foreign native C function rand().
-- Seed for the sequence is initialized with the
-- SRAND() function and value of the seed is changed every
-- time SRAND() is called, but it is not visible.
-- The range of generated values is platform dependent.
attribute FOREIGN of RAND : function is "C_NATIVE";
function GET_RAND_MAX return integer;
--
-- returns the upper bound of the range of the
-- pseudo-random numbers generated by RAND().
-- The support for this function is platform dependent, and
-- it uses foreign native C functions or constants.
-- It may not be available in some platforms.
-- Note: the value of (RAND() / GET_RAND_MAX()) is a
-- pseudo-random number distributed between 0 & 1.
attribute FOREIGN of GET_RAND_MAX : function is "C_NATIVE";
function SQRT (X : real ) return real;
-- returns square root of X; X >= 0
function CBRT (X : real ) return real;
-- returns cube root of X
function "**" (X : integer; Y : real) return real;
-- returns Y power of X ==> X**Y;
-- error if X = 0 and Y <= 0.0
-- error if X < 0 and Y does not have an integer value
function "**" (X : real; Y : real) return real;
-- returns Y power of X ==> X**Y;
-- error if X = 0.0 and Y <= 0.0
-- error if X < 0.0 and Y does not have an integer value
function EXP (X : real ) return real;
-- returns e**X; where e = MATH_E
function LOG (X : real ) return real;
-- returns natural logarithm of X; X > 0
function LOG (BASE: positive; X : real) return real;
-- returns logarithm base BASE of X; X > 0
function SIN (X : real ) return real;
-- returns sin X; X in radians
function COS ( X : real ) return real;
-- returns cos X; X in radians
function TAN (X : real ) return real;
-- returns tan X; X in radians
-- X /= ((2k+1) * PI/2), where k is an integer
function ASIN (X : real ) return real;
-- returns -PI/2 < asin X < PI/2; | X | <= 1
function ACOS (X : real ) return real;
-- returns 0 < acos X < PI; | X | <= 1
function ATAN (X : real) return real;
-- returns -PI/2 < atan X < PI/2
function ATAN2 (X : real; Y : real) return real;
-- returns atan (X/Y); -PI < atan2(X,Y) < PI; Y /= 0.0
function SINH (X : real) return real;
-- hyperbolic sine; returns (e**X - e**(-X))/2
function COSH (X : real) return real;
-- hyperbolic cosine; returns (e**X + e**(-X))/2
function TANH (X : real) return real;
-- hyperbolic tangent; -- returns (e**X - e**(-X))/(e**X + e**(-X))
function ASINH (X : real) return real;
-- returns ln( X + sqrt( X**2 + 1))
function ACOSH (X : real) return real;
-- returns ln( X + sqrt( X**2 - 1)); X >= 1
function ATANH (X : real) return real;
-- returns (ln( (1 + X)/(1 - X)))/2 ; | X | < 1
end MATH_REAL;
---------------------------------------------------------------
--
-- This source file may be used and distributed without restriction.
-- No declarations or definitions shall be included in this package.
-- This package cannot be sold or distributed for profit.
--
-- ****************************************************************
-- * *
-- * W A R N I N G *
-- * *
-- * This DRAFT version IS NOT endorsed or approved by IEEE *
-- * *
-- ****************************************************************
--
-- Title: PACKAGE MATH_COMPLEX
--
-- Purpose: VHDL declarations for mathematical package MATH_COMPLEX
-- which contains common complex constants and basic complex
-- functions and operations.
--
-- Author: IEEE VHDL Math Package Study Group
--
-- Notes:
-- The package body uses package IEEE.MATH_REAL
--
-- The package body shall be considered the formal definition of
-- the semantics of this package. Tool developers may choose to implement
-- the package body in the most efficient manner available to them.
--
-- History:
-- Version 0.1 (Strawman) Jose A. Torres 6/22/92
-- Version 0.2 Jose A. Torres 1/15/93
-- Version 0.3 Jose A. Torres 4/13/93
-- Version 0.4 Jose A. Torres 4/19/93
-- Version 0.5 Jose A. Torres 4/20/93
-- Version 0.6 Jose A. Torres 4/23/93 Added unary minus
-- and CONJ for polar
-- Version 0.7 Jose A. Torres 5/28/93 Rev up for compatibility
-- with package body.
-------------------------------------------------------------
Library IEEE;
Package MATH_COMPLEX is
type COMPLEX is record RE, IM: real; end record;
type COMPLEX_VECTOR is array (integer range <>) of COMPLEX;
type COMPLEX_POLAR is record MAG: real; ARG: real; end record;
constant CBASE_1: complex := COMPLEX'(1.0, 0.0);
constant CBASE_j: complex := COMPLEX'(0.0, 1.0);
constant CZERO: complex := COMPLEX'(0.0, 0.0);
function CABS(Z: in complex ) return real;
-- returns absolute value (magnitude) of Z
function CARG(Z: in complex ) return real;
-- returns argument (angle) in radians of a complex number
function CMPLX(X: in real; Y: in real:= 0.0 ) return complex;
-- returns complex number X + iY
function "-" (Z: in complex ) return complex;
-- unary minus
function "-" (Z: in complex_polar ) return complex_polar;
-- unary minus
function CONJ (Z: in complex) return complex;
-- returns complex conjugate
function CONJ (Z: in complex_polar) return complex_polar;
-- returns complex conjugate
function CSQRT(Z: in complex ) return complex_vector;
-- returns square root of Z; 2 values
function CEXP(Z: in complex ) return complex;
-- returns e**Z
function COMPLEX_TO_POLAR(Z: in complex ) return complex_polar;
-- converts complex to complex_polar
function POLAR_TO_COMPLEX(Z: in complex_polar ) return complex;
-- converts complex_polar to complex
-- arithmetic operators
function "+" ( L: in complex; R: in complex ) return complex;
function "+" ( L: in complex_polar; R: in complex_polar) return complex;
function "+" ( L: in complex_polar; R: in complex ) return complex;
function "+" ( L: in complex; R: in complex_polar) return complex;
function "+" ( L: in real; R: in complex ) return complex;
function "+" ( L: in complex; R: in real ) return complex;
function "+" ( L: in real; R: in complex_polar) return complex;
function "+" ( L: in complex_polar; R: in real) return complex;
function "-" ( L: in complex; R: in complex ) return complex;
function "-" ( L: in complex_polar; R: in complex_polar) return complex;
function "-" ( L: in complex_polar; R: in complex ) return complex;
function "-" ( L: in complex; R: in complex_polar) return complex;
function "-" ( L: in real; R: in complex ) return complex;
function "-" ( L: in complex; R: in real ) return complex;
function "-" ( L: in real; R: in complex_polar) return complex;
function "-" ( L: in complex_polar; R: in real) return complex;
function "*" ( L: in complex; R: in complex ) return complex;
function "*" ( L: in complex_polar; R: in complex_polar) return complex;
function "*" ( L: in complex_polar; R: in complex ) return complex;
function "*" ( L: in complex; R: in complex_polar) return complex;
function "*" ( L: in real; R: in complex ) return complex;
function "*" ( L: in complex; R: in real ) return complex;
function "*" ( L: in real; R: in complex_polar) return complex;
function "*" ( L: in complex_polar; R: in real) return complex;
function "/" ( L: in complex; R: in complex ) return complex;
function "/" ( L: in complex_polar; R: in complex_polar) return complex;
function "/" ( L: in complex_polar; R: in complex ) return complex;
function "/" ( L: in complex; R: in complex_polar) return complex;
function "/" ( L: in real; R: in complex ) return complex;
function "/" ( L: in complex; R: in real ) return complex;
function "/" ( L: in real; R: in complex_polar) return complex;
function "/" ( L: in complex_polar; R: in real) return complex;
end MATH_COMPLEX;
---------------------------------------------------------------
--
-- This source file may be used and distributed without restriction.
-- No declarations or definitions shall be added to this package.
-- This package cannot be sold or distributed for profit.
--
-- ****************************************************************
-- * *
-- * W A R N I N G *
-- * *
-- * This DRAFT version IS NOT endorsed or approved by IEEE *
-- * *
-- ****************************************************************
--
-- Title: PACKAGE BODY MATH_REAL
--
-- Library: This package shall be compiled into a library
-- symbolically named IEEE.
--
-- Purpose: VHDL declarations for mathematical package MATH_REAL
-- which contains common real constants, common real
-- functions, and real trascendental functions.
--
-- Author: IEEE VHDL Math Package Study Group
--
-- Notes:
-- The package body shall be considered the formal definition of
-- the semantics of this package. Tool developers may choose to implement
-- the package body in the most efficient manner available to them.
--
-- Source code and algorithms for this package body comes from the
-- following sources:
-- IEEE VHDL Math Package Study Group participants,
-- U. of Mississippi, Mentor Graphics, Synopsys,
-- Viewlogic/Vantage, Communications of the ACM (June 1988, Vol
-- 31, Number 6, pp. 747, Pierre L'Ecuyer, Efficient and Portable
-- Random Number Generators), Handbook of Mathematical Functions
-- by Milton Abramowitz and Irene A. Stegun (Dover).
--
-- History:
-- Version 0.1 Jose A. Torres 4/23/93 First draft
-- Version 0.2 Jose A. Torres 5/28/93 Fixed potentially illegal code
-------------------------------------------------------------
Library IEEE;
Package body MATH_REAL is
--
-- some constants for use in the package body only
--
constant Q_PI : real := MATH_PI/4.0;
constant HALF_PI : real := MATH_PI/2.0;
constant TWO_PI : real := MATH_PI*2.0;
constant MAX_ITER: integer := 27; -- max precision factor for cordic
--
-- some type declarations for cordic operations
--
constant KC : REAL := 6.0725293500888142e-01; -- constant for cordic
type REAL_VECTOR is array (NATURAL range <>) of REAL;
type NATURAL_VECTOR is array (NATURAL range <>) of NATURAL;
subtype REAL_VECTOR_N is REAL_VECTOR (0 to max_iter);
subtype REAL_ARR_2 is REAL_VECTOR (0 to 1);
subtype REAL_ARR_3 is REAL_VECTOR (0 to 2);
subtype QUADRANT is INTEGER range 0 to 3;
type CORDIC_MODE_TYPE is (ROTATION, VECTORING);
--
-- auxiliary functions for cordic algorithms
--
function POWER_OF_2_SERIES (d : NATURAL_VECTOR; initial_value : REAL;
number_of_values : NATURAL) return REAL_VECTOR is
variable v : REAL_VECTOR (0 to number_of_values);
variable temp : REAL := initial_value;
variable flag : boolean := true;
begin
for i in 0 to number_of_values loop
v(i) := temp;
for p in d'range loop
if i = d(p) then
flag := false;
end if;
end loop;
if flag then
temp := temp/2.0;
end if;
flag := true;
end loop;
return v;
end POWER_OF_2_SERIES;
constant two_at_minus : REAL_VECTOR := POWER_OF_2_SERIES(
NATURAL_VECTOR'(100, 90),1.0,
MAX_ITER);
constant epsilon : REAL_VECTOR_N := (
7.8539816339744827e-01,
4.6364760900080606e-01,
2.4497866312686413e-01,
1.2435499454676144e-01,
6.2418809995957351e-02,
3.1239833430268277e-02,
1.5623728620476830e-02,
7.8123410601011116e-03,
3.9062301319669717e-03,
1.9531225164788189e-03,
9.7656218955931937e-04,
4.8828121119489829e-04,
2.4414062014936175e-04,
1.2207031189367021e-04,
6.1035156174208768e-05,
3.0517578115526093e-05,
1.5258789061315760e-05,
7.6293945311019699e-06,
3.8146972656064960e-06,
1.9073486328101870e-06,
9.5367431640596080e-07,
4.7683715820308876e-07,
2.3841857910155801e-07,
1.1920928955078067e-07,
5.9604644775390553e-08,
2.9802322387695303e-08,
1.4901161193847654e-08,
7.4505805969238281e-09
);
function CORDIC ( x0 : REAL;
y0 : REAL;
z0 : REAL;
n : NATURAL; -- precision factor
CORDIC_MODE : CORDIC_MODE_TYPE -- rotation (z -> 0)
-- or vectoring (y -> 0)
) return REAL_ARR_3 is
variable x : REAL := x0;
variable y : REAL := y0;
variable z : REAL := z0;
variable x_temp : REAL;
begin
if CORDIC_MODE = ROTATION then
for k in 0 to n loop
x_temp := x;
if ( z >= 0.0) then
x := x - y * two_at_minus(k);
y := y + x_temp * two_at_minus(k);
z := z - epsilon(k);
else
x := x + y * two_at_minus(k);
y := y - x_temp * two_at_minus(k);
z := z + epsilon(k);
end if;
end loop;
else
for k in 0 to n loop
x_temp := x;
if ( y < 0.0) then
x := x - y * two_at_minus(k);
y := y + x_temp * two_at_minus(k);
z := z - epsilon(k);
else
x := x + y * two_at_minus(k);
y := y - x_temp * two_at_minus(k);
z := z + epsilon(k);
end if;
end loop;
end if;
return REAL_ARR_3'(x, y, z);
end CORDIC;
--
-- non-trascendental functions
--
function SIGN (X: real ) return real is
-- returns 1.0 if X > 0.0; 0.0 if X == 0.0; -1.0 if X < 0.0
begin
if ( X > 0.0 ) then
return 1.0;
elsif ( X < 0.0 ) then
return -1.0;
else
return 0.0;
end if;
end SIGN;
function CEIL (X : real ) return real is
-- returns smallest integer value (as real) not less than X
-- No conversion to an integer type is expected, so truncate cannot
-- overflow for large arguments.
variable large: real := 1073741824.0;
type long is range -1073741824 to 1073741824;
-- 2**30 is longer than any single-precision mantissa
variable rd: real;
begin
if abs( X) >= large then
return X;
else
rd := real ( long( X));
if X > 0.0 then
if rd >= X then
return rd;
else
return rd + 1.0;
end if;
elsif X = 0.0 then
return 0.0;
else
if rd <= X then
return rd;
else
return rd - 1.0;
end if;
end if;
end if;
end CEIL;
function FLOOR (X : real ) return real is
-- returns largest integer value (as real) not greater than X
-- No conversion to an integer type is expected, so truncate
-- cannot overflow for large arguments.
--
variable large: real := 1073741824.0;
type long is range -1073741824 to 1073741824;
-- 2**30 is longer than any single-precision mantissa
variable rd: real;
begin
if abs( X ) >= large then
return X;
else
rd := real ( long( X));
if X > 0.0 then
if rd <= X then
return rd;
else
return rd - 1.0;
end if;
elsif X = 0.0 then
return 0.0;
else
if rd >= X then
return rd;
else
return rd + 1.0;
end if;
end if;
end if;
end FLOOR;
function ROUND (X : real ) return real is
-- returns integer FLOOR(X + 0.5) if X > 0;
-- return integer CEIL(X - 0.5) if X < 0
begin
if X > 0.0 then
return FLOOR(X + 0.5);
elsif X < 0.0 then
return CEIL( X - 0.5);
else
return 0.0;
end if;
end ROUND;
function FMAX (X, Y : real ) return real is
-- returns the algebraically larger of X and Y
begin
if X > Y then
return X;
else
return Y;
end if;
end FMAX;
function FMIN (X, Y : real ) return real is
-- returns the algebraically smaller of X and Y
begin
if X < Y then
return X;
else
return Y;
end if;
end FMIN;
--
-- Pseudo-random number generators
--
procedure UNIFORM(variable Seed1,Seed2:inout integer;variable X:out real) is
-- returns a pseudo-random number with uniform distribution in the
-- interval (0.0, 1.0).
-- Before the first call to UNIFORM, the seed values (Seed1, Seed2) must
-- be initialized to values in the range [1, 2147483562] and
-- [1, 2147483398] respectively. The seed values are modified after
-- each call to UNIFORM.
-- This random number generator is portable for 32-bit computers, and
-- it has period ~2.30584*(10**18) for each set of seed values.
--
-- For VHDL-1992, the seeds will be global variables, functions to
-- initialize their values (INIT_SEED) will be provided, and the UNIFORM
-- procedure call will be modified accordingly.
variable z, k: integer;
begin
k := Seed1/53668;
Seed1 := 40014 * (Seed1 - k * 53668) - k * 12211;
if Seed1 < 0 then
Seed1 := Seed1 + 2147483563;
end if;
k := Seed2/52774;
Seed2 := 40692 * (Seed2 - k * 52774) - k * 3791;
if Seed2 < 0 then
Seed2 := Seed2 + 2147483399;
end if;
z := Seed1 - Seed2;
if z < 1 then
z := z + 2147483562;
end if;
X := REAL(Z)*4.656613e-10;
end UNIFORM;
function SRAND (seed: in integer ) return integer is
--
-- sets value of seed for sequence of
-- pseudo-random numbers.
-- Returns the value of the seed.
-- It uses the foreign native C function srand().
begin
end SRAND;
function RAND return integer is
--
-- returns an integer pseudo-random number with uniform distribution.
-- It uses the foreign native C function rand().
-- Seed for the sequence is initialized with the
-- SRAND() function and value of the seed is changed every
-- time SRAND() is called, but it is not visible.
-- The range of generated values is platform dependent.
begin
end RAND;
function GET_RAND_MAX return integer is
--
-- returns the upper bound of the range of the
-- pseudo-random numbers generated by RAND().
-- The support for this function is platform dependent, and
-- it uses foreign native C functions or constants.
-- It may not be available in some platforms.
-- Note: the value of (RAND / GET_RAND_MAX) is a
-- pseudo-random number distributed between 0 & 1.
begin
end GET_RAND_MAX;
--
-- trascendental and trigonometric functions
--
function SQRT (X : real ) return real is
-- returns square root of X; X >= 0
--
-- Computes square root using the Newton-Raphson approximation:
-- F(n+1) = 0.5*[F(n) + x/F(n)];
--
constant inival: real := 1.5;
constant eps : real := 0.000001;
constant relative_err : real := eps*X;
variable oldval : real ;
variable newval : real ;
begin
-- check validity of argument
if ( X < 0.0 ) then
assert false report "X < 0 in SQRT(X)"
severity ERROR;
return (0.0);
end if;
-- get the square root for special cases
if X = 0.0 then
return 0.0;
else
if ( X = 1.0 ) then
return 1.0; -- return exact value
end if;
end if;
-- get the square root for general cases
oldval := inival;
newval := (X/oldval + oldval)/2.0;
while ( abs(newval -oldval) > relative_err ) loop
oldval := newval;
newval := (X/oldval + oldval)/2.0;
end loop;
return newval;
end SQRT;
function CBRT (X : real ) return real is
-- returns cube root of X
-- Computes square root using the Newton-Raphson approximation:
-- F(n+1) = (1/3)*[2*F(n) + x/F(n)**2];
--
constant inival: real := 1.5;
constant eps : real := 0.000001;
constant relative_err : real := eps*abs(X);
variable xlocal : real := X;
variable negative : boolean := X < 0.0;
variable oldval : real ;
variable newval : real ;
begin
-- compute root for special cases
if X = 0.0 then
return 0.0;
elsif ( X = 1.0 ) then
return 1.0;
else
if X = -1.0 then
return -1.0;
end if;
end if;
-- compute root for general cases
if negative then
xlocal := -X;
end if;
oldval := inival;
newval := (xlocal/(oldval*oldval) + 2.0*oldval)/3.0;
while ( abs(newval -oldval) > relative_err ) loop
oldval := newval;
newval :=(xlocal/(oldval*oldval) + 2.0*oldval)/3.0;
end loop;
if negative then
newval := -newval;
end if;
return newval;
end CBRT;
function "**" (X : integer; Y : real) return real is
-- returns Y power of X ==> X**Y;
-- error if X = 0 and Y <= 0.0
-- error if X < 0 and Y does not have an integer value
begin
-- check validity of argument
if ( X = 0 ) and ( Y <= 0.0 ) then
assert false report "X = 0 and Y <= 0.0 in X**Y"
severity ERROR;
return (0.0);
end if;
if ( X < 0 ) and ( Y /= REAL(INTEGER(Y)) ) then
assert false report "X < 0 and Y \= integer in X**Y"
severity ERROR;
return (0.0);
end if;
-- compute the result
return EXP (Y * LOG (REAL(X)));
end "**";
function "**" (X : real; Y : real) return real is
-- returns Y power of X ==> X**Y;
-- error if X = 0.0 and Y <= 0.0
-- error if X < 0.0 and Y does not have an integer value
begin
-- check validity of argument
if ( X = 0.0 ) and ( Y <= 0.0 ) then
assert false report "X = 0.0 and Y <= 0.0 in X**Y"
severity ERROR;
return (0.0);
end if;
if ( X < 0.0 ) and ( Y /= REAL(INTEGER(Y)) ) then
assert false report "X < 0.0 and Y \= integer in X**Y"
severity ERROR;
return (0.0);
end if;
-- compute the result
return EXP (Y * LOG (X));
end "**";
function EXP (X : real ) return real is
-- returns e**X; where e = MATH_E
--
-- This function computes the exponential using the following series:
-- exp(x) = 1 + x + x**2/2! + x**3/3! + ... ; x > 0
--
constant eps : real := 0.000001; -- precision criteria
variable reciprocal: boolean := x < 0.0;-- check sign of argument
variable xlocal : real := abs(x); -- use positive value
variable oldval: real ; -- following variables are
variable num: real ; -- used for series evaluation
variable count: integer ;
variable denom: real ;
variable newval: real ;
begin
-- compute value for special cases
if X = 0.0 then
return 1.0;
else
if X = 1.0 then
return MATH_E;
end if;
end if;
-- compute value for general cases
oldval := 1.0;
num := xlocal;
count := 1;
denom := 1.0;
newval:= oldval + num/denom;
while ( abs(newval - oldval) > eps ) loop
oldval := newval;
num := num*xlocal;
count := count +1;
denom := denom*(real(count));
newval := oldval + num/denom;
end loop;
if reciprocal then
newval := 1.0/newval;
end if;
return newval;
end EXP;
function LOG (X : real ) return real is
-- returns natural logarithm of X; X > 0
--
-- This function computes the exponential using the following series:
-- log(x) = 2[ (x-1)/(x+1) + (((x-1)/(x+1))**3)/3.0 + ...] ; x > 0
--
constant eps : real := 0.000001; -- precision criteria
variable xlocal: real ; -- following variables are
variable oldval: real ; -- used to evaluate the series
variable xlocalsqr: real ;
variable factor : real ;
variable count: integer ;
variable newval: real ;
begin
-- check validity of argument
if ( x <= 0.0 ) then
assert false report "X <= 0 in LOG(X)"
severity ERROR;
return(REAL'LOW);
end if;
-- compute value for special cases
if ( X = 1.0 ) then
return 0.0;
else
if ( X = MATH_E ) then
return 1.0;
end if;
end if;
-- compute value for general cases
xlocal := (X - 1.0)/(X + 1.0);
oldval := xlocal;
xlocalsqr := xlocal*xlocal;
factor := xlocal*xlocalsqr;
count := 3;
newval := oldval + (factor/real(count));
while ( abs(newval - oldval) > eps ) loop
oldval := newval;
count := count +2;
factor := factor * xlocalsqr;
newval := oldval + factor/real(count);
end loop;
newval := newval * 2.0;
return newval;
end LOG;
function LOG (BASE: positive; X : real) return real is
-- returns logarithm base BASE of X; X > 0
begin
-- check validity of argument
if ( BASE <= 0 ) or ( x <= 0.0 ) then
assert false report "BASE <= 0 or X <= 0.0 in LOG(BASE, X)"
severity ERROR;
return(REAL'LOW);
end if;
-- compute the value
return ( LOG(X)/LOG(REAL(BASE)));
end LOG;
function SIN (X : real ) return real is
-- returns sin X; X in radians
variable n : INTEGER;
begin
if (x < 1.6 ) and (x > -1.6) then
return CORDIC( KC, 0.0, x, 27, ROTATION)(1);
end if;
n := INTEGER( x / HALF_PI );
case QUADRANT( n mod 4 ) is
when 0 =>
return CORDIC( KC, 0.0, x - REAL(n) * HALF_PI, 27, ROTATION)(1);
when 1 =>
return CORDIC( KC, 0.0, x - REAL(n) * HALF_PI, 27, ROTATION)(0);
when 2 =>
return -CORDIC( KC, 0.0, x - REAL(n) * HALF_PI, 27, ROTATION)(1);
when 3 =>
return -CORDIC( KC, 0.0, x - REAL(n) * HALF_PI, 27, ROTATION)(0);
end case;
end SIN;
function COS (x : REAL) return REAL is
-- returns cos X; X in radians
variable n : INTEGER;
begin
if (x < 1.6 ) and (x > -1.6) then
return CORDIC( KC, 0.0, x, 27, ROTATION)(0);
end if;
n := INTEGER( x / HALF_PI );
case QUADRANT( n mod 4 ) is
when 0 =>
return CORDIC( KC, 0.0, x - REAL(n) * HALF_PI, 27, ROTATION)(0);
when 1 =>
return -CORDIC( KC, 0.0, x - REAL(n) * HALF_PI, 27, ROTATION)(1);
when 2 =>
return -CORDIC( KC, 0.0, x - REAL(n) * HALF_PI, 27, ROTATION)(0);
when 3 =>
return CORDIC( KC, 0.0, x - REAL(n) * HALF_PI, 27, ROTATION)(1);
end case;
end COS;
function TAN (x : REAL) return REAL is
-- returns tan X; X in radians
-- X /= ((2k+1) * PI/2), where k is an integer
variable n : INTEGER := INTEGER( x / HALF_PI );
variable v : REAL_ARR_3 :=
CORDIC( KC, 0.0, x - REAL(n) * HALF_PI, 27, ROTATION);
begin
if n mod 2 = 0 then
return v(1)/v(0);
else
return -v(0)/v(1);
end if;
end TAN;
function ASIN (x : real ) return real is
-- returns -PI/2 < asin X < PI/2; | X | <= 1
begin
if abs x > 1.0 then
assert false report "Out of range parameter passed to ASIN"
severity ERROR;
return x;
elsif abs x < 0.9 then
return atan(x/(sqrt(1.0 - x*x)));
elsif x > 0.0 then
return HALF_PI - atan(sqrt(1.0 - x*x)/x);
else
return - HALF_PI + atan((sqrt(1.0 - x*x))/x);
end if;
end ASIN;
function ACOS (x : REAL) return REAL is
-- returns 0 < acos X < PI; | X | <= 1
begin
if abs x > 1.0 then
assert false report "Out of range parameter passed to ACOS"
severity ERROR;
return x;
elsif abs x > 0.9 then
if x > 0.0 then
return atan(sqrt(1.0 - x*x)/x);
else
return MATH_PI - atan(sqrt(1.0 - x*x)/x);
end if;
else
return HALF_PI - atan(x/sqrt(1.0 - x*x));
end if;
end ACOS;
function ATAN (x : REAL) return REAL is
-- returns -PI/2 < atan X < PI/2
begin
return CORDIC( 1.0, x, 0.0, 27, VECTORING )(2);
end ATAN;
function ATAN2 (x : REAL; y : REAL) return REAL is
-- returns atan (X/Y); -PI < atan2(X,Y) < PI; Y /= 0.0
begin
if y = 0.0 then
if x = 0.0 then
assert false report "atan2(0.0, 0.0) is undetermined, returned 0,0"
severity NOTE;
return 0.0;
elsif x > 0.0 then
return 0.0;
else
return MATH_PI;
end if;
elsif x > 0.0 then
return CORDIC( x, y, 0.0, 27, VECTORING )(2);
else
return MATH_PI + CORDIC( x, y, 0.0, 27, VECTORING )(2);
end if;
end ATAN2;
function SINH (X : real) return real is
-- hyperbolic sine; returns (e**X - e**(-X))/2
begin
return ( (EXP(X) - EXP(-X))/2.0 );
end SINH;
function COSH (X : real) return real is
-- hyperbolic cosine; returns (e**X + e**(-X))/2
begin
return ( (EXP(X) + EXP(-X))/2.0 );
end COSH;
function TANH (X : real) return real is
-- hyperbolic tangent; -- returns (e**X - e**(-X))/(e**X + e**(-X))
begin
return ( (EXP(X) - EXP(-X))/(EXP(X) + EXP(-X)) );
end TANH;
function ASINH (X : real) return real is
-- returns ln( X + sqrt( X**2 + 1))
begin
return ( LOG( X + SQRT( X**2 + 1.0)) );
end ASINH;
function ACOSH (X : real) return real is
-- returns ln( X + sqrt( X**2 - 1)); X >= 1
begin
if abs x >= 1.0 then
assert false report "Out of range parameter passed to ACOSH"
severity ERROR;
return x;
end if;
return ( LOG( X + SQRT( X**2 - 1.0)) );
end ACOSH;
function ATANH (X : real) return real is
-- returns (ln( (1 + X)/(1 - X)))/2 ; | X | < 1
begin
if abs x < 1.0 then
assert false report "Out of range parameter passed to ATANH"
severity ERROR;
return x;
end if;
return( LOG( (1.0+X)/(1.0-X) )/2.0 );
end ATANH;
end MATH_REAL;
---------------------------------------------------------------
--
-- This source file may be used and distributed without restriction.
-- No declarations or definitions shall be included in this package.
-- This package cannot be sold or distributed for profit.
--
-- ****************************************************************
-- * *
-- * W A R N I N G *
-- * *
-- * This DRAFT version IS NOT endorsed or approved by IEEE *
-- * *
-- ****************************************************************
--
-- Title: PACKAGE BODY MATH_COMPLEX
--
-- Purpose: VHDL declarations for mathematical package MATH_COMPLEX
-- which contains common complex constants and basic complex
-- functions and operations.
--
-- Author: IEEE VHDL Math Package Study Group
--
-- Notes:
-- The package body uses package IEEE.MATH_REAL
--
-- The package body shall be considered the formal definition of
-- the semantics of this package. Tool developers may choose to implement
-- the package body in the most efficient manner available to them.
--
-- Source code for this package body comes from the following
-- following sources:
-- IEEE VHDL Math Package Study Group participants,
-- U. of Mississippi, Mentor Graphics, Synopsys,
-- Viewlogic/Vantage, Communications of the ACM (June 1988, Vol
-- 31, Number 6, pp. 747, Pierre L'Ecuyer, Efficient and Portable
-- Random Number Generators, Handbook of Mathematical Functions
-- by Milton Abramowitz and Irene A. Stegun (Dover).
--
-- History:
-- Version 0.1 Jose A. Torres 4/23/93 First draft
-- Version 0.2 Jose A. Torres 5/28/93 Fixed potentially illegal code
--
-------------------------------------------------------------
Library IEEE;
Use IEEE.MATH_REAL.all; -- real trascendental operations
Package body MATH_COMPLEX is
function CABS(Z: in complex ) return real is
-- returns absolute value (magnitude) of Z
variable ztemp : complex_polar;
begin
ztemp := COMPLEX_TO_POLAR(Z);
return ztemp.mag;
end CABS;
function CARG(Z: in complex ) return real is
-- returns argument (angle) in radians of a complex number
variable ztemp : complex_polar;
begin
ztemp := COMPLEX_TO_POLAR(Z);
return ztemp.arg;
end CARG;
function CMPLX(X: in real; Y: in real := 0.0 ) return complex is
-- returns complex number X + iY
begin
return COMPLEX'(X, Y);
end CMPLX;
function "-" (Z: in complex ) return complex is
-- unary minus; returns -x -jy for z= x + jy
begin
return COMPLEX'(-z.Re, -z.Im);
end "-";
function "-" (Z: in complex_polar ) return complex_polar is
-- unary minus; returns (z.mag, z.arg + MATH_PI)
begin
return COMPLEX_POLAR'(z.mag, z.arg + MATH_PI);
end "-";
function CONJ (Z: in complex) return complex is
-- returns complex conjugate (x-jy for z = x+ jy)
begin
return COMPLEX'(z.Re, -z.Im);
end CONJ;
function CONJ (Z: in complex_polar) return complex_polar is
-- returns complex conjugate (z.mag, -z.arg)
begin
return COMPLEX_POLAR'(z.mag, -z.arg);
end CONJ;
function CSQRT(Z: in complex ) return complex_vector is
-- returns square root of Z; 2 values
variable ztemp : complex_polar;
variable zout : complex_vector (0 to 1);
variable temp : real;
begin
ztemp := COMPLEX_TO_POLAR(Z);
temp := SQRT(ztemp.mag);
zout(0).re := temp*COS(ztemp.arg/2.0);
zout(0).im := temp*SIN(ztemp.arg/2.0);
zout(1).re := temp*COS(ztemp.arg/2.0 + MATH_PI);
zout(1).im := temp*SIN(ztemp.arg/2.0 + MATH_PI);
return zout;
end CSQRT;
function CEXP(Z: in complex ) return complex is
-- returns e**Z
begin
return COMPLEX'(EXP(Z.re)*COS(Z.im), EXP(Z.re)*SIN(Z.im));
end CEXP;
function COMPLEX_TO_POLAR(Z: in complex ) return complex_polar is
-- converts complex to complex_polar
begin
return COMPLEX_POLAR'(sqrt(z.re**2 + z.im**2),atan2(z.re,z.im));
end COMPLEX_TO_POLAR;
function POLAR_TO_COMPLEX(Z: in complex_polar ) return complex is
-- converts complex_polar to complex
begin
return COMPLEX'( z.mag*cos(z.arg), z.mag*sin(z.arg) );
end POLAR_TO_COMPLEX;
--
-- arithmetic operators
--
function "+" ( L: in complex; R: in complex ) return complex is
begin
return COMPLEX'(L.Re + R.Re, L.Im + R.Im);
end "+";
function "+" (L: in complex_polar; R: in complex_polar) return complex is
variable zL, zR : complex;
begin
zL := POLAR_TO_COMPLEX( L );
zR := POLAR_TO_COMPLEX( R );
return COMPLEX'(zL.Re + zR.Re, zL.Im + zR.Im);
end "+";
function "+" ( L: in complex_polar; R: in complex ) return complex is
variable zL : complex;
begin
zL := POLAR_TO_COMPLEX( L );
return COMPLEX'(zL.Re + R.Re, zL.Im + R.Im);
end "+";
function "+" ( L: in complex; R: in complex_polar) return complex is
variable zR : complex;
begin
zR := POLAR_TO_COMPLEX( R );
return COMPLEX'(L.Re + zR.Re, L.Im + zR.Im);
end "+";
function "+" ( L: in real; R: in complex ) return complex is
begin
return COMPLEX'(L + R.Re, R.Im);
end "+";
function "+" ( L: in complex; R: in real ) return complex is
begin
return COMPLEX'(L.Re + R, L.Im);
end "+";
function "+" ( L: in real; R: in complex_polar) return complex is
variable zR : complex;
begin
zR := POLAR_TO_COMPLEX( R );
return COMPLEX'(L + zR.Re, zR.Im);
end "+";
function "+" ( L: in complex_polar; R: in real) return complex is
variable zL : complex;
begin
zL := POLAR_TO_COMPLEX( L );
return COMPLEX'(zL.Re + R, zL.Im);
end "+";
function "-" ( L: in complex; R: in complex ) return complex is
begin
return COMPLEX'(L.Re - R.Re, L.Im - R.Im);
end "-";
function "-" ( L: in complex_polar; R: in complex_polar) return complex is
variable zL, zR : complex;
begin
zL := POLAR_TO_COMPLEX( L );
zR := POLAR_TO_COMPLEX( R );
return COMPLEX'(zL.Re - zR.Re, zL.Im - zR.Im);
end "-";
function "-" ( L: in complex_polar; R: in complex ) return complex is
variable zL : complex;
begin
zL := POLAR_TO_COMPLEX( L );
return COMPLEX'(zL.Re - R.Re, zL.Im - R.Im);
end "-";
function "-" ( L: in complex; R: in complex_polar) return complex is
variable zR : complex;
begin
zR := POLAR_TO_COMPLEX( R );
return COMPLEX'(L.Re - zR.Re, L.Im - zR.Im);
end "-";
function "-" ( L: in real; R: in complex ) return complex is
begin
return COMPLEX'(L - R.Re, -1.0 * R.Im);
end "-";
function "-" ( L: in complex; R: in real ) return complex is
begin
return COMPLEX'(L.Re - R, L.Im);
end "-";
function "-" ( L: in real; R: in complex_polar) return complex is
variable zR : complex;
begin
zR := POLAR_TO_COMPLEX( R );
return COMPLEX'(L - zR.Re, -1.0*zR.Im);
end "-";
function "-" ( L: in complex_polar; R: in real) return complex is
variable zL : complex;
begin
zL := POLAR_TO_COMPLEX( L );
return COMPLEX'(zL.Re - R, zL.Im);
end "-";
function "*" ( L: in complex; R: in complex ) return complex is
begin
return COMPLEX'(L.Re * R.Re - L.Im * R.Im, L.Re * R.Im + L.Im * R.Re);
end "*";
function "*" ( L: in complex_polar; R: in complex_polar) return complex is
variable zout : complex_polar;
begin
zout.mag := L.mag * R.mag;
zout.arg := L.arg + R.arg;
return POLAR_TO_COMPLEX(zout);
end "*";
function "*" ( L: in complex_polar; R: in complex ) return complex is
variable zL : complex;
begin
zL := POLAR_TO_COMPLEX( L );
return COMPLEX'(zL.Re*R.Re - zL.Im * R.Im, zL.Re * R.Im + zL.Im*R.Re);
end "*";
function "*" ( L: in complex; R: in complex_polar) return complex is
variable zR : complex;
begin
zR := POLAR_TO_COMPLEX( R );
return COMPLEX'(L.Re*zR.Re - L.Im * zR.Im, L.Re * zR.Im + L.Im*zR.Re);
end "*";
function "*" ( L: in real; R: in complex ) return complex is
begin
return COMPLEX'(L * R.Re, L * R.Im);
end "*";
function "*" ( L: in complex; R: in real ) return complex is
begin
return COMPLEX'(L.Re * R, L.Im * R);
end "*";
function "*" ( L: in real; R: in complex_polar) return complex is
variable zR : complex;
begin
zR := POLAR_TO_COMPLEX( R );
return COMPLEX'(L * zR.Re, L * zR.Im);
end "*";
function "*" ( L: in complex_polar; R: in real) return complex is
variable zL : complex;
begin
zL := POLAR_TO_COMPLEX( L );
return COMPLEX'(zL.Re * R, zL.Im * R);
end "*";
function "/" ( L: in complex; R: in complex ) return complex is
variable magrsq : REAL := R.Re ** 2 + R.Im ** 2;
begin
if (magrsq = 0.0) then
assert FALSE report "Attempt to divide by (0,0)"
severity ERROR;
return COMPLEX'(REAL'RIGHT, REAL'RIGHT);
else
return COMPLEX'( (L.Re * R.Re + L.Im * R.Im) / magrsq,
(L.Im * R.Re - L.Re * R.Im) / magrsq);
end if;
end "/";
function "/" ( L: in complex_polar; R: in complex_polar) return complex is
variable zout : complex_polar;
begin
if (R.mag = 0.0) then
assert FALSE report "Attempt to divide by (0,0)"
severity ERROR;
return COMPLEX'(REAL'RIGHT, REAL'RIGHT);
else
zout.mag := L.mag/R.mag;
zout.arg := L.arg - R.arg;
return POLAR_TO_COMPLEX(zout);
end if;
end "/";
function "/" ( L: in complex_polar; R: in complex ) return complex is
variable zL : complex;
variable temp : REAL := R.Re ** 2 + R.Im ** 2;
begin
if (temp = 0.0) then
assert FALSE report "Attempt to divide by (0.0,0.0)"
severity ERROR;
return COMPLEX'(REAL'RIGHT, REAL'RIGHT);
else
zL := POLAR_TO_COMPLEX( L );
return COMPLEX'( (zL.Re * R.Re + zL.Im * R.Im) / temp,
(zL.Im * R.Re - zL.Re * R.Im) / temp);
end if;
end "/";
function "/" ( L: in complex; R: in complex_polar) return complex is
variable zR : complex := POLAR_TO_COMPLEX( R );
variable temp : REAL := zR.Re ** 2 + zR.Im ** 2;
begin
if (R.mag = 0.0) or (temp = 0.0) then
assert FALSE report "Attempt to divide by (0.0,0.0)"
severity ERROR;
return COMPLEX'(REAL'RIGHT, REAL'RIGHT);
else
return COMPLEX'( (L.Re * zR.Re + L.Im * zR.Im) / temp,
(L.Im * zR.Re - L.Re * zR.Im) / temp);
end if;
end "/";
function "/" ( L: in real; R: in complex ) return complex is
variable temp : REAL := R.Re ** 2 + R.Im ** 2;
begin
if (temp = 0.0) then
assert FALSE report "Attempt to divide by (0.0,0.0)"
severity ERROR;
return COMPLEX'(REAL'RIGHT, REAL'RIGHT);
else
temp := L / temp;
return COMPLEX'( temp * R.Re, -temp * R.Im );
end if;
end "/";
function "/" ( L: in complex; R: in real ) return complex is
begin
if (R = 0.0) then
assert FALSE report "Attempt to divide by (0.0,0.0)"
severity ERROR;
return COMPLEX'(REAL'RIGHT, REAL'RIGHT);
else
return COMPLEX'(L.Re / R, L.Im / R);
end if;
end "/";
function "/" ( L: in real; R: in complex_polar) return complex is
variable zR : complex := POLAR_TO_COMPLEX( R );
variable temp : REAL := zR.Re ** 2 + zR.Im ** 2;
begin
if (R.mag = 0.0) or (temp = 0.0) then
assert FALSE report "Attempt to divide by (0.0,0.0)"
severity ERROR;
return COMPLEX'(REAL'RIGHT, REAL'RIGHT);
else
temp := L / temp;
return COMPLEX'( temp * zR.Re, -temp * zR.Im );
end if;
end "/";
function "/" ( L: in complex_polar; R: in real) return complex is
variable zL : complex := POLAR_TO_COMPLEX( L );
begin
if (R = 0.0) then
assert FALSE report "Attempt to divide by (0.0,0.0)"
severity ERROR;
return COMPLEX'(REAL'RIGHT, REAL'RIGHT);
else
return COMPLEX'(zL.Re / R, zL.Im / R);
end if;
end "/";
end MATH_COMPLEX;
|
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
entity zero_counter_t is
end zero_counter_t;
architecture Beh of zero_counter_t is
component ZeroCounter
port (
CLK, RST, Start: in std_logic;
Stop: out std_logic
);
end component;
signal clk: std_logic := '0';
signal rst: std_logic := '0';
signal start: std_logic := '0';
signal stop: std_logic := '0';
constant CLK_period: time := 10 ns;
begin
UZEROCOUNTER: ZeroCounter port map (
CLK => clk,
RST => rst,
START => start,
STOP => stop
);
CLK_Process: process
begin
CLK <= '0';
wait for CLK_Period/2;
CLK <= '1';
wait for CLK_Period/2;
end process;
main: process
begin
rst <= '1';
wait for 1 * CLK_PERIOD;
rst <= '0';
start <= '1';
wait for 100 * CLK_PERIOD;
wait;
end process;
end Beh;
configuration config of zero_counter_t is
for Beh
for UZEROCOUNTER : ZeroCounter
use entity work.ZeroCounter(Beh);
end for;
end for;
end config; |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2754.vhd,v 1.2 2001-10-26 16:30:22 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s07b00x00p03n01i02754ent IS
END c13s07b00x00p03n01i02754ent;
ARCHITECTURE c13s07b00x00p03n01i02754arch OF c13s07b00x00p03n01i02754ent IS
BEGIN
TESTING: PROCESS
variable bit_str : bit_vector (1 to 8) := x"";
BEGIN
assert FALSE
report "***FAILED TEST: c13s07b00x00p03n01i02754 - Bit string must contain at least one digit.(Test for base specifier of X)"
severity ERROR;
wait;
END PROCESS TESTING;
END c13s07b00x00p03n01i02754arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2754.vhd,v 1.2 2001-10-26 16:30:22 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s07b00x00p03n01i02754ent IS
END c13s07b00x00p03n01i02754ent;
ARCHITECTURE c13s07b00x00p03n01i02754arch OF c13s07b00x00p03n01i02754ent IS
BEGIN
TESTING: PROCESS
variable bit_str : bit_vector (1 to 8) := x"";
BEGIN
assert FALSE
report "***FAILED TEST: c13s07b00x00p03n01i02754 - Bit string must contain at least one digit.(Test for base specifier of X)"
severity ERROR;
wait;
END PROCESS TESTING;
END c13s07b00x00p03n01i02754arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2754.vhd,v 1.2 2001-10-26 16:30:22 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s07b00x00p03n01i02754ent IS
END c13s07b00x00p03n01i02754ent;
ARCHITECTURE c13s07b00x00p03n01i02754arch OF c13s07b00x00p03n01i02754ent IS
BEGIN
TESTING: PROCESS
variable bit_str : bit_vector (1 to 8) := x"";
BEGIN
assert FALSE
report "***FAILED TEST: c13s07b00x00p03n01i02754 - Bit string must contain at least one digit.(Test for base specifier of X)"
severity ERROR;
wait;
END PROCESS TESTING;
END c13s07b00x00p03n01i02754arch;
|
-------------------------------------------------------------------------------
--! @file PreProcessor_Datapath.vhd
--! @brief Datapath for the pre-processor
--! @project CAESAR Candidate Evaluation
--! @author Ekawat (ice) Homsirikamol
--! @copyright Copyright (c) 2015 Cryptographic Engineering Research Group
--! ECE Department, George Mason University Fairfax, VA, U.S.A.
--! All rights Reserved.
--! @license This project is released under the GNU Public License.
--! The license and distribution terms for this file may be
--! found in the file LICENSE in this distribution or at
--! http://www.gnu.org/licenses/gpl-3.0.txt
--! @note This is publicly available encryption source code that falls
--! under the License Exception TSU (Technology and software-
--! —unrestricted)
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use work.AEAD_pkg.all;
entity PreProcessor_Datapath is
generic (
G_W : integer := 64; --! Public data width (bits)
G_SW : integer := 64; --! Secret data width (bits)
G_CTR_AD_SIZE : integer := 64; --! Maximum size for the counter that keeps track of authenticated data
G_CTR_D_SIZE : integer := 64; --! Maximum size for the counter that keeps track of data
G_DBLK_SIZE : integer := 128; --! Block size (bits)
G_KEY_SIZE : integer := 128; --! Key size (bits)
G_KEYAK : integer := 0; --! Special input mode, used only for Keyak with G_W = 128 and G_DBLK_SIZE = 1344
G_NPUB_DISABLE : integer := 0; --! Disable Npub related port(s)
G_NPUB_SIZE : integer := 128; --! Npub width (bits)
G_NSEC_ENABLE : integer := 0; --! Enable nsec port
G_NSEC_SIZE : integer := 128; --! Nsec width (bits)
G_LOADLEN_ENABLE : integer := 0; --! Enable load length section
G_PAD : integer := 0; --! Enable padding
G_PAD_STYLE : integer := 1; --! Padding mode 0 = *10..., 1 = ICEPOLE's padding
G_RDKEY_ENABLE : integer := 0; --! Enable rdkey port (also disables key port)
G_RDKEY_SIZE : integer := 128; --! Roundkey size (bits)
G_TAG_SIZE : integer := 128 --! Tag size (bits)
);
port (
--! =================
--! External Signals
--! =================
--! Global signals
clk : in std_logic;
rst : in std_logic;
pdi : in std_logic_vector(G_W -1 downto 0); --! Public data
sdi : in std_logic_vector(G_SW -1 downto 0); --! Secret data
--! =================
--! Crypto Core Signals
--! =================
key : out std_logic_vector(G_KEY_SIZE -1 downto 0); --! Key data
rdkey : out std_logic_vector(G_RDKEY_SIZE -1 downto 0); --! Round key data
bdi : out std_logic_vector(G_DBLK_SIZE -1 downto 0); --! Block data
npub : out std_logic_vector(G_NPUB_SIZE -1 downto 0); --! Npub data
nsec : out std_logic_vector(G_NSEC_SIZE -1 downto 0); --! Nsec data
exp_tag : out std_logic_vector(G_TAG_SIZE -1 downto 0); --! Expected tag data
bdi_valid_bytes : out std_logic_vector(G_DBLK_SIZE/8 -1 downto 0);
bdi_pad_loc : out std_logic_vector(G_DBLK_SIZE/8 -1 downto 0);
len_a : out std_logic_vector(G_CTR_AD_SIZE -1 downto 0); --! Len of authenticated data in bytes (used for some algorithm)
len_d : out std_logic_vector(G_CTR_D_SIZE -1 downto 0); --! Len of data in bytes (used for some algorithm)
--! =================
--! Internal Signals
--! =================
--! Control signals
key_updated : in std_logic; --! (if G_DBLK_SIZE mod G_W > 0) Key updated signal (used only for situation when key is stored within input processor)
pad_shift : in std_logic_vector(log2_ceil(G_W/8) -1 downto 0);
en_data : in std_logic; --! Shift data SIPO
en_npub : in std_logic; --! Shift Npub SIPO
en_nsec : in std_logic; --! Shift Nsec SIPO
en_key : in std_logic; --! Shift key SIPO
en_rdkey : in std_logic; --! Shift round key SIPO
en_exp_tag : in std_logic; --! Shift expected tag SIPO
sel_blank_pdi : in std_logic; --! Select input data as blank (for filling in the remaining data within a block)
clr_len : in std_logic; --! Clear stored length (len_a and len_d)
en_len_a_r : in std_logic; --! Add authenticated data counter
en_len_d_r : in std_logic; --! Add data counter
en_len_last_r : in std_logic; --! Special signal for en_len_*_r
en_len_a : in std_logic; --! Add authenticated data counter (instant)
en_len_d : in std_logic; --! Add data counter (no)
size_dword : in std_logic_vector(log2_ceil(G_W/8) downto 0); --! Size of data word
en_last_word : in std_logic; --! Last word in a block
pad_eot : in std_logic; --! Padding is EOT
pad_eoi : in std_logic; --! Padding is EOI
pad_type_ad : in std_logic; --! Padding is AD
pad_enable : in std_logic; --! Enable padding signal (indicates that the current word requires padding)
en_pad_loc : in std_logic; --! Save the padding location into a register
sel_input : in std_logic_vector(3 -1 downto 0) --! (if G_DBLK_SIZE mod G_W > 0) Select input for m
);
end PreProcessor_Datapath;
architecture dataflow of PreProcessor_Datapath is
--! Constants declaration
constant LOG2_W : integer := log2_ceil(G_W/8); --! LOG_2(G_W)
constant LOG2_SW : integer := log2_ceil(G_SW/8); --! LOG_2(G_SW)
constant REG_NPUB_WIDTH : integer := (((G_NPUB_SIZE-1)/G_W)+1)*G_W; --! Calculate the width of Npub register
constant CNTR_WIDTH : integer := get_cntr_width(G_W); --! Calculate the length of p_size register
constant LEN_A_WIDTH : integer := maximum(CNTR_WIDTH, G_CTR_AD_SIZE);
constant LEN_D_WIDTH : integer := maximum(CNTR_WIDTH, G_CTR_D_SIZE);
constant CNT_DATA_WORDS : integer := (G_DBLK_SIZE+(G_W-1))/G_W; --! Calculate the number of words required for data (rounded up)
constant CNT_TAG_WORDS : integer := (G_DBLK_SIZE+(G_W-1))/G_W; --! Calculate the number of words required for tag (rounded up)
constant BSHIFT_INPUT : std_logic_vector(G_W/8 -1 downto 0) := std_logic_vector(to_unsigned(1,G_W/8));
constant OWORD_BYTES : std_logic_vector(G_DBLK_SIZE/8 -1 downto 0) := (others => '1'); --! The number of bytes in a word in ones.
constant ZWORD_BYTES : std_logic_vector(G_DBLK_SIZE/8 -1 downto 0) := (others => '0'); --! The number of bytes in a word in zeros.
function reverse_bit(aa: std_logic_vector) return std_logic_vector is
variable bb : std_logic_vector(aa'high downto aa'low);
begin
for i in aa'high downto aa'low loop
bb(i) := aa(aa'high-i);
end loop;
return bb;
end function reverse_bit;
type lookup_type is array (0 to ((G_W/8)*2-1)) of std_logic_vector(G_W/8-1 downto 0);
function getVbytesLookup(size: integer) return lookup_type is
variable ret : lookup_type;
begin
for i in 0 to ((size/8)*2-1) loop
if (i >= (size/8)) then
ret(i) := (others => '1');
elsif (i = 0) then
ret(i) := (others => '0');
else
ret(i)(size/8-1 downto size/8-i) := (others => '1');
ret(i)(size/8-i-1 downto 0) := (others => '0');
end if;
end loop;
return ret;
end function getVbytesLookup;
constant VBYTES_LOOKUP : lookup_type := getVbytesLookup(G_W);
--! ==================
--! Note: Current unused (keep this portion for later consideration)
function getPlocLookup(size: integer) return lookup_type is
variable ret : lookup_type;
begin
for i in 0 to ((size/8)*2-1) loop
if (i >= (size/8)) then
ret(i) := (others => '0');
else
ret(i) := (i => '1', others => '0');
end if;
end loop;
return ret;
end function getPlocLookup;
constant PLOC_LOOKUP : lookup_type := getPlocLookup(G_W);
--! End of note
--! ==================
--! Key related signals and registers
signal reg_key : std_logic_vector(G_KEY_SIZE -1 downto 0);
signal reg_rdkey : std_logic_vector(G_RDKEY_SIZE -1 downto 0);
--! Public data signals and registers
signal reg_data : std_logic_vector(G_DBLK_SIZE -1 downto 0); --! Data block register
signal reg_exp_tag : std_logic_vector(G_TAG_SIZE -1 downto 0); --! Tag register
signal reg_vbytes : std_logic_vector(G_DBLK_SIZE/8 -1 downto 0); --! Valid bytes register
signal reg_ploc : std_logic_vector(G_DBLK_SIZE/8 -1 downto 0); --! Pad location register
signal p_size : std_logic_vector(CNTR_WIDTH -1 downto 0); --! Public data segment size
signal p_zpad_di : std_logic_vector(G_W -1 downto 0); --! Internally selected signal for padding
signal p_1pad_di : std_logic_vector(G_W -1 downto 0); --! Internally selected signal for padding
signal input_data : std_logic_vector(G_W -1 downto 0); --! Additional select signal for padding
signal input_vbytes : std_logic_vector(G_W/8 -1 downto 0); --! Additional select signal for bytes size
signal input_ploc : std_logic_vector(G_W/8 -1 downto 0); --! Additional select signal for bytes size
--! Data block status register for external modules
signal len_a_reg : std_logic_vector(LEN_A_WIDTH -1 downto 0); --! Total authenticated data register
signal len_d_reg : std_logic_vector(LEN_D_WIDTH -1 downto 0); --! Total message data register --! Current block contains no message data (used for authenticated encryption data only mode)
--! Padding related signals
signal pad_loc_r : std_logic_vector(G_W/8 -1 downto 0);
--! Lookups
signal vbytes : std_logic_vector(G_W/8 -1 downto 0);
signal ploc : std_logic_vector(G_W/8 -1 downto 0);
begin
p_zpad_di <= pdi when sel_blank_pdi = '0' else (others => '0');
vbytes <= VBYTES_LOOKUP(conv_integer(size_dword));
ploc <= PLOC_LOOKUP(conv_integer(size_dword));
--! Datapath
procReg:
process( clk )
begin
if rising_edge( clk ) then
if rst = '1' then
reg_data <= (others => '0');
reg_exp_tag <= (others => '0');
len_a_reg <= (others => '0');
len_d_reg <= (others => '0');
reg_vbytes <= (others => '0');
else
--! === Public data
--! Data SIPO
if (en_data = '1') then
--! Handle different block size
if (G_W >= G_DBLK_SIZE) then
reg_data <= p_1pad_di(G_W-1 downto G_W-G_DBLK_SIZE);
reg_vbytes <= vbytes(G_W/8-1 downto G_W/8-G_DBLK_SIZE/8);
elsif ((G_DBLK_SIZE MOD G_W) = 0) then
reg_data <= reg_data(G_DBLK_SIZE-G_W-1 downto 0) & p_1pad_di;
reg_vbytes <= reg_vbytes(G_DBLK_SIZE/8-G_W/8-1 downto 0) & vbytes;
elsif ((G_DBLK_SIZE MOD G_W) /= 0) then
if (en_last_word = '0') then
reg_data (G_DBLK_SIZE-1 downto ( G_DBLK_SIZE MOD G_W)) <= reg_data (G_DBLK_SIZE- G_W -1 downto ( G_DBLK_SIZE MOD G_W)) & input_data;
reg_vbytes(G_DBLK_SIZE/8-1 downto ((G_DBLK_SIZE/8) MOD (G_W/8))) <= reg_vbytes(G_DBLK_SIZE/8-G_W/8-1 downto ((G_DBLK_SIZE/8) MOD (G_W/8))) & input_vbytes;
else
reg_data ((G_DBLK_SIZE mod G_W )-1 downto 0) <= input_data (G_W -1 downto G_W /2);
reg_vbytes(((G_DBLK_SIZE/8) mod (G_W/8))-1 downto 0) <= input_vbytes(G_W/8-1 downto (G_W/8)/2);
end if;
end if;
end if;
--! Tag SIPO
if (en_exp_tag = '1') then
--! Handle different block size
if (G_W >= G_TAG_SIZE) then
reg_exp_tag <= pdi(G_W-1 downto G_W-G_TAG_SIZE);
else
reg_exp_tag <= reg_exp_tag(G_TAG_SIZE-G_W-1 downto 0) & pdi;
end if;
end if;
--! === Secret data
--! Key SIPO
if (en_key = '1') then
--! Handle different I/O and key size
if (G_SW < G_KEY_SIZE) then
reg_key <= reg_key(G_KEY_SIZE-G_SW-1 downto 0) & sdi;
elsif G_SW = G_KEY_SIZE then
reg_key <= sdi;
end if;
end if;
--! Round Key SIPO
if (en_rdkey = '1') then
--! Handle different I/O and key size
if (G_SW < G_RDKEY_SIZE) then
reg_rdkey <= reg_rdkey(G_RDKEY_SIZE-G_SW-1 downto 0) & sdi;
elsif G_SW = G_RDKEY_SIZE then
reg_rdkey <= sdi;
end if;
end if;
--! === Status
--! Length registers
if (clr_len = '1') then
len_a_reg <= (others => '0');
len_d_reg <= (others => '0');
else
if (G_LOADLEN_ENABLE = 0) then
if (en_len_a = '1') then
len_a_reg <= len_a_reg + p_size;
end if;
if (en_len_d = '1') then
len_d_reg <= len_d_reg + p_size;
end if;
else
if (en_len_a_r = '1') then
if (G_W >= LEN_A_WIDTH) then
len_a_reg <= pdi(LEN_A_WIDTH-1 downto 0);
elsif ((LEN_A_WIDTH MOD G_W) = 0) then
len_a_reg <= len_a_reg(LEN_A_WIDTH-G_W-1 downto 0) & pdi;
else
if (en_len_last_r = '0') then
if (LEN_A_WIDTH/G_W > 1) then
len_a_reg(LEN_A_WIDTH-1 downto (LEN_A_WIDTH MOD G_W)) <= len_a_reg(LEN_A_WIDTH-G_W-1 downto (LEN_A_WIDTH MOD G_W)) & pdi;
else
len_a_reg(LEN_A_WIDTH-1 downto (LEN_A_WIDTH MOD G_W)) <= pdi;
end if;
else
len_a_reg((LEN_A_WIDTH MOD G_W)-1 downto 0) <= pdi(G_W-1 downto G_W-(LEN_A_WIDTH MOD G_W));
end if;
end if;
end if;
if (en_len_d_r = '1') then
if (G_W >= LEN_D_WIDTH) then
len_d_reg <= pdi(LEN_D_WIDTH-1 downto 0);
elsif ((LEN_D_WIDTH MOD G_W) = 0) then
len_d_reg <= len_d_reg(LEN_D_WIDTH-G_W-1 downto 0) & pdi;
else
if (en_len_last_r = '0') then
if (LEN_D_WIDTH/G_W > 1) then
len_d_reg(LEN_D_WIDTH-1 downto (LEN_D_WIDTH MOD G_W)) <= len_d_reg(LEN_D_WIDTH-G_W-1 downto (LEN_D_WIDTH MOD G_W)) & pdi;
else
len_d_reg(LEN_D_WIDTH-1 downto (LEN_D_WIDTH MOD G_W)) <= pdi;
end if;
else
len_d_reg((LEN_D_WIDTH MOD G_W)-1 downto 0) <= pdi(G_W-1 downto G_W-(LEN_D_WIDTH MOD G_W));
end if;
end if;
end if;
end if;
end if;
end if;
end if;
end process;
--! Public data size (based on the interface)
p_size <= pdi(CNTR_WIDTH -1 downto 0);
--! Output
len_a <= len_a_reg(G_CTR_AD_SIZE -1 downto 0);
len_d <= len_d_reg(G_CTR_D_SIZE -1 downto 0);
bdi <= reg_data;
exp_tag <= reg_exp_tag;
genKey: if (G_RDKEY_ENABLE = 0) generate
key <= reg_key;
end generate;
genRdKey: if (G_RDKEY_ENABLE = 1) generate
rdkey <= reg_rdkey;
end generate;
bdi_valid_bytes <= reg_vbytes;
bdi_pad_loc <= reg_ploc;
genNpub: if (G_NPUB_DISABLE = 0) generate
signal reg_npub : std_logic_vector(REG_NPUB_WIDTH -1 downto 0); --! Npub register
begin
npub <= reg_npub(REG_NPUB_WIDTH-1 downto REG_NPUB_WIDTH-G_NPUB_SIZE);
procReg:
process( clk )
begin
if rising_edge( clk ) then
if (rst = '1') then
reg_npub <= (others => '0');
elsif (en_npub = '1') then
if (G_W >= G_NPUB_SIZE) then
reg_npub <= pdi(G_W-1 downto G_W-REG_NPUB_WIDTH);
else
reg_npub <= reg_npub(REG_NPUB_WIDTH-G_W-1 downto 0) & pdi;
end if;
end if;
end if;
end process;
end generate;
genNsec: if (G_NSEC_ENABLE = 1) generate
signal reg_nsec : std_logic_vector(G_NSEC_SIZE -1 downto 0); --! Nsec register
begin
nsec <= reg_nsec;
procReg:
process( clk )
begin
if rising_edge( clk ) then
if (en_nsec = '1') then
if (G_W < G_NSEC_SIZE) then
reg_nsec <= reg_nsec(G_NSEC_SIZE-G_W-1 downto 0) & pdi;
else
reg_nsec <= pdi(G_W-1 downto G_W-G_NSEC_SIZE);
end if;
end if;
end if;
end process;
end generate;
--! ============ Special mode ===========
genPartial: if ((G_DBLK_SIZE mod G_W) > 0) generate
constant ZEROS : std_logic_vector(G_W-1 downto 0) := (others => '0');
signal padded_reg : std_logic_vector(G_W/2-1 downto 0);
signal dbytes_reg : std_logic_vector((G_W/8)/2-1 downto 0);
begin
process(clk)
begin
if rising_edge(clk) then
if (en_data = '1' and sel_blank_pdi = '0') then
padded_reg <= p_1pad_di(G_W/2-1 downto 0);
dbytes_reg <= vbytes((G_W/8)/2-1 downto 0);
end if;
end if;
end process;
genKeyak0: if G_KEYAK = 0 generate
with sel_input(2 downto 0) select
input_data <= p_1pad_di when "000",
p_1pad_di(G_W-1 downto G_W-G_W/2) & ZEROS(G_W-1 downto G_W-G_W/2) when "001",
padded_reg & p_1pad_di(G_W-1 downto G_W-G_W/2) when "010",
padded_reg & ZEROS(G_W-1 downto G_W-G_W/2) when "011",
(others => '0') when others;
with sel_input(2 downto 0) select
input_vbytes <= vbytes when "000",
vbytes(G_W/8-1 downto G_W/8-(G_W/8)/2) & ZEROS(G_W/8-1 downto G_W/8-(G_W/8)/2) when "001",
dbytes_reg & vbytes(G_W/8-1 downto G_W/8-(G_W/8)/2) when "010",
dbytes_reg & ZEROS(G_W/8-1 downto G_W/8-(G_W/8)/2) when "011",
(others => '0') when others;
end generate;
--! Special loading for Keyak
genKeyak1: if (G_KEYAK = 1 and G_W = 128 and G_DBLK_SIZE = 1344) generate
signal key_r : std_logic_vector(G_KEY_SIZE-1 downto 0);
begin
pKey: process(clk)
begin
if rising_edge(clk) then
if (key_updated = '1') then
key_r <= reg_key;
end if;
end if;
end process;
with sel_input(2 downto 0) select
input_data <= p_1pad_di when "000",
p_1pad_di(G_W-1 downto G_W-G_W/2) & ZEROS(G_W-1 downto G_W-G_W/2) when "001",
padded_reg & p_1pad_di(G_W-1 downto G_W-G_W/2) when "010",
padded_reg & ZEROS(G_W-1 downto G_W-G_W/2) when "011",
x"1E" & key_r(G_KEY_SIZE-1 downto 8) when "100",
key_r(7 downto 0) & x"01" & x"000000000000000000000000" & x"0100" when "101",
(others => '0') when others;
with sel_input(2 downto 0) select
input_vbytes <= vbytes when "000",
vbytes(G_W/8-1 downto G_W/8-(G_W/8)/2) & ZEROS(G_W/8-1 downto G_W/8-(G_W/8)/2) when "001",
dbytes_reg & vbytes(G_W/8-1 downto G_W/8-(G_W/8)/2) when "010",
dbytes_reg & ZEROS(G_W/8-1 downto G_W/8-(G_W/8)/2) when "011",
(others => '1') when "100",
(others => '1') when "101",
(others => '0') when others;
end generate;
end generate;
--! ============ Padding related logic =================
--! No padding unit
genPad0: if G_PAD = 0 generate
begin
p_1pad_di <= p_zpad_di;
end generate;
--! With padding unit
genPad1: if G_PAD = 1 generate
signal pad_loc_s : std_logic_vector(G_W/8 -1 downto 0);
signal ploc_reg : std_logic_vector((G_W/8)/2 -1 downto 0);
begin
--! No actual padding is performed. However, padding location is produced. Used this mode if bdi_pad_loc signal is required)
genPadMode0:
if G_PAD_STYLE = 0 generate
p_1pad_di <= p_zpad_di;
end generate;
--! Pad 10*
genPadMode1:
if G_PAD_STYLE = 1 generate
genLoop:
for i in 0 to G_W/8-1 generate
p_1pad_di(G_W-i*8-1) <= '1' when (pad_enable = '1' and pad_loc_r(i) = '1' ) else p_zpad_di(G_W-i*8-1);
p_1pad_di(G_W-i*8-2 downto G_W-i*8-8) <= p_zpad_di(G_W-i*8-2 downto G_W-i*8-8);
end generate;
end generate;
--! Padding mode for ICEPOLE
genPadMode2:
if G_PAD_STYLE = 2 generate
genLoop:
for i in 0 to G_W/8-1 generate
p_1pad_di(G_W-i*8-1 downto G_W-i*8-6) <= p_zpad_di(G_W-i*8-1 downto G_W-i*8-6);
p_1pad_di(G_W-i*8-7) <= '1' when (pad_enable = '1' and pad_loc_r(i) = '1' ) else p_zpad_di(G_W-i*8-7);
p_1pad_di(G_W-i*8-8) <= '1' when (pad_enable = '1' and pad_loc_r(i) = '1' and ((pad_eot = '1' and pad_type_ad = '1') or (pad_eot = '0' and pad_type_ad = '0'))) else p_zpad_di(G_W-i*8-8);
end generate;
end generate;
--! Padding mode for Keyak
genPadMode3:
if G_PAD_STYLE = 3 generate
genLoop:
for i in 0 to G_W/8-1 generate
p_1pad_di(G_W-i*8-1) <= p_zpad_di(G_W-i*8-1);
p_1pad_di(G_W-i*8-2) <= p_zpad_di(G_W-i*8-2);
p_1pad_di(G_W-i*8-3) <= p_zpad_di(G_W-i*8-3);
p_1pad_di(G_W-i*8-4) <= p_zpad_di(G_W-i*8-4);
p_1pad_di(G_W-i*8-5) <= p_zpad_di(G_W-i*8-5);
p_1pad_di(G_W-i*8-6) <= '1' when (pad_enable = '1' and pad_loc_r(i) = '1') else p_zpad_di(G_W-i*8-6);
p_1pad_di(G_W-i*8-7) <= '1' when (pad_enable = '1' and pad_loc_r(i) = '1' and ((pad_type_ad = '1' and pad_eoi = '0' and pad_eot = '1') or (pad_type_ad = '0' and pad_eot = '0'))) else p_zpad_di(G_W-i*8-7);
p_1pad_di(G_W-i*8-8) <= '1' when (pad_enable = '1' and pad_loc_r(i) = '1' and (pad_type_ad = '0' or (pad_eoi = '1' and pad_type_ad = '1'))) else p_zpad_di(G_W-i*8-8);
end generate;
end generate;
procReg: process(clk)
begin
if rising_edge(clk) then
if en_pad_loc = '1' then
pad_loc_r <= pad_loc_s;
end if;
if G_W >= G_DBLK_SIZE then
if (en_data = '1') then
if (pad_enable = '1') then
reg_ploc <= reverse_bit(pad_loc_r);
else
reg_ploc <= (others => '0');
end if;
end if;
elsif (G_DBLK_SIZE MOD G_W) = 0 then
if (en_data = '1') then
if (pad_enable = '1') then
reg_ploc <= reg_ploc(G_DBLK_SIZE/8-G_W/8-1 downto 0) & reverse_bit(pad_loc_s);
else
reg_ploc <= reg_ploc(G_DBLK_SIZE/8-G_W/8-1 downto 0) & ZWORD_BYTES(G_W/8-1 downto 0);
end if;
end if;
elsif (G_DBLK_SIZE MOD G_W) /= 0 then
if (rst = '1') then
reg_ploc <= (others => '0');
elsif (en_data = '1') then
ploc_reg <= pad_loc_s(((G_W/8)-1) downto ((G_W/8)/2));
if (en_last_word = '0') then
if (pad_enable = '1') then
reg_ploc(G_DBLK_SIZE/8-1 downto ((G_DBLK_SIZE/8) MOD (G_W/8))) <= reg_ploc(G_DBLK_SIZE/8-G_W/8-1 downto ((G_DBLK_SIZE/8) MOD (G_W/8))) & input_ploc;
else
reg_ploc(G_DBLK_SIZE/8-1 downto ((G_DBLK_SIZE/8) MOD (G_W/8))) <= reg_ploc(G_DBLK_SIZE/8-G_W/8-1 downto ((G_DBLK_SIZE/8) MOD (G_W/8))) & ZWORD_BYTES(G_W/8-1 downto 0);
end if;
else
if (pad_enable = '1') then
reg_ploc(((G_DBLK_SIZE/8) mod (G_W/8))-1 downto 0) <= input_ploc(G_W/8-1 downto (G_W/8)/2);
else
reg_ploc(((G_DBLK_SIZE/8) mod (G_W/8))-1 downto 0) <= (others => '0');
end if;
end if;
end if;
end if;
end if;
end process;
gKeyak0:
if ((G_KEYAK = 0) and ((G_DBLK_SIZE MOD G_W) /= 0)) generate
with sel_input(2 downto 0) select
input_ploc <= reverse_bit(pad_loc_s) when "000",
reverse_bit(pad_loc_s)(G_W/8-1 downto (G_W/8)/2) & ZWORD_BYTES(G_W/8-1 downto G_W/8-(G_W/8)/2) when "001",
reverse_bit(ploc_reg) & reverse_bit(pad_loc_s((G_W/8)/2-1 downto 0)) when "010",
reverse_bit(ploc_reg) & ZWORD_BYTES(G_W/8-1 downto G_W/8-(G_W/8)/2) when "011",
(others => '0') when others;
end generate;
gKeyak1:
if (G_KEYAK = 1) generate
with sel_input(2 downto 0) select
input_ploc <= reverse_bit(pad_loc_s) when "000",
reverse_bit(pad_loc_s)(G_W/8-1 downto (G_W/8)/2) & ZWORD_BYTES(G_W/8-1 downto G_W/8-(G_W/8)/2) when "001",
reverse_bit(ploc_reg) & reverse_bit(pad_loc_s((G_W/8)/2-1 downto 0)) when "010",
reverse_bit(ploc_reg) & ZWORD_BYTES(G_W/8-1 downto G_W/8-(G_W/8)/2) when "011",
(others => '0') when others;
-- with sel_input(2 downto 0) select
-- input_ploc <= reverse_bit(pad_loc_s) when "000",
-- reverse_bit(ploc_reg) & reverse_bit(pad_loc_s((G_W/8)/2-1 downto 0)) when "001",
-- reverse_bit(ploc_reg) & ZWORD_BYTES(G_W/8-1 downto G_W/8-(G_W/8)/2) when "010",
-- (others => '0') when others;
end generate;
--! Calculate the padding locatin
uBarrelShifter:
entity work.bshift(struct)
generic map (G_W => G_W/8, G_LOG2_W => LOG2_W, G_LEFT => 1, G_ROTATE => 0)
port map (ii => BSHIFT_INPUT, rtr => pad_shift, oo => pad_loc_s);
end generate;
end dataflow;
|
-------------------------------------------------------------------------------
--! @file PreProcessor_Datapath.vhd
--! @brief Datapath for the pre-processor
--! @project CAESAR Candidate Evaluation
--! @author Ekawat (ice) Homsirikamol
--! @copyright Copyright (c) 2015 Cryptographic Engineering Research Group
--! ECE Department, George Mason University Fairfax, VA, U.S.A.
--! All rights Reserved.
--! @license This project is released under the GNU Public License.
--! The license and distribution terms for this file may be
--! found in the file LICENSE in this distribution or at
--! http://www.gnu.org/licenses/gpl-3.0.txt
--! @note This is publicly available encryption source code that falls
--! under the License Exception TSU (Technology and software-
--! —unrestricted)
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use work.AEAD_pkg.all;
entity PreProcessor_Datapath is
generic (
G_W : integer := 64; --! Public data width (bits)
G_SW : integer := 64; --! Secret data width (bits)
G_CTR_AD_SIZE : integer := 64; --! Maximum size for the counter that keeps track of authenticated data
G_CTR_D_SIZE : integer := 64; --! Maximum size for the counter that keeps track of data
G_DBLK_SIZE : integer := 128; --! Block size (bits)
G_KEY_SIZE : integer := 128; --! Key size (bits)
G_KEYAK : integer := 0; --! Special input mode, used only for Keyak with G_W = 128 and G_DBLK_SIZE = 1344
G_NPUB_DISABLE : integer := 0; --! Disable Npub related port(s)
G_NPUB_SIZE : integer := 128; --! Npub width (bits)
G_NSEC_ENABLE : integer := 0; --! Enable nsec port
G_NSEC_SIZE : integer := 128; --! Nsec width (bits)
G_LOADLEN_ENABLE : integer := 0; --! Enable load length section
G_PAD : integer := 0; --! Enable padding
G_PAD_STYLE : integer := 1; --! Padding mode 0 = *10..., 1 = ICEPOLE's padding
G_RDKEY_ENABLE : integer := 0; --! Enable rdkey port (also disables key port)
G_RDKEY_SIZE : integer := 128; --! Roundkey size (bits)
G_TAG_SIZE : integer := 128 --! Tag size (bits)
);
port (
--! =================
--! External Signals
--! =================
--! Global signals
clk : in std_logic;
rst : in std_logic;
pdi : in std_logic_vector(G_W -1 downto 0); --! Public data
sdi : in std_logic_vector(G_SW -1 downto 0); --! Secret data
--! =================
--! Crypto Core Signals
--! =================
key : out std_logic_vector(G_KEY_SIZE -1 downto 0); --! Key data
rdkey : out std_logic_vector(G_RDKEY_SIZE -1 downto 0); --! Round key data
bdi : out std_logic_vector(G_DBLK_SIZE -1 downto 0); --! Block data
npub : out std_logic_vector(G_NPUB_SIZE -1 downto 0); --! Npub data
nsec : out std_logic_vector(G_NSEC_SIZE -1 downto 0); --! Nsec data
exp_tag : out std_logic_vector(G_TAG_SIZE -1 downto 0); --! Expected tag data
bdi_valid_bytes : out std_logic_vector(G_DBLK_SIZE/8 -1 downto 0);
bdi_pad_loc : out std_logic_vector(G_DBLK_SIZE/8 -1 downto 0);
len_a : out std_logic_vector(G_CTR_AD_SIZE -1 downto 0); --! Len of authenticated data in bytes (used for some algorithm)
len_d : out std_logic_vector(G_CTR_D_SIZE -1 downto 0); --! Len of data in bytes (used for some algorithm)
--! =================
--! Internal Signals
--! =================
--! Control signals
key_updated : in std_logic; --! (if G_DBLK_SIZE mod G_W > 0) Key updated signal (used only for situation when key is stored within input processor)
pad_shift : in std_logic_vector(log2_ceil(G_W/8) -1 downto 0);
en_data : in std_logic; --! Shift data SIPO
en_npub : in std_logic; --! Shift Npub SIPO
en_nsec : in std_logic; --! Shift Nsec SIPO
en_key : in std_logic; --! Shift key SIPO
en_rdkey : in std_logic; --! Shift round key SIPO
en_exp_tag : in std_logic; --! Shift expected tag SIPO
sel_blank_pdi : in std_logic; --! Select input data as blank (for filling in the remaining data within a block)
clr_len : in std_logic; --! Clear stored length (len_a and len_d)
en_len_a_r : in std_logic; --! Add authenticated data counter
en_len_d_r : in std_logic; --! Add data counter
en_len_last_r : in std_logic; --! Special signal for en_len_*_r
en_len_a : in std_logic; --! Add authenticated data counter (instant)
en_len_d : in std_logic; --! Add data counter (no)
size_dword : in std_logic_vector(log2_ceil(G_W/8) downto 0); --! Size of data word
en_last_word : in std_logic; --! Last word in a block
pad_eot : in std_logic; --! Padding is EOT
pad_eoi : in std_logic; --! Padding is EOI
pad_type_ad : in std_logic; --! Padding is AD
pad_enable : in std_logic; --! Enable padding signal (indicates that the current word requires padding)
en_pad_loc : in std_logic; --! Save the padding location into a register
sel_input : in std_logic_vector(3 -1 downto 0) --! (if G_DBLK_SIZE mod G_W > 0) Select input for m
);
end PreProcessor_Datapath;
architecture dataflow of PreProcessor_Datapath is
--! Constants declaration
constant LOG2_W : integer := log2_ceil(G_W/8); --! LOG_2(G_W)
constant LOG2_SW : integer := log2_ceil(G_SW/8); --! LOG_2(G_SW)
constant REG_NPUB_WIDTH : integer := (((G_NPUB_SIZE-1)/G_W)+1)*G_W; --! Calculate the width of Npub register
constant CNTR_WIDTH : integer := get_cntr_width(G_W); --! Calculate the length of p_size register
constant LEN_A_WIDTH : integer := maximum(CNTR_WIDTH, G_CTR_AD_SIZE);
constant LEN_D_WIDTH : integer := maximum(CNTR_WIDTH, G_CTR_D_SIZE);
constant CNT_DATA_WORDS : integer := (G_DBLK_SIZE+(G_W-1))/G_W; --! Calculate the number of words required for data (rounded up)
constant CNT_TAG_WORDS : integer := (G_DBLK_SIZE+(G_W-1))/G_W; --! Calculate the number of words required for tag (rounded up)
constant BSHIFT_INPUT : std_logic_vector(G_W/8 -1 downto 0) := std_logic_vector(to_unsigned(1,G_W/8));
constant OWORD_BYTES : std_logic_vector(G_DBLK_SIZE/8 -1 downto 0) := (others => '1'); --! The number of bytes in a word in ones.
constant ZWORD_BYTES : std_logic_vector(G_DBLK_SIZE/8 -1 downto 0) := (others => '0'); --! The number of bytes in a word in zeros.
function reverse_bit(aa: std_logic_vector) return std_logic_vector is
variable bb : std_logic_vector(aa'high downto aa'low);
begin
for i in aa'high downto aa'low loop
bb(i) := aa(aa'high-i);
end loop;
return bb;
end function reverse_bit;
type lookup_type is array (0 to ((G_W/8)*2-1)) of std_logic_vector(G_W/8-1 downto 0);
function getVbytesLookup(size: integer) return lookup_type is
variable ret : lookup_type;
begin
for i in 0 to ((size/8)*2-1) loop
if (i >= (size/8)) then
ret(i) := (others => '1');
elsif (i = 0) then
ret(i) := (others => '0');
else
ret(i)(size/8-1 downto size/8-i) := (others => '1');
ret(i)(size/8-i-1 downto 0) := (others => '0');
end if;
end loop;
return ret;
end function getVbytesLookup;
constant VBYTES_LOOKUP : lookup_type := getVbytesLookup(G_W);
--! ==================
--! Note: Current unused (keep this portion for later consideration)
function getPlocLookup(size: integer) return lookup_type is
variable ret : lookup_type;
begin
for i in 0 to ((size/8)*2-1) loop
if (i >= (size/8)) then
ret(i) := (others => '0');
else
ret(i) := (i => '1', others => '0');
end if;
end loop;
return ret;
end function getPlocLookup;
constant PLOC_LOOKUP : lookup_type := getPlocLookup(G_W);
--! End of note
--! ==================
--! Key related signals and registers
signal reg_key : std_logic_vector(G_KEY_SIZE -1 downto 0);
signal reg_rdkey : std_logic_vector(G_RDKEY_SIZE -1 downto 0);
--! Public data signals and registers
signal reg_data : std_logic_vector(G_DBLK_SIZE -1 downto 0); --! Data block register
signal reg_exp_tag : std_logic_vector(G_TAG_SIZE -1 downto 0); --! Tag register
signal reg_vbytes : std_logic_vector(G_DBLK_SIZE/8 -1 downto 0); --! Valid bytes register
signal reg_ploc : std_logic_vector(G_DBLK_SIZE/8 -1 downto 0); --! Pad location register
signal p_size : std_logic_vector(CNTR_WIDTH -1 downto 0); --! Public data segment size
signal p_zpad_di : std_logic_vector(G_W -1 downto 0); --! Internally selected signal for padding
signal p_1pad_di : std_logic_vector(G_W -1 downto 0); --! Internally selected signal for padding
signal input_data : std_logic_vector(G_W -1 downto 0); --! Additional select signal for padding
signal input_vbytes : std_logic_vector(G_W/8 -1 downto 0); --! Additional select signal for bytes size
signal input_ploc : std_logic_vector(G_W/8 -1 downto 0); --! Additional select signal for bytes size
--! Data block status register for external modules
signal len_a_reg : std_logic_vector(LEN_A_WIDTH -1 downto 0); --! Total authenticated data register
signal len_d_reg : std_logic_vector(LEN_D_WIDTH -1 downto 0); --! Total message data register --! Current block contains no message data (used for authenticated encryption data only mode)
--! Padding related signals
signal pad_loc_r : std_logic_vector(G_W/8 -1 downto 0);
--! Lookups
signal vbytes : std_logic_vector(G_W/8 -1 downto 0);
signal ploc : std_logic_vector(G_W/8 -1 downto 0);
begin
p_zpad_di <= pdi when sel_blank_pdi = '0' else (others => '0');
vbytes <= VBYTES_LOOKUP(conv_integer(size_dword));
ploc <= PLOC_LOOKUP(conv_integer(size_dword));
--! Datapath
procReg:
process( clk )
begin
if rising_edge( clk ) then
if rst = '1' then
reg_data <= (others => '0');
reg_exp_tag <= (others => '0');
len_a_reg <= (others => '0');
len_d_reg <= (others => '0');
reg_vbytes <= (others => '0');
else
--! === Public data
--! Data SIPO
if (en_data = '1') then
--! Handle different block size
if (G_W >= G_DBLK_SIZE) then
reg_data <= p_1pad_di(G_W-1 downto G_W-G_DBLK_SIZE);
reg_vbytes <= vbytes(G_W/8-1 downto G_W/8-G_DBLK_SIZE/8);
elsif ((G_DBLK_SIZE MOD G_W) = 0) then
reg_data <= reg_data(G_DBLK_SIZE-G_W-1 downto 0) & p_1pad_di;
reg_vbytes <= reg_vbytes(G_DBLK_SIZE/8-G_W/8-1 downto 0) & vbytes;
elsif ((G_DBLK_SIZE MOD G_W) /= 0) then
if (en_last_word = '0') then
reg_data (G_DBLK_SIZE-1 downto ( G_DBLK_SIZE MOD G_W)) <= reg_data (G_DBLK_SIZE- G_W -1 downto ( G_DBLK_SIZE MOD G_W)) & input_data;
reg_vbytes(G_DBLK_SIZE/8-1 downto ((G_DBLK_SIZE/8) MOD (G_W/8))) <= reg_vbytes(G_DBLK_SIZE/8-G_W/8-1 downto ((G_DBLK_SIZE/8) MOD (G_W/8))) & input_vbytes;
else
reg_data ((G_DBLK_SIZE mod G_W )-1 downto 0) <= input_data (G_W -1 downto G_W /2);
reg_vbytes(((G_DBLK_SIZE/8) mod (G_W/8))-1 downto 0) <= input_vbytes(G_W/8-1 downto (G_W/8)/2);
end if;
end if;
end if;
--! Tag SIPO
if (en_exp_tag = '1') then
--! Handle different block size
if (G_W >= G_TAG_SIZE) then
reg_exp_tag <= pdi(G_W-1 downto G_W-G_TAG_SIZE);
else
reg_exp_tag <= reg_exp_tag(G_TAG_SIZE-G_W-1 downto 0) & pdi;
end if;
end if;
--! === Secret data
--! Key SIPO
if (en_key = '1') then
--! Handle different I/O and key size
if (G_SW < G_KEY_SIZE) then
reg_key <= reg_key(G_KEY_SIZE-G_SW-1 downto 0) & sdi;
elsif G_SW = G_KEY_SIZE then
reg_key <= sdi;
end if;
end if;
--! Round Key SIPO
if (en_rdkey = '1') then
--! Handle different I/O and key size
if (G_SW < G_RDKEY_SIZE) then
reg_rdkey <= reg_rdkey(G_RDKEY_SIZE-G_SW-1 downto 0) & sdi;
elsif G_SW = G_RDKEY_SIZE then
reg_rdkey <= sdi;
end if;
end if;
--! === Status
--! Length registers
if (clr_len = '1') then
len_a_reg <= (others => '0');
len_d_reg <= (others => '0');
else
if (G_LOADLEN_ENABLE = 0) then
if (en_len_a = '1') then
len_a_reg <= len_a_reg + p_size;
end if;
if (en_len_d = '1') then
len_d_reg <= len_d_reg + p_size;
end if;
else
if (en_len_a_r = '1') then
if (G_W >= LEN_A_WIDTH) then
len_a_reg <= pdi(LEN_A_WIDTH-1 downto 0);
elsif ((LEN_A_WIDTH MOD G_W) = 0) then
len_a_reg <= len_a_reg(LEN_A_WIDTH-G_W-1 downto 0) & pdi;
else
if (en_len_last_r = '0') then
if (LEN_A_WIDTH/G_W > 1) then
len_a_reg(LEN_A_WIDTH-1 downto (LEN_A_WIDTH MOD G_W)) <= len_a_reg(LEN_A_WIDTH-G_W-1 downto (LEN_A_WIDTH MOD G_W)) & pdi;
else
len_a_reg(LEN_A_WIDTH-1 downto (LEN_A_WIDTH MOD G_W)) <= pdi;
end if;
else
len_a_reg((LEN_A_WIDTH MOD G_W)-1 downto 0) <= pdi(G_W-1 downto G_W-(LEN_A_WIDTH MOD G_W));
end if;
end if;
end if;
if (en_len_d_r = '1') then
if (G_W >= LEN_D_WIDTH) then
len_d_reg <= pdi(LEN_D_WIDTH-1 downto 0);
elsif ((LEN_D_WIDTH MOD G_W) = 0) then
len_d_reg <= len_d_reg(LEN_D_WIDTH-G_W-1 downto 0) & pdi;
else
if (en_len_last_r = '0') then
if (LEN_D_WIDTH/G_W > 1) then
len_d_reg(LEN_D_WIDTH-1 downto (LEN_D_WIDTH MOD G_W)) <= len_d_reg(LEN_D_WIDTH-G_W-1 downto (LEN_D_WIDTH MOD G_W)) & pdi;
else
len_d_reg(LEN_D_WIDTH-1 downto (LEN_D_WIDTH MOD G_W)) <= pdi;
end if;
else
len_d_reg((LEN_D_WIDTH MOD G_W)-1 downto 0) <= pdi(G_W-1 downto G_W-(LEN_D_WIDTH MOD G_W));
end if;
end if;
end if;
end if;
end if;
end if;
end if;
end process;
--! Public data size (based on the interface)
p_size <= pdi(CNTR_WIDTH -1 downto 0);
--! Output
len_a <= len_a_reg(G_CTR_AD_SIZE -1 downto 0);
len_d <= len_d_reg(G_CTR_D_SIZE -1 downto 0);
bdi <= reg_data;
exp_tag <= reg_exp_tag;
genKey: if (G_RDKEY_ENABLE = 0) generate
key <= reg_key;
end generate;
genRdKey: if (G_RDKEY_ENABLE = 1) generate
rdkey <= reg_rdkey;
end generate;
bdi_valid_bytes <= reg_vbytes;
bdi_pad_loc <= reg_ploc;
genNpub: if (G_NPUB_DISABLE = 0) generate
signal reg_npub : std_logic_vector(REG_NPUB_WIDTH -1 downto 0); --! Npub register
begin
npub <= reg_npub(REG_NPUB_WIDTH-1 downto REG_NPUB_WIDTH-G_NPUB_SIZE);
procReg:
process( clk )
begin
if rising_edge( clk ) then
if (rst = '1') then
reg_npub <= (others => '0');
elsif (en_npub = '1') then
if (G_W >= G_NPUB_SIZE) then
reg_npub <= pdi(G_W-1 downto G_W-REG_NPUB_WIDTH);
else
reg_npub <= reg_npub(REG_NPUB_WIDTH-G_W-1 downto 0) & pdi;
end if;
end if;
end if;
end process;
end generate;
genNsec: if (G_NSEC_ENABLE = 1) generate
signal reg_nsec : std_logic_vector(G_NSEC_SIZE -1 downto 0); --! Nsec register
begin
nsec <= reg_nsec;
procReg:
process( clk )
begin
if rising_edge( clk ) then
if (en_nsec = '1') then
if (G_W < G_NSEC_SIZE) then
reg_nsec <= reg_nsec(G_NSEC_SIZE-G_W-1 downto 0) & pdi;
else
reg_nsec <= pdi(G_W-1 downto G_W-G_NSEC_SIZE);
end if;
end if;
end if;
end process;
end generate;
--! ============ Special mode ===========
genPartial: if ((G_DBLK_SIZE mod G_W) > 0) generate
constant ZEROS : std_logic_vector(G_W-1 downto 0) := (others => '0');
signal padded_reg : std_logic_vector(G_W/2-1 downto 0);
signal dbytes_reg : std_logic_vector((G_W/8)/2-1 downto 0);
begin
process(clk)
begin
if rising_edge(clk) then
if (en_data = '1' and sel_blank_pdi = '0') then
padded_reg <= p_1pad_di(G_W/2-1 downto 0);
dbytes_reg <= vbytes((G_W/8)/2-1 downto 0);
end if;
end if;
end process;
genKeyak0: if G_KEYAK = 0 generate
with sel_input(2 downto 0) select
input_data <= p_1pad_di when "000",
p_1pad_di(G_W-1 downto G_W-G_W/2) & ZEROS(G_W-1 downto G_W-G_W/2) when "001",
padded_reg & p_1pad_di(G_W-1 downto G_W-G_W/2) when "010",
padded_reg & ZEROS(G_W-1 downto G_W-G_W/2) when "011",
(others => '0') when others;
with sel_input(2 downto 0) select
input_vbytes <= vbytes when "000",
vbytes(G_W/8-1 downto G_W/8-(G_W/8)/2) & ZEROS(G_W/8-1 downto G_W/8-(G_W/8)/2) when "001",
dbytes_reg & vbytes(G_W/8-1 downto G_W/8-(G_W/8)/2) when "010",
dbytes_reg & ZEROS(G_W/8-1 downto G_W/8-(G_W/8)/2) when "011",
(others => '0') when others;
end generate;
--! Special loading for Keyak
genKeyak1: if (G_KEYAK = 1 and G_W = 128 and G_DBLK_SIZE = 1344) generate
signal key_r : std_logic_vector(G_KEY_SIZE-1 downto 0);
begin
pKey: process(clk)
begin
if rising_edge(clk) then
if (key_updated = '1') then
key_r <= reg_key;
end if;
end if;
end process;
with sel_input(2 downto 0) select
input_data <= p_1pad_di when "000",
p_1pad_di(G_W-1 downto G_W-G_W/2) & ZEROS(G_W-1 downto G_W-G_W/2) when "001",
padded_reg & p_1pad_di(G_W-1 downto G_W-G_W/2) when "010",
padded_reg & ZEROS(G_W-1 downto G_W-G_W/2) when "011",
x"1E" & key_r(G_KEY_SIZE-1 downto 8) when "100",
key_r(7 downto 0) & x"01" & x"000000000000000000000000" & x"0100" when "101",
(others => '0') when others;
with sel_input(2 downto 0) select
input_vbytes <= vbytes when "000",
vbytes(G_W/8-1 downto G_W/8-(G_W/8)/2) & ZEROS(G_W/8-1 downto G_W/8-(G_W/8)/2) when "001",
dbytes_reg & vbytes(G_W/8-1 downto G_W/8-(G_W/8)/2) when "010",
dbytes_reg & ZEROS(G_W/8-1 downto G_W/8-(G_W/8)/2) when "011",
(others => '1') when "100",
(others => '1') when "101",
(others => '0') when others;
end generate;
end generate;
--! ============ Padding related logic =================
--! No padding unit
genPad0: if G_PAD = 0 generate
begin
p_1pad_di <= p_zpad_di;
end generate;
--! With padding unit
genPad1: if G_PAD = 1 generate
signal pad_loc_s : std_logic_vector(G_W/8 -1 downto 0);
signal ploc_reg : std_logic_vector((G_W/8)/2 -1 downto 0);
begin
--! No actual padding is performed. However, padding location is produced. Used this mode if bdi_pad_loc signal is required)
genPadMode0:
if G_PAD_STYLE = 0 generate
p_1pad_di <= p_zpad_di;
end generate;
--! Pad 10*
genPadMode1:
if G_PAD_STYLE = 1 generate
genLoop:
for i in 0 to G_W/8-1 generate
p_1pad_di(G_W-i*8-1) <= '1' when (pad_enable = '1' and pad_loc_r(i) = '1' ) else p_zpad_di(G_W-i*8-1);
p_1pad_di(G_W-i*8-2 downto G_W-i*8-8) <= p_zpad_di(G_W-i*8-2 downto G_W-i*8-8);
end generate;
end generate;
--! Padding mode for ICEPOLE
genPadMode2:
if G_PAD_STYLE = 2 generate
genLoop:
for i in 0 to G_W/8-1 generate
p_1pad_di(G_W-i*8-1 downto G_W-i*8-6) <= p_zpad_di(G_W-i*8-1 downto G_W-i*8-6);
p_1pad_di(G_W-i*8-7) <= '1' when (pad_enable = '1' and pad_loc_r(i) = '1' ) else p_zpad_di(G_W-i*8-7);
p_1pad_di(G_W-i*8-8) <= '1' when (pad_enable = '1' and pad_loc_r(i) = '1' and ((pad_eot = '1' and pad_type_ad = '1') or (pad_eot = '0' and pad_type_ad = '0'))) else p_zpad_di(G_W-i*8-8);
end generate;
end generate;
--! Padding mode for Keyak
genPadMode3:
if G_PAD_STYLE = 3 generate
genLoop:
for i in 0 to G_W/8-1 generate
p_1pad_di(G_W-i*8-1) <= p_zpad_di(G_W-i*8-1);
p_1pad_di(G_W-i*8-2) <= p_zpad_di(G_W-i*8-2);
p_1pad_di(G_W-i*8-3) <= p_zpad_di(G_W-i*8-3);
p_1pad_di(G_W-i*8-4) <= p_zpad_di(G_W-i*8-4);
p_1pad_di(G_W-i*8-5) <= p_zpad_di(G_W-i*8-5);
p_1pad_di(G_W-i*8-6) <= '1' when (pad_enable = '1' and pad_loc_r(i) = '1') else p_zpad_di(G_W-i*8-6);
p_1pad_di(G_W-i*8-7) <= '1' when (pad_enable = '1' and pad_loc_r(i) = '1' and ((pad_type_ad = '1' and pad_eoi = '0' and pad_eot = '1') or (pad_type_ad = '0' and pad_eot = '0'))) else p_zpad_di(G_W-i*8-7);
p_1pad_di(G_W-i*8-8) <= '1' when (pad_enable = '1' and pad_loc_r(i) = '1' and (pad_type_ad = '0' or (pad_eoi = '1' and pad_type_ad = '1'))) else p_zpad_di(G_W-i*8-8);
end generate;
end generate;
procReg: process(clk)
begin
if rising_edge(clk) then
if en_pad_loc = '1' then
pad_loc_r <= pad_loc_s;
end if;
if G_W >= G_DBLK_SIZE then
if (en_data = '1') then
if (pad_enable = '1') then
reg_ploc <= reverse_bit(pad_loc_r);
else
reg_ploc <= (others => '0');
end if;
end if;
elsif (G_DBLK_SIZE MOD G_W) = 0 then
if (en_data = '1') then
if (pad_enable = '1') then
reg_ploc <= reg_ploc(G_DBLK_SIZE/8-G_W/8-1 downto 0) & reverse_bit(pad_loc_s);
else
reg_ploc <= reg_ploc(G_DBLK_SIZE/8-G_W/8-1 downto 0) & ZWORD_BYTES(G_W/8-1 downto 0);
end if;
end if;
elsif (G_DBLK_SIZE MOD G_W) /= 0 then
if (rst = '1') then
reg_ploc <= (others => '0');
elsif (en_data = '1') then
ploc_reg <= pad_loc_s(((G_W/8)-1) downto ((G_W/8)/2));
if (en_last_word = '0') then
if (pad_enable = '1') then
reg_ploc(G_DBLK_SIZE/8-1 downto ((G_DBLK_SIZE/8) MOD (G_W/8))) <= reg_ploc(G_DBLK_SIZE/8-G_W/8-1 downto ((G_DBLK_SIZE/8) MOD (G_W/8))) & input_ploc;
else
reg_ploc(G_DBLK_SIZE/8-1 downto ((G_DBLK_SIZE/8) MOD (G_W/8))) <= reg_ploc(G_DBLK_SIZE/8-G_W/8-1 downto ((G_DBLK_SIZE/8) MOD (G_W/8))) & ZWORD_BYTES(G_W/8-1 downto 0);
end if;
else
if (pad_enable = '1') then
reg_ploc(((G_DBLK_SIZE/8) mod (G_W/8))-1 downto 0) <= input_ploc(G_W/8-1 downto (G_W/8)/2);
else
reg_ploc(((G_DBLK_SIZE/8) mod (G_W/8))-1 downto 0) <= (others => '0');
end if;
end if;
end if;
end if;
end if;
end process;
gKeyak0:
if ((G_KEYAK = 0) and ((G_DBLK_SIZE MOD G_W) /= 0)) generate
with sel_input(2 downto 0) select
input_ploc <= reverse_bit(pad_loc_s) when "000",
reverse_bit(pad_loc_s)(G_W/8-1 downto (G_W/8)/2) & ZWORD_BYTES(G_W/8-1 downto G_W/8-(G_W/8)/2) when "001",
reverse_bit(ploc_reg) & reverse_bit(pad_loc_s((G_W/8)/2-1 downto 0)) when "010",
reverse_bit(ploc_reg) & ZWORD_BYTES(G_W/8-1 downto G_W/8-(G_W/8)/2) when "011",
(others => '0') when others;
end generate;
gKeyak1:
if (G_KEYAK = 1) generate
with sel_input(2 downto 0) select
input_ploc <= reverse_bit(pad_loc_s) when "000",
reverse_bit(pad_loc_s)(G_W/8-1 downto (G_W/8)/2) & ZWORD_BYTES(G_W/8-1 downto G_W/8-(G_W/8)/2) when "001",
reverse_bit(ploc_reg) & reverse_bit(pad_loc_s((G_W/8)/2-1 downto 0)) when "010",
reverse_bit(ploc_reg) & ZWORD_BYTES(G_W/8-1 downto G_W/8-(G_W/8)/2) when "011",
(others => '0') when others;
-- with sel_input(2 downto 0) select
-- input_ploc <= reverse_bit(pad_loc_s) when "000",
-- reverse_bit(ploc_reg) & reverse_bit(pad_loc_s((G_W/8)/2-1 downto 0)) when "001",
-- reverse_bit(ploc_reg) & ZWORD_BYTES(G_W/8-1 downto G_W/8-(G_W/8)/2) when "010",
-- (others => '0') when others;
end generate;
--! Calculate the padding locatin
uBarrelShifter:
entity work.bshift(struct)
generic map (G_W => G_W/8, G_LOG2_W => LOG2_W, G_LEFT => 1, G_ROTATE => 0)
port map (ii => BSHIFT_INPUT, rtr => pad_shift, oo => pad_loc_s);
end generate;
end dataflow;
|
-------------------------------------------------------------------------------
--! @file PreProcessor_Datapath.vhd
--! @brief Datapath for the pre-processor
--! @project CAESAR Candidate Evaluation
--! @author Ekawat (ice) Homsirikamol
--! @copyright Copyright (c) 2015 Cryptographic Engineering Research Group
--! ECE Department, George Mason University Fairfax, VA, U.S.A.
--! All rights Reserved.
--! @license This project is released under the GNU Public License.
--! The license and distribution terms for this file may be
--! found in the file LICENSE in this distribution or at
--! http://www.gnu.org/licenses/gpl-3.0.txt
--! @note This is publicly available encryption source code that falls
--! under the License Exception TSU (Technology and software-
--! —unrestricted)
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use work.AEAD_pkg.all;
entity PreProcessor_Datapath is
generic (
G_W : integer := 64; --! Public data width (bits)
G_SW : integer := 64; --! Secret data width (bits)
G_CTR_AD_SIZE : integer := 64; --! Maximum size for the counter that keeps track of authenticated data
G_CTR_D_SIZE : integer := 64; --! Maximum size for the counter that keeps track of data
G_DBLK_SIZE : integer := 128; --! Block size (bits)
G_KEY_SIZE : integer := 128; --! Key size (bits)
G_KEYAK : integer := 0; --! Special input mode, used only for Keyak with G_W = 128 and G_DBLK_SIZE = 1344
G_NPUB_DISABLE : integer := 0; --! Disable Npub related port(s)
G_NPUB_SIZE : integer := 128; --! Npub width (bits)
G_NSEC_ENABLE : integer := 0; --! Enable nsec port
G_NSEC_SIZE : integer := 128; --! Nsec width (bits)
G_LOADLEN_ENABLE : integer := 0; --! Enable load length section
G_PAD : integer := 0; --! Enable padding
G_PAD_STYLE : integer := 1; --! Padding mode 0 = *10..., 1 = ICEPOLE's padding
G_RDKEY_ENABLE : integer := 0; --! Enable rdkey port (also disables key port)
G_RDKEY_SIZE : integer := 128; --! Roundkey size (bits)
G_TAG_SIZE : integer := 128 --! Tag size (bits)
);
port (
--! =================
--! External Signals
--! =================
--! Global signals
clk : in std_logic;
rst : in std_logic;
pdi : in std_logic_vector(G_W -1 downto 0); --! Public data
sdi : in std_logic_vector(G_SW -1 downto 0); --! Secret data
--! =================
--! Crypto Core Signals
--! =================
key : out std_logic_vector(G_KEY_SIZE -1 downto 0); --! Key data
rdkey : out std_logic_vector(G_RDKEY_SIZE -1 downto 0); --! Round key data
bdi : out std_logic_vector(G_DBLK_SIZE -1 downto 0); --! Block data
npub : out std_logic_vector(G_NPUB_SIZE -1 downto 0); --! Npub data
nsec : out std_logic_vector(G_NSEC_SIZE -1 downto 0); --! Nsec data
exp_tag : out std_logic_vector(G_TAG_SIZE -1 downto 0); --! Expected tag data
bdi_valid_bytes : out std_logic_vector(G_DBLK_SIZE/8 -1 downto 0);
bdi_pad_loc : out std_logic_vector(G_DBLK_SIZE/8 -1 downto 0);
len_a : out std_logic_vector(G_CTR_AD_SIZE -1 downto 0); --! Len of authenticated data in bytes (used for some algorithm)
len_d : out std_logic_vector(G_CTR_D_SIZE -1 downto 0); --! Len of data in bytes (used for some algorithm)
--! =================
--! Internal Signals
--! =================
--! Control signals
key_updated : in std_logic; --! (if G_DBLK_SIZE mod G_W > 0) Key updated signal (used only for situation when key is stored within input processor)
pad_shift : in std_logic_vector(log2_ceil(G_W/8) -1 downto 0);
en_data : in std_logic; --! Shift data SIPO
en_npub : in std_logic; --! Shift Npub SIPO
en_nsec : in std_logic; --! Shift Nsec SIPO
en_key : in std_logic; --! Shift key SIPO
en_rdkey : in std_logic; --! Shift round key SIPO
en_exp_tag : in std_logic; --! Shift expected tag SIPO
sel_blank_pdi : in std_logic; --! Select input data as blank (for filling in the remaining data within a block)
clr_len : in std_logic; --! Clear stored length (len_a and len_d)
en_len_a_r : in std_logic; --! Add authenticated data counter
en_len_d_r : in std_logic; --! Add data counter
en_len_last_r : in std_logic; --! Special signal for en_len_*_r
en_len_a : in std_logic; --! Add authenticated data counter (instant)
en_len_d : in std_logic; --! Add data counter (no)
size_dword : in std_logic_vector(log2_ceil(G_W/8) downto 0); --! Size of data word
en_last_word : in std_logic; --! Last word in a block
pad_eot : in std_logic; --! Padding is EOT
pad_eoi : in std_logic; --! Padding is EOI
pad_type_ad : in std_logic; --! Padding is AD
pad_enable : in std_logic; --! Enable padding signal (indicates that the current word requires padding)
en_pad_loc : in std_logic; --! Save the padding location into a register
sel_input : in std_logic_vector(3 -1 downto 0) --! (if G_DBLK_SIZE mod G_W > 0) Select input for m
);
end PreProcessor_Datapath;
architecture dataflow of PreProcessor_Datapath is
--! Constants declaration
constant LOG2_W : integer := log2_ceil(G_W/8); --! LOG_2(G_W)
constant LOG2_SW : integer := log2_ceil(G_SW/8); --! LOG_2(G_SW)
constant REG_NPUB_WIDTH : integer := (((G_NPUB_SIZE-1)/G_W)+1)*G_W; --! Calculate the width of Npub register
constant CNTR_WIDTH : integer := get_cntr_width(G_W); --! Calculate the length of p_size register
constant LEN_A_WIDTH : integer := maximum(CNTR_WIDTH, G_CTR_AD_SIZE);
constant LEN_D_WIDTH : integer := maximum(CNTR_WIDTH, G_CTR_D_SIZE);
constant CNT_DATA_WORDS : integer := (G_DBLK_SIZE+(G_W-1))/G_W; --! Calculate the number of words required for data (rounded up)
constant CNT_TAG_WORDS : integer := (G_DBLK_SIZE+(G_W-1))/G_W; --! Calculate the number of words required for tag (rounded up)
constant BSHIFT_INPUT : std_logic_vector(G_W/8 -1 downto 0) := std_logic_vector(to_unsigned(1,G_W/8));
constant OWORD_BYTES : std_logic_vector(G_DBLK_SIZE/8 -1 downto 0) := (others => '1'); --! The number of bytes in a word in ones.
constant ZWORD_BYTES : std_logic_vector(G_DBLK_SIZE/8 -1 downto 0) := (others => '0'); --! The number of bytes in a word in zeros.
function reverse_bit(aa: std_logic_vector) return std_logic_vector is
variable bb : std_logic_vector(aa'high downto aa'low);
begin
for i in aa'high downto aa'low loop
bb(i) := aa(aa'high-i);
end loop;
return bb;
end function reverse_bit;
type lookup_type is array (0 to ((G_W/8)*2-1)) of std_logic_vector(G_W/8-1 downto 0);
function getVbytesLookup(size: integer) return lookup_type is
variable ret : lookup_type;
begin
for i in 0 to ((size/8)*2-1) loop
if (i >= (size/8)) then
ret(i) := (others => '1');
elsif (i = 0) then
ret(i) := (others => '0');
else
ret(i)(size/8-1 downto size/8-i) := (others => '1');
ret(i)(size/8-i-1 downto 0) := (others => '0');
end if;
end loop;
return ret;
end function getVbytesLookup;
constant VBYTES_LOOKUP : lookup_type := getVbytesLookup(G_W);
--! ==================
--! Note: Current unused (keep this portion for later consideration)
function getPlocLookup(size: integer) return lookup_type is
variable ret : lookup_type;
begin
for i in 0 to ((size/8)*2-1) loop
if (i >= (size/8)) then
ret(i) := (others => '0');
else
ret(i) := (i => '1', others => '0');
end if;
end loop;
return ret;
end function getPlocLookup;
constant PLOC_LOOKUP : lookup_type := getPlocLookup(G_W);
--! End of note
--! ==================
--! Key related signals and registers
signal reg_key : std_logic_vector(G_KEY_SIZE -1 downto 0);
signal reg_rdkey : std_logic_vector(G_RDKEY_SIZE -1 downto 0);
--! Public data signals and registers
signal reg_data : std_logic_vector(G_DBLK_SIZE -1 downto 0); --! Data block register
signal reg_exp_tag : std_logic_vector(G_TAG_SIZE -1 downto 0); --! Tag register
signal reg_vbytes : std_logic_vector(G_DBLK_SIZE/8 -1 downto 0); --! Valid bytes register
signal reg_ploc : std_logic_vector(G_DBLK_SIZE/8 -1 downto 0); --! Pad location register
signal p_size : std_logic_vector(CNTR_WIDTH -1 downto 0); --! Public data segment size
signal p_zpad_di : std_logic_vector(G_W -1 downto 0); --! Internally selected signal for padding
signal p_1pad_di : std_logic_vector(G_W -1 downto 0); --! Internally selected signal for padding
signal input_data : std_logic_vector(G_W -1 downto 0); --! Additional select signal for padding
signal input_vbytes : std_logic_vector(G_W/8 -1 downto 0); --! Additional select signal for bytes size
signal input_ploc : std_logic_vector(G_W/8 -1 downto 0); --! Additional select signal for bytes size
--! Data block status register for external modules
signal len_a_reg : std_logic_vector(LEN_A_WIDTH -1 downto 0); --! Total authenticated data register
signal len_d_reg : std_logic_vector(LEN_D_WIDTH -1 downto 0); --! Total message data register --! Current block contains no message data (used for authenticated encryption data only mode)
--! Padding related signals
signal pad_loc_r : std_logic_vector(G_W/8 -1 downto 0);
--! Lookups
signal vbytes : std_logic_vector(G_W/8 -1 downto 0);
signal ploc : std_logic_vector(G_W/8 -1 downto 0);
begin
p_zpad_di <= pdi when sel_blank_pdi = '0' else (others => '0');
vbytes <= VBYTES_LOOKUP(conv_integer(size_dword));
ploc <= PLOC_LOOKUP(conv_integer(size_dword));
--! Datapath
procReg:
process( clk )
begin
if rising_edge( clk ) then
if rst = '1' then
reg_data <= (others => '0');
reg_exp_tag <= (others => '0');
len_a_reg <= (others => '0');
len_d_reg <= (others => '0');
reg_vbytes <= (others => '0');
else
--! === Public data
--! Data SIPO
if (en_data = '1') then
--! Handle different block size
if (G_W >= G_DBLK_SIZE) then
reg_data <= p_1pad_di(G_W-1 downto G_W-G_DBLK_SIZE);
reg_vbytes <= vbytes(G_W/8-1 downto G_W/8-G_DBLK_SIZE/8);
elsif ((G_DBLK_SIZE MOD G_W) = 0) then
reg_data <= reg_data(G_DBLK_SIZE-G_W-1 downto 0) & p_1pad_di;
reg_vbytes <= reg_vbytes(G_DBLK_SIZE/8-G_W/8-1 downto 0) & vbytes;
elsif ((G_DBLK_SIZE MOD G_W) /= 0) then
if (en_last_word = '0') then
reg_data (G_DBLK_SIZE-1 downto ( G_DBLK_SIZE MOD G_W)) <= reg_data (G_DBLK_SIZE- G_W -1 downto ( G_DBLK_SIZE MOD G_W)) & input_data;
reg_vbytes(G_DBLK_SIZE/8-1 downto ((G_DBLK_SIZE/8) MOD (G_W/8))) <= reg_vbytes(G_DBLK_SIZE/8-G_W/8-1 downto ((G_DBLK_SIZE/8) MOD (G_W/8))) & input_vbytes;
else
reg_data ((G_DBLK_SIZE mod G_W )-1 downto 0) <= input_data (G_W -1 downto G_W /2);
reg_vbytes(((G_DBLK_SIZE/8) mod (G_W/8))-1 downto 0) <= input_vbytes(G_W/8-1 downto (G_W/8)/2);
end if;
end if;
end if;
--! Tag SIPO
if (en_exp_tag = '1') then
--! Handle different block size
if (G_W >= G_TAG_SIZE) then
reg_exp_tag <= pdi(G_W-1 downto G_W-G_TAG_SIZE);
else
reg_exp_tag <= reg_exp_tag(G_TAG_SIZE-G_W-1 downto 0) & pdi;
end if;
end if;
--! === Secret data
--! Key SIPO
if (en_key = '1') then
--! Handle different I/O and key size
if (G_SW < G_KEY_SIZE) then
reg_key <= reg_key(G_KEY_SIZE-G_SW-1 downto 0) & sdi;
elsif G_SW = G_KEY_SIZE then
reg_key <= sdi;
end if;
end if;
--! Round Key SIPO
if (en_rdkey = '1') then
--! Handle different I/O and key size
if (G_SW < G_RDKEY_SIZE) then
reg_rdkey <= reg_rdkey(G_RDKEY_SIZE-G_SW-1 downto 0) & sdi;
elsif G_SW = G_RDKEY_SIZE then
reg_rdkey <= sdi;
end if;
end if;
--! === Status
--! Length registers
if (clr_len = '1') then
len_a_reg <= (others => '0');
len_d_reg <= (others => '0');
else
if (G_LOADLEN_ENABLE = 0) then
if (en_len_a = '1') then
len_a_reg <= len_a_reg + p_size;
end if;
if (en_len_d = '1') then
len_d_reg <= len_d_reg + p_size;
end if;
else
if (en_len_a_r = '1') then
if (G_W >= LEN_A_WIDTH) then
len_a_reg <= pdi(LEN_A_WIDTH-1 downto 0);
elsif ((LEN_A_WIDTH MOD G_W) = 0) then
len_a_reg <= len_a_reg(LEN_A_WIDTH-G_W-1 downto 0) & pdi;
else
if (en_len_last_r = '0') then
if (LEN_A_WIDTH/G_W > 1) then
len_a_reg(LEN_A_WIDTH-1 downto (LEN_A_WIDTH MOD G_W)) <= len_a_reg(LEN_A_WIDTH-G_W-1 downto (LEN_A_WIDTH MOD G_W)) & pdi;
else
len_a_reg(LEN_A_WIDTH-1 downto (LEN_A_WIDTH MOD G_W)) <= pdi;
end if;
else
len_a_reg((LEN_A_WIDTH MOD G_W)-1 downto 0) <= pdi(G_W-1 downto G_W-(LEN_A_WIDTH MOD G_W));
end if;
end if;
end if;
if (en_len_d_r = '1') then
if (G_W >= LEN_D_WIDTH) then
len_d_reg <= pdi(LEN_D_WIDTH-1 downto 0);
elsif ((LEN_D_WIDTH MOD G_W) = 0) then
len_d_reg <= len_d_reg(LEN_D_WIDTH-G_W-1 downto 0) & pdi;
else
if (en_len_last_r = '0') then
if (LEN_D_WIDTH/G_W > 1) then
len_d_reg(LEN_D_WIDTH-1 downto (LEN_D_WIDTH MOD G_W)) <= len_d_reg(LEN_D_WIDTH-G_W-1 downto (LEN_D_WIDTH MOD G_W)) & pdi;
else
len_d_reg(LEN_D_WIDTH-1 downto (LEN_D_WIDTH MOD G_W)) <= pdi;
end if;
else
len_d_reg((LEN_D_WIDTH MOD G_W)-1 downto 0) <= pdi(G_W-1 downto G_W-(LEN_D_WIDTH MOD G_W));
end if;
end if;
end if;
end if;
end if;
end if;
end if;
end process;
--! Public data size (based on the interface)
p_size <= pdi(CNTR_WIDTH -1 downto 0);
--! Output
len_a <= len_a_reg(G_CTR_AD_SIZE -1 downto 0);
len_d <= len_d_reg(G_CTR_D_SIZE -1 downto 0);
bdi <= reg_data;
exp_tag <= reg_exp_tag;
genKey: if (G_RDKEY_ENABLE = 0) generate
key <= reg_key;
end generate;
genRdKey: if (G_RDKEY_ENABLE = 1) generate
rdkey <= reg_rdkey;
end generate;
bdi_valid_bytes <= reg_vbytes;
bdi_pad_loc <= reg_ploc;
genNpub: if (G_NPUB_DISABLE = 0) generate
signal reg_npub : std_logic_vector(REG_NPUB_WIDTH -1 downto 0); --! Npub register
begin
npub <= reg_npub(REG_NPUB_WIDTH-1 downto REG_NPUB_WIDTH-G_NPUB_SIZE);
procReg:
process( clk )
begin
if rising_edge( clk ) then
if (rst = '1') then
reg_npub <= (others => '0');
elsif (en_npub = '1') then
if (G_W >= G_NPUB_SIZE) then
reg_npub <= pdi(G_W-1 downto G_W-REG_NPUB_WIDTH);
else
reg_npub <= reg_npub(REG_NPUB_WIDTH-G_W-1 downto 0) & pdi;
end if;
end if;
end if;
end process;
end generate;
genNsec: if (G_NSEC_ENABLE = 1) generate
signal reg_nsec : std_logic_vector(G_NSEC_SIZE -1 downto 0); --! Nsec register
begin
nsec <= reg_nsec;
procReg:
process( clk )
begin
if rising_edge( clk ) then
if (en_nsec = '1') then
if (G_W < G_NSEC_SIZE) then
reg_nsec <= reg_nsec(G_NSEC_SIZE-G_W-1 downto 0) & pdi;
else
reg_nsec <= pdi(G_W-1 downto G_W-G_NSEC_SIZE);
end if;
end if;
end if;
end process;
end generate;
--! ============ Special mode ===========
genPartial: if ((G_DBLK_SIZE mod G_W) > 0) generate
constant ZEROS : std_logic_vector(G_W-1 downto 0) := (others => '0');
signal padded_reg : std_logic_vector(G_W/2-1 downto 0);
signal dbytes_reg : std_logic_vector((G_W/8)/2-1 downto 0);
begin
process(clk)
begin
if rising_edge(clk) then
if (en_data = '1' and sel_blank_pdi = '0') then
padded_reg <= p_1pad_di(G_W/2-1 downto 0);
dbytes_reg <= vbytes((G_W/8)/2-1 downto 0);
end if;
end if;
end process;
genKeyak0: if G_KEYAK = 0 generate
with sel_input(2 downto 0) select
input_data <= p_1pad_di when "000",
p_1pad_di(G_W-1 downto G_W-G_W/2) & ZEROS(G_W-1 downto G_W-G_W/2) when "001",
padded_reg & p_1pad_di(G_W-1 downto G_W-G_W/2) when "010",
padded_reg & ZEROS(G_W-1 downto G_W-G_W/2) when "011",
(others => '0') when others;
with sel_input(2 downto 0) select
input_vbytes <= vbytes when "000",
vbytes(G_W/8-1 downto G_W/8-(G_W/8)/2) & ZEROS(G_W/8-1 downto G_W/8-(G_W/8)/2) when "001",
dbytes_reg & vbytes(G_W/8-1 downto G_W/8-(G_W/8)/2) when "010",
dbytes_reg & ZEROS(G_W/8-1 downto G_W/8-(G_W/8)/2) when "011",
(others => '0') when others;
end generate;
--! Special loading for Keyak
genKeyak1: if (G_KEYAK = 1 and G_W = 128 and G_DBLK_SIZE = 1344) generate
signal key_r : std_logic_vector(G_KEY_SIZE-1 downto 0);
begin
pKey: process(clk)
begin
if rising_edge(clk) then
if (key_updated = '1') then
key_r <= reg_key;
end if;
end if;
end process;
with sel_input(2 downto 0) select
input_data <= p_1pad_di when "000",
p_1pad_di(G_W-1 downto G_W-G_W/2) & ZEROS(G_W-1 downto G_W-G_W/2) when "001",
padded_reg & p_1pad_di(G_W-1 downto G_W-G_W/2) when "010",
padded_reg & ZEROS(G_W-1 downto G_W-G_W/2) when "011",
x"1E" & key_r(G_KEY_SIZE-1 downto 8) when "100",
key_r(7 downto 0) & x"01" & x"000000000000000000000000" & x"0100" when "101",
(others => '0') when others;
with sel_input(2 downto 0) select
input_vbytes <= vbytes when "000",
vbytes(G_W/8-1 downto G_W/8-(G_W/8)/2) & ZEROS(G_W/8-1 downto G_W/8-(G_W/8)/2) when "001",
dbytes_reg & vbytes(G_W/8-1 downto G_W/8-(G_W/8)/2) when "010",
dbytes_reg & ZEROS(G_W/8-1 downto G_W/8-(G_W/8)/2) when "011",
(others => '1') when "100",
(others => '1') when "101",
(others => '0') when others;
end generate;
end generate;
--! ============ Padding related logic =================
--! No padding unit
genPad0: if G_PAD = 0 generate
begin
p_1pad_di <= p_zpad_di;
end generate;
--! With padding unit
genPad1: if G_PAD = 1 generate
signal pad_loc_s : std_logic_vector(G_W/8 -1 downto 0);
signal ploc_reg : std_logic_vector((G_W/8)/2 -1 downto 0);
begin
--! No actual padding is performed. However, padding location is produced. Used this mode if bdi_pad_loc signal is required)
genPadMode0:
if G_PAD_STYLE = 0 generate
p_1pad_di <= p_zpad_di;
end generate;
--! Pad 10*
genPadMode1:
if G_PAD_STYLE = 1 generate
genLoop:
for i in 0 to G_W/8-1 generate
p_1pad_di(G_W-i*8-1) <= '1' when (pad_enable = '1' and pad_loc_r(i) = '1' ) else p_zpad_di(G_W-i*8-1);
p_1pad_di(G_W-i*8-2 downto G_W-i*8-8) <= p_zpad_di(G_W-i*8-2 downto G_W-i*8-8);
end generate;
end generate;
--! Padding mode for ICEPOLE
genPadMode2:
if G_PAD_STYLE = 2 generate
genLoop:
for i in 0 to G_W/8-1 generate
p_1pad_di(G_W-i*8-1 downto G_W-i*8-6) <= p_zpad_di(G_W-i*8-1 downto G_W-i*8-6);
p_1pad_di(G_W-i*8-7) <= '1' when (pad_enable = '1' and pad_loc_r(i) = '1' ) else p_zpad_di(G_W-i*8-7);
p_1pad_di(G_W-i*8-8) <= '1' when (pad_enable = '1' and pad_loc_r(i) = '1' and ((pad_eot = '1' and pad_type_ad = '1') or (pad_eot = '0' and pad_type_ad = '0'))) else p_zpad_di(G_W-i*8-8);
end generate;
end generate;
--! Padding mode for Keyak
genPadMode3:
if G_PAD_STYLE = 3 generate
genLoop:
for i in 0 to G_W/8-1 generate
p_1pad_di(G_W-i*8-1) <= p_zpad_di(G_W-i*8-1);
p_1pad_di(G_W-i*8-2) <= p_zpad_di(G_W-i*8-2);
p_1pad_di(G_W-i*8-3) <= p_zpad_di(G_W-i*8-3);
p_1pad_di(G_W-i*8-4) <= p_zpad_di(G_W-i*8-4);
p_1pad_di(G_W-i*8-5) <= p_zpad_di(G_W-i*8-5);
p_1pad_di(G_W-i*8-6) <= '1' when (pad_enable = '1' and pad_loc_r(i) = '1') else p_zpad_di(G_W-i*8-6);
p_1pad_di(G_W-i*8-7) <= '1' when (pad_enable = '1' and pad_loc_r(i) = '1' and ((pad_type_ad = '1' and pad_eoi = '0' and pad_eot = '1') or (pad_type_ad = '0' and pad_eot = '0'))) else p_zpad_di(G_W-i*8-7);
p_1pad_di(G_W-i*8-8) <= '1' when (pad_enable = '1' and pad_loc_r(i) = '1' and (pad_type_ad = '0' or (pad_eoi = '1' and pad_type_ad = '1'))) else p_zpad_di(G_W-i*8-8);
end generate;
end generate;
procReg: process(clk)
begin
if rising_edge(clk) then
if en_pad_loc = '1' then
pad_loc_r <= pad_loc_s;
end if;
if G_W >= G_DBLK_SIZE then
if (en_data = '1') then
if (pad_enable = '1') then
reg_ploc <= reverse_bit(pad_loc_r);
else
reg_ploc <= (others => '0');
end if;
end if;
elsif (G_DBLK_SIZE MOD G_W) = 0 then
if (en_data = '1') then
if (pad_enable = '1') then
reg_ploc <= reg_ploc(G_DBLK_SIZE/8-G_W/8-1 downto 0) & reverse_bit(pad_loc_s);
else
reg_ploc <= reg_ploc(G_DBLK_SIZE/8-G_W/8-1 downto 0) & ZWORD_BYTES(G_W/8-1 downto 0);
end if;
end if;
elsif (G_DBLK_SIZE MOD G_W) /= 0 then
if (rst = '1') then
reg_ploc <= (others => '0');
elsif (en_data = '1') then
ploc_reg <= pad_loc_s(((G_W/8)-1) downto ((G_W/8)/2));
if (en_last_word = '0') then
if (pad_enable = '1') then
reg_ploc(G_DBLK_SIZE/8-1 downto ((G_DBLK_SIZE/8) MOD (G_W/8))) <= reg_ploc(G_DBLK_SIZE/8-G_W/8-1 downto ((G_DBLK_SIZE/8) MOD (G_W/8))) & input_ploc;
else
reg_ploc(G_DBLK_SIZE/8-1 downto ((G_DBLK_SIZE/8) MOD (G_W/8))) <= reg_ploc(G_DBLK_SIZE/8-G_W/8-1 downto ((G_DBLK_SIZE/8) MOD (G_W/8))) & ZWORD_BYTES(G_W/8-1 downto 0);
end if;
else
if (pad_enable = '1') then
reg_ploc(((G_DBLK_SIZE/8) mod (G_W/8))-1 downto 0) <= input_ploc(G_W/8-1 downto (G_W/8)/2);
else
reg_ploc(((G_DBLK_SIZE/8) mod (G_W/8))-1 downto 0) <= (others => '0');
end if;
end if;
end if;
end if;
end if;
end process;
gKeyak0:
if ((G_KEYAK = 0) and ((G_DBLK_SIZE MOD G_W) /= 0)) generate
with sel_input(2 downto 0) select
input_ploc <= reverse_bit(pad_loc_s) when "000",
reverse_bit(pad_loc_s)(G_W/8-1 downto (G_W/8)/2) & ZWORD_BYTES(G_W/8-1 downto G_W/8-(G_W/8)/2) when "001",
reverse_bit(ploc_reg) & reverse_bit(pad_loc_s((G_W/8)/2-1 downto 0)) when "010",
reverse_bit(ploc_reg) & ZWORD_BYTES(G_W/8-1 downto G_W/8-(G_W/8)/2) when "011",
(others => '0') when others;
end generate;
gKeyak1:
if (G_KEYAK = 1) generate
with sel_input(2 downto 0) select
input_ploc <= reverse_bit(pad_loc_s) when "000",
reverse_bit(pad_loc_s)(G_W/8-1 downto (G_W/8)/2) & ZWORD_BYTES(G_W/8-1 downto G_W/8-(G_W/8)/2) when "001",
reverse_bit(ploc_reg) & reverse_bit(pad_loc_s((G_W/8)/2-1 downto 0)) when "010",
reverse_bit(ploc_reg) & ZWORD_BYTES(G_W/8-1 downto G_W/8-(G_W/8)/2) when "011",
(others => '0') when others;
-- with sel_input(2 downto 0) select
-- input_ploc <= reverse_bit(pad_loc_s) when "000",
-- reverse_bit(ploc_reg) & reverse_bit(pad_loc_s((G_W/8)/2-1 downto 0)) when "001",
-- reverse_bit(ploc_reg) & ZWORD_BYTES(G_W/8-1 downto G_W/8-(G_W/8)/2) when "010",
-- (others => '0') when others;
end generate;
--! Calculate the padding locatin
uBarrelShifter:
entity work.bshift(struct)
generic map (G_W => G_W/8, G_LOG2_W => LOG2_W, G_LEFT => 1, G_ROTATE => 0)
port map (ii => BSHIFT_INPUT, rtr => pad_shift, oo => pad_loc_s);
end generate;
end dataflow;
|
-------------------------------------------------------------------------------
--! @file PreProcessor_Datapath.vhd
--! @brief Datapath for the pre-processor
--! @project CAESAR Candidate Evaluation
--! @author Ekawat (ice) Homsirikamol
--! @copyright Copyright (c) 2015 Cryptographic Engineering Research Group
--! ECE Department, George Mason University Fairfax, VA, U.S.A.
--! All rights Reserved.
--! @license This project is released under the GNU Public License.
--! The license and distribution terms for this file may be
--! found in the file LICENSE in this distribution or at
--! http://www.gnu.org/licenses/gpl-3.0.txt
--! @note This is publicly available encryption source code that falls
--! under the License Exception TSU (Technology and software-
--! —unrestricted)
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use work.AEAD_pkg.all;
entity PreProcessor_Datapath is
generic (
G_W : integer := 64; --! Public data width (bits)
G_SW : integer := 64; --! Secret data width (bits)
G_CTR_AD_SIZE : integer := 64; --! Maximum size for the counter that keeps track of authenticated data
G_CTR_D_SIZE : integer := 64; --! Maximum size for the counter that keeps track of data
G_DBLK_SIZE : integer := 128; --! Block size (bits)
G_KEY_SIZE : integer := 128; --! Key size (bits)
G_KEYAK : integer := 0; --! Special input mode, used only for Keyak with G_W = 128 and G_DBLK_SIZE = 1344
G_NPUB_DISABLE : integer := 0; --! Disable Npub related port(s)
G_NPUB_SIZE : integer := 128; --! Npub width (bits)
G_NSEC_ENABLE : integer := 0; --! Enable nsec port
G_NSEC_SIZE : integer := 128; --! Nsec width (bits)
G_LOADLEN_ENABLE : integer := 0; --! Enable load length section
G_PAD : integer := 0; --! Enable padding
G_PAD_STYLE : integer := 1; --! Padding mode 0 = *10..., 1 = ICEPOLE's padding
G_RDKEY_ENABLE : integer := 0; --! Enable rdkey port (also disables key port)
G_RDKEY_SIZE : integer := 128; --! Roundkey size (bits)
G_TAG_SIZE : integer := 128 --! Tag size (bits)
);
port (
--! =================
--! External Signals
--! =================
--! Global signals
clk : in std_logic;
rst : in std_logic;
pdi : in std_logic_vector(G_W -1 downto 0); --! Public data
sdi : in std_logic_vector(G_SW -1 downto 0); --! Secret data
--! =================
--! Crypto Core Signals
--! =================
key : out std_logic_vector(G_KEY_SIZE -1 downto 0); --! Key data
rdkey : out std_logic_vector(G_RDKEY_SIZE -1 downto 0); --! Round key data
bdi : out std_logic_vector(G_DBLK_SIZE -1 downto 0); --! Block data
npub : out std_logic_vector(G_NPUB_SIZE -1 downto 0); --! Npub data
nsec : out std_logic_vector(G_NSEC_SIZE -1 downto 0); --! Nsec data
exp_tag : out std_logic_vector(G_TAG_SIZE -1 downto 0); --! Expected tag data
bdi_valid_bytes : out std_logic_vector(G_DBLK_SIZE/8 -1 downto 0);
bdi_pad_loc : out std_logic_vector(G_DBLK_SIZE/8 -1 downto 0);
len_a : out std_logic_vector(G_CTR_AD_SIZE -1 downto 0); --! Len of authenticated data in bytes (used for some algorithm)
len_d : out std_logic_vector(G_CTR_D_SIZE -1 downto 0); --! Len of data in bytes (used for some algorithm)
--! =================
--! Internal Signals
--! =================
--! Control signals
key_updated : in std_logic; --! (if G_DBLK_SIZE mod G_W > 0) Key updated signal (used only for situation when key is stored within input processor)
pad_shift : in std_logic_vector(log2_ceil(G_W/8) -1 downto 0);
en_data : in std_logic; --! Shift data SIPO
en_npub : in std_logic; --! Shift Npub SIPO
en_nsec : in std_logic; --! Shift Nsec SIPO
en_key : in std_logic; --! Shift key SIPO
en_rdkey : in std_logic; --! Shift round key SIPO
en_exp_tag : in std_logic; --! Shift expected tag SIPO
sel_blank_pdi : in std_logic; --! Select input data as blank (for filling in the remaining data within a block)
clr_len : in std_logic; --! Clear stored length (len_a and len_d)
en_len_a_r : in std_logic; --! Add authenticated data counter
en_len_d_r : in std_logic; --! Add data counter
en_len_last_r : in std_logic; --! Special signal for en_len_*_r
en_len_a : in std_logic; --! Add authenticated data counter (instant)
en_len_d : in std_logic; --! Add data counter (no)
size_dword : in std_logic_vector(log2_ceil(G_W/8) downto 0); --! Size of data word
en_last_word : in std_logic; --! Last word in a block
pad_eot : in std_logic; --! Padding is EOT
pad_eoi : in std_logic; --! Padding is EOI
pad_type_ad : in std_logic; --! Padding is AD
pad_enable : in std_logic; --! Enable padding signal (indicates that the current word requires padding)
en_pad_loc : in std_logic; --! Save the padding location into a register
sel_input : in std_logic_vector(3 -1 downto 0) --! (if G_DBLK_SIZE mod G_W > 0) Select input for m
);
end PreProcessor_Datapath;
architecture dataflow of PreProcessor_Datapath is
--! Constants declaration
constant LOG2_W : integer := log2_ceil(G_W/8); --! LOG_2(G_W)
constant LOG2_SW : integer := log2_ceil(G_SW/8); --! LOG_2(G_SW)
constant REG_NPUB_WIDTH : integer := (((G_NPUB_SIZE-1)/G_W)+1)*G_W; --! Calculate the width of Npub register
constant CNTR_WIDTH : integer := get_cntr_width(G_W); --! Calculate the length of p_size register
constant LEN_A_WIDTH : integer := maximum(CNTR_WIDTH, G_CTR_AD_SIZE);
constant LEN_D_WIDTH : integer := maximum(CNTR_WIDTH, G_CTR_D_SIZE);
constant CNT_DATA_WORDS : integer := (G_DBLK_SIZE+(G_W-1))/G_W; --! Calculate the number of words required for data (rounded up)
constant CNT_TAG_WORDS : integer := (G_DBLK_SIZE+(G_W-1))/G_W; --! Calculate the number of words required for tag (rounded up)
constant BSHIFT_INPUT : std_logic_vector(G_W/8 -1 downto 0) := std_logic_vector(to_unsigned(1,G_W/8));
constant OWORD_BYTES : std_logic_vector(G_DBLK_SIZE/8 -1 downto 0) := (others => '1'); --! The number of bytes in a word in ones.
constant ZWORD_BYTES : std_logic_vector(G_DBLK_SIZE/8 -1 downto 0) := (others => '0'); --! The number of bytes in a word in zeros.
function reverse_bit(aa: std_logic_vector) return std_logic_vector is
variable bb : std_logic_vector(aa'high downto aa'low);
begin
for i in aa'high downto aa'low loop
bb(i) := aa(aa'high-i);
end loop;
return bb;
end function reverse_bit;
type lookup_type is array (0 to ((G_W/8)*2-1)) of std_logic_vector(G_W/8-1 downto 0);
function getVbytesLookup(size: integer) return lookup_type is
variable ret : lookup_type;
begin
for i in 0 to ((size/8)*2-1) loop
if (i >= (size/8)) then
ret(i) := (others => '1');
elsif (i = 0) then
ret(i) := (others => '0');
else
ret(i)(size/8-1 downto size/8-i) := (others => '1');
ret(i)(size/8-i-1 downto 0) := (others => '0');
end if;
end loop;
return ret;
end function getVbytesLookup;
constant VBYTES_LOOKUP : lookup_type := getVbytesLookup(G_W);
--! ==================
--! Note: Current unused (keep this portion for later consideration)
function getPlocLookup(size: integer) return lookup_type is
variable ret : lookup_type;
begin
for i in 0 to ((size/8)*2-1) loop
if (i >= (size/8)) then
ret(i) := (others => '0');
else
ret(i) := (i => '1', others => '0');
end if;
end loop;
return ret;
end function getPlocLookup;
constant PLOC_LOOKUP : lookup_type := getPlocLookup(G_W);
--! End of note
--! ==================
--! Key related signals and registers
signal reg_key : std_logic_vector(G_KEY_SIZE -1 downto 0);
signal reg_rdkey : std_logic_vector(G_RDKEY_SIZE -1 downto 0);
--! Public data signals and registers
signal reg_data : std_logic_vector(G_DBLK_SIZE -1 downto 0); --! Data block register
signal reg_exp_tag : std_logic_vector(G_TAG_SIZE -1 downto 0); --! Tag register
signal reg_vbytes : std_logic_vector(G_DBLK_SIZE/8 -1 downto 0); --! Valid bytes register
signal reg_ploc : std_logic_vector(G_DBLK_SIZE/8 -1 downto 0); --! Pad location register
signal p_size : std_logic_vector(CNTR_WIDTH -1 downto 0); --! Public data segment size
signal p_zpad_di : std_logic_vector(G_W -1 downto 0); --! Internally selected signal for padding
signal p_1pad_di : std_logic_vector(G_W -1 downto 0); --! Internally selected signal for padding
signal input_data : std_logic_vector(G_W -1 downto 0); --! Additional select signal for padding
signal input_vbytes : std_logic_vector(G_W/8 -1 downto 0); --! Additional select signal for bytes size
signal input_ploc : std_logic_vector(G_W/8 -1 downto 0); --! Additional select signal for bytes size
--! Data block status register for external modules
signal len_a_reg : std_logic_vector(LEN_A_WIDTH -1 downto 0); --! Total authenticated data register
signal len_d_reg : std_logic_vector(LEN_D_WIDTH -1 downto 0); --! Total message data register --! Current block contains no message data (used for authenticated encryption data only mode)
--! Padding related signals
signal pad_loc_r : std_logic_vector(G_W/8 -1 downto 0);
--! Lookups
signal vbytes : std_logic_vector(G_W/8 -1 downto 0);
signal ploc : std_logic_vector(G_W/8 -1 downto 0);
begin
p_zpad_di <= pdi when sel_blank_pdi = '0' else (others => '0');
vbytes <= VBYTES_LOOKUP(conv_integer(size_dword));
ploc <= PLOC_LOOKUP(conv_integer(size_dword));
--! Datapath
procReg:
process( clk )
begin
if rising_edge( clk ) then
if rst = '1' then
reg_data <= (others => '0');
reg_exp_tag <= (others => '0');
len_a_reg <= (others => '0');
len_d_reg <= (others => '0');
reg_vbytes <= (others => '0');
else
--! === Public data
--! Data SIPO
if (en_data = '1') then
--! Handle different block size
if (G_W >= G_DBLK_SIZE) then
reg_data <= p_1pad_di(G_W-1 downto G_W-G_DBLK_SIZE);
reg_vbytes <= vbytes(G_W/8-1 downto G_W/8-G_DBLK_SIZE/8);
elsif ((G_DBLK_SIZE MOD G_W) = 0) then
reg_data <= reg_data(G_DBLK_SIZE-G_W-1 downto 0) & p_1pad_di;
reg_vbytes <= reg_vbytes(G_DBLK_SIZE/8-G_W/8-1 downto 0) & vbytes;
elsif ((G_DBLK_SIZE MOD G_W) /= 0) then
if (en_last_word = '0') then
reg_data (G_DBLK_SIZE-1 downto ( G_DBLK_SIZE MOD G_W)) <= reg_data (G_DBLK_SIZE- G_W -1 downto ( G_DBLK_SIZE MOD G_W)) & input_data;
reg_vbytes(G_DBLK_SIZE/8-1 downto ((G_DBLK_SIZE/8) MOD (G_W/8))) <= reg_vbytes(G_DBLK_SIZE/8-G_W/8-1 downto ((G_DBLK_SIZE/8) MOD (G_W/8))) & input_vbytes;
else
reg_data ((G_DBLK_SIZE mod G_W )-1 downto 0) <= input_data (G_W -1 downto G_W /2);
reg_vbytes(((G_DBLK_SIZE/8) mod (G_W/8))-1 downto 0) <= input_vbytes(G_W/8-1 downto (G_W/8)/2);
end if;
end if;
end if;
--! Tag SIPO
if (en_exp_tag = '1') then
--! Handle different block size
if (G_W >= G_TAG_SIZE) then
reg_exp_tag <= pdi(G_W-1 downto G_W-G_TAG_SIZE);
else
reg_exp_tag <= reg_exp_tag(G_TAG_SIZE-G_W-1 downto 0) & pdi;
end if;
end if;
--! === Secret data
--! Key SIPO
if (en_key = '1') then
--! Handle different I/O and key size
if (G_SW < G_KEY_SIZE) then
reg_key <= reg_key(G_KEY_SIZE-G_SW-1 downto 0) & sdi;
elsif G_SW = G_KEY_SIZE then
reg_key <= sdi;
end if;
end if;
--! Round Key SIPO
if (en_rdkey = '1') then
--! Handle different I/O and key size
if (G_SW < G_RDKEY_SIZE) then
reg_rdkey <= reg_rdkey(G_RDKEY_SIZE-G_SW-1 downto 0) & sdi;
elsif G_SW = G_RDKEY_SIZE then
reg_rdkey <= sdi;
end if;
end if;
--! === Status
--! Length registers
if (clr_len = '1') then
len_a_reg <= (others => '0');
len_d_reg <= (others => '0');
else
if (G_LOADLEN_ENABLE = 0) then
if (en_len_a = '1') then
len_a_reg <= len_a_reg + p_size;
end if;
if (en_len_d = '1') then
len_d_reg <= len_d_reg + p_size;
end if;
else
if (en_len_a_r = '1') then
if (G_W >= LEN_A_WIDTH) then
len_a_reg <= pdi(LEN_A_WIDTH-1 downto 0);
elsif ((LEN_A_WIDTH MOD G_W) = 0) then
len_a_reg <= len_a_reg(LEN_A_WIDTH-G_W-1 downto 0) & pdi;
else
if (en_len_last_r = '0') then
if (LEN_A_WIDTH/G_W > 1) then
len_a_reg(LEN_A_WIDTH-1 downto (LEN_A_WIDTH MOD G_W)) <= len_a_reg(LEN_A_WIDTH-G_W-1 downto (LEN_A_WIDTH MOD G_W)) & pdi;
else
len_a_reg(LEN_A_WIDTH-1 downto (LEN_A_WIDTH MOD G_W)) <= pdi;
end if;
else
len_a_reg((LEN_A_WIDTH MOD G_W)-1 downto 0) <= pdi(G_W-1 downto G_W-(LEN_A_WIDTH MOD G_W));
end if;
end if;
end if;
if (en_len_d_r = '1') then
if (G_W >= LEN_D_WIDTH) then
len_d_reg <= pdi(LEN_D_WIDTH-1 downto 0);
elsif ((LEN_D_WIDTH MOD G_W) = 0) then
len_d_reg <= len_d_reg(LEN_D_WIDTH-G_W-1 downto 0) & pdi;
else
if (en_len_last_r = '0') then
if (LEN_D_WIDTH/G_W > 1) then
len_d_reg(LEN_D_WIDTH-1 downto (LEN_D_WIDTH MOD G_W)) <= len_d_reg(LEN_D_WIDTH-G_W-1 downto (LEN_D_WIDTH MOD G_W)) & pdi;
else
len_d_reg(LEN_D_WIDTH-1 downto (LEN_D_WIDTH MOD G_W)) <= pdi;
end if;
else
len_d_reg((LEN_D_WIDTH MOD G_W)-1 downto 0) <= pdi(G_W-1 downto G_W-(LEN_D_WIDTH MOD G_W));
end if;
end if;
end if;
end if;
end if;
end if;
end if;
end process;
--! Public data size (based on the interface)
p_size <= pdi(CNTR_WIDTH -1 downto 0);
--! Output
len_a <= len_a_reg(G_CTR_AD_SIZE -1 downto 0);
len_d <= len_d_reg(G_CTR_D_SIZE -1 downto 0);
bdi <= reg_data;
exp_tag <= reg_exp_tag;
genKey: if (G_RDKEY_ENABLE = 0) generate
key <= reg_key;
end generate;
genRdKey: if (G_RDKEY_ENABLE = 1) generate
rdkey <= reg_rdkey;
end generate;
bdi_valid_bytes <= reg_vbytes;
bdi_pad_loc <= reg_ploc;
genNpub: if (G_NPUB_DISABLE = 0) generate
signal reg_npub : std_logic_vector(REG_NPUB_WIDTH -1 downto 0); --! Npub register
begin
npub <= reg_npub(REG_NPUB_WIDTH-1 downto REG_NPUB_WIDTH-G_NPUB_SIZE);
procReg:
process( clk )
begin
if rising_edge( clk ) then
if (rst = '1') then
reg_npub <= (others => '0');
elsif (en_npub = '1') then
if (G_W >= G_NPUB_SIZE) then
reg_npub <= pdi(G_W-1 downto G_W-REG_NPUB_WIDTH);
else
reg_npub <= reg_npub(REG_NPUB_WIDTH-G_W-1 downto 0) & pdi;
end if;
end if;
end if;
end process;
end generate;
genNsec: if (G_NSEC_ENABLE = 1) generate
signal reg_nsec : std_logic_vector(G_NSEC_SIZE -1 downto 0); --! Nsec register
begin
nsec <= reg_nsec;
procReg:
process( clk )
begin
if rising_edge( clk ) then
if (en_nsec = '1') then
if (G_W < G_NSEC_SIZE) then
reg_nsec <= reg_nsec(G_NSEC_SIZE-G_W-1 downto 0) & pdi;
else
reg_nsec <= pdi(G_W-1 downto G_W-G_NSEC_SIZE);
end if;
end if;
end if;
end process;
end generate;
--! ============ Special mode ===========
genPartial: if ((G_DBLK_SIZE mod G_W) > 0) generate
constant ZEROS : std_logic_vector(G_W-1 downto 0) := (others => '0');
signal padded_reg : std_logic_vector(G_W/2-1 downto 0);
signal dbytes_reg : std_logic_vector((G_W/8)/2-1 downto 0);
begin
process(clk)
begin
if rising_edge(clk) then
if (en_data = '1' and sel_blank_pdi = '0') then
padded_reg <= p_1pad_di(G_W/2-1 downto 0);
dbytes_reg <= vbytes((G_W/8)/2-1 downto 0);
end if;
end if;
end process;
genKeyak0: if G_KEYAK = 0 generate
with sel_input(2 downto 0) select
input_data <= p_1pad_di when "000",
p_1pad_di(G_W-1 downto G_W-G_W/2) & ZEROS(G_W-1 downto G_W-G_W/2) when "001",
padded_reg & p_1pad_di(G_W-1 downto G_W-G_W/2) when "010",
padded_reg & ZEROS(G_W-1 downto G_W-G_W/2) when "011",
(others => '0') when others;
with sel_input(2 downto 0) select
input_vbytes <= vbytes when "000",
vbytes(G_W/8-1 downto G_W/8-(G_W/8)/2) & ZEROS(G_W/8-1 downto G_W/8-(G_W/8)/2) when "001",
dbytes_reg & vbytes(G_W/8-1 downto G_W/8-(G_W/8)/2) when "010",
dbytes_reg & ZEROS(G_W/8-1 downto G_W/8-(G_W/8)/2) when "011",
(others => '0') when others;
end generate;
--! Special loading for Keyak
genKeyak1: if (G_KEYAK = 1 and G_W = 128 and G_DBLK_SIZE = 1344) generate
signal key_r : std_logic_vector(G_KEY_SIZE-1 downto 0);
begin
pKey: process(clk)
begin
if rising_edge(clk) then
if (key_updated = '1') then
key_r <= reg_key;
end if;
end if;
end process;
with sel_input(2 downto 0) select
input_data <= p_1pad_di when "000",
p_1pad_di(G_W-1 downto G_W-G_W/2) & ZEROS(G_W-1 downto G_W-G_W/2) when "001",
padded_reg & p_1pad_di(G_W-1 downto G_W-G_W/2) when "010",
padded_reg & ZEROS(G_W-1 downto G_W-G_W/2) when "011",
x"1E" & key_r(G_KEY_SIZE-1 downto 8) when "100",
key_r(7 downto 0) & x"01" & x"000000000000000000000000" & x"0100" when "101",
(others => '0') when others;
with sel_input(2 downto 0) select
input_vbytes <= vbytes when "000",
vbytes(G_W/8-1 downto G_W/8-(G_W/8)/2) & ZEROS(G_W/8-1 downto G_W/8-(G_W/8)/2) when "001",
dbytes_reg & vbytes(G_W/8-1 downto G_W/8-(G_W/8)/2) when "010",
dbytes_reg & ZEROS(G_W/8-1 downto G_W/8-(G_W/8)/2) when "011",
(others => '1') when "100",
(others => '1') when "101",
(others => '0') when others;
end generate;
end generate;
--! ============ Padding related logic =================
--! No padding unit
genPad0: if G_PAD = 0 generate
begin
p_1pad_di <= p_zpad_di;
end generate;
--! With padding unit
genPad1: if G_PAD = 1 generate
signal pad_loc_s : std_logic_vector(G_W/8 -1 downto 0);
signal ploc_reg : std_logic_vector((G_W/8)/2 -1 downto 0);
begin
--! No actual padding is performed. However, padding location is produced. Used this mode if bdi_pad_loc signal is required)
genPadMode0:
if G_PAD_STYLE = 0 generate
p_1pad_di <= p_zpad_di;
end generate;
--! Pad 10*
genPadMode1:
if G_PAD_STYLE = 1 generate
genLoop:
for i in 0 to G_W/8-1 generate
p_1pad_di(G_W-i*8-1) <= '1' when (pad_enable = '1' and pad_loc_r(i) = '1' ) else p_zpad_di(G_W-i*8-1);
p_1pad_di(G_W-i*8-2 downto G_W-i*8-8) <= p_zpad_di(G_W-i*8-2 downto G_W-i*8-8);
end generate;
end generate;
--! Padding mode for ICEPOLE
genPadMode2:
if G_PAD_STYLE = 2 generate
genLoop:
for i in 0 to G_W/8-1 generate
p_1pad_di(G_W-i*8-1 downto G_W-i*8-6) <= p_zpad_di(G_W-i*8-1 downto G_W-i*8-6);
p_1pad_di(G_W-i*8-7) <= '1' when (pad_enable = '1' and pad_loc_r(i) = '1' ) else p_zpad_di(G_W-i*8-7);
p_1pad_di(G_W-i*8-8) <= '1' when (pad_enable = '1' and pad_loc_r(i) = '1' and ((pad_eot = '1' and pad_type_ad = '1') or (pad_eot = '0' and pad_type_ad = '0'))) else p_zpad_di(G_W-i*8-8);
end generate;
end generate;
--! Padding mode for Keyak
genPadMode3:
if G_PAD_STYLE = 3 generate
genLoop:
for i in 0 to G_W/8-1 generate
p_1pad_di(G_W-i*8-1) <= p_zpad_di(G_W-i*8-1);
p_1pad_di(G_W-i*8-2) <= p_zpad_di(G_W-i*8-2);
p_1pad_di(G_W-i*8-3) <= p_zpad_di(G_W-i*8-3);
p_1pad_di(G_W-i*8-4) <= p_zpad_di(G_W-i*8-4);
p_1pad_di(G_W-i*8-5) <= p_zpad_di(G_W-i*8-5);
p_1pad_di(G_W-i*8-6) <= '1' when (pad_enable = '1' and pad_loc_r(i) = '1') else p_zpad_di(G_W-i*8-6);
p_1pad_di(G_W-i*8-7) <= '1' when (pad_enable = '1' and pad_loc_r(i) = '1' and ((pad_type_ad = '1' and pad_eoi = '0' and pad_eot = '1') or (pad_type_ad = '0' and pad_eot = '0'))) else p_zpad_di(G_W-i*8-7);
p_1pad_di(G_W-i*8-8) <= '1' when (pad_enable = '1' and pad_loc_r(i) = '1' and (pad_type_ad = '0' or (pad_eoi = '1' and pad_type_ad = '1'))) else p_zpad_di(G_W-i*8-8);
end generate;
end generate;
procReg: process(clk)
begin
if rising_edge(clk) then
if en_pad_loc = '1' then
pad_loc_r <= pad_loc_s;
end if;
if G_W >= G_DBLK_SIZE then
if (en_data = '1') then
if (pad_enable = '1') then
reg_ploc <= reverse_bit(pad_loc_r);
else
reg_ploc <= (others => '0');
end if;
end if;
elsif (G_DBLK_SIZE MOD G_W) = 0 then
if (en_data = '1') then
if (pad_enable = '1') then
reg_ploc <= reg_ploc(G_DBLK_SIZE/8-G_W/8-1 downto 0) & reverse_bit(pad_loc_s);
else
reg_ploc <= reg_ploc(G_DBLK_SIZE/8-G_W/8-1 downto 0) & ZWORD_BYTES(G_W/8-1 downto 0);
end if;
end if;
elsif (G_DBLK_SIZE MOD G_W) /= 0 then
if (rst = '1') then
reg_ploc <= (others => '0');
elsif (en_data = '1') then
ploc_reg <= pad_loc_s(((G_W/8)-1) downto ((G_W/8)/2));
if (en_last_word = '0') then
if (pad_enable = '1') then
reg_ploc(G_DBLK_SIZE/8-1 downto ((G_DBLK_SIZE/8) MOD (G_W/8))) <= reg_ploc(G_DBLK_SIZE/8-G_W/8-1 downto ((G_DBLK_SIZE/8) MOD (G_W/8))) & input_ploc;
else
reg_ploc(G_DBLK_SIZE/8-1 downto ((G_DBLK_SIZE/8) MOD (G_W/8))) <= reg_ploc(G_DBLK_SIZE/8-G_W/8-1 downto ((G_DBLK_SIZE/8) MOD (G_W/8))) & ZWORD_BYTES(G_W/8-1 downto 0);
end if;
else
if (pad_enable = '1') then
reg_ploc(((G_DBLK_SIZE/8) mod (G_W/8))-1 downto 0) <= input_ploc(G_W/8-1 downto (G_W/8)/2);
else
reg_ploc(((G_DBLK_SIZE/8) mod (G_W/8))-1 downto 0) <= (others => '0');
end if;
end if;
end if;
end if;
end if;
end process;
gKeyak0:
if ((G_KEYAK = 0) and ((G_DBLK_SIZE MOD G_W) /= 0)) generate
with sel_input(2 downto 0) select
input_ploc <= reverse_bit(pad_loc_s) when "000",
reverse_bit(pad_loc_s)(G_W/8-1 downto (G_W/8)/2) & ZWORD_BYTES(G_W/8-1 downto G_W/8-(G_W/8)/2) when "001",
reverse_bit(ploc_reg) & reverse_bit(pad_loc_s((G_W/8)/2-1 downto 0)) when "010",
reverse_bit(ploc_reg) & ZWORD_BYTES(G_W/8-1 downto G_W/8-(G_W/8)/2) when "011",
(others => '0') when others;
end generate;
gKeyak1:
if (G_KEYAK = 1) generate
with sel_input(2 downto 0) select
input_ploc <= reverse_bit(pad_loc_s) when "000",
reverse_bit(pad_loc_s)(G_W/8-1 downto (G_W/8)/2) & ZWORD_BYTES(G_W/8-1 downto G_W/8-(G_W/8)/2) when "001",
reverse_bit(ploc_reg) & reverse_bit(pad_loc_s((G_W/8)/2-1 downto 0)) when "010",
reverse_bit(ploc_reg) & ZWORD_BYTES(G_W/8-1 downto G_W/8-(G_W/8)/2) when "011",
(others => '0') when others;
-- with sel_input(2 downto 0) select
-- input_ploc <= reverse_bit(pad_loc_s) when "000",
-- reverse_bit(ploc_reg) & reverse_bit(pad_loc_s((G_W/8)/2-1 downto 0)) when "001",
-- reverse_bit(ploc_reg) & ZWORD_BYTES(G_W/8-1 downto G_W/8-(G_W/8)/2) when "010",
-- (others => '0') when others;
end generate;
--! Calculate the padding locatin
uBarrelShifter:
entity work.bshift(struct)
generic map (G_W => G_W/8, G_LOG2_W => LOG2_W, G_LEFT => 1, G_ROTATE => 0)
port map (ii => BSHIFT_INPUT, rtr => pad_shift, oo => pad_loc_s);
end generate;
end dataflow;
|
-------------------------------------------------------------------------------
--! @file PreProcessor_Datapath.vhd
--! @brief Datapath for the pre-processor
--! @project CAESAR Candidate Evaluation
--! @author Ekawat (ice) Homsirikamol
--! @copyright Copyright (c) 2015 Cryptographic Engineering Research Group
--! ECE Department, George Mason University Fairfax, VA, U.S.A.
--! All rights Reserved.
--! @license This project is released under the GNU Public License.
--! The license and distribution terms for this file may be
--! found in the file LICENSE in this distribution or at
--! http://www.gnu.org/licenses/gpl-3.0.txt
--! @note This is publicly available encryption source code that falls
--! under the License Exception TSU (Technology and software-
--! —unrestricted)
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use work.AEAD_pkg.all;
entity PreProcessor_Datapath is
generic (
G_W : integer := 64; --! Public data width (bits)
G_SW : integer := 64; --! Secret data width (bits)
G_CTR_AD_SIZE : integer := 64; --! Maximum size for the counter that keeps track of authenticated data
G_CTR_D_SIZE : integer := 64; --! Maximum size for the counter that keeps track of data
G_DBLK_SIZE : integer := 128; --! Block size (bits)
G_KEY_SIZE : integer := 128; --! Key size (bits)
G_KEYAK : integer := 0; --! Special input mode, used only for Keyak with G_W = 128 and G_DBLK_SIZE = 1344
G_NPUB_DISABLE : integer := 0; --! Disable Npub related port(s)
G_NPUB_SIZE : integer := 128; --! Npub width (bits)
G_NSEC_ENABLE : integer := 0; --! Enable nsec port
G_NSEC_SIZE : integer := 128; --! Nsec width (bits)
G_LOADLEN_ENABLE : integer := 0; --! Enable load length section
G_PAD : integer := 0; --! Enable padding
G_PAD_STYLE : integer := 1; --! Padding mode 0 = *10..., 1 = ICEPOLE's padding
G_RDKEY_ENABLE : integer := 0; --! Enable rdkey port (also disables key port)
G_RDKEY_SIZE : integer := 128; --! Roundkey size (bits)
G_TAG_SIZE : integer := 128 --! Tag size (bits)
);
port (
--! =================
--! External Signals
--! =================
--! Global signals
clk : in std_logic;
rst : in std_logic;
pdi : in std_logic_vector(G_W -1 downto 0); --! Public data
sdi : in std_logic_vector(G_SW -1 downto 0); --! Secret data
--! =================
--! Crypto Core Signals
--! =================
key : out std_logic_vector(G_KEY_SIZE -1 downto 0); --! Key data
rdkey : out std_logic_vector(G_RDKEY_SIZE -1 downto 0); --! Round key data
bdi : out std_logic_vector(G_DBLK_SIZE -1 downto 0); --! Block data
npub : out std_logic_vector(G_NPUB_SIZE -1 downto 0); --! Npub data
nsec : out std_logic_vector(G_NSEC_SIZE -1 downto 0); --! Nsec data
exp_tag : out std_logic_vector(G_TAG_SIZE -1 downto 0); --! Expected tag data
bdi_valid_bytes : out std_logic_vector(G_DBLK_SIZE/8 -1 downto 0);
bdi_pad_loc : out std_logic_vector(G_DBLK_SIZE/8 -1 downto 0);
len_a : out std_logic_vector(G_CTR_AD_SIZE -1 downto 0); --! Len of authenticated data in bytes (used for some algorithm)
len_d : out std_logic_vector(G_CTR_D_SIZE -1 downto 0); --! Len of data in bytes (used for some algorithm)
--! =================
--! Internal Signals
--! =================
--! Control signals
key_updated : in std_logic; --! (if G_DBLK_SIZE mod G_W > 0) Key updated signal (used only for situation when key is stored within input processor)
pad_shift : in std_logic_vector(log2_ceil(G_W/8) -1 downto 0);
en_data : in std_logic; --! Shift data SIPO
en_npub : in std_logic; --! Shift Npub SIPO
en_nsec : in std_logic; --! Shift Nsec SIPO
en_key : in std_logic; --! Shift key SIPO
en_rdkey : in std_logic; --! Shift round key SIPO
en_exp_tag : in std_logic; --! Shift expected tag SIPO
sel_blank_pdi : in std_logic; --! Select input data as blank (for filling in the remaining data within a block)
clr_len : in std_logic; --! Clear stored length (len_a and len_d)
en_len_a_r : in std_logic; --! Add authenticated data counter
en_len_d_r : in std_logic; --! Add data counter
en_len_last_r : in std_logic; --! Special signal for en_len_*_r
en_len_a : in std_logic; --! Add authenticated data counter (instant)
en_len_d : in std_logic; --! Add data counter (no)
size_dword : in std_logic_vector(log2_ceil(G_W/8) downto 0); --! Size of data word
en_last_word : in std_logic; --! Last word in a block
pad_eot : in std_logic; --! Padding is EOT
pad_eoi : in std_logic; --! Padding is EOI
pad_type_ad : in std_logic; --! Padding is AD
pad_enable : in std_logic; --! Enable padding signal (indicates that the current word requires padding)
en_pad_loc : in std_logic; --! Save the padding location into a register
sel_input : in std_logic_vector(3 -1 downto 0) --! (if G_DBLK_SIZE mod G_W > 0) Select input for m
);
end PreProcessor_Datapath;
architecture dataflow of PreProcessor_Datapath is
--! Constants declaration
constant LOG2_W : integer := log2_ceil(G_W/8); --! LOG_2(G_W)
constant LOG2_SW : integer := log2_ceil(G_SW/8); --! LOG_2(G_SW)
constant REG_NPUB_WIDTH : integer := (((G_NPUB_SIZE-1)/G_W)+1)*G_W; --! Calculate the width of Npub register
constant CNTR_WIDTH : integer := get_cntr_width(G_W); --! Calculate the length of p_size register
constant LEN_A_WIDTH : integer := maximum(CNTR_WIDTH, G_CTR_AD_SIZE);
constant LEN_D_WIDTH : integer := maximum(CNTR_WIDTH, G_CTR_D_SIZE);
constant CNT_DATA_WORDS : integer := (G_DBLK_SIZE+(G_W-1))/G_W; --! Calculate the number of words required for data (rounded up)
constant CNT_TAG_WORDS : integer := (G_DBLK_SIZE+(G_W-1))/G_W; --! Calculate the number of words required for tag (rounded up)
constant BSHIFT_INPUT : std_logic_vector(G_W/8 -1 downto 0) := std_logic_vector(to_unsigned(1,G_W/8));
constant OWORD_BYTES : std_logic_vector(G_DBLK_SIZE/8 -1 downto 0) := (others => '1'); --! The number of bytes in a word in ones.
constant ZWORD_BYTES : std_logic_vector(G_DBLK_SIZE/8 -1 downto 0) := (others => '0'); --! The number of bytes in a word in zeros.
function reverse_bit(aa: std_logic_vector) return std_logic_vector is
variable bb : std_logic_vector(aa'high downto aa'low);
begin
for i in aa'high downto aa'low loop
bb(i) := aa(aa'high-i);
end loop;
return bb;
end function reverse_bit;
type lookup_type is array (0 to ((G_W/8)*2-1)) of std_logic_vector(G_W/8-1 downto 0);
function getVbytesLookup(size: integer) return lookup_type is
variable ret : lookup_type;
begin
for i in 0 to ((size/8)*2-1) loop
if (i >= (size/8)) then
ret(i) := (others => '1');
elsif (i = 0) then
ret(i) := (others => '0');
else
ret(i)(size/8-1 downto size/8-i) := (others => '1');
ret(i)(size/8-i-1 downto 0) := (others => '0');
end if;
end loop;
return ret;
end function getVbytesLookup;
constant VBYTES_LOOKUP : lookup_type := getVbytesLookup(G_W);
--! ==================
--! Note: Current unused (keep this portion for later consideration)
function getPlocLookup(size: integer) return lookup_type is
variable ret : lookup_type;
begin
for i in 0 to ((size/8)*2-1) loop
if (i >= (size/8)) then
ret(i) := (others => '0');
else
ret(i) := (i => '1', others => '0');
end if;
end loop;
return ret;
end function getPlocLookup;
constant PLOC_LOOKUP : lookup_type := getPlocLookup(G_W);
--! End of note
--! ==================
--! Key related signals and registers
signal reg_key : std_logic_vector(G_KEY_SIZE -1 downto 0);
signal reg_rdkey : std_logic_vector(G_RDKEY_SIZE -1 downto 0);
--! Public data signals and registers
signal reg_data : std_logic_vector(G_DBLK_SIZE -1 downto 0); --! Data block register
signal reg_exp_tag : std_logic_vector(G_TAG_SIZE -1 downto 0); --! Tag register
signal reg_vbytes : std_logic_vector(G_DBLK_SIZE/8 -1 downto 0); --! Valid bytes register
signal reg_ploc : std_logic_vector(G_DBLK_SIZE/8 -1 downto 0); --! Pad location register
signal p_size : std_logic_vector(CNTR_WIDTH -1 downto 0); --! Public data segment size
signal p_zpad_di : std_logic_vector(G_W -1 downto 0); --! Internally selected signal for padding
signal p_1pad_di : std_logic_vector(G_W -1 downto 0); --! Internally selected signal for padding
signal input_data : std_logic_vector(G_W -1 downto 0); --! Additional select signal for padding
signal input_vbytes : std_logic_vector(G_W/8 -1 downto 0); --! Additional select signal for bytes size
signal input_ploc : std_logic_vector(G_W/8 -1 downto 0); --! Additional select signal for bytes size
--! Data block status register for external modules
signal len_a_reg : std_logic_vector(LEN_A_WIDTH -1 downto 0); --! Total authenticated data register
signal len_d_reg : std_logic_vector(LEN_D_WIDTH -1 downto 0); --! Total message data register --! Current block contains no message data (used for authenticated encryption data only mode)
--! Padding related signals
signal pad_loc_r : std_logic_vector(G_W/8 -1 downto 0);
--! Lookups
signal vbytes : std_logic_vector(G_W/8 -1 downto 0);
signal ploc : std_logic_vector(G_W/8 -1 downto 0);
begin
p_zpad_di <= pdi when sel_blank_pdi = '0' else (others => '0');
vbytes <= VBYTES_LOOKUP(conv_integer(size_dword));
ploc <= PLOC_LOOKUP(conv_integer(size_dword));
--! Datapath
procReg:
process( clk )
begin
if rising_edge( clk ) then
if rst = '1' then
reg_data <= (others => '0');
reg_exp_tag <= (others => '0');
len_a_reg <= (others => '0');
len_d_reg <= (others => '0');
reg_vbytes <= (others => '0');
else
--! === Public data
--! Data SIPO
if (en_data = '1') then
--! Handle different block size
if (G_W >= G_DBLK_SIZE) then
reg_data <= p_1pad_di(G_W-1 downto G_W-G_DBLK_SIZE);
reg_vbytes <= vbytes(G_W/8-1 downto G_W/8-G_DBLK_SIZE/8);
elsif ((G_DBLK_SIZE MOD G_W) = 0) then
reg_data <= reg_data(G_DBLK_SIZE-G_W-1 downto 0) & p_1pad_di;
reg_vbytes <= reg_vbytes(G_DBLK_SIZE/8-G_W/8-1 downto 0) & vbytes;
elsif ((G_DBLK_SIZE MOD G_W) /= 0) then
if (en_last_word = '0') then
reg_data (G_DBLK_SIZE-1 downto ( G_DBLK_SIZE MOD G_W)) <= reg_data (G_DBLK_SIZE- G_W -1 downto ( G_DBLK_SIZE MOD G_W)) & input_data;
reg_vbytes(G_DBLK_SIZE/8-1 downto ((G_DBLK_SIZE/8) MOD (G_W/8))) <= reg_vbytes(G_DBLK_SIZE/8-G_W/8-1 downto ((G_DBLK_SIZE/8) MOD (G_W/8))) & input_vbytes;
else
reg_data ((G_DBLK_SIZE mod G_W )-1 downto 0) <= input_data (G_W -1 downto G_W /2);
reg_vbytes(((G_DBLK_SIZE/8) mod (G_W/8))-1 downto 0) <= input_vbytes(G_W/8-1 downto (G_W/8)/2);
end if;
end if;
end if;
--! Tag SIPO
if (en_exp_tag = '1') then
--! Handle different block size
if (G_W >= G_TAG_SIZE) then
reg_exp_tag <= pdi(G_W-1 downto G_W-G_TAG_SIZE);
else
reg_exp_tag <= reg_exp_tag(G_TAG_SIZE-G_W-1 downto 0) & pdi;
end if;
end if;
--! === Secret data
--! Key SIPO
if (en_key = '1') then
--! Handle different I/O and key size
if (G_SW < G_KEY_SIZE) then
reg_key <= reg_key(G_KEY_SIZE-G_SW-1 downto 0) & sdi;
elsif G_SW = G_KEY_SIZE then
reg_key <= sdi;
end if;
end if;
--! Round Key SIPO
if (en_rdkey = '1') then
--! Handle different I/O and key size
if (G_SW < G_RDKEY_SIZE) then
reg_rdkey <= reg_rdkey(G_RDKEY_SIZE-G_SW-1 downto 0) & sdi;
elsif G_SW = G_RDKEY_SIZE then
reg_rdkey <= sdi;
end if;
end if;
--! === Status
--! Length registers
if (clr_len = '1') then
len_a_reg <= (others => '0');
len_d_reg <= (others => '0');
else
if (G_LOADLEN_ENABLE = 0) then
if (en_len_a = '1') then
len_a_reg <= len_a_reg + p_size;
end if;
if (en_len_d = '1') then
len_d_reg <= len_d_reg + p_size;
end if;
else
if (en_len_a_r = '1') then
if (G_W >= LEN_A_WIDTH) then
len_a_reg <= pdi(LEN_A_WIDTH-1 downto 0);
elsif ((LEN_A_WIDTH MOD G_W) = 0) then
len_a_reg <= len_a_reg(LEN_A_WIDTH-G_W-1 downto 0) & pdi;
else
if (en_len_last_r = '0') then
if (LEN_A_WIDTH/G_W > 1) then
len_a_reg(LEN_A_WIDTH-1 downto (LEN_A_WIDTH MOD G_W)) <= len_a_reg(LEN_A_WIDTH-G_W-1 downto (LEN_A_WIDTH MOD G_W)) & pdi;
else
len_a_reg(LEN_A_WIDTH-1 downto (LEN_A_WIDTH MOD G_W)) <= pdi;
end if;
else
len_a_reg((LEN_A_WIDTH MOD G_W)-1 downto 0) <= pdi(G_W-1 downto G_W-(LEN_A_WIDTH MOD G_W));
end if;
end if;
end if;
if (en_len_d_r = '1') then
if (G_W >= LEN_D_WIDTH) then
len_d_reg <= pdi(LEN_D_WIDTH-1 downto 0);
elsif ((LEN_D_WIDTH MOD G_W) = 0) then
len_d_reg <= len_d_reg(LEN_D_WIDTH-G_W-1 downto 0) & pdi;
else
if (en_len_last_r = '0') then
if (LEN_D_WIDTH/G_W > 1) then
len_d_reg(LEN_D_WIDTH-1 downto (LEN_D_WIDTH MOD G_W)) <= len_d_reg(LEN_D_WIDTH-G_W-1 downto (LEN_D_WIDTH MOD G_W)) & pdi;
else
len_d_reg(LEN_D_WIDTH-1 downto (LEN_D_WIDTH MOD G_W)) <= pdi;
end if;
else
len_d_reg((LEN_D_WIDTH MOD G_W)-1 downto 0) <= pdi(G_W-1 downto G_W-(LEN_D_WIDTH MOD G_W));
end if;
end if;
end if;
end if;
end if;
end if;
end if;
end process;
--! Public data size (based on the interface)
p_size <= pdi(CNTR_WIDTH -1 downto 0);
--! Output
len_a <= len_a_reg(G_CTR_AD_SIZE -1 downto 0);
len_d <= len_d_reg(G_CTR_D_SIZE -1 downto 0);
bdi <= reg_data;
exp_tag <= reg_exp_tag;
genKey: if (G_RDKEY_ENABLE = 0) generate
key <= reg_key;
end generate;
genRdKey: if (G_RDKEY_ENABLE = 1) generate
rdkey <= reg_rdkey;
end generate;
bdi_valid_bytes <= reg_vbytes;
bdi_pad_loc <= reg_ploc;
genNpub: if (G_NPUB_DISABLE = 0) generate
signal reg_npub : std_logic_vector(REG_NPUB_WIDTH -1 downto 0); --! Npub register
begin
npub <= reg_npub(REG_NPUB_WIDTH-1 downto REG_NPUB_WIDTH-G_NPUB_SIZE);
procReg:
process( clk )
begin
if rising_edge( clk ) then
if (rst = '1') then
reg_npub <= (others => '0');
elsif (en_npub = '1') then
if (G_W >= G_NPUB_SIZE) then
reg_npub <= pdi(G_W-1 downto G_W-REG_NPUB_WIDTH);
else
reg_npub <= reg_npub(REG_NPUB_WIDTH-G_W-1 downto 0) & pdi;
end if;
end if;
end if;
end process;
end generate;
genNsec: if (G_NSEC_ENABLE = 1) generate
signal reg_nsec : std_logic_vector(G_NSEC_SIZE -1 downto 0); --! Nsec register
begin
nsec <= reg_nsec;
procReg:
process( clk )
begin
if rising_edge( clk ) then
if (en_nsec = '1') then
if (G_W < G_NSEC_SIZE) then
reg_nsec <= reg_nsec(G_NSEC_SIZE-G_W-1 downto 0) & pdi;
else
reg_nsec <= pdi(G_W-1 downto G_W-G_NSEC_SIZE);
end if;
end if;
end if;
end process;
end generate;
--! ============ Special mode ===========
genPartial: if ((G_DBLK_SIZE mod G_W) > 0) generate
constant ZEROS : std_logic_vector(G_W-1 downto 0) := (others => '0');
signal padded_reg : std_logic_vector(G_W/2-1 downto 0);
signal dbytes_reg : std_logic_vector((G_W/8)/2-1 downto 0);
begin
process(clk)
begin
if rising_edge(clk) then
if (en_data = '1' and sel_blank_pdi = '0') then
padded_reg <= p_1pad_di(G_W/2-1 downto 0);
dbytes_reg <= vbytes((G_W/8)/2-1 downto 0);
end if;
end if;
end process;
genKeyak0: if G_KEYAK = 0 generate
with sel_input(2 downto 0) select
input_data <= p_1pad_di when "000",
p_1pad_di(G_W-1 downto G_W-G_W/2) & ZEROS(G_W-1 downto G_W-G_W/2) when "001",
padded_reg & p_1pad_di(G_W-1 downto G_W-G_W/2) when "010",
padded_reg & ZEROS(G_W-1 downto G_W-G_W/2) when "011",
(others => '0') when others;
with sel_input(2 downto 0) select
input_vbytes <= vbytes when "000",
vbytes(G_W/8-1 downto G_W/8-(G_W/8)/2) & ZEROS(G_W/8-1 downto G_W/8-(G_W/8)/2) when "001",
dbytes_reg & vbytes(G_W/8-1 downto G_W/8-(G_W/8)/2) when "010",
dbytes_reg & ZEROS(G_W/8-1 downto G_W/8-(G_W/8)/2) when "011",
(others => '0') when others;
end generate;
--! Special loading for Keyak
genKeyak1: if (G_KEYAK = 1 and G_W = 128 and G_DBLK_SIZE = 1344) generate
signal key_r : std_logic_vector(G_KEY_SIZE-1 downto 0);
begin
pKey: process(clk)
begin
if rising_edge(clk) then
if (key_updated = '1') then
key_r <= reg_key;
end if;
end if;
end process;
with sel_input(2 downto 0) select
input_data <= p_1pad_di when "000",
p_1pad_di(G_W-1 downto G_W-G_W/2) & ZEROS(G_W-1 downto G_W-G_W/2) when "001",
padded_reg & p_1pad_di(G_W-1 downto G_W-G_W/2) when "010",
padded_reg & ZEROS(G_W-1 downto G_W-G_W/2) when "011",
x"1E" & key_r(G_KEY_SIZE-1 downto 8) when "100",
key_r(7 downto 0) & x"01" & x"000000000000000000000000" & x"0100" when "101",
(others => '0') when others;
with sel_input(2 downto 0) select
input_vbytes <= vbytes when "000",
vbytes(G_W/8-1 downto G_W/8-(G_W/8)/2) & ZEROS(G_W/8-1 downto G_W/8-(G_W/8)/2) when "001",
dbytes_reg & vbytes(G_W/8-1 downto G_W/8-(G_W/8)/2) when "010",
dbytes_reg & ZEROS(G_W/8-1 downto G_W/8-(G_W/8)/2) when "011",
(others => '1') when "100",
(others => '1') when "101",
(others => '0') when others;
end generate;
end generate;
--! ============ Padding related logic =================
--! No padding unit
genPad0: if G_PAD = 0 generate
begin
p_1pad_di <= p_zpad_di;
end generate;
--! With padding unit
genPad1: if G_PAD = 1 generate
signal pad_loc_s : std_logic_vector(G_W/8 -1 downto 0);
signal ploc_reg : std_logic_vector((G_W/8)/2 -1 downto 0);
begin
--! No actual padding is performed. However, padding location is produced. Used this mode if bdi_pad_loc signal is required)
genPadMode0:
if G_PAD_STYLE = 0 generate
p_1pad_di <= p_zpad_di;
end generate;
--! Pad 10*
genPadMode1:
if G_PAD_STYLE = 1 generate
genLoop:
for i in 0 to G_W/8-1 generate
p_1pad_di(G_W-i*8-1) <= '1' when (pad_enable = '1' and pad_loc_r(i) = '1' ) else p_zpad_di(G_W-i*8-1);
p_1pad_di(G_W-i*8-2 downto G_W-i*8-8) <= p_zpad_di(G_W-i*8-2 downto G_W-i*8-8);
end generate;
end generate;
--! Padding mode for ICEPOLE
genPadMode2:
if G_PAD_STYLE = 2 generate
genLoop:
for i in 0 to G_W/8-1 generate
p_1pad_di(G_W-i*8-1 downto G_W-i*8-6) <= p_zpad_di(G_W-i*8-1 downto G_W-i*8-6);
p_1pad_di(G_W-i*8-7) <= '1' when (pad_enable = '1' and pad_loc_r(i) = '1' ) else p_zpad_di(G_W-i*8-7);
p_1pad_di(G_W-i*8-8) <= '1' when (pad_enable = '1' and pad_loc_r(i) = '1' and ((pad_eot = '1' and pad_type_ad = '1') or (pad_eot = '0' and pad_type_ad = '0'))) else p_zpad_di(G_W-i*8-8);
end generate;
end generate;
--! Padding mode for Keyak
genPadMode3:
if G_PAD_STYLE = 3 generate
genLoop:
for i in 0 to G_W/8-1 generate
p_1pad_di(G_W-i*8-1) <= p_zpad_di(G_W-i*8-1);
p_1pad_di(G_W-i*8-2) <= p_zpad_di(G_W-i*8-2);
p_1pad_di(G_W-i*8-3) <= p_zpad_di(G_W-i*8-3);
p_1pad_di(G_W-i*8-4) <= p_zpad_di(G_W-i*8-4);
p_1pad_di(G_W-i*8-5) <= p_zpad_di(G_W-i*8-5);
p_1pad_di(G_W-i*8-6) <= '1' when (pad_enable = '1' and pad_loc_r(i) = '1') else p_zpad_di(G_W-i*8-6);
p_1pad_di(G_W-i*8-7) <= '1' when (pad_enable = '1' and pad_loc_r(i) = '1' and ((pad_type_ad = '1' and pad_eoi = '0' and pad_eot = '1') or (pad_type_ad = '0' and pad_eot = '0'))) else p_zpad_di(G_W-i*8-7);
p_1pad_di(G_W-i*8-8) <= '1' when (pad_enable = '1' and pad_loc_r(i) = '1' and (pad_type_ad = '0' or (pad_eoi = '1' and pad_type_ad = '1'))) else p_zpad_di(G_W-i*8-8);
end generate;
end generate;
procReg: process(clk)
begin
if rising_edge(clk) then
if en_pad_loc = '1' then
pad_loc_r <= pad_loc_s;
end if;
if G_W >= G_DBLK_SIZE then
if (en_data = '1') then
if (pad_enable = '1') then
reg_ploc <= reverse_bit(pad_loc_r);
else
reg_ploc <= (others => '0');
end if;
end if;
elsif (G_DBLK_SIZE MOD G_W) = 0 then
if (en_data = '1') then
if (pad_enable = '1') then
reg_ploc <= reg_ploc(G_DBLK_SIZE/8-G_W/8-1 downto 0) & reverse_bit(pad_loc_s);
else
reg_ploc <= reg_ploc(G_DBLK_SIZE/8-G_W/8-1 downto 0) & ZWORD_BYTES(G_W/8-1 downto 0);
end if;
end if;
elsif (G_DBLK_SIZE MOD G_W) /= 0 then
if (rst = '1') then
reg_ploc <= (others => '0');
elsif (en_data = '1') then
ploc_reg <= pad_loc_s(((G_W/8)-1) downto ((G_W/8)/2));
if (en_last_word = '0') then
if (pad_enable = '1') then
reg_ploc(G_DBLK_SIZE/8-1 downto ((G_DBLK_SIZE/8) MOD (G_W/8))) <= reg_ploc(G_DBLK_SIZE/8-G_W/8-1 downto ((G_DBLK_SIZE/8) MOD (G_W/8))) & input_ploc;
else
reg_ploc(G_DBLK_SIZE/8-1 downto ((G_DBLK_SIZE/8) MOD (G_W/8))) <= reg_ploc(G_DBLK_SIZE/8-G_W/8-1 downto ((G_DBLK_SIZE/8) MOD (G_W/8))) & ZWORD_BYTES(G_W/8-1 downto 0);
end if;
else
if (pad_enable = '1') then
reg_ploc(((G_DBLK_SIZE/8) mod (G_W/8))-1 downto 0) <= input_ploc(G_W/8-1 downto (G_W/8)/2);
else
reg_ploc(((G_DBLK_SIZE/8) mod (G_W/8))-1 downto 0) <= (others => '0');
end if;
end if;
end if;
end if;
end if;
end process;
gKeyak0:
if ((G_KEYAK = 0) and ((G_DBLK_SIZE MOD G_W) /= 0)) generate
with sel_input(2 downto 0) select
input_ploc <= reverse_bit(pad_loc_s) when "000",
reverse_bit(pad_loc_s)(G_W/8-1 downto (G_W/8)/2) & ZWORD_BYTES(G_W/8-1 downto G_W/8-(G_W/8)/2) when "001",
reverse_bit(ploc_reg) & reverse_bit(pad_loc_s((G_W/8)/2-1 downto 0)) when "010",
reverse_bit(ploc_reg) & ZWORD_BYTES(G_W/8-1 downto G_W/8-(G_W/8)/2) when "011",
(others => '0') when others;
end generate;
gKeyak1:
if (G_KEYAK = 1) generate
with sel_input(2 downto 0) select
input_ploc <= reverse_bit(pad_loc_s) when "000",
reverse_bit(pad_loc_s)(G_W/8-1 downto (G_W/8)/2) & ZWORD_BYTES(G_W/8-1 downto G_W/8-(G_W/8)/2) when "001",
reverse_bit(ploc_reg) & reverse_bit(pad_loc_s((G_W/8)/2-1 downto 0)) when "010",
reverse_bit(ploc_reg) & ZWORD_BYTES(G_W/8-1 downto G_W/8-(G_W/8)/2) when "011",
(others => '0') when others;
-- with sel_input(2 downto 0) select
-- input_ploc <= reverse_bit(pad_loc_s) when "000",
-- reverse_bit(ploc_reg) & reverse_bit(pad_loc_s((G_W/8)/2-1 downto 0)) when "001",
-- reverse_bit(ploc_reg) & ZWORD_BYTES(G_W/8-1 downto G_W/8-(G_W/8)/2) when "010",
-- (others => '0') when others;
end generate;
--! Calculate the padding locatin
uBarrelShifter:
entity work.bshift(struct)
generic map (G_W => G_W/8, G_LOG2_W => LOG2_W, G_LEFT => 1, G_ROTATE => 0)
port map (ii => BSHIFT_INPUT, rtr => pad_shift, oo => pad_loc_s);
end generate;
end dataflow;
|
-------------------------------------------------------------------------------
--! @file PreProcessor_Datapath.vhd
--! @brief Datapath for the pre-processor
--! @project CAESAR Candidate Evaluation
--! @author Ekawat (ice) Homsirikamol
--! @copyright Copyright (c) 2015 Cryptographic Engineering Research Group
--! ECE Department, George Mason University Fairfax, VA, U.S.A.
--! All rights Reserved.
--! @license This project is released under the GNU Public License.
--! The license and distribution terms for this file may be
--! found in the file LICENSE in this distribution or at
--! http://www.gnu.org/licenses/gpl-3.0.txt
--! @note This is publicly available encryption source code that falls
--! under the License Exception TSU (Technology and software-
--! —unrestricted)
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use work.AEAD_pkg.all;
entity PreProcessor_Datapath is
generic (
G_W : integer := 64; --! Public data width (bits)
G_SW : integer := 64; --! Secret data width (bits)
G_CTR_AD_SIZE : integer := 64; --! Maximum size for the counter that keeps track of authenticated data
G_CTR_D_SIZE : integer := 64; --! Maximum size for the counter that keeps track of data
G_DBLK_SIZE : integer := 128; --! Block size (bits)
G_KEY_SIZE : integer := 128; --! Key size (bits)
G_KEYAK : integer := 0; --! Special input mode, used only for Keyak with G_W = 128 and G_DBLK_SIZE = 1344
G_NPUB_DISABLE : integer := 0; --! Disable Npub related port(s)
G_NPUB_SIZE : integer := 128; --! Npub width (bits)
G_NSEC_ENABLE : integer := 0; --! Enable nsec port
G_NSEC_SIZE : integer := 128; --! Nsec width (bits)
G_LOADLEN_ENABLE : integer := 0; --! Enable load length section
G_PAD : integer := 0; --! Enable padding
G_PAD_STYLE : integer := 1; --! Padding mode 0 = *10..., 1 = ICEPOLE's padding
G_RDKEY_ENABLE : integer := 0; --! Enable rdkey port (also disables key port)
G_RDKEY_SIZE : integer := 128; --! Roundkey size (bits)
G_TAG_SIZE : integer := 128 --! Tag size (bits)
);
port (
--! =================
--! External Signals
--! =================
--! Global signals
clk : in std_logic;
rst : in std_logic;
pdi : in std_logic_vector(G_W -1 downto 0); --! Public data
sdi : in std_logic_vector(G_SW -1 downto 0); --! Secret data
--! =================
--! Crypto Core Signals
--! =================
key : out std_logic_vector(G_KEY_SIZE -1 downto 0); --! Key data
rdkey : out std_logic_vector(G_RDKEY_SIZE -1 downto 0); --! Round key data
bdi : out std_logic_vector(G_DBLK_SIZE -1 downto 0); --! Block data
npub : out std_logic_vector(G_NPUB_SIZE -1 downto 0); --! Npub data
nsec : out std_logic_vector(G_NSEC_SIZE -1 downto 0); --! Nsec data
exp_tag : out std_logic_vector(G_TAG_SIZE -1 downto 0); --! Expected tag data
bdi_valid_bytes : out std_logic_vector(G_DBLK_SIZE/8 -1 downto 0);
bdi_pad_loc : out std_logic_vector(G_DBLK_SIZE/8 -1 downto 0);
len_a : out std_logic_vector(G_CTR_AD_SIZE -1 downto 0); --! Len of authenticated data in bytes (used for some algorithm)
len_d : out std_logic_vector(G_CTR_D_SIZE -1 downto 0); --! Len of data in bytes (used for some algorithm)
--! =================
--! Internal Signals
--! =================
--! Control signals
key_updated : in std_logic; --! (if G_DBLK_SIZE mod G_W > 0) Key updated signal (used only for situation when key is stored within input processor)
pad_shift : in std_logic_vector(log2_ceil(G_W/8) -1 downto 0);
en_data : in std_logic; --! Shift data SIPO
en_npub : in std_logic; --! Shift Npub SIPO
en_nsec : in std_logic; --! Shift Nsec SIPO
en_key : in std_logic; --! Shift key SIPO
en_rdkey : in std_logic; --! Shift round key SIPO
en_exp_tag : in std_logic; --! Shift expected tag SIPO
sel_blank_pdi : in std_logic; --! Select input data as blank (for filling in the remaining data within a block)
clr_len : in std_logic; --! Clear stored length (len_a and len_d)
en_len_a_r : in std_logic; --! Add authenticated data counter
en_len_d_r : in std_logic; --! Add data counter
en_len_last_r : in std_logic; --! Special signal for en_len_*_r
en_len_a : in std_logic; --! Add authenticated data counter (instant)
en_len_d : in std_logic; --! Add data counter (no)
size_dword : in std_logic_vector(log2_ceil(G_W/8) downto 0); --! Size of data word
en_last_word : in std_logic; --! Last word in a block
pad_eot : in std_logic; --! Padding is EOT
pad_eoi : in std_logic; --! Padding is EOI
pad_type_ad : in std_logic; --! Padding is AD
pad_enable : in std_logic; --! Enable padding signal (indicates that the current word requires padding)
en_pad_loc : in std_logic; --! Save the padding location into a register
sel_input : in std_logic_vector(3 -1 downto 0) --! (if G_DBLK_SIZE mod G_W > 0) Select input for m
);
end PreProcessor_Datapath;
architecture dataflow of PreProcessor_Datapath is
--! Constants declaration
constant LOG2_W : integer := log2_ceil(G_W/8); --! LOG_2(G_W)
constant LOG2_SW : integer := log2_ceil(G_SW/8); --! LOG_2(G_SW)
constant REG_NPUB_WIDTH : integer := (((G_NPUB_SIZE-1)/G_W)+1)*G_W; --! Calculate the width of Npub register
constant CNTR_WIDTH : integer := get_cntr_width(G_W); --! Calculate the length of p_size register
constant LEN_A_WIDTH : integer := maximum(CNTR_WIDTH, G_CTR_AD_SIZE);
constant LEN_D_WIDTH : integer := maximum(CNTR_WIDTH, G_CTR_D_SIZE);
constant CNT_DATA_WORDS : integer := (G_DBLK_SIZE+(G_W-1))/G_W; --! Calculate the number of words required for data (rounded up)
constant CNT_TAG_WORDS : integer := (G_DBLK_SIZE+(G_W-1))/G_W; --! Calculate the number of words required for tag (rounded up)
constant BSHIFT_INPUT : std_logic_vector(G_W/8 -1 downto 0) := std_logic_vector(to_unsigned(1,G_W/8));
constant OWORD_BYTES : std_logic_vector(G_DBLK_SIZE/8 -1 downto 0) := (others => '1'); --! The number of bytes in a word in ones.
constant ZWORD_BYTES : std_logic_vector(G_DBLK_SIZE/8 -1 downto 0) := (others => '0'); --! The number of bytes in a word in zeros.
function reverse_bit(aa: std_logic_vector) return std_logic_vector is
variable bb : std_logic_vector(aa'high downto aa'low);
begin
for i in aa'high downto aa'low loop
bb(i) := aa(aa'high-i);
end loop;
return bb;
end function reverse_bit;
type lookup_type is array (0 to ((G_W/8)*2-1)) of std_logic_vector(G_W/8-1 downto 0);
function getVbytesLookup(size: integer) return lookup_type is
variable ret : lookup_type;
begin
for i in 0 to ((size/8)*2-1) loop
if (i >= (size/8)) then
ret(i) := (others => '1');
elsif (i = 0) then
ret(i) := (others => '0');
else
ret(i)(size/8-1 downto size/8-i) := (others => '1');
ret(i)(size/8-i-1 downto 0) := (others => '0');
end if;
end loop;
return ret;
end function getVbytesLookup;
constant VBYTES_LOOKUP : lookup_type := getVbytesLookup(G_W);
--! ==================
--! Note: Current unused (keep this portion for later consideration)
function getPlocLookup(size: integer) return lookup_type is
variable ret : lookup_type;
begin
for i in 0 to ((size/8)*2-1) loop
if (i >= (size/8)) then
ret(i) := (others => '0');
else
ret(i) := (i => '1', others => '0');
end if;
end loop;
return ret;
end function getPlocLookup;
constant PLOC_LOOKUP : lookup_type := getPlocLookup(G_W);
--! End of note
--! ==================
--! Key related signals and registers
signal reg_key : std_logic_vector(G_KEY_SIZE -1 downto 0);
signal reg_rdkey : std_logic_vector(G_RDKEY_SIZE -1 downto 0);
--! Public data signals and registers
signal reg_data : std_logic_vector(G_DBLK_SIZE -1 downto 0); --! Data block register
signal reg_exp_tag : std_logic_vector(G_TAG_SIZE -1 downto 0); --! Tag register
signal reg_vbytes : std_logic_vector(G_DBLK_SIZE/8 -1 downto 0); --! Valid bytes register
signal reg_ploc : std_logic_vector(G_DBLK_SIZE/8 -1 downto 0); --! Pad location register
signal p_size : std_logic_vector(CNTR_WIDTH -1 downto 0); --! Public data segment size
signal p_zpad_di : std_logic_vector(G_W -1 downto 0); --! Internally selected signal for padding
signal p_1pad_di : std_logic_vector(G_W -1 downto 0); --! Internally selected signal for padding
signal input_data : std_logic_vector(G_W -1 downto 0); --! Additional select signal for padding
signal input_vbytes : std_logic_vector(G_W/8 -1 downto 0); --! Additional select signal for bytes size
signal input_ploc : std_logic_vector(G_W/8 -1 downto 0); --! Additional select signal for bytes size
--! Data block status register for external modules
signal len_a_reg : std_logic_vector(LEN_A_WIDTH -1 downto 0); --! Total authenticated data register
signal len_d_reg : std_logic_vector(LEN_D_WIDTH -1 downto 0); --! Total message data register --! Current block contains no message data (used for authenticated encryption data only mode)
--! Padding related signals
signal pad_loc_r : std_logic_vector(G_W/8 -1 downto 0);
--! Lookups
signal vbytes : std_logic_vector(G_W/8 -1 downto 0);
signal ploc : std_logic_vector(G_W/8 -1 downto 0);
begin
p_zpad_di <= pdi when sel_blank_pdi = '0' else (others => '0');
vbytes <= VBYTES_LOOKUP(conv_integer(size_dword));
ploc <= PLOC_LOOKUP(conv_integer(size_dword));
--! Datapath
procReg:
process( clk )
begin
if rising_edge( clk ) then
if rst = '1' then
reg_data <= (others => '0');
reg_exp_tag <= (others => '0');
len_a_reg <= (others => '0');
len_d_reg <= (others => '0');
reg_vbytes <= (others => '0');
else
--! === Public data
--! Data SIPO
if (en_data = '1') then
--! Handle different block size
if (G_W >= G_DBLK_SIZE) then
reg_data <= p_1pad_di(G_W-1 downto G_W-G_DBLK_SIZE);
reg_vbytes <= vbytes(G_W/8-1 downto G_W/8-G_DBLK_SIZE/8);
elsif ((G_DBLK_SIZE MOD G_W) = 0) then
reg_data <= reg_data(G_DBLK_SIZE-G_W-1 downto 0) & p_1pad_di;
reg_vbytes <= reg_vbytes(G_DBLK_SIZE/8-G_W/8-1 downto 0) & vbytes;
elsif ((G_DBLK_SIZE MOD G_W) /= 0) then
if (en_last_word = '0') then
reg_data (G_DBLK_SIZE-1 downto ( G_DBLK_SIZE MOD G_W)) <= reg_data (G_DBLK_SIZE- G_W -1 downto ( G_DBLK_SIZE MOD G_W)) & input_data;
reg_vbytes(G_DBLK_SIZE/8-1 downto ((G_DBLK_SIZE/8) MOD (G_W/8))) <= reg_vbytes(G_DBLK_SIZE/8-G_W/8-1 downto ((G_DBLK_SIZE/8) MOD (G_W/8))) & input_vbytes;
else
reg_data ((G_DBLK_SIZE mod G_W )-1 downto 0) <= input_data (G_W -1 downto G_W /2);
reg_vbytes(((G_DBLK_SIZE/8) mod (G_W/8))-1 downto 0) <= input_vbytes(G_W/8-1 downto (G_W/8)/2);
end if;
end if;
end if;
--! Tag SIPO
if (en_exp_tag = '1') then
--! Handle different block size
if (G_W >= G_TAG_SIZE) then
reg_exp_tag <= pdi(G_W-1 downto G_W-G_TAG_SIZE);
else
reg_exp_tag <= reg_exp_tag(G_TAG_SIZE-G_W-1 downto 0) & pdi;
end if;
end if;
--! === Secret data
--! Key SIPO
if (en_key = '1') then
--! Handle different I/O and key size
if (G_SW < G_KEY_SIZE) then
reg_key <= reg_key(G_KEY_SIZE-G_SW-1 downto 0) & sdi;
elsif G_SW = G_KEY_SIZE then
reg_key <= sdi;
end if;
end if;
--! Round Key SIPO
if (en_rdkey = '1') then
--! Handle different I/O and key size
if (G_SW < G_RDKEY_SIZE) then
reg_rdkey <= reg_rdkey(G_RDKEY_SIZE-G_SW-1 downto 0) & sdi;
elsif G_SW = G_RDKEY_SIZE then
reg_rdkey <= sdi;
end if;
end if;
--! === Status
--! Length registers
if (clr_len = '1') then
len_a_reg <= (others => '0');
len_d_reg <= (others => '0');
else
if (G_LOADLEN_ENABLE = 0) then
if (en_len_a = '1') then
len_a_reg <= len_a_reg + p_size;
end if;
if (en_len_d = '1') then
len_d_reg <= len_d_reg + p_size;
end if;
else
if (en_len_a_r = '1') then
if (G_W >= LEN_A_WIDTH) then
len_a_reg <= pdi(LEN_A_WIDTH-1 downto 0);
elsif ((LEN_A_WIDTH MOD G_W) = 0) then
len_a_reg <= len_a_reg(LEN_A_WIDTH-G_W-1 downto 0) & pdi;
else
if (en_len_last_r = '0') then
if (LEN_A_WIDTH/G_W > 1) then
len_a_reg(LEN_A_WIDTH-1 downto (LEN_A_WIDTH MOD G_W)) <= len_a_reg(LEN_A_WIDTH-G_W-1 downto (LEN_A_WIDTH MOD G_W)) & pdi;
else
len_a_reg(LEN_A_WIDTH-1 downto (LEN_A_WIDTH MOD G_W)) <= pdi;
end if;
else
len_a_reg((LEN_A_WIDTH MOD G_W)-1 downto 0) <= pdi(G_W-1 downto G_W-(LEN_A_WIDTH MOD G_W));
end if;
end if;
end if;
if (en_len_d_r = '1') then
if (G_W >= LEN_D_WIDTH) then
len_d_reg <= pdi(LEN_D_WIDTH-1 downto 0);
elsif ((LEN_D_WIDTH MOD G_W) = 0) then
len_d_reg <= len_d_reg(LEN_D_WIDTH-G_W-1 downto 0) & pdi;
else
if (en_len_last_r = '0') then
if (LEN_D_WIDTH/G_W > 1) then
len_d_reg(LEN_D_WIDTH-1 downto (LEN_D_WIDTH MOD G_W)) <= len_d_reg(LEN_D_WIDTH-G_W-1 downto (LEN_D_WIDTH MOD G_W)) & pdi;
else
len_d_reg(LEN_D_WIDTH-1 downto (LEN_D_WIDTH MOD G_W)) <= pdi;
end if;
else
len_d_reg((LEN_D_WIDTH MOD G_W)-1 downto 0) <= pdi(G_W-1 downto G_W-(LEN_D_WIDTH MOD G_W));
end if;
end if;
end if;
end if;
end if;
end if;
end if;
end process;
--! Public data size (based on the interface)
p_size <= pdi(CNTR_WIDTH -1 downto 0);
--! Output
len_a <= len_a_reg(G_CTR_AD_SIZE -1 downto 0);
len_d <= len_d_reg(G_CTR_D_SIZE -1 downto 0);
bdi <= reg_data;
exp_tag <= reg_exp_tag;
genKey: if (G_RDKEY_ENABLE = 0) generate
key <= reg_key;
end generate;
genRdKey: if (G_RDKEY_ENABLE = 1) generate
rdkey <= reg_rdkey;
end generate;
bdi_valid_bytes <= reg_vbytes;
bdi_pad_loc <= reg_ploc;
genNpub: if (G_NPUB_DISABLE = 0) generate
signal reg_npub : std_logic_vector(REG_NPUB_WIDTH -1 downto 0); --! Npub register
begin
npub <= reg_npub(REG_NPUB_WIDTH-1 downto REG_NPUB_WIDTH-G_NPUB_SIZE);
procReg:
process( clk )
begin
if rising_edge( clk ) then
if (rst = '1') then
reg_npub <= (others => '0');
elsif (en_npub = '1') then
if (G_W >= G_NPUB_SIZE) then
reg_npub <= pdi(G_W-1 downto G_W-REG_NPUB_WIDTH);
else
reg_npub <= reg_npub(REG_NPUB_WIDTH-G_W-1 downto 0) & pdi;
end if;
end if;
end if;
end process;
end generate;
genNsec: if (G_NSEC_ENABLE = 1) generate
signal reg_nsec : std_logic_vector(G_NSEC_SIZE -1 downto 0); --! Nsec register
begin
nsec <= reg_nsec;
procReg:
process( clk )
begin
if rising_edge( clk ) then
if (en_nsec = '1') then
if (G_W < G_NSEC_SIZE) then
reg_nsec <= reg_nsec(G_NSEC_SIZE-G_W-1 downto 0) & pdi;
else
reg_nsec <= pdi(G_W-1 downto G_W-G_NSEC_SIZE);
end if;
end if;
end if;
end process;
end generate;
--! ============ Special mode ===========
genPartial: if ((G_DBLK_SIZE mod G_W) > 0) generate
constant ZEROS : std_logic_vector(G_W-1 downto 0) := (others => '0');
signal padded_reg : std_logic_vector(G_W/2-1 downto 0);
signal dbytes_reg : std_logic_vector((G_W/8)/2-1 downto 0);
begin
process(clk)
begin
if rising_edge(clk) then
if (en_data = '1' and sel_blank_pdi = '0') then
padded_reg <= p_1pad_di(G_W/2-1 downto 0);
dbytes_reg <= vbytes((G_W/8)/2-1 downto 0);
end if;
end if;
end process;
genKeyak0: if G_KEYAK = 0 generate
with sel_input(2 downto 0) select
input_data <= p_1pad_di when "000",
p_1pad_di(G_W-1 downto G_W-G_W/2) & ZEROS(G_W-1 downto G_W-G_W/2) when "001",
padded_reg & p_1pad_di(G_W-1 downto G_W-G_W/2) when "010",
padded_reg & ZEROS(G_W-1 downto G_W-G_W/2) when "011",
(others => '0') when others;
with sel_input(2 downto 0) select
input_vbytes <= vbytes when "000",
vbytes(G_W/8-1 downto G_W/8-(G_W/8)/2) & ZEROS(G_W/8-1 downto G_W/8-(G_W/8)/2) when "001",
dbytes_reg & vbytes(G_W/8-1 downto G_W/8-(G_W/8)/2) when "010",
dbytes_reg & ZEROS(G_W/8-1 downto G_W/8-(G_W/8)/2) when "011",
(others => '0') when others;
end generate;
--! Special loading for Keyak
genKeyak1: if (G_KEYAK = 1 and G_W = 128 and G_DBLK_SIZE = 1344) generate
signal key_r : std_logic_vector(G_KEY_SIZE-1 downto 0);
begin
pKey: process(clk)
begin
if rising_edge(clk) then
if (key_updated = '1') then
key_r <= reg_key;
end if;
end if;
end process;
with sel_input(2 downto 0) select
input_data <= p_1pad_di when "000",
p_1pad_di(G_W-1 downto G_W-G_W/2) & ZEROS(G_W-1 downto G_W-G_W/2) when "001",
padded_reg & p_1pad_di(G_W-1 downto G_W-G_W/2) when "010",
padded_reg & ZEROS(G_W-1 downto G_W-G_W/2) when "011",
x"1E" & key_r(G_KEY_SIZE-1 downto 8) when "100",
key_r(7 downto 0) & x"01" & x"000000000000000000000000" & x"0100" when "101",
(others => '0') when others;
with sel_input(2 downto 0) select
input_vbytes <= vbytes when "000",
vbytes(G_W/8-1 downto G_W/8-(G_W/8)/2) & ZEROS(G_W/8-1 downto G_W/8-(G_W/8)/2) when "001",
dbytes_reg & vbytes(G_W/8-1 downto G_W/8-(G_W/8)/2) when "010",
dbytes_reg & ZEROS(G_W/8-1 downto G_W/8-(G_W/8)/2) when "011",
(others => '1') when "100",
(others => '1') when "101",
(others => '0') when others;
end generate;
end generate;
--! ============ Padding related logic =================
--! No padding unit
genPad0: if G_PAD = 0 generate
begin
p_1pad_di <= p_zpad_di;
end generate;
--! With padding unit
genPad1: if G_PAD = 1 generate
signal pad_loc_s : std_logic_vector(G_W/8 -1 downto 0);
signal ploc_reg : std_logic_vector((G_W/8)/2 -1 downto 0);
begin
--! No actual padding is performed. However, padding location is produced. Used this mode if bdi_pad_loc signal is required)
genPadMode0:
if G_PAD_STYLE = 0 generate
p_1pad_di <= p_zpad_di;
end generate;
--! Pad 10*
genPadMode1:
if G_PAD_STYLE = 1 generate
genLoop:
for i in 0 to G_W/8-1 generate
p_1pad_di(G_W-i*8-1) <= '1' when (pad_enable = '1' and pad_loc_r(i) = '1' ) else p_zpad_di(G_W-i*8-1);
p_1pad_di(G_W-i*8-2 downto G_W-i*8-8) <= p_zpad_di(G_W-i*8-2 downto G_W-i*8-8);
end generate;
end generate;
--! Padding mode for ICEPOLE
genPadMode2:
if G_PAD_STYLE = 2 generate
genLoop:
for i in 0 to G_W/8-1 generate
p_1pad_di(G_W-i*8-1 downto G_W-i*8-6) <= p_zpad_di(G_W-i*8-1 downto G_W-i*8-6);
p_1pad_di(G_W-i*8-7) <= '1' when (pad_enable = '1' and pad_loc_r(i) = '1' ) else p_zpad_di(G_W-i*8-7);
p_1pad_di(G_W-i*8-8) <= '1' when (pad_enable = '1' and pad_loc_r(i) = '1' and ((pad_eot = '1' and pad_type_ad = '1') or (pad_eot = '0' and pad_type_ad = '0'))) else p_zpad_di(G_W-i*8-8);
end generate;
end generate;
--! Padding mode for Keyak
genPadMode3:
if G_PAD_STYLE = 3 generate
genLoop:
for i in 0 to G_W/8-1 generate
p_1pad_di(G_W-i*8-1) <= p_zpad_di(G_W-i*8-1);
p_1pad_di(G_W-i*8-2) <= p_zpad_di(G_W-i*8-2);
p_1pad_di(G_W-i*8-3) <= p_zpad_di(G_W-i*8-3);
p_1pad_di(G_W-i*8-4) <= p_zpad_di(G_W-i*8-4);
p_1pad_di(G_W-i*8-5) <= p_zpad_di(G_W-i*8-5);
p_1pad_di(G_W-i*8-6) <= '1' when (pad_enable = '1' and pad_loc_r(i) = '1') else p_zpad_di(G_W-i*8-6);
p_1pad_di(G_W-i*8-7) <= '1' when (pad_enable = '1' and pad_loc_r(i) = '1' and ((pad_type_ad = '1' and pad_eoi = '0' and pad_eot = '1') or (pad_type_ad = '0' and pad_eot = '0'))) else p_zpad_di(G_W-i*8-7);
p_1pad_di(G_W-i*8-8) <= '1' when (pad_enable = '1' and pad_loc_r(i) = '1' and (pad_type_ad = '0' or (pad_eoi = '1' and pad_type_ad = '1'))) else p_zpad_di(G_W-i*8-8);
end generate;
end generate;
procReg: process(clk)
begin
if rising_edge(clk) then
if en_pad_loc = '1' then
pad_loc_r <= pad_loc_s;
end if;
if G_W >= G_DBLK_SIZE then
if (en_data = '1') then
if (pad_enable = '1') then
reg_ploc <= reverse_bit(pad_loc_r);
else
reg_ploc <= (others => '0');
end if;
end if;
elsif (G_DBLK_SIZE MOD G_W) = 0 then
if (en_data = '1') then
if (pad_enable = '1') then
reg_ploc <= reg_ploc(G_DBLK_SIZE/8-G_W/8-1 downto 0) & reverse_bit(pad_loc_s);
else
reg_ploc <= reg_ploc(G_DBLK_SIZE/8-G_W/8-1 downto 0) & ZWORD_BYTES(G_W/8-1 downto 0);
end if;
end if;
elsif (G_DBLK_SIZE MOD G_W) /= 0 then
if (rst = '1') then
reg_ploc <= (others => '0');
elsif (en_data = '1') then
ploc_reg <= pad_loc_s(((G_W/8)-1) downto ((G_W/8)/2));
if (en_last_word = '0') then
if (pad_enable = '1') then
reg_ploc(G_DBLK_SIZE/8-1 downto ((G_DBLK_SIZE/8) MOD (G_W/8))) <= reg_ploc(G_DBLK_SIZE/8-G_W/8-1 downto ((G_DBLK_SIZE/8) MOD (G_W/8))) & input_ploc;
else
reg_ploc(G_DBLK_SIZE/8-1 downto ((G_DBLK_SIZE/8) MOD (G_W/8))) <= reg_ploc(G_DBLK_SIZE/8-G_W/8-1 downto ((G_DBLK_SIZE/8) MOD (G_W/8))) & ZWORD_BYTES(G_W/8-1 downto 0);
end if;
else
if (pad_enable = '1') then
reg_ploc(((G_DBLK_SIZE/8) mod (G_W/8))-1 downto 0) <= input_ploc(G_W/8-1 downto (G_W/8)/2);
else
reg_ploc(((G_DBLK_SIZE/8) mod (G_W/8))-1 downto 0) <= (others => '0');
end if;
end if;
end if;
end if;
end if;
end process;
gKeyak0:
if ((G_KEYAK = 0) and ((G_DBLK_SIZE MOD G_W) /= 0)) generate
with sel_input(2 downto 0) select
input_ploc <= reverse_bit(pad_loc_s) when "000",
reverse_bit(pad_loc_s)(G_W/8-1 downto (G_W/8)/2) & ZWORD_BYTES(G_W/8-1 downto G_W/8-(G_W/8)/2) when "001",
reverse_bit(ploc_reg) & reverse_bit(pad_loc_s((G_W/8)/2-1 downto 0)) when "010",
reverse_bit(ploc_reg) & ZWORD_BYTES(G_W/8-1 downto G_W/8-(G_W/8)/2) when "011",
(others => '0') when others;
end generate;
gKeyak1:
if (G_KEYAK = 1) generate
with sel_input(2 downto 0) select
input_ploc <= reverse_bit(pad_loc_s) when "000",
reverse_bit(pad_loc_s)(G_W/8-1 downto (G_W/8)/2) & ZWORD_BYTES(G_W/8-1 downto G_W/8-(G_W/8)/2) when "001",
reverse_bit(ploc_reg) & reverse_bit(pad_loc_s((G_W/8)/2-1 downto 0)) when "010",
reverse_bit(ploc_reg) & ZWORD_BYTES(G_W/8-1 downto G_W/8-(G_W/8)/2) when "011",
(others => '0') when others;
-- with sel_input(2 downto 0) select
-- input_ploc <= reverse_bit(pad_loc_s) when "000",
-- reverse_bit(ploc_reg) & reverse_bit(pad_loc_s((G_W/8)/2-1 downto 0)) when "001",
-- reverse_bit(ploc_reg) & ZWORD_BYTES(G_W/8-1 downto G_W/8-(G_W/8)/2) when "010",
-- (others => '0') when others;
end generate;
--! Calculate the padding locatin
uBarrelShifter:
entity work.bshift(struct)
generic map (G_W => G_W/8, G_LOG2_W => LOG2_W, G_LEFT => 1, G_ROTATE => 0)
port map (ii => BSHIFT_INPUT, rtr => pad_shift, oo => pad_loc_s);
end generate;
end dataflow;
|
-------------------------------------------------------------------------------
--! @file PreProcessor_Datapath.vhd
--! @brief Datapath for the pre-processor
--! @project CAESAR Candidate Evaluation
--! @author Ekawat (ice) Homsirikamol
--! @copyright Copyright (c) 2015 Cryptographic Engineering Research Group
--! ECE Department, George Mason University Fairfax, VA, U.S.A.
--! All rights Reserved.
--! @license This project is released under the GNU Public License.
--! The license and distribution terms for this file may be
--! found in the file LICENSE in this distribution or at
--! http://www.gnu.org/licenses/gpl-3.0.txt
--! @note This is publicly available encryption source code that falls
--! under the License Exception TSU (Technology and software-
--! —unrestricted)
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use work.AEAD_pkg.all;
entity PreProcessor_Datapath is
generic (
G_W : integer := 64; --! Public data width (bits)
G_SW : integer := 64; --! Secret data width (bits)
G_CTR_AD_SIZE : integer := 64; --! Maximum size for the counter that keeps track of authenticated data
G_CTR_D_SIZE : integer := 64; --! Maximum size for the counter that keeps track of data
G_DBLK_SIZE : integer := 128; --! Block size (bits)
G_KEY_SIZE : integer := 128; --! Key size (bits)
G_KEYAK : integer := 0; --! Special input mode, used only for Keyak with G_W = 128 and G_DBLK_SIZE = 1344
G_NPUB_DISABLE : integer := 0; --! Disable Npub related port(s)
G_NPUB_SIZE : integer := 128; --! Npub width (bits)
G_NSEC_ENABLE : integer := 0; --! Enable nsec port
G_NSEC_SIZE : integer := 128; --! Nsec width (bits)
G_LOADLEN_ENABLE : integer := 0; --! Enable load length section
G_PAD : integer := 0; --! Enable padding
G_PAD_STYLE : integer := 1; --! Padding mode 0 = *10..., 1 = ICEPOLE's padding
G_RDKEY_ENABLE : integer := 0; --! Enable rdkey port (also disables key port)
G_RDKEY_SIZE : integer := 128; --! Roundkey size (bits)
G_TAG_SIZE : integer := 128 --! Tag size (bits)
);
port (
--! =================
--! External Signals
--! =================
--! Global signals
clk : in std_logic;
rst : in std_logic;
pdi : in std_logic_vector(G_W -1 downto 0); --! Public data
sdi : in std_logic_vector(G_SW -1 downto 0); --! Secret data
--! =================
--! Crypto Core Signals
--! =================
key : out std_logic_vector(G_KEY_SIZE -1 downto 0); --! Key data
rdkey : out std_logic_vector(G_RDKEY_SIZE -1 downto 0); --! Round key data
bdi : out std_logic_vector(G_DBLK_SIZE -1 downto 0); --! Block data
npub : out std_logic_vector(G_NPUB_SIZE -1 downto 0); --! Npub data
nsec : out std_logic_vector(G_NSEC_SIZE -1 downto 0); --! Nsec data
exp_tag : out std_logic_vector(G_TAG_SIZE -1 downto 0); --! Expected tag data
bdi_valid_bytes : out std_logic_vector(G_DBLK_SIZE/8 -1 downto 0);
bdi_pad_loc : out std_logic_vector(G_DBLK_SIZE/8 -1 downto 0);
len_a : out std_logic_vector(G_CTR_AD_SIZE -1 downto 0); --! Len of authenticated data in bytes (used for some algorithm)
len_d : out std_logic_vector(G_CTR_D_SIZE -1 downto 0); --! Len of data in bytes (used for some algorithm)
--! =================
--! Internal Signals
--! =================
--! Control signals
key_updated : in std_logic; --! (if G_DBLK_SIZE mod G_W > 0) Key updated signal (used only for situation when key is stored within input processor)
pad_shift : in std_logic_vector(log2_ceil(G_W/8) -1 downto 0);
en_data : in std_logic; --! Shift data SIPO
en_npub : in std_logic; --! Shift Npub SIPO
en_nsec : in std_logic; --! Shift Nsec SIPO
en_key : in std_logic; --! Shift key SIPO
en_rdkey : in std_logic; --! Shift round key SIPO
en_exp_tag : in std_logic; --! Shift expected tag SIPO
sel_blank_pdi : in std_logic; --! Select input data as blank (for filling in the remaining data within a block)
clr_len : in std_logic; --! Clear stored length (len_a and len_d)
en_len_a_r : in std_logic; --! Add authenticated data counter
en_len_d_r : in std_logic; --! Add data counter
en_len_last_r : in std_logic; --! Special signal for en_len_*_r
en_len_a : in std_logic; --! Add authenticated data counter (instant)
en_len_d : in std_logic; --! Add data counter (no)
size_dword : in std_logic_vector(log2_ceil(G_W/8) downto 0); --! Size of data word
en_last_word : in std_logic; --! Last word in a block
pad_eot : in std_logic; --! Padding is EOT
pad_eoi : in std_logic; --! Padding is EOI
pad_type_ad : in std_logic; --! Padding is AD
pad_enable : in std_logic; --! Enable padding signal (indicates that the current word requires padding)
en_pad_loc : in std_logic; --! Save the padding location into a register
sel_input : in std_logic_vector(3 -1 downto 0) --! (if G_DBLK_SIZE mod G_W > 0) Select input for m
);
end PreProcessor_Datapath;
architecture dataflow of PreProcessor_Datapath is
--! Constants declaration
constant LOG2_W : integer := log2_ceil(G_W/8); --! LOG_2(G_W)
constant LOG2_SW : integer := log2_ceil(G_SW/8); --! LOG_2(G_SW)
constant REG_NPUB_WIDTH : integer := (((G_NPUB_SIZE-1)/G_W)+1)*G_W; --! Calculate the width of Npub register
constant CNTR_WIDTH : integer := get_cntr_width(G_W); --! Calculate the length of p_size register
constant LEN_A_WIDTH : integer := maximum(CNTR_WIDTH, G_CTR_AD_SIZE);
constant LEN_D_WIDTH : integer := maximum(CNTR_WIDTH, G_CTR_D_SIZE);
constant CNT_DATA_WORDS : integer := (G_DBLK_SIZE+(G_W-1))/G_W; --! Calculate the number of words required for data (rounded up)
constant CNT_TAG_WORDS : integer := (G_DBLK_SIZE+(G_W-1))/G_W; --! Calculate the number of words required for tag (rounded up)
constant BSHIFT_INPUT : std_logic_vector(G_W/8 -1 downto 0) := std_logic_vector(to_unsigned(1,G_W/8));
constant OWORD_BYTES : std_logic_vector(G_DBLK_SIZE/8 -1 downto 0) := (others => '1'); --! The number of bytes in a word in ones.
constant ZWORD_BYTES : std_logic_vector(G_DBLK_SIZE/8 -1 downto 0) := (others => '0'); --! The number of bytes in a word in zeros.
function reverse_bit(aa: std_logic_vector) return std_logic_vector is
variable bb : std_logic_vector(aa'high downto aa'low);
begin
for i in aa'high downto aa'low loop
bb(i) := aa(aa'high-i);
end loop;
return bb;
end function reverse_bit;
type lookup_type is array (0 to ((G_W/8)*2-1)) of std_logic_vector(G_W/8-1 downto 0);
function getVbytesLookup(size: integer) return lookup_type is
variable ret : lookup_type;
begin
for i in 0 to ((size/8)*2-1) loop
if (i >= (size/8)) then
ret(i) := (others => '1');
elsif (i = 0) then
ret(i) := (others => '0');
else
ret(i)(size/8-1 downto size/8-i) := (others => '1');
ret(i)(size/8-i-1 downto 0) := (others => '0');
end if;
end loop;
return ret;
end function getVbytesLookup;
constant VBYTES_LOOKUP : lookup_type := getVbytesLookup(G_W);
--! ==================
--! Note: Current unused (keep this portion for later consideration)
function getPlocLookup(size: integer) return lookup_type is
variable ret : lookup_type;
begin
for i in 0 to ((size/8)*2-1) loop
if (i >= (size/8)) then
ret(i) := (others => '0');
else
ret(i) := (i => '1', others => '0');
end if;
end loop;
return ret;
end function getPlocLookup;
constant PLOC_LOOKUP : lookup_type := getPlocLookup(G_W);
--! End of note
--! ==================
--! Key related signals and registers
signal reg_key : std_logic_vector(G_KEY_SIZE -1 downto 0);
signal reg_rdkey : std_logic_vector(G_RDKEY_SIZE -1 downto 0);
--! Public data signals and registers
signal reg_data : std_logic_vector(G_DBLK_SIZE -1 downto 0); --! Data block register
signal reg_exp_tag : std_logic_vector(G_TAG_SIZE -1 downto 0); --! Tag register
signal reg_vbytes : std_logic_vector(G_DBLK_SIZE/8 -1 downto 0); --! Valid bytes register
signal reg_ploc : std_logic_vector(G_DBLK_SIZE/8 -1 downto 0); --! Pad location register
signal p_size : std_logic_vector(CNTR_WIDTH -1 downto 0); --! Public data segment size
signal p_zpad_di : std_logic_vector(G_W -1 downto 0); --! Internally selected signal for padding
signal p_1pad_di : std_logic_vector(G_W -1 downto 0); --! Internally selected signal for padding
signal input_data : std_logic_vector(G_W -1 downto 0); --! Additional select signal for padding
signal input_vbytes : std_logic_vector(G_W/8 -1 downto 0); --! Additional select signal for bytes size
signal input_ploc : std_logic_vector(G_W/8 -1 downto 0); --! Additional select signal for bytes size
--! Data block status register for external modules
signal len_a_reg : std_logic_vector(LEN_A_WIDTH -1 downto 0); --! Total authenticated data register
signal len_d_reg : std_logic_vector(LEN_D_WIDTH -1 downto 0); --! Total message data register --! Current block contains no message data (used for authenticated encryption data only mode)
--! Padding related signals
signal pad_loc_r : std_logic_vector(G_W/8 -1 downto 0);
--! Lookups
signal vbytes : std_logic_vector(G_W/8 -1 downto 0);
signal ploc : std_logic_vector(G_W/8 -1 downto 0);
begin
p_zpad_di <= pdi when sel_blank_pdi = '0' else (others => '0');
vbytes <= VBYTES_LOOKUP(conv_integer(size_dword));
ploc <= PLOC_LOOKUP(conv_integer(size_dword));
--! Datapath
procReg:
process( clk )
begin
if rising_edge( clk ) then
if rst = '1' then
reg_data <= (others => '0');
reg_exp_tag <= (others => '0');
len_a_reg <= (others => '0');
len_d_reg <= (others => '0');
reg_vbytes <= (others => '0');
else
--! === Public data
--! Data SIPO
if (en_data = '1') then
--! Handle different block size
if (G_W >= G_DBLK_SIZE) then
reg_data <= p_1pad_di(G_W-1 downto G_W-G_DBLK_SIZE);
reg_vbytes <= vbytes(G_W/8-1 downto G_W/8-G_DBLK_SIZE/8);
elsif ((G_DBLK_SIZE MOD G_W) = 0) then
reg_data <= reg_data(G_DBLK_SIZE-G_W-1 downto 0) & p_1pad_di;
reg_vbytes <= reg_vbytes(G_DBLK_SIZE/8-G_W/8-1 downto 0) & vbytes;
elsif ((G_DBLK_SIZE MOD G_W) /= 0) then
if (en_last_word = '0') then
reg_data (G_DBLK_SIZE-1 downto ( G_DBLK_SIZE MOD G_W)) <= reg_data (G_DBLK_SIZE- G_W -1 downto ( G_DBLK_SIZE MOD G_W)) & input_data;
reg_vbytes(G_DBLK_SIZE/8-1 downto ((G_DBLK_SIZE/8) MOD (G_W/8))) <= reg_vbytes(G_DBLK_SIZE/8-G_W/8-1 downto ((G_DBLK_SIZE/8) MOD (G_W/8))) & input_vbytes;
else
reg_data ((G_DBLK_SIZE mod G_W )-1 downto 0) <= input_data (G_W -1 downto G_W /2);
reg_vbytes(((G_DBLK_SIZE/8) mod (G_W/8))-1 downto 0) <= input_vbytes(G_W/8-1 downto (G_W/8)/2);
end if;
end if;
end if;
--! Tag SIPO
if (en_exp_tag = '1') then
--! Handle different block size
if (G_W >= G_TAG_SIZE) then
reg_exp_tag <= pdi(G_W-1 downto G_W-G_TAG_SIZE);
else
reg_exp_tag <= reg_exp_tag(G_TAG_SIZE-G_W-1 downto 0) & pdi;
end if;
end if;
--! === Secret data
--! Key SIPO
if (en_key = '1') then
--! Handle different I/O and key size
if (G_SW < G_KEY_SIZE) then
reg_key <= reg_key(G_KEY_SIZE-G_SW-1 downto 0) & sdi;
elsif G_SW = G_KEY_SIZE then
reg_key <= sdi;
end if;
end if;
--! Round Key SIPO
if (en_rdkey = '1') then
--! Handle different I/O and key size
if (G_SW < G_RDKEY_SIZE) then
reg_rdkey <= reg_rdkey(G_RDKEY_SIZE-G_SW-1 downto 0) & sdi;
elsif G_SW = G_RDKEY_SIZE then
reg_rdkey <= sdi;
end if;
end if;
--! === Status
--! Length registers
if (clr_len = '1') then
len_a_reg <= (others => '0');
len_d_reg <= (others => '0');
else
if (G_LOADLEN_ENABLE = 0) then
if (en_len_a = '1') then
len_a_reg <= len_a_reg + p_size;
end if;
if (en_len_d = '1') then
len_d_reg <= len_d_reg + p_size;
end if;
else
if (en_len_a_r = '1') then
if (G_W >= LEN_A_WIDTH) then
len_a_reg <= pdi(LEN_A_WIDTH-1 downto 0);
elsif ((LEN_A_WIDTH MOD G_W) = 0) then
len_a_reg <= len_a_reg(LEN_A_WIDTH-G_W-1 downto 0) & pdi;
else
if (en_len_last_r = '0') then
if (LEN_A_WIDTH/G_W > 1) then
len_a_reg(LEN_A_WIDTH-1 downto (LEN_A_WIDTH MOD G_W)) <= len_a_reg(LEN_A_WIDTH-G_W-1 downto (LEN_A_WIDTH MOD G_W)) & pdi;
else
len_a_reg(LEN_A_WIDTH-1 downto (LEN_A_WIDTH MOD G_W)) <= pdi;
end if;
else
len_a_reg((LEN_A_WIDTH MOD G_W)-1 downto 0) <= pdi(G_W-1 downto G_W-(LEN_A_WIDTH MOD G_W));
end if;
end if;
end if;
if (en_len_d_r = '1') then
if (G_W >= LEN_D_WIDTH) then
len_d_reg <= pdi(LEN_D_WIDTH-1 downto 0);
elsif ((LEN_D_WIDTH MOD G_W) = 0) then
len_d_reg <= len_d_reg(LEN_D_WIDTH-G_W-1 downto 0) & pdi;
else
if (en_len_last_r = '0') then
if (LEN_D_WIDTH/G_W > 1) then
len_d_reg(LEN_D_WIDTH-1 downto (LEN_D_WIDTH MOD G_W)) <= len_d_reg(LEN_D_WIDTH-G_W-1 downto (LEN_D_WIDTH MOD G_W)) & pdi;
else
len_d_reg(LEN_D_WIDTH-1 downto (LEN_D_WIDTH MOD G_W)) <= pdi;
end if;
else
len_d_reg((LEN_D_WIDTH MOD G_W)-1 downto 0) <= pdi(G_W-1 downto G_W-(LEN_D_WIDTH MOD G_W));
end if;
end if;
end if;
end if;
end if;
end if;
end if;
end process;
--! Public data size (based on the interface)
p_size <= pdi(CNTR_WIDTH -1 downto 0);
--! Output
len_a <= len_a_reg(G_CTR_AD_SIZE -1 downto 0);
len_d <= len_d_reg(G_CTR_D_SIZE -1 downto 0);
bdi <= reg_data;
exp_tag <= reg_exp_tag;
genKey: if (G_RDKEY_ENABLE = 0) generate
key <= reg_key;
end generate;
genRdKey: if (G_RDKEY_ENABLE = 1) generate
rdkey <= reg_rdkey;
end generate;
bdi_valid_bytes <= reg_vbytes;
bdi_pad_loc <= reg_ploc;
genNpub: if (G_NPUB_DISABLE = 0) generate
signal reg_npub : std_logic_vector(REG_NPUB_WIDTH -1 downto 0); --! Npub register
begin
npub <= reg_npub(REG_NPUB_WIDTH-1 downto REG_NPUB_WIDTH-G_NPUB_SIZE);
procReg:
process( clk )
begin
if rising_edge( clk ) then
if (rst = '1') then
reg_npub <= (others => '0');
elsif (en_npub = '1') then
if (G_W >= G_NPUB_SIZE) then
reg_npub <= pdi(G_W-1 downto G_W-REG_NPUB_WIDTH);
else
reg_npub <= reg_npub(REG_NPUB_WIDTH-G_W-1 downto 0) & pdi;
end if;
end if;
end if;
end process;
end generate;
genNsec: if (G_NSEC_ENABLE = 1) generate
signal reg_nsec : std_logic_vector(G_NSEC_SIZE -1 downto 0); --! Nsec register
begin
nsec <= reg_nsec;
procReg:
process( clk )
begin
if rising_edge( clk ) then
if (en_nsec = '1') then
if (G_W < G_NSEC_SIZE) then
reg_nsec <= reg_nsec(G_NSEC_SIZE-G_W-1 downto 0) & pdi;
else
reg_nsec <= pdi(G_W-1 downto G_W-G_NSEC_SIZE);
end if;
end if;
end if;
end process;
end generate;
--! ============ Special mode ===========
genPartial: if ((G_DBLK_SIZE mod G_W) > 0) generate
constant ZEROS : std_logic_vector(G_W-1 downto 0) := (others => '0');
signal padded_reg : std_logic_vector(G_W/2-1 downto 0);
signal dbytes_reg : std_logic_vector((G_W/8)/2-1 downto 0);
begin
process(clk)
begin
if rising_edge(clk) then
if (en_data = '1' and sel_blank_pdi = '0') then
padded_reg <= p_1pad_di(G_W/2-1 downto 0);
dbytes_reg <= vbytes((G_W/8)/2-1 downto 0);
end if;
end if;
end process;
genKeyak0: if G_KEYAK = 0 generate
with sel_input(2 downto 0) select
input_data <= p_1pad_di when "000",
p_1pad_di(G_W-1 downto G_W-G_W/2) & ZEROS(G_W-1 downto G_W-G_W/2) when "001",
padded_reg & p_1pad_di(G_W-1 downto G_W-G_W/2) when "010",
padded_reg & ZEROS(G_W-1 downto G_W-G_W/2) when "011",
(others => '0') when others;
with sel_input(2 downto 0) select
input_vbytes <= vbytes when "000",
vbytes(G_W/8-1 downto G_W/8-(G_W/8)/2) & ZEROS(G_W/8-1 downto G_W/8-(G_W/8)/2) when "001",
dbytes_reg & vbytes(G_W/8-1 downto G_W/8-(G_W/8)/2) when "010",
dbytes_reg & ZEROS(G_W/8-1 downto G_W/8-(G_W/8)/2) when "011",
(others => '0') when others;
end generate;
--! Special loading for Keyak
genKeyak1: if (G_KEYAK = 1 and G_W = 128 and G_DBLK_SIZE = 1344) generate
signal key_r : std_logic_vector(G_KEY_SIZE-1 downto 0);
begin
pKey: process(clk)
begin
if rising_edge(clk) then
if (key_updated = '1') then
key_r <= reg_key;
end if;
end if;
end process;
with sel_input(2 downto 0) select
input_data <= p_1pad_di when "000",
p_1pad_di(G_W-1 downto G_W-G_W/2) & ZEROS(G_W-1 downto G_W-G_W/2) when "001",
padded_reg & p_1pad_di(G_W-1 downto G_W-G_W/2) when "010",
padded_reg & ZEROS(G_W-1 downto G_W-G_W/2) when "011",
x"1E" & key_r(G_KEY_SIZE-1 downto 8) when "100",
key_r(7 downto 0) & x"01" & x"000000000000000000000000" & x"0100" when "101",
(others => '0') when others;
with sel_input(2 downto 0) select
input_vbytes <= vbytes when "000",
vbytes(G_W/8-1 downto G_W/8-(G_W/8)/2) & ZEROS(G_W/8-1 downto G_W/8-(G_W/8)/2) when "001",
dbytes_reg & vbytes(G_W/8-1 downto G_W/8-(G_W/8)/2) when "010",
dbytes_reg & ZEROS(G_W/8-1 downto G_W/8-(G_W/8)/2) when "011",
(others => '1') when "100",
(others => '1') when "101",
(others => '0') when others;
end generate;
end generate;
--! ============ Padding related logic =================
--! No padding unit
genPad0: if G_PAD = 0 generate
begin
p_1pad_di <= p_zpad_di;
end generate;
--! With padding unit
genPad1: if G_PAD = 1 generate
signal pad_loc_s : std_logic_vector(G_W/8 -1 downto 0);
signal ploc_reg : std_logic_vector((G_W/8)/2 -1 downto 0);
begin
--! No actual padding is performed. However, padding location is produced. Used this mode if bdi_pad_loc signal is required)
genPadMode0:
if G_PAD_STYLE = 0 generate
p_1pad_di <= p_zpad_di;
end generate;
--! Pad 10*
genPadMode1:
if G_PAD_STYLE = 1 generate
genLoop:
for i in 0 to G_W/8-1 generate
p_1pad_di(G_W-i*8-1) <= '1' when (pad_enable = '1' and pad_loc_r(i) = '1' ) else p_zpad_di(G_W-i*8-1);
p_1pad_di(G_W-i*8-2 downto G_W-i*8-8) <= p_zpad_di(G_W-i*8-2 downto G_W-i*8-8);
end generate;
end generate;
--! Padding mode for ICEPOLE
genPadMode2:
if G_PAD_STYLE = 2 generate
genLoop:
for i in 0 to G_W/8-1 generate
p_1pad_di(G_W-i*8-1 downto G_W-i*8-6) <= p_zpad_di(G_W-i*8-1 downto G_W-i*8-6);
p_1pad_di(G_W-i*8-7) <= '1' when (pad_enable = '1' and pad_loc_r(i) = '1' ) else p_zpad_di(G_W-i*8-7);
p_1pad_di(G_W-i*8-8) <= '1' when (pad_enable = '1' and pad_loc_r(i) = '1' and ((pad_eot = '1' and pad_type_ad = '1') or (pad_eot = '0' and pad_type_ad = '0'))) else p_zpad_di(G_W-i*8-8);
end generate;
end generate;
--! Padding mode for Keyak
genPadMode3:
if G_PAD_STYLE = 3 generate
genLoop:
for i in 0 to G_W/8-1 generate
p_1pad_di(G_W-i*8-1) <= p_zpad_di(G_W-i*8-1);
p_1pad_di(G_W-i*8-2) <= p_zpad_di(G_W-i*8-2);
p_1pad_di(G_W-i*8-3) <= p_zpad_di(G_W-i*8-3);
p_1pad_di(G_W-i*8-4) <= p_zpad_di(G_W-i*8-4);
p_1pad_di(G_W-i*8-5) <= p_zpad_di(G_W-i*8-5);
p_1pad_di(G_W-i*8-6) <= '1' when (pad_enable = '1' and pad_loc_r(i) = '1') else p_zpad_di(G_W-i*8-6);
p_1pad_di(G_W-i*8-7) <= '1' when (pad_enable = '1' and pad_loc_r(i) = '1' and ((pad_type_ad = '1' and pad_eoi = '0' and pad_eot = '1') or (pad_type_ad = '0' and pad_eot = '0'))) else p_zpad_di(G_W-i*8-7);
p_1pad_di(G_W-i*8-8) <= '1' when (pad_enable = '1' and pad_loc_r(i) = '1' and (pad_type_ad = '0' or (pad_eoi = '1' and pad_type_ad = '1'))) else p_zpad_di(G_W-i*8-8);
end generate;
end generate;
procReg: process(clk)
begin
if rising_edge(clk) then
if en_pad_loc = '1' then
pad_loc_r <= pad_loc_s;
end if;
if G_W >= G_DBLK_SIZE then
if (en_data = '1') then
if (pad_enable = '1') then
reg_ploc <= reverse_bit(pad_loc_r);
else
reg_ploc <= (others => '0');
end if;
end if;
elsif (G_DBLK_SIZE MOD G_W) = 0 then
if (en_data = '1') then
if (pad_enable = '1') then
reg_ploc <= reg_ploc(G_DBLK_SIZE/8-G_W/8-1 downto 0) & reverse_bit(pad_loc_s);
else
reg_ploc <= reg_ploc(G_DBLK_SIZE/8-G_W/8-1 downto 0) & ZWORD_BYTES(G_W/8-1 downto 0);
end if;
end if;
elsif (G_DBLK_SIZE MOD G_W) /= 0 then
if (rst = '1') then
reg_ploc <= (others => '0');
elsif (en_data = '1') then
ploc_reg <= pad_loc_s(((G_W/8)-1) downto ((G_W/8)/2));
if (en_last_word = '0') then
if (pad_enable = '1') then
reg_ploc(G_DBLK_SIZE/8-1 downto ((G_DBLK_SIZE/8) MOD (G_W/8))) <= reg_ploc(G_DBLK_SIZE/8-G_W/8-1 downto ((G_DBLK_SIZE/8) MOD (G_W/8))) & input_ploc;
else
reg_ploc(G_DBLK_SIZE/8-1 downto ((G_DBLK_SIZE/8) MOD (G_W/8))) <= reg_ploc(G_DBLK_SIZE/8-G_W/8-1 downto ((G_DBLK_SIZE/8) MOD (G_W/8))) & ZWORD_BYTES(G_W/8-1 downto 0);
end if;
else
if (pad_enable = '1') then
reg_ploc(((G_DBLK_SIZE/8) mod (G_W/8))-1 downto 0) <= input_ploc(G_W/8-1 downto (G_W/8)/2);
else
reg_ploc(((G_DBLK_SIZE/8) mod (G_W/8))-1 downto 0) <= (others => '0');
end if;
end if;
end if;
end if;
end if;
end process;
gKeyak0:
if ((G_KEYAK = 0) and ((G_DBLK_SIZE MOD G_W) /= 0)) generate
with sel_input(2 downto 0) select
input_ploc <= reverse_bit(pad_loc_s) when "000",
reverse_bit(pad_loc_s)(G_W/8-1 downto (G_W/8)/2) & ZWORD_BYTES(G_W/8-1 downto G_W/8-(G_W/8)/2) when "001",
reverse_bit(ploc_reg) & reverse_bit(pad_loc_s((G_W/8)/2-1 downto 0)) when "010",
reverse_bit(ploc_reg) & ZWORD_BYTES(G_W/8-1 downto G_W/8-(G_W/8)/2) when "011",
(others => '0') when others;
end generate;
gKeyak1:
if (G_KEYAK = 1) generate
with sel_input(2 downto 0) select
input_ploc <= reverse_bit(pad_loc_s) when "000",
reverse_bit(pad_loc_s)(G_W/8-1 downto (G_W/8)/2) & ZWORD_BYTES(G_W/8-1 downto G_W/8-(G_W/8)/2) when "001",
reverse_bit(ploc_reg) & reverse_bit(pad_loc_s((G_W/8)/2-1 downto 0)) when "010",
reverse_bit(ploc_reg) & ZWORD_BYTES(G_W/8-1 downto G_W/8-(G_W/8)/2) when "011",
(others => '0') when others;
-- with sel_input(2 downto 0) select
-- input_ploc <= reverse_bit(pad_loc_s) when "000",
-- reverse_bit(ploc_reg) & reverse_bit(pad_loc_s((G_W/8)/2-1 downto 0)) when "001",
-- reverse_bit(ploc_reg) & ZWORD_BYTES(G_W/8-1 downto G_W/8-(G_W/8)/2) when "010",
-- (others => '0') when others;
end generate;
--! Calculate the padding locatin
uBarrelShifter:
entity work.bshift(struct)
generic map (G_W => G_W/8, G_LOG2_W => LOG2_W, G_LEFT => 1, G_ROTATE => 0)
port map (ii => BSHIFT_INPUT, rtr => pad_shift, oo => pad_loc_s);
end generate;
end dataflow;
|
-------------------------------------------------------------------------------
--! @file PreProcessor_Datapath.vhd
--! @brief Datapath for the pre-processor
--! @project CAESAR Candidate Evaluation
--! @author Ekawat (ice) Homsirikamol
--! @copyright Copyright (c) 2015 Cryptographic Engineering Research Group
--! ECE Department, George Mason University Fairfax, VA, U.S.A.
--! All rights Reserved.
--! @license This project is released under the GNU Public License.
--! The license and distribution terms for this file may be
--! found in the file LICENSE in this distribution or at
--! http://www.gnu.org/licenses/gpl-3.0.txt
--! @note This is publicly available encryption source code that falls
--! under the License Exception TSU (Technology and software-
--! —unrestricted)
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use work.AEAD_pkg.all;
entity PreProcessor_Datapath is
generic (
G_W : integer := 64; --! Public data width (bits)
G_SW : integer := 64; --! Secret data width (bits)
G_CTR_AD_SIZE : integer := 64; --! Maximum size for the counter that keeps track of authenticated data
G_CTR_D_SIZE : integer := 64; --! Maximum size for the counter that keeps track of data
G_DBLK_SIZE : integer := 128; --! Block size (bits)
G_KEY_SIZE : integer := 128; --! Key size (bits)
G_KEYAK : integer := 0; --! Special input mode, used only for Keyak with G_W = 128 and G_DBLK_SIZE = 1344
G_NPUB_DISABLE : integer := 0; --! Disable Npub related port(s)
G_NPUB_SIZE : integer := 128; --! Npub width (bits)
G_NSEC_ENABLE : integer := 0; --! Enable nsec port
G_NSEC_SIZE : integer := 128; --! Nsec width (bits)
G_LOADLEN_ENABLE : integer := 0; --! Enable load length section
G_PAD : integer := 0; --! Enable padding
G_PAD_STYLE : integer := 1; --! Padding mode 0 = *10..., 1 = ICEPOLE's padding
G_RDKEY_ENABLE : integer := 0; --! Enable rdkey port (also disables key port)
G_RDKEY_SIZE : integer := 128; --! Roundkey size (bits)
G_TAG_SIZE : integer := 128 --! Tag size (bits)
);
port (
--! =================
--! External Signals
--! =================
--! Global signals
clk : in std_logic;
rst : in std_logic;
pdi : in std_logic_vector(G_W -1 downto 0); --! Public data
sdi : in std_logic_vector(G_SW -1 downto 0); --! Secret data
--! =================
--! Crypto Core Signals
--! =================
key : out std_logic_vector(G_KEY_SIZE -1 downto 0); --! Key data
rdkey : out std_logic_vector(G_RDKEY_SIZE -1 downto 0); --! Round key data
bdi : out std_logic_vector(G_DBLK_SIZE -1 downto 0); --! Block data
npub : out std_logic_vector(G_NPUB_SIZE -1 downto 0); --! Npub data
nsec : out std_logic_vector(G_NSEC_SIZE -1 downto 0); --! Nsec data
exp_tag : out std_logic_vector(G_TAG_SIZE -1 downto 0); --! Expected tag data
bdi_valid_bytes : out std_logic_vector(G_DBLK_SIZE/8 -1 downto 0);
bdi_pad_loc : out std_logic_vector(G_DBLK_SIZE/8 -1 downto 0);
len_a : out std_logic_vector(G_CTR_AD_SIZE -1 downto 0); --! Len of authenticated data in bytes (used for some algorithm)
len_d : out std_logic_vector(G_CTR_D_SIZE -1 downto 0); --! Len of data in bytes (used for some algorithm)
--! =================
--! Internal Signals
--! =================
--! Control signals
key_updated : in std_logic; --! (if G_DBLK_SIZE mod G_W > 0) Key updated signal (used only for situation when key is stored within input processor)
pad_shift : in std_logic_vector(log2_ceil(G_W/8) -1 downto 0);
en_data : in std_logic; --! Shift data SIPO
en_npub : in std_logic; --! Shift Npub SIPO
en_nsec : in std_logic; --! Shift Nsec SIPO
en_key : in std_logic; --! Shift key SIPO
en_rdkey : in std_logic; --! Shift round key SIPO
en_exp_tag : in std_logic; --! Shift expected tag SIPO
sel_blank_pdi : in std_logic; --! Select input data as blank (for filling in the remaining data within a block)
clr_len : in std_logic; --! Clear stored length (len_a and len_d)
en_len_a_r : in std_logic; --! Add authenticated data counter
en_len_d_r : in std_logic; --! Add data counter
en_len_last_r : in std_logic; --! Special signal for en_len_*_r
en_len_a : in std_logic; --! Add authenticated data counter (instant)
en_len_d : in std_logic; --! Add data counter (no)
size_dword : in std_logic_vector(log2_ceil(G_W/8) downto 0); --! Size of data word
en_last_word : in std_logic; --! Last word in a block
pad_eot : in std_logic; --! Padding is EOT
pad_eoi : in std_logic; --! Padding is EOI
pad_type_ad : in std_logic; --! Padding is AD
pad_enable : in std_logic; --! Enable padding signal (indicates that the current word requires padding)
en_pad_loc : in std_logic; --! Save the padding location into a register
sel_input : in std_logic_vector(3 -1 downto 0) --! (if G_DBLK_SIZE mod G_W > 0) Select input for m
);
end PreProcessor_Datapath;
architecture dataflow of PreProcessor_Datapath is
--! Constants declaration
constant LOG2_W : integer := log2_ceil(G_W/8); --! LOG_2(G_W)
constant LOG2_SW : integer := log2_ceil(G_SW/8); --! LOG_2(G_SW)
constant REG_NPUB_WIDTH : integer := (((G_NPUB_SIZE-1)/G_W)+1)*G_W; --! Calculate the width of Npub register
constant CNTR_WIDTH : integer := get_cntr_width(G_W); --! Calculate the length of p_size register
constant LEN_A_WIDTH : integer := maximum(CNTR_WIDTH, G_CTR_AD_SIZE);
constant LEN_D_WIDTH : integer := maximum(CNTR_WIDTH, G_CTR_D_SIZE);
constant CNT_DATA_WORDS : integer := (G_DBLK_SIZE+(G_W-1))/G_W; --! Calculate the number of words required for data (rounded up)
constant CNT_TAG_WORDS : integer := (G_DBLK_SIZE+(G_W-1))/G_W; --! Calculate the number of words required for tag (rounded up)
constant BSHIFT_INPUT : std_logic_vector(G_W/8 -1 downto 0) := std_logic_vector(to_unsigned(1,G_W/8));
constant OWORD_BYTES : std_logic_vector(G_DBLK_SIZE/8 -1 downto 0) := (others => '1'); --! The number of bytes in a word in ones.
constant ZWORD_BYTES : std_logic_vector(G_DBLK_SIZE/8 -1 downto 0) := (others => '0'); --! The number of bytes in a word in zeros.
function reverse_bit(aa: std_logic_vector) return std_logic_vector is
variable bb : std_logic_vector(aa'high downto aa'low);
begin
for i in aa'high downto aa'low loop
bb(i) := aa(aa'high-i);
end loop;
return bb;
end function reverse_bit;
type lookup_type is array (0 to ((G_W/8)*2-1)) of std_logic_vector(G_W/8-1 downto 0);
function getVbytesLookup(size: integer) return lookup_type is
variable ret : lookup_type;
begin
for i in 0 to ((size/8)*2-1) loop
if (i >= (size/8)) then
ret(i) := (others => '1');
elsif (i = 0) then
ret(i) := (others => '0');
else
ret(i)(size/8-1 downto size/8-i) := (others => '1');
ret(i)(size/8-i-1 downto 0) := (others => '0');
end if;
end loop;
return ret;
end function getVbytesLookup;
constant VBYTES_LOOKUP : lookup_type := getVbytesLookup(G_W);
--! ==================
--! Note: Current unused (keep this portion for later consideration)
function getPlocLookup(size: integer) return lookup_type is
variable ret : lookup_type;
begin
for i in 0 to ((size/8)*2-1) loop
if (i >= (size/8)) then
ret(i) := (others => '0');
else
ret(i) := (i => '1', others => '0');
end if;
end loop;
return ret;
end function getPlocLookup;
constant PLOC_LOOKUP : lookup_type := getPlocLookup(G_W);
--! End of note
--! ==================
--! Key related signals and registers
signal reg_key : std_logic_vector(G_KEY_SIZE -1 downto 0);
signal reg_rdkey : std_logic_vector(G_RDKEY_SIZE -1 downto 0);
--! Public data signals and registers
signal reg_data : std_logic_vector(G_DBLK_SIZE -1 downto 0); --! Data block register
signal reg_exp_tag : std_logic_vector(G_TAG_SIZE -1 downto 0); --! Tag register
signal reg_vbytes : std_logic_vector(G_DBLK_SIZE/8 -1 downto 0); --! Valid bytes register
signal reg_ploc : std_logic_vector(G_DBLK_SIZE/8 -1 downto 0); --! Pad location register
signal p_size : std_logic_vector(CNTR_WIDTH -1 downto 0); --! Public data segment size
signal p_zpad_di : std_logic_vector(G_W -1 downto 0); --! Internally selected signal for padding
signal p_1pad_di : std_logic_vector(G_W -1 downto 0); --! Internally selected signal for padding
signal input_data : std_logic_vector(G_W -1 downto 0); --! Additional select signal for padding
signal input_vbytes : std_logic_vector(G_W/8 -1 downto 0); --! Additional select signal for bytes size
signal input_ploc : std_logic_vector(G_W/8 -1 downto 0); --! Additional select signal for bytes size
--! Data block status register for external modules
signal len_a_reg : std_logic_vector(LEN_A_WIDTH -1 downto 0); --! Total authenticated data register
signal len_d_reg : std_logic_vector(LEN_D_WIDTH -1 downto 0); --! Total message data register --! Current block contains no message data (used for authenticated encryption data only mode)
--! Padding related signals
signal pad_loc_r : std_logic_vector(G_W/8 -1 downto 0);
--! Lookups
signal vbytes : std_logic_vector(G_W/8 -1 downto 0);
signal ploc : std_logic_vector(G_W/8 -1 downto 0);
begin
p_zpad_di <= pdi when sel_blank_pdi = '0' else (others => '0');
vbytes <= VBYTES_LOOKUP(conv_integer(size_dword));
ploc <= PLOC_LOOKUP(conv_integer(size_dword));
--! Datapath
procReg:
process( clk )
begin
if rising_edge( clk ) then
if rst = '1' then
reg_data <= (others => '0');
reg_exp_tag <= (others => '0');
len_a_reg <= (others => '0');
len_d_reg <= (others => '0');
reg_vbytes <= (others => '0');
else
--! === Public data
--! Data SIPO
if (en_data = '1') then
--! Handle different block size
if (G_W >= G_DBLK_SIZE) then
reg_data <= p_1pad_di(G_W-1 downto G_W-G_DBLK_SIZE);
reg_vbytes <= vbytes(G_W/8-1 downto G_W/8-G_DBLK_SIZE/8);
elsif ((G_DBLK_SIZE MOD G_W) = 0) then
reg_data <= reg_data(G_DBLK_SIZE-G_W-1 downto 0) & p_1pad_di;
reg_vbytes <= reg_vbytes(G_DBLK_SIZE/8-G_W/8-1 downto 0) & vbytes;
elsif ((G_DBLK_SIZE MOD G_W) /= 0) then
if (en_last_word = '0') then
reg_data (G_DBLK_SIZE-1 downto ( G_DBLK_SIZE MOD G_W)) <= reg_data (G_DBLK_SIZE- G_W -1 downto ( G_DBLK_SIZE MOD G_W)) & input_data;
reg_vbytes(G_DBLK_SIZE/8-1 downto ((G_DBLK_SIZE/8) MOD (G_W/8))) <= reg_vbytes(G_DBLK_SIZE/8-G_W/8-1 downto ((G_DBLK_SIZE/8) MOD (G_W/8))) & input_vbytes;
else
reg_data ((G_DBLK_SIZE mod G_W )-1 downto 0) <= input_data (G_W -1 downto G_W /2);
reg_vbytes(((G_DBLK_SIZE/8) mod (G_W/8))-1 downto 0) <= input_vbytes(G_W/8-1 downto (G_W/8)/2);
end if;
end if;
end if;
--! Tag SIPO
if (en_exp_tag = '1') then
--! Handle different block size
if (G_W >= G_TAG_SIZE) then
reg_exp_tag <= pdi(G_W-1 downto G_W-G_TAG_SIZE);
else
reg_exp_tag <= reg_exp_tag(G_TAG_SIZE-G_W-1 downto 0) & pdi;
end if;
end if;
--! === Secret data
--! Key SIPO
if (en_key = '1') then
--! Handle different I/O and key size
if (G_SW < G_KEY_SIZE) then
reg_key <= reg_key(G_KEY_SIZE-G_SW-1 downto 0) & sdi;
elsif G_SW = G_KEY_SIZE then
reg_key <= sdi;
end if;
end if;
--! Round Key SIPO
if (en_rdkey = '1') then
--! Handle different I/O and key size
if (G_SW < G_RDKEY_SIZE) then
reg_rdkey <= reg_rdkey(G_RDKEY_SIZE-G_SW-1 downto 0) & sdi;
elsif G_SW = G_RDKEY_SIZE then
reg_rdkey <= sdi;
end if;
end if;
--! === Status
--! Length registers
if (clr_len = '1') then
len_a_reg <= (others => '0');
len_d_reg <= (others => '0');
else
if (G_LOADLEN_ENABLE = 0) then
if (en_len_a = '1') then
len_a_reg <= len_a_reg + p_size;
end if;
if (en_len_d = '1') then
len_d_reg <= len_d_reg + p_size;
end if;
else
if (en_len_a_r = '1') then
if (G_W >= LEN_A_WIDTH) then
len_a_reg <= pdi(LEN_A_WIDTH-1 downto 0);
elsif ((LEN_A_WIDTH MOD G_W) = 0) then
len_a_reg <= len_a_reg(LEN_A_WIDTH-G_W-1 downto 0) & pdi;
else
if (en_len_last_r = '0') then
if (LEN_A_WIDTH/G_W > 1) then
len_a_reg(LEN_A_WIDTH-1 downto (LEN_A_WIDTH MOD G_W)) <= len_a_reg(LEN_A_WIDTH-G_W-1 downto (LEN_A_WIDTH MOD G_W)) & pdi;
else
len_a_reg(LEN_A_WIDTH-1 downto (LEN_A_WIDTH MOD G_W)) <= pdi;
end if;
else
len_a_reg((LEN_A_WIDTH MOD G_W)-1 downto 0) <= pdi(G_W-1 downto G_W-(LEN_A_WIDTH MOD G_W));
end if;
end if;
end if;
if (en_len_d_r = '1') then
if (G_W >= LEN_D_WIDTH) then
len_d_reg <= pdi(LEN_D_WIDTH-1 downto 0);
elsif ((LEN_D_WIDTH MOD G_W) = 0) then
len_d_reg <= len_d_reg(LEN_D_WIDTH-G_W-1 downto 0) & pdi;
else
if (en_len_last_r = '0') then
if (LEN_D_WIDTH/G_W > 1) then
len_d_reg(LEN_D_WIDTH-1 downto (LEN_D_WIDTH MOD G_W)) <= len_d_reg(LEN_D_WIDTH-G_W-1 downto (LEN_D_WIDTH MOD G_W)) & pdi;
else
len_d_reg(LEN_D_WIDTH-1 downto (LEN_D_WIDTH MOD G_W)) <= pdi;
end if;
else
len_d_reg((LEN_D_WIDTH MOD G_W)-1 downto 0) <= pdi(G_W-1 downto G_W-(LEN_D_WIDTH MOD G_W));
end if;
end if;
end if;
end if;
end if;
end if;
end if;
end process;
--! Public data size (based on the interface)
p_size <= pdi(CNTR_WIDTH -1 downto 0);
--! Output
len_a <= len_a_reg(G_CTR_AD_SIZE -1 downto 0);
len_d <= len_d_reg(G_CTR_D_SIZE -1 downto 0);
bdi <= reg_data;
exp_tag <= reg_exp_tag;
genKey: if (G_RDKEY_ENABLE = 0) generate
key <= reg_key;
end generate;
genRdKey: if (G_RDKEY_ENABLE = 1) generate
rdkey <= reg_rdkey;
end generate;
bdi_valid_bytes <= reg_vbytes;
bdi_pad_loc <= reg_ploc;
genNpub: if (G_NPUB_DISABLE = 0) generate
signal reg_npub : std_logic_vector(REG_NPUB_WIDTH -1 downto 0); --! Npub register
begin
npub <= reg_npub(REG_NPUB_WIDTH-1 downto REG_NPUB_WIDTH-G_NPUB_SIZE);
procReg:
process( clk )
begin
if rising_edge( clk ) then
if (rst = '1') then
reg_npub <= (others => '0');
elsif (en_npub = '1') then
if (G_W >= G_NPUB_SIZE) then
reg_npub <= pdi(G_W-1 downto G_W-REG_NPUB_WIDTH);
else
reg_npub <= reg_npub(REG_NPUB_WIDTH-G_W-1 downto 0) & pdi;
end if;
end if;
end if;
end process;
end generate;
genNsec: if (G_NSEC_ENABLE = 1) generate
signal reg_nsec : std_logic_vector(G_NSEC_SIZE -1 downto 0); --! Nsec register
begin
nsec <= reg_nsec;
procReg:
process( clk )
begin
if rising_edge( clk ) then
if (en_nsec = '1') then
if (G_W < G_NSEC_SIZE) then
reg_nsec <= reg_nsec(G_NSEC_SIZE-G_W-1 downto 0) & pdi;
else
reg_nsec <= pdi(G_W-1 downto G_W-G_NSEC_SIZE);
end if;
end if;
end if;
end process;
end generate;
--! ============ Special mode ===========
genPartial: if ((G_DBLK_SIZE mod G_W) > 0) generate
constant ZEROS : std_logic_vector(G_W-1 downto 0) := (others => '0');
signal padded_reg : std_logic_vector(G_W/2-1 downto 0);
signal dbytes_reg : std_logic_vector((G_W/8)/2-1 downto 0);
begin
process(clk)
begin
if rising_edge(clk) then
if (en_data = '1' and sel_blank_pdi = '0') then
padded_reg <= p_1pad_di(G_W/2-1 downto 0);
dbytes_reg <= vbytes((G_W/8)/2-1 downto 0);
end if;
end if;
end process;
genKeyak0: if G_KEYAK = 0 generate
with sel_input(2 downto 0) select
input_data <= p_1pad_di when "000",
p_1pad_di(G_W-1 downto G_W-G_W/2) & ZEROS(G_W-1 downto G_W-G_W/2) when "001",
padded_reg & p_1pad_di(G_W-1 downto G_W-G_W/2) when "010",
padded_reg & ZEROS(G_W-1 downto G_W-G_W/2) when "011",
(others => '0') when others;
with sel_input(2 downto 0) select
input_vbytes <= vbytes when "000",
vbytes(G_W/8-1 downto G_W/8-(G_W/8)/2) & ZEROS(G_W/8-1 downto G_W/8-(G_W/8)/2) when "001",
dbytes_reg & vbytes(G_W/8-1 downto G_W/8-(G_W/8)/2) when "010",
dbytes_reg & ZEROS(G_W/8-1 downto G_W/8-(G_W/8)/2) when "011",
(others => '0') when others;
end generate;
--! Special loading for Keyak
genKeyak1: if (G_KEYAK = 1 and G_W = 128 and G_DBLK_SIZE = 1344) generate
signal key_r : std_logic_vector(G_KEY_SIZE-1 downto 0);
begin
pKey: process(clk)
begin
if rising_edge(clk) then
if (key_updated = '1') then
key_r <= reg_key;
end if;
end if;
end process;
with sel_input(2 downto 0) select
input_data <= p_1pad_di when "000",
p_1pad_di(G_W-1 downto G_W-G_W/2) & ZEROS(G_W-1 downto G_W-G_W/2) when "001",
padded_reg & p_1pad_di(G_W-1 downto G_W-G_W/2) when "010",
padded_reg & ZEROS(G_W-1 downto G_W-G_W/2) when "011",
x"1E" & key_r(G_KEY_SIZE-1 downto 8) when "100",
key_r(7 downto 0) & x"01" & x"000000000000000000000000" & x"0100" when "101",
(others => '0') when others;
with sel_input(2 downto 0) select
input_vbytes <= vbytes when "000",
vbytes(G_W/8-1 downto G_W/8-(G_W/8)/2) & ZEROS(G_W/8-1 downto G_W/8-(G_W/8)/2) when "001",
dbytes_reg & vbytes(G_W/8-1 downto G_W/8-(G_W/8)/2) when "010",
dbytes_reg & ZEROS(G_W/8-1 downto G_W/8-(G_W/8)/2) when "011",
(others => '1') when "100",
(others => '1') when "101",
(others => '0') when others;
end generate;
end generate;
--! ============ Padding related logic =================
--! No padding unit
genPad0: if G_PAD = 0 generate
begin
p_1pad_di <= p_zpad_di;
end generate;
--! With padding unit
genPad1: if G_PAD = 1 generate
signal pad_loc_s : std_logic_vector(G_W/8 -1 downto 0);
signal ploc_reg : std_logic_vector((G_W/8)/2 -1 downto 0);
begin
--! No actual padding is performed. However, padding location is produced. Used this mode if bdi_pad_loc signal is required)
genPadMode0:
if G_PAD_STYLE = 0 generate
p_1pad_di <= p_zpad_di;
end generate;
--! Pad 10*
genPadMode1:
if G_PAD_STYLE = 1 generate
genLoop:
for i in 0 to G_W/8-1 generate
p_1pad_di(G_W-i*8-1) <= '1' when (pad_enable = '1' and pad_loc_r(i) = '1' ) else p_zpad_di(G_W-i*8-1);
p_1pad_di(G_W-i*8-2 downto G_W-i*8-8) <= p_zpad_di(G_W-i*8-2 downto G_W-i*8-8);
end generate;
end generate;
--! Padding mode for ICEPOLE
genPadMode2:
if G_PAD_STYLE = 2 generate
genLoop:
for i in 0 to G_W/8-1 generate
p_1pad_di(G_W-i*8-1 downto G_W-i*8-6) <= p_zpad_di(G_W-i*8-1 downto G_W-i*8-6);
p_1pad_di(G_W-i*8-7) <= '1' when (pad_enable = '1' and pad_loc_r(i) = '1' ) else p_zpad_di(G_W-i*8-7);
p_1pad_di(G_W-i*8-8) <= '1' when (pad_enable = '1' and pad_loc_r(i) = '1' and ((pad_eot = '1' and pad_type_ad = '1') or (pad_eot = '0' and pad_type_ad = '0'))) else p_zpad_di(G_W-i*8-8);
end generate;
end generate;
--! Padding mode for Keyak
genPadMode3:
if G_PAD_STYLE = 3 generate
genLoop:
for i in 0 to G_W/8-1 generate
p_1pad_di(G_W-i*8-1) <= p_zpad_di(G_W-i*8-1);
p_1pad_di(G_W-i*8-2) <= p_zpad_di(G_W-i*8-2);
p_1pad_di(G_W-i*8-3) <= p_zpad_di(G_W-i*8-3);
p_1pad_di(G_W-i*8-4) <= p_zpad_di(G_W-i*8-4);
p_1pad_di(G_W-i*8-5) <= p_zpad_di(G_W-i*8-5);
p_1pad_di(G_W-i*8-6) <= '1' when (pad_enable = '1' and pad_loc_r(i) = '1') else p_zpad_di(G_W-i*8-6);
p_1pad_di(G_W-i*8-7) <= '1' when (pad_enable = '1' and pad_loc_r(i) = '1' and ((pad_type_ad = '1' and pad_eoi = '0' and pad_eot = '1') or (pad_type_ad = '0' and pad_eot = '0'))) else p_zpad_di(G_W-i*8-7);
p_1pad_di(G_W-i*8-8) <= '1' when (pad_enable = '1' and pad_loc_r(i) = '1' and (pad_type_ad = '0' or (pad_eoi = '1' and pad_type_ad = '1'))) else p_zpad_di(G_W-i*8-8);
end generate;
end generate;
procReg: process(clk)
begin
if rising_edge(clk) then
if en_pad_loc = '1' then
pad_loc_r <= pad_loc_s;
end if;
if G_W >= G_DBLK_SIZE then
if (en_data = '1') then
if (pad_enable = '1') then
reg_ploc <= reverse_bit(pad_loc_r);
else
reg_ploc <= (others => '0');
end if;
end if;
elsif (G_DBLK_SIZE MOD G_W) = 0 then
if (en_data = '1') then
if (pad_enable = '1') then
reg_ploc <= reg_ploc(G_DBLK_SIZE/8-G_W/8-1 downto 0) & reverse_bit(pad_loc_s);
else
reg_ploc <= reg_ploc(G_DBLK_SIZE/8-G_W/8-1 downto 0) & ZWORD_BYTES(G_W/8-1 downto 0);
end if;
end if;
elsif (G_DBLK_SIZE MOD G_W) /= 0 then
if (rst = '1') then
reg_ploc <= (others => '0');
elsif (en_data = '1') then
ploc_reg <= pad_loc_s(((G_W/8)-1) downto ((G_W/8)/2));
if (en_last_word = '0') then
if (pad_enable = '1') then
reg_ploc(G_DBLK_SIZE/8-1 downto ((G_DBLK_SIZE/8) MOD (G_W/8))) <= reg_ploc(G_DBLK_SIZE/8-G_W/8-1 downto ((G_DBLK_SIZE/8) MOD (G_W/8))) & input_ploc;
else
reg_ploc(G_DBLK_SIZE/8-1 downto ((G_DBLK_SIZE/8) MOD (G_W/8))) <= reg_ploc(G_DBLK_SIZE/8-G_W/8-1 downto ((G_DBLK_SIZE/8) MOD (G_W/8))) & ZWORD_BYTES(G_W/8-1 downto 0);
end if;
else
if (pad_enable = '1') then
reg_ploc(((G_DBLK_SIZE/8) mod (G_W/8))-1 downto 0) <= input_ploc(G_W/8-1 downto (G_W/8)/2);
else
reg_ploc(((G_DBLK_SIZE/8) mod (G_W/8))-1 downto 0) <= (others => '0');
end if;
end if;
end if;
end if;
end if;
end process;
gKeyak0:
if ((G_KEYAK = 0) and ((G_DBLK_SIZE MOD G_W) /= 0)) generate
with sel_input(2 downto 0) select
input_ploc <= reverse_bit(pad_loc_s) when "000",
reverse_bit(pad_loc_s)(G_W/8-1 downto (G_W/8)/2) & ZWORD_BYTES(G_W/8-1 downto G_W/8-(G_W/8)/2) when "001",
reverse_bit(ploc_reg) & reverse_bit(pad_loc_s((G_W/8)/2-1 downto 0)) when "010",
reverse_bit(ploc_reg) & ZWORD_BYTES(G_W/8-1 downto G_W/8-(G_W/8)/2) when "011",
(others => '0') when others;
end generate;
gKeyak1:
if (G_KEYAK = 1) generate
with sel_input(2 downto 0) select
input_ploc <= reverse_bit(pad_loc_s) when "000",
reverse_bit(pad_loc_s)(G_W/8-1 downto (G_W/8)/2) & ZWORD_BYTES(G_W/8-1 downto G_W/8-(G_W/8)/2) when "001",
reverse_bit(ploc_reg) & reverse_bit(pad_loc_s((G_W/8)/2-1 downto 0)) when "010",
reverse_bit(ploc_reg) & ZWORD_BYTES(G_W/8-1 downto G_W/8-(G_W/8)/2) when "011",
(others => '0') when others;
-- with sel_input(2 downto 0) select
-- input_ploc <= reverse_bit(pad_loc_s) when "000",
-- reverse_bit(ploc_reg) & reverse_bit(pad_loc_s((G_W/8)/2-1 downto 0)) when "001",
-- reverse_bit(ploc_reg) & ZWORD_BYTES(G_W/8-1 downto G_W/8-(G_W/8)/2) when "010",
-- (others => '0') when others;
end generate;
--! Calculate the padding locatin
uBarrelShifter:
entity work.bshift(struct)
generic map (G_W => G_W/8, G_LOG2_W => LOG2_W, G_LEFT => 1, G_ROTATE => 0)
port map (ii => BSHIFT_INPUT, rtr => pad_shift, oo => pad_loc_s);
end generate;
end dataflow;
|
-------------------------------------------------------------------------------
--! @file PreProcessor_Datapath.vhd
--! @brief Datapath for the pre-processor
--! @project CAESAR Candidate Evaluation
--! @author Ekawat (ice) Homsirikamol
--! @copyright Copyright (c) 2015 Cryptographic Engineering Research Group
--! ECE Department, George Mason University Fairfax, VA, U.S.A.
--! All rights Reserved.
--! @license This project is released under the GNU Public License.
--! The license and distribution terms for this file may be
--! found in the file LICENSE in this distribution or at
--! http://www.gnu.org/licenses/gpl-3.0.txt
--! @note This is publicly available encryption source code that falls
--! under the License Exception TSU (Technology and software-
--! —unrestricted)
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use work.AEAD_pkg.all;
entity PreProcessor_Datapath is
generic (
G_W : integer := 64; --! Public data width (bits)
G_SW : integer := 64; --! Secret data width (bits)
G_CTR_AD_SIZE : integer := 64; --! Maximum size for the counter that keeps track of authenticated data
G_CTR_D_SIZE : integer := 64; --! Maximum size for the counter that keeps track of data
G_DBLK_SIZE : integer := 128; --! Block size (bits)
G_KEY_SIZE : integer := 128; --! Key size (bits)
G_KEYAK : integer := 0; --! Special input mode, used only for Keyak with G_W = 128 and G_DBLK_SIZE = 1344
G_NPUB_DISABLE : integer := 0; --! Disable Npub related port(s)
G_NPUB_SIZE : integer := 128; --! Npub width (bits)
G_NSEC_ENABLE : integer := 0; --! Enable nsec port
G_NSEC_SIZE : integer := 128; --! Nsec width (bits)
G_LOADLEN_ENABLE : integer := 0; --! Enable load length section
G_PAD : integer := 0; --! Enable padding
G_PAD_STYLE : integer := 1; --! Padding mode 0 = *10..., 1 = ICEPOLE's padding
G_RDKEY_ENABLE : integer := 0; --! Enable rdkey port (also disables key port)
G_RDKEY_SIZE : integer := 128; --! Roundkey size (bits)
G_TAG_SIZE : integer := 128 --! Tag size (bits)
);
port (
--! =================
--! External Signals
--! =================
--! Global signals
clk : in std_logic;
rst : in std_logic;
pdi : in std_logic_vector(G_W -1 downto 0); --! Public data
sdi : in std_logic_vector(G_SW -1 downto 0); --! Secret data
--! =================
--! Crypto Core Signals
--! =================
key : out std_logic_vector(G_KEY_SIZE -1 downto 0); --! Key data
rdkey : out std_logic_vector(G_RDKEY_SIZE -1 downto 0); --! Round key data
bdi : out std_logic_vector(G_DBLK_SIZE -1 downto 0); --! Block data
npub : out std_logic_vector(G_NPUB_SIZE -1 downto 0); --! Npub data
nsec : out std_logic_vector(G_NSEC_SIZE -1 downto 0); --! Nsec data
exp_tag : out std_logic_vector(G_TAG_SIZE -1 downto 0); --! Expected tag data
bdi_valid_bytes : out std_logic_vector(G_DBLK_SIZE/8 -1 downto 0);
bdi_pad_loc : out std_logic_vector(G_DBLK_SIZE/8 -1 downto 0);
len_a : out std_logic_vector(G_CTR_AD_SIZE -1 downto 0); --! Len of authenticated data in bytes (used for some algorithm)
len_d : out std_logic_vector(G_CTR_D_SIZE -1 downto 0); --! Len of data in bytes (used for some algorithm)
--! =================
--! Internal Signals
--! =================
--! Control signals
key_updated : in std_logic; --! (if G_DBLK_SIZE mod G_W > 0) Key updated signal (used only for situation when key is stored within input processor)
pad_shift : in std_logic_vector(log2_ceil(G_W/8) -1 downto 0);
en_data : in std_logic; --! Shift data SIPO
en_npub : in std_logic; --! Shift Npub SIPO
en_nsec : in std_logic; --! Shift Nsec SIPO
en_key : in std_logic; --! Shift key SIPO
en_rdkey : in std_logic; --! Shift round key SIPO
en_exp_tag : in std_logic; --! Shift expected tag SIPO
sel_blank_pdi : in std_logic; --! Select input data as blank (for filling in the remaining data within a block)
clr_len : in std_logic; --! Clear stored length (len_a and len_d)
en_len_a_r : in std_logic; --! Add authenticated data counter
en_len_d_r : in std_logic; --! Add data counter
en_len_last_r : in std_logic; --! Special signal for en_len_*_r
en_len_a : in std_logic; --! Add authenticated data counter (instant)
en_len_d : in std_logic; --! Add data counter (no)
size_dword : in std_logic_vector(log2_ceil(G_W/8) downto 0); --! Size of data word
en_last_word : in std_logic; --! Last word in a block
pad_eot : in std_logic; --! Padding is EOT
pad_eoi : in std_logic; --! Padding is EOI
pad_type_ad : in std_logic; --! Padding is AD
pad_enable : in std_logic; --! Enable padding signal (indicates that the current word requires padding)
en_pad_loc : in std_logic; --! Save the padding location into a register
sel_input : in std_logic_vector(3 -1 downto 0) --! (if G_DBLK_SIZE mod G_W > 0) Select input for m
);
end PreProcessor_Datapath;
architecture dataflow of PreProcessor_Datapath is
--! Constants declaration
constant LOG2_W : integer := log2_ceil(G_W/8); --! LOG_2(G_W)
constant LOG2_SW : integer := log2_ceil(G_SW/8); --! LOG_2(G_SW)
constant REG_NPUB_WIDTH : integer := (((G_NPUB_SIZE-1)/G_W)+1)*G_W; --! Calculate the width of Npub register
constant CNTR_WIDTH : integer := get_cntr_width(G_W); --! Calculate the length of p_size register
constant LEN_A_WIDTH : integer := maximum(CNTR_WIDTH, G_CTR_AD_SIZE);
constant LEN_D_WIDTH : integer := maximum(CNTR_WIDTH, G_CTR_D_SIZE);
constant CNT_DATA_WORDS : integer := (G_DBLK_SIZE+(G_W-1))/G_W; --! Calculate the number of words required for data (rounded up)
constant CNT_TAG_WORDS : integer := (G_DBLK_SIZE+(G_W-1))/G_W; --! Calculate the number of words required for tag (rounded up)
constant BSHIFT_INPUT : std_logic_vector(G_W/8 -1 downto 0) := std_logic_vector(to_unsigned(1,G_W/8));
constant OWORD_BYTES : std_logic_vector(G_DBLK_SIZE/8 -1 downto 0) := (others => '1'); --! The number of bytes in a word in ones.
constant ZWORD_BYTES : std_logic_vector(G_DBLK_SIZE/8 -1 downto 0) := (others => '0'); --! The number of bytes in a word in zeros.
function reverse_bit(aa: std_logic_vector) return std_logic_vector is
variable bb : std_logic_vector(aa'high downto aa'low);
begin
for i in aa'high downto aa'low loop
bb(i) := aa(aa'high-i);
end loop;
return bb;
end function reverse_bit;
type lookup_type is array (0 to ((G_W/8)*2-1)) of std_logic_vector(G_W/8-1 downto 0);
function getVbytesLookup(size: integer) return lookup_type is
variable ret : lookup_type;
begin
for i in 0 to ((size/8)*2-1) loop
if (i >= (size/8)) then
ret(i) := (others => '1');
elsif (i = 0) then
ret(i) := (others => '0');
else
ret(i)(size/8-1 downto size/8-i) := (others => '1');
ret(i)(size/8-i-1 downto 0) := (others => '0');
end if;
end loop;
return ret;
end function getVbytesLookup;
constant VBYTES_LOOKUP : lookup_type := getVbytesLookup(G_W);
--! ==================
--! Note: Current unused (keep this portion for later consideration)
function getPlocLookup(size: integer) return lookup_type is
variable ret : lookup_type;
begin
for i in 0 to ((size/8)*2-1) loop
if (i >= (size/8)) then
ret(i) := (others => '0');
else
ret(i) := (i => '1', others => '0');
end if;
end loop;
return ret;
end function getPlocLookup;
constant PLOC_LOOKUP : lookup_type := getPlocLookup(G_W);
--! End of note
--! ==================
--! Key related signals and registers
signal reg_key : std_logic_vector(G_KEY_SIZE -1 downto 0);
signal reg_rdkey : std_logic_vector(G_RDKEY_SIZE -1 downto 0);
--! Public data signals and registers
signal reg_data : std_logic_vector(G_DBLK_SIZE -1 downto 0); --! Data block register
signal reg_exp_tag : std_logic_vector(G_TAG_SIZE -1 downto 0); --! Tag register
signal reg_vbytes : std_logic_vector(G_DBLK_SIZE/8 -1 downto 0); --! Valid bytes register
signal reg_ploc : std_logic_vector(G_DBLK_SIZE/8 -1 downto 0); --! Pad location register
signal p_size : std_logic_vector(CNTR_WIDTH -1 downto 0); --! Public data segment size
signal p_zpad_di : std_logic_vector(G_W -1 downto 0); --! Internally selected signal for padding
signal p_1pad_di : std_logic_vector(G_W -1 downto 0); --! Internally selected signal for padding
signal input_data : std_logic_vector(G_W -1 downto 0); --! Additional select signal for padding
signal input_vbytes : std_logic_vector(G_W/8 -1 downto 0); --! Additional select signal for bytes size
signal input_ploc : std_logic_vector(G_W/8 -1 downto 0); --! Additional select signal for bytes size
--! Data block status register for external modules
signal len_a_reg : std_logic_vector(LEN_A_WIDTH -1 downto 0); --! Total authenticated data register
signal len_d_reg : std_logic_vector(LEN_D_WIDTH -1 downto 0); --! Total message data register --! Current block contains no message data (used for authenticated encryption data only mode)
--! Padding related signals
signal pad_loc_r : std_logic_vector(G_W/8 -1 downto 0);
--! Lookups
signal vbytes : std_logic_vector(G_W/8 -1 downto 0);
signal ploc : std_logic_vector(G_W/8 -1 downto 0);
begin
p_zpad_di <= pdi when sel_blank_pdi = '0' else (others => '0');
vbytes <= VBYTES_LOOKUP(conv_integer(size_dword));
ploc <= PLOC_LOOKUP(conv_integer(size_dword));
--! Datapath
procReg:
process( clk )
begin
if rising_edge( clk ) then
if rst = '1' then
reg_data <= (others => '0');
reg_exp_tag <= (others => '0');
len_a_reg <= (others => '0');
len_d_reg <= (others => '0');
reg_vbytes <= (others => '0');
else
--! === Public data
--! Data SIPO
if (en_data = '1') then
--! Handle different block size
if (G_W >= G_DBLK_SIZE) then
reg_data <= p_1pad_di(G_W-1 downto G_W-G_DBLK_SIZE);
reg_vbytes <= vbytes(G_W/8-1 downto G_W/8-G_DBLK_SIZE/8);
elsif ((G_DBLK_SIZE MOD G_W) = 0) then
reg_data <= reg_data(G_DBLK_SIZE-G_W-1 downto 0) & p_1pad_di;
reg_vbytes <= reg_vbytes(G_DBLK_SIZE/8-G_W/8-1 downto 0) & vbytes;
elsif ((G_DBLK_SIZE MOD G_W) /= 0) then
if (en_last_word = '0') then
reg_data (G_DBLK_SIZE-1 downto ( G_DBLK_SIZE MOD G_W)) <= reg_data (G_DBLK_SIZE- G_W -1 downto ( G_DBLK_SIZE MOD G_W)) & input_data;
reg_vbytes(G_DBLK_SIZE/8-1 downto ((G_DBLK_SIZE/8) MOD (G_W/8))) <= reg_vbytes(G_DBLK_SIZE/8-G_W/8-1 downto ((G_DBLK_SIZE/8) MOD (G_W/8))) & input_vbytes;
else
reg_data ((G_DBLK_SIZE mod G_W )-1 downto 0) <= input_data (G_W -1 downto G_W /2);
reg_vbytes(((G_DBLK_SIZE/8) mod (G_W/8))-1 downto 0) <= input_vbytes(G_W/8-1 downto (G_W/8)/2);
end if;
end if;
end if;
--! Tag SIPO
if (en_exp_tag = '1') then
--! Handle different block size
if (G_W >= G_TAG_SIZE) then
reg_exp_tag <= pdi(G_W-1 downto G_W-G_TAG_SIZE);
else
reg_exp_tag <= reg_exp_tag(G_TAG_SIZE-G_W-1 downto 0) & pdi;
end if;
end if;
--! === Secret data
--! Key SIPO
if (en_key = '1') then
--! Handle different I/O and key size
if (G_SW < G_KEY_SIZE) then
reg_key <= reg_key(G_KEY_SIZE-G_SW-1 downto 0) & sdi;
elsif G_SW = G_KEY_SIZE then
reg_key <= sdi;
end if;
end if;
--! Round Key SIPO
if (en_rdkey = '1') then
--! Handle different I/O and key size
if (G_SW < G_RDKEY_SIZE) then
reg_rdkey <= reg_rdkey(G_RDKEY_SIZE-G_SW-1 downto 0) & sdi;
elsif G_SW = G_RDKEY_SIZE then
reg_rdkey <= sdi;
end if;
end if;
--! === Status
--! Length registers
if (clr_len = '1') then
len_a_reg <= (others => '0');
len_d_reg <= (others => '0');
else
if (G_LOADLEN_ENABLE = 0) then
if (en_len_a = '1') then
len_a_reg <= len_a_reg + p_size;
end if;
if (en_len_d = '1') then
len_d_reg <= len_d_reg + p_size;
end if;
else
if (en_len_a_r = '1') then
if (G_W >= LEN_A_WIDTH) then
len_a_reg <= pdi(LEN_A_WIDTH-1 downto 0);
elsif ((LEN_A_WIDTH MOD G_W) = 0) then
len_a_reg <= len_a_reg(LEN_A_WIDTH-G_W-1 downto 0) & pdi;
else
if (en_len_last_r = '0') then
if (LEN_A_WIDTH/G_W > 1) then
len_a_reg(LEN_A_WIDTH-1 downto (LEN_A_WIDTH MOD G_W)) <= len_a_reg(LEN_A_WIDTH-G_W-1 downto (LEN_A_WIDTH MOD G_W)) & pdi;
else
len_a_reg(LEN_A_WIDTH-1 downto (LEN_A_WIDTH MOD G_W)) <= pdi;
end if;
else
len_a_reg((LEN_A_WIDTH MOD G_W)-1 downto 0) <= pdi(G_W-1 downto G_W-(LEN_A_WIDTH MOD G_W));
end if;
end if;
end if;
if (en_len_d_r = '1') then
if (G_W >= LEN_D_WIDTH) then
len_d_reg <= pdi(LEN_D_WIDTH-1 downto 0);
elsif ((LEN_D_WIDTH MOD G_W) = 0) then
len_d_reg <= len_d_reg(LEN_D_WIDTH-G_W-1 downto 0) & pdi;
else
if (en_len_last_r = '0') then
if (LEN_D_WIDTH/G_W > 1) then
len_d_reg(LEN_D_WIDTH-1 downto (LEN_D_WIDTH MOD G_W)) <= len_d_reg(LEN_D_WIDTH-G_W-1 downto (LEN_D_WIDTH MOD G_W)) & pdi;
else
len_d_reg(LEN_D_WIDTH-1 downto (LEN_D_WIDTH MOD G_W)) <= pdi;
end if;
else
len_d_reg((LEN_D_WIDTH MOD G_W)-1 downto 0) <= pdi(G_W-1 downto G_W-(LEN_D_WIDTH MOD G_W));
end if;
end if;
end if;
end if;
end if;
end if;
end if;
end process;
--! Public data size (based on the interface)
p_size <= pdi(CNTR_WIDTH -1 downto 0);
--! Output
len_a <= len_a_reg(G_CTR_AD_SIZE -1 downto 0);
len_d <= len_d_reg(G_CTR_D_SIZE -1 downto 0);
bdi <= reg_data;
exp_tag <= reg_exp_tag;
genKey: if (G_RDKEY_ENABLE = 0) generate
key <= reg_key;
end generate;
genRdKey: if (G_RDKEY_ENABLE = 1) generate
rdkey <= reg_rdkey;
end generate;
bdi_valid_bytes <= reg_vbytes;
bdi_pad_loc <= reg_ploc;
genNpub: if (G_NPUB_DISABLE = 0) generate
signal reg_npub : std_logic_vector(REG_NPUB_WIDTH -1 downto 0); --! Npub register
begin
npub <= reg_npub(REG_NPUB_WIDTH-1 downto REG_NPUB_WIDTH-G_NPUB_SIZE);
procReg:
process( clk )
begin
if rising_edge( clk ) then
if (rst = '1') then
reg_npub <= (others => '0');
elsif (en_npub = '1') then
if (G_W >= G_NPUB_SIZE) then
reg_npub <= pdi(G_W-1 downto G_W-REG_NPUB_WIDTH);
else
reg_npub <= reg_npub(REG_NPUB_WIDTH-G_W-1 downto 0) & pdi;
end if;
end if;
end if;
end process;
end generate;
genNsec: if (G_NSEC_ENABLE = 1) generate
signal reg_nsec : std_logic_vector(G_NSEC_SIZE -1 downto 0); --! Nsec register
begin
nsec <= reg_nsec;
procReg:
process( clk )
begin
if rising_edge( clk ) then
if (en_nsec = '1') then
if (G_W < G_NSEC_SIZE) then
reg_nsec <= reg_nsec(G_NSEC_SIZE-G_W-1 downto 0) & pdi;
else
reg_nsec <= pdi(G_W-1 downto G_W-G_NSEC_SIZE);
end if;
end if;
end if;
end process;
end generate;
--! ============ Special mode ===========
genPartial: if ((G_DBLK_SIZE mod G_W) > 0) generate
constant ZEROS : std_logic_vector(G_W-1 downto 0) := (others => '0');
signal padded_reg : std_logic_vector(G_W/2-1 downto 0);
signal dbytes_reg : std_logic_vector((G_W/8)/2-1 downto 0);
begin
process(clk)
begin
if rising_edge(clk) then
if (en_data = '1' and sel_blank_pdi = '0') then
padded_reg <= p_1pad_di(G_W/2-1 downto 0);
dbytes_reg <= vbytes((G_W/8)/2-1 downto 0);
end if;
end if;
end process;
genKeyak0: if G_KEYAK = 0 generate
with sel_input(2 downto 0) select
input_data <= p_1pad_di when "000",
p_1pad_di(G_W-1 downto G_W-G_W/2) & ZEROS(G_W-1 downto G_W-G_W/2) when "001",
padded_reg & p_1pad_di(G_W-1 downto G_W-G_W/2) when "010",
padded_reg & ZEROS(G_W-1 downto G_W-G_W/2) when "011",
(others => '0') when others;
with sel_input(2 downto 0) select
input_vbytes <= vbytes when "000",
vbytes(G_W/8-1 downto G_W/8-(G_W/8)/2) & ZEROS(G_W/8-1 downto G_W/8-(G_W/8)/2) when "001",
dbytes_reg & vbytes(G_W/8-1 downto G_W/8-(G_W/8)/2) when "010",
dbytes_reg & ZEROS(G_W/8-1 downto G_W/8-(G_W/8)/2) when "011",
(others => '0') when others;
end generate;
--! Special loading for Keyak
genKeyak1: if (G_KEYAK = 1 and G_W = 128 and G_DBLK_SIZE = 1344) generate
signal key_r : std_logic_vector(G_KEY_SIZE-1 downto 0);
begin
pKey: process(clk)
begin
if rising_edge(clk) then
if (key_updated = '1') then
key_r <= reg_key;
end if;
end if;
end process;
with sel_input(2 downto 0) select
input_data <= p_1pad_di when "000",
p_1pad_di(G_W-1 downto G_W-G_W/2) & ZEROS(G_W-1 downto G_W-G_W/2) when "001",
padded_reg & p_1pad_di(G_W-1 downto G_W-G_W/2) when "010",
padded_reg & ZEROS(G_W-1 downto G_W-G_W/2) when "011",
x"1E" & key_r(G_KEY_SIZE-1 downto 8) when "100",
key_r(7 downto 0) & x"01" & x"000000000000000000000000" & x"0100" when "101",
(others => '0') when others;
with sel_input(2 downto 0) select
input_vbytes <= vbytes when "000",
vbytes(G_W/8-1 downto G_W/8-(G_W/8)/2) & ZEROS(G_W/8-1 downto G_W/8-(G_W/8)/2) when "001",
dbytes_reg & vbytes(G_W/8-1 downto G_W/8-(G_W/8)/2) when "010",
dbytes_reg & ZEROS(G_W/8-1 downto G_W/8-(G_W/8)/2) when "011",
(others => '1') when "100",
(others => '1') when "101",
(others => '0') when others;
end generate;
end generate;
--! ============ Padding related logic =================
--! No padding unit
genPad0: if G_PAD = 0 generate
begin
p_1pad_di <= p_zpad_di;
end generate;
--! With padding unit
genPad1: if G_PAD = 1 generate
signal pad_loc_s : std_logic_vector(G_W/8 -1 downto 0);
signal ploc_reg : std_logic_vector((G_W/8)/2 -1 downto 0);
begin
--! No actual padding is performed. However, padding location is produced. Used this mode if bdi_pad_loc signal is required)
genPadMode0:
if G_PAD_STYLE = 0 generate
p_1pad_di <= p_zpad_di;
end generate;
--! Pad 10*
genPadMode1:
if G_PAD_STYLE = 1 generate
genLoop:
for i in 0 to G_W/8-1 generate
p_1pad_di(G_W-i*8-1) <= '1' when (pad_enable = '1' and pad_loc_r(i) = '1' ) else p_zpad_di(G_W-i*8-1);
p_1pad_di(G_W-i*8-2 downto G_W-i*8-8) <= p_zpad_di(G_W-i*8-2 downto G_W-i*8-8);
end generate;
end generate;
--! Padding mode for ICEPOLE
genPadMode2:
if G_PAD_STYLE = 2 generate
genLoop:
for i in 0 to G_W/8-1 generate
p_1pad_di(G_W-i*8-1 downto G_W-i*8-6) <= p_zpad_di(G_W-i*8-1 downto G_W-i*8-6);
p_1pad_di(G_W-i*8-7) <= '1' when (pad_enable = '1' and pad_loc_r(i) = '1' ) else p_zpad_di(G_W-i*8-7);
p_1pad_di(G_W-i*8-8) <= '1' when (pad_enable = '1' and pad_loc_r(i) = '1' and ((pad_eot = '1' and pad_type_ad = '1') or (pad_eot = '0' and pad_type_ad = '0'))) else p_zpad_di(G_W-i*8-8);
end generate;
end generate;
--! Padding mode for Keyak
genPadMode3:
if G_PAD_STYLE = 3 generate
genLoop:
for i in 0 to G_W/8-1 generate
p_1pad_di(G_W-i*8-1) <= p_zpad_di(G_W-i*8-1);
p_1pad_di(G_W-i*8-2) <= p_zpad_di(G_W-i*8-2);
p_1pad_di(G_W-i*8-3) <= p_zpad_di(G_W-i*8-3);
p_1pad_di(G_W-i*8-4) <= p_zpad_di(G_W-i*8-4);
p_1pad_di(G_W-i*8-5) <= p_zpad_di(G_W-i*8-5);
p_1pad_di(G_W-i*8-6) <= '1' when (pad_enable = '1' and pad_loc_r(i) = '1') else p_zpad_di(G_W-i*8-6);
p_1pad_di(G_W-i*8-7) <= '1' when (pad_enable = '1' and pad_loc_r(i) = '1' and ((pad_type_ad = '1' and pad_eoi = '0' and pad_eot = '1') or (pad_type_ad = '0' and pad_eot = '0'))) else p_zpad_di(G_W-i*8-7);
p_1pad_di(G_W-i*8-8) <= '1' when (pad_enable = '1' and pad_loc_r(i) = '1' and (pad_type_ad = '0' or (pad_eoi = '1' and pad_type_ad = '1'))) else p_zpad_di(G_W-i*8-8);
end generate;
end generate;
procReg: process(clk)
begin
if rising_edge(clk) then
if en_pad_loc = '1' then
pad_loc_r <= pad_loc_s;
end if;
if G_W >= G_DBLK_SIZE then
if (en_data = '1') then
if (pad_enable = '1') then
reg_ploc <= reverse_bit(pad_loc_r);
else
reg_ploc <= (others => '0');
end if;
end if;
elsif (G_DBLK_SIZE MOD G_W) = 0 then
if (en_data = '1') then
if (pad_enable = '1') then
reg_ploc <= reg_ploc(G_DBLK_SIZE/8-G_W/8-1 downto 0) & reverse_bit(pad_loc_s);
else
reg_ploc <= reg_ploc(G_DBLK_SIZE/8-G_W/8-1 downto 0) & ZWORD_BYTES(G_W/8-1 downto 0);
end if;
end if;
elsif (G_DBLK_SIZE MOD G_W) /= 0 then
if (rst = '1') then
reg_ploc <= (others => '0');
elsif (en_data = '1') then
ploc_reg <= pad_loc_s(((G_W/8)-1) downto ((G_W/8)/2));
if (en_last_word = '0') then
if (pad_enable = '1') then
reg_ploc(G_DBLK_SIZE/8-1 downto ((G_DBLK_SIZE/8) MOD (G_W/8))) <= reg_ploc(G_DBLK_SIZE/8-G_W/8-1 downto ((G_DBLK_SIZE/8) MOD (G_W/8))) & input_ploc;
else
reg_ploc(G_DBLK_SIZE/8-1 downto ((G_DBLK_SIZE/8) MOD (G_W/8))) <= reg_ploc(G_DBLK_SIZE/8-G_W/8-1 downto ((G_DBLK_SIZE/8) MOD (G_W/8))) & ZWORD_BYTES(G_W/8-1 downto 0);
end if;
else
if (pad_enable = '1') then
reg_ploc(((G_DBLK_SIZE/8) mod (G_W/8))-1 downto 0) <= input_ploc(G_W/8-1 downto (G_W/8)/2);
else
reg_ploc(((G_DBLK_SIZE/8) mod (G_W/8))-1 downto 0) <= (others => '0');
end if;
end if;
end if;
end if;
end if;
end process;
gKeyak0:
if ((G_KEYAK = 0) and ((G_DBLK_SIZE MOD G_W) /= 0)) generate
with sel_input(2 downto 0) select
input_ploc <= reverse_bit(pad_loc_s) when "000",
reverse_bit(pad_loc_s)(G_W/8-1 downto (G_W/8)/2) & ZWORD_BYTES(G_W/8-1 downto G_W/8-(G_W/8)/2) when "001",
reverse_bit(ploc_reg) & reverse_bit(pad_loc_s((G_W/8)/2-1 downto 0)) when "010",
reverse_bit(ploc_reg) & ZWORD_BYTES(G_W/8-1 downto G_W/8-(G_W/8)/2) when "011",
(others => '0') when others;
end generate;
gKeyak1:
if (G_KEYAK = 1) generate
with sel_input(2 downto 0) select
input_ploc <= reverse_bit(pad_loc_s) when "000",
reverse_bit(pad_loc_s)(G_W/8-1 downto (G_W/8)/2) & ZWORD_BYTES(G_W/8-1 downto G_W/8-(G_W/8)/2) when "001",
reverse_bit(ploc_reg) & reverse_bit(pad_loc_s((G_W/8)/2-1 downto 0)) when "010",
reverse_bit(ploc_reg) & ZWORD_BYTES(G_W/8-1 downto G_W/8-(G_W/8)/2) when "011",
(others => '0') when others;
-- with sel_input(2 downto 0) select
-- input_ploc <= reverse_bit(pad_loc_s) when "000",
-- reverse_bit(ploc_reg) & reverse_bit(pad_loc_s((G_W/8)/2-1 downto 0)) when "001",
-- reverse_bit(ploc_reg) & ZWORD_BYTES(G_W/8-1 downto G_W/8-(G_W/8)/2) when "010",
-- (others => '0') when others;
end generate;
--! Calculate the padding locatin
uBarrelShifter:
entity work.bshift(struct)
generic map (G_W => G_W/8, G_LOG2_W => LOG2_W, G_LEFT => 1, G_ROTATE => 0)
port map (ii => BSHIFT_INPUT, rtr => pad_shift, oo => pad_loc_s);
end generate;
end dataflow;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.Numeric_std.all;
entity divider_TB is
end divider_TB;
architecture Behavioral of divider_TB is
component divider_sequential
port (
Enable : in std_logic;
Ready : out std_logic;
CLK : in std_logic;
Overflow : out std_logic;
Divisor : in std_logic_vector(31 downto 0);
Dividend : in std_logic_vector(31 downto 0);
Remainder : out std_logic_vector(31 downto 0);
Quotient : out std_logic_vector(31 downto 0);
isSigned : in std_logic);
end component;
signal CLK_S : std_logic;
signal Enable_S : std_logic := '0';
signal Ready_S : std_logic;
signal Overflow_S : std_logic;
signal Divisor_S : std_logic_vector(31 downto 0);
signal Quotient_S : std_logic_vector(31 downto 0);
signal Remainder_S : std_logic_vector(31 downto 0);
signal Dividend_S : std_logic_vector(31 downto 0);
signal isSigned_S : std_logic := '1';
signal Stop : std_logic := '0';
begin -- Behavioral
uut : divider_sequential port map (
CLK => CLK_S,
Enable => Enable_S,
Ready => Ready_S,
Overflow => Overflow_S,
Divisor => Divisor_S,
Quotient => Quotient_S,
Remainder => Remainder_S,
Dividend => Dividend_S,
isSigned => isSigned_S);
test: process
variable dividend_V : integer;
variable divisor_V : integer;
begin -- process
for dividend_V in 1 to 256 loop
report "Iteration: Dividend = " & integer'image(dividend_v - 129) severity note;
for divisor_V in 1 to dividend_V loop
--report "Iteration: Dividend = " & integer'image(dividend_v - 129) & ", " & "Divisor = " & integer'image(divisor_v - 129) severity note;
wait until rising_edge(CLK_S);
Dividend_S <= std_logic_vector(to_signed(dividend_V - 129,32));
Divisor_S <= std_logic_vector(to_signed(divisor_V - 129,32));
Enable_S <= '1';
wait until Ready_S = '1';
--assert (divisor_V - 129) /= 0 report "error" severity error;
assert ((divisor_V - 129) /= 0 and Overflow_S = '0') or ((divisor_V - 129) = 0 and Overflow_S = '1') report "Overflow failure" severity error;
assert Overflow_S = '1' or Dividend_S =
std_logic_vector(
to_signed(
to_integer(signed(Quotient_S)) *
to_integer(signed(Divisor_S)) +
to_integer(signed(Remainder_S)),32)) report "Incorrect Answer "&integer'image(to_integer(signed(Dividend_S)))&" / "&integer'image(to_integer(signed(Divisor_S)))&" = "&integer'image(to_integer(signed(Quotient_S)))&" rem "&integer'image(to_integer(signed(Remainder_S))) severity error;
wait for 10 ns;
Enable_S <= '0';
end loop; -- divisor
end loop; -- dividend
Stop <= '1';
wait;
end process;
clock: process
begin
CLK_S <= '0';
wait for 10 ns;
CLK_S <= '1';
wait for 10 ns;
if Stop = '1' then
wait;
end if;
end process;
end Behavioral;
|
--
-- Copyright (C) 2009-2012 Chris McClelland
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
library ieee;
library unisim;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use unisim.vcomponents.all;
entity top_level is
generic (
NUM_DEVS : integer := 1
);
port(
-- FX2LP interface ---------------------------------------------------------------------------
fx2Clk_in : in std_logic; -- 48MHz clock from FX2LP
fx2Addr_out : out std_logic_vector(1 downto 0); -- select FIFO: "00" for EP2OUT, "10" for EP6IN
fx2Data_io : inout std_logic_vector(7 downto 0); -- 8-bit data to/from FX2LP
-- When EP2OUT selected:
fx2Read_out : out std_logic; -- asserted (active-low) when reading from FX2LP
fx2OE_out : out std_logic; -- asserted (active-low) to tell FX2LP to drive bus
fx2GotData_in : in std_logic; -- asserted (active-high) when FX2LP has data for us
-- When EP6IN selected:
fx2Write_out : out std_logic; -- asserted (active-low) when writing to FX2LP
fx2GotRoom_in : in std_logic; -- asserted (active-high) when FX2LP has room for more data from us
fx2PktEnd_out : out std_logic -- asserted (active-low) when a host read needs to be committed early
);
end entity;
architecture structural of top_level is
-- Channel read/write interface -----------------------------------------------------------------
signal chanAddr : std_logic_vector(6 downto 0); -- the selected channel (0-127)
-- Host >> FPGA pipe:
signal h2fData : std_logic_vector(7 downto 0); -- data lines used when the host writes to a channel
signal h2fValid : std_logic; -- '1' means "on the next clock rising edge, please accept the data on h2fData"
signal h2fReady : std_logic; -- channel logic can drive this low to say "I'm not ready for more data yet"
-- Host << FPGA pipe:
signal f2hData : std_logic_vector(7 downto 0); -- data lines used when the host reads from a channel
signal f2hValid : std_logic; -- channel logic can drive this low to say "I don't have data ready for you"
signal f2hReady : std_logic; -- '1' means "on the next clock rising edge, put your next byte of data on f2hData"
-- ----------------------------------------------------------------------------------------------
-- Needed so that the comm_fpga_fx2 module can drive both fx2Read_out and fx2OE_out
signal fx2Read : std_logic;
-- Reset signal so host can delay startup
signal fx2Reset : std_logic;
-- SPI signals
signal spiCS : std_logic_vector(NUM_DEVS-1 downto 0);
signal spiClk : std_logic;
signal spiDataOut : std_logic;
signal spiDataIn : std_logic;
begin
-- CommFPGA module
fx2Read_out <= fx2Read;
fx2OE_out <= fx2Read;
fx2Addr_out(0) <= -- So fx2Addr_out(1)='0' selects EP2OUT, fx2Addr_out(1)='1' selects EP6IN
'0' when fx2Reset = '0'
else 'Z';
comm_fpga_fx2 : entity work.comm_fpga_fx2
port map(
clk_in => fx2Clk_in,
reset_in => '0',
reset_out => fx2Reset,
-- FX2LP interface
fx2FifoSel_out => fx2Addr_out(1),
fx2Data_io => fx2Data_io,
fx2Read_out => fx2Read,
fx2GotData_in => fx2GotData_in,
fx2Write_out => fx2Write_out,
fx2GotRoom_in => fx2GotRoom_in,
fx2PktEnd_out => fx2PktEnd_out,
-- DVR interface -> Connects to application module
chanAddr_out => chanAddr,
h2fData_out => h2fData,
h2fValid_out => h2fValid,
h2fReady_in => h2fReady,
f2hData_in => f2hData,
f2hValid_in => f2hValid,
f2hReady_out => f2hReady
);
-- Switches & LEDs application
spi_talk_app : entity work.spi_talk
generic map (
NUM_DEVS => NUM_DEVS
)
port map(
clk_in => fx2Clk_in,
-- DVR interface -> Connects to comm_fpga module
chanAddr_in => chanAddr,
h2fData_in => h2fData,
h2fValid_in => h2fValid,
h2fReady_out => h2fReady,
f2hData_out => f2hData,
f2hValid_out => f2hValid,
f2hReady_in => f2hReady,
-- Peripheral interface
spiClk_out => spiClk,
spiData_out => spiDataOut,
spiData_in => spiDataIn,
spiCS_out => spiCS
);
spi_access: spi_access
generic map(
SIM_DEVICE => "3S200AN"
)
port map(
MISO => spiDataIn, -- 1-bit SPI output data
MOSI => spiDataOut, -- 1-bit SPI input data
CSB => spiCS(0), -- 1-bit SPI chip enable
CLK => spiClk -- 1-bit SPI clock input
);
end architecture;
|
entity b is end entity;
entity foo is
generic ( a : integer );
port ( b : in integer );
end entity;
architecture arch of foo is
begin
end architecture;
configuration yah of foo is
use work.foo;
for arch
end for;
end configuration;
architecture a of b is
component y is end component;
component p is end component;
for x : y use entity work.foo;
for x1, x2 : y use entity work.foo;
for x3 : y use entity work.foo(arch);
for x4 : y use entity work.foo(arch)
generic map ( a => 1 )
port map ( b => 6 );
for all : p use configuration work.yah;
for others : y use open;
begin
x: component y;
x1: component y;
x2: component y;
x3: component y;
x4: component y;
end architecture;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: iopad_ddr, iopad_ddrv, iopad_ddrvv
-- File: iopad_ddr.vhd
-- Author: Jan Andersson - Aeroflex Gaisler
-- Description: Wrapper that instantiates an iopad connected to DDR register.
-- Special case for easic90 tech since this tech requires that
-- oe is directly connected between DDR register and pad.
------------------------------------------------------------------------------
library techmap;
library ieee;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
use techmap.allddr.all;
use techmap.allpads.all;
entity iopad_ddr is
generic (
tech : integer := 0;
level : integer := 0;
slew : integer := 0;
voltage : integer := x33v;
strength : integer := 12;
oepol : integer := 0);
port (
pad : inout std_ulogic;
i1, i2 : in std_ulogic; -- Input H and L
en : in std_ulogic; -- Output enable
o1, o2 : out std_ulogic; -- Output H and L
c1, c2 : in std_ulogic;
ce : in std_ulogic;
r : in std_ulogic;
s : in std_ulogic);
end;
architecture rtl of iopad_ddr is
signal oe, oen, d, q : std_ulogic;
begin
def: if (tech /= easic90) generate
p : iopad generic map (tech, level, slew, voltage, strength, oepol)
port map (pad, q, en, d);
ddrregi : ddr_ireg generic map (tech)
port map (o1, o2, c1, c2, ce, d, r, s);
ddrrego : ddr_oreg generic map (tech)
port map (q, c1, c2, ce, i1, i2, r, s);
oe <= '0'; oen <= '0'; -- Not used in this configuration
end generate def;
nex : if (tech = easic90) generate
oen <= not en when oepol /= padoen_polarity(tech) else en;
p : nextreme_iopad generic map (level, slew, voltage, strength)
port map (pad, q, oe, d);
ddrregi : nextreme_iddr_reg
port map (ck => c1, d => d, qh => o1, ql => o2, rstb => r);
ddrrego : nextreme_oddr_reg
port map (ck => c1, dh => i1, dl => i2, doe => oen, q => q,
oe => oe, rstb => r);
end generate;
end;
library techmap;
library ieee;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
entity iopad_ddrv is
generic (
tech : integer := 0;
level : integer := 0;
slew : integer := 0;
voltage : integer := x33v;
strength : integer := 12;
width : integer := 1;
oepol : integer := 0);
port (
pad : inout std_logic_vector(width-1 downto 0);
i1, i2 : in std_logic_vector(width-1 downto 0);
en : in std_ulogic;
o1, o2 : out std_logic_vector(width-1 downto 0);
c1, c2 : in std_ulogic;
ce : in std_ulogic;
r : in std_ulogic;
s : in std_ulogic);
end;
architecture rtl of iopad_ddrv is
begin
v : for j in width-1 downto 0 generate
x0 : iopad_ddr generic map (tech, level, slew, voltage, strength, oepol)
port map (pad(j), i1(j), i2(j), en, o1(j), o2(j), c1, c2, ce, r, s);
end generate;
end;
library techmap;
library ieee;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
entity iopad_ddrvv is
generic (
tech : integer := 0;
level : integer := 0;
slew : integer := 0;
voltage : integer := x33v;
strength : integer := 12;
width : integer := 1;
oepol : integer := 0);
port (
pad : inout std_logic_vector(width-1 downto 0);
i1, i2 : in std_logic_vector(width-1 downto 0);
en : in std_logic_vector(width-1 downto 0);
o1, o2 : out std_logic_vector(width-1 downto 0);
c1, c2 : in std_ulogic;
ce : in std_ulogic;
r : in std_ulogic;
s : in std_ulogic);
end;
architecture rtl of iopad_ddrvv is
begin
v : for j in width-1 downto 0 generate
x0 : iopad_ddr generic map (tech, level, slew, voltage, strength, oepol)
port map (pad(j), i1(j), i2(j), en(j), o1(j), o2(j), c1, c2, ce, r, s);
end generate;
end;
|
--------------------------------------------------------------------------
-- --
-- Copyright (c) 1990,1991,1992 by Synopsys, Inc. All rights reserved. --
-- --
-- This source file may be used and distributed without restriction --
-- provided that this copyright statement is not removed from the file --
-- and that any derivative work contains this copyright notice. --
-- --
-- Package name: STD_LOGIC_ARITH --
-- --
-- Purpose: --
-- A set of arithemtic, conversion, and comparison functions --
-- for SIGNED, UNSIGNED, SMALL_INT, INTEGER, --
-- STD_ULOGIC, STD_LOGIC, and STD_LOGIC_VECTOR. --
-- --
--------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
package std_logic_arith is
type UNSIGNED is array (NATURAL range <>) of STD_LOGIC;
type SIGNED is array (NATURAL range <>) of STD_LOGIC;
subtype SMALL_INT is INTEGER range 0 to 1;
function "+"(L: UNSIGNED; R: UNSIGNED) return UNSIGNED;
function "+"(L: SIGNED; R: SIGNED) return SIGNED;
function "+"(L: UNSIGNED; R: SIGNED) return SIGNED;
function "+"(L: SIGNED; R: UNSIGNED) return SIGNED;
function "+"(L: UNSIGNED; R: INTEGER) return UNSIGNED;
function "+"(L: INTEGER; R: UNSIGNED) return UNSIGNED;
function "+"(L: SIGNED; R: INTEGER) return SIGNED;
function "+"(L: INTEGER; R: SIGNED) return SIGNED;
function "+"(L: UNSIGNED; R: STD_ULOGIC) return UNSIGNED;
function "+"(L: STD_ULOGIC; R: UNSIGNED) return UNSIGNED;
function "+"(L: SIGNED; R: STD_ULOGIC) return SIGNED;
function "+"(L: STD_ULOGIC; R: SIGNED) return SIGNED;
function "+"(L: UNSIGNED; R: UNSIGNED) return STD_LOGIC_VECTOR;
function "+"(L: SIGNED; R: SIGNED) return STD_LOGIC_VECTOR;
function "+"(L: UNSIGNED; R: SIGNED) return STD_LOGIC_VECTOR;
function "+"(L: SIGNED; R: UNSIGNED) return STD_LOGIC_VECTOR;
function "+"(L: UNSIGNED; R: INTEGER) return STD_LOGIC_VECTOR;
function "+"(L: INTEGER; R: UNSIGNED) return STD_LOGIC_VECTOR;
function "+"(L: SIGNED; R: INTEGER) return STD_LOGIC_VECTOR;
function "+"(L: INTEGER; R: SIGNED) return STD_LOGIC_VECTOR;
function "+"(L: UNSIGNED; R: STD_ULOGIC) return STD_LOGIC_VECTOR;
function "+"(L: STD_ULOGIC; R: UNSIGNED) return STD_LOGIC_VECTOR;
function "+"(L: SIGNED; R: STD_ULOGIC) return STD_LOGIC_VECTOR;
function "+"(L: STD_ULOGIC; R: SIGNED) return STD_LOGIC_VECTOR;
function "-"(L: UNSIGNED; R: UNSIGNED) return UNSIGNED;
function "-"(L: SIGNED; R: SIGNED) return SIGNED;
function "-"(L: UNSIGNED; R: SIGNED) return SIGNED;
function "-"(L: SIGNED; R: UNSIGNED) return SIGNED;
function "-"(L: UNSIGNED; R: INTEGER) return UNSIGNED;
function "-"(L: INTEGER; R: UNSIGNED) return UNSIGNED;
function "-"(L: SIGNED; R: INTEGER) return SIGNED;
function "-"(L: INTEGER; R: SIGNED) return SIGNED;
function "-"(L: UNSIGNED; R: STD_ULOGIC) return UNSIGNED;
function "-"(L: STD_ULOGIC; R: UNSIGNED) return UNSIGNED;
function "-"(L: SIGNED; R: STD_ULOGIC) return SIGNED;
function "-"(L: STD_ULOGIC; R: SIGNED) return SIGNED;
function "-"(L: UNSIGNED; R: UNSIGNED) return STD_LOGIC_VECTOR;
function "-"(L: SIGNED; R: SIGNED) return STD_LOGIC_VECTOR;
function "-"(L: UNSIGNED; R: SIGNED) return STD_LOGIC_VECTOR;
function "-"(L: SIGNED; R: UNSIGNED) return STD_LOGIC_VECTOR;
function "-"(L: UNSIGNED; R: INTEGER) return STD_LOGIC_VECTOR;
function "-"(L: INTEGER; R: UNSIGNED) return STD_LOGIC_VECTOR;
function "-"(L: SIGNED; R: INTEGER) return STD_LOGIC_VECTOR;
function "-"(L: INTEGER; R: SIGNED) return STD_LOGIC_VECTOR;
function "-"(L: UNSIGNED; R: STD_ULOGIC) return STD_LOGIC_VECTOR;
function "-"(L: STD_ULOGIC; R: UNSIGNED) return STD_LOGIC_VECTOR;
function "-"(L: SIGNED; R: STD_ULOGIC) return STD_LOGIC_VECTOR;
function "-"(L: STD_ULOGIC; R: SIGNED) return STD_LOGIC_VECTOR;
function "+"(L: UNSIGNED) return UNSIGNED;
function "+"(L: SIGNED) return SIGNED;
function "-"(L: SIGNED) return SIGNED;
function "ABS"(L: SIGNED) return SIGNED;
function "+"(L: UNSIGNED) return STD_LOGIC_VECTOR;
function "+"(L: SIGNED) return STD_LOGIC_VECTOR;
function "-"(L: SIGNED) return STD_LOGIC_VECTOR;
function "ABS"(L: SIGNED) return STD_LOGIC_VECTOR;
function "*"(L: UNSIGNED; R: UNSIGNED) return UNSIGNED;
function "*"(L: SIGNED; R: SIGNED) return SIGNED;
function "*"(L: SIGNED; R: UNSIGNED) return SIGNED;
function "*"(L: UNSIGNED; R: SIGNED) return SIGNED;
function "*"(L: UNSIGNED; R: UNSIGNED) return STD_LOGIC_VECTOR;
function "*"(L: SIGNED; R: SIGNED) return STD_LOGIC_VECTOR;
function "*"(L: SIGNED; R: UNSIGNED) return STD_LOGIC_VECTOR;
function "*"(L: UNSIGNED; R: SIGNED) return STD_LOGIC_VECTOR;
function "<"(L: UNSIGNED; R: UNSIGNED) return BOOLEAN;
function "<"(L: SIGNED; R: SIGNED) return BOOLEAN;
function "<"(L: UNSIGNED; R: SIGNED) return BOOLEAN;
function "<"(L: SIGNED; R: UNSIGNED) return BOOLEAN;
function "<"(L: UNSIGNED; R: INTEGER) return BOOLEAN;
function "<"(L: INTEGER; R: UNSIGNED) return BOOLEAN;
function "<"(L: SIGNED; R: INTEGER) return BOOLEAN;
function "<"(L: INTEGER; R: SIGNED) return BOOLEAN;
function "<="(L: UNSIGNED; R: UNSIGNED) return BOOLEAN;
function "<="(L: SIGNED; R: SIGNED) return BOOLEAN;
function "<="(L: UNSIGNED; R: SIGNED) return BOOLEAN;
function "<="(L: SIGNED; R: UNSIGNED) return BOOLEAN;
function "<="(L: UNSIGNED; R: INTEGER) return BOOLEAN;
function "<="(L: INTEGER; R: UNSIGNED) return BOOLEAN;
function "<="(L: SIGNED; R: INTEGER) return BOOLEAN;
function "<="(L: INTEGER; R: SIGNED) return BOOLEAN;
function ">"(L: UNSIGNED; R: UNSIGNED) return BOOLEAN;
function ">"(L: SIGNED; R: SIGNED) return BOOLEAN;
function ">"(L: UNSIGNED; R: SIGNED) return BOOLEAN;
function ">"(L: SIGNED; R: UNSIGNED) return BOOLEAN;
function ">"(L: UNSIGNED; R: INTEGER) return BOOLEAN;
function ">"(L: INTEGER; R: UNSIGNED) return BOOLEAN;
function ">"(L: SIGNED; R: INTEGER) return BOOLEAN;
function ">"(L: INTEGER; R: SIGNED) return BOOLEAN;
function ">="(L: UNSIGNED; R: UNSIGNED) return BOOLEAN;
function ">="(L: SIGNED; R: SIGNED) return BOOLEAN;
function ">="(L: UNSIGNED; R: SIGNED) return BOOLEAN;
function ">="(L: SIGNED; R: UNSIGNED) return BOOLEAN;
function ">="(L: UNSIGNED; R: INTEGER) return BOOLEAN;
function ">="(L: INTEGER; R: UNSIGNED) return BOOLEAN;
function ">="(L: SIGNED; R: INTEGER) return BOOLEAN;
function ">="(L: INTEGER; R: SIGNED) return BOOLEAN;
function "="(L: UNSIGNED; R: UNSIGNED) return BOOLEAN;
function "="(L: SIGNED; R: SIGNED) return BOOLEAN;
function "="(L: UNSIGNED; R: SIGNED) return BOOLEAN;
function "="(L: SIGNED; R: UNSIGNED) return BOOLEAN;
function "="(L: UNSIGNED; R: INTEGER) return BOOLEAN;
function "="(L: INTEGER; R: UNSIGNED) return BOOLEAN;
function "="(L: SIGNED; R: INTEGER) return BOOLEAN;
function "="(L: INTEGER; R: SIGNED) return BOOLEAN;
function "/="(L: UNSIGNED; R: UNSIGNED) return BOOLEAN;
function "/="(L: SIGNED; R: SIGNED) return BOOLEAN;
function "/="(L: UNSIGNED; R: SIGNED) return BOOLEAN;
function "/="(L: SIGNED; R: UNSIGNED) return BOOLEAN;
function "/="(L: UNSIGNED; R: INTEGER) return BOOLEAN;
function "/="(L: INTEGER; R: UNSIGNED) return BOOLEAN;
function "/="(L: SIGNED; R: INTEGER) return BOOLEAN;
function "/="(L: INTEGER; R: SIGNED) return BOOLEAN;
function SHL(ARG: UNSIGNED; COUNT: UNSIGNED) return UNSIGNED;
function SHL(ARG: SIGNED; COUNT: UNSIGNED) return SIGNED;
function SHR(ARG: UNSIGNED; COUNT: UNSIGNED) return UNSIGNED;
function SHR(ARG: SIGNED; COUNT: UNSIGNED) return SIGNED;
function CONV_INTEGER(ARG: INTEGER) return INTEGER;
function CONV_INTEGER(ARG: UNSIGNED) return INTEGER;
function CONV_INTEGER(ARG: SIGNED) return INTEGER;
function CONV_INTEGER(ARG: STD_ULOGIC) return SMALL_INT;
function CONV_UNSIGNED(ARG: INTEGER; SIZE: INTEGER) return UNSIGNED;
function CONV_UNSIGNED(ARG: UNSIGNED; SIZE: INTEGER) return UNSIGNED;
function CONV_UNSIGNED(ARG: SIGNED; SIZE: INTEGER) return UNSIGNED;
function CONV_UNSIGNED(ARG: STD_ULOGIC; SIZE: INTEGER) return UNSIGNED;
function CONV_SIGNED(ARG: INTEGER; SIZE: INTEGER) return SIGNED;
function CONV_SIGNED(ARG: UNSIGNED; SIZE: INTEGER) return SIGNED;
function CONV_SIGNED(ARG: SIGNED; SIZE: INTEGER) return SIGNED;
function CONV_SIGNED(ARG: STD_ULOGIC; SIZE: INTEGER) return SIGNED;
function CONV_STD_LOGIC_VECTOR(ARG: INTEGER; SIZE: INTEGER)
return STD_LOGIC_VECTOR;
function CONV_STD_LOGIC_VECTOR(ARG: UNSIGNED; SIZE: INTEGER)
return STD_LOGIC_VECTOR;
function CONV_STD_LOGIC_VECTOR(ARG: SIGNED; SIZE: INTEGER)
return STD_LOGIC_VECTOR;
function CONV_STD_LOGIC_VECTOR(ARG: STD_ULOGIC; SIZE: INTEGER)
return STD_LOGIC_VECTOR;
-- zero extend STD_LOGIC_VECTOR (ARG) to SIZE,
-- SIZE < 0 is same as SIZE = 0
-- returns STD_LOGIC_VECTOR(SIZE-1 downto 0)
function EXT(ARG: STD_LOGIC_VECTOR; SIZE: INTEGER) return STD_LOGIC_VECTOR;
-- sign extend STD_LOGIC_VECTOR (ARG) to SIZE,
-- SIZE < 0 is same as SIZE = 0
-- return STD_LOGIC_VECTOR(SIZE-1 downto 0)
function SXT(ARG: STD_LOGIC_VECTOR; SIZE: INTEGER) return STD_LOGIC_VECTOR;
end Std_logic_arith;
library IEEE;
use IEEE.std_logic_1164.all;
library nvc;
use nvc.sim_pkg.ieee_warnings;
package body std_logic_arith is
constant NO_WARNING : BOOLEAN := not ieee_warnings;
function max(L, R: INTEGER) return INTEGER is
begin
if L > R then
return L;
else
return R;
end if;
end;
function min(L, R: INTEGER) return INTEGER is
begin
if L < R then
return L;
else
return R;
end if;
end;
-- synopsys synthesis_off
type tbl_type is array (STD_ULOGIC) of STD_ULOGIC;
constant tbl_BINARY : tbl_type :=
('X', 'X', '0', '1', 'X', 'X', '0', '1', 'X');
-- synopsys synthesis_on
-- synopsys synthesis_off
type tbl_mvl9_boolean is array (STD_ULOGIC) of boolean;
constant IS_X : tbl_mvl9_boolean :=
(true, true, false, false, true, true, false, false, true);
-- synopsys synthesis_on
function MAKE_BINARY(A : STD_ULOGIC) return STD_ULOGIC is
-- synopsys built_in SYN_FEED_THRU
begin
-- synopsys synthesis_off
if (IS_X(A)) then
assert no_warning
report "There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es)."
severity warning;
return ('X');
end if;
return tbl_BINARY(A);
-- synopsys synthesis_on
end;
function MAKE_BINARY(A : UNSIGNED) return UNSIGNED is
-- synopsys built_in SYN_FEED_THRU
variable one_bit : STD_ULOGIC;
variable result : UNSIGNED (A'range);
begin
-- synopsys synthesis_off
for i in A'range loop
if (IS_X(A(i))) then
assert no_warning
report "There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es)."
severity warning;
result := (others => 'X');
return result;
end if;
result(i) := tbl_BINARY(A(i));
end loop;
return result;
-- synopsys synthesis_on
end;
function MAKE_BINARY(A : UNSIGNED) return SIGNED is
-- synopsys built_in SYN_FEED_THRU
variable one_bit : STD_ULOGIC;
variable result : SIGNED (A'range);
begin
-- synopsys synthesis_off
for i in A'range loop
if (IS_X(A(i))) then
assert no_warning
report "There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es)."
severity warning;
result := (others => 'X');
return result;
end if;
result(i) := tbl_BINARY(A(i));
end loop;
return result;
-- synopsys synthesis_on
end;
function MAKE_BINARY(A : SIGNED) return UNSIGNED is
-- synopsys built_in SYN_FEED_THRU
variable one_bit : STD_ULOGIC;
variable result : UNSIGNED (A'range);
begin
-- synopsys synthesis_off
for i in A'range loop
if (IS_X(A(i))) then
assert no_warning
report "There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es)."
severity warning;
result := (others => 'X');
return result;
end if;
result(i) := tbl_BINARY(A(i));
end loop;
return result;
-- synopsys synthesis_on
end;
function MAKE_BINARY(A : SIGNED) return SIGNED is
-- synopsys built_in SYN_FEED_THRU
variable one_bit : STD_ULOGIC;
variable result : SIGNED (A'range);
begin
-- synopsys synthesis_off
for i in A'range loop
if (IS_X(A(i))) then
assert no_warning
report "There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es)."
severity warning;
result := (others => 'X');
return result;
end if;
result(i) := tbl_BINARY(A(i));
end loop;
return result;
-- synopsys synthesis_on
end;
function MAKE_BINARY(A : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- synopsys built_in SYN_FEED_THRU
variable one_bit : STD_ULOGIC;
variable result : STD_LOGIC_VECTOR (A'range);
begin
-- synopsys synthesis_off
for i in A'range loop
if (IS_X(A(i))) then
assert no_warning
report "There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es)."
severity warning;
result := (others => 'X');
return result;
end if;
result(i) := tbl_BINARY(A(i));
end loop;
return result;
-- synopsys synthesis_on
end;
function MAKE_BINARY(A : UNSIGNED) return STD_LOGIC_VECTOR is
-- synopsys built_in SYN_FEED_THRU
variable one_bit : STD_ULOGIC;
variable result : STD_LOGIC_VECTOR (A'range);
begin
-- synopsys synthesis_off
for i in A'range loop
if (IS_X(A(i))) then
assert no_warning
report "There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es)."
severity warning;
result := (others => 'X');
return result;
end if;
result(i) := tbl_BINARY(A(i));
end loop;
return result;
-- synopsys synthesis_on
end;
function MAKE_BINARY(A : SIGNED) return STD_LOGIC_VECTOR is
-- synopsys built_in SYN_FEED_THRU
variable one_bit : STD_ULOGIC;
variable result : STD_LOGIC_VECTOR (A'range);
begin
-- synopsys synthesis_off
for i in A'range loop
if (IS_X(A(i))) then
assert no_warning
report "There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es)."
severity warning;
result := (others => 'X');
return result;
end if;
result(i) := tbl_BINARY(A(i));
end loop;
return result;
-- synopsys synthesis_on
end;
-- Type propagation function which returns a signed type with the
-- size of the left arg.
function LEFT_SIGNED_ARG(A,B: SIGNED) return SIGNED is
variable Z: SIGNED (A'left downto 0);
-- pragma return_port_name Z
begin
return(Z);
end;
-- Type propagation function which returns an unsigned type with the
-- size of the left arg.
function LEFT_UNSIGNED_ARG(A,B: UNSIGNED) return UNSIGNED is
variable Z: UNSIGNED (A'left downto 0);
-- pragma return_port_name Z
begin
return(Z);
end;
-- Type propagation function which returns a signed type with the
-- size of the result of a signed multiplication
function MULT_SIGNED_ARG(A,B: SIGNED) return SIGNED is
variable Z: SIGNED ((A'length+B'length-1) downto 0);
-- pragma return_port_name Z
begin
return(Z);
end;
-- Type propagation function which returns an unsigned type with the
-- size of the result of a unsigned multiplication
function MULT_UNSIGNED_ARG(A,B: UNSIGNED) return UNSIGNED is
variable Z: UNSIGNED ((A'length+B'length-1) downto 0);
-- pragma return_port_name Z
begin
return(Z);
end;
function mult(A,B: SIGNED) return SIGNED is
variable BA: SIGNED((A'length+B'length-1) downto 0);
variable PA: SIGNED((A'length+B'length-1) downto 0);
variable AA: SIGNED(A'length downto 0);
variable neg: STD_ULOGIC;
constant one : UNSIGNED(1 downto 0) := "01";
-- pragma map_to_operator MULT_TC_OP
-- pragma type_function MULT_SIGNED_ARG
-- pragma return_port_name Z
begin
if (A(A'left) = 'X' or B(B'left) = 'X') then
PA := (others => 'X');
return(PA);
end if;
PA := (others => '0');
neg := B(B'left) xor A(A'left);
BA := CONV_SIGNED(('0' & ABS(B)),(A'length+B'length));
AA := '0' & ABS(A);
for i in 0 to A'length-1 loop
if AA(i) = '1' then
PA := PA+BA;
end if;
BA := SHL(BA,one);
end loop;
if (neg= '1') then
return(-PA);
else
return(PA);
end if;
end;
function mult(A,B: UNSIGNED) return UNSIGNED is
variable BA: UNSIGNED((A'length+B'length-1) downto 0);
variable PA: UNSIGNED((A'length+B'length-1) downto 0);
constant one : UNSIGNED(1 downto 0) := "01";
-- pragma map_to_operator MULT_UNS_OP
-- pragma type_function MULT_UNSIGNED_ARG
-- pragma return_port_name Z
begin
if (A(A'left) = 'X' or B(B'left) = 'X') then
PA := (others => 'X');
return(PA);
end if;
PA := (others => '0');
BA := CONV_UNSIGNED(B,(A'length+B'length));
for i in 0 to A'length-1 loop
if A(i) = '1' then
PA := PA+BA;
end if;
BA := SHL(BA,one);
end loop;
return(PA);
end;
-- subtract two signed numbers of the same length
-- both arrays must have range (msb downto 0)
function minus(A, B: SIGNED) return SIGNED is
variable carry: STD_ULOGIC;
variable BV: STD_ULOGIC_VECTOR (A'left downto 0);
variable sum: SIGNED (A'left downto 0);
-- pragma map_to_operator SUB_TC_OP
-- pragma type_function LEFT_SIGNED_ARG
-- pragma return_port_name Z
begin
if (A(A'left) = 'X' or B(B'left) = 'X') then
sum := (others => 'X');
return(sum);
end if;
carry := '1';
BV := not STD_ULOGIC_VECTOR(B);
for i in 0 to A'left loop
sum(i) := A(i) xor BV(i) xor carry;
carry := (A(i) and BV(i)) or
(A(i) and carry) or
(carry and BV(i));
end loop;
return sum;
end;
-- add two signed numbers of the same length
-- both arrays must have range (msb downto 0)
function plus(A, B: SIGNED) return SIGNED is
variable carry: STD_ULOGIC;
variable BV, sum: SIGNED (A'left downto 0);
-- pragma map_to_operator ADD_TC_OP
-- pragma type_function LEFT_SIGNED_ARG
-- pragma return_port_name Z
begin
if (A(A'left) = 'X' or B(B'left) = 'X') then
sum := (others => 'X');
return(sum);
end if;
carry := '0';
BV := B;
for i in 0 to A'left loop
sum(i) := A(i) xor BV(i) xor carry;
carry := (A(i) and BV(i)) or
(A(i) and carry) or
(carry and BV(i));
end loop;
return sum;
end;
-- subtract two unsigned numbers of the same length
-- both arrays must have range (msb downto 0)
function unsigned_minus(A, B: UNSIGNED) return UNSIGNED is
variable carry: STD_ULOGIC;
variable BV: STD_ULOGIC_VECTOR (A'left downto 0);
variable sum: UNSIGNED (A'left downto 0);
-- pragma map_to_operator SUB_UNS_OP
-- pragma type_function LEFT_UNSIGNED_ARG
-- pragma return_port_name Z
begin
if (A(A'left) = 'X' or B(B'left) = 'X') then
sum := (others => 'X');
return(sum);
end if;
carry := '1';
BV := not STD_ULOGIC_VECTOR(B);
for i in 0 to A'left loop
sum(i) := A(i) xor BV(i) xor carry;
carry := (A(i) and BV(i)) or
(A(i) and carry) or
(carry and BV(i));
end loop;
return sum;
end;
-- add two unsigned numbers of the same length
-- both arrays must have range (msb downto 0)
function unsigned_plus(A, B: UNSIGNED) return UNSIGNED is
variable carry: STD_ULOGIC;
variable BV, sum: UNSIGNED (A'left downto 0);
-- pragma map_to_operator ADD_UNS_OP
-- pragma type_function LEFT_UNSIGNED_ARG
-- pragma return_port_name Z
begin
if (A(A'left) = 'X' or B(B'left) = 'X') then
sum := (others => 'X');
return(sum);
end if;
carry := '0';
BV := B;
for i in 0 to A'left loop
sum(i) := A(i) xor BV(i) xor carry;
carry := (A(i) and BV(i)) or
(A(i) and carry) or
(carry and BV(i));
end loop;
return sum;
end;
function "*"(L: SIGNED; R: SIGNED) return SIGNED is
-- pragma label_applies_to mult
-- synopsys subpgm_id 296
begin
return mult(CONV_SIGNED(L, L'length),
CONV_SIGNED(R, R'length)); -- pragma label mult
end;
function "*"(L: UNSIGNED; R: UNSIGNED) return UNSIGNED is
-- pragma label_applies_to mult
-- synopsys subpgm_id 295
begin
return mult(CONV_UNSIGNED(L, L'length),
CONV_UNSIGNED(R, R'length)); -- pragma label mult
end;
function "*"(L: UNSIGNED; R: SIGNED) return SIGNED is
-- pragma label_applies_to mult
-- synopsys subpgm_id 297
begin
return mult(CONV_SIGNED(L, L'length+1),
CONV_SIGNED(R, R'length)); -- pragma label mult
end;
function "*"(L: SIGNED; R: UNSIGNED) return SIGNED is
-- pragma label_applies_to mult
-- synopsys subpgm_id 298
begin
return mult(CONV_SIGNED(L, L'length),
CONV_SIGNED(R, R'length+1)); -- pragma label mult
end;
function "*"(L: SIGNED; R: SIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to mult
-- synopsys subpgm_id 301
begin
return STD_LOGIC_VECTOR (
mult(-- pragma label mult
CONV_SIGNED(L, L'length), CONV_SIGNED(R, R'length)));
end;
function "*"(L: UNSIGNED; R: UNSIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to mult
-- synopsys subpgm_id 300
begin
return STD_LOGIC_VECTOR (
mult(-- pragma label mult
CONV_UNSIGNED(L, L'length), CONV_UNSIGNED(R, R'length)));
end;
function "*"(L: UNSIGNED; R: SIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to mult
-- synopsys subpgm_id 302
begin
return STD_LOGIC_VECTOR (
mult(-- pragma label mult
CONV_SIGNED(L, L'length+1), CONV_SIGNED(R, R'length)));
end;
function "*"(L: SIGNED; R: UNSIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to mult
-- synopsys subpgm_id 303
begin
return STD_LOGIC_VECTOR (
mult(-- pragma label mult
CONV_SIGNED(L, L'length), CONV_SIGNED(R, R'length+1)));
end;
function "+"(L: UNSIGNED; R: UNSIGNED) return UNSIGNED is
-- pragma label_applies_to plus
-- synopsys subpgm_id 236
constant length: INTEGER := max(L'length, R'length);
begin
return unsigned_plus(CONV_UNSIGNED(L, length),
CONV_UNSIGNED(R, length)); -- pragma label plus
end;
function "+"(L: SIGNED; R: SIGNED) return SIGNED is
-- pragma label_applies_to plus
-- synopsys subpgm_id 237
constant length: INTEGER := max(L'length, R'length);
begin
return plus(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label plus
end;
function "+"(L: UNSIGNED; R: SIGNED) return SIGNED is
-- pragma label_applies_to plus
-- synopsys subpgm_id 238
constant length: INTEGER := max(L'length + 1, R'length);
begin
return plus(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label plus
end;
function "+"(L: SIGNED; R: UNSIGNED) return SIGNED is
-- pragma label_applies_to plus
-- synopsys subpgm_id 239
constant length: INTEGER := max(L'length, R'length + 1);
begin
return plus(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label plus
end;
function "+"(L: UNSIGNED; R: INTEGER) return UNSIGNED is
-- pragma label_applies_to plus
-- synopsys subpgm_id 240
constant length: INTEGER := L'length + 1;
begin
return CONV_UNSIGNED(
plus( -- pragma label plus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)), length-1);
end;
function "+"(L: INTEGER; R: UNSIGNED) return UNSIGNED is
-- pragma label_applies_to plus
-- synopsys subpgm_id 241
constant length: INTEGER := R'length + 1;
begin
return CONV_UNSIGNED(
plus( -- pragma label plus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)), length-1);
end;
function "+"(L: SIGNED; R: INTEGER) return SIGNED is
-- pragma label_applies_to plus
-- synopsys subpgm_id 242
constant length: INTEGER := L'length;
begin
return plus(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label plus
end;
function "+"(L: INTEGER; R: SIGNED) return SIGNED is
-- pragma label_applies_to plus
-- synopsys subpgm_id 243
constant length: INTEGER := R'length;
begin
return plus(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label plus
end;
function "+"(L: UNSIGNED; R: STD_ULOGIC) return UNSIGNED is
-- pragma label_applies_to plus
-- synopsys subpgm_id 244
constant length: INTEGER := L'length;
begin
return unsigned_plus(CONV_UNSIGNED(L, length),
CONV_UNSIGNED(R, length)) ; -- pragma label plus
end;
function "+"(L: STD_ULOGIC; R: UNSIGNED) return UNSIGNED is
-- pragma label_applies_to plus
-- synopsys subpgm_id 245
constant length: INTEGER := R'length;
begin
return unsigned_plus(CONV_UNSIGNED(L, length),
CONV_UNSIGNED(R, length)); -- pragma label plus
end;
function "+"(L: SIGNED; R: STD_ULOGIC) return SIGNED is
-- pragma label_applies_to plus
-- synopsys subpgm_id 246
constant length: INTEGER := L'length;
begin
return plus(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label plus
end;
function "+"(L: STD_ULOGIC; R: SIGNED) return SIGNED is
-- pragma label_applies_to plus
-- synopsys subpgm_id 247
constant length: INTEGER := R'length;
begin
return plus(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label plus
end;
function "+"(L: UNSIGNED; R: UNSIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
-- synopsys subpgm_id 260
constant length: INTEGER := max(L'length, R'length);
begin
return STD_LOGIC_VECTOR (
unsigned_plus(-- pragma label plus
CONV_UNSIGNED(L, length), CONV_UNSIGNED(R, length)));
end;
function "+"(L: SIGNED; R: SIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
-- synopsys subpgm_id 261
constant length: INTEGER := max(L'length, R'length);
begin
return STD_LOGIC_VECTOR (
plus(-- pragma label plus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)));
end;
function "+"(L: UNSIGNED; R: SIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
-- synopsys subpgm_id 262
constant length: INTEGER := max(L'length + 1, R'length);
begin
return STD_LOGIC_VECTOR (
plus(-- pragma label plus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)));
end;
function "+"(L: SIGNED; R: UNSIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
-- synopsys subpgm_id 263
constant length: INTEGER := max(L'length, R'length + 1);
begin
return STD_LOGIC_VECTOR (
plus(-- pragma label plus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)));
end;
function "+"(L: UNSIGNED; R: INTEGER) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
-- synopsys subpgm_id 264
constant length: INTEGER := L'length + 1;
begin
return STD_LOGIC_VECTOR (CONV_UNSIGNED(
plus( -- pragma label plus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)), length-1));
end;
function "+"(L: INTEGER; R: UNSIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
-- synopsys subpgm_id 265
constant length: INTEGER := R'length + 1;
begin
return STD_LOGIC_VECTOR (CONV_UNSIGNED(
plus( -- pragma label plus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)), length-1));
end;
function "+"(L: SIGNED; R: INTEGER) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
-- synopsys subpgm_id 266
constant length: INTEGER := L'length;
begin
return STD_LOGIC_VECTOR (
plus(-- pragma label plus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)));
end;
function "+"(L: INTEGER; R: SIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
-- synopsys subpgm_id 267
constant length: INTEGER := R'length;
begin
return STD_LOGIC_VECTOR (
plus(-- pragma label plus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)));
end;
function "+"(L: UNSIGNED; R: STD_ULOGIC) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
-- synopsys subpgm_id 268
constant length: INTEGER := L'length;
begin
return STD_LOGIC_VECTOR (
unsigned_plus(-- pragma label plus
CONV_UNSIGNED(L, length), CONV_UNSIGNED(R, length))) ;
end;
function "+"(L: STD_ULOGIC; R: UNSIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
-- synopsys subpgm_id 269
constant length: INTEGER := R'length;
begin
return STD_LOGIC_VECTOR (
unsigned_plus(-- pragma label plus
CONV_UNSIGNED(L, length), CONV_UNSIGNED(R, length)));
end;
function "+"(L: SIGNED; R: STD_ULOGIC) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
-- synopsys subpgm_id 270
constant length: INTEGER := L'length;
begin
return STD_LOGIC_VECTOR (
plus(-- pragma label plus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)));
end;
function "+"(L: STD_ULOGIC; R: SIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
-- synopsys subpgm_id 271
constant length: INTEGER := R'length;
begin
return STD_LOGIC_VECTOR (
plus(-- pragma label plus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)));
end;
function "-"(L: UNSIGNED; R: UNSIGNED) return UNSIGNED is
-- pragma label_applies_to minus
-- synopsys subpgm_id 248
constant length: INTEGER := max(L'length, R'length);
begin
return unsigned_minus(CONV_UNSIGNED(L, length),
CONV_UNSIGNED(R, length)); -- pragma label minus
end;
function "-"(L: SIGNED; R: SIGNED) return SIGNED is
-- pragma label_applies_to minus
-- synopsys subpgm_id 249
constant length: INTEGER := max(L'length, R'length);
begin
return minus(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label minus
end;
function "-"(L: UNSIGNED; R: SIGNED) return SIGNED is
-- pragma label_applies_to minus
-- synopsys subpgm_id 250
constant length: INTEGER := max(L'length + 1, R'length);
begin
return minus(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label minus
end;
function "-"(L: SIGNED; R: UNSIGNED) return SIGNED is
-- pragma label_applies_to minus
-- synopsys subpgm_id 251
constant length: INTEGER := max(L'length, R'length + 1);
begin
return minus(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label minus
end;
function "-"(L: UNSIGNED; R: INTEGER) return UNSIGNED is
-- pragma label_applies_to minus
-- synopsys subpgm_id 252
constant length: INTEGER := L'length + 1;
begin
return CONV_UNSIGNED(
minus( -- pragma label minus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)), length-1);
end;
function "-"(L: INTEGER; R: UNSIGNED) return UNSIGNED is
-- pragma label_applies_to minus
-- synopsys subpgm_id 253
constant length: INTEGER := R'length + 1;
begin
return CONV_UNSIGNED(
minus( -- pragma label minus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)), length-1);
end;
function "-"(L: SIGNED; R: INTEGER) return SIGNED is
-- pragma label_applies_to minus
-- synopsys subpgm_id 254
constant length: INTEGER := L'length;
begin
return minus(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label minus
end;
function "-"(L: INTEGER; R: SIGNED) return SIGNED is
-- pragma label_applies_to minus
-- synopsys subpgm_id 255
constant length: INTEGER := R'length;
begin
return minus(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label minus
end;
function "-"(L: UNSIGNED; R: STD_ULOGIC) return UNSIGNED is
-- pragma label_applies_to minus
-- synopsys subpgm_id 256
constant length: INTEGER := L'length + 1;
begin
return CONV_UNSIGNED(
minus( -- pragma label minus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)), length-1);
end;
function "-"(L: STD_ULOGIC; R: UNSIGNED) return UNSIGNED is
-- pragma label_applies_to minus
-- synopsys subpgm_id 257
constant length: INTEGER := R'length + 1;
begin
return CONV_UNSIGNED(
minus( -- pragma label minus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)), length-1);
end;
function "-"(L: SIGNED; R: STD_ULOGIC) return SIGNED is
-- pragma label_applies_to minus
-- synopsys subpgm_id 258
constant length: INTEGER := L'length;
begin
return minus(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label minus
end;
function "-"(L: STD_ULOGIC; R: SIGNED) return SIGNED is
-- pragma label_applies_to minus
-- synopsys subpgm_id 259
constant length: INTEGER := R'length;
begin
return minus(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label minus
end;
function "-"(L: UNSIGNED; R: UNSIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
-- synopsys subpgm_id 272
constant length: INTEGER := max(L'length, R'length);
begin
return STD_LOGIC_VECTOR (
unsigned_minus(-- pragma label minus
CONV_UNSIGNED(L, length), CONV_UNSIGNED(R, length)));
end;
function "-"(L: SIGNED; R: SIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
-- synopsys subpgm_id 273
constant length: INTEGER := max(L'length, R'length);
begin
return STD_LOGIC_VECTOR (
minus(-- pragma label minus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)));
end;
function "-"(L: UNSIGNED; R: SIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
-- synopsys subpgm_id 274
constant length: INTEGER := max(L'length + 1, R'length);
begin
return STD_LOGIC_VECTOR (
minus(-- pragma label minus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)));
end;
function "-"(L: SIGNED; R: UNSIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
-- synopsys subpgm_id 275
constant length: INTEGER := max(L'length, R'length + 1);
begin
return STD_LOGIC_VECTOR (
minus(-- pragma label minus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)));
end;
function "-"(L: UNSIGNED; R: INTEGER) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
-- synopsys subpgm_id 276
constant length: INTEGER := L'length + 1;
begin
return STD_LOGIC_VECTOR (CONV_UNSIGNED(
minus( -- pragma label minus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)), length-1));
end;
function "-"(L: INTEGER; R: UNSIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
-- synopsys subpgm_id 277
constant length: INTEGER := R'length + 1;
begin
return STD_LOGIC_VECTOR (CONV_UNSIGNED(
minus( -- pragma label minus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)), length-1));
end;
function "-"(L: SIGNED; R: INTEGER) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
-- synopsys subpgm_id 278
constant length: INTEGER := L'length;
begin
return STD_LOGIC_VECTOR (
minus(-- pragma label minus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)));
end;
function "-"(L: INTEGER; R: SIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
-- synopsys subpgm_id 279
constant length: INTEGER := R'length;
begin
return STD_LOGIC_VECTOR (
minus(-- pragma label minus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)));
end;
function "-"(L: UNSIGNED; R: STD_ULOGIC) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
-- synopsys subpgm_id 280
constant length: INTEGER := L'length + 1;
begin
return STD_LOGIC_VECTOR (CONV_UNSIGNED(
minus( -- pragma label minus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)), length-1));
end;
function "-"(L: STD_ULOGIC; R: UNSIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
-- synopsys subpgm_id 281
constant length: INTEGER := R'length + 1;
begin
return STD_LOGIC_VECTOR (CONV_UNSIGNED(
minus( -- pragma label minus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)), length-1));
end;
function "-"(L: SIGNED; R: STD_ULOGIC) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
-- synopsys subpgm_id 282
constant length: INTEGER := L'length;
begin
return STD_LOGIC_VECTOR (
minus(-- pragma label minus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)));
end;
function "-"(L: STD_ULOGIC; R: SIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
-- synopsys subpgm_id 283
constant length: INTEGER := R'length;
begin
return STD_LOGIC_VECTOR (
minus(-- pragma label minus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)));
end;
function "+"(L: UNSIGNED) return UNSIGNED is
-- synopsys subpgm_id 284
begin
return L;
end;
function "+"(L: SIGNED) return SIGNED is
-- synopsys subpgm_id 285
begin
return L;
end;
function "-"(L: SIGNED) return SIGNED is
-- pragma label_applies_to minus
-- synopsys subpgm_id 286
begin
return 0 - L; -- pragma label minus
end;
function "ABS"(L: SIGNED) return SIGNED is
-- synopsys subpgm_id 287
begin
if (L(L'left) = '0' or L(L'left) = 'L') then
return L;
else
return 0 - L;
end if;
end;
function "+"(L: UNSIGNED) return STD_LOGIC_VECTOR is
-- synopsys subpgm_id 289
begin
return STD_LOGIC_VECTOR (L);
end;
function "+"(L: SIGNED) return STD_LOGIC_VECTOR is
-- synopsys subpgm_id 290
begin
return STD_LOGIC_VECTOR (L);
end;
function "-"(L: SIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
-- synopsys subpgm_id 292
variable tmp: SIGNED(L'length-1 downto 0);
begin
tmp := 0 - L; -- pragma label minus
return STD_LOGIC_VECTOR (tmp);
end;
function "ABS"(L: SIGNED) return STD_LOGIC_VECTOR is
-- synopsys subpgm_id 294
variable tmp: SIGNED(L'length-1 downto 0);
begin
if (L(L'left) = '0' or L(L'left) = 'L') then
return STD_LOGIC_VECTOR (L);
else
tmp := 0 - L;
return STD_LOGIC_VECTOR (tmp);
end if;
end;
-- Type propagation function which returns the type BOOLEAN
function UNSIGNED_RETURN_BOOLEAN(A,B: UNSIGNED) return BOOLEAN is
variable Z: BOOLEAN;
-- pragma return_port_name Z
begin
return(Z);
end;
-- Type propagation function which returns the type BOOLEAN
function SIGNED_RETURN_BOOLEAN(A,B: SIGNED) return BOOLEAN is
variable Z: BOOLEAN;
-- pragma return_port_name Z
begin
return(Z);
end;
-- compare two signed numbers of the same length
-- both arrays must have range (msb downto 0)
function is_less(A, B: SIGNED) return BOOLEAN is
constant sign: INTEGER := A'left;
variable a_is_0, b_is_1, result : boolean;
-- pragma map_to_operator LT_TC_OP
-- pragma type_function SIGNED_RETURN_BOOLEAN
-- pragma return_port_name Z
begin
if A(sign) /= B(sign) then
result := A(sign) = '1';
else
result := FALSE;
for i in 0 to sign-1 loop
a_is_0 := A(i) = '0';
b_is_1 := B(i) = '1';
result := (a_is_0 and b_is_1) or
(a_is_0 and result) or
(b_is_1 and result);
end loop;
end if;
return result;
end;
-- compare two signed numbers of the same length
-- both arrays must have range (msb downto 0)
function is_less_or_equal(A, B: SIGNED) return BOOLEAN is
constant sign: INTEGER := A'left;
variable a_is_0, b_is_1, result : boolean;
-- pragma map_to_operator LEQ_TC_OP
-- pragma type_function SIGNED_RETURN_BOOLEAN
-- pragma return_port_name Z
begin
if A(sign) /= B(sign) then
result := A(sign) = '1';
else
result := TRUE;
for i in 0 to sign-1 loop
a_is_0 := A(i) = '0';
b_is_1 := B(i) = '1';
result := (a_is_0 and b_is_1) or
(a_is_0 and result) or
(b_is_1 and result);
end loop;
end if;
return result;
end;
-- compare two unsigned numbers of the same length
-- both arrays must have range (msb downto 0)
function unsigned_is_less(A, B: UNSIGNED) return BOOLEAN is
constant sign: INTEGER := A'left;
variable a_is_0, b_is_1, result : boolean;
-- pragma map_to_operator LT_UNS_OP
-- pragma type_function UNSIGNED_RETURN_BOOLEAN
-- pragma return_port_name Z
begin
result := FALSE;
for i in 0 to sign loop
a_is_0 := A(i) = '0';
b_is_1 := B(i) = '1';
result := (a_is_0 and b_is_1) or
(a_is_0 and result) or
(b_is_1 and result);
end loop;
return result;
end;
-- compare two unsigned numbers of the same length
-- both arrays must have range (msb downto 0)
function unsigned_is_less_or_equal(A, B: UNSIGNED) return BOOLEAN is
constant sign: INTEGER := A'left;
variable a_is_0, b_is_1, result : boolean;
-- pragma map_to_operator LEQ_UNS_OP
-- pragma type_function UNSIGNED_RETURN_BOOLEAN
-- pragma return_port_name Z
begin
result := TRUE;
for i in 0 to sign loop
a_is_0 := A(i) = '0';
b_is_1 := B(i) = '1';
result := (a_is_0 and b_is_1) or
(a_is_0 and result) or
(b_is_1 and result);
end loop;
return result;
end;
function "<"(L: UNSIGNED; R: UNSIGNED) return BOOLEAN is
-- pragma label_applies_to lt
-- synopsys subpgm_id 305
constant length: INTEGER := max(L'length, R'length);
begin
return unsigned_is_less(CONV_UNSIGNED(L, length),
CONV_UNSIGNED(R, length)); -- pragma label lt
end;
function "<"(L: SIGNED; R: SIGNED) return BOOLEAN is
-- pragma label_applies_to lt
-- synopsys subpgm_id 306
constant length: INTEGER := max(L'length, R'length);
begin
return is_less(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label lt
end;
function "<"(L: UNSIGNED; R: SIGNED) return BOOLEAN is
-- pragma label_applies_to lt
-- synopsys subpgm_id 307
constant length: INTEGER := max(L'length + 1, R'length);
begin
return is_less(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label lt
end;
function "<"(L: SIGNED; R: UNSIGNED) return BOOLEAN is
-- pragma label_applies_to lt
-- synopsys subpgm_id 308
constant length: INTEGER := max(L'length, R'length + 1);
begin
return is_less(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label lt
end;
function "<"(L: UNSIGNED; R: INTEGER) return BOOLEAN is
-- pragma label_applies_to lt
-- synopsys subpgm_id 309
constant length: INTEGER := L'length + 1;
begin
return is_less(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label lt
end;
function "<"(L: INTEGER; R: UNSIGNED) return BOOLEAN is
-- pragma label_applies_to lt
-- synopsys subpgm_id 310
constant length: INTEGER := R'length + 1;
begin
return is_less(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label lt
end;
function "<"(L: SIGNED; R: INTEGER) return BOOLEAN is
-- pragma label_applies_to lt
-- synopsys subpgm_id 311
constant length: INTEGER := L'length;
begin
return is_less(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label lt
end;
function "<"(L: INTEGER; R: SIGNED) return BOOLEAN is
-- pragma label_applies_to lt
-- synopsys subpgm_id 312
constant length: INTEGER := R'length;
begin
return is_less(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label lt
end;
function "<="(L: UNSIGNED; R: UNSIGNED) return BOOLEAN is
-- pragma label_applies_to leq
-- synopsys subpgm_id 314
constant length: INTEGER := max(L'length, R'length);
begin
return unsigned_is_less_or_equal(CONV_UNSIGNED(L, length),
CONV_UNSIGNED(R, length)); -- pragma label leq
end;
function "<="(L: SIGNED; R: SIGNED) return BOOLEAN is
-- pragma label_applies_to leq
-- synopsys subpgm_id 315
constant length: INTEGER := max(L'length, R'length);
begin
return is_less_or_equal(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label leq
end;
function "<="(L: UNSIGNED; R: SIGNED) return BOOLEAN is
-- pragma label_applies_to leq
-- synopsys subpgm_id 316
constant length: INTEGER := max(L'length + 1, R'length);
begin
return is_less_or_equal(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label leq
end;
function "<="(L: SIGNED; R: UNSIGNED) return BOOLEAN is
-- pragma label_applies_to leq
-- synopsys subpgm_id 317
constant length: INTEGER := max(L'length, R'length + 1);
begin
return is_less_or_equal(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label leq
end;
function "<="(L: UNSIGNED; R: INTEGER) return BOOLEAN is
-- pragma label_applies_to leq
-- synopsys subpgm_id 318
constant length: INTEGER := L'length + 1;
begin
return is_less_or_equal(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label leq
end;
function "<="(L: INTEGER; R: UNSIGNED) return BOOLEAN is
-- pragma label_applies_to leq
-- synopsys subpgm_id 319
constant length: INTEGER := R'length + 1;
begin
return is_less_or_equal(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label leq
end;
function "<="(L: SIGNED; R: INTEGER) return BOOLEAN is
-- pragma label_applies_to leq
-- synopsys subpgm_id 320
constant length: INTEGER := L'length;
begin
return is_less_or_equal(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label leq
end;
function "<="(L: INTEGER; R: SIGNED) return BOOLEAN is
-- pragma label_applies_to leq
-- synopsys subpgm_id 321
constant length: INTEGER := R'length;
begin
return is_less_or_equal(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label leq
end;
function ">"(L: UNSIGNED; R: UNSIGNED) return BOOLEAN is
-- pragma label_applies_to gt
-- synopsys subpgm_id 323
constant length: INTEGER := max(L'length, R'length);
begin
return unsigned_is_less(CONV_UNSIGNED(R, length),
CONV_UNSIGNED(L, length)); -- pragma label gt
end;
function ">"(L: SIGNED; R: SIGNED) return BOOLEAN is
-- pragma label_applies_to gt
-- synopsys subpgm_id 324
constant length: INTEGER := max(L'length, R'length);
begin
return is_less(CONV_SIGNED(R, length),
CONV_SIGNED(L, length)); -- pragma label gt
end;
function ">"(L: UNSIGNED; R: SIGNED) return BOOLEAN is
-- pragma label_applies_to gt
-- synopsys subpgm_id 325
constant length: INTEGER := max(L'length + 1, R'length);
begin
return is_less(CONV_SIGNED(R, length),
CONV_SIGNED(L, length)); -- pragma label gt
end;
function ">"(L: SIGNED; R: UNSIGNED) return BOOLEAN is
-- pragma label_applies_to gt
-- synopsys subpgm_id 326
constant length: INTEGER := max(L'length, R'length + 1);
begin
return is_less(CONV_SIGNED(R, length),
CONV_SIGNED(L, length)); -- pragma label gt
end;
function ">"(L: UNSIGNED; R: INTEGER) return BOOLEAN is
-- pragma label_applies_to gt
-- synopsys subpgm_id 327
constant length: INTEGER := L'length + 1;
begin
return is_less(CONV_SIGNED(R, length),
CONV_SIGNED(L, length)); -- pragma label gt
end;
function ">"(L: INTEGER; R: UNSIGNED) return BOOLEAN is
-- pragma label_applies_to gt
-- synopsys subpgm_id 328
constant length: INTEGER := R'length + 1;
begin
return is_less(CONV_SIGNED(R, length),
CONV_SIGNED(L, length)); -- pragma label gt
end;
function ">"(L: SIGNED; R: INTEGER) return BOOLEAN is
-- pragma label_applies_to gt
-- synopsys subpgm_id 329
constant length: INTEGER := L'length;
begin
return is_less(CONV_SIGNED(R, length),
CONV_SIGNED(L, length)); -- pragma label gt
end;
function ">"(L: INTEGER; R: SIGNED) return BOOLEAN is
-- pragma label_applies_to gt
-- synopsys subpgm_id 330
constant length: INTEGER := R'length;
begin
return is_less(CONV_SIGNED(R, length),
CONV_SIGNED(L, length)); -- pragma label gt
end;
function ">="(L: UNSIGNED; R: UNSIGNED) return BOOLEAN is
-- pragma label_applies_to geq
-- synopsys subpgm_id 332
constant length: INTEGER := max(L'length, R'length);
begin
return unsigned_is_less_or_equal(CONV_UNSIGNED(R, length),
CONV_UNSIGNED(L, length)); -- pragma label geq
end;
function ">="(L: SIGNED; R: SIGNED) return BOOLEAN is
-- pragma label_applies_to geq
-- synopsys subpgm_id 333
constant length: INTEGER := max(L'length, R'length);
begin
return is_less_or_equal(CONV_SIGNED(R, length),
CONV_SIGNED(L, length)); -- pragma label geq
end;
function ">="(L: UNSIGNED; R: SIGNED) return BOOLEAN is
-- pragma label_applies_to geq
-- synopsys subpgm_id 334
constant length: INTEGER := max(L'length + 1, R'length);
begin
return is_less_or_equal(CONV_SIGNED(R, length),
CONV_SIGNED(L, length)); -- pragma label geq
end;
function ">="(L: SIGNED; R: UNSIGNED) return BOOLEAN is
-- pragma label_applies_to geq
-- synopsys subpgm_id 335
constant length: INTEGER := max(L'length, R'length + 1);
begin
return is_less_or_equal(CONV_SIGNED(R, length),
CONV_SIGNED(L, length)); -- pragma label geq
end;
function ">="(L: UNSIGNED; R: INTEGER) return BOOLEAN is
-- pragma label_applies_to geq
-- synopsys subpgm_id 336
constant length: INTEGER := L'length + 1;
begin
return is_less_or_equal(CONV_SIGNED(R, length),
CONV_SIGNED(L, length)); -- pragma label geq
end;
function ">="(L: INTEGER; R: UNSIGNED) return BOOLEAN is
-- pragma label_applies_to geq
-- synopsys subpgm_id 337
constant length: INTEGER := R'length + 1;
begin
return is_less_or_equal(CONV_SIGNED(R, length),
CONV_SIGNED(L, length)); -- pragma label geq
end;
function ">="(L: SIGNED; R: INTEGER) return BOOLEAN is
-- pragma label_applies_to geq
-- synopsys subpgm_id 338
constant length: INTEGER := L'length;
begin
return is_less_or_equal(CONV_SIGNED(R, length),
CONV_SIGNED(L, length)); -- pragma label geq
end;
function ">="(L: INTEGER; R: SIGNED) return BOOLEAN is
-- pragma label_applies_to geq
-- synopsys subpgm_id 339
constant length: INTEGER := R'length;
begin
return is_less_or_equal(CONV_SIGNED(R, length),
CONV_SIGNED(L, length)); -- pragma label geq
end;
-- for internal use only. Assumes SIGNED arguments of equal length.
function bitwise_eql(L: STD_ULOGIC_VECTOR; R: STD_ULOGIC_VECTOR)
return BOOLEAN is
-- pragma built_in SYN_EQL
begin
for i in L'range loop
if L(i) /= R(i) then
return FALSE;
end if;
end loop;
return TRUE;
end;
-- for internal use only. Assumes SIGNED arguments of equal length.
function bitwise_neq(L: STD_ULOGIC_VECTOR; R: STD_ULOGIC_VECTOR)
return BOOLEAN is
-- pragma built_in SYN_NEQ
begin
for i in L'range loop
if L(i) /= R(i) then
return TRUE;
end if;
end loop;
return FALSE;
end;
function "="(L: UNSIGNED; R: UNSIGNED) return BOOLEAN is
-- synopsys subpgm_id 341
constant length: INTEGER := max(L'length, R'length);
begin
return bitwise_eql( STD_ULOGIC_VECTOR( CONV_UNSIGNED(L, length) ),
STD_ULOGIC_VECTOR( CONV_UNSIGNED(R, length) ) );
end;
function "="(L: SIGNED; R: SIGNED) return BOOLEAN is
-- synopsys subpgm_id 342
constant length: INTEGER := max(L'length, R'length);
begin
return bitwise_eql( STD_ULOGIC_VECTOR( CONV_SIGNED(L, length) ),
STD_ULOGIC_VECTOR( CONV_SIGNED(R, length) ) );
end;
function "="(L: UNSIGNED; R: SIGNED) return BOOLEAN is
-- synopsys subpgm_id 343
constant length: INTEGER := max(L'length + 1, R'length);
begin
return bitwise_eql( STD_ULOGIC_VECTOR( CONV_SIGNED(L, length) ),
STD_ULOGIC_VECTOR( CONV_SIGNED(R, length) ) );
end;
function "="(L: SIGNED; R: UNSIGNED) return BOOLEAN is
-- synopsys subpgm_id 344
constant length: INTEGER := max(L'length, R'length + 1);
begin
return bitwise_eql( STD_ULOGIC_VECTOR( CONV_SIGNED(L, length) ),
STD_ULOGIC_VECTOR( CONV_SIGNED(R, length) ) );
end;
function "="(L: UNSIGNED; R: INTEGER) return BOOLEAN is
-- synopsys subpgm_id 345
constant length: INTEGER := L'length + 1;
begin
return bitwise_eql( STD_ULOGIC_VECTOR( CONV_SIGNED(L, length) ),
STD_ULOGIC_VECTOR( CONV_SIGNED(R, length) ) );
end;
function "="(L: INTEGER; R: UNSIGNED) return BOOLEAN is
-- synopsys subpgm_id 346
constant length: INTEGER := R'length + 1;
begin
return bitwise_eql( STD_ULOGIC_VECTOR( CONV_SIGNED(L, length) ),
STD_ULOGIC_VECTOR( CONV_SIGNED(R, length) ) );
end;
function "="(L: SIGNED; R: INTEGER) return BOOLEAN is
-- synopsys subpgm_id 347
constant length: INTEGER := L'length;
begin
return bitwise_eql( STD_ULOGIC_VECTOR( CONV_SIGNED(L, length) ),
STD_ULOGIC_VECTOR( CONV_SIGNED(R, length) ) );
end;
function "="(L: INTEGER; R: SIGNED) return BOOLEAN is
-- synopsys subpgm_id 348
constant length: INTEGER := R'length;
begin
return bitwise_eql( STD_ULOGIC_VECTOR( CONV_SIGNED(L, length) ),
STD_ULOGIC_VECTOR( CONV_SIGNED(R, length) ) );
end;
function "/="(L: UNSIGNED; R: UNSIGNED) return BOOLEAN is
-- synopsys subpgm_id 350
constant length: INTEGER := max(L'length, R'length);
begin
return bitwise_neq( STD_ULOGIC_VECTOR( CONV_UNSIGNED(L, length) ),
STD_ULOGIC_VECTOR( CONV_UNSIGNED(R, length) ) );
end;
function "/="(L: SIGNED; R: SIGNED) return BOOLEAN is
-- synopsys subpgm_id 351
constant length: INTEGER := max(L'length, R'length);
begin
return bitwise_neq( STD_ULOGIC_VECTOR( CONV_SIGNED(L, length) ),
STD_ULOGIC_VECTOR( CONV_SIGNED(R, length) ) );
end;
function "/="(L: UNSIGNED; R: SIGNED) return BOOLEAN is
-- synopsys subpgm_id 352
constant length: INTEGER := max(L'length + 1, R'length);
begin
return bitwise_neq( STD_ULOGIC_VECTOR( CONV_SIGNED(L, length) ),
STD_ULOGIC_VECTOR( CONV_SIGNED(R, length) ) );
end;
function "/="(L: SIGNED; R: UNSIGNED) return BOOLEAN is
-- synopsys subpgm_id 353
constant length: INTEGER := max(L'length, R'length + 1);
begin
return bitwise_neq( STD_ULOGIC_VECTOR( CONV_SIGNED(L, length) ),
STD_ULOGIC_VECTOR( CONV_SIGNED(R, length) ) );
end;
function "/="(L: UNSIGNED; R: INTEGER) return BOOLEAN is
-- synopsys subpgm_id 354
constant length: INTEGER := L'length + 1;
begin
return bitwise_neq( STD_ULOGIC_VECTOR( CONV_SIGNED(L, length) ),
STD_ULOGIC_VECTOR( CONV_SIGNED(R, length) ) );
end;
function "/="(L: INTEGER; R: UNSIGNED) return BOOLEAN is
-- synopsys subpgm_id 355
constant length: INTEGER := R'length + 1;
begin
return bitwise_neq( STD_ULOGIC_VECTOR( CONV_SIGNED(L, length) ),
STD_ULOGIC_VECTOR( CONV_SIGNED(R, length) ) );
end;
function "/="(L: SIGNED; R: INTEGER) return BOOLEAN is
-- synopsys subpgm_id 356
constant length: INTEGER := L'length;
begin
return bitwise_neq( STD_ULOGIC_VECTOR( CONV_SIGNED(L, length) ),
STD_ULOGIC_VECTOR( CONV_SIGNED(R, length) ) );
end;
function "/="(L: INTEGER; R: SIGNED) return BOOLEAN is
-- synopsys subpgm_id 357
constant length: INTEGER := R'length;
begin
return bitwise_neq( STD_ULOGIC_VECTOR( CONV_SIGNED(L, length) ),
STD_ULOGIC_VECTOR( CONV_SIGNED(R, length) ) );
end;
function SHL(ARG: UNSIGNED; COUNT: UNSIGNED) return UNSIGNED is
-- synopsys subpgm_id 358
constant control_msb: INTEGER := COUNT'length - 1;
variable control: UNSIGNED (control_msb downto 0);
constant result_msb: INTEGER := ARG'length-1;
subtype rtype is UNSIGNED (result_msb downto 0);
variable result, temp: rtype;
begin
control := MAKE_BINARY(COUNT);
-- synopsys synthesis_off
if (control(0) = 'X') then
result := rtype'(others => 'X');
return result;
end if;
-- synopsys synthesis_on
result := ARG;
for i in 0 to control_msb loop
if control(i) = '1' then
temp := rtype'(others => '0');
if 2**i <= result_msb then
temp(result_msb downto 2**i) :=
result(result_msb - 2**i downto 0);
end if;
result := temp;
end if;
end loop;
return result;
end;
function SHL(ARG: SIGNED; COUNT: UNSIGNED) return SIGNED is
-- synopsys subpgm_id 359
constant control_msb: INTEGER := COUNT'length - 1;
variable control: UNSIGNED (control_msb downto 0);
constant result_msb: INTEGER := ARG'length-1;
subtype rtype is SIGNED (result_msb downto 0);
variable result, temp: rtype;
begin
control := MAKE_BINARY(COUNT);
-- synopsys synthesis_off
if (control(0) = 'X') then
result := rtype'(others => 'X');
return result;
end if;
-- synopsys synthesis_on
result := ARG;
for i in 0 to control_msb loop
if control(i) = '1' then
temp := rtype'(others => '0');
if 2**i <= result_msb then
temp(result_msb downto 2**i) :=
result(result_msb - 2**i downto 0);
end if;
result := temp;
end if;
end loop;
return result;
end;
function SHR(ARG: UNSIGNED; COUNT: UNSIGNED) return UNSIGNED is
-- synopsys subpgm_id 360
constant control_msb: INTEGER := COUNT'length - 1;
variable control: UNSIGNED (control_msb downto 0);
constant result_msb: INTEGER := ARG'length-1;
subtype rtype is UNSIGNED (result_msb downto 0);
variable result, temp: rtype;
begin
control := MAKE_BINARY(COUNT);
-- synopsys synthesis_off
if (control(0) = 'X') then
result := rtype'(others => 'X');
return result;
end if;
-- synopsys synthesis_on
result := ARG;
for i in 0 to control_msb loop
if control(i) = '1' then
temp := rtype'(others => '0');
if 2**i <= result_msb then
temp(result_msb - 2**i downto 0) :=
result(result_msb downto 2**i);
end if;
result := temp;
end if;
end loop;
return result;
end;
function SHR(ARG: SIGNED; COUNT: UNSIGNED) return SIGNED is
-- synopsys subpgm_id 361
constant control_msb: INTEGER := COUNT'length - 1;
variable control: UNSIGNED (control_msb downto 0);
constant result_msb: INTEGER := ARG'length-1;
subtype rtype is SIGNED (result_msb downto 0);
variable result, temp: rtype;
variable sign_bit: STD_ULOGIC;
begin
control := MAKE_BINARY(COUNT);
-- synopsys synthesis_off
if (control(0) = 'X') then
result := rtype'(others => 'X');
return result;
end if;
-- synopsys synthesis_on
result := ARG;
sign_bit := ARG(ARG'left);
for i in 0 to control_msb loop
if control(i) = '1' then
temp := rtype'(others => sign_bit);
if 2**i <= result_msb then
temp(result_msb - 2**i downto 0) :=
result(result_msb downto 2**i);
end if;
result := temp;
end if;
end loop;
return result;
end;
function CONV_INTEGER(ARG: INTEGER) return INTEGER is
-- synopsys subpgm_id 365
begin
return ARG;
end;
function CONV_INTEGER(ARG: UNSIGNED) return INTEGER is
variable result: INTEGER;
variable tmp: STD_ULOGIC;
-- synopsys built_in SYN_UNSIGNED_TO_INTEGER
-- synopsys subpgm_id 366
begin
-- synopsys synthesis_off
assert ARG'length <= 31
report "ARG is too large in CONV_INTEGER"
severity FAILURE;
result := 0;
for i in ARG'range loop
result := result * 2;
tmp := tbl_BINARY(ARG(i));
if tmp = '1' then
result := result + 1;
elsif tmp = 'X' then
assert no_warning
report "There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es)."
severity warning;
assert no_warning
report "CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0."
severity WARNING;
return 0;
end if;
end loop;
return result;
-- synopsys synthesis_on
end;
function CONV_INTEGER(ARG: SIGNED) return INTEGER is
variable result: INTEGER;
variable tmp: STD_ULOGIC;
-- synopsys built_in SYN_SIGNED_TO_INTEGER
-- synopsys subpgm_id 367
begin
-- synopsys synthesis_off
assert ARG'length <= 32
report "ARG is too large in CONV_INTEGER"
severity FAILURE;
result := 0;
for i in ARG'range loop
if i /= ARG'left then
result := result * 2;
tmp := tbl_BINARY(ARG(i));
if tmp = '1' then
result := result + 1;
elsif tmp = 'X' then
assert no_warning
report "There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es)."
severity warning;
assert no_warning
report "CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0."
severity WARNING;
return 0;
end if;
end if;
end loop;
tmp := MAKE_BINARY(ARG(ARG'left));
if tmp = '1' then
if ARG'length = 32 then
result := (result - 2**30) - 2**30;
else
result := result - (2 ** (ARG'length-1));
end if;
end if;
return result;
-- synopsys synthesis_on
end;
function CONV_INTEGER(ARG: STD_ULOGIC) return SMALL_INT is
variable tmp: STD_ULOGIC;
-- synopsys built_in SYN_FEED_THRU
-- synopsys subpgm_id 370
begin
-- synopsys synthesis_off
tmp := tbl_BINARY(ARG);
if tmp = '1' then
return 1;
elsif tmp = 'X' then
assert no_warning
report "CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0."
severity WARNING;
return 0;
else
return 0;
end if;
-- synopsys synthesis_on
end;
-- convert an integer to a unsigned STD_ULOGIC_VECTOR
function CONV_UNSIGNED(ARG: INTEGER; SIZE: INTEGER) return UNSIGNED is
variable result: UNSIGNED(SIZE-1 downto 0);
variable temp: integer;
-- synopsys built_in SYN_INTEGER_TO_UNSIGNED
-- synopsys subpgm_id 371
begin
-- synopsys synthesis_off
temp := ARG;
for i in 0 to SIZE-1 loop
if (temp mod 2) = 1 then
result(i) := '1';
else
result(i) := '0';
end if;
if temp > 0 then
temp := temp / 2;
else
temp := (temp - 1) / 2; -- simulate ASR
end if;
end loop;
return result;
-- synopsys synthesis_on
end;
function CONV_UNSIGNED(ARG: UNSIGNED; SIZE: INTEGER) return UNSIGNED is
constant msb: INTEGER := min(ARG'length, SIZE) - 1;
subtype rtype is UNSIGNED (SIZE-1 downto 0);
variable new_bounds: UNSIGNED (ARG'length-1 downto 0);
variable result: rtype;
-- synopsys built_in SYN_ZERO_EXTEND
-- synopsys subpgm_id 372
begin
-- synopsys synthesis_off
new_bounds := MAKE_BINARY(ARG);
if (new_bounds(0) = 'X') then
result := rtype'(others => 'X');
return result;
end if;
result := rtype'(others => '0');
result(msb downto 0) := new_bounds(msb downto 0);
return result;
-- synopsys synthesis_on
end;
function CONV_UNSIGNED(ARG: SIGNED; SIZE: INTEGER) return UNSIGNED is
constant msb: INTEGER := min(ARG'length, SIZE) - 1;
subtype rtype is UNSIGNED (SIZE-1 downto 0);
variable new_bounds: UNSIGNED (ARG'length-1 downto 0);
variable result: rtype;
-- synopsys built_in SYN_SIGN_EXTEND
-- synopsys subpgm_id 373
begin
-- synopsys synthesis_off
new_bounds := MAKE_BINARY(ARG);
if (new_bounds(0) = 'X') then
result := rtype'(others => 'X');
return result;
end if;
result := rtype'(others => new_bounds(new_bounds'left));
result(msb downto 0) := new_bounds(msb downto 0);
return result;
-- synopsys synthesis_on
end;
function CONV_UNSIGNED(ARG: STD_ULOGIC; SIZE: INTEGER) return UNSIGNED is
subtype rtype is UNSIGNED (SIZE-1 downto 0);
variable result: rtype;
-- synopsys built_in SYN_ZERO_EXTEND
-- synopsys subpgm_id 375
begin
-- synopsys synthesis_off
result := rtype'(others => '0');
result(0) := MAKE_BINARY(ARG);
if (result(0) = 'X') then
result := rtype'(others => 'X');
end if;
return result;
-- synopsys synthesis_on
end;
-- convert an integer to a 2's complement STD_ULOGIC_VECTOR
function CONV_SIGNED(ARG: INTEGER; SIZE: INTEGER) return SIGNED is
variable result: SIGNED (SIZE-1 downto 0);
variable temp: integer;
-- synopsys built_in SYN_INTEGER_TO_SIGNED
-- synopsys subpgm_id 376
begin
-- synopsys synthesis_off
temp := ARG;
for i in 0 to SIZE-1 loop
if (temp mod 2) = 1 then
result(i) := '1';
else
result(i) := '0';
end if;
if temp > 0 then
temp := temp / 2;
elsif (temp > integer'low) then
temp := (temp - 1) / 2; -- simulate ASR
else
temp := temp / 2; -- simulate ASR
end if;
end loop;
return result;
-- synopsys synthesis_on
end;
function CONV_SIGNED(ARG: UNSIGNED; SIZE: INTEGER) return SIGNED is
constant msb: INTEGER := min(ARG'length, SIZE) - 1;
subtype rtype is SIGNED (SIZE-1 downto 0);
variable new_bounds : SIGNED (ARG'length-1 downto 0);
variable result: rtype;
-- synopsys built_in SYN_ZERO_EXTEND
-- synopsys subpgm_id 377
begin
-- synopsys synthesis_off
new_bounds := MAKE_BINARY(ARG);
if (new_bounds(0) = 'X') then
result := rtype'(others => 'X');
return result;
end if;
result := rtype'(others => '0');
result(msb downto 0) := new_bounds(msb downto 0);
return result;
-- synopsys synthesis_on
end;
function CONV_SIGNED(ARG: SIGNED; SIZE: INTEGER) return SIGNED is
constant msb: INTEGER := min(ARG'length, SIZE) - 1;
subtype rtype is SIGNED (SIZE-1 downto 0);
variable new_bounds : SIGNED (ARG'length-1 downto 0);
variable result: rtype;
-- synopsys built_in SYN_SIGN_EXTEND
-- synopsys subpgm_id 378
begin
-- synopsys synthesis_off
new_bounds := MAKE_BINARY(ARG);
if (new_bounds(0) = 'X') then
result := rtype'(others => 'X');
return result;
end if;
result := rtype'(others => new_bounds(new_bounds'left));
result(msb downto 0) := new_bounds(msb downto 0);
return result;
-- synopsys synthesis_on
end;
function CONV_SIGNED(ARG: STD_ULOGIC; SIZE: INTEGER) return SIGNED is
subtype rtype is SIGNED (SIZE-1 downto 0);
variable result: rtype;
-- synopsys built_in SYN_ZERO_EXTEND
-- synopsys subpgm_id 380
begin
-- synopsys synthesis_off
result := rtype'(others => '0');
result(0) := MAKE_BINARY(ARG);
if (result(0) = 'X') then
result := rtype'(others => 'X');
end if;
return result;
-- synopsys synthesis_on
end;
-- convert an integer to an STD_LOGIC_VECTOR
function CONV_STD_LOGIC_VECTOR(ARG: INTEGER; SIZE: INTEGER) return STD_LOGIC_VECTOR is
variable result: STD_LOGIC_VECTOR (SIZE-1 downto 0);
variable temp: integer;
-- synopsys built_in SYN_INTEGER_TO_SIGNED
-- synopsys subpgm_id 381
begin
-- synopsys synthesis_off
temp := ARG;
for i in 0 to SIZE-1 loop
if (temp mod 2) = 1 then
result(i) := '1';
else
result(i) := '0';
end if;
if temp > 0 then
temp := temp / 2;
elsif (temp > integer'low) then
temp := (temp - 1) / 2; -- simulate ASR
else
temp := temp / 2; -- simulate ASR
end if;
end loop;
return result;
-- synopsys synthesis_on
end;
function CONV_STD_LOGIC_VECTOR(ARG: UNSIGNED; SIZE: INTEGER) return STD_LOGIC_VECTOR is
constant msb: INTEGER := min(ARG'length, SIZE) - 1;
subtype rtype is STD_LOGIC_VECTOR (SIZE-1 downto 0);
variable new_bounds : STD_LOGIC_VECTOR (ARG'length-1 downto 0);
variable result: rtype;
-- synopsys built_in SYN_ZERO_EXTEND
-- synopsys subpgm_id 382
begin
-- synopsys synthesis_off
new_bounds := MAKE_BINARY(ARG);
if (new_bounds(0) = 'X') then
result := rtype'(others => 'X');
return result;
end if;
result := rtype'(others => '0');
result(msb downto 0) := new_bounds(msb downto 0);
return result;
-- synopsys synthesis_on
end;
function CONV_STD_LOGIC_VECTOR(ARG: SIGNED; SIZE: INTEGER) return STD_LOGIC_VECTOR is
constant msb: INTEGER := min(ARG'length, SIZE) - 1;
subtype rtype is STD_LOGIC_VECTOR (SIZE-1 downto 0);
variable new_bounds : STD_LOGIC_VECTOR (ARG'length-1 downto 0);
variable result: rtype;
-- synopsys built_in SYN_SIGN_EXTEND
-- synopsys subpgm_id 383
begin
-- synopsys synthesis_off
new_bounds := MAKE_BINARY(ARG);
if (new_bounds(0) = 'X') then
result := rtype'(others => 'X');
return result;
end if;
result := rtype'(others => new_bounds(new_bounds'left));
result(msb downto 0) := new_bounds(msb downto 0);
return result;
-- synopsys synthesis_on
end;
function CONV_STD_LOGIC_VECTOR(ARG: STD_ULOGIC; SIZE: INTEGER) return STD_LOGIC_VECTOR is
subtype rtype is STD_LOGIC_VECTOR (SIZE-1 downto 0);
variable result: rtype;
-- synopsys built_in SYN_ZERO_EXTEND
-- synopsys subpgm_id 384
begin
-- synopsys synthesis_off
result := rtype'(others => '0');
result(0) := MAKE_BINARY(ARG);
if (result(0) = 'X') then
result := rtype'(others => 'X');
end if;
return result;
-- synopsys synthesis_on
end;
function EXT(ARG: STD_LOGIC_VECTOR; SIZE: INTEGER)
return STD_LOGIC_VECTOR is
constant msb: INTEGER := min(ARG'length, SIZE) - 1;
subtype rtype is STD_LOGIC_VECTOR (SIZE-1 downto 0);
variable new_bounds: STD_LOGIC_VECTOR (ARG'length-1 downto 0);
variable result: rtype;
-- synopsys built_in SYN_ZERO_EXTEND
-- synopsys subpgm_id 385
begin
-- synopsys synthesis_off
new_bounds := MAKE_BINARY(ARG);
if (new_bounds(0) = 'X') then
result := rtype'(others => 'X');
return result;
end if;
result := rtype'(others => '0');
result(msb downto 0) := new_bounds(msb downto 0);
return result;
-- synopsys synthesis_on
end;
function SXT(ARG: STD_LOGIC_VECTOR; SIZE: INTEGER) return STD_LOGIC_VECTOR is
constant msb: INTEGER := min(ARG'length, SIZE) - 1;
subtype rtype is STD_LOGIC_VECTOR (SIZE-1 downto 0);
variable new_bounds : STD_LOGIC_VECTOR (ARG'length-1 downto 0);
variable result: rtype;
-- synopsys built_in SYN_SIGN_EXTEND
-- synopsys subpgm_id 386
begin
-- synopsys synthesis_off
new_bounds := MAKE_BINARY(ARG);
if (new_bounds(0) = 'X') then
result := rtype'(others => 'X');
return result;
end if;
result := rtype'(others => new_bounds(new_bounds'left));
result(msb downto 0) := new_bounds(msb downto 0);
return result;
-- synopsys synthesis_on
end;
end std_logic_arith;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_constant_GNCKXZT4CF is
generic ( HDLTYPE : string := "STD_LOGIC_VECTOR";
BitPattern : string := "0000000001100100";
width : natural := 16);
port(
output : out std_logic_vector(15 downto 0));
end entity;
architecture rtl of alt_dspbuilder_constant_GNCKXZT4CF is
Begin
-- Constant
output <= "0000000001100100";
end architecture; |
-------------------------------------------------------------------------------
-- $Id: checkbit_handler.vhd,v 1.1.2.2 2010/09/06 09:01:24 rolandp Exp $
-------------------------------------------------------------------------------
--
-- (c) Copyright [2003] - [2011] Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES
--
-------------------------------------------------------------------------------
-- Filename: gen_checkbits.vhd
--
-- Description:
--
-- VHDL-Standard: VHDL'93/02
-------------------------------------------------------------------------------
-- Structure:
-- gen_checkbits.vhd
--
-------------------------------------------------------------------------------
-- Author: goran
-- Revision: $Revision: 1.1.2.2 $
-- Date: $Date: 2010/09/06 09:01:24 $
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity checkbit_handler is
generic (
C_ENCODE : boolean := true;
C_USE_LUT6 : boolean := true);
port (
DataIn : in std_logic_vector(0 to 31);
CheckIn : in std_logic_vector(0 to 6);
CheckOut : out std_logic_vector(0 to 6);
Syndrome : out std_logic_vector(0 to 6);
Enable_ECC : in std_logic;
UE_Q : in std_logic;
CE_Q : in std_logic;
UE : out std_logic;
CE : out std_logic
);
end entity checkbit_handler;
library unisim;
use unisim.vcomponents.all;
library lmb_bram_if_cntlr_v4_0;
use lmb_bram_if_cntlr_v4_0.all;
architecture IMP of checkbit_handler is
component XOR18 is
generic (
C_USE_LUT6 : boolean);
port (
InA : in std_logic_vector(0 to 17);
res : out std_logic);
end component XOR18;
component Parity is
generic (
C_USE_LUT6 : boolean;
C_SIZE : integer);
port (
InA : in std_logic_vector(0 to C_SIZE - 1);
Res : out std_logic);
end component Parity;
component ParityEnable
generic (
C_USE_LUT6 : boolean;
C_SIZE : integer);
port (
InA : in std_logic_vector(0 to C_SIZE - 1);
Enable : in std_logic;
Res : out std_logic);
end component ParityEnable;
signal data_chk0 : std_logic_vector(0 to 17);
signal data_chk1 : std_logic_vector(0 to 17);
signal data_chk2 : std_logic_vector(0 to 17);
signal data_chk3 : std_logic_vector(0 to 14);
signal data_chk4 : std_logic_vector(0 to 14);
signal data_chk5 : std_logic_vector(0 to 5);
begin -- architecture IMP
data_chk0 <= DataIn(0) & DataIn(1) & DataIn(3) & DataIn(4) & DataIn(6) & DataIn(8) & DataIn(10) &
DataIn(11) & DataIn(13) & DataIn(15) & DataIn(17) & DataIn(19) & DataIn(21) &
DataIn(23) & DataIn(25) & DataIn(26) & DataIn(28) & DataIn(30);
data_chk1 <= DataIn(0) & DataIn(2) & DataIn(3) & DataIn(5) & DataIn(6) & DataIn(9) & DataIn(10) &
DataIn(12) & DataIn(13) & DataIn(16) & DataIn(17) & DataIn(20) & DataIn(21) &
DataIn(24) & DataIn(25) & DataIn(27) & DataIn(28) & DataIn(31);
data_chk2 <= DataIn(1) & DataIn(2) & DataIn(3) & DataIn(7) & DataIn(8) & DataIn(9) & DataIn(10) &
DataIn(14) & DataIn(15) & DataIn(16) & DataIn(17) & DataIn(22) & DataIn(23) & DataIn(24) &
DataIn(25) & DataIn(29) & DataIn(30) & DataIn(31);
data_chk3 <= DataIn(4) & DataIn(5) & DataIn(6) & DataIn(7) & DataIn(8) & DataIn(9) & DataIn(10) &
DataIn(18) & DataIn(19) & DataIn(20) & DataIn(21) & DataIn(22) & DataIn(23) & DataIn(24) &
DataIn(25);
data_chk4 <= DataIn(11) & DataIn(12) & DataIn(13) & DataIn(14) & DataIn(15) & DataIn(16) & DataIn(17) &
DataIn(18) & DataIn(19) & DataIn(20) & DataIn(21) & DataIn(22) & DataIn(23) & DataIn(24) &
DataIn(25);
data_chk5 <= DataIn(26) & DataIn(27) & DataIn(28) & DataIn(29) & DataIn(30) & DataIn(31);
-- Encode bits for writing data
Encode_Bits : if (C_ENCODE) generate
signal data_chk3_i : std_logic_vector(0 to 17);
signal data_chk4_i : std_logic_vector(0 to 17);
signal data_chk6 : std_logic_vector(0 to 17);
begin
------------------------------------------------------------------------------------------------
-- Checkbit 0 built up using XOR18
------------------------------------------------------------------------------------------------
XOR18_I0 : XOR18
generic map (
C_USE_LUT6 => C_USE_LUT6) -- [boolean]
port map (
InA => data_chk0, -- [in std_logic_vector(0 to 17)]
res => CheckOut(0)); -- [out std_logic]
------------------------------------------------------------------------------------------------
-- Checkbit 1 built up using XOR18
------------------------------------------------------------------------------------------------
XOR18_I1 : XOR18
generic map (
C_USE_LUT6 => C_USE_LUT6) -- [boolean]
port map (
InA => data_chk1, -- [in std_logic_vector(0 to 17)]
res => CheckOut(1)); -- [out std_logic]
------------------------------------------------------------------------------------------------
-- Checkbit 2 built up using XOR18
------------------------------------------------------------------------------------------------
XOR18_I2 : XOR18
generic map (
C_USE_LUT6 => C_USE_LUT6) -- [boolean]
port map (
InA => data_chk2, -- [in std_logic_vector(0 to 17)]
res => CheckOut(2)); -- [out std_logic]
------------------------------------------------------------------------------------------------
-- Checkbit 3 built up using XOR18
------------------------------------------------------------------------------------------------
data_chk3_i <= data_chk3 & "000";
XOR18_I3 : XOR18
generic map (
C_USE_LUT6 => C_USE_LUT6) -- [boolean]
port map (
InA => data_chk3_i, -- [in std_logic_vector(0 to 17)]
res => CheckOut(3)); -- [out std_logic]
------------------------------------------------------------------------------------------------
-- Checkbit 4 built up using XOR18
------------------------------------------------------------------------------------------------
data_chk4_i <= data_chk4 & "000";
XOR18_I4 : XOR18
generic map (
C_USE_LUT6 => C_USE_LUT6) -- [boolean]
port map (
InA => data_chk4_i, -- [in std_logic_vector(0 to 17)]
res => CheckOut(4)); -- [out std_logic]
------------------------------------------------------------------------------------------------
-- Checkbit 5 built up from 1 LUT6
------------------------------------------------------------------------------------------------
Parity_chk5_1 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => data_chk5, -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => CheckOut(5)); -- [out std_logic]
------------------------------------------------------------------------------------------------
-- Checkbit 6 built up from 3 LUT7 and 4 LUT6
------------------------------------------------------------------------------------------------
data_chk6 <= DataIn(0) & DataIn(1) & DataIn(2) & DataIn(4) & DataIn(5) & DataIn(7) & DataIn(10) &
DataIn(11) & DataIn(12) & DataIn(14) & DataIn(17) & DataIn(18) & DataIn(21) &
DataIn(23) & DataIn(24) & DataIn(26) & DataIn(27) & DataIn(29);
XOR18_I6 : XOR18
generic map (
C_USE_LUT6 => C_USE_LUT6) -- [boolean]
port map (
InA => data_chk6, -- [in std_logic_vector(0 to 17)]
res => CheckOut(6)); -- [out std_logic]
-- Unused
Syndrome <= (others => '0');
UE <= '0';
CE <= '0';
end generate Encode_Bits;
--------------------------------------------------------------------------------------------------
-- Decode bits to get syndrome and UE/CE signals
--------------------------------------------------------------------------------------------------
Decode_Bits : if (not C_ENCODE) generate
signal syndrome_i : std_logic_vector(0 to 6);
signal chk0_1 : std_logic_vector(0 to 3);
signal chk1_1 : std_logic_vector(0 to 3);
signal chk2_1 : std_logic_vector(0 to 3);
signal data_chk3_i : std_logic_vector(0 to 15);
signal chk3_1 : std_logic_vector(0 to 1);
signal data_chk4_i : std_logic_vector(0 to 15);
signal chk4_1 : std_logic_vector(0 to 1);
signal data_chk5_i : std_logic_vector(0 to 6);
signal data_chk6 : std_logic_vector(0 to 38);
signal chk6_1 : std_logic_vector(0 to 5);
signal syndrome_3_to_5 : std_logic_vector(3 to 5);
signal syndrome_3_to_5_multi : std_logic;
signal syndrome_3_to_5_zero : std_logic;
signal ue_i_0 : std_logic;
signal ue_i_1 : std_logic;
begin
------------------------------------------------------------------------------------------------
-- Syndrome bit 0 built up from 3 LUT6 and 1 LUT4
------------------------------------------------------------------------------------------------
chk0_1(3) <= CheckIn(0);
Parity_chk0_1 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => data_chk0(0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk0_1(0)); -- [out std_logic]
Parity_chk0_2 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => data_chk0(6 to 11), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk0_1(1)); -- [out std_logic]
Parity_chk0_3 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => data_chk0(12 to 17), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk0_1(2)); -- [out std_logic]
Parity_chk0_4 : ParityEnable
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 4)
port map (
InA => chk0_1, -- [in std_logic_vector(0 to C_SIZE - 1)]
Enable => Enable_ECC, -- [in std_logic]
Res => syndrome_i(0)); -- [out std_logic]
------------------------------------------------------------------------------------------------
-- Syndrome bit 1 built up from 3 LUT6 and 1 LUT4
------------------------------------------------------------------------------------------------
chk1_1(3) <= CheckIn(1);
Parity_chk1_1 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => data_chk1(0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk1_1(0)); -- [out std_logic]
Parity_chk1_2 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => data_chk1(6 to 11), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk1_1(1)); -- [out std_logic]
Parity_chk1_3 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => data_chk1(12 to 17), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk1_1(2)); -- [out std_logic]
Parity_chk1_4 : ParityEnable
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 4)
port map (
InA => chk1_1, -- [in std_logic_vector(0 to C_SIZE - 1)]
Enable => Enable_ECC, -- [in std_logic]
Res => syndrome_i(1)); -- [out std_logic]
------------------------------------------------------------------------------------------------
-- Syndrome bit 2 built up from 3 LUT6 and 1 LUT4
------------------------------------------------------------------------------------------------
chk2_1(3) <= CheckIn(2);
Parity_chk2_1 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => data_chk2(0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk2_1(0)); -- [out std_logic]
Parity_chk2_2 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => data_chk2(6 to 11), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk2_1(1)); -- [out std_logic]
Parity_chk2_3 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => data_chk2(12 to 17), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk2_1(2)); -- [out std_logic]
Parity_chk2_4 : ParityEnable
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 4)
port map (
InA => chk2_1, -- [in std_logic_vector(0 to C_SIZE - 1)]
Enable => Enable_ECC, -- [in std_logic]
Res => syndrome_i(2)); -- [out std_logic]
------------------------------------------------------------------------------------------------
-- Syndrome bit 3 built up from 2 LUT8 and 1 LUT2
------------------------------------------------------------------------------------------------
data_chk3_i <= data_chk3 & CheckIn(3);
Parity_chk3_1 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 8)
port map (
InA => data_chk3_i(0 to 7), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk3_1(0)); -- [out std_logic]
Parity_chk3_2 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 8)
port map (
InA => data_chk3_i(8 to 15), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk3_1(1)); -- [out std_logic]
Parity_chk3_3 : ParityEnable
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 2)
port map (
InA => chk3_1, -- [in std_logic_vector(0 to C_SIZE - 1)]
Enable => Enable_ECC, -- [in std_logic]
Res => syndrome_i(3)); -- [out std_logic]
------------------------------------------------------------------------------------------------
-- Syndrome bit 4 built up from 2 LUT8 and 1 LUT2
------------------------------------------------------------------------------------------------
data_chk4_i <= data_chk4 & CheckIn(4);
Parity_chk4_1 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 8)
port map (
InA => data_chk4_i(0 to 7), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk4_1(0)); -- [out std_logic]
Parity_chk4_2 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 8)
port map (
InA => data_chk4_i(8 to 15), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk4_1(1)); -- [out std_logic]
Parity_chk4_3 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 2)
port map (
InA => chk4_1, -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => syndrome_i(4)); -- [out std_logic]
------------------------------------------------------------------------------------------------
-- Syndrome bit 5 built up from 1 LUT7
------------------------------------------------------------------------------------------------
data_chk5_i <= data_chk5 & CheckIn(5);
Parity_chk5_1 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 7)
port map (
InA => data_chk5_i, -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => syndrome_i(5)); -- [out std_logic]
------------------------------------------------------------------------------------------------
-- Syndrome bit 6 built up from 3 LUT7 and 4 LUT6
------------------------------------------------------------------------------------------------
data_chk6 <= DataIn(0) & DataIn(1) & DataIn(2) & DataIn(3) & DataIn(4) & DataIn(5) & DataIn(6) & DataIn(7) &
DataIn(8) & DataIn(9) & DataIn(10) & DataIn(11) & DataIn(12) & DataIn(13) & DataIn(14) &
DataIn(15) & DataIn(16) & DataIn(17) & DataIn(18) & DataIn(19) & DataIn(20) & DataIn(21) &
DataIn(22) & DataIn(23) & DataIn(24) & DataIn(25) & DataIn(26) & DataIn(27) & DataIn(28) &
DataIn(29) & DataIn(30) & DataIn(31) & CheckIn(5) & CheckIn(4) & CheckIn(3) & CheckIn(2) &
CheckIn(1) & CheckIn(0) & CheckIn(6);
Parity_chk6_1 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => data_chk6(0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk6_1(0)); -- [out std_logic]
Parity_chk6_2 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => data_chk6(6 to 11), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk6_1(1)); -- [out std_logic]
Parity_chk6_3 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => data_chk6(12 to 17), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk6_1(2)); -- [out std_logic]
Parity_chk6_4 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 7)
port map (
InA => data_chk6(18 to 24), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk6_1(3)); -- [out std_logic]
Parity_chk6_5 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 7)
port map (
InA => data_chk6(25 to 31), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk6_1(4)); -- [out std_logic]
Parity_chk6_6 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 7)
port map (
InA => data_chk6(32 to 38), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk6_1(5)); -- [out std_logic]
Parity_chk6_7 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => chk6_1, -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => syndrome_i(6)); -- [out std_logic]
Syndrome <= syndrome_i;
syndrome_3_to_5 <= (chk3_1(0) xor chk3_1(1)) & (chk4_1(0) xor chk4_1(1)) & syndrome_i(5);
syndrome_3_to_5_zero <= '1' when syndrome_3_to_5 = "000" else '0';
syndrome_3_to_5_multi <= '1' when (syndrome_3_to_5 = "111" or
syndrome_3_to_5 = "011" or
syndrome_3_to_5 = "101") else
'0';
CE <= '0' when (Enable_ECC = '0') else
(syndrome_i(6) or CE_Q) when (syndrome_3_to_5_multi = '0') else
CE_Q;
ue_i_0 <= '0' when (Enable_ECC = '0') else
'1' when (syndrome_3_to_5_zero = '0') or (syndrome_i(0 to 2) /= "000") else
UE_Q;
ue_i_1 <= '0' when (Enable_ECC = '0') else
(syndrome_3_to_5_multi or UE_Q);
Use_LUT6: if (C_USE_LUT6) generate
UE_MUXF7 : MUXF7
port map (
I0 => ue_i_0,
I1 => ue_i_1,
S => syndrome_i(6),
O => UE);
end generate Use_LUT6;
Use_RTL: if (not C_USE_LUT6) generate
UE <= ue_i_1 when syndrome_i(6) = '1' else ue_i_0;
end generate Use_RTL;
-- Unused
CheckOut <= (others => '0');
end generate Decode_Bits;
end architecture IMP;
|
ARCHITECTURE behavior OF tb_ClkDiv IS
CONSTANT HalfClkPer : time := 62.5 ns; -- 62.5ns => 8 MHz
-- Component Declaration
COMPONENT ClkDiv IS
Generic (DividerWidth_g : integer range 4 to 32 := 16);
Port ( F100_400_n_i : in STD_LOGIC;
Divider800_i : in std_logic_vector(DividerWidth_g-1 downto 0);
Clk_i : in STD_LOGIC;
Reset_i : in STD_LOGIC;
Clk_o : out STD_LOGIC);
END COMPONENT;
-- Signal Declaration
-- General Signals
SIGNAL Reset_i : STD_LOGIC;
SIGNAL Clk_i : STD_LOGIC;
SIGNAL Clk_o : STD_LOGIC;
signal Divider800_i : std_logic_vector(15 downto 0);
SIGNAL F100_400_n_i : STD_LOGIC; -- Selects either 100 kHz or 400 kHz as
-- resulting SCL-I2C-Bus frequency.
-- (The resulting Clk_o frequency will
-- be 200 kHz or 800 kHz)
BEGIN
-- Component Instantiation
myClkDiv : ClkDiv
GENERIC MAP(DividerWidth_g => 16)
PORT MAP( Reset_i => Reset_i,
Clk_i => Clk_i,
Clk_o => Clk_o,
Divider800_i => Divider800_i,
F100_400_n_i => F100_400_n_i);
-- END OF COMPONENTS
-- PROCESS to generate 100-MHz Input-Clock-Signal
clock: PROCESS
BEGIN
Clk_i <= '0';
wait for HalfClkPer;
Clk_i <= '1';
wait for HalfClkPer;
END PROCESS clock;
-- Process to generate ControllCommands
CTRL : PROCESS
BEGIN
-- Reset
F100_400_n_i <= '0';
Divider800_i <= conv_std_logic_vector(8*1000*1000/(800*1000)-1,16);
Reset_i <= '1';
wait for HalfClkPer;
Reset_i <= '0';
wait for 52 us;
F100_400_n_i <= '1';
wait for 50 us;
F100_400_n_i <= '0';
wait for 50 us;
assert false report "Simulation finished" severity failure;
END PROCESS;
END;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
use ieee.math_real.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.Font.all;
entity top is
Port (
vgaRed : out std_logic_vector (3 downto 0);
vgaGreen : out std_logic_vector (3 downto 0);
vgaBlue : out std_logic_vector (3 downto 0);
Hsync : out std_logic;
Vsync : out std_logic;
led : out std_logic_vector (15 downto 0);
sw : in std_logic_vector (15 downto 0);
clk : in std_logic;
btnC : in std_logic;
btnU : in std_logic;
btnL : in std_logic;
btnR : in std_logic;
btnD : in std_logic;
PS2Clk : in std_logic;
PS2Data : in std_logic;
RsRx : inout std_logic;
RsTx : inout std_logic
);
end top;
architecture Behavioral of top is
-- CONSTANTS ----------------------------------------------------
constant COLS : integer := 160;
constant ROWS : integer := 64;
constant CHARS : integer := COLS * ROWS;
constant CPU_FREQ : integer := 15_000_000;
constant BLINKDATA : string := "Press any key to continue...";
constant TYPE_LRG_CNT : std_logic_vector := "00";
constant TYPE_SML_CNT : std_logic_vector := "01";
constant TYPE_VAR : std_logic_vector := "10";
constant TYPE_OMITTED : std_logic_vector := "11";
type alphabets_type is array (0 to 2, 6 to 31) of character;
constant alphabets: alphabets_type := (
('a', 'b', 'c', 'd', 'e', 'f', 'g', 'h', 'i', 'j', 'k', 'l', 'm', 'n', 'o', 'p', 'q', 'r', 's', 't', 'u', 'v', 'w', 'x', 'y', 'z'),
('A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', 'I', 'J', 'K', 'L', 'M', 'N', 'O', 'P', 'Q', 'R', 'S', 'T', 'U', 'V', 'W', 'X', 'Y', 'Z'),
(character'val(255), character'val(10), '0', '1', '2', '3', '4', '5', '6', '7', '8', '9', '.', ',', '!', '?', '_', '#', character'val(39), character'val(34), '/', '\', '-', ':', '(', ')')
);
-- CLOCK --------------------------------------------------------
component ClockDivider
port (
clkIn : in std_logic;
clk108M : out std_logic;
clk_cpu : out std_logic;
clk2cpu : out std_logic;
clk6cpu : out std_logic
);
end component;
signal clk_vga : std_logic := '0';
signal clk_cpu : std_logic := '0';
signal clk_2cpu : std_logic := '0';
signal clk_6cpu : std_logic := '0';
signal clk_10 : std_logic := '0';
signal clk_2 : std_logic := '0';
signal clk_1 : std_logic := '0';
signal clk_1k : std_logic := '0';
-- VGA controller -----------------------------------------------
component Vga
Port (
clk : in std_logic;
hSync : out std_logic;
vSync : out std_logic;
vgaRed : out std_logic_vector (3 downto 0);
vgaGreen : out std_logic_vector (3 downto 0);
vgaBlue : out std_logic_vector (3 downto 0);
fbOutAddr : out std_logic_vector(13 downto 0);
fbOutDat : in std_logic_vector(7 downto 0)
);
end component;
signal vga_addr : std_logic_vector(13 downto 0) := (others =>'0');
signal vga_dat : std_logic_vector(7 downto 0) := (others =>'0');
-- FRAMEBUFFER --------------------------------------------------
-- NEEDS to run at 2x CPU freq, for 1 CPU cycle mem access
component Framebuffer is
port (
clka : in std_logic;
ena : in std_logic;
wea : in std_logic_vector(0 downto 0);
addra : in std_logic_vector(13 downto 0);
dina : in std_logic_vector(7 downto 0);
douta : out std_logic_vector(7 downto 0);
clkb : in std_logic;
web : in std_logic_vector(0 downto 0);
addrb : in std_logic_vector(13 downto 0);
dinb : in std_logic_vector(7 downto 0);
doutb : out std_logic_vector(7 downto 0)
);
end component;
signal fb_a_we : std_logic_vector(0 downto 0) := (others =>'0');
signal fb_a_addr : std_logic_vector(13 downto 0) := (others =>'0');
signal fb_a_dat_in : std_logic_vector(7 downto 0) := (others =>'0');
signal fb_a_dat_out : std_logic_vector(7 downto 0) := (others =>'0');
signal fb_a_en : std_logic := '0';
-- RNG ----------------------------------------------------------
component Prng is
Generic
(
BITS : integer := 16
);
Port
(
seed : in std_logic_vector (16-1 downto 0);
seed_en : in std_logic;
clk : in std_logic;
rnd : out std_logic_vector (16-1 downto 0)
);
end component;
signal rng_seed : std_logic_vector(15 downto 0) := (others =>'0');
signal rng_seed_en : std_logic := '0';
signal rng_clk : std_logic := '0';
signal rng_out : std_logic_vector(15 downto 0) := (others =>'0');
-- KEYBOARD CONTROLLER ------------------------------------------
-- NEEDS to be at CPU freq
component ps2_keyboard_to_ascii is
Generic
(
CLK_FREQ : integer := CPU_FREQ
);
Port
(
clk : in std_logic; --system clock input
ps2_clk : in std_logic; --clock signal from ps2 keyboard
ps2_data : in std_logic; --data signal from ps2 keyboard
ascii_new : out std_logic; --output flag indicating new ascii value
ascii_code : out std_logic_vector(6 downto 0) --ascii value
);
end component;
signal kb_event : std_logic := '0';
signal kb_acsii : std_logic_vector(6 downto 0) := (others => '0');
-- RAM ----------------------------------------------------------
-- NEEDS to run at 6x CPU freq, for 1 CPU cycle mem access
component Ram is
Port
(
clk : in std_logic;
re : in std_logic_vector (1 downto 0);
we : in std_logic_vector (1 downto 0);
addr : in integer range 0 to 16#1FFFF#;
dat_r : out std_logic_vector (15 downto 0);
dat_w : in std_logic_vector (15 downto 0)
);
end component;
signal ram_re : std_logic_vector(1 downto 0) := (others => '0');
signal ram_we : std_logic_vector(1 downto 0) := (others => '0');
signal ram_addr : integer range 0 to 16#1FFFF# := 0;
signal ram_dat_r : std_logic_vector(15 downto 0) := (others => '0');
signal ram_dat_w : std_logic_vector(15 downto 0) := (others => '0');
-- STACK --------------------------------------------------------
component Stack is
port (
a : in std_logic_vector(9 downto 0);
d : in std_logic_vector(15 downto 0);
clk : in std_logic;
we : in std_logic;
spo : out std_logic_vector(15 downto 0)
);
end component;
signal stack_addr : std_logic_vector(9 downto 0) := (others => '0');
signal stack_dat_w : std_logic_vector(15 downto 0) := (others => '0');
signal stack_we : std_logic := '0';
signal stack_dat_r : std_logic_vector(15 downto 0) := (others => '0');
-- MISC ---------------------------------------------------------
-- runtime in ms
signal runtime : unsigned(32 downto 0) := (others => '0');
-- FUNCTIONS ----------------------------------------------------
function cursor_delta(current : integer range 0 to CHARS; delta : integer range -CHARS to CHARS := 1; modulo : integer range 0 to CHARS := CHARS) return integer is
begin
return (current + delta) mod modulo;
end cursor_delta;
function pad_string(input : string; size : positive; hex : std_logic_vector := "") return string is
variable tmp: string(1 to size) := (others => NUL);
begin
if hex'length = 0 then
if input'length >= size then
tmp := input(1 to size);
else
tmp(1 to input'length) := input;
tmp(input'length + 1 to size) := (others => ' ');
end if;
else
if input'length >= (size - (hex'length / 4) - 1) then
tmp(1 to (size - (hex'length / 4)) - 1) := input(1 to (size - (hex'length / 4)) - 1); -- copy over as much as will fit
tmp(size - (hex'length / 4)) := ' '; -- add space
for i in 0 to (hex'length / 4) - 1 loop -- per 4 bits
case to_integer(unsigned(hex(hex'length - (4 * i) to hex'length - (4 * i) - 4))) is
when 0 => tmp(size - (hex'length / 4) + i) := '0';
when 1 => tmp(size - (hex'length / 4) + i) := '1';
when 2 => tmp(size - (hex'length / 4) + i) := '2';
when 3 => tmp(size - (hex'length / 4) + i) := '3';
when 4 => tmp(size - (hex'length / 4) + i) := '4';
when 5 => tmp(size - (hex'length / 4) + i) := '5';
when 6 => tmp(size - (hex'length / 4) + i) := '6';
when 7 => tmp(size - (hex'length / 4) + i) := '7';
when 8 => tmp(size - (hex'length / 4) + i) := '8';
when 9 => tmp(size - (hex'length / 4) + i) := '9';
when 10 => tmp(size - (hex'length / 4) + i) := 'A';
when 11 => tmp(size - (hex'length / 4) + i) := 'B';
when 12 => tmp(size - (hex'length / 4) + i) := 'D';
when 13 => tmp(size - (hex'length / 4) + i) := 'D';
when 14 => tmp(size - (hex'length / 4) + i) := 'E';
when 15 => tmp(size - (hex'length / 4) + i) := 'F';
when others => tmp(size - (hex'length / 4) + i) := '?';
end case;
end loop;
else
tmp(1 to input'length) := input;
tmp(input'length + 1 to size) := (others => ' ');
end if;
end if;
return tmp;
end pad_string;
function ascii_c(char : character; inverted : boolean := false) return std_logic_vector(7 downto 0) is
variable tmp : std_logic_vector(7 downto 0) := (others => '0');
begin
if inverted then
tmp(7) := '1';
end if;
tmp(6 downto 0) := std_logic_vector(to_unsigned(character'pos(char), 7));
return tmp;
end ascii_c;
function ascii_b(b : std_logic; inverted : boolean := false) return std_logic_vector(7 downto 0) is
variable tmp : std_logic_vector(7 downto 0) := '0' & std_logic_vector(to_unsigned(character'pos('0'), 7));
begin
if inverted then
tmp(7) := '1';
end if;
tmp(0) := b;
return tmp;
end ascii_b;
function ascii_i(i : integer range -999_999 to 999_999; didget : integer range 0 to 10 := 0; inverted : boolean := false; sign : boolean := false) return std_logic_vector(7 downto 0) is
variable tmp : std_logic_vector(7 downto 0) := (others => '0');
begin
if inverted then
tmp(7) := '1';
end if;
if sign then
if i > 0 then
tmp(6 downto 0) := std_logic_vector(to_unsigned(character'pos('+'), 7));
else
tmp(6 downto 0) := std_logic_vector(to_unsigned(character'pos('-'), 7));
end if;
else
tmp(6 downto 0) := std_logic_vector(to_unsigned(character'pos('0') + ((i mod (10 ** (didget + 1))) / (10 ** didget)), 7));
end if;
return tmp;
end ascii_i;
function ascii_x(i : integer range 0 to 16#FF_FFFF#; didget : integer range 0 to 10 := 0; inverted : boolean := false) return std_logic_vector(7 downto 0) is
variable tmp : std_logic_vector(7 downto 0) := (others => '0');
begin
if inverted then
tmp(7) := '1';
end if;
case to_integer(shift_right(to_unsigned(i, 6 * 4), 4 * didget) and "000000000000000000001111") is
when 0 => tmp(6 downto 0) := std_logic_vector(to_unsigned(character'pos('0'), 7));
when 1 => tmp(6 downto 0) := std_logic_vector(to_unsigned(character'pos('1'), 7));
when 2 => tmp(6 downto 0) := std_logic_vector(to_unsigned(character'pos('2'), 7));
when 3 => tmp(6 downto 0) := std_logic_vector(to_unsigned(character'pos('3'), 7));
when 4 => tmp(6 downto 0) := std_logic_vector(to_unsigned(character'pos('4'), 7));
when 5 => tmp(6 downto 0) := std_logic_vector(to_unsigned(character'pos('5'), 7));
when 6 => tmp(6 downto 0) := std_logic_vector(to_unsigned(character'pos('6'), 7));
when 7 => tmp(6 downto 0) := std_logic_vector(to_unsigned(character'pos('7'), 7));
when 8 => tmp(6 downto 0) := std_logic_vector(to_unsigned(character'pos('8'), 7));
when 9 => tmp(6 downto 0) := std_logic_vector(to_unsigned(character'pos('9'), 7));
when 10 => tmp(6 downto 0) := std_logic_vector(to_unsigned(character'pos('A'), 7));
when 11 => tmp(6 downto 0) := std_logic_vector(to_unsigned(character'pos('B'), 7));
when 12 => tmp(6 downto 0) := std_logic_vector(to_unsigned(character'pos('C'), 7));
when 13 => tmp(6 downto 0) := std_logic_vector(to_unsigned(character'pos('D'), 7));
when 14 => tmp(6 downto 0) := std_logic_vector(to_unsigned(character'pos('E'), 7));
when 15 => tmp(6 downto 0) := std_logic_vector(to_unsigned(character'pos('F'), 7));
when others => tmp(6 downto 0) := std_logic_vector(to_unsigned(character'pos('?'), 7));
end case;
return tmp;
end ascii_x;
--------------------------------------------------------
begin -- BEGIN
--------------------------------------------------------
-- CLOCK --------------------------------------------------------
clock0: ClockDivider
port map (
clkIn => clk,
clk108M => clk_vga,
clk_cpu => clk_cpu,
clk2cpu => clk_2cpu,
clk6cpu => clk_6cpu
);
-- Slow clock devider
process (clk_cpu)
constant MAX : integer := CPU_FREQ/2;
variable i : integer range 0 to MAX := 0;
begin
if rising_edge(clk_cpu) then
if i < MAX then
i := i + 1;
else
i := 0;
end if;
if i = 0 then
clk_1 <= not(clk_1);
end if;
if i mod (MAX / 2) = 0 then
clk_2 <= not(clk_2);
end if;
if i mod (MAX / 1000) = 0 then
clk_1k <= not(clk_1k);
end if;
if i mod (MAX / 10) = 0 then
clk_10 <= not(clk_10);
end if;
end if;
end process;
-- VGA controller -----------------------------------------------
vga0: Vga
port map (
clk => clk_vga,
hSync => Hsync,
vSync => Vsync,
vgaRed => vgaRed,
vgaGreen => vgaGreen,
vgaBlue => vgaBlue,
fbOutAddr => vga_addr,
fbOutDat => vga_dat
);
-- FRAMEBUFFER --------------------------------------------------
frameBuffer0: Framebuffer
port map (
clka => clk_2cpu,
ena => fb_a_en,
wea => fb_a_we,
addra => fb_a_addr,
dina => fb_a_dat_in,
douta => fb_a_dat_out,
clkb => clk_vga,
web => "0",
addrb => vga_addr,
dinb => x"00",
doutb => vga_dat
);
-- RNG ----------------------------------------------------------
prng0: Prng
port map (
seed => rng_seed,
seed_en => rng_seed_en,
clk => rng_clk,
rnd => rng_out
);
-- KEYBOARD CONTROLLER ------------------------------------------
keyboard0: ps2_keyboard_to_ascii
port map (
clk => clk_cpu,
ps2_clk => PS2Clk,
ps2_data => PS2Data,
ascii_new => kb_event,
ascii_code => kb_acsii
);
-- RAM ----------------------------------------------------------
ram0: Ram
port map (
clk => clk_6cpu,
re => ram_re,
we => ram_we,
addr => ram_addr,
dat_r => ram_dat_r,
dat_w => ram_dat_w
);
-- STACK --------------------------------------------------------
stack0: Stack
port map (
a => stack_addr,
d => stack_dat_w,
clk => clk_cpu,
we => stack_we,
spo => stack_dat_r
);
-- MISC ---------------------------------------------------------
-- runtime cursor
process (clk_1k)
begin
if rising_edge(clk_1k) then
runtime <= runtime + 1;
end if;
end process;
---- PRNG test
--rng_seed <= sw;
--led <= rng_out;
--process (clk_10)
--begin
-- if rising_edge(clk_10) then
-- if btnL = '1' then
-- rng_seed_en <= '1';
-- rng_clk <= not(rng_clk);
-- else
-- rng_seed_en <= '0';
-- end if;
-- if btnR = '1' then
-- rng_clk <= not(rng_clk);
-- end if;
-- end if;
--end process;
---- debug info
-- led <= (clk_1, clk_2, runtime(13 downto 0));
-- led <= clk_1 & clk_2 & std_logic_vector(runtime(17 downto 4));
-- MAIN ---------------------------------------------------------
-- CPU control state machine, not a proper FSM!
process (clk_cpu)
type state_type is
(
RESET, BLANK, SCROLL, SCROLL_W, LOAD, LOAD_ABBR, DEBUG, DEBUG_KB, ERROR, -- Background states, used for 'interpreter' stuff
FETCH, FETCH_OP, DECODE, EXEC -- Z machine states
);
variable state : state_type := RESET;-- LOAD;-- The current/next state
variable next_state : state_type := RESET; -- The state to go to, after finishing the current one.
type instuction_type is
(
OP_NOP, OP_PRINT, OP_POP, OP_PRINT_NL, OP_STATUS, OP_VERIFY, OP_COMP_ZERO, OP_GET_SIBLING, OP_GET_CHILD, OP_GET_PARENT, OP_GET_PROP_LEN,
OP_INC, OP_DEC, OP_PRINT_ADDR, OP_REMOVE_OBJ, OP_PRINT_OBJ, OP_JUMP, OP_PRINT_PADDR, OP_LOAD, OP_NOT_BW, OP_COMP_EQ, OP_COMP_LT,
OP_COMP_GT, OP_DEC_CHK, OP_INC_CHK, OP_JIN, OP_TEST, OP_OR_BW, OP_AND_BW, OP_TEST_ATTR, OP_SET_ATTR, OP_CLEAR_ATTR, OP_STORE,
OP_INSERT_OBJ, OP_LOADW, OP_LOADB, OP_GET_PROP, OP_GET_PROP_ADDR, OP_GET_NEXT_PROP, OP_ADD, OP_SUB, OP_MUL, OP_DIV, OP_MOD, OP_CALL,
OP_STOREW, OP_STOREB, OP_PUT_PROP, OP_SREAD, OP_PRINT_CHAR, OP_PRINT_NUM, OP_RND, OP_PUSH, OP_PULL, OP_SPLIT_WINDOW, OP_SET_WINDOW
);
variable instruction : instuction_type := OP_NOP;
variable instruction_raw : std_logic_vector(7 downto 0) := (others => '0');
variable ret : boolean := false;
variable string_fetch : boolean := false;
variable string_buffer : string(1 to COLS);
variable string_pointer : integer range 0 to COLS := 0;
variable string_back : integer range 0 to 16#1FFFF# := 0;
variable string_back_inner : integer range 0 to 2 := 0;
variable string_in_abbr : boolean := false;
variable string_alphabet : integer range 0 to 2 := 0;
variable string_current_z : integer range 0 to 31 := 0;
variable string_abbreviation : integer range 0 to 3 := 0; -- if not 0, do an abbreviation next
variable string_zscii : integer range 0 to 2 := 0; -- if not 0, do a zscii character of 2x 5 bits. 2 = upper bits, 1 = lower bits
variable branch : boolean := false;
variable branch_on_true : boolean := false;
variable branch_fetch : boolean := false;
variable branch_offset : integer range -8192 to 8191;
variable store : boolean := false;
variable store_fetch : boolean := false;
variable store_var : std_logic_vector(7 downto 0) := (others => '0');
variable op0_fetch : boolean := false;
variable op0_type : std_logic_vector(1 downto 0) := "00";
variable op0 : std_logic_vector(15 downto 0) := (others => '0');
variable op1_fetch : boolean := false;
variable op1_type : std_logic_vector(1 downto 0) := "00";
variable op1 : std_logic_vector(15 downto 0) := (others => '0');
variable op2_fetch : boolean := false;
variable op2_type : std_logic_vector(1 downto 0) := "00";
variable op2 : std_logic_vector(15 downto 0) := (others => '0');
variable op3_fetch : boolean := false;
variable op3_type : std_logic_vector(1 downto 0) := "00";
variable op3 : std_logic_vector(15 downto 0) := (others => '0');
variable delay : boolean := false;-- Delay 1 clock tick
variable cursor : integer range 0 to CHARS := 0;
variable message : string(1 to COLS);
variable flags1 : std_logic_vector(15 downto 0) := (others => '0');
variable flags2 : std_logic_vector(15 downto 0) := (others => '0');
variable high : integer range 0 to 16#FFFF# := 0;
variable pc : integer range 0 to 16#1FFFF# := 0;
variable dict : integer range 0 to 16#FFFF# := 0;
variable objtab : integer range 0 to 16#FFFF# := 0;
variable globals : integer range 0 to 16#FFFF# := 0;
variable static : integer range 0 to 16#FFFF# := 0;
variable abbreviations_start : integer range 0 to 16#FFFF# := 0;
variable length : integer range 0 to 16#FF_FFFF# := 0;
variable checksum : integer range 0 to 16#FFFF# := 0;
-- Table of abbreviation addresses, for reduced access time.
-- It could be left in ram and accessed when required, but that would require more stare registers and clock cycles.
type abbreviations_type is array(95 downto 0) of integer range 0 to 16#1FFFF#;
variable abbreviations : abbreviations_type;
begin
if rising_edge(clk_cpu) then
fb_a_en <= '0';
fb_a_we <= "0";
ram_re <= "00";
ram_we <= "00";
if delay then
delay := false;
elsif kb_event = '1' and kb_acsii = "0011011" then
cursor := 0;
state := BLANK;
next_state := LOAD;
else
case state is
---------------------------------------------
-- Z STATES
---------------------------------------------------------------------------------------------------------------------------------------
when EXEC =>
state := ERROR;
message := pad_string("Debug", message'LENGTH, ram_dat_r);
ret := false;
string_buffer := pad_string("-", string_buffer'LENGTH);
string_pointer := 0;
string_back := 0;
string_back_inner := 0;
string_in_abbr := false;
string_alphabet := 0;
string_current_z := 0;
string_abbreviation := 0;
string_zscii := 0;
branch := false;
branch_on_true := false;
branch_offset := 0;
store := false;
store_var := (others => '0');
op0_type := "11";
op0 := "0000000000000000";
op1_type := "11";
op1 := "0000000000000000";
op2_type := "11";
op2 := "0000000000000000";
op3_type := "11";
op3 := "0000000000000000";
-- state := FETCH;
when FETCH_OP =>
pc := pc + 1;
if op0_fetch then
op0_fetch := false;
case op0_type is
when TYPE_LRG_CNT =>
op0 := ram_dat_r;
pc := pc + 1;
when TYPE_SML_CNT | TYPE_VAR =>
op0 := "00000000" & ram_dat_r(15 downto 8);
when TYPE_OMITTED =>
op0 := (others => '0');
end case;
elsif op1_fetch then
op1_fetch := false;
case op1_type is
when TYPE_LRG_CNT =>
op1 := ram_dat_r;
pc := pc + 1;
when TYPE_SML_CNT | TYPE_VAR =>
op1 := "00000000" & ram_dat_r(15 downto 8);
when TYPE_OMITTED =>
op1 := (others => '0');
end case;
elsif op2_fetch then
op2_fetch := false;
case op2_type is
when TYPE_LRG_CNT =>
op2 := ram_dat_r;
pc := pc + 1;
when TYPE_SML_CNT | TYPE_VAR =>
op2 := "00000000" & ram_dat_r(15 downto 8);
when TYPE_OMITTED =>
op2 := (others => '0');
end case;
elsif op3_fetch then
op3_fetch := false;
case op3_type is
when TYPE_LRG_CNT =>
op3 := ram_dat_r;
pc := pc + 1;
when TYPE_SML_CNT | TYPE_VAR =>
op3 := "00000000" & ram_dat_r(15 downto 8);
when TYPE_OMITTED =>
op3 := (others => '0');
end case;
elsif store_fetch then
store_fetch := false;
store_var := ram_dat_r(15 downto 8);
elsif branch_fetch then
branch_fetch := false;
if ram_dat_r(15) = '1' then -- true or false?
branch_on_true := true;
else
branch_on_true := false;
end if;
if ram_dat_r(14) = '1' then -- short format, 0 to 63)
branch_offset := to_integer(unsigned(ram_dat_r(13 downto 8)));
else -- long format, !!signed!! -8192 to 8191
branch_offset := to_integer(signed(ram_dat_r(13 downto 0)));
pc := pc + 1;
end if;
elsif string_fetch then
pc := pc + 2; -- string is always word alligned
-- bit 15 only set when last 3 characters.
if ram_dat_r(15) = '1' then
if string_in_abbr then -- go back to main string
string_in_abbr := false;
pc := string_back;
else -- string is done
string_fetch := false;
end if;
end if;
------------------------
-- -- z char 1 (bits 14 to 10)
-- string_current_z := to_integer(unsigned(ram_dat_r(14 downto 10)));
-- if string_abbreviation /= 0 then -- prev char was abbreviation char
-- string_back := pc;
-- string_in_abbr := true;
-- pc := abbreviations(32 * (string_abbreviation - 1) + string_current_z); -- address of the "32(z-1)+n"th abbreviation
-- string_abbreviation := 0;
-- elsif string_zscii = 2 then -- part 1 of zscii
-- -- string_buffer(string_pointer)(8 downto 6) := std_logic_vector(to_unsigned(string_current_z, 3));
-- string_zscii := 1;
-- elsif string_zscii = 1 then -- part 2 of zscii
-- -- string_buffer(string_pointer)(5 downto 0) := std_logic_vector(to_unsigned(string_current_z, 5));
-- string_buffer(string_pointer) := character'val(254); -- todo
-- string_zscii := 0;
-- string_pointer := string_pointer + 1;
-- else -- not escaped
-- case string_current_z is
-- when 0 => -- space
-- string_buffer(string_pointer) := ' ';
-- string_pointer := string_pointer + 1;
-- when 1 to 3 => -- abbreviation character
-- if string_in_abbr then
-- state := ERROR;
-- message := pad_string("Abbreviation inside abbreviation.", message'LENGTH);
-- end if;
-- string_abbreviation := string_current_z;
-- when 4 => -- alphabet shift to 1
-- string_alphabet := 1;
-- when 5 => -- alphabet shift to 2
-- string_alphabet := 2;
-- when 6 to 31 =>
-- if string_alphabet = 2 and string_current_z = 6 then -- zscii escape char
-- string_zscii := 2;
-- else -- regular character
-- string_buffer(string_pointer) := alphabets(string_alphabet, string_current_z);
-- string_pointer := string_pointer + 1;
-- end if;
-- end case;
-- end if;
------------------------
-- -- z char 2 (bits 9 to 5)
-- string_current_z := to_integer(unsigned(ram_dat_r(9 downto 5)));
-- if string_abbreviation /= 0 then -- prev char was abbreviation char
-- string_back := pc;
-- string_in_abbr := true;
-- pc := abbreviations(32 * (string_abbreviation - 1) + string_current_z); -- address of the "32(z-1)+n"th abbreviation
-- string_abbreviation := 0;
-- else
-- case string_current_z is
-- when 0 => -- space
-- string_buffer(string_pointer) = ' '
-- string_pointer := string_pointer + 1;
-- when 1 to 3 => -- abbreviation character
-- if string_in_abbr then
-- state := ERROR;
-- message := pad_string("Abbreviation inside abbreviation.", message'LENGTH);
-- end if;
-- string_abbreviation := string_current_z;
-- when 4 => -- alphabet shift to 1
-- string_alphabet := 1;
-- when 5 => -- alphabet shift to 2
-- string_alphabet := 2;
-- when 6 to 31 => -- regular character
-- if string_alphabet = 2 and z = 6 then
-- string_zscii = 2;
-- end if;
-- string_buffer(string_pointer) = alphabets(string_alphabet, string_current_z);
-- string_pointer := string_pointer + 1;
-- end case;
-- end if;
-- ---------------------------------------------------------------------------------------------------------
-- z := to_integer(unsigned(ram_dat_r(14 downto 10)))
-- z := to_integer(unsigned(ram_dat_r(9 downto 5)))
-- z := to_integer(unsigned(ram_dat_r(4 downto 0)))
-- if string_abbreviation /= 0 then -- prev char was abbreviation char
-- string_back := pc;
-- string_back_inner := 1;
-- string_in_abbr := true;
-- pc := abbreviations(32 * (string_abbreviation - 1) + z); -- set pc to the address of the "32(z-1)+n"th abbreviation
-- string_abbreviation := 0;
-- else -- previous char was normal
-- case z is
-- when 0 => -- space
-- string_buffer(string_pointer) = ' '
-- string_pointer := string_pointer + 1;
-- when 1 to 3 => -- abbreviation character
-- if string_in_abbr then
-- state := ERROR;
-- message := pad_string("Abbreviation inside abbreviation.", message'LENGTH);
-- end if;
-- string_abbreviation := z;
-- when 4 => -- alphabet shift to 1
-- string_alphabet := 1;
-- when 5 => -- alphabet shift to 2
-- string_alphabet := 2;
-- when 6 to 31 => -- regular character
-- if string_alphabet = 2 and z = 6 then
-- string_zscii = 2;
-- end if;
-- string_buffer(string_pointer) = alphabets(string_alphabet, z);
-- string_pointer := string_pointer + 1;
-- end case;
-- end if;
-- if z > 6 then
-- string_buffer(string_pointer) = alphabets(string_alphabet, z);
-- string_pointer := string_pointer + 1;
-- else if z == 1 then
-- end if;
-- string_alphabet := 0;
-- ram_dat_r(14 downto 10) -- z char 1
end if;
ram_re <= "11";
ram_addr <= pc;
-- if no more fetch steps will follow, go to the next stage, don't need to check op0
if not (op1_fetch or op2_fetch or op3_fetch or store_fetch or branch_fetch or string_fetch) then
state := EXEC;
end if;
---------------------------------------------
when FETCH =>
ram_re <= "11";
ram_addr <= pc;
state := DECODE;
if pc > length then
cursor := 0;
state := ERROR;
message := pad_string("PC > length?", message'LENGTH);
end if;
---------------------------------------------
when DECODE =>
state := FETCH_OP;
pc := pc + 1;
ram_re <= "11";
ram_addr <= pc;
instruction_raw := ram_dat_r(15 downto 8);
-- Short form ------------------------
if ram_dat_r(15 downto 14) = "10" then
-- 0OP ------------------------------
if ram_dat_r(13 downto 12) = "11" then
case to_integer(unsigned(ram_dat_r(11 downto 9))) is
when 0 => -- rtrue
instruction := OP_NOP;
ret := true;
op0 := "0000000000000001";
op0_type := TYPE_SML_CNT;
when 1 => -- rfalse
instruction := OP_NOP;
ret := true;
op0 := "0000000000000000";
op0_type := TYPE_SML_CNT;
when 2 => -- print (literal-string)
instruction := OP_PRINT;
string_fetch := true;
when 3 => -- print_ret (literal-string)
instruction := OP_PRINT;
string_fetch := true;
ret := true;
op0 := "0000000000000001";
op0_type := TYPE_SML_CNT;
when 4 => -- nop
instruction := OP_NOP;
when 5 => -- save ?(label) -- TODO
instruction := OP_NOP;
branch := true;
branch_fetch := true;
-- branch_on_true := ram_dat_r(7) = '1';
-- branch_fetch := ram_dat_r(6) = '0';
-- branch_offset := "0000000000" & ram_dat_r(5 downto 0);
when 6 => -- save ?(label) -- TODO
instruction := OP_NOP;
branch := true;
branch_fetch := true;
-- branch_on_true := ram_dat_r(7) = '1';
-- branch_fetch := ram_dat_r(6) = '0';
-- branch_offset := "0000000000" & ram_dat_r(5 downto 0);
when 7 => -- restart -- TODO
instruction := OP_NOP;
state := ERROR;
message := pad_string("Power cycling is the restart in this universe!", message'LENGTH, ram_dat_r);
when 8 => -- ret_popped
instruction := OP_POP;
ret := true;
when 9 => -- pop
instruction := OP_POP;
when 10 =>
instruction := OP_NOP;
state := ERROR;
message := pad_string("It is now safe to power off your computer.", message'LENGTH, ram_dat_r);
when 11 =>
instruction := OP_PRINT_NL;
when 12 =>
instruction := OP_STATUS;
when 13 =>
instruction := OP_VERIFY;
when others =>
cursor := 0;
state := ERROR;
message := pad_string("Instruction undecodable. Short, 0OP", message'LENGTH, ram_dat_r);
end case;
-- 1OP ------------------------------
else
op0_type := ram_dat_r(11 downto 10);
if op0_type /= TYPE_LRG_CNT then -- NOT Lage constant that will require later fetching, BUT Variable or small constant
op0 := "00000000" & ram_dat_r(7 downto 0);
pc := pc + 1; -- Increment PC again, since the 2nd byte of the word we got is (part of) the operand
else
op0_fetch := true;
end if;
ram_re <= "11";
ram_addr <= pc;
case to_integer(unsigned(ram_dat_r(9 downto 8))) is
when 0 =>
instruction := OP_COMP_ZERO;
branch := true;
when 1 =>
instruction := OP_GET_SIBLING;
store := true;
store_fetch := true;
branch := true;
branch_fetch := true;
when 2 =>
instruction := OP_GET_CHILD;
store := true;
store_fetch := true;
branch := true;
branch_fetch := true;
when 3 =>
instruction := OP_GET_PARENT;
store := true;
store_fetch := true;
when 4 =>
instruction := OP_GET_PROP_LEN;
store := true;
store_fetch := true;
when 5 =>
instruction := OP_INC;
when 6 =>
instruction := OP_DEC;
when 7 =>
instruction := OP_PRINT_ADDR;
when 9 =>
instruction := OP_REMOVE_OBJ;
when 10 =>
instruction := OP_PRINT_OBJ;
when 11 =>
instruction := OP_NOP;
ret := true;
when 12 =>
instruction := OP_JUMP;
when 13 =>
instruction := OP_PRINT_PADDR;
when 14 =>
instruction := OP_LOAD;
store := true;
store_fetch := true;
when 15 =>
instruction := OP_NOT_BW;
store := true;
store_fetch := true;
when others =>
cursor := 0;
state := ERROR;
message := pad_string("Instruction undecodable. Short, 1OP", message'LENGTH, ram_dat_r);
end case;
end if;
-- Variable form ---------------------
elsif ram_dat_r(15 downto 14) = "11" then
pc := pc + 1; -- second byte was type info, inc again
ram_re <= "11";
ram_addr <= pc;
op0_type := ram_dat_r(7 downto 6);
op1_type := ram_dat_r(5 downto 4);
op2_type := ram_dat_r(3 downto 2);
op3_type := ram_dat_r(1 downto 0);
if op0_type /= TYPE_OMITTED then
op0_fetch := true;
end if;
if op1_type /= TYPE_OMITTED then
op1_fetch := true;
end if;
if op2_type /= TYPE_OMITTED then
op2_fetch := true;
end if;
if op3_type /= TYPE_OMITTED then
op3_fetch := true;
end if;
-- VAR ------------------------------
if ram_dat_r(13) = '1' then
case to_integer(unsigned(ram_dat_r(12 downto 8))) is
when 0 => -- call routine ...0 to 3 args... -> (result)
instruction := OP_CALL;
store := true;
store_fetch := true;
when 1 => -- storew array word-index value
instruction := OP_STOREW;
when 2 => -- storeb array byte-index value
instruction := OP_STOREB;
when 3 => -- put_prop object property value
instruction := OP_PUT_PROP;
when 4 => -- sread text parse
instruction := OP_SREAD;
when 5 => -- print_char output-character-code
instruction := OP_PRINT_CHAR;
when 6 => -- print_num value
instruction := OP_PRINT_NUM;
when 7 => -- random range -> (result)
instruction := OP_RND;
store := true;
store_fetch := true;
when 8 => -- push value
instruction := OP_PUSH;
when 9 => -- pull (variable)
instruction := OP_PULL;
when 10 => -- split_window lines
instruction := OP_SPLIT_WINDOW;
when 11 => -- set_window window
instruction := OP_SET_WINDOW;
when others =>
cursor := 0;
state := ERROR;
message := pad_string("Instruction undecodable. Variable, VAR", message'LENGTH, ram_dat_r);
end case;
-- 2OP ------------------------------
else
-- TODO ??? Is this correct ??
case to_integer(unsigned(ram_dat_r(12 downto 8))) is
when 0 =>
instruction := OP_COMP_ZERO;
branch := true;
when 1 =>
instruction := OP_GET_SIBLING;
store := true;
store_fetch := true;
branch := true;
branch_fetch := true;
when 2 =>
instruction := OP_GET_CHILD;
store := true;
store_fetch := true;
branch := true;
branch_fetch := true;
when 3 =>
instruction := OP_GET_PARENT;
store := true;
store_fetch := true;
when 4 =>
instruction := OP_GET_PROP_LEN;
store := true;
store_fetch := true;
when 5 =>
instruction := OP_INC;
when 6 =>
instruction := OP_DEC;
when 7 =>
instruction := OP_PRINT_ADDR;
when 9 =>
instruction := OP_REMOVE_OBJ;
when 10 =>
instruction := OP_PRINT_OBJ;
when 11 =>
instruction := OP_NOP;
ret := true;
when 12 =>
instruction := OP_JUMP;
when 13 =>
instruction := OP_PRINT_PADDR;
when 14 =>
instruction := OP_LOAD;
store := true;
store_fetch := true;
when 15 =>
instruction := OP_NOT_BW;
store := true;
store_fetch := true;
when others =>
cursor := 0;
state := ERROR;
message := pad_string("Instruction undecodable. Variable, 2OP", message'LENGTH, ram_dat_r);
end case;
end if;
-- Long form -------------------------
else -- Always 2OP
op0_fetch := true;
op1_fetch := true;
-- Type OP 1
if ram_dat_r(14) = '0' then
op0_type := "01";
else
op0_type := "10";
end if;
-- Type OP 2
if ram_dat_r(13) = '0' then
op1_type := "01";
else
op1_type := "10";
end if;
case to_integer(unsigned(ram_dat_r(12 downto 8))) is
when 1 => -- je a b ?(label)
instruction := OP_COMP_EQ;
branch := true;
branch_fetch := true;
when 2 => -- jl a b ?(label)
instruction := OP_COMP_LT;
branch := true;
branch_fetch := true;
when 3 => -- jg a b ?(label)
instruction := OP_COMP_GT;
branch := true;
branch_fetch := true;
when 4 => -- dec_chk (variable) value ?(label)
instruction := OP_DEC_CHK;
branch := true;
branch_fetch := true;
when 5 => -- inc_chk (variable) value ?(label)
instruction := OP_INC_CHK;
branch := true;
branch_fetch := true;
when 6 => -- jin obj1 obj2 ?(label)
instruction := OP_JIN;
branch := true;
branch_fetch := true;
when 7 => -- test bitmap flags ?(label)
instruction := OP_TEST;
branch := true;
branch_fetch := true;
when 8 => -- or a b -> (result)
instruction := OP_OR_BW;
store := true;
store_fetch := true;
when 9 => -- and a b -> (result)
instruction := OP_AND_BW;
store := true;
store_fetch := true;
when 10 => -- test_attr object attribute ?(label)
instruction := OP_TEST_ATTR;
branch := true;
branch_fetch := true;
when 11 => -- set_attr object attribute
instruction := OP_SET_ATTR;
when 12 => -- set_attr object attribute
instruction := OP_CLEAR_ATTR;
when 13 => -- set_attr object attribute
instruction := OP_STORE;
when 14 => -- insert_obj object destination
instruction := OP_INSERT_OBJ;
when 15 => -- loadw array word-index -> (result)
instruction := OP_LOADW;
store := true;
store_fetch := true;
when 16 => -- loadb array byte-index -> (result)
instruction := OP_LOADB;
store := true;
store_fetch := true;
when 17 => -- get_prop object property -> (result)
instruction := OP_GET_PROP;
store := true;
store_fetch := true;
when 18 => -- get_prop_addr object property -> (result)
instruction := OP_GET_PROP_ADDR;
store := true;
store_fetch := true;
when 19 => -- get_next_prop object property -> (result)
instruction := OP_GET_NEXT_PROP;
store := true;
store_fetch := true;
when 20 => -- add a b -> (result)
instruction := OP_ADD;
store := true;
store_fetch := true;
when 21 => -- sub a b -> (result)
instruction := OP_SUB;
store := true;
store_fetch := true;
when 22 => -- mul a b -> (result)
instruction := OP_MUL;
store := true;
store_fetch := true;
when 23 => -- div a b -> (result)
instruction := OP_DIV;
store := true;
store_fetch := true;
when 24 => -- mod a b -> (result)
instruction := OP_MOD;
store := true;
store_fetch := true;
when others =>
cursor := 0;
state := ERROR;
message := pad_string("Instruction undecodable. Long", message'LENGTH, ram_dat_r);
end case;
end if;
---------------------------------------------------------------------------------------------------------------------------------------
-- INTERPRETER STATES
---------------------------------------------
when RESET => -- splash screen
fb_a_en <= '1';
fb_a_we <= "1";
fb_a_dat_in <= clk_1 & std_logic_vector(to_unsigned(character'pos(blinkData(cursor + 1)), 7));
fb_a_addr <= std_logic_vector(to_unsigned(cursor + COLS * 21 + 66, 14));
cursor := cursor_delta(cursor, modulo => blinkData'LENGTH);
if kb_event = '1' then
cursor := 0;
state := BLANK;
next_state := LOAD;
end if;
---------------------------------------------
when BLANK => -- erase all of the screen
fb_a_en <= '1';
fb_a_we <= "1";
fb_a_addr <= std_logic_vector(to_unsigned(cursor, 14));
fb_a_dat_in <= x"00";
cursor := cursor_delta(cursor);
if cursor = 0 then
state := next_state;
next_state := RESET;
end if;
---------------------------------------------
when ERROR =>
fb_a_en <= '1';
fb_a_we <= "1";
fb_a_dat_in <= '1' & std_logic_vector(to_unsigned(character'pos(message(cursor + 1)), 7));
fb_a_addr <= std_logic_vector(to_unsigned(cursor, 14));
cursor := cursor_delta(cursor, modulo => message'LENGTH);
if cursor = 0 then
cursor := COLS;
state := DEBUG;
end if;
---------------------------------------------
when LOAD =>
cursor := cursor_delta(cursor);
ram_re <= "11";
case cursor is
when 1 =>
ram_re <= "10";
ram_addr <= 16#00#;
when 2 =>
if ram_dat_r(15 downto 8) /= x"03" then
cursor := 0;
state := ERROR;
message := pad_string("Version != 3", message'LENGTH);
end if;
ram_addr <= 16#01#; -- Flags 1
when 3 =>
ram_re <= "00";
flags1 := ram_dat_r;
-- SET FLAGS 1 BITS
flags1(4) := '0';
flags1(5) := '0';
flags1(6) := '0';
ram_dat_w <= flags1;
ram_we <= "11";
when 4 =>
ram_addr <= 16#04#; -- Base of high memory (byte address)
when 5 =>
high := to_integer(unsigned(ram_dat_r));
ram_addr <= 16#06#; -- Initial value of program counter (byte address)
when 6 =>
pc := to_integer(unsigned(ram_dat_r));
ram_addr <= 16#08#; -- Location of dictionary (byte address)
when 7 =>
dict := to_integer(unsigned(ram_dat_r));
ram_addr <= 16#0A#; -- Location of object table (byte address)
when 8 =>
objtab := to_integer(unsigned(ram_dat_r));
ram_addr <= 16#0C#; -- Location of global variables table (byte address)
when 9 =>
globals := to_integer(unsigned(ram_dat_r));
ram_addr <= 16#0E#; -- Base of static memory (byte address)
when 10 =>
static := to_integer(unsigned(ram_dat_r));
ram_addr <= 16#10#; -- Flags 2
when 11 =>
flags2 := ram_dat_r;
ram_addr <= 16#18#; -- Location of abbreviations table (byte address)
when 12 =>
abbreviations_start := to_integer(unsigned(ram_dat_r));
ram_addr <= 16#1A#; -- Length of file, Not always available
when 13 =>
length := 2 * to_integer(unsigned(ram_dat_r));
ram_addr <= 16#1C#; -- Checksum, Not always available
when 14 =>
checksum := to_integer(unsigned(ram_dat_r));
when 15 => -- HEADER LOADED
ram_addr <= abbreviations_start;
state := LOAD_ABBR;
cursor := 0;
-- ram_re <= "00";
-- cursor := 0;
-- state := FETCH;
when others =>
ram_re <= "00";
cursor := 0;
state := ERROR;
message := pad_string("Illegal load state.", message'LENGTH);
end case;
---------------------------------------------
when LOAD_ABBR =>
ram_re <= "11";
-- because the abbreviations are always 2n bytes long, they devided the address by 2.
abbreviations(cursor) := 2 * to_integer(unsigned(ram_dat_r));
if cursor = 96 then
ram_re <= "00";
cursor := 0;
state := FETCH;
else
ram_addr <= ram_addr + 2;
cursor := cursor_delta(cursor);
end if;
---------------------------------------------
when SCROLL => -- move all of the screen up one row, read part
fb_a_en <= '1';
-- Read next line's char
fb_a_addr <= std_logic_vector(to_unsigned((cursor + COLS) mod CHARS, 14));
state := SCROLL_W;
when SCROLL_W => -- Write part of scroll state
fb_a_en <= '1';
-- Write current char
fb_a_we <= "1";
fb_a_addr <= std_logic_vector(to_unsigned(cursor, 14));
-- Last line is special
if cursor > COLS * (ROWS - 1) then
fb_a_dat_in <= x"00";
-- Last character is the exit condition
if cursor = CHARS - 1 then
-- Wrap cursor to fist col, last line
cursor := (ROWS - 1) * COLS;
state := next_state;
next_state := RESET;
-- Last line doesn't need to go back to read the mem
else
cursor := cursor_delta(cursor);
state := SCROLL_W;
end if;
-- Copy data
else
cursor := cursor_delta(cursor);
fb_a_dat_in <= fb_a_dat_out;
state := SCROLL;
end if;
---------------------------------------------
when DEBUG =>
fb_a_en <= '1';
fb_a_we <= "1";
fb_a_addr <= std_logic_vector(to_unsigned(cursor, 14));
fb_a_dat_in <= (others => '0');
case cursor is
when 0 to COLS - 1 => -- Leave top line
fb_a_en <= '0';
fb_a_we <= "0";
when COLS + 0 => fb_a_dat_in <= ascii_c('F');
when COLS + 1 => fb_a_dat_in <= ascii_c('l');
when COLS + 2 => fb_a_dat_in <= ascii_c('a');
when COLS + 3 => fb_a_dat_in <= ascii_c('g');
when COLS + 4 => fb_a_dat_in <= ascii_c('s');
when COLS + 5 => fb_a_dat_in <= ascii_c('1');
when COLS + 6 => fb_a_dat_in <= ascii_c(':');
when COLS + 16 => fb_a_dat_in <= ascii_b(flags1(15));
when COLS + 17 => fb_a_dat_in <= ascii_b(flags1(14));
when COLS + 18 => fb_a_dat_in <= ascii_b(flags1(13));
when COLS + 19 => fb_a_dat_in <= ascii_b(flags1(12));
when COLS + 20 => fb_a_dat_in <= ascii_b(flags1(11));
when COLS + 21 => fb_a_dat_in <= ascii_b(flags1(10));
when COLS + 22 => fb_a_dat_in <= ascii_b(flags1(9));
when COLS + 23 => fb_a_dat_in <= ascii_b(flags1(8));
when COLS + 24 => fb_a_dat_in <= ascii_b(flags1(7));
when COLS + 25 => fb_a_dat_in <= ascii_b(flags1(6));
when COLS + 26 => fb_a_dat_in <= ascii_b(flags1(5));
when COLS + 27 => fb_a_dat_in <= ascii_b(flags1(4));
when COLS + 28 => fb_a_dat_in <= ascii_b(flags1(3));
when COLS + 29 => fb_a_dat_in <= ascii_b(flags1(2));
when COLS + 30 => fb_a_dat_in <= ascii_b(flags1(1));
when COLS + 31 => fb_a_dat_in <= ascii_b(flags1(0));
when 2 * COLS + 0 => fb_a_dat_in <= ascii_c('F');
when 2 * COLS + 1 => fb_a_dat_in <= ascii_c('l');
when 2 * COLS + 2 => fb_a_dat_in <= ascii_c('a');
when 2 * COLS + 3 => fb_a_dat_in <= ascii_c('g');
when 2 * COLS + 4 => fb_a_dat_in <= ascii_c('s');
when 2 * COLS + 5 => fb_a_dat_in <= ascii_c('2');
when 2 * COLS + 6 => fb_a_dat_in <= ascii_c(':');
when 2 * COLS + 16 => fb_a_dat_in <= ascii_b(flags2(15));
when 2 * COLS + 17 => fb_a_dat_in <= ascii_b(flags2(14));
when 2 * COLS + 18 => fb_a_dat_in <= ascii_b(flags2(13));
when 2 * COLS + 19 => fb_a_dat_in <= ascii_b(flags2(12));
when 2 * COLS + 20 => fb_a_dat_in <= ascii_b(flags2(11));
when 2 * COLS + 21 => fb_a_dat_in <= ascii_b(flags2(10));
when 2 * COLS + 22 => fb_a_dat_in <= ascii_b(flags2(9));
when 2 * COLS + 23 => fb_a_dat_in <= ascii_b(flags2(8));
when 2 * COLS + 24 => fb_a_dat_in <= ascii_b(flags2(7));
when 2 * COLS + 25 => fb_a_dat_in <= ascii_b(flags2(6));
when 2 * COLS + 26 => fb_a_dat_in <= ascii_b(flags2(5));
when 2 * COLS + 27 => fb_a_dat_in <= ascii_b(flags2(4));
when 2 * COLS + 28 => fb_a_dat_in <= ascii_b(flags2(3));
when 2 * COLS + 29 => fb_a_dat_in <= ascii_b(flags2(2));
when 2 * COLS + 30 => fb_a_dat_in <= ascii_b(flags2(1));
when 2 * COLS + 31 => fb_a_dat_in <= ascii_b(flags2(0));
when 3 * COLS + 0 => fb_a_dat_in <= ascii_c('H');
when 3 * COLS + 1 => fb_a_dat_in <= ascii_c('i');
when 3 * COLS + 2 => fb_a_dat_in <= ascii_c('g');
when 3 * COLS + 3 => fb_a_dat_in <= ascii_c('h');
when 3 * COLS + 4 => fb_a_dat_in <= ascii_c(':');
when 3 * COLS + 16 => fb_a_dat_in <= ascii_c('0');
when 3 * COLS + 17 => fb_a_dat_in <= ascii_c('x');
when 3 * COLS + 18 => fb_a_dat_in <= ascii_x(high, 3);
when 3 * COLS + 19 => fb_a_dat_in <= ascii_x(high, 2);
when 3 * COLS + 20 => fb_a_dat_in <= ascii_x(high, 1);
when 3 * COLS + 21 => fb_a_dat_in <= ascii_x(high, 0);
when 4 * COLS + 0 => fb_a_dat_in <= ascii_c('P');
when 4 * COLS + 1 => fb_a_dat_in <= ascii_c('C');
when 4 * COLS + 2 => fb_a_dat_in <= ascii_c(':');
when 4 * COLS + 3 => fb_a_dat_in <= ascii_c(' ');
when 4 * COLS + 16 => fb_a_dat_in <= ascii_c('0');
when 4 * COLS + 17 => fb_a_dat_in <= ascii_c('x');
when 4 * COLS + 18 => fb_a_dat_in <= ascii_x(pc, 3);
when 4 * COLS + 19 => fb_a_dat_in <= ascii_x(pc, 2);
when 4 * COLS + 20 => fb_a_dat_in <= ascii_x(pc, 1);
when 4 * COLS + 21 => fb_a_dat_in <= ascii_x(pc, 0);
when 5 * COLS + 0 => fb_a_dat_in <= ascii_c('D');
when 5 * COLS + 1 => fb_a_dat_in <= ascii_c('i');
when 5 * COLS + 2 => fb_a_dat_in <= ascii_c('c');
when 5 * COLS + 3 => fb_a_dat_in <= ascii_c('t');
when 5 * COLS + 4 => fb_a_dat_in <= ascii_c(':');
when 5 * COLS + 16 => fb_a_dat_in <= ascii_c('0');
when 5 * COLS + 17 => fb_a_dat_in <= ascii_c('x');
when 5 * COLS + 18 => fb_a_dat_in <= ascii_x(dict, 3);
when 5 * COLS + 19 => fb_a_dat_in <= ascii_x(dict, 2);
when 5 * COLS + 20 => fb_a_dat_in <= ascii_x(dict, 1);
when 5 * COLS + 21 => fb_a_dat_in <= ascii_x(dict, 0);
when 6 * COLS + 0 => fb_a_dat_in <= ascii_c('O');
when 6 * COLS + 1 => fb_a_dat_in <= ascii_c('b');
when 6 * COLS + 2 => fb_a_dat_in <= ascii_c('j');
when 6 * COLS + 3 => fb_a_dat_in <= ascii_c(':');
when 6 * COLS + 16 => fb_a_dat_in <= ascii_c('0');
when 6 * COLS + 17 => fb_a_dat_in <= ascii_c('x');
when 6 * COLS + 18 => fb_a_dat_in <= ascii_x(objtab, 3);
when 6 * COLS + 19 => fb_a_dat_in <= ascii_x(objtab, 2);
when 6 * COLS + 20 => fb_a_dat_in <= ascii_x(objtab, 1);
when 6 * COLS + 21 => fb_a_dat_in <= ascii_x(objtab, 0);
when 7 * COLS + 0 => fb_a_dat_in <= ascii_c('G');
when 7 * COLS + 1 => fb_a_dat_in <= ascii_c('l');
when 7 * COLS + 2 => fb_a_dat_in <= ascii_c('o');
when 7 * COLS + 3 => fb_a_dat_in <= ascii_c('b');
when 7 * COLS + 4 => fb_a_dat_in <= ascii_c('a');
when 7 * COLS + 5 => fb_a_dat_in <= ascii_c('l');
when 7 * COLS + 6 => fb_a_dat_in <= ascii_c('s');
when 7 * COLS + 7 => fb_a_dat_in <= ascii_c(':');
when 7 * COLS + 16 => fb_a_dat_in <= ascii_c('0');
when 7 * COLS + 17 => fb_a_dat_in <= ascii_c('x');
when 7 * COLS + 18 => fb_a_dat_in <= ascii_x(globals, 3);
when 7 * COLS + 19 => fb_a_dat_in <= ascii_x(globals, 2);
when 7 * COLS + 20 => fb_a_dat_in <= ascii_x(globals, 1);
when 7 * COLS + 21 => fb_a_dat_in <= ascii_x(globals, 0);
when 8 * COLS + 0 => fb_a_dat_in <= ascii_c('S');
when 8 * COLS + 1 => fb_a_dat_in <= ascii_c('t');
when 8 * COLS + 2 => fb_a_dat_in <= ascii_c('a');
when 8 * COLS + 3 => fb_a_dat_in <= ascii_c('t');
when 8 * COLS + 4 => fb_a_dat_in <= ascii_c('i');
when 8 * COLS + 5 => fb_a_dat_in <= ascii_c('c');
when 8 * COLS + 6 => fb_a_dat_in <= ascii_c(':');
when 8 * COLS + 16 => fb_a_dat_in <= ascii_c('0');
when 8 * COLS + 17 => fb_a_dat_in <= ascii_c('x');
when 8 * COLS + 18 => fb_a_dat_in <= ascii_x(static, 3);
when 8 * COLS + 19 => fb_a_dat_in <= ascii_x(static, 2);
when 8 * COLS + 20 => fb_a_dat_in <= ascii_x(static, 1);
when 8 * COLS + 21 => fb_a_dat_in <= ascii_x(static, 0);
when 9 * COLS + 0 => fb_a_dat_in <= ascii_c('A');
when 9 * COLS + 1 => fb_a_dat_in <= ascii_c('b');
when 9 * COLS + 2 => fb_a_dat_in <= ascii_c('b');
when 9 * COLS + 3 => fb_a_dat_in <= ascii_c('r');
when 9 * COLS + 4 => fb_a_dat_in <= ascii_c('e');
when 9 * COLS + 5 => fb_a_dat_in <= ascii_c('v');
when 9 * COLS + 6 => fb_a_dat_in <= ascii_c(':');
when 9 * COLS + 16 => fb_a_dat_in <= ascii_c('0');
when 9 * COLS + 17 => fb_a_dat_in <= ascii_c('x');
when 9 * COLS + 18 => fb_a_dat_in <= ascii_x(abbreviations_start, 3);
when 9 * COLS + 19 => fb_a_dat_in <= ascii_x(abbreviations_start, 2);
when 9 * COLS + 20 => fb_a_dat_in <= ascii_x(abbreviations_start, 1);
when 9 * COLS + 21 => fb_a_dat_in <= ascii_x(abbreviations_start, 0);
when 10 * COLS + 0 => fb_a_dat_in <= ascii_c('L');
when 10 * COLS + 1 => fb_a_dat_in <= ascii_c('e');
when 10 * COLS + 2 => fb_a_dat_in <= ascii_c('n');
when 10 * COLS + 3 => fb_a_dat_in <= ascii_c('g');
when 10 * COLS + 4 => fb_a_dat_in <= ascii_c('t');
when 10 * COLS + 5 => fb_a_dat_in <= ascii_c('h');
when 10 * COLS + 6 => fb_a_dat_in <= ascii_c(':');
when 10 * COLS + 16 => fb_a_dat_in <= ascii_i(length, 4);
when 10 * COLS + 17 => fb_a_dat_in <= ascii_i(length, 3);
when 10 * COLS + 18 => fb_a_dat_in <= ascii_i(length, 2);
when 10 * COLS + 19 => fb_a_dat_in <= ascii_i(length, 1);
when 10 * COLS + 20 => fb_a_dat_in <= ascii_i(length, 0);
when 11 * COLS + 0 => fb_a_dat_in <= ascii_c('C');
when 11 * COLS + 1 => fb_a_dat_in <= ascii_c('h');
when 11 * COLS + 2 => fb_a_dat_in <= ascii_c('e');
when 11 * COLS + 3 => fb_a_dat_in <= ascii_c('c');
when 11 * COLS + 4 => fb_a_dat_in <= ascii_c('k');
when 11 * COLS + 5 => fb_a_dat_in <= ascii_c('s');
when 11 * COLS + 6 => fb_a_dat_in <= ascii_c('u');
when 11 * COLS + 7 => fb_a_dat_in <= ascii_c('m');
when 11 * COLS + 8 => fb_a_dat_in <= ascii_c(':');
when 11 * COLS + 16 => fb_a_dat_in <= ascii_c('0');
when 11 * COLS + 17 => fb_a_dat_in <= ascii_c('x');
when 11 * COLS + 18 => fb_a_dat_in <= ascii_x(checksum, 3);
when 11 * COLS + 19 => fb_a_dat_in <= ascii_x(checksum, 2);
when 11 * COLS + 20 => fb_a_dat_in <= ascii_x(checksum, 1);
when 11 * COLS + 21 => fb_a_dat_in <= ascii_x(checksum, 0);
when 12 * COLS + 0 => fb_a_dat_in <= ascii_c('R');
when 12 * COLS + 1 => fb_a_dat_in <= ascii_c('A');
when 12 * COLS + 2 => fb_a_dat_in <= ascii_c('M');
when 12 * COLS + 3 => fb_a_dat_in <= ascii_c(' ');
when 12 * COLS + 4 => fb_a_dat_in <= ascii_c('R');
when 12 * COLS + 5 => fb_a_dat_in <= ascii_c('e');
when 12 * COLS + 6 => fb_a_dat_in <= ascii_c('a');
when 12 * COLS + 7 => fb_a_dat_in <= ascii_c('d');
when 12 * COLS + 8 => fb_a_dat_in <= ascii_c(':');
when 12 * COLS + 16 => fb_a_dat_in <= ascii_c('0');
when 12 * COLS + 17 => fb_a_dat_in <= ascii_c('x');
when 12 * COLS + 18 => fb_a_dat_in <= ascii_x(to_integer(unsigned(ram_dat_r)), 3);
when 12 * COLS + 19 => fb_a_dat_in <= ascii_x(to_integer(unsigned(ram_dat_r)), 2);
when 12 * COLS + 20 => fb_a_dat_in <= ascii_x(to_integer(unsigned(ram_dat_r)), 1);
when 12 * COLS + 21 => fb_a_dat_in <= ascii_x(to_integer(unsigned(ram_dat_r)), 0);
when 12 * COLS + 32 => fb_a_dat_in <= ascii_i(to_integer(unsigned(ram_dat_r)), 4);
when 12 * COLS + 33 => fb_a_dat_in <= ascii_i(to_integer(unsigned(ram_dat_r)), 3);
when 12 * COLS + 34 => fb_a_dat_in <= ascii_i(to_integer(unsigned(ram_dat_r)), 2);
when 12 * COLS + 35 => fb_a_dat_in <= ascii_i(to_integer(unsigned(ram_dat_r)), 1);
when 12 * COLS + 36 => fb_a_dat_in <= ascii_i(to_integer(unsigned(ram_dat_r)), 0);
when 13 * COLS + 0 => fb_a_dat_in <= ascii_c('I');
when 13 * COLS + 1 => fb_a_dat_in <= ascii_c('n');
when 13 * COLS + 2 => fb_a_dat_in <= ascii_c('s');
when 13 * COLS + 3 => fb_a_dat_in <= ascii_c('t');
when 13 * COLS + 4 => fb_a_dat_in <= ascii_c('r');
when 13 * COLS + 5 => fb_a_dat_in <= ascii_c('u');
when 13 * COLS + 6 => fb_a_dat_in <= ascii_c('c');
when 13 * COLS + 7 => fb_a_dat_in <= ascii_c('t');
when 13 * COLS + 8 => fb_a_dat_in <= ascii_c('i');
when 13 * COLS + 9 => fb_a_dat_in <= ascii_c('o');
when 13 * COLS + 10 => fb_a_dat_in <= ascii_c('n');
when 13 * COLS + 11 => fb_a_dat_in <= ascii_c(':');
when 13 * COLS + 16 => fb_a_dat_in <= ascii_c('0');
when 13 * COLS + 17 => fb_a_dat_in <= ascii_c('x');
when 13 * COLS + 18 => fb_a_dat_in <= ascii_x(to_integer(unsigned(instruction_raw)), 1);
when 13 * COLS + 19 => fb_a_dat_in <= ascii_x(to_integer(unsigned(instruction_raw)), 0);
when 14 * COLS + 0 => fb_a_dat_in <= ascii_c('O');
when 14 * COLS + 1 => fb_a_dat_in <= ascii_c('P');
when 14 * COLS + 2 => fb_a_dat_in <= ascii_c('0');
when 14 * COLS + 3 => fb_a_dat_in <= ascii_c(':');
when 14 * COLS + 4 => fb_a_dat_in <= ascii_c(' ');
when 14 * COLS + 5 => fb_a_dat_in <= ascii_b(op0_type(1));
when 14 * COLS + 6 => fb_a_dat_in <= ascii_b(op0_type(0));
when 14 * COLS + 16 => fb_a_dat_in <= ascii_c('0');
when 14 * COLS + 17 => fb_a_dat_in <= ascii_c('x');
when 14 * COLS + 18 => fb_a_dat_in <= ascii_x(to_integer(unsigned(op0)), 3);
when 14 * COLS + 19 => fb_a_dat_in <= ascii_x(to_integer(unsigned(op0)), 2);
when 14 * COLS + 20 => fb_a_dat_in <= ascii_x(to_integer(unsigned(op0)), 1);
when 14 * COLS + 21 => fb_a_dat_in <= ascii_x(to_integer(unsigned(op0)), 0);
when 15 * COLS + 0 => fb_a_dat_in <= ascii_c('O');
when 15 * COLS + 1 => fb_a_dat_in <= ascii_c('P');
when 15 * COLS + 2 => fb_a_dat_in <= ascii_c('1');
when 15 * COLS + 3 => fb_a_dat_in <= ascii_c(':');
when 15 * COLS + 4 => fb_a_dat_in <= ascii_c(' ');
when 15 * COLS + 5 => fb_a_dat_in <= ascii_b(op1_type(1));
when 15 * COLS + 6 => fb_a_dat_in <= ascii_b(op1_type(0));
when 15 * COLS + 16 => fb_a_dat_in <= ascii_c('0');
when 15 * COLS + 17 => fb_a_dat_in <= ascii_c('x');
when 15 * COLS + 18 => fb_a_dat_in <= ascii_x(to_integer(unsigned(op1)), 3);
when 15 * COLS + 19 => fb_a_dat_in <= ascii_x(to_integer(unsigned(op1)), 2);
when 15 * COLS + 20 => fb_a_dat_in <= ascii_x(to_integer(unsigned(op1)), 1);
when 15 * COLS + 21 => fb_a_dat_in <= ascii_x(to_integer(unsigned(op1)), 0);
when 16 * COLS + 0 => fb_a_dat_in <= ascii_c('O');
when 16 * COLS + 1 => fb_a_dat_in <= ascii_c('P');
when 16 * COLS + 2 => fb_a_dat_in <= ascii_c('2');
when 16 * COLS + 3 => fb_a_dat_in <= ascii_c(':');
when 16 * COLS + 4 => fb_a_dat_in <= ascii_c(' ');
when 16 * COLS + 5 => fb_a_dat_in <= ascii_b(op2_type(1));
when 16 * COLS + 6 => fb_a_dat_in <= ascii_b(op2_type(0));
when 16 * COLS + 16 => fb_a_dat_in <= ascii_c('0');
when 16 * COLS + 17 => fb_a_dat_in <= ascii_c('x');
when 16 * COLS + 18 => fb_a_dat_in <= ascii_x(to_integer(unsigned(op2)), 3);
when 16 * COLS + 19 => fb_a_dat_in <= ascii_x(to_integer(unsigned(op2)), 2);
when 16 * COLS + 20 => fb_a_dat_in <= ascii_x(to_integer(unsigned(op2)), 1);
when 16 * COLS + 21 => fb_a_dat_in <= ascii_x(to_integer(unsigned(op2)), 0);
when 17 * COLS + 0 => fb_a_dat_in <= ascii_c('O');
when 17 * COLS + 1 => fb_a_dat_in <= ascii_c('P');
when 17 * COLS + 2 => fb_a_dat_in <= ascii_c('3');
when 17 * COLS + 3 => fb_a_dat_in <= ascii_c(':');
when 17 * COLS + 4 => fb_a_dat_in <= ascii_c(' ');
when 17 * COLS + 5 => fb_a_dat_in <= ascii_b(op3_type(1));
when 17 * COLS + 6 => fb_a_dat_in <= ascii_b(op3_type(0));
when 17 * COLS + 16 => fb_a_dat_in <= ascii_c('0');
when 17 * COLS + 17 => fb_a_dat_in <= ascii_c('x');
when 17 * COLS + 18 => fb_a_dat_in <= ascii_x(to_integer(unsigned(op3)), 3);
when 17 * COLS + 19 => fb_a_dat_in <= ascii_x(to_integer(unsigned(op3)), 2);
when 17 * COLS + 20 => fb_a_dat_in <= ascii_x(to_integer(unsigned(op3)), 1);
when 17 * COLS + 21 => fb_a_dat_in <= ascii_x(to_integer(unsigned(op3)), 0);
when 18 * COLS + 0 => fb_a_dat_in <= ascii_c('S');
when 18 * COLS + 1 => fb_a_dat_in <= ascii_c('t');
when 18 * COLS + 2 => fb_a_dat_in <= ascii_c('o');
when 18 * COLS + 3 => fb_a_dat_in <= ascii_c('r');
when 18 * COLS + 4 => fb_a_dat_in <= ascii_c('e');
when 18 * COLS + 5 => fb_a_dat_in <= ascii_c(':');
when 18 * COLS + 6 => fb_a_dat_in <= ascii_c(' ');
when 18 * COLS + 16 => fb_a_dat_in <= ascii_c('0');
when 18 * COLS + 17 => fb_a_dat_in <= ascii_c('x');
when 18 * COLS + 18 => fb_a_dat_in <= ascii_x(to_integer(unsigned(store_var)), 1);
when 18 * COLS + 19 => fb_a_dat_in <= ascii_x(to_integer(unsigned(store_var)), 0);
when 19 * COLS + 0 => fb_a_dat_in <= ascii_c('B');
when 19 * COLS + 1 => fb_a_dat_in <= ascii_c('r');
when 19 * COLS + 2 => fb_a_dat_in <= ascii_c('a');
when 19 * COLS + 3 => fb_a_dat_in <= ascii_c('n');
when 19 * COLS + 4 => fb_a_dat_in <= ascii_c('c');
when 19 * COLS + 5 => fb_a_dat_in <= ascii_c('h');
when 19 * COLS + 6 => fb_a_dat_in <= ascii_c(':');
when 19 * COLS + 7 => fb_a_dat_in <= ascii_c(' ');
when 19 * COLS + 16 => fb_a_dat_in <= ascii_i(branch_offset, 6, false, true);
when 19 * COLS + 17 => fb_a_dat_in <= ascii_i(branch_offset, 5);
when 19 * COLS + 18 => fb_a_dat_in <= ascii_i(branch_offset, 4);
when 19 * COLS + 19 => fb_a_dat_in <= ascii_i(branch_offset, 3);
when 19 * COLS + 20 => fb_a_dat_in <= ascii_i(branch_offset, 2);
when 19 * COLS + 21 => fb_a_dat_in <= ascii_i(branch_offset, 1);
when 19 * COLS + 22 => fb_a_dat_in <= ascii_i(branch_offset, 0);
when 20 * COLS + 0 => fb_a_dat_in <= ascii_c('T');
when 20 * COLS + 1 => fb_a_dat_in <= ascii_c('e');
when 20 * COLS + 2 => fb_a_dat_in <= ascii_c('x');
when 20 * COLS + 3 => fb_a_dat_in <= ascii_c('t');
when 20 * COLS + 4 => fb_a_dat_in <= ascii_c(' ');
when 20 * COLS + 5 => fb_a_dat_in <= ascii_c('s');
when 20 * COLS + 6 => fb_a_dat_in <= ascii_c('i');
when 20 * COLS + 7 => fb_a_dat_in <= ascii_c('z');
when 20 * COLS + 8 => fb_a_dat_in <= ascii_c('e');
when 20 * COLS + 10 => fb_a_dat_in <= ascii_i(string_pointer, 4);
when 20 * COLS + 11 => fb_a_dat_in <= ascii_i(string_pointer, 3);
when 20 * COLS + 12 => fb_a_dat_in <= ascii_i(string_pointer, 2);
when 20 * COLS + 13 => fb_a_dat_in <= ascii_i(string_pointer, 1);
when 20 * COLS + 14 => fb_a_dat_in <= ascii_i(string_pointer, 0);
when 21 * COLS to (22 * COLS) - 1 => fb_a_dat_in <= ascii_c(string_buffer(cursor - (21 * COLS)));
when others =>
-- Nothing
end case;
cursor := cursor_delta(cursor);
if cursor = 0 then
state := DEBUG_KB;
cursor := 32 * COLS;
end if;
when DEBUG_KB =>
if kb_event = '1' then
-- By default, we want to write a space to the current position
fb_a_en <= '1';
fb_a_we <= "1";
fb_a_addr <= std_logic_vector(to_unsigned(cursor, 14));
fb_a_dat_in <= "00100000"; -- space
-- IF Backspace
if kb_acsii = "0001000" then
cursor := cursor_delta(cursor, -1);
-- ELSE IF Enter (treated like carage return, not line feed)
elsif kb_acsii = "0001101" then
if cursor / COLS = (ROWS - 1) then
state := SCROLL;
next_state := DEBUG_KB;
cursor := 0;
else
cursor := cursor_delta(cursor, COLS - (cursor mod COLS));
end if;
-- ELSE IF NULL Continue
elsif kb_acsii = "0000000" then
state := FETCH;
-- ELSE IF Delete (wipe whole screen)
elsif kb_acsii = "1111111" then
fb_a_en <= '0';
fb_a_we <= "0";
cursor := 0;
state := BLANK;
next_state := DEBUG_KB;
-- OTHERWISE print character to screen
else
fb_a_dat_in <= '0' & kb_acsii;
cursor := cursor_delta(cursor);
end if;
-- No kb event, blink cursors
else
fb_a_en <= '1';
fb_a_we <= "1";
fb_a_addr <= std_logic_vector(to_unsigned(cursor, 14));
if clk_2 = '1' then
fb_a_dat_in <= "00100000"; -- space
else
fb_a_dat_in <= "01011111"; -- underscore
end if;
end if;
---------------------------------------------
when others => -- WTF?
cursor := 0;
state := ERROR;
message := pad_string("Illegal state", message'LENGTH);
end case;
end if;
end if;
end process;
end Behavioral;
|
-- -------------------------------------------------------------
--
-- File Name: hdl_prj/hdlsrc/OFDM_transmitter/RADIX22FFT_SDNF1_1_block2.vhd
-- Created: 2017-03-27 15:50:06
--
-- Generated by MATLAB 9.1 and HDL Coder 3.9
--
-- -------------------------------------------------------------
-- -------------------------------------------------------------
--
-- Module: RADIX22FFT_SDNF1_1_block2
-- Source Path: OFDM_transmitter/IFFT HDL Optimized/RADIX22FFT_SDNF1_1
-- Hierarchy Level: 2
--
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY RADIX22FFT_SDNF1_1_block2 IS
PORT( clk : IN std_logic;
reset : IN std_logic;
enb_1_16_0 : IN std_logic;
twdlXdin_4_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_4_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_12_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_12_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_1_vld : IN std_logic;
softReset : IN std_logic;
dout_7_re : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_7_im : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_8_re : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_8_im : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_7_vld : OUT std_logic
);
END RADIX22FFT_SDNF1_1_block2;
ARCHITECTURE rtl OF RADIX22FFT_SDNF1_1_block2 IS
-- Signals
SIGNAL twdlXdin_4_re_signed : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL twdlXdin_4_im_signed : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL twdlXdin_12_re_signed : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL twdlXdin_12_im_signed : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL Radix22ButterflyG1_NF_btf1_re_reg : signed(16 DOWNTO 0); -- sfix17
SIGNAL Radix22ButterflyG1_NF_btf1_im_reg : signed(16 DOWNTO 0); -- sfix17
SIGNAL Radix22ButterflyG1_NF_btf2_re_reg : signed(16 DOWNTO 0); -- sfix17
SIGNAL Radix22ButterflyG1_NF_btf2_im_reg : signed(16 DOWNTO 0); -- sfix17
SIGNAL Radix22ButterflyG1_NF_dinXtwdl_vld_dly1 : std_logic;
SIGNAL Radix22ButterflyG1_NF_btf1_re_reg_next : signed(16 DOWNTO 0); -- sfix17_En13
SIGNAL Radix22ButterflyG1_NF_btf1_im_reg_next : signed(16 DOWNTO 0); -- sfix17_En13
SIGNAL Radix22ButterflyG1_NF_btf2_re_reg_next : signed(16 DOWNTO 0); -- sfix17_En13
SIGNAL Radix22ButterflyG1_NF_btf2_im_reg_next : signed(16 DOWNTO 0); -- sfix17_En13
SIGNAL Radix22ButterflyG1_NF_dinXtwdl_vld_dly1_next : std_logic;
SIGNAL dout_7_re_tmp : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL dout_7_im_tmp : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL dout_8_re_tmp : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL dout_8_im_tmp : signed(15 DOWNTO 0); -- sfix16_En13
BEGIN
twdlXdin_4_re_signed <= signed(twdlXdin_4_re);
twdlXdin_4_im_signed <= signed(twdlXdin_4_im);
twdlXdin_12_re_signed <= signed(twdlXdin_12_re);
twdlXdin_12_im_signed <= signed(twdlXdin_12_im);
-- Radix22ButterflyG1_NF
Radix22ButterflyG1_NF_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
Radix22ButterflyG1_NF_btf1_re_reg <= to_signed(16#00000#, 17);
Radix22ButterflyG1_NF_btf1_im_reg <= to_signed(16#00000#, 17);
Radix22ButterflyG1_NF_btf2_re_reg <= to_signed(16#00000#, 17);
Radix22ButterflyG1_NF_btf2_im_reg <= to_signed(16#00000#, 17);
Radix22ButterflyG1_NF_dinXtwdl_vld_dly1 <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
Radix22ButterflyG1_NF_btf1_re_reg <= Radix22ButterflyG1_NF_btf1_re_reg_next;
Radix22ButterflyG1_NF_btf1_im_reg <= Radix22ButterflyG1_NF_btf1_im_reg_next;
Radix22ButterflyG1_NF_btf2_re_reg <= Radix22ButterflyG1_NF_btf2_re_reg_next;
Radix22ButterflyG1_NF_btf2_im_reg <= Radix22ButterflyG1_NF_btf2_im_reg_next;
Radix22ButterflyG1_NF_dinXtwdl_vld_dly1 <= Radix22ButterflyG1_NF_dinXtwdl_vld_dly1_next;
END IF;
END IF;
END PROCESS Radix22ButterflyG1_NF_process;
Radix22ButterflyG1_NF_output : PROCESS (Radix22ButterflyG1_NF_btf1_re_reg, Radix22ButterflyG1_NF_btf1_im_reg,
Radix22ButterflyG1_NF_btf2_re_reg, Radix22ButterflyG1_NF_btf2_im_reg,
Radix22ButterflyG1_NF_dinXtwdl_vld_dly1, twdlXdin_4_re_signed,
twdlXdin_4_im_signed, twdlXdin_12_re_signed, twdlXdin_12_im_signed,
twdlXdin_1_vld)
VARIABLE add_cast : signed(16 DOWNTO 0);
VARIABLE add_cast_0 : signed(16 DOWNTO 0);
VARIABLE sra_temp : signed(16 DOWNTO 0);
VARIABLE sub_cast : signed(16 DOWNTO 0);
VARIABLE sub_cast_0 : signed(16 DOWNTO 0);
VARIABLE sra_temp_0 : signed(16 DOWNTO 0);
VARIABLE add_cast_1 : signed(16 DOWNTO 0);
VARIABLE add_cast_2 : signed(16 DOWNTO 0);
VARIABLE sra_temp_1 : signed(16 DOWNTO 0);
VARIABLE sub_cast_1 : signed(16 DOWNTO 0);
VARIABLE sub_cast_2 : signed(16 DOWNTO 0);
VARIABLE sra_temp_2 : signed(16 DOWNTO 0);
BEGIN
Radix22ButterflyG1_NF_btf1_re_reg_next <= Radix22ButterflyG1_NF_btf1_re_reg;
Radix22ButterflyG1_NF_btf1_im_reg_next <= Radix22ButterflyG1_NF_btf1_im_reg;
Radix22ButterflyG1_NF_btf2_re_reg_next <= Radix22ButterflyG1_NF_btf2_re_reg;
Radix22ButterflyG1_NF_btf2_im_reg_next <= Radix22ButterflyG1_NF_btf2_im_reg;
Radix22ButterflyG1_NF_dinXtwdl_vld_dly1_next <= twdlXdin_1_vld;
IF twdlXdin_1_vld = '1' THEN
add_cast := resize(twdlXdin_4_re_signed, 17);
add_cast_0 := resize(twdlXdin_12_re_signed, 17);
Radix22ButterflyG1_NF_btf1_re_reg_next <= add_cast + add_cast_0;
sub_cast := resize(twdlXdin_4_re_signed, 17);
sub_cast_0 := resize(twdlXdin_12_re_signed, 17);
Radix22ButterflyG1_NF_btf2_re_reg_next <= sub_cast - sub_cast_0;
add_cast_1 := resize(twdlXdin_4_im_signed, 17);
add_cast_2 := resize(twdlXdin_12_im_signed, 17);
Radix22ButterflyG1_NF_btf1_im_reg_next <= add_cast_1 + add_cast_2;
sub_cast_1 := resize(twdlXdin_4_im_signed, 17);
sub_cast_2 := resize(twdlXdin_12_im_signed, 17);
Radix22ButterflyG1_NF_btf2_im_reg_next <= sub_cast_1 - sub_cast_2;
END IF;
sra_temp := SHIFT_RIGHT(Radix22ButterflyG1_NF_btf1_re_reg, 1);
dout_7_re_tmp <= sra_temp(15 DOWNTO 0);
sra_temp_0 := SHIFT_RIGHT(Radix22ButterflyG1_NF_btf1_im_reg, 1);
dout_7_im_tmp <= sra_temp_0(15 DOWNTO 0);
sra_temp_1 := SHIFT_RIGHT(Radix22ButterflyG1_NF_btf2_re_reg, 1);
dout_8_re_tmp <= sra_temp_1(15 DOWNTO 0);
sra_temp_2 := SHIFT_RIGHT(Radix22ButterflyG1_NF_btf2_im_reg, 1);
dout_8_im_tmp <= sra_temp_2(15 DOWNTO 0);
dout_7_vld <= Radix22ButterflyG1_NF_dinXtwdl_vld_dly1;
END PROCESS Radix22ButterflyG1_NF_output;
dout_7_re <= std_logic_vector(dout_7_re_tmp);
dout_7_im <= std_logic_vector(dout_7_im_tmp);
dout_8_re <= std_logic_vector(dout_8_re_tmp);
dout_8_im <= std_logic_vector(dout_8_im_tmp);
END rtl;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
-- Entity: i2c2ahb
-- File: i2c2ahb.vhd
-- Author: Jan Andersson - Aeroflex Gaisler AB
-- Contact: [email protected]
-- Description: Simple I2C-slave providing a bridge to AMBA AHB
-- See i2c2ahbx.vhd and GRIP for documentation
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.conv_std_logic_vector;
library gaisler;
use gaisler.i2c.all;
entity i2c2ahb is
generic (
-- AHB Configuration
hindex : integer := 0;
--
ahbaddrh : integer := 0;
ahbaddrl : integer := 0;
ahbmaskh : integer := 0;
ahbmaskl : integer := 0;
-- I2C configuration
i2cslvaddr : integer range 0 to 127 := 0;
i2ccfgaddr : integer range 0 to 127 := 0;
oepol : integer range 0 to 1 := 0;
--
filter : integer range 2 to 512 := 2
);
port (
rstn : in std_ulogic;
clk : in std_ulogic;
-- AHB master interface
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
-- I2C signals
i2ci : in i2c_in_type;
i2co : out i2c_out_type
);
end entity i2c2ahb;
architecture rtl of i2c2ahb is
signal i2c2ahbi : i2c2ahb_in_type;
begin
bridge : i2c2ahbx
generic map (
hindex => hindex,
oepol => oepol,
filter => filter)
port map (
rstn => rstn,
clk => clk,
ahbi => ahbi,
ahbo => ahbo,
i2ci => i2ci,
i2co => i2co,
i2c2ahbi => i2c2ahbi,
i2c2ahbo => open);
i2c2ahbi.en <= '1';
i2c2ahbi.haddr <= conv_std_logic_vector(ahbaddrh, 16) &
conv_std_logic_vector(ahbaddrl, 16);
i2c2ahbi.hmask <= conv_std_logic_vector(ahbmaskh, 16) &
conv_std_logic_vector(ahbmaskl, 16);
i2c2ahbi.slvaddr <= conv_std_logic_vector(i2cslvaddr, 7);
i2c2ahbi.cfgaddr <= conv_std_logic_vector(i2ccfgaddr, 7);
end architecture rtl;
|
---------------------------------------------------------------------
-- --
-- This file is generated automatically by AUDI (AUtomatic --
-- Design Instantiation) system, a behavioral synthesis system, --
-- developed at the University of South Florida. This project --
-- is supported by the National Science Foundation (NSF) under --
-- the project number XYZ. If you have any questions, contact --
-- Dr. Srinivas Katkoori ([email protected]), Computer --
-- Science & Engineering Department, University of South Florida, --
-- Tampa, FL 33647. --
-- --
---------------------------------------------------------------------
--
-- Date & Time:
-- User login id/name:
--
-- File name:
-- Type:
--
-- Input aif file name:
--
-- CDFG statistics:
-- * Number of PI's:
-- * Number of PO's:
-- * Number of internal edges:
-- * Number of Operations:
-- * Conditionals:
-- * Loops:
-- * Types of Operations:
--
-- Design Flow/Algorithm Information:
-- * Scheduling Algorithm:
-- * Allocation:
-- * Binding:
-- Interconnect style: Multiplexor-Based or Bus-based
--
-- Design Information:
--
-- Datapath:
-- * Registers:
-- * Functional units:
-- * Number of Multiplexors:
-- * Number of Buses:
--
-- * Operator Binding Information:
--
-- * Register Optimization Information:
--
-- * Register Binding Information:
--
--
-- Controller:
-- * Type: Moore/Mealy
-- * Number of states:
-- * Number of control bits:
--
---------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library Beh_Lib;
use Beh_Lib.all;
entity input_dp is
port( a : IN std_logic_vector(3 downto 0);
b : IN std_logic_vector(3 downto 0);
c : IN std_logic_vector(3 downto 0);
d : IN std_logic_vector(3 downto 0);
e : IN std_logic_vector(3 downto 0);
f : IN std_logic_vector(3 downto 0);
g : IN std_logic_vector(3 downto 0);
h : IN std_logic_vector(3 downto 0);
i : OUT std_logic_vector(3 downto 0);
ctrl: IN std_logic_vector(14 downto 0);
clear: IN std_logic;
clock: IN std_logic
);
end input_dp;
architecture RTL of input_dp is
component c_register
generic (width : integer := 4);
port (input : in std_logic_vector((width-1) downto 0);
WR: in std_logic;
clear : in std_logic;
clock : in std_logic;
output : out std_logic_vector((width -1) downto 0));
end component;
-- for all : c_register use entity Beh_Lib.c_register(behavior);
component C_Latch
generic (width : integer);
port( input : in Std_logic_vector ((width - 1) downto 0);
ENABLE : in Std_logic;
CLEAR : in Std_logic;
CLOCK : in Std_logic;
output : out Std_logic_vector ((width - 1) downto 0));
end component;
-- for all : C_Latch use entity Beh_Lib.C_Latch(Behavior);
component Constant_Reg
generic (width : integer;
const : integer);
port( output : out Std_logic_vector ((width - 1) downto 0));
end component;
-- for all : Constant_Reg use entity Beh_Lib.Constant_Reg(Behavior);
component Shift_Reg
generic (width : integer);
port( input : in Std_logic_vector ((width - 1) downto 0);
CONTROL : in Std_logic_vector (1 downto 0);
CLEAR : in Std_logic;
CLOCK : in Std_logic;
output : out Std_logic_vector ((width - 1) downto 0));
end component;
-- for all : Shift_Reg use entity Beh_Lib.Shift_Reg(Behavior);
component C_Signal
generic (width : integer);
port( input : in Std_logic_vector ((width - 1) downto 0);
STORE : in Std_logic;
UPDATE : in Std_logic;
CLEAR : in Std_logic;
CLOCK : in Std_logic;
output : out Std_logic_vector ((width + 1) downto 0));
end component;
-- for all : C_Signal use entity Beh_Lib.C_Signal(Behavior);
component Ram
generic (width : integer;
ram_select : integer);
port( input1 : in Std_logic_vector ((width - 1) downto 0);
input2 : in Std_logic_vector ((ram_select - 1) downto 0);
WR : in Std_logic;
RD : in Std_logic;
CLOCK : in Std_logic;
output : out Std_logic_vector ((width - 1) downto 0));
end component;
-- for all : Ram use entity Beh_Lib.Ram(Behavior);
component C_Adder
generic (width : integer);
port( input1 : in Std_logic_vector ((width - 1) downto 0);
input2 : in Std_logic_vector ((width - 1) downto 0);
output : out Std_logic_vector (width downto 0));
end component;
-- for all : C_Adder use entity Beh_Lib.C_Adder(Behavior);
component C_subtractor
generic (width : integer);
port( input1 : in Std_logic_vector ((width - 1) downto 0);
input2 : in Std_logic_vector ((width - 1) downto 0);
output : out Std_logic_vector (width downto 0));
end component;
-- for all : C_Subtractor use entity Beh_Lib.C_Subtractor(Behavior);
component C_Comparator
generic (width : integer);
port( input1 : in Std_logic_vector ((width - 1) downto 0);
input2 : in Std_logic_vector ((width - 1) downto 0);
output : out Std_logic_vector (2 downto 0));
end component;
-- for all : C_Comparator use entity Beh_Lib.C_Comparator(Behavior);
component C_multiplier
generic (width : integer);
port( input1 : in Std_logic_vector ((width - 1) downto 0);
input2 : in Std_logic_vector ((width - 1) downto 0);
output : out Std_logic_vector (((width * 2) - 2) downto 0));
end component;
-- for all : C_Multiplier use entity Beh_Lib.C_Multiplier(Behavior);
component C_Divider
generic (width : integer;
const : integer);
port( input : in Std_logic_vector ((width - 1) downto 0);
output : out Std_logic_vector ((width - 1) downto 0));
end component;
-- for all : C_Divider use entity Beh_Lib.C_Divider(Behavior);
component C_Concat
generic (width1: integer;
width2 : integer);
port( input1 : in Std_logic_vector ((width1 - 1) downto 0);
input2 : in Std_logic_vector ((width2 - 1) downto 0);
output : out Std_logic_vector (((width1 + width2) - 1) downto 0));
end component;
-- for all : C_Concat use entity Beh_Lib.C_Concat(Behavior);
component C_Multiplexer
generic (width : integer;
no_of_inputs : integer;
select_size : integer);
port( input : in Std_logic_vector (((width*no_of_inputs) - 1) downto 0);
MUX_SELECT : in Std_logic_vector ((select_size - 1) downto 0);
output : out Std_logic_vector ((width - 1) downto 0));
end component;
-- for all : C_Multiplexer use entity Beh_Lib.C_Multiplexer(Behavior);
component C_Bus
generic (width : integer;
no_of_inputs : integer);
port( input : in Std_logic_vector (((width*no_of_inputs) - 1) downto 0);
BUS_SELECT : in Std_logic_vector ((no_of_inputs - 1) downto 0);
output : out Std_logic_vector ((width - 1) downto 0));
end component;
-- for all : C_Bus use entity Beh_Lib.C_Bus(Behavior);
component C_And
generic (width : integer);
port( input1 : in Std_logic_vector ((width - 1) downto 0);
input2 : in Std_logic_vector ((width - 1) downto 0);
output : out Std_logic_vector ((width - 1) downto 0));
end component;
-- for all : C_And use entity Beh_Lib.C_And(Behavior);
component C_Or
generic (width : integer);
port( input1 : in Std_logic_vector ((width - 1) downto 0);
input2 : in Std_logic_vector ((width - 1) downto 0);
output : out Std_logic_vector ((width - 1) downto 0));
end component;
-- for all : C_Or use entity Beh_Lib.C_Or(Behavior);
component C_Nand
generic (width : integer);
port( input1 : in Std_logic_vector ((width - 1) downto 0);
input2 : in Std_logic_vector ((width - 1) downto 0);
output : out Std_logic_vector ((width - 1) downto 0));
end component;
-- for all : C_Nand use entity Beh_Lib.C_Nand(Behavior);
component C_Nor
generic (width : integer);
port( input1 : in Std_logic_vector ((width - 1) downto 0);
input2 : in Std_logic_vector ((width - 1) downto 0);
output : out Std_logic_vector ((width - 1) downto 0));
end component;
-- for all : C_Nor use entity Beh_Lib.C_Nor(Behavior);
component C_XNor
generic (width : integer);
port( input1 : in Std_logic_vector ((width - 1) downto 0);
input2 : in Std_logic_vector ((width - 1) downto 0);
output : out Std_logic_vector ((width - 1) downto 0));
end component;
-- for all : C_XNor use entity Beh_Lib.C_XNor(Behavior);
component C_Xor
generic (width : integer);
port( input1 : in Std_logic_vector ((width - 1) downto 0);
input2 : in Std_logic_vector ((width - 1) downto 0);
output : out Std_logic_vector ((width - 1) downto 0));
end component;
-- for all : C_Xor use entity Beh_Lib.C_Xor(Behavior);
component C_Not
generic (width : integer);
port( input : in Std_logic_vector ((width - 1) downto 0);
output : out Std_logic_vector ((width - 1) downto 0));
end component;
-- for all : C_Not use entity Beh_Lib.C_Not(Behavior);
component Tri_State_Buf
generic (width : integer);
port (input : in Std_logic_vector ((width - 1) downto 0);
enable : in Std_logic;
output : out Std_logic_vector ((width - 1) downto 0));
end component;
-- for all : Tri_State_Buf use entity Beh_Lib.Tri_State_Buf(Behavior);
-- Outputs of registers
signal R0_out : Std_logic_vector(3 downto 0);
signal R1_out : Std_logic_vector(3 downto 0);
signal R2_out : Std_logic_vector(3 downto 0);
signal R3_out : Std_logic_vector(3 downto 0);
signal R4_out : Std_logic_vector(3 downto 0);
signal R5_out : Std_logic_vector(3 downto 0);
signal R6_out : Std_logic_vector(3 downto 0);
signal R7_out : Std_logic_vector(3 downto 0);
signal R8_out : Std_logic_vector(3 downto 0);
signal R9_out : Std_logic_vector(3 downto 0);
-- Outputs of FUs
signal FU0_0_out : Std_logic_vector(4 downto 0);
signal FU0_1_out : Std_logic_vector(4 downto 0);
signal FU0_2_out : Std_logic_vector(4 downto 0);
signal FU0_3_out : Std_logic_vector(4 downto 0);
signal FU0_4_out : Std_logic_vector(4 downto 0);
signal FU1_0_out : Std_logic_vector(4 downto 0);
signal FU1_1_out : Std_logic_vector(4 downto 0);
-- Outputs of Interconnect Units
signal Mux0_out : Std_logic_vector(3 downto 0);
signal Mux1_out : Std_logic_vector(3 downto 0);
signal Mux2_out : Std_logic_vector(3 downto 0);
begin
R0 : C_Register
generic map(4)
port map (
input(3 downto 0) => Mux0_out(3 downto 0),
WR => ctrl(0),
CLEAR => clear,
CLOCK => clock,
output => R0_out);
R1 : C_Register
generic map(4)
port map (
input(3 downto 0) => Mux1_out(3 downto 0),
WR => ctrl(1),
CLEAR => clear,
CLOCK => clock,
output => R1_out);
R2 : C_Register
generic map(4)
port map (
input(3 downto 0) => h(3 downto 0),
WR => ctrl(2),
CLEAR => clear,
CLOCK => clock,
output => R2_out);
R3 : C_Register
generic map(4)
port map (
input(3 downto 0) => g(3 downto 0),
WR => ctrl(3),
CLEAR => clear,
CLOCK => clock,
output => R3_out);
R4 : C_Register
generic map(4)
port map (
input(3 downto 0) => f(3 downto 0),
WR => ctrl(4),
CLEAR => clear,
CLOCK => clock,
output => R4_out);
R5 : C_Register
generic map(4)
port map (
input(3 downto 0) => e(3 downto 0),
WR => ctrl(5),
CLEAR => clear,
CLOCK => clock,
output => R5_out);
R6 : C_Register
generic map(4)
port map (
input(3 downto 0) => d(3 downto 0),
WR => ctrl(6),
CLEAR => clear,
CLOCK => clock,
output => R6_out);
R7 : C_Register
generic map(4)
port map (
input(3 downto 0) => c(3 downto 0),
WR => ctrl(7),
CLEAR => clear,
CLOCK => clock,
output => R7_out);
R8 : C_Register
generic map(4)
port map (
input(3 downto 0) => Mux2_out(3 downto 0),
WR => ctrl(8),
CLEAR => clear,
CLOCK => clock,
output => R8_out);
R9 : C_Register
generic map(4)
port map (
input(3 downto 0) => b(3 downto 0),
WR => ctrl(9),
CLEAR => clear,
CLOCK => clock,
output => R9_out);
MULT0_0 : C_Multiplier
generic map(4)
port map (
input1(3 downto 0) => R0_out(3 downto 0),
input2(3 downto 0) => R9_out(3 downto 0),
output(4 downto 0) => FU0_0_out(4 downto 0));
MULT0_1 : C_Multiplier
generic map(4)
port map (
input1(3 downto 0) => R7_out(3 downto 0),
input2(3 downto 0) => R6_out(3 downto 0),
output(4 downto 0) => FU0_1_out(4 downto 0));
MULT0_2 : C_Multiplier
generic map(4)
port map (
input1(3 downto 0) => R5_out(3 downto 0),
input2(3 downto 0) => R4_out(3 downto 0),
output(4 downto 0) => FU0_2_out(4 downto 0));
MULT0_3 : C_Multiplier
generic map(4)
port map (
input1(3 downto 0) => R8_out(3 downto 0),
input2(3 downto 0) => R1_out(3 downto 0),
output(4 downto 0) => FU0_3_out(4 downto 0));
MULT0_4 : C_Multiplier
generic map(4)
port map (
input1(3 downto 0) => R3_out(3 downto 0),
input2(3 downto 0) => R8_out(3 downto 0),
output(4 downto 0) => FU0_4_out(4 downto 0));
SUB1_0 : C_Subtractor
generic map(4)
port map (
input1(3 downto 0) => R1_out(3 downto 0),
input2(3 downto 0) => R2_out(3 downto 0),
output(4 downto 0) => FU1_0_out(4 downto 0));
SUB1_1 : C_Subtractor
generic map(4)
port map (
input1(3 downto 0) => R1_out(3 downto 0),
input2(3 downto 0) => R8_out(3 downto 0),
output(4 downto 0) => FU1_1_out(4 downto 0));
Mux0 : C_Multiplexer
generic map(4, 2, 1)
port map(
input(3 downto 0) => FU1_1_out(3 downto 0),
input(7 downto 4) => a(3 downto 0),
MUX_SELECT(0 downto 0) => ctrl(10 downto 10),
output => Mux0_out);
Mux1 : C_Multiplexer
generic map(4, 3, 2)
port map(
input(3 downto 0) => FU1_0_out(3 downto 0),
input(7 downto 4) => FU0_1_out(3 downto 0),
input(11 downto 8) => FU0_3_out(3 downto 0),
MUX_SELECT(1 downto 0) => ctrl(12 downto 11),
output => Mux1_out);
Mux2 : C_Multiplexer
generic map(4, 3, 2)
port map(
input(3 downto 0) => FU0_0_out(3 downto 0),
input(7 downto 4) => FU0_2_out(3 downto 0),
input(11 downto 8) => FU0_4_out(3 downto 0),
MUX_SELECT(1 downto 0) => ctrl(14 downto 13),
output => Mux2_out);
-- Primary outputs
i(3 downto 0) <= R0_out(3 downto 0);
end RTL;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1676.vhd,v 1.2 2001-10-26 16:30:12 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c09s01b00x00p07n01i01676ent IS
port (p: in boolean);
END c09s01b00x00p07n01i01676ent;
ARCHITECTURE c09s01b00x00p07n01i01676arch OF c09s01b00x00p07n01i01676ent IS
BEGIN
B: block (p)
begin
GUARD <= p; -- Failure_here
end block;
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c09s01b00x00p07n01i01676 - Implicit signal GUARD can not have a source."
severity ERROR;
wait;
END PROCESS TESTING;
END c09s01b00x00p07n01i01676arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1676.vhd,v 1.2 2001-10-26 16:30:12 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c09s01b00x00p07n01i01676ent IS
port (p: in boolean);
END c09s01b00x00p07n01i01676ent;
ARCHITECTURE c09s01b00x00p07n01i01676arch OF c09s01b00x00p07n01i01676ent IS
BEGIN
B: block (p)
begin
GUARD <= p; -- Failure_here
end block;
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c09s01b00x00p07n01i01676 - Implicit signal GUARD can not have a source."
severity ERROR;
wait;
END PROCESS TESTING;
END c09s01b00x00p07n01i01676arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1676.vhd,v 1.2 2001-10-26 16:30:12 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c09s01b00x00p07n01i01676ent IS
port (p: in boolean);
END c09s01b00x00p07n01i01676ent;
ARCHITECTURE c09s01b00x00p07n01i01676arch OF c09s01b00x00p07n01i01676ent IS
BEGIN
B: block (p)
begin
GUARD <= p; -- Failure_here
end block;
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c09s01b00x00p07n01i01676 - Implicit signal GUARD can not have a source."
severity ERROR;
wait;
END PROCESS TESTING;
END c09s01b00x00p07n01i01676arch;
|
-------------------------------------------------------------------------------
-- Entity: lcd
-- Author: Waj
-- Date : 11-May-13
-------------------------------------------------------------------------------
-- Description: (ECS Uebung 9)
-- LCD controller with bus interface and 4-bit data interface.
-------------------------------------------------------------------------------
-- Total # of FFs: ... tbd ...
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.mcu_pkg.all;
entity lcd is
port(rst : in std_logic;
clk : in std_logic;
-- LCD bus signals
bus_in : in t_bus2rws;
bus_out : out t_rws2bus;
-- LCD control/data interface
lcd_out : out std_logic_vector(LCD_PW-1 downto 0)
);
end lcd;
architecture rtl of lcd is
begin
-----------------------------------------------------------------------------
-- sequential process: DUMMY to avoid logic optimization
-- To be replaced.....
-- # of FFs: ......
-----------------------------------------------------------------------------
P_dummy: process(rst, clk)
begin
if rst = '1' then
lcd_out <= (others => '0');
elsif rising_edge(clk) then
if bus_in.wr_enb = '1' then
if unsigned(bus_in.addr) > 0 then
bus_out.data <= bus_in.data;
lcd_out <= bus_in.addr & bus_in.data(3);
end if;
end if;
end if;
end process;
end rtl;
|
-------------------------------------------------------------------------------
-- Entity: lcd
-- Author: Waj
-- Date : 11-May-13
-------------------------------------------------------------------------------
-- Description: (ECS Uebung 9)
-- LCD controller with bus interface and 4-bit data interface.
-------------------------------------------------------------------------------
-- Total # of FFs: ... tbd ...
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.mcu_pkg.all;
entity lcd is
port(rst : in std_logic;
clk : in std_logic;
-- LCD bus signals
bus_in : in t_bus2rws;
bus_out : out t_rws2bus;
-- LCD control/data interface
lcd_out : out std_logic_vector(LCD_PW-1 downto 0)
);
end lcd;
architecture rtl of lcd is
begin
-----------------------------------------------------------------------------
-- sequential process: DUMMY to avoid logic optimization
-- To be replaced.....
-- # of FFs: ......
-----------------------------------------------------------------------------
P_dummy: process(rst, clk)
begin
if rst = '1' then
lcd_out <= (others => '0');
elsif rising_edge(clk) then
if bus_in.wr_enb = '1' then
if unsigned(bus_in.addr) > 0 then
bus_out.data <= bus_in.data;
lcd_out <= bus_in.addr & bus_in.data(3);
end if;
end if;
end if;
end process;
end rtl;
|
-------------------------------------------------------------------------------
-- Entity: lcd
-- Author: Waj
-- Date : 11-May-13
-------------------------------------------------------------------------------
-- Description: (ECS Uebung 9)
-- LCD controller with bus interface and 4-bit data interface.
-------------------------------------------------------------------------------
-- Total # of FFs: ... tbd ...
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.mcu_pkg.all;
entity lcd is
port(rst : in std_logic;
clk : in std_logic;
-- LCD bus signals
bus_in : in t_bus2rws;
bus_out : out t_rws2bus;
-- LCD control/data interface
lcd_out : out std_logic_vector(LCD_PW-1 downto 0)
);
end lcd;
architecture rtl of lcd is
begin
-----------------------------------------------------------------------------
-- sequential process: DUMMY to avoid logic optimization
-- To be replaced.....
-- # of FFs: ......
-----------------------------------------------------------------------------
P_dummy: process(rst, clk)
begin
if rst = '1' then
lcd_out <= (others => '0');
elsif rising_edge(clk) then
if bus_in.wr_enb = '1' then
if unsigned(bus_in.addr) > 0 then
bus_out.data <= bus_in.data;
lcd_out <= bus_in.addr & bus_in.data(3);
end if;
end if;
end if;
end process;
end rtl;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
--
-- This hooks up to the bus, LED display, LEDs, switches and buttons and allows
-- control of the processor. It allows single-stepping of the processor, and
-- when not in debug mode, functions as a memory-mapped peripheral that can
-- control the seven-segments, buttons and LEDs.
--
-- To single-step the CPU, put SW0 into the up position. The LED above it will
-- begin blinking, indicating you are in single-stepping mode. KEY0 can then be
-- used to single-step. Note that all other debugger functions are dependant
-- on this.
--
-- To change what is displayed on the LED display, use SW8 and SW9. With both off,
-- the contents of the data bus is displayed. With SW8 on and SW9 off, the low 16
-- bits of the address bus are displayed. With SW9 on and SW8 off, the IPL and high
-- 8 bits of the address bus are displayed. With both SW8 and SW9 on, the contents
-- of the memory-mapped register is displayed.
--
entity BusMonitor is
PORT(
-- CPU clock
clk_cpu: IN std_logic;
sys_reset: INOUT std_logic;
-- Blinking clock
blink_clk: IN std_logic;
-- 68k bus: system control
bus_reset: IN std_logic;
bus_clk: INOUT std_logic; -- CPU clock
bus_halt: INOUT std_logic;
bus_error: IN std_logic;
-- 68k bus: data
bus_data: INOUT std_logic_vector(15 downto 0);
bus_addr: INOUT std_logic_vector(23 downto 0);
-- 68k bus: bus control
bus_as: INOUT std_logic;
bus_rw: INOUT std_logic; -- read = 1, write = 0
bus_uds: INOUT std_logic; -- upper and lower byte strobes
bus_lds: INOUT std_logic;
bus_dtack: IN std_logic; -- data acknowledge, driven by peripheral
-- 68k bus: bus arbitration
bus_br: INOUT std_logic; -- assert to request bus
bus_bg: IN std_logic; -- asserted when bus is free
bus_bgack: INOUT std_logic; -- assert to acknowledge bus request
-- 68k bus: interrupt control
bus_irq: IN std_logic_vector(2 downto 0);
-- peripherals
HEX0: OUT std_logic_vector(6 downto 0);
HEX1: OUT std_logic_vector(6 downto 0);
HEX2: OUT std_logic_vector(6 downto 0);
HEX3: OUT std_logic_vector(6 downto 0);
SW: IN std_logic_vector(9 downto 0);
KEY: IN std_logic_vector(3 downto 0);
LEDR: OUT std_logic_vector(9 downto 0);
LEDG: OUT std_logic_vector(7 downto 0)
);
end BusMonitor;
architecture behavioral of BusMonitor is
signal hexValue: std_logic_vector(15 downto 0);
begin
-- hex displays
u_hex0: entity work.HexDisplay(behavioral)
port map(
clk => clk_cpu,
reset => sys_reset,
Display => HEX3,
InVal => hexValue(15 downto 12)
);
u_hex1: entity work.HexDisplay(behavioral)
port map(
clk => clk_cpu,
reset => sys_reset,
Display => HEX2,
InVal => hexValue(11 downto 8)
);
u_hex2: entity work.HexDisplay(behavioral)
port map(
clk => clk_cpu,
reset => sys_reset,
Display => HEX1,
InVal => hexValue(7 downto 4)
);
u_hex3: entity work.HexDisplay(behavioral)
port map(
clk => clk_cpu,
reset => sys_reset,
Display => HEX0,
InVal => hexValue(3 downto 0)
);
-- Green LEDs indicate the bus state:
-- BERR | AS | RW | UDS | LDS | DTACK | BR | BG
process(bus_clk, sys_reset, bus_error, bus_as, bus_rw, bus_uds, bus_lds, bus_dtack, bus_br, bus_bg)
begin
if sys_reset='1' then
elsif rising_edge(bus_clk) then
LEDG(7) <= bus_error;
LEDG(6) <= bus_as;
LEDG(5) <= bus_rw;
LEDG(4) <= bus_uds;
LEDG(3) <= bus_lds;
LEDG(2) <= bus_dtack;
LEDG(1) <= bus_br;
LEDG(0) <= bus_bg;
end if;
end process;
-- reset button
sys_reset <= NOT KEY(3);
-- Single-stepping
process(SW(0), KEY(0), blink_clk)
begin
if SW(0)='1' then
bus_clk <= KEY(0);
LEDR(0) <= blink_clk;
else
bus_clk <= clk_cpu;
LEDR(0) <= '0';
end if;
end process;
-- Display
process (SW(9 downto 8))
begin
case SW(9 downto 8) is
when "00" =>
hexValue <= bus_data;
when "01" =>
hexValue <= bus_addr(15 downto 0);
when "10" =>
hexValue <= "0" & bus_irq & "0000" & bus_addr(23 downto 16);
when "11" =>
hexValue <= x"ABCD";
end case;
end process;
end behavioral; |
--------------------------------------------------------------------------------
--
-- Distributed Memory Generator v6.3 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--------------------------------------------------------------------------------
--
--
-- Description:
-- This is the actual DMG core wrapper.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity LUT_exdes is
PORT (
A : IN STD_LOGIC_VECTOR(8-1-(4*0*boolean'pos(8>4)) downto 0)
:= (OTHERS => '0');
D : IN STD_LOGIC_VECTOR(8-1 downto 0) := (OTHERS => '0');
DPRA : IN STD_LOGIC_VECTOR(8-1 downto 0) := (OTHERS => '0');
SPRA : IN STD_LOGIC_VECTOR(8-1 downto 0) := (OTHERS => '0');
CLK : IN STD_LOGIC := '0';
WE : IN STD_LOGIC := '0';
I_CE : IN STD_LOGIC := '1';
QSPO_CE : IN STD_LOGIC := '1';
QDPO_CE : IN STD_LOGIC := '1';
QDPO_CLK : IN STD_LOGIC := '0';
QSPO_RST : IN STD_LOGIC := '0';
QDPO_RST : IN STD_LOGIC := '0';
QSPO_SRST : IN STD_LOGIC := '0';
QDPO_SRST : IN STD_LOGIC := '0';
SPO : OUT STD_LOGIC_VECTOR(8-1 downto 0);
DPO : OUT STD_LOGIC_VECTOR(8-1 downto 0);
QSPO : OUT STD_LOGIC_VECTOR(8-1 downto 0);
QDPO : OUT STD_LOGIC_VECTOR(8-1 downto 0)
);
end LUT_exdes;
architecture xilinx of LUT_exdes is
SIGNAL CLK_i : std_logic;
component LUT is
PORT (
CLK : IN STD_LOGIC;
QSPO : OUT STD_LOGIC_VECTOR(8-1 downto 0);
A : IN STD_LOGIC_VECTOR(8-1-(4*0*boolean'pos(8>4)) downto 0)
:= (OTHERS => '0')
);
end component;
begin
dmg0 : LUT
port map (
CLK => CLK_i,
QSPO => QSPO,
A => A
);
clk_buf: bufg
PORT map(
i => CLK,
o => CLK_i
);
end xilinx;
|
--------------------------------------------------------------------------------
--
-- Distributed Memory Generator v6.3 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--------------------------------------------------------------------------------
--
--
-- Description:
-- This is the actual DMG core wrapper.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity LUT_exdes is
PORT (
A : IN STD_LOGIC_VECTOR(8-1-(4*0*boolean'pos(8>4)) downto 0)
:= (OTHERS => '0');
D : IN STD_LOGIC_VECTOR(8-1 downto 0) := (OTHERS => '0');
DPRA : IN STD_LOGIC_VECTOR(8-1 downto 0) := (OTHERS => '0');
SPRA : IN STD_LOGIC_VECTOR(8-1 downto 0) := (OTHERS => '0');
CLK : IN STD_LOGIC := '0';
WE : IN STD_LOGIC := '0';
I_CE : IN STD_LOGIC := '1';
QSPO_CE : IN STD_LOGIC := '1';
QDPO_CE : IN STD_LOGIC := '1';
QDPO_CLK : IN STD_LOGIC := '0';
QSPO_RST : IN STD_LOGIC := '0';
QDPO_RST : IN STD_LOGIC := '0';
QSPO_SRST : IN STD_LOGIC := '0';
QDPO_SRST : IN STD_LOGIC := '0';
SPO : OUT STD_LOGIC_VECTOR(8-1 downto 0);
DPO : OUT STD_LOGIC_VECTOR(8-1 downto 0);
QSPO : OUT STD_LOGIC_VECTOR(8-1 downto 0);
QDPO : OUT STD_LOGIC_VECTOR(8-1 downto 0)
);
end LUT_exdes;
architecture xilinx of LUT_exdes is
SIGNAL CLK_i : std_logic;
component LUT is
PORT (
CLK : IN STD_LOGIC;
QSPO : OUT STD_LOGIC_VECTOR(8-1 downto 0);
A : IN STD_LOGIC_VECTOR(8-1-(4*0*boolean'pos(8>4)) downto 0)
:= (OTHERS => '0')
);
end component;
begin
dmg0 : LUT
port map (
CLK => CLK_i,
QSPO => QSPO,
A => A
);
clk_buf: bufg
PORT map(
i => CLK,
o => CLK_i
);
end xilinx;
|
--------------------------------------------------------------------------------
--
-- Distributed Memory Generator v6.3 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--------------------------------------------------------------------------------
--
--
-- Description:
-- This is the actual DMG core wrapper.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity LUT_exdes is
PORT (
A : IN STD_LOGIC_VECTOR(8-1-(4*0*boolean'pos(8>4)) downto 0)
:= (OTHERS => '0');
D : IN STD_LOGIC_VECTOR(8-1 downto 0) := (OTHERS => '0');
DPRA : IN STD_LOGIC_VECTOR(8-1 downto 0) := (OTHERS => '0');
SPRA : IN STD_LOGIC_VECTOR(8-1 downto 0) := (OTHERS => '0');
CLK : IN STD_LOGIC := '0';
WE : IN STD_LOGIC := '0';
I_CE : IN STD_LOGIC := '1';
QSPO_CE : IN STD_LOGIC := '1';
QDPO_CE : IN STD_LOGIC := '1';
QDPO_CLK : IN STD_LOGIC := '0';
QSPO_RST : IN STD_LOGIC := '0';
QDPO_RST : IN STD_LOGIC := '0';
QSPO_SRST : IN STD_LOGIC := '0';
QDPO_SRST : IN STD_LOGIC := '0';
SPO : OUT STD_LOGIC_VECTOR(8-1 downto 0);
DPO : OUT STD_LOGIC_VECTOR(8-1 downto 0);
QSPO : OUT STD_LOGIC_VECTOR(8-1 downto 0);
QDPO : OUT STD_LOGIC_VECTOR(8-1 downto 0)
);
end LUT_exdes;
architecture xilinx of LUT_exdes is
SIGNAL CLK_i : std_logic;
component LUT is
PORT (
CLK : IN STD_LOGIC;
QSPO : OUT STD_LOGIC_VECTOR(8-1 downto 0);
A : IN STD_LOGIC_VECTOR(8-1-(4*0*boolean'pos(8>4)) downto 0)
:= (OTHERS => '0')
);
end component;
begin
dmg0 : LUT
port map (
CLK => CLK_i,
QSPO => QSPO,
A => A
);
clk_buf: bufg
PORT map(
i => CLK,
o => CLK_i
);
end xilinx;
|
--------------------------------------------------------------------------------
--
-- Distributed Memory Generator v6.3 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--------------------------------------------------------------------------------
--
--
-- Description:
-- This is the actual DMG core wrapper.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity LUT_exdes is
PORT (
A : IN STD_LOGIC_VECTOR(8-1-(4*0*boolean'pos(8>4)) downto 0)
:= (OTHERS => '0');
D : IN STD_LOGIC_VECTOR(8-1 downto 0) := (OTHERS => '0');
DPRA : IN STD_LOGIC_VECTOR(8-1 downto 0) := (OTHERS => '0');
SPRA : IN STD_LOGIC_VECTOR(8-1 downto 0) := (OTHERS => '0');
CLK : IN STD_LOGIC := '0';
WE : IN STD_LOGIC := '0';
I_CE : IN STD_LOGIC := '1';
QSPO_CE : IN STD_LOGIC := '1';
QDPO_CE : IN STD_LOGIC := '1';
QDPO_CLK : IN STD_LOGIC := '0';
QSPO_RST : IN STD_LOGIC := '0';
QDPO_RST : IN STD_LOGIC := '0';
QSPO_SRST : IN STD_LOGIC := '0';
QDPO_SRST : IN STD_LOGIC := '0';
SPO : OUT STD_LOGIC_VECTOR(8-1 downto 0);
DPO : OUT STD_LOGIC_VECTOR(8-1 downto 0);
QSPO : OUT STD_LOGIC_VECTOR(8-1 downto 0);
QDPO : OUT STD_LOGIC_VECTOR(8-1 downto 0)
);
end LUT_exdes;
architecture xilinx of LUT_exdes is
SIGNAL CLK_i : std_logic;
component LUT is
PORT (
CLK : IN STD_LOGIC;
QSPO : OUT STD_LOGIC_VECTOR(8-1 downto 0);
A : IN STD_LOGIC_VECTOR(8-1-(4*0*boolean'pos(8>4)) downto 0)
:= (OTHERS => '0')
);
end component;
begin
dmg0 : LUT
port map (
CLK => CLK_i,
QSPO => QSPO,
A => A
);
clk_buf: bufg
PORT map(
i => CLK,
o => CLK_i
);
end xilinx;
|
--------------------------------------------------------------------------------
--
-- Distributed Memory Generator v6.3 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--------------------------------------------------------------------------------
--
--
-- Description:
-- This is the actual DMG core wrapper.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity LUT_exdes is
PORT (
A : IN STD_LOGIC_VECTOR(8-1-(4*0*boolean'pos(8>4)) downto 0)
:= (OTHERS => '0');
D : IN STD_LOGIC_VECTOR(8-1 downto 0) := (OTHERS => '0');
DPRA : IN STD_LOGIC_VECTOR(8-1 downto 0) := (OTHERS => '0');
SPRA : IN STD_LOGIC_VECTOR(8-1 downto 0) := (OTHERS => '0');
CLK : IN STD_LOGIC := '0';
WE : IN STD_LOGIC := '0';
I_CE : IN STD_LOGIC := '1';
QSPO_CE : IN STD_LOGIC := '1';
QDPO_CE : IN STD_LOGIC := '1';
QDPO_CLK : IN STD_LOGIC := '0';
QSPO_RST : IN STD_LOGIC := '0';
QDPO_RST : IN STD_LOGIC := '0';
QSPO_SRST : IN STD_LOGIC := '0';
QDPO_SRST : IN STD_LOGIC := '0';
SPO : OUT STD_LOGIC_VECTOR(8-1 downto 0);
DPO : OUT STD_LOGIC_VECTOR(8-1 downto 0);
QSPO : OUT STD_LOGIC_VECTOR(8-1 downto 0);
QDPO : OUT STD_LOGIC_VECTOR(8-1 downto 0)
);
end LUT_exdes;
architecture xilinx of LUT_exdes is
SIGNAL CLK_i : std_logic;
component LUT is
PORT (
CLK : IN STD_LOGIC;
QSPO : OUT STD_LOGIC_VECTOR(8-1 downto 0);
A : IN STD_LOGIC_VECTOR(8-1-(4*0*boolean'pos(8>4)) downto 0)
:= (OTHERS => '0')
);
end component;
begin
dmg0 : LUT
port map (
CLK => CLK_i,
QSPO => QSPO,
A => A
);
clk_buf: bufg
PORT map(
i => CLK,
o => CLK_i
);
end xilinx;
|
--------------------------------------------------------------------------------
--
-- Distributed Memory Generator v6.3 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--------------------------------------------------------------------------------
--
--
-- Description:
-- This is the actual DMG core wrapper.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity LUT_exdes is
PORT (
A : IN STD_LOGIC_VECTOR(8-1-(4*0*boolean'pos(8>4)) downto 0)
:= (OTHERS => '0');
D : IN STD_LOGIC_VECTOR(8-1 downto 0) := (OTHERS => '0');
DPRA : IN STD_LOGIC_VECTOR(8-1 downto 0) := (OTHERS => '0');
SPRA : IN STD_LOGIC_VECTOR(8-1 downto 0) := (OTHERS => '0');
CLK : IN STD_LOGIC := '0';
WE : IN STD_LOGIC := '0';
I_CE : IN STD_LOGIC := '1';
QSPO_CE : IN STD_LOGIC := '1';
QDPO_CE : IN STD_LOGIC := '1';
QDPO_CLK : IN STD_LOGIC := '0';
QSPO_RST : IN STD_LOGIC := '0';
QDPO_RST : IN STD_LOGIC := '0';
QSPO_SRST : IN STD_LOGIC := '0';
QDPO_SRST : IN STD_LOGIC := '0';
SPO : OUT STD_LOGIC_VECTOR(8-1 downto 0);
DPO : OUT STD_LOGIC_VECTOR(8-1 downto 0);
QSPO : OUT STD_LOGIC_VECTOR(8-1 downto 0);
QDPO : OUT STD_LOGIC_VECTOR(8-1 downto 0)
);
end LUT_exdes;
architecture xilinx of LUT_exdes is
SIGNAL CLK_i : std_logic;
component LUT is
PORT (
CLK : IN STD_LOGIC;
QSPO : OUT STD_LOGIC_VECTOR(8-1 downto 0);
A : IN STD_LOGIC_VECTOR(8-1-(4*0*boolean'pos(8>4)) downto 0)
:= (OTHERS => '0')
);
end component;
begin
dmg0 : LUT
port map (
CLK => CLK_i,
QSPO => QSPO,
A => A
);
clk_buf: bufg
PORT map(
i => CLK,
o => CLK_i
);
end xilinx;
|
--
-- Copyright (C) 2012 Chris McClelland
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package hex_util is
function to_1(c : character) return std_logic;
function to_2(c : character) return std_logic_vector;
function to_3(c : character) return std_logic_vector;
function to_4(c : character) return std_logic_vector;
function from_1(oneBit : std_logic) return character;
function from_2(twoBits : std_logic_vector(1 downto 0)) return character;
function from_4(nibble : std_logic_vector(3 downto 0)) return character;
end package;
package body hex_util is
-- Return the bits of the supplied hex nibble
function to_4(c : character) return std_logic_vector is
variable nibble : std_logic_vector(3 downto 0);
begin
case c is
when '0' =>
nibble := "0000";
when '1' =>
nibble := "0001";
when '2' =>
nibble := "0010";
when '3' =>
nibble := "0011";
when '4' =>
nibble := "0100";
when '5' =>
nibble := "0101";
when '6' =>
nibble := "0110";
when '7' =>
nibble := "0111";
when '8' =>
nibble := "1000";
when '9' =>
nibble := "1001";
when 'a' =>
nibble := "1010";
when 'A' =>
nibble := "1010";
when 'b' =>
nibble := "1011";
when 'B' =>
nibble := "1011";
when 'c' =>
nibble := "1100";
when 'C' =>
nibble := "1100";
when 'd' =>
nibble := "1101";
when 'D' =>
nibble := "1101";
when 'e' =>
nibble := "1110";
when 'E' =>
nibble := "1110";
when 'f' =>
nibble := "1111";
when 'F' =>
nibble := "1111";
when 'X' =>
nibble := "XXXX";
when 'x' =>
nibble := "XXXX";
when 'Z' =>
nibble := "ZZZZ";
when 'z' =>
nibble := "ZZZZ";
when others =>
nibble := "UUUU";
end case;
return nibble;
end function;
-- Return the least-significant bit of the supplied hex nibble
function to_1(c : character) return std_logic is
variable nibble : std_logic_vector(3 downto 0);
begin
nibble := to_4(c);
return nibble(0);
end function;
-- Return two least-significant bits of the supplied hex nibble
function to_2(c : character) return std_logic_vector is
variable nibble : std_logic_vector(3 downto 0);
begin
nibble := to_4(c);
return nibble(1 downto 0);
end function;
-- Return three least-significant bits of the supplied hex nibble
function to_3(c : character) return std_logic_vector is
variable nibble : std_logic_vector(3 downto 0);
begin
nibble := to_4(c);
return nibble(2 downto 0);
end function;
-- Return a hex character representation of the supplied std_logic_vector nibble
function from_4(nibble : std_logic_vector(3 downto 0)) return character is
begin
case nibble is
when x"0" =>
return '0';
when x"1" =>
return '1';
when x"2" =>
return '2';
when x"3" =>
return '3';
when x"4" =>
return '4';
when x"5" =>
return '5';
when x"6" =>
return '6';
when x"7" =>
return '7';
when x"8" =>
return '8';
when x"9" =>
return '9';
when x"A" =>
return 'A';
when x"B" =>
return 'B';
when x"C" =>
return 'C';
when x"D" =>
return 'D';
when x"E" =>
return 'E';
when x"F" =>
return 'F';
when "XXXX" =>
return 'X';
when "ZZZZ" =>
return 'Z';
when others =>
return 'U';
end case;
end function;
-- Return a hex character representation of the supplied std_logic_vector nibble
function from_2(twoBits : std_logic_vector(1 downto 0)) return character is
begin
case twoBits is
when "00" =>
return '0';
when "01" =>
return '1';
when "10" =>
return '2';
when "11" =>
return '3';
when "XX" =>
return 'X';
when "ZZ" =>
return 'Z';
when others =>
return 'U';
end case;
end function;
-- Return a 0/1 character representation of the supplied std_logic
function from_1(oneBit : std_logic) return character is
begin
case oneBit is
when '0' =>
return '0';
when '1' =>
return '1';
when 'X' =>
return 'X';
when 'Z' =>
return 'Z';
when others =>
return 'U';
end case;
end function;
end package body;
|
architecture ARCH of ENTITY1 is
begin
U_INST1 : INST1
generic map (
g_gen_1(3 downto 0) => 3,
g_gen_2(2 downto 1) => 4,
g_gen_3 => 5
)
port map (
PORT_1(3 downto 0) => w_port_1,
PORT_2 => w_port_2,
PORT_3(2 downto 1) => w_port_3
);
-- Violations below
U_INST1 : INST1
generic map (
g_gen_1(3 downto 0) => 3,
g_gen_2(2 downto 1) => 4,
g_gen_3 => 5
)
port map (
port_1(3 downto 0) => w_port_1,
port_2 => w_port_2,
port_3(2 downto 1) => w_port_3
);
end architecture ARCH;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use work.UtilityPkg.all;
library UNISIM;
use UNISIM.VComponents.all;
entity K7SerialInterfaceOut is
Generic (
GATE_DELAY_G : time := 1 ns
);
Port (
-- Parallel clock and reset
sstClk : in sl;
sstRst : in sl := '0';
-- Parallel data in
data10bIn : in slv(9 downto 0);
-- Serial clock
sstX5Clk : in sl;
sstX5Rst : in sl := '0';
-- Serial data out
dataOut : out sl
);
end K7SerialInterfaceOut;
architecture Behavioral of K7SerialInterfaceOut is
type StateType is (RESET_S, SEND_AND_READ_S);
type RegType is record
state : StateType;
dataWord : slv(9 downto 0);
bitCount : slv(3 downto 0);
serialDataOutRising : sl;
serialDataOutFalling : sl;
end record RegType;
constant REG_INIT_C : RegType := (
state => RESET_S,
dataWord => (others => '0'),
bitCount => (others => '0'),
serialDataOutRising => '0',
serialDataOutFalling => '0'
);
signal r : RegType := REG_INIT_C;
signal rin : RegType;
signal fifoEmpty : sl;
signal fifoRdData : slv(9 downto 0);
signal fifoRdValid : sl;
begin
-- Instantiate 10 bit FIFO, written on sstClk, read on sstX5Clk
U_SerializationFifo : entity work.SerializationFifo
PORT MAP (
rst => sstRst,
wr_clk => sstClk,
rd_clk => sstX5Clk,
din => data10bIn,
wr_en => '1',
rd_en => not(fifoEmpty),
dout => fifoRdData,
full => open,
empty => fifoEmpty,
valid => fifoRdValid
);
-- Master state machine (combinatorial)
comb : process(r, fifoRdValid, fifoRdData, sstX5Rst) is
variable v : RegType;
begin
v := r;
-- Resets for pulsed outputs
-- None for now
-- State machine
case(r.state) is
when RESET_S =>
v.bitCount := (others => '0');
if (fifoRdValid = '1') then
v.dataWord := fifoRdData;
v.state := SEND_AND_READ_S;
end if;
when SEND_AND_READ_S =>
v.serialDataOutRising := r.dataWord(r.dataWord'left - conv_integer(r.bitCount));
v.serialDataOutFalling := r.dataWord(r.dataWord'left - conv_integer(r.bitCount)-1);
if (r.bitCount = 8) then
v.bitCount := (others => '0');
v.dataWord := fifoRdData;
else
v.bitCount := r.bitCount + 2;
end if;
when others =>
v.state := RESET_S;
end case;
-- Reset logic
if (sstX5Rst = '1') then
v := REG_INIT_C;
end if;
-- Assignment of combinatorial variable to signal
rin <= v;
end process;
-- Master state machine (sequential)
seq : process (sstX5Clk) is
begin
if (rising_edge(sstX5Clk)) then
r <= rin after GATE_DELAY_G;
end if;
end process seq;
-- ODDR to grab the serial data
-- Template here: http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_7/7series_hdl.pdf
-- Documentation here: http://www.xilinx.com/support/documentation/user_guides/ug471_7Series_SelectIO.pdf
gclk_to_output : ODDR
generic map(
DDR_CLK_EDGE => "OPPOSITE_EDGE", -- "OPPOSITE_EDGE" or "SAME_EDGE"
INIT => '0', -- Initial value for Q port ('1' or '0')
SRTYPE => "ASYNC" -- Reset Type ("ASYNC" or "SYNC")
)
port map (
Q => dataOut, -- 1-bit DDR output
C => sstX5Clk, -- 1-bit clock input
CE => '1', -- 1-bit clock enable input
D1 => r.serialDataOutRising, -- 1-bit data input (positive edge)
D2 => r.serialDataOutFalling, -- 1-bit data input (negative edge)
R => '0', -- 1-bit reset input
S => '0' -- 1-bit set input
);
end Behavioral;
|
-- megafunction wizard: %LPM_COMPARE%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: LPM_COMPARE
-- ============================================================
-- File Name: lpm_compare0.vhd
-- Megafunction Name(s):
-- LPM_COMPARE
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.1.0 Build 162 10/23/2013 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY lpm_compare0 IS
PORT
(
dataa : IN STD_LOGIC_VECTOR (16 DOWNTO 0);
ageb : OUT STD_LOGIC
);
END lpm_compare0;
ARCHITECTURE SYN OF lpm_compare0 IS
SIGNAL sub_wire0 : STD_LOGIC ;
SIGNAL sub_wire1_bv : BIT_VECTOR (16 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (16 DOWNTO 0);
COMPONENT lpm_compare
GENERIC (
lpm_hint : STRING;
lpm_representation : STRING;
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
ageb : OUT STD_LOGIC ;
dataa : IN STD_LOGIC_VECTOR (16 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (16 DOWNTO 0)
);
END COMPONENT;
BEGIN
sub_wire1_bv(16 DOWNTO 0) <= "01000110010100000";
sub_wire1 <= To_stdlogicvector(sub_wire1_bv);
ageb <= sub_wire0;
LPM_COMPARE_component : LPM_COMPARE
GENERIC MAP (
lpm_hint => "ONE_INPUT_IS_CONSTANT=YES",
lpm_representation => "UNSIGNED",
lpm_type => "LPM_COMPARE",
lpm_width => 17
)
PORT MAP (
dataa => dataa,
datab => sub_wire1,
ageb => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: AeqB NUMERIC "0"
-- Retrieval info: PRIVATE: AgeB NUMERIC "1"
-- Retrieval info: PRIVATE: AgtB NUMERIC "0"
-- Retrieval info: PRIVATE: AleB NUMERIC "0"
-- Retrieval info: PRIVATE: AltB NUMERIC "0"
-- Retrieval info: PRIVATE: AneB NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "0"
-- Retrieval info: PRIVATE: Latency NUMERIC "0"
-- Retrieval info: PRIVATE: PortBValue NUMERIC "36000"
-- Retrieval info: PRIVATE: Radix NUMERIC "10"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: SignedCompare NUMERIC "0"
-- Retrieval info: PRIVATE: aclr NUMERIC "0"
-- Retrieval info: PRIVATE: clken NUMERIC "0"
-- Retrieval info: PRIVATE: isPortBConstant NUMERIC "1"
-- Retrieval info: PRIVATE: nBit NUMERIC "17"
-- Retrieval info: PRIVATE: new_diagram STRING "1"
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: CONSTANT: LPM_HINT STRING "ONE_INPUT_IS_CONSTANT=YES"
-- Retrieval info: CONSTANT: LPM_REPRESENTATION STRING "UNSIGNED"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_COMPARE"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "17"
-- Retrieval info: USED_PORT: ageb 0 0 0 0 OUTPUT NODEFVAL "ageb"
-- Retrieval info: USED_PORT: dataa 0 0 17 0 INPUT NODEFVAL "dataa[16..0]"
-- Retrieval info: CONNECT: @dataa 0 0 17 0 dataa 0 0 17 0
-- Retrieval info: CONNECT: @datab 0 0 17 0 36000 0 0 17 0
-- Retrieval info: CONNECT: ageb 0 0 0 0 @ageb 0 0 0 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare0.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare0.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare0.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare0.bsf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare0_inst.vhd FALSE
-- Retrieval info: LIB_FILE: lpm
|
entity t5 is
end t5;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of t5 is
signal s : std_logic := '0';
begin
b: block
port (p : out std_logic := 'Z');
port map (p => s);
begin
end block;
b2: block
port (p : out std_logic := '1');
port map (p => s);
begin
end block;
process
begin
wait for 1 ns;
assert s = 'X' severity failure;
wait;
end process;
end behav;
|
-- ========== Copyright Header Begin =============================================
-- AmgPacman File: cont10.vhd
-- Copyright (c) 2015 Alberto Miedes Garcés
-- DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
--
-- The above named program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- The above named program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with Foobar. If not, see <http://www.gnu.org/licenses/>.
-- ========== Copyright Header End ===============================================
----------------------------------------------------------------------------------
-- Engineer: Alberto Miedes Garcés
-- Correo: [email protected]
-- Create Date: January 2015
-- Target Devices: Spartan3E - XC3S500E - Nexys 2 (Digilent)
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- =================================================================================
-- ENTITY
-- =================================================================================
entity cont10 is
Port ( clk : in STD_LOGIC;
ena : in STD_LOGIC;
rst: in std_logic;
fin : out STD_LOGIC);
end cont10;
-- =================================================================================
-- ARCHITECTURE
-- =================================================================================
architecture rtl of cont10 is
-----------------------------------------------------------------------------
-- Declaracion de senales
-----------------------------------------------------------------------------
signal reg_cuenta: std_logic_vector(3 downto 0);
signal reg_cuenta_in: std_logic_vector(3 downto 0);
signal fin_aux: std_logic;
-----------------------------------------------------------------------------
-- Componentes
-----------------------------------------------------------------------------
-- COMPONENT adder4bits_comb
-- PORT(
-- A : IN std_logic_vector(3 downto 0);
-- B : IN std_logic_vector(3 downto 0);
-- Cin : IN std_logic;
-- Z : OUT std_logic_vector(3 downto 0);
-- Cout : OUT std_logic
-- );
-- END COMPONENT;
COMPONENT adder4bits_comb_noCout
PORT(
A : IN std_logic_vector(3 downto 0);
B : IN std_logic_vector(3 downto 0);
Cin : IN std_logic;
Z : OUT std_logic_vector(3 downto 0)
);
END COMPONENT;
begin
-----------------------------------------------------------------------------
-- Conexion de senales
-----------------------------------------------------------------------------
fin <= fin_aux;
-----------------------------------------------------------------------------
-- Conexion de componentes
-----------------------------------------------------------------------------
-- Inst_adder4bits_comb: adder4bits_comb PORT MAP(
-- A => reg_cuenta,
-- B => "0001",
-- Cin => '0',
-- Z => reg_cuenta_in
-- --Cout => disconnected
-- );
Inst_adder4bits_comb_noCout: adder4bits_comb_noCout PORT MAP(
A => reg_cuenta,
B => "0001",
Cin => '0',
Z => reg_cuenta_in
);
-----------------------------------------------------------------------------
-- Procesos
-----------------------------------------------------------------------------
p_cuenta: process(clk, ena, rst)
begin
if rst = '1' then
reg_cuenta <= (others => '0');
fin_aux <= '0';
elsif rising_edge(clk) then
if fin_aux = '1' then
reg_cuenta <= (others => '0');
fin_aux <= '0';
elsif ena = '1' then
if reg_cuenta = "1001" then
fin_aux <= '1';
reg_cuenta <= (others => '0');
else
reg_cuenta <= reg_cuenta_in;
fin_aux <= '0';
end if;
else
fin_aux <= '0';
reg_cuenta <= reg_cuenta;
end if;
end if;
end process p_cuenta;
end rtl;
|
-------------------------------------------------------------------------------
--! @file xf_pkg.vhd
--! @author Johannes Walter <[email protected]>
--! @copyright CERN TE-EPC-CCE
--! @date 2014-07-11
--! @brief Auxiliary FPGA package.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
--! @brief Package declaration of xf_pkg
--! @details
--! This provides types and constants for the Auxiliary FPGA component.
package xf_pkg is
---------------------------------------------------------------------------
-- Types and Constants
---------------------------------------------------------------------------
type xf_in_t is record
--! @brief Signals from XF
--! @param rx_frame 2 x serial frame
--! @param rx_bit_en 2 x serial bit enable
--! @param rx 2 x serial data
rx_frame : std_ulogic_vector(1 downto 0);
rx_bit_en : std_ulogic_vector(1 downto 0);
rx : std_ulogic_vector(1 downto 0);
end record xf_in_t;
type xf_out_t is record
--! @brief Signals to XF
--! @param dim_trig 2 x serial frame
--! @param dim_rst 2 x serial bit enable
--! @param ow_trig 2 x serial data
--! @param ow_bus_select 2 x serial data
dim_trig : std_ulogic;
dim_rst : std_ulogic;
ow_trig : std_ulogic;
ow_bus_select : std_ulogic_vector(2 downto 0);
end record xf_out_t;
end package xf_pkg;
|
-----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov - [email protected]
--! @brief Implementation of the 'starter' module.
--! @details Everytime after hard reset Rocket core is in resetting
--! state. Module Uncore::HTIF implements writting into
--! MRESET CSR-register (0x784) and not allow to start CPU
--! execution. This resetting cycle is ongoing upto external
--! write 0-value into this MRESET register.
-----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library rocketlib;
use rocketlib.types_rocket.all;
--! @brief Hard-reset initialization module.
--! @details L2-cached system implementing Uncore module must be switched
--! from resetting state that is done by this module.
--! param[in] HTIF interface clock.
--! param[in] Reset signal with the active LOW level.
--! param[in] i_host HostIO input signals.
--! param[out] o_host HostIO output signals.
entity starter is port
(
clk : in std_logic;
nrst : in std_logic;
i_host : in host_in_type;
o_host : out host_out_type;
o_init_ena : out std_logic
);
end;
architecture arch_starter of starter is
type state_type is (init_reset, init_cmd, wait_ready, wait_resp, disable);
type registers is record
state : state_type;
init_ena : std_logic;
cmdCnt : integer range 0 to 3;
end record;
signal r, rin: registers;
begin
comblogic : process(i_host, r)
variable v : registers;
begin
v := r;
case r.state is
when init_reset =>
v.state := init_cmd;
o_host.reset <= '1';
o_host.id <= '0';
o_host.csr_req_valid <= '0';
o_host.csr_req_bits_rw <= '0';
o_host.csr_req_bits_addr <= (others => '0');
o_host.csr_req_bits_data <= (others => '0');
o_host.csr_resp_ready <= '1';
when init_cmd =>
o_host.reset <= '0';
--! Select CSR write command
case r.cmdCnt is
when 0 =>
-- PLL divide. One Tile at once.
o_host.csr_req_valid <= '1';
o_host.csr_req_bits_rw <= '1';
o_host.csr_req_bits_addr <= X"03f";
o_host.csr_req_bits_data <= X"0000000000020005";
when 1 =>
-- Set CSR29.
o_host.csr_req_valid <= '1';
o_host.csr_req_bits_rw <= '1';
o_host.csr_req_bits_addr <= X"01d";
o_host.csr_req_bits_data <= X"0000000000000001";
when 2 =>
-- Clear CSR29.
o_host.csr_req_valid <= '1';
o_host.csr_req_bits_rw <= '1';
o_host.csr_req_bits_addr <= X"01d";
o_host.csr_req_bits_data <= X"0000000000000000";
when 3 =>
-- Write MRESET
o_host.csr_req_valid <= '1';
o_host.csr_req_bits_rw <= '1';
o_host.csr_req_bits_addr <= X"782";
o_host.csr_req_bits_data <= X"0000000000000000";
when others =>
v.state := disable;
end case;
if i_host.csr_req_ready = '0' then
v.state := wait_ready;
else
v.state := wait_resp;
end if;
when wait_ready =>
if i_host.csr_req_ready = '1' then
v.state := wait_resp;
o_host.csr_req_valid <= '0';
end if;
when wait_resp =>
if i_host.csr_resp_valid = '1' then
v.cmdCnt := r.cmdCnt + 1;
if r.cmdCnt = 3 then
v.state := disable;
v.init_ena := '0';
else
v.state := init_cmd;
end if;
end if;
when others =>
end case;
rin <= v;
end process;
o_init_ena <= r.init_ena;
-- registers:
regs : process(clk, nrst)
begin
if nrst = '0' then
r.state <= init_reset;
r.init_ena <= '1';
r.cmdCnt <= 0;
elsif rising_edge(clk) then
r <= rin;
end if;
end process;
end;
|
-----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov - [email protected]
--! @brief Implementation of the 'starter' module.
--! @details Everytime after hard reset Rocket core is in resetting
--! state. Module Uncore::HTIF implements writting into
--! MRESET CSR-register (0x784) and not allow to start CPU
--! execution. This resetting cycle is ongoing upto external
--! write 0-value into this MRESET register.
-----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library rocketlib;
use rocketlib.types_rocket.all;
--! @brief Hard-reset initialization module.
--! @details L2-cached system implementing Uncore module must be switched
--! from resetting state that is done by this module.
--! param[in] HTIF interface clock.
--! param[in] Reset signal with the active LOW level.
--! param[in] i_host HostIO input signals.
--! param[out] o_host HostIO output signals.
entity starter is port
(
clk : in std_logic;
nrst : in std_logic;
i_host : in host_in_type;
o_host : out host_out_type;
o_init_ena : out std_logic
);
end;
architecture arch_starter of starter is
type state_type is (init_reset, init_cmd, wait_ready, wait_resp, disable);
type registers is record
state : state_type;
init_ena : std_logic;
cmdCnt : integer range 0 to 3;
end record;
signal r, rin: registers;
begin
comblogic : process(i_host, r)
variable v : registers;
begin
v := r;
case r.state is
when init_reset =>
v.state := init_cmd;
o_host.reset <= '1';
o_host.id <= '0';
o_host.csr_req_valid <= '0';
o_host.csr_req_bits_rw <= '0';
o_host.csr_req_bits_addr <= (others => '0');
o_host.csr_req_bits_data <= (others => '0');
o_host.csr_resp_ready <= '1';
when init_cmd =>
o_host.reset <= '0';
--! Select CSR write command
case r.cmdCnt is
when 0 =>
-- PLL divide. One Tile at once.
o_host.csr_req_valid <= '1';
o_host.csr_req_bits_rw <= '1';
o_host.csr_req_bits_addr <= X"03f";
o_host.csr_req_bits_data <= X"0000000000020005";
when 1 =>
-- Set CSR29.
o_host.csr_req_valid <= '1';
o_host.csr_req_bits_rw <= '1';
o_host.csr_req_bits_addr <= X"01d";
o_host.csr_req_bits_data <= X"0000000000000001";
when 2 =>
-- Clear CSR29.
o_host.csr_req_valid <= '1';
o_host.csr_req_bits_rw <= '1';
o_host.csr_req_bits_addr <= X"01d";
o_host.csr_req_bits_data <= X"0000000000000000";
when 3 =>
-- Write MRESET
o_host.csr_req_valid <= '1';
o_host.csr_req_bits_rw <= '1';
o_host.csr_req_bits_addr <= X"782";
o_host.csr_req_bits_data <= X"0000000000000000";
when others =>
v.state := disable;
end case;
if i_host.csr_req_ready = '0' then
v.state := wait_ready;
else
v.state := wait_resp;
end if;
when wait_ready =>
if i_host.csr_req_ready = '1' then
v.state := wait_resp;
o_host.csr_req_valid <= '0';
end if;
when wait_resp =>
if i_host.csr_resp_valid = '1' then
v.cmdCnt := r.cmdCnt + 1;
if r.cmdCnt = 3 then
v.state := disable;
v.init_ena := '0';
else
v.state := init_cmd;
end if;
end if;
when others =>
end case;
rin <= v;
end process;
o_init_ena <= r.init_ena;
-- registers:
regs : process(clk, nrst)
begin
if nrst = '0' then
r.state <= init_reset;
r.init_ena <= '1';
r.cmdCnt <= 0;
elsif rising_edge(clk) then
r <= rin;
end if;
end process;
end;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.arch_defs.all;
entity shiftLeftImm is
port (
imm: in std_logic_vector (31 downto 0);
output: out std_logic_vector (31 downto 0)
);
end entity;
architecture behav of shiftLeftImm is
begin
output <= std_logic_vector(shift_left(unsigned(imm), 2));
end architecture behav;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc431.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY model IS
PORT
(
F1: OUT integer := 3;
F2: INOUT integer := 3;
F3: IN integer
);
END model;
architecture model of model is
begin
process
begin
wait for 1 ns;
assert F3= 3
report"wrong initialization of F3 through type conversion" severity failure;
assert F2 = 3
report"wrong initialization of F2 through type conversion" severity failure;
wait;
end process;
end;
ENTITY c03s02b01x01p19n01i00431ent IS
END c03s02b01x01p19n01i00431ent;
ARCHITECTURE c03s02b01x01p19n01i00431arch OF c03s02b01x01p19n01i00431ent IS
type column is range 1 to 2;
type row is range 1 to 8;
type s2char_cons_vector is array (row,column) of character;
constant C1 : s2char_cons_vector := (others => (others => 's'));
function complex_scalar(s : s2char_cons_vector) return integer is
begin
return 3;
end complex_scalar;
function scalar_complex(s : integer) return s2char_cons_vector is
begin
return C1;
end scalar_complex;
component model1
PORT
(
F1: OUT integer;
F2: INOUT integer;
F3: IN integer
);
end component;
for T1 : model1 use entity work.model(model);
signal S1 : s2char_cons_vector;
signal S2 : s2char_cons_vector;
signal S3 : s2char_cons_vector := C1;
BEGIN
T1: model1
port map (
scalar_complex(F1) => S1,
scalar_complex(F2) => complex_scalar(S2),
F3 => complex_scalar(S3)
);
TESTING: PROCESS
BEGIN
wait for 1 ns;
assert NOT((S1 = C1) and (S2 = C1))
report "***PASSED TEST: c03s02b01x01p19n01i00431"
severity NOTE;
assert ((S1 = C1) and (S2 = C1))
report "***FAILED TEST: c03s02b01x01p19n01i00431 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x01p19n01i00431arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc431.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY model IS
PORT
(
F1: OUT integer := 3;
F2: INOUT integer := 3;
F3: IN integer
);
END model;
architecture model of model is
begin
process
begin
wait for 1 ns;
assert F3= 3
report"wrong initialization of F3 through type conversion" severity failure;
assert F2 = 3
report"wrong initialization of F2 through type conversion" severity failure;
wait;
end process;
end;
ENTITY c03s02b01x01p19n01i00431ent IS
END c03s02b01x01p19n01i00431ent;
ARCHITECTURE c03s02b01x01p19n01i00431arch OF c03s02b01x01p19n01i00431ent IS
type column is range 1 to 2;
type row is range 1 to 8;
type s2char_cons_vector is array (row,column) of character;
constant C1 : s2char_cons_vector := (others => (others => 's'));
function complex_scalar(s : s2char_cons_vector) return integer is
begin
return 3;
end complex_scalar;
function scalar_complex(s : integer) return s2char_cons_vector is
begin
return C1;
end scalar_complex;
component model1
PORT
(
F1: OUT integer;
F2: INOUT integer;
F3: IN integer
);
end component;
for T1 : model1 use entity work.model(model);
signal S1 : s2char_cons_vector;
signal S2 : s2char_cons_vector;
signal S3 : s2char_cons_vector := C1;
BEGIN
T1: model1
port map (
scalar_complex(F1) => S1,
scalar_complex(F2) => complex_scalar(S2),
F3 => complex_scalar(S3)
);
TESTING: PROCESS
BEGIN
wait for 1 ns;
assert NOT((S1 = C1) and (S2 = C1))
report "***PASSED TEST: c03s02b01x01p19n01i00431"
severity NOTE;
assert ((S1 = C1) and (S2 = C1))
report "***FAILED TEST: c03s02b01x01p19n01i00431 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x01p19n01i00431arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc431.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY model IS
PORT
(
F1: OUT integer := 3;
F2: INOUT integer := 3;
F3: IN integer
);
END model;
architecture model of model is
begin
process
begin
wait for 1 ns;
assert F3= 3
report"wrong initialization of F3 through type conversion" severity failure;
assert F2 = 3
report"wrong initialization of F2 through type conversion" severity failure;
wait;
end process;
end;
ENTITY c03s02b01x01p19n01i00431ent IS
END c03s02b01x01p19n01i00431ent;
ARCHITECTURE c03s02b01x01p19n01i00431arch OF c03s02b01x01p19n01i00431ent IS
type column is range 1 to 2;
type row is range 1 to 8;
type s2char_cons_vector is array (row,column) of character;
constant C1 : s2char_cons_vector := (others => (others => 's'));
function complex_scalar(s : s2char_cons_vector) return integer is
begin
return 3;
end complex_scalar;
function scalar_complex(s : integer) return s2char_cons_vector is
begin
return C1;
end scalar_complex;
component model1
PORT
(
F1: OUT integer;
F2: INOUT integer;
F3: IN integer
);
end component;
for T1 : model1 use entity work.model(model);
signal S1 : s2char_cons_vector;
signal S2 : s2char_cons_vector;
signal S3 : s2char_cons_vector := C1;
BEGIN
T1: model1
port map (
scalar_complex(F1) => S1,
scalar_complex(F2) => complex_scalar(S2),
F3 => complex_scalar(S3)
);
TESTING: PROCESS
BEGIN
wait for 1 ns;
assert NOT((S1 = C1) and (S2 = C1))
report "***PASSED TEST: c03s02b01x01p19n01i00431"
severity NOTE;
assert ((S1 = C1) and (S2 = C1))
report "***FAILED TEST: c03s02b01x01p19n01i00431 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x01p19n01i00431arch;
|
-------------------------------------------------------------------------------
-- (c) Copyright 2006 - 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------
--
-- Filename: blk_mem_gen_v8_3_0.vhd
--
-- Description:
-- This file is the VHDL behvarial model for the
-- Block Memory Generator Core.
--
-------------------------------------------------------------------------------
-- Author: Xilinx
--
-- History: January 11, 2006: Initial revision
-- June 11, 2007 : Added independent register stages for
-- Port A and Port B (IP1_Jm/v2.5)
-- August 28, 2007 : Added mux pipeline stages feature (IP2_Jm/v2.6)
-- April 07, 2009 : Added support for Spartan-6 and Virtex-6
-- features, including the following:
-- (i) error injection, detection and/or correction
-- (ii) reset priority
-- (iii) special reset behavior
--
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use ieee.numeric_std.all;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY STD;
USE STD.TEXTIO.ALL;
ENTITY blk_mem_axi_regs_fwd_v8_3 IS
GENERIC(
C_DATA_WIDTH : INTEGER := 8
);
PORT (
ACLK : IN STD_LOGIC;
ARESET : IN STD_LOGIC;
S_VALID : IN STD_LOGIC;
S_READY : OUT STD_LOGIC;
S_PAYLOAD_DATA : IN STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
M_VALID : OUT STD_LOGIC;
M_READY : IN STD_LOGIC;
M_PAYLOAD_DATA : OUT STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0)
);
END ENTITY blk_mem_axi_regs_fwd_v8_3;
ARCHITECTURE axi_regs_fwd_arch OF blk_mem_axi_regs_fwd_v8_3 IS
SIGNAL STORAGE_DATA : STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL S_READY_I : STD_LOGIC := '0';
SIGNAL M_VALID_I : STD_LOGIC := '0';
SIGNAL ARESET_D : STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');-- Reset delay register
BEGIN
--assign local signal to its output signal
S_READY <= S_READY_I;
M_VALID <= M_VALID_I;
PROCESS(ACLK)
BEGIN
IF(ACLK'event AND ACLK = '1') THEN
ARESET_D <= ARESET_D(0) & ARESET;
END IF;
END PROCESS;
--Save payload data whenever we have a transaction on the slave side
PROCESS(ACLK, ARESET)
BEGIN
IF (ARESET = '1') THEN
STORAGE_DATA <= (OTHERS => '0');
ELSIF(ACLK'event AND ACLK = '1') THEN
IF(S_VALID = '1' AND S_READY_I = '1') THEN
STORAGE_DATA <= S_PAYLOAD_DATA;
END IF;
END IF;
END PROCESS;
M_PAYLOAD_DATA <= STORAGE_DATA;
-- M_Valid set to high when we have a completed transfer on slave side
-- Is removed on a M_READY except if we have a new transfer on the slave side
PROCESS(ACLK,ARESET)
BEGIN
IF (ARESET_D /= "00") THEN
M_VALID_I <= '0';
ELSIF(ACLK'event AND ACLK = '1') THEN
IF (S_VALID = '1') THEN
--Always set M_VALID_I when slave side is valid
M_VALID_I <= '1';
ELSIF (M_READY = '1') THEN
--Clear (or keep) when no slave side is valid but master side is ready
M_VALID_I <= '0';
END IF;
END IF;
END PROCESS;
--Slave Ready is either when Master side drives M_READY or we have space in our storage data
S_READY_I <= (M_READY OR (NOT M_VALID_I)) AND NOT(OR_REDUCE(ARESET_D));
END axi_regs_fwd_arch;
-------------------------------------------------------------------------------
-- Description:
-- This is the behavioral model of write_wrapper for the
-- Block Memory Generator Core.
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY blk_mem_axi_write_wrapper_beh IS
GENERIC (
-- AXI Interface related parameters start here
C_INTERFACE_TYPE : integer := 0; -- 0: Native Interface; 1: AXI Interface
C_AXI_TYPE : integer := 0; -- 0: AXI Lite; 1: AXI Full;
C_AXI_SLAVE_TYPE : integer := 0; -- 0: MEMORY SLAVE; 1: PERIPHERAL SLAVE;
C_MEMORY_TYPE : integer := 0; -- 0: SP-RAM, 1: SDP-RAM; 2: TDP-RAM; 3: DP-ROM;
C_WRITE_DEPTH_A : integer := 0;
C_AXI_AWADDR_WIDTH : integer := 32;
C_ADDRA_WIDTH : integer := 12;
C_AXI_WDATA_WIDTH : integer := 32;
C_HAS_AXI_ID : integer := 0;
C_AXI_ID_WIDTH : integer := 4;
-- AXI OUTSTANDING WRITES
C_AXI_OS_WR : integer := 2
);
PORT (
-- AXI Global Signals
S_ACLK : IN std_logic;
S_ARESETN : IN std_logic;
-- AXI Full/Lite Slave Write Channel (write side)
S_AXI_AWID : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWADDR : IN std_logic_vector(C_AXI_AWADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWLEN : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWVALID : IN std_logic := '0';
S_AXI_AWREADY : OUT std_logic := '0';
S_AXI_WVALID : IN std_logic := '0';
S_AXI_WREADY : OUT std_logic := '0';
S_AXI_BID : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_BVALID : OUT std_logic := '0';
S_AXI_BREADY : IN std_logic := '0';
-- Signals for BMG interface
S_AXI_AWADDR_OUT : OUT std_logic_vector(C_ADDRA_WIDTH-1 DOWNTO 0);
S_AXI_WR_EN : OUT std_logic:= '0'
);
END blk_mem_axi_write_wrapper_beh;
ARCHITECTURE axi_write_wrap_arch OF blk_mem_axi_write_wrapper_beh IS
------------------------------------------------------------------------------
-- FUNCTION: if_then_else
-- This function is used to implement an IF..THEN when such a statement is not
-- allowed.
------------------------------------------------------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
VARIABLE retval : INTEGER := 0;
BEGIN
IF NOT condition THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC_VECTOR;
false_case : STD_LOGIC_VECTOR)
RETURN STD_LOGIC_VECTOR IS
BEGIN
IF NOT condition THEN
RETURN false_case;
ELSE
RETURN true_case;
END IF;
END if_then_else;
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STRING;
false_case : STRING)
RETURN STRING IS
BEGIN
IF NOT condition THEN
RETURN false_case;
ELSE
RETURN true_case;
END IF;
END if_then_else;
CONSTANT FLOP_DELAY : TIME := 100 PS;
CONSTANT ONE : std_logic_vector(7 DOWNTO 0) := ("00000001");
CONSTANT C_RANGE : INTEGER := if_then_else(C_AXI_WDATA_WIDTH=8,0,
if_then_else((C_AXI_WDATA_WIDTH=16),1,
if_then_else((C_AXI_WDATA_WIDTH=32),2,
if_then_else((C_AXI_WDATA_WIDTH=64),3,
if_then_else((C_AXI_WDATA_WIDTH=128),4,
if_then_else((C_AXI_WDATA_WIDTH=256),5,0))))));
SIGNAL bvalid_c : std_logic := '0';
SIGNAL bready_timeout_c : std_logic := '0';
SIGNAL bvalid_rd_cnt_c : std_logic_vector(1 DOWNTO 0) := (OTHERS => '0');
SIGNAL bvalid_r : std_logic := '0';
SIGNAL bvalid_count_r : std_logic_vector(2 DOWNTO 0) := (OTHERS => '0');
SIGNAL awaddr_reg : std_logic_vector(if_then_else((C_AXI_TYPE = 1 AND C_AXI_SLAVE_TYPE = 0),
C_AXI_AWADDR_WIDTH,C_ADDRA_WIDTH)-1 DOWNTO 0);
SIGNAL bvalid_wr_cnt_r : std_logic_vector(1 DOWNTO 0) := (OTHERS => '0');
SIGNAL bvalid_rd_cnt_r : std_logic_vector(1 DOWNTO 0) := (OTHERS => '0');
SIGNAL w_last_c : std_logic := '0';
SIGNAL addr_en_c : std_logic := '0';
SIGNAL incr_addr_c : std_logic := '0';
SIGNAL aw_ready_r : std_logic := '0';
SIGNAL dec_alen_c : std_logic := '0';
SIGNAL awlen_cntr_r : std_logic_vector(7 DOWNTO 0) := (OTHERS => '1');
SIGNAL awlen_int : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL awburst_int : std_logic_vector(1 DOWNTO 0) := (OTHERS => '0');
SIGNAL total_bytes : integer := 0;
SIGNAL wrap_boundary : integer := 0;
SIGNAL wrap_base_addr : integer := 0;
SIGNAL num_of_bytes_c : integer := 0;
SIGNAL num_of_bytes_r : integer := 0;
-- Array to store BIDs
TYPE id_array IS ARRAY (3 DOWNTO 0) OF std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
SIGNAL axi_bid_array : id_array := (others => (others => '0'));
COMPONENT write_netlist
GENERIC(
C_AXI_TYPE : integer
);
PORT(
S_ACLK : IN std_logic;
S_ARESETN : IN std_logic;
S_AXI_AWVALID : IN std_logic;
aw_ready_r : OUT std_logic;
S_AXI_WVALID : IN std_logic;
S_AXI_WREADY : OUT std_logic;
S_AXI_BVALID : OUT STD_LOGIC;
S_AXI_BREADY : IN std_logic;
S_AXI_WR_EN : OUT std_logic;
w_last_c : IN std_logic;
bready_timeout_c : IN std_logic;
addr_en_c : OUT std_logic;
incr_addr_c : OUT std_logic;
bvalid_c : OUT std_logic
);
END COMPONENT write_netlist;
BEGIN
---------------------------------------
--AXI WRITE FSM COMPONENT INSTANTIATION
---------------------------------------
axi_wr_fsm : write_netlist
GENERIC MAP (
C_AXI_TYPE => C_AXI_TYPE
)
PORT MAP (
S_ACLK => S_ACLK,
S_ARESETN => S_ARESETN,
S_AXI_AWVALID => S_AXI_AWVALID,
aw_ready_r => aw_ready_r,
S_AXI_WVALID => S_AXI_WVALID,
S_AXI_BVALID => OPEN,
S_AXI_WREADY => S_AXI_WREADY,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_WR_EN => S_AXI_WR_EN,
w_last_c => w_last_c,
bready_timeout_c => bready_timeout_c,
addr_en_c => addr_en_c,
incr_addr_c => incr_addr_c,
bvalid_c => bvalid_c
);
--Wrap Address boundary calculation
num_of_bytes_c <= 2**conv_integer(if_then_else((C_AXI_TYPE = 1 AND C_AXI_SLAVE_TYPE = 0),S_AXI_AWSIZE,"000"));
total_bytes <= conv_integer(num_of_bytes_r)*(conv_integer(awlen_int)+1);
wrap_base_addr <= (conv_integer(awaddr_reg)/if_then_else(total_bytes=0,1,total_bytes))*(total_bytes);
wrap_boundary <= wrap_base_addr+total_bytes;
---------------------------------------------------------------------------
-- BMG address generation
---------------------------------------------------------------------------
P_addr_reg: PROCESS (S_ACLK,S_ARESETN)
BEGIN
IF (S_ARESETN = '1') THEN
awaddr_reg <= (OTHERS => '0');
num_of_bytes_r <= 0;
awburst_int <= (OTHERS => '0');
ELSIF (S_ACLK'event AND S_ACLK = '1') THEN
IF (addr_en_c = '1') THEN
awaddr_reg <= S_AXI_AWADDR AFTER FLOP_DELAY;
num_of_bytes_r <= num_of_bytes_c;
awburst_int <= if_then_else((C_AXI_TYPE = 1 AND C_AXI_SLAVE_TYPE = 0),S_AXI_AWBURST,"01");
ELSIF (incr_addr_c = '1') THEN
IF (awburst_int = "10") THEN
IF(conv_integer(awaddr_reg) = (wrap_boundary-num_of_bytes_r)) THEN
awaddr_reg <= conv_std_logic_vector(wrap_base_addr,C_AXI_AWADDR_WIDTH);
ELSE
awaddr_reg <= awaddr_reg + num_of_bytes_r;
END IF;
ELSIF (awburst_int = "01" OR awburst_int = "11") THEN
awaddr_reg <= awaddr_reg + num_of_bytes_r;
END IF;
END IF;
END IF;
END PROCESS P_addr_reg;
S_AXI_AWADDR_OUT <= if_then_else((C_AXI_TYPE = 1 AND C_AXI_SLAVE_TYPE = 0),
awaddr_reg(C_AXI_AWADDR_WIDTH-1 DOWNTO C_RANGE),awaddr_reg);
---------------------------------------------------------------------------
-- AXI wlast generation
---------------------------------------------------------------------------
P_addr_cnt: PROCESS (S_ACLK, S_ARESETN)
BEGIN
IF (S_ARESETN = '1') THEN
awlen_cntr_r <= (OTHERS => '1');
awlen_int <= (OTHERS => '0');
ELSIF (S_ACLK'event AND S_ACLK = '1') THEN
IF (addr_en_c = '1') THEN
awlen_int <= if_then_else(C_AXI_TYPE = 0,"00000000",S_AXI_AWLEN) AFTER FLOP_DELAY;
awlen_cntr_r <= if_then_else(C_AXI_TYPE = 0,"00000000",S_AXI_AWLEN) AFTER FLOP_DELAY;
ELSIF (dec_alen_c = '1') THEN
awlen_cntr_r <= awlen_cntr_r - ONE AFTER FLOP_DELAY;
END IF;
END IF;
END PROCESS P_addr_cnt;
w_last_c <= '1' WHEN (awlen_cntr_r = "00000000" AND S_AXI_WVALID = '1') ELSE '0';
dec_alen_c <= (incr_addr_c OR w_last_c);
---------------------------------------------------------------------------
-- Generation of bvalid counter for outstanding transactions
---------------------------------------------------------------------------
P_b_valid_os_r: PROCESS (S_ACLK, S_ARESETN)
BEGIN
IF (S_ARESETN = '1') THEN
bvalid_count_r <= (OTHERS => '0');
ELSIF (S_ACLK'event AND S_ACLK='1') THEN
-- bvalid_count_r generation
IF (bvalid_c = '1' AND bvalid_r = '1' AND S_AXI_BREADY = '1') THEN
bvalid_count_r <= bvalid_count_r AFTER FLOP_DELAY;
ELSIF (bvalid_c = '1') THEN
bvalid_count_r <= bvalid_count_r + "01" AFTER FLOP_DELAY;
ELSIF (bvalid_r = '1' AND S_AXI_BREADY = '1' AND bvalid_count_r /= "0") THEN
bvalid_count_r <= bvalid_count_r - "01" AFTER FLOP_DELAY;
END IF;
END IF;
END PROCESS P_b_valid_os_r ;
---------------------------------------------------------------------------
-- Generation of bvalid when BID is used
---------------------------------------------------------------------------
gaxi_bvalid_id_r:IF (C_HAS_AXI_ID = 1) GENERATE
SIGNAL bvalid_d1_c : std_logic := '0';
BEGIN
P_b_valid_r: PROCESS (S_ACLK, S_ARESETN)
BEGIN
IF (S_ARESETN = '1') THEN
bvalid_r <= '0';
bvalid_d1_c <= '0';
ELSIF (S_ACLK'event AND S_ACLK='1') THEN
-- Delay the generation o bvalid_r for generation for BID
bvalid_d1_c <= bvalid_c;
--external bvalid signal generation
IF (bvalid_d1_c = '1') THEN
bvalid_r <= '1' AFTER FLOP_DELAY;
ELSIF (conv_integer(bvalid_count_r) <= 1 AND S_AXI_BREADY = '1') THEN
bvalid_r <= '0' AFTER FLOP_DELAY;
END IF;
END IF;
END PROCESS P_b_valid_r ;
END GENERATE gaxi_bvalid_id_r;
---------------------------------------------------------------------------
-- Generation of bvalid when BID is not used
---------------------------------------------------------------------------
gaxi_bvalid_noid_r:IF (C_HAS_AXI_ID = 0) GENERATE
P_b_valid_r: PROCESS (S_ACLK, S_ARESETN)
BEGIN
IF (S_ARESETN = '1') THEN
bvalid_r <= '0';
ELSIF (S_ACLK'event AND S_ACLK='1') THEN
--external bvalid signal generation
IF (bvalid_c = '1') THEN
bvalid_r <= '1' AFTER FLOP_DELAY;
ELSIF (conv_integer(bvalid_count_r) <= 1 AND S_AXI_BREADY = '1') THEN
bvalid_r <= '0' AFTER FLOP_DELAY;
END IF;
END IF;
END PROCESS P_b_valid_r ;
END GENERATE gaxi_bvalid_noid_r;
---------------------------------------------------------------------------
-- Generation of Bready timeout
---------------------------------------------------------------------------
P_brdy_tout_c: PROCESS (bvalid_count_r)
BEGIN
-- bready_timeout_c generation
IF(conv_integer(bvalid_count_r) = C_AXI_OS_WR-1) THEN
bready_timeout_c <= '1';
ELSE
bready_timeout_c <= '0';
END IF;
END PROCESS P_brdy_tout_c;
---------------------------------------------------------------------------
-- Generation of BID
---------------------------------------------------------------------------
gaxi_bid_gen:IF (C_HAS_AXI_ID = 1) GENERATE
P_bid_gen: PROCESS (S_ACLK,S_ARESETN)
BEGIN
IF (S_ARESETN='1') THEN
bvalid_wr_cnt_r <= (OTHERS => '0');
bvalid_rd_cnt_r <= (OTHERS => '0');
ELSIF (S_ACLK'event AND S_ACLK='1') THEN
-- STORE AWID IN AN ARRAY
IF(bvalid_c = '1') THEN
bvalid_wr_cnt_r <= bvalid_wr_cnt_r + "01";
END IF;
-- GENERATE BID FROM AWID ARRAY
bvalid_rd_cnt_r <= bvalid_rd_cnt_c AFTER FLOP_DELAY;
S_AXI_BID <= axi_bid_array(conv_integer(bvalid_rd_cnt_c));
END IF;
END PROCESS P_bid_gen;
bvalid_rd_cnt_c <= bvalid_rd_cnt_r + "01" WHEN (bvalid_r = '1' AND S_AXI_BREADY = '1') ELSE bvalid_rd_cnt_r;
---------------------------------------------------------------------------
-- Storing AWID for generation of BID
---------------------------------------------------------------------------
P_awid_reg:PROCESS (S_ACLK)
BEGIN
IF (S_ACLK'event AND S_ACLK='1') THEN
IF(aw_ready_r = '1' AND S_AXI_AWVALID = '1') THEN
axi_bid_array(conv_integer(bvalid_wr_cnt_r)) <= S_AXI_AWID;
END IF;
END IF;
END PROCESS P_awid_reg;
END GENERATE gaxi_bid_gen;
S_AXI_BVALID <= bvalid_r;
S_AXI_AWREADY <= aw_ready_r;
END axi_write_wrap_arch;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
entity write_netlist is
GENERIC(
C_AXI_TYPE : integer
);
port (
S_ACLK : in STD_LOGIC := '0';
S_ARESETN : in STD_LOGIC := '0';
S_AXI_AWVALID : in STD_LOGIC := '0';
S_AXI_WVALID : in STD_LOGIC := '0';
S_AXI_BREADY : in STD_LOGIC := '0';
w_last_c : in STD_LOGIC := '0';
bready_timeout_c : in STD_LOGIC := '0';
aw_ready_r : out STD_LOGIC;
S_AXI_WREADY : out STD_LOGIC;
S_AXI_BVALID : out STD_LOGIC;
S_AXI_WR_EN : out STD_LOGIC;
addr_en_c : out STD_LOGIC;
incr_addr_c : out STD_LOGIC;
bvalid_c : out STD_LOGIC
);
end write_netlist;
architecture STRUCTURE of write_netlist is
component beh_muxf7
port(
O : out std_ulogic;
I0 : in std_ulogic;
I1 : in std_ulogic;
S : in std_ulogic
);
end component;
COMPONENT beh_ff_pre
generic(
INIT : std_logic := '1'
);
port(
Q : out std_logic;
C : in std_logic;
D : in std_logic;
PRE : in std_logic
);
end COMPONENT beh_ff_pre;
COMPONENT beh_ff_ce
generic(
INIT : std_logic := '0'
);
port(
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
CLR : in std_logic;
D : in std_logic
);
end COMPONENT beh_ff_ce;
COMPONENT beh_ff_clr
generic(
INIT : std_logic := '0'
);
port(
Q : out std_logic;
C : in std_logic;
CLR : in std_logic;
D : in std_logic
);
end COMPONENT beh_ff_clr;
COMPONENT STATE_LOGIC
generic(
INIT : std_logic_vector(63 downto 0) := X"0000000000000000"
);
port(
O : out std_logic;
I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic;
I3 : in std_logic;
I4 : in std_logic;
I5 : in std_logic
);
end COMPONENT STATE_LOGIC;
BEGIN
---------------------------------------------------------------------------
-- AXI LITE
---------------------------------------------------------------------------
gbeh_axi_lite_sm: IF (C_AXI_TYPE = 0 ) GENERATE
signal w_ready_r_7 : STD_LOGIC;
signal w_ready_c : STD_LOGIC;
signal aw_ready_c : STD_LOGIC;
signal NlwRenamedSignal_bvalid_c : STD_LOGIC;
signal NlwRenamedSignal_incr_addr_c : STD_LOGIC;
signal present_state_FSM_FFd3_13 : STD_LOGIC;
signal present_state_FSM_FFd2_14 : STD_LOGIC;
signal present_state_FSM_FFd1_15 : STD_LOGIC;
signal present_state_FSM_FFd4_16 : STD_LOGIC;
signal present_state_FSM_FFd4_In : STD_LOGIC;
signal present_state_FSM_FFd3_In : STD_LOGIC;
signal present_state_FSM_FFd2_In : STD_LOGIC;
signal present_state_FSM_FFd1_In : STD_LOGIC;
signal present_state_FSM_FFd4_In1_21 : STD_LOGIC;
signal Mmux_aw_ready_c : STD_LOGIC_VECTOR ( 0 downto 0 );
begin
S_AXI_WREADY <= w_ready_r_7;
S_AXI_BVALID <= NlwRenamedSignal_incr_addr_c;
S_AXI_WR_EN <= NlwRenamedSignal_bvalid_c;
incr_addr_c <= NlwRenamedSignal_incr_addr_c;
bvalid_c <= NlwRenamedSignal_bvalid_c;
NlwRenamedSignal_incr_addr_c <= '0';
aw_ready_r_2 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => aw_ready_c,
Q => aw_ready_r
);
w_ready_r : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => w_ready_c,
Q => w_ready_r_7
);
present_state_FSM_FFd4 : beh_ff_pre
generic map(
INIT => '1'
)
port map (
C => S_ACLK,
D => present_state_FSM_FFd4_In,
PRE => S_ARESETN,
Q => present_state_FSM_FFd4_16
);
present_state_FSM_FFd3 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => present_state_FSM_FFd3_In,
Q => present_state_FSM_FFd3_13
);
present_state_FSM_FFd2 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => present_state_FSM_FFd2_In,
Q => present_state_FSM_FFd2_14
);
present_state_FSM_FFd1 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => present_state_FSM_FFd1_In,
Q => present_state_FSM_FFd1_15
);
present_state_FSM_FFd3_In1 : STATE_LOGIC
generic map(
INIT => X"0000000055554440"
)
port map (
I0 => S_AXI_WVALID,
I1 => S_AXI_AWVALID,
I2 => present_state_FSM_FFd2_14,
I3 => present_state_FSM_FFd4_16,
I4 => present_state_FSM_FFd3_13,
I5 => '0',
O => present_state_FSM_FFd3_In
);
present_state_FSM_FFd2_In1 : STATE_LOGIC
generic map(
INIT => X"0000000088880800"
)
port map (
I0 => S_AXI_AWVALID,
I1 => S_AXI_WVALID,
I2 => bready_timeout_c,
I3 => present_state_FSM_FFd2_14,
I4 => present_state_FSM_FFd4_16,
I5 => '0',
O => present_state_FSM_FFd2_In
);
Mmux_addr_en_c_0_1 : STATE_LOGIC
generic map(
INIT => X"00000000AAAA2000"
)
port map (
I0 => S_AXI_AWVALID,
I1 => bready_timeout_c,
I2 => present_state_FSM_FFd2_14,
I3 => S_AXI_WVALID,
I4 => present_state_FSM_FFd4_16,
I5 => '0',
O => addr_en_c
);
Mmux_w_ready_c_0_1 : STATE_LOGIC
generic map(
INIT => X"F5F07570F5F05500"
)
port map (
I0 => S_AXI_WVALID,
I1 => bready_timeout_c,
I2 => S_AXI_AWVALID,
I3 => present_state_FSM_FFd3_13,
I4 => present_state_FSM_FFd4_16,
I5 => present_state_FSM_FFd2_14,
O => w_ready_c
);
present_state_FSM_FFd1_In1 : STATE_LOGIC
generic map(
INIT => X"88808880FFFF8880"
)
port map (
I0 => S_AXI_WVALID,
I1 => bready_timeout_c,
I2 => present_state_FSM_FFd3_13,
I3 => present_state_FSM_FFd2_14,
I4 => present_state_FSM_FFd1_15,
I5 => S_AXI_BREADY,
O => present_state_FSM_FFd1_In
);
Mmux_S_AXI_WR_EN_0_1 : STATE_LOGIC
generic map(
INIT => X"00000000000000A8"
)
port map (
I0 => S_AXI_WVALID,
I1 => present_state_FSM_FFd2_14,
I2 => present_state_FSM_FFd3_13,
I3 => '0',
I4 => '0',
I5 => '0',
O => NlwRenamedSignal_bvalid_c
);
present_state_FSM_FFd4_In1 : STATE_LOGIC
generic map(
INIT => X"2F0F27072F0F2200"
)
port map (
I0 => S_AXI_WVALID,
I1 => bready_timeout_c,
I2 => S_AXI_AWVALID,
I3 => present_state_FSM_FFd3_13,
I4 => present_state_FSM_FFd4_16,
I5 => present_state_FSM_FFd2_14,
O => present_state_FSM_FFd4_In1_21
);
present_state_FSM_FFd4_In2 : STATE_LOGIC
generic map(
INIT => X"00000000000000F8"
)
port map (
I0 => present_state_FSM_FFd1_15,
I1 => S_AXI_BREADY,
I2 => present_state_FSM_FFd4_In1_21,
I3 => '0',
I4 => '0',
I5 => '0',
O => present_state_FSM_FFd4_In
);
Mmux_aw_ready_c_0_1 : STATE_LOGIC
generic map(
INIT => X"7535753575305500"
)
port map (
I0 => S_AXI_AWVALID,
I1 => bready_timeout_c,
I2 => S_AXI_WVALID,
I3 => present_state_FSM_FFd4_16,
I4 => present_state_FSM_FFd3_13,
I5 => present_state_FSM_FFd2_14,
O => Mmux_aw_ready_c(0)
);
Mmux_aw_ready_c_0_2 : STATE_LOGIC
generic map(
INIT => X"00000000000000F8"
)
port map (
I0 => present_state_FSM_FFd1_15,
I1 => S_AXI_BREADY,
I2 => Mmux_aw_ready_c(0),
I3 => '0',
I4 => '0',
I5 => '0',
O => aw_ready_c
);
END GENERATE gbeh_axi_lite_sm;
---------------------------------------------------------------------------
-- AXI FULL
---------------------------------------------------------------------------
gbeh_axi_full_sm: IF (C_AXI_TYPE = 1 ) GENERATE
signal w_ready_r_8 : STD_LOGIC;
signal w_ready_c : STD_LOGIC;
signal aw_ready_c : STD_LOGIC;
signal NlwRenamedSig_OI_bvalid_c : STD_LOGIC;
signal present_state_FSM_FFd1_16 : STD_LOGIC;
signal present_state_FSM_FFd4_17 : STD_LOGIC;
signal present_state_FSM_FFd3_18 : STD_LOGIC;
signal present_state_FSM_FFd2_19 : STD_LOGIC;
signal present_state_FSM_FFd4_In : STD_LOGIC;
signal present_state_FSM_FFd3_In : STD_LOGIC;
signal present_state_FSM_FFd2_In : STD_LOGIC;
signal present_state_FSM_FFd1_In : STD_LOGIC;
signal present_state_FSM_FFd2_In1_24 : STD_LOGIC;
signal present_state_FSM_FFd4_In1_25 : STD_LOGIC;
signal N2 : STD_LOGIC;
signal N4 : STD_LOGIC;
begin
S_AXI_WREADY <= w_ready_r_8;
bvalid_c <= NlwRenamedSig_OI_bvalid_c;
S_AXI_BVALID <= '0';
aw_ready_r_2 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => aw_ready_c,
Q => aw_ready_r
);
w_ready_r : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => w_ready_c,
Q => w_ready_r_8
);
present_state_FSM_FFd4 : beh_ff_pre
generic map(
INIT => '1'
)
port map (
C => S_ACLK,
D => present_state_FSM_FFd4_In,
PRE => S_ARESETN,
Q => present_state_FSM_FFd4_17
);
present_state_FSM_FFd3 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => present_state_FSM_FFd3_In,
Q => present_state_FSM_FFd3_18
);
present_state_FSM_FFd2 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => present_state_FSM_FFd2_In,
Q => present_state_FSM_FFd2_19
);
present_state_FSM_FFd1 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => present_state_FSM_FFd1_In,
Q => present_state_FSM_FFd1_16
);
present_state_FSM_FFd3_In1 : STATE_LOGIC
generic map(
INIT => X"0000000000005540"
)
port map (
I0 => S_AXI_WVALID,
I1 => present_state_FSM_FFd4_17,
I2 => S_AXI_AWVALID,
I3 => present_state_FSM_FFd3_18,
I4 => '0',
I5 => '0',
O => present_state_FSM_FFd3_In
);
Mmux_aw_ready_c_0_2 : STATE_LOGIC
generic map(
INIT => X"BF3FBB33AF0FAA00"
)
port map (
I0 => S_AXI_BREADY,
I1 => bready_timeout_c,
I2 => S_AXI_AWVALID,
I3 => present_state_FSM_FFd1_16,
I4 => present_state_FSM_FFd4_17,
I5 => NlwRenamedSig_OI_bvalid_c,
O => aw_ready_c
);
Mmux_addr_en_c_0_1 : STATE_LOGIC
generic map(
INIT => X"AAAAAAAA20000000"
)
port map (
I0 => S_AXI_AWVALID,
I1 => bready_timeout_c,
I2 => present_state_FSM_FFd2_19,
I3 => S_AXI_WVALID,
I4 => w_last_c,
I5 => present_state_FSM_FFd4_17,
O => addr_en_c
);
Mmux_S_AXI_WR_EN_0_1 : STATE_LOGIC
generic map(
INIT => X"00000000000000A8"
)
port map (
I0 => S_AXI_WVALID,
I1 => present_state_FSM_FFd2_19,
I2 => present_state_FSM_FFd3_18,
I3 => '0',
I4 => '0',
I5 => '0',
O => S_AXI_WR_EN
);
Mmux_incr_addr_c_0_1 : STATE_LOGIC
generic map(
INIT => X"0000000000002220"
)
port map (
I0 => S_AXI_WVALID,
I1 => w_last_c,
I2 => present_state_FSM_FFd2_19,
I3 => present_state_FSM_FFd3_18,
I4 => '0',
I5 => '0',
O => incr_addr_c
);
Mmux_aw_ready_c_0_11 : STATE_LOGIC
generic map(
INIT => X"0000000000008880"
)
port map (
I0 => S_AXI_WVALID,
I1 => w_last_c,
I2 => present_state_FSM_FFd2_19,
I3 => present_state_FSM_FFd3_18,
I4 => '0',
I5 => '0',
O => NlwRenamedSig_OI_bvalid_c
);
present_state_FSM_FFd2_In1 : STATE_LOGIC
generic map(
INIT => X"000000000000D5C0"
)
port map (
I0 => w_last_c,
I1 => S_AXI_AWVALID,
I2 => present_state_FSM_FFd4_17,
I3 => present_state_FSM_FFd3_18,
I4 => '0',
I5 => '0',
O => present_state_FSM_FFd2_In1_24
);
present_state_FSM_FFd2_In2 : STATE_LOGIC
generic map(
INIT => X"FFFFAAAA08AAAAAA"
)
port map (
I0 => present_state_FSM_FFd2_19,
I1 => S_AXI_AWVALID,
I2 => bready_timeout_c,
I3 => w_last_c,
I4 => S_AXI_WVALID,
I5 => present_state_FSM_FFd2_In1_24,
O => present_state_FSM_FFd2_In
);
present_state_FSM_FFd4_In1 : STATE_LOGIC
generic map(
INIT => X"00C0004000C00000"
)
port map (
I0 => S_AXI_AWVALID,
I1 => w_last_c,
I2 => S_AXI_WVALID,
I3 => bready_timeout_c,
I4 => present_state_FSM_FFd3_18,
I5 => present_state_FSM_FFd2_19,
O => present_state_FSM_FFd4_In1_25
);
present_state_FSM_FFd4_In2 : STATE_LOGIC
generic map(
INIT => X"00000000FFFF88F8"
)
port map (
I0 => present_state_FSM_FFd1_16,
I1 => S_AXI_BREADY,
I2 => present_state_FSM_FFd4_17,
I3 => S_AXI_AWVALID,
I4 => present_state_FSM_FFd4_In1_25,
I5 => '0',
O => present_state_FSM_FFd4_In
);
Mmux_w_ready_c_0_SW0 : STATE_LOGIC
generic map(
INIT => X"0000000000000007"
)
port map (
I0 => w_last_c,
I1 => S_AXI_WVALID,
I2 => '0',
I3 => '0',
I4 => '0',
I5 => '0',
O => N2
);
Mmux_w_ready_c_0_Q : STATE_LOGIC
generic map(
INIT => X"FABAFABAFAAAF000"
)
port map (
I0 => N2,
I1 => bready_timeout_c,
I2 => S_AXI_AWVALID,
I3 => present_state_FSM_FFd4_17,
I4 => present_state_FSM_FFd3_18,
I5 => present_state_FSM_FFd2_19,
O => w_ready_c
);
Mmux_aw_ready_c_0_11_SW0 : STATE_LOGIC
generic map(
INIT => X"0000000000000008"
)
port map (
I0 => bready_timeout_c,
I1 => S_AXI_WVALID,
I2 => '0',
I3 => '0',
I4 => '0',
I5 => '0',
O => N4
);
present_state_FSM_FFd1_In1 : STATE_LOGIC
generic map(
INIT => X"88808880FFFF8880"
)
port map (
I0 => w_last_c,
I1 => N4,
I2 => present_state_FSM_FFd2_19,
I3 => present_state_FSM_FFd3_18,
I4 => present_state_FSM_FFd1_16,
I5 => S_AXI_BREADY,
O => present_state_FSM_FFd1_In
);
END GENERATE gbeh_axi_full_sm;
end STRUCTURE;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
--AXI Behavioral Model entities
ENTITY blk_mem_axi_read_wrapper_beh is
GENERIC (
-- AXI Interface related parameters start here
C_INTERFACE_TYPE : integer := 0;
C_AXI_TYPE : integer := 0;
C_AXI_SLAVE_TYPE : integer := 0;
C_MEMORY_TYPE : integer := 0;
C_WRITE_WIDTH_A : integer := 4;
C_WRITE_DEPTH_A : integer := 32;
C_ADDRA_WIDTH : integer := 12;
C_AXI_PIPELINE_STAGES : integer := 0;
C_AXI_ARADDR_WIDTH : integer := 12;
C_HAS_AXI_ID : integer := 0;
C_AXI_ID_WIDTH : integer := 4;
C_ADDRB_WIDTH : integer := 12
);
port (
-- AXI Global Signals
S_ACLK : IN std_logic;
S_ARESETN : IN std_logic;
-- AXI Full/Lite Slave Read (Read side)
S_AXI_ARADDR : IN std_logic_vector(C_AXI_ARADDR_WIDTH-1 downto 0) := (OTHERS => '0');
S_AXI_ARLEN : IN std_logic_vector(7 downto 0) := (OTHERS => '0');
S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARVALID : IN std_logic := '0';
S_AXI_ARREADY : OUT std_logic;
S_AXI_RLAST : OUT std_logic;
S_AXI_RVALID : OUT std_logic;
S_AXI_RREADY : IN std_logic := '0';
S_AXI_ARID : IN std_logic_vector(C_AXI_ID_WIDTH-1 downto 0) := (OTHERS => '0');
S_AXI_RID : OUT std_logic_vector(C_AXI_ID_WIDTH-1 downto 0) := (OTHERS => '0');
-- AXI Full/Lite Read Address Signals to BRAM
S_AXI_ARADDR_OUT : OUT std_logic_vector(C_ADDRB_WIDTH-1 downto 0);
S_AXI_RD_EN : OUT std_logic
);
END blk_mem_axi_read_wrapper_beh;
architecture blk_mem_axi_read_wrapper_beh_arch of blk_mem_axi_read_wrapper_beh is
------------------------------------------------------------------------------
-- FUNCTION: if_then_else
-- This function is used to implement an IF..THEN when such a statement is not
-- allowed.
------------------------------------------------------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STRING;
false_case : STRING)
RETURN STRING IS
BEGIN
IF NOT condition THEN
RETURN false_case;
ELSE
RETURN true_case;
END IF;
END if_then_else;
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
VARIABLE retval : INTEGER := 0;
BEGIN
IF NOT condition THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC_VECTOR;
false_case : STD_LOGIC_VECTOR)
RETURN STD_LOGIC_VECTOR IS
BEGIN
IF NOT condition THEN
RETURN false_case;
ELSE
RETURN true_case;
END IF;
END if_then_else;
CONSTANT FLOP_DELAY : TIME := 100 PS;
CONSTANT ONE : std_logic_vector(7 DOWNTO 0) := ("00000001");
CONSTANT C_RANGE : INTEGER := if_then_else(C_WRITE_WIDTH_A=8,0,
if_then_else((C_WRITE_WIDTH_A=16),1,
if_then_else((C_WRITE_WIDTH_A=32),2,
if_then_else((C_WRITE_WIDTH_A=64),3,
if_then_else((C_WRITE_WIDTH_A=128),4,
if_then_else((C_WRITE_WIDTH_A=256),5,0))))));
SIGNAL ar_id_r : std_logic_vector (C_AXI_ID_WIDTH-1 downto 0) := (OTHERS => '0');
SIGNAL addr_en_c : std_logic := '0';
SIGNAL rd_en_c : std_logic := '0';
SIGNAL incr_addr_c : std_logic := '0';
SIGNAL single_trans_c : std_logic := '0';
SIGNAL dec_alen_c : std_logic := '0';
SIGNAL mux_sel_c : std_logic := '0';
SIGNAL r_last_c : std_logic := '0';
SIGNAL r_last_int_c : std_logic := '0';
SIGNAL arlen_int_r : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL arlen_cntr : std_logic_vector(7 DOWNTO 0) := ONE;
SIGNAL arburst_int_c : std_logic_vector(1 DOWNTO 0) := (OTHERS => '0');
SIGNAL arburst_int_r : std_logic_vector(1 DOWNTO 0) := (OTHERS => '0');
SIGNAL araddr_reg : std_logic_vector(if_then_else((C_AXI_TYPE = 1 AND C_AXI_SLAVE_TYPE = 0),C_AXI_ARADDR_WIDTH,C_ADDRA_WIDTH)-1 DOWNTO 0);
SIGNAL num_of_bytes_c : integer := 0;
SIGNAL total_bytes : integer := 0;
SIGNAL num_of_bytes_r : integer := 0;
SIGNAL wrap_base_addr_r : integer := 0;
SIGNAL wrap_boundary_r : integer := 0;
SIGNAL arlen_int_c : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL total_bytes_c : integer := 0;
SIGNAL wrap_base_addr_c : integer := 0;
SIGNAL wrap_boundary_c : integer := 0;
SIGNAL araddr_out : std_logic_vector(C_ADDRB_WIDTH-1 downto 0) := (OTHERS => '0');
COMPONENT read_netlist
GENERIC (
-- AXI Interface related parameters start here
C_AXI_TYPE : integer := 1;
C_ADDRB_WIDTH : integer := 12
);
port (
S_AXI_INCR_ADDR : OUT std_logic := '0';
S_AXI_ADDR_EN : OUT std_logic := '0';
S_AXI_SINGLE_TRANS : OUT std_logic := '0';
S_AXI_MUX_SEL : OUT std_logic := '0';
S_AXI_R_LAST : OUT std_logic := '0';
S_AXI_R_LAST_INT : IN std_logic := '0';
-- AXI Global Signals
S_ACLK : IN std_logic;
S_ARESETN : IN std_logic;
-- AXI Full/Lite Slave Read (Read side)
S_AXI_ARLEN : IN std_logic_vector(7 downto 0) := (OTHERS => '0');
S_AXI_ARVALID : IN std_logic := '0';
S_AXI_ARREADY : OUT std_logic;
S_AXI_RLAST : OUT std_logic;
S_AXI_RVALID : OUT std_logic;
S_AXI_RREADY : IN std_logic := '0';
-- AXI Full/Lite Read Address Signals to BRAM
S_AXI_RD_EN : OUT std_logic
);
END COMPONENT read_netlist;
BEGIN
dec_alen_c <= incr_addr_c OR r_last_int_c;
axi_read_fsm : read_netlist
GENERIC MAP(
C_AXI_TYPE => 1,
C_ADDRB_WIDTH => C_ADDRB_WIDTH
)
PORT MAP(
S_AXI_INCR_ADDR => incr_addr_c,
S_AXI_ADDR_EN => addr_en_c,
S_AXI_SINGLE_TRANS => single_trans_c,
S_AXI_MUX_SEL => mux_sel_c,
S_AXI_R_LAST => r_last_c,
S_AXI_R_LAST_INT => r_last_int_c,
-- AXI Global Signals
S_ACLK => S_ACLK,
S_ARESETN => S_ARESETN,
-- AXI Full/Lite Slave Read (Read side)
S_AXI_ARLEN => S_AXI_ARLEN,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_RLAST => S_AXI_RLAST,
S_AXI_RVALID => S_AXI_RVALID,
S_AXI_RREADY => S_AXI_RREADY,
-- AXI Full/Lite Read Address Signals to BRAM
S_AXI_RD_EN => rd_en_c
);
total_bytes <= conv_integer(num_of_bytes_r)*(conv_integer(arlen_int_r)+1);
wrap_base_addr_r <= (conv_integer(araddr_reg)/if_then_else(total_bytes=0,1,total_bytes))*(total_bytes);
wrap_boundary_r <= wrap_base_addr_r+total_bytes;
---- combinatorial from interface
num_of_bytes_c <= 2**conv_integer(if_then_else((C_AXI_TYPE = 1 AND C_AXI_SLAVE_TYPE = 0),S_AXI_ARSIZE,"000"));
arlen_int_c <= if_then_else(C_AXI_TYPE = 0,"00000000",S_AXI_ARLEN);
total_bytes_c <= conv_integer(num_of_bytes_c)*(conv_integer(arlen_int_c)+1);
wrap_base_addr_c <= (conv_integer(S_AXI_ARADDR)/if_then_else(total_bytes_c=0,1,total_bytes_c))*(total_bytes_c);
wrap_boundary_c <= wrap_base_addr_c+total_bytes_c;
arburst_int_c <= if_then_else((C_AXI_TYPE = 1 AND C_AXI_SLAVE_TYPE = 0),S_AXI_ARBURST,"01");
---------------------------------------------------------------------------
-- BMG address generation
---------------------------------------------------------------------------
P_addr_reg: PROCESS (S_ACLK,S_ARESETN)
BEGIN
IF (S_ARESETN = '1') THEN
araddr_reg <= (OTHERS => '0');
arburst_int_r <= (OTHERS => '0');
num_of_bytes_r <= 0;
ELSIF (S_ACLK'event AND S_ACLK = '1') THEN
IF (incr_addr_c = '1' AND addr_en_c = '1' AND single_trans_c = '0') THEN
arburst_int_r <= arburst_int_c;
num_of_bytes_r <= num_of_bytes_c;
IF (arburst_int_c = "10") THEN
IF(conv_integer(S_AXI_ARADDR) = (wrap_boundary_c-num_of_bytes_c)) THEN
araddr_reg <= conv_std_logic_vector(wrap_base_addr_c,C_AXI_ARADDR_WIDTH);
ELSE
araddr_reg <= S_AXI_ARADDR + num_of_bytes_c;
END IF;
ELSIF (arburst_int_c = "01" OR arburst_int_c = "11") THEN
araddr_reg <= S_AXI_ARADDR + num_of_bytes_c;
END IF;
ELSIF (addr_en_c = '1') THEN
araddr_reg <= S_AXI_ARADDR AFTER FLOP_DELAY;
num_of_bytes_r <= num_of_bytes_c;
arburst_int_r <= arburst_int_c;
ELSIF (incr_addr_c = '1') THEN
IF (arburst_int_r = "10") THEN
IF(conv_integer(araddr_reg) = (wrap_boundary_r-num_of_bytes_r)) THEN
araddr_reg <= conv_std_logic_vector(wrap_base_addr_r,C_AXI_ARADDR_WIDTH);
ELSE
araddr_reg <= araddr_reg + num_of_bytes_r;
END IF;
ELSIF (arburst_int_r = "01" OR arburst_int_r = "11") THEN
araddr_reg <= araddr_reg + num_of_bytes_r;
END IF;
END IF;
END IF;
END PROCESS P_addr_reg;
araddr_out <= if_then_else((C_AXI_TYPE = 1 AND C_AXI_SLAVE_TYPE = 0),araddr_reg(C_AXI_ARADDR_WIDTH-1 DOWNTO C_RANGE),araddr_reg);
--------------------------------------------------------------------------
-- Counter to generate r_last_int_c from registered ARLEN - AXI FULL FSM
--------------------------------------------------------------------------
P_addr_cnt: PROCESS (S_ACLK, S_ARESETN)
BEGIN
IF S_ARESETN = '1' THEN
arlen_cntr <= ONE;
arlen_int_r <= (OTHERS => '0');
ELSIF S_ACLK'event AND S_ACLK = '1' THEN
IF (addr_en_c = '1' AND dec_alen_c = '1' AND single_trans_c = '0') THEN
arlen_int_r <= if_then_else(C_AXI_TYPE = 0,"00000000",S_AXI_ARLEN);
arlen_cntr <= S_AXI_ARLEN - ONE AFTER FLOP_DELAY;
ELSIF addr_en_c = '1' THEN
arlen_int_r <= if_then_else(C_AXI_TYPE = 0,"00000000",S_AXI_ARLEN);
arlen_cntr <= if_then_else(C_AXI_TYPE = 0,"00000000",S_AXI_ARLEN);
ELSIF dec_alen_c = '1' THEN
arlen_cntr <= arlen_cntr - ONE AFTER FLOP_DELAY;
ELSE
arlen_cntr <= arlen_cntr AFTER FLOP_DELAY;
END IF;
END IF;
END PROCESS P_addr_cnt;
r_last_int_c <= '1' WHEN (arlen_cntr = "00000000" AND S_AXI_RREADY = '1') ELSE '0' ;
--------------------------------------------------------------------------
-- AXI FULL FSM
-- Mux Selection of ARADDR
-- ARADDR is driven out from the read fsm based on the mux_sel_c
-- Based on mux_sel either ARADDR is given out or the latched ARADDR is
-- given out to BRAM
--------------------------------------------------------------------------
P_araddr_mux: PROCESS (mux_sel_c,S_AXI_ARADDR,araddr_out)
BEGIN
IF (mux_sel_c = '0') THEN
S_AXI_ARADDR_OUT <= if_then_else((C_AXI_TYPE = 1 AND C_AXI_SLAVE_TYPE = 0),S_AXI_ARADDR(C_AXI_ARADDR_WIDTH-1 DOWNTO C_RANGE),S_AXI_ARADDR);
ELSE
S_AXI_ARADDR_OUT <= araddr_out;
END IF;
END PROCESS P_araddr_mux;
--------------------------------------------------------------------------
-- Assign output signals - AXI FULL FSM
--------------------------------------------------------------------------
S_AXI_RD_EN <= rd_en_c;
grid: IF (C_HAS_AXI_ID = 1) GENERATE
P_rid_gen: PROCESS (S_ACLK,S_ARESETN)
BEGIN
IF (S_ARESETN='1') THEN
S_AXI_RID <= (OTHERS => '0');
ar_id_r <= (OTHERS => '0');
ELSIF (S_ACLK'event AND S_ACLK='1') THEN
IF (addr_en_c = '1' AND rd_en_c = '1') THEN
S_AXI_RID <= S_AXI_ARID;
ar_id_r <= S_AXI_ARID;
ELSIF (addr_en_c = '1' AND rd_en_c = '0') THEN
ar_id_r <= S_AXI_ARID;
ELSIF (rd_en_c = '1') THEN
S_AXI_RID <= ar_id_r;
END IF;
END IF;
END PROCESS P_rid_gen;
END GENERATE grid;
END blk_mem_axi_read_wrapper_beh_arch;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
entity read_netlist is
GENERIC (
-- AXI Interface related parameters start here
C_AXI_TYPE : integer := 1;
C_ADDRB_WIDTH : integer := 12
);
port (
S_AXI_R_LAST_INT : in STD_LOGIC := '0';
S_ACLK : in STD_LOGIC := '0';
S_ARESETN : in STD_LOGIC := '0';
S_AXI_ARVALID : in STD_LOGIC := '0';
S_AXI_RREADY : in STD_LOGIC := '0';
S_AXI_INCR_ADDR : out STD_LOGIC;
S_AXI_ADDR_EN : out STD_LOGIC;
S_AXI_SINGLE_TRANS : out STD_LOGIC;
S_AXI_MUX_SEL : out STD_LOGIC;
S_AXI_R_LAST : out STD_LOGIC;
S_AXI_ARREADY : out STD_LOGIC;
S_AXI_RLAST : out STD_LOGIC;
S_AXI_RVALID : out STD_LOGIC;
S_AXI_RD_EN : out STD_LOGIC;
S_AXI_ARLEN : in STD_LOGIC_VECTOR ( 7 downto 0 )
);
end read_netlist;
architecture STRUCTURE of read_netlist is
component beh_muxf7
port(
O : out std_ulogic;
I0 : in std_ulogic;
I1 : in std_ulogic;
S : in std_ulogic
);
end component;
COMPONENT beh_ff_pre
generic(
INIT : std_logic := '1'
);
port(
Q : out std_logic;
C : in std_logic;
D : in std_logic;
PRE : in std_logic
);
end COMPONENT beh_ff_pre;
COMPONENT beh_ff_ce
generic(
INIT : std_logic := '0'
);
port(
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
CLR : in std_logic;
D : in std_logic
);
end COMPONENT beh_ff_ce;
COMPONENT beh_ff_clr
generic(
INIT : std_logic := '0'
);
port(
Q : out std_logic;
C : in std_logic;
CLR : in std_logic;
D : in std_logic
);
end COMPONENT beh_ff_clr;
COMPONENT STATE_LOGIC
generic(
INIT : std_logic_vector(63 downto 0) := X"0000000000000000"
);
port(
O : out std_logic;
I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic;
I3 : in std_logic;
I4 : in std_logic;
I5 : in std_logic
);
end COMPONENT STATE_LOGIC;
signal present_state_FSM_FFd1_13 : STD_LOGIC;
signal present_state_FSM_FFd2_14 : STD_LOGIC;
signal gaxi_full_sm_outstanding_read_r_15 : STD_LOGIC;
signal gaxi_full_sm_ar_ready_r_16 : STD_LOGIC;
signal gaxi_full_sm_r_last_r_17 : STD_LOGIC;
signal NlwRenamedSig_OI_gaxi_full_sm_r_valid_r : STD_LOGIC;
signal gaxi_full_sm_r_valid_c : STD_LOGIC;
signal S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o : STD_LOGIC;
signal gaxi_full_sm_ar_ready_c : STD_LOGIC;
signal gaxi_full_sm_outstanding_read_c : STD_LOGIC;
signal NlwRenamedSig_OI_S_AXI_R_LAST : STD_LOGIC;
signal S_AXI_ARLEN_7_GND_8_o_equal_1_o : STD_LOGIC;
signal present_state_FSM_FFd2_In : STD_LOGIC;
signal present_state_FSM_FFd1_In : STD_LOGIC;
signal Mmux_S_AXI_R_LAST13 : STD_LOGIC;
signal N01 : STD_LOGIC;
signal N2 : STD_LOGIC;
signal Mmux_gaxi_full_sm_ar_ready_c11 : STD_LOGIC;
signal N4 : STD_LOGIC;
signal N8 : STD_LOGIC;
signal N9 : STD_LOGIC;
signal N10 : STD_LOGIC;
signal N11 : STD_LOGIC;
signal N12 : STD_LOGIC;
signal N13 : STD_LOGIC;
begin
S_AXI_R_LAST <= NlwRenamedSig_OI_S_AXI_R_LAST;
S_AXI_ARREADY <= gaxi_full_sm_ar_ready_r_16;
S_AXI_RLAST <= gaxi_full_sm_r_last_r_17;
S_AXI_RVALID <= NlwRenamedSig_OI_gaxi_full_sm_r_valid_r;
gaxi_full_sm_outstanding_read_r : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => gaxi_full_sm_outstanding_read_c,
Q => gaxi_full_sm_outstanding_read_r_15
);
gaxi_full_sm_r_valid_r : beh_ff_ce
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CE => S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o,
CLR => S_ARESETN,
D => gaxi_full_sm_r_valid_c,
Q => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r
);
gaxi_full_sm_ar_ready_r : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => gaxi_full_sm_ar_ready_c,
Q => gaxi_full_sm_ar_ready_r_16
);
gaxi_full_sm_r_last_r : beh_ff_ce
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CE => S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o,
CLR => S_ARESETN,
D => NlwRenamedSig_OI_S_AXI_R_LAST,
Q => gaxi_full_sm_r_last_r_17
);
present_state_FSM_FFd2 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => present_state_FSM_FFd2_In,
Q => present_state_FSM_FFd2_14
);
present_state_FSM_FFd1 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => present_state_FSM_FFd1_In,
Q => present_state_FSM_FFd1_13
);
S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o1 : STATE_LOGIC
generic map(
INIT => X"000000000000000B"
)
port map (
I0 => S_AXI_RREADY,
I1 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I2 => '0',
I3 => '0',
I4 => '0',
I5 => '0',
O => S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o
);
Mmux_S_AXI_SINGLE_TRANS11 : STATE_LOGIC
generic map(
INIT => X"0000000000000008"
)
port map (
I0 => S_AXI_ARVALID,
I1 => S_AXI_ARLEN_7_GND_8_o_equal_1_o,
I2 => '0',
I3 => '0',
I4 => '0',
I5 => '0',
O => S_AXI_SINGLE_TRANS
);
Mmux_S_AXI_ADDR_EN11 : STATE_LOGIC
generic map(
INIT => X"0000000000000004"
)
port map (
I0 => present_state_FSM_FFd1_13,
I1 => S_AXI_ARVALID,
I2 => '0',
I3 => '0',
I4 => '0',
I5 => '0',
O => S_AXI_ADDR_EN
);
present_state_FSM_FFd2_In1 : STATE_LOGIC
generic map(
INIT => X"ECEE2022EEEE2022"
)
port map (
I0 => S_AXI_ARVALID,
I1 => present_state_FSM_FFd1_13,
I2 => S_AXI_RREADY,
I3 => S_AXI_ARLEN_7_GND_8_o_equal_1_o,
I4 => present_state_FSM_FFd2_14,
I5 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
O => present_state_FSM_FFd2_In
);
Mmux_S_AXI_R_LAST131 : STATE_LOGIC
generic map(
INIT => X"0000000044440444"
)
port map (
I0 => present_state_FSM_FFd1_13,
I1 => S_AXI_ARVALID,
I2 => present_state_FSM_FFd2_14,
I3 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I4 => S_AXI_RREADY,
I5 => '0',
O => Mmux_S_AXI_R_LAST13
);
Mmux_S_AXI_INCR_ADDR11 : STATE_LOGIC
generic map(
INIT => X"4000FFFF40004000"
)
port map (
I0 => S_AXI_R_LAST_INT,
I1 => S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o,
I2 => present_state_FSM_FFd2_14,
I3 => present_state_FSM_FFd1_13,
I4 => S_AXI_ARLEN_7_GND_8_o_equal_1_o,
I5 => Mmux_S_AXI_R_LAST13,
O => S_AXI_INCR_ADDR
);
S_AXI_ARLEN_7_GND_8_o_equal_1_o_7_SW0 : STATE_LOGIC
generic map(
INIT => X"00000000000000FE"
)
port map (
I0 => S_AXI_ARLEN(2),
I1 => S_AXI_ARLEN(1),
I2 => S_AXI_ARLEN(0),
I3 => '0',
I4 => '0',
I5 => '0',
O => N01
);
S_AXI_ARLEN_7_GND_8_o_equal_1_o_7_Q : STATE_LOGIC
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => S_AXI_ARLEN(7),
I1 => S_AXI_ARLEN(6),
I2 => S_AXI_ARLEN(5),
I3 => S_AXI_ARLEN(4),
I4 => S_AXI_ARLEN(3),
I5 => N01,
O => S_AXI_ARLEN_7_GND_8_o_equal_1_o
);
Mmux_gaxi_full_sm_outstanding_read_c1_SW0 : STATE_LOGIC
generic map(
INIT => X"0000000000000007"
)
port map (
I0 => S_AXI_ARVALID,
I1 => S_AXI_ARLEN_7_GND_8_o_equal_1_o,
I2 => '0',
I3 => '0',
I4 => '0',
I5 => '0',
O => N2
);
Mmux_gaxi_full_sm_outstanding_read_c1 : STATE_LOGIC
generic map(
INIT => X"0020000002200200"
)
port map (
I0 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I1 => S_AXI_RREADY,
I2 => present_state_FSM_FFd1_13,
I3 => present_state_FSM_FFd2_14,
I4 => gaxi_full_sm_outstanding_read_r_15,
I5 => N2,
O => gaxi_full_sm_outstanding_read_c
);
Mmux_gaxi_full_sm_ar_ready_c12 : STATE_LOGIC
generic map(
INIT => X"0000000000004555"
)
port map (
I0 => S_AXI_ARVALID,
I1 => S_AXI_RREADY,
I2 => present_state_FSM_FFd2_14,
I3 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I4 => '0',
I5 => '0',
O => Mmux_gaxi_full_sm_ar_ready_c11
);
Mmux_S_AXI_R_LAST11_SW0 : STATE_LOGIC
generic map(
INIT => X"00000000000000EF"
)
port map (
I0 => S_AXI_ARLEN_7_GND_8_o_equal_1_o,
I1 => S_AXI_RREADY,
I2 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I3 => '0',
I4 => '0',
I5 => '0',
O => N4
);
Mmux_S_AXI_R_LAST11 : STATE_LOGIC
generic map(
INIT => X"FCAAFC0A00AA000A"
)
port map (
I0 => S_AXI_ARVALID,
I1 => gaxi_full_sm_outstanding_read_r_15,
I2 => present_state_FSM_FFd2_14,
I3 => present_state_FSM_FFd1_13,
I4 => N4,
I5 => S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o,
O => gaxi_full_sm_r_valid_c
);
S_AXI_MUX_SEL1 : STATE_LOGIC
generic map(
INIT => X"00000000AAAAAA08"
)
port map (
I0 => present_state_FSM_FFd1_13,
I1 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I2 => S_AXI_RREADY,
I3 => present_state_FSM_FFd2_14,
I4 => gaxi_full_sm_outstanding_read_r_15,
I5 => '0',
O => S_AXI_MUX_SEL
);
Mmux_S_AXI_RD_EN11 : STATE_LOGIC
generic map(
INIT => X"F3F3F755A2A2A200"
)
port map (
I0 => present_state_FSM_FFd1_13,
I1 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I2 => S_AXI_RREADY,
I3 => gaxi_full_sm_outstanding_read_r_15,
I4 => present_state_FSM_FFd2_14,
I5 => S_AXI_ARVALID,
O => S_AXI_RD_EN
);
present_state_FSM_FFd1_In3 : beh_muxf7
port map (
I0 => N8,
I1 => N9,
S => present_state_FSM_FFd1_13,
O => present_state_FSM_FFd1_In
);
present_state_FSM_FFd1_In3_F : STATE_LOGIC
generic map(
INIT => X"000000005410F4F0"
)
port map (
I0 => S_AXI_RREADY,
I1 => present_state_FSM_FFd2_14,
I2 => S_AXI_ARVALID,
I3 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I4 => S_AXI_ARLEN_7_GND_8_o_equal_1_o,
I5 => '0',
O => N8
);
present_state_FSM_FFd1_In3_G : STATE_LOGIC
generic map(
INIT => X"0000000072FF7272"
)
port map (
I0 => present_state_FSM_FFd2_14,
I1 => S_AXI_R_LAST_INT,
I2 => gaxi_full_sm_outstanding_read_r_15,
I3 => S_AXI_RREADY,
I4 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I5 => '0',
O => N9
);
Mmux_gaxi_full_sm_ar_ready_c14 : beh_muxf7
port map (
I0 => N10,
I1 => N11,
S => present_state_FSM_FFd1_13,
O => gaxi_full_sm_ar_ready_c
);
Mmux_gaxi_full_sm_ar_ready_c14_F : STATE_LOGIC
generic map(
INIT => X"00000000FFFF88A8"
)
port map (
I0 => S_AXI_ARLEN_7_GND_8_o_equal_1_o,
I1 => S_AXI_RREADY,
I2 => present_state_FSM_FFd2_14,
I3 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I4 => Mmux_gaxi_full_sm_ar_ready_c11,
I5 => '0',
O => N10
);
Mmux_gaxi_full_sm_ar_ready_c14_G : STATE_LOGIC
generic map(
INIT => X"000000008D008D8D"
)
port map (
I0 => present_state_FSM_FFd2_14,
I1 => S_AXI_R_LAST_INT,
I2 => gaxi_full_sm_outstanding_read_r_15,
I3 => S_AXI_RREADY,
I4 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I5 => '0',
O => N11
);
Mmux_S_AXI_R_LAST1 : beh_muxf7
port map (
I0 => N12,
I1 => N13,
S => present_state_FSM_FFd1_13,
O => NlwRenamedSig_OI_S_AXI_R_LAST
);
Mmux_S_AXI_R_LAST1_F : STATE_LOGIC
generic map(
INIT => X"0000000088088888"
)
port map (
I0 => S_AXI_ARLEN_7_GND_8_o_equal_1_o,
I1 => S_AXI_ARVALID,
I2 => present_state_FSM_FFd2_14,
I3 => S_AXI_RREADY,
I4 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I5 => '0',
O => N12
);
Mmux_S_AXI_R_LAST1_G : STATE_LOGIC
generic map(
INIT => X"00000000E400E4E4"
)
port map (
I0 => present_state_FSM_FFd2_14,
I1 => gaxi_full_sm_outstanding_read_r_15,
I2 => S_AXI_R_LAST_INT,
I3 => S_AXI_RREADY,
I4 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I5 => '0',
O => N13
);
end STRUCTURE;
-------------------------------------------------------------------------------
-- Output Register Stage Entity
--
-- This module builds the output register stages of the memory. This module is
-- instantiated in the main memory module (blk_mem_gen_v8_3_0) which is
-- declared/implemented further down in this file.
-------------------------------------------------------------------------------
LIBRARY STD;
USE STD.TEXTIO.ALL;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY blk_mem_gen_v8_3_0_output_stage IS
GENERIC (
C_FAMILY : STRING := "virtex7";
C_XDEVICEFAMILY : STRING := "virtex7";
C_RST_TYPE : STRING := "SYNC";
C_HAS_RST : INTEGER := 0;
C_RSTRAM : INTEGER := 0;
C_RST_PRIORITY : STRING := "CE";
init_val : STD_LOGIC_VECTOR;
C_HAS_EN : INTEGER := 0;
C_HAS_REGCE : INTEGER := 0;
C_DATA_WIDTH : INTEGER := 32;
C_ADDRB_WIDTH : INTEGER := 10;
C_HAS_MEM_OUTPUT_REGS : INTEGER := 0;
C_USE_SOFTECC : INTEGER := 0;
C_USE_ECC : INTEGER := 0;
NUM_STAGES : INTEGER := 1;
C_EN_ECC_PIPE : INTEGER := 0;
FLOP_DELAY : TIME := 100 ps
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
REGCE : IN STD_LOGIC;
DIN_I : IN STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
DOUT : OUT STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
SBITERR_IN_I : IN STD_LOGIC;
DBITERR_IN_I : IN STD_LOGIC;
SBITERR : OUT STD_LOGIC;
DBITERR : OUT STD_LOGIC;
RDADDRECC_IN_I : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0);
eccpipece : IN STD_LOGIC;
RDADDRECC : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0)
);
END blk_mem_gen_v8_3_0_output_stage;
--******************************
-- Port and Generic Definitions
--******************************
---------------------------------------------------------------------------
-- Generic Definitions
---------------------------------------------------------------------------
-- C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following
-- options are available - "spartan3", "spartan6",
-- "virtex4", "virtex5", "virtex6" and "virtex6l".
-- C_RST_TYPE : Type of reset - Synchronous or Asynchronous
-- C_HAS_RST : Determines the presence of the RST port
-- C_RSTRAM : Determines if special reset behavior is used
-- C_RST_PRIORITY : Determines the priority between CE and SR
-- C_INIT_VAL : Initialization value
-- C_HAS_EN : Determines the presence of the EN port
-- C_HAS_REGCE : Determines the presence of the REGCE port
-- C_DATA_WIDTH : Memory write/read width
-- C_ADDRB_WIDTH : Width of the ADDRB input port
-- C_HAS_MEM_OUTPUT_REGS : Designates the use of a register at the output
-- of the RAM primitive
-- C_USE_SOFTECC : Determines if the Soft ECC feature is used or
-- not. Only applicable Spartan-6
-- C_USE_ECC : Determines if the ECC feature is used or
-- not. Only applicable for V5 and V6
-- NUM_STAGES : Determines the number of output stages
-- FLOP_DELAY : Constant delay for register assignments
---------------------------------------------------------------------------
-- Port Definitions
---------------------------------------------------------------------------
-- CLK : Clock to synchronize all read and write operations
-- RST : Reset input to reset memory outputs to a user-defined
-- reset state
-- EN : Enable all read and write operations
-- REGCE : Register Clock Enable to control each pipeline output
-- register stages
-- DIN : Data input to the Output stage.
-- DOUT : Final Data output
-- SBITERR_IN : SBITERR input signal to the Output stage.
-- SBITERR : Final SBITERR Output signal.
-- DBITERR_IN : DBITERR input signal to the Output stage.
-- DBITERR : Final DBITERR Output signal.
-- RDADDRECC_IN : RDADDRECC input signal to the Output stage.
-- RDADDRECC : Final RDADDRECC Output signal.
---------------------------------------------------------------------------
ARCHITECTURE output_stage_behavioral OF blk_mem_gen_v8_3_0_output_stage IS
--*******************************************************
-- Functions used in the output stage ARCHITECTURE
--*******************************************************
-- Calculate num_reg_stages
FUNCTION get_num_reg_stages(NUM_STAGES: INTEGER) RETURN INTEGER IS
VARIABLE num_reg_stages : INTEGER := 0;
BEGIN
IF (NUM_STAGES = 0) THEN
num_reg_stages := 0;
ELSE
num_reg_stages := NUM_STAGES - 1;
END IF;
RETURN num_reg_stages;
END get_num_reg_stages;
-- Check if the INTEGER is zero or non-zero
FUNCTION int_to_bit(input: INTEGER) RETURN STD_LOGIC IS
VARIABLE temp_return : STD_LOGIC;
BEGIN
IF (input = 0) THEN
temp_return := '0';
ELSE
temp_return := '1';
END IF;
RETURN temp_return;
END int_to_bit;
-- Constants
CONSTANT HAS_EN : STD_LOGIC := int_to_bit(C_HAS_EN);
CONSTANT HAS_REGCE : STD_LOGIC := int_to_bit(C_HAS_REGCE);
CONSTANT HAS_RST : STD_LOGIC := int_to_bit(C_HAS_RST);
CONSTANT REG_STAGES : INTEGER := get_num_reg_stages(NUM_STAGES);
-- Pipeline array
TYPE reg_data_array IS ARRAY (REG_STAGES-1 DOWNTO 0) OF STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
TYPE reg_ecc_array IS ARRAY (REG_STAGES-1 DOWNTO 0) OF STD_LOGIC;
TYPE reg_eccaddr_array IS ARRAY (REG_STAGES-1 DOWNTO 0) OF STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0);
CONSTANT REG_INIT : reg_data_array := (OTHERS => init_val);
SIGNAL out_regs : reg_data_array := REG_INIT;
SIGNAL sbiterr_regs : reg_ecc_array := (OTHERS => '0');
SIGNAL dbiterr_regs : reg_ecc_array := (OTHERS => '0');
SIGNAL rdaddrecc_regs: reg_eccaddr_array := (OTHERS => (OTHERS => '0'));
-- Internal signals
SIGNAL en_i : STD_LOGIC;
SIGNAL regce_i : STD_LOGIC;
SIGNAL rst_i : STD_LOGIC;
SIGNAL dout_i : STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0) := init_val;
SIGNAL sbiterr_i: STD_LOGIC := '0';
SIGNAL dbiterr_i: STD_LOGIC := '0';
SIGNAL rdaddrecc_i : STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL DIN : STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL RDADDRECC_IN : STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0') ;
SIGNAL SBITERR_IN : STD_LOGIC := '0';
SIGNAL DBITERR_IN : STD_LOGIC := '0';
BEGIN
--***********************************************************************
-- Assign internal signals. This effectively wires off optional inputs.
--***********************************************************************
-- Internal enable for output registers is tied to user EN or '1' depending
-- on parameters
en_i <= EN OR (NOT HAS_EN);
-- Internal register enable for output registers is tied to user REGCE, EN
-- or '1' depending on parameters
regce_i <= (HAS_REGCE AND REGCE)
OR ((NOT HAS_REGCE) AND en_i);
-- Internal SRR is tied to user RST or '0' depending on parameters
rst_i <= RST AND HAS_RST;
--***************************************************************************
-- NUM_STAGES = 0 (No output registers. RAM only)
--***************************************************************************
zero_stages: IF (NUM_STAGES = 0) GENERATE
DOUT <= DIN;
SBITERR <= SBITERR_IN;
DBITERR <= DBITERR_IN;
RDADDRECC <= RDADDRECC_IN;
END GENERATE zero_stages;
NO_ECC_PIPE_REG: IF (C_EN_ECC_PIPE = 0) GENERATE
DIN <= DIN_I;
RDADDRECC_IN <= RDADDRECC_IN_I;
SBITERR_IN <= SBITERR_IN_I;
DBITERR_IN <= DBITERR_IN_I;
END GENERATE NO_ECC_PIPE_REG;
WITH_ECC_PIPE_REG: IF (C_EN_ECC_PIPE = 1) GENERATE
PROCESS (CLK)
BEGIN
IF (CLK'EVENT AND CLK = '1') THEN
IF(ECCPIPECE = '1') THEN
DIN <= DIN_I AFTER FLOP_DELAY;
RDADDRECC_IN <= RDADDRECC_IN_I AFTER FLOP_DELAY;
SBITERR_IN <= SBITERR_IN_I AFTER FLOP_DELAY;
DBITERR_IN <= DBITERR_IN_I AFTER FLOP_DELAY;
END IF;
END IF;
END PROCESS;
END GENERATE WITH_ECC_PIPE_REG;
--***************************************************************************
-- NUM_STAGES = 1
-- (Mem Output Reg only or Mux Output Reg only)
--***************************************************************************
-- Possible valid combinations:
-- Note: C_HAS_MUX_OUTPUT_REGS_*=0 when (C_RSTRAM_*=1)
-- +-----------------------------------------+
-- | C_RSTRAM_* | Reset Behavior |
-- +----------------+------------------------+
-- | 0 | Normal Behavior |
-- +----------------+------------------------+
-- | 1 | Special Behavior |
-- +----------------+------------------------+
--
-- Normal = REGCE gates reset, as in the case of all Virtex families and all
-- spartan families with the exception of S3ADSP and S6.
-- Special = EN gates reset, as in the case of S3ADSP and S6.
one_stage_norm: IF (NUM_STAGES = 1 AND
(C_RSTRAM=0 OR (C_RSTRAM=1 AND (C_XDEVICEFAMILY/="spartan3adsp" AND C_XDEVICEFAMILY/="aspartan3adsp")) OR
C_HAS_MEM_OUTPUT_REGS=0 OR C_HAS_RST=0)) GENERATE
DOUT <= dout_i;
SBITERR <= sbiterr_i WHEN (C_USE_ECC=1 OR C_USE_SOFTECC = 1) ELSE '0';
DBITERR <= dbiterr_i WHEN (C_USE_ECC=1 OR C_USE_SOFTECC = 1) ELSE '0';
RDADDRECC <= rdaddrecc_i WHEN (C_USE_ECC=1 OR C_USE_SOFTECC = 1) ELSE (OTHERS => '0');
PROCESS (CLK,rst_i,regce_i)
BEGIN
IF (CLK'EVENT AND CLK = '1') THEN
IF(C_RST_PRIORITY = "CE") THEN --REGCE has priority and controls reset
IF (rst_i = '1' AND regce_i='1') THEN
dout_i <= init_val AFTER FLOP_DELAY;
sbiterr_i <= '0' AFTER FLOP_DELAY;
dbiterr_i <= '0' AFTER FLOP_DELAY;
rdaddrecc_i <= (OTHERS => '0') AFTER FLOP_DELAY;
ELSIF (regce_i='1') THEN
dout_i <= DIN AFTER FLOP_DELAY;
sbiterr_i <= SBITERR_IN AFTER FLOP_DELAY;
dbiterr_i <= DBITERR_IN AFTER FLOP_DELAY;
rdaddrecc_i <= RDADDRECC_IN AFTER FLOP_DELAY;
END IF;
ELSE --RSTA has priority and is independent of REGCE
IF (rst_i = '1') THEN
dout_i <= init_val AFTER FLOP_DELAY;
sbiterr_i <= '0' AFTER FLOP_DELAY;
dbiterr_i <= '0' AFTER FLOP_DELAY;
rdaddrecc_i <= (OTHERS => '0') AFTER FLOP_DELAY;
ELSIF (regce_i='1') THEN
dout_i <= DIN AFTER FLOP_DELAY;
sbiterr_i <= SBITERR_IN AFTER FLOP_DELAY;
dbiterr_i <= DBITERR_IN AFTER FLOP_DELAY;
rdaddrecc_i <= RDADDRECC_IN AFTER FLOP_DELAY;
END IF;
END IF;--Priority conditions
END IF;--CLK
END PROCESS;
END GENERATE one_stage_norm;
-- Special Reset Behavior for S6 and S3ADSP
one_stage_splbhv: IF (NUM_STAGES=1 AND C_RSTRAM=1 AND (C_XDEVICEFAMILY ="spartan3adsp" OR C_XDEVICEFAMILY ="aspartan3adsp"))
GENERATE
DOUT <= dout_i;
SBITERR <= '0';
DBITERR <= '0';
RDADDRECC <= (OTHERS => '0');
PROCESS (CLK)
BEGIN
IF (CLK'EVENT AND CLK = '1') THEN
IF (rst_i='1' AND en_i='1') THEN
dout_i <= init_val AFTER FLOP_DELAY;
ELSIF (regce_i='1' AND rst_i/='1') THEN
dout_i <= DIN AFTER FLOP_DELAY;
END IF;
END IF;--CLK
END PROCESS;
END GENERATE one_stage_splbhv;
--****************************************************************************
-- NUM_STAGES > 1
-- Mem Output Reg + Mux Output Reg
-- or
-- Mem Output Reg + Mux Pipeline Stages (>0) + Mux Output Reg
-- or
-- Mux Pipeline Stages (>0) + Mux Output Reg
--****************************************************************************
multi_stage: IF (NUM_STAGES > 1) GENERATE
DOUT <= dout_i;
SBITERR <= sbiterr_i;
DBITERR <= dbiterr_i;
RDADDRECC <= rdaddrecc_i;
PROCESS (CLK,rst_i,regce_i)
BEGIN
IF (CLK'EVENT AND CLK = '1') THEN
IF(C_RST_PRIORITY = "CE") THEN --REGCE has priority and controls reset
IF (rst_i='1'AND regce_i='1') THEN
dout_i <= init_val AFTER FLOP_DELAY;
sbiterr_i <= '0' AFTER FLOP_DELAY;
dbiterr_i <= '0' AFTER FLOP_DELAY;
rdaddrecc_i <= (OTHERS => '0') AFTER FLOP_DELAY;
ELSIF (regce_i='1') THEN
dout_i <= out_regs(REG_STAGES-1) AFTER FLOP_DELAY;
sbiterr_i <= sbiterr_regs(REG_STAGES-1) AFTER FLOP_DELAY;
dbiterr_i <= dbiterr_regs(REG_STAGES-1) AFTER FLOP_DELAY;
rdaddrecc_i <= rdaddrecc_regs(REG_STAGES-1) AFTER FLOP_DELAY;
END IF;
ELSE --RSTA has priority and is independent of REGCE
IF (rst_i = '1') THEN
dout_i <= init_val AFTER FLOP_DELAY;
sbiterr_i <= '0' AFTER FLOP_DELAY;
dbiterr_i <= '0' AFTER FLOP_DELAY;
rdaddrecc_i <= (OTHERS => '0') AFTER FLOP_DELAY;
ELSIF (regce_i='1') THEN
dout_i <= out_regs(REG_STAGES-1) AFTER FLOP_DELAY;
sbiterr_i <= sbiterr_regs(REG_STAGES-1) AFTER FLOP_DELAY;
dbiterr_i <= dbiterr_regs(REG_STAGES-1) AFTER FLOP_DELAY;
rdaddrecc_i <= rdaddrecc_regs(REG_STAGES-1) AFTER FLOP_DELAY;
END IF;
END IF;--Priority conditions
IF (en_i='1') THEN
-- Shift the data through the output stages
FOR i IN 1 TO REG_STAGES-1 LOOP
out_regs(i) <= out_regs(i-1) AFTER FLOP_DELAY;
sbiterr_regs(i) <= sbiterr_regs(i-1) AFTER FLOP_DELAY;
dbiterr_regs(i) <= dbiterr_regs(i-1) AFTER FLOP_DELAY;
rdaddrecc_regs(i) <= rdaddrecc_regs(i-1) AFTER FLOP_DELAY;
END LOOP;
out_regs(0) <= DIN;
sbiterr_regs(0) <= SBITERR_IN;
dbiterr_regs(0) <= DBITERR_IN;
rdaddrecc_regs(0) <= RDADDRECC_IN;
END IF;
END IF;--CLK
END PROCESS;
END GENERATE multi_stage;
END output_stage_behavioral;
-------------------------------------------------------------------------------
-- SoftECC Output Register Stage Entity
-- This module builds the softecc output register stages. This module is
-- instantiated in the memory module (blk_mem_gen_v8_3_0_mem_module) which is
-- declared/implemented further down in this file.
-------------------------------------------------------------------------------
LIBRARY STD;
USE STD.TEXTIO.ALL;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY blk_mem_gen_v8_3_0_softecc_output_reg_stage IS
GENERIC (
C_DATA_WIDTH : INTEGER := 32;
C_ADDRB_WIDTH : INTEGER := 10;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER := 0;
C_USE_SOFTECC : INTEGER := 0;
FLOP_DELAY : TIME := 100 ps
);
PORT (
CLK : IN STD_LOGIC;
DIN : IN STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0) ;
DOUT : OUT STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
SBITERR_IN : IN STD_LOGIC;
DBITERR_IN : IN STD_LOGIC;
SBITERR : OUT STD_LOGIC;
DBITERR : OUT STD_LOGIC;
RDADDRECC_IN : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) ;
RDADDRECC : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0)
);
END blk_mem_gen_v8_3_0_softecc_output_reg_stage;
--******************************
-- Port and Generic Definitions
--******************************
---------------------------------------------------------------------------
-- Generic Definitions
---------------------------------------------------------------------------
-- C_DATA_WIDTH : Memory write/read width
-- C_ADDRB_WIDTH : Width of the ADDRB input port
-- of the RAM primitive
-- FLOP_DELAY : Constant delay for register assignments
---------------------------------------------------------------------------
-- Port Definitions
---------------------------------------------------------------------------
-- CLK : Clock to synchronize all read and write operations
-- RST : Reset input to reset memory outputs to a user-defined
-- reset state
-- EN : Enable all read and write operations
-- REGCE : Register Clock Enable to control each pipeline output
-- register stages
-- DIN : Data input to the Output stage.
-- DOUT : Final Data output
-- SBITERR_IN : SBITERR input signal to the Output stage.
-- SBITERR : Final SBITERR Output signal.
-- DBITERR_IN : DBITERR input signal to the Output stage.
-- DBITERR : Final DBITERR Output signal.
-- RDADDRECC_IN : RDADDRECC input signal to the Output stage.
-- RDADDRECC : Final RDADDRECC Output signal.
---------------------------------------------------------------------------
ARCHITECTURE softecc_output_reg_stage_behavioral OF blk_mem_gen_v8_3_0_softecc_output_reg_stage IS
-- Internal signals
SIGNAL dout_i : STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL sbiterr_i: STD_LOGIC := '0';
SIGNAL dbiterr_i: STD_LOGIC := '0';
SIGNAL rdaddrecc_i : STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
BEGIN
--***************************************************************************
-- NO OUTPUT STAGES
--***************************************************************************
no_output_stage: IF (C_HAS_SOFTECC_OUTPUT_REGS_B=0) GENERATE
DOUT <= DIN;
SBITERR <= SBITERR_IN;
DBITERR <= DBITERR_IN;
RDADDRECC <= RDADDRECC_IN;
END GENERATE no_output_stage;
--****************************************************************************
-- WITH OUTPUT STAGE
--****************************************************************************
has_output_stage: IF (C_HAS_SOFTECC_OUTPUT_REGS_B=1) GENERATE
PROCESS (CLK)
BEGIN
IF (CLK'EVENT AND CLK = '1') THEN
dout_i <= DIN AFTER FLOP_DELAY;
sbiterr_i <= SBITERR_IN AFTER FLOP_DELAY;
dbiterr_i <= DBITERR_IN AFTER FLOP_DELAY;
rdaddrecc_i <= RDADDRECC_IN AFTER FLOP_DELAY;
END IF;
END PROCESS;
DOUT <= dout_i;
SBITERR <= sbiterr_i;
DBITERR <= dbiterr_i;
RDADDRECC <= rdaddrecc_i;
END GENERATE has_output_stage;
END softecc_output_reg_stage_behavioral;
--******************************************************************************
-- Main Memory module
--
-- This module is the behavioral model which implements the RAM
--******************************************************************************
LIBRARY STD;
USE STD.TEXTIO.ALL;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.std_logic_textio.all;
ENTITY blk_mem_gen_v8_3_0_mem_module IS
GENERIC (
C_CORENAME : STRING := "blk_mem_gen_v8_3_0";
C_FAMILY : STRING := "virtex7";
C_XDEVICEFAMILY : STRING := "virtex7";
C_USE_BRAM_BLOCK : INTEGER := 0;
C_ENABLE_32BIT_ADDRESS : INTEGER := 0;
C_MEM_TYPE : INTEGER := 2;
C_BYTE_SIZE : INTEGER := 8;
C_ALGORITHM : INTEGER := 2;
C_PRIM_TYPE : INTEGER := 3;
C_LOAD_INIT_FILE : INTEGER := 0;
C_INIT_FILE_NAME : STRING := "";
C_INIT_FILE : STRING := "";
C_USE_DEFAULT_DATA : INTEGER := 0;
C_DEFAULT_DATA : STRING := "";
C_RST_TYPE : STRING := "SYNC";
C_HAS_RSTA : INTEGER := 0;
C_RST_PRIORITY_A : STRING := "CE";
C_RSTRAM_A : INTEGER := 0;
C_INITA_VAL : STRING := "";
C_HAS_ENA : INTEGER := 1;
C_HAS_REGCEA : INTEGER := 0;
C_USE_BYTE_WEA : INTEGER := 0;
C_WEA_WIDTH : INTEGER := 1;
C_WRITE_MODE_A : STRING := "WRITE_FIRST";
C_WRITE_WIDTH_A : INTEGER := 32;
C_READ_WIDTH_A : INTEGER := 32;
C_WRITE_DEPTH_A : INTEGER := 64;
C_READ_DEPTH_A : INTEGER := 64;
C_ADDRA_WIDTH : INTEGER := 6;
C_HAS_RSTB : INTEGER := 0;
C_RST_PRIORITY_B : STRING := "CE";
C_RSTRAM_B : INTEGER := 0;
C_INITB_VAL : STRING := "";
C_HAS_ENB : INTEGER := 1;
C_HAS_REGCEB : INTEGER := 0;
C_USE_BYTE_WEB : INTEGER := 0;
C_WEB_WIDTH : INTEGER := 1;
C_WRITE_MODE_B : STRING := "WRITE_FIRST";
C_WRITE_WIDTH_B : INTEGER := 32;
C_READ_WIDTH_B : INTEGER := 32;
C_WRITE_DEPTH_B : INTEGER := 64;
C_READ_DEPTH_B : INTEGER := 64;
C_ADDRB_WIDTH : INTEGER := 6;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER := 0;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER := 0;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER := 0;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER := 0;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER := 0;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER := 0;
C_MUX_PIPELINE_STAGES : INTEGER := 0;
C_USE_SOFTECC : INTEGER := 0;
C_USE_ECC : INTEGER := 0;
C_HAS_INJECTERR : INTEGER := 0;
C_SIM_COLLISION_CHECK : STRING := "NONE";
C_COMMON_CLK : INTEGER := 1;
FLOP_DELAY : TIME := 100 ps;
C_DISABLE_WARN_BHV_COLL : INTEGER := 0;
C_EN_ECC_PIPE : INTEGER := 0;
C_DISABLE_WARN_BHV_RANGE : INTEGER := 0
);
PORT (
CLKA : IN STD_LOGIC := '0';
RSTA : IN STD_LOGIC := '0';
ENA : IN STD_LOGIC := '1';
REGCEA : IN STD_LOGIC := '1';
WEA : IN STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
ADDRA : IN STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0):= (OTHERS => '0');
DINA : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0)
:= (OTHERS => '0');
DOUTA : OUT STD_LOGIC_VECTOR(C_READ_WIDTH_A-1 DOWNTO 0);
CLKB : IN STD_LOGIC := '0';
RSTB : IN STD_LOGIC := '0';
ENB : IN STD_LOGIC := '1';
REGCEB : IN STD_LOGIC := '1';
WEB : IN STD_LOGIC_VECTOR(C_WEB_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
ADDRB : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
DINB : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0)
:= (OTHERS => '0');
DOUTB : OUT STD_LOGIC_VECTOR(C_READ_WIDTH_B-1 DOWNTO 0);
INJECTSBITERR : IN STD_LOGIC := '0';
INJECTDBITERR : IN STD_LOGIC := '0';
SBITERR : OUT STD_LOGIC;
DBITERR : OUT STD_LOGIC;
ECCPIPECE : IN STD_LOGIC;
SLEEP : IN STD_LOGIC;
RDADDRECC : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0)
);
END blk_mem_gen_v8_3_0_mem_module;
--******************************
-- Port and Generic Definitions
--******************************
---------------------------------------------------------------------------
-- Generic Definitions
---------------------------------------------------------------------------
-- C_CORENAME : Instance name of the Block Memory Generator core
-- C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following
-- options are available - "spartan3", "spartan6",
-- "virtex4", "virtex5", "virtex6l" and "virtex6".
-- C_MEM_TYPE : Designates memory type.
-- It can be
-- 0 - Single Port Memory
-- 1 - Simple Dual Port Memory
-- 2 - True Dual Port Memory
-- 3 - Single Port Read Only Memory
-- 4 - Dual Port Read Only Memory
-- C_BYTE_SIZE : Size of a byte (8 or 9 bits)
-- C_ALGORITHM : Designates the algorithm method used
-- for constructing the memory.
-- It can be Fixed_Primitives, Minimum_Area or
-- Low_Power
-- C_PRIM_TYPE : Designates the user selected primitive used to
-- construct the memory.
--
-- C_LOAD_INIT_FILE : Designates the use of an initialization file to
-- initialize memory contents.
-- C_INIT_FILE_NAME : Memory initialization file name.
-- C_USE_DEFAULT_DATA : Designates whether to fill remaining
-- initialization space with default data
-- C_DEFAULT_DATA : Default value of all memory locations
-- not initialized by the memory
-- initialization file.
-- C_RST_TYPE : Type of reset - Synchronous or Asynchronous
--
-- C_HAS_RSTA : Determines the presence of the RSTA port
-- C_RST_PRIORITY_A : Determines the priority between CE and SR for
-- Port A.
-- C_RSTRAM_A : Determines if special reset behavior is used for
-- Port A
-- C_INITA_VAL : The initialization value for Port A
-- C_HAS_ENA : Determines the presence of the ENA port
-- C_HAS_REGCEA : Determines the presence of the REGCEA port
-- C_USE_BYTE_WEA : Determines if the Byte Write is used or not.
-- C_WEA_WIDTH : The width of the WEA port
-- C_WRITE_MODE_A : Configurable write mode for Port A. It can be
-- WRITE_FIRST, READ_FIRST or NO_CHANGE.
-- C_WRITE_WIDTH_A : Memory write width for Port A.
-- C_READ_WIDTH_A : Memory read width for Port A.
-- C_WRITE_DEPTH_A : Memory write depth for Port A.
-- C_READ_DEPTH_A : Memory read depth for Port A.
-- C_ADDRA_WIDTH : Width of the ADDRA input port
-- C_HAS_RSTB : Determines the presence of the RSTB port
-- C_RST_PRIORITY_B : Determines the priority between CE and SR for
-- Port B.
-- C_RSTRAM_B : Determines if special reset behavior is used for
-- Port B
-- C_INITB_VAL : The initialization value for Port B
-- C_HAS_ENB : Determines the presence of the ENB port
-- C_HAS_REGCEB : Determines the presence of the REGCEB port
-- C_USE_BYTE_WEB : Determines if the Byte Write is used or not.
-- C_WEB_WIDTH : The width of the WEB port
-- C_WRITE_MODE_B : Configurable write mode for Port B. It can be
-- WRITE_FIRST, READ_FIRST or NO_CHANGE.
-- C_WRITE_WIDTH_B : Memory write width for Port B.
-- C_READ_WIDTH_B : Memory read width for Port B.
-- C_WRITE_DEPTH_B : Memory write depth for Port B.
-- C_READ_DEPTH_B : Memory read depth for Port B.
-- C_ADDRB_WIDTH : Width of the ADDRB input port
-- C_HAS_MEM_OUTPUT_REGS_A : Designates the use of a register at the output
-- of the RAM primitive for Port A.
-- C_HAS_MEM_OUTPUT_REGS_B : Designates the use of a register at the output
-- of the RAM primitive for Port B.
-- C_HAS_MUX_OUTPUT_REGS_A : Designates the use of a register at the output
-- of the MUX for Port A.
-- C_HAS_MUX_OUTPUT_REGS_B : Designates the use of a register at the output
-- of the MUX for Port B.
-- C_MUX_PIPELINE_STAGES : Designates the number of pipeline stages in
-- between the muxes.
-- C_USE_SOFTECC : Determines if the Soft ECC feature is used or
-- not. Only applicable Spartan-6
-- C_USE_ECC : Determines if the ECC feature is used or
-- not. Only applicable for V5 and V6
-- C_HAS_INJECTERR : Determines if the error injection pins
-- are present or not. If the ECC feature
-- is not used, this value is defaulted to
-- 0, else the following are the allowed
-- values:
-- 0 : No INJECTSBITERR or INJECTDBITERR pins
-- 1 : Only INJECTSBITERR pin exists
-- 2 : Only INJECTDBITERR pin exists
-- 3 : Both INJECTSBITERR and INJECTDBITERR pins exist
-- C_SIM_COLLISION_CHECK : Controls the disabling of Unisim model collision
-- warnings. It can be "ALL", "NONE",
-- "Warnings_Only" or "Generate_X_Only".
-- C_COMMON_CLK : Determins if the core has a single CLK input.
-- C_DISABLE_WARN_BHV_COLL : Controls the Behavioral Model Collision warnings
-- C_DISABLE_WARN_BHV_RANGE: Controls the Behavioral Model Out of Range
-- warnings
---------------------------------------------------------------------------
-- Port Definitions
---------------------------------------------------------------------------
-- CLKA : Clock to synchronize all read and write operations of Port A.
-- RSTA : Reset input to reset memory outputs to a user-defined
-- reset state for Port A.
-- ENA : Enable all read and write operations of Port A.
-- REGCEA : Register Clock Enable to control each pipeline output
-- register stages for Port A.
-- WEA : Write Enable to enable all write operations of Port A.
-- ADDRA : Address of Port A.
-- DINA : Data input of Port A.
-- DOUTA : Data output of Port A.
-- CLKB : Clock to synchronize all read and write operations of Port B.
-- RSTB : Reset input to reset memory outputs to a user-defined
-- reset state for Port B.
-- ENB : Enable all read and write operations of Port B.
-- REGCEB : Register Clock Enable to control each pipeline output
-- register stages for Port B.
-- WEB : Write Enable to enable all write operations of Port B.
-- ADDRB : Address of Port B.
-- DINB : Data input of Port B.
-- DOUTB : Data output of Port B.
-- INJECTSBITERR : Single Bit ECC Error Injection Pin.
-- INJECTDBITERR : Double Bit ECC Error Injection Pin.
-- SBITERR : Output signal indicating that a Single Bit ECC Error has been
-- detected and corrected.
-- DBITERR : Output signal indicating that a Double Bit ECC Error has been
-- detected.
-- RDADDRECC : Read Address Output signal indicating address at which an
-- ECC error has occurred.
---------------------------------------------------------------------------
ARCHITECTURE mem_module_behavioral OF blk_mem_gen_v8_3_0_mem_module IS
--****************************************
-- min/max constant functions
--****************************************
-- get_max
----------
function SLV_TO_INT(SLV: in std_logic_vector
) return integer is
variable int : integer;
begin
int := 0;
for i in SLV'high downto SLV'low loop
int := int * 2;
if SLV(i) = '1' then
int := int + 1;
end if;
end loop;
return int;
end;
FUNCTION get_max(a: INTEGER; b: INTEGER) RETURN INTEGER IS
BEGIN
IF (a > b) THEN
RETURN a;
ELSE
RETURN b;
END IF;
END FUNCTION;
-- get_min
----------
FUNCTION get_min(a: INTEGER; b: INTEGER) RETURN INTEGER IS
BEGIN
IF (a < b) THEN
RETURN a;
ELSE
RETURN b;
END IF;
END FUNCTION;
--***************************************************************
-- convert write_mode from STRING type for use in case statement
--***************************************************************
FUNCTION write_mode_to_vector(mode: STRING) RETURN STD_LOGIC_VECTOR IS
BEGIN
IF (mode = "NO_CHANGE") THEN
RETURN "10";
ELSIF (mode = "READ_FIRST") THEN
RETURN "01";
ELSE
RETURN "00"; -- WRITE_FIRST
END IF;
END FUNCTION;
--***************************************************************
-- convert hex STRING to STD_LOGIC_VECTOR
--***************************************************************
FUNCTION hex_to_std_logic_vector(
hex_str : STRING;
return_width : INTEGER)
RETURN STD_LOGIC_VECTOR IS
VARIABLE tmp : STD_LOGIC_VECTOR((hex_str'LENGTH*4)+return_width-1
DOWNTO 0);
BEGIN
tmp := (OTHERS => '0');
FOR i IN 1 TO hex_str'LENGTH LOOP
CASE hex_str((hex_str'LENGTH+1)-i) IS
WHEN '0' => tmp(i*4-1 DOWNTO (i-1)*4) := "0000";
WHEN '1' => tmp(i*4-1 DOWNTO (i-1)*4) := "0001";
WHEN '2' => tmp(i*4-1 DOWNTO (i-1)*4) := "0010";
WHEN '3' => tmp(i*4-1 DOWNTO (i-1)*4) := "0011";
WHEN '4' => tmp(i*4-1 DOWNTO (i-1)*4) := "0100";
WHEN '5' => tmp(i*4-1 DOWNTO (i-1)*4) := "0101";
WHEN '6' => tmp(i*4-1 DOWNTO (i-1)*4) := "0110";
WHEN '7' => tmp(i*4-1 DOWNTO (i-1)*4) := "0111";
WHEN '8' => tmp(i*4-1 DOWNTO (i-1)*4) := "1000";
WHEN '9' => tmp(i*4-1 DOWNTO (i-1)*4) := "1001";
WHEN 'a' | 'A' => tmp(i*4-1 DOWNTO (i-1)*4) := "1010";
WHEN 'b' | 'B' => tmp(i*4-1 DOWNTO (i-1)*4) := "1011";
WHEN 'c' | 'C' => tmp(i*4-1 DOWNTO (i-1)*4) := "1100";
WHEN 'd' | 'D' => tmp(i*4-1 DOWNTO (i-1)*4) := "1101";
WHEN 'e' | 'E' => tmp(i*4-1 DOWNTO (i-1)*4) := "1110";
WHEN 'f' | 'F' => tmp(i*4-1 DOWNTO (i-1)*4) := "1111";
WHEN OTHERS => tmp(i*4-1 DOWNTO (i-1)*4) := "1111";
END CASE;
END LOOP;
RETURN tmp(return_width-1 DOWNTO 0);
END hex_to_std_logic_vector;
--***************************************************************
-- convert bit to STD_LOGIC
--***************************************************************
FUNCTION bit_to_sl(input: BIT) RETURN STD_LOGIC IS
VARIABLE temp_return : STD_LOGIC;
BEGIN
IF (input = '0') THEN
temp_return := '0';
ELSE
temp_return := '1';
END IF;
RETURN temp_return;
END bit_to_sl;
--***************************************************************
-- locally derived constants to determine memory shape
--***************************************************************
CONSTANT MIN_WIDTH_A : INTEGER := get_min(C_WRITE_WIDTH_A, C_READ_WIDTH_A);
CONSTANT MIN_WIDTH_B : INTEGER := get_min(C_WRITE_WIDTH_B,C_READ_WIDTH_B);
CONSTANT MIN_WIDTH : INTEGER := get_min(MIN_WIDTH_A, MIN_WIDTH_B);
CONSTANT MAX_DEPTH_A : INTEGER := get_max(C_WRITE_DEPTH_A, C_READ_DEPTH_A);
CONSTANT MAX_DEPTH_B : INTEGER := get_max(C_WRITE_DEPTH_B, C_READ_DEPTH_B);
CONSTANT MAX_DEPTH : INTEGER := get_max(MAX_DEPTH_A, MAX_DEPTH_B);
TYPE int_array IS ARRAY (MAX_DEPTH-1 DOWNTO 0) OF std_logic_vector(C_WRITE_WIDTH_A-1 DOWNTO 0);
TYPE mem_array IS ARRAY (MAX_DEPTH-1 DOWNTO 0) OF STD_LOGIC_VECTOR(MIN_WIDTH-1 DOWNTO 0);
TYPE ecc_err_array IS ARRAY (MAX_DEPTH-1 DOWNTO 0) OF STD_LOGIC;
TYPE softecc_err_array IS ARRAY (MAX_DEPTH-1 DOWNTO 0) OF STD_LOGIC;
--***************************************************************
-- memory initialization function
--***************************************************************
IMPURE FUNCTION init_memory(DEFAULT_DATA :
STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0);
write_width_a : INTEGER;
depth : INTEGER;
width : INTEGER)
RETURN mem_array IS
VARIABLE init_return : mem_array := (OTHERS => (OTHERS => '0'));
FILE init_file : TEXT;
VARIABLE mem_vector : BIT_VECTOR(write_width_a-1 DOWNTO 0);
VARIABLE int_mem_vector : int_array:= (OTHERS => (OTHERS => '0'));
VARIABLE file_buffer : LINE;
VARIABLE i : INTEGER := 0;
VARIABLE j : INTEGER;
VARIABLE k : INTEGER;
VARIABLE ignore_line : BOOLEAN := false;
VARIABLE good_data : BOOLEAN := false;
VARIABLE char_tmp : CHARACTER;
VARIABLE index : INTEGER;
variable init_addr_slv : std_logic_vector(31 downto 0) := (others => '0');
variable data : std_logic_vector(255 downto 0) := (others => '0');
variable inside_init_addr_slv : std_logic_vector(31 downto 0) := (others => '0');
variable k_slv : std_logic_vector(31 downto 0) := (others => '0');
variable i_slv : std_logic_vector(31 downto 0) := (others => '0');
VARIABLE disp_line : line := null;
variable open_status : file_open_status;
variable input_initf_tmp : mem_array ;
variable input_initf : mem_array := (others => (others => '0'));
file int_infile : text;
variable data_line, data_line_tmp, out_data_line : line;
variable slv_width : integer;
VARIABLE d_l : LINE;
BEGIN
--Display output message indicating that the behavioral model is being
--initialized
-- Setup the default data
-- Default data is with respect to write_port_A and may be wider
-- or narrower than init_return width. The following loops map
-- default data into the memory
IF (C_USE_DEFAULT_DATA=1) THEN
index := 0;
FOR i IN 0 TO depth-1 LOOP
FOR j IN 0 TO width-1 LOOP
init_return(i)(j) := DEFAULT_DATA(index);
index := (index + 1) MOD C_WRITE_WIDTH_A;
END LOOP;
END LOOP;
END IF;
-- Read in the .mif file
-- The init data is formatted with respect to write port A dimensions.
-- The init_return vector is formatted with respect to minimum width and
-- maximum depth; the following loops map the .mif file into the memory
IF (C_LOAD_INIT_FILE=1) THEN
file_open(init_file, C_INIT_FILE_NAME, read_mode);
i := 0;
WHILE (i < depth AND NOT endfile(init_file)) LOOP
mem_vector := (OTHERS => '0');
readline(init_file, file_buffer);
read(file_buffer, mem_vector(file_buffer'LENGTH-1 DOWNTO 0));
FOR j IN 0 TO write_width_a-1 LOOP
IF (j MOD width = 0 AND j /= 0) THEN
i := i + 1;
END IF;
init_return(i)(j MOD width) := bit_to_sl(mem_vector(j));
END LOOP;
i := i + 1;
END LOOP;
file_close(init_file);
END IF;
--Display output message indicating that the behavioral model is done
--initializing
ASSERT (NOT (C_USE_DEFAULT_DATA=1 OR C_LOAD_INIT_FILE=1)) REPORT " Block Memory Generator data initialization complete." SEVERITY NOTE;
if (C_USE_BRAM_BLOCK = 1) then
--Display output message indicating that the behavioral model is being
--initialized
-- Read in the .mem file
-- The init data is formatted with respect to write port A dimensions.
-- The init_return vector is formatted with respect to minimum width and
-- maximum depth; the following loops map the .mif file into the memory
IF (C_INIT_FILE /= "NONE") then
file_open(open_status, int_infile, C_INIT_FILE, read_mode);
while not endfile(int_infile) loop
readline(int_infile, data_line);
while (data_line /= null and data_line'length > 0) loop
if (data_line(data_line'low to data_line'low + 1) = "//") then
deallocate(data_line);
elsif ((data_line(data_line'low to data_line'low + 1) = "/*") and (data_line(data_line'high-1 to data_line'high) = "*/")) then
deallocate(data_line);
elsif (data_line(data_line'low to data_line'low + 1) = "/*") then
deallocate(data_line);
ignore_line := true;
elsif (ignore_line = true and data_line(data_line'high-1 to data_line'high) = "*/") then
deallocate(data_line);
ignore_line := false;
elsif (ignore_line = false and data_line(data_line'low) = '@') then
read(data_line, char_tmp);
hread(data_line, init_addr_slv, good_data);
i := SLV_TO_INT(init_addr_slv);
elsif (ignore_line = false) then
hread(data_line, input_initf_tmp(i), good_data);
init_return(i)(write_width_a - 1 downto 0) := input_initf_tmp(i)(write_width_a - 1 downto 0);
if (good_data = true) then
i := i + 1;
end if;
else
deallocate(data_line);
end if;
end loop;
end loop;
file_close(int_infile);
END IF;
END IF;
RETURN init_return;
END FUNCTION;
--***************************************************************
-- memory type constants
--***************************************************************
CONSTANT MEM_TYPE_SP_RAM : INTEGER := 0;
CONSTANT MEM_TYPE_SDP_RAM : INTEGER := 1;
CONSTANT MEM_TYPE_TDP_RAM : INTEGER := 2;
CONSTANT MEM_TYPE_SP_ROM : INTEGER := 3;
CONSTANT MEM_TYPE_DP_ROM : INTEGER := 4;
--***************************************************************
-- memory configuration constant functions
--***************************************************************
--get_single_port
-----------------
FUNCTION get_single_port(mem_type : INTEGER) RETURN INTEGER IS
BEGIN
IF (mem_type=MEM_TYPE_SP_RAM OR mem_type=MEM_TYPE_SP_ROM) THEN
RETURN 1;
ELSE
RETURN 0;
END IF;
END get_single_port;
--get_is_rom
--------------
FUNCTION get_is_rom(mem_type : INTEGER) RETURN INTEGER IS
BEGIN
IF (mem_type=MEM_TYPE_SP_ROM OR mem_type=MEM_TYPE_DP_ROM) THEN
RETURN 1;
ELSE
RETURN 0;
END IF;
END get_is_rom;
--get_has_a_write
------------------
FUNCTION get_has_a_write(IS_ROM : INTEGER) RETURN INTEGER IS
BEGIN
IF (IS_ROM=0) THEN
RETURN 1;
ELSE
RETURN 0;
END IF;
END get_has_a_write;
--get_has_b_write
------------------
FUNCTION get_has_b_write(mem_type : INTEGER) RETURN INTEGER IS
BEGIN
IF (mem_type=MEM_TYPE_TDP_RAM) THEN
RETURN 1;
ELSE
RETURN 0;
END IF;
END get_has_b_write;
--get_has_a_read
------------------
FUNCTION get_has_a_read(mem_type : INTEGER) RETURN INTEGER IS
BEGIN
IF (mem_type=MEM_TYPE_SDP_RAM) THEN
RETURN 0;
ELSE
RETURN 1;
END IF;
END get_has_a_read;
--get_has_b_read
------------------
FUNCTION get_has_b_read(SINGLE_PORT : INTEGER) RETURN INTEGER IS
BEGIN
IF (SINGLE_PORT=1) THEN
RETURN 0;
ELSE
RETURN 1;
END IF;
END get_has_b_read;
--get_has_b_port
------------------
FUNCTION get_has_b_port(HAS_B_READ : INTEGER;
HAS_B_WRITE : INTEGER)
RETURN INTEGER IS
BEGIN
IF (HAS_B_READ=1 OR HAS_B_WRITE=1) THEN
RETURN 1;
ELSE
RETURN 0;
END IF;
END get_has_b_port;
--get_num_output_stages
-----------------------
FUNCTION get_num_output_stages(has_mem_output_regs : INTEGER;
has_mux_output_regs : INTEGER;
mux_pipeline_stages : INTEGER)
RETURN INTEGER IS
VARIABLE actual_mux_pipeline_stages : INTEGER;
BEGIN
-- Mux pipeline stages can be non-zero only when there is a mux
-- output register.
IF (has_mux_output_regs=1) THEN
actual_mux_pipeline_stages := mux_pipeline_stages;
ELSE
actual_mux_pipeline_stages := 0;
END IF;
RETURN has_mem_output_regs+actual_mux_pipeline_stages+has_mux_output_regs;
END get_num_output_stages;
--***************************************************************************
-- Component declaration of the VARIABLE depth output register stage
--***************************************************************************
COMPONENT blk_mem_gen_v8_3_0_output_stage
GENERIC (
C_FAMILY : STRING := "virtex7";
C_XDEVICEFAMILY : STRING := "virtex7";
C_RST_TYPE : STRING := "SYNC";
C_HAS_RST : INTEGER := 0;
C_RSTRAM : INTEGER := 0;
C_RST_PRIORITY : STRING := "CE";
init_val : STD_LOGIC_VECTOR;
C_HAS_EN : INTEGER := 0;
C_HAS_REGCE : INTEGER := 0;
C_DATA_WIDTH : INTEGER := 32;
C_ADDRB_WIDTH : INTEGER := 10;
C_HAS_MEM_OUTPUT_REGS : INTEGER := 0;
C_USE_SOFTECC : INTEGER := 0;
C_USE_ECC : INTEGER := 0;
NUM_STAGES : INTEGER := 1;
C_EN_ECC_PIPE : INTEGER := 0;
FLOP_DELAY : TIME := 100 ps);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
REGCE : IN STD_LOGIC;
EN : IN STD_LOGIC;
DIN_I : IN STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
DOUT : OUT STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
SBITERR_IN_I : IN STD_LOGIC;
DBITERR_IN_I : IN STD_LOGIC;
SBITERR : OUT STD_LOGIC;
DBITERR : OUT STD_LOGIC;
RDADDRECC_IN_I : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0);
ECCPIPECE : IN STD_LOGIC;
RDADDRECC : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_3_0_output_stage;
COMPONENT blk_mem_gen_v8_3_0_softecc_output_reg_stage
GENERIC (
C_DATA_WIDTH : INTEGER := 32;
C_ADDRB_WIDTH : INTEGER := 10;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER := 0;
C_USE_SOFTECC : INTEGER := 0;
FLOP_DELAY : TIME := 100 ps
);
PORT (
CLK : IN STD_LOGIC;
DIN : IN STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
DOUT : OUT STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
SBITERR_IN : IN STD_LOGIC;
DBITERR_IN : IN STD_LOGIC;
SBITERR : OUT STD_LOGIC;
DBITERR : OUT STD_LOGIC;
RDADDRECC_IN : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0);
RDADDRECC : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_3_0_softecc_output_reg_stage;
--******************************************************
-- locally derived constants to assist memory access
--******************************************************
CONSTANT WRITE_WIDTH_RATIO_A : INTEGER := C_WRITE_WIDTH_A/MIN_WIDTH;
CONSTANT READ_WIDTH_RATIO_A : INTEGER := C_READ_WIDTH_A/MIN_WIDTH;
CONSTANT WRITE_WIDTH_RATIO_B : INTEGER := C_WRITE_WIDTH_B/MIN_WIDTH;
CONSTANT READ_WIDTH_RATIO_B : INTEGER := C_READ_WIDTH_B/MIN_WIDTH;
--******************************************************
-- To modify the LSBs of the 'wider' data to the actual
-- address value
--******************************************************
CONSTANT WRITE_ADDR_A_DIV : INTEGER := C_WRITE_WIDTH_A/MIN_WIDTH_A;
CONSTANT READ_ADDR_A_DIV : INTEGER := C_READ_WIDTH_A/MIN_WIDTH_A;
CONSTANT WRITE_ADDR_B_DIV : INTEGER := C_WRITE_WIDTH_B/MIN_WIDTH_B;
CONSTANT READ_ADDR_B_DIV : INTEGER := C_READ_WIDTH_B/MIN_WIDTH_B;
--******************************************************
-- FUNCTION : log2roundup
--******************************************************
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := 1;
BEGIN
IF (data_value <= 1) THEN
width := 0;
ELSE
WHILE (cnt < data_value) LOOP
width := width + 1;
cnt := cnt *2;
END LOOP;
END IF;
RETURN width;
END log2roundup;
-----------------------------------------------------------------------------
-- FUNCTION : log2int
-----------------------------------------------------------------------------
FUNCTION log2int (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := data_value;
BEGIN
WHILE (cnt >1) LOOP
width := width + 1;
cnt := cnt/2;
END LOOP;
RETURN width;
END log2int;
------------------------------------------------------------------------------
-- FUNCTION: if_then_else
-- This function is used to implement an IF..THEN when such a statement is not
-- allowed.
------------------------------------------------------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
VARIABLE retval : INTEGER := 0;
BEGIN
IF NOT condition THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
--******************************************************
-- Other constants and signals
--******************************************************
CONSTANT COLL_DELAY : TIME := 100 ps;
-- default data vector
CONSTANT DEFAULT_DATA : STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0)
:= hex_to_std_logic_vector(C_DEFAULT_DATA,
C_WRITE_WIDTH_A);
CONSTANT CHKBIT_WIDTH : INTEGER := if_then_else(C_WRITE_WIDTH_A>57,8,if_then_else(C_WRITE_WIDTH_A>26,7,if_then_else(C_WRITE_WIDTH_A>11,6,if_then_else(C_WRITE_WIDTH_A>4,5,if_then_else(C_WRITE_WIDTH_A<5,4,0)))));
-- the init memory SIGNAL
SIGNAL memory_i : mem_array;
SIGNAL doublebit_error_i : STD_LOGIC_VECTOR(C_WRITE_WIDTH_A+CHKBIT_WIDTH-1 DOWNTO 0);
SIGNAL current_contents_i : STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0);
-- write mode constants
CONSTANT WRITE_MODE_A : STD_LOGIC_VECTOR(1 DOWNTO 0) :=
write_mode_to_vector(C_WRITE_MODE_A);
CONSTANT WRITE_MODE_B : STD_LOGIC_VECTOR(1 DOWNTO 0) :=
write_mode_to_vector(C_WRITE_MODE_B);
CONSTANT WRITE_MODES : STD_LOGIC_VECTOR(3 DOWNTO 0) :=
WRITE_MODE_A & WRITE_MODE_B;
-- reset values
CONSTANT INITA_VAL : STD_LOGIC_VECTOR(C_READ_WIDTH_A-1 DOWNTO 0)
:= hex_to_std_logic_vector(C_INITA_VAL,
C_READ_WIDTH_A);
CONSTANT INITB_VAL : STD_LOGIC_VECTOR(C_READ_WIDTH_B-1 DOWNTO 0)
:= hex_to_std_logic_vector(C_INITB_VAL,
C_READ_WIDTH_B);
-- memory output 'latches'
SIGNAL memory_out_a : STD_LOGIC_VECTOR(C_READ_WIDTH_A-1 DOWNTO 0) :=
INITA_VAL;
SIGNAL memory_out_b : STD_LOGIC_VECTOR(C_READ_WIDTH_B-1 DOWNTO 0) :=
INITB_VAL;
SIGNAL sbiterr_in : STD_LOGIC := '0';
SIGNAL sbiterr_sdp : STD_LOGIC := '0';
SIGNAL dbiterr_in : STD_LOGIC := '0';
SIGNAL dbiterr_sdp : STD_LOGIC := '0';
SIGNAL rdaddrecc_in : STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL rdaddrecc_sdp : STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL doutb_i : STD_LOGIC_VECTOR(C_READ_WIDTH_B-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL rdaddrecc_i : STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL sbiterr_i : STD_LOGIC := '0';
SIGNAL dbiterr_i : STD_LOGIC := '0';
-- memory configuration constants
-----------------------------------------------
CONSTANT SINGLE_PORT : INTEGER := get_single_port(C_MEM_TYPE);
CONSTANT IS_ROM : INTEGER := get_is_rom(C_MEM_TYPE);
CONSTANT HAS_A_WRITE : INTEGER := get_has_a_write(IS_ROM);
CONSTANT HAS_B_WRITE : INTEGER := get_has_b_write(C_MEM_TYPE);
CONSTANT HAS_A_READ : INTEGER := get_has_a_read(C_MEM_TYPE);
CONSTANT HAS_B_READ : INTEGER := get_has_b_read(SINGLE_PORT);
CONSTANT HAS_B_PORT : INTEGER := get_has_b_port(HAS_B_READ, HAS_B_WRITE);
CONSTANT NUM_OUTPUT_STAGES_A : INTEGER :=
get_num_output_stages(C_HAS_MEM_OUTPUT_REGS_A, C_HAS_MUX_OUTPUT_REGS_A,
C_MUX_PIPELINE_STAGES);
CONSTANT NUM_OUTPUT_STAGES_B : INTEGER :=
get_num_output_stages(C_HAS_MEM_OUTPUT_REGS_B, C_HAS_MUX_OUTPUT_REGS_B,
C_MUX_PIPELINE_STAGES);
CONSTANT WEA0 : STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
CONSTANT WEB0 : STD_LOGIC_VECTOR(C_WEB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
-----------------------------------------------------------------------------
-- DEBUG CONTROL
-- DEBUG=0 : Debug output OFF
-- DEBUG=1 : Some debug info printed
-----------------------------------------------------------------------------
CONSTANT DEBUG : INTEGER := 0;
-- internal signals
-----------------------------------------------
SIGNAL ena_i : STD_LOGIC;
SIGNAL enb_i : STD_LOGIC;
SIGNAL reseta_i : STD_LOGIC;
SIGNAL resetb_i : STD_LOGIC;
SIGNAL wea_i : STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0);
SIGNAL web_i : STD_LOGIC_VECTOR(C_WEB_WIDTH-1 DOWNTO 0);
SIGNAL rea_i : STD_LOGIC;
SIGNAL reb_i : STD_LOGIC;
SIGNAL message_complete : BOOLEAN := false;
SIGNAL rsta_outp_stage : STD_LOGIC := '0';
SIGNAL rstb_outp_stage : STD_LOGIC := '0';
--*********************************************************
--FUNCTION : Collision check
--*********************************************************
FUNCTION collision_check (addr_a :
STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0);
iswrite_a : BOOLEAN;
addr_b :
STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0);
iswrite_b : BOOLEAN)
RETURN BOOLEAN IS
VARIABLE c_aw_bw : INTEGER;
VARIABLE c_aw_br : INTEGER;
VARIABLE c_ar_bw : INTEGER;
VARIABLE write_addr_a_width : INTEGER;
VARIABLE read_addr_a_width : INTEGER;
VARIABLE write_addr_b_width : INTEGER;
VARIABLE read_addr_b_width : INTEGER;
BEGIN
c_aw_bw := 0;
c_aw_br := 0;
c_ar_bw := 0;
-- Determine the effective address widths FOR each of the 4 ports
write_addr_a_width := C_ADDRA_WIDTH-log2roundup(WRITE_ADDR_A_DIV);
read_addr_a_width := C_ADDRA_WIDTH-log2roundup(READ_ADDR_A_DIV);
write_addr_b_width := C_ADDRB_WIDTH-log2roundup(WRITE_ADDR_B_DIV);
read_addr_b_width := C_ADDRB_WIDTH-log2roundup(READ_ADDR_B_DIV);
--Look FOR a write-write collision. In order FOR a write-write
--collision to exist, both ports must have a write transaction.
IF (iswrite_a AND iswrite_b) THEN
IF (write_addr_a_width > write_addr_b_width) THEN
--write_addr_b_width is smaller, so scale both addresses to that
-- width FOR comparing write_addr_a and write_addr_b
--addr_a starts as C_ADDRA_WIDTH,
-- scale it down to write_addr_b_width
--addr_b starts as C_ADDRB_WIDTH,
-- scale it down to write_addr_b_width
--Once both are scaled to write_addr_b_width, compare.
IF ((conv_integer(addr_a)/2**(C_ADDRA_WIDTH-write_addr_b_width)) =
(conv_integer(addr_b)/2**(C_ADDRB_WIDTH-write_addr_b_width))) THEN
c_aw_bw := 1;
ELSE
c_aw_bw := 0;
END IF;
ELSE
--write_addr_a_width is smaller, so scale both addresses to that
-- width FOR comparing write_addr_a and write_addr_b
--addr_a starts as C_ADDRA_WIDTH,
-- scale it down to write_addr_a_width
--addr_b starts as C_ADDRB_WIDTH,
-- scale it down to write_addr_a_width
--Once both are scaled to write_addr_a_width, compare.
IF ((conv_integer(addr_b)/2**(C_ADDRB_WIDTH-write_addr_a_width)) =
(conv_integer(addr_a)/2**(C_ADDRA_WIDTH-write_addr_a_width))) THEN
c_aw_bw := 1;
ELSE
c_aw_bw := 0;
END IF;
END IF; --width
END IF; --iswrite_a and iswrite_b
--If the B port is reading (which means it is enabled - so could be
-- a TX_WRITE or TX_READ), then check FOR a write-read collision).
--This could happen whether or not a write-write collision exists due
-- to asymmetric write/read ports.
IF (iswrite_a) THEN
IF (write_addr_a_width > read_addr_b_width) THEN
--read_addr_b_width is smaller, so scale both addresses to that
-- width FOR comparing write_addr_a and read_addr_b
--addr_a starts as C_ADDRA_WIDTH,
-- scale it down to read_addr_b_width
--addr_b starts as C_ADDRB_WIDTH,
-- scale it down to read_addr_b_width
--Once both are scaled to read_addr_b_width, compare.
IF ((conv_integer(addr_a)/2**(C_ADDRA_WIDTH-read_addr_b_width)) =
(conv_integer(addr_b)/2**(C_ADDRB_WIDTH-read_addr_b_width))) THEN
c_aw_br := 1;
ELSE
c_aw_br := 0;
END IF;
ELSE
--write_addr_a_width is smaller, so scale both addresses to that
-- width FOR comparing write_addr_a and read_addr_b
--addr_a starts as C_ADDRA_WIDTH,
-- scale it down to write_addr_a_width
--addr_b starts as C_ADDRB_WIDTH,
-- scale it down to write_addr_a_width
--Once both are scaled to write_addr_a_width, compare.
IF ((conv_integer(addr_b)/2**(C_ADDRB_WIDTH-write_addr_a_width)) =
(conv_integer(addr_a)/2**(C_ADDRA_WIDTH-write_addr_a_width))) THEN
c_aw_br := 1;
ELSE
c_aw_br := 0;
END IF;
END IF; --width
END IF; --iswrite_a
--If the A port is reading (which means it is enabled - so could be
-- a TX_WRITE or TX_READ), then check FOR a write-read collision).
--This could happen whether or not a write-write collision exists due
-- to asymmetric write/read ports.
IF (iswrite_b) THEN
IF (read_addr_a_width > write_addr_b_width) THEN
--write_addr_b_width is smaller, so scale both addresses to that
-- width FOR comparing read_addr_a and write_addr_b
--addr_a starts as C_ADDRA_WIDTH,
-- scale it down to write_addr_b_width
--addr_b starts as C_ADDRB_WIDTH,
-- scale it down to write_addr_b_width
--Once both are scaled to write_addr_b_width, compare.
IF ((conv_integer(addr_a)/2**(C_ADDRA_WIDTH-write_addr_b_width)) =
(conv_integer(addr_b)/2**(C_ADDRB_WIDTH-write_addr_b_width))) THEN
c_ar_bw := 1;
ELSE
c_ar_bw := 0;
END IF;
ELSE
--read_addr_a_width is smaller, so scale both addresses to that
-- width FOR comparing read_addr_a and write_addr_b
--addr_a starts as C_ADDRA_WIDTH,
-- scale it down to read_addr_a_width
--addr_b starts as C_ADDRB_WIDTH,
-- scale it down to read_addr_a_width
--Once both are scaled to read_addr_a_width, compare.
IF ((conv_integer(addr_b)/2**(C_ADDRB_WIDTH-read_addr_a_width)) =
(conv_integer(addr_a)/2**(C_ADDRA_WIDTH-read_addr_a_width))) THEN
c_ar_bw := 1;
ELSE
c_ar_bw := 0;
END IF;
END IF; --width
END IF; --iswrite_b
RETURN (c_aw_bw=1 OR c_aw_br=1 OR c_ar_bw=1);
END FUNCTION collision_check;
BEGIN -- Architecture
-----------------------------------------------------------------------------
-- SOFTECC and ECC SBITERR/DBITERR Outputs
-- The ECC Behavior is modeled by the behavioral models only for Virtex-6.
-- The SOFTECC Behavior is modeled by the behavioral models for Spartan-6.
-- For Virtex-5, these outputs will be tied to 0.
-----------------------------------------------------------------------------
SBITERR <= sbiterr_sdp WHEN ((C_MEM_TYPE = 1 AND C_USE_ECC = 1) OR C_USE_SOFTECC = 1) ELSE '0';
DBITERR <= dbiterr_sdp WHEN ((C_MEM_TYPE = 1 AND C_USE_ECC = 1) OR C_USE_SOFTECC = 1) ELSE '0';
RDADDRECC <= rdaddrecc_sdp WHEN (((C_FAMILY="virtex7") AND C_MEM_TYPE = 1 AND C_USE_ECC = 1) OR C_USE_SOFTECC = 1) ELSE (OTHERS => '0');
-----------------------------------------------
-- This effectively wires off optional inputs
-----------------------------------------------
ena_i <= ENA WHEN (C_HAS_ENA=1) ELSE '1';
enb_i <= ENB WHEN (C_HAS_ENB=1 AND HAS_B_PORT=1) ELSE '1';
-- We are doing an "AND" operation of WEA and ENA and passing to Enbale pin of BRAM when built-in ECC is enabled,
-- what this means is that the write operation happens only when both WEA and ENA are high.
wea_i <= WEA WHEN (HAS_A_WRITE=1 AND ena_i='1') ELSE WEA0;
-- wea_i <= (OTHERS => '1') WHEN (HAS_A_WRITE=1 AND C_MEM_TYPE = 1 AND C_USE_ECC = 1 AND C_HAS_ENA=1 AND ENA = '1') ELSE -- Use_ENA_pin
-- WEA WHEN (HAS_A_WRITE=1 AND C_MEM_TYPE = 1 AND C_USE_ECC = 1 AND C_HAS_ENA=0) ELSE -- Always_enabled
-- WEA WHEN (HAS_A_WRITE=1 AND ena_i='1' AND C_USE_ECC = 0) ELSE
-- WEA0;
web_i <= WEB WHEN (HAS_B_WRITE=1 AND enb_i='1') ELSE WEB0;
rea_i <= ena_i WHEN (HAS_A_READ=1) ELSE '0';
reb_i <= enb_i WHEN (HAS_B_READ=1) ELSE '0';
-- these signals reset the memory latches
-- For the special reset behaviors in some of the families, the C_RSTRAM
-- attribute of the corresponding port is used to indicate if the latch is
-- reset or not.
reseta_i <= RSTA WHEN
((C_HAS_RSTA=1 AND NUM_OUTPUT_STAGES_A=0) OR
(C_HAS_RSTA=1 AND C_RSTRAM_A=1))
ELSE '0';
resetb_i <= RSTB WHEN
((C_HAS_RSTB=1 AND NUM_OUTPUT_STAGES_B=0) OR
(C_HAS_RSTB=1 AND C_RSTRAM_B=1) )
ELSE '0';
--***************************************************************************
-- This is the main PROCESS which includes the memory VARIABLE and the read
-- and write procedures. It also schedules read and write operations
--***************************************************************************
PROCESS (CLKA, CLKB,rea_i,reb_i,reseta_i,resetb_i)
-- Initialize the init memory array
------------------------------------
VARIABLE memory : mem_array := init_memory(DEFAULT_DATA,
C_WRITE_WIDTH_A,
MAX_DEPTH,
MIN_WIDTH);
-- Initialize the mem memory array
------------------------------------
VARIABLE softecc_sbiterr_arr : softecc_err_array;
VARIABLE softecc_dbiterr_arr : softecc_err_array;
VARIABLE sbiterr_arr : ecc_err_array;
VARIABLE dbiterr_arr : ecc_err_array;
CONSTANT doublebit_lsb : STD_LOGIC_VECTOR (1 DOWNTO 0):="11";
CONSTANT doublebit_msb : STD_LOGIC_VECTOR (C_WRITE_WIDTH_A+CHKBIT_WIDTH-3 DOWNTO 0):= (OTHERS => '0');
VARIABLE doublebit_error : STD_LOGIC_VECTOR(C_WRITE_WIDTH_A+CHKBIT_WIDTH-1 DOWNTO 0) := doublebit_msb & doublebit_lsb ;
VARIABLE current_contents_var : STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0);
--***********************************
-- procedures to access the memory
--***********************************
-- write_a
----------
PROCEDURE write_a
(addr : IN STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0);
byte_en : IN STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0);
data : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0);
inj_sbiterr : IN STD_LOGIC;
inj_dbiterr : IN STD_LOGIC) IS
VARIABLE current_contents : STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0);
VARIABLE address_i : INTEGER;
VARIABLE i : INTEGER;
VARIABLE message : LINE;
VARIABLE errbit_current_contents : STD_LOGIC_VECTOR(1 DOWNTO 0);
BEGIN
-- Block Memory Generator non-cycle-accurate message
ASSERT (message_complete) REPORT "Block Memory Generator module is using a behavioral model FOR simulation which will not precisely model memory collision behavior."
SEVERITY NOTE;
message_complete <= true;
-- Shift the address by the ratio
address_i := (conv_integer(addr)/WRITE_ADDR_A_DIV);
IF (address_i >= C_WRITE_DEPTH_A) THEN
IF (C_DISABLE_WARN_BHV_RANGE = 0) THEN
ASSERT FALSE
REPORT C_CORENAME & " WARNING: Address " &
INTEGER'IMAGE(conv_integer(addr)) & " is outside range FOR A Write"
SEVERITY WARNING;
END IF;
-- valid address
ELSE
-- Combine w/ byte writes
IF (C_USE_BYTE_WEA = 1) THEN
-- Get the current memory contents
FOR i IN 0 TO WRITE_WIDTH_RATIO_A-1 LOOP
current_contents(MIN_WIDTH*(i+1)-1 DOWNTO MIN_WIDTH*i)
:= memory(address_i*WRITE_WIDTH_RATIO_A + i);
END LOOP;
-- Apply incoming bytes
FOR i IN 0 TO C_WEA_WIDTH-1 LOOP
IF (byte_en(i) = '1') THEN
current_contents(C_BYTE_SIZE*(i+1)-1 DOWNTO C_BYTE_SIZE*i)
:= data(C_BYTE_SIZE*(i+1)-1 DOWNTO C_BYTE_SIZE*i);
END IF;
END LOOP;
-- No byte-writes, overwrite the whole word
ELSE
current_contents := data;
END IF;
-- Insert double bit errors:
IF (C_USE_ECC = 1) THEN
IF ((C_HAS_INJECTERR = 2 OR C_HAS_INJECTERR = 3) AND inj_dbiterr = '1') THEN
current_contents(0) := NOT(current_contents(0));
current_contents(1) := NOT(current_contents(1));
--current_contents(0) := NOT(current_contents(30));
--current_contents(1) := NOT(current_contents(62));
END IF;
END IF;
-- Insert double bit errors:
IF (C_USE_SOFTECC=1) THEN
IF ((C_HAS_INJECTERR = 2 OR C_HAS_INJECTERR = 3) AND inj_dbiterr = '1') THEN
doublebit_error(C_WRITE_WIDTH_A+CHKBIT_WIDTH-1 downto 2) := doublebit_error(C_WRITE_WIDTH_A+CHKBIT_WIDTH-3 downto 0);
doublebit_error(0) := doublebit_error(C_WRITE_WIDTH_A+CHKBIT_WIDTH-1);
doublebit_error(1) := doublebit_error(C_WRITE_WIDTH_A+CHKBIT_WIDTH-2);
current_contents := current_contents XOR doublebit_error(C_WRITE_WIDTH_A-1 DOWNTO 0);
END IF;
END IF;
IF(DEBUG=1) THEN
current_contents_var := current_contents; --for debugging current
END IF;
-- Write data to memory
FOR i IN 0 TO WRITE_WIDTH_RATIO_A-1 LOOP
memory(address_i*WRITE_WIDTH_RATIO_A + i) :=
current_contents(MIN_WIDTH*(i+1)-1 DOWNTO MIN_WIDTH*i);
END LOOP;
-- Store address at which error is injected:
IF ((C_FAMILY = "virtex7") AND C_USE_ECC = 1) THEN
IF ((C_HAS_INJECTERR = 1 AND inj_sbiterr = '1') OR (C_HAS_INJECTERR = 3 AND inj_sbiterr = '1' AND inj_dbiterr /= '1')) THEN
sbiterr_arr(address_i) := '1';
ELSE
sbiterr_arr(address_i) := '0';
END IF;
IF ((C_HAS_INJECTERR = 2 OR C_HAS_INJECTERR = 3) AND inj_dbiterr = '1') THEN
dbiterr_arr(address_i) := '1';
ELSE
dbiterr_arr(address_i) := '0';
END IF;
END IF;
-- Store address at which softecc error is injected:
IF (C_USE_SOFTECC = 1) THEN
IF ((C_HAS_INJECTERR = 1 AND inj_sbiterr = '1') OR (C_HAS_INJECTERR = 3 AND inj_sbiterr = '1' AND inj_dbiterr /= '1')) THEN
softecc_sbiterr_arr(address_i) := '1';
ELSE
softecc_sbiterr_arr(address_i) := '0';
END IF;
IF ((C_HAS_INJECTERR = 2 OR C_HAS_INJECTERR = 3) AND inj_dbiterr = '1') THEN
softecc_dbiterr_arr(address_i) := '1';
ELSE
softecc_dbiterr_arr(address_i) := '0';
END IF;
END IF;
END IF;
END PROCEDURE;
-- write_b
----------
PROCEDURE write_b
(addr : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0);
byte_en : IN STD_LOGIC_VECTOR(C_WEB_WIDTH-1 DOWNTO 0);
data : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0)) IS
VARIABLE current_contents : STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0);
VARIABLE address_i : INTEGER;
VARIABLE i : INTEGER;
BEGIN
-- Shift the address by the ratio
address_i := (conv_integer(addr)/WRITE_ADDR_B_DIV);
IF (address_i >= C_WRITE_DEPTH_B) THEN
IF (C_DISABLE_WARN_BHV_RANGE = 0) THEN
ASSERT FALSE
REPORT C_CORENAME & " WARNING: Address " &
INTEGER'IMAGE(conv_integer(addr)) & " is outside range for B Write"
SEVERITY WARNING;
END IF;
-- valid address
ELSE
-- Combine w/ byte writes
IF (C_USE_BYTE_WEB = 1) THEN
-- Get the current memory contents
FOR i IN 0 TO WRITE_WIDTH_RATIO_B-1 LOOP
current_contents(MIN_WIDTH*(i+1)-1 DOWNTO MIN_WIDTH*i)
:= memory(address_i*WRITE_WIDTH_RATIO_B + i);
END LOOP;
-- Apply incoming bytes
FOR i IN 0 TO C_WEB_WIDTH-1 LOOP
IF (byte_en(i) = '1') THEN
current_contents(C_BYTE_SIZE*(i+1)-1 DOWNTO C_BYTE_SIZE*i)
:= data(C_BYTE_SIZE*(i+1)-1 DOWNTO C_BYTE_SIZE*i);
END IF;
END LOOP;
-- No byte-writes, overwrite the whole word
ELSE
current_contents := data;
END IF;
-- Write data to memory
FOR i IN 0 TO WRITE_WIDTH_RATIO_B-1 LOOP
memory(address_i*WRITE_WIDTH_RATIO_B + i) :=
current_contents(MIN_WIDTH*(i+1)-1 DOWNTO MIN_WIDTH*i);
END LOOP;
END IF;
END PROCEDURE;
-- read_a
----------
PROCEDURE read_a
(addr : IN STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0);
reset : IN STD_LOGIC) IS
VARIABLE address_i : INTEGER;
VARIABLE i : INTEGER;
BEGIN
IF (reset = '1') THEN
memory_out_a <= INITA_VAL AFTER FLOP_DELAY;
ELSE
-- Shift the address by the ratio
address_i := (conv_integer(addr)/READ_ADDR_A_DIV);
IF (address_i >= C_READ_DEPTH_A) THEN
IF (C_DISABLE_WARN_BHV_RANGE=0) THEN
ASSERT FALSE
REPORT C_CORENAME & " WARNING: Address " &
INTEGER'IMAGE(conv_integer(addr)) & " is outside range for A Read"
SEVERITY WARNING;
END IF;
memory_out_a <= (OTHERS => 'X') AFTER FLOP_DELAY;
-- valid address
ELSE
-- Increment through the 'partial' words in the memory
FOR i IN 0 TO READ_WIDTH_RATIO_A-1 LOOP
memory_out_a(MIN_WIDTH*(i+1)-1 DOWNTO MIN_WIDTH*i) <=
memory(address_i*READ_WIDTH_RATIO_A + i) AFTER FLOP_DELAY;
END LOOP;
END IF;
END IF;
END PROCEDURE;
-- read_b
----------
PROCEDURE read_b
(addr : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0);
reset : IN STD_LOGIC) IS
VARIABLE address_i : INTEGER;
VARIABLE i : INTEGER;
BEGIN
IF (reset = '1') THEN
memory_out_b <= INITB_VAL AFTER FLOP_DELAY;
sbiterr_in <= '0' AFTER FLOP_DELAY;
dbiterr_in <= '0' AFTER FLOP_DELAY;
rdaddrecc_in <= (OTHERS => '0') AFTER FLOP_DELAY;
ELSE
-- Shift the address by the ratio
address_i := (conv_integer(addr)/READ_ADDR_B_DIV);
IF (address_i >= C_READ_DEPTH_B) THEN
IF (C_DISABLE_WARN_BHV_RANGE=0) THEN
ASSERT FALSE
REPORT C_CORENAME & " WARNING: Address " &
INTEGER'IMAGE(conv_integer(addr)) & " is outside range for B Read"
SEVERITY WARNING;
END IF;
memory_out_b <= (OTHERS => 'X') AFTER FLOP_DELAY;
sbiterr_in <= 'X' AFTER FLOP_DELAY;
dbiterr_in <= 'X' AFTER FLOP_DELAY;
rdaddrecc_in <= (OTHERS => 'X') AFTER FLOP_DELAY;
-- valid address
ELSE
-- Increment through the 'partial' words in the memory
FOR i IN 0 TO READ_WIDTH_RATIO_B-1 LOOP
memory_out_b(MIN_WIDTH*(i+1)-1 DOWNTO MIN_WIDTH*i) <=
memory(address_i*READ_WIDTH_RATIO_B + i) AFTER FLOP_DELAY;
END LOOP;
--assert sbiterr and dbiterr signals
IF ((C_FAMILY="virtex7") AND C_USE_ECC = 1) THEN
rdaddrecc_in <= addr AFTER FLOP_DELAY;
IF (sbiterr_arr(address_i) = '1') THEN
sbiterr_in <= '1' AFTER FLOP_DELAY;
ELSE
sbiterr_in <= '0' AFTER FLOP_DELAY;
END IF;
IF (dbiterr_arr(address_i) = '1') THEN
dbiterr_in <= '1' AFTER FLOP_DELAY;
ELSE
dbiterr_in <= '0' AFTER FLOP_DELAY;
END IF;
--assert softecc sbiterr and dbiterr signals
ELSIF (C_USE_SOFTECC = 1) THEN
rdaddrecc_in <= addr AFTER FLOP_DELAY;
IF (softecc_sbiterr_arr(address_i) = '1') THEN
sbiterr_in <= '1' AFTER FLOP_DELAY;
ELSE
sbiterr_in <= '0' AFTER FLOP_DELAY;
END IF;
IF (softecc_dbiterr_arr(address_i) = '1') THEN
dbiterr_in <= '1' AFTER FLOP_DELAY;
ELSE
dbiterr_in <= '0' AFTER FLOP_DELAY;
END IF;
ELSE
sbiterr_in <= '0' AFTER FLOP_DELAY;
dbiterr_in <= '0' AFTER FLOP_DELAY;
rdaddrecc_in <= (OTHERS => '0') AFTER FLOP_DELAY;
END IF;
END IF;
END IF;
END PROCEDURE;
-- reset_a
----------
PROCEDURE reset_a
(reset : IN STD_LOGIC) IS
BEGIN
IF (reset = '1') THEN
memory_out_a <= INITA_VAL AFTER FLOP_DELAY;
END IF;
END PROCEDURE;
-- reset_b
----------
PROCEDURE reset_b
(reset : IN STD_LOGIC) IS
BEGIN
IF (reset = '1') THEN
memory_out_b <= INITB_VAL AFTER FLOP_DELAY;
END IF;
END PROCEDURE;
BEGIN -- begin the main PROCESS
--***************************************************************************
-- These are the main blocks which schedule read and write operations
-- Note that the reset priority feature at the latch stage is only supported
-- for Spartan-6. For other families, the default priority at the latch stage
-- is "CE"
--***************************************************************************
-- Synchronous clocks: schedule port operations with respect to both
-- write operating modes
IF (C_COMMON_CLK=1) THEN
IF (CLKA='1' AND CLKA'EVENT) THEN
CASE WRITE_MODES IS
WHEN "0000" => -- write_first write_first
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
--Read A
IF (rea_i='1') THEN
read_a(ADDRA, reseta_i);
END IF;
--Read B
IF (reb_i='1') THEN
read_b(ADDRB, resetb_i);
END IF;
WHEN "0100" => -- read_first write_first
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
--Read B
IF (reb_i='1') THEN
read_b(ADDRB, resetb_i);
END IF;
--Read A
IF (rea_i='1') THEN
read_a(ADDRA, reseta_i);
END IF;
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
WHEN "0001" => -- write_first read_first
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Read A
IF (rea_i='1') THEN
read_a(ADDRA, reseta_i);
END IF;
--Read B
IF (reb_i='1') THEN
read_b(ADDRB, resetb_i);
END IF;
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
WHEN "0101" => --read_first read_first
--Read A
IF (rea_i='1') THEN
read_a(ADDRA, reseta_i);
END IF;
--Read B
IF (reb_i='1') THEN
read_b(ADDRB, resetb_i);
END IF;
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
WHEN "0010" => -- write_first no_change
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Read A
IF (rea_i='1') THEN
read_a(ADDRA, reseta_i);
END IF;
--Read B
IF (reb_i='1' AND (web_i=WEB0 OR resetb_i='1')) THEN
read_b(ADDRB, resetb_i);
END IF;
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
WHEN "0110" => -- read_first no_change
--Read A
IF (rea_i='1') THEN
read_a(ADDRA, reseta_i);
END IF;
--Read B
IF (reb_i='1' AND (web_i=WEB0 OR resetb_i='1')) THEN
read_b(ADDRB, resetb_i);
END IF;
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
WHEN "1000" => -- no_change write_first
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
--Read A
IF (rea_i='1' AND (wea_i=WEA0 OR reseta_i='1')) THEN
read_a(ADDRA, reseta_i);
END IF;
--Read B
IF (reb_i='1') THEN
read_b(ADDRB, resetb_i);
END IF;
WHEN "1001" => -- no_change read_first
--Read B
IF (reb_i='1') THEN
read_b(ADDRB, resetb_i);
END IF;
--Read A
IF (rea_i='1' AND (wea_i=WEA0 OR reseta_i='1')) THEN
read_a(ADDRA, reseta_i);
END IF;
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
WHEN "1010" => -- no_change no_change
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
--Read A
IF (rea_i='1' AND (wea_i=WEA0 OR reseta_i='1')) THEN
read_a(ADDRA, reseta_i);
END IF;
--Read B
IF (reb_i='1' AND (web_i=WEB0 OR resetb_i='1')) THEN
read_b(ADDRB, resetb_i);
END IF;
WHEN OTHERS =>
ASSERT FALSE REPORT "Invalid Operating Mode" SEVERITY ERROR;
END CASE;
END IF;
END IF; -- Synchronous clocks
-- Asynchronous clocks: port operation is independent
IF (C_COMMON_CLK=0) THEN
IF (CLKA='1' AND CLKA'EVENT) THEN
CASE WRITE_MODE_A IS
WHEN "00" => -- write_first
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Read A
IF (rea_i='1') THEN
read_a(ADDRA, reseta_i);
END IF;
WHEN "01" => -- read_first
--Read A
IF (rea_i='1') THEN
read_a(ADDRA, reseta_i);
END IF;
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
WHEN "10" => -- no_change
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Read A
IF (rea_i='1' AND (wea_i=WEA0 OR reseta_i='1')) THEN
read_a(ADDRA, reseta_i);
END IF;
WHEN OTHERS =>
ASSERT FALSE REPORT "Invalid Operating Mode" SEVERITY ERROR;
END CASE;
END IF;
IF (CLKB='1' AND CLKB'EVENT) THEN
CASE WRITE_MODE_B IS
WHEN "00" => -- write_first
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
--Read B
IF (reb_i='1') THEN
read_b(ADDRB, resetb_i);
END IF;
WHEN "01" => -- read_first
--Read B
IF (reb_i='1') THEN
read_b(ADDRB, resetb_i);
END IF;
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
WHEN "10" => -- no_change
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
--Read B
IF (reb_i='1' AND (web_i=WEB0 OR resetb_i='1')) THEN
read_b(ADDRB, resetb_i);
END IF;
WHEN OTHERS =>
ASSERT FALSE REPORT "Invalid Operating Mode" SEVERITY ERROR;
END CASE;
END IF;
END IF; -- Asynchronous clocks
-- Assign the memory VARIABLE to the user_visible memory_i SIGNAL
IF(DEBUG=1) THEN
memory_i <= memory;
doublebit_error_i <= doublebit_error;
current_contents_i <= current_contents_var;
END IF;
END PROCESS;
--********************************************************************
-- Instantiate the VARIABLE depth output stage
--********************************************************************
-- Port A
rsta_outp_stage <= RSTA and not sleep;
rstb_outp_stage <= RSTB and not sleep;
reg_a : blk_mem_gen_v8_3_0_output_stage
GENERIC MAP(
C_FAMILY => C_FAMILY,
C_XDEVICEFAMILY => C_XDEVICEFAMILY,
C_RST_TYPE => "SYNC",
C_HAS_RST => C_HAS_RSTA,
C_RSTRAM => C_RSTRAM_A,
C_RST_PRIORITY => C_RST_PRIORITY_A,
init_val => INITA_VAL,
C_HAS_EN => C_HAS_ENA,
C_HAS_REGCE => C_HAS_REGCEA,
C_DATA_WIDTH => C_READ_WIDTH_A,
C_ADDRB_WIDTH => C_ADDRB_WIDTH,
C_HAS_MEM_OUTPUT_REGS => C_HAS_MEM_OUTPUT_REGS_A,
C_USE_SOFTECC => C_USE_SOFTECC,
C_USE_ECC => C_USE_ECC,
NUM_STAGES => NUM_OUTPUT_STAGES_A,
C_EN_ECC_PIPE => C_EN_ECC_PIPE,
FLOP_DELAY => FLOP_DELAY
)
PORT MAP (
CLK => CLKA,
RST => rsta_outp_stage, --RSTA,
EN => ENA,
REGCE => REGCEA,
DIN_I => memory_out_a,
DOUT => DOUTA,
SBITERR_IN_I => '0',
DBITERR_IN_I => '0',
SBITERR => OPEN,
DBITERR => OPEN,
RDADDRECC_IN_I => (OTHERS => '0'),
ECCPIPECE => '0',
RDADDRECC => OPEN
);
-- Port B
reg_b : blk_mem_gen_v8_3_0_output_stage
GENERIC MAP(
C_FAMILY => C_FAMILY,
C_XDEVICEFAMILY => C_XDEVICEFAMILY,
C_RST_TYPE => "SYNC",
C_HAS_RST => C_HAS_RSTB,
C_RSTRAM => C_RSTRAM_B,
C_RST_PRIORITY => C_RST_PRIORITY_B,
init_val => INITB_VAL,
C_HAS_EN => C_HAS_ENB,
C_HAS_REGCE => C_HAS_REGCEB,
C_DATA_WIDTH => C_READ_WIDTH_B,
C_ADDRB_WIDTH => C_ADDRB_WIDTH,
C_HAS_MEM_OUTPUT_REGS => C_HAS_MEM_OUTPUT_REGS_B,
C_USE_SOFTECC => C_USE_SOFTECC,
C_USE_ECC => C_USE_ECC,
NUM_STAGES => NUM_OUTPUT_STAGES_B,
C_EN_ECC_PIPE => C_EN_ECC_PIPE,
FLOP_DELAY => FLOP_DELAY
)
PORT MAP (
CLK => CLKB,
RST => rstb_outp_stage,--RSTB,
EN => ENB,
REGCE => REGCEB,
DIN_I => memory_out_b,
DOUT => doutb_i,
SBITERR_IN_I => sbiterr_in,
DBITERR_IN_I => dbiterr_in,
SBITERR => sbiterr_i,
DBITERR => dbiterr_i,
RDADDRECC_IN_I => rdaddrecc_in,
ECCPIPECE => ECCPIPECE,
RDADDRECC => rdaddrecc_i
);
--********************************************************************
-- Instantiate the input / Output Register stages
--********************************************************************
output_reg_stage: blk_mem_gen_v8_3_0_softecc_output_reg_stage
GENERIC MAP(
C_DATA_WIDTH => C_READ_WIDTH_B,
C_ADDRB_WIDTH => C_ADDRB_WIDTH,
C_HAS_SOFTECC_OUTPUT_REGS_B => C_HAS_SOFTECC_OUTPUT_REGS_B,
C_USE_SOFTECC => C_USE_SOFTECC,
FLOP_DELAY => FLOP_DELAY
)
PORT MAP(
CLK => CLKB,
DIN => doutb_i,
DOUT => DOUTB,
SBITERR_IN => sbiterr_i,
DBITERR_IN => dbiterr_i,
SBITERR => sbiterr_sdp,
DBITERR => dbiterr_sdp,
RDADDRECC_IN => rdaddrecc_i,
RDADDRECC => rdaddrecc_sdp
);
--*********************************
-- Synchronous collision checks
--*********************************
sync_coll: IF (C_DISABLE_WARN_BHV_COLL=0 AND C_COMMON_CLK=1) GENERATE
PROCESS (CLKA)
use IEEE.STD_LOGIC_TEXTIO.ALL;
-- collision detect
VARIABLE is_collision : BOOLEAN;
VARIABLE message : LINE;
BEGIN
IF (CLKA='1' AND CLKA'EVENT) THEN
-- Possible collision if both are enabled and the addresses match
-- Not checking the collision condition when there is an 'x' on the Addr bus
IF (ena_i='1' AND enb_i='1' AND OR_REDUCE(ADDRA)/='X') THEN
is_collision := collision_check(ADDRA,
wea_i/=WEA0,
ADDRB,
web_i/=WEB0);
ELSE
is_collision := false;
END IF;
-- If the write port is in READ_FIRST mode, there is no collision
IF (C_WRITE_MODE_A="READ_FIRST" AND wea_i/=WEA0 AND web_i=WEB0) THEN
is_collision := false;
END IF;
IF (C_WRITE_MODE_B="READ_FIRST" AND web_i/=WEB0 AND wea_i=WEA0) THEN
is_collision := false;
END IF;
-- Only flag if one of the accesses is a write
IF (is_collision AND (wea_i/=WEA0 OR web_i/=WEB0)) THEN
write(message, C_CORENAME);
write(message, STRING'(" WARNING: collision detected: "));
IF (wea_i/=WEA0) THEN
write(message, STRING'("A write address: "));
ELSE
write(message, STRING'("A read address: "));
END IF;
write(message, ADDRA);
IF (web_i/=WEB0) THEN
write(message, STRING'(", B write address: "));
ELSE
write(message, STRING'(", B read address: "));
END IF;
write(message, ADDRB);
write(message, LF);
ASSERT false REPORT message.ALL SEVERITY WARNING;
deallocate(message);
END IF;
END IF;
END PROCESS;
END GENERATE;
--*********************************
-- Asynchronous collision checks
--*********************************
async_coll: IF (C_DISABLE_WARN_BHV_COLL=0 AND C_COMMON_CLK=0) GENERATE
SIGNAL addra_delay : STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0);
SIGNAL wea_delay : STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0);
SIGNAL ena_delay : STD_LOGIC;
SIGNAL addrb_delay : STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0);
SIGNAL web_delay : STD_LOGIC_VECTOR(C_WEB_WIDTH-1 DOWNTO 0);
SIGNAL enb_delay : STD_LOGIC;
BEGIN
-- Delay A and B addresses in order to mimic setup/hold times
PROCESS (ADDRA, wea_i, ena_i, ADDRB, web_i, enb_i)
BEGIN
addra_delay <= ADDRA AFTER COLL_DELAY;
wea_delay <= wea_i AFTER COLL_DELAY;
ena_delay <= ena_i AFTER COLL_DELAY;
addrb_delay <= ADDRB AFTER COLL_DELAY;
web_delay <= web_i AFTER COLL_DELAY;
enb_delay <= enb_i AFTER COLL_DELAY;
END PROCESS;
-- Do the checks w/rt A
PROCESS (CLKA)
use IEEE.STD_LOGIC_TEXTIO.ALL;
VARIABLE is_collision_a : BOOLEAN;
VARIABLE is_collision_delay_a : BOOLEAN;
VARIABLE message : LINE;
BEGIN
-- Possible collision if both are enabled and the addresses match
-- Not checking the collision condition when there is an 'x' on the Addr bus
IF (ena_i='1' AND enb_i='1' AND OR_REDUCE(ADDRA)/='X') THEN
is_collision_a := collision_check(ADDRA,
wea_i/=WEA0,
ADDRB,
web_i/=WEB0);
ELSE
is_collision_a := false;
END IF;
IF (ena_i='1' AND enb_delay='1' AND OR_REDUCE(ADDRA)/='X') THEN
is_collision_delay_a := collision_check(ADDRA,
wea_i/=WEA0,
addrb_delay,
web_delay/=WEB0);
ELSE
is_collision_delay_a := false;
END IF;
-- Only flag if B access is a write
IF (is_collision_a AND web_i/=WEB0) THEN
write(message, C_CORENAME);
write(message, STRING'(" WARNING: collision detected: "));
IF (wea_i/=WEA0) THEN
write(message, STRING'("A write address: "));
ELSE
write(message, STRING'("A read address: "));
END IF;
write(message, ADDRA);
write(message, STRING'(", B write address: "));
write(message, ADDRB);
write(message, LF);
ASSERT false REPORT message.ALL SEVERITY WARNING;
deallocate(message);
ELSIF (is_collision_delay_a AND web_delay/=WEB0) THEN
write(message, C_CORENAME);
write(message, STRING'(" WARNING: collision detected: "));
IF (wea_i/=WEA0) THEN
write(message, STRING'("A write address: "));
ELSE
write(message, STRING'("A read address: "));
END IF;
write(message, ADDRA);
write(message, STRING'(", B write address: "));
write(message, addrb_delay);
write(message, LF);
ASSERT false REPORT message.ALL SEVERITY WARNING;
deallocate(message);
END IF;
END PROCESS;
-- Do the checks w/rt B
PROCESS (CLKB)
use IEEE.STD_LOGIC_TEXTIO.ALL;
VARIABLE is_collision_b : BOOLEAN;
VARIABLE is_collision_delay_b : BOOLEAN;
VARIABLE message : LINE;
BEGIN
-- Possible collision if both are enabled and the addresses match
-- Not checking the collision condition when there is an 'x' on the Addr bus
IF (ena_i='1' AND enb_i='1' AND OR_REDUCE(ADDRA) /= 'X') THEN
is_collision_b := collision_check(ADDRA,
wea_i/=WEA0,
ADDRB,
web_i/=WEB0);
ELSE
is_collision_b := false;
END IF;
IF (ena_i='1' AND enb_delay='1' AND OR_REDUCE(addra_delay) /= 'X') THEN
is_collision_delay_b := collision_check(addra_delay,
wea_delay/=WEA0,
ADDRB,
web_i/=WEB0);
ELSE
is_collision_delay_b := false;
END IF;
-- Only flag if A access is a write
-- Modified condition checking (is_collision_b AND WEA0_i=/WEA0) to fix CR526228
IF (is_collision_b AND wea_i/=WEA0) THEN
write(message, C_CORENAME);
write(message, STRING'(" WARNING: collision detected: "));
write(message, STRING'("A write address: "));
write(message, ADDRA);
IF (web_i/=WEB0) THEN
write(message, STRING'(", B write address: "));
ELSE
write(message, STRING'(", B read address: "));
END IF;
write(message, ADDRB);
write(message, LF);
ASSERT false REPORT message.ALL SEVERITY WARNING;
deallocate(message);
ELSIF (is_collision_delay_b AND wea_delay/=WEA0) THEN
write(message, C_CORENAME);
write(message, STRING'(" WARNING: collision detected: "));
write(message, STRING'("A write address: "));
write(message, addra_delay);
IF (web_i/=WEB0) THEN
write(message, STRING'(", B write address: "));
ELSE
write(message, STRING'(", B read address: "));
END IF;
write(message, ADDRB);
write(message, LF);
ASSERT false REPORT message.ALL SEVERITY WARNING;
deallocate(message);
END IF;
END PROCESS;
END GENERATE;
END mem_module_behavioral;
--******************************************************************************
-- Top module that wraps SoftECC Input register stage and the main memory module
--
-- This module is the top-level of behavioral model
--******************************************************************************
LIBRARY STD;
USE STD.TEXTIO.ALL;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY blk_mem_gen_v8_3_0 IS
GENERIC (
C_CORENAME : STRING := "blk_mem_gen_v8_3_0";
C_FAMILY : STRING := "virtex7";
C_XDEVICEFAMILY : STRING := "virtex7";
C_ELABORATION_DIR : STRING := "";
C_INTERFACE_TYPE : INTEGER := 0;
C_USE_BRAM_BLOCK : INTEGER := 0;
C_ENABLE_32BIT_ADDRESS : INTEGER := 0;
C_CTRL_ECC_ALGO : STRING := "NONE";
C_AXI_TYPE : INTEGER := 0;
C_AXI_SLAVE_TYPE : INTEGER := 0;
C_HAS_AXI_ID : INTEGER := 0;
C_AXI_ID_WIDTH : INTEGER := 4;
C_MEM_TYPE : INTEGER := 2;
C_BYTE_SIZE : INTEGER := 8;
C_ALGORITHM : INTEGER := 2;
C_PRIM_TYPE : INTEGER := 3;
C_LOAD_INIT_FILE : INTEGER := 0;
C_INIT_FILE_NAME : STRING := "";
C_INIT_FILE : STRING := "";
C_USE_DEFAULT_DATA : INTEGER := 0;
C_DEFAULT_DATA : STRING := "";
--C_RST_TYPE : STRING := "SYNC";
C_HAS_RSTA : INTEGER := 0;
C_RST_PRIORITY_A : STRING := "CE";
C_RSTRAM_A : INTEGER := 0;
C_INITA_VAL : STRING := "";
C_HAS_ENA : INTEGER := 1;
C_HAS_REGCEA : INTEGER := 0;
C_USE_BYTE_WEA : INTEGER := 0;
C_WEA_WIDTH : INTEGER := 1;
C_WRITE_MODE_A : STRING := "WRITE_FIRST";
C_WRITE_WIDTH_A : INTEGER := 32;
C_READ_WIDTH_A : INTEGER := 32;
C_WRITE_DEPTH_A : INTEGER := 64;
C_READ_DEPTH_A : INTEGER := 64;
C_ADDRA_WIDTH : INTEGER := 6;
C_HAS_RSTB : INTEGER := 0;
C_RST_PRIORITY_B : STRING := "CE";
C_RSTRAM_B : INTEGER := 0;
C_INITB_VAL : STRING := "";
C_HAS_ENB : INTEGER := 1;
C_HAS_REGCEB : INTEGER := 0;
C_USE_BYTE_WEB : INTEGER := 0;
C_WEB_WIDTH : INTEGER := 1;
C_WRITE_MODE_B : STRING := "WRITE_FIRST";
C_WRITE_WIDTH_B : INTEGER := 32;
C_READ_WIDTH_B : INTEGER := 32;
C_WRITE_DEPTH_B : INTEGER := 64;
C_READ_DEPTH_B : INTEGER := 64;
C_ADDRB_WIDTH : INTEGER := 6;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER := 0;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER := 0;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER := 0;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER := 0;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER := 0;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER := 0;
C_MUX_PIPELINE_STAGES : INTEGER := 0;
C_USE_SOFTECC : INTEGER := 0;
C_USE_ECC : INTEGER := 0;
C_EN_ECC_PIPE : INTEGER := 0;
C_HAS_INJECTERR : INTEGER := 0;
C_SIM_COLLISION_CHECK : STRING := "NONE";
C_COMMON_CLK : INTEGER := 1;
C_DISABLE_WARN_BHV_COLL : INTEGER := 0;
C_EN_SLEEP_PIN : INTEGER := 0;
C_USE_URAM : integer := 0;
C_EN_RDADDRA_CHG : integer := 0;
C_EN_RDADDRB_CHG : integer := 0;
C_EN_DEEPSLEEP_PIN : integer := 0;
C_EN_SHUTDOWN_PIN : integer := 0;
C_EN_SAFETY_CKT : integer := 0;
C_DISABLE_WARN_BHV_RANGE : INTEGER := 0;
C_COUNT_36K_BRAM : string := "";
C_COUNT_18K_BRAM : string := "";
C_EST_POWER_SUMMARY : string := ""
);
PORT (
clka : IN STD_LOGIC := '0';
rsta : IN STD_LOGIC := '0';
ena : IN STD_LOGIC := '1';
regcea : IN STD_LOGIC := '1';
wea : IN STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
addra : IN STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0):= (OTHERS => '0');
dina : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0)
:= (OTHERS => '0');
douta : OUT STD_LOGIC_VECTOR(C_READ_WIDTH_A-1 DOWNTO 0);
clkb : IN STD_LOGIC := '0';
rstb : IN STD_LOGIC := '0';
enb : IN STD_LOGIC := '1';
regceb : IN STD_LOGIC := '1';
web : IN STD_LOGIC_VECTOR(C_WEB_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
addrb : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
dinb : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0)
:= (OTHERS => '0');
doutb : OUT STD_LOGIC_VECTOR(C_READ_WIDTH_B-1 DOWNTO 0);
injectsbiterr : IN STD_LOGIC := '0';
injectdbiterr : IN STD_LOGIC := '0';
sbiterr : OUT STD_LOGIC := '0';
dbiterr : OUT STD_LOGIC := '0';
rdaddrecc : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0);
eccpipece : in std_logic := '0';
sleep : in std_logic := '0';
deepsleep : in std_logic := '0';
shutdown : in std_logic := '0';
rsta_busy : out std_logic := '0';
rstb_busy : out std_logic := '0';
-- AXI BMG Input and Output Port Declarations
-- AXI Global Signals
s_aclk : IN STD_LOGIC := '0';
s_aresetn : IN STD_LOGIC := '0';
-- axi full/lite slave Write (write side)
s_axi_awid : IN STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0');
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
s_axi_awvalid : IN STD_LOGIC := '0';
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wstrb : IN STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wlast : IN STD_LOGIC := '0';
s_axi_wvalid : IN STD_LOGIC := '0';
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC := '0';
-- axi full/lite slave Read (Write side)
s_axi_arid : IN STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
s_axi_arlen : IN STD_LOGIC_VECTOR(8-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0');
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
s_axi_arvalid : IN STD_LOGIC := '0';
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_rdata : OUT STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(2-1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC := '0';
-- axi full/lite sideband Signals
s_axi_injectsbiterr : IN STD_LOGIC := '0';
s_axi_injectdbiterr : IN STD_LOGIC := '0';
s_axi_sbiterr : OUT STD_LOGIC := '0';
s_axi_dbiterr : OUT STD_LOGIC := '0';
s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0')
);
END blk_mem_gen_v8_3_0;
--******************************
-- Port and Generic Definitions
--******************************
---------------------------------------------------------------------------
-- Generic Definitions
---------------------------------------------------------------------------
-- C_CORENAME : Instance name of the Block Memory Generator core
-- C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following
-- options are available - "spartan3", "spartan6",
-- "virtex4", "virtex5", "virtex6l" and "virtex6".
-- C_MEM_TYPE : Designates memory type.
-- It can be
-- 0 - Single Port Memory
-- 1 - Simple Dual Port Memory
-- 2 - True Dual Port Memory
-- 3 - Single Port Read Only Memory
-- 4 - Dual Port Read Only Memory
-- C_BYTE_SIZE : Size of a byte (8 or 9 bits)
-- C_ALGORITHM : Designates the algorithm method used
-- for constructing the memory.
-- It can be Fixed_Primitives, Minimum_Area or
-- Low_Power
-- C_PRIM_TYPE : Designates the user selected primitive used to
-- construct the memory.
--
-- C_LOAD_INIT_FILE : Designates the use of an initialization file to
-- initialize memory contents.
-- C_INIT_FILE_NAME : Memory initialization file name.
-- C_USE_DEFAULT_DATA : Designates whether to fill remaining
-- initialization space with default data
-- C_DEFAULT_DATA : Default value of all memory locations
-- not initialized by the memory
-- initialization file.
-- C_RST_TYPE : Type of reset - Synchronous or Asynchronous
--
-- C_HAS_RSTA : Determines the presence of the RSTA port
-- C_RST_PRIORITY_A : Determines the priority between CE and SR for
-- Port A.
-- C_RSTRAM_A : Determines if special reset behavior is used for
-- Port A
-- C_INITA_VAL : The initialization value for Port A
-- C_HAS_ENA : Determines the presence of the ENA port
-- C_HAS_REGCEA : Determines the presence of the REGCEA port
-- C_USE_BYTE_WEA : Determines if the Byte Write is used or not.
-- C_WEA_WIDTH : The width of the WEA port
-- C_WRITE_MODE_A : Configurable write mode for Port A. It can be
-- WRITE_FIRST, READ_FIRST or NO_CHANGE.
-- C_WRITE_WIDTH_A : Memory write width for Port A.
-- C_READ_WIDTH_A : Memory read width for Port A.
-- C_WRITE_DEPTH_A : Memory write depth for Port A.
-- C_READ_DEPTH_A : Memory read depth for Port A.
-- C_ADDRA_WIDTH : Width of the ADDRA input port
-- C_HAS_RSTB : Determines the presence of the RSTB port
-- C_RST_PRIORITY_B : Determines the priority between CE and SR for
-- Port B.
-- C_RSTRAM_B : Determines if special reset behavior is used for
-- Port B
-- C_INITB_VAL : The initialization value for Port B
-- C_HAS_ENB : Determines the presence of the ENB port
-- C_HAS_REGCEB : Determines the presence of the REGCEB port
-- C_USE_BYTE_WEB : Determines if the Byte Write is used or not.
-- C_WEB_WIDTH : The width of the WEB port
-- C_WRITE_MODE_B : Configurable write mode for Port B. It can be
-- WRITE_FIRST, READ_FIRST or NO_CHANGE.
-- C_WRITE_WIDTH_B : Memory write width for Port B.
-- C_READ_WIDTH_B : Memory read width for Port B.
-- C_WRITE_DEPTH_B : Memory write depth for Port B.
-- C_READ_DEPTH_B : Memory read depth for Port B.
-- C_ADDRB_WIDTH : Width of the ADDRB input port
-- C_HAS_MEM_OUTPUT_REGS_A : Designates the use of a register at the output
-- of the RAM primitive for Port A.
-- C_HAS_MEM_OUTPUT_REGS_B : Designates the use of a register at the output
-- of the RAM primitive for Port B.
-- C_HAS_MUX_OUTPUT_REGS_A : Designates the use of a register at the output
-- of the MUX for Port A.
-- C_HAS_MUX_OUTPUT_REGS_B : Designates the use of a register at the output
-- of the MUX for Port B.
-- C_MUX_PIPELINE_STAGES : Designates the number of pipeline stages in
-- between the muxes.
-- C_USE_SOFTECC : Determines if the Soft ECC feature is used or
-- not. Only applicable Spartan-6
-- C_USE_ECC : Determines if the ECC feature is used or
-- not. Only applicable for V5 and V6
-- C_HAS_INJECTERR : Determines if the error injection pins
-- are present or not. If the ECC feature
-- is not used, this value is defaulted to
-- 0, else the following are the allowed
-- values:
-- 0 : No INJECTSBITERR or INJECTDBITERR pins
-- 1 : Only INJECTSBITERR pin exists
-- 2 : Only INJECTDBITERR pin exists
-- 3 : Both INJECTSBITERR and INJECTDBITERR pins exist
-- C_SIM_COLLISION_CHECK : Controls the disabling of Unisim model collision
-- warnings. It can be "ALL", "NONE",
-- "Warnings_Only" or "Generate_X_Only".
-- C_COMMON_CLK : Determins if the core has a single CLK input.
-- C_DISABLE_WARN_BHV_COLL : Controls the Behavioral Model Collision warnings
-- C_DISABLE_WARN_BHV_RANGE: Controls the Behavioral Model Out of Range
-- warnings
---------------------------------------------------------------------------
-- Port Definitions
---------------------------------------------------------------------------
-- CLKA : Clock to synchronize all read and write operations of Port A.
-- RSTA : Reset input to reset memory outputs to a user-defined
-- reset state for Port A.
-- ENA : Enable all read and write operations of Port A.
-- REGCEA : Register Clock Enable to control each pipeline output
-- register stages for Port A.
-- WEA : Write Enable to enable all write operations of Port A.
-- ADDRA : Address of Port A.
-- DINA : Data input of Port A.
-- DOUTA : Data output of Port A.
-- CLKB : Clock to synchronize all read and write operations of Port B.
-- RSTB : Reset input to reset memory outputs to a user-defined
-- reset state for Port B.
-- ENB : Enable all read and write operations of Port B.
-- REGCEB : Register Clock Enable to control each pipeline output
-- register stages for Port B.
-- WEB : Write Enable to enable all write operations of Port B.
-- ADDRB : Address of Port B.
-- DINB : Data input of Port B.
-- DOUTB : Data output of Port B.
-- INJECTSBITERR : Single Bit ECC Error Injection Pin.
-- INJECTDBITERR : Double Bit ECC Error Injection Pin.
-- SBITERR : Output signal indicating that a Single Bit ECC Error has been
-- detected and corrected.
-- DBITERR : Output signal indicating that a Double Bit ECC Error has been
-- detected.
-- RDADDRECC : Read Address Output signal indicating address at which an
-- ECC error has occurred.
---------------------------------------------------------------------------
ARCHITECTURE behavioral OF blk_mem_gen_v8_3_0 IS
COMPONENT blk_mem_gen_v8_3_0_mem_module
GENERIC (
C_CORENAME : STRING := "blk_mem_gen_v8_3_0";
C_FAMILY : STRING := "virtex7";
C_XDEVICEFAMILY : STRING := "virtex7";
C_USE_BRAM_BLOCK : INTEGER := 0;
C_ENABLE_32BIT_ADDRESS : INTEGER := 0;
C_MEM_TYPE : INTEGER := 2;
C_BYTE_SIZE : INTEGER := 8;
C_ALGORITHM : INTEGER := 2;
C_PRIM_TYPE : INTEGER := 3;
C_LOAD_INIT_FILE : INTEGER := 0;
C_INIT_FILE_NAME : STRING := "";
C_INIT_FILE : STRING := "";
C_USE_DEFAULT_DATA : INTEGER := 0;
C_DEFAULT_DATA : STRING := "";
C_RST_TYPE : STRING := "SYNC";
C_HAS_RSTA : INTEGER := 0;
C_RST_PRIORITY_A : STRING := "CE";
C_RSTRAM_A : INTEGER := 0;
C_INITA_VAL : STRING := "";
C_HAS_ENA : INTEGER := 1;
C_HAS_REGCEA : INTEGER := 0;
C_USE_BYTE_WEA : INTEGER := 0;
C_WEA_WIDTH : INTEGER := 1;
C_WRITE_MODE_A : STRING := "WRITE_FIRST";
C_WRITE_WIDTH_A : INTEGER := 32;
C_READ_WIDTH_A : INTEGER := 32;
C_WRITE_DEPTH_A : INTEGER := 64;
C_READ_DEPTH_A : INTEGER := 64;
C_ADDRA_WIDTH : INTEGER := 6;
C_HAS_RSTB : INTEGER := 0;
C_RST_PRIORITY_B : STRING := "CE";
C_RSTRAM_B : INTEGER := 0;
C_INITB_VAL : STRING := "";
C_HAS_ENB : INTEGER := 1;
C_HAS_REGCEB : INTEGER := 0;
C_USE_BYTE_WEB : INTEGER := 0;
C_WEB_WIDTH : INTEGER := 1;
C_WRITE_MODE_B : STRING := "WRITE_FIRST";
C_WRITE_WIDTH_B : INTEGER := 32;
C_READ_WIDTH_B : INTEGER := 32;
C_WRITE_DEPTH_B : INTEGER := 64;
C_READ_DEPTH_B : INTEGER := 64;
C_ADDRB_WIDTH : INTEGER := 6;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER := 0;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER := 0;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER := 0;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER := 0;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER := 0;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER := 0;
C_MUX_PIPELINE_STAGES : INTEGER := 0;
C_USE_SOFTECC : INTEGER := 0;
C_USE_ECC : INTEGER := 0;
C_HAS_INJECTERR : INTEGER := 0;
C_SIM_COLLISION_CHECK : STRING := "NONE";
C_COMMON_CLK : INTEGER := 1;
FLOP_DELAY : TIME := 100 ps;
C_DISABLE_WARN_BHV_COLL : INTEGER := 0;
C_EN_ECC_PIPE : INTEGER := 0;
C_DISABLE_WARN_BHV_RANGE : INTEGER := 0
);
PORT (
CLKA : IN STD_LOGIC := '0';
RSTA : IN STD_LOGIC := '0';
ENA : IN STD_LOGIC := '1';
REGCEA : IN STD_LOGIC := '1';
WEA : IN STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
ADDRA : IN STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0):= (OTHERS => '0');
DINA : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0)
:= (OTHERS => '0');
DOUTA : OUT STD_LOGIC_VECTOR(C_READ_WIDTH_A-1 DOWNTO 0);
CLKB : IN STD_LOGIC := '0';
RSTB : IN STD_LOGIC := '0';
ENB : IN STD_LOGIC := '1';
REGCEB : IN STD_LOGIC := '1';
WEB : IN STD_LOGIC_VECTOR(C_WEB_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
ADDRB : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
DINB : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0)
:= (OTHERS => '0');
DOUTB : OUT STD_LOGIC_VECTOR(C_READ_WIDTH_B-1 DOWNTO 0);
INJECTSBITERR : IN STD_LOGIC := '0';
INJECTDBITERR : IN STD_LOGIC := '0';
ECCPIPECE : IN STD_LOGIC;
SLEEP : IN STD_LOGIC;
SBITERR : OUT STD_LOGIC;
DBITERR : OUT STD_LOGIC;
RDADDRECC : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_3_0_mem_module;
COMPONENT blk_mem_axi_regs_fwd_v8_3 IS
GENERIC(
C_DATA_WIDTH : INTEGER := 8
);
PORT (
ACLK : IN STD_LOGIC;
ARESET : IN STD_LOGIC;
S_VALID : IN STD_LOGIC;
S_READY : OUT STD_LOGIC;
S_PAYLOAD_DATA : IN STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
M_VALID : OUT STD_LOGIC;
M_READY : IN STD_LOGIC;
M_PAYLOAD_DATA : OUT STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0)
);
END COMPONENT blk_mem_axi_regs_fwd_v8_3;
COMPONENT blk_mem_axi_read_wrapper_beh
GENERIC (
-- AXI Interface related parameters start here
C_INTERFACE_TYPE : integer := 0;
C_AXI_TYPE : integer := 0;
C_AXI_SLAVE_TYPE : integer := 0;
C_MEMORY_TYPE : integer := 0;
C_WRITE_WIDTH_A : integer := 4;
C_WRITE_DEPTH_A : integer := 32;
C_ADDRA_WIDTH : integer := 12;
C_AXI_PIPELINE_STAGES : integer := 0;
C_AXI_ARADDR_WIDTH : integer := 12;
C_HAS_AXI_ID : integer := 0;
C_AXI_ID_WIDTH : integer := 4;
C_ADDRB_WIDTH : integer := 12
);
PORT (
-- AXI Global Signals
S_ACLK : IN std_logic;
S_ARESETN : IN std_logic;
-- AXI Full/Lite Slave Read (Read side)
S_AXI_ARADDR : IN std_logic_vector(C_AXI_ARADDR_WIDTH-1 downto 0) := (OTHERS => '0');
S_AXI_ARLEN : IN std_logic_vector(7 downto 0) := (OTHERS => '0');
S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARVALID : IN std_logic := '0';
S_AXI_ARREADY : OUT std_logic;
S_AXI_RLAST : OUT std_logic;
S_AXI_RVALID : OUT std_logic;
S_AXI_RREADY : IN std_logic := '0';
S_AXI_ARID : IN std_logic_vector(C_AXI_ID_WIDTH-1 downto 0) := (OTHERS => '0');
S_AXI_RID : OUT std_logic_vector(C_AXI_ID_WIDTH-1 downto 0) := (OTHERS => '0');
-- AXI Full/Lite Read Address Signals to BRAM
S_AXI_ARADDR_OUT : OUT std_logic_vector(C_ADDRB_WIDTH-1 downto 0);
S_AXI_RD_EN : OUT std_logic
);
END COMPONENT blk_mem_axi_read_wrapper_beh;
COMPONENT blk_mem_axi_write_wrapper_beh
GENERIC (
-- AXI Interface related parameters start here
C_INTERFACE_TYPE : integer := 0; -- 0: Native Interface; 1: AXI Interface
C_AXI_TYPE : integer := 0; -- 0: AXI Lite; 1: AXI Full;
C_AXI_SLAVE_TYPE : integer := 0; -- 0: MEMORY SLAVE; 1: PERIPHERAL SLAVE;
C_MEMORY_TYPE : integer := 0; -- 0: SP-RAM, 1: SDP-RAM; 2: TDP-RAM; 3: DP-ROM;
C_WRITE_DEPTH_A : integer := 0;
C_AXI_AWADDR_WIDTH : integer := 32;
C_ADDRA_WIDTH : integer := 12;
C_AXI_WDATA_WIDTH : integer := 32;
C_HAS_AXI_ID : integer := 0;
C_AXI_ID_WIDTH : integer := 4;
-- AXI OUTSTANDING WRITES
C_AXI_OS_WR : integer := 2
);
PORT (
-- AXI Global Signals
S_ACLK : IN std_logic;
S_ARESETN : IN std_logic;
-- AXI Full/Lite Slave Write Channel (write side)
S_AXI_AWID : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWADDR : IN std_logic_vector(C_AXI_AWADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWLEN : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWVALID : IN std_logic := '0';
S_AXI_AWREADY : OUT std_logic := '0';
S_AXI_WVALID : IN std_logic := '0';
S_AXI_WREADY : OUT std_logic := '0';
S_AXI_BID : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_BVALID : OUT std_logic := '0';
S_AXI_BREADY : IN std_logic := '0';
-- Signals for BMG interface
S_AXI_AWADDR_OUT : OUT std_logic_vector(C_ADDRA_WIDTH-1 DOWNTO 0);
S_AXI_WR_EN : OUT std_logic:= '0'
);
END COMPONENT blk_mem_axi_write_wrapper_beh;
CONSTANT FLOP_DELAY : TIME := 100 ps;
SIGNAL rsta_in : STD_LOGIC := '1';
SIGNAL ena_in : STD_LOGIC := '1';
SIGNAL regcea_in : STD_LOGIC := '1';
SIGNAL wea_in : STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0):= (OTHERS => '0');
SIGNAL addra_in : STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0);
SIGNAL dina_in : STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0):= (OTHERS => '0');
SIGNAL injectsbiterr_in : STD_LOGIC := '0';
SIGNAL injectdbiterr_in : STD_LOGIC := '0';
-----------------------------------------------------------------------------
-- FUNCTION: toLowerCaseChar
-- Returns the lower case form of char if char is an upper case letter.
-- Otherwise char is returned.
-----------------------------------------------------------------------------
FUNCTION toLowerCaseChar(
char : character )
RETURN character IS
BEGIN
-- If char is not an upper case letter then return char
IF char<'A' OR char>'Z' THEN
RETURN char;
END IF;
-- Otherwise map char to its corresponding lower case character and
-- RETURN that
CASE char IS
WHEN 'A' => RETURN 'a';
WHEN 'B' => RETURN 'b';
WHEN 'C' => RETURN 'c';
WHEN 'D' => RETURN 'd';
WHEN 'E' => RETURN 'e';
WHEN 'F' => RETURN 'f';
WHEN 'G' => RETURN 'g';
WHEN 'H' => RETURN 'h';
WHEN 'I' => RETURN 'i';
WHEN 'J' => RETURN 'j';
WHEN 'K' => RETURN 'k';
WHEN 'L' => RETURN 'l';
WHEN 'M' => RETURN 'm';
WHEN 'N' => RETURN 'n';
WHEN 'O' => RETURN 'o';
WHEN 'P' => RETURN 'p';
WHEN 'Q' => RETURN 'q';
WHEN 'R' => RETURN 'r';
WHEN 'S' => RETURN 's';
WHEN 'T' => RETURN 't';
WHEN 'U' => RETURN 'u';
WHEN 'V' => RETURN 'v';
WHEN 'W' => RETURN 'w';
WHEN 'X' => RETURN 'x';
WHEN 'Y' => RETURN 'y';
WHEN 'Z' => RETURN 'z';
WHEN OTHERS => RETURN char;
END CASE;
END toLowerCaseChar;
-- Returns true if case insensitive string comparison determines that
-- str1 and str2 are equal
FUNCTION equalIgnoreCase(
str1 : STRING;
str2 : STRING )
RETURN BOOLEAN IS
CONSTANT len1 : INTEGER := str1'length;
CONSTANT len2 : INTEGER := str2'length;
VARIABLE equal : BOOLEAN := TRUE;
BEGIN
IF NOT (len1=len2) THEN
equal := FALSE;
ELSE
FOR i IN str2'left TO str1'right LOOP
IF NOT (toLowerCaseChar(str1(i)) = toLowerCaseChar(str2(i))) THEN
equal := FALSE;
END IF;
END LOOP;
END IF;
RETURN equal;
END equalIgnoreCase;
-----------------------------------------------------------------------------
-- FUNCTION: if_then_else
-- This function is used to implement an IF..THEN when such a statement is not
-- allowed.
----------------------------------------------------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STRING;
false_case : STRING)
RETURN STRING IS
BEGIN
IF NOT condition THEN
RETURN false_case;
ELSE
RETURN true_case;
END IF;
END if_then_else;
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
BEGIN
IF NOT condition THEN
RETURN false_case;
ELSE
RETURN true_case;
END IF;
END if_then_else;
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC_VECTOR;
false_case : STD_LOGIC_VECTOR)
RETURN STD_LOGIC_VECTOR IS
BEGIN
IF NOT condition THEN
RETURN false_case;
ELSE
RETURN true_case;
END IF;
END if_then_else;
----------------------------------------------------------------------------
-- FUNCTION : log2roundup
----------------------------------------------------------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := 1;
CONSTANT lower_limit : INTEGER := 1;
CONSTANT upper_limit : INTEGER := 8;
BEGIN
IF (data_value <= 1) THEN
width := 0;
ELSE
WHILE (cnt < data_value) LOOP
width := width + 1;
cnt := cnt *2;
END LOOP;
END IF;
RETURN width;
END log2roundup;
-----------------------------------------------------------------------------
-- FUNCTION : log2int
-----------------------------------------------------------------------------
FUNCTION log2int (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := data_value;
BEGIN
WHILE (cnt >1) LOOP
width := width + 1;
cnt := cnt/2;
END LOOP;
RETURN width;
END log2int;
-----------------------------------------------------------------------------
-- FUNCTION : divroundup
-- Returns the ceiling value of the division
-- Data_value - the quantity to be divided, dividend
-- Divisor - the value to divide the data_value by
-----------------------------------------------------------------------------
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER IS
VARIABLE div : INTEGER;
BEGIN
div := data_value/divisor;
IF ( (data_value MOD divisor) /= 0) THEN
div := div+1;
END IF;
RETURN div;
END divroundup;
SIGNAL s_axi_awaddr_out_c : STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL s_axi_araddr_out_c : STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL s_axi_wr_en_c : STD_LOGIC := '0';
SIGNAL s_axi_rd_en_c : STD_LOGIC := '0';
SIGNAL s_aresetn_a_c : STD_LOGIC := '0';
--**************************************************************************
-- AXI PARAMETERS
CONSTANT AXI_FULL_MEMORY_SLAVE : integer := if_then_else((C_AXI_SLAVE_TYPE = 0 AND C_AXI_TYPE = 1),1,0);
CONSTANT C_AXI_ADDR_WIDTH_MSB : integer := C_ADDRA_WIDTH+log2roundup(C_WRITE_WIDTH_A/8);
CONSTANT C_AXI_ADDR_WIDTH : integer := C_AXI_ADDR_WIDTH_MSB;
-- Data Width Number of LSB address bits to be discarded
-- 1 to 16 1
-- 17 to 32 2
-- 33 to 64 3
-- 65 to 128 4
-- 129 to 256 5
-- 257 to 512 6
-- 513 to 1024 7
-- The following two constants determine this.
CONSTANT LOWER_BOUND_VAL : integer := if_then_else((log2roundup(divroundup(C_WRITE_WIDTH_A,8))) = 0, 0, log2roundup(divroundup(C_WRITE_WIDTH_A,8)));
CONSTANT C_AXI_ADDR_WIDTH_LSB : integer := if_then_else((AXI_FULL_MEMORY_SLAVE = 1),0,LOWER_BOUND_VAL);
CONSTANT C_AXI_OS_WR : integer := 2;
-- SAFETY LOGIC related Signals
SIGNAL RSTA_SHFT_REG : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
SIGNAL POR_A : STD_LOGIC := '0';
SIGNAL RSTB_SHFT_REG : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
SIGNAL POR_B : STD_LOGIC := '0';
SIGNAL ENA_dly : STD_LOGIC := '0';
SIGNAL ENA_dly_D : STD_LOGIC := '0';
SIGNAL ENB_dly : STD_LOGIC := '0';
SIGNAL ENB_dly_D : STD_LOGIC := '0';
SIGNAL RSTA_I_SAFE : STD_LOGIC := '0';
SIGNAL RSTB_I_SAFE : STD_LOGIC := '0';
SIGNAL ENA_I_SAFE : STD_LOGIC := '0';
SIGNAL ENB_I_SAFE : STD_LOGIC := '0';
SIGNAL ram_rstram_a_busy : STD_LOGIC := '0';
SIGNAL ram_rstreg_a_busy : STD_LOGIC := '0';
SIGNAL ram_rstram_b_busy : STD_LOGIC := '0';
SIGNAL ram_rstreg_b_busy : STD_LOGIC := '0';
SIGNAL ENA_dly_reg : STD_LOGIC := '0';
SIGNAL ENB_dly_reg : STD_LOGIC := '0';
SIGNAL ENA_dly_reg_D : STD_LOGIC := '0';
SIGNAL ENB_dly_reg_D : STD_LOGIC := '0';
--**************************************************************************
BEGIN -- Architecture
--*************************************************************************
-- NO INPUT STAGE
--*************************************************************************
no_input_stage: IF (C_HAS_SOFTECC_INPUT_REGS_A=0) GENERATE
rsta_in <= RSTA;
ena_in <= ENA;
regcea_in <= REGCEA;
wea_in <= WEA;
addra_in <= ADDRA;
dina_in <= DINA;
injectsbiterr_in <= INJECTSBITERR;
injectdbiterr_in <= INJECTDBITERR;
END GENERATE no_input_stage;
--**************************************************************************
-- WITH INPUT STAGE
--**************************************************************************
has_input_stage: IF (C_HAS_SOFTECC_INPUT_REGS_A=1) GENERATE
PROCESS (CLKA)
BEGIN
IF (CLKA'EVENT AND CLKA = '1') THEN
rsta_in <= RSTA AFTER FLOP_DELAY;
ena_in <= ENA AFTER FLOP_DELAY;
regcea_in <= REGCEA AFTER FLOP_DELAY;
wea_in <= WEA AFTER FLOP_DELAY;
addra_in <= ADDRA AFTER FLOP_DELAY;
dina_in <= DINA AFTER FLOP_DELAY;
injectsbiterr_in <= INJECTSBITERR AFTER FLOP_DELAY;
injectdbiterr_in <= INJECTDBITERR AFTER FLOP_DELAY;
END IF;
END PROCESS;
END GENERATE has_input_stage;
--**************************************************************************
-- NO SAFETY LOGIC
--**************************************************************************
NO_SAFETY_CKT_GEN: IF(C_EN_SAFETY_CKT = 0) GENERATE
ENA_I_SAFE <= ena_in;
ENB_I_SAFE <= ENB;
RSTA_I_SAFE <= rsta_in;
RSTB_I_SAFE <= RSTB;
END GENERATE NO_SAFETY_CKT_GEN;
--**************************************************************************
-- SAFETY LOGIC
--**************************************************************************
SAFETY_CKT_GEN: IF(C_EN_SAFETY_CKT = 1) GENERATE
-- RESET SAFETY LOGIC Generation
-- POR Generation
------------------------------------------------------------------------------
-- Power-ON Reset Generation
------------------------------------------------------------------------------
RST_SHFT_LOGIC_A : PROCESS(CLKA)
BEGIN
IF RISING_EDGE(CLKA) THEN
RSTA_SHFT_REG(4 DOWNTO 0) <= RSTA_SHFT_REG(3 DOWNTO 0) & '1' AFTER FLOP_DELAY;
END IF;
END PROCESS RST_SHFT_LOGIC_A;
POR_RSTA_GEN : PROCESS(CLKA)
BEGIN
IF RISING_EDGE(CLKA) THEN
POR_A <= RSTA_SHFT_REG(4) xor RSTA_SHFT_REG(0) AFTER FLOP_DELAY;
END IF;
END PROCESS POR_RSTA_GEN;
RST_SHFT_LOGIC_B : PROCESS(CLKB)
BEGIN
IF RISING_EDGE(CLKB) THEN
RSTB_SHFT_REG(4 DOWNTO 0) <= RSTB_SHFT_REG(3 DOWNTO 0) & '1' AFTER FLOP_DELAY;
END IF;
END PROCESS RST_SHFT_LOGIC_B;
POR_RSTB_GEN : PROCESS(CLKB)
BEGIN
IF RISING_EDGE(CLKB) THEN
POR_B <= RSTB_SHFT_REG(4) xor RSTB_SHFT_REG(0) AFTER FLOP_DELAY;
END IF;
END PROCESS POR_RSTB_GEN;
-----------------------------------------------------------------------------
-- Fix for the AR42571
-----------------------------------------------------------------------------
-- Reset Generation
-----------------------------------------------------------------------------
RSTA_I_SAFE <= rsta_in OR POR_A;
SPRAM_RST: IF ((C_MEM_TYPE = 0) OR (C_MEM_TYPE = 3)) GENERATE
BEGIN
RSTB_I_SAFE <= '0';
END GENERATE SPRAM_RST;
nSPRAM_RST: IF ((C_MEM_TYPE /= 0) AND (C_MEM_TYPE /= 3)) GENERATE
BEGIN
RSTB_I_SAFE <= RSTB OR POR_B;
END GENERATE nSPRAM_RST;
-----------------------------------------------------------------------------
-- RSTA/B_BUSY Generation
-----------------------------------------------------------------------------
RSTA_BUSY_NO_REG: IF (C_HAS_MEM_OUTPUT_REGS_A=0 OR (C_HAS_MEM_OUTPUT_REGS_A=1 AND C_RSTRAM_A=1)) GENERATE
BEGIN
ram_rstram_a_busy <= rsta_in OR ENA_dly OR ENA_dly_D;
PROC_RSTA_BUSY_GEN : PROCESS(CLKA)
BEGIN
IF RISING_EDGE (CLKA) THEN
RSTA_BUSY <= ram_rstram_a_busy AFTER FLOP_DELAY;
END IF;
END PROCESS;
END GENERATE RSTA_BUSY_NO_REG;
RSTA_BUSY_WITH_REG: IF (C_HAS_MEM_OUTPUT_REGS_A=1 AND C_RSTRAM_A=0) GENERATE
BEGIN
ram_rstreg_a_busy <= rsta_in OR ENA_dly OR ENA_dly_reg_D;
PROC_RSTA_BUSY_GEN : PROCESS(CLKA)
BEGIN
IF RISING_EDGE (CLKA) THEN
RSTA_BUSY <= ram_rstreg_a_busy AFTER FLOP_DELAY;
END IF;
END PROCESS;
END GENERATE RSTA_BUSY_WITH_REG;
SPRAM_RST_BUSY: IF ((C_MEM_TYPE = 0) OR (C_MEM_TYPE = 3)) GENERATE
BEGIN
RSTB_BUSY <= '0';
END GENERATE SPRAM_RST_BUSY;
nSPRAM_RST_BUSY: IF ((C_MEM_TYPE /= 0) AND (C_MEM_TYPE /= 3)) GENERATE
BEGIN
RSTB_BUSY_NO_REG: IF (C_HAS_MEM_OUTPUT_REGS_B=0 OR (C_HAS_MEM_OUTPUT_REGS_B=1 AND C_RSTRAM_B=1)) GENERATE
BEGIN
ram_rstram_b_busy <= RSTB OR ENB_dly OR ENB_dly_D;
PROC_RSTB_BUSY_GEN : PROCESS(CLKB)
BEGIN
IF RISING_EDGE (CLKB) THEN
RSTB_BUSY <= ram_rstram_b_busy AFTER FLOP_DELAY;
END IF;
END PROCESS;
END GENERATE RSTB_BUSY_NO_REG;
RSTB_BUSY_WITH_REG: IF (C_HAS_MEM_OUTPUT_REGS_B=1 AND C_RSTRAM_B=0) GENERATE
BEGIN
ram_rstreg_b_busy <= RSTB OR ENB_dly OR ENB_dly_reg_D;
PROC_RSTB_BUSY_GEN : PROCESS(CLKB)
BEGIN
IF RISING_EDGE (CLKB) THEN
RSTB_BUSY <= ram_rstreg_b_busy AFTER FLOP_DELAY;
END IF;
END PROCESS;
END GENERATE RSTB_BUSY_WITH_REG;
END GENERATE nSPRAM_RST_BUSY;
-----------------------------------------------------------------------------
-- ENA/ENB Generation
-----------------------------------------------------------------------------
ENA_NO_REG: IF (C_HAS_MEM_OUTPUT_REGS_A=0 OR (C_HAS_MEM_OUTPUT_REGS_A=1 AND C_RSTRAM_A=1)) GENERATE
BEGIN
PROC_ENA_GEN : PROCESS(CLKA)
BEGIN
IF RISING_EDGE (CLKA) THEN
ENA_dly <= rsta_in AFTER FLOP_DELAY;
ENA_dly_D <= ENA_dly AFTER FLOP_DELAY;
END IF;
END PROCESS;
ENA_I_SAFE <= ENA_dly_D OR ena_in;
END GENERATE ENA_NO_REG;
ENA_WITH_REG: IF (C_HAS_MEM_OUTPUT_REGS_A=1 AND C_RSTRAM_A=0) GENERATE
BEGIN
PROC_ENA_GEN : PROCESS(CLKA)
BEGIN
IF RISING_EDGE (CLKA) THEN
ENA_dly_reg <= rsta_in AFTER FLOP_DELAY;
ENA_dly_reg_D <= ENA_dly_reg AFTER FLOP_DELAY;
END IF;
END PROCESS;
ENA_I_SAFE <= ENA_dly_reg_D OR ena_in;
END GENERATE ENA_WITH_REG;
SPRAM_ENB: IF ((C_MEM_TYPE = 0) OR (C_MEM_TYPE = 3)) GENERATE
BEGIN
ENB_I_SAFE <= '0';
END GENERATE SPRAM_ENB;
nSPRAM_ENB: IF ((C_MEM_TYPE /= 0) AND (C_MEM_TYPE /= 3)) GENERATE
BEGIN
ENB_NO_REG: IF (C_HAS_MEM_OUTPUT_REGS_B=0 OR (C_HAS_MEM_OUTPUT_REGS_B=1 AND C_RSTRAM_B=1)) GENERATE
BEGIN
PROC_ENB_GEN : PROCESS(CLKB)
BEGIN
IF RISING_EDGE (CLKB) THEN
ENB_dly <= RSTB AFTER FLOP_DELAY;
ENB_dly_D <= ENB_dly AFTER FLOP_DELAY;
END IF;
END PROCESS;
ENB_I_SAFE <= ENB_dly_D OR ENB;
END GENERATE ENB_NO_REG;
ENB_WITH_REG: IF (C_HAS_MEM_OUTPUT_REGS_B=1 AND C_RSTRAM_B=0) GENERATE
BEGIN
PROC_ENB_GEN : PROCESS(CLKB)
BEGIN
IF RISING_EDGE (CLKB) THEN
ENB_dly_reg <= RSTB AFTER FLOP_DELAY;
ENB_dly_reg_D <= ENB_dly_reg AFTER FLOP_DELAY;
END IF;
END PROCESS;
ENB_I_SAFE <= ENB_dly_reg_D OR ENB;
END GENERATE ENB_WITH_REG;
END GENERATE nSPRAM_ENB;
END GENERATE SAFETY_CKT_GEN;
--**************************************************************************
-- NATIVE MEMORY MODULE INSTANCE
--**************************************************************************
native_mem_module: IF (C_INTERFACE_TYPE = 0 AND C_ENABLE_32BIT_ADDRESS = 0) GENERATE
mem_module: blk_mem_gen_v8_3_0_mem_module
GENERIC MAP(
C_CORENAME => C_CORENAME,
C_FAMILY => if_then_else(equalIgnoreCase(C_FAMILY,"KINTEXUPLUS"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ZYNQUPLUS"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"VIRTEXUPLUS"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"VIRTEXU"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"KINTEXU"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"VIRTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QVIRTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QVIRTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"VIRTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"KINTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"KINTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QKINTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QKINTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ARTIX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ARTIX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QARTIX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QARTIX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"AARTIX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ZYNQ"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"AZYNQ"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QZYNQ"),"virtex7",C_FAMILY))))))))))))))))))))),
C_XDEVICEFAMILY => C_XDEVICEFAMILY,
C_USE_BRAM_BLOCK => C_USE_BRAM_BLOCK,
C_ENABLE_32BIT_ADDRESS => C_ENABLE_32BIT_ADDRESS,
C_MEM_TYPE => C_MEM_TYPE,
C_BYTE_SIZE => C_BYTE_SIZE,
C_ALGORITHM => C_ALGORITHM,
C_PRIM_TYPE => C_PRIM_TYPE,
C_LOAD_INIT_FILE => C_LOAD_INIT_FILE,
C_INIT_FILE_NAME => C_INIT_FILE_NAME,
C_INIT_FILE => C_INIT_FILE,
C_USE_DEFAULT_DATA => C_USE_DEFAULT_DATA,
C_DEFAULT_DATA => C_DEFAULT_DATA,
C_RST_TYPE => "SYNC",
C_HAS_RSTA => C_HAS_RSTA,
C_RST_PRIORITY_A => C_RST_PRIORITY_A,
C_RSTRAM_A => C_RSTRAM_A,
C_INITA_VAL => C_INITA_VAL,
C_HAS_ENA => C_HAS_ENA,
C_HAS_REGCEA => C_HAS_REGCEA,
C_USE_BYTE_WEA => C_USE_BYTE_WEA,
C_WEA_WIDTH => C_WEA_WIDTH,
C_WRITE_MODE_A => C_WRITE_MODE_A,
C_WRITE_WIDTH_A => C_WRITE_WIDTH_A,
C_READ_WIDTH_A => C_READ_WIDTH_A,
C_WRITE_DEPTH_A => C_WRITE_DEPTH_A,
C_READ_DEPTH_A => C_READ_DEPTH_A,
C_ADDRA_WIDTH => C_ADDRA_WIDTH,
C_HAS_RSTB => C_HAS_RSTB,
C_RST_PRIORITY_B => C_RST_PRIORITY_B,
C_RSTRAM_B => C_RSTRAM_B,
C_INITB_VAL => C_INITB_VAL,
C_HAS_ENB => C_HAS_ENB,
C_HAS_REGCEB => C_HAS_REGCEB,
C_USE_BYTE_WEB => C_USE_BYTE_WEB,
C_WEB_WIDTH => C_WEB_WIDTH,
C_WRITE_MODE_B => C_WRITE_MODE_B,
C_WRITE_WIDTH_B => C_WRITE_WIDTH_B,
C_READ_WIDTH_B => C_READ_WIDTH_B,
C_WRITE_DEPTH_B => C_WRITE_DEPTH_B,
C_READ_DEPTH_B => C_READ_DEPTH_B,
C_ADDRB_WIDTH => C_ADDRB_WIDTH,
C_HAS_MEM_OUTPUT_REGS_A => C_HAS_MEM_OUTPUT_REGS_A,
C_HAS_MEM_OUTPUT_REGS_B => C_HAS_MEM_OUTPUT_REGS_B,
C_HAS_MUX_OUTPUT_REGS_A => C_HAS_MUX_OUTPUT_REGS_A,
C_HAS_MUX_OUTPUT_REGS_B => C_HAS_MUX_OUTPUT_REGS_B,
C_HAS_SOFTECC_INPUT_REGS_A => C_HAS_SOFTECC_INPUT_REGS_A,
C_HAS_SOFTECC_OUTPUT_REGS_B => C_HAS_SOFTECC_OUTPUT_REGS_B,
C_MUX_PIPELINE_STAGES => C_MUX_PIPELINE_STAGES,
C_USE_SOFTECC => C_USE_SOFTECC,
C_USE_ECC => C_USE_ECC,
C_HAS_INJECTERR => C_HAS_INJECTERR,
C_SIM_COLLISION_CHECK => C_SIM_COLLISION_CHECK,
C_COMMON_CLK => C_COMMON_CLK,
FLOP_DELAY => FLOP_DELAY,
C_DISABLE_WARN_BHV_COLL => C_DISABLE_WARN_BHV_COLL,
C_EN_ECC_PIPE => C_EN_ECC_PIPE,
C_DISABLE_WARN_BHV_RANGE => C_DISABLE_WARN_BHV_RANGE
)
PORT MAP(
CLKA => CLKA,
RSTA => RSTA_I_SAFE,--rsta_in,
ENA => ENA_I_SAFE,--ena_in,
REGCEA => regcea_in,
WEA => wea_in,
ADDRA => addra_in,
DINA => dina_in,
DOUTA => DOUTA,
CLKB => CLKB,
RSTB => RSTB_I_SAFE,
ENB => ENB_I_SAFE,
REGCEB => REGCEB,
WEB => WEB,
ADDRB => ADDRB,
DINB => DINB,
DOUTB => DOUTB,
INJECTSBITERR => injectsbiterr_in,
INJECTDBITERR => injectdbiterr_in,
SBITERR => SBITERR,
DBITERR => DBITERR,
ECCPIPECE => ECCPIPECE,
SLEEP => SLEEP,
RDADDRECC => RDADDRECC
);
END GENERATE native_mem_module;
--**************************************************************************
-- NATIVE MEMORY MAPPED MODULE INSTANCE
--**************************************************************************
native_mem_map_module: IF (C_INTERFACE_TYPE = 0 AND C_ENABLE_32BIT_ADDRESS = 1) GENERATE
--**************************************************************************
-- NATIVE MEMORY MAPPED PARAMETERS
CONSTANT C_ADDRA_WIDTH_ACTUAL : integer := log2roundup(C_WRITE_DEPTH_A);
CONSTANT C_ADDRB_WIDTH_ACTUAL : integer := log2roundup(C_WRITE_DEPTH_B);
CONSTANT C_ADDRA_WIDTH_MSB : integer := C_ADDRA_WIDTH_ACTUAL+log2int(C_WRITE_WIDTH_A/8);
CONSTANT C_ADDRB_WIDTH_MSB : integer := C_ADDRB_WIDTH_ACTUAL+log2int(C_WRITE_WIDTH_B/8);
CONSTANT C_MEM_MAP_ADDRA_WIDTH_MSB : integer := C_ADDRA_WIDTH_MSB;
CONSTANT C_MEM_MAP_ADDRB_WIDTH_MSB : integer := C_ADDRB_WIDTH_MSB;
-- Data Width Number of LSB address bits to be discarded
-- 1 to 16 1
-- 17 to 32 2
-- 33 to 64 3
-- 65 to 128 4
-- 129 to 256 5
-- 257 to 512 6
-- 513 to 1024 7
-- The following two constants determine this.
CONSTANT MEM_MAP_LOWER_BOUND_VAL_A : integer := if_then_else((log2int(divroundup(C_WRITE_WIDTH_A,8))) = 0, 0, log2int(divroundup(C_WRITE_WIDTH_A,8)));
CONSTANT MEM_MAP_LOWER_BOUND_VAL_B : integer := if_then_else((log2int(divroundup(C_WRITE_WIDTH_B,8))) = 0, 0, log2int(divroundup(C_WRITE_WIDTH_B,8)));
CONSTANT C_MEM_MAP_ADDRA_WIDTH_LSB : integer := MEM_MAP_LOWER_BOUND_VAL_A;
CONSTANT C_MEM_MAP_ADDRB_WIDTH_LSB : integer := MEM_MAP_LOWER_BOUND_VAL_B;
SIGNAL rdaddrecc_i : STD_LOGIC_VECTOR(C_ADDRB_WIDTH_ACTUAL-1 DOWNTO 0) := (OTHERS => '0');
--**************************************************************************
BEGIN
RDADDRECC(C_ADDRB_WIDTH-1 DOWNTO C_MEM_MAP_ADDRB_WIDTH_MSB) <= (OTHERS => '0');
RDADDRECC(C_MEM_MAP_ADDRB_WIDTH_MSB-1 DOWNTO C_MEM_MAP_ADDRB_WIDTH_LSB) <= rdaddrecc_i;
RDADDRECC(C_MEM_MAP_ADDRB_WIDTH_LSB-1 DOWNTO 0) <= (OTHERS => '0');
mem_map_module: blk_mem_gen_v8_3_0_mem_module
GENERIC MAP(
C_CORENAME => C_CORENAME,
C_FAMILY => if_then_else(equalIgnoreCase(C_FAMILY,"VIRTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QVIRTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QVIRTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"KINTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"KINTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QKINTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QKINTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ARTIX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ARTIX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QARTIX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QARTIX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"AARTIX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ZYNQ"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"AZYNQ"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QZYNQ"),"virtex7",C_FAMILY))))))))))))))),
C_XDEVICEFAMILY => C_XDEVICEFAMILY,
C_USE_BRAM_BLOCK => C_USE_BRAM_BLOCK,
C_ENABLE_32BIT_ADDRESS => C_ENABLE_32BIT_ADDRESS,
C_MEM_TYPE => C_MEM_TYPE,
C_BYTE_SIZE => C_BYTE_SIZE,
C_ALGORITHM => C_ALGORITHM,
C_PRIM_TYPE => C_PRIM_TYPE,
C_LOAD_INIT_FILE => C_LOAD_INIT_FILE,
C_INIT_FILE_NAME => C_INIT_FILE_NAME,
C_INIT_FILE => C_INIT_FILE,
C_USE_DEFAULT_DATA => C_USE_DEFAULT_DATA,
C_DEFAULT_DATA => C_DEFAULT_DATA,
C_RST_TYPE => "SYNC",
C_HAS_RSTA => C_HAS_RSTA,
C_RST_PRIORITY_A => C_RST_PRIORITY_A,
C_RSTRAM_A => C_RSTRAM_A,
C_INITA_VAL => C_INITA_VAL,
C_HAS_ENA => C_HAS_ENA,
C_HAS_REGCEA => C_HAS_REGCEA,
C_USE_BYTE_WEA => C_USE_BYTE_WEA,
C_WEA_WIDTH => C_WEA_WIDTH,
C_WRITE_MODE_A => C_WRITE_MODE_A,
C_WRITE_WIDTH_A => C_WRITE_WIDTH_A,
C_READ_WIDTH_A => C_READ_WIDTH_A,
C_WRITE_DEPTH_A => C_WRITE_DEPTH_A,
C_READ_DEPTH_A => C_READ_DEPTH_A,
C_ADDRA_WIDTH => C_ADDRA_WIDTH_ACTUAL,
C_HAS_RSTB => C_HAS_RSTB,
C_RST_PRIORITY_B => C_RST_PRIORITY_B,
C_RSTRAM_B => C_RSTRAM_B,
C_INITB_VAL => C_INITB_VAL,
C_HAS_ENB => C_HAS_ENB,
C_HAS_REGCEB => C_HAS_REGCEB,
C_USE_BYTE_WEB => C_USE_BYTE_WEB,
C_WEB_WIDTH => C_WEB_WIDTH,
C_WRITE_MODE_B => C_WRITE_MODE_B,
C_WRITE_WIDTH_B => C_WRITE_WIDTH_B,
C_READ_WIDTH_B => C_READ_WIDTH_B,
C_WRITE_DEPTH_B => C_WRITE_DEPTH_B,
C_READ_DEPTH_B => C_READ_DEPTH_B,
C_ADDRB_WIDTH => C_ADDRB_WIDTH_ACTUAL,
C_HAS_MEM_OUTPUT_REGS_A => C_HAS_MEM_OUTPUT_REGS_A,
C_HAS_MEM_OUTPUT_REGS_B => C_HAS_MEM_OUTPUT_REGS_B,
C_HAS_MUX_OUTPUT_REGS_A => C_HAS_MUX_OUTPUT_REGS_A,
C_HAS_MUX_OUTPUT_REGS_B => C_HAS_MUX_OUTPUT_REGS_B,
C_HAS_SOFTECC_INPUT_REGS_A => C_HAS_SOFTECC_INPUT_REGS_A,
C_HAS_SOFTECC_OUTPUT_REGS_B => C_HAS_SOFTECC_OUTPUT_REGS_B,
C_MUX_PIPELINE_STAGES => C_MUX_PIPELINE_STAGES,
C_USE_SOFTECC => C_USE_SOFTECC,
C_USE_ECC => C_USE_ECC,
C_HAS_INJECTERR => C_HAS_INJECTERR,
C_SIM_COLLISION_CHECK => C_SIM_COLLISION_CHECK,
C_COMMON_CLK => C_COMMON_CLK,
FLOP_DELAY => FLOP_DELAY,
C_DISABLE_WARN_BHV_COLL => C_DISABLE_WARN_BHV_COLL,
C_EN_ECC_PIPE => C_EN_ECC_PIPE,
C_DISABLE_WARN_BHV_RANGE => C_DISABLE_WARN_BHV_RANGE
)
PORT MAP(
CLKA => CLKA,
RSTA => RSTA_I_SAFE,
ENA => ENA_I_SAFE,
REGCEA => regcea_in,
WEA => wea_in,
ADDRA => addra_in(C_MEM_MAP_ADDRA_WIDTH_MSB-1 DOWNTO C_MEM_MAP_ADDRA_WIDTH_LSB),
DINA => dina_in,
DOUTA => DOUTA,
CLKB => CLKB,
RSTB => RSTB_I_SAFE,
ENB => ENB_I_SAFE,
REGCEB => REGCEB,
WEB => WEB,
ADDRB => ADDRB(C_MEM_MAP_ADDRB_WIDTH_MSB-1 DOWNTO C_MEM_MAP_ADDRB_WIDTH_LSB),
DINB => DINB,
DOUTB => DOUTB,
INJECTSBITERR => injectsbiterr_in,
INJECTDBITERR => injectdbiterr_in,
SBITERR => SBITERR,
DBITERR => DBITERR,
ECCPIPECE => ECCPIPECE,
SLEEP => SLEEP,
RDADDRECC => rdaddrecc_i
);
END GENERATE native_mem_map_module;
--****************************************************************************
-- AXI MEMORY MODULE INSTANCE
--****************************************************************************
axi_mem_module: IF (C_INTERFACE_TYPE = 1) GENERATE
SIGNAL s_axi_rid_c : STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL s_axi_rdata_c : STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL s_axi_rresp_c : STD_LOGIC_VECTOR(2-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL s_axi_rlast_c : STD_LOGIC := '0';
SIGNAL s_axi_rvalid_c : STD_LOGIC := '0';
SIGNAL s_axi_rready_c : STD_LOGIC := '0';
SIGNAL regceb_c : STD_LOGIC := '0';
BEGIN
s_aresetn_a_c <= NOT S_ARESETN;
S_AXI_BRESP <= (OTHERS => '0');
s_axi_rresp_c <= (OTHERS => '0');
no_regs: IF (C_HAS_MEM_OUTPUT_REGS_B = 0 AND C_HAS_MUX_OUTPUT_REGS_B = 0 ) GENERATE
S_AXI_RDATA <= s_axi_rdata_c;
S_AXI_RLAST <= s_axi_rlast_c;
S_AXI_RVALID <= s_axi_rvalid_c;
S_AXI_RID <= s_axi_rid_c;
S_AXI_RRESP <= s_axi_rresp_c;
s_axi_rready_c <= S_AXI_RREADY;
END GENERATE no_regs;
has_regs_fwd: IF (C_HAS_MUX_OUTPUT_REGS_B = 1 OR C_HAS_MEM_OUTPUT_REGS_B = 1) GENERATE
CONSTANT C_AXI_PAYLOAD : INTEGER := if_then_else((C_HAS_MUX_OUTPUT_REGS_B = 1),C_WRITE_WIDTH_B+C_AXI_ID_WIDTH+3,C_AXI_ID_WIDTH+3);
SIGNAL s_axi_payload_c : STD_LOGIC_VECTOR(C_AXI_PAYLOAD-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL m_axi_payload_c : STD_LOGIC_VECTOR(C_AXI_PAYLOAD-1 DOWNTO 0) := (OTHERS => '0');
BEGIN
has_regceb: IF (C_HAS_MEM_OUTPUT_REGS_B = 1) GENERATE
regceb_c <= s_axi_rvalid_c AND s_axi_rready_c;
END GENERATE has_regceb;
no_regceb: IF (C_HAS_MEM_OUTPUT_REGS_B = 0) GENERATE
regceb_c <= REGCEB;
END GENERATE no_regceb;
only_core_op_regs: IF (C_HAS_MUX_OUTPUT_REGS_B = 1) GENERATE
s_axi_payload_c <= s_axi_rid_c & s_axi_rdata_c & s_axi_rresp_c & s_axi_rlast_c;
S_AXI_RID <= m_axi_payload_c(C_AXI_PAYLOAD-1 DOWNTO C_AXI_PAYLOAD-C_AXI_ID_WIDTH);
S_AXI_RDATA <= m_axi_payload_c(C_AXI_PAYLOAD-C_AXI_ID_WIDTH-1 DOWNTO C_AXI_PAYLOAD-C_AXI_ID_WIDTH-C_WRITE_WIDTH_B);
S_AXI_RRESP <= m_axi_payload_c(2 DOWNTO 1);
S_AXI_RLAST <= m_axi_payload_c(0);
END GENERATE only_core_op_regs;
only_emb_op_regs: IF (C_HAS_MEM_OUTPUT_REGS_B = 1) GENERATE
s_axi_payload_c <= s_axi_rid_c & s_axi_rresp_c & s_axi_rlast_c;
S_AXI_RDATA <= s_axi_rdata_c;
S_AXI_RID <= m_axi_payload_c(C_AXI_PAYLOAD-1 DOWNTO C_AXI_PAYLOAD-C_AXI_ID_WIDTH);
S_AXI_RRESP <= m_axi_payload_c(2 DOWNTO 1);
S_AXI_RLAST <= m_axi_payload_c(0);
END GENERATE only_emb_op_regs;
axi_regs_inst : blk_mem_axi_regs_fwd_v8_3
GENERIC MAP(
C_DATA_WIDTH => C_AXI_PAYLOAD
)
PORT MAP (
ACLK => S_ACLK,
ARESET => s_aresetn_a_c,
S_VALID => s_axi_rvalid_c,
S_READY => s_axi_rready_c,
S_PAYLOAD_DATA => s_axi_payload_c,
M_VALID => S_AXI_RVALID,
M_READY => S_AXI_RREADY,
M_PAYLOAD_DATA => m_axi_payload_c
);
END GENERATE has_regs_fwd;
axi_wr_fsm : blk_mem_axi_write_wrapper_beh
GENERIC MAP(
-- AXI Interface related parameters start here
C_INTERFACE_TYPE => C_INTERFACE_TYPE,
C_AXI_TYPE => C_AXI_TYPE,
C_AXI_SLAVE_TYPE => C_AXI_SLAVE_TYPE,
C_MEMORY_TYPE => C_MEM_TYPE,
C_WRITE_DEPTH_A => C_WRITE_DEPTH_A,
C_AXI_AWADDR_WIDTH => if_then_else((AXI_FULL_MEMORY_SLAVE = 1),C_AXI_ADDR_WIDTH,C_AXI_ADDR_WIDTH-C_AXI_ADDR_WIDTH_LSB),
C_HAS_AXI_ID => C_HAS_AXI_ID,
C_AXI_ID_WIDTH => C_AXI_ID_WIDTH,
C_ADDRA_WIDTH => C_ADDRA_WIDTH,
C_AXI_WDATA_WIDTH => C_WRITE_WIDTH_A,
C_AXI_OS_WR => C_AXI_OS_WR
)
PORT MAP(
-- AXI Global Signals
S_ACLK => S_ACLK,
S_ARESETN => s_aresetn_a_c,
-- AXI Full/Lite Slave Write Interface
S_AXI_AWADDR => S_AXI_AWADDR(C_AXI_ADDR_WIDTH_MSB-1 DOWNTO C_AXI_ADDR_WIDTH_LSB),
S_AXI_AWLEN => S_AXI_AWLEN,
S_AXI_AWID => S_AXI_AWID,
S_AXI_AWSIZE => S_AXI_AWSIZE,
S_AXI_AWBURST => S_AXI_AWBURST,
S_AXI_AWVALID => S_AXI_AWVALID,
S_AXI_AWREADY => S_AXI_AWREADY,
S_AXI_WVALID => S_AXI_WVALID,
S_AXI_WREADY => S_AXI_WREADY,
S_AXI_BVALID => S_AXI_BVALID,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_BID => S_AXI_BID,
-- Signals for BRAM interface
S_AXI_AWADDR_OUT =>s_axi_awaddr_out_c,
S_AXI_WR_EN =>s_axi_wr_en_c
);
mem_module: blk_mem_gen_v8_3_0_mem_module
GENERIC MAP(
C_CORENAME => C_CORENAME,
C_FAMILY => if_then_else(equalIgnoreCase(C_FAMILY,"VIRTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QVIRTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QVIRTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"KINTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"KINTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QKINTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QKINTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ARTIX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ARTIX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QARTIX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QARTIX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"AARTIX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ZYNQ"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"AZYNQ"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QZYNQ"),"virtex7",C_FAMILY))))))))))))))),
C_XDEVICEFAMILY => C_XDEVICEFAMILY,
C_USE_BRAM_BLOCK => C_USE_BRAM_BLOCK,
C_ENABLE_32BIT_ADDRESS => C_ENABLE_32BIT_ADDRESS,
C_MEM_TYPE => C_MEM_TYPE,
C_BYTE_SIZE => C_BYTE_SIZE,
C_ALGORITHM => C_ALGORITHM,
C_PRIM_TYPE => C_PRIM_TYPE,
C_LOAD_INIT_FILE => C_LOAD_INIT_FILE,
C_INIT_FILE_NAME => C_INIT_FILE_NAME,
C_INIT_FILE => C_INIT_FILE,
C_USE_DEFAULT_DATA => C_USE_DEFAULT_DATA,
C_DEFAULT_DATA => C_DEFAULT_DATA,
C_RST_TYPE => "SYNC",
C_HAS_RSTA => C_HAS_RSTA,
C_RST_PRIORITY_A => C_RST_PRIORITY_A,
C_RSTRAM_A => C_RSTRAM_A,
C_INITA_VAL => C_INITA_VAL,
C_HAS_ENA => 1, -- For AXI, Read Enable is always C_HAS_ENA,
C_HAS_REGCEA => C_HAS_REGCEA,
C_USE_BYTE_WEA => 1, -- For AXI C_USE_BYTE_WEA is always 1,
C_WEA_WIDTH => C_WEA_WIDTH,
C_WRITE_MODE_A => C_WRITE_MODE_A,
C_WRITE_WIDTH_A => C_WRITE_WIDTH_A,
C_READ_WIDTH_A => C_READ_WIDTH_A,
C_WRITE_DEPTH_A => C_WRITE_DEPTH_A,
C_READ_DEPTH_A => C_READ_DEPTH_A,
C_ADDRA_WIDTH => C_ADDRA_WIDTH,
C_HAS_RSTB => C_HAS_RSTB,
C_RST_PRIORITY_B => C_RST_PRIORITY_B,
C_RSTRAM_B => C_RSTRAM_B,
C_INITB_VAL => C_INITB_VAL,
C_HAS_ENB => 1, -- For AXI, Read Enable is always C_HAS_ENB,
C_HAS_REGCEB => C_HAS_MEM_OUTPUT_REGS_B,
C_USE_BYTE_WEB => 1, -- For AXI C_USE_BYTE_WEB is always 1,
C_WEB_WIDTH => C_WEB_WIDTH,
C_WRITE_MODE_B => C_WRITE_MODE_B,
C_WRITE_WIDTH_B => C_WRITE_WIDTH_B,
C_READ_WIDTH_B => C_READ_WIDTH_B,
C_WRITE_DEPTH_B => C_WRITE_DEPTH_B,
C_READ_DEPTH_B => C_READ_DEPTH_B,
C_ADDRB_WIDTH => C_ADDRB_WIDTH,
C_HAS_MEM_OUTPUT_REGS_A => 0, --For AXI, Primitive Registers A is not supported C_HAS_MEM_OUTPUT_REGS_A,
C_HAS_MEM_OUTPUT_REGS_B => C_HAS_MEM_OUTPUT_REGS_B,
C_HAS_MUX_OUTPUT_REGS_A => 0,
C_HAS_MUX_OUTPUT_REGS_B => 0,
C_HAS_SOFTECC_INPUT_REGS_A => C_HAS_SOFTECC_INPUT_REGS_A,
C_HAS_SOFTECC_OUTPUT_REGS_B => C_HAS_SOFTECC_OUTPUT_REGS_B,
C_MUX_PIPELINE_STAGES => C_MUX_PIPELINE_STAGES,
C_USE_SOFTECC => C_USE_SOFTECC,
C_USE_ECC => C_USE_ECC,
C_HAS_INJECTERR => C_HAS_INJECTERR,
C_SIM_COLLISION_CHECK => C_SIM_COLLISION_CHECK,
C_COMMON_CLK => C_COMMON_CLK,
FLOP_DELAY => FLOP_DELAY,
C_DISABLE_WARN_BHV_COLL => C_DISABLE_WARN_BHV_COLL,
C_EN_ECC_PIPE => 0,
C_DISABLE_WARN_BHV_RANGE => C_DISABLE_WARN_BHV_RANGE
)
PORT MAP(
--Port A:
CLKA => S_AClk,
RSTA => s_aresetn_a_c,
ENA => s_axi_wr_en_c,
REGCEA => regcea_in,
WEA => S_AXI_WSTRB,
ADDRA => s_axi_awaddr_out_c,
DINA => S_AXI_WDATA,
DOUTA => DOUTA,
--Port B:
CLKB => S_AClk,
RSTB => s_aresetn_a_c,
ENB => s_axi_rd_en_c,
REGCEB => regceb_c,
WEB => (OTHERS => '0'),
ADDRB => s_axi_araddr_out_c,
DINB => DINB,
DOUTB => s_axi_rdata_c,
INJECTSBITERR => injectsbiterr_in,
INJECTDBITERR => injectdbiterr_in,
SBITERR => SBITERR,
DBITERR => DBITERR,
ECCPIPECE => '0',
SLEEP => '0',
RDADDRECC => RDADDRECC
);
axi_rd_sm : blk_mem_axi_read_wrapper_beh
GENERIC MAP (
-- AXI Interface related parameters start here
C_INTERFACE_TYPE => C_INTERFACE_TYPE,
C_AXI_TYPE => C_AXI_TYPE,
C_AXI_SLAVE_TYPE => C_AXI_SLAVE_TYPE,
C_MEMORY_TYPE => C_MEM_TYPE,
C_WRITE_WIDTH_A => C_WRITE_WIDTH_A,
C_ADDRA_WIDTH => C_ADDRA_WIDTH,
C_AXI_PIPELINE_STAGES => 1,
C_AXI_ARADDR_WIDTH => if_then_else((AXI_FULL_MEMORY_SLAVE = 1),C_AXI_ADDR_WIDTH,C_AXI_ADDR_WIDTH-C_AXI_ADDR_WIDTH_LSB),
C_HAS_AXI_ID => C_HAS_AXI_ID,
C_AXI_ID_WIDTH => C_AXI_ID_WIDTH,
C_ADDRB_WIDTH => C_ADDRB_WIDTH
)
PORT MAP(
-- AXI Global Signals
S_ACLK => S_AClk,
S_ARESETN => s_aresetn_a_c,
-- AXI Full/Lite Read Side
S_AXI_ARADDR => S_AXI_ARADDR(C_AXI_ADDR_WIDTH_MSB-1 DOWNTO C_AXI_ADDR_WIDTH_LSB),
S_AXI_ARLEN => S_AXI_ARLEN,
S_AXI_ARSIZE => S_AXI_ARSIZE,
S_AXI_ARBURST => S_AXI_ARBURST,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_RLAST => s_axi_rlast_c,
S_AXI_RVALID => s_axi_rvalid_c,
S_AXI_RREADY => s_axi_rready_c,
S_AXI_ARID => S_AXI_ARID,
S_AXI_RID => s_axi_rid_c,
-- AXI Full/Lite Read FSM Outputs
S_AXI_ARADDR_OUT => s_axi_araddr_out_c,
S_AXI_RD_EN => s_axi_rd_en_c
);
END GENERATE axi_mem_module;
END behavioral;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity beh_ff_clr is
generic(
INIT : std_logic := '0'
);
port(
Q : out std_logic;
C : in std_logic;
CLR : in std_logic;
D : in std_logic
);
end beh_ff_clr;
architecture beh_ff_clr_arch of beh_ff_clr is
signal q_o : std_logic := INIT;
begin
Q <= q_o;
VITALBehavior : process(CLR, C)
begin
if (CLR = '1') then
q_o <= '0';
elsif (rising_edge(C)) then
q_o <= D after 100 ps;
end if;
end process;
end beh_ff_clr_arch;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity beh_ff_ce is
generic(
INIT : std_logic := '0'
);
port(
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
CLR : in std_logic;
D : in std_logic
);
end beh_ff_ce;
architecture beh_ff_ce_arch of beh_ff_ce is
signal q_o : std_logic := INIT;
begin
Q <= q_o;
VITALBehavior : process(C, CLR)
begin
if (CLR = '1') then
q_o <= '0';
elsif (rising_edge(C)) then
if (CE = '1') then
q_o <= D after 100 ps;
end if;
end if;
end process;
end beh_ff_ce_arch;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity beh_ff_pre is
generic(
INIT : std_logic := '1'
);
port(
Q : out std_logic;
C : in std_logic;
D : in std_logic;
PRE : in std_logic
);
end beh_ff_pre;
architecture beh_ff_pre_arch of beh_ff_pre is
signal q_o : std_logic := INIT;
begin
Q <= q_o;
VITALBehavior : process(C, PRE)
begin
if (PRE = '1') then
q_o <= '1';
elsif (C' event and C = '1') then
q_o <= D after 100 ps;
end if;
end process;
end beh_ff_pre_arch;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity beh_muxf7 is
port(
O : out std_ulogic;
I0 : in std_ulogic;
I1 : in std_ulogic;
S : in std_ulogic
);
end beh_muxf7;
architecture beh_muxf7_arch of beh_muxf7 is
begin
VITALBehavior : process (I0, I1, S)
begin
if (S = '0') then
O <= I0;
else
O <= I1;
end if;
end process;
end beh_muxf7_arch;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
entity STATE_LOGIC is
generic(
INIT : std_logic_vector(63 downto 0) := X"0000000000000000"
);
port(
O : out std_logic := '0';
I0 : in std_logic := '0';
I1 : in std_logic := '0';
I2 : in std_logic := '0';
I3 : in std_logic := '0';
I4 : in std_logic := '0';
I5 : in std_logic := '0'
);
end STATE_LOGIC;
architecture STATE_LOGIC_arch of STATE_LOGIC is
constant INIT_reg : std_logic_vector(63 downto 0) := INIT;
begin
LUT_beh:process (I0, I1, I2, I3, I4, I5)
variable I_reg : std_logic_vector(5 downto 0);
begin
I_reg := I5 & I4 & I3 & I2 & I1 & I0;
O <= INIT_reg(conv_integer(I_reg));
end process;
end STATE_LOGIC_arch;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
package mouse_ref_pkg is
component MouseRefComp
port (
clk : in std_logic;
resolution : in std_logic;
rst : in std_logic;
switch : in std_logic;
left : out std_logic;
middle : out std_logic;
new_event : out std_logic;
right : out std_logic;
busy : out std_logic;
xpos : out std_logic_vector (9 downto 0);
ypos : out std_logic_vector (9 downto 0);
zpos : out std_logic_vector (3 downto 0);
ps2_clk : inout std_logic;
ps2_data : inout std_logic
);
end component;
component cdiv
port (
cin : in std_logic;
tcvl : in integer;
cout : out std_logic
);
end component;
component mouse_controller
port (
clk : in std_logic;
rst : in std_logic;
read : in std_logic;
err : in std_logic;
rx_data : in std_logic_vector(7 downto 0);
xpos : out std_logic_vector(9 downto 0);
ypos : out std_logic_vector(9 downto 0);
zpos : out std_logic_vector(3 downto 0);
left : out std_logic;
middle : out std_logic;
right : out std_logic;
new_event : out std_logic;
tx_data : out std_logic_vector(7 downto 0);
write : out std_logic;
value : in std_logic_vector(9 downto 0);
setx : in std_logic;
sety : in std_logic;
setmax_x : in std_logic;
setmax_y : in std_logic
);
end component;
component resolution_mouse_informer
port (
clk : in std_logic;
rst : in std_logic;
resolution : in std_logic;
switch : in std_logic;
value : out std_logic_vector(9 downto 0);
setx : out std_logic;
sety : out std_logic;
setmax_x : out std_logic;
setmax_y : out std_logic
);
end component;
component ps2interface
port (
ps2_clk : inout std_logic;
ps2_data : inout std_logic;
clk : in std_logic;
rst : in std_logic;
tx_data : in std_logic_vector(7 downto 0);
write : in std_logic;
rx_data : out std_logic_vector(7 downto 0);
read : out std_logic;
busy : out std_logic;
err : out std_logic
);
end component;
end mouse_ref_pkg;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_dma_0_wrapper_fifo_generator_v9_3_2_synth.vhd
--
-- Description:
-- This is the demo testbench for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.STD_LOGIC_1164.ALL;
USE ieee.STD_LOGIC_unsigned.ALL;
USE IEEE.STD_LOGIC_arith.ALL;
USE ieee.numeric_std.ALL;
USE ieee.STD_LOGIC_misc.ALL;
LIBRARY std;
USE std.textio.ALL;
LIBRARY work;
USE work.system_axi_dma_0_wrapper_fifo_generator_v9_3_2_pkg.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY system_axi_dma_0_wrapper_fifo_generator_v9_3_2_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE simulation_arch OF system_axi_dma_0_wrapper_fifo_generator_v9_3_2_synth IS
-- FIFO interface signal declarations
SIGNAL clk_i : STD_LOGIC;
SIGNAL data_count : STD_LOGIC_VECTOR(3-1 DOWNTO 0);
SIGNAL wr_ack : STD_LOGIC;
SIGNAL valid : STD_LOGIC;
SIGNAL almost_empty : STD_LOGIC;
SIGNAL srst : STD_LOGIC;
SIGNAL wr_en : STD_LOGIC;
SIGNAL rd_en : STD_LOGIC;
SIGNAL din : STD_LOGIC_VECTOR(9-1 DOWNTO 0);
SIGNAL dout : STD_LOGIC_VECTOR(9-1 DOWNTO 0);
SIGNAL full : STD_LOGIC;
SIGNAL empty : STD_LOGIC;
-- TB Signals
SIGNAL wr_data : STD_LOGIC_VECTOR(9-1 DOWNTO 0);
SIGNAL dout_i : STD_LOGIC_VECTOR(9-1 DOWNTO 0);
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL full_i : STD_LOGIC := '0';
SIGNAL empty_i : STD_LOGIC := '0';
SIGNAL almost_full_i : STD_LOGIC := '0';
SIGNAL almost_empty_i : STD_LOGIC := '0';
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL dout_chk_i : STD_LOGIC := '0';
SIGNAL rst_int_rd : STD_LOGIC := '0';
SIGNAL rst_int_wr : STD_LOGIC := '0';
SIGNAL rst_gen_rd : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL rst_s_wr3 : STD_LOGIC := '0';
SIGNAL rst_s_rd : STD_LOGIC := '0';
SIGNAL reset_en : STD_LOGIC := '0';
SIGNAL rst_async_rd1 : STD_LOGIC := '0';
SIGNAL rst_async_rd2 : STD_LOGIC := '0';
SIGNAL rst_async_rd3 : STD_LOGIC := '0';
SIGNAL rst_sync_rd1 : STD_LOGIC := '0';
SIGNAL rst_sync_rd2 : STD_LOGIC := '0';
SIGNAL rst_sync_rd3 : STD_LOGIC := '0';
BEGIN
---- Reset generation logic -----
rst_int_wr <= rst_async_rd3 OR rst_s_rd;
rst_int_rd <= rst_async_rd3 OR rst_s_rd;
--Testbench reset synchronization
PROCESS(clk_i,RESET)
BEGIN
IF(RESET = '1') THEN
rst_async_rd1 <= '1';
rst_async_rd2 <= '1';
rst_async_rd3 <= '1';
ELSIF(clk_i'event AND clk_i='1') THEN
rst_async_rd1 <= RESET;
rst_async_rd2 <= rst_async_rd1;
rst_async_rd3 <= rst_async_rd2;
END IF;
END PROCESS;
--Synchronous reset generation for FIFO core
PROCESS(clk_i)
BEGIN
IF(clk_i'event AND clk_i='1') THEN
rst_sync_rd1 <= RESET;
rst_sync_rd2 <= rst_sync_rd1;
rst_sync_rd3 <= rst_sync_rd2;
END IF;
END PROCESS;
--Soft reset for core and testbench
PROCESS(clk_i)
BEGIN
IF(clk_i'event AND clk_i='1') THEN
rst_gen_rd <= rst_gen_rd + "1";
IF(reset_en = '1' AND AND_REDUCE(rst_gen_rd) = '1') THEN
rst_s_rd <= '1';
assert false
report "Reset applied..Memory Collision checks are not valid"
severity note;
ELSE
IF(AND_REDUCE(rst_gen_rd) = '1' AND rst_s_rd = '1') THEN
rst_s_rd <= '0';
assert false
report "Reset removed..Memory Collision checks are valid"
severity note;
END IF;
END IF;
END IF;
END PROCESS;
------------------
---- Clock buffers for testbench ----
clk_i <= CLK;
------------------
srst <= rst_sync_rd3 OR rst_s_rd AFTER 50 ns;
din <= wr_data;
dout_i <= dout;
wr_en <= wr_en_i;
rd_en <= rd_en_i;
full_i <= full;
empty_i <= empty;
almost_empty_i <= almost_empty;
fg_dg_nv: system_axi_dma_0_wrapper_fifo_generator_v9_3_2_dgen
GENERIC MAP (
C_DIN_WIDTH => 9,
C_DOUT_WIDTH => 9,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP ( -- Write Port
RESET => rst_int_wr,
WR_CLK => clk_i,
PRC_WR_EN => prc_we_i,
FULL => full_i,
WR_EN => wr_en_i,
WR_DATA => wr_data
);
fg_dv_nv: system_axi_dma_0_wrapper_fifo_generator_v9_3_2_dverif
GENERIC MAP (
C_DOUT_WIDTH => 9,
C_DIN_WIDTH => 9,
C_USE_EMBEDDED_REG => 0,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP(
RESET => rst_int_rd,
RD_CLK => clk_i,
PRC_RD_EN => prc_re_i,
RD_EN => rd_en_i,
EMPTY => empty_i,
DATA_OUT => dout_i,
DOUT_CHK => dout_chk_i
);
fg_pc_nv: system_axi_dma_0_wrapper_fifo_generator_v9_3_2_pctrl
GENERIC MAP (
AXI_CHANNEL => "Native",
C_APPLICATION_TYPE => 0,
C_DOUT_WIDTH => 9,
C_DIN_WIDTH => 9,
C_WR_PNTR_WIDTH => 3,
C_RD_PNTR_WIDTH => 3,
C_CH_TYPE => 0,
FREEZEON_ERROR => FREEZEON_ERROR,
TB_SEED => TB_SEED,
TB_STOP_CNT => TB_STOP_CNT
)
PORT MAP(
RESET_WR => rst_int_wr,
RESET_RD => rst_int_rd,
RESET_EN => reset_en,
WR_CLK => clk_i,
RD_CLK => clk_i,
PRC_WR_EN => prc_we_i,
PRC_RD_EN => prc_re_i,
FULL => full_i,
ALMOST_FULL => almost_full_i,
ALMOST_EMPTY => almost_empty_i,
DOUT_CHK => dout_chk_i,
EMPTY => empty_i,
DATA_IN => wr_data,
DATA_OUT => dout,
SIM_DONE => SIM_DONE,
STATUS => STATUS
);
system_axi_dma_0_wrapper_fifo_generator_v9_3_2_inst : system_axi_dma_0_wrapper_fifo_generator_v9_3_2_exdes
PORT MAP (
CLK => clk_i,
DATA_COUNT => data_count,
WR_ACK => wr_ack,
VALID => valid,
ALMOST_EMPTY => almost_empty,
SRST => srst,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
END ARCHITECTURE;
|
package pkgc is
constant width : natural;
end pkgc;
package body pkgc is
constant width : natural := 4;
end pkgc;
use work.pkgc.all;
package pkgcomp is
component comp is
generic (val : bit_vector (width -1 downto 0));
port (b : out bit);
end component;
end pkgcomp;
use work.pkgc.all;
entity comp is
generic (val : bit_vector (width -1 downto 0));
port (b : out bit);
end comp;
architecture behav of comp is
begin
b <= val (val'left);
end behav;
entity repro is
end repro;
use work.pkgc.all;
use work.pkgcomp.all;
architecture behav of repro is
signal res : bit;
begin
inst : comp
generic map (val => "0010")
port map (b => res );
end behav;
|
-- new_component.vhd
-- This file was auto-generated as a prototype implementation of a module
-- created in component editor. It ties off all outputs to ground and
-- ignores all inputs. It needs to be edited to make it do something
-- useful.
--
-- This file will not be automatically regenerated. You should check it in
-- to your version control system if you want to keep it.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity ip_pwm_top is
port (
avs_s0_address : in std_logic_vector(7 downto 0) := (others => '0'); -- avs_s0.address
avs_s0_read : in std_logic := '0'; -- .read
avs_s0_readdata : out std_logic_vector(31 downto 0); -- .readdata
avs_s0_write : in std_logic := '0'; -- .write
avs_s0_writedata : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata
avs_s0_waitrequest : out std_logic; -- .waitrequest
clock_clk : in std_logic := '0'; -- clock.clk
reset_reset : in std_logic := '0'; -- reset.reset
pwm_out : out std_logic_vector(1 downto 0); -- pwm.pwm_signal
pwm_dir : out std_logic_vector(1 downto 0) -- .dir_signal
);
end entity ip_pwm_top;
architecture rtl of ip_pwm_top is
component ip_pwm_out is
port (
reset_n : in STD_LOGIC;
clk : in STD_LOGIC;
pwm_hz : in STD_LOGIC_VECTOR (7 downto 0);
pwm_dir : in STD_LOGIC;
pwm_duty : in STD_LOGIC_VECTOR (7 downto 0);
pwm_pin_duty : out STD_LOGIC;
pwm_pin_dir : out STD_LOGIC
);
end component ip_pwm_out;
signal reg_data_out :std_logic_vector(31 downto 0);
signal slv_reg0 :std_logic_vector(31 downto 0);
signal slv_reg1 :std_logic_vector(31 downto 0);
signal slv_reg2 :std_logic_vector(31 downto 0);
signal slv_reg3 :std_logic_vector(31 downto 0);
begin
-- TODO: Auto-generated HDL template
process (clock_clk, reset_reset)
variable loc_addr :std_logic_vector(7 downto 0);
begin
if rising_edge(clock_clk) then
if reset_reset = '1' then
slv_reg0 <= (others => '0');
slv_reg1 <= (others => '0');
slv_reg2 <= (others => '0');
slv_reg3 <= (others => '0');
else
loc_addr := avs_s0_address(7 downto 0);
if (avs_s0_write = '1') then
case loc_addr is
when x"00" =>
slv_reg0 <= avs_s0_writedata;
when x"01" =>
slv_reg1 <= avs_s0_writedata;
when x"02" =>
slv_reg2 <= avs_s0_writedata;
when x"03" =>
slv_reg3 <= avs_s0_writedata;
when others =>
slv_reg0 <= slv_reg0;
slv_reg1 <= slv_reg1;
slv_reg2 <= slv_reg2;
slv_reg3 <= slv_reg3;
end case;
end if;
end if;
end if;
end process;
process (slv_reg0, slv_reg1, slv_reg2, slv_reg3)
variable loc_addr :std_logic_vector(7 downto 0);
begin
-- Address decoding for reading registers
loc_addr := avs_s0_address;
case loc_addr is
when x"00" =>
reg_data_out <= slv_reg0;
when x"01" =>
reg_data_out <= slv_reg1;
when x"02" =>
reg_data_out <= slv_reg2;
when x"03" =>
reg_data_out <= slv_reg3;
when others =>
reg_data_out <= (others => '0');
end case;
end process;
avs_s0_readdata <= reg_data_out;
avs_s0_waitrequest <= '0';
PWM_0 : ip_pwm_out
port map (
reset_n => not reset_reset,
clk => clock_clk,
pwm_hz => slv_reg0( 7 downto 0 ),
pwm_dir => slv_reg0( 8 ),
pwm_duty => slv_reg1( 7 downto 0 ),
pwm_pin_duty => pwm_out(0),
pwm_pin_dir => pwm_dir(0)
);
PWM_1 : ip_pwm_out
port map (
reset_n => not reset_reset,
clk => clock_clk,
pwm_hz => slv_reg2( 7 downto 0 ),
pwm_dir => slv_reg2( 8 ),
pwm_duty => slv_reg3( 7 downto 0 ),
pwm_pin_duty => pwm_out(1),
pwm_pin_dir => pwm_dir(1)
);
end architecture rtl; -- of new_component
|
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